[PATCH v7 19/22] target/riscv: Adjust vector address with mask

qemu-riscv

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[PATCH v7 19/22] target/riscv: Adjust vector address with mask

From:	LIU Zhiwei
Subject:	[PATCH v7 19/22] target/riscv: Adjust vector address with mask
Date:	Wed, 19 Jan 2022 13:18:21 +0800

The mask comes from the pointer masking extension, or the max value
corresponding to XLEN bits.

Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
 target/riscv/vector_helper.c | 25 +++++++++++++++----------
 1 file changed, 15 insertions(+), 10 deletions(-)

diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index efb3129532..020d2e841f 100644
--- a/target/riscv/vector_helper.c
+++ b/target/riscv/vector_helper.c
@@ -139,6 +139,11 @@ static inline uint32_t vext_max_elems(uint32_t desc, 
uint32_t esz)
     return scale < 0 ? vlenb >> -scale : vlenb << scale;
 }
 
+static inline target_ulong adjust_addr(CPURISCVState *env, target_ulong addr)
+{
+    return (addr & env->cur_pmmask) | env->cur_pmbase;
+}
+
 /*
  * This function checks watchpoint before real load operation.
  *
@@ -156,12 +161,12 @@ static void probe_pages(CPURISCVState *env, target_ulong 
addr,
     target_ulong pagelen = -(addr | TARGET_PAGE_MASK);
     target_ulong curlen = MIN(pagelen, len);
 
-    probe_access(env, addr, curlen, access_type,
+    probe_access(env, adjust_addr(env, addr), curlen, access_type,
                  cpu_mmu_index(env, false), ra);
     if (len > curlen) {
         addr += curlen;
         curlen = len - curlen;
-        probe_access(env, addr, curlen, access_type,
+        probe_access(env, adjust_addr(env, addr), curlen, access_type,
                      cpu_mmu_index(env, false), ra);
     }
 }
@@ -239,7 +244,7 @@ vext_ldst_stride(void *vd, void *v0, target_ulong base,
         k = 0;
         while (k < nf) {
             target_ulong addr = base + stride * i + (k << esz);
-            ldst_elem(env, addr, i + k * max_elems, vd, ra);
+            ldst_elem(env, adjust_addr(env, addr), i + k * max_elems, vd, ra);
             k++;
         }
     }
@@ -295,7 +300,7 @@ vext_ldst_us(void *vd, target_ulong base, CPURISCVState 
*env, uint32_t desc,
         k = 0;
         while (k < nf) {
             target_ulong addr = base + ((i * nf + k) << esz);
-            ldst_elem(env, addr, i + k * max_elems, vd, ra);
+            ldst_elem(env, adjust_addr(env, addr), i + k * max_elems, vd, ra);
             k++;
         }
     }
@@ -409,7 +414,7 @@ vext_ldst_index(void *vd, void *v0, target_ulong base,
         k = 0;
         while (k < nf) {
             abi_ptr addr = get_index_addr(base, i, vs2) + (k << esz);
-            ldst_elem(env, addr, i + k * max_elems, vd, ra);
+            ldst_elem(env, adjust_addr(env, addr), i + k * max_elems, vd, ra);
             k++;
         }
     }
@@ -488,7 +493,7 @@ vext_ldff(void *vd, void *v0, target_ulong base,
         if (!vm && !vext_elem_mask(v0, i)) {
             continue;
         }
-        addr = base + i * (nf << esz);
+        addr = adjust_addr(env, base + i * (nf << esz));
         if (i == 0) {
             probe_pages(env, addr, nf << esz, ra, MMU_DATA_LOAD);
         } else {
@@ -515,7 +520,7 @@ vext_ldff(void *vd, void *v0, target_ulong base,
                     break;
                 }
                 remain -= offset;
-                addr += offset;
+                addr = adjust_addr(env, addr + offset);
             }
         }
     }
@@ -531,7 +536,7 @@ ProbeSuccess:
         }
         while (k < nf) {
             target_ulong addr = base + ((i * nf + k) << esz);
-            ldst_elem(env, addr, i + k * max_elems, vd, ra);
+            ldst_elem(env, adjust_addr(env, addr), i + k * max_elems, vd, ra);
             k++;
         }
     }
@@ -585,7 +590,7 @@ vext_ldst_whole(void *vd, target_ulong base, CPURISCVState 
*env, uint32_t desc,
         /* load/store rest of elements of current segment pointed by vstart */
         for (pos = off; pos < max_elems; pos++, env->vstart++) {
             target_ulong addr = base + ((pos + k * max_elems) << esz);
-            ldst_elem(env, addr, pos + k * max_elems, vd, ra);
+            ldst_elem(env, adjust_addr(env, addr), pos + k * max_elems, vd, 
ra);
         }
         k++;
     }
@@ -594,7 +599,7 @@ vext_ldst_whole(void *vd, target_ulong base, CPURISCVState 
*env, uint32_t desc,
     for (; k < nf; k++) {
         for (i = 0; i < max_elems; i++, env->vstart++) {
             target_ulong addr = base + ((i + k * max_elems) << esz);
-            ldst_elem(env, addr, i + k * max_elems, vd, ra);
+            ldst_elem(env, adjust_addr(env, addr), i + k * max_elems, vd, ra);
         }
     }
 
-- 
2.25.1

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[PATCH v7 09/22] target/riscv: Relax debug check for pm write, (continued)
- [PATCH v7 09/22] target/riscv: Relax debug check for pm write, LIU Zhiwei, 2022/01/19
- [PATCH v7 10/22] target/riscv: Adjust csr write mask with XLEN, LIU Zhiwei, 2022/01/19
- [PATCH v7 11/22] target/riscv: Create current pm fields in env, LIU Zhiwei, 2022/01/19
- [PATCH v7 12/22] target/riscv: Alloc tcg global for cur_pm[mask|base], LIU Zhiwei, 2022/01/19
- [PATCH v7 13/22] target/riscv: Calculate address according to XLEN, LIU Zhiwei, 2022/01/19
- [PATCH v7 14/22] target/riscv: Split pm_enabled into mask and base, LIU Zhiwei, 2022/01/19
- [PATCH v7 15/22] target/riscv: Split out the vill from vtype, LIU Zhiwei, 2022/01/19
- [PATCH v7 16/22] target/riscv: Adjust vsetvl according to XLEN, LIU Zhiwei, 2022/01/19
- [PATCH v7 17/22] target/riscv: Remove VILL field in VTYPE, LIU Zhiwei, 2022/01/19
- [PATCH v7 18/22] target/riscv: Fix check range for first fault only, LIU Zhiwei, 2022/01/19
- [PATCH v7 19/22] target/riscv: Adjust vector address with mask, LIU Zhiwei <=
- [PATCH v7 20/22] target/riscv: Adjust scalar reg in vector with XLEN, LIU Zhiwei, 2022/01/19
- [PATCH v7 21/22] target/riscv: Enable uxl field write, LIU Zhiwei, 2022/01/19
  - Re: [PATCH v7 21/22] target/riscv: Enable uxl field write, Alistair Francis, 2022/01/19
    - Re: [PATCH v7 21/22] target/riscv: Enable uxl field write, LIU Zhiwei, 2022/01/19
    - Re: [PATCH v7 21/22] target/riscv: Enable uxl field write, Alistair Francis, 2022/01/19
    - Re: [PATCH v7 21/22] target/riscv: Enable uxl field write, LIU Zhiwei, 2022/01/20
    - Re: [PATCH v7 21/22] target/riscv: Enable uxl field write, LIU Zhiwei, 2022/01/19
- [PATCH v7 22/22] target/riscv: Relax UXL field for debugging, LIU Zhiwei, 2022/01/19

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