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[PATCH v8 21/23] target/riscv: Set default XLEN for hypervisor
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From: |
LIU Zhiwei |
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Subject: |
[PATCH v8 21/23] target/riscv: Set default XLEN for hypervisor |
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Date: |
Thu, 20 Jan 2022 20:20:48 +0800 |
When swap regs for hypervisor, the value of vsstatus or mstatus_hs
should have the right XLEN. Otherwise, it will propagate to mstatus.
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
---
target/riscv/cpu.c | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index a120d474df..1cb0436187 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -422,6 +422,16 @@ static void riscv_cpu_reset(DeviceState *dev)
*/
env->mstatus = set_field(env->mstatus, MSTATUS64_SXL, env->misa_mxl);
env->mstatus = set_field(env->mstatus, MSTATUS64_UXL, env->misa_mxl);
+ if (riscv_has_ext(env, RVH)) {
+ env->vsstatus = set_field(env->vsstatus,
+ MSTATUS64_SXL, env->misa_mxl);
+ env->vsstatus = set_field(env->vsstatus,
+ MSTATUS64_UXL, env->misa_mxl);
+ env->mstatus_hs = set_field(env->mstatus_hs,
+ MSTATUS64_SXL, env->misa_mxl);
+ env->mstatus_hs = set_field(env->mstatus_hs,
+ MSTATUS64_UXL, env->misa_mxl);
+ }
}
env->mcause = 0;
env->pc = env->resetvec;
--
2.25.1
- [PATCH v8 11/23] target/riscv: Create current pm fields in env, (continued)
- [PATCH v8 11/23] target/riscv: Create current pm fields in env, LIU Zhiwei, 2022/01/20
- [PATCH v8 13/23] target/riscv: Calculate address according to XLEN, LIU Zhiwei, 2022/01/20
- [PATCH v8 14/23] target/riscv: Split pm_enabled into mask and base, LIU Zhiwei, 2022/01/20
- [PATCH v8 15/23] target/riscv: Split out the vill from vtype, LIU Zhiwei, 2022/01/20
- [PATCH v8 16/23] target/riscv: Adjust vsetvl according to XLEN, LIU Zhiwei, 2022/01/20
- [PATCH v8 17/23] target/riscv: Remove VILL field in VTYPE, LIU Zhiwei, 2022/01/20
- [PATCH v8 18/23] target/riscv: Fix check range for first fault only, LIU Zhiwei, 2022/01/20
- [PATCH v8 19/23] target/riscv: Adjust vector address with mask, LIU Zhiwei, 2022/01/20
- [PATCH v8 20/23] target/riscv: Adjust scalar reg in vector with XLEN, LIU Zhiwei, 2022/01/20
- [PATCH v8 22/23] target/riscv: Enable uxl field write, LIU Zhiwei, 2022/01/20
- [PATCH v8 21/23] target/riscv: Set default XLEN for hypervisor,
LIU Zhiwei <=
- [PATCH v8 23/23] target/riscv: Relax UXL field for debugging, LIU Zhiwei, 2022/01/20
- Re: [PATCH v8 00/23] Support UXL filed in xstatus, Alistair Francis, 2022/01/20