Re: [PATCH v4 2/6] target/riscv: hardwire mstatus.FS to zero when enable zfinx

[Alistair Francis]

On Thu, Jan 13, 2022 at 11:52 AM Weiwei Li <liweiwei@iscas.ac.cn> wrote:
>
> Co-authored-by: ardxwe <ardxwe@gmail.com>
> Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
> Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>

Alistair

> ---
>  target/riscv/cpu_helper.c |  6 +++++-
>  target/riscv/csr.c        | 25 ++++++++++++++++++++-----
>  target/riscv/translate.c  |  4 ++++
>  3 files changed, 29 insertions(+), 6 deletions(-)
>
> diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
> index 434a83e66a..3854acf7fe 100644
> --- a/target/riscv/cpu_helper.c
> +++ b/target/riscv/cpu_helper.c
> @@ -222,9 +222,13 @@ bool riscv_cpu_vector_enabled(CPURISCVState *env)
>
>  void riscv_cpu_swap_hypervisor_regs(CPURISCVState *env)
>  {
> -    uint64_t mstatus_mask = MSTATUS_MXR | MSTATUS_SUM | MSTATUS_FS |
> +    uint64_t mstatus_mask = MSTATUS_MXR | MSTATUS_SUM |
>                              MSTATUS_SPP | MSTATUS_SPIE | MSTATUS_SIE |
>                              MSTATUS64_UXL | MSTATUS_VS;
> +
> +    if (riscv_has_ext(env, RVF)) {
> +        mstatus_mask |= MSTATUS_FS;
> +    }
>      bool current_virt = riscv_cpu_virt_enabled(env);
>
>      g_assert(riscv_has_ext(env, RVH));
> diff --git a/target/riscv/csr.c b/target/riscv/csr.c
> index adb3d4381d..f4466cba05 100644
> --- a/target/riscv/csr.c
> +++ b/target/riscv/csr.c
> @@ -38,7 +38,8 @@ void riscv_set_csr_ops(int csrno, riscv_csr_operations *ops)
>  static RISCVException fs(CPURISCVState *env, int csrno)
>  {
>  #if !defined(CONFIG_USER_ONLY)
> -    if (!env->debugger && !riscv_cpu_fp_enabled(env)) {
> +    if (!env->debugger && !riscv_cpu_fp_enabled(env) &&
> +        !RISCV_CPU(env_cpu(env))->cfg.ext_zfinx) {
>          return RISCV_EXCP_ILLEGAL_INST;
>      }
>  #endif
> @@ -234,7 +235,9 @@ static RISCVException write_fflags(CPURISCVState *env, 
> int csrno,
>                                     target_ulong val)
>  {
>  #if !defined(CONFIG_USER_ONLY)
> -    env->mstatus |= MSTATUS_FS;
> +    if (riscv_has_ext(env, RVF)) {
> +        env->mstatus |= MSTATUS_FS;
> +    }
>  #endif
>      riscv_cpu_set_fflags(env, val & (FSR_AEXC >> FSR_AEXC_SHIFT));
>      return RISCV_EXCP_NONE;
> @@ -251,7 +254,9 @@ static RISCVException write_frm(CPURISCVState *env, int 
> csrno,
>                                  target_ulong val)
>  {
>  #if !defined(CONFIG_USER_ONLY)
> -    env->mstatus |= MSTATUS_FS;
> +    if (riscv_has_ext(env, RVF)) {
> +        env->mstatus |= MSTATUS_FS;
> +    }
>  #endif
>      env->frm = val & (FSR_RD >> FSR_RD_SHIFT);
>      return RISCV_EXCP_NONE;
> @@ -269,7 +274,9 @@ static RISCVException write_fcsr(CPURISCVState *env, int 
> csrno,
>                                   target_ulong val)
>  {
>  #if !defined(CONFIG_USER_ONLY)
> -    env->mstatus |= MSTATUS_FS;
> +    if (riscv_has_ext(env, RVF)) {
> +        env->mstatus |= MSTATUS_FS;
> +    }
>  #endif
>      env->frm = (val & FSR_RD) >> FSR_RD_SHIFT;
>      riscv_cpu_set_fflags(env, (val & FSR_AEXC) >> FSR_AEXC_SHIFT);
> @@ -564,10 +571,14 @@ static RISCVException write_mstatus(CPURISCVState *env, 
> int csrno,
>          tlb_flush(env_cpu(env));
>      }
>      mask = MSTATUS_SIE | MSTATUS_SPIE | MSTATUS_MIE | MSTATUS_MPIE |
> -        MSTATUS_SPP | MSTATUS_FS | MSTATUS_MPRV | MSTATUS_SUM |
> +        MSTATUS_SPP | MSTATUS_MPRV | MSTATUS_SUM |
>          MSTATUS_MPP | MSTATUS_MXR | MSTATUS_TVM | MSTATUS_TSR |
>          MSTATUS_TW | MSTATUS_VS;
>
> +    if (riscv_has_ext(env, RVF)) {
> +        mask |= MSTATUS_FS;
> +    }
> +
>      if (riscv_cpu_mxl(env) != MXL_RV32) {
>          /*
>           * RV32: MPV and GVA are not in mstatus. The current plan is to
> @@ -697,6 +708,10 @@ static RISCVException write_misa(CPURISCVState *env, int 
> csrno,
>          return RISCV_EXCP_NONE;
>      }
>
> +    if (!(val & RVF)) {
> +        env->mstatus &= ~MSTATUS_FS;
> +    }
> +
>      /* flush translation cache */
>      tb_flush(env_cpu(env));
>      env->misa_ext = val;
> diff --git a/target/riscv/translate.c b/target/riscv/translate.c
> index 9687fa3e7c..8f01063618 100644
> --- a/target/riscv/translate.c
> +++ b/target/riscv/translate.c
> @@ -406,6 +406,10 @@ static void mark_fs_dirty(DisasContext *ctx)
>  {
>      TCGv tmp;
>
> +    if (!has_ext(ctx, RVF)) {
> +        return;
> +    }
> +
>      if (ctx->mstatus_fs != MSTATUS_FS) {
>          /* Remember the state change for the rest of the TB. */
>          ctx->mstatus_fs = MSTATUS_FS;
> --
> 2.17.1
>
>