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[PATCH v5 1/6] target/riscv: add cfg properties for zfinx, zdinx and zhi
From: |
Weiwei Li |
Subject: |
[PATCH v5 1/6] target/riscv: add cfg properties for zfinx, zdinx and zhinx{min} |
Date: |
Fri, 28 Jan 2022 21:16:38 +0800 |
Co-authored-by: ardxwe <ardxwe@gmail.com>
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu.c | 12 ++++++++++++
target/riscv/cpu.h | 4 ++++
target/riscv/translate.c | 8 ++++++++
3 files changed, 24 insertions(+)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 1cb0436187..7006e6647b 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -569,6 +569,11 @@ static void riscv_cpu_realize(DeviceState *dev, Error
**errp)
cpu->cfg.ext_d = true;
}
+ if (cpu->cfg.ext_zdinx || cpu->cfg.ext_zhinx ||
+ cpu->cfg.ext_zhinxmin) {
+ cpu->cfg.ext_zfinx = true;
+ }
+
/* Set the ISA extensions, checks should have happened above */
if (cpu->cfg.ext_i) {
ext |= RVI;
@@ -647,6 +652,13 @@ static void riscv_cpu_realize(DeviceState *dev, Error
**errp)
if (cpu->cfg.ext_j) {
ext |= RVJ;
}
+ if (cpu->cfg.ext_zfinx && ((ext & (RVF | RVD)) || cpu->cfg.ext_zfh ||
+ cpu->cfg.ext_zfhmin)) {
+ error_setg(errp,
+ "'Zfinx' cannot be supported together with 'F', 'D',
'Zfh',"
+ " 'Zfhmin'");
+ return;
+ }
set_misa(env, env->misa_mxl, ext);
}
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 55635d68d5..be46840541 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -341,8 +341,12 @@ struct RISCVCPU {
bool ext_counters;
bool ext_ifencei;
bool ext_icsr;
+ bool ext_zdinx;
bool ext_zfh;
bool ext_zfhmin;
+ bool ext_zfinx;
+ bool ext_zhinx;
+ bool ext_zhinxmin;
bool ext_zve32f;
bool ext_zve64f;
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index f0bbe80875..1484586fe7 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -77,8 +77,12 @@ typedef struct DisasContext {
RISCVMXL ol;
bool virt_enabled;
bool ext_ifencei;
+ bool ext_zdinx;
bool ext_zfh;
bool ext_zfhmin;
+ bool ext_zfinx;
+ bool ext_zhinx;
+ bool ext_zhinxmin;
bool ext_zve32f;
bool ext_zve64f;
bool hlsx;
@@ -909,8 +913,12 @@ static void riscv_tr_init_disas_context(DisasContextBase
*dcbase, CPUState *cs)
ctx->misa_ext = env->misa_ext;
ctx->frm = -1; /* unknown rounding mode */
ctx->ext_ifencei = cpu->cfg.ext_ifencei;
+ ctx->ext_zdinx = cpu->cfg.ext_zdinx;
ctx->ext_zfh = cpu->cfg.ext_zfh;
ctx->ext_zfhmin = cpu->cfg.ext_zfhmin;
+ ctx->ext_zfinx = cpu->cfg.ext_zfinx;
+ ctx->ext_zhinx = cpu->cfg.ext_zhinx;
+ ctx->ext_zhinxmin = cpu->cfg.ext_zhinxmin;
ctx->ext_zve32f = cpu->cfg.ext_zve32f;
ctx->ext_zve64f = cpu->cfg.ext_zve64f;
ctx->vlen = cpu->cfg.vlen;
--
2.17.1
- [PATCH v5 0/6] support subsets of Float-Point in Integer Registers extensions, Weiwei Li, 2022/01/28
- [PATCH v5 6/6] target/riscv: expose zfinx, zdinx, zhinx{min} properties, Weiwei Li, 2022/01/28
- [PATCH v5 5/6] target/riscv: add support for zhinx/zhinxmin, Weiwei Li, 2022/01/28
- [PATCH v5 2/6] target/riscv: hardwire mstatus.FS to zero when enable zfinx, Weiwei Li, 2022/01/28
- [PATCH v5 1/6] target/riscv: add cfg properties for zfinx, zdinx and zhinx{min},
Weiwei Li <=
- [PATCH v5 4/6] target/riscv: add support for zdinx, Weiwei Li, 2022/01/28
- [PATCH v5 3/6] target/riscv: add support for zfinx, Weiwei Li, 2022/01/28