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Re: [PATCH v7 2/5] target/riscv: add PTE_A/PTE_D/PTE_U bits check for in
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From: |
Alistair Francis |
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Subject: |
Re: [PATCH v7 2/5] target/riscv: add PTE_A/PTE_D/PTE_U bits check for inner PTE |
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Date: |
Tue, 1 Feb 2022 13:34:51 +1000 |
On Fri, Jan 28, 2022 at 7:06 PM Weiwei Li <liweiwei@iscas.ac.cn> wrote:
>
> For non-leaf PTEs, the D, A, and U bits are reserved for future standard use.
>
> Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
> Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
> Reviewed-by: Anup Patel <anup@brainfault.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> target/riscv/cpu_helper.c | 3 +++
> 1 file changed, 3 insertions(+)
>
> diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
> index 5a1c0e239e..b820166dc5 100644
> --- a/target/riscv/cpu_helper.c
> +++ b/target/riscv/cpu_helper.c
> @@ -641,6 +641,9 @@ restart:
> return TRANSLATE_FAIL;
> } else if (!(pte & (PTE_R | PTE_W | PTE_X))) {
> /* Inner PTE, continue walking */
> + if (pte & (PTE_D | PTE_A | PTE_U)) {
> + return TRANSLATE_FAIL;
> + }
> base = ppn << PGSHIFT;
> } else if ((pte & (PTE_R | PTE_W | PTE_X)) == PTE_W) {
> /* Reserved leaf PTE flags: PTE_W */
> --
> 2.17.1
>
>
- [PATCH v7 0/5] support subsets of virtual memory extension, Weiwei Li, 2022/01/28
- [PATCH v7 2/5] target/riscv: add PTE_A/PTE_D/PTE_U bits check for inner PTE, Weiwei Li, 2022/01/28
- Re: [PATCH v7 2/5] target/riscv: add PTE_A/PTE_D/PTE_U bits check for inner PTE,
Alistair Francis <=
- [PATCH v7 1/5] target/riscv: Ignore reserved bits in PTE for RV64, Weiwei Li, 2022/01/28
- [PATCH v7 3/5] target/riscv: add support for svnapot extension, Weiwei Li, 2022/01/28
- [PATCH v7 5/5] target/riscv: add support for svpbmt extension, Weiwei Li, 2022/01/28
- [PATCH v7 4/5] target/riscv: add support for svinval extension, Weiwei Li, 2022/01/28