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Re: [PATCH v9 0/5] support subsets of virtual memory extension


From: Alistair Francis
Subject: Re: [PATCH v9 0/5] support subsets of virtual memory extension
Date: Thu, 10 Feb 2022 13:07:13 +1000

On Fri, Feb 4, 2022 at 12:32 PM Weiwei Li <liweiwei@iscas.ac.cn> wrote:
>
> This patchset implements virtual memory related RISC-V extensions: Svnapot 
> version 1.0, Svinval vesion 1.0, Svpbmt version 1.0.
>
> Specification:
> https://github.com/riscv/virtual-memory/tree/main/specs
>
> The port is available here:
> https://github.com/plctlab/plct-qemu/tree/plct-virtmem-upstream-v9
>
> To test this implementation, specify cpu argument with 
> 'svinval=true,svnapot=true,svpbmt=true'.
>
> This implementation can pass the riscv-tests for rv64ssvnapot.
>
> v9:
> * delete cast for PTE bits check
>
> v8:
> * rebase on 
> https://lore.kernel.org/qemu-devel/20220131110201.2303275-1-philipp.tomsich@vrull.eu/
> * move variables to tops of function
> * add ULL for PTE_N and PTE_PMBT
> * add mask variable for napot_bits
>
> v7:
> * delete definition of PTE_PPN_MASK for TARGET_RISCV32
> * make riscv_cpu_sxl works for user mode
> * add commit msg for patch 2
>
> v6:
> * select ppn mask base on sxl
>
> v5:
> * merge patch 
> https://lore.kernel.org/qemu-devel/1569456861-8502-1-git-send-email-guoren@kernel.org/
> * relax pte attribute check
>
> v4:
> * fix encodings for hinval_vvma and hinval_gvma
> * partition inner PTE check into several steps
> * improve commit messages to describe changes
>
> v3:
> * drop "x-" in exposed properties
>
> v2:
> * add extension check for svnapot and svpbmt
>
> Guo Ren (1):
>   target/riscv: Ignore reserved bits in PTE for RV64
>
> Weiwei Li (4):
>   target/riscv: add PTE_A/PTE_D/PTE_U bits check for inner PTE
>   target/riscv: add support for svnapot extension
>   target/riscv: add support for svinval extension
>   target/riscv: add support for svpbmt extension

Thanks!

Applied to riscv-to-apply.next

Alistair

>
>  target/riscv/cpu.c                          |  4 ++
>  target/riscv/cpu.h                          | 16 +++++
>  target/riscv/cpu_bits.h                     |  6 ++
>  target/riscv/cpu_helper.c                   | 34 +++++++++-
>  target/riscv/insn32.decode                  |  7 ++
>  target/riscv/insn_trans/trans_svinval.c.inc | 75 +++++++++++++++++++++
>  target/riscv/translate.c                    |  1 +
>  7 files changed, 140 insertions(+), 3 deletions(-)
>  create mode 100644 target/riscv/insn_trans/trans_svinval.c.inc
>
> --
> 2.17.1
>
>



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