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Re: [PATCH v3 4/6] target/riscv: Add support for mconfigptr


From: Alistair Francis
Subject: Re: [PATCH v3 4/6] target/riscv: Add support for mconfigptr
Date: Tue, 22 Feb 2022 07:41:47 +1000

On Sun, Feb 6, 2022 at 7:43 PM Atish Patra <atishp@rivosinc.com> wrote:
>
> RISC-V privileged specification v1.12 introduced a mconfigptr
> which will hold the physical address of a configuration data
> structure. As Qemu doesn't have a configuration data structure,
> is read as zero which is valid as per the priv spec.
>
> Signed-off-by: Atish Patra <atishp@rivosinc.com>

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>

Alistair

> ---
>  target/riscv/cpu_bits.h | 1 +
>  target/riscv/csr.c      | 2 ++
>  2 files changed, 3 insertions(+)
>
> diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
> index f96d26399607..89440241632a 100644
> --- a/target/riscv/cpu_bits.h
> +++ b/target/riscv/cpu_bits.h
> @@ -148,6 +148,7 @@
>  #define CSR_MARCHID         0xf12
>  #define CSR_MIMPID          0xf13
>  #define CSR_MHARTID         0xf14
> +#define CSR_MCONFIGPTR      0xf15
>
>  /* Machine Trap Setup */
>  #define CSR_MSTATUS         0x300
> diff --git a/target/riscv/csr.c b/target/riscv/csr.c
> index 25a0df498669..18fe17b62f51 100644
> --- a/target/riscv/csr.c
> +++ b/target/riscv/csr.c
> @@ -3021,6 +3021,8 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
>      [CSR_MIMPID]    = { "mimpid",    any,   read_zero    },
>      [CSR_MHARTID]   = { "mhartid",   any,   read_mhartid },
>
> +    [CSR_MCONFIGPTR]  = { "mconfigptr", any,   read_zero,
> +                                        .min_priv_ver = PRIV_VERSION_1_12_0 
> },
>      /* Machine Trap Setup */
>      [CSR_MSTATUS]     = { "mstatus",    any,   read_mstatus,     
> write_mstatus, NULL,
>                                                 read_mstatus_i128             
>       },
> --
> 2.30.2
>
>



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