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Re: [PATCH v4 14/14] hw: set user_creatable on opentitan/sifive_e device

From: Philippe Mathieu-Daudé
Subject: Re: [PATCH v4 14/14] hw: set user_creatable on opentitan/sifive_e devices
Date: Fri, 4 Mar 2022 13:58:36 +0100
User-agent: Mozilla/5.0 (Macintosh; Intel Mac OS X 10.15; rv:91.0) Gecko/20100101 Thunderbird/91.6.1

On 23/2/22 10:07, Damien Hedde wrote:
The devices are:
+ ibex-timer
+ ibex-uart
+ riscv.aclint.swi
+ riscv.aclint.mtimer
+ riscv.hart_array
+ riscv.sifive.e.prci
+ riscv.sifive.plic
+ riscv.sifive.uart
+ sifive_soc.gpio
+ unimplemented-device

These devices are clean regarding error handling in realize.

They are all sysbus devices, so setting user-creatable will only
enable cold-plugging them on machine having explicitely allowed them
(only _none_ machine does that).

Note that this commit include the ricv_array which embeds cpus. There

Typo "includes" I guess.

Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>

are some deep internal constraints about them: you cannot create more
cpus than the machine's maxcpus. TCG accelerator's code will for example
assert if a user try to create too many cpus.

Signed-off-by: Damien Hedde <damien.hedde@greensocs.com>

I can also split this patch if you think it's better.
But it is mostly a one-line fix per file.

This patch requires first some cleanups in order to fix error errors
and some more memory leaks that could happend in legit user-related
life cycles: a miss-configuration should not be a fatal error anymore.
  hw/char/ibex_uart.c     | 1 +
  hw/char/sifive_uart.c   | 1 +
  hw/gpio/sifive_gpio.c   | 1 +
  hw/intc/riscv_aclint.c  | 2 ++
  hw/intc/sifive_plic.c   | 1 +
  hw/misc/sifive_e_prci.c | 8 ++++++++
  hw/misc/unimp.c         | 1 +
  hw/riscv/riscv_hart.c   | 1 +
  hw/timer/ibex_timer.c   | 1 +
  9 files changed, 17 insertions(+)

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