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[PATCH qemu 06/13] target/riscv: rvv: Add tail agnostic for vector integ
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From: |
~eopxd |
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Subject: |
[PATCH qemu 06/13] target/riscv: rvv: Add tail agnostic for vector integer shift instructions |
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Date: |
Mon, 07 Mar 2022 01:38:18 -0800 |
From: eopXD <eop.chen@sifive.com>
Signed-off-by: eop Chen <eop.chen@sifive.com>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
---
target/riscv/insn_trans/trans_rvv.c.inc | 1 +
target/riscv/vector_helper.c | 12 ++++++++++++
2 files changed, 13 insertions(+)
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc
b/target/riscv/insn_trans/trans_rvv.c.inc
index ac6379a8fc..f1838fbf11 100644
--- a/target/riscv/insn_trans/trans_rvv.c.inc
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
@@ -1871,6 +1871,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a)
\
\
data = FIELD_DP32(data, VDATA, VM, a->vm); \
data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \
+ data = FIELD_DP32(data, VDATA, VTA, s->vta); \
tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \
vreg_ofs(s, a->rs1), \
vreg_ofs(s, a->rs2), cpu_env, \
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index 56a32adcb9..6d79908ffe 100644
--- a/target/riscv/vector_helper.c
+++ b/target/riscv/vector_helper.c
@@ -1216,6 +1216,9 @@ void HELPER(NAME)(void *vd, void *v0, void *vs1,
\
{ \
uint32_t vm = vext_vm(desc); \
uint32_t vl = env->vl; \
+ uint32_t esz = sizeof(TS1); \
+ uint32_t vlmax = vext_get_vlmax(env_archcpu(env), env->vtype); \
+ uint32_t vta = vext_vta(desc); \
uint32_t i; \
\
for (i = env->vstart; i < vl; i++) { \
@@ -1227,6 +1230,8 @@ void HELPER(NAME)(void *vd, void *v0, void *vs1,
\
*((TS1 *)vd + HS1(i)) = OP(s2, s1 & MASK); \
} \
env->vstart = 0; \
+ /* set tail elements to 1s */ \
+ vext_set_elems_1s_fns[ctzl(esz)](vd, vta, vl, vl * esz, vlmax * esz); \
}
GEN_VEXT_SHIFT_VV(vsll_vv_b, uint8_t, uint8_t, H1, H1, DO_SLL, 0x7)
@@ -1251,6 +1256,10 @@ void HELPER(NAME)(void *vd, void *v0, target_ulong s1,
\
{ \
uint32_t vm = vext_vm(desc); \
uint32_t vl = env->vl; \
+ uint32_t esz = sizeof(TD); \
+ uint32_t vlmax = \
+ vext_get_vlmax(env_archcpu(env), env->vtype); \
+ uint32_t vta = vext_vta(desc); \
uint32_t i; \
\
for (i = env->vstart; i < vl; i++) { \
@@ -1261,6 +1270,9 @@ void HELPER(NAME)(void *vd, void *v0, target_ulong s1,
\
*((TD *)vd + HD(i)) = OP(s2, s1 & MASK); \
} \
env->vstart = 0; \
+ /* set tail elements to 1s */ \
+ vext_set_elems_1s_fns[ctzl(esz)](vd, vta, vl, vl * esz, \
+ vlmax * esz); \
}
GEN_VEXT_SHIFT_VX(vsll_vx_b, uint8_t, int8_t, H1, H1, DO_SLL, 0x7)
--
2.34.1
- Re: [PATCH qemu 03/13] target/riscv: rvv: Early exit when vstart >= vl, (continued)
- [PATCH qemu 01/13] target/riscv: rvv: Prune redundant ESZ, DSZ parameter passed, ~eopxd, 2022/03/19
- [PATCH qemu 04/13] target/riscv: rvv: Add tail agnostic for vv instructions, ~eopxd, 2022/03/19
- [PATCH qemu 05/13] target/riscv: rvv: Add tail agnostic for vx, vvm, vxm instructions, ~eopxd, 2022/03/19
- [PATCH qemu 07/13] target/riscv: rvv: Add tail agnostic for vector integer comparison instructions, ~eopxd, 2022/03/19
- [PATCH qemu 06/13] target/riscv: rvv: Add tail agnostic for vector integer shift instructions,
~eopxd <=
- [PATCH qemu 10/13] target/riscv: rvv: Add tail agnostic for vector floating-point instructions, ~eopxd, 2022/03/19
- [PATCH qemu 02/13] target/riscv: rvv: Rename ambiguous esz, ~eopxd, 2022/03/19
- [PATCH qemu 08/13] target/riscv: rvv: Add tail agnostic for vector integer merge and move instructions, ~eopxd, 2022/03/19
- [PATCH qemu 11/13] target/riscv: rvv: Add tail agnostic for vector reduction instructions, ~eopxd, 2022/03/19
- [PATCH qemu 12/13] target/riscv: rvv: Add tail agnostic for vector mask instructions, ~eopxd, 2022/03/19
- [PATCH qemu 13/13] target/riscv: rvv: Add tail agnostic for vector permutation instructions, ~eopxd, 2022/03/19
- [PATCH qemu 09/13] target/riscv: rvv: Add tail agnostic for vector fix-point arithmetic instructions, ~eopxd, 2022/03/19
- Re: [PATCH qemu 00/13] Add tail agnostic behavior for rvv instructions, Weiwei Li, 2022/03/19
- Re: [PATCH qemu 00/13] Add tail agnostic behavior for rvv instructions, eop Chen, 2022/03/21