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[PATCH (PING) 0/1] target/riscv: misa to ISA string conversion fix

From: Tsukasa OI
Subject: [PATCH (PING) 0/1] target/riscv: misa to ISA string conversion fix
Date: Sat, 26 Mar 2022 14:01:44 +0900

[This is the same patch as previous ones]
 (qemu-riscv only)
 (resent due to configuration error of my mail server; qemu-riscv only)

I hope this is applied before the QEMU 7.0 release.

Signed-off-by: Tsukasa OI <research_trasio@irq.a4lg.com>
Reviewed-by: Frank Chang <frank.chang@sifive.com>

S and U are misa bits but not extensions (instead, they are supported
privilege modes).  Thus, they should not be copied to the ISA string.

I am truly surprised that this patchset is the THIRD attempt to fix this
longstanding problem.

(1) August 2019: by Palmer Dabbelt

(2) April 2021: by Emmanuel Blot

(3) February 2022: by me (this patchset)

I feel this is urgent to eliminate this bug now considering it required
a workaround to RISC-V Linux kernel as I pointed out:

Though my patchset is first developed independently, this submitted
version is influenced by (2) Emmanuel Blot's patchset.  Thanks to this,
constant "[n]" can now be variable "[]".

It also fixes an ordering issue where 'C' should be preceded by 'L'
(order: 'L' -> 'C') as per the RISC-V ISA Manual (version 20191213),
Table 27.1.

It clarifies the role of `riscv_exts'.  It's a single-letter extrension
ordering list.

Tsukasa OI (1):
  target/riscv: misa to ISA string conversion fix

 target/riscv/cpu.c | 10 +++++-----
 1 file changed, 5 insertions(+), 5 deletions(-)

base-commit: f345abe36527a8b575482bb5a0616f43952bf1f4

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