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[PATCH v5 4/6] target/riscv: machine: Add debug state description
From: |
Bin Meng |
Subject: |
[PATCH v5 4/6] target/riscv: machine: Add debug state description |
Date: |
Thu, 21 Apr 2022 08:33:22 +0800 |
From: Bin Meng <bin.meng@windriver.com>
Add a subsection to machine.c to migrate debug CSR state.
Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
---
(no changes since v2)
Changes in v2:
- new patch: add debug state description
target/riscv/machine.c | 32 ++++++++++++++++++++++++++++++++
1 file changed, 32 insertions(+)
diff --git a/target/riscv/machine.c b/target/riscv/machine.c
index 243f567949..2a437b29a1 100644
--- a/target/riscv/machine.c
+++ b/target/riscv/machine.c
@@ -216,7 +216,38 @@ static const VMStateDescription vmstate_kvmtimer = {
VMSTATE_UINT64(env.kvm_timer_time, RISCVCPU),
VMSTATE_UINT64(env.kvm_timer_compare, RISCVCPU),
VMSTATE_UINT64(env.kvm_timer_state, RISCVCPU),
+ VMSTATE_END_OF_LIST()
+ }
+};
+
+static bool debug_needed(void *opaque)
+{
+ RISCVCPU *cpu = opaque;
+ CPURISCVState *env = &cpu->env;
+
+ return riscv_feature(env, RISCV_FEATURE_DEBUG);
+}
+static const VMStateDescription vmstate_debug_type2 = {
+ .name = "cpu/debug/type2",
+ .version_id = 1,
+ .minimum_version_id = 1,
+ .fields = (VMStateField[]) {
+ VMSTATE_UINTTL(mcontrol, type2_trigger_t),
+ VMSTATE_UINTTL(maddress, type2_trigger_t),
+ VMSTATE_END_OF_LIST()
+ }
+};
+
+static const VMStateDescription vmstate_debug = {
+ .name = "cpu/debug",
+ .version_id = 1,
+ .minimum_version_id = 1,
+ .needed = debug_needed,
+ .fields = (VMStateField[]) {
+ VMSTATE_UINTTL(env.trigger_cur, RISCVCPU),
+ VMSTATE_STRUCT_ARRAY(env.type2_trig, RISCVCPU, TRIGGER_TYPE2_NUM,
+ 0, vmstate_debug_type2, type2_trigger_t),
VMSTATE_END_OF_LIST()
}
};
@@ -315,6 +346,7 @@ const VMStateDescription vmstate_riscv_cpu = {
&vmstate_rv128,
&vmstate_kvmtimer,
&vmstate_envcfg,
+ &vmstate_debug,
NULL
}
};
--
2.25.1
- [PATCH v5 0/6] target/riscv: Initial support for the Sdtrig extension via M-mode CSRs, Bin Meng, 2022/04/20
- [PATCH v5 1/6] target/riscv: debug: Implement debug related TCGCPUOps, Bin Meng, 2022/04/20
- [PATCH v5 2/6] target/riscv: cpu: Add a config option for native debug, Bin Meng, 2022/04/20
- [PATCH v5 3/6] target/riscv: csr: Hook debug CSR read/write, Bin Meng, 2022/04/20
- [PATCH v5 4/6] target/riscv: machine: Add debug state description,
Bin Meng <=
- [PATCH v5 5/6] target/riscv: cpu: Enable native debug feature, Bin Meng, 2022/04/20
- [PATCH v5 6/6] hw/core: tcg-cpu-ops.h: Update comments of debug_check_watchpoint(), Bin Meng, 2022/04/20
- Re: [PATCH v5 0/6] target/riscv: Initial support for the Sdtrig extension via M-mode CSRs, Alistair Francis, 2022/04/20