[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[PATCH qemu 6/9] target/riscv: rvv: Add mask agnostic for vector fix-poi
From: |
~eopxd |
Subject: |
[PATCH qemu 6/9] target/riscv: rvv: Add mask agnostic for vector fix-point arithmetic instructions |
Date: |
Mon, 25 Apr 2022 14:18:47 -0000 |
From: Yueh-Ting (eop) Chen <eop.chen@sifive.com>
Signed-off-by: eop Chen <eop.chen@sifive.com>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
---
target/riscv/vector_helper.c | 26 ++++++++++++++++----------
1 file changed, 16 insertions(+), 10 deletions(-)
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index 2b341d6679..e266a8673c 100644
--- a/target/riscv/vector_helper.c
+++ b/target/riscv/vector_helper.c
@@ -2129,10 +2129,12 @@ static inline void
vext_vv_rm_1(void *vd, void *v0, void *vs1, void *vs2,
CPURISCVState *env,
uint32_t vl, uint32_t vm, int vxrm,
- opivv2_rm_fn *fn)
+ opivv2_rm_fn *fn, uint32_t vma, uint32_t esz)
{
for (uint32_t i = env->vstart; i < vl; i++) {
if (!vm && !vext_elem_mask(v0, i)) {
+ /* set masked-off elements to 1s */
+ vext_set_elems_1s_fns[ctzl(esz)](vd, vma, i, i * esz, (i + 1) *
esz);
continue;
}
fn(vd, vs1, vs2, i, env, vxrm);
@@ -2150,23 +2152,24 @@ vext_vv_rm_2(void *vd, void *v0, void *vs1, void *vs2,
uint32_t vl = env->vl;
uint32_t total_elems = vext_get_total_elems(desc, esz);
uint32_t vta = vext_vta(desc);
+ uint32_t vma = vext_vma(desc);
switch (env->vxrm) {
case 0: /* rnu */
vext_vv_rm_1(vd, v0, vs1, vs2,
- env, vl, vm, 0, fn);
+ env, vl, vm, 0, fn, vma, esz);
break;
case 1: /* rne */
vext_vv_rm_1(vd, v0, vs1, vs2,
- env, vl, vm, 1, fn);
+ env, vl, vm, 1, fn, vma, esz);
break;
case 2: /* rdn */
vext_vv_rm_1(vd, v0, vs1, vs2,
- env, vl, vm, 2, fn);
+ env, vl, vm, 2, fn, vma, esz);
break;
default: /* rod */
vext_vv_rm_1(vd, v0, vs1, vs2,
- env, vl, vm, 3, fn);
+ env, vl, vm, 3, fn, vma, esz);
break;
}
/* set tail elements to 1s */
@@ -2250,10 +2253,12 @@ static inline void
vext_vx_rm_1(void *vd, void *v0, target_long s1, void *vs2,
CPURISCVState *env,
uint32_t vl, uint32_t vm, int vxrm,
- opivx2_rm_fn *fn)
+ opivx2_rm_fn *fn, uint32_t vma, uint32_t esz)
{
for (uint32_t i = env->vstart; i < vl; i++) {
if (!vm && !vext_elem_mask(v0, i)) {
+ /* set masked-off elements to 1s */
+ vext_set_elems_1s_fns[ctzl(esz)](vd, vma, i, i * esz, (i + 1) *
esz);
continue;
}
fn(vd, s1, vs2, i, env, vxrm);
@@ -2271,23 +2276,24 @@ vext_vx_rm_2(void *vd, void *v0, target_long s1, void
*vs2,
uint32_t vl = env->vl;
uint32_t total_elems = vext_get_total_elems(desc, esz);
uint32_t vta = vext_vta(desc);
+ uint32_t vma = vext_vma(desc);
switch (env->vxrm) {
case 0: /* rnu */
vext_vx_rm_1(vd, v0, s1, vs2,
- env, vl, vm, 0, fn);
+ env, vl, vm, 0, fn, vma, esz);
break;
case 1: /* rne */
vext_vx_rm_1(vd, v0, s1, vs2,
- env, vl, vm, 1, fn);
+ env, vl, vm, 1, fn, vma, esz);
break;
case 2: /* rdn */
vext_vx_rm_1(vd, v0, s1, vs2,
- env, vl, vm, 2, fn);
+ env, vl, vm, 2, fn, vma, esz);
break;
default: /* rod */
vext_vx_rm_1(vd, v0, s1, vs2,
- env, vl, vm, 3, fn);
+ env, vl, vm, 3, fn, vma, esz);
break;
}
/* set tail elements to 1s */
--
2.34.2
- Re: [PATCH qemu 1/9] target/riscv: rvv: Add mask agnostic for vv instructions, (continued)
[PATCH qemu 5/9] target/riscv: rvv: Add mask agnostic for vector integer comparison instructions, ~eopxd, 2022/04/25
[PATCH qemu 9/9] target/riscv: rvv: Add mask agnostic for vector permutation instructions, ~eopxd, 2022/04/25
[PATCH qemu 2/9] target/riscv: rvv: Add mask agnostic for vector load / store instructions, ~eopxd, 2022/04/25
[PATCH qemu 4/9] target/riscv: rvv: Add mask agnostic for vector integer shift instructions, ~eopxd, 2022/04/25
[PATCH qemu 8/9] target/riscv: rvv: Add mask agnostic for vector mask instructions, ~eopxd, 2022/04/25
[PATCH qemu 7/9] target/riscv: rvv: Add mask agnostic for vector floating-point instructions, ~eopxd, 2022/04/25
[PATCH qemu 6/9] target/riscv: rvv: Add mask agnostic for vector fix-point arithmetic instructions,
~eopxd <=