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Re: Modelling core local interrupts

From: Frank Chang
Subject: Re: Modelling core local interrupts
Date: Tue, 3 May 2022 23:48:03 +0800

On Fri, Apr 22, 2022 at 8:41 AM vysakh pillai <vysakhpillai@gmail.com> wrote:
I am looking for some reference code that will let me hook up a peripheral to the core local interrupt controller. I want to avoid going through the PLIC for modeling some simpler peripherals that directly interrupt the CPU. 

The polar fire SoC datasheet says " 48 interrupts from peripherals are directly connected as Local interrupts to each processor core". But the mpsoc machine model seems to be configuring everything via the PLIC. I also could not find peripherals being connected to the CLIC in any other machine model. 

Is the CLIC currently not modelled in RISC-V QEMU? OR, does the PLIC model behave similarly to CLIC in the current model?

Vysakh P Pillai

For CLIC, there was a RFC patchet modeling RISC-V CLIC v0.9:

I'm not sure whether the author has any plan to upstream the newer version of the patchset.

Frank Chang 

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