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[PATCH qemu v19 02/16] target/riscv: rvv: Prune redundant access_type pa
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From: |
~eopxd |
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Subject: |
[PATCH qemu v19 02/16] target/riscv: rvv: Prune redundant access_type parameter passed |
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Date: |
Mon, 06 Jun 2022 06:16:18 -0000 |
From: eopXD <yueh.ting.chen@gmail.com>
No functional change intended in this commit.
Signed-off-by: eop Chen <eop.chen@sifive.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/vector_helper.c | 35 ++++++++++++++++-------------------
1 file changed, 16 insertions(+), 19 deletions(-)
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index 85dd611cd9..60840325c4 100644
--- a/target/riscv/vector_helper.c
+++ b/target/riscv/vector_helper.c
@@ -231,7 +231,7 @@ vext_ldst_stride(void *vd, void *v0, target_ulong base,
target_ulong stride, CPURISCVState *env,
uint32_t desc, uint32_t vm,
vext_ldst_elem_fn *ldst_elem,
- uint32_t esz, uintptr_t ra, MMUAccessType access_type)
+ uint32_t esz, uintptr_t ra)
{
uint32_t i, k;
uint32_t nf = vext_nf(desc);
@@ -259,7 +259,7 @@ void HELPER(NAME)(void *vd, void * v0, target_ulong base,
\
{ \
uint32_t vm = vext_vm(desc); \
vext_ldst_stride(vd, v0, base, stride, env, desc, vm, LOAD_FN, \
- ctzl(sizeof(ETYPE)), GETPC(), MMU_DATA_LOAD); \
+ ctzl(sizeof(ETYPE)), GETPC()); \
}
GEN_VEXT_LD_STRIDE(vlse8_v, int8_t, lde_b)
@@ -274,7 +274,7 @@ void HELPER(NAME)(void *vd, void *v0, target_ulong base,
\
{ \
uint32_t vm = vext_vm(desc); \
vext_ldst_stride(vd, v0, base, stride, env, desc, vm, STORE_FN, \
- ctzl(sizeof(ETYPE)), GETPC(), MMU_DATA_STORE); \
+ ctzl(sizeof(ETYPE)), GETPC()); \
}
GEN_VEXT_ST_STRIDE(vsse8_v, int8_t, ste_b)
@@ -290,7 +290,7 @@ GEN_VEXT_ST_STRIDE(vsse64_v, int64_t, ste_d)
static void
vext_ldst_us(void *vd, target_ulong base, CPURISCVState *env, uint32_t desc,
vext_ldst_elem_fn *ldst_elem, uint32_t esz, uint32_t evl,
- uintptr_t ra, MMUAccessType access_type)
+ uintptr_t ra)
{
uint32_t i, k;
uint32_t nf = vext_nf(desc);
@@ -319,14 +319,14 @@ void HELPER(NAME##_mask)(void *vd, void *v0, target_ulong
base, \
{ \
uint32_t stride = vext_nf(desc) << ctzl(sizeof(ETYPE)); \
vext_ldst_stride(vd, v0, base, stride, env, desc, false, LOAD_FN, \
- ctzl(sizeof(ETYPE)), GETPC(), MMU_DATA_LOAD); \
+ ctzl(sizeof(ETYPE)), GETPC()); \
} \
\
void HELPER(NAME)(void *vd, void *v0, target_ulong base, \
CPURISCVState *env, uint32_t desc) \
{ \
vext_ldst_us(vd, base, env, desc, LOAD_FN, \
- ctzl(sizeof(ETYPE)), env->vl, GETPC(), MMU_DATA_LOAD); \
+ ctzl(sizeof(ETYPE)), env->vl, GETPC()); \
}
GEN_VEXT_LD_US(vle8_v, int8_t, lde_b)
@@ -340,14 +340,14 @@ void HELPER(NAME##_mask)(void *vd, void *v0, target_ulong
base, \
{ \
uint32_t stride = vext_nf(desc) << ctzl(sizeof(ETYPE)); \
vext_ldst_stride(vd, v0, base, stride, env, desc, false, STORE_FN, \
- ctzl(sizeof(ETYPE)), GETPC(), MMU_DATA_STORE); \
+ ctzl(sizeof(ETYPE)), GETPC()); \
} \
\
void HELPER(NAME)(void *vd, void *v0, target_ulong base, \
CPURISCVState *env, uint32_t desc) \
{ \
vext_ldst_us(vd, base, env, desc, STORE_FN, \
- ctzl(sizeof(ETYPE)), env->vl, GETPC(), MMU_DATA_STORE); \
+ ctzl(sizeof(ETYPE)), env->vl, GETPC()); \
}
GEN_VEXT_ST_US(vse8_v, int8_t, ste_b)
@@ -364,7 +364,7 @@ void HELPER(vlm_v)(void *vd, void *v0, target_ulong base,
/* evl = ceil(vl/8) */
uint8_t evl = (env->vl + 7) >> 3;
vext_ldst_us(vd, base, env, desc, lde_b,
- 0, evl, GETPC(), MMU_DATA_LOAD);
+ 0, evl, GETPC());
}
void HELPER(vsm_v)(void *vd, void *v0, target_ulong base,
@@ -373,7 +373,7 @@ void HELPER(vsm_v)(void *vd, void *v0, target_ulong base,
/* evl = ceil(vl/8) */
uint8_t evl = (env->vl + 7) >> 3;
vext_ldst_us(vd, base, env, desc, ste_b,
- 0, evl, GETPC(), MMU_DATA_STORE);
+ 0, evl, GETPC());
}
/*
@@ -399,7 +399,7 @@ vext_ldst_index(void *vd, void *v0, target_ulong base,
void *vs2, CPURISCVState *env, uint32_t desc,
vext_get_index_addr get_index_addr,
vext_ldst_elem_fn *ldst_elem,
- uint32_t esz, uintptr_t ra, MMUAccessType access_type)
+ uint32_t esz, uintptr_t ra)
{
uint32_t i, k;
uint32_t nf = vext_nf(desc);
@@ -427,7 +427,7 @@ void HELPER(NAME)(void *vd, void *v0, target_ulong base,
\
void *vs2, CPURISCVState *env, uint32_t desc) \
{ \
vext_ldst_index(vd, v0, base, vs2, env, desc, INDEX_FN, \
- LOAD_FN, ctzl(sizeof(ETYPE)), GETPC(), MMU_DATA_LOAD); \
+ LOAD_FN, ctzl(sizeof(ETYPE)), GETPC()); \
}
GEN_VEXT_LD_INDEX(vlxei8_8_v, int8_t, idx_b, lde_b)
@@ -453,7 +453,7 @@ void HELPER(NAME)(void *vd, void *v0, target_ulong base,
\
{ \
vext_ldst_index(vd, v0, base, vs2, env, desc, INDEX_FN, \
STORE_FN, ctzl(sizeof(ETYPE)), \
- GETPC(), MMU_DATA_STORE); \
+ GETPC()); \
}
GEN_VEXT_ST_INDEX(vsxei8_8_v, int8_t, idx_b, ste_b)
@@ -576,8 +576,7 @@ GEN_VEXT_LDFF(vle64ff_v, int64_t, lde_d)
*/
static void
vext_ldst_whole(void *vd, target_ulong base, CPURISCVState *env, uint32_t desc,
- vext_ldst_elem_fn *ldst_elem, uint32_t esz, uintptr_t ra,
- MMUAccessType access_type)
+ vext_ldst_elem_fn *ldst_elem, uint32_t esz, uintptr_t ra)
{
uint32_t i, k, off, pos;
uint32_t nf = vext_nf(desc);
@@ -612,8 +611,7 @@ void HELPER(NAME)(void *vd, target_ulong base, \
CPURISCVState *env, uint32_t desc) \
{ \
vext_ldst_whole(vd, base, env, desc, LOAD_FN, \
- ctzl(sizeof(ETYPE)), GETPC(), \
- MMU_DATA_LOAD); \
+ ctzl(sizeof(ETYPE)), GETPC()); \
}
GEN_VEXT_LD_WHOLE(vl1re8_v, int8_t, lde_b)
@@ -638,8 +636,7 @@ void HELPER(NAME)(void *vd, target_ulong base, \
CPURISCVState *env, uint32_t desc) \
{ \
vext_ldst_whole(vd, base, env, desc, STORE_FN, \
- ctzl(sizeof(ETYPE)), GETPC(), \
- MMU_DATA_STORE); \
+ ctzl(sizeof(ETYPE)), GETPC()); \
}
GEN_VEXT_ST_WHOLE(vs1r_v, int8_t, ste_b)
--
2.34.2
- [PATCH qemu v19 00/16] Add tail agnostic behavior for rvv instructions, ~eopxd, 2022/06/06
- [PATCH qemu v19 03/16] target/riscv: rvv: Rename ambiguous esz, ~eopxd, 2022/06/06
- [PATCH qemu v19 06/16] target/riscv: rvv: Add tail agnostic for vector load / store instructions, ~eopxd, 2022/06/06
- [PATCH qemu v19 05/16] target/riscv: rvv: Add tail agnostic for vv instructions, ~eopxd, 2022/06/06
- [PATCH qemu v19 11/16] target/riscv: rvv: Add tail agnostic for vector fix-point arithmetic instructions, ~eopxd, 2022/06/06
- [PATCH qemu v19 12/16] target/riscv: rvv: Add tail agnostic for vector floating-point instructions, ~eopxd, 2022/06/06
- [PATCH qemu v19 01/16] target/riscv: rvv: Prune redundant ESZ, DSZ parameter passed, ~eopxd, 2022/06/06
- [PATCH qemu v19 02/16] target/riscv: rvv: Prune redundant access_type parameter passed,
~eopxd <=
- [PATCH qemu v19 04/16] target/riscv: rvv: Early exit when vstart >= vl, ~eopxd, 2022/06/06
- [PATCH qemu v19 08/16] target/riscv: rvv: Add tail agnostic for vector integer shift instructions, ~eopxd, 2022/06/06
- [PATCH qemu v19 14/16] target/riscv: rvv: Add tail agnostic for vector mask instructions, ~eopxd, 2022/06/06
- [PATCH qemu v19 07/16] target/riscv: rvv: Add tail agnostic for vx, vvm, vxm instructions, ~eopxd, 2022/06/06
- [PATCH qemu v19 10/16] target/riscv: rvv: Add tail agnostic for vector integer merge and move instructions, ~eopxd, 2022/06/06
- [PATCH qemu v19 13/16] target/riscv: rvv: Add tail agnostic for vector reduction instructions, ~eopxd, 2022/06/06
- [PATCH qemu v19 09/16] target/riscv: rvv: Add tail agnostic for vector integer comparison instructions, ~eopxd, 2022/06/06
- [PATCH qemu v19 16/16] target/riscv: rvv: Add option 'rvv_ta_all_1s' to enable optional tail agnostic behavior, ~eopxd, 2022/06/06
- [PATCH qemu v19 15/16] target/riscv: rvv: Add tail agnostic for vector permutation instructions, ~eopxd, 2022/06/06
- Re: [PATCH qemu v19 00/16] Add tail agnostic behavior for rvv instructions, Alistair Francis, 2022/06/07