[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
Re: [PATCH] target/riscv: Remove condition guarding register zero for au
From: |
Alistair Francis |
Subject: |
Re: [PATCH] target/riscv: Remove condition guarding register zero for auipc and lui |
Date: |
Mon, 13 Jun 2022 09:37:08 +1000 |
On Sat, Jun 11, 2022 at 2:59 AM Víctor Colombo
<victor.colombo@eldorado.org.br> wrote:
>
> Commit 57c108b8646 introduced gen_set_gpri(), which already contains
> a check for if the destination register is 'zero'. The check in auipc
> and lui are then redundant. This patch removes those checks.
>
> Signed-off-by: Víctor Colombo <victor.colombo@eldorado.org.br>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> target/riscv/insn_trans/trans_rvi.c.inc | 8 ++------
> 1 file changed, 2 insertions(+), 6 deletions(-)
>
> diff --git a/target/riscv/insn_trans/trans_rvi.c.inc
> b/target/riscv/insn_trans/trans_rvi.c.inc
> index f1342f30f8..c190a59f22 100644
> --- a/target/riscv/insn_trans/trans_rvi.c.inc
> +++ b/target/riscv/insn_trans/trans_rvi.c.inc
> @@ -32,17 +32,13 @@ static bool trans_c64_illegal(DisasContext *ctx,
> arg_empty *a)
>
> static bool trans_lui(DisasContext *ctx, arg_lui *a)
> {
> - if (a->rd != 0) {
> - gen_set_gpri(ctx, a->rd, a->imm);
> - }
> + gen_set_gpri(ctx, a->rd, a->imm);
> return true;
> }
>
> static bool trans_auipc(DisasContext *ctx, arg_auipc *a)
> {
> - if (a->rd != 0) {
> - gen_set_gpri(ctx, a->rd, a->imm + ctx->base.pc_next);
> - }
> + gen_set_gpri(ctx, a->rd, a->imm + ctx->base.pc_next);
> return true;
> }
>
> --
> 2.25.1
>
>