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Re: [PATCH] target/riscv: Update tval for hardware watchpoint

From: Richard Henderson
Subject: Re: [PATCH] target/riscv: Update tval for hardware watchpoint
Date: Wed, 15 Jun 2022 08:15:22 -0700
User-agent: Mozilla/5.0 (X11; Linux x86_64; rv:91.0) Gecko/20100101 Thunderbird/91.9.1

On 6/14/22 21:08, Bin Meng wrote:
From: Bin Meng <bin.meng@windriver.com>

When watchpoint is hit, the breakpoint exception should update tval
to point to the faulting virtual address.

Signed-off-by: Bin Meng <bin.meng@windriver.com>

  target/riscv/cpu.h        | 1 +
  target/riscv/cpu_helper.c | 6 ++++++
  target/riscv/debug.c      | 2 ++
  3 files changed, 9 insertions(+)

diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 7d6397acdf..fdcba8978b 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -289,6 +289,7 @@ struct CPUArchState {
/* trigger module */
      target_ulong trigger_cur;
+    bool wp_hit;

It would be better to not add this, which duplicates cs->watchpoint_hit.
In riscv_cpu_debug_excp_handler, raise a synthetic exception number (RISCV_EXCP_WATCHPOINT?), then set tval in the same switch as the others.


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