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[PATCH v7 1/4] Revert "target/riscv: Add dummy mcountinhibit CSR for pri
From: |
Anup Patel |
Subject: |
[PATCH v7 1/4] Revert "target/riscv: Add dummy mcountinhibit CSR for priv spec v1.11 or higher" |
Date: |
Tue, 28 Jun 2022 10:10:25 +0530 |
This reverts commit 33cc1c0b69e457f5c526f64297353cba6f7bfdb4 because
commit eab4776b2badd4088a4f807c9bb3dc453c53dc23 already implements
proper mcountinhibit CSR emulation.
Signed-off-by: Anup Patel <apatel@ventanamicro.com>
---
target/riscv/cpu_bits.h | 3 ---
target/riscv/csr.c | 2 --
2 files changed, 5 deletions(-)
diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
index 8724b45c08..b3f7fa7130 100644
--- a/target/riscv/cpu_bits.h
+++ b/target/riscv/cpu_bits.h
@@ -159,9 +159,6 @@
#define CSR_MTVEC 0x305
#define CSR_MCOUNTEREN 0x306
-/* Machine Counter Setup */
-#define CSR_MCOUNTINHIBIT 0x320
-
/* 32-bit only */
#define CSR_MSTATUSH 0x310
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index b5734957cf..d65318dcc6 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -3642,8 +3642,6 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
[CSR_MIE] = { "mie", any, NULL, NULL, rmw_mie
},
[CSR_MTVEC] = { "mtvec", any, read_mtvec, write_mtvec
},
[CSR_MCOUNTEREN] = { "mcounteren", any, read_mcounteren,
write_mcounteren },
- [CSR_MCOUNTINHIBIT] = { "mcountinhibit", any, read_zero, write_ignore,
- .min_priv_ver =
PRIV_VERSION_1_11_0 },
[CSR_MSTATUSH] = { "mstatush", any32, read_mstatush,
write_mstatush },
--
2.34.1