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Re: [PATCH v9 1/2] target/riscv: Update [m|h]tinst CSR in riscv_cpu_do_i

From: Alistair Francis
Subject: Re: [PATCH v9 1/2] target/riscv: Update [m|h]tinst CSR in riscv_cpu_do_interrupt()
Date: Mon, 4 Jul 2022 12:17:21 +1000

On Thu, Jun 30, 2022 at 4:13 PM Anup Patel <apatel@ventanamicro.com> wrote:
> We should write transformed instruction encoding of the trapped
> instruction in [m|h]tinst CSR at time of taking trap as defined
> by the RISC-V privileged specification v1.12.
> Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
> Signed-off-by: Anup Patel <apatel@ventanamicro.com>

@dramforever do you want to give an Ack or Reviewed-by?


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