Re: [PATCH v2] target/riscv: fix shifts shamt value for rv128c

[Richard Henderson]

On 7/12/22 01:24, Frédéric Pétrot wrote:
>    Agreed, on the non compressed insns, but the compressed ones have a 6-bit
>    shamt only as visible on page 18.6 page 125. The explanation for rv128 shifts
>    is further detailed in the emphasized paragraph on top of page 120.

I see.  I should have read the "c" more carefully there.
Indeed, the code is correct.

I think the language could be improved a little for clarity:

> >     +static int ex_rvc_shiftri(DisasContext *ctx, int imm)
> >     +{
> >     +    /*
> >     +     * For RV128 a shamt of 0 means a shift by 64, furthermore, for right
> >     +     * shifts, the shamt is sign-extended.
> >     +     */

For RV128C, a shamt of 0 means shift by 64, and the shamt is sign-extended.  Combine this 
with implicit truncation to 7 bits, and this equates to replicating bit 5 to bit 6.

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>


r~