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Re: [PATCH] riscv: Make semihosting configurable for all privilege modes

From: Furquan Shaikh
Subject: Re: [PATCH] riscv: Make semihosting configurable for all privilege modes
Date: Fri, 12 Aug 2022 22:22:26 -0700

On Fri, Aug 12, 2022 at 7:32 PM Richard Henderson
<richard.henderson@linaro.org> wrote:
> On 8/12/22 17:50, Furquan Shaikh wrote:
> >> Why do you need such fine-grained control?  What is the use-case?
> >
> > I ran into a problem when I was testing a project (with a microkernel
> > in M-mode and tasks in U-mode) that uses semihosting for debugging.
> > The semihosting worked fine for M-mode but not in U-mode.
> Sure.  This would be handled by Peter's proposed userspace-enable=on property.
> > As I started
> > digging into this, I realized that this is because qemu restricts
> > semihosting to only M and S modes. From reading the debug spec, I
> > understood that the DCSR presents options for ebreak behavior in each
> > mode including VS and VU.
> I strongly suspect that VS also already works, since that's just
>    env->priv == PRV_S && riscv_cpu_virt_enabled(env)
> VU would also be handled by userspace-enable=on.
> I do not see any use for 5 separate properties.

It felt more natural to mimic the knobs that are provided by the debug
spec to allow users to easily control the ebreak behavior for
semihosting in all possible modes. I agree that it is possible to just
allow semihosting to be turned on/off for U-mode using the above
proposed config. It would work for the use case I ran into, but if
finer control is required for other cases, it makes sense to provide
the ebreak options. Anyways, if others here feel that the
userspace-enable option is sufficient, we can go ahead with that.

> r~

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