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[PATCH 09/15] hw/riscv: microchip_pfsoc: Fix the number of interrupt sou
From: |
Bin Meng |
Subject: |
[PATCH 09/15] hw/riscv: microchip_pfsoc: Fix the number of interrupt sources of PLIC |
Date: |
Thu, 1 Dec 2022 22:08:05 +0800 |
Per chapter 6.5.2 in [1], the number of interupt sources including
interrupt source 0 should be 187.
[1] PolarFire SoC MSS TRM:
https://ww1.microchip.com/downloads/aemDocuments/documents/FPGA/ProductDocuments/ReferenceManuals/PolarFire_SoC_FPGA_MSS_Technical_Reference_Manual_VC.pdf
Fixes: 56f6e31e7b7e ("hw/riscv: Initial support for Microchip PolarFire SoC
Icicle Kit board")
Signed-off-by: Bin Meng <bmeng@tinylab.org>
---
include/hw/riscv/microchip_pfsoc.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/include/hw/riscv/microchip_pfsoc.h
b/include/hw/riscv/microchip_pfsoc.h
index a757b240e0..9720bac2d5 100644
--- a/include/hw/riscv/microchip_pfsoc.h
+++ b/include/hw/riscv/microchip_pfsoc.h
@@ -150,7 +150,7 @@ enum {
#define MICROCHIP_PFSOC_MANAGEMENT_CPU_COUNT 1
#define MICROCHIP_PFSOC_COMPUTE_CPU_COUNT 4
-#define MICROCHIP_PFSOC_PLIC_NUM_SOURCES 185
+#define MICROCHIP_PFSOC_PLIC_NUM_SOURCES 187
#define MICROCHIP_PFSOC_PLIC_NUM_PRIORITIES 7
#define MICROCHIP_PFSOC_PLIC_PRIORITY_BASE 0x04
#define MICROCHIP_PFSOC_PLIC_PENDING_BASE 0x1000
--
2.34.1
- Re: [PATCH 06/15] hw/intc: sifive_plic: Drop PLICMode_H, (continued)
- [PATCH 05/15] hw/riscv: spike: Remove misleading comments, Bin Meng, 2022/12/01
- [PATCH 07/15] hw/intc: sifive_plic: Improve robustness of the PLIC config parser, Bin Meng, 2022/12/01
- [PATCH 04/15] hw/riscv: Sort machines Kconfig options in alphabetical order, Bin Meng, 2022/12/01
- [PATCH 08/15] hw/intc: sifive_plic: Update "num-sources" property default value, Bin Meng, 2022/12/01
- [PATCH 09/15] hw/riscv: microchip_pfsoc: Fix the number of interrupt sources of PLIC,
Bin Meng <=
- [PATCH 11/15] hw/riscv: sifive_u: Avoid using magic number for "riscv, ndev", Bin Meng, 2022/12/01
- [PATCH 10/15] hw/riscv: sifive_e: Fix the number of interrupt sources of PLIC, Bin Meng, 2022/12/01
- [PATCH 12/15] hw/riscv: virt: Fix the value of "riscv, ndev" in the dtb, Bin Meng, 2022/12/01