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[PATCH v2 11/15] RISC-V: Adding T-Head XMAE support
From: |
Christoph Muellner |
Subject: |
[PATCH v2 11/15] RISC-V: Adding T-Head XMAE support |
Date: |
Fri, 23 Dec 2022 19:00:11 +0100 |
From: Christoph Müllner <christoph.muellner@vrull.eu>
This patch adds support for the T-Head specific extended memory
attributes. Similar like Svpbmt, this support does not have much effect
as most behaviour is not modelled in QEMU.
We also don't set any EDATA information, because XMAE discovery is done
using the vendor ID in the Linux kernel.
Changes in v2:
- Add ISA_EXT_DATA_ENTRY()
Co-developed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
---
target/riscv/cpu.c | 2 ++
target/riscv/cpu.h | 1 +
target/riscv/cpu_helper.c | 6 ++++--
3 files changed, 7 insertions(+), 2 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 9c31a50e90..bb310755b1 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -118,6 +118,7 @@ static const struct isa_ext_data isa_edata_arr[] = {
ISA_EXT_DATA_ENTRY(xtheadmemidx, true, PRIV_VERSION_1_11_0,
ext_xtheadmemidx),
ISA_EXT_DATA_ENTRY(xtheadmempair, true, PRIV_VERSION_1_11_0,
ext_xtheadmempair),
ISA_EXT_DATA_ENTRY(xtheadsync, true, PRIV_VERSION_1_11_0, ext_xtheadsync),
+ ISA_EXT_DATA_ENTRY(xtheadxmae, true, PRIV_VERSION_1_11_0, ext_xtheadxmae),
ISA_EXT_DATA_ENTRY(xventanacondops, true, PRIV_VERSION_1_12_0,
ext_XVentanaCondOps),
};
@@ -1080,6 +1081,7 @@ static Property riscv_cpu_extensions[] = {
DEFINE_PROP_BOOL("xtheadmemidx", RISCVCPU, cfg.ext_xtheadmemidx, false),
DEFINE_PROP_BOOL("xtheadmempair", RISCVCPU, cfg.ext_xtheadmempair, false),
DEFINE_PROP_BOOL("xtheadsync", RISCVCPU, cfg.ext_xtheadsync, false),
+ DEFINE_PROP_BOOL("xtheadxmae", RISCVCPU, cfg.ext_xtheadxmae, false),
DEFINE_PROP_BOOL("xventanacondops", RISCVCPU, cfg.ext_XVentanaCondOps,
false),
/* These are experimental so mark with 'x-' */
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index c97c1c0af0..897962f107 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -475,6 +475,7 @@ struct RISCVCPUConfig {
bool ext_xtheadmemidx;
bool ext_xtheadmempair;
bool ext_xtheadsync;
+ bool ext_xtheadxmae;
bool ext_XVentanaCondOps;
uint8_t pmu_num;
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index 278d163803..345bb69b79 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -938,7 +938,8 @@ restart:
if (riscv_cpu_sxl(env) == MXL_RV32) {
ppn = pte >> PTE_PPN_SHIFT;
- } else if (cpu->cfg.ext_svpbmt || cpu->cfg.ext_svnapot) {
+ } else if (cpu->cfg.ext_svpbmt || cpu->cfg.ext_svnapot ||
+ cpu->cfg.ext_xtheadxmae) {
ppn = (pte & (target_ulong)PTE_PPN_MASK) >> PTE_PPN_SHIFT;
} else {
ppn = pte >> PTE_PPN_SHIFT;
@@ -950,7 +951,8 @@ restart:
if (!(pte & PTE_V)) {
/* Invalid PTE */
return TRANSLATE_FAIL;
- } else if (!cpu->cfg.ext_svpbmt && (pte & PTE_PBMT)) {
+ } else if (!cpu->cfg.ext_svpbmt && (pte & PTE_PBMT) &&
+ !cpu->cfg.ext_xtheadxmae) {
return TRANSLATE_FAIL;
} else if (!(pte & (PTE_R | PTE_W | PTE_X))) {
/* Inner PTE, continue walking */
--
2.38.1
- [PATCH v2 00/15] Add support for the T-Head vendor extensions, Christoph Muellner, 2022/12/23
- [PATCH v2 02/15] RISC-V: Adding XTheadSync ISA extension, Christoph Muellner, 2022/12/23
- [PATCH v2 05/15] RISC-V: Adding XTheadBs ISA extension, Christoph Muellner, 2022/12/23
- [PATCH v2 06/15] RISC-V: Adding XTheadCondMov ISA extension, Christoph Muellner, 2022/12/23
- [PATCH v2 01/15] RISC-V: Adding XTheadCmo ISA extension, Christoph Muellner, 2022/12/23
- [PATCH v2 03/15] RISC-V: Adding XTheadBa ISA extension, Christoph Muellner, 2022/12/23
- [PATCH v2 04/15] RISC-V: Adding XTheadBb ISA extension, Christoph Muellner, 2022/12/23
- [PATCH v2 09/15] RISC-V: Adding T-Head MemIdx extension, Christoph Muellner, 2022/12/23
- [PATCH v2 07/15] RISC-V: Adding T-Head multiply-accumulate instructions, Christoph Muellner, 2022/12/23
- [PATCH v2 11/15] RISC-V: Adding T-Head XMAE support,
Christoph Muellner <=
- [PATCH v2 15/15] target/riscv: add a MAINTAINERS entry for XThead* extension support, Christoph Muellner, 2022/12/23
- [PATCH v2 08/15] RISC-V: Adding T-Head MemPair extension, Christoph Muellner, 2022/12/23
- [PATCH v2 10/15] RISC-V: Adding T-Head FMemIdx extension, Christoph Muellner, 2022/12/23
- [PATCH v2 12/15] RISC-V: Set minimum priv version for Zfh to 1.11, Christoph Muellner, 2022/12/23
- [PATCH v2 14/15] RISC-V: Adding XTheadFmv ISA extension, Christoph Muellner, 2022/12/23
- [PATCH v2 13/15] RISC-V: Add initial support for T-Head C906, Christoph Muellner, 2022/12/23