Re: [PATCH 08/11] target/riscv: remove RISCV_FEATURE_PMP

[weiwei]

On 2023/2/10 21:36, Daniel Henrique Barboza wrote:
> RISCV_FEATURE_PMP is being set via riscv_set_feature() by mirroring the
> cpu->cfg.pmp flag. Use the flag instead.
>
> Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>

Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>

Regards,

Weiwei Li

> ---
>   target/riscv/cpu.c        | 4 ----
>   target/riscv/cpu.h        | 1 -
>   target/riscv/cpu_helper.c | 2 +-
>   target/riscv/csr.c        | 2 +-
>   target/riscv/machine.c    | 3 +--
>   target/riscv/op_helper.c  | 2 +-
>   target/riscv/pmp.c        | 2 +-
>   7 files changed, 5 insertions(+), 11 deletions(-)
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index 430b6adccb..a803395ed1 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -923,10 +923,6 @@ static void riscv_cpu_realize(DeviceState *dev, Error 
> **errp)
>           riscv_set_feature(env, RISCV_FEATURE_MMU);
>       }
>   
> -    if (cpu->cfg.pmp) {
> -        riscv_set_feature(env, RISCV_FEATURE_PMP);
> -    }
> -
>       if (cpu->cfg.epmp && !cpu->cfg.pmp) {
>           /*
>            * Enhanced PMP should only be available
> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
> index d0de11fd41..62919cd5cc 100644
> --- a/target/riscv/cpu.h
> +++ b/target/riscv/cpu.h
> @@ -87,7 +87,6 @@
>      so a cpu features bitfield is required, likewise for optional PMP support 
> */
>   enum {
>       RISCV_FEATURE_MMU,
> -    RISCV_FEATURE_PMP,
>   };
>   
>   /* Privileged specification version */
> diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
> index 4cdd247c6c..15d9542691 100644
> --- a/target/riscv/cpu_helper.c
> +++ b/target/riscv/cpu_helper.c
> @@ -706,7 +706,7 @@ static int get_physical_address_pmp(CPURISCVState *env, int 
> *prot,
>       pmp_priv_t pmp_priv;
>       int pmp_index = -1;
>   
> -    if (!riscv_feature(env, RISCV_FEATURE_PMP)) {
> +    if (!riscv_cpu_cfg(env).pmp) {
>           *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
>           return TRANSLATE_SUCCESS;
>       }
> diff --git a/target/riscv/csr.c b/target/riscv/csr.c
> index 5b974dad6b..3d55b1b138 100644
> --- a/target/riscv/csr.c
> +++ b/target/riscv/csr.c
> @@ -419,7 +419,7 @@ static int aia_hmode32(CPURISCVState *env, int csrno)
>   
>   static RISCVException pmp(CPURISCVState *env, int csrno)
>   {
> -    if (riscv_feature(env, RISCV_FEATURE_PMP)) {
> +    if (riscv_cpu_cfg(env).pmp) {
>           return RISCV_EXCP_NONE;
>       }
>   
> diff --git a/target/riscv/machine.c b/target/riscv/machine.c
> index 4634968898..67e9e56853 100644
> --- a/target/riscv/machine.c
> +++ b/target/riscv/machine.c
> @@ -27,9 +27,8 @@
>   static bool pmp_needed(void *opaque)
>   {
>       RISCVCPU *cpu = opaque;
> -    CPURISCVState *env = &cpu->env;
>   
> -    return riscv_feature(env, RISCV_FEATURE_PMP);
> +    return cpu->cfg.pmp;
>   }
>   
>   static int pmp_post_load(void *opaque, int version_id)
> diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c
> index 48f918b71b..f34701b443 100644
> --- a/target/riscv/op_helper.c
> +++ b/target/riscv/op_helper.c
> @@ -195,7 +195,7 @@ target_ulong helper_mret(CPURISCVState *env)
>       uint64_t mstatus = env->mstatus;
>       target_ulong prev_priv = get_field(mstatus, MSTATUS_MPP);
>   
> -    if (riscv_feature(env, RISCV_FEATURE_PMP) &&
> +    if (riscv_cpu_cfg(env).pmp &&
>           !pmp_get_num_rules(env) && (prev_priv != PRV_M)) {
>           riscv_raise_exception(env, RISCV_EXCP_INST_ACCESS_FAULT, GETPC());
>       }
> diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c
> index bb54899635..1e7903dffa 100644
> --- a/target/riscv/pmp.c
> +++ b/target/riscv/pmp.c
> @@ -265,7 +265,7 @@ static bool pmp_hart_has_privs_default(CPURISCVState *env, 
> target_ulong addr,
>           }
>       }
>   
> -    if ((!riscv_feature(env, RISCV_FEATURE_PMP)) || (mode == PRV_M)) {
> +    if (!riscv_cpu_cfg(env).pmp || (mode == PRV_M)) {
>           /*
>            * Privileged spec v1.10 states if HW doesn't implement any PMP entry
>            * or no PMP entry matches an M-Mode access, the access succeeds.