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[PATCH v2 03/14] target/riscv: Simplify the check for Zfhmin and Zhinxmi
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From: |
Weiwei Li |
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Subject: |
[PATCH v2 03/14] target/riscv: Simplify the check for Zfhmin and Zhinxmin |
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Date: |
Wed, 15 Feb 2023 10:05:28 +0800 |
We needn't check Zfh and Zhinx in these instructions.
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
---
target/riscv/insn_trans/trans_rvzfh.c.inc | 25 +++++++++++------------
1 file changed, 12 insertions(+), 13 deletions(-)
diff --git a/target/riscv/insn_trans/trans_rvzfh.c.inc
b/target/riscv/insn_trans/trans_rvzfh.c.inc
index 2ad5716312..85fc1aa822 100644
--- a/target/riscv/insn_trans/trans_rvzfh.c.inc
+++ b/target/riscv/insn_trans/trans_rvzfh.c.inc
@@ -28,15 +28,14 @@
} \
} while (0)
-#define REQUIRE_ZFH_OR_ZFHMIN(ctx) do { \
- if (!(ctx->cfg_ptr->ext_zfh || ctx->cfg_ptr->ext_zfhmin)) { \
+#define REQUIRE_ZFHMIN(ctx) do { \
+ if (!ctx->cfg_ptr->ext_zfhmin) { \
return false; \
} \
} while (0)
-#define REQUIRE_ZFH_OR_ZFHMIN_OR_ZHINX_OR_ZHINXMIN(ctx) do { \
- if (!(ctx->cfg_ptr->ext_zfh || ctx->cfg_ptr->ext_zfhmin || \
- ctx->cfg_ptr->ext_zhinx || ctx->cfg_ptr->ext_zhinxmin)) { \
+#define REQUIRE_ZFHMIN_OR_ZHINXMIN(ctx) do { \
+ if (!(ctx->cfg_ptr->ext_zfhmin || ctx->cfg_ptr->ext_zhinxmin)) { \
return false; \
} \
} while (0)
@@ -47,7 +46,7 @@ static bool trans_flh(DisasContext *ctx, arg_flh *a)
TCGv t0;
REQUIRE_FPU;
- REQUIRE_ZFH_OR_ZFHMIN(ctx);
+ REQUIRE_ZFHMIN(ctx);
decode_save_opc(ctx);
t0 = get_gpr(ctx, a->rs1, EXT_NONE);
@@ -70,7 +69,7 @@ static bool trans_fsh(DisasContext *ctx, arg_fsh *a)
TCGv t0;
REQUIRE_FPU;
- REQUIRE_ZFH_OR_ZFHMIN(ctx);
+ REQUIRE_ZFHMIN(ctx);
decode_save_opc(ctx);
t0 = get_gpr(ctx, a->rs1, EXT_NONE);
@@ -401,7 +400,7 @@ static bool trans_fmax_h(DisasContext *ctx, arg_fmax_h *a)
static bool trans_fcvt_s_h(DisasContext *ctx, arg_fcvt_s_h *a)
{
REQUIRE_FPU;
- REQUIRE_ZFH_OR_ZFHMIN_OR_ZHINX_OR_ZHINXMIN(ctx);
+ REQUIRE_ZFHMIN_OR_ZHINXMIN(ctx);
TCGv_i64 dest = dest_fpr(ctx, a->rd);
TCGv_i64 src1 = get_fpr_hs(ctx, a->rs1);
@@ -418,7 +417,7 @@ static bool trans_fcvt_s_h(DisasContext *ctx, arg_fcvt_s_h
*a)
static bool trans_fcvt_d_h(DisasContext *ctx, arg_fcvt_d_h *a)
{
REQUIRE_FPU;
- REQUIRE_ZFH_OR_ZFHMIN_OR_ZHINX_OR_ZHINXMIN(ctx);
+ REQUIRE_ZFHMIN_OR_ZHINXMIN(ctx);
REQUIRE_ZDINX_OR_D(ctx);
TCGv_i64 dest = dest_fpr(ctx, a->rd);
@@ -436,7 +435,7 @@ static bool trans_fcvt_d_h(DisasContext *ctx, arg_fcvt_d_h
*a)
static bool trans_fcvt_h_s(DisasContext *ctx, arg_fcvt_h_s *a)
{
REQUIRE_FPU;
- REQUIRE_ZFH_OR_ZFHMIN_OR_ZHINX_OR_ZHINXMIN(ctx);
+ REQUIRE_ZFHMIN_OR_ZHINXMIN(ctx);
TCGv_i64 dest = dest_fpr(ctx, a->rd);
TCGv_i64 src1 = get_fpr_hs(ctx, a->rs1);
@@ -452,7 +451,7 @@ static bool trans_fcvt_h_s(DisasContext *ctx, arg_fcvt_h_s
*a)
static bool trans_fcvt_h_d(DisasContext *ctx, arg_fcvt_h_d *a)
{
REQUIRE_FPU;
- REQUIRE_ZFH_OR_ZFHMIN_OR_ZHINX_OR_ZHINXMIN(ctx);
+ REQUIRE_ZFHMIN_OR_ZHINXMIN(ctx);
REQUIRE_ZDINX_OR_D(ctx);
TCGv_i64 dest = dest_fpr(ctx, a->rd);
@@ -585,7 +584,7 @@ static bool trans_fcvt_h_wu(DisasContext *ctx,
arg_fcvt_h_wu *a)
static bool trans_fmv_x_h(DisasContext *ctx, arg_fmv_x_h *a)
{
REQUIRE_FPU;
- REQUIRE_ZFH_OR_ZFHMIN(ctx);
+ REQUIRE_ZFHMIN(ctx);
TCGv dest = dest_gpr(ctx, a->rd);
@@ -605,7 +604,7 @@ static bool trans_fmv_x_h(DisasContext *ctx, arg_fmv_x_h *a)
static bool trans_fmv_h_x(DisasContext *ctx, arg_fmv_h_x *a)
{
REQUIRE_FPU;
- REQUIRE_ZFH_OR_ZFHMIN(ctx);
+ REQUIRE_ZFHMIN(ctx);
TCGv t0 = get_gpr(ctx, a->rs1, EXT_ZERO);
--
2.25.1
- [PATCH v2 00/14] target/riscv: Some updates to float point related extensions, Weiwei Li, 2023/02/14
- [PATCH v2 07/14] target/riscv: Indent fixes in cpu.c, Weiwei Li, 2023/02/14
- [PATCH v2 01/14] target/riscv: Fix the relationship between Zfhmin and Zfh, Weiwei Li, 2023/02/14
- [PATCH v2 05/14] target/riscv: Fix relationship between V, Zve*, F and D, Weiwei Li, 2023/02/14
- [PATCH v2 04/14] target/riscv: Add cfg properties for Zv* extensions, Weiwei Li, 2023/02/14
- [PATCH v2 10/14] target/riscv: Remove rebundunt check for zve32f and zve64f, Weiwei Li, 2023/02/14
- [PATCH v2 03/14] target/riscv: Simplify the check for Zfhmin and Zhinxmin,
Weiwei Li <=
- [PATCH v2 14/14] target/riscv: Expose properties for Zv* extensions, Weiwei Li, 2023/02/14
- [PATCH v2 02/14] target/riscv: Fix the relationship between Zhinxmin and Zhinx, Weiwei Li, 2023/02/14
- [PATCH v2 06/14] target/riscv: Add propertie check for Zvfh{min} extensions, Weiwei Li, 2023/02/14
- [PATCH v2 11/14] target/riscv: Add support for Zvfh/zvfhmin extensions, Weiwei Li, 2023/02/14
- [PATCH v2 09/14] target/riscv: Replace check for F/D to Zve32f/Zve64d in trans_rvv.c.inc, Weiwei Li, 2023/02/14
- [PATCH v2 13/14] target/riscv: Simplify check for EEW = 64 in trans_rvv.c.inc, Weiwei Li, 2023/02/14
- [PATCH v2 12/14] target/riscv: Fix check for vector load/store instructions when EEW=64, Weiwei Li, 2023/02/14
- [PATCH v2 08/14] target/riscv: Simplify check for Zve32f and Zve64f, Weiwei Li, 2023/02/14