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Re: [PATCH v5 2/4] target/riscv: implement Zicboz extension

From: Richard Henderson
Subject: Re: [PATCH v5 2/4] target/riscv: implement Zicboz extension
Date: Wed, 15 Feb 2023 11:28:13 -1000
User-agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.7.1

On 2/15/23 10:59, Daniel Henrique Barboza wrote:
+    mem = probe_access(env, address, cbozlen, MMU_DATA_STORE,
+                       cpu_mmu_index(env, false), ra);
+    /* Zero the block */
+    memset(mem, 0, cbozlen);

Will crash if address does not resolve to ram.

According to page 16, you need to store zeros even if the memory is not cacheable. C.f. target/arm/helper-a64.c HELPER(dc_zva) or target/s390x/tcg/mem_helper.c do_access_memset.

While re-reading the ARM code, I remembered that the ARM dc.zva instruction is required to produce original unmasked address on a page fault, thus the little dance with two calls to probe_write.

I don't immediately see language in the risc-v spec beyond "CMO instructions do not generate address misaligned exceptions."


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