Re: [PATCH 12/18] target/riscv: Allow debugger to access user timer and counter CSRs

[LIU Zhiwei]

On 2023/2/14 9:09, Bin Meng wrote:
> At present user timer and counter CSRs are not reported in the
> CSR XML hence gdb cannot access them.
>
> Fix it by addding a debugger check in their predicate() routine.
>
> Signed-off-by: Bin Meng <bmeng@tinylab.org>
> ---
>
>   target/riscv/csr.c | 4 ++++
>   1 file changed, 4 insertions(+)
>
> diff --git a/target/riscv/csr.c b/target/riscv/csr.c
> index 749d0ef83e..515b05348b 100644
> --- a/target/riscv/csr.c
> +++ b/target/riscv/csr.c
> @@ -131,6 +131,10 @@ static RISCVException ctr(CPURISCVState *env, int csrno)
>   
>   skip_ext_pmu_check:
>   
> +    if (env->debugger) {
> +        return RISCV_EXCP_NONE;
> +    }
> +

Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>


Zhiwei

>       if (env->priv < PRV_M && !get_field(env->mcounteren, ctr_mask)) {
>           return RISCV_EXCP_ILLEGAL_INST;
>       }