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[PATCH v7 02/10] target/riscv: do not mask unsupported QEMU extensions i
From: |
Daniel Henrique Barboza |
Subject: |
[PATCH v7 02/10] target/riscv: do not mask unsupported QEMU extensions in write_misa() |
Date: |
Wed, 22 Feb 2023 15:51:57 -0300 |
The masking done using env->misa_ext_mask already filters any extension
that QEMU doesn't support. If the hart supports the extension then QEMU
supports it as well.
If the masking done by env->misa_ext_mask is somehow letting unsupported
QEMU extensions pass by, misa_ext_mask itself needs to be fixed instead.
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
Reviewed-by: Bin Meng <bmeng@tinylab.org>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
---
target/riscv/csr.c | 3 ---
1 file changed, 3 deletions(-)
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index 1b0a0c1693..e149b453da 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -1356,9 +1356,6 @@ static RISCVException write_misa(CPURISCVState *env, int
csrno,
/* Mask extensions that are not supported by this hart */
val &= env->misa_ext_mask;
- /* Mask extensions that are not supported by QEMU */
- val &= (RVI | RVE | RVM | RVA | RVF | RVD | RVC | RVS | RVU | RVV);
-
/* 'D' depends on 'F', so clear 'D' if 'F' is not present */
if ((val & RVD) && !(val & RVF)) {
val &= ~RVD;
--
2.39.2
- [PATCH v7 00/10] make write_misa a no-op and FEATURE_* cleanups, Daniel Henrique Barboza, 2023/02/22
- [PATCH v7 01/10] target/riscv: introduce riscv_cpu_cfg(), Daniel Henrique Barboza, 2023/02/22
- [PATCH v7 02/10] target/riscv: do not mask unsupported QEMU extensions in write_misa(),
Daniel Henrique Barboza <=
- [PATCH v7 03/10] target/riscv: allow MISA writes as experimental, Daniel Henrique Barboza, 2023/02/22
- Re: [PATCH v7 03/10] target/riscv: allow MISA writes as experimental, liweiwei, 2023/02/22
- Re: [PATCH v7 03/10] target/riscv: allow MISA writes as experimental, Andrew Jones, 2023/02/23
- Re: [PATCH v7 03/10] target/riscv: allow MISA writes as experimental, Bin Meng, 2023/02/28
- Re: [PATCH v7 03/10] target/riscv: allow MISA writes as experimental, liweiwei, 2023/02/28
- Re: [PATCH v7 03/10] target/riscv: allow MISA writes as experimental, LIU Zhiwei, 2023/02/28
- [PATCH v7 04/10] target/riscv: remove RISCV_FEATURE_DEBUG, Daniel Henrique Barboza, 2023/02/22
- [PATCH v7 05/10] target/riscv/cpu.c: error out if EPMP is enabled without PMP, Daniel Henrique Barboza, 2023/02/22
- [PATCH v7 06/10] target/riscv: remove RISCV_FEATURE_EPMP, Daniel Henrique Barboza, 2023/02/22
- [PATCH v7 07/10] target/riscv: remove RISCV_FEATURE_PMP, Daniel Henrique Barboza, 2023/02/22