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[PATCH v2 13/19] target/riscv: remove cpu->cfg.ext_h
From: |
Daniel Henrique Barboza |
Subject: |
[PATCH v2 13/19] target/riscv: remove cpu->cfg.ext_h |
Date: |
Mon, 27 Mar 2023 19:49:28 -0300 |
Create a new "h" RISCVCPUMisaExtConfig property that will update
env->misa_ext* with RVH. Instances of cpu->cfg.ext_h and similar are
replaced with riscv_has_ext(env, RVH).
Remove the old "h" property and 'ext_h' from RISCVCPUConfig.
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
---
target/riscv/cpu.c | 10 +++++-----
target/riscv/cpu.h | 1 -
2 files changed, 5 insertions(+), 6 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 68233c8e89..9fa7104801 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -841,13 +841,13 @@ static void riscv_cpu_validate_set_extensions(RISCVCPU
*cpu, Error **errp)
return;
}
- if (cpu->cfg.ext_h && !riscv_has_ext(env, RVI)) {
+ if (riscv_has_ext(env, RVH) && !riscv_has_ext(env, RVI)) {
error_setg(errp,
"H depends on an I base integer ISA with 32 x registers");
return;
}
- if (cpu->cfg.ext_h && !riscv_has_ext(env, RVS)) {
+ if (riscv_has_ext(env, RVH) && !riscv_has_ext(env, RVS)) {
error_setg(errp, "H extension implicitly requires S-mode");
return;
}
@@ -1113,7 +1113,7 @@ static void riscv_cpu_sync_misa_cfg(CPURISCVState *env)
if (riscv_has_ext(env, RVU)) {
ext |= RVU;
}
- if (riscv_cpu_cfg(env)->ext_h) {
+ if (riscv_has_ext(env, RVH)) {
ext |= RVH;
}
if (riscv_cpu_cfg(env)->ext_v) {
@@ -1450,6 +1450,8 @@ static const RISCVCPUMisaExtConfig misa_ext_cfgs[] = {
.misa_bit = RVS, .enabled = true},
{.name = "u", .description = "User-level instructions",
.misa_bit = RVU, .enabled = true},
+ {.name = "h", .description = "Hypervisor",
+ .misa_bit = RVH, .enabled = true},
};
static void riscv_cpu_add_misa_properties(Object *cpu_obj)
@@ -1474,7 +1476,6 @@ static Property riscv_cpu_extensions[] = {
/* Defaults for standard extensions */
DEFINE_PROP_BOOL("g", RISCVCPU, cfg.ext_g, false),
DEFINE_PROP_BOOL("v", RISCVCPU, cfg.ext_v, false),
- DEFINE_PROP_BOOL("h", RISCVCPU, cfg.ext_h, true),
DEFINE_PROP_UINT8("pmu-num", RISCVCPU, cfg.pmu_num, 16),
DEFINE_PROP_BOOL("sscofpmf", RISCVCPU, cfg.ext_sscofpmf, false),
DEFINE_PROP_BOOL("Zifencei", RISCVCPU, cfg.ext_ifencei, true),
@@ -1579,7 +1580,6 @@ static void register_cpu_props(Object *obj)
*/
if (cpu->env.misa_ext != 0) {
cpu->cfg.ext_v = misa_ext & RVV;
- cpu->cfg.ext_h = misa_ext & RVH;
cpu->cfg.ext_j = misa_ext & RVJ;
/*
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 7b98cf4dd7..f3cb28443c 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -419,7 +419,6 @@ typedef struct {
struct RISCVCPUConfig {
bool ext_g;
- bool ext_h;
bool ext_j;
bool ext_v;
bool ext_zba;
--
2.39.2
- [PATCH v2 01/19] target/riscv: sync env->misa_ext* with cpu->cfg in realize(), (continued)
- [PATCH v2 01/19] target/riscv: sync env->misa_ext* with cpu->cfg in realize(), Daniel Henrique Barboza, 2023/03/27
- [PATCH v2 02/19] target/riscv: remove MISA properties from isa_edata_arr[], Daniel Henrique Barboza, 2023/03/27
- [PATCH v2 03/19] target/riscv: introduce riscv_cpu_add_misa_properties(), Daniel Henrique Barboza, 2023/03/27
- [PATCH v2 04/19] target/riscv: remove cpu->cfg.ext_a, Daniel Henrique Barboza, 2023/03/27
- [PATCH v2 05/19] target/riscv: remove cpu->cfg.ext_c, Daniel Henrique Barboza, 2023/03/27
- [PATCH v2 06/19] target/riscv: remove cpu->cfg.ext_d, Daniel Henrique Barboza, 2023/03/27
- [PATCH v2 07/19] target/riscv: remove cpu->cfg.ext_f, Daniel Henrique Barboza, 2023/03/27
- [PATCH v2 10/19] target/riscv: remove cpu->cfg.ext_m, Daniel Henrique Barboza, 2023/03/27
- [PATCH v2 09/19] target/riscv: remove cpu->cfg.ext_e, Daniel Henrique Barboza, 2023/03/27
- [PATCH v2 08/19] target/riscv: remove cpu->cfg.ext_i, Daniel Henrique Barboza, 2023/03/27
- [PATCH v2 13/19] target/riscv: remove cpu->cfg.ext_h,
Daniel Henrique Barboza <=
- [PATCH v2 11/19] target/riscv: remove cpu->cfg.ext_s, Daniel Henrique Barboza, 2023/03/27
- [PATCH v2 12/19] target/riscv: remove cpu->cfg.ext_u, Daniel Henrique Barboza, 2023/03/27
- [PATCH v2 14/19] target/riscv: remove cpu->cfg.ext_j, Daniel Henrique Barboza, 2023/03/27
- [PATCH v2 15/19] target/riscv: remove cpu->cfg.ext_v, Daniel Henrique Barboza, 2023/03/27
- [PATCH v2 16/19] target/riscv: remove riscv_cpu_sync_misa_cfg(), Daniel Henrique Barboza, 2023/03/27
- [PATCH v2 17/19] target/riscv: remove cfg.ext_g setup from rv64_thead_c906_cpu_init(), Daniel Henrique Barboza, 2023/03/27
- [PATCH v2 18/19] target/riscv: add RVG and remove cpu->cfg.ext_g, Daniel Henrique Barboza, 2023/03/27
- [PATCH v2 19/19] target/riscv/cpu.c: redesign register_cpu_props(), Daniel Henrique Barboza, 2023/03/27