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Re: [PATCH 6/9] target/riscv/cpu: Share RISCVCPUConfig with disassembler

From: LIU Zhiwei
Subject: Re: [PATCH 6/9] target/riscv/cpu: Share RISCVCPUConfig with disassembler
Date: Mon, 12 Jun 2023 14:25:34 +0800
User-agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:102.0) Gecko/20100101 Thunderbird/102.12.0

On 2023/5/30 21:18, Christoph Muellner wrote:
From: Christoph Müllner <christoph.muellner@vrull.eu>

The disassembler needs the available extensions in order
to properly decode instructions in case of overlapping
encodings (e.g. for vendor extensions).

Let's use the field 'disassemble_info::private_data' to store
our RISCVCPUConfig pointer.

Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
  target/riscv/cpu.c | 3 +++
  1 file changed, 3 insertions(+)

diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 5b7818dbd1..6f0cd9a0bb 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -819,6 +819,9 @@ static void riscv_cpu_disas_set_info(CPUState *s, 
disassemble_info *info)
      RISCVCPU *cpu = RISCV_CPU(s);
      CPURISCVState *env = &cpu->env;
+    RISCVCPUConfig *cfg = &cpu->cfg;
+    info->private_data = cfg;

I don't know if this field will be overridden by the binutils. Can we extend the struct disassemble_info, and add some fields like supporting for Capstone?


switch (env->xl) {
      case MXL_RV32:

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