Re: [PATCH v3 02/14] util: Add RISC-V vector extension probe in cpuinfo

[Richard Henderson]

On 9/4/24 07:27, LIU Zhiwei wrote:
> +    if (info & CPUINFO_ZVE64X) {
> +        /*
> +         * Get vlenb for Vector: vsetvli rd, x0, e64.
> +         * VLMAX = LMUL * VLEN / SEW.
> +         * The "vsetvli rd, x0, e64" means "LMUL = 1, SEW = 64, rd = VLMAX",
> +         * so "vlenb = VLMAX * 64 / 8".
> +         */
> +        unsigned long vlmax = 0;
> +        asm volatile(".insn i 0x57, 7, %0, zero, (3 << 3)" : "=r"(vlmax));
> +        if (vlmax) {
> +            riscv_vlenb = vlmax * 8;
> +            assert(riscv_vlen >= 64 && !(riscv_vlen & (riscv_vlen - 1)));
> +        } else {
> +            info &= ~CPUINFO_ZVE64X;
> +        }
> +    }

Surely this does not compile, since the riscv_vlen referenced in the assert 
does not exist.

That said, I've done some experimentation and I believe there is a further simplification 
to be had in instead saving log2(vlenb).

    if (info & CPUINFO_ZVE64X) {
        /*
         * We are guaranteed by RVV-1.0 that VLEN is a power of 2.
         * We are guaranteed by Zve64x that VLEN >= 64, and that
         * EEW of {8,16,32,64} are supported.
         *
         * Cache VLEN in a convenient form.
         */
        unsigned long vlenb;
        asm("csrr %0, vlenb" : "=r"(vlenb));
        riscv_lg2_vlenb = ctz32(vlenb);
    }

I'll talk about how this can be used against the next patch with vsetvl.


r~