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[PATCH v2 6/8] target/riscv: Implement Smdbltrp sret, mret and mnret beh
From: |
Clément Léger |
Subject: |
[PATCH v2 6/8] target/riscv: Implement Smdbltrp sret, mret and mnret behavior |
Date: |
Wed, 25 Sep 2024 13:58:04 +0200 |
When the Ssdbltrp extension is enabled, SSTATUS.MDT field is cleared
when executing sret if executed in M-mode. When executing mret/mnret,
SSTATUS.MDT is cleared.
Signed-off-by: Clément Léger <cleger@rivosinc.com>
---
target/riscv/op_helper.c | 12 ++++++++++++
1 file changed, 12 insertions(+)
diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c
index 00b6f75102..9d0911f697 100644
--- a/target/riscv/op_helper.c
+++ b/target/riscv/op_helper.c
@@ -299,6 +299,9 @@ target_ulong helper_sret(CPURISCVState *env)
}
mstatus = set_field(mstatus, MSTATUS_SDT, 0);
}
+ if (riscv_cpu_cfg(env)->ext_smdbltrp && env->priv >= PRV_M) {
+ mstatus = set_field(mstatus, MSTATUS_MDT, 0);
+ }
if (env->priv_ver >= PRIV_VERSION_1_12_0) {
mstatus = set_field(mstatus, MSTATUS_MPRV, 0);
}
@@ -375,6 +378,9 @@ target_ulong helper_mret(CPURISCVState *env)
if (riscv_cpu_cfg(env)->ext_ssdbltrp) {
mstatus = ssdbltrp_mxret(env, mstatus, prev_priv, prev_virt);
}
+ if (riscv_cpu_cfg(env)->ext_smdbltrp) {
+ mstatus = set_field(mstatus, MSTATUS_MDT, 0);
+ }
if ((env->priv_ver >= PRIV_VERSION_1_12_0) && (prev_priv != PRV_M)) {
mstatus = set_field(mstatus, MSTATUS_MPRV, 0);
}
@@ -416,6 +422,12 @@ target_ulong helper_mnret(CPURISCVState *env)
env->mstatus = ssdbltrp_mxret(env, env->mstatus, prev_priv, prev_virt);
}
+ if (riscv_cpu_cfg(env)->ext_smdbltrp) {
+ if (prev_priv < PRV_M) {
+ env->mstatus = set_field(env->mstatus, MSTATUS_MDT, false);
+ }
+ }
+
if (riscv_has_ext(env, RVH) && prev_virt) {
riscv_cpu_swap_hypervisor_regs(env);
}
--
2.45.2
- [PATCH v2 0/8] target/riscv: Add support for Smdbltrp and Ssdbltrp extensions, Clément Léger, 2024/09/25
- [PATCH v2 2/8] target/riscv: Implement Ssdbltrp sret, mret and mnret behavior, Clément Léger, 2024/09/25
- [PATCH v2 3/8] target/riscv: Implement Ssdbltrp exception handling, Clément Léger, 2024/09/25
- [PATCH v2 1/8] target/riscv: Add Ssdbltrp CSRs handling, Clément Léger, 2024/09/25
- [PATCH v2 4/8] target/riscv: Add Ssdbltrp ISA extension enable switch, Clément Léger, 2024/09/25
- [PATCH v2 5/8] target/riscv: Add Smdbltrp CSRs handling, Clément Léger, 2024/09/25
- [PATCH v2 8/8] target/riscv: Add Smdbltrp ISA extension enable switch, Clément Léger, 2024/09/25
- [PATCH v2 7/8] target/riscv: Implement Smdbltrp behavior, Clément Léger, 2024/09/25
- [PATCH v2 6/8] target/riscv: Implement Smdbltrp sret, mret and mnret behavior,
Clément Léger <=