qemu-riscv (date)

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qemu-riscv (date)

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Last Modified: Fri Jun 13 2025 15:37:17 -0400
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June 13, 2025
- Re: [PATCH v2 01/12] python: convert packages to PEP517/pyproject.toml, John Snow, 15:37
- Re: [PATCH v2 05/12] python: fix illegal escape sequences, Thomas Huth, 06:41
- Re: [PATCH v2 02/12] python: update pylint ignores, Thomas Huth, 06:18
- Re: [PATCH v2 01/12] python: convert packages to PEP517/pyproject.toml, Thomas Huth, 04:36
June 12, 2025
- [PATCH v2 12/12] scripts/codeconverter: remove * imports, John Snow, 17:02
- [PATCH v2 11/12] scripts/codeconverter: remove unused code, John Snow, 17:01
- [PATCH v2 10/12] python: remove version restriction for mypy, John Snow, 17:01
- [PATCH v2 09/12] python: update mkvenv to type-check under different python versions, John Snow, 17:00
- [PATCH v2 08/12] python: further 3.9+ syntax upgrades, John Snow, 17:00
- [PATCH v2 07/12] fixup, John Snow, 16:59
- [PATCH v2 06/12] python: upgrade to python3.9+ syntax, John Snow, 16:59
- [PATCH v2 05/12] python: fix illegal escape sequences, John Snow, 16:58
- [PATCH v2 04/12] python: update shebangs to standard, using /usr/bin/env, John Snow, 16:58
- [PATCH v2 03/12] python: sync changes from external qemu.qmp package, John Snow, 16:57
- [PATCH v2 02/12] python: update pylint ignores, John Snow, 16:57
- [PATCH v2 01/12] python: convert packages to PEP517/pyproject.toml, John Snow, 16:56
- [PATCH v2 00/12] Python: Fix 'make check-dev' and modernize to 3.9+, John Snow, 16:56
- [PATCH v3] Add RISCV ZALASR extension, Roan Richmond, 03:55
- Re: [PATCH v2 00/12] hw/riscv/virt: device tree reg cleanups, Alistair Francis, 00:32
June 11, 2025
- Re: [PATCH v2 1/1] Add RISCV ZALASR extension, Alistair Francis, 05:47
- Re: [PATCH v2 0/1] Add RISCV ZALASR Extension, Roan Richmond, 05:37
- Re: [PATCH v2 1/1] Add RISCV ZALASR extension, Roan Richmond, 05:33
- Re: [PATCH v5 00/10] target/i386/kvm/pmu: PMU Enhancement, Bugfix and Cleanup, Dongli Zhang, 04:46
- Re: [PATCH REPOST v4 0/4] acpi: Add machine option to disable SPCR table, Li Chen, 03:44
- Re: [PATCH v2 0/1] Add RISCV ZALASR Extension, Alistair Francis, 00:31
- Re: [PATCH v2 1/1] Add RISCV ZALASR extension, Alistair Francis, 00:29
June 10, 2025
- Re: [PATCH v2 0/9] riscv: Add support for MIPS P8700 CPU, Alistair Francis, 07:42
- Re: [PATCH v2 9/9] hw/riscv: Add a network device e1000e to the boston-aia, Alistair Francis, 07:42
- Re: [PATCH v2 5/9] target/riscv: Add mips.ccmov instruction, Alistair Francis, 07:40
- Re: [PATCH v2 4/9] target/riscv: Add MIPS P8700 CSRs, Alistair Francis, 07:37
- Re: [PATCH v2 2/9] target/riscv: Add cpu_set_exception_base, Alistair Francis, 07:30
- [PATCH v2 1/1] Add RISCV ZALASR extension, Roan Richmond, 04:33
- [PATCH v2 0/1] Add RISCV ZALASR Extension, Roan Richmond, 04:33
- Re: [PATCH v2 8/9] configs/devices: Add MIPS Boston-aia board model to RISC-V, Philippe Mathieu-Daudé, 03:46
- Re: [PATCH v2 2/9] target/riscv: Add cpu_set_exception_base, Philippe Mathieu-Daudé, 03:44
- Re: [PATCH v2 4/9] target/riscv: Add MIPS P8700 CSRs, Philippe Mathieu-Daudé, 03:41
- Re: [PATCH v2 3/9] target/riscv: Add MIPS P8700 CPU, Philippe Mathieu-Daudé, 03:38
- Re: [PATCH v2 1/9] hw/intc: Allow gaps in hartids for aclint and aplic, Philippe Mathieu-Daudé, 03:34
June 09, 2025
- Re: [PATCH v3 3/3] hw/riscv: set cva6 to use TYPE_RISCV_CPU_CVA6, Alistair Francis, 19:31
- Re: [PATCH v3 2/3] target/riscv: add cva6 core type, Alistair Francis, 19:30
- Re: [PATCH v3 1/3] hw/riscv: add CVA6 machine, Alistair Francis, 19:30
- Re: Public Review : RISC-V Supervisor Binary Interface (SBI) version v3.0, Atish Patra, 19:09
- [PATCH v3 1/3] hw/riscv: add CVA6 machine, Ben Dooks, 09:17
- [PATCH v3 3/3] hw/riscv: set cva6 to use TYPE_RISCV_CPU_CVA6, Ben Dooks, 09:17
- RISC-V: Add CVA6 machine, Ben Dooks, 09:17
- [PATCH v3 2/3] target/riscv: add cva6 core type, Ben Dooks, 09:17
- Re: [PATCH v2 2/3] target/riscv: add cva6 core type, Daniel Henrique Barboza, 08:31
- Re: [PATCH v2 2/3] target/riscv: add cva6 core type, Daniel Henrique Barboza, 08:28
- Re: [PATCH v5 00/10] target/i386/kvm/pmu: PMU Enhancement, Bugfix and Cleanup, Zhao Liu, 08:05
- Re: [PATCH v2 1/3] hw/riscv: add CVA6 machine, Daniel Henrique Barboza, 08:03
- Re: [PATCH v2 2/3] target/riscv: add cva6 core type, Ben Dooks, 07:59
- Re: [PATCH v2 2/3] target/riscv: add cva6 core type, Ben Dooks, 07:47
- Re: [PATCH v2 1/3] hw/riscv: add CVA6 machine, Ben Dooks, 07:33
- Re: [PATCH v2 2/3] target/riscv: add cva6 core type, Daniel Henrique Barboza, 07:30
- Re: [PATCH v2 1/3] hw/riscv: add CVA6 machine, Daniel Henrique Barboza, 07:24
- Re: [PATCH v2 2/3] target/riscv: add cva6 core type, Ben Dooks, 06:40
- Re: [PATCH] hw/char: sifive_uart: Avoid infinite delay of async xmit function, Alistair Francis, 01:27
- Re: [PATCH] hw/char: sifive_uart: Avoid infinite delay of async xmit function, Alistair Francis, 01:05
- Re: [PATCH v2] target/riscv: Fix fcvt.s.bf16 NaN box checking, Alistair Francis, 01:02
- Re: [PATCH v2] target/riscv: Fix fcvt.s.bf16 NaN box checking, Alistair Francis, 00:28
- Re: [PATCH v4 2/2] hw/riscv: Initial support for BOSC's Xiangshan Kunminghu FPGA prototype, Alistair Francis, 00:27
- Re: [PATCH v5 0/1] fix the way riscv_plic_hart_config_string() gets the CPUState, Alistair Francis, 00:27
- Re: [PATCH v5 1/1] hw/riscv: fix PLIC hart topology configuration string when not getting CPUState correctly, Alistair Francis, 00:16
- Re: [PATCH v2 0/1] riscv: qemu_chr_fe_write_all() in CONSOLE_WRITE_BYTE, Alistair Francis, 00:04
June 08, 2025
- Re: [PATCH v4 5/5] hw/riscv/riscv-iommu: Remove definition of RISCVIOMMU[Pci|Sys]Class, Alistair Francis, 23:43
- Re: [PATCH v2] hw/riscv/riscv-iommu: Fix PPN field of Translation-reponse register, Alistair Francis, 23:42
- Re: [PATCH v5 2/2] target/riscv: Make PMP region count configurable, Alistair Francis, 23:05
- Re: [PATCH v5 2/2] target/riscv: Make PMP region count configurable, Alistair Francis, 22:47
- Re: [PATCH v6] target/riscv/kvm: add max_satp_mode from host cpu, Alistair Francis, 22:41
June 07, 2025
- Re: Add initial CVA6 implementaiton, Daniel Henrique Barboza, 16:23
- Re: [PATCH v2 2/3] target/riscv: add cva6 core type, Daniel Henrique Barboza, 16:17
- Re: [PATCH] target: riscv: Add Svrsw60t59b extension support, Daniel Henrique Barboza, 13:54
- [PATCH v5 1/1] hw/riscv: fix PLIC hart topology configuration string when not getting CPUState correctly, Chao Liu, 01:20
- [PATCH v5 0/1] fix the way riscv_plic_hart_config_string() gets the CPUState, Chao Liu, 01:20
June 06, 2025
- Re: [PATCH] target: riscv: Add Svrsw60t59b extension support, Deepak Gupta, 12:34
- [PATCH v4 5/5] hw/riscv/riscv-iommu: Remove definition of RISCVIOMMU[Pci|Sys]Class, Zhenzhong Duan, 05:28
- [PATCH v5 2/2] target/riscv: Make PMP region count configurable, Jay Chang, 03:28
- [PATCH v5 1/2] target/riscv: Extend PMP region up to 64, Jay Chang, 03:25
- [PATCH v5 0/2] Extend and configure PMP region count, Jay Chang, 03:25
June 05, 2025
- [PATCH v6] target/riscv/kvm: add max_satp_mode from host cpu, Meng Zhuo, 23:44
- [PATCH] target: riscv: Add Svrsw60t59b extension support, Alexandre Ghiti, 10:21
- Re: [PATCH v3 5/5] hw/riscv/riscv-iommu: Remove definition of RISCVIOMMU[Pci|Sys]Class, Daniel Henrique Barboza, 09:24
- [PATCH v2] hw/riscv/riscv-iommu: Fix PPN field of Translation-reponse register, Nutty Liu, 08:49
- Re: [PATCH] hw/riscv/riscv-iommu: Fix PPN field of Translation-reponse register, Nutty Liu, 07:57
- [PATCH v3 5/5] hw/riscv/riscv-iommu: Remove definition of RISCVIOMMU[Pci|Sys]Class, Zhenzhong Duan, 06:27
- [PATCH] hw/char: sifive_uart: Avoid infinite delay of async xmit function, Florian Lugou, 06:14
- Re: [PATCH] target/riscv/kvm: use qemu_chr_fe_write_all() in SBI_EXT_DBCN_CONSOLE_WRITE_BYTE, Daniel Henrique Barboza, 05:46
- [PATCH v2 0/1] riscv: qemu_chr_fe_write_all() in CONSOLE_WRITE_BYTE, Daniel Henrique Barboza, 05:45
- [PATCH v2 1/1] target/riscv: use qemu_chr_fe_write_all() in DBCN_CONSOLE_WRITE_BYTE, Daniel Henrique Barboza, 05:45
- [PATCH v3 3/3] target/riscv/cpu.c: do better with 'named features' doc, Daniel Henrique Barboza, 05:29
- [PATCH v3 2/3] target/riscv/cpu.c: add 'ssstrict' to riscv,isa, Daniel Henrique Barboza, 05:29
- [PATCH v3 1/3] target/riscv/cpu.c: add 'sdtrig' in riscv,isa, Daniel Henrique Barboza, 05:28
- [PATCH v3 0/3] target/riscv: add missing named features, Daniel Henrique Barboza, 05:28
- Re: [PATCH] target/riscv/kvm: use qemu_chr_fe_write_all() in SBI_EXT_DBCN_CONSOLE_WRITE_BYTE, Philippe Mathieu-Daudé, 05:26
- [PATCH] target/riscv/kvm: use qemu_chr_fe_write_all() in SBI_EXT_DBCN_CONSOLE_WRITE_BYTE, Daniel Henrique Barboza, 05:00
- Re: [PATCH 0/3] Fix some more RVV source overlap issues, Max Chou, 03:55
- Re: [PATCH v4 2/2] target/riscv: Make PMP region count configurable, Alistair Francis, 02:39
- Re: [PATCH v2] target/riscv: support atomic instruction fetch (Ziccif), Alistair Francis, 02:38
- Re: [PATCH v4 2/2] target/riscv: Make PMP region count configurable, Jay Chang, 01:33
- Re: [PATCH v2] target/riscv: support atomic instruction fetch (Ziccif), Alistair Francis, 00:22
June 04, 2025
- Re: [PATCH RESEND v2 3/3] target/riscv/cpu.c: do better with 'named features' doc, Alistair Francis, 23:44
- Re: [PATCH v2 2/3] target/riscv/tcg: decouple profile enablement from user prop, Alistair Francis, 23:43
- Re: [PATCH RESEND v2 1/3] target/riscv/cpu.c: add 'sdtrig' in riscv, isa, Alistair Francis, 23:37
- Re: [PATCH v4 1/1] hw/riscv: fix PLIC hart topology configuration string when not getting CPUState correctly, Daniel Henrique Barboza, 16:11
- Re: [PATCH v4 2/2] target/riscv: Make PMP region count configurable, Daniel Henrique Barboza, 14:21
- Re: [PATCH v2 0/3] target/riscv: add missing named features, Daniel Henrique Barboza, 13:45
- [PATCH RESEND v2 3/3] target/riscv/cpu.c: do better with 'named features' doc, Daniel Henrique Barboza, 13:44
- [PATCH RESEND v2 1/3] target/riscv/cpu.c: add 'sdtrig' in riscv,isa, Daniel Henrique Barboza, 13:44
- [PATCH RESEND v2 2/3] target/riscv/cpu.c: add 'ssstrict' to riscv, isa, Daniel Henrique Barboza, 13:43
- [PATCH RESEND v2 0/3] target/riscv: add missing named features, Daniel Henrique Barboza, 13:43
- [PATCH v2 3/3] target/riscv: add profile->present flag, Daniel Henrique Barboza, 13:38
- [PATCH v2 3/3] target/riscv/cpu.c: do better with 'named features' doc, Daniel Henrique Barboza, 13:38
- [PATCH v2 2/3] target/riscv/tcg: decouple profile enablement from user prop, Daniel Henrique Barboza, 13:38
- [PATCH v2 2/3] target/riscv/cpu.c: add 'ssstrict' to riscv,isa, Daniel Henrique Barboza, 13:38
- [PATCH v2 1/3] target/riscv/tcg: restrict satp_mode changes in cpu_set_profile, Daniel Henrique Barboza, 13:38
- [PATCH v2 1/3] target/riscv/cpu.c: add 'sdtrig' in riscv,isa, Daniel Henrique Barboza, 13:38
- [PATCH v2 0/3] target/riscv: add missing named features, Daniel Henrique Barboza, 13:38
- Re: [qemu PATCH 0/3] target/riscv: add missing named features, Daniel Henrique Barboza, 10:16
- [PATCH v2 5/5] hw/riscv/riscv-iommu: Remove definition of RISCVIOMMU[Pci|Sys]Class, Zhenzhong Duan, 08:50
- Re: [PATCH] target/riscv/kvm: implement SBI debug console (DBCN) calls, Daniel Henrique Barboza, 06:54
- Re: [PATCH] target/riscv/kvm: implement SBI debug console (DBCN) calls, Daniel P . Berrangé, 05:50
- [PATCH v2] Add RISCV ZALASR extension, Roan Richmond, 05:40
- Re: [PATCH] target/riscv/kvm: implement SBI debug console (DBCN) calls, Philippe Mathieu-Daudé, 05:38
- Re: [PATCH] target/riscv/kvm: implement SBI debug console (DBCN) calls, Daniel Henrique Barboza, 05:17
- Re: [PATCH] target/riscv/kvm: implement SBI debug console (DBCN) calls, Philippe Mathieu-Daudé, 03:32
June 03, 2025
- [PATCH v2 12/12] hw/riscv/virt: Use setprop_sized_cells for pcie, Joel Stanley, 22:56
- [PATCH v2 11/12] hw/riscv/virt: Use setprop_sized_cells for iommu, Joel Stanley, 22:56
- [PATCH v2 10/12] hw/riscv/virt: Use setprop_sized_cells for rtc, Joel Stanley, 22:56
- [PATCH v2 09/12] hw/riscv/virt: Use setprop_sized_cells for uart, Joel Stanley, 22:56
- [PATCH v2 08/12] hw/riscv/virt: Use setprop_sized_cells for reset, Joel Stanley, 22:56
- [PATCH v2 07/12] hw/riscv/virt: Use setprop_sized_cells for virtio, Joel Stanley, 22:56
- [PATCH v2 06/12] hw/riscv/virt: Use setprop_sized_cells for plic, Joel Stanley, 22:56
- [PATCH v2 05/12] hw/riscv/virt: Use setprop_sized_cells for aclint, Joel Stanley, 22:56
- [PATCH v2 04/12] hw/riscv/virt: Use setprop_sized_cells for aplic, Joel Stanley, 22:56
- [PATCH v2 03/12] hw/riscv/virt: Use setprop_sized_cells for memory, Joel Stanley, 22:56
- [PATCH v2 02/12] hw/riscv/virt: Use setprop_sized_cells for clint, Joel Stanley, 22:56
- [PATCH v2 01/12] hw/riscv/virt: Fix clint base address type, Joel Stanley, 22:56
- [PATCH v2 00/12] hw/riscv/virt: device tree reg cleanups, Joel Stanley, 22:56
- Re: [PATCH] target/riscv/kvm: implement SBI debug console (DBCN) calls, Daniel Henrique Barboza, 14:04
- Re: [PATCH] target/riscv/kvm: implement SBI debug console (DBCN) calls, Philippe Mathieu-Daudé, 09:19
- Re: [PATCH] hw/riscv/riscv-iommu: Fix PPN field of Translation-reponse register, Nutty Liu, 04:02
- Re: [PATCH] hw/riscv/riscv-iommu: Fix PPN field of Translation-reponse register, liu, 00:42
- RE: [PATCH v2 2/2] target/riscv: Support matching scontext in Sdtrig's textra CSRs, 張哲嘉, 00:32
June 02, 2025
- [PATCH v2 9/9] hw/riscv: Add a network device e1000e to the boston-aia, Djordje Todorovic, 09:25
- [PATCH v2 0/9] riscv: Add support for MIPS P8700 CPU, Djordje Todorovic, 09:24
- [PATCH v2 3/9] target/riscv: Add MIPS P8700 CPU, Djordje Todorovic, 09:24
- [PATCH v2 1/9] hw/intc: Allow gaps in hartids for aclint and aplic, Djordje Todorovic, 09:24
- [PATCH v2 5/9] target/riscv: Add mips.ccmov instruction, Djordje Todorovic, 09:24
- [PATCH v2 2/9] target/riscv: Add cpu_set_exception_base, Djordje Todorovic, 09:24
- [PATCH v2 4/9] target/riscv: Add MIPS P8700 CSRs, Djordje Todorovic, 09:24
- [PATCH v2 8/9] configs/devices: Add MIPS Boston-aia board model to RISC-V, Djordje Todorovic, 09:24
- [PATCH v2 6/9] target/riscv: Add mips.pref instruction, Djordje Todorovic, 09:24
- [PATCH v2 7/9] target/riscv: Add Xmipslsp instructions, Djordje Todorovic, 09:24
- Re: [PATCH v4 01/27] hw/i386/pc: Remove deprecated pc-q35-2.6 and pc-i440fx-2.6 machines, Igor Mammedov, 06:26
- Re: [PATCH v2] target/riscv: support atomic instruction fetch (Ziccif), Jim Shu, 04:55
- Re: [PATCH v4 01/27] hw/i386/pc: Remove deprecated pc-q35-2.6 and pc-i440fx-2.6 machines, Philippe Mathieu-Daudé, 04:53
- Re: [PATCH v4 01/27] hw/i386/pc: Remove deprecated pc-q35-2.6 and pc-i440fx-2.6 machines, Thomas Huth, 02:16
- Re: [PATCH 1/1] Add RISCV ZALASR extension, Alistair Francis, 02:11
- Re: [qemu PATCH 3/3] target/riscv/cpu.c: do better with 'named features' doc, Alistair Francis, 02:08
- Re: [qemu PATCH 2/3] target/riscv/cpu.c: add 'ssstrict' to riscv,isa, Alistair Francis, 02:07
- Re: [PATCH v4 1/2] target/riscv: Add BOSC's Xiangshan Kunminghu CPU, Alistair Francis, 02:00
- Re: [qemu PATCH 1/3] target/riscv/cpu.c: add 'sdtrig' in riscv,isa, Alistair Francis, 01:48
- Re: [PATCH] hw/riscv/riscv-iommu: Fix PPN field of Translation-reponse register, Alistair Francis, 01:46
- Re: [qemu PATCH 0/3] target/riscv: add missing named features, Alistair Francis, 01:46
- Re: [PATCH v4 1/1] hw/riscv: fix PLIC hart topology configuration string when not getting CPUState correctly, Alistair Francis, 01:46
- Re: [PATCH v5] target/riscv/kvm: add satp mode for host cpu, Alistair Francis, 00:03
June 01, 2025
- Re: [PATCH] target/riscv: remove capital 'Z' CPU properties, Alistair Francis, 20:56
- Re: [PATCH] target/riscv: remove capital 'Z' CPU properties, Alistair Francis, 20:53

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