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[PATCH v1 06/20] s390x/tcg: Implement 32/128 bit for VECTOR FP MULTIPLY
From: |
David Hildenbrand |
Subject: |
[PATCH v1 06/20] s390x/tcg: Implement 32/128 bit for VECTOR FP MULTIPLY |
Date: |
Wed, 30 Sep 2020 16:55:09 +0200 |
Just like VECTOR FP ADD.
Signed-off-by: David Hildenbrand <david@redhat.com>
---
target/s390x/helper.h | 3 +++
target/s390x/translate_vx.c.inc | 18 +++++++++++++++++-
target/s390x/vec_fpu_helper.c | 28 +++++++++++++++-------------
3 files changed, 35 insertions(+), 14 deletions(-)
diff --git a/target/s390x/helper.h b/target/s390x/helper.h
index 3dfd480fc1..a7a902ed9c 100644
--- a/target/s390x/helper.h
+++ b/target/s390x/helper.h
@@ -285,8 +285,11 @@ DEF_HELPER_FLAGS_4(gvec_vfll32, TCG_CALL_NO_WG, void, ptr,
cptr, env, i32)
DEF_HELPER_FLAGS_4(gvec_vfll32s, TCG_CALL_NO_WG, void, ptr, cptr, env, i32)
DEF_HELPER_FLAGS_4(gvec_vflr64, TCG_CALL_NO_WG, void, ptr, cptr, env, i32)
DEF_HELPER_FLAGS_4(gvec_vflr64s, TCG_CALL_NO_WG, void, ptr, cptr, env, i32)
+DEF_HELPER_FLAGS_5(gvec_vfm32, TCG_CALL_NO_WG, void, ptr, cptr, cptr, env, i32)
+DEF_HELPER_FLAGS_5(gvec_vfm32s, TCG_CALL_NO_WG, void, ptr, cptr, cptr, env,
i32)
DEF_HELPER_FLAGS_5(gvec_vfm64, TCG_CALL_NO_WG, void, ptr, cptr, cptr, env, i32)
DEF_HELPER_FLAGS_5(gvec_vfm64s, TCG_CALL_NO_WG, void, ptr, cptr, cptr, env,
i32)
+DEF_HELPER_FLAGS_5(gvec_vfm128, TCG_CALL_NO_WG, void, ptr, cptr, cptr, env,
i32)
DEF_HELPER_FLAGS_6(gvec_vfma64, TCG_CALL_NO_WG, void, ptr, cptr, cptr, cptr,
env, i32)
DEF_HELPER_FLAGS_6(gvec_vfma64s, TCG_CALL_NO_WG, void, ptr, cptr, cptr, cptr,
env, i32)
DEF_HELPER_FLAGS_6(gvec_vfms64, TCG_CALL_NO_WG, void, ptr, cptr, cptr, cptr,
env, i32)
diff --git a/target/s390x/translate_vx.c.inc b/target/s390x/translate_vx.c.inc
index ea1b2732bc..65385ce5ee 100644
--- a/target/s390x/translate_vx.c.inc
+++ b/target/s390x/translate_vx.c.inc
@@ -2546,7 +2546,23 @@ static DisasJumpType op_vfa(DisasContext *s, DisasOps *o)
}
break;
case 0xe7:
- fn = se ? gen_helper_gvec_vfm64s : gen_helper_gvec_vfm64;
+ switch (fpf) {
+ case FPF_SHORT:
+ if (s390_has_feat(S390_FEAT_VECTOR_ENH)) {
+ fn = se ? gen_helper_gvec_vfm32s : gen_helper_gvec_vfm32;
+ }
+ break;
+ case FPF_LONG:
+ fn = se ? gen_helper_gvec_vfm64s : gen_helper_gvec_vfm64;
+ break;
+ case FPF_EXT:
+ if (s390_has_feat(S390_FEAT_VECTOR_ENH)) {
+ fn = gen_helper_gvec_vfm128;
+ }
+ break;
+ default:
+ break;
+ }
break;
case 0xe2:
fn = se ? gen_helper_gvec_vfs64s : gen_helper_gvec_vfs64;
diff --git a/target/s390x/vec_fpu_helper.c b/target/s390x/vec_fpu_helper.c
index cfa143b62a..335d540622 100644
--- a/target/s390x/vec_fpu_helper.c
+++ b/target/s390x/vec_fpu_helper.c
@@ -531,22 +531,24 @@ void HELPER(gvec_vflr64s)(void *v1, const void *v2,
CPUS390XState *env,
vflr64(v1, v2, env, true, XxC, erm, GETPC());
}
-static uint64_t vfm64(uint64_t a, uint64_t b, float_status *s)
-{
- return float64_mul(a, b, s);
-}
-
-void HELPER(gvec_vfm64)(void *v1, const void *v2, const void *v3,
- CPUS390XState *env, uint32_t desc)
-{
- vop64_3(v1, v2, v3, env, false, vfm64, GETPC());
+#define DEF_GVEC_FVM(BITS)
\
+void HELPER(gvec_vfm##BITS)(void *v1, const void *v2, const void *v3,
\
+ CPUS390XState *env, uint32_t desc)
\
+{
\
+ vop##BITS##_3(v1, v2, v3, env, false, float##BITS##_mul, GETPC());
\
}
+DEF_GVEC_FVM(32)
+DEF_GVEC_FVM(64)
+DEF_GVEC_FVM(128)
-void HELPER(gvec_vfm64s)(void *v1, const void *v2, const void *v3,
- CPUS390XState *env, uint32_t desc)
-{
- vop64_3(v1, v2, v3, env, true, vfm64, GETPC());
+#define DEF_GVEC_FVM_S(BITS)
\
+void HELPER(gvec_vfm##BITS##s)(void *v1, const void *v2, const void *v3,
\
+ CPUS390XState *env, uint32_t desc)
\
+{
\
+ vop##BITS##_3(v1, v2, v3, env, true, float##BITS##_mul, GETPC());
\
}
+DEF_GVEC_FVM_S(32)
+DEF_GVEC_FVM_S(64)
static void vfma64(S390Vector *v1, const S390Vector *v2, const S390Vector *v3,
const S390Vector *v4, CPUS390XState *env, bool s, int flags,
--
2.26.2
- [PATCH v1 00/20] s390x/tcg: Implement Vector enhancements facility and switch to z14, David Hildenbrand, 2020/09/30
- [PATCH v1 01/20] softfloat: Implement float128_(min|minnum|minnummag|max|maxnum|maxnummag), David Hildenbrand, 2020/09/30
- [PATCH v1 03/20] s390x/tcg: Implement VECTOR MULTIPLY SUM LOGICAL, David Hildenbrand, 2020/09/30
- [PATCH v1 05/20] s390x/tcg: Implement 32/128 bit for VECTOR FP DIVIDE, David Hildenbrand, 2020/09/30
- [PATCH v1 02/20] s390x/tcg: Implement VECTOR BIT PERMUTE, David Hildenbrand, 2020/09/30
- [PATCH v1 04/20] s390x/tcg: Implement 32/128 bit for VECTOR FP ADD, David Hildenbrand, 2020/09/30
- [PATCH v1 06/20] s390x/tcg: Implement 32/128 bit for VECTOR FP MULTIPLY,
David Hildenbrand <=
- [PATCH v1 08/20] s390x/tcg: Implement 32/128 bit for VECTOR FP COMPARE (AND SIGNAL) SCALAR, David Hildenbrand, 2020/09/30
- [PATCH v1 07/20] s390x/tcg: Implement 32/128 bit for VECTOR FP SUBTRACT, David Hildenbrand, 2020/09/30
- [PATCH v1 10/20] s390x/tcg: Implement 32/128 bit for VECTOR LOAD FP INTEGER, David Hildenbrand, 2020/09/30
- [PATCH v1 09/20] s390x/tcg: Implement 32/128 bit for VECTOR FP COMPARE *, David Hildenbrand, 2020/09/30
- [PATCH v1 11/20] s390x/tcg: Implement 64 bit for VECTOR FP LOAD LENGTHENED, David Hildenbrand, 2020/09/30
- [PATCH v1 12/20] s390x/tcg: Implement 128 bit for VECTOR FP LOAD ROUNDED, David Hildenbrand, 2020/09/30
- [PATCH v1 13/20] s390x/tcg: Implement 32/128 bit for VECTOR FP PERFORM SIGN OPERATION, David Hildenbrand, 2020/09/30
- [PATCH v1 14/20] s390x/tcg: Implement 32/128 bit for VECTOR FP SQUARE ROOT, David Hildenbrand, 2020/09/30
- [PATCH v1 16/20] s390x/tcg: Implement 32/128bit for VECTOR FP MULTIPLY AND (ADD|SUBTRACT), David Hildenbrand, 2020/09/30
- [PATCH v1 15/20] s390x/tcg: Implement 32/128 bit for VECTOR FP TEST DATA CLASS IMMEDIATE, David Hildenbrand, 2020/09/30