Re: [Simulavr-devel] spi test

[Onno Kortmann]

Hi,

I am also trying to use the SPI code, as I was trying to write a small example 
simulavr-verilog SPI interface.
Maybe someone with knowledge of the SPI sim code can chime in; I found several 
parts in the code
which looked quite strange to me (and caused some problems, at least in my 
patched simulavrxx version):

1. AddToCycleList/RemoveFromCycleList is still not done properly in CVS HEAD. 
What is the result of the
   discussions in the "ATMega48 Crash" thread? I also like to mention here that 
my patch for 
   similar issues in the timer is still pending! :-)

2. for me, SPI transfers stop somewhere in the first bit. I looked into the 
CPUCycle code and found the following
   nested checks:

  if (( clkCnt%(clkDiv/4))==0) {
            switch( state) {
                case READY:
                    break;
        [...]

and then, inside this switch, case 'BIT_MASTER', further down:

 if ( spcr & CPHA) { //==1
                            switch (clkCnt%(clkDiv/4)) {

which as far as I can see puts the SPI into idle before anything has been 
transmitted as Master.


Greetings,

Onno