From MAILER-DAEMON Tue Aug 01 00:32:43 2017 Received: from list by lists.gnu.org with archive (Exim 4.71) id 1dcOrL-0000CA-BO for mharc-qemu-arm@gnu.org; Tue, 01 Aug 2017 00:32:43 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:35737) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dcOrF-0000C1-Ly for qemu-arm@nongnu.org; Tue, 01 Aug 2017 00:32:41 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dcOrA-0001mo-Fi for qemu-arm@nongnu.org; Tue, 01 Aug 2017 00:32:37 -0400 Received: from out1-smtp.messagingengine.com ([66.111.4.25]:56319) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1dcOr9-0001l8-PK; Tue, 01 Aug 2017 00:32:32 -0400 Received: from compute4.internal (compute4.nyi.internal [10.202.2.44]) by mailout.nyi.internal (Postfix) with ESMTP id B78A8207CC; Tue, 1 Aug 2017 00:32:30 -0400 (EDT) Received: from frontend2 ([10.202.2.161]) by compute4.internal (MEProxy); Tue, 01 Aug 2017 00:32:30 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=aj.id.au; h=cc :content-type:date:from:in-reply-to:message-id:mime-version :references:subject:to:x-me-sender:x-me-sender:x-sasl-enc :x-sasl-enc; s=fm1; bh=vVbHIfMce1OQFj3hTh0ONX+J4bBAVyxdoZ5bmgJE8 h8=; b=Mr0XaaADXk/RUmHCQKXFVMthktgdu9VaXIXp7FBMuNHgbQsn42xNdHYXw tg+e0zNDM5oTRdoNqfN+cMuH2koVLgzztj7xFpuffRXEDJXM88i7Sc5CvIZ4WNfz GTyzWJcPrm/oFhg0OxcOdYg6tGO5GRL5sG6GXHmhE68Tzv8WPrsjzPoq/iwNaSQ2 lRXnDoPCkibby2WmafwYo163lceZGVIut36JhJfP2FBffcronHB1tB0TUOLkgZs3 PKSz4NlJmrtVTX+tRqphu8ujgaf6CUBwOLOI+0H+l6CL2pMO/xZVLSqeVk/Kagcl 8nXCK5LeGxBmS8QZVyKV5XxQmATrw== DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d= messagingengine.com; h=cc:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to:x-me-sender :x-me-sender:x-sasl-enc:x-sasl-enc; s=fm1; bh=vVbHIfMce1OQFj3hTh 0ONX+J4bBAVyxdoZ5bmgJE8h8=; b=gZhMoiPAppK6iXcAvHo9wc9CpBTvWHfGvv T9yiN8i507uLbVh7DGXqssqdVXUOWWDDvo77AysQP9+d6slKrTu1iwVfqpNYN+Nt T5abYNiNSieSit1gW4EZDqy9ZsN46QWdmfcstp8UJlAUInUVBjAPOoOv5SG3A0qS z9S1APe3wJRuefJLaQ9pIcWJBH1VkC1PldHYAzB36SlCYE0thCuid1dRiCXD+Wsu 1XWx7TP26jKn3w+bIXXJG2XQ6iGZT2+/gvzvsHhwi59MviA3vMLKPgPo4QKjZlIi wpXceCSajvIg7rU225osUdGdq93vLL5j9cKEXMzh2aSZ0JaGoavA== X-ME-Sender: X-Sasl-enc: hqCEd+BsptKOYX4w9/1Vkmy2vgeUHg2ykbKFly4OFpXn 1501561949 Received: from keelia (ppp118-210-176-216.bras2.adl6.internode.on.net [118.210.176.216]) by mail.messagingengine.com (Postfix) with ESMTPA id CB39D24604; Tue, 1 Aug 2017 00:32:27 -0400 (EDT) Message-ID: <1501561942.5179.34.camel@aj.id.au> From: Andrew Jeffery To: Philippe =?ISO-8859-1?Q?Mathieu-Daud=E9?= , qemu-arm@nongnu.org Cc: peter.maydell@linaro.org, openbmc@lists.ozlabs.org, qemu-devel@nongnu.org, joel@jms.id.au, clg@kaod.org Date: Tue, 01 Aug 2017 14:02:22 +0930 In-Reply-To: References: <20170801010425.25778-1-andrew@aj.id.au> Content-Type: multipart/signed; micalg="pgp-sha512"; protocol="application/pgp-signature"; boundary="=-mw8h11HAz22QEgQhmKe5" X-Mailer: Evolution 3.22.6-1ubuntu1 Mime-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 66.111.4.25 Subject: Re: [Qemu-arm] [PATCH] watchdog: wdt_aspeed: Add support for the reset width register X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 01 Aug 2017 04:32:41 -0000 --=-mw8h11HAz22QEgQhmKe5 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Hi Phil, On Tue, 2017-08-01 at 00:23 -0300, Philippe Mathieu-Daud=C3=A9 wrote: > Hi Andrew, >=20 > On 07/31/2017 10:04 PM, Andrew Jeffery wrote: > > The reset width register controls how the pulse on the SoC's WDTRST{1,2= } > > pins behaves. A pulse is emitted if the external reset bit is set in > > WDT_CTRL. WDT_RESET_WIDTH requires magic bit patterns to configure both > > push-pull/open-drain and active-high/active-low behaviours and thus > > needs some special handling in the write path. >=20 > I wanted to verify the datashit but it seems to unavailable, looking ther= e: > https://www.verical.com/datasheet/aspeed-technology-inc-interface-misc-as= t2050a3-gp-4078885.pdf >=20 > Can you point out which cpu model you are modeling and where to get this= =C2=A0 > watchdog datashit please? You might also add this to the header, for the= =C2=A0 > next one looking at this file :) The watchdog model is common to at least the Aspeed AST2400- and AST2500- SoC families, which I have datasheets for. However, they are not available to the public and therefore (unfortunately) I can't point you to them. You may be able to access them if you have appropriate arrangements with Aspeed. Regarding the features exposed by the patch, configuration of the electrical properties of the external reset signal is only provided in the AST2500's watchdog IP, but the bits used in the reset width register are marked as reserved on the AST2400. Therefore I thought it was reasonable not to guard them behind some kind of revision test. >=20 > >=20 > > > > Signed-off-by: Andrew Jeffery > > --- > > I understand that we're in stabilisation mode, but I thought I'd send t= his out > > to provoke any feedback. Happy to resend after the 2.10 release if requ= ired. >=20 > you can subject it "PATCH for 2.11" so ppl testing/closing 2.10 can keep= =C2=A0 > focused but still queue your mail for when 2.10 release is out. Thanks for the tip. >=20 > >=20 > > =C2=A0 hw/watchdog/wdt_aspeed.c | 47 ++++++++++++++++++++++++++++++++++= +++---------- > > =C2=A0 1 file changed, 37 insertions(+), 10 deletions(-) > >=20 > > diff --git a/hw/watchdog/wdt_aspeed.c b/hw/watchdog/wdt_aspeed.c > > index 8bbe579b6b66..4ef1412e99fc 100644 > > --- a/hw/watchdog/wdt_aspeed.c > > +++ b/hw/watchdog/wdt_aspeed.c > > @@ -14,10 +14,10 @@ > > =C2=A0 #include "qemu/timer.h" > > =C2=A0 #include "hw/watchdog/wdt_aspeed.h" > > =C2=A0=C2=A0 > > -#define WDT_STATUS=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0(0x00 / 4) > > -#define WDT_RELOAD_VALUE=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0(0x04 / 4) > > -#define WDT_RESTART=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0=C2=A0=C2=A0(0x08 / 4) > > -#define WDT_CTRL=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0(0x0C / 4) > > +#define WDT_STATUS=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0(0x00 / 4) > > +#define WDT_RELOAD_VALUE=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0(0x04 / 4) > > +#define WDT_RESTART=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= (0x08 / 4) > > +#define WDT_CTRL=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0(0x0C / 4) > > =C2=A0 #define=C2=A0=C2=A0=C2=A0WDT_CTRL_RESET_MODE_SOC=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0=C2=A0=C2=A0(0x00 << 5) > > =C2=A0 #define=C2=A0=C2=A0=C2=A0WDT_CTRL_RESET_MODE_FULL_CHIP (0x01 << = 5) > > =C2=A0 #define=C2=A0=C2=A0=C2=A0WDT_CTRL_1MHZ_CLK=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0BIT(4) > > @@ -25,12 +25,21 @@ > > =C2=A0 #define=C2=A0=C2=A0=C2=A0WDT_CTRL_WDT_INTR=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0BIT(2) > > =C2=A0 #define=C2=A0=C2=A0=C2=A0WDT_CTRL_RESET_SYSTEM=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0BIT(1) > > =C2=A0 #define=C2=A0=C2=A0=C2=A0WDT_CTRL_ENABLE=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0BIT(0) > > +#define WDT_RESET_WIDTH=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0(0x18 / 4) > > +#define=C2=A0=C2=A0=C2=A0WDT_RESET_WIDTH_ACTIVE_HIGH=C2=A0=C2=A0=C2=A0= BIT(31) > > +#define=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0WDT_POLARITY_MASK=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0(0xFF << 24) > > +#define=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0WDT_ACTIVE_HIGH_MAGIC=C2=A0=C2=A0= =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0(0xA5 << 24) > > +#define=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0WDT_ACTIVE_LOW_MAGIC=C2=A0=C2=A0= =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0(0x5A << 24) > > +#define=C2=A0=C2=A0=C2=A0WDT_RESET_WIDTH_PUSH_PULL=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0BIT(30) > > +#define=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0WDT_DRIVE_TYPE_MASK=C2=A0=C2=A0= =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0(0xFF << 24) > > +#define=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0WDT_PUSH_PULL_MAGIC=C2=A0=C2=A0= =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0(0xA8 << 24) > > +#define=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0WDT_OPEN_DRAIN_MAGIC=C2=A0=C2=A0= =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0(0x8A << 24) > > +#define=C2=A0=C2=A0=C2=A0WDT_RESET_WIDTH_DURATION=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A00xFFF; >=20 > Which model? the AST2050 seems to be 0xff. Ah, good catch, this is also the case in the AST2400. The AST2500 extends this field. Host code for the AST2400 and AST2050 *shouldn't* set any greater values; is it worth enforcing? >=20 > > =C2=A0=C2=A0 > > -#define WDT_TIMEOUT_STATUS=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0(0x10 / = 4) > > -#define WDT_TIMEOUT_CLEAR=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0(0x= 14 / 4) > > -#define WDT_RESET_WDITH=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0(0x18 / 4) > > +#define WDT_TIMEOUT_STATUS=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0(0x10 / 4) > > +#define WDT_TIMEOUT_CLEAR=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0(0x14 / 4) > > =C2=A0=C2=A0 > > -#define WDT_RESTART_MAGIC=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A00x4= 755 > > +#define WDT_RESTART_MAGIC=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A00x4755 > > =C2=A0=C2=A0 > > =C2=A0 static bool aspeed_wdt_is_enabled(const AspeedWDTState *s) > > =C2=A0 { > > @@ -55,9 +64,10 @@ static uint64_t aspeed_wdt_read(void *opaque, hwaddr= offset, unsigned size) > > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0return 0; > > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0case WDT_CTRL: > > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0return s->r= egs[WDT_CTRL]; > > +=C2=A0=C2=A0=C2=A0=C2=A0case WDT_RESET_WIDTH: > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0return s->regs[WDT_RES= ET_WIDTH]; > > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0case WDT_TIMEOUT_STATUS: > > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0case WDT_TIMEOUT_CLEAR: > > -=C2=A0=C2=A0=C2=A0=C2=A0case WDT_RESET_WDITH: > > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0qemu_log_ma= sk(LOG_UNIMP, > > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= "%s: uninmplemented read at offset 0x%" HWADDR_PRIx "\n", > > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= __func__, offset); > > @@ -119,9 +129,25 @@ static void aspeed_wdt_write(void *opaque, hwaddr = offset, uint64_t data, > > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0timer_del(s->timer); > > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0} > > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0break; > > +=C2=A0=C2=A0=C2=A0=C2=A0case WDT_RESET_WIDTH: > > +=C2=A0=C2=A0=C2=A0=C2=A0{ > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0uint32_t property =3D = data & WDT_POLARITY_MASK; > > + > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0if (property =3D=3D WD= T_ACTIVE_HIGH_MAGIC) { > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0s->regs[WDT_RESET_WIDTH] |=3D WDT_RESET_WIDTH_ACTIVE_HIGH; > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0} else if (property = =3D=3D WDT_ACTIVE_LOW_MAGIC) { > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0s->regs[WDT_RESET_WIDTH] &=3D ~WDT_RESET_WIDTH_ACTIVE_HIGH; > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0} else if (property = =3D=3D WDT_PUSH_PULL_MAGIC) { > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0s->regs[WDT_RESET_WIDTH] |=3D WDT_RESET_WIDTH_PUSH_PULL; > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0} else if (property = =3D=3D WDT_OPEN_DRAIN_MAGIC) { > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0s->regs[WDT_RESET_WIDTH] &=3D ~WDT_RESET_WIDTH_PUSH_PULL; >=20 > } else { > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0qemu_log_mask(LOG_GUEST_ERROR, ... >=20 > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0} =46rom the datasheet: "For others value, this bit will keep old value without change." So it is not a guest error to write a value not matching the cases above. >=20 > Anyway I'm not sure about this if(). > Usually watchdogs have a state machine, if you don't do all unlock steps= =C2=A0 > ordered, the SM get reset. This is why magic is involved, else you could= =C2=A0 > use it as a regular register. > I'd expect a guest writing ACTIVE_HIGH_MAGIC then PUSH_PULL_MAGIC to not= =C2=A0 > modify the RESET_WIDTH register, since the correct behavior would be to= =C2=A0 > write ordered RESTART_MAGIC, then HIGH_MAGIC, then LOW_MAGIC and finally= =C2=A0 > the PULL/DRAIN change, but I'm just trying to model this wdg in my head= =C2=A0 > without having study the DS so you can't rely on my comments :) Well, given I have it handy, I think the behaviour of the hardware resolves this query: root@romulus:~# devmem 0x1e785018 0x000000FF root@romulus:~# devmem 0x1e785018 32 0xa80000ff root@romulus:~# devmem 0x1e785018 0x400000FF root@romulus:~# devmem 0x1e785018 32 0x8a0000ff root@romulus:~# devmem 0x1e785018 0x000000FF root@romulus:~# devmem 0x1e785018 32 0xa50000ff root@romulus:~# devmem 0x1e785018 0x800000FF root@romulus:~# devmem 0x1e785018 32 0x5a0000ff root@romulus:~# devmem 0x1e785018 0x000000FF root@romulus:~# devmem 0x1e785018 32 0xa80000ff root@romulus:~# devmem 0x1e785018 32 0xa50000ff root@romulus:~# devmem 0x1e785018 0xC00000FF root @romulus:~# devmem 0x1e785018 32 0x5a0000ff root@romulus:~# devmem 0x1e785018 32 0x8a0000ff root@romulus:~# devmem 0x1e785018 0x000000FF root@romulus:~# devmem 0x1e785018 32 0xa50000ff root@romulus:~# devmem 0x1e785018 0x800000FF root@romulus:~# devmem 0x1e785018 32 0x000a5a5a root@romulus:~# devmem 0x1e785018 0x800A5A5A root@romulus:~# devmem 0x1e785018 32 0x5a0000ff root@romulus:~# devmem 0x1e785018 0x000000FF Bear in mind the driver is loaded, so maybe it's messing with the test, but I haven't seen any indication to the contrary. >=20 > Also it seems unsafe to modify that kind of property while the watchdog= =C2=A0 > is running, usually you disable it before modifying it, else while=C2=A0 > running changes are automagically ignored. But that's a host-code problem, right? I don't see any hardware restriction noted in the datasheet along these lines. >=20 > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0s->regs[WDT_RESET_WIDT= H] &=3D ~WDT_RESET_WIDTH_DURATION; > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0s->regs[WDT_RESET_WIDT= H] |=3D data & WDT_RESET_WIDTH_DURATION; > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0break; > > +=C2=A0=C2=A0=C2=A0=C2=A0} > > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0case WDT_TIMEOUT_STATUS: > > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0case WDT_TIMEOUT_CLEAR: > > -=C2=A0=C2=A0=C2=A0=C2=A0case WDT_RESET_WDITH: > > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0qemu_log_ma= sk(LOG_UNIMP, > > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= "%s: uninmplemented write at offset 0x%" HWADDR_PRIx "\n", > > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= __func__, offset); > > @@ -167,6 +193,7 @@ static void aspeed_wdt_reset(DeviceState *dev) > > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0s->regs[WDT_RELOAD_VALUE] =3D 0x03E= F1480; > > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0s->regs[WDT_RESTART] =3D 0; > > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0s->regs[WDT_CTRL] =3D 0; > > +=C2=A0=C2=A0=C2=A0=C2=A0s->regs[WDT_RESET_WIDTH] =3D 0XFF; >=20 > why different than your define WDT_RESET_WIDTH_DURATION? Maybe WDT_RESET_WIDTH_DURATION is poorly named, but it's a mask, not a value. The 0xFF here (somehow I got an upper-case X in there) is the default value for the register as documented in both the AST2400 and AST2500 datasheets. However, this *has* lead me to discover that I've defined the WDT_RESET_WIDTH_DURATION mask too narrow for the AST2500, it should be 0xFFFFF (19:0). The AST2400 datasheet documents the field as 7:0 (0xFF). I'll respin, taking into account the 2.11 note above, unless you have any more comments. Thanks for taking a look! Andrew > > =C2=A0=C2=A0 > > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0timer_del(s->timer); > > =C2=A0 } > >=20 >=20 > Regards, >=20 > Phil. --=-mw8h11HAz22QEgQhmKe5 Content-Type: application/pgp-signature; name="signature.asc" Content-Description: This is a digitally signed message part Content-Transfer-Encoding: 7bit -----BEGIN PGP SIGNATURE----- iQIcBAABCgAGBQJZgARWAAoJEJ0dnzgO5LT5yzoP/A/dsr7O61gySJwGn3+TGSsF DmyLfDlDzPpG2vHpG+lE/ipgd0hnnkXF3JakEfpfDfR1Oj0fayrF1NfGVIHFpoTz kAlsztmg6mZssDHraPTmBON2cftPN1+rT4mX96XCWJRN072CNY/MTSAG9xVm7ph4 yYi6hkX7cQA9hozTNOSJV0KIsBkH3vJBbxSN8NG/0/M24KghYOzLagOs3Od+63ES A2HDfAISniXpXeuvWWuNb46ZMSuMJTJoV8PBp8VT8SIkF5aKgT0vJQouJE7JkAAu DU3f+cbmBslXL6ZLlzS4uFK2K9XCD4FPCCbJi66UJiQnmIACa6NJZiKol4eXyy7P yQB1+bNPzsOxf2jI866Q5JsTxIclhWBYXTW0OQ4E0iPlJpVCFctEMiKwNn7/C+y6 WdN54SbPJn/8TLpepd7lehg4yN3XLchWzowCgYUhyeOkGny7gYmWt2fl0ZXoCWhe j0w/+1zc9ZxRvak+X74pyFQ9AsyJqhRdtt7e8D0GVpBCLr/OJX0JNDRreyT+mpBp deAwgVEx4EJ6AQc7H76Y6nnqBOz6hm8UI0QK/X/3EXsUL9sx6h5FT5LD39u0U7r+ W2HbduAEIM4Z22arM/Cqq+NgkYANhYd9KngSIbETLvDQMKJ0dnvWewrKjEH5URqb I4qzEZb+utZmwyyA64ky =AWxP -----END PGP SIGNATURE----- --=-mw8h11HAz22QEgQhmKe5-- From MAILER-DAEMON Tue Aug 01 02:08:23 2017 Received: from list by lists.gnu.org with archive (Exim 4.71) id 1dcQLv-0007Kn-8e for mharc-qemu-arm@gnu.org; Tue, 01 Aug 2017 02:08:23 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:55272) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dcQLr-0007Ic-RK for qemu-arm@nongnu.org; Tue, 01 Aug 2017 02:08:21 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dcQLp-0005x3-SE for qemu-arm@nongnu.org; Tue, 01 Aug 2017 02:08:19 -0400 Received: from mail-vk0-x241.google.com ([2607:f8b0:400c:c05::241]:36891) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1dcQLg-0005vA-OU; Tue, 01 Aug 2017 02:08:08 -0400 Received: by mail-vk0-x241.google.com with SMTP id r199so298279vke.4; Mon, 31 Jul 2017 23:08:06 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=mime-version:in-reply-to:references:from:date:message-id:subject:to :cc; bh=yqb/tC2puwrabtt4R5PhETbZjFHfX1kYNw+PhI/zs6U=; b=TT8yZYfA5E+HlTwtZJHvEEAT3chjW2jgxI4ZIOZp8KPMwUt0wMrwyEC23etxPOpKv8 tJ9W9z6wP3YMPwmXXze0B3vuFuo1AXPhbdyjs8mQSRa01Dr3xjdHLyOLYYf4ho4zxnwG +cIx+exUjaapzDXL04iyoH8Jf5oPGcYH4OeyPOmOKwU3HMCEvmjQ/CiV5h8RrU3yLXlb tgN6N7yjqLu97n7YjZ5PshcL21Qo3sfsvgPGqPZ5uYooD46hJ0j0toqs0w8OsPKy9BKd s3p5FKw5/pXyVFCIedVjAB+eRgJlUnttMGtzsEA5yyy0ogYmBgxlFN7H3ZG7O2dvDC+n lTew== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:in-reply-to:references:from:date :message-id:subject:to:cc; bh=yqb/tC2puwrabtt4R5PhETbZjFHfX1kYNw+PhI/zs6U=; b=okYkH3OpPEKWtOaKYGsgUgpris0uSDd7HrcwLCzdzFCL//SAM4vwm0RFuuvZiKzRE0 HX6AkhPCXbPxlnV6WG3VDDrWLmyrQDjqsA5ZLsnpwN3V5tQkppaOH3+bJa4j6wmA6rPI MDB+8TRAzzTHyBdxTSZiOdXNhffpDInlI7z2Tux26RnXnGt8O6fV95+bjCZnDhYvzOHO XJiYYMTyl6ao2dCNUdoP3lNrvohESEeloy9b/yA7v9BBJmN/9opK5kuGUxif9yl9ROfa 2icR8N7/OvrnJhOREJ3WUHS8UyD3CEmY8WhjrFilpLw2BJcVdBvhIrgbG8Wzla4dcwj8 Oigw== X-Gm-Message-State: AIVw110Dc4TmlqXbbrV8UbCY9XVKT3RAg7U3qoAPrLgriOvspo8P/b3l 1VFUX1VYffJrgTnXuUtib6+KgfpE5w== X-Received: by 10.31.149.151 with SMTP id x145mr12063245vkd.139.1501567686186; Mon, 31 Jul 2017 23:08:06 -0700 (PDT) MIME-Version: 1.0 Received: by 10.176.83.139 with HTTP; Mon, 31 Jul 2017 23:08:05 -0700 (PDT) In-Reply-To: References: <1499057115-6773-1-git-send-email-sundeep.lkml@gmail.com> <1499057115-6773-3-git-send-email-sundeep.lkml@gmail.com> From: sundeep subbaraya Date: Tue, 1 Aug 2017 11:38:05 +0530 Message-ID: To: Alistair Francis , =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= Cc: "qemu-devel@nongnu.org Developers" , qemu-arm , Peter Maydell , Peter Crosthwaite Content-Type: multipart/alternative; boundary="001a114259e48a9bda0555aaf89e" X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400c:c05::241 Subject: Re: [Qemu-arm] [Qemu devel v6 PATCH 2/5] msf2: Microsemi Smartfusion2 System Register block. X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 01 Aug 2017 06:08:22 -0000 --001a114259e48a9bda0555aaf89e Content-Type: text/plain; charset="UTF-8" Hi Philippe, Ping again :) Thanks, Sundeep On Fri, Jul 21, 2017 at 2:50 PM, sundeep subbaraya wrote: > Hi, > > Ping > > On Thu, Jul 13, 2017 at 7:51 AM, sundeep subbaraya > wrote: > >> Hi Phiiippe, >> >> Gentle reminder. >> >> Thanks, >> Sundeep >> >> >> On Mon, Jul 10, 2017 at 1:55 PM, sundeep subbaraya < >> sundeep.lkml@gmail.com> wrote: >> >>> Hi Alistair, >>> >>> On Fri, Jul 7, 2017 at 10:03 PM, Alistair Francis >>> wrote: >>> >>>> On Fri, Jul 7, 2017 at 12:08 AM, sundeep subbaraya >>>> wrote: >>>> > Hi Alistair, >>>> > >>>> > On Wed, Jul 5, 2017 at 11:36 PM, Alistair Francis < >>>> alistair23@gmail.com> >>>> > wrote: >>>> >> >>>> >> On Sun, Jul 2, 2017 at 9:45 PM, Subbaraya Sundeep >>>> >> wrote: >>>> >> > Added Sytem register block of Smartfusion2. >>>> >> > This block has PLL registers which are accessed by guest. >>>> >> > >>>> >> > Signed-off-by: Subbaraya Sundeep >>>> >> > --- >>>> >> > hw/misc/Makefile.objs | 1 + >>>> >> > hw/misc/msf2-sysreg.c | 200 >>>> >> > ++++++++++++++++++++++++++++++++++++++++++ >>>> >> > include/hw/misc/msf2-sysreg.h | 82 +++++++++++++++++ >>>> >> > 3 files changed, 283 insertions(+) >>>> >> > create mode 100644 hw/misc/msf2-sysreg.c >>>> >> > create mode 100644 include/hw/misc/msf2-sysreg.h >>>> >> > >>>> >> > diff --git a/hw/misc/Makefile.objs b/hw/misc/Makefile.objs >>>> >> > index c8b4893..0f52354 100644 >>>> >> > --- a/hw/misc/Makefile.objs >>>> >> > +++ b/hw/misc/Makefile.objs >>>> >> > @@ -56,3 +56,4 @@ obj-$(CONFIG_EDU) += edu.o >>>> >> > obj-$(CONFIG_HYPERV_TESTDEV) += hyperv_testdev.o >>>> >> > obj-$(CONFIG_AUX) += auxbus.o >>>> >> > obj-$(CONFIG_ASPEED_SOC) += aspeed_scu.o aspeed_sdmc.o >>>> >> > +obj-$(CONFIG_MSF2) += msf2-sysreg.o >>>> >> > diff --git a/hw/misc/msf2-sysreg.c b/hw/misc/msf2-sysreg.c >>>> >> > new file mode 100644 >>>> >> > index 0000000..64ee141 >>>> >> > --- /dev/null >>>> >> > +++ b/hw/misc/msf2-sysreg.c >>>> >> > @@ -0,0 +1,200 @@ >>>> >> > +/* >>>> >> > + * System Register block model of Microsemi SmartFusion2. >>>> >> > + * >>>> >> > + * Copyright (c) 2017 Subbaraya Sundeep >>>> >> > + * >>>> >> > + * This program is free software; you can redistribute it and/or >>>> >> > + * modify it under the terms of the GNU General Public License >>>> >> > + * as published by the Free Software Foundation; either version >>>> >> > + * 2 of the License, or (at your option) any later version. >>>> >> > + * >>>> >> > + * You should have received a copy of the GNU General Public >>>> License >>>> >> > along >>>> >> > + * with this program; if not, see . >>>> >> > + */ >>>> >> > + >>>> >> > +#include "hw/misc/msf2-sysreg.h" >>>> >> >>>> >> Same #include comment from patch 1. >>>> > >>>> > >>>> > Ok will change. >>>> >> >>>> >> >>>> >> > + >>>> >> > +#ifndef MSF2_SYSREG_ERR_DEBUG >>>> >> > +#define MSF2_SYSREG_ERR_DEBUG 0 >>>> >> > +#endif >>>> >> > + >>>> >> > +#define DB_PRINT_L(lvl, fmt, args...) do { \ >>>> >> > + if (MSF2_SYSREG_ERR_DEBUG >= lvl) { \ >>>> >> > + qemu_log("%s: " fmt "\n", __func__, ## args); \ >>>> >> > + } \ >>>> >> > +} while (0); >>>> >> > + >>>> >> > +#define DB_PRINT(fmt, args...) DB_PRINT_L(1, fmt, ## args) >>>> >> > + >>>> >> > +static inline int msf2_divbits(uint32_t div) >>>> >> > +{ >>>> >> > + int ret = 0; >>>> >> > + >>>> >> > + switch (div) { >>>> >> > + case 1: >>>> >> > + ret = 0; >>>> >> > + break; >>>> >> > + case 2: >>>> >> > + ret = 1; >>>> >> > + break; >>>> >> > + case 4: >>>> >> > + ret = 2; >>>> >> > + break; >>>> >> > + case 8: >>>> >> > + ret = 4; >>>> >> > + break; >>>> >> > + case 16: >>>> >> > + ret = 5; >>>> >> > + break; >>>> >> > + case 32: >>>> >> > + ret = 6; >>>> >> > + break; >>>> >> > + default: >>>> >> > + break; >>>> >> > + } >>>> >> > + >>>> >> > + return ret; >>>> >> > +} >>>> >> > + >>>> >> > +static void msf2_sysreg_reset(DeviceState *d) >>>> >> > +{ >>>> >> > + MSF2SysregState *s = MSF2_SYSREG(d); >>>> >> > + >>>> >> > + DB_PRINT("RESET"); >>>> >> > + >>>> >> > + s->regs[MSSDDR_PLL_STATUS_LOW_CR] = 0x021A2358; >>>> >> > + s->regs[MSSDDR_PLL_STATUS] = 0x3; >>>> >> > + s->regs[MSSDDR_FACC1_CR] = msf2_divbits(s->apb0div) << 5 | >>>> >> > + msf2_divbits(s->apb1div) << 2; >>>> >> > +} >>>> >> > + >>>> >> > +static uint64_t msf2_sysreg_read(void *opaque, hwaddr offset, >>>> >> > + unsigned size) >>>> >> > +{ >>>> >> > + MSF2SysregState *s = opaque; >>>> >> > + offset /= 4; >>>> >> >>>> >> Probably best to use a bitshift. >>>> > >>>> > >>>> > Ok will change. >>>> >> >>>> >> >>>> >> > + uint32_t ret = 0; >>>> >> > + >>>> >> > + if (offset < ARRAY_SIZE(s->regs)) { >>>> >> > + ret = s->regs[offset]; >>>> >> > + DB_PRINT("addr: 0x%08" HWADDR_PRIx " data: 0x%08" PRIx32, >>>> >> > + offset * 4, ret); >>>> >> >>>> >> Bitshift here as well. >>>> > >>>> > >>>> > Ok will change. >>>> >> >>>> >> >>>> >> > + } else { >>>> >> > + qemu_log_mask(LOG_GUEST_ERROR, >>>> >> > + "%s: Bad offset 0x%08" HWADDR_PRIx "\n", >>>> __func__, >>>> >> > + offset * 4); >>>> >> > + } >>>> >> > + >>>> >> > + return ret; >>>> >> > +} >>>> >> > + >>>> >> > +static void msf2_sysreg_write(void *opaque, hwaddr offset, >>>> >> > + uint64_t val, unsigned size) >>>> >> > +{ >>>> >> > + MSF2SysregState *s = (MSF2SysregState *)opaque; >>>> >> > + uint32_t newval = val; >>>> >> > + uint32_t oldval; >>>> >> > + >>>> >> > + DB_PRINT("addr: 0x%08" HWADDR_PRIx " data: 0x%08" PRIx64, >>>> >> > + offset, val); >>>> >> > + >>>> >> > + offset /= 4; >>>> >> >>>> >> Same here >>>> > >>>> > >>>> > Ok will change >>>> >> >>>> >> >>>> >> > + >>>> >> > + switch (offset) { >>>> >> > + case MSSDDR_PLL_STATUS: >>>> >> > + break; >>>> >> > + >>>> >> > + case ESRAM_CR: >>>> >> > + oldval = s->regs[ESRAM_CR]; >>>> >> > + if (oldval ^ newval) { >>>> >> > + qemu_log_mask(LOG_GUEST_ERROR, >>>> >> > + TYPE_MSF2_SYSREG": eSRAM remapping not >>>> >> > supported\n"); >>>> >> > + abort(); >>>> >> >>>> >> The guest should not be able to kill QEMU, a guest error should never >>>> >> result in an abort. >>>> > >>>> > >>>> > Philippe suggested to abort because: >>>> > If guest tries to remap since firmware do a remap, the code flow will >>>> be >>>> > completely wrong. >>>> > Reporting a GUEST_ERROR here is not enough since code flow continuing >>>> would >>>> > be >>>> > pretty hard to understand/debug. >>>> >>>> I don't see how it will be that hard to debug as QEMU will tell you >>>> that the guest is doing something wrong. >>>> >>>> You can't allow the guest to abort or exit QEMU. It's a security >>>> liability issue and specifically mentioned as not allowed: >>>> https://github.com/qemu/qemu/blob/master/HACKING#L230 >>>> >>>> Ok. Lets hear from Philippe. Philippe? >>> >>> Thanks, >>> Sundeep >>> >>> >>>> Thanks, >>>> Alistair >>>> >>>> > We decided to abort for now. >>>> >>> >>> >> > --001a114259e48a9bda0555aaf89e Content-Type: text/html; charset="UTF-8" Content-Transfer-Encoding: quoted-printable
Hi Philippe,

Ping again :)
Thanks,
Sundeep

On Fri, Jul 21, 2017 at 2:50 PM, sundeep s= ubbaraya <sundeep.lkml@gmail.com> wrote:
Hi,

Ping

On Thu, Jul 13, 2017 at 7:51 AM, sundeep subbaraya = <sundeep.lkml@gmail.com> wrote:
Hi Phiiippe,

Gentle= reminder.

Thanks,
Sundeep


On Mon, Jul 10, 2017 at 1:55 PM, sundeep subbaraya <sundeep.lkml@gmail.com> wrote:
Hi Alistair,

On Fri, Jul 7, 2017 at 10:03 PM, Alistair Francis <alis= tair23@gmail.com> wrote:
On Fri, Jul 7, 2017 at 12:08 AM, sundeep subbaraya
<sundeep.lkm= l@gmail.com> wrote:
> Hi Alistair,
>
> On Wed, Jul 5, 2017 at 11:36 PM, Alistair Francis <alistair23@gmail.com>
> wrote:
>>
>> On Sun, Jul 2, 2017 at 9:45 PM, Subbaraya Sundeep
>> <su= ndeep.lkml@gmail.com> wrote:
>> > Added Sytem register block of Smartfusion2.
>> > This block has PLL registers which are accessed by guest.
>> >
>> > Signed-off-by: Subbaraya Sundeep <sundeep.lkml@gmail.com>
>> > ---
>> >=C2=A0 hw/misc/Makefile.objs=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= |=C2=A0 =C2=A01 +
>> >=C2=A0 hw/misc/msf2-sysreg.c=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= | 200
>> > ++++++++++++++++++++++++++++++++++++++++++
>> >=C2=A0 include/hw/misc/msf2-sysreg.h |=C2=A0 82 ++++++++++++++= +++
>> >=C2=A0 3 files changed, 283 insertions(+)
>> >=C2=A0 create mode 100644 hw/misc/msf2-sysreg.c
>> >=C2=A0 create mode 100644 include/hw/misc/msf2-sysreg.h
>> >
>> > diff --git a/hw/misc/Makefile.objs b/hw/misc/Makefile.objs >> > index c8b4893..0f52354 100644
>> > --- a/hw/misc/Makefile.objs
>> > +++ b/hw/misc/Makefile.objs
>> > @@ -56,3 +56,4 @@ obj-$(CONFIG_EDU) +=3D edu.o
>> >=C2=A0 obj-$(CONFIG_HYPERV_TESTDEV) +=3D hyperv_testdev.o
>> >=C2=A0 obj-$(CONFIG_AUX) +=3D auxbus.o
>> >=C2=A0 obj-$(CONFIG_ASPEED_SOC) +=3D aspeed_scu.o aspeed_sdmc.= o
>> > +obj-$(CONFIG_MSF2) +=3D msf2-sysreg.o
>> > diff --git a/hw/misc/msf2-sysreg.c b/hw/misc/msf2-sysreg.c >> > new file mode 100644
>> > index 0000000..64ee141
>> > --- /dev/null
>> > +++ b/hw/misc/msf2-sysreg.c
>> > @@ -0,0 +1,200 @@
>> > +/*
>> > + * System Register block model of Microsemi SmartFusion2. >> > + *
>> > + * Copyright (c) 2017 Subbaraya Sundeep <sundeep.lkml@gmail.com><= br> >> > + *
>> > + * This program is free software; you can redistribute it an= d/or
>> > + * modify it under the terms of the GNU General Public Licen= se
>> > + * as published by the Free Software Foundation; either vers= ion
>> > + * 2 of the License, or (at your option) any later version.<= br> >> > + *
>> > + * You should have received a copy of the GNU General Public= License
>> > along
>> > + * with this program; if not, see <http://www.gnu.org/= licenses/>.
>> > + */
>> > +
>> > +#include "hw/misc/msf2-sysreg.h"
>>
>> Same #include comment from patch 1.
>
>
> Ok will change.
>>
>>
>> > +
>> > +#ifndef MSF2_SYSREG_ERR_DEBUG
>> > +#define MSF2_SYSREG_ERR_DEBUG=C2=A0 0
>> > +#endif
>> > +
>> > +#define DB_PRINT_L(lvl, fmt, args...) do { \
>> > +=C2=A0 =C2=A0 if (MSF2_SYSREG_ERR_DEBUG >=3D lvl) { \
>> > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 qemu_log("%s: " fmt &q= uot;\n", __func__, ## args); \
>> > +=C2=A0 =C2=A0 } \
>> > +} while (0);
>> > +
>> > +#define DB_PRINT(fmt, args...) DB_PRINT_L(1, fmt, ## args) >> > +
>> > +static inline int msf2_divbits(uint32_t div)
>> > +{
>> > +=C2=A0 =C2=A0 int ret =3D 0;
>> > +
>> > +=C2=A0 =C2=A0 switch (div) {
>> > +=C2=A0 =C2=A0 case 1:
>> > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 ret =3D 0;
>> > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 break;
>> > +=C2=A0 =C2=A0 case 2:
>> > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 ret =3D 1;
>> > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 break;
>> > +=C2=A0 =C2=A0 case 4:
>> > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 ret =3D 2;
>> > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 break;
>> > +=C2=A0 =C2=A0 case 8:
>> > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 ret =3D 4;
>> > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 break;
>> > +=C2=A0 =C2=A0 case 16:
>> > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 ret =3D 5;
>> > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 break;
>> > +=C2=A0 =C2=A0 case 32:
>> > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 ret =3D 6;
>> > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 break;
>> > +=C2=A0 =C2=A0 default:
>> > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 break;
>> > +=C2=A0 =C2=A0 }
>> > +
>> > +=C2=A0 =C2=A0 return ret;
>> > +}
>> > +
>> > +static void msf2_sysreg_reset(DeviceState *d)
>> > +{
>> > +=C2=A0 =C2=A0 MSF2SysregState *s =3D MSF2_SYSREG(d);
>> > +
>> > +=C2=A0 =C2=A0 DB_PRINT("RESET");
>> > +
>> > +=C2=A0 =C2=A0 s->regs[MSSDDR_PLL_STATUS_LOW_CR] =3D = 0x021A2358;
>> > +=C2=A0 =C2=A0 s->regs[MSSDDR_PLL_STATUS] =3D 0x3;
>> > +=C2=A0 =C2=A0 s->regs[MSSDDR_FACC1_CR] =3D msf2_divbits(s= ->apb0div) << 5 |
>> > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0msf2_divbits(s->apb1= div) << 2;
>> > +}
>> > +
>> > +static uint64_t msf2_sysreg_read(void *opaque, hwaddr offset= ,
>> > +=C2=A0 =C2=A0 unsigned size)
>> > +{
>> > +=C2=A0 =C2=A0 MSF2SysregState *s =3D opaque;
>> > +=C2=A0 =C2=A0 offset /=3D 4;
>>
>> Probably best to use a bitshift.
>
>
> Ok will change.
>>
>>
>> > +=C2=A0 =C2=A0 uint32_t ret =3D 0;
>> > +
>> > +=C2=A0 =C2=A0 if (offset < ARRAY_SIZE(s->regs)) {
>> > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 ret =3D s->regs[offset];
>> > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 DB_PRINT("addr: 0x%08"= HWADDR_PRIx " data: 0x%08" PRIx32,
>> > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 offset * 4, ret);
>>
>> Bitshift here as well.
>
>
> Ok will change.
>>
>>
>> > +=C2=A0 =C2=A0 } else {
>> > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 qemu_log_mask(LOG_GUEST_ERROR, >> > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 "%s: Bad offset 0x%08" HWADDR_PRIx "\n", __f= unc__,
>> > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 offset * 4);
>> > +=C2=A0 =C2=A0 }
>> > +
>> > +=C2=A0 =C2=A0 return ret;
>> > +}
>> > +
>> > +static void msf2_sysreg_write(void *opaque, hwaddr offset, >> > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 uint64_t val, unsigned size)
>> > +{
>> > +=C2=A0 =C2=A0 MSF2SysregState *s =3D (MSF2SysregState *)opaq= ue;
>> > +=C2=A0 =C2=A0 uint32_t newval =3D val;
>> > +=C2=A0 =C2=A0 uint32_t oldval;
>> > +
>> > +=C2=A0 =C2=A0 DB_PRINT("addr: 0x%08" HWADDR_PRIx &= quot; data: 0x%08" PRIx64,
>> > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 offset, val);
>> > +
>> > +=C2=A0 =C2=A0 offset /=3D 4;
>>
>> Same here
>
>
> Ok will change
>>
>>
>> > +
>> > +=C2=A0 =C2=A0 switch (offset) {
>> > +=C2=A0 =C2=A0 case MSSDDR_PLL_STATUS:
>> > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 break;
>> > +
>> > +=C2=A0 =C2=A0 case ESRAM_CR:
>> > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 oldval =3D s->regs[ESRAM_CR];=
>> > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 if (oldval ^ newval) {
>> > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 qemu_log_mask(LOG_= GUEST_ERROR,
>> > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0TYPE_MSF2_SYSREG": eSRAM remapping not
>> > supported\n");
>> > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 abort();
>>
>> The guest should not be able to kill QEMU, a guest error should ne= ver
>> result in an abort.
>
>
> Philippe suggested to abort because:
> If guest tries to remap since firmware do a remap, the code flow will = be
> completely wrong.
> Reporting a GUEST_ERROR here is not enough since code flow continuing = would
> be
> pretty hard to understand/debug.

I don't see how it will be that hard to debug as QEMU will = tell you
that the guest is doing something wrong.

You can't allow the guest to abort or exit QEMU. It's a security liability issue and specifically mentioned as not allowed:
https://github.com/qemu/qemu/blob/master/H= ACKING#L230

Ok. Lets hear from Philippe. Philippe?
Thanks,
Sundeep
=C2=A0
Thanks,
Alistair

> We decided to abort for now.




--001a114259e48a9bda0555aaf89e-- From MAILER-DAEMON Tue Aug 01 03:21:29 2017 Received: from list by lists.gnu.org with archive (Exim 4.71) id 1dcRUf-0003YK-Qy for mharc-qemu-arm@gnu.org; Tue, 01 Aug 2017 03:21:29 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:53595) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dcRUe-0003Y5-2L for qemu-arm@nongnu.org; Tue, 01 Aug 2017 03:21:29 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dcRUa-0000QK-QJ for qemu-arm@nongnu.org; Tue, 01 Aug 2017 03:21:28 -0400 Received: from 10.mo178.mail-out.ovh.net ([46.105.76.150]:38786) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1dcRUa-0000Mz-Fr for qemu-arm@nongnu.org; Tue, 01 Aug 2017 03:21:24 -0400 Received: from player715.ha.ovh.net (b9.ovh.net [213.186.33.59]) by mo178.mail-out.ovh.net (Postfix) with ESMTP id CD2674AFDA for ; Tue, 1 Aug 2017 09:21:14 +0200 (CEST) Received: from zorba.kaod.org (LFbn-1-10652-153.w90-89.abo.wanadoo.fr [90.89.238.153]) (Authenticated sender: postmaster@kaod.org) by player715.ha.ovh.net (Postfix) with ESMTPSA id 5FC581C008F; Tue, 1 Aug 2017 09:21:07 +0200 (CEST) To: Andrew Jeffery , qemu-arm@nongnu.org References: <20170801010425.25778-1-andrew@aj.id.au> Cc: qemu-devel@nongnu.org, peter.maydell@linaro.org, joel@jms.id.au, openbmc@lists.ozlabs.org From: =?UTF-8?Q?C=c3=a9dric_Le_Goater?= Message-ID: <855a154a-4cdf-b29a-6440-5deadbeed12e@kaod.org> Date: Tue, 1 Aug 2017 09:21:07 +0200 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:45.0) Gecko/20100101 Thunderbird/45.8.0 MIME-Version: 1.0 In-Reply-To: <20170801010425.25778-1-andrew@aj.id.au> Content-Type: text/plain; charset=windows-1252 Content-Transfer-Encoding: 7bit X-Ovh-Tracer-Id: 3164341688418077442 X-VR-SPAMSTATE: OK X-VR-SPAMSCORE: -100 X-VR-SPAMCAUSE: gggruggvucftvghtrhhoucdtuddrfeelkedrieekgdduvddvucetufdoteggodetrfdotffvucfrrhhofhhilhgvmecuqfggjfdpvefjgfevmfevgfenuceurghilhhouhhtmecufedttdenucesvcftvggtihhpihgvnhhtshculddquddttddm X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 46.105.76.150 Subject: Re: [Qemu-arm] [PATCH] watchdog: wdt_aspeed: Add support for the reset width register X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 01 Aug 2017 07:21:29 -0000 On 08/01/2017 03:04 AM, Andrew Jeffery wrote: > The reset width register controls how the pulse on the SoC's WDTRST{1,2} > pins behaves. A pulse is emitted if the external reset bit is set in > WDT_CTRL. WDT_RESET_WIDTH requires magic bit patterns to configure both > push-pull/open-drain and active-high/active-low behaviours and thus > needs some special handling in the write path. > > Signed-off-by: Andrew Jeffery > --- > I understand that we're in stabilisation mode, but I thought I'd send this out > to provoke any feedback. Happy to resend after the 2.10 release if required. > > hw/watchdog/wdt_aspeed.c | 47 +++++++++++++++++++++++++++++++++++++---------- > 1 file changed, 37 insertions(+), 10 deletions(-) > > diff --git a/hw/watchdog/wdt_aspeed.c b/hw/watchdog/wdt_aspeed.c > index 8bbe579b6b66..4ef1412e99fc 100644 > --- a/hw/watchdog/wdt_aspeed.c > +++ b/hw/watchdog/wdt_aspeed.c > @@ -14,10 +14,10 @@ > #include "qemu/timer.h" > #include "hw/watchdog/wdt_aspeed.h" > > -#define WDT_STATUS (0x00 / 4) > -#define WDT_RELOAD_VALUE (0x04 / 4) > -#define WDT_RESTART (0x08 / 4) > -#define WDT_CTRL (0x0C / 4) > +#define WDT_STATUS (0x00 / 4) > +#define WDT_RELOAD_VALUE (0x04 / 4) > +#define WDT_RESTART (0x08 / 4) > +#define WDT_CTRL (0x0C / 4) > #define WDT_CTRL_RESET_MODE_SOC (0x00 << 5) > #define WDT_CTRL_RESET_MODE_FULL_CHIP (0x01 << 5) > #define WDT_CTRL_1MHZ_CLK BIT(4) > @@ -25,12 +25,21 @@ > #define WDT_CTRL_WDT_INTR BIT(2) > #define WDT_CTRL_RESET_SYSTEM BIT(1) > #define WDT_CTRL_ENABLE BIT(0) > +#define WDT_RESET_WIDTH (0x18 / 4) > +#define WDT_RESET_WIDTH_ACTIVE_HIGH BIT(31) > +#define WDT_POLARITY_MASK (0xFF << 24) > +#define WDT_ACTIVE_HIGH_MAGIC (0xA5 << 24) > +#define WDT_ACTIVE_LOW_MAGIC (0x5A << 24) > +#define WDT_RESET_WIDTH_PUSH_PULL BIT(30) > +#define WDT_DRIVE_TYPE_MASK (0xFF << 24) > +#define WDT_PUSH_PULL_MAGIC (0xA8 << 24) > +#define WDT_OPEN_DRAIN_MAGIC (0x8A << 24) > +#define WDT_RESET_WIDTH_DURATION 0xFFF; I would call this define WDT_RESET_WIDTH_DEFAULT (0xFF) and use it also in the aspeed_wdt_reset() I have checked the specs and the bits definitions are correct. What else could we model ? Would the pulse be interesting ? C. > > -#define WDT_TIMEOUT_STATUS (0x10 / 4) > -#define WDT_TIMEOUT_CLEAR (0x14 / 4) > -#define WDT_RESET_WDITH (0x18 / 4) > +#define WDT_TIMEOUT_STATUS (0x10 / 4) > +#define WDT_TIMEOUT_CLEAR (0x14 / 4) > > -#define WDT_RESTART_MAGIC 0x4755 > +#define WDT_RESTART_MAGIC 0x4755 > > static bool aspeed_wdt_is_enabled(const AspeedWDTState *s) > { > @@ -55,9 +64,10 @@ static uint64_t aspeed_wdt_read(void *opaque, hwaddr offset, unsigned size) > return 0; > case WDT_CTRL: > return s->regs[WDT_CTRL]; > + case WDT_RESET_WIDTH: > + return s->regs[WDT_RESET_WIDTH]; > case WDT_TIMEOUT_STATUS: > case WDT_TIMEOUT_CLEAR: > - case WDT_RESET_WDITH: > qemu_log_mask(LOG_UNIMP, > "%s: uninmplemented read at offset 0x%" HWADDR_PRIx "\n", > __func__, offset); > @@ -119,9 +129,25 @@ static void aspeed_wdt_write(void *opaque, hwaddr offset, uint64_t data, > timer_del(s->timer); > } > break; > + case WDT_RESET_WIDTH: > + { > + uint32_t property = data & WDT_POLARITY_MASK; > + > + if (property == WDT_ACTIVE_HIGH_MAGIC) { > + s->regs[WDT_RESET_WIDTH] |= WDT_RESET_WIDTH_ACTIVE_HIGH; > + } else if (property == WDT_ACTIVE_LOW_MAGIC) { > + s->regs[WDT_RESET_WIDTH] &= ~WDT_RESET_WIDTH_ACTIVE_HIGH; > + } else if (property == WDT_PUSH_PULL_MAGIC) { > + s->regs[WDT_RESET_WIDTH] |= WDT_RESET_WIDTH_PUSH_PULL; > + } else if (property == WDT_OPEN_DRAIN_MAGIC) { > + s->regs[WDT_RESET_WIDTH] &= ~WDT_RESET_WIDTH_PUSH_PULL; > + } > + s->regs[WDT_RESET_WIDTH] &= ~WDT_RESET_WIDTH_DURATION; > + s->regs[WDT_RESET_WIDTH] |= data & WDT_RESET_WIDTH_DURATION; > + break; > + } > case WDT_TIMEOUT_STATUS: > case WDT_TIMEOUT_CLEAR: > - case WDT_RESET_WDITH: > qemu_log_mask(LOG_UNIMP, > "%s: uninmplemented write at offset 0x%" HWADDR_PRIx "\n", > __func__, offset); > @@ -167,6 +193,7 @@ static void aspeed_wdt_reset(DeviceState *dev) > s->regs[WDT_RELOAD_VALUE] = 0x03EF1480; > s->regs[WDT_RESTART] = 0; > s->regs[WDT_CTRL] = 0; > + s->regs[WDT_RESET_WIDTH] = 0XFF; > > timer_del(s->timer); > } > From MAILER-DAEMON Tue Aug 01 04:30:38 2017 Received: from list by lists.gnu.org with archive (Exim 4.71) id 1dcSZa-00011X-Bk for mharc-qemu-arm@gnu.org; Tue, 01 Aug 2017 04:30:38 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:44351) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dcSZW-00010f-Ob for qemu-arm@nongnu.org; Tue, 01 Aug 2017 04:30:37 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dcSZV-0008Af-LV for qemu-arm@nongnu.org; Tue, 01 Aug 2017 04:30:34 -0400 Received: from mail-lf0-x242.google.com ([2a00:1450:4010:c07::242]:36930) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1dcSZP-00082a-9U; Tue, 01 Aug 2017 04:30:27 -0400 Received: by mail-lf0-x242.google.com with SMTP id x16so774377lfb.4; Tue, 01 Aug 2017 01:30:27 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=date:from:to:cc:subject:message-id:references:mime-version :content-disposition:in-reply-to:user-agent; bh=srABhKl2b+vD/Z4lU2FIaTJTeez07FbpMFAFLrWGT0o=; b=K6xGOGp67s4ql7ITCD9bmiPIqtMynfFokHj+3mydHzI0WTsGDjpb7reDzpuQ1EBbSq j4scXuDn6JvZrtcf6XDj9hO700rsmLzOsOWDmAeXmZDHD9llgfc/7Jal4P9UsaRU6C2h DdM6eZckVZBiXIi4MSbBR9WRI+NctSSQpIYgzUck2S8pW0fMFWNGltkECStHjvS7z2JT b5DflBkz7IeEROQy08r8i7OCGZX2DuDs58umNV7uHli81Cb1Af7hCqhz2ijnDN7gb335 lv/8TFOGsmlxqM0vG9QWl/Sggrcp6Ir3yvzDtMnKaFL7hG2iRIeXNyE6BB3X8w6R3dBW KWkg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:in-reply-to:user-agent; bh=srABhKl2b+vD/Z4lU2FIaTJTeez07FbpMFAFLrWGT0o=; b=dEtdRWjYgZsfNDy5Gw0x2xbRlJh8wH491b35jwn34m8N8ZI5ALj9nUOzrw4P5UElqc sVzDmftO+GGCAebdKVplwiDiQkSib2yuZkdf0Q8X5r2XTyWQgAeSY1+wFFqPqHJjldlA 4NTUvU9VTwfCcVYmZQUlA/YOWpXlkzdbAVuqIfpGYq8aIIHGfhAwCwkzeY0YwlCvpPKB sE+xNPV3XIQNmKJE5XTfzB9bp01oT9BaYNsugs35zy02Vyl4ePI4Fn4mUeTgsm5KgDbn jZM4r+yAiPUKodQ9g/5mjrib7CguCRa70NqbyO/h7GNHIjsSSl3UvWCaTfgFGPY/MKdB TjjA== X-Gm-Message-State: AIVw113BuppAr+aXMWViyJlvYtCr/JF9/BPPGQ8QlmDLS4fq3uKKAFMr uxE+9J6+FIbsIQ== X-Received: by 10.46.80.72 with SMTP id v8mr6410508ljd.192.1501576225816; Tue, 01 Aug 2017 01:30:25 -0700 (PDT) Received: from gmail.com (81-231-233-234-no56.tbcn.telia.com. [81.231.233.234]) by smtp.gmail.com with ESMTPSA id s203sm6009232lja.21.2017.08.01.01.30.24 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 01 Aug 2017 01:30:24 -0700 (PDT) Date: Tue, 1 Aug 2017 10:30:24 +0200 From: "Edgar E. Iglesias" To: "Michael S. Tsirkin" Cc: Diana Madalina Craciun , "qemu-devel@nongnu.org" , "eric.auger@redhat.com" , Mike Caraman , "qemu-arm@nongnu.org" , "marcel@redhat.com" , Bharat Bhushan , "christoffer.dall@linaro.org" , Laurentiu Tudor Message-ID: <20170801083024.GZ4859@toto> References: <1495537965-4187-1-git-send-email-diana.craciun@nxp.com> <20170525011034-mutt-send-email-mst@kernel.org> <20170706023845-mutt-send-email-mst@kernel.org> <20170731170217-mutt-send-email-mst@kernel.org> <20170801045857-mutt-send-email-mst@kernel.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20170801045857-mutt-send-email-mst@kernel.org> User-Agent: Mutt/1.5.24 (2015-08-30) X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4010:c07::242 Subject: Re: [Qemu-arm] [PATCH v2 0/2] Add global device ID in virt machine X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 01 Aug 2017 08:30:37 -0000 On Tue, Aug 01, 2017 at 05:05:42AM +0300, Michael S. Tsirkin wrote: > On Mon, Jul 31, 2017 at 03:13:09PM +0000, Diana Madalina Craciun wrote: > > On 07/31/2017 05:06 PM, Michael S. Tsirkin wrote: > > > On Mon, Jul 31, 2017 at 01:22:45PM +0000, Diana Madalina Craciun wrote: > > >>>> If we are to use a value of 0 for the constant in case of PCI devices, > > >>>> what happens if we have multiple PCI controllers? > > >>> I guess we'd use the PCI Segment number for that? > > >>> > > >>> > > >> Yes, we can use the PCI segment for this scenario. But this would mean > > >> different solutions for the same problem. The main problem is that we > > >> can have multiple entities in the system that are using MSIs (for now > > >> PCI and NXP non-PCI bus infrastructure > > >> (https://emea01.safelinks.protection.outlook.com/?url=https%3A%2F%2Flwn.net%2FArticles%2F635905%2F&data=01%7C01%7Cdiana.craciun%40nxp.com%7C6b0c6c879af64718a21908d4d81d534e%7C686ea1d3bc2b4c6fa92cd99c5c301635%7C0&sdata=bpYMMqajWzgzdbdQgy%2FUYR7y%2BswyvwE%2BqFzs7wdIkkA%3D&reserved=0). I guess that we may have other > > >> platform devices that are using MSIs in the future. > > >> > > >> Thanks, > > >> Diana > > >> > > >> > > > Don't have the time to explore NXP in depth, sorry - there's > > > a lot of complexity there. > > > Could you maybe stick some bits to specify bus type in there? > > > It just looks very wrong to push low level things like this > > > that users have no interest in up the stack. > > > > > Let's generalize the problem a little bit, the NXP details just does not > > matter much. The problem we have is the following: > > > > The GIC-ITS, the ARM MSI controller is using deviceIDs in order to remap > > the interrupts. Each device which is expected to send MSIs has a > > deviceID associated with it. These deviceIDs are configured into devices > > by software/firmware. There is support in the device tree to specify the > > correlation between requesterID and deviceID: > > > > "msi-map: Maps a Requester ID to an MSI controller and associated > > msi-specifier data. The property is an arbitrary number of tuples of > > (rid-base,msi-controller,msi-base,length)" > > (https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/Documentation/devicetree/bindings/pci/pci-msi.txt) > > > > Our problem is that we have to allocate these deviceIDs in QEMU as well > > and we have to ensure that they are unique. Currently, for PCI, the > > assumption requesterID=deviceID is made which will no longer be true in > > case other devices are added. So we need a way (preferable a general > > one) to allocate these IDs to different devices in the system in a > > consistent way which will ensure that two devices do not share the same ID. > > My question would be, do other types of devices that are there > right now have some kind of ID like the requester ID? > If so I would say just use that, and set high bits in the device ID > to specify the type (e.g. 00 for pci, etc). > > > IMHO if possible that is preferable to pushing this up to users. > > > > The reason I put this ID into the controller itself is because on real > > hardware is actually programmed into the controller. It is needed (for > > example) when the MSIs are sent. > > > > Thanks, > > > > Diana > > > > IIUC what happens on real hardware is controller maps each requester ID > (or presumably other source ID in the request) to the device ID, > and the mapping is internal to controller. > If you wanted a lot of flexibility then looks like you could pass this > mapping to controllers, but is it really necessary? > Why don't we build a mapping that's convenient for us? > Hi, I agree with you for boards that are defined by QEMU (like the ARM virt board). We can pick a convenient scheme and avoid too much user interaction. But when we model real SoCs, the IDs and the way bridges convert these IDs needs to match real HW. Otherwise guest SW will not work unmodified. To make this work, users should not need to be involved though, it's the machine and SoC modules that should instantiate the necessary handling of it, IMO. Cheers, Edgar From MAILER-DAEMON Tue Aug 01 05:34:24 2017 Received: from list by lists.gnu.org with archive (Exim 4.71) id 1dcTZI-0007GG-RJ for mharc-qemu-arm@gnu.org; Tue, 01 Aug 2017 05:34:24 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:38071) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dcTZG-0007Fq-92 for qemu-arm@nongnu.org; Tue, 01 Aug 2017 05:34:23 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dcTZD-00017u-10 for qemu-arm@nongnu.org; Tue, 01 Aug 2017 05:34:22 -0400 Received: from mx1.redhat.com ([209.132.183.28]:49712) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1dcTZC-00017H-OA; Tue, 01 Aug 2017 05:34:18 -0400 Received: from smtp.corp.redhat.com (int-mx01.intmail.prod.int.phx2.redhat.com [10.5.11.11]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id 7C7EF10794A; Tue, 1 Aug 2017 09:34:17 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mx1.redhat.com 7C7EF10794A Authentication-Results: ext-mx04.extmail.prod.ext.phx2.redhat.com; dmarc=none (p=none dis=none) header.from=redhat.com Authentication-Results: ext-mx04.extmail.prod.ext.phx2.redhat.com; spf=fail smtp.mailfrom=eric.auger@redhat.com Received: from localhost.localdomain.com (ovpn-116-181.ams2.redhat.com [10.36.116.181]) by smtp.corp.redhat.com (Postfix) with ESMTP id 78D5C6047A; Tue, 1 Aug 2017 09:34:03 +0000 (UTC) From: Eric Auger To: eric.auger.pro@gmail.com, eric.auger@redhat.com, peter.maydell@linaro.org, alex.williamson@redhat.com, mst@redhat.com, qemu-arm@nongnu.org, qemu-devel@nongnu.org, jean-philippe.brucker@arm.com Cc: will.deacon@arm.com, kevin.tian@intel.com, marc.zyngier@arm.com, christoffer.dall@linaro.org, drjones@redhat.com, wei@redhat.com, tn@semihalf.com, bharat.bhushan@nxp.com, peterx@redhat.com Date: Tue, 1 Aug 2017 11:33:06 +0200 Message-Id: <1501579994-3320-1-git-send-email-eric.auger@redhat.com> X-Scanned-By: MIMEDefang 2.79 on 10.5.11.11 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.28]); Tue, 01 Aug 2017 09:34:17 +0000 (UTC) X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.132.183.28 Subject: [Qemu-arm] [RFC v3 0/8] VIRTIO-IOMMU device X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 01 Aug 2017 09:34:23 -0000 This series implements the virtio-iommu device. This v3 mostly is a rebase on top of v2.10-rc0 that uses IOMMUMmeoryRegion plus some small fixes. This is a proof of concept based on the virtio-iommu specification written by Jean-Philippe Brucker [1]. The device gets instantiated using the "-device virtio-iommu-device" option. It currently works with ARM virt machine only, as the machine must handle the dt binding between the virtio-mmio "iommu" node and the PCI host bridge node. ACPI booting is not yet supported. Best Regards Eric This series can be found at: https://github.com/eauger/qemu/tree/v2.10.0-rc0-virtio-iommu-rfcv3 References: [1] [RFC 0/3] virtio-iommu: a paravirtualized IOMMU, [2] [RFC PATCH linux] iommu: Add virtio-iommu driver [3] [RFC PATCH kvmtool 00/15] Add virtio-iommu Testing: - >= 4.12 guest kernel + virtio-iommu driver [2] - guest using a virtio-net-pci device: ,vhost=off,iommu_platform,disable-modern=off,disable-legacy=on History: v2 -> v3: - rebase on top of 2.10-rc0 and especially [PATCH qemu v9 0/2] memory/iommu: QOM'fy IOMMU MemoryRegion - add mutex init - fix as->mappings deletion using g_tree_ref/unref - when a dev is attached whereas it is already attached to another address space, first detach it - fix some error values - page_sizes = TARGET_PAGE_MASK; - I haven't changed the unmap() semantics yet, waiting for the next virtio-iommu spec revision. v1 -> v2: - fix redifinition of viommu_as typedef Eric Auger (8): update-linux-headers: import virtio_iommu.h linux-headers: Update for virtio-iommu virtio_iommu: add skeleton virtio-iommu: Decode the command payload virtio_iommu: Add the iommu regions virtio-iommu: Implement the translation and commands hw/arm/virt: Add 2.10 machine type hw/arm/virt: Add virtio-iommu the virt board hw/arm/virt.c | 116 ++++- hw/virtio/Makefile.objs | 1 + hw/virtio/trace-events | 14 + hw/virtio/virtio-iommu.c | 670 ++++++++++++++++++++++++++ include/hw/arm/virt.h | 5 + include/hw/virtio/virtio-iommu.h | 61 +++ include/standard-headers/linux/virtio_ids.h | 1 + include/standard-headers/linux/virtio_iommu.h | 142 ++++++ linux-headers/linux/virtio_iommu.h | 1 + scripts/update-linux-headers.sh | 3 + 10 files changed, 1005 insertions(+), 9 deletions(-) create mode 100644 hw/virtio/virtio-iommu.c create mode 100644 include/hw/virtio/virtio-iommu.h create mode 100644 include/standard-headers/linux/virtio_iommu.h create mode 100644 linux-headers/linux/virtio_iommu.h -- 2.5.5 From MAILER-DAEMON Tue Aug 01 05:34:26 2017 Received: from list by lists.gnu.org with archive (Exim 4.71) id 1dcTZJ-0007H7-VG for mharc-qemu-arm@gnu.org; Tue, 01 Aug 2017 05:34:25 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:38084) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dcTZH-0007Fy-MD for qemu-arm@nongnu.org; Tue, 01 Aug 2017 05:34:24 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dcTZG-0001By-R0 for qemu-arm@nongnu.org; Tue, 01 Aug 2017 05:34:23 -0400 Received: from mx1.redhat.com ([209.132.183.28]:46272) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1dcTZG-0001BF-LX; Tue, 01 Aug 2017 05:34:22 -0400 Received: from smtp.corp.redhat.com (int-mx01.intmail.prod.int.phx2.redhat.com [10.5.11.11]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id 7FDFDC04B071; Tue, 1 Aug 2017 09:34:21 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mx1.redhat.com 7FDFDC04B071 Authentication-Results: ext-mx08.extmail.prod.ext.phx2.redhat.com; dmarc=none (p=none dis=none) header.from=redhat.com Authentication-Results: ext-mx08.extmail.prod.ext.phx2.redhat.com; spf=fail smtp.mailfrom=eric.auger@redhat.com Received: from localhost.localdomain.com (ovpn-116-181.ams2.redhat.com [10.36.116.181]) by smtp.corp.redhat.com (Postfix) with ESMTP id CF1826017B; Tue, 1 Aug 2017 09:34:17 +0000 (UTC) From: Eric Auger To: eric.auger.pro@gmail.com, eric.auger@redhat.com, peter.maydell@linaro.org, alex.williamson@redhat.com, mst@redhat.com, qemu-arm@nongnu.org, qemu-devel@nongnu.org, jean-philippe.brucker@arm.com Cc: will.deacon@arm.com, kevin.tian@intel.com, marc.zyngier@arm.com, christoffer.dall@linaro.org, drjones@redhat.com, wei@redhat.com, tn@semihalf.com, bharat.bhushan@nxp.com, peterx@redhat.com Date: Tue, 1 Aug 2017 11:33:07 +0200 Message-Id: <1501579994-3320-2-git-send-email-eric.auger@redhat.com> In-Reply-To: <1501579994-3320-1-git-send-email-eric.auger@redhat.com> References: <1501579994-3320-1-git-send-email-eric.auger@redhat.com> X-Scanned-By: MIMEDefang 2.79 on 10.5.11.11 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.32]); Tue, 01 Aug 2017 09:34:21 +0000 (UTC) X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.132.183.28 Subject: [Qemu-arm] [RFC v3 1/8] update-linux-headers: import virtio_iommu.h X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 01 Aug 2017 09:34:24 -0000 Update the script to update the virtio_iommu.h header. Signed-off-by: Eric Auger --- scripts/update-linux-headers.sh | 3 +++ 1 file changed, 3 insertions(+) diff --git a/scripts/update-linux-headers.sh b/scripts/update-linux-headers.sh index 2f906c4..03f6712 100755 --- a/scripts/update-linux-headers.sh +++ b/scripts/update-linux-headers.sh @@ -134,6 +134,9 @@ EOF cat <$output/linux-headers/linux/virtio_config.h #include "standard-headers/linux/virtio_config.h" EOF +cat <$output/linux-headers/linux/virtio_iommu.h +#include "standard-headers/linux/virtio_iommu.h" +EOF cat <$output/linux-headers/linux/virtio_ring.h #include "standard-headers/linux/virtio_ring.h" EOF -- 2.5.5 From MAILER-DAEMON Tue Aug 01 05:34:42 2017 Received: from list by lists.gnu.org with archive (Exim 4.71) id 1dcTZa-0007Ti-My for mharc-qemu-arm@gnu.org; Tue, 01 Aug 2017 05:34:42 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:38139) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dcTZW-0007QD-9X for qemu-arm@nongnu.org; Tue, 01 Aug 2017 05:34:41 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dcTZU-0001Sx-NE for qemu-arm@nongnu.org; Tue, 01 Aug 2017 05:34:38 -0400 Received: from mx1.redhat.com ([209.132.183.28]:44160) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1dcTZU-0001QL-Ei; Tue, 01 Aug 2017 05:34:36 -0400 Received: from smtp.corp.redhat.com (int-mx01.intmail.prod.int.phx2.redhat.com [10.5.11.11]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id 42E8512E52D; Tue, 1 Aug 2017 09:34:35 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mx1.redhat.com 42E8512E52D Authentication-Results: ext-mx02.extmail.prod.ext.phx2.redhat.com; dmarc=none (p=none dis=none) header.from=redhat.com Authentication-Results: ext-mx02.extmail.prod.ext.phx2.redhat.com; spf=fail smtp.mailfrom=eric.auger@redhat.com Received: from localhost.localdomain.com (ovpn-116-181.ams2.redhat.com [10.36.116.181]) by smtp.corp.redhat.com (Postfix) with ESMTP id DCEBA60186; Tue, 1 Aug 2017 09:34:21 +0000 (UTC) From: Eric Auger To: eric.auger.pro@gmail.com, eric.auger@redhat.com, peter.maydell@linaro.org, alex.williamson@redhat.com, mst@redhat.com, qemu-arm@nongnu.org, qemu-devel@nongnu.org, jean-philippe.brucker@arm.com Cc: will.deacon@arm.com, kevin.tian@intel.com, marc.zyngier@arm.com, christoffer.dall@linaro.org, drjones@redhat.com, wei@redhat.com, tn@semihalf.com, bharat.bhushan@nxp.com, peterx@redhat.com Date: Tue, 1 Aug 2017 11:33:08 +0200 Message-Id: <1501579994-3320-3-git-send-email-eric.auger@redhat.com> In-Reply-To: <1501579994-3320-1-git-send-email-eric.auger@redhat.com> References: <1501579994-3320-1-git-send-email-eric.auger@redhat.com> X-Scanned-By: MIMEDefang 2.79 on 10.5.11.11 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.26]); Tue, 01 Aug 2017 09:34:35 +0000 (UTC) X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.132.183.28 Subject: [Qemu-arm] [RFC v3 2/8] linux-headers: Update for virtio-iommu X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 01 Aug 2017 09:34:41 -0000 This is a partial linux header update against Jean-Philippe's branch: git://linux-arm.org/linux-jpb.git virtio-iommu/base (unstable) Signed-off-by: Eric Auger --- include/standard-headers/linux/virtio_ids.h | 1 + include/standard-headers/linux/virtio_iommu.h | 142 ++++++++++++++++++++++++++ linux-headers/linux/virtio_iommu.h | 1 + 3 files changed, 144 insertions(+) create mode 100644 include/standard-headers/linux/virtio_iommu.h create mode 100644 linux-headers/linux/virtio_iommu.h diff --git a/include/standard-headers/linux/virtio_ids.h b/include/standard-headers/linux/virtio_ids.h index 6d5c3b2..934ed3d 100644 --- a/include/standard-headers/linux/virtio_ids.h +++ b/include/standard-headers/linux/virtio_ids.h @@ -43,5 +43,6 @@ #define VIRTIO_ID_INPUT 18 /* virtio input */ #define VIRTIO_ID_VSOCK 19 /* virtio vsock transport */ #define VIRTIO_ID_CRYPTO 20 /* virtio crypto */ +#define VIRTIO_ID_IOMMU 61216 /* virtio IOMMU (temporary) */ #endif /* _LINUX_VIRTIO_IDS_H */ diff --git a/include/standard-headers/linux/virtio_iommu.h b/include/standard-headers/linux/virtio_iommu.h new file mode 100644 index 0000000..e139587 --- /dev/null +++ b/include/standard-headers/linux/virtio_iommu.h @@ -0,0 +1,142 @@ +/* + * Copyright (C) 2017 ARM Ltd. + * + * This header is BSD licensed so anyone can use the definitions + * to implement compatible drivers/servers: + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of ARM Ltd. nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL IBM OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT + * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ +#ifndef _LINUX_VIRTIO_IOMMU_H +#define _LINUX_VIRTIO_IOMMU_H + +/* Feature bits */ +#define VIRTIO_IOMMU_F_INPUT_RANGE 0 +#define VIRTIO_IOMMU_F_IOASID_BITS 1 +#define VIRTIO_IOMMU_F_MAP_UNMAP 2 +#define VIRTIO_IOMMU_F_BYPASS 3 + +QEMU_PACKED +struct virtio_iommu_config { + /* Supported page sizes */ + uint64_t page_sizes; + struct virtio_iommu_range { + uint64_t start; + uint64_t end; + } input_range; + uint8_t ioasid_bits; +}; + +/* Request types */ +#define VIRTIO_IOMMU_T_ATTACH 0x01 +#define VIRTIO_IOMMU_T_DETACH 0x02 +#define VIRTIO_IOMMU_T_MAP 0x03 +#define VIRTIO_IOMMU_T_UNMAP 0x04 + +/* Status types */ +#define VIRTIO_IOMMU_S_OK 0x00 +#define VIRTIO_IOMMU_S_IOERR 0x01 +#define VIRTIO_IOMMU_S_UNSUPP 0x02 +#define VIRTIO_IOMMU_S_DEVERR 0x03 +#define VIRTIO_IOMMU_S_INVAL 0x04 +#define VIRTIO_IOMMU_S_RANGE 0x05 +#define VIRTIO_IOMMU_S_NOENT 0x06 +#define VIRTIO_IOMMU_S_FAULT 0x07 + +QEMU_PACKED +struct virtio_iommu_req_head { + uint8_t type; + uint8_t reserved[3]; +}; + +QEMU_PACKED +struct virtio_iommu_req_tail { + uint8_t status; + uint8_t reserved[3]; +}; + +QEMU_PACKED +struct virtio_iommu_req_attach { + struct virtio_iommu_req_head head; + + uint32_t address_space; + uint32_t device; + uint32_t reserved; + + struct virtio_iommu_req_tail tail; +}; + +QEMU_PACKED +struct virtio_iommu_req_detach { + struct virtio_iommu_req_head head; + + uint32_t device; + uint32_t reserved; + + struct virtio_iommu_req_tail tail; +}; + +#define VIRTIO_IOMMU_MAP_F_READ (1 << 0) +#define VIRTIO_IOMMU_MAP_F_WRITE (1 << 1) +#define VIRTIO_IOMMU_MAP_F_EXEC (1 << 2) + +#define VIRTIO_IOMMU_MAP_F_MASK (VIRTIO_IOMMU_MAP_F_READ | \ + VIRTIO_IOMMU_MAP_F_WRITE | \ + VIRTIO_IOMMU_MAP_F_EXEC) + +QEMU_PACKED +struct virtio_iommu_req_map { + struct virtio_iommu_req_head head; + + uint32_t address_space; + uint32_t flags; + uint64_t virt_addr; + uint64_t phys_addr; + uint64_t size; + + struct virtio_iommu_req_tail tail; +}; + +QEMU_PACKED +struct virtio_iommu_req_unmap { + struct virtio_iommu_req_head head; + + uint32_t address_space; + uint32_t flags; + uint64_t virt_addr; + uint64_t size; + + struct virtio_iommu_req_tail tail; +}; + +union virtio_iommu_req { + struct virtio_iommu_req_head head; + + struct virtio_iommu_req_attach attach; + struct virtio_iommu_req_detach detach; + struct virtio_iommu_req_map map; + struct virtio_iommu_req_unmap unmap; +}; + +#endif diff --git a/linux-headers/linux/virtio_iommu.h b/linux-headers/linux/virtio_iommu.h new file mode 100644 index 0000000..2dc4609 --- /dev/null +++ b/linux-headers/linux/virtio_iommu.h @@ -0,0 +1 @@ +#include "standard-headers/linux/virtio_iommu.h" -- 2.5.5 From MAILER-DAEMON Tue Aug 01 05:34:46 2017 Received: from list by lists.gnu.org with archive (Exim 4.71) id 1dcTZe-0007X4-NB for mharc-qemu-arm@gnu.org; Tue, 01 Aug 2017 05:34:46 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:38161) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dcTZb-0007UG-1L for qemu-arm@nongnu.org; Tue, 01 Aug 2017 05:34:44 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dcTZZ-0001ZI-9X for qemu-arm@nongnu.org; Tue, 01 Aug 2017 05:34:43 -0400 Received: from mx1.redhat.com ([209.132.183.28]:47446) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1dcTZY-0001YH-V4; Tue, 01 Aug 2017 05:34:41 -0400 Received: from smtp.corp.redhat.com (int-mx01.intmail.prod.int.phx2.redhat.com [10.5.11.11]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id D03158FF62; Tue, 1 Aug 2017 09:34:39 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mx1.redhat.com D03158FF62 Authentication-Results: ext-mx06.extmail.prod.ext.phx2.redhat.com; dmarc=none (p=none dis=none) header.from=redhat.com Authentication-Results: ext-mx06.extmail.prod.ext.phx2.redhat.com; spf=fail smtp.mailfrom=eric.auger@redhat.com Received: from localhost.localdomain.com (ovpn-116-181.ams2.redhat.com [10.36.116.181]) by smtp.corp.redhat.com (Postfix) with ESMTP id 9C47460176; Tue, 1 Aug 2017 09:34:35 +0000 (UTC) From: Eric Auger To: eric.auger.pro@gmail.com, eric.auger@redhat.com, peter.maydell@linaro.org, alex.williamson@redhat.com, mst@redhat.com, qemu-arm@nongnu.org, qemu-devel@nongnu.org, jean-philippe.brucker@arm.com Cc: will.deacon@arm.com, kevin.tian@intel.com, marc.zyngier@arm.com, christoffer.dall@linaro.org, drjones@redhat.com, wei@redhat.com, tn@semihalf.com, bharat.bhushan@nxp.com, peterx@redhat.com Date: Tue, 1 Aug 2017 11:33:09 +0200 Message-Id: <1501579994-3320-4-git-send-email-eric.auger@redhat.com> In-Reply-To: <1501579994-3320-1-git-send-email-eric.auger@redhat.com> References: <1501579994-3320-1-git-send-email-eric.auger@redhat.com> X-Scanned-By: MIMEDefang 2.79 on 10.5.11.11 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.30]); Tue, 01 Aug 2017 09:34:40 +0000 (UTC) X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.132.183.28 Subject: [Qemu-arm] [RFC v3 3/8] virtio_iommu: add skeleton X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 01 Aug 2017 09:34:44 -0000 This patchs adds the skeleton for the virtio-iommu device. Signed-off-by: Eric Auger --- v2 -> v3: - rebase on 2.10-rc0, ie. use IOMMUMemoryRegion and remove iommu_ops. - advertise VIRTIO_IOMMU_F_MAP_UNMAP feature - page_sizes set to TARGET_PAGE_SIZE --- hw/virtio/Makefile.objs | 1 + hw/virtio/virtio-iommu.c | 248 +++++++++++++++++++++++++++++++++++++++ include/hw/virtio/virtio-iommu.h | 59 ++++++++++ 3 files changed, 308 insertions(+) create mode 100644 hw/virtio/virtio-iommu.c create mode 100644 include/hw/virtio/virtio-iommu.h diff --git a/hw/virtio/Makefile.objs b/hw/virtio/Makefile.objs index 765d363..8967a4a 100644 --- a/hw/virtio/Makefile.objs +++ b/hw/virtio/Makefile.objs @@ -6,6 +6,7 @@ common-obj-y += virtio-mmio.o obj-y += virtio.o virtio-balloon.o obj-$(CONFIG_LINUX) += vhost.o vhost-backend.o vhost-user.o +obj-$(CONFIG_LINUX) += virtio-iommu.o obj-$(CONFIG_VHOST_VSOCK) += vhost-vsock.o obj-y += virtio-crypto.o obj-$(CONFIG_VIRTIO_PCI) += virtio-crypto-pci.o diff --git a/hw/virtio/virtio-iommu.c b/hw/virtio/virtio-iommu.c new file mode 100644 index 0000000..4570e19 --- /dev/null +++ b/hw/virtio/virtio-iommu.c @@ -0,0 +1,248 @@ +/* + * virtio-iommu device + * + * Copyright (c) 2017 Red Hat, Inc. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2 or later, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program. If not, see . + * + */ + +#include "qemu/osdep.h" +#include "qemu/iov.h" +#include "qemu-common.h" +#include "hw/virtio/virtio.h" +#include "sysemu/kvm.h" +#include "qapi-event.h" +#include "trace.h" + +#include "standard-headers/linux/virtio_ids.h" +#include + +#include "hw/virtio/virtio-bus.h" +#include "hw/virtio/virtio-access.h" +#include "hw/virtio/virtio-iommu.h" + +/* Max size */ +#define VIOMMU_DEFAULT_QUEUE_SIZE 256 + +static int virtio_iommu_handle_attach(VirtIOIOMMU *s, + struct iovec *iov, + unsigned int iov_cnt) +{ + return -ENOENT; +} +static int virtio_iommu_handle_detach(VirtIOIOMMU *s, + struct iovec *iov, + unsigned int iov_cnt) +{ + return -ENOENT; +} +static int virtio_iommu_handle_map(VirtIOIOMMU *s, + struct iovec *iov, + unsigned int iov_cnt) +{ + return -ENOENT; +} +static int virtio_iommu_handle_unmap(VirtIOIOMMU *s, + struct iovec *iov, + unsigned int iov_cnt) +{ + return -ENOENT; +} + +static void virtio_iommu_handle_command(VirtIODevice *vdev, VirtQueue *vq) +{ + VirtIOIOMMU *s = VIRTIO_IOMMU(vdev); + VirtQueueElement *elem; + struct virtio_iommu_req_head head; + struct virtio_iommu_req_tail tail; + unsigned int iov_cnt; + struct iovec *iov; + size_t sz; + + for (;;) { + elem = virtqueue_pop(vq, sizeof(VirtQueueElement)); + if (!elem) { + return; + } + + if (iov_size(elem->in_sg, elem->in_num) < sizeof(tail) || + iov_size(elem->out_sg, elem->out_num) < sizeof(head)) { + virtio_error(vdev, "virtio-iommu erroneous head or tail"); + virtqueue_detach_element(vq, elem, 0); + g_free(elem); + break; + } + + iov_cnt = elem->out_num; + iov = g_memdup(elem->out_sg, sizeof(struct iovec) * elem->out_num); + sz = iov_to_buf(iov, iov_cnt, 0, &head, sizeof(head)); + if (sz != sizeof(head)) { + tail.status = VIRTIO_IOMMU_S_UNSUPP; + } + qemu_mutex_lock(&s->mutex); + switch (head.type) { + case VIRTIO_IOMMU_T_ATTACH: + tail.status = virtio_iommu_handle_attach(s, iov, iov_cnt); + break; + case VIRTIO_IOMMU_T_DETACH: + tail.status = virtio_iommu_handle_detach(s, iov, iov_cnt); + break; + case VIRTIO_IOMMU_T_MAP: + tail.status = virtio_iommu_handle_map(s, iov, iov_cnt); + break; + case VIRTIO_IOMMU_T_UNMAP: + tail.status = virtio_iommu_handle_unmap(s, iov, iov_cnt); + break; + default: + tail.status = VIRTIO_IOMMU_S_UNSUPP; + } + qemu_mutex_unlock(&s->mutex); + + sz = iov_from_buf(elem->in_sg, elem->in_num, 0, + &tail, sizeof(tail)); + assert(sz == sizeof(tail)); + + virtqueue_push(vq, elem, sizeof(tail)); + virtio_notify(vdev, vq); + g_free(elem); + } +} + +static void virtio_iommu_get_config(VirtIODevice *vdev, uint8_t *config_data) +{ + VirtIOIOMMU *dev = VIRTIO_IOMMU(vdev); + + memcpy(config_data, &dev->config, sizeof(struct virtio_iommu_config)); +} + +static void virtio_iommu_set_config(VirtIODevice *vdev, + const uint8_t *config_data) +{ + VirtIOIOMMU *dev = VIRTIO_IOMMU(vdev); + struct virtio_iommu_config config; + + memcpy(&config, config_data, sizeof(struct virtio_iommu_config)); + + dev->config.page_sizes = le64_to_cpu(config.page_sizes); + dev->config.input_range.end = le64_to_cpu(config.input_range.end); +} + +static uint64_t virtio_iommu_get_features(VirtIODevice *vdev, uint64_t f, + Error **errp) +{ + VirtIOIOMMU *dev = VIRTIO_IOMMU(vdev); + f |= dev->host_features; + virtio_add_feature(&f, VIRTIO_RING_F_EVENT_IDX); + virtio_add_feature(&f, VIRTIO_RING_F_INDIRECT_DESC); + virtio_add_feature(&f, VIRTIO_IOMMU_F_INPUT_RANGE); + virtio_add_feature(&f, VIRTIO_IOMMU_F_MAP_UNMAP); + return f; +} + +static int virtio_iommu_post_load_device(void *opaque, int version_id) +{ + return 0; +} + +static const VMStateDescription vmstate_virtio_iommu_device = { + .name = "virtio-iommu-device", + .version_id = 1, + .minimum_version_id = 1, + .post_load = virtio_iommu_post_load_device, + .fields = (VMStateField[]) { + VMSTATE_END_OF_LIST() + }, +}; + +static void virtio_iommu_device_realize(DeviceState *dev, Error **errp) +{ + VirtIODevice *vdev = VIRTIO_DEVICE(dev); + VirtIOIOMMU *s = VIRTIO_IOMMU(dev); + + virtio_init(vdev, "virtio-iommu", VIRTIO_ID_IOMMU, + sizeof(struct virtio_iommu_config)); + + s->vq = virtio_add_queue(vdev, VIOMMU_DEFAULT_QUEUE_SIZE, + virtio_iommu_handle_command); + + s->config.page_sizes = TARGET_PAGE_MASK; + s->config.input_range.end = -1UL; +} + +static void virtio_iommu_device_unrealize(DeviceState *dev, Error **errp) +{ + VirtIODevice *vdev = VIRTIO_DEVICE(dev); + + virtio_cleanup(vdev); +} + +static void virtio_iommu_device_reset(VirtIODevice *vdev) +{ +} + +static void virtio_iommu_set_status(VirtIODevice *vdev, uint8_t status) +{ +} + +static void virtio_iommu_instance_init(Object *obj) +{ +} + +static const VMStateDescription vmstate_virtio_iommu = { + .name = "virtio-iommu", + .minimum_version_id = 1, + .version_id = 1, + .fields = (VMStateField[]) { + VMSTATE_VIRTIO_DEVICE, + VMSTATE_END_OF_LIST() + }, +}; + +static Property virtio_iommu_properties[] = { + DEFINE_PROP_END_OF_LIST(), +}; + +static void virtio_iommu_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + VirtioDeviceClass *vdc = VIRTIO_DEVICE_CLASS(klass); + + dc->props = virtio_iommu_properties; + dc->vmsd = &vmstate_virtio_iommu; + + set_bit(DEVICE_CATEGORY_MISC, dc->categories); + vdc->realize = virtio_iommu_device_realize; + vdc->unrealize = virtio_iommu_device_unrealize; + vdc->reset = virtio_iommu_device_reset; + vdc->get_config = virtio_iommu_get_config; + vdc->set_config = virtio_iommu_set_config; + vdc->get_features = virtio_iommu_get_features; + vdc->set_status = virtio_iommu_set_status; + vdc->vmsd = &vmstate_virtio_iommu_device; +} + +static const TypeInfo virtio_iommu_info = { + .name = TYPE_VIRTIO_IOMMU, + .parent = TYPE_VIRTIO_DEVICE, + .instance_size = sizeof(VirtIOIOMMU), + .instance_init = virtio_iommu_instance_init, + .class_init = virtio_iommu_class_init, +}; + +static void virtio_register_types(void) +{ + type_register_static(&virtio_iommu_info); +} + +type_init(virtio_register_types) diff --git a/include/hw/virtio/virtio-iommu.h b/include/hw/virtio/virtio-iommu.h new file mode 100644 index 0000000..6716cdb --- /dev/null +++ b/include/hw/virtio/virtio-iommu.h @@ -0,0 +1,59 @@ +/* + * virtio-iommu device + * + * Copyright (c) 2017 Red Hat, Inc. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2 or later, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program. If not, see . + * + */ + +#ifndef QEMU_VIRTIO_IOMMU_H +#define QEMU_VIRTIO_IOMMU_H + +#include "standard-headers/linux/virtio_iommu.h" +#include "hw/virtio/virtio.h" +#include "hw/pci/pci.h" + +#define TYPE_VIRTIO_IOMMU "virtio-iommu-device" +#define VIRTIO_IOMMU(obj) \ + OBJECT_CHECK(VirtIOIOMMU, (obj), TYPE_VIRTIO_IOMMU) + +#define IOMMU_PCI_BUS_MAX 256 +#define IOMMU_PCI_DEVFN_MAX 256 + +typedef struct IOMMUDevice { + void *viommu; + PCIBus *bus; + int devfn; + IOMMUMemoryRegion iommu_mr; + AddressSpace as; +} IOMMUDevice; + +typedef struct IOMMUPciBus { + PCIBus *bus; + IOMMUDevice *pbdev[0]; /* Parent array is sparse, so dynamically alloc */ +} IOMMUPciBus; + +typedef struct VirtIOIOMMU { + VirtIODevice parent_obj; + VirtQueue *vq; + struct virtio_iommu_config config; + uint32_t host_features; + GHashTable *as_by_busptr; + IOMMUPciBus *as_by_bus_num[IOMMU_PCI_BUS_MAX]; + GTree *address_spaces; + QemuMutex mutex; + GTree *devices; +} VirtIOIOMMU; + +#endif -- 2.5.5 From MAILER-DAEMON Tue Aug 01 05:35:01 2017 Received: from list by lists.gnu.org with archive (Exim 4.71) id 1dcTZs-0007jx-TX for mharc-qemu-arm@gnu.org; Tue, 01 Aug 2017 05:35:00 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:38250) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dcTZp-0007h8-Qa for qemu-arm@nongnu.org; Tue, 01 Aug 2017 05:34:59 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dcTZm-0001qT-FC for qemu-arm@nongnu.org; Tue, 01 Aug 2017 05:34:57 -0400 Received: from mx1.redhat.com ([209.132.183.28]:49715) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1dcTZm-0001pu-6c; Tue, 01 Aug 2017 05:34:54 -0400 Received: from smtp.corp.redhat.com (int-mx01.intmail.prod.int.phx2.redhat.com [10.5.11.11]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id 149DB166A68; Tue, 1 Aug 2017 09:34:53 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mx1.redhat.com 149DB166A68 Authentication-Results: ext-mx01.extmail.prod.ext.phx2.redhat.com; dmarc=none (p=none dis=none) header.from=redhat.com Authentication-Results: ext-mx01.extmail.prod.ext.phx2.redhat.com; spf=fail smtp.mailfrom=eric.auger@redhat.com Received: from localhost.localdomain.com (ovpn-116-181.ams2.redhat.com [10.36.116.181]) by smtp.corp.redhat.com (Postfix) with ESMTP id 2EEF36047A; Tue, 1 Aug 2017 09:34:40 +0000 (UTC) From: Eric Auger To: eric.auger.pro@gmail.com, eric.auger@redhat.com, peter.maydell@linaro.org, alex.williamson@redhat.com, mst@redhat.com, qemu-arm@nongnu.org, qemu-devel@nongnu.org, jean-philippe.brucker@arm.com Cc: will.deacon@arm.com, kevin.tian@intel.com, marc.zyngier@arm.com, christoffer.dall@linaro.org, drjones@redhat.com, wei@redhat.com, tn@semihalf.com, bharat.bhushan@nxp.com, peterx@redhat.com Date: Tue, 1 Aug 2017 11:33:10 +0200 Message-Id: <1501579994-3320-5-git-send-email-eric.auger@redhat.com> In-Reply-To: <1501579994-3320-1-git-send-email-eric.auger@redhat.com> References: <1501579994-3320-1-git-send-email-eric.auger@redhat.com> X-Scanned-By: MIMEDefang 2.79 on 10.5.11.11 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.25]); Tue, 01 Aug 2017 09:34:53 +0000 (UTC) X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.132.183.28 Subject: [Qemu-arm] [RFC v3 4/8] virtio-iommu: Decode the command payload X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 01 Aug 2017 09:34:59 -0000 This patch adds the command payload decoding and introduces the functions that will do the actual command handling. Those functions are not yet implemented. Signed-off-by: Eric Auger --- hw/virtio/trace-events | 7 ++++ hw/virtio/virtio-iommu.c | 97 ++++++++++++++++++++++++++++++++++++++++++++++-- 2 files changed, 100 insertions(+), 4 deletions(-) diff --git a/hw/virtio/trace-events b/hw/virtio/trace-events index e24d8fa..fba1da6 100644 --- a/hw/virtio/trace-events +++ b/hw/virtio/trace-events @@ -25,3 +25,10 @@ virtio_balloon_handle_output(const char *name, uint64_t gpa) "section name: %s g virtio_balloon_get_config(uint32_t num_pages, uint32_t actual) "num_pages: %d actual: %d" virtio_balloon_set_config(uint32_t actual, uint32_t oldactual) "actual: %d oldactual: %d" virtio_balloon_to_target(uint64_t target, uint32_t num_pages) "balloon target: %"PRIx64" num_pages: %d" + +# hw/virtio/virtio-iommu.c +# +virtio_iommu_attach(uint32_t as, uint32_t dev, uint32_t flags) "as=%d dev=%d flags=%d" +virtio_iommu_detach(uint32_t dev, uint32_t flags) "dev=%d flags=%d" +virtio_iommu_map(uint32_t as, uint64_t phys_addr, uint64_t virt_addr, uint64_t size, uint32_t flags) "as= %d phys_addr=0x%"PRIx64" virt_addr=0x%"PRIx64" size=0x%"PRIx64" flags=%d" +virtio_iommu_unmap(uint32_t as, uint64_t virt_addr, uint64_t size, uint32_t reserved) "as= %d virt_addr=0x%"PRIx64" size=0x%"PRIx64" reserved=%d" diff --git a/hw/virtio/virtio-iommu.c b/hw/virtio/virtio-iommu.c index 4570e19..6f5b71c 100644 --- a/hw/virtio/virtio-iommu.c +++ b/hw/virtio/virtio-iommu.c @@ -35,29 +35,118 @@ /* Max size */ #define VIOMMU_DEFAULT_QUEUE_SIZE 256 +static int virtio_iommu_attach(VirtIOIOMMU *s, + struct virtio_iommu_req_attach *req) +{ + uint32_t asid = le32_to_cpu(req->address_space); + uint32_t devid = le32_to_cpu(req->device); + uint32_t reserved = le32_to_cpu(req->reserved); + + trace_virtio_iommu_attach(asid, devid, reserved); + + return VIRTIO_IOMMU_S_UNSUPP; +} + +static int virtio_iommu_detach(VirtIOIOMMU *s, + struct virtio_iommu_req_detach *req) +{ + uint32_t devid = le32_to_cpu(req->device); + uint32_t reserved = le32_to_cpu(req->reserved); + + trace_virtio_iommu_detach(devid, reserved); + + return VIRTIO_IOMMU_S_UNSUPP; +} + +static int virtio_iommu_map(VirtIOIOMMU *s, + struct virtio_iommu_req_map *req) +{ + uint32_t asid = le32_to_cpu(req->address_space); + uint64_t phys_addr = le64_to_cpu(req->phys_addr); + uint64_t virt_addr = le64_to_cpu(req->virt_addr); + uint64_t size = le64_to_cpu(req->size); + uint32_t flags = le32_to_cpu(req->flags); + + trace_virtio_iommu_map(asid, phys_addr, virt_addr, size, flags); + + return VIRTIO_IOMMU_S_UNSUPP; +} + +static int virtio_iommu_unmap(VirtIOIOMMU *s, + struct virtio_iommu_req_unmap *req) +{ + uint32_t asid = le32_to_cpu(req->address_space); + uint64_t virt_addr = le64_to_cpu(req->virt_addr); + uint64_t size = le64_to_cpu(req->size); + uint32_t flags = le32_to_cpu(req->flags); + + trace_virtio_iommu_unmap(asid, virt_addr, size, flags); + + return VIRTIO_IOMMU_S_UNSUPP; +} + +#define get_payload_size(req) (\ +sizeof((req)) - sizeof(struct virtio_iommu_req_tail)) + static int virtio_iommu_handle_attach(VirtIOIOMMU *s, struct iovec *iov, unsigned int iov_cnt) { - return -ENOENT; + struct virtio_iommu_req_attach req; + size_t sz, payload_sz; + + payload_sz = get_payload_size(req); + + sz = iov_to_buf(iov, iov_cnt, 0, &req, payload_sz); + if (sz != payload_sz) { + return VIRTIO_IOMMU_S_INVAL; + } + return virtio_iommu_attach(s, &req); } static int virtio_iommu_handle_detach(VirtIOIOMMU *s, struct iovec *iov, unsigned int iov_cnt) { - return -ENOENT; + struct virtio_iommu_req_detach req; + size_t sz, payload_sz; + + payload_sz = get_payload_size(req); + + sz = iov_to_buf(iov, iov_cnt, 0, &req, payload_sz); + if (sz != payload_sz) { + return VIRTIO_IOMMU_S_INVAL; + } + return virtio_iommu_detach(s, &req); } static int virtio_iommu_handle_map(VirtIOIOMMU *s, struct iovec *iov, unsigned int iov_cnt) { - return -ENOENT; + struct virtio_iommu_req_map req; + size_t sz, payload_sz; + + payload_sz = get_payload_size(req); + + sz = iov_to_buf(iov, iov_cnt, 0, &req, payload_sz); + if (sz != payload_sz) { + return VIRTIO_IOMMU_S_INVAL; + } + return virtio_iommu_map(s, &req); } static int virtio_iommu_handle_unmap(VirtIOIOMMU *s, struct iovec *iov, unsigned int iov_cnt) { - return -ENOENT; + struct virtio_iommu_req_unmap req; + size_t sz, payload_sz; + + payload_sz = get_payload_size(req); + + sz = iov_to_buf(iov, iov_cnt, 0, &req, payload_sz); + if (sz != payload_sz) { + return VIRTIO_IOMMU_S_INVAL; + } + return virtio_iommu_unmap(s, &req); } static void virtio_iommu_handle_command(VirtIODevice *vdev, VirtQueue *vq) -- 2.5.5 From MAILER-DAEMON Tue Aug 01 05:35:04 2017 Received: from list by lists.gnu.org with archive (Exim 4.71) id 1dcTZw-0007lc-23 for mharc-qemu-arm@gnu.org; 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dmarc=none (p=none dis=none) header.from=redhat.com Authentication-Results: ext-mx02.extmail.prod.ext.phx2.redhat.com; spf=fail smtp.mailfrom=eric.auger@redhat.com Received: from localhost.localdomain.com (ovpn-116-181.ams2.redhat.com [10.36.116.181]) by smtp.corp.redhat.com (Postfix) with ESMTP id 6AB556047A; Tue, 1 Aug 2017 09:34:53 +0000 (UTC) From: Eric Auger To: eric.auger.pro@gmail.com, eric.auger@redhat.com, peter.maydell@linaro.org, alex.williamson@redhat.com, mst@redhat.com, qemu-arm@nongnu.org, qemu-devel@nongnu.org, jean-philippe.brucker@arm.com Cc: will.deacon@arm.com, kevin.tian@intel.com, marc.zyngier@arm.com, christoffer.dall@linaro.org, drjones@redhat.com, wei@redhat.com, tn@semihalf.com, bharat.bhushan@nxp.com, peterx@redhat.com Date: Tue, 1 Aug 2017 11:33:11 +0200 Message-Id: <1501579994-3320-6-git-send-email-eric.auger@redhat.com> In-Reply-To: <1501579994-3320-1-git-send-email-eric.auger@redhat.com> References: <1501579994-3320-1-git-send-email-eric.auger@redhat.com> X-Scanned-By: MIMEDefang 2.79 on 10.5.11.11 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.26]); Tue, 01 Aug 2017 09:34:57 +0000 (UTC) X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.132.183.28 Subject: [Qemu-arm] [RFC v3 5/8] virtio_iommu: Add the iommu regions X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 01 Aug 2017 09:35:03 -0000 This patch initializes the iommu memory regions so that PCIe end point transactions get translated. The translation function is not yet implemented at that stage. Signed-off-by: Eric Auger --- v2 -> v3: - use IOMMUMemoryRegion - iommu mr name built with BDF - rename smmu_get_sid into virtio_iommu_get_sid and use PCI_BUILD_BDF --- hw/virtio/trace-events | 1 + hw/virtio/virtio-iommu.c | 117 +++++++++++++++++++++++++++++++++++++++ include/hw/virtio/virtio-iommu.h | 2 + 3 files changed, 120 insertions(+) diff --git a/hw/virtio/trace-events b/hw/virtio/trace-events index fba1da6..341dbdf 100644 --- a/hw/virtio/trace-events +++ b/hw/virtio/trace-events @@ -32,3 +32,4 @@ virtio_iommu_attach(uint32_t as, uint32_t dev, uint32_t flags) "as=%d dev=%d fla virtio_iommu_detach(uint32_t dev, uint32_t flags) "dev=%d flags=%d" virtio_iommu_map(uint32_t as, uint64_t phys_addr, uint64_t virt_addr, uint64_t size, uint32_t flags) "as= %d phys_addr=0x%"PRIx64" virt_addr=0x%"PRIx64" size=0x%"PRIx64" flags=%d" virtio_iommu_unmap(uint32_t as, uint64_t virt_addr, uint64_t size, uint32_t reserved) "as= %d virt_addr=0x%"PRIx64" size=0x%"PRIx64" reserved=%d" +virtio_iommu_translate(const char *name, uint32_t rid, uint64_t iova, int flag) "mr=%s rid=%d addr=0x%"PRIx64" flag=%d" diff --git a/hw/virtio/virtio-iommu.c b/hw/virtio/virtio-iommu.c index 6f5b71c..e663d9e 100644 --- a/hw/virtio/virtio-iommu.c +++ b/hw/virtio/virtio-iommu.c @@ -23,6 +23,7 @@ #include "hw/virtio/virtio.h" #include "sysemu/kvm.h" #include "qapi-event.h" +#include "qemu/error-report.h" #include "trace.h" #include "standard-headers/linux/virtio_ids.h" @@ -35,6 +36,64 @@ /* Max size */ #define VIOMMU_DEFAULT_QUEUE_SIZE 256 +static inline uint16_t virtio_iommu_get_sid(IOMMUDevice *dev) +{ + return PCI_BUILD_BDF(pci_bus_num(dev->bus), dev->devfn); +} + +static AddressSpace *virtio_iommu_find_add_as(PCIBus *bus, void *opaque, + int devfn) +{ + VirtIOIOMMU *s = opaque; + uintptr_t key = (uintptr_t)bus; + IOMMUPciBus *sbus = g_hash_table_lookup(s->as_by_busptr, &key); + IOMMUDevice *sdev; + + if (!sbus) { + uintptr_t *new_key = g_malloc(sizeof(*new_key)); + + *new_key = (uintptr_t)bus; + sbus = g_malloc0(sizeof(IOMMUPciBus) + + sizeof(IOMMUDevice *) * IOMMU_PCI_DEVFN_MAX); + sbus->bus = bus; + g_hash_table_insert(s->as_by_busptr, new_key, sbus); + } + + sdev = sbus->pbdev[devfn]; + if (!sdev) { + char *name = g_strdup_printf("%s-%d-%d", + TYPE_VIRTIO_IOMMU_MEMORY_REGION, + pci_bus_num(bus), devfn); + sdev = sbus->pbdev[devfn] = g_malloc0(sizeof(IOMMUDevice)); + + sdev->viommu = s; + sdev->bus = bus; + sdev->devfn = devfn; + + memory_region_init_iommu(&sdev->iommu_mr, sizeof(sdev->iommu_mr), + TYPE_VIRTIO_IOMMU_MEMORY_REGION, + OBJECT(s), name, + UINT64_MAX); + address_space_init(&sdev->as, + MEMORY_REGION(&sdev->iommu_mr), TYPE_VIRTIO_IOMMU); + } + + return &sdev->as; + +} + +static void virtio_iommu_init_as(VirtIOIOMMU *s) +{ + PCIBus *pcibus = pci_find_primary_bus(); + + if (pcibus) { + pci_setup_iommu(pcibus, virtio_iommu_find_add_as, s); + } else { + error_report("No PCI bus, virtio-iommu is not registered"); + } +} + + static int virtio_iommu_attach(VirtIOIOMMU *s, struct virtio_iommu_req_attach *req) { @@ -208,6 +267,26 @@ static void virtio_iommu_handle_command(VirtIODevice *vdev, VirtQueue *vq) } } +static IOMMUTLBEntry virtio_iommu_translate(IOMMUMemoryRegion *mr, hwaddr addr, + IOMMUAccessFlags flag) +{ + IOMMUDevice *sdev = container_of(mr, IOMMUDevice, iommu_mr); + uint32_t sid; + + IOMMUTLBEntry entry = { + .target_as = &address_space_memory, + .iova = addr, + .translated_addr = addr, + .addr_mask = ~(hwaddr)0, + .perm = IOMMU_NONE, + }; + + sid = virtio_iommu_get_sid(sdev); + + trace_virtio_iommu_translate(mr->parent_obj.name, sid, addr, flag); + return entry; +} + static void virtio_iommu_get_config(VirtIODevice *vdev, uint8_t *config_data) { VirtIOIOMMU *dev = VIRTIO_IOMMU(vdev); @@ -254,6 +333,21 @@ static const VMStateDescription vmstate_virtio_iommu_device = { }, }; +/***************************** + * Hash Table + *****************************/ + +static inline gboolean as_uint64_equal(gconstpointer v1, gconstpointer v2) +{ + return *((const uint64_t *)v1) == *((const uint64_t *)v2); +} + +static inline guint as_uint64_hash(gconstpointer v) +{ + return (guint)*(const uint64_t *)v; +} + + static void virtio_iommu_device_realize(DeviceState *dev, Error **errp) { VirtIODevice *vdev = VIRTIO_DEVICE(dev); @@ -267,6 +361,13 @@ static void virtio_iommu_device_realize(DeviceState *dev, Error **errp) s->config.page_sizes = TARGET_PAGE_MASK; s->config.input_range.end = -1UL; + + memset(s->as_by_bus_num, 0, sizeof(s->as_by_bus_num)); + s->as_by_busptr = g_hash_table_new_full(as_uint64_hash, + as_uint64_equal, + g_free, g_free); + + virtio_iommu_init_as(s); } static void virtio_iommu_device_unrealize(DeviceState *dev, Error **errp) @@ -321,6 +422,14 @@ static void virtio_iommu_class_init(ObjectClass *klass, void *data) vdc->vmsd = &vmstate_virtio_iommu_device; } +static void virtio_iommu_memory_region_class_init(ObjectClass *klass, + void *data) +{ + IOMMUMemoryRegionClass *imrc = IOMMU_MEMORY_REGION_CLASS(klass); + + imrc->translate = virtio_iommu_translate; +} + static const TypeInfo virtio_iommu_info = { .name = TYPE_VIRTIO_IOMMU, .parent = TYPE_VIRTIO_DEVICE, @@ -329,9 +438,17 @@ static const TypeInfo virtio_iommu_info = { .class_init = virtio_iommu_class_init, }; +static const TypeInfo virtio_iommu_memory_region_info = { + .parent = TYPE_IOMMU_MEMORY_REGION, + .name = TYPE_VIRTIO_IOMMU_MEMORY_REGION, + .class_init = virtio_iommu_memory_region_class_init, +}; + + static void virtio_register_types(void) { type_register_static(&virtio_iommu_info); + type_register_static(&virtio_iommu_memory_region_info); } type_init(virtio_register_types) diff --git a/include/hw/virtio/virtio-iommu.h b/include/hw/virtio/virtio-iommu.h index 6716cdb..f9c988f 100644 --- a/include/hw/virtio/virtio-iommu.h +++ b/include/hw/virtio/virtio-iommu.h @@ -28,6 +28,8 @@ #define VIRTIO_IOMMU(obj) \ OBJECT_CHECK(VirtIOIOMMU, (obj), TYPE_VIRTIO_IOMMU) +#define TYPE_VIRTIO_IOMMU_MEMORY_REGION "virtio-iommu-memory-region" + #define IOMMU_PCI_BUS_MAX 256 #define IOMMU_PCI_DEVFN_MAX 256 -- 2.5.5 From MAILER-DAEMON Tue Aug 01 05:35:15 2017 Received: from list by lists.gnu.org with archive (Exim 4.71) id 1dcTa7-0007zz-9g for mharc-qemu-arm@gnu.org; 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dmarc=none (p=none dis=none) header.from=redhat.com Authentication-Results: ext-mx02.extmail.prod.ext.phx2.redhat.com; spf=fail smtp.mailfrom=eric.auger@redhat.com Received: from localhost.localdomain.com (ovpn-116-181.ams2.redhat.com [10.36.116.181]) by smtp.corp.redhat.com (Postfix) with ESMTP id 6F9966047A; Tue, 1 Aug 2017 09:34:57 +0000 (UTC) From: Eric Auger To: eric.auger.pro@gmail.com, eric.auger@redhat.com, peter.maydell@linaro.org, alex.williamson@redhat.com, mst@redhat.com, qemu-arm@nongnu.org, qemu-devel@nongnu.org, jean-philippe.brucker@arm.com Cc: will.deacon@arm.com, kevin.tian@intel.com, marc.zyngier@arm.com, christoffer.dall@linaro.org, drjones@redhat.com, wei@redhat.com, tn@semihalf.com, bharat.bhushan@nxp.com, peterx@redhat.com Date: Tue, 1 Aug 2017 11:33:12 +0200 Message-Id: <1501579994-3320-7-git-send-email-eric.auger@redhat.com> In-Reply-To: <1501579994-3320-1-git-send-email-eric.auger@redhat.com> References: <1501579994-3320-1-git-send-email-eric.auger@redhat.com> X-Scanned-By: MIMEDefang 2.79 on 10.5.11.11 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.26]); Tue, 01 Aug 2017 09:35:03 +0000 (UTC) X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.132.183.28 Subject: [Qemu-arm] [RFC v3 6/8] virtio-iommu: Implement the translation and commands X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 01 Aug 2017 09:35:13 -0000 This patch adds the actual implementation for the translation routine and the virtio-iommu commands. Signed-off-by: Eric Auger --- v2 -> v3: - init the mutex - return VIRTIO_IOMMU_S_INVAL is reserved field is not null on attach/detach commands - on attach, when the device is already attached to an address space, detach it first instead of returning an error - remove nr_devices and use g_tree_ref/unref to destroy the as->mappings on last device detach - map/unmap: return NOENT instead of INVAL error if as does not exist - remove flags argument from attach/detach trace functions v1 -> v2: - fix compilation issue reported by autobuild system --- hw/virtio/trace-events | 10 +- hw/virtio/virtio-iommu.c | 232 +++++++++++++++++++++++++++++++++++++++++++++-- 2 files changed, 232 insertions(+), 10 deletions(-) diff --git a/hw/virtio/trace-events b/hw/virtio/trace-events index 341dbdf..8db3d91 100644 --- a/hw/virtio/trace-events +++ b/hw/virtio/trace-events @@ -28,8 +28,14 @@ virtio_balloon_to_target(uint64_t target, uint32_t num_pages) "balloon target: % # hw/virtio/virtio-iommu.c # -virtio_iommu_attach(uint32_t as, uint32_t dev, uint32_t flags) "as=%d dev=%d flags=%d" -virtio_iommu_detach(uint32_t dev, uint32_t flags) "dev=%d flags=%d" +virtio_iommu_attach(uint32_t as, uint32_t dev) "as=%d dev=%d" +virtio_iommu_detach(uint32_t dev) "dev=%d" virtio_iommu_map(uint32_t as, uint64_t phys_addr, uint64_t virt_addr, uint64_t size, uint32_t flags) "as= %d phys_addr=0x%"PRIx64" virt_addr=0x%"PRIx64" size=0x%"PRIx64" flags=%d" virtio_iommu_unmap(uint32_t as, uint64_t virt_addr, uint64_t size, uint32_t reserved) "as= %d virt_addr=0x%"PRIx64" size=0x%"PRIx64" reserved=%d" virtio_iommu_translate(const char *name, uint32_t rid, uint64_t iova, int flag) "mr=%s rid=%d addr=0x%"PRIx64" flag=%d" +virtio_iommu_new_asid(uint32_t asid) "Allocate a new asid=%d" +virtio_iommu_new_devid(uint32_t devid) "Allocate a new devid=%d" +virtio_iommu_unmap_left_interval(uint64_t low, uint64_t high, uint64_t next_low, uint64_t next_high) "Unmap left [0x%"PRIx64",0x%"PRIx64"], new interval=[0x%"PRIx64",0x%"PRIx64"]" +virtio_iommu_unmap_right_interval(uint64_t low, uint64_t high, uint64_t next_low, uint64_t next_high) "Unmap right [0x%"PRIx64",0x%"PRIx64"], new interval=[0x%"PRIx64",0x%"PRIx64"]" +virtio_iommu_unmap_inc_interval(uint64_t low, uint64_t high) "Unmap inc [0x%"PRIx64",0x%"PRIx64"]" +virtio_iommu_translate_result(uint64_t virt_addr, uint64_t phys_addr, uint32_t sid) "0x%"PRIx64" -> 0x%"PRIx64 " for sid=%d" diff --git a/hw/virtio/virtio-iommu.c b/hw/virtio/virtio-iommu.c index e663d9e..9217587 100644 --- a/hw/virtio/virtio-iommu.c +++ b/hw/virtio/virtio-iommu.c @@ -32,10 +32,36 @@ #include "hw/virtio/virtio-bus.h" #include "hw/virtio/virtio-access.h" #include "hw/virtio/virtio-iommu.h" +#include "hw/pci/pci_bus.h" +#include "hw/pci/pci.h" /* Max size */ #define VIOMMU_DEFAULT_QUEUE_SIZE 256 +typedef struct viommu_as viommu_as; + +typedef struct viommu_mapping { + uint64_t virt_addr; + uint64_t phys_addr; + uint64_t size; + uint32_t flags; +} viommu_mapping; + +typedef struct viommu_interval { + uint64_t low; + uint64_t high; +} viommu_interval; + +typedef struct viommu_dev { + uint32_t id; + viommu_as *as; +} viommu_dev; + +struct viommu_as { + uint32_t id; + GTree *mappings; +}; + static inline uint16_t virtio_iommu_get_sid(IOMMUDevice *dev) { return PCI_BUILD_BDF(pci_bus_num(dev->bus), dev->devfn); @@ -93,6 +119,29 @@ static void virtio_iommu_init_as(VirtIOIOMMU *s) } } +static gint interval_cmp(gconstpointer a, gconstpointer b, gpointer user_data) +{ + viommu_interval *inta = (viommu_interval *)a; + viommu_interval *intb = (viommu_interval *)b; + + if (inta->high <= intb->low) { + return -1; + } else if (intb->high <= inta->low) { + return 1; + } else { + return 0; + } +} + +static void virtio_iommu_detach_dev(VirtIOIOMMU *s, viommu_dev *dev) +{ + viommu_as *as = dev->as; + + trace_virtio_iommu_detach(dev->id); + + g_tree_remove(s->devices, GUINT_TO_POINTER(dev->id)); + g_tree_unref(as->mappings); +} static int virtio_iommu_attach(VirtIOIOMMU *s, struct virtio_iommu_req_attach *req) @@ -100,10 +149,42 @@ static int virtio_iommu_attach(VirtIOIOMMU *s, uint32_t asid = le32_to_cpu(req->address_space); uint32_t devid = le32_to_cpu(req->device); uint32_t reserved = le32_to_cpu(req->reserved); + viommu_as *as; + viommu_dev *dev; + + trace_virtio_iommu_attach(asid, devid); + + if (reserved) { + return VIRTIO_IOMMU_S_INVAL; + } + + dev = g_tree_lookup(s->devices, GUINT_TO_POINTER(devid)); + if (dev) { + /* + * the device is already attached to an address space, + * detach it first + */ + virtio_iommu_detach_dev(s, dev); + } - trace_virtio_iommu_attach(asid, devid, reserved); + as = g_tree_lookup(s->address_spaces, GUINT_TO_POINTER(asid)); + if (!as) { + as = g_malloc0(sizeof(*as)); + as->id = asid; + as->mappings = g_tree_new_full((GCompareDataFunc)interval_cmp, + NULL, NULL, (GDestroyNotify)g_free); + g_tree_insert(s->address_spaces, GUINT_TO_POINTER(asid), as); + trace_virtio_iommu_new_asid(asid); + } - return VIRTIO_IOMMU_S_UNSUPP; + dev = g_malloc0(sizeof(*dev)); + dev->as = as; + dev->id = devid; + trace_virtio_iommu_new_devid(devid); + g_tree_insert(s->devices, GUINT_TO_POINTER(devid), dev); + g_tree_ref(as->mappings); + + return VIRTIO_IOMMU_S_OK; } static int virtio_iommu_detach(VirtIOIOMMU *s, @@ -111,10 +192,20 @@ static int virtio_iommu_detach(VirtIOIOMMU *s, { uint32_t devid = le32_to_cpu(req->device); uint32_t reserved = le32_to_cpu(req->reserved); + viommu_dev *dev; + + if (reserved) { + return VIRTIO_IOMMU_S_INVAL; + } + + dev = g_tree_lookup(s->devices, GUINT_TO_POINTER(devid)); + if (!dev) { + return VIRTIO_IOMMU_S_INVAL; + } - trace_virtio_iommu_detach(devid, reserved); + virtio_iommu_detach_dev(s, dev); - return VIRTIO_IOMMU_S_UNSUPP; + return VIRTIO_IOMMU_S_OK; } static int virtio_iommu_map(VirtIOIOMMU *s, @@ -125,10 +216,37 @@ static int virtio_iommu_map(VirtIOIOMMU *s, uint64_t virt_addr = le64_to_cpu(req->virt_addr); uint64_t size = le64_to_cpu(req->size); uint32_t flags = le32_to_cpu(req->flags); + viommu_as *as; + viommu_interval *interval; + viommu_mapping *mapping; + + interval = g_malloc0(sizeof(*interval)); + + interval->low = virt_addr; + interval->high = virt_addr + size - 1; + + as = g_tree_lookup(s->address_spaces, GUINT_TO_POINTER(asid)); + if (!as) { + return VIRTIO_IOMMU_S_NOENT; + } + + mapping = g_tree_lookup(as->mappings, (gpointer)interval); + if (mapping) { + g_free(interval); + return VIRTIO_IOMMU_S_INVAL; + } trace_virtio_iommu_map(asid, phys_addr, virt_addr, size, flags); - return VIRTIO_IOMMU_S_UNSUPP; + mapping = g_malloc0(sizeof(*mapping)); + mapping->virt_addr = virt_addr; + mapping->phys_addr = phys_addr; + mapping->size = size; + mapping->flags = flags; + + g_tree_insert(as->mappings, interval, mapping); + + return VIRTIO_IOMMU_S_OK; } static int virtio_iommu_unmap(VirtIOIOMMU *s, @@ -138,10 +256,64 @@ static int virtio_iommu_unmap(VirtIOIOMMU *s, uint64_t virt_addr = le64_to_cpu(req->virt_addr); uint64_t size = le64_to_cpu(req->size); uint32_t flags = le32_to_cpu(req->flags); + viommu_mapping *mapping; + viommu_interval interval; + viommu_as *as; trace_virtio_iommu_unmap(asid, virt_addr, size, flags); - return VIRTIO_IOMMU_S_UNSUPP; + as = g_tree_lookup(s->address_spaces, GUINT_TO_POINTER(asid)); + if (!as) { + error_report("%s: no as", __func__); + return VIRTIO_IOMMU_S_NOENT; + } + interval.low = virt_addr; + interval.high = virt_addr + size - 1; + + mapping = g_tree_lookup(as->mappings, (gpointer)&interval); + + while (mapping) { + viommu_interval current; + uint64_t low = mapping->virt_addr; + uint64_t high = mapping->virt_addr + mapping->size - 1; + + current.low = low; + current.high = high; + + if (low == interval.low && size >= mapping->size) { + g_tree_remove(as->mappings, (gpointer)¤t); + interval.low = high + 1; + trace_virtio_iommu_unmap_left_interval(current.low, current.high, + interval.low, interval.high); + } else if (high == interval.high && size >= mapping->size) { + trace_virtio_iommu_unmap_right_interval(current.low, current.high, + interval.low, interval.high); + g_tree_remove(as->mappings, (gpointer)¤t); + interval.high = low - 1; + } else if (low > interval.low && high < interval.high) { + trace_virtio_iommu_unmap_inc_interval(current.low, current.high); + g_tree_remove(as->mappings, (gpointer)¤t); + } else { + break; + } + if (interval.low >= interval.high) { + return VIRTIO_IOMMU_S_OK; + } else { + mapping = g_tree_lookup(as->mappings, (gpointer)&interval); + } + } + + if (mapping) { + error_report("****** %s: Unmap 0x%"PRIx64" size=0x%"PRIx64 + " from 0x%"PRIx64" size=0x%"PRIx64" is not supported", + __func__, interval.low, size, + mapping->virt_addr, mapping->size); + } else { + error_report("****** %s: no mapping for [0x%"PRIx64",0x%"PRIx64"]", + __func__, interval.low, interval.high); + } + + return VIRTIO_IOMMU_S_INVAL; } #define get_payload_size(req) (\ @@ -271,19 +443,46 @@ static IOMMUTLBEntry virtio_iommu_translate(IOMMUMemoryRegion *mr, hwaddr addr, IOMMUAccessFlags flag) { IOMMUDevice *sdev = container_of(mr, IOMMUDevice, iommu_mr); + VirtIOIOMMU *s = sdev->viommu; uint32_t sid; + viommu_dev *dev; + viommu_mapping *mapping; + viommu_interval interval; + + interval.low = addr; + interval.high = addr + 1; IOMMUTLBEntry entry = { .target_as = &address_space_memory, .iova = addr, .translated_addr = addr, - .addr_mask = ~(hwaddr)0, - .perm = IOMMU_NONE, + .addr_mask = (1 << 12) - 1, /* TODO */ + .perm = 3, }; sid = virtio_iommu_get_sid(sdev); trace_virtio_iommu_translate(mr->parent_obj.name, sid, addr, flag); + qemu_mutex_lock(&s->mutex); + + dev = g_tree_lookup(s->devices, GUINT_TO_POINTER(sid)); + if (!dev) { + /* device cannot be attached to another as */ + printf("%s sid=%d is not known!!\n", __func__, sid); + goto unlock; + } + + mapping = g_tree_lookup(dev->as->mappings, (gpointer)&interval); + if (!mapping) { + printf("%s no mapping for 0x%"PRIx64" for sid=%d\n", __func__, + addr, sid); + goto unlock; + } + entry.translated_addr = addr - mapping->virt_addr + mapping->phys_addr, + trace_virtio_iommu_translate_result(addr, entry.translated_addr, sid); + +unlock: + qemu_mutex_unlock(&s->mutex); return entry; } @@ -347,6 +546,12 @@ static inline guint as_uint64_hash(gconstpointer v) return (guint)*(const uint64_t *)v; } +static gint int_cmp(gconstpointer a, gconstpointer b, gpointer user_data) +{ + uint ua = GPOINTER_TO_UINT(a); + uint ub = GPOINTER_TO_UINT(b); + return (ua > ub) - (ua < ub); +} static void virtio_iommu_device_realize(DeviceState *dev, Error **errp) { @@ -362,17 +567,28 @@ static void virtio_iommu_device_realize(DeviceState *dev, Error **errp) s->config.page_sizes = TARGET_PAGE_MASK; s->config.input_range.end = -1UL; + qemu_mutex_init(&s->mutex); + memset(s->as_by_bus_num, 0, sizeof(s->as_by_bus_num)); s->as_by_busptr = g_hash_table_new_full(as_uint64_hash, as_uint64_equal, g_free, g_free); + s->address_spaces = g_tree_new_full((GCompareDataFunc)int_cmp, + NULL, NULL, (GDestroyNotify)g_free); + s->devices = g_tree_new_full((GCompareDataFunc)int_cmp, + NULL, NULL, (GDestroyNotify)g_free); + virtio_iommu_init_as(s); } static void virtio_iommu_device_unrealize(DeviceState *dev, Error **errp) { VirtIODevice *vdev = VIRTIO_DEVICE(dev); + VirtIOIOMMU *s = VIRTIO_IOMMU(dev); + + g_tree_destroy(s->address_spaces); + g_tree_destroy(s->devices); virtio_cleanup(vdev); } -- 2.5.5 From MAILER-DAEMON Tue Aug 01 05:35:24 2017 Received: from list by lists.gnu.org with archive (Exim 4.71) id 1dcTaG-00089v-BT for mharc-qemu-arm@gnu.org; Tue, 01 Aug 2017 05:35:24 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:38478) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dcTaD-00086B-6o for qemu-arm@nongnu.org; Tue, 01 Aug 2017 05:35:22 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dcTaC-0002XT-AE for qemu-arm@nongnu.org; Tue, 01 Aug 2017 05:35:21 -0400 Received: from mx1.redhat.com ([209.132.183.28]:52312) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1dcTaC-0002Vz-3o; Tue, 01 Aug 2017 05:35:20 -0400 Received: from smtp.corp.redhat.com (int-mx01.intmail.prod.int.phx2.redhat.com [10.5.11.11]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id 72CFC2861C8; Tue, 1 Aug 2017 09:35:18 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mx1.redhat.com 72CFC2861C8 Authentication-Results: ext-mx10.extmail.prod.ext.phx2.redhat.com; dmarc=none (p=none dis=none) header.from=redhat.com Authentication-Results: ext-mx10.extmail.prod.ext.phx2.redhat.com; spf=fail smtp.mailfrom=eric.auger@redhat.com Received: from localhost.localdomain.com (ovpn-116-181.ams2.redhat.com [10.36.116.181]) by smtp.corp.redhat.com (Postfix) with ESMTP id 3F6C36017B; Tue, 1 Aug 2017 09:35:03 +0000 (UTC) From: Eric Auger To: eric.auger.pro@gmail.com, eric.auger@redhat.com, peter.maydell@linaro.org, alex.williamson@redhat.com, mst@redhat.com, qemu-arm@nongnu.org, qemu-devel@nongnu.org, jean-philippe.brucker@arm.com Cc: will.deacon@arm.com, kevin.tian@intel.com, marc.zyngier@arm.com, christoffer.dall@linaro.org, drjones@redhat.com, wei@redhat.com, tn@semihalf.com, bharat.bhushan@nxp.com, peterx@redhat.com Date: Tue, 1 Aug 2017 11:33:13 +0200 Message-Id: <1501579994-3320-8-git-send-email-eric.auger@redhat.com> In-Reply-To: <1501579994-3320-1-git-send-email-eric.auger@redhat.com> References: <1501579994-3320-1-git-send-email-eric.auger@redhat.com> X-Scanned-By: MIMEDefang 2.79 on 10.5.11.11 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.39]); Tue, 01 Aug 2017 09:35:19 +0000 (UTC) X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.132.183.28 Subject: [Qemu-arm] [RFC v3 7/8] hw/arm/virt: Add 2.10 machine type X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 01 Aug 2017 09:35:22 -0000 The new machine type allows virtio-iommu instantiation. Signed-off-by: Eric Auger --- a Veuillez saisir le message de validation pour vos modifications. Les lignes --- hw/arm/virt.c | 24 ++++++++++++++++++++++-- include/hw/arm/virt.h | 1 + 2 files changed, 23 insertions(+), 2 deletions(-) diff --git a/hw/arm/virt.c b/hw/arm/virt.c index 31739d7..93c4ab2 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -1639,7 +1639,7 @@ static void machvirt_machine_init(void) } type_init(machvirt_machine_init); -static void virt_2_9_instance_init(Object *obj) +static void virt_2_10_instance_init(Object *obj) { VirtMachineState *vms = VIRT_MACHINE(obj); VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms); @@ -1699,10 +1699,30 @@ static void virt_2_9_instance_init(Object *obj) vms->irqmap = a15irqmap; } +static void virt_machine_2_10_options(MachineClass *mc) +{ +} +DEFINE_VIRT_MACHINE_AS_LATEST(2, 10) + +#define VIRT_COMPAT_2_9 \ + HW_COMPAT_2_9 + +static void virt_2_9_instance_init(Object *obj) +{ + virt_2_10_instance_init(obj); +} + static void virt_machine_2_9_options(MachineClass *mc) { + VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc)); + + virt_machine_2_10_options(mc); + SET_MACHINE_COMPAT(mc, VIRT_COMPAT_2_9); + + vmc->no_iommu = true; } -DEFINE_VIRT_MACHINE_AS_LATEST(2, 9) +DEFINE_VIRT_MACHINE(2, 9) + #define VIRT_COMPAT_2_8 \ HW_COMPAT_2_8 diff --git a/include/hw/arm/virt.h b/include/hw/arm/virt.h index 33b0ff3..ff27551 100644 --- a/include/hw/arm/virt.h +++ b/include/hw/arm/virt.h @@ -84,6 +84,7 @@ typedef struct { bool disallow_affinity_adjustment; bool no_its; bool no_pmu; + bool no_iommu; bool claim_edge_triggered_timers; } VirtMachineClass; -- 2.5.5 From MAILER-DAEMON Tue Aug 01 05:35:28 2017 Received: from list by lists.gnu.org with archive (Exim 4.71) id 1dcTaK-0008EY-LS for mharc-qemu-arm@gnu.org; Tue, 01 Aug 2017 05:35:28 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:38533) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dcTaH-0008BA-I2 for qemu-arm@nongnu.org; Tue, 01 Aug 2017 05:35:26 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dcTaF-0002cw-U3 for qemu-arm@nongnu.org; Tue, 01 Aug 2017 05:35:25 -0400 Received: from mx1.redhat.com ([209.132.183.28]:49012) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1dcTaF-0002bV-Lg; Tue, 01 Aug 2017 05:35:23 -0400 Received: from smtp.corp.redhat.com (int-mx01.intmail.prod.int.phx2.redhat.com [10.5.11.11]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id 908B9169366; Tue, 1 Aug 2017 09:35:22 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mx1.redhat.com 908B9169366 Authentication-Results: ext-mx03.extmail.prod.ext.phx2.redhat.com; dmarc=none (p=none dis=none) header.from=redhat.com Authentication-Results: ext-mx03.extmail.prod.ext.phx2.redhat.com; spf=fail smtp.mailfrom=eric.auger@redhat.com Received: from localhost.localdomain.com (ovpn-116-181.ams2.redhat.com [10.36.116.181]) by smtp.corp.redhat.com (Postfix) with ESMTP id C896D60176; Tue, 1 Aug 2017 09:35:18 +0000 (UTC) From: Eric Auger To: eric.auger.pro@gmail.com, eric.auger@redhat.com, peter.maydell@linaro.org, alex.williamson@redhat.com, mst@redhat.com, qemu-arm@nongnu.org, qemu-devel@nongnu.org, jean-philippe.brucker@arm.com Cc: will.deacon@arm.com, kevin.tian@intel.com, marc.zyngier@arm.com, christoffer.dall@linaro.org, drjones@redhat.com, wei@redhat.com, tn@semihalf.com, bharat.bhushan@nxp.com, peterx@redhat.com Date: Tue, 1 Aug 2017 11:33:14 +0200 Message-Id: <1501579994-3320-9-git-send-email-eric.auger@redhat.com> In-Reply-To: <1501579994-3320-1-git-send-email-eric.auger@redhat.com> References: <1501579994-3320-1-git-send-email-eric.auger@redhat.com> X-Scanned-By: MIMEDefang 2.79 on 10.5.11.11 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.27]); Tue, 01 Aug 2017 09:35:22 +0000 (UTC) X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.132.183.28 Subject: [Qemu-arm] [RFC v3 8/8] hw/arm/virt: Add virtio-iommu the virt board X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 01 Aug 2017 09:35:27 -0000 The specific virtio-mmio node is inconditionally added on machine init while the binding between this latter and the PCIe host bridge is done on machine init done notifier, only if -device virtio-iommu-device was added to the qemu command line. Signed-off-by: Eric Auger --- --- hw/arm/virt.c | 92 +++++++++++++++++++++++++++++++++++++++++++++++---- include/hw/arm/virt.h | 4 +++ 2 files changed, 89 insertions(+), 7 deletions(-) diff --git a/hw/arm/virt.c b/hw/arm/virt.c index 93c4ab2..9509399 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -52,6 +52,7 @@ #include "hw/arm/fdt.h" #include "hw/intc/arm_gic.h" #include "hw/intc/arm_gicv3_common.h" +#include "hw/virtio/virtio-iommu.h" #include "kvm_arm.h" #include "hw/smbios/smbios.h" #include "qapi/visitor.h" @@ -139,6 +140,7 @@ static const MemMapEntry a15memmap[] = { [VIRT_FW_CFG] = { 0x09020000, 0x00000018 }, [VIRT_GPIO] = { 0x09030000, 0x00001000 }, [VIRT_SECURE_UART] = { 0x09040000, 0x00001000 }, + [VIRT_SMMU] = { 0x09050000, 0x00000200 }, [VIRT_MMIO] = { 0x0a000000, 0x00000200 }, /* ...repeating for a total of NUM_VIRTIO_TRANSPORTS, each of that size */ [VIRT_PLATFORM_BUS] = { 0x0c000000, 0x02000000 }, @@ -159,6 +161,7 @@ static const int a15irqmap[] = { [VIRT_SECURE_UART] = 8, [VIRT_MMIO] = 16, /* ...to 16 + NUM_VIRTIO_TRANSPORTS - 1 */ [VIRT_GIC_V2M] = 48, /* ...to 48 + NUM_GICV2M_SPIS - 1 */ + [VIRT_SMMU] = 74, [VIRT_PLATFORM_BUS] = 112, /* ...to 112 + PLATFORM_BUS_NUM_IRQS -1 */ }; @@ -991,7 +994,81 @@ static void create_pcie_irq_map(const VirtMachineState *vms, 0x7 /* PCI irq */); } -static void create_pcie(const VirtMachineState *vms, qemu_irq *pic) +static int bind_virtio_iommu_device(Object *obj, void *opaque) +{ + VirtMachineState *vms = (VirtMachineState *)opaque; + struct arm_boot_info *info = &vms->bootinfo; + int dtb_size; + void *fdt = info->get_dtb(info, &dtb_size); + Object *dev; + + dev = object_dynamic_cast(obj, TYPE_VIRTIO_IOMMU); + + if (!dev) { + /* Container, traverse it for children */ + return object_child_foreach(obj, bind_virtio_iommu_device, opaque); + } + + qemu_fdt_setprop_cells(fdt, vms->pcie_host_nodename, "iommu-map", + 0x0, vms->smmu_phandle, 0x0, 0x10000); + + return true; +} + +static +void virtio_iommu_notifier(Notifier *notifier, void *data) +{ + VirtMachineState *vms = container_of(notifier, VirtMachineState, + virtio_iommu_done); + VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms); + Object *container; + + + if (vmc->no_iommu) { + return; + } + + container = container_get(qdev_get_machine(), "/peripheral"); + bind_virtio_iommu_device(container, vms); + container = container_get(qdev_get_machine(), "/peripheral-anon"); + bind_virtio_iommu_device(container, vms); +} + +static void create_virtio_iommu(VirtMachineState *vms, qemu_irq *pic) +{ + char *smmu; + const char compat[] = "virtio,mmio"; + int irq = vms->irqmap[VIRT_SMMU]; + hwaddr base = vms->memmap[VIRT_SMMU].base; + hwaddr size = vms->memmap[VIRT_SMMU].size; + VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms); + + if (vmc->no_iommu) { + return; + } + + vms->smmu_phandle = qemu_fdt_alloc_phandle(vms->fdt); + + sysbus_create_simple("virtio-mmio", base, pic[irq]); + + smmu = g_strdup_printf("/virtio_mmio@%" PRIx64, base); + qemu_fdt_add_subnode(vms->fdt, smmu); + qemu_fdt_setprop(vms->fdt, smmu, "compatible", compat, sizeof(compat)); + qemu_fdt_setprop_sized_cells(vms->fdt, smmu, "reg", 2, base, 2, size); + + qemu_fdt_setprop_cells(vms->fdt, smmu, "interrupts", + GIC_FDT_IRQ_TYPE_SPI, irq, GIC_FDT_IRQ_FLAGS_EDGE_LO_HI); + + qemu_fdt_setprop(vms->fdt, smmu, "dma-coherent", NULL, 0); + qemu_fdt_setprop_cell(vms->fdt, smmu, "#iommu-cells", 1); + qemu_fdt_setprop_cell(vms->fdt, smmu, "phandle", vms->smmu_phandle); + g_free(smmu); + + vms->virtio_iommu_done.notify = virtio_iommu_notifier; + qemu_add_machine_init_done_notifier(&vms->virtio_iommu_done); +} + +static void create_pcie(VirtMachineState *vms, qemu_irq *pic) { hwaddr base_mmio = vms->memmap[VIRT_PCIE_MMIO].base; hwaddr size_mmio = vms->memmap[VIRT_PCIE_MMIO].size; @@ -1064,7 +1141,8 @@ static void create_pcie(const VirtMachineState *vms, qemu_irq *pic) } } - nodename = g_strdup_printf("/pcie@%" PRIx64, base); + vms->pcie_host_nodename = g_strdup_printf("/pcie@%" PRIx64, base); + nodename = vms->pcie_host_nodename; qemu_fdt_add_subnode(vms->fdt, nodename); qemu_fdt_setprop_string(vms->fdt, nodename, "compatible", "pci-host-ecam-generic"); @@ -1103,7 +1181,6 @@ static void create_pcie(const VirtMachineState *vms, qemu_irq *pic) qemu_fdt_setprop_cell(vms->fdt, nodename, "#interrupt-cells", 1); create_pcie_irq_map(vms, vms->gic_phandle, irq, nodename); - g_free(nodename); } static void create_platform_bus(VirtMachineState *vms, qemu_irq *pic) @@ -1448,16 +1525,16 @@ static void machvirt_init(MachineState *machine) create_rtc(vms, pic); - create_pcie(vms, pic); - - create_gpio(vms, pic); - /* Create mmio transports, so the user can create virtio backends * (which will be automatically plugged in to the transports). If * no backend is created the transport will just sit harmlessly idle. */ create_virtio_devices(vms, pic); + create_pcie(vms, pic); + + create_gpio(vms, pic); + vms->fw_cfg = create_fw_cfg(vms, &address_space_memory); rom_set_fw(vms->fw_cfg); @@ -1482,6 +1559,7 @@ static void machvirt_init(MachineState *machine) * Notifiers are executed in registration reverse order. */ create_platform_bus(vms, pic); + create_virtio_iommu(vms, pic); } static bool virt_get_secure(Object *obj, Error **errp) diff --git a/include/hw/arm/virt.h b/include/hw/arm/virt.h index ff27551..070cb39 100644 --- a/include/hw/arm/virt.h +++ b/include/hw/arm/virt.h @@ -59,6 +59,7 @@ enum { VIRT_GIC_V2M, VIRT_GIC_ITS, VIRT_GIC_REDIST, + VIRT_SMMU, VIRT_UART, VIRT_MMIO, VIRT_RTC, @@ -91,6 +92,7 @@ typedef struct { typedef struct { MachineState parent; Notifier machine_done; + Notifier virtio_iommu_done; FWCfgState *fw_cfg; bool secure; bool highmem; @@ -106,6 +108,8 @@ typedef struct { uint32_t clock_phandle; uint32_t gic_phandle; uint32_t msi_phandle; + uint32_t smmu_phandle; + char *pcie_host_nodename; int psci_conduit; } VirtMachineState; -- 2.5.5 From MAILER-DAEMON Tue Aug 01 09:07:38 2017 Received: from list by lists.gnu.org with archive (Exim 4.71) id 1dcWte-0006Uw-Dx for mharc-qemu-arm@gnu.org; Tue, 01 Aug 2017 09:07:38 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:44894) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dcWtb-0006UQ-6F for qemu-arm@nongnu.org; Tue, 01 Aug 2017 09:07:37 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dcWtY-00019J-9Y for qemu-arm@nongnu.org; Tue, 01 Aug 2017 09:07:35 -0400 Received: from mx1.redhat.com ([209.132.183.28]:40560) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1dcWtY-00018q-0V; Tue, 01 Aug 2017 09:07:32 -0400 Received: from smtp.corp.redhat.com (int-mx03.intmail.prod.int.phx2.redhat.com [10.5.11.13]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id B9C6DB6F5D; Tue, 1 Aug 2017 13:07:30 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mx1.redhat.com B9C6DB6F5D Authentication-Results: ext-mx01.extmail.prod.ext.phx2.redhat.com; dmarc=none (p=none dis=none) header.from=redhat.com Authentication-Results: ext-mx01.extmail.prod.ext.phx2.redhat.com; spf=fail smtp.mailfrom=eric.auger@redhat.com Received: from localhost.localdomain (ovpn-116-181.ams2.redhat.com [10.36.116.181]) by smtp.corp.redhat.com (Postfix) with ESMTPS id 5D43317DFF; Tue, 1 Aug 2017 13:07:17 +0000 (UTC) To: Tomasz Nowicki , eric.auger.pro@gmail.com, peter.maydell@linaro.org, qemu-arm@nongnu.org, qemu-devel@nongnu.org, alex.williamson@redhat.com, prem.mallappa@gmail.com References: <1499633493-19865-1-git-send-email-eric.auger@redhat.com> Cc: drjones@redhat.com, christoffer.dall@linaro.org, Radha.Chintakuntla@cavium.com, Sunil.Goutham@cavium.com, mohun106@gmail.com, tcain@qti.qualcomm.com, bharat.bhushan@nxp.com, mst@redhat.com, will.deacon@arm.com, jean-philippe.brucker@arm.com, robin.murphy@arm.com, peterx@redhat.com, edgar.iglesias@gmail.com, "Nair, Jayachandran" From: Auger Eric Message-ID: <50d1685e-bfa6-02ac-2650-37637745431a@redhat.com> Date: Tue, 1 Aug 2017 15:07:15 +0200 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:45.0) Gecko/20100101 Thunderbird/45.4.0 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: 7bit X-Scanned-By: MIMEDefang 2.79 on 10.5.11.13 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.25]); Tue, 01 Aug 2017 13:07:31 +0000 (UTC) X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.132.183.28 Subject: Re: [Qemu-arm] [RFC v5 0/8] ARM SMMUv3 Emulation Support X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 01 Aug 2017 13:07:37 -0000 Hi Tomasz, On 01/08/2017 13:01, Tomasz Nowicki wrote: > Hi Eric, > > Just letting you know that I am facing another issue with the following > setup: > 1. host (4.12 kernel & 64K page) and VM (4.12 kernel & 64K page) > 2. QEMU + -netdev type=tap,ifname=tap,id=net0 -device > virtio-net-pci,netdev=net0,iommu_platform,disable-modern=off,disable-legacy=on > > 2. On VM, I allocate some huge pages and run DPDK testpmd app: > # echo 4 > /sys/kernel/mm/hugepages/hugepages-524288kB/nr_hugepages > # ./dpdk/usertools/dpdk-devbind.py -b vfio-pci 0000:00:02.0 > # ./dpdk/build/app/testpmd -l 0-13 -n 4 -w 0000:00:02.0 -- > --disable-hw-vlan-filter --disable-rss -i > EAL: Detected 14 lcore(s) > EAL: Probing VFIO support... > EAL: VFIO support initialized > EAL: PCI device 0000:00:02.0 on NUMA socket -1 > EAL: probe driver: 1af4:1041 net_virtio > EAL: using IOMMU type 1 (Type 1) > EAL: iommu_map_dma vaddr ffff20000000 size 80000000 iova 120000000 > EAL: Can't write to PCI bar (0) : offset (12) > EAL: Can't read from PCI bar (0) : offset (12) > EAL: Can't read from PCI bar (0) : offset (12) > EAL: Can't write to PCI bar (0) : offset (12) > EAL: Can't read from PCI bar (0) : offset (12) > EAL: Can't write to PCI bar (0) : offset (12) > EAL: Can't read from PCI bar (0) : offset (0) > EAL: Can't write to PCI bar (0) : offset (4) > EAL: Can't write to PCI bar (0) : offset (14) > EAL: Can't write to PCI bar (0) : offset (e) > EAL: Can't read from PCI bar (0) : offset (c) > EAL: Requested device 0000:00:02.0 cannot be used > EAL: No probed ethernet devices > Interactive-mode selected > USER1: create a new mbuf pool : n=251456, size=2176, > socket=0 > > When VM uses *4K pages* the same setup works fine. I will work on this > but please let me know in case you already know what is going on. No I did not face that one. I was able to launch testpmd without such early message. However I assigned an igbvf device to the guest and then to DPDK. I've never tested your config. However as stated in my cover letter at the moment DPDK is not working for me because of storms of tlbi-on-maps. I intend to work on this as soon as get some bandwidth, sorry. Thanks Eric > > Thanks, > Tomasz > > > On 09.07.2017 22:51, Eric Auger wrote: >> This series implements the emulation code for ARM SMMUv3. >> This is the continuation of Prem's work [1]. >> >> This v5 mainly brings VFIO integration in DT mode. On guest kernel >> side, this requires a quirk [1] to force TLB invalidation on map. >> >> The following changes also are noticeable: >> - fix SMMU_CMDQ_CONS offset >> - adds dma-coherent dt property which fixes the unhandled command >> opcode bug. >> - implements block PTE >> >> The smmu is instantiated when passing the smmu option to machvirt: >> "-M virt-2.10,smmu" >> >> As I haven't split the code yet so that it can be easily reviewable >> I don't expect deep reviews at this stage. Also the implementation may >> be largely sub-optimal. >> >> Tested Use Cases: >> - booted a guest in dt and acpi mode with an iommu_platform >> virtio-net-pci device (using dma ops). Tested with the following >> guest combinations: 4K page - 39 bit VA, 4K - 48b, 64K - 39b, >> 64K - 48b. >> - booted a guest (featuring [1]) with PCIe passthrough'ed PCIe devices: >> - AMD Overdrive and igbvf passthrough (using gsi direct mapping) >> - Cavium ThunderX and ixgbevf passthrough (using KVM MSI routing) >> >> Unfortunately I have not been able to run DPDK testpmd yet on guest side. >> The problem I see is the user space driver dma-maps a huge area >> and this causes plenty of CMDQ_OP_TLBI_NH_VA commands to be sent >> (tlbi-on-map) which are sent for each page whereas the dma-map covers a >> huge page. I will work on this issue for next version. >> >> Known limitations: >> - no VMSAv8-32 suport >> - no nested stage support (S1 + S2) >> - no support for HYP mappings >> - register fine emulation, commands, interrupts and errors were >> not accurately tested. Handling is sufficient to run use cases >> described hereafter though. >> >> Best Regards >> >> Eric >> >> This series can be found at: >> v5: https://github.com/eauger/qemu/tree/v2.9-SMMU-v5 >> v4: https://github.com/eauger/qemu/tree/v2.9-SMMU-v4 >> >> References: >> [1] [RFC 0/2] arm-smmu-v3 tlbi-on-map option >> [2] Prem's last iteration: >> - https://lists.gnu.org/archive/html/qemu-devel/2016-08/msg03531.html >> >> History: >> v4 -> v5: >> - initial_level now part of SMMUTransCfg >> - smmu_page_walk_64 takes into account the max input size >> - implement sys->iommu_ops.replay and sys->iommu_ops.notify_flag_changed >> - smmuv3_translate: bug fix: don't walk on bypass >> - smmu_update_qreg: fix PROD index update >> - I did not yet address Peter's comments as the code is not mature enough >> to be split into sub patches. >> >> v3 -> v4 [Eric]: >> - page table walk rewritten to allow scan of the page table within a >> range of IOVA. This prepares for VFIO integration and replay. >> - configuration parsing partially reworked. >> - do not advertise unsupported/untested features: S2, S1 + S2, HYP, >> PRI, ATS, .. >> - added ACPI table generation >> - migrated to dynamic traces >> - mingw compilation fix >> >> v2 -> v3 [Eric]: >> - rebased on 2.9 >> - mostly code and patch reorganization to ease the review process >> - optional patches removed. They may be handled separately. I am >> currently >> working on ACPI enablement. >> - optional instantiation of the smmu in mach-virt >> - removed [2/9] (fdt functions) since not mandated >> - start splitting main patch into base and derived object >> - no new function feature added >> >> v1 -> v2 [Prem]: >> - Adopted review comments from Eric Auger >> - Make SMMU_DPRINTF to internally call qemu_log >> (since translation requests are too many, we need control >> on the type of log we want) >> - SMMUTransCfg modified to suite simplicity >> - Change RegInfo to uint64 register array >> - Code cleanup >> - Test cleanups >> - Reshuffled patches >> >> v0 -> v1 [Prem]: >> - As per SMMUv3 spec 16.0 (only is_ste_consistant() is noticeable) >> - Reworked register access/update logic >> - Factored out translation code for >> - single point bug fix >> - sharing/removal in future >> - (optional) Unit tests added, with PCI test device >> - S1 with 4k/64k, S1+S2 with 4k/64k >> - (S1 or S2) only can be verified by Linux 4.7 driver >> - (optional) Priliminary ACPI support >> >> v0 [Prem]: >> - Implements SMMUv3 spec 11.0 >> - Supported for PCIe devices, >> - Command Queue and Event Queue supported >> - LPAE only, S1 is supported and Tested, S2 not tested >> - BE mode Translation not supported >> - IRQ support (legacy, no MSI) >> - Tested with DPDK and e1000 >> >> >> Eric Auger (5): >> hw/arm/smmu-common: smmu base class >> hw/arm/virt: Add 2.10 machine type >> hw/arm/virt: Add tlbi-on-map property to the smmuv3 node >> target/arm/kvm: Translate the MSI doorbell in kvm_arch_fixup_msi_route >> hw/arm/smmuv3: VFIO integration >> >> Prem Mallappa (3): >> hw/arm/smmuv3: smmuv3 emulation model >> hw/arm/virt: Add SMMUv3 to the virt board >> hw/arm/virt-acpi-build: Add smmuv3 node in IORT table >> >> default-configs/aarch64-softmmu.mak | 1 + >> hw/arm/Makefile.objs | 1 + >> hw/arm/smmu-common.c | 474 +++++++++++++ >> hw/arm/smmu-internal.h | 89 +++ >> hw/arm/smmuv3-internal.h | 651 ++++++++++++++++++ >> hw/arm/smmuv3.c | 1256 >> +++++++++++++++++++++++++++++++++++ >> hw/arm/trace-events | 54 ++ >> hw/arm/virt-acpi-build.c | 56 +- >> hw/arm/virt.c | 111 +++- >> include/hw/acpi/acpi-defs.h | 15 + >> include/hw/arm/smmu-common.h | 127 ++++ >> include/hw/arm/smmuv3.h | 87 +++ >> include/hw/arm/virt.h | 5 + >> target/arm/kvm.c | 28 + >> target/arm/trace-events | 3 + >> 15 files changed, 2949 insertions(+), 9 deletions(-) >> create mode 100644 hw/arm/smmu-common.c >> create mode 100644 hw/arm/smmu-internal.h >> create mode 100644 hw/arm/smmuv3-internal.h >> create mode 100644 hw/arm/smmuv3.c >> create mode 100644 include/hw/arm/smmu-common.h >> create mode 100644 include/hw/arm/smmuv3.h >> From MAILER-DAEMON Tue Aug 01 09:50:27 2017 Received: from list by lists.gnu.org with archive (Exim 4.71) id 1dcXZ5-0005om-4G for mharc-qemu-arm@gnu.org; Tue, 01 Aug 2017 09:50:27 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:35511) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dcUvh-0002dV-IK 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X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM5PR07MB2812 X-detected-operating-system: by eggs.gnu.org: Windows 7 or 8 [fuzzy] X-Received-From: 104.47.32.41 X-Mailman-Approved-At: Tue, 01 Aug 2017 09:50:26 -0400 Subject: Re: [Qemu-arm] [RFC v5 0/8] ARM SMMUv3 Emulation Support X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 01 Aug 2017 11:01:39 -0000 Hi Eric, Just letting you know that I am facing another issue with the following setup: 1. host (4.12 kernel & 64K page) and VM (4.12 kernel & 64K page) 2. QEMU + -netdev type=tap,ifname=tap,id=net0 -device virtio-net-pci,netdev=net0,iommu_platform,disable-modern=off,disable-legacy=on 2. On VM, I allocate some huge pages and run DPDK testpmd app: # echo 4 > /sys/kernel/mm/hugepages/hugepages-524288kB/nr_hugepages # ./dpdk/usertools/dpdk-devbind.py -b vfio-pci 0000:00:02.0 # ./dpdk/build/app/testpmd -l 0-13 -n 4 -w 0000:00:02.0 -- --disable-hw-vlan-filter --disable-rss -i EAL: Detected 14 lcore(s) EAL: Probing VFIO support... EAL: VFIO support initialized EAL: PCI device 0000:00:02.0 on NUMA socket -1 EAL: probe driver: 1af4:1041 net_virtio EAL: using IOMMU type 1 (Type 1) EAL: iommu_map_dma vaddr ffff20000000 size 80000000 iova 120000000 EAL: Can't write to PCI bar (0) : offset (12) EAL: Can't read from PCI bar (0) : offset (12) EAL: Can't read from PCI bar (0) : offset (12) EAL: Can't write to PCI bar (0) : offset (12) EAL: Can't read from PCI bar (0) : offset (12) EAL: Can't write to PCI bar (0) : offset (12) EAL: Can't read from PCI bar (0) : offset (0) EAL: Can't write to PCI bar (0) : offset (4) EAL: Can't write to PCI bar (0) : offset (14) EAL: Can't write to PCI bar (0) : offset (e) EAL: Can't read from PCI bar (0) : offset (c) EAL: Requested device 0000:00:02.0 cannot be used EAL: No probed ethernet devices Interactive-mode selected USER1: create a new mbuf pool : n=251456, size=2176, socket=0 When VM uses *4K pages* the same setup works fine. I will work on this but please let me know in case you already know what is going on. Thanks, Tomasz On 09.07.2017 22:51, Eric Auger wrote: > This series implements the emulation code for ARM SMMUv3. > This is the continuation of Prem's work [1]. > > This v5 mainly brings VFIO integration in DT mode. On guest kernel > side, this requires a quirk [1] to force TLB invalidation on map. > > The following changes also are noticeable: > - fix SMMU_CMDQ_CONS offset > - adds dma-coherent dt property which fixes the unhandled command > opcode bug. > - implements block PTE > > The smmu is instantiated when passing the smmu option to machvirt: > "-M virt-2.10,smmu" > > As I haven't split the code yet so that it can be easily reviewable > I don't expect deep reviews at this stage. Also the implementation may > be largely sub-optimal. > > Tested Use Cases: > - booted a guest in dt and acpi mode with an iommu_platform > virtio-net-pci device (using dma ops). Tested with the following > guest combinations: 4K page - 39 bit VA, 4K - 48b, 64K - 39b, > 64K - 48b. > - booted a guest (featuring [1]) with PCIe passthrough'ed PCIe devices: > - AMD Overdrive and igbvf passthrough (using gsi direct mapping) > - Cavium ThunderX and ixgbevf passthrough (using KVM MSI routing) > > Unfortunately I have not been able to run DPDK testpmd yet on guest side. > The problem I see is the user space driver dma-maps a huge area > and this causes plenty of CMDQ_OP_TLBI_NH_VA commands to be sent > (tlbi-on-map) which are sent for each page whereas the dma-map covers a > huge page. I will work on this issue for next version. > > Known limitations: > - no VMSAv8-32 suport > - no nested stage support (S1 + S2) > - no support for HYP mappings > - register fine emulation, commands, interrupts and errors were > not accurately tested. Handling is sufficient to run use cases > described hereafter though. > > Best Regards > > Eric > > This series can be found at: > v5: https://github.com/eauger/qemu/tree/v2.9-SMMU-v5 > v4: https://github.com/eauger/qemu/tree/v2.9-SMMU-v4 > > References: > [1] [RFC 0/2] arm-smmu-v3 tlbi-on-map option > [2] Prem's last iteration: > - https://lists.gnu.org/archive/html/qemu-devel/2016-08/msg03531.html > > History: > v4 -> v5: > - initial_level now part of SMMUTransCfg > - smmu_page_walk_64 takes into account the max input size > - implement sys->iommu_ops.replay and sys->iommu_ops.notify_flag_changed > - smmuv3_translate: bug fix: don't walk on bypass > - smmu_update_qreg: fix PROD index update > - I did not yet address Peter's comments as the code is not mature enough > to be split into sub patches. > > v3 -> v4 [Eric]: > - page table walk rewritten to allow scan of the page table within a > range of IOVA. This prepares for VFIO integration and replay. > - configuration parsing partially reworked. > - do not advertise unsupported/untested features: S2, S1 + S2, HYP, > PRI, ATS, .. > - added ACPI table generation > - migrated to dynamic traces > - mingw compilation fix > > v2 -> v3 [Eric]: > - rebased on 2.9 > - mostly code and patch reorganization to ease the review process > - optional patches removed. They may be handled separately. I am currently > working on ACPI enablement. > - optional instantiation of the smmu in mach-virt > - removed [2/9] (fdt functions) since not mandated > - start splitting main patch into base and derived object > - no new function feature added > > v1 -> v2 [Prem]: > - Adopted review comments from Eric Auger > - Make SMMU_DPRINTF to internally call qemu_log > (since translation requests are too many, we need control > on the type of log we want) > - SMMUTransCfg modified to suite simplicity > - Change RegInfo to uint64 register array > - Code cleanup > - Test cleanups > - Reshuffled patches > > v0 -> v1 [Prem]: > - As per SMMUv3 spec 16.0 (only is_ste_consistant() is noticeable) > - Reworked register access/update logic > - Factored out translation code for > - single point bug fix > - sharing/removal in future > - (optional) Unit tests added, with PCI test device > - S1 with 4k/64k, S1+S2 with 4k/64k > - (S1 or S2) only can be verified by Linux 4.7 driver > - (optional) Priliminary ACPI support > > v0 [Prem]: > - Implements SMMUv3 spec 11.0 > - Supported for PCIe devices, > - Command Queue and Event Queue supported > - LPAE only, S1 is supported and Tested, S2 not tested > - BE mode Translation not supported > - IRQ support (legacy, no MSI) > - Tested with DPDK and e1000 > > > Eric Auger (5): > hw/arm/smmu-common: smmu base class > hw/arm/virt: Add 2.10 machine type > hw/arm/virt: Add tlbi-on-map property to the smmuv3 node > target/arm/kvm: Translate the MSI doorbell in kvm_arch_fixup_msi_route > hw/arm/smmuv3: VFIO integration > > Prem Mallappa (3): > hw/arm/smmuv3: smmuv3 emulation model > hw/arm/virt: Add SMMUv3 to the virt board > hw/arm/virt-acpi-build: Add smmuv3 node in IORT table > > default-configs/aarch64-softmmu.mak | 1 + > hw/arm/Makefile.objs | 1 + > hw/arm/smmu-common.c | 474 +++++++++++++ > hw/arm/smmu-internal.h | 89 +++ > hw/arm/smmuv3-internal.h | 651 ++++++++++++++++++ > hw/arm/smmuv3.c | 1256 +++++++++++++++++++++++++++++++++++ > hw/arm/trace-events | 54 ++ > hw/arm/virt-acpi-build.c | 56 +- > hw/arm/virt.c | 111 +++- > include/hw/acpi/acpi-defs.h | 15 + > include/hw/arm/smmu-common.h | 127 ++++ > include/hw/arm/smmuv3.h | 87 +++ > include/hw/arm/virt.h | 5 + > target/arm/kvm.c | 28 + > target/arm/trace-events | 3 + > 15 files changed, 2949 insertions(+), 9 deletions(-) > create mode 100644 hw/arm/smmu-common.c > create mode 100644 hw/arm/smmu-internal.h > create mode 100644 hw/arm/smmuv3-internal.h > create mode 100644 hw/arm/smmuv3.c > create mode 100644 include/hw/arm/smmu-common.h > create mode 100644 include/hw/arm/smmuv3.h > From MAILER-DAEMON Wed Aug 02 04:37:38 2017 Received: from list by lists.gnu.org with archive (Exim 4.71) id 1dcp9u-0003Wq-HT for mharc-qemu-arm@gnu.org; Wed, 02 Aug 2017 04:37:38 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:46182) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dcp9r-0003Wa-Mz for qemu-arm@nongnu.org; Wed, 02 Aug 2017 04:37:37 -0400 Received: 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Received: from keelia (unknown [203.0.153.9]) by mail.messagingengine.com (Postfix) with ESMTPA id 7FD9D241DF; Wed, 2 Aug 2017 04:37:26 -0400 (EDT) Message-ID: <1501663040.29409.3.camel@aj.id.au> From: Andrew Jeffery To: =?ISO-8859-1?Q?C=E9dric?= Le Goater , qemu-arm@nongnu.org Cc: qemu-devel@nongnu.org, peter.maydell@linaro.org, joel@jms.id.au, openbmc@lists.ozlabs.org Date: Wed, 02 Aug 2017 18:07:20 +0930 In-Reply-To: <855a154a-4cdf-b29a-6440-5deadbeed12e@kaod.org> References: <20170801010425.25778-1-andrew@aj.id.au> <855a154a-4cdf-b29a-6440-5deadbeed12e@kaod.org> Content-Type: multipart/signed; micalg="pgp-sha512"; protocol="application/pgp-signature"; boundary="=-JEaDxwHEhN5nLi7aYnCM" X-Mailer: Evolution 3.22.6-1ubuntu1 Mime-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 66.111.4.25 Subject: Re: [Qemu-arm] [PATCH] watchdog: wdt_aspeed: Add support for the reset width register X-BeenThere: qemu-arm@nongnu.org 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(envelope-from ) id 1dctPy-00083v-1A for qemu-arm@nongnu.org; Wed, 02 Aug 2017 09:10:34 -0400 Received: from mx1.redhat.com ([209.132.183.28]:39300) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1dctPx-0007yb-Rg; Wed, 02 Aug 2017 09:10:29 -0400 Received: from smtp.corp.redhat.com (int-mx02.intmail.prod.int.phx2.redhat.com [10.5.11.12]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id 383DF10E08; Wed, 2 Aug 2017 13:10:26 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mx1.redhat.com 383DF10E08 Authentication-Results: ext-mx03.extmail.prod.ext.phx2.redhat.com; dmarc=none (p=none dis=none) header.from=redhat.com Authentication-Results: ext-mx03.extmail.prod.ext.phx2.redhat.com; spf=fail smtp.mailfrom=ehabkost@redhat.com Received: from localhost (ovpn-116-46.gru2.redhat.com [10.97.116.46]) by smtp.corp.redhat.com (Postfix) with ESMTP id C8A9A7F568; Wed, 2 Aug 2017 13:10:22 +0000 (UTC) Date: Wed, 2 Aug 2017 10:10:21 -0300 From: Eduardo Habkost To: qemu-devel@nongnu.org Cc: Markus Armbruster , "Michael S. Tsirkin" , Peter Maydell , qemu-arm@nongnu.org Message-ID: <20170802131021.GF3108@localhost.localdomain> References: <20170801230155.21083-1-ehabkost@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20170801230155.21083-1-ehabkost@redhat.com> X-Fnord: you can see the fnord User-Agent: Mutt/1.8.0 (2017-02-23) X-Scanned-By: MIMEDefang 2.79 on 10.5.11.12 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.27]); Wed, 02 Aug 2017 13:10:26 +0000 (UTC) X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.132.183.28 Subject: Re: [Qemu-arm] [PATCH] virtio: Mark virtio-device as non-user-creatable X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 02 Aug 2017 13:10:36 -0000 On Tue, Aug 01, 2017 at 08:01:55PM -0300, Eduardo Habkost wrote: > TYPE_VIRTIO_DEVICE devices are already not usable with -device > and device_add, but they are reported as user-creatable on > "-device help" and through monitor interfaces. > > Mark them as not user-creatable to avoid confusing users, and to > allow automated testing (e.g. scripts/device-crash-test) to skip > them. > > Before this patch, device-crash-test will try to test > virtio-device devices with all machine-types: > > $ time ./scripts/device-crash-test -D virtio-device -v ./x86_64-softmmu/qemu-system-x86_64 > [...] > INFO: Total: 1088 test cases > INFO: Skipped 408 test cases > > real 0m49.775s > > After this patch, the script won't try to test virtio-device > devices: > > $ time ./scripts/device-crash-test -D virtio-device -v ./x86_64-softmmu/qemu-system-x86_64 > INFO: Total: 0 test cases > > real 0m0.092s > > Signed-off-by: Eduardo Habkost > --- > hw/virtio/virtio.c | 11 +++++++++++ > 1 file changed, 11 insertions(+) > > diff --git a/hw/virtio/virtio.c b/hw/virtio/virtio.c > index 464947f..c4bdb94 100644 > --- a/hw/virtio/virtio.c > +++ b/hw/virtio/virtio.c > @@ -2653,6 +2653,17 @@ static void virtio_device_class_init(ObjectClass *klass, void *data) > dc->unrealize = virtio_device_unrealize; > dc->bus_type = TYPE_VIRTIO_BUS; > dc->props = virtio_properties; > + /* > + * Reason: > + * - TYPE_VIRTIO_DEVICE devices are not visible to guests > + * unless they are created and controlled by transport-specific > + * devices (virtio-pci, virtio-mmio, and virtio-ccw). > + * - A TYPE_VIRTIO_BUS bus is never available for plugging > + * using -device/device_add, as virtio-bus buses are > + * created on the fly and immediately populated by the > + * transport-specific devices' realize methods. > + */ Oops, I just found out that this is not true on virtio-mmio: unused virtio-mmio-bus buses are available for plugging when virtio-mmio devices are created. So at least on arm, there are virtio-bus buses where virtio-device devices can be plugged by users, and this patch is incorrect. > + dc->user_creatable = false; > vdc->start_ioeventfd = virtio_device_start_ioeventfd_impl; > vdc->stop_ioeventfd = virtio_device_stop_ioeventfd_impl; > > -- > 2.9.4 > -- Eduardo From MAILER-DAEMON Wed Aug 02 12:44:30 2017 Received: from list by lists.gnu.org with archive (Exim 4.71) id 1dcwl4-0003U4-Os for mharc-qemu-arm@gnu.org; Wed, 02 Aug 2017 12:44:30 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:49332) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dcwl2-0003TY-BL for qemu-arm@nongnu.org; Wed, 02 Aug 2017 12:44:29 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dcwl1-0004Xg-1i for qemu-arm@nongnu.org; Wed, 02 Aug 2017 12:44:28 -0400 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:37764) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1dcwl0-0003zA-NO; Wed, 02 Aug 2017 12:44:26 -0400 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.84_2) (envelope-from ) id 1dcwkc-0003wC-QZ; Wed, 02 Aug 2017 17:44:02 +0100 From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: patches@linaro.org Date: Wed, 2 Aug 2017 17:43:47 +0100 Message-Id: <1501692241-23310-2-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1501692241-23310-1-git-send-email-peter.maydell@linaro.org> References: <1501692241-23310-1-git-send-email-peter.maydell@linaro.org> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-arm] [PATCH 01/15] target/arm: Use MMUAccessType enum rather than int X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 02 Aug 2017 16:44:29 -0000 In the ARM get_phys_addr() code, switch to using the MMUAccessType enum and its MMU_* values rather than int and literal 0/1/2. Signed-off-by: Peter Maydell --- target/arm/helper.c | 30 +++++++++++++++--------------- target/arm/internals.h | 3 ++- 2 files changed, 17 insertions(+), 16 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index fa60040..b78d277 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -20,13 +20,13 @@ #ifndef CONFIG_USER_ONLY static bool get_phys_addr(CPUARMState *env, target_ulong address, - int access_type, ARMMMUIdx mmu_idx, + MMUAccessType access_type, ARMMMUIdx mmu_idx, hwaddr *phys_ptr, MemTxAttrs *attrs, int *prot, target_ulong *page_size, uint32_t *fsr, ARMMMUFaultInfo *fi); static bool get_phys_addr_lpae(CPUARMState *env, target_ulong address, - int access_type, ARMMMUIdx mmu_idx, + MMUAccessType access_type, ARMMMUIdx mmu_idx, hwaddr *phys_ptr, MemTxAttrs *txattrs, int *prot, target_ulong *page_size_ptr, uint32_t *fsr, ARMMMUFaultInfo *fi); @@ -2135,7 +2135,7 @@ static CPAccessResult ats_access(CPUARMState *env, const ARMCPRegInfo *ri, } static uint64_t do_ats_write(CPUARMState *env, uint64_t value, - int access_type, ARMMMUIdx mmu_idx) + MMUAccessType access_type, ARMMMUIdx mmu_idx) { hwaddr phys_addr; target_ulong page_size; @@ -2194,7 +2194,7 @@ static uint64_t do_ats_write(CPUARMState *env, uint64_t value, static void ats_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { - int access_type = ri->opc2 & 1; + MMUAccessType access_type = ri->opc2 & 1 ? MMU_DATA_STORE : MMU_DATA_LOAD; uint64_t par64; ARMMMUIdx mmu_idx; int el = arm_current_el(env); @@ -2253,7 +2253,7 @@ static void ats_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) static void ats1h_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { - int access_type = ri->opc2 & 1; + MMUAccessType access_type = ri->opc2 & 1 ? MMU_DATA_STORE : MMU_DATA_LOAD; uint64_t par64; par64 = do_ats_write(env, value, access_type, ARMMMUIdx_S2NS); @@ -2273,7 +2273,7 @@ static CPAccessResult at_s1e2_access(CPUARMState *env, const ARMCPRegInfo *ri, static void ats_write64(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { - int access_type = ri->opc2 & 1; + MMUAccessType access_type = ri->opc2 & 1 ? MMU_DATA_STORE : MMU_DATA_LOAD; ARMMMUIdx mmu_idx; int secure = arm_is_secure_below_el3(env); @@ -7510,7 +7510,7 @@ static uint64_t arm_ldq_ptw(CPUState *cs, hwaddr addr, bool is_secure, } static bool get_phys_addr_v5(CPUARMState *env, uint32_t address, - int access_type, ARMMMUIdx mmu_idx, + MMUAccessType access_type, ARMMMUIdx mmu_idx, hwaddr *phys_ptr, int *prot, target_ulong *page_size, uint32_t *fsr, ARMMMUFaultInfo *fi) @@ -7626,7 +7626,7 @@ do_fault: } static bool get_phys_addr_v6(CPUARMState *env, uint32_t address, - int access_type, ARMMMUIdx mmu_idx, + MMUAccessType access_type, ARMMMUIdx mmu_idx, hwaddr *phys_ptr, MemTxAttrs *attrs, int *prot, target_ulong *page_size, uint32_t *fsr, ARMMMUFaultInfo *fi) @@ -7733,7 +7733,7 @@ static bool get_phys_addr_v6(CPUARMState *env, uint32_t address, if (pxn && !regime_is_user(env, mmu_idx)) { xn = 1; } - if (xn && access_type == 2) + if (xn && access_type == MMU_INST_FETCH) goto do_fault; if (arm_feature(env, ARM_FEATURE_V6K) && @@ -7848,7 +7848,7 @@ static bool check_s2_mmu_setup(ARMCPU *cpu, bool is_aa64, int level, } static bool get_phys_addr_lpae(CPUARMState *env, target_ulong address, - int access_type, ARMMMUIdx mmu_idx, + MMUAccessType access_type, ARMMMUIdx mmu_idx, hwaddr *phys_ptr, MemTxAttrs *txattrs, int *prot, target_ulong *page_size_ptr, uint32_t *fsr, ARMMMUFaultInfo *fi) @@ -8256,7 +8256,7 @@ static inline bool m_is_system_region(CPUARMState *env, uint32_t address) } static bool get_phys_addr_pmsav7(CPUARMState *env, uint32_t address, - int access_type, ARMMMUIdx mmu_idx, + MMUAccessType access_type, ARMMMUIdx mmu_idx, hwaddr *phys_ptr, int *prot, uint32_t *fsr) { ARMCPU *cpu = arm_env_get_cpu(env); @@ -8415,7 +8415,7 @@ static bool get_phys_addr_pmsav7(CPUARMState *env, uint32_t address, } static bool get_phys_addr_pmsav5(CPUARMState *env, uint32_t address, - int access_type, ARMMMUIdx mmu_idx, + MMUAccessType access_type, ARMMMUIdx mmu_idx, hwaddr *phys_ptr, int *prot, uint32_t *fsr) { int n; @@ -8442,7 +8442,7 @@ static bool get_phys_addr_pmsav5(CPUARMState *env, uint32_t address, return true; } - if (access_type == 2) { + if (access_type == MMU_INST_FETCH) { mask = env->cp15.pmsav5_insn_ap; } else { mask = env->cp15.pmsav5_data_ap; @@ -8513,7 +8513,7 @@ static bool get_phys_addr_pmsav5(CPUARMState *env, uint32_t address, * @fsr: set to the DFSR/IFSR value on failure */ static bool get_phys_addr(CPUARMState *env, target_ulong address, - int access_type, ARMMMUIdx mmu_idx, + MMUAccessType access_type, ARMMMUIdx mmu_idx, hwaddr *phys_ptr, MemTxAttrs *attrs, int *prot, target_ulong *page_size, uint32_t *fsr, ARMMMUFaultInfo *fi) @@ -8626,7 +8626,7 @@ static bool get_phys_addr(CPUARMState *env, target_ulong address, * fsr with ARM DFSR/IFSR fault register format value on failure. */ bool arm_tlb_fill(CPUState *cs, vaddr address, - int access_type, int mmu_idx, uint32_t *fsr, + MMUAccessType access_type, int mmu_idx, uint32_t *fsr, ARMMMUFaultInfo *fi) { ARMCPU *cpu = ARM_CPU(cs); diff --git a/target/arm/internals.h b/target/arm/internals.h index 1f6efef..bb06946 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -457,7 +457,8 @@ struct ARMMMUFaultInfo { }; /* Do a page table walk and add page to TLB if possible */ -bool arm_tlb_fill(CPUState *cpu, vaddr address, int rw, int mmu_idx, +bool arm_tlb_fill(CPUState *cpu, vaddr address, + MMUAccessType access_type, int mmu_idx, uint32_t *fsr, ARMMMUFaultInfo *fi); /* Return true if the stage 1 translation regime is using LPAE format page -- 2.7.4 From MAILER-DAEMON Wed Aug 02 12:44:31 2017 Received: from list by lists.gnu.org with archive (Exim 4.71) id 1dcwl5-0003Uk-JQ for mharc-qemu-arm@gnu.org; Wed, 02 Aug 2017 12:44:31 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:49356) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dcwl3-0003Th-LY for qemu-arm@nongnu.org; Wed, 02 Aug 2017 12:44:30 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dcwl2-0004cS-No for qemu-arm@nongnu.org; Wed, 02 Aug 2017 12:44:29 -0400 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:37764) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1dcwl2-0003zA-HK; Wed, 02 Aug 2017 12:44:28 -0400 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.84_2) (envelope-from ) id 1dcwkj-000417-AT; Wed, 02 Aug 2017 17:44:09 +0100 From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: patches@linaro.org Date: Wed, 2 Aug 2017 17:44:00 +0100 Message-Id: <1501692241-23310-15-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1501692241-23310-1-git-send-email-peter.maydell@linaro.org> References: <1501692241-23310-1-git-send-email-peter.maydell@linaro.org> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-arm] [PATCH 14/15] armv7m_nvic.h: Move from include/hw/arm to include/hw/intc X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 02 Aug 2017 16:44:30 -0000 The armv7m_nvic.h header file was accidentally placed in include/hw/arm; move it to include/hw/intc to match where its corresponding .c file lives. Signed-off-by: Peter Maydell --- hw/intc/armv7m_nvic.c | 2 +- include/hw/arm/armv7m.h | 2 +- include/hw/{arm => intc}/armv7m_nvic.h | 0 3 files changed, 2 insertions(+), 2 deletions(-) rename include/hw/{arm => intc}/armv7m_nvic.h (100%) diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c index 343bc16..5a18025 100644 --- a/hw/intc/armv7m_nvic.c +++ b/hw/intc/armv7m_nvic.c @@ -17,7 +17,7 @@ #include "hw/sysbus.h" #include "qemu/timer.h" #include "hw/arm/arm.h" -#include "hw/arm/armv7m_nvic.h" +#include "hw/intc/armv7m_nvic.h" #include "target/arm/cpu.h" #include "exec/exec-all.h" #include "qemu/log.h" diff --git a/include/hw/arm/armv7m.h b/include/hw/arm/armv7m.h index a9b3f2a..10eb058 100644 --- a/include/hw/arm/armv7m.h +++ b/include/hw/arm/armv7m.h @@ -11,7 +11,7 @@ #define HW_ARM_ARMV7M_H #include "hw/sysbus.h" -#include "hw/arm/armv7m_nvic.h" +#include "hw/intc/armv7m_nvic.h" #define TYPE_BITBAND "ARM,bitband-memory" #define BITBAND(obj) OBJECT_CHECK(BitBandState, (obj), TYPE_BITBAND) diff --git a/include/hw/arm/armv7m_nvic.h b/include/hw/intc/armv7m_nvic.h similarity index 100% rename from include/hw/arm/armv7m_nvic.h rename to include/hw/intc/armv7m_nvic.h -- 2.7.4 From MAILER-DAEMON Wed Aug 02 12:44:32 2017 Received: from list by lists.gnu.org with archive (Exim 4.71) id 1dcwl5-0003V5-Sh for mharc-qemu-arm@gnu.org; Wed, 02 Aug 2017 12:44:31 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:49352) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dcwl3-0003Tc-DV for qemu-arm@nongnu.org; Wed, 02 Aug 2017 12:44:30 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dcwl1-0004a4-UA for qemu-arm@nongnu.org; Wed, 02 Aug 2017 12:44:29 -0400 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:37764) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1dcwl1-0003zA-LF; Wed, 02 Aug 2017 12:44:27 -0400 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.84_2) (envelope-from ) id 1dcwkj-00041K-Op; Wed, 02 Aug 2017 17:44:09 +0100 From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: patches@linaro.org Date: Wed, 2 Aug 2017 17:44:01 +0100 Message-Id: <1501692241-23310-16-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1501692241-23310-1-git-send-email-peter.maydell@linaro.org> References: <1501692241-23310-1-git-send-email-peter.maydell@linaro.org> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-arm] [PATCH 15/15] nvic: Implement "user accesses BusFault" SCS region behaviour X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 02 Aug 2017 16:44:30 -0000 The ARMv7M architecture specifies that most of the addresses in the PPB region (which includes the NVIC, systick and system registers) are not accessible to unprivileged accesses, which should BusFault with a few exceptions: * the STIR is configurably user-accessible * the ITM (which we don't implement at all) is always user-accessible Implement this by switching the register access functions to the _with_attrs scheme that lets us distinguish user mode accesses. This allows us to pull the handling of the CCR.USERSETMPEND flag up to the level where we can make it generate a BusFault as it should for non-permitted accesses. Note that until the core ARM CPU code implements turning MEMTX_ERROR into a BusFault the registers will continue to act as RAZ/WI to user accesses. Signed-off-by: Peter Maydell --- hw/intc/armv7m_nvic.c | 58 ++++++++++++++++++++++++++++++++++++--------------- 1 file changed, 41 insertions(+), 17 deletions(-) diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c index 5a18025..bbfe2d5 100644 --- a/hw/intc/armv7m_nvic.c +++ b/hw/intc/armv7m_nvic.c @@ -733,11 +733,8 @@ static void nvic_writel(NVICState *s, uint32_t offset, uint32_t value) } case 0xf00: /* Software Triggered Interrupt Register */ { - /* user mode can only write to STIR if CCR.USERSETMPEND permits it */ int excnum = (value & 0x1ff) + NVIC_FIRST_IRQ; - if (excnum < s->num_irq && - (arm_current_el(&cpu->env) || - (cpu->env.v7m.ccr & R_V7M_CCR_USERSETMPEND_MASK))) { + if (excnum < s->num_irq) { armv7m_nvic_set_pending(s, excnum); } break; @@ -748,14 +745,32 @@ static void nvic_writel(NVICState *s, uint32_t offset, uint32_t value) } } -static uint64_t nvic_sysreg_read(void *opaque, hwaddr addr, - unsigned size) +static bool nvic_user_access_ok(NVICState *s, hwaddr offset) +{ + /* Return true if unprivileged access to this register is permitted. */ + switch (offset) { + case 0xf00: /* STIR: accessible only if CCR.USERSETMPEND permits */ + return s->cpu->env.v7m.ccr & R_V7M_CCR_USERSETMPEND_MASK; + default: + /* All other user accesses cause a BusFault unconditionally */ + return false; + } +} + +static MemTxResult nvic_sysreg_read(void *opaque, hwaddr addr, + uint64_t *data, unsigned size, + MemTxAttrs attrs) { NVICState *s = (NVICState *)opaque; uint32_t offset = addr; unsigned i, startvec, end; uint32_t val; + if (attrs.user && !nvic_user_access_ok(s, addr)) { + /* Generate BusFault for unprivileged accesses */ + return MEMTX_ERROR; + } + switch (offset) { /* reads of set and clear both return the status */ case 0x100 ... 0x13f: /* NVIC Set enable */ @@ -826,11 +841,13 @@ static uint64_t nvic_sysreg_read(void *opaque, hwaddr addr, } trace_nvic_sysreg_read(addr, val, size); - return val; + *data = val; + return MEMTX_OK; } -static void nvic_sysreg_write(void *opaque, hwaddr addr, - uint64_t value, unsigned size) +static MemTxResult nvic_sysreg_write(void *opaque, hwaddr addr, + uint64_t value, unsigned size, + MemTxAttrs attrs) { NVICState *s = (NVICState *)opaque; uint32_t offset = addr; @@ -839,6 +856,11 @@ static void nvic_sysreg_write(void *opaque, hwaddr addr, trace_nvic_sysreg_write(addr, value, size); + if (attrs.user && !nvic_user_access_ok(s, addr)) { + /* Generate BusFault for unprivileged accesses */ + return MEMTX_ERROR; + } + switch (offset) { case 0x100 ... 0x13f: /* NVIC Set enable */ offset += 0x80; @@ -853,7 +875,7 @@ static void nvic_sysreg_write(void *opaque, hwaddr addr, } } nvic_irq_update(s); - return; + return MEMTX_OK; case 0x200 ... 0x23f: /* NVIC Set pend */ /* the special logic in armv7m_nvic_set_pending() * is not needed since IRQs are never escalated @@ -870,9 +892,9 @@ static void nvic_sysreg_write(void *opaque, hwaddr addr, } } nvic_irq_update(s); - return; + return MEMTX_OK; case 0x300 ... 0x33f: /* NVIC Active */ - return; /* R/O */ + return MEMTX_OK; /* R/O */ case 0x400 ... 0x5ef: /* NVIC Priority */ startvec = 8 * (offset - 0x400) + NVIC_FIRST_IRQ; /* vector # */ @@ -880,26 +902,28 @@ static void nvic_sysreg_write(void *opaque, hwaddr addr, set_prio(s, startvec + i, (value >> (i * 8)) & 0xff); } nvic_irq_update(s); - return; + return MEMTX_OK; case 0xd18 ... 0xd23: /* System Handler Priority. */ for (i = 0; i < size; i++) { unsigned hdlidx = (offset - 0xd14) + i; set_prio(s, hdlidx, (value >> (i * 8)) & 0xff); } nvic_irq_update(s); - return; + return MEMTX_OK; } if (size == 4) { nvic_writel(s, offset, value); - return; + return MEMTX_OK; } qemu_log_mask(LOG_GUEST_ERROR, "NVIC: Bad write of size %d at offset 0x%x\n", size, offset); + /* This is UNPREDICTABLE; treat as RAZ/WI */ + return MEMTX_OK; } static const MemoryRegionOps nvic_sysreg_ops = { - .read = nvic_sysreg_read, - .write = nvic_sysreg_write, + .read_with_attrs = nvic_sysreg_read, + .write_with_attrs = nvic_sysreg_write, .endianness = DEVICE_NATIVE_ENDIAN, }; -- 2.7.4 From MAILER-DAEMON Wed Aug 02 12:44:32 2017 Received: from list by lists.gnu.org with archive (Exim 4.71) id 1dcwl6-0003W6-NQ for mharc-qemu-arm@gnu.org; Wed, 02 Aug 2017 12:44:32 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:49395) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dcwl5-0003UO-2B for qemu-arm@nongnu.org; Wed, 02 Aug 2017 12:44:31 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dcwl4-0004dz-C5 for qemu-arm@nongnu.org; Wed, 02 Aug 2017 12:44:31 -0400 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:37764) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1dcwl4-0003zA-51; Wed, 02 Aug 2017 12:44:30 -0400 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.84_2) (envelope-from ) id 1dcwki-00040L-D5; Wed, 02 Aug 2017 17:44:08 +0100 From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: patches@linaro.org Date: Wed, 2 Aug 2017 17:43:58 +0100 Message-Id: <1501692241-23310-13-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1501692241-23310-1-git-send-email-peter.maydell@linaro.org> References: <1501692241-23310-1-git-send-email-peter.maydell@linaro.org> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-arm] [PATCH 12/15] target/arm: Don't calculate lr in arm_v7m_cpu_do_interrupt() until needed X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 02 Aug 2017 16:44:32 -0000 Move the code in arm_v7m_cpu_do_interrupt() that calculates the magic LR value down to when we're actually going to use it. Having the calculation and use so far apart makes the code a little harder to understand than it needs to be. Signed-off-by: Peter Maydell --- target/arm/helper.c | 15 ++++++++------- 1 file changed, 8 insertions(+), 7 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index b64ddb1..0ecc8f1 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -6311,13 +6311,6 @@ void arm_v7m_cpu_do_interrupt(CPUState *cs) arm_log_exception(cs->exception_index); - lr = 0xfffffff1; - if (env->v7m.control & R_V7M_CONTROL_SPSEL_MASK) { - lr |= 4; - } - if (env->v7m.exception == 0) - lr |= 8; - /* For exceptions we just mark as pending on the NVIC, and let that handle it. */ switch (cs->exception_index) { @@ -6408,6 +6401,14 @@ void arm_v7m_cpu_do_interrupt(CPUState *cs) return; /* Never happens. Keep compiler happy. */ } + lr = 0xfffffff1; + if (env->v7m.control & R_V7M_CONTROL_SPSEL_MASK) { + lr |= 4; + } + if (env->v7m.exception == 0) { + lr |= 8; + } + v7m_push_stack(cpu); v7m_exception_taken(cpu, lr); qemu_log_mask(CPU_LOG_INT, "... as %d\n", env->v7m.exception); -- 2.7.4 From MAILER-DAEMON Wed Aug 02 12:44:33 2017 Received: from list by lists.gnu.org with archive (Exim 4.71) id 1dcwl7-0003Wg-32 for mharc-qemu-arm@gnu.org; Wed, 02 Aug 2017 12:44:33 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:49381) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dcwl4-0003Tu-J9 for qemu-arm@nongnu.org; Wed, 02 Aug 2017 12:44:31 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dcwl3-0004d1-Iy for qemu-arm@nongnu.org; Wed, 02 Aug 2017 12:44:30 -0400 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:37764) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1dcwl3-0003zA-BQ; Wed, 02 Aug 2017 12:44:29 -0400 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.84_2) (envelope-from ) id 1dcwki-00040j-RZ; Wed, 02 Aug 2017 17:44:08 +0100 From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: patches@linaro.org Date: Wed, 2 Aug 2017 17:43:59 +0100 Message-Id: <1501692241-23310-14-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1501692241-23310-1-git-send-email-peter.maydell@linaro.org> References: <1501692241-23310-1-git-send-email-peter.maydell@linaro.org> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-arm] [PATCH 13/15] target/arm: Create and use new function arm_v7m_is_handler_mode() X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 02 Aug 2017 16:44:32 -0000 Add a utility function for testing whether the CPU is in Handler mode; this is just a check whether v7m.exception is non-zero, but we do it in several places and it makes the code a bit easier to read to not have to mentally figure out what the test is testing. Signed-off-by: Peter Maydell --- target/arm/cpu.h | 10 ++++++++-- target/arm/helper.c | 8 ++++---- 2 files changed, 12 insertions(+), 6 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index da90b7a..a3b4b78 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -1630,13 +1630,19 @@ static inline int arm_highest_el(CPUARMState *env) return 1; } +/* Return true if a v7M CPU is in Handler mode */ +static inline bool arm_v7m_is_handler_mode(CPUARMState *env) +{ + return env->v7m.exception != 0; +} + /* Return the current Exception Level (as per ARMv8; note that this differs * from the ARMv7 Privilege Level). */ static inline int arm_current_el(CPUARMState *env) { if (arm_feature(env, ARM_FEATURE_M)) { - return !((env->v7m.exception == 0) && (env->v7m.control & 1)); + return arm_v7m_is_handler_mode(env) || !(env->v7m.control & 1); } if (is_a64(env)) { @@ -2636,7 +2642,7 @@ static inline void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc, } *flags |= fp_exception_el(env) << ARM_TBFLAG_FPEXC_EL_SHIFT; - if (env->v7m.exception != 0) { + if (arm_v7m_is_handler_mode(env)) { *flags |= ARM_TBFLAG_HANDLER_MASK; } diff --git a/target/arm/helper.c b/target/arm/helper.c index 0ecc8f1..7920153 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -6147,7 +6147,7 @@ static void do_v7m_exception_exit(ARMCPU *cpu) * that jumps to magic addresses don't have magic behaviour unless * we're in Handler mode (compare pseudocode BXWritePC()). */ - assert(env->v7m.exception != 0); + assert(arm_v7m_is_handler_mode(env)); /* In the spec pseudocode ExceptionReturn() is called directly * from BXWritePC() and gets the full target PC value including @@ -6254,7 +6254,7 @@ static void do_v7m_exception_exit(ARMCPU *cpu) * resuming in Thread mode. If that doesn't match what the * exception return type specified then this is a UsageFault. */ - if (return_to_handler == (env->v7m.exception == 0)) { + if (return_to_handler != arm_v7m_is_handler_mode(env)) { /* Take an INVPC UsageFault by pushing the stack again. */ armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE); env->v7m.cfsr |= R_V7M_CFSR_INVPC_MASK; @@ -6405,7 +6405,7 @@ void arm_v7m_cpu_do_interrupt(CPUState *cs) if (env->v7m.control & R_V7M_CONTROL_SPSEL_MASK) { lr |= 4; } - if (env->v7m.exception == 0) { + if (!arm_v7m_is_handler_mode(env)) { lr |= 8; } @@ -8798,7 +8798,7 @@ void HELPER(v7m_msr)(CPUARMState *env, uint32_t maskreg, uint32_t val) * switch_v7m_sp() deals with updating the SPSEL bit in * env->v7m.control, so we only need update the others. */ - if (env->v7m.exception == 0) { + if (!arm_v7m_is_handler_mode(env)) { switch_v7m_sp(env, (val & R_V7M_CONTROL_SPSEL_MASK) != 0); } env->v7m.control &= ~R_V7M_CONTROL_NPRIV_MASK; -- 2.7.4 From MAILER-DAEMON Wed Aug 02 12:44:34 2017 Received: from list by lists.gnu.org with archive (Exim 4.71) id 1dcwl7-0003XZ-Sp for mharc-qemu-arm@gnu.org; Wed, 02 Aug 2017 12:44:33 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:49429) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dcwl6-0003Va-5b for qemu-arm@nongnu.org; Wed, 02 Aug 2017 12:44:33 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dcwl5-0004fi-69 for qemu-arm@nongnu.org; Wed, 02 Aug 2017 12:44:32 -0400 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:37764) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1dcwl4-0003zA-V0; Wed, 02 Aug 2017 12:44:31 -0400 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.84_2) (envelope-from ) id 1dcwkh-0003zm-U3; Wed, 02 Aug 2017 17:44:07 +0100 From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: patches@linaro.org Date: Wed, 2 Aug 2017 17:43:57 +0100 Message-Id: <1501692241-23310-12-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1501692241-23310-1-git-send-email-peter.maydell@linaro.org> References: <1501692241-23310-1-git-send-email-peter.maydell@linaro.org> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-arm] [PATCH 11/15] target/arm: Make arm_cpu_dump_state() handle the M-profile XPSR X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 02 Aug 2017 16:44:33 -0000 Make the arm_cpu_dump_state() debug logging handle the M-profile XPSR rather than assuming it's an A-profile CPSR. On M profile the PSR line of a register dump will now look like this: XPSR=41000000 -Z-- T priv-thread Signed-off-by: Peter Maydell --- target/arm/translate.c | 58 ++++++++++++++++++++++++++++++++++---------------- 1 file changed, 40 insertions(+), 18 deletions(-) diff --git a/target/arm/translate.c b/target/arm/translate.c index 3c14cb0..e52a6d7 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -12215,8 +12215,6 @@ void arm_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf, ARMCPU *cpu = ARM_CPU(cs); CPUARMState *env = &cpu->env; int i; - uint32_t psr; - const char *ns_status; if (is_a64(env)) { aarch64_cpu_dump_state(cs, f, cpu_fprintf, flags); @@ -12230,24 +12228,48 @@ void arm_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf, else cpu_fprintf(f, " "); } - psr = cpsr_read(env); - if (arm_feature(env, ARM_FEATURE_EL3) && - (psr & CPSR_M) != ARM_CPU_MODE_MON) { - ns_status = env->cp15.scr_el3 & SCR_NS ? "NS " : "S "; + if (arm_feature(env, ARM_FEATURE_M)) { + uint32_t xpsr = xpsr_read(env); + const char *mode; + + if (xpsr & XPSR_EXCP) { + mode = "handler"; + } else { + if (env->v7m.control & R_V7M_CONTROL_NPRIV_MASK) { + mode = "unpriv-thread"; + } else { + mode = "priv-thread"; + } + } + + cpu_fprintf(f, "XPSR=%08x %c%c%c%c %c %s\n", + xpsr, + xpsr & XPSR_N ? 'N' : '-', + xpsr & XPSR_Z ? 'Z' : '-', + xpsr & XPSR_C ? 'C' : '-', + xpsr & XPSR_V ? 'V' : '-', + xpsr & XPSR_T ? 'T' : 'A', + mode); } else { - ns_status = ""; - } - - cpu_fprintf(f, "PSR=%08x %c%c%c%c %c %s%s%d\n", - psr, - psr & (1 << 31) ? 'N' : '-', - psr & (1 << 30) ? 'Z' : '-', - psr & (1 << 29) ? 'C' : '-', - psr & (1 << 28) ? 'V' : '-', - psr & CPSR_T ? 'T' : 'A', - ns_status, - cpu_mode_names[psr & 0xf], (psr & 0x10) ? 32 : 26); + uint32_t psr = cpsr_read(env); + const char *ns_status = ""; + + if (arm_feature(env, ARM_FEATURE_EL3) && + (psr & CPSR_M) != ARM_CPU_MODE_MON) { + ns_status = env->cp15.scr_el3 & SCR_NS ? "NS " : "S "; + } + + cpu_fprintf(f, "PSR=%08x %c%c%c%c %c %s%s%d\n", + psr, + psr & CPSR_N ? 'N' : '-', + psr & CPSR_Z ? 'Z' : '-', + psr & CPSR_C ? 'C' : '-', + psr & CPSR_V ? 'V' : '-', + psr & CPSR_T ? 'T' : 'A', + ns_status, + cpu_mode_names[psr & 0xf], (psr & 0x10) ? 32 : 26); + } if (flags & CPU_DUMP_FPU) { int numvfpregs = 0; -- 2.7.4 From MAILER-DAEMON Wed Aug 02 12:44:36 2017 Received: from list by lists.gnu.org with archive (Exim 4.71) id 1dcwlA-0003Zm-7l for mharc-qemu-arm@gnu.org; Wed, 02 Aug 2017 12:44:36 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:49487) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dcwl8-0003Y1-5R for qemu-arm@nongnu.org; Wed, 02 Aug 2017 12:44:35 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dcwl6-0004jF-Ur for qemu-arm@nongnu.org; Wed, 02 Aug 2017 12:44:34 -0400 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:37764) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1dcwl6-0003zA-Lo; Wed, 02 Aug 2017 12:44:32 -0400 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.84_2) (envelope-from ) id 1dcwkg-0003z0-U7; Wed, 02 Aug 2017 17:44:06 +0100 From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: patches@linaro.org Date: Wed, 2 Aug 2017 17:43:55 +0100 Message-Id: <1501692241-23310-10-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1501692241-23310-1-git-send-email-peter.maydell@linaro.org> References: <1501692241-23310-1-git-send-email-peter.maydell@linaro.org> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-arm] [PATCH 09/15] target/arm: Don't store M profile PRIMASK and FAULTMASK in daif X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 02 Aug 2017 16:44:35 -0000 We currently store the M profile CPU register state PRIMASK and FAULTMASK in the daif field of the CPU state in its I and F bits. This is a legacy from the original implementation, which tried to share the cpu_exec_interrupt code between A profile and M profile. We've since separated out the two cases because they are significantly different, so now there is no common code between M and A profile which looks at env->daif: all the uses are either in A-only or M-only code paths. Sharing the state fields now is just confusing, and will make things awkward when we implement v8M, where the PRIMASK and FAULTMASK registers are banked between security states. Switch M profile over to using v7m.faultmask and v7m.primask fields for these registers. Signed-off-by: Peter Maydell --- hw/intc/armv7m_nvic.c | 4 ++-- target/arm/cpu.c | 5 ----- target/arm/cpu.h | 4 +++- target/arm/helper.c | 18 +++++------------- target/arm/machine.c | 33 +++++++++++++++++++++++++++++++++ 5 files changed, 43 insertions(+), 21 deletions(-) diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c index 2e8166a..343bc16 100644 --- a/hw/intc/armv7m_nvic.c +++ b/hw/intc/armv7m_nvic.c @@ -167,9 +167,9 @@ static inline int nvic_exec_prio(NVICState *s) CPUARMState *env = &s->cpu->env; int running; - if (env->daif & PSTATE_F) { /* FAULTMASK */ + if (env->v7m.faultmask) { running = -1; - } else if (env->daif & PSTATE_I) { /* PRIMASK */ + } else if (env->v7m.primask) { running = 0; } else if (env->v7m.basepri > 0) { running = env->v7m.basepri & nvic_gprio_mask(s); diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 05c038b..b241a63 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -185,11 +185,6 @@ static void arm_cpu_reset(CPUState *s) uint32_t initial_pc; /* Loaded from 0x4 */ uint8_t *rom; - /* For M profile we store FAULTMASK and PRIMASK in the - * PSTATE F and I bits; these are both clear at reset. - */ - env->daif &= ~(PSTATE_I | PSTATE_F); - /* The reset value of this bit is IMPDEF, but ARM recommends * that it resets to 1, so QEMU always does that rather than making * it dependent on CPU model. diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 1f06de0..da90b7a 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -418,6 +418,8 @@ typedef struct CPUARMState { uint32_t bfar; /* BusFault Address */ unsigned mpu_ctrl; /* MPU_CTRL */ int exception; + uint32_t primask; + uint32_t faultmask; } v7m; /* Information associated with an exception about to be taken: @@ -2179,7 +2181,7 @@ static inline int cpu_mmu_index(CPUARMState *env, bool ifetch) * we're in a HardFault or NMI handler. */ if ((env->v7m.exception > 0 && env->v7m.exception <= 3) - || env->daif & PSTATE_F) { + || env->v7m.faultmask) { return arm_to_core_mmu_idx(ARMMMUIdx_MNegPri); } diff --git a/target/arm/helper.c b/target/arm/helper.c index f087d42..b64ddb1 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -6172,7 +6172,7 @@ static void do_v7m_exception_exit(ARMCPU *cpu) if (env->v7m.exception != ARMV7M_EXCP_NMI) { /* Auto-clear FAULTMASK on return from other than NMI */ - env->daif &= ~PSTATE_F; + env->v7m.faultmask = 0; } switch (armv7m_nvic_complete_irq(env->nvic, env->v7m.exception)) { @@ -8718,12 +8718,12 @@ uint32_t HELPER(v7m_mrs)(CPUARMState *env, uint32_t reg) return (env->v7m.control & R_V7M_CONTROL_SPSEL_MASK) ? env->regs[13] : env->v7m.other_sp; case 16: /* PRIMASK */ - return (env->daif & PSTATE_I) != 0; + return env->v7m.primask; case 17: /* BASEPRI */ case 18: /* BASEPRI_MAX */ return env->v7m.basepri; case 19: /* FAULTMASK */ - return (env->daif & PSTATE_F) != 0; + return env->v7m.faultmask; default: qemu_log_mask(LOG_GUEST_ERROR, "Attempt to read unknown special" " register %d\n", reg); @@ -8778,11 +8778,7 @@ void HELPER(v7m_msr)(CPUARMState *env, uint32_t maskreg, uint32_t val) } break; case 16: /* PRIMASK */ - if (val & 1) { - env->daif |= PSTATE_I; - } else { - env->daif &= ~PSTATE_I; - } + env->v7m.primask = val & 1; break; case 17: /* BASEPRI */ env->v7m.basepri = val & 0xff; @@ -8793,11 +8789,7 @@ void HELPER(v7m_msr)(CPUARMState *env, uint32_t maskreg, uint32_t val) env->v7m.basepri = val; break; case 19: /* FAULTMASK */ - if (val & 1) { - env->daif |= PSTATE_F; - } else { - env->daif &= ~PSTATE_F; - } + env->v7m.faultmask = val & 1; break; case 20: /* CONTROL */ /* Writing to the SPSEL bit only has an effect if we are in diff --git a/target/arm/machine.c b/target/arm/machine.c index 1f66da4..2fb4b76 100644 --- a/target/arm/machine.c +++ b/target/arm/machine.c @@ -97,6 +97,17 @@ static bool m_needed(void *opaque) return arm_feature(env, ARM_FEATURE_M); } +static const VMStateDescription vmstate_m_faultmask_primask = { + .name = "cpu/m/faultmask-primask", + .version_id = 1, + .minimum_version_id = 1, + .fields = (VMStateField[]) { + VMSTATE_UINT32(env.v7m.faultmask, ARMCPU), + VMSTATE_UINT32(env.v7m.primask, ARMCPU), + VMSTATE_END_OF_LIST() + } +}; + static const VMStateDescription vmstate_m = { .name = "cpu/m", .version_id = 4, @@ -115,6 +126,10 @@ static const VMStateDescription vmstate_m = { VMSTATE_UINT32(env.v7m.mpu_ctrl, ARMCPU), VMSTATE_INT32(env.v7m.exception, ARMCPU), VMSTATE_END_OF_LIST() + }, + .subsections = (const VMStateDescription*[]) { + &vmstate_m_faultmask_primask, + NULL } }; @@ -201,6 +216,24 @@ static int get_cpsr(QEMUFile *f, void *opaque, size_t size, CPUARMState *env = &cpu->env; uint32_t val = qemu_get_be32(f); + if (arm_feature(env, ARM_FEATURE_M)) { + /* If the I or F bits are set then this is a migration from + * an old QEMU which still stored the M profile FAULTMASK + * and PRIMASK in env->daif. Set v7m.faultmask and v7m.primask + * accordingly, and then clear the bits so they don't confuse + * cpsr_write(). For a new QEMU, the bits here will always be + * clear, and the data is transferred using the + * vmstate_m_faultmask_primask subsection. + */ + if (val & CPSR_F) { + env->v7m.faultmask = 1; + } + if (val & CPSR_I) { + env->v7m.primask = 1; + } + val &= ~(CPSR_F | CPSR_I); + } + env->aarch64 = ((val & PSTATE_nRW) == 0); if (is_a64(env)) { -- 2.7.4 From MAILER-DAEMON Wed Aug 02 12:44:39 2017 Received: from list by lists.gnu.org with archive (Exim 4.71) id 1dcwlC-0003cg-Pn for mharc-qemu-arm@gnu.org; Wed, 02 Aug 2017 12:44:38 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:49535) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dcwlA-0003ZU-4H for qemu-arm@nongnu.org; Wed, 02 Aug 2017 12:44:36 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dcwl9-0004mk-CU for qemu-arm@nongnu.org; Wed, 02 Aug 2017 12:44:36 -0400 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:37764) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1dcwl9-0003zA-6b; Wed, 02 Aug 2017 12:44:35 -0400 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.84_2) (envelope-from ) id 1dcwkf-0003xp-H1; Wed, 02 Aug 2017 17:44:05 +0100 From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: patches@linaro.org Date: Wed, 2 Aug 2017 17:43:52 +0100 Message-Id: <1501692241-23310-7-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1501692241-23310-1-git-send-email-peter.maydell@linaro.org> References: <1501692241-23310-1-git-send-email-peter.maydell@linaro.org> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-arm] [PATCH 06/15] target/arm: Remove incorrect comment about MPU_CTRL X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 02 Aug 2017 16:44:37 -0000 Remove the comment that claims that some MPU_CTRL bits are stored in sctlr_el[1]. This has never been true since MPU_CTRL was added in commit 29c483a50607 -- the comment is a leftover from Michael Davidsaver's original implementation, which I modified not to use sctlr_el[1]; I forgot to delete the comment then. Signed-off-by: Peter Maydell --- target/arm/cpu.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index b39d64a..b64474c 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -416,7 +416,7 @@ typedef struct CPUARMState { uint32_t dfsr; /* Debug Fault Status Register */ uint32_t mmfar; /* MemManage Fault Address */ uint32_t bfar; /* BusFault Address */ - unsigned mpu_ctrl; /* MPU_CTRL (some bits kept in sctlr_el[1]) */ + unsigned mpu_ctrl; /* MPU_CTRL */ int exception; } v7m; -- 2.7.4 From MAILER-DAEMON Wed Aug 02 12:44:42 2017 Received: from list by lists.gnu.org with archive (Exim 4.71) id 1dcwlF-0003gT-Nj for mharc-qemu-arm@gnu.org; Wed, 02 Aug 2017 12:44:41 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:49459) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dcwl7-0003WW-0S for qemu-arm@nongnu.org; Wed, 02 Aug 2017 12:44:34 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dcwl6-0004h4-0T for qemu-arm@nongnu.org; Wed, 02 Aug 2017 12:44:32 -0400 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:37764) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1dcwl5-0003zA-PS; Wed, 02 Aug 2017 12:44:31 -0400 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.84_2) (envelope-from ) id 1dcwkh-0003zO-EN; Wed, 02 Aug 2017 17:44:07 +0100 From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: patches@linaro.org Date: Wed, 2 Aug 2017 17:43:56 +0100 Message-Id: <1501692241-23310-11-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1501692241-23310-1-git-send-email-peter.maydell@linaro.org> References: <1501692241-23310-1-git-send-email-peter.maydell@linaro.org> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-arm] [PATCH 10/15] target/arm: Don't use cpsr_write/cpsr_read to transfer M profile XPSR X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 02 Aug 2017 16:44:34 -0000 For M profile the XPSR is a similar but not identical format to the A profile CPSR/SPSR. (For instance the Thumb bit is in a different place.) For guest accesses we make the M profile code go through xpsr_read() and xpsr_write() which handle the different layout. However for migration we use cpsr_read() and cpsr_write() to marshal state into and out of the migration data stream. This is pretty confusing and works more by luck than anything else. Make M profile migration use xpsr_read() and xpsr_write() instead. The most complicated part of this is handling the possibility that the migration source is an older QEMU which hands us a CPSR format value; helpfully we can always tell the two apart. Signed-off-by: Peter Maydell --- target/arm/machine.c | 49 ++++++++++++++++++++++++++++++++++--------------- 1 file changed, 34 insertions(+), 15 deletions(-) diff --git a/target/arm/machine.c b/target/arm/machine.c index 2fb4b76..3193b00 100644 --- a/target/arm/machine.c +++ b/target/arm/machine.c @@ -217,21 +217,37 @@ static int get_cpsr(QEMUFile *f, void *opaque, size_t size, uint32_t val = qemu_get_be32(f); if (arm_feature(env, ARM_FEATURE_M)) { - /* If the I or F bits are set then this is a migration from - * an old QEMU which still stored the M profile FAULTMASK - * and PRIMASK in env->daif. Set v7m.faultmask and v7m.primask - * accordingly, and then clear the bits so they don't confuse - * cpsr_write(). For a new QEMU, the bits here will always be - * clear, and the data is transferred using the - * vmstate_m_faultmask_primask subsection. - */ - if (val & CPSR_F) { - env->v7m.faultmask = 1; - } - if (val & CPSR_I) { - env->v7m.primask = 1; + if (val & XPSR_EXCP) { + /* This is a CPSR format value from an older QEMU. (We can tell + * because values transferred in XPSR format always have zero + * for the EXCP field, and CPSR format will always have bit 4 + * set in CPSR_M.) Rearrange it into XPSR format. The significant + * differences are that the T bit is not in the same place, the + * primask/faultmask info may be in the CPSR I and F bits, and + * we do not want the mode bits. + */ + uint32_t newval = val; + + newval &= (CPSR_NZCV | CPSR_Q | CPSR_IT | CPSR_GE); + if (val & CPSR_T) { + newval |= XPSR_T; + } + /* If the I or F bits are set then this is a migration from + * an old QEMU which still stored the M profile FAULTMASK + * and PRIMASK in env->daif. For a new QEMU, the data is + * transferred using the vmstate_m_faultmask_primask subsection. + */ + if (val & CPSR_F) { + env->v7m.faultmask = 1; + } + if (val & CPSR_I) { + env->v7m.primask = 1; + } + val = newval; } - val &= ~(CPSR_F | CPSR_I); + /* Ignore the low bits, they are handled by vmstate_m. */ + xpsr_write(env, val, ~XPSR_EXCP); + return 0; } env->aarch64 = ((val & PSTATE_nRW) == 0); @@ -252,7 +268,10 @@ static int put_cpsr(QEMUFile *f, void *opaque, size_t size, CPUARMState *env = &cpu->env; uint32_t val; - if (is_a64(env)) { + if (arm_feature(env, ARM_FEATURE_M)) { + /* The low 9 bits are v7m.exception, which is handled by vmstate_m. */ + val = xpsr_read(env) & ~XPSR_EXCP; + } else if (is_a64(env)) { val = pstate_read(env); } else { val = cpsr_read(env); -- 2.7.4 From MAILER-DAEMON Wed Aug 02 12:44:42 2017 Received: from list by lists.gnu.org with archive (Exim 4.71) id 1dcwlG-0003gm-1i for mharc-qemu-arm@gnu.org; Wed, 02 Aug 2017 12:44:42 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:49516) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dcwl9-0003Yd-8e for qemu-arm@nongnu.org; Wed, 02 Aug 2017 12:44:36 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dcwl8-0004m6-JY for qemu-arm@nongnu.org; Wed, 02 Aug 2017 12:44:35 -0400 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:37764) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1dcwl8-0003zA-CI; Wed, 02 Aug 2017 12:44:34 -0400 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.84_2) (envelope-from ) id 1dcwkf-0003yE-Vq; Wed, 02 Aug 2017 17:44:05 +0100 From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: patches@linaro.org Date: Wed, 2 Aug 2017 17:43:53 +0100 Message-Id: <1501692241-23310-8-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1501692241-23310-1-git-send-email-peter.maydell@linaro.org> References: <1501692241-23310-1-git-send-email-peter.maydell@linaro.org> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-arm] [PATCH 07/15] target/arm: Fix outdated comment about exception exit X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 02 Aug 2017 16:44:36 -0000 When we switched our handling of exception exit to detect the magic addresses at translate time rather than via a do_unassigned_access hook, we forgot to update a comment; correct the omission. Signed-off-by: Peter Maydell --- target/arm/helper.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index fd83a21..cb88c66 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -6143,7 +6143,7 @@ static void do_v7m_exception_exit(ARMCPU *cpu) bool rettobase = false; /* We can only get here from an EXCP_EXCEPTION_EXIT, and - * arm_v7m_do_unassigned_access() enforces the architectural rule + * gen_bx_excret() enforces the architectural rule * that jumps to magic addresses don't have magic behaviour unless * we're in Handler mode (compare pseudocode BXWritePC()). */ -- 2.7.4 From MAILER-DAEMON Wed Aug 02 12:44:42 2017 Received: from list by lists.gnu.org with archive (Exim 4.71) id 1dcwlG-0003hC-8P for mharc-qemu-arm@gnu.org; Wed, 02 Aug 2017 12:44:42 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:49504) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dcwl9-0003YS-1N for qemu-arm@nongnu.org; Wed, 02 Aug 2017 12:44:36 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dcwl7-0004l4-Pe for qemu-arm@nongnu.org; Wed, 02 Aug 2017 12:44:34 -0400 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:37764) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1dcwl7-0003zA-HB; Wed, 02 Aug 2017 12:44:33 -0400 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.84_2) (envelope-from ) id 1dcwkg-0003yc-Do; Wed, 02 Aug 2017 17:44:06 +0100 From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: patches@linaro.org Date: Wed, 2 Aug 2017 17:43:54 +0100 Message-Id: <1501692241-23310-9-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1501692241-23310-1-git-send-email-peter.maydell@linaro.org> References: <1501692241-23310-1-git-send-email-peter.maydell@linaro.org> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-arm] [PATCH 08/15] target/arm: Define and use XPSR bit masks X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 02 Aug 2017 16:44:36 -0000 The M profile XPSR is almost the same format as the A profile CPSR, but not quite. Define some XPSR_* macros and use them where we definitely dealing with an XPSR rather than reusing the CPSR ones. Signed-off-by: Peter Maydell --- target/arm/cpu.h | 38 ++++++++++++++++++++++++++++---------- target/arm/helper.c | 15 ++++++++------- 2 files changed, 36 insertions(+), 17 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index b64474c..1f06de0 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -883,6 +883,22 @@ void pmccntr_sync(CPUARMState *env); /* Mask of bits which may be set by exception return copying them from SPSR */ #define CPSR_ERET_MASK (~CPSR_RESERVED) +/* Bit definitions for M profile XPSR. Most are the same as CPSR. */ +#define XPSR_EXCP 0x1ffU +#define XPSR_SPREALIGN (1U << 9) /* Only set in exception stack frames */ +#define XPSR_IT_2_7 CPSR_IT_2_7 +#define XPSR_GE CPSR_GE +#define XPSR_SFPA (1U << 20) /* Only set in exception stack frames */ +#define XPSR_T (1U << 24) /* Not the same as CPSR_T ! */ +#define XPSR_IT_0_1 CPSR_IT_0_1 +#define XPSR_Q CPSR_Q +#define XPSR_V CPSR_V +#define XPSR_C CPSR_C +#define XPSR_Z CPSR_Z +#define XPSR_N CPSR_N +#define XPSR_NZCV CPSR_NZCV +#define XPSR_IT CPSR_IT + #define TTBCR_N (7U << 0) /* TTBCR.EAE==0 */ #define TTBCR_T0SZ (7U << 0) /* TTBCR.EAE==1 */ #define TTBCR_PD0 (1U << 4) @@ -987,26 +1003,28 @@ static inline uint32_t xpsr_read(CPUARMState *env) /* Set the xPSR. Note that some bits of mask must be all-set or all-clear. */ static inline void xpsr_write(CPUARMState *env, uint32_t val, uint32_t mask) { - if (mask & CPSR_NZCV) { - env->ZF = (~val) & CPSR_Z; + if (mask & XPSR_NZCV) { + env->ZF = (~val) & XPSR_Z; env->NF = val; env->CF = (val >> 29) & 1; env->VF = (val << 3) & 0x80000000; } - if (mask & CPSR_Q) - env->QF = ((val & CPSR_Q) != 0); - if (mask & (1 << 24)) - env->thumb = ((val & (1 << 24)) != 0); - if (mask & CPSR_IT_0_1) { + if (mask & XPSR_Q) { + env->QF = ((val & XPSR_Q) != 0); + } + if (mask & XPSR_T) { + env->thumb = ((val & XPSR_T) != 0); + } + if (mask & XPSR_IT_0_1) { env->condexec_bits &= ~3; env->condexec_bits |= (val >> 25) & 3; } - if (mask & CPSR_IT_2_7) { + if (mask & XPSR_IT_2_7) { env->condexec_bits &= 3; env->condexec_bits |= (val >> 8) & 0xfc; } - if (mask & 0x1ff) { - env->v7m.exception = val & 0x1ff; + if (mask & XPSR_EXCP) { + env->v7m.exception = val & XPSR_EXCP; } } diff --git a/target/arm/helper.c b/target/arm/helper.c index cb88c66..f087d42 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -6119,7 +6119,7 @@ static void v7m_push_stack(ARMCPU *cpu) /* Align stack pointer if the guest wants that */ if ((env->regs[13] & 4) && (env->v7m.ccr & R_V7M_CCR_STKALIGN_MASK)) { env->regs[13] -= 4; - xpsr |= 0x200; + xpsr |= XPSR_SPREALIGN; } /* Switch to the handler mode. */ v7m_push(env, xpsr); @@ -6244,10 +6244,11 @@ static void do_v7m_exception_exit(ARMCPU *cpu) env->regs[15] &= ~1U; } xpsr = v7m_pop(env); - xpsr_write(env, xpsr, 0xfffffdff); + xpsr_write(env, xpsr, ~XPSR_SPREALIGN); /* Undo stack alignment. */ - if (xpsr & 0x200) + if (xpsr & XPSR_SPREALIGN) { env->regs[13] |= 4; + } /* The restored xPSR exception field will be zero if we're * resuming in Thread mode. If that doesn't match what the @@ -8693,10 +8694,10 @@ uint32_t HELPER(v7m_mrs)(CPUARMState *env, uint32_t reg) case 0 ... 7: /* xPSR sub-fields */ mask = 0; if ((reg & 1) && el) { - mask |= 0x000001ff; /* IPSR (unpriv. reads as zero) */ + mask |= XPSR_EXCP; /* IPSR (unpriv. reads as zero) */ } if (!(reg & 4)) { - mask |= 0xf8000000; /* APSR */ + mask |= XPSR_NZCV | XPSR_Q; /* APSR */ } /* EPSR reads as zero */ return xpsr_read(env) & mask; @@ -8754,10 +8755,10 @@ void HELPER(v7m_msr)(CPUARMState *env, uint32_t maskreg, uint32_t val) uint32_t apsrmask = 0; if (mask & 8) { - apsrmask |= 0xf8000000; /* APSR NZCVQ */ + apsrmask |= XPSR_NZCV | XPSR_Q; } if ((mask & 4) && arm_feature(env, ARM_FEATURE_THUMB_DSP)) { - apsrmask |= 0x000f0000; /* APSR GE[3:0] */ + apsrmask |= XPSR_GE; } xpsr_write(env, val, apsrmask); } -- 2.7.4 From MAILER-DAEMON Wed Aug 02 12:44:43 2017 Received: from list by lists.gnu.org with archive (Exim 4.71) id 1dcwlG-0003i6-Ps for mharc-qemu-arm@gnu.org; Wed, 02 Aug 2017 12:44:42 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:49563) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dcwlA-0003al-Ut for qemu-arm@nongnu.org; Wed, 02 Aug 2017 12:44:37 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dcwlA-0004nJ-7Z for qemu-arm@nongnu.org; Wed, 02 Aug 2017 12:44:36 -0400 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:37764) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1dcwlA-0003zA-0F; Wed, 02 Aug 2017 12:44:36 -0400 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.84_2) (envelope-from ) id 1dcwkf-0003xR-14; Wed, 02 Aug 2017 17:44:05 +0100 From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: patches@linaro.org Date: Wed, 2 Aug 2017 17:43:51 +0100 Message-Id: <1501692241-23310-6-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1501692241-23310-1-git-send-email-peter.maydell@linaro.org> References: <1501692241-23310-1-git-send-email-peter.maydell@linaro.org> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-arm] [PATCH 05/15] hw/intc/armv7m_nvic.c: Remove out of date comment X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 02 Aug 2017 16:44:38 -0000 Remove an out of date comment which says there's only one item in the NVIC container region -- we put systick into its own device object a while back and so now there are two things in the container. Signed-off-by: Peter Maydell --- hw/intc/armv7m_nvic.c | 4 ---- 1 file changed, 4 deletions(-) diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c index 323e2d4..2e8166a 100644 --- a/hw/intc/armv7m_nvic.c +++ b/hw/intc/armv7m_nvic.c @@ -1036,10 +1036,6 @@ static void armv7m_nvic_realize(DeviceState *dev, Error **errp) * 0xd00..0xd3c - SCS registers * 0xd40..0xeff - Reserved or Not implemented * 0xf00 - STIR - * - * At the moment there is only one thing in the container region, - * but we leave it in place to allow us to pull systick out into - * its own device object later. */ memory_region_init(&s->container, OBJECT(s), "nvic", 0x1000); /* The system register region goes at the bottom of the priority -- 2.7.4 From MAILER-DAEMON Wed Aug 02 12:44:44 2017 Received: from list by lists.gnu.org with archive (Exim 4.71) id 1dcwlH-0003jS-RM for mharc-qemu-arm@gnu.org; Wed, 02 Aug 2017 12:44:43 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:49605) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dcwlC-0003c6-90 for qemu-arm@nongnu.org; Wed, 02 Aug 2017 12:44:39 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dcwlB-0004o1-1j for qemu-arm@nongnu.org; Wed, 02 Aug 2017 12:44:38 -0400 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:37764) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1dcwlA-0003zA-QY; Wed, 02 Aug 2017 12:44:36 -0400 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.84_2) (envelope-from ) id 1dcwke-0003x6-Ho; Wed, 02 Aug 2017 17:44:04 +0100 From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: patches@linaro.org Date: Wed, 2 Aug 2017 17:43:50 +0100 Message-Id: <1501692241-23310-5-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1501692241-23310-1-git-send-email-peter.maydell@linaro.org> References: <1501692241-23310-1-git-send-email-peter.maydell@linaro.org> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-arm] [PATCH 04/15] target/arm: Tighten up Thumb decode where new v8M insns will be X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 02 Aug 2017 16:44:39 -0000 Tighten up the T32 decoder in the places where new v8M instructions will be: * TT/TTT/TTA/TTAT are in what was nominally LDREX/STREX r15, ... which is UNPREDICTABLE: make the UNPREDICTABLE behaviour be to UNDEF * BXNS/BLXNS are distinguished from BX/BLX via the low 3 bits, which in previous architectural versions are SBZ: enforce the SBZ via UNDEF rather than ignoring it, and move the "ARCH(5)" UNDEF case up so we don't leak a TCG temporary * SG is in the encoding which would be LDRD/STRD with rn = r15; this is UNPREDICTABLE and we currently UNDEF: move this check further up the code so that we don't leak TCG temporaries in the UNDEF case and have a better place to put the SG decode. This means that if a v8M binary is accidentally run on v7M or if a test case hits something that we haven't implemented yet the behaviour will be obvious (UNDEF) rather than obscure (plough on treating it as a different instruction). In the process, add some comments about the instruction patterns at these points in the decode. Our Thumb and ARM decoders are very difficult to understand currently, but gradually adding comments like this should help to clarify what exactly has been decoded when. Signed-off-by: Peter Maydell --- target/arm/translate.c | 48 +++++++++++++++++++++++++++++++++++++++--------- 1 file changed, 39 insertions(+), 9 deletions(-) diff --git a/target/arm/translate.c b/target/arm/translate.c index d1a5f56..3c14cb0 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -9735,10 +9735,23 @@ static int disas_thumb2_insn(CPUARMState *env, DisasContext *s, uint16_t insn_hw abort(); case 4: if (insn & (1 << 22)) { - /* Other load/store, table branch. */ + /* 0b1110_100x_x1xx_xxxx_xxxx_xxxx_xxxx_xxxx + * - load/store doubleword, load/store exclusive, ldacq/strel, + * table branch. + */ if (insn & 0x01200000) { - /* Load/store doubleword. */ + /* 0b1110_1000_x11x_xxxx_xxxx_xxxx_xxxx_xxxx + * - load/store dual (post-indexed) + * 0b1111_1001_x10x_xxxx_xxxx_xxxx_xxxx_xxxx + * - load/store dual (literal and immediate) + * 0b1111_1001_x11x_xxxx_xxxx_xxxx_xxxx_xxxx + * - load/store dual (pre-indexed) + */ if (rn == 15) { + if (insn & (1 << 21)) { + /* UNPREDICTABLE */ + goto illegal_op; + } addr = tcg_temp_new_i32(); tcg_gen_movi_i32(addr, s->pc & ~3); } else { @@ -9772,15 +9785,18 @@ static int disas_thumb2_insn(CPUARMState *env, DisasContext *s, uint16_t insn_hw } if (insn & (1 << 21)) { /* Base writeback. */ - if (rn == 15) - goto illegal_op; tcg_gen_addi_i32(addr, addr, offset - 4); store_reg(s, rn, addr); } else { tcg_temp_free_i32(addr); } } else if ((insn & (1 << 23)) == 0) { - /* Load/store exclusive word. */ + /* 0b1110_1000_010x_xxxx_xxxx_xxxx_xxxx_xxxx + * - load/store exclusive word + */ + if (rs == 15) { + goto illegal_op; + } addr = tcg_temp_local_new_i32(); load_reg_var(s, addr, rn); tcg_gen_addi_i32(addr, addr, (insn & 0xff) << 2); @@ -11137,7 +11153,9 @@ static void disas_thumb_insn(CPUARMState *env, DisasContext *s) break; } if (insn & (1 << 10)) { - /* data processing extended or blx */ + /* 0b0100_01xx_xxxx_xxxx + * - data processing extended, branch and exchange + */ rd = (insn & 7) | ((insn >> 4) & 8); rm = (insn >> 3) & 0xf; op = (insn >> 8) & 3; @@ -11160,10 +11178,21 @@ static void disas_thumb_insn(CPUARMState *env, DisasContext *s) tmp = load_reg(s, rm); store_reg(s, rd, tmp); break; - case 3:/* branch [and link] exchange thumb register */ - tmp = load_reg(s, rm); - if (insn & (1 << 7)) { + case 3: + { + /* 0b0100_0111_xxxx_xxxx + * - branch [and link] exchange thumb register + */ + bool link = insn & (1 << 7); + + if (insn & 7) { + goto undef; + } + if (link) { ARCH(5); + } + tmp = load_reg(s, rm); + if (link) { val = (uint32_t)s->pc | 1; tmp2 = tcg_temp_new_i32(); tcg_gen_movi_i32(tmp2, val); @@ -11175,6 +11204,7 @@ static void disas_thumb_insn(CPUARMState *env, DisasContext *s) } break; } + } break; } -- 2.7.4 From MAILER-DAEMON Wed Aug 02 12:44:44 2017 Received: from list by lists.gnu.org with archive (Exim 4.71) id 1dcwlI-0003jj-1N for mharc-qemu-arm@gnu.org; Wed, 02 Aug 2017 12:44:44 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:49620) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dcwlC-0003cd-P3 for qemu-arm@nongnu.org; Wed, 02 Aug 2017 12:44:39 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dcwlB-0004od-So for qemu-arm@nongnu.org; Wed, 02 Aug 2017 12:44:38 -0400 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:37764) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1dcwlB-0003zA-Ka; Wed, 02 Aug 2017 12:44:37 -0400 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.84_2) (envelope-from ) id 1dcwkd-0003wq-SX; Wed, 02 Aug 2017 17:44:03 +0100 From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: patches@linaro.org Date: Wed, 2 Aug 2017 17:43:49 +0100 Message-Id: <1501692241-23310-4-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1501692241-23310-1-git-send-email-peter.maydell@linaro.org> References: <1501692241-23310-1-git-send-email-peter.maydell@linaro.org> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-arm] [PATCH 03/15] target/arm: Consolidate PMSA handling in get_phys_addr() X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 02 Aug 2017 16:44:39 -0000 Currently get_phys_addr() has PMSAv7 handling before the "is translation disabled?" check, and then PMSAv5 after it. Tidy this up by making the PMSAv5 code handle the "MPU disabled" case itself, so that we have all the PMSA code in one place. This will make adding the PMSAv8 code slightly cleaner, and also means that pre-v7 PMSA cores benefit from the MPU lookup logging that the PMSAv7 codepath had. Signed-off-by: Peter Maydell --- target/arm/helper.c | 38 ++++++++++++++++++++++---------------- 1 file changed, 22 insertions(+), 16 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index b78d277..fd83a21 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -8423,6 +8423,13 @@ static bool get_phys_addr_pmsav5(CPUARMState *env, uint32_t address, uint32_t base; bool is_user = regime_is_user(env, mmu_idx); + if (regime_translation_disabled(env, mmu_idx)) { + /* MPU disabled. */ + *phys_ptr = address; + *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC; + return false; + } + *phys_ptr = address; for (n = 7; n >= 0; n--) { base = env->cp15.c6_region[n]; @@ -8572,16 +8579,20 @@ static bool get_phys_addr(CPUARMState *env, target_ulong address, } } - /* pmsav7 has special handling for when MPU is disabled so call it before - * the common MMU/MPU disabled check below. - */ - if (arm_feature(env, ARM_FEATURE_PMSA) && - arm_feature(env, ARM_FEATURE_V7)) { + if (arm_feature(env, ARM_FEATURE_PMSA)) { bool ret; *page_size = TARGET_PAGE_SIZE; - ret = get_phys_addr_pmsav7(env, address, access_type, mmu_idx, - phys_ptr, prot, fsr); - qemu_log_mask(CPU_LOG_MMU, "PMSAv7 MPU lookup for %s at 0x%08" PRIx32 + + if (arm_feature(env, ARM_FEATURE_V7)) { + /* PMSAv7 */ + ret = get_phys_addr_pmsav7(env, address, access_type, mmu_idx, + phys_ptr, prot, fsr); + } else { + /* Pre-v7 MPU */ + ret = get_phys_addr_pmsav5(env, address, access_type, mmu_idx, + phys_ptr, prot, fsr); + } + qemu_log_mask(CPU_LOG_MMU, "PMSA MPU lookup for %s at 0x%08" PRIx32 " mmu_idx %u -> %s (prot %c%c%c)\n", access_type == MMU_DATA_LOAD ? "reading" : (access_type == MMU_DATA_STORE ? "writing" : "execute"), @@ -8594,21 +8605,16 @@ static bool get_phys_addr(CPUARMState *env, target_ulong address, return ret; } + /* Definitely a real MMU, not an MPU */ + if (regime_translation_disabled(env, mmu_idx)) { - /* MMU/MPU disabled. */ + /* MMU disabled. */ *phys_ptr = address; *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC; *page_size = TARGET_PAGE_SIZE; return 0; } - if (arm_feature(env, ARM_FEATURE_PMSA)) { - /* Pre-v7 MPU */ - *page_size = TARGET_PAGE_SIZE; - return get_phys_addr_pmsav5(env, address, access_type, mmu_idx, - phys_ptr, prot, fsr); - } - if (regime_using_lpae_format(env, mmu_idx)) { return get_phys_addr_lpae(env, address, access_type, mmu_idx, phys_ptr, attrs, prot, page_size, fsr, fi); -- 2.7.4 From MAILER-DAEMON Wed Aug 02 12:44:45 2017 Received: from list by lists.gnu.org with archive (Exim 4.71) id 1dcwlJ-0003lW-81 for mharc-qemu-arm@gnu.org; Wed, 02 Aug 2017 12:44:45 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:49639) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dcwlD-0003dT-Es for qemu-arm@nongnu.org; Wed, 02 Aug 2017 12:44:40 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dcwlC-0004qG-M9 for qemu-arm@nongnu.org; Wed, 02 Aug 2017 12:44:39 -0400 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:37764) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1dcwlC-0003zA-Fm; Wed, 02 Aug 2017 12:44:38 -0400 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.84_2) (envelope-from ) id 1dcwkd-0003wR-EG; Wed, 02 Aug 2017 17:44:03 +0100 From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: patches@linaro.org Date: Wed, 2 Aug 2017 17:43:48 +0100 Message-Id: <1501692241-23310-3-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1501692241-23310-1-git-send-email-peter.maydell@linaro.org> References: <1501692241-23310-1-git-send-email-peter.maydell@linaro.org> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-arm] [PATCH 02/15] target/arm: Don't trap WFI/WFE for M profile X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 02 Aug 2017 16:44:40 -0000 M profile cores can never trap on WFI or WFE instructions. Check for M profile in check_wfx_trap() to ensure this. The existing code will do the right thing for v7M cores because the hcr_el2 and scr_el3 registers will be all-zeroes and so we won't attempt to trap, but when we start setting ARM_FEATURE_V8 for v8M cores the v8A handling of SCTLR.nTWE and .nTWI will not give the right results. Signed-off-by: Peter Maydell --- target/arm/op_helper.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/target/arm/op_helper.c b/target/arm/op_helper.c index 2a85666..5a94a5f 100644 --- a/target/arm/op_helper.c +++ b/target/arm/op_helper.c @@ -370,6 +370,11 @@ static inline int check_wfx_trap(CPUARMState *env, bool is_wfe) int cur_el = arm_current_el(env); uint64_t mask; + if (arm_feature(env, ARM_FEATURE_M)) { + /* M profile cores can never trap WFI/WFE. */ + return 0; + } + /* If we are currently in EL0 then we need to check if SCTLR is set up for * WFx instructions being trapped to EL1. These trap bits don't exist in v7. */ -- 2.7.4 From MAILER-DAEMON Wed Aug 02 12:44:48 2017 Received: from list by lists.gnu.org with archive (Exim 4.71) id 1dcwlL-0003o0-Rs for mharc-qemu-arm@gnu.org; Wed, 02 Aug 2017 12:44:47 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:49661) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dcwlE-0003ei-Ee for qemu-arm@nongnu.org; Wed, 02 Aug 2017 12:44:41 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dcwlD-0004ru-HH for qemu-arm@nongnu.org; Wed, 02 Aug 2017 12:44:40 -0400 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:37764) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1dcwlD-0003zA-9M; Wed, 02 Aug 2017 12:44:39 -0400 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.84_2) (envelope-from ) id 1dcwkc-0003w1-Bt; Wed, 02 Aug 2017 17:44:02 +0100 From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: patches@linaro.org Date: Wed, 2 Aug 2017 17:43:46 +0100 Message-Id: <1501692241-23310-1-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 2.7.4 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-arm] [PATCH 00/15] v7M: cleanups and bugfixes prior to v8M X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 02 Aug 2017 16:44:41 -0000 (This is 2.11 material, obviously, but it's a coherent and large enough set of patches that I figured I might as well push it out for review now.) This patchset is a collection of cleanups, bugfixes, etc to the existing v7M code which are either necessary preliminary to implementing v8M or just things I noticed along the way. The non-trivial stuff is: * migration for M profile is shifted to not use read_cpsr() and write_cpsr() which assume A profile semantics (back compatibility with old migration state is maintained) * we implement the "user accesses should BusFault" behaviour for the memory mapped registers in the SCS, though this won't actually kick in until we turn MEMTX_ERROR into a BusFault (I have patches for that) thanks -- PMM Peter Maydell (15): target/arm: Use MMUAccessType enum rather than int target/arm: Don't trap WFI/WFE for M profile target/arm: Consolidate PMSA handling in get_phys_addr() target/arm: Tighten up Thumb decode where new v8M insns will be hw/intc/armv7m_nvic.c: Remove out of date comment target/arm: Remove incorrect comment about MPU_CTRL target/arm: Fix outdated comment about exception exit target/arm: Define and use XPSR bit masks target/arm: Don't store M profile PRIMASK and FAULTMASK in daif target/arm: Don't use cpsr_write/cpsr_read to transfer M profile XPSR target/arm: Make arm_cpu_dump_state() handle the M-profile XPSR target/arm: Don't calculate lr in arm_v7m_cpu_do_interrupt() until needed target/arm: Create and use new function arm_v7m_is_handler_mode() armv7m_nvic.h: Move from include/hw/arm to include/hw/intc nvic: Implement "user accesses BusFault" SCS region behaviour hw/intc/armv7m_nvic.c | 68 +++++++++++------- include/hw/arm/armv7m.h | 2 +- include/hw/{arm => intc}/armv7m_nvic.h | 0 target/arm/cpu.c | 5 -- target/arm/cpu.h | 54 ++++++++++---- target/arm/helper.c | 124 ++++++++++++++++----------------- target/arm/internals.h | 3 +- target/arm/machine.c | 54 +++++++++++++- target/arm/op_helper.c | 5 ++ target/arm/translate.c | 106 +++++++++++++++++++++------- 10 files changed, 286 insertions(+), 135 deletions(-) rename include/hw/{arm => intc}/armv7m_nvic.h (100%) -- 2.7.4 From MAILER-DAEMON Wed Aug 02 13:27:16 2017 Received: from list by lists.gnu.org with archive (Exim 4.71) id 1dcxQS-0004pe-IR for mharc-qemu-arm@gnu.org; Wed, 02 Aug 2017 13:27:16 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:36911) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dcxQQ-0004oZ-GX for qemu-arm@nongnu.org; Wed, 02 Aug 2017 13:27:15 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dcxQM-0000kE-GD for qemu-arm@nongnu.org; Wed, 02 Aug 2017 13:27:14 -0400 Received: from mail-lf0-x244.google.com ([2a00:1450:4010:c07::244]:38336) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1dcxQM-0000gu-4E; Wed, 02 Aug 2017 13:27:10 -0400 Received: by mail-lf0-x244.google.com with SMTP id y15so4179429lfd.5; Wed, 02 Aug 2017 10:27:08 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=date:from:to:cc:subject:message-id:references:mime-version :content-disposition:in-reply-to:user-agent; bh=CSxRkAWBnoJnEdDqBNplkkRVjaqbDpKrNabk5QDXD98=; b=q926By+wz+hJpDf4Q5x8Yba+H/mJdFn0Qy9YUbvD6khWj9+YsAtBoTkdHeYTGi6RZT 2yiBKDIhyT08hZ8Ix88Q+cpeH1D2HFQKTBuWUsRmMiP/xfItDg2K2VrKEBz0XwTka5eT 1aBpJtMKaMj8M9bmUzkmjgKq6nDdvb7Tw18HmN2n697tU9N+SSUlrv590Kgm3N/rGxl1 T0kH1+2IECBN6MRRQn4b/4ZUlg9t6Fj3buVcS1xzKj9if8+H6mp0hhWIlLnp4Ql3Eu6b f/BX8V4Gviprt3d+FQI4MHDsVmya0zcX03zM3RpRFggw3nEaId2ghCEmq0Re0aoVm4Ee IfZg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:in-reply-to:user-agent; bh=CSxRkAWBnoJnEdDqBNplkkRVjaqbDpKrNabk5QDXD98=; b=WYQXUpB67yRsX1FVxYwYuz9J9MY8onps0Rnqm/tbvZ4ieVlK9yC2iTFJrNUsc6rH6K xzlI1HfbrNnNLnbicSK63I5ZH+sLjqV2KsPIfM0rta6VsMpYPAaAxLBrlxDAafjHcdHD BUBVqUpBqFlYMf76eg7pHzkZ9EyxLbJIfAF5siHoWj/xxVkOYER+FWoXneF94z1rJBYv Ukv1rKBlnYfS6pFjQHdy90D2btEGBPNjt9clRobxv0wnASmX27p0hrNe6RVqcPxt4E1o JpKOuPiiA5LxQaHywP+DzVF+igzntLv4UziVuyH27E843+xbX6NLAQUIj1hjo5bBP4Ya pA4w== X-Gm-Message-State: AIVw110aK1Om5llW7sOhbq5bDBO86icWnPVKFr/Gxr9BFP8UM6DY4GPD 6fcgV130vZ3PBw== X-Received: by 10.46.20.22 with SMTP id u22mr5048005ljd.58.1501694826830; Wed, 02 Aug 2017 10:27:06 -0700 (PDT) Received: from gmail.com (81-231-233-234-no56.tbcn.telia.com. [81.231.233.234]) by smtp.gmail.com with ESMTPSA id m124sm6319027lfg.5.2017.08.02.10.27.05 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 02 Aug 2017 10:27:05 -0700 (PDT) Date: Wed, 2 Aug 2017 19:27:05 +0200 From: "Edgar E. Iglesias" To: Peter Maydell Cc: qemu-arm@nongnu.org, qemu-devel@nongnu.org, patches@linaro.org Message-ID: <20170802172705.GG4859@toto> References: <1501692241-23310-1-git-send-email-peter.maydell@linaro.org> <1501692241-23310-2-git-send-email-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1501692241-23310-2-git-send-email-peter.maydell@linaro.org> User-Agent: Mutt/1.5.24 (2015-08-30) X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4010:c07::244 Subject: Re: [Qemu-arm] [PATCH 01/15] target/arm: Use MMUAccessType enum rather than int X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 02 Aug 2017 17:27:16 -0000 On Wed, Aug 02, 2017 at 05:43:47PM +0100, Peter Maydell wrote: > In the ARM get_phys_addr() code, switch to using the MMUAccessType > enum and its MMU_* values rather than int and literal 0/1/2. > > Signed-off-by: Peter Maydell Reviewed-by: Edgar E. Iglesias > --- > target/arm/helper.c | 30 +++++++++++++++--------------- > target/arm/internals.h | 3 ++- > 2 files changed, 17 insertions(+), 16 deletions(-) > > diff --git a/target/arm/helper.c b/target/arm/helper.c > index fa60040..b78d277 100644 > --- a/target/arm/helper.c > +++ b/target/arm/helper.c > @@ -20,13 +20,13 @@ > > #ifndef CONFIG_USER_ONLY > static bool get_phys_addr(CPUARMState *env, target_ulong address, > - int access_type, ARMMMUIdx mmu_idx, > + MMUAccessType access_type, ARMMMUIdx mmu_idx, > hwaddr *phys_ptr, MemTxAttrs *attrs, int *prot, > target_ulong *page_size, uint32_t *fsr, > ARMMMUFaultInfo *fi); > > static bool get_phys_addr_lpae(CPUARMState *env, target_ulong address, > - int access_type, ARMMMUIdx mmu_idx, > + MMUAccessType access_type, ARMMMUIdx mmu_idx, > hwaddr *phys_ptr, MemTxAttrs *txattrs, int *prot, > target_ulong *page_size_ptr, uint32_t *fsr, > ARMMMUFaultInfo *fi); > @@ -2135,7 +2135,7 @@ static CPAccessResult ats_access(CPUARMState *env, const ARMCPRegInfo *ri, > } > > static uint64_t do_ats_write(CPUARMState *env, uint64_t value, > - int access_type, ARMMMUIdx mmu_idx) > + MMUAccessType access_type, ARMMMUIdx mmu_idx) > { > hwaddr phys_addr; > target_ulong page_size; > @@ -2194,7 +2194,7 @@ static uint64_t do_ats_write(CPUARMState *env, uint64_t value, > > static void ats_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) > { > - int access_type = ri->opc2 & 1; > + MMUAccessType access_type = ri->opc2 & 1 ? MMU_DATA_STORE : MMU_DATA_LOAD; > uint64_t par64; > ARMMMUIdx mmu_idx; > int el = arm_current_el(env); > @@ -2253,7 +2253,7 @@ static void ats_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) > static void ats1h_write(CPUARMState *env, const ARMCPRegInfo *ri, > uint64_t value) > { > - int access_type = ri->opc2 & 1; > + MMUAccessType access_type = ri->opc2 & 1 ? MMU_DATA_STORE : MMU_DATA_LOAD; > uint64_t par64; > > par64 = do_ats_write(env, value, access_type, ARMMMUIdx_S2NS); > @@ -2273,7 +2273,7 @@ static CPAccessResult at_s1e2_access(CPUARMState *env, const ARMCPRegInfo *ri, > static void ats_write64(CPUARMState *env, const ARMCPRegInfo *ri, > uint64_t value) > { > - int access_type = ri->opc2 & 1; > + MMUAccessType access_type = ri->opc2 & 1 ? MMU_DATA_STORE : MMU_DATA_LOAD; > ARMMMUIdx mmu_idx; > int secure = arm_is_secure_below_el3(env); > > @@ -7510,7 +7510,7 @@ static uint64_t arm_ldq_ptw(CPUState *cs, hwaddr addr, bool is_secure, > } > > static bool get_phys_addr_v5(CPUARMState *env, uint32_t address, > - int access_type, ARMMMUIdx mmu_idx, > + MMUAccessType access_type, ARMMMUIdx mmu_idx, > hwaddr *phys_ptr, int *prot, > target_ulong *page_size, uint32_t *fsr, > ARMMMUFaultInfo *fi) > @@ -7626,7 +7626,7 @@ do_fault: > } > > static bool get_phys_addr_v6(CPUARMState *env, uint32_t address, > - int access_type, ARMMMUIdx mmu_idx, > + MMUAccessType access_type, ARMMMUIdx mmu_idx, > hwaddr *phys_ptr, MemTxAttrs *attrs, int *prot, > target_ulong *page_size, uint32_t *fsr, > ARMMMUFaultInfo *fi) > @@ -7733,7 +7733,7 @@ static bool get_phys_addr_v6(CPUARMState *env, uint32_t address, > if (pxn && !regime_is_user(env, mmu_idx)) { > xn = 1; > } > - if (xn && access_type == 2) > + if (xn && access_type == MMU_INST_FETCH) > goto do_fault; > > if (arm_feature(env, ARM_FEATURE_V6K) && > @@ -7848,7 +7848,7 @@ static bool check_s2_mmu_setup(ARMCPU *cpu, bool is_aa64, int level, > } > > static bool get_phys_addr_lpae(CPUARMState *env, target_ulong address, > - int access_type, ARMMMUIdx mmu_idx, > + MMUAccessType access_type, ARMMMUIdx mmu_idx, > hwaddr *phys_ptr, MemTxAttrs *txattrs, int *prot, > target_ulong *page_size_ptr, uint32_t *fsr, > ARMMMUFaultInfo *fi) > @@ -8256,7 +8256,7 @@ static inline bool m_is_system_region(CPUARMState *env, uint32_t address) > } > > static bool get_phys_addr_pmsav7(CPUARMState *env, uint32_t address, > - int access_type, ARMMMUIdx mmu_idx, > + MMUAccessType access_type, ARMMMUIdx mmu_idx, > hwaddr *phys_ptr, int *prot, uint32_t *fsr) > { > ARMCPU *cpu = arm_env_get_cpu(env); > @@ -8415,7 +8415,7 @@ static bool get_phys_addr_pmsav7(CPUARMState *env, uint32_t address, > } > > static bool get_phys_addr_pmsav5(CPUARMState *env, uint32_t address, > - int access_type, ARMMMUIdx mmu_idx, > + MMUAccessType access_type, ARMMMUIdx mmu_idx, > hwaddr *phys_ptr, int *prot, uint32_t *fsr) > { > int n; > @@ -8442,7 +8442,7 @@ static bool get_phys_addr_pmsav5(CPUARMState *env, uint32_t address, > return true; > } > > - if (access_type == 2) { > + if (access_type == MMU_INST_FETCH) { > mask = env->cp15.pmsav5_insn_ap; > } else { > mask = env->cp15.pmsav5_data_ap; > @@ -8513,7 +8513,7 @@ static bool get_phys_addr_pmsav5(CPUARMState *env, uint32_t address, > * @fsr: set to the DFSR/IFSR value on failure > */ > static bool get_phys_addr(CPUARMState *env, target_ulong address, > - int access_type, ARMMMUIdx mmu_idx, > + MMUAccessType access_type, ARMMMUIdx mmu_idx, > hwaddr *phys_ptr, MemTxAttrs *attrs, int *prot, > target_ulong *page_size, uint32_t *fsr, > ARMMMUFaultInfo *fi) > @@ -8626,7 +8626,7 @@ static bool get_phys_addr(CPUARMState *env, target_ulong address, > * fsr with ARM DFSR/IFSR fault register format value on failure. > */ > bool arm_tlb_fill(CPUState *cs, vaddr address, > - int access_type, int mmu_idx, uint32_t *fsr, > + MMUAccessType access_type, int mmu_idx, uint32_t *fsr, > ARMMMUFaultInfo *fi) > { > ARMCPU *cpu = ARM_CPU(cs); > diff --git a/target/arm/internals.h b/target/arm/internals.h > index 1f6efef..bb06946 100644 > --- a/target/arm/internals.h > +++ b/target/arm/internals.h > @@ -457,7 +457,8 @@ struct ARMMMUFaultInfo { > }; > > /* Do a page table walk and add page to TLB if possible */ > -bool arm_tlb_fill(CPUState *cpu, vaddr address, int rw, int mmu_idx, > +bool arm_tlb_fill(CPUState *cpu, vaddr address, > + MMUAccessType access_type, int mmu_idx, > uint32_t *fsr, ARMMMUFaultInfo *fi); > > /* Return true if the stage 1 translation regime is using LPAE format page > -- > 2.7.4 > > From MAILER-DAEMON Wed Aug 02 13:34:21 2017 Received: from list by lists.gnu.org with archive (Exim 4.71) id 1dcxXJ-0000Dv-L0 for mharc-qemu-arm@gnu.org; Wed, 02 Aug 2017 13:34:21 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:43285) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dcxXH-0000By-1q for qemu-arm@nongnu.org; Wed, 02 Aug 2017 13:34:20 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dcxXD-0005Nk-4k for qemu-arm@nongnu.org; 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[81.231.233.234]) by smtp.gmail.com with ESMTPSA id b125sm4237545lfb.22.2017.08.02.10.34.12 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 02 Aug 2017 10:34:12 -0700 (PDT) Date: Wed, 2 Aug 2017 19:34:11 +0200 From: "Edgar E. Iglesias" To: Peter Maydell Cc: qemu-arm@nongnu.org, qemu-devel@nongnu.org, patches@linaro.org Message-ID: <20170802173411.GH4859@toto> References: <1501692241-23310-1-git-send-email-peter.maydell@linaro.org> <1501692241-23310-3-git-send-email-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1501692241-23310-3-git-send-email-peter.maydell@linaro.org> User-Agent: Mutt/1.5.24 (2015-08-30) X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4010:c07::242 Subject: Re: [Qemu-arm] [Qemu-devel] [PATCH 02/15] target/arm: Don't trap WFI/WFE for M profile X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 02 Aug 2017 17:34:20 -0000 On Wed, Aug 02, 2017 at 05:43:48PM +0100, Peter Maydell wrote: > M profile cores can never trap on WFI or WFE instructions. Check for > M profile in check_wfx_trap() to ensure this. > > The existing code will do the right thing for v7M cores because > the hcr_el2 and scr_el3 registers will be all-zeroes and so we > won't attempt to trap, but when we start setting ARM_FEATURE_V8 > for v8M cores the v8A handling of SCTLR.nTWE and .nTWI will not > give the right results. > > Signed-off-by: Peter Maydell Reviewed-by: Edgar E. Iglesias > --- > target/arm/op_helper.c | 5 +++++ > 1 file changed, 5 insertions(+) > > diff --git a/target/arm/op_helper.c b/target/arm/op_helper.c > index 2a85666..5a94a5f 100644 > --- a/target/arm/op_helper.c > +++ b/target/arm/op_helper.c > @@ -370,6 +370,11 @@ static inline int check_wfx_trap(CPUARMState *env, bool is_wfe) > int cur_el = arm_current_el(env); > uint64_t mask; > > + if (arm_feature(env, ARM_FEATURE_M)) { > + /* M profile cores can never trap WFI/WFE. */ > + return 0; > + } > + > /* If we are currently in EL0 then we need to check if SCTLR is set up for > * WFx instructions being trapped to EL1. These trap bits don't exist in v7. > */ > -- > 2.7.4 > > From MAILER-DAEMON Wed Aug 02 13:40:27 2017 Received: from list by lists.gnu.org with archive (Exim 4.71) id 1dcxdD-00030T-F4 for mharc-qemu-arm@gnu.org; Wed, 02 Aug 2017 13:40:27 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:47059) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dcxdA-000308-Je for qemu-arm@nongnu.org; Wed, 02 Aug 2017 13:40:25 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dcxd7-00015U-Fx for qemu-arm@nongnu.org; Wed, 02 Aug 2017 13:40:24 -0400 Received: from mail-lf0-x241.google.com ([2a00:1450:4010:c07::241]:37567) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1dcxd7-00014g-7n; Wed, 02 Aug 2017 13:40:21 -0400 Received: by mail-lf0-x241.google.com with SMTP id x16so4219252lfb.4; Wed, 02 Aug 2017 10:40:21 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=date:from:to:cc:subject:message-id:references:mime-version :content-disposition:in-reply-to:user-agent; bh=DBZh92mIC/gLH4WMXKrZMIf6ekzbF/beIQz5o2I0rdU=; b=Qc+XqBSE7iv69yueJeqwg7oQrOWSVC4fCaV5iZP20T/ofv3HirYQ7zjU0EvVC/4RX3 FlcX5sk1eLvX7NK1LzFnd0joQr7L/zo8aMggxIFOWPTfiI1pm0qHtDvRQKrv10zglE4H LLz5iljSqGyQXdq5YMjXnUwPAdsAE6nTRyexs1Q8KRq0gnu4RRjD5V4UyxIhfy0zyWyj bpBQ3EAhI4Tc0n3DIGaGow1YQpgH6jYmRT/pNV2f+/PU0C3m+FEI2tVD64hX8FLPYKyq OR7V5D9w9sopjD0HY0Npoj6/LmK3hdys5BodeKJtNLpqIbOND8Nq0bzWC/s69X0evbKs aiAw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:in-reply-to:user-agent; bh=DBZh92mIC/gLH4WMXKrZMIf6ekzbF/beIQz5o2I0rdU=; b=PW4Qr00p5+A0ratC53EiwlmUNUqetFIrtvP7rsmKveXX+pUgau6UhnvleVyShzyGgT cA8Es0H2rwuofKGo7ELrKsCt5UfClus8DR0B8COjGU7sfpeaBfgQvp+ezvayHb752P98 9n4Mn8cUtF2GYV1q7WLjdS6NnRuIM3t1IikhmsGjmo08A2oCV3oqFp4eEirNQ6XNnUt6 kZiVXjx/y9j8xCgbLAY25DIpy+E2PjvsgFdjeZGv7f0kWDdcmJGrKrmcJvwM6+xv4f1x FbNHZPowX2r9XBGQ3SBH+YhCWBslUvhawt7BKDOR69s0PlVTHdLSPSPQZu+Z2pin7CeE d5iA== X-Gm-Message-State: AIVw111gry8rvwP/wSkcy3KUsY8QV9vm8FJSjb4OZEowE7M5diP5hD+u v2n1K++JnaYE0g== X-Received: by 10.46.83.81 with SMTP id t17mr8334824ljd.187.1501695619745; Wed, 02 Aug 2017 10:40:19 -0700 (PDT) Received: from gmail.com (81-231-233-234-no56.tbcn.telia.com. [81.231.233.234]) by smtp.gmail.com with ESMTPSA id x133sm6202877lfd.58.2017.08.02.10.40.18 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 02 Aug 2017 10:40:18 -0700 (PDT) Date: Wed, 2 Aug 2017 19:40:18 +0200 From: "Edgar E. Iglesias" To: Peter Maydell Cc: qemu-arm@nongnu.org, qemu-devel@nongnu.org, patches@linaro.org Message-ID: <20170802174018.GI4859@toto> References: <1501692241-23310-1-git-send-email-peter.maydell@linaro.org> <1501692241-23310-4-git-send-email-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1501692241-23310-4-git-send-email-peter.maydell@linaro.org> User-Agent: Mutt/1.5.24 (2015-08-30) X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4010:c07::241 Subject: Re: [Qemu-arm] [Qemu-devel] [PATCH 03/15] target/arm: Consolidate PMSA handling in get_phys_addr() X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 02 Aug 2017 17:40:25 -0000 On Wed, Aug 02, 2017 at 05:43:49PM +0100, Peter Maydell wrote: > Currently get_phys_addr() has PMSAv7 handling before the > "is translation disabled?" check, and then PMSAv5 after it. > Tidy this up by making the PMSAv5 code handle the "MPU disabled" > case itself, so that we have all the PMSA code in one place. > This will make adding the PMSAv8 code slightly cleaner, and > also means that pre-v7 PMSA cores benefit from the MPU lookup > logging that the PMSAv7 codepath had. > > Signed-off-by: Peter Maydell Reviewed-by: Edgar E. Iglesias > --- > target/arm/helper.c | 38 ++++++++++++++++++++++---------------- > 1 file changed, 22 insertions(+), 16 deletions(-) > > diff --git a/target/arm/helper.c b/target/arm/helper.c > index b78d277..fd83a21 100644 > --- a/target/arm/helper.c > +++ b/target/arm/helper.c > @@ -8423,6 +8423,13 @@ static bool get_phys_addr_pmsav5(CPUARMState *env, uint32_t address, > uint32_t base; > bool is_user = regime_is_user(env, mmu_idx); > > + if (regime_translation_disabled(env, mmu_idx)) { > + /* MPU disabled. */ > + *phys_ptr = address; > + *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC; > + return false; > + } > + > *phys_ptr = address; > for (n = 7; n >= 0; n--) { > base = env->cp15.c6_region[n]; > @@ -8572,16 +8579,20 @@ static bool get_phys_addr(CPUARMState *env, target_ulong address, > } > } > > - /* pmsav7 has special handling for when MPU is disabled so call it before > - * the common MMU/MPU disabled check below. > - */ > - if (arm_feature(env, ARM_FEATURE_PMSA) && > - arm_feature(env, ARM_FEATURE_V7)) { > + if (arm_feature(env, ARM_FEATURE_PMSA)) { > bool ret; > *page_size = TARGET_PAGE_SIZE; > - ret = get_phys_addr_pmsav7(env, address, access_type, mmu_idx, > - phys_ptr, prot, fsr); > - qemu_log_mask(CPU_LOG_MMU, "PMSAv7 MPU lookup for %s at 0x%08" PRIx32 > + > + if (arm_feature(env, ARM_FEATURE_V7)) { > + /* PMSAv7 */ > + ret = get_phys_addr_pmsav7(env, address, access_type, mmu_idx, > + phys_ptr, prot, fsr); > + } else { > + /* Pre-v7 MPU */ > + ret = get_phys_addr_pmsav5(env, address, access_type, mmu_idx, > + phys_ptr, prot, fsr); > + } > + qemu_log_mask(CPU_LOG_MMU, "PMSA MPU lookup for %s at 0x%08" PRIx32 > " mmu_idx %u -> %s (prot %c%c%c)\n", > access_type == MMU_DATA_LOAD ? "reading" : > (access_type == MMU_DATA_STORE ? "writing" : "execute"), > @@ -8594,21 +8605,16 @@ static bool get_phys_addr(CPUARMState *env, target_ulong address, > return ret; > } > > + /* Definitely a real MMU, not an MPU */ > + > if (regime_translation_disabled(env, mmu_idx)) { > - /* MMU/MPU disabled. */ > + /* MMU disabled. */ > *phys_ptr = address; > *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC; > *page_size = TARGET_PAGE_SIZE; > return 0; > } > > - if (arm_feature(env, ARM_FEATURE_PMSA)) { > - /* Pre-v7 MPU */ > - *page_size = TARGET_PAGE_SIZE; > - return get_phys_addr_pmsav5(env, address, access_type, mmu_idx, > - phys_ptr, prot, fsr); > - } > - > if (regime_using_lpae_format(env, mmu_idx)) { > return get_phys_addr_lpae(env, address, access_type, mmu_idx, phys_ptr, > attrs, prot, page_size, fsr, fi); > -- > 2.7.4 > > From MAILER-DAEMON Wed Aug 02 13:47:31 2017 Received: from list by lists.gnu.org with archive (Exim 4.71) id 1dcxk3-0004gQ-AI for mharc-qemu-arm@gnu.org; Wed, 02 Aug 2017 13:47:31 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:50321) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dcxk0-0004fw-JO for qemu-arm@nongnu.org; Wed, 02 Aug 2017 13:47:29 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dcxjx-0007dx-Fq for qemu-arm@nongnu.org; Wed, 02 Aug 2017 13:47:28 -0400 Received: from mail-lf0-x241.google.com ([2a00:1450:4010:c07::241]:37875) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1dcxjx-0007cQ-4B; Wed, 02 Aug 2017 13:47:25 -0400 Received: by mail-lf0-x241.google.com with SMTP id x16so4230340lfb.4; Wed, 02 Aug 2017 10:47:24 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=date:from:to:cc:subject:message-id:references:mime-version :content-disposition:in-reply-to:user-agent; bh=rRKrUkLdXiLucSgdeZ/xsCCVTyhEO7N74mBt1hHdJuY=; b=KYnC3xuLPdTBtPnnF+d6Wn8LFPlqG/Jefh6ZRKRo0dFXIw8sCfmQr3bXnMUvGQqjAA +ZkH/FwMf5tdgepRya7ZO6BRCObe32djXFI8zJt4isEH2vkFP/Ohu6pMUHX4pZ3nLgsa I3lXLInF4u4pF2d/omY3skDEvYemg89fHkymaEageChwJt4Hsz8M6hxhDt2YmGAQxFMs 8g9uke0dtyxD5KzieYAkeouTcX+vNs52P3pJ++nh3tLNrgAOj/63KTWNfo7VMIApAIVA vOAAQYZl9iw9JyAQGT7vIf6TuUCZUMrblcRJcLJS4GRy5e/wrx+mUkDKT1EgLwBnUuD7 40Lw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:in-reply-to:user-agent; bh=rRKrUkLdXiLucSgdeZ/xsCCVTyhEO7N74mBt1hHdJuY=; b=jUsH7ID7Y8O+sKgkrEMDVCbsootklMyN8Cc4ho8PUFjzMwlipOpcdAm4Hdy4U6J3zZ yoegsInwi2i8J+D2IHJW/WxYNJcklunPmupboOxdzpWlIX9RQVHGpoBr6bPwvFil66X4 ziZvFjF5N8skpGknN52q1yrNSx9V1Y0ARRFRQI00XPYlkFCkdNXgduJYvnxmi0Ji2u+d GEgGWp5GlnGDnM0pJ7UCI2/3i7OsDpAPCuq25slCYqVDagrUjutSfYKU4gJ8HgpdweGg 4wya1hG8rvmzy+GJeh/6Yb0dZ42MRjVz0HVYCZMiqMzIWHXAq/G6wcQBSogHoCbT1CAE KXbg== X-Gm-Message-State: AIVw111Zm4B8gNID1l4nVTc38hThfhkv/mQQzOziXLfkd0zB4UAvgbNW 8hdm26VxpwfTew== X-Received: by 10.46.14.17 with SMTP id 17mr4333487ljo.61.1501696043323; Wed, 02 Aug 2017 10:47:23 -0700 (PDT) Received: from gmail.com (81-231-233-234-no56.tbcn.telia.com. [81.231.233.234]) by smtp.gmail.com with ESMTPSA id w25sm744622ljd.61.2017.08.02.10.47.22 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 02 Aug 2017 10:47:22 -0700 (PDT) Date: Wed, 2 Aug 2017 19:47:22 +0200 From: "Edgar E. Iglesias" To: Peter Maydell Cc: qemu-arm@nongnu.org, qemu-devel@nongnu.org, patches@linaro.org Message-ID: <20170802174722.GJ4859@toto> References: <1501692241-23310-1-git-send-email-peter.maydell@linaro.org> <1501692241-23310-5-git-send-email-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1501692241-23310-5-git-send-email-peter.maydell@linaro.org> User-Agent: Mutt/1.5.24 (2015-08-30) X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4010:c07::241 Subject: Re: [Qemu-arm] [PATCH 04/15] target/arm: Tighten up Thumb decode where new v8M insns will be X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 02 Aug 2017 17:47:29 -0000 On Wed, Aug 02, 2017 at 05:43:50PM +0100, Peter Maydell wrote: > Tighten up the T32 decoder in the places where new v8M instructions > will be: > * TT/TTT/TTA/TTAT are in what was nominally LDREX/STREX r15, ... > which is UNPREDICTABLE: > make the UNPREDICTABLE behaviour be to UNDEF > * BXNS/BLXNS are distinguished from BX/BLX via the low 3 bits, > which in previous architectural versions are SBZ: > enforce the SBZ via UNDEF rather than ignoring it, and move > the "ARCH(5)" UNDEF case up so we don't leak a TCG temporary > * SG is in the encoding which would be LDRD/STRD with rn = r15; > this is UNPREDICTABLE and we currently UNDEF: > move this check further up the code so that we don't leak > TCG temporaries in the UNDEF case and have a better place > to put the SG decode. > > This means that if a v8M binary is accidentally run on v7M > or if a test case hits something that we haven't implemented > yet the behaviour will be obvious (UNDEF) rather than obscure > (plough on treating it as a different instruction). > > In the process, add some comments about the instruction patterns > at these points in the decode. Our Thumb and ARM decoders are > very difficult to understand currently, but gradually adding > comments like this should help to clarify what exactly has > been decoded when. > > Signed-off-by: Peter Maydell Reviewed-by: Edgar E. Iglesias > --- > target/arm/translate.c | 48 +++++++++++++++++++++++++++++++++++++++--------- > 1 file changed, 39 insertions(+), 9 deletions(-) > > diff --git a/target/arm/translate.c b/target/arm/translate.c > index d1a5f56..3c14cb0 100644 > --- a/target/arm/translate.c > +++ b/target/arm/translate.c > @@ -9735,10 +9735,23 @@ static int disas_thumb2_insn(CPUARMState *env, DisasContext *s, uint16_t insn_hw > abort(); > case 4: > if (insn & (1 << 22)) { > - /* Other load/store, table branch. */ > + /* 0b1110_100x_x1xx_xxxx_xxxx_xxxx_xxxx_xxxx > + * - load/store doubleword, load/store exclusive, ldacq/strel, > + * table branch. > + */ > if (insn & 0x01200000) { > - /* Load/store doubleword. */ > + /* 0b1110_1000_x11x_xxxx_xxxx_xxxx_xxxx_xxxx > + * - load/store dual (post-indexed) > + * 0b1111_1001_x10x_xxxx_xxxx_xxxx_xxxx_xxxx > + * - load/store dual (literal and immediate) > + * 0b1111_1001_x11x_xxxx_xxxx_xxxx_xxxx_xxxx > + * - load/store dual (pre-indexed) > + */ > if (rn == 15) { > + if (insn & (1 << 21)) { > + /* UNPREDICTABLE */ > + goto illegal_op; > + } > addr = tcg_temp_new_i32(); > tcg_gen_movi_i32(addr, s->pc & ~3); > } else { > @@ -9772,15 +9785,18 @@ static int disas_thumb2_insn(CPUARMState *env, DisasContext *s, uint16_t insn_hw > } > if (insn & (1 << 21)) { > /* Base writeback. */ > - if (rn == 15) > - goto illegal_op; > tcg_gen_addi_i32(addr, addr, offset - 4); > store_reg(s, rn, addr); > } else { > tcg_temp_free_i32(addr); > } > } else if ((insn & (1 << 23)) == 0) { > - /* Load/store exclusive word. */ > + /* 0b1110_1000_010x_xxxx_xxxx_xxxx_xxxx_xxxx > + * - load/store exclusive word > + */ > + if (rs == 15) { > + goto illegal_op; > + } > addr = tcg_temp_local_new_i32(); > load_reg_var(s, addr, rn); > tcg_gen_addi_i32(addr, addr, (insn & 0xff) << 2); > @@ -11137,7 +11153,9 @@ static void disas_thumb_insn(CPUARMState *env, DisasContext *s) > break; > } > if (insn & (1 << 10)) { > - /* data processing extended or blx */ > + /* 0b0100_01xx_xxxx_xxxx > + * - data processing extended, branch and exchange > + */ > rd = (insn & 7) | ((insn >> 4) & 8); > rm = (insn >> 3) & 0xf; > op = (insn >> 8) & 3; > @@ -11160,10 +11178,21 @@ static void disas_thumb_insn(CPUARMState *env, DisasContext *s) > tmp = load_reg(s, rm); > store_reg(s, rd, tmp); > break; > - case 3:/* branch [and link] exchange thumb register */ > - tmp = load_reg(s, rm); > - if (insn & (1 << 7)) { > + case 3: > + { > + /* 0b0100_0111_xxxx_xxxx > + * - branch [and link] exchange thumb register > + */ > + bool link = insn & (1 << 7); > + > + if (insn & 7) { > + goto undef; > + } > + if (link) { > ARCH(5); > + } > + tmp = load_reg(s, rm); > + if (link) { > val = (uint32_t)s->pc | 1; > tmp2 = tcg_temp_new_i32(); > tcg_gen_movi_i32(tmp2, val); > @@ -11175,6 +11204,7 @@ static void disas_thumb_insn(CPUARMState *env, DisasContext *s) > } > break; > } > + } > break; > } > > -- > 2.7.4 > > From MAILER-DAEMON Wed Aug 02 13:48:39 2017 Received: from list by lists.gnu.org with archive (Exim 4.71) id 1dcxl9-0005Mm-Be for mharc-qemu-arm@gnu.org; Wed, 02 Aug 2017 13:48:39 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:50745) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dcxl7-0005Iq-1q for qemu-arm@nongnu.org; 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X-Received-From: 2a00:1450:4010:c07::241 Subject: Re: [Qemu-arm] [PATCH 05/15] hw/intc/armv7m_nvic.c: Remove out of date comment X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 02 Aug 2017 17:48:38 -0000 On Wed, Aug 02, 2017 at 05:43:51PM +0100, Peter Maydell wrote: > Remove an out of date comment which says there's only one > item in the NVIC container region -- we put systick into its > own device object a while back and so now there are two > things in the container. > > Signed-off-by: Peter Maydell Reviewed-by: Edgar E. Iglesias > --- > hw/intc/armv7m_nvic.c | 4 ---- > 1 file changed, 4 deletions(-) > > diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c > index 323e2d4..2e8166a 100644 > --- a/hw/intc/armv7m_nvic.c > +++ b/hw/intc/armv7m_nvic.c > @@ -1036,10 +1036,6 @@ static void armv7m_nvic_realize(DeviceState *dev, Error **errp) > * 0xd00..0xd3c - SCS registers > * 0xd40..0xeff - Reserved or Not implemented > * 0xf00 - STIR > - * > - * At the moment there is only one thing in the container region, > - * but we leave it in place to allow us to pull systick out into > - * its own device object later. > */ > memory_region_init(&s->container, OBJECT(s), "nvic", 0x1000); > /* The system register region goes at the bottom of the priority > -- > 2.7.4 > > From MAILER-DAEMON Wed Aug 02 17:47:05 2017 Received: from list by lists.gnu.org with archive (Exim 4.71) id 1dd1Ts-0007la-Ra for mharc-qemu-arm@gnu.org; Wed, 02 Aug 2017 17:47:04 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:49979) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dd1Tr-0007kR-0G for qemu-arm@nongnu.org; Wed, 02 Aug 2017 17:47:03 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dd1Tq-0008H1-51 for qemu-arm@nongnu.org; Wed, 02 Aug 2017 17:47:03 -0400 Received: from mail-vk0-x244.google.com ([2607:f8b0:400c:c05::244]:38273) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1dd1Tl-0008FH-08; Wed, 02 Aug 2017 17:46:57 -0400 Received: by mail-vk0-x244.google.com with SMTP id i133so2797777vka.5; Wed, 02 Aug 2017 14:46:56 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:subject:to:cc:references:from:message-id:date:user-agent :mime-version:in-reply-to:content-language:content-transfer-encoding; bh=7tBCZotMyWhoESq+y/Pz7d6XX6qBqxx3uGqdNrm1l60=; b=hmPTnJXtuXgPdt7ObXyzCTLI5pvm+0FnTmGfS0h/DZG2sjTuefnNmjvkrG/T7qwM4p rVPhnVTeZqEZleF4V2kc53SvW9ptsL9ttOxIRMcPdpDqSUlw7vzWTbPzc6pf0w2eCEfn TktFRHNd3CppreumNf33qzNd21xHrcSivN5h4hUZsoioJAbpo2XvybgZNko+A2aEgXij Yijo3QCJmnna1VvmrRjcHjbwX4ECcxfkOx+JJ3RvUp5Nxa29nZ1AjFDuhhOmO4Uci/+p LgCtG4urxtYizF/1Oyt77bHOUATeyIJfbSVTAg31w3zc9eP9ZcHfoJXCZQlqZj3ZjNGj kLlg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:subject:to:cc:references:from:message-id :date:user-agent:mime-version:in-reply-to:content-language :content-transfer-encoding; bh=7tBCZotMyWhoESq+y/Pz7d6XX6qBqxx3uGqdNrm1l60=; b=Ns8hgdC4RH/9P3CET2NXz5GnZJzquYtaBmz22lDSsbVbWM0JtomUWW1IZ8sgjydVFu MW5jnleSW0Bqxxj5ClwuPD5SJjTsuauaqTZe9Fsc8KCX72p/00rkgc+blNkHq5U1dX2B m+jyieTgyvDBfTqYu3oBqscGvjXoAC3k33gyPaupN/bT4ZlNgHK7vGdinTNJohRnFxVW E+Vcm9ZJ9d3jQ21TsFckBuIItUjOB1twiYt+cUONzK8h9mcDcNqGaEpFBRJOeznWjPEn CKD9ZhC9OtYg0G13LnDB1ghqag4KavTBaZPQTzargnTthDy7KiQWRKx3xbQ4CiaBDaX/ qCXw== X-Gm-Message-State: AIVw1110eutkc6h/2fcRk5iEV9QF56wKjbV01QqnkEbbLrLyT8K07Eap bTOvHTX7vYJVnA== X-Received: by 10.31.33.80 with SMTP id h77mr13002756vkh.11.1501710416341; Wed, 02 Aug 2017 14:46:56 -0700 (PDT) Received: from [192.168.1.10] ([138.117.48.223]) by smtp.gmail.com with ESMTPSA id h97sm8056969uah.56.2017.08.02.14.46.54 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 02 Aug 2017 14:46:55 -0700 (PDT) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= To: Peter Maydell , qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: patches@linaro.org References: <1501692241-23310-1-git-send-email-peter.maydell@linaro.org> <1501692241-23310-13-git-send-email-peter.maydell@linaro.org> From: =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= Message-ID: Date: Wed, 2 Aug 2017 18:46:53 -0300 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.2.1 MIME-Version: 1.0 In-Reply-To: <1501692241-23310-13-git-send-email-peter.maydell@linaro.org> Content-Type: text/plain; charset=utf-8; format=flowed Content-Language: en-US Content-Transfer-Encoding: 8bit X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400c:c05::244 Subject: Re: [Qemu-arm] [PATCH 12/15] target/arm: Don't calculate lr in arm_v7m_cpu_do_interrupt() until needed X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 02 Aug 2017 21:47:04 -0000 On 08/02/2017 01:43 PM, Peter Maydell wrote: > Move the code in arm_v7m_cpu_do_interrupt() that calculates the > magic LR value down to when we're actually going to use it. > Having the calculation and use so far apart makes the code > a little harder to understand than it needs to be. > > Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daudé > --- > target/arm/helper.c | 15 ++++++++------- > 1 file changed, 8 insertions(+), 7 deletions(-) > > diff --git a/target/arm/helper.c b/target/arm/helper.c > index b64ddb1..0ecc8f1 100644 > --- a/target/arm/helper.c > +++ b/target/arm/helper.c > @@ -6311,13 +6311,6 @@ void arm_v7m_cpu_do_interrupt(CPUState *cs) > > arm_log_exception(cs->exception_index); > > - lr = 0xfffffff1; > - if (env->v7m.control & R_V7M_CONTROL_SPSEL_MASK) { > - lr |= 4; > - } > - if (env->v7m.exception == 0) > - lr |= 8; > - > /* For exceptions we just mark as pending on the NVIC, and let that > handle it. */ > switch (cs->exception_index) { > @@ -6408,6 +6401,14 @@ void arm_v7m_cpu_do_interrupt(CPUState *cs) > return; /* Never happens. Keep compiler happy. */ > } > > + lr = 0xfffffff1; > + if (env->v7m.control & R_V7M_CONTROL_SPSEL_MASK) { > + lr |= 4; > + } > + if (env->v7m.exception == 0) { > + lr |= 8; > + } > + > v7m_push_stack(cpu); > v7m_exception_taken(cpu, lr); > qemu_log_mask(CPU_LOG_INT, "... as %d\n", env->v7m.exception); > From MAILER-DAEMON Wed Aug 02 17:48:19 2017 Received: from list by lists.gnu.org with archive (Exim 4.71) id 1dd1V5-0008Rn-Oa for mharc-qemu-arm@gnu.org; Wed, 02 Aug 2017 17:48:19 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:50404) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dd1V1-0008Pr-NZ for qemu-arm@nongnu.org; Wed, 02 Aug 2017 17:48:16 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dd1V0-0000Ji-OG for qemu-arm@nongnu.org; Wed, 02 Aug 2017 17:48:15 -0400 Received: from mail-ua0-x242.google.com ([2607:f8b0:400c:c08::242]:35740) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1dd1Uv-0000Hz-9P; Wed, 02 Aug 2017 17:48:09 -0400 Received: by mail-ua0-x242.google.com with SMTP id d29so3245226uai.2; Wed, 02 Aug 2017 14:48:09 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:subject:to:cc:references:from:message-id:date:user-agent :mime-version:in-reply-to:content-language:content-transfer-encoding; bh=lCgDkqfX8Qj9Uidkm4agKWj5wQQUQFt+okT/rF6i2g4=; b=AEOKqCbvch+PZHaHKtyKk1v2JpW8MzPampTsBYJolGgrKoU2UWxYEHinbx/gW3Ngk7 /u7TJtEnTZYu4cwqWwnIn+7jfurBVcl9QEnksPvIgaXl4e+bMBoyBnXqscCjtcnPNVnG /5aR8OalDnCHFqJ4BFLQx1RWwxAjbXi+yVQUGZitPCLd6DaBahPPUSDeR5plnZtVKNoJ sIuqtGeI9o8JqGwfR/Aei6dfDidtmdx13intj2wOs8omlexTS9jQgFow1c/MeJQwRwtr jum2p89iVWXdNYOssnR8l2e/i1Oa86BTXInBVQGouq3gXkTNPcGb4pDX3PBowUdttlKc 8xpg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:subject:to:cc:references:from:message-id :date:user-agent:mime-version:in-reply-to:content-language :content-transfer-encoding; bh=lCgDkqfX8Qj9Uidkm4agKWj5wQQUQFt+okT/rF6i2g4=; b=f7ArcFeleGR/c/2wLnQNyDaVBVm7aeVnos6Qr+3IqoT1g4AIBXx3e9yG33+b1n+9HA GVQCIaoV2TmiyVf0LG4n+0hg2Idt9NL6P/XqumRZH4UNXwYIjVNWyNnvXZLNFW6DiguA T5yMJ/HKnBB1kELzxXxtj1Y1pLRd8G+5RAydv8j6WrDpKsRcMj+XVnROeHgiHzjmAaeJ yuB4p2QONQqWxECr/36JLCk2z2S3kY3KFiOUUE1K5aZ+Qi1mKGFGBa9VKxya+zBKakzs 5M+eYk6o4LLN7gbdlk2hQgtA9sMlshAk/J+5s3owOWP4IAo+bijqoqF2rdrtj4v/Nsh2 gNhA== X-Gm-Message-State: AIVw110TnuhW7XR8uOW/s/Q49+5ccoDmpIZ/B6oSxNc7kUfBVcFqpzyk 9Garp3SFXbUh5w== X-Received: by 10.176.91.7 with SMTP id u7mr10947127uae.152.1501710488566; Wed, 02 Aug 2017 14:48:08 -0700 (PDT) Received: from [192.168.1.10] ([138.117.48.223]) by smtp.gmail.com with ESMTPSA id i3sm5828573uad.17.2017.08.02.14.48.06 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 02 Aug 2017 14:48:07 -0700 (PDT) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= To: Peter Maydell , qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: patches@linaro.org References: <1501692241-23310-1-git-send-email-peter.maydell@linaro.org> <1501692241-23310-14-git-send-email-peter.maydell@linaro.org> From: =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= Message-ID: <065454c5-623d-8859-3e8d-bdfe3300c91e@amsat.org> Date: Wed, 2 Aug 2017 18:48:05 -0300 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.2.1 MIME-Version: 1.0 In-Reply-To: <1501692241-23310-14-git-send-email-peter.maydell@linaro.org> Content-Type: text/plain; charset=utf-8; format=flowed Content-Language: en-US Content-Transfer-Encoding: 8bit X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400c:c08::242 Subject: Re: [Qemu-arm] [PATCH 13/15] target/arm: Create and use new function arm_v7m_is_handler_mode() X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 02 Aug 2017 21:48:17 -0000 On 08/02/2017 01:43 PM, Peter Maydell wrote: > Add a utility function for testing whether the CPU is in Handler > mode; this is just a check whether v7m.exception is non-zero, but > we do it in several places and it makes the code a bit easier > to read to not have to mentally figure out what the test is testing. <3 <3 <3 > > Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daudé > --- > target/arm/cpu.h | 10 ++++++++-- > target/arm/helper.c | 8 ++++---- > 2 files changed, 12 insertions(+), 6 deletions(-) > > diff --git a/target/arm/cpu.h b/target/arm/cpu.h > index da90b7a..a3b4b78 100644 > --- a/target/arm/cpu.h > +++ b/target/arm/cpu.h > @@ -1630,13 +1630,19 @@ static inline int arm_highest_el(CPUARMState *env) > return 1; > } > > +/* Return true if a v7M CPU is in Handler mode */ > +static inline bool arm_v7m_is_handler_mode(CPUARMState *env) > +{ > + return env->v7m.exception != 0; > +} > + > /* Return the current Exception Level (as per ARMv8; note that this differs > * from the ARMv7 Privilege Level). > */ > static inline int arm_current_el(CPUARMState *env) > { > if (arm_feature(env, ARM_FEATURE_M)) { > - return !((env->v7m.exception == 0) && (env->v7m.control & 1)); > + return arm_v7m_is_handler_mode(env) || !(env->v7m.control & 1); > } > > if (is_a64(env)) { > @@ -2636,7 +2642,7 @@ static inline void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc, > } > *flags |= fp_exception_el(env) << ARM_TBFLAG_FPEXC_EL_SHIFT; > > - if (env->v7m.exception != 0) { > + if (arm_v7m_is_handler_mode(env)) { > *flags |= ARM_TBFLAG_HANDLER_MASK; > } > > diff --git a/target/arm/helper.c b/target/arm/helper.c > index 0ecc8f1..7920153 100644 > --- a/target/arm/helper.c > +++ b/target/arm/helper.c > @@ -6147,7 +6147,7 @@ static void do_v7m_exception_exit(ARMCPU *cpu) > * that jumps to magic addresses don't have magic behaviour unless > * we're in Handler mode (compare pseudocode BXWritePC()). > */ > - assert(env->v7m.exception != 0); > + assert(arm_v7m_is_handler_mode(env)); > > /* In the spec pseudocode ExceptionReturn() is called directly > * from BXWritePC() and gets the full target PC value including > @@ -6254,7 +6254,7 @@ static void do_v7m_exception_exit(ARMCPU *cpu) > * resuming in Thread mode. If that doesn't match what the > * exception return type specified then this is a UsageFault. > */ > - if (return_to_handler == (env->v7m.exception == 0)) { > + if (return_to_handler != arm_v7m_is_handler_mode(env)) { > /* Take an INVPC UsageFault by pushing the stack again. */ > armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE); > env->v7m.cfsr |= R_V7M_CFSR_INVPC_MASK; > @@ -6405,7 +6405,7 @@ void arm_v7m_cpu_do_interrupt(CPUState *cs) > if (env->v7m.control & R_V7M_CONTROL_SPSEL_MASK) { > lr |= 4; > } > - if (env->v7m.exception == 0) { > + if (!arm_v7m_is_handler_mode(env)) { > lr |= 8; > } > > @@ -8798,7 +8798,7 @@ void HELPER(v7m_msr)(CPUARMState *env, uint32_t maskreg, uint32_t val) > * switch_v7m_sp() deals with updating the SPSEL bit in > * env->v7m.control, so we only need update the others. > */ > - if (env->v7m.exception == 0) { > + if (!arm_v7m_is_handler_mode(env)) { > switch_v7m_sp(env, (val & R_V7M_CONTROL_SPSEL_MASK) != 0); > } > env->v7m.control &= ~R_V7M_CONTROL_NPRIV_MASK; > From MAILER-DAEMON Wed Aug 02 17:49:19 2017 Received: from list by lists.gnu.org with archive (Exim 4.71) id 1dd1W3-0000mo-1F for mharc-qemu-arm@gnu.org; Wed, 02 Aug 2017 17:49:19 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:50910) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dd1W0-0000ky-Ke for qemu-arm@nongnu.org; Wed, 02 Aug 2017 17:49:17 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dd1Vz-0000iI-NI for qemu-arm@nongnu.org; Wed, 02 Aug 2017 17:49:16 -0400 Received: from mail-qk0-x244.google.com ([2607:f8b0:400d:c09::244]:38881) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1dd1Vx-0000gz-5Q; Wed, 02 Aug 2017 17:49:13 -0400 Received: by mail-qk0-x244.google.com with SMTP id m84so5881720qki.5; Wed, 02 Aug 2017 14:49:13 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:subject:to:cc:references:from:message-id:date:user-agent :mime-version:in-reply-to:content-language:content-transfer-encoding; bh=OOX77wjwMZXmqch69YiLuoCKvHduHh2K3N8aWKdD19M=; b=WqG14tDAzn8oEzfDqvgq0K7gM/sYXjOx/uUcxHHrf4UlBZU0b8UpcBNonTtRAQBrvr 1YEA/T3KH9qBTFs8su6vBds3rhxd3isui+8OHXEdTjDcNl/XphERLGjH0vu/wqYtNx6l TMejDNICP51uQ49cKFb9Mn5dbXrmRkuqPfb0Ph4SNodOTfp0Z6lEhJzoqQ/SJ/xvEhHB 91k+SqIWSJz5AL+58CObxOsi+VdUHw0aYXhwhQVVPORmprXNOqIue1QZhhPbRsyxv+zk W5HbIy4KDZ8G5jqxzJgEysS0H1/efw/H2v7cAjHwpPdJFU7uGYdW01IjZAHFypWzsqqg SitQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:subject:to:cc:references:from:message-id :date:user-agent:mime-version:in-reply-to:content-language :content-transfer-encoding; bh=OOX77wjwMZXmqch69YiLuoCKvHduHh2K3N8aWKdD19M=; b=EZwsMda4fB2zanIfwUQBvab+BV9Ng/K9cKGL4byrFgOVQD6V/ikjGSgTAZ83ONwiWv 54gfNgWVCVvWRgYwtRl7OD9dcwqPQeIFG9YyDdfdJjeXAkoJxcY9a0nk3Yfz0gs0YDMc aG5RSptr474ws9VX8flDqvRp1oXf/rHBT01s0WZ322bOthqDOd4UlysO/J4ghepSiLf/ Qw6pkciboh/dpVXaGqbQohUpP8ZUZ91smmiIfq5uOw6XrT7/+PbDEcaFs7P7OljJuS/a a8C47LVYgUyE+OWaV6+inVasqYnsxDoaLE0rKRukf8G0h8ZjXRlLIo5cCVng6p/Ygu7Z psXA== X-Gm-Message-State: AIVw113po/6VbrABDsIfdtTqjaV35smIKyTmPofB1hMbTezfBK1aV4FH +qBLuJ4OO699SA== X-Received: by 10.55.113.5 with SMTP id m5mr31581381qkc.88.1501710552542; Wed, 02 Aug 2017 14:49:12 -0700 (PDT) Received: from [192.168.1.10] ([138.117.48.223]) by smtp.gmail.com with ESMTPSA id m123sm24029925qke.12.2017.08.02.14.49.10 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 02 Aug 2017 14:49:11 -0700 (PDT) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= To: Peter Maydell , qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: patches@linaro.org References: <1501692241-23310-1-git-send-email-peter.maydell@linaro.org> <1501692241-23310-15-git-send-email-peter.maydell@linaro.org> From: =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= Message-ID: <988ce89c-4e6c-5cf3-f040-7797a9f7902d@amsat.org> Date: Wed, 2 Aug 2017 18:49:09 -0300 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.2.1 MIME-Version: 1.0 In-Reply-To: <1501692241-23310-15-git-send-email-peter.maydell@linaro.org> Content-Type: text/plain; charset=utf-8; format=flowed Content-Language: en-US Content-Transfer-Encoding: 8bit X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400d:c09::244 Subject: Re: [Qemu-arm] [PATCH 14/15] armv7m_nvic.h: Move from include/hw/arm to include/hw/intc X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 02 Aug 2017 21:49:17 -0000 On 08/02/2017 01:44 PM, Peter Maydell wrote: > The armv7m_nvic.h header file was accidentally placed in > include/hw/arm; move it to include/hw/intc to match where > its corresponding .c file lives. > > Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daudé > --- > hw/intc/armv7m_nvic.c | 2 +- > include/hw/arm/armv7m.h | 2 +- > include/hw/{arm => intc}/armv7m_nvic.h | 0 > 3 files changed, 2 insertions(+), 2 deletions(-) > rename include/hw/{arm => intc}/armv7m_nvic.h (100%) > > diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c > index 343bc16..5a18025 100644 > --- a/hw/intc/armv7m_nvic.c > +++ b/hw/intc/armv7m_nvic.c > @@ -17,7 +17,7 @@ > #include "hw/sysbus.h" > #include "qemu/timer.h" > #include "hw/arm/arm.h" > -#include "hw/arm/armv7m_nvic.h" > +#include "hw/intc/armv7m_nvic.h" > #include "target/arm/cpu.h" > #include "exec/exec-all.h" > #include "qemu/log.h" > diff --git a/include/hw/arm/armv7m.h b/include/hw/arm/armv7m.h > index a9b3f2a..10eb058 100644 > --- a/include/hw/arm/armv7m.h > +++ b/include/hw/arm/armv7m.h > @@ -11,7 +11,7 @@ > #define HW_ARM_ARMV7M_H > > #include "hw/sysbus.h" > -#include "hw/arm/armv7m_nvic.h" > +#include "hw/intc/armv7m_nvic.h" > > #define TYPE_BITBAND "ARM,bitband-memory" > #define BITBAND(obj) OBJECT_CHECK(BitBandState, (obj), TYPE_BITBAND) > diff --git a/include/hw/arm/armv7m_nvic.h b/include/hw/intc/armv7m_nvic.h > similarity index 100% > rename from include/hw/arm/armv7m_nvic.h > rename to include/hw/intc/armv7m_nvic.h > From MAILER-DAEMON Wed Aug 02 17:51:12 2017 Received: from list by lists.gnu.org with archive (Exim 4.71) id 1dd1Xs-0001iW-HK for mharc-qemu-arm@gnu.org; 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Wed, 02 Aug 2017 14:51:01 -0700 (PDT) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= To: Peter Maydell , qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: patches@linaro.org References: <1501692241-23310-1-git-send-email-peter.maydell@linaro.org> <1501692241-23310-4-git-send-email-peter.maydell@linaro.org> From: =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= Message-ID: <6c967927-f368-84c4-ce7e-54e51576ed14@amsat.org> Date: Wed, 2 Aug 2017 18:50:59 -0300 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.2.1 MIME-Version: 1.0 In-Reply-To: <1501692241-23310-4-git-send-email-peter.maydell@linaro.org> Content-Type: text/plain; charset=utf-8; format=flowed Content-Language: en-US Content-Transfer-Encoding: 8bit X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400d:c0d::242 Subject: Re: [Qemu-arm] [Qemu-devel] [PATCH 03/15] target/arm: Consolidate PMSA handling in get_phys_addr() X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 02 Aug 2017 21:51:10 -0000 On 08/02/2017 01:43 PM, Peter Maydell wrote: > Currently get_phys_addr() has PMSAv7 handling before the > "is translation disabled?" check, and then PMSAv5 after it. > Tidy this up by making the PMSAv5 code handle the "MPU disabled" > case itself, so that we have all the PMSA code in one place. > This will make adding the PMSAv8 code slightly cleaner, and > also means that pre-v7 PMSA cores benefit from the MPU lookup > logging that the PMSAv7 codepath had. > > Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daudé > --- > target/arm/helper.c | 38 ++++++++++++++++++++++---------------- > 1 file changed, 22 insertions(+), 16 deletions(-) > > diff --git a/target/arm/helper.c b/target/arm/helper.c > index b78d277..fd83a21 100644 > --- a/target/arm/helper.c > +++ b/target/arm/helper.c > @@ -8423,6 +8423,13 @@ static bool get_phys_addr_pmsav5(CPUARMState *env, uint32_t address, > uint32_t base; > bool is_user = regime_is_user(env, mmu_idx); > > + if (regime_translation_disabled(env, mmu_idx)) { > + /* MPU disabled. */ > + *phys_ptr = address; > + *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC; > + return false; > + } > + > *phys_ptr = address; > for (n = 7; n >= 0; n--) { > base = env->cp15.c6_region[n]; > @@ -8572,16 +8579,20 @@ static bool get_phys_addr(CPUARMState *env, target_ulong address, > } > } > > - /* pmsav7 has special handling for when MPU is disabled so call it before > - * the common MMU/MPU disabled check below. > - */ > - if (arm_feature(env, ARM_FEATURE_PMSA) && > - arm_feature(env, ARM_FEATURE_V7)) { > + if (arm_feature(env, ARM_FEATURE_PMSA)) { > bool ret; > *page_size = TARGET_PAGE_SIZE; > - ret = get_phys_addr_pmsav7(env, address, access_type, mmu_idx, > - phys_ptr, prot, fsr); > - qemu_log_mask(CPU_LOG_MMU, "PMSAv7 MPU lookup for %s at 0x%08" PRIx32 > + > + if (arm_feature(env, ARM_FEATURE_V7)) { > + /* PMSAv7 */ > + ret = get_phys_addr_pmsav7(env, address, access_type, mmu_idx, > + phys_ptr, prot, fsr); > + } else { > + /* Pre-v7 MPU */ > + ret = get_phys_addr_pmsav5(env, address, access_type, mmu_idx, > + phys_ptr, prot, fsr); > + } > + qemu_log_mask(CPU_LOG_MMU, "PMSA MPU lookup for %s at 0x%08" PRIx32 > " mmu_idx %u -> %s (prot %c%c%c)\n", > access_type == MMU_DATA_LOAD ? "reading" : > (access_type == MMU_DATA_STORE ? "writing" : "execute"), > @@ -8594,21 +8605,16 @@ static bool get_phys_addr(CPUARMState *env, target_ulong address, > return ret; > } > > + /* Definitely a real MMU, not an MPU */ > + > if (regime_translation_disabled(env, mmu_idx)) { > - /* MMU/MPU disabled. */ > + /* MMU disabled. */ > *phys_ptr = address; > *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC; > *page_size = TARGET_PAGE_SIZE; > return 0; > } > > - if (arm_feature(env, ARM_FEATURE_PMSA)) { > - /* Pre-v7 MPU */ > - *page_size = TARGET_PAGE_SIZE; > - return get_phys_addr_pmsav5(env, address, access_type, mmu_idx, > - phys_ptr, prot, fsr); > - } > - > if (regime_using_lpae_format(env, mmu_idx)) { > return get_phys_addr_lpae(env, address, access_type, mmu_idx, phys_ptr, > attrs, prot, page_size, fsr, fi); > From MAILER-DAEMON Wed Aug 02 17:52:39 2017 Received: from list by lists.gnu.org with archive (Exim 4.71) id 1dd1ZH-0002K3-Ls for mharc-qemu-arm@gnu.org; Wed, 02 Aug 2017 17:52:39 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:52038) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dd1ZF-0002IP-DQ for qemu-arm@nongnu.org; Wed, 02 Aug 2017 17:52:38 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dd1ZE-0002Sf-0A for qemu-arm@nongnu.org; Wed, 02 Aug 2017 17:52:37 -0400 Received: from mail-qk0-x244.google.com ([2607:f8b0:400d:c09::244]:35387) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1dd1Z9-0002Pi-1H; Wed, 02 Aug 2017 17:52:31 -0400 Received: by mail-qk0-x244.google.com with SMTP id a77so5897056qkb.2; Wed, 02 Aug 2017 14:52:30 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:subject:to:cc:references:from:message-id:date:user-agent :mime-version:in-reply-to:content-language:content-transfer-encoding; bh=uM36W44eEre2ZYawEhXVgaKDvYhqrnowz49vzzxfH+Y=; b=pJgSDm03EzHcZCpZmikxnTIR28gAxcEoy5g1pBECIpeyRGAMR8yuHI5a3xDxCdX1/I F7rC+NpCJ7NuG3q6440+8YFhQieR12B2Ty9cGN4yJVla64B5HIp3UiANVzuclgvSgT5P 2hzqu8ti/JNEaWpuZ8mf2rU3nDU9spNF2LIc1RV6N6U+WkWPLFrdmbJpnDVQ2vsgJwoq U/I8PaA50ThIPKAbx8J3Wx0p3BS/ZhIyBbfV/RodEEJ068XLGjuZx6+FWely2tmT74em 4NrAbAjFW69uwv71xVfUDhpoNZUHI/zsdM5oNAifDP9dHF+0X8OfQuB5S8KyWSDy3fbf yTcQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:subject:to:cc:references:from:message-id :date:user-agent:mime-version:in-reply-to:content-language :content-transfer-encoding; bh=uM36W44eEre2ZYawEhXVgaKDvYhqrnowz49vzzxfH+Y=; b=cUOYpL3XutAAj4l+y6DStbwsV49t1OfvI2wF7Zn9R++Lm6si1xX4crTQjZoEGGf309 wAZkTdMR9aKNgy+8Fz7f86UsUoY91p/GGYnJlC9Bm3Wot+fXhHcK5N93YUbcZBiz/HX4 EZMtrXt9nH+ddHNrw0BIFP2X8r/q1PLXd34NTzqF7zaKHG5w/4HdLZv+D/CO/Q3ruA3c p8ZaTgnnxuwhn4+v9Nw2rStOSG1MuHzFXdr0QbmTQ7GN1fr8OfWft407TYmCTJCyS9wt vItPAQCGqFcYBS6FSjyfRr/hXopqpoP+OnuEzu53IM+IR5McvAOhK56fI/H01XJ4xJzb ZpYg== X-Gm-Message-State: AIVw110pVvQcZ1qf0Uh7PdOQy2ZKZ69peBak9HjFC4t8C3Exla1uo68a w0TKiAuI1RqnOg== X-Received: by 10.55.160.15 with SMTP id j15mr33893569qke.324.1501710750328; Wed, 02 Aug 2017 14:52:30 -0700 (PDT) Received: from [192.168.1.10] ([138.117.48.223]) by smtp.gmail.com with ESMTPSA id w46sm8855498qtc.16.2017.08.02.14.52.28 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 02 Aug 2017 14:52:29 -0700 (PDT) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= To: Peter Maydell , qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: patches@linaro.org References: <1501692241-23310-1-git-send-email-peter.maydell@linaro.org> <1501692241-23310-2-git-send-email-peter.maydell@linaro.org> From: =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= Message-ID: Date: Wed, 2 Aug 2017 18:52:27 -0300 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.2.1 MIME-Version: 1.0 In-Reply-To: <1501692241-23310-2-git-send-email-peter.maydell@linaro.org> Content-Type: text/plain; charset=utf-8; format=flowed Content-Language: en-US Content-Transfer-Encoding: 8bit X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400d:c09::244 Subject: Re: [Qemu-arm] [PATCH 01/15] target/arm: Use MMUAccessType enum rather than int X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 02 Aug 2017 21:52:38 -0000 On 08/02/2017 01:43 PM, Peter Maydell wrote: > In the ARM get_phys_addr() code, switch to using the MMUAccessType > enum and its MMU_* values rather than int and literal 0/1/2. > > Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daudé > --- > target/arm/helper.c | 30 +++++++++++++++--------------- > target/arm/internals.h | 3 ++- > 2 files changed, 17 insertions(+), 16 deletions(-) > > diff --git a/target/arm/helper.c b/target/arm/helper.c > index fa60040..b78d277 100644 > --- a/target/arm/helper.c > +++ b/target/arm/helper.c > @@ -20,13 +20,13 @@ > > #ifndef CONFIG_USER_ONLY > static bool get_phys_addr(CPUARMState *env, target_ulong address, > - int access_type, ARMMMUIdx mmu_idx, > + MMUAccessType access_type, ARMMMUIdx mmu_idx, > hwaddr *phys_ptr, MemTxAttrs *attrs, int *prot, > target_ulong *page_size, uint32_t *fsr, > ARMMMUFaultInfo *fi); > > static bool get_phys_addr_lpae(CPUARMState *env, target_ulong address, > - int access_type, ARMMMUIdx mmu_idx, > + MMUAccessType access_type, ARMMMUIdx mmu_idx, > hwaddr *phys_ptr, MemTxAttrs *txattrs, int *prot, > target_ulong *page_size_ptr, uint32_t *fsr, > ARMMMUFaultInfo *fi); > @@ -2135,7 +2135,7 @@ static CPAccessResult ats_access(CPUARMState *env, const ARMCPRegInfo *ri, > } > > static uint64_t do_ats_write(CPUARMState *env, uint64_t value, > - int access_type, ARMMMUIdx mmu_idx) > + MMUAccessType access_type, ARMMMUIdx mmu_idx) > { > hwaddr phys_addr; > target_ulong page_size; > @@ -2194,7 +2194,7 @@ static uint64_t do_ats_write(CPUARMState *env, uint64_t value, > > static void ats_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) > { > - int access_type = ri->opc2 & 1; > + MMUAccessType access_type = ri->opc2 & 1 ? MMU_DATA_STORE : MMU_DATA_LOAD; > uint64_t par64; > ARMMMUIdx mmu_idx; > int el = arm_current_el(env); > @@ -2253,7 +2253,7 @@ static void ats_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) > static void ats1h_write(CPUARMState *env, const ARMCPRegInfo *ri, > uint64_t value) > { > - int access_type = ri->opc2 & 1; > + MMUAccessType access_type = ri->opc2 & 1 ? MMU_DATA_STORE : MMU_DATA_LOAD; > uint64_t par64; > > par64 = do_ats_write(env, value, access_type, ARMMMUIdx_S2NS); > @@ -2273,7 +2273,7 @@ static CPAccessResult at_s1e2_access(CPUARMState *env, const ARMCPRegInfo *ri, > static void ats_write64(CPUARMState *env, const ARMCPRegInfo *ri, > uint64_t value) > { > - int access_type = ri->opc2 & 1; > + MMUAccessType access_type = ri->opc2 & 1 ? MMU_DATA_STORE : MMU_DATA_LOAD; > ARMMMUIdx mmu_idx; > int secure = arm_is_secure_below_el3(env); > > @@ -7510,7 +7510,7 @@ static uint64_t arm_ldq_ptw(CPUState *cs, hwaddr addr, bool is_secure, > } > > static bool get_phys_addr_v5(CPUARMState *env, uint32_t address, > - int access_type, ARMMMUIdx mmu_idx, > + MMUAccessType access_type, ARMMMUIdx mmu_idx, > hwaddr *phys_ptr, int *prot, > target_ulong *page_size, uint32_t *fsr, > ARMMMUFaultInfo *fi) > @@ -7626,7 +7626,7 @@ do_fault: > } > > static bool get_phys_addr_v6(CPUARMState *env, uint32_t address, > - int access_type, ARMMMUIdx mmu_idx, > + MMUAccessType access_type, ARMMMUIdx mmu_idx, > hwaddr *phys_ptr, MemTxAttrs *attrs, int *prot, > target_ulong *page_size, uint32_t *fsr, > ARMMMUFaultInfo *fi) > @@ -7733,7 +7733,7 @@ static bool get_phys_addr_v6(CPUARMState *env, uint32_t address, > if (pxn && !regime_is_user(env, mmu_idx)) { > xn = 1; > } > - if (xn && access_type == 2) > + if (xn && access_type == MMU_INST_FETCH) > goto do_fault; > > if (arm_feature(env, ARM_FEATURE_V6K) && > @@ -7848,7 +7848,7 @@ static bool check_s2_mmu_setup(ARMCPU *cpu, bool is_aa64, int level, > } > > static bool get_phys_addr_lpae(CPUARMState *env, target_ulong address, > - int access_type, ARMMMUIdx mmu_idx, > + MMUAccessType access_type, ARMMMUIdx mmu_idx, > hwaddr *phys_ptr, MemTxAttrs *txattrs, int *prot, > target_ulong *page_size_ptr, uint32_t *fsr, > ARMMMUFaultInfo *fi) > @@ -8256,7 +8256,7 @@ static inline bool m_is_system_region(CPUARMState *env, uint32_t address) > } > > static bool get_phys_addr_pmsav7(CPUARMState *env, uint32_t address, > - int access_type, ARMMMUIdx mmu_idx, > + MMUAccessType access_type, ARMMMUIdx mmu_idx, > hwaddr *phys_ptr, int *prot, uint32_t *fsr) > { > ARMCPU *cpu = arm_env_get_cpu(env); > @@ -8415,7 +8415,7 @@ static bool get_phys_addr_pmsav7(CPUARMState *env, uint32_t address, > } > > static bool get_phys_addr_pmsav5(CPUARMState *env, uint32_t address, > - int access_type, ARMMMUIdx mmu_idx, > + MMUAccessType access_type, ARMMMUIdx mmu_idx, > hwaddr *phys_ptr, int *prot, uint32_t *fsr) > { > int n; > @@ -8442,7 +8442,7 @@ static bool get_phys_addr_pmsav5(CPUARMState *env, uint32_t address, > return true; > } > > - if (access_type == 2) { > + if (access_type == MMU_INST_FETCH) { > mask = env->cp15.pmsav5_insn_ap; > } else { > mask = env->cp15.pmsav5_data_ap; > @@ -8513,7 +8513,7 @@ static bool get_phys_addr_pmsav5(CPUARMState *env, uint32_t address, > * @fsr: set to the DFSR/IFSR value on failure > */ > static bool get_phys_addr(CPUARMState *env, target_ulong address, > - int access_type, ARMMMUIdx mmu_idx, > + MMUAccessType access_type, ARMMMUIdx mmu_idx, > hwaddr *phys_ptr, MemTxAttrs *attrs, int *prot, > target_ulong *page_size, uint32_t *fsr, > ARMMMUFaultInfo *fi) > @@ -8626,7 +8626,7 @@ static bool get_phys_addr(CPUARMState *env, target_ulong address, > * fsr with ARM DFSR/IFSR fault register format value on failure. > */ > bool arm_tlb_fill(CPUState *cs, vaddr address, > - int access_type, int mmu_idx, uint32_t *fsr, > + MMUAccessType access_type, int mmu_idx, uint32_t *fsr, > ARMMMUFaultInfo *fi) > { > ARMCPU *cpu = ARM_CPU(cs); > diff --git a/target/arm/internals.h b/target/arm/internals.h > index 1f6efef..bb06946 100644 > --- a/target/arm/internals.h > +++ b/target/arm/internals.h > @@ -457,7 +457,8 @@ struct ARMMMUFaultInfo { > }; > > /* Do a page table walk and add page to TLB if possible */ > -bool arm_tlb_fill(CPUState *cpu, vaddr address, int rw, int mmu_idx, > +bool arm_tlb_fill(CPUState *cpu, vaddr address, > + MMUAccessType access_type, int mmu_idx, > uint32_t *fsr, ARMMMUFaultInfo *fi); > > /* Return true if the stage 1 translation regime is using LPAE format page > From MAILER-DAEMON Thu Aug 03 06:11:42 2017 Received: from list by lists.gnu.org with archive (Exim 4.71) id 1ddD6T-0004YU-Vi for mharc-qemu-arm@gnu.org; Thu, 03 Aug 2017 06:11:42 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:51862) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ddD6R-0004WU-Pl for qemu-arm@nongnu.org; Thu, 03 Aug 2017 06:11:40 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ddD6N-0000kd-HR for qemu-arm@nongnu.org; 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Thu, 3 Aug 2017 10:11:23 +0000 To: Auger Eric , eric.auger.pro@gmail.com, peter.maydell@linaro.org, qemu-arm@nongnu.org, qemu-devel@nongnu.org, alex.williamson@redhat.com, prem.mallappa@gmail.com Cc: drjones@redhat.com, christoffer.dall@linaro.org, Radha.Chintakuntla@cavium.com, Sunil.Goutham@cavium.com, mohun106@gmail.com, tcain@qti.qualcomm.com, bharat.bhushan@nxp.com, mst@redhat.com, will.deacon@arm.com, jean-philippe.brucker@arm.com, robin.murphy@arm.com, peterx@redhat.com, edgar.iglesias@gmail.com, "Nair, Jayachandran" References: <1499633493-19865-1-git-send-email-eric.auger@redhat.com> <50d1685e-bfa6-02ac-2650-37637745431a@redhat.com> From: Tomasz Nowicki Message-ID: <35467208-4e8f-b944-c247-c049c2301878@caviumnetworks.com> Date: Thu, 3 Aug 2017 12:11:12 +0200 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Firefox/52.0 Thunderbird/52.2.1 MIME-Version: 1.0 In-Reply-To: <50d1685e-bfa6-02ac-2650-37637745431a@redhat.com> Content-Type: text/plain; charset=utf-8; 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QEMU + -netdev type=tap,ifname=tap,id=net0 -device >> virtio-net-pci,netdev=net0,iommu_platform,disable-modern=off,disable-legacy=on >> >> 2. On VM, I allocate some huge pages and run DPDK testpmd app: >> # echo 4 > /sys/kernel/mm/hugepages/hugepages-524288kB/nr_hugepages >> # ./dpdk/usertools/dpdk-devbind.py -b vfio-pci 0000:00:02.0 >> # ./dpdk/build/app/testpmd -l 0-13 -n 4 -w 0000:00:02.0 -- >> --disable-hw-vlan-filter --disable-rss -i >> EAL: Detected 14 lcore(s) >> EAL: Probing VFIO support... >> EAL: VFIO support initialized >> EAL: PCI device 0000:00:02.0 on NUMA socket -1 >> EAL: probe driver: 1af4:1041 net_virtio >> EAL: using IOMMU type 1 (Type 1) >> EAL: iommu_map_dma vaddr ffff20000000 size 80000000 iova 120000000 >> EAL: Can't write to PCI bar (0) : offset (12) >> EAL: Can't read from PCI bar (0) : offset (12) >> EAL: Can't read from PCI bar (0) : offset (12) >> EAL: Can't write to PCI bar (0) : offset (12) >> EAL: Can't read from PCI bar (0) : offset (12) >> EAL: Can't write to PCI bar (0) : offset (12) >> EAL: Can't read from PCI bar (0) : offset (0) >> EAL: Can't write to PCI bar (0) : offset (4) >> EAL: Can't write to PCI bar (0) : offset (14) >> EAL: Can't write to PCI bar (0) : offset (e) >> EAL: Can't read from PCI bar (0) : offset (c) >> EAL: Requested device 0000:00:02.0 cannot be used >> EAL: No probed ethernet devices >> Interactive-mode selected >> USER1: create a new mbuf pool : n=251456, size=2176, >> socket=0 >> >> When VM uses *4K pages* the same setup works fine. I will work on this >> but please let me know in case you already know what is going on. > > No I did not face that one. I was able to launch testpmd without such > early message. However I assigned an igbvf device to the guest and then > to DPDK. I've never tested your config. > > However as stated in my cover letter at the moment DPDK is not working > for me because of storms of tlbi-on-maps. I intend to work on this as > soon as get some bandwidth, sorry. I found what was the reason of failure. QEMU creates BARs for VIRTIO PCI device. The size of it depends on what is necessary for VIRTIO protocol. In my case the BAR is 16K size which is too small to be mmapable for kernel with 64K pages: vfio_pci_enable() -> vfio_pci_probe_mmaps() -> here guest kernel checks that BAR size is smaller than current PAGE_SIZE and clears VFIO_REGION_INFO_FLAG_MMAP flag which prevents BAR from being mmapped later on. I added -device virtio-net-pci,...,page-per-vq=on to enlarge BAR size to 8M and now testpmd works fine. I wonder how the same setup is working with e.g. Intel or AMD IOMMU. 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H:AM5PR0401MB2545.eurprd04.prod.outlook.com; FPR:; SPF:None; PTR:InfoNoRecords; MX:1; A:1; LANG:en; received-spf: None (protection.outlook.com: nxp.com does not designate permitted sender hosts) spamdiagnosticoutput: 1:99 spamdiagnosticmetadata: NSPM Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-originalarrivaltime: 03 Aug 2017 10:15:39.5724 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM5PR0401MB2546 X-detected-operating-system: by eggs.gnu.org: Windows 7 or 8 [fuzzy] X-Received-From: 40.107.0.71 Subject: Re: [Qemu-arm] [RFC v3 6/8] virtio-iommu: Implement the translation and commands X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 03 Aug 2017 10:15:51 -0000 Hi Eric, > -----Original Message----- > From: Eric Auger [mailto:eric.auger@redhat.com] > Sent: Tuesday, August 01, 2017 3:03 PM > To: eric.auger.pro@gmail.com; eric.auger@redhat.com; > peter.maydell@linaro.org; alex.williamson@redhat.com; mst@redhat.com; > qemu-arm@nongnu.org; qemu-devel@nongnu.org; jean- > philippe.brucker@arm.com > Cc: will.deacon@arm.com; kevin.tian@intel.com; marc.zyngier@arm.com; > christoffer.dall@linaro.org; drjones@redhat.com; wei@redhat.com; > tn@semihalf.com; Bharat Bhushan ; > peterx@redhat.com > Subject: [RFC v3 6/8] virtio-iommu: Implement the translation and > commands >=20 > This patch adds the actual implementation for the translation routine > and the virtio-iommu commands. >=20 > Signed-off-by: Eric Auger >=20 > --- > v2 -> v3: > - init the mutex > - return VIRTIO_IOMMU_S_INVAL is reserved field is not null on > attach/detach commands > - on attach, when the device is already attached to an address space, > detach it first instead of returning an error > - remove nr_devices and use g_tree_ref/unref to destroy the as->mappings > on last device detach > - map/unmap: return NOENT instead of INVAL error if as does not exist > - remove flags argument from attach/detach trace functions >=20 > v1 -> v2: > - fix compilation issue reported by autobuild system > --- > hw/virtio/trace-events | 10 +- > hw/virtio/virtio-iommu.c | 232 > +++++++++++++++++++++++++++++++++++++++++++++-- > 2 files changed, 232 insertions(+), 10 deletions(-) >=20 > diff --git a/hw/virtio/trace-events b/hw/virtio/trace-events > index 341dbdf..8db3d91 100644 > --- a/hw/virtio/trace-events > +++ b/hw/virtio/trace-events > @@ -28,8 +28,14 @@ virtio_balloon_to_target(uint64_t target, uint32_t > num_pages) "balloon target: % >=20 > # hw/virtio/virtio-iommu.c > # > -virtio_iommu_attach(uint32_t as, uint32_t dev, uint32_t flags) "as=3D%d > dev=3D%d flags=3D%d" > -virtio_iommu_detach(uint32_t dev, uint32_t flags) "dev=3D%d flags=3D%d" > +virtio_iommu_attach(uint32_t as, uint32_t dev) "as=3D%d dev=3D%d" > +virtio_iommu_detach(uint32_t dev) "dev=3D%d" > virtio_iommu_map(uint32_t as, uint64_t phys_addr, uint64_t virt_addr, > uint64_t size, uint32_t flags) "as=3D %d phys_addr=3D0x%"PRIx64" > virt_addr=3D0x%"PRIx64" size=3D0x%"PRIx64" flags=3D%d" > virtio_iommu_unmap(uint32_t as, uint64_t virt_addr, uint64_t size, uint3= 2_t > reserved) "as=3D %d virt_addr=3D0x%"PRIx64" size=3D0x%"PRIx64" reserved= =3D%d" > virtio_iommu_translate(const char *name, uint32_t rid, uint64_t iova, in= t > flag) "mr=3D%s rid=3D%d addr=3D0x%"PRIx64" flag=3D%d" > +virtio_iommu_new_asid(uint32_t asid) "Allocate a new asid=3D%d" > +virtio_iommu_new_devid(uint32_t devid) "Allocate a new devid=3D%d" > +virtio_iommu_unmap_left_interval(uint64_t low, uint64_t high, uint64_t > next_low, uint64_t next_high) "Unmap left [0x%"PRIx64",0x%"PRIx64"], > new interval=3D[0x%"PRIx64",0x%"PRIx64"]" > +virtio_iommu_unmap_right_interval(uint64_t low, uint64_t high, uint64_t > next_low, uint64_t next_high) "Unmap right [0x%"PRIx64",0x%"PRIx64"], > new interval=3D[0x%"PRIx64",0x%"PRIx64"]" > +virtio_iommu_unmap_inc_interval(uint64_t low, uint64_t high) "Unmap inc > [0x%"PRIx64",0x%"PRIx64"]" > +virtio_iommu_translate_result(uint64_t virt_addr, uint64_t phys_addr, > uint32_t sid) "0x%"PRIx64" -> 0x%"PRIx64 " for sid=3D%d" > diff --git a/hw/virtio/virtio-iommu.c b/hw/virtio/virtio-iommu.c > index e663d9e..9217587 100644 > --- a/hw/virtio/virtio-iommu.c > +++ b/hw/virtio/virtio-iommu.c > @@ -32,10 +32,36 @@ > #include "hw/virtio/virtio-bus.h" > #include "hw/virtio/virtio-access.h" > #include "hw/virtio/virtio-iommu.h" > +#include "hw/pci/pci_bus.h" > +#include "hw/pci/pci.h" >=20 > /* Max size */ > #define VIOMMU_DEFAULT_QUEUE_SIZE 256 >=20 > +typedef struct viommu_as viommu_as; > + > +typedef struct viommu_mapping { > + uint64_t virt_addr; > + uint64_t phys_addr; > + uint64_t size; > + uint32_t flags; > +} viommu_mapping; > + > +typedef struct viommu_interval { > + uint64_t low; > + uint64_t high; > +} viommu_interval; > + > +typedef struct viommu_dev { > + uint32_t id; > + viommu_as *as; > +} viommu_dev; > + > +struct viommu_as { > + uint32_t id; > + GTree *mappings; > +}; > + > static inline uint16_t virtio_iommu_get_sid(IOMMUDevice *dev) > { > return PCI_BUILD_BDF(pci_bus_num(dev->bus), dev->devfn); > @@ -93,6 +119,29 @@ static void virtio_iommu_init_as(VirtIOIOMMU *s) > } > } >=20 > +static gint interval_cmp(gconstpointer a, gconstpointer b, gpointer > user_data) > +{ > + viommu_interval *inta =3D (viommu_interval *)a; > + viommu_interval *intb =3D (viommu_interval *)b; > + > + if (inta->high <=3D intb->low) { > + return -1; > + } else if (intb->high <=3D inta->low) { > + return 1; > + } else { > + return 0; > + } > +} > + > +static void virtio_iommu_detach_dev(VirtIOIOMMU *s, viommu_dev *dev) > +{ > + viommu_as *as =3D dev->as; > + > + trace_virtio_iommu_detach(dev->id); > + > + g_tree_remove(s->devices, GUINT_TO_POINTER(dev->id)); > + g_tree_unref(as->mappings); > +} >=20 > static int virtio_iommu_attach(VirtIOIOMMU *s, > struct virtio_iommu_req_attach *req) > @@ -100,10 +149,42 @@ static int virtio_iommu_attach(VirtIOIOMMU *s, > uint32_t asid =3D le32_to_cpu(req->address_space); > uint32_t devid =3D le32_to_cpu(req->device); > uint32_t reserved =3D le32_to_cpu(req->reserved); > + viommu_as *as; > + viommu_dev *dev; > + > + trace_virtio_iommu_attach(asid, devid); > + > + if (reserved) { > + return VIRTIO_IOMMU_S_INVAL; > + } > + > + dev =3D g_tree_lookup(s->devices, GUINT_TO_POINTER(devid)); > + if (dev) { > + /* > + * the device is already attached to an address space, > + * detach it first > + */ > + virtio_iommu_detach_dev(s, dev); > + } >=20 > - trace_virtio_iommu_attach(asid, devid, reserved); > + as =3D g_tree_lookup(s->address_spaces, GUINT_TO_POINTER(asid)); > + if (!as) { > + as =3D g_malloc0(sizeof(*as)); > + as->id =3D asid; > + as->mappings =3D g_tree_new_full((GCompareDataFunc)interval_cmp, > + NULL, NULL, (GDestroyNotify)g_f= ree); "key" free function is not provided while "value" free function is provided= (continue ..) > + g_tree_insert(s->address_spaces, GUINT_TO_POINTER(asid), as); > + trace_virtio_iommu_new_asid(asid); > + } >=20 > - return VIRTIO_IOMMU_S_UNSUPP; > + dev =3D g_malloc0(sizeof(*dev)); > + dev->as =3D as; > + dev->id =3D devid; > + trace_virtio_iommu_new_devid(devid); > + g_tree_insert(s->devices, GUINT_TO_POINTER(devid), dev); > + g_tree_ref(as->mappings); > + > + return VIRTIO_IOMMU_S_OK; > } >=20 > static int virtio_iommu_detach(VirtIOIOMMU *s, > @@ -111,10 +192,20 @@ static int virtio_iommu_detach(VirtIOIOMMU *s, > { > uint32_t devid =3D le32_to_cpu(req->device); > uint32_t reserved =3D le32_to_cpu(req->reserved); > + viommu_dev *dev; > + > + if (reserved) { > + return VIRTIO_IOMMU_S_INVAL; > + } > + > + dev =3D g_tree_lookup(s->devices, GUINT_TO_POINTER(devid)); > + if (!dev) { > + return VIRTIO_IOMMU_S_INVAL; > + } >=20 > - trace_virtio_iommu_detach(devid, reserved); > + virtio_iommu_detach_dev(s, dev); >=20 > - return VIRTIO_IOMMU_S_UNSUPP; > + return VIRTIO_IOMMU_S_OK; > } >=20 > static int virtio_iommu_map(VirtIOIOMMU *s, > @@ -125,10 +216,37 @@ static int virtio_iommu_map(VirtIOIOMMU *s, > uint64_t virt_addr =3D le64_to_cpu(req->virt_addr); > uint64_t size =3D le64_to_cpu(req->size); > uint32_t flags =3D le32_to_cpu(req->flags); > + viommu_as *as; > + viommu_interval *interval; > + viommu_mapping *mapping; > + > + interval =3D g_malloc0(sizeof(*interval)); "Key" is allocated here (continue below ...) > + > + interval->low =3D virt_addr; > + interval->high =3D virt_addr + size - 1; > + > + as =3D g_tree_lookup(s->address_spaces, GUINT_TO_POINTER(asid)); > + if (!as) { > + return VIRTIO_IOMMU_S_NOENT; > + } > + > + mapping =3D g_tree_lookup(as->mappings, (gpointer)interval); > + if (mapping) { > + g_free(interval); > + return VIRTIO_IOMMU_S_INVAL; > + } >=20 > trace_virtio_iommu_map(asid, phys_addr, virt_addr, size, flags); >=20 > - return VIRTIO_IOMMU_S_UNSUPP; > + mapping =3D g_malloc0(sizeof(*mapping)); "Value" for b-tree is allocated here (continue below ..) > + mapping->virt_addr =3D virt_addr; > + mapping->phys_addr =3D phys_addr; > + mapping->size =3D size; > + mapping->flags =3D flags; > + > + g_tree_insert(as->mappings, interval, mapping); > + > + return VIRTIO_IOMMU_S_OK; > } >=20 > static int virtio_iommu_unmap(VirtIOIOMMU *s, > @@ -138,10 +256,64 @@ static int virtio_iommu_unmap(VirtIOIOMMU *s, > uint64_t virt_addr =3D le64_to_cpu(req->virt_addr); > uint64_t size =3D le64_to_cpu(req->size); > uint32_t flags =3D le32_to_cpu(req->flags); > + viommu_mapping *mapping; > + viommu_interval interval; > + viommu_as *as; >=20 > trace_virtio_iommu_unmap(asid, virt_addr, size, flags); >=20 > - return VIRTIO_IOMMU_S_UNSUPP; > + as =3D g_tree_lookup(s->address_spaces, GUINT_TO_POINTER(asid)); > + if (!as) { > + error_report("%s: no as", __func__); > + return VIRTIO_IOMMU_S_NOENT; > + } > + interval.low =3D virt_addr; > + interval.high =3D virt_addr + size - 1; > + > + mapping =3D g_tree_lookup(as->mappings, (gpointer)&interval); > + > + while (mapping) { > + viommu_interval current; > + uint64_t low =3D mapping->virt_addr; > + uint64_t high =3D mapping->virt_addr + mapping->size - 1; > + > + current.low =3D low; > + current.high =3D high; > + > + if (low =3D=3D interval.low && size >=3D mapping->size) { > + g_tree_remove(as->mappings, (gpointer)¤t); > + interval.low =3D high + 1; > + trace_virtio_iommu_unmap_left_interval(current.low, current.= high, > + interval.low, interval.high); > + } else if (high =3D=3D interval.high && size >=3D mapping->size)= { > + trace_virtio_iommu_unmap_right_interval(current.low, current= .high, > + interval.low, interval.high); > + g_tree_remove(as->mappings, (gpointer)¤t); > + interval.high =3D low - 1; > + } else if (low > interval.low && high < interval.high) { > + trace_virtio_iommu_unmap_inc_interval(current.low, current.h= igh); > + g_tree_remove(as->mappings, (gpointer)¤t); > + } else { > + break; > + } "value" will be destroyed here but seems like "Key" are not freed. Looks like memory allocated for "key" are never freed. Hopefully I am under= standing it correctly Thanks -Bharat > + if (interval.low >=3D interval.high) { > + return VIRTIO_IOMMU_S_OK; > + } else { > + mapping =3D g_tree_lookup(as->mappings, (gpointer)&interval)= ; > + } > + } > + > + if (mapping) { > + error_report("****** %s: Unmap 0x%"PRIx64" size=3D0x%"PRIx64 > + " from 0x%"PRIx64" size=3D0x%"PRIx64" is not suppor= ted", > + __func__, interval.low, size, > + mapping->virt_addr, mapping->size); > + } else { > + error_report("****** %s: no mapping for > [0x%"PRIx64",0x%"PRIx64"]", > + __func__, interval.low, interval.high); > + } > + > + return VIRTIO_IOMMU_S_INVAL; > } >=20 > #define get_payload_size(req) (\ > @@ -271,19 +443,46 @@ static IOMMUTLBEntry > virtio_iommu_translate(IOMMUMemoryRegion *mr, hwaddr addr, > IOMMUAccessFlags flag) > { > IOMMUDevice *sdev =3D container_of(mr, IOMMUDevice, iommu_mr); > + VirtIOIOMMU *s =3D sdev->viommu; > uint32_t sid; > + viommu_dev *dev; > + viommu_mapping *mapping; > + viommu_interval interval; > + > + interval.low =3D addr; > + interval.high =3D addr + 1; >=20 > IOMMUTLBEntry entry =3D { > .target_as =3D &address_space_memory, > .iova =3D addr, > .translated_addr =3D addr, > - .addr_mask =3D ~(hwaddr)0, > - .perm =3D IOMMU_NONE, > + .addr_mask =3D (1 << 12) - 1, /* TODO */ > + .perm =3D 3, > }; >=20 > sid =3D virtio_iommu_get_sid(sdev); >=20 > trace_virtio_iommu_translate(mr->parent_obj.name, sid, addr, flag); > + qemu_mutex_lock(&s->mutex); > + > + dev =3D g_tree_lookup(s->devices, GUINT_TO_POINTER(sid)); > + if (!dev) { > + /* device cannot be attached to another as */ > + printf("%s sid=3D%d is not known!!\n", __func__, sid); > + goto unlock; > + } > + > + mapping =3D g_tree_lookup(dev->as->mappings, (gpointer)&interval); > + if (!mapping) { > + printf("%s no mapping for 0x%"PRIx64" for sid=3D%d\n", __func__, > + addr, sid); > + goto unlock; > + } > + entry.translated_addr =3D addr - mapping->virt_addr + mapping- > >phys_addr, > + trace_virtio_iommu_translate_result(addr, entry.translated_addr, sid= ); > + > +unlock: > + qemu_mutex_unlock(&s->mutex); > return entry; > } >=20 > @@ -347,6 +546,12 @@ static inline guint as_uint64_hash(gconstpointer v) > return (guint)*(const uint64_t *)v; > } >=20 > +static gint int_cmp(gconstpointer a, gconstpointer b, gpointer user_data= ) > +{ > + uint ua =3D GPOINTER_TO_UINT(a); > + uint ub =3D GPOINTER_TO_UINT(b); > + return (ua > ub) - (ua < ub); > +} >=20 > static void virtio_iommu_device_realize(DeviceState *dev, Error **errp) > { > @@ -362,17 +567,28 @@ static void > virtio_iommu_device_realize(DeviceState *dev, Error **errp) > s->config.page_sizes =3D TARGET_PAGE_MASK; > s->config.input_range.end =3D -1UL; >=20 > + qemu_mutex_init(&s->mutex); > + > memset(s->as_by_bus_num, 0, sizeof(s->as_by_bus_num)); > s->as_by_busptr =3D g_hash_table_new_full(as_uint64_hash, > as_uint64_equal, > g_free, g_free); >=20 > + s->address_spaces =3D g_tree_new_full((GCompareDataFunc)int_cmp, > + NULL, NULL, (GDestroyNotify)g_f= ree); > + s->devices =3D g_tree_new_full((GCompareDataFunc)int_cmp, > + NULL, NULL, (GDestroyNotify)g_f= ree); > + > virtio_iommu_init_as(s); > } >=20 > static void virtio_iommu_device_unrealize(DeviceState *dev, Error **errp= ) > { > VirtIODevice *vdev =3D VIRTIO_DEVICE(dev); > + VirtIOIOMMU *s =3D VIRTIO_IOMMU(dev); > + > + g_tree_destroy(s->address_spaces); > + g_tree_destroy(s->devices); >=20 > virtio_cleanup(vdev); > } > -- > 2.5.5 From MAILER-DAEMON Thu Aug 03 06:48:28 2017 Received: from list by lists.gnu.org with archive (Exim 4.71) id 1ddDg4-0002eA-Cu for mharc-qemu-arm@gnu.org; Thu, 03 Aug 2017 06:48:28 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:45038) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ddDg1-0002bi-5x for qemu-arm@nongnu.org; Thu, 03 Aug 2017 06:48:26 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ddDfz-0001OH-P1 for qemu-arm@nongnu.org; Thu, 03 Aug 2017 06:48:25 -0400 Received: from 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SU8gaW50ZWdyYXRpb24gcGF0Y2hlcy4NCg0KVGhhbmtzDQotQmhhcmF0DQoNCj4gDQo+IFRoYW5r cw0KPiANCj4gRXJpYw0KPiA+DQo+ID4gU29ycnkgSSBkaWRuJ3QgcmVhZCB0aGF0IHdoZW4gcG9z dGluZy4gSXQgaXMgd2hhdCBJIG1lYW4uICBUaGFua3MsDQo+ID4NCg== From MAILER-DAEMON Thu Aug 03 07:15:45 2017 Received: from list by lists.gnu.org with archive (Exim 4.71) id 1ddE6T-00058R-Pu for mharc-qemu-arm@gnu.org; Thu, 03 Aug 2017 07:15:45 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:50989) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ddE6Q-000580-OD for qemu-arm@nongnu.org; Thu, 03 Aug 2017 07:15:43 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ddE6M-0008EC-Qq for qemu-arm@nongnu.org; Thu, 03 Aug 2017 07:15:42 -0400 Received: from mx1.redhat.com ([209.132.183.28]:55746) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1ddE6M-0008Ax-IL; Thu, 03 Aug 2017 07:15:38 -0400 Received: from smtp.corp.redhat.com (int-mx04.intmail.prod.int.phx2.redhat.com [10.5.11.14]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id 391EAC058ECE; Thu, 3 Aug 2017 11:15:35 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mx1.redhat.com 391EAC058ECE Authentication-Results: ext-mx08.extmail.prod.ext.phx2.redhat.com; dmarc=none (p=none dis=none) header.from=redhat.com Authentication-Results: ext-mx08.extmail.prod.ext.phx2.redhat.com; spf=fail smtp.mailfrom=eric.auger@redhat.com Received: from localhost.localdomain (ovpn-116-181.ams2.redhat.com [10.36.116.181]) by smtp.corp.redhat.com (Postfix) with ESMTPS id EDB787D53E; Thu, 3 Aug 2017 11:15:11 +0000 (UTC) To: Tomasz Nowicki , eric.auger.pro@gmail.com, peter.maydell@linaro.org, qemu-arm@nongnu.org, qemu-devel@nongnu.org, alex.williamson@redhat.com, prem.mallappa@gmail.com References: <1499633493-19865-1-git-send-email-eric.auger@redhat.com> <50d1685e-bfa6-02ac-2650-37637745431a@redhat.com> <35467208-4e8f-b944-c247-c049c2301878@caviumnetworks.com> Cc: mohun106@gmail.com, drjones@redhat.com, tcain@qti.qualcomm.com, Radha.Chintakuntla@cavium.com, Sunil.Goutham@cavium.com, mst@redhat.com, jean-philippe.brucker@arm.com, robin.murphy@arm.com, will.deacon@arm.com, "Nair, Jayachandran" , peterx@redhat.com, edgar.iglesias@gmail.com, bharat.bhushan@nxp.com, christoffer.dall@linaro.org From: Auger Eric Message-ID: <8f2b1045-e7f5-a2e1-8a14-54c3d1054e0b@redhat.com> Date: Thu, 3 Aug 2017 13:15:10 +0200 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:45.0) Gecko/20100101 Thunderbird/45.4.0 MIME-Version: 1.0 In-Reply-To: <35467208-4e8f-b944-c247-c049c2301878@caviumnetworks.com> Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: 7bit X-Scanned-By: MIMEDefang 2.79 on 10.5.11.14 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.32]); Thu, 03 Aug 2017 11:15:35 +0000 (UTC) X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.132.183.28 Subject: Re: [Qemu-arm] [Qemu-devel] [RFC v5 0/8] ARM SMMUv3 Emulation Support X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 03 Aug 2017 11:15:43 -0000 Hi Tomasz, On 03/08/2017 12:11, Tomasz Nowicki wrote: > Hi Eric, > > On 01.08.2017 15:07, Auger Eric wrote: >> Hi Tomasz, >> On 01/08/2017 13:01, Tomasz Nowicki wrote: >>> Hi Eric, >>> >>> Just letting you know that I am facing another issue with the following >>> setup: >>> 1. host (4.12 kernel & 64K page) and VM (4.12 kernel & 64K page) >>> 2. QEMU + -netdev type=tap,ifname=tap,id=net0 -device >>> virtio-net-pci,netdev=net0,iommu_platform,disable-modern=off,disable-legacy=on >>> >>> >>> 2. On VM, I allocate some huge pages and run DPDK testpmd app: >>> # echo 4 > /sys/kernel/mm/hugepages/hugepages-524288kB/nr_hugepages >>> # ./dpdk/usertools/dpdk-devbind.py -b vfio-pci 0000:00:02.0 >>> # ./dpdk/build/app/testpmd -l 0-13 -n 4 -w 0000:00:02.0 -- >>> --disable-hw-vlan-filter --disable-rss -i >>> EAL: Detected 14 lcore(s) >>> EAL: Probing VFIO support... >>> EAL: VFIO support initialized >>> EAL: PCI device 0000:00:02.0 on NUMA socket -1 >>> EAL: probe driver: 1af4:1041 net_virtio >>> EAL: using IOMMU type 1 (Type 1) >>> EAL: iommu_map_dma vaddr ffff20000000 size 80000000 iova 120000000 >>> EAL: Can't write to PCI bar (0) : offset (12) >>> EAL: Can't read from PCI bar (0) : offset (12) >>> EAL: Can't read from PCI bar (0) : offset (12) >>> EAL: Can't write to PCI bar (0) : offset (12) >>> EAL: Can't read from PCI bar (0) : offset (12) >>> EAL: Can't write to PCI bar (0) : offset (12) >>> EAL: Can't read from PCI bar (0) : offset (0) >>> EAL: Can't write to PCI bar (0) : offset (4) >>> EAL: Can't write to PCI bar (0) : offset (14) >>> EAL: Can't write to PCI bar (0) : offset (e) >>> EAL: Can't read from PCI bar (0) : offset (c) >>> EAL: Requested device 0000:00:02.0 cannot be used >>> EAL: No probed ethernet devices >>> Interactive-mode selected >>> USER1: create a new mbuf pool : n=251456, size=2176, >>> socket=0 >>> >>> When VM uses *4K pages* the same setup works fine. I will work on this >>> but please let me know in case you already know what is going on. >> >> No I did not face that one. I was able to launch testpmd without such >> early message. However I assigned an igbvf device to the guest and then >> to DPDK. I've never tested your config. >> >> However as stated in my cover letter at the moment DPDK is not working >> for me because of storms of tlbi-on-maps. I intend to work on this as >> soon as get some bandwidth, sorry. > > I found what was the reason of failure. > > QEMU creates BARs for VIRTIO PCI device. The size of it depends on what > is necessary for VIRTIO protocol. In my case the BAR is 16K size which > is too small to be mmapable for kernel with 64K pages: > vfio_pci_enable() -> vfio_pci_probe_mmaps() -> > here guest kernel checks that BAR size is smaller than current PAGE_SIZE > and clears VFIO_REGION_INFO_FLAG_MMAP flag which prevents BAR from being > mmapped later on. I added -device virtio-net-pci,...,page-per-vq=on to > enlarge BAR size to 8M and now testpmd works fine. I wonder how the same > setup is working with e.g. Intel or AMD IOMMU. Hum OK. Yet another thing to investigate! thank you for your efforts and excellent news overall. Preparing a rebase ... Thanks Eric > > Thanks, > Tomasz > From MAILER-DAEMON Thu Aug 03 11:24:19 2017 Received: from list by lists.gnu.org with archive (Exim 4.71) id 1ddHz1-0000gn-AG for mharc-qemu-arm@gnu.org; Thu, 03 Aug 2017 11:24:19 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:34598) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ddHyz-0000gQ-In for qemu-arm@nongnu.org; Thu, 03 Aug 2017 11:24:18 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ddHyu-00080H-MJ for qemu-arm@nongnu.org; Thu, 03 Aug 2017 11:24:17 -0400 Received: from mail-lf0-x242.google.com ([2a00:1450:4010:c07::242]:33361) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ddHyu-0007xk-FU; Thu, 03 Aug 2017 11:24:12 -0400 Received: by mail-lf0-x242.google.com with SMTP id 65so1177397lfa.0; Thu, 03 Aug 2017 08:24:12 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=date:from:to:cc:subject:message-id:references:mime-version :content-disposition:in-reply-to:user-agent; bh=qRPVjyN+wcN6mr8C0GhPONlM0NM8dRkXv/0aM7mxvqA=; b=fdykiQho85X4VdPjwgMllD0pTb/bvHfCq1YlJWwnZ62BfKkbr7VD04jrWgKP4G7zp6 yRhPtXdNzjOwdL1rvItgkYyVQ5C0RB4dBX5ZQ1t8jIxX+7axkuciMkMQ7yGTq7BHwZ1K nXj6iJexphgYbAXXjkAcHLJOiEPsitBYr8FecPEOfcVNjiyc6NaIV/hvoHyitbSzBrzK DQATsUbmb+X7EQj9pc8PWMQSl/fNbsfQzmEyZKCwYJy2lyeA8+MksVKiphQ7E1wwCRaU wQWdeb/Fy3+26lSE1O+k+CGKDAFRJsmaaZXl1Pzq/RX/IEnemtklKrKgyrw0qt3mugUE gtWw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:in-reply-to:user-agent; bh=qRPVjyN+wcN6mr8C0GhPONlM0NM8dRkXv/0aM7mxvqA=; b=gZaOTSWoLaLSPC73Xwrrsp2d4qhKnBCItgpvcouw8gVdCQ/tVyrddmYQogz8w4Rzpo Wkbytm0GduIDkI6NnB/bQbQ7r1CmfPQegZ4Yfuj5nzY1Hq/1tRhpRyDHOaKay+RDkJv3 lI6j9bdbqDTfemOLIfyyOhgwJyNHspaTOasumn7mYiQ72DIWgy73ICdqdQRlK18CU8Tr Axj8OFF8jWmrjcZhAoFv8k0UUQoDhf7dLy9C4ha2g+Z4KzCtapbcZ9HCRkaF0azVkjTT qDi5DAMZbgDJOESao53HQDvjEK4Sok0nRTq0fuNrEz2g4NEblOdjMFS0lSP2x4OgK0kq rDSw== X-Gm-Message-State: AIVw1122CZ1qsjw9QNHCygi2sNgzBviwK+IZKuAwkLdttJwsCMUBJ3AV mRy7Wt733AfbYQ== X-Received: by 10.46.88.65 with SMTP id x1mr968208ljd.162.1501773850063; Thu, 03 Aug 2017 08:24:10 -0700 (PDT) Received: from gmail.com (81-231-233-234-no56.tbcn.telia.com. [81.231.233.234]) by smtp.gmail.com with ESMTPSA id g41sm445234lji.94.2017.08.03.08.24.09 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 03 Aug 2017 08:24:09 -0700 (PDT) Date: Thu, 3 Aug 2017 17:24:08 +0200 From: "Edgar E. Iglesias" To: Peter Maydell Cc: qemu-arm@nongnu.org, qemu-devel@nongnu.org, patches@linaro.org Message-ID: <20170803152408.GO4859@toto> References: <1501692241-23310-1-git-send-email-peter.maydell@linaro.org> <1501692241-23310-7-git-send-email-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1501692241-23310-7-git-send-email-peter.maydell@linaro.org> User-Agent: Mutt/1.5.24 (2015-08-30) X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4010:c07::242 Subject: Re: [Qemu-arm] [PATCH 06/15] target/arm: Remove incorrect comment about MPU_CTRL X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 03 Aug 2017 15:24:18 -0000 On Wed, Aug 02, 2017 at 05:43:52PM +0100, Peter Maydell wrote: > Remove the comment that claims that some MPU_CTRL bits are stored > in sctlr_el[1]. This has never been true since MPU_CTRL was added > in commit 29c483a50607 -- the comment is a leftover from > Michael Davidsaver's original implementation, which I modified > not to use sctlr_el[1]; I forgot to delete the comment then. > > Signed-off-by: Peter Maydell Reviewed-by: Edgar E. Iglesias > --- > target/arm/cpu.h | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/target/arm/cpu.h b/target/arm/cpu.h > index b39d64a..b64474c 100644 > --- a/target/arm/cpu.h > +++ b/target/arm/cpu.h > @@ -416,7 +416,7 @@ typedef struct CPUARMState { > uint32_t dfsr; /* Debug Fault Status Register */ > uint32_t mmfar; /* MemManage Fault Address */ > uint32_t bfar; /* BusFault Address */ > - unsigned mpu_ctrl; /* MPU_CTRL (some bits kept in sctlr_el[1]) */ > + unsigned mpu_ctrl; /* MPU_CTRL */ > int exception; > } v7m; > > -- > 2.7.4 > > From MAILER-DAEMON Thu Aug 03 11:25:50 2017 Received: from list by lists.gnu.org with archive (Exim 4.71) id 1ddI0U-0001YQ-9t for mharc-qemu-arm@gnu.org; Thu, 03 Aug 2017 11:25:50 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:36949) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ddI0S-0001Xs-8r for qemu-arm@nongnu.org; Thu, 03 Aug 2017 11:25:49 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ddI0N-0001vW-EI for qemu-arm@nongnu.org; Thu, 03 Aug 2017 11:25:48 -0400 Received: from mail-lf0-x242.google.com ([2a00:1450:4010:c07::242]:36418) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ddI0N-0001uw-6G; Thu, 03 Aug 2017 11:25:43 -0400 Received: by mail-lf0-x242.google.com with SMTP id t128so1169441lff.3; Thu, 03 Aug 2017 08:25:43 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=date:from:to:cc:subject:message-id:references:mime-version :content-disposition:in-reply-to:user-agent; bh=ZMJDGhoar9DEU2DW/Ja26KkpDX6FHKusfAMYgt8JnP0=; b=FSOtsNtNGW4hgi2wQF19krpIlMiLFRPNyLUgfod2dFAS6njPq/RruWwOAsnZBAvmeP gqzlBLCNKFDveEnmeT3+okvjyInBfOia3uYbNJUEsqmyORCNFX+Jax8UffxzZphUVL7J WwcZ97bC8ScOKRLwHl2kNU4xIySjMT5pltG2WHhOIPB8JmKzaAUFVVq0UJzl1pZJO3HZ TN3r2azokakuubF/qChBw4raEBWXviaffHg1usIVgN+6PsRl9n/oPC5lKmVUrTQkCDgF KGCVdsxeXTsGJw9HzeNQ1/faTugT06IkS/GnE92oDWOq6YqttAsXAVu1ivwvVom5dUh3 /W4A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:in-reply-to:user-agent; bh=ZMJDGhoar9DEU2DW/Ja26KkpDX6FHKusfAMYgt8JnP0=; b=anx/TiChXdR0aqR0vprSwwda8XBfDVSsT8rgjcWNijrvaT1hn29QH4Io+TLws9Um2T uoJYZlK3nixgSKlzAjJzY0tJ3ma2QYWN5shpP7mGGE8qOOMSMIfT5IZiL+t4KKpEFwyF Z1DVA53yt+UK2VycK/C1SktSMwn2UX1qlsPPn+yPdG+IDFzA7EBGMpIUMXWCfdJsgM23 8Wjm2TawCzJ+fSovl9plZmVQVS4aduEomlB+6fXWp0APKuoKv3U5m75SBJXE5W9NgXiy oNd2UTtSAT6Lx7nLSBJkBzUqA/NIJj3Pq1qsCtUW38EjUcljXf2tsj5hrJAXmjIa+Msl cWvQ== X-Gm-Message-State: AHYfb5joQS0COXG99p8oMwNCzHaGj5bohJJZ5M9UxluoqoeOK7nJOItK 6ED4yXb4xUs5kNgs X-Received: by 10.25.77.213 with SMTP id a204mr790413lfb.215.1501773941953; Thu, 03 Aug 2017 08:25:41 -0700 (PDT) Received: from gmail.com (81-231-233-234-no56.tbcn.telia.com. [81.231.233.234]) by smtp.gmail.com with ESMTPSA id t23sm447097ljd.40.2017.08.03.08.25.41 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 03 Aug 2017 08:25:41 -0700 (PDT) Date: Thu, 3 Aug 2017 17:25:40 +0200 From: "Edgar E. Iglesias" To: Peter Maydell Cc: qemu-arm@nongnu.org, qemu-devel@nongnu.org, patches@linaro.org Message-ID: <20170803152540.GP4859@toto> References: <1501692241-23310-1-git-send-email-peter.maydell@linaro.org> <1501692241-23310-8-git-send-email-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1501692241-23310-8-git-send-email-peter.maydell@linaro.org> User-Agent: Mutt/1.5.24 (2015-08-30) X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4010:c07::242 Subject: Re: [Qemu-arm] [Qemu-devel] [PATCH 07/15] target/arm: Fix outdated comment about exception exit X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 03 Aug 2017 15:25:49 -0000 On Wed, Aug 02, 2017 at 05:43:53PM +0100, Peter Maydell wrote: > When we switched our handling of exception exit to detect > the magic addresses at translate time rather than via > a do_unassigned_access hook, we forgot to update a > comment; correct the omission. > > Signed-off-by: Peter Maydell Reviewed-by: Edgar E. Iglesias > --- > target/arm/helper.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/target/arm/helper.c b/target/arm/helper.c > index fd83a21..cb88c66 100644 > --- a/target/arm/helper.c > +++ b/target/arm/helper.c > @@ -6143,7 +6143,7 @@ static void do_v7m_exception_exit(ARMCPU *cpu) > bool rettobase = false; > > /* We can only get here from an EXCP_EXCEPTION_EXIT, and > - * arm_v7m_do_unassigned_access() enforces the architectural rule > + * gen_bx_excret() enforces the architectural rule > * that jumps to magic addresses don't have magic behaviour unless > * we're in Handler mode (compare pseudocode BXWritePC()). > */ > -- > 2.7.4 > > From MAILER-DAEMON Thu Aug 03 11:32:39 2017 Received: from list by lists.gnu.org with archive (Exim 4.71) id 1ddI75-0005FN-Hj for mharc-qemu-arm@gnu.org; Thu, 03 Aug 2017 11:32:39 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:46585) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ddI71-0005Ep-Vz for qemu-arm@nongnu.org; Thu, 03 Aug 2017 11:32:38 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ddI6x-0001bO-9n for qemu-arm@nongnu.org; Thu, 03 Aug 2017 11:32:36 -0400 Received: from mail-lf0-x244.google.com ([2a00:1450:4010:c07::244]:38150) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ddI6w-0001aC-VZ; Thu, 03 Aug 2017 11:32:31 -0400 Received: by mail-lf0-x244.google.com with SMTP id y15so1176361lfd.5; Thu, 03 Aug 2017 08:32:30 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=date:from:to:cc:subject:message-id:references:mime-version :content-disposition:in-reply-to:user-agent; bh=MlPNTbVut5JSW8HtbY64PMySf4rg3bqfxVWrYKYTspg=; b=Lpmjx9i3HPFZUYOlOhcqLq2fPF2PwKlEJEqfxwao6uog/9HTQUbgNR/op9LYPKzRG6 JUMaobbE9jNeRsa5auJWmHLCZtPIqctdCh8QC6nxpdLjcIWptLGzYIS2c9+8ugzM6VoH 5/+htazvr3LC/h663hGqNkws9uXVaB4y6ScXmr0OJptS3Zp8/ncBcNJ+MLYw8rkffnfI /vgE7JrirIL0WPSTWjXr7pQ9VqrUGHRNfhohD4ffk4fAHYE2mBKGwS0Fud9AS4GRLUCC SFMq/8VfAjY4DjCLcuFfvyo09iFb2Bk59uknsHeiXpnCW1Jcv48YpkH1+dvYUb2BmDCA zPAw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:in-reply-to:user-agent; bh=MlPNTbVut5JSW8HtbY64PMySf4rg3bqfxVWrYKYTspg=; b=fSFLNsWoQa8szJbxMUkc1w/3sgo+4IDHBKklsjMGFdgDf7arMUd6AvYPAgCjor7G6r jAxvu4YZ3fXyTn+ei+RQ4g6QvRvM7zpoVL8/xCFYZMod6UbwC/Wgif/LW+BPOPKGACs3 Tlxo7xlzGeRxuHty2RWw1vBd8o2hq7Kv+D+HRQLm2Uar5obGfdMXXENewVS2MhqxNUBS wYZK19djALy3FzocdUaZfHHI47g28HilRb3DT0dcKyOWy9ifit+T9LVNPJ4Rrm54Vupo LA0FvGJwmUrEEQfwFbtC0wS2CkQOktp71YQdR6fuHgXPQ7+jYj87tn6L/9SrnG2qz+i7 ML9w== X-Gm-Message-State: AIVw112E9/3fC3z1uQPRpT8WekXHFk2CuPxXhUrzzfJRppdYxzlF7IMV cFnwmlRX0NPftw== X-Received: by 10.46.25.151 with SMTP id 23mr889439ljz.114.1501774349414; Thu, 03 Aug 2017 08:32:29 -0700 (PDT) Received: from gmail.com (81-231-233-234-no56.tbcn.telia.com. [81.231.233.234]) by smtp.gmail.com with ESMTPSA id i28sm446114ljb.79.2017.08.03.08.32.27 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 03 Aug 2017 08:32:27 -0700 (PDT) Date: Thu, 3 Aug 2017 17:32:27 +0200 From: "Edgar E. Iglesias" To: Peter Maydell Cc: qemu-arm@nongnu.org, qemu-devel@nongnu.org, patches@linaro.org Message-ID: <20170803153227.GQ4859@toto> References: <1501692241-23310-1-git-send-email-peter.maydell@linaro.org> <1501692241-23310-9-git-send-email-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1501692241-23310-9-git-send-email-peter.maydell@linaro.org> User-Agent: Mutt/1.5.24 (2015-08-30) X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4010:c07::244 Subject: Re: [Qemu-arm] [PATCH 08/15] target/arm: Define and use XPSR bit masks X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 03 Aug 2017 15:32:39 -0000 On Wed, Aug 02, 2017 at 05:43:54PM +0100, Peter Maydell wrote: > The M profile XPSR is almost the same format as the A profile CPSR, > but not quite. Define some XPSR_* macros and use them where we > definitely dealing with an XPSR rather than reusing the CPSR ones. > > Signed-off-by: Peter Maydell Reviewed-by: Edgar E. Iglesias > --- > target/arm/cpu.h | 38 ++++++++++++++++++++++++++++---------- > target/arm/helper.c | 15 ++++++++------- > 2 files changed, 36 insertions(+), 17 deletions(-) > > diff --git a/target/arm/cpu.h b/target/arm/cpu.h > index b64474c..1f06de0 100644 > --- a/target/arm/cpu.h > +++ b/target/arm/cpu.h > @@ -883,6 +883,22 @@ void pmccntr_sync(CPUARMState *env); > /* Mask of bits which may be set by exception return copying them from SPSR */ > #define CPSR_ERET_MASK (~CPSR_RESERVED) > > +/* Bit definitions for M profile XPSR. Most are the same as CPSR. */ > +#define XPSR_EXCP 0x1ffU > +#define XPSR_SPREALIGN (1U << 9) /* Only set in exception stack frames */ > +#define XPSR_IT_2_7 CPSR_IT_2_7 > +#define XPSR_GE CPSR_GE > +#define XPSR_SFPA (1U << 20) /* Only set in exception stack frames */ > +#define XPSR_T (1U << 24) /* Not the same as CPSR_T ! */ > +#define XPSR_IT_0_1 CPSR_IT_0_1 > +#define XPSR_Q CPSR_Q > +#define XPSR_V CPSR_V > +#define XPSR_C CPSR_C > +#define XPSR_Z CPSR_Z > +#define XPSR_N CPSR_N > +#define XPSR_NZCV CPSR_NZCV > +#define XPSR_IT CPSR_IT > + > #define TTBCR_N (7U << 0) /* TTBCR.EAE==0 */ > #define TTBCR_T0SZ (7U << 0) /* TTBCR.EAE==1 */ > #define TTBCR_PD0 (1U << 4) > @@ -987,26 +1003,28 @@ static inline uint32_t xpsr_read(CPUARMState *env) > /* Set the xPSR. Note that some bits of mask must be all-set or all-clear. */ > static inline void xpsr_write(CPUARMState *env, uint32_t val, uint32_t mask) > { > - if (mask & CPSR_NZCV) { > - env->ZF = (~val) & CPSR_Z; > + if (mask & XPSR_NZCV) { > + env->ZF = (~val) & XPSR_Z; > env->NF = val; > env->CF = (val >> 29) & 1; > env->VF = (val << 3) & 0x80000000; > } > - if (mask & CPSR_Q) > - env->QF = ((val & CPSR_Q) != 0); > - if (mask & (1 << 24)) > - env->thumb = ((val & (1 << 24)) != 0); > - if (mask & CPSR_IT_0_1) { > + if (mask & XPSR_Q) { > + env->QF = ((val & XPSR_Q) != 0); > + } > + if (mask & XPSR_T) { > + env->thumb = ((val & XPSR_T) != 0); > + } > + if (mask & XPSR_IT_0_1) { > env->condexec_bits &= ~3; > env->condexec_bits |= (val >> 25) & 3; > } > - if (mask & CPSR_IT_2_7) { > + if (mask & XPSR_IT_2_7) { > env->condexec_bits &= 3; > env->condexec_bits |= (val >> 8) & 0xfc; > } > - if (mask & 0x1ff) { > - env->v7m.exception = val & 0x1ff; > + if (mask & XPSR_EXCP) { > + env->v7m.exception = val & XPSR_EXCP; > } > } > > diff --git a/target/arm/helper.c b/target/arm/helper.c > index cb88c66..f087d42 100644 > --- a/target/arm/helper.c > +++ b/target/arm/helper.c > @@ -6119,7 +6119,7 @@ static void v7m_push_stack(ARMCPU *cpu) > /* Align stack pointer if the guest wants that */ > if ((env->regs[13] & 4) && (env->v7m.ccr & R_V7M_CCR_STKALIGN_MASK)) { > env->regs[13] -= 4; > - xpsr |= 0x200; > + xpsr |= XPSR_SPREALIGN; > } > /* Switch to the handler mode. */ > v7m_push(env, xpsr); > @@ -6244,10 +6244,11 @@ static void do_v7m_exception_exit(ARMCPU *cpu) > env->regs[15] &= ~1U; > } > xpsr = v7m_pop(env); > - xpsr_write(env, xpsr, 0xfffffdff); > + xpsr_write(env, xpsr, ~XPSR_SPREALIGN); > /* Undo stack alignment. */ > - if (xpsr & 0x200) > + if (xpsr & XPSR_SPREALIGN) { > env->regs[13] |= 4; > + } > > /* The restored xPSR exception field will be zero if we're > * resuming in Thread mode. If that doesn't match what the > @@ -8693,10 +8694,10 @@ uint32_t HELPER(v7m_mrs)(CPUARMState *env, uint32_t reg) > case 0 ... 7: /* xPSR sub-fields */ > mask = 0; > if ((reg & 1) && el) { > - mask |= 0x000001ff; /* IPSR (unpriv. reads as zero) */ > + mask |= XPSR_EXCP; /* IPSR (unpriv. reads as zero) */ > } > if (!(reg & 4)) { > - mask |= 0xf8000000; /* APSR */ > + mask |= XPSR_NZCV | XPSR_Q; /* APSR */ > } > /* EPSR reads as zero */ > return xpsr_read(env) & mask; > @@ -8754,10 +8755,10 @@ void HELPER(v7m_msr)(CPUARMState *env, uint32_t maskreg, uint32_t val) > uint32_t apsrmask = 0; > > if (mask & 8) { > - apsrmask |= 0xf8000000; /* APSR NZCVQ */ > + apsrmask |= XPSR_NZCV | XPSR_Q; > } > if ((mask & 4) && arm_feature(env, ARM_FEATURE_THUMB_DSP)) { > - apsrmask |= 0x000f0000; /* APSR GE[3:0] */ > + apsrmask |= XPSR_GE; > } > xpsr_write(env, val, apsrmask); > } > -- > 2.7.4 > > From MAILER-DAEMON Thu Aug 03 11:38:11 2017 Received: from list by lists.gnu.org with archive (Exim 4.71) id 1ddICR-0007T9-8W for mharc-qemu-arm@gnu.org; Thu, 03 Aug 2017 11:38:11 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:53619) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ddICO-0007RF-Gt for qemu-arm@nongnu.org; Thu, 03 Aug 2017 11:38:09 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ddICJ-000738-KW for qemu-arm@nongnu.org; Thu, 03 Aug 2017 11:38:08 -0400 Received: from mail-lf0-x243.google.com ([2a00:1450:4010:c07::243]:35399) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ddICJ-00070j-8o; Thu, 03 Aug 2017 11:38:03 -0400 Received: by mail-lf0-x243.google.com with SMTP id w199so1192303lff.2; Thu, 03 Aug 2017 08:38:03 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=date:from:to:cc:subject:message-id:references:mime-version :content-disposition:in-reply-to:user-agent; bh=5/0UdQuuztdAA6F4xprwgDcUA8ZgyC3m3vEzeC4B8GI=; b=iL1ZW4iTfl4IQqYfoGCCdVnyc1C4YxSgQMJBcg+0NNixwLvVuH5D2etABCZuTb9adM txWR41O3WXRv8fJB7K9mvO+oDwXxSYlW4sV7jTaM6V9coIjrTPdMHgFzCy/QegUOkyJo +t8Tw1/BEQTDuaua8jGT2meXYGpOWcGX3KXpQGbYN13qeyyI6xTOq/AW2XhmRhkkg6EU doS11ozy/kGC+u/51qtmDcMy1HM4odsLFM7TNWT0/tMUZawBWiQ75tNNVn73KbnThSJ4 vyGrLUGjfiRK3pgQylonPcRSIe++Hur3c+LnAbpPZm64+TCD4r95/lfVD4GN7KhySqxU CFaQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:in-reply-to:user-agent; bh=5/0UdQuuztdAA6F4xprwgDcUA8ZgyC3m3vEzeC4B8GI=; b=o1FEyiuqUjoQaavHHSE6xnFQhUyuVoT/f/0u1PfHAQnQWjEzPsKFFMwJRHIPwanTDp KI0yPwCHapHXgYiw99Tl+eal8QfKj0v6vu85sQMQqqaZkIRf5Tivs8Tw/6fgPTo0qNmM wZ3JAXxOShTtmQdQQg0MtHbaOF0g0zQpEX+RsOcdwsR4jF3zB36u2ds7D/5yYXX3T8wc S8H3NrEKrBT+sXgfbkwNU44BPPPlKJ3J79tbbMNqqzLHzzjfMnDDnIKmpE9T11tEiqZi PVKeAwjQ0feB5fHTebGf2f6lEM4UzDiWdaEiV/l2jKPy0pOGXsVZdpSYTt55kXmjhE/g zIPA== X-Gm-Message-State: AIVw112nGYu9/ZL5KswHb9llsejgCWH/CBS5TBuoVgQv8nmMDYeLitS8 lXO2HBa3piNmBg== X-Received: by 10.46.76.18 with SMTP id z18mr867003lja.111.1501774681523; Thu, 03 Aug 2017 08:38:01 -0700 (PDT) Received: from gmail.com (81-231-233-234-no56.tbcn.telia.com. [81.231.233.234]) by smtp.gmail.com with ESMTPSA id 9sm450093ljo.89.2017.08.03.08.38.00 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 03 Aug 2017 08:38:00 -0700 (PDT) Date: Thu, 3 Aug 2017 17:38:00 +0200 From: "Edgar E. Iglesias" To: Peter Maydell Cc: qemu-arm@nongnu.org, qemu-devel@nongnu.org, patches@linaro.org Message-ID: <20170803153800.GR4859@toto> References: <1501692241-23310-1-git-send-email-peter.maydell@linaro.org> <1501692241-23310-10-git-send-email-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1501692241-23310-10-git-send-email-peter.maydell@linaro.org> User-Agent: Mutt/1.5.24 (2015-08-30) X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4010:c07::243 Subject: Re: [Qemu-arm] [PATCH 09/15] target/arm: Don't store M profile PRIMASK and FAULTMASK in daif X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 03 Aug 2017 15:38:10 -0000 On Wed, Aug 02, 2017 at 05:43:55PM +0100, Peter Maydell wrote: > We currently store the M profile CPU register state PRIMASK and > FAULTMASK in the daif field of the CPU state in its I and F > bits. This is a legacy from the original implementation, which > tried to share the cpu_exec_interrupt code between A profile > and M profile. We've since separated out the two cases because > they are significantly different, so now there is no common > code between M and A profile which looks at env->daif: all the > uses are either in A-only or M-only code paths. Sharing the state > fields now is just confusing, and will make things awkward > when we implement v8M, where the PRIMASK and FAULTMASK > registers are banked between security states. > > Switch M profile over to using v7m.faultmask and v7m.primask > fields for these registers. > > Signed-off-by: Peter Maydell > --- > hw/intc/armv7m_nvic.c | 4 ++-- > target/arm/cpu.c | 5 ----- > target/arm/cpu.h | 4 +++- > target/arm/helper.c | 18 +++++------------- > target/arm/machine.c | 33 +++++++++++++++++++++++++++++++++ > 5 files changed, 43 insertions(+), 21 deletions(-) > > diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c > index 2e8166a..343bc16 100644 > --- a/hw/intc/armv7m_nvic.c > +++ b/hw/intc/armv7m_nvic.c > @@ -167,9 +167,9 @@ static inline int nvic_exec_prio(NVICState *s) > CPUARMState *env = &s->cpu->env; > int running; > > - if (env->daif & PSTATE_F) { /* FAULTMASK */ > + if (env->v7m.faultmask) { > running = -1; > - } else if (env->daif & PSTATE_I) { /* PRIMASK */ > + } else if (env->v7m.primask) { > running = 0; > } else if (env->v7m.basepri > 0) { > running = env->v7m.basepri & nvic_gprio_mask(s); > diff --git a/target/arm/cpu.c b/target/arm/cpu.c > index 05c038b..b241a63 100644 > --- a/target/arm/cpu.c > +++ b/target/arm/cpu.c > @@ -185,11 +185,6 @@ static void arm_cpu_reset(CPUState *s) > uint32_t initial_pc; /* Loaded from 0x4 */ > uint8_t *rom; > > - /* For M profile we store FAULTMASK and PRIMASK in the > - * PSTATE F and I bits; these are both clear at reset. > - */ > - env->daif &= ~(PSTATE_I | PSTATE_F); > - > /* The reset value of this bit is IMPDEF, but ARM recommends > * that it resets to 1, so QEMU always does that rather than making > * it dependent on CPU model. > diff --git a/target/arm/cpu.h b/target/arm/cpu.h > index 1f06de0..da90b7a 100644 > --- a/target/arm/cpu.h > +++ b/target/arm/cpu.h > @@ -418,6 +418,8 @@ typedef struct CPUARMState { > uint32_t bfar; /* BusFault Address */ > unsigned mpu_ctrl; /* MPU_CTRL */ > int exception; > + uint32_t primask; > + uint32_t faultmask; It seems like these could be booleans? Cheers, Edgar > } v7m; > > /* Information associated with an exception about to be taken: > @@ -2179,7 +2181,7 @@ static inline int cpu_mmu_index(CPUARMState *env, bool ifetch) > * we're in a HardFault or NMI handler. > */ > if ((env->v7m.exception > 0 && env->v7m.exception <= 3) > - || env->daif & PSTATE_F) { > + || env->v7m.faultmask) { > return arm_to_core_mmu_idx(ARMMMUIdx_MNegPri); > } > > diff --git a/target/arm/helper.c b/target/arm/helper.c > index f087d42..b64ddb1 100644 > --- a/target/arm/helper.c > +++ b/target/arm/helper.c > @@ -6172,7 +6172,7 @@ static void do_v7m_exception_exit(ARMCPU *cpu) > > if (env->v7m.exception != ARMV7M_EXCP_NMI) { > /* Auto-clear FAULTMASK on return from other than NMI */ > - env->daif &= ~PSTATE_F; > + env->v7m.faultmask = 0; > } > > switch (armv7m_nvic_complete_irq(env->nvic, env->v7m.exception)) { > @@ -8718,12 +8718,12 @@ uint32_t HELPER(v7m_mrs)(CPUARMState *env, uint32_t reg) > return (env->v7m.control & R_V7M_CONTROL_SPSEL_MASK) ? > env->regs[13] : env->v7m.other_sp; > case 16: /* PRIMASK */ > - return (env->daif & PSTATE_I) != 0; > + return env->v7m.primask; > case 17: /* BASEPRI */ > case 18: /* BASEPRI_MAX */ > return env->v7m.basepri; > case 19: /* FAULTMASK */ > - return (env->daif & PSTATE_F) != 0; > + return env->v7m.faultmask; > default: > qemu_log_mask(LOG_GUEST_ERROR, "Attempt to read unknown special" > " register %d\n", reg); > @@ -8778,11 +8778,7 @@ void HELPER(v7m_msr)(CPUARMState *env, uint32_t maskreg, uint32_t val) > } > break; > case 16: /* PRIMASK */ > - if (val & 1) { > - env->daif |= PSTATE_I; > - } else { > - env->daif &= ~PSTATE_I; > - } > + env->v7m.primask = val & 1; > break; > case 17: /* BASEPRI */ > env->v7m.basepri = val & 0xff; > @@ -8793,11 +8789,7 @@ void HELPER(v7m_msr)(CPUARMState *env, uint32_t maskreg, uint32_t val) > env->v7m.basepri = val; > break; > case 19: /* FAULTMASK */ > - if (val & 1) { > - env->daif |= PSTATE_F; > - } else { > - env->daif &= ~PSTATE_F; > - } > + env->v7m.faultmask = val & 1; > break; > case 20: /* CONTROL */ > /* Writing to the SPSEL bit only has an effect if we are in > diff --git a/target/arm/machine.c b/target/arm/machine.c > index 1f66da4..2fb4b76 100644 > --- a/target/arm/machine.c > +++ b/target/arm/machine.c > @@ -97,6 +97,17 @@ static bool m_needed(void *opaque) > return arm_feature(env, ARM_FEATURE_M); > } > > +static const VMStateDescription vmstate_m_faultmask_primask = { > + .name = "cpu/m/faultmask-primask", > + .version_id = 1, > + .minimum_version_id = 1, > + .fields = (VMStateField[]) { > + VMSTATE_UINT32(env.v7m.faultmask, ARMCPU), > + VMSTATE_UINT32(env.v7m.primask, ARMCPU), > + VMSTATE_END_OF_LIST() > + } > +}; > + > static const VMStateDescription vmstate_m = { > .name = "cpu/m", > .version_id = 4, > @@ -115,6 +126,10 @@ static const VMStateDescription vmstate_m = { > VMSTATE_UINT32(env.v7m.mpu_ctrl, ARMCPU), > VMSTATE_INT32(env.v7m.exception, ARMCPU), > VMSTATE_END_OF_LIST() > + }, > + .subsections = (const VMStateDescription*[]) { > + &vmstate_m_faultmask_primask, > + NULL > } > }; > > @@ -201,6 +216,24 @@ static int get_cpsr(QEMUFile *f, void *opaque, size_t size, > CPUARMState *env = &cpu->env; > uint32_t val = qemu_get_be32(f); > > + if (arm_feature(env, ARM_FEATURE_M)) { > + /* If the I or F bits are set then this is a migration from > + * an old QEMU which still stored the M profile FAULTMASK > + * and PRIMASK in env->daif. Set v7m.faultmask and v7m.primask > + * accordingly, and then clear the bits so they don't confuse > + * cpsr_write(). For a new QEMU, the bits here will always be > + * clear, and the data is transferred using the > + * vmstate_m_faultmask_primask subsection. > + */ > + if (val & CPSR_F) { > + env->v7m.faultmask = 1; > + } > + if (val & CPSR_I) { > + env->v7m.primask = 1; > + } > + val &= ~(CPSR_F | CPSR_I); > + } > + > env->aarch64 = ((val & PSTATE_nRW) == 0); > > if (is_a64(env)) { > -- > 2.7.4 > > From MAILER-DAEMON Thu Aug 03 11:48:23 2017 Received: from list by lists.gnu.org with archive (Exim 4.71) id 1ddIMJ-0005Zd-3C for mharc-qemu-arm@gnu.org; Thu, 03 Aug 2017 11:48:23 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:38528) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ddIMG-0005Yu-4G for qemu-arm@nongnu.org; Thu, 03 Aug 2017 11:48:21 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ddIMC-0002FL-7u for qemu-arm@nongnu.org; Thu, 03 Aug 2017 11:48:20 -0400 Received: from mail-lf0-x244.google.com ([2a00:1450:4010:c07::244]:36689) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ddIMC-0002D7-05; Thu, 03 Aug 2017 11:48:16 -0400 Received: by mail-lf0-x244.google.com with SMTP id t128so1208187lff.3; Thu, 03 Aug 2017 08:48:15 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=date:from:to:cc:subject:message-id:references:mime-version :content-disposition:in-reply-to:user-agent; bh=By+ktitLBlYVzyXwXh0VQbCZw/jIYlHESOXkyjqTLlU=; b=OTQ8CfjN5tkToat7a5RgH8/2mkhHwmqk5NvNABv2mMLQk/oOeOvEZccBQN3qY8TkOq j5rXbpFMytoLG/s+Keu/y1FCNA7n/HQeQKWTGbILrwEc1oIk59SjYl3G5BECghqKvG3X 5wLGg+BjvxjYJrvqM7SnY8/KekEb9r0UQvK3mxoSuYUTdSFwx9H2Ak1npEKCJuXjo8Ge 7Gf1twuSs99d1KXwOO7tYLd7sHdMkJRA7nbtex6mk50jpFgrE6vKIoyyWybrFTC33tDF cI0TwWFLFZK+4w6n+obWcISVd/9GjtIrR8TylBpjcSHFvPYSqIGhLNPVaRk07C1RudY2 qvxg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:in-reply-to:user-agent; bh=By+ktitLBlYVzyXwXh0VQbCZw/jIYlHESOXkyjqTLlU=; b=p3FbK+EXGK2RMH+RtcHFDMFqwxtVccj9G4bXdlnjfAvvunvX2kX2sG/JNMVpXFXE83 p5poZWbuKLrH6OLEgZTehV2RqMSxb7efsdrbXjPs//eBPHhzkI4CC5NQ8prYp8e5tVlK LQLy7WUgtlrj5h+/uvjSKldvqnXydlFDj4393EsBzLGUNh6brGkbkJCFV1r19V9HAdR8 seXwohYROpMY4jM6W2SBLAH2Czgto0pHu9M7GFM/KdhWcw38wBs87kN8IN6cYeD7QPvl GwU3NECwE2MagWxAOjG9USuX961xHOuUg6avgCopa8Y6nnw22I2i1EcDsqL4djFPx+RT h/Yw== X-Gm-Message-State: AHYfb5jtNpvnCWnbkcUqcW7vDUOpwj3ypTwId3jTQkqqEukRep1g3qO5 EV3gshuhXGksOw== X-Received: by 10.25.79.4 with SMTP id d4mr819667lfb.138.1501775294480; Thu, 03 Aug 2017 08:48:14 -0700 (PDT) Received: from gmail.com (81-231-233-234-no56.tbcn.telia.com. [81.231.233.234]) by smtp.gmail.com with ESMTPSA id 79sm464312ljf.8.2017.08.03.08.48.13 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 03 Aug 2017 08:48:13 -0700 (PDT) Date: Thu, 3 Aug 2017 17:48:13 +0200 From: "Edgar E. Iglesias" To: Peter Maydell Cc: qemu-arm@nongnu.org, qemu-devel@nongnu.org, patches@linaro.org Message-ID: <20170803154813.GS4859@toto> References: <1501692241-23310-1-git-send-email-peter.maydell@linaro.org> <1501692241-23310-12-git-send-email-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1501692241-23310-12-git-send-email-peter.maydell@linaro.org> User-Agent: Mutt/1.5.24 (2015-08-30) X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4010:c07::244 Subject: Re: [Qemu-arm] [PATCH 11/15] target/arm: Make arm_cpu_dump_state() handle the M-profile XPSR X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 03 Aug 2017 15:48:21 -0000 On Wed, Aug 02, 2017 at 05:43:57PM +0100, Peter Maydell wrote: > Make the arm_cpu_dump_state() debug logging handle the M-profile XPSR > rather than assuming it's an A-profile CPSR. On M profile the PSR > line of a register dump will now look like this: > > XPSR=41000000 -Z-- T priv-thread > > Signed-off-by: Peter Maydell Reviewed-by: Edgar E. Iglesias > --- > target/arm/translate.c | 58 ++++++++++++++++++++++++++++++++++---------------- > 1 file changed, 40 insertions(+), 18 deletions(-) > > diff --git a/target/arm/translate.c b/target/arm/translate.c > index 3c14cb0..e52a6d7 100644 > --- a/target/arm/translate.c > +++ b/target/arm/translate.c > @@ -12215,8 +12215,6 @@ void arm_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf, > ARMCPU *cpu = ARM_CPU(cs); > CPUARMState *env = &cpu->env; > int i; > - uint32_t psr; > - const char *ns_status; > > if (is_a64(env)) { > aarch64_cpu_dump_state(cs, f, cpu_fprintf, flags); > @@ -12230,24 +12228,48 @@ void arm_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf, > else > cpu_fprintf(f, " "); > } > - psr = cpsr_read(env); > > - if (arm_feature(env, ARM_FEATURE_EL3) && > - (psr & CPSR_M) != ARM_CPU_MODE_MON) { > - ns_status = env->cp15.scr_el3 & SCR_NS ? "NS " : "S "; > + if (arm_feature(env, ARM_FEATURE_M)) { > + uint32_t xpsr = xpsr_read(env); > + const char *mode; > + > + if (xpsr & XPSR_EXCP) { > + mode = "handler"; > + } else { > + if (env->v7m.control & R_V7M_CONTROL_NPRIV_MASK) { > + mode = "unpriv-thread"; > + } else { > + mode = "priv-thread"; > + } > + } > + > + cpu_fprintf(f, "XPSR=%08x %c%c%c%c %c %s\n", > + xpsr, > + xpsr & XPSR_N ? 'N' : '-', > + xpsr & XPSR_Z ? 'Z' : '-', > + xpsr & XPSR_C ? 'C' : '-', > + xpsr & XPSR_V ? 'V' : '-', > + xpsr & XPSR_T ? 'T' : 'A', > + mode); > } else { > - ns_status = ""; > - } > - > - cpu_fprintf(f, "PSR=%08x %c%c%c%c %c %s%s%d\n", > - psr, > - psr & (1 << 31) ? 'N' : '-', > - psr & (1 << 30) ? 'Z' : '-', > - psr & (1 << 29) ? 'C' : '-', > - psr & (1 << 28) ? 'V' : '-', > - psr & CPSR_T ? 'T' : 'A', > - ns_status, > - cpu_mode_names[psr & 0xf], (psr & 0x10) ? 32 : 26); > + uint32_t psr = cpsr_read(env); > + const char *ns_status = ""; > + > + if (arm_feature(env, ARM_FEATURE_EL3) && > + (psr & CPSR_M) != ARM_CPU_MODE_MON) { > + ns_status = env->cp15.scr_el3 & SCR_NS ? "NS " : "S "; > + } > + > + cpu_fprintf(f, "PSR=%08x %c%c%c%c %c %s%s%d\n", > + psr, > + psr & CPSR_N ? 'N' : '-', > + psr & CPSR_Z ? 'Z' : '-', > + psr & CPSR_C ? 'C' : '-', > + psr & CPSR_V ? 'V' : '-', > + psr & CPSR_T ? 'T' : 'A', > + ns_status, > + cpu_mode_names[psr & 0xf], (psr & 0x10) ? 32 : 26); > + } > > if (flags & CPU_DUMP_FPU) { > int numvfpregs = 0; > -- > 2.7.4 > > From MAILER-DAEMON Thu Aug 03 11:49:08 2017 Received: from list by lists.gnu.org with archive (Exim 4.71) id 1ddIN2-0006Ei-PE for mharc-qemu-arm@gnu.org; Thu, 03 Aug 2017 11:49:08 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:39714) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ddIMz-0006BQ-Us for qemu-arm@nongnu.org; Thu, 03 Aug 2017 11:49:06 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ddIMv-0003KT-W6 for qemu-arm@nongnu.org; Thu, 03 Aug 2017 11:49:05 -0400 Received: from mail-lf0-x244.google.com ([2a00:1450:4010:c07::244]:34396) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ddIMv-0003GP-ON; Thu, 03 Aug 2017 11:49:01 -0400 Received: by mail-lf0-x244.google.com with SMTP id o85so1212817lff.1; Thu, 03 Aug 2017 08:49:01 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=date:from:to:cc:subject:message-id:references:mime-version :content-disposition:in-reply-to:user-agent; bh=lnzWeSGhFIGDLgQWVShh3E1O91RmuECl7cVZu4TQu3w=; b=O6p5GCJIKuuD3lndo0zLEw/RqIPnvXj/jPe+Mn2Pb9DNIz43KixqIPPmWX2LWcVnBZ hl/AKMC8eBLCOyCV21ptxHKQ6jtn27aO0cCsNdk+rbV7CnR9YtAccxoJ2nBNIL3O1ZSH 5khof5R1afcMsA84EKsn04oyPsDhvvFCP4G6HyuT7lFn+FPKFvLfef9wJSHVGpv28QJG f6XO+iEJzLdzkyc793OeWL+z48rbWvaJ0ztdZmfrnWp3vAlgNkP3xYvcqi6fg+NjjoK8 XLLM651RCsxkmsronWAIlaFcU4zwL8eud9JNws9ApoUcb1Ls0BW7lDAPXe+2BMJPPluY tb3w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:in-reply-to:user-agent; bh=lnzWeSGhFIGDLgQWVShh3E1O91RmuECl7cVZu4TQu3w=; b=eURa4TxaN32TnWH8k6lV0GmpMFqhobR9F8od1xqWpm9ztgv+O1rI5iPB0rlcYUF7qj fTE/OXWK36rCRF2x2mDZ/4rbLj2v3lgH+P0wlezFJmjK8tJwR723uNb0pgC+PPd5yDmr roRyo2dHogrIKjnQYVtTQ6HtRYQReWXAuYMMpqZCCJ4NZ8ZzInL1eCyzwX9lANA+4s8L abdtkft++9secoo2aRcV6xf9E0JGCNIVajY98X12sJBulOPfWIlUFULPu6z0+noOegpW 3l7yfvGNa62pqfnkCCepV/3tDhcwrAVXPmOtZKie0w30kbZJSkwGjjKgw5i8l2WRjrL9 Z/GA== X-Gm-Message-State: AHYfb5iYyCHkTnSiyLUcIQajL8bnYrT9fNI5KkVjPsPwwGXhK6h4ErED Ux3ObjNOUQaI82Pn X-Received: by 10.25.233.143 with SMTP id j15mr854739lfk.64.1501775340371; Thu, 03 Aug 2017 08:49:00 -0700 (PDT) Received: from gmail.com (81-231-233-234-no56.tbcn.telia.com. [81.231.233.234]) by smtp.gmail.com with ESMTPSA id m12sm6712109lfe.12.2017.08.03.08.48.59 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 03 Aug 2017 08:48:59 -0700 (PDT) Date: Thu, 3 Aug 2017 17:48:59 +0200 From: "Edgar E. Iglesias" To: Peter Maydell Cc: qemu-arm@nongnu.org, qemu-devel@nongnu.org, patches@linaro.org Message-ID: <20170803154859.GT4859@toto> References: <1501692241-23310-1-git-send-email-peter.maydell@linaro.org> <1501692241-23310-13-git-send-email-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1501692241-23310-13-git-send-email-peter.maydell@linaro.org> User-Agent: Mutt/1.5.24 (2015-08-30) X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4010:c07::244 Subject: Re: [Qemu-arm] [PATCH 12/15] target/arm: Don't calculate lr in arm_v7m_cpu_do_interrupt() until needed X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 03 Aug 2017 15:49:07 -0000 On Wed, Aug 02, 2017 at 05:43:58PM +0100, Peter Maydell wrote: > Move the code in arm_v7m_cpu_do_interrupt() that calculates the > magic LR value down to when we're actually going to use it. > Having the calculation and use so far apart makes the code > a little harder to understand than it needs to be. > > Signed-off-by: Peter Maydell Reviewed-by: Edgar E. Iglesias > --- > target/arm/helper.c | 15 ++++++++------- > 1 file changed, 8 insertions(+), 7 deletions(-) > > diff --git a/target/arm/helper.c b/target/arm/helper.c > index b64ddb1..0ecc8f1 100644 > --- a/target/arm/helper.c > +++ b/target/arm/helper.c > @@ -6311,13 +6311,6 @@ void arm_v7m_cpu_do_interrupt(CPUState *cs) > > arm_log_exception(cs->exception_index); > > - lr = 0xfffffff1; > - if (env->v7m.control & R_V7M_CONTROL_SPSEL_MASK) { > - lr |= 4; > - } > - if (env->v7m.exception == 0) > - lr |= 8; > - > /* For exceptions we just mark as pending on the NVIC, and let that > handle it. */ > switch (cs->exception_index) { > @@ -6408,6 +6401,14 @@ void arm_v7m_cpu_do_interrupt(CPUState *cs) > return; /* Never happens. Keep compiler happy. */ > } > > + lr = 0xfffffff1; > + if (env->v7m.control & R_V7M_CONTROL_SPSEL_MASK) { > + lr |= 4; > + } > + if (env->v7m.exception == 0) { > + lr |= 8; > + } > + > v7m_push_stack(cpu); > v7m_exception_taken(cpu, lr); > qemu_log_mask(CPU_LOG_INT, "... as %d\n", env->v7m.exception); > -- > 2.7.4 > > From MAILER-DAEMON Thu Aug 03 11:56:49 2017 Received: from list by lists.gnu.org with archive (Exim 4.71) id 1ddIUT-0002E7-7p for mharc-qemu-arm@gnu.org; Thu, 03 Aug 2017 11:56:49 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:53514) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ddIUP-0002DY-VK for qemu-arm@nongnu.org; Thu, 03 Aug 2017 11:56:47 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ddIUM-0005xQ-SH for qemu-arm@nongnu.org; Thu, 03 Aug 2017 11:56:46 -0400 Received: from mail-lf0-x242.google.com ([2a00:1450:4010:c07::242]:36207) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ddIUM-0005vy-IT; Thu, 03 Aug 2017 11:56:42 -0400 Received: by mail-lf0-x242.google.com with SMTP id t128so1222649lff.3; Thu, 03 Aug 2017 08:56:42 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=date:from:to:cc:subject:message-id:references:mime-version :content-disposition:in-reply-to:user-agent; bh=HzqPeTYjvSqjjI/8bbPL0otBJw3J+uHqOR5CI/MVyOU=; b=BJAKJiFAg1OGNy9DwEt0S0GqyrxbpYzABQ+sNQieqq5TNCCv7dbAg1TMsy4IaW9vud KuEo04Tu0w9RwhRqvPviNhin6FsPWTXz9VdiAbb/omswqIKZwLbsi0vUV6TASOILtPf1 wbXhPa5+/FmLk1KLWHbMp850eqvjR11jY0shxUqPdTNZpJns+O9awIVuwQkGSJQjJG3O Oh7x7H7GeQ+8Zqz8AYxY+9fgY8ABzzgXhq0mUTHssUH62oRyxINuVz0/2TXC4dWGnUmI v629Z5r4jWQUs7E96n1zoLhJna1S15TQOf/fYNQlG/5lfMQ2bA1HLUWAkMWaH1UyNN7R zINw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:in-reply-to:user-agent; bh=HzqPeTYjvSqjjI/8bbPL0otBJw3J+uHqOR5CI/MVyOU=; b=o3duFkvyL+qw3SwCO5MT/9nnPkxXGnH/GrTvzrm7Ir1RvjWzWmlItp17pI1QwkLl6K 8ePo6wS4h2+Zs48XQggMU0di4jVdyJ08wmz/Y4UawCR4/cIEcdpRbEWSr6uVyqz3L0jM VVZoPEywXgbQSfJbDSFnYNj7QvTob6EXCIBda5j7IUwKmQD1qspRl72Qim0jCrrcSkVB QQ0qgzDOmy9co71JV0M43UZm0oXT9BGueksw6ZwVKbFjvRQBkdbmjTjmyaqwAVvHkr1a Ip87TWTlr3Cq1y1wRNh02ReclTuVB+jCH5DI/DeBtDYUIBEoEwpQ3k9SBUpFplL/hhQe g3Tg== X-Gm-Message-State: AIVw112zoP4lKEIof2+Z/ajMO30YGVzUBahLYYFxenFXW05uMpArTwXn 1UTN/c58QMUTMQ== X-Received: by 10.46.69.9 with SMTP id s9mr899178lja.141.1501775800897; Thu, 03 Aug 2017 08:56:40 -0700 (PDT) Received: from gmail.com (81-231-233-234-no56.tbcn.telia.com. [81.231.233.234]) by smtp.gmail.com with ESMTPSA id q192sm667428lfe.85.2017.08.03.08.56.39 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 03 Aug 2017 08:56:40 -0700 (PDT) Date: Thu, 3 Aug 2017 17:56:39 +0200 From: "Edgar E. Iglesias" To: Peter Maydell Cc: qemu-arm@nongnu.org, qemu-devel@nongnu.org, patches@linaro.org Message-ID: <20170803155639.GU4859@toto> References: <1501692241-23310-1-git-send-email-peter.maydell@linaro.org> <1501692241-23310-14-git-send-email-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1501692241-23310-14-git-send-email-peter.maydell@linaro.org> User-Agent: Mutt/1.5.24 (2015-08-30) X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4010:c07::242 Subject: Re: [Qemu-arm] [PATCH 13/15] target/arm: Create and use new function arm_v7m_is_handler_mode() X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 03 Aug 2017 15:56:47 -0000 On Wed, Aug 02, 2017 at 05:43:59PM +0100, Peter Maydell wrote: > Add a utility function for testing whether the CPU is in Handler > mode; this is just a check whether v7m.exception is non-zero, but > we do it in several places and it makes the code a bit easier > to read to not have to mentally figure out what the test is testing. > > Signed-off-by: Peter Maydell > --- > target/arm/cpu.h | 10 ++++++++-- > target/arm/helper.c | 8 ++++---- > 2 files changed, 12 insertions(+), 6 deletions(-) > > diff --git a/target/arm/cpu.h b/target/arm/cpu.h > index da90b7a..a3b4b78 100644 > --- a/target/arm/cpu.h > +++ b/target/arm/cpu.h > @@ -1630,13 +1630,19 @@ static inline int arm_highest_el(CPUARMState *env) > return 1; > } > > +/* Return true if a v7M CPU is in Handler mode */ > +static inline bool arm_v7m_is_handler_mode(CPUARMState *env) > +{ > + return env->v7m.exception != 0; The != 0 shouldn't be needed when you return a bool... Either way: Reviewed-by: Edgar E. Iglesias > +} > + > /* Return the current Exception Level (as per ARMv8; note that this differs > * from the ARMv7 Privilege Level). > */ > static inline int arm_current_el(CPUARMState *env) > { > if (arm_feature(env, ARM_FEATURE_M)) { > - return !((env->v7m.exception == 0) && (env->v7m.control & 1)); > + return arm_v7m_is_handler_mode(env) || !(env->v7m.control & 1); > } > > if (is_a64(env)) { > @@ -2636,7 +2642,7 @@ static inline void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc, > } > *flags |= fp_exception_el(env) << ARM_TBFLAG_FPEXC_EL_SHIFT; > > - if (env->v7m.exception != 0) { > + if (arm_v7m_is_handler_mode(env)) { > *flags |= ARM_TBFLAG_HANDLER_MASK; > } > > diff --git a/target/arm/helper.c b/target/arm/helper.c > index 0ecc8f1..7920153 100644 > --- a/target/arm/helper.c > +++ b/target/arm/helper.c > @@ -6147,7 +6147,7 @@ static void do_v7m_exception_exit(ARMCPU *cpu) > * that jumps to magic addresses don't have magic behaviour unless > * we're in Handler mode (compare pseudocode BXWritePC()). > */ > - assert(env->v7m.exception != 0); > + assert(arm_v7m_is_handler_mode(env)); > > /* In the spec pseudocode ExceptionReturn() is called directly > * from BXWritePC() and gets the full target PC value including > @@ -6254,7 +6254,7 @@ static void do_v7m_exception_exit(ARMCPU *cpu) > * resuming in Thread mode. If that doesn't match what the > * exception return type specified then this is a UsageFault. > */ > - if (return_to_handler == (env->v7m.exception == 0)) { > + if (return_to_handler != arm_v7m_is_handler_mode(env)) { > /* Take an INVPC UsageFault by pushing the stack again. */ > armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE); > env->v7m.cfsr |= R_V7M_CFSR_INVPC_MASK; > @@ -6405,7 +6405,7 @@ void arm_v7m_cpu_do_interrupt(CPUState *cs) > if (env->v7m.control & R_V7M_CONTROL_SPSEL_MASK) { > lr |= 4; > } > - if (env->v7m.exception == 0) { > + if (!arm_v7m_is_handler_mode(env)) { > lr |= 8; > } > > @@ -8798,7 +8798,7 @@ void HELPER(v7m_msr)(CPUARMState *env, uint32_t maskreg, uint32_t val) > * switch_v7m_sp() deals with updating the SPSEL bit in > * env->v7m.control, so we only need update the others. > */ > - if (env->v7m.exception == 0) { > + if (!arm_v7m_is_handler_mode(env)) { > switch_v7m_sp(env, (val & R_V7M_CONTROL_SPSEL_MASK) != 0); > } > env->v7m.control &= ~R_V7M_CONTROL_NPRIV_MASK; > -- > 2.7.4 > > From MAILER-DAEMON Thu Aug 03 11:57:18 2017 Received: from list by lists.gnu.org with archive (Exim 4.71) id 1ddIUw-0002Xm-3t for mharc-qemu-arm@gnu.org; Thu, 03 Aug 2017 11:57:18 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:54289) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ddIUs-0002W1-Si for qemu-arm@nongnu.org; Thu, 03 Aug 2017 11:57:16 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ddIUp-0006dW-Pp for qemu-arm@nongnu.org; Thu, 03 Aug 2017 11:57:14 -0400 Received: from mail-lf0-x241.google.com ([2a00:1450:4010:c07::241]:33180) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ddIUp-0006cb-Im; Thu, 03 Aug 2017 11:57:11 -0400 Received: by mail-lf0-x241.google.com with SMTP id 65so1234155lfa.0; Thu, 03 Aug 2017 08:57:11 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=date:from:to:cc:subject:message-id:references:mime-version :content-disposition:in-reply-to:user-agent; bh=tobNEWmmw6fNjwPGxA/dh8zCge+Am/OxYR7Gzb2ReuE=; b=ETOGVuoaxi650+s6A2HJlxu4mG+vidak2uZwgzCBP2j7bI4PUtW7RWAgpv3SYleiUh kcwQbZeljKXVT++6+5A9vjmZY2xpyaHJt8WPA6P9otBOBndp8IcRUFYvwCBvvi/O8BCO 5rrCpeV1ewjbn9VR4p7L/n4e8aEADGYZSlsV5zlTPZKcaZPBzAofec3TP7JTD+Ca7G+I DoWe4uc174gPfpGMaKGWF25/rMV0gjiBY0f5X1T2PoNaytxzgi+NQi36KiZrGQ01iNHc VvUt0Tn+RE8xrQSIbyDNVgeQYfLNTMpb09oAqNSeDDeMZZLu3pNjRK8bGTcWyKTzRvqC Cyow== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:in-reply-to:user-agent; bh=tobNEWmmw6fNjwPGxA/dh8zCge+Am/OxYR7Gzb2ReuE=; b=dkOOvYk88kQk3fhNpFytuwle3pC97Qj0AVquuKeaK2pqaCiwIzw4lP7MDcd15COB51 lJnIHyq5omFsO/bucYGPP0NYYrROrnjxucW1f5owEmUUp8KVZiak0uX1l6ftVoj9sML5 qliP/kBWSWDih/GMCgPPO0wvLqlsormmg+EUu9o0J8x9TXaISUodwbzL17Jfd/0+yOev +NtY/DZ0xlM88hszrv+17PxATZ1mdUUiCNGE729PQcFPcjjHOhqQrs3SLuhXO2RWFCpb vyWJAzACgKzOgPU4uqNOZXHadsKI0kEm9VrHFsgvPexZRsJX2aIbwQBI6YTvEHnELZXV u8Jg== X-Gm-Message-State: AIVw110sg2kXUzG+96hcmRQIlxMB9xbWnoqCrs4HV+R8NKmNPpabILUZ 4317lhW0kQ07+Q== X-Received: by 10.46.8.74 with SMTP id g10mr917917ljd.194.1501775830118; Thu, 03 Aug 2017 08:57:10 -0700 (PDT) Received: from gmail.com (81-231-233-234-no56.tbcn.telia.com. [81.231.233.234]) by smtp.gmail.com with ESMTPSA id s186sm458201lja.17.2017.08.03.08.57.09 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 03 Aug 2017 08:57:09 -0700 (PDT) Date: Thu, 3 Aug 2017 17:57:08 +0200 From: "Edgar E. Iglesias" To: Peter Maydell Cc: qemu-arm@nongnu.org, qemu-devel@nongnu.org, patches@linaro.org Message-ID: <20170803155708.GV4859@toto> References: <1501692241-23310-1-git-send-email-peter.maydell@linaro.org> <1501692241-23310-15-git-send-email-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1501692241-23310-15-git-send-email-peter.maydell@linaro.org> User-Agent: Mutt/1.5.24 (2015-08-30) X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4010:c07::241 Subject: Re: [Qemu-arm] [PATCH 14/15] armv7m_nvic.h: Move from include/hw/arm to include/hw/intc X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 03 Aug 2017 15:57:17 -0000 On Wed, Aug 02, 2017 at 05:44:00PM +0100, Peter Maydell wrote: > The armv7m_nvic.h header file was accidentally placed in > include/hw/arm; move it to include/hw/intc to match where > its corresponding .c file lives. > > Signed-off-by: Peter Maydell Reviewed-by: Edgar E. Iglesias > --- > hw/intc/armv7m_nvic.c | 2 +- > include/hw/arm/armv7m.h | 2 +- > include/hw/{arm => intc}/armv7m_nvic.h | 0 > 3 files changed, 2 insertions(+), 2 deletions(-) > rename include/hw/{arm => intc}/armv7m_nvic.h (100%) > > diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c > index 343bc16..5a18025 100644 > --- a/hw/intc/armv7m_nvic.c > +++ b/hw/intc/armv7m_nvic.c > @@ -17,7 +17,7 @@ > #include "hw/sysbus.h" > #include "qemu/timer.h" > #include "hw/arm/arm.h" > -#include "hw/arm/armv7m_nvic.h" > +#include "hw/intc/armv7m_nvic.h" > #include "target/arm/cpu.h" > #include "exec/exec-all.h" > #include "qemu/log.h" > diff --git a/include/hw/arm/armv7m.h b/include/hw/arm/armv7m.h > index a9b3f2a..10eb058 100644 > --- a/include/hw/arm/armv7m.h > +++ b/include/hw/arm/armv7m.h > @@ -11,7 +11,7 @@ > #define HW_ARM_ARMV7M_H > > #include "hw/sysbus.h" > -#include "hw/arm/armv7m_nvic.h" > +#include "hw/intc/armv7m_nvic.h" > > #define TYPE_BITBAND "ARM,bitband-memory" > #define BITBAND(obj) OBJECT_CHECK(BitBandState, (obj), TYPE_BITBAND) > diff --git a/include/hw/arm/armv7m_nvic.h b/include/hw/intc/armv7m_nvic.h > similarity index 100% > rename from include/hw/arm/armv7m_nvic.h > rename to include/hw/intc/armv7m_nvic.h > -- > 2.7.4 > > From MAILER-DAEMON Thu Aug 03 11:59:52 2017 Received: from list by lists.gnu.org with archive (Exim 4.71) id 1ddIXQ-0004et-Jn for mharc-qemu-arm@gnu.org; Thu, 03 Aug 2017 11:59:52 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:58627) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ddIXM-0004bj-8F for qemu-arm@nongnu.org; Thu, 03 Aug 2017 11:59:49 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ddIXJ-0001dH-0g for qemu-arm@nongnu.org; Thu, 03 Aug 2017 11:59:48 -0400 Received: from mail-lf0-x242.google.com ([2a00:1450:4010:c07::242]:36335) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ddIXI-0001bh-KW; Thu, 03 Aug 2017 11:59:44 -0400 Received: by mail-lf0-x242.google.com with SMTP id t128so1227512lff.3; Thu, 03 Aug 2017 08:59:44 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=date:from:to:cc:subject:message-id:references:mime-version :content-disposition:in-reply-to:user-agent; bh=taFnCuvqNyvEBRXjdbMXVf8MHpN7OnJaeiXURjllD78=; b=qN6+owA9Jh0NzCX0T2q6X6I0yOYi+fmkRqLHFJabmZ5uJzzyMV6xcLQEldGl/Vj6UZ mNs8e8pvf4rZL8hzRs5KUwb2sq5O9j7wUYkmS1lx1EqlEcFVOj1YodODtcZryfz8wN9C Pb7OamHLbh9HM2KKsai3sQIjoUF9VKrSmj9ORkYYdZVkWkCmIGnQtF3OvrqLAgk46/IR MvjYlXLKd8y6R2AJLsLMyMWJ2y5ZRSlNW5ON5NpS4h+aGnmqv6OQ9E9URujTrHJH0XnW JfjTzoaYDmGD7T0rGIyJa1PIMTNdfQWROB+VcFPBSGxOx4qDOGWiM+x742MJoQ3uRW4i sEvg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:in-reply-to:user-agent; bh=taFnCuvqNyvEBRXjdbMXVf8MHpN7OnJaeiXURjllD78=; b=mT/1awpVtovJMUS2tlxZR0OmvIT+VxHb6c6LYSMY9HnZljwKw7afxPnDm6/sLt/xVb lexR5nIYyuYDEPzt0brTPFIPAsyEecf3XkoO1TFaM6cdUXAZchu+7Q8O1MSM4MNPUc3S 3MurO0MHp8RJXwhnMX0aNjUNDpXLk1O1AH7263kcLg9PctmpR+2Ab3o7oU0TZihg/tqi WQ7YdSueIF2A0b26yy828kQtOzmfuPflnOXKJV7oXS0uYlM7tmdr+BGVm9M+STkS/d5j 5Cynvzm9Oi5+Ofqawl1UvD6ZHlC3ey09Hfy7GKw0ZcIW5wr8juyGc4naQnQQyJxJFsKD kTXA== X-Gm-Message-State: AHYfb5juqaVCv8MoUqtlrR8F6kArx2ZTkIKqvF5dY5r0yoQE0qo3YH2l QJWJeAGK0DyutA== X-Received: by 10.25.18.151 with SMTP id 23mr724515lfs.95.1501775983126; Thu, 03 Aug 2017 08:59:43 -0700 (PDT) Received: from gmail.com (81-231-233-234-no56.tbcn.telia.com. [81.231.233.234]) by smtp.gmail.com with ESMTPSA id 14sm455554ljv.62.2017.08.03.08.59.42 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 03 Aug 2017 08:59:42 -0700 (PDT) Date: Thu, 3 Aug 2017 17:59:41 +0200 From: "Edgar E. Iglesias" To: Peter Maydell Cc: qemu-arm@nongnu.org, qemu-devel@nongnu.org, patches@linaro.org Message-ID: <20170803155941.GW4859@toto> References: <1501692241-23310-1-git-send-email-peter.maydell@linaro.org> <1501692241-23310-16-git-send-email-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1501692241-23310-16-git-send-email-peter.maydell@linaro.org> User-Agent: Mutt/1.5.24 (2015-08-30) X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4010:c07::242 Subject: Re: [Qemu-arm] [PATCH 15/15] nvic: Implement "user accesses BusFault" SCS region behaviour X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 03 Aug 2017 15:59:49 -0000 On Wed, Aug 02, 2017 at 05:44:01PM +0100, Peter Maydell wrote: > The ARMv7M architecture specifies that most of the addresses in the > PPB region (which includes the NVIC, systick and system registers) > are not accessible to unprivileged accesses, which should > BusFault with a few exceptions: > * the STIR is configurably user-accessible > * the ITM (which we don't implement at all) is always > user-accessible > > Implement this by switching the register access functions > to the _with_attrs scheme that lets us distinguish user > mode accesses. > > This allows us to pull the handling of the CCR.USERSETMPEND > flag up to the level where we can make it generate a BusFault > as it should for non-permitted accesses. > > Note that until the core ARM CPU code implements turning > MEMTX_ERROR into a BusFault the registers will continue to > act as RAZ/WI to user accesses. > > Signed-off-by: Peter Maydell Reviewed-by: Edgar E. Iglesias > --- > hw/intc/armv7m_nvic.c | 58 ++++++++++++++++++++++++++++++++++++--------------- > 1 file changed, 41 insertions(+), 17 deletions(-) > > diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c > index 5a18025..bbfe2d5 100644 > --- a/hw/intc/armv7m_nvic.c > +++ b/hw/intc/armv7m_nvic.c > @@ -733,11 +733,8 @@ static void nvic_writel(NVICState *s, uint32_t offset, uint32_t value) > } > case 0xf00: /* Software Triggered Interrupt Register */ > { > - /* user mode can only write to STIR if CCR.USERSETMPEND permits it */ > int excnum = (value & 0x1ff) + NVIC_FIRST_IRQ; > - if (excnum < s->num_irq && > - (arm_current_el(&cpu->env) || > - (cpu->env.v7m.ccr & R_V7M_CCR_USERSETMPEND_MASK))) { > + if (excnum < s->num_irq) { > armv7m_nvic_set_pending(s, excnum); > } > break; > @@ -748,14 +745,32 @@ static void nvic_writel(NVICState *s, uint32_t offset, uint32_t value) > } > } > > -static uint64_t nvic_sysreg_read(void *opaque, hwaddr addr, > - unsigned size) > +static bool nvic_user_access_ok(NVICState *s, hwaddr offset) > +{ > + /* Return true if unprivileged access to this register is permitted. */ > + switch (offset) { > + case 0xf00: /* STIR: accessible only if CCR.USERSETMPEND permits */ > + return s->cpu->env.v7m.ccr & R_V7M_CCR_USERSETMPEND_MASK; > + default: > + /* All other user accesses cause a BusFault unconditionally */ > + return false; > + } > +} > + > +static MemTxResult nvic_sysreg_read(void *opaque, hwaddr addr, > + uint64_t *data, unsigned size, > + MemTxAttrs attrs) > { > NVICState *s = (NVICState *)opaque; > uint32_t offset = addr; > unsigned i, startvec, end; > uint32_t val; > > + if (attrs.user && !nvic_user_access_ok(s, addr)) { > + /* Generate BusFault for unprivileged accesses */ > + return MEMTX_ERROR; > + } > + > switch (offset) { > /* reads of set and clear both return the status */ > case 0x100 ... 0x13f: /* NVIC Set enable */ > @@ -826,11 +841,13 @@ static uint64_t nvic_sysreg_read(void *opaque, hwaddr addr, > } > > trace_nvic_sysreg_read(addr, val, size); > - return val; > + *data = val; > + return MEMTX_OK; > } > > -static void nvic_sysreg_write(void *opaque, hwaddr addr, > - uint64_t value, unsigned size) > +static MemTxResult nvic_sysreg_write(void *opaque, hwaddr addr, > + uint64_t value, unsigned size, > + MemTxAttrs attrs) > { > NVICState *s = (NVICState *)opaque; > uint32_t offset = addr; > @@ -839,6 +856,11 @@ static void nvic_sysreg_write(void *opaque, hwaddr addr, > > trace_nvic_sysreg_write(addr, value, size); > > + if (attrs.user && !nvic_user_access_ok(s, addr)) { > + /* Generate BusFault for unprivileged accesses */ > + return MEMTX_ERROR; > + } > + > switch (offset) { > case 0x100 ... 0x13f: /* NVIC Set enable */ > offset += 0x80; > @@ -853,7 +875,7 @@ static void nvic_sysreg_write(void *opaque, hwaddr addr, > } > } > nvic_irq_update(s); > - return; > + return MEMTX_OK; > case 0x200 ... 0x23f: /* NVIC Set pend */ > /* the special logic in armv7m_nvic_set_pending() > * is not needed since IRQs are never escalated > @@ -870,9 +892,9 @@ static void nvic_sysreg_write(void *opaque, hwaddr addr, > } > } > nvic_irq_update(s); > - return; > + return MEMTX_OK; > case 0x300 ... 0x33f: /* NVIC Active */ > - return; /* R/O */ > + return MEMTX_OK; /* R/O */ > case 0x400 ... 0x5ef: /* NVIC Priority */ > startvec = 8 * (offset - 0x400) + NVIC_FIRST_IRQ; /* vector # */ > > @@ -880,26 +902,28 @@ static void nvic_sysreg_write(void *opaque, hwaddr addr, > set_prio(s, startvec + i, (value >> (i * 8)) & 0xff); > } > nvic_irq_update(s); > - return; > + return MEMTX_OK; > case 0xd18 ... 0xd23: /* System Handler Priority. */ > for (i = 0; i < size; i++) { > unsigned hdlidx = (offset - 0xd14) + i; > set_prio(s, hdlidx, (value >> (i * 8)) & 0xff); > } > nvic_irq_update(s); > - return; > + return MEMTX_OK; > } > if (size == 4) { > nvic_writel(s, offset, value); > - return; > + return MEMTX_OK; > } > qemu_log_mask(LOG_GUEST_ERROR, > "NVIC: Bad write of size %d at offset 0x%x\n", size, offset); > + /* This is UNPREDICTABLE; treat as RAZ/WI */ > + return MEMTX_OK; > } > > static const MemoryRegionOps nvic_sysreg_ops = { > - .read = nvic_sysreg_read, > - .write = nvic_sysreg_write, > + .read_with_attrs = nvic_sysreg_read, > + .write_with_attrs = nvic_sysreg_write, > .endianness = DEVICE_NATIVE_ENDIAN, > }; > > -- > 2.7.4 > > From MAILER-DAEMON Thu Aug 03 16:28:41 2017 Received: from list by lists.gnu.org with archive (Exim 4.71) id 1ddMjZ-0007vY-R5 for mharc-qemu-arm@gnu.org; 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[97.126.108.236]) by smtp.googlemail.com with ESMTPSA id u12sm13449486pgq.24.2017.08.03.13.28.29 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 03 Aug 2017 13:28:29 -0700 (PDT) Sender: Richard Henderson To: Peter Maydell , qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: patches@linaro.org References: <1501692241-23310-1-git-send-email-peter.maydell@linaro.org> <1501692241-23310-3-git-send-email-peter.maydell@linaro.org> From: Richard Henderson Message-ID: <3f6ee028-b7f9-fbe0-1aea-eb1e6faab5a3@twiddle.net> Date: Thu, 3 Aug 2017 13:28:28 -0700 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.2.1 MIME-Version: 1.0 In-Reply-To: <1501692241-23310-3-git-send-email-peter.maydell@linaro.org> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 7bit X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::241 Subject: Re: [Qemu-arm] [Qemu-devel] [PATCH 02/15] target/arm: Don't trap WFI/WFE for M profile X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 03 Aug 2017 20:28:40 -0000 On 08/02/2017 09:43 AM, Peter Maydell wrote: > M profile cores can never trap on WFI or WFE instructions. Check for > M profile in check_wfx_trap() to ensure this. > > The existing code will do the right thing for v7M cores because > the hcr_el2 and scr_el3 registers will be all-zeroes and so we > won't attempt to trap, but when we start setting ARM_FEATURE_V8 > for v8M cores the v8A handling of SCTLR.nTWE and .nTWI will not > give the right results. > > Signed-off-by: Peter Maydell > --- > target/arm/op_helper.c | 5 +++++ > 1 file changed, 5 insertions(+) Reviewed-by: Richard Henderson While looking at this, I think there's an error in helper_wfi. The early exit for cpu_has_work should happen after the exception check. r~ From MAILER-DAEMON Thu Aug 03 16:33:43 2017 Received: from list by lists.gnu.org with archive (Exim 4.71) id 1ddMoQ-000282-TO for mharc-qemu-arm@gnu.org; Thu, 03 Aug 2017 16:33:42 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:46315) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ddMoN-00026w-Dp for qemu-arm@nongnu.org; Thu, 03 Aug 2017 16:33:41 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ddMoM-0002fm-Hx for qemu-arm@nongnu.org; Thu, 03 Aug 2017 16:33:39 -0400 Received: from mail-pg0-x243.google.com ([2607:f8b0:400e:c05::243]:36755) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ddMoH-0002Zi-QJ; Thu, 03 Aug 2017 16:33:34 -0400 Received: by mail-pg0-x243.google.com with SMTP id y129so2441734pgy.3; Thu, 03 Aug 2017 13:33:33 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:subject:to:cc:references:from:message-id:date:user-agent :mime-version:in-reply-to:content-language:content-transfer-encoding; bh=YK2v5DR00+ngRt3QY+j0TS+6s14qIbF8z9TqIIpH7nI=; b=GlyXjNhtx/ka3W/BdB3PpRsZx7bWmS0adVH8Vdt/f/OAVOJbsgPo3LDHSGdj1djC9y w+Vj1BMqBbUmA14goZTsr/dK/oYNJUdxg1bFqISMUdEeYGPy7vNEAHGZcZoc11CG+Wwk KCViUTrp0bPkc9Lqq4GA6JTyhE5/3PStU4k9XL3gk/uDSKNH6r4jeN7f4OA6eHICux7y AWxsComSAIhwoYGvhd6Da2JXqQ0rGPUGSqGVJYLXM1JYQXwsr5DDrfEb+286Ypze81dn KowCCyPHzq9BqPAEV7qDIZpIBm3zWF7o4TfV22GjDtnF9yxSWovQm4jn2Wu/kpUXiMgc KQOA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:subject:to:cc:references:from:message-id :date:user-agent:mime-version:in-reply-to:content-language :content-transfer-encoding; bh=YK2v5DR00+ngRt3QY+j0TS+6s14qIbF8z9TqIIpH7nI=; b=uiDV8hCur/EB1LQmKoqqN+MbQrj9/8aEeAJSDAygmgnA3U5Dma8xI9f91UsrAM/LCp MCb/46rX/gYEGOuEw8tPi8NQFKUOL+kO2m+8xikR1pOrocljGVFM/7kebaJMlG649J+3 MF9g3YFNrh9Nd9ZBURcjktyKxayIULYamt6SsoeBoCz0275LCGlcs2P4zGk8uxoNDtyX 1+Mxp757kmN7qT4la+aLq0FPB26XsaaESPXkv7eJLLYqtnDIMkSnXhSqTgbyrziG50JZ ovCcSioMpXT4bJbATOc6xyLQ9bThVSUFxhj0L+A68ZG2rTGq6VkNZ+7IMYyiYzEQPvB5 osYw== X-Gm-Message-State: AIVw112ZIZiwGok3NvO0C68B6a82T1+YfPBj+BQt0Acb4LF8lZ59/mAn cCOuUgQg0p/Zh8z5HUQ= X-Received: by 10.99.127.90 with SMTP id p26mr23953pgn.377.1501792412711; Thu, 03 Aug 2017 13:33:32 -0700 (PDT) Received: from bigtime.twiddle.net (97-126-108-236.tukw.qwest.net. [97.126.108.236]) by smtp.googlemail.com with ESMTPSA id t3sm61351326pfb.147.2017.08.03.13.33.31 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 03 Aug 2017 13:33:32 -0700 (PDT) Sender: Richard Henderson To: Peter Maydell , qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: patches@linaro.org References: <1501692241-23310-1-git-send-email-peter.maydell@linaro.org> <1501692241-23310-4-git-send-email-peter.maydell@linaro.org> From: Richard Henderson Message-ID: Date: Thu, 3 Aug 2017 13:33:30 -0700 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.2.1 MIME-Version: 1.0 In-Reply-To: <1501692241-23310-4-git-send-email-peter.maydell@linaro.org> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 7bit X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::243 Subject: Re: [Qemu-arm] [Qemu-devel] [PATCH 03/15] target/arm: Consolidate PMSA handling in get_phys_addr() X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 03 Aug 2017 20:33:41 -0000 On 08/02/2017 09:43 AM, Peter Maydell wrote: > Currently get_phys_addr() has PMSAv7 handling before the > "is translation disabled?" check, and then PMSAv5 after it. > Tidy this up by making the PMSAv5 code handle the "MPU disabled" > case itself, so that we have all the PMSA code in one place. > This will make adding the PMSAv8 code slightly cleaner, and > also means that pre-v7 PMSA cores benefit from the MPU lookup > logging that the PMSAv7 codepath had. > > Signed-off-by: Peter Maydell > --- > target/arm/helper.c | 38 ++++++++++++++++++++++---------------- > 1 file changed, 22 insertions(+), 16 deletions(-) Reviewed-by: Richard Henderson r~ From MAILER-DAEMON Thu Aug 03 16:40:11 2017 Received: from list by lists.gnu.org with archive (Exim 4.71) id 1ddMuh-0004V6-Hb for mharc-qemu-arm@gnu.org; Thu, 03 Aug 2017 16:40:11 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:57774) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ddMuf-0004RF-CT for qemu-arm@nongnu.org; Thu, 03 Aug 2017 16:40:10 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ddMuc-0002KN-Hz for qemu-arm@nongnu.org; Thu, 03 Aug 2017 16:40:09 -0400 Received: from mail-lf0-x242.google.com ([2a00:1450:4010:c07::242]:32811) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ddMuc-0002Hm-92; Thu, 03 Aug 2017 16:40:06 -0400 Received: by mail-lf0-x242.google.com with SMTP id 65so1689792lfa.0; Thu, 03 Aug 2017 13:40:04 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=date:from:to:cc:subject:message-id:references:mime-version :content-disposition:in-reply-to:user-agent; bh=MlCfXOfsXZy8M+dj6JePXXybU/Z1rfXgXmiwd/ExM2o=; b=rlnC6RNxiXWj3aCEJZAYBkZmTTSB4ugxIY0ujnmuxovYm3xnfGE3Cho+kB7h1LDHc3 A2frwoRMQtTDKvJw9fl8QCeBdFQnc00/5syliSesE0QaZ2pM3c8SJU9K86h/KmqnkyQv klqY2IVGJxKVQrwiPx2X+8jRccL05HH2C4pxmvRRw2xjCESz7uJo5f8Uxk/EDbFVgkvY aldNvnYxgHC+3nLmFjEs6bdaIWFKth2yKvrHK7wg4DpMVLUkFu44lY8W3arlVgtEmVdJ pbTqZYSaHmYIugo5lVRP+1A1m2IdbxJAGwo++k8FWKrVHouXubOyzx6KT1vzOrtD2D6j CyQQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:in-reply-to:user-agent; bh=MlCfXOfsXZy8M+dj6JePXXybU/Z1rfXgXmiwd/ExM2o=; b=NYS47u1oK60H1KXZdq7gna0gG532VZWd3SMCFmGNJVY2bl5AzTyVxja4xgss9zkadv vyNp5ghU0xTQ7+tkm4JXADijW+MlN8C2wfcv8yasRyiWjallae9K0eDBctmhs8iPV3dw om3wJ+qFLwWZHZUftrhaVsRmRC+ujX+sHPDJWTQEJMHHCPKTJPOunLyq9Fn+UV7lr8ng 0PHSUSO+rzj47k/Z0Gq3jJ8vsdUqZT1ryay5P44qtGl+Ryh/lK4A/DTh9MrIT5PbZrn+ MS3JVe1b7TUKRdm864VVTYkezsqC4/VbbDjr2hQHzTpVV9yTSRN9CzoBL14A82IT67bT 3xjQ== X-Gm-Message-State: AHYfb5iJGJ7rf8E8m4a5z9sfLwgVZypJ9msOMsknj9jI4P5j0I5aawoA 6WJDy9GCiEZ1qw== X-Received: by 10.25.201.216 with SMTP id z207mr19143lff.206.1501792803172; Thu, 03 Aug 2017 13:40:03 -0700 (PDT) Received: from gmail.com (81-231-233-234-no56.tbcn.telia.com. [81.231.233.234]) by smtp.gmail.com with ESMTPSA id k70sm2231468lfe.73.2017.08.03.13.40.01 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 03 Aug 2017 13:40:02 -0700 (PDT) Date: Thu, 3 Aug 2017 22:40:01 +0200 From: "Edgar E. Iglesias" To: Richard Henderson Cc: Peter Maydell , qemu-arm@nongnu.org, qemu-devel@nongnu.org, patches@linaro.org Message-ID: <20170803204001.GX4859@toto> References: <1501692241-23310-1-git-send-email-peter.maydell@linaro.org> <1501692241-23310-3-git-send-email-peter.maydell@linaro.org> <3f6ee028-b7f9-fbe0-1aea-eb1e6faab5a3@twiddle.net> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <3f6ee028-b7f9-fbe0-1aea-eb1e6faab5a3@twiddle.net> User-Agent: Mutt/1.5.24 (2015-08-30) X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4010:c07::242 Subject: Re: [Qemu-arm] [Qemu-devel] [PATCH 02/15] target/arm: Don't trap WFI/WFE for M profile X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 03 Aug 2017 20:40:10 -0000 On Thu, Aug 03, 2017 at 01:28:28PM -0700, Richard Henderson wrote: > On 08/02/2017 09:43 AM, Peter Maydell wrote: > > M profile cores can never trap on WFI or WFE instructions. Check for > > M profile in check_wfx_trap() to ensure this. > > > > The existing code will do the right thing for v7M cores because > > the hcr_el2 and scr_el3 registers will be all-zeroes and so we > > won't attempt to trap, but when we start setting ARM_FEATURE_V8 > > for v8M cores the v8A handling of SCTLR.nTWE and .nTWI will not > > give the right results. > > > > Signed-off-by: Peter Maydell > > --- > > target/arm/op_helper.c | 5 +++++ > > 1 file changed, 5 insertions(+) > > Reviewed-by: Richard Henderson > > While looking at this, I think there's an error in helper_wfi. The early exit > for cpu_has_work should happen after the exception check. I don't have the spec at hand but IIRC the trap should only happen if the processor would have entered the low-power state (i.e if there's no work). A comment in the code would probably be good... Cheers, Edgar From MAILER-DAEMON Thu Aug 03 16:45:06 2017 Received: from list by lists.gnu.org with archive (Exim 4.71) id 1ddMzS-0006du-7m for mharc-qemu-arm@gnu.org; Thu, 03 Aug 2017 16:45:06 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:38291) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ddMzP-0006cj-Vs for qemu-arm@nongnu.org; Thu, 03 Aug 2017 16:45:04 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ddMzO-0001E5-VV for qemu-arm@nongnu.org; Thu, 03 Aug 2017 16:45:03 -0400 Received: from mail-wr0-x232.google.com ([2a00:1450:400c:c0c::232]:34360) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ddMzO-00018b-Mx for qemu-arm@nongnu.org; Thu, 03 Aug 2017 16:45:02 -0400 Received: by mail-wr0-x232.google.com with SMTP id 12so9899875wrb.1 for ; Thu, 03 Aug 2017 13:45:00 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:in-reply-to:references:from:date:message-id:subject:to :cc; bh=hDO236pVuqQR4aAUeWmB3boycnnstKAKdj0nAOfB4sg=; b=b640FU2xd01bgwPH8vEgb377Yz2/plBZOU1HWkqBctZ2wvFfn7r/37v/spNyYVyiSk tVsiIF9ZnWPczOIfwZGY7audSAYGsWs44reISF2DfCVswF1lVQxiKiHY8FXs1XONuKCc DsSDbAUJZ3/sNN5MIGbmqyZRhV0wvjw9mh+X0= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:in-reply-to:references:from:date :message-id:subject:to:cc; bh=hDO236pVuqQR4aAUeWmB3boycnnstKAKdj0nAOfB4sg=; b=LsR7sZknuCa577NTLXI1wv4cj9w6UH77txVpTnxY9t4vVqy1S+gro643q+AnzCJF4H OHvU5b0ol3U8VZnAAoFGNA9HfYNM2FAyNNof+h5jKjmxQ3JgTHr1Bz3brjLbyTH66t41 Q7mHVzqemmEfbbKmXxPXNLL/8ghONGylYs/7B7sJ/Ydqg7yW4F2ACWGXWcre2MaIoDjg Tx0fyc6yHyIvj6tLm7X8nFHJGmUmHKukJr1DAuFSux+YUHTXvpP8CvJFd+NdHWT5HG/T vlSjco2i1Tbm7H3UwQ7r7VdsAYXRU/UKLT/ORLdOPbZfOxTwqoKGjON4ns0C8zZMb47v faSA== X-Gm-Message-State: AIVw113uAJjk+rgjYzhzcxOy3e8mmEE0yH06MLsnlU+9kHZrvUOkW0ry ETnatuRsX1cYrSa3f7yvXX8PpxVcf5EB X-Received: by 10.223.174.242 with SMTP id y105mr65162wrc.262.1501793099909; Thu, 03 Aug 2017 13:44:59 -0700 (PDT) MIME-Version: 1.0 Received: by 10.223.134.54 with HTTP; Thu, 3 Aug 2017 13:44:39 -0700 (PDT) In-Reply-To: <3f6ee028-b7f9-fbe0-1aea-eb1e6faab5a3@twiddle.net> References: <1501692241-23310-1-git-send-email-peter.maydell@linaro.org> <1501692241-23310-3-git-send-email-peter.maydell@linaro.org> <3f6ee028-b7f9-fbe0-1aea-eb1e6faab5a3@twiddle.net> From: Peter Maydell Date: Thu, 3 Aug 2017 21:44:39 +0100 Message-ID: To: Richard Henderson Cc: qemu-arm , QEMU Developers , "patches@linaro.org" Content-Type: text/plain; charset="UTF-8" X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:400c:c0c::232 Subject: Re: [Qemu-arm] [Qemu-devel] [PATCH 02/15] target/arm: Don't trap WFI/WFE for M profile X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 03 Aug 2017 20:45:05 -0000 On 3 August 2017 at 21:28, Richard Henderson wrote: > While looking at this, I think there's an error in helper_wfi. The early exit > for cpu_has_work should happen after the exception check. No, that's deliberate; as Edgar says, the trap only happens "if the instruction would otherwise have caused the PE to enter a low-power state". The rationale AIUI is that the traps to EL2 are there so that when an EL guest does a WFI in its idle loop the EL2 hypervisor can gain control and give the CPU to something else. This obviously imposes overhead, so if the WFI wouldn't actually halt (because there's already a condition that will cause it to wake up) it's more efficient just to let the guest continue to execute. (It also means that NOP is a valid WFI implementation, though I think that's just a coincidental bonus.) In fact the architecture gives even more flexibility in that it only requires the trap to be taken "if the instruction does not complete in finite time in the absence of a Wakeup event", so you can do more complicated things like "just pause for a short period of time to see if an interrupt might come in and wake us up, before giving up and taking the trap to EL2". thanks -- PMM From MAILER-DAEMON Thu Aug 03 16:47:06 2017 Received: from list by lists.gnu.org with archive (Exim 4.71) id 1ddN1O-000857-En for mharc-qemu-arm@gnu.org; Thu, 03 Aug 2017 16:47:06 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:42264) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ddN1M-00083n-Gg for qemu-arm@nongnu.org; Thu, 03 Aug 2017 16:47:05 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ddN1L-0004dx-Sf for qemu-arm@nongnu.org; Thu, 03 Aug 2017 16:47:04 -0400 Received: from mail-pg0-x241.google.com ([2607:f8b0:400e:c05::241]:36553) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ddN1H-0004VA-Qr; Thu, 03 Aug 2017 16:46:59 -0400 Received: by mail-pg0-x241.google.com with SMTP id y129so2467898pgy.3; Thu, 03 Aug 2017 13:46:59 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:subject:to:cc:references:from:message-id:date:user-agent :mime-version:in-reply-to:content-language:content-transfer-encoding; bh=MyN/4gdpQJCvs7RFyf+EsvoiQk8U6pHEIKGUeTb+cpE=; b=LAYqzva0JXpKhH9ifgUuQ0OcfwayEMYIvN9qcfvkqtS2qAR+RV0yoJ2sfp2h4030wH aVdov7ksDiDPDJyfEh+3JSrsA8IrE87Sh6nZ16KZD5NM2el5fPBXTFFwrsn4evLfnnxi 6SkVbDnjJkPh/aXotvH4zHWwUBs+6Bq8GNIaGzoR6gpHD5aniDfY77lruA4NQBYFIrTa C1fsXO4tcHa3XXVPMQFdKaas9hkCg4dPHM8hw4cF5ma+35c3JenUalOvGvEUpfjz7IH5 bcdyYH8N93I/Iw+bfdB4OZpQkYMJZ3YeHySNnhu+up/HTQojpbmDvEVaaFqWl+yG4nrH Ns3w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:subject:to:cc:references:from:message-id :date:user-agent:mime-version:in-reply-to:content-language :content-transfer-encoding; bh=MyN/4gdpQJCvs7RFyf+EsvoiQk8U6pHEIKGUeTb+cpE=; b=XA2pKol06WMm+03aauJC4HuK74n6vsBZrr5F6Nsol30TKuQ2Oe6K+OAgoB2lUrv1g/ St0JCymFMcmwWRyL1taQeUaz1cRDWmdRRwKnP8TCB14ZbOXd9zTqxNmd+47RRIaKnQ1+ IyDzy5HKeTQLWwIXKM/vgqgLtJzEXzsRSDZH5VowFruVQXwd7p5sl7ULP+m0mX+LMCkt DC7BySmrx4BRaazLWZMI/FYL53UOZSe3zk9CqZJoihSAyd6EKW9mIzrE2Ndd5hZVLSNl pCzc1UOcxm/2opiJX4YTNGbl6s0wtk4s0TS5T5Xh5uqvyaJeZzw3zz1CrlHlRN2mqPzc 8cAw== X-Gm-Message-State: AIVw112+gZRCTr26hzgRLUzePUwU6IXXP6qkrZXuzsOZfLO801dvacd2 pgw58/FO/6jNlw== X-Received: by 10.84.205.70 with SMTP id o6mr91913plh.51.1501793218795; Thu, 03 Aug 2017 13:46:58 -0700 (PDT) Received: from bigtime.twiddle.net (97-126-108-236.tukw.qwest.net. [97.126.108.236]) by smtp.googlemail.com with ESMTPSA id 204sm17836858pfu.118.2017.08.03.13.46.57 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 03 Aug 2017 13:46:58 -0700 (PDT) Sender: Richard Henderson To: "Edgar E. Iglesias" Cc: Peter Maydell , qemu-arm@nongnu.org, qemu-devel@nongnu.org, patches@linaro.org References: <1501692241-23310-1-git-send-email-peter.maydell@linaro.org> <1501692241-23310-3-git-send-email-peter.maydell@linaro.org> <3f6ee028-b7f9-fbe0-1aea-eb1e6faab5a3@twiddle.net> <20170803204001.GX4859@toto> From: Richard Henderson Message-ID: <4e0cab0f-83ab-0742-988d-9b2615f6ef4b@twiddle.net> Date: Thu, 3 Aug 2017 13:46:56 -0700 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.2.1 MIME-Version: 1.0 In-Reply-To: <20170803204001.GX4859@toto> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 7bit X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::241 Subject: Re: [Qemu-arm] [Qemu-devel] [PATCH 02/15] target/arm: Don't trap WFI/WFE for M profile X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 03 Aug 2017 20:47:05 -0000 On 08/03/2017 01:40 PM, Edgar E. Iglesias wrote: > I don't have the spec at hand but IIRC the trap should only happen > if the processor would have entered the low-power state (i.e if > there's no work). when SystemHintOp_WFE if IsEventRegisterSet() then ClearEventRegister(); else if PSTATE.EL == EL0 then AArch64.CheckForWFxTrap(EL1, TRUE); if HaveEL(EL2) && !IsSecure() && PSTATE.EL IN {EL0, EL1} && !IsInHost() then AArch64.CheckForWFxTrap(EL2, TRUE); if HaveEL(EL3) && PSTATE.EL != EL3 then AArch64.CheckForWFxTrap(EL3, TRUE); WaitForEvent(); Ah, I see what you mean, since WaitForEvent is also described as checking EventRegister. Thanks. r~ From MAILER-DAEMON Thu Aug 03 16:47:22 2017 Received: from list by lists.gnu.org with archive (Exim 4.71) id 1ddN1d-0008Is-KP for mharc-qemu-arm@gnu.org; Thu, 03 Aug 2017 16:47:22 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:39062) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ddMVP-0004K9-Cs for qemu-arm@nongnu.org; Thu, 03 Aug 2017 16:14:04 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ddMVK-0000bK-Tp for qemu-arm@nongnu.org; Thu, 03 Aug 2017 16:14:03 -0400 Received: from mail-pg0-x234.google.com ([2607:f8b0:400e:c05::234]:37642) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ddMVK-0000Z7-Mb for qemu-arm@nongnu.org; Thu, 03 Aug 2017 16:13:58 -0400 Received: by mail-pg0-x234.google.com with SMTP id y129so10300972pgy.4 for ; Thu, 03 Aug 2017 13:13:57 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=subject:to:cc:references:from:message-id:date:user-agent :mime-version:in-reply-to:content-language:content-transfer-encoding; bh=lWSSFDsfrT+iQh3R9JMNL0vaAj1GAJ7iSR1czVMRKI4=; b=TkthdcEqzhr8nVW5EW5O+znmFZY6dtsOox6Chcms/AG7PnTjGNz6URLhqOwmiAjbtS Sdm0PSnYq+0x5p9DKxjCIYef5ujuo42OUq3CEuMFrAHlY+83WsLwYEbjPkGNSTgvq543 P8eV/t6pV+QTuaodDX0o3cIsPmOLCB+2SoLnc= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:subject:to:cc:references:from:message-id:date :user-agent:mime-version:in-reply-to:content-language :content-transfer-encoding; bh=lWSSFDsfrT+iQh3R9JMNL0vaAj1GAJ7iSR1czVMRKI4=; b=KHK/NnH1lxI+nVueJxldRIorSHSTkaq0CZYPCHxPgWCnBW1IysRbHqv7yn6JQ1Fj/m 6re7WHVIVb3BprTwH60q/ZvVPmYyU0UFO9XuNaNT6Dl2HAb6BTDXrwq5ElAjjruuDpYL TodEdA0p+xNCW3GuIw8CtXIGtOsVpR0I7L4T2WyZpgSGxEoA1FfyTO7NvFE9MFdmoQTM WR7pCxzr5ZNvwEN/wORwEd1LA24QhG2f6kmZdCpm9P0gVmGHn332pWPFwoGYfnTLfbJo FYg++JUHkS8Y98cAA2k+pEJOyi0J1cVIDWcTohTmR3IwuyjP1q5gbvW2CbrCCxRf8VZr jnog== X-Gm-Message-State: AIVw1137tmRHt+zpVl83jJCF8jQtIsT/BCrLRmxjozJ1P5dVJdDkDbSH qZrIEdG5Q8tkWKKL X-Received: by 10.84.225.4 with SMTP id t4mr15424plj.428.1501791236294; Thu, 03 Aug 2017 13:13:56 -0700 (PDT) Received: from bigtime.twiddle.net (97-126-108-236.tukw.qwest.net. [97.126.108.236]) by smtp.gmail.com with ESMTPSA id d81sm27150318pfb.7.2017.08.03.13.13.54 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 03 Aug 2017 13:13:55 -0700 (PDT) To: Peter Maydell , qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: patches@linaro.org References: <1501692241-23310-1-git-send-email-peter.maydell@linaro.org> <1501692241-23310-2-git-send-email-peter.maydell@linaro.org> From: Richard Henderson Message-ID: <14c11400-2b2e-57b1-075e-09869dbb2801@linaro.org> Date: Thu, 3 Aug 2017 13:13:53 -0700 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.2.1 MIME-Version: 1.0 In-Reply-To: <1501692241-23310-2-git-send-email-peter.maydell@linaro.org> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 7bit X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::234 X-Mailman-Approved-At: Thu, 03 Aug 2017 16:47:20 -0400 Subject: Re: [Qemu-arm] [Qemu-devel] [PATCH 01/15] target/arm: Use MMUAccessType enum rather than int X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 03 Aug 2017 20:14:04 -0000 On 08/02/2017 09:43 AM, Peter Maydell wrote: > In the ARM get_phys_addr() code, switch to using the MMUAccessType > enum and its MMU_* values rather than int and literal 0/1/2. > > Signed-off-by: Peter Maydell > --- > target/arm/helper.c | 30 +++++++++++++++--------------- > target/arm/internals.h | 3 ++- > 2 files changed, 17 insertions(+), 16 deletions(-) Reviewed-by: Richard Henderson r~ From MAILER-DAEMON Thu Aug 03 17:34:02 2017 Received: from list by lists.gnu.org with archive (Exim 4.71) id 1ddNko-0005kJ-9D for mharc-qemu-arm@gnu.org; Thu, 03 Aug 2017 17:34:02 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:38163) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ddNkl-0005io-Bk for qemu-arm@nongnu.org; Thu, 03 Aug 2017 17:34:00 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ddNkk-00064A-Fj for qemu-arm@nongnu.org; Thu, 03 Aug 2017 17:33:59 -0400 Received: from mail-pf0-x243.google.com ([2607:f8b0:400e:c00::243]:33348) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ddNkg-000600-9B; Thu, 03 Aug 2017 17:33:54 -0400 Received: by mail-pf0-x243.google.com with SMTP id c65so2589609pfl.0; Thu, 03 Aug 2017 14:33:54 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:subject:to:cc:references:from:message-id:date:user-agent :mime-version:in-reply-to:content-language:content-transfer-encoding; bh=G0eg2D+AANxVTZS0cSGSJLLhr3hPStJCRELoBdLCDgM=; b=Zyyr21FZAX37JqYWThYBYN7l0BFBHnKdU5ZJ7wxK3UDRIcQSYYZS4pVsjhIRZniNYV FP1rT3ZLvQmvHxWuZXYpH5AP6EUnTrIl9umc3B0k6G6K4Kij4OX25+difwYa1MWPvdom 2h0ePQzbcuBqJbhXns8Tvj1OeHFSWQD081vOAtiwF5jNBrKmOLQo+z/KXRp99i/neWSb HZlA/UWuiS3nsvOQ3Ecby7EI4Bn5ICQdgLpaX+jmzv0dSffe98Tcgy/byrWioC9z6u9v 1I5ANg/isFb8+tBbmFsOztuRjC4gAovneqL8iIp/Ybyt9PogJ5q2grymr5gt8KTD9hvX vpBA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:subject:to:cc:references:from:message-id :date:user-agent:mime-version:in-reply-to:content-language :content-transfer-encoding; bh=G0eg2D+AANxVTZS0cSGSJLLhr3hPStJCRELoBdLCDgM=; b=HL07UleqNP1d/6BzevQb/nYbGUS82+M6q26cLFV35E1zVSH2XIlJRFQ59K50Qaxkfy w/RGrTruEislHJ6rs5Yk8pzDGLIQDg45Hweo6AGDtuBiZiWQrZHtFFN1z84EJw+1IjjV ruz4ny/c7FZGHPtTUvbl3+gtLdzF2nqDRt11AW04DyR/X4DujKMMGK5fgBE7GIkPZ7iR d4i87g/HqUBwVk/5Zh2JMvpuYif/NpW4UNLGsvQgMNylWTepCVsa02ID4G8p4w1YFBrQ 48nXzTd2fBwdQ3BKrLlWw3Di1uYWZb7s6bRFG4hVUgZFnwGlVOTCYJZTIWZczUEMnICJ Oxtw== X-Gm-Message-State: AIVw111iak0w9366GdbMZy9QaFTnKyQq5GD+OFjnTJUvYKZgoO+O/Ojj KgLqlce0kUuN5Q== X-Received: by 10.98.158.194 with SMTP id f63mr188364pfk.288.1501796033262; Thu, 03 Aug 2017 14:33:53 -0700 (PDT) Received: from bigtime.twiddle.net (97-126-108-236.tukw.qwest.net. [97.126.108.236]) by smtp.googlemail.com with ESMTPSA id q76sm17528272pfg.42.2017.08.03.14.33.51 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 03 Aug 2017 14:33:51 -0700 (PDT) Sender: Richard Henderson To: Peter Maydell , qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: patches@linaro.org References: <1501692241-23310-1-git-send-email-peter.maydell@linaro.org> <1501692241-23310-5-git-send-email-peter.maydell@linaro.org> From: Richard Henderson Message-ID: <1dc53909-4cd9-2977-1188-d0316165652e@twiddle.net> Date: Thu, 3 Aug 2017 14:33:50 -0700 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.2.1 MIME-Version: 1.0 In-Reply-To: <1501692241-23310-5-git-send-email-peter.maydell@linaro.org> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 7bit X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::243 Subject: Re: [Qemu-arm] [Qemu-devel] [PATCH 04/15] target/arm: Tighten up Thumb decode where new v8M insns will be X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 03 Aug 2017 21:34:00 -0000 On 08/02/2017 09:43 AM, Peter Maydell wrote: > Tighten up the T32 decoder in the places where new v8M instructions > will be: > * TT/TTT/TTA/TTAT are in what was nominally LDREX/STREX r15, ... > which is UNPREDICTABLE: > make the UNPREDICTABLE behaviour be to UNDEF > * BXNS/BLXNS are distinguished from BX/BLX via the low 3 bits, > which in previous architectural versions are SBZ: > enforce the SBZ via UNDEF rather than ignoring it, and move > the "ARCH(5)" UNDEF case up so we don't leak a TCG temporary > * SG is in the encoding which would be LDRD/STRD with rn = r15; > this is UNPREDICTABLE and we currently UNDEF: > move this check further up the code so that we don't leak > TCG temporaries in the UNDEF case and have a better place > to put the SG decode. > > This means that if a v8M binary is accidentally run on v7M > or if a test case hits something that we haven't implemented > yet the behaviour will be obvious (UNDEF) rather than obscure > (plough on treating it as a different instruction). > > In the process, add some comments about the instruction patterns > at these points in the decode. Our Thumb and ARM decoders are > very difficult to understand currently, but gradually adding > comments like this should help to clarify what exactly has > been decoded when. > > Signed-off-by: Peter Maydell > --- > target/arm/translate.c | 48 +++++++++++++++++++++++++++++++++++++++--------- > 1 file changed, 39 insertions(+), 9 deletions(-) Reviewed-by: Richard Henderson r~ From MAILER-DAEMON Thu Aug 03 17:34:59 2017 Received: from list by lists.gnu.org with archive (Exim 4.71) id 1ddNlj-0006N0-K1 for mharc-qemu-arm@gnu.org; Thu, 03 Aug 2017 17:34:59 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:39465) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ddNle-0006Le-Bu for qemu-arm@nongnu.org; Thu, 03 Aug 2017 17:34:58 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ddNld-0006w5-KD for qemu-arm@nongnu.org; Thu, 03 Aug 2017 17:34:54 -0400 Received: from mail-pg0-x244.google.com ([2607:f8b0:400e:c05::244]:33315) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ddNlb-0006tL-OL; Thu, 03 Aug 2017 17:34:51 -0400 Received: by mail-pg0-x244.google.com with SMTP id u185so2568226pgb.0; Thu, 03 Aug 2017 14:34:51 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:subject:to:cc:references:from:message-id:date:user-agent :mime-version:in-reply-to:content-language:content-transfer-encoding; bh=LagNwx2JMFcL5NmlMJoE8gRApfuC6RRMjBYDEFM69T4=; b=tSYIIX45w6H+nkPE5f7xqtiePoi3iMS76nvy9qMNLbMTSq2UQI8CrWBM73OX1MU4Oz S9MCZoRyR/WrThpzWQPWVGNL+7O+oYvxaZl+CmCaQASJNc1msj9MaOo7mpL7hEer4Rys 2oi4oUiuTFAnZiY6nyT99GqlprI/7/Qxfd5YSDtXI6lamkRoMZMS4uaJBXEu9ehSbxZr 60eZVCxbmsxBk9RvtqGcMFuuoySlxLHbJ52hbecmdOmW/1HnON2ZWV2OjPQ9P2NOSsJn kDs2m7mWNYR7rxGCm+vQwZFbwnXB0ihWwdRVWuuAFLIwtZ9PL/nIMv6bx0eP/pqWYXGn 0UkQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:subject:to:cc:references:from:message-id :date:user-agent:mime-version:in-reply-to:content-language :content-transfer-encoding; bh=LagNwx2JMFcL5NmlMJoE8gRApfuC6RRMjBYDEFM69T4=; b=SjlttN3jOu8AvJtJHj7i7QYL7fCvkn8EuYi6Q7O3KQ23Hs+x7v4A04Vwi1KQGc9SzN QVpV65wTwztuA6c5TcEZ83Q++AzFjCFRsQ3sreQJmnCWvmC4HqzXaweAc5W5EEl4WwF5 pWf0nBzObNbNA12Ah7+aHJysR6QA1GJAnBObEctIrufhwWD9OpFb6oiYWtxpa+/m3nrv i+axFaBfjvy1FwIWJG553+WKMKitXjprVWCmx9TJYkVvRxXHO3TNT5qh5zCb9UwXLVLs EKl5tpV7fsjyMlPwp/CKL3E2nqKLmEfoAtIfGv+INKLCtuDHUiUpW/0YcE2ZvEsV+K1g 2Mmw== X-Gm-Message-State: AIVw112PKLWdboW01mf47NIfzegosJqb2Thds0cnzocwDXSAqryWE5ce cD87RQ/Q9s/Vy5FdEh0= X-Received: by 10.98.219.70 with SMTP id f67mr199682pfg.336.1501796090803; Thu, 03 Aug 2017 14:34:50 -0700 (PDT) Received: from bigtime.twiddle.net (97-126-108-236.tukw.qwest.net. [97.126.108.236]) by smtp.googlemail.com with ESMTPSA id q79sm65078557pfi.99.2017.08.03.14.34.50 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 03 Aug 2017 14:34:50 -0700 (PDT) Sender: Richard Henderson To: Peter Maydell , qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: patches@linaro.org References: <1501692241-23310-1-git-send-email-peter.maydell@linaro.org> <1501692241-23310-6-git-send-email-peter.maydell@linaro.org> From: Richard Henderson Message-ID: <41deac29-1b75-6224-fb5f-983b4533f213@twiddle.net> Date: Thu, 3 Aug 2017 14:34:48 -0700 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.2.1 MIME-Version: 1.0 In-Reply-To: <1501692241-23310-6-git-send-email-peter.maydell@linaro.org> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 7bit X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::244 Subject: Re: [Qemu-arm] [Qemu-devel] [PATCH 05/15] hw/intc/armv7m_nvic.c: Remove out of date comment X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 03 Aug 2017 21:34:58 -0000 On 08/02/2017 09:43 AM, Peter Maydell wrote: > Remove an out of date comment which says there's only one > item in the NVIC container region -- we put systick into its > own device object a while back and so now there are two > things in the container. > > Signed-off-by: Peter Maydell > --- > hw/intc/armv7m_nvic.c | 4 ---- > 1 file changed, 4 deletions(-) Reviewed-by: Richard Henderson r~ From MAILER-DAEMON Thu Aug 03 17:36:03 2017 Received: from list by lists.gnu.org with archive (Exim 4.71) id 1ddNml-00071v-Ab for mharc-qemu-arm@gnu.org; Thu, 03 Aug 2017 17:36:03 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:41181) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ddNmg-0006zh-Ut for qemu-arm@nongnu.org; Thu, 03 Aug 2017 17:35:59 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ddNmg-0008E7-4j for qemu-arm@nongnu.org; Thu, 03 Aug 2017 17:35:58 -0400 Received: from mail-pf0-x241.google.com ([2607:f8b0:400e:c00::241]:34768) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ddNmc-00088u-2a; Thu, 03 Aug 2017 17:35:54 -0400 Received: by mail-pf0-x241.google.com with SMTP id t86so2594144pfe.1; Thu, 03 Aug 2017 14:35:53 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:subject:to:cc:references:from:message-id:date:user-agent :mime-version:in-reply-to:content-language:content-transfer-encoding; bh=tTh/X09uKNRwMRu/rocP1bXkgYvPuwHORsxwa5LoXhU=; b=ADhZWh9rVLEKGBKXe0AAAMmtlndpOAwj+NnVq+CRZGYmbDa6+982FkS/7So8LEbp8U EvPfrTfk92PjPYlpvsd32fkvV4o0FWDn0wipDdxBCsqdWOEW3lrLreWHWpi1l6XJPUzT JBh3zcwXEiL/tb2zo7bg5yE5v1gx1quCowCKPKG5Zh0wmNwjLb/xyThT9kpznpOQkly9 rfwp5XpmQe0b+esG+cAlJk4xc1e46Dl3IfjX2OyXXwfGetp5SDQOLcJ8UMX1ZFLwZHyx Rvlg3hf4zWQgpCm4iZc5l9NBwbFJlu4U7UdiCETvwR12sCLvSDbDdAEeFv5Y4LKTWy6p nQXg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:subject:to:cc:references:from:message-id :date:user-agent:mime-version:in-reply-to:content-language :content-transfer-encoding; bh=tTh/X09uKNRwMRu/rocP1bXkgYvPuwHORsxwa5LoXhU=; b=fod4nd9cWztmu2Xjxjmr+3klV4EniH5XLaLLt4TfkOK9T0np0STEixi8HLSV/AN3lu YAVhqjNnEQ9RC99DdN6VaIGw9lG5mOvX4zqifKkgskEL4qF4jtiQDk4jABFvfjUen/8d ngrH4c1VXi8GN4QnwSqAzlFxMPxq0n+NLcUT4ZcFGSOfgpEWnaAlLcT2XgR7wVdvzzK9 Kac8V+EDD9niUWEHwFCFdcbsgDnvpCyjCsTwa4fr7ga+e8ywZY43RBhpMHaIeTPkp7YO qZ/eiM/jdAYQC2S+MJ/b2l0n2jAEwsI/NCei20wVr+HlWQNh6S+VR84HiKBjnHI/+PUk 38yQ== X-Gm-Message-State: AIVw113lnM0Gv0bN1SIhvjiIBKR0SSr74PVBqe+wnlcVbtavUI5+KLxU MUGsWUPuALvgoA== X-Received: by 10.98.11.65 with SMTP id t62mr184002pfi.119.1501796153211; Thu, 03 Aug 2017 14:35:53 -0700 (PDT) Received: from bigtime.twiddle.net (97-126-108-236.tukw.qwest.net. [97.126.108.236]) by smtp.googlemail.com with ESMTPSA id q5sm11323007pgn.21.2017.08.03.14.35.52 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 03 Aug 2017 14:35:52 -0700 (PDT) Sender: Richard Henderson To: Peter Maydell , qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: patches@linaro.org References: <1501692241-23310-1-git-send-email-peter.maydell@linaro.org> <1501692241-23310-7-git-send-email-peter.maydell@linaro.org> From: Richard Henderson Message-ID: Date: Thu, 3 Aug 2017 14:35:51 -0700 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.2.1 MIME-Version: 1.0 In-Reply-To: <1501692241-23310-7-git-send-email-peter.maydell@linaro.org> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 7bit X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::241 Subject: Re: [Qemu-arm] [Qemu-devel] [PATCH 06/15] target/arm: Remove incorrect comment about MPU_CTRL X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 03 Aug 2017 21:35:59 -0000 On 08/02/2017 09:43 AM, Peter Maydell wrote: > Remove the comment that claims that some MPU_CTRL bits are stored > in sctlr_el[1]. This has never been true since MPU_CTRL was added > in commit 29c483a50607 -- the comment is a leftover from > Michael Davidsaver's original implementation, which I modified > not to use sctlr_el[1]; I forgot to delete the comment then. > > Signed-off-by: Peter Maydell > --- > target/arm/cpu.h | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) Reviewed-by: Richard Henderson r~ From MAILER-DAEMON Thu Aug 03 17:36:30 2017 Received: from list by lists.gnu.org with archive (Exim 4.71) id 1ddNnC-0007Lk-BQ for mharc-qemu-arm@gnu.org; Thu, 03 Aug 2017 17:36:30 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:42153) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ddNn9-0007Jl-U6 for qemu-arm@nongnu.org; Thu, 03 Aug 2017 17:36:28 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ddNn8-0000P9-Pj for qemu-arm@nongnu.org; Thu, 03 Aug 2017 17:36:27 -0400 Received: from mail-pg0-x244.google.com ([2607:f8b0:400e:c05::244]:33400) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ddNn4-0000HH-0F; Thu, 03 Aug 2017 17:36:22 -0400 Received: by mail-pg0-x244.google.com with SMTP id u185so2570874pgb.0; Thu, 03 Aug 2017 14:36:21 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:subject:to:cc:references:from:message-id:date:user-agent :mime-version:in-reply-to:content-language:content-transfer-encoding; bh=58wZKequcRDYGwhsqvtcSqk9ztt9hILGoDNIrAWgoyw=; b=ZzrwPK3NCAXxfhMQ/Lp3/gc+wdVNn3FFZpk3XgkeHzbfIZms0ll9cziUQKkHpykgK2 a959J6X1AZPBz5Yz2h1UCOJwj2IHpy+3ZN+VCZg4Qkusixs0uoi8UNu+hlqEFQqTokCO +gLR+SREjmA6nlG6grZ7Ra2a9Yk+5Oxuzgx57bXk4wMuE3FfzceNivCrBjwCCofqVjXQ q9oQxn9o1+1b2D7FdNO0SJW6DkrS9+kBiu8yaDtAiZSzWPB8fj/Z6E83gujDdfW4TtU0 v8wepDfgOHBnebQthU9mdCWDgSU4udjfayvD6mITEtcpkgNNtKmOglhyN9DNOkf0nCzV H3cQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:subject:to:cc:references:from:message-id :date:user-agent:mime-version:in-reply-to:content-language :content-transfer-encoding; bh=58wZKequcRDYGwhsqvtcSqk9ztt9hILGoDNIrAWgoyw=; b=VYgiDd5If1oZ6O35UWnDTwMHQ46gZL5K6gBaHGes8IHhZDF5FBrbpjUDimTUtWXbY0 1X0rFyCdM1i9sFKNsmvVuE3LwEl/uEMtqMrumMniyUNTWBLv8Pqli7OP1aGypskQty+T 1VRGWzNRnekdJOkXH1eNcJI7Zxq0dQdeAXVYg9vkBo35ZegXYnfgBkX0HHcmFTtql88g DzWSInPFtbx3kRGziJIp3N+Nrlr9tJ01CamXI2rixERTm+PKw/942NpJk7W3veMjldbA DmRXWHzniwHcwoBr04NRP7c5ArR/pB0WUPdwzTNRUSpypZEF1YQav1dmsaBhAhDxWGv4 keVw== X-Gm-Message-State: AIVw112BzHWO2WcqLclvIeWgzWSW0GX4e0Iub/Cm2JW/y02Dv+XgqbNb 3O9O8EgqSnVHKg== X-Received: by 10.99.36.7 with SMTP id k7mr141254pgk.325.1501796181173; Thu, 03 Aug 2017 14:36:21 -0700 (PDT) Received: from bigtime.twiddle.net (97-126-108-236.tukw.qwest.net. [97.126.108.236]) by smtp.googlemail.com with ESMTPSA id g1sm2962986pfk.92.2017.08.03.14.36.20 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 03 Aug 2017 14:36:20 -0700 (PDT) Sender: Richard Henderson To: Peter Maydell , qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: patches@linaro.org References: <1501692241-23310-1-git-send-email-peter.maydell@linaro.org> <1501692241-23310-8-git-send-email-peter.maydell@linaro.org> From: Richard Henderson Message-ID: Date: Thu, 3 Aug 2017 14:36:19 -0700 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.2.1 MIME-Version: 1.0 In-Reply-To: <1501692241-23310-8-git-send-email-peter.maydell@linaro.org> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 7bit X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::244 Subject: Re: [Qemu-arm] [Qemu-devel] [PATCH 07/15] target/arm: Fix outdated comment about exception exit X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 03 Aug 2017 21:36:28 -0000 On 08/02/2017 09:43 AM, Peter Maydell wrote: > When we switched our handling of exception exit to detect > the magic addresses at translate time rather than via > a do_unassigned_access hook, we forgot to update a > comment; correct the omission. > > Signed-off-by: Peter Maydell > --- > target/arm/helper.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) Reviewed-by: Richard Henderson r~ From MAILER-DAEMON Thu Aug 03 17:51:47 2017 Received: from list by lists.gnu.org with archive (Exim 4.71) id 1ddO1z-0004A1-Mn for mharc-qemu-arm@gnu.org; Thu, 03 Aug 2017 17:51:47 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:37986) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ddO1x-00047W-FW for qemu-arm@nongnu.org; Thu, 03 Aug 2017 17:51:46 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ddO1w-00026l-Ol for qemu-arm@nongnu.org; Thu, 03 Aug 2017 17:51:45 -0400 Received: from mail-pf0-x242.google.com ([2607:f8b0:400e:c00::242]:38148) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ddO1q-0001vT-Lh; Thu, 03 Aug 2017 17:51:38 -0400 Received: by mail-pf0-x242.google.com with SMTP id h75so1449601pfh.5; Thu, 03 Aug 2017 14:51:38 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:subject:to:cc:references:from:message-id:date:user-agent :mime-version:in-reply-to:content-language:content-transfer-encoding; bh=RJ0t2d+8ZxBLI9FDLkCvRD6rWChvupS/1SsE5Thfrqc=; b=rNqzV5fJWl/7IPwk7jfUlkgqk1zvO6IGsAMKnwpKmZn5xWyjWDtVd1suqxnHCGTFSW oqxMja9O2XexjsUeM07G8AVm5mPgaaiTsl+YKpCdG3cFK4eAd8Um3fGWXFo533849NqX BLwqUEC6xYqg1fLxZvTD1Pfyx6QONM1OaZswdil03uYAMMOuxaM6aweYMnD2uSrAn0oT puYCgL6D78TX5FBH82OFBd4H4+y3p55nQrt1bcRObUeE7VtEFwr2lhNx/XVo/zEvZVP4 QTyLdluSi+5c8ac+/n91hznHr63WiAvD6MaLa1aQrBLMcg4GBklso3Nn8azwMOf/W4I7 6pTg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:subject:to:cc:references:from:message-id :date:user-agent:mime-version:in-reply-to:content-language :content-transfer-encoding; bh=RJ0t2d+8ZxBLI9FDLkCvRD6rWChvupS/1SsE5Thfrqc=; b=MxAE5/1DobIBZUJcuV5pmSq9yFl/8mgg4zjfTpaXFIS7kYm8yeQxyJ4/UuFXCHtSvD iBe+QsQlq+DR0+dVI/+CLRThaAZn7CpOMwnWCSe8hPxSuDAr/5oWQPVY/CgJcmx1UhMU 4XAJ8jAQB4UW+/yzGsROMLT8OHxgwXGIw2fAfUUFuHNF5CIFNRLhMmlFULTxQSZ6ralt VygmGtWpqi5TnXjvqJn9LuKSVFuM2fJj3LWJZfJr1VZELPVd5+yY9KbnUdZOSNJZywVT Rbaov7aaN0hCaiUear3hjk3x+Cro4EC3pABgFj+TM3lX62rf76wlrHydCMylzXEAwqT3 rQtg== X-Gm-Message-State: AIVw1112Oi6ziBjnWPMPGns/+AzA+5NzHu3hlKyLQNXkqO3E7Jgdm0iB PtlIkLDnYFFmMg== X-Received: by 10.84.232.13 with SMTP id h13mr309248plk.168.1501797097670; Thu, 03 Aug 2017 14:51:37 -0700 (PDT) Received: from bigtime.twiddle.net (97-126-108-236.tukw.qwest.net. [97.126.108.236]) by smtp.googlemail.com with ESMTPSA id 22sm23448874pfx.73.2017.08.03.14.51.36 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 03 Aug 2017 14:51:37 -0700 (PDT) Sender: Richard Henderson To: Peter Maydell , qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: patches@linaro.org References: <1501692241-23310-1-git-send-email-peter.maydell@linaro.org> <1501692241-23310-9-git-send-email-peter.maydell@linaro.org> From: Richard Henderson Message-ID: <80e9ff87-14d8-2e18-7c21-c1c7803b3a58@twiddle.net> Date: Thu, 3 Aug 2017 14:51:35 -0700 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.2.1 MIME-Version: 1.0 In-Reply-To: <1501692241-23310-9-git-send-email-peter.maydell@linaro.org> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 7bit X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::242 Subject: Re: [Qemu-arm] [Qemu-devel] [PATCH 08/15] target/arm: Define and use XPSR bit masks X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 03 Aug 2017 21:51:46 -0000 On 08/02/2017 09:43 AM, Peter Maydell wrote: > The M profile XPSR is almost the same format as the A profile CPSR, > but not quite. Define some XPSR_* macros and use them where we > definitely dealing with an XPSR rather than reusing the CPSR ones. > > Signed-off-by: Peter Maydell > --- > target/arm/cpu.h | 38 ++++++++++++++++++++++++++++---------- > target/arm/helper.c | 15 ++++++++------- > 2 files changed, 36 insertions(+), 17 deletions(-) Reviewed-by: Richard Henderson r~ From MAILER-DAEMON Thu Aug 03 18:03:33 2017 Received: from list by lists.gnu.org with archive (Exim 4.71) id 1ddODM-00087P-UU for mharc-qemu-arm@gnu.org; Thu, 03 Aug 2017 18:03:33 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:57007) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ddODI-00084u-2a for qemu-arm@nongnu.org; Thu, 03 Aug 2017 18:03:29 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ddODH-0007yN-A2 for qemu-arm@nongnu.org; Thu, 03 Aug 2017 18:03:28 -0400 Received: from mail-pf0-x241.google.com ([2607:f8b0:400e:c00::241]:35818) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ddODB-0007my-IL; Thu, 03 Aug 2017 18:03:21 -0400 Received: by mail-pf0-x241.google.com with SMTP id j68so6334pfc.2; Thu, 03 Aug 2017 15:03:21 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:subject:to:cc:references:from:message-id:date:user-agent :mime-version:in-reply-to:content-language:content-transfer-encoding; bh=ArZx5vsxiNY/zTM4RTLQBMbE7iETsTsPnsGuWQ/XuCs=; b=LppGENHtg1PDZ4vVi6e5rMrJrqrF4blCn/f8X1L+aCsU6EfbC2nZ20wBJEty1S8B33 W6zxK5g8UJEp9a5ZzMSpS6Nh5iyofWtRjuBrRvHXlAQPbu+4N72kuaMBcs7sSWLbwm1B UQRdGbkYlD7fMbmzzy3skTQC1V5dNREuQ9H7w6uzB5Ls21HTK83A6IS054ylXkAsS/a7 3hB6H6bUzSLsx2HplkpNXL/dPv3YHuYahBSX9xHF86akiC5F8ukqcJcrC6h89lUp+Cts INBjnph2wZvJnIH0Zs2pjtPi9dZYRtguljLilftEV47JM6sGlnyU6HxnS+82AjbBjTV6 ASbw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:subject:to:cc:references:from:message-id :date:user-agent:mime-version:in-reply-to:content-language :content-transfer-encoding; bh=ArZx5vsxiNY/zTM4RTLQBMbE7iETsTsPnsGuWQ/XuCs=; b=B+n3uYNMLG7uNELUWqPYwjjOys97qQt/L4EmfXXMfvfkKa2s30o3+c1nDzq1yMr10/ y9X0CtCt3JlvfIMZ42B5dskDyooY6bigw4u+NMtJz96YVP9GfFMhcSn9Er8NABwgrjVh lV7otF43wTSXvx/1UPVLUiB9GLXDiPZ2eAGyXPvyglqcVAO+DjgNiOdbC/h1I4VpyAIE 0IB25b4LylvU9eZZpB1T8VjjtqReSEoBlyBREvtQHi3rGcuDjG+TWwiLpwzT/tUiiMhM My24pCUNa8gsU7z5wl9d1kzlNvW5g3WIZzEfw1b/bcySxe+THd1Pm89zQp+OL9rk+jAc ZP9Q== X-Gm-Message-State: AIVw111WacQTuvd3bdOwz7DtScMLELwPk4+g9Ahf+clMWAAHL8FNJ/Jz oFTudxb2KfT7IQ== X-Received: by 10.84.164.193 with SMTP id l1mr283660plg.279.1501797800515; Thu, 03 Aug 2017 15:03:20 -0700 (PDT) Received: from bigtime.twiddle.net (97-126-108-236.tukw.qwest.net. [97.126.108.236]) by smtp.googlemail.com with ESMTPSA id z66sm29671728pfi.137.2017.08.03.15.03.19 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 03 Aug 2017 15:03:19 -0700 (PDT) Sender: Richard Henderson To: Peter Maydell , qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: patches@linaro.org References: <1501692241-23310-1-git-send-email-peter.maydell@linaro.org> <1501692241-23310-10-git-send-email-peter.maydell@linaro.org> From: Richard Henderson Message-ID: <20ef352d-38d3-90bb-27ef-a6a644240b9b@twiddle.net> Date: Thu, 3 Aug 2017 15:03:18 -0700 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.2.1 MIME-Version: 1.0 In-Reply-To: <1501692241-23310-10-git-send-email-peter.maydell@linaro.org> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 7bit X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::241 Subject: Re: [Qemu-arm] [Qemu-devel] [PATCH 09/15] target/arm: Don't store M profile PRIMASK and FAULTMASK in daif X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 03 Aug 2017 22:03:29 -0000 On 08/02/2017 09:43 AM, Peter Maydell wrote: > We currently store the M profile CPU register state PRIMASK and > FAULTMASK in the daif field of the CPU state in its I and F > bits. This is a legacy from the original implementation, which > tried to share the cpu_exec_interrupt code between A profile > and M profile. We've since separated out the two cases because > they are significantly different, so now there is no common > code between M and A profile which looks at env->daif: all the > uses are either in A-only or M-only code paths. Sharing the state > fields now is just confusing, and will make things awkward > when we implement v8M, where the PRIMASK and FAULTMASK > registers are banked between security states. > > Switch M profile over to using v7m.faultmask and v7m.primask > fields for these registers. > > Signed-off-by: Peter Maydell > --- > hw/intc/armv7m_nvic.c | 4 ++-- > target/arm/cpu.c | 5 ----- > target/arm/cpu.h | 4 +++- > target/arm/helper.c | 18 +++++------------- > target/arm/machine.c | 33 +++++++++++++++++++++++++++++++++ > 5 files changed, 43 insertions(+), 21 deletions(-) Reviewed-by: Richard Henderson r~ From MAILER-DAEMON Thu Aug 03 18:05:28 2017 Received: from list by lists.gnu.org with archive (Exim 4.71) id 1ddOFE-0001RH-Hh for mharc-qemu-arm@gnu.org; Thu, 03 Aug 2017 18:05:28 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:60488) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ddOFC-0001QD-A9 for qemu-arm@nongnu.org; Thu, 03 Aug 2017 18:05:27 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ddOFB-0002Er-Ij for qemu-arm@nongnu.org; Thu, 03 Aug 2017 18:05:26 -0400 Received: from mail-pf0-x244.google.com ([2607:f8b0:400e:c00::244]:34931) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ddOF6-00027c-SS; Thu, 03 Aug 2017 18:05:20 -0400 Received: by mail-pf0-x244.google.com with SMTP id j68so10511pfc.2; Thu, 03 Aug 2017 15:05:20 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:subject:to:cc:references:from:message-id:date:user-agent :mime-version:in-reply-to:content-language:content-transfer-encoding; bh=n8DMweNGGrDZxg7c8qIw7+GNC/NbvMc7onhDg0vXrM0=; b=k+edCeVdN/cX9vzb5WQgfen/7nH+Oo6KkmOrfafZzQomga4uQgm2YoOggzqIeqO18o VGI0GSYfbrNZ96ofajSvAfQgeQH6vtz4EF8z4JQ1Dx/hQs3QbfRcrFKhUp/eyfeBgbKc 0MihUQWSdVu0zJ8uG5Iz+jMehgIwXRcIpjOkmYWeFZf0lIGZRnvUzHBXqDE3VcsjJDQf jEtB8xxR0K2CaFmg5GXW8+TmUpo5NE8nnTFhwHzIjieUz8aZ/7KkEVSwF6yObPt57dcW qSi1saU1Qi3gk0UaavZ7Y7Wq0tkwAHXRzavsvazZZwTZ2n2wg0oFAJLyFRdEezezQZck SE0g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:subject:to:cc:references:from:message-id :date:user-agent:mime-version:in-reply-to:content-language :content-transfer-encoding; bh=n8DMweNGGrDZxg7c8qIw7+GNC/NbvMc7onhDg0vXrM0=; b=DZ5UHUPLYTb1kMa+OwNzNzZocnwG5CQ0zWqmBq7tOe9dd33dCTBUSaHg9fNkYqsPHy +LeV+CoNkuJPEazWvYGdnqVjjPdWg7i7DF+oqdB3wfO/ObHtabOK2YkPM/J3FfVMThTT YJuKex11OQuCn/Y9wRP6Khamm0KsgmQeMiEQIrfVxdwmEUuxltqtumAoqD74oBkZdO65 +qRevbv1YTuz+cIwENMTefK5pQ4jmKTaju162bx/vhNopvaUplSOlwI5eAaxzK1gce0x uU7X1zvMnvHpoDMoRxlh8IW4HcVoSd5wPF6rblj76A1tzwvv9uL2QCd1b445MSSZNIcR 16oQ== X-Gm-Message-State: AIVw113vqiQ8r9hYUSas1Uk9HJa5XoxN2iieBt8SVLqAwAd/VILoVJSI 5I7rcnHBN/nUGg== X-Received: by 10.99.107.193 with SMTP id g184mr227899pgc.167.1501797919661; Thu, 03 Aug 2017 15:05:19 -0700 (PDT) Received: from bigtime.twiddle.net (97-126-108-236.tukw.qwest.net. [97.126.108.236]) by smtp.googlemail.com with ESMTPSA id o10sm65950229pgc.81.2017.08.03.15.05.18 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 03 Aug 2017 15:05:19 -0700 (PDT) Sender: Richard Henderson To: "Edgar E. Iglesias" , Peter Maydell Cc: qemu-arm@nongnu.org, qemu-devel@nongnu.org, patches@linaro.org References: <1501692241-23310-1-git-send-email-peter.maydell@linaro.org> <1501692241-23310-10-git-send-email-peter.maydell@linaro.org> <20170803153800.GR4859@toto> From: Richard Henderson Message-ID: <854126f3-84da-087c-f35b-480165871e7f@twiddle.net> Date: Thu, 3 Aug 2017 15:05:17 -0700 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.2.1 MIME-Version: 1.0 In-Reply-To: <20170803153800.GR4859@toto> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 7bit X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::244 Subject: Re: [Qemu-arm] [Qemu-devel] [PATCH 09/15] target/arm: Don't store M profile PRIMASK and FAULTMASK in daif X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 03 Aug 2017 22:05:27 -0000 On 08/03/2017 08:38 AM, Edgar E. Iglesias wrote: >> + uint32_t primask; >> + uint32_t faultmask; > It seems like these could be booleans? I was thinking the same thing until I read the v8m description as a 32-bit register. This makes qemu match the spec, which has value. r~ From MAILER-DAEMON Thu Aug 03 18:13:38 2017 Received: from list by lists.gnu.org with archive (Exim 4.71) id 1ddON8-0004r9-Nv for mharc-qemu-arm@gnu.org; Thu, 03 Aug 2017 18:13:38 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:45762) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ddON6-0004om-FK for qemu-arm@nongnu.org; Thu, 03 Aug 2017 18:13:37 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ddON5-00065X-HJ for qemu-arm@nongnu.org; Thu, 03 Aug 2017 18:13:36 -0400 Received: from mail-pg0-x243.google.com ([2607:f8b0:400e:c05::243]:34331) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ddON1-0005yS-5I; Thu, 03 Aug 2017 18:13:31 -0400 Received: by mail-pg0-x243.google.com with SMTP id y192so15863pgd.1; Thu, 03 Aug 2017 15:13:31 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:subject:to:cc:references:from:message-id:date:user-agent :mime-version:in-reply-to:content-language:content-transfer-encoding; bh=XoA5lIoK7V0trv/sXsrkvd+2gS8SiJXFVCxxeqjZGG8=; b=qMatTagaPlsMOTT+zXfR+L0FPozBXVpD3eYfd+lJZfIgYof9Ei9B5ARHI9rSRyrtAm NVWwCaVG/usceZ6EjdoK1GDlvvPncoyDdwrHiNXbN+Ns2owWFh1M+cSuZJ/1WWYyir1a 0hu1cz0BP8g2s5nN6sgyhIrP3TLHuO3ASoFcAZ74Z4DU7nV74V7jSV3ic+hT+BbmCZ5V lZICbHFuyhZQY8FJTmUEr9HYQwJYH3WEw9wOTyySgeeJCZrIMpqBGog7CrJxQ5JNuwOD F2E0GIOq6ym39Xx938urQahE5pie1vWa6sV8BTuOpW0aToxCH45YHJ5z+0aXWFQ4N1aX AWAg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:subject:to:cc:references:from:message-id :date:user-agent:mime-version:in-reply-to:content-language :content-transfer-encoding; bh=XoA5lIoK7V0trv/sXsrkvd+2gS8SiJXFVCxxeqjZGG8=; b=KuNxd21Tl55UV33P3HMueZLMIvjctOBo2mWQfz1P9x35anG7eVX5FIg/CIKGN7FJ2v wT5lEiMISp7y8tN6zgatBodpDssq2341MkRA+DWQpxrzBq03nsv9zhugbpFu33geRN5f JmUGKSitpGGwkMjVfn+R6IxAGujBeKnIA6kFVnjv779vfYVVsvXBz6i+xkHteYwWWs+M 6mb3bawsdShEMDf/bM2/OFTE0s2fHgvP6+wnKcctSDsCVDBuLlite3AX/UlmnG3h3w9l dER0gvbp2EeQnRoBhJSzBwMuNmyNcV53ZlGHKi8qazY13SVRXUgSkh2BP+SmJ6K7ODL/ VQjA== X-Gm-Message-State: AIVw111lnSe3RaG+/FjbPSzgY9xOp9GAy8Hy4LnsXDIYbDJ/CwUaPeA3 wtE1Gu9a6oKJvg== X-Received: by 10.99.134.194 with SMTP id x185mr284245pgd.210.1501798409933; Thu, 03 Aug 2017 15:13:29 -0700 (PDT) Received: from bigtime.twiddle.net (97-126-108-236.tukw.qwest.net. [97.126.108.236]) by smtp.googlemail.com with ESMTPSA id c12sm1141pfe.154.2017.08.03.15.13.29 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 03 Aug 2017 15:13:29 -0700 (PDT) Sender: Richard Henderson To: Peter Maydell , qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: patches@linaro.org References: <1501692241-23310-1-git-send-email-peter.maydell@linaro.org> <1501692241-23310-11-git-send-email-peter.maydell@linaro.org> From: Richard Henderson Message-ID: <91f1649d-ffcf-85c5-b83b-644ad1875fcd@twiddle.net> Date: Thu, 3 Aug 2017 15:13:27 -0700 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.2.1 MIME-Version: 1.0 In-Reply-To: <1501692241-23310-11-git-send-email-peter.maydell@linaro.org> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 7bit X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::243 Subject: Re: [Qemu-arm] [Qemu-devel] [PATCH 10/15] target/arm: Don't use cpsr_write/cpsr_read to transfer M profile XPSR X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 03 Aug 2017 22:13:37 -0000 On 08/02/2017 09:43 AM, Peter Maydell wrote: > + if (val & XPSR_EXCP) { > + /* This is a CPSR format value from an older QEMU. (We can tell > + * because values transferred in XPSR format always have zero > + * for the EXCP field, and CPSR format will always have bit 4 > + * set in CPSR_M.) Rearrange it into XPSR format. The significant > + * differences are that the T bit is not in the same place, the > + * primask/faultmask info may be in the CPSR I and F bits, and > + * we do not want the mode bits. > + */ > + uint32_t newval = val; > + > + newval &= (CPSR_NZCV | CPSR_Q | CPSR_IT | CPSR_GE); > + if (val & CPSR_T) { > + newval |= XPSR_T; > + } > + /* If the I or F bits are set then this is a migration from > + * an old QEMU which still stored the M profile FAULTMASK > + * and PRIMASK in env->daif. For a new QEMU, the data is > + * transferred using the vmstate_m_faultmask_primask subsection. > + */ The second comment seems sort of redundant with the first now. r~ From MAILER-DAEMON Thu Aug 03 18:14:53 2017 Received: from list by lists.gnu.org with archive (Exim 4.71) id 1ddOOL-0005nk-GI for mharc-qemu-arm@gnu.org; Thu, 03 Aug 2017 18:14:53 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:47503) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ddOOJ-0005mT-Vo for qemu-arm@nongnu.org; Thu, 03 Aug 2017 18:14:52 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ddOOI-0007ct-W6 for qemu-arm@nongnu.org; Thu, 03 Aug 2017 18:14:51 -0400 Received: from mail-pg0-x242.google.com ([2607:f8b0:400e:c05::242]:34874) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ddOOE-0007XM-Nh; Thu, 03 Aug 2017 18:14:46 -0400 Received: by mail-pg0-x242.google.com with SMTP id l64so9025pge.2; Thu, 03 Aug 2017 15:14:46 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:subject:to:cc:references:from:message-id:date:user-agent :mime-version:in-reply-to:content-language:content-transfer-encoding; bh=96lbVeOk4Ip8MhkILEIN0IRgAK/hMOmNChGEhkZ3LZw=; b=b9lWxJwY4fBNOniJrK86AlvwzTHO+ygl6qKuRzYioUWOqbEy4f+j1EuoJ8U1Du4/bA 2z6CPnTgL7hfkzeufZS69j70sRyMrIOEql/VcVdBMegCH38fgPU0DlDiBLulprKvjULO OOktIGn43feecIG9Jnv88E7rsOygdKdEBx3BNxLWm1pywqIT8OM7zXnyORT15e+kK9CX gjrUXAk3QjWyZca4JNqWsdADy3HzzFqGJpxEIOpY87SCRMLTGeAi6/A0pDKyieaPzWFY QcBajlt2xO0+R8pLf2nY2HkdHNtOeqKBCF2p+GzbwqlnzfpvwLIY67YuGCEI6eMI5NQA LQTw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:subject:to:cc:references:from:message-id :date:user-agent:mime-version:in-reply-to:content-language :content-transfer-encoding; bh=96lbVeOk4Ip8MhkILEIN0IRgAK/hMOmNChGEhkZ3LZw=; b=to3nv41U0GbuBZmshbQWuiWe+1bfx+SUq8bmvcVCSmcg1ny+hCbNZXvCk0Inj+fXud 1XaFK690YBSKNHl367HpAfDbxXuFCEMqqLBQMDYJuzBuhxst51yajZb/jUVdOLEb0odq 3EKijANfYbf9mvN8pulSa1M95qgToYx4shw/loGL45qayIAwZEKp0xqqwtVaFX0wu5dX /RD0w4QapUUbXrVFz6KNFFDv3CvZ1tkMilMObE9Q9ghb0c3scRmj6v/lE441FeR6rLHj /OW+iHklnO2B0ftrklp67s0yGtA8uf6iWZD2QxUyePsgHt+IBnqFhO1t02hKv0uEYDx1 2VzQ== X-Gm-Message-State: AIVw110jhWkUs03lX3EbtlsK/pMblvGG3/TB9myGDVCnyqcWxudHTadQ AT9OGPnzetjg5g== X-Received: by 10.98.245.147 with SMTP id b19mr291492pfm.286.1501798485865; Thu, 03 Aug 2017 15:14:45 -0700 (PDT) Received: from bigtime.twiddle.net (97-126-108-236.tukw.qwest.net. [97.126.108.236]) by smtp.googlemail.com with ESMTPSA id q66sm1340pfb.188.2017.08.03.15.14.45 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 03 Aug 2017 15:14:45 -0700 (PDT) Sender: Richard Henderson To: Peter Maydell , qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: patches@linaro.org References: <1501692241-23310-1-git-send-email-peter.maydell@linaro.org> <1501692241-23310-12-git-send-email-peter.maydell@linaro.org> From: Richard Henderson Message-ID: <2f3523e9-a8b8-ed6d-3fae-33a4dfbaa6db@twiddle.net> Date: Thu, 3 Aug 2017 15:14:43 -0700 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.2.1 MIME-Version: 1.0 In-Reply-To: <1501692241-23310-12-git-send-email-peter.maydell@linaro.org> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 7bit X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::242 Subject: Re: [Qemu-arm] [Qemu-devel] [PATCH 11/15] target/arm: Make arm_cpu_dump_state() handle the M-profile XPSR X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 03 Aug 2017 22:14:53 -0000 On 08/02/2017 09:43 AM, Peter Maydell wrote: > Make the arm_cpu_dump_state() debug logging handle the M-profile XPSR > rather than assuming it's an A-profile CPSR. On M profile the PSR > line of a register dump will now look like this: > > XPSR=41000000 -Z-- T priv-thread > > Signed-off-by: Peter Maydell > --- > target/arm/translate.c | 58 ++++++++++++++++++++++++++++++++++---------------- > 1 file changed, 40 insertions(+), 18 deletions(-) Reviewed-by: Richard Henderson r~ From MAILER-DAEMON Thu Aug 03 18:15:42 2017 Received: from list by lists.gnu.org with archive (Exim 4.71) id 1ddOP7-0006a1-Tt for mharc-qemu-arm@gnu.org; Thu, 03 Aug 2017 18:15:41 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:48523) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ddOP5-0006Wt-LT for qemu-arm@nongnu.org; Thu, 03 Aug 2017 18:15:40 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ddOP4-0000DH-Jx for qemu-arm@nongnu.org; Thu, 03 Aug 2017 18:15:39 -0400 Received: from mail-pg0-x242.google.com ([2607:f8b0:400e:c05::242]:36629) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ddOOz-00006X-TO; Thu, 03 Aug 2017 18:15:34 -0400 Received: by mail-pg0-x242.google.com with SMTP id y129so6259pgy.3; Thu, 03 Aug 2017 15:15:33 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:subject:from:to:cc:references:message-id:date:user-agent :mime-version:in-reply-to:content-language:content-transfer-encoding; bh=cD9ZBnz3l+KRoCHqOqCWyge4jONGM1SP5msCYqhnKv8=; b=otazEBRi7cE0nbiAuIfXOGVHTz4JIVUAnZgBaxaPCccd52lnoeiBaccPAuPXSy+UqE lJkWubW9hfRmp331k4VzT1XuWrmAhrSiw60hIhaA8T2Ze29VK827qiuWb9PJWv0zpmGL sAZnTgiMTKdV8X5OesseG/pVTLTi04LUSgvrcVnZAmobyhfpLFEw8P7xZXPBkSukYb0O XWFSKjvifkDdFPUta4nAK8Q3SsL4lwQAHAqlHB9N+6VVDSCNeUORLPzmVQvZZLWilW4x TeDMXfCQczE81cD5tkbQaWCWxRxYO+0Tnm3pampXJsBwF3CC6wTRzaPNeAMX09X8Sm3Z wh1Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:subject:from:to:cc:references:message-id :date:user-agent:mime-version:in-reply-to:content-language :content-transfer-encoding; bh=cD9ZBnz3l+KRoCHqOqCWyge4jONGM1SP5msCYqhnKv8=; b=eQW7/Ai6zdPnM4Lc6GRyzYg2NxuqlQWy/Pt7vEUvGwstA2aZvTgCaF5QC5Cch8liXA RcSs6au5+tuFMWPmmFeQXgsNpKXygYJHqt/z6hghZlZMOphldp9kc/iREdFmtbn9IwT6 WriQBCHZkHOLdttZK9m7EVQrfjJjPoVofyYEUvP7DBtwoAbQ2pO9TbMG8oAFJaz3v+Y8 1AI5aG71KAhrNFa+l2Y9RUVfdGtvR9qe1zG9LjpyJrgeeJg/hyjaitcp0Hzq8SfEJnBS PSkmboSdTncw92NuwjC/XYiXLxCI00Q49z+UKz3IngVmaHwgMoAYU+I1mDdnEDaAZ4GF zcnQ== X-Gm-Message-State: AIVw1101ZAxI+7dtYI9B6ptqZO0rW0EdbWq7FcuZOtaWxSF/WbF2V749 Ip/5TPuIVBsMyQ== X-Received: by 10.84.241.14 with SMTP id a14mr290417pll.421.1501798533135; Thu, 03 Aug 2017 15:15:33 -0700 (PDT) Received: from bigtime.twiddle.net (97-126-108-236.tukw.qwest.net. [97.126.108.236]) by smtp.googlemail.com with ESMTPSA id n11sm33224pfg.15.2017.08.03.15.15.32 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 03 Aug 2017 15:15:32 -0700 (PDT) Sender: Richard Henderson From: Richard Henderson To: Peter Maydell , qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: patches@linaro.org References: <1501692241-23310-1-git-send-email-peter.maydell@linaro.org> <1501692241-23310-11-git-send-email-peter.maydell@linaro.org> <91f1649d-ffcf-85c5-b83b-644ad1875fcd@twiddle.net> Message-ID: Date: Thu, 3 Aug 2017 15:15:31 -0700 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.2.1 MIME-Version: 1.0 In-Reply-To: <91f1649d-ffcf-85c5-b83b-644ad1875fcd@twiddle.net> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 7bit X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::242 Subject: Re: [Qemu-arm] [Qemu-devel] [PATCH 10/15] target/arm: Don't use cpsr_write/cpsr_read to transfer M profile XPSR X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 03 Aug 2017 22:15:40 -0000 On 08/03/2017 03:13 PM, Richard Henderson wrote: > On 08/02/2017 09:43 AM, Peter Maydell wrote: >> + if (val & XPSR_EXCP) { >> + /* This is a CPSR format value from an older QEMU. (We can tell >> + * because values transferred in XPSR format always have zero >> + * for the EXCP field, and CPSR format will always have bit 4 >> + * set in CPSR_M.) Rearrange it into XPSR format. The significant >> + * differences are that the T bit is not in the same place, the >> + * primask/faultmask info may be in the CPSR I and F bits, and >> + * we do not want the mode bits. >> + */ >> + uint32_t newval = val; >> + >> + newval &= (CPSR_NZCV | CPSR_Q | CPSR_IT | CPSR_GE); >> + if (val & CPSR_T) { >> + newval |= XPSR_T; >> + } >> + /* If the I or F bits are set then this is a migration from >> + * an old QEMU which still stored the M profile FAULTMASK >> + * and PRIMASK in env->daif. For a new QEMU, the data is >> + * transferred using the vmstate_m_faultmask_primask subsection. >> + */ > > The second comment seems sort of redundant with the first now. ... and I meant to say, otherwise, Reviewed-by: Richard Henderson r~ From MAILER-DAEMON Thu Aug 03 18:16:22 2017 Received: from list by lists.gnu.org with archive (Exim 4.71) id 1ddOPm-0007Sf-Gi for mharc-qemu-arm@gnu.org; Thu, 03 Aug 2017 18:16:22 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:49400) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ddOPk-0007Qg-4p for qemu-arm@nongnu.org; Thu, 03 Aug 2017 18:16:20 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ddOPj-0001A1-9k for qemu-arm@nongnu.org; Thu, 03 Aug 2017 18:16:20 -0400 Received: from mail-pg0-x244.google.com ([2607:f8b0:400e:c05::244]:34524) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ddOPe-00010h-P9; Thu, 03 Aug 2017 18:16:15 -0400 Received: by mail-pg0-x244.google.com with SMTP id y192so20733pgd.1; Thu, 03 Aug 2017 15:16:14 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:subject:to:cc:references:from:message-id:date:user-agent :mime-version:in-reply-to:content-language:content-transfer-encoding; bh=LyXqi9LTozfyW2U7LHP51RJiIJyUMv991pwF5h5q2cM=; b=Zi++Opg38Jpp20wILvytL24I2I8fomEt77DelFf/vKjiWoqHnZnIjBZye3kBM44VO+ qPc050OKRJol7AQUHO96MhKWrWXrxGicW82Jb8/W5IvIe6ns+8Eq7YtPV9xN5T6QDbCK wDJo1Ru8huifeQQmksa3+NX/87B/cd5jKuEOsSxnhjw/Hu4IYsqXu+IeLWub96dvoFpe comZ7/4nxH6WLLUXVWtXATgKAjRErEE4oq/yC6QEPVKILOBqCyS3a7HD/7mLJeUjGHpZ 0lKLrmx6lm74A59A+OeNydlixXyKaS1YmBHpxyFREZDP1MOqB/cZ9LfCT2FQNh2/Icvw Y+4w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:subject:to:cc:references:from:message-id :date:user-agent:mime-version:in-reply-to:content-language :content-transfer-encoding; bh=LyXqi9LTozfyW2U7LHP51RJiIJyUMv991pwF5h5q2cM=; b=seYwLn1mdgoG4ZsnEVdmskQjeU5uPweQy2BxXdqEsLIppijaPGOgX0BhgKR79qnRAt /oI3pISZefuR0oaMYDiC8AFnCDtlxd2mwMOeHSlT58CS8psB0kKgMKCDaPTr2glkhVvF Y9QsHv51xUUT3/z9EFnR6bzGTKteHFF4ZIsHU4iPImNDY4xrO/l+gKzv1jvWcD3+eHY7 weasBCfSnQCy2IJfk/ZmC1Wl71VkZIqOqDzQoT1vwzQaGrzmG3Xd2W45PGlsLZeLUD/H ldupDeLlxFclIsaFpU/GQAuxuJ8NDCof2Ur9BFXNfQ897blcLzKJeFkNrGFDbiLS5XHP gMSw== X-Gm-Message-State: AIVw1124lAxAluDKihH+1mRdalG0b9mJJEImjNUYIgG9G8Z5/G0PGY8R Ao9nwdh6QPFKV/aeMD0= X-Received: by 10.98.7.204 with SMTP id 73mr328448pfh.110.1501798573940; Thu, 03 Aug 2017 15:16:13 -0700 (PDT) Received: from bigtime.twiddle.net (97-126-108-236.tukw.qwest.net. [97.126.108.236]) by smtp.googlemail.com with ESMTPSA id v9sm20772pgo.39.2017.08.03.15.16.12 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 03 Aug 2017 15:16:13 -0700 (PDT) Sender: Richard Henderson To: Peter Maydell , qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: patches@linaro.org References: <1501692241-23310-1-git-send-email-peter.maydell@linaro.org> <1501692241-23310-13-git-send-email-peter.maydell@linaro.org> From: Richard Henderson Message-ID: <2266f042-5c2c-301e-f5e1-9e19c7879e37@twiddle.net> Date: Thu, 3 Aug 2017 15:16:11 -0700 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.2.1 MIME-Version: 1.0 In-Reply-To: <1501692241-23310-13-git-send-email-peter.maydell@linaro.org> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 7bit X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::244 Subject: Re: [Qemu-arm] [Qemu-devel] [PATCH 12/15] target/arm: Don't calculate lr in arm_v7m_cpu_do_interrupt() until needed X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 03 Aug 2017 22:16:21 -0000 On 08/02/2017 09:43 AM, Peter Maydell wrote: > Move the code in arm_v7m_cpu_do_interrupt() that calculates the > magic LR value down to when we're actually going to use it. > Having the calculation and use so far apart makes the code > a little harder to understand than it needs to be. > > Signed-off-by: Peter Maydell > --- > target/arm/helper.c | 15 ++++++++------- > 1 file changed, 8 insertions(+), 7 deletions(-) Reviewed-by: Richard Henderson r~ From MAILER-DAEMON Thu Aug 03 18:18:53 2017 Received: from list by lists.gnu.org with archive (Exim 4.71) id 1ddOSD-0001Gg-6a for mharc-qemu-arm@gnu.org; Thu, 03 Aug 2017 18:18:53 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:52445) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ddOSA-00018W-CZ for qemu-arm@nongnu.org; Thu, 03 Aug 2017 18:18:51 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ddOS9-0003Fc-Lw for qemu-arm@nongnu.org; Thu, 03 Aug 2017 18:18:50 -0400 Received: from mail-pg0-x242.google.com ([2607:f8b0:400e:c05::242]:36838) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ddOS5-0003B1-EG; Thu, 03 Aug 2017 18:18:45 -0400 Received: by mail-pg0-x242.google.com with SMTP id y129so12269pgy.3; Thu, 03 Aug 2017 15:18:45 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:subject:to:cc:references:from:message-id:date:user-agent :mime-version:in-reply-to:content-language:content-transfer-encoding; bh=d++pVB3mdq1hoW1aIbEjb5xIHBEMklaXZ64uEqmFaoU=; b=vZUXU9uKtQrDX2UJgynqV3bCKs9Jbjd8B2QQoRQsBEHAvwjolGo+u1Ajx2aDhN+cfu ZAEtbEzlLdaGVmJRWcqwD3elLLaXqp/82pxmFZJ6USDhyreQIBNw+pmq3aV9vrUNq6vP UPtNqkpOQROb53vb08BkmxBJLsw7Qm9vYIjIt2TOjMY9Df8nBm0Z8Cp6F+RbPEMWHOTj P202pzvA4WFFe5dkRoM6t4dh2HNKD6CKV2xsbDDT2rc2m5f0ZZSUDXwFOwNT7tj6zPNf c/GBdmqx6QakARjcuCkGPoq+ctAtCke5yb3WNQKQN4tuRDqhK49X8FMnXDeOM9Uw02k4 RqfQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:subject:to:cc:references:from:message-id :date:user-agent:mime-version:in-reply-to:content-language :content-transfer-encoding; bh=d++pVB3mdq1hoW1aIbEjb5xIHBEMklaXZ64uEqmFaoU=; b=i84ivKs0jMLuI99QKSQOU+ULWSuXF6+4kC/n/+y9sIXbVOxJSN+B0QigqaWfeLdUTM ZKVjiLBXL0Um1SqOtf+DI7A5QP/CxAxRG0rnVIE4uf8CT+EtGDIMDHRoUU8I3YFmkKEH BGo+w3xXYI/d5sCV5hIZ2mUdo1iABTPRlL3H2YfGAtHs3eD/qG799dklpTbm/Owifn2H QJZXtXO9k6rAHLA8g+VAgBn+Vzn+tSbFthI2ylQn3Vr19AXaQa5jAAMowZIgOaHhHc0X atay6qKYhWz/OKY9VwiS6a6OP/9Yzeiwvhph/g5MTlpLHzYtE5NxnJhAnDpcaZtXhwEQ 11Ew== X-Gm-Message-State: AIVw113K5SEEZtH78S+nJGR9dGlvJMg1vo2YTR9xsEzlR2HQPizi45AR RfLbrpzZfH34NF7zB94= X-Received: by 10.98.211.197 with SMTP id z66mr332139pfk.160.1501798724631; Thu, 03 Aug 2017 15:18:44 -0700 (PDT) Received: from bigtime.twiddle.net (97-126-108-236.tukw.qwest.net. [97.126.108.236]) by smtp.googlemail.com with ESMTPSA id y6sm23453pgq.41.2017.08.03.15.18.43 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 03 Aug 2017 15:18:43 -0700 (PDT) Sender: Richard Henderson To: Peter Maydell , qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: patches@linaro.org References: <1501692241-23310-1-git-send-email-peter.maydell@linaro.org> <1501692241-23310-14-git-send-email-peter.maydell@linaro.org> From: Richard Henderson Message-ID: Date: Thu, 3 Aug 2017 15:18:42 -0700 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.2.1 MIME-Version: 1.0 In-Reply-To: <1501692241-23310-14-git-send-email-peter.maydell@linaro.org> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 7bit X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::242 Subject: Re: [Qemu-arm] [Qemu-devel] [PATCH 13/15] target/arm: Create and use new function arm_v7m_is_handler_mode() X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 03 Aug 2017 22:18:51 -0000 On 08/02/2017 09:43 AM, Peter Maydell wrote: > Add a utility function for testing whether the CPU is in Handler > mode; this is just a check whether v7m.exception is non-zero, but > we do it in several places and it makes the code a bit easier > to read to not have to mentally figure out what the test is testing. > > Signed-off-by: Peter Maydell > --- > target/arm/cpu.h | 10 ++++++++-- > target/arm/helper.c | 8 ++++---- > 2 files changed, 12 insertions(+), 6 deletions(-) Reviewed-by: Richard Henderson r~ From MAILER-DAEMON Thu Aug 03 18:19:56 2017 Received: from list by lists.gnu.org with archive (Exim 4.71) id 1ddOTE-00027C-8u for mharc-qemu-arm@gnu.org; Thu, 03 Aug 2017 18:19:56 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:54018) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ddOTB-00024r-SH for qemu-arm@nongnu.org; Thu, 03 Aug 2017 18:19:54 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ddOTB-0004JK-1z for qemu-arm@nongnu.org; Thu, 03 Aug 2017 18:19:53 -0400 Received: from mail-pg0-x242.google.com ([2607:f8b0:400e:c05::242]:34748) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ddOT6-0004Dl-Ca; Thu, 03 Aug 2017 18:19:48 -0400 Received: by mail-pg0-x242.google.com with SMTP id y192so26976pgd.1; Thu, 03 Aug 2017 15:19:48 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:subject:to:cc:references:from:message-id:date:user-agent :mime-version:in-reply-to:content-language:content-transfer-encoding; bh=fgkSuR3ww96p2eGv1P24d61/i3E9vtu2KLwmVgtulsM=; b=HMAu+YgE0PonZbWSvz2V0+l+matewYZWL70d9TK+vSGN2pqni7dCgCd8HKI/TCcq2b 56XYTfUKF4FE4a/96J2i+1oAILh6LJg5PS8DihVKtgTSqLBoQldbzs2LpNvrJMkFYBjf 5/eXAOU4JK8PXIQmxaY4gShxqsw2RlyGxBaEFy9hc04VlfX++RoQNmkFn9q5OsLObRhG 8ABXPyuBjt88UXREnCqJ6NHu93RnIJJ1iqQXHaRjiOEjRziXBRr4A+7sJ+EvWsimslnG Hl/1dXORL6gbGRd37Q7H1pGja8I+TwdsrU6VvrZoguf1/bxxWuLoUssBEC8PKOgl4Z85 6LgA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:subject:to:cc:references:from:message-id :date:user-agent:mime-version:in-reply-to:content-language :content-transfer-encoding; bh=fgkSuR3ww96p2eGv1P24d61/i3E9vtu2KLwmVgtulsM=; b=L1ChaR2BO+/IEQwvB9+4Ku4idoMDuSqxIW+FLoVcMczOw3V7IvYxp51StPjGFBRM15 qSeXB40+uX9zFBB7LFO5I7yvkC3VHODfwbNz8k1uDESMCtxgIsl/lxUUm61cdB5OH/9U YQOi+5p3xuXnppB4s9hDyMDnJIMg34VbuSsrd+yDyoRhlpFbyyiaow52dSGrwr4qDWad q1lEgcRWFi71otA0wF1+KYWKWXkA6QYuXYEQgNp1NFYd9rL6p4+HNKd90Udwe2RVd/sm UFcvcfPnD2ovXTlUJ3r9lDcfWCvEmgxp0HFiOjSgCPczr/EmRUAAnmDFmCzDKNLkgRYx rcTw== X-Gm-Message-State: AIVw112swvDK1wl+kbhbRwHgwQh7A75oVT/nnEyi/bfF0pnL8xIZmQyQ VJNnsHNoI15g6g== X-Received: by 10.84.212.1 with SMTP id d1mr339576pli.17.1501798787636; Thu, 03 Aug 2017 15:19:47 -0700 (PDT) Received: from bigtime.twiddle.net (97-126-108-236.tukw.qwest.net. [97.126.108.236]) by smtp.googlemail.com with ESMTPSA id x29sm40141pff.2.2017.08.03.15.19.46 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 03 Aug 2017 15:19:47 -0700 (PDT) Sender: Richard Henderson To: Peter Maydell , qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: patches@linaro.org References: <1501692241-23310-1-git-send-email-peter.maydell@linaro.org> <1501692241-23310-15-git-send-email-peter.maydell@linaro.org> From: Richard Henderson Message-ID: <9ebbff0f-4aef-3032-7691-15ccf34a660d@twiddle.net> Date: Thu, 3 Aug 2017 15:19:45 -0700 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.2.1 MIME-Version: 1.0 In-Reply-To: <1501692241-23310-15-git-send-email-peter.maydell@linaro.org> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 7bit X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::242 Subject: Re: [Qemu-arm] [Qemu-devel] [PATCH 14/15] armv7m_nvic.h: Move from include/hw/arm to include/hw/intc X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 03 Aug 2017 22:19:54 -0000 On 08/02/2017 09:44 AM, Peter Maydell wrote: > The armv7m_nvic.h header file was accidentally placed in > include/hw/arm; move it to include/hw/intc to match where > its corresponding .c file lives. > > Signed-off-by: Peter Maydell > --- > hw/intc/armv7m_nvic.c | 2 +- > include/hw/arm/armv7m.h | 2 +- > include/hw/{arm => intc}/armv7m_nvic.h | 0 > 3 files changed, 2 insertions(+), 2 deletions(-) > rename include/hw/{arm => intc}/armv7m_nvic.h (100%) Reviewed-by: Richard Henderson r~ From MAILER-DAEMON Thu Aug 03 18:23:29 2017 Received: from list by lists.gnu.org with archive (Exim 4.71) id 1ddOWf-0003wB-89 for mharc-qemu-arm@gnu.org; Thu, 03 Aug 2017 18:23:29 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:59535) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ddOWd-0003uw-D3 for qemu-arm@nongnu.org; Thu, 03 Aug 2017 18:23:28 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ddOWc-000055-G4 for qemu-arm@nongnu.org; Thu, 03 Aug 2017 18:23:27 -0400 Received: from mail-pg0-x241.google.com ([2607:f8b0:400e:c05::241]:37498) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ddOWY-0008Qa-B0; Thu, 03 Aug 2017 18:23:22 -0400 Received: by mail-pg0-x241.google.com with SMTP id 83so17112pgb.4; Thu, 03 Aug 2017 15:23:22 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:subject:to:cc:references:from:message-id:date:user-agent :mime-version:in-reply-to:content-language:content-transfer-encoding; bh=enTBqbNyKcW7OdA4JXMST5945WlM1ngbB153j3OJkrs=; b=YwWD9NigjhSzu5+y+gaKc1raEfh/SrAfGjNs5GSwcxHF/e+k1B0Lktvy0vsMjkkT5a wuqKHE1RJIdvldMRegbvzNY5qx5h2uETJR7KRBN4VjTDohOMxH3aEPBXjE7lzX6hA3bu 0UfEWfJ8E+coKizorTNiYwWPZ/tP0OVDm0sCRU3GAc7A1SRis9MVetgr/dLMsY0tHuMk wSm/lTwgCjCpF4m4HXnnvHmgkxGhaevKNuv0VayWq+nsNtxmSIyaqFo9IoCU1Mc0updf BIi0QH8LMA/KlgsRpF+ddMT8Po+PNR5jaHrVcqJyOkmAfn/xIlOIvF78Rhy1UKw93QMP FmZQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:subject:to:cc:references:from:message-id :date:user-agent:mime-version:in-reply-to:content-language :content-transfer-encoding; bh=enTBqbNyKcW7OdA4JXMST5945WlM1ngbB153j3OJkrs=; b=ErVCUZpGn21TAJpHLDGEpWSYMY+ENOrfdONEIEpjIR1jzwRtwFIuLy/UhfL4oMqMCj 93b8Wkz6mg+z82NPljzLWGVx0oP6ioahQYC3AjX35tWyGCdHy4R6Sn7Qfxgfcq6aAhdo F56Vq2ccrv+wPgHKTKPlZzICgx7pjdMsrH42TvauHs+1RRqdn70rQ5sVoZip35ubtEEn wmJr27iM1DUcfGn0/vxayou6miNih7mrxg2XcEDBCX9RJu5K1BpcvTWHE5+smrCIlKjI YC52Fe/7Bm/W93dlr/eMumahMcOzQpu49qSYhSm0ZhMR4FC/K/hPPsu70pLMaofplq3G Kpiw== X-Gm-Message-State: AIVw1104kwB1uJNdGSff8zh8TVrtciMXbTiAKsdWEtWoC1YqW31Jga6I 7DX5Ecbh1SzPDQ== X-Received: by 10.84.213.137 with SMTP id g9mr320636pli.325.1501799001434; Thu, 03 Aug 2017 15:23:21 -0700 (PDT) Received: from bigtime.twiddle.net (97-126-108-236.tukw.qwest.net. [97.126.108.236]) by smtp.googlemail.com with ESMTPSA id u37sm19844pgn.74.2017.08.03.15.23.20 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 03 Aug 2017 15:23:20 -0700 (PDT) Sender: Richard Henderson To: Peter Maydell , qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: patches@linaro.org References: <1501692241-23310-1-git-send-email-peter.maydell@linaro.org> <1501692241-23310-16-git-send-email-peter.maydell@linaro.org> From: Richard Henderson Message-ID: Date: Thu, 3 Aug 2017 15:23:19 -0700 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.2.1 MIME-Version: 1.0 In-Reply-To: <1501692241-23310-16-git-send-email-peter.maydell@linaro.org> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 7bit X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::241 Subject: Re: [Qemu-arm] [Qemu-devel] [PATCH 15/15] nvic: Implement "user accesses BusFault" SCS region behaviour X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 03 Aug 2017 22:23:28 -0000 On 08/02/2017 09:44 AM, Peter Maydell wrote: > The ARMv7M architecture specifies that most of the addresses in the > PPB region (which includes the NVIC, systick and system registers) > are not accessible to unprivileged accesses, which should > BusFault with a few exceptions: > * the STIR is configurably user-accessible > * the ITM (which we don't implement at all) is always > user-accessible > > Implement this by switching the register access functions > to the _with_attrs scheme that lets us distinguish user > mode accesses. > > This allows us to pull the handling of the CCR.USERSETMPEND > flag up to the level where we can make it generate a BusFault > as it should for non-permitted accesses. > > Note that until the core ARM CPU code implements turning > MEMTX_ERROR into a BusFault the registers will continue to > act as RAZ/WI to user accesses. > > Signed-off-by: Peter Maydell > --- > hw/intc/armv7m_nvic.c | 58 ++++++++++++++++++++++++++++++++++++--------------- > 1 file changed, 41 insertions(+), 17 deletions(-) Reviewed-by: Richard Henderson r~ From MAILER-DAEMON Fri Aug 04 00:18:35 2017 Received: from list by lists.gnu.org with archive (Exim 4.71) id 1ddU4J-0006qd-0d for mharc-qemu-arm@gnu.org; Fri, 04 Aug 2017 00:18:35 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:51732) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ddU4G-0006ob-D4 for qemu-arm@nongnu.org; Fri, 04 Aug 2017 00:18:33 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ddU4F-0006JF-Hk for qemu-arm@nongnu.org; Fri, 04 Aug 2017 00:18:32 -0400 Received: from szxga02-in.huawei.com ([45.249.212.188]:4409) by eggs.gnu.org with esmtps (TLS1.0:RSA_ARCFOUR_SHA1:16) (Exim 4.71) (envelope-from ) id 1ddU4A-0006BQ-Mf; Fri, 04 Aug 2017 00:18:27 -0400 Received: from 172.30.72.56 (EHLO DGGEML403-HUB.china.huawei.com) ([172.30.72.56]) by dggrg02-dlp.huawei.com (MOS 4.4.6-GA FastPath queued) with ESMTP id ASU19231; Fri, 04 Aug 2017 12:18:19 +0800 (CST) Received: from linux.huawei.com (10.67.187.203) by DGGEML403-HUB.china.huawei.com (10.3.17.33) with Microsoft SMTP Server id 14.3.301.0; Fri, 4 Aug 2017 12:18:10 +0800 From: Dongjiu Geng To: , , , , , , CC: , , Date: Fri, 4 Aug 2017 12:37:55 +0800 Message-ID: <1501821475-14647-4-git-send-email-gengdongjiu@huawei.com> X-Mailer: git-send-email 1.7.7 In-Reply-To: <1501821475-14647-1-git-send-email-gengdongjiu@huawei.com> References: <1501821475-14647-1-git-send-email-gengdongjiu@huawei.com> MIME-Version: 1.0 Content-Type: text/plain X-Originating-IP: [10.67.187.203] X-CFilter-Loop: Reflected X-Mirapoint-Virus-RAPID-Raw: score=unknown(0), refid=str=0001.0A020201.5983F58C.00DD, ss=1, re=0.000, recu=0.000, reip=0.000, cl=1, cld=1, fgs=0, ip=0.0.0.0, so=2014-11-16 11:51:01, dmn=2013-03-21 17:37:32 X-Mirapoint-Loop-Id: ee31a131f885d8f484333c02c95efcd0 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.4.x-2.6.x [generic] [fuzzy] X-Received-From: 45.249.212.188 Subject: [Qemu-arm] [PATCH v6 3/3] ACPI: build and enable APEI GHES in the Makefile and configuration X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 04 Aug 2017 04:18:33 -0000 Add CONFIG_ACPI_APEI configuration in the Makefile and enable it in the arm-softmmu.mak Signed-off-by: Dongjiu Geng --- thanks a lot Michael and Laszlo's review and comments: change since v5: (1) no change change since v4: (1) fix email threading in this series is incorrect issue change since v3: (1) change name to "CONFIG_ACPI_APEI" from CONFIG_ACPI_APEI_GENERATION --- default-configs/arm-softmmu.mak | 1 + hw/acpi/Makefile.objs | 1 + 2 files changed, 2 insertions(+) diff --git a/default-configs/arm-softmmu.mak b/default-configs/arm-softmmu.mak index 1e3bd2b..ee6f5fc 100644 --- a/default-configs/arm-softmmu.mak +++ b/default-configs/arm-softmmu.mak @@ -121,3 +121,4 @@ CONFIG_ACPI=y CONFIG_SMBIOS=y CONFIG_ASPEED_SOC=y CONFIG_GPIO_KEY=y +CONFIG_ACPI_APEI=y diff --git a/hw/acpi/Makefile.objs b/hw/acpi/Makefile.objs index 11c35bc..bafb148 100644 --- a/hw/acpi/Makefile.objs +++ b/hw/acpi/Makefile.objs @@ -6,6 +6,7 @@ common-obj-$(CONFIG_ACPI_MEMORY_HOTPLUG) += memory_hotplug.o common-obj-$(CONFIG_ACPI_CPU_HOTPLUG) += cpu.o common-obj-$(CONFIG_ACPI_NVDIMM) += nvdimm.o common-obj-$(CONFIG_ACPI_VMGENID) += vmgenid.o +common-obj-$(CONFIG_ACPI_APEI) += hest_ghes.o common-obj-$(call lnot,$(CONFIG_ACPI_X86)) += acpi-stub.o common-obj-y += acpi_interface.o -- 1.8.3.1 From MAILER-DAEMON Fri Aug 04 00:18:37 2017 Received: from list by lists.gnu.org with archive (Exim 4.71) id 1ddU4L-0006wS-9B for mharc-qemu-arm@gnu.org; Fri, 04 Aug 2017 00:18:37 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:51787) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ddU4I-0006pm-Ad for qemu-arm@nongnu.org; Fri, 04 Aug 2017 00:18:35 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ddU4G-0006KZ-Fa for qemu-arm@nongnu.org; Fri, 04 Aug 2017 00:18:34 -0400 Received: from szxga02-in.huawei.com ([45.249.212.188]:4412) by eggs.gnu.org with esmtps (TLS1.0:RSA_ARCFOUR_SHA1:16) (Exim 4.71) (envelope-from ) id 1ddU4A-0006BN-S9; Fri, 04 Aug 2017 00:18:27 -0400 Received: from 172.30.72.56 (EHLO DGGEML403-HUB.china.huawei.com) ([172.30.72.56]) by dggrg02-dlp.huawei.com (MOS 4.4.6-GA FastPath queued) with ESMTP id ASU19233; Fri, 04 Aug 2017 12:18:19 +0800 (CST) Received: from linux.huawei.com (10.67.187.203) by DGGEML403-HUB.china.huawei.com (10.3.17.33) with Microsoft SMTP Server id 14.3.301.0; Fri, 4 Aug 2017 12:18:09 +0800 From: Dongjiu Geng To: , , , , , , CC: , , Date: Fri, 4 Aug 2017 12:37:53 +0800 Message-ID: <1501821475-14647-2-git-send-email-gengdongjiu@huawei.com> X-Mailer: git-send-email 1.7.7 In-Reply-To: <1501821475-14647-1-git-send-email-gengdongjiu@huawei.com> References: <1501821475-14647-1-git-send-email-gengdongjiu@huawei.com> MIME-Version: 1.0 Content-Type: text/plain X-Originating-IP: [10.67.187.203] X-CFilter-Loop: Reflected X-Mirapoint-Virus-RAPID-Raw: score=unknown(0), refid=str=0001.0A020206.5983F58C.0122, ss=1, re=0.000, recu=0.000, reip=0.000, cl=1, cld=1, fgs=0, ip=0.0.0.0, so=2014-11-16 11:51:01, dmn=2013-03-21 17:37:32 X-Mirapoint-Loop-Id: e242c920ac85dab15391efa2fccc8621 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.4.x-2.6.x [generic] [fuzzy] X-Received-From: 45.249.212.188 Subject: [Qemu-arm] [PATCH v6 1/3] ACPI: add APEI/HEST/CPER structures and macros X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 04 Aug 2017 04:18:36 -0000 (1) Add related APEI/HEST table structures and macros, these definition refer to ACPI 6.1 and UEFI 2.6 spec. (2) Add generic error status block and CPER memory section definition, user space only handle memory section errors. Signed-off-by: Dongjiu Geng --- thanks Michael and Laszlo's review: change since V5: (1) update the commit message title (2) remove UUID_BE and UEFI_CPER_SEC_PLATFORM_MEM macros (3) remove including "qemu/uuid.h" file in this patch (4) remove including "hest_ghes.h" file in this patch (5) drop "this is" from the comment of structures and macros (6) replace the "QemuUUID section_type_le" to "uint8_t section_type_le[16]" chnage since v4: (1) fix email threading in this series is incorrect issue change since v3: (1) separate the original one patch into three patches: one is new ACPI structures and macros, another is C source file to generate ACPI HEST table and dynamically record CPER ,final patch is the change about Makefile and configuration (2) add comments about where the ACPI structures and macros come from, for example, they come from the UEFI Spec 2.6, "xxxxxxxxxxxx"; ACPI 6.1 spec, "xxxxxxxxxxxxxx". (3) correct the macros name, for emaple, prefix some macro names with "UEFI_". (4) remove the uuid_le struct and use the QemuUUID in the include/qemu/uuid.h" (5) remove the duplicate ACPI address space, because it already defined in the "include/hw/acpi/aml-build.h" (6) remove the acpi_generic_address structure because same definition exists in the AcpiGenericAddress. (7) rename the struct acpi_hest_notify to AcpiHestNotifyType (8) rename the struct acpi_hest_types to AcpiHestSourceType (9) rename enum constants AcpiHestSourceType to ACPI_HEST_SOURCE_xxx from ACPI_HEST_TYPE_xxx (10) remove the NOT_USED{3,4,5} enum constants in the AcpiHestSourceType. (11) add missed QEMU_PACKED for the struct definition. (12) remove the defnition of AcpiGenericErrorData, and rename the AcpiGenericErrorDataV300 to AcpiGenericErrorData. (13) use the QemuUUID type for the "section_type" field AcpiGenericErrorData, and rename it to section_type_le. (14) moving type AcpiGenericErrorSeverity above AcpiGenericErrorData and AcpiGenericErrorDataV300, and remarking on the "error_severity" fields that they take their values from AcpiGenericErrorSeverity (15) remove the wrongly call to BERT(Boot Error Record Table) (16) add comments for the struction member, for example, pint out that the block_status member in the AcpiGenericErrorStatus is a bitmask composed of ACPI_GEBS_xxx macros (17) remove the hardware error source notification type list, and rename the MAX_ERROR_SOURCE_COUNT_V6 to ACPI_HEST_NOTIFY_RESERVED. (18) remove the physical_addr member of GhesErrorState (19) change the "uint64_t ghes_addr_le[8]" in GhesErrorState to uint64_t ghes_addr_le (20) change the second parameter to "error_physical_addr" in the ghes_update_guest API statement --- include/hw/acpi/acpi-defs.h | 193 ++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 193 insertions(+) diff --git a/include/hw/acpi/acpi-defs.h b/include/hw/acpi/acpi-defs.h index 4cc3630..ff9525e 100644 --- a/include/hw/acpi/acpi-defs.h +++ b/include/hw/acpi/acpi-defs.h @@ -295,6 +295,44 @@ typedef struct AcpiMultipleApicTable AcpiMultipleApicTable; #define ACPI_APIC_GENERIC_TRANSLATOR 15 #define ACPI_APIC_RESERVED 16 /* 16 and greater are reserved */ +/* UEFI Spec 2.6, "N.2.5 Memory Error Section */ +#define UEFI_CPER_MEM_VALID_ERROR_STATUS 0x0001 +#define UEFI_CPER_MEM_VALID_PA 0x0002 +#define UEFI_CPER_MEM_VALID_PA_MASK 0x0004 +#define UEFI_CPER_MEM_VALID_NODE 0x0008 +#define UEFI_CPER_MEM_VALID_CARD 0x0010 +#define UEFI_CPER_MEM_VALID_MODULE 0x0020 +#define UEFI_CPER_MEM_VALID_BANK 0x0040 +#define UEFI_CPER_MEM_VALID_DEVICE 0x0080 +#define UEFI_CPER_MEM_VALID_ROW 0x0100 +#define UEFI_CPER_MEM_VALID_COLUMN 0x0200 +#define UEFI_CPER_MEM_VALID_BIT_POSITION 0x0400 +#define UEFI_CPER_MEM_VALID_REQUESTOR 0x0800 +#define UEFI_CPER_MEM_VALID_RESPONDER 0x1000 +#define UEFI_CPER_MEM_VALID_TARGET 0x2000 +#define UEFI_CPER_MEM_VALID_ERROR_TYPE 0x4000 +#define UEFI_CPER_MEM_VALID_RANK_NUMBER 0x8000 +#define UEFI_CPER_MEM_VALID_CARD_HANDLE 0x10000 +#define UEFI_CPER_MEM_VALID_MODULE_HANDLE 0x20000 +#define UEFI_CPER_MEM_ERROR_TYPE_MULTI_ECC 3 + +/* From the ACPI 6.1 spec, "18.3.2.9 Hardware Error Notification" */ + +enum AcpiHestNotifyType { + ACPI_HEST_NOTIFY_POLLED = 0, + ACPI_HEST_NOTIFY_EXTERNAL = 1, + ACPI_HEST_NOTIFY_LOCAL = 2, + ACPI_HEST_NOTIFY_SCI = 3, + ACPI_HEST_NOTIFY_NMI = 4, + ACPI_HEST_NOTIFY_CMCI = 5, /* ACPI 5.0 */ + ACPI_HEST_NOTIFY_MCE = 6, /* ACPI 5.0 */ + ACPI_HEST_NOTIFY_GPIO = 7, /* ACPI 6.0 */ + ACPI_HEST_NOTIFY_SEA = 8, /* ACPI 6.1 */ + ACPI_HEST_NOTIFY_SEI = 9, /* ACPI 6.1 */ + ACPI_HEST_NOTIFY_GSIV = 10, /* ACPI 6.1 */ + ACPI_HEST_NOTIFY_RESERVED = 11 /* 11 and greater are reserved */ +}; + /* * MADT sub-structures (Follow MULTIPLE_APIC_DESCRIPTION_TABLE) */ @@ -475,6 +513,161 @@ struct AcpiSystemResourceAffinityTable } QEMU_PACKED; typedef struct AcpiSystemResourceAffinityTable AcpiSystemResourceAffinityTable; +/* Hardware Error Notification, from the ACPI 6.1 + * spec, "18.3.2.9 Hardware Error Notification" + */ +struct AcpiHestNotify { + uint8_t type; + uint8_t length; + uint16_t config_write_enable; + uint32_t poll_interval; + uint32_t vector; + uint32_t polling_threshold_value; + uint32_t polling_threshold_window; + uint32_t error_threshold_value; + uint32_t error_threshold_window; +} QEMU_PACKED; +typedef struct AcpiHestNotify AcpiHestNotify; + +/* From ACPI 6.1, sections "18.3.2.1 IA-32 Architecture Machine + * Check Exception" through "18.3.2.8 Generic Hardware Error Source version 2". + */ +enum AcpiHestSourceType { + ACPI_HEST_SOURCE_IA32_CHECK = 0, + ACPI_HEST_SOURCE_IA32_CORRECTED_CHECK = 1, + ACPI_HEST_SOURCE_IA32_NMI = 2, + ACPI_HEST_SOURCE_AER_ROOT_PORT = 6, + ACPI_HEST_SOURCE_AER_ENDPOINT = 7, + ACPI_HEST_SOURCE_AER_BRIDGE = 8, + ACPI_HEST_SOURCE_GENERIC_ERROR = 9, + ACPI_HEST_SOURCE_GENERIC_ERROR_V2 = 10, + ACPI_HEST_SOURCE_RESERVED = 11 /* 11 and greater are reserved */ +}; + +/* Block status bitmasks from ACPI 6.1, "18.3.2.7.1 Generic Error Data" */ +#define ACPI_GEBS_UNCORRECTABLE (1) +#define ACPI_GEBS_CORRECTABLE (1 << 1) +#define ACPI_GEBS_MULTIPLE_UNCORRECTABLE (1 << 2) +#define ACPI_GEBS_MULTIPLE_CORRECTABLE (1 << 3) +/* 10 bits, error data entry count */ +#define ACPI_GEBS_ERROR_ENTRY_COUNT (0x3FF << 4) + +/* Generic Hardware Error Source Structure, refer to ACPI 6.1 + * "18.3.2.7 Generic Hardware Error Source". in this struct the + * "type" field has to be ACPI_HEST_SOURCE_GENERIC_ERROR + */ + +struct AcpiGenericHardwareErrorSource { + uint16_t type; + uint16_t source_id; + uint16_t related_source_id; + uint8_t flags; + uint8_t enabled; + uint32_t number_of_records; + uint32_t max_sections_per_record; + uint32_t max_raw_data_length; + struct AcpiGenericAddress error_status_address; + struct AcpiHestNotify notify; + uint32_t error_status_block_length; +} QEMU_PACKED; +typedef struct AcpiGenericHardwareErrorSource AcpiGenericHardwareErrorSource; + +/* Generic Hardware Error Source, version 2, ACPI 6.1, "18.3.2.8 Generic + * Hardware Error Source version 2", in this struct the "type" field has to + * be ACPI_HEST_SOURCE_GENERIC_ERROR_V2 + */ +struct AcpiGenericHardwareErrorSourceV2 { + uint16_t type; + uint16_t source_id; + uint16_t related_source_id; + uint8_t flags; + uint8_t enabled; + uint32_t number_of_records; + uint32_t max_sections_per_record; + uint32_t max_raw_data_length; + struct AcpiGenericAddress error_status_address; + struct AcpiHestNotify notify; + uint32_t error_status_block_length; + struct AcpiGenericAddress read_ack_register; + uint64_t read_ack_preserve; + uint64_t read_ack_write; +} QEMU_PACKED; +typedef struct AcpiGenericHardwareErrorSourceV2 + AcpiGenericHardwareErrorSourceV2; + +/* Generic Error Status block, from ACPI 6.1, + * "18.3.2.7.1 Generic Error Data" + */ +struct AcpiGenericErrorStatus { + /* It is a bitmask composed of ACPI_GEBS_xxx macros */ + uint32_t block_status; + uint32_t raw_data_offset; + uint32_t raw_data_length; + uint32_t data_length; + uint32_t error_severity; +} QEMU_PACKED; +typedef struct AcpiGenericErrorStatus AcpiGenericErrorStatus; + +enum AcpiGenericErrorSeverity { + ACPI_CPER_SEV_RECOVERABLE, + ACPI_CPER_SEV_FATAL, + ACPI_CPER_SEV_CORRECTED, + ACPI_CPER_SEV_NONE, +}; + +/* Generic Error Data entry, revision number is 0x0300, + * ACPI 6.1, "18.3.2.7.1 Generic Error Data" + */ +struct AcpiGenericErrorData { + uint8_t section_type_le[16]; + /* The "error_severity" fields that they take their + * values from AcpiGenericErrorSeverity + */ + uint32_t error_severity; + uint16_t revision; + uint8_t validation_bits; + uint8_t flags; + uint32_t error_data_length; + uint8_t fru_id[16]; + uint8_t fru_text[20]; + uint64_t time_stamp; +} QEMU_PACKED; +typedef struct AcpiGenericErrorData AcpiGenericErrorData; + +/* From UEFI 2.6, "N.2.5 Memory Error Section" */ +struct UefiCperSecMemErr { + uint64_t validation_bits; + uint64_t error_status; + uint64_t physical_addr; + uint64_t physical_addr_mask; + uint16_t node; + uint16_t card; + uint16_t module; + uint16_t bank; + uint16_t device; + uint16_t row; + uint16_t column; + uint16_t bit_pos; + uint64_t requestor_id; + uint64_t responder_id; + uint64_t target_id; + uint8_t error_type; + uint8_t reserved; + uint16_t rank; + uint16_t mem_array_handle; /* card handle in UEFI 2.4 */ + uint16_t mem_dev_handle; /* module handle in UEFI 2.4 */ +} QEMU_PACKED; +typedef struct UefiCperSecMemErr UefiCperSecMemErr; + +/* + * HEST Description Table + */ +struct AcpiHardwareErrorSourceTable { + ACPI_TABLE_HEADER_DEF /* ACPI common table header */ + uint32_t error_source_count; +} QEMU_PACKED; +typedef struct AcpiHardwareErrorSourceTable AcpiHardwareErrorSourceTable; + #define ACPI_SRAT_PROCESSOR_APIC 0 #define ACPI_SRAT_MEMORY 1 #define ACPI_SRAT_PROCESSOR_x2APIC 2 -- 1.8.3.1 From MAILER-DAEMON Fri Aug 04 00:18:38 2017 Received: from list by lists.gnu.org with archive (Exim 4.71) id 1ddU4M-0006zd-HP for mharc-qemu-arm@gnu.org; Fri, 04 Aug 2017 00:18:38 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:51781) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ddU4I-0006pY-25 for qemu-arm@nongnu.org; Fri, 04 Aug 2017 00:18:36 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ddU4G-0006KL-Ae for qemu-arm@nongnu.org; Fri, 04 Aug 2017 00:18:34 -0400 Received: from szxga02-in.huawei.com ([45.249.212.188]:4410) by eggs.gnu.org with esmtps (TLS1.0:RSA_ARCFOUR_SHA1:16) (Exim 4.71) (envelope-from ) id 1ddU4A-0006BP-L5; Fri, 04 Aug 2017 00:18:27 -0400 Received: from 172.30.72.56 (EHLO DGGEML403-HUB.china.huawei.com) ([172.30.72.56]) by dggrg02-dlp.huawei.com (MOS 4.4.6-GA FastPath queued) with ESMTP id ASU19234; Fri, 04 Aug 2017 12:18:19 +0800 (CST) Received: from linux.huawei.com (10.67.187.203) by DGGEML403-HUB.china.huawei.com (10.3.17.33) with Microsoft SMTP Server id 14.3.301.0; Fri, 4 Aug 2017 12:18:09 +0800 From: Dongjiu Geng To: , , , , , , CC: , , Date: Fri, 4 Aug 2017 12:37:52 +0800 Message-ID: <1501821475-14647-1-git-send-email-gengdongjiu@huawei.com> X-Mailer: git-send-email 1.7.7 MIME-Version: 1.0 Content-Type: text/plain X-Originating-IP: [10.67.187.203] X-CFilter-Loop: Reflected X-Mirapoint-Virus-RAPID-Raw: score=unknown(0), refid=str=0001.0A020204.5983F58C.00D2, ss=1, re=0.000, recu=0.000, reip=0.000, cl=1, cld=1, fgs=0, ip=0.0.0.0, so=2014-11-16 11:51:01, dmn=2013-03-21 17:37:32 X-Mirapoint-Loop-Id: b5ffa5335f3f6438d4f20cfbbbc260bc X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.4.x-2.6.x [generic] [fuzzy] X-Received-From: 45.249.212.188 Subject: [Qemu-arm] [PATCH v6 0/3] Generate APEI GHES table and dynamically record CPER X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 04 Aug 2017 04:18:36 -0000 In the armv8 platform, the mainly hardware error source are ARMv8 SEA/SEI/GSIV. For the ARMv8 SEA/SEI, the KVM or host kernel will signal SIGBUS or use other interface to notify user space, such as Qemu. After Qemu gets the notification, it will record the CPER and inject the SEA/SEI to KVM. this series of patches will generate APEI table when guest OS boot up, and dynamically record CPER for the guest OS about the generic hardware errors, currently the userspace only handle the memory section hardware errors. Before Qemu record the CPER, it needs to check the ACK value written by the guest OS to avoid read-write race condition. Below is the APEI/GHESV2/CPER table layout, the max number of error soure is 11, which is classified by notification type, now only enable the SEA/SEI notification type error source. etc/acpi/tables etc/hardware_errors ==================== ========================================== +------------------+ +----------------------------+ | address | +--------------+ | HEST + | registers | | Error Status | + +--------------------------+ | +----------------+ | Data Block 0 | | | GHES0 | +--------->| |status_address0 |------------->| +------------+ +--------------------------+ | | +----------------+ | | CPER | | | ................. | | +------->| |status_address1 |----------+ | | CPER | | | error_status_address | | | | +----------------+ | | | .... | | | ................. | | | | ............. | | | | CPER | | | error_status_address-----+-+ | +------------------+ | | +-+------------+ | | ................. | | +----->| |status_address10|--------+ | | Error Status | | | read_ack_register--------+-+ | | | +----------------+ | | | Data Block 1 | | | read_ack_preserve | +-+-+----->| |ack_address0 |--+ | +-->| +------------+ | | read_ack_write | | | | +----------------+ | | | | CPER | + +--------------------------+ | | +--->| |ack_address1 |--+-+ | | | CPER | | | GHES1 | | | | | +----------------+ | | | | | .... | + +--------------------------+ | | | | | ............. | | | | | | CPER | | | ................. | | | | | +----------------+ | | | +-+------------+ | | error_status_address-----+---+ | | +->| |ack_address10 |--+-+-+ | | |.......... | | | ................. | | | | | +----------------+ | | | | | +------------+ | | read_ack_register--------+-----+-+ | | | ack0 |<-+ | | | | Error Status | | | read_ack_preserve | | | | +----------------+ | | | | Data Block 10| | | read_ack_write | | | | | ack1 |<---+ | +---->| +------------+ + +--------------------------+ | | | +----------------+ | | | CPER | | | ............... | | | | | .... | | | | CPER | + +--------------------------+ | | | +--------------+ | | | | .... | | | GHES10 | | | | | ack10 |<---- + | | CPER | + +--------------------------+ | | | +----------------+ +-+------------+ | | ................. | | | | | error_status_address-----+-----+ | | | ................. | | | | read_ack_register--------+---------+ | | read_ack_preserve | | | read_ack_write | + +--------------------------+ After injecting a SEA/SEI ghes error, the gueset OS kernel log will be shown as below: [ 142.911115] {1}[Hardware Error]: Hardware error from APEI Generic Hardware Error Source: 8 [ 142.913141] {1}[Hardware Error]: event severity: recoverable [ 142.914498] {1}[Hardware Error]: Error 0, type: recoverable [ 142.915851] {1}[Hardware Error]: section_type: memory error [ 142.917163] {1}[Hardware Error]: physical_address: 0x0000000000001111 [ 142.918792] {1}[Hardware Error]: error_type: 3, multi-bit ECC how to test: 1. In the guest OS, use this command to dump the APEI table: "iasl -p ./HEST -d /sys/firmware/acpi/tables/HEST" 2. And find the address for the generic error status block according to the notification type 3. then find the CPER record through the generic error status block. For example(notification type is SEA): (1) root@genericarmv8:~# iasl -p ./HEST -d /sys/firmware/acpi/tables/HEST (2) root@genericarmv8:~# cat HEST.dsl /* * Intel ACPI Component Architecture * AML/ASL+ Disassembler version 20170728 (64-bit version) * Copyright (c) 2000 - 2017 Intel Corporation * * Disassembly of /sys/firmware/acpi/tables/HEST, Mon Sep 5 07:59:17 2016 * * ACPI Data Table [HEST] * * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue */ .................................................................................. [308h 0776 2] Subtable Type : 000A [Generic Hardware Error Source V2] [30Ah 0778 2] Source Id : 0008 [30Ch 0780 2] Related Source Id : FFFF [30Eh 0782 1] Reserved : 00 [30Fh 0783 1] Enabled : 01 [310h 0784 4] Records To Preallocate : 00000001 [314h 0788 4] Max Sections Per Record : 00000001 [318h 0792 4] Max Raw Data Length : 00001000 [31Ch 0796 12] Error Status Address : [Generic Address Structure] [31Ch 0796 1] Space ID : 00 [SystemMemory] [31Dh 0797 1] Bit Width : 40 [31Eh 0798 1] Bit Offset : 00 [31Fh 0799 1] Encoded Access Width : 04 [QWord Access:64] [320h 0800 8] Address : 00000000785D0040 [328h 0808 28] Notify : [Hardware Error Notification Structure] [328h 0808 1] Notify Type : 08 [SEA] [329h 0809 1] Notify Length : 1C [32Ah 0810 2] Configuration Write Enable : 0000 [32Ch 0812 4] PollInterval : 00000000 [330h 0816 4] Vector : 00000000 [334h 0820 4] Polling Threshold Value : 00000000 [338h 0824 4] Polling Threshold Window : 00000000 [33Ch 0828 4] Error Threshold Value : 00000000 [340h 0832 4] Error Threshold Window : 00000000 [344h 0836 4] Error Status Block Length : 00001000 [348h 0840 12] Read Ack Register : [Generic Address Structure] [348h 0840 1] Space ID : 00 [SystemMemory] [349h 0841 1] Bit Width : 40 [34Ah 0842 1] Bit Offset : 00 [34Bh 0843 1] Encoded Access Width : 04 [QWord Access:64] [34Ch 0844 8] Address : 00000000785D0098 [354h 0852 8] Read Ack Preserve : 00000000FFFFFFFE [35Ch 0860 8] Read Ack Write : 0000000000000001 [364h 0868 2] Subtable Type : 000A [Generic Hardware Error Source V2] [366h 0870 2] Source Id : 0009 [368h 0872 2] Related Source Id : FFFF [36Ah 0874 1] Reserved : 00 [36Bh 0875 1] Enabled : 01 [36Ch 0876 4] Records To Preallocate : 00000001 [370h 0880 4] Max Sections Per Record : 00000001 [374h 0884 4] Max Raw Data Length : 00001000 [378h 0888 12] Error Status Address : [Generic Address Structure] [378h 0888 1] Space ID : 00 [SystemMemory] [379h 0889 1] Bit Width : 40 [37Ah 0890 1] Bit Offset : 00 [37Bh 0891 1] Encoded Access Width : 04 [QWord Access:64] [37Ch 0892 8] Address : 00000000785D0048 [384h 0900 28] Notify : [Hardware Error Notification Structure] [384h 0900 1] Notify Type : 09 [SEI] [385h 0901 1] Notify Length : 1C [386h 0902 2] Configuration Write Enable : 0000 [388h 0904 4] PollInterval : 00000000 [38Ch 0908 4] Vector : 00000000 [390h 0912 4] Polling Threshold Value : 00000000 [394h 0916 4] Polling Threshold Window : 00000000 [398h 0920 4] Error Threshold Value : 00000000 [39Ch 0924 4] Error Threshold Window : 00000000 [3A0h 0928 4] Error Status Block Length : 00001000 [3A4h 0932 12] Read Ack Register : [Generic Address Structure] [3A4h 0932 1] Space ID : 00 [SystemMemory] [3A5h 0933 1] Bit Width : 40 [3A6h 0934 1] Bit Offset : 00 [3A7h 0935 1] Encoded Access Width : 04 [QWord Access:64] [3A8h 0936 8] Address : 00000000785D00A0 [3B0h 0944 8] Read Ack Preserve : 00000000FFFFFFFE [3B8h 0952 8] Read Ack Write : 000000000000000 ..................................................................................... (3) according to above table, the address that contains the physical address of a block of memory that holds the error status data for SEA notification error source is 0x00000000785D0040 (4) the address for SEA notification error source is 0x785d8108 (qemu) xp /1 0x00000000785D0040 00000000785d0040: 0x785d8108 (5) check the content of generic error status block and generic error data entry (qemu) xp /100x 0x785d8108 00000000785d8108: 0x00000000 0x00000000 0x00000000 0x00000098 00000000785d8118: 0x00000000 0xa5bc1114 0x4ede6f64 0x833e63b8 00000000785d8128: 0xb1837ced 0x00000000 0x00000300 0x00000050 00000000785d8138: 0x00000000 0x00000000 0x00000000 0x00000000 00000000785d8148: 0x00000000 0x00000000 0x00000000 0x00000000 00000000785d8158: 0x00000000 0x00000000 0x00000000 0x00004002 00000000785d8168: 0x00000000 0x00000000 0x00000000 0x00001111 00000000785d8178: 0x00000000 0x00000000 0x00000000 0x00000000 00000000785d8188: 0x00000000 0x00000000 0x00000000 0x00000000 00000000785d8198: 0x00000000 0x00000000 0x00000000 0x00000000 00000000785d81a8: 0x00000000 0x00000003 0x00000000 0x00000000 00000000785d81b8: 0x00000000 0x00000000 0x00000000 0x00000000 00000000785d81c8: 0x00000000 0x00000000 0x00000000 0x00000000 00000000785d81d8: 0x00000000 0x00000000 0x00000000 0x00000000 00000000785d81e8: 0x00000000 0x00000000 0x00000000 0x00000000 00000000785d81f8: 0x00000000 0x00000000 0x00000000 0x00000000 00000000785d8208: 0x00000000 0x00000000 0x00000000 0x00000000 00000000785d8218: 0x00000000 0x00000000 0x00000000 0x00000000 00000000785d8228: 0x00000000 0x00000000 0x00000000 0x00000000 00000000785d8238: 0x00000000 0x00000000 0x00000000 0x00000000 00000000785d8248: 0x00000000 0x00000000 0x00000000 0x00000000 00000000785d8258: 0x00000000 0x00000000 0x00000000 0x00000000 00000000785d8268: 0x00000000 0x00000000 0x00000000 0x00000000 00000000785d8278: 0x00000000 0x00000000 0x00000000 0x00000000 00000000785d8288: 0x00000000 0x00000000 0x00000000 0x00000000 (6) check the OSPM's ACK value(for example SEA) /* The address of ACK value */ (qemu) xp /1 0x00000000785D0098 00000000785d0098: 0x785d00f0 /* Before OSPM acknowledges the error */ (qemu) xp /1 0x785d00f0 00000000785d00f0: 0x00000000 /* After OSPM acknowledges the error */ (qemu) xp /1 0x785d00f0 00000000785d00f0: 0x00000001 Dongjiu Geng (3): ACPI: add APEI/HEST/CPER structures and macros ACPI: Add APEI GHES Table Generation support ACPI: build and enable APEI GHES in the Makefile and configuration default-configs/arm-softmmu.mak | 1 + hw/acpi/Makefile.objs | 1 + hw/acpi/aml-build.c | 2 + hw/acpi/hest_ghes.c | 370 ++++++++++++++++++++++++++++++++++++++++ hw/arm/virt-acpi-build.c | 6 + include/hw/acpi/acpi-defs.h | 193 +++++++++++++++++++++ include/hw/acpi/aml-build.h | 1 + include/hw/acpi/hest_ghes.h | 47 +++++ 8 files changed, 621 insertions(+) create mode 100644 hw/acpi/hest_ghes.c create mode 100644 include/hw/acpi/hest_ghes.h -- 1.8.3.1 From MAILER-DAEMON Fri Aug 04 00:18:43 2017 Received: from list by lists.gnu.org with archive (Exim 4.71) id 1ddU4R-00077W-PL for mharc-qemu-arm@gnu.org; Fri, 04 Aug 2017 00:18:43 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:51810) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ddU4L-0006wl-CU for qemu-arm@nongnu.org; Fri, 04 Aug 2017 00:18:40 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ddU4I-0006MU-A9 for qemu-arm@nongnu.org; Fri, 04 Aug 2017 00:18:37 -0400 Received: from szxga02-in.huawei.com ([45.249.212.188]:4411) by eggs.gnu.org with esmtps (TLS1.0:RSA_ARCFOUR_SHA1:16) (Exim 4.71) (envelope-from ) id 1ddU4A-0006BO-SB; Fri, 04 Aug 2017 00:18:28 -0400 Received: from 172.30.72.56 (EHLO DGGEML403-HUB.china.huawei.com) ([172.30.72.56]) by dggrg02-dlp.huawei.com (MOS 4.4.6-GA FastPath queued) with ESMTP id ASU19227; Fri, 04 Aug 2017 12:18:19 +0800 (CST) Received: from linux.huawei.com (10.67.187.203) by DGGEML403-HUB.china.huawei.com (10.3.17.33) with Microsoft SMTP Server id 14.3.301.0; Fri, 4 Aug 2017 12:18:09 +0800 From: Dongjiu Geng To: , , , , , , CC: , , Date: Fri, 4 Aug 2017 12:37:54 +0800 Message-ID: <1501821475-14647-3-git-send-email-gengdongjiu@huawei.com> X-Mailer: git-send-email 1.7.7 In-Reply-To: <1501821475-14647-1-git-send-email-gengdongjiu@huawei.com> References: <1501821475-14647-1-git-send-email-gengdongjiu@huawei.com> MIME-Version: 1.0 Content-Type: text/plain X-Originating-IP: [10.67.187.203] X-CFilter-Loop: Reflected X-Mirapoint-Virus-RAPID-Raw: score=unknown(0), refid=str=0001.0A020206.5983F58C.0148, ss=1, re=0.000, recu=0.000, reip=0.000, cl=1, cld=1, fgs=0, ip=0.0.0.0, so=2014-11-16 11:51:01, dmn=2013-03-21 17:37:32 X-Mirapoint-Loop-Id: c3c343456386e0c081d3558bb7e2f307 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.4.x-2.6.x [generic] [fuzzy] X-Received-From: 45.249.212.188 Subject: [Qemu-arm] [PATCH v6 2/3] ACPI: Add APEI GHES Table Generation support X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 04 Aug 2017 04:18:40 -0000 This implements APEI GHES Table by passing the error CPER info to the guest via a fw_cfg_blob. After a CPER info is recorded, an SEA(Synchronous External Abort)/SEI(SError Interrupt) exception will be injected into the guest OS. Below is the table layout, the max number of error soure is 11, which is classified by notification type. etc/acpi/tables etc/hardware_errors ==================== ========================================== +------------------+ +----------------------------+ | address | +--------------+ | HEST + | registers | | Error Status | + +--------------------------+ | +----------------+ | Data Block 0 | | | GHES0 | +--------->| |status_address0 |------------->| +------------+ +--------------------------+ | | +----------------+ | | CPER | | | ................. | | +------->| |status_address1 |----------+ | | CPER | | | error_status_address | | | | +----------------+ | | | .... | | | ................. | | | | ............. | | | | CPER | | | error_status_address-----+-+ | +------------------+ | | +-+------------+ | | ................. | | +----->| |status_address10|--------+ | | Error Status | | | read_ack_register--------+-+ | | | +----------------+ | | | Data Block 1 | | | read_ack_preserve | +-+-+----->| |ack_address0 |--+ | +-->| +------------+ | | read_ack_write | | | | +----------------+ | | | | CPER | + +--------------------------+ | | +--->| |ack_address1 |--+-+ | | | CPER | | | GHES1 | | | | | +----------------+ | | | | | .... | + +--------------------------+ | | | | | ............. | | | | | | CPER | | | ................. | | | | | +----------------+ | | | +-+------------+ | | error_status_address-----+---+ | | +->| |ack_address10 |--+-+-+ | | |.......... | | | ................. | | | | | +----------------+ | | | | | +------------+ | | read_ack_register--------+-----+-+ | | | ack0 |<-+ | | | | Error Status | | | read_ack_preserve | | | | +----------------+ | | | | Data Block 10| | | read_ack_write | | | | | ack1 |<---+ | +---->| +------------+ + +--------------------------+ | | | +----------------+ | | | CPER | | | ............... | | | | | .... | | | | CPER | + +--------------------------+ | | | +--------------+ | | | | .... | | | GHES10 | | | | | ack10 |<---- + | | CPER | + +--------------------------+ | | | +----------------+ +-+------------+ | | ................. | | | | | error_status_address-----+-----+ | | | ................. | | | | read_ack_register--------+---------+ | | read_ack_preserve | | | read_ack_write | + +--------------------------+ For GHESv2 error source, the OSPM must acknowledges the error via Read Ack register. so user space must check the ack value to avoid read-write race condition. Signed-off-by: Dongjiu Geng --- thanks a lot Michael and Laszlo's review and comments: change since v5: (1) move to GHESv2 error source from GHESv1, because we maily use the GHESv2 (2) add the GHESv2 error source layout in the comments (2) add the logic to read the ack value from OSPM to avoid read-write race condition (3) including header files "aml-build.h" and "hest_ghes.h" in this patch to make it reasonable (4) calculate the fw_cfg blob offsets that should be patched in more fine-grained steps, with multiple separate increments, using: - structure type names, - sizeof operators, - offsetof macros, - and possibly a separate comment for each offset increment. (5) remove page boundary refers to 4096 in the "bios_linker_loader_alloc" (6) using build_append_int_noprefix to avoid use pointer math, so that the code is easily readable (7) change memory section definition to array from QemuUUID (8) only enable SEA/SEI notification hardware error source to avoid guest OS ACPI driver probe warning change since v4: 1. fix email threading in this series is incorrect issue change since v3: 1. remove the unnecessary include for "hw/acpi/vmgenid.h" in hw/arm/virt-acpi-build.c 2. add conversion between LE and host-endian for the CPER record 3. handle the case that run out of the preallocated memory for the CPER record 4. change to use g_malloc0 instead of g_malloc 5. change block_reqr_size name to block_rer_size 6. change QEMU coding style, that is, the operator is at the end of the line. 7. drop the ERROR_STATUS_ADDRESS_OFFSET and GAS_ADDRESS_OFFSET macros (from the header file as well), and use the offsetof to replace it. 8. remove the init_aml_allocator() / free_aml_allocator(), calculate the needed size, and push that many bytes directly to "table_data". 9. take an "OVMF header probe suppressor" into account 10.corrct HEST and CPER value assigment, for example, correct the source_id for every error source, this identifier of source_id should be unique among all error sources; 11. create only one WRITE_POINTER command, for the base address of "etc/hardware_errors". This should be done outside of the loop.The base addresses of the individual error status data blocks should be calculated in ghes_update_guest(), based on the error source / notification type 12.correct the commit message lists error sources / notification types 0 through 10 (count=11 in total). 13.correct the size calculation for GHES_DATA_ADDR_FW_CFG_FILE 14.range-checked the value of "notify" before using it as an array subscript --- hw/acpi/aml-build.c | 2 + hw/acpi/hest_ghes.c | 368 ++++++++++++++++++++++++++++++++++++++++++++ hw/arm/virt-acpi-build.c | 6 + include/hw/acpi/aml-build.h | 1 + include/hw/acpi/hest_ghes.h | 47 ++++++ 5 files changed, 424 insertions(+) create mode 100644 hw/acpi/hest_ghes.c create mode 100644 include/hw/acpi/hest_ghes.h diff --git a/hw/acpi/aml-build.c b/hw/acpi/aml-build.c index c6f2032..802b98d 100644 --- a/hw/acpi/aml-build.c +++ b/hw/acpi/aml-build.c @@ -1560,6 +1560,7 @@ void acpi_build_tables_init(AcpiBuildTables *tables) tables->table_data = g_array_new(false, true /* clear */, 1); tables->tcpalog = g_array_new(false, true /* clear */, 1); tables->vmgenid = g_array_new(false, true /* clear */, 1); + tables->hardware_errors = g_array_new(false, true /* clear */, 1); tables->linker = bios_linker_loader_init(); } @@ -1570,6 +1571,7 @@ void acpi_build_tables_cleanup(AcpiBuildTables *tables, bool mfre) g_array_free(tables->table_data, true); g_array_free(tables->tcpalog, mfre); g_array_free(tables->vmgenid, mfre); + g_array_free(tables->hardware_errors, mfre); } /* Build rsdt table */ diff --git a/hw/acpi/hest_ghes.c b/hw/acpi/hest_ghes.c new file mode 100644 index 0000000..cc06662 --- /dev/null +++ b/hw/acpi/hest_ghes.c @@ -0,0 +1,368 @@ +/* + * APEI GHES table Generation + * + * Copyright (C) 2017 huawei. + * + * Author: Dongjiu Geng + * + * This work is licensed under the terms of the GNU GPL, version 2 or later. + * See the COPYING file in the top-level directory. + * + */ + +#include "qemu/osdep.h" +#include "qmp-commands.h" +#include "hw/acpi/acpi.h" +#include "hw/acpi/aml-build.h" +#include "hw/acpi/hest_ghes.h" +#include "hw/nvram/fw_cfg.h" +#include "sysemu/sysemu.h" +#include "qemu/error-report.h" + +/* The structure that stands for the layout + * GHES_ERRORS_FW_CFG_FILE fw_cfg blob + * + * etc/hardware_errors + * ========================================== + * +------------------+ + * | address | +--------------+ + * | registers | | Error Status | + * | +----------------+ | Data Block 0 | + * | |status_address0 |------------->| +------------+ + * | +----------------+ | | CPER | + * | |status_address1 |----------+ | | CPER | + * | +----------------+ | | | .... | + * | |............. | | | | CPER | + * | +----------------+ | | +------------+ + * | |status_address10|--------+ | | Error Status | + * | +----------------+ | | | Data Block 1 | + * | |ack_address0 |--+ | +-->| +------------+ + * | +----------------+ | | | | CPER | + * | |ack_address1 |--+-+ | | | CPER | + * | +----------------+ | | | | | .... | + * | | ............. | | | | | | CPER | + * | +----------------+ | | | +-+------------+ + * | |ack_address10 |--+-+-+ | | |.......... | + * | +----------------+ | | | | | +------------+ + * | | ack0 |<-+ | | | | Error Status | + * | +----------------+ | | | | Data Block10 | + * | | ack1 |<---+ | +---->| +------------+ + * | +----------------+ | | | CPER | + * | | .... | | | | CPER | + * | +--------------+ | | | | .... | + * | | ack10 |<---- + | | CPER | + * | +----------------+ +-+------------+ + */ +struct hardware_errors_buffer { + /* Generic Error Status Block register */ + uint64_t gesb_register[GHES_ACPI_HEST_NOTIFY_RESERVED]; + uint64_t ack_register[GHES_ACPI_HEST_NOTIFY_RESERVED]; + uint64_t ack[GHES_ACPI_HEST_NOTIFY_RESERVED]; + char gesb[GHES_MAX_RAW_DATA_LENGTH][GHES_ACPI_HEST_NOTIFY_RESERVED]; +}; + +static int ghes_record_cper(uint64_t error_block_address, + uint64_t error_physical_addr) +{ + AcpiGenericErrorStatus block; + AcpiGenericErrorData *gdata; + UefiCperSecMemErr *mem_err; + uint64_t current_block_length; + unsigned char *buffer; + /* memory section */ + char mem_section_id_le[] = {0x14, 0x11, 0xBC, 0xA5, 0x64, 0x6F, 0xDE, + 0x4E, 0xB8, 0x63, 0x3E, 0x83, 0xED, 0x7C, + 0x83, 0xB1}; + + cpu_physical_memory_read(error_block_address, &block, + sizeof(AcpiGenericErrorStatus)); + + /* Get the current generic error status block length */ + current_block_length = sizeof(AcpiGenericErrorStatus) + + le32_to_cpu(block.data_length); + + /* If the Generic Error Status Block is NULL, update + * the block header + */ + if (!block.block_status) { + block.block_status = ACPI_GEBS_UNCORRECTABLE; + block.error_severity = ACPI_CPER_SEV_RECOVERABLE; + } + + block.data_length += cpu_to_le32(sizeof(AcpiGenericErrorData)); + block.data_length += cpu_to_le32(sizeof(UefiCperSecMemErr)); + + /* check whether it runs out of the preallocated memory */ + if ((le32_to_cpu(block.data_length) + sizeof(AcpiGenericErrorStatus)) > + GHES_MAX_RAW_DATA_LENGTH) { + error_report("Record CPER out of boundary!!!"); + return GHES_CPER_FAIL; + } + + /* Write back the Generic Error Status Block to guest memory */ + cpu_physical_memory_write(error_block_address, &block, + sizeof(AcpiGenericErrorStatus)); + + /* Fill in Generic Error Data Entry */ + buffer = g_malloc0(sizeof(AcpiGenericErrorData) + + sizeof(UefiCperSecMemErr)); + + + memset(buffer, 0, sizeof(AcpiGenericErrorData) + sizeof(UefiCperSecMemErr)); + gdata = (AcpiGenericErrorData *)buffer; + + /* Memory section */ + memcpy(&(gdata->section_type_le), &mem_section_id_le, + sizeof(mem_section_id_le)); + + /* error severity is recoverable */ + gdata->error_severity = ACPI_CPER_SEV_RECOVERABLE; + gdata->revision = 0x300; /* the revision number is 0x300 */ + gdata->error_data_length = cpu_to_le32(sizeof(UefiCperSecMemErr)); + + mem_err = (UefiCperSecMemErr *) (gdata + 1); + + /* User space only handle the memory section CPER */ + + /* Hard code to Multi-bit ECC error */ + mem_err->validation_bits |= cpu_to_le32(UEFI_CPER_MEM_VALID_ERROR_TYPE); + mem_err->error_type = cpu_to_le32(UEFI_CPER_MEM_ERROR_TYPE_MULTI_ECC); + + /* Record the physical address at which the memory error occurred */ + mem_err->validation_bits |= cpu_to_le32(UEFI_CPER_MEM_VALID_PA); + mem_err->physical_addr = cpu_to_le32(error_physical_addr); + + /* Write back the Generic Error Data Entry to guest memory */ + cpu_physical_memory_write(error_block_address + current_block_length, + buffer, sizeof(AcpiGenericErrorData) + sizeof(UefiCperSecMemErr)); + + g_free(buffer); + return GHES_CPER_OK; +} + +static void +build_address(GArray *table_data, BIOSLinker *linker, + uint32_t dst_patched_offset, uint32_t src_offset, + uint8_t address_space_id , uint8_t register_bit_width, + uint8_t register_bit_offset, uint8_t access_size) +{ + uint32_t address_size = sizeof(struct AcpiGenericAddress) - + offsetof(struct AcpiGenericAddress, address); + + /* Address space */ + build_append_int_noprefix(table_data, address_space_id, 1); + /* register bit width */ + build_append_int_noprefix(table_data, register_bit_width, 1); + /* register bit offset */ + build_append_int_noprefix(table_data, register_bit_offset, 1); + /* access size */ + build_append_int_noprefix(table_data, access_size, 1); + acpi_data_push(table_data, address_size); + + /* Patch address of ERRORS fw_cfg blob into the TABLE fw_cfg blob so OSPM + * can retrieve and read it. the address size is 64 bits. + */ + bios_linker_loader_add_pointer(linker, + ACPI_BUILD_TABLE_FILE, dst_patched_offset, sizeof(uint64_t), + GHES_ERRORS_FW_CFG_FILE, src_offset); +} + +void ghes_build_acpi(GArray *table_data, GArray *hardware_error, + BIOSLinker *linker) +{ + uint32_t ghes_start = table_data->len; + uint32_t address_size, ack_value_size, error_status_address_offset; + uint32_t read_ack_register_offset, i; + /* + * The block_req_size stands for two address and one + * generic error status block + * +---------+ + * | address |-----------> +---------+ + * +---------+ | CPER | + * | ack | | CPER | + * | address |----+ | CPER | + * +---------+ | | CPER | + * | ack0 |<---+ | .... | + * +---------+ +---------+ + */ + address_size = sizeof(struct AcpiGenericAddress) - + offsetof(struct AcpiGenericAddress, address); + ack_value_size = (offsetof(struct hardware_errors_buffer, gesb) - + offsetof(struct hardware_errors_buffer, ack)) / + GHES_ACPI_HEST_NOTIFY_RESERVED; + + error_status_address_offset = ghes_start + + sizeof(AcpiHardwareErrorSourceTable) + + offsetof(AcpiGenericHardwareErrorSourceV2, error_status_address) + + offsetof(struct AcpiGenericAddress, address); + + read_ack_register_offset = ghes_start + + sizeof(AcpiHardwareErrorSourceTable) + + offsetof(AcpiGenericHardwareErrorSourceV2, read_ack_register) + + offsetof(struct AcpiGenericAddress, address); + + acpi_data_push(hardware_error, + offsetof(struct hardware_errors_buffer, ack)); + for (i = 0; i < GHES_ACPI_HEST_NOTIFY_RESERVED; i++) + /* Initialize read ack value */ + build_append_int_noprefix((void *)hardware_error, 1, 8); + + /* Reserved the total size for ERRORS fw_cfg blob + */ + acpi_data_push(hardware_error, sizeof(struct hardware_errors_buffer)); + + /* Allocate guest memory for the Data fw_cfg blob */ + bios_linker_loader_alloc(linker, GHES_ERRORS_FW_CFG_FILE, hardware_error, + 1, false); + /* Reserve table header size */ + acpi_data_push(table_data, sizeof(AcpiTableHeader)); + + build_append_int_noprefix(table_data, GHES_ACPI_HEST_NOTIFY_RESERVED, 4); + + for (i = 0; i < GHES_ACPI_HEST_NOTIFY_RESERVED; i++) { + build_append_int_noprefix(table_data, + ACPI_HEST_SOURCE_GENERIC_ERROR_V2, 2); /* type */ + /* source id */ + build_append_int_noprefix(table_data, cpu_to_le16(i), 2); + /* related source id */ + build_append_int_noprefix(table_data, 0xffff, 2); + build_append_int_noprefix(table_data, 0, 1); /* flags */ + + /* Currently only enable SEA and SEI notification type to avoid the + * kernel warning, reserve the space for other notification error source + */ + if (i == ACPI_HEST_NOTIFY_SEA || i == ACPI_HEST_NOTIFY_SEI) { + build_append_int_noprefix(table_data, 1, 1); /* enabled */ + } else { + build_append_int_noprefix(table_data, 0, 1); /* enabled */ + } + + /* The number of error status block per generic hardware error source */ + build_append_int_noprefix(table_data, 1, 4); + /* Max sections per record */ + build_append_int_noprefix(table_data, 1, 4); + /* Max raw data length */ + build_append_int_noprefix(table_data, GHES_MAX_RAW_DATA_LENGTH, 4); + + /* Build error Status Address*/ + build_address(table_data, linker, error_status_address_offset + i * + sizeof(AcpiGenericHardwareErrorSourceV2), i * address_size, + AML_SYSTEM_MEMORY, 0x40, 0, 4 /* QWord access */); + + /* Hardware error notification structure */ + build_append_int_noprefix(table_data, i, 1); /* type */ + /* length */ + build_append_int_noprefix(table_data, sizeof(AcpiHestNotify), 1); + build_append_int_noprefix(table_data, 0, 26); + + /* Error Status Block Length */ + build_append_int_noprefix(table_data, + cpu_to_le32(GHES_MAX_RAW_DATA_LENGTH), 4); + + /* Build read ack register */ + build_address(table_data, linker, read_ack_register_offset + i * + sizeof(AcpiGenericHardwareErrorSourceV2), + offsetof(struct hardware_errors_buffer, ack_register) + + i * address_size, AML_SYSTEM_MEMORY, 0x40, 0, + 4 /* QWord access */); + + /* Read ack preserve */ + build_append_int_noprefix(table_data, cpu_to_le64(0xfffffffe), 8); + + /* Read ack write */ + build_append_int_noprefix(table_data, cpu_to_le64(0x1), 8); + } + + for (i = 0; i < GHES_ACPI_HEST_NOTIFY_RESERVED; i++) { + /* Patch address of generic error status block into + * the address register so OSPM can retrieve and read it. + */ + bios_linker_loader_add_pointer(linker, + GHES_ERRORS_FW_CFG_FILE, address_size * i, address_size, + GHES_ERRORS_FW_CFG_FILE, + offsetof(struct hardware_errors_buffer, gesb) + + i * GHES_MAX_RAW_DATA_LENGTH); + + /* Patch address of read ack into the read ack register so + * OSPM can retrieve and read it. + */ + bios_linker_loader_add_pointer(linker, + GHES_ERRORS_FW_CFG_FILE, + offsetof(struct hardware_errors_buffer, ack_register) + + address_size * i, address_size, GHES_ERRORS_FW_CFG_FILE, + offsetof(struct hardware_errors_buffer, ack) + i * ack_value_size); + } + + /* Patch address of ERRORS fw_cfg blob into the ADDR fw_cfg blob + * so QEMU can write the ERRORS there. The address is expected to be + * < 4GB, but write 64 bits anyway. + */ + bios_linker_loader_write_pointer(linker, GHES_DATA_ADDR_FW_CFG_FILE, + 0, address_size, GHES_ERRORS_FW_CFG_FILE, + offsetof(struct hardware_errors_buffer, gesb)); + + build_header(linker, table_data, + (void *)(table_data->data + ghes_start), "HEST", + table_data->len - ghes_start, 1, NULL, "GHES"); +} + +static GhesState ges; +void ghes_add_fw_cfg(FWCfgState *s, GArray *hardware_error) +{ + + size_t request_block_size = sizeof(uint64_t) + GHES_MAX_RAW_DATA_LENGTH; + size_t size = GHES_ACPI_HEST_NOTIFY_RESERVED * request_block_size; + + /* Create a read-only fw_cfg file for GHES */ + fw_cfg_add_file(s, GHES_ERRORS_FW_CFG_FILE, hardware_error->data, + size); + /* Create a read-write fw_cfg file for Address */ + fw_cfg_add_file_callback(s, GHES_DATA_ADDR_FW_CFG_FILE, NULL, NULL, + &ges.ghes_addr_le, sizeof(ges.ghes_addr_le), false); +} + +bool ghes_update_guest(uint32_t notify, uint64_t physical_address) +{ + uint64_t error_block_addr; + uint64_t ack_addr, ack_value = 0; + int loop = 0, ack_value_size; + bool ret = GHES_CPER_FAIL; + + ack_value_size = (offsetof(struct hardware_errors_buffer, gesb) - + offsetof(struct hardware_errors_buffer, ack)) / + GHES_ACPI_HEST_NOTIFY_RESERVED; +retry: + if (physical_address && notify < GHES_ACPI_HEST_NOTIFY_RESERVED) { + error_block_addr = ges.ghes_addr_le + notify * GHES_MAX_RAW_DATA_LENGTH; + error_block_addr = le32_to_cpu(error_block_addr); + + ack_addr = ges.ghes_addr_le - + (GHES_ACPI_HEST_NOTIFY_RESERVED - notify) * ack_value_size; + cpu_physical_memory_read(ack_addr, &ack_value, ack_value_size); + if (!ack_value) { + if (loop < 3) { + usleep(100 * 1000); + loop++; + goto retry; + } else { + error_report("Last time OSPM does not acknowledge the error," + " record CPER failed this time, set the ack value to" + " avoid blocking next time CPER record! exit"); + ack_value = 1; + cpu_physical_memory_write(ack_addr, &ack_value, ack_value_size); + return ret; + } + } else { + /* A zero value in ghes_addr means that BIOS has not yet written + * the address + */ + if (error_block_addr) { + ack_value = 0; + cpu_physical_memory_write(ack_addr, &ack_value, ack_value_size); + ret = ghes_record_cper(error_block_addr, physical_address); + } + } + } + + return ret; +} diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c index 0835e59..5c97016 100644 --- a/hw/arm/virt-acpi-build.c +++ b/hw/arm/virt-acpi-build.c @@ -45,6 +45,7 @@ #include "hw/arm/virt.h" #include "sysemu/numa.h" #include "kvm_arm.h" +#include "hw/acpi/hest_ghes.h" #define ARM_SPI_BASE 32 #define ACPI_POWER_BUTTON_DEVICE "PWRB" @@ -778,6 +779,9 @@ void virt_acpi_build(VirtMachineState *vms, AcpiBuildTables *tables) acpi_add_table(table_offsets, tables_blob); build_spcr(tables_blob, tables->linker, vms); + acpi_add_table(table_offsets, tables_blob); + ghes_build_acpi(tables_blob, tables->hardware_errors, tables->linker); + if (nb_numa_nodes > 0) { acpi_add_table(table_offsets, tables_blob); build_srat(tables_blob, tables->linker, vms); @@ -890,6 +894,8 @@ void virt_acpi_setup(VirtMachineState *vms) fw_cfg_add_file(vms->fw_cfg, ACPI_BUILD_TPMLOG_FILE, tables.tcpalog->data, acpi_data_len(tables.tcpalog)); + ghes_add_fw_cfg(vms->fw_cfg, tables.hardware_errors); + build_state->rsdp_mr = acpi_add_rom_blob(build_state, tables.rsdp, ACPI_BUILD_RSDP_FILE, 0); diff --git a/include/hw/acpi/aml-build.h b/include/hw/acpi/aml-build.h index 00c21f1..c1d15b3 100644 --- a/include/hw/acpi/aml-build.h +++ b/include/hw/acpi/aml-build.h @@ -211,6 +211,7 @@ struct AcpiBuildTables { GArray *rsdp; GArray *tcpalog; GArray *vmgenid; + GArray *hardware_errors; BIOSLinker *linker; } AcpiBuildTables; diff --git a/include/hw/acpi/hest_ghes.h b/include/hw/acpi/hest_ghes.h new file mode 100644 index 0000000..0772756 --- /dev/null +++ b/include/hw/acpi/hest_ghes.h @@ -0,0 +1,47 @@ +/* + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Authors: + * Dongjiu Geng + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#ifndef ACPI_GHES_H +#define ACPI_GHES_H + +#include "hw/acpi/bios-linker-loader.h" + +#define GHES_ERRORS_FW_CFG_FILE "etc/hardware_errors" +#define GHES_DATA_ADDR_FW_CFG_FILE "etc/hardware_errors_addr" + +#define GHES_GAS_ADDRESS_OFFSET 4 +#define GHES_ERROR_STATUS_ADDRESS_OFFSET 20 +#define GHES_NOTIFICATION_STRUCTURE 32 + +#define GHES_CPER_OK 1 +#define GHES_CPER_FAIL 0 + +#define GHES_ACPI_HEST_NOTIFY_RESERVED 11 +/* The max size in Bytes for one error block */ +#define GHES_MAX_RAW_DATA_LENGTH 0x1000 + + +typedef struct GhesState { + uint64_t ghes_addr_le; +} GhesState; + +void ghes_build_acpi(GArray *table_data, GArray *hardware_error, + BIOSLinker *linker); +void ghes_add_fw_cfg(FWCfgState *s, GArray *hardware_errors); +bool ghes_update_guest(uint32_t notify, uint64_t error_physical_addr); +#endif -- 1.8.3.1 From MAILER-DAEMON Fri Aug 04 01:22:31 2017 Received: from list by lists.gnu.org with archive (Exim 4.71) id 1ddV4B-0003SC-KQ for mharc-qemu-arm@gnu.org; Fri, 04 Aug 2017 01:22:31 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:56336) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ddV49-0003QN-46 for qemu-arm@nongnu.org; Fri, 04 Aug 2017 01:22:30 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ddV48-00079j-9Y for qemu-arm@nongnu.org; Fri, 04 Aug 2017 01:22:29 -0400 Received: from szxga01-in.huawei.com ([45.249.212.187]:4478) by eggs.gnu.org with esmtps (TLS1.0:RSA_ARCFOUR_SHA1:16) (Exim 4.71) (envelope-from ) id 1ddV43-0006wY-Ot; Fri, 04 Aug 2017 01:22:24 -0400 Received: from 172.30.72.54 (EHLO dggeml405-hub.china.huawei.com) ([172.30.72.54]) by dggrg01-dlp.huawei.com (MOS 4.4.6-GA FastPath queued) with ESMTP id ATU24759; Fri, 04 Aug 2017 13:22:17 +0800 (CST) Received: from linux.huawei.com (10.67.187.203) by dggeml405-hub.china.huawei.com (10.3.17.49) with Microsoft SMTP Server id 14.3.301.0; Fri, 4 Aug 2017 13:22:05 +0800 From: Dongjiu Geng To: , , , , , CC: , Date: Fri, 4 Aug 2017 13:41:51 +0800 Message-ID: <1501825311-4559-4-git-send-email-gengdongjiu@huawei.com> X-Mailer: git-send-email 1.7.7 In-Reply-To: <1501825311-4559-1-git-send-email-gengdongjiu@huawei.com> References: <1501825311-4559-1-git-send-email-gengdongjiu@huawei.com> MIME-Version: 1.0 Content-Type: text/plain X-Originating-IP: [10.67.187.203] X-CFilter-Loop: Reflected X-Mirapoint-Virus-RAPID-Raw: score=unknown(0), refid=str=0001.0A090202.5984048A.0068, ss=1, re=0.000, recu=0.000, reip=0.000, cl=1, cld=1, fgs=0, ip=0.0.0.0, so=2014-11-16 11:51:01, dmn=2013-03-21 17:37:32 X-Mirapoint-Loop-Id: 819f74fb690641ac697ab5e3113b198f X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.4.x-2.6.x [generic] [fuzzy] X-Received-From: 45.249.212.187 Subject: [Qemu-arm] [PATCH v7 3/3] ACPI: build and enable APEI GHES in the Makefile and configuration X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 04 Aug 2017 05:22:30 -0000 Add CONFIG_ACPI_APEI configuration in the Makefile and enable it in the arm-softmmu.mak Signed-off-by: Dongjiu Geng --- thanks a lot Michael and Laszlo's review and comments: change since v5: (1) no change change since v4: (1) fix email threading in this series is incorrect issue change since v3: (1) change name to "CONFIG_ACPI_APEI" from CONFIG_ACPI_APEI_GENERATION --- default-configs/arm-softmmu.mak | 1 + hw/acpi/Makefile.objs | 1 + 2 files changed, 2 insertions(+) diff --git a/default-configs/arm-softmmu.mak b/default-configs/arm-softmmu.mak index 1e3bd2b..ee6f5fc 100644 --- a/default-configs/arm-softmmu.mak +++ b/default-configs/arm-softmmu.mak @@ -121,3 +121,4 @@ CONFIG_ACPI=y CONFIG_SMBIOS=y CONFIG_ASPEED_SOC=y CONFIG_GPIO_KEY=y +CONFIG_ACPI_APEI=y diff --git a/hw/acpi/Makefile.objs b/hw/acpi/Makefile.objs index 11c35bc..bafb148 100644 --- a/hw/acpi/Makefile.objs +++ b/hw/acpi/Makefile.objs @@ -6,6 +6,7 @@ common-obj-$(CONFIG_ACPI_MEMORY_HOTPLUG) += memory_hotplug.o common-obj-$(CONFIG_ACPI_CPU_HOTPLUG) += cpu.o common-obj-$(CONFIG_ACPI_NVDIMM) += nvdimm.o common-obj-$(CONFIG_ACPI_VMGENID) += vmgenid.o +common-obj-$(CONFIG_ACPI_APEI) += hest_ghes.o common-obj-$(call lnot,$(CONFIG_ACPI_X86)) += acpi-stub.o common-obj-y += acpi_interface.o -- 1.8.3.1 From MAILER-DAEMON Fri Aug 04 01:22:35 2017 Received: from list by lists.gnu.org with archive (Exim 4.71) id 1ddV4E-0003VP-Oq for mharc-qemu-arm@gnu.org; Fri, 04 Aug 2017 01:22:34 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:56403) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ddV4B-0003Rl-5v for qemu-arm@nongnu.org; Fri, 04 Aug 2017 01:22:33 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ddV49-0007Ax-1T for qemu-arm@nongnu.org; Fri, 04 Aug 2017 01:22:31 -0400 Received: from szxga01-in.huawei.com ([45.249.212.187]:4477) by eggs.gnu.org with esmtps (TLS1.0:RSA_ARCFOUR_SHA1:16) (Exim 4.71) (envelope-from ) id 1ddV43-0006wX-OC; Fri, 04 Aug 2017 01:22:24 -0400 Received: from 172.30.72.54 (EHLO dggeml405-hub.china.huawei.com) ([172.30.72.54]) by dggrg01-dlp.huawei.com (MOS 4.4.6-GA FastPath queued) with ESMTP id ATU24760; Fri, 04 Aug 2017 13:22:17 +0800 (CST) Received: from linux.huawei.com (10.67.187.203) by dggeml405-hub.china.huawei.com (10.3.17.49) with Microsoft SMTP Server id 14.3.301.0; Fri, 4 Aug 2017 13:22:05 +0800 From: Dongjiu Geng To: , , , , , CC: , Date: Fri, 4 Aug 2017 13:41:48 +0800 Message-ID: <1501825311-4559-1-git-send-email-gengdongjiu@huawei.com> X-Mailer: git-send-email 1.7.7 MIME-Version: 1.0 Content-Type: text/plain X-Originating-IP: [10.67.187.203] X-CFilter-Loop: Reflected X-Mirapoint-Virus-RAPID-Raw: score=unknown(0), refid=str=0001.0A090202.5984048B.0012, ss=1, re=0.000, recu=0.000, reip=0.000, cl=1, cld=1, fgs=0, ip=0.0.0.0, so=2014-11-16 11:51:01, dmn=2013-03-21 17:37:32 X-Mirapoint-Loop-Id: 439bf95a091420e840c2f8f9b05d7c3e X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.4.x-2.6.x [generic] [fuzzy] X-Received-From: 45.249.212.187 Subject: [Qemu-arm] [PATCH v7 0/3] Generate APEI GHES table and dynamically record CPER X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 04 Aug 2017 05:22:33 -0000 In the armv8 platform, the mainly hardware error source are ARMv8 SEA/SEI/GSIV. For the ARMv8 SEA/SEI, the KVM or host kernel will signal SIGBUS or use other interface to notify user space, such as Qemu. After Qemu gets the notification, it will record the CPER and inject the SEA/SEI to KVM. this series of patches will generate APEI table when guest OS boot up, and dynamically record CPER for the guest OS about the generic hardware errors, currently the userspace only handle the memory section hardware errors. Before Qemu record the CPER, it needs to check the ACK value written by the guest OS to avoid read-write race condition. Below is the APEI/GHESV2/CPER table layout, the max number of error soure is 11, which is classified by notification type, now only enable the SEA/SEI notification type error source. etc/acpi/tables etc/hardware_errors ==================== ========================================== + +--------------------------+ +------------------+ | | HEST | | address | +--------------+ | +--------------------------+ | registers | | Error Status | | | GHES0 | | +----------------+ | Data Block 0 | | +--------------------------+ +--------->| |status_address0 |------------->| +------------+ | | ................. | | | +----------------+ | | CPER | | | error_status_address-----+-+ +------->| |status_address1 |----------+ | | CPER | | | ................. | | | +----------------+ | | | .... | | | read_ack_register--------+-+ | | ............. | | | | CPER | | | read_ack_preserve | | | +------------------+ | | +-+------------+ | | read_ack_write | | | +----->| |status_address10|--------+ | | Error Status | + +--------------------------+ | | | | +----------------+ | | | Data Block 1 | | | GHES1 | +-+-+----->| |ack_address0 |--+ | +-->| +------------+ + +--------------------------+ | | | +----------------+ | | | | CPER | | | ................. | | | +--->| |ack_address1 |--+-+ | | | CPER | | | error_status_address-----+---+ | | | +----------------+ | | | | | .... | | | ................. | | | | | ............. | | | | | | CPER | | | read_ack_register--------+-----+-+ | +----------------+ | | | +-+------------+ | | read_ack_preserve | | +->| |ack_address10 |--+-+-+ | | |.......... | | | read_ack_write | | | | +----------------+ | | | | | +------------+ + +--------------------------| | | | | ack0 |<-+ | | | | Error Status | | | ............... | | | | +----------------+ | | | | Data Block 10| + +--------------------------+ | | | | ack1 |<---+ | +---->| +------------+ | | GHES10 | | | | +----------------+ | | | CPER | + +--------------------------+ | | | | .... | | | | CPER | | | ................. | | | | +--------------+ | | | | .... | | | error_status_address-----+-----+ | | | ack10 |<---- + | | CPER | | | ................. | | | +----------------+ +-+------------+ | | read_ack_register--------+---------+ | | read_ack_preserve | | | read_ack_write | + +--------------------------+ After injecting a SEA/SEI ghes error, the gueset OS kernel log will be shown as below: [ 142.911115] {1}[Hardware Error]: Hardware error from APEI Generic Hardware Error Source: 8 [ 142.913141] {1}[Hardware Error]: event severity: recoverable [ 142.914498] {1}[Hardware Error]: Error 0, type: recoverable [ 142.915851] {1}[Hardware Error]: section_type: memory error [ 142.917163] {1}[Hardware Error]: physical_address: 0x0000000000001111 [ 142.918792] {1}[Hardware Error]: error_type: 3, multi-bit ECC how to test: 1. In the guest OS, use this command to dump the APEI table: "iasl -p ./HEST -d /sys/firmware/acpi/tables/HEST" 2. And find the address for the generic error status block according to the notification type 3. then find the CPER record through the generic error status block. For example(notification type is SEA): (1) root@genericarmv8:~# iasl -p ./HEST -d /sys/firmware/acpi/tables/HEST (2) root@genericarmv8:~# cat HEST.dsl /* * Intel ACPI Component Architecture * AML/ASL+ Disassembler version 20170728 (64-bit version) * Copyright (c) 2000 - 2017 Intel Corporation * * Disassembly of /sys/firmware/acpi/tables/HEST, Mon Sep 5 07:59:17 2016 * * ACPI Data Table [HEST] * * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue */ .................................................................................. [308h 0776 2] Subtable Type : 000A [Generic Hardware Error Source V2] [30Ah 0778 2] Source Id : 0008 [30Ch 0780 2] Related Source Id : FFFF [30Eh 0782 1] Reserved : 00 [30Fh 0783 1] Enabled : 01 [310h 0784 4] Records To Preallocate : 00000001 [314h 0788 4] Max Sections Per Record : 00000001 [318h 0792 4] Max Raw Data Length : 00001000 [31Ch 0796 12] Error Status Address : [Generic Address Structure] [31Ch 0796 1] Space ID : 00 [SystemMemory] [31Dh 0797 1] Bit Width : 40 [31Eh 0798 1] Bit Offset : 00 [31Fh 0799 1] Encoded Access Width : 04 [QWord Access:64] [320h 0800 8] Address : 00000000785D0040 [328h 0808 28] Notify : [Hardware Error Notification Structure] [328h 0808 1] Notify Type : 08 [SEA] [329h 0809 1] Notify Length : 1C [32Ah 0810 2] Configuration Write Enable : 0000 [32Ch 0812 4] PollInterval : 00000000 [330h 0816 4] Vector : 00000000 [334h 0820 4] Polling Threshold Value : 00000000 [338h 0824 4] Polling Threshold Window : 00000000 [33Ch 0828 4] Error Threshold Value : 00000000 [340h 0832 4] Error Threshold Window : 00000000 [344h 0836 4] Error Status Block Length : 00001000 [348h 0840 12] Read Ack Register : [Generic Address Structure] [348h 0840 1] Space ID : 00 [SystemMemory] [349h 0841 1] Bit Width : 40 [34Ah 0842 1] Bit Offset : 00 [34Bh 0843 1] Encoded Access Width : 04 [QWord Access:64] [34Ch 0844 8] Address : 00000000785D0098 [354h 0852 8] Read Ack Preserve : 00000000FFFFFFFE [35Ch 0860 8] Read Ack Write : 0000000000000001 [364h 0868 2] Subtable Type : 000A [Generic Hardware Error Source V2] [366h 0870 2] Source Id : 0009 [368h 0872 2] Related Source Id : FFFF [36Ah 0874 1] Reserved : 00 [36Bh 0875 1] Enabled : 01 [36Ch 0876 4] Records To Preallocate : 00000001 [370h 0880 4] Max Sections Per Record : 00000001 [374h 0884 4] Max Raw Data Length : 00001000 [378h 0888 12] Error Status Address : [Generic Address Structure] [378h 0888 1] Space ID : 00 [SystemMemory] [379h 0889 1] Bit Width : 40 [37Ah 0890 1] Bit Offset : 00 [37Bh 0891 1] Encoded Access Width : 04 [QWord Access:64] [37Ch 0892 8] Address : 00000000785D0048 [384h 0900 28] Notify : [Hardware Error Notification Structure] [384h 0900 1] Notify Type : 09 [SEI] [385h 0901 1] Notify Length : 1C [386h 0902 2] Configuration Write Enable : 0000 [388h 0904 4] PollInterval : 00000000 [38Ch 0908 4] Vector : 00000000 [390h 0912 4] Polling Threshold Value : 00000000 [394h 0916 4] Polling Threshold Window : 00000000 [398h 0920 4] Error Threshold Value : 00000000 [39Ch 0924 4] Error Threshold Window : 00000000 [3A0h 0928 4] Error Status Block Length : 00001000 [3A4h 0932 12] Read Ack Register : [Generic Address Structure] [3A4h 0932 1] Space ID : 00 [SystemMemory] [3A5h 0933 1] Bit Width : 40 [3A6h 0934 1] Bit Offset : 00 [3A7h 0935 1] Encoded Access Width : 04 [QWord Access:64] [3A8h 0936 8] Address : 00000000785D00A0 [3B0h 0944 8] Read Ack Preserve : 00000000FFFFFFFE [3B8h 0952 8] Read Ack Write : 000000000000000 ..................................................................................... (3) according to above table, the address that contains the physical address of a block of memory that holds the error status data for SEA notification error source is 0x00000000785D0040 (4) the address for SEA notification error source is 0x785d8108 (qemu) xp /1 0x00000000785D0040 00000000785d0040: 0x785d8108 (5) check the content of generic error status block and generic error data entry (qemu) xp /100x 0x785d8108 00000000785d8108: 0x00000000 0x00000000 0x00000000 0x00000098 00000000785d8118: 0x00000000 0xa5bc1114 0x4ede6f64 0x833e63b8 00000000785d8128: 0xb1837ced 0x00000000 0x00000300 0x00000050 00000000785d8138: 0x00000000 0x00000000 0x00000000 0x00000000 00000000785d8148: 0x00000000 0x00000000 0x00000000 0x00000000 00000000785d8158: 0x00000000 0x00000000 0x00000000 0x00004002 00000000785d8168: 0x00000000 0x00000000 0x00000000 0x00001111 00000000785d8178: 0x00000000 0x00000000 0x00000000 0x00000000 00000000785d8188: 0x00000000 0x00000000 0x00000000 0x00000000 00000000785d8198: 0x00000000 0x00000000 0x00000000 0x00000000 00000000785d81a8: 0x00000000 0x00000003 0x00000000 0x00000000 00000000785d81b8: 0x00000000 0x00000000 0x00000000 0x00000000 00000000785d81c8: 0x00000000 0x00000000 0x00000000 0x00000000 00000000785d81d8: 0x00000000 0x00000000 0x00000000 0x00000000 00000000785d81e8: 0x00000000 0x00000000 0x00000000 0x00000000 00000000785d81f8: 0x00000000 0x00000000 0x00000000 0x00000000 00000000785d8208: 0x00000000 0x00000000 0x00000000 0x00000000 00000000785d8218: 0x00000000 0x00000000 0x00000000 0x00000000 00000000785d8228: 0x00000000 0x00000000 0x00000000 0x00000000 00000000785d8238: 0x00000000 0x00000000 0x00000000 0x00000000 00000000785d8248: 0x00000000 0x00000000 0x00000000 0x00000000 00000000785d8258: 0x00000000 0x00000000 0x00000000 0x00000000 00000000785d8268: 0x00000000 0x00000000 0x00000000 0x00000000 00000000785d8278: 0x00000000 0x00000000 0x00000000 0x00000000 00000000785d8288: 0x00000000 0x00000000 0x00000000 0x00000000 (6) check the OSPM's ACK value(for example SEA) /* The address of ACK value */ (qemu) xp /1 0x00000000785D0098 00000000785d0098: 0x785d00f0 /* Before OSPM acknowledges the error */ (qemu) xp /1 0x785d00f0 00000000785d00f0: 0x00000000 /* After OSPM acknowledges the error */ (qemu) xp /1 0x785d00f0 00000000785d00f0: 0x00000001 Dongjiu Geng (3): ACPI: add APEI/HEST/CPER structures and macros ACPI: Add APEI GHES Table Generation support ACPI: build and enable APEI GHES in the Makefile and configuration default-configs/arm-softmmu.mak | 1 + hw/acpi/Makefile.objs | 1 + hw/acpi/aml-build.c | 2 + hw/acpi/hest_ghes.c | 370 ++++++++++++++++++++++++++++++++++++++++ hw/arm/virt-acpi-build.c | 6 + include/hw/acpi/acpi-defs.h | 193 +++++++++++++++++++++ include/hw/acpi/aml-build.h | 1 + include/hw/acpi/hest_ghes.h | 47 +++++ 8 files changed, 621 insertions(+) create mode 100644 hw/acpi/hest_ghes.c create mode 100644 include/hw/acpi/hest_ghes.h -- 1.8.3.1 From MAILER-DAEMON Fri Aug 04 01:22:35 2017 Received: from list by lists.gnu.org with archive (Exim 4.71) id 1ddV4F-0003Vw-24 for mharc-qemu-arm@gnu.org; Fri, 04 Aug 2017 01:22:35 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:56401) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ddV4B-0003Rh-40 for qemu-arm@nongnu.org; Fri, 04 Aug 2017 01:22:32 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ddV49-0007BD-3w for qemu-arm@nongnu.org; Fri, 04 Aug 2017 01:22:31 -0400 Received: from szxga01-in.huawei.com ([45.249.212.187]:4476) by eggs.gnu.org with esmtps (TLS1.0:RSA_ARCFOUR_SHA1:16) (Exim 4.71) (envelope-from ) id 1ddV43-0006wV-Np; Fri, 04 Aug 2017 01:22:24 -0400 Received: from 172.30.72.54 (EHLO dggeml405-hub.china.huawei.com) ([172.30.72.54]) by dggrg01-dlp.huawei.com (MOS 4.4.6-GA FastPath queued) with ESMTP id ATU24758; Fri, 04 Aug 2017 13:22:16 +0800 (CST) Received: from linux.huawei.com (10.67.187.203) by dggeml405-hub.china.huawei.com (10.3.17.49) with Microsoft SMTP Server id 14.3.301.0; Fri, 4 Aug 2017 13:22:05 +0800 From: Dongjiu Geng To: , , , , , CC: , Date: Fri, 4 Aug 2017 13:41:49 +0800 Message-ID: <1501825311-4559-2-git-send-email-gengdongjiu@huawei.com> X-Mailer: git-send-email 1.7.7 In-Reply-To: <1501825311-4559-1-git-send-email-gengdongjiu@huawei.com> References: <1501825311-4559-1-git-send-email-gengdongjiu@huawei.com> MIME-Version: 1.0 Content-Type: text/plain X-Originating-IP: [10.67.187.203] X-CFilter-Loop: Reflected X-Mirapoint-Virus-RAPID-Raw: score=unknown(0), refid=str=0001.0A090206.5984048A.0051, ss=1, re=0.000, recu=0.000, reip=0.000, cl=1, cld=1, fgs=0, ip=0.0.0.0, so=2014-11-16 11:51:01, dmn=2013-03-21 17:37:32 X-Mirapoint-Loop-Id: 661646d846c380a1e62e0076e22f5390 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.4.x-2.6.x [generic] [fuzzy] X-Received-From: 45.249.212.187 Subject: [Qemu-arm] [PATCH v7 1/3] ACPI: add APEI/HEST/CPER structures and macros X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 04 Aug 2017 05:22:33 -0000 (1) Add related APEI/HEST table structures and macros, these definition refer to ACPI 6.1 and UEFI 2.6 spec. (2) Add generic error status block and CPER memory section definition, user space only handle memory section errors. Signed-off-by: Dongjiu Geng --- thanks Michael and Laszlo's review: change since v5: (1) update the commit message title (2) remove UUID_BE and UEFI_CPER_SEC_PLATFORM_MEM macros (3) remove including "qemu/uuid.h" file in this patch (4) remove including "hest_ghes.h" file in this patch (5) drop "this is" from the comment of structures and macros (6) replace the "QemuUUID section_type_le" to "uint8_t section_type_le[16]" chnage since v4: (1) fix email threading in this series is incorrect issue change since v3: (1) separate the original one patch into three patches: one is new ACPI structures and macros, another is C source file to generate ACPI HEST table and dynamically record CPER ,final patch is the change about Makefile and configuration (2) add comments about where the ACPI structures and macros come from, for example, they come from the UEFI Spec 2.6, "xxxxxxxxxxxx"; ACPI 6.1 spec, "xxxxxxxxxxxxxx". (3) correct the macros name, for emaple, prefix some macro names with "UEFI_". (4) remove the uuid_le struct and use the QemuUUID in the include/qemu/uuid.h" (5) remove the duplicate ACPI address space, because it already defined in the "include/hw/acpi/aml-build.h" (6) remove the acpi_generic_address structure because same definition exists in the AcpiGenericAddress. (7) rename the struct acpi_hest_notify to AcpiHestNotifyType (8) rename the struct acpi_hest_types to AcpiHestSourceType (9) rename enum constants AcpiHestSourceType to ACPI_HEST_SOURCE_xxx from ACPI_HEST_TYPE_xxx (10) remove the NOT_USED{3,4,5} enum constants in the AcpiHestSourceType. (11) add missed QEMU_PACKED for the struct definition. (12) remove the defnition of AcpiGenericErrorData, and rename the AcpiGenericErrorDataV300 to AcpiGenericErrorData. (13) use the QemuUUID type for the "section_type" field AcpiGenericErrorData, and rename it to section_type_le. (14) moving type AcpiGenericErrorSeverity above AcpiGenericErrorData and AcpiGenericErrorDataV300, and remarking on the "error_severity" fields that they take their values from AcpiGenericErrorSeverity (15) remove the wrongly call to BERT(Boot Error Record Table) (16) add comments for the struction member, for example, pint out that the block_status member in the AcpiGenericErrorStatus is a bitmask composed of ACPI_GEBS_xxx macros (17) remove the hardware error source notification type list, and rename the MAX_ERROR_SOURCE_COUNT_V6 to ACPI_HEST_NOTIFY_RESERVED. (18) remove the physical_addr member of GhesErrorState (19) change the "uint64_t ghes_addr_le[8]" in GhesErrorState to uint64_t ghes_addr_le (20) change the second parameter to "error_physical_addr" in the ghes_update_guest API statement --- include/hw/acpi/acpi-defs.h | 193 ++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 193 insertions(+) diff --git a/include/hw/acpi/acpi-defs.h b/include/hw/acpi/acpi-defs.h index 4cc3630..ff9525e 100644 --- a/include/hw/acpi/acpi-defs.h +++ b/include/hw/acpi/acpi-defs.h @@ -295,6 +295,44 @@ typedef struct AcpiMultipleApicTable AcpiMultipleApicTable; #define ACPI_APIC_GENERIC_TRANSLATOR 15 #define ACPI_APIC_RESERVED 16 /* 16 and greater are reserved */ +/* UEFI Spec 2.6, "N.2.5 Memory Error Section */ +#define UEFI_CPER_MEM_VALID_ERROR_STATUS 0x0001 +#define UEFI_CPER_MEM_VALID_PA 0x0002 +#define UEFI_CPER_MEM_VALID_PA_MASK 0x0004 +#define UEFI_CPER_MEM_VALID_NODE 0x0008 +#define UEFI_CPER_MEM_VALID_CARD 0x0010 +#define UEFI_CPER_MEM_VALID_MODULE 0x0020 +#define UEFI_CPER_MEM_VALID_BANK 0x0040 +#define UEFI_CPER_MEM_VALID_DEVICE 0x0080 +#define UEFI_CPER_MEM_VALID_ROW 0x0100 +#define UEFI_CPER_MEM_VALID_COLUMN 0x0200 +#define UEFI_CPER_MEM_VALID_BIT_POSITION 0x0400 +#define UEFI_CPER_MEM_VALID_REQUESTOR 0x0800 +#define UEFI_CPER_MEM_VALID_RESPONDER 0x1000 +#define UEFI_CPER_MEM_VALID_TARGET 0x2000 +#define UEFI_CPER_MEM_VALID_ERROR_TYPE 0x4000 +#define UEFI_CPER_MEM_VALID_RANK_NUMBER 0x8000 +#define UEFI_CPER_MEM_VALID_CARD_HANDLE 0x10000 +#define UEFI_CPER_MEM_VALID_MODULE_HANDLE 0x20000 +#define UEFI_CPER_MEM_ERROR_TYPE_MULTI_ECC 3 + +/* From the ACPI 6.1 spec, "18.3.2.9 Hardware Error Notification" */ + +enum AcpiHestNotifyType { + ACPI_HEST_NOTIFY_POLLED = 0, + ACPI_HEST_NOTIFY_EXTERNAL = 1, + ACPI_HEST_NOTIFY_LOCAL = 2, + ACPI_HEST_NOTIFY_SCI = 3, + ACPI_HEST_NOTIFY_NMI = 4, + ACPI_HEST_NOTIFY_CMCI = 5, /* ACPI 5.0 */ + ACPI_HEST_NOTIFY_MCE = 6, /* ACPI 5.0 */ + ACPI_HEST_NOTIFY_GPIO = 7, /* ACPI 6.0 */ + ACPI_HEST_NOTIFY_SEA = 8, /* ACPI 6.1 */ + ACPI_HEST_NOTIFY_SEI = 9, /* ACPI 6.1 */ + ACPI_HEST_NOTIFY_GSIV = 10, /* ACPI 6.1 */ + ACPI_HEST_NOTIFY_RESERVED = 11 /* 11 and greater are reserved */ +}; + /* * MADT sub-structures (Follow MULTIPLE_APIC_DESCRIPTION_TABLE) */ @@ -475,6 +513,161 @@ struct AcpiSystemResourceAffinityTable } QEMU_PACKED; typedef struct AcpiSystemResourceAffinityTable AcpiSystemResourceAffinityTable; +/* Hardware Error Notification, from the ACPI 6.1 + * spec, "18.3.2.9 Hardware Error Notification" + */ +struct AcpiHestNotify { + uint8_t type; + uint8_t length; + uint16_t config_write_enable; + uint32_t poll_interval; + uint32_t vector; + uint32_t polling_threshold_value; + uint32_t polling_threshold_window; + uint32_t error_threshold_value; + uint32_t error_threshold_window; +} QEMU_PACKED; +typedef struct AcpiHestNotify AcpiHestNotify; + +/* From ACPI 6.1, sections "18.3.2.1 IA-32 Architecture Machine + * Check Exception" through "18.3.2.8 Generic Hardware Error Source version 2". + */ +enum AcpiHestSourceType { + ACPI_HEST_SOURCE_IA32_CHECK = 0, + ACPI_HEST_SOURCE_IA32_CORRECTED_CHECK = 1, + ACPI_HEST_SOURCE_IA32_NMI = 2, + ACPI_HEST_SOURCE_AER_ROOT_PORT = 6, + ACPI_HEST_SOURCE_AER_ENDPOINT = 7, + ACPI_HEST_SOURCE_AER_BRIDGE = 8, + ACPI_HEST_SOURCE_GENERIC_ERROR = 9, + ACPI_HEST_SOURCE_GENERIC_ERROR_V2 = 10, + ACPI_HEST_SOURCE_RESERVED = 11 /* 11 and greater are reserved */ +}; + +/* Block status bitmasks from ACPI 6.1, "18.3.2.7.1 Generic Error Data" */ +#define ACPI_GEBS_UNCORRECTABLE (1) +#define ACPI_GEBS_CORRECTABLE (1 << 1) +#define ACPI_GEBS_MULTIPLE_UNCORRECTABLE (1 << 2) +#define ACPI_GEBS_MULTIPLE_CORRECTABLE (1 << 3) +/* 10 bits, error data entry count */ +#define ACPI_GEBS_ERROR_ENTRY_COUNT (0x3FF << 4) + +/* Generic Hardware Error Source Structure, refer to ACPI 6.1 + * "18.3.2.7 Generic Hardware Error Source". in this struct the + * "type" field has to be ACPI_HEST_SOURCE_GENERIC_ERROR + */ + +struct AcpiGenericHardwareErrorSource { + uint16_t type; + uint16_t source_id; + uint16_t related_source_id; + uint8_t flags; + uint8_t enabled; + uint32_t number_of_records; + uint32_t max_sections_per_record; + uint32_t max_raw_data_length; + struct AcpiGenericAddress error_status_address; + struct AcpiHestNotify notify; + uint32_t error_status_block_length; +} QEMU_PACKED; +typedef struct AcpiGenericHardwareErrorSource AcpiGenericHardwareErrorSource; + +/* Generic Hardware Error Source, version 2, ACPI 6.1, "18.3.2.8 Generic + * Hardware Error Source version 2", in this struct the "type" field has to + * be ACPI_HEST_SOURCE_GENERIC_ERROR_V2 + */ +struct AcpiGenericHardwareErrorSourceV2 { + uint16_t type; + uint16_t source_id; + uint16_t related_source_id; + uint8_t flags; + uint8_t enabled; + uint32_t number_of_records; + uint32_t max_sections_per_record; + uint32_t max_raw_data_length; + struct AcpiGenericAddress error_status_address; + struct AcpiHestNotify notify; + uint32_t error_status_block_length; + struct AcpiGenericAddress read_ack_register; + uint64_t read_ack_preserve; + uint64_t read_ack_write; +} QEMU_PACKED; +typedef struct AcpiGenericHardwareErrorSourceV2 + AcpiGenericHardwareErrorSourceV2; + +/* Generic Error Status block, from ACPI 6.1, + * "18.3.2.7.1 Generic Error Data" + */ +struct AcpiGenericErrorStatus { + /* It is a bitmask composed of ACPI_GEBS_xxx macros */ + uint32_t block_status; + uint32_t raw_data_offset; + uint32_t raw_data_length; + uint32_t data_length; + uint32_t error_severity; +} QEMU_PACKED; +typedef struct AcpiGenericErrorStatus AcpiGenericErrorStatus; + +enum AcpiGenericErrorSeverity { + ACPI_CPER_SEV_RECOVERABLE, + ACPI_CPER_SEV_FATAL, + ACPI_CPER_SEV_CORRECTED, + ACPI_CPER_SEV_NONE, +}; + +/* Generic Error Data entry, revision number is 0x0300, + * ACPI 6.1, "18.3.2.7.1 Generic Error Data" + */ +struct AcpiGenericErrorData { + uint8_t section_type_le[16]; + /* The "error_severity" fields that they take their + * values from AcpiGenericErrorSeverity + */ + uint32_t error_severity; + uint16_t revision; + uint8_t validation_bits; + uint8_t flags; + uint32_t error_data_length; + uint8_t fru_id[16]; + uint8_t fru_text[20]; + uint64_t time_stamp; +} QEMU_PACKED; +typedef struct AcpiGenericErrorData AcpiGenericErrorData; + +/* From UEFI 2.6, "N.2.5 Memory Error Section" */ +struct UefiCperSecMemErr { + uint64_t validation_bits; + uint64_t error_status; + uint64_t physical_addr; + uint64_t physical_addr_mask; + uint16_t node; + uint16_t card; + uint16_t module; + uint16_t bank; + uint16_t device; + uint16_t row; + uint16_t column; + uint16_t bit_pos; + uint64_t requestor_id; + uint64_t responder_id; + uint64_t target_id; + uint8_t error_type; + uint8_t reserved; + uint16_t rank; + uint16_t mem_array_handle; /* card handle in UEFI 2.4 */ + uint16_t mem_dev_handle; /* module handle in UEFI 2.4 */ +} QEMU_PACKED; +typedef struct UefiCperSecMemErr UefiCperSecMemErr; + +/* + * HEST Description Table + */ +struct AcpiHardwareErrorSourceTable { + ACPI_TABLE_HEADER_DEF /* ACPI common table header */ + uint32_t error_source_count; +} QEMU_PACKED; +typedef struct AcpiHardwareErrorSourceTable AcpiHardwareErrorSourceTable; + #define ACPI_SRAT_PROCESSOR_APIC 0 #define ACPI_SRAT_MEMORY 1 #define ACPI_SRAT_PROCESSOR_x2APIC 2 -- 1.8.3.1 From MAILER-DAEMON Fri Aug 04 01:22:41 2017 Received: from list by lists.gnu.org with archive (Exim 4.71) id 1ddV4L-0003bV-85 for mharc-qemu-arm@gnu.org; Fri, 04 Aug 2017 01:22:41 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:56489) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ddV4F-0003Wc-N9 for qemu-arm@nongnu.org; Fri, 04 Aug 2017 01:22:38 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ddV4C-0007H5-Re for qemu-arm@nongnu.org; Fri, 04 Aug 2017 01:22:35 -0400 Received: from szxga01-in.huawei.com ([45.249.212.187]:4479) by eggs.gnu.org with esmtps (TLS1.0:RSA_ARCFOUR_SHA1:16) (Exim 4.71) (envelope-from ) id 1ddV43-0006wZ-T4; Fri, 04 Aug 2017 01:22:25 -0400 Received: from 172.30.72.54 (EHLO dggeml405-hub.china.huawei.com) ([172.30.72.54]) by dggrg01-dlp.huawei.com (MOS 4.4.6-GA FastPath queued) with ESMTP id ATU24753; Fri, 04 Aug 2017 13:22:16 +0800 (CST) Received: from linux.huawei.com (10.67.187.203) by dggeml405-hub.china.huawei.com (10.3.17.49) with Microsoft SMTP Server id 14.3.301.0; Fri, 4 Aug 2017 13:22:05 +0800 From: Dongjiu Geng To: , , , , , CC: , Date: Fri, 4 Aug 2017 13:41:50 +0800 Message-ID: <1501825311-4559-3-git-send-email-gengdongjiu@huawei.com> X-Mailer: git-send-email 1.7.7 In-Reply-To: <1501825311-4559-1-git-send-email-gengdongjiu@huawei.com> References: <1501825311-4559-1-git-send-email-gengdongjiu@huawei.com> MIME-Version: 1.0 Content-Type: text/plain X-Originating-IP: [10.67.187.203] X-CFilter-Loop: Reflected X-Mirapoint-Virus-RAPID-Raw: score=unknown(0), refid=str=0001.0A090206.5984048A.005F, ss=1, re=0.000, recu=0.000, reip=0.000, cl=1, cld=1, fgs=0, ip=0.0.0.0, so=2014-11-16 11:51:01, dmn=2013-03-21 17:37:32 X-Mirapoint-Loop-Id: 41aa380a158c5e0a3681cbac5eb805df X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.4.x-2.6.x [generic] [fuzzy] X-Received-From: 45.249.212.187 Subject: [Qemu-arm] [PATCH v7 2/3] ACPI: Add APEI GHES Table Generation support X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 04 Aug 2017 05:22:39 -0000 This implements APEI GHES Table by passing the error CPER info to the guest via a fw_cfg_blob. After a CPER info is recorded, an SEA(Synchronous External Abort)/SEI(SError Interrupt) exception will be injected into the guest OS. Below is the table layout, the max number of error soure is 11, which is classified by notification type. etc/acpi/tables etc/hardware_errors ==================== ========================================== + +--------------------------+ +------------------+ | | HEST | | address | +--------------+ | +--------------------------+ | registers | | Error Status | | | GHES0 | | +----------------+ | Data Block 0 | | +--------------------------+ +--------->| |status_address0 |------------->| +------------+ | | ................. | | | +----------------+ | | CPER | | | error_status_address-----+-+ +------->| |status_address1 |----------+ | | CPER | | | ................. | | | +----------------+ | | | .... | | | read_ack_register--------+-+ | | ............. | | | | CPER | | | read_ack_preserve | | | +------------------+ | | +-+------------+ | | read_ack_write | | | +----->| |status_address10|--------+ | | Error Status | + +--------------------------+ | | | | +----------------+ | | | Data Block 1 | | | GHES1 | +-+-+----->| |ack_address0 |--+ | +-->| +------------+ + +--------------------------+ | | | +----------------+ | | | | CPER | | | ................. | | | +--->| |ack_address1 |--+-+ | | | CPER | | | error_status_address-----+---+ | | | +----------------+ | | | | | .... | | | ................. | | | | | ............. | | | | | | CPER | | | read_ack_register--------+-----+-+ | +----------------+ | | | +-+------------+ | | read_ack_preserve | | +->| |ack_address10 |--+-+-+ | | |.......... | | | read_ack_write | | | | +----------------+ | | | | | +------------+ + +--------------------------| | | | | ack0 |<-+ | | | | Error Status | | | ............... | | | | +----------------+ | | | | Data Block 10| + +--------------------------+ | | | | ack1 |<---+ | +---->| +------------+ | | GHES10 | | | | +----------------+ | | | CPER | + +--------------------------+ | | | | .... | | | | CPER | | | ................. | | | | +--------------+ | | | | .... | | | error_status_address-----+-----+ | | | ack10 |<---- + | | CPER | | | ................. | | | +----------------+ +-+------------+ | | read_ack_register--------+---------+ | | read_ack_preserve | | | read_ack_write | + +--------------------------+ For GHESv2 error source, the OSPM must acknowledges the error via Read Ack register. so user space must check the ack value to avoid read-write race condition. Signed-off-by: Dongjiu Geng --- thanks a lot Michael and Laszlo's review and comments: change since v6: (1) update the commit message change since v5: (1) move to GHESv2 error source from GHESv1, because we maily use the GHESv2 (2) add the GHESv2 error source layout in the comments (2) add the logic to read the ack value from OSPM to avoid read-write race condition (3) including header files "aml-build.h" and "hest_ghes.h" in this patch to make it reasonable (4) calculate the fw_cfg blob offsets that should be patched in more fine-grained steps, with multiple separate increments, using: - structure type names, - sizeof operators, - offsetof macros, - and possibly a separate comment for each offset increment. (5) remove page boundary refers to 4096 in the "bios_linker_loader_alloc" (6) using build_append_int_noprefix to avoid use pointer math, so that the code is easily readable (7) change memory section definition to array from QemuUUID (8) only enable SEA/SEI notification hardware error source to avoid guest OS ACPI driver probe warning change since v4: 1. fix email threading in this series is incorrect issue change since v3: 1. remove the unnecessary include for "hw/acpi/vmgenid.h" in hw/arm/virt-acpi-build.c 2. add conversion between LE and host-endian for the CPER record 3. handle the case that run out of the preallocated memory for the CPER record 4. change to use g_malloc0 instead of g_malloc 5. change block_reqr_size name to block_rer_size 6. change QEMU coding style, that is, the operator is at the end of the line. 7. drop the ERROR_STATUS_ADDRESS_OFFSET and GAS_ADDRESS_OFFSET macros (from the header file as well), and use the offsetof to replace it. 8. remove the init_aml_allocator() / free_aml_allocator(), calculate the needed size, and push that many bytes directly to "table_data". 9. take an "OVMF header probe suppressor" into account 10.corrct HEST and CPER value assigment, for example, correct the source_id for every error source, this identifier of source_id should be unique among all error sources; 11. create only one WRITE_POINTER command, for the base address of "etc/hardware_errors". This should be done outside of the loop.The base addresses of the individual error status data blocks should be calculated in ghes_update_guest(), based on the error source / notification type 12.correct the commit message lists error sources / notification types 0 through 10 (count=11 in total). 13.correct the size calculation for GHES_DATA_ADDR_FW_CFG_FILE 14.range-checked the value of "notify" before using it as an array subscript --- hw/acpi/aml-build.c | 2 + hw/acpi/hest_ghes.c | 368 ++++++++++++++++++++++++++++++++++++++++++++ hw/arm/virt-acpi-build.c | 6 + include/hw/acpi/aml-build.h | 1 + include/hw/acpi/hest_ghes.h | 47 ++++++ 5 files changed, 424 insertions(+) create mode 100644 hw/acpi/hest_ghes.c create mode 100644 include/hw/acpi/hest_ghes.h diff --git a/hw/acpi/aml-build.c b/hw/acpi/aml-build.c index c6f2032..802b98d 100644 --- a/hw/acpi/aml-build.c +++ b/hw/acpi/aml-build.c @@ -1560,6 +1560,7 @@ void acpi_build_tables_init(AcpiBuildTables *tables) tables->table_data = g_array_new(false, true /* clear */, 1); tables->tcpalog = g_array_new(false, true /* clear */, 1); tables->vmgenid = g_array_new(false, true /* clear */, 1); + tables->hardware_errors = g_array_new(false, true /* clear */, 1); tables->linker = bios_linker_loader_init(); } @@ -1570,6 +1571,7 @@ void acpi_build_tables_cleanup(AcpiBuildTables *tables, bool mfre) g_array_free(tables->table_data, true); g_array_free(tables->tcpalog, mfre); g_array_free(tables->vmgenid, mfre); + g_array_free(tables->hardware_errors, mfre); } /* Build rsdt table */ diff --git a/hw/acpi/hest_ghes.c b/hw/acpi/hest_ghes.c new file mode 100644 index 0000000..cc06662 --- /dev/null +++ b/hw/acpi/hest_ghes.c @@ -0,0 +1,368 @@ +/* + * APEI GHES table Generation + * + * Copyright (C) 2017 huawei. + * + * Author: Dongjiu Geng + * + * This work is licensed under the terms of the GNU GPL, version 2 or later. + * See the COPYING file in the top-level directory. + * + */ + +#include "qemu/osdep.h" +#include "qmp-commands.h" +#include "hw/acpi/acpi.h" +#include "hw/acpi/aml-build.h" +#include "hw/acpi/hest_ghes.h" +#include "hw/nvram/fw_cfg.h" +#include "sysemu/sysemu.h" +#include "qemu/error-report.h" + +/* The structure that stands for the layout + * GHES_ERRORS_FW_CFG_FILE fw_cfg blob + * + * etc/hardware_errors + * ========================================== + * +------------------+ + * | address | +--------------+ + * | registers | | Error Status | + * | +----------------+ | Data Block 0 | + * | |status_address0 |------------->| +------------+ + * | +----------------+ | | CPER | + * | |status_address1 |----------+ | | CPER | + * | +----------------+ | | | .... | + * | |............. | | | | CPER | + * | +----------------+ | | +------------+ + * | |status_address10|--------+ | | Error Status | + * | +----------------+ | | | Data Block 1 | + * | |ack_address0 |--+ | +-->| +------------+ + * | +----------------+ | | | | CPER | + * | |ack_address1 |--+-+ | | | CPER | + * | +----------------+ | | | | | .... | + * | | ............. | | | | | | CPER | + * | +----------------+ | | | +-+------------+ + * | |ack_address10 |--+-+-+ | | |.......... | + * | +----------------+ | | | | | +------------+ + * | | ack0 |<-+ | | | | Error Status | + * | +----------------+ | | | | Data Block10 | + * | | ack1 |<---+ | +---->| +------------+ + * | +----------------+ | | | CPER | + * | | .... | | | | CPER | + * | +--------------+ | | | | .... | + * | | ack10 |<---- + | | CPER | + * | +----------------+ +-+------------+ + */ +struct hardware_errors_buffer { + /* Generic Error Status Block register */ + uint64_t gesb_register[GHES_ACPI_HEST_NOTIFY_RESERVED]; + uint64_t ack_register[GHES_ACPI_HEST_NOTIFY_RESERVED]; + uint64_t ack_value[GHES_ACPI_HEST_NOTIFY_RESERVED]; + char gesb[GHES_MAX_RAW_DATA_LENGTH][GHES_ACPI_HEST_NOTIFY_RESERVED]; +}; + +static int ghes_record_cper(uint64_t error_block_address, + uint64_t error_physical_addr) +{ + AcpiGenericErrorStatus block; + AcpiGenericErrorData *gdata; + UefiCperSecMemErr *mem_err; + uint64_t current_block_length; + unsigned char *buffer; + /* memory section */ + char mem_section_id_le[] = {0x14, 0x11, 0xBC, 0xA5, 0x64, 0x6F, 0xDE, + 0x4E, 0xB8, 0x63, 0x3E, 0x83, 0xED, 0x7C, + 0x83, 0xB1}; + + cpu_physical_memory_read(error_block_address, &block, + sizeof(AcpiGenericErrorStatus)); + + /* Get the current generic error status block length */ + current_block_length = sizeof(AcpiGenericErrorStatus) + + le32_to_cpu(block.data_length); + + /* If the Generic Error Status Block is NULL, update + * the block header + */ + if (!block.block_status) { + block.block_status = ACPI_GEBS_UNCORRECTABLE; + block.error_severity = ACPI_CPER_SEV_RECOVERABLE; + } + + block.data_length += cpu_to_le32(sizeof(AcpiGenericErrorData)); + block.data_length += cpu_to_le32(sizeof(UefiCperSecMemErr)); + + /* check whether it runs out of the preallocated memory */ + if ((le32_to_cpu(block.data_length) + sizeof(AcpiGenericErrorStatus)) > + GHES_MAX_RAW_DATA_LENGTH) { + error_report("Record CPER out of boundary!!!"); + return GHES_CPER_FAIL; + } + + /* Write back the Generic Error Status Block to guest memory */ + cpu_physical_memory_write(error_block_address, &block, + sizeof(AcpiGenericErrorStatus)); + + /* Fill in Generic Error Data Entry */ + buffer = g_malloc0(sizeof(AcpiGenericErrorData) + + sizeof(UefiCperSecMemErr)); + + + memset(buffer, 0, sizeof(AcpiGenericErrorData) + sizeof(UefiCperSecMemErr)); + gdata = (AcpiGenericErrorData *)buffer; + + /* Memory section */ + memcpy(&(gdata->section_type_le), &mem_section_id_le, + sizeof(mem_section_id_le)); + + /* error severity is recoverable */ + gdata->error_severity = ACPI_CPER_SEV_RECOVERABLE; + gdata->revision = 0x300; /* the revision number is 0x300 */ + gdata->error_data_length = cpu_to_le32(sizeof(UefiCperSecMemErr)); + + mem_err = (UefiCperSecMemErr *) (gdata + 1); + + /* User space only handle the memory section CPER */ + + /* Hard code to Multi-bit ECC error */ + mem_err->validation_bits |= cpu_to_le32(UEFI_CPER_MEM_VALID_ERROR_TYPE); + mem_err->error_type = cpu_to_le32(UEFI_CPER_MEM_ERROR_TYPE_MULTI_ECC); + + /* Record the physical address at which the memory error occurred */ + mem_err->validation_bits |= cpu_to_le32(UEFI_CPER_MEM_VALID_PA); + mem_err->physical_addr = cpu_to_le32(error_physical_addr); + + /* Write back the Generic Error Data Entry to guest memory */ + cpu_physical_memory_write(error_block_address + current_block_length, + buffer, sizeof(AcpiGenericErrorData) + sizeof(UefiCperSecMemErr)); + + g_free(buffer); + return GHES_CPER_OK; +} + +static void +build_address(GArray *table_data, BIOSLinker *linker, + uint32_t dst_patched_offset, uint32_t src_offset, + uint8_t address_space_id , uint8_t register_bit_width, + uint8_t register_bit_offset, uint8_t access_size) +{ + uint32_t address_size = sizeof(struct AcpiGenericAddress) - + offsetof(struct AcpiGenericAddress, address); + + /* Address space */ + build_append_int_noprefix(table_data, address_space_id, 1); + /* register bit width */ + build_append_int_noprefix(table_data, register_bit_width, 1); + /* register bit offset */ + build_append_int_noprefix(table_data, register_bit_offset, 1); + /* access size */ + build_append_int_noprefix(table_data, access_size, 1); + acpi_data_push(table_data, address_size); + + /* Patch address of ERRORS fw_cfg blob into the TABLE fw_cfg blob so OSPM + * can retrieve and read it. the address size is 64 bits. + */ + bios_linker_loader_add_pointer(linker, + ACPI_BUILD_TABLE_FILE, dst_patched_offset, sizeof(uint64_t), + GHES_ERRORS_FW_CFG_FILE, src_offset); +} + +void ghes_build_acpi(GArray *table_data, GArray *hardware_error, + BIOSLinker *linker) +{ + uint32_t ghes_start = table_data->len; + uint32_t address_size, ack_value_size, error_status_address_offset; + uint32_t read_ack_register_offset, i; + /* + * The block_req_size stands for two address and one + * generic error status block + * +---------+ + * | address |-----------> +---------+ + * +---------+ | CPER | + * | ack | | CPER | + * | address |----+ | CPER | + * +---------+ | | CPER | + * | ack0 |<---+ | .... | + * +---------+ +---------+ + */ + address_size = sizeof(struct AcpiGenericAddress) - + offsetof(struct AcpiGenericAddress, address); + ack_value_size = (offsetof(struct hardware_errors_buffer, gesb) - + offsetof(struct hardware_errors_buffer, ack_value)) / + GHES_ACPI_HEST_NOTIFY_RESERVED; + + error_status_address_offset = ghes_start + + sizeof(AcpiHardwareErrorSourceTable) + + offsetof(AcpiGenericHardwareErrorSourceV2, error_status_address) + + offsetof(struct AcpiGenericAddress, address); + + read_ack_register_offset = ghes_start + + sizeof(AcpiHardwareErrorSourceTable) + + offsetof(AcpiGenericHardwareErrorSourceV2, read_ack_register) + + offsetof(struct AcpiGenericAddress, address); + + acpi_data_push(hardware_error, + offsetof(struct hardware_errors_buffer, ack_value)); + for (i = 0; i < GHES_ACPI_HEST_NOTIFY_RESERVED; i++) + /* Initialize read ack value */ + build_append_int_noprefix((void *)hardware_error, 1, 8); + + /* Reserved the total size for ERRORS fw_cfg blob + */ + acpi_data_push(hardware_error, sizeof(struct hardware_errors_buffer)); + + /* Allocate guest memory for the Data fw_cfg blob */ + bios_linker_loader_alloc(linker, GHES_ERRORS_FW_CFG_FILE, hardware_error, + 1, false); + /* Reserve table header size */ + acpi_data_push(table_data, sizeof(AcpiTableHeader)); + + build_append_int_noprefix(table_data, GHES_ACPI_HEST_NOTIFY_RESERVED, 4); + + for (i = 0; i < GHES_ACPI_HEST_NOTIFY_RESERVED; i++) { + build_append_int_noprefix(table_data, + ACPI_HEST_SOURCE_GENERIC_ERROR_V2, 2); /* type */ + /* source id */ + build_append_int_noprefix(table_data, cpu_to_le16(i), 2); + /* related source id */ + build_append_int_noprefix(table_data, 0xffff, 2); + build_append_int_noprefix(table_data, 0, 1); /* flags */ + + /* Currently only enable SEA and SEI notification type to avoid the + * kernel warning, reserve the space for other notification error source + */ + if (i == ACPI_HEST_NOTIFY_SEA || i == ACPI_HEST_NOTIFY_SEI) { + build_append_int_noprefix(table_data, 1, 1); /* enabled */ + } else { + build_append_int_noprefix(table_data, 0, 1); /* enabled */ + } + + /* The number of error status block per generic hardware error source */ + build_append_int_noprefix(table_data, 1, 4); + /* Max sections per record */ + build_append_int_noprefix(table_data, 1, 4); + /* Max raw data length */ + build_append_int_noprefix(table_data, GHES_MAX_RAW_DATA_LENGTH, 4); + + /* Build error Status Address*/ + build_address(table_data, linker, error_status_address_offset + i * + sizeof(AcpiGenericHardwareErrorSourceV2), i * address_size, + AML_SYSTEM_MEMORY, 0x40, 0, 4 /* QWord access */); + + /* Hardware error notification structure */ + build_append_int_noprefix(table_data, i, 1); /* type */ + /* length */ + build_append_int_noprefix(table_data, sizeof(AcpiHestNotify), 1); + build_append_int_noprefix(table_data, 0, 26); + + /* Error Status Block Length */ + build_append_int_noprefix(table_data, + cpu_to_le32(GHES_MAX_RAW_DATA_LENGTH), 4); + + /* Build read ack register */ + build_address(table_data, linker, read_ack_register_offset + i * + sizeof(AcpiGenericHardwareErrorSourceV2), + offsetof(struct hardware_errors_buffer, ack_register) + + i * address_size, AML_SYSTEM_MEMORY, 0x40, 0, + 4 /* QWord access */); + + /* Read ack preserve */ + build_append_int_noprefix(table_data, cpu_to_le64(0xfffffffe), 8); + + /* Read ack write */ + build_append_int_noprefix(table_data, cpu_to_le64(0x1), 8); + } + + for (i = 0; i < GHES_ACPI_HEST_NOTIFY_RESERVED; i++) { + /* Patch address of generic error status block into + * the address register so OSPM can retrieve and read it. + */ + bios_linker_loader_add_pointer(linker, + GHES_ERRORS_FW_CFG_FILE, address_size * i, address_size, + GHES_ERRORS_FW_CFG_FILE, + offsetof(struct hardware_errors_buffer, gesb) + + i * GHES_MAX_RAW_DATA_LENGTH); + + /* Patch address of read ack into the read ack register so + * OSPM can retrieve and read it. + */ + bios_linker_loader_add_pointer(linker, + GHES_ERRORS_FW_CFG_FILE, + offsetof(struct hardware_errors_buffer, ack_register) + + address_size * i, address_size, GHES_ERRORS_FW_CFG_FILE, + offsetof(struct hardware_errors_buffer, ack_value) + i * ack_value_size); + } + + /* Patch address of ERRORS fw_cfg blob into the ADDR fw_cfg blob + * so QEMU can write the ERRORS there. The address is expected to be + * < 4GB, but write 64 bits anyway. + */ + bios_linker_loader_write_pointer(linker, GHES_DATA_ADDR_FW_CFG_FILE, + 0, address_size, GHES_ERRORS_FW_CFG_FILE, + offsetof(struct hardware_errors_buffer, gesb)); + + build_header(linker, table_data, + (void *)(table_data->data + ghes_start), "HEST", + table_data->len - ghes_start, 1, NULL, "GHES"); +} + +static GhesState ges; +void ghes_add_fw_cfg(FWCfgState *s, GArray *hardware_error) +{ + + size_t request_block_size = sizeof(uint64_t) + GHES_MAX_RAW_DATA_LENGTH; + size_t size = GHES_ACPI_HEST_NOTIFY_RESERVED * request_block_size; + + /* Create a read-only fw_cfg file for GHES */ + fw_cfg_add_file(s, GHES_ERRORS_FW_CFG_FILE, hardware_error->data, + size); + /* Create a read-write fw_cfg file for Address */ + fw_cfg_add_file_callback(s, GHES_DATA_ADDR_FW_CFG_FILE, NULL, NULL, + &ges.ghes_addr_le, sizeof(ges.ghes_addr_le), false); +} + +bool ghes_update_guest(uint32_t notify, uint64_t physical_address) +{ + uint64_t error_block_addr; + uint64_t ack_addr, ack_value = 0; + int loop = 0, ack_value_size; + bool ret = GHES_CPER_FAIL; + + ack_value_size = (offsetof(struct hardware_errors_buffer, gesb) - + offsetof(struct hardware_errors_buffer, ack_value)) / + GHES_ACPI_HEST_NOTIFY_RESERVED; +retry: + if (physical_address && notify < GHES_ACPI_HEST_NOTIFY_RESERVED) { + error_block_addr = ges.ghes_addr_le + notify * GHES_MAX_RAW_DATA_LENGTH; + error_block_addr = le32_to_cpu(error_block_addr); + + ack_addr = ges.ghes_addr_le - + (GHES_ACPI_HEST_NOTIFY_RESERVED - notify) * ack_value_size; + cpu_physical_memory_read(ack_addr, &ack_value, ack_value_size); + if (!ack_value) { + if (loop < 3) { + usleep(100 * 1000); + loop++; + goto retry; + } else { + error_report("Last time OSPM does not acknowledge the error," + " record CPER failed this time, set the ack value to" + " avoid blocking next time CPER record! exit"); + ack_value = 1; + cpu_physical_memory_write(ack_addr, &ack_value, ack_value_size); + return ret; + } + } else { + /* A zero value in ghes_addr means that BIOS has not yet written + * the address + */ + if (error_block_addr) { + ack_value = 0; + cpu_physical_memory_write(ack_addr, &ack_value, ack_value_size); + ret = ghes_record_cper(error_block_addr, physical_address); + } + } + } + + return ret; +} diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c index 0835e59..5c97016 100644 --- a/hw/arm/virt-acpi-build.c +++ b/hw/arm/virt-acpi-build.c @@ -45,6 +45,7 @@ #include "hw/arm/virt.h" #include "sysemu/numa.h" #include "kvm_arm.h" +#include "hw/acpi/hest_ghes.h" #define ARM_SPI_BASE 32 #define ACPI_POWER_BUTTON_DEVICE "PWRB" @@ -778,6 +779,9 @@ void virt_acpi_build(VirtMachineState *vms, AcpiBuildTables *tables) acpi_add_table(table_offsets, tables_blob); build_spcr(tables_blob, tables->linker, vms); + acpi_add_table(table_offsets, tables_blob); + ghes_build_acpi(tables_blob, tables->hardware_errors, tables->linker); + if (nb_numa_nodes > 0) { acpi_add_table(table_offsets, tables_blob); build_srat(tables_blob, tables->linker, vms); @@ -890,6 +894,8 @@ void virt_acpi_setup(VirtMachineState *vms) fw_cfg_add_file(vms->fw_cfg, ACPI_BUILD_TPMLOG_FILE, tables.tcpalog->data, acpi_data_len(tables.tcpalog)); + ghes_add_fw_cfg(vms->fw_cfg, tables.hardware_errors); + build_state->rsdp_mr = acpi_add_rom_blob(build_state, tables.rsdp, ACPI_BUILD_RSDP_FILE, 0); diff --git a/include/hw/acpi/aml-build.h b/include/hw/acpi/aml-build.h index 00c21f1..c1d15b3 100644 --- a/include/hw/acpi/aml-build.h +++ b/include/hw/acpi/aml-build.h @@ -211,6 +211,7 @@ struct AcpiBuildTables { GArray *rsdp; GArray *tcpalog; GArray *vmgenid; + GArray *hardware_errors; BIOSLinker *linker; } AcpiBuildTables; diff --git a/include/hw/acpi/hest_ghes.h b/include/hw/acpi/hest_ghes.h new file mode 100644 index 0000000..0772756 --- /dev/null +++ b/include/hw/acpi/hest_ghes.h @@ -0,0 +1,47 @@ +/* + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Authors: + * Dongjiu Geng + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#ifndef ACPI_GHES_H +#define ACPI_GHES_H + +#include "hw/acpi/bios-linker-loader.h" + +#define GHES_ERRORS_FW_CFG_FILE "etc/hardware_errors" +#define GHES_DATA_ADDR_FW_CFG_FILE "etc/hardware_errors_addr" + +#define GHES_GAS_ADDRESS_OFFSET 4 +#define GHES_ERROR_STATUS_ADDRESS_OFFSET 20 +#define GHES_NOTIFICATION_STRUCTURE 32 + +#define GHES_CPER_OK 1 +#define GHES_CPER_FAIL 0 + +#define GHES_ACPI_HEST_NOTIFY_RESERVED 11 +/* The max size in Bytes for one error block */ +#define GHES_MAX_RAW_DATA_LENGTH 0x1000 + + +typedef struct GhesState { + uint64_t ghes_addr_le; +} GhesState; + +void ghes_build_acpi(GArray *table_data, GArray *hardware_error, + BIOSLinker *linker); +void ghes_add_fw_cfg(FWCfgState *s, GArray *hardware_errors); +bool ghes_update_guest(uint32_t notify, uint64_t error_physical_addr); +#endif -- 1.8.3.1 From MAILER-DAEMON Fri Aug 04 01:31:51 2017 Received: from list by lists.gnu.org with archive (Exim 4.71) id 1ddVDC-0002Jc-Pl for mharc-qemu-arm@gnu.org; Fri, 04 Aug 2017 01:31:50 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:40918) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ddVD9-0002G5-IV for qemu-arm@nongnu.org; Fri, 04 Aug 2017 01:31:48 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ddVD8-0005gu-MR for qemu-arm@nongnu.org; Fri, 04 Aug 2017 01:31:47 -0400 Received: from szxga01-in.huawei.com ([45.249.212.187]:4481) by eggs.gnu.org with esmtps (TLS1.0:RSA_ARCFOUR_SHA1:16) (Exim 4.71) (envelope-from ) id 1ddVD2-0005W8-Ul; Fri, 04 Aug 2017 01:31:41 -0400 Received: from 172.30.72.53 (EHLO DGGEML402-HUB.china.huawei.com) ([172.30.72.53]) by dggrg01-dlp.huawei.com (MOS 4.4.6-GA FastPath queued) with ESMTP id ATU25596; Fri, 04 Aug 2017 13:31:36 +0800 (CST) Received: from linux.huawei.com (10.67.187.203) by DGGEML402-HUB.china.huawei.com (10.3.17.38) with Microsoft SMTP Server id 14.3.301.0; Fri, 4 Aug 2017 13:31:27 +0800 From: Dongjiu Geng To: , , , , , , CC: , , , Date: Fri, 4 Aug 2017 13:51:12 +0800 Message-ID: <1501825872-12555-4-git-send-email-gengdongjiu@huawei.com> X-Mailer: git-send-email 1.7.7 In-Reply-To: <1501825872-12555-1-git-send-email-gengdongjiu@huawei.com> References: <1501825872-12555-1-git-send-email-gengdongjiu@huawei.com> MIME-Version: 1.0 Content-Type: text/plain X-Originating-IP: [10.67.187.203] X-CFilter-Loop: Reflected X-Mirapoint-Virus-RAPID-Raw: score=unknown(0), refid=str=0001.0A090205.598406B9.000C, ss=1, re=0.000, recu=0.000, reip=0.000, cl=1, cld=1, fgs=0, ip=0.0.0.0, so=2014-11-16 11:51:01, dmn=2013-03-21 17:37:32 X-Mirapoint-Loop-Id: 928e1e74f6a7bf9a997219771967300e X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.4.x-2.6.x [generic] [fuzzy] X-Received-From: 45.249.212.187 Subject: [Qemu-arm] [PATCH v8 3/3] ACPI: build and enable APEI GHES in the Makefile and configuration X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 04 Aug 2017 05:31:48 -0000 Add CONFIG_ACPI_APEI configuration in the Makefile and enable it in the arm-softmmu.mak Signed-off-by: Dongjiu Geng --- thanks a lot Michael and Laszlo's review and comments: change since v5: (1) no change change since v4: (1) fix email threading in this series is incorrect issue change since v3: (1) change name to "CONFIG_ACPI_APEI" from CONFIG_ACPI_APEI_GENERATION --- default-configs/arm-softmmu.mak | 1 + hw/acpi/Makefile.objs | 1 + 2 files changed, 2 insertions(+) diff --git a/default-configs/arm-softmmu.mak b/default-configs/arm-softmmu.mak index 1e3bd2b..ee6f5fc 100644 --- a/default-configs/arm-softmmu.mak +++ b/default-configs/arm-softmmu.mak @@ -121,3 +121,4 @@ CONFIG_ACPI=y CONFIG_SMBIOS=y CONFIG_ASPEED_SOC=y CONFIG_GPIO_KEY=y +CONFIG_ACPI_APEI=y diff --git a/hw/acpi/Makefile.objs b/hw/acpi/Makefile.objs index 11c35bc..bafb148 100644 --- a/hw/acpi/Makefile.objs +++ b/hw/acpi/Makefile.objs @@ -6,6 +6,7 @@ common-obj-$(CONFIG_ACPI_MEMORY_HOTPLUG) += memory_hotplug.o common-obj-$(CONFIG_ACPI_CPU_HOTPLUG) += cpu.o common-obj-$(CONFIG_ACPI_NVDIMM) += nvdimm.o common-obj-$(CONFIG_ACPI_VMGENID) += vmgenid.o +common-obj-$(CONFIG_ACPI_APEI) += hest_ghes.o common-obj-$(call lnot,$(CONFIG_ACPI_X86)) += acpi-stub.o common-obj-y += acpi_interface.o -- 1.8.3.1 From MAILER-DAEMON Fri Aug 04 01:31:53 2017 Received: from list by lists.gnu.org with archive (Exim 4.71) id 1ddVDF-0002Lw-4Q for mharc-qemu-arm@gnu.org; Fri, 04 Aug 2017 01:31:53 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:40967) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ddVDB-0002Hy-Dp for qemu-arm@nongnu.org; Fri, 04 Aug 2017 01:31:51 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ddVD9-0005hx-KO for qemu-arm@nongnu.org; Fri, 04 Aug 2017 01:31:49 -0400 Received: from szxga01-in.huawei.com ([45.249.212.187]:4480) by eggs.gnu.org with esmtps (TLS1.0:RSA_ARCFOUR_SHA1:16) (Exim 4.71) (envelope-from ) id 1ddVD3-0005W9-06; Fri, 04 Aug 2017 01:31:42 -0400 Received: from 172.30.72.53 (EHLO DGGEML402-HUB.china.huawei.com) ([172.30.72.53]) by dggrg01-dlp.huawei.com (MOS 4.4.6-GA FastPath queued) with ESMTP id ATU25597; Fri, 04 Aug 2017 13:31:36 +0800 (CST) Received: from linux.huawei.com (10.67.187.203) by DGGEML402-HUB.china.huawei.com (10.3.17.38) with Microsoft SMTP Server id 14.3.301.0; Fri, 4 Aug 2017 13:31:26 +0800 From: Dongjiu Geng To: , , , , , , CC: , , , Date: Fri, 4 Aug 2017 13:51:10 +0800 Message-ID: <1501825872-12555-2-git-send-email-gengdongjiu@huawei.com> X-Mailer: git-send-email 1.7.7 In-Reply-To: <1501825872-12555-1-git-send-email-gengdongjiu@huawei.com> References: <1501825872-12555-1-git-send-email-gengdongjiu@huawei.com> MIME-Version: 1.0 Content-Type: text/plain X-Originating-IP: [10.67.187.203] X-CFilter-Loop: Reflected X-Mirapoint-Virus-RAPID-Raw: score=unknown(0), refid=str=0001.0A090206.598406B9.0024, ss=1, re=0.000, recu=0.000, reip=0.000, cl=1, cld=1, fgs=0, ip=0.0.0.0, so=2014-11-16 11:51:01, dmn=2013-03-21 17:37:32 X-Mirapoint-Loop-Id: e67e76661654031dc94ffce30950f93f X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.4.x-2.6.x [generic] [fuzzy] X-Received-From: 45.249.212.187 Subject: [Qemu-arm] [PATCH v8 1/3] ACPI: add APEI/HEST/CPER structures and macros X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 04 Aug 2017 05:31:51 -0000 (1) Add related APEI/HEST table structures and macros, these definition refer to ACPI 6.1 and UEFI 2.6 spec. (2) Add generic error status block and CPER memory section definition, user space only handle memory section errors. Signed-off-by: Dongjiu Geng --- thanks Michael and Laszlo's review: change since v5: (1) update the commit message title (2) remove UUID_BE and UEFI_CPER_SEC_PLATFORM_MEM macros (3) remove including "qemu/uuid.h" file in this patch (4) remove including "hest_ghes.h" file in this patch (5) drop "this is" from the comment of structures and macros (6) replace the "QemuUUID section_type_le" to "uint8_t section_type_le[16]" chnage since v4: (1) fix email threading in this series is incorrect issue change since v3: (1) separate the original one patch into three patches: one is new ACPI structures and macros, another is C source file to generate ACPI HEST table and dynamically record CPER ,final patch is the change about Makefile and configuration (2) add comments about where the ACPI structures and macros come from, for example, they come from the UEFI Spec 2.6, "xxxxxxxxxxxx"; ACPI 6.1 spec, "xxxxxxxxxxxxxx". (3) correct the macros name, for emaple, prefix some macro names with "UEFI_". (4) remove the uuid_le struct and use the QemuUUID in the include/qemu/uuid.h" (5) remove the duplicate ACPI address space, because it already defined in the "include/hw/acpi/aml-build.h" (6) remove the acpi_generic_address structure because same definition exists in the AcpiGenericAddress. (7) rename the struct acpi_hest_notify to AcpiHestNotifyType (8) rename the struct acpi_hest_types to AcpiHestSourceType (9) rename enum constants AcpiHestSourceType to ACPI_HEST_SOURCE_xxx from ACPI_HEST_TYPE_xxx (10) remove the NOT_USED{3,4,5} enum constants in the AcpiHestSourceType. (11) add missed QEMU_PACKED for the struct definition. (12) remove the defnition of AcpiGenericErrorData, and rename the AcpiGenericErrorDataV300 to AcpiGenericErrorData. (13) use the QemuUUID type for the "section_type" field AcpiGenericErrorData, and rename it to section_type_le. (14) moving type AcpiGenericErrorSeverity above AcpiGenericErrorData and AcpiGenericErrorDataV300, and remarking on the "error_severity" fields that they take their values from AcpiGenericErrorSeverity (15) remove the wrongly call to BERT(Boot Error Record Table) (16) add comments for the struction member, for example, pint out that the block_status member in the AcpiGenericErrorStatus is a bitmask composed of ACPI_GEBS_xxx macros (17) remove the hardware error source notification type list, and rename the MAX_ERROR_SOURCE_COUNT_V6 to ACPI_HEST_NOTIFY_RESERVED. (18) remove the physical_addr member of GhesErrorState (19) change the "uint64_t ghes_addr_le[8]" in GhesErrorState to uint64_t ghes_addr_le (20) change the second parameter to "error_physical_addr" in the ghes_update_guest API statement --- include/hw/acpi/acpi-defs.h | 193 ++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 193 insertions(+) diff --git a/include/hw/acpi/acpi-defs.h b/include/hw/acpi/acpi-defs.h index 4cc3630..ff9525e 100644 --- a/include/hw/acpi/acpi-defs.h +++ b/include/hw/acpi/acpi-defs.h @@ -295,6 +295,44 @@ typedef struct AcpiMultipleApicTable AcpiMultipleApicTable; #define ACPI_APIC_GENERIC_TRANSLATOR 15 #define ACPI_APIC_RESERVED 16 /* 16 and greater are reserved */ +/* UEFI Spec 2.6, "N.2.5 Memory Error Section */ +#define UEFI_CPER_MEM_VALID_ERROR_STATUS 0x0001 +#define UEFI_CPER_MEM_VALID_PA 0x0002 +#define UEFI_CPER_MEM_VALID_PA_MASK 0x0004 +#define UEFI_CPER_MEM_VALID_NODE 0x0008 +#define UEFI_CPER_MEM_VALID_CARD 0x0010 +#define UEFI_CPER_MEM_VALID_MODULE 0x0020 +#define UEFI_CPER_MEM_VALID_BANK 0x0040 +#define UEFI_CPER_MEM_VALID_DEVICE 0x0080 +#define UEFI_CPER_MEM_VALID_ROW 0x0100 +#define UEFI_CPER_MEM_VALID_COLUMN 0x0200 +#define UEFI_CPER_MEM_VALID_BIT_POSITION 0x0400 +#define UEFI_CPER_MEM_VALID_REQUESTOR 0x0800 +#define UEFI_CPER_MEM_VALID_RESPONDER 0x1000 +#define UEFI_CPER_MEM_VALID_TARGET 0x2000 +#define UEFI_CPER_MEM_VALID_ERROR_TYPE 0x4000 +#define UEFI_CPER_MEM_VALID_RANK_NUMBER 0x8000 +#define UEFI_CPER_MEM_VALID_CARD_HANDLE 0x10000 +#define UEFI_CPER_MEM_VALID_MODULE_HANDLE 0x20000 +#define UEFI_CPER_MEM_ERROR_TYPE_MULTI_ECC 3 + +/* From the ACPI 6.1 spec, "18.3.2.9 Hardware Error Notification" */ + +enum AcpiHestNotifyType { + ACPI_HEST_NOTIFY_POLLED = 0, + ACPI_HEST_NOTIFY_EXTERNAL = 1, + ACPI_HEST_NOTIFY_LOCAL = 2, + ACPI_HEST_NOTIFY_SCI = 3, + ACPI_HEST_NOTIFY_NMI = 4, + ACPI_HEST_NOTIFY_CMCI = 5, /* ACPI 5.0 */ + ACPI_HEST_NOTIFY_MCE = 6, /* ACPI 5.0 */ + ACPI_HEST_NOTIFY_GPIO = 7, /* ACPI 6.0 */ + ACPI_HEST_NOTIFY_SEA = 8, /* ACPI 6.1 */ + ACPI_HEST_NOTIFY_SEI = 9, /* ACPI 6.1 */ + ACPI_HEST_NOTIFY_GSIV = 10, /* ACPI 6.1 */ + ACPI_HEST_NOTIFY_RESERVED = 11 /* 11 and greater are reserved */ +}; + /* * MADT sub-structures (Follow MULTIPLE_APIC_DESCRIPTION_TABLE) */ @@ -475,6 +513,161 @@ struct AcpiSystemResourceAffinityTable } QEMU_PACKED; typedef struct AcpiSystemResourceAffinityTable AcpiSystemResourceAffinityTable; +/* Hardware Error Notification, from the ACPI 6.1 + * spec, "18.3.2.9 Hardware Error Notification" + */ +struct AcpiHestNotify { + uint8_t type; + uint8_t length; + uint16_t config_write_enable; + uint32_t poll_interval; + uint32_t vector; + uint32_t polling_threshold_value; + uint32_t polling_threshold_window; + uint32_t error_threshold_value; + uint32_t error_threshold_window; +} QEMU_PACKED; +typedef struct AcpiHestNotify AcpiHestNotify; + +/* From ACPI 6.1, sections "18.3.2.1 IA-32 Architecture Machine + * Check Exception" through "18.3.2.8 Generic Hardware Error Source version 2". + */ +enum AcpiHestSourceType { + ACPI_HEST_SOURCE_IA32_CHECK = 0, + ACPI_HEST_SOURCE_IA32_CORRECTED_CHECK = 1, + ACPI_HEST_SOURCE_IA32_NMI = 2, + ACPI_HEST_SOURCE_AER_ROOT_PORT = 6, + ACPI_HEST_SOURCE_AER_ENDPOINT = 7, + ACPI_HEST_SOURCE_AER_BRIDGE = 8, + ACPI_HEST_SOURCE_GENERIC_ERROR = 9, + ACPI_HEST_SOURCE_GENERIC_ERROR_V2 = 10, + ACPI_HEST_SOURCE_RESERVED = 11 /* 11 and greater are reserved */ +}; + +/* Block status bitmasks from ACPI 6.1, "18.3.2.7.1 Generic Error Data" */ +#define ACPI_GEBS_UNCORRECTABLE (1) +#define ACPI_GEBS_CORRECTABLE (1 << 1) +#define ACPI_GEBS_MULTIPLE_UNCORRECTABLE (1 << 2) +#define ACPI_GEBS_MULTIPLE_CORRECTABLE (1 << 3) +/* 10 bits, error data entry count */ +#define ACPI_GEBS_ERROR_ENTRY_COUNT (0x3FF << 4) + +/* Generic Hardware Error Source Structure, refer to ACPI 6.1 + * "18.3.2.7 Generic Hardware Error Source". in this struct the + * "type" field has to be ACPI_HEST_SOURCE_GENERIC_ERROR + */ + +struct AcpiGenericHardwareErrorSource { + uint16_t type; + uint16_t source_id; + uint16_t related_source_id; + uint8_t flags; + uint8_t enabled; + uint32_t number_of_records; + uint32_t max_sections_per_record; + uint32_t max_raw_data_length; + struct AcpiGenericAddress error_status_address; + struct AcpiHestNotify notify; + uint32_t error_status_block_length; +} QEMU_PACKED; +typedef struct AcpiGenericHardwareErrorSource AcpiGenericHardwareErrorSource; + +/* Generic Hardware Error Source, version 2, ACPI 6.1, "18.3.2.8 Generic + * Hardware Error Source version 2", in this struct the "type" field has to + * be ACPI_HEST_SOURCE_GENERIC_ERROR_V2 + */ +struct AcpiGenericHardwareErrorSourceV2 { + uint16_t type; + uint16_t source_id; + uint16_t related_source_id; + uint8_t flags; + uint8_t enabled; + uint32_t number_of_records; + uint32_t max_sections_per_record; + uint32_t max_raw_data_length; + struct AcpiGenericAddress error_status_address; + struct AcpiHestNotify notify; + uint32_t error_status_block_length; + struct AcpiGenericAddress read_ack_register; + uint64_t read_ack_preserve; + uint64_t read_ack_write; +} QEMU_PACKED; +typedef struct AcpiGenericHardwareErrorSourceV2 + AcpiGenericHardwareErrorSourceV2; + +/* Generic Error Status block, from ACPI 6.1, + * "18.3.2.7.1 Generic Error Data" + */ +struct AcpiGenericErrorStatus { + /* It is a bitmask composed of ACPI_GEBS_xxx macros */ + uint32_t block_status; + uint32_t raw_data_offset; + uint32_t raw_data_length; + uint32_t data_length; + uint32_t error_severity; +} QEMU_PACKED; +typedef struct AcpiGenericErrorStatus AcpiGenericErrorStatus; + +enum AcpiGenericErrorSeverity { + ACPI_CPER_SEV_RECOVERABLE, + ACPI_CPER_SEV_FATAL, + ACPI_CPER_SEV_CORRECTED, + ACPI_CPER_SEV_NONE, +}; + +/* Generic Error Data entry, revision number is 0x0300, + * ACPI 6.1, "18.3.2.7.1 Generic Error Data" + */ +struct AcpiGenericErrorData { + uint8_t section_type_le[16]; + /* The "error_severity" fields that they take their + * values from AcpiGenericErrorSeverity + */ + uint32_t error_severity; + uint16_t revision; + uint8_t validation_bits; + uint8_t flags; + uint32_t error_data_length; + uint8_t fru_id[16]; + uint8_t fru_text[20]; + uint64_t time_stamp; +} QEMU_PACKED; +typedef struct AcpiGenericErrorData AcpiGenericErrorData; + +/* From UEFI 2.6, "N.2.5 Memory Error Section" */ +struct UefiCperSecMemErr { + uint64_t validation_bits; + uint64_t error_status; + uint64_t physical_addr; + uint64_t physical_addr_mask; + uint16_t node; + uint16_t card; + uint16_t module; + uint16_t bank; + uint16_t device; + uint16_t row; + uint16_t column; + uint16_t bit_pos; + uint64_t requestor_id; + uint64_t responder_id; + uint64_t target_id; + uint8_t error_type; + uint8_t reserved; + uint16_t rank; + uint16_t mem_array_handle; /* card handle in UEFI 2.4 */ + uint16_t mem_dev_handle; /* module handle in UEFI 2.4 */ +} QEMU_PACKED; +typedef struct UefiCperSecMemErr UefiCperSecMemErr; + +/* + * HEST Description Table + */ +struct AcpiHardwareErrorSourceTable { + ACPI_TABLE_HEADER_DEF /* ACPI common table header */ + uint32_t error_source_count; +} QEMU_PACKED; +typedef struct AcpiHardwareErrorSourceTable AcpiHardwareErrorSourceTable; + #define ACPI_SRAT_PROCESSOR_APIC 0 #define ACPI_SRAT_MEMORY 1 #define ACPI_SRAT_PROCESSOR_x2APIC 2 -- 1.8.3.1 From MAILER-DAEMON Fri Aug 04 01:31:54 2017 Received: from list by lists.gnu.org with archive (Exim 4.71) id 1ddVDG-0002Mx-1q for mharc-qemu-arm@gnu.org; Fri, 04 Aug 2017 01:31:54 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:40984) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ddVDB-0002IU-QT for qemu-arm@nongnu.org; Fri, 04 Aug 2017 01:31:53 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ddVD9-0005iL-U6 for qemu-arm@nongnu.org; Fri, 04 Aug 2017 01:31:49 -0400 Received: from szxga01-in.huawei.com ([45.249.212.187]:4482) by eggs.gnu.org with esmtps (TLS1.0:RSA_ARCFOUR_SHA1:16) (Exim 4.71) (envelope-from ) id 1ddVD2-0005W7-U6; Fri, 04 Aug 2017 01:31:42 -0400 Received: from 172.30.72.53 (EHLO DGGEML402-HUB.china.huawei.com) ([172.30.72.53]) by dggrg01-dlp.huawei.com (MOS 4.4.6-GA FastPath queued) with ESMTP id ATU25595; Fri, 04 Aug 2017 13:31:35 +0800 (CST) Received: from linux.huawei.com (10.67.187.203) by DGGEML402-HUB.china.huawei.com (10.3.17.38) with Microsoft SMTP Server id 14.3.301.0; Fri, 4 Aug 2017 13:31:26 +0800 From: Dongjiu Geng To: , , , , , , CC: , , , Date: Fri, 4 Aug 2017 13:51:09 +0800 Message-ID: <1501825872-12555-1-git-send-email-gengdongjiu@huawei.com> X-Mailer: git-send-email 1.7.7 MIME-Version: 1.0 Content-Type: text/plain X-Originating-IP: [10.67.187.203] X-CFilter-Loop: Reflected X-Mirapoint-Virus-RAPID-Raw: score=unknown(0), refid=str=0001.0A020202.598406B9.002C, ss=1, re=0.000, recu=0.000, reip=0.000, cl=1, cld=1, fgs=0, ip=0.0.0.0, so=2014-11-16 11:51:01, dmn=2013-03-21 17:37:32 X-Mirapoint-Loop-Id: 6d80dab917e2dfb89b0c78a236eb6285 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.4.x-2.6.x [generic] [fuzzy] X-Received-From: 45.249.212.187 Subject: [Qemu-arm] [PATCH v8 0/3] Generate APEI GHES table and dynamically record CPER X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 04 Aug 2017 05:31:53 -0000 In the armv8 platform, the mainly hardware error source are ARMv8 SEA/SEI/GSIV. For the ARMv8 SEA/SEI, the KVM or host kernel will signal SIGBUS or use other interface to notify user space, such as Qemu. After Qemu gets the notification, it will record the CPER and inject the SEA/SEI to KVM. this series of patches will generate APEI table when guest OS boot up, and dynamically record CPER for the guest OS about the generic hardware errors, currently the userspace only handle the memory section hardware errors. Before Qemu record the CPER, it needs to check the ACK value written by the guest OS to avoid read-write race condition. Below is the APEI/GHESV2/CPER table layout, the max number of error soure is 11, which is classified by notification type, now only enable the SEA/SEI notification type error source. etc/acpi/tables etc/hardware_errors ==================== ========================================== + +--------------------------+ +------------------+ | | HEST | | address | +--------------+ | +--------------------------+ | registers | | Error Status | | | GHES0 | | +----------------+ | Data Block 0 | | +--------------------------+ +--------->| |status_address0 |------------->| +------------+ | | ................. | | | +----------------+ | | CPER | | | error_status_address-----+-+ +------->| |status_address1 |----------+ | | CPER | | | ................. | | | +----------------+ | | | .... | | | read_ack_register--------+-+ | | ............. | | | | CPER | | | read_ack_preserve | | | +------------------+ | | +-+------------+ | | read_ack_write | | | +----->| |status_address10|--------+ | | Error Status | + +--------------------------+ | | | | +----------------+ | | | Data Block 1 | | | GHES1 | +-+-+----->| |ack_address0 |--+ | +-->| +------------+ + +--------------------------+ | | | +----------------+ | | | | CPER | | | ................. | | | +--->| |ack_address1 |--+-+ | | | CPER | | | error_status_address-----+---+ | | | +----------------+ | | | | | .... | | | ................. | | | | | ............. | | | | | | CPER | | | read_ack_register--------+-----+-+ | +----------------+ | | | +-+------------+ | | read_ack_preserve | | +->| |ack_address10 |--+-+-+ | | |.......... | | | read_ack_write | | | | +----------------+ | | | | | +------------+ + +--------------------------| | | | | ack0 |<-+ | | | | Error Status | | | ............... | | | | +----------------+ | | | | Data Block 10| + +--------------------------+ | | | | ack1 |<---+ | +---->| +------------+ | | GHES10 | | | | +----------------+ | | | CPER | + +--------------------------+ | | | | .... | | | | CPER | | | ................. | | | | +--------------+ | | | | .... | | | error_status_address-----+-----+ | | | ack10 |<---- + | | CPER | | | ................. | | | +----------------+ +-+------------+ | | read_ack_register--------+---------+ | | read_ack_preserve | | | read_ack_write | + +--------------------------+ After injecting a SEA/SEI ghes error, the gueset OS kernel log will be shown as below: [ 142.911115] {1}[Hardware Error]: Hardware error from APEI Generic Hardware Error Source: 8 [ 142.913141] {1}[Hardware Error]: event severity: recoverable [ 142.914498] {1}[Hardware Error]: Error 0, type: recoverable [ 142.915851] {1}[Hardware Error]: section_type: memory error [ 142.917163] {1}[Hardware Error]: physical_address: 0x0000000000001111 [ 142.918792] {1}[Hardware Error]: error_type: 3, multi-bit ECC how to test: 1. In the guest OS, use this command to dump the APEI table: "iasl -p ./HEST -d /sys/firmware/acpi/tables/HEST" 2. And find the address for the generic error status block according to the notification type 3. then find the CPER record through the generic error status block. For example(notification type is SEA): (1) root@genericarmv8:~# iasl -p ./HEST -d /sys/firmware/acpi/tables/HEST (2) root@genericarmv8:~# cat HEST.dsl /* * Intel ACPI Component Architecture * AML/ASL+ Disassembler version 20170728 (64-bit version) * Copyright (c) 2000 - 2017 Intel Corporation * * Disassembly of /sys/firmware/acpi/tables/HEST, Mon Sep 5 07:59:17 2016 * * ACPI Data Table [HEST] * * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue */ .................................................................................. [308h 0776 2] Subtable Type : 000A [Generic Hardware Error Source V2] [30Ah 0778 2] Source Id : 0008 [30Ch 0780 2] Related Source Id : FFFF [30Eh 0782 1] Reserved : 00 [30Fh 0783 1] Enabled : 01 [310h 0784 4] Records To Preallocate : 00000001 [314h 0788 4] Max Sections Per Record : 00000001 [318h 0792 4] Max Raw Data Length : 00001000 [31Ch 0796 12] Error Status Address : [Generic Address Structure] [31Ch 0796 1] Space ID : 00 [SystemMemory] [31Dh 0797 1] Bit Width : 40 [31Eh 0798 1] Bit Offset : 00 [31Fh 0799 1] Encoded Access Width : 04 [QWord Access:64] [320h 0800 8] Address : 00000000785D0040 [328h 0808 28] Notify : [Hardware Error Notification Structure] [328h 0808 1] Notify Type : 08 [SEA] [329h 0809 1] Notify Length : 1C [32Ah 0810 2] Configuration Write Enable : 0000 [32Ch 0812 4] PollInterval : 00000000 [330h 0816 4] Vector : 00000000 [334h 0820 4] Polling Threshold Value : 00000000 [338h 0824 4] Polling Threshold Window : 00000000 [33Ch 0828 4] Error Threshold Value : 00000000 [340h 0832 4] Error Threshold Window : 00000000 [344h 0836 4] Error Status Block Length : 00001000 [348h 0840 12] Read Ack Register : [Generic Address Structure] [348h 0840 1] Space ID : 00 [SystemMemory] [349h 0841 1] Bit Width : 40 [34Ah 0842 1] Bit Offset : 00 [34Bh 0843 1] Encoded Access Width : 04 [QWord Access:64] [34Ch 0844 8] Address : 00000000785D0098 [354h 0852 8] Read Ack Preserve : 00000000FFFFFFFE [35Ch 0860 8] Read Ack Write : 0000000000000001 [364h 0868 2] Subtable Type : 000A [Generic Hardware Error Source V2] [366h 0870 2] Source Id : 0009 [368h 0872 2] Related Source Id : FFFF [36Ah 0874 1] Reserved : 00 [36Bh 0875 1] Enabled : 01 [36Ch 0876 4] Records To Preallocate : 00000001 [370h 0880 4] Max Sections Per Record : 00000001 [374h 0884 4] Max Raw Data Length : 00001000 [378h 0888 12] Error Status Address : [Generic Address Structure] [378h 0888 1] Space ID : 00 [SystemMemory] [379h 0889 1] Bit Width : 40 [37Ah 0890 1] Bit Offset : 00 [37Bh 0891 1] Encoded Access Width : 04 [QWord Access:64] [37Ch 0892 8] Address : 00000000785D0048 [384h 0900 28] Notify : [Hardware Error Notification Structure] [384h 0900 1] Notify Type : 09 [SEI] [385h 0901 1] Notify Length : 1C [386h 0902 2] Configuration Write Enable : 0000 [388h 0904 4] PollInterval : 00000000 [38Ch 0908 4] Vector : 00000000 [390h 0912 4] Polling Threshold Value : 00000000 [394h 0916 4] Polling Threshold Window : 00000000 [398h 0920 4] Error Threshold Value : 00000000 [39Ch 0924 4] Error Threshold Window : 00000000 [3A0h 0928 4] Error Status Block Length : 00001000 [3A4h 0932 12] Read Ack Register : [Generic Address Structure] [3A4h 0932 1] Space ID : 00 [SystemMemory] [3A5h 0933 1] Bit Width : 40 [3A6h 0934 1] Bit Offset : 00 [3A7h 0935 1] Encoded Access Width : 04 [QWord Access:64] [3A8h 0936 8] Address : 00000000785D00A0 [3B0h 0944 8] Read Ack Preserve : 00000000FFFFFFFE [3B8h 0952 8] Read Ack Write : 000000000000000 ..................................................................................... (3) according to above table, the address that contains the physical address of a block of memory that holds the error status data for SEA notification error source is 0x00000000785D0040 (4) the address for SEA notification error source is 0x785d8108 (qemu) xp /1 0x00000000785D0040 00000000785d0040: 0x785d8108 (5) check the content of generic error status block and generic error data entry (qemu) xp /100x 0x785d8108 00000000785d8108: 0x00000000 0x00000000 0x00000000 0x00000098 00000000785d8118: 0x00000000 0xa5bc1114 0x4ede6f64 0x833e63b8 00000000785d8128: 0xb1837ced 0x00000000 0x00000300 0x00000050 00000000785d8138: 0x00000000 0x00000000 0x00000000 0x00000000 00000000785d8148: 0x00000000 0x00000000 0x00000000 0x00000000 00000000785d8158: 0x00000000 0x00000000 0x00000000 0x00004002 00000000785d8168: 0x00000000 0x00000000 0x00000000 0x00001111 00000000785d8178: 0x00000000 0x00000000 0x00000000 0x00000000 00000000785d8188: 0x00000000 0x00000000 0x00000000 0x00000000 00000000785d8198: 0x00000000 0x00000000 0x00000000 0x00000000 00000000785d81a8: 0x00000000 0x00000003 0x00000000 0x00000000 00000000785d81b8: 0x00000000 0x00000000 0x00000000 0x00000000 00000000785d81c8: 0x00000000 0x00000000 0x00000000 0x00000000 00000000785d81d8: 0x00000000 0x00000000 0x00000000 0x00000000 00000000785d81e8: 0x00000000 0x00000000 0x00000000 0x00000000 00000000785d81f8: 0x00000000 0x00000000 0x00000000 0x00000000 00000000785d8208: 0x00000000 0x00000000 0x00000000 0x00000000 00000000785d8218: 0x00000000 0x00000000 0x00000000 0x00000000 00000000785d8228: 0x00000000 0x00000000 0x00000000 0x00000000 00000000785d8238: 0x00000000 0x00000000 0x00000000 0x00000000 00000000785d8248: 0x00000000 0x00000000 0x00000000 0x00000000 00000000785d8258: 0x00000000 0x00000000 0x00000000 0x00000000 00000000785d8268: 0x00000000 0x00000000 0x00000000 0x00000000 00000000785d8278: 0x00000000 0x00000000 0x00000000 0x00000000 00000000785d8288: 0x00000000 0x00000000 0x00000000 0x00000000 (6) check the OSPM's ACK value(for example SEA) /* The address of ACK value */ (qemu) xp /1 0x00000000785D0098 00000000785d0098: 0x785d00f0 /* Before OSPM acknowledges the error */ (qemu) xp /1 0x785d00f0 00000000785d00f0: 0x00000000 /* After OSPM acknowledges the error */ (qemu) xp /1 0x785d00f0 00000000785d00f0: 0x00000001 Dongjiu Geng (3): ACPI: add APEI/HEST/CPER structures and macros ACPI: Add APEI GHES Table Generation support ACPI: build and enable APEI GHES in the Makefile and configuration default-configs/arm-softmmu.mak | 1 + hw/acpi/Makefile.objs | 1 + hw/acpi/aml-build.c | 2 + hw/acpi/hest_ghes.c | 370 ++++++++++++++++++++++++++++++++++++++++ hw/arm/virt-acpi-build.c | 6 + include/hw/acpi/acpi-defs.h | 193 +++++++++++++++++++++ include/hw/acpi/aml-build.h | 1 + include/hw/acpi/hest_ghes.h | 47 +++++ 8 files changed, 621 insertions(+) create mode 100644 hw/acpi/hest_ghes.c create mode 100644 include/hw/acpi/hest_ghes.h -- 1.8.3.1 From MAILER-DAEMON Fri Aug 04 01:32:13 2017 Received: from list by lists.gnu.org with archive (Exim 4.71) id 1ddVDY-0002cl-Ml for mharc-qemu-arm@gnu.org; Fri, 04 Aug 2017 01:32:12 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:41248) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ddVDK-0002R2-FB for qemu-arm@nongnu.org; Fri, 04 Aug 2017 01:32:10 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ddVDE-0005pC-CU for qemu-arm@nongnu.org; Fri, 04 Aug 2017 01:31:58 -0400 Received: from szxga01-in.huawei.com ([45.249.212.187]:4483) by eggs.gnu.org with esmtps (TLS1.0:RSA_ARCFOUR_SHA1:16) (Exim 4.71) (envelope-from ) id 1ddVD5-0005YQ-1b; Fri, 04 Aug 2017 01:31:44 -0400 Received: from 172.30.72.53 (EHLO DGGEML402-HUB.china.huawei.com) ([172.30.72.53]) by dggrg01-dlp.huawei.com (MOS 4.4.6-GA FastPath queued) with ESMTP id ATU25592; Fri, 04 Aug 2017 13:31:35 +0800 (CST) Received: from linux.huawei.com (10.67.187.203) by DGGEML402-HUB.china.huawei.com (10.3.17.38) with Microsoft SMTP Server id 14.3.301.0; Fri, 4 Aug 2017 13:31:26 +0800 From: Dongjiu Geng To: , , , , , , CC: , , , Date: Fri, 4 Aug 2017 13:51:11 +0800 Message-ID: <1501825872-12555-3-git-send-email-gengdongjiu@huawei.com> X-Mailer: git-send-email 1.7.7 In-Reply-To: <1501825872-12555-1-git-send-email-gengdongjiu@huawei.com> References: <1501825872-12555-1-git-send-email-gengdongjiu@huawei.com> MIME-Version: 1.0 Content-Type: text/plain X-Originating-IP: [10.67.187.203] X-CFilter-Loop: Reflected X-Mirapoint-Virus-RAPID-Raw: score=unknown(0), refid=str=0001.0A020205.598406BB.00A7, ss=1, re=0.000, recu=0.000, reip=0.000, cl=1, cld=1, fgs=0, ip=0.0.0.0, so=2014-11-16 11:51:01, dmn=2013-03-21 17:37:32 X-Mirapoint-Loop-Id: ce5c4df6126617e040905d48bc238f67 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.4.x-2.6.x [generic] [fuzzy] X-Received-From: 45.249.212.187 Subject: [Qemu-arm] [PATCH v8 2/3] ACPI: Add APEI GHES Table Generation support X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 04 Aug 2017 05:32:11 -0000 This implements APEI GHES Table by passing the error CPER info to the guest via a fw_cfg_blob. After a CPER info is recorded, an SEA(Synchronous External Abort)/SEI(SError Interrupt) exception will be injected into the guest OS. Below is the table layout, the max number of error soure is 11, which is classified by notification type. etc/acpi/tables etc/hardware_errors ==================== ========================================== + +--------------------------+ +------------------+ | | HEST | | address | +--------------+ | +--------------------------+ | registers | | Error Status | | | GHES0 | | +----------------+ | Data Block 0 | | +--------------------------+ +--------->| |status_address0 |------------->| +------------+ | | ................. | | | +----------------+ | | CPER | | | error_status_address-----+-+ +------->| |status_address1 |----------+ | | CPER | | | ................. | | | +----------------+ | | | .... | | | read_ack_register--------+-+ | | ............. | | | | CPER | | | read_ack_preserve | | | +------------------+ | | +-+------------+ | | read_ack_write | | | +----->| |status_address10|--------+ | | Error Status | + +--------------------------+ | | | | +----------------+ | | | Data Block 1 | | | GHES1 | +-+-+----->| |ack_address0 |--+ | +-->| +------------+ + +--------------------------+ | | | +----------------+ | | | | CPER | | | ................. | | | +--->| |ack_address1 |--+-+ | | | CPER | | | error_status_address-----+---+ | | | +----------------+ | | | | | .... | | | ................. | | | | | ............. | | | | | | CPER | | | read_ack_register--------+-----+-+ | +----------------+ | | | +-+------------+ | | read_ack_preserve | | +->| |ack_address10 |--+-+-+ | | |.......... | | | read_ack_write | | | | +----------------+ | | | | | +------------+ + +--------------------------| | | | | ack0 |<-+ | | | | Error Status | | | ............... | | | | +----------------+ | | | | Data Block 10| + +--------------------------+ | | | | ack1 |<---+ | +---->| +------------+ | | GHES10 | | | | +----------------+ | | | CPER | + +--------------------------+ | | | | .... | | | | CPER | | | ................. | | | | +--------------+ | | | | .... | | | error_status_address-----+-----+ | | | ack10 |<---- + | | CPER | | | ................. | | | +----------------+ +-+------------+ | | read_ack_register--------+---------+ | | read_ack_preserve | | | read_ack_write | + +--------------------------+ For GHESv2 error source, the OSPM must acknowledges the error via Read Ack register. so user space must check the ack value to avoid read-write race condition. Signed-off-by: Dongjiu Geng --- thanks a lot Michael and Laszlo's review and comments: change since v6: (1) update the commit message change since v5: (1) move to GHESv2 error source from GHESv1, because we maily use the GHESv2 (2) add the GHESv2 error source layout in the comments (2) add the logic to read the ack value from OSPM to avoid read-write race condition (3) including header files "aml-build.h" and "hest_ghes.h" in this patch to make it reasonable (4) calculate the fw_cfg blob offsets that should be patched in more fine-grained steps, with multiple separate increments, using: - structure type names, - sizeof operators, - offsetof macros, - and possibly a separate comment for each offset increment. (5) remove page boundary refers to 4096 in the "bios_linker_loader_alloc" (6) using build_append_int_noprefix to avoid use pointer math, so that the code is easily readable (7) change memory section definition to array from QemuUUID (8) only enable SEA/SEI notification hardware error source to avoid guest OS ACPI driver probe warning change since v4: 1. fix email threading in this series is incorrect issue change since v3: 1. remove the unnecessary include for "hw/acpi/vmgenid.h" in hw/arm/virt-acpi-build.c 2. add conversion between LE and host-endian for the CPER record 3. handle the case that run out of the preallocated memory for the CPER record 4. change to use g_malloc0 instead of g_malloc 5. change block_reqr_size name to block_rer_size 6. change QEMU coding style, that is, the operator is at the end of the line. 7. drop the ERROR_STATUS_ADDRESS_OFFSET and GAS_ADDRESS_OFFSET macros (from the header file as well), and use the offsetof to replace it. 8. remove the init_aml_allocator() / free_aml_allocator(), calculate the needed size, and push that many bytes directly to "table_data". 9. take an "OVMF header probe suppressor" into account 10.corrct HEST and CPER value assigment, for example, correct the source_id for every error source, this identifier of source_id should be unique among all error sources; 11. create only one WRITE_POINTER command, for the base address of "etc/hardware_errors". This should be done outside of the loop.The base addresses of the individual error status data blocks should be calculated in ghes_update_guest(), based on the error source / notification type 12.correct the commit message lists error sources / notification types 0 through 10 (count=11 in total). 13.correct the size calculation for GHES_DATA_ADDR_FW_CFG_FILE 14.range-checked the value of "notify" before using it as an array subscript --- hw/acpi/aml-build.c | 2 + hw/acpi/hest_ghes.c | 368 ++++++++++++++++++++++++++++++++++++++++++++ hw/arm/virt-acpi-build.c | 6 + include/hw/acpi/aml-build.h | 1 + include/hw/acpi/hest_ghes.h | 47 ++++++ 5 files changed, 424 insertions(+) create mode 100644 hw/acpi/hest_ghes.c create mode 100644 include/hw/acpi/hest_ghes.h diff --git a/hw/acpi/aml-build.c b/hw/acpi/aml-build.c index c6f2032..802b98d 100644 --- a/hw/acpi/aml-build.c +++ b/hw/acpi/aml-build.c @@ -1560,6 +1560,7 @@ void acpi_build_tables_init(AcpiBuildTables *tables) tables->table_data = g_array_new(false, true /* clear */, 1); tables->tcpalog = g_array_new(false, true /* clear */, 1); tables->vmgenid = g_array_new(false, true /* clear */, 1); + tables->hardware_errors = g_array_new(false, true /* clear */, 1); tables->linker = bios_linker_loader_init(); } @@ -1570,6 +1571,7 @@ void acpi_build_tables_cleanup(AcpiBuildTables *tables, bool mfre) g_array_free(tables->table_data, true); g_array_free(tables->tcpalog, mfre); g_array_free(tables->vmgenid, mfre); + g_array_free(tables->hardware_errors, mfre); } /* Build rsdt table */ diff --git a/hw/acpi/hest_ghes.c b/hw/acpi/hest_ghes.c new file mode 100644 index 0000000..cc06662 --- /dev/null +++ b/hw/acpi/hest_ghes.c @@ -0,0 +1,368 @@ +/* + * APEI GHES table Generation + * + * Copyright (C) 2017 huawei. + * + * Author: Dongjiu Geng + * + * This work is licensed under the terms of the GNU GPL, version 2 or later. + * See the COPYING file in the top-level directory. + * + */ + +#include "qemu/osdep.h" +#include "qmp-commands.h" +#include "hw/acpi/acpi.h" +#include "hw/acpi/aml-build.h" +#include "hw/acpi/hest_ghes.h" +#include "hw/nvram/fw_cfg.h" +#include "sysemu/sysemu.h" +#include "qemu/error-report.h" + +/* The structure that stands for the layout + * GHES_ERRORS_FW_CFG_FILE fw_cfg blob + * + * etc/hardware_errors + * ========================================== + * +------------------+ + * | address | +--------------+ + * | registers | | Error Status | + * | +----------------+ | Data Block 0 | + * | |status_address0 |------------->| +------------+ + * | +----------------+ | | CPER | + * | |status_address1 |----------+ | | CPER | + * | +----------------+ | | | .... | + * | |............. | | | | CPER | + * | +----------------+ | | +------------+ + * | |status_address10|--------+ | | Error Status | + * | +----------------+ | | | Data Block 1 | + * | |ack_address0 |--+ | +-->| +------------+ + * | +----------------+ | | | | CPER | + * | |ack_address1 |--+-+ | | | CPER | + * | +----------------+ | | | | | .... | + * | | ............. | | | | | | CPER | + * | +----------------+ | | | +-+------------+ + * | |ack_address10 |--+-+-+ | | |.......... | + * | +----------------+ | | | | | +------------+ + * | | ack0 |<-+ | | | | Error Status | + * | +----------------+ | | | | Data Block10 | + * | | ack1 |<---+ | +---->| +------------+ + * | +----------------+ | | | CPER | + * | | .... | | | | CPER | + * | +--------------+ | | | | .... | + * | | ack10 |<---- + | | CPER | + * | +----------------+ +-+------------+ + */ +struct hardware_errors_buffer { + /* Generic Error Status Block register */ + uint64_t gesb_register[GHES_ACPI_HEST_NOTIFY_RESERVED]; + uint64_t ack_register[GHES_ACPI_HEST_NOTIFY_RESERVED]; + uint64_t ack_value[GHES_ACPI_HEST_NOTIFY_RESERVED]; + char gesb[GHES_MAX_RAW_DATA_LENGTH][GHES_ACPI_HEST_NOTIFY_RESERVED]; +}; + +static int ghes_record_cper(uint64_t error_block_address, + uint64_t error_physical_addr) +{ + AcpiGenericErrorStatus block; + AcpiGenericErrorData *gdata; + UefiCperSecMemErr *mem_err; + uint64_t current_block_length; + unsigned char *buffer; + /* memory section */ + char mem_section_id_le[] = {0x14, 0x11, 0xBC, 0xA5, 0x64, 0x6F, 0xDE, + 0x4E, 0xB8, 0x63, 0x3E, 0x83, 0xED, 0x7C, + 0x83, 0xB1}; + + cpu_physical_memory_read(error_block_address, &block, + sizeof(AcpiGenericErrorStatus)); + + /* Get the current generic error status block length */ + current_block_length = sizeof(AcpiGenericErrorStatus) + + le32_to_cpu(block.data_length); + + /* If the Generic Error Status Block is NULL, update + * the block header + */ + if (!block.block_status) { + block.block_status = ACPI_GEBS_UNCORRECTABLE; + block.error_severity = ACPI_CPER_SEV_RECOVERABLE; + } + + block.data_length += cpu_to_le32(sizeof(AcpiGenericErrorData)); + block.data_length += cpu_to_le32(sizeof(UefiCperSecMemErr)); + + /* check whether it runs out of the preallocated memory */ + if ((le32_to_cpu(block.data_length) + sizeof(AcpiGenericErrorStatus)) > + GHES_MAX_RAW_DATA_LENGTH) { + error_report("Record CPER out of boundary!!!"); + return GHES_CPER_FAIL; + } + + /* Write back the Generic Error Status Block to guest memory */ + cpu_physical_memory_write(error_block_address, &block, + sizeof(AcpiGenericErrorStatus)); + + /* Fill in Generic Error Data Entry */ + buffer = g_malloc0(sizeof(AcpiGenericErrorData) + + sizeof(UefiCperSecMemErr)); + + + memset(buffer, 0, sizeof(AcpiGenericErrorData) + sizeof(UefiCperSecMemErr)); + gdata = (AcpiGenericErrorData *)buffer; + + /* Memory section */ + memcpy(&(gdata->section_type_le), &mem_section_id_le, + sizeof(mem_section_id_le)); + + /* error severity is recoverable */ + gdata->error_severity = ACPI_CPER_SEV_RECOVERABLE; + gdata->revision = 0x300; /* the revision number is 0x300 */ + gdata->error_data_length = cpu_to_le32(sizeof(UefiCperSecMemErr)); + + mem_err = (UefiCperSecMemErr *) (gdata + 1); + + /* User space only handle the memory section CPER */ + + /* Hard code to Multi-bit ECC error */ + mem_err->validation_bits |= cpu_to_le32(UEFI_CPER_MEM_VALID_ERROR_TYPE); + mem_err->error_type = cpu_to_le32(UEFI_CPER_MEM_ERROR_TYPE_MULTI_ECC); + + /* Record the physical address at which the memory error occurred */ + mem_err->validation_bits |= cpu_to_le32(UEFI_CPER_MEM_VALID_PA); + mem_err->physical_addr = cpu_to_le32(error_physical_addr); + + /* Write back the Generic Error Data Entry to guest memory */ + cpu_physical_memory_write(error_block_address + current_block_length, + buffer, sizeof(AcpiGenericErrorData) + sizeof(UefiCperSecMemErr)); + + g_free(buffer); + return GHES_CPER_OK; +} + +static void +build_address(GArray *table_data, BIOSLinker *linker, + uint32_t dst_patched_offset, uint32_t src_offset, + uint8_t address_space_id , uint8_t register_bit_width, + uint8_t register_bit_offset, uint8_t access_size) +{ + uint32_t address_size = sizeof(struct AcpiGenericAddress) - + offsetof(struct AcpiGenericAddress, address); + + /* Address space */ + build_append_int_noprefix(table_data, address_space_id, 1); + /* register bit width */ + build_append_int_noprefix(table_data, register_bit_width, 1); + /* register bit offset */ + build_append_int_noprefix(table_data, register_bit_offset, 1); + /* access size */ + build_append_int_noprefix(table_data, access_size, 1); + acpi_data_push(table_data, address_size); + + /* Patch address of ERRORS fw_cfg blob into the TABLE fw_cfg blob so OSPM + * can retrieve and read it. the address size is 64 bits. + */ + bios_linker_loader_add_pointer(linker, + ACPI_BUILD_TABLE_FILE, dst_patched_offset, sizeof(uint64_t), + GHES_ERRORS_FW_CFG_FILE, src_offset); +} + +void ghes_build_acpi(GArray *table_data, GArray *hardware_error, + BIOSLinker *linker) +{ + uint32_t ghes_start = table_data->len; + uint32_t address_size, ack_value_size, error_status_address_offset; + uint32_t read_ack_register_offset, i; + /* + * The block_req_size stands for two address and one + * generic error status block + * +---------+ + * | address |-----------> +---------+ + * +---------+ | CPER | + * | ack | | CPER | + * | address |----+ | CPER | + * +---------+ | | CPER | + * | ack0 |<---+ | .... | + * +---------+ +---------+ + */ + address_size = sizeof(struct AcpiGenericAddress) - + offsetof(struct AcpiGenericAddress, address); + ack_value_size = (offsetof(struct hardware_errors_buffer, gesb) - + offsetof(struct hardware_errors_buffer, ack_value)) / + GHES_ACPI_HEST_NOTIFY_RESERVED; + + error_status_address_offset = ghes_start + + sizeof(AcpiHardwareErrorSourceTable) + + offsetof(AcpiGenericHardwareErrorSourceV2, error_status_address) + + offsetof(struct AcpiGenericAddress, address); + + read_ack_register_offset = ghes_start + + sizeof(AcpiHardwareErrorSourceTable) + + offsetof(AcpiGenericHardwareErrorSourceV2, read_ack_register) + + offsetof(struct AcpiGenericAddress, address); + + acpi_data_push(hardware_error, + offsetof(struct hardware_errors_buffer, ack_value)); + for (i = 0; i < GHES_ACPI_HEST_NOTIFY_RESERVED; i++) + /* Initialize read ack value */ + build_append_int_noprefix((void *)hardware_error, 1, 8); + + /* Reserved the total size for ERRORS fw_cfg blob + */ + acpi_data_push(hardware_error, sizeof(struct hardware_errors_buffer)); + + /* Allocate guest memory for the Data fw_cfg blob */ + bios_linker_loader_alloc(linker, GHES_ERRORS_FW_CFG_FILE, hardware_error, + 1, false); + /* Reserve table header size */ + acpi_data_push(table_data, sizeof(AcpiTableHeader)); + + build_append_int_noprefix(table_data, GHES_ACPI_HEST_NOTIFY_RESERVED, 4); + + for (i = 0; i < GHES_ACPI_HEST_NOTIFY_RESERVED; i++) { + build_append_int_noprefix(table_data, + ACPI_HEST_SOURCE_GENERIC_ERROR_V2, 2); /* type */ + /* source id */ + build_append_int_noprefix(table_data, cpu_to_le16(i), 2); + /* related source id */ + build_append_int_noprefix(table_data, 0xffff, 2); + build_append_int_noprefix(table_data, 0, 1); /* flags */ + + /* Currently only enable SEA and SEI notification type to avoid the + * kernel warning, reserve the space for other notification error source + */ + if (i == ACPI_HEST_NOTIFY_SEA || i == ACPI_HEST_NOTIFY_SEI) { + build_append_int_noprefix(table_data, 1, 1); /* enabled */ + } else { + build_append_int_noprefix(table_data, 0, 1); /* enabled */ + } + + /* The number of error status block per generic hardware error source */ + build_append_int_noprefix(table_data, 1, 4); + /* Max sections per record */ + build_append_int_noprefix(table_data, 1, 4); + /* Max raw data length */ + build_append_int_noprefix(table_data, GHES_MAX_RAW_DATA_LENGTH, 4); + + /* Build error Status Address*/ + build_address(table_data, linker, error_status_address_offset + i * + sizeof(AcpiGenericHardwareErrorSourceV2), i * address_size, + AML_SYSTEM_MEMORY, 0x40, 0, 4 /* QWord access */); + + /* Hardware error notification structure */ + build_append_int_noprefix(table_data, i, 1); /* type */ + /* length */ + build_append_int_noprefix(table_data, sizeof(AcpiHestNotify), 1); + build_append_int_noprefix(table_data, 0, 26); + + /* Error Status Block Length */ + build_append_int_noprefix(table_data, + cpu_to_le32(GHES_MAX_RAW_DATA_LENGTH), 4); + + /* Build read ack register */ + build_address(table_data, linker, read_ack_register_offset + i * + sizeof(AcpiGenericHardwareErrorSourceV2), + offsetof(struct hardware_errors_buffer, ack_register) + + i * address_size, AML_SYSTEM_MEMORY, 0x40, 0, + 4 /* QWord access */); + + /* Read ack preserve */ + build_append_int_noprefix(table_data, cpu_to_le64(0xfffffffe), 8); + + /* Read ack write */ + build_append_int_noprefix(table_data, cpu_to_le64(0x1), 8); + } + + for (i = 0; i < GHES_ACPI_HEST_NOTIFY_RESERVED; i++) { + /* Patch address of generic error status block into + * the address register so OSPM can retrieve and read it. + */ + bios_linker_loader_add_pointer(linker, + GHES_ERRORS_FW_CFG_FILE, address_size * i, address_size, + GHES_ERRORS_FW_CFG_FILE, + offsetof(struct hardware_errors_buffer, gesb) + + i * GHES_MAX_RAW_DATA_LENGTH); + + /* Patch address of read ack into the read ack register so + * OSPM can retrieve and read it. + */ + bios_linker_loader_add_pointer(linker, + GHES_ERRORS_FW_CFG_FILE, + offsetof(struct hardware_errors_buffer, ack_register) + + address_size * i, address_size, GHES_ERRORS_FW_CFG_FILE, + offsetof(struct hardware_errors_buffer, ack_value) + i * ack_value_size); + } + + /* Patch address of ERRORS fw_cfg blob into the ADDR fw_cfg blob + * so QEMU can write the ERRORS there. The address is expected to be + * < 4GB, but write 64 bits anyway. + */ + bios_linker_loader_write_pointer(linker, GHES_DATA_ADDR_FW_CFG_FILE, + 0, address_size, GHES_ERRORS_FW_CFG_FILE, + offsetof(struct hardware_errors_buffer, gesb)); + + build_header(linker, table_data, + (void *)(table_data->data + ghes_start), "HEST", + table_data->len - ghes_start, 1, NULL, "GHES"); +} + +static GhesState ges; +void ghes_add_fw_cfg(FWCfgState *s, GArray *hardware_error) +{ + + size_t request_block_size = sizeof(uint64_t) + GHES_MAX_RAW_DATA_LENGTH; + size_t size = GHES_ACPI_HEST_NOTIFY_RESERVED * request_block_size; + + /* Create a read-only fw_cfg file for GHES */ + fw_cfg_add_file(s, GHES_ERRORS_FW_CFG_FILE, hardware_error->data, + size); + /* Create a read-write fw_cfg file for Address */ + fw_cfg_add_file_callback(s, GHES_DATA_ADDR_FW_CFG_FILE, NULL, NULL, + &ges.ghes_addr_le, sizeof(ges.ghes_addr_le), false); +} + +bool ghes_update_guest(uint32_t notify, uint64_t physical_address) +{ + uint64_t error_block_addr; + uint64_t ack_addr, ack_value = 0; + int loop = 0, ack_value_size; + bool ret = GHES_CPER_FAIL; + + ack_value_size = (offsetof(struct hardware_errors_buffer, gesb) - + offsetof(struct hardware_errors_buffer, ack_value)) / + GHES_ACPI_HEST_NOTIFY_RESERVED; +retry: + if (physical_address && notify < GHES_ACPI_HEST_NOTIFY_RESERVED) { + error_block_addr = ges.ghes_addr_le + notify * GHES_MAX_RAW_DATA_LENGTH; + error_block_addr = le32_to_cpu(error_block_addr); + + ack_addr = ges.ghes_addr_le - + (GHES_ACPI_HEST_NOTIFY_RESERVED - notify) * ack_value_size; + cpu_physical_memory_read(ack_addr, &ack_value, ack_value_size); + if (!ack_value) { + if (loop < 3) { + usleep(100 * 1000); + loop++; + goto retry; + } else { + error_report("Last time OSPM does not acknowledge the error," + " record CPER failed this time, set the ack value to" + " avoid blocking next time CPER record! exit"); + ack_value = 1; + cpu_physical_memory_write(ack_addr, &ack_value, ack_value_size); + return ret; + } + } else { + /* A zero value in ghes_addr means that BIOS has not yet written + * the address + */ + if (error_block_addr) { + ack_value = 0; + cpu_physical_memory_write(ack_addr, &ack_value, ack_value_size); + ret = ghes_record_cper(error_block_addr, physical_address); + } + } + } + + return ret; +} diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c index 0835e59..5c97016 100644 --- a/hw/arm/virt-acpi-build.c +++ b/hw/arm/virt-acpi-build.c @@ -45,6 +45,7 @@ #include "hw/arm/virt.h" #include "sysemu/numa.h" #include "kvm_arm.h" +#include "hw/acpi/hest_ghes.h" #define ARM_SPI_BASE 32 #define ACPI_POWER_BUTTON_DEVICE "PWRB" @@ -778,6 +779,9 @@ void virt_acpi_build(VirtMachineState *vms, AcpiBuildTables *tables) acpi_add_table(table_offsets, tables_blob); build_spcr(tables_blob, tables->linker, vms); + acpi_add_table(table_offsets, tables_blob); + ghes_build_acpi(tables_blob, tables->hardware_errors, tables->linker); + if (nb_numa_nodes > 0) { acpi_add_table(table_offsets, tables_blob); build_srat(tables_blob, tables->linker, vms); @@ -890,6 +894,8 @@ void virt_acpi_setup(VirtMachineState *vms) fw_cfg_add_file(vms->fw_cfg, ACPI_BUILD_TPMLOG_FILE, tables.tcpalog->data, acpi_data_len(tables.tcpalog)); + ghes_add_fw_cfg(vms->fw_cfg, tables.hardware_errors); + build_state->rsdp_mr = acpi_add_rom_blob(build_state, tables.rsdp, ACPI_BUILD_RSDP_FILE, 0); diff --git a/include/hw/acpi/aml-build.h b/include/hw/acpi/aml-build.h index 00c21f1..c1d15b3 100644 --- a/include/hw/acpi/aml-build.h +++ b/include/hw/acpi/aml-build.h @@ -211,6 +211,7 @@ struct AcpiBuildTables { GArray *rsdp; GArray *tcpalog; GArray *vmgenid; + GArray *hardware_errors; BIOSLinker *linker; } AcpiBuildTables; diff --git a/include/hw/acpi/hest_ghes.h b/include/hw/acpi/hest_ghes.h new file mode 100644 index 0000000..0772756 --- /dev/null +++ b/include/hw/acpi/hest_ghes.h @@ -0,0 +1,47 @@ +/* + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Authors: + * Dongjiu Geng + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#ifndef ACPI_GHES_H +#define ACPI_GHES_H + +#include "hw/acpi/bios-linker-loader.h" + +#define GHES_ERRORS_FW_CFG_FILE "etc/hardware_errors" +#define GHES_DATA_ADDR_FW_CFG_FILE "etc/hardware_errors_addr" + +#define GHES_GAS_ADDRESS_OFFSET 4 +#define GHES_ERROR_STATUS_ADDRESS_OFFSET 20 +#define GHES_NOTIFICATION_STRUCTURE 32 + +#define GHES_CPER_OK 1 +#define GHES_CPER_FAIL 0 + +#define GHES_ACPI_HEST_NOTIFY_RESERVED 11 +/* The max size in Bytes for one error block */ +#define GHES_MAX_RAW_DATA_LENGTH 0x1000 + + +typedef struct GhesState { + uint64_t ghes_addr_le; +} GhesState; + +void ghes_build_acpi(GArray *table_data, GArray *hardware_error, + BIOSLinker *linker); +void ghes_add_fw_cfg(FWCfgState *s, GArray *hardware_errors); +bool ghes_update_guest(uint32_t notify, uint64_t error_physical_addr); +#endif -- 1.8.3.1 From MAILER-DAEMON Fri Aug 04 02:26:16 2017 Received: from list by lists.gnu.org with archive (Exim 4.71) id 1ddW3s-0006Qz-Kh for mharc-qemu-arm@gnu.org; Fri, 04 Aug 2017 02:26:16 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:38782) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ddULC-0005vY-Lv for qemu-arm@nongnu.org; Fri, 04 Aug 2017 00:36:24 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ddUKq-0007Ef-A5 for qemu-arm@nongnu.org; Fri, 04 Aug 2017 00:36:02 -0400 Resent-Date: Fri, 04 Aug 2017 00:36:02 -0400 Resent-Message-Id: Received: from sender-of-o53.zoho.com ([135.84.80.218]:21719) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1ddUK7-0005za-J6; Fri, 04 Aug 2017 00:34:56 -0400 Received: from [172.17.0.2] (23.253.156.214 [23.253.156.214]) by mx.zohomail.com with SMTPS id 1501821263415737.3754309032093; Thu, 3 Aug 2017 21:34:23 -0700 (PDT) Reply-To: In-Reply-To: <1501821475-14647-1-git-send-email-gengdongjiu@huawei.com> Message-ID: <150182126158.60.8043980657896114045@93e45bedd699> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Resent-From: From: no-reply@patchew.org To: gengdongjiu@huawei.com Cc: famz@redhat.com, lersek@redhat.com, mst@redhat.com, imammedo@redhat.com, zhaoshenglong@huawei.com, peter.maydell@linaro.org, qemu-devel@nongnu.org, qemu-arm@nongnu.org, wuquanming@huawei.com, huangshaoyu@huawei.com, gengdongjiu@huawei.com Date: Thu, 3 Aug 2017 21:34:23 -0700 (PDT) X-ZohoMailClient: External X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [fuzzy] X-Received-From: 135.84.80.218 X-Mailman-Approved-At: Fri, 04 Aug 2017 02:26:10 -0400 Subject: Re: [Qemu-arm] [Qemu-devel] [PATCH v6 0/3] Generate APEI GHES table and dynamically record CPER X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: 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(TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1ddWW3-0006Z4-Ei; Fri, 04 Aug 2017 02:55:23 -0400 Received: from smtp.corp.redhat.com (int-mx02.intmail.prod.int.phx2.redhat.com [10.5.11.12]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id DF1C9461D6; Fri, 4 Aug 2017 06:55:17 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mx1.redhat.com DF1C9461D6 Authentication-Results: ext-mx05.extmail.prod.ext.phx2.redhat.com; dmarc=none (p=none dis=none) header.from=redhat.com Authentication-Results: ext-mx05.extmail.prod.ext.phx2.redhat.com; spf=fail smtp.mailfrom=famz@redhat.com Received: from localhost (ovpn-12-95.pek2.redhat.com [10.72.12.95]) by smtp.corp.redhat.com (Postfix) with ESMTP id 134C160BE2; Fri, 4 Aug 2017 06:55:10 +0000 (UTC) Date: Fri, 4 Aug 2017 14:55:06 +0800 From: Fam Zheng To: qemu-devel@nongnu.org Cc: gengdongjiu@huawei.com, lersek@redhat.com, mst@redhat.com, imammedo@redhat.com, zhaoshenglong@huawei.com, peter.maydell@linaro.org, qemu-arm@nongnu.org, zhengqiang10@huawei.com, wuquanming@huawei.com, huangshaoyu@huawei.com Message-ID: <20170804065506.GA30690@lemon.lan> References: <1501825872-12555-1-git-send-email-gengdongjiu@huawei.com> <150182648212.60.18351046270646942452@93e45bedd699> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <150182648212.60.18351046270646942452@93e45bedd699> User-Agent: Mutt/1.8.3 (2017-05-23) X-Scanned-By: MIMEDefang 2.79 on 10.5.11.12 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.29]); Fri, 04 Aug 2017 06:55:18 +0000 (UTC) X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.132.183.28 Subject: Re: [Qemu-arm] [Qemu-devel] [PATCH v8 0/3] Generate APEI GHES table and dynamically record CPER X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 04 Aug 2017 06:55:28 -0000 On Thu, 08/03 23:01, no-reply@patchew.org wrote: > /var/tmp/patchew-tester-tmp-2j515e8v/src/tcg/tcg-op.c:3056:1: fatal error: error writing to /tmp/cc9gtyQ1.s: No space left on device Sorry, it is a false positive. I will clean up the disk space and rerun the test. Sorry for the noise. Fam From MAILER-DAEMON Fri Aug 04 05:49:53 2017 Received: from list by lists.gnu.org with archive (Exim 4.71) id 1ddZEu-0006UW-UR for mharc-qemu-arm@gnu.org; Fri, 04 Aug 2017 05:49:52 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:38605) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ddZEs-0006Pi-Lr for qemu-arm@nongnu.org; Fri, 04 Aug 2017 05:49:51 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ddZEr-00049M-T4 for qemu-arm@nongnu.org; Fri, 04 Aug 2017 05:49:50 -0400 Received: from szxga02-in.huawei.com ([45.249.212.188]:4414) by eggs.gnu.org with esmtps (TLS1.0:RSA_ARCFOUR_SHA1:16) (Exim 4.71) (envelope-from ) id 1ddZEn-00045j-8b; Fri, 04 Aug 2017 05:49:45 -0400 Received: from 172.30.72.54 (EHLO DGGEML402-HUB.china.huawei.com) ([172.30.72.54]) by dggrg02-dlp.huawei.com (MOS 4.4.6-GA FastPath queued) with ESMTP id ASW04676; Fri, 04 Aug 2017 17:49:39 +0800 (CST) Received: from linux.huawei.com (10.67.187.203) by DGGEML402-HUB.china.huawei.com (10.3.17.38) with Microsoft SMTP Server id 14.3.301.0; Fri, 4 Aug 2017 17:49:31 +0800 From: Dongjiu Geng To: , , , , , , CC: , , , Date: Fri, 4 Aug 2017 18:09:16 +0800 Message-ID: <1501841356-6486-4-git-send-email-gengdongjiu@huawei.com> X-Mailer: git-send-email 1.7.7 In-Reply-To: <1501841356-6486-1-git-send-email-gengdongjiu@huawei.com> References: <1501841356-6486-1-git-send-email-gengdongjiu@huawei.com> MIME-Version: 1.0 Content-Type: text/plain X-Originating-IP: [10.67.187.203] X-CFilter-Loop: Reflected X-Mirapoint-Virus-RAPID-Raw: score=unknown(0), refid=str=0001.0A020202.59844335.0059, ss=1, re=0.000, recu=0.000, reip=0.000, cl=1, cld=1, fgs=0, ip=0.0.0.0, so=2014-11-16 11:51:01, dmn=2013-03-21 17:37:32 X-Mirapoint-Loop-Id: fef60eaecf1c28c15ff459b02be33903 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.4.x-2.6.x [generic] [fuzzy] X-Received-From: 45.249.212.188 Subject: [Qemu-arm] [PATCH v9 3/3] ACPI: build and enable APEI GHES in the Makefile and configuration X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 04 Aug 2017 09:49:51 -0000 Add CONFIG_ACPI_APEI configuration in the Makefile and enable it in the arm-softmmu.mak Signed-off-by: Dongjiu Geng --- thanks a lot Michael and Laszlo's review and comments: change since v5: (1) no change change since v4: (1) fix email threading in this series is incorrect issue change since v3: (1) change name to "CONFIG_ACPI_APEI" from CONFIG_ACPI_APEI_GENERATION --- default-configs/arm-softmmu.mak | 1 + hw/acpi/Makefile.objs | 1 + 2 files changed, 2 insertions(+) diff --git a/default-configs/arm-softmmu.mak b/default-configs/arm-softmmu.mak index 1e3bd2b..ee6f5fc 100644 --- a/default-configs/arm-softmmu.mak +++ b/default-configs/arm-softmmu.mak @@ -121,3 +121,4 @@ CONFIG_ACPI=y CONFIG_SMBIOS=y CONFIG_ASPEED_SOC=y CONFIG_GPIO_KEY=y +CONFIG_ACPI_APEI=y diff --git a/hw/acpi/Makefile.objs b/hw/acpi/Makefile.objs index 11c35bc..bafb148 100644 --- a/hw/acpi/Makefile.objs +++ b/hw/acpi/Makefile.objs @@ -6,6 +6,7 @@ common-obj-$(CONFIG_ACPI_MEMORY_HOTPLUG) += memory_hotplug.o common-obj-$(CONFIG_ACPI_CPU_HOTPLUG) += cpu.o common-obj-$(CONFIG_ACPI_NVDIMM) += nvdimm.o common-obj-$(CONFIG_ACPI_VMGENID) += vmgenid.o +common-obj-$(CONFIG_ACPI_APEI) += hest_ghes.o common-obj-$(call lnot,$(CONFIG_ACPI_X86)) += acpi-stub.o common-obj-y += acpi_interface.o -- 1.8.3.1 From MAILER-DAEMON Fri Aug 04 05:49:57 2017 Received: from list by lists.gnu.org with archive (Exim 4.71) id 1ddZEy-0006b1-Sk for mharc-qemu-arm@gnu.org; Fri, 04 Aug 2017 05:49:56 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:38637) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ddZEu-0006TB-A3 for qemu-arm@nongnu.org; Fri, 04 Aug 2017 05:49:54 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ddZEs-00049s-Sm for qemu-arm@nongnu.org; Fri, 04 Aug 2017 05:49:52 -0400 Received: from szxga02-in.huawei.com ([45.249.212.188]:4413) by eggs.gnu.org with esmtps (TLS1.0:RSA_ARCFOUR_SHA1:16) (Exim 4.71) (envelope-from ) id 1ddZEn-00045l-9b; Fri, 04 Aug 2017 05:49:46 -0400 Received: from 172.30.72.54 (EHLO DGGEML402-HUB.china.huawei.com) ([172.30.72.54]) by dggrg02-dlp.huawei.com (MOS 4.4.6-GA FastPath queued) with ESMTP id ASW04679; Fri, 04 Aug 2017 17:49:40 +0800 (CST) Received: from linux.huawei.com (10.67.187.203) by DGGEML402-HUB.china.huawei.com (10.3.17.38) with Microsoft SMTP Server id 14.3.301.0; Fri, 4 Aug 2017 17:49:31 +0800 From: Dongjiu Geng To: , , , , , , CC: , , , Date: Fri, 4 Aug 2017 18:09:14 +0800 Message-ID: <1501841356-6486-2-git-send-email-gengdongjiu@huawei.com> X-Mailer: git-send-email 1.7.7 In-Reply-To: <1501841356-6486-1-git-send-email-gengdongjiu@huawei.com> References: <1501841356-6486-1-git-send-email-gengdongjiu@huawei.com> MIME-Version: 1.0 Content-Type: text/plain X-Originating-IP: [10.67.187.203] X-CFilter-Loop: Reflected X-Mirapoint-Virus-RAPID-Raw: score=unknown(0), refid=str=0001.0A020202.59844335.006C, ss=1, re=0.000, recu=0.000, reip=0.000, cl=1, cld=1, fgs=0, ip=0.0.0.0, so=2014-11-16 11:51:01, dmn=2013-03-21 17:37:32 X-Mirapoint-Loop-Id: 24638b1015786536c59fdbc76ab10284 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.4.x-2.6.x [generic] [fuzzy] X-Received-From: 45.249.212.188 Subject: [Qemu-arm] [PATCH v9 1/3] ACPI: add APEI/HEST/CPER structures and macros X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 04 Aug 2017 09:49:54 -0000 (1) Add related APEI/HEST table structures and macros, these definition refer to ACPI 6.1 and UEFI 2.6 spec. (2) Add generic error status block and CPER memory section definition, user space only handle memory section errors. Signed-off-by: Dongjiu Geng --- thanks Michael and Laszlo's review: change since v5: (1) update the commit message title (2) remove UUID_BE and UEFI_CPER_SEC_PLATFORM_MEM macros (3) remove including "qemu/uuid.h" file in this patch (4) remove including "hest_ghes.h" file in this patch (5) drop "this is" from the comment of structures and macros (6) replace the "QemuUUID section_type_le" to "uint8_t section_type_le[16]" chnage since v4: (1) fix email threading in this series is incorrect issue change since v3: (1) separate the original one patch into three patches: one is new ACPI structures and macros, another is C source file to generate ACPI HEST table and dynamically record CPER ,final patch is the change about Makefile and configuration (2) add comments about where the ACPI structures and macros come from, for example, they come from the UEFI Spec 2.6, "xxxxxxxxxxxx"; ACPI 6.1 spec, "xxxxxxxxxxxxxx". (3) correct the macros name, for emaple, prefix some macro names with "UEFI_". (4) remove the uuid_le struct and use the QemuUUID in the include/qemu/uuid.h" (5) remove the duplicate ACPI address space, because it already defined in the "include/hw/acpi/aml-build.h" (6) remove the acpi_generic_address structure because same definition exists in the AcpiGenericAddress. (7) rename the struct acpi_hest_notify to AcpiHestNotifyType (8) rename the struct acpi_hest_types to AcpiHestSourceType (9) rename enum constants AcpiHestSourceType to ACPI_HEST_SOURCE_xxx from ACPI_HEST_TYPE_xxx (10) remove the NOT_USED{3,4,5} enum constants in the AcpiHestSourceType. (11) add missed QEMU_PACKED for the struct definition. (12) remove the defnition of AcpiGenericErrorData, and rename the AcpiGenericErrorDataV300 to AcpiGenericErrorData. (13) use the QemuUUID type for the "section_type" field AcpiGenericErrorData, and rename it to section_type_le. (14) moving type AcpiGenericErrorSeverity above AcpiGenericErrorData and AcpiGenericErrorDataV300, and remarking on the "error_severity" fields that they take their values from AcpiGenericErrorSeverity (15) remove the wrongly call to BERT(Boot Error Record Table) (16) add comments for the struction member, for example, pint out that the block_status member in the AcpiGenericErrorStatus is a bitmask composed of ACPI_GEBS_xxx macros (17) remove the hardware error source notification type list, and rename the MAX_ERROR_SOURCE_COUNT_V6 to ACPI_HEST_NOTIFY_RESERVED. (18) remove the physical_addr member of GhesErrorState (19) change the "uint64_t ghes_addr_le[8]" in GhesErrorState to uint64_t ghes_addr_le (20) change the second parameter to "error_physical_addr" in the ghes_update_guest API statement --- include/hw/acpi/acpi-defs.h | 193 ++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 193 insertions(+) diff --git a/include/hw/acpi/acpi-defs.h b/include/hw/acpi/acpi-defs.h index 4cc3630..ff9525e 100644 --- a/include/hw/acpi/acpi-defs.h +++ b/include/hw/acpi/acpi-defs.h @@ -295,6 +295,44 @@ typedef struct AcpiMultipleApicTable AcpiMultipleApicTable; #define ACPI_APIC_GENERIC_TRANSLATOR 15 #define ACPI_APIC_RESERVED 16 /* 16 and greater are reserved */ +/* UEFI Spec 2.6, "N.2.5 Memory Error Section */ +#define UEFI_CPER_MEM_VALID_ERROR_STATUS 0x0001 +#define UEFI_CPER_MEM_VALID_PA 0x0002 +#define UEFI_CPER_MEM_VALID_PA_MASK 0x0004 +#define UEFI_CPER_MEM_VALID_NODE 0x0008 +#define UEFI_CPER_MEM_VALID_CARD 0x0010 +#define UEFI_CPER_MEM_VALID_MODULE 0x0020 +#define UEFI_CPER_MEM_VALID_BANK 0x0040 +#define UEFI_CPER_MEM_VALID_DEVICE 0x0080 +#define UEFI_CPER_MEM_VALID_ROW 0x0100 +#define UEFI_CPER_MEM_VALID_COLUMN 0x0200 +#define UEFI_CPER_MEM_VALID_BIT_POSITION 0x0400 +#define UEFI_CPER_MEM_VALID_REQUESTOR 0x0800 +#define UEFI_CPER_MEM_VALID_RESPONDER 0x1000 +#define UEFI_CPER_MEM_VALID_TARGET 0x2000 +#define UEFI_CPER_MEM_VALID_ERROR_TYPE 0x4000 +#define UEFI_CPER_MEM_VALID_RANK_NUMBER 0x8000 +#define UEFI_CPER_MEM_VALID_CARD_HANDLE 0x10000 +#define UEFI_CPER_MEM_VALID_MODULE_HANDLE 0x20000 +#define UEFI_CPER_MEM_ERROR_TYPE_MULTI_ECC 3 + +/* From the ACPI 6.1 spec, "18.3.2.9 Hardware Error Notification" */ + +enum AcpiHestNotifyType { + ACPI_HEST_NOTIFY_POLLED = 0, + ACPI_HEST_NOTIFY_EXTERNAL = 1, + ACPI_HEST_NOTIFY_LOCAL = 2, + ACPI_HEST_NOTIFY_SCI = 3, + ACPI_HEST_NOTIFY_NMI = 4, + ACPI_HEST_NOTIFY_CMCI = 5, /* ACPI 5.0 */ + ACPI_HEST_NOTIFY_MCE = 6, /* ACPI 5.0 */ + ACPI_HEST_NOTIFY_GPIO = 7, /* ACPI 6.0 */ + ACPI_HEST_NOTIFY_SEA = 8, /* ACPI 6.1 */ + ACPI_HEST_NOTIFY_SEI = 9, /* ACPI 6.1 */ + ACPI_HEST_NOTIFY_GSIV = 10, /* ACPI 6.1 */ + ACPI_HEST_NOTIFY_RESERVED = 11 /* 11 and greater are reserved */ +}; + /* * MADT sub-structures (Follow MULTIPLE_APIC_DESCRIPTION_TABLE) */ @@ -475,6 +513,161 @@ struct AcpiSystemResourceAffinityTable } QEMU_PACKED; typedef struct AcpiSystemResourceAffinityTable AcpiSystemResourceAffinityTable; +/* Hardware Error Notification, from the ACPI 6.1 + * spec, "18.3.2.9 Hardware Error Notification" + */ +struct AcpiHestNotify { + uint8_t type; + uint8_t length; + uint16_t config_write_enable; + uint32_t poll_interval; + uint32_t vector; + uint32_t polling_threshold_value; + uint32_t polling_threshold_window; + uint32_t error_threshold_value; + uint32_t error_threshold_window; +} QEMU_PACKED; +typedef struct AcpiHestNotify AcpiHestNotify; + +/* From ACPI 6.1, sections "18.3.2.1 IA-32 Architecture Machine + * Check Exception" through "18.3.2.8 Generic Hardware Error Source version 2". + */ +enum AcpiHestSourceType { + ACPI_HEST_SOURCE_IA32_CHECK = 0, + ACPI_HEST_SOURCE_IA32_CORRECTED_CHECK = 1, + ACPI_HEST_SOURCE_IA32_NMI = 2, + ACPI_HEST_SOURCE_AER_ROOT_PORT = 6, + ACPI_HEST_SOURCE_AER_ENDPOINT = 7, + ACPI_HEST_SOURCE_AER_BRIDGE = 8, + ACPI_HEST_SOURCE_GENERIC_ERROR = 9, + ACPI_HEST_SOURCE_GENERIC_ERROR_V2 = 10, + ACPI_HEST_SOURCE_RESERVED = 11 /* 11 and greater are reserved */ +}; + +/* Block status bitmasks from ACPI 6.1, "18.3.2.7.1 Generic Error Data" */ +#define ACPI_GEBS_UNCORRECTABLE (1) +#define ACPI_GEBS_CORRECTABLE (1 << 1) +#define ACPI_GEBS_MULTIPLE_UNCORRECTABLE (1 << 2) +#define ACPI_GEBS_MULTIPLE_CORRECTABLE (1 << 3) +/* 10 bits, error data entry count */ +#define ACPI_GEBS_ERROR_ENTRY_COUNT (0x3FF << 4) + +/* Generic Hardware Error Source Structure, refer to ACPI 6.1 + * "18.3.2.7 Generic Hardware Error Source". in this struct the + * "type" field has to be ACPI_HEST_SOURCE_GENERIC_ERROR + */ + +struct AcpiGenericHardwareErrorSource { + uint16_t type; + uint16_t source_id; + uint16_t related_source_id; + uint8_t flags; + uint8_t enabled; + uint32_t number_of_records; + uint32_t max_sections_per_record; + uint32_t max_raw_data_length; + struct AcpiGenericAddress error_status_address; + struct AcpiHestNotify notify; + uint32_t error_status_block_length; +} QEMU_PACKED; +typedef struct AcpiGenericHardwareErrorSource AcpiGenericHardwareErrorSource; + +/* Generic Hardware Error Source, version 2, ACPI 6.1, "18.3.2.8 Generic + * Hardware Error Source version 2", in this struct the "type" field has to + * be ACPI_HEST_SOURCE_GENERIC_ERROR_V2 + */ +struct AcpiGenericHardwareErrorSourceV2 { + uint16_t type; + uint16_t source_id; + uint16_t related_source_id; + uint8_t flags; + uint8_t enabled; + uint32_t number_of_records; + uint32_t max_sections_per_record; + uint32_t max_raw_data_length; + struct AcpiGenericAddress error_status_address; + struct AcpiHestNotify notify; + uint32_t error_status_block_length; + struct AcpiGenericAddress read_ack_register; + uint64_t read_ack_preserve; + uint64_t read_ack_write; +} QEMU_PACKED; +typedef struct AcpiGenericHardwareErrorSourceV2 + AcpiGenericHardwareErrorSourceV2; + +/* Generic Error Status block, from ACPI 6.1, + * "18.3.2.7.1 Generic Error Data" + */ +struct AcpiGenericErrorStatus { + /* It is a bitmask composed of ACPI_GEBS_xxx macros */ + uint32_t block_status; + uint32_t raw_data_offset; + uint32_t raw_data_length; + uint32_t data_length; + uint32_t error_severity; +} QEMU_PACKED; +typedef struct AcpiGenericErrorStatus AcpiGenericErrorStatus; + +enum AcpiGenericErrorSeverity { + ACPI_CPER_SEV_RECOVERABLE, + ACPI_CPER_SEV_FATAL, + ACPI_CPER_SEV_CORRECTED, + ACPI_CPER_SEV_NONE, +}; + +/* Generic Error Data entry, revision number is 0x0300, + * ACPI 6.1, "18.3.2.7.1 Generic Error Data" + */ +struct AcpiGenericErrorData { + uint8_t section_type_le[16]; + /* The "error_severity" fields that they take their + * values from AcpiGenericErrorSeverity + */ + uint32_t error_severity; + uint16_t revision; + uint8_t validation_bits; + uint8_t flags; + uint32_t error_data_length; + uint8_t fru_id[16]; + uint8_t fru_text[20]; + uint64_t time_stamp; +} QEMU_PACKED; +typedef struct AcpiGenericErrorData AcpiGenericErrorData; + +/* From UEFI 2.6, "N.2.5 Memory Error Section" */ +struct UefiCperSecMemErr { + uint64_t validation_bits; + uint64_t error_status; + uint64_t physical_addr; + uint64_t physical_addr_mask; + uint16_t node; + uint16_t card; + uint16_t module; + uint16_t bank; + uint16_t device; + uint16_t row; + uint16_t column; + uint16_t bit_pos; + uint64_t requestor_id; + uint64_t responder_id; + uint64_t target_id; + uint8_t error_type; + uint8_t reserved; + uint16_t rank; + uint16_t mem_array_handle; /* card handle in UEFI 2.4 */ + uint16_t mem_dev_handle; /* module handle in UEFI 2.4 */ +} QEMU_PACKED; +typedef struct UefiCperSecMemErr UefiCperSecMemErr; + +/* + * HEST Description Table + */ +struct AcpiHardwareErrorSourceTable { + ACPI_TABLE_HEADER_DEF /* ACPI common table header */ + uint32_t error_source_count; +} QEMU_PACKED; +typedef struct AcpiHardwareErrorSourceTable AcpiHardwareErrorSourceTable; + #define ACPI_SRAT_PROCESSOR_APIC 0 #define ACPI_SRAT_MEMORY 1 #define ACPI_SRAT_PROCESSOR_x2APIC 2 -- 1.8.3.1 From MAILER-DAEMON Fri Aug 04 05:49:57 2017 Received: from list by lists.gnu.org with archive (Exim 4.71) id 1ddZEz-0006bq-4m for mharc-qemu-arm@gnu.org; Fri, 04 Aug 2017 05:49:57 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:38646) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ddZEu-0006UK-OX for qemu-arm@nongnu.org; Fri, 04 Aug 2017 05:49:54 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ddZEt-0004A7-0K for qemu-arm@nongnu.org; Fri, 04 Aug 2017 05:49:52 -0400 Received: from szxga02-in.huawei.com ([45.249.212.188]:4416) by eggs.gnu.org with esmtps (TLS1.0:RSA_ARCFOUR_SHA1:16) (Exim 4.71) (envelope-from ) id 1ddZEn-00046B-BK; Fri, 04 Aug 2017 05:49:46 -0400 Received: from 172.30.72.54 (EHLO DGGEML402-HUB.china.huawei.com) ([172.30.72.54]) by dggrg02-dlp.huawei.com (MOS 4.4.6-GA FastPath queued) with ESMTP id ASW04680; Fri, 04 Aug 2017 17:49:40 +0800 (CST) Received: from linux.huawei.com (10.67.187.203) by DGGEML402-HUB.china.huawei.com (10.3.17.38) with Microsoft SMTP Server id 14.3.301.0; Fri, 4 Aug 2017 17:49:30 +0800 From: Dongjiu Geng To: , , , , , , CC: , , , Date: Fri, 4 Aug 2017 18:09:13 +0800 Message-ID: <1501841356-6486-1-git-send-email-gengdongjiu@huawei.com> X-Mailer: git-send-email 1.7.7 MIME-Version: 1.0 Content-Type: text/plain X-Originating-IP: [10.67.187.203] X-CFilter-Loop: Reflected X-Mirapoint-Virus-RAPID-Raw: score=unknown(0), refid=str=0001.0A090201.59844336.0162, ss=1, re=0.000, recu=0.000, reip=0.000, cl=1, cld=1, fgs=0, ip=0.0.0.0, so=2014-11-16 11:51:01, dmn=2013-03-21 17:37:32 X-Mirapoint-Loop-Id: bd2467e7446401e5a3a8df08fc737ce7 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.4.x-2.6.x [generic] [fuzzy] X-Received-From: 45.249.212.188 Subject: [Qemu-arm] [PATCH v9 0/3] Generate APEI GHES table and dynamically record CPER X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 04 Aug 2017 09:49:54 -0000 In the armv8 platform, the mainly hardware error source are ARMv8 SEA/SEI/GSIV. For the ARMv8 SEA/SEI, the KVM or host kernel will signal SIGBUS or use other interface to notify user space, such as Qemu. After Qemu gets the notification, it will record the CPER and inject the SEA/SEI to KVM. this series of patches will generate APEI table when guest OS boot up, and dynamically record CPER for the guest OS about the generic hardware errors, currently the userspace only handle the memory section hardware errors. Before Qemu record the CPER, it needs to check the ACK value written by the guest OS to avoid read-write race condition. Below is the APEI/GHESV2/CPER table layout, the max number of error soure is 11, which is classified by notification type, now only enable the SEA/SEI notification type error source. etc/acpi/tables etc/hardware_errors ==================== ========================================== + +--------------------------+ +------------------+ | | HEST | | address | +--------------+ | +--------------------------+ | registers | | Error Status | | | GHES0 | | +----------------+ | Data Block 0 | | +--------------------------+ +--------->| |status_address0 |------------->| +------------+ | | ................. | | | +----------------+ | | CPER | | | error_status_address-----+-+ +------->| |status_address1 |----------+ | | CPER | | | ................. | | | +----------------+ | | | .... | | | read_ack_register--------+-+ | | ............. | | | | CPER | | | read_ack_preserve | | | +------------------+ | | +-+------------+ | | read_ack_write | | | +----->| |status_address10|--------+ | | Error Status | + +--------------------------+ | | | | +----------------+ | | | Data Block 1 | | | GHES1 | +-+-+----->| |ack_address0 |--+ | +-->| +------------+ + +--------------------------+ | | | +----------------+ | | | | CPER | | | ................. | | | +--->| |ack_address1 |--+-+ | | | CPER | | | error_status_address-----+---+ | | | +----------------+ | | | | | .... | | | ................. | | | | | ............. | | | | | | CPER | | | read_ack_register--------+-----+-+ | +----------------+ | | | +-+------------+ | | read_ack_preserve | | +->| |ack_address10 |--+-+-+ | | |.......... | | | read_ack_write | | | | +----------------+ | | | | | +------------+ + +--------------------------| | | | | ack0 |<-+ | | | | Error Status | | | ............... | | | | +----------------+ | | | | Data Block 10| + +--------------------------+ | | | | ack1 |<---+ | +---->| +------------+ | | GHES10 | | | | +----------------+ | | | CPER | + +--------------------------+ | | | | .... | | | | CPER | | | ................. | | | | +--------------+ | | | | .... | | | error_status_address-----+-----+ | | | ack10 |<---- + | | CPER | | | ................. | | | +----------------+ +-+------------+ | | read_ack_register--------+---------+ | | read_ack_preserve | | | read_ack_write | + +--------------------------+ After injecting a SEA/SEI ghes error, the gueset OS kernel log will be shown as below: [ 142.911115] {1}[Hardware Error]: Hardware error from APEI Generic Hardware Error Source: 8 [ 142.913141] {1}[Hardware Error]: event severity: recoverable [ 142.914498] {1}[Hardware Error]: Error 0, type: recoverable [ 142.915851] {1}[Hardware Error]: section_type: memory error [ 142.917163] {1}[Hardware Error]: physical_address: 0x0000000000001111 [ 142.918792] {1}[Hardware Error]: error_type: 3, multi-bit ECC how to test: 1. In the guest OS, use this command to dump the APEI table: "iasl -p ./HEST -d /sys/firmware/acpi/tables/HEST" 2. And find the address for the generic error status block according to the notification type 3. then find the CPER record through the generic error status block. For example(notification type is SEA): (1) root@genericarmv8:~# iasl -p ./HEST -d /sys/firmware/acpi/tables/HEST (2) root@genericarmv8:~# cat HEST.dsl /* * Intel ACPI Component Architecture * AML/ASL+ Disassembler version 20170728 (64-bit version) * Copyright (c) 2000 - 2017 Intel Corporation * * Disassembly of /sys/firmware/acpi/tables/HEST, Mon Sep 5 07:59:17 2016 * * ACPI Data Table [HEST] * * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue */ .................................................................................. [308h 0776 2] Subtable Type : 000A [Generic Hardware Error Source V2] [30Ah 0778 2] Source Id : 0008 [30Ch 0780 2] Related Source Id : FFFF [30Eh 0782 1] Reserved : 00 [30Fh 0783 1] Enabled : 01 [310h 0784 4] Records To Preallocate : 00000001 [314h 0788 4] Max Sections Per Record : 00000001 [318h 0792 4] Max Raw Data Length : 00001000 [31Ch 0796 12] Error Status Address : [Generic Address Structure] [31Ch 0796 1] Space ID : 00 [SystemMemory] [31Dh 0797 1] Bit Width : 40 [31Eh 0798 1] Bit Offset : 00 [31Fh 0799 1] Encoded Access Width : 04 [QWord Access:64] [320h 0800 8] Address : 00000000785D0040 [328h 0808 28] Notify : [Hardware Error Notification Structure] [328h 0808 1] Notify Type : 08 [SEA] [329h 0809 1] Notify Length : 1C [32Ah 0810 2] Configuration Write Enable : 0000 [32Ch 0812 4] PollInterval : 00000000 [330h 0816 4] Vector : 00000000 [334h 0820 4] Polling Threshold Value : 00000000 [338h 0824 4] Polling Threshold Window : 00000000 [33Ch 0828 4] Error Threshold Value : 00000000 [340h 0832 4] Error Threshold Window : 00000000 [344h 0836 4] Error Status Block Length : 00001000 [348h 0840 12] Read Ack Register : [Generic Address Structure] [348h 0840 1] Space ID : 00 [SystemMemory] [349h 0841 1] Bit Width : 40 [34Ah 0842 1] Bit Offset : 00 [34Bh 0843 1] Encoded Access Width : 04 [QWord Access:64] [34Ch 0844 8] Address : 00000000785D0098 [354h 0852 8] Read Ack Preserve : 00000000FFFFFFFE [35Ch 0860 8] Read Ack Write : 0000000000000001 [364h 0868 2] Subtable Type : 000A [Generic Hardware Error Source V2] [366h 0870 2] Source Id : 0009 [368h 0872 2] Related Source Id : FFFF [36Ah 0874 1] Reserved : 00 [36Bh 0875 1] Enabled : 01 [36Ch 0876 4] Records To Preallocate : 00000001 [370h 0880 4] Max Sections Per Record : 00000001 [374h 0884 4] Max Raw Data Length : 00001000 [378h 0888 12] Error Status Address : [Generic Address Structure] [378h 0888 1] Space ID : 00 [SystemMemory] [379h 0889 1] Bit Width : 40 [37Ah 0890 1] Bit Offset : 00 [37Bh 0891 1] Encoded Access Width : 04 [QWord Access:64] [37Ch 0892 8] Address : 00000000785D0048 [384h 0900 28] Notify : [Hardware Error Notification Structure] [384h 0900 1] Notify Type : 09 [SEI] [385h 0901 1] Notify Length : 1C [386h 0902 2] Configuration Write Enable : 0000 [388h 0904 4] PollInterval : 00000000 [38Ch 0908 4] Vector : 00000000 [390h 0912 4] Polling Threshold Value : 00000000 [394h 0916 4] Polling Threshold Window : 00000000 [398h 0920 4] Error Threshold Value : 00000000 [39Ch 0924 4] Error Threshold Window : 00000000 [3A0h 0928 4] Error Status Block Length : 00001000 [3A4h 0932 12] Read Ack Register : [Generic Address Structure] [3A4h 0932 1] Space ID : 00 [SystemMemory] [3A5h 0933 1] Bit Width : 40 [3A6h 0934 1] Bit Offset : 00 [3A7h 0935 1] Encoded Access Width : 04 [QWord Access:64] [3A8h 0936 8] Address : 00000000785D00A0 [3B0h 0944 8] Read Ack Preserve : 00000000FFFFFFFE [3B8h 0952 8] Read Ack Write : 0000000000000001 ..................................................................................... (3) according to above table, the address that contains the physical address of a block of memory that holds the error status data for SEA notification error source is 0x00000000785D0040 (4) the address for SEA notification error source is 0x785d8108 (qemu) xp /1 0x00000000785D0040 00000000785d0040: 0x785d80b0 (5) check the content of generic error status block and generic error data entry (qemu) xp /100x 0x785d80b0 00000000785d80b0: 0x00000001 0x00000000 0x00000000 0x00000098 00000000785d80c0: 0x00000000 0xa5bc1114 0x4ede6f64 0x833e63b8 00000000785d80d0: 0xb1837ced 0x00000000 0x00000300 0x00000050 00000000785d80e0: 0x00000000 0x00000000 0x00000000 0x00000000 00000000785d80f0: 0x00000000 0x00000000 0x00000000 0x00000000 00000000785d8100: 0x00000000 0x00000000 0x00000000 0x00004002 00000000785d8110: 0x00000000 0x00000000 0x00000000 0x00001111 00000000785d8120: 0x00000000 0x00000000 0x00000000 0x00000000 00000000785d8130: 0x00000000 0x00000000 0x00000000 0x00000000 00000000785d8140: 0x00000000 0x00000000 0x00000000 0x00000000 00000000785d8150: 0x00000000 0x00000003 0x00000000 0x00000000 00000000785d8160: 0x00000000 0x00000000 0x00000000 0x00000000 00000000785d8170: 0x00000000 0x00000000 0x00000000 0x00000000 00000000785d8180: 0x00000000 0x00000000 0x00000000 0x00000000 00000000785d8190: 0x00000000 0x00000000 0x00000000 0x00000000 00000000785d81a0: 0x00000000 0x00000000 0x00000000 0x00000000 00000000785d81b0: 0x00000000 0x00000000 0x00000000 0x00000000 00000000785d81c0: 0x00000000 0x00000000 0x00000000 0x00000000 00000000785d81d0: 0x00000000 0x00000000 0x00000000 0x00000000 00000000785d81e0: 0x00000000 0x00000000 0x00000000 0x00000000 00000000785d81f0: 0x00000000 0x00000000 0x00000000 0x00000000 00000000785d8200: 0x00000000 0x00000000 0x00000000 0x00000000 00000000785d8210: 0x00000000 0x00000000 0x00000000 0x00000000 00000000785d8220: 0x00000000 0x00000000 0x00000000 0x00000000 00000000785d8230: 0x00000000 0x00000000 0x00000000 0x00000000 (6) check the OSPM's ACK value(for example SEA) /* Before OSPM acknowledges the error, check the ACK value */ (qemu) xp /1 0x00000000785D0098 00000000785d00f0: 0x00000000 /* After OSPM acknowledges the error, check the ACK value */ (qemu) xp /1 0x00000000785D0098 00000000785d00f0: 0x00000001 Dongjiu Geng (3): ACPI: add APEI/HEST/CPER structures and macros ACPI: Add APEI GHES Table Generation support ACPI: build and enable APEI GHES in the Makefile and configuration default-configs/arm-softmmu.mak | 1 + hw/acpi/Makefile.objs | 1 + hw/acpi/aml-build.c | 2 + hw/acpi/hest_ghes.c | 344 ++++++++++++++++++++++++++++++++++++++++ hw/arm/virt-acpi-build.c | 6 + include/hw/acpi/acpi-defs.h | 193 ++++++++++++++++++++++ include/hw/acpi/aml-build.h | 1 + include/hw/acpi/hest_ghes.h | 47 ++++++ 8 files changed, 595 insertions(+) create mode 100644 hw/acpi/hest_ghes.c create mode 100644 include/hw/acpi/hest_ghes.h -- 1.8.3.1 From MAILER-DAEMON Fri Aug 04 05:50:00 2017 Received: from list by lists.gnu.org with archive (Exim 4.71) id 1ddZF2-0006hg-Cl for mharc-qemu-arm@gnu.org; Fri, 04 Aug 2017 05:50:00 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:38678) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ddZEx-0006ZS-8O for qemu-arm@nongnu.org; Fri, 04 Aug 2017 05:49:58 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ddZEu-0004Ai-Dr for qemu-arm@nongnu.org; Fri, 04 Aug 2017 05:49:55 -0400 Received: from szxga02-in.huawei.com ([45.249.212.188]:4415) by eggs.gnu.org with esmtps (TLS1.0:RSA_ARCFOUR_SHA1:16) (Exim 4.71) (envelope-from ) id 1ddZEn-00045v-8H; Fri, 04 Aug 2017 05:49:46 -0400 Received: from 172.30.72.54 (EHLO DGGEML402-HUB.china.huawei.com) ([172.30.72.54]) by dggrg02-dlp.huawei.com (MOS 4.4.6-GA FastPath queued) with ESMTP id ASW04678; Fri, 04 Aug 2017 17:49:40 +0800 (CST) Received: from linux.huawei.com (10.67.187.203) by DGGEML402-HUB.china.huawei.com (10.3.17.38) with Microsoft SMTP Server id 14.3.301.0; Fri, 4 Aug 2017 17:49:31 +0800 From: Dongjiu Geng To: , , , , , , CC: , , , Date: Fri, 4 Aug 2017 18:09:15 +0800 Message-ID: <1501841356-6486-3-git-send-email-gengdongjiu@huawei.com> X-Mailer: git-send-email 1.7.7 In-Reply-To: <1501841356-6486-1-git-send-email-gengdongjiu@huawei.com> References: <1501841356-6486-1-git-send-email-gengdongjiu@huawei.com> MIME-Version: 1.0 Content-Type: text/plain X-Originating-IP: [10.67.187.203] X-CFilter-Loop: Reflected X-Mirapoint-Virus-RAPID-Raw: score=unknown(0), refid=str=0001.0A090201.59844336.002A, ss=1, re=0.000, recu=0.000, reip=0.000, cl=1, cld=1, fgs=0, ip=0.0.0.0, so=2014-11-16 11:51:01, dmn=2013-03-21 17:37:32 X-Mirapoint-Loop-Id: 6a2765d5378c0e48b4f49a8117f1e14f X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.4.x-2.6.x [generic] [fuzzy] X-Received-From: 45.249.212.188 Subject: [Qemu-arm] [PATCH v9 2/3] ACPI: Add APEI GHES Table Generation support X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 04 Aug 2017 09:49:58 -0000 This implements APEI GHES Table by passing the error CPER info to the guest via a fw_cfg_blob. After a CPER info is recorded, an SEA(Synchronous External Abort)/SEI(SError Interrupt) exception will be injected into the guest OS. Below is the table layout, the max number of error soure is 11, which is classified by notification type. etc/acpi/tables etc/hardware_errors ==================== ========================================== + +--------------------------+ +------------------+ | | HEST | | address | +--------------+ | +--------------------------+ | registers | | Error Status | | | GHES0 | | +----------------+ | Data Block 0 | | +--------------------------+ +--------->| |status_address0 |------------->| +------------+ | | ................. | | | +----------------+ | | CPER | | | error_status_address-----+-+ +------->| |status_address1 |----------+ | | CPER | | | ................. | | | +----------------+ | | | .... | | | read_ack_register--------+-+ | | ............. | | | | CPER | | | read_ack_preserve | | | +------------------+ | | +-+------------+ | | read_ack_write | | | +----->| |status_address10|--------+ | | Error Status | + +--------------------------+ | | | | +----------------+ | | | Data Block 1 | | | GHES1 | +-+-+----->| | ack_value0 | | +-->| +------------+ + +--------------------------+ | | | +----------------+ | | | CPER | | | ................. | | | +--->| | ack_value1 | | | | CPER | | | error_status_address-----+---+ | | | +----------------+ | | | .... | | | ................. | | | | | ............. | | | | CPER | | | read_ack_register--------+-----+-+ | +----------------+ | +-+------------+ | | read_ack_preserve | | +->| | ack_value10 | | | |.......... | | | read_ack_write | | | | +----------------+ | | +------------+ + +--------------------------| | | | | Error Status | | | ............... | | | | | Data Block 10| + +--------------------------+ | | +---->| +------------+ | | GHES10 | | | | | CPER | + +--------------------------+ | | | | CPER | | | ................. | | | | | .... | | | error_status_address-----+-----+ | | | CPER | | | ................. | | +-+------------+ | | read_ack_register--------+---------+ | | read_ack_preserve | | | read_ack_write | + +--------------------------+ For GHESv2 error source, the OSPM must acknowledges the error via Read Ack register. so user space must check the ack value to avoid read-write race condition. Signed-off-by: Dongjiu Geng --- thanks a lot Michael and Laszlo's review and comments: change since v8: (1) remove the ACK value address change since v6: (1) update the commit message change since v5: (1) move to GHESv2 error source from GHESv1, because we maily use the GHESv2 (2) add the GHESv2 error source layout in the comments (2) add the logic to read the ack value from OSPM to avoid read-write race condition (3) including header files "aml-build.h" and "hest_ghes.h" in this patch to make it reasonable (4) calculate the fw_cfg blob offsets that should be patched in more fine-grained steps, with multiple separate increments, using: - structure type names, - sizeof operators, - offsetof macros, - and possibly a separate comment for each offset increment. (5) remove page boundary refers to 4096 in the "bios_linker_loader_alloc" (6) using build_append_int_noprefix to avoid use pointer math, so that the code is easily readable (7) change memory section definition to array from QemuUUID (8) only enable SEA/SEI notification hardware error source to avoid guest OS ACPI driver probe warning change since v4: 1. fix email threading in this series is incorrect issue change since v3: 1. remove the unnecessary include for "hw/acpi/vmgenid.h" in hw/arm/virt-acpi-build.c 2. add conversion between LE and host-endian for the CPER record 3. handle the case that run out of the preallocated memory for the CPER record 4. change to use g_malloc0 instead of g_malloc 5. change block_reqr_size name to block_rer_size 6. change QEMU coding style, that is, the operator is at the end of the line. 7. drop the ERROR_STATUS_ADDRESS_OFFSET and GAS_ADDRESS_OFFSET macros (from the header file as well), and use the offsetof to replace it. 8. remove the init_aml_allocator() / free_aml_allocator(), calculate the needed size, and push that many bytes directly to "table_data". 9. take an "OVMF header probe suppressor" into account 10.corrct HEST and CPER value assigment, for example, correct the source_id for every error source, this identifier of source_id should be unique among all error sources; 11. create only one WRITE_POINTER command, for the base address of "etc/hardware_errors". This should be done outside of the loop.The base addresses of the individual error status data blocks should be calculated in ghes_update_guest(), based on the error source / notification type 12.correct the commit message lists error sources / notification types 0 through 10 (count=11 in total). 13.correct the size calculation for GHES_DATA_ADDR_FW_CFG_FILE 14.range-checked the value of "notify" before using it as an array subscript --- hw/acpi/aml-build.c | 2 + hw/acpi/hest_ghes.c | 344 ++++++++++++++++++++++++++++++++++++++++++++ hw/arm/virt-acpi-build.c | 6 + include/hw/acpi/aml-build.h | 1 + include/hw/acpi/hest_ghes.h | 47 ++++++ 5 files changed, 400 insertions(+) create mode 100644 hw/acpi/hest_ghes.c create mode 100644 include/hw/acpi/hest_ghes.h diff --git a/hw/acpi/aml-build.c b/hw/acpi/aml-build.c index c6f2032..802b98d 100644 --- a/hw/acpi/aml-build.c +++ b/hw/acpi/aml-build.c @@ -1560,6 +1560,7 @@ void acpi_build_tables_init(AcpiBuildTables *tables) tables->table_data = g_array_new(false, true /* clear */, 1); tables->tcpalog = g_array_new(false, true /* clear */, 1); tables->vmgenid = g_array_new(false, true /* clear */, 1); + tables->hardware_errors = g_array_new(false, true /* clear */, 1); tables->linker = bios_linker_loader_init(); } @@ -1570,6 +1571,7 @@ void acpi_build_tables_cleanup(AcpiBuildTables *tables, bool mfre) g_array_free(tables->table_data, true); g_array_free(tables->tcpalog, mfre); g_array_free(tables->vmgenid, mfre); + g_array_free(tables->hardware_errors, mfre); } /* Build rsdt table */ diff --git a/hw/acpi/hest_ghes.c b/hw/acpi/hest_ghes.c new file mode 100644 index 0000000..7e256f7 --- /dev/null +++ b/hw/acpi/hest_ghes.c @@ -0,0 +1,344 @@ +/* + * APEI GHES table Generation + * + * Copyright (C) 2017 huawei. + * + * Author: Dongjiu Geng + * + * This work is licensed under the terms of the GNU GPL, version 2 or later. + * See the COPYING file in the top-level directory. + * + */ + +#include "qemu/osdep.h" +#include "qmp-commands.h" +#include "hw/acpi/acpi.h" +#include "hw/acpi/aml-build.h" +#include "hw/acpi/hest_ghes.h" +#include "hw/nvram/fw_cfg.h" +#include "sysemu/sysemu.h" +#include "qemu/error-report.h" + +/* The structure that stands for the layout + * GHES_ERRORS_FW_CFG_FILE fw_cfg blob + * + * etc/hardware_errors + * ========================================== + * +------------------+ + * | address | +--------------+ + * | registers | | Error Status | + * | +----------------+ | Data Block 0 | + * | |status_address0 |------------->| +------------+ + * | +----------------+ | | CPER | + * | |status_address1 |----------+ | | CPER | + * | +----------------+ | | | .... | + * | |............. | | | | CPER | + * | +----------------+ | | +------------+ + * | |status_address10|-----+ | | Error Status | + * | +----------------+ | | | Data Block 1 | + * | |ack_value0 | | +-->| +------------+ + * | +----------------+ | | | CPER | + * | |ack_value1 | | | | CPER | + * | +----------------+ | | | .... | + * | | ............. | | | | CPER | + * | +----------------+ | +-+------------+ + * | |ack_value10 | | | |.......... | + * | +----------------+ | | +------------+ + * | | Error Status | + * | | Data Block10 | + * +------->+------------+ + * | | CPER | + * | | CPER | + * | | .... | + * | | CPER | + * +-+------------+ + */ +struct hardware_errors_buffer { + /* Generic Error Status Block register */ + uint64_t gesb_address[GHES_ACPI_HEST_NOTIFY_RESERVED]; + uint64_t ack_value[GHES_ACPI_HEST_NOTIFY_RESERVED]; + char gesb[GHES_MAX_RAW_DATA_LENGTH][GHES_ACPI_HEST_NOTIFY_RESERVED]; +}; + +static int ghes_record_cper(uint64_t error_block_address, + uint64_t error_physical_addr) +{ + AcpiGenericErrorStatus block; + AcpiGenericErrorData *gdata; + UefiCperSecMemErr *mem_err; + uint64_t current_block_length; + unsigned char *buffer; + /* memory section */ + char mem_section_id_le[] = {0x14, 0x11, 0xBC, 0xA5, 0x64, 0x6F, 0xDE, + 0x4E, 0xB8, 0x63, 0x3E, 0x83, 0xED, 0x7C, + 0x83, 0xB1}; + + cpu_physical_memory_read(error_block_address, &block, + sizeof(AcpiGenericErrorStatus)); + + /* Get the current generic error status block length */ + current_block_length = sizeof(AcpiGenericErrorStatus) + + le32_to_cpu(block.data_length); + + /* If the Generic Error Status Block is NULL, update + * the block header + */ + if (!block.block_status) { + block.block_status = ACPI_GEBS_UNCORRECTABLE; + block.error_severity = ACPI_CPER_SEV_RECOVERABLE; + } + + block.data_length += cpu_to_le32(sizeof(AcpiGenericErrorData)); + block.data_length += cpu_to_le32(sizeof(UefiCperSecMemErr)); + + /* check whether it runs out of the preallocated memory */ + if ((le32_to_cpu(block.data_length) + sizeof(AcpiGenericErrorStatus)) > + GHES_MAX_RAW_DATA_LENGTH) { + error_report("Record CPER out of boundary!!!"); + return GHES_CPER_FAIL; + } + + /* Write back the Generic Error Status Block to guest memory */ + cpu_physical_memory_write(error_block_address, &block, + sizeof(AcpiGenericErrorStatus)); + + /* Fill in Generic Error Data Entry */ + buffer = g_malloc0(sizeof(AcpiGenericErrorData) + + sizeof(UefiCperSecMemErr)); + + + memset(buffer, 0, sizeof(AcpiGenericErrorData) + sizeof(UefiCperSecMemErr)); + gdata = (AcpiGenericErrorData *)buffer; + + /* Memory section */ + memcpy(&(gdata->section_type_le), &mem_section_id_le, + sizeof(mem_section_id_le)); + + /* error severity is recoverable */ + gdata->error_severity = ACPI_CPER_SEV_RECOVERABLE; + gdata->revision = 0x300; /* the revision number is 0x300 */ + gdata->error_data_length = cpu_to_le32(sizeof(UefiCperSecMemErr)); + + mem_err = (UefiCperSecMemErr *) (gdata + 1); + + /* User space only handle the memory section CPER */ + + /* Hard code to Multi-bit ECC error */ + mem_err->validation_bits |= cpu_to_le32(UEFI_CPER_MEM_VALID_ERROR_TYPE); + mem_err->error_type = cpu_to_le32(UEFI_CPER_MEM_ERROR_TYPE_MULTI_ECC); + + /* Record the physical address at which the memory error occurred */ + mem_err->validation_bits |= cpu_to_le32(UEFI_CPER_MEM_VALID_PA); + mem_err->physical_addr = cpu_to_le32(error_physical_addr); + + /* Write back the Generic Error Data Entry to guest memory */ + cpu_physical_memory_write(error_block_address + current_block_length, + buffer, sizeof(AcpiGenericErrorData) + sizeof(UefiCperSecMemErr)); + + g_free(buffer); + return GHES_CPER_OK; +} + +static void +build_address(GArray *table_data, BIOSLinker *linker, + uint32_t dst_patched_offset, uint32_t src_offset, + uint8_t address_space_id , uint8_t register_bit_width, + uint8_t register_bit_offset, uint8_t access_size) +{ + uint32_t address_size = sizeof(struct AcpiGenericAddress) - + offsetof(struct AcpiGenericAddress, address); + + /* Address space */ + build_append_int_noprefix(table_data, address_space_id, 1); + /* register bit width */ + build_append_int_noprefix(table_data, register_bit_width, 1); + /* register bit offset */ + build_append_int_noprefix(table_data, register_bit_offset, 1); + /* access size */ + build_append_int_noprefix(table_data, access_size, 1); + acpi_data_push(table_data, address_size); + + /* Patch address of ERRORS fw_cfg blob into the TABLE fw_cfg blob so OSPM + * can retrieve and read it. the address size is 64 bits. + */ + bios_linker_loader_add_pointer(linker, + ACPI_BUILD_TABLE_FILE, dst_patched_offset, sizeof(uint64_t), + GHES_ERRORS_FW_CFG_FILE, src_offset); +} + +void ghes_build_acpi(GArray *table_data, GArray *hardware_error, + BIOSLinker *linker) +{ + uint32_t ghes_start = table_data->len; + uint32_t address_size, error_status_address_offset; + uint32_t read_ack_register_offset, i; + + address_size = sizeof(struct AcpiGenericAddress) - + offsetof(struct AcpiGenericAddress, address); + + error_status_address_offset = ghes_start + + sizeof(AcpiHardwareErrorSourceTable) + + offsetof(AcpiGenericHardwareErrorSourceV2, error_status_address) + + offsetof(struct AcpiGenericAddress, address); + + read_ack_register_offset = ghes_start + + sizeof(AcpiHardwareErrorSourceTable) + + offsetof(AcpiGenericHardwareErrorSourceV2, read_ack_register) + + offsetof(struct AcpiGenericAddress, address); + + acpi_data_push(hardware_error, + offsetof(struct hardware_errors_buffer, ack_value)); + for (i = 0; i < GHES_ACPI_HEST_NOTIFY_RESERVED; i++) + /* Initialize read ack register */ + build_append_int_noprefix((void *)hardware_error, 1, 8); + + /* Reserved the total size for ERRORS fw_cfg blob + */ + acpi_data_push(hardware_error, sizeof(struct hardware_errors_buffer)); + + /* Allocate guest memory for the Data fw_cfg blob */ + bios_linker_loader_alloc(linker, GHES_ERRORS_FW_CFG_FILE, hardware_error, + 1, false); + /* Reserve table header size */ + acpi_data_push(table_data, sizeof(AcpiTableHeader)); + + build_append_int_noprefix(table_data, GHES_ACPI_HEST_NOTIFY_RESERVED, 4); + + for (i = 0; i < GHES_ACPI_HEST_NOTIFY_RESERVED; i++) { + build_append_int_noprefix(table_data, + ACPI_HEST_SOURCE_GENERIC_ERROR_V2, 2); /* type */ + /* source id */ + build_append_int_noprefix(table_data, cpu_to_le16(i), 2); + /* related source id */ + build_append_int_noprefix(table_data, 0xffff, 2); + build_append_int_noprefix(table_data, 0, 1); /* flags */ + + /* Currently only enable SEA and SEI notification type to avoid the + * kernel warning, reserve the space for other notification error source + */ + if (i == ACPI_HEST_NOTIFY_SEA || i == ACPI_HEST_NOTIFY_SEI) { + build_append_int_noprefix(table_data, 1, 1); /* enabled */ + } else { + build_append_int_noprefix(table_data, 0, 1); /* enabled */ + } + + /* The number of error status block per generic hardware error source */ + build_append_int_noprefix(table_data, 1, 4); + /* Max sections per record */ + build_append_int_noprefix(table_data, 1, 4); + /* Max raw data length */ + build_append_int_noprefix(table_data, GHES_MAX_RAW_DATA_LENGTH, 4); + + /* Build error status address*/ + build_address(table_data, linker, error_status_address_offset + i * + sizeof(AcpiGenericHardwareErrorSourceV2), i * address_size, + AML_SYSTEM_MEMORY, 0x40, 0, 4 /* QWord access */); + + /* Hardware error notification structure */ + build_append_int_noprefix(table_data, i, 1); /* type */ + /* length */ + build_append_int_noprefix(table_data, sizeof(AcpiHestNotify), 1); + build_append_int_noprefix(table_data, 0, 26); + + /* Error Status Block Length */ + build_append_int_noprefix(table_data, + cpu_to_le32(GHES_MAX_RAW_DATA_LENGTH), 4); + + /* Build read ack register */ + build_address(table_data, linker, read_ack_register_offset + i * + sizeof(AcpiGenericHardwareErrorSourceV2), + offsetof(struct hardware_errors_buffer, ack_value) + + i * address_size, AML_SYSTEM_MEMORY, 0x40, 0, + 4 /* QWord access */); + + /* Read ack preserve */ + build_append_int_noprefix(table_data, cpu_to_le64(0xfffffffe), 8); + + /* Read ack write */ + build_append_int_noprefix(table_data, cpu_to_le64(0x1), 8); + } + + for (i = 0; i < GHES_ACPI_HEST_NOTIFY_RESERVED; i++) + /* Patch address of generic error status block into + * the address register so OSPM can retrieve and read it. + */ + bios_linker_loader_add_pointer(linker, + GHES_ERRORS_FW_CFG_FILE, address_size * i, address_size, + GHES_ERRORS_FW_CFG_FILE, + offsetof(struct hardware_errors_buffer, gesb) + + i * GHES_MAX_RAW_DATA_LENGTH); + + /* Patch address of ERRORS fw_cfg blob into the ADDR fw_cfg blob + * so QEMU can write the ERRORS there. The address is expected to be + * < 4GB, but write 64 bits anyway. + */ + bios_linker_loader_write_pointer(linker, GHES_DATA_ADDR_FW_CFG_FILE, + 0, address_size, GHES_ERRORS_FW_CFG_FILE, + offsetof(struct hardware_errors_buffer, gesb)); + + build_header(linker, table_data, + (void *)(table_data->data + ghes_start), "HEST", + table_data->len - ghes_start, 1, NULL, "GHES"); +} + +static GhesState ges; +void ghes_add_fw_cfg(FWCfgState *s, GArray *hardware_error) +{ + + size_t request_block_size = sizeof(uint64_t) + GHES_MAX_RAW_DATA_LENGTH; + size_t size = GHES_ACPI_HEST_NOTIFY_RESERVED * request_block_size; + + /* Create a read-only fw_cfg file for GHES */ + fw_cfg_add_file(s, GHES_ERRORS_FW_CFG_FILE, hardware_error->data, + size); + /* Create a read-write fw_cfg file for Address */ + fw_cfg_add_file_callback(s, GHES_DATA_ADDR_FW_CFG_FILE, NULL, NULL, + &ges.ghes_addr_le, sizeof(ges.ghes_addr_le), false); +} + +bool ghes_update_guest(uint32_t notify, uint64_t physical_address) +{ + uint64_t error_block_addr; + uint64_t ack_value_addr, ack_value = 0; + int loop = 0, ack_value_size; + bool ret = GHES_CPER_FAIL; + + ack_value_size = (offsetof(struct hardware_errors_buffer, gesb) - + offsetof(struct hardware_errors_buffer, ack_value)) / + GHES_ACPI_HEST_NOTIFY_RESERVED; +retry: + if (physical_address && notify < GHES_ACPI_HEST_NOTIFY_RESERVED) { + error_block_addr = ges.ghes_addr_le + notify * GHES_MAX_RAW_DATA_LENGTH; + error_block_addr = le32_to_cpu(error_block_addr); + + ack_value_addr = ges.ghes_addr_le - + (GHES_ACPI_HEST_NOTIFY_RESERVED - notify) * ack_value_size; + cpu_physical_memory_read(ack_value_addr, &ack_value, ack_value_size); + if (!ack_value) { + if (loop < 3) { + usleep(100 * 1000); + loop++; + goto retry; + } else { + error_report("Last time OSPM does not acknowledge the error," + " record CPER failed this time, set the ack value to" + " avoid blocking next time CPER record! exit"); + ack_value = 1; + cpu_physical_memory_write(ack_value_addr, + &ack_value, ack_value_size); + return ret; + } + } else { + /* A zero value in ghes_addr means that BIOS has not yet written + * the address + */ + if (error_block_addr) { + ack_value = 0; + cpu_physical_memory_write(ack_value_addr, + &ack_value, ack_value_size); + ret = ghes_record_cper(error_block_addr, physical_address); + } + } + } + return ret; +} diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c index 0835e59..5c97016 100644 --- a/hw/arm/virt-acpi-build.c +++ b/hw/arm/virt-acpi-build.c @@ -45,6 +45,7 @@ #include "hw/arm/virt.h" #include "sysemu/numa.h" #include "kvm_arm.h" +#include "hw/acpi/hest_ghes.h" #define ARM_SPI_BASE 32 #define ACPI_POWER_BUTTON_DEVICE "PWRB" @@ -778,6 +779,9 @@ void virt_acpi_build(VirtMachineState *vms, AcpiBuildTables *tables) acpi_add_table(table_offsets, tables_blob); build_spcr(tables_blob, tables->linker, vms); + acpi_add_table(table_offsets, tables_blob); + ghes_build_acpi(tables_blob, tables->hardware_errors, tables->linker); + if (nb_numa_nodes > 0) { acpi_add_table(table_offsets, tables_blob); build_srat(tables_blob, tables->linker, vms); @@ -890,6 +894,8 @@ void virt_acpi_setup(VirtMachineState *vms) fw_cfg_add_file(vms->fw_cfg, ACPI_BUILD_TPMLOG_FILE, tables.tcpalog->data, acpi_data_len(tables.tcpalog)); + ghes_add_fw_cfg(vms->fw_cfg, tables.hardware_errors); + build_state->rsdp_mr = acpi_add_rom_blob(build_state, tables.rsdp, ACPI_BUILD_RSDP_FILE, 0); diff --git a/include/hw/acpi/aml-build.h b/include/hw/acpi/aml-build.h index 00c21f1..c1d15b3 100644 --- a/include/hw/acpi/aml-build.h +++ b/include/hw/acpi/aml-build.h @@ -211,6 +211,7 @@ struct AcpiBuildTables { GArray *rsdp; GArray *tcpalog; GArray *vmgenid; + GArray *hardware_errors; BIOSLinker *linker; } AcpiBuildTables; diff --git a/include/hw/acpi/hest_ghes.h b/include/hw/acpi/hest_ghes.h new file mode 100644 index 0000000..0772756 --- /dev/null +++ b/include/hw/acpi/hest_ghes.h @@ -0,0 +1,47 @@ +/* + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Authors: + * Dongjiu Geng + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#ifndef ACPI_GHES_H +#define ACPI_GHES_H + +#include "hw/acpi/bios-linker-loader.h" + +#define GHES_ERRORS_FW_CFG_FILE "etc/hardware_errors" +#define GHES_DATA_ADDR_FW_CFG_FILE "etc/hardware_errors_addr" + +#define GHES_GAS_ADDRESS_OFFSET 4 +#define GHES_ERROR_STATUS_ADDRESS_OFFSET 20 +#define GHES_NOTIFICATION_STRUCTURE 32 + +#define GHES_CPER_OK 1 +#define GHES_CPER_FAIL 0 + +#define GHES_ACPI_HEST_NOTIFY_RESERVED 11 +/* The max size in Bytes for one error block */ +#define GHES_MAX_RAW_DATA_LENGTH 0x1000 + + +typedef struct GhesState { + uint64_t ghes_addr_le; +} GhesState; + +void ghes_build_acpi(GArray *table_data, GArray *hardware_error, + BIOSLinker *linker); +void ghes_add_fw_cfg(FWCfgState *s, GArray *hardware_errors); +bool ghes_update_guest(uint32_t notify, uint64_t error_physical_addr); +#endif -- 1.8.3.1 From MAILER-DAEMON Fri Aug 04 05:51:50 2017 Received: from list by lists.gnu.org with archive (Exim 4.71) id 1ddZGo-0008Bq-7h for mharc-qemu-arm@gnu.org; Fri, 04 Aug 2017 05:51:50 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:39338) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ddZGl-00089l-73 for qemu-arm@nongnu.org; Fri, 04 Aug 2017 05:51:48 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ddZGk-0005bl-Fr for qemu-arm@nongnu.org; Fri, 04 Aug 2017 05:51:47 -0400 Received: from mail-wm0-x22b.google.com ([2a00:1450:400c:c09::22b]:34816) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ddZGk-0005bD-8j for qemu-arm@nongnu.org; Fri, 04 Aug 2017 05:51:46 -0400 Received: by mail-wm0-x22b.google.com with SMTP id m85so15385691wma.0 for ; Fri, 04 Aug 2017 02:51:46 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:in-reply-to:references:from:date:message-id:subject:to :cc; bh=3Kj1LLb0YQb03/w+zMdJmXB1I6ZYr2cM2kNuDiJGtBw=; b=T2JKQj4gRCnj5BFMFu2BYhzyybd5N/CE+L6X49i7OvaMSVM11tq/asDc5cFiq9yDR/ DxFhZ7UO1ZruLHQ+DJbsKHOwYTffZ23jx/4PzFGHSfVrLV8yGslvK97mIHFMV80UXkHr f0zCYmThCsZdgR3Hxh8fL5MqopRFlzDCzjvEA= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:in-reply-to:references:from:date :message-id:subject:to:cc; bh=3Kj1LLb0YQb03/w+zMdJmXB1I6ZYr2cM2kNuDiJGtBw=; b=GoR7rSfqwP6aDx0W02x5rJgVjDQ8A7SmB6esDbgELo8CHInVsDiE1HUSyMBf034ZOc SfAx0SywU/5L5eVrI0G7yUaFY2fKkL1YHmlNEy67zhLJGf13/eUpyI7lKnM2dwGgvVU/ dPfJ96alKrEv5q6PRaNQemovAcMsA6RfecmMAF7VQLjXN6IGRTXTWHhMK1s6bnbsddfV EhNGaC0pAqK54E0i4OL5OrCks1DL8Zf4Y+fo9Y7IGD5CjyXYxOrbF/VFTwzm39vnHpNQ bwpKG/QH5ikpL63dfu/8NCkCl/nTgc8CWij8nKEn/R7bG0sd2IHmVnw/9TwfmFPlqV9U fKgw== X-Gm-Message-State: AHYfb5iGa6NnVldINOXAKuVSFxeuW1HKkZQmLRJuWAIvjhRlzsXlR4QA /qZLhTcxOf15m8meVW/5zwhw5BMnGkh6 X-Received: by 10.28.105.28 with SMTP id e28mr894891wmc.42.1501840304998; Fri, 04 Aug 2017 02:51:44 -0700 (PDT) MIME-Version: 1.0 Received: by 10.223.134.54 with HTTP; Fri, 4 Aug 2017 02:51:24 -0700 (PDT) In-Reply-To: <91f1649d-ffcf-85c5-b83b-644ad1875fcd@twiddle.net> References: <1501692241-23310-1-git-send-email-peter.maydell@linaro.org> <1501692241-23310-11-git-send-email-peter.maydell@linaro.org> <91f1649d-ffcf-85c5-b83b-644ad1875fcd@twiddle.net> From: Peter Maydell Date: Fri, 4 Aug 2017 10:51:24 +0100 Message-ID: To: Richard Henderson Cc: qemu-arm , QEMU Developers , "patches@linaro.org" Content-Type: text/plain; charset="UTF-8" X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:400c:c09::22b Subject: Re: [Qemu-arm] [Qemu-devel] [PATCH 10/15] target/arm: Don't use cpsr_write/cpsr_read to transfer M profile XPSR X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 04 Aug 2017 09:51:48 -0000 On 3 August 2017 at 23:13, Richard Henderson wrote: > On 08/02/2017 09:43 AM, Peter Maydell wrote: >> + if (val & XPSR_EXCP) { >> + /* This is a CPSR format value from an older QEMU. (We can tell >> + * because values transferred in XPSR format always have zero >> + * for the EXCP field, and CPSR format will always have bit 4 >> + * set in CPSR_M.) Rearrange it into XPSR format. The significant >> + * differences are that the T bit is not in the same place, the >> + * primask/faultmask info may be in the CPSR I and F bits, and >> + * we do not want the mode bits. >> + */ >> + uint32_t newval = val; >> + >> + newval &= (CPSR_NZCV | CPSR_Q | CPSR_IT | CPSR_GE); >> + if (val & CPSR_T) { >> + newval |= XPSR_T; >> + } >> + /* If the I or F bits are set then this is a migration from >> + * an old QEMU which still stored the M profile FAULTMASK >> + * and PRIMASK in env->daif. For a new QEMU, the data is >> + * transferred using the vmstate_m_faultmask_primask subsection. >> + */ > > The second comment seems sort of redundant with the first now. I felt that the migration-compat stuff was sufficiently subtle that it was worth retaining the second detailed comment as well as the brief summary in the new first comment. thanks -- PMM From MAILER-DAEMON Fri Aug 04 06:02:59 2017 Received: from list by lists.gnu.org with archive (Exim 4.71) id 1ddZRb-0000vp-Cz for mharc-qemu-arm@gnu.org; Fri, 04 Aug 2017 06:02:59 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:42445) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ddZRY-0000tD-Fq for qemu-arm@nongnu.org; Fri, 04 Aug 2017 06:02:57 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ddZRX-0003p4-G5 for qemu-arm@nongnu.org; Fri, 04 Aug 2017 06:02:56 -0400 Received: from szxga03-in.huawei.com ([45.249.212.189]:4351) by eggs.gnu.org with esmtps (TLS1.0:RSA_ARCFOUR_SHA1:16) (Exim 4.71) (envelope-from ) id 1ddZRQ-0003iz-Sn; Fri, 04 Aug 2017 06:02:49 -0400 Received: from 172.30.72.56 (EHLO DGGEML402-HUB.china.huawei.com) ([172.30.72.56]) by dggrg03-dlp.huawei.com (MOS 4.4.6-GA FastPath queued) with ESMTP id ASX06414; Fri, 04 Aug 2017 18:02:44 +0800 (CST) Received: from linux.huawei.com (10.67.187.203) by DGGEML402-HUB.china.huawei.com (10.3.17.38) with Microsoft SMTP Server id 14.3.301.0; Fri, 4 Aug 2017 18:02:33 +0800 From: Dongjiu Geng To: , , , , , , CC: , , , Date: Fri, 4 Aug 2017 18:22:18 +0800 Message-ID: <1501842138-17606-4-git-send-email-gengdongjiu@huawei.com> X-Mailer: git-send-email 1.7.7 In-Reply-To: <1501842138-17606-1-git-send-email-gengdongjiu@huawei.com> References: <1501842138-17606-1-git-send-email-gengdongjiu@huawei.com> MIME-Version: 1.0 Content-Type: text/plain X-Originating-IP: [10.67.187.203] X-CFilter-Loop: Reflected X-Mirapoint-Virus-RAPID-Raw: score=unknown(0), refid=str=0001.0A090204.59844646.0011, ss=1, re=0.000, recu=0.000, reip=0.000, cl=1, cld=1, fgs=0, ip=0.0.0.0, so=2014-11-16 11:51:01, dmn=2013-03-21 17:37:32 X-Mirapoint-Loop-Id: 3abe503b2868db3fe2c2e72148dc7042 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.4.x-2.6.x [generic] [fuzzy] X-Received-From: 45.249.212.189 Subject: [Qemu-arm] [PATCH v10 3/3] ACPI: build and enable APEI GHES in the Makefile and configuration X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 04 Aug 2017 10:02:57 -0000 Add CONFIG_ACPI_APEI configuration in the Makefile and enable it in the arm-softmmu.mak Signed-off-by: Dongjiu Geng --- thanks a lot Michael and Laszlo's review and comments: change since v5: (1) no change change since v4: (1) fix email threading in this series is incorrect issue change since v3: (1) change name to "CONFIG_ACPI_APEI" from CONFIG_ACPI_APEI_GENERATION --- default-configs/arm-softmmu.mak | 1 + hw/acpi/Makefile.objs | 1 + 2 files changed, 2 insertions(+) diff --git a/default-configs/arm-softmmu.mak b/default-configs/arm-softmmu.mak index 1e3bd2b..ee6f5fc 100644 --- a/default-configs/arm-softmmu.mak +++ b/default-configs/arm-softmmu.mak @@ -121,3 +121,4 @@ CONFIG_ACPI=y CONFIG_SMBIOS=y CONFIG_ASPEED_SOC=y CONFIG_GPIO_KEY=y +CONFIG_ACPI_APEI=y diff --git a/hw/acpi/Makefile.objs b/hw/acpi/Makefile.objs index 11c35bc..bafb148 100644 --- a/hw/acpi/Makefile.objs +++ b/hw/acpi/Makefile.objs @@ -6,6 +6,7 @@ common-obj-$(CONFIG_ACPI_MEMORY_HOTPLUG) += memory_hotplug.o common-obj-$(CONFIG_ACPI_CPU_HOTPLUG) += cpu.o common-obj-$(CONFIG_ACPI_NVDIMM) += nvdimm.o common-obj-$(CONFIG_ACPI_VMGENID) += vmgenid.o +common-obj-$(CONFIG_ACPI_APEI) += hest_ghes.o common-obj-$(call lnot,$(CONFIG_ACPI_X86)) += acpi-stub.o common-obj-y += acpi_interface.o -- 1.8.3.1 From MAILER-DAEMON Fri Aug 04 06:03:02 2017 Received: from list by lists.gnu.org with archive (Exim 4.71) id 1ddZRe-0000yw-IA for mharc-qemu-arm@gnu.org; Fri, 04 Aug 2017 06:03:02 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:42464) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ddZRa-0000uu-DT for qemu-arm@nongnu.org; Fri, 04 Aug 2017 06:03:00 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ddZRY-0003pf-Jt for qemu-arm@nongnu.org; Fri, 04 Aug 2017 06:02:58 -0400 Received: from szxga03-in.huawei.com ([45.249.212.189]:4349) by eggs.gnu.org with esmtps (TLS1.0:RSA_ARCFOUR_SHA1:16) (Exim 4.71) (envelope-from ) id 1ddZRQ-0003ic-QC; Fri, 04 Aug 2017 06:02:49 -0400 Received: from 172.30.72.56 (EHLO DGGEML402-HUB.china.huawei.com) ([172.30.72.56]) by dggrg03-dlp.huawei.com (MOS 4.4.6-GA FastPath queued) with ESMTP id ASX06407; Fri, 04 Aug 2017 18:02:44 +0800 (CST) Received: from linux.huawei.com (10.67.187.203) by DGGEML402-HUB.china.huawei.com (10.3.17.38) with Microsoft SMTP Server id 14.3.301.0; Fri, 4 Aug 2017 18:02:32 +0800 From: Dongjiu Geng To: , , , , , , CC: , , , Date: Fri, 4 Aug 2017 18:22:15 +0800 Message-ID: <1501842138-17606-1-git-send-email-gengdongjiu@huawei.com> X-Mailer: git-send-email 1.7.7 MIME-Version: 1.0 Content-Type: text/plain X-Originating-IP: [10.67.187.203] X-CFilter-Loop: Reflected X-Mirapoint-Virus-RAPID-Raw: score=unknown(0), refid=str=0001.0A090201.59844644.0185, ss=1, re=0.000, recu=0.000, reip=0.000, cl=1, cld=1, fgs=0, ip=0.0.0.0, so=2014-11-16 11:51:01, dmn=2013-03-21 17:37:32 X-Mirapoint-Loop-Id: 43e03f9907b223421f82c625b7a10854 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.4.x-2.6.x [generic] [fuzzy] X-Received-From: 45.249.212.189 Subject: [Qemu-arm] [PATCH v10 0/3] Generate APEI GHES table and dynamically record CPER X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 04 Aug 2017 10:03:00 -0000 In the armv8 platform, the mainly hardware error source are ARMv8 SEA/SEI/GSIV. For the ARMv8 SEA/SEI, the KVM or host kernel will signal SIGBUS or use other interface to notify user space, such as Qemu. After Qemu gets the notification, it will record the CPER and inject the SEA/SEI to KVM. this series of patches will generate APEI table when guest OS boot up, and dynamically record CPER for the guest OS about the generic hardware errors, currently the userspace only handle the memory section hardware errors. Before Qemu record the CPER, it needs to check the ACK value written by the guest OS to avoid read-write race condition. Below is the APEI/GHESV2/CPER table layout, the max number of error soure is 11, which is classified by notification type, now only enable the SEA/SEI notification type error source. etc/acpi/tables etc/hardware_errors ==================== ========================================== + +--------------------------+ +------------------+ | | HEST | | address | +--------------+ | +--------------------------+ | registers | | Error Status | | | GHES0 | | +----------------+ | Data Block 0 | | +--------------------------+ +--------->| |status_address0 |------------->| +------------+ | | ................. | | | +----------------+ | | CPER | | | error_status_address-----+-+ +------->| |status_address1 |----------+ | | CPER | | | ................. | | | +----------------+ | | | .... | | | read_ack_register--------+-+ | | ............. | | | | CPER | | | read_ack_preserve | | | +------------------+ | | +------------+ | | read_ack_write | | | +----->| |status_address10|--------+ | | Error Status | + +--------------------------+ | | | | +----------------+ | | | Data Block 1 | | | GHES1 | +-+-+----->| | ack_value0 | | +-->| +------------+ + +--------------------------+ | | | +----------------+ | | | CPER | | | ................. | | | +--->| | ack_value1 | | | | CPER | | | error_status_address-----+---+ | | | +----------------+ | | | .... | | | ................. | | | | | ............. | | | | CPER | | | read_ack_register--------+-----+-+ | +----------------+ | +-+------------+ | | read_ack_preserve | | +->| | ack_value10 | | | |.......... | | | read_ack_write | | | | +----------------+ | | +------------+ + +--------------------------| | | | | Error Status | | | ............... | | | | | Data Block 10| + +--------------------------+ | | +---->| +------------+ | | GHES10 | | | | | CPER | + +--------------------------+ | | | | CPER | | | ................. | | | | | .... | | | error_status_address-----+-----+ | | | CPER | | | ................. | | +-+------------+ | | read_ack_register--------+---------+ | | read_ack_preserve | | | read_ack_write | + +--------------------------+ After injecting a SEA/SEI ghes error, the gueset OS kernel log will be shown as below: [ 142.911115] {1}[Hardware Error]: Hardware error from APEI Generic Hardware Error Source: 8 [ 142.913141] {1}[Hardware Error]: event severity: recoverable [ 142.914498] {1}[Hardware Error]: Error 0, type: recoverable [ 142.915851] {1}[Hardware Error]: section_type: memory error [ 142.917163] {1}[Hardware Error]: physical_address: 0x0000000000001111 [ 142.918792] {1}[Hardware Error]: error_type: 3, multi-bit ECC how to test: 1. In the guest OS, use this command to dump the APEI table: "iasl -p ./HEST -d /sys/firmware/acpi/tables/HEST" 2. And find the address for the generic error status block according to the notification type 3. then find the CPER record through the generic error status block. For example(notification type is SEA): (1) root@genericarmv8:~# iasl -p ./HEST -d /sys/firmware/acpi/tables/HEST (2) root@genericarmv8:~# cat HEST.dsl /* * Intel ACPI Component Architecture * AML/ASL+ Disassembler version 20170728 (64-bit version) * Copyright (c) 2000 - 2017 Intel Corporation * * Disassembly of /sys/firmware/acpi/tables/HEST, Mon Sep 5 07:59:17 2016 * * ACPI Data Table [HEST] * * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue */ .................................................................................. [308h 0776 2] Subtable Type : 000A [Generic Hardware Error Source V2] [30Ah 0778 2] Source Id : 0008 [30Ch 0780 2] Related Source Id : FFFF [30Eh 0782 1] Reserved : 00 [30Fh 0783 1] Enabled : 01 [310h 0784 4] Records To Preallocate : 00000001 [314h 0788 4] Max Sections Per Record : 00000001 [318h 0792 4] Max Raw Data Length : 00001000 [31Ch 0796 12] Error Status Address : [Generic Address Structure] [31Ch 0796 1] Space ID : 00 [SystemMemory] [31Dh 0797 1] Bit Width : 40 [31Eh 0798 1] Bit Offset : 00 [31Fh 0799 1] Encoded Access Width : 04 [QWord Access:64] [320h 0800 8] Address : 00000000785D0040 [328h 0808 28] Notify : [Hardware Error Notification Structure] [328h 0808 1] Notify Type : 08 [SEA] [329h 0809 1] Notify Length : 1C [32Ah 0810 2] Configuration Write Enable : 0000 [32Ch 0812 4] PollInterval : 00000000 [330h 0816 4] Vector : 00000000 [334h 0820 4] Polling Threshold Value : 00000000 [338h 0824 4] Polling Threshold Window : 00000000 [33Ch 0828 4] Error Threshold Value : 00000000 [340h 0832 4] Error Threshold Window : 00000000 [344h 0836 4] Error Status Block Length : 00001000 [348h 0840 12] Read Ack Register : [Generic Address Structure] [348h 0840 1] Space ID : 00 [SystemMemory] [349h 0841 1] Bit Width : 40 [34Ah 0842 1] Bit Offset : 00 [34Bh 0843 1] Encoded Access Width : 04 [QWord Access:64] [34Ch 0844 8] Address : 00000000785D0098 [354h 0852 8] Read Ack Preserve : 00000000FFFFFFFE [35Ch 0860 8] Read Ack Write : 0000000000000001 [364h 0868 2] Subtable Type : 000A [Generic Hardware Error Source V2] [366h 0870 2] Source Id : 0009 [368h 0872 2] Related Source Id : FFFF [36Ah 0874 1] Reserved : 00 [36Bh 0875 1] Enabled : 01 [36Ch 0876 4] Records To Preallocate : 00000001 [370h 0880 4] Max Sections Per Record : 00000001 [374h 0884 4] Max Raw Data Length : 00001000 [378h 0888 12] Error Status Address : [Generic Address Structure] [378h 0888 1] Space ID : 00 [SystemMemory] [379h 0889 1] Bit Width : 40 [37Ah 0890 1] Bit Offset : 00 [37Bh 0891 1] Encoded Access Width : 04 [QWord Access:64] [37Ch 0892 8] Address : 00000000785D0048 [384h 0900 28] Notify : [Hardware Error Notification Structure] [384h 0900 1] Notify Type : 09 [SEI] [385h 0901 1] Notify Length : 1C [386h 0902 2] Configuration Write Enable : 0000 [388h 0904 4] PollInterval : 00000000 [38Ch 0908 4] Vector : 00000000 [390h 0912 4] Polling Threshold Value : 00000000 [394h 0916 4] Polling Threshold Window : 00000000 [398h 0920 4] Error Threshold Value : 00000000 [39Ch 0924 4] Error Threshold Window : 00000000 [3A0h 0928 4] Error Status Block Length : 00001000 [3A4h 0932 12] Read Ack Register : [Generic Address Structure] [3A4h 0932 1] Space ID : 00 [SystemMemory] [3A5h 0933 1] Bit Width : 40 [3A6h 0934 1] Bit Offset : 00 [3A7h 0935 1] Encoded Access Width : 04 [QWord Access:64] [3A8h 0936 8] Address : 00000000785D00A0 [3B0h 0944 8] Read Ack Preserve : 00000000FFFFFFFE [3B8h 0952 8] Read Ack Write : 0000000000000001 ..................................................................................... (3) according to above table, the address that contains the physical address of a block of memory that holds the error status data for SEA notification error source is 0x00000000785D0040 (4) the address for SEA notification error source is 0x785d8108 (qemu) xp /1 0x00000000785D0040 00000000785d0040: 0x785d80b0 (5) check the content of generic error status block and generic error data entry (qemu) xp /100x 0x785d80b0 00000000785d80b0: 0x00000001 0x00000000 0x00000000 0x00000098 00000000785d80c0: 0x00000000 0xa5bc1114 0x4ede6f64 0x833e63b8 00000000785d80d0: 0xb1837ced 0x00000000 0x00000300 0x00000050 00000000785d80e0: 0x00000000 0x00000000 0x00000000 0x00000000 00000000785d80f0: 0x00000000 0x00000000 0x00000000 0x00000000 00000000785d8100: 0x00000000 0x00000000 0x00000000 0x00004002 00000000785d8110: 0x00000000 0x00000000 0x00000000 0x00001111 00000000785d8120: 0x00000000 0x00000000 0x00000000 0x00000000 00000000785d8130: 0x00000000 0x00000000 0x00000000 0x00000000 00000000785d8140: 0x00000000 0x00000000 0x00000000 0x00000000 00000000785d8150: 0x00000000 0x00000003 0x00000000 0x00000000 00000000785d8160: 0x00000000 0x00000000 0x00000000 0x00000000 00000000785d8170: 0x00000000 0x00000000 0x00000000 0x00000000 00000000785d8180: 0x00000000 0x00000000 0x00000000 0x00000000 00000000785d8190: 0x00000000 0x00000000 0x00000000 0x00000000 00000000785d81a0: 0x00000000 0x00000000 0x00000000 0x00000000 00000000785d81b0: 0x00000000 0x00000000 0x00000000 0x00000000 00000000785d81c0: 0x00000000 0x00000000 0x00000000 0x00000000 00000000785d81d0: 0x00000000 0x00000000 0x00000000 0x00000000 00000000785d81e0: 0x00000000 0x00000000 0x00000000 0x00000000 00000000785d81f0: 0x00000000 0x00000000 0x00000000 0x00000000 00000000785d8200: 0x00000000 0x00000000 0x00000000 0x00000000 00000000785d8210: 0x00000000 0x00000000 0x00000000 0x00000000 00000000785d8220: 0x00000000 0x00000000 0x00000000 0x00000000 00000000785d8230: 0x00000000 0x00000000 0x00000000 0x00000000 (6) check the OSPM's ACK value(for example SEA) /* Before OSPM acknowledges the error, check the ACK value */ (qemu) xp /1 0x00000000785D0098 00000000785d00f0: 0x00000000 /* After OSPM acknowledges the error, check the ACK value */ (qemu) xp /1 0x00000000785D0098 00000000785d00f0: 0x00000001 Dongjiu Geng (3): ACPI: add APEI/HEST/CPER structures and macros ACPI: Add APEI GHES Table Generation support ACPI: build and enable APEI GHES in the Makefile and configuration default-configs/arm-softmmu.mak | 1 + hw/acpi/Makefile.objs | 1 + hw/acpi/aml-build.c | 2 + hw/acpi/hest_ghes.c | 344 ++++++++++++++++++++++++++++++++++++++++ hw/arm/virt-acpi-build.c | 6 + include/hw/acpi/acpi-defs.h | 193 ++++++++++++++++++++++ include/hw/acpi/aml-build.h | 1 + include/hw/acpi/hest_ghes.h | 47 ++++++ 8 files changed, 595 insertions(+) create mode 100644 hw/acpi/hest_ghes.c create mode 100644 include/hw/acpi/hest_ghes.h -- 1.8.3.1 From MAILER-DAEMON Fri Aug 04 06:03:08 2017 Received: from list by lists.gnu.org with archive (Exim 4.71) id 1ddZRk-000147-2I for mharc-qemu-arm@gnu.org; Fri, 04 Aug 2017 06:03:08 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:42483) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ddZRe-0000yO-08 for qemu-arm@nongnu.org; Fri, 04 Aug 2017 06:03:06 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ddZRY-0003pV-GV for qemu-arm@nongnu.org; Fri, 04 Aug 2017 06:03:02 -0400 Received: from szxga03-in.huawei.com ([45.249.212.189]:4348) by eggs.gnu.org with esmtps (TLS1.0:RSA_ARCFOUR_SHA1:16) (Exim 4.71) (envelope-from ) id 1ddZRQ-0003id-Q0; Fri, 04 Aug 2017 06:02:49 -0400 Received: from 172.30.72.56 (EHLO DGGEML402-HUB.china.huawei.com) ([172.30.72.56]) by dggrg03-dlp.huawei.com (MOS 4.4.6-GA FastPath queued) with ESMTP id ASX06412; Fri, 04 Aug 2017 18:02:44 +0800 (CST) Received: from linux.huawei.com (10.67.187.203) by DGGEML402-HUB.china.huawei.com (10.3.17.38) with Microsoft SMTP Server id 14.3.301.0; Fri, 4 Aug 2017 18:02:32 +0800 From: Dongjiu Geng To: , , , , , , CC: , , , Date: Fri, 4 Aug 2017 18:22:16 +0800 Message-ID: <1501842138-17606-2-git-send-email-gengdongjiu@huawei.com> X-Mailer: git-send-email 1.7.7 In-Reply-To: <1501842138-17606-1-git-send-email-gengdongjiu@huawei.com> References: <1501842138-17606-1-git-send-email-gengdongjiu@huawei.com> MIME-Version: 1.0 Content-Type: text/plain X-Originating-IP: [10.67.187.203] X-CFilter-Loop: Reflected X-Mirapoint-Virus-RAPID-Raw: score=unknown(0), refid=str=0001.0A090201.59844644.0172, ss=1, re=0.000, recu=0.000, reip=0.000, cl=1, cld=1, fgs=0, ip=0.0.0.0, so=2014-11-16 11:51:01, dmn=2013-03-21 17:37:32 X-Mirapoint-Loop-Id: c82bbd58d503ad30444d30adac5e5c27 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.4.x-2.6.x [generic] [fuzzy] X-Received-From: 45.249.212.189 Subject: [Qemu-arm] [PATCH v10 1/3] ACPI: add APEI/HEST/CPER structures and macros X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 04 Aug 2017 10:03:06 -0000 (1) Add related APEI/HEST table structures and macros, these definition refer to ACPI 6.1 and UEFI 2.6 spec. (2) Add generic error status block and CPER memory section definition, user space only handle memory section errors. Signed-off-by: Dongjiu Geng --- thanks Michael and Laszlo's review: change since v5: (1) update the commit message title (2) remove UUID_BE and UEFI_CPER_SEC_PLATFORM_MEM macros (3) remove including "qemu/uuid.h" file in this patch (4) remove including "hest_ghes.h" file in this patch (5) drop "this is" from the comment of structures and macros (6) replace the "QemuUUID section_type_le" to "uint8_t section_type_le[16]" chnage since v4: (1) fix email threading in this series is incorrect issue change since v3: (1) separate the original one patch into three patches: one is new ACPI structures and macros, another is C source file to generate ACPI HEST table and dynamically record CPER ,final patch is the change about Makefile and configuration (2) add comments about where the ACPI structures and macros come from, for example, they come from the UEFI Spec 2.6, "xxxxxxxxxxxx"; ACPI 6.1 spec, "xxxxxxxxxxxxxx". (3) correct the macros name, for emaple, prefix some macro names with "UEFI_". (4) remove the uuid_le struct and use the QemuUUID in the include/qemu/uuid.h" (5) remove the duplicate ACPI address space, because it already defined in the "include/hw/acpi/aml-build.h" (6) remove the acpi_generic_address structure because same definition exists in the AcpiGenericAddress. (7) rename the struct acpi_hest_notify to AcpiHestNotifyType (8) rename the struct acpi_hest_types to AcpiHestSourceType (9) rename enum constants AcpiHestSourceType to ACPI_HEST_SOURCE_xxx from ACPI_HEST_TYPE_xxx (10) remove the NOT_USED{3,4,5} enum constants in the AcpiHestSourceType. (11) add missed QEMU_PACKED for the struct definition. (12) remove the defnition of AcpiGenericErrorData, and rename the AcpiGenericErrorDataV300 to AcpiGenericErrorData. (13) use the QemuUUID type for the "section_type" field AcpiGenericErrorData, and rename it to section_type_le. (14) moving type AcpiGenericErrorSeverity above AcpiGenericErrorData and AcpiGenericErrorDataV300, and remarking on the "error_severity" fields that they take their values from AcpiGenericErrorSeverity (15) remove the wrongly call to BERT(Boot Error Record Table) (16) add comments for the struction member, for example, pint out that the block_status member in the AcpiGenericErrorStatus is a bitmask composed of ACPI_GEBS_xxx macros (17) remove the hardware error source notification type list, and rename the MAX_ERROR_SOURCE_COUNT_V6 to ACPI_HEST_NOTIFY_RESERVED. (18) remove the physical_addr member of GhesErrorState (19) change the "uint64_t ghes_addr_le[8]" in GhesErrorState to uint64_t ghes_addr_le (20) change the second parameter to "error_physical_addr" in the ghes_update_guest API statement --- include/hw/acpi/acpi-defs.h | 193 ++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 193 insertions(+) diff --git a/include/hw/acpi/acpi-defs.h b/include/hw/acpi/acpi-defs.h index 4cc3630..ff9525e 100644 --- a/include/hw/acpi/acpi-defs.h +++ b/include/hw/acpi/acpi-defs.h @@ -295,6 +295,44 @@ typedef struct AcpiMultipleApicTable AcpiMultipleApicTable; #define ACPI_APIC_GENERIC_TRANSLATOR 15 #define ACPI_APIC_RESERVED 16 /* 16 and greater are reserved */ +/* UEFI Spec 2.6, "N.2.5 Memory Error Section */ +#define UEFI_CPER_MEM_VALID_ERROR_STATUS 0x0001 +#define UEFI_CPER_MEM_VALID_PA 0x0002 +#define UEFI_CPER_MEM_VALID_PA_MASK 0x0004 +#define UEFI_CPER_MEM_VALID_NODE 0x0008 +#define UEFI_CPER_MEM_VALID_CARD 0x0010 +#define UEFI_CPER_MEM_VALID_MODULE 0x0020 +#define UEFI_CPER_MEM_VALID_BANK 0x0040 +#define UEFI_CPER_MEM_VALID_DEVICE 0x0080 +#define UEFI_CPER_MEM_VALID_ROW 0x0100 +#define UEFI_CPER_MEM_VALID_COLUMN 0x0200 +#define UEFI_CPER_MEM_VALID_BIT_POSITION 0x0400 +#define UEFI_CPER_MEM_VALID_REQUESTOR 0x0800 +#define UEFI_CPER_MEM_VALID_RESPONDER 0x1000 +#define UEFI_CPER_MEM_VALID_TARGET 0x2000 +#define UEFI_CPER_MEM_VALID_ERROR_TYPE 0x4000 +#define UEFI_CPER_MEM_VALID_RANK_NUMBER 0x8000 +#define UEFI_CPER_MEM_VALID_CARD_HANDLE 0x10000 +#define UEFI_CPER_MEM_VALID_MODULE_HANDLE 0x20000 +#define UEFI_CPER_MEM_ERROR_TYPE_MULTI_ECC 3 + +/* From the ACPI 6.1 spec, "18.3.2.9 Hardware Error Notification" */ + +enum AcpiHestNotifyType { + ACPI_HEST_NOTIFY_POLLED = 0, + ACPI_HEST_NOTIFY_EXTERNAL = 1, + ACPI_HEST_NOTIFY_LOCAL = 2, + ACPI_HEST_NOTIFY_SCI = 3, + ACPI_HEST_NOTIFY_NMI = 4, + ACPI_HEST_NOTIFY_CMCI = 5, /* ACPI 5.0 */ + ACPI_HEST_NOTIFY_MCE = 6, /* ACPI 5.0 */ + ACPI_HEST_NOTIFY_GPIO = 7, /* ACPI 6.0 */ + ACPI_HEST_NOTIFY_SEA = 8, /* ACPI 6.1 */ + ACPI_HEST_NOTIFY_SEI = 9, /* ACPI 6.1 */ + ACPI_HEST_NOTIFY_GSIV = 10, /* ACPI 6.1 */ + ACPI_HEST_NOTIFY_RESERVED = 11 /* 11 and greater are reserved */ +}; + /* * MADT sub-structures (Follow MULTIPLE_APIC_DESCRIPTION_TABLE) */ @@ -475,6 +513,161 @@ struct AcpiSystemResourceAffinityTable } QEMU_PACKED; typedef struct AcpiSystemResourceAffinityTable AcpiSystemResourceAffinityTable; +/* Hardware Error Notification, from the ACPI 6.1 + * spec, "18.3.2.9 Hardware Error Notification" + */ +struct AcpiHestNotify { + uint8_t type; + uint8_t length; + uint16_t config_write_enable; + uint32_t poll_interval; + uint32_t vector; + uint32_t polling_threshold_value; + uint32_t polling_threshold_window; + uint32_t error_threshold_value; + uint32_t error_threshold_window; +} QEMU_PACKED; +typedef struct AcpiHestNotify AcpiHestNotify; + +/* From ACPI 6.1, sections "18.3.2.1 IA-32 Architecture Machine + * Check Exception" through "18.3.2.8 Generic Hardware Error Source version 2". + */ +enum AcpiHestSourceType { + ACPI_HEST_SOURCE_IA32_CHECK = 0, + ACPI_HEST_SOURCE_IA32_CORRECTED_CHECK = 1, + ACPI_HEST_SOURCE_IA32_NMI = 2, + ACPI_HEST_SOURCE_AER_ROOT_PORT = 6, + ACPI_HEST_SOURCE_AER_ENDPOINT = 7, + ACPI_HEST_SOURCE_AER_BRIDGE = 8, + ACPI_HEST_SOURCE_GENERIC_ERROR = 9, + ACPI_HEST_SOURCE_GENERIC_ERROR_V2 = 10, + ACPI_HEST_SOURCE_RESERVED = 11 /* 11 and greater are reserved */ +}; + +/* Block status bitmasks from ACPI 6.1, "18.3.2.7.1 Generic Error Data" */ +#define ACPI_GEBS_UNCORRECTABLE (1) +#define ACPI_GEBS_CORRECTABLE (1 << 1) +#define ACPI_GEBS_MULTIPLE_UNCORRECTABLE (1 << 2) +#define ACPI_GEBS_MULTIPLE_CORRECTABLE (1 << 3) +/* 10 bits, error data entry count */ +#define ACPI_GEBS_ERROR_ENTRY_COUNT (0x3FF << 4) + +/* Generic Hardware Error Source Structure, refer to ACPI 6.1 + * "18.3.2.7 Generic Hardware Error Source". in this struct the + * "type" field has to be ACPI_HEST_SOURCE_GENERIC_ERROR + */ + +struct AcpiGenericHardwareErrorSource { + uint16_t type; + uint16_t source_id; + uint16_t related_source_id; + uint8_t flags; + uint8_t enabled; + uint32_t number_of_records; + uint32_t max_sections_per_record; + uint32_t max_raw_data_length; + struct AcpiGenericAddress error_status_address; + struct AcpiHestNotify notify; + uint32_t error_status_block_length; +} QEMU_PACKED; +typedef struct AcpiGenericHardwareErrorSource AcpiGenericHardwareErrorSource; + +/* Generic Hardware Error Source, version 2, ACPI 6.1, "18.3.2.8 Generic + * Hardware Error Source version 2", in this struct the "type" field has to + * be ACPI_HEST_SOURCE_GENERIC_ERROR_V2 + */ +struct AcpiGenericHardwareErrorSourceV2 { + uint16_t type; + uint16_t source_id; + uint16_t related_source_id; + uint8_t flags; + uint8_t enabled; + uint32_t number_of_records; + uint32_t max_sections_per_record; + uint32_t max_raw_data_length; + struct AcpiGenericAddress error_status_address; + struct AcpiHestNotify notify; + uint32_t error_status_block_length; + struct AcpiGenericAddress read_ack_register; + uint64_t read_ack_preserve; + uint64_t read_ack_write; +} QEMU_PACKED; +typedef struct AcpiGenericHardwareErrorSourceV2 + AcpiGenericHardwareErrorSourceV2; + +/* Generic Error Status block, from ACPI 6.1, + * "18.3.2.7.1 Generic Error Data" + */ +struct AcpiGenericErrorStatus { + /* It is a bitmask composed of ACPI_GEBS_xxx macros */ + uint32_t block_status; + uint32_t raw_data_offset; + uint32_t raw_data_length; + uint32_t data_length; + uint32_t error_severity; +} QEMU_PACKED; +typedef struct AcpiGenericErrorStatus AcpiGenericErrorStatus; + +enum AcpiGenericErrorSeverity { + ACPI_CPER_SEV_RECOVERABLE, + ACPI_CPER_SEV_FATAL, + ACPI_CPER_SEV_CORRECTED, + ACPI_CPER_SEV_NONE, +}; + +/* Generic Error Data entry, revision number is 0x0300, + * ACPI 6.1, "18.3.2.7.1 Generic Error Data" + */ +struct AcpiGenericErrorData { + uint8_t section_type_le[16]; + /* The "error_severity" fields that they take their + * values from AcpiGenericErrorSeverity + */ + uint32_t error_severity; + uint16_t revision; + uint8_t validation_bits; + uint8_t flags; + uint32_t error_data_length; + uint8_t fru_id[16]; + uint8_t fru_text[20]; + uint64_t time_stamp; +} QEMU_PACKED; +typedef struct AcpiGenericErrorData AcpiGenericErrorData; + +/* From UEFI 2.6, "N.2.5 Memory Error Section" */ +struct UefiCperSecMemErr { + uint64_t validation_bits; + uint64_t error_status; + uint64_t physical_addr; + uint64_t physical_addr_mask; + uint16_t node; + uint16_t card; + uint16_t module; + uint16_t bank; + uint16_t device; + uint16_t row; + uint16_t column; + uint16_t bit_pos; + uint64_t requestor_id; + uint64_t responder_id; + uint64_t target_id; + uint8_t error_type; + uint8_t reserved; + uint16_t rank; + uint16_t mem_array_handle; /* card handle in UEFI 2.4 */ + uint16_t mem_dev_handle; /* module handle in UEFI 2.4 */ +} QEMU_PACKED; +typedef struct UefiCperSecMemErr UefiCperSecMemErr; + +/* + * HEST Description Table + */ +struct AcpiHardwareErrorSourceTable { + ACPI_TABLE_HEADER_DEF /* ACPI common table header */ + uint32_t error_source_count; +} QEMU_PACKED; +typedef struct AcpiHardwareErrorSourceTable AcpiHardwareErrorSourceTable; + #define ACPI_SRAT_PROCESSOR_APIC 0 #define ACPI_SRAT_MEMORY 1 #define ACPI_SRAT_PROCESSOR_x2APIC 2 -- 1.8.3.1 From MAILER-DAEMON Fri Aug 04 06:03:11 2017 Received: from list by lists.gnu.org with archive (Exim 4.71) id 1ddZRm-000173-9E for mharc-qemu-arm@gnu.org; Fri, 04 Aug 2017 06:03:11 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:42502) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ddZRh-00011n-Fn for qemu-arm@nongnu.org; Fri, 04 Aug 2017 06:03:08 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ddZRd-0003r1-7N for qemu-arm@nongnu.org; Fri, 04 Aug 2017 06:03:05 -0400 Received: from szxga03-in.huawei.com ([45.249.212.189]:4350) by eggs.gnu.org with esmtps (TLS1.0:RSA_ARCFOUR_SHA1:16) (Exim 4.71) (envelope-from ) id 1ddZRQ-0003iu-Ou; Fri, 04 Aug 2017 06:02:49 -0400 Received: from 172.30.72.56 (EHLO DGGEML402-HUB.china.huawei.com) ([172.30.72.56]) by dggrg03-dlp.huawei.com (MOS 4.4.6-GA FastPath queued) with ESMTP id ASX06417; Fri, 04 Aug 2017 18:02:45 +0800 (CST) Received: from linux.huawei.com (10.67.187.203) by DGGEML402-HUB.china.huawei.com (10.3.17.38) with Microsoft SMTP Server id 14.3.301.0; Fri, 4 Aug 2017 18:02:32 +0800 From: Dongjiu Geng To: , , , , , , CC: , , , Date: Fri, 4 Aug 2017 18:22:17 +0800 Message-ID: <1501842138-17606-3-git-send-email-gengdongjiu@huawei.com> X-Mailer: git-send-email 1.7.7 In-Reply-To: <1501842138-17606-1-git-send-email-gengdongjiu@huawei.com> References: <1501842138-17606-1-git-send-email-gengdongjiu@huawei.com> MIME-Version: 1.0 Content-Type: text/plain X-Originating-IP: [10.67.187.203] X-CFilter-Loop: Reflected X-Mirapoint-Virus-RAPID-Raw: score=unknown(0), refid=str=0001.0A090205.59844645.00EC, ss=1, re=0.000, recu=0.000, reip=0.000, cl=1, cld=1, fgs=0, ip=0.0.0.0, so=2014-11-16 11:51:01, dmn=2013-03-21 17:37:32 X-Mirapoint-Loop-Id: d2fceeae715b4e58bada1bcdf1257b06 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.4.x-2.6.x [generic] [fuzzy] X-Received-From: 45.249.212.189 Subject: [Qemu-arm] [PATCH v10 2/3] ACPI: Add APEI GHES Table Generation support X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 04 Aug 2017 10:03:08 -0000 This implements APEI GHES Table by passing the error CPER info to the guest via a fw_cfg_blob. After a CPER info is recorded, an SEA(Synchronous External Abort)/SEI(SError Interrupt) exception will be injected into the guest OS. Below is the table layout, the max number of error soure is 11, which is classified by notification type. etc/acpi/tables etc/hardware_errors ==================== ========================================== + +--------------------------+ +------------------+ | | HEST | | address | +--------------+ | +--------------------------+ | registers | | Error Status | | | GHES0 | | +----------------+ | Data Block 0 | | +--------------------------+ +--------->| |status_address0 |------------->| +------------+ | | ................. | | | +----------------+ | | CPER | | | error_status_address-----+-+ +------->| |status_address1 |----------+ | | CPER | | | ................. | | | +----------------+ | | | .... | | | read_ack_register--------+-+ | | ............. | | | | CPER | | | read_ack_preserve | | | +------------------+ | | +------------+ | | read_ack_write | | | +----->| |status_address10|--------+ | | Error Status | + +--------------------------+ | | | | +----------------+ | | | Data Block 1 | | | GHES1 | +-+-+----->| | ack_value0 | | +-->| +------------+ + +--------------------------+ | | | +----------------+ | | | CPER | | | ................. | | | +--->| | ack_value1 | | | | CPER | | | error_status_address-----+---+ | | | +----------------+ | | | .... | | | ................. | | | | | ............. | | | | CPER | | | read_ack_register--------+-----+-+ | +----------------+ | +-+------------+ | | read_ack_preserve | | +->| | ack_value10 | | | |.......... | | | read_ack_write | | | | +----------------+ | | +------------+ + +--------------------------| | | | | Error Status | | | ............... | | | | | Data Block 10| + +--------------------------+ | | +---->| +------------+ | | GHES10 | | | | | CPER | + +--------------------------+ | | | | CPER | | | ................. | | | | | .... | | | error_status_address-----+-----+ | | | CPER | | | ................. | | +-+------------+ | | read_ack_register--------+---------+ | | read_ack_preserve | | | read_ack_write | + +--------------------------+ For GHESv2 error source, the OSPM must acknowledges the error via Read Ack register. so user space must check the ack value to avoid read-write race condition. Signed-off-by: Dongjiu Geng --- thanks a lot Michael and Laszlo's review and comments: change since v8: (1) remove the ACK value address change since v6: (1) update the commit message change since v5: (1) move to GHESv2 error source from GHESv1, because we maily use the GHESv2 (2) add the GHESv2 error source layout in the comments (2) add the logic to read the ack value from OSPM to avoid read-write race condition (3) including header files "aml-build.h" and "hest_ghes.h" in this patch to make it reasonable (4) calculate the fw_cfg blob offsets that should be patched in more fine-grained steps, with multiple separate increments, using: - structure type names, - sizeof operators, - offsetof macros, - and possibly a separate comment for each offset increment. (5) remove page boundary refers to 4096 in the "bios_linker_loader_alloc" (6) using build_append_int_noprefix to avoid use pointer math, so that the code is easily readable (7) change memory section definition to array from QemuUUID (8) only enable SEA/SEI notification hardware error source to avoid guest OS ACPI driver probe warning change since v4: 1. fix email threading in this series is incorrect issue change since v3: 1. remove the unnecessary include for "hw/acpi/vmgenid.h" in hw/arm/virt-acpi-build.c 2. add conversion between LE and host-endian for the CPER record 3. handle the case that run out of the preallocated memory for the CPER record 4. change to use g_malloc0 instead of g_malloc 5. change block_reqr_size name to block_rer_size 6. change QEMU coding style, that is, the operator is at the end of the line. 7. drop the ERROR_STATUS_ADDRESS_OFFSET and GAS_ADDRESS_OFFSET macros (from the header file as well), and use the offsetof to replace it. 8. remove the init_aml_allocator() / free_aml_allocator(), calculate the needed size, and push that many bytes directly to "table_data". 9. take an "OVMF header probe suppressor" into account 10.corrct HEST and CPER value assigment, for example, correct the source_id for every error source, this identifier of source_id should be unique among all error sources; 11. create only one WRITE_POINTER command, for the base address of "etc/hardware_errors". This should be done outside of the loop.The base addresses of the individual error status data blocks should be calculated in ghes_update_guest(), based on the error source / notification type 12.correct the commit message lists error sources / notification types 0 through 10 (count=11 in total). 13.correct the size calculation for GHES_DATA_ADDR_FW_CFG_FILE 14.range-checked the value of "notify" before using it as an array subscript --- hw/acpi/aml-build.c | 2 + hw/acpi/hest_ghes.c | 344 ++++++++++++++++++++++++++++++++++++++++++++ hw/arm/virt-acpi-build.c | 6 + include/hw/acpi/aml-build.h | 1 + include/hw/acpi/hest_ghes.h | 47 ++++++ 5 files changed, 400 insertions(+) create mode 100644 hw/acpi/hest_ghes.c create mode 100644 include/hw/acpi/hest_ghes.h diff --git a/hw/acpi/aml-build.c b/hw/acpi/aml-build.c index c6f2032..802b98d 100644 --- a/hw/acpi/aml-build.c +++ b/hw/acpi/aml-build.c @@ -1560,6 +1560,7 @@ void acpi_build_tables_init(AcpiBuildTables *tables) tables->table_data = g_array_new(false, true /* clear */, 1); tables->tcpalog = g_array_new(false, true /* clear */, 1); tables->vmgenid = g_array_new(false, true /* clear */, 1); + tables->hardware_errors = g_array_new(false, true /* clear */, 1); tables->linker = bios_linker_loader_init(); } @@ -1570,6 +1571,7 @@ void acpi_build_tables_cleanup(AcpiBuildTables *tables, bool mfre) g_array_free(tables->table_data, true); g_array_free(tables->tcpalog, mfre); g_array_free(tables->vmgenid, mfre); + g_array_free(tables->hardware_errors, mfre); } /* Build rsdt table */ diff --git a/hw/acpi/hest_ghes.c b/hw/acpi/hest_ghes.c new file mode 100644 index 0000000..7e256f7 --- /dev/null +++ b/hw/acpi/hest_ghes.c @@ -0,0 +1,344 @@ +/* + * APEI GHES table Generation + * + * Copyright (C) 2017 huawei. + * + * Author: Dongjiu Geng + * + * This work is licensed under the terms of the GNU GPL, version 2 or later. + * See the COPYING file in the top-level directory. + * + */ + +#include "qemu/osdep.h" +#include "qmp-commands.h" +#include "hw/acpi/acpi.h" +#include "hw/acpi/aml-build.h" +#include "hw/acpi/hest_ghes.h" +#include "hw/nvram/fw_cfg.h" +#include "sysemu/sysemu.h" +#include "qemu/error-report.h" + +/* The structure that stands for the layout + * GHES_ERRORS_FW_CFG_FILE fw_cfg blob + * + * etc/hardware_errors + * ========================================== + * +------------------+ + * | address | +--------------+ + * | registers | | Error Status | + * | +----------------+ | Data Block 0 | + * | |status_address0 |------------->| +------------+ + * | +----------------+ | | CPER | + * | |status_address1 |----------+ | | CPER | + * | +----------------+ | | | .... | + * | |............. | | | | CPER | + * | +----------------+ | | +------------+ + * | |status_address10|-----+ | | Error Status | + * | +----------------+ | | | Data Block 1 | + * | |ack_value0 | | +-->| +------------+ + * | +----------------+ | | | CPER | + * | |ack_value1 | | | | CPER | + * | +----------------+ | | | .... | + * | | ............. | | | | CPER | + * | +----------------+ | +-+------------+ + * | |ack_value10 | | | |.......... | + * | +----------------+ | | +------------+ + * | | Error Status | + * | | Data Block10 | + * +------->+------------+ + * | | CPER | + * | | CPER | + * | | .... | + * | | CPER | + * +-+------------+ + */ +struct hardware_errors_buffer { + /* Generic Error Status Block register */ + uint64_t gesb_address[GHES_ACPI_HEST_NOTIFY_RESERVED]; + uint64_t ack_value[GHES_ACPI_HEST_NOTIFY_RESERVED]; + char gesb[GHES_MAX_RAW_DATA_LENGTH][GHES_ACPI_HEST_NOTIFY_RESERVED]; +}; + +static int ghes_record_cper(uint64_t error_block_address, + uint64_t error_physical_addr) +{ + AcpiGenericErrorStatus block; + AcpiGenericErrorData *gdata; + UefiCperSecMemErr *mem_err; + uint64_t current_block_length; + unsigned char *buffer; + /* memory section */ + char mem_section_id_le[] = {0x14, 0x11, 0xBC, 0xA5, 0x64, 0x6F, 0xDE, + 0x4E, 0xB8, 0x63, 0x3E, 0x83, 0xED, 0x7C, + 0x83, 0xB1}; + + cpu_physical_memory_read(error_block_address, &block, + sizeof(AcpiGenericErrorStatus)); + + /* Get the current generic error status block length */ + current_block_length = sizeof(AcpiGenericErrorStatus) + + le32_to_cpu(block.data_length); + + /* If the Generic Error Status Block is NULL, update + * the block header + */ + if (!block.block_status) { + block.block_status = ACPI_GEBS_UNCORRECTABLE; + block.error_severity = ACPI_CPER_SEV_RECOVERABLE; + } + + block.data_length += cpu_to_le32(sizeof(AcpiGenericErrorData)); + block.data_length += cpu_to_le32(sizeof(UefiCperSecMemErr)); + + /* check whether it runs out of the preallocated memory */ + if ((le32_to_cpu(block.data_length) + sizeof(AcpiGenericErrorStatus)) > + GHES_MAX_RAW_DATA_LENGTH) { + error_report("Record CPER out of boundary!!!"); + return GHES_CPER_FAIL; + } + + /* Write back the Generic Error Status Block to guest memory */ + cpu_physical_memory_write(error_block_address, &block, + sizeof(AcpiGenericErrorStatus)); + + /* Fill in Generic Error Data Entry */ + buffer = g_malloc0(sizeof(AcpiGenericErrorData) + + sizeof(UefiCperSecMemErr)); + + + memset(buffer, 0, sizeof(AcpiGenericErrorData) + sizeof(UefiCperSecMemErr)); + gdata = (AcpiGenericErrorData *)buffer; + + /* Memory section */ + memcpy(&(gdata->section_type_le), &mem_section_id_le, + sizeof(mem_section_id_le)); + + /* error severity is recoverable */ + gdata->error_severity = ACPI_CPER_SEV_RECOVERABLE; + gdata->revision = 0x300; /* the revision number is 0x300 */ + gdata->error_data_length = cpu_to_le32(sizeof(UefiCperSecMemErr)); + + mem_err = (UefiCperSecMemErr *) (gdata + 1); + + /* User space only handle the memory section CPER */ + + /* Hard code to Multi-bit ECC error */ + mem_err->validation_bits |= cpu_to_le32(UEFI_CPER_MEM_VALID_ERROR_TYPE); + mem_err->error_type = cpu_to_le32(UEFI_CPER_MEM_ERROR_TYPE_MULTI_ECC); + + /* Record the physical address at which the memory error occurred */ + mem_err->validation_bits |= cpu_to_le32(UEFI_CPER_MEM_VALID_PA); + mem_err->physical_addr = cpu_to_le32(error_physical_addr); + + /* Write back the Generic Error Data Entry to guest memory */ + cpu_physical_memory_write(error_block_address + current_block_length, + buffer, sizeof(AcpiGenericErrorData) + sizeof(UefiCperSecMemErr)); + + g_free(buffer); + return GHES_CPER_OK; +} + +static void +build_address(GArray *table_data, BIOSLinker *linker, + uint32_t dst_patched_offset, uint32_t src_offset, + uint8_t address_space_id , uint8_t register_bit_width, + uint8_t register_bit_offset, uint8_t access_size) +{ + uint32_t address_size = sizeof(struct AcpiGenericAddress) - + offsetof(struct AcpiGenericAddress, address); + + /* Address space */ + build_append_int_noprefix(table_data, address_space_id, 1); + /* register bit width */ + build_append_int_noprefix(table_data, register_bit_width, 1); + /* register bit offset */ + build_append_int_noprefix(table_data, register_bit_offset, 1); + /* access size */ + build_append_int_noprefix(table_data, access_size, 1); + acpi_data_push(table_data, address_size); + + /* Patch address of ERRORS fw_cfg blob into the TABLE fw_cfg blob so OSPM + * can retrieve and read it. the address size is 64 bits. + */ + bios_linker_loader_add_pointer(linker, + ACPI_BUILD_TABLE_FILE, dst_patched_offset, sizeof(uint64_t), + GHES_ERRORS_FW_CFG_FILE, src_offset); +} + +void ghes_build_acpi(GArray *table_data, GArray *hardware_error, + BIOSLinker *linker) +{ + uint32_t ghes_start = table_data->len; + uint32_t address_size, error_status_address_offset; + uint32_t read_ack_register_offset, i; + + address_size = sizeof(struct AcpiGenericAddress) - + offsetof(struct AcpiGenericAddress, address); + + error_status_address_offset = ghes_start + + sizeof(AcpiHardwareErrorSourceTable) + + offsetof(AcpiGenericHardwareErrorSourceV2, error_status_address) + + offsetof(struct AcpiGenericAddress, address); + + read_ack_register_offset = ghes_start + + sizeof(AcpiHardwareErrorSourceTable) + + offsetof(AcpiGenericHardwareErrorSourceV2, read_ack_register) + + offsetof(struct AcpiGenericAddress, address); + + acpi_data_push(hardware_error, + offsetof(struct hardware_errors_buffer, ack_value)); + for (i = 0; i < GHES_ACPI_HEST_NOTIFY_RESERVED; i++) + /* Initialize read ack register */ + build_append_int_noprefix((void *)hardware_error, 1, 8); + + /* Reserved the total size for ERRORS fw_cfg blob + */ + acpi_data_push(hardware_error, sizeof(struct hardware_errors_buffer)); + + /* Allocate guest memory for the Data fw_cfg blob */ + bios_linker_loader_alloc(linker, GHES_ERRORS_FW_CFG_FILE, hardware_error, + 1, false); + /* Reserve table header size */ + acpi_data_push(table_data, sizeof(AcpiTableHeader)); + + build_append_int_noprefix(table_data, GHES_ACPI_HEST_NOTIFY_RESERVED, 4); + + for (i = 0; i < GHES_ACPI_HEST_NOTIFY_RESERVED; i++) { + build_append_int_noprefix(table_data, + ACPI_HEST_SOURCE_GENERIC_ERROR_V2, 2); /* type */ + /* source id */ + build_append_int_noprefix(table_data, cpu_to_le16(i), 2); + /* related source id */ + build_append_int_noprefix(table_data, 0xffff, 2); + build_append_int_noprefix(table_data, 0, 1); /* flags */ + + /* Currently only enable SEA and SEI notification type to avoid the + * kernel warning, reserve the space for other notification error source + */ + if (i == ACPI_HEST_NOTIFY_SEA || i == ACPI_HEST_NOTIFY_SEI) { + build_append_int_noprefix(table_data, 1, 1); /* enabled */ + } else { + build_append_int_noprefix(table_data, 0, 1); /* enabled */ + } + + /* The number of error status block per generic hardware error source */ + build_append_int_noprefix(table_data, 1, 4); + /* Max sections per record */ + build_append_int_noprefix(table_data, 1, 4); + /* Max raw data length */ + build_append_int_noprefix(table_data, GHES_MAX_RAW_DATA_LENGTH, 4); + + /* Build error status address*/ + build_address(table_data, linker, error_status_address_offset + i * + sizeof(AcpiGenericHardwareErrorSourceV2), i * address_size, + AML_SYSTEM_MEMORY, 0x40, 0, 4 /* QWord access */); + + /* Hardware error notification structure */ + build_append_int_noprefix(table_data, i, 1); /* type */ + /* length */ + build_append_int_noprefix(table_data, sizeof(AcpiHestNotify), 1); + build_append_int_noprefix(table_data, 0, 26); + + /* Error Status Block Length */ + build_append_int_noprefix(table_data, + cpu_to_le32(GHES_MAX_RAW_DATA_LENGTH), 4); + + /* Build read ack register */ + build_address(table_data, linker, read_ack_register_offset + i * + sizeof(AcpiGenericHardwareErrorSourceV2), + offsetof(struct hardware_errors_buffer, ack_value) + + i * address_size, AML_SYSTEM_MEMORY, 0x40, 0, + 4 /* QWord access */); + + /* Read ack preserve */ + build_append_int_noprefix(table_data, cpu_to_le64(0xfffffffe), 8); + + /* Read ack write */ + build_append_int_noprefix(table_data, cpu_to_le64(0x1), 8); + } + + for (i = 0; i < GHES_ACPI_HEST_NOTIFY_RESERVED; i++) + /* Patch address of generic error status block into + * the address register so OSPM can retrieve and read it. + */ + bios_linker_loader_add_pointer(linker, + GHES_ERRORS_FW_CFG_FILE, address_size * i, address_size, + GHES_ERRORS_FW_CFG_FILE, + offsetof(struct hardware_errors_buffer, gesb) + + i * GHES_MAX_RAW_DATA_LENGTH); + + /* Patch address of ERRORS fw_cfg blob into the ADDR fw_cfg blob + * so QEMU can write the ERRORS there. The address is expected to be + * < 4GB, but write 64 bits anyway. + */ + bios_linker_loader_write_pointer(linker, GHES_DATA_ADDR_FW_CFG_FILE, + 0, address_size, GHES_ERRORS_FW_CFG_FILE, + offsetof(struct hardware_errors_buffer, gesb)); + + build_header(linker, table_data, + (void *)(table_data->data + ghes_start), "HEST", + table_data->len - ghes_start, 1, NULL, "GHES"); +} + +static GhesState ges; +void ghes_add_fw_cfg(FWCfgState *s, GArray *hardware_error) +{ + + size_t request_block_size = sizeof(uint64_t) + GHES_MAX_RAW_DATA_LENGTH; + size_t size = GHES_ACPI_HEST_NOTIFY_RESERVED * request_block_size; + + /* Create a read-only fw_cfg file for GHES */ + fw_cfg_add_file(s, GHES_ERRORS_FW_CFG_FILE, hardware_error->data, + size); + /* Create a read-write fw_cfg file for Address */ + fw_cfg_add_file_callback(s, GHES_DATA_ADDR_FW_CFG_FILE, NULL, NULL, + &ges.ghes_addr_le, sizeof(ges.ghes_addr_le), false); +} + +bool ghes_update_guest(uint32_t notify, uint64_t physical_address) +{ + uint64_t error_block_addr; + uint64_t ack_value_addr, ack_value = 0; + int loop = 0, ack_value_size; + bool ret = GHES_CPER_FAIL; + + ack_value_size = (offsetof(struct hardware_errors_buffer, gesb) - + offsetof(struct hardware_errors_buffer, ack_value)) / + GHES_ACPI_HEST_NOTIFY_RESERVED; +retry: + if (physical_address && notify < GHES_ACPI_HEST_NOTIFY_RESERVED) { + error_block_addr = ges.ghes_addr_le + notify * GHES_MAX_RAW_DATA_LENGTH; + error_block_addr = le32_to_cpu(error_block_addr); + + ack_value_addr = ges.ghes_addr_le - + (GHES_ACPI_HEST_NOTIFY_RESERVED - notify) * ack_value_size; + cpu_physical_memory_read(ack_value_addr, &ack_value, ack_value_size); + if (!ack_value) { + if (loop < 3) { + usleep(100 * 1000); + loop++; + goto retry; + } else { + error_report("Last time OSPM does not acknowledge the error," + " record CPER failed this time, set the ack value to" + " avoid blocking next time CPER record! exit"); + ack_value = 1; + cpu_physical_memory_write(ack_value_addr, + &ack_value, ack_value_size); + return ret; + } + } else { + /* A zero value in ghes_addr means that BIOS has not yet written + * the address + */ + if (error_block_addr) { + ack_value = 0; + cpu_physical_memory_write(ack_value_addr, + &ack_value, ack_value_size); + ret = ghes_record_cper(error_block_addr, physical_address); + } + } + } + return ret; +} diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c index 0835e59..5c97016 100644 --- a/hw/arm/virt-acpi-build.c +++ b/hw/arm/virt-acpi-build.c @@ -45,6 +45,7 @@ #include "hw/arm/virt.h" #include "sysemu/numa.h" #include "kvm_arm.h" +#include "hw/acpi/hest_ghes.h" #define ARM_SPI_BASE 32 #define ACPI_POWER_BUTTON_DEVICE "PWRB" @@ -778,6 +779,9 @@ void virt_acpi_build(VirtMachineState *vms, AcpiBuildTables *tables) acpi_add_table(table_offsets, tables_blob); build_spcr(tables_blob, tables->linker, vms); + acpi_add_table(table_offsets, tables_blob); + ghes_build_acpi(tables_blob, tables->hardware_errors, tables->linker); + if (nb_numa_nodes > 0) { acpi_add_table(table_offsets, tables_blob); build_srat(tables_blob, tables->linker, vms); @@ -890,6 +894,8 @@ void virt_acpi_setup(VirtMachineState *vms) fw_cfg_add_file(vms->fw_cfg, ACPI_BUILD_TPMLOG_FILE, tables.tcpalog->data, acpi_data_len(tables.tcpalog)); + ghes_add_fw_cfg(vms->fw_cfg, tables.hardware_errors); + build_state->rsdp_mr = acpi_add_rom_blob(build_state, tables.rsdp, ACPI_BUILD_RSDP_FILE, 0); diff --git a/include/hw/acpi/aml-build.h b/include/hw/acpi/aml-build.h index 00c21f1..c1d15b3 100644 --- a/include/hw/acpi/aml-build.h +++ b/include/hw/acpi/aml-build.h @@ -211,6 +211,7 @@ struct AcpiBuildTables { GArray *rsdp; GArray *tcpalog; GArray *vmgenid; + GArray *hardware_errors; BIOSLinker *linker; } AcpiBuildTables; diff --git a/include/hw/acpi/hest_ghes.h b/include/hw/acpi/hest_ghes.h new file mode 100644 index 0000000..0772756 --- /dev/null +++ b/include/hw/acpi/hest_ghes.h @@ -0,0 +1,47 @@ +/* + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Authors: + * Dongjiu Geng + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#ifndef ACPI_GHES_H +#define ACPI_GHES_H + +#include "hw/acpi/bios-linker-loader.h" + +#define GHES_ERRORS_FW_CFG_FILE "etc/hardware_errors" +#define GHES_DATA_ADDR_FW_CFG_FILE "etc/hardware_errors_addr" + +#define GHES_GAS_ADDRESS_OFFSET 4 +#define GHES_ERROR_STATUS_ADDRESS_OFFSET 20 +#define GHES_NOTIFICATION_STRUCTURE 32 + +#define GHES_CPER_OK 1 +#define GHES_CPER_FAIL 0 + +#define GHES_ACPI_HEST_NOTIFY_RESERVED 11 +/* The max size in Bytes for one error block */ +#define GHES_MAX_RAW_DATA_LENGTH 0x1000 + + +typedef struct GhesState { + uint64_t ghes_addr_le; +} GhesState; + +void ghes_build_acpi(GArray *table_data, GArray *hardware_error, + BIOSLinker *linker); +void ghes_add_fw_cfg(FWCfgState *s, GArray *hardware_errors); +bool ghes_update_guest(uint32_t notify, uint64_t error_physical_addr); +#endif -- 1.8.3.1 From MAILER-DAEMON Fri Aug 04 10:35:33 2017 Received: from list by lists.gnu.org with archive (Exim 4.71) id 1dddhN-0003Mj-5R for mharc-qemu-arm@gnu.org; Fri, 04 Aug 2017 10:35:33 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:37141) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dddh8-00033x-QW for qemu-arm@nongnu.org; Fri, 04 Aug 2017 10:35:31 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dddgv-0002HX-Ei for qemu-arm@nongnu.org; Fri, 04 Aug 2017 10:35:18 -0400 Received: from mail-it0-x244.google.com ([2607:f8b0:4001:c0b::244]:38088) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1dddgv-0002Fp-4L; Fri, 04 Aug 2017 10:35:05 -0400 Received: by mail-it0-x244.google.com with SMTP id h199so1191764ith.5; Fri, 04 Aug 2017 07:35:03 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=mime-version:subject:from:in-reply-to:date:cc :content-transfer-encoding:message-id:references:to; bh=JhpQ0UkGfpG5nsytaphI+XNJO9zHKzVSD+eDsV/vxJg=; b=GJs9H85pUhzYMolosjTyXFFapTt3mZrHP93XyvmmbMYizq9ShjLsXPPnqvsrGB5pKM jCHaiy4NZhTLc4N9NcJT4MxPOc5eg3GfBAaoiQHu9tHG5Gyt6Yn/KGqp8cP+uynWgGr1 QR+oZaa2mX9VnD2/EWVzAbrl1rOEUIDTHN2IAn5OfalW3vPFMEwwb9WNmAkjIuIUX0nn PgrcgJNrTtwKOfWm3nfkz6M8fQR1EOsd3EEXQD6uStLLXNGqrAwZuojkOu/4+zfzmJiW M2/6B/CurR3pUeeNkSOTX88rYSSD+p4XhJftGw+WKPcDcGoO0ZF2owrSheJQLlvz8lM4 0rVw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:subject:from:in-reply-to:date:cc :content-transfer-encoding:message-id:references:to; bh=JhpQ0UkGfpG5nsytaphI+XNJO9zHKzVSD+eDsV/vxJg=; b=mg3g5+PGE98u31DjdvGKaGf+tSUOuUlbN1lpujvbHltwEKtFINIlxiFfDhyoifU/DJ ryUButUN/ZxnDsFA3cw6CcS2MQs/cVJFMU0BexyYs+fnGCsudzYLjMykG/MWntU2ahec 1YpFwOKqv3ARJQ6Vrnz331KkywPdWuk0fJeYGHqFE8Hzzm6qrG5tJ651WGpYbtucL7hx fIQ+1f+i4sNyMkTGc7EjVR7dZ2JXNXsbCV2/Mm+OaLREJdLAqS0wdZFOGJCtrRMLgyHI p+qrYM9h2QGBoUfBoS2HFiGFmsDkosU+KStW/jt2WWDUYMaZkv57rraODkxgcuPTrDPM uA9w== X-Gm-Message-State: AHYfb5jApGVL1N2T1StMvuqSf6vcVae3DCggplP1AQPvoLtMlWPt3CqY Dtkz6RGd7VIQKA== X-Received: by 10.36.170.7 with SMTP id b7mr2410757itf.10.1501857302883; Fri, 04 Aug 2017 07:35:02 -0700 (PDT) Received: from [192.168.0.7] (d199-74-164-53.col.wideopenwest.com. [74.199.53.164]) by smtp.gmail.com with ESMTPSA id p95sm769782ioi.62.2017.08.04.07.35.01 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 04 Aug 2017 07:35:02 -0700 (PDT) Content-Type: text/plain; charset=us-ascii Mime-Version: 1.0 (Mac OS X Mail 10.3 \(3273\)) From: Programmingkid In-Reply-To: Date: Fri, 4 Aug 2017 10:35:00 -0400 Cc: Laszlo Ersek , "Michael S. Tsirkin" , Igor Mammedov , zhaoshenglong@huawei.com, Peter Maydell , qemu-arm@nongnu.org, huangshaoyu@huawei.com, wuquanming@huawei.com, "qemu-devel@nongnu.org qemu-devel" Content-Transfer-Encoding: quoted-printable Message-Id: References: To: Dongjiu Geng X-Mailer: Apple Mail (2.3273) X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4001:c0b::244 Subject: [Qemu-arm] [Qemu-devel] [PATCH v6 0/3] Generate APEI GHES table and dynamically record CPER X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 04 Aug 2017 14:35:31 -0000 > On Aug 4, 2017, at 1:22 AM, qemu-devel-request@nongnu.org wrote: >=20 > Date: Fri, 4 Aug 2017 12:37:52 +0800 > From: Dongjiu Geng > To: , , , > , , > , > Cc: , , > > Subject: [Qemu-devel] [PATCH v6 0/3] Generate APEI GHES table and > dynamically record CPER > Message-ID: <1501821475-14647-1-git-send-email-gengdongjiu@huawei.com> > Content-Type: text/plain >=20 > In the armv8 platform, the mainly hardware error source are ARMv8 > SEA/SEI/GSIV. For the ARMv8 SEA/SEI, the KVM or host kernel will = signal SIGBUS > or use other interface to notify user space, such as Qemu. After Qemu = gets > the notification, it will record the CPER and inject the SEA/SEI to = KVM. this > series of patches will generate APEI table when guest OS boot up, and = dynamically > record CPER for the guest OS about the generic hardware errors, = currently the > userspace only handle the memory section hardware errors. Before Qemu = record the > CPER, it needs to check the ACK value written by the guest OS to avoid = read-write > race condition. >=20 > Below is the APEI/GHESV2/CPER table layout, the max number of error = soure is 11, > which is classified by notification type, now only enable the SEA/SEI = notification type > error source. >=20 > etc/acpi/tables etc/hardware_errors > =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D = =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D > +------------------+ > +----------------------------+ | address | = +--------------+ > | HEST + | registers | = | Error Status | > + +--------------------------+ | +----------------+ = | Data Block 0 | > | | GHES0 | +--------->| |status_address0 = |------------->| +------------+ > +--------------------------+ | | +----------------+ = | | CPER | > | | ................. | | +------->| |status_address1 = |----------+ | | CPER | > | | error_status_address | | | | +----------------+ = | | | .... | > | | ................. | | | | ............. | = | | | CPER | > | | error_status_address-----+-+ | +------------------+ = | | +-+------------+ > | | ................. | | +----->| = |status_address10|--------+ | | Error Status | > | | read_ack_register--------+-+ | | | +----------------+ = | | | Data Block 1 | > | | read_ack_preserve | +-+-+----->| |ack_address0 |--+ = | +-->| +------------+ > | | read_ack_write | | | | +----------------+ | = | | | CPER | > + +--------------------------+ | | +--->| |ack_address1 |--+-+ = | | | CPER | > | | GHES1 | | | | | +----------------+ | | = | | | .... | > + +--------------------------+ | | | | | ............. | | | = | | | CPER | > | | ................. | | | | | +----------------+ | | = | +-+------------+ > | | error_status_address-----+---+ | | +->| |ack_address10 |--+-+-+ = | | |.......... | > | | ................. | | | | | +----------------+ | | | = | | +------------+ > | | read_ack_register--------+-----+-+ | | | ack0 |<-+ | | = | | Error Status | > | | read_ack_preserve | | | | +----------------+ | | = | | Data Block 10| > | | read_ack_write | | | | | ack1 |<---+ | = +---->| +------------+ > + +--------------------------+ | | | +----------------+ | = | | CPER | > | | ............... | | | | | .... | | = | | CPER | > + +--------------------------+ | | | +--------------+ | | = | | .... | > | | GHES10 | | | | | ack10 |<---- + = | | CPER | > + +--------------------------+ | | | +----------------+ = +-+------------+ > | | ................. | | | > | | error_status_address-----+-----+ | > | | ................. | | > | | read_ack_register--------+---------+ > | | read_ack_preserve | > | | read_ack_write | > + +--------------------------+ Excellent job with the ASCII drawing.=20 From MAILER-DAEMON Fri Aug 04 13:21:02 2017 Received: from list by lists.gnu.org with archive (Exim 4.71) id 1ddgHW-0007Cn-M6 for mharc-qemu-arm@gnu.org; Fri, 04 Aug 2017 13:21:02 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:39698) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ddgHU-0007C3-Sq for qemu-arm@nongnu.org; Fri, 04 Aug 2017 13:21:01 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ddgHT-0001QQ-No for qemu-arm@nongnu.org; Fri, 04 Aug 2017 13:21:00 -0400 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:37794) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ddgHT-0001Dp-Bx; Fri, 04 Aug 2017 13:20:59 -0400 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.84_2) (envelope-from ) id 1ddgHK-0006s5-BW; Fri, 04 Aug 2017 18:20:50 +0100 From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: patches@linaro.org, Richard Henderson Date: Fri, 4 Aug 2017 18:20:41 +0100 Message-Id: <1501867249-1924-1-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 2.7.4 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-arm] [PATCH 0/8] Implement ARM external abort handling X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 04 Aug 2017 17:21:02 -0000 Following recent list discussion https://lists.gnu.org/archive/html/qemu-devel/2017-08/msg00063.html here's a patchseries which defines a new API for handling CPU memory transaction failures at the right level in the memory subsystem code, and implements it for ARM so that we can generate prefetch abort and data abort exceptions for external aborts. The first 3 patches here implement the core code support for the new cpu_transaction_failed_hook. The next 2 patches add support for turning it off on a per-board basis, and use that to go back to RAZ/WI on the legacy ARM board models, because right now we rely on that so that guest code doesn't blow up when it touches a device we don't have a model for yet. (We leave the support enabled for 'virt' and 'mps2'.) Finally the last 3 patches do some cleanup and then implement the new hook for ARM. (I have not as yet audited the target/arm code to check that we correctly handle failed transactions in all the places that C code does physical address accesses; but since those lookups don't generate exceptions today, the series leaves behaviour there no worse off than they were before.) thanks -- PMM Peter Maydell (8): memory.h: Move MemTxResult type to memattrs.h cpu: Define new cpu_transaction_failed() hook cputlb: Support generating CPU exceptions on memory transaction failures boards.h: Define new flag ignore_memory_transaction_failures hw/arm: Set ignore_memory_transaction_failures for most ARM boards target/arm: Factor out fault delivery code target/arm: Allow deliver_fault() caller to specify EA bit target/arm: Implement new do_transaction_failed hook include/exec/memattrs.h | 10 ++++ include/exec/memory.h | 10 ---- include/hw/boards.h | 11 ++++ include/qom/cpu.h | 26 ++++++++ softmmu_template.h | 4 +- target/arm/internals.h | 12 ++++ accel/tcg/cputlb.c | 32 +++++++++- hw/arm/aspeed.c | 3 + hw/arm/collie.c | 1 + hw/arm/cubieboard.c | 1 + hw/arm/digic_boards.c | 1 + hw/arm/exynos4_boards.c | 2 + hw/arm/gumstix.c | 2 + hw/arm/highbank.c | 2 + hw/arm/imx25_pdk.c | 1 + hw/arm/integratorcp.c | 1 + hw/arm/kzm.c | 1 + hw/arm/mainstone.c | 1 + hw/arm/musicpal.c | 1 + hw/arm/netduino2.c | 1 + hw/arm/nseries.c | 2 + hw/arm/omap_sx1.c | 2 + hw/arm/palm.c | 1 + hw/arm/raspi.c | 1 + hw/arm/realview.c | 4 ++ hw/arm/sabrelite.c | 1 + hw/arm/spitz.c | 4 ++ hw/arm/stellaris.c | 2 + hw/arm/tosa.c | 1 + hw/arm/versatilepb.c | 2 + hw/arm/vexpress.c | 1 + hw/arm/xilinx_zynq.c | 1 + hw/arm/xlnx-ep108.c | 2 + hw/arm/z2.c | 1 + qom/cpu.c | 7 +++ target/arm/cpu.c | 1 + target/arm/op_helper.c | 155 +++++++++++++++++++++++++++++++----------------- 37 files changed, 243 insertions(+), 68 deletions(-) -- 2.7.4 From MAILER-DAEMON Fri Aug 04 13:21:04 2017 Received: from list by lists.gnu.org with archive (Exim 4.71) id 1ddgHY-0007Gw-Q0 for mharc-qemu-arm@gnu.org; Fri, 04 Aug 2017 13:21:04 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:39723) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ddgHW-0007CZ-BA for qemu-arm@nongnu.org; Fri, 04 Aug 2017 13:21:03 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ddgHU-0001Rb-KW for qemu-arm@nongnu.org; Fri, 04 Aug 2017 13:21:02 -0400 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:37794) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ddgHU-0001Dp-CX; Fri, 04 Aug 2017 13:21:00 -0400 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.84_2) (envelope-from ) id 1ddgHO-0006uU-DU; Fri, 04 Aug 2017 18:20:54 +0100 From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: patches@linaro.org, Richard Henderson Date: Fri, 4 Aug 2017 18:20:49 +0100 Message-Id: <1501867249-1924-9-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1501867249-1924-1-git-send-email-peter.maydell@linaro.org> References: <1501867249-1924-1-git-send-email-peter.maydell@linaro.org> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-arm] [PATCH 8/8] target/arm: Implement new do_transaction_failed hook X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 04 Aug 2017 17:21:03 -0000 Implement the new do_transaction_failed hook for ARM, which should cause the CPU to take a prefetch abort or data abort. Signed-off-by: Peter Maydell --- target/arm/internals.h | 10 ++++++++++ target/arm/cpu.c | 1 + target/arm/op_helper.c | 43 +++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 54 insertions(+) diff --git a/target/arm/internals.h b/target/arm/internals.h index a3adbd8..13bb001 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -471,6 +471,16 @@ void arm_cpu_do_unaligned_access(CPUState *cs, vaddr vaddr, MMUAccessType access_type, int mmu_idx, uintptr_t retaddr); +/* arm_cpu_do_transaction_failed: handle a memory system error response + * (eg "no device/memory present at address") by raising an external abort + * exception + */ +void arm_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, + vaddr addr, unsigned size, + MMUAccessType access_type, + int mmu_idx, MemTxAttrs attrs, + MemTxResult response, uintptr_t retaddr); + /* Call the EL change hook if one has been registered */ static inline void arm_call_el_change_hook(ARMCPU *cpu) { diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 05c038b..6baede0 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -1670,6 +1670,7 @@ static void arm_cpu_class_init(ObjectClass *oc, void *data) #else cc->do_interrupt = arm_cpu_do_interrupt; cc->do_unaligned_access = arm_cpu_do_unaligned_access; + cc->do_transaction_failed = arm_cpu_do_transaction_failed; cc->get_phys_page_attrs_debug = arm_cpu_get_phys_page_attrs_debug; cc->asidx_from_attrs = arm_asidx_from_attrs; cc->vmsd = &vmstate_arm_cpu; diff --git a/target/arm/op_helper.c b/target/arm/op_helper.c index 7eac272..54b6dd8 100644 --- a/target/arm/op_helper.c +++ b/target/arm/op_helper.c @@ -229,6 +229,49 @@ void arm_cpu_do_unaligned_access(CPUState *cs, vaddr vaddr, deliver_fault(cpu, vaddr, access_type, fsr, fsc, &fi); } +/* arm_cpu_do_transaction_failed: handle a memory system error response + * (eg "no device/memory present at address") by raising an external abort + * exception + */ +void arm_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, + vaddr addr, unsigned size, + MMUAccessType access_type, + int mmu_idx, MemTxAttrs attrs, + MemTxResult response, uintptr_t retaddr) +{ + ARMCPU *cpu = ARM_CPU(cs); + CPUARMState *env = &cpu->env; + uint32_t fsr, fsc; + ARMMMUFaultInfo fi = {}; + ARMMMUIdx arm_mmu_idx = core_to_arm_mmu_idx(env, mmu_idx); + + if (retaddr) { + /* now we have a real cpu fault */ + cpu_restore_state(cs, retaddr); + } + + /* The EA bit in syndromes and fault status registers is an + * IMPDEF classification of external aborts. ARM implementations + * usually use this to indicate AXI bus Decode error (0) or + * Slave error (1); in QEMU we follow that. + */ + fi.ea = (response != MEMTX_DECODE_ERROR); + + /* The fault status register format depends on whether we're using + * the LPAE long descriptor format, or the short descriptor format. + */ + if (arm_s1_regime_using_lpae_format(env, arm_mmu_idx)) { + /* long descriptor form, STATUS 0b010000: synchronous ext abort */ + fsr = (fi.ea << 12) | (1 << 9) | 0x10; + } else { + /* short descriptor form, FSR 0b01000 : synchronous ext abort */ + fsr = (fi.ea << 12) | 0x8; + } + fsc = 0x10; + + deliver_fault(cpu, addr, access_type, fsr, fsc, &fi); +} + #endif /* !defined(CONFIG_USER_ONLY) */ uint32_t HELPER(add_setq)(CPUARMState *env, uint32_t a, uint32_t b) -- 2.7.4 From MAILER-DAEMON Fri Aug 04 13:21:05 2017 Received: from list by lists.gnu.org with archive (Exim 4.71) id 1ddgHZ-0007I3-Qv for mharc-qemu-arm@gnu.org; Fri, 04 Aug 2017 13:21:05 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:39728) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ddgHW-0007Cj-Fh for qemu-arm@nongnu.org; Fri, 04 Aug 2017 13:21:03 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ddgHV-0001T0-FR for qemu-arm@nongnu.org; Fri, 04 Aug 2017 13:21:02 -0400 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:37794) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ddgHV-0001Dp-7X; Fri, 04 Aug 2017 13:21:01 -0400 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.84_2) (envelope-from ) id 1ddgHN-0006u2-V1; Fri, 04 Aug 2017 18:20:53 +0100 From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: patches@linaro.org, Richard Henderson Date: Fri, 4 Aug 2017 18:20:48 +0100 Message-Id: <1501867249-1924-8-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1501867249-1924-1-git-send-email-peter.maydell@linaro.org> References: <1501867249-1924-1-git-send-email-peter.maydell@linaro.org> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-arm] [PATCH 7/8] target/arm: Allow deliver_fault() caller to specify EA bit X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 04 Aug 2017 17:21:03 -0000 For external aborts, we will want to be able to specify the EA (external abort type) bit in the syndrome field. Allow callers of deliver_fault() to do that by adding a field to ARMMMUFaultInfo which we use when constructing the syndrome values. Signed-off-by: Peter Maydell --- target/arm/internals.h | 2 ++ target/arm/op_helper.c | 10 +++++----- 2 files changed, 7 insertions(+), 5 deletions(-) diff --git a/target/arm/internals.h b/target/arm/internals.h index 1f6efef..a3adbd8 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -448,12 +448,14 @@ void arm_handle_psci_call(ARMCPU *cpu); * @s2addr: Address that caused a fault at stage 2 * @stage2: True if we faulted at stage 2 * @s1ptw: True if we faulted at stage 2 while doing a stage 1 page-table walk + * @ea: True if we should set the EA (external abort type) bit in syndrome */ typedef struct ARMMMUFaultInfo ARMMMUFaultInfo; struct ARMMMUFaultInfo { target_ulong s2addr; bool stage2; bool s1ptw; + bool ea; }; /* Do a page table walk and add page to TLB if possible */ diff --git a/target/arm/op_helper.c b/target/arm/op_helper.c index aa52a98..7eac272 100644 --- a/target/arm/op_helper.c +++ b/target/arm/op_helper.c @@ -80,7 +80,7 @@ uint32_t HELPER(neon_tbl)(CPUARMState *env, uint32_t ireg, uint32_t def, static inline uint32_t merge_syn_data_abort(uint32_t template_syn, unsigned int target_el, - bool same_el, + bool same_el, bool ea, bool s1ptw, bool is_write, int fsc) { @@ -99,7 +99,7 @@ static inline uint32_t merge_syn_data_abort(uint32_t template_syn, */ if (!(template_syn & ARM_EL_ISV) || target_el != 2 || s1ptw) { syn = syn_data_abort_no_iss(same_el, - 0, 0, s1ptw, is_write, fsc); + ea, 0, s1ptw, is_write, fsc); } else { /* Fields: IL, ISV, SAS, SSE, SRT, SF and AR come from the template * syndrome created at translation time. @@ -107,7 +107,7 @@ static inline uint32_t merge_syn_data_abort(uint32_t template_syn, */ syn = syn_data_abort_with_iss(same_el, 0, 0, 0, 0, 0, - 0, 0, s1ptw, is_write, fsc, + ea, 0, s1ptw, is_write, fsc, false); /* Merge the runtime syndrome with the template syndrome. */ syn |= template_syn; @@ -141,11 +141,11 @@ static void deliver_fault(ARMCPU *cpu, vaddr addr, MMUAccessType access_type, } if (access_type == MMU_INST_FETCH) { - syn = syn_insn_abort(same_el, 0, fi->s1ptw, fsc); + syn = syn_insn_abort(same_el, fi->ea, fi->s1ptw, fsc); exc = EXCP_PREFETCH_ABORT; } else { syn = merge_syn_data_abort(env->exception.syndrome, target_el, - same_el, fi->s1ptw, + same_el, fi->ea, fi->s1ptw, access_type == MMU_DATA_STORE, fsc); if (access_type == MMU_DATA_STORE -- 2.7.4 From MAILER-DAEMON Fri Aug 04 13:21:07 2017 Received: from list by lists.gnu.org with archive (Exim 4.71) id 1ddgHa-0007JQ-VD for mharc-qemu-arm@gnu.org; Fri, 04 Aug 2017 13:21:07 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:39770) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ddgHX-0007Ew-Qu for qemu-arm@nongnu.org; Fri, 04 Aug 2017 13:21:05 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ddgHW-0001Wf-CO for qemu-arm@nongnu.org; Fri, 04 Aug 2017 13:21:03 -0400 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:37794) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ddgHW-0001Dp-3J; Fri, 04 Aug 2017 13:21:02 -0400 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.84_2) (envelope-from ) id 1ddgHN-0006to-DB; Fri, 04 Aug 2017 18:20:53 +0100 From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: patches@linaro.org, Richard Henderson Date: Fri, 4 Aug 2017 18:20:47 +0100 Message-Id: <1501867249-1924-7-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1501867249-1924-1-git-send-email-peter.maydell@linaro.org> References: <1501867249-1924-1-git-send-email-peter.maydell@linaro.org> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-arm] [PATCH 6/8] target/arm: Factor out fault delivery code X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 04 Aug 2017 17:21:05 -0000 We currently have some similar code in tlb_fill() and in arm_cpu_do_unaligned_access() for delivering a data abort or prefetch abort. We're also going to want to do the same thing to handle external aborts. Factor out the common code into a new function deliver_fault(). Signed-off-by: Peter Maydell --- target/arm/op_helper.c | 110 +++++++++++++++++++++++++------------------------ 1 file changed, 57 insertions(+), 53 deletions(-) diff --git a/target/arm/op_helper.c b/target/arm/op_helper.c index 2a85666..aa52a98 100644 --- a/target/arm/op_helper.c +++ b/target/arm/op_helper.c @@ -115,6 +115,51 @@ static inline uint32_t merge_syn_data_abort(uint32_t template_syn, return syn; } +static void deliver_fault(ARMCPU *cpu, vaddr addr, MMUAccessType access_type, + uint32_t fsr, uint32_t fsc, ARMMMUFaultInfo *fi) +{ + CPUARMState *env = &cpu->env; + int target_el; + bool same_el; + uint32_t syn, exc; + + target_el = exception_target_el(env); + if (fi->stage2) { + target_el = 2; + env->cp15.hpfar_el2 = extract64(fi->s2addr, 12, 47) << 4; + } + same_el = (arm_current_el(env) == target_el); + + if (fsc == 0x3f) { + /* Caller doesn't have a long-format fault status code. This + * should only happen if this fault will never actually be reported + * to an EL that uses a syndrome register. Check that here. + * 0x3f is a (currently) reserved FSR code, in case the constructed + * syndrome does leak into the guest somehow. + */ + assert(target_el != 2 && !arm_el_is_aa64(env, target_el)); + } + + if (access_type == MMU_INST_FETCH) { + syn = syn_insn_abort(same_el, 0, fi->s1ptw, fsc); + exc = EXCP_PREFETCH_ABORT; + } else { + syn = merge_syn_data_abort(env->exception.syndrome, target_el, + same_el, fi->s1ptw, + access_type == MMU_DATA_STORE, + fsc); + if (access_type == MMU_DATA_STORE + && arm_feature(env, ARM_FEATURE_V6)) { + fsr |= (1 << 11); + } + exc = EXCP_DATA_ABORT; + } + + env->exception.vaddress = addr; + env->exception.fsr = fsr; + raise_exception(env, exc, syn, target_el); +} + /* try to fill the TLB and return an exception if error. If retaddr is * NULL, it means that the function was called in C code (i.e. not * from generated code or from helper.c) @@ -129,23 +174,13 @@ void tlb_fill(CPUState *cs, target_ulong addr, MMUAccessType access_type, ret = arm_tlb_fill(cs, addr, access_type, mmu_idx, &fsr, &fi); if (unlikely(ret)) { ARMCPU *cpu = ARM_CPU(cs); - CPUARMState *env = &cpu->env; - uint32_t syn, exc, fsc; - unsigned int target_el; - bool same_el; + uint32_t fsc; if (retaddr) { /* now we have a real cpu fault */ cpu_restore_state(cs, retaddr); } - target_el = exception_target_el(env); - if (fi.stage2) { - target_el = 2; - env->cp15.hpfar_el2 = extract64(fi.s2addr, 12, 47) << 4; - } - same_el = arm_current_el(env) == target_el; - if (fsr & (1 << 9)) { /* LPAE format fault status register : bottom 6 bits are * status code in the same form as needed for syndrome @@ -153,34 +188,15 @@ void tlb_fill(CPUState *cs, target_ulong addr, MMUAccessType access_type, fsc = extract32(fsr, 0, 6); } else { /* Short format FSR : this fault will never actually be reported - * to an EL that uses a syndrome register. Check that here, - * and use a (currently) reserved FSR code in case the constructed - * syndrome does leak into the guest somehow. + * to an EL that uses a syndrome register. Use a (currently) + * reserved FSR code in case the constructed syndrome does leak + * into the guest somehow. deliver_fault will assert that + * we don't target an EL using the syndrome. */ - assert(target_el != 2 && !arm_el_is_aa64(env, target_el)); fsc = 0x3f; } - /* For insn and data aborts we assume there is no instruction syndrome - * information; this is always true for exceptions reported to EL1. - */ - if (access_type == MMU_INST_FETCH) { - syn = syn_insn_abort(same_el, 0, fi.s1ptw, fsc); - exc = EXCP_PREFETCH_ABORT; - } else { - syn = merge_syn_data_abort(env->exception.syndrome, target_el, - same_el, fi.s1ptw, - access_type == MMU_DATA_STORE, fsc); - if (access_type == MMU_DATA_STORE - && arm_feature(env, ARM_FEATURE_V6)) { - fsr |= (1 << 11); - } - exc = EXCP_DATA_ABORT; - } - - env->exception.vaddress = addr; - env->exception.fsr = fsr; - raise_exception(env, exc, syn, target_el); + deliver_fault(cpu, addr, access_type, fsr, fsc, &fi); } } @@ -191,9 +207,8 @@ void arm_cpu_do_unaligned_access(CPUState *cs, vaddr vaddr, { ARMCPU *cpu = ARM_CPU(cs); CPUARMState *env = &cpu->env; - int target_el; - bool same_el; - uint32_t syn; + uint32_t fsr, fsc; + ARMMMUFaultInfo fi = {}; ARMMMUIdx arm_mmu_idx = core_to_arm_mmu_idx(env, mmu_idx); if (retaddr) { @@ -201,28 +216,17 @@ void arm_cpu_do_unaligned_access(CPUState *cs, vaddr vaddr, cpu_restore_state(cs, retaddr); } - target_el = exception_target_el(env); - same_el = (arm_current_el(env) == target_el); - - env->exception.vaddress = vaddr; - /* the DFSR for an alignment fault depends on whether we're using * the LPAE long descriptor format, or the short descriptor format */ if (arm_s1_regime_using_lpae_format(env, arm_mmu_idx)) { - env->exception.fsr = (1 << 9) | 0x21; + fsr = (1 << 9) | 0x21; } else { - env->exception.fsr = 0x1; - } - - if (access_type == MMU_DATA_STORE && arm_feature(env, ARM_FEATURE_V6)) { - env->exception.fsr |= (1 << 11); + fsr = 0x1; } + fsc = 0x21; - syn = merge_syn_data_abort(env->exception.syndrome, target_el, - same_el, 0, access_type == MMU_DATA_STORE, - 0x21); - raise_exception(env, EXCP_DATA_ABORT, syn, target_el); + deliver_fault(cpu, vaddr, access_type, fsr, fsc, &fi); } #endif /* !defined(CONFIG_USER_ONLY) */ -- 2.7.4 From MAILER-DAEMON Fri Aug 04 13:33:09 2017 Received: from list by lists.gnu.org with archive (Exim 4.71) id 1ddgTF-0007Tx-M1 for mharc-qemu-arm@gnu.org; Fri, 04 Aug 2017 13:33:09 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:46926) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ddgTD-0007TM-S7 for qemu-arm@nongnu.org; Fri, 04 Aug 2017 13:33:09 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ddgTC-0001iL-IX for qemu-arm@nongnu.org; Fri, 04 Aug 2017 13:33:07 -0400 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:37805) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ddgTC-0001gy-Bg; Fri, 04 Aug 2017 13:33:06 -0400 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.84_2) (envelope-from ) id 1ddgHM-0006sy-69; Fri, 04 Aug 2017 18:20:52 +0100 From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: patches@linaro.org, Richard Henderson Date: Fri, 4 Aug 2017 18:20:45 +0100 Message-Id: <1501867249-1924-5-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1501867249-1924-1-git-send-email-peter.maydell@linaro.org> References: <1501867249-1924-1-git-send-email-peter.maydell@linaro.org> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-arm] [PATCH 4/8] boards.h: Define new flag ignore_memory_transaction_failures X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 04 Aug 2017 17:33:09 -0000 Define a new MachineClass field ignore_memory_transaction_failures. If this is flag is true then the CPU will ignore memory transaction failures which should cause the CPU to take an exception due to an access to an unassigned physical address; the transaction will instead return zero (for a read) or be ignored (for a write). This should be set only by legacy board models which rely on the old RAZ/WI behaviour for handling devices that QEMU does not yet model. New board models should instead use "unimplemented-device" for all memory ranges where the guest will attempt to probe for a device that QEMU doesn't implement and a stub device is required. We need this for ARM boards, where we're about to implement support for generating external aborts on memory transaction failures. Too many of our legacy board models rely on the RAZ/WI behaviour and we would break currently working guests when their "probe for device" code provoked an external abort rather than a RAZ. Signed-off-by: Peter Maydell --- include/hw/boards.h | 11 +++++++++++ include/qom/cpu.h | 7 ++++++- qom/cpu.c | 7 +++++++ 3 files changed, 24 insertions(+), 1 deletion(-) diff --git a/include/hw/boards.h b/include/hw/boards.h index 3363dd1..7f044d1 100644 --- a/include/hw/boards.h +++ b/include/hw/boards.h @@ -131,6 +131,16 @@ typedef struct { * size than the target architecture's minimum. (Attempting to create * such a CPU will fail.) Note that changing this is a migration * compatibility break for the machine. + * @ignore_memory_transaction_failures: + * If this is flag is true then the CPU will ignore memory transaction + * failures which should cause the CPU to take an exception due to an + * access to an unassigned physical address; the transaction will instead + * return zero (for a read) or be ignored (for a write). This should be + * set only by legacy board models which rely on the old RAZ/WI behaviour + * for handling devices that QEMU does not yet model. New board models + * should instead use "unimplemented-device" for all memory ranges where + * the guest will attempt to probe for a device that QEMU doesn't + * implement and a stub device is required. */ struct MachineClass { /*< private >*/ @@ -171,6 +181,7 @@ struct MachineClass { bool rom_file_has_mr; int minimum_page_bits; bool has_hotpluggable_cpus; + bool ignore_memory_transaction_failures; int numa_mem_align_shift; void (*numa_auto_assign_ram)(MachineClass *mc, NodeInfo *nodes, int nb_nodes, ram_addr_t size); diff --git a/include/qom/cpu.h b/include/qom/cpu.h index fc54d55..8cff86f 100644 --- a/include/qom/cpu.h +++ b/include/qom/cpu.h @@ -311,6 +311,9 @@ struct qemu_work_item; * @trace_dstate_delayed: Delayed changes to trace_dstate (includes all changes * to @trace_dstate). * @trace_dstate: Dynamic tracing state of events for this vCPU (bitmask). + * @ignore_memory_transaction_failures: Cached copy of the MachineState + * flag of the same name: allows the board to suppress calling of the + * CPU do_transaction_failed hook function. * * State of one CPU core or thread. */ @@ -397,6 +400,8 @@ struct CPUState { */ bool throttle_thread_scheduled; + bool ignore_memory_transaction_failures; + /* Note that this is accessed at the start of every TB via a negative offset from AREG0. Leave this field at the end so as to make the (absolute value) offset as small as possible. This reduces code @@ -853,7 +858,7 @@ static inline void cpu_transaction_failed(CPUState *cpu, hwaddr physaddr, { CPUClass *cc = CPU_GET_CLASS(cpu); - if (cc->do_transaction_failed) { + if (!cpu->ignore_memory_transaction_failures && cc->do_transaction_failed) { cc->do_transaction_failed(cpu, physaddr, addr, size, access_type, mmu_idx, attrs, response, retaddr); } diff --git a/qom/cpu.c b/qom/cpu.c index 4f38db0..d8dcf64 100644 --- a/qom/cpu.c +++ b/qom/cpu.c @@ -29,6 +29,7 @@ #include "exec/cpu-common.h" #include "qemu/error-report.h" #include "sysemu/sysemu.h" +#include "hw/boards.h" #include "hw/qdev-properties.h" #include "trace-root.h" @@ -360,6 +361,12 @@ static void cpu_common_parse_features(const char *typename, char *features, static void cpu_common_realizefn(DeviceState *dev, Error **errp) { CPUState *cpu = CPU(dev); + Object *machine = qdev_get_machine(); + ObjectClass *oc = object_get_class(machine); + MachineClass *mc = MACHINE_CLASS(oc); + + cpu->ignore_memory_transaction_failures = + mc->ignore_memory_transaction_failures; if (dev->hotplugged) { cpu_synchronize_post_init(cpu); -- 2.7.4 From MAILER-DAEMON Fri Aug 04 13:33:11 2017 Received: from list by lists.gnu.org with archive (Exim 4.71) id 1ddgTH-0007Vk-HI for mharc-qemu-arm@gnu.org; Fri, 04 Aug 2017 13:33:11 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:46901) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ddgTC-0007TC-SR for qemu-arm@nongnu.org; Fri, 04 Aug 2017 13:33:07 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ddgTB-0001ht-O1 for qemu-arm@nongnu.org; Fri, 04 Aug 2017 13:33:06 -0400 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:37805) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ddgTB-0001gy-H3; Fri, 04 Aug 2017 13:33:05 -0400 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.84_2) (envelope-from ) id 1ddgHL-0006sR-8c; Fri, 04 Aug 2017 18:20:51 +0100 From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: patches@linaro.org, Richard Henderson Date: Fri, 4 Aug 2017 18:20:43 +0100 Message-Id: <1501867249-1924-3-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1501867249-1924-1-git-send-email-peter.maydell@linaro.org> References: <1501867249-1924-1-git-send-email-peter.maydell@linaro.org> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-arm] [PATCH 2/8] cpu: Define new cpu_transaction_failed() hook X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 04 Aug 2017 17:33:08 -0000 Currently we have a rather half-baked setup for allowing CPUs to generate exceptions on accesses to invalid memory: the CPU has a cpu_unassigned_access() hook which the memory system calls in unassigned_mem_write() and unassigned_mem_read() if the current_cpu pointer is non-NULL. This was originally designed before we implemented the MemTxResult type that allows memory operations to report a success or failure code, which is why the hook is called right at the bottom of the memory system. The major problem with this is that it means that the hook can be called even when the access was not actually done by the CPU: for instance if the CPU writes to a DMA engine register which causes the DMA engine to begin a transaction which has been set up by the guest to operate on invalid memory then this will casue the CPU to take an exception incorrectly. Another minor problem is that currently if a device returns a transaction error then this won't turn into a CPU exception at all. The right way to do this is to have allow the CPU to respond to memory system transaction failures at the point where the CPU specific code calls into the memory system. Define a new QOM CPU method and utility function cpu_transaction_failed() which is called in these cases. The functionality here overlaps with the existing cpu_unassigned_access() because individual target CPUs will need some work to convert them to the new system. When this transition is complete we can remove the old cpu_unassigned_access() code. Signed-off-by: Peter Maydell --- include/qom/cpu.h | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/include/qom/cpu.h b/include/qom/cpu.h index 25eefea..fc54d55 100644 --- a/include/qom/cpu.h +++ b/include/qom/cpu.h @@ -85,8 +85,10 @@ struct TranslationBlock; * @has_work: Callback for checking if there is work to do. * @do_interrupt: Callback for interrupt handling. * @do_unassigned_access: Callback for unassigned access handling. + * (this is deprecated: new targets should use do_transaction_failed instead) * @do_unaligned_access: Callback for unaligned access handling, if * the target defines #ALIGNED_ONLY. + * @do_transaction_failed: Callback for handling failed memory transactions * @virtio_is_big_endian: Callback to return %true if a CPU which supports * runtime configurable endianness is currently big-endian. Non-configurable * CPUs can use the default implementation of this method. This method should @@ -153,6 +155,10 @@ typedef struct CPUClass { void (*do_unaligned_access)(CPUState *cpu, vaddr addr, MMUAccessType access_type, int mmu_idx, uintptr_t retaddr); + void (*do_transaction_failed)(CPUState *cpu, hwaddr physaddr, vaddr addr, + unsigned size, MMUAccessType access_type, + int mmu_idx, MemTxAttrs attrs, + MemTxResult response, uintptr_t retaddr); bool (*virtio_is_big_endian)(CPUState *cpu); int (*memory_rw_debug)(CPUState *cpu, vaddr addr, uint8_t *buf, int len, bool is_write); @@ -837,6 +843,21 @@ static inline void cpu_unaligned_access(CPUState *cpu, vaddr addr, cc->do_unaligned_access(cpu, addr, access_type, mmu_idx, retaddr); } + +static inline void cpu_transaction_failed(CPUState *cpu, hwaddr physaddr, + vaddr addr, unsigned size, + MMUAccessType access_type, + int mmu_idx, MemTxAttrs attrs, + MemTxResult response, + uintptr_t retaddr) +{ + CPUClass *cc = CPU_GET_CLASS(cpu); + + if (cc->do_transaction_failed) { + cc->do_transaction_failed(cpu, physaddr, addr, size, access_type, + mmu_idx, attrs, response, retaddr); + } +} #endif #endif /* NEED_CPU_H */ -- 2.7.4 From MAILER-DAEMON Fri Aug 04 13:33:11 2017 Received: from list by lists.gnu.org with archive (Exim 4.71) id 1ddgTH-0007W1-Mk for mharc-qemu-arm@gnu.org; Fri, 04 Aug 2017 13:33:11 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:46969) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ddgTF-0007To-5D for qemu-arm@nongnu.org; Fri, 04 Aug 2017 13:33:10 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ddgTE-0001jf-8m for qemu-arm@nongnu.org; Fri, 04 Aug 2017 13:33:09 -0400 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:37805) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ddgTE-0001gy-17; Fri, 04 Aug 2017 13:33:08 -0400 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.84_2) (envelope-from ) id 1ddgHK-0006sG-Pd; Fri, 04 Aug 2017 18:20:50 +0100 From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: patches@linaro.org, Richard Henderson Date: Fri, 4 Aug 2017 18:20:42 +0100 Message-Id: <1501867249-1924-2-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1501867249-1924-1-git-send-email-peter.maydell@linaro.org> References: <1501867249-1924-1-git-send-email-peter.maydell@linaro.org> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-arm] [PATCH 1/8] memory.h: Move MemTxResult type to memattrs.h X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 04 Aug 2017 17:33:10 -0000 Move the MemTxResult type to memattrs.h. We're going to want to use it in cpu/qom.h, which doesn't want to include all of memory.h. In practice MemTxResult and MemTxAttrs are pretty closely linked since both are used for the new-style read_with_attrs and write_with_attrs callbacks, so memattrs.h is a reasonable home for this rather than creating a whole new header file for it. Signed-off-by: Peter Maydell --- include/exec/memattrs.h | 10 ++++++++++ include/exec/memory.h | 10 ---------- 2 files changed, 10 insertions(+), 10 deletions(-) diff --git a/include/exec/memattrs.h b/include/exec/memattrs.h index e601061..d4a1642 100644 --- a/include/exec/memattrs.h +++ b/include/exec/memattrs.h @@ -46,4 +46,14 @@ typedef struct MemTxAttrs { */ #define MEMTXATTRS_UNSPECIFIED ((MemTxAttrs) { .unspecified = 1 }) +/* New-style MMIO accessors can indicate that the transaction failed. + * A zero (MEMTX_OK) response means success; anything else is a failure + * of some kind. The memory subsystem will bitwise-OR together results + * if it is synthesizing an operation from multiple smaller accesses. + */ +#define MEMTX_OK 0 +#define MEMTX_ERROR (1U << 0) /* device returned an error */ +#define MEMTX_DECODE_ERROR (1U << 1) /* nothing at that address */ +typedef uint32_t MemTxResult; + #endif diff --git a/include/exec/memory.h b/include/exec/memory.h index 400dd44..1dcd312 100644 --- a/include/exec/memory.h +++ b/include/exec/memory.h @@ -112,16 +112,6 @@ static inline void iommu_notifier_init(IOMMUNotifier *n, IOMMUNotify fn, n->end = end; } -/* New-style MMIO accessors can indicate that the transaction failed. - * A zero (MEMTX_OK) response means success; anything else is a failure - * of some kind. The memory subsystem will bitwise-OR together results - * if it is synthesizing an operation from multiple smaller accesses. - */ -#define MEMTX_OK 0 -#define MEMTX_ERROR (1U << 0) /* device returned an error */ -#define MEMTX_DECODE_ERROR (1U << 1) /* nothing at that address */ -typedef uint32_t MemTxResult; - /* * Memory region callbacks */ -- 2.7.4 From MAILER-DAEMON Fri Aug 04 13:33:13 2017 Received: from list by lists.gnu.org with archive (Exim 4.71) id 1ddgTI-0007XE-IS for mharc-qemu-arm@gnu.org; Fri, 04 Aug 2017 13:33:12 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:46962) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ddgTE-0007Tg-Vf for qemu-arm@nongnu.org; Fri, 04 Aug 2017 13:33:10 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ddgTD-0001ix-DT for qemu-arm@nongnu.org; Fri, 04 Aug 2017 13:33:08 -0400 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:37805) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ddgTD-0001gy-6T; Fri, 04 Aug 2017 13:33:07 -0400 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.84_2) (envelope-from ) id 1ddgHL-0006si-N7; Fri, 04 Aug 2017 18:20:51 +0100 From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: patches@linaro.org, Richard Henderson Date: Fri, 4 Aug 2017 18:20:44 +0100 Message-Id: <1501867249-1924-4-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1501867249-1924-1-git-send-email-peter.maydell@linaro.org> References: <1501867249-1924-1-git-send-email-peter.maydell@linaro.org> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-arm] [PATCH 3/8] cputlb: Support generating CPU exceptions on memory transaction failures X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 04 Aug 2017 17:33:10 -0000 Call the new cpu_transaction_failed() hook at the places where CPU generated code interacts with the memory system: io_readx() io_writex() get_page_addr_code() Any access from C code (eg via cpu_physical_memory_rw(), address_space_rw(), ld/st_*_phys()) will *not* trigger CPU exceptions via cpu_transaction_failed(). Handling for transactions failures for this kind of call should be done by using a function which returns a MemTxResult and treating the failure case appropriately in the calling code. In an ideal world we would not generate CPU exceptions for instruction fetch failures in get_page_addr_code() but instead wait until the code translation process tried a load and it failed; however that change would require too great a restructuring and redesign to attempt at this point. Signed-off-by: Peter Maydell --- softmmu_template.h | 4 ++-- accel/tcg/cputlb.c | 32 ++++++++++++++++++++++++++++++-- 2 files changed, 32 insertions(+), 4 deletions(-) diff --git a/softmmu_template.h b/softmmu_template.h index 4a2b665..d756329 100644 --- a/softmmu_template.h +++ b/softmmu_template.h @@ -101,7 +101,7 @@ static inline DATA_TYPE glue(io_read, SUFFIX)(CPUArchState *env, uintptr_t retaddr) { CPUIOTLBEntry *iotlbentry = &env->iotlb[mmu_idx][index]; - return io_readx(env, iotlbentry, addr, retaddr, DATA_SIZE); + return io_readx(env, iotlbentry, mmu_idx, addr, retaddr, DATA_SIZE); } #endif @@ -262,7 +262,7 @@ static inline void glue(io_write, SUFFIX)(CPUArchState *env, uintptr_t retaddr) { CPUIOTLBEntry *iotlbentry = &env->iotlb[mmu_idx][index]; - return io_writex(env, iotlbentry, val, addr, retaddr, DATA_SIZE); + return io_writex(env, iotlbentry, mmu_idx, val, addr, retaddr, DATA_SIZE); } void helper_le_st_name(CPUArchState *env, target_ulong addr, DATA_TYPE val, diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index 85635ae..e72415a 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -747,6 +747,7 @@ static inline ram_addr_t qemu_ram_addr_from_host_nofail(void *ptr) } static uint64_t io_readx(CPUArchState *env, CPUIOTLBEntry *iotlbentry, + int mmu_idx, target_ulong addr, uintptr_t retaddr, int size) { CPUState *cpu = ENV_GET_CPU(env); @@ -754,6 +755,7 @@ static uint64_t io_readx(CPUArchState *env, CPUIOTLBEntry *iotlbentry, MemoryRegion *mr = iotlb_to_region(cpu, physaddr, iotlbentry->attrs); uint64_t val; bool locked = false; + MemTxResult r; physaddr = (physaddr & TARGET_PAGE_MASK) + addr; cpu->mem_io_pc = retaddr; @@ -767,7 +769,12 @@ static uint64_t io_readx(CPUArchState *env, CPUIOTLBEntry *iotlbentry, qemu_mutex_lock_iothread(); locked = true; } - memory_region_dispatch_read(mr, physaddr, &val, size, iotlbentry->attrs); + r = memory_region_dispatch_read(mr, physaddr, + &val, size, iotlbentry->attrs); + if (r != MEMTX_OK) { + cpu_transaction_failed(cpu, physaddr, addr, size, MMU_DATA_LOAD, + mmu_idx, iotlbentry->attrs, r, retaddr); + } if (locked) { qemu_mutex_unlock_iothread(); } @@ -776,6 +783,7 @@ static uint64_t io_readx(CPUArchState *env, CPUIOTLBEntry *iotlbentry, } static void io_writex(CPUArchState *env, CPUIOTLBEntry *iotlbentry, + int mmu_idx, uint64_t val, target_ulong addr, uintptr_t retaddr, int size) { @@ -783,6 +791,7 @@ static void io_writex(CPUArchState *env, CPUIOTLBEntry *iotlbentry, hwaddr physaddr = iotlbentry->addr; MemoryRegion *mr = iotlb_to_region(cpu, physaddr, iotlbentry->attrs); bool locked = false; + MemTxResult r; physaddr = (physaddr & TARGET_PAGE_MASK) + addr; if (mr != &io_mem_rom && mr != &io_mem_notdirty && !cpu->can_do_io) { @@ -795,7 +804,12 @@ static void io_writex(CPUArchState *env, CPUIOTLBEntry *iotlbentry, qemu_mutex_lock_iothread(); locked = true; } - memory_region_dispatch_write(mr, physaddr, val, size, iotlbentry->attrs); + r = memory_region_dispatch_write(mr, physaddr, + val, size, iotlbentry->attrs); + if (r != MEMTX_OK) { + cpu_transaction_failed(cpu, physaddr, addr, size, MMU_DATA_STORE, + mmu_idx, iotlbentry->attrs, r, retaddr); + } if (locked) { qemu_mutex_unlock_iothread(); } @@ -845,6 +859,7 @@ tb_page_addr_t get_page_addr_code(CPUArchState *env, target_ulong addr) MemoryRegion *mr; CPUState *cpu = ENV_GET_CPU(env); CPUIOTLBEntry *iotlbentry; + hwaddr physaddr; index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1); mmu_idx = cpu_mmu_index(env, true); @@ -868,6 +883,19 @@ tb_page_addr_t get_page_addr_code(CPUArchState *env, target_ulong addr) } qemu_mutex_unlock_iothread(); + /* Give the new-style cpu_transaction_failed() hook first chance + * to handle this. + * This is not the ideal place to detect and generate CPU + * exceptions for instruction fetch failure (for instance + * we don't know the length of the access that the CPU would + * use, and it would be better to go ahead and try the access + * and use the MemTXResult it produced). However it is the + * simplest place we have currently available for the check. + */ + physaddr = (iotlbentry->addr & TARGET_PAGE_MASK) + addr; + cpu_transaction_failed(cpu, physaddr, addr, 0, MMU_INST_FETCH, mmu_idx, + iotlbentry->attrs, MEMTX_DECODE_ERROR, 0); + cpu_unassigned_access(cpu, addr, false, true, 0, 4); /* The CPU's unassigned access hook might have longjumped out * with an exception. If it didn't (or there was no hook) then -- 2.7.4 From MAILER-DAEMON Fri Aug 04 13:33:15 2017 Received: from list by lists.gnu.org with archive (Exim 4.71) id 1ddgTL-0007aa-4D for mharc-qemu-arm@gnu.org; Fri, 04 Aug 2017 13:33:15 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:47041) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ddgTH-0007Vo-IZ for qemu-arm@nongnu.org; Fri, 04 Aug 2017 13:33:13 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ddgTF-0001kq-Dj for qemu-arm@nongnu.org; Fri, 04 Aug 2017 13:33:11 -0400 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:37806) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ddgTF-0001ju-1j; Fri, 04 Aug 2017 13:33:09 -0400 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.84_2) (envelope-from ) id 1ddgHM-0006tD-M1; Fri, 04 Aug 2017 18:20:52 +0100 From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: patches@linaro.org, Richard Henderson Date: Fri, 4 Aug 2017 18:20:46 +0100 Message-Id: <1501867249-1924-6-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1501867249-1924-1-git-send-email-peter.maydell@linaro.org> References: <1501867249-1924-1-git-send-email-peter.maydell@linaro.org> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-arm] [PATCH 5/8] hw/arm: Set ignore_memory_transaction_failures for most ARM boards X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 04 Aug 2017 17:33:14 -0000 Set the MachineClass flag ignore_memory_transaction_failures for almost all ARM boards. This means they retain the legacy behaviour that accesses to unimplemented addresses will RAZ/WI rather than aborting, when a subsequent commit adds support for external aborts. The exceptions are: * virt -- we know that guests won't try to prod devices that we don't describe in the device tree or ACPI tables * mps2 -- this board was written to use unimplemented-device for all the ranges with devices we don't yet handle New boards should not set the flag, but instead be written like the mps2. Signed-off-by: Peter Maydell --- hw/arm/aspeed.c | 3 +++ hw/arm/collie.c | 1 + hw/arm/cubieboard.c | 1 + hw/arm/digic_boards.c | 1 + hw/arm/exynos4_boards.c | 2 ++ hw/arm/gumstix.c | 2 ++ hw/arm/highbank.c | 2 ++ hw/arm/imx25_pdk.c | 1 + hw/arm/integratorcp.c | 1 + hw/arm/kzm.c | 1 + hw/arm/mainstone.c | 1 + hw/arm/musicpal.c | 1 + hw/arm/netduino2.c | 1 + hw/arm/nseries.c | 2 ++ hw/arm/omap_sx1.c | 2 ++ hw/arm/palm.c | 1 + hw/arm/raspi.c | 1 + hw/arm/realview.c | 4 ++++ hw/arm/sabrelite.c | 1 + hw/arm/spitz.c | 4 ++++ hw/arm/stellaris.c | 2 ++ hw/arm/tosa.c | 1 + hw/arm/versatilepb.c | 2 ++ hw/arm/vexpress.c | 1 + hw/arm/xilinx_zynq.c | 1 + hw/arm/xlnx-ep108.c | 2 ++ hw/arm/z2.c | 1 + 27 files changed, 43 insertions(+) diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c index 0c5635f..ab895ad 100644 --- a/hw/arm/aspeed.c +++ b/hw/arm/aspeed.c @@ -270,6 +270,7 @@ static void palmetto_bmc_class_init(ObjectClass *oc, void *data) mc->no_floppy = 1; mc->no_cdrom = 1; mc->no_parallel = 1; + mc->ignore_memory_transaction_failures = true; } static const TypeInfo palmetto_bmc_type = { @@ -302,6 +303,7 @@ static void ast2500_evb_class_init(ObjectClass *oc, void *data) mc->no_floppy = 1; mc->no_cdrom = 1; mc->no_parallel = 1; + mc->ignore_memory_transaction_failures = true; } static const TypeInfo ast2500_evb_type = { @@ -326,6 +328,7 @@ static void romulus_bmc_class_init(ObjectClass *oc, void *data) mc->no_floppy = 1; mc->no_cdrom = 1; mc->no_parallel = 1; + mc->ignore_memory_transaction_failures = true; } static const TypeInfo romulus_bmc_type = { diff --git a/hw/arm/collie.c b/hw/arm/collie.c index 2e69531..8830192 100644 --- a/hw/arm/collie.c +++ b/hw/arm/collie.c @@ -64,6 +64,7 @@ static void collie_machine_init(MachineClass *mc) { mc->desc = "Sharp SL-5500 (Collie) PDA (SA-1110)"; mc->init = collie_init; + mc->ignore_memory_transaction_failures = true; } DEFINE_MACHINE("collie", collie_machine_init) diff --git a/hw/arm/cubieboard.c b/hw/arm/cubieboard.c index b98e1c4..32f1edd 100644 --- a/hw/arm/cubieboard.c +++ b/hw/arm/cubieboard.c @@ -86,6 +86,7 @@ static void cubieboard_machine_init(MachineClass *mc) mc->init = cubieboard_init; mc->block_default_type = IF_IDE; mc->units_per_default_bus = 1; + mc->ignore_memory_transaction_failures = true; } DEFINE_MACHINE("cubieboard", cubieboard_machine_init) diff --git a/hw/arm/digic_boards.c b/hw/arm/digic_boards.c index 520c8e9..9f11dcd 100644 --- a/hw/arm/digic_boards.c +++ b/hw/arm/digic_boards.c @@ -155,6 +155,7 @@ static void canon_a1100_machine_init(MachineClass *mc) { mc->desc = "Canon PowerShot A1100 IS"; mc->init = &canon_a1100_init; + mc->ignore_memory_transaction_failures = true; } DEFINE_MACHINE("canon-a1100", canon_a1100_machine_init) diff --git a/hw/arm/exynos4_boards.c b/hw/arm/exynos4_boards.c index 7c03ed3..f1441ec 100644 --- a/hw/arm/exynos4_boards.c +++ b/hw/arm/exynos4_boards.c @@ -189,6 +189,7 @@ static void nuri_class_init(ObjectClass *oc, void *data) mc->desc = "Samsung NURI board (Exynos4210)"; mc->init = nuri_init; mc->max_cpus = EXYNOS4210_NCPUS; + mc->ignore_memory_transaction_failures = true; } static const TypeInfo nuri_type = { @@ -204,6 +205,7 @@ static void smdkc210_class_init(ObjectClass *oc, void *data) mc->desc = "Samsung SMDKC210 board (Exynos4210)"; mc->init = smdkc210_init; mc->max_cpus = EXYNOS4210_NCPUS; + mc->ignore_memory_transaction_failures = true; } static const TypeInfo smdkc210_type = { diff --git a/hw/arm/gumstix.c b/hw/arm/gumstix.c index d59d9ba..092ce36 100644 --- a/hw/arm/gumstix.c +++ b/hw/arm/gumstix.c @@ -128,6 +128,7 @@ static void connex_class_init(ObjectClass *oc, void *data) mc->desc = "Gumstix Connex (PXA255)"; mc->init = connex_init; + mc->ignore_memory_transaction_failures = true; } static const TypeInfo connex_type = { @@ -142,6 +143,7 @@ static void verdex_class_init(ObjectClass *oc, void *data) mc->desc = "Gumstix Verdex (PXA270)"; mc->init = verdex_init; + mc->ignore_memory_transaction_failures = true; } static const TypeInfo verdex_type = { diff --git a/hw/arm/highbank.c b/hw/arm/highbank.c index 20e60f1..0d222fe 100644 --- a/hw/arm/highbank.c +++ b/hw/arm/highbank.c @@ -410,6 +410,7 @@ static void highbank_class_init(ObjectClass *oc, void *data) mc->block_default_type = IF_IDE; mc->units_per_default_bus = 1; mc->max_cpus = 4; + mc->ignore_memory_transaction_failures = true; } static const TypeInfo highbank_type = { @@ -427,6 +428,7 @@ static void midway_class_init(ObjectClass *oc, void *data) mc->block_default_type = IF_IDE; mc->units_per_default_bus = 1; mc->max_cpus = 4; + mc->ignore_memory_transaction_failures = true; } static const TypeInfo midway_type = { diff --git a/hw/arm/imx25_pdk.c b/hw/arm/imx25_pdk.c index 7d42c74..9f3ee14 100644 --- a/hw/arm/imx25_pdk.c +++ b/hw/arm/imx25_pdk.c @@ -148,6 +148,7 @@ static void imx25_pdk_machine_init(MachineClass *mc) { mc->desc = "ARM i.MX25 PDK board (ARM926)"; mc->init = imx25_pdk_init; + mc->ignore_memory_transaction_failures = true; } DEFINE_MACHINE("imx25-pdk", imx25_pdk_machine_init) diff --git a/hw/arm/integratorcp.c b/hw/arm/integratorcp.c index d9530ed..d603af9 100644 --- a/hw/arm/integratorcp.c +++ b/hw/arm/integratorcp.c @@ -681,6 +681,7 @@ static void integratorcp_machine_init(MachineClass *mc) { mc->desc = "ARM Integrator/CP (ARM926EJ-S)"; mc->init = integratorcp_init; + mc->ignore_memory_transaction_failures = true; } DEFINE_MACHINE("integratorcp", integratorcp_machine_init) diff --git a/hw/arm/kzm.c b/hw/arm/kzm.c index 3ed6577..f9c2228 100644 --- a/hw/arm/kzm.c +++ b/hw/arm/kzm.c @@ -142,6 +142,7 @@ static void kzm_machine_init(MachineClass *mc) { mc->desc = "ARM KZM Emulation Baseboard (ARM1136)"; mc->init = kzm_init; + mc->ignore_memory_transaction_failures = true; } DEFINE_MACHINE("kzm", kzm_machine_init) diff --git a/hw/arm/mainstone.c b/hw/arm/mainstone.c index fb268e6..637f52c 100644 --- a/hw/arm/mainstone.c +++ b/hw/arm/mainstone.c @@ -196,6 +196,7 @@ static void mainstone2_machine_init(MachineClass *mc) { mc->desc = "Mainstone II (PXA27x)"; mc->init = mainstone_init; + mc->ignore_memory_transaction_failures = true; } DEFINE_MACHINE("mainstone", mainstone2_machine_init) diff --git a/hw/arm/musicpal.c b/hw/arm/musicpal.c index 7e8ab31..fcf6224 100644 --- a/hw/arm/musicpal.c +++ b/hw/arm/musicpal.c @@ -1718,6 +1718,7 @@ static void musicpal_machine_init(MachineClass *mc) { mc->desc = "Marvell 88w8618 / MusicPal (ARM926EJ-S)"; mc->init = musicpal_init; + mc->ignore_memory_transaction_failures = true; } DEFINE_MACHINE("musicpal", musicpal_machine_init) diff --git a/hw/arm/netduino2.c b/hw/arm/netduino2.c index 3cfe332..9d34d4c 100644 --- a/hw/arm/netduino2.c +++ b/hw/arm/netduino2.c @@ -45,6 +45,7 @@ static void netduino2_machine_init(MachineClass *mc) { mc->desc = "Netduino 2 Machine"; mc->init = netduino2_init; + mc->ignore_memory_transaction_failures = true; } DEFINE_MACHINE("netduino2", netduino2_machine_init) diff --git a/hw/arm/nseries.c b/hw/arm/nseries.c index 503a3b6..a32ac82 100644 --- a/hw/arm/nseries.c +++ b/hw/arm/nseries.c @@ -1425,6 +1425,7 @@ static void n800_class_init(ObjectClass *oc, void *data) mc->desc = "Nokia N800 tablet aka. RX-34 (OMAP2420)"; mc->init = n800_init; mc->default_boot_order = ""; + mc->ignore_memory_transaction_failures = true; } static const TypeInfo n800_type = { @@ -1440,6 +1441,7 @@ static void n810_class_init(ObjectClass *oc, void *data) mc->desc = "Nokia N810 tablet aka. RX-44 (OMAP2420)"; mc->init = n810_init; mc->default_boot_order = ""; + mc->ignore_memory_transaction_failures = true; } static const TypeInfo n810_type = { diff --git a/hw/arm/omap_sx1.c b/hw/arm/omap_sx1.c index 9809106..4535617 100644 --- a/hw/arm/omap_sx1.c +++ b/hw/arm/omap_sx1.c @@ -223,6 +223,7 @@ static void sx1_machine_v2_class_init(ObjectClass *oc, void *data) mc->desc = "Siemens SX1 (OMAP310) V2"; mc->init = sx1_init_v2; + mc->ignore_memory_transaction_failures = true; } static const TypeInfo sx1_machine_v2_type = { @@ -237,6 +238,7 @@ static void sx1_machine_v1_class_init(ObjectClass *oc, void *data) mc->desc = "Siemens SX1 (OMAP310) V1"; mc->init = sx1_init_v1; + mc->ignore_memory_transaction_failures = true; } static const TypeInfo sx1_machine_v1_type = { diff --git a/hw/arm/palm.c b/hw/arm/palm.c index 64cf8ca..bf070a2 100644 --- a/hw/arm/palm.c +++ b/hw/arm/palm.c @@ -274,6 +274,7 @@ static void palmte_machine_init(MachineClass *mc) { mc->desc = "Palm Tungsten|E aka. Cheetah PDA (OMAP310)"; mc->init = palmte_init; + mc->ignore_memory_transaction_failures = true; } DEFINE_MACHINE("cheetah", palmte_machine_init) diff --git a/hw/arm/raspi.c b/hw/arm/raspi.c index 32cdc98..5941c9f 100644 --- a/hw/arm/raspi.c +++ b/hw/arm/raspi.c @@ -168,5 +168,6 @@ static void raspi2_machine_init(MachineClass *mc) mc->no_cdrom = 1; mc->max_cpus = BCM2836_NCPUS; mc->default_ram_size = 1024 * 1024 * 1024; + mc->ignore_memory_transaction_failures = true; }; DEFINE_MACHINE("raspi2", raspi2_machine_init) diff --git a/hw/arm/realview.c b/hw/arm/realview.c index 76ff557..f1b261f 100644 --- a/hw/arm/realview.c +++ b/hw/arm/realview.c @@ -396,6 +396,7 @@ static void realview_eb_class_init(ObjectClass *oc, void *data) mc->desc = "ARM RealView Emulation Baseboard (ARM926EJ-S)"; mc->init = realview_eb_init; mc->block_default_type = IF_SCSI; + mc->ignore_memory_transaction_failures = true; } static const TypeInfo realview_eb_type = { @@ -412,6 +413,7 @@ static void realview_eb_mpcore_class_init(ObjectClass *oc, void *data) mc->init = realview_eb_mpcore_init; mc->block_default_type = IF_SCSI; mc->max_cpus = 4; + mc->ignore_memory_transaction_failures = true; } static const TypeInfo realview_eb_mpcore_type = { @@ -426,6 +428,7 @@ static void realview_pb_a8_class_init(ObjectClass *oc, void *data) mc->desc = "ARM RealView Platform Baseboard for Cortex-A8"; mc->init = realview_pb_a8_init; + mc->ignore_memory_transaction_failures = true; } static const TypeInfo realview_pb_a8_type = { @@ -441,6 +444,7 @@ static void realview_pbx_a9_class_init(ObjectClass *oc, void *data) mc->desc = "ARM RealView Platform Baseboard Explore for Cortex-A9"; mc->init = realview_pbx_a9_init; mc->max_cpus = 4; + mc->ignore_memory_transaction_failures = true; } static const TypeInfo realview_pbx_a9_type = { diff --git a/hw/arm/sabrelite.c b/hw/arm/sabrelite.c index 4e7ac8c..ee140e5 100644 --- a/hw/arm/sabrelite.c +++ b/hw/arm/sabrelite.c @@ -122,6 +122,7 @@ static void sabrelite_machine_init(MachineClass *mc) mc->desc = "Freescale i.MX6 Quad SABRE Lite Board (Cortex A9)"; mc->init = sabrelite_init; mc->max_cpus = FSL_IMX6_NUM_CPUS; + mc->ignore_memory_transaction_failures = true; } DEFINE_MACHINE("sabrelite", sabrelite_machine_init) diff --git a/hw/arm/spitz.c b/hw/arm/spitz.c index 7f588ce..6406421 100644 --- a/hw/arm/spitz.c +++ b/hw/arm/spitz.c @@ -983,6 +983,7 @@ static void akitapda_class_init(ObjectClass *oc, void *data) mc->desc = "Sharp SL-C1000 (Akita) PDA (PXA270)"; mc->init = akita_init; + mc->ignore_memory_transaction_failures = true; } static const TypeInfo akitapda_type = { @@ -998,6 +999,7 @@ static void spitzpda_class_init(ObjectClass *oc, void *data) mc->desc = "Sharp SL-C3000 (Spitz) PDA (PXA270)"; mc->init = spitz_init; mc->block_default_type = IF_IDE; + mc->ignore_memory_transaction_failures = true; } static const TypeInfo spitzpda_type = { @@ -1013,6 +1015,7 @@ static void borzoipda_class_init(ObjectClass *oc, void *data) mc->desc = "Sharp SL-C3100 (Borzoi) PDA (PXA270)"; mc->init = borzoi_init; mc->block_default_type = IF_IDE; + mc->ignore_memory_transaction_failures = true; } static const TypeInfo borzoipda_type = { @@ -1028,6 +1031,7 @@ static void terrierpda_class_init(ObjectClass *oc, void *data) mc->desc = "Sharp SL-C3200 (Terrier) PDA (PXA270)"; mc->init = terrier_init; mc->block_default_type = IF_IDE; + mc->ignore_memory_transaction_failures = true; } static const TypeInfo terrierpda_type = { diff --git a/hw/arm/stellaris.c b/hw/arm/stellaris.c index 408c1a1..b3aad23 100644 --- a/hw/arm/stellaris.c +++ b/hw/arm/stellaris.c @@ -1453,6 +1453,7 @@ static void lm3s811evb_class_init(ObjectClass *oc, void *data) mc->desc = "Stellaris LM3S811EVB"; mc->init = lm3s811evb_init; + mc->ignore_memory_transaction_failures = true; } static const TypeInfo lm3s811evb_type = { @@ -1467,6 +1468,7 @@ static void lm3s6965evb_class_init(ObjectClass *oc, void *data) mc->desc = "Stellaris LM3S6965EVB"; mc->init = lm3s6965evb_init; + mc->ignore_memory_transaction_failures = true; } static const TypeInfo lm3s6965evb_type = { diff --git a/hw/arm/tosa.c b/hw/arm/tosa.c index 8b757ff..1134cf7 100644 --- a/hw/arm/tosa.c +++ b/hw/arm/tosa.c @@ -263,6 +263,7 @@ static void tosapda_machine_init(MachineClass *mc) mc->desc = "Sharp SL-6000 (Tosa) PDA (PXA255)"; mc->init = tosa_init; mc->block_default_type = IF_IDE; + mc->ignore_memory_transaction_failures = true; } DEFINE_MACHINE("tosa", tosapda_machine_init) diff --git a/hw/arm/versatilepb.c b/hw/arm/versatilepb.c index b0e9f5b..76664e4 100644 --- a/hw/arm/versatilepb.c +++ b/hw/arm/versatilepb.c @@ -403,6 +403,7 @@ static void versatilepb_class_init(ObjectClass *oc, void *data) mc->desc = "ARM Versatile/PB (ARM926EJ-S)"; mc->init = vpb_init; mc->block_default_type = IF_SCSI; + mc->ignore_memory_transaction_failures = true; } static const TypeInfo versatilepb_type = { @@ -418,6 +419,7 @@ static void versatileab_class_init(ObjectClass *oc, void *data) mc->desc = "ARM Versatile/AB (ARM926EJ-S)"; mc->init = vab_init; mc->block_default_type = IF_SCSI; + mc->ignore_memory_transaction_failures = true; } static const TypeInfo versatileab_type = { diff --git a/hw/arm/vexpress.c b/hw/arm/vexpress.c index 528c65d..9be1833 100644 --- a/hw/arm/vexpress.c +++ b/hw/arm/vexpress.c @@ -750,6 +750,7 @@ static void vexpress_class_init(ObjectClass *oc, void *data) mc->desc = "ARM Versatile Express"; mc->init = vexpress_common_init; mc->max_cpus = 4; + mc->ignore_memory_transaction_failures = true; } static void vexpress_a9_class_init(ObjectClass *oc, void *data) diff --git a/hw/arm/xilinx_zynq.c b/hw/arm/xilinx_zynq.c index 6b11a75..9883215 100644 --- a/hw/arm/xilinx_zynq.c +++ b/hw/arm/xilinx_zynq.c @@ -324,6 +324,7 @@ static void zynq_machine_init(MachineClass *mc) mc->init = zynq_init; mc->max_cpus = 1; mc->no_sdcard = 1; + mc->ignore_memory_transaction_failures = true; } DEFINE_MACHINE("xilinx-zynq-a9", zynq_machine_init) diff --git a/hw/arm/xlnx-ep108.c b/hw/arm/xlnx-ep108.c index 860780a..c339cd4 100644 --- a/hw/arm/xlnx-ep108.c +++ b/hw/arm/xlnx-ep108.c @@ -122,6 +122,7 @@ static void xlnx_ep108_machine_init(MachineClass *mc) mc->init = xlnx_ep108_init; mc->block_default_type = IF_IDE; mc->units_per_default_bus = 1; + mc->ignore_memory_transaction_failures = true; } DEFINE_MACHINE("xlnx-ep108", xlnx_ep108_machine_init) @@ -132,6 +133,7 @@ static void xlnx_zcu102_machine_init(MachineClass *mc) mc->init = xlnx_ep108_init; mc->block_default_type = IF_IDE; mc->units_per_default_bus = 1; + mc->ignore_memory_transaction_failures = true; } DEFINE_MACHINE("xlnx-zcu102", xlnx_zcu102_machine_init) diff --git a/hw/arm/z2.c b/hw/arm/z2.c index 1607cbd..417bc1a 100644 --- a/hw/arm/z2.c +++ b/hw/arm/z2.c @@ -370,6 +370,7 @@ static void z2_machine_init(MachineClass *mc) { mc->desc = "Zipit Z2 (PXA27x)"; mc->init = z2_init; + mc->ignore_memory_transaction_failures = true; } DEFINE_MACHINE("z2", z2_machine_init) -- 2.7.4 From MAILER-DAEMON Fri Aug 04 13:47:46 2017 Received: from list by lists.gnu.org with archive (Exim 4.71) id 1ddghO-0007kL-Sj for mharc-qemu-arm@gnu.org; Fri, 04 Aug 2017 13:47:46 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:54902) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ddghM-0007jz-Vq for qemu-arm@nongnu.org; Fri, 04 Aug 2017 13:47:45 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ddghI-0005Tv-30 for qemu-arm@nongnu.org; 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[97.126.108.236]) by smtp.gmail.com with ESMTPSA id f74sm3516224pfk.131.2017.08.04.10.47.37 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 04 Aug 2017 10:47:37 -0700 (PDT) To: Peter Maydell , qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: patches@linaro.org References: <1501867249-1924-1-git-send-email-peter.maydell@linaro.org> <1501867249-1924-2-git-send-email-peter.maydell@linaro.org> From: Richard Henderson Message-ID: <7bec1b4f-1fd2-4104-814b-97476d619bf5@linaro.org> Date: Fri, 4 Aug 2017 10:47:36 -0700 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.2.1 MIME-Version: 1.0 In-Reply-To: <1501867249-1924-2-git-send-email-peter.maydell@linaro.org> Content-Type: text/plain; charset=utf-8 Content-Language: en-MW Content-Transfer-Encoding: 7bit X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::22f Subject: Re: [Qemu-arm] [PATCH 1/8] memory.h: Move MemTxResult type to memattrs.h X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 04 Aug 2017 17:47:45 -0000 On 08/04/2017 10:20 AM, Peter Maydell wrote: > Move the MemTxResult type to memattrs.h. We're going to want to > use it in cpu/qom.h, which doesn't want to include all of > memory.h. In practice MemTxResult and MemTxAttrs are pretty > closely linked since both are used for the new-style > read_with_attrs and write_with_attrs callbacks, so memattrs.h > is a reasonable home for this rather than creating a whole > new header file for it. > > Signed-off-by: Peter Maydell > --- > include/exec/memattrs.h | 10 ++++++++++ > include/exec/memory.h | 10 ---------- > 2 files changed, 10 insertions(+), 10 deletions(-) Reviewed-by: Richard Henderson r~ From MAILER-DAEMON Fri Aug 04 14:10:09 2017 Received: from list by lists.gnu.org with archive (Exim 4.71) id 1ddh33-0001sj-Jd for mharc-qemu-arm@gnu.org; Fri, 04 Aug 2017 14:10:09 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:38828) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ddh2z-0001p8-E0 for qemu-arm@nongnu.org; Fri, 04 Aug 2017 14:10:06 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ddh2x-0000PW-Mm for qemu-arm@nongnu.org; Fri, 04 Aug 2017 14:10:05 -0400 Received: from mail-qk0-x243.google.com ([2607:f8b0:400d:c09::243]:37463) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ddh2s-0000F1-OC; Fri, 04 Aug 2017 14:09:58 -0400 Received: by mail-qk0-x243.google.com with SMTP id x77so2238440qka.4; Fri, 04 Aug 2017 11:09:58 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:subject:to:cc:references:from:message-id:date:user-agent :mime-version:in-reply-to:content-language:content-transfer-encoding; bh=4fs8KvYZd2EPWhY7oBoNE4KKq6heQVtmgKYYKziSFt4=; b=QXcqFjQiiWAqfEtivk8FLY0dV2ChhzgE39LLjRSNoLNukuUW1HLNLbfLlEGTpthELF 9WyBGUFf9PypxofX4FqbASfkPy+9GD2MEBtVGJFWHhHQSgFYJheReu1o+ghGrxI7FqGV Iwt7ZraW9zeANxq3CizCoYlq6opplqkU13Iwn+DP4OISFfc7lXLggZXnapoAqjFdJn1n CGXM5qm2LHa9G/aM6hvZZLZb+WtPyjxiZfKs6pjj6s3NqhK+BzpoKqXeau9EmwUmV2P2 VcXZnv6/7sLsMndLSwR6+iTsH+LHSVut9MoWfSVpI6n087B0AMq/cnD43Ow+lue4C1g1 NsYg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:subject:to:cc:references:from:message-id :date:user-agent:mime-version:in-reply-to:content-language :content-transfer-encoding; bh=4fs8KvYZd2EPWhY7oBoNE4KKq6heQVtmgKYYKziSFt4=; b=MYVpQTdbbcrh/8Yxi7Ib846JhlIqko6ZpnUxlIKkElI/3utXQL746VlV2eEorfk9B/ Vnd4KKjs52jnL1USav2EAIbL81Dsuz0UUtuUj3ljAzxbOOPQ5c9ufm0XJDuxY4fTjWUD GorP+KIDUiN2KX95MrTtDRcfB1E9lIeeBAXziTgsljFBlczBZUDWWB9epxOpw+LKOG+s 0a6dhB1bDCnDMvZVYc7k11BD3FTJjBAL/P+XLGlOtCPTy3sKe/8QE+HSN0FEUyZMCdXh KLVuh5SxsNPVaIf0LssKcKUbvgVaGmhUL8qrnES1WMy45bQEUabrRe5Ujcw2RfpMQ8en 2lbA== X-Gm-Message-State: AHYfb5g1NMw9qRJ0k6+MeCug0b0h+R1fMPUUWCFXHoKvmPqe2z1t+s8t YjEsO6VpxhLZ1g== X-Received: by 10.55.33.77 with SMTP id h74mr4494317qkh.353.1501870198151; Fri, 04 Aug 2017 11:09:58 -0700 (PDT) Received: from [192.168.1.10] ([138.117.48.223]) by smtp.gmail.com with ESMTPSA id b142sm1344655qka.37.2017.08.04.11.09.56 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 04 Aug 2017 11:09:57 -0700 (PDT) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= To: Peter Maydell , qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Richard Henderson References: <1501867249-1924-1-git-send-email-peter.maydell@linaro.org> <1501867249-1924-5-git-send-email-peter.maydell@linaro.org> From: =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= Message-ID: <50d6ba4d-cfa3-5b5f-5da1-dca2326d4f5d@amsat.org> Date: Fri, 4 Aug 2017 15:09:54 -0300 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.2.1 MIME-Version: 1.0 In-Reply-To: <1501867249-1924-5-git-send-email-peter.maydell@linaro.org> Content-Type: text/plain; charset=utf-8; format=flowed Content-Language: en-US Content-Transfer-Encoding: 7bit X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400d:c09::243 Subject: Re: [Qemu-arm] [PATCH 4/8] boards.h: Define new flag ignore_memory_transaction_failures X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 04 Aug 2017 18:10:07 -0000 On 08/04/2017 02:20 PM, Peter Maydell wrote: > Define a new MachineClass field ignore_memory_transaction_failures. > If this is flag is true then the CPU will ignore memory transaction > failures which should cause the CPU to take an exception due to an > access to an unassigned physical address; the transaction will > instead return zero (for a read) or be ignored (for a write). This > should be set only by legacy board models which rely on the old > RAZ/WI behaviour for handling devices that QEMU does not yet model. > New board models should instead use "unimplemented-device" for all > memory ranges where the guest will attempt to probe for a device that > QEMU doesn't implement and a stub device is required. This is a very good idea. At least it will help understanding why not all firmwares compiled for the same board can boot. Since create_unimplemented_device() register overlapped with low priority, why not register it as default device directly, over the whole address space? > > We need this for ARM boards, where we're about to implement support for > generating external aborts on memory transaction failures. Too many > of our legacy board models rely on the RAZ/WI behaviour and we > would break currently working guests when their "probe for device" > code provoked an external abort rather than a RAZ. I think some firmware will give some surprises, those probing device is not here and expect RAZ/WI. I remember some fw probing PCI space, or enumerating CS this way for ex. RAZ/WI is a bus-feature, this is also bus-dependent to reply with abort or behave RAZ/WI. Maybe the effort should be done on how model/use buses in QEMU? Bus device would be an alias of unimplemented_device, which current purpose is more debugging than avoiding unassigned physical access aborts. I'm pretty sure this library setup probes for unassigned access installing an handler and checking it got hit, in this case (ab)using unimplemented_device would prevent this firmware to boot: http://www.ti.com/ww/en/functional_safety/safeti/index.html (I might have self-answered my first question) > > Signed-off-by: Peter Maydell > --- > include/hw/boards.h | 11 +++++++++++ > include/qom/cpu.h | 7 ++++++- > qom/cpu.c | 7 +++++++ > 3 files changed, 24 insertions(+), 1 deletion(-) > > diff --git a/include/hw/boards.h b/include/hw/boards.h > index 3363dd1..7f044d1 100644 > --- a/include/hw/boards.h > +++ b/include/hw/boards.h > @@ -131,6 +131,16 @@ typedef struct { > * size than the target architecture's minimum. (Attempting to create > * such a CPU will fail.) Note that changing this is a migration > * compatibility break for the machine. > + * @ignore_memory_transaction_failures: > + * If this is flag is true then the CPU will ignore memory transaction > + * failures which should cause the CPU to take an exception due to an > + * access to an unassigned physical address; the transaction will instead > + * return zero (for a read) or be ignored (for a write). This should be > + * set only by legacy board models which rely on the old RAZ/WI behaviour > + * for handling devices that QEMU does not yet model. New board models > + * should instead use "unimplemented-device" for all memory ranges where > + * the guest will attempt to probe for a device that QEMU doesn't > + * implement and a stub device is required. > */ > struct MachineClass { > /*< private >*/ > @@ -171,6 +181,7 @@ struct MachineClass { > bool rom_file_has_mr; > int minimum_page_bits; > bool has_hotpluggable_cpus; > + bool ignore_memory_transaction_failures; > int numa_mem_align_shift; > void (*numa_auto_assign_ram)(MachineClass *mc, NodeInfo *nodes, > int nb_nodes, ram_addr_t size); > diff --git a/include/qom/cpu.h b/include/qom/cpu.h > index fc54d55..8cff86f 100644 > --- a/include/qom/cpu.h > +++ b/include/qom/cpu.h > @@ -311,6 +311,9 @@ struct qemu_work_item; > * @trace_dstate_delayed: Delayed changes to trace_dstate (includes all changes > * to @trace_dstate). > * @trace_dstate: Dynamic tracing state of events for this vCPU (bitmask). > + * @ignore_memory_transaction_failures: Cached copy of the MachineState > + * flag of the same name: allows the board to suppress calling of the > + * CPU do_transaction_failed hook function. > * > * State of one CPU core or thread. > */ > @@ -397,6 +400,8 @@ struct CPUState { > */ > bool throttle_thread_scheduled; > > + bool ignore_memory_transaction_failures; > + > /* Note that this is accessed at the start of every TB via a negative > offset from AREG0. Leave this field at the end so as to make the > (absolute value) offset as small as possible. This reduces code > @@ -853,7 +858,7 @@ static inline void cpu_transaction_failed(CPUState *cpu, hwaddr physaddr, > { > CPUClass *cc = CPU_GET_CLASS(cpu); > > - if (cc->do_transaction_failed) { > + if (!cpu->ignore_memory_transaction_failures && cc->do_transaction_failed) { > cc->do_transaction_failed(cpu, physaddr, addr, size, access_type, > mmu_idx, attrs, response, retaddr); > } > diff --git a/qom/cpu.c b/qom/cpu.c > index 4f38db0..d8dcf64 100644 > --- a/qom/cpu.c > +++ b/qom/cpu.c > @@ -29,6 +29,7 @@ > #include "exec/cpu-common.h" > #include "qemu/error-report.h" > #include "sysemu/sysemu.h" > +#include "hw/boards.h" > #include "hw/qdev-properties.h" > #include "trace-root.h" > > @@ -360,6 +361,12 @@ static void cpu_common_parse_features(const char *typename, char *features, > static void cpu_common_realizefn(DeviceState *dev, Error **errp) > { > CPUState *cpu = CPU(dev); > + Object *machine = qdev_get_machine(); > + ObjectClass *oc = object_get_class(machine); > + MachineClass *mc = MACHINE_CLASS(oc); > + > + cpu->ignore_memory_transaction_failures = > + mc->ignore_memory_transaction_failures; > > if (dev->hotplugged) { > cpu_synchronize_post_init(cpu); > From MAILER-DAEMON Fri Aug 04 14:42:36 2017 Received: from list by lists.gnu.org with archive (Exim 4.71) id 1ddhYR-0004S1-UM for mharc-qemu-arm@gnu.org; Fri, 04 Aug 2017 14:42:35 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:54684) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ddhYP-0004R8-14 for qemu-arm@nongnu.org; Fri, 04 Aug 2017 14:42:34 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ddhYL-0001pZ-T6 for qemu-arm@nongnu.org; Fri, 04 Aug 2017 14:42:33 -0400 Received: from mail-pg0-x229.google.com ([2607:f8b0:400e:c05::229]:35783) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ddhYL-0001o1-Le for qemu-arm@nongnu.org; Fri, 04 Aug 2017 14:42:29 -0400 Received: by mail-pg0-x229.google.com with SMTP id v189so11110283pgd.2 for ; Fri, 04 Aug 2017 11:42:29 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=subject:to:cc:references:from:message-id:date:user-agent :mime-version:in-reply-to:content-language:content-transfer-encoding; bh=TkAuo+qH9ozndZfBZe2mJoO422cRzvaWKcVXSAzdPVc=; b=W1TQUcZ+48f/YQVRR0m1hjjCQDDUxxsHI+U0XykEcMUGGUR62qAH3D6rBV/t5blOVY CcR0BR8aRYBd7RMCcrXxKaewAmTOeADCyFxdCaMkUmCj2b7f6pGeFyaB17SY+Zih3MSH T7H84F2ylrL3XeUhFBlry3VckqUzXEZDavba8= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:subject:to:cc:references:from:message-id:date :user-agent:mime-version:in-reply-to:content-language :content-transfer-encoding; bh=TkAuo+qH9ozndZfBZe2mJoO422cRzvaWKcVXSAzdPVc=; b=jQTy11HxoA92uUZBVtoPxpE1CWgJLG1Z94C04++j58SkUh0PeyHer5rVPC7DYQvTuW bu1tGhZAhcWCMWWEIAF6B3PONyZm2wfxkTx0CNNAR0krxKtx3h3j537UrSGw6Qs7JxK7 W1HimmXpzgCOQzH46XzTINjzPp7SWcspbebiPmzmL/f8B0A5JMpXIkUPoBaTteNYL2NC iD6Dh+J/YnVRM5EESDcWP1Nklyv0RThMQ1jFTJkrYWc4D4DbIru5lW3j5pui5mz53NIq s8V76XoRzfBXSvndgFk1oEgoNmSWaA8zPIQCr9cVVX9bCKOCWSu5thP4OTwr7Y+EQ5xe hq9g== X-Gm-Message-State: AIVw112R+RQl1tOqYtPPjbeavIu9a4AAkR/o7eJiZAC9chx1GAJDzkoI atDKVcYlv1J59HMz X-Received: by 10.84.208.236 with SMTP id c41mr3951071plj.244.1501872148469; Fri, 04 Aug 2017 11:42:28 -0700 (PDT) Received: from anchor.twiddle.net (97-126-108-236.tukw.qwest.net. [97.126.108.236]) by smtp.gmail.com with ESMTPSA id n19sm4442278pfi.35.2017.08.04.11.42.27 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 04 Aug 2017 11:42:27 -0700 (PDT) To: Peter Maydell , qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: patches@linaro.org References: <1501867249-1924-1-git-send-email-peter.maydell@linaro.org> <1501867249-1924-3-git-send-email-peter.maydell@linaro.org> From: Richard Henderson Message-ID: <45d91dda-55e3-0221-d56d-66fbecdb7d9c@linaro.org> Date: Fri, 4 Aug 2017 11:42:26 -0700 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.2.1 MIME-Version: 1.0 In-Reply-To: <1501867249-1924-3-git-send-email-peter.maydell@linaro.org> Content-Type: text/plain; charset=utf-8 Content-Language: en-MW Content-Transfer-Encoding: 7bit X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::229 Subject: Re: [Qemu-arm] [PATCH 2/8] cpu: Define new cpu_transaction_failed() hook X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 04 Aug 2017 18:42:34 -0000 On 08/04/2017 10:20 AM, Peter Maydell wrote: > Currently we have a rather half-baked setup for allowing CPUs to > generate exceptions on accesses to invalid memory: the CPU has a > cpu_unassigned_access() hook which the memory system calls in > unassigned_mem_write() and unassigned_mem_read() if the current_cpu > pointer is non-NULL. This was originally designed before we > implemented the MemTxResult type that allows memory operations to > report a success or failure code, which is why the hook is called > right at the bottom of the memory system. The major problem with > this is that it means that the hook can be called even when the > access was not actually done by the CPU: for instance if the CPU > writes to a DMA engine register which causes the DMA engine to begin > a transaction which has been set up by the guest to operate on > invalid memory then this will casue the CPU to take an exception > incorrectly. Another minor problem is that currently if a device > returns a transaction error then this won't turn into a CPU exception > at all. > > The right way to do this is to have allow the CPU to respond > to memory system transaction failures at the point where the > CPU specific code calls into the memory system. > > Define a new QOM CPU method and utility function > cpu_transaction_failed() which is called in these cases. > The functionality here overlaps with the existing > cpu_unassigned_access() because individual target CPUs will > need some work to convert them to the new system. When this > transition is complete we can remove the old cpu_unassigned_access() > code. > > Signed-off-by: Peter Maydell > --- > include/qom/cpu.h | 21 +++++++++++++++++++++ > 1 file changed, 21 insertions(+) Reviewed-by: Richard Henderson r~ From MAILER-DAEMON Fri Aug 04 15:23:17 2017 Received: from list by lists.gnu.org with archive (Exim 4.71) id 1ddiBp-0002X2-5n for mharc-qemu-arm@gnu.org; Fri, 04 Aug 2017 15:23:17 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:49711) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ddiBn-0002Wl-MT for qemu-arm@nongnu.org; Fri, 04 Aug 2017 15:23:16 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ddiBj-0007lB-KY for qemu-arm@nongnu.org; Fri, 04 Aug 2017 15:23:15 -0400 Received: from mail-pg0-x22c.google.com ([2607:f8b0:400e:c05::22c]:35637) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ddiBj-0007kf-Di for qemu-arm@nongnu.org; Fri, 04 Aug 2017 15:23:11 -0400 Received: by mail-pg0-x22c.google.com with SMTP id v189so11454084pgd.2 for ; Fri, 04 Aug 2017 12:23:11 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=subject:to:references:from:message-id:date:user-agent:mime-version :in-reply-to:content-language:content-transfer-encoding; bh=13Jor6y1EcNYr/L3fBR/oYcDp81QqM4MT7Yu1l7kfZE=; b=ZUe53ztDID80/jABAVVqVMZSUmUmD9GXSwZvsMwYfMdK2kkr4ydHIThAeWMRVnd+Ho sQbgBVaXV+hreBWbber34cMV05lt6tOcZ7tIRewD6H/jnePHeT10SsCrF9PUZjcX7vOq bA5ZzRvNCLx9vPl60cNbXZRMMe9T6lbnV62SM= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:subject:to:references:from:message-id:date :user-agent:mime-version:in-reply-to:content-language :content-transfer-encoding; bh=13Jor6y1EcNYr/L3fBR/oYcDp81QqM4MT7Yu1l7kfZE=; b=Oq9ghOSbVwq4lNLO3cS69FkSJ9voR6Ry4CkC9x/4iqsgya8q/njVzdhhODGAfumd39 GtoBy5SJ2ITlU7yXoDDo9o6i2MJZGHD5rntAEUdrU7HdrD5PXcxlOu0cOYdLJKYAmO8z ZeMrq5uHOwPHIi4uMQE+1jloRHHGseD4ScS6hCdFaaLU0egCqS2jjsJ9UDWWI+k1NGPX qI3MFiQBZimg3ZVAVspLZVPML/Los3o4xmtxmtMix6zglS9UpcipKosxFT+a8OuGEIVF bFMDpGpYaMT0RATW9yc1armqc3X4T450uU4p6chMMnZPHFiZCM2vrNC/1V0g4yXPT1Xv mw4A== X-Gm-Message-State: AIVw110vL3jGfYd3eUA1JV9ZISjy24jKqqYPRPXBmI9u9fwRppn2oPOm NIyLuIcraiElcFAG X-Received: by 10.99.42.141 with SMTP id q135mr3410928pgq.175.1501874590440; Fri, 04 Aug 2017 12:23:10 -0700 (PDT) Received: from anchor.twiddle.net (97-126-108-236.tukw.qwest.net. [97.126.108.236]) by smtp.gmail.com with ESMTPSA id o14sm3857353pfi.158.2017.08.04.12.23.09 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 04 Aug 2017 12:23:09 -0700 (PDT) To: =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= , Peter Maydell , qemu-arm@nongnu.org, qemu-devel@nongnu.org References: <1501867249-1924-1-git-send-email-peter.maydell@linaro.org> <1501867249-1924-5-git-send-email-peter.maydell@linaro.org> <50d6ba4d-cfa3-5b5f-5da1-dca2326d4f5d@amsat.org> From: Richard Henderson Message-ID: Date: Fri, 4 Aug 2017 12:23:07 -0700 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.2.1 MIME-Version: 1.0 In-Reply-To: <50d6ba4d-cfa3-5b5f-5da1-dca2326d4f5d@amsat.org> Content-Type: text/plain; charset=utf-8 Content-Language: en-MW Content-Transfer-Encoding: 8bit X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::22c Subject: Re: [Qemu-arm] [PATCH 4/8] boards.h: Define new flag ignore_memory_transaction_failures X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 04 Aug 2017 19:23:16 -0000 On 08/04/2017 11:09 AM, Philippe Mathieu-Daudé wrote: > Since create_unimplemented_device() register overlapped with low priority, why > not register it as default device directly, over the whole address space? That's a good suggestion. It makes more sense to me than adding a flag on the MachineClass. r~ From MAILER-DAEMON Fri Aug 04 16:10:14 2017 Received: from list by lists.gnu.org with archive (Exim 4.71) id 1ddivG-0003Oe-05 for mharc-qemu-arm@gnu.org; Fri, 04 Aug 2017 16:10:14 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:46956) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ddivD-0003O2-Sm for qemu-arm@nongnu.org; Fri, 04 Aug 2017 16:10:12 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ddivA-00064Q-NP for qemu-arm@nongnu.org; Fri, 04 Aug 2017 16:10:11 -0400 Received: from mail-pf0-x22f.google.com ([2607:f8b0:400e:c00::22f]:34481) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ddivA-00060c-HS for qemu-arm@nongnu.org; Fri, 04 Aug 2017 16:10:08 -0400 Received: by mail-pf0-x22f.google.com with SMTP id o86so11735196pfj.1 for ; Fri, 04 Aug 2017 13:10:08 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=subject:to:cc:references:from:message-id:date:user-agent :mime-version:in-reply-to:content-language:content-transfer-encoding; bh=pW06FYdLkisvvIt/Jwv6Hr5WLRJKKWmdCmc2tt9AF+Q=; b=Qe2V+5PwKy1ZpwARxXuE7OogyYdr8lp4ncv1lEM9FUeUJQv+omq3hmxcgvUgmMoEK2 oKFol0QS1QYm3nDsqMMtuflc1tYUpIOLlD83bGWqdH74wL+fjLrndWmwWZfE5tyHq3jV cgXGKjbtFTWqFfctcJy+hpNzZzblPD3UG+puI= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:subject:to:cc:references:from:message-id:date :user-agent:mime-version:in-reply-to:content-language :content-transfer-encoding; bh=pW06FYdLkisvvIt/Jwv6Hr5WLRJKKWmdCmc2tt9AF+Q=; b=cgL8USCccyZkrWI7+fjA5q5VK00EcDLB6Q5Um+aT83areghJ4YEkFhUqfoKWlzgVUH oadLoWZh27SuhZ16pYDLj5Iqh4/7fHYa5N1gzAHWcPzdK4GZnhEu9OYCYUiI+OLf6AlR bbPA4uLqjUQu8X5ntks3s1krr2JBCjd+Kfrb3DMtHePdVIltM9+bMISNV+gNchkyJARo nJRsRCexmayW8F3wCMwuwRUx1beN1mzunhuq3opoG6fDbwbojsBm7dvjDFK+5BzmYfj7 Y+DtxP1qnmx6o1k5hTIAFRee8ghpnnI2Bn3+/B6j5dfNuggQdn89coXhSvmLPQrRIPgS 5YYg== X-Gm-Message-State: AIVw112+2qwOjkm2ZdqizqVk1lS6iltlLBojINY6WpDnUI5CkP+cTXhN bnmZbpJVxKzQR2tE X-Received: by 10.99.123.76 with SMTP id k12mr3466056pgn.277.1501877407322; Fri, 04 Aug 2017 13:10:07 -0700 (PDT) Received: from bigtime.twiddle.net (97-126-108-236.tukw.qwest.net. [97.126.108.236]) by smtp.gmail.com with ESMTPSA id 184sm3998423pfg.16.2017.08.04.13.10.06 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 04 Aug 2017 13:10:06 -0700 (PDT) To: Peter Maydell , qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: patches@linaro.org References: <1501867249-1924-1-git-send-email-peter.maydell@linaro.org> <1501867249-1924-7-git-send-email-peter.maydell@linaro.org> From: Richard Henderson Message-ID: <83c6b830-d15a-633a-c310-e3e541f1a6e2@linaro.org> Date: Fri, 4 Aug 2017 13:10:04 -0700 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.2.1 MIME-Version: 1.0 In-Reply-To: <1501867249-1924-7-git-send-email-peter.maydell@linaro.org> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 7bit X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::22f Subject: Re: [Qemu-arm] [PATCH 6/8] target/arm: Factor out fault delivery code X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 04 Aug 2017 20:10:12 -0000 On 08/04/2017 10:20 AM, Peter Maydell wrote: > + if (fsc == 0x3f) { > + /* Caller doesn't have a long-format fault status code. This > + * should only happen if this fault will never actually be reported > + * to an EL that uses a syndrome register. Check that here. > + * 0x3f is a (currently) reserved FSR code, in case the constructed > + * syndrome does leak into the guest somehow. > + */ > + assert(target_el != 2 && !arm_el_is_aa64(env, target_el)); > + } I see that this is just code movement, but there appears to be a typo in the comment, confusing fsc vs fsr and the 0x3f reserved value. Otherwise, Reviewed-by: Richard Henderson r~ From MAILER-DAEMON Fri Aug 04 16:15:26 2017 Received: from list by lists.gnu.org with archive (Exim 4.71) id 1ddj0I-0005Pm-L1 for mharc-qemu-arm@gnu.org; Fri, 04 Aug 2017 16:15:26 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:49167) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ddj0E-0005Nv-Ro for qemu-arm@nongnu.org; Fri, 04 Aug 2017 16:15:23 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ddj09-0000v9-Pm for qemu-arm@nongnu.org; Fri, 04 Aug 2017 16:15:22 -0400 Received: from mail-pg0-x236.google.com ([2607:f8b0:400e:c05::236]:37138) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ddj09-0000uW-KS for qemu-arm@nongnu.org; Fri, 04 Aug 2017 16:15:17 -0400 Received: by mail-pg0-x236.google.com with SMTP id y129so11842142pgy.4 for ; Fri, 04 Aug 2017 13:15:15 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=subject:to:cc:references:from:message-id:date:user-agent :mime-version:in-reply-to:content-language:content-transfer-encoding; bh=F/3idsBQJfZmQ4e1TAVDYMy5mVy5XCzsWE4BmSRenvM=; b=L3wwd35vYYxIeCX3HNmcIlm1T52yGPEOBLnfyaL0b5MRS+mTwUUJ/1K7uhOi2AH4NF lTV7QVaWB9m3qOxES3p+LiPV/F/Ue6p8PupwTPQVWct3pNKS5RpsYcBXSHE5r3cYeCFi 6vjSoV8UFXbVh8fRRUkp3TfvU2Ww3sdz8dPno= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:subject:to:cc:references:from:message-id:date :user-agent:mime-version:in-reply-to:content-language :content-transfer-encoding; bh=F/3idsBQJfZmQ4e1TAVDYMy5mVy5XCzsWE4BmSRenvM=; b=Cb0GvwKhHvC5t+RnQnTO/hLPFrdTQBC5qfTDMS21JF/z7O8kRrd1VBECsN7HAbULXr q4JXI+x3DCsEs7M7gxdXDmALBkzSxFcFRmq9E174GiEK2LzdmE40n9xGgvMM/czllw6U /BlXO0arBq5M1685P0iG9Y739eBuyDlLtd6IK0k6uUQ4dA7dtzTF0b5OWwaNAW/B06o5 TaMOebDRsD2bC4UKOduwcvzH7dNYtfWby7ik1owncW7HLLeFefcCUzvUk7ZsSpibLyjF hp8Ngk1Ftok0vltbVYv1rTBD8HoWfM6zY6dFGFRSfrROh4Jnq78zqekeSlkEiuKCNyGE xiUA== X-Gm-Message-State: AIVw110iKTq8gSMWtdrDGLyEAvSj+hINayPVj+g7EPkE1PS30WQtLEfy WCCAWynBWHkaWLDg X-Received: by 10.84.128.106 with SMTP id 97mr4168175pla.41.1501877714998; Fri, 04 Aug 2017 13:15:14 -0700 (PDT) Received: from bigtime.twiddle.net (97-126-108-236.tukw.qwest.net. [97.126.108.236]) by smtp.gmail.com with ESMTPSA id g7sm4181110pfj.29.2017.08.04.13.15.13 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 04 Aug 2017 13:15:14 -0700 (PDT) To: Peter Maydell , qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: patches@linaro.org References: <1501867249-1924-1-git-send-email-peter.maydell@linaro.org> <1501867249-1924-8-git-send-email-peter.maydell@linaro.org> From: Richard Henderson Message-ID: Date: Fri, 4 Aug 2017 13:15:13 -0700 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.2.1 MIME-Version: 1.0 In-Reply-To: <1501867249-1924-8-git-send-email-peter.maydell@linaro.org> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 7bit X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::236 Subject: Re: [Qemu-arm] [PATCH 7/8] target/arm: Allow deliver_fault() caller to specify EA bit X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 04 Aug 2017 20:15:23 -0000 On 08/04/2017 10:20 AM, Peter Maydell wrote: > For external aborts, we will want to be able to specify the EA > (external abort type) bit in the syndrome field. Allow callers of > deliver_fault() to do that by adding a field to ARMMMUFaultInfo which > we use when constructing the syndrome values. > > Signed-off-by: Peter Maydell > --- > target/arm/internals.h | 2 ++ > target/arm/op_helper.c | 10 +++++----- > 2 files changed, 7 insertions(+), 5 deletions(-) Reviewed-by: Richard Henderson r~ From MAILER-DAEMON Fri Aug 04 16:27:03 2017 Received: from list by lists.gnu.org with archive (Exim 4.71) id 1ddjBX-0000ZZ-1Z for mharc-qemu-arm@gnu.org; Fri, 04 Aug 2017 16:27:03 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:55471) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ddjBV-0000YU-3z for qemu-arm@nongnu.org; Fri, 04 Aug 2017 16:27:01 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ddjBR-000132-7l for qemu-arm@nongnu.org; Fri, 04 Aug 2017 16:27:01 -0400 Received: from mail-pg0-x232.google.com ([2607:f8b0:400e:c05::232]:34462) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ddjBR-00012c-1G for qemu-arm@nongnu.org; Fri, 04 Aug 2017 16:26:57 -0400 Received: by mail-pg0-x232.google.com with SMTP id u185so11976027pgb.1 for ; Fri, 04 Aug 2017 13:26:56 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=subject:to:cc:references:from:message-id:date:user-agent :mime-version:in-reply-to:content-language:content-transfer-encoding; bh=G+LM330PIVd/Gi9p85VJa38/0wBXPz6uMD4eqrcYiuU=; b=I/pv/GMzhjixCbPNn3yxDpeFErmQZe4zsnuPyvGX+Yh3j4dlwBKjiwCumqk7G0gB7b 01+jP1/HcgqvJGNCfDb8BR453bzKOBr6O+AB4Aopb+5ogNMZm4Z7xxEQfJRfF52B6lIf HyJ/Phqp4VXzc0eaeLon/kqyWsaWCbQU99ros= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:subject:to:cc:references:from:message-id:date :user-agent:mime-version:in-reply-to:content-language :content-transfer-encoding; bh=G+LM330PIVd/Gi9p85VJa38/0wBXPz6uMD4eqrcYiuU=; b=NDS2t0D3vr5cZ82oE0CdEHw7buNUFK+qVHNmiSZYpb9QVO/+3RPBe6wHYe48hjRE2J qnfGTDGN3DivIV4kTAUQUsgMYpTFNwHH0rylNsuaGq0y/0hdYtAKHCbfMvwy+tswU1XY 82aboxTheB7h5LlUaTN2UuqxMVSt0qHruocCYN2/sACbIW70shFb6kn+xPXh/xrw0Oum NzCWoJGyC2BnwwLpaz+kMkoLiNVvI5kdjpL0xVpaV06FY4WGsBu/EeOM03crqSzrsboZ LY75kk4z9GSaoftjS5wLiR5SSQegTJA6kgxwfM5mZK7MtxA9ZEpK65eNHWdGOZ6nK+bE puMw== X-Gm-Message-State: AIVw113DsG6nIAq+bnuAPCdki7Jfgtk4k0GkS7wsa8tA+smUEVQgUoXW 4NtenT/m6vsfcRKs X-Received: by 10.84.178.4 with SMTP id y4mr4163783plb.135.1501878416069; Fri, 04 Aug 2017 13:26:56 -0700 (PDT) Received: from bigtime.twiddle.net (97-126-108-236.tukw.qwest.net. [97.126.108.236]) by smtp.gmail.com with ESMTPSA id c69sm4089805pfd.76.2017.08.04.13.26.54 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 04 Aug 2017 13:26:55 -0700 (PDT) To: Peter Maydell , qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: patches@linaro.org References: <1501867249-1924-1-git-send-email-peter.maydell@linaro.org> <1501867249-1924-9-git-send-email-peter.maydell@linaro.org> From: Richard Henderson Message-ID: <17d709e6-7f71-1d5b-1bdd-57b0323d2bcb@linaro.org> Date: Fri, 4 Aug 2017 13:26:53 -0700 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.2.1 MIME-Version: 1.0 In-Reply-To: <1501867249-1924-9-git-send-email-peter.maydell@linaro.org> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 7bit X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::232 Subject: Re: [Qemu-arm] [PATCH 8/8] target/arm: Implement new do_transaction_failed hook X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 04 Aug 2017 20:27:02 -0000 On 08/04/2017 10:20 AM, Peter Maydell wrote: > Implement the new do_transaction_failed hook for ARM, which should > cause the CPU to take a prefetch abort or data abort. > > Signed-off-by: Peter Maydell > --- > target/arm/internals.h | 10 ++++++++++ > target/arm/cpu.c | 1 + > target/arm/op_helper.c | 43 +++++++++++++++++++++++++++++++++++++++++++ > 3 files changed, 54 insertions(+) Reviewed-by: Richard Henderson r~ From MAILER-DAEMON Fri Aug 04 21:00:08 2017 Received: from list by lists.gnu.org with archive (Exim 4.71) id 1ddnRo-0005Qe-J9 for mharc-qemu-arm@gnu.org; Fri, 04 Aug 2017 21:00:08 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:48919) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ddnRh-00056Q-AW for qemu-arm@nongnu.org; Fri, 04 Aug 2017 21:00:07 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ddnRb-0004AM-Jp for qemu-arm@nongnu.org; Fri, 04 Aug 2017 21:00:01 -0400 Received: from mail-lf0-x242.google.com ([2a00:1450:4010:c07::242]:33058) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ddnRb-00049g-Aj; Fri, 04 Aug 2017 20:59:55 -0400 Received: by mail-lf0-x242.google.com with SMTP id 65so2016128lfa.0; Fri, 04 Aug 2017 17:59:53 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=date:from:to:cc:subject:message-id:references:mime-version :content-disposition:in-reply-to:user-agent; bh=a4RooRKZtaeF8XrME918KGg1GUVvnZV/pJ168cpGpZ0=; b=QjpdhzNChFIfwoaipifwqcmzaTgoLLnqSaVdCc5OjcVB5WeIKU4+ajTYMljDQh+dc5 YIKkSkFyqr66h+XuckHT02nmFAnGk/k6Q6cJaXveGsSWorqA/8xue00Pv6qgWgw62JJH jlXUFF58Eo/AobqvjK7coko+3vE6R14RAXUyfTVQ1Cnbn7wsDg1gCtyTKwXO0USHCQx4 FQvBiR4JHXCzxCoRYgd6v7NeOcHwSDHfZQI9L06QTZB5Ol0tq0V4xCus8oLRNRqSeKXt rGF5sOjEsGrp+UfDxqjTEo+1NAUGnfKiK5ZNQm4vcf0KKRULGkcTInIfX7ic2p0T7/hd f2zA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:in-reply-to:user-agent; bh=a4RooRKZtaeF8XrME918KGg1GUVvnZV/pJ168cpGpZ0=; b=GgzW1/zJETDRsvlxFbXRzUX8WAn9RAzT9YJtgZ7AFmdBN3hlQyZAD/Uf805kgwlfUn wTLHvVa9xrsqUGbvYft5ESk4rxD2gTbB2grxelWw9B//wriJ4ztNfX708S81M3VpI7MR HJPtyMeAdBDkRo0qa6rvyORtrOItaObHQvj2eErvIXJGaY4ZZXO5ZfHRwByW9lJfQDZD DJSLoTdd7uJkqALdvj1vtVthwrtOmjelmrnQz1RrO3g3t7UueMbsX0VvLjWSPuaKzWsb aUuKz7p9ihByDwYC/MlIyOJt1VPV90I42Fgnw4KSmSg9bUOzpuDZzDpTz+HUWCn8oOqG P9Pg== X-Gm-Message-State: AIVw112enqY948vPavYEb8f9G0h2nVvGa42mD+QrN2Anhuwtf0HAHyCD Cq337yjAV5QIyA== X-Received: by 10.46.5.80 with SMTP id 77mr1454269ljf.91.1501894792210; Fri, 04 Aug 2017 17:59:52 -0700 (PDT) Received: from gmail.com (81-231-233-234-no56.tbcn.telia.com. [81.231.233.234]) by smtp.gmail.com with ESMTPSA id p76sm812394lfe.2.2017.08.04.17.59.50 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 04 Aug 2017 17:59:50 -0700 (PDT) Date: Sat, 5 Aug 2017 02:59:49 +0200 From: "Edgar E. Iglesias" To: Peter Maydell Cc: qemu-arm@nongnu.org, qemu-devel@nongnu.org, Richard Henderson , patches@linaro.org Message-ID: <20170805005949.GY4859@toto> References: <1501867249-1924-1-git-send-email-peter.maydell@linaro.org> <1501867249-1924-2-git-send-email-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1501867249-1924-2-git-send-email-peter.maydell@linaro.org> User-Agent: Mutt/1.5.24 (2015-08-30) X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4010:c07::242 Subject: Re: [Qemu-arm] [PATCH 1/8] memory.h: Move MemTxResult type to memattrs.h X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sat, 05 Aug 2017 01:00:07 -0000 On Fri, Aug 04, 2017 at 06:20:42PM +0100, Peter Maydell wrote: > Move the MemTxResult type to memattrs.h. We're going to want to > use it in cpu/qom.h, which doesn't want to include all of > memory.h. In practice MemTxResult and MemTxAttrs are pretty > closely linked since both are used for the new-style > read_with_attrs and write_with_attrs callbacks, so memattrs.h > is a reasonable home for this rather than creating a whole > new header file for it. > > Signed-off-by: Peter Maydell Reviewed-by: Edgar E. Iglesias > --- > include/exec/memattrs.h | 10 ++++++++++ > include/exec/memory.h | 10 ---------- > 2 files changed, 10 insertions(+), 10 deletions(-) > > diff --git a/include/exec/memattrs.h b/include/exec/memattrs.h > index e601061..d4a1642 100644 > --- a/include/exec/memattrs.h > +++ b/include/exec/memattrs.h > @@ -46,4 +46,14 @@ typedef struct MemTxAttrs { > */ > #define MEMTXATTRS_UNSPECIFIED ((MemTxAttrs) { .unspecified = 1 }) > > +/* New-style MMIO accessors can indicate that the transaction failed. > + * A zero (MEMTX_OK) response means success; anything else is a failure > + * of some kind. The memory subsystem will bitwise-OR together results > + * if it is synthesizing an operation from multiple smaller accesses. > + */ > +#define MEMTX_OK 0 > +#define MEMTX_ERROR (1U << 0) /* device returned an error */ > +#define MEMTX_DECODE_ERROR (1U << 1) /* nothing at that address */ > +typedef uint32_t MemTxResult; > + > #endif > diff --git a/include/exec/memory.h b/include/exec/memory.h > index 400dd44..1dcd312 100644 > --- a/include/exec/memory.h > +++ b/include/exec/memory.h > @@ -112,16 +112,6 @@ static inline void iommu_notifier_init(IOMMUNotifier *n, IOMMUNotify fn, > n->end = end; > } > > -/* New-style MMIO accessors can indicate that the transaction failed. > - * A zero (MEMTX_OK) response means success; anything else is a failure > - * of some kind. The memory subsystem will bitwise-OR together results > - * if it is synthesizing an operation from multiple smaller accesses. > - */ > -#define MEMTX_OK 0 > -#define MEMTX_ERROR (1U << 0) /* device returned an error */ > -#define MEMTX_DECODE_ERROR (1U << 1) /* nothing at that address */ > -typedef uint32_t MemTxResult; > - > /* > * Memory region callbacks > */ > -- > 2.7.4 > > From MAILER-DAEMON Fri Aug 04 21:06:40 2017 Received: from list by lists.gnu.org with archive (Exim 4.71) id 1ddnY8-0007nq-RL for mharc-qemu-arm@gnu.org; Fri, 04 Aug 2017 21:06:40 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:50270) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ddnXz-0007kB-EB for qemu-arm@nongnu.org; Fri, 04 Aug 2017 21:06:39 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ddnXt-0000bq-FU for qemu-arm@nongnu.org; Fri, 04 Aug 2017 21:06:31 -0400 Received: from mail-lf0-x242.google.com ([2a00:1450:4010:c07::242]:37489) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ddnXt-0000aL-30; Fri, 04 Aug 2017 21:06:25 -0400 Received: by mail-lf0-x242.google.com with SMTP id x16so2009301lfb.4; Fri, 04 Aug 2017 18:06:24 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=date:from:to:cc:subject:message-id:references:mime-version :content-disposition:in-reply-to:user-agent; bh=aBRatPUIDDPs6YOB+gJNHluek13IRbxV44ptJa0ULJ8=; b=rK7hfqth+gRFc3R7BWST3zOzdz9Fk2ZZhPLlam0zCG2wuHYcUvLH/Bj8jaPF0xnaN8 LmawrLLak2QSl/BEDYFuu/I3BTsND30J02LDB9W0BBsWcmeUokwC4CpqWnNxuKjg19Yw 43kh+OaJfGn8Dkvr1EZE3IQETcDPL9NRdxxuluP7wQoZ17UuzNxMv1wDYsoEXfLbTIFV a7Dh94jQa+ADTJt72kskA4ldxtfuXg8C/bFeUXvOtXWYu6felwy24hCFFPIpDXmtgK+X vLjnznzenJtBWGM+3ozijktvQf7UchHxJDKQe4R+vDnbha1W2bQCzQaHG+PN9/MGmeUK G61w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:in-reply-to:user-agent; bh=aBRatPUIDDPs6YOB+gJNHluek13IRbxV44ptJa0ULJ8=; b=FkZrOPD8ZA1dPoLpZAcTm0R5NG5DZOwagbyHvCVeYIY+y8Po3LMThJvchRqy3JN27y rg8IDqsGLVhhNR30bfLt9kini90UtLQRbH9PVhIF+N12Dy14opQFj94IvnkVce4ICXLe AGQOvon3e4N2JyQ/IO7130oLBuuvrh2K1nOliR3kNIPXZmziF2PSy7MsrjODeAJp2N61 Y3O9GQWI3TMqX5xmLgcMtfoWOunaWe2PhWZLrIuroC14UEsLHe6cLjgY8yFYb+sesiQs YBwpVVj19eY0zcllW9C1vmqsJV+vOIOyihun8fWLliuLmN9VuiD+pqS5AxL81fzWMVWU 08RQ== X-Gm-Message-State: AIVw1115Zb+YGHcweq7sj0rC6jZEnMzjRxbeJwpR+PlnTnIGGLEkMYUs NhlOI8S7FAlTjw== X-Received: by 10.46.5.141 with SMTP id 135mr1568229ljf.95.1501895183527; Fri, 04 Aug 2017 18:06:23 -0700 (PDT) Received: from gmail.com (81-231-233-234-no56.tbcn.telia.com. [81.231.233.234]) by smtp.gmail.com with ESMTPSA id x133sm774127lfd.58.2017.08.04.18.06.22 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 04 Aug 2017 18:06:22 -0700 (PDT) Date: Sat, 5 Aug 2017 03:06:22 +0200 From: "Edgar E. Iglesias" To: Peter Maydell Cc: qemu-arm@nongnu.org, qemu-devel@nongnu.org, Richard Henderson , patches@linaro.org Message-ID: <20170805010622.GZ4859@toto> References: <1501867249-1924-1-git-send-email-peter.maydell@linaro.org> <1501867249-1924-3-git-send-email-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1501867249-1924-3-git-send-email-peter.maydell@linaro.org> User-Agent: Mutt/1.5.24 (2015-08-30) X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4010:c07::242 Subject: Re: [Qemu-arm] [PATCH 2/8] cpu: Define new cpu_transaction_failed() hook X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sat, 05 Aug 2017 01:06:39 -0000 On Fri, Aug 04, 2017 at 06:20:43PM +0100, Peter Maydell wrote: > Currently we have a rather half-baked setup for allowing CPUs to > generate exceptions on accesses to invalid memory: the CPU has a > cpu_unassigned_access() hook which the memory system calls in > unassigned_mem_write() and unassigned_mem_read() if the current_cpu > pointer is non-NULL. This was originally designed before we > implemented the MemTxResult type that allows memory operations to > report a success or failure code, which is why the hook is called > right at the bottom of the memory system. The major problem with > this is that it means that the hook can be called even when the > access was not actually done by the CPU: for instance if the CPU > writes to a DMA engine register which causes the DMA engine to begin > a transaction which has been set up by the guest to operate on > invalid memory then this will casue the CPU to take an exception > incorrectly. Another minor problem is that currently if a device > returns a transaction error then this won't turn into a CPU exception > at all. > > The right way to do this is to have allow the CPU to respond > to memory system transaction failures at the point where the > CPU specific code calls into the memory system. > > Define a new QOM CPU method and utility function > cpu_transaction_failed() which is called in these cases. > The functionality here overlaps with the existing > cpu_unassigned_access() because individual target CPUs will > need some work to convert them to the new system. When this > transition is complete we can remove the old cpu_unassigned_access() > code. > > Signed-off-by: Peter Maydell > > --- > include/qom/cpu.h | 21 +++++++++++++++++++++ > 1 file changed, 21 insertions(+) > > diff --git a/include/qom/cpu.h b/include/qom/cpu.h > index 25eefea..fc54d55 100644 > --- a/include/qom/cpu.h > +++ b/include/qom/cpu.h > @@ -85,8 +85,10 @@ struct TranslationBlock; > * @has_work: Callback for checking if there is work to do. > * @do_interrupt: Callback for interrupt handling. > * @do_unassigned_access: Callback for unassigned access handling. > + * (this is deprecated: new targets should use do_transaction_failed instead) > * @do_unaligned_access: Callback for unaligned access handling, if > * the target defines #ALIGNED_ONLY. > + * @do_transaction_failed: Callback for handling failed memory transactions Looks OK but I wonder if there you might want to clarify that this is a bus/slave failure and not a failure within the CPU (e.g not an MMU fault). Anyway: Reviewed-by: Edgar E. Iglesias > * @virtio_is_big_endian: Callback to return %true if a CPU which supports > * runtime configurable endianness is currently big-endian. Non-configurable > * CPUs can use the default implementation of this method. This method should > @@ -153,6 +155,10 @@ typedef struct CPUClass { > void (*do_unaligned_access)(CPUState *cpu, vaddr addr, > MMUAccessType access_type, > int mmu_idx, uintptr_t retaddr); > + void (*do_transaction_failed)(CPUState *cpu, hwaddr physaddr, vaddr addr, > + unsigned size, MMUAccessType access_type, > + int mmu_idx, MemTxAttrs attrs, > + MemTxResult response, uintptr_t retaddr); > bool (*virtio_is_big_endian)(CPUState *cpu); > int (*memory_rw_debug)(CPUState *cpu, vaddr addr, > uint8_t *buf, int len, bool is_write); > @@ -837,6 +843,21 @@ static inline void cpu_unaligned_access(CPUState *cpu, vaddr addr, > > cc->do_unaligned_access(cpu, addr, access_type, mmu_idx, retaddr); > } > + > +static inline void cpu_transaction_failed(CPUState *cpu, hwaddr physaddr, > + vaddr addr, unsigned size, > + MMUAccessType access_type, > + int mmu_idx, MemTxAttrs attrs, > + MemTxResult response, > + uintptr_t retaddr) > +{ > + CPUClass *cc = CPU_GET_CLASS(cpu); > + > + if (cc->do_transaction_failed) { > + cc->do_transaction_failed(cpu, physaddr, addr, size, access_type, > + mmu_idx, attrs, response, retaddr); > + } > +} > #endif > > #endif /* NEED_CPU_H */ > -- > 2.7.4 > > From MAILER-DAEMON Fri Aug 04 21:12:17 2017 Received: from list by lists.gnu.org with archive (Exim 4.71) id 1ddndZ-0001wu-Dy for mharc-qemu-arm@gnu.org; Fri, 04 Aug 2017 21:12:17 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:51502) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ddndX-0001wi-4f for qemu-arm@nongnu.org; Fri, 04 Aug 2017 21:12:16 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ddndU-00065m-GH for qemu-arm@nongnu.org; Fri, 04 Aug 2017 21:12:15 -0400 Received: from mail-lf0-x243.google.com ([2a00:1450:4010:c07::243]:35213) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ddndU-00063o-3R; Fri, 04 Aug 2017 21:12:12 -0400 Received: by mail-lf0-x243.google.com with SMTP id w199so2013764lff.2; Fri, 04 Aug 2017 18:12:12 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=date:from:to:cc:subject:message-id:references:mime-version :content-disposition:in-reply-to:user-agent; bh=Qs0jVTCab+QodIl4GQjZplgctPJ4HHu8RQ+yXaFkVHU=; b=FTYKsVesGxRq/mVK4eJ+XDth0Mqguyr87Iewe7Px4wkdP/M7kvT3np36KebU9R+bwj 4bRIot1dvx4tHtfgc64rpq1aKoyBUTYZCz1Je/L2VrV2qZNcp7Sk11VFfnifN7bm9c3Z /UTpJ5UWTd+Ua69RVOgp6VUB9G+SX1j3pPFhN2TIW0b367YfNQf8XCBduatMbF3ZdZbu GiQOGILPn5g+KmrShxIDDf2kynVRrRggSG4rfVAmfzW4GajmmiDsw7JFscbkT8anIlJi 13ks3z8E82pCLn1n35OKo8GsmWVtCQVjUZX8I517uYrWHKQjEcjaGyoPLxdnf2t+KrAt eBHg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:in-reply-to:user-agent; bh=Qs0jVTCab+QodIl4GQjZplgctPJ4HHu8RQ+yXaFkVHU=; b=oLEice9G8TA2auHVIl2JF5vbEfrogz5WqxmDDYAffkgfVx2zJYLz7EV3DLaGU2kRWR TM7mp4mL9sJjjwVBOu3e5Ji9E/9Lug1PnBBZ/yOirfwq1AinmmbAV837ikm4fVU4cFN0 Sz18Ynt/R8i9n3dtNn7QwsM1FoLlBpL9yKsZmdY6LX9WxoTpFv3lOdesf5zhGmpNRnRx Hhy5KdsXSaZY0Eepj0DP5mCAH7BvWyuSAb0dj4COR2NwABxdWgqEi0gV89fO+TsdGO8J E/zu3M0YSbiA3Td+LYYwYDGKNncKmkbAnR/LuIlYeb3bXhANNutZbZlp7oWwHEg6dwS1 c1HQ== X-Gm-Message-State: AHYfb5jvzUsqUZguV6vvx2zimDQkGeUIoSNrRItKcbqhrG01x43uMdU1 6f+N7g0iK9yvRg== X-Received: by 10.25.207.85 with SMTP id f82mr1442331lfg.2.1501895530632; Fri, 04 Aug 2017 18:12:10 -0700 (PDT) Received: from gmail.com (81-231-233-234-no56.tbcn.telia.com. [81.231.233.234]) by smtp.gmail.com with ESMTPSA id o142sm799864lfe.56.2017.08.04.18.12.09 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 04 Aug 2017 18:12:09 -0700 (PDT) Date: Sat, 5 Aug 2017 03:12:09 +0200 From: "Edgar E. Iglesias" To: Peter Maydell Cc: qemu-arm@nongnu.org, qemu-devel@nongnu.org, Richard Henderson , patches@linaro.org Message-ID: <20170805011209.GA4859@toto> References: <1501867249-1924-1-git-send-email-peter.maydell@linaro.org> <1501867249-1924-3-git-send-email-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1501867249-1924-3-git-send-email-peter.maydell@linaro.org> User-Agent: Mutt/1.5.24 (2015-08-30) X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4010:c07::243 Subject: Re: [Qemu-arm] [PATCH 2/8] cpu: Define new cpu_transaction_failed() hook X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sat, 05 Aug 2017 01:12:16 -0000 On Fri, Aug 04, 2017 at 06:20:43PM +0100, Peter Maydell wrote: > Currently we have a rather half-baked setup for allowing CPUs to > generate exceptions on accesses to invalid memory: the CPU has a > cpu_unassigned_access() hook which the memory system calls in > unassigned_mem_write() and unassigned_mem_read() if the current_cpu > pointer is non-NULL. This was originally designed before we > implemented the MemTxResult type that allows memory operations to > report a success or failure code, which is why the hook is called > right at the bottom of the memory system. The major problem with > this is that it means that the hook can be called even when the > access was not actually done by the CPU: for instance if the CPU > writes to a DMA engine register which causes the DMA engine to begin > a transaction which has been set up by the guest to operate on > invalid memory then this will casue the CPU to take an exception > incorrectly. Another minor problem is that currently if a device > returns a transaction error then this won't turn into a CPU exception > at all. > > The right way to do this is to have allow the CPU to respond > to memory system transaction failures at the point where the > CPU specific code calls into the memory system. > > Define a new QOM CPU method and utility function > cpu_transaction_failed() which is called in these cases. > The functionality here overlaps with the existing > cpu_unassigned_access() because individual target CPUs will > need some work to convert them to the new system. When this > transition is complete we can remove the old cpu_unassigned_access() > code. BTW, a question. I don't know of any from memory but does any arch have the ability to report the payload that failed for stores? I guess it's easy enough to add that if needed though. > > Signed-off-by: Peter Maydell > --- > include/qom/cpu.h | 21 +++++++++++++++++++++ > 1 file changed, 21 insertions(+) > > diff --git a/include/qom/cpu.h b/include/qom/cpu.h > index 25eefea..fc54d55 100644 > --- a/include/qom/cpu.h > +++ b/include/qom/cpu.h > @@ -85,8 +85,10 @@ struct TranslationBlock; > * @has_work: Callback for checking if there is work to do. > * @do_interrupt: Callback for interrupt handling. > * @do_unassigned_access: Callback for unassigned access handling. > + * (this is deprecated: new targets should use do_transaction_failed instead) > * @do_unaligned_access: Callback for unaligned access handling, if > * the target defines #ALIGNED_ONLY. > + * @do_transaction_failed: Callback for handling failed memory transactions > * @virtio_is_big_endian: Callback to return %true if a CPU which supports > * runtime configurable endianness is currently big-endian. Non-configurable > * CPUs can use the default implementation of this method. This method should > @@ -153,6 +155,10 @@ typedef struct CPUClass { > void (*do_unaligned_access)(CPUState *cpu, vaddr addr, > MMUAccessType access_type, > int mmu_idx, uintptr_t retaddr); > + void (*do_transaction_failed)(CPUState *cpu, hwaddr physaddr, vaddr addr, > + unsigned size, MMUAccessType access_type, > + int mmu_idx, MemTxAttrs attrs, > + MemTxResult response, uintptr_t retaddr); > bool (*virtio_is_big_endian)(CPUState *cpu); > int (*memory_rw_debug)(CPUState *cpu, vaddr addr, > uint8_t *buf, int len, bool is_write); > @@ -837,6 +843,21 @@ static inline void cpu_unaligned_access(CPUState *cpu, vaddr addr, > > cc->do_unaligned_access(cpu, addr, access_type, mmu_idx, retaddr); > } > + > +static inline void cpu_transaction_failed(CPUState *cpu, hwaddr physaddr, > + vaddr addr, unsigned size, > + MMUAccessType access_type, > + int mmu_idx, MemTxAttrs attrs, > + MemTxResult response, > + uintptr_t retaddr) > +{ > + CPUClass *cc = CPU_GET_CLASS(cpu); > + > + if (cc->do_transaction_failed) { > + cc->do_transaction_failed(cpu, physaddr, addr, size, access_type, > + mmu_idx, attrs, response, retaddr); > + } > +} > #endif > > #endif /* NEED_CPU_H */ > -- > 2.7.4 > > From MAILER-DAEMON Fri Aug 04 21:16:00 2017 Received: from list by lists.gnu.org with archive (Exim 4.71) id 1ddnhA-0003nH-Rk for mharc-qemu-arm@gnu.org; Fri, 04 Aug 2017 21:16:00 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:52464) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ddnh7-0003ma-Nc for qemu-arm@nongnu.org; Fri, 04 Aug 2017 21:15:58 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ddnh5-0000we-1a for qemu-arm@nongnu.org; Fri, 04 Aug 2017 21:15:57 -0400 Received: from mail-lf0-x242.google.com ([2a00:1450:4010:c07::242]:37689) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ddnh4-0000u6-M1; Fri, 04 Aug 2017 21:15:54 -0400 Received: by mail-lf0-x242.google.com with SMTP id x16so2016960lfb.4; Fri, 04 Aug 2017 18:15:54 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=date:from:to:cc:subject:message-id:references:mime-version :content-disposition:in-reply-to:user-agent; bh=nCytR8/ihAtqRJi6UyUEGrHlo92hiL6bMzDIVBLRLac=; b=kbcKm1ZKqce06+qkn1WBPrVPzLcm/1BqY5ayy9JMmejvpVxfO5pEvTyXxOzB/1PzBH /KJrTlrU89KFsg4Acemr/RLnHriW+4QT+KRbiyhc0nTfMnD2DuUlUMX5IfedCXsH6bs/ opJ1vxIlYX40Wn39efFUChbGX1Y6CB6wfW+HJJC5hkaHBG5VbsKD/eKfIv5m9++roMfF 8ArOJGbHLqWL+7GjG9WtG4759lGImRS3b8iPcAXLuMim70KBPuSsrTzPT5Fqez5G7fW2 e0HtYVJiDN/07C34l9u0bsTRtbnPA/d9OWLL2ROtgdm7q1H6ZsO24kPnsMW7UuNcCljf XDdw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:in-reply-to:user-agent; bh=nCytR8/ihAtqRJi6UyUEGrHlo92hiL6bMzDIVBLRLac=; b=gq9GxS7Cj+lGuYiCFzrPSr9zdKDKcbOcAEQl6ve0fsY7EtRnFEBgKSRkdpIFKupXHG s0spjfDne0dKEsd3OQXzwAbhnrxTmAWIEQvjHeYPBCnxG8dkjy4IeVe7vTnYJdkcxt9z Mpr1Xtg9toFHXnSkR56X6tKacQoCB50GY9hlZn+X5KRfHSUbsj1FrrxraT4OG24E1Ujh S8jrBpxuDc35lyNxCc7TSaj8+y9mXmy1fAYzZYrE229BfWiDnla3t0o/KRsBZVFKcJIR MpT4tiDxIKcioJtFQaw7u1pZAeXgkJc6NkcQA3TIb2ykAt5TZbAfW/eLhuv6y5/XtZnz UEEQ== X-Gm-Message-State: AHYfb5gZNyuDPhLMpi7GtfeI+8CLyxe+W55DpRQ+ScBcFyKnkjghw/S8 KJEQ/lDbQL7e4w== X-Received: by 10.25.146.9 with SMTP id u9mr1506816lfd.88.1501895753255; Fri, 04 Aug 2017 18:15:53 -0700 (PDT) Received: from gmail.com (81-231-233-234-no56.tbcn.telia.com. [81.231.233.234]) by smtp.gmail.com with ESMTPSA id y1sm1382421lja.24.2017.08.04.18.15.52 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 04 Aug 2017 18:15:52 -0700 (PDT) Date: Sat, 5 Aug 2017 03:15:52 +0200 From: "Edgar E. Iglesias" To: Peter Maydell Cc: qemu-arm@nongnu.org, qemu-devel@nongnu.org, Richard Henderson , patches@linaro.org Message-ID: <20170805011551.GB4859@toto> References: <1501867249-1924-1-git-send-email-peter.maydell@linaro.org> <1501867249-1924-4-git-send-email-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1501867249-1924-4-git-send-email-peter.maydell@linaro.org> User-Agent: Mutt/1.5.24 (2015-08-30) X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4010:c07::242 Subject: Re: [Qemu-arm] [PATCH 3/8] cputlb: Support generating CPU exceptions on memory transaction failures X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sat, 05 Aug 2017 01:15:59 -0000 On Fri, Aug 04, 2017 at 06:20:44PM +0100, Peter Maydell wrote: > Call the new cpu_transaction_failed() hook at the places where > CPU generated code interacts with the memory system: > io_readx() > io_writex() > get_page_addr_code() > > Any access from C code (eg via cpu_physical_memory_rw(), > address_space_rw(), ld/st_*_phys()) will *not* trigger CPU exceptions > via cpu_transaction_failed(). Handling for transactions failures for > this kind of call should be done by using a function which returns a > MemTxResult and treating the failure case appropriately in the > calling code. > > In an ideal world we would not generate CPU exceptions for > instruction fetch failures in get_page_addr_code() but instead wait > until the code translation process tried a load and it failed; > however that change would require too great a restructuring and > redesign to attempt at this point. You're right but onsidering the lack of models for I caches and prefetching, I don't think that matters much... Reviewed-by: Edgar E. Iglesias > > Signed-off-by: Peter Maydell > --- > softmmu_template.h | 4 ++-- > accel/tcg/cputlb.c | 32 ++++++++++++++++++++++++++++++-- > 2 files changed, 32 insertions(+), 4 deletions(-) > > diff --git a/softmmu_template.h b/softmmu_template.h > index 4a2b665..d756329 100644 > --- a/softmmu_template.h > +++ b/softmmu_template.h > @@ -101,7 +101,7 @@ static inline DATA_TYPE glue(io_read, SUFFIX)(CPUArchState *env, > uintptr_t retaddr) > { > CPUIOTLBEntry *iotlbentry = &env->iotlb[mmu_idx][index]; > - return io_readx(env, iotlbentry, addr, retaddr, DATA_SIZE); > + return io_readx(env, iotlbentry, mmu_idx, addr, retaddr, DATA_SIZE); > } > #endif > > @@ -262,7 +262,7 @@ static inline void glue(io_write, SUFFIX)(CPUArchState *env, > uintptr_t retaddr) > { > CPUIOTLBEntry *iotlbentry = &env->iotlb[mmu_idx][index]; > - return io_writex(env, iotlbentry, val, addr, retaddr, DATA_SIZE); > + return io_writex(env, iotlbentry, mmu_idx, val, addr, retaddr, DATA_SIZE); > } > > void helper_le_st_name(CPUArchState *env, target_ulong addr, DATA_TYPE val, > diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c > index 85635ae..e72415a 100644 > --- a/accel/tcg/cputlb.c > +++ b/accel/tcg/cputlb.c > @@ -747,6 +747,7 @@ static inline ram_addr_t qemu_ram_addr_from_host_nofail(void *ptr) > } > > static uint64_t io_readx(CPUArchState *env, CPUIOTLBEntry *iotlbentry, > + int mmu_idx, > target_ulong addr, uintptr_t retaddr, int size) > { > CPUState *cpu = ENV_GET_CPU(env); > @@ -754,6 +755,7 @@ static uint64_t io_readx(CPUArchState *env, CPUIOTLBEntry *iotlbentry, > MemoryRegion *mr = iotlb_to_region(cpu, physaddr, iotlbentry->attrs); > uint64_t val; > bool locked = false; > + MemTxResult r; > > physaddr = (physaddr & TARGET_PAGE_MASK) + addr; > cpu->mem_io_pc = retaddr; > @@ -767,7 +769,12 @@ static uint64_t io_readx(CPUArchState *env, CPUIOTLBEntry *iotlbentry, > qemu_mutex_lock_iothread(); > locked = true; > } > - memory_region_dispatch_read(mr, physaddr, &val, size, iotlbentry->attrs); > + r = memory_region_dispatch_read(mr, physaddr, > + &val, size, iotlbentry->attrs); > + if (r != MEMTX_OK) { > + cpu_transaction_failed(cpu, physaddr, addr, size, MMU_DATA_LOAD, > + mmu_idx, iotlbentry->attrs, r, retaddr); > + } > if (locked) { > qemu_mutex_unlock_iothread(); > } > @@ -776,6 +783,7 @@ static uint64_t io_readx(CPUArchState *env, CPUIOTLBEntry *iotlbentry, > } > > static void io_writex(CPUArchState *env, CPUIOTLBEntry *iotlbentry, > + int mmu_idx, > uint64_t val, target_ulong addr, > uintptr_t retaddr, int size) > { > @@ -783,6 +791,7 @@ static void io_writex(CPUArchState *env, CPUIOTLBEntry *iotlbentry, > hwaddr physaddr = iotlbentry->addr; > MemoryRegion *mr = iotlb_to_region(cpu, physaddr, iotlbentry->attrs); > bool locked = false; > + MemTxResult r; > > physaddr = (physaddr & TARGET_PAGE_MASK) + addr; > if (mr != &io_mem_rom && mr != &io_mem_notdirty && !cpu->can_do_io) { > @@ -795,7 +804,12 @@ static void io_writex(CPUArchState *env, CPUIOTLBEntry *iotlbentry, > qemu_mutex_lock_iothread(); > locked = true; > } > - memory_region_dispatch_write(mr, physaddr, val, size, iotlbentry->attrs); > + r = memory_region_dispatch_write(mr, physaddr, > + val, size, iotlbentry->attrs); > + if (r != MEMTX_OK) { > + cpu_transaction_failed(cpu, physaddr, addr, size, MMU_DATA_STORE, > + mmu_idx, iotlbentry->attrs, r, retaddr); > + } > if (locked) { > qemu_mutex_unlock_iothread(); > } > @@ -845,6 +859,7 @@ tb_page_addr_t get_page_addr_code(CPUArchState *env, target_ulong addr) > MemoryRegion *mr; > CPUState *cpu = ENV_GET_CPU(env); > CPUIOTLBEntry *iotlbentry; > + hwaddr physaddr; > > index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1); > mmu_idx = cpu_mmu_index(env, true); > @@ -868,6 +883,19 @@ tb_page_addr_t get_page_addr_code(CPUArchState *env, target_ulong addr) > } > qemu_mutex_unlock_iothread(); > > + /* Give the new-style cpu_transaction_failed() hook first chance > + * to handle this. > + * This is not the ideal place to detect and generate CPU > + * exceptions for instruction fetch failure (for instance > + * we don't know the length of the access that the CPU would > + * use, and it would be better to go ahead and try the access > + * and use the MemTXResult it produced). However it is the > + * simplest place we have currently available for the check. > + */ > + physaddr = (iotlbentry->addr & TARGET_PAGE_MASK) + addr; > + cpu_transaction_failed(cpu, physaddr, addr, 0, MMU_INST_FETCH, mmu_idx, > + iotlbentry->attrs, MEMTX_DECODE_ERROR, 0); > + > cpu_unassigned_access(cpu, addr, false, true, 0, 4); > /* The CPU's unassigned access hook might have longjumped out > * with an exception. If it didn't (or there was no hook) then > -- > 2.7.4 > > From MAILER-DAEMON Fri Aug 04 21:23:52 2017 Received: from list by lists.gnu.org with archive (Exim 4.71) id 1ddnom-00069m-0A for mharc-qemu-arm@gnu.org; Fri, 04 Aug 2017 21:23:52 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:54446) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ddnoj-00069S-B5 for qemu-arm@nongnu.org; Fri, 04 Aug 2017 21:23:50 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ddnog-0001Ij-Mn for qemu-arm@nongnu.org; Fri, 04 Aug 2017 21:23:49 -0400 Received: from mail-lf0-x241.google.com ([2a00:1450:4010:c07::241]:34681) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ddnog-0001H0-9d; Fri, 04 Aug 2017 21:23:46 -0400 Received: by mail-lf0-x241.google.com with SMTP id o85so2027689lff.1; Fri, 04 Aug 2017 18:23:46 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=date:from:to:cc:subject:message-id:references:mime-version :content-disposition:in-reply-to:user-agent; bh=I1XEaGXDB74cbg1drjQ03i0670bAVsb1/miUC+sN3k0=; b=fNNaNkq3oOfH40HCKGsmca1bgnDJdN54ttcWbgmopciC+4OIf1HHtVX1E4yjL+TcZj RsFbZX2Juwc9KfP6qyjxnDDNRfpUiklWy7aA+gs2sf7UPQOKYqUaYBjfzwKLnJpmdLNx zmACy8vOZHVyb7vsw4s10aa8pcVY3F1lEuBtr0nQWdvRag2RaazW0gGXLnhXbc3e/iAy UtD0Vq3+OyBbl5A4Mfp5zvOas3GKbHD1w4zlIq79UzMe7WT5Ggr/00Z29UoBbsO8r85g NYjCrK4guUR6XmtSmfBNhvlFycDnFDv8YFNRpoUJes9Ab3tE+BxWvxm8C5nsw4WFJpfc dXzw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:in-reply-to:user-agent; bh=I1XEaGXDB74cbg1drjQ03i0670bAVsb1/miUC+sN3k0=; b=V3FXKJUlXdAYxaUj/93a3PzFS02hVbuSurE74yrR+vazw1Msax5Qc/QSLKS9+OZYEg ++usWrZLcwKY2UZf86temDBrXrgI6lDts4O05z8jRvB8IUX7kt8+I2F6JzQB2wGj8eVa vvaH2K3ldCo9pWm5yQwE7zeVGqpCgPD9TJQA1XWUzCnJRpgclfMlzgLjBH0vT3g8JUNC k5jFVkwyjzf/wQSt3cr54ZUjmWCAf00/oiDUAz+VNEHU9F4pfctyt4pP19lDFnQl4QHR oE81Rgd4kldR8XA8ZzF+pzbFvPdwT3XPKb5DvuxCuiqAVBBymvLp0DKRJirZfmWcpUfW adhA== X-Gm-Message-State: AHYfb5ifwtpXZNKZCVyZBOn2Df3ybS/QSSSDewPn6ifr3NoiE1FxER27 0SasT3tlj5smvA== X-Received: by 10.46.13.26 with SMTP id 26mr1335593ljn.117.1501896224788; Fri, 04 Aug 2017 18:23:44 -0700 (PDT) Received: from gmail.com (81-231-233-234-no56.tbcn.telia.com. [81.231.233.234]) by smtp.gmail.com with ESMTPSA id r8sm787580lff.81.2017.08.04.18.23.43 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 04 Aug 2017 18:23:43 -0700 (PDT) Date: Sat, 5 Aug 2017 03:23:43 +0200 From: "Edgar E. Iglesias" To: Peter Maydell Cc: qemu-arm@nongnu.org, qemu-devel@nongnu.org, Richard Henderson , patches@linaro.org Message-ID: <20170805012343.GC4859@toto> References: <1501867249-1924-1-git-send-email-peter.maydell@linaro.org> <1501867249-1924-5-git-send-email-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1501867249-1924-5-git-send-email-peter.maydell@linaro.org> User-Agent: Mutt/1.5.24 (2015-08-30) X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4010:c07::241 Subject: Re: [Qemu-arm] [PATCH 4/8] boards.h: Define new flag ignore_memory_transaction_failures X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sat, 05 Aug 2017 01:23:50 -0000 On Fri, Aug 04, 2017 at 06:20:45PM +0100, Peter Maydell wrote: > Define a new MachineClass field ignore_memory_transaction_failures. > If this is flag is true then the CPU will ignore memory transaction > failures which should cause the CPU to take an exception due to an > access to an unassigned physical address; the transaction will > instead return zero (for a read) or be ignored (for a write). This > should be set only by legacy board models which rely on the old > RAZ/WI behaviour for handling devices that QEMU does not yet model. > New board models should instead use "unimplemented-device" for all > memory ranges where the guest will attempt to probe for a device that > QEMU doesn't implement and a stub device is required. > > We need this for ARM boards, where we're about to implement support for > generating external aborts on memory transaction failures. Too many > of our legacy board models rely on the RAZ/WI behaviour and we > would break currently working guests when their "probe for device" > code provoked an external abort rather than a RAZ. > > Signed-off-by: Peter Maydell Reviewed-by: Edgar E. Iglesias > --- > include/hw/boards.h | 11 +++++++++++ > include/qom/cpu.h | 7 ++++++- > qom/cpu.c | 7 +++++++ > 3 files changed, 24 insertions(+), 1 deletion(-) > > diff --git a/include/hw/boards.h b/include/hw/boards.h > index 3363dd1..7f044d1 100644 > --- a/include/hw/boards.h > +++ b/include/hw/boards.h > @@ -131,6 +131,16 @@ typedef struct { > * size than the target architecture's minimum. (Attempting to create > * such a CPU will fail.) Note that changing this is a migration > * compatibility break for the machine. > + * @ignore_memory_transaction_failures: > + * If this is flag is true then the CPU will ignore memory transaction > + * failures which should cause the CPU to take an exception due to an > + * access to an unassigned physical address; the transaction will instead > + * return zero (for a read) or be ignored (for a write). This should be > + * set only by legacy board models which rely on the old RAZ/WI behaviour > + * for handling devices that QEMU does not yet model. New board models > + * should instead use "unimplemented-device" for all memory ranges where > + * the guest will attempt to probe for a device that QEMU doesn't > + * implement and a stub device is required. > */ > struct MachineClass { > /*< private >*/ > @@ -171,6 +181,7 @@ struct MachineClass { > bool rom_file_has_mr; > int minimum_page_bits; > bool has_hotpluggable_cpus; > + bool ignore_memory_transaction_failures; > int numa_mem_align_shift; > void (*numa_auto_assign_ram)(MachineClass *mc, NodeInfo *nodes, > int nb_nodes, ram_addr_t size); > diff --git a/include/qom/cpu.h b/include/qom/cpu.h > index fc54d55..8cff86f 100644 > --- a/include/qom/cpu.h > +++ b/include/qom/cpu.h > @@ -311,6 +311,9 @@ struct qemu_work_item; > * @trace_dstate_delayed: Delayed changes to trace_dstate (includes all changes > * to @trace_dstate). > * @trace_dstate: Dynamic tracing state of events for this vCPU (bitmask). > + * @ignore_memory_transaction_failures: Cached copy of the MachineState > + * flag of the same name: allows the board to suppress calling of the > + * CPU do_transaction_failed hook function. > * > * State of one CPU core or thread. > */ > @@ -397,6 +400,8 @@ struct CPUState { > */ > bool throttle_thread_scheduled; > > + bool ignore_memory_transaction_failures; > + > /* Note that this is accessed at the start of every TB via a negative > offset from AREG0. Leave this field at the end so as to make the > (absolute value) offset as small as possible. This reduces code > @@ -853,7 +858,7 @@ static inline void cpu_transaction_failed(CPUState *cpu, hwaddr physaddr, > { > CPUClass *cc = CPU_GET_CLASS(cpu); > > - if (cc->do_transaction_failed) { > + if (!cpu->ignore_memory_transaction_failures && cc->do_transaction_failed) { > cc->do_transaction_failed(cpu, physaddr, addr, size, access_type, > mmu_idx, attrs, response, retaddr); > } > diff --git a/qom/cpu.c b/qom/cpu.c > index 4f38db0..d8dcf64 100644 > --- a/qom/cpu.c > +++ b/qom/cpu.c > @@ -29,6 +29,7 @@ > #include "exec/cpu-common.h" > #include "qemu/error-report.h" > #include "sysemu/sysemu.h" > +#include "hw/boards.h" > #include "hw/qdev-properties.h" > #include "trace-root.h" > > @@ -360,6 +361,12 @@ static void cpu_common_parse_features(const char *typename, char *features, > static void cpu_common_realizefn(DeviceState *dev, Error **errp) > { > CPUState *cpu = CPU(dev); > + Object *machine = qdev_get_machine(); > + ObjectClass *oc = object_get_class(machine); > + MachineClass *mc = MACHINE_CLASS(oc); > + > + cpu->ignore_memory_transaction_failures = > + mc->ignore_memory_transaction_failures; > > if (dev->hotplugged) { > cpu_synchronize_post_init(cpu); > -- > 2.7.4 > > From MAILER-DAEMON Fri Aug 04 21:24:49 2017 Received: from list by lists.gnu.org with archive (Exim 4.71) id 1ddnph-00073k-Af for mharc-qemu-arm@gnu.org; Fri, 04 Aug 2017 21:24:49 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:54710) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ddnpd-0006t4-O8 for qemu-arm@nongnu.org; Fri, 04 Aug 2017 21:24:48 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ddnpb-0003Bt-Gv for qemu-arm@nongnu.org; Fri, 04 Aug 2017 21:24:45 -0400 Received: from mail-lf0-x241.google.com ([2a00:1450:4010:c07::241]:37869) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ddnpb-00039C-45; Fri, 04 Aug 2017 21:24:43 -0400 Received: by mail-lf0-x241.google.com with SMTP id x16so2023368lfb.4; Fri, 04 Aug 2017 18:24:43 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=date:from:to:cc:subject:message-id:references:mime-version :content-disposition:in-reply-to:user-agent; bh=iCzMouK0rE7cqPKhaHckj5lf8KO8XwVsnifh0s6z4fo=; b=ebaDtdYEq4T8RyDKlYaQ4aOWUcTqgWlRr3Dt+S/UZZsK4udOJVxOLQ4r+r87iUSwY1 hXZpqs6fJ1ody1JePbPJjY4U+yPc0KAZuoZ96SVuDsOt1OzfZJW8npPI7TVrIKjFAmPy K3YMTWv/IN5DtKLgU39sxX2844QM7O23Aj2n1ZZZVCxdC4CP+ByXRG0zryVdpOp5Vgic 6GYY32OmNEhG7Gic6qD+28gYtqv58z5mEvj/zr0tZcCXFM0lBnyZY5cwqdO+2oxnswQE 0Qyz+loIZA/6TGwM+T70OLo+ckCXr1CwLFxgM7XHC5XML5bkwBZJIq/mA1tUmsk4yyIM GoWw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:in-reply-to:user-agent; bh=iCzMouK0rE7cqPKhaHckj5lf8KO8XwVsnifh0s6z4fo=; b=ryYx94aBkm5Y8d0yCNnNDfYnU/sfRss6hibaWoOVrOBcGukRysWXdB4aE3dBx/pA1m aDNNjwEivhonIO9H7G56v1rjdwQbFYRxicBggCMYqT08dPx0Rip4O41GjFljdamP70L9 TpZZadCONiU90Kg9NN4GyxeIsmenYK+sdBHlE5fPrtT+VMPs6iY0yVvv0fSRerKgCF1G vzW8q/o3VBA/XmTwtwbK5MlWTl16JPqi781WkX7S5YIG+rnKmr/NpZRutswYTyvYxWfw VBa1haOloQtcCV1IwX1PFcth8CkaUWnCY24Y/XrqdsrSCPt/h2v7CWL2JhuS42wcZSDQ pL2w== X-Gm-Message-State: AHYfb5g/l9jnZLIij2T61fc8s1ZTZjdc/SycCdiE9L/ewKljmh3XWuth 2uQSgLvSLCYcuriA X-Received: by 10.25.40.147 with SMTP id o141mr1156837lfo.262.1501896281447; Fri, 04 Aug 2017 18:24:41 -0700 (PDT) Received: from gmail.com (81-231-233-234-no56.tbcn.telia.com. [81.231.233.234]) by smtp.gmail.com with ESMTPSA id y10sm1382259lja.49.2017.08.04.18.24.40 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 04 Aug 2017 18:24:40 -0700 (PDT) Date: Sat, 5 Aug 2017 03:24:40 +0200 From: "Edgar E. Iglesias" To: Peter Maydell Cc: qemu-arm@nongnu.org, qemu-devel@nongnu.org, Richard Henderson , patches@linaro.org Message-ID: <20170805012440.GD4859@toto> References: <1501867249-1924-1-git-send-email-peter.maydell@linaro.org> <1501867249-1924-6-git-send-email-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1501867249-1924-6-git-send-email-peter.maydell@linaro.org> User-Agent: Mutt/1.5.24 (2015-08-30) X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4010:c07::241 Subject: Re: [Qemu-arm] [PATCH 5/8] hw/arm: Set ignore_memory_transaction_failures for most ARM boards X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sat, 05 Aug 2017 01:24:48 -0000 On Fri, Aug 04, 2017 at 06:20:46PM +0100, Peter Maydell wrote: > Set the MachineClass flag ignore_memory_transaction_failures > for almost all ARM boards. This means they retain the legacy > behaviour that accesses to unimplemented addresses will RAZ/WI > rather than aborting, when a subsequent commit adds support > for external aborts. > > The exceptions are: > * virt -- we know that guests won't try to prod devices > that we don't describe in the device tree or ACPI tables > * mps2 -- this board was written to use unimplemented-device > for all the ranges with devices we don't yet handle > > New boards should not set the flag, but instead be written > like the mps2. For the Xilinx boards: Reviewed-by: Edgar E. Iglesias > > Signed-off-by: Peter Maydell > --- > hw/arm/aspeed.c | 3 +++ > hw/arm/collie.c | 1 + > hw/arm/cubieboard.c | 1 + > hw/arm/digic_boards.c | 1 + > hw/arm/exynos4_boards.c | 2 ++ > hw/arm/gumstix.c | 2 ++ > hw/arm/highbank.c | 2 ++ > hw/arm/imx25_pdk.c | 1 + > hw/arm/integratorcp.c | 1 + > hw/arm/kzm.c | 1 + > hw/arm/mainstone.c | 1 + > hw/arm/musicpal.c | 1 + > hw/arm/netduino2.c | 1 + > hw/arm/nseries.c | 2 ++ > hw/arm/omap_sx1.c | 2 ++ > hw/arm/palm.c | 1 + > hw/arm/raspi.c | 1 + > hw/arm/realview.c | 4 ++++ > hw/arm/sabrelite.c | 1 + > hw/arm/spitz.c | 4 ++++ > hw/arm/stellaris.c | 2 ++ > hw/arm/tosa.c | 1 + > hw/arm/versatilepb.c | 2 ++ > hw/arm/vexpress.c | 1 + > hw/arm/xilinx_zynq.c | 1 + > hw/arm/xlnx-ep108.c | 2 ++ > hw/arm/z2.c | 1 + > 27 files changed, 43 insertions(+) > > diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c > index 0c5635f..ab895ad 100644 > --- a/hw/arm/aspeed.c > +++ b/hw/arm/aspeed.c > @@ -270,6 +270,7 @@ static void palmetto_bmc_class_init(ObjectClass *oc, void *data) > mc->no_floppy = 1; > mc->no_cdrom = 1; > mc->no_parallel = 1; > + mc->ignore_memory_transaction_failures = true; > } > > static const TypeInfo palmetto_bmc_type = { > @@ -302,6 +303,7 @@ static void ast2500_evb_class_init(ObjectClass *oc, void *data) > mc->no_floppy = 1; > mc->no_cdrom = 1; > mc->no_parallel = 1; > + mc->ignore_memory_transaction_failures = true; > } > > static const TypeInfo ast2500_evb_type = { > @@ -326,6 +328,7 @@ static void romulus_bmc_class_init(ObjectClass *oc, void *data) > mc->no_floppy = 1; > mc->no_cdrom = 1; > mc->no_parallel = 1; > + mc->ignore_memory_transaction_failures = true; > } > > static const TypeInfo romulus_bmc_type = { > diff --git a/hw/arm/collie.c b/hw/arm/collie.c > index 2e69531..8830192 100644 > --- a/hw/arm/collie.c > +++ b/hw/arm/collie.c > @@ -64,6 +64,7 @@ static void collie_machine_init(MachineClass *mc) > { > mc->desc = "Sharp SL-5500 (Collie) PDA (SA-1110)"; > mc->init = collie_init; > + mc->ignore_memory_transaction_failures = true; > } > > DEFINE_MACHINE("collie", collie_machine_init) > diff --git a/hw/arm/cubieboard.c b/hw/arm/cubieboard.c > index b98e1c4..32f1edd 100644 > --- a/hw/arm/cubieboard.c > +++ b/hw/arm/cubieboard.c > @@ -86,6 +86,7 @@ static void cubieboard_machine_init(MachineClass *mc) > mc->init = cubieboard_init; > mc->block_default_type = IF_IDE; > mc->units_per_default_bus = 1; > + mc->ignore_memory_transaction_failures = true; > } > > DEFINE_MACHINE("cubieboard", cubieboard_machine_init) > diff --git a/hw/arm/digic_boards.c b/hw/arm/digic_boards.c > index 520c8e9..9f11dcd 100644 > --- a/hw/arm/digic_boards.c > +++ b/hw/arm/digic_boards.c > @@ -155,6 +155,7 @@ static void canon_a1100_machine_init(MachineClass *mc) > { > mc->desc = "Canon PowerShot A1100 IS"; > mc->init = &canon_a1100_init; > + mc->ignore_memory_transaction_failures = true; > } > > DEFINE_MACHINE("canon-a1100", canon_a1100_machine_init) > diff --git a/hw/arm/exynos4_boards.c b/hw/arm/exynos4_boards.c > index 7c03ed3..f1441ec 100644 > --- a/hw/arm/exynos4_boards.c > +++ b/hw/arm/exynos4_boards.c > @@ -189,6 +189,7 @@ static void nuri_class_init(ObjectClass *oc, void *data) > mc->desc = "Samsung NURI board (Exynos4210)"; > mc->init = nuri_init; > mc->max_cpus = EXYNOS4210_NCPUS; > + mc->ignore_memory_transaction_failures = true; > } > > static const TypeInfo nuri_type = { > @@ -204,6 +205,7 @@ static void smdkc210_class_init(ObjectClass *oc, void *data) > mc->desc = "Samsung SMDKC210 board (Exynos4210)"; > mc->init = smdkc210_init; > mc->max_cpus = EXYNOS4210_NCPUS; > + mc->ignore_memory_transaction_failures = true; > } > > static const TypeInfo smdkc210_type = { > diff --git a/hw/arm/gumstix.c b/hw/arm/gumstix.c > index d59d9ba..092ce36 100644 > --- a/hw/arm/gumstix.c > +++ b/hw/arm/gumstix.c > @@ -128,6 +128,7 @@ static void connex_class_init(ObjectClass *oc, void *data) > > mc->desc = "Gumstix Connex (PXA255)"; > mc->init = connex_init; > + mc->ignore_memory_transaction_failures = true; > } > > static const TypeInfo connex_type = { > @@ -142,6 +143,7 @@ static void verdex_class_init(ObjectClass *oc, void *data) > > mc->desc = "Gumstix Verdex (PXA270)"; > mc->init = verdex_init; > + mc->ignore_memory_transaction_failures = true; > } > > static const TypeInfo verdex_type = { > diff --git a/hw/arm/highbank.c b/hw/arm/highbank.c > index 20e60f1..0d222fe 100644 > --- a/hw/arm/highbank.c > +++ b/hw/arm/highbank.c > @@ -410,6 +410,7 @@ static void highbank_class_init(ObjectClass *oc, void *data) > mc->block_default_type = IF_IDE; > mc->units_per_default_bus = 1; > mc->max_cpus = 4; > + mc->ignore_memory_transaction_failures = true; > } > > static const TypeInfo highbank_type = { > @@ -427,6 +428,7 @@ static void midway_class_init(ObjectClass *oc, void *data) > mc->block_default_type = IF_IDE; > mc->units_per_default_bus = 1; > mc->max_cpus = 4; > + mc->ignore_memory_transaction_failures = true; > } > > static const TypeInfo midway_type = { > diff --git a/hw/arm/imx25_pdk.c b/hw/arm/imx25_pdk.c > index 7d42c74..9f3ee14 100644 > --- a/hw/arm/imx25_pdk.c > +++ b/hw/arm/imx25_pdk.c > @@ -148,6 +148,7 @@ static void imx25_pdk_machine_init(MachineClass *mc) > { > mc->desc = "ARM i.MX25 PDK board (ARM926)"; > mc->init = imx25_pdk_init; > + mc->ignore_memory_transaction_failures = true; > } > > DEFINE_MACHINE("imx25-pdk", imx25_pdk_machine_init) > diff --git a/hw/arm/integratorcp.c b/hw/arm/integratorcp.c > index d9530ed..d603af9 100644 > --- a/hw/arm/integratorcp.c > +++ b/hw/arm/integratorcp.c > @@ -681,6 +681,7 @@ static void integratorcp_machine_init(MachineClass *mc) > { > mc->desc = "ARM Integrator/CP (ARM926EJ-S)"; > mc->init = integratorcp_init; > + mc->ignore_memory_transaction_failures = true; > } > > DEFINE_MACHINE("integratorcp", integratorcp_machine_init) > diff --git a/hw/arm/kzm.c b/hw/arm/kzm.c > index 3ed6577..f9c2228 100644 > --- a/hw/arm/kzm.c > +++ b/hw/arm/kzm.c > @@ -142,6 +142,7 @@ static void kzm_machine_init(MachineClass *mc) > { > mc->desc = "ARM KZM Emulation Baseboard (ARM1136)"; > mc->init = kzm_init; > + mc->ignore_memory_transaction_failures = true; > } > > DEFINE_MACHINE("kzm", kzm_machine_init) > diff --git a/hw/arm/mainstone.c b/hw/arm/mainstone.c > index fb268e6..637f52c 100644 > --- a/hw/arm/mainstone.c > +++ b/hw/arm/mainstone.c > @@ -196,6 +196,7 @@ static void mainstone2_machine_init(MachineClass *mc) > { > mc->desc = "Mainstone II (PXA27x)"; > mc->init = mainstone_init; > + mc->ignore_memory_transaction_failures = true; > } > > DEFINE_MACHINE("mainstone", mainstone2_machine_init) > diff --git a/hw/arm/musicpal.c b/hw/arm/musicpal.c > index 7e8ab31..fcf6224 100644 > --- a/hw/arm/musicpal.c > +++ b/hw/arm/musicpal.c > @@ -1718,6 +1718,7 @@ static void musicpal_machine_init(MachineClass *mc) > { > mc->desc = "Marvell 88w8618 / MusicPal (ARM926EJ-S)"; > mc->init = musicpal_init; > + mc->ignore_memory_transaction_failures = true; > } > > DEFINE_MACHINE("musicpal", musicpal_machine_init) > diff --git a/hw/arm/netduino2.c b/hw/arm/netduino2.c > index 3cfe332..9d34d4c 100644 > --- a/hw/arm/netduino2.c > +++ b/hw/arm/netduino2.c > @@ -45,6 +45,7 @@ static void netduino2_machine_init(MachineClass *mc) > { > mc->desc = "Netduino 2 Machine"; > mc->init = netduino2_init; > + mc->ignore_memory_transaction_failures = true; > } > > DEFINE_MACHINE("netduino2", netduino2_machine_init) > diff --git a/hw/arm/nseries.c b/hw/arm/nseries.c > index 503a3b6..a32ac82 100644 > --- a/hw/arm/nseries.c > +++ b/hw/arm/nseries.c > @@ -1425,6 +1425,7 @@ static void n800_class_init(ObjectClass *oc, void *data) > mc->desc = "Nokia N800 tablet aka. RX-34 (OMAP2420)"; > mc->init = n800_init; > mc->default_boot_order = ""; > + mc->ignore_memory_transaction_failures = true; > } > > static const TypeInfo n800_type = { > @@ -1440,6 +1441,7 @@ static void n810_class_init(ObjectClass *oc, void *data) > mc->desc = "Nokia N810 tablet aka. RX-44 (OMAP2420)"; > mc->init = n810_init; > mc->default_boot_order = ""; > + mc->ignore_memory_transaction_failures = true; > } > > static const TypeInfo n810_type = { > diff --git a/hw/arm/omap_sx1.c b/hw/arm/omap_sx1.c > index 9809106..4535617 100644 > --- a/hw/arm/omap_sx1.c > +++ b/hw/arm/omap_sx1.c > @@ -223,6 +223,7 @@ static void sx1_machine_v2_class_init(ObjectClass *oc, void *data) > > mc->desc = "Siemens SX1 (OMAP310) V2"; > mc->init = sx1_init_v2; > + mc->ignore_memory_transaction_failures = true; > } > > static const TypeInfo sx1_machine_v2_type = { > @@ -237,6 +238,7 @@ static void sx1_machine_v1_class_init(ObjectClass *oc, void *data) > > mc->desc = "Siemens SX1 (OMAP310) V1"; > mc->init = sx1_init_v1; > + mc->ignore_memory_transaction_failures = true; > } > > static const TypeInfo sx1_machine_v1_type = { > diff --git a/hw/arm/palm.c b/hw/arm/palm.c > index 64cf8ca..bf070a2 100644 > --- a/hw/arm/palm.c > +++ b/hw/arm/palm.c > @@ -274,6 +274,7 @@ static void palmte_machine_init(MachineClass *mc) > { > mc->desc = "Palm Tungsten|E aka. Cheetah PDA (OMAP310)"; > mc->init = palmte_init; > + mc->ignore_memory_transaction_failures = true; > } > > DEFINE_MACHINE("cheetah", palmte_machine_init) > diff --git a/hw/arm/raspi.c b/hw/arm/raspi.c > index 32cdc98..5941c9f 100644 > --- a/hw/arm/raspi.c > +++ b/hw/arm/raspi.c > @@ -168,5 +168,6 @@ static void raspi2_machine_init(MachineClass *mc) > mc->no_cdrom = 1; > mc->max_cpus = BCM2836_NCPUS; > mc->default_ram_size = 1024 * 1024 * 1024; > + mc->ignore_memory_transaction_failures = true; > }; > DEFINE_MACHINE("raspi2", raspi2_machine_init) > diff --git a/hw/arm/realview.c b/hw/arm/realview.c > index 76ff557..f1b261f 100644 > --- a/hw/arm/realview.c > +++ b/hw/arm/realview.c > @@ -396,6 +396,7 @@ static void realview_eb_class_init(ObjectClass *oc, void *data) > mc->desc = "ARM RealView Emulation Baseboard (ARM926EJ-S)"; > mc->init = realview_eb_init; > mc->block_default_type = IF_SCSI; > + mc->ignore_memory_transaction_failures = true; > } > > static const TypeInfo realview_eb_type = { > @@ -412,6 +413,7 @@ static void realview_eb_mpcore_class_init(ObjectClass *oc, void *data) > mc->init = realview_eb_mpcore_init; > mc->block_default_type = IF_SCSI; > mc->max_cpus = 4; > + mc->ignore_memory_transaction_failures = true; > } > > static const TypeInfo realview_eb_mpcore_type = { > @@ -426,6 +428,7 @@ static void realview_pb_a8_class_init(ObjectClass *oc, void *data) > > mc->desc = "ARM RealView Platform Baseboard for Cortex-A8"; > mc->init = realview_pb_a8_init; > + mc->ignore_memory_transaction_failures = true; > } > > static const TypeInfo realview_pb_a8_type = { > @@ -441,6 +444,7 @@ static void realview_pbx_a9_class_init(ObjectClass *oc, void *data) > mc->desc = "ARM RealView Platform Baseboard Explore for Cortex-A9"; > mc->init = realview_pbx_a9_init; > mc->max_cpus = 4; > + mc->ignore_memory_transaction_failures = true; > } > > static const TypeInfo realview_pbx_a9_type = { > diff --git a/hw/arm/sabrelite.c b/hw/arm/sabrelite.c > index 4e7ac8c..ee140e5 100644 > --- a/hw/arm/sabrelite.c > +++ b/hw/arm/sabrelite.c > @@ -122,6 +122,7 @@ static void sabrelite_machine_init(MachineClass *mc) > mc->desc = "Freescale i.MX6 Quad SABRE Lite Board (Cortex A9)"; > mc->init = sabrelite_init; > mc->max_cpus = FSL_IMX6_NUM_CPUS; > + mc->ignore_memory_transaction_failures = true; > } > > DEFINE_MACHINE("sabrelite", sabrelite_machine_init) > diff --git a/hw/arm/spitz.c b/hw/arm/spitz.c > index 7f588ce..6406421 100644 > --- a/hw/arm/spitz.c > +++ b/hw/arm/spitz.c > @@ -983,6 +983,7 @@ static void akitapda_class_init(ObjectClass *oc, void *data) > > mc->desc = "Sharp SL-C1000 (Akita) PDA (PXA270)"; > mc->init = akita_init; > + mc->ignore_memory_transaction_failures = true; > } > > static const TypeInfo akitapda_type = { > @@ -998,6 +999,7 @@ static void spitzpda_class_init(ObjectClass *oc, void *data) > mc->desc = "Sharp SL-C3000 (Spitz) PDA (PXA270)"; > mc->init = spitz_init; > mc->block_default_type = IF_IDE; > + mc->ignore_memory_transaction_failures = true; > } > > static const TypeInfo spitzpda_type = { > @@ -1013,6 +1015,7 @@ static void borzoipda_class_init(ObjectClass *oc, void *data) > mc->desc = "Sharp SL-C3100 (Borzoi) PDA (PXA270)"; > mc->init = borzoi_init; > mc->block_default_type = IF_IDE; > + mc->ignore_memory_transaction_failures = true; > } > > static const TypeInfo borzoipda_type = { > @@ -1028,6 +1031,7 @@ static void terrierpda_class_init(ObjectClass *oc, void *data) > mc->desc = "Sharp SL-C3200 (Terrier) PDA (PXA270)"; > mc->init = terrier_init; > mc->block_default_type = IF_IDE; > + mc->ignore_memory_transaction_failures = true; > } > > static const TypeInfo terrierpda_type = { > diff --git a/hw/arm/stellaris.c b/hw/arm/stellaris.c > index 408c1a1..b3aad23 100644 > --- a/hw/arm/stellaris.c > +++ b/hw/arm/stellaris.c > @@ -1453,6 +1453,7 @@ static void lm3s811evb_class_init(ObjectClass *oc, void *data) > > mc->desc = "Stellaris LM3S811EVB"; > mc->init = lm3s811evb_init; > + mc->ignore_memory_transaction_failures = true; > } > > static const TypeInfo lm3s811evb_type = { > @@ -1467,6 +1468,7 @@ static void lm3s6965evb_class_init(ObjectClass *oc, void *data) > > mc->desc = "Stellaris LM3S6965EVB"; > mc->init = lm3s6965evb_init; > + mc->ignore_memory_transaction_failures = true; > } > > static const TypeInfo lm3s6965evb_type = { > diff --git a/hw/arm/tosa.c b/hw/arm/tosa.c > index 8b757ff..1134cf7 100644 > --- a/hw/arm/tosa.c > +++ b/hw/arm/tosa.c > @@ -263,6 +263,7 @@ static void tosapda_machine_init(MachineClass *mc) > mc->desc = "Sharp SL-6000 (Tosa) PDA (PXA255)"; > mc->init = tosa_init; > mc->block_default_type = IF_IDE; > + mc->ignore_memory_transaction_failures = true; > } > > DEFINE_MACHINE("tosa", tosapda_machine_init) > diff --git a/hw/arm/versatilepb.c b/hw/arm/versatilepb.c > index b0e9f5b..76664e4 100644 > --- a/hw/arm/versatilepb.c > +++ b/hw/arm/versatilepb.c > @@ -403,6 +403,7 @@ static void versatilepb_class_init(ObjectClass *oc, void *data) > mc->desc = "ARM Versatile/PB (ARM926EJ-S)"; > mc->init = vpb_init; > mc->block_default_type = IF_SCSI; > + mc->ignore_memory_transaction_failures = true; > } > > static const TypeInfo versatilepb_type = { > @@ -418,6 +419,7 @@ static void versatileab_class_init(ObjectClass *oc, void *data) > mc->desc = "ARM Versatile/AB (ARM926EJ-S)"; > mc->init = vab_init; > mc->block_default_type = IF_SCSI; > + mc->ignore_memory_transaction_failures = true; > } > > static const TypeInfo versatileab_type = { > diff --git a/hw/arm/vexpress.c b/hw/arm/vexpress.c > index 528c65d..9be1833 100644 > --- a/hw/arm/vexpress.c > +++ b/hw/arm/vexpress.c > @@ -750,6 +750,7 @@ static void vexpress_class_init(ObjectClass *oc, void *data) > mc->desc = "ARM Versatile Express"; > mc->init = vexpress_common_init; > mc->max_cpus = 4; > + mc->ignore_memory_transaction_failures = true; > } > > static void vexpress_a9_class_init(ObjectClass *oc, void *data) > diff --git a/hw/arm/xilinx_zynq.c b/hw/arm/xilinx_zynq.c > index 6b11a75..9883215 100644 > --- a/hw/arm/xilinx_zynq.c > +++ b/hw/arm/xilinx_zynq.c > @@ -324,6 +324,7 @@ static void zynq_machine_init(MachineClass *mc) > mc->init = zynq_init; > mc->max_cpus = 1; > mc->no_sdcard = 1; > + mc->ignore_memory_transaction_failures = true; > } > > DEFINE_MACHINE("xilinx-zynq-a9", zynq_machine_init) > diff --git a/hw/arm/xlnx-ep108.c b/hw/arm/xlnx-ep108.c > index 860780a..c339cd4 100644 > --- a/hw/arm/xlnx-ep108.c > +++ b/hw/arm/xlnx-ep108.c > @@ -122,6 +122,7 @@ static void xlnx_ep108_machine_init(MachineClass *mc) > mc->init = xlnx_ep108_init; > mc->block_default_type = IF_IDE; > mc->units_per_default_bus = 1; > + mc->ignore_memory_transaction_failures = true; > } > > DEFINE_MACHINE("xlnx-ep108", xlnx_ep108_machine_init) > @@ -132,6 +133,7 @@ static void xlnx_zcu102_machine_init(MachineClass *mc) > mc->init = xlnx_ep108_init; > mc->block_default_type = IF_IDE; > mc->units_per_default_bus = 1; > + mc->ignore_memory_transaction_failures = true; > } > > DEFINE_MACHINE("xlnx-zcu102", xlnx_zcu102_machine_init) > diff --git a/hw/arm/z2.c b/hw/arm/z2.c > index 1607cbd..417bc1a 100644 > --- a/hw/arm/z2.c > +++ b/hw/arm/z2.c > @@ -370,6 +370,7 @@ static void z2_machine_init(MachineClass *mc) > { > mc->desc = "Zipit Z2 (PXA27x)"; > mc->init = z2_init; > + mc->ignore_memory_transaction_failures = true; > } > > DEFINE_MACHINE("z2", z2_machine_init) > -- > 2.7.4 > > From MAILER-DAEMON Fri Aug 04 21:40:55 2017 Received: from list by lists.gnu.org with archive (Exim 4.71) id 1ddo5H-0004T9-AP for mharc-qemu-arm@gnu.org; Fri, 04 Aug 2017 21:40:55 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:59183) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ddo5E-0004Ss-Ij for qemu-arm@nongnu.org; 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[81.231.233.234]) by smtp.gmail.com with ESMTPSA id n80sm813580lfb.14.2017.08.04.18.40.45 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 04 Aug 2017 18:40:45 -0700 (PDT) Date: Sat, 5 Aug 2017 03:40:45 +0200 From: "Edgar E. Iglesias" To: Peter Maydell Cc: qemu-arm@nongnu.org, qemu-devel@nongnu.org, Richard Henderson , patches@linaro.org Message-ID: <20170805014045.GE4859@toto> References: <1501867249-1924-1-git-send-email-peter.maydell@linaro.org> <1501867249-1924-7-git-send-email-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1501867249-1924-7-git-send-email-peter.maydell@linaro.org> User-Agent: Mutt/1.5.24 (2015-08-30) X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4010:c07::242 Subject: Re: [Qemu-arm] [PATCH 6/8] target/arm: Factor out fault delivery code X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sat, 05 Aug 2017 01:40:54 -0000 On Fri, Aug 04, 2017 at 06:20:47PM +0100, Peter Maydell wrote: > We currently have some similar code in tlb_fill() and in > arm_cpu_do_unaligned_access() for delivering a data abort or prefetch > abort. We're also going to want to do the same thing to handle > external aborts. Factor out the common code into a new function > deliver_fault(). I found this a bit hard to read but I think it looks OK :-) Acked-by: Edgar E. Iglesias > > Signed-off-by: Peter Maydell > --- > target/arm/op_helper.c | 110 +++++++++++++++++++++++++------------------------ > 1 file changed, 57 insertions(+), 53 deletions(-) > > diff --git a/target/arm/op_helper.c b/target/arm/op_helper.c > index 2a85666..aa52a98 100644 > --- a/target/arm/op_helper.c > +++ b/target/arm/op_helper.c > @@ -115,6 +115,51 @@ static inline uint32_t merge_syn_data_abort(uint32_t template_syn, > return syn; > } > > +static void deliver_fault(ARMCPU *cpu, vaddr addr, MMUAccessType access_type, > + uint32_t fsr, uint32_t fsc, ARMMMUFaultInfo *fi) > +{ > + CPUARMState *env = &cpu->env; > + int target_el; > + bool same_el; > + uint32_t syn, exc; > + > + target_el = exception_target_el(env); > + if (fi->stage2) { > + target_el = 2; > + env->cp15.hpfar_el2 = extract64(fi->s2addr, 12, 47) << 4; > + } > + same_el = (arm_current_el(env) == target_el); > + > + if (fsc == 0x3f) { > + /* Caller doesn't have a long-format fault status code. This > + * should only happen if this fault will never actually be reported > + * to an EL that uses a syndrome register. Check that here. > + * 0x3f is a (currently) reserved FSR code, in case the constructed > + * syndrome does leak into the guest somehow. > + */ > + assert(target_el != 2 && !arm_el_is_aa64(env, target_el)); > + } > + > + if (access_type == MMU_INST_FETCH) { > + syn = syn_insn_abort(same_el, 0, fi->s1ptw, fsc); > + exc = EXCP_PREFETCH_ABORT; > + } else { > + syn = merge_syn_data_abort(env->exception.syndrome, target_el, > + same_el, fi->s1ptw, > + access_type == MMU_DATA_STORE, > + fsc); > + if (access_type == MMU_DATA_STORE > + && arm_feature(env, ARM_FEATURE_V6)) { > + fsr |= (1 << 11); > + } > + exc = EXCP_DATA_ABORT; > + } > + > + env->exception.vaddress = addr; > + env->exception.fsr = fsr; > + raise_exception(env, exc, syn, target_el); > +} > + > /* try to fill the TLB and return an exception if error. If retaddr is > * NULL, it means that the function was called in C code (i.e. not > * from generated code or from helper.c) > @@ -129,23 +174,13 @@ void tlb_fill(CPUState *cs, target_ulong addr, MMUAccessType access_type, > ret = arm_tlb_fill(cs, addr, access_type, mmu_idx, &fsr, &fi); > if (unlikely(ret)) { > ARMCPU *cpu = ARM_CPU(cs); > - CPUARMState *env = &cpu->env; > - uint32_t syn, exc, fsc; > - unsigned int target_el; > - bool same_el; > + uint32_t fsc; > > if (retaddr) { > /* now we have a real cpu fault */ > cpu_restore_state(cs, retaddr); > } > > - target_el = exception_target_el(env); > - if (fi.stage2) { > - target_el = 2; > - env->cp15.hpfar_el2 = extract64(fi.s2addr, 12, 47) << 4; > - } > - same_el = arm_current_el(env) == target_el; > - > if (fsr & (1 << 9)) { > /* LPAE format fault status register : bottom 6 bits are > * status code in the same form as needed for syndrome > @@ -153,34 +188,15 @@ void tlb_fill(CPUState *cs, target_ulong addr, MMUAccessType access_type, > fsc = extract32(fsr, 0, 6); > } else { > /* Short format FSR : this fault will never actually be reported > - * to an EL that uses a syndrome register. Check that here, > - * and use a (currently) reserved FSR code in case the constructed > - * syndrome does leak into the guest somehow. > + * to an EL that uses a syndrome register. Use a (currently) > + * reserved FSR code in case the constructed syndrome does leak > + * into the guest somehow. deliver_fault will assert that > + * we don't target an EL using the syndrome. > */ > - assert(target_el != 2 && !arm_el_is_aa64(env, target_el)); > fsc = 0x3f; > } > > - /* For insn and data aborts we assume there is no instruction syndrome > - * information; this is always true for exceptions reported to EL1. > - */ > - if (access_type == MMU_INST_FETCH) { > - syn = syn_insn_abort(same_el, 0, fi.s1ptw, fsc); > - exc = EXCP_PREFETCH_ABORT; > - } else { > - syn = merge_syn_data_abort(env->exception.syndrome, target_el, > - same_el, fi.s1ptw, > - access_type == MMU_DATA_STORE, fsc); > - if (access_type == MMU_DATA_STORE > - && arm_feature(env, ARM_FEATURE_V6)) { > - fsr |= (1 << 11); > - } > - exc = EXCP_DATA_ABORT; > - } > - > - env->exception.vaddress = addr; > - env->exception.fsr = fsr; > - raise_exception(env, exc, syn, target_el); > + deliver_fault(cpu, addr, access_type, fsr, fsc, &fi); > } > } > > @@ -191,9 +207,8 @@ void arm_cpu_do_unaligned_access(CPUState *cs, vaddr vaddr, > { > ARMCPU *cpu = ARM_CPU(cs); > CPUARMState *env = &cpu->env; > - int target_el; > - bool same_el; > - uint32_t syn; > + uint32_t fsr, fsc; > + ARMMMUFaultInfo fi = {}; > ARMMMUIdx arm_mmu_idx = core_to_arm_mmu_idx(env, mmu_idx); > > if (retaddr) { > @@ -201,28 +216,17 @@ void arm_cpu_do_unaligned_access(CPUState *cs, vaddr vaddr, > cpu_restore_state(cs, retaddr); > } > > - target_el = exception_target_el(env); > - same_el = (arm_current_el(env) == target_el); > - > - env->exception.vaddress = vaddr; > - > /* the DFSR for an alignment fault depends on whether we're using > * the LPAE long descriptor format, or the short descriptor format > */ > if (arm_s1_regime_using_lpae_format(env, arm_mmu_idx)) { > - env->exception.fsr = (1 << 9) | 0x21; > + fsr = (1 << 9) | 0x21; > } else { > - env->exception.fsr = 0x1; > - } > - > - if (access_type == MMU_DATA_STORE && arm_feature(env, ARM_FEATURE_V6)) { > - env->exception.fsr |= (1 << 11); > + fsr = 0x1; > } > + fsc = 0x21; > > - syn = merge_syn_data_abort(env->exception.syndrome, target_el, > - same_el, 0, access_type == MMU_DATA_STORE, > - 0x21); > - raise_exception(env, EXCP_DATA_ABORT, syn, target_el); > + deliver_fault(cpu, vaddr, access_type, fsr, fsc, &fi); > } > > #endif /* !defined(CONFIG_USER_ONLY) */ > -- > 2.7.4 > > From MAILER-DAEMON Fri Aug 04 21:45:05 2017 Received: from list by lists.gnu.org with archive (Exim 4.71) id 1ddo9J-0005cS-CF for mharc-qemu-arm@gnu.org; Fri, 04 Aug 2017 21:45:05 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:60364) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ddo9H-0005b3-GE for qemu-arm@nongnu.org; Fri, 04 Aug 2017 21:45:04 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ddo9C-0006rZ-S1 for qemu-arm@nongnu.org; Fri, 04 Aug 2017 21:45:03 -0400 Received: from mail-lf0-x242.google.com ([2a00:1450:4010:c07::242]:38436) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ddo9C-0006r4-Gk; Fri, 04 Aug 2017 21:44:58 -0400 Received: by mail-lf0-x242.google.com with SMTP id y15so2030569lfd.5; Fri, 04 Aug 2017 18:44:58 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=date:from:to:cc:subject:message-id:references:mime-version :content-disposition:in-reply-to:user-agent; bh=5X6y92SuGvQKAv9UzbJBk6xCv/wcmROYhpdhQqDcO1Q=; b=iKnGDb4rQz9FejaEDb1HngPONnft4NDFE4qMgcqqbfL4iVnMZ/8SwSUh1T0Ae2G0SH uH1vvd+qBDMzXgfCT1eFxsGCrOmNGSKPDpDfJ0IiLRnt/pKwnMdBBZ25sM/S356b0mYT A02IboPRE32BfFDliN7lgsLeb9KdddkQhzdPWBWPadZAJVV6b7HUbXDwiLkJusWc2Oi8 DzDhgFZOialULWllTZxpdiddVSzpEXgnvAE0FHANMFqXvWS1mqAX/kPsqRcFyZbFA2jX d5ld3c04SD76ZurjN0d4Umw+rioqC2kDf2jpT1pXbI2hxcRmVwRFeyZ6Y3pw0TD9O+CR wHIQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:in-reply-to:user-agent; bh=5X6y92SuGvQKAv9UzbJBk6xCv/wcmROYhpdhQqDcO1Q=; b=qt62k6hC/taP1YT3thT4e9usmJV59pcXz0ECh2Zj5T9nbc8O0Z3Svmu8nm/b9weXGE oCsj2IYVFATM8gmw/Z/rt1xWayTZ5rjm3G/r2dgwA82k8pCwUeMk3XZYTjfPG4d/rays kcOnMpxvzZ/eIq48VAS4lahrh5VRUb5PeEIUSupNRJv7xjlvPiBWUAJn/4WgtGgl0tdC NCSwLXhWcm3xaQsoHaAchISV7s5PcEifdvnUxGz3t+BSSLE44r188/Nax3jLsbxmQ+T0 V4RBvwgcV914SZPVKYQG9IQduBypkRzhuZ8CYCJnmS0lixryUc0knB/Ipa+FL5So9upH isXg== X-Gm-Message-State: AHYfb5jv0+6gvPcC3dIdJPjEjjr31SeBSlc9kpyhgfw52rJjOaIgpY2I cK5RmpW6czETyQ== X-Received: by 10.46.20.22 with SMTP id u22mr1300188ljd.58.1501897497114; Fri, 04 Aug 2017 18:44:57 -0700 (PDT) Received: from gmail.com (81-231-233-234-no56.tbcn.telia.com. [81.231.233.234]) by smtp.gmail.com with ESMTPSA id 2sm972042lji.5.2017.08.04.18.44.56 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 04 Aug 2017 18:44:56 -0700 (PDT) Date: Sat, 5 Aug 2017 03:44:55 +0200 From: "Edgar E. Iglesias" To: Peter Maydell Cc: qemu-arm@nongnu.org, qemu-devel@nongnu.org, Richard Henderson , patches@linaro.org Message-ID: <20170805014455.GF4859@toto> References: <1501867249-1924-1-git-send-email-peter.maydell@linaro.org> <1501867249-1924-9-git-send-email-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1501867249-1924-9-git-send-email-peter.maydell@linaro.org> User-Agent: Mutt/1.5.24 (2015-08-30) X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4010:c07::242 Subject: Re: [Qemu-arm] [PATCH 8/8] target/arm: Implement new do_transaction_failed hook X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sat, 05 Aug 2017 01:45:04 -0000 On Fri, Aug 04, 2017 at 06:20:49PM +0100, Peter Maydell wrote: > Implement the new do_transaction_failed hook for ARM, which should > cause the CPU to take a prefetch abort or data abort. > > Signed-off-by: Peter Maydell Reviewed-by: Edgar E. Iglesias > --- > target/arm/internals.h | 10 ++++++++++ > target/arm/cpu.c | 1 + > target/arm/op_helper.c | 43 +++++++++++++++++++++++++++++++++++++++++++ > 3 files changed, 54 insertions(+) > > diff --git a/target/arm/internals.h b/target/arm/internals.h > index a3adbd8..13bb001 100644 > --- a/target/arm/internals.h > +++ b/target/arm/internals.h > @@ -471,6 +471,16 @@ void arm_cpu_do_unaligned_access(CPUState *cs, vaddr vaddr, > MMUAccessType access_type, > int mmu_idx, uintptr_t retaddr); > > +/* arm_cpu_do_transaction_failed: handle a memory system error response > + * (eg "no device/memory present at address") by raising an external abort > + * exception > + */ > +void arm_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, > + vaddr addr, unsigned size, > + MMUAccessType access_type, > + int mmu_idx, MemTxAttrs attrs, > + MemTxResult response, uintptr_t retaddr); > + > /* Call the EL change hook if one has been registered */ > static inline void arm_call_el_change_hook(ARMCPU *cpu) > { > diff --git a/target/arm/cpu.c b/target/arm/cpu.c > index 05c038b..6baede0 100644 > --- a/target/arm/cpu.c > +++ b/target/arm/cpu.c > @@ -1670,6 +1670,7 @@ static void arm_cpu_class_init(ObjectClass *oc, void *data) > #else > cc->do_interrupt = arm_cpu_do_interrupt; > cc->do_unaligned_access = arm_cpu_do_unaligned_access; > + cc->do_transaction_failed = arm_cpu_do_transaction_failed; > cc->get_phys_page_attrs_debug = arm_cpu_get_phys_page_attrs_debug; > cc->asidx_from_attrs = arm_asidx_from_attrs; > cc->vmsd = &vmstate_arm_cpu; > diff --git a/target/arm/op_helper.c b/target/arm/op_helper.c > index 7eac272..54b6dd8 100644 > --- a/target/arm/op_helper.c > +++ b/target/arm/op_helper.c > @@ -229,6 +229,49 @@ void arm_cpu_do_unaligned_access(CPUState *cs, vaddr vaddr, > deliver_fault(cpu, vaddr, access_type, fsr, fsc, &fi); > } > > +/* arm_cpu_do_transaction_failed: handle a memory system error response > + * (eg "no device/memory present at address") by raising an external abort > + * exception > + */ > +void arm_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, > + vaddr addr, unsigned size, > + MMUAccessType access_type, > + int mmu_idx, MemTxAttrs attrs, > + MemTxResult response, uintptr_t retaddr) > +{ > + ARMCPU *cpu = ARM_CPU(cs); > + CPUARMState *env = &cpu->env; > + uint32_t fsr, fsc; > + ARMMMUFaultInfo fi = {}; > + ARMMMUIdx arm_mmu_idx = core_to_arm_mmu_idx(env, mmu_idx); > + > + if (retaddr) { > + /* now we have a real cpu fault */ > + cpu_restore_state(cs, retaddr); > + } > + > + /* The EA bit in syndromes and fault status registers is an > + * IMPDEF classification of external aborts. ARM implementations > + * usually use this to indicate AXI bus Decode error (0) or > + * Slave error (1); in QEMU we follow that. > + */ > + fi.ea = (response != MEMTX_DECODE_ERROR); > + > + /* The fault status register format depends on whether we're using > + * the LPAE long descriptor format, or the short descriptor format. > + */ > + if (arm_s1_regime_using_lpae_format(env, arm_mmu_idx)) { > + /* long descriptor form, STATUS 0b010000: synchronous ext abort */ > + fsr = (fi.ea << 12) | (1 << 9) | 0x10; > + } else { > + /* short descriptor form, FSR 0b01000 : synchronous ext abort */ > + fsr = (fi.ea << 12) | 0x8; > + } > + fsc = 0x10; > + > + deliver_fault(cpu, addr, access_type, fsr, fsc, &fi); > +} > + > #endif /* !defined(CONFIG_USER_ONLY) */ > > uint32_t HELPER(add_setq)(CPUARMState *env, uint32_t a, uint32_t b) > -- > 2.7.4 > > From MAILER-DAEMON Fri Aug 04 21:45:18 2017 Received: from list by lists.gnu.org with archive (Exim 4.71) id 1ddo9V-0006I1-Vn for mharc-qemu-arm@gnu.org; Fri, 04 Aug 2017 21:45:18 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:60437) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ddo9T-00069F-Dw for qemu-arm@nongnu.org; Fri, 04 Aug 2017 21:45:16 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ddo9O-00075g-Jh for qemu-arm@nongnu.org; Fri, 04 Aug 2017 21:45:15 -0400 Received: from mail-lf0-x243.google.com ([2a00:1450:4010:c07::243]:32946) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ddo9O-00073n-CK; Fri, 04 Aug 2017 21:45:10 -0400 Received: by mail-lf0-x243.google.com with SMTP id 65so2050366lfa.0; Fri, 04 Aug 2017 18:45:10 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=date:from:to:cc:subject:message-id:references:mime-version :content-disposition:in-reply-to:user-agent; bh=kCBZXtKMH/pRVNQuA5KOru3ZCwws27J5QZ6rSHn29LM=; b=iNaUZznb7MXSu9/+On6vvH3ehXAR/CxH3SXczjnFCbSRb5TzTHEDjd38O5MD8c4Xnv FezQxin4/5lGh5jIQmlSsH20qQ4v8xNVOguuFy/ZrWQRO19xQsian205kfzv3Wzf7aUB 28VJieXLQwaNzDAXfQVoh1TX27Jd2uPvEn/G2y7anLUXYlsBa0zGZZU/Qfl/MSvFl4SL 1zffQ2Yb7KDH+8f9IV56GJkESqGtQd0InfFQF3VKiS+A7KJ7XOOUaWrZCFHtwMnpn9rX vwWpO/g/ZoRfplw9ereP0k4EzpSqHWrThBBG5hvZSZM2ydPByAUUZHGL6d9DNbSlP/0A ZW4Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:in-reply-to:user-agent; bh=kCBZXtKMH/pRVNQuA5KOru3ZCwws27J5QZ6rSHn29LM=; b=M1lCl0ziAM5Yz+XkP4+OJrJJVzuT4be7VoF091keIbmP5ju1vBTVNh9ZRJDZFxFJT0 H2JzrwmMLbuDvi2SBWtigr+6DAD8NRjy9Hq1vyvpalWAwteMkcMm7nsXFURpiCMIhIrO Vxi4F9lSXwb+IBPXqfr5E3o9yFOcrBRebwoFWg/0c08z4czIUA6cQLUyuEJ3fKdTdWq8 iZADeFyP2BfXKc1XnPy5vVrsvIul7mna1Hi3ewCEXQ85Y1e7V5ww9nWzeGGidi1KGrAq pc8sc6cqwp8MLLqjsSNC3oHNp6I7YL51sLK4ycqGuYfVHgNkT8fnAehuInxm5QAIOWHE V40w== X-Gm-Message-State: AHYfb5gam9/i8DUst4KRWO9zNzTssWJhpmDgwnWdLNkzBvwiHnVM+54R ZAeSGoemQVlc5RQR X-Received: by 10.25.56.3 with SMTP id f3mr1156575lfa.253.1501897508966; Fri, 04 Aug 2017 18:45:08 -0700 (PDT) Received: from gmail.com (81-231-233-234-no56.tbcn.telia.com. [81.231.233.234]) by smtp.gmail.com with ESMTPSA id 14sm1374074ljv.62.2017.08.04.18.45.08 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 04 Aug 2017 18:45:08 -0700 (PDT) Date: Sat, 5 Aug 2017 03:45:07 +0200 From: "Edgar E. Iglesias" To: Peter Maydell Cc: qemu-arm@nongnu.org, qemu-devel@nongnu.org, Richard Henderson , patches@linaro.org Message-ID: <20170805014507.GG4859@toto> References: <1501867249-1924-1-git-send-email-peter.maydell@linaro.org> <1501867249-1924-8-git-send-email-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1501867249-1924-8-git-send-email-peter.maydell@linaro.org> User-Agent: Mutt/1.5.24 (2015-08-30) X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4010:c07::243 Subject: Re: [Qemu-arm] [PATCH 7/8] target/arm: Allow deliver_fault() caller to specify EA bit X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sat, 05 Aug 2017 01:45:16 -0000 On Fri, Aug 04, 2017 at 06:20:48PM +0100, Peter Maydell wrote: > For external aborts, we will want to be able to specify the EA > (external abort type) bit in the syndrome field. Allow callers of > deliver_fault() to do that by adding a field to ARMMMUFaultInfo which > we use when constructing the syndrome values. > > Signed-off-by: Peter Maydell Reviewed-by: Edgar E. Iglesias > --- > target/arm/internals.h | 2 ++ > target/arm/op_helper.c | 10 +++++----- > 2 files changed, 7 insertions(+), 5 deletions(-) > > diff --git a/target/arm/internals.h b/target/arm/internals.h > index 1f6efef..a3adbd8 100644 > --- a/target/arm/internals.h > +++ b/target/arm/internals.h > @@ -448,12 +448,14 @@ void arm_handle_psci_call(ARMCPU *cpu); > * @s2addr: Address that caused a fault at stage 2 > * @stage2: True if we faulted at stage 2 > * @s1ptw: True if we faulted at stage 2 while doing a stage 1 page-table walk > + * @ea: True if we should set the EA (external abort type) bit in syndrome > */ > typedef struct ARMMMUFaultInfo ARMMMUFaultInfo; > struct ARMMMUFaultInfo { > target_ulong s2addr; > bool stage2; > bool s1ptw; > + bool ea; > }; > > /* Do a page table walk and add page to TLB if possible */ > diff --git a/target/arm/op_helper.c b/target/arm/op_helper.c > index aa52a98..7eac272 100644 > --- a/target/arm/op_helper.c > +++ b/target/arm/op_helper.c > @@ -80,7 +80,7 @@ uint32_t HELPER(neon_tbl)(CPUARMState *env, uint32_t ireg, uint32_t def, > > static inline uint32_t merge_syn_data_abort(uint32_t template_syn, > unsigned int target_el, > - bool same_el, > + bool same_el, bool ea, > bool s1ptw, bool is_write, > int fsc) > { > @@ -99,7 +99,7 @@ static inline uint32_t merge_syn_data_abort(uint32_t template_syn, > */ > if (!(template_syn & ARM_EL_ISV) || target_el != 2 || s1ptw) { > syn = syn_data_abort_no_iss(same_el, > - 0, 0, s1ptw, is_write, fsc); > + ea, 0, s1ptw, is_write, fsc); > } else { > /* Fields: IL, ISV, SAS, SSE, SRT, SF and AR come from the template > * syndrome created at translation time. > @@ -107,7 +107,7 @@ static inline uint32_t merge_syn_data_abort(uint32_t template_syn, > */ > syn = syn_data_abort_with_iss(same_el, > 0, 0, 0, 0, 0, > - 0, 0, s1ptw, is_write, fsc, > + ea, 0, s1ptw, is_write, fsc, > false); > /* Merge the runtime syndrome with the template syndrome. */ > syn |= template_syn; > @@ -141,11 +141,11 @@ static void deliver_fault(ARMCPU *cpu, vaddr addr, MMUAccessType access_type, > } > > if (access_type == MMU_INST_FETCH) { > - syn = syn_insn_abort(same_el, 0, fi->s1ptw, fsc); > + syn = syn_insn_abort(same_el, fi->ea, fi->s1ptw, fsc); > exc = EXCP_PREFETCH_ABORT; > } else { > syn = merge_syn_data_abort(env->exception.syndrome, target_el, > - same_el, fi->s1ptw, > + same_el, fi->ea, fi->s1ptw, > access_type == MMU_DATA_STORE, > fsc); > if (access_type == MMU_DATA_STORE > -- > 2.7.4 > > From MAILER-DAEMON Sat Aug 05 00:47:33 2017 Received: from list by lists.gnu.org with archive (Exim 4.71) id 1ddqzt-0003eg-LD for mharc-qemu-arm@gnu.org; Sat, 05 Aug 2017 00:47:33 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:39848) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ddqzr-0003eJ-P6 for qemu-arm@nongnu.org; Sat, 05 Aug 2017 00:47:32 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ddqzn-0007oQ-QC for qemu-arm@nongnu.org; Sat, 05 Aug 2017 00:47:31 -0400 Received: from mail-lf0-x244.google.com ([2a00:1450:4010:c07::244]:36819) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ddqzn-0007nu-H9; Sat, 05 Aug 2017 00:47:27 -0400 Received: by mail-lf0-x244.google.com with SMTP id t128so2168293lff.3; Fri, 04 Aug 2017 21:47:27 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=date:from:to:cc:subject:message-id:references:mime-version :content-disposition:in-reply-to:user-agent; bh=tWDRJn1xzqJ2iiX7WaO5HK45MwkHVedTdss0s/17EKY=; b=VxXbSShqCNwSxcM0sQcQXXZNBmPXryt6eaJEruEgmWf9nRKXPBcKo6QKmbf5M2oNyU fAusOylaOeDv+ROUAPt0W86Azn7H5OAPUwatHKszfwW8xJ8KKRIlz80CBrwU3fWDf+4w 9EX21g0MdD7nr9xy6NjvhlcNdbqvxsekg6vVcYR9svuAftlFsBZF7NV/W11d3ORRpK+U 98VBeHihVkE1+grASCme1/cbGRDiSFbB8EFzyhLWtZONc31jPjyLjpbAB+f5drluCuVZ TUFhdldXuQwCDfJSKH11BkJbDpal0wEyPqaHhlhMxIlNGiqvt9wOPaImsk9QTq0EHf6t 8LiQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:in-reply-to:user-agent; bh=tWDRJn1xzqJ2iiX7WaO5HK45MwkHVedTdss0s/17EKY=; b=V3CB7ORFl4/xMWLhzIquTWaAEOyg66kOG19GDlyFrC2xw1hF538DBRgJC2yv+hCLDR IqjRsmgyp+bwtBKvbxO7ki75YbZzG8kIs5ANCEgpAdDpi3Poa17vdV65XS6MYuGC+LH4 iWBSwwRZdmRAU2Vgvk4BnrilxEq/nKH56Zmo9P9OHS1aX2h6Sns4iQcycS9uhdEP/5HY zm0gcpgcES4CelTUpNQCq0xgQKMht0kFbZvkj9QAIhV0jIk1/hPhLLN5F1oaD135PzqU JQqGZ4ITlYUl7HwV/vuopQGYSmqljpe4FN4CmA/PzBXRHXyVmZrgDL+YFjdepC5FHo42 dt6g== X-Gm-Message-State: AIVw111oJEBw4C89lxsSK0cMopfg2f1wz4UtAeSZdLFViyMXsNhTMosd fIF86mUUUkb7YQ== X-Received: by 10.46.80.11 with SMTP id e11mr1600204ljb.123.1501908445927; Fri, 04 Aug 2017 21:47:25 -0700 (PDT) Received: from gmail.com (81-231-233-234-no56.tbcn.telia.com. [81.231.233.234]) by smtp.gmail.com with ESMTPSA id z66sm888854lfd.3.2017.08.04.21.47.24 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 04 Aug 2017 21:47:25 -0700 (PDT) Date: Sat, 5 Aug 2017 06:47:24 +0200 From: "Edgar E. Iglesias" To: Richard Henderson Cc: Peter Maydell , qemu-arm@nongnu.org, qemu-devel@nongnu.org, patches@linaro.org Message-ID: <20170805044724.GH4859@toto> References: <1501692241-23310-1-git-send-email-peter.maydell@linaro.org> <1501692241-23310-10-git-send-email-peter.maydell@linaro.org> <20170803153800.GR4859@toto> <854126f3-84da-087c-f35b-480165871e7f@twiddle.net> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <854126f3-84da-087c-f35b-480165871e7f@twiddle.net> User-Agent: Mutt/1.5.24 (2015-08-30) X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4010:c07::244 Subject: Re: [Qemu-arm] [Qemu-devel] [PATCH 09/15] target/arm: Don't store M profile PRIMASK and FAULTMASK in daif X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sat, 05 Aug 2017 04:47:32 -0000 On Thu, Aug 03, 2017 at 03:05:17PM -0700, Richard Henderson wrote: > On 08/03/2017 08:38 AM, Edgar E. Iglesias wrote: > >> + uint32_t primask; > >> + uint32_t faultmask; > > It seems like these could be booleans? > > I was thinking the same thing until I read the v8m description as a 32-bit > register. This makes qemu match the spec, which has value. > Ah, I didn't check the spec :-) From MAILER-DAEMON Sat Aug 05 06:13:34 2017 Received: from list by lists.gnu.org with archive (Exim 4.71) id 1ddw5O-0006n0-O8 for mharc-qemu-arm@gnu.org; Sat, 05 Aug 2017 06:13:34 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:37880) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ddw5J-0006lu-AI for qemu-arm@nongnu.org; Sat, 05 Aug 2017 06:13:30 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ddw5I-00018U-1F for qemu-arm@nongnu.org; Sat, 05 Aug 2017 06:13:29 -0400 Received: from mail-wm0-x230.google.com ([2a00:1450:400c:c09::230]:38626) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ddw5H-00016Y-RI for qemu-arm@nongnu.org; Sat, 05 Aug 2017 06:13:27 -0400 Received: by mail-wm0-x230.google.com with SMTP id m85so36084607wma.1 for ; Sat, 05 Aug 2017 03:13:26 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:in-reply-to:references:from:date:message-id:subject:to :cc:content-transfer-encoding; bh=bO+Ep6mna8023m4YvFjz7bdG1dH0tqV6mTE929g2G+c=; b=W1bKuThxQwx47bX9MHVzmwh5rELyHOHDUU0aAjLKXFnDJI0zKVCPj8ZSOOssiYkhr3 GrX9geC0S+lfRHxJXYV/3SRxmTAEUuW4u3MDE9XwtGY0ycZ5i7we24TEWrGhSb/wDfEN mA84rU4VEdhKS41y5vDXhhb4VZvMLtYxSRhOk= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:in-reply-to:references:from:date :message-id:subject:to:cc:content-transfer-encoding; bh=bO+Ep6mna8023m4YvFjz7bdG1dH0tqV6mTE929g2G+c=; b=Fr4G1LbWWYQdJCBKQ6PbkV/T6scOizxIn9cbRqNgsQt/ljO4NMImLOrVHwAnxRSwY8 EpgclXHyizrXXNKhjkdgl2/y2MhvkEkX3Amy7/xLRhD3eYcYp7mbR+AleDaHFRDs32YV Kt538APGKa5jDRWpdKNpIp+34PQ/BnxLVlSlM3UY7iZ6yYJmjhKzT042LyfSX1pZKy1B aEMnnBgLk1I/3Z8sRubQtWbOWbMcBwKEpgBAylHcmwJgIk0qp/2ehg06L3yJpDO2pir0 I3AN0FchZF71Fyib8Asy1poIxDOhqCiNPgSHjr6w0XNS4TMTAvOXN8nfKPc15yrjbsXn QJZA== X-Gm-Message-State: AHYfb5iQgFBY2b6v3ZfQWoKUhHxsqCNel1Twd8sYYwMM7GzUfRXyMY1u dVrtFeZsJxLx3xBXVIJtHEltJu1B2+X1 X-Received: by 10.28.175.8 with SMTP id y8mr480572wme.42.1501928005021; Sat, 05 Aug 2017 03:13:25 -0700 (PDT) MIME-Version: 1.0 Received: by 10.223.134.54 with HTTP; Sat, 5 Aug 2017 03:13:04 -0700 (PDT) In-Reply-To: References: <1501867249-1924-1-git-send-email-peter.maydell@linaro.org> <1501867249-1924-5-git-send-email-peter.maydell@linaro.org> <50d6ba4d-cfa3-5b5f-5da1-dca2326d4f5d@amsat.org> From: Peter Maydell Date: Sat, 5 Aug 2017 11:13:04 +0100 Message-ID: To: Richard Henderson Cc: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= , qemu-arm , QEMU Developers Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:400c:c09::230 Subject: Re: [Qemu-arm] [PATCH 4/8] boards.h: Define new flag ignore_memory_transaction_failures X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sat, 05 Aug 2017 10:13:30 -0000 On 4 August 2017 at 20:23, Richard Henderson wrote: > On 08/04/2017 11:09 AM, Philippe Mathieu-Daud=C3=A9 wrote: >> Since create_unimplemented_device() register overlapped with low priorit= y, why >> not register it as default device directly, over the whole address space= ? > > That's a good suggestion. It makes more sense to me than adding a flag o= n the > MachineClass. Yeah, I did think about implementing it that way, but... That wouldn't handle the case of a device model directly returning a MEMTX_ERROR, or a transaction dispatched to a memory region whose MemoryRegionOps valid settings prohibit it (eg byte accesses to a word-access-only device), or accesses to a MemoryRegion that was created by passing a NULL MemoryRegionOps pointer to memory_region_init_io (I dunno why you'd do that but some code does). In short, there are lots of ways the memory subsystem might end up returning a transaction error -- this mechanism ensures that none of them start generating exceptions when they previously did not, and is (I hope) easy to review in the sense of being sure that it does what it intends to do without the need to audit a lot of corner cases. thanks -- PMM From MAILER-DAEMON Sat Aug 05 06:29:32 2017 Received: from list by lists.gnu.org with archive (Exim 4.71) id 1ddwKq-0003sh-Gg for mharc-qemu-arm@gnu.org; Sat, 05 Aug 2017 06:29:32 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:44825) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ddwKn-0003s9-W4 for qemu-arm@nongnu.org; Sat, 05 Aug 2017 06:29:31 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ddwKm-0000Ab-QR for qemu-arm@nongnu.org; Sat, 05 Aug 2017 06:29:30 -0400 Received: from mail-wr0-x235.google.com ([2a00:1450:400c:c0c::235]:36033) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ddwKm-00009a-JM for qemu-arm@nongnu.org; Sat, 05 Aug 2017 06:29:28 -0400 Received: by mail-wr0-x235.google.com with SMTP id y43so24243581wrd.3 for ; Sat, 05 Aug 2017 03:29:28 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:in-reply-to:references:from:date:message-id:subject:to :cc:content-transfer-encoding; bh=avR7gStxVzM3aNjxGPfhPrybJwCaqKC3HZhz5UHZYfs=; b=OztqT1KmzDCSattoo6bWLJxtF4oIekSaJhd6nlOVerdovHhloj6pdQ8ymw9SqeQ+pd JIuVHnxX1c23VE3Vm57syQEdnuufJK7U4WgOEKBFdg+ONyHVEMg5w7wcTqeMFYNkOBsQ AxuZ3imz5k1a9q1zN+XgLrSh6Ea33I3qMAyns= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:in-reply-to:references:from:date :message-id:subject:to:cc:content-transfer-encoding; bh=avR7gStxVzM3aNjxGPfhPrybJwCaqKC3HZhz5UHZYfs=; b=cgZ0uUy0JyGgns0+c69sjwAtD3x7LAFPVnLFPmq2yGUPqJjEcdBK9TeC/jdq8ku15B dkttwxkpax7dgTtJnDlF6PKCcUpZxfennooWaR0SQ47Qt/U8oqzBggvjNP+a/5fUeVr7 6nsuP+I+cRDDMDbPwQwBdKHu2Wys6bUyKW+EQ2IcOs0fpqPL2GEsePIYivwOWM/TtCuv IpiJBQDaisfpEArcHByhExiB4WdkirvK/6G6qLiqmsRL3r5UsC9WUb5Bm7CwVtI6I91V TejBGA2lgmc+a6/6JeqGzYFFv0+OdlKepHc/a3udl/RCQK1HIE1TWk3fBGnu3BFAahPD 3r6w== X-Gm-Message-State: AIVw113cuMI7i1xg1ScAQcfe8PvFp5puoCgkfkTXWnW6nU4S5artm1/y N98kTJLJ3ue5A1CfiMDgcKXVylMcHbLO X-Received: by 10.223.160.229 with SMTP id n34mr4274831wrn.117.1501928967478; Sat, 05 Aug 2017 03:29:27 -0700 (PDT) MIME-Version: 1.0 Received: by 10.223.134.54 with HTTP; Sat, 5 Aug 2017 03:29:06 -0700 (PDT) In-Reply-To: <50d6ba4d-cfa3-5b5f-5da1-dca2326d4f5d@amsat.org> References: <1501867249-1924-1-git-send-email-peter.maydell@linaro.org> <1501867249-1924-5-git-send-email-peter.maydell@linaro.org> <50d6ba4d-cfa3-5b5f-5da1-dca2326d4f5d@amsat.org> From: Peter Maydell Date: Sat, 5 Aug 2017 11:29:06 +0100 Message-ID: To: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= Cc: qemu-arm , QEMU Developers , Richard Henderson Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:400c:c0c::235 Subject: Re: [Qemu-arm] [PATCH 4/8] boards.h: Define new flag ignore_memory_transaction_failures X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sat, 05 Aug 2017 10:29:31 -0000 On 4 August 2017 at 19:09, Philippe Mathieu-Daud=C3=A9 wr= ote: > On 08/04/2017 02:20 PM, Peter Maydell wrote: >> We need this for ARM boards, where we're about to implement support for >> generating external aborts on memory transaction failures. Too many >> of our legacy board models rely on the RAZ/WI behaviour and we >> would break currently working guests when their "probe for device" >> code provoked an external abort rather than a RAZ. > I think some firmware will give some surprises, those probing device is n= ot > here and expect RAZ/WI. I remember some fw probing PCI space, or enumerat= ing > CS this way for ex. PCI space is funny anyway because IIRC the PCI spec mandates RAZ/WI (which is handled by QEMU's PCI implementation I think, it doesn't fall out to the memory system's unmapped-address handling). That said: yes, possibly some guest code really wants the fault (indeed the motivation for this patchset was having some test guest code which wanted to see the faults), but that guest code won't work on QEMU today, so if it doesn't boot on QEMU with this patchsets that's not a regression. We can then (as the issue arises) look at fixing whatever particular board model it is to properly model or stub out all its devices so we can boot that guest code without breaking existing working guest code. > RAZ/WI is a bus-feature, this is also bus-dependent to reply with abort o= r > behave RAZ/WI. Maybe the effort should be done on how model/use buses in > QEMU? Bus device would be an alias of unimplemented_device, which current > purpose is more debugging than avoiding unassigned physical access aborts= . You can model this kind of bus-dependent behaviour by having the bus register a background region which implements the default behaviour that is desired. (That way accesses to that part of the address space don't ever respond with a transaction error, which is what's happening on hardware where the bus doesn't report errors.) thanks -- PMM From MAILER-DAEMON Sat Aug 05 12:52:04 2017 Received: from list by lists.gnu.org with archive (Exim 4.71) id 1de2J2-0007UG-Hw for mharc-qemu-arm@gnu.org; Sat, 05 Aug 2017 12:52:04 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:34323) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1de2J0-0007Tv-F6 for qemu-arm@nongnu.org; Sat, 05 Aug 2017 12:52:03 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1de2Iz-0005GQ-5w for qemu-arm@nongnu.org; Sat, 05 Aug 2017 12:52:02 -0400 Received: from mail-wr0-x22f.google.com ([2a00:1450:400c:c0c::22f]:36341) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1de2Iy-0005Ey-Uj for qemu-arm@nongnu.org; Sat, 05 Aug 2017 12:52:01 -0400 Received: by mail-wr0-x22f.google.com with SMTP id y43so26134137wrd.3 for ; Sat, 05 Aug 2017 09:52:00 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:in-reply-to:references:from:date:message-id:subject:to :cc; bh=LJ45qLcsThY5Vctj4iwE8GoGw+aOaOztX6iVhqDdEgM=; b=En9sBRcvLAhnA53c3WenmVU6Mf3tSXs4FA0c7ErRORRiUSB2q9r7Zg3DupcgSEil1t sSuV7uTIB/XdmDmoudnym6r7j71sgJeut92IiniV4IPUCmJIDGOYPPue8Dy5EOc3QWog KlyycrmkcJfsbe8smHL/0uZZJUtGKGuDO2+Ic= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:in-reply-to:references:from:date :message-id:subject:to:cc; bh=LJ45qLcsThY5Vctj4iwE8GoGw+aOaOztX6iVhqDdEgM=; b=PW8ZWJzGM2GNih57QTGuOw+Wy6d0ylEwkbP3wAB89WnQT2bYUNqz/kQfMclqBs6qPd 7hfc/xfqAr8CqTK2mpGTLwjbXPyL4hPkeW/TYP72b95/zP0bfEcijsPJ5I/+R5bpcTTp GpEYVoIhwAVITMpV6JkvWoi6OoU0HDMRTURlOL0MXte0KdRzveaC4q8TYkqgGxjoluRX PQ74vQzlEkco3ypy2HOSjQI1xPs/vndicyBP8FL6kJHkJfCkd7lRdc70ExyAWn82xQXk BOd9dw3Kgv+nAO4imNh9lgG/CbArCiDN08zdKtMe7I4aBcHDTVAQATtxrK5LdJSYeulh FnNQ== X-Gm-Message-State: AIVw111jVpmzAkMJqcs9poYuW1vI0Y/JcIFhdc3qqaDUrVxgSm+cGsEW mT/IXPBNvIQ3BpTwLcHIgXA/rtuOVupC X-Received: by 10.223.174.242 with SMTP id y105mr5079170wrc.262.1501951919332; Sat, 05 Aug 2017 09:51:59 -0700 (PDT) MIME-Version: 1.0 Received: by 10.223.134.54 with HTTP; Sat, 5 Aug 2017 09:51:38 -0700 (PDT) In-Reply-To: <20170805010622.GZ4859@toto> References: <1501867249-1924-1-git-send-email-peter.maydell@linaro.org> <1501867249-1924-3-git-send-email-peter.maydell@linaro.org> <20170805010622.GZ4859@toto> From: Peter Maydell Date: Sat, 5 Aug 2017 17:51:38 +0100 Message-ID: To: "Edgar E. Iglesias" Cc: qemu-arm , QEMU Developers , Richard Henderson , "patches@linaro.org" Content-Type: text/plain; charset="UTF-8" X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:400c:c0c::22f Subject: Re: [Qemu-arm] [PATCH 2/8] cpu: Define new cpu_transaction_failed() hook X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sat, 05 Aug 2017 16:52:03 -0000 On 5 August 2017 at 02:06, Edgar E. Iglesias wrote: > On Fri, Aug 04, 2017 at 06:20:43PM +0100, Peter Maydell wrote: >> @@ -85,8 +85,10 @@ struct TranslationBlock; >> * @has_work: Callback for checking if there is work to do. >> * @do_interrupt: Callback for interrupt handling. >> * @do_unassigned_access: Callback for unassigned access handling. >> + * (this is deprecated: new targets should use do_transaction_failed instead) >> * @do_unaligned_access: Callback for unaligned access handling, if >> * the target defines #ALIGNED_ONLY. >> + * @do_transaction_failed: Callback for handling failed memory transactions > > Looks OK but I wonder if there you might want to clarify that this is a > bus/slave failure and not a failure within the CPU (e.g not an MMU fault). Yes, we could add "(ie bus faults or external aborts; not MMU faults)" just to clarify. thanks -- PMM From MAILER-DAEMON Sat Aug 05 13:18:31 2017 Received: from list by lists.gnu.org with archive (Exim 4.71) id 1de2id-0004Yc-3H for mharc-qemu-arm@gnu.org; Sat, 05 Aug 2017 13:18:31 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:41849) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1de2ia-0004Xr-NP for qemu-arm@nongnu.org; Sat, 05 Aug 2017 13:18:29 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1de2iZ-0000NS-Jp for qemu-arm@nongnu.org; Sat, 05 Aug 2017 13:18:28 -0400 Received: from mail-wr0-x22f.google.com ([2a00:1450:400c:c0c::22f]:37957) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1de2iZ-0000MQ-D2 for qemu-arm@nongnu.org; Sat, 05 Aug 2017 13:18:27 -0400 Received: by mail-wr0-x22f.google.com with SMTP id f21so26203883wrf.5 for ; Sat, 05 Aug 2017 10:18:27 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:in-reply-to:references:from:date:message-id:subject:to :cc; bh=DrSQE4G0LvNil9UVkDUrBIbBzyabnsoDl5pre3EeV8k=; b=O2G/fMrFBiHH3Qeb+HtsLkWjw7mjGB2NfSc7Kb9PoJ2AknZ9xAoNSwlMCsBwRUWszT f2dHDKJ0huEru7Tj/aPoeeerIyoicDIkq9/DHbt3SlmAHI98ljrYxdHWfPYWhWq+X856 606CilO2UIXi0SuSxlXWvwKqf3kVCwZac7aWs= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:in-reply-to:references:from:date :message-id:subject:to:cc; bh=DrSQE4G0LvNil9UVkDUrBIbBzyabnsoDl5pre3EeV8k=; b=s2ERvV71o8lVc9xH7Y6lCgkVkB8k7j8iRI9vVLUrdApvkFtMoW2pEyTl/Ggrv7ITMW l1dL4MCm7H/nTKJARoBEMkwLNL2sHlZUKwP678cGfJu+e0mEQmLssKybdjVky8btz20H hnesUdBK8pqX8dkr6V5vmvktc8T/D6SK1UcvWLj7XeyCGR5Zk0TB2cri3jrtD2EriABJ oSuLe4QgcgDqLmp0kYicZNVohZsIrMNpfG3cV8spbQdnqSeqeiSfu3DhiZam4hG7i303 sfUrPy6tlfsC78RZrXt2ON+DHsUyeRpc+2cXiVUx/t5RegGT67F4qoOdbsIu0SYhp8jw /NoA== X-Gm-Message-State: AIVw113MJ8a26qorwDGjuiMZc4ZoFBKPuj0P0Q71ck4dn1k6040FvLih tT4JyPrhIBOAaJTjSHLSlcAQ8QigkdNI X-Received: by 10.223.174.242 with SMTP id y105mr5122003wrc.262.1501953506167; Sat, 05 Aug 2017 10:18:26 -0700 (PDT) MIME-Version: 1.0 Received: by 10.223.134.54 with HTTP; Sat, 5 Aug 2017 10:18:05 -0700 (PDT) In-Reply-To: <20170805011209.GA4859@toto> References: <1501867249-1924-1-git-send-email-peter.maydell@linaro.org> <1501867249-1924-3-git-send-email-peter.maydell@linaro.org> <20170805011209.GA4859@toto> From: Peter Maydell Date: Sat, 5 Aug 2017 18:18:05 +0100 Message-ID: To: "Edgar E. Iglesias" Cc: qemu-arm , QEMU Developers , Richard Henderson , "patches@linaro.org" , Laurent Vivier Content-Type: text/plain; charset="UTF-8" X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:400c:c0c::22f Subject: Re: [Qemu-arm] [PATCH 2/8] cpu: Define new cpu_transaction_failed() hook X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sat, 05 Aug 2017 17:18:29 -0000 On 5 August 2017 at 02:12, Edgar E. Iglesias wrote: > BTW, a question. I don't know of any from memory but does any arch > have the ability to report the payload that failed for stores? > I guess it's easy enough to add that if needed though. I think maybe m68k bus fault stack frames have store payload data? The description of them is pretty complicated though and I'm not sure how much of the frame is "stuff we actually need to emulate" vs "data that's only important if your implementation pipelines instruction execution"... As you say, we can easily add a 'uint64_t data' (only valid when access_type == MMU_DATA_STORE), either now or later. thanks -- PMM From MAILER-DAEMON Mon Aug 07 07:50:02 2017 Received: from list by lists.gnu.org with archive (Exim 4.71) id 1degXq-00021x-RB for mharc-qemu-arm@gnu.org; Mon, 07 Aug 2017 07:50:02 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:39965) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1degXk-0001yJ-Gt for qemu-arm@nongnu.org; Mon, 07 Aug 2017 07:50:01 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1degXf-0006gX-Ne for qemu-arm@nongnu.org; Mon, 07 Aug 2017 07:49:56 -0400 Received: from mx1.redhat.com ([209.132.183.28]:55748) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1degXf-0006gN-Hk; Mon, 07 Aug 2017 07:49:51 -0400 Received: from smtp.corp.redhat.com (int-mx05.intmail.prod.int.phx2.redhat.com [10.5.11.15]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id 76B2C80E6A; Mon, 7 Aug 2017 11:49:50 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mx1.redhat.com 76B2C80E6A Authentication-Results: ext-mx01.extmail.prod.ext.phx2.redhat.com; dmarc=none (p=none dis=none) header.from=redhat.com Authentication-Results: ext-mx01.extmail.prod.ext.phx2.redhat.com; spf=fail smtp.mailfrom=eric.auger@redhat.com Received: from AMD.redhat.com (ovpn-117-173.ams2.redhat.com [10.36.117.173]) by smtp.corp.redhat.com (Postfix) with ESMTP id 707F67E69D; Mon, 7 Aug 2017 11:49:48 +0000 (UTC) From: Eric Auger To: eric.auger@redhat.com, eric.auger.pro@gmail.com, qemu-devel@nongnu.org, qemu-arm@nongnu.org, peter.maydell@linaro.org Cc: drjones@redhat.com Date: Mon, 7 Aug 2017 11:49:41 +0000 Message-Id: <1502106581-11714-1-git-send-email-eric.auger@redhat.com> X-Scanned-By: MIMEDefang 2.79 on 10.5.11.15 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.25]); Mon, 07 Aug 2017 11:49:50 +0000 (UTC) X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.132.183.28 Subject: [Qemu-arm] [PATCH for-2.10] hw/arm/virt: Add 2.10 machine type X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 07 Aug 2017 11:50:01 -0000 Add virt-2.10 machine type. Signed-off-by: Eric Auger --- --- hw/arm/virt.c | 19 +++++++++++++++++-- 1 file changed, 17 insertions(+), 2 deletions(-) diff --git a/hw/arm/virt.c b/hw/arm/virt.c index 31739d7..6b7a0fe 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -1639,7 +1639,7 @@ static void machvirt_machine_init(void) } type_init(machvirt_machine_init); -static void virt_2_9_instance_init(Object *obj) +static void virt_2_10_instance_init(Object *obj) { VirtMachineState *vms = VIRT_MACHINE(obj); VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms); @@ -1699,10 +1699,25 @@ static void virt_2_9_instance_init(Object *obj) vms->irqmap = a15irqmap; } +static void virt_machine_2_10_options(MachineClass *mc) +{ +} +DEFINE_VIRT_MACHINE_AS_LATEST(2, 10) + +#define VIRT_COMPAT_2_9 \ + HW_COMPAT_2_9 + +static void virt_2_9_instance_init(Object *obj) +{ + virt_2_10_instance_init(obj); +} + static void virt_machine_2_9_options(MachineClass *mc) { + virt_machine_2_10_options(mc); + SET_MACHINE_COMPAT(mc, VIRT_COMPAT_2_9); } -DEFINE_VIRT_MACHINE_AS_LATEST(2, 9) +DEFINE_VIRT_MACHINE(2, 9) #define VIRT_COMPAT_2_8 \ HW_COMPAT_2_8 -- 1.9.1 From MAILER-DAEMON Mon Aug 07 08:14:31 2017 Received: from list by lists.gnu.org with archive (Exim 4.71) id 1degvX-00047v-BW for mharc-qemu-arm@gnu.org; Mon, 07 Aug 2017 08:14:31 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:46322) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1degvQ-000442-Js for qemu-arm@nongnu.org; Mon, 07 Aug 2017 08:14:29 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1degvL-00009z-DE for qemu-arm@nongnu.org; Mon, 07 Aug 2017 08:14:24 -0400 Received: from mx1.redhat.com ([209.132.183.28]:38704) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1degvL-00009Q-73; Mon, 07 Aug 2017 08:14:19 -0400 Received: from smtp.corp.redhat.com (int-mx06.intmail.prod.int.phx2.redhat.com [10.5.11.16]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id 3F03F15565; Mon, 7 Aug 2017 12:14:18 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mx1.redhat.com 3F03F15565 Authentication-Results: ext-mx05.extmail.prod.ext.phx2.redhat.com; dmarc=none (p=none dis=none) header.from=redhat.com Authentication-Results: ext-mx05.extmail.prod.ext.phx2.redhat.com; spf=fail smtp.mailfrom=drjones@redhat.com Received: from kamzik.brq.redhat.com (unknown [10.43.2.160]) by smtp.corp.redhat.com (Postfix) with ESMTPS id 1629C18232; Mon, 7 Aug 2017 12:14:12 +0000 (UTC) Date: Mon, 7 Aug 2017 14:14:10 +0200 From: Andrew Jones To: Eric Auger Cc: eric.auger.pro@gmail.com, qemu-devel@nongnu.org, qemu-arm@nongnu.org, peter.maydell@linaro.org Message-ID: <20170807121410.2h5k6duxw7aia3ow@kamzik.brq.redhat.com> References: <1502106581-11714-1-git-send-email-eric.auger@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1502106581-11714-1-git-send-email-eric.auger@redhat.com> User-Agent: Mutt/1.6.0.1 (2016-04-01) X-Scanned-By: MIMEDefang 2.79 on 10.5.11.16 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.29]); Mon, 07 Aug 2017 12:14:18 +0000 (UTC) X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.132.183.28 Subject: Re: [Qemu-arm] [Qemu-devel] [PATCH for-2.10] hw/arm/virt: Add 2.10 machine type X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 07 Aug 2017 12:14:29 -0000 On Mon, Aug 07, 2017 at 11:49:41AM +0000, Eric Auger wrote: > Add virt-2.10 machine type. > > Signed-off-by: Eric Auger > > --- > --- > hw/arm/virt.c | 19 +++++++++++++++++-- > 1 file changed, 17 insertions(+), 2 deletions(-) > > diff --git a/hw/arm/virt.c b/hw/arm/virt.c > index 31739d7..6b7a0fe 100644 > --- a/hw/arm/virt.c > +++ b/hw/arm/virt.c > @@ -1639,7 +1639,7 @@ static void machvirt_machine_init(void) > } > type_init(machvirt_machine_init); > > -static void virt_2_9_instance_init(Object *obj) > +static void virt_2_10_instance_init(Object *obj) > { > VirtMachineState *vms = VIRT_MACHINE(obj); > VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms); > @@ -1699,10 +1699,25 @@ static void virt_2_9_instance_init(Object *obj) > vms->irqmap = a15irqmap; > } > > +static void virt_machine_2_10_options(MachineClass *mc) > +{ > +} > +DEFINE_VIRT_MACHINE_AS_LATEST(2, 10) > + > +#define VIRT_COMPAT_2_9 \ > + HW_COMPAT_2_9 > + > +static void virt_2_9_instance_init(Object *obj) > +{ > + virt_2_10_instance_init(obj); > +} > + > static void virt_machine_2_9_options(MachineClass *mc) > { > + virt_machine_2_10_options(mc); > + SET_MACHINE_COMPAT(mc, VIRT_COMPAT_2_9); > } > -DEFINE_VIRT_MACHINE_AS_LATEST(2, 9) > +DEFINE_VIRT_MACHINE(2, 9) > > #define VIRT_COMPAT_2_8 \ > HW_COMPAT_2_8 > -- > 1.9.1 > > Reviewed-by: Andrew Jones From MAILER-DAEMON Mon Aug 07 09:56:29 2017 Received: from list by lists.gnu.org with archive (Exim 4.71) id 1deiWD-0000R8-JO for mharc-qemu-arm@gnu.org; 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X-Received-From: 2a00:1450:400c:c09::234 Subject: Re: [Qemu-arm] [Qemu-devel] [PATCH for-2.10] hw/arm/virt: Add 2.10 machine type X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 07 Aug 2017 13:56:28 -0000 On 7 August 2017 at 13:14, Andrew Jones wrote: > On Mon, Aug 07, 2017 at 11:49:41AM +0000, Eric Auger wrote: >> Add virt-2.10 machine type. >> >> Signed-off-by: Eric Auger >> >> --- Applied to master, thanks. -- PMM From MAILER-DAEMON Mon Aug 07 10:39:37 2017 Received: from list by lists.gnu.org with archive (Exim 4.71) id 1dejBx-0002i1-By for mharc-qemu-arm@gnu.org; Mon, 07 Aug 2017 10:39:37 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:45028) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dejBq-0002hJ-Fn for qemu-arm@nongnu.org; Mon, 07 Aug 2017 10:39:35 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dejBl-0006QQ-Bi for qemu-arm@nongnu.org; Mon, 07 Aug 2017 10:39:30 -0400 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:36782) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1dejBl-0006M3-3Y; Mon, 07 Aug 2017 10:39:25 -0400 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1dejBc-0004Oy-7s; Mon, 07 Aug 2017 15:39:16 +0100 From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: patches@linaro.org, Richard Henderson , Hua Yanghao Date: Mon, 7 Aug 2017 15:39:13 +0100 Message-Id: <1502116754-18867-2-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1502116754-18867-1-git-send-email-peter.maydell@linaro.org> References: <1502116754-18867-1-git-send-email-peter.maydell@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-arm] [PATCH 1/2] loader: Handle ELF files with overlapping zero-initialized data X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 07 Aug 2017 14:39:35 -0000 For embedded systems, notably ARM, one common use of ELF file segments is that the 'physical addresses' represent load addresses and the 'virtual addresses' execution addresses, such that the load addresses are packed into ROM or flash, and the relocation and zero-initialization of data is done at runtime. This means that the 'memsz' in the segment header represents the runtime size of the segment, but the size that needs to be loaded is only the 'filesz'. In particular, paddr+memsz may overlap with the next segment to be loaded, as in this example: 0x70000001 off 0x00007f68 vaddr 0x00008150 paddr 0x00008150 align 2**2 filesz 0x00000008 memsz 0x00000008 flags r-- LOAD off 0x000000f4 vaddr 0x00000000 paddr 0x00000000 align 2**2 filesz 0x00000124 memsz 0x00000124 flags r-- LOAD off 0x00000218 vaddr 0x00000400 paddr 0x00000400 align 2**3 filesz 0x00007d58 memsz 0x00007d58 flags r-x LOAD off 0x00007f70 vaddr 0x20000140 paddr 0x00008158 align 2**3 filesz 0x00000a80 memsz 0x000022f8 flags rw- LOAD off 0x000089f0 vaddr 0x20002438 paddr 0x00008bd8 align 2**0 filesz 0x00000000 memsz 0x00004000 flags rw- LOAD off 0x000089f0 vaddr 0x20000000 paddr 0x20000000 align 2**0 filesz 0x00000000 memsz 0x00000140 flags rw- where the segment at paddr 0x8158 has a memsz of 0x2258 and would overlap with the segment at paddr 0x8bd8 if QEMU's loader tried to honour it. (At runtime the segments will not overlap since their vaddrs are more widely spaced than their paddrs.) Currently if you try to load an ELF file like this with QEMU then it will fail with an error "rom: requested regions overlap", because we create a ROM image for each segment using the memsz as the size. Support ELF files using this scheme, by truncating the zero-initialized part of the segment if it would overlap another segment. This will retain the existing loader behaviour for all ELF files we currently accept, and also accept ELF files which only need 'filesz' bytes to be loaded. Signed-off-by: Peter Maydell --- include/hw/elf_ops.h | 48 ++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 48 insertions(+) diff --git a/include/hw/elf_ops.h b/include/hw/elf_ops.h index a172a60..2e526d3 100644 --- a/include/hw/elf_ops.h +++ b/include/hw/elf_ops.h @@ -362,6 +362,54 @@ static int glue(load_elf, SZ)(const char *name, int fd, goto fail; } } + + /* The ELF spec is somewhat vague about the purpose of the + * physical address field. One common use in the embedded world + * is that physical address field specifies the load address + * and the virtual address field specifies the execution address. + * Segments are packed into ROM or flash, and the relocation + * and zero-initialization of data is done at runtime. This + * means that the memsz header represents the runtime size of the + * segment, but the filesz represents the loadtime size. If + * we try to honour the memsz value for an ELF file like this + * we will end up with overlapping segments (which the + * loader.c code will later reject). + * We support ELF files using this scheme by by checking whether + * paddr + memsz for this segment would overlap with any other + * segment. If so, then we assume it's using this scheme and + * truncate the loaded segment to the filesz size. + * If the segment considered as being memsz size doesn't overlap + * then we use memsz for the segment length, to handle ELF files + * which assume that the loader will do the zero-initialization. + */ + if (mem_size > file_size) { + /* If this segment's zero-init portion overlaps another + * segment's data or zero-init portion, then truncate this one. + * Invalid ELF files where the segments overlap even when + * only file_size bytes are loaded will be rejected by + * the ROM overlap check in loader.c, so we don't try to + * explicitly detect those here. + */ + int j; + elf_word zero_start = ph->p_paddr + file_size; + elf_word zero_end = ph->p_paddr + mem_size; + + for (j = 0; j < ehdr.e_phnum; j++) { + struct elf_phdr *jph = &phdr[j]; + + if (i != j && jph->p_type == PT_LOAD) { + elf_word other_start = jph->p_paddr; + elf_word other_end = jph->p_paddr + jph->p_memsz; + + if (!(other_start >= zero_end || + zero_start >= other_end)) { + mem_size = file_size; + break; + } + } + } + } + /* address_offset is hack for kernel images that are linked at the wrong physical address. */ if (translate_fn) { -- 2.7.4 From MAILER-DAEMON Mon Aug 07 10:39:40 2017 Received: from list by lists.gnu.org with archive (Exim 4.71) id 1dejC0-0002of-G6 for mharc-qemu-arm@gnu.org; Mon, 07 Aug 2017 10:39:40 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:45065) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dejBu-0002ha-A0 for qemu-arm@nongnu.org; Mon, 07 Aug 2017 10:39:39 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dejBp-0006SF-CQ for qemu-arm@nongnu.org; Mon, 07 Aug 2017 10:39:34 -0400 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:36782) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1dejBp-0006M3-4x; Mon, 07 Aug 2017 10:39:29 -0400 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1dejBc-0004PB-T6; Mon, 07 Aug 2017 15:39:16 +0100 From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: patches@linaro.org, Richard Henderson , Hua Yanghao Date: Mon, 7 Aug 2017 15:39:14 +0100 Message-Id: <1502116754-18867-3-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1502116754-18867-1-git-send-email-peter.maydell@linaro.org> References: <1502116754-18867-1-git-send-email-peter.maydell@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-arm] [PATCH 2/2] loader: Ignore zero-sized ELF segments X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 07 Aug 2017 14:39:39 -0000 Some ELF files have program headers that specify segments that are of zero size. Ignore them, rather than trying to create zero-length ROM blobs for them, because the zero-length blob can falsely trigger the overlapping-ROM-blobs check. Signed-off-by: Peter Maydell --- include/hw/elf_ops.h | 24 +++++++++++++++++------- 1 file changed, 17 insertions(+), 7 deletions(-) diff --git a/include/hw/elf_ops.h b/include/hw/elf_ops.h index 2e526d3..d192e7e 100644 --- a/include/hw/elf_ops.h +++ b/include/hw/elf_ops.h @@ -451,14 +451,24 @@ static int glue(load_elf, SZ)(const char *name, int fd, *pentry = ehdr.e_entry - ph->p_vaddr + ph->p_paddr; } - if (load_rom) { - snprintf(label, sizeof(label), "phdr #%d: %s", i, name); - - /* rom_add_elf_program() seize the ownership of 'data' */ - rom_add_elf_program(label, data, file_size, mem_size, addr, as); - } else { - cpu_physical_memory_write(addr, data, file_size); + if (mem_size == 0) { + /* Some ELF files really do have segments of zero size; + * just ignore them rather than trying to create empty + * ROM blobs, because the zero-length blob can falsely + * trigger the overlapping-ROM-blobs check. + */ g_free(data); + } else { + if (load_rom) { + snprintf(label, sizeof(label), "phdr #%d: %s", i, name); + + /* rom_add_elf_program() seize the ownership of 'data' */ + rom_add_elf_program(label, data, file_size, mem_size, + addr, as); + } else { + cpu_physical_memory_write(addr, data, file_size); + g_free(data); + } } total_size += mem_size; -- 2.7.4 From MAILER-DAEMON Mon Aug 07 10:39:41 2017 Received: from list by lists.gnu.org with archive (Exim 4.71) id 1dejC1-0002rx-Ey for mharc-qemu-arm@gnu.org; Mon, 07 Aug 2017 10:39:41 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:45074) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dejBv-0002hl-9C for qemu-arm@nongnu.org; Mon, 07 Aug 2017 10:39:40 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dejBq-0006T2-Br for qemu-arm@nongnu.org; Mon, 07 Aug 2017 10:39:35 -0400 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:36782) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1dejBq-0006M3-5E; Mon, 07 Aug 2017 10:39:30 -0400 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1dejBb-0004Ol-He; Mon, 07 Aug 2017 15:39:15 +0100 From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: patches@linaro.org, Richard Henderson , Hua Yanghao Date: Mon, 7 Aug 2017 15:39:12 +0100 Message-Id: <1502116754-18867-1-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 2.7.4 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-arm] [PATCH 0/2] loader: Handle ELF files with overlapping zero-init data X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 07 Aug 2017 14:39:40 -0000 For embedded systems, notably ARM, one common use of ELF file segments is that the 'physical addresses' represent load addresses and the 'virtual addresses' execution addresses, such that the load addresses are packed into ROM or flash, and the relocation and zero-initialization of data is done at runtime. This means that the 'memsz' in the segment header represents the runtime size of the segment, but the size that needs to be loaded is only the 'filesz'. In particular, paddr+memsz may overlap with another segment to be loaded, as in this example: 0x70000001 off 0x00007f68 vaddr 0x00008150 paddr 0x00008150 align 2**2 filesz 0x00000008 memsz 0x00000008 flags r-- LOAD off 0x000000f4 vaddr 0x00000000 paddr 0x00000000 align 2**2 filesz 0x00000124 memsz 0x00000124 flags r-- LOAD off 0x00000218 vaddr 0x00000400 paddr 0x00000400 align 2**3 filesz 0x00007d58 memsz 0x00007d58 flags r-x LOAD off 0x00007f70 vaddr 0x20000140 paddr 0x00008158 align 2**3 filesz 0x00000a80 memsz 0x000022f8 flags rw- LOAD off 0x000089f0 vaddr 0x20002438 paddr 0x00008bd8 align 2**0 filesz 0x00000000 memsz 0x00004000 flags rw- LOAD off 0x000089f0 vaddr 0x20000000 paddr 0x20000000 align 2**0 filesz 0x00000000 memsz 0x00000140 flags rw- where the segment at paddr 0x8158 has a memsz of 0x2258 and would overlap with the segment at paddr 0x8bd8 if QEMU's loader tried to honour it. (At runtime the segments will not overlap since their vaddrs are more widely spaced than their paddrs.) Currently if you try to load an ELF file like this with QEMU then it will fail with an error "rom: requested regions overlap", because we create a ROM image for each segment using the memsz as the size. This patchset adds support for ELF files using this scheme, by truncating the zero-initialized part of the segment if it would overlap another segment. This will retain the existing loader behaviour for all ELF files we currently accept, and also accept ELF files which only need 'filesz' bytes to be loaded. Patch 2 deals with a vaguely related issue which is that if the ELF file specified a zero-length segment we would happily try to create a zero-length ROM blob, which could then falsely trigger the ROM-overlap check. (The zero-length case is more common after patch 1 has done its truncation thing, but I have seen real-world ELF files with both filesz and memsz zero...) thanks -- PMM Peter Maydell (2): loader: Handle ELF files with overlapping zero-initialized data loader: Ignore zero-sized ELF segments include/hw/elf_ops.h | 72 +++++++++++++++++++++++++++++++++++++++++++++++----- 1 file changed, 65 insertions(+), 7 deletions(-) -- 2.7.4 From MAILER-DAEMON Mon Aug 07 16:59:19 2017 Received: from list by lists.gnu.org with archive (Exim 4.71) id 1dep7P-0001yL-6J for mharc-qemu-arm@gnu.org; Mon, 07 Aug 2017 16:59:19 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:58789) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dep7I-0001uR-N2 for qemu-arm@nongnu.org; Mon, 07 Aug 2017 16:59:17 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dep7D-0006Oj-Se for qemu-arm@nongnu.org; Mon, 07 Aug 2017 16:59:12 -0400 Received: from mail-qt0-x244.google.com ([2607:f8b0:400d:c0d::244]:38894) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1dep73-0006GF-In; Mon, 07 Aug 2017 16:58:57 -0400 Received: by mail-qt0-x244.google.com with SMTP id p3so1653805qtg.5; Mon, 07 Aug 2017 13:58:57 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:subject:to:cc:references:from:message-id:date:user-agent :mime-version:in-reply-to:content-language:content-transfer-encoding; bh=j/sUL0k2MWSH4SoGsDtT+wceoeOcecB2CSHMT4nDxaQ=; b=OhL3UGF4v4986oCWcVdLz8o5X4Gp3ktbzJl8G9JAKfzqjtRQ2cLetpZIMJBDO4Z5EW h2mJVXkaKfc4DY44DwL6nOLm+hGYLSYUIutZZVF+yyql5d+STgWAkUxzIigAO8hqPMcF vyaOgkLdhmP28lOhGTOWf+rR+xsihLjBzUD2VLXU1BTfB/6cawHU1vMxBwfJMIqN0/dn OhT9q3C0U9bf/jRWyEF9klYMSrlVwNngLUulyA1xLXccUUtlJGERveEbS/TGjheTSrom gb7WMVkmHsUPZ3VMWiLYat0ZQ7wn/lip2+3EhX+tk+IL1ufnV0A/VMt9s7Sr61C9ycbZ aiGA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:subject:to:cc:references:from:message-id :date:user-agent:mime-version:in-reply-to:content-language :content-transfer-encoding; bh=j/sUL0k2MWSH4SoGsDtT+wceoeOcecB2CSHMT4nDxaQ=; b=V+2Sgth4mvv/fxgNzPL66/lkjOJdTpk46lNVZ2ztZMyKFMXd3BWJ4OacdAK9d5674Y mD4HXxUEDtp3OTdic2HzkvEyj8U3w3C0bu+yktRpcgnQrSCmDsNbsNs1nbYbpvU4vDJD BxM0fRvymOWTUexQcmI0FkHWp3m8PrMRcODCyIze1CutzqL2YzkG8tL22v4EA6/GIgYj JoyMyitFMX10vU0QzITwEa5r39YtFOa+S1I6saylYGRCtuoTBxHnDPpA71peEm69AKzv mh+JE8CUPFjYIQYIMr7dAGBZLz6Gie4SY/6uYsaxfS1dvVBQLEoO7nOurvrIYrTHIZP8 eeOQ== X-Gm-Message-State: AHYfb5iPT/HsaNfXEpcOuLO8Ae97CjXAWPk0bmQXDysciS7qGXE9U48U 2uKi9MbsSziEGQ== X-Received: by 10.200.3.195 with SMTP id z3mr2679325qtg.185.1502139536919; Mon, 07 Aug 2017 13:58:56 -0700 (PDT) Received: from [192.168.1.10] ([138.117.48.223]) by smtp.gmail.com with ESMTPSA id z30sm4175935qta.84.2017.08.07.13.58.54 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 07 Aug 2017 13:58:56 -0700 (PDT) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= To: Peter Maydell , qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Hua Yanghao , Richard Henderson , patches@linaro.org References: <1502116754-18867-1-git-send-email-peter.maydell@linaro.org> <1502116754-18867-3-git-send-email-peter.maydell@linaro.org> From: =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= Message-ID: <3913adf1-78be-e668-57d6-5f9ba2910962@amsat.org> Date: Mon, 7 Aug 2017 17:58:52 -0300 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.2.1 MIME-Version: 1.0 In-Reply-To: <1502116754-18867-3-git-send-email-peter.maydell@linaro.org> Content-Type: text/plain; charset=utf-8; format=flowed Content-Language: en-US Content-Transfer-Encoding: 8bit X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400d:c0d::244 Subject: Re: [Qemu-arm] [PATCH 2/2] loader: Ignore zero-sized ELF segments X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 07 Aug 2017 20:59:17 -0000 On 08/07/2017 11:39 AM, Peter Maydell wrote: > Some ELF files have program headers that specify segments that > are of zero size. Ignore them, rather than trying to create > zero-length ROM blobs for them, because the zero-length blob > can falsely trigger the overlapping-ROM-blobs check. > > Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daudé > --- > include/hw/elf_ops.h | 24 +++++++++++++++++------- > 1 file changed, 17 insertions(+), 7 deletions(-) > > diff --git a/include/hw/elf_ops.h b/include/hw/elf_ops.h > index 2e526d3..d192e7e 100644 > --- a/include/hw/elf_ops.h > +++ b/include/hw/elf_ops.h > @@ -451,14 +451,24 @@ static int glue(load_elf, SZ)(const char *name, int fd, > *pentry = ehdr.e_entry - ph->p_vaddr + ph->p_paddr; > } > > - if (load_rom) { > - snprintf(label, sizeof(label), "phdr #%d: %s", i, name); > - > - /* rom_add_elf_program() seize the ownership of 'data' */ > - rom_add_elf_program(label, data, file_size, mem_size, addr, as); > - } else { > - cpu_physical_memory_write(addr, data, file_size); > + if (mem_size == 0) { > + /* Some ELF files really do have segments of zero size; > + * just ignore them rather than trying to create empty > + * ROM blobs, because the zero-length blob can falsely > + * trigger the overlapping-ROM-blobs check. > + */ > g_free(data); > + } else { > + if (load_rom) { > + snprintf(label, sizeof(label), "phdr #%d: %s", i, name); > + > + /* rom_add_elf_program() seize the ownership of 'data' */ > + rom_add_elf_program(label, data, file_size, mem_size, > + addr, as); > + } else { > + cpu_physical_memory_write(addr, data, file_size); > + g_free(data); > + } > } > > total_size += mem_size; > From MAILER-DAEMON Mon Aug 07 19:12:05 2017 Received: from list by lists.gnu.org with archive (Exim 4.71) id 1derBt-0002eO-Si for mharc-qemu-arm@gnu.org; Mon, 07 Aug 2017 19:12:05 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:32966) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1derBn-0002e4-6d for qemu-arm@nongnu.org; Mon, 07 Aug 2017 19:12:04 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1derBi-0002zR-34 for qemu-arm@nongnu.org; Mon, 07 Aug 2017 19:11:59 -0400 Received: from mail-wr0-x241.google.com ([2a00:1450:400c:c0c::241]:38862) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1derBh-0002y9-SE; Mon, 07 Aug 2017 19:11:54 -0400 Received: by mail-wr0-x241.google.com with SMTP id g32so1262164wrd.5; Mon, 07 Aug 2017 16:11:51 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=mime-version:in-reply-to:references:from:date:message-id:subject:to :cc; bh=dfW3x2LbxjWtmPaAvRNvDNQzQkXnkpzc+CwRt6BGtQ4=; b=Vog0d8rHm/R4Z2P8PaqEUCNqlpFaYmCAaUxUVEvxT+/ZYkwSLbs3JthmFJv4WZS9TE hi54a74b/D7+D2aX+PKru8UaNiBiVG+bZHa6ZeMK6t4I7Yc8yNjaAztJIvxxWmPhwxa3 j1lzBoKcKLhYh6PUeR7CsNG73e+yhJQc1MeO6xicM8vCPUfu+/kpMXLHiYalNKADfB2+ mHMyUziCGHNHJmUAKX2NzAN1saySVKhRBMUsTuy+gOFPE6kug/8bZAl6/s7Z3tG54Nba 0HsvqE5huEq8ro/738F4/LiChiUMWaRtvr2RGlsLaHNCNq665lYHARUi8IwQC9AeKSkc dNrw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:in-reply-to:references:from:date :message-id:subject:to:cc; bh=dfW3x2LbxjWtmPaAvRNvDNQzQkXnkpzc+CwRt6BGtQ4=; b=j2hQxmIXAEHSkn2US2+Sg5n4NwP4CR34wc7E3VPRGHaorpqRz+9UZyCh+j74AwIJ4Q c5ehXqaqH+uQoYjtzI0NRmHWtPHDjBY8eJukEcQGtQG9XVPG4GrrXQf+FMuXLwM7u85B OEgAEvl7NkSUXwdJ3278hE6brQ0ZNJLC7OibAN1kGLnMWGI1KKn4HSeFquKFjfDAOqae w9Q0O48qd6Pfx6F7ZRwHlPhnrS8UbNBRwiD0sugH2NiG4yJnaf4WzDsgm8IJEjcDQSkD UPzjZuMwtmlDv3bU0/Oyx/NphVwO+bT9sCtdWDyNDscsEqiDb+pZljx0PgPpicYfZKyn pZiQ== X-Gm-Message-State: AHYfb5g4cauRcoz37u/WM2lshWtqUabqKnjkXycx9G/u9AprLlZe7Myo RRjsSPEbfi33lxfNgMnoi06e2EHU0w== X-Received: by 10.223.135.35 with SMTP id a32mr1460747wra.138.1502147510893; Mon, 07 Aug 2017 16:11:50 -0700 (PDT) MIME-Version: 1.0 Received: by 10.28.191.130 with HTTP; Mon, 7 Aug 2017 16:11:20 -0700 (PDT) In-Reply-To: <20170805005949.GY4859@toto> References: <1501867249-1924-1-git-send-email-peter.maydell@linaro.org> <1501867249-1924-2-git-send-email-peter.maydell@linaro.org> <20170805005949.GY4859@toto> From: Alistair Francis Date: Mon, 7 Aug 2017 16:11:20 -0700 Message-ID: To: "Edgar E. Iglesias" Cc: Peter Maydell , qemu-arm , "qemu-devel@nongnu.org Developers" , Patch Tracking , Richard Henderson Content-Type: text/plain; charset="UTF-8" X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:400c:c0c::241 Subject: Re: [Qemu-arm] [Qemu-devel] [PATCH 1/8] memory.h: Move MemTxResult type to memattrs.h X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 07 Aug 2017 23:12:04 -0000 On Fri, Aug 4, 2017 at 5:59 PM, Edgar E. Iglesias wrote: > On Fri, Aug 04, 2017 at 06:20:42PM +0100, Peter Maydell wrote: >> Move the MemTxResult type to memattrs.h. We're going to want to >> use it in cpu/qom.h, which doesn't want to include all of >> memory.h. In practice MemTxResult and MemTxAttrs are pretty >> closely linked since both are used for the new-style >> read_with_attrs and write_with_attrs callbacks, so memattrs.h >> is a reasonable home for this rather than creating a whole >> new header file for it. >> >> Signed-off-by: Peter Maydell > > Reviewed-by: Edgar E. Iglesias Reviewed-by: Alistair Francis Thanks, Alistair > > >> --- >> include/exec/memattrs.h | 10 ++++++++++ >> include/exec/memory.h | 10 ---------- >> 2 files changed, 10 insertions(+), 10 deletions(-) >> >> diff --git a/include/exec/memattrs.h b/include/exec/memattrs.h >> index e601061..d4a1642 100644 >> --- a/include/exec/memattrs.h >> +++ b/include/exec/memattrs.h >> @@ -46,4 +46,14 @@ typedef struct MemTxAttrs { >> */ >> #define MEMTXATTRS_UNSPECIFIED ((MemTxAttrs) { .unspecified = 1 }) >> >> +/* New-style MMIO accessors can indicate that the transaction failed. >> + * A zero (MEMTX_OK) response means success; anything else is a failure >> + * of some kind. The memory subsystem will bitwise-OR together results >> + * if it is synthesizing an operation from multiple smaller accesses. >> + */ >> +#define MEMTX_OK 0 >> +#define MEMTX_ERROR (1U << 0) /* device returned an error */ >> +#define MEMTX_DECODE_ERROR (1U << 1) /* nothing at that address */ >> +typedef uint32_t MemTxResult; >> + >> #endif >> diff --git a/include/exec/memory.h b/include/exec/memory.h >> index 400dd44..1dcd312 100644 >> --- a/include/exec/memory.h >> +++ b/include/exec/memory.h >> @@ -112,16 +112,6 @@ static inline void iommu_notifier_init(IOMMUNotifier *n, IOMMUNotify fn, >> n->end = end; >> } >> >> -/* New-style MMIO accessors can indicate that the transaction failed. >> - * A zero (MEMTX_OK) response means success; anything else is a failure >> - * of some kind. The memory subsystem will bitwise-OR together results >> - * if it is synthesizing an operation from multiple smaller accesses. >> - */ >> -#define MEMTX_OK 0 >> -#define MEMTX_ERROR (1U << 0) /* device returned an error */ >> -#define MEMTX_DECODE_ERROR (1U << 1) /* nothing at that address */ >> -typedef uint32_t MemTxResult; >> - >> /* >> * Memory region callbacks >> */ >> -- >> 2.7.4 >> >> > From MAILER-DAEMON Tue Aug 08 09:23:18 2017 Received: from list by lists.gnu.org with archive (Exim 4.71) id 1df4Te-00010c-Ox for mharc-qemu-arm@gnu.org; Tue, 08 Aug 2017 09:23:18 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:55107) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1df4TY-00010J-Uf for qemu-arm@nongnu.org; Tue, 08 Aug 2017 09:23:17 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1df4TU-0000Fz-4M for qemu-arm@nongnu.org; Tue, 08 Aug 2017 09:23:12 -0400 Received: from mx1.redhat.com ([209.132.183.28]:37026) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1df4TT-0000Ep-Lk; Tue, 08 Aug 2017 09:23:08 -0400 Received: from smtp.corp.redhat.com (int-mx02.intmail.prod.int.phx2.redhat.com [10.5.11.12]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id 3F476C057FA6; Tue, 8 Aug 2017 13:23:04 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mx1.redhat.com 3F476C057FA6 Authentication-Results: ext-mx08.extmail.prod.ext.phx2.redhat.com; dmarc=none (p=none dis=none) header.from=redhat.com Authentication-Results: ext-mx08.extmail.prod.ext.phx2.redhat.com; spf=fail smtp.mailfrom=drjones@redhat.com Received: from kamzik.brq.redhat.com (unknown [10.43.2.160]) by smtp.corp.redhat.com (Postfix) with ESMTPS id 07C6E95A6A; Tue, 8 Aug 2017 13:23:02 +0000 (UTC) Date: Tue, 8 Aug 2017 15:23:00 +0200 From: Andrew Jones To: qemu-devel@nongnu.org, qemu-arm@nongnu.org Cc: peter.maydell@linaro.org, agraf@suse.de, cdall@linaro.org Message-ID: <20170808132300.uyrrmgoij4qlwy52@kamzik.brq.redhat.com> References: <1500471597-2517-1-git-send-email-drjones@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1500471597-2517-1-git-send-email-drjones@redhat.com> User-Agent: Mutt/1.6.0.1 (2016-04-01) X-Scanned-By: MIMEDefang 2.79 on 10.5.11.12 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.32]); Tue, 08 Aug 2017 13:23:04 +0000 (UTC) X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.132.183.28 Subject: Re: [Qemu-arm] [Qemu-devel] [PATCH v2 0/4] ARM: KVM: Enable in-kernel PMU with user space gic X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 08 Aug 2017 13:23:17 -0000 Peter, ping? Thanks, drew On Wed, Jul 19, 2017 at 09:39:53AM -0400, Andrew Jones wrote: > v2: > - renamed the kvm pmu 'create' function to 'set_irq' after doing the > create/set-irq split > - added another patch that improves the error handling of the kvm pmu > init and set-irq calls > > Andrew Jones (4): > hw/arm/virt: add pmu interrupt state > target/arm/kvm: pmu: split init and set-irq stages > hw/arm/virt: allow pmu instantiation with userspace irqchip > target/arm/kvm: pmu: improve error handling > > hw/arm/virt.c | 12 ++++++++-- > target/arm/cpu.c | 2 ++ > target/arm/cpu.h | 2 ++ > target/arm/kvm.c | 6 ++++- > target/arm/kvm32.c | 7 +++++- > target/arm/kvm64.c | 63 ++++++++++++++++++++++++++++++---------------------- > target/arm/kvm_arm.h | 9 ++++---- > 7 files changed, 65 insertions(+), 36 deletions(-) > > -- > 1.8.3.1 > > From MAILER-DAEMON Tue Aug 08 10:09:47 2017 Received: from list by lists.gnu.org with archive (Exim 4.71) id 1df5Cd-0001fs-0M for mharc-qemu-arm@gnu.org; Tue, 08 Aug 2017 10:09:47 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:58746) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dezj0-0008Ph-Pa for qemu-arm@nongnu.org; Tue, 08 Aug 2017 04:18:52 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1deziz-0003DU-Iv for qemu-arm@nongnu.org; Tue, 08 Aug 2017 04:18:50 -0400 Received: from mail-yw0-x241.google.com ([2607:f8b0:4002:c05::241]:33914) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1deziz-0003Ct-Dr; Tue, 08 Aug 2017 04:18:49 -0400 Received: by mail-yw0-x241.google.com with SMTP id t139so1896968ywg.1; Tue, 08 Aug 2017 01:18:49 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=mime-version:in-reply-to:references:from:date:message-id:subject:to :cc; bh=lQt5pVMCUzGsSM2qvKfKeUJ5zvDnDWsRIMlNlidPyqw=; b=hlhTagLtkHS4Nc59S2nZhyc8kMhp3kW2PWjF33+/PaSRCnsEQ/kQ9Rf00NX5HmMXmo Nyq6y9E66KmeF3aEGMBpTyctbcDla7egQjQ9VUWmpWihnmvXxD7A0JiaBMZ9b4iTMbk4 tvGsY5THX2zd/YbeuI4dViG+gjcVSeTBftZAI+UJMAseqZ7zAiAGRBPPekjGPkQmz6oF XboomWR2FtX1Ko7fKh4+AqCEUKRC7UUU98OIyiemgQIsfQFCyKg0cqVpYDRRnx7IRiSh /acehTX08yIMdYnhN+9/zRln3pExR926Ts+r98eQ+cTTwKn6xJtQimf4OTkrD96q8LTA hhVA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:in-reply-to:references:from:date :message-id:subject:to:cc; bh=lQt5pVMCUzGsSM2qvKfKeUJ5zvDnDWsRIMlNlidPyqw=; b=SCQ2rH+9qr/C6b7KUXn593hQODaNAjLjDU0KMXOCcaaVNyLol7Tkcb4J1Uo4GNdEEC iK4KIxZ4+idsHu1hz4JbZ2zy/o/mcz4jONJn/kXhUq6FbFs8iXA6pN6KWEYKdAFmDk/m HRxbloLS4o6vlwOkkqo00l6HnUZbFZF1MfqZPmGZSwUdAXkW+Jd9LsRRdC6dEkTscQCJ EtaiOVj51TeUXqd911dD1iRQiM6zIjEVxjenOT59HgUmsxDfpMGJ2/nK0/jzVjCk04Nj SYEYjrYD3A2qfGiaai8vEzsOagLeNoix3oRJ4iCxUIWh/e8c3JtSEOIMILc0uN0VuhSp q5TA== X-Gm-Message-State: AHYfb5j7ssBSizMNnysG/SW8OKNvsY/w/WRNknbgkZvZCJyOh4Ac7rpy 29fE8pwRQWc0BDhRusNwa2A769Hleg== X-Received: by 10.129.74.7 with SMTP id x7mr2627395ywa.193.1502180328551; Tue, 08 Aug 2017 01:18:48 -0700 (PDT) MIME-Version: 1.0 Received: by 10.13.229.130 with HTTP; Tue, 8 Aug 2017 01:18:47 -0700 (PDT) In-Reply-To: <1502116754-18867-3-git-send-email-peter.maydell@linaro.org> References: <1502116754-18867-1-git-send-email-peter.maydell@linaro.org> <1502116754-18867-3-git-send-email-peter.maydell@linaro.org> From: Hua Yanghao Date: Tue, 8 Aug 2017 10:18:47 +0200 Message-ID: To: Peter Maydell Cc: qemu-arm@nongnu.org, QEMU Developers , patches@linaro.org, Richard Henderson Content-Type: text/plain; charset="UTF-8" X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4002:c05::241 X-Mailman-Approved-At: Tue, 08 Aug 2017 10:09:45 -0400 Subject: Re: [Qemu-arm] [PATCH 2/2] loader: Ignore zero-sized ELF segments X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 08 Aug 2017 08:18:52 -0000 Tested-by: Hua Yanghao On Mon, Aug 7, 2017 at 4:39 PM, Peter Maydell wrote: > Some ELF files have program headers that specify segments that > are of zero size. Ignore them, rather than trying to create > zero-length ROM blobs for them, because the zero-length blob > can falsely trigger the overlapping-ROM-blobs check. > > Signed-off-by: Peter Maydell > --- > include/hw/elf_ops.h | 24 +++++++++++++++++------- > 1 file changed, 17 insertions(+), 7 deletions(-) > > diff --git a/include/hw/elf_ops.h b/include/hw/elf_ops.h > index 2e526d3..d192e7e 100644 > --- a/include/hw/elf_ops.h > +++ b/include/hw/elf_ops.h > @@ -451,14 +451,24 @@ static int glue(load_elf, SZ)(const char *name, int fd, > *pentry = ehdr.e_entry - ph->p_vaddr + ph->p_paddr; > } > > - if (load_rom) { > - snprintf(label, sizeof(label), "phdr #%d: %s", i, name); > - > - /* rom_add_elf_program() seize the ownership of 'data' */ > - rom_add_elf_program(label, data, file_size, mem_size, addr, as); > - } else { > - cpu_physical_memory_write(addr, data, file_size); > + if (mem_size == 0) { > + /* Some ELF files really do have segments of zero size; > + * just ignore them rather than trying to create empty > + * ROM blobs, because the zero-length blob can falsely > + * trigger the overlapping-ROM-blobs check. > + */ > g_free(data); > + } else { > + if (load_rom) { > + snprintf(label, sizeof(label), "phdr #%d: %s", i, name); > + > + /* rom_add_elf_program() seize the ownership of 'data' */ > + rom_add_elf_program(label, data, file_size, mem_size, > + addr, as); > + } else { > + cpu_physical_memory_write(addr, data, file_size); > + g_free(data); > + } > } > > total_size += mem_size; > -- > 2.7.4 > From MAILER-DAEMON Wed Aug 09 02:29:14 2017 Received: from list by lists.gnu.org with archive (Exim 4.71) id 1dfKUU-00063R-7i for mharc-qemu-arm@gnu.org; Wed, 09 Aug 2017 02:29:14 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:37009) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dfKUR-000630-N6 for qemu-arm@nongnu.org; Wed, 09 Aug 2017 02:29:13 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dfKUO-00070u-Jd for qemu-arm@nongnu.org; Wed, 09 Aug 2017 02:29:11 -0400 Received: from out1-smtp.messagingengine.com ([66.111.4.25]:46559) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1dfKUO-0006yy-6P; Wed, 09 Aug 2017 02:29:08 -0400 Received: from compute4.internal (compute4.nyi.internal [10.202.2.44]) by mailout.nyi.internal (Postfix) with ESMTP id 593A421D8A; Wed, 9 Aug 2017 02:29:04 -0400 (EDT) Received: from frontend1 ([10.202.2.160]) by compute4.internal (MEProxy); Wed, 09 Aug 2017 02:29:04 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=aj.id.au; h=cc :date:from:message-id:subject:to:x-me-sender:x-me-sender :x-sasl-enc:x-sasl-enc; s=fm1; bh=nzpy4AFz5RRQ/dXQA1fozxAB2mDJVh hr2zzPzm7M/Xo=; b=MPHAu8dsYvjRXQ4uGHBbGcUMgqw17THOSP14TI9vt71/yP bjZq/eA7WLNNvRq2lk3t5pf32bDnJrsL+U9IYGkX4GfYEENM1AGEtiwSxj5YZOEy bvXZMAHkuzcURaxaDx7FBfVU5oK3haP7e3r7hQ6JOY8X+8KWcFAGP7dm8F5adxZE 43hBxM0msoOR3u+DGt0YAJNJViSk6eOUyo8XYxwv/plrVhi+bhoXY8BFVti/99bL LCQL+wJhiWnICjrWhHqorih4PCJlRvIAbRxwSX8M1Sh7KKo/XgbkMn1FdPNueorh t4+o3+rZyOw1T3l6DMRYZxWVdsg0ZDim4CMFf7fg== DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d= messagingengine.com; h=cc:date:from:message-id:subject:to :x-me-sender:x-me-sender:x-sasl-enc:x-sasl-enc; s=fm1; bh=nzpy4A Fz5RRQ/dXQA1fozxAB2mDJVhhr2zzPzm7M/Xo=; b=MZrnyTxCMDs42zcBST8aUr dxu0DhXV7oHZQc5wctzS5F+frdfLDDsnVgK47Oshe+em1zNVNu52RohmlUDxLGI7 dZXdgiY6p8jDzcHYI0bUuSwrMffZ6s8t1hpTikwar0oRnus7r2WgaC+WX8/HZlLU YeV0K7TIWeKtyuDPJbIug2f1/cM0O+hEI185e8z9tfCpgYU8i0FGyH7rfmwYWeBc rIOj2ZsUry9QX+Ka5xr1UM9QJgV0xCeUawYb8Dtf3Tu6Ex/WFp5l2iZKVt7PJ0+l KrGXhMmfmWxxEFnmLURMyPmLoSaWjyZ4++Yacobev1Q1IFx21uzTSyafLrg1BDgA == X-ME-Sender: X-Sasl-enc: AkqOGMNDlu4TbWKUtakKVm0+GpfI7Nzz9d0jmpw2a3VG 1502260143 Received: from keelia.au.ibm.com (unknown [203.0.153.9]) by mail.messagingengine.com (Postfix) with ESMTPA id 7A0DB7E73B; Wed, 9 Aug 2017 02:29:00 -0400 (EDT) From: Andrew Jeffery To: qemu-arm@nongnu.org Cc: Andrew Jeffery , qemu-devel@nongnu.org, clg@kaod.org, peter.maydell@linaro.org, joel@jms.id.au, f4bug@amsat.org, ryan_chen@aspeedtech.com, openbmc@lists.ozlabs.org Date: Wed, 9 Aug 2017 15:58:25 +0930 Message-Id: <20170809062828.3673-1-andrew@aj.id.au> X-Mailer: git-send-email 2.11.0 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 66.111.4.25 Subject: [Qemu-arm] [PATCH for 2.11 v2 0/2] wdt_aspeed: Support reset width patterns X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 09 Aug 2017 06:29:13 -0000 Hello, These two patches add support for the reset width configuration register in the Aspeed watchdog. Initially this was just one patch[1], but I've reworked it as two to explicitly support the varying capabilities between Aspeed SoC versions. Andrew [1] http://patchwork.ozlabs.org/patch/796039/ Andrew Jeffery (2): watchdog: wdt_aspeed: Add support for the reset width register aspeed_soc: Propagate silicon-rev to watchdog hw/arm/aspeed_soc.c | 2 + hw/watchdog/wdt_aspeed.c | 93 +++++++++++++++++++++++++++++++++++----- include/hw/watchdog/wdt_aspeed.h | 2 + 3 files changed, 86 insertions(+), 11 deletions(-) -- 2.11.0 From MAILER-DAEMON Wed Aug 09 02:29:14 2017 Received: from list by lists.gnu.org with archive (Exim 4.71) id 1dfKUU-00063x-QX for mharc-qemu-arm@gnu.org; Wed, 09 Aug 2017 02:29:14 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:37010) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dfKUR-000631-N5 for qemu-arm@nongnu.org; Wed, 09 Aug 2017 02:29:13 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dfKUO-00071P-KZ for qemu-arm@nongnu.org; Wed, 09 Aug 2017 02:29:11 -0400 Received: from out1-smtp.messagingengine.com ([66.111.4.25]:46323) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1dfKUO-00070a-FG; Wed, 09 Aug 2017 02:29:08 -0400 Received: from compute4.internal (compute4.nyi.internal [10.202.2.44]) by mailout.nyi.internal (Postfix) with ESMTP id 2DBA921D8E; Wed, 9 Aug 2017 02:29:08 -0400 (EDT) Received: from frontend1 ([10.202.2.160]) by compute4.internal (MEProxy); Wed, 09 Aug 2017 02:29:08 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=aj.id.au; h=cc :date:from:in-reply-to:message-id:references:subject:to :x-me-sender:x-me-sender:x-sasl-enc:x-sasl-enc; s=fm1; bh=GNDR9v AWMtBkJSHNWfHfTP0dAWDNQ4A24GlGMzS/HTE=; b=Jm6SYB99QtOLhJTExMaFwj YT+KsU5B9Rj+ZLf8lVrDvAPF59UNM4SnXYc2Fu60C2sohnT39D3iz7HiKWUVBnuZ mpSP6uIGquIyNrWxpLdDI0uUTQvFisWhCJJGLoIwImGHuF1UjB62BAzAmsGhTF1g Fth5MzzEVZUk3LecahNW2goX7kwvnLg7FK/EdGyJ0fR8SQ2Za7fQASp3TcjuFxYt W/PGR8ThnkGelYxXaerc9Hs6G4mFMr30xVRAinEzLBwhTWgvkzVxNvtj+EomkqLv nb2llqBEhiqRW+SdA88c0GsD8E0kmPPcQG+dLgn4z0OfwusEIuMMSJ6DCEcIRcAQ == DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d= messagingengine.com; h=cc:date:from:in-reply-to:message-id :references:subject:to:x-me-sender:x-me-sender:x-sasl-enc :x-sasl-enc; s=fm1; bh=GNDR9vAWMtBkJSHNWfHfTP0dAWDNQ4A24GlGMzS/H TE=; b=dqGLmE/3WW2auXadagzWBkO+erkgutMijd9/oxliUv/kcURIggiTefLXJ Xg9cOcJFCx8Iz7lGyEvvKeVC0vsmK+kQ7eAdD6Op8G+hL+LaaXAFekJuMmGQN/3+ UiinTm4nMfkKatxBxSkBtEaiEIZsttxm/d3/lwGnAyDAMQGxxqSLjkaUCGWOuu6p kzBQjG003H/8nwsFOrAf3RZMjt74EQ+b54azneAfjTheZhWNEyq874v18Ocv8mlr qYtxdJlDegN7W1jBE4mbU9zFlC9MQ2qasHEnIhJz9TA13I/RMJ8t4hz+2vtnPswl h+cyc95W8e/jn8ivKMkm61s805WdQ== X-ME-Sender: X-Sasl-enc: ZU1C114svhnd1gywXlZDwGaDCqnAj4irrggN3aF2tm9D 1502260147 Received: from keelia.au.ibm.com (unknown [203.0.153.9]) by mail.messagingengine.com (Postfix) with ESMTPA id BE5147E4EA; Wed, 9 Aug 2017 02:29:04 -0400 (EDT) From: Andrew Jeffery To: qemu-arm@nongnu.org Cc: Andrew Jeffery , qemu-devel@nongnu.org, clg@kaod.org, peter.maydell@linaro.org, joel@jms.id.au, f4bug@amsat.org, ryan_chen@aspeedtech.com, openbmc@lists.ozlabs.org Date: Wed, 9 Aug 2017 15:58:26 +0930 Message-Id: <20170809062828.3673-2-andrew@aj.id.au> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20170809062828.3673-1-andrew@aj.id.au> References: <20170809062828.3673-1-andrew@aj.id.au> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 66.111.4.25 Subject: [Qemu-arm] [PATCH for 2.11 v2 1/2] watchdog: wdt_aspeed: Add support for the reset width register X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 09 Aug 2017 06:29:13 -0000 The reset width register controls how the pulse on the SoC's WDTRST{1,2} pins behaves. A pulse is emitted if the external reset bit is set in WDT_CTRL. On the AST2500 WDT_RESET_WIDTH can consume magic bit patterns to configure push-pull/open-drain and active-high/active-low behaviours and thus needs some special handling in the write path. As some of the capabilities depend on the SoC version a silicon-rev property is introduced, which is used to guard version-specific behaviour. Signed-off-by: Andrew Jeffery --- hw/watchdog/wdt_aspeed.c | 93 +++++++++++++++++++++++++++++++++++----- include/hw/watchdog/wdt_aspeed.h | 2 + 2 files changed, 84 insertions(+), 11 deletions(-) diff --git a/hw/watchdog/wdt_aspeed.c b/hw/watchdog/wdt_aspeed.c index 8bbe579b6b66..22bce364d7b5 100644 --- a/hw/watchdog/wdt_aspeed.c +++ b/hw/watchdog/wdt_aspeed.c @@ -8,16 +8,19 @@ */ #include "qemu/osdep.h" + +#include "qapi/error.h" #include "qemu/log.h" +#include "qemu/timer.h" #include "sysemu/watchdog.h" +#include "hw/misc/aspeed_scu.h" #include "hw/sysbus.h" -#include "qemu/timer.h" #include "hw/watchdog/wdt_aspeed.h" -#define WDT_STATUS (0x00 / 4) -#define WDT_RELOAD_VALUE (0x04 / 4) -#define WDT_RESTART (0x08 / 4) -#define WDT_CTRL (0x0C / 4) +#define WDT_STATUS (0x00 / 4) +#define WDT_RELOAD_VALUE (0x04 / 4) +#define WDT_RESTART (0x08 / 4) +#define WDT_CTRL (0x0C / 4) #define WDT_CTRL_RESET_MODE_SOC (0x00 << 5) #define WDT_CTRL_RESET_MODE_FULL_CHIP (0x01 << 5) #define WDT_CTRL_1MHZ_CLK BIT(4) @@ -25,18 +28,41 @@ #define WDT_CTRL_WDT_INTR BIT(2) #define WDT_CTRL_RESET_SYSTEM BIT(1) #define WDT_CTRL_ENABLE BIT(0) +#define WDT_RESET_WIDTH (0x18 / 4) +#define WDT_RESET_WIDTH_ACTIVE_HIGH BIT(31) +#define WDT_POLARITY_MASK (0xFF << 24) +#define WDT_ACTIVE_HIGH_MAGIC (0xA5 << 24) +#define WDT_ACTIVE_LOW_MAGIC (0x5A << 24) +#define WDT_RESET_WIDTH_PUSH_PULL BIT(30) +#define WDT_DRIVE_TYPE_MASK (0xFF << 24) +#define WDT_PUSH_PULL_MAGIC (0xA8 << 24) +#define WDT_OPEN_DRAIN_MAGIC (0x8A << 24) -#define WDT_TIMEOUT_STATUS (0x10 / 4) -#define WDT_TIMEOUT_CLEAR (0x14 / 4) -#define WDT_RESET_WDITH (0x18 / 4) +#define WDT_TIMEOUT_STATUS (0x10 / 4) +#define WDT_TIMEOUT_CLEAR (0x14 / 4) -#define WDT_RESTART_MAGIC 0x4755 +#define WDT_RESTART_MAGIC 0x4755 static bool aspeed_wdt_is_enabled(const AspeedWDTState *s) { return s->regs[WDT_CTRL] & WDT_CTRL_ENABLE; } +static bool is_ast2500(const AspeedWDTState *s) +{ + switch (s->silicon_rev) { + case AST2500_A0_SILICON_REV: + case AST2500_A1_SILICON_REV: + return true; + case AST2400_A0_SILICON_REV: + case AST2400_A1_SILICON_REV: + default: + break; + } + + return false; +} + static uint64_t aspeed_wdt_read(void *opaque, hwaddr offset, unsigned size) { AspeedWDTState *s = ASPEED_WDT(opaque); @@ -55,9 +81,10 @@ static uint64_t aspeed_wdt_read(void *opaque, hwaddr offset, unsigned size) return 0; case WDT_CTRL: return s->regs[WDT_CTRL]; + case WDT_RESET_WIDTH: + return s->regs[WDT_RESET_WIDTH]; case WDT_TIMEOUT_STATUS: case WDT_TIMEOUT_CLEAR: - case WDT_RESET_WDITH: qemu_log_mask(LOG_UNIMP, "%s: uninmplemented read at offset 0x%" HWADDR_PRIx "\n", __func__, offset); @@ -119,9 +146,27 @@ static void aspeed_wdt_write(void *opaque, hwaddr offset, uint64_t data, timer_del(s->timer); } break; + case WDT_RESET_WIDTH: + { + uint32_t property = data & WDT_POLARITY_MASK; + + if (property && is_ast2500(s)) { + if (property == WDT_ACTIVE_HIGH_MAGIC) { + s->regs[WDT_RESET_WIDTH] |= WDT_RESET_WIDTH_ACTIVE_HIGH; + } else if (property == WDT_ACTIVE_LOW_MAGIC) { + s->regs[WDT_RESET_WIDTH] &= ~WDT_RESET_WIDTH_ACTIVE_HIGH; + } else if (property == WDT_PUSH_PULL_MAGIC) { + s->regs[WDT_RESET_WIDTH] |= WDT_RESET_WIDTH_PUSH_PULL; + } else if (property == WDT_OPEN_DRAIN_MAGIC) { + s->regs[WDT_RESET_WIDTH] &= ~WDT_RESET_WIDTH_PUSH_PULL; + } + } + s->regs[WDT_RESET_WIDTH] &= ~s->ext_pulse_width_mask; + s->regs[WDT_RESET_WIDTH] |= data & s->ext_pulse_width_mask; + break; + } case WDT_TIMEOUT_STATUS: case WDT_TIMEOUT_CLEAR: - case WDT_RESET_WDITH: qemu_log_mask(LOG_UNIMP, "%s: uninmplemented write at offset 0x%" HWADDR_PRIx "\n", __func__, offset); @@ -167,6 +212,7 @@ static void aspeed_wdt_reset(DeviceState *dev) s->regs[WDT_RELOAD_VALUE] = 0x03EF1480; s->regs[WDT_RESTART] = 0; s->regs[WDT_CTRL] = 0; + s->regs[WDT_RESET_WIDTH] = 0xFF; timer_del(s->timer); } @@ -187,6 +233,25 @@ static void aspeed_wdt_realize(DeviceState *dev, Error **errp) SysBusDevice *sbd = SYS_BUS_DEVICE(dev); AspeedWDTState *s = ASPEED_WDT(dev); + if (!is_supported_silicon_rev(s->silicon_rev)) { + error_setg(errp, "Unknown silicon revision: 0x%" PRIx32, + s->silicon_rev); + return; + } + + switch (s->silicon_rev) { + case AST2400_A0_SILICON_REV: + case AST2400_A1_SILICON_REV: + s->ext_pulse_width_mask = 0xff; + break; + case AST2500_A0_SILICON_REV: + case AST2500_A1_SILICON_REV: + s->ext_pulse_width_mask = 0xfffff; + break; + default: + g_assert_not_reached(); + } + s->timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, aspeed_wdt_timer_expired, dev); /* FIXME: This setting should be derived from the SCU hw strapping @@ -199,6 +264,11 @@ static void aspeed_wdt_realize(DeviceState *dev, Error **errp) sysbus_init_mmio(sbd, &s->iomem); } +static Property aspeed_wdt_properties[] = { + DEFINE_PROP_UINT32("silicon-rev", AspeedWDTState, silicon_rev, 0), + DEFINE_PROP_END_OF_LIST(), +}; + static void aspeed_wdt_class_init(ObjectClass *klass, void *data) { DeviceClass *dc = DEVICE_CLASS(klass); @@ -207,6 +277,7 @@ static void aspeed_wdt_class_init(ObjectClass *klass, void *data) dc->reset = aspeed_wdt_reset; set_bit(DEVICE_CATEGORY_MISC, dc->categories); dc->vmsd = &vmstate_aspeed_wdt; + dc->props = aspeed_wdt_properties; } static const TypeInfo aspeed_wdt_info = { diff --git a/include/hw/watchdog/wdt_aspeed.h b/include/hw/watchdog/wdt_aspeed.h index 080c2231222e..7de3e5c224fb 100644 --- a/include/hw/watchdog/wdt_aspeed.h +++ b/include/hw/watchdog/wdt_aspeed.h @@ -27,6 +27,8 @@ typedef struct AspeedWDTState { uint32_t regs[ASPEED_WDT_REGS_MAX]; uint32_t pclk_freq; + uint32_t silicon_rev; + uint32_t ext_pulse_width_mask; } AspeedWDTState; #endif /* ASPEED_WDT_H */ -- 2.11.0 From MAILER-DAEMON Wed Aug 09 02:29:16 2017 Received: from list by lists.gnu.org with archive (Exim 4.71) id 1dfKUV-00064r-UC for mharc-qemu-arm@gnu.org; Wed, 09 Aug 2017 02:29:15 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:37040) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dfKUT-00063B-Hf for qemu-arm@nongnu.org; Wed, 09 Aug 2017 02:29:15 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dfKUS-00074h-H8 for qemu-arm@nongnu.org; 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a=rsa-sha256; c=relaxed/relaxed; d= messagingengine.com; h=cc:date:from:in-reply-to:message-id :references:subject:to:x-me-sender:x-me-sender:x-sasl-enc :x-sasl-enc; s=fm1; bh=uzkJPqWJqx0LJSLGO2T7w8trESySPWwGjTeWE+nE2 Eg=; b=iJsVEs2rNkve9hzB53n83/540vLaOjuIIUJpievNU+ogWoVFnz2nrcZb6 pLSrhkKTgwt1ninRqinv/EocardHS9JkXyTkXoqlJQzZw1eZc2/D5RnYzcd6ngvv xwg7Yh/H21ZSDg1h7T2ksNLKOzTUJerkSsD8o32/Z0Mvo63dwJua1ZPkntnzsiIV WJPojo3cfjuQgE+bm5yWWLtohFfdbZqM1AyzpFQ7nSCk6OOIsdq5UbE3uaFz6dt4 ZTiND/XpehKk+/cqIWyuKYZjYR6TS0JPp/ptRTTRnEG+puPf2cT/sD/O6Xrch/Rl sWoS/68Tu/Z27DBm8/RfUwZ/F3e6A== X-ME-Sender: X-Sasl-enc: tTMzAZynhKDKbaPvkMIe+Qk0KQeNohPjhIulxVqiyMr+ 1502260150 Received: from keelia.au.ibm.com (unknown [203.0.153.9]) by mail.messagingengine.com (Postfix) with ESMTPA id 7A4BF7E4EA; Wed, 9 Aug 2017 02:29:08 -0400 (EDT) From: Andrew Jeffery To: qemu-arm@nongnu.org Cc: Andrew Jeffery , qemu-devel@nongnu.org, clg@kaod.org, peter.maydell@linaro.org, joel@jms.id.au, ryan_chen@aspeedtech.com, f4bug@amsat.org, openbmc@lists.ozlabs.org Date: Wed, 9 Aug 2017 15:58:27 +0930 Message-Id: <20170809062828.3673-3-andrew@aj.id.au> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20170809062828.3673-1-andrew@aj.id.au> References: <20170809062828.3673-1-andrew@aj.id.au> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 66.111.4.25 Subject: [Qemu-arm] [PATCH for 2.11 v2 2/2] ARM: aspeed_soc: Propagate silicon-rev to watchdog X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 09 Aug 2017 06:29:15 -0000 This is required to configure differences in behaviour between the AST2400 and AST2500 watchdog IPs. Signed-off-by: Andrew Jeffery --- hw/arm/aspeed_soc.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/hw/arm/aspeed_soc.c b/hw/arm/aspeed_soc.c index 3034849c80bf..79804e1ee652 100644 --- a/hw/arm/aspeed_soc.c +++ b/hw/arm/aspeed_soc.c @@ -183,6 +183,8 @@ static void aspeed_soc_init(Object *obj) object_initialize(&s->wdt[i], sizeof(s->wdt[i]), TYPE_ASPEED_WDT); object_property_add_child(obj, "wdt[*]", OBJECT(&s->wdt[i]), NULL); qdev_set_parent_bus(DEVICE(&s->wdt[i]), sysbus_get_default()); + qdev_prop_set_uint32(DEVICE(&s->wdt[i]), "silicon-rev", + sc->info->silicon_rev); } object_initialize(&s->ftgmac100, sizeof(s->ftgmac100), TYPE_FTGMAC100); -- 2.11.0 From MAILER-DAEMON Wed Aug 09 02:29:22 2017 Received: from list by lists.gnu.org with archive (Exim 4.71) id 1dfKUc-0006As-Jp for mharc-qemu-arm@gnu.org; Wed, 09 Aug 2017 02:29:22 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:37103) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dfKUX-00066d-LS for qemu-arm@nongnu.org; Wed, 09 Aug 2017 02:29:20 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dfKUW-00078k-Ke for qemu-arm@nongnu.org; Wed, 09 Aug 2017 02:29:17 -0400 Received: from out1-smtp.messagingengine.com ([66.111.4.25]:37551) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1dfKUW-00078O-Hi; Wed, 09 Aug 2017 02:29:16 -0400 Received: from compute4.internal (compute4.nyi.internal [10.202.2.44]) by mailout.nyi.internal (Postfix) with ESMTP id 33E8021D94; Wed, 9 Aug 2017 02:29:16 -0400 (EDT) Received: from frontend1 ([10.202.2.160]) by compute4.internal (MEProxy); Wed, 09 Aug 2017 02:29:16 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=aj.id.au; h=cc :date:from:in-reply-to:message-id:references:subject:to :x-me-sender:x-me-sender:x-sasl-enc:x-sasl-enc; s=fm1; bh=uzkJPq WJqx0LJSLGO2T7w8trESySPWwGjTeWE+nE2Eg=; b=Xb6mpwXIPKUtOUan33+fYL L/SDOpXbz/zkzMyv5CW17cRox7fvXWCGgw54ZF9BYcwiZmq+VVhp7Y0sK901pUDq DjNZfccf0n8N+EyR0rP1QxDd/B+iXd3DKpIbHSOQxWCK5EqtuIhLB9xbmRDE2fzz FI+s75/vFu0TH30ruJWXQcR8WKwH3Dl9KnWtxj+WcrS2qm72c1NxB9hm94F1TK2l vp6yJVYzyhUEYd+yyBAjtQNKUXhv6/LwO4pRLVrLUJm8vmXPDPcSJSglIqjSy74G aAp5QNmwsWC1QXKYhI+iZuG/yJHIryVRYjSeg8YC0F2RKAXe62sOYKX7PAgBGuLA == DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d= messagingengine.com; h=cc:date:from:in-reply-to:message-id :references:subject:to:x-me-sender:x-me-sender:x-sasl-enc :x-sasl-enc; s=fm1; bh=uzkJPqWJqx0LJSLGO2T7w8trESySPWwGjTeWE+nE2 Eg=; b=o+NmTluxJduFUK2GS50lpjwEg3qbwsvUd2YUCfeBFK49wZjo3kgmY0M6e y/zQocURtsJVYiDV/D1TbOiRGAhcQvOi6NXP72dXckEgxHyEsf/F3pSxk31PzLtp dJf681C8GrmVj7WqMh4vMOZpTYVpA7WcGWRKXWB1yZxvYuVPdGkL6N28zB2Vwfd4 cNnfhZfbqH1BoybIphGp/qoGFxZdd4WR5nkqf6vwEUAryeO35hvAvxjp9WtMMERs SD0w9Af4f6Z9bDk7CMbzICWJLjYEkhVssCIxmXBeBolYdGyD4hoKicgx2YugzPhu +9HQYBPB2Kv9ewIKN3pzGTkxtbUTQ== X-ME-Sender: X-Sasl-enc: RVCtiwK1GOosjdI/Fu7vDvXKZ2dhAy+/pq7OHJNhdLpb 1502260155 Received: from keelia.au.ibm.com (unknown [203.0.153.9]) by mail.messagingengine.com (Postfix) with ESMTPA id 87B997E4EA; Wed, 9 Aug 2017 02:29:12 -0400 (EDT) From: Andrew Jeffery To: qemu-arm@nongnu.org Cc: Andrew Jeffery , qemu-devel@nongnu.org, clg@kaod.org, peter.maydell@linaro.org, joel@jms.id.au, f4bug@amsat.org, ryan_chen@aspeedtech.com, openbmc@lists.ozlabs.org Date: Wed, 9 Aug 2017 15:58:28 +0930 Message-Id: <20170809062828.3673-4-andrew@aj.id.au> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20170809062828.3673-1-andrew@aj.id.au> References: <20170809062828.3673-1-andrew@aj.id.au> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 66.111.4.25 Subject: [Qemu-arm] [PATCH for 2.11 v2 2/2] aspeed_soc: Propagate silicon-rev to watchdog X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 09 Aug 2017 06:29:20 -0000 This is required to configure differences in behaviour between the AST2400 and AST2500 watchdog IPs. Signed-off-by: Andrew Jeffery --- hw/arm/aspeed_soc.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/hw/arm/aspeed_soc.c b/hw/arm/aspeed_soc.c index 3034849c80bf..79804e1ee652 100644 --- a/hw/arm/aspeed_soc.c +++ b/hw/arm/aspeed_soc.c @@ -183,6 +183,8 @@ static void aspeed_soc_init(Object *obj) object_initialize(&s->wdt[i], sizeof(s->wdt[i]), TYPE_ASPEED_WDT); object_property_add_child(obj, "wdt[*]", OBJECT(&s->wdt[i]), NULL); qdev_set_parent_bus(DEVICE(&s->wdt[i]), sysbus_get_default()); + qdev_prop_set_uint32(DEVICE(&s->wdt[i]), "silicon-rev", + sc->info->silicon_rev); } object_initialize(&s->ftgmac100, sizeof(s->ftgmac100), TYPE_FTGMAC100); -- 2.11.0 From MAILER-DAEMON Wed Aug 09 02:39:16 2017 Received: from list by lists.gnu.org with archive (Exim 4.71) id 1dfKeC-0001PH-1I for mharc-qemu-arm@gnu.org; Wed, 09 Aug 2017 02:39:16 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:39347) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dfKe9-0001P9-Cw for qemu-arm@nongnu.org; Wed, 09 Aug 2017 02:39:14 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dfKe6-0005RQ-7l for qemu-arm@nongnu.org; Wed, 09 Aug 2017 02:39:13 -0400 Received: from out1-smtp.messagingengine.com ([66.111.4.25]:55525) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1dfKe6-0005RA-2l; Wed, 09 Aug 2017 02:39:10 -0400 Received: from compute4.internal (compute4.nyi.internal [10.202.2.44]) by mailout.nyi.internal (Postfix) with ESMTP id 9243821C22; Wed, 9 Aug 2017 02:39:07 -0400 (EDT) Received: from frontend2 ([10.202.2.161]) by compute4.internal (MEProxy); Wed, 09 Aug 2017 02:39:07 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=aj.id.au; h=cc :content-type:date:from:in-reply-to:message-id:mime-version :references:subject:to:x-me-sender:x-me-sender:x-sasl-enc :x-sasl-enc; s=fm1; bh=fccj3QHexLSa662Fsy3J4criB8vmHNmfWeTGXmsmF hU=; b=AA4XBctT20L+J7MmoIyjMo3iMARE6zZkJ113gG94Gsle2gzinNOonl4P7 NISSWN1kwxrKt8nb2y/cWDKtx10Wei5tdgiwy4gDmgVdrXTHPf5y/9EA0CDFIu5q f3zxZ6/w/kxV4KHQ1DddNaw7mMUei8oQSvHUwRPC0jabLLAjOuaCbNnBZctltg7e hgWGCotadWAQk8jUI9s/hF8USN1omhd1NFZFJ8+uGPhZQEps4sSb3sXnYcsXIy1F 3R0bOSxRQsY4zKNJZKVsp6fjZdlnVFXs3NEdRv8BtgYuUsczdrrh5iBiHNpcSvTG LK0J7h46lF7v7p4a/HQtZPoshOUYA== DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d= messagingengine.com; h=cc:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to:x-me-sender :x-me-sender:x-sasl-enc:x-sasl-enc; s=fm1; bh=fccj3QHexLSa662Fsy 3J4criB8vmHNmfWeTGXmsmFhU=; b=p6pixRA7RYckcm4bK40ivKtkCo9FlNpSO2 OsHw7rI93X+HTAxQ5ohmvXB6PArroOBiGVfSPkUoEk+FqlSsxS9FSfMx9S4aNyY/ 5IwaVTV7sa0mHIx5gNwVjQYdE5tPzB1+VRqinfxgQ5L5KmBuzvMmEO8/ggrTo50C ZRok3yjKh6fPfXCELYP5dDoCX9S4rrC8mkpREdLQmwj6kXMkrz5YOxwhTIr6nSqJ kqEFbwtZY2a8w7BWhe9QNz5d2LNj2YY3+yJnnM+reEF7VnYsomF4qGEbB1T+xQBh CHuYqIRAXRGrLGVe/7Vl6F/+VIKgylUjdp2wfdTlyU+hUoLY1PKw== X-ME-Sender: X-Sasl-enc: qcrieKU9CsN922CVtMCUS8AHGh1Cim7WQEBZT7uUgiv3 1502260746 Received: from keelia (unknown [203.0.153.9]) by mail.messagingengine.com (Postfix) with ESMTPA id 43E81244B4; Wed, 9 Aug 2017 02:39:03 -0400 (EDT) Message-ID: <1502260737.7946.8.camel@aj.id.au> From: Andrew Jeffery To: qemu-arm@nongnu.org Cc: qemu-devel@nongnu.org, clg@kaod.org, peter.maydell@linaro.org, joel@jms.id.au, ryan_chen@aspeedtech.com, f4bug@amsat.org, openbmc@lists.ozlabs.org Date: Wed, 09 Aug 2017 16:08:57 +0930 In-Reply-To: <20170809062828.3673-3-andrew@aj.id.au> References: <20170809062828.3673-1-andrew@aj.id.au> <20170809062828.3673-3-andrew@aj.id.au> Content-Type: multipart/signed; micalg="pgp-sha512"; protocol="application/pgp-signature"; boundary="=-8XhJjBNpGSdVp8W+1GiW" X-Mailer: Evolution 3.22.6-1ubuntu1 Mime-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 66.111.4.25 Subject: Re: [Qemu-arm] [PATCH for 2.11 v2 2/2] ARM: aspeed_soc: Propagate silicon-rev to watchdog X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 09 Aug 2017 06:39:14 -0000 --=-8XhJjBNpGSdVp8W+1GiW Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Ugh, disregard this one; I changed the subject and reissued `git format-patch`, which naturally doesn't overwrite any existing patch in the output directory and so the old one got sent as well. Andrew On Wed, 2017-08-09 at 15:58 +0930, Andrew Jeffery wrote: > This is required to configure differences in behaviour between the > AST2400 and AST2500 watchdog IPs. >=20 > Signed-off-by: Andrew Jeffery > --- > =C2=A0hw/arm/aspeed_soc.c | 2 ++ > =C2=A01 file changed, 2 insertions(+) >=20 > diff --git a/hw/arm/aspeed_soc.c b/hw/arm/aspeed_soc.c > index 3034849c80bf..79804e1ee652 100644 > --- a/hw/arm/aspeed_soc.c > +++ b/hw/arm/aspeed_soc.c > @@ -183,6 +183,8 @@ static void aspeed_soc_init(Object *obj) > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0object_initialize(&= s->wdt[i], sizeof(s->wdt[i]), > TYPE_ASPEED_WDT); > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0object_property_add= _child(obj, "wdt[*]", OBJECT(&s->wdt[i]),=20 > NULL); > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0qdev_set_parent_bus= (DEVICE(&s->wdt[i]), > sysbus_get_default()); > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0qdev_prop_set_uint32(DEV= ICE(&s->wdt[i]), "silicon-rev", > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0sc->in= fo->silicon_rev); > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0} > =C2=A0 > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0object_initialize(&s->ftgmac100, sizeof(s->= ftgmac100), > TYPE_FTGMAC100); --=-8XhJjBNpGSdVp8W+1GiW Content-Type: application/pgp-signature; name="signature.asc" Content-Description: This is a digitally signed message part Content-Transfer-Encoding: 7bit -----BEGIN PGP SIGNATURE----- iQIcBAABCgAGBQJZiq4BAAoJEJ0dnzgO5LT5tA4P/065hV+GiIoAUi6VRVPPiKoA KxXA3jfMAELdwniWC2XhCIBPr2pFXMLqLOGTwqRBs8tDR/+RF9/0EnyfxA9rDB2S PmNyFfHiwmRlDn8nD9Sn7kYzM/JzHGQuKMjlLZHLSfU+B+y8mWUMdvujkp7NoFwx MoNvJsq9y0eqDUsk4VEZd/MqJNhhuNylLmVd1ptsQRGDpHYSk+5dSvyq2/y4FjRU OYY/5Dt9m86WA70Yiesyr0UgPaQ2u+/F9hCzienHLwnWgdJGaCVsCbIWQDZ9eDRi IcpFUhVBcfjF4xwV5U0iuo2mbUBXdPtFU32EJJmVtaSMbD5PpGgFjOYd1sK4TEsu SLRaQQ8TRMLfXqyS5hlrD3cEmF2aicJFpriLzVFJYFqtb8eX26hsTjPglbQC2DBg OSyybGeU3YSiZvkzzQym4kktsxgQ1hM5NSLzqlxQjwWfc440fLgkPK3Iq0tNm6w8 eEKFEnfzB41mZ7zgVlJu8wB47ZP/pKNJZuZO8520bSRuiMuUC+NvqWQhoRV707jp INWX7JDilvqDF/0VpETfEAatslAoRmbSItOrNbxwv6CTzyApmR4tqhbGeH9Upmj7 /t0jH9P4DjC9JX3g94Fz73rVimh0DzhMrcICeWnChqygcIBTo2B1LwXS7oc9W7nc nQFRyMwa+RWGaFZo/uf5 =sEhT -----END PGP SIGNATURE----- --=-8XhJjBNpGSdVp8W+1GiW-- From MAILER-DAEMON Wed Aug 09 04:58:37 2017 Received: from list by lists.gnu.org with archive (Exim 4.71) id 1dfMp3-0002Dy-NY for mharc-qemu-arm@gnu.org; Wed, 09 Aug 2017 04:58:37 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:51818) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dfMp0-0002Dh-O9 for qemu-arm@nongnu.org; Wed, 09 Aug 2017 04:58:36 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dfMov-0004Ae-Pw for qemu-arm@nongnu.org; Wed, 09 Aug 2017 04:58:34 -0400 Received: from 7.mo177.mail-out.ovh.net ([46.105.61.149]:59218) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1dfMov-00049n-GF for qemu-arm@nongnu.org; Wed, 09 Aug 2017 04:58:29 -0400 Received: from player779.ha.ovh.net (b9.ovh.net [213.186.33.59]) by mo177.mail-out.ovh.net (Postfix) with ESMTP id E8229740A6 for ; Wed, 9 Aug 2017 10:58:25 +0200 (CEST) Received: from zorba.kaod.org (LFbn-1-10652-153.w90-89.abo.wanadoo.fr [90.89.238.153]) (Authenticated sender: postmaster@kaod.org) by player779.ha.ovh.net (Postfix) with ESMTPSA id E953C7C0082; Wed, 9 Aug 2017 10:58:16 +0200 (CEST) To: Andrew Jeffery , qemu-arm@nongnu.org Cc: qemu-devel@nongnu.org, peter.maydell@linaro.org, joel@jms.id.au, f4bug@amsat.org, ryan_chen@aspeedtech.com, openbmc@lists.ozlabs.org References: <20170809062828.3673-1-andrew@aj.id.au> <20170809062828.3673-2-andrew@aj.id.au> From: =?UTF-8?Q?C=c3=a9dric_Le_Goater?= Message-ID: <8d122179-665f-2cbe-939e-2e466b98b28d@kaod.org> Date: Wed, 9 Aug 2017 10:58:16 +0200 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.2.1 MIME-Version: 1.0 In-Reply-To: <20170809062828.3673-2-andrew@aj.id.au> Content-Type: text/plain; charset=utf-8 Content-Language: en-US X-Ovh-Tracer-Id: 14893685446081088258 X-VR-SPAMSTATE: OK X-VR-SPAMSCORE: -100 X-VR-SPAMCAUSE: gggruggvucftvghtrhhoucdtuddrfeelkedrkeehgdduudcutefuodetggdotefrodftvfcurfhrohhfihhlvgemucfqggfjpdevjffgvefmvefgnecuuegrihhlohhuthemuceftddtnecusecvtfgvtghiphhivghnthhsucdlqddutddtmd Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 46.105.61.149 Subject: Re: [Qemu-arm] [PATCH for 2.11 v2 1/2] watchdog: wdt_aspeed: Add support for the reset width register X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 09 Aug 2017 08:58:36 -0000 On 08/09/2017 08:28 AM, Andrew Jeffery wrote: > The reset width register controls how the pulse on the SoC's WDTRST{1,2= } > pins behaves. A pulse is emitted if the external reset bit is set in > WDT_CTRL. On the AST2500 WDT_RESET_WIDTH can consume magic bit patterns > to configure push-pull/open-drain and active-high/active-low > behaviours and thus needs some special handling in the write path. >=20 > As some of the capabilities depend on the SoC version a silicon-rev > property is introduced, which is used to guard version-specific > behaviour. >=20 > Signed-off-by: Andrew Jeffery One minor comment below. Nevertheless : Reviewed-by: C=C3=A9dric Le Goater > --- > hw/watchdog/wdt_aspeed.c | 93 ++++++++++++++++++++++++++++++++= +++----- > include/hw/watchdog/wdt_aspeed.h | 2 + > 2 files changed, 84 insertions(+), 11 deletions(-) >=20 > diff --git a/hw/watchdog/wdt_aspeed.c b/hw/watchdog/wdt_aspeed.c > index 8bbe579b6b66..22bce364d7b5 100644 > --- a/hw/watchdog/wdt_aspeed.c > +++ b/hw/watchdog/wdt_aspeed.c > @@ -8,16 +8,19 @@ > */ > =20 > #include "qemu/osdep.h" > + > +#include "qapi/error.h" > #include "qemu/log.h" > +#include "qemu/timer.h" > #include "sysemu/watchdog.h" > +#include "hw/misc/aspeed_scu.h" > #include "hw/sysbus.h" > -#include "qemu/timer.h" > #include "hw/watchdog/wdt_aspeed.h" > =20 > -#define WDT_STATUS (0x00 / 4) > -#define WDT_RELOAD_VALUE (0x04 / 4) > -#define WDT_RESTART (0x08 / 4) > -#define WDT_CTRL (0x0C / 4) > +#define WDT_STATUS (0x00 / 4) > +#define WDT_RELOAD_VALUE (0x04 / 4) > +#define WDT_RESTART (0x08 / 4) > +#define WDT_CTRL (0x0C / 4) > #define WDT_CTRL_RESET_MODE_SOC (0x00 << 5) > #define WDT_CTRL_RESET_MODE_FULL_CHIP (0x01 << 5) > #define WDT_CTRL_1MHZ_CLK BIT(4) > @@ -25,18 +28,41 @@ > #define WDT_CTRL_WDT_INTR BIT(2) > #define WDT_CTRL_RESET_SYSTEM BIT(1) > #define WDT_CTRL_ENABLE BIT(0) > +#define WDT_RESET_WIDTH (0x18 / 4) > +#define WDT_RESET_WIDTH_ACTIVE_HIGH BIT(31) > +#define WDT_POLARITY_MASK (0xFF << 24) > +#define WDT_ACTIVE_HIGH_MAGIC (0xA5 << 24) > +#define WDT_ACTIVE_LOW_MAGIC (0x5A << 24) > +#define WDT_RESET_WIDTH_PUSH_PULL BIT(30) > +#define WDT_DRIVE_TYPE_MASK (0xFF << 24) > +#define WDT_PUSH_PULL_MAGIC (0xA8 << 24) > +#define WDT_OPEN_DRAIN_MAGIC (0x8A << 24) > =20 > -#define WDT_TIMEOUT_STATUS (0x10 / 4) > -#define WDT_TIMEOUT_CLEAR (0x14 / 4) > -#define WDT_RESET_WDITH (0x18 / 4) > +#define WDT_TIMEOUT_STATUS (0x10 / 4) > +#define WDT_TIMEOUT_CLEAR (0x14 / 4) > =20 > -#define WDT_RESTART_MAGIC 0x4755 > +#define WDT_RESTART_MAGIC 0x4755 > =20 > static bool aspeed_wdt_is_enabled(const AspeedWDTState *s) > { > return s->regs[WDT_CTRL] & WDT_CTRL_ENABLE; > } > =20 > +static bool is_ast2500(const AspeedWDTState *s) I think we could use this routine in other controllers (scu, sdmc).=20 So may be, in a follow-up patch, we could move it in aspeed_scu.h Thanks, C.=20 =20 > +{ > + switch (s->silicon_rev) { > + case AST2500_A0_SILICON_REV: > + case AST2500_A1_SILICON_REV: > + return true; > + case AST2400_A0_SILICON_REV: > + case AST2400_A1_SILICON_REV: > + default: > + break; > + } > + > + return false; > +} > + > static uint64_t aspeed_wdt_read(void *opaque, hwaddr offset, unsigned = size) > { > AspeedWDTState *s =3D ASPEED_WDT(opaque); > @@ -55,9 +81,10 @@ static uint64_t aspeed_wdt_read(void *opaque, hwaddr= offset, unsigned size) > return 0; > case WDT_CTRL: > return s->regs[WDT_CTRL]; > + case WDT_RESET_WIDTH: > + return s->regs[WDT_RESET_WIDTH]; > case WDT_TIMEOUT_STATUS: > case WDT_TIMEOUT_CLEAR: > - case WDT_RESET_WDITH: > qemu_log_mask(LOG_UNIMP, > "%s: uninmplemented read at offset 0x%" HWADDR_P= RIx "\n", > __func__, offset); > @@ -119,9 +146,27 @@ static void aspeed_wdt_write(void *opaque, hwaddr = offset, uint64_t data, > timer_del(s->timer); > } > break; > + case WDT_RESET_WIDTH: > + { > + uint32_t property =3D data & WDT_POLARITY_MASK; > + > + if (property && is_ast2500(s)) { > + if (property =3D=3D WDT_ACTIVE_HIGH_MAGIC) { > + s->regs[WDT_RESET_WIDTH] |=3D WDT_RESET_WIDTH_ACTIVE_H= IGH; > + } else if (property =3D=3D WDT_ACTIVE_LOW_MAGIC) { > + s->regs[WDT_RESET_WIDTH] &=3D ~WDT_RESET_WIDTH_ACTIVE_= HIGH; > + } else if (property =3D=3D WDT_PUSH_PULL_MAGIC) { > + s->regs[WDT_RESET_WIDTH] |=3D WDT_RESET_WIDTH_PUSH_PUL= L; > + } else if (property =3D=3D WDT_OPEN_DRAIN_MAGIC) { > + s->regs[WDT_RESET_WIDTH] &=3D ~WDT_RESET_WIDTH_PUSH_PU= LL; > + } > + } > + s->regs[WDT_RESET_WIDTH] &=3D ~s->ext_pulse_width_mask; > + s->regs[WDT_RESET_WIDTH] |=3D data & s->ext_pulse_width_mask; > + break; > + } > case WDT_TIMEOUT_STATUS: > case WDT_TIMEOUT_CLEAR: > - case WDT_RESET_WDITH: > qemu_log_mask(LOG_UNIMP, > "%s: uninmplemented write at offset 0x%" HWADDR_= PRIx "\n", > __func__, offset); > @@ -167,6 +212,7 @@ static void aspeed_wdt_reset(DeviceState *dev) > s->regs[WDT_RELOAD_VALUE] =3D 0x03EF1480; > s->regs[WDT_RESTART] =3D 0; > s->regs[WDT_CTRL] =3D 0; > + s->regs[WDT_RESET_WIDTH] =3D 0xFF; > =20 > timer_del(s->timer); > } > @@ -187,6 +233,25 @@ static void aspeed_wdt_realize(DeviceState *dev, E= rror **errp) > SysBusDevice *sbd =3D SYS_BUS_DEVICE(dev); > AspeedWDTState *s =3D ASPEED_WDT(dev); > =20 > + if (!is_supported_silicon_rev(s->silicon_rev)) { > + error_setg(errp, "Unknown silicon revision: 0x%" PRIx32, > + s->silicon_rev); > + return; > + } > + > + switch (s->silicon_rev) { > + case AST2400_A0_SILICON_REV: > + case AST2400_A1_SILICON_REV: > + s->ext_pulse_width_mask =3D 0xff; > + break; > + case AST2500_A0_SILICON_REV: > + case AST2500_A1_SILICON_REV: > + s->ext_pulse_width_mask =3D 0xfffff; > + break; > + default: > + g_assert_not_reached(); > + } > + > s->timer =3D timer_new_ns(QEMU_CLOCK_VIRTUAL, aspeed_wdt_timer_exp= ired, dev); > =20 > /* FIXME: This setting should be derived from the SCU hw strapping > @@ -199,6 +264,11 @@ static void aspeed_wdt_realize(DeviceState *dev, E= rror **errp) > sysbus_init_mmio(sbd, &s->iomem); > } > =20 > +static Property aspeed_wdt_properties[] =3D { > + DEFINE_PROP_UINT32("silicon-rev", AspeedWDTState, silicon_rev, 0), > + DEFINE_PROP_END_OF_LIST(), > +}; > + > static void aspeed_wdt_class_init(ObjectClass *klass, void *data) > { > DeviceClass *dc =3D DEVICE_CLASS(klass); > @@ -207,6 +277,7 @@ static void aspeed_wdt_class_init(ObjectClass *klas= s, void *data) > dc->reset =3D aspeed_wdt_reset; > set_bit(DEVICE_CATEGORY_MISC, dc->categories); > dc->vmsd =3D &vmstate_aspeed_wdt; > + dc->props =3D aspeed_wdt_properties; > } > =20 > static const TypeInfo aspeed_wdt_info =3D { > diff --git a/include/hw/watchdog/wdt_aspeed.h b/include/hw/watchdog/wdt= _aspeed.h > index 080c2231222e..7de3e5c224fb 100644 > --- a/include/hw/watchdog/wdt_aspeed.h > +++ b/include/hw/watchdog/wdt_aspeed.h > @@ -27,6 +27,8 @@ typedef struct AspeedWDTState { > uint32_t regs[ASPEED_WDT_REGS_MAX]; > =20 > uint32_t pclk_freq; > + uint32_t silicon_rev; > + uint32_t ext_pulse_width_mask; > } AspeedWDTState; > =20 > #endif /* ASPEED_WDT_H */ >=20 From MAILER-DAEMON Wed Aug 09 04:59:10 2017 Received: from list by lists.gnu.org with archive (Exim 4.71) id 1dfMpa-0002TE-2e for mharc-qemu-arm@gnu.org; Wed, 09 Aug 2017 04:59:10 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:51912) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dfMpX-0002Rg-OE for qemu-arm@nongnu.org; Wed, 09 Aug 2017 04:59:08 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dfMpT-0004No-OC for qemu-arm@nongnu.org; Wed, 09 Aug 2017 04:59:07 -0400 Received: from 5.mo177.mail-out.ovh.net ([46.105.39.154]:44102) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1dfMpT-0004NQ-HO for qemu-arm@nongnu.org; Wed, 09 Aug 2017 04:59:03 -0400 Received: from player779.ha.ovh.net (b9.ovh.net [213.186.33.59]) by mo177.mail-out.ovh.net (Postfix) with ESMTP id 2A4D9743B2 for ; Wed, 9 Aug 2017 10:59:02 +0200 (CEST) Received: from zorba.kaod.org (LFbn-1-10652-153.w90-89.abo.wanadoo.fr [90.89.238.153]) (Authenticated sender: postmaster@kaod.org) by player779.ha.ovh.net (Postfix) with ESMTPSA id E273D7C008B; Wed, 9 Aug 2017 10:58:54 +0200 (CEST) To: Andrew Jeffery , qemu-arm@nongnu.org Cc: qemu-devel@nongnu.org, peter.maydell@linaro.org, joel@jms.id.au, ryan_chen@aspeedtech.com, f4bug@amsat.org, openbmc@lists.ozlabs.org References: <20170809062828.3673-1-andrew@aj.id.au> <20170809062828.3673-3-andrew@aj.id.au> From: =?UTF-8?Q?C=c3=a9dric_Le_Goater?= Message-ID: <78e09d93-ba07-c882-8830-737691f83a3c@kaod.org> Date: Wed, 9 Aug 2017 10:58:54 +0200 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.2.1 MIME-Version: 1.0 In-Reply-To: <20170809062828.3673-3-andrew@aj.id.au> Content-Type: text/plain; charset=utf-8 Content-Language: en-US X-Ovh-Tracer-Id: 14904100021060471554 X-VR-SPAMSTATE: OK X-VR-SPAMSCORE: -100 X-VR-SPAMCAUSE: gggruggvucftvghtrhhoucdtuddrfeelkedrkeehgdduudcutefuodetggdotefrodftvfcurfhrohhfihhlvgemucfqggfjpdevjffgvefmvefgnecuuegrihhlohhuthemuceftddtnecusecvtfgvtghiphhivghnthhsucdlqddutddtmd Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 46.105.39.154 Subject: Re: [Qemu-arm] [PATCH for 2.11 v2 2/2] ARM: aspeed_soc: Propagate silicon-rev to watchdog X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 09 Aug 2017 08:59:09 -0000 On 08/09/2017 08:28 AM, Andrew Jeffery wrote: > This is required to configure differences in behaviour between the > AST2400 and AST2500 watchdog IPs. >=20 > Signed-off-by: Andrew Jeffery Reviewed-by: C=C3=A9dric Le Goater > --- > hw/arm/aspeed_soc.c | 2 ++ > 1 file changed, 2 insertions(+) >=20 > diff --git a/hw/arm/aspeed_soc.c b/hw/arm/aspeed_soc.c > index 3034849c80bf..79804e1ee652 100644 > --- a/hw/arm/aspeed_soc.c > +++ b/hw/arm/aspeed_soc.c > @@ -183,6 +183,8 @@ static void aspeed_soc_init(Object *obj) > object_initialize(&s->wdt[i], sizeof(s->wdt[i]), TYPE_ASPEED_W= DT); > object_property_add_child(obj, "wdt[*]", OBJECT(&s->wdt[i]), N= ULL); > qdev_set_parent_bus(DEVICE(&s->wdt[i]), sysbus_get_default()); > + qdev_prop_set_uint32(DEVICE(&s->wdt[i]), "silicon-rev", > + sc->info->silicon_rev); > } > =20 > object_initialize(&s->ftgmac100, sizeof(s->ftgmac100), TYPE_FTGMAC= 100); >=20 From MAILER-DAEMON Wed Aug 09 06:30:27 2017 Received: from list by lists.gnu.org with archive (Exim 4.71) id 1dfOFv-0005Vp-0N for mharc-qemu-arm@gnu.org; Wed, 09 Aug 2017 06:30:27 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:52532) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dfOFr-0005VG-Mj for qemu-arm@nongnu.org; Wed, 09 Aug 2017 06:30:25 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dfOFn-0001Gu-8V for qemu-arm@nongnu.org; Wed, 09 Aug 2017 06:30:23 -0400 Received: from out1-smtp.messagingengine.com ([66.111.4.25]:52885) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1dfOFm-0001Ev-H7; Wed, 09 Aug 2017 06:30:19 -0400 Received: from compute4.internal (compute4.nyi.internal [10.202.2.44]) by mailout.nyi.internal (Postfix) with ESMTP id E050B20958; Wed, 9 Aug 2017 06:30:17 -0400 (EDT) Received: from web2 ([10.202.2.212]) by compute4.internal (MEProxy); Wed, 09 Aug 2017 06:30:17 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=aj.id.au; h=cc :content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to:x-me-sender :x-me-sender:x-sasl-enc; s=fm1; bh=weuV/nlyoPanR4Dz089WDkLD91w0h ARLHdOdov2iF6k=; b=t6bgbRL/vxIEnwnKD3XiDEJ7/VxpQCIVJS6eQuij8bZpN wEr2IYYQeUNznZrLy4537pFvmY47W+meeIMfp6fs4dJmdlgHLcgE1PS1gwuDmToG IIrRhE5eZnh8JHbMaUVdBhq9FBhXGKqWe+ycjVHcO/4I7Szkkmx5UX0LQvHH+u9u ilTwkWHtaPD1qAvUw/y6Odxg6DjGCNu4/nOlh3VsiYwZHHtHKZ6+IIUJm36s+eFo 2K2q+JZboAHMZU/UVxniOff8WfLgYmWUFgtk7FwoB0AX7zv4qlF6Y+uSDJmEOYP1 ohfttIYcGBQOiQQhBNFAMkiD2XGTtwZpNGM6Wyrkw== DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d= messagingengine.com; h=cc:content-transfer-encoding:content-type :date:from:in-reply-to:message-id:mime-version:references :subject:to:x-me-sender:x-me-sender:x-sasl-enc; s=fm1; bh=weuV/n lyoPanR4Dz089WDkLD91w0hARLHdOdov2iF6k=; b=njhl3EqlpJfKKtL4jjZgwc cYwrSGKu+2FQKKylujxYXLguyychtzJeCDvC0tUvoz/IQ5KUm+CAP2d7ZW2nh7RU 6zSy3e2Uczg3+Gq9F3hQtVEi4AEQ8zZR3JCI9uHcUnhr4SIzhpWBVNxRuxQXw0tH SYJWUgoEdMWsP1wnRExxCD6vRf80gSS9gufp4Ka54shlyPvUjT7lBn0XZmajaFNi 1RgI1JISidGE2gL7disXTbwK63FWePwTXHAVxNsuhB9hxKdTo+1YItivsHAhDvFt +XYgS6CYI29a31/tgIxjm+X6+LXlU1412pC/+hSL0j5dH+pD1fQ09Qx4kQ7wCsVQ == X-ME-Sender: Received: by mailuser.nyi.internal (Postfix, from userid 99) id BBEDA6264D; Wed, 9 Aug 2017 06:30:17 -0400 (EDT) Message-Id: <1502274617.2058464.1067857056.3F238295@webmail.messagingengine.com> From: Andrew Jeffery To: =?utf-8?Q?C=C3=A9dric=20Le=20Goater?= , qemu-arm@nongnu.org Cc: qemu-devel@nongnu.org, peter.maydell@linaro.org, joel@jms.id.au, f4bug@amsat.org, ryan_chen@aspeedtech.com, openbmc@lists.ozlabs.org MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" X-Mailer: MessagingEngine.com Webmail Interface - ajax-4448c6f4 Date: Wed, 09 Aug 2017 20:00:17 +0930 References: <20170809062828.3673-1-andrew@aj.id.au> <20170809062828.3673-2-andrew@aj.id.au> <8d122179-665f-2cbe-939e-2e466b98b28d@kaod.org> In-Reply-To: <8d122179-665f-2cbe-939e-2e466b98b28d@kaod.org> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 66.111.4.25 Subject: Re: [Qemu-arm] [PATCH for 2.11 v2 1/2] watchdog: wdt_aspeed: Add support for the reset width register X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 09 Aug 2017 10:30:25 -0000 On Wed, Aug 9, 2017, at 18:28, C=C3=A9dric Le Goater wrote: > On 08/09/2017 08:28 AM, Andrew Jeffery wrote: > > The reset width register controls how the pulse on the SoC's WDTRST{1,2} > > pins behaves. A pulse is emitted if the external reset bit is set in > > WDT_CTRL. On the AST2500 WDT_RESET_WIDTH can consume magic bit patterns > > to configure push-pull/open-drain and active-high/active-low > > behaviours and thus needs some special handling in the write path. > >=20 > > As some of the capabilities depend on the SoC version a silicon-rev > > property is introduced, which is used to guard version-specific > > behaviour. > >=20 > > Signed-off-by: Andrew Jeffery >=20 > One minor comment below. Nevertheless : >=20 > Reviewed-by: C=C3=A9dric Le Goater >=20 > > --- > > hw/watchdog/wdt_aspeed.c | 93 ++++++++++++++++++++++++++++++++= +++----- > > include/hw/watchdog/wdt_aspeed.h | 2 + > > 2 files changed, 84 insertions(+), 11 deletions(-) > >=20 > > diff --git a/hw/watchdog/wdt_aspeed.c b/hw/watchdog/wdt_aspeed.c > > index 8bbe579b6b66..22bce364d7b5 100644 > > --- a/hw/watchdog/wdt_aspeed.c > > +++ b/hw/watchdog/wdt_aspeed.c > > @@ -8,16 +8,19 @@ > > */ > >=20=20 > > #include "qemu/osdep.h" > > + > > +#include "qapi/error.h" > > #include "qemu/log.h" > > +#include "qemu/timer.h" > > #include "sysemu/watchdog.h" > > +#include "hw/misc/aspeed_scu.h" > > #include "hw/sysbus.h" > > -#include "qemu/timer.h" > > #include "hw/watchdog/wdt_aspeed.h" > >=20=20 > > -#define WDT_STATUS (0x00 / 4) > > -#define WDT_RELOAD_VALUE (0x04 / 4) > > -#define WDT_RESTART (0x08 / 4) > > -#define WDT_CTRL (0x0C / 4) > > +#define WDT_STATUS (0x00 / 4) > > +#define WDT_RELOAD_VALUE (0x04 / 4) > > +#define WDT_RESTART (0x08 / 4) > > +#define WDT_CTRL (0x0C / 4) > > #define WDT_CTRL_RESET_MODE_SOC (0x00 << 5) > > #define WDT_CTRL_RESET_MODE_FULL_CHIP (0x01 << 5) > > #define WDT_CTRL_1MHZ_CLK BIT(4) > > @@ -25,18 +28,41 @@ > > #define WDT_CTRL_WDT_INTR BIT(2) > > #define WDT_CTRL_RESET_SYSTEM BIT(1) > > #define WDT_CTRL_ENABLE BIT(0) > > +#define WDT_RESET_WIDTH (0x18 / 4) > > +#define WDT_RESET_WIDTH_ACTIVE_HIGH BIT(31) > > +#define WDT_POLARITY_MASK (0xFF << 24) > > +#define WDT_ACTIVE_HIGH_MAGIC (0xA5 << 24) > > +#define WDT_ACTIVE_LOW_MAGIC (0x5A << 24) > > +#define WDT_RESET_WIDTH_PUSH_PULL BIT(30) > > +#define WDT_DRIVE_TYPE_MASK (0xFF << 24) > > +#define WDT_PUSH_PULL_MAGIC (0xA8 << 24) > > +#define WDT_OPEN_DRAIN_MAGIC (0x8A << 24) > >=20=20 > > -#define WDT_TIMEOUT_STATUS (0x10 / 4) > > -#define WDT_TIMEOUT_CLEAR (0x14 / 4) > > -#define WDT_RESET_WDITH (0x18 / 4) > > +#define WDT_TIMEOUT_STATUS (0x10 / 4) > > +#define WDT_TIMEOUT_CLEAR (0x14 / 4) > >=20=20 > > -#define WDT_RESTART_MAGIC 0x4755 > > +#define WDT_RESTART_MAGIC 0x4755 > >=20=20 > > static bool aspeed_wdt_is_enabled(const AspeedWDTState *s) > > { > > return s->regs[WDT_CTRL] & WDT_CTRL_ENABLE; > > } > >=20=20 > > +static bool is_ast2500(const AspeedWDTState *s) >=20 > I think we could use this routine in other controllers (scu, sdmc).=20 > So may be, in a follow-up patch, we could move it in aspeed_scu.h Right, I figured we would move it when we came to need it elsewhere. Thanks for the review. Cheers, Andrew >=20 > Thanks, >=20 > C.=20 >=20=20 > > +{ > > + switch (s->silicon_rev) { > > + case AST2500_A0_SILICON_REV: > > + case AST2500_A1_SILICON_REV: > > + return true; > > + case AST2400_A0_SILICON_REV: > > + case AST2400_A1_SILICON_REV: > > + default: > > + break; > > + } > > + > > + return false; > > +} > > + > > static uint64_t aspeed_wdt_read(void *opaque, hwaddr offset, unsigned = size) > > { > > AspeedWDTState *s =3D ASPEED_WDT(opaque); > > @@ -55,9 +81,10 @@ static uint64_t aspeed_wdt_read(void *opaque, hwaddr= offset, unsigned size) > > return 0; > > case WDT_CTRL: > > return s->regs[WDT_CTRL]; > > + case WDT_RESET_WIDTH: > > + return s->regs[WDT_RESET_WIDTH]; > > case WDT_TIMEOUT_STATUS: > > case WDT_TIMEOUT_CLEAR: > > - case WDT_RESET_WDITH: > > qemu_log_mask(LOG_UNIMP, > > "%s: uninmplemented read at offset 0x%" HWADDR_P= RIx "\n", > > __func__, offset); > > @@ -119,9 +146,27 @@ static void aspeed_wdt_write(void *opaque, hwaddr = offset, uint64_t data, > > timer_del(s->timer); > > } > > break; > > + case WDT_RESET_WIDTH: > > + { > > + uint32_t property =3D data & WDT_POLARITY_MASK; > > + > > + if (property && is_ast2500(s)) { > > + if (property =3D=3D WDT_ACTIVE_HIGH_MAGIC) { > > + s->regs[WDT_RESET_WIDTH] |=3D WDT_RESET_WIDTH_ACTIVE_H= IGH; > > + } else if (property =3D=3D WDT_ACTIVE_LOW_MAGIC) { > > + s->regs[WDT_RESET_WIDTH] &=3D ~WDT_RESET_WIDTH_ACTIVE_= HIGH; > > + } else if (property =3D=3D WDT_PUSH_PULL_MAGIC) { > > + s->regs[WDT_RESET_WIDTH] |=3D WDT_RESET_WIDTH_PUSH_PUL= L; > > + } else if (property =3D=3D WDT_OPEN_DRAIN_MAGIC) { > > + s->regs[WDT_RESET_WIDTH] &=3D ~WDT_RESET_WIDTH_PUSH_PU= LL; > > + } > > + } > > + s->regs[WDT_RESET_WIDTH] &=3D ~s->ext_pulse_width_mask; > > + s->regs[WDT_RESET_WIDTH] |=3D data & s->ext_pulse_width_mask; > > + break; > > + } > > case WDT_TIMEOUT_STATUS: > > case WDT_TIMEOUT_CLEAR: > > - case WDT_RESET_WDITH: > > qemu_log_mask(LOG_UNIMP, > > "%s: uninmplemented write at offset 0x%" HWADDR_= PRIx "\n", > > __func__, offset); > > @@ -167,6 +212,7 @@ static void aspeed_wdt_reset(DeviceState *dev) > > s->regs[WDT_RELOAD_VALUE] =3D 0x03EF1480; > > s->regs[WDT_RESTART] =3D 0; > > s->regs[WDT_CTRL] =3D 0; > > + s->regs[WDT_RESET_WIDTH] =3D 0xFF; > >=20=20 > > timer_del(s->timer); > > } > > @@ -187,6 +233,25 @@ static void aspeed_wdt_realize(DeviceState *dev, E= rror **errp) > > SysBusDevice *sbd =3D SYS_BUS_DEVICE(dev); > > AspeedWDTState *s =3D ASPEED_WDT(dev); > >=20=20 > > + if (!is_supported_silicon_rev(s->silicon_rev)) { > > + error_setg(errp, "Unknown silicon revision: 0x%" PRIx32, > > + s->silicon_rev); > > + return; > > + } > > + > > + switch (s->silicon_rev) { > > + case AST2400_A0_SILICON_REV: > > + case AST2400_A1_SILICON_REV: > > + s->ext_pulse_width_mask =3D 0xff; > > + break; > > + case AST2500_A0_SILICON_REV: > > + case AST2500_A1_SILICON_REV: > > + s->ext_pulse_width_mask =3D 0xfffff; > > + break; > > + default: > > + g_assert_not_reached(); > > + } > > + > > s->timer =3D timer_new_ns(QEMU_CLOCK_VIRTUAL, aspeed_wdt_timer_exp= ired, dev); > >=20=20 > > /* FIXME: This setting should be derived from the SCU hw strapping > > @@ -199,6 +264,11 @@ static void aspeed_wdt_realize(DeviceState *dev, E= rror **errp) > > sysbus_init_mmio(sbd, &s->iomem); > > } > >=20=20 > > +static Property aspeed_wdt_properties[] =3D { > > + DEFINE_PROP_UINT32("silicon-rev", AspeedWDTState, silicon_rev, 0), > > + DEFINE_PROP_END_OF_LIST(), > > +}; > > + > > static void aspeed_wdt_class_init(ObjectClass *klass, void *data) > > { > > DeviceClass *dc =3D DEVICE_CLASS(klass); > > @@ -207,6 +277,7 @@ static void aspeed_wdt_class_init(ObjectClass *klas= s, void *data) > > dc->reset =3D aspeed_wdt_reset; > > set_bit(DEVICE_CATEGORY_MISC, dc->categories); > > dc->vmsd =3D &vmstate_aspeed_wdt; > > + dc->props =3D aspeed_wdt_properties; > > } > >=20=20 > > static const TypeInfo aspeed_wdt_info =3D { > > diff --git a/include/hw/watchdog/wdt_aspeed.h b/include/hw/watchdog/wdt= _aspeed.h > > index 080c2231222e..7de3e5c224fb 100644 > > --- a/include/hw/watchdog/wdt_aspeed.h > > +++ b/include/hw/watchdog/wdt_aspeed.h > > @@ -27,6 +27,8 @@ typedef struct AspeedWDTState { > > uint32_t regs[ASPEED_WDT_REGS_MAX]; > >=20=20 > > uint32_t pclk_freq; > > + uint32_t silicon_rev; > > + uint32_t ext_pulse_width_mask; > > } AspeedWDTState; > >=20=20 > > #endif /* ASPEED_WDT_H */ > >=20 >=20 From MAILER-DAEMON Fri Aug 11 09:50:39 2017 Received: from list by lists.gnu.org with archive (Exim 4.71) id 1dgAKl-0000NC-8D for mharc-qemu-arm@gnu.org; Fri, 11 Aug 2017 09:50:39 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:52570) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dgAKi-0000My-FB for qemu-arm@nongnu.org; Fri, 11 Aug 2017 09:50:37 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dgAKf-0000IA-5f for qemu-arm@nongnu.org; Fri, 11 Aug 2017 09:50:36 -0400 Received: from mail-pg0-x22d.google.com ([2607:f8b0:400e:c05::22d]:33738) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1dgAKe-0000HL-To for qemu-arm@nongnu.org; Fri, 11 Aug 2017 09:50:33 -0400 Received: by mail-pg0-x22d.google.com with SMTP id u5so15936516pgn.0 for ; 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[50.233.235.3]) by smtp.gmail.com with ESMTPSA id x2sm3177971pfe.129.2017.08.11.06.50.30 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 11 Aug 2017 06:50:30 -0700 (PDT) To: Peter Maydell , qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Hua Yanghao , Richard Henderson , patches@linaro.org References: <1502116754-18867-1-git-send-email-peter.maydell@linaro.org> <1502116754-18867-2-git-send-email-peter.maydell@linaro.org> From: Richard Henderson Message-ID: Date: Fri, 11 Aug 2017 06:50:28 -0700 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.2.1 MIME-Version: 1.0 In-Reply-To: <1502116754-18867-2-git-send-email-peter.maydell@linaro.org> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 7bit X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::22d Subject: Re: [Qemu-arm] [Qemu-devel] [PATCH 1/2] loader: Handle ELF files with overlapping zero-initialized data X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 11 Aug 2017 13:50:37 -0000 On 08/07/2017 07:39 AM, Peter Maydell wrote: > For embedded systems, notably ARM, one common use of ELF > file segments is that the 'physical addresses' represent load addresses > and the 'virtual addresses' execution addresses, such that > the load addresses are packed into ROM or flash, and the > relocation and zero-initialization of data is done at runtime. > This means that the 'memsz' in the segment header represents > the runtime size of the segment, but the size that needs to > be loaded is only the 'filesz'. In particular, paddr+memsz > may overlap with the next segment to be loaded, as in this > example: > > 0x70000001 off 0x00007f68 vaddr 0x00008150 paddr 0x00008150 align 2**2 > filesz 0x00000008 memsz 0x00000008 flags r-- > LOAD off 0x000000f4 vaddr 0x00000000 paddr 0x00000000 align 2**2 > filesz 0x00000124 memsz 0x00000124 flags r-- > LOAD off 0x00000218 vaddr 0x00000400 paddr 0x00000400 align 2**3 > filesz 0x00007d58 memsz 0x00007d58 flags r-x > LOAD off 0x00007f70 vaddr 0x20000140 paddr 0x00008158 align 2**3 > filesz 0x00000a80 memsz 0x000022f8 flags rw- > LOAD off 0x000089f0 vaddr 0x20002438 paddr 0x00008bd8 align 2**0 > filesz 0x00000000 memsz 0x00004000 flags rw- > LOAD off 0x000089f0 vaddr 0x20000000 paddr 0x20000000 align 2**0 > filesz 0x00000000 memsz 0x00000140 flags rw- > > where the segment at paddr 0x8158 has a memsz of 0x2258 and > would overlap with the segment at paddr 0x8bd8 if QEMU's loader > tried to honour it. (At runtime the segments will not overlap > since their vaddrs are more widely spaced than their paddrs.) > > Currently if you try to load an ELF file like this with QEMU then > it will fail with an error "rom: requested regions overlap", > because we create a ROM image for each segment using the memsz > as the size. > > Support ELF files using this scheme, by truncating the > zero-initialized part of the segment if it would overlap another > segment. This will retain the existing loader behaviour for > all ELF files we currently accept, and also accept ELF files > which only need 'filesz' bytes to be loaded. > > Signed-off-by: Peter Maydell > --- > include/hw/elf_ops.h | 48 ++++++++++++++++++++++++++++++++++++++++++++++++ > 1 file changed, 48 insertions(+) Reviewed-by: Richard Henderson r~ From MAILER-DAEMON Fri Aug 11 09:51:32 2017 Received: from list by lists.gnu.org with archive (Exim 4.71) id 1dgALa-0000tJ-Rh for mharc-qemu-arm@gnu.org; Fri, 11 Aug 2017 09:51:32 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:52795) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dgALX-0000rq-Om for qemu-arm@nongnu.org; Fri, 11 Aug 2017 09:51:28 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dgALW-0001CU-O5 for qemu-arm@nongnu.org; Fri, 11 Aug 2017 09:51:27 -0400 Received: from mail-pg0-x234.google.com ([2607:f8b0:400e:c05::234]:32871) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1dgALW-0001C2-IU for qemu-arm@nongnu.org; Fri, 11 Aug 2017 09:51:26 -0400 Received: by mail-pg0-x234.google.com with SMTP id u5so15945013pgn.0 for ; Fri, 11 Aug 2017 06:51:26 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=subject:to:cc:references:from:message-id:date:user-agent :mime-version:in-reply-to:content-language:content-transfer-encoding; bh=MhFeo6BTJBKy2EFZXVLRDmfve0Fmj1DFDNoi9h75uY8=; b=DR5W3ZmpMC0CEHsnWoR0ej9rkP+w440YqomBxJ1l7y+dczX3kbClhWOhtDW4VM/Twd YDUEQsqJeSM9jPNaPiGj7ttssP0MgM1Iw5lzaZjaPoiXKMeBaRuM/2rryvNaFKUvlegf uKXQnArr1nJTsWq7HsWYbgo/jtG+K443/VE7M= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:subject:to:cc:references:from:message-id:date :user-agent:mime-version:in-reply-to:content-language :content-transfer-encoding; bh=MhFeo6BTJBKy2EFZXVLRDmfve0Fmj1DFDNoi9h75uY8=; b=ULlvSEMUHXrhZt7W6u65FVYMwSDqwmcLZB+Po6yNOsAxMH92PqtaX4n9njfEkH8f25 Y/hKrXkTJu3R4FIOelS3j7LaY8Ivke37zxkxLHVo/QBFLfi+9H83vv7zs1WZOalvlCR4 iQkD7P77/XK12e86oLl1BRKROAJKiUGcxTDEva7hyGykxq1YpBIj5hBRISg6TgtW+G7q lRb1BlAuUhZPwK8f8w45IxVTs/cVJCo/N+T9klrtpZNbS7b+neQajcJ6POiXa0AaZBhD YMMZHvG+/6sdwMUpP2mGNrwkVrNMc7aApmMDj9duzrYSosJ/c25CWI16jxVi/rCcNas2 SSGw== X-Gm-Message-State: AHYfb5hrOSQh3Vsv1+kb3x6Us3fZXidg7yFOS0rqXu8z9oFZGyWSfDqB iok2v5hZz07TWRaM X-Received: by 10.98.64.196 with SMTP id f65mr16124240pfd.123.1502459485628; Fri, 11 Aug 2017 06:51:25 -0700 (PDT) Received: from bigtime.twiddle.net (50-233-235-3-static.hfc.comcastbusiness.net. [50.233.235.3]) by smtp.gmail.com with ESMTPSA id a86sm2167457pfe.181.2017.08.11.06.51.23 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 11 Aug 2017 06:51:24 -0700 (PDT) To: Peter Maydell , qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Hua Yanghao , Richard Henderson , patches@linaro.org References: <1502116754-18867-1-git-send-email-peter.maydell@linaro.org> <1502116754-18867-3-git-send-email-peter.maydell@linaro.org> From: Richard Henderson Message-ID: <9c319371-41d7-d72a-bdfa-33f85e3bfa36@linaro.org> Date: Fri, 11 Aug 2017 06:51:22 -0700 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.2.1 MIME-Version: 1.0 In-Reply-To: <1502116754-18867-3-git-send-email-peter.maydell@linaro.org> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 7bit X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::234 Subject: Re: [Qemu-arm] [Qemu-devel] [PATCH 2/2] loader: Ignore zero-sized ELF segments X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 11 Aug 2017 13:51:29 -0000 On 08/07/2017 07:39 AM, Peter Maydell wrote: > Some ELF files have program headers that specify segments that > are of zero size. Ignore them, rather than trying to create > zero-length ROM blobs for them, because the zero-length blob > can falsely trigger the overlapping-ROM-blobs check. > > Signed-off-by: Peter Maydell > --- > include/hw/elf_ops.h | 24 +++++++++++++++++------- > 1 file changed, 17 insertions(+), 7 deletions(-) Reviewed-by: Richard Henderson r~ From MAILER-DAEMON Fri Aug 11 10:23:30 2017 Received: from list by lists.gnu.org with archive (Exim 4.71) id 1dgAqX-0008Ir-VK for mharc-qemu-arm@gnu.org; Fri, 11 Aug 2017 10:23:30 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:34037) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dgAqV-0008GZ-2F for qemu-arm@nongnu.org; Fri, 11 Aug 2017 10:23:28 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dgAqQ-0001qE-Tu for qemu-arm@nongnu.org; Fri, 11 Aug 2017 10:23:27 -0400 Received: from mx1.redhat.com ([209.132.183.28]:39222) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1dgAqQ-0001oB-L7; Fri, 11 Aug 2017 10:23:22 -0400 Received: from smtp.corp.redhat.com (int-mx06.intmail.prod.int.phx2.redhat.com [10.5.11.16]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id 79209A0B20; Fri, 11 Aug 2017 14:23:19 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mx1.redhat.com 79209A0B20 Authentication-Results: ext-mx01.extmail.prod.ext.phx2.redhat.com; dmarc=none (p=none dis=none) header.from=redhat.com Authentication-Results: ext-mx01.extmail.prod.ext.phx2.redhat.com; spf=fail smtp.mailfrom=eric.auger@redhat.com Received: from localhost.localdomain.com (ovpn-116-162.ams2.redhat.com [10.36.116.162]) by smtp.corp.redhat.com (Postfix) with ESMTP id 4A568A21A6; Fri, 11 Aug 2017 14:23:04 +0000 (UTC) From: Eric Auger To: eric.auger.pro@gmail.com, eric.auger@redhat.com, peter.maydell@linaro.org, qemu-arm@nongnu.org, qemu-devel@nongnu.org, alex.williamson@redhat.com, prem.mallappa@gmail.com Cc: drjones@redhat.com, christoffer.dall@linaro.org, Radha.Chintakuntla@cavium.com, Sunil.Goutham@cavium.com, mohun106@gmail.com, tcain@qti.qualcomm.com, bharat.bhushan@nxp.com, tn@semihalf.com, mst@redhat.com, will.deacon@arm.com, jean-philippe.brucker@arm.com, robin.murphy@arm.com, peterx@redhat.com, edgar.iglesias@gmail.com Date: Fri, 11 Aug 2017 16:22:25 +0200 Message-Id: <1502461354-11327-1-git-send-email-eric.auger@redhat.com> X-Scanned-By: MIMEDefang 2.79 on 10.5.11.16 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.25]); Fri, 11 Aug 2017 14:23:19 +0000 (UTC) X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.132.183.28 Subject: [Qemu-arm] [RFC v6 0/9] ARM SMMUv3 Emulation Support X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 11 Aug 2017 14:23:29 -0000 This series implements the emulation code for ARM SMMUv3. This is the continuation of Prem's work [1]. This v6 fixes some VFIO integration issues: - Block replay was corrected. - Range unmap is done before the replay (vhost issue). - Introduction of a new CMDQ_OP_TLBI_NH_VA_AM command to handle invalidation of hugepages. DPDK was tested with a single assigned VF*. Also 64b MMIO accesses should be fixed now. For VFIO integration, a quirk is needed on guest side in the arm-smmu-v3 driver [2]. This quirk now can used both in dt and ACPI modes. The smmu is instantiated when passing the smmu option to machvirt: "-M virt-2.10,smmu". Most probably I will change this to instantiate it using -device option in next version and add an option to select caching mode. The series needs to be further split to allow decent reviews and I don't expect any at this stage. However testing really is welcome. I tested the following use cases: - booted a guest in dt and acpi mode with an iommu_platform virtio-net-pci device (using dma ops). Tested with the following guest combinations: 4K page - 39 bit VA, 4K - 48b, 64K - 39b, 64K - 48b. - booted a guest [2] with assigned PCIe device virtual functions: - AMD Overdrive and igbvf passthrough (using gsi direct mapping) - Cavium ThunderX and ixgbevf passthrough (using KVM MSI routing) - ran DPDK testpmd on guest using a single passthroughed igbvf. * dpdk testpmd using Using 2 igbvf's does not work at the moment: - the issue is on guest side the 2 devices are put in the same domain by vfio_iommu_type1_attach_group() and mappings are replayed on a single devicephysical smmu only for the 1st device. This causes an smmu fault. I will address this in next revision. Known limitations: - no VMSAv8-32 suport - no nested stage support (S1 + S2) - no support for HYP mappings - register fine emulation, commands, interrupts and errors were not accurately tested. Handling is sufficient to run use cases described above though. Best Regards Eric This series can be found at: v6: https://github.com/eauger/qemu/tree/v2.10.0-rc2-SMMU-v6 v5: https://github.com/eauger/qemu/tree/v2.9-SMMU-v5 References: [1] Prem's last iteration: [2] [RFC v2 0/4] arm-smmu-v3 tlbi-on-map option History: v5 -> v6: - Rebase on 2.10 and IOMMUMemoryRegion - add ACPI TLBI_ON_MAP support (VFIO integration also works in ACPI mode) - fix block replay - handle implementation defined SMMU_CMD_TLBI_NH_VA_AM cmd (goes along with TLBI_ON_MAP FW quirk) - replay systematically unmap the whole range first - smmuv3_map_hook does not unmap anymore and the unmap is done before the replay - add and use smmuv3_context_device_invalidate instead of blindly replaying everything v4 -> v5: - initial_level now part of SMMUTransCfg - smmu_page_walk_64 takes into account the max input size - implement sys->iommu_ops.replay and sys->iommu_ops.notify_flag_changed - smmuv3_translate: bug fix: don't walk on bypass - smmu_update_qreg: fix PROD index update - I did not yet address Peter's comments as the code is not mature enough to be split into sub patches. v3 -> v4 [Eric]: - page table walk rewritten to allow scan of the page table within a range of IOVA. This prepares for VFIO integration and replay. - configuration parsing partially reworked. - do not advertise unsupported/untested features: S2, S1 + S2, HYP, PRI, ATS, .. - added ACPI table generation - migrated to dynamic traces - mingw compilation fix v2 -> v3 [Eric]: - rebased on 2.9 - mostly code and patch reorganization to ease the review process - optional patches removed. They may be handled separately. I am currently working on ACPI enablement. - optional instantiation of the smmu in mach-virt - removed [2/9] (fdt functions) since not mandated - start splitting main patch into base and derived object - no new function feature added v1 -> v2 [Prem]: - Adopted review comments from Eric Auger - Make SMMU_DPRINTF to internally call qemu_log (since translation requests are too many, we need control on the type of log we want) - SMMUTransCfg modified to suite simplicity - Change RegInfo to uint64 register array - Code cleanup - Test cleanups - Reshuffled patches v0 -> v1 [Prem]: - As per SMMUv3 spec 16.0 (only is_ste_consistant() is noticeable) - Reworked register access/update logic - Factored out translation code for - single point bug fix - sharing/removal in future - (optional) Unit tests added, with PCI test device - S1 with 4k/64k, S1+S2 with 4k/64k - (S1 or S2) only can be verified by Linux 4.7 driver - (optional) Priliminary ACPI support v0 [Prem]: - Implements SMMUv3 spec 11.0 - Supported for PCIe devices, - Command Queue and Event Queue supported - LPAE only, S1 is supported and Tested, S2 not tested - BE mode Translation not supported - IRQ support (legacy, no MSI) - Tested with DPDK and e1000 Eric Auger (6): hw/arm/smmu-common: smmu base class hw/arm/virt: Add 2.11 machine type hw/arm/virt: Add tlbi-on-map property to the smmuv3 node target/arm/kvm: Translate the MSI doorbell in kvm_arch_fixup_msi_route hw/arm/smmuv3: VFIO integration hw/arm/virt-acpi-build: Use the ACPI_IORT_SMMU_V3_CACHING_MODE model Prem Mallappa (3): hw/arm/smmuv3: smmuv3 emulation model hw/arm/virt: Add SMMUv3 to the virt board hw/arm/virt-acpi-build: Add smmuv3 node in IORT table default-configs/aarch64-softmmu.mak | 1 + hw/arm/Makefile.objs | 1 + hw/arm/smmu-common.c | 493 ++++++++++++ hw/arm/smmu-internal.h | 89 +++ hw/arm/smmuv3-internal.h | 652 ++++++++++++++++ hw/arm/smmuv3.c | 1412 +++++++++++++++++++++++++++++++++++ hw/arm/trace-events | 62 ++ hw/arm/virt-acpi-build.c | 58 +- hw/arm/virt.c | 110 ++- include/hw/acpi/acpi-defs.h | 15 + include/hw/arm/smmu-common.h | 126 ++++ include/hw/arm/smmuv3.h | 89 +++ include/hw/arm/virt.h | 5 + include/hw/compat.h | 3 + target/arm/kvm.c | 27 + target/arm/trace-events | 3 + 16 files changed, 3137 insertions(+), 9 deletions(-) create mode 100644 hw/arm/smmu-common.c create mode 100644 hw/arm/smmu-internal.h create mode 100644 hw/arm/smmuv3-internal.h create mode 100644 hw/arm/smmuv3.c create mode 100644 include/hw/arm/smmu-common.h create mode 100644 include/hw/arm/smmuv3.h -- 2.5.5 From MAILER-DAEMON Fri Aug 11 10:23:39 2017 Received: from list by lists.gnu.org with archive (Exim 4.71) id 1dgAqh-0008Os-3g for mharc-qemu-arm@gnu.org; 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dmarc=none (p=none dis=none) header.from=redhat.com Authentication-Results: ext-mx07.extmail.prod.ext.phx2.redhat.com; spf=fail smtp.mailfrom=eric.auger@redhat.com Received: from localhost.localdomain.com (ovpn-116-162.ams2.redhat.com [10.36.116.162]) by smtp.corp.redhat.com (Postfix) with ESMTP id CD382A01DB; Fri, 11 Aug 2017 14:23:19 +0000 (UTC) From: Eric Auger To: eric.auger.pro@gmail.com, eric.auger@redhat.com, peter.maydell@linaro.org, qemu-arm@nongnu.org, qemu-devel@nongnu.org, alex.williamson@redhat.com, prem.mallappa@gmail.com Cc: drjones@redhat.com, christoffer.dall@linaro.org, Radha.Chintakuntla@cavium.com, Sunil.Goutham@cavium.com, mohun106@gmail.com, tcain@qti.qualcomm.com, bharat.bhushan@nxp.com, tn@semihalf.com, mst@redhat.com, will.deacon@arm.com, jean-philippe.brucker@arm.com, robin.murphy@arm.com, peterx@redhat.com, edgar.iglesias@gmail.com Date: Fri, 11 Aug 2017 16:22:26 +0200 Message-Id: <1502461354-11327-2-git-send-email-eric.auger@redhat.com> In-Reply-To: <1502461354-11327-1-git-send-email-eric.auger@redhat.com> References: <1502461354-11327-1-git-send-email-eric.auger@redhat.com> X-Scanned-By: MIMEDefang 2.79 on 10.5.11.16 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.31]); Fri, 11 Aug 2017 14:23:29 +0000 (UTC) X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.132.183.28 Subject: [Qemu-arm] [RFC v6 1/9] hw/arm/smmu-common: smmu base class X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 11 Aug 2017 14:23:38 -0000 Introduces the base device and class for the ARM smmu. Implements VMSAv8-64 table lookup and translation. VMSAv8-32 is not implemented. Signed-off-by: Eric Auger Signed-off-by: Prem Mallappa --- v5 -> v6: - use IOMMUMemoryRegion - remove initial_lookup_level() - fix block replay v4 -> v5: - add initial level in translation config - implement block pte - rename must_translate into nofail - introduce call_entry_hook - small changes to dynamic traces - smmu_page_walk code moved from smmuv3.c to this file - remove smmu_translate* v3 -> v4: - reworked page table walk to prepare for VFIO integration (capability to scan a range of IOVA). Same function is used for translate for a single iova. This is largely inspired from intel_iommu.c - as the translate function was not straightforward to me, I tried to stick more closely to the VMSA spec. - remove support of nested stage (kernel driver does not support it anyway) - introduce smmu-internal.h to put page table definitions - added smmu_find_as_from_bus_num - SMMU_PCI_BUS_MAX and SMMU_PCI_DEVFN_MAX in smmu-common header - new fields in SMMUState: - iommu_ops, smmu_as_by_busptr, smmu_as_by_bus_num - use error_report and trace events - add aa64[] field in SMMUTransCfg v3: - moved the base code in a separate patch to ease the review. - clearer separation between base class and smmuv3 class - translate_* only implemented as class methods --- default-configs/aarch64-softmmu.mak | 1 + hw/arm/Makefile.objs | 1 + hw/arm/smmu-common.c | 493 ++++++++++++++++++++++++++++++++++++ hw/arm/smmu-internal.h | 89 +++++++ hw/arm/trace-events | 14 + include/hw/arm/smmu-common.h | 126 +++++++++ 6 files changed, 724 insertions(+) create mode 100644 hw/arm/smmu-common.c create mode 100644 hw/arm/smmu-internal.h create mode 100644 include/hw/arm/smmu-common.h diff --git a/default-configs/aarch64-softmmu.mak b/default-configs/aarch64-softmmu.mak index 2449483..83a2932 100644 --- a/default-configs/aarch64-softmmu.mak +++ b/default-configs/aarch64-softmmu.mak @@ -7,3 +7,4 @@ CONFIG_AUX=y CONFIG_DDC=y CONFIG_DPCD=y CONFIG_XLNX_ZYNQMP=y +CONFIG_ARM_SMMUV3=y diff --git a/hw/arm/Makefile.objs b/hw/arm/Makefile.objs index a2e56ec..5b2d38d 100644 --- a/hw/arm/Makefile.objs +++ b/hw/arm/Makefile.objs @@ -19,3 +19,4 @@ obj-$(CONFIG_FSL_IMX31) += fsl-imx31.o kzm.o obj-$(CONFIG_FSL_IMX6) += fsl-imx6.o sabrelite.o obj-$(CONFIG_ASPEED_SOC) += aspeed_soc.o aspeed.o obj-$(CONFIG_MPS2) += mps2.o +obj-$(CONFIG_ARM_SMMUV3) += smmu-common.o diff --git a/hw/arm/smmu-common.c b/hw/arm/smmu-common.c new file mode 100644 index 0000000..02741c2 --- /dev/null +++ b/hw/arm/smmu-common.c @@ -0,0 +1,493 @@ +/* + * Copyright (C) 2014-2016 Broadcom Corporation + * Copyright (c) 2017 Red Hat, Inc. + * Written by Prem Mallappa, Eric Auger + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + * + * Author: Prem Mallappa + * + */ + +#include "qemu/osdep.h" +#include "sysemu/sysemu.h" +#include "exec/address-spaces.h" +#include "trace.h" +#include "exec/target_page.h" +#include "qom/cpu.h" + +#include "qemu/error-report.h" +#include "hw/arm/smmu-common.h" +#include "smmu-internal.h" + +inline MemTxResult smmu_read_sysmem(dma_addr_t addr, void *buf, dma_addr_t len, + bool secure) +{ + MemTxAttrs attrs = {.unspecified = 1, .secure = secure}; + + switch (len) { + case 4: + *(uint32_t *)buf = ldl_le_phys(&address_space_memory, addr); + break; + case 8: + *(uint64_t *)buf = ldq_le_phys(&address_space_memory, addr); + break; + default: + return address_space_rw(&address_space_memory, addr, + attrs, buf, len, false); + } + return MEMTX_OK; +} + +inline void +smmu_write_sysmem(dma_addr_t addr, void *buf, dma_addr_t len, bool secure) +{ + MemTxAttrs attrs = {.unspecified = 1, .secure = secure}; + + switch (len) { + case 4: + stl_le_phys(&address_space_memory, addr, *(uint32_t *)buf); + break; + case 8: + stq_le_phys(&address_space_memory, addr, *(uint64_t *)buf); + break; + default: + address_space_rw(&address_space_memory, addr, + attrs, buf, len, true); + } +} + +/*************************/ +/* VMSAv8-64 Translation */ +/*************************/ + +/** + * get_pte - Get the content of a page table entry located in + * @base_addr[@index] + */ +static uint64_t get_pte(dma_addr_t baseaddr, uint32_t index) +{ + uint64_t pte; + + if (smmu_read_sysmem(baseaddr + index * sizeof(pte), + &pte, sizeof(pte), false)) { + error_report("can't read pte at address=0x%"PRIx64, + baseaddr + index * sizeof(pte)); + pte = (uint64_t)-1; + return pte; + } + trace_smmu_get_pte(baseaddr, index, baseaddr + index * sizeof(pte), pte); + /* TODO: handle endianness */ + return pte; +} + +/* VMSAv8-64 Translation Table Format Descriptor Decoding */ + +#define PTE_ADDRESS(pte, shift) (extract64(pte, shift, 47 - shift) << shift) + +/** + * get_page_pte_address - returns the L3 descriptor output address, + * ie. the page frame + * ARM ARM spec: Figure D4-17 VMSAv8-64 level 3 descriptor format + */ +static inline hwaddr get_page_pte_address(uint64_t pte, int granule_sz) +{ + return PTE_ADDRESS(pte, granule_sz); +} + +/** + * get_table_pte_address - return table descriptor output address, + * ie. address of next level table + * ARM ARM Figure D4-16 VMSAv8-64 level0, level1, and level 2 descriptor formats + */ +static inline hwaddr get_table_pte_address(uint64_t pte, int granule_sz) +{ + return PTE_ADDRESS(pte, granule_sz); +} + +/** + * get_block_pte_address - return block descriptor output address and block size + * ARM ARM Figure D4-16 VMSAv8-64 level0, level1, and level 2 descriptor formats + */ +static hwaddr get_block_pte_address(uint64_t pte, int level, int granule_sz, + uint64_t *bsz) +{ + int n; + + switch (granule_sz) { + case 12: + if (level == 1) { + n = 30; + } else if (level == 2) { + n = 21; + } else { + goto error_out; + } + break; + case 14: + if (level == 2) { + n = 25; + } else { + goto error_out; + } + break; + case 16: + if (level == 2) { + n = 29; + } else { + goto error_out; + } + break; + default: + goto error_out; + } + *bsz = 1 << n; + return PTE_ADDRESS(pte, n); + +error_out: + + error_report("unexpected granule_sz=%d/level=%d for block pte", + granule_sz, level); + *bsz = 0; + return (hwaddr)-1; +} + +static int call_entry_hook(uint64_t iova, uint64_t mask, uint64_t gpa, + int perm, smmu_page_walk_hook hook_fn, void *private) +{ + IOMMUTLBEntry entry; + int ret; + + entry.target_as = &address_space_memory; + entry.iova = iova & mask; + entry.translated_addr = gpa; + entry.addr_mask = ~mask; + entry.perm = perm; + + ret = hook_fn(&entry, private); + if (ret) { + error_report("%s hook returned %d", __func__, ret); + } + return ret; +} + +/** + * smmu_page_walk_level_64 - Walk an IOVA range from a specific level + * @baseaddr: table base address corresponding to @level + * @level: level + * @cfg: translation config + * @start: end of the IOVA range + * @end: end of the IOVA range + * @hook_fn: the hook that to be called for each detected area + * @private: private data for the hook function + * @read: whether parent level has read permission + * @write: whether parent level has write permission + * @nofail: indicates whether each iova of the range + * must be translated or whether failure is allowed + * @notify_unmap: whether we should notify invalid entries + * + * Return 0 on success, < 0 on errors not related to translation + * process, > 1 on errors related to translation process (only + * if nofail is set) + */ +static int +smmu_page_walk_level_64(dma_addr_t baseaddr, int level, + SMMUTransCfg *cfg, uint64_t start, uint64_t end, + smmu_page_walk_hook hook_fn, void *private, + bool read, bool write, bool nofail, + bool notify_unmap) +{ + uint64_t subpage_size, subpage_mask, pte, iova = start; + bool read_cur, write_cur, entry_valid; + int ret, granule_sz, stage; + + granule_sz = cfg->granule_sz; + stage = cfg->stage; + subpage_size = 1ULL << level_shift(level, granule_sz); + subpage_mask = level_page_mask(level, granule_sz); + + trace_smmu_page_walk_level_in(level, baseaddr, granule_sz, + start, end, subpage_size); + + while (iova < end) { + dma_addr_t next_table_baseaddr; + uint64_t iova_next, pte_addr; + uint32_t offset; + + iova_next = (iova & subpage_mask) + subpage_size; + offset = iova_level_offset(iova, level, granule_sz); + pte_addr = baseaddr + offset * sizeof(pte); + pte = get_pte(baseaddr, offset); + + trace_smmu_page_walk_level(level, iova, subpage_size, + baseaddr, offset, pte); + + if (pte == (uint64_t)-1) { + if (nofail) { + return SMMU_TRANS_ERR_WALK_EXT_ABRT; + } + goto next; + } + if (is_invalid_pte(pte) || is_reserved_pte(pte, level)) { + trace_smmu_page_walk_level_res_invalid_pte(stage, level, baseaddr, + pte_addr, offset, pte); + if (nofail) { + return SMMU_TRANS_ERR_WALK_EXT_ABRT; + } + goto next; + } + + read_cur = read; /* TODO */ + write_cur = write; /* TODO */ + entry_valid = read_cur | write_cur; /* TODO */ + + if (is_page_pte(pte, level)) { + uint64_t gpa = get_page_pte_address(pte, granule_sz); + int perm = IOMMU_ACCESS_FLAG(read_cur, write_cur); + + trace_smmu_page_walk_level_page_pte(stage, level, iova, + baseaddr, pte_addr, pte, gpa); + if (!entry_valid && !notify_unmap) { + printf("%s entry_valid=%d notify_unmap=%d\n", __func__, + entry_valid, notify_unmap); + goto next; + } + ret = call_entry_hook(iova, subpage_mask, gpa, perm, + hook_fn, private); + if (ret) { + return ret; + } + goto next; + } + if (is_block_pte(pte, level)) { + size_t target_page_size = qemu_target_page_size();; + int perm = IOMMU_ACCESS_FLAG(read_cur, write_cur); + uint64_t block_size, top_iova; + hwaddr gpa, block_gpa; + + block_gpa = get_block_pte_address(pte, level, granule_sz, + &block_size); + + if (block_gpa == -1) { + if (nofail) { + return SMMU_TRANS_ERR_WALK_EXT_ABRT; + } else { + goto next; + } + } + trace_smmu_page_walk_level_block_pte(stage, level, baseaddr, + pte_addr, pte, iova, block_gpa, + (int)(block_size >> 20)); + + gpa = block_gpa + (iova & (block_size - 1)); + if ((block_gpa == gpa) && (end >= iova_next - 1)) { + ret = call_entry_hook(iova, ~(block_size - 1), block_gpa, + perm, hook_fn, private); + if (ret) { + return ret; + } + goto next; + } else { + top_iova = MIN(end, iova_next); + while (iova < top_iova) { + gpa = block_gpa + (iova & (block_size - 1)); + ret = call_entry_hook(iova, ~(target_page_size - 1), + gpa, perm, hook_fn, private); + if (ret) { + return ret; + } + iova += target_page_size; + } + } + } + if (level == 3) { + goto next; + } + /* table pte */ + next_table_baseaddr = get_table_pte_address(pte, granule_sz); + trace_smmu_page_walk_level_table_pte(stage, level, baseaddr, pte_addr, + pte, next_table_baseaddr); + ret = smmu_page_walk_level_64(next_table_baseaddr, level + 1, cfg, + iova, MIN(iova_next, end), + hook_fn, private, read_cur, write_cur, + nofail, notify_unmap); + if (!ret) { + return ret; + } + +next: + iova = iova_next; + } + + return SMMU_TRANS_ERR_NONE; +} + +/** + * smmu_page_walk_64 - walk a specific IOVA range from the initial + * lookup level, and call the hook for each valid entry + * + * @cfg: translation config + * @start: start of the IOVA range + * @end: end of the IOVA range + * @nofail: indicates whether each iova of the range + * must be translated or whether failure is allowed + * @hook_fn: the hook that to be called for each detected area + * @private: private data for the hook function + */ +static int +smmu_page_walk_64(SMMUTransCfg *cfg, uint64_t start, uint64_t end, + bool nofail, smmu_page_walk_hook hook_fn, + void *private) +{ + dma_addr_t ttbr; + int stage = cfg->stage; + uint64_t roof = MIN(end, (1ULL << (64 - cfg->tsz)) - 1); + + if (!hook_fn) { + return 0; + } + + ttbr = extract64(cfg->ttbr, 0, 48); + + trace_smmu_page_walk_64(stage, cfg->ttbr, cfg->initial_level, start, roof); + + return smmu_page_walk_level_64(ttbr, cfg->initial_level, cfg, start, roof, + hook_fn, private, + true /* read */, true /* write */, + nofail, false /* notify_unmap */); +} + +static int set_translated_address(IOMMUTLBEntry *entry, void *private) +{ + SMMUTransCfg *cfg = (SMMUTransCfg *)private; + size_t offset = cfg->input - entry->iova; + + cfg->output = entry->translated_addr + offset; + + trace_smmu_set_translated_address(cfg->input, cfg->output); + return 0; +} + +/** + * smmu_page_walk - Walk the page table for a given + * config and a given entry + * + * tlbe->iova must have been populated + */ +int smmu_page_walk(SMMUState *sys, SMMUTransCfg *cfg, + IOMMUTLBEntry *tlbe, bool is_write) +{ + uint32_t page_size = 0, perm = 0; + int ret = 0; + + trace_smmu_walk_pgtable(tlbe->iova, is_write); + + if (cfg->bypassed || cfg->disabled) { + return 0; + } + + cfg->input = tlbe->iova; + + if (cfg->aa64) { + ret = smmu_page_walk_64(cfg, cfg->input, cfg->input + 1, + true /* nofail */, + set_translated_address, cfg); + page_size = 1 << cfg->granule_sz; + } else { + error_report("VMSAv8-32 translation is not yet implemented"); + abort(); + } + + if (ret) { + error_report("PTW failed for iova=0x%"PRIx64" is_write=%d (%d)", + cfg->input, is_write, ret); + goto exit; + } + tlbe->translated_addr = cfg->output; + tlbe->addr_mask = page_size - 1; + tlbe->perm = perm; + + trace_smmu_walk_pgtable_out(tlbe->translated_addr, + tlbe->addr_mask, tlbe->perm); +exit: + return ret; +} + +/*************************/ +/* VMSAv8-32 Translation */ +/*************************/ + +static int +smmu_page_walk_32(SMMUTransCfg *cfg, uint64_t start, uint64_t end, + bool nofail, smmu_page_walk_hook hook_fn, + void *private) +{ + error_report("VMSAv8-32 translation is not yet implemented"); + abort(); +} + +/******************/ +/* Infrastructure */ +/******************/ + +SMMUPciBus *smmu_find_as_from_bus_num(SMMUState *s, uint8_t bus_num) +{ + SMMUPciBus *smmu_pci_bus = s->smmu_as_by_bus_num[bus_num]; + + if (!smmu_pci_bus) { + GHashTableIter iter; + + g_hash_table_iter_init(&iter, s->smmu_as_by_busptr); + while (g_hash_table_iter_next(&iter, NULL, (void **)&smmu_pci_bus)) { + if (pci_bus_num(smmu_pci_bus->bus) == bus_num) { + s->smmu_as_by_bus_num[bus_num] = smmu_pci_bus; + return smmu_pci_bus; + } + } + } + return smmu_pci_bus; +} + +static void smmu_base_instance_init(Object *obj) +{ + /* Nothing much to do here as of now */ +} + +static void smmu_base_class_init(ObjectClass *klass, void *data) +{ + SMMUBaseClass *sbc = SMMU_DEVICE_CLASS(klass); + + sbc->page_walk_64 = smmu_page_walk_64; + + sbc->page_walk_32 = smmu_page_walk_32; +} + +static const TypeInfo smmu_base_info = { + .name = TYPE_SMMU_DEV_BASE, + .parent = TYPE_SYS_BUS_DEVICE, + .instance_size = sizeof(SMMUState), + .instance_init = smmu_base_instance_init, + .class_data = NULL, + .class_size = sizeof(SMMUBaseClass), + .class_init = smmu_base_class_init, + .abstract = true, +}; + +static void smmu_base_register_types(void) +{ + type_register_static(&smmu_base_info); +} + +type_init(smmu_base_register_types) + diff --git a/hw/arm/smmu-internal.h b/hw/arm/smmu-internal.h new file mode 100644 index 0000000..3b1e222 --- /dev/null +++ b/hw/arm/smmu-internal.h @@ -0,0 +1,89 @@ +/* + * ARM SMMU support - Internal API + * + * Copyright (c) 2017 Red Hat, Inc. + * Written by Eric Auger + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#define ARM_LPAE_MAX_ADDR_BITS 48 +#define ARM_LPAE_MAX_LEVELS 4 + +/* Page table bits */ + +#ifndef HW_ARM_SMMU_INTERNAL_H +#define HW_ARM_SMMU_INTERNAL_H + +#define ARM_LPAE_PTE_TYPE_SHIFT 0 +#define ARM_LPAE_PTE_TYPE_MASK 0x3 + +#define ARM_LPAE_PTE_TYPE_BLOCK 1 +#define ARM_LPAE_PTE_TYPE_RESERVED 1 +#define ARM_LPAE_PTE_TYPE_TABLE 3 +#define ARM_LPAE_PTE_TYPE_PAGE 3 + +#define ARM_LPAE_PTE_VALID (1 << 0) + +static inline bool is_invalid_pte(uint64_t pte) +{ + return !(pte & ARM_LPAE_PTE_VALID); +} + +static inline bool is_reserved_pte(uint64_t pte, int level) +{ + return ((level == 3) && + ((pte & ARM_LPAE_PTE_TYPE_MASK) == ARM_LPAE_PTE_TYPE_RESERVED)); +} + +static inline bool is_block_pte(uint64_t pte, int level) +{ + return ((level < 3) && + ((pte & ARM_LPAE_PTE_TYPE_MASK) == ARM_LPAE_PTE_TYPE_BLOCK)); +} + +static inline bool is_table_pte(uint64_t pte, int level) +{ + return ((level < 3) && + ((pte & ARM_LPAE_PTE_TYPE_MASK) == ARM_LPAE_PTE_TYPE_TABLE)); +} + +static inline bool is_page_pte(uint64_t pte, int level) +{ + return ((level == 3) && + ((pte & ARM_LPAE_PTE_TYPE_MASK) == ARM_LPAE_PTE_TYPE_PAGE)); +} + +static inline int level_shift(int level, int granule_sz) +{ + return granule_sz + (3 - level) * (granule_sz - 3); +} + +static inline uint64_t level_page_mask(int level, int granule_sz) +{ + return ~((1ULL << level_shift(level, granule_sz)) - 1); +} + +/** + * TODO: handle the case where the level resolves less than + * granule_sz -3 IA bits. + */ +static inline +uint64_t iova_level_offset(uint64_t iova, int level, int granule_sz) +{ + return (iova >> level_shift(level, granule_sz)) & + ((1ULL << (granule_sz - 3)) - 1); +} + +#endif diff --git a/hw/arm/trace-events b/hw/arm/trace-events index 193063e..b371b4d 100644 --- a/hw/arm/trace-events +++ b/hw/arm/trace-events @@ -2,3 +2,17 @@ # hw/arm/virt-acpi-build.c virt_acpi_setup(void) "No fw cfg or ACPI disabled. Bailing out." + +# hw/arm/smmu-common.c + +smmu_page_walk_64(int stage, uint64_t baseaddr, int first_level, uint64_t start, uint64_t end) "stage=%d, baseaddr=0x%"PRIx64", first level=%d, start=0x%"PRIx64", end=0x%"PRIx64 +smmu_page_walk_level_in(int level, uint64_t baseaddr, int granule_sz, uint64_t start, uint64_t end, uint64_t subpage_size) "level=%d baseaddr=0x%"PRIx64" granule=%d, start=0x%"PRIx64" end=0x%"PRIx64", subpage_size=0x%lx" +smmu_page_walk_level(int level, uint64_t iova, size_t subpage_size, uint64_t baseaddr, uint32_t offset, uint64_t pte) "level=%d iova=0x%lx subpage_sz=0x%lx baseaddr=0x%"PRIx64" offset=%d => pte=0x%lx" +smmu_page_walk_level_res_invalid_pte(int stage, int level, uint64_t baseaddr, uint64_t pteaddr, uint32_t offset, uint64_t pte) "stage=%d level=%d base@=0x%"PRIx64" pte@=0x%"PRIx64" offset=%d pte=0x%lx" +smmu_page_walk_level_page_pte(int stage, int level, uint64_t iova, uint64_t baseaddr, uint64_t pteaddr, uint64_t pte, uint64_t address) "stage=%d level=%d iova=0x%"PRIx64" base@=0x%"PRIx64" pte@=0x%"PRIx64" pte=0x%"PRIx64" page address = 0x%"PRIx64 +smmu_page_walk_level_block_pte(int stage, int level, uint64_t baseaddr, uint64_t pteaddr, uint64_t pte, uint64_t iova, uint64_t gpa, int bsize_mb) "stage=%d level=%d base@=0x%"PRIx64" pte@=0x%"PRIx64" pte=0x%"PRIx64" iova=0x%"PRIx64" block address = 0x%"PRIx64" block size = %d MiB" +smmu_page_walk_level_table_pte(int stage, int level, uint64_t baseaddr, uint64_t pteaddr, uint64_t pte, uint64_t address) "stage=%d, level=%d base@=0x%"PRIx64" pte@=0x%"PRIx64" pte=0x%"PRIx64" next table address = 0x%"PRIx64 +smmu_get_pte(uint64_t baseaddr, int index, uint64_t pteaddr, uint64_t pte) "baseaddr=0x%"PRIx64" index=0x%x, pteaddr=0x%"PRIx64", pte=0x%"PRIx64 +smmu_set_translated_address(hwaddr iova, hwaddr pa) "iova = 0x%"PRIx64" -> pa = 0x%"PRIx64 +smmu_walk_pgtable(hwaddr iova, bool is_write) "Input addr: 0x%"PRIx64", is_write=%d" +smmu_walk_pgtable_out(hwaddr addr, uint32_t mask, int perm) "DONE: o/p addr:0x%"PRIx64" mask:0x%x perm:%d" diff --git a/include/hw/arm/smmu-common.h b/include/hw/arm/smmu-common.h new file mode 100644 index 0000000..ea20a78 --- /dev/null +++ b/include/hw/arm/smmu-common.h @@ -0,0 +1,126 @@ +/* + * ARM SMMU Support + * + * Copyright (C) 2015-2016 Broadcom Corporation + * Copyright (c) 2017 Red Hat, Inc. + * Written by Prem Mallappa, Eric Auger + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#ifndef HW_ARM_SMMU_COMMON_H +#define HW_ARM_SMMU_COMMON_H + +#include +#include "hw/pci/pci.h" + +#define SMMU_PCI_BUS_MAX 256 +#define SMMU_PCI_DEVFN_MAX 256 + +typedef enum { + SMMU_TRANS_ERR_NONE = 0x0, + SMMU_TRANS_ERR_WALK_EXT_ABRT = 0x1, /* Translation walk external abort */ + SMMU_TRANS_ERR_TRANS = 0x10, /* Translation fault */ + SMMU_TRANS_ERR_ADDR_SZ, /* Address Size fault */ + SMMU_TRANS_ERR_ACCESS, /* Access fault */ + SMMU_TRANS_ERR_PERM, /* Permission fault */ + SMMU_TRANS_ERR_TLB_CONFLICT = 0x20, /* TLB Conflict */ +} SMMUTransErr; + +/* + * Generic structure populated by derived SMMU devices + * after decoding the configuration information and used as + * input to the page table walk + */ +typedef struct SMMUTransCfg { + hwaddr input; /* input address */ + hwaddr output; /* Output address */ + int stage; /* translation stage */ + uint32_t oas; /* output address width */ + uint32_t tsz; /* input range, ie. 2^(64 -tnsz)*/ + uint64_t ttbr; /* TTBR address */ + uint32_t granule_sz; /* granule page shift */ + bool aa64; /* arch64 or aarch32 translation table */ + int initial_level; /* initial lookup level */ + bool disabled; /* smmu is disabled */ + bool bypassed; /* stage is bypassed */ +} SMMUTransCfg; + +typedef struct SMMUDevice { + void *smmu; + PCIBus *bus; + int devfn; + IOMMUMemoryRegion iommu; + AddressSpace as; +} SMMUDevice; + +typedef struct SMMUNotifierNode { + SMMUDevice *sdev; + QLIST_ENTRY(SMMUNotifierNode) next; +} SMMUNotifierNode; + +typedef struct SMMUPciBus { + PCIBus *bus; + SMMUDevice *pbdev[0]; /* Parent array is sparse, so dynamically alloc */ +} SMMUPciBus; + +typedef struct SMMUState { + /* */ + SysBusDevice dev; + + MemoryRegion iomem; + + GHashTable *smmu_as_by_busptr; + SMMUPciBus *smmu_as_by_bus_num[SMMU_PCI_BUS_MAX]; + QLIST_HEAD(, SMMUNotifierNode) notifiers_list; + +} SMMUState; + +typedef int (*smmu_page_walk_hook)(IOMMUTLBEntry *entry, void *private); + +typedef struct { + /* */ + SysBusDeviceClass parent_class; + + /* public */ + int (*page_walk_32)(SMMUTransCfg *cfg, uint64_t start, uint64_t end, + bool nofail, smmu_page_walk_hook hook_fn, + void *private); + int (*page_walk_64)(SMMUTransCfg *cfg, uint64_t start, uint64_t end, + bool nofail, smmu_page_walk_hook hook_fn, + void *private); +} SMMUBaseClass; + +#define TYPE_SMMU_DEV_BASE "smmu-base" +#define SMMU_SYS_DEV(obj) OBJECT_CHECK(SMMUState, (obj), TYPE_SMMU_DEV_BASE) +#define SMMU_DEVICE_GET_CLASS(obj) \ + OBJECT_GET_CLASS(SMMUBaseClass, (obj), TYPE_SMMU_DEV_BASE) +#define SMMU_DEVICE_CLASS(klass) \ + OBJECT_CLASS_CHECK(SMMUBaseClass, (klass), TYPE_SMMU_DEV_BASE) + +MemTxResult smmu_read_sysmem(dma_addr_t addr, void *buf, + dma_addr_t len, bool secure); +void smmu_write_sysmem(dma_addr_t addr, void *buf, dma_addr_t len, bool secure); + +SMMUPciBus *smmu_find_as_from_bus_num(SMMUState *s, uint8_t bus_num); + +static inline uint16_t smmu_get_sid(SMMUDevice *sdev) +{ + return ((pci_bus_num(sdev->bus) & 0xff) << 8) | sdev->devfn; +} + +int smmu_page_walk(SMMUState *s, SMMUTransCfg *cfg, + IOMMUTLBEntry *tlbe, bool is_write); + +#endif /* HW_ARM_SMMU_COMMON */ -- 2.5.5 From MAILER-DAEMON Fri Aug 11 10:24:02 2017 Received: from list by lists.gnu.org with archive (Exim 4.71) id 1dgAr4-0000GD-8f for mharc-qemu-arm@gnu.org; Fri, 11 Aug 2017 10:24:02 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:34249) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dgAqv-00007s-QA for qemu-arm@nongnu.org; Fri, 11 Aug 2017 10:24:00 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dgAqp-00022m-W2 for qemu-arm@nongnu.org; Fri, 11 Aug 2017 10:23:53 -0400 Received: from mx1.redhat.com ([209.132.183.28]:41394) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1dgAqp-00022J-FE; Fri, 11 Aug 2017 10:23:47 -0400 Received: from smtp.corp.redhat.com (int-mx06.intmail.prod.int.phx2.redhat.com [10.5.11.16]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id 48B83C553A; Fri, 11 Aug 2017 14:23:46 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mx1.redhat.com 48B83C553A Authentication-Results: ext-mx01.extmail.prod.ext.phx2.redhat.com; dmarc=none (p=none dis=none) header.from=redhat.com Authentication-Results: ext-mx01.extmail.prod.ext.phx2.redhat.com; spf=fail smtp.mailfrom=eric.auger@redhat.com Received: from localhost.localdomain.com (ovpn-116-162.ams2.redhat.com [10.36.116.162]) by smtp.corp.redhat.com (Postfix) with ESMTP id 19BD1A21B1; Fri, 11 Aug 2017 14:23:28 +0000 (UTC) From: Eric Auger To: eric.auger.pro@gmail.com, eric.auger@redhat.com, peter.maydell@linaro.org, qemu-arm@nongnu.org, qemu-devel@nongnu.org, alex.williamson@redhat.com, prem.mallappa@gmail.com Cc: drjones@redhat.com, christoffer.dall@linaro.org, Radha.Chintakuntla@cavium.com, Sunil.Goutham@cavium.com, mohun106@gmail.com, tcain@qti.qualcomm.com, bharat.bhushan@nxp.com, tn@semihalf.com, mst@redhat.com, will.deacon@arm.com, jean-philippe.brucker@arm.com, robin.murphy@arm.com, peterx@redhat.com, edgar.iglesias@gmail.com Date: Fri, 11 Aug 2017 16:22:27 +0200 Message-Id: <1502461354-11327-3-git-send-email-eric.auger@redhat.com> In-Reply-To: <1502461354-11327-1-git-send-email-eric.auger@redhat.com> References: <1502461354-11327-1-git-send-email-eric.auger@redhat.com> X-Scanned-By: MIMEDefang 2.79 on 10.5.11.16 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.25]); Fri, 11 Aug 2017 14:23:46 +0000 (UTC) X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.132.183.28 Subject: [Qemu-arm] [RFC v6 2/9] hw/arm/smmuv3: smmuv3 emulation model X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 11 Aug 2017 14:24:00 -0000 From: Prem Mallappa Introduces the SMMUv3 derived model. This is based on System MMUv3 specification (v17). Signed-off-by: Prem Mallappa Signed-off-by: Eric Auger --- v5 -> v6: - Use IOMMUMemoryregion - regs become uint32_t and fix 64b MMIO access (.impl) - trace_smmuv3_write/read_mmio take the size param v4 -> v5: - change smmuv3_translate proto (IOMMUAccessFlags flag) - has_stagex replaced by is_ste_stagex - smmu_cfg_populate removed - added smmuv3_decode_config and reworked error management - remwork the naming of IOMMU mrs - fix SMMU_CMDQ_CONS offset v3 -> v4 - smmu_irq_update - fix hash key allocation - set smmu_iommu_ops - set SMMU_REG_CR0, - smmuv3_translate: ret.perm not set in bypass mode - use trace events - renamed STM2U64 into L1STD_L2PTR and STMSPAN into L1STD_SPAN - rework smmu_find_ste - fix tg2granule in TT0/0b10 corresponds to 16kB v2 -> v3: - move creation of include/hw/arm/smmuv3.h to this patch to fix compil issue - compilation allowed - fix sbus allocation in smmu_init_pci_iommu - restructure code into headers - misc cleanups --- hw/arm/Makefile.objs | 2 +- hw/arm/smmuv3-internal.h | 651 ++++++++++++++++++++++++++ hw/arm/smmuv3.c | 1152 ++++++++++++++++++++++++++++++++++++++++++++++ hw/arm/trace-events | 34 ++ include/hw/arm/smmuv3.h | 89 ++++ 5 files changed, 1927 insertions(+), 1 deletion(-) create mode 100644 hw/arm/smmuv3-internal.h create mode 100644 hw/arm/smmuv3.c create mode 100644 include/hw/arm/smmuv3.h diff --git a/hw/arm/Makefile.objs b/hw/arm/Makefile.objs index 5b2d38d..a7c808b 100644 --- a/hw/arm/Makefile.objs +++ b/hw/arm/Makefile.objs @@ -19,4 +19,4 @@ obj-$(CONFIG_FSL_IMX31) += fsl-imx31.o kzm.o obj-$(CONFIG_FSL_IMX6) += fsl-imx6.o sabrelite.o obj-$(CONFIG_ASPEED_SOC) += aspeed_soc.o aspeed.o obj-$(CONFIG_MPS2) += mps2.o -obj-$(CONFIG_ARM_SMMUV3) += smmu-common.o +obj-$(CONFIG_ARM_SMMUV3) += smmu-common.o smmuv3.o diff --git a/hw/arm/smmuv3-internal.h b/hw/arm/smmuv3-internal.h new file mode 100644 index 0000000..e255df1 --- /dev/null +++ b/hw/arm/smmuv3-internal.h @@ -0,0 +1,651 @@ +/* + * ARM SMMUv3 support - Internal API + * + * Copyright (C) 2014-2016 Broadcom Corporation + * Copyright (c) 2017 Red Hat, Inc. + * Written by Prem Mallappa, Eric Auger + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#ifndef HW_ARM_SMMU_V3_INTERNAL_H +#define HW_ARM_SMMU_V3_INTERNAL_H + +#include "trace.h" +#include "qemu/error-report.h" +#include "hw/arm/smmu-common.h" + +/***************************** + * MMIO Register + *****************************/ +enum { + SMMU_REG_IDR0 = 0x0, + +/* IDR0 Field Values and supported features */ + +#define SMMU_IDR0_S2P 1 /* stage 2 */ +#define SMMU_IDR0_S1P 1 /* stage 1 */ +#define SMMU_IDR0_TTF 2 /* Aarch64 only - not Aarch32 (LPAE) */ +#define SMMU_IDR0_COHACC 1 /* IO coherent access */ +#define SMMU_IDR0_HTTU 2 /* Access and Dirty flag update */ +#define SMMU_IDR0_HYP 0 /* Hypervisor Stage 1 contexts */ +#define SMMU_IDR0_ATS 0 /* PCIe RC ATS */ +#define SMMU_IDR0_ASID16 1 /* 16-bit ASID */ +#define SMMU_IDR0_PRI 0 /* Page Request Interface */ +#define SMMU_IDR0_VMID16 0 /* 16-bit VMID */ +#define SMMU_IDR0_CD2L 0 /* 2-level Context Descriptor table */ +#define SMMU_IDR0_STALL 1 /* Stalling fault model */ +#define SMMU_IDR0_TERM 1 /* Termination model behaviour */ +#define SMMU_IDR0_STLEVEL 1 /* Multi-level Stream Table */ + +#define SMMU_IDR0_S2P_SHIFT 0 +#define SMMU_IDR0_S1P_SHIFT 1 +#define SMMU_IDR0_TTF_SHIFT 2 +#define SMMU_IDR0_COHACC_SHIFT 4 +#define SMMU_IDR0_HTTU_SHIFT 6 +#define SMMU_IDR0_HYP_SHIFT 9 +#define SMMU_IDR0_ATS_SHIFT 10 +#define SMMU_IDR0_ASID16_SHIFT 12 +#define SMMU_IDR0_PRI_SHIFT 16 +#define SMMU_IDR0_VMID16_SHIFT 18 +#define SMMU_IDR0_CD2L_SHIFT 19 +#define SMMU_IDR0_STALL_SHIFT 24 +#define SMMU_IDR0_TERM_SHIFT 26 +#define SMMU_IDR0_STLEVEL_SHIFT 27 + + SMMU_REG_IDR1 = 0x4, +#define SMMU_IDR1_SIDSIZE 16 + SMMU_REG_IDR2 = 0x8, + SMMU_REG_IDR3 = 0xc, + SMMU_REG_IDR4 = 0x10, + SMMU_REG_IDR5 = 0x14, +#define SMMU_IDR5_GRAN_SHIFT 4 +#define SMMU_IDR5_GRAN 0b101 /* GRAN4K, GRAN64K */ +#define SMMU_IDR5_OAS 4 /* 44 bits */ + SMMU_REG_IIDR = 0x1c, + SMMU_REG_CR0 = 0x20, + +#define SMMU_CR0_SMMU_ENABLE (1 << 0) +#define SMMU_CR0_PRIQ_ENABLE (1 << 1) +#define SMMU_CR0_EVTQ_ENABLE (1 << 2) +#define SMMU_CR0_CMDQ_ENABLE (1 << 3) +#define SMMU_CR0_ATS_CHECK (1 << 4) + + SMMU_REG_CR0_ACK = 0x24, + SMMU_REG_CR1 = 0x28, + SMMU_REG_CR2 = 0x2c, + + SMMU_REG_STATUSR = 0x40, + + SMMU_REG_IRQ_CTRL = 0x50, + SMMU_REG_IRQ_CTRL_ACK = 0x54, + +#define SMMU_IRQ_CTRL_GERROR_EN (1 << 0) +#define SMMU_IRQ_CTRL_EVENT_EN (1 << 1) +#define SMMU_IRQ_CTRL_PRI_EN (1 << 2) + + SMMU_REG_GERROR = 0x60, + +#define SMMU_GERROR_CMDQ (1 << 0) +#define SMMU_GERROR_EVENTQ (1 << 2) +#define SMMU_GERROR_PRIQ (1 << 3) +#define SMMU_GERROR_MSI_CMDQ (1 << 4) +#define SMMU_GERROR_MSI_EVENTQ (1 << 5) +#define SMMU_GERROR_MSI_PRIQ (1 << 6) +#define SMMU_GERROR_MSI_GERROR (1 << 7) +#define SMMU_GERROR_SFM_ERR (1 << 8) + + SMMU_REG_GERRORN = 0x64, + SMMU_REG_GERROR_IRQ_CFG0 = 0x68, + SMMU_REG_GERROR_IRQ_CFG1 = 0x70, + SMMU_REG_GERROR_IRQ_CFG2 = 0x74, + + /* SMMU_BASE_RA Applies to STRTAB_BASE, CMDQ_BASE and EVTQ_BASE */ +#define SMMU_BASE_RA (1ULL << 62) + SMMU_REG_STRTAB_BASE = 0x80, + SMMU_REG_STRTAB_BASE_CFG = 0x88, + + SMMU_REG_CMDQ_BASE = 0x90, + SMMU_REG_CMDQ_PROD = 0x98, + SMMU_REG_CMDQ_CONS = 0x9c, + /* CMD Consumer (CONS) */ +#define SMMU_CMD_CONS_ERR_SHIFT 24 +#define SMMU_CMD_CONS_ERR_BITS 7 + + SMMU_REG_EVTQ_BASE = 0xa0, + SMMU_REG_EVTQ_PROD = 0xa8, + SMMU_REG_EVTQ_CONS = 0xac, + SMMU_REG_EVTQ_IRQ_CFG0 = 0xb0, + SMMU_REG_EVTQ_IRQ_CFG1 = 0xb8, + SMMU_REG_EVTQ_IRQ_CFG2 = 0xbc, + + SMMU_REG_PRIQ_BASE = 0xc0, + SMMU_REG_PRIQ_PROD = 0xc8, + SMMU_REG_PRIQ_CONS = 0xcc, + SMMU_REG_PRIQ_IRQ_CFG0 = 0xd0, + SMMU_REG_PRIQ_IRQ_CFG1 = 0xd8, + SMMU_REG_PRIQ_IRQ_CFG2 = 0xdc, + + SMMU_ID_REGS_OFFSET = 0xfd0, + + /* Secure registers are not used for now */ + SMMU_SECURE_OFFSET = 0x8000, +}; + +/********************** + * Data Structures + **********************/ + +struct __smmu_data2 { + uint32_t word[2]; +}; + +struct __smmu_data8 { + uint32_t word[8]; +}; + +struct __smmu_data16 { + uint32_t word[16]; +}; + +struct __smmu_data4 { + uint32_t word[4]; +}; + +typedef struct __smmu_data2 STEDesc; /* STE Level 1 Descriptor */ +typedef struct __smmu_data16 Ste; /* Stream Table Entry(STE) */ +typedef struct __smmu_data2 CDDesc; /* CD Level 1 Descriptor */ +typedef struct __smmu_data16 Cd; /* Context Descriptor(CD) */ + +typedef struct __smmu_data4 Cmd; /* Command Entry */ +typedef struct __smmu_data8 Evt; /* Event Entry */ +typedef struct __smmu_data4 Pri; /* PRI entry */ + +/***************************** + * STE fields + *****************************/ + +#define STE_VALID(x) extract32((x)->word[0], 0, 1) /* 0 */ +#define STE_CONFIG(x) extract32((x)->word[0], 1, 3) +enum { + STE_CONFIG_NONE = 0, + STE_CONFIG_BYPASS = 4, /* S1 Bypass , S2 Bypass */ + STE_CONFIG_S1 = 5, /* S1 Translate , S2 Bypass */ + STE_CONFIG_S2 = 6, /* S1 Bypass , S2 Translate */ + STE_CONFIG_NESTED = 7, /* S1 Translate , S2 Translate */ +}; +#define STE_S1FMT(x) extract32((x)->word[0], 4, 2) +#define STE_S1CDMAX(x) extract32((x)->word[1], 27, 5) +#define STE_EATS(x) extract32((x)->word[2], 28, 2) +#define STE_STRW(x) extract32((x)->word[2], 30, 2) +#define STE_S2VMID(x) extract32((x)->word[4], 0, 16) +#define STE_S2T0SZ(x) extract32((x)->word[5], 0, 6) +#define STE_S2SL0(x) extract32((x)->word[5], 6, 2) +#define STE_S2TG(x) extract32((x)->word[5], 14, 2) +#define STE_S2PS(x) extract32((x)->word[5], 16, 3) +#define STE_S2AA64(x) extract32((x)->word[5], 19, 1) +#define STE_S2HD(x) extract32((x)->word[5], 24, 1) +#define STE_S2HA(x) extract32((x)->word[5], 25, 1) +#define STE_S2S(x) extract32((x)->word[5], 26, 1) +#define STE_CTXPTR(x) \ + ({ \ + unsigned long addr; \ + addr = (uint64_t)extract32((x)->word[1], 0, 16) << 32; \ + addr |= (uint64_t)((x)->word[0] & 0xffffffc0); \ + addr; \ + }) + +#define STE_S2TTB(x) \ + ({ \ + unsigned long addr; \ + addr = (uint64_t)extract32((x)->word[7], 0, 16) << 32; \ + addr |= (uint64_t)((x)->word[6] & 0xfffffff0); \ + addr; \ + }) + +static inline int is_ste_bypass(Ste *ste) +{ + return STE_CONFIG(ste) == STE_CONFIG_BYPASS; +} + +static inline bool is_ste_stage1(Ste *ste) +{ + return STE_CONFIG(ste) == STE_CONFIG_S1; +} + +static inline bool is_ste_stage2(Ste *ste) +{ + return STE_CONFIG(ste) == STE_CONFIG_S2; +} + +/** + * is_s2granule_valid - Check the stage 2 translation granule size + * advertised in the STE matches any IDR5 supported value + */ +static inline bool is_s2granule_valid(Ste *ste) +{ + int idr5_format = 0; + + switch (STE_S2TG(ste)) { + case 0: /* 4kB */ + idr5_format = 0x1; + break; + case 1: /* 64 kB */ + idr5_format = 0x4; + break; + case 2: /* 16 kB */ + idr5_format = 0x2; + break; + case 3: /* reserved */ + break; + } + idr5_format &= SMMU_IDR5_GRAN; + return idr5_format; +} + +static inline int oas2bits(int oas_field) +{ + switch (oas_field) { + case 0b011: + return 42; + case 0b100: + return 44; + default: + return 32 + (1 << oas_field); + } +} + +static inline int pa_range(Ste *ste) +{ + int oas_field = MIN(STE_S2PS(ste), SMMU_IDR5_OAS); + + if (!STE_S2AA64(ste)) { + return 40; + } + + return oas2bits(oas_field); +} + +#define MAX_PA(ste) ((1 << pa_range(ste)) - 1) + +/***************************** + * CD fields + *****************************/ +#define CD_VALID(x) extract32((x)->word[0], 30, 1) +#define CD_ASID(x) extract32((x)->word[1], 16, 16) +#define CD_TTB(x, sel) \ + ({ \ + uint64_t hi, lo; \ + hi = extract32((x)->word[(sel) * 2 + 3], 0, 16); \ + hi <<= 32; \ + lo = (x)->word[(sel) * 2 + 2] & ~0xf; \ + hi | lo; \ + }) + +#define CD_TSZ(x, sel) extract32((x)->word[0], (16 * (sel)) + 0, 6) +#define CD_TG(x, sel) extract32((x)->word[0], (16 * (sel)) + 6, 2) +#define CD_EPD(x, sel) extract32((x)->word[0], (16 * (sel)) + 14, 1) + +#define CD_T0SZ(x) CD_TSZ((x), 0) +#define CD_T1SZ(x) CD_TSZ((x), 1) +#define CD_TG0(x) CD_TG((x), 0) +#define CD_TG1(x) CD_TG((x), 1) +#define CD_EPD0(x) CD_EPD((x), 0) +#define CD_EPD1(x) CD_EPD((x), 1) +#define CD_IPS(x) extract32((x)->word[1], 0, 3) +#define CD_AARCH64(x) extract32((x)->word[1], 9, 1) +#define CD_TTB0(x) CD_TTB((x), 0) +#define CD_TTB1(x) CD_TTB((x), 1) + +#define CDM_VALID(x) ((x)->word[0] & 0x1) + +static inline int is_cd_valid(SMMUV3State *s, Ste *ste, Cd *cd) +{ + return CD_VALID(cd); +} + +/***************************** + * Commands + *****************************/ +enum { + SMMU_CMD_PREFETCH_CONFIG = 0x01, + SMMU_CMD_PREFETCH_ADDR, + SMMU_CMD_CFGI_STE, + SMMU_CMD_CFGI_STE_RANGE, + SMMU_CMD_CFGI_CD, + SMMU_CMD_CFGI_CD_ALL, + SMMU_CMD_CFGI_ALL, + SMMU_CMD_TLBI_NH_ALL = 0x10, + SMMU_CMD_TLBI_NH_ASID, + SMMU_CMD_TLBI_NH_VA, + SMMU_CMD_TLBI_NH_VAA, + SMMU_CMD_TLBI_EL3_ALL = 0x18, + SMMU_CMD_TLBI_EL3_VA = 0x1a, + SMMU_CMD_TLBI_EL2_ALL = 0x20, + SMMU_CMD_TLBI_EL2_ASID, + SMMU_CMD_TLBI_EL2_VA, + SMMU_CMD_TLBI_EL2_VAA, /* 0x23 */ + SMMU_CMD_TLBI_S12_VMALL = 0x28, + SMMU_CMD_TLBI_S2_IPA = 0x2a, + SMMU_CMD_TLBI_NSNH_ALL = 0x30, + SMMU_CMD_ATC_INV = 0x40, + SMMU_CMD_PRI_RESP, + SMMU_CMD_RESUME = 0x44, + SMMU_CMD_STALL_TERM, + SMMU_CMD_SYNC, /* 0x46 */ +}; + +static const char *cmd_stringify[] = { + [SMMU_CMD_PREFETCH_CONFIG] = "SMMU_CMD_PREFETCH_CONFIG", + [SMMU_CMD_PREFETCH_ADDR] = "SMMU_CMD_PREFETCH_ADDR", + [SMMU_CMD_CFGI_STE] = "SMMU_CMD_CFGI_STE", + [SMMU_CMD_CFGI_STE_RANGE] = "SMMU_CMD_CFGI_STE_RANGE", + [SMMU_CMD_CFGI_CD] = "SMMU_CMD_CFGI_CD", + [SMMU_CMD_CFGI_CD_ALL] = "SMMU_CMD_CFGI_CD_ALL", + [SMMU_CMD_CFGI_ALL] = "SMMU_CMD_CFGI_ALL", + [SMMU_CMD_TLBI_NH_ALL] = "SMMU_CMD_TLBI_NH_ALL", + [SMMU_CMD_TLBI_NH_ASID] = "SMMU_CMD_TLBI_NH_ASID", + [SMMU_CMD_TLBI_NH_VA] = "SMMU_CMD_TLBI_NH_VA", + [SMMU_CMD_TLBI_NH_VAA] = "SMMU_CMD_TLBI_NH_VAA", + [SMMU_CMD_TLBI_EL3_ALL] = "SMMU_CMD_TLBI_EL3_ALL", + [SMMU_CMD_TLBI_EL3_VA] = "SMMU_CMD_TLBI_EL3_VA", + [SMMU_CMD_TLBI_EL2_ALL] = "SMMU_CMD_TLBI_EL2_ALL", + [SMMU_CMD_TLBI_EL2_ASID] = "SMMU_CMD_TLBI_EL2_ASID", + [SMMU_CMD_TLBI_EL2_VA] = "SMMU_CMD_TLBI_EL2_VA", + [SMMU_CMD_TLBI_EL2_VAA] = "SMMU_CMD_TLBI_EL2_VAA", + [SMMU_CMD_TLBI_S12_VMALL] = "SMMU_CMD_TLBI_S12_VMALL", + [SMMU_CMD_TLBI_S2_IPA] = "SMMU_CMD_TLBI_S2_IPA", + [SMMU_CMD_TLBI_NSNH_ALL] = "SMMU_CMD_TLBI_NSNH_ALL", + [SMMU_CMD_ATC_INV] = "SMMU_CMD_ATC_INV", + [SMMU_CMD_PRI_RESP] = "SMMU_CMD_PRI_RESP", + [SMMU_CMD_RESUME] = "SMMU_CMD_RESUME", + [SMMU_CMD_STALL_TERM] = "SMMU_CMD_STALL_TERM", + [SMMU_CMD_SYNC] = "SMMU_CMD_SYNC", +}; + +/***************************** + * Register Access Primitives + *****************************/ + +static inline void smmu_write64_reg(SMMUV3State *s, uint32_t addr, uint64_t val) +{ + addr >>= 2; + s->regs[addr] = extract64(val, 0, 32); + s->regs[addr + 1] = extract64(val, 32, 32); +} + +static inline void smmu_write_reg(SMMUV3State *s, uint32_t addr, uint64_t val) +{ + s->regs[addr >> 2] = val; +} + +static inline uint32_t smmu_read_reg(SMMUV3State *s, uint32_t addr) +{ + return s->regs[addr >> 2]; +} + +static inline uint64_t smmu_read64_reg(SMMUV3State *s, uint32_t addr) +{ + addr >>= 2; + return s->regs[addr] | ((uint64_t)(s->regs[addr + 1]) << 32); +} + +#define smmu_read32_reg smmu_read_reg +#define smmu_write32_reg smmu_write_reg + +/***************************** + * CMDQ fields + *****************************/ + +enum { /* Command Errors */ + SMMU_CMD_ERR_NONE = 0, + SMMU_CMD_ERR_ILLEGAL, + SMMU_CMD_ERR_ABORT +}; + +enum { /* Command completion notification */ + CMD_SYNC_SIG_NONE, + CMD_SYNC_SIG_IRQ, + CMD_SYNC_SIG_SEV, +}; + +#define CMD_TYPE(x) extract32((x)->word[0], 0, 8) +#define CMD_SEC(x) extract32((x)->word[0], 9, 1) +#define CMD_SEV(x) extract32((x)->word[0], 10, 1) +#define CMD_AC(x) extract32((x)->word[0], 12, 1) +#define CMD_AB(x) extract32((x)->word[0], 13, 1) +#define CMD_CS(x) extract32((x)->word[0], 12, 2) +#define CMD_SSID(x) extract32((x)->word[0], 16, 16) +#define CMD_SID(x) ((x)->word[1]) +#define CMD_VMID(x) extract32((x)->word[1], 0, 16) +#define CMD_ASID(x) extract32((x)->word[1], 16, 16) +#define CMD_STAG(x) extract32((x)->word[2], 0, 16) +#define CMD_RESP(x) extract32((x)->word[2], 11, 2) +#define CMD_GRPID(x) extract32((x)->word[3], 0, 8) +#define CMD_SIZE(x) extract32((x)->word[3], 0, 16) +#define CMD_LEAF(x) extract32((x)->word[3], 0, 1) +#define CMD_SPAN(x) extract32((x)->word[3], 0, 5) +#define CMD_ADDR(x) ({ \ + uint64_t addr = (uint64_t)(x)->word[3]; \ + addr <<= 32; \ + addr |= extract32((x)->word[3], 12, 20); \ + addr; \ + }) + +/*************************** + * Queue Handling + ***************************/ + +typedef enum { + CMD_Q_EMPTY, + CMD_Q_FULL, + CMD_Q_INUSE, +} SMMUQStatus; + +#define Q_ENTRY(q, idx) (q->base + q->ent_size * idx) +#define Q_WRAP(q, pc) ((pc) >> (q)->shift) +#define Q_IDX(q, pc) ((pc) & ((1 << (q)->shift) - 1)) + +static inline SMMUQStatus __smmu_queue_status(SMMUV3State *s, SMMUQueue *q) +{ + uint32_t prod = Q_IDX(q, q->prod); + uint32_t cons = Q_IDX(q, q->cons); + + if ((prod == cons) && (q->wrap.prod != q->wrap.cons)) { + return CMD_Q_FULL; + } else if ((prod == cons) && (q->wrap.prod == q->wrap.cons)) { + return CMD_Q_EMPTY; + } + return CMD_Q_INUSE; +} +#define smmu_is_q_full(s, q) (__smmu_queue_status(s, q) == CMD_Q_FULL) +#define smmu_is_q_empty(s, q) (__smmu_queue_status(s, q) == CMD_Q_EMPTY) + +static inline int __smmu_q_enabled(SMMUV3State *s, uint32_t q) +{ + return smmu_read32_reg(s, SMMU_REG_CR0) & q; +} +#define smmu_cmd_q_enabled(s) __smmu_q_enabled(s, SMMU_CR0_CMDQ_ENABLE) +#define smmu_evt_q_enabled(s) __smmu_q_enabled(s, SMMU_CR0_EVTQ_ENABLE) + +#define SMMU_CMDQ_ERR(s) ((smmu_read32_reg(s, SMMU_REG_GERROR) ^ \ + smmu_read32_reg(s, SMMU_REG_GERRORN)) & \ + SMMU_GERROR_CMDQ) + +static inline void smmuv3_init_queues(SMMUV3State *s) +{ + s->cmdq.prod = 0; + s->cmdq.cons = 0; + s->cmdq.wrap.prod = 0; + s->cmdq.wrap.cons = 0; + + s->evtq.prod = 0; + s->evtq.cons = 0; + s->evtq.wrap.prod = 0; + s->evtq.wrap.cons = 0; + + s->priq.prod = 0; + s->priq.cons = 0; + s->priq.wrap.prod = 0; + s->priq.wrap.cons = 0; +} + +/***************************** + * EVTQ fields + *****************************/ + +#define EVT_Q_OVERFLOW (1 << 31) + +#define EVT_SET_TYPE(x, t) deposit32((x)->word[0], 0, 8, t) +#define EVT_SET_SID(x, s) ((x)->word[1] = s) +#define EVT_SET_INPUT_ADDR(x, addr) ({ \ + (x)->word[5] = (uint32_t)(addr >> 32); \ + (x)->word[4] = (uint32_t)(addr & 0xffffffff); \ + addr; \ + }) + +/***************************** + * Events + *****************************/ + +enum evt_err { + SMMU_EVT_F_UUT = 0x1, + SMMU_EVT_C_BAD_SID, + SMMU_EVT_F_STE_FETCH, + SMMU_EVT_C_BAD_STE, + SMMU_EVT_F_BAD_ATS_REQ, + SMMU_EVT_F_STREAM_DISABLED, + SMMU_EVT_F_TRANS_FORBIDDEN, + SMMU_EVT_C_BAD_SSID, + SMMU_EVT_F_CD_FETCH, + SMMU_EVT_C_BAD_CD, + SMMU_EVT_F_WALK_EXT_ABRT, + SMMU_EVT_F_TRANS = 0x10, + SMMU_EVT_F_ADDR_SZ, + SMMU_EVT_F_ACCESS, + SMMU_EVT_F_PERM, + SMMU_EVT_F_TLB_CONFLICT = 0x20, + SMMU_EVT_F_CFG_CONFLICT = 0x21, + SMMU_EVT_E_PAGE_REQ = 0x24, +}; + +typedef enum evt_err SMMUEvtErr; + +/***************************** + * Interrupts + *****************************/ + +static inline int __smmu_irq_enabled(SMMUV3State *s, uint32_t q) +{ + return smmu_read64_reg(s, SMMU_REG_IRQ_CTRL) & q; +} +#define smmu_evt_irq_enabled(s) \ + __smmu_irq_enabled(s, SMMU_IRQ_CTRL_EVENT_EN) +#define smmu_gerror_irq_enabled(s) \ + __smmu_irq_enabled(s, SMMU_IRQ_CTRL_GERROR_EN) +#define smmu_pri_irq_enabled(s) \ + __smmu_irq_enabled(s, SMMU_IRQ_CTRL_PRI_EN) + +static inline bool +smmu_is_irq_pending(SMMUV3State *s, int irq) +{ + return smmu_read32_reg(s, SMMU_REG_GERROR) ^ + smmu_read32_reg(s, SMMU_REG_GERRORN); +} + +/***************************** + * Hash Table + *****************************/ + +static inline gboolean smmu_uint64_equal(gconstpointer v1, gconstpointer v2) +{ + return *((const uint64_t *)v1) == *((const uint64_t *)v2); +} + +static inline guint smmu_uint64_hash(gconstpointer v) +{ + return (guint)*(const uint64_t *)v; +} + +/***************************** + * Misc + *****************************/ + +/** + * tg2granule - Decodes the CD translation granule size field according + * to the TT in use + * @bits: TG0/1 fiels + * @tg1: if set, @bits belong to TG1, otherwise belong to TG0 + */ +static inline int tg2granule(int bits, bool tg1) +{ + switch (bits) { + case 1: + return tg1 ? 14 : 16; + case 2: + return tg1 ? 12 : 14; + case 3: + return tg1 ? 16 : 12; + default: + return 12; + } +} + +#define L1STD_L2PTR(stm) ({ \ + uint64_t hi, lo; \ + hi = (stm)->word[1]; \ + lo = (stm)->word[0] & ~(uint64_t)0x1f; \ + hi << 32 | lo; \ + }) + +#define L1STD_SPAN(stm) (extract32((stm)->word[0], 0, 4)) + +/***************************** + * Debug + *****************************/ +#define ARM_SMMU_DEBUG + +#ifdef ARM_SMMU_DEBUG +static inline void dump_ste(Ste *ste) +{ + int i; + + for (i = 0; i < ARRAY_SIZE(ste->word); i += 2) { + trace_smmuv3_dump_ste(i, ste->word[i], i + 1, ste->word[i + 1]); + } +} + +static inline void dump_cd(Cd *cd) +{ + int i; + for (i = 0; i < ARRAY_SIZE(cd->word); i += 2) { + trace_smmuv3_dump_cd(i, cd->word[i], i + 1, cd->word[i + 1]); + } +} + +static inline void dump_cmd(Cmd *cmd) +{ + int i; + for (i = 0; i < ARRAY_SIZE(cmd->word); i += 2) { + trace_smmuv3_dump_cmd(i, cmd->word[i], i + 1, cmd->word[i + 1]); + } +} + +#else +#define dump_ste(...) do {} while (0) +#define dump_cd(...) do {} while (0) +#define dump_cmd(...) do {} while (0) +#endif /* ARM_SMMU_DEBUG */ + +#endif diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c new file mode 100644 index 0000000..a3199f1 --- /dev/null +++ b/hw/arm/smmuv3.c @@ -0,0 +1,1152 @@ +/* + * Copyright (C) 2014-2016 Broadcom Corporation + * Copyright (c) 2017 Red Hat, Inc. + * Written by Prem Mallappa, Eric Auger + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#include "qemu/osdep.h" +#include "hw/boards.h" +#include "sysemu/sysemu.h" +#include "hw/sysbus.h" +#include "hw/pci/pci.h" +#include "exec/address-spaces.h" +#include "trace.h" +#include "qemu/error-report.h" + +#include "hw/arm/smmuv3.h" +#include "smmuv3-internal.h" + +static inline int smmu_enabled(SMMUV3State *s) +{ + return smmu_read32_reg(s, SMMU_REG_CR0) & SMMU_CR0_SMMU_ENABLE; +} + +/** + * smmu_irq_update - update the GERROR register according to + * the IRQ and the enable state + * + * return > 0 when IRQ is supposed to be raised + */ +static int smmu_irq_update(SMMUV3State *s, int irq, uint64_t data) +{ + uint32_t error = 0; + + if (!smmu_gerror_irq_enabled(s)) { + return 0; + } + + switch (irq) { + case SMMU_IRQ_EVTQ: + if (smmu_evt_irq_enabled(s)) { + error = SMMU_GERROR_EVENTQ; + } + break; + case SMMU_IRQ_CMD_SYNC: + if (smmu_gerror_irq_enabled(s)) { + uint32_t err_type = (uint32_t)data; + + if (err_type) { + uint32_t regval = smmu_read32_reg(s, SMMU_REG_CMDQ_CONS); + smmu_write32_reg(s, SMMU_REG_CMDQ_CONS, + regval | err_type << SMMU_CMD_CONS_ERR_SHIFT); + } + error = SMMU_GERROR_CMDQ; + } + break; + case SMMU_IRQ_PRIQ: + if (smmu_pri_irq_enabled(s)) { + error = SMMU_GERROR_PRIQ; + } + break; + } + + if (error) { + uint32_t gerror = smmu_read32_reg(s, SMMU_REG_GERROR); + uint32_t gerrorn = smmu_read32_reg(s, SMMU_REG_GERRORN); + + trace_smmuv3_irq_update(error, gerror, gerrorn); + + /* only toggle GERROR if the interrupt is not active */ + if (!((gerror ^ gerrorn) & error)) { + smmu_write32_reg(s, SMMU_REG_GERROR, gerror ^ error); + } + } + + return error; +} + +static void smmu_irq_raise(SMMUV3State *s, int irq, uint64_t data) +{ + trace_smmuv3_irq_raise(irq); + if (smmu_irq_update(s, irq, data)) { + qemu_irq_raise(s->irq[irq]); + } +} + +static MemTxResult smmu_q_read(SMMUQueue *q, void *data) +{ + uint64_t addr = Q_ENTRY(q, Q_IDX(q, q->cons)); + MemTxResult ret; + + ret = smmu_read_sysmem(addr, data, q->ent_size, false); + /* TODO if (ret != MEMTX_OK ) handle error */ + + q->cons++; + if (q->cons == q->entries) { + q->cons = 0; + q->wrap.cons++; /* this will toggle */ + } + + return ret; +} + +static MemTxResult smmu_q_write(SMMUQueue *q, void *data) +{ + uint64_t addr = Q_ENTRY(q, Q_IDX(q, q->prod)); + + if (q->prod == q->entries) { + q->prod = 0; + q->wrap.prod++; /* this will toggle */ + } + + q->prod++; + + smmu_write_sysmem(addr, data, q->ent_size, false); + + return MEMTX_OK; +} + +static MemTxResult smmu_read_cmdq(SMMUV3State *s, Cmd *cmd) +{ + SMMUQueue *q = &s->cmdq; + MemTxResult ret = smmu_q_read(q, cmd); + uint32_t val = 0; + + val |= (q->wrap.cons << q->shift) | q->cons; + + /* Update consumer pointer */ + smmu_write32_reg(s, SMMU_REG_CMDQ_CONS, val); + + return ret; +} + +static int smmu_cmdq_consume(SMMUV3State *s) +{ + uint32_t error = SMMU_CMD_ERR_NONE; + + trace_smmuv3_cmdq_consume(SMMU_CMDQ_ERR(s), smmu_cmd_q_enabled(s), + s->cmdq.prod, s->cmdq.cons, + s->cmdq.wrap.prod, s->cmdq.wrap.cons); + + if (!smmu_cmd_q_enabled(s)) { + return 0; + } + + while (!SMMU_CMDQ_ERR(s) && !smmu_is_q_empty(s, &s->cmdq)) { + uint32_t type; + Cmd cmd; + + if (smmu_read_cmdq(s, &cmd) != MEMTX_OK) { + error = SMMU_CMD_ERR_ABORT; + break; + } + + type = CMD_TYPE(&cmd); + + trace_smmuv3_cmdq_opcode(cmd_stringify[type]); + + switch (CMD_TYPE(&cmd)) { + case SMMU_CMD_SYNC: /* Fallthrough */ + if (CMD_CS(&cmd) & CMD_SYNC_SIG_IRQ) { + smmu_irq_raise(s, SMMU_IRQ_CMD_SYNC, SMMU_CMD_ERR_NONE); + } else if (CMD_CS(&cmd) & CMD_SYNC_SIG_SEV) { + trace_smmuv3_cmdq_consume_sev(); + } + break; + case SMMU_CMD_PREFETCH_CONFIG: + case SMMU_CMD_PREFETCH_ADDR: + case SMMU_CMD_CFGI_STE: + { + uint32_t streamid = cmd.word[1]; + + trace_smmuv3_cmdq_cfgi_ste(streamid); + break; + } + case SMMU_CMD_CFGI_STE_RANGE: /* same as SMMU_CMD_CFGI_ALL */ + { + uint32_t start = cmd.word[1], range, end; + + range = extract32(cmd.word[2], 0, 5); + end = start + (1 << (range + 1)) - 1; + trace_smmuv3_cmdq_cfgi_ste_range(start, end); + break; + } + case SMMU_CMD_CFGI_CD: + case SMMU_CMD_CFGI_CD_ALL: + break; + case SMMU_CMD_TLBI_NH_ALL: + case SMMU_CMD_TLBI_NH_ASID: + printf("%s TLBI* replay\n", __func__); + break; + case SMMU_CMD_TLBI_NH_VA: + { + int asid = extract32(cmd.word[1], 16, 16); + int vmid = extract32(cmd.word[1], 0, 16); + uint64_t low = extract32(cmd.word[2], 12, 20); + uint64_t high = cmd.word[3]; + uint64_t addr = high << 32 | (low << 12); + + trace_smmuv3_cmdq_tlbi_nh_va(asid, vmid, addr); + break; + } + case SMMU_CMD_TLBI_NH_VAA: + case SMMU_CMD_TLBI_EL3_ALL: + case SMMU_CMD_TLBI_EL3_VA: + case SMMU_CMD_TLBI_EL2_ALL: + case SMMU_CMD_TLBI_EL2_ASID: + case SMMU_CMD_TLBI_EL2_VA: + case SMMU_CMD_TLBI_EL2_VAA: + case SMMU_CMD_TLBI_S12_VMALL: + case SMMU_CMD_TLBI_S2_IPA: + case SMMU_CMD_TLBI_NSNH_ALL: + break; + case SMMU_CMD_ATC_INV: + case SMMU_CMD_PRI_RESP: + case SMMU_CMD_RESUME: + case SMMU_CMD_STALL_TERM: + trace_smmuv3_unhandled_cmd(type); + break; + default: + error = SMMU_CMD_ERR_ILLEGAL; + error_report("Illegal command type: %d, ignoring", CMD_TYPE(&cmd)); + dump_cmd(&cmd); + break; + } + + if (error != SMMU_CMD_ERR_NONE) { + error_report("CMD Error"); + break; + } + } + + if (error) { + smmu_irq_raise(s, SMMU_IRQ_GERROR, error); + } + + trace_smmuv3_cmdq_consume_out(s->cmdq.wrap.prod, s->cmdq.prod, + s->cmdq.wrap.cons, s->cmdq.cons); + + return 0; +} + +/** + * GERROR is updated when raising an interrupt, GERRORN will be updated + * by SW and should match GERROR before normal operation resumes. + */ +static void smmu_irq_clear(SMMUV3State *s, uint64_t gerrorn) +{ + int irq = SMMU_IRQ_GERROR; + uint32_t toggled; + + toggled = smmu_read32_reg(s, SMMU_REG_GERRORN) ^ gerrorn; + + while (toggled) { + irq = ctz32(toggled); + + qemu_irq_lower(s->irq[irq]); + + toggled &= toggled - 1; + } +} + +static int smmu_evtq_update(SMMUV3State *s) +{ + if (!smmu_enabled(s)) { + return 0; + } + + if (!smmu_is_q_empty(s, &s->evtq)) { + if (smmu_evt_irq_enabled(s)) { + smmu_irq_raise(s, SMMU_IRQ_EVTQ, 0); + } + } + + if (smmu_is_q_empty(s, &s->evtq)) { + smmu_irq_clear(s, SMMU_GERROR_EVENTQ); + } + + return 1; +} + +static void smmu_create_event(SMMUV3State *s, hwaddr iova, + uint32_t sid, bool is_write, int error); + +static void smmu_update(SMMUV3State *s) +{ + int error = 0; + + /* SMMU starts processing commands even when not enabled */ + if (!smmu_enabled(s)) { + goto check_cmdq; + } + + /* EVENT Q updates takes more priority */ + if ((smmu_evt_q_enabled(s)) && !smmu_is_q_empty(s, &s->evtq)) { + trace_smmuv3_update(smmu_is_q_empty(s, &s->evtq), s->evtq.prod, + s->evtq.cons, s->evtq.wrap.prod, s->evtq.wrap.cons); + error = smmu_evtq_update(s); + } + + if (error) { + /* TODO: May be in future we create proper event queue entry */ + /* an error condition is not a recoverable event, like other devices */ + error_report("An unfavourable condition"); + smmu_create_event(s, 0, 0, 0, error); + } + +check_cmdq: + if (smmu_cmd_q_enabled(s) && !SMMU_CMDQ_ERR(s)) { + smmu_cmdq_consume(s); + } else { + trace_smmuv3_update_check_cmd(SMMU_CMDQ_ERR(s)); + } + +} + +static void smmu_update_irq(SMMUV3State *s, uint64_t addr, uint64_t val) +{ + smmu_irq_clear(s, val); + + smmu_write32_reg(s, SMMU_REG_GERRORN, val); + + trace_smmuv3_update_irq(smmu_is_irq_pending(s, 0), + smmu_read32_reg(s, SMMU_REG_GERROR), + smmu_read32_reg(s, SMMU_REG_GERRORN)); + + /* Clear only when no more left */ + if (!smmu_is_irq_pending(s, 0)) { + qemu_irq_lower(s->irq[0]); + } +} + +#define SMMU_ID_REG_INIT(s, reg, d) do { \ + s->regs[reg >> 2] = d; \ + } while (0) + +static void smmuv3_id_reg_init(SMMUV3State *s) +{ + uint32_t data = + SMMU_IDR0_STLEVEL << SMMU_IDR0_STLEVEL_SHIFT | + SMMU_IDR0_TERM << SMMU_IDR0_TERM_SHIFT | + SMMU_IDR0_STALL << SMMU_IDR0_STALL_SHIFT | + SMMU_IDR0_VMID16 << SMMU_IDR0_VMID16_SHIFT | + SMMU_IDR0_PRI << SMMU_IDR0_PRI_SHIFT | + SMMU_IDR0_ASID16 << SMMU_IDR0_ASID16_SHIFT | + SMMU_IDR0_ATS << SMMU_IDR0_ATS_SHIFT | + SMMU_IDR0_HYP << SMMU_IDR0_HYP_SHIFT | + SMMU_IDR0_HTTU << SMMU_IDR0_HTTU_SHIFT | + SMMU_IDR0_COHACC << SMMU_IDR0_COHACC_SHIFT | + SMMU_IDR0_TTF << SMMU_IDR0_TTF_SHIFT | + SMMU_IDR0_S1P << SMMU_IDR0_S1P_SHIFT | + SMMU_IDR0_S2P << SMMU_IDR0_S2P_SHIFT; + + SMMU_ID_REG_INIT(s, SMMU_REG_IDR0, data); + +#define SMMU_QUEUE_SIZE_LOG2 19 + data = + 1 << 27 | /* Attr Types override */ + SMMU_QUEUE_SIZE_LOG2 << 21 | /* Cmd Q size */ + SMMU_QUEUE_SIZE_LOG2 << 16 | /* Event Q size */ + SMMU_QUEUE_SIZE_LOG2 << 11 | /* PRI Q size */ + 0 << 6 | /* SSID not supported */ + SMMU_IDR1_SIDSIZE; + + SMMU_ID_REG_INIT(s, SMMU_REG_IDR1, data); + + data = + SMMU_IDR5_GRAN << SMMU_IDR5_GRAN_SHIFT | SMMU_IDR5_OAS; + + SMMU_ID_REG_INIT(s, SMMU_REG_IDR5, data); + +} + +static void smmuv3_init(SMMUV3State *s) +{ + smmuv3_id_reg_init(s); /* Update ID regs alone */ + + s->sid_size = SMMU_IDR1_SIDSIZE; + + s->cmdq.entries = (smmu_read32_reg(s, SMMU_REG_IDR1) >> 21) & 0x1f; + s->cmdq.ent_size = sizeof(Cmd); + s->evtq.entries = (smmu_read32_reg(s, SMMU_REG_IDR1) >> 16) & 0x1f; + s->evtq.ent_size = sizeof(Evt); +} + +/* + * All SMMU data structures are little endian, and are aligned to 8 bytes + * L1STE/STE/L1CD/CD, Queue entries in CMDQ/EVTQ/PRIQ + */ +static inline int smmu_get_ste(SMMUV3State *s, hwaddr addr, Ste *buf) +{ + int ret; + + trace_smmuv3_get_ste(addr); + ret = dma_memory_read(&address_space_memory, addr, buf, sizeof(*buf)); + dump_ste(buf); + return ret; +} + +/* + * For now we only support CD with a single entry, 'ssid' is used to identify + * otherwise + */ +static inline int smmu_get_cd(SMMUV3State *s, Ste *ste, uint32_t ssid, Cd *buf) +{ + hwaddr addr = STE_CTXPTR(ste); + int ret; + + if (STE_S1CDMAX(ste) != 0) { + error_report("Multilevel Ctx Descriptor not supported yet"); + } + + ret = dma_memory_read(&address_space_memory, addr, buf, sizeof(*buf)); + + trace_smmuv3_get_cd(addr); + dump_cd(buf); + + return ret; +} + +/** + * is_ste_consistent - Check validity of STE + * according to 6.2.1 Validty of STE + * TODO: check the relevance of each check and compliance + * with this spec chapter + */ +static int is_ste_consistent(SMMUV3State *s, Ste *ste) +{ + uint32_t _config = STE_CONFIG(ste); + uint32_t ste_vmid, ste_eats, ste_s2s, ste_s1fmt, ste_s2aa64, ste_s1cdmax; + uint32_t ste_strw; + bool strw_unused, addr_out_of_range, granule_supported; + bool config[] = {_config & 0x1, _config & 0x2, _config & 0x3}; + + ste_vmid = STE_S2VMID(ste); + ste_eats = STE_EATS(ste); /* Enable PCIe ATS trans */ + ste_s2s = STE_S2S(ste); + ste_s1fmt = STE_S1FMT(ste); + ste_s2aa64 = STE_S2AA64(ste); + ste_s1cdmax = STE_S1CDMAX(ste); /*CD bit # S1ContextPtr */ + ste_strw = STE_STRW(ste); /* stream world control */ + + if (!STE_VALID(ste)) { + error_report("STE NOT valid"); + return false; + } + + granule_supported = is_s2granule_valid(ste); + + /* As S1/S2 combinations are supported do not check + * corresponding STE config values */ + + if (!config[2]) { + /* Report abort to device, no event recorded */ + error_report("STE config 0b000 not implemented"); + return false; + } + + if (!SMMU_IDR1_SIDSIZE && ste_s1cdmax && config[0] && + !SMMU_IDR0_CD2L && (ste_s1fmt == 1 || ste_s1fmt == 2)) { + error_report("STE inconsistant, CD mismatch"); + return false; + } + if (SMMU_IDR0_ATS && ((_config & 0x3) == 0) && + ((ste_eats == 2 && (_config != 0x7 || ste_s2s)) || + (ste_eats == 1 && !ste_s2s))) { + error_report("STE inconsistant, EATS/S2S mismatch"); + return false; + } + if (config[0] && (SMMU_IDR1_SIDSIZE && + (ste_s1cdmax > SMMU_IDR1_SIDSIZE))) { + error_report("STE inconsistant, SSID out of range"); + return false; + } + + strw_unused = (!SMMU_IDR0_S1P || !SMMU_IDR0_HYP || (_config == 4)); + + addr_out_of_range = STE_S2TTB(ste) > MAX_PA(ste); + + if (is_ste_stage2(ste)) { + if ((ste_s2aa64 && !is_s2granule_valid(ste)) || + (!ste_s2aa64 && !(SMMU_IDR0_TTF & 0x1)) || + (ste_s2aa64 && !(SMMU_IDR0_TTF & 0x2)) || + ((STE_S2HA(ste) || STE_S2HD(ste)) && !ste_s2aa64) || + ((STE_S2HA(ste) || STE_S2HD(ste)) && !SMMU_IDR0_HTTU) || + (STE_S2HD(ste) && (SMMU_IDR0_HTTU == 1)) || addr_out_of_range) { + error_report("STE inconsistant"); + trace_smmuv3_is_ste_consistent(config[1], granule_supported, + addr_out_of_range, ste_s2aa64, + STE_S2HA(ste), STE_S2HD(ste), + STE_S2TTB(ste)); + return false; + } + } + if (SMMU_IDR0_S2P && (config[0] == 0 && config[1]) && + (strw_unused || !ste_strw) && !SMMU_IDR0_VMID16 && !(ste_vmid >> 8)) { + error_report("STE inconsistant, VMID out of range"); + return false; + } + + return true; +} + +/** + * smmu_find_ste - Return the stream table entry associated + * to the sid + * + * @s: smmuv3 handle + * @sid: stream ID + * @ste: returned stream table entry + * Supports linear and 2-level stream table + */ +static int smmu_find_ste(SMMUV3State *s, uint16_t sid, Ste *ste) +{ + hwaddr addr; + + trace_smmuv3_find_ste(sid, s->features, s->sid_split); + /* Check SID range */ + if (sid > (1 << s->sid_size)) { + return SMMU_EVT_C_BAD_SID; + } + if (s->features & SMMU_FEATURE_2LVL_STE) { + int l1_ste_offset, l2_ste_offset, max_l2_ste, span; + hwaddr l1ptr, l2ptr; + STEDesc l1std; + + l1_ste_offset = sid >> s->sid_split; + l2_ste_offset = sid & ((1 << s->sid_split) - 1); + l1ptr = (hwaddr)(s->strtab_base + l1_ste_offset * sizeof(l1std)); + smmu_read_sysmem(l1ptr, &l1std, sizeof(l1std), false); + span = L1STD_SPAN(&l1std); + + if (!span) { + /* l2ptr is not valid */ + error_report("invalid sid=%d (L1STD span=0)", sid); + return SMMU_EVT_C_BAD_SID; + } + max_l2_ste = (1 << span) - 1; + l2ptr = L1STD_L2PTR(&l1std); + trace_smmuv3_find_ste_2lvl(s->strtab_base, l1ptr, l1_ste_offset, + l2ptr, l2_ste_offset, max_l2_ste); + if (l2_ste_offset > max_l2_ste) { + error_report("l2_ste_offset=%d > max_l2_ste=%d", + l2_ste_offset, max_l2_ste); + return SMMU_EVT_C_BAD_STE; + } + addr = L1STD_L2PTR(&l1std) + l2_ste_offset * sizeof(*ste); + } else { + addr = s->strtab_base + sid * sizeof(*ste); + } + + if (smmu_get_ste(s, addr, ste)) { + error_report("Unable to Fetch STE"); + return SMMU_EVT_F_UUT; + } + + return 0; +} + +/** + * smmu_cfg_populate_s1 - Populate the stage 1 translation config + * from the context descriptor + */ +static int smmu_cfg_populate_s1(SMMUTransCfg *cfg, Cd *cd) +{ + bool s1a64 = CD_AARCH64(cd); + int epd0 = CD_EPD0(cd); + int tg; + + cfg->stage = 1; + tg = epd0 ? CD_TG1(cd) : CD_TG0(cd); + cfg->tsz = epd0 ? CD_T1SZ(cd) : CD_T0SZ(cd); + cfg->ttbr = epd0 ? CD_TTB1(cd) : CD_TTB0(cd); + cfg->oas = oas2bits(CD_IPS(cd)); + + if (s1a64) { + cfg->tsz = MIN(cfg->tsz, 39); + cfg->tsz = MAX(cfg->tsz, 16); + } + cfg->granule_sz = tg2granule(tg, epd0); + + cfg->oas = MIN(oas2bits(SMMU_IDR5_OAS), cfg->oas); + /* fix ttbr - make top bits zero*/ + cfg->ttbr = extract64(cfg->ttbr, 0, cfg->oas); + cfg->aa64 = s1a64; + cfg->initial_level = 4 - (64 - cfg->tsz - 4) / (cfg->granule_sz - 3); + + trace_smmuv3_cfg_stage(cfg->stage, cfg->oas, cfg->tsz, cfg->ttbr, + cfg->aa64, cfg->granule_sz, cfg->initial_level); + + return 0; +} + +/** + * smmu_cfg_populate_s2 - Populate the stage 2 translation config + * from the Stream Table Entry + */ +static int smmu_cfg_populate_s2(SMMUTransCfg *cfg, Ste *ste) +{ + bool s2a64 = STE_S2AA64(ste); + int default_initial_level; + int tg; + + cfg->stage = 2; + + tg = STE_S2TG(ste); + cfg->tsz = STE_S2T0SZ(ste); + cfg->ttbr = STE_S2TTB(ste); + cfg->oas = pa_range(ste); + + cfg->aa64 = s2a64; + + if (s2a64) { + cfg->tsz = MIN(cfg->tsz, 39); + cfg->tsz = MAX(cfg->tsz, 16); + } + cfg->granule_sz = tg2granule(tg, 0); + + cfg->oas = MIN(oas2bits(SMMU_IDR5_OAS), cfg->oas); + /* fix ttbr - make top bits zero*/ + cfg->ttbr = extract64(cfg->ttbr, 0, cfg->oas); + + default_initial_level = 4 - (64 - cfg->tsz - 4) / (cfg->granule_sz - 3); + cfg->initial_level = ~STE_S2SL0(ste); + if (cfg->initial_level != default_initial_level) { + error_report("%s concatenated translation tables at initial S2 lookup" + " not supported", __func__); + return -1; + } + + trace_smmuv3_cfg_stage(cfg->stage, cfg->oas, cfg->tsz, cfg->ttbr, + cfg->aa64, cfg->granule_sz, cfg->initial_level); + + return 0; +} + +static MemTxResult smmu_write_evtq(SMMUV3State *s, Evt *evt) +{ + SMMUQueue *q = &s->evtq; + int ret = smmu_q_write(q, evt); + uint32_t val = 0; + + val |= (q->wrap.prod << q->shift) | q->prod; + + smmu_write32_reg(s, SMMU_REG_EVTQ_PROD, val); + + return ret; +} + +/* + * Events created on the EventQ + */ +static void smmu_create_event(SMMUV3State *s, hwaddr iova, + uint32_t sid, bool is_write, int error) +{ + SMMUQueue *q = &s->evtq; + uint64_t head; + Evt evt; + + if (!smmu_evt_q_enabled(s)) { + return; + } + + EVT_SET_TYPE(&evt, error); + EVT_SET_SID(&evt, sid); + + switch (error) { + case SMMU_EVT_F_UUT: + case SMMU_EVT_C_BAD_STE: + break; + case SMMU_EVT_C_BAD_CD: + case SMMU_EVT_F_CD_FETCH: + break; + case SMMU_EVT_F_TRANS_FORBIDDEN: + case SMMU_EVT_F_WALK_EXT_ABRT: + EVT_SET_INPUT_ADDR(&evt, iova); + default: + break; + } + + smmu_write_evtq(s, &evt); + + head = Q_IDX(q, q->prod); + + if (smmu_is_q_full(s, &s->evtq)) { + head = q->prod ^ (1 << 31); /* Set overflow */ + } + + smmu_write32_reg(s, SMMU_REG_EVTQ_PROD, head); + + smmu_irq_raise(s, SMMU_IRQ_EVTQ, 0); +} + +/** + * smmuv3_config_config - Prepare the translation configuration + * for the @mr iommu region + * @mr: iommu memory region the translation config must be prepared for + * @cfg: output translation configuration + * + * return 0 on success or error code on failure + */ +static int smmuv3_decode_config(IOMMUMemoryRegion *mr, SMMUTransCfg *cfg) +{ + SMMUDevice *sdev = container_of(mr, SMMUDevice, iommu); + int sid = smmu_get_sid(sdev); + SMMUV3State *s = sdev->smmu; + Ste ste; + Cd cd; + int ret = 0; + + if (!smmu_enabled(s)) { + cfg->disabled = true; + return 0; + } + ret = smmu_find_ste(s, sid, &ste); + if (ret) { + return ret; + } + + if (!STE_VALID(&ste)) { + return SMMU_EVT_C_BAD_STE; + } + + switch (STE_CONFIG(&ste)) { + case STE_CONFIG_BYPASS: + cfg->bypassed = true; + return 0; + case STE_CONFIG_S1: + break; + case STE_CONFIG_S2: + break; + default: /* reserved, abort, nested */ + return -1; + } + + /* S1 or S2 */ + + if (!is_ste_consistent(s, &ste)) { + return SMMU_EVT_C_BAD_STE; + } + + if (is_ste_stage1(&ste)) { + ret = smmu_get_cd(s, &ste, 0, &cd); /* We dont have SSID yet */ + if (ret) { + return ret; + } + + if (!is_cd_valid(s, &ste, &cd)) { + return SMMU_EVT_C_BAD_CD; + } + return smmu_cfg_populate_s1(cfg, &cd); + } + + return smmu_cfg_populate_s2(cfg, &ste); +} + +static IOMMUTLBEntry smmuv3_translate(IOMMUMemoryRegion *mr, hwaddr addr, + IOMMUAccessFlags flag) +{ + SMMUDevice *sdev = container_of(mr, SMMUDevice, iommu); + SMMUV3State *s = sdev->smmu; + SMMUState *sys = SMMU_SYS_DEV(s); + bool is_write = flag & IOMMU_WO; + uint16_t sid = 0; + SMMUEvtErr ret; + SMMUTransCfg cfg = {}; + IOMMUTLBEntry entry = { + .target_as = &address_space_memory, + .iova = addr, + .translated_addr = addr, + .addr_mask = ~(hwaddr)0, + .perm = IOMMU_NONE, + }; + + ret = smmuv3_decode_config(mr, &cfg); + if (ret || cfg.disabled || cfg.bypassed) { + goto out; + } + + ret = smmu_page_walk(sys, &cfg, &entry, is_write); + + entry.perm = is_write ? IOMMU_RW : IOMMU_RO; + + trace_smmuv3_translate_ok(mr->parent_obj.name, sid, addr, + entry.translated_addr, entry.perm); +out: + if (ret) { + error_report("%s translation failed for iova=0x%"PRIx64, + mr->parent_obj.name, addr); + smmu_create_event(s, entry.iova, sid, is_write, ret); + } + return entry; +} + + +static inline void smmu_update_base_reg(SMMUV3State *s, uint64_t *base, + uint64_t val) +{ + *base = val & ~(SMMU_BASE_RA | 0x3fULL); +} + +static void smmu_update_qreg(SMMUV3State *s, SMMUQueue *q, hwaddr reg, + uint32_t off, uint64_t val, unsigned size) +{ + if (size == 8 && off == 0) { + smmu_write64_reg(s, reg, val); + } else { + smmu_write_reg(s, reg, val); + } + + switch (off) { + case 0: /* BASE register */ + val = smmu_read64_reg(s, reg); + q->shift = val & 0x1f; + q->entries = 1 << (q->shift); + smmu_update_base_reg(s, &q->base, val); + break; + + case 8: /* PROD */ + q->prod = Q_IDX(q, val); + q->wrap.prod = val >> q->shift; + break; + + case 12: /* CONS */ + q->cons = Q_IDX(q, val); + q->wrap.cons = val >> q->shift; + trace_smmuv3_update_qreg(q->cons, val); + break; + + } + + switch (reg) { + case SMMU_REG_CMDQ_PROD: /* should be only for CMDQ_PROD */ + case SMMU_REG_CMDQ_CONS: /* but we do it anyway */ + smmu_update(s); + break; + } +} + +static void smmu_write_mmio_fixup(SMMUV3State *s, hwaddr *addr) +{ + switch (*addr) { + case 0x100a8: case 0x100ac: /* Aliasing => page0 registers */ + case 0x100c8: case 0x100cc: + *addr ^= (hwaddr)0x10000; + } +} + +static void smmu_write_mmio(void *opaque, hwaddr addr, + uint64_t val, unsigned size) +{ + SMMUState *sys = opaque; + SMMUV3State *s = SMMU_V3_DEV(sys); + bool update = false; + + smmu_write_mmio_fixup(s, &addr); + + trace_smmuv3_write_mmio(addr, val, size); + + switch (addr) { + case 0xFDC ... 0xFFC: + case SMMU_REG_IDR0 ... SMMU_REG_IDR5: + trace_smmuv3_write_mmio_idr(addr, val); + return; + + case SMMU_REG_GERRORN: + smmu_update_irq(s, addr, val); + return; + + case SMMU_REG_CR0: + smmu_write32_reg(s, SMMU_REG_CR0, val); + smmu_write32_reg(s, SMMU_REG_CR0_ACK, val); + update = true; + break; + + case SMMU_REG_IRQ_CTRL: + smmu_write32_reg(s, SMMU_REG_IRQ_CTRL_ACK, val); + update = true; + break; + + case SMMU_REG_STRTAB_BASE: + smmu_update_base_reg(s, &s->strtab_base, val); + return; + + case SMMU_REG_STRTAB_BASE_CFG: + if (((val >> 16) & 0x3) == 0x1) { + s->sid_split = (val >> 6) & 0x1f; + s->features |= SMMU_FEATURE_2LVL_STE; + } + break; + + case SMMU_REG_CMDQ_PROD: + case SMMU_REG_CMDQ_CONS: + case SMMU_REG_CMDQ_BASE: + case SMMU_REG_CMDQ_BASE + 4: + smmu_update_qreg(s, &s->cmdq, addr, addr - SMMU_REG_CMDQ_BASE, + val, size); + return; + + case SMMU_REG_EVTQ_CONS: /* fallthrough */ + { + SMMUQueue *evtq = &s->evtq; + evtq->cons = Q_IDX(evtq, val); + evtq->wrap.cons = Q_WRAP(evtq, val); + + trace_smmuv3_write_mmio_evtq_cons_bef_clear(evtq->prod, evtq->cons, + evtq->wrap.prod, + evtq->wrap.cons); + if (smmu_is_q_empty(s, &s->evtq)) { + trace_smmuv3_write_mmio_evtq_cons_after_clear(evtq->prod, + evtq->cons, + evtq->wrap.prod, + evtq->wrap.cons); + qemu_irq_lower(s->irq[SMMU_IRQ_EVTQ]); + } + } + case SMMU_REG_EVTQ_BASE: + case SMMU_REG_EVTQ_BASE + 4: + case SMMU_REG_EVTQ_PROD: + smmu_update_qreg(s, &s->evtq, addr, addr - SMMU_REG_EVTQ_BASE, + val, size); + return; + + case SMMU_REG_PRIQ_CONS: + case SMMU_REG_PRIQ_BASE: + case SMMU_REG_PRIQ_BASE + 4: + case SMMU_REG_PRIQ_PROD: + smmu_update_qreg(s, &s->priq, addr, addr - SMMU_REG_PRIQ_BASE, + val, size); + return; + } + + if (size == 8) { + smmu_write_reg(s, addr, val); + } else { + smmu_write32_reg(s, addr, (uint32_t)val); + } + + if (update) { + smmu_update(s); + } +} + +static uint64_t smmu_read_mmio(void *opaque, hwaddr addr, unsigned size) +{ + SMMUState *sys = opaque; + SMMUV3State *s = SMMU_V3_DEV(sys); + uint64_t val; + + smmu_write_mmio_fixup(s, &addr); + + /* Primecell/Corelink ID registers */ + switch (addr) { + case 0xFF0 ... 0xFFC: + case 0xFDC ... 0xFE4: + val = 0; + error_report("addr:0x%"PRIx64" val:0x%"PRIx64, addr, val); + break; + + default: + val = (uint64_t)smmu_read32_reg(s, addr); + break; + + case SMMU_REG_STRTAB_BASE ... SMMU_REG_CMDQ_BASE: + case SMMU_REG_EVTQ_BASE: + case SMMU_REG_PRIQ_BASE ... SMMU_REG_PRIQ_IRQ_CFG1: + val = smmu_read64_reg(s, addr); + break; + } + + trace_smmuv3_read_mmio(addr, val, size); + return val; +} + +static const MemoryRegionOps smmu_mem_ops = { + .read = smmu_read_mmio, + .write = smmu_write_mmio, + .endianness = DEVICE_LITTLE_ENDIAN, + .valid = { + .min_access_size = 4, + .max_access_size = 8, + }, + .impl = { + .min_access_size = 4, + .max_access_size = 8, + }, +}; + +static void smmu_init_irq(SMMUV3State *s, SysBusDevice *dev) +{ + int i; + + for (i = 0; i < ARRAY_SIZE(s->irq); i++) { + sysbus_init_irq(dev, &s->irq[i]); + } +} + +static AddressSpace *smmu_find_add_as(PCIBus *bus, void *opaque, int devfn) +{ + SMMUState *s = opaque; + uintptr_t key = (uintptr_t)bus; + SMMUPciBus *sbus = g_hash_table_lookup(s->smmu_as_by_busptr, &key); + SMMUDevice *sdev; + + if (!sbus) { + uintptr_t *new_key = g_malloc(sizeof(*new_key)); + + *new_key = (uintptr_t)bus; + sbus = g_malloc0(sizeof(SMMUPciBus) + + sizeof(SMMUDevice *) * SMMU_PCI_DEVFN_MAX); + sbus->bus = bus; + g_hash_table_insert(s->smmu_as_by_busptr, new_key, sbus); + } + + sdev = sbus->pbdev[devfn]; + if (!sdev) { + char *name = g_strdup_printf("%s-%d-%d", TYPE_SMMU_V3_DEV, + pci_bus_num(bus), devfn); + sdev = sbus->pbdev[devfn] = g_malloc0(sizeof(SMMUDevice)); + + sdev->smmu = s; + sdev->bus = bus; + sdev->devfn = devfn; + + memory_region_init_iommu(&sdev->iommu, sizeof(sdev->iommu), + TYPE_SMMUV3_IOMMU_MEMORY_REGION, + OBJECT(s), name, 1ULL << 48); + address_space_init(&sdev->as, + MEMORY_REGION(&sdev->iommu), TYPE_SMMU_V3_DEV); + } + + return &sdev->as; + +} + +static void smmu_init_iommu_as(SMMUV3State *sys) +{ + SMMUState *s = SMMU_SYS_DEV(sys); + PCIBus *pcibus = pci_find_primary_bus(); + + if (pcibus) { + pci_setup_iommu(pcibus, smmu_find_add_as, s); + } else { + error_report("No PCI bus, SMMU is not registered"); + } +} + +static void smmu_reset(DeviceState *dev) +{ + SMMUV3State *s = SMMU_V3_DEV(dev); + smmuv3_init(s); +} + +static int smmu_populate_internal_state(void *opaque, int version_id) +{ + SMMUV3State *s = opaque; + + smmu_update(s); + return 0; +} + +static void smmu_realize(DeviceState *d, Error **errp) +{ + SMMUState *sys = SMMU_SYS_DEV(d); + SMMUV3State *s = SMMU_V3_DEV(sys); + SysBusDevice *dev = SYS_BUS_DEVICE(d); + + memset(sys->smmu_as_by_bus_num, 0, sizeof(sys->smmu_as_by_bus_num)); + memory_region_init_io(&sys->iomem, OBJECT(s), + &smmu_mem_ops, sys, TYPE_SMMU_V3_DEV, 0x20000); + + sys->smmu_as_by_busptr = g_hash_table_new_full(smmu_uint64_hash, + smmu_uint64_equal, + g_free, g_free); + sysbus_init_mmio(dev, &sys->iomem); + + smmuv3_init_queues(s); + + smmu_init_irq(s, dev); + + smmu_init_iommu_as(s); +} + +static const VMStateDescription vmstate_smmuv3 = { + .name = "smmuv3", + .version_id = 1, + .minimum_version_id = 1, + .post_load = smmu_populate_internal_state, + .fields = (VMStateField[]) { + VMSTATE_UINT32_ARRAY(regs, SMMUV3State, SMMU_NREGS), + VMSTATE_END_OF_LIST(), + }, +}; + +static void smmuv3_instance_init(Object *obj) +{ + /* Nothing much to do here as of now */ +} + +static void smmuv3_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + + dc->reset = smmu_reset; + dc->vmsd = &vmstate_smmuv3; + dc->realize = smmu_realize; +} + +static void smmuv3_iommu_memory_region_class_init(ObjectClass *klass, + void *data) +{ + IOMMUMemoryRegionClass *imrc = IOMMU_MEMORY_REGION_CLASS(klass); + + imrc->translate = smmuv3_translate; +} + +static const TypeInfo smmuv3_type_info = { + .name = TYPE_SMMU_V3_DEV, + .parent = TYPE_SMMU_DEV_BASE, + .instance_size = sizeof(SMMUV3State), + .instance_init = smmuv3_instance_init, + .class_data = NULL, + .class_size = sizeof(SMMUV3Class), + .class_init = smmuv3_class_init, +}; + +static const TypeInfo smmuv3_iommu_memory_region_info = { + .parent = TYPE_IOMMU_MEMORY_REGION, + .name = TYPE_SMMUV3_IOMMU_MEMORY_REGION, + .class_init = smmuv3_iommu_memory_region_class_init, +}; + +static void smmuv3_register_types(void) +{ + type_register(&smmuv3_type_info); + type_register(&smmuv3_iommu_memory_region_info); +} + +type_init(smmuv3_register_types) + diff --git a/hw/arm/trace-events b/hw/arm/trace-events index b371b4d..f9b9cbe 100644 --- a/hw/arm/trace-events +++ b/hw/arm/trace-events @@ -16,3 +16,37 @@ smmu_get_pte(uint64_t baseaddr, int index, uint64_t pteaddr, uint64_t pte) "base smmu_set_translated_address(hwaddr iova, hwaddr pa) "iova = 0x%"PRIx64" -> pa = 0x%"PRIx64 smmu_walk_pgtable(hwaddr iova, bool is_write) "Input addr: 0x%"PRIx64", is_write=%d" smmu_walk_pgtable_out(hwaddr addr, uint32_t mask, int perm) "DONE: o/p addr:0x%"PRIx64" mask:0x%x perm:%d" + +#hw/arm/smmuv3.c +smmuv3_irq_update(uint32_t error, uint32_t gerror, uint32_t gerrorn) "<<<< error:0x%x gerror:0x%x gerrorn:0x%x" +smmuv3_irq_raise(int irq) "irq:%d" +smmuv3_unhandled_cmd(uint32_t type) "Unhandled command type=%d" +smmuv3_cmdq_consume(int error, bool enabled, uint32_t prod, uint32_t cons, uint8_t wrap_prod, uint8_t wrap_cons) "error=%d, enabled=%d prod=%d cons=%d wrap.prod=%d wrap.cons=%d" +smmuv3_cmdq_consume_details(hwaddr base, uint32_t cons, uint32_t prod, uint32_t word, uint8_t wrap_cons) "CMDQ base: 0x%"PRIx64" cons:%d prod:%d val:0x%x wrap:%d" +smmuv3_cmdq_opcode(const char *opcode) "<--- %s" +smmuv3_cmdq_cfgi_ste(int streamid) " |_ streamid =%d" +smmuv3_cmdq_cfgi_ste_range(int start, int end) " |_ start=0x%d - end=0x%d" +smmuv3_cmdq_tlbi_nh_va(int asid, int vmid, uint64_t addr) " |_ asid =%d vmid =%d addr=0x%"PRIx64 +smmuv3_cmdq_consume_sev(void) "CMD_SYNC CS=SEV not supported, ignoring" +smmuv3_cmdq_consume_out(uint8_t prod_wrap, uint32_t prod, uint8_t cons_wrap, uint32_t cons) "prod_wrap:%d, prod:0x%x cons_wrap:%d cons:0x%x" +smmuv3_update(bool is_empty, uint32_t prod, uint32_t cons, uint8_t prod_wrap, uint8_t cons_wrap) "q empty:%d prod:%d cons:%d p.wrap:%d p.cons:%d" +smmuv3_update_check_cmd(int error) "cmdq not enabled or error :0x%x" +smmuv3_update_irq(bool is_pending, uint32_t gerror, uint32_t gerrorn) "irq pend: %d gerror:0x%x gerrorn:0x%x" +smmuv3_is_ste_consistent(bool cfg, bool granule_supported, bool addr_oor, uint32_t aa64, int s2ha, int s2hd, uint64_t s2ttb ) "config[1]:%d gran:%d addr:%d aa64:%d s2ha:%d s2hd:%d s2ttb:0x%"PRIx64 +smmuv3_find_ste(uint16_t sid, uint32_t features, uint16_t sid_split) "SID:0x%x features:0x%x, sid_split:0x%x" +smmuv3_find_ste_2lvl(uint64_t strtab_base, hwaddr l1ptr, int l1_ste_offset, hwaddr l2ptr, int l2_ste_offset, int max_l2_ste) "strtab_base:0x%lx l1ptr:0x%"PRIx64" l1_off:0x%x, l2ptr:0x%"PRIx64" l2_off:0x%x max_l2_ste:%d" +smmuv3_get_ste(hwaddr addr) "STE addr: 0x%"PRIx64 +smmuv3_translate_bypass(const char *n, uint16_t sid, hwaddr addr, bool is_write) "%s sid=%d bypass iova:0x%"PRIx64" is_write=%d" +smmuv3_translate_in(uint16_t sid, int pci_bus_num, hwaddr strtab_base) "SID:0x%x bus:%d strtab_base:0x%"PRIx64 +smmuv3_get_cd(hwaddr addr) "CD addr: 0x%"PRIx64 +smmuv3_translate_ok(const char *n, uint16_t sid, hwaddr iova, hwaddr translated, int perm) "%s sid=%d iova=0x%"PRIx64" translated=0x%"PRIx64" perm=0x%x" +smmuv3_update_qreg(uint32_t cons, uint64_t val) "cons written : %d val:0x%"PRIx64 +smmuv3_write_mmio(hwaddr addr, uint64_t val, unsigned size) "addr: 0x%"PRIx64" val:0x%"PRIx64" size: 0x%x" +smmuv3_write_mmio_idr(hwaddr addr, uint64_t val) "write to RO/Unimpl reg 0x%lx val64:0x%lx" +smmuv3_write_mmio_evtq_cons_bef_clear(uint32_t prod, uint32_t cons, uint8_t prod_wrap, uint8_t cons_wrap) "Before clearing interrupt prod:0x%x cons:0x%x prod.w:%d cons.w:%d" +smmuv3_write_mmio_evtq_cons_after_clear(uint32_t prod, uint32_t cons, uint8_t prod_wrap, uint8_t cons_wrap) "after clearing interrupt prod:0x%x cons:0x%x prod.w:%d cons.w:%d" +smmuv3_read_mmio(hwaddr addr, uint64_t val, unsigned size) "addr: 0x%"PRIx64" val:0x%"PRIx64" size: 0x%x" +smmuv3_dump_ste(int i, uint32_t word0, int j, uint32_t word1) "STE[%2d]: 0x%x\t STE[%2d]: 0x%x" +smmuv3_dump_cd(int i, uint32_t word0, int j, uint32_t word1) "CD[%2d]: 0x%x\t CD[%2d]: 0x%x" +smmuv3_dump_cmd(int i, uint32_t word0, int j, uint32_t word1) "CMD[%2d]: 0x%x\t CMD[%2d]: 0x%x" +smmuv3_cfg_stage(int s, uint32_t oas, uint32_t tsz, uint64_t ttbr, bool aa64, uint32_t granule_sz, int initial_level) "TransCFG stage:%d oas:%d tsz:%d ttbr:0x%"PRIx64" aa64:%d granule_sz:%d, initial_level = %d" diff --git a/include/hw/arm/smmuv3.h b/include/hw/arm/smmuv3.h new file mode 100644 index 0000000..bdeea1b --- /dev/null +++ b/include/hw/arm/smmuv3.h @@ -0,0 +1,89 @@ +/* + * Copyright (C) 2014-2016 Broadcom Corporation + * Copyright (c) 2017 Red Hat, Inc. + * Written by Prem Mallappa, Eric Auger + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#ifndef HW_ARM_SMMUV3_H +#define HW_ARM_SMMUV3_H + +#include "hw/arm/smmu-common.h" + +#define TYPE_SMMUV3_IOMMU_MEMORY_REGION "smmuv3-iommu-iommu-memory-region" + +#define SMMU_NREGS 0x200 + +typedef struct SMMUQueue { + hwaddr base; + uint32_t prod; + uint32_t cons; + union { + struct { + uint8_t prod:1; + uint8_t cons:1; + }; + uint8_t unused; + } wrap; + + uint16_t entries; /* Number of entries */ + uint8_t ent_size; /* Size of entry in bytes */ + uint8_t shift; /* Size in log2 */ +} SMMUQueue; + +typedef struct SMMUV3State { + SMMUState smmu_state; + +#define SMMU_FEATURE_2LVL_STE (1 << 0) + /* Local cache of most-frequently used register */ + uint32_t features; + uint16_t sid_size; + uint16_t sid_split; + uint64_t strtab_base; + + uint32_t regs[SMMU_NREGS]; + + qemu_irq irq[4]; + + SMMUQueue cmdq, evtq, priq; + + /* IOMMU Address space */ + MemoryRegion iommu; + AddressSpace iommu_as; + /* + * Bus number is not populated in the beginning, hence we need + * a mechanism to retrieve the corresponding address space for each + * pci device. + */ + GHashTable *smmu_as_by_busptr; +} SMMUV3State; + +typedef enum { + SMMU_IRQ_GERROR, + SMMU_IRQ_PRIQ, + SMMU_IRQ_EVTQ, + SMMU_IRQ_CMD_SYNC, +} SMMUIrq; + +typedef struct { + SMMUBaseClass smmu_base_class; +} SMMUV3Class; + +#define TYPE_SMMU_V3_DEV "smmuv3" +#define SMMU_V3_DEV(obj) OBJECT_CHECK(SMMUV3State, (obj), TYPE_SMMU_V3_DEV) +#define SMMU_V3_DEVICE_GET_CLASS(obj) \ + OBJECT_GET_CLASS(SMMUBaseClass, (obj), TYPE_SMMU_V3_DEV) + +#endif -- 2.5.5 From MAILER-DAEMON Fri Aug 11 10:24:05 2017 Received: from list by lists.gnu.org with archive (Exim 4.71) id 1dgAr7-0000JP-Hq for mharc-qemu-arm@gnu.org; Fri, 11 Aug 2017 10:24:05 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:34346) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dgAr5-0000H9-8B for qemu-arm@nongnu.org; Fri, 11 Aug 2017 10:24:04 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dgAr1-00029n-3e for qemu-arm@nongnu.org; Fri, 11 Aug 2017 10:24:03 -0400 Received: from mx1.redhat.com ([209.132.183.28]:13976) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1dgAr0-00029I-Qb; Fri, 11 Aug 2017 10:23:59 -0400 Received: from smtp.corp.redhat.com (int-mx06.intmail.prod.int.phx2.redhat.com [10.5.11.16]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id 90297C050CDA; Fri, 11 Aug 2017 14:23:57 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mx1.redhat.com 90297C050CDA Authentication-Results: ext-mx08.extmail.prod.ext.phx2.redhat.com; dmarc=none (p=none dis=none) header.from=redhat.com Authentication-Results: ext-mx08.extmail.prod.ext.phx2.redhat.com; spf=fail smtp.mailfrom=eric.auger@redhat.com Received: from localhost.localdomain.com (ovpn-116-162.ams2.redhat.com [10.36.116.162]) by smtp.corp.redhat.com (Postfix) with ESMTP id 97625A21B0; Fri, 11 Aug 2017 14:23:46 +0000 (UTC) From: Eric Auger To: eric.auger.pro@gmail.com, eric.auger@redhat.com, peter.maydell@linaro.org, qemu-arm@nongnu.org, qemu-devel@nongnu.org, alex.williamson@redhat.com, prem.mallappa@gmail.com Cc: drjones@redhat.com, christoffer.dall@linaro.org, Radha.Chintakuntla@cavium.com, Sunil.Goutham@cavium.com, mohun106@gmail.com, tcain@qti.qualcomm.com, bharat.bhushan@nxp.com, tn@semihalf.com, mst@redhat.com, will.deacon@arm.com, jean-philippe.brucker@arm.com, robin.murphy@arm.com, peterx@redhat.com, edgar.iglesias@gmail.com Date: Fri, 11 Aug 2017 16:22:28 +0200 Message-Id: <1502461354-11327-4-git-send-email-eric.auger@redhat.com> In-Reply-To: <1502461354-11327-1-git-send-email-eric.auger@redhat.com> References: <1502461354-11327-1-git-send-email-eric.auger@redhat.com> X-Scanned-By: MIMEDefang 2.79 on 10.5.11.16 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.32]); Fri, 11 Aug 2017 14:23:57 +0000 (UTC) X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.132.183.28 Subject: [Qemu-arm] [RFC v6 3/9] hw/arm/virt: Add SMMUv3 to the virt board X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 11 Aug 2017 14:24:05 -0000 From: Prem Mallappa Add code to instantiate an smmu-v3 in mach-virt. A new boolean flag is introduced in VirtMachineState to allow this instantiation. It is currently false. Signed-off-by: Prem Mallappa Signed-off-by: Eric Auger --- v4 -> v5: - add dma-coherent property v2 -> v3: - vbi was removed. Use vms instead - migrate to new smmu binding format (iommu-map) - don't use appendprop anymore - add vms->smmu and guard instantiation with this latter - interrupts type changed to edge --- hw/arm/smmuv3.c | 5 +++-- hw/arm/virt.c | 59 +++++++++++++++++++++++++++++++++++++++++++++++++ include/hw/arm/smmuv3.h | 2 +- include/hw/arm/virt.h | 4 ++++ 4 files changed, 67 insertions(+), 3 deletions(-) diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c index a3199f1..e195a0e 100644 --- a/hw/arm/smmuv3.c +++ b/hw/arm/smmuv3.c @@ -1026,8 +1026,9 @@ static AddressSpace *smmu_find_add_as(PCIBus *bus, void *opaque, int devfn) sdev = sbus->pbdev[devfn]; if (!sdev) { - char *name = g_strdup_printf("%s-%d-%d", TYPE_SMMU_V3_DEV, - pci_bus_num(bus), devfn); + char *name = g_strdup_printf("%s-%d-%d", + TYPE_SMMUV3_IOMMU_MEMORY_REGION, + pci_bus_num(bus), devfn); sdev = sbus->pbdev[devfn] = g_malloc0(sizeof(SMMUDevice)); sdev->smmu = s; diff --git a/hw/arm/virt.c b/hw/arm/virt.c index 6b7a0fe..b9246b9 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -56,6 +56,7 @@ #include "hw/smbios/smbios.h" #include "qapi/visitor.h" #include "standard-headers/linux/input.h" +#include "hw/arm/smmuv3.h" #define DEFINE_VIRT_MACHINE_LATEST(major, minor, latest) \ static void virt_##major##_##minor##_class_init(ObjectClass *oc, \ @@ -139,6 +140,7 @@ static const MemMapEntry a15memmap[] = { [VIRT_FW_CFG] = { 0x09020000, 0x00000018 }, [VIRT_GPIO] = { 0x09030000, 0x00001000 }, [VIRT_SECURE_UART] = { 0x09040000, 0x00001000 }, + [VIRT_SMMU] = { 0x09050000, 0x00020000 }, /* 128K, needed */ [VIRT_MMIO] = { 0x0a000000, 0x00000200 }, /* ...repeating for a total of NUM_VIRTIO_TRANSPORTS, each of that size */ [VIRT_PLATFORM_BUS] = { 0x0c000000, 0x02000000 }, @@ -159,6 +161,7 @@ static const int a15irqmap[] = { [VIRT_SECURE_UART] = 8, [VIRT_MMIO] = 16, /* ...to 16 + NUM_VIRTIO_TRANSPORTS - 1 */ [VIRT_GIC_V2M] = 48, /* ...to 48 + NUM_GICV2M_SPIS - 1 */ + [VIRT_SMMU] = 74, /* ...to 74 + NUM_SMMU_IRQS - 1 */ [VIRT_PLATFORM_BUS] = 112, /* ...to 112 + PLATFORM_BUS_NUM_IRQS -1 */ }; @@ -991,6 +994,53 @@ static void create_pcie_irq_map(const VirtMachineState *vms, 0x7 /* PCI irq */); } +static void alloc_smmu_phandle(VirtMachineState *vms) +{ + if (vms->smmu && !vms->smmu_phandle) { + vms->smmu_phandle = qemu_fdt_alloc_phandle(vms->fdt); + } +} + +static void create_smmu(const VirtMachineState *vms, qemu_irq *pic) +{ + char *smmu; + const char compat[] = "arm,smmu-v3"; + int irq = vms->irqmap[VIRT_SMMU]; + hwaddr base = vms->memmap[VIRT_SMMU].base; + hwaddr size = vms->memmap[VIRT_SMMU].size; + const char irq_names[] = "eventq\0priq\0cmdq-sync\0gerror"; + + if (!vms->smmu) { + return; + } + + sysbus_create_varargs("smmuv3", base, pic[irq], pic[irq + 1], + pic[irq + 2], pic[irq + 3], NULL); + + smmu = g_strdup_printf("/smmuv3@%" PRIx64, base); + qemu_fdt_add_subnode(vms->fdt, smmu); + qemu_fdt_setprop(vms->fdt, smmu, "compatible", compat, sizeof(compat)); + qemu_fdt_setprop_sized_cells(vms->fdt, smmu, "reg", 2, base, 2, size); + + qemu_fdt_setprop_cells(vms->fdt, smmu, "interrupts", + GIC_FDT_IRQ_TYPE_SPI, irq , GIC_FDT_IRQ_FLAGS_EDGE_LO_HI, + GIC_FDT_IRQ_TYPE_SPI, irq + 1, GIC_FDT_IRQ_FLAGS_EDGE_LO_HI, + GIC_FDT_IRQ_TYPE_SPI, irq + 2, GIC_FDT_IRQ_FLAGS_EDGE_LO_HI, + GIC_FDT_IRQ_TYPE_SPI, irq + 3, GIC_FDT_IRQ_FLAGS_EDGE_LO_HI); + + qemu_fdt_setprop(vms->fdt, smmu, "interrupt-names", irq_names, + sizeof(irq_names)); + + qemu_fdt_setprop_cell(vms->fdt, smmu, "clocks", vms->clock_phandle); + qemu_fdt_setprop_string(vms->fdt, smmu, "clock-names", "apb_pclk"); + qemu_fdt_setprop(vms->fdt, smmu, "dma-coherent", NULL, 0); + + qemu_fdt_setprop_cell(vms->fdt, smmu, "#iommu-cells", 1); + + qemu_fdt_setprop_cell(vms->fdt, smmu, "phandle", vms->smmu_phandle); + g_free(smmu); +} + static void create_pcie(const VirtMachineState *vms, qemu_irq *pic) { hwaddr base_mmio = vms->memmap[VIRT_PCIE_MMIO].base; @@ -1103,6 +1153,11 @@ static void create_pcie(const VirtMachineState *vms, qemu_irq *pic) qemu_fdt_setprop_cell(vms->fdt, nodename, "#interrupt-cells", 1); create_pcie_irq_map(vms, vms->gic_phandle, irq, nodename); + if (vms->smmu) { + qemu_fdt_setprop_cells(vms->fdt, nodename, "iommu-map", + 0x0, vms->smmu_phandle, 0x0, 0x10000); + } + g_free(nodename); } @@ -1448,8 +1503,12 @@ static void machvirt_init(MachineState *machine) create_rtc(vms, pic); + alloc_smmu_phandle(vms); + create_pcie(vms, pic); + create_smmu(vms, pic); + create_gpio(vms, pic); /* Create mmio transports, so the user can create virtio backends diff --git a/include/hw/arm/smmuv3.h b/include/hw/arm/smmuv3.h index bdeea1b..dbc5a57 100644 --- a/include/hw/arm/smmuv3.h +++ b/include/hw/arm/smmuv3.h @@ -22,7 +22,7 @@ #include "hw/arm/smmu-common.h" -#define TYPE_SMMUV3_IOMMU_MEMORY_REGION "smmuv3-iommu-iommu-memory-region" +#define TYPE_SMMUV3_IOMMU_MEMORY_REGION "smmuv3-iommu-memory-region" #define SMMU_NREGS 0x200 diff --git a/include/hw/arm/virt.h b/include/hw/arm/virt.h index 33b0ff3..164a531 100644 --- a/include/hw/arm/virt.h +++ b/include/hw/arm/virt.h @@ -38,6 +38,7 @@ #define NUM_GICV2M_SPIS 64 #define NUM_VIRTIO_TRANSPORTS 32 +#define NUM_SMMU_IRQS 4 #define ARCH_GICV3_MAINT_IRQ 9 @@ -59,6 +60,7 @@ enum { VIRT_GIC_V2M, VIRT_GIC_ITS, VIRT_GIC_REDIST, + VIRT_SMMU, VIRT_UART, VIRT_MMIO, VIRT_RTC, @@ -95,6 +97,7 @@ typedef struct { bool highmem; bool its; bool virt; + bool smmu; int32_t gic_version; struct arm_boot_info bootinfo; const MemMapEntry *memmap; @@ -105,6 +108,7 @@ typedef struct { uint32_t clock_phandle; uint32_t gic_phandle; uint32_t msi_phandle; + uint32_t smmu_phandle; int psci_conduit; } VirtMachineState; -- 2.5.5 From MAILER-DAEMON Fri Aug 11 10:24:36 2017 Received: from list by lists.gnu.org with archive (Exim 4.71) id 1dgArc-0000jj-9Y for mharc-qemu-arm@gnu.org; Fri, 11 Aug 2017 10:24:36 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:34606) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dgArY-0000hy-1q for qemu-arm@nongnu.org; Fri, 11 Aug 2017 10:24:34 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dgArT-0002N1-U4 for qemu-arm@nongnu.org; Fri, 11 Aug 2017 10:24:32 -0400 Received: from mx1.redhat.com ([209.132.183.28]:56600) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1dgArT-0002Mg-Le; Fri, 11 Aug 2017 10:24:27 -0400 Received: from smtp.corp.redhat.com (int-mx06.intmail.prod.int.phx2.redhat.com [10.5.11.16]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id 8A9F2B17E; Fri, 11 Aug 2017 14:24:26 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mx1.redhat.com 8A9F2B17E Authentication-Results: ext-mx06.extmail.prod.ext.phx2.redhat.com; dmarc=none (p=none dis=none) header.from=redhat.com Authentication-Results: ext-mx06.extmail.prod.ext.phx2.redhat.com; spf=fail smtp.mailfrom=eric.auger@redhat.com Received: from localhost.localdomain.com (ovpn-116-162.ams2.redhat.com [10.36.116.162]) by smtp.corp.redhat.com (Postfix) with ESMTP id E53A2A01E5; Fri, 11 Aug 2017 14:23:57 +0000 (UTC) From: Eric Auger To: eric.auger.pro@gmail.com, eric.auger@redhat.com, peter.maydell@linaro.org, qemu-arm@nongnu.org, qemu-devel@nongnu.org, alex.williamson@redhat.com, prem.mallappa@gmail.com Cc: drjones@redhat.com, christoffer.dall@linaro.org, Radha.Chintakuntla@cavium.com, Sunil.Goutham@cavium.com, mohun106@gmail.com, tcain@qti.qualcomm.com, bharat.bhushan@nxp.com, tn@semihalf.com, mst@redhat.com, will.deacon@arm.com, jean-philippe.brucker@arm.com, robin.murphy@arm.com, peterx@redhat.com, edgar.iglesias@gmail.com Date: Fri, 11 Aug 2017 16:22:29 +0200 Message-Id: <1502461354-11327-5-git-send-email-eric.auger@redhat.com> In-Reply-To: <1502461354-11327-1-git-send-email-eric.auger@redhat.com> References: <1502461354-11327-1-git-send-email-eric.auger@redhat.com> X-Scanned-By: MIMEDefang 2.79 on 10.5.11.16 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.30]); Fri, 11 Aug 2017 14:24:26 +0000 (UTC) X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.132.183.28 Subject: [Qemu-arm] [RFC v6 4/9] hw/arm/virt: Add 2.11 machine type X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 11 Aug 2017 14:24:35 -0000 The new machine type allows smmuv3 instantiation. A new option is introduced to turn the feature on/off (off by default). Signed-off-by: Eric Auger --- v5 -> v6: machine 2_11 Another alternative would be to use the -device option as done on x86. As the smmu is a sysbus device, we would need to use the platform bus framework. --- hw/arm/virt.c | 50 ++++++++++++++++++++++++++++++++++++++++++++++++-- include/hw/arm/virt.h | 1 + include/hw/compat.h | 3 +++ 3 files changed, 52 insertions(+), 2 deletions(-) diff --git a/hw/arm/virt.c b/hw/arm/virt.c index b9246b9..b758173 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -1543,6 +1543,20 @@ static void machvirt_init(MachineState *machine) create_platform_bus(vms, pic); } +static bool virt_get_smmu(Object *obj, Error **errp) +{ + VirtMachineState *vms = VIRT_MACHINE(obj); + + return vms->smmu; +} + +static void virt_set_smmu(Object *obj, bool value, Error **errp) +{ + VirtMachineState *vms = VIRT_MACHINE(obj); + + vms->smmu = value; +} + static bool virt_get_secure(Object *obj, Error **errp) { VirtMachineState *vms = VIRT_MACHINE(obj); @@ -1698,7 +1712,7 @@ static void machvirt_machine_init(void) } type_init(machvirt_machine_init); -static void virt_2_10_instance_init(Object *obj) +static void virt_2_11_instance_init(Object *obj) { VirtMachineState *vms = VIRT_MACHINE(obj); VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms); @@ -1754,14 +1768,46 @@ static void virt_2_10_instance_init(Object *obj) NULL); } + if (vmc->no_smmu) { + vms->smmu = false; + } else { + /* Default disallows smmu instantiation */ + vms->smmu = false; + object_property_add_bool(obj, "smmu", virt_get_smmu, + virt_set_smmu, NULL); + object_property_set_description(obj, "smmu", + "Set on/off to enable/disable " + "smmu instantiation (default off)", + NULL); + } + vms->memmap = a15memmap; vms->irqmap = a15irqmap; } +static void virt_machine_2_11_options(MachineClass *mc) +{ +} +DEFINE_VIRT_MACHINE_AS_LATEST(2, 11) + +#define VIRT_COMPAT_2_10 \ + HW_COMPAT_2_10 + +static void virt_2_10_instance_init(Object *obj) +{ + virt_2_11_instance_init(obj); +} + static void virt_machine_2_10_options(MachineClass *mc) { + VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc)); + + virt_machine_2_11_options(mc); + SET_MACHINE_COMPAT(mc, VIRT_COMPAT_2_10); + + vmc->no_smmu = true; } -DEFINE_VIRT_MACHINE_AS_LATEST(2, 10) +DEFINE_VIRT_MACHINE(2, 10) #define VIRT_COMPAT_2_9 \ HW_COMPAT_2_9 diff --git a/include/hw/arm/virt.h b/include/hw/arm/virt.h index 164a531..cd2c82e 100644 --- a/include/hw/arm/virt.h +++ b/include/hw/arm/virt.h @@ -86,6 +86,7 @@ typedef struct { bool disallow_affinity_adjustment; bool no_its; bool no_pmu; + bool no_smmu; bool claim_edge_triggered_timers; } VirtMachineClass; diff --git a/include/hw/compat.h b/include/hw/compat.h index 08f3600..3e101f8 100644 --- a/include/hw/compat.h +++ b/include/hw/compat.h @@ -1,6 +1,9 @@ #ifndef HW_COMPAT_H #define HW_COMPAT_H +#define HW_COMPAT_2_10 \ + /* empty */ + #define HW_COMPAT_2_9 \ {\ .driver = "pci-bridge",\ -- 2.5.5 From MAILER-DAEMON Fri Aug 11 10:24:53 2017 Received: from list by lists.gnu.org with archive (Exim 4.71) id 1dgArt-00010F-Gq for mharc-qemu-arm@gnu.org; Fri, 11 Aug 2017 10:24:53 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:34741) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dgArq-0000xu-SG for qemu-arm@nongnu.org; Fri, 11 Aug 2017 10:24:52 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dgArm-0002Rz-Lh for qemu-arm@nongnu.org; Fri, 11 Aug 2017 10:24:50 -0400 Received: from mx1.redhat.com ([209.132.183.28]:45358) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1dgArm-0002Rc-CA; Fri, 11 Aug 2017 10:24:46 -0400 Received: from smtp.corp.redhat.com (int-mx06.intmail.prod.int.phx2.redhat.com [10.5.11.16]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id 48B3660145; Fri, 11 Aug 2017 14:24:45 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mx1.redhat.com 48B3660145 Authentication-Results: ext-mx01.extmail.prod.ext.phx2.redhat.com; dmarc=none (p=none dis=none) header.from=redhat.com Authentication-Results: ext-mx01.extmail.prod.ext.phx2.redhat.com; spf=fail smtp.mailfrom=eric.auger@redhat.com Received: from localhost.localdomain.com (ovpn-116-162.ams2.redhat.com [10.36.116.162]) by smtp.corp.redhat.com (Postfix) with ESMTP id E100B99DD7; Fri, 11 Aug 2017 14:24:26 +0000 (UTC) From: Eric Auger To: eric.auger.pro@gmail.com, eric.auger@redhat.com, peter.maydell@linaro.org, qemu-arm@nongnu.org, qemu-devel@nongnu.org, alex.williamson@redhat.com, prem.mallappa@gmail.com Cc: drjones@redhat.com, christoffer.dall@linaro.org, Radha.Chintakuntla@cavium.com, Sunil.Goutham@cavium.com, mohun106@gmail.com, tcain@qti.qualcomm.com, bharat.bhushan@nxp.com, tn@semihalf.com, mst@redhat.com, will.deacon@arm.com, jean-philippe.brucker@arm.com, robin.murphy@arm.com, peterx@redhat.com, edgar.iglesias@gmail.com Date: Fri, 11 Aug 2017 16:22:30 +0200 Message-Id: <1502461354-11327-6-git-send-email-eric.auger@redhat.com> In-Reply-To: <1502461354-11327-1-git-send-email-eric.auger@redhat.com> References: <1502461354-11327-1-git-send-email-eric.auger@redhat.com> X-Scanned-By: MIMEDefang 2.79 on 10.5.11.16 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.25]); Fri, 11 Aug 2017 14:24:45 +0000 (UTC) X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.132.183.28 Subject: [Qemu-arm] [RFC v6 5/9] hw/arm/virt-acpi-build: Add smmuv3 node in IORT table X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 11 Aug 2017 14:24:52 -0000 From: Prem Mallappa This patch builds the smmuv3 node in the ACPI IORT table. The RID space of the root complex, which spans 0x0-0x10000 maps to streamid space 0x0-0x10000 in smmuv3, which in turn maps to deviceid space 0x0-0x10000 in the ITS group. The guest must feature the IOMMU probe deferral series (https://lkml.org/lkml/2017/4/10/214) wich fixes streamid multiple lookup. This bug is not related to the SMMU emulation. Signed-off-by: Prem Mallappa Signed-off-by: Eric Auger --- v2 -> v3: - integrate into the existing IORT table made up of ITS, RC nodes - take into account vms->smmu - match linux actbl2.h acpi_iort_smmu_v3 field names --- hw/arm/virt-acpi-build.c | 56 +++++++++++++++++++++++++++++++++++++++------ include/hw/acpi/acpi-defs.h | 15 ++++++++++++ 2 files changed, 64 insertions(+), 7 deletions(-) diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c index 3d78ff6..ac2cd3e 100644 --- a/hw/arm/virt-acpi-build.c +++ b/hw/arm/virt-acpi-build.c @@ -393,19 +393,26 @@ build_rsdp(GArray *rsdp_table, BIOSLinker *linker, unsigned xsdt_tbl_offset) } static void -build_iort(GArray *table_data, BIOSLinker *linker) +build_iort(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms) { - int iort_start = table_data->len; + int nb_nodes, iort_start = table_data->len; AcpiIortIdMapping *idmap; AcpiIortItsGroup *its; AcpiIortTable *iort; - size_t node_size, iort_length; + AcpiIortSmmu3 *smmu; + size_t node_size, iort_length, smmu_offset = 0; AcpiIortRC *rc; iort = acpi_data_push(table_data, sizeof(*iort)); + if (vms->smmu) { + nb_nodes = 3; /* RC, ITS, SMMUv3 */ + } else { + nb_nodes = 2; /* RC, ITS */ + } + iort_length = sizeof(*iort); - iort->node_count = cpu_to_le32(2); /* RC and ITS nodes */ + iort->node_count = cpu_to_le32(nb_nodes); iort->node_offset = cpu_to_le32(sizeof(*iort)); /* ITS group node */ @@ -418,6 +425,35 @@ build_iort(GArray *table_data, BIOSLinker *linker) its->its_count = cpu_to_le32(1); its->identifiers[0] = 0; /* MADT translation_id */ + if (vms->smmu) { + int irq = vms->irqmap[VIRT_SMMU]; + + /* SMMUv3 node */ + smmu_offset = cpu_to_le32(iort->node_offset + node_size); + node_size = sizeof(*smmu) + sizeof(*idmap); + iort_length += node_size; + smmu = acpi_data_push(table_data, node_size); + + + smmu->type = ACPI_IORT_NODE_SMMU_V3; + smmu->length = cpu_to_le16(node_size); + smmu->mapping_count = cpu_to_le32(1); + smmu->mapping_offset = cpu_to_le32(sizeof(*smmu)); + smmu->base_address = cpu_to_le64(vms->memmap[VIRT_SMMU].base); + smmu->event_gsiv = cpu_to_le32(irq); + smmu->pri_gsiv = cpu_to_le32(irq + 1); + smmu->gerr_gsiv = cpu_to_le32(irq + 2); + smmu->sync_gsiv = cpu_to_le32(irq + 3); + + /* Identity RID mapping covering the whole input RID range */ + idmap = &smmu->id_mapping_array[0]; + idmap->input_base = 0; + idmap->id_count = cpu_to_le32(0xFFFF); + idmap->output_base = 0; + /* output IORT node is the ITS group node (the first node) */ + idmap->output_reference = cpu_to_le32(iort->node_offset); + } + /* Root Complex Node */ node_size = sizeof(*rc) + sizeof(*idmap); iort_length += node_size; @@ -438,8 +474,14 @@ build_iort(GArray *table_data, BIOSLinker *linker) idmap->input_base = 0; idmap->id_count = cpu_to_le32(0xFFFF); idmap->output_base = 0; - /* output IORT node is the ITS group node (the first node) */ - idmap->output_reference = cpu_to_le32(iort->node_offset); + + if (vms->smmu) { + /* output IORT node is the smmuv3 node */ + idmap->output_reference = cpu_to_le32(smmu_offset); + } else { + /* output IORT node is the ITS group node (the first node) */ + idmap->output_reference = cpu_to_le32(iort->node_offset); + } iort->length = cpu_to_le32(iort_length); @@ -782,7 +824,7 @@ void virt_acpi_build(VirtMachineState *vms, AcpiBuildTables *tables) if (its_class_name() && !vmc->no_its) { acpi_add_table(table_offsets, tables_blob); - build_iort(tables_blob, tables->linker); + build_iort(tables_blob, tables->linker, vms); } /* XSDT is pointed to by RSDP */ diff --git a/include/hw/acpi/acpi-defs.h b/include/hw/acpi/acpi-defs.h index 72be675..69307b7 100644 --- a/include/hw/acpi/acpi-defs.h +++ b/include/hw/acpi/acpi-defs.h @@ -697,6 +697,21 @@ struct AcpiIortItsGroup { } QEMU_PACKED; typedef struct AcpiIortItsGroup AcpiIortItsGroup; +struct AcpiIortSmmu3 { + ACPI_IORT_NODE_HEADER_DEF + uint64_t base_address; + uint32_t flags; + uint32_t reserved2; + uint64_t vatos_address; + uint32_t model; + uint32_t event_gsiv; + uint32_t pri_gsiv; + uint32_t gerr_gsiv; + uint32_t sync_gsiv; + AcpiIortIdMapping id_mapping_array[0]; +} QEMU_PACKED; +typedef struct AcpiIortSmmu3 AcpiIortSmmu3; + struct AcpiIortRC { ACPI_IORT_NODE_HEADER_DEF AcpiIortMemoryAccess memory_properties; -- 2.5.5 From MAILER-DAEMON Fri Aug 11 10:25:02 2017 Received: from list by lists.gnu.org with archive (Exim 4.71) id 1dgAs2-00017R-NA for mharc-qemu-arm@gnu.org; Fri, 11 Aug 2017 10:25:02 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:34815) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dgAs0-00015J-66 for qemu-arm@nongnu.org; Fri, 11 Aug 2017 10:25:01 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dgArw-0002WG-1W for qemu-arm@nongnu.org; Fri, 11 Aug 2017 10:25:00 -0400 Received: from mx1.redhat.com ([209.132.183.28]:37882) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1dgArv-0002W6-R4; Fri, 11 Aug 2017 10:24:55 -0400 Received: from smtp.corp.redhat.com (int-mx06.intmail.prod.int.phx2.redhat.com [10.5.11.16]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id B4ECFFFCB8; Fri, 11 Aug 2017 14:24:54 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mx1.redhat.com B4ECFFFCB8 Authentication-Results: ext-mx09.extmail.prod.ext.phx2.redhat.com; dmarc=none (p=none dis=none) header.from=redhat.com Authentication-Results: ext-mx09.extmail.prod.ext.phx2.redhat.com; spf=fail smtp.mailfrom=eric.auger@redhat.com Received: from localhost.localdomain.com (ovpn-116-162.ams2.redhat.com [10.36.116.162]) by smtp.corp.redhat.com (Postfix) with ESMTP id 9EB9DA01F2; Fri, 11 Aug 2017 14:24:45 +0000 (UTC) From: Eric Auger To: eric.auger.pro@gmail.com, eric.auger@redhat.com, peter.maydell@linaro.org, qemu-arm@nongnu.org, qemu-devel@nongnu.org, alex.williamson@redhat.com, prem.mallappa@gmail.com Cc: drjones@redhat.com, christoffer.dall@linaro.org, Radha.Chintakuntla@cavium.com, Sunil.Goutham@cavium.com, mohun106@gmail.com, tcain@qti.qualcomm.com, bharat.bhushan@nxp.com, tn@semihalf.com, mst@redhat.com, will.deacon@arm.com, jean-philippe.brucker@arm.com, robin.murphy@arm.com, peterx@redhat.com, edgar.iglesias@gmail.com Date: Fri, 11 Aug 2017 16:22:31 +0200 Message-Id: <1502461354-11327-7-git-send-email-eric.auger@redhat.com> In-Reply-To: <1502461354-11327-1-git-send-email-eric.auger@redhat.com> References: <1502461354-11327-1-git-send-email-eric.auger@redhat.com> X-Scanned-By: MIMEDefang 2.79 on 10.5.11.16 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.38]); Fri, 11 Aug 2017 14:24:54 +0000 (UTC) X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.132.183.28 Subject: [Qemu-arm] [RFC v6 6/9] hw/arm/virt: Add tlbi-on-map property to the smmuv3 node X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 11 Aug 2017 14:25:01 -0000 For VFIO integration we need to update physical IOMMU mappings each time the guest updates the vIOMMU translation structures. For that, we rely on a special smmuv3 option, "tlbi-on-map" which forces TLB invalidations on map (this mode is similar to the Intel VTD caching Mode). The smmuv3 driver then sends SMMU_CMD_TLBI_NH_VA commands, upon which we will update the physical mappings. Signed-off-by: Eric Auger --- hw/arm/virt.c | 1 + 1 file changed, 1 insertion(+) diff --git a/hw/arm/virt.c b/hw/arm/virt.c index b758173..c2ac8c6 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -1034,6 +1034,7 @@ static void create_smmu(const VirtMachineState *vms, qemu_irq *pic) qemu_fdt_setprop_cell(vms->fdt, smmu, "clocks", vms->clock_phandle); qemu_fdt_setprop_string(vms->fdt, smmu, "clock-names", "apb_pclk"); qemu_fdt_setprop(vms->fdt, smmu, "dma-coherent", NULL, 0); + qemu_fdt_setprop(vms->fdt, smmu, "tlbi-on-map", NULL, 0); qemu_fdt_setprop_cell(vms->fdt, smmu, "#iommu-cells", 1); -- 2.5.5 From MAILER-DAEMON Fri Aug 11 10:25:16 2017 Received: from list by lists.gnu.org with archive (Exim 4.71) id 1dgAsG-0001Lg-7m for mharc-qemu-arm@gnu.org; Fri, 11 Aug 2017 10:25:16 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:34925) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dgAsD-0001JK-Md for qemu-arm@nongnu.org; Fri, 11 Aug 2017 10:25:15 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dgAsC-0002gw-Fo for qemu-arm@nongnu.org; Fri, 11 Aug 2017 10:25:13 -0400 Received: from mx1.redhat.com ([209.132.183.28]:30905) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1dgAsC-0002g8-7F; Fri, 11 Aug 2017 10:25:12 -0400 Received: from smtp.corp.redhat.com (int-mx06.intmail.prod.int.phx2.redhat.com [10.5.11.16]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id F2D272C96EB; Fri, 11 Aug 2017 14:25:10 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mx1.redhat.com F2D272C96EB Authentication-Results: ext-mx05.extmail.prod.ext.phx2.redhat.com; dmarc=none (p=none dis=none) header.from=redhat.com Authentication-Results: ext-mx05.extmail.prod.ext.phx2.redhat.com; spf=fail smtp.mailfrom=eric.auger@redhat.com Received: from localhost.localdomain.com (ovpn-116-162.ams2.redhat.com [10.36.116.162]) by smtp.corp.redhat.com (Postfix) with ESMTP id 153EFA01F2; Fri, 11 Aug 2017 14:24:54 +0000 (UTC) From: Eric Auger To: eric.auger.pro@gmail.com, eric.auger@redhat.com, peter.maydell@linaro.org, qemu-arm@nongnu.org, qemu-devel@nongnu.org, alex.williamson@redhat.com, prem.mallappa@gmail.com Cc: drjones@redhat.com, christoffer.dall@linaro.org, Radha.Chintakuntla@cavium.com, Sunil.Goutham@cavium.com, mohun106@gmail.com, tcain@qti.qualcomm.com, bharat.bhushan@nxp.com, tn@semihalf.com, mst@redhat.com, will.deacon@arm.com, jean-philippe.brucker@arm.com, robin.murphy@arm.com, peterx@redhat.com, edgar.iglesias@gmail.com Date: Fri, 11 Aug 2017 16:22:32 +0200 Message-Id: <1502461354-11327-8-git-send-email-eric.auger@redhat.com> In-Reply-To: <1502461354-11327-1-git-send-email-eric.auger@redhat.com> References: <1502461354-11327-1-git-send-email-eric.auger@redhat.com> X-Scanned-By: MIMEDefang 2.79 on 10.5.11.16 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.29]); Fri, 11 Aug 2017 14:25:11 +0000 (UTC) X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.132.183.28 Subject: [Qemu-arm] [RFC v6 7/9] target/arm/kvm: Translate the MSI doorbell in kvm_arch_fixup_msi_route X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 11 Aug 2017 14:25:15 -0000 In case the MSI is translated by an IOMMU we need to fixup the MSI route with the translated address. Signed-off-by: Eric Auger --- v5 -> v6: - use IOMMUMemoryRegionClass API It is still unclear to me if we need to register an IOMMUNotifier to handle any change in the MSI doorbell which would occur behind the scene and would not lead to any call to kvm_arch_fixup_msi_route(). --- target/arm/kvm.c | 27 +++++++++++++++++++++++++++ target/arm/trace-events | 3 +++ 2 files changed, 30 insertions(+) diff --git a/target/arm/kvm.c b/target/arm/kvm.c index 7c17f0d..a2fa948 100644 --- a/target/arm/kvm.c +++ b/target/arm/kvm.c @@ -20,8 +20,13 @@ #include "sysemu/kvm.h" #include "kvm_arm.h" #include "cpu.h" +#include "trace.h" #include "internals.h" #include "hw/arm/arm.h" +#include "hw/pci/pci.h" +#include "hw/pci/msi.h" +#include "hw/arm/smmu-common.h" +#include "hw/arm/smmuv3.h" #include "exec/memattrs.h" #include "exec/address-spaces.h" #include "hw/boards.h" @@ -662,6 +667,28 @@ int kvm_arm_vgic_probe(void) int kvm_arch_fixup_msi_route(struct kvm_irq_routing_entry *route, uint64_t address, uint32_t data, PCIDevice *dev) { + AddressSpace *as = pci_device_iommu_address_space(dev); + IOMMUMemoryRegionClass *imrc; + IOMMUTLBEntry entry; + SMMUDevice *sdev; + + if (as == &address_space_memory) { + return 0; + } + + /* MSI doorbell address is translated by an IOMMU */ + sdev = container_of(as, SMMUDevice, as); + imrc = IOMMU_MEMORY_REGION_GET_CLASS(&sdev->iommu); + + entry = imrc->translate(&sdev->iommu, address, IOMMU_WO); + + route->u.msi.address_lo = entry.translated_addr; + route->u.msi.address_hi = entry.translated_addr >> 32; + + trace_kvm_arm_fixup_msi_route(address, sdev->devfn, + sdev->iommu.parent_obj.name, + entry.translated_addr); + return 0; } diff --git a/target/arm/trace-events b/target/arm/trace-events index 9e37131..8b3c220 100644 --- a/target/arm/trace-events +++ b/target/arm/trace-events @@ -8,3 +8,6 @@ arm_gt_tval_write(int timer, uint64_t value) "gt_tval_write: timer %d value 0x%" arm_gt_ctl_write(int timer, uint64_t value) "gt_ctl_write: timer %d value 0x%" PRIx64 arm_gt_imask_toggle(int timer, int irqstate) "gt_ctl_write: timer %d IMASK toggle, new irqstate %d" arm_gt_cntvoff_write(uint64_t value) "gt_cntvoff_write: value 0x%" PRIx64 + +# target/arm/kvm.c +kvm_arm_fixup_msi_route(uint64_t iova, uint32_t devid, const char *name, uint64_t gpa) "MSI addr = 0x%"PRIx64" is translated for devfn=%d through %s into 0x%"PRIx64 -- 2.5.5 From MAILER-DAEMON Fri Aug 11 10:25:40 2017 Received: from list by lists.gnu.org with archive (Exim 4.71) id 1dgAsd-0001g8-UC for mharc-qemu-arm@gnu.org; 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dmarc=none (p=none dis=none) header.from=redhat.com Authentication-Results: ext-mx04.extmail.prod.ext.phx2.redhat.com; spf=fail smtp.mailfrom=eric.auger@redhat.com Received: from localhost.localdomain.com (ovpn-116-162.ams2.redhat.com [10.36.116.162]) by smtp.corp.redhat.com (Postfix) with ESMTP id 57D69A01F2; Fri, 11 Aug 2017 14:25:11 +0000 (UTC) From: Eric Auger To: eric.auger.pro@gmail.com, eric.auger@redhat.com, peter.maydell@linaro.org, qemu-arm@nongnu.org, qemu-devel@nongnu.org, alex.williamson@redhat.com, prem.mallappa@gmail.com Cc: drjones@redhat.com, christoffer.dall@linaro.org, Radha.Chintakuntla@cavium.com, Sunil.Goutham@cavium.com, mohun106@gmail.com, tcain@qti.qualcomm.com, bharat.bhushan@nxp.com, tn@semihalf.com, mst@redhat.com, will.deacon@arm.com, jean-philippe.brucker@arm.com, robin.murphy@arm.com, peterx@redhat.com, edgar.iglesias@gmail.com Date: Fri, 11 Aug 2017 16:22:33 +0200 Message-Id: <1502461354-11327-9-git-send-email-eric.auger@redhat.com> In-Reply-To: <1502461354-11327-1-git-send-email-eric.auger@redhat.com> References: <1502461354-11327-1-git-send-email-eric.auger@redhat.com> X-Scanned-By: MIMEDefang 2.79 on 10.5.11.16 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.28]); Fri, 11 Aug 2017 14:25:31 +0000 (UTC) X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.132.183.28 Subject: [Qemu-arm] [RFC v6 8/9] hw/arm/smmuv3: VFIO integration X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 11 Aug 2017 14:25:39 -0000 This patch allows doing PCIe passthrough with a guest exposed with a vSMMUv3. It implements the replay and notify_flag_changed iommu ops. Also on TLB and data structure invalidation commands, we replay the mappings so that the physical IOMMU implements updated stage 1 settings (Guest IOVA -> Guest PA) + stage 2 settings. This works only if the guest smmuv3 driver implements the "tlbi-on-map" option. Signed-off-by: Eric Auger --- v5 -> v6: - use IOMMUMemoryRegion - handle implementation defined SMMU_CMD_TLBI_NH_VA_AM cmd (goes along with TLBI_ON_MAP FW quirk) - replay systematically unmap the whole range first - smmuv3_map_hook does not unmap anymore and the unmap is done before the replay - add and use smmuv3_context_device_invalidate instead of blindly replaying everything --- hw/arm/smmuv3-internal.h | 1 + hw/arm/smmuv3.c | 265 ++++++++++++++++++++++++++++++++++++++++++++++- hw/arm/trace-events | 14 +++ 3 files changed, 277 insertions(+), 3 deletions(-) diff --git a/hw/arm/smmuv3-internal.h b/hw/arm/smmuv3-internal.h index e255df1..ac4628f 100644 --- a/hw/arm/smmuv3-internal.h +++ b/hw/arm/smmuv3-internal.h @@ -344,6 +344,7 @@ enum { SMMU_CMD_RESUME = 0x44, SMMU_CMD_STALL_TERM, SMMU_CMD_SYNC, /* 0x46 */ + SMMU_CMD_TLBI_NH_VA_AM = 0x8F, /* VIOMMU Impl Defined */ }; static const char *cmd_stringify[] = { diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c index e195a0e..89fb116 100644 --- a/hw/arm/smmuv3.c +++ b/hw/arm/smmuv3.c @@ -25,6 +25,7 @@ #include "exec/address-spaces.h" #include "trace.h" #include "qemu/error-report.h" +#include "exec/target_page.h" #include "hw/arm/smmuv3.h" #include "smmuv3-internal.h" @@ -143,6 +144,71 @@ static MemTxResult smmu_read_cmdq(SMMUV3State *s, Cmd *cmd) return ret; } +static void smmuv3_replay_all(SMMUState *s) +{ + SMMUNotifierNode *node; + + QLIST_FOREACH(node, &s->notifiers_list, next) { + trace_smmuv3_replay_all(node->sdev->iommu.parent_obj.name); + memory_region_iommu_replay_all(&node->sdev->iommu); + } +} + +/* Replay the mappings for a given streamid */ +static void smmuv3_context_device_invalidate(SMMUState *s, uint16_t sid) +{ + uint8_t bus_n, devfn; + SMMUPciBus *smmu_bus; + SMMUDevice *smmu; + + trace_smmuv3_context_device_invalidate(sid); + bus_n = PCI_BUS_NUM(sid); + smmu_bus = smmu_find_as_from_bus_num(s, bus_n); + if (smmu_bus) { + devfn = PCI_FUNC(sid); + smmu = smmu_bus->pbdev[devfn]; + if (smmu) { + memory_region_iommu_replay_all(&smmu->iommu); + } + } +} + +static void smmuv3_replay_single(IOMMUMemoryRegion *mr, IOMMUNotifier *n, + uint64_t iova); + +static void smmuv3_replay_range(IOMMUMemoryRegion *mr, IOMMUNotifier *n, + uint64_t iova, size_t nb_pages); + +static void smmuv3_notify_single(SMMUState *s, uint64_t iova) +{ + SMMUNotifierNode *node; + + QLIST_FOREACH(node, &s->notifiers_list, next) { + IOMMUMemoryRegion *mr = &node->sdev->iommu; + IOMMUNotifier *n; + + trace_smmuv3_notify_all(node->sdev->iommu.parent_obj.name, iova); + IOMMU_NOTIFIER_FOREACH(n, mr) { + smmuv3_replay_single(mr, n, iova); + } + } +} + +static void smmuv3_notify_range(SMMUState *s, uint64_t iova, size_t size) +{ + SMMUNotifierNode *node; + + QLIST_FOREACH(node, &s->notifiers_list, next) { + IOMMUMemoryRegion *mr = &node->sdev->iommu; + IOMMUNotifier *n; + + trace_smmuv3_notify_all(node->sdev->iommu.parent_obj.name, iova); + IOMMU_NOTIFIER_FOREACH(n, mr) { + smmuv3_replay_range(mr, n, iova, size); + } + } +} + static int smmu_cmdq_consume(SMMUV3State *s) { uint32_t error = SMMU_CMD_ERR_NONE; @@ -178,28 +244,38 @@ static int smmu_cmdq_consume(SMMUV3State *s) break; case SMMU_CMD_PREFETCH_CONFIG: case SMMU_CMD_PREFETCH_ADDR: + break; case SMMU_CMD_CFGI_STE: { uint32_t streamid = cmd.word[1]; trace_smmuv3_cmdq_cfgi_ste(streamid); - break; + smmuv3_context_device_invalidate(&s->smmu_state, streamid); + break; } case SMMU_CMD_CFGI_STE_RANGE: /* same as SMMU_CMD_CFGI_ALL */ { - uint32_t start = cmd.word[1], range, end; + uint32_t start = cmd.word[1], range, end, i; range = extract32(cmd.word[2], 0, 5); end = start + (1 << (range + 1)) - 1; trace_smmuv3_cmdq_cfgi_ste_range(start, end); + for (i = start; i <= end; i++) { + smmuv3_context_device_invalidate(&s->smmu_state, i); + } break; } case SMMU_CMD_CFGI_CD: case SMMU_CMD_CFGI_CD_ALL: + { + uint32_t streamid = cmd.word[1]; + + smmuv3_context_device_invalidate(&s->smmu_state, streamid); break; + } case SMMU_CMD_TLBI_NH_ALL: case SMMU_CMD_TLBI_NH_ASID: - printf("%s TLBI* replay\n", __func__); + smmuv3_replay_all(&s->smmu_state); break; case SMMU_CMD_TLBI_NH_VA: { @@ -210,6 +286,20 @@ static int smmu_cmdq_consume(SMMUV3State *s) uint64_t addr = high << 32 | (low << 12); trace_smmuv3_cmdq_tlbi_nh_va(asid, vmid, addr); + smmuv3_notify_single(&s->smmu_state, addr); + break; + } + case SMMU_CMD_TLBI_NH_VA_AM: + { + int asid = extract32(cmd.word[1], 16, 16); + int am = extract32(cmd.word[1], 0, 16); + uint64_t low = extract32(cmd.word[2], 12, 20); + uint64_t high = cmd.word[3]; + uint64_t addr = high << 32 | (low << 12); + size_t size = am << 12; + + trace_smmuv3_cmdq_tlbi_nh_va_am(asid, am, addr, size); + smmuv3_notify_range(&s->smmu_state, addr, size); break; } case SMMU_CMD_TLBI_NH_VAA: @@ -222,6 +312,7 @@ static int smmu_cmdq_consume(SMMUV3State *s) case SMMU_CMD_TLBI_S12_VMALL: case SMMU_CMD_TLBI_S2_IPA: case SMMU_CMD_TLBI_NSNH_ALL: + smmuv3_replay_all(&s->smmu_state); break; case SMMU_CMD_ATC_INV: case SMMU_CMD_PRI_RESP: @@ -804,6 +895,172 @@ out: return entry; } +static int smmuv3_replay_hook(IOMMUTLBEntry *entry, void *private) +{ + trace_smmuv3_replay_hook(entry->iova, entry->translated_addr, + entry->addr_mask, entry->perm); + memory_region_notify_one((IOMMUNotifier *)private, entry); + return 0; +} + +static int smmuv3_map_hook(IOMMUTLBEntry *entry, void *private) +{ + trace_smmuv3_map_hook(entry->iova, entry->translated_addr, + entry->addr_mask, entry->perm); + memory_region_notify_one((IOMMUNotifier *)private, entry); + return 0; +} + +/* Unmap the whole range in the notifier's scope. */ +static void smmuv3_unmap_notifier(SMMUDevice *sdev, IOMMUNotifier *n) +{ + IOMMUTLBEntry entry; + hwaddr size; + hwaddr start = n->start; + hwaddr end = n->end; + + size = end - start + 1; + + entry.target_as = &address_space_memory; + /* Adjust iova for the size */ + entry.iova = n->start & ~(size - 1); + /* This field is meaningless for unmap */ + entry.translated_addr = 0; + entry.perm = IOMMU_NONE; + entry.addr_mask = size - 1; + + /* TODO: check start/end/size/mask */ + + trace_smmuv3_unmap_notifier(pci_bus_num(sdev->bus), + PCI_SLOT(sdev->devfn), + PCI_FUNC(sdev->devfn), + entry.iova, size); + + memory_region_notify_one(n, &entry); +} + +static void smmuv3_replay(IOMMUMemoryRegion *mr, IOMMUNotifier *n) +{ + SMMUDevice *sdev = container_of(mr, SMMUDevice, iommu); + SMMUV3State *s = sdev->smmu; + SMMUBaseClass *sbc = SMMU_DEVICE_GET_CLASS(s); + SMMUTransCfg cfg = {}; + int ret; + + smmuv3_unmap_notifier(sdev, n); + + ret = smmuv3_decode_config(mr, &cfg); + if (ret) { + error_report("%s error decoding the configuration for iommu mr=%s", + __func__, mr->parent_obj.name); + } + + if (cfg.disabled || cfg.bypassed) { + return; + } + /* is the smmu enabled */ + sbc->page_walk_64(&cfg, 0, (1ULL << (64 - cfg.tsz)) - 1, false, + smmuv3_replay_hook, n); +} +static void smmuv3_replay_range(IOMMUMemoryRegion *mr, IOMMUNotifier *n, + uint64_t iova, size_t size) +{ + SMMUDevice *sdev = container_of(mr, SMMUDevice, iommu); + SMMUV3State *s = sdev->smmu; + SMMUBaseClass *sbc = SMMU_DEVICE_GET_CLASS(s); + SMMUTransCfg cfg = {}; + IOMMUTLBEntry entry; + int ret; + + trace_smmuv3_replay_range(mr->parent_obj.name, iova, size, n); + ret = smmuv3_decode_config(mr, &cfg); + if (ret) { + error_report("%s error decoding the configuration for iommu mr=%s", + __func__, mr->parent_obj.name); + } + + if (cfg.disabled || cfg.bypassed) { + return; + } + + /* first unmap */ + entry.target_as = &address_space_memory; + entry.iova = iova & ~(size - 1); + entry.addr_mask = size - 1; + entry.perm = IOMMU_NONE; + + memory_region_notify_one(n, &entry); + + /* then figure out if a new mapping needs to be applied */ + sbc->page_walk_64(&cfg, iova, iova + entry.addr_mask , false, + smmuv3_map_hook, n); +} + +static void smmuv3_replay_single(IOMMUMemoryRegion *mr, IOMMUNotifier *n, + uint64_t iova) +{ + SMMUDevice *sdev = container_of(mr, SMMUDevice, iommu); + SMMUV3State *s = sdev->smmu; + size_t target_page_size = qemu_target_page_size(); + SMMUBaseClass *sbc = SMMU_DEVICE_GET_CLASS(s); + SMMUTransCfg cfg = {}; + IOMMUTLBEntry entry; + int ret; + + trace_smmuv3_replay_single(mr->parent_obj.name, iova, n); + ret = smmuv3_decode_config(mr, &cfg); + if (ret) { + error_report("%s error decoding the configuration for iommu mr=%s", + __func__, mr->parent_obj.name); + } + + if (cfg.disabled || cfg.bypassed) { + return; + } + + /* first unmap */ + entry.target_as = &address_space_memory; + entry.iova = iova & ~(target_page_size - 1); + entry.addr_mask = target_page_size - 1; + entry.perm = IOMMU_NONE; + + memory_region_notify_one(n, &entry); + + /* then figure out if a new mapping needs to be applied */ + sbc->page_walk_64(&cfg, iova, iova + 1, false, + smmuv3_map_hook, n); +} + +static void smmuv3_notify_flag_changed(IOMMUMemoryRegion *iommu, + IOMMUNotifierFlag old, + IOMMUNotifierFlag new) +{ + SMMUDevice *sdev = container_of(iommu, SMMUDevice, iommu); + SMMUV3State *s3 = sdev->smmu; + SMMUState *s = &(s3->smmu_state); + SMMUNotifierNode *node = NULL; + SMMUNotifierNode *next_node = NULL; + + if (old == IOMMU_NOTIFIER_NONE) { + trace_smmuv3_notify_flag_add(iommu->parent_obj.name); + node = g_malloc0(sizeof(*node)); + node->sdev = sdev; + QLIST_INSERT_HEAD(&s->notifiers_list, node, next); + return; + } + + /* update notifier node with new flags */ + QLIST_FOREACH_SAFE(node, &s->notifiers_list, next, next_node) { + if (node->sdev == sdev) { + if (new == IOMMU_NOTIFIER_NONE) { + trace_smmuv3_notify_flag_del(iommu->parent_obj.name); + QLIST_REMOVE(node, next); + g_free(node); + } + return; + } + } +} static inline void smmu_update_base_reg(SMMUV3State *s, uint64_t *base, uint64_t val) @@ -1125,6 +1382,8 @@ static void smmuv3_iommu_memory_region_class_init(ObjectClass *klass, IOMMUMemoryRegionClass *imrc = IOMMU_MEMORY_REGION_CLASS(klass); imrc->translate = smmuv3_translate; + imrc->notify_flag_changed = smmuv3_notify_flag_changed; + imrc->replay = smmuv3_replay; } static const TypeInfo smmuv3_type_info = { diff --git a/hw/arm/trace-events b/hw/arm/trace-events index f9b9cbe..8228e26 100644 --- a/hw/arm/trace-events +++ b/hw/arm/trace-events @@ -27,6 +27,7 @@ smmuv3_cmdq_opcode(const char *opcode) "<--- %s" smmuv3_cmdq_cfgi_ste(int streamid) " |_ streamid =%d" smmuv3_cmdq_cfgi_ste_range(int start, int end) " |_ start=0x%d - end=0x%d" smmuv3_cmdq_tlbi_nh_va(int asid, int vmid, uint64_t addr) " |_ asid =%d vmid =%d addr=0x%"PRIx64 +smmuv3_cmdq_tlbi_nh_va_am(int asid, int am, size_t size, uint64_t addr) " |_ asid =%d am =%d size=0x%lx addr=0x%"PRIx64 smmuv3_cmdq_consume_sev(void) "CMD_SYNC CS=SEV not supported, ignoring" smmuv3_cmdq_consume_out(uint8_t prod_wrap, uint32_t prod, uint8_t cons_wrap, uint32_t cons) "prod_wrap:%d, prod:0x%x cons_wrap:%d cons:0x%x" smmuv3_update(bool is_empty, uint32_t prod, uint32_t cons, uint8_t prod_wrap, uint8_t cons_wrap) "q empty:%d prod:%d cons:%d p.wrap:%d p.cons:%d" @@ -50,3 +51,16 @@ smmuv3_dump_ste(int i, uint32_t word0, int j, uint32_t word1) "STE[%2d]: 0x%x\t smmuv3_dump_cd(int i, uint32_t word0, int j, uint32_t word1) "CD[%2d]: 0x%x\t CD[%2d]: 0x%x" smmuv3_dump_cmd(int i, uint32_t word0, int j, uint32_t word1) "CMD[%2d]: 0x%x\t CMD[%2d]: 0x%x" smmuv3_cfg_stage(int s, uint32_t oas, uint32_t tsz, uint64_t ttbr, bool aa64, uint32_t granule_sz, int initial_level) "TransCFG stage:%d oas:%d tsz:%d ttbr:0x%"PRIx64" aa64:%d granule_sz:%d, initial_level = %d" + +smmuv3_replay(uint16_t sid, bool enabled) "sid=%d, enabled=%d" +smmuv3_replay_hook(hwaddr iova, hwaddr pa, hwaddr mask, int perm) "iova=0x%"PRIx64" pa=0x%" PRIx64" mask=0x%"PRIx64" perm=%d" +smmuv3_map_hook(hwaddr iova, hwaddr pa, hwaddr mask, int perm) "iova=0x%"PRIx64" pa=0x%" PRIx64" mask=0x%"PRIx64" perm=%d" +smmuv3_notify_flag_add(const char *iommu) "ADD SMMUNotifier node for iommu mr=%s" +smmuv3_notify_flag_del(const char *iommu) "DEL SMMUNotifier node for iommu mr=%s" +smmuv3_replay_single(const char *name, uint64_t iova, void *n) "iommu mr=%s iova=0x%"PRIx64" n=%p" +smmuv3_replay_range(const char *name, uint64_t iova, size_t size, void *n) "iommu mr=%s iova=0x%"PRIx64" size=0x%lx n=%p" +smmuv3_replay_all(const char *name) "iommu mr=%s" +smmuv3_notify_all(const char *name, uint64_t iova) "iommu mr=%s iova=0x%"PRIx64 +smmuv3_unmap_notifier(uint8_t bus, uint8_t slot, uint8_t fn, uint64_t iova, uint64_t size) "Device %02x:%02x.%x start 0x%"PRIx64" size 0x%"PRIx64 +smmuv3_context_device_invalidate(uint32_t sid) "sid=%d" + -- 2.5.5 From MAILER-DAEMON Fri Aug 11 10:26:01 2017 Received: from list by lists.gnu.org with archive (Exim 4.71) id 1dgAsz-00021P-JM for mharc-qemu-arm@gnu.org; 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dmarc=none (p=none dis=none) header.from=redhat.com Authentication-Results: ext-mx04.extmail.prod.ext.phx2.redhat.com; spf=fail smtp.mailfrom=eric.auger@redhat.com Received: from localhost.localdomain.com (ovpn-116-162.ams2.redhat.com [10.36.116.162]) by smtp.corp.redhat.com (Postfix) with ESMTP id 1AC3AA21A6; Fri, 11 Aug 2017 14:25:30 +0000 (UTC) From: Eric Auger To: eric.auger.pro@gmail.com, eric.auger@redhat.com, peter.maydell@linaro.org, qemu-arm@nongnu.org, qemu-devel@nongnu.org, alex.williamson@redhat.com, prem.mallappa@gmail.com Cc: drjones@redhat.com, christoffer.dall@linaro.org, Radha.Chintakuntla@cavium.com, Sunil.Goutham@cavium.com, mohun106@gmail.com, tcain@qti.qualcomm.com, bharat.bhushan@nxp.com, tn@semihalf.com, mst@redhat.com, will.deacon@arm.com, jean-philippe.brucker@arm.com, robin.murphy@arm.com, peterx@redhat.com, edgar.iglesias@gmail.com Date: Fri, 11 Aug 2017 16:22:34 +0200 Message-Id: <1502461354-11327-10-git-send-email-eric.auger@redhat.com> In-Reply-To: <1502461354-11327-1-git-send-email-eric.auger@redhat.com> References: <1502461354-11327-1-git-send-email-eric.auger@redhat.com> X-Scanned-By: MIMEDefang 2.79 on 10.5.11.16 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.28]); Fri, 11 Aug 2017 14:25:53 +0000 (UTC) X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.132.183.28 Subject: [Qemu-arm] [RFC v6 9/9] hw/arm/virt-acpi-build: Use the ACPI_IORT_SMMU_V3_CACHING_MODE model X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 11 Aug 2017 14:26:00 -0000 To allow VFIO use case, let's set the smmu model to ACPI_IORT_SMMU_V3_CACHING_MODE. An important notice is this model is not standardized in the ACPI IORT as this work is a proof of concept. We also set the COHACC override flag which seems to be mandated. Signed-off-by: Eric Auger --- hw/arm/virt-acpi-build.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c index ac2cd3e..9103117 100644 --- a/hw/arm/virt-acpi-build.c +++ b/hw/arm/virt-acpi-build.c @@ -437,6 +437,7 @@ build_iort(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms) smmu->type = ACPI_IORT_NODE_SMMU_V3; smmu->length = cpu_to_le16(node_size); + smmu->model = 0x3; /* ACPI_IORT_SMMU_V3_CACHING_MODE */ smmu->mapping_count = cpu_to_le32(1); smmu->mapping_offset = cpu_to_le32(sizeof(*smmu)); smmu->base_address = cpu_to_le64(vms->memmap[VIRT_SMMU].base); @@ -444,6 +445,7 @@ build_iort(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms) smmu->pri_gsiv = cpu_to_le32(irq + 1); smmu->gerr_gsiv = cpu_to_le32(irq + 2); smmu->sync_gsiv = cpu_to_le32(irq + 3); + smmu->flags = 0x1; /* COHACC Override */ /* Identity RID mapping covering the whole input RID range */ idmap = &smmu->id_mapping_array[0]; -- 2.5.5 From MAILER-DAEMON Fri Aug 11 10:32:10 2017 Received: from list by lists.gnu.org with archive (Exim 4.71) id 1dgAyv-00087Z-OY for mharc-qemu-arm@gnu.org; Fri, 11 Aug 2017 10:32:09 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:36623) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dgAys-00084s-TI for qemu-arm@nongnu.org; Fri, 11 Aug 2017 10:32:08 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dgAyr-0006JH-Bz for qemu-arm@nongnu.org; Fri, 11 Aug 2017 10:32:06 -0400 Received: from mail-db5eur01on0076.outbound.protection.outlook.com ([104.47.2.76]:23040 helo=EUR01-DB5-obe.outbound.protection.outlook.com) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1dgAyk-0006HQ-Cy; Fri, 11 Aug 2017 10:31:58 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nxp.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version; bh=QfJr2oegcqxKEg+E5CU2JHxQza1lWkf6JMa8Hx7RjJs=; b=Ho9I1L1+NBVbljhPKipDOVosOs50RZIoiOuI5ElAsmKZmlaTIfepOggia8J9aYNVxvWsuCFNk4kvu2krdDSmv89t0AcTzuCcxPbDt39HgzSXo4pvdMx5jolpUnUZU4sktF/jwQPlfdAEE1wDBleNqMulWACl2/w0XJFpGkOTch0= Received: from AM3PR04MB0616.eurprd04.prod.outlook.com (10.255.133.15) by AM3PR04MB0806.eurprd04.prod.outlook.com (10.242.253.144) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384_P256) id 15.1.1341.17; Fri, 11 Aug 2017 14:31:54 +0000 Received: from AM3PR04MB0616.eurprd04.prod.outlook.com ([fe80::840e:32fc:ecf4:2ffb]) by AM3PR04MB0616.eurprd04.prod.outlook.com ([fe80::840e:32fc:ecf4:2ffb%14]) with mapi id 15.01.1341.019; Fri, 11 Aug 2017 14:31:52 +0000 From: Diana Madalina Craciun To: "Michael S. Tsirkin" CC: "qemu-devel@nongnu.org" , "qemu-arm@nongnu.org" , "christoffer.dall@linaro.org" , "marcel@redhat.com" , "eric.auger@redhat.com" , Bharat Bhushan , Mike Caraman , "Laurentiu Tudor" Thread-Topic: [PATCH v2 0/2] Add global device ID in virt machine Thread-Index: AQHS07WHLIdRw36YjE2WVULSPv0RNA== Date: Fri, 11 Aug 2017 14:31:52 +0000 Message-ID: References: <1495537965-4187-1-git-send-email-diana.craciun@nxp.com> <20170525011034-mutt-send-email-mst@kernel.org> <20170706023845-mutt-send-email-mst@kernel.org> <20170731170217-mutt-send-email-mst@kernel.org> <20170801045857-mutt-send-email-mst@kernel.org> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: authentication-results: spf=none (sender IP is ) smtp.mailfrom=diana.craciun@nxp.com; x-originating-ip: [192.88.146.1] x-ms-publictraffictype: Email x-microsoft-exchange-diagnostics: 1; AM3PR04MB0806; 6:MjwzuTgQnp9o8xBnkhXjXkS6eG67puzO5SUK5rZR0AVf9yDjYo+HCEBzRljKpxUE5Xt0lNmAdsvtg/OiaXzn32XSxLTpeFnh0DDapZSvG08U7l9HG1qGKaW4HP83DHYWbgquiGfr4cPIXMOZv5N0ukSyhENv/kdnAbftlB19FP6sIrJ6aUbdccUW9f0E2x7qkgYpFaPU9HzWjIpR2XPhzqsOSsKwIWUWwUTP9yHuObzMokVGcO4ne0ZHAhquU4j7QVTGDvsnE3FSE8OYPzrjB0HSGPgSskpP78umVnJnlDsfHtSoF6hijD9wgIqYNgBnEfmpfsYm9RgX3WPEXO9wQg==; 5:64HgJ2O2Ny6oTVTfhQ/OlnTopqMBK22HRIV7SP6fanNymLGmhtUtneDp27zYx46I0CzVqZa1mvfL+UN6n8imvHy4f1V0b52XTwVAPWf5rESgeTa/nU9KRyyjpAA8OYphZIZHb6FeMg+3ruYclRBIzw==; 24:/LMWLphE97/oRmOqXj0/EslDQQZMcf0wNLuAENRnyYYjopM0TkfRKmVjXc77a3rrnLDpdMob7PZ5OdaSphQzOrY2BUYQCbm5HBfB+mePI2s=; 7:wEa3rCTjXShg7muDwxlQDdV1+AJyGSCiwgAOF965gYd6miTzLYNeD9fZj2ZWAobE5qi8zO7HWxB7DBRLaxXaBCqyFv3f577r1le7JDFacjlvcSmmHvOSr4gxn4JfcS84pk4CgkxxEOd8U/6T9X4EBhp/G88+vI3C+WwRMXYG+v1m3NJhfr3xHoHUfYbN1vt5OkhxqyfskNP+Qb47DXHtdKx/TBUUjRVRSMTiYq4OIjI= x-ms-exchange-antispam-srfa-diagnostics: SSOS;SSOR; x-forefront-antispam-report: SFV:SKI; SCL:-1; SFV:NSPM; SFS:(10009020)(6009001)(39860400002)(199003)(189002)(377454003)(24454002)(2900100001)(54906002)(14454004)(99286003)(105586002)(55016002)(101416001)(106356001)(6436002)(50986999)(76176999)(54356999)(9686003)(2906002)(6306002)(5250100002)(93886004)(6506006)(7736002)(229853002)(189998001)(305945005)(66066001)(81156014)(8676002)(81166006)(8936002)(7696004)(3660700001)(33656002)(478600001)(102836003)(3846002)(5660300001)(6116002)(4326008)(6916009)(97736004)(53546010)(6246003)(110136004)(25786009)(3280700002)(45080400002)(53936002)(68736007)(74316002)(86362001)(575784001); DIR:OUT; SFP:1101; SCL:1; SRVR:AM3PR04MB0806; H:AM3PR04MB0616.eurprd04.prod.outlook.com; FPR:; SPF:None; PTR:InfoNoRecords; A:1; MX:1; LANG:en; x-ms-office365-filtering-correlation-id: 3205f3b1-f5bb-469d-9392-08d4e0c5b581 x-ms-office365-filtering-ht: Tenant x-microsoft-antispam: UriScan:; BCL:0; PCL:0; RULEID:(300000500095)(300135000095)(300000501095)(300135300095)(300000502095)(300135100095)(22001)(2017030254152)(300000503095)(300135400095)(48565401081)(2017052603031)(201703131423075)(201703031133081)(201702281549075)(300000504095)(300135200095)(300000505095)(300135600095)(300000506095)(300135500095); SRVR:AM3PR04MB0806; x-ms-traffictypediagnostic: AM3PR04MB0806: x-exchange-antispam-report-test: UriScan:(189930954265078)(45079756050767); x-microsoft-antispam-prvs: x-exchange-antispam-report-cfa-test: BCL:0; PCL:0; RULEID:(100000700101)(100105000095)(100000701101)(100105300095)(100000702101)(100105100095)(6040450)(601004)(2401047)(5005006)(8121501046)(3002001)(10201501046)(100000703101)(100105400095)(93006095)(93001095)(6055026)(6041248)(201703131423075)(201702281528075)(201703061421075)(201703061406153)(20161123555025)(20161123562025)(20161123564025)(20161123558100)(20161123560025)(6072148)(201708071742011)(100000704101)(100105200095)(100000705101)(100105500095); SRVR:AM3PR04MB0806; BCL:0; PCL:0; RULEID:(100000800101)(100110000095)(100000801101)(100110300095)(100000802101)(100110100095)(100000803101)(100110400095)(100000804101)(100110200095)(100000805101)(100110500095); SRVR:AM3PR04MB0806; x-forefront-prvs: 03965EFC76 received-spf: None (protection.outlook.com: nxp.com does not designate permitted sender hosts) spamdiagnosticoutput: 1:99 spamdiagnosticmetadata: NSPM Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-originalarrivaltime: 11 Aug 2017 14:31:52.3188 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM3PR04MB0806 X-detected-operating-system: by eggs.gnu.org: Windows 7 or 8 [fuzzy] X-Received-From: 104.47.2.76 Subject: Re: [Qemu-arm] [PATCH v2 0/2] Add global device ID in virt machine X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 11 Aug 2017 14:32:08 -0000 On 08/01/2017 05:05 AM, Michael S. Tsirkin wrote:=0A= > On Mon, Jul 31, 2017 at 03:13:09PM +0000, Diana Madalina Craciun wrote:= =0A= >> On 07/31/2017 05:06 PM, Michael S. Tsirkin wrote:=0A= >>> On Mon, Jul 31, 2017 at 01:22:45PM +0000, Diana Madalina Craciun wrote:= =0A= >>>>>> If we are to use a value of 0 for the constant in case of PCI device= s,=0A= >>>>>> what happens if we have multiple PCI controllers?=0A= >>>>> I guess we'd use the PCI Segment number for that?=0A= >>>>>=0A= >>>>>=0A= >>>> Yes, we can use the PCI segment for this scenario. But this would mean= =0A= >>>> different solutions for the same problem. The main problem is that we= =0A= >>>> can have multiple entities in the system that are using MSIs (for now= =0A= >>>> PCI and NXP non-PCI bus infrastructure=0A= >>>> (https://emea01.safelinks.protection.outlook.com/?url=3Dhttps%3A%2F%2F= lwn.net%2FArticles%2F635905%2F&data=3D01%7C01%7Cdiana.craciun%40nxp.com%7C6= b0c6c879af64718a21908d4d81d534e%7C686ea1d3bc2b4c6fa92cd99c5c301635%7C0&sdat= a=3DbpYMMqajWzgzdbdQgy%2FUYR7y%2BswyvwE%2BqFzs7wdIkkA%3D&reserved=3D0). I g= uess that we may have other=0A= >>>> platform devices that are using MSIs in the future.=0A= >>>>=0A= >>>> Thanks,=0A= >>>> Diana=0A= >>>>=0A= >>>>=0A= >>> Don't have the time to explore NXP in depth, sorry - there's=0A= >>> a lot of complexity there.=0A= >>> Could you maybe stick some bits to specify bus type in there?=0A= >>> It just looks very wrong to push low level things like this=0A= >>> that users have no interest in up the stack.=0A= >>>=0A= >> Let's generalize the problem a little bit, the NXP details just does not= =0A= >> matter much. The problem we have is the following:=0A= >>=0A= >> The GIC-ITS, the ARM MSI controller is using deviceIDs in order to remap= =0A= >> the interrupts. Each device which is expected to send MSIs has a=0A= >> deviceID associated with it. These deviceIDs are configured into devices= =0A= >> by software/firmware. There is support in the device tree to specify the= =0A= >> correlation between requesterID and deviceID:=0A= >>=0A= >> "msi-map: Maps a Requester ID to an MSI controller and associated=0A= >> msi-specifier data. The property is an arbitrary number of tuples of= =0A= >> (rid-base,msi-controller,msi-base,length)"=0A= >> (https://emea01.safelinks.protection.outlook.com/?url=3Dhttps%3A%2F%2Fgi= t.kernel.org%2Fpub%2Fscm%2Flinux%2Fkernel%2Fgit%2Ftorvalds%2Flinux.git%2Ftr= ee%2FDocumentation%2Fdevicetree%2Fbindings%2Fpci%2Fpci-msi.txt&data=3D01%7C= 01%7Cdiana.craciun%40nxp.com%7C259982f3a83b4160083708d4d881d48a%7C686ea1d3b= c2b4c6fa92cd99c5c301635%7C0&sdata=3DQSRwrYcsTk9%2FgekD0YBYKvpWv05%2BXKiH2ab= Pp%2FtHpes%3D&reserved=3D0)=0A= >>=0A= >> Our problem is that we have to allocate these deviceIDs in QEMU as well= =0A= >> and we have to ensure that they are unique. Currently, for PCI, the=0A= >> assumption requesterID=3DdeviceID is made which will no longer be true i= n=0A= >> case other devices are added. So we need a way (preferable a general=0A= >> one) to allocate these IDs to different devices in the system in a=0A= >> consistent way which will ensure that two devices do not share the same = ID.=0A= > My question would be, do other types of devices that are there=0A= > right now have some kind of ID like the requester ID?=0A= > If so I would say just use that, and set high bits in the device ID=0A= > to specify the type (e.g. 00 for pci, etc).=0A= =0A= Would this mean extending the PCI requesterID usage as well? Or assume=0A= that it's 00 for PCI and no changes are needed? I understand that with=0A= this approach the allocation is static: 00 for PCI, 01 for device type=0A= X, etc., so the situation when we have multiple controllers (PCI or=0A= whatever other devices) has to be solved differently. Wouldn't be this=0A= more complex?=0A= =0A= >=0A= >=0A= > IMHO if possible that is preferable to pushing this up to users.=0A= >=0A= >=0A= >> The reason I put this ID into the controller itself is because on real= =0A= >> hardware is actually programmed into the controller. It is needed (for= =0A= >> example) when the MSIs are sent.=0A= >>=0A= >> Thanks,=0A= >>=0A= >> Diana=0A= >>=0A= > IIUC what happens on real hardware is controller maps each requester ID= =0A= > (or presumably other source ID in the request) to the device ID,=0A= > and the mapping is internal to controller.=0A= > If you wanted a lot of flexibility then looks like you could pass this=0A= > mapping to controllers, but is it really necessary?=0A= > Why don't we build a mapping that's convenient for us?=0A= >=0A= >=0A= Thanks,=0A= =0A= Diana=0A= =0A= From MAILER-DAEMON Fri Aug 11 10:32:34 2017 Received: from list by lists.gnu.org with archive (Exim 4.71) id 1dgAzJ-0008Nc-Rn for mharc-qemu-arm@gnu.org; Fri, 11 Aug 2017 10:32:33 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:36724) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dgAzH-0008LY-Jm for qemu-arm@nongnu.org; Fri, 11 Aug 2017 10:32:33 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dgAzG-0006OI-GB for qemu-arm@nongnu.org; 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Fri, 11 Aug 2017 14:32:21 +0000 From: Diana Madalina Craciun To: Auger Eric , "qemu-devel@nongnu.org" CC: "mst@redhat.com" , Mike Caraman , "qemu-arm@nongnu.org" , "marcel@redhat.com" , Bharat Bhushan , "christoffer.dall@linaro.org" , Laurentiu Tudor Thread-Topic: [Qemu-devel] [PATCH v2 1/2] Increased the size of requester_id field from MemTxAttrs Thread-Index: AQHS07WNuEqtEroxdEC9jZ/8jBjQOQ== Date: Fri, 11 Aug 2017 14:32:21 +0000 Message-ID: References: <1495537965-4187-1-git-send-email-diana.craciun@nxp.com> <1495537965-4187-2-git-send-email-diana.craciun@nxp.com> <17ae81be-a86e-d0ab-de93-046846e0b7d2@redhat.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: authentication-results: spf=none (sender IP is ) smtp.mailfrom=diana.craciun@nxp.com; x-originating-ip: [192.88.146.1] x-ms-publictraffictype: Email x-microsoft-exchange-diagnostics: 1; AM3PR04MB0806; 6:yYoV4+DYCyAz6h6OJXKjUTZhR2BSu+SpC6Q5XYqa9p8xjH0NYX3+079F6JI2KNeT4lqyFUUEvjEJo+KfJ/O1D5PmCtvt8ILYQhYsUcbHEV9r9Gz0vcklO0QOnzw1ZGtvp/8Tp1xKOPlIrKUFasxB7PaC6YCF7qqGYqZqG4RBOjT8FPnm31hlE1QKotKvxRL2YZ42+TuKQej0s13mcXrNtGIOg5uRElQ4/tWCwdq5Y49QADH/lDDcofaVwRmY/CJE+MsKTsBTSTz4kDxKgxePwKJzhSOvQ/UdaXmqDH9XG9xVPCv63IDRa5dq5GySXRXfugc+ktaszxugnGTRyYwiAA==; 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SRVR:AM3PR04MB0806; BCL:0; PCL:0; RULEID:(100000800101)(100110000095)(100000801101)(100110300095)(100000802101)(100110100095)(100000803101)(100110400095)(100000804101)(100110200095)(100000805101)(100110500095); SRVR:AM3PR04MB0806; x-forefront-prvs: 03965EFC76 received-spf: None (protection.outlook.com: nxp.com does not designate permitted sender hosts) spamdiagnosticoutput: 1:99 spamdiagnosticmetadata: NSPM Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-originalarrivaltime: 11 Aug 2017 14:32:21.4245 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM3PR04MB0806 X-detected-operating-system: by eggs.gnu.org: Windows 7 or 8 [fuzzy] X-Received-From: 104.47.1.43 Subject: Re: [Qemu-arm] [Qemu-devel] [PATCH v2 1/2] Increased the size of requester_id field from MemTxAttrs X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 11 Aug 2017 14:32:33 -0000 Hi Eric,=0A= =0A= On 07/26/2017 03:23 PM, Auger Eric wrote:=0A= > Hi Diana,=0A= > On 23/05/2017 13:12, Diana Craciun wrote:=0A= >> The PCI requester ID field is 16 bits. The requester_id field=0A= >> from MemTxAttrs is used for MSIs to specify the device ID for=0A= >> the platforms where this device ID is needed (e.g virt machine + GICv3= =0A= >> ITS). However, if more entities that uses MSIs in the system are used,= =0A= >> 16 bit is no longer enough to represent the device ID. Increased the siz= e=0A= >> of this field to 24 bits in order to accomodate 256 entities.=0A= >> Also the name requester_id does no longer reflect the content, so=0A= >> the name was changed to stream_id.=0A= > I think both deviceid and streamid can be up to 32 bits in theory.=0A= =0A= Yes, both of them can be up to 32 bit. I can extend the field to 32 bit.=0A= =0A= >=0A= > With respect to the renaming, stream_id really is ARM specific and=0A= > corresponds to the ID space before the SMMU while you mostly address=0A= > device id problematics here (ie. space id input to the interrupt=0A= > controller). Maybe a more generic terminology such as originator id=0A= > could be used or source id (I think this is Intel terminology though).=0A= =0A= I agree, originator id sounds good and so far it doesn't seem to overlap=0A= to other specific terminology.=0A= =0A= >=0A= > Maybe the changes in semantics of the field should be=0A= > associated/combined with its new computation found in next patch? see=0A= > comments in subsequent patch.=0A= =0A= I agree.=0A= =0A= Thanks,=0A= =0A= Diana=0A= =0A= =0A= From MAILER-DAEMON Fri Aug 11 10:35:01 2017 Received: from list by lists.gnu.org with archive (Exim 4.71) id 1dgB1h-0001oc-7R for mharc-qemu-arm@gnu.org; Fri, 11 Aug 2017 10:35:01 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:37276) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dgB1b-0001k8-3g for qemu-arm@nongnu.org; Fri, 11 Aug 2017 10:34:59 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dgB1Y-0006sv-93 for qemu-arm@nongnu.org; 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charset="us-ascii" Content-Transfer-Encoding: quoted-printable Hi Eric, Thanks for looking into this. On 07/26/2017 03:22 PM, Auger Eric wrote: Hi Diana, On 23/05/2017 13:12, Diana Craciun wrote: Device IDs are required by the ARM GICv3 ITS for IRQ remapping. Currently, for PCI devices, the requester ID was used as device ID in the virt machine. If the system has multiple masters that if the system has multiple root complex? Well ... root complex is PCI specific terminology. Our device is not a PCI = device. However masters is not the best choice either, it should be rephras= ed. use MSIs a unique ID accross the platform is needed. across A static scheme is used and each master is allocated a range of IDs with the formula: DeviceID =3D zero_extend( RequesterID[15:0] ) + 0x10000*Constant (as recommended by SBSA). This ID will be configured in the machine creation and if not configured the PCI requester ID will be used insteead. instead Signed-off-by: Diana Craciun --- hw/arm/virt.c | 26 ++++++++++++++++++++++++++ hw/pci-host/gpex.c | 6 ++++++ hw/pci/msi.c | 2 +- hw/pci/pci.c | 25 +++++++++++++++++++++++++ include/hw/arm/virt.h | 1 + include/hw/pci-host/gpex.h | 2 ++ include/hw/pci/pci.h | 8 ++++++++ kvm-all.c | 4 ++-- 8 files changed, 71 insertions(+), 3 deletions(-) diff --git a/hw/arm/virt.c b/hw/arm/virt.c index 5f62a03..a969694 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -110,6 +110,8 @@ static ARMPlatformBusSystemParams platform_bus_params; #define RAMLIMIT_GB 255 #define RAMLIMIT_BYTES (RAMLIMIT_GB * 1024ULL * 1024 * 1024) +#define STREAM_ID_RANGE_SIZE 0x10000 + /* Addresses and sizes of our components. * 0..128MB is space for a flash device so we can run bootrom code such as= UEFI. * 128MB..256MB is used for miscellaneous device I/O. @@ -162,6 +164,22 @@ static const int a15irqmap[] =3D { [VIRT_PLATFORM_BUS] =3D 112, /* ...to 112 + PLATFORM_BUS_NUM_IRQS -1 *= / }; +/* Device IDs are required by the ARM GICV3 ITS for IRQ remapping. Current= ly + * for PCI devices the requester ID was used as device ID. But if the syst= em has + * multiple masters that use MSIs, the requester ID may cause deviceID cla= shes. + * So a unique number is needed accross the system. + * We are using the following formula: + * DeviceID =3D zero_extend( RequesterID[15:0] ) + 0x10000*Constant + * (as recommanded by SBSA). Currently we do not have an SMMU emulation, b= ut the + * same formula can be used for the generation of the streamID as well. + * For each master the device ID will be derrived from the requester ID us= ing + * the abovemntione formula. + */ I think most of this comment should only be in the commit message. typos in derived and above mentioned. OK. stream id is the terminology for the id space at the input of the smmu. device id is the terminology for the id space at the input of the msi controller I think. RID -> deviceID (no IOMMU) RID -> streamID -> deviceID (IOMMU) I would personally get rid of all streamid uses as the smmu is not yet supported and stick to the Documentation/devicetree/bindings/pci/pci-msi.txt terminology? OK. + +static const uint32_t streamidmap[] =3D { + [VIRT_PCIE] =3D 0, /* currently only one PCI controller */ +}; + static const char *valid_cpus[] =3D { "cortex-a15", "cortex-a53", @@ -980,6 +998,7 @@ static void create_pcie(const VirtMachineState *vms, qe= mu_irq *pic) hwaddr base_ecam =3D vms->memmap[VIRT_PCIE_ECAM].base; hwaddr size_ecam =3D vms->memmap[VIRT_PCIE_ECAM].size; hwaddr base =3D base_mmio; + uint32_t stream_id =3D vms->streamidmap[VIRT_PCIE] * STREAM_ID_RANGE_S= IZE; msi-base? OK, I will get rid of the stream_id naming. STREAM_ID_RANGE_SIZE ~ MSI_MAP_LENGTH? OK. int nr_pcie_buses =3D size_ecam / PCIE_MMCFG_SIZE_MIN; int irq =3D vms->irqmap[VIRT_PCIE]; MemoryRegion *mmio_alias; @@ -992,6 +1011,7 @@ static void create_pcie(const VirtMachineState *vms, q= emu_irq *pic) PCIHostState *pci; dev =3D qdev_create(NULL, TYPE_GPEX_HOST); + qdev_prop_set_uint32(dev, "stream-id-base", stream_id); qdev_init_nofail(dev); /* Map only the first size_ecam bytes of ECAM space */ @@ -1056,6 +1076,11 @@ static void create_pcie(const VirtMachineState *vms,= qemu_irq *pic) if (vms->msi_phandle) { qemu_fdt_setprop_cells(vms->fdt, nodename, "msi-parent", vms->msi_phandle); + qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "msi-map", + 1, 0, + 1, vms->msi_phandle, + 1, stream_id, + 1, STREAM_ID_RANGE_SIZE); } qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg", @@ -1609,6 +1634,7 @@ static void virt_2_9_instance_init(Object *obj) vms->memmap =3D a15memmap; vms->irqmap =3D a15irqmap; + vms->streamidmap =3D streamidmap; } static void virt_machine_2_9_options(MachineClass *mc) diff --git a/hw/pci-host/gpex.c b/hw/pci-host/gpex.c index 66055ee..de72408 100644 --- a/hw/pci-host/gpex.c +++ b/hw/pci-host/gpex.c @@ -43,6 +43,11 @@ static void gpex_set_irq(void *opaque, int irq_num, int = level) qemu_set_irq(s->irq[irq_num], level); } +static Property gpex_props[] =3D { + DEFINE_PROP_UINT32("stream-id-base", GPEXHost, stream_id_base, 0), msi_base_base + DEFINE_PROP_END_OF_LIST(), +}; + static void gpex_host_realize(DeviceState *dev, Error **errp) { PCIHostState *pci =3D PCI_HOST_BRIDGE(dev); @@ -83,6 +88,7 @@ static void gpex_host_class_init(ObjectClass *klass, void= *data) hc->root_bus_path =3D gpex_host_root_bus_path; dc->realize =3D gpex_host_realize; + dc->props =3D gpex_props; set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories); dc->fw_name =3D "pci"; } diff --git a/hw/pci/msi.c b/hw/pci/msi.c index 7925851..b60a410 100644 --- a/hw/pci/msi.c +++ b/hw/pci/msi.c @@ -336,7 +336,7 @@ void msi_send_message(PCIDevice *dev, MSIMessage msg) { MemTxAttrs attrs =3D {}; - attrs.stream_id =3D pci_requester_id(dev); + attrs.stream_id =3D pci_stream_id(dev); address_space_stl_le(&dev->bus_master_as, msg.address, msg.data, attrs, NULL); } diff --git a/hw/pci/pci.c b/hw/pci/pci.c index 259483b..92e9a2b 100644 --- a/hw/pci/pci.c +++ b/hw/pci/pci.c @@ -951,6 +951,30 @@ uint16_t pci_requester_id(PCIDevice *dev) return pci_req_id_cache_extract(&dev->requester_id_cache); } +static uint32_t pci_get_stream_id_base(PCIDevice *dev) +{ + PCIBus *rootbus =3D pci_device_root_bus(dev); + PCIHostState *host_bridge =3D PCI_HOST_BRIDGE(rootbus->qbus.parent); + Error *err =3D NULL; + int64_t stream_id; + + stream_id =3D object_property_get_int(OBJECT(host_bridge), "stream-id-= base", + &err); + if (stream_id < 0) { + stream_id =3D 0; + } + + return stream_id; +} + +uint32_t pci_stream_id(PCIDevice *dev) +{ + /* Stream ID =3D RequesterID[15:0] + stream_id_base. stream_id_base ma= y + * be 0 for devices that are not using any translation between request= er_id + * and stream_id */ + return (uint16_t)pci_requester_id(dev) + dev->stream_id_base; +} I think you should split the changes in virt from pci/gpex generic changes. I agree. + /* -1 for devfn means auto assign */ static PCIDevice *do_pci_register_device(PCIDevice *pci_dev, PCIBus *bus, const char *name, int devfn, @@ -1000,6 +1024,7 @@ static PCIDevice *do_pci_register_device(PCIDevice *p= ci_dev, PCIBus *bus, pci_dev->devfn =3D devfn; pci_dev->requester_id_cache =3D pci_req_id_cache_get(pci_dev); + pci_dev->stream_id_base =3D pci_get_stream_id_base(pci_dev); looks strange to me to store the rid base in the end point as this is rather a property of the PCI complex. I acknowledge this is much more simple than reworking pci_requester_id() though. I actually did implemented it in a different way at the beginning: +uint32_t pci_stream_id(PCIDevice *dev) +{ + PCIBus *rootbus =3D pci_device_root_bus(dev); + PCIHostState *host_bridge =3D PCI_HOST_BRIDGE(rootbus->qbus.parent); + Error *err =3D NULL; + int64_t stream_id; + + stream_id =3D object_property_get_int(OBJECT(host_bridge), "stream-id-= base", + &err); + if (stream_id < 0) { + stream_id =3D 0; + } + /* DeviceID =3D RequesterID[15:0] + stream_id_base. If the stream-id-b= ase + * property is not found (e.g. for platforms that are not needing a + * global ID) the requester ID will be used instead. */ + stream_id +=3D (uint16_t)pci_requester_id(dev); + + return stream_id; +} The reason I have changed was to avoid traversing the entire hierarchy each= time the ID is needed (for example each time when a MSI is sent). memory_region_init(&pci_dev->bus_master_container_region, OBJECT(pci_d= ev), "bus master container", UINT64_MAX); diff --git a/include/hw/arm/virt.h b/include/hw/arm/virt.h index 33b0ff3..94c007a 100644 --- a/include/hw/arm/virt.h +++ b/include/hw/arm/virt.h @@ -99,6 +99,7 @@ typedef struct { struct arm_boot_info bootinfo; const MemMapEntry *memmap; const int *irqmap; + const uint32_t *streamidmap; int smp_cpus; void *fdt; int fdt_size; diff --git a/include/hw/pci-host/gpex.h b/include/hw/pci-host/gpex.h index 68c9348..47df01a 100644 --- a/include/hw/pci-host/gpex.h +++ b/include/hw/pci-host/gpex.h @@ -48,6 +48,8 @@ typedef struct GPEXHost { GPEXRootState gpex_root; + uint32_t stream_id_base; + MemoryRegion io_ioport; MemoryRegion io_mmio; qemu_irq irq[GPEX_NUM_IRQS]; diff --git a/include/hw/pci/pci.h b/include/hw/pci/pci.h index a37a2d5..e6e9334 100644 --- a/include/hw/pci/pci.h +++ b/include/hw/pci/pci.h @@ -283,6 +283,12 @@ struct PCIDevice { * MSI). For conventional PCI root complex, this field is * meaningless. */ PCIReqIDCache requester_id_cache; + /* Some platforms need a unique ID for IOMMU source identification + * or MSI source identification. QEMU implements a simple scheme: + * stream_id =3D stream_id_base + requester_id. The stream_id_base wi= ll + * ensure that all the devices in the system have different stream ID + * domains */ + uint32_t stream_id_base; get rid of IOMMU terminology? OK. Note that when adding other sub-systems you will need to address the ACPI side as the IORT table built by hw/arm/virt-acpi-build.c currently defines an RID mapping for the single root complex. I am not quite familiar with ACPI but for sure I will take a look into this= . Thanks for pointing it out. Thanks, Diana --_000_AM3PR04MB0616B6DDCF5A59D8C29E9516FF890AM3PR04MB0616eurp_ Content-Type: text/html; charset="us-ascii" Content-Transfer-Encoding: quoted-printable
Hi Eric,

Thanks for looking into this.

On 07/26/2017 03:22 PM, Auger Eric wrote:
Hi Diana,=0A=
On 23/05/2017 13:12, Diana Craciun wrote:=0A=
Device IDs are required by the ARM GICv3 ITS for IRQ remappi=
ng.=0A=
Currently, for PCI devices, the requester ID was used as device=0A=
ID in the virt machine. If the system has multiple masters that=0A=
if the system has multiple root complex?

Well ... root complex is PCI specific terminology. Our device is not a PCI = device. However masters is not the best choice either, it should be rephras= ed.

=0A=
use MSIs a unique ID accross the platform is needed.=0A=
across=0A=
A static scheme is used and each master is allocated a range=
 of IDs=0A=
with the formula:=0A=
DeviceID =3D zero_extend( RequesterID[15:0] ) + 0x10000*Constant (as=0A=
recommended by SBSA).=0A=
=0A=
This ID will be configured in the machine creation and if not configured=0A=
the PCI requester ID will be used insteead.=0A=
instead=0A=
=0A=
Signed-off-by: Diana Craciun <diana.craciun@nxp.com>=0A=
---=0A=
 hw/arm/virt.c              | 26 ++++++++&#=
43;++++++++++++++&#=
43;++=0A=
 hw/pci-host/gpex.c         |  6 ++++++=0A=
 hw/pci/msi.c               |  2 +-=0A=
 hw/pci/pci.c               | 25 ++++++++&#=
43;++++++++++++++&#=
43;+=0A=
 include/hw/arm/virt.h      |  1 +=0A=
 include/hw/pci-host/gpex.h |  2 ++=0A=
 include/hw/pci/pci.h       |  8 ++++++++=
=0A=
 kvm-all.c                  |  4 ++--=0A=
 8 files changed, 71 insertions(+), 3 deletions(-)=0A=
=0A=
diff --git a/hw/arm/virt.c b/hw/arm/virt.c=0A=
index 5f62a03..a969694 100644=0A=
--- a/hw/arm/virt.c=0A=
+++ b/hw/arm/virt.c=0A=
@@ -110,6 +110,8 @@ static ARMPlatformBusSystemParams platform_bus_para=
ms;=0A=
 #define RAMLIMIT_GB 255=0A=
 #define RAMLIMIT_BYTES (RAMLIMIT_GB * 1024ULL * 1024 * 1024)=0A=
 =0A=
+#define STREAM_ID_RANGE_SIZE 0x10000=0A=
+=0A=
 /* Addresses and sizes of our components.=0A=
  * 0..128MB is space for a flash device so we can run bootrom code such as=
 UEFI.=0A=
  * 128MB..256MB is used for miscellaneous device I/O.=0A=
@@ -162,6 +164,22 @@ static const int a15irqmap[] =3D {=0A=
     [VIRT_PLATFORM_BUS] =3D 112, /* ...to 112 + PLATFORM_BUS_NUM_IRQS =
-1 */=0A=
 };=0A=
 =0A=
+/* Device IDs are required by the ARM GICV3 ITS for IRQ remapping. Cur=
rently=0A=
+ * for PCI devices the requester ID was used as device ID. But if the =
system has=0A=
+ * multiple masters that use MSIs, the requester ID may cause deviceID=
 clashes.=0A=
+ * So a unique number is  needed accross the system.=0A=
+ * We are using the following formula:=0A=
+ * DeviceID =3D zero_extend( RequesterID[15:0] ) + 0x10000*Constan=
t=0A=
+ * (as recommanded by SBSA). Currently we do not have an SMMU emulatio=
n, but the=0A=
+ * same formula can be used for the generation of the streamID as well=
.=0A=
+ * For each master the device ID will be derrived from the requester I=
D using=0A=
+ * the abovemntione formula.=0A=
+ */=0A=
I think most of this comment should only be in the commit me=
ssage. typos=0A=
in derived and above mentioned.

OK.

=0A=
=0A=
stream id is the terminology for the id space at the input of the smmu.=0A=
device id is the terminology for the id space at the input of the msi=0A=
controller I think.=0A=
=0A=
RID -> deviceID (no IOMMU)=0A=
RID -> streamID -> deviceID (IOMMU)=0A=
=0A=
I would personally get rid of all streamid uses as the smmu is not yet=0A=
supported and stick to the=0A=
Documentation/devicetree/bindings/pci/pci-msi.txt terminology?=0A=

OK.

=0A=
+=0A=
+static const uint32_t streamidmap[] =3D {=0A=
+    [VIRT_PCIE] =3D 0,         /* currently only one PCI controller */=
=0A=
+};=0A=
+=0A=
 static const char *valid_cpus[] =3D {=0A=
     "cortex-a15",=0A=
     "cortex-a53",=0A=
@@ -980,6 +998,7 @@ static void create_pcie(const VirtMachineState *vms=
, qemu_irq *pic)=0A=
     hwaddr base_ecam =3D vms->memmap[VIRT_PCIE_ECAM].base;=0A=
     hwaddr size_ecam =3D vms->memmap[VIRT_PCIE_ECAM].size;=0A=
     hwaddr base =3D base_mmio;=0A=
+    uint32_t stream_id =3D vms->streamidmap[VIRT_PCIE] * STREAM_ID_=
RANGE_SIZE;=0A=
msi-base?

OK, I will get rid of the stream_id naming.

=0A=
STREAM_ID_RANGE_SIZE ~ MSI_MAP_LENGTH?

OK.

=0A=
     int nr_pcie_buses =3D size_ecam / PCIE_MMCFG_SIZE_MIN;=
=0A=
     int irq =3D vms->irqmap[VIRT_PCIE];=0A=
     MemoryRegion *mmio_alias;=0A=
@@ -992,6 +1011,7 @@ static void create_pcie(const VirtMachineState *vm=
s, qemu_irq *pic)=0A=
     PCIHostState *pci;=0A=
 =0A=
     dev =3D qdev_create(NULL, TYPE_GPEX_HOST);=0A=
+    qdev_prop_set_uint32(dev, "stream-id-base", stream_id);=
=0A=
     qdev_init_nofail(dev);=0A=
 =0A=
     /* Map only the first size_ecam bytes of ECAM space */=0A=
@@ -1056,6 +1076,11 @@ static void create_pcie(const VirtMachineState *=
vms, qemu_irq *pic)=0A=
     if (vms->msi_phandle) {=0A=
         qemu_fdt_setprop_cells(vms->fdt, nodename, "msi-parent&quo=
t;,=0A=
                                vms->msi_phandle);=0A=
+        qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "msi-=
map",=0A=
+                                     1, 0,=0A=
+                                     1, vms->msi_phandle,=0A=
+                                     1, stream_id,=0A=
+                                     1, STREAM_ID_RANGE_SIZE);=0A=
     }=0A=
 =0A=
     qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg",=
=0A=
@@ -1609,6 +1634,7 @@ static void virt_2_9_instance_init(Object *obj)=
=0A=
 =0A=
     vms->memmap =3D a15memmap;=0A=
     vms->irqmap =3D a15irqmap;=0A=
+    vms->streamidmap =3D streamidmap;=0A=
 }=0A=
 =0A=
 static void virt_machine_2_9_options(MachineClass *mc)=0A=
diff --git a/hw/pci-host/gpex.c b/hw/pci-host/gpex.c=0A=
index 66055ee..de72408 100644=0A=
--- a/hw/pci-host/gpex.c=0A=
+++ b/hw/pci-host/gpex.c=0A=
@@ -43,6 +43,11 @@ static void gpex_set_irq(void *opaque, int irq_num, =
int level)=0A=
     qemu_set_irq(s->irq[irq_num], level);=0A=
 }=0A=
 =0A=
+static Property gpex_props[] =3D {=0A=
+    DEFINE_PROP_UINT32("stream-id-base", GPEXHost, stream_id=
_base, 0),=0A=
msi_base_base=0A=
+    DEFINE_PROP_END_OF_LIST(),=0A=
+};=0A=
+=0A=
 static void gpex_host_realize(DeviceState *dev, Error **errp)=0A=
 {=0A=
     PCIHostState *pci =3D PCI_HOST_BRIDGE(dev);=0A=
@@ -83,6 +88,7 @@ static void gpex_host_class_init(ObjectClass *klass, =
void *data)=0A=
 =0A=
     hc->root_bus_path =3D gpex_host_root_bus_path;=0A=
     dc->realize =3D gpex_host_realize;=0A=
+    dc->props =3D gpex_props;=0A=
     set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories);=0A=
     dc->fw_name =3D "pci";=0A=
 }=0A=
diff --git a/hw/pci/msi.c b/hw/pci/msi.c=0A=
index 7925851..b60a410 100644=0A=
--- a/hw/pci/msi.c=0A=
+++ b/hw/pci/msi.c=0A=
@@ -336,7 +336,7 @@ void msi_send_message(PCIDevice *dev, MSIMessage ms=
g)=0A=
 {=0A=
     MemTxAttrs attrs =3D {};=0A=
 =0A=
-    attrs.stream_id =3D pci_requester_id(dev);=0A=
+    attrs.stream_id =3D pci_stream_id(dev);=0A=
     address_space_stl_le(&dev->bus_master_as, msg.address, msg.data=
,=0A=
                          attrs, NULL);=0A=
 }=0A=
diff --git a/hw/pci/pci.c b/hw/pci/pci.c=0A=
index 259483b..92e9a2b 100644=0A=
--- a/hw/pci/pci.c=0A=
+++ b/hw/pci/pci.c=0A=
@@ -951,6 +951,30 @@ uint16_t pci_requester_id(PCIDevice *dev)=0A=
     return pci_req_id_cache_extract(&dev->requester_id_cache);=0A=
 }=0A=
 =0A=
+static uint32_t pci_get_stream_id_base(PCIDevice *dev)=0A=
+{=0A=
+    PCIBus *rootbus =3D pci_device_root_bus(dev);=0A=
+    PCIHostState *host_bridge =3D PCI_HOST_BRIDGE(rootbus->qbus.par=
ent);=0A=
+    Error *err =3D NULL;=0A=
+    int64_t stream_id;=0A=
+=0A=
+    stream_id =3D object_property_get_int(OBJECT(host_bridge), "s=
tream-id-base",=0A=
+                                        &err);=0A=
+    if (stream_id < 0) {=0A=
+        stream_id =3D 0;=0A=
+    }=0A=
+=0A=
+    return stream_id;=0A=
+}=0A=
+=0A=
+uint32_t pci_stream_id(PCIDevice *dev)=0A=
+{=0A=
+    /* Stream ID =3D RequesterID[15:0] + stream_id_base. stream_id=
_base may=0A=
+     * be 0 for devices that are not using any translation between req=
uester_id=0A=
+     * and stream_id */=0A=
+    return  (uint16_t)pci_requester_id(dev) + dev->stream_id_ba=
se;=0A=
+}=0A=
I think you should split the changes in virt from pci/gpex g=
eneric changes.

I agree.

=0A=
=0A=
+=0A=
 /* -1 for devfn means auto assign */=0A=
 static PCIDevice *do_pci_register_device(PCIDevice *pci_dev, PCIBus *bus,=
=0A=
                                          const char *name, int devfn,=0A=
@@ -1000,6 +1024,7 @@ static PCIDevice *do_pci_register_device(PCIDevic=
e *pci_dev, PCIBus *bus,=0A=
 =0A=
     pci_dev->devfn =3D devfn;=0A=
     pci_dev->requester_id_cache =3D pci_req_id_cache_get(pci_dev);=0A=
+    pci_dev->stream_id_base =3D pci_get_stream_id_base(pci_dev);=0A=
looks strange to me to store the rid base in the end point a=
s this is=0A=
rather a property of the PCI complex. I acknowledge this is much more=0A=
simple than reworking pci_requester_id() though.

I actually did implemented it in a different way at the beginning:

+uint32_t pci_stream_id(PCIDevice *dev)
+{
+    PCIBus *rootbus =3D pci_device_root_bus(dev);
+    PCIHostState *host_bridge =3D PCI_HOST_BRIDGE(rootb= us->qbus.parent);
+    Error *err =3D NULL;
+    int64_t stream_id;
+
+    stream_id =3D object_property_get_int(OBJECT(host_b= ridge), "stream-id-base",
+           &nbs= p;            &= nbsp;           &nbs= p;   &err);
+    if (stream_id < 0) {
+        stream_id =3D  0;
+    }
+    /* DeviceID =3D RequesterID[15:0] + stream_id_b= ase. If the stream-id-base
+     * property is not found (e.g. for platforms t= hat are not needing a
+     * global ID) the requester ID will be used in= stead. */
+    stream_id +=3D (uint16_t)pci_requester_id(dev);=
+
+    return stream_id;
+}

The reason I have changed was to avoid traversing the entire hierarchy each= time the ID is needed (for example each time when a MSI is sent).


=0A=
 =0A=
     memory_region_init(&pci_dev->bus_master_container_region, OBJEC=
T(pci_dev),=0A=
                        "bus master container", UINT64_MAX);=0A=
diff --git a/include/hw/arm/virt.h b/include/hw/arm/virt.h=0A=
index 33b0ff3..94c007a 100644=0A=
--- a/include/hw/arm/virt.h=0A=
+++ b/include/hw/arm/virt.h=0A=
@@ -99,6 +99,7 @@ typedef struct {=0A=
     struct arm_boot_info bootinfo;=0A=
     const MemMapEntry *memmap;=0A=
     const int *irqmap;=0A=
+    const uint32_t *streamidmap;=0A=
     int smp_cpus;=0A=
     void *fdt;=0A=
     int fdt_size;=0A=
diff --git a/include/hw/pci-host/gpex.h b/include/hw/pci-host/gpex.h=0A=
index 68c9348..47df01a 100644=0A=
--- a/include/hw/pci-host/gpex.h=0A=
+++ b/include/hw/pci-host/gpex.h=0A=
@@ -48,6 +48,8 @@ typedef struct GPEXHost {=0A=
 =0A=
     GPEXRootState gpex_root;=0A=
 =0A=
+    uint32_t stream_id_base;=0A=
+=0A=
     MemoryRegion io_ioport;=0A=
     MemoryRegion io_mmio;=0A=
     qemu_irq irq[GPEX_NUM_IRQS];=0A=
diff --git a/include/hw/pci/pci.h b/include/hw/pci/pci.h=0A=
index a37a2d5..e6e9334 100644=0A=
--- a/include/hw/pci/pci.h=0A=
+++ b/include/hw/pci/pci.h=0A=
@@ -283,6 +283,12 @@ struct PCIDevice {=0A=
      * MSI). For conventional PCI root complex, this field is=0A=
      * meaningless. */=0A=
     PCIReqIDCache requester_id_cache;=0A=
+    /* Some platforms need a unique ID for IOMMU source identification=
=0A=
+     * or MSI source identification. QEMU implements a simple scheme:=
=0A=
+     * stream_id =3D  stream_id_base + requester_id. The stream_id=
_base will=0A=
+     * ensure that all the devices in the system have different stream=
 ID=0A=
+     * domains */=0A=
+    uint32_t stream_id_base;=0A=
get rid of IOMMU terminology?

OK.

=0A=
=0A=
Note that when adding other sub-systems you will need to address the=0A=
ACPI side as the IORT table built by hw/arm/virt-acpi-build.c currently=0A=
defines an RID mapping for the single root complex.

I am not quite familiar with ACPI but for sure I will take a look into this= . Thanks for pointing it out.

Thanks,

Diana
--_000_AM3PR04MB0616B6DDCF5A59D8C29E9516FF890AM3PR04MB0616eurp_-- From MAILER-DAEMON Fri Aug 11 10:35:49 2017 Received: from list by lists.gnu.org with archive (Exim 4.71) id 1dgB2S-0002bW-QQ for mharc-qemu-arm@gnu.org; Fri, 11 Aug 2017 10:35:48 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:37450) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dgB2L-0002WY-G2 for qemu-arm@nongnu.org; Fri, 11 Aug 2017 10:35:43 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dgB2J-0007Dr-7y for qemu-arm@nongnu.org; Fri, 11 Aug 2017 10:35:41 -0400 Received: from mail-db5eur01on0072.outbound.protection.outlook.com ([104.47.2.72]:1184 helo=EUR01-DB5-obe.outbound.protection.outlook.com) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1dgB2C-0007C3-7g; Fri, 11 Aug 2017 10:35:32 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nxp.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version; bh=f1i107R/g2ROdEHH/qkgxAIGheUtomq20qrRdYQ7pqk=; b=DLxCP999D/YqHSKr6cKt0akP3i+ZA03q5bZ609pdWma9JQ3rA1uE8ATH7Q1BWlMmrxX9ZsLenAeJ7pmeQj13AeUpoTGzyMrmt/k0zBcfc6cpno4Uin4eSWqdyEzfLPcsI5afTJqksgpgticJMs3PBLtYy5BhUTWtcwNO/j8OOeY= Received: from AM3PR04MB0616.eurprd04.prod.outlook.com (10.255.133.15) by AM3PR04MB0806.eurprd04.prod.outlook.com (10.242.253.144) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384_P256) id 15.1.1341.17; Fri, 11 Aug 2017 14:35:29 +0000 Received: from AM3PR04MB0616.eurprd04.prod.outlook.com ([fe80::840e:32fc:ecf4:2ffb]) by AM3PR04MB0616.eurprd04.prod.outlook.com ([fe80::840e:32fc:ecf4:2ffb%14]) with mapi id 15.01.1341.019; Fri, 11 Aug 2017 14:35:28 +0000 From: Diana Madalina Craciun To: "Edgar E. Iglesias" , Auger Eric CC: "qemu-devel@nongnu.org" , "mst@redhat.com" , Mike Caraman , "qemu-arm@nongnu.org" , "marcel@redhat.com" , "Bharat Bhushan" , "christoffer.dall@linaro.org" , Laurentiu Tudor Thread-Topic: [Qemu-devel] [PATCH v2 2/2] Add a unique ID in the virt machine to be used as device ID Thread-Index: AQHS07WQhQaf1stp7kus9qldhP1WKg== Date: Fri, 11 Aug 2017 14:35:28 +0000 Message-ID: References: <1495537965-4187-1-git-send-email-diana.craciun@nxp.com> <1495537965-4187-3-git-send-email-diana.craciun@nxp.com> <20170731151602.GU4859@toto> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: authentication-results: spf=none (sender IP is ) smtp.mailfrom=diana.craciun@nxp.com; x-originating-ip: [192.88.146.1] x-ms-publictraffictype: Email x-microsoft-exchange-diagnostics: 1; AM3PR04MB0806; 6:vaWM7WE7bZyXx8T/XEu1Fo1/4JnAcjsIUZbZeSSHIAFdWmn9cRgteqEkW9jTG7JjeUedoYZSx+G7orN2IcZzybtnM81K0DJ08VvUUO/x+ykDDT6IiHZv2H2JoGYAimEjCF+6/5rRIPkzjI42FLbt/XWJueGIdEJF1Sjgg0HiJuXwl5bTG39MHDj9IaDIuWqLUNhcihQRgRjPhGsJPwEvw5oB7qUgAaAgLnJ4g5/9BWgqmnm/HLYC1dkURTxpGJYROk96t4fhtdYCMCXe7x9m1FbncHhgvxQq7pyOjN6LXizN+S7A/YnecQIG8Mg4UCEHCH/2MWjP8kk1zLdVUw6IrA==; 5:SvXxMOU/R35bJ2qrBWXsUXQLIAmY+NOWDJO/kDDYSmwEXsdINQ9IngZFo+1ORx7wDzkKLbJ1n380dx7IQalZ+hK7eWEQOxwi5kckfuPOF4wEjKJ98IxZdYJwUWEGdY3PufBrCV5DZgR8zLDbyHwGEQ==; 24:/HuGbmej6wGx4TAs/ALuz7i2L1UXk1eau00NJVWHUsudnkNP5uNHi96HXCf7z31zT3/WDxJZ1BHOliIx04tVXq8rnSVx4H2kd3IG4BCDq7c=; 7:sciA9/bcFMwSWlu3RG9Z9ypc41OWJfkK5jkq3reeU1gU5NJgD3XH46PCaDKdgXNyJGoEXndcMbDWwp1kMg/5hiKdeyvrdWsXKVvVNCMczWnoCiRMD2aKdDi+D2qFgQ/6WMdVm7Zw5sCR4CTaF+YK4Oj5R9r0uNWk6uuUbue9wsojX7vjH7BPzHjogi5KC3YDKkARdEIuJxJiTGFtSid+TYAEpAEX0GCghur4pQLflyk= x-ms-exchange-antispam-srfa-diagnostics: SSOS;SSOR; x-forefront-antispam-report: SFV:SKI; SCL:-1; SFV:NSPM; SFS:(10009020)(6009001)(39860400002)(199003)(51444003)(189002)(377454003)(24454002)(2900100001)(54906002)(14454004)(99286003)(105586002)(55016002)(101416001)(106356001)(6436002)(50986999)(76176999)(54356999)(9686003)(2906002)(5250100002)(93886004)(6506006)(7736002)(229853002)(189998001)(305945005)(66066001)(81156014)(8676002)(81166006)(8936002)(551934003)(7696004)(3660700001)(33656002)(39060400002)(478600001)(102836003)(3846002)(5660300001)(6116002)(4326008)(97736004)(53546010)(6246003)(25786009)(3280700002)(53936002)(68736007)(74316002)(86362001)(575784001); DIR:OUT; SFP:1101; SCL:1; SRVR:AM3PR04MB0806; H:AM3PR04MB0616.eurprd04.prod.outlook.com; FPR:; SPF:None; PTR:InfoNoRecords; A:1; MX:1; LANG:en; x-ms-office365-filtering-correlation-id: 2ca667f4-c91f-4056-e500-08d4e0c6366c x-ms-office365-filtering-ht: Tenant x-microsoft-antispam: UriScan:; BCL:0; PCL:0; RULEID:(300000500095)(300135000095)(300000501095)(300135300095)(300000502095)(300135100095)(22001)(2017030254152)(300000503095)(300135400095)(48565401081)(2017052603031)(201703131423075)(201703031133081)(201702281549075)(300000504095)(300135200095)(300000505095)(300135600095)(300000506095)(300135500095); SRVR:AM3PR04MB0806; x-ms-traffictypediagnostic: AM3PR04MB0806: x-exchange-antispam-report-test: UriScan:(185117386973197); x-microsoft-antispam-prvs: x-exchange-antispam-report-cfa-test: BCL:0; PCL:0; RULEID:(100000700101)(100105000095)(100000701101)(100105300095)(100000702101)(100105100095)(6040450)(601004)(2401047)(5005006)(8121501046)(3002001)(10201501046)(100000703101)(100105400095)(93006095)(93001095)(6055026)(6041248)(201703131423075)(201702281528075)(201703061421075)(201703061406153)(20161123555025)(20161123562025)(20161123564025)(20161123558100)(20161123560025)(6072148)(201708071742011)(100000704101)(100105200095)(100000705101)(100105500095); SRVR:AM3PR04MB0806; BCL:0; PCL:0; RULEID:(100000800101)(100110000095)(100000801101)(100110300095)(100000802101)(100110100095)(100000803101)(100110400095)(100000804101)(100110200095)(100000805101)(100110500095); SRVR:AM3PR04MB0806; x-forefront-prvs: 03965EFC76 received-spf: None (protection.outlook.com: nxp.com does not designate permitted sender hosts) spamdiagnosticoutput: 1:99 spamdiagnosticmetadata: NSPM Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-originalarrivaltime: 11 Aug 2017 14:35:28.5753 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM3PR04MB0806 X-detected-operating-system: by eggs.gnu.org: Windows 7 or 8 [fuzzy] X-Received-From: 104.47.2.72 Subject: Re: [Qemu-arm] [Qemu-devel] [PATCH v2 2/2] Add a unique ID in the virt machine to be used as device ID X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 11 Aug 2017 14:35:43 -0000 Hi Edgar,=0A= =0A= On 07/31/2017 06:16 PM, Edgar E. Iglesias wrote:=0A= > On Wed, Jul 26, 2017 at 02:22:28PM +0200, Auger Eric wrote:=0A= >> Hi Diana,=0A= >> On 23/05/2017 13:12, Diana Craciun wrote:=0A= >>> Device IDs are required by the ARM GICv3 ITS for IRQ remapping.=0A= >>> Currently, for PCI devices, the requester ID was used as device=0A= >>> ID in the virt machine. If the system has multiple masters that=0A= >> if the system has multiple root complex?=0A= >>> use MSIs a unique ID accross the platform is needed.=0A= >> across=0A= >>> A static scheme is used and each master is allocated a range of IDs=0A= >>> with the formula:=0A= >>> DeviceID =3D zero_extend( RequesterID[15:0] ) + 0x10000*Constant (as=0A= >>> recommended by SBSA).=0A= >>>=0A= >>> This ID will be configured in the machine creation and if not configure= d=0A= >>> the PCI requester ID will be used insteead.=0A= >> instead=0A= >>> Signed-off-by: Diana Craciun =0A= >>> ---=0A= >>> hw/arm/virt.c | 26 ++++++++++++++++++++++++++=0A= >>> hw/pci-host/gpex.c | 6 ++++++=0A= >>> hw/pci/msi.c | 2 +-=0A= >>> hw/pci/pci.c | 25 +++++++++++++++++++++++++=0A= >>> include/hw/arm/virt.h | 1 +=0A= >>> include/hw/pci-host/gpex.h | 2 ++=0A= >>> include/hw/pci/pci.h | 8 ++++++++=0A= >>> kvm-all.c | 4 ++--=0A= >>> 8 files changed, 71 insertions(+), 3 deletions(-)=0A= >>>=0A= >>> diff --git a/hw/arm/virt.c b/hw/arm/virt.c=0A= >>> index 5f62a03..a969694 100644=0A= >>> --- a/hw/arm/virt.c=0A= >>> +++ b/hw/arm/virt.c=0A= >>> @@ -110,6 +110,8 @@ static ARMPlatformBusSystemParams platform_bus_para= ms;=0A= >>> #define RAMLIMIT_GB 255=0A= >>> #define RAMLIMIT_BYTES (RAMLIMIT_GB * 1024ULL * 1024 * 1024)=0A= >>> =0A= >>> +#define STREAM_ID_RANGE_SIZE 0x10000=0A= >>> +=0A= >>> /* Addresses and sizes of our components.=0A= >>> * 0..128MB is space for a flash device so we can run bootrom code suc= h as UEFI.=0A= >>> * 128MB..256MB is used for miscellaneous device I/O.=0A= >>> @@ -162,6 +164,22 @@ static const int a15irqmap[] =3D {=0A= >>> [VIRT_PLATFORM_BUS] =3D 112, /* ...to 112 + PLATFORM_BUS_NUM_IRQS = -1 */=0A= >>> };=0A= >>> =0A= >>> +/* Device IDs are required by the ARM GICV3 ITS for IRQ remapping. Cur= rently=0A= >>> + * for PCI devices the requester ID was used as device ID. But if the = system has=0A= >>> + * multiple masters that use MSIs, the requester ID may cause deviceID= clashes.=0A= >>> + * So a unique number is needed accross the system.=0A= >>> + * We are using the following formula:=0A= >>> + * DeviceID =3D zero_extend( RequesterID[15:0] ) + 0x10000*Constant=0A= >>> + * (as recommanded by SBSA). Currently we do not have an SMMU emulatio= n, but the=0A= >>> + * same formula can be used for the generation of the streamID as well= .=0A= >>> + * For each master the device ID will be derrived from the requester I= D using=0A= >>> + * the abovemntione formula.=0A= >>> + */=0A= >> I think most of this comment should only be in the commit message. typos= =0A= >> in derived and above mentioned.=0A= >>=0A= >> stream id is the terminology for the id space at the input of the smmu.= =0A= >> device id is the terminology for the id space at the input of the msi=0A= >> controller I think.=0A= >>=0A= >> RID -> deviceID (no IOMMU)=0A= >> RID -> streamID -> deviceID (IOMMU)=0A= >>=0A= >> I would personally get rid of all streamid uses as the smmu is not yet= =0A= >> supported and stick to the=0A= >> Documentation/devicetree/bindings/pci/pci-msi.txt terminology?=0A= >>=0A= >>> +=0A= >>> +static const uint32_t streamidmap[] =3D {=0A= >>> + [VIRT_PCIE] =3D 0, /* currently only one PCI controller */= =0A= >>> +};=0A= >>> +=0A= >>> static const char *valid_cpus[] =3D {=0A= >>> "cortex-a15",=0A= >>> "cortex-a53",=0A= >>> @@ -980,6 +998,7 @@ static void create_pcie(const VirtMachineState *vms= , qemu_irq *pic)=0A= >>> hwaddr base_ecam =3D vms->memmap[VIRT_PCIE_ECAM].base;=0A= >>> hwaddr size_ecam =3D vms->memmap[VIRT_PCIE_ECAM].size;=0A= >>> hwaddr base =3D base_mmio;=0A= >>> + uint32_t stream_id =3D vms->streamidmap[VIRT_PCIE] * STREAM_ID_RAN= GE_SIZE;=0A= >> msi-base?=0A= >> STREAM_ID_RANGE_SIZE ~ MSI_MAP_LENGTH?=0A= >>> int nr_pcie_buses =3D size_ecam / PCIE_MMCFG_SIZE_MIN;=0A= >>> int irq =3D vms->irqmap[VIRT_PCIE];=0A= >>> MemoryRegion *mmio_alias;=0A= >>> @@ -992,6 +1011,7 @@ static void create_pcie(const VirtMachineState *vm= s, qemu_irq *pic)=0A= >>> PCIHostState *pci;=0A= >>> =0A= >>> dev =3D qdev_create(NULL, TYPE_GPEX_HOST);=0A= >>> + qdev_prop_set_uint32(dev, "stream-id-base", stream_id);=0A= >>> qdev_init_nofail(dev);=0A= >>> =0A= >>> /* Map only the first size_ecam bytes of ECAM space */=0A= >>> @@ -1056,6 +1076,11 @@ static void create_pcie(const VirtMachineState *= vms, qemu_irq *pic)=0A= >>> if (vms->msi_phandle) {=0A= >>> qemu_fdt_setprop_cells(vms->fdt, nodename, "msi-parent",=0A= >>> vms->msi_phandle);=0A= >>> + qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "msi-map",=0A= >>> + 1, 0,=0A= >>> + 1, vms->msi_phandle,=0A= >>> + 1, stream_id,=0A= >>> + 1, STREAM_ID_RANGE_SIZE);=0A= >>> }=0A= >>> =0A= >>> qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg",=0A= >>> @@ -1609,6 +1634,7 @@ static void virt_2_9_instance_init(Object *obj)= =0A= >>> =0A= >>> vms->memmap =3D a15memmap;=0A= >>> vms->irqmap =3D a15irqmap;=0A= >>> + vms->streamidmap =3D streamidmap;=0A= >>> }=0A= >>> =0A= >>> static void virt_machine_2_9_options(MachineClass *mc)=0A= >>> diff --git a/hw/pci-host/gpex.c b/hw/pci-host/gpex.c=0A= >>> index 66055ee..de72408 100644=0A= >>> --- a/hw/pci-host/gpex.c=0A= >>> +++ b/hw/pci-host/gpex.c=0A= >>> @@ -43,6 +43,11 @@ static void gpex_set_irq(void *opaque, int irq_num, = int level)=0A= >>> qemu_set_irq(s->irq[irq_num], level);=0A= >>> }=0A= >>> =0A= >>> +static Property gpex_props[] =3D {=0A= >>> + DEFINE_PROP_UINT32("stream-id-base", GPEXHost, stream_id_base, 0),= =0A= >> msi_base_base=0A= >>> + DEFINE_PROP_END_OF_LIST(),=0A= >>> +};=0A= >>> +=0A= >>> static void gpex_host_realize(DeviceState *dev, Error **errp)=0A= >>> {=0A= >>> PCIHostState *pci =3D PCI_HOST_BRIDGE(dev);=0A= >>> @@ -83,6 +88,7 @@ static void gpex_host_class_init(ObjectClass *klass, = void *data)=0A= >>> =0A= >>> hc->root_bus_path =3D gpex_host_root_bus_path;=0A= >>> dc->realize =3D gpex_host_realize;=0A= >>> + dc->props =3D gpex_props;=0A= >>> set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories);=0A= >>> dc->fw_name =3D "pci";=0A= >>> }=0A= >>> diff --git a/hw/pci/msi.c b/hw/pci/msi.c=0A= >>> index 7925851..b60a410 100644=0A= >>> --- a/hw/pci/msi.c=0A= >>> +++ b/hw/pci/msi.c=0A= >>> @@ -336,7 +336,7 @@ void msi_send_message(PCIDevice *dev, MSIMessage ms= g)=0A= >>> {=0A= >>> MemTxAttrs attrs =3D {};=0A= >>> =0A= >>> - attrs.stream_id =3D pci_requester_id(dev);=0A= >>> + attrs.stream_id =3D pci_stream_id(dev);=0A= >>> address_space_stl_le(&dev->bus_master_as, msg.address, msg.data,= =0A= >>> attrs, NULL);=0A= >>> }=0A= >>> diff --git a/hw/pci/pci.c b/hw/pci/pci.c=0A= >>> index 259483b..92e9a2b 100644=0A= >>> --- a/hw/pci/pci.c=0A= >>> +++ b/hw/pci/pci.c=0A= >>> @@ -951,6 +951,30 @@ uint16_t pci_requester_id(PCIDevice *dev)=0A= >>> return pci_req_id_cache_extract(&dev->requester_id_cache);=0A= >>> }=0A= >>> =0A= >>> +static uint32_t pci_get_stream_id_base(PCIDevice *dev)=0A= >>> +{=0A= >>> + PCIBus *rootbus =3D pci_device_root_bus(dev);=0A= >>> + PCIHostState *host_bridge =3D PCI_HOST_BRIDGE(rootbus->qbus.parent= );=0A= >>> + Error *err =3D NULL;=0A= >>> + int64_t stream_id;=0A= >>> +=0A= >>> + stream_id =3D object_property_get_int(OBJECT(host_bridge), "stream= -id-base",=0A= >>> + &err);=0A= >>> + if (stream_id < 0) {=0A= >>> + stream_id =3D 0;=0A= >>> + }=0A= >>> +=0A= >>> + return stream_id;=0A= >>> +}=0A= >>> +=0A= >>> +uint32_t pci_stream_id(PCIDevice *dev)=0A= >>> +{=0A= >>> + /* Stream ID =3D RequesterID[15:0] + stream_id_base. stream_id_bas= e may=0A= >>> + * be 0 for devices that are not using any translation between req= uester_id=0A= >>> + * and stream_id */=0A= >>> + return (uint16_t)pci_requester_id(dev) + dev->stream_id_base;=0A= >>> +}=0A= >> I think you should split the changes in virt from pci/gpex generic chang= es.=0A= >>=0A= >>> +=0A= >>> /* -1 for devfn means auto assign */=0A= >>> static PCIDevice *do_pci_register_device(PCIDevice *pci_dev, PCIBus *b= us,=0A= >>> const char *name, int devfn,= =0A= >>> @@ -1000,6 +1024,7 @@ static PCIDevice *do_pci_register_device(PCIDevic= e *pci_dev, PCIBus *bus,=0A= >>> =0A= >>> pci_dev->devfn =3D devfn;=0A= >>> pci_dev->requester_id_cache =3D pci_req_id_cache_get(pci_dev);=0A= >>> + pci_dev->stream_id_base =3D pci_get_stream_id_base(pci_dev);=0A= >> looks strange to me to store the rid base in the end point as this is=0A= >> rather a property of the PCI complex. I acknowledge this is much more=0A= > I agree.=0A= =0A= The reason I have changed was to avoid traversing the entire hierarchy=0A= each time the ID is needed (for example each time when a MSI is sent).=0A= =0A= > I think that what we need is to add support for allowing PCI RCs=0A= > to transform requesterIDs in transactions attributes according to the=0A= > implementation specifics.=0A= =0A= Do you mean that you need more than a linear offset between requesterID=0A= and whatever other ID?=0A= =0A= >=0A= > The way we did it when modelling the ZynqMP is by adding support for=0A= > transaction attribute translation in QEMU's IOMMU interface.=0A= > In our PCI RC, we have an IOMMU covering the entire AS that PCI devs DMA = into.=0A= > This IOMMU doesn't do address-translation, only RequesterID -> StreamID= =0A= > transforms according to how the ZynqMP PCI RC derives StreamIDs from Requ= esterIDs.=0A= =0A= Are there any patches for this support in order for me to better understand= ?=0A= =0A= Thanks,=0A= =0A= Diana=0A= =0A= =0A= > This is useful not only to model PCI RequesterID to AXI Master ID mapping= s but=0A= > also for modelling things like the ARM TZC (or the Xilinx ZynqMP XMPU/XPP= Us).=0A= >=0A= > Cheers,=0A= > Edgar=0A= >=0A= >=0A= >> simple than reworking pci_requester_id() though.=0A= >>> =0A= >>> memory_region_init(&pci_dev->bus_master_container_region, OBJECT(p= ci_dev),=0A= >>> "bus master container", UINT64_MAX);=0A= >>> diff --git a/include/hw/arm/virt.h b/include/hw/arm/virt.h=0A= >>> index 33b0ff3..94c007a 100644=0A= >>> --- a/include/hw/arm/virt.h=0A= >>> +++ b/include/hw/arm/virt.h=0A= >>> @@ -99,6 +99,7 @@ typedef struct {=0A= >>> struct arm_boot_info bootinfo;=0A= >>> const MemMapEntry *memmap;=0A= >>> const int *irqmap;=0A= >>> + const uint32_t *streamidmap;=0A= >>> int smp_cpus;=0A= >>> void *fdt;=0A= >>> int fdt_size;=0A= >>> diff --git a/include/hw/pci-host/gpex.h b/include/hw/pci-host/gpex.h=0A= >>> index 68c9348..47df01a 100644=0A= >>> --- a/include/hw/pci-host/gpex.h=0A= >>> +++ b/include/hw/pci-host/gpex.h=0A= >>> @@ -48,6 +48,8 @@ typedef struct GPEXHost {=0A= >>> =0A= >>> GPEXRootState gpex_root;=0A= >>> =0A= >>> + uint32_t stream_id_base;=0A= >>> +=0A= >>> MemoryRegion io_ioport;=0A= >>> MemoryRegion io_mmio;=0A= >>> qemu_irq irq[GPEX_NUM_IRQS];=0A= >>> diff --git a/include/hw/pci/pci.h b/include/hw/pci/pci.h=0A= >>> index a37a2d5..e6e9334 100644=0A= >>> --- a/include/hw/pci/pci.h=0A= >>> +++ b/include/hw/pci/pci.h=0A= >>> @@ -283,6 +283,12 @@ struct PCIDevice {=0A= >>> * MSI). For conventional PCI root complex, this field is=0A= >>> * meaningless. */=0A= >>> PCIReqIDCache requester_id_cache;=0A= >>> + /* Some platforms need a unique ID for IOMMU source identification= =0A= >>> + * or MSI source identification. QEMU implements a simple scheme:= =0A= >>> + * stream_id =3D stream_id_base + requester_id. The stream_id_bas= e will=0A= >>> + * ensure that all the devices in the system have different stream= ID=0A= >>> + * domains */=0A= >>> + uint32_t stream_id_base;=0A= >> get rid of IOMMU terminology?=0A= >>=0A= >> Note that when adding other sub-systems you will need to address the=0A= >> ACPI side as the IORT table built by hw/arm/virt-acpi-build.c currently= =0A= >> defines an RID mapping for the single root complex.=0A= >>=0A= >> Thanks=0A= >>=0A= >> Eric=0A= >>> char name[64];=0A= >>> PCIIORegion io_regions[PCI_NUM_REGIONS];=0A= >>> AddressSpace bus_master_as;=0A= >>> @@ -737,6 +743,8 @@ static inline uint16_t pci_get_bdf(PCIDevice *dev)= =0A= >>> =0A= >>> uint16_t pci_requester_id(PCIDevice *dev);=0A= >>> =0A= >>> +uint32_t pci_stream_id(PCIDevice *dev);=0A= >>> +=0A= >>> /* DMA access functions */=0A= >>> static inline AddressSpace *pci_get_address_space(PCIDevice *dev)=0A= >>> {=0A= >>> diff --git a/kvm-all.c b/kvm-all.c=0A= >>> index 90b8573..5a508c3 100644=0A= >>> --- a/kvm-all.c=0A= >>> +++ b/kvm-all.c=0A= >>> @@ -1280,7 +1280,7 @@ int kvm_irqchip_add_msi_route(KVMState *s, int ve= ctor, PCIDevice *dev)=0A= >>> kroute.u.msi.data =3D le32_to_cpu(msg.data);=0A= >>> if (kvm_msi_devid_required()) {=0A= >>> kroute.flags =3D KVM_MSI_VALID_DEVID;=0A= >>> - kroute.u.msi.devid =3D pci_requester_id(dev);=0A= >>> + kroute.u.msi.devid =3D pci_stream_id(dev);=0A= >>> }=0A= >>> if (kvm_arch_fixup_msi_route(&kroute, msg.address, msg.data, dev))= {=0A= >>> kvm_irqchip_release_virq(s, virq);=0A= >>> @@ -1317,7 +1317,7 @@ int kvm_irqchip_update_msi_route(KVMState *s, int= virq, MSIMessage msg,=0A= >>> kroute.u.msi.data =3D le32_to_cpu(msg.data);=0A= >>> if (kvm_msi_devid_required()) {=0A= >>> kroute.flags =3D KVM_MSI_VALID_DEVID;=0A= >>> - kroute.u.msi.devid =3D pci_requester_id(dev);=0A= >>> + kroute.u.msi.devid =3D pci_stream_id(dev);=0A= >>> }=0A= >>> if (kvm_arch_fixup_msi_route(&kroute, msg.address, msg.data, dev))= {=0A= >>> return -EINVAL;=0A= >>>=0A= =0A= From MAILER-DAEMON Fri Aug 11 11:39:20 2017 Received: from list by lists.gnu.org with archive (Exim 4.71) id 1dgC1w-00018Q-6P for mharc-qemu-arm@gnu.org; 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charset="utf-8" Content-Transfer-Encoding: base64 Resent-From: From: no-reply@patchew.org To: eric.auger@redhat.com Cc: famz@redhat.com, eric.auger.pro@gmail.com, eric.auger@redhat.com, peter.maydell@linaro.org, qemu-arm@nongnu.org, qemu-devel@nongnu.org, alex.williamson@redhat.com, prem.mallappa@gmail.com, mohun106@gmail.com, drjones@redhat.com, tcain@qti.qualcomm.com, Radha.Chintakuntla@cavium.com, Sunil.Goutham@cavium.com, mst@redhat.com, jean-philippe.brucker@arm.com, tn@semihalf.com, will.deacon@arm.com, robin.murphy@arm.com, peterx@redhat.com, edgar.iglesias@gmail.com, bharat.bhushan@nxp.com, christoffer.dall@linaro.org Date: Fri, 11 Aug 2017 08:38:30 -0700 (PDT) X-ZohoMailClient: External X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [fuzzy] X-Received-From: 135.84.80.217 Subject: Re: [Qemu-arm] [Qemu-devel] [RFC v6 0/9] ARM SMMUv3 Emulation Support X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 11 Aug 2017 15:39:19 -0000 SGksCgpUaGlzIHNlcmllcyBzZWVtcyB0byBoYXZlIHNvbWUgY29kaW5nIHN0eWxlIHByb2JsZW1z LiBTZWUgb3V0cHV0IGJlbG93IGZvcgptb3JlIGluZm9ybWF0aW9uOgoKTWVzc2FnZS1pZDogMTUw MjQ2MTM1NC0xMTMyNy0xLWdpdC1zZW5kLWVtYWlsLWVyaWMuYXVnZXJAcmVkaGF0LmNvbQpTdWJq ZWN0OiBbUWVtdS1kZXZlbF0gW1JGQyB2NiAwLzldIEFSTSBTTU1VdjMgRW11bGF0aW9uIFN1cHBv cnQKVHlwZTogc2VyaWVzCgo9PT0gVEVTVCBTQ1JJUFQgQkVHSU4gPT09CiMhL2Jpbi9iYXNoCgpC QVNFPWJhc2UKbj0xCnRvdGFsPSQoZ2l0IGxvZyAtLW9uZWxpbmUgJEJBU0UuLiB8IHdjIC1sKQpm YWlsZWQ9MAoKZ2l0IGNvbmZpZyAtLWxvY2FsIGRpZmYucmVuYW1lbGltaXQgMApnaXQgY29uZmln IC0tbG9jYWwgZGlmZi5yZW5hbWVzIFRydWUKCmNvbW1pdHM9IiQoZ2l0IGxvZyAtLWZvcm1hdD0l SCAtLXJldmVyc2UgJEJBU0UuLikiCmZvciBjIGluICRjb21taXRzOyBkbwogICAgZWNobyAiQ2hl Y2tpbmcgUEFUQ0ggJG4vJHRvdGFsOiAkKGdpdCBsb2cgLW4gMSAtLWZvcm1hdD0lcyAkYykuLi4i CiAgICBpZiAhIGdpdCBzaG93ICRjIC0tZm9ybWF0PWVtYWlsIHwgLi9zY3JpcHRzL2NoZWNrcGF0 Y2gucGwgLS1tYWlsYmFjayAtOyB0aGVuCiAgICAgICAgZmFpbGVkPTEKICAgICAgICBlY2hvCiAg ICBmaQogICAgbj0kKChuKzEpKQpkb25lCgpleGl0ICRmYWlsZWQKPT09IFRFU1QgU0NSSVBUIEVO RCA9PT0KClVwZGF0aW5nIDNjOGNmNWE5YzIxZmY4NzgyMTY0ZDFkZWY3ZjQ0YmQ4ODg3MTMzODQK U3dpdGNoZWQgdG8gYSBuZXcgYnJhbmNoICd0ZXN0JwozZTYyY2VkZDczIGh3L2FybS92aXJ0LWFj cGktYnVpbGQ6IFVzZSB0aGUgQUNQSV9JT1JUX1NNTVVfVjNfQ0FDSElOR19NT0RFIG1vZGVsCjNh NTEwOTRlZTkgaHcvYXJtL3NtbXV2MzogVkZJTyBpbnRlZ3JhdGlvbgo4MTU1NzU1MTVmIHRhcmdl dC9hcm0va3ZtOiBUcmFuc2xhdGUgdGhlIE1TSSBkb29yYmVsbCBpbiBrdm1fYXJjaF9maXh1cF9t c2lfcm91dGUKZjcyYmM2YWU2NyBody9hcm0vdmlydDogQWRkIHRsYmktb24tbWFwIHByb3BlcnR5 IHRvIHRoZSBzbW11djMgbm9kZQo1MmEyNTY5ZmU3IGh3L2FybS92aXJ0LWFjcGktYnVpbGQ6IEFk ZCBzbW11djMgbm9kZSBpbiBJT1JUIHRhYmxlCjYyYzNjMmZjYWUgaHcvYXJtL3ZpcnQ6IEFkZCAy LjExIG1hY2hpbmUgdHlwZQo4MDY3MWI0ZTkwIGh3L2FybS92aXJ0OiBBZGQgU01NVXYzIHRvIHRo ZSB2aXJ0IGJvYXJkCmFlMWMyMDNkNzMgaHcvYXJtL3NtbXV2Mzogc21tdXYzIGVtdWxhdGlvbiBt b2RlbApiY2I3ZDZlNDVkIGh3L2FybS9zbW11LWNvbW1vbjogc21tdSBiYXNlIGNsYXNzCgo9PT0g T1VUUFVUIEJFR0lOID09PQpDaGVja2luZyBQQVRDSCAxLzk6IGh3L2FybS9zbW11LWNvbW1vbjog c21tdSBiYXNlIGNsYXNzLi4uCkNoZWNraW5nIFBBVENIIDIvOTogaHcvYXJtL3NtbXV2Mzogc21t dXYzIGVtdWxhdGlvbiBtb2RlbC4uLgpDaGVja2luZyBQQVRDSCAzLzk6IGh3L2FybS92aXJ0OiBB ZGQgU01NVXYzIHRvIHRoZSB2aXJ0IGJvYXJkLi4uCkNoZWNraW5nIFBBVENIIDQvOTogaHcvYXJt L3ZpcnQ6IEFkZCAyLjExIG1hY2hpbmUgdHlwZS4uLgpDaGVja2luZyBQQVRDSCA1Lzk6IGh3L2Fy bS92aXJ0LWFjcGktYnVpbGQ6IEFkZCBzbW11djMgbm9kZSBpbiBJT1JUIHRhYmxlLi4uCkNoZWNr aW5nIFBBVENIIDYvOTogaHcvYXJtL3ZpcnQ6IEFkZCB0bGJpLW9uLW1hcCBwcm9wZXJ0eSB0byB0 aGUgc21tdXYzIG5vZGUuLi4KQ2hlY2tpbmcgUEFUQ0ggNy85OiB0YXJnZXQvYXJtL2t2bTogVHJh bnNsYXRlIHRoZSBNU0kgZG9vcmJlbGwgaW4ga3ZtX2FyY2hfZml4dXBfbXNpX3JvdXRlLi4uCkNo ZWNraW5nIFBBVENIIDgvOTogaHcvYXJtL3NtbXV2MzogVkZJTyBpbnRlZ3JhdGlvbi4uLgpDaGVj a2luZyBQQVRDSCA5Lzk6IGh3L2FybS92aXJ0LWFjcGktYnVpbGQ6IFVzZSB0aGUgQUNQSV9JT1JU X1NNTVVfVjNfQ0FDSElOR19NT0RFIG1vZGVsLi4uCkVSUk9SOiBjb2RlIGluZGVudCBzaG91bGQg bmV2ZXIgdXNlIHRhYnMKIzI2OiBGSUxFOiBody9hcm0vdmlydC1hY3BpLWJ1aWxkLmM6NDQwOgor XkleSXNtbXUtPm1vZGVsID0gMHgzOyAvKiBBQ1BJX0lPUlRfU01NVV9WM19DQUNISU5HX01PREUg Ki8kCgp0b3RhbDogMSBlcnJvcnMsIDAgd2FybmluZ3MsIDE0IGxpbmVzIGNoZWNrZWQKCllvdXIg cGF0Y2ggaGFzIHN0eWxlIHByb2JsZW1zLCBwbGVhc2UgcmV2aWV3LiAgSWYgYW55IG9mIHRoZXNl IGVycm9ycwphcmUgZmFsc2UgcG9zaXRpdmVzIHJlcG9ydCB0aGVtIHRvIHRoZSBtYWludGFpbmVy LCBzZWUKQ0hFQ0tQQVRDSCBpbiBNQUlOVEFJTkVSUy4KCj09PSBPVVRQVVQgRU5EID09PQoKVGVz dCBjb21tYW5kIGV4aXRlZCB3aXRoIGNvZGU6IDEKCgotLS0KRW1haWwgZ2VuZXJhdGVkIGF1dG9t YXRpY2FsbHkgYnkgUGF0Y2hldyBbaHR0cDovL3BhdGNoZXcub3JnL10uClBsZWFzZSBzZW5kIHlv dXIgZmVlZGJhY2sgdG8gcGF0Y2hldy1kZXZlbEBmcmVlbGlzdHMub3Jn From MAILER-DAEMON Fri Aug 11 11:50:54 2017 Received: from list by lists.gnu.org with archive (Exim 4.71) id 1dgCD8-0006Rt-0y for mharc-qemu-arm@gnu.org; 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[81.231.233.234]) by smtp.gmail.com with ESMTPSA id g38sm196646lfi.79.2017.08.11.08.50.27 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 11 Aug 2017 08:50:28 -0700 (PDT) Date: Fri, 11 Aug 2017 17:50:27 +0200 From: "Edgar E. Iglesias" To: Diana Madalina Craciun Cc: Auger Eric , "qemu-devel@nongnu.org" , "mst@redhat.com" , Mike Caraman , "qemu-arm@nongnu.org" , "marcel@redhat.com" , Bharat Bhushan , "christoffer.dall@linaro.org" , Laurentiu Tudor Message-ID: <20170811155027.GO4859@toto> References: <1495537965-4187-1-git-send-email-diana.craciun@nxp.com> <1495537965-4187-3-git-send-email-diana.craciun@nxp.com> <20170731151602.GU4859@toto> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.5.24 (2015-08-30) X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4010:c07::241 Subject: Re: [Qemu-arm] [Qemu-devel] [PATCH v2 2/2] Add a unique ID in the virt machine to be used as device ID X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 11 Aug 2017 15:50:52 -0000 On Fri, Aug 11, 2017 at 02:35:28PM +0000, Diana Madalina Craciun wrote: > Hi Edgar, > > On 07/31/2017 06:16 PM, Edgar E. Iglesias wrote: > > On Wed, Jul 26, 2017 at 02:22:28PM +0200, Auger Eric wrote: > >> Hi Diana, > >> On 23/05/2017 13:12, Diana Craciun wrote: > >>> Device IDs are required by the ARM GICv3 ITS for IRQ remapping. > >>> Currently, for PCI devices, the requester ID was used as device > >>> ID in the virt machine. If the system has multiple masters that > >> if the system has multiple root complex? > >>> use MSIs a unique ID accross the platform is needed. > >> across > >>> A static scheme is used and each master is allocated a range of IDs > >>> with the formula: > >>> DeviceID = zero_extend( RequesterID[15:0] ) + 0x10000*Constant (as > >>> recommended by SBSA). > >>> > >>> This ID will be configured in the machine creation and if not configured > >>> the PCI requester ID will be used insteead. > >> instead > >>> Signed-off-by: Diana Craciun > >>> --- > >>> hw/arm/virt.c | 26 ++++++++++++++++++++++++++ > >>> hw/pci-host/gpex.c | 6 ++++++ > >>> hw/pci/msi.c | 2 +- > >>> hw/pci/pci.c | 25 +++++++++++++++++++++++++ > >>> include/hw/arm/virt.h | 1 + > >>> include/hw/pci-host/gpex.h | 2 ++ > >>> include/hw/pci/pci.h | 8 ++++++++ > >>> kvm-all.c | 4 ++-- > >>> 8 files changed, 71 insertions(+), 3 deletions(-) > >>> > >>> diff --git a/hw/arm/virt.c b/hw/arm/virt.c > >>> index 5f62a03..a969694 100644 > >>> --- a/hw/arm/virt.c > >>> +++ b/hw/arm/virt.c > >>> @@ -110,6 +110,8 @@ static ARMPlatformBusSystemParams platform_bus_params; > >>> #define RAMLIMIT_GB 255 > >>> #define RAMLIMIT_BYTES (RAMLIMIT_GB * 1024ULL * 1024 * 1024) > >>> > >>> +#define STREAM_ID_RANGE_SIZE 0x10000 > >>> + > >>> /* Addresses and sizes of our components. > >>> * 0..128MB is space for a flash device so we can run bootrom code such as UEFI. > >>> * 128MB..256MB is used for miscellaneous device I/O. > >>> @@ -162,6 +164,22 @@ static const int a15irqmap[] = { > >>> [VIRT_PLATFORM_BUS] = 112, /* ...to 112 + PLATFORM_BUS_NUM_IRQS -1 */ > >>> }; > >>> > >>> +/* Device IDs are required by the ARM GICV3 ITS for IRQ remapping. Currently > >>> + * for PCI devices the requester ID was used as device ID. But if the system has > >>> + * multiple masters that use MSIs, the requester ID may cause deviceID clashes. > >>> + * So a unique number is needed accross the system. > >>> + * We are using the following formula: > >>> + * DeviceID = zero_extend( RequesterID[15:0] ) + 0x10000*Constant > >>> + * (as recommanded by SBSA). Currently we do not have an SMMU emulation, but the > >>> + * same formula can be used for the generation of the streamID as well. > >>> + * For each master the device ID will be derrived from the requester ID using > >>> + * the abovemntione formula. > >>> + */ > >> I think most of this comment should only be in the commit message. typos > >> in derived and above mentioned. > >> > >> stream id is the terminology for the id space at the input of the smmu. > >> device id is the terminology for the id space at the input of the msi > >> controller I think. > >> > >> RID -> deviceID (no IOMMU) > >> RID -> streamID -> deviceID (IOMMU) > >> > >> I would personally get rid of all streamid uses as the smmu is not yet > >> supported and stick to the > >> Documentation/devicetree/bindings/pci/pci-msi.txt terminology? > >> > >>> + > >>> +static const uint32_t streamidmap[] = { > >>> + [VIRT_PCIE] = 0, /* currently only one PCI controller */ > >>> +}; > >>> + > >>> static const char *valid_cpus[] = { > >>> "cortex-a15", > >>> "cortex-a53", > >>> @@ -980,6 +998,7 @@ static void create_pcie(const VirtMachineState *vms, qemu_irq *pic) > >>> hwaddr base_ecam = vms->memmap[VIRT_PCIE_ECAM].base; > >>> hwaddr size_ecam = vms->memmap[VIRT_PCIE_ECAM].size; > >>> hwaddr base = base_mmio; > >>> + uint32_t stream_id = vms->streamidmap[VIRT_PCIE] * STREAM_ID_RANGE_SIZE; > >> msi-base? > >> STREAM_ID_RANGE_SIZE ~ MSI_MAP_LENGTH? > >>> int nr_pcie_buses = size_ecam / PCIE_MMCFG_SIZE_MIN; > >>> int irq = vms->irqmap[VIRT_PCIE]; > >>> MemoryRegion *mmio_alias; > >>> @@ -992,6 +1011,7 @@ static void create_pcie(const VirtMachineState *vms, qemu_irq *pic) > >>> PCIHostState *pci; > >>> > >>> dev = qdev_create(NULL, TYPE_GPEX_HOST); > >>> + qdev_prop_set_uint32(dev, "stream-id-base", stream_id); > >>> qdev_init_nofail(dev); > >>> > >>> /* Map only the first size_ecam bytes of ECAM space */ > >>> @@ -1056,6 +1076,11 @@ static void create_pcie(const VirtMachineState *vms, qemu_irq *pic) > >>> if (vms->msi_phandle) { > >>> qemu_fdt_setprop_cells(vms->fdt, nodename, "msi-parent", > >>> vms->msi_phandle); > >>> + qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "msi-map", > >>> + 1, 0, > >>> + 1, vms->msi_phandle, > >>> + 1, stream_id, > >>> + 1, STREAM_ID_RANGE_SIZE); > >>> } > >>> > >>> qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg", > >>> @@ -1609,6 +1634,7 @@ static void virt_2_9_instance_init(Object *obj) > >>> > >>> vms->memmap = a15memmap; > >>> vms->irqmap = a15irqmap; > >>> + vms->streamidmap = streamidmap; > >>> } > >>> > >>> static void virt_machine_2_9_options(MachineClass *mc) > >>> diff --git a/hw/pci-host/gpex.c b/hw/pci-host/gpex.c > >>> index 66055ee..de72408 100644 > >>> --- a/hw/pci-host/gpex.c > >>> +++ b/hw/pci-host/gpex.c > >>> @@ -43,6 +43,11 @@ static void gpex_set_irq(void *opaque, int irq_num, int level) > >>> qemu_set_irq(s->irq[irq_num], level); > >>> } > >>> > >>> +static Property gpex_props[] = { > >>> + DEFINE_PROP_UINT32("stream-id-base", GPEXHost, stream_id_base, 0), > >> msi_base_base > >>> + DEFINE_PROP_END_OF_LIST(), > >>> +}; > >>> + > >>> static void gpex_host_realize(DeviceState *dev, Error **errp) > >>> { > >>> PCIHostState *pci = PCI_HOST_BRIDGE(dev); > >>> @@ -83,6 +88,7 @@ static void gpex_host_class_init(ObjectClass *klass, void *data) > >>> > >>> hc->root_bus_path = gpex_host_root_bus_path; > >>> dc->realize = gpex_host_realize; > >>> + dc->props = gpex_props; > >>> set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories); > >>> dc->fw_name = "pci"; > >>> } > >>> diff --git a/hw/pci/msi.c b/hw/pci/msi.c > >>> index 7925851..b60a410 100644 > >>> --- a/hw/pci/msi.c > >>> +++ b/hw/pci/msi.c > >>> @@ -336,7 +336,7 @@ void msi_send_message(PCIDevice *dev, MSIMessage msg) > >>> { > >>> MemTxAttrs attrs = {}; > >>> > >>> - attrs.stream_id = pci_requester_id(dev); > >>> + attrs.stream_id = pci_stream_id(dev); > >>> address_space_stl_le(&dev->bus_master_as, msg.address, msg.data, > >>> attrs, NULL); > >>> } > >>> diff --git a/hw/pci/pci.c b/hw/pci/pci.c > >>> index 259483b..92e9a2b 100644 > >>> --- a/hw/pci/pci.c > >>> +++ b/hw/pci/pci.c > >>> @@ -951,6 +951,30 @@ uint16_t pci_requester_id(PCIDevice *dev) > >>> return pci_req_id_cache_extract(&dev->requester_id_cache); > >>> } > >>> > >>> +static uint32_t pci_get_stream_id_base(PCIDevice *dev) > >>> +{ > >>> + PCIBus *rootbus = pci_device_root_bus(dev); > >>> + PCIHostState *host_bridge = PCI_HOST_BRIDGE(rootbus->qbus.parent); > >>> + Error *err = NULL; > >>> + int64_t stream_id; > >>> + > >>> + stream_id = object_property_get_int(OBJECT(host_bridge), "stream-id-base", > >>> + &err); > >>> + if (stream_id < 0) { > >>> + stream_id = 0; > >>> + } > >>> + > >>> + return stream_id; > >>> +} > >>> + > >>> +uint32_t pci_stream_id(PCIDevice *dev) > >>> +{ > >>> + /* Stream ID = RequesterID[15:0] + stream_id_base. stream_id_base may > >>> + * be 0 for devices that are not using any translation between requester_id > >>> + * and stream_id */ > >>> + return (uint16_t)pci_requester_id(dev) + dev->stream_id_base; > >>> +} > >> I think you should split the changes in virt from pci/gpex generic changes. > >> > >>> + > >>> /* -1 for devfn means auto assign */ > >>> static PCIDevice *do_pci_register_device(PCIDevice *pci_dev, PCIBus *bus, > >>> const char *name, int devfn, > >>> @@ -1000,6 +1024,7 @@ static PCIDevice *do_pci_register_device(PCIDevice *pci_dev, PCIBus *bus, > >>> > >>> pci_dev->devfn = devfn; > >>> pci_dev->requester_id_cache = pci_req_id_cache_get(pci_dev); > >>> + pci_dev->stream_id_base = pci_get_stream_id_base(pci_dev); > >> looks strange to me to store the rid base in the end point as this is > >> rather a property of the PCI complex. I acknowledge this is much more > > I agree. > > The reason I have changed was to avoid traversing the entire hierarchy > each time the ID is needed (for example each time when a MSI is sent). > > > I think that what we need is to add support for allowing PCI RCs > > to transform requesterIDs in transactions attributes according to the > > implementation specifics. > > Do you mean that you need more than a linear offset between requesterID > and whatever other ID? Yes. This is my understanding for the ARM platforms I'm familiar with: Since AXI busses don't have a defined way to carry Master IDs, these are typically carried on the AXI user signals. I'll just refer to these signals as AXI Master IDs. 1. An endpoint issues an MSI (or any) transaction on the PCI bus. In QEMU, these trasactions carry the requester ID in their attributes. 2. The transaction hits the PCI "host" bridge to the SoC internal interconnect (typically AXI). This bridge needs to forward the PCI transaction onto the AXI bus. Including mapping the PCI RequesterID into an AXI MasterID. 3. The AXI transaction hits the IOMMU and the MasterID is mapped into a streamID to identify the origin of the transaction and apply address translation accordingly. If the SMMU allows the transaction to pass, the stream ID is mapped back into the transactions MasterID. 4. The AXI transaction continues down the interconnect and hits the MSI doorbell and the MasterID is mapped into a DeviceID to identify the origin of the MSI and apply possible interrupt translation. Adding streamID fields to a PCI endpoint doesn't make any sense to me. The requester ID is already there and is IMO enough. StreamIDs are a concept of ARM System MMUs, not of PCI endpoints. When modelling #2, hardcoding a specific linear mapping between PCI requester IDs and AXI Master IDs may work for one platform but it won't work for all platforms. There is no one mapping for all. It can even be run-time programmable in the bridge. IIRC, the SMMUv3 docs have a section that suggest how these ReqID to AXI Master ID mappings can be done. > > The way we did it when modelling the ZynqMP is by adding support for > > transaction attribute translation in QEMU's IOMMU interface. > > In our PCI RC, we have an IOMMU covering the entire AS that PCI devs DMA into. > > This IOMMU doesn't do address-translation, only RequesterID -> StreamID > > transforms according to how the ZynqMP PCI RC derives StreamIDs from RequesterIDs. > > Are there any patches for this support in order for me to better understand? It's currently on the Xilinx QEMU fork on GitHub. https://github.com/Xilinx/qemu/blob/master/hw/pci-host/xlnx-nwl-pcie-main.c In the current ZynqMP, all RequesterIDs map to a single MasterID (it's a HW limitation). In future versions of the HW, another mapping will be used. I can't share code for the latter yet though.... Best regards, Edgar > > Thanks, > > Diana > > > > This is useful not only to model PCI RequesterID to AXI Master ID mappings but > > also for modelling things like the ARM TZC (or the Xilinx ZynqMP XMPU/XPPUs). > > > > Cheers, > > Edgar > > > > > >> simple than reworking pci_requester_id() though. > >>> > >>> memory_region_init(&pci_dev->bus_master_container_region, OBJECT(pci_dev), > >>> "bus master container", UINT64_MAX); > >>> diff --git a/include/hw/arm/virt.h b/include/hw/arm/virt.h > >>> index 33b0ff3..94c007a 100644 > >>> --- a/include/hw/arm/virt.h > >>> +++ b/include/hw/arm/virt.h > >>> @@ -99,6 +99,7 @@ typedef struct { > >>> struct arm_boot_info bootinfo; > >>> const MemMapEntry *memmap; > >>> const int *irqmap; > >>> + const uint32_t *streamidmap; > >>> int smp_cpus; > >>> void *fdt; > >>> int fdt_size; > >>> diff --git a/include/hw/pci-host/gpex.h b/include/hw/pci-host/gpex.h > >>> index 68c9348..47df01a 100644 > >>> --- a/include/hw/pci-host/gpex.h > >>> +++ b/include/hw/pci-host/gpex.h > >>> @@ -48,6 +48,8 @@ typedef struct GPEXHost { > >>> > >>> GPEXRootState gpex_root; > >>> > >>> + uint32_t stream_id_base; > >>> + > >>> MemoryRegion io_ioport; > >>> MemoryRegion io_mmio; > >>> qemu_irq irq[GPEX_NUM_IRQS]; > >>> diff --git a/include/hw/pci/pci.h b/include/hw/pci/pci.h > >>> index a37a2d5..e6e9334 100644 > >>> --- a/include/hw/pci/pci.h > >>> +++ b/include/hw/pci/pci.h > >>> @@ -283,6 +283,12 @@ struct PCIDevice { > >>> * MSI). For conventional PCI root complex, this field is > >>> * meaningless. */ > >>> PCIReqIDCache requester_id_cache; > >>> + /* Some platforms need a unique ID for IOMMU source identification > >>> + * or MSI source identification. QEMU implements a simple scheme: > >>> + * stream_id = stream_id_base + requester_id. The stream_id_base will > >>> + * ensure that all the devices in the system have different stream ID > >>> + * domains */ > >>> + uint32_t stream_id_base; > >> get rid of IOMMU terminology? > >> > >> Note that when adding other sub-systems you will need to address the > >> ACPI side as the IORT table built by hw/arm/virt-acpi-build.c currently > >> defines an RID mapping for the single root complex. > >> > >> Thanks > >> > >> Eric > >>> char name[64]; > >>> PCIIORegion io_regions[PCI_NUM_REGIONS]; > >>> AddressSpace bus_master_as; > >>> @@ -737,6 +743,8 @@ static inline uint16_t pci_get_bdf(PCIDevice *dev) > >>> > >>> uint16_t pci_requester_id(PCIDevice *dev); > >>> > >>> +uint32_t pci_stream_id(PCIDevice *dev); > >>> + > >>> /* DMA access functions */ > >>> static inline AddressSpace *pci_get_address_space(PCIDevice *dev) > >>> { > >>> diff --git a/kvm-all.c b/kvm-all.c > >>> index 90b8573..5a508c3 100644 > >>> --- a/kvm-all.c > >>> +++ b/kvm-all.c > >>> @@ -1280,7 +1280,7 @@ int kvm_irqchip_add_msi_route(KVMState *s, int vector, PCIDevice *dev) > >>> kroute.u.msi.data = le32_to_cpu(msg.data); > >>> if (kvm_msi_devid_required()) { > >>> kroute.flags = KVM_MSI_VALID_DEVID; > >>> - kroute.u.msi.devid = pci_requester_id(dev); > >>> + kroute.u.msi.devid = pci_stream_id(dev); > >>> } > >>> if (kvm_arch_fixup_msi_route(&kroute, msg.address, msg.data, dev)) { > >>> kvm_irqchip_release_virq(s, virq); > >>> @@ -1317,7 +1317,7 @@ int kvm_irqchip_update_msi_route(KVMState *s, int virq, MSIMessage msg, > >>> kroute.u.msi.data = le32_to_cpu(msg.data); > >>> if (kvm_msi_devid_required()) { > >>> kroute.flags = KVM_MSI_VALID_DEVID; > >>> - kroute.u.msi.devid = pci_requester_id(dev); > >>> + kroute.u.msi.devid = pci_stream_id(dev); > >>> } > >>> if (kvm_arch_fixup_msi_route(&kroute, msg.address, msg.data, dev)) { > >>> return -EINVAL; > >>> > From MAILER-DAEMON Fri Aug 11 12:50:30 2017 Received: from list by lists.gnu.org with archive (Exim 4.71) id 1dgD8o-0006Rz-KR for mharc-qemu-arm@gnu.org; Fri, 11 Aug 2017 12:50:30 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:50925) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dgD8k-0006Pz-Rw for qemu-arm@nongnu.org; Fri, 11 Aug 2017 12:50:28 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dgD8j-0006KS-Rz for qemu-arm@nongnu.org; Fri, 11 Aug 2017 12:50:26 -0400 Received: from mail-wm0-x22a.google.com ([2a00:1450:400c:c09::22a]:36250) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1dgD8j-0006Jh-MV for qemu-arm@nongnu.org; Fri, 11 Aug 2017 12:50:25 -0400 Received: by mail-wm0-x22a.google.com with SMTP id t201so45905584wmt.1 for ; Fri, 11 Aug 2017 09:50:23 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:in-reply-to:references:from:date:message-id:subject:to :cc; bh=bVUQkubm3snmKPVByxDVR40WM0YvZLkAT1odEZIw0jg=; b=V4ahf/0fYNOyUUIXo+Ewf1IwL6JfGBBNSZVvfuaciemJCuUOgr5LGFMHPwIjNeeXgp 6VK2HEntSWoFLSh2YnW90MRMz+Hss3XxXxw5Vj1G1CRIuiX/cZb/MsADGEMqWqonQ20J 00sj0YAS3hrHUuMBaw8+aMpyCRP1pf4DsAloA= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:in-reply-to:references:from:date :message-id:subject:to:cc; bh=bVUQkubm3snmKPVByxDVR40WM0YvZLkAT1odEZIw0jg=; b=s6XuMX8zRT6M4dN6NNpw0d59eQRXEkyeUAKM0ujQ9Q+SuKwR2BeRNp/8z0ozw2lJPP WcQG1PLZScJW8IMQU8i3/G3yljK7Y8ZdNnOoxeEBNTq23J1pkuuefnLdlgu3yKZNXhh3 mt7K3eugdc8YVWi1XAbPokbPbD00agK0/5y18O6MssOhVNfAMN5rLz8IAMFA00CmW1jY 2vk1LgkCzPfCHtyqNAJfP+yb7Ms296tzmyurkfwEPQ5txxmiCKD0cRFkNYY8dgHnh8hP G5H/OUa2KpCrcUYpQUo/gB0gC7iSvJeZ/zBv5S+uMQaXT+RlJ9JMPQlHrWq4/NHkFEvm h4xw== X-Gm-Message-State: AHYfb5g4Iz8/TKzppjHUmXaIg/KIFOdhvk9BQHIr7kEL/crfIZL0uy5r qtnjTwDH0wN//mcdVvv0jRQqjG4TaIhW X-Received: by 10.28.8.140 with SMTP id 134mr1605596wmi.108.1502470222855; Fri, 11 Aug 2017 09:50:22 -0700 (PDT) MIME-Version: 1.0 Received: by 10.223.134.54 with HTTP; Fri, 11 Aug 2017 09:50:02 -0700 (PDT) In-Reply-To: References: <1495537965-4187-1-git-send-email-diana.craciun@nxp.com> <1495537965-4187-2-git-send-email-diana.craciun@nxp.com> <17ae81be-a86e-d0ab-de93-046846e0b7d2@redhat.com> From: Peter Maydell Date: Fri, 11 Aug 2017 17:50:02 +0100 Message-ID: To: Diana Madalina Craciun Cc: Auger Eric , "qemu-devel@nongnu.org" , "mst@redhat.com" , Mike Caraman , "qemu-arm@nongnu.org" , "marcel@redhat.com" , Bharat Bhushan , "christoffer.dall@linaro.org" , Laurentiu Tudor Content-Type: text/plain; charset="UTF-8" X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:400c:c09::22a Subject: Re: [Qemu-arm] [Qemu-devel] [PATCH v2 1/2] Increased the size of requester_id field from MemTxAttrs X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 11 Aug 2017 16:50:28 -0000 On 11 August 2017 at 15:32, Diana Madalina Craciun wrote: > On 07/26/2017 03:23 PM, Auger Eric wrote: >> With respect to the renaming, stream_id really is ARM specific and >> corresponds to the ID space before the SMMU while you mostly address >> device id problematics here (ie. space id input to the interrupt >> controller). Maybe a more generic terminology such as originator id >> could be used or source id (I think this is Intel terminology though). > > I agree, originator id sounds good and so far it doesn't seem to overlap > to other specific terminology. That reminds me that the other thing I'd like to use this field for is the "identify which CPU of a cluster made this memory transaction" thing (which you can get on ARM AXI etc buses). So that's another thing that would need to have some part of the ID space... thanks -- PMM From MAILER-DAEMON Fri Aug 11 14:22:53 2017 Received: from list by lists.gnu.org with archive (Exim 4.71) id 1dgEaD-000064-SV for mharc-qemu-arm@gnu.org; Fri, 11 Aug 2017 14:22:53 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:45093) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dgEaA-0008WT-RI for qemu-arm@nongnu.org; Fri, 11 Aug 2017 14:22:51 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dgEa7-0007OD-My for qemu-arm@nongnu.org; Fri, 11 Aug 2017 14:22:50 -0400 Received: from mail-co1nam03on0055.outbound.protection.outlook.com ([104.47.40.55]:45251 helo=NAM03-CO1-obe.outbound.protection.outlook.com) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1dgEa7-0007NA-95; Fri, 11 Aug 2017 14:22:47 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=xilinx.onmicrosoft.com; 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Ip=[149.199.60.100]; Helo=[xsj-pvapsmtpgw02] X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BN6PR02MB2242 X-detected-operating-system: by eggs.gnu.org: Windows 7 or 8 [fuzzy] X-Received-From: 104.47.40.55 Subject: [Qemu-arm] [RFC v1 0/3] Fixup exclusive store logic X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 11 Aug 2017 18:22:52 -0000 I found some issues with the way exclusive store was working. This patch series seems to fix the test cases that were failing for me and also seem to follow what the ARM ARM says. The first patch is just a simple adjustment. The second patch is just preparing for the third patch. The third patch is where the big change is. It includes details of the limited testing that I have done. Alistair Francis (3): target/arm: Update the memops for exclusive load tcg/tcg-op: Expose the tcg_gen_ext_i* functions target/arm: Correct exclusive store return value target/arm/translate-a64.c | 24 +++++++++++++----------- tcg/tcg-op.c | 4 ++-- tcg/tcg-op.h | 2 ++ 3 files changed, 17 insertions(+), 13 deletions(-) -- 2.11.0 From MAILER-DAEMON Fri Aug 11 14:23:03 2017 Received: from list by lists.gnu.org with archive (Exim 4.71) id 1dgEaN-0000CE-10 for mharc-qemu-arm@gnu.org; Fri, 11 Aug 2017 14:23:03 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:45133) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dgEaJ-0000Aq-T1 for qemu-arm@nongnu.org; Fri, 11 Aug 2017 14:23:01 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dgEaG-0007R7-Mj for qemu-arm@nongnu.org; Fri, 11 Aug 2017 14:22:59 -0400 Received: from mail-cys01nam02on0053.outbound.protection.outlook.com ([104.47.37.53]:12640 helo=NAM02-CY1-obe.outbound.protection.outlook.com) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1dgEaG-0007Qj-Ce; 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Ip=[149.199.60.83]; Helo=[xsj-pvapsmtpgw01] X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BN6PR02MB2465 X-detected-operating-system: by eggs.gnu.org: Windows 7 or 8 [fuzzy] X-Received-From: 104.47.37.53 Subject: [Qemu-arm] [RFC v1 1/3] target/arm: Update the memops for exclusive load X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 11 Aug 2017 18:23:02 -0000 Acording to the ARM ARM exclusive loads require the same allignment as exclusive stores. Let's update the memops used for the load to match that of the store. This adds the alignment requirement to the memops. Signed-off-by: Alistair Francis --- target/arm/translate-a64.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 58ed4c6d05..245175e2f1 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -1854,7 +1854,7 @@ static void gen_load_exclusive(DisasContext *s, int rt, int rt2, TCGv_i64 addr, int size, bool is_pair) { TCGv_i64 tmp = tcg_temp_new_i64(); - TCGMemOp memop = s->be_data + size; + TCGMemOp memop = size | MO_ALIGN | s->be_data; g_assert(size <= 3); tcg_gen_qemu_ld_i64(tmp, addr, get_mem_index(s), memop); -- 2.11.0 From MAILER-DAEMON Fri Aug 11 14:23:04 2017 Received: from list by lists.gnu.org with archive (Exim 4.71) id 1dgEaO-0000DR-6X for mharc-qemu-arm@gnu.org; Fri, 11 Aug 2017 14:23:04 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:45139) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dgEaK-0000As-Ie for qemu-arm@nongnu.org; Fri, 11 Aug 2017 14:23:01 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dgEaH-0007RP-Ew for qemu-arm@nongnu.org; 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Ip=[149.199.60.83]; Helo=[xsj-pvapsmtpgw01] X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM5PR02MB2251 X-detected-operating-system: by eggs.gnu.org: Windows 7 or 8 [fuzzy] X-Received-From: 104.47.34.40 Subject: [Qemu-arm] [RFC v1 2/3] tcg/tcg-op: Expose the tcg_gen_ext_i* functions X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 11 Aug 2017 18:23:02 -0000 Expose the tcg_gen_ext_i32() and tcg_gen_ext_i64() functions as we are going to use them later. Signed-off-by: Alistair Francis --- tcg/tcg-op.c | 4 ++-- tcg/tcg-op.h | 2 ++ 2 files changed, 4 insertions(+), 2 deletions(-) diff --git a/tcg/tcg-op.c b/tcg/tcg-op.c index 87f673ef49..d25e3003ef 100644 --- a/tcg/tcg-op.c +++ b/tcg/tcg-op.c @@ -2709,7 +2709,7 @@ void tcg_gen_qemu_st_i64(TCGv_i64 val, TCGv addr, TCGArg idx, TCGMemOp memop) gen_ldst_i64(INDEX_op_qemu_st_i64, val, addr, memop, idx); } -static void tcg_gen_ext_i32(TCGv_i32 ret, TCGv_i32 val, TCGMemOp opc) +void tcg_gen_ext_i32(TCGv_i32 ret, TCGv_i32 val, TCGMemOp opc) { switch (opc & MO_SSIZE) { case MO_SB: @@ -2730,7 +2730,7 @@ static void tcg_gen_ext_i32(TCGv_i32 ret, TCGv_i32 val, TCGMemOp opc) } } -static void tcg_gen_ext_i64(TCGv_i64 ret, TCGv_i64 val, TCGMemOp opc) +void tcg_gen_ext_i64(TCGv_i64 ret, TCGv_i64 val, TCGMemOp opc) { switch (opc & MO_SSIZE) { case MO_SB: diff --git a/tcg/tcg-op.h b/tcg/tcg-op.h index 5d3278f243..8c45b79a92 100644 --- a/tcg/tcg-op.h +++ b/tcg/tcg-op.h @@ -835,6 +835,8 @@ void tcg_gen_qemu_ld_i32(TCGv_i32, TCGv, TCGArg, TCGMemOp); void tcg_gen_qemu_st_i32(TCGv_i32, TCGv, TCGArg, TCGMemOp); void tcg_gen_qemu_ld_i64(TCGv_i64, TCGv, TCGArg, TCGMemOp); void tcg_gen_qemu_st_i64(TCGv_i64, TCGv, TCGArg, TCGMemOp); +void tcg_gen_ext_i32(TCGv_i32 ret, TCGv_i32 val, TCGMemOp opc); +void tcg_gen_ext_i64(TCGv_i64 ret, TCGv_i64 val, TCGMemOp opc); static inline void tcg_gen_qemu_ld8u(TCGv ret, TCGv addr, int mem_index) { -- 2.11.0 From MAILER-DAEMON Fri Aug 11 14:23:04 2017 Received: from list by lists.gnu.org with archive (Exim 4.71) id 1dgEaO-0000Dj-C1 for mharc-qemu-arm@gnu.org; Fri, 11 Aug 2017 14:23:04 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:45143) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dgEaK-0000Au-R7 for qemu-arm@nongnu.org; Fri, 11 Aug 2017 14:23:02 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dgEaH-0007Rg-Mc for qemu-arm@nongnu.org; Fri, 11 Aug 2017 14:23:00 -0400 Received: from mail-co1nam03on0080.outbound.protection.outlook.com ([104.47.40.80]:36672 helo=NAM03-CO1-obe.outbound.protection.outlook.com) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1dgEaH-0007Qx-C1; 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Ip=[149.199.60.100]; Helo=[xsj-pvapsmtpgw02] X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM5PR02MB2250 X-detected-operating-system: by eggs.gnu.org: Windows 7 or 8 [fuzzy] X-Received-From: 104.47.40.80 Subject: [Qemu-arm] [RFC v1 3/3] target/arm: Correct exclusive store return value X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 11 Aug 2017 18:23:02 -0000 The exclusive store operation should return 0 if the operation updates memory and 1 if it doesn't. This means that storing tmp in the rd register is incorrect. This patch updates the succesful opertion to store 0 into the rd register instead of tmp. It also adds a branch to fail if the memory isn't updated. In order to add a branch for the pair case when size equals 2 we first need to apply the same memory operation on the exclusive value in order for the comparison to work. There is still no value checks added if we are doing a 64-bit store with pairs. Signed-off-by: Alistair Francis --- This was caught with an internal fuzzy tester. These patches fix the Xilinx 2.10-rc2 tree. I tested with the fuzzy tester (single CPU) and Linux boot (4 CPUs) on the Xilinx tree. I don't have a good test case to run on mainline at the moment, but I'm working on getting one. Also linux-user is fully untested. All tests were with MTTCG enabled. target/arm/translate-a64.c | 22 ++++++++++++---------- 1 file changed, 12 insertions(+), 10 deletions(-) diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 245175e2f1..ea7c61bc6f 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -1894,10 +1894,11 @@ static void gen_store_exclusive(DisasContext *s, int rd, int rt, int rt2, * } * env->exclusive_addr = -1; */ + TCGMemOp memop = size | MO_ALIGN | s->be_data; TCGLabel *fail_label = gen_new_label(); TCGLabel *done_label = gen_new_label(); TCGv_i64 addr = tcg_temp_local_new_i64(); - TCGv_i64 tmp; + TCGv_i64 tmp, val; /* Copy input into a local temp so it is not trashed when the * basic block ends at the branch insn. @@ -1907,15 +1908,15 @@ static void gen_store_exclusive(DisasContext *s, int rd, int rt, int rt2, tmp = tcg_temp_new_i64(); if (is_pair) { + val = tcg_temp_new_i64(); if (size == 2) { - TCGv_i64 val = tcg_temp_new_i64(); tcg_gen_concat32_i64(tmp, cpu_reg(s, rt), cpu_reg(s, rt2)); tcg_gen_concat32_i64(val, cpu_exclusive_val, cpu_exclusive_high); tcg_gen_atomic_cmpxchg_i64(tmp, addr, val, tmp, get_mem_index(s), - size | MO_ALIGN | s->be_data); - tcg_gen_setcond_i64(TCG_COND_NE, tmp, tmp, val); - tcg_temp_free_i64(val); + memop); + tcg_gen_ext_i64(val, val, memop); + tcg_gen_brcond_i64(TCG_COND_NE, tmp, val, fail_label); } else if (s->be_data == MO_LE) { gen_helper_paired_cmpxchg64_le(tmp, cpu_env, addr, cpu_reg(s, rt), cpu_reg(s, rt2)); @@ -1924,22 +1925,23 @@ static void gen_store_exclusive(DisasContext *s, int rd, int rt, int rt2, cpu_reg(s, rt2)); } } else { - TCGv_i64 val = cpu_reg(s, rt); + val = cpu_reg(s, rt); tcg_gen_atomic_cmpxchg_i64(tmp, addr, cpu_exclusive_val, val, get_mem_index(s), - size | MO_ALIGN | s->be_data); - tcg_gen_setcond_i64(TCG_COND_NE, tmp, tmp, cpu_exclusive_val); + memop); + tcg_gen_brcond_i64(TCG_COND_NE, tmp, cpu_exclusive_val, fail_label); } tcg_temp_free_i64(addr); - tcg_gen_mov_i64(cpu_reg(s, rd), tmp); - tcg_temp_free_i64(tmp); + tcg_gen_movi_i64(cpu_reg(s, rd), 0); tcg_gen_br(done_label); gen_set_label(fail_label); tcg_gen_movi_i64(cpu_reg(s, rd), 1); gen_set_label(done_label); + tcg_temp_free_i64(tmp); + tcg_temp_free_i64(val); tcg_gen_movi_i64(cpu_exclusive_addr, -1); } -- 2.11.0 From MAILER-DAEMON Fri Aug 11 15:46:35 2017 Received: from list by lists.gnu.org with archive (Exim 4.71) id 1dgFtD-00052i-HI for mharc-qemu-arm@gnu.org; Fri, 11 Aug 2017 15:46:35 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:34959) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dgFtB-00051z-MM for qemu-arm@nongnu.org; Fri, 11 Aug 2017 15:46:34 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dgFt7-0004jw-P2 for qemu-arm@nongnu.org; Fri, 11 Aug 2017 15:46:33 -0400 Received: from mail-pg0-x233.google.com ([2607:f8b0:400e:c05::233]:35887) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1dgFt7-0004jJ-E8 for qemu-arm@nongnu.org; Fri, 11 Aug 2017 15:46:29 -0400 Received: by mail-pg0-x233.google.com with SMTP id v77so19148398pgb.3 for ; Fri, 11 Aug 2017 12:46:29 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=subject:to:cc:references:from:message-id:date:user-agent :mime-version:in-reply-to:content-language:content-transfer-encoding; bh=BvANXtcJkApSraEtTi3qeWL0bnCZRoD0WaYP2GNhkw4=; b=L2D543jE1QAYLN92NknTNrtUmd7tPOlK4SBc67vR3Ww6mLdhlJg4FhDSotKQr/+PXD 5+id0Wa59Xyg9LH4h71psbHsE1fYEecwwikCUzfzm10tmHlppVugIWRpRXTnykvCUScF mMQKpKluj1Elxd/+ra2sUuVrcdAJ4OvHKJD5w= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:subject:to:cc:references:from:message-id:date :user-agent:mime-version:in-reply-to:content-language :content-transfer-encoding; bh=BvANXtcJkApSraEtTi3qeWL0bnCZRoD0WaYP2GNhkw4=; b=SfLBX9FwlYf0YyL2Kei+wc/9Om+OfWhHqnbS4hXsHC3DmIIWCMbp4zU/pzyEur3CTr GjBDWe6XHr2lbzk5I1SdDEYkgRzOJk8941KriAu1C9vxNiNl/5Yn8DWHt813WpFWlEuU 9MRIY909a0/9SQSWuDUsKITc5tK1gM8zLcAHQlU1enY3SpumIOAivUzheSqzrbRcDA9k PwnfNs2yAd5ZNI0QkF9mjgC+beAERI0TPSSc4JX236NARU7wqxlNpzjvrra++qyuQ/g+ 43rqf69lM9Lzchkdr/EUTZivi5wxmM1CwYZe0+UvsL/G5ORcLg2oBhtYRQ5vkZM5XpUU JShQ== X-Gm-Message-State: AHYfb5jgvLwtF6DDslwGDuJBDU8lovPo8CxhQQFT0Q8CFBXWDlG+kgT6 zBy9ZDtV+nl/g344 X-Received: by 10.99.95.200 with SMTP id t191mr15997426pgb.237.1502480788257; Fri, 11 Aug 2017 12:46:28 -0700 (PDT) Received: from bigtime.twiddle.net (50-233-235-3-static.hfc.comcastbusiness.net. [50.233.235.3]) by smtp.gmail.com with ESMTPSA id q3sm3992672pfl.89.2017.08.11.12.46.26 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 11 Aug 2017 12:46:27 -0700 (PDT) To: Alistair Francis , qemu-devel@nongnu.org, peter.maydell@linaro.org Cc: edgar.iglesias@xilinx.com, alistair23@gmail.com, qemu-arm@nongnu.org, edgar.iglesias@gmail.com References: <2fbcf76e4ff63d8527edd3662342948276e2cd37.1502474835.git.alistair.francis@xilinx.com> From: Richard Henderson Message-ID: Date: Fri, 11 Aug 2017 12:46:24 -0700 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.2.1 MIME-Version: 1.0 In-Reply-To: <2fbcf76e4ff63d8527edd3662342948276e2cd37.1502474835.git.alistair.francis@xilinx.com> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 7bit X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::233 Subject: Re: [Qemu-arm] [Qemu-devel] [RFC v1 3/3] target/arm: Correct exclusive store return value X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 11 Aug 2017 19:46:34 -0000 On 08/11/2017 11:19 AM, Alistair Francis wrote: > The exclusive store operation should return 0 if the operation updates > memory and 1 if it doesn't. This means that storing tmp in the rd > register is incorrect. I'm confused as to what you believe is wrong. > tcg_gen_atomic_cmpxchg_i64(tmp, addr, val, tmp, > get_mem_index(s), > - size | MO_ALIGN | s->be_data); > - tcg_gen_setcond_i64(TCG_COND_NE, tmp, tmp, val); Yes, we load the result of the cmpxchg into tmp, but then we immediately overwrite tmp with 0/1 depending on whether the operation succeeded. > > This patch updates the succesful opertion to store 0 into the rd > register instead of tmp. It also adds a branch to fail if the memory > isn't updated. Since we use setcond, a branch is not required. > + tcg_gen_ext_i64(val, val, memop); What is this addition intended to accomplish? Because of the position within the code, you know that memop contains MO_64, so that this is a no-op. r~ From MAILER-DAEMON Fri Aug 11 15:59:54 2017 Received: from list by lists.gnu.org with archive (Exim 4.71) id 1dgG65-0002bH-VJ for mharc-qemu-arm@gnu.org; Fri, 11 Aug 2017 15:59:53 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:38249) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dgG63-0002Zf-HL for qemu-arm@nongnu.org; Fri, 11 Aug 2017 15:59:52 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dgG60-0002Zm-Bx for qemu-arm@nongnu.org; Fri, 11 Aug 2017 15:59:51 -0400 Received: from mail-pf0-x22c.google.com ([2607:f8b0:400e:c00::22c]:34744) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1dgG60-0002ZH-4R for qemu-arm@nongnu.org; Fri, 11 Aug 2017 15:59:48 -0400 Received: by mail-pf0-x22c.google.com with SMTP id o86so19671181pfj.1 for ; Fri, 11 Aug 2017 12:59:47 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=subject:to:cc:references:from:message-id:date:user-agent :mime-version:in-reply-to:content-language:content-transfer-encoding; bh=On6t3Kng1PIIRgcpqVi3bPboeiDdxt4pKj+VE5Qe7ug=; b=EDU0aMqAKWZeEZxbIzhevc2IxMIj4jeuj4qda6PsLz/260SzKzAUlb5jktgB6+4Duv NU0lFpfawENdYCDl5PkSAsxIwAXc5UBazo0jXuqRqNrW+3DC9pD/eWaZo7IVhekYemxh 5dxBkL2+LCOP7PhCB+6EAXW1GmgyYlQNXIT/A= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:subject:to:cc:references:from:message-id:date :user-agent:mime-version:in-reply-to:content-language :content-transfer-encoding; bh=On6t3Kng1PIIRgcpqVi3bPboeiDdxt4pKj+VE5Qe7ug=; b=Yetos7Fi041GsS9zJqK+jSiPcX1ODDtc5URWVd81kwi2K02KVTKds4vmo6Y3v2Im7t YiHGr0Ic0o8r4QI115hRFqzKG9VudAckVrBDBk9zMv6/w1JeDqSO1wS+kqkp6+8auhPW 8dM+LPX9gg+SXIOgJapV/Yjcqvy0KW6QusM8gtvW0fK6r52iD8ZEYIQ+0H3sbv46gkXD 8trn7dtmsZFijhnuKuMUrdJiIXIJBJsGM6v1S3eGMFX7rO+LA2779grwpWfcQC4tYKjg hcBqtStoTUesGe2IgeAteOu66NDRP8j7lxCsgX1rF/kXucXDqQ51+6qQixuOBnANSgKr aJOw== X-Gm-Message-State: AHYfb5igWHL+izHb+/5v0t5g9AO3k5skW/wjf5UH28xbLYq5Bd4zqPeD H7rSaLGduJwRF6vE X-Received: by 10.98.193.5 with SMTP id i5mr17463121pfg.317.1502481586996; Fri, 11 Aug 2017 12:59:46 -0700 (PDT) Received: from bigtime.twiddle.net (50-233-235-3-static.hfc.comcastbusiness.net. [50.233.235.3]) by smtp.gmail.com with ESMTPSA id r82sm4552909pfe.0.2017.08.11.12.59.45 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 11 Aug 2017 12:59:46 -0700 (PDT) To: Alistair Francis , qemu-devel@nongnu.org, peter.maydell@linaro.org Cc: edgar.iglesias@xilinx.com, alistair23@gmail.com, qemu-arm@nongnu.org, edgar.iglesias@gmail.com References: <20b283f7eaf100783b291de3830dd226ec286b6a.1502474835.git.alistair.francis@xilinx.com> From: Richard Henderson Message-ID: <202d07a5-b1a5-cd37-2a31-de45dc0690da@linaro.org> Date: Fri, 11 Aug 2017 12:59:43 -0700 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.2.1 MIME-Version: 1.0 In-Reply-To: <20b283f7eaf100783b291de3830dd226ec286b6a.1502474835.git.alistair.francis@xilinx.com> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 7bit X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::22c Subject: Re: [Qemu-arm] [Qemu-devel] [RFC v1 1/3] target/arm: Update the memops for exclusive load X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 11 Aug 2017 19:59:52 -0000 On 08/11/2017 11:19 AM, Alistair Francis wrote: > Acording to the ARM ARM exclusive loads require the same allignment as > exclusive stores. Let's update the memops used for the load to match > that of the store. This adds the alignment requirement to the memops. > > Signed-off-by: Alistair Francis > --- > > target/arm/translate-a64.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) Reviewed-by: Richard Henderson r~ From MAILER-DAEMON Fri Aug 11 16:00:37 2017 Received: from list by lists.gnu.org with archive (Exim 4.71) id 1dgG6n-0003Eg-Fc for mharc-qemu-arm@gnu.org; Fri, 11 Aug 2017 16:00:37 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:38517) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dgG6l-0003DK-4e for qemu-arm@nongnu.org; Fri, 11 Aug 2017 16:00:36 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dgG6i-0002wH-1P for qemu-arm@nongnu.org; Fri, 11 Aug 2017 16:00:35 -0400 Received: from mail-pf0-x230.google.com ([2607:f8b0:400e:c00::230]:36469) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1dgG6h-0002vu-RO for qemu-arm@nongnu.org; Fri, 11 Aug 2017 16:00:31 -0400 Received: by mail-pf0-x230.google.com with SMTP id c28so19612208pfe.3 for ; Fri, 11 Aug 2017 13:00:31 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=subject:to:cc:references:from:message-id:date:user-agent :mime-version:in-reply-to:content-language:content-transfer-encoding; bh=72TKMmSqFRHZNaK3PxSAvbtyjQLVTh6p7/GDx78jpKs=; b=QXYW5sgo+54f0bVr17BMF++OLRhJPFJiMWlJDxm/9Lh6zF2bM86HHSN4rN8N6NNKB7 OKk8cnxaVabjtQvo8sqyIw2/4RAAa9upBf2DaIk8sVFBYMONaQwA6V8u3PNq2Iiv3qaT 04UJ/LeCAs8nKl0EmfGZsg1j2w6T/iy8NE6NQ= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:subject:to:cc:references:from:message-id:date :user-agent:mime-version:in-reply-to:content-language :content-transfer-encoding; bh=72TKMmSqFRHZNaK3PxSAvbtyjQLVTh6p7/GDx78jpKs=; b=P1SnC2WPAGToMPf18SMv2XePtM6ctBjBlNgLCgNmZTud5XSCHzk86ZzXR0pNEh+pg2 cfVVp7j1UbGiZBc0v5zHPLK1RKBybgbZL9H4FTR/4a8r/WgRZfeyKWQn1iDipaApTz6g 8h5pWvGADD6HREe7nBmmiGKkCr3/UvJZ40or9kKgqGAPenVRT3QmQmRuDJ/lCbJ1xebz +2DU0C/DX8JwjDN5O9H/BGePIccD0WMOBdAFS/ovjdA/ybNnOlE0/yROHygB4GyQNZsz UYJqpiPFQ/BzEmOvRILKu9mKhN/x054dNwmsrf5hsEqSSQ5kK2dGOUC5AEOLuBf89YkI ur3Q== X-Gm-Message-State: AHYfb5gPahTdeW0pK4iMOaAF0gDUNJf7DxIHj8GQ0g1C7JV/H5VL/y0i hVXvv7ZpxHD2TwnH X-Received: by 10.98.65.86 with SMTP id o83mr17385297pfa.117.1502481630733; Fri, 11 Aug 2017 13:00:30 -0700 (PDT) Received: from bigtime.twiddle.net (50-233-235-3-static.hfc.comcastbusiness.net. [50.233.235.3]) by smtp.gmail.com with ESMTPSA id t12sm4189881pfg.12.2017.08.11.13.00.29 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 11 Aug 2017 13:00:29 -0700 (PDT) To: Alistair Francis , qemu-devel@nongnu.org, peter.maydell@linaro.org Cc: edgar.iglesias@xilinx.com, alistair23@gmail.com, qemu-arm@nongnu.org, edgar.iglesias@gmail.com References: From: Richard Henderson Message-ID: <6e40aec2-10ed-589d-d380-a296402ae4bd@linaro.org> Date: Fri, 11 Aug 2017 13:00:27 -0700 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.2.1 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 7bit X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::230 Subject: Re: [Qemu-arm] [Qemu-devel] [RFC v1 2/3] tcg/tcg-op: Expose the tcg_gen_ext_i* functions X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 11 Aug 2017 20:00:36 -0000 On 08/11/2017 11:19 AM, Alistair Francis wrote: > Expose the tcg_gen_ext_i32() and tcg_gen_ext_i64() functions as we are > going to use them later. > > Signed-off-by: Alistair Francis > --- > > tcg/tcg-op.c | 4 ++-- > tcg/tcg-op.h | 2 ++ > 2 files changed, 4 insertions(+), 2 deletions(-) This is a good idea, since I'm certain we have several copies of this in several of the target translators. Reviewed-by: Richard Henderson r~ From MAILER-DAEMON Fri Aug 11 16:13:48 2017 Received: from list by lists.gnu.org with archive (Exim 4.71) id 1dgGJY-0001Ku-Rf for mharc-qemu-arm@gnu.org; Fri, 11 Aug 2017 16:13:48 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:41331) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dgGJW-0001Ix-9c for qemu-arm@nongnu.org; Fri, 11 Aug 2017 16:13:47 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dgGJV-0004Vm-5l for qemu-arm@nongnu.org; Fri, 11 Aug 2017 16:13:46 -0400 Received: from mail-wr0-x244.google.com ([2a00:1450:400c:c0c::244]:36552) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1dgGJS-0004Tl-E6; Fri, 11 Aug 2017 16:13:42 -0400 Received: by mail-wr0-x244.google.com with SMTP id y67so3185023wrb.3; Fri, 11 Aug 2017 13:13:40 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=mime-version:sender:in-reply-to:references:from:date:message-id :subject:to:cc; bh=bI7yK9Meax/zYzWNY6VGsJeKEo5k/e+KGHFY2N5UywE=; b=pHwun0UzZ7Gxs5iVbpZ8FdFEweoNPvl34bP8NKylUZTyd1Ku3AbRRYZ9zn97Upi1ks 4ao29ZZtPCN1vCRvE0dkbMKjkIJTJzVxbYtc3QeVMA+QNZxkZxwE0qoPYJex3hiNJd4R L0HjAFqu+5aAastAHClbaqbfaIiKs6y1sPQgUuwR/v7rz1zck7PcfvLg2cmgmfCe2fUM uDd+A3yC1kpUGwQ5L7aq2sy3pWQ3fQRqUgvVaJuMzsfNDqfs+3VuZyyC1JC46uH28e7H FTdRVfQuje4JkW0GSIS11rk1CHjqhPBn7C/2nxMgvjFNjjUwakOsP2T2oDlaSyogmBC2 IybQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:sender:in-reply-to:references:from :date:message-id:subject:to:cc; bh=bI7yK9Meax/zYzWNY6VGsJeKEo5k/e+KGHFY2N5UywE=; b=hhES+8aXIc4k3xQ0Zh7Pe0XxggM00R5+35hKiiQereSr180yDqA53BIcV6iy1+esel b1UKVFpPC1HlJ6sLWQeUo42X88B9UW0pXu3HNNcIKn8LGoaNxMZFw1jg8/ricUqUf55i GEfmABfd3IRRMHjuuAkpQIZpo4zWnRBMGzenR4sp1JoVq0yEz/LoU9jkbUAaVnKyyP+K zPxdBgecLCjDsMpmP9f145QZSfq7uqBchxBNXJlIE2vj2BpvT69GWa36RskqmB7Mn9d5 D7/FrN5O2qrtQf8IQ52YMWgystve0mviZOeyChuuBUkoz/BL3rNIhHqJuYj+WrcwzR2v QY0w== X-Gm-Message-State: AHYfb5jd0GmguC44LjYn+prlZ8Ugnnf3ofZiMKMM6RUGkeja4Enp7yts TflKZ5N9OfvLdAO5bb7k5bhMRXND/A== X-Received: by 10.223.166.7 with SMTP id k7mr12836844wrc.34.1502482419852; Fri, 11 Aug 2017 13:13:39 -0700 (PDT) MIME-Version: 1.0 Sender: alistair23@gmail.com Received: by 10.28.191.130 with HTTP; Fri, 11 Aug 2017 13:13:09 -0700 (PDT) In-Reply-To: References: <2fbcf76e4ff63d8527edd3662342948276e2cd37.1502474835.git.alistair.francis@xilinx.com> From: Alistair Francis Date: Fri, 11 Aug 2017 13:13:09 -0700 X-Google-Sender-Auth: 9IglbG0mx1btOooabCZ2qFZoP68 Message-ID: To: Richard Henderson Cc: Alistair Francis , "qemu-devel@nongnu.org Developers" , Peter Maydell , Edgar Iglesias , qemu-arm , Edgar Iglesias Content-Type: text/plain; charset="UTF-8" X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:400c:c0c::244 Subject: Re: [Qemu-arm] [Qemu-devel] [RFC v1 3/3] target/arm: Correct exclusive store return value X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 11 Aug 2017 20:13:48 -0000 On Fri, Aug 11, 2017 at 12:46 PM, Richard Henderson wrote: > On 08/11/2017 11:19 AM, Alistair Francis wrote: >> The exclusive store operation should return 0 if the operation updates >> memory and 1 if it doesn't. This means that storing tmp in the rd >> register is incorrect. > > I'm confused as to what you believe is wrong. > >> tcg_gen_atomic_cmpxchg_i64(tmp, addr, val, tmp, >> get_mem_index(s), >> - size | MO_ALIGN | s->be_data); >> - tcg_gen_setcond_i64(TCG_COND_NE, tmp, tmp, val); > > Yes, we load the result of the cmpxchg into tmp, but then we immediately > overwrite tmp with 0/1 depending on whether the operation succeeded. Hmmm... When I looked at the values in tmp I was seeing non 0/1 values in there. > >> >> This patch updates the succesful opertion to store 0 into the rd >> register instead of tmp. It also adds a branch to fail if the memory >> isn't updated. > > Since we use setcond, a branch is not required. > >> + tcg_gen_ext_i64(val, val, memop); > > What is this addition intended to accomplish? Because of the position within > the code, you know that memop contains MO_64, so that this is a no-op. This is when size == 2 so it's a 32bit operation so memop contains MO_32. Thanks, Alistair > > > r~ From MAILER-DAEMON Fri Aug 11 16:24:50 2017 Received: from list by lists.gnu.org with archive (Exim 4.71) id 1dgGUE-0005Zn-JH for mharc-qemu-arm@gnu.org; Fri, 11 Aug 2017 16:24:50 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:43745) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dgGUC-0005Uc-Ko for qemu-arm@nongnu.org; Fri, 11 Aug 2017 16:24:49 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dgGU8-0003uS-Kb for qemu-arm@nongnu.org; Fri, 11 Aug 2017 16:24:48 -0400 Received: from mail-pg0-x235.google.com ([2607:f8b0:400e:c05::235]:36344) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1dgGU8-0003to-Bd for qemu-arm@nongnu.org; Fri, 11 Aug 2017 16:24:44 -0400 Received: by mail-pg0-x235.google.com with SMTP id v77so19464018pgb.3 for ; Fri, 11 Aug 2017 13:24:44 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=subject:to:cc:references:from:message-id:date:user-agent :mime-version:in-reply-to:content-language:content-transfer-encoding; bh=PeExYAi2rUCyBIshcdGG4fAQGZ/h6iY2lrUxQThkOls=; b=Qu5+qdADueAeMgzTWv9UVygieDwBsudZER25FTBcQpS0kWGmr3jOLExfir8NHKByVi yrRwAgBZsJE4d8uysmK4Fjkkfvyfgpt9KF6ZpPL9SBTG6x1HulvNCm26E647AaK5dcDR jwzCFH/4KRoPbPiSGLNjkt4LPb67ve7Je31jY= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:subject:to:cc:references:from:message-id:date :user-agent:mime-version:in-reply-to:content-language :content-transfer-encoding; bh=PeExYAi2rUCyBIshcdGG4fAQGZ/h6iY2lrUxQThkOls=; b=jtPSMhCus1t2LNU+6HZmniodUbajlKTxXYpbMqMhNq8cIZqI5AhR97E/vuRvLe+A7s OKM8s96Gh8MkstV7XoLLuSQgFABXKulzIhHPWrFOIr6NTvMBJaqYCrGG5HcToAwpr9QY UJwKx1Y2gXW2hSLeWjLrAgQncif1OMtxiJTV2TiY9LaRVbtaQswA+0ElVYaXNdRA6Inp MQ0QRiZG2482yHVp5mAZJBm0idqzSLUhURgU8NGhGnOTZjrI7K+QKMH+CC3aGLtDUuHV QVmOwJ5IPTmQnMfjNuHG++J7uPkeGKTKx4tlIuO+3LUiEiAllD1NgF1eATApZ3nOyMT0 QzFg== X-Gm-Message-State: AHYfb5iz0mzPyX4IQwsKYNaXxND9yh1oflkWCZAILwLBoQ9YAQk8ZH5k RhSisONHMQXyrYIA X-Received: by 10.84.129.132 with SMTP id b4mr18805296plb.294.1502483083283; Fri, 11 Aug 2017 13:24:43 -0700 (PDT) Received: from bigtime.twiddle.net (50-233-235-3-static.hfc.comcastbusiness.net. [50.233.235.3]) by smtp.gmail.com with ESMTPSA id d71sm3197502pfg.169.2017.08.11.13.24.41 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 11 Aug 2017 13:24:42 -0700 (PDT) To: Alistair Francis Cc: "qemu-devel@nongnu.org Developers" , Peter Maydell , Edgar Iglesias , qemu-arm , Edgar Iglesias References: <2fbcf76e4ff63d8527edd3662342948276e2cd37.1502474835.git.alistair.francis@xilinx.com> From: Richard Henderson Message-ID: Date: Fri, 11 Aug 2017 13:24:39 -0700 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.2.1 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 7bit X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::235 Subject: Re: [Qemu-arm] [Qemu-devel] [RFC v1 3/3] target/arm: Correct exclusive store return value X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 11 Aug 2017 20:24:49 -0000 On 08/11/2017 01:13 PM, Alistair Francis wrote: >>> + tcg_gen_ext_i64(val, val, memop); >> >> What is this addition intended to accomplish? Because of the position within >> the code, you know that memop contains MO_64, so that this is a no-op. > > This is when size == 2 so it's a 32bit operation so memop contains MO_32. It's a paired 32-bit operation, so we're operating on a 64-bit quantity. So extending from 32-bits would be actively wrong. r~ From MAILER-DAEMON Fri Aug 11 16:29:49 2017 Received: from list by lists.gnu.org with archive (Exim 4.71) id 1dgGZ3-0007Y3-Ar for mharc-qemu-arm@gnu.org; Fri, 11 Aug 2017 16:29:49 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:44729) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dgGZ1-0007WD-2n for qemu-arm@nongnu.org; Fri, 11 Aug 2017 16:29:48 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dgGZ0-0007mY-2b for qemu-arm@nongnu.org; Fri, 11 Aug 2017 16:29:47 -0400 Received: from mail-wm0-x241.google.com ([2a00:1450:400c:c09::241]:37027) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1dgGYz-0007m1-SO; Fri, 11 Aug 2017 16:29:46 -0400 Received: by mail-wm0-x241.google.com with SMTP id t138so7615549wmt.4; Fri, 11 Aug 2017 13:29:45 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=mime-version:sender:in-reply-to:references:from:date:message-id :subject:to:cc; bh=W16gJZxFCiXXtUTxyTlcrMMgyxAEGPS0lTQKTaLlJbU=; b=haIFYU8Ivj8sFbnPnHJYbqHuy8xTwJ9W2ICZCFaTDzpSK2N92jP9pk29yac3ABE6Ev T6HXXnPvV7lGQPmj8oHLNEaf3YITyde6jkfpICmmnExJaXbEm/8MkKRQXZ2lmt2ybLM7 nQJLCHA6/KGOWhAyJay/fmVgYuIFH5Qhd5oy8tM4xGSYhfn+zqUJr5KYp88FYMh5/xXn 5DUISJkDvTPJxHpoqwczQvJ9LMOxobcrXMcvJsappIXs/BCpFAC+lVfWFzIhZheznzZn Qz2R2F5Ogc4zEri6QuEaWyrnEX8Nk9KIPs5yaxVgfAKwunsfXe4YSwaeaW/amMwXsQkd 2l+g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:sender:in-reply-to:references:from :date:message-id:subject:to:cc; bh=W16gJZxFCiXXtUTxyTlcrMMgyxAEGPS0lTQKTaLlJbU=; b=QLLP59dtM9rqL0PvL7CpPnc4Yoqg6F8KHPzsJvjGFCC4sj/Zge9gHmBKPWOV/FE+WE LVVPkLzazwKlUCSfmpmCVNEj7XHdyjIN+LRkWjK3idjx1qrwaapxWgnTXbWFsrWqG/Of mA11fJcZb1JCkJ4HxU6uPkXUrfoA9PeOIASsc9xHQSitsdryYfWE9BMqeacARQh2sO1D eBqUiBVr14DDF3/NfAuAFqQHKmh7jWv/WHMIyi713y822UKMBqEZlBzMsRP5p46AXbQa uJu4xZ62rgAIw6suKmeekV7o/srWRygJHobLreyABrcpSq485K/qpYu+Xp7nap2Kn3uX Lxeg== X-Gm-Message-State: AHYfb5iLSybs87xR0ffln3QwfMW8y/rs3w4w4kZOUjurIeEFJb1WCy+x qLgT+NYYVR4CSk3Go6wp0D6pGllfKQ== X-Received: by 10.28.96.197 with SMTP id u188mr9751410wmb.73.1502483384774; Fri, 11 Aug 2017 13:29:44 -0700 (PDT) MIME-Version: 1.0 Sender: alistair23@gmail.com Received: by 10.28.191.130 with HTTP; Fri, 11 Aug 2017 13:29:13 -0700 (PDT) In-Reply-To: References: <2fbcf76e4ff63d8527edd3662342948276e2cd37.1502474835.git.alistair.francis@xilinx.com> From: Alistair Francis Date: Fri, 11 Aug 2017 13:29:13 -0700 X-Google-Sender-Auth: B5vEagpSAGZ8MBsJH7rZb12-GkY Message-ID: To: Richard Henderson Cc: Alistair Francis , Edgar Iglesias , Peter Maydell , qemu-arm , "qemu-devel@nongnu.org Developers" , Edgar Iglesias Content-Type: text/plain; charset="UTF-8" X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:400c:c09::241 Subject: Re: [Qemu-arm] [Qemu-devel] [RFC v1 3/3] target/arm: Correct exclusive store return value X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 11 Aug 2017 20:29:48 -0000 On Fri, Aug 11, 2017 at 1:24 PM, Richard Henderson wrote: > On 08/11/2017 01:13 PM, Alistair Francis wrote: >>>> + tcg_gen_ext_i64(val, val, memop); >>> >>> What is this addition intended to accomplish? Because of the position within >>> the code, you know that memop contains MO_64, so that this is a no-op. >> >> This is when size == 2 so it's a 32bit operation so memop contains MO_32. > > It's a paired 32-bit operation, so we're operating on a 64-bit quantity. So > extending from 32-bits would be actively wrong. >From what I can see though, the 32bit memop is carried into the tcg_gen_atomic_cmpxchg_i64() call so the value returned to tmp is masked by the 32bit operation. Is passing down MO_32 into tcg_gen_atomic_cmpxchg_i64() wrong then as it ends up as a 64-bit operation? My TCG knowledge is pretty limited here. Thanks, Alistair > > > r~ > From MAILER-DAEMON Fri Aug 11 16:38:17 2017 Received: from list by lists.gnu.org with archive (Exim 4.71) id 1dgGhF-00036P-7d for mharc-qemu-arm@gnu.org; Fri, 11 Aug 2017 16:38:17 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:46873) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dgGhC-00035J-Eq for qemu-arm@nongnu.org; Fri, 11 Aug 2017 16:38:15 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dgGh9-0004ts-7e for qemu-arm@nongnu.org; Fri, 11 Aug 2017 16:38:14 -0400 Received: from mail-pg0-x235.google.com ([2607:f8b0:400e:c05::235]:35267) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1dgGh8-0004tX-Vv for qemu-arm@nongnu.org; Fri, 11 Aug 2017 16:38:11 -0400 Received: by mail-pg0-x235.google.com with SMTP id v189so19628921pgd.2 for ; Fri, 11 Aug 2017 13:38:10 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=subject:to:cc:references:from:message-id:date:user-agent :mime-version:in-reply-to:content-language:content-transfer-encoding; bh=UPSNMKtRU3jlDqHEXvesYT7boWGThUh/8TgNRsen8fQ=; b=eS1vuiybmNBw1/0LTrk+jP2FfHouu6bv6sztWfHvltmh1VyW2UgHZ5Qs+Dr1Uqq6LP gZFZ3s6oAUWVP/uVQn1AS7B/Wg8kiRzQBGjbEicHGhTRNPHpeoIl+h2QVdvSk7djQ1i8 ilAUP80CL0P52ARzbs4XYDDpoiMNMbLmwvRuc= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:subject:to:cc:references:from:message-id:date :user-agent:mime-version:in-reply-to:content-language :content-transfer-encoding; bh=UPSNMKtRU3jlDqHEXvesYT7boWGThUh/8TgNRsen8fQ=; b=BYhCErH8BGOf+02YEMKIGi8Bn4ZUfUPeEFFhNO+ZOqoT0Yag/+yqDOjvfHyKDLoSqb 4osQYVsMF5AO4q5gI2Y0nAyB8ObN/bg4S+eO0x0WREwneyxmDf/ZrICVtXPZfkS/l3kH B2Z17v2kTtMGA4Q7JQjmFseXq2d9pNDSp9Bsudmxo8OYpeP0f0XnCIaJtw2y8zNsehzy IPoM8digpuDDQIg49pLmL5DhPlCp2uZRLIpwPq6Eua/6phMtpuW8XAog6nren8Wuvxwa p52azBMhGPPma3OHjTYZh1wDez7M2cbg6LoD7n8osPxO8iteQ2UGO12/V3JvrBpkaOcS HEeg== X-Gm-Message-State: AHYfb5iW2SSrpFoes+V5Zhybz2OhIY5aqZfUSLOFT8lQRlmlIF13vczs 8OUCQem2evdtdlAf X-Received: by 10.84.217.143 with SMTP id p15mr19199877pli.45.1502483889989; Fri, 11 Aug 2017 13:38:09 -0700 (PDT) Received: from bigtime.twiddle.net (50-233-235-3-static.hfc.comcastbusiness.net. [50.233.235.3]) by smtp.gmail.com with ESMTPSA id d5sm3099907pfc.110.2017.08.11.13.38.08 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 11 Aug 2017 13:38:09 -0700 (PDT) To: Alistair Francis Cc: Edgar Iglesias , Peter Maydell , qemu-arm , "qemu-devel@nongnu.org Developers" , Edgar Iglesias References: <2fbcf76e4ff63d8527edd3662342948276e2cd37.1502474835.git.alistair.francis@xilinx.com> From: Richard Henderson Message-ID: Date: Fri, 11 Aug 2017 13:38:06 -0700 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.2.1 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 7bit X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::235 Subject: Re: [Qemu-arm] [Qemu-devel] [RFC v1 3/3] target/arm: Correct exclusive store return value X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 11 Aug 2017 20:38:15 -0000 On 08/11/2017 01:29 PM, Alistair Francis wrote: > On Fri, Aug 11, 2017 at 1:24 PM, Richard Henderson > wrote: >> On 08/11/2017 01:13 PM, Alistair Francis wrote: >>>>> + tcg_gen_ext_i64(val, val, memop); >>>> >>>> What is this addition intended to accomplish? Because of the position within >>>> the code, you know that memop contains MO_64, so that this is a no-op. >>> >>> This is when size == 2 so it's a 32bit operation so memop contains MO_32. >> >> It's a paired 32-bit operation, so we're operating on a 64-bit quantity. So >> extending from 32-bits would be actively wrong. > > From what I can see though, the 32bit memop is carried into the > tcg_gen_atomic_cmpxchg_i64() call so the value returned to tmp is > masked by the 32bit operation. > > Is passing down MO_32 into tcg_gen_atomic_cmpxchg_i64() wrong then as > it ends up as a 64-bit operation? If we're passing MO_32 down to cmpxchg_i64 for this case, you have indeed found a bug. I'll investigate this further on Monday. r~ From MAILER-DAEMON Fri Aug 11 16:40:00 2017 Received: from list by lists.gnu.org with archive (Exim 4.71) id 1dgGiu-0004N6-IY for mharc-qemu-arm@gnu.org; Fri, 11 Aug 2017 16:40:00 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:47166) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dgGis-0004Ma-70 for qemu-arm@nongnu.org; Fri, 11 Aug 2017 16:39:59 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dgGir-0005Sr-AO for qemu-arm@nongnu.org; Fri, 11 Aug 2017 16:39:58 -0400 Received: from mail-wm0-x242.google.com ([2a00:1450:400c:c09::242]:33667) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1dgGir-0005Sb-3P; Fri, 11 Aug 2017 16:39:57 -0400 Received: by mail-wm0-x242.google.com with SMTP id q189so7702067wmd.0; Fri, 11 Aug 2017 13:39:56 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=mime-version:sender:in-reply-to:references:from:date:message-id :subject:to:cc; bh=zV9QWIxV6wzmM5IBfOEINdXAxYtrvH29wYW8MYYeywE=; b=HRvX8vhQdLheCBSMpc8ruUgLE9EBmApFYD2H9Bvggb1wKEQll+jZFsCdV4Xa+TlOHn EXnXtEJXKbmaF/H5XYGtgkpzmN6jMFmRiRXBJXIt2CCa5TgWleeyxhuRaRQi3p+Bx+P8 WKRb2LLOwtPE7RBySHgzNISWO7iixCsBjH1w/cANXx6aJADsGF9Rq0p4mGj3FcVYo2uy hYvMm0M47eXd7SjRM29EF0mZaxR0m7yIAD03xc4WlSPot5y578TmfIhRiHGimMWppcZ9 NRX8h39kNSKX4KekrtaJBKcUS2kr2v5z7E8nVvG6VacWEqFWNbKmPcWhhOTLR1p05gIg R3rg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:sender:in-reply-to:references:from :date:message-id:subject:to:cc; bh=zV9QWIxV6wzmM5IBfOEINdXAxYtrvH29wYW8MYYeywE=; b=JmUe+WMLm+YFsFQJ1jpflbw+Y1GAvhdmksnJCbuv/4TX9BUMG2SmMs1TAbMjHmKceK DKIltzBacAi2I19MeaCOFarVMZGn5PiGXi8yIK0AZ/T58kXspIajGXPlPuUr+7UVOqai 7R97Fb6FdkKb1zGGU4wTtgA57a+okKW26LgiR0rsdptETx4yekP0jET/grC+WJNFu/Zp BVrctjHYg/mOhE1auD33weHgOjqh4jsYpBzQz6IgjTuv4ZFuY7U1fCsLqQ+Mixq+UQNS blm8zl6Ti8SfN0JUCz880dlW5FbnXzSHb4ZmErfMlpsB9zNPUzCQDNEoPNCPaPfaB53a 6XKQ== X-Gm-Message-State: AHYfb5iq7khtEybMYL5ZN6RmynypcEn5Gy8f49nHvyVVz0DTtJ1IMT93 1ibQq1innWUHZYGMqjeC8oOa7uctTA== X-Received: by 10.28.207.10 with SMTP id f10mr6854wmg.159.1502483995915; Fri, 11 Aug 2017 13:39:55 -0700 (PDT) MIME-Version: 1.0 Sender: alistair23@gmail.com Received: by 10.28.191.130 with HTTP; Fri, 11 Aug 2017 13:39:25 -0700 (PDT) In-Reply-To: References: <2fbcf76e4ff63d8527edd3662342948276e2cd37.1502474835.git.alistair.francis@xilinx.com> From: Alistair Francis Date: Fri, 11 Aug 2017 13:39:25 -0700 X-Google-Sender-Auth: YWl0fSCFSNHvEwCnvnXUfHCuIWQ Message-ID: To: Richard Henderson Cc: Alistair Francis , Edgar Iglesias , Peter Maydell , qemu-arm , "qemu-devel@nongnu.org Developers" , Edgar Iglesias Content-Type: text/plain; charset="UTF-8" X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:400c:c09::242 Subject: Re: [Qemu-arm] [Qemu-devel] [RFC v1 3/3] target/arm: Correct exclusive store return value X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 11 Aug 2017 20:39:59 -0000 On Fri, Aug 11, 2017 at 1:38 PM, Richard Henderson wrote: > On 08/11/2017 01:29 PM, Alistair Francis wrote: >> On Fri, Aug 11, 2017 at 1:24 PM, Richard Henderson >> wrote: >>> On 08/11/2017 01:13 PM, Alistair Francis wrote: >>>>>> + tcg_gen_ext_i64(val, val, memop); >>>>> >>>>> What is this addition intended to accomplish? Because of the position within >>>>> the code, you know that memop contains MO_64, so that this is a no-op. >>>> >>>> This is when size == 2 so it's a 32bit operation so memop contains MO_32. >>> >>> It's a paired 32-bit operation, so we're operating on a 64-bit quantity. So >>> extending from 32-bits would be actively wrong. >> >> From what I can see though, the 32bit memop is carried into the >> tcg_gen_atomic_cmpxchg_i64() call so the value returned to tmp is >> masked by the 32bit operation. >> >> Is passing down MO_32 into tcg_gen_atomic_cmpxchg_i64() wrong then as >> it ends up as a 64-bit operation? > > If we're passing MO_32 down to cmpxchg_i64 for this case, you have indeed found > a bug. I'll investigate this further on Monday. Maybe that is why I'm seeing these failures. I'll have a look as well to see if this fixes my problems. Thanks, Alistair > > > r~ > From MAILER-DAEMON Fri Aug 11 16:53:58 2017 Received: from list by lists.gnu.org with archive (Exim 4.71) id 1dgGwQ-0001G6-G0 for mharc-qemu-arm@gnu.org; Fri, 11 Aug 2017 16:53:58 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:49682) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dgGwO-0001FR-BB for qemu-arm@nongnu.org; Fri, 11 Aug 2017 16:53:57 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dgGwN-0005rx-8W for qemu-arm@nongnu.org; Fri, 11 Aug 2017 16:53:56 -0400 Received: from mail-wr0-x244.google.com ([2a00:1450:400c:c0c::244]:36648) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1dgGwN-0005rh-1s; Fri, 11 Aug 2017 16:53:55 -0400 Received: by mail-wr0-x244.google.com with SMTP id y67so3237328wrb.3; Fri, 11 Aug 2017 13:53:54 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=mime-version:sender:in-reply-to:references:from:date:message-id :subject:to:cc; bh=SDWepybD+uv6sbk2bkGZVlYHgM15ZpLTU3C9YpEvduM=; b=cXj93ltse74kKhv42Kf6SKTO1plCMYVx4puSmYLb7thWOZp0ey5Abwmyi9/r0BwxfN 26/OVZ4I0OtM0+aggUMd/XpYryvcOiw1k0af3/JnEavnxRqQPJGcQBomHsFU5Hj3GCrz yNJLK10qrTY6DWHGwbMp/CP8TKzR+M9Ehpv8uQmHmA1D2TR2By0buIKUzGbCuorjHJ67 UB1QrjNZmKdydyBom1ekK9VhYQDaXBD7+kE15adBhO3xoj6Ct8GY9f4dn6zJWrjp7CDg KFE6iO1DygZc4VAhobMUewKUW075iCxPdOHgeVdKatl8MYy4ZnAbE/1HFEP55H9sNpV8 0oKA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:sender:in-reply-to:references:from :date:message-id:subject:to:cc; bh=SDWepybD+uv6sbk2bkGZVlYHgM15ZpLTU3C9YpEvduM=; b=UxrDdAsypcm0aGBfaI8tE9UC6dEXknnTsWvozimjTiHk/I2AlYjO9vcpUk6GFqD4yc GdRZLmBTPxjILNIFF1emseWWZeduHrmeWLwBGZx7ZP1+aSR4TRp3lmc0/RrkLm2aiB5y 6Yn9DSwNvKXAIFZBZRxgl6sIQS8nfnyqjJFWfQxmqYKLVATN38bY0OCvKWjAPzkfCVyy piCp+23D7DtKwvKtwluf4Q6RU6xeEbXKMNJ3HaT89aYveNBvU0/TqiKDInaL0htR94Sz R9530z53SaFNpbVIkGDjSgUlAYKpdsNX52WvLS85b5JWm8d+Sl21TVzyWKbCPGtpnOts 1efQ== X-Gm-Message-State: AHYfb5gbbsp+qkIyotRNLLqO4K7yenq87hlL34AFrijU3T8ywXItatVo yob7nFg0Q4HRotE/MG6NybkBI1v88Q== X-Received: by 10.223.163.135 with SMTP id l7mr13752109wrb.89.1502484833861; Fri, 11 Aug 2017 13:53:53 -0700 (PDT) MIME-Version: 1.0 Sender: alistair23@gmail.com Received: by 10.28.191.130 with HTTP; Fri, 11 Aug 2017 13:53:23 -0700 (PDT) In-Reply-To: References: <2fbcf76e4ff63d8527edd3662342948276e2cd37.1502474835.git.alistair.francis@xilinx.com> From: Alistair Francis Date: Fri, 11 Aug 2017 13:53:23 -0700 X-Google-Sender-Auth: dVT5z-d3DE4tvRj9sg6xL-tWTA0 Message-ID: To: Alistair Francis Cc: Richard Henderson , Edgar Iglesias , Peter Maydell , qemu-arm , "qemu-devel@nongnu.org Developers" , Edgar Iglesias Content-Type: text/plain; charset="UTF-8" X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:400c:c0c::244 Subject: Re: [Qemu-arm] [Qemu-devel] [RFC v1 3/3] target/arm: Correct exclusive store return value X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 11 Aug 2017 20:53:57 -0000 On Fri, Aug 11, 2017 at 1:39 PM, Alistair Francis wrote: > On Fri, Aug 11, 2017 at 1:38 PM, Richard Henderson > wrote: >> On 08/11/2017 01:29 PM, Alistair Francis wrote: >>> On Fri, Aug 11, 2017 at 1:24 PM, Richard Henderson >>> wrote: >>>> On 08/11/2017 01:13 PM, Alistair Francis wrote: >>>>>>> + tcg_gen_ext_i64(val, val, memop); >>>>>> >>>>>> What is this addition intended to accomplish? Because of the position within >>>>>> the code, you know that memop contains MO_64, so that this is a no-op. >>>>> >>>>> This is when size == 2 so it's a 32bit operation so memop contains MO_32. >>>> >>>> It's a paired 32-bit operation, so we're operating on a 64-bit quantity. So >>>> extending from 32-bits would be actively wrong. >>> >>> From what I can see though, the 32bit memop is carried into the >>> tcg_gen_atomic_cmpxchg_i64() call so the value returned to tmp is >>> masked by the 32bit operation. >>> >>> Is passing down MO_32 into tcg_gen_atomic_cmpxchg_i64() wrong then as >>> it ends up as a 64-bit operation? >> >> If we're passing MO_32 down to cmpxchg_i64 for this case, you have indeed found >> a bug. I'll investigate this further on Monday. > > Maybe that is why I'm seeing these failures. I'll have a look as well > to see if this fixes my problems. That's it. That wrong mask was causing all my breakages. I'll send out a new series, thanks for your help. Thanks, Alistair > > Thanks, > Alistair > >> >> >> r~ >> From MAILER-DAEMON Fri Aug 11 18:21:16 2017 Received: from list by lists.gnu.org with archive (Exim 4.71) id 1dgIIu-0008Pe-E0 for mharc-qemu-arm@gnu.org; Fri, 11 Aug 2017 18:21:16 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:39922) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dgIIr-0008P9-BU for qemu-arm@nongnu.org; Fri, 11 Aug 2017 18:21:14 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dgIIo-0007Gf-90 for qemu-arm@nongnu.org; Fri, 11 Aug 2017 18:21:13 -0400 Received: from mail-by2nam03on0074.outbound.protection.outlook.com ([104.47.42.74]:44064 helo=NAM03-BY2-obe.outbound.protection.outlook.com) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1dgIIn-0007Fk-Op; Fri, 11 Aug 2017 18:21:10 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=xilinx.onmicrosoft.com; s=selector1-xilinx-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version; 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Ip=[149.199.60.100]; Helo=[xsj-pvapsmtpgw02] X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BN6PR02MB2241 X-detected-operating-system: by eggs.gnu.org: Windows 7 or 8 [fuzzy] X-Received-From: 104.47.42.74 Subject: [Qemu-arm] [PATCH v1 0/3] Fixup exclusive store logic X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 11 Aug 2017 22:21:14 -0000 I found some issues with the way exclusive store was working. This patch series seems to fix the test cases that were failing for me. The first patch is just a simple adjustment. The third patch fixes the main bug I was seeing. The second patch is left over from the RFC that seems like it is still a good idea. Changes from RFC: - Rewrite the third patch to correctly fix the issue. Alistair Francis (3): target/arm: Update the memops for exclusive load tcg/tcg-op: Expose the tcg_gen_ext_i* functions target/arm: Correct exclusive store cmpxchg memop mask target/arm/translate-a64.c | 4 ++-- tcg/tcg-op.c | 4 ++-- tcg/tcg-op.h | 2 ++ 3 files changed, 6 insertions(+), 4 deletions(-) -- 2.11.0 From MAILER-DAEMON Fri Aug 11 18:21:16 2017 Received: from list by lists.gnu.org with archive (Exim 4.71) id 1dgIIu-0008Pq-HP for mharc-qemu-arm@gnu.org; Fri, 11 Aug 2017 18:21:16 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:39927) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dgIIr-0008PC-OD for qemu-arm@nongnu.org; Fri, 11 Aug 2017 18:21:15 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dgIIo-0007Gm-KG for qemu-arm@nongnu.org; Fri, 11 Aug 2017 18:21:13 -0400 Received: from mail-sn1nam02on0057.outbound.protection.outlook.com ([104.47.36.57]:40256 helo=NAM02-SN1-obe.outbound.protection.outlook.com) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1dgIIo-0007GM-B7; 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Fri, 11 Aug 2017 15:21:03 -0700 Received: from xsj-pvapsmtp01 (smtp3.xilinx.com [149.199.38.66]) by xsj-smtp-dlp2.xlnx.xilinx.com (8.13.8/8.13.1) with ESMTP id v7BML28i011766; Fri, 11 Aug 2017 15:21:02 -0700 Received: from [172.19.2.220] (helo=localhost.localdomain) by xsj-pvapsmtp01 with esmtp (Exim 4.63) (envelope-from ) id 1dgIIg-0006HS-1U; Fri, 11 Aug 2017 15:21:02 -0700 From: Alistair Francis To: , CC: , , , , Date: Fri, 11 Aug 2017 15:17:38 -0700 Message-ID: <885b354ba1e79510bfd6a905d62971c275645ad5.1502488636.git.alistair.francis@xilinx.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: References: X-RCIS-Action: ALLOW X-TM-AS-Product-Ver: IMSS-7.1.0.1224-8.1.0.1062-23250.005 X-TM-AS-User-Approved-Sender: Yes;Yes X-EOPAttributedMessage: 0 X-MS-Office365-Filtering-HT: Tenant X-Forefront-Antispam-Report: CIP:149.199.60.83; IPV:NLI; CTRY:US; EFV:NLI; SFV:NSPM; SFS:(10009020)(6009001)(39860400002)(2980300002)(438002)(189002)(199003)(63266004)(77096006)(2906002)(36386004)(4326008)(626005)(5660300001)(6666003)(2950100002)(478600001)(305945005)(5003940100001)(50466002)(48376002)(118296001)(356003)(50986999)(50226002)(76176999)(47776003)(9786002)(33646002)(8936002)(106466001)(39060400002)(36756003)(81166006)(54906002)(189998001)(8676002)(81156014)(107986001); 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Ip=[149.199.60.83]; Helo=[xsj-pvapsmtpgw01] X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BY1PR0201MB1045 X-detected-operating-system: by eggs.gnu.org: Windows 7 or 8 [fuzzy] X-Received-From: 104.47.36.57 Subject: [Qemu-arm] [PATCH v1 2/3] tcg/tcg-op: Expose the tcg_gen_ext_i* functions X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 11 Aug 2017 22:21:15 -0000 Expose the tcg_gen_ext_i32() and tcg_gen_ext_i64() functions. Signed-off-by: Alistair Francis Reviewed-by: Richard Henderson --- Although I no longer am using these functions I have left this patch in as Richard thought it was a good idea. tcg/tcg-op.c | 4 ++-- tcg/tcg-op.h | 2 ++ 2 files changed, 4 insertions(+), 2 deletions(-) diff --git a/tcg/tcg-op.c b/tcg/tcg-op.c index 87f673ef49..d25e3003ef 100644 --- a/tcg/tcg-op.c +++ b/tcg/tcg-op.c @@ -2709,7 +2709,7 @@ void tcg_gen_qemu_st_i64(TCGv_i64 val, TCGv addr, TCGArg idx, TCGMemOp memop) gen_ldst_i64(INDEX_op_qemu_st_i64, val, addr, memop, idx); } -static void tcg_gen_ext_i32(TCGv_i32 ret, TCGv_i32 val, TCGMemOp opc) +void tcg_gen_ext_i32(TCGv_i32 ret, TCGv_i32 val, TCGMemOp opc) { switch (opc & MO_SSIZE) { case MO_SB: @@ -2730,7 +2730,7 @@ static void tcg_gen_ext_i32(TCGv_i32 ret, TCGv_i32 val, TCGMemOp opc) } } -static void tcg_gen_ext_i64(TCGv_i64 ret, TCGv_i64 val, TCGMemOp opc) +void tcg_gen_ext_i64(TCGv_i64 ret, TCGv_i64 val, TCGMemOp opc) { switch (opc & MO_SSIZE) { case MO_SB: diff --git a/tcg/tcg-op.h b/tcg/tcg-op.h index 5d3278f243..8c45b79a92 100644 --- a/tcg/tcg-op.h +++ b/tcg/tcg-op.h @@ -835,6 +835,8 @@ void tcg_gen_qemu_ld_i32(TCGv_i32, TCGv, TCGArg, TCGMemOp); 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Ip=[149.199.60.100]; Helo=[xsj-pvapsmtpgw02] X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MWHPR02MB2254 X-detected-operating-system: by eggs.gnu.org: Windows 7 or 8 [fuzzy] X-Received-From: 104.47.34.40 Subject: [Qemu-arm] [PATCH v1 1/3] target/arm: Update the memops for exclusive load X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 11 Aug 2017 22:21:16 -0000 Acording to the ARM ARM exclusive loads require the same allignment as exclusive stores. Let's update the memops used for the load to match that of the store. This adds the alignment requirement to the memops. Signed-off-by: Alistair Francis Reviewed-by: Richard Henderson --- target/arm/translate-a64.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 58ed4c6d05..245175e2f1 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -1854,7 +1854,7 @@ static void gen_load_exclusive(DisasContext *s, int rt, int rt2, TCGv_i64 addr, int size, bool is_pair) { TCGv_i64 tmp = tcg_temp_new_i64(); - TCGMemOp memop = s->be_data + size; + TCGMemOp memop = size | MO_ALIGN | s->be_data; g_assert(size <= 3); tcg_gen_qemu_ld_i64(tmp, addr, get_mem_index(s), memop); -- 2.11.0 From MAILER-DAEMON Fri Aug 11 18:21:29 2017 Received: from list by lists.gnu.org with archive (Exim 4.71) id 1dgIJ5-00008K-Cp for mharc-qemu-arm@gnu.org; Fri, 11 Aug 2017 18:21:28 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:39996) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dgIJ2-00005p-IX for qemu-arm@nongnu.org; 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Fri, 11 Aug 2017 15:21:14 -0700 Received: from xsj-pvapsmtp01 (smtp2.xilinx.com [149.199.38.66]) by xsj-smtp-dlp2.xlnx.xilinx.com (8.13.8/8.13.1) with ESMTP id v7BML4tT011788; Fri, 11 Aug 2017 15:21:04 -0700 Received: from [172.19.2.220] (helo=localhost.localdomain) by xsj-pvapsmtp01 with esmtp (Exim 4.63) (envelope-from ) id 1dgIIi-0006JG-E1; Fri, 11 Aug 2017 15:21:04 -0700 From: Alistair Francis To: , CC: , , , , Date: Fri, 11 Aug 2017 15:17:41 -0700 Message-ID: X-Mailer: git-send-email 2.11.0 In-Reply-To: References: X-RCIS-Action: ALLOW X-TM-AS-Product-Ver: IMSS-7.1.0.1224-8.1.0.1062-23250.005 X-TM-AS-User-Approved-Sender: Yes;Yes X-EOPAttributedMessage: 0 X-MS-Office365-Filtering-HT: Tenant X-Forefront-Antispam-Report: CIP:149.199.60.83; IPV:NLI; CTRY:US; EFV:NLI; SFV:NSPM; SFS:(10009020)(6009001)(39860400002)(2980300002)(438002)(189002)(199003)(33646002)(6666003)(189998001)(118296001)(8936002)(36386004)(106466001)(81166006)(81156014)(8676002)(77096006)(54906002)(2950100002)(39060400002)(5660300001)(47776003)(36756003)(478600001)(305945005)(356003)(48376002)(4326008)(626005)(2906002)(63266004)(50986999)(5003940100001)(50466002)(50226002)(9786002)(76176999)(40753002)(133343001)(107986001); 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Ip=[149.199.60.83]; Helo=[xsj-pvapsmtpgw01] X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY4PR02MB2245 X-detected-operating-system: by eggs.gnu.org: Windows 7 or 8 [fuzzy] X-Received-From: 104.47.36.65 Subject: [Qemu-arm] [PATCH v1 3/3] target/arm: Correct exclusive store cmpxchg memop mask X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 11 Aug 2017 22:21:25 -0000 When we perform the atomic_cmpxchg operation we want to perform the operation on a pair of 32-bit registers. Previously we were just passing the register size in which was set to MO_32. This would result in the high register to be ignored. To fix this issue we hardcode the size to be 64-bits long when operating on 32-bit pairs. Signed-off-by: Alistair Francis --- This was caught with an internal fuzzy tester. These patches fix the Xilinx 2.10-rc2 tree. I tested with the fuzzy tester (single CPU) and Linux boot (4 CPUs) on the Xilinx tree. I don't have a good test case to run on mainline, but am working with some internal teams to get one. Also linux-user is fully untested. All tests were with MTTCG enabled. target/arm/translate-a64.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 245175e2f1..49b4d6918d 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -1913,7 +1913,7 @@ static void gen_store_exclusive(DisasContext *s, int rd, int rt, int rt2, tcg_gen_concat32_i64(val, cpu_exclusive_val, cpu_exclusive_high); tcg_gen_atomic_cmpxchg_i64(tmp, addr, val, tmp, get_mem_index(s), - size | MO_ALIGN | s->be_data); + MO_64 | MO_ALIGN | s->be_data); tcg_gen_setcond_i64(TCG_COND_NE, tmp, tmp, val); tcg_temp_free_i64(val); } else if (s->be_data == MO_LE) { -- 2.11.0 From MAILER-DAEMON Fri Aug 11 19:21:52 2017 Received: from list by lists.gnu.org with archive (Exim 4.71) id 1dgJFY-000648-3v for mharc-qemu-arm@gnu.org; Fri, 11 Aug 2017 19:21:52 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:50185) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dgJFW-00062l-2M for qemu-arm@nongnu.org; Fri, 11 Aug 2017 19:21:51 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dgJFV-00012t-0o for qemu-arm@nongnu.org; Fri, 11 Aug 2017 19:21:50 -0400 Received: from mail-wm0-x241.google.com ([2a00:1450:400c:c09::241]:38661) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1dgJFS-00012L-KY; Fri, 11 Aug 2017 19:21:46 -0400 Received: by mail-wm0-x241.google.com with SMTP id y206so7955488wmd.5; Fri, 11 Aug 2017 16:21:46 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=mime-version:in-reply-to:references:from:date:message-id:subject:to :cc; bh=8g1YqebbzmFmaCrk5Iwzg4Qc8CE1lcarDjfgPi9EFSc=; b=G1XyN+kfHOuWaVDM4G1wZ//D6yhIHxIcnBEN0XqkI3L7kMFiKzfKJgJStO9NzQ7v4a 5FZPatFAYPefOAoauxjrvxFehohu0OjuNUdsQ30G+LDIc3JowpEu8oxd3cgadj4/HmtR xGIeo7Ugo/+Plp+W+BVald9ohEeFP2NaI2HfmZ6seNTP2XpV5wy19TDkKgB6ayNcRuLj IIld7drCw9+6bt9f8bQV2REVKirZXzBX/LrNv//JKVm/0ERzZk4fmHVh6VQU3guZL0X2 do3lpxXlZ+f4f63jDu9ID8l1XFJzU7F11enzRiUmWKroQxr2GEqKWYjQ71P70JZuwa1E f/4g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:in-reply-to:references:from:date :message-id:subject:to:cc; bh=8g1YqebbzmFmaCrk5Iwzg4Qc8CE1lcarDjfgPi9EFSc=; b=cQemfjXKTeyJWF70xtOghSafQ/AxU9jhQAiPIc6zHzEbTWgJiq7rsfPix3R3ESkDfJ +3bqK0OZQ34/HAfEo1QrDWNsG5KkrRf9Wd1dso6wLXtDXfKxKr5fl7c30mV0IzTqwG6O 1n5BHXb5txH1hcZxjOBVUZ5+GEBFL/b9D4cBPgJZvXD7QoBicNZNYj5fI3IdYjW9fd8n A65/tUnQtHfQ2qurdOD+Nu3W8GJGdkpX199+yvn7gT47Y0kRGg0mCJjllugxPWPdFFsQ ZfIpGZfqwGH7acqHBcvh7Om6FblB6xQTJCZSIXw9D8uZe4LWDnWvwmCCknmVr4Z+tPLf Besg== X-Gm-Message-State: AHYfb5ih+0uFbViqo33Y/5rihTLZS6QqFNCxMW0n0gjc6tad3LqIApcl 9qz0eX3dTYKoUCxgIsFvOcwyF7+EmA== X-Received: by 10.28.96.197 with SMTP id u188mr141850wmb.73.1502493705616; Fri, 11 Aug 2017 16:21:45 -0700 (PDT) MIME-Version: 1.0 Received: by 10.28.191.130 with HTTP; Fri, 11 Aug 2017 16:21:14 -0700 (PDT) In-Reply-To: References: From: Alistair Francis Date: Fri, 11 Aug 2017 16:21:14 -0700 Message-ID: To: Alistair Francis Cc: "qemu-devel@nongnu.org Developers" , Peter Maydell , Edgar Iglesias , Edgar Iglesias , qemu-arm Content-Type: text/plain; charset="UTF-8" X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:400c:c09::241 Subject: Re: [Qemu-arm] [PATCH v1 0/3] Fixup exclusive store logic X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 11 Aug 2017 23:21:51 -0000 On Fri, Aug 11, 2017 at 3:17 PM, Alistair Francis wrote: > I found some issues with the way exclusive store was working. This patch > series seems to fix the test cases that were failing for me. > > The first patch is just a simple adjustment. > > The third patch fixes the main bug I was seeing. > > The second patch is left over from the RFC that seems like it is still a > good idea. After working with the internal fuzzy testing team I have a test case where exclusive operations are failing on master but working on top of this patch series. Thanks, Alistair > > Changes from RFC: > - Rewrite the third patch to correctly fix the issue. > > Alistair Francis (3): > target/arm: Update the memops for exclusive load > tcg/tcg-op: Expose the tcg_gen_ext_i* functions > target/arm: Correct exclusive store cmpxchg memop mask > > target/arm/translate-a64.c | 4 ++-- > tcg/tcg-op.c | 4 ++-- > tcg/tcg-op.h | 2 ++ > 3 files changed, 6 insertions(+), 4 deletions(-) > > -- > 2.11.0 > From MAILER-DAEMON Fri Aug 11 19:23:20 2017 Received: from list by lists.gnu.org with archive (Exim 4.71) id 1dgJGx-0006wn-TG for mharc-qemu-arm@gnu.org; Fri, 11 Aug 2017 19:23:19 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:50354) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dgJGw-0006vM-63 for qemu-arm@nongnu.org; Fri, 11 Aug 2017 19:23:19 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dgJGv-0001KJ-74 for qemu-arm@nongnu.org; Fri, 11 Aug 2017 19:23:18 -0400 Received: from mail-wm0-x244.google.com ([2a00:1450:400c:c09::244]:38722) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1dgJGs-0001JS-IK; Fri, 11 Aug 2017 19:23:14 -0400 Received: by mail-wm0-x244.google.com with SMTP id y206so7957724wmd.5; Fri, 11 Aug 2017 16:23:14 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=mime-version:sender:in-reply-to:references:from:date:message-id :subject:to:cc; bh=2mBWWA3BaatHOtIft07HPTA8jNa7r50mNbKZ/mgAcFY=; b=uJOrNy6SGXHzo2PXiGvM2QYH9LDq97qh+3V0IKRLhuA7mcD3PFkMT0wiG9TgsquWBk j+zBgULcrEZcRcmzp1V4qFNd3CjWP8V+tG6X9NCjQyWVdaVzV7Af/zYUgwh4d2UIRNhi K1BwOUhGZ4CsmvwEy1m5N1YbVeNQfbKV/sp12+67RKGZtmJquK1m/9ayjKSVL7h+xA1T tieI3iTT2TKaW4xcjY9T+LZUWSTkUJHdu/R63pWYim8zyXkspSGrtbigRlJfLdUywPuZ CXgVwkNr+CR6lDAidj8k5yjyq4CKza6+SjvhMtOYEBGTCqTdSZ7/84jWZ+a5+Ddu5itl eZXw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:sender:in-reply-to:references:from :date:message-id:subject:to:cc; bh=2mBWWA3BaatHOtIft07HPTA8jNa7r50mNbKZ/mgAcFY=; b=fqW8o8SxUG5TRB4bcyjWFkAAMTv9zAinLG5kqFvTcPE1CoKheTI9FPHq3FvSauF2q7 Sjz6aQS0nvBMRbdp1l59LJs9tdtQ78gVquf4QkjQnwza/GyYYsx02mUJUkOvK/7LgowT PGHDSYkaeUV5TXL0WWw3h4eWhfk9ZZRLsqN3dme2AUcUXYDaTE0vq8FPiGGnl0X05Vjl l/FOV7SbkYGHCVoY5jh/HS7StGBl9lcB+gd6jmkUY4wZTZi0AztCBYmY3MSI/ce4ysm2 6XgNHFNqh2G+kt/hdDZL5sq46tsBeIw6mFqCJU3xRHxzanmfOfj04yMW9wrLSULUUABZ PKBQ== X-Gm-Message-State: AHYfb5i8Mha4D0CR0wK99yp8IqV8u87YtjbEzfARGHeVhLJ+gnSbzZae sUmgVvRNXuDH71EUAzpA0W0jaCzqPA== X-Received: by 10.28.207.10 with SMTP id f10mr119591wmg.159.1502493793512; Fri, 11 Aug 2017 16:23:13 -0700 (PDT) MIME-Version: 1.0 Sender: alistair23@gmail.com Received: by 10.28.191.130 with HTTP; Fri, 11 Aug 2017 16:22:42 -0700 (PDT) In-Reply-To: References: From: Alistair Francis Date: Fri, 11 Aug 2017 16:22:42 -0700 X-Google-Sender-Auth: vN-gdF5HWvjwn_LdKmm3_2ygJs8 Message-ID: To: Alistair Francis , portia.stephens@xilinx.com Cc: "qemu-devel@nongnu.org Developers" , Peter Maydell , Edgar Iglesias , Edgar Iglesias , qemu-arm Content-Type: text/plain; charset="UTF-8" X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:400c:c09::244 Subject: Re: [Qemu-arm] [PATCH v1 0/3] Fixup exclusive store logic X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 11 Aug 2017 23:23:19 -0000 On Fri, Aug 11, 2017 at 4:21 PM, Alistair Francis wrote: > On Fri, Aug 11, 2017 at 3:17 PM, Alistair Francis > wrote: >> I found some issues with the way exclusive store was working. This patch >> series seems to fix the test cases that were failing for me. >> >> The first patch is just a simple adjustment. >> >> The third patch fixes the main bug I was seeing. >> >> The second patch is left over from the RFC that seems like it is still a >> good idea. + Portia from fuzzy testing team. > > After working with the internal fuzzy testing team I have a test case > where exclusive operations are failing on master but working on top of > this patch series. > > Thanks, > Alistair > >> >> Changes from RFC: >> - Rewrite the third patch to correctly fix the issue. >> >> Alistair Francis (3): >> target/arm: Update the memops for exclusive load >> tcg/tcg-op: Expose the tcg_gen_ext_i* functions >> target/arm: Correct exclusive store cmpxchg memop mask >> >> target/arm/translate-a64.c | 4 ++-- >> tcg/tcg-op.c | 4 ++-- >> tcg/tcg-op.h | 2 ++ >> 3 files changed, 6 insertions(+), 4 deletions(-) >> >> -- >> 2.11.0 >> From MAILER-DAEMON Sat Aug 12 03:24:38 2017 Received: from list by lists.gnu.org with archive (Exim 4.71) id 1dgQmk-000555-Iz for mharc-qemu-arm@gnu.org; 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Sat, 12 Aug 2017 03:22:49 +0300 Received: from DAG-EX10.ad.checkpoint.com ([169.254.3.250]) by IL-EX10.ad.checkpoint.com ([169.254.2.190]) with mapi id 14.03.0351.000; Sat, 12 Aug 2017 03:22:48 +0300 From: Wagde Zabit To: "qemu-arm@nongnu.org" Thread-Topic: multiple network interfaces in vexpress-a15 Thread-Index: AdMTAPpReup0EM2HTyKDnMEsuAKuog== Date: Sat, 12 Aug 2017 00:22:47 +0000 Message-ID: <6693042127413E41B2F161A6405E34A702438DD698@DAG-EX10.ad.checkpoint.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [194.29.34.193] x-kse-antivirus-interceptor-info: scan successful x-kse-antivirus-info: Clean x-cpdlp: 1138e86b8cc5adc6784394b3a63abcc4ca8bb4cca5 Content-Type: multipart/alternative; boundary="_000_6693042127413E41B2F161A6405E34A702438DD698DAGEX10adchec_" MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 194.29.34.68 X-Mailman-Approved-At: Sat, 12 Aug 2017 03:24:37 -0400 Subject: [Qemu-arm] multiple network interfaces in vexpress-a15 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sat, 12 Aug 2017 00:23:02 -0000 --_000_6693042127413E41B2F161A6405E34A702438DD698DAGEX10adchec_ Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable Hi I'm trying to create 2 network interfaces on my virtual machine with no luc= k. Does this machine support multiple network interfaces? How can I configure = it? Thanx --_000_6693042127413E41B2F161A6405E34A702438DD698DAGEX10adchec_ Content-Type: text/html; charset="us-ascii" Content-Transfer-Encoding: quoted-printable

Hi

 

I’m trying to create 2 network interfaces on m= y virtual machine with no luck.

Does this machine support multiple network interface= s? How can I configure it?

 

Thanx

--_000_6693042127413E41B2F161A6405E34A702438DD698DAGEX10adchec_-- From MAILER-DAEMON Sat Aug 12 06:24:59 2017 Received: from list by lists.gnu.org with archive (Exim 4.71) id 1dgTbH-0003IA-9p for mharc-qemu-arm@gnu.org; Sat, 12 Aug 2017 06:24:59 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:43681) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dgTbB-0003FB-OK for qemu-arm@nongnu.org; Sat, 12 Aug 2017 06:24:58 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dgTbA-00062u-IV for qemu-arm@nongnu.org; Sat, 12 Aug 2017 06:24:53 -0400 Received: from mail-wr0-x22b.google.com ([2a00:1450:400c:c0c::22b]:34949) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1dgTbA-000626-Ab for qemu-arm@nongnu.org; Sat, 12 Aug 2017 06:24:52 -0400 Received: by mail-wr0-x22b.google.com with SMTP id k71so20649634wrc.2 for ; Sat, 12 Aug 2017 03:24:52 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:in-reply-to:references:from:date:message-id:subject:to :cc; bh=kIplSY5C/hVtzdln6tSYfVBPCMcUEHdFcS6J9hyFNTY=; b=LH/toEllEx6Fxw7ZF6dAgOSrWlpJL4XlOsBs4AToXIUxxb+wB901as+GQZ1MVyeavT /rpeIITe4Nkhwh6Uo+51lYq2blvi4aF6x1XaXlWSXqgujaT2pQUx7XtPrzy4LlcGr26t CYxF3K/Pu3tKMOPGt0IZENJvsmzRhAHepfwJk= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:in-reply-to:references:from:date :message-id:subject:to:cc; bh=kIplSY5C/hVtzdln6tSYfVBPCMcUEHdFcS6J9hyFNTY=; b=B3Bo7Dc5GrDFsOW6eXl/3pYhjqBOH9ZNw4YTuP6SVNtc2MrVRRMwblIkbTrZl6VvHG t+Gl9dOi9QpLaY0cpUQFXYpYNCIpLxpRdvhIaJEJgKDV2Gj2/ddRfGx4LetFmkxliOwK TQjm+Qic2eZwwn/BrJg9tw91qAcNUAactl++qzMgaf+oy1Aqt9R0sLWcvo4bFgy67Goc vSFUFrmvFCc85TO6Dt0iV5l44O8MIZG9envJcZVJ6vjKS3CeQHe1bK8TebjnvB8OHeld zivNkFWqA1hpE2WGKyDRNrtFCa/SpPx3fbwE+EH4cdtN4cw7zuYKyNfMMmrPX1dB4PX+ rc7Q== X-Gm-Message-State: AHYfb5jVaCjL2vaojn5csf13AS9BUF1cV85vozEthlCQ3t2WfKiodAcU 4YBwY5dObSF4jUjRoDXpFowkW6sorsB2 X-Received: by 10.223.165.138 with SMTP id g10mr11904932wrc.167.1502533490735; Sat, 12 Aug 2017 03:24:50 -0700 (PDT) MIME-Version: 1.0 Received: by 10.223.134.54 with HTTP; Sat, 12 Aug 2017 03:24:30 -0700 (PDT) In-Reply-To: References: From: Peter Maydell Date: Sat, 12 Aug 2017 11:24:30 +0100 Message-ID: To: Alistair Francis Cc: QEMU Developers , Alistair Francis , Edgar Iglesias , "Edgar E. Iglesias" , qemu-arm Content-Type: text/plain; charset="UTF-8" X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:400c:c0c::22b Subject: Re: [Qemu-arm] [PATCH v1 0/3] Fixup exclusive store logic X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sat, 12 Aug 2017 10:24:58 -0000 On 11 August 2017 at 23:17, Alistair Francis wrote: > I found some issues with the way exclusive store was working. This patch > series seems to fix the test cases that were failing for me. > > The first patch is just a simple adjustment. > > The third patch fixes the main bug I was seeing. > > The second patch is left over from the RFC that seems like it is still a > good idea. > > Changes from RFC: > - Rewrite the third patch to correctly fix the issue. > > Alistair Francis (3): > target/arm: Update the memops for exclusive load > tcg/tcg-op: Expose the tcg_gen_ext_i* functions > target/arm: Correct exclusive store cmpxchg memop mask > > target/arm/translate-a64.c | 4 ++-- > tcg/tcg-op.c | 4 ++-- > tcg/tcg-op.h | 2 ++ > 3 files changed, 6 insertions(+), 4 deletions(-) Is this series (or at least patches 1 and 3) worth putting into 2.10 ? thanks -- PMM From MAILER-DAEMON Sat Aug 12 07:37:07 2017 Received: from list by lists.gnu.org with archive (Exim 4.71) id 1dgUj5-0005Hn-8w for mharc-qemu-arm@gnu.org; Sat, 12 Aug 2017 07:37:07 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:59826) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dgUj3-0005HP-2O for qemu-arm@nongnu.org; Sat, 12 Aug 2017 07:37:06 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dgUiy-0001IM-3X for qemu-arm@nongnu.org; Sat, 12 Aug 2017 07:37:05 -0400 Received: from mail-cys01nam02on0083.outbound.protection.outlook.com ([104.47.37.83]:30228 helo=NAM02-CY1-obe.outbound.protection.outlook.com) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1dgUix-0001Hh-Ik; Sat, 12 Aug 2017 07:37:00 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=xilinx.onmicrosoft.com; s=selector1-xilinx-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version; bh=HfbsY6vmf5f8umfQGo2nJzDB+Rom9e1cehZd1SIzTeE=; b=TVZ4t6uhYP72UgXJEyQ9a5yWA67BKBVsz+YTIq5AOW0lu8U+BEtYbew4lSmWgCfgNdFuCcD6npy/jNwDSUwly8qWejvASh9eHZvzkuorGMrdnN5mzcnQbEdHo2RL1PJYb8iH24zDotPE491o4bQis8y3z6yNhVIaLDK26QcDrn4= Received: from BLUPR0201CA0033.namprd02.prod.outlook.com (10.163.116.43) by MWHPR02MB2256.namprd02.prod.outlook.com (10.168.243.138) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1320.16; Sat, 12 Aug 2017 11:36:56 +0000 Received: from BL2NAM02FT039.eop-nam02.prod.protection.outlook.com (2a01:111:f400:7e46::206) by BLUPR0201CA0033.outlook.office365.com (2a01:111:e400:52e7::43) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1341.17 via Frontend Transport; Sat, 12 Aug 2017 11:36:55 +0000 Authentication-Results: spf=pass (sender IP is 149.199.60.100) smtp.mailfrom=xilinx.com; nongnu.org; dkim=none (message not signed) header.d=none;nongnu.org; dmarc=bestguesspass action=none header.from=xilinx.com; Received-SPF: Pass (protection.outlook.com: domain of xilinx.com designates 149.199.60.100 as permitted sender) receiver=protection.outlook.com; client-ip=149.199.60.100; helo=xsj-pvapsmtpgw02; Received: from xsj-pvapsmtpgw02 (149.199.60.100) by BL2NAM02FT039.mail.protection.outlook.com (10.152.77.152) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.1304.16 via Frontend Transport; Sat, 12 Aug 2017 11:36:55 +0000 Received: from unknown-38-66.xilinx.com ([149.199.38.66]:33139 helo=xsj-pvapsmtp01) by xsj-pvapsmtpgw02 with esmtp (Exim 4.63) (envelope-from ) id 1dgUis-0003MD-Hy; Sat, 12 Aug 2017 04:36:54 -0700 Received: from [127.0.0.1] (helo=localhost) by xsj-pvapsmtp01 with smtp (Exim 4.63) (envelope-from ) id 1dgUis-00022h-FO; Sat, 12 Aug 2017 04:36:54 -0700 Received: from xsj-pvapsmtp01 (smtp2.xilinx.com [149.199.38.66]) by xsj-smtp-dlp2.xlnx.xilinx.com (8.13.8/8.13.1) with ESMTP id v7CBakuf017487; Sat, 12 Aug 2017 04:36:46 -0700 Received: from [172.19.116.66] (helo=xsjedgari31.xlnx.xilinx.com) by xsj-pvapsmtp01 with esmtp (Exim 4.63) (envelope-from ) id 1dgUik-00022U-Bk; Sat, 12 Aug 2017 04:36:46 -0700 Date: Sat, 12 Aug 2017 13:36:45 +0200 From: "Edgar E. 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Ip=[149.199.60.100]; Helo=[xsj-pvapsmtpgw02] X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MWHPR02MB2256 X-detected-operating-system: by eggs.gnu.org: Windows 7 or 8 [fuzzy] X-Received-From: 104.47.37.83 Subject: Re: [Qemu-arm] [PATCH v1 3/3] target/arm: Correct exclusive store cmpxchg memop mask X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sat, 12 Aug 2017 11:37:06 -0000 On Fri, Aug 11, 2017 at 03:17:41PM -0700, Alistair Francis wrote: > When we perform the atomic_cmpxchg operation we want to perform the > operation on a pair of 32-bit registers. Previously we were just passing > the register size in which was set to MO_32. This would result in the > high register to be ignored. To fix this issue we hardcode the size to > be 64-bits long when operating on 32-bit pairs. Good catch Alistair! Reviewed-by: Edgar E. Iglesias > > Signed-off-by: Alistair Francis > --- > > This was caught with an internal fuzzy tester. These patches fix the > Xilinx 2.10-rc2 tree. I tested with the fuzzy tester (single CPU) and > Linux boot (4 CPUs) on the Xilinx tree. I don't have a good test case to > run on mainline, but am working with some internal teams to get one. > Also linux-user is fully untested. > > All tests were with MTTCG enabled. > > target/arm/translate-a64.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c > index 245175e2f1..49b4d6918d 100644 > --- a/target/arm/translate-a64.c > +++ b/target/arm/translate-a64.c > @@ -1913,7 +1913,7 @@ static void gen_store_exclusive(DisasContext *s, int rd, int rt, int rt2, > tcg_gen_concat32_i64(val, cpu_exclusive_val, cpu_exclusive_high); > tcg_gen_atomic_cmpxchg_i64(tmp, addr, val, tmp, > get_mem_index(s), > - size | MO_ALIGN | s->be_data); > + MO_64 | MO_ALIGN | s->be_data); > tcg_gen_setcond_i64(TCG_COND_NE, tmp, tmp, val); > tcg_temp_free_i64(val); > } else if (s->be_data == MO_LE) { > -- > 2.11.0 > From MAILER-DAEMON Sat Aug 12 07:38:45 2017 Received: from list by lists.gnu.org with archive (Exim 4.71) id 1dgUkf-0006Oh-OU for mharc-qemu-arm@gnu.org; Sat, 12 Aug 2017 07:38:45 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:60266) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dgUkd-0006MJ-JU for qemu-arm@nongnu.org; Sat, 12 Aug 2017 07:38:44 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dgUkZ-00024C-J5 for qemu-arm@nongnu.org; Sat, 12 Aug 2017 07:38:43 -0400 Received: from mail-co1nam03on0076.outbound.protection.outlook.com ([104.47.40.76]:53170 helo=NAM03-CO1-obe.outbound.protection.outlook.com) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1dgUkZ-00023O-87; Sat, 12 Aug 2017 07:38:39 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=xilinx.onmicrosoft.com; s=selector1-xilinx-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version; bh=WbLZGU+v0KIECz/U4rPJUko8dRWPmYK2FZSRnNhyAJU=; b=stJwkDmqw4vUO4UnBK0K8zs0Xg0T7bLpqCwvYzV8zWkk0eMu2s6Q9DcfgwV3FrDtPU+G2Cb43LlszSecbgixETIMctqF/u7F79KUFr7Ukt1rzSn13hvfijBbYNmFuMmE+5Tk32qbNvFlRuJWcxaKCJDdvwiMIWI+OZVQUagmU/A= Received: from CY1PR0201CA0034.namprd02.prod.outlook.com (10.163.30.172) by CY4PR02MB2248.namprd02.prod.outlook.com (10.169.181.13) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384_P256) id 15.1.1341.17; Sat, 12 Aug 2017 11:38:36 +0000 Received: from SN1NAM02FT011.eop-nam02.prod.protection.outlook.com (2a01:111:f400:7e44::207) by CY1PR0201CA0034.outlook.office365.com (2a01:111:e400:58b9::44) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384_P256) id 15.1.1341.17 via Frontend Transport; Sat, 12 Aug 2017 11:38:36 +0000 Authentication-Results: spf=pass (sender IP is 149.199.60.83) smtp.mailfrom=xilinx.com; nongnu.org; dkim=none (message not signed) header.d=none;nongnu.org; dmarc=bestguesspass action=none header.from=xilinx.com; Received-SPF: Pass (protection.outlook.com: domain of xilinx.com designates 149.199.60.83 as permitted sender) receiver=protection.outlook.com; client-ip=149.199.60.83; helo=xsj-pvapsmtpgw01; Received: from xsj-pvapsmtpgw01 (149.199.60.83) by SN1NAM02FT011.mail.protection.outlook.com (10.152.72.82) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.1304.16 via Frontend Transport; Sat, 12 Aug 2017 11:38:35 +0000 Received: from unknown-38-66.xilinx.com ([149.199.38.66] helo=xsj-pvapsmtp01) by xsj-pvapsmtpgw01 with esmtp (Exim 4.63) (envelope-from ) id 1dgUkU-0003hq-Vq; Sat, 12 Aug 2017 04:38:34 -0700 Received: from [127.0.0.1] (helo=localhost) by xsj-pvapsmtp01 with smtp (Exim 4.63) (envelope-from ) id 1dgUkU-0002C2-RM; Sat, 12 Aug 2017 04:38:34 -0700 Received: from xsj-pvapsmtp01 (smtp.xilinx.com [149.199.38.66]) by xsj-smtp-dlp2.xlnx.xilinx.com (8.13.8/8.13.1) with ESMTP id v7CBcRle017663; Sat, 12 Aug 2017 04:38:27 -0700 Received: from [172.19.116.66] (helo=xsjedgari31.xlnx.xilinx.com) by xsj-pvapsmtp01 with esmtp (Exim 4.63) (envelope-from ) id 1dgUkN-0002Bp-6g; Sat, 12 Aug 2017 04:38:27 -0700 Date: Sat, 12 Aug 2017 13:38:26 +0200 From: "Edgar E. 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Ip=[149.199.60.83]; Helo=[xsj-pvapsmtpgw01] X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY4PR02MB2248 X-detected-operating-system: by eggs.gnu.org: Windows 7 or 8 [fuzzy] X-Received-From: 104.47.40.76 Subject: Re: [Qemu-arm] [PATCH v1 1/3] target/arm: Update the memops for exclusive load X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sat, 12 Aug 2017 11:38:44 -0000 On Fri, Aug 11, 2017 at 03:17:36PM -0700, Alistair Francis wrote: > Acording to the ARM ARM exclusive loads require the same allignment as > exclusive stores. Let's update the memops used for the load to match > that of the store. This adds the alignment requirement to the memops. > > Signed-off-by: Alistair Francis > Reviewed-by: Richard Henderson Reviewed-by: Edgar E. Iglesias > --- > > target/arm/translate-a64.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c > index 58ed4c6d05..245175e2f1 100644 > --- a/target/arm/translate-a64.c > +++ b/target/arm/translate-a64.c > @@ -1854,7 +1854,7 @@ static void gen_load_exclusive(DisasContext *s, int rt, int rt2, > TCGv_i64 addr, int size, bool is_pair) > { > TCGv_i64 tmp = tcg_temp_new_i64(); > - TCGMemOp memop = s->be_data + size; > + TCGMemOp memop = size | MO_ALIGN | s->be_data; > > g_assert(size <= 3); > tcg_gen_qemu_ld_i64(tmp, addr, get_mem_index(s), memop); > -- > 2.11.0 > From MAILER-DAEMON Sat Aug 12 07:39:36 2017 Received: from list by lists.gnu.org with archive (Exim 4.71) id 1dgUlT-00071J-U3 for mharc-qemu-arm@gnu.org; Sat, 12 Aug 2017 07:39:35 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:60577) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dgUlR-0006zF-IW for qemu-arm@nongnu.org; Sat, 12 Aug 2017 07:39:34 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dgUlN-0002Th-Ha for qemu-arm@nongnu.org; Sat, 12 Aug 2017 07:39:33 -0400 Received: from mail-bl2nam02on0053.outbound.protection.outlook.com ([104.47.38.53]:59744 helo=NAM02-BL2-obe.outbound.protection.outlook.com) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1dgUlN-0002T4-Ai; Sat, 12 Aug 2017 07:39:29 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=xilinx.onmicrosoft.com; s=selector1-xilinx-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version; bh=HB0FeWw78sixWNuFoMYsx7xEKlp/wuTwfcu9UUJCAY8=; b=Yk8g4UH0XBVGsK9LA+/wCKXJ61Ai6RAMwOaTRRJNLMLG36Td17jzXsP5cRG8wL3W4M44jOYQt05fbLm32TK6Gyyiqas5GMTeP6v+zd1bymr+cwBJm05HZn5Q4/Bj9nNL9icP664j4sgTgMaNY708Yrl5UnMZuoN33M495qBGVQ4= Received: from BY2PR02CA0110.namprd02.prod.outlook.com (2a01:111:e400:5261::36) by DM2PR0201MB1056.namprd02.prod.outlook.com (2a01:111:e400:5021::25) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1320.16; Sat, 12 Aug 2017 11:39:26 +0000 Received: from BL2NAM02FT057.eop-nam02.prod.protection.outlook.com (2a01:111:f400:7e46::203) by BY2PR02CA0110.outlook.office365.com (2a01:111:e400:5261::36) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1341.17 via Frontend Transport; Sat, 12 Aug 2017 11:39:26 +0000 Authentication-Results: spf=pass (sender IP is 149.199.60.83) smtp.mailfrom=xilinx.com; nongnu.org; dkim=none (message not signed) header.d=none;nongnu.org; dmarc=bestguesspass action=none header.from=xilinx.com; Received-SPF: Pass (protection.outlook.com: domain of xilinx.com designates 149.199.60.83 as permitted sender) receiver=protection.outlook.com; client-ip=149.199.60.83; helo=xsj-pvapsmtpgw01; Received: from xsj-pvapsmtpgw01 (149.199.60.83) by BL2NAM02FT057.mail.protection.outlook.com (10.152.77.36) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.1304.16 via Frontend Transport; Sat, 12 Aug 2017 11:39:26 +0000 Received: from unknown-38-66.xilinx.com ([149.199.38.66] helo=xsj-pvapsmtp01) by xsj-pvapsmtpgw01 with esmtp (Exim 4.63) (envelope-from ) id 1dgUlJ-0003if-4p; Sat, 12 Aug 2017 04:39:25 -0700 Received: from [127.0.0.1] (helo=localhost) by xsj-pvapsmtp01 with smtp (Exim 4.63) (envelope-from ) id 1dgUlJ-0002Gl-2C; Sat, 12 Aug 2017 04:39:25 -0700 Received: from xsj-pvapsmtp01 (xsj-smtp1.xilinx.com [149.199.38.66]) by xsj-smtp-dlp1.xlnx.xilinx.com (8.13.8/8.13.1) with ESMTP id v7CBdF0C023115; Sat, 12 Aug 2017 04:39:16 -0700 Received: from [172.19.116.66] (helo=xsjedgari31.xlnx.xilinx.com) by xsj-pvapsmtp01 with esmtp (Exim 4.63) (envelope-from ) id 1dgUl9-0002GH-Ge; Sat, 12 Aug 2017 04:39:15 -0700 Date: Sat, 12 Aug 2017 13:39:14 +0200 From: "Edgar E. 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Ip=[149.199.60.83]; Helo=[xsj-pvapsmtpgw01] X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM2PR0201MB1056 X-detected-operating-system: by eggs.gnu.org: Windows 7 or 8 [fuzzy] X-Received-From: 104.47.38.53 Subject: Re: [Qemu-arm] [PATCH v1 2/3] tcg/tcg-op: Expose the tcg_gen_ext_i* functions X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sat, 12 Aug 2017 11:39:35 -0000 On Fri, Aug 11, 2017 at 03:17:38PM -0700, Alistair Francis wrote: > Expose the tcg_gen_ext_i32() and tcg_gen_ext_i64() functions. > > Signed-off-by: Alistair Francis > Reviewed-by: Richard Henderson Reviewed-by: Edgar E. Iglesias > --- > > Although I no longer am using these functions I have left this patch in > as Richard thought it was a good idea. > > tcg/tcg-op.c | 4 ++-- > tcg/tcg-op.h | 2 ++ > 2 files changed, 4 insertions(+), 2 deletions(-) > > diff --git a/tcg/tcg-op.c b/tcg/tcg-op.c > index 87f673ef49..d25e3003ef 100644 > --- a/tcg/tcg-op.c > +++ b/tcg/tcg-op.c > @@ -2709,7 +2709,7 @@ void tcg_gen_qemu_st_i64(TCGv_i64 val, TCGv addr, TCGArg idx, TCGMemOp memop) > gen_ldst_i64(INDEX_op_qemu_st_i64, val, addr, memop, idx); > } > > -static void tcg_gen_ext_i32(TCGv_i32 ret, TCGv_i32 val, TCGMemOp opc) > +void tcg_gen_ext_i32(TCGv_i32 ret, TCGv_i32 val, TCGMemOp opc) > { > switch (opc & MO_SSIZE) { > case MO_SB: > @@ -2730,7 +2730,7 @@ static void tcg_gen_ext_i32(TCGv_i32 ret, TCGv_i32 val, TCGMemOp opc) > } > } > > -static void tcg_gen_ext_i64(TCGv_i64 ret, TCGv_i64 val, TCGMemOp opc) > +void tcg_gen_ext_i64(TCGv_i64 ret, TCGv_i64 val, TCGMemOp opc) > { > switch (opc & MO_SSIZE) { > case MO_SB: > diff --git a/tcg/tcg-op.h b/tcg/tcg-op.h > index 5d3278f243..8c45b79a92 100644 > --- a/tcg/tcg-op.h > +++ b/tcg/tcg-op.h > @@ -835,6 +835,8 @@ void tcg_gen_qemu_ld_i32(TCGv_i32, TCGv, TCGArg, TCGMemOp); > void tcg_gen_qemu_st_i32(TCGv_i32, TCGv, TCGArg, TCGMemOp); > void tcg_gen_qemu_ld_i64(TCGv_i64, TCGv, TCGArg, TCGMemOp); > void tcg_gen_qemu_st_i64(TCGv_i64, TCGv, TCGArg, TCGMemOp); > +void tcg_gen_ext_i32(TCGv_i32 ret, TCGv_i32 val, TCGMemOp opc); > +void tcg_gen_ext_i64(TCGv_i64 ret, TCGv_i64 val, TCGMemOp opc); > > static inline void tcg_gen_qemu_ld8u(TCGv ret, TCGv addr, int mem_index) > { > -- > 2.11.0 > From MAILER-DAEMON Sat Aug 12 07:43:25 2017 Received: from list by lists.gnu.org with archive (Exim 4.71) id 1dgUpB-0001UA-Cy for mharc-qemu-arm@gnu.org; Sat, 12 Aug 2017 07:43:25 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:33347) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dgUp9-0001Tu-Bz for qemu-arm@nongnu.org; Sat, 12 Aug 2017 07:43:24 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dgUp5-0004It-CN for qemu-arm@nongnu.org; Sat, 12 Aug 2017 07:43:23 -0400 Received: from mail-dm3nam03on0064.outbound.protection.outlook.com ([104.47.41.64]:22112 helo=NAM03-DM3-obe.outbound.protection.outlook.com) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1dgUp5-0004IT-3c; Sat, 12 Aug 2017 07:43:19 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=xilinx.onmicrosoft.com; s=selector1-xilinx-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version; bh=owQ0+GnmVoQgoyYNlZeh4mt/L4YuLxsonjqI+m/nBdw=; b=ZY/PfRvYcWzpLcqdcAwaQSI5nAGGxL7Vj82o4PAtAviLR3qw+oRbD8oZQRmCXTALG1SNJrQJoK3JOahUL/ix1/XeQx9XoIO9UV0gJTItKsgi4LnaLInqZngSyqVejzAWPXr1ilZodebtuDNskve4ti3gYoNlmyieOVgbPixC3m0= Received: from MWHPR0201CA0023.namprd02.prod.outlook.com (2603:10b6:301:74::36) by DM2PR0201MB1053.namprd02.prod.outlook.com (2a01:111:e400:5021::22) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384_P256) id 15.1.1320.16; Sat, 12 Aug 2017 11:42:57 +0000 Received: from BL2NAM02FT035.eop-nam02.prod.protection.outlook.com (2a01:111:f400:7e46::207) by MWHPR0201CA0023.outlook.office365.com (2603:10b6:301:74::36) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384_P256) id 15.1.1341.17 via Frontend Transport; Sat, 12 Aug 2017 11:42:57 +0000 Authentication-Results: spf=pass (sender IP is 149.199.60.100) smtp.mailfrom=xilinx.com; nongnu.org; dkim=none (message not signed) header.d=none;nongnu.org; dmarc=bestguesspass action=none header.from=xilinx.com; Received-SPF: Pass (protection.outlook.com: domain of xilinx.com designates 149.199.60.100 as permitted sender) receiver=protection.outlook.com; client-ip=149.199.60.100; helo=xsj-pvapsmtpgw02; Received: from xsj-pvapsmtpgw02 (149.199.60.100) by BL2NAM02FT035.mail.protection.outlook.com (10.152.77.157) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.1304.16 via Frontend Transport; Sat, 12 Aug 2017 11:42:56 +0000 Received: from unknown-38-66.xilinx.com ([149.199.38.66]:36004 helo=xsj-pvapsmtp01) by xsj-pvapsmtpgw02 with esmtp (Exim 4.63) (envelope-from ) id 1dgUoh-0003OC-N1; Sat, 12 Aug 2017 04:42:55 -0700 Received: from [127.0.0.1] (helo=localhost) by xsj-pvapsmtp01 with smtp (Exim 4.63) (envelope-from ) id 1dgUoh-0002jY-Jf; Sat, 12 Aug 2017 04:42:55 -0700 Received: from xsj-pvapsmtp01 (smtp.xilinx.com [149.199.38.66]) by xsj-smtp-dlp1.xlnx.xilinx.com (8.13.8/8.13.1) with ESMTP id v7CBgjLL023602; Sat, 12 Aug 2017 04:42:45 -0700 Received: from [172.19.116.66] (helo=xsjedgari31.xlnx.xilinx.com) by xsj-pvapsmtp01 with esmtp (Exim 4.63) (envelope-from ) id 1dgUoW-0002iA-Rs; Sat, 12 Aug 2017 04:42:45 -0700 Date: Sat, 12 Aug 2017 13:42:43 +0200 From: "Edgar E. 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Ip=[149.199.60.100]; Helo=[xsj-pvapsmtpgw02] X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM2PR0201MB1053 X-detected-operating-system: by eggs.gnu.org: Windows 7 or 8 [fuzzy] X-Received-From: 104.47.41.64 Subject: Re: [Qemu-arm] [PATCH v1 0/3] Fixup exclusive store logic X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sat, 12 Aug 2017 11:43:24 -0000 On Sat, Aug 12, 2017 at 11:24:30AM +0100, Peter Maydell wrote: > On 11 August 2017 at 23:17, Alistair Francis > wrote: > > I found some issues with the way exclusive store was working. This patch > > series seems to fix the test cases that were failing for me. > > > > The first patch is just a simple adjustment. > > > > The third patch fixes the main bug I was seeing. > > > > The second patch is left over from the RFC that seems like it is still a > > good idea. > > > > Changes from RFC: > > - Rewrite the third patch to correctly fix the issue. > > > > Alistair Francis (3): > > target/arm: Update the memops for exclusive load > > tcg/tcg-op: Expose the tcg_gen_ext_i* functions > > target/arm: Correct exclusive store cmpxchg memop mask > > > > target/arm/translate-a64.c | 4 ++-- > > tcg/tcg-op.c | 4 ++-- > > tcg/tcg-op.h | 2 ++ > > 3 files changed, 6 insertions(+), 4 deletions(-) > > Is this series (or at least patches 1 and 3) worth putting > into 2.10 ? I would vote for including it... Cheers, Edgar From MAILER-DAEMON Sat Aug 12 09:39:27 2017 Received: from list by lists.gnu.org with archive (Exim 4.71) id 1dgWdT-0000zQ-Lk for mharc-qemu-arm@gnu.org; Sat, 12 Aug 2017 09:39:27 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:51217) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dgVkx-0006q5-Jt for Qemu-arm@nongnu.org; Sat, 12 Aug 2017 08:43:08 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dgVkw-0001Ny-Dx for Qemu-arm@nongnu.org; Sat, 12 Aug 2017 08:43:07 -0400 Received: from mail-qk0-x231.google.com ([2607:f8b0:400d:c09::231]:32950) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1dgVkw-0001Nb-8N for Qemu-arm@nongnu.org; Sat, 12 Aug 2017 08:43:06 -0400 Received: by mail-qk0-x231.google.com with SMTP id a77so32454632qkb.0 for ; Sat, 12 Aug 2017 05:43:04 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=mime-version:from:date:message-id:subject:to; bh=sdGep+UrjQYFz7T/UR/0vg5c/iWjSzRjK99QBmL2ICc=; b=YtNr5VqSS/KEcl5NAg4C8HUACKdN6gPrz09zBL7tzsJmmpW0tX9uVKknpzfbfDPc9P 0e8u7YDJmQWr8Gci2/VayI6DYnT1NrVVzb1u/cogRMEwhER6tV7PxhZOnPxoo8b4mQ8h kE/++YxL1rg+uqpF2rb4rOmkNvXY1P4e7MQ9VKxeA0+N0jLhcudMSQ7suuXB+0nrf0CP 6SbSG21C2SG2R0X3fdl++DaK7FZFUH9QYnYMNXcWAe6VYoujgtODpvvKoliAp5eGn2go 9qV2/k2vSRai2+jwY2P5uHJuveVTdFzKxM0yFqeN17lCglEB4VmfUFpORhDtW4NRUBGt Sz8w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:from:date:message-id:subject:to; bh=sdGep+UrjQYFz7T/UR/0vg5c/iWjSzRjK99QBmL2ICc=; b=Dvc17hzTWwDXALW/vHtBhOuzhq8+kOWDqILK6o86eLHw094BtzRMXudkMnKvTeAexL uku5vq+H497fGfIyiaRJSusHubRXmvjzhaoT8J6oodyuOQ1I81C6GEdmRJ51YfIm446s qslD9FIpr66+oR8+DRilbpKMz0E0ePcOfq2mYNPHTLK34PXhg5rRIpZw1UlHjto81kz3 j9B54nxhFugpqpn2d3RGGtyz3+X77T5IxuGlwz+a7Xs93TNRBUtNojwLNqQrazE9PsiE xIGH7gbvvJzY0zhilV3m0dsK/l0mu4DF8htYKYS4g4uLtXC19KgYYXOdZwuILKCG+C8V TT1w== X-Gm-Message-State: AHYfb5gKHM1Tfd1i69TFykKEwGYAXVAZZDGT8Z87CyCPGcIQq3co5oLn SC3MVxFzWefN3xA/yYuY70nC998qQ+69 X-Received: by 10.55.157.135 with SMTP id g129mr25146358qke.241.1502541783699; Sat, 12 Aug 2017 05:43:03 -0700 (PDT) MIME-Version: 1.0 Received: by 10.237.34.174 with HTTP; Sat, 12 Aug 2017 05:43:03 -0700 (PDT) From: Ismi Abidi Date: Sat, 12 Aug 2017 18:13:03 +0530 Message-ID: To: Qemu-arm@nongnu.org Content-Type: multipart/alternative; boundary="94eb2c0654c847171a05568dc5a7" X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400d:c09::231 X-Mailman-Approved-At: Sat, 12 Aug 2017 09:39:25 -0400 Subject: [Qemu-arm] Instruction trace for ARM X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sat, 12 Aug 2017 12:43:08 -0000 --94eb2c0654c847171a05568dc5a7 Content-Type: text/plain; charset="UTF-8" Hi, I would like to generate an instruction trace for ARM architecture having instruction code with its parameters and the instruction address. I am new to Qemu so can anybody give me some pointers from where should I start. The patch link given in thread https://lists.gnu.org/archive/html/qemu-devel/2008-04/msg00038.html is dead. Thanks, Abidi --94eb2c0654c847171a05568dc5a7 Content-Type: text/html; charset="UTF-8" Content-Transfer-Encoding: quoted-printable
Hi,

I would like to generate a= n instruction trace for ARM architecture having instruction code with its p= arameters and the instruction address. I am new to Qemu so can anybody give= me some pointers from where should I start. The patch link given in thread= https://lists.gnu.org/archive/html/qemu-devel/2008-04/msg00038.html is dead.

Thanks,
--94eb2c0654c847171a05568dc5a7-- From MAILER-DAEMON Sat Aug 12 09:52:41 2017 Received: from list by lists.gnu.org with archive (Exim 4.71) id 1dgWqH-0005V5-4A for mharc-qemu-arm@gnu.org; Sat, 12 Aug 2017 09:52:41 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:42799) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dgWqE-0005Sm-4H for qemu-arm@nongnu.org; Sat, 12 Aug 2017 09:52:39 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dgWqC-0002pV-V1 for qemu-arm@nongnu.org; Sat, 12 Aug 2017 09:52:38 -0400 Received: from mail-wm0-x241.google.com ([2a00:1450:400c:c09::241]:35775) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1dgWqA-0002m7-4q; Sat, 12 Aug 2017 09:52:34 -0400 Received: by mail-wm0-x241.google.com with SMTP id r77so9415551wmd.2; Sat, 12 Aug 2017 06:52:33 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=mime-version:in-reply-to:references:from:date:message-id:subject:to :cc; bh=zxXLTU/jL9zeVXIW2YxsKz93z4OfwBoQeW4A3Xyy//E=; b=IsPQ50mHJ+zrdDh/fd/q7fH37av9MicXCCy1mTbTz7emmTbCknrlgmovWXkXQBu0Lb 6XQZLZUPzlHP2rEsP9nvK52/5wNGrWJ7OpTWMaZ0IVxuVhKvTdmZKDC1k3hO3YlhxYDJ iTqv20+5FRojc4uZf8iU6wIMCAI3jVUavW5HHpwAvyva4eWyc+c41JPx6njIE0qjS8EV XTCfM2TdC0uIkTYGtxcWf3kppTOK/okKE4poBHWOdw+bvA21/2uFNH0BNXxjbKtsnk4e PQCLd+3dgSzO782w7NjornhFMx45DHb7fPuYASVqnosqwQAlAS7K/1e5mP2r8bBuWuW5 ntaQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:in-reply-to:references:from:date :message-id:subject:to:cc; bh=zxXLTU/jL9zeVXIW2YxsKz93z4OfwBoQeW4A3Xyy//E=; b=H1dGSmDo6dEARAuu6NO8f6iCWRO4zKeIHgUBQWSHJGFF33+3A4be7AjIF2r4Mg6vRI nq3EMk9QOMLI35T848l3tSVaGXQTLpuy1qSy2d2fnUXidzOsWaaueR1oDtqB7JQR3mGb A+ne3iZ0o68kTgd3iyobsUptuSaB0P8+knCRdszZJyFgqAQK4tFqZuo9MxPSybiBgEzV l1lDgYSMqpOEZ7P+ccCja+mGWt0QjtkMO4Hxvt9cs7lVTnDQbNXBoywPOWKtOw0buuUz BXeajG2BHObKSV1CoK+rzboQjRKt1+NhqexGl0ghrCSC7M6i8gLVLjmTKEvSzvSF6deG FGjw== X-Gm-Message-State: AHYfb5hiLbQZRTbsMXPy9d9eC9nSTcSuySLRm25OMaHp8828pe1FribE UvX6wE9zZBeGd2QHSebbpexLipyThw== X-Received: by 10.28.207.10 with SMTP id f10mr1050476wmg.159.1502545952948; Sat, 12 Aug 2017 06:52:32 -0700 (PDT) MIME-Version: 1.0 Received: by 10.28.191.130 with HTTP; Sat, 12 Aug 2017 06:52:02 -0700 (PDT) In-Reply-To: <20170812114243.GZ12347@toto> References: <20170812114243.GZ12347@toto> From: Alistair Francis Date: Sat, 12 Aug 2017 06:52:02 -0700 Message-ID: To: "Edgar E. Iglesias" Cc: Peter Maydell , Alistair Francis , QEMU Developers , "Edgar E. Iglesias" , qemu-arm Content-Type: text/plain; charset="UTF-8" X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:400c:c09::241 Subject: Re: [Qemu-arm] [PATCH v1 0/3] Fixup exclusive store logic X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sat, 12 Aug 2017 13:52:39 -0000 On Sat, Aug 12, 2017 at 4:42 AM, Edgar E. Iglesias wrote: > On Sat, Aug 12, 2017 at 11:24:30AM +0100, Peter Maydell wrote: >> On 11 August 2017 at 23:17, Alistair Francis >> wrote: >> > I found some issues with the way exclusive store was working. This patch >> > series seems to fix the test cases that were failing for me. >> > >> > The first patch is just a simple adjustment. >> > >> > The third patch fixes the main bug I was seeing. >> > >> > The second patch is left over from the RFC that seems like it is still a >> > good idea. >> > >> > Changes from RFC: >> > - Rewrite the third patch to correctly fix the issue. >> > >> > Alistair Francis (3): >> > target/arm: Update the memops for exclusive load >> > tcg/tcg-op: Expose the tcg_gen_ext_i* functions >> > target/arm: Correct exclusive store cmpxchg memop mask >> > >> > target/arm/translate-a64.c | 4 ++-- >> > tcg/tcg-op.c | 4 ++-- >> > tcg/tcg-op.h | 2 ++ >> > 3 files changed, 6 insertions(+), 4 deletions(-) >> >> Is this series (or at least patches 1 and 3) worth putting >> into 2.10 ? > > > I would vote for including it... The only reason not to is because this bug has been in QEMU for a while, so it obviously isn't hit very often. In saying that it is a pretty big issue (32-bit pair stores are completely broken) which might become an issue during the 2.10 support window and I don't see many complications from including the series. I agree with Edgar, probably worth including. Thanks, Alistair > > Cheers, > Edgar From MAILER-DAEMON Sat Aug 12 11:02:02 2017 Received: from list by lists.gnu.org with archive (Exim 4.71) id 1dgXvO-0003d3-T5 for mharc-qemu-arm@gnu.org; Sat, 12 Aug 2017 11:02:02 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:59557) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dgXvM-0003cb-Mk for qemu-arm@nongnu.org; Sat, 12 Aug 2017 11:02:02 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dgXvI-0005Zf-2j for qemu-arm@nongnu.org; Sat, 12 Aug 2017 11:02:00 -0400 Received: from mail-pf0-x229.google.com ([2607:f8b0:400e:c00::229]:34308) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1dgXvH-0005Z9-QO for qemu-arm@nongnu.org; Sat, 12 Aug 2017 11:01:55 -0400 Received: by mail-pf0-x229.google.com with SMTP id o86so26450453pfj.1 for ; Sat, 12 Aug 2017 08:01:54 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=subject:to:cc:references:from:message-id:date:user-agent :mime-version:in-reply-to:content-language:content-transfer-encoding; bh=SzsO6xKjoLv/GZNVCAo2NbcJipTyUYgxDb1PhmGc6m0=; b=FjNuOMIfkFONeTXrhBYRmtqIRfT9+xuqkEJdk3DAtBENEWTJsTKIUegZswNf0McKti SpU+TM/8NDh+O3XVMcSLAtgr+GwCuQtvqBVR9KVu+aXU56PHvTKGGeewUbkflvsvSeTv hTlCxi44r9qAiaqUeMvkGGJmvldJuqJP6P6uw= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:subject:to:cc:references:from:message-id:date :user-agent:mime-version:in-reply-to:content-language :content-transfer-encoding; bh=SzsO6xKjoLv/GZNVCAo2NbcJipTyUYgxDb1PhmGc6m0=; b=nvu9sCOVs/WIH4p6rU1Bu6mNEL9bG/YhpWLMEyEP3Finb7bnf7ai1Ci8fWI0bJVQwT CSSUBoD/83RHTd7Yc0wAGRm/FcKR+wXKLshztdH1Ey7ect+PUDHyMp8Xh+zGP/uaUwrO z+8Y/AWSCfvwyB4GAln73Iq3hLntm/xONnaBkGNJBL4aiKjHKBwO3RF3D0tZtNBvSVnh VWinPo7Y40oX8dUubB6UNm61neYYGDQJTZM8FuEbCNKo4z35GN959qa5pEJ8kOL6ksUW QLoQUK7wnxjwrcJfnE8JNQd4o5U6hyAKavERwfgKyuh+reB6WhMuc03cox/7/yJKuw01 L5sA== X-Gm-Message-State: AHYfb5g9wVDmO9Asy7YmRQHN73n61nQ/r9M1LrRt2ZdM5yTSo62eUCOE XaLdeb89xd0XuDRr X-Received: by 10.84.248.69 with SMTP id e5mr21856252pln.38.1502550113033; Sat, 12 Aug 2017 08:01:53 -0700 (PDT) Received: from bigtime.twiddle.net (50-233-235-3-static.hfc.comcastbusiness.net. [50.233.235.3]) by smtp.gmail.com with ESMTPSA id y25sm7108429pfk.162.2017.08.12.08.01.50 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sat, 12 Aug 2017 08:01:52 -0700 (PDT) To: Alistair Francis , qemu-devel@nongnu.org, peter.maydell@linaro.org Cc: edgar.iglesias@xilinx.com, alistair23@gmail.com, qemu-arm@nongnu.org, edgar.iglesias@gmail.com References: From: Richard Henderson Message-ID: Date: Sat, 12 Aug 2017 08:01:48 -0700 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.2.1 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 7bit X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::229 Subject: Re: [Qemu-arm] [Qemu-devel] [PATCH v1 3/3] target/arm: Correct exclusive store cmpxchg memop mask X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sat, 12 Aug 2017 15:02:02 -0000 On 08/11/2017 03:17 PM, Alistair Francis wrote: > When we perform the atomic_cmpxchg operation we want to perform the > operation on a pair of 32-bit registers. Previously we were just passing > the register size in which was set to MO_32. This would result in the > high register to be ignored. To fix this issue we hardcode the size to > be 64-bits long when operating on 32-bit pairs. > > Signed-off-by: Alistair Francis > --- > > This was caught with an internal fuzzy tester. These patches fix the > Xilinx 2.10-rc2 tree. I tested with the fuzzy tester (single CPU) and > Linux boot (4 CPUs) on the Xilinx tree. I don't have a good test case to > run on mainline, but am working with some internal teams to get one. > Also linux-user is fully untested. > > All tests were with MTTCG enabled. > > target/arm/translate-a64.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c > index 245175e2f1..49b4d6918d 100644 > --- a/target/arm/translate-a64.c > +++ b/target/arm/translate-a64.c > @@ -1913,7 +1913,7 @@ static void gen_store_exclusive(DisasContext *s, int rd, int rt, int rt2, > tcg_gen_concat32_i64(val, cpu_exclusive_val, cpu_exclusive_high); > tcg_gen_atomic_cmpxchg_i64(tmp, addr, val, tmp, > get_mem_index(s), > - size | MO_ALIGN | s->be_data); > + MO_64 | MO_ALIGN | s->be_data); > tcg_gen_setcond_i64(TCG_COND_NE, tmp, tmp, val); > tcg_temp_free_i64(val); > } else if (s->be_data == MO_LE) { > Reading the ARM pseudocode again, especially wrt SetExclusiveMonitors, I think there are other bugs here wrt 32-bit LDXP/STXP. Since SetExclusiveMonitors is invoked only with address + dsize, one should be able to write ldxp w0, w1, [x5] stxr w3, x2, [x5] or ldxr x0, [x5] stxp w3, w1, w2, [x5] However, the LDXR and LDXP above do not store the cpu_exclusive_* metadata in the same format. Fixing this is simply a matter of ignoring cpu_exclusive_high for 32-bit pair operations and store it all in cpu_exclusive_val, as the 64-bit single-register operation does. In addition, 32-bit LDXP must be single-copy atomic, and we're issuing 2 loads, this is trivially fixed with the rest of the required changes, but perhaps worth noting. I'll post a patch shortly. r~ From MAILER-DAEMON Sat Aug 12 12:30:27 2017 Received: from list by lists.gnu.org with archive (Exim 4.71) id 1dgZIw-0000vc-RK for mharc-qemu-arm@gnu.org; Sat, 12 Aug 2017 12:30:26 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:59670) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dgZIu-0000qp-6o for qemu-arm@nongnu.org; Sat, 12 Aug 2017 12:30:25 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dgZIs-0008BW-NU for qemu-arm@nongnu.org; Sat, 12 Aug 2017 12:30:24 -0400 Received: from mail-wm0-x241.google.com ([2a00:1450:400c:c09::241]:37924) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1dgZIp-0008Ae-Fl; Sat, 12 Aug 2017 12:30:19 -0400 Received: by mail-wm0-x241.google.com with SMTP id y206so9694360wmd.5; Sat, 12 Aug 2017 09:30:19 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=mime-version:sender:in-reply-to:references:from:date:message-id :subject:to:cc; bh=AOVERSA4r3M9ySyrY0zlq4kCYWIO+zt/3MXGyT7ep/I=; b=Egu2IjSlocH8QIX5QKvJwoE9FL6QMKolNJC6aEhaoJWa/UihHD3j1efRas8xc/sUT9 r6P/Agm6RTLek1OhprM4lV9wgUFDEs7SWn6+nGUwwH2oBXKcGIdifpAy3nH9oUceXgV9 NdLQ6+CMAfQvgXHsAi9SK8dTRaV2k9DXPxE06xyF+1SyblluXZ2VGl50icHCaTKH7IP7 ja8CxofLIbT0zx+MquW/AB3h0d44hRaeyQCMziVF7cc3wzyQjYLLGQsLVkxH9TrxZL2A ib7A2gsR5omMTw7NQH2H+GB+2K2WKfY+It6rlOEjnOGXBA20MBfZYD11uRK0oTDaoSxN KosQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:sender:in-reply-to:references:from :date:message-id:subject:to:cc; bh=AOVERSA4r3M9ySyrY0zlq4kCYWIO+zt/3MXGyT7ep/I=; b=rLuTs70lZOrxJVZ9jPFsrqpAsFGnRBgEx4EwCW6qWkEOwUcBuuHFfCTXwYtxSttYKy jesl688dDWJ3ANi7AoeWHD3CtJN499aGXXM0ti4diebx0uajpwONiNFNgPUf5yQfG7i4 3p8I9qxISnELMnWT+aAntwVFGZxU74vEBREjp/Sg7FjrS+gWmhuspPD0XRwK2565qg0K X6JTW+/LLPHg4SM8R0W9JZ9lNSzBkm1XsJmDLuO3mr3EqXwUjjEp7EUEvkdKnLa3oXO1 BU1hSg/plMliDz3z5oWZmuTxJIKdfLR3XKX9cS1evzRgtanFy+pkKc6EkZEOwxe0UKdy jw0Q== X-Gm-Message-State: AHYfb5j98FvbmIW2k1Fkl37NjqmWfzfJKaJxGDUj47IB7WO7wNvUMB7o UBO234rCYWCKytQyNBxHCEXHjDeAGg== X-Received: by 10.28.54.67 with SMTP id d64mr1319448wma.135.1502555418143; Sat, 12 Aug 2017 09:30:18 -0700 (PDT) MIME-Version: 1.0 Sender: alistair23@gmail.com Received: by 10.28.191.130 with HTTP; Sat, 12 Aug 2017 09:29:47 -0700 (PDT) In-Reply-To: <20170812154131.29372-1-richard.henderson@linaro.org> References: <20170812154131.29372-1-richard.henderson@linaro.org> From: Alistair Francis Date: Sat, 12 Aug 2017 09:29:47 -0700 X-Google-Sender-Auth: Y_T4zaulWyfzwEE3gos7ysBYUys Message-ID: To: Richard Henderson Cc: "qemu-devel@nongnu.org Developers" , Edgar Iglesias , Peter Maydell , qemu-arm , Alistair Francis Content-Type: text/plain; charset="UTF-8" X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:400c:c09::241 Subject: Re: [Qemu-arm] [Qemu-devel] [PATCH] target/arm: Correct load/store exclusive pairing and alignment X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sat, 12 Aug 2017 16:30:25 -0000 On Sat, Aug 12, 2017 at 8:41 AM, Richard Henderson wrote: > SetExclusiveMonitors in the pseudocode is on the address + width, > and says nothing about the manner of the load. Therefore > > ldxp w0, w1, [x2] > vs > ldxr x0, [x2] > > must record the same metadata so that either may pair with > > stxp w3, w0, w1, [x2] > vs > stxr w3, x0, [x2] > > Fix this by ignoring cpu_exclusive_high except for 64-bit LDXP/STXP. > > Also note that we were not providing the required single-copy atomic > semantics for 32-bit LDXP. This is trivially fixed alongside the > cpu_exclusive_val change. > > At the same time, exclusive loads require the same alignment as > exclusive stores. For 64-bit LDXP, this means adding MO_ALIGN_16; > for the others adding MO_ALIGN. > > Reported-by: Alistair Francis > Signed-off-by: Richard Henderson > --- > target/arm/translate-a64.c | 65 +++++++++++++++++++++++++++++----------------- > 1 file changed, 41 insertions(+), 24 deletions(-) > --- > > I have not yet constructed test cases for all of the combinations > listed above. I wanted to put this into your hands so that you could > test against your existing code using LDXP/STXP. I can test it on Monday when I'm back in the office. I'll let you know what I find. > > > r~ > > > diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c > index 58ed4c6d05..f3643ac8dc 100644 > --- a/target/arm/translate-a64.c > +++ b/target/arm/translate-a64.c > @@ -1853,29 +1853,45 @@ static void disas_b_exc_sys(DisasContext *s, uint32_t insn) > static void gen_load_exclusive(DisasContext *s, int rt, int rt2, > TCGv_i64 addr, int size, bool is_pair) > { > - TCGv_i64 tmp = tcg_temp_new_i64(); > - TCGMemOp memop = s->be_data + size; > + int idx = get_mem_index(s); > + TCGMemOp memop = s->be_data; > > g_assert(size <= 3); > - tcg_gen_qemu_ld_i64(tmp, addr, get_mem_index(s), memop); > - > if (is_pair) { > - TCGv_i64 addr2 = tcg_temp_new_i64(); > - TCGv_i64 hitmp = tcg_temp_new_i64(); > - > g_assert(size >= 2); > - tcg_gen_addi_i64(addr2, addr, 1 << size); > - tcg_gen_qemu_ld_i64(hitmp, addr2, get_mem_index(s), memop); > - tcg_temp_free_i64(addr2); > - tcg_gen_mov_i64(cpu_exclusive_high, hitmp); > - tcg_gen_mov_i64(cpu_reg(s, rt2), hitmp); > - tcg_temp_free_i64(hitmp); > - } > + if (size == 2) { > + /* The pair must be single-copy atomic for the doubleword. */ > + memop |= MO_64 | MO_ALIGN; > + tcg_gen_qemu_ld_i64(cpu_exclusive_val, addr, idx, memop); > + if (s->be_data == MO_LE) { > + tcg_gen_extract_i64(cpu_reg(s, rt), cpu_exclusive_val, 0, 32); > + tcg_gen_extract_i64(cpu_reg(s, rt2), cpu_exclusive_val, 32, 32); > + } else { > + tcg_gen_extract_i64(cpu_reg(s, rt), cpu_exclusive_val, 32, 32); > + tcg_gen_extract_i64(cpu_reg(s, rt2), cpu_exclusive_val, 0, 32); > + } > + } else { > + /* The pair must be single-copy atomic for *each* doubleword, > + but not the entire quadword. It must, however, be aligned. */ > + TCGv_i64 addr2; > > - tcg_gen_mov_i64(cpu_exclusive_val, tmp); > - tcg_gen_mov_i64(cpu_reg(s, rt), tmp); > + memop |= MO_64; > + tcg_gen_qemu_ld_i64(cpu_exclusive_val, addr, idx, > + memop | MO_ALIGN_16); > > - tcg_temp_free_i64(tmp); > + addr2 = tcg_temp_new_i64(); > + tcg_gen_addi_i64(addr2, addr, 8); > + tcg_gen_qemu_ld_i64(cpu_exclusive_high, addr2, idx, memop); > + tcg_temp_free_i64(addr2); > + > + tcg_gen_mov_i64(cpu_reg(s, rt), cpu_exclusive_val); > + tcg_gen_mov_i64(cpu_reg(s, rt2), cpu_exclusive_high); > + } > + } else { > + memop |= size | MO_ALIGN; > + tcg_gen_qemu_ld_i64(cpu_exclusive_val, addr, idx, memop); > + tcg_gen_mov_i64(cpu_reg(s, rt), cpu_exclusive_val); > + } > tcg_gen_mov_i64(cpu_exclusive_addr, addr); > } > > @@ -1908,14 +1924,15 @@ static void gen_store_exclusive(DisasContext *s, int rd, int rt, int rt2, > tmp = tcg_temp_new_i64(); > if (is_pair) { > if (size == 2) { > - TCGv_i64 val = tcg_temp_new_i64(); > - tcg_gen_concat32_i64(tmp, cpu_reg(s, rt), cpu_reg(s, rt2)); > - tcg_gen_concat32_i64(val, cpu_exclusive_val, cpu_exclusive_high); > - tcg_gen_atomic_cmpxchg_i64(tmp, addr, val, tmp, > + if (s->be_data == MO_LE) { > + tcg_gen_concat32_i64(tmp, cpu_reg(s, rt), cpu_reg(s, rt2)); > + } else { > + tcg_gen_concat32_i64(tmp, cpu_reg(s, rt2), cpu_reg(s, rt)); > + } > + tcg_gen_atomic_cmpxchg_i64(tmp, addr, cpu_exclusive_val, tmp, > get_mem_index(s), > - size | MO_ALIGN | s->be_data); > - tcg_gen_setcond_i64(TCG_COND_NE, tmp, tmp, val); > - tcg_temp_free_i64(val); > + MO_64 | MO_ALIGN | s->be_data); > + tcg_gen_setcond_i64(TCG_COND_NE, tmp, tmp, cpu_exclusive_val); Now we aren't ever checking cpu_exclusive_high. Is it even worth having? Otherwise the patch looks good, let me test it next week and I'll get back to you. Thanks, Alistair > } else if (s->be_data == MO_LE) { > gen_helper_paired_cmpxchg64_le(tmp, cpu_env, addr, cpu_reg(s, rt), > cpu_reg(s, rt2)); > -- > 2.13.4 > > From MAILER-DAEMON Sat Aug 12 12:41:47 2017 Received: from list by lists.gnu.org with archive (Exim 4.71) id 1dgZTv-00057l-He for mharc-qemu-arm@gnu.org; Sat, 12 Aug 2017 12:41:47 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:37065) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dgZTt-00056q-CL for qemu-arm@nongnu.org; Sat, 12 Aug 2017 12:41:46 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dgZTq-0004Qo-Ag for qemu-arm@nongnu.org; Sat, 12 Aug 2017 12:41:45 -0400 Received: from mail-pg0-x22c.google.com ([2607:f8b0:400e:c05::22c]:35572) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1dgZTq-0004Qc-35 for qemu-arm@nongnu.org; Sat, 12 Aug 2017 12:41:42 -0400 Received: by mail-pg0-x22c.google.com with SMTP id v189so26453619pgd.2 for ; Sat, 12 Aug 2017 09:41:41 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=subject:to:cc:references:from:message-id:date:user-agent :mime-version:in-reply-to:content-language:content-transfer-encoding; bh=sRPhTJr6cUXPVWn5Tm0h2oHf50BQHSx2WVEV9TOs36M=; b=PZ+cwnO9h5MZYNJ79kjq/BpCrOPHE606sBYjfTEuzwNeB4OzxaGjaOCLDS3WNTcIWh 7XUna3kOw4Ol61jIPKY7+CbgqU6kVJkztt9IaaMU1IXY57KKBWKsOKUxv4lTJcixg9Rk OHxYUoeEklC6trY5DlZosECZ9N8YmMuG0XOcM= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:subject:to:cc:references:from:message-id:date :user-agent:mime-version:in-reply-to:content-language :content-transfer-encoding; bh=sRPhTJr6cUXPVWn5Tm0h2oHf50BQHSx2WVEV9TOs36M=; b=EDzA8ZQLtKBKQp+uGg8tDKm0e5tSDAa7iDHdfntwRdirvs7OM/3fOWHpQZyos4kT0o 63m+0n1EbQE5vNSieJPxepSFK6BwMBfHkkBC2HoruT9BFPSrNEGaXAgypbX7plQiEcXE YKRF3wOL6R+Hve7cvVd86QsC1aRkCBD2jXCyqmsdZS9aYoKXogyNkjY9N2hChZGau/+q klPaK3+mhGFvF59FudgtwEf7hXDJjJCe5TRmYjNIfq0oaTnGemdTuU2H3UNGkl020+h0 kWM39ZfvuT6LsideGcgsY+KTqOGfMVwYBc644PQTo04erMJpuqVHASgo9D9DjDZ4od3U rCTA== X-Gm-Message-State: AHYfb5h5qXl6GwyGWi8MwEpRw25rBZ1YtL9KDIUFYtvWdwLLtpeZXegK vQeLU9u+byXffuWD X-Received: by 10.84.167.2 with SMTP id c2mr22073695plb.336.1502556100719; Sat, 12 Aug 2017 09:41:40 -0700 (PDT) Received: from bigtime.twiddle.net (50-233-235-3-static.hfc.comcastbusiness.net. [50.233.235.3]) by smtp.gmail.com with ESMTPSA id l24sm6256167pgo.43.2017.08.12.09.41.39 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sat, 12 Aug 2017 09:41:39 -0700 (PDT) To: Alistair Francis , Richard Henderson Cc: Edgar Iglesias , Peter Maydell , qemu-arm , "qemu-devel@nongnu.org Developers" References: <20170812154131.29372-1-richard.henderson@linaro.org> From: Richard Henderson Message-ID: <7343971c-2563-d18b-cdac-60c4d66f5240@linaro.org> Date: Sat, 12 Aug 2017 09:41:37 -0700 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.2.1 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 7bit X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::22c Subject: Re: [Qemu-arm] [Qemu-devel] [PATCH] target/arm: Correct load/store exclusive pairing and alignment X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sat, 12 Aug 2017 16:41:46 -0000 On 08/12/2017 09:29 AM, Alistair Francis wrote: > Now we aren't ever checking cpu_exclusive_high. Is it even worth having? We are checking cpu_exclusive_high for 64-bit STXP. See paired_cmpxchg64_{l,b}e in target/arm/helper-a64.c. r~ From MAILER-DAEMON Sat Aug 12 14:23:37 2017 Received: from list by lists.gnu.org with archive (Exim 4.71) id 1dgb4T-0000J2-KB for mharc-qemu-arm@gnu.org; Sat, 12 Aug 2017 14:23:37 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:42989) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dgYXo-0001pg-Qx for qemu-arm@nongnu.org; Sat, 12 Aug 2017 11:41:46 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dgYXn-0004OF-EM for qemu-arm@nongnu.org; Sat, 12 Aug 2017 11:41:44 -0400 Received: from mail-pg0-x244.google.com ([2607:f8b0:400e:c05::244]:34161) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1dgYXi-0004Fl-D3; Sat, 12 Aug 2017 11:41:38 -0400 Received: by mail-pg0-x244.google.com with SMTP id y192so5371443pgd.1; Sat, 12 Aug 2017 08:41:36 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id; bh=nfUiRuuW2ZaqbgUQZyDm9sycQ/8BCH8lzVvBBPXGEgc=; b=HLUbgPWVTcLmIkt2XQYtVSu2FNDIa6yX/sIYrz0mqFLocza5UWvVMMrLpT8tDzlwlX 8a5NzQSyR/XM17aFLU+opsatu7k50RzfmlxbQ3qtbQ+C9rxFfU3WjHEZIcEAVu9EP5Rf gyXuppgXLtvi8znx1LAn6lcFuu1dp5Yioz06kDKs7Sq58CQ49+8VVMq8A8cZaLnHefdt lY7PiB9Da1qXpHJB8gVgw4SqezJB5cwftjBKcJXyPllmEWux/89LCSAH37PKWyRHjR5A n8jfziY8YB9LO8WeUskeBYTj39jHT6cGNzcXT5UPJ9L42Trvfp5JrS/wvzMW4AVKvF8K Afzg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=nfUiRuuW2ZaqbgUQZyDm9sycQ/8BCH8lzVvBBPXGEgc=; b=lKND7I0451jy5FX79ig2J9ezbPaQFPzPT90LjJERvlgbBxqxcIAM/yvWGMAVDs3lXd PB70hJFtTIRTzbUdBUcsGTh+9XvlpogESKgCMTYweQPtG40yqSrYPh1QbYCBt6FbETGm UdvXB7QgF6BZmgL7B+vu6go3wmzDssASWj0vDhpTAVnDvaRFoeS1RG7FUQPY+LNHm5Q+ Ur2b8TwdAaUfNYCmHFqlHPzUAh7/yfRdLWUauRbAmSBBN278ob0Z40lZ+9F8vfUtKX5W X+lQIREiSc97r/PcRypvdRW5ymaRaFK6nse59qRF77RmvZRdzABhpmN+lqZ6GlIf9SNT xSDw== X-Gm-Message-State: AHYfb5jGuDD+zkR4o3ktle/ZHY87NJi+1SfKQ9zdLVNOWbBYRpBNuJAv FFCLvZr1yzo2DcUAdUQ= X-Received: by 10.98.129.197 with SMTP id t188mr19433352pfd.318.1502552495578; Sat, 12 Aug 2017 08:41:35 -0700 (PDT) Received: from bigtime.twiddle.net (50-233-235-3-static.hfc.comcastbusiness.net. [50.233.235.3]) by smtp.gmail.com with ESMTPSA id e198sm6394041pfh.36.2017.08.12.08.41.33 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Sat, 12 Aug 2017 08:41:34 -0700 (PDT) From: Richard Henderson X-Google-Original-From: Richard Henderson To: qemu-devel@nongnu.org Cc: peter.maydell@linaro.org, alistair.francis@xilinx.com, edgar.iglesias@xilinx.com, qemu-arm@nongnu.org Date: Sat, 12 Aug 2017 08:41:31 -0700 Message-Id: <20170812154131.29372-1-richard.henderson@linaro.org> X-Mailer: git-send-email 2.13.4 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::244 X-Mailman-Approved-At: Sat, 12 Aug 2017 14:23:36 -0400 Subject: [Qemu-arm] [PATCH] target/arm: Correct load/store exclusive pairing and alignment X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sat, 12 Aug 2017 15:41:46 -0000 SetExclusiveMonitors in the pseudocode is on the address + width, and says nothing about the manner of the load. Therefore ldxp w0, w1, [x2] vs ldxr x0, [x2] must record the same metadata so that either may pair with stxp w3, w0, w1, [x2] vs stxr w3, x0, [x2] Fix this by ignoring cpu_exclusive_high except for 64-bit LDXP/STXP. Also note that we were not providing the required single-copy atomic semantics for 32-bit LDXP. This is trivially fixed alongside the cpu_exclusive_val change. At the same time, exclusive loads require the same alignment as exclusive stores. For 64-bit LDXP, this means adding MO_ALIGN_16; for the others adding MO_ALIGN. Reported-by: Alistair Francis Signed-off-by: Richard Henderson --- target/arm/translate-a64.c | 65 +++++++++++++++++++++++++++++----------------- 1 file changed, 41 insertions(+), 24 deletions(-) --- I have not yet constructed test cases for all of the combinations listed above. I wanted to put this into your hands so that you could test against your existing code using LDXP/STXP. r~ diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 58ed4c6d05..f3643ac8dc 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -1853,29 +1853,45 @@ static void disas_b_exc_sys(DisasContext *s, uint32_t insn) static void gen_load_exclusive(DisasContext *s, int rt, int rt2, TCGv_i64 addr, int size, bool is_pair) { - TCGv_i64 tmp = tcg_temp_new_i64(); - TCGMemOp memop = s->be_data + size; + int idx = get_mem_index(s); + TCGMemOp memop = s->be_data; g_assert(size <= 3); - tcg_gen_qemu_ld_i64(tmp, addr, get_mem_index(s), memop); - if (is_pair) { - TCGv_i64 addr2 = tcg_temp_new_i64(); - TCGv_i64 hitmp = tcg_temp_new_i64(); - g_assert(size >= 2); - tcg_gen_addi_i64(addr2, addr, 1 << size); - tcg_gen_qemu_ld_i64(hitmp, addr2, get_mem_index(s), memop); - tcg_temp_free_i64(addr2); - tcg_gen_mov_i64(cpu_exclusive_high, hitmp); - tcg_gen_mov_i64(cpu_reg(s, rt2), hitmp); - tcg_temp_free_i64(hitmp); - } + if (size == 2) { + /* The pair must be single-copy atomic for the doubleword. */ + memop |= MO_64 | MO_ALIGN; + tcg_gen_qemu_ld_i64(cpu_exclusive_val, addr, idx, memop); + if (s->be_data == MO_LE) { + tcg_gen_extract_i64(cpu_reg(s, rt), cpu_exclusive_val, 0, 32); + tcg_gen_extract_i64(cpu_reg(s, rt2), cpu_exclusive_val, 32, 32); + } else { + tcg_gen_extract_i64(cpu_reg(s, rt), cpu_exclusive_val, 32, 32); + tcg_gen_extract_i64(cpu_reg(s, rt2), cpu_exclusive_val, 0, 32); + } + } else { + /* The pair must be single-copy atomic for *each* doubleword, + but not the entire quadword. It must, however, be aligned. */ + TCGv_i64 addr2; - tcg_gen_mov_i64(cpu_exclusive_val, tmp); - tcg_gen_mov_i64(cpu_reg(s, rt), tmp); + memop |= MO_64; + tcg_gen_qemu_ld_i64(cpu_exclusive_val, addr, idx, + memop | MO_ALIGN_16); - tcg_temp_free_i64(tmp); + addr2 = tcg_temp_new_i64(); + tcg_gen_addi_i64(addr2, addr, 8); + tcg_gen_qemu_ld_i64(cpu_exclusive_high, addr2, idx, memop); + tcg_temp_free_i64(addr2); + + tcg_gen_mov_i64(cpu_reg(s, rt), cpu_exclusive_val); + tcg_gen_mov_i64(cpu_reg(s, rt2), cpu_exclusive_high); + } + } else { + memop |= size | MO_ALIGN; + tcg_gen_qemu_ld_i64(cpu_exclusive_val, addr, idx, memop); + tcg_gen_mov_i64(cpu_reg(s, rt), cpu_exclusive_val); + } tcg_gen_mov_i64(cpu_exclusive_addr, addr); } @@ -1908,14 +1924,15 @@ static void gen_store_exclusive(DisasContext *s, int rd, int rt, int rt2, tmp = tcg_temp_new_i64(); if (is_pair) { if (size == 2) { - TCGv_i64 val = tcg_temp_new_i64(); - tcg_gen_concat32_i64(tmp, cpu_reg(s, rt), cpu_reg(s, rt2)); - tcg_gen_concat32_i64(val, cpu_exclusive_val, cpu_exclusive_high); - tcg_gen_atomic_cmpxchg_i64(tmp, addr, val, tmp, + if (s->be_data == MO_LE) { + tcg_gen_concat32_i64(tmp, cpu_reg(s, rt), cpu_reg(s, rt2)); + } else { + tcg_gen_concat32_i64(tmp, cpu_reg(s, rt2), cpu_reg(s, rt)); + } + tcg_gen_atomic_cmpxchg_i64(tmp, addr, cpu_exclusive_val, tmp, get_mem_index(s), - size | MO_ALIGN | s->be_data); - tcg_gen_setcond_i64(TCG_COND_NE, tmp, tmp, val); - tcg_temp_free_i64(val); + MO_64 | MO_ALIGN | s->be_data); + tcg_gen_setcond_i64(TCG_COND_NE, tmp, tmp, cpu_exclusive_val); } else if (s->be_data == MO_LE) { gen_helper_paired_cmpxchg64_le(tmp, cpu_env, addr, cpu_reg(s, rt), cpu_reg(s, rt2)); -- 2.13.4 From MAILER-DAEMON Sat Aug 12 14:23:40 2017 Received: from list by lists.gnu.org with archive (Exim 4.71) id 1dgb4W-0000LV-B6 for mharc-qemu-arm@gnu.org; Sat, 12 Aug 2017 14:23:40 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:54501) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dgZ86-0003DJ-Qg for qemu-arm@nongnu.org; Sat, 12 Aug 2017 12:19:16 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dgZ85-0001C6-MM for qemu-arm@nongnu.org; Sat, 12 Aug 2017 12:19:14 -0400 Received: from mail-pf0-x244.google.com ([2607:f8b0:400e:c00::244]:34703) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1dgZ7z-00016f-Tu; Sat, 12 Aug 2017 12:19:08 -0400 Received: by mail-pf0-x244.google.com with SMTP id t86so6089402pfe.1; Sat, 12 Aug 2017 09:19:07 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id; bh=Mc7qw1Vfs3qsF08MS8HxmRPcaiuIejYYbAVNjDiIB+k=; b=Ge5QRplw8OZm3oR/slSuRSogdsKOWsrlEqBpYO93vCYQYPrz7afH0y7ScE+Jj92S6P UM981lFUbm1L+n+0lOYweccyh/SGl9VTO/9mNN60lBOwV/DZFDBzyvl/N4FohbLdhakG D3NTqJBaU4zdb8ZrkB2YUQFBpO7XNRlGiNwxnPeFHX+qiSKRHy8VL8z0zhJsF8p01vJt de4oAvzpboMIgd/1iR+8Pj1UqzHQRa7iy8fApEFVUrWNbnp3GE8AifvjOw+H7rLS9yqb wM+IOmY3MhSEYk7Y7fdyZrCdvtSZyB87QgAN8+b6mRAMFPcbnnWWm/kHbs5Jj8Pgwyd/ NVhA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=Mc7qw1Vfs3qsF08MS8HxmRPcaiuIejYYbAVNjDiIB+k=; b=d6GvYa3Pd8C/A2hklVReELh2VnUmO1Sp6zifE64S+IZfy7abH4Gx9sZktdqStgIeiD 0QkEE1uO7Gv0ifj0y4mWLaCScq4VEZXhdGjd1LL4AKjE579zObOWQcxUeWBxoesfIY/J xTW8MOVupOfRbiNCcCbtYxe2KKWZahw/2ehQLAepSb2bb1CgyJrHRvORIPhYImgXUnaP xzUfsLgov4XtJ9WwBvbPuA44d37BKGJy5WoZsOLEDnJa9tlV1E2O8CzuOIJIdUAtV+nz UU9Xs55IimNGHAAayiqlnyfLaWrnxHNhfj/jbXpWdQoxmUJvB34nwnclNpf3QHRlBKuA sEmg== X-Gm-Message-State: AHYfb5hVUlLLYMwMTcarI3RqU2tp+DH0Q/OtY1knymfaCY8rAHy62qJr kVCJJ0su3Rb2I6vlMAc= X-Received: by 10.84.169.3 with SMTP id g3mr21509761plb.136.1502554746539; Sat, 12 Aug 2017 09:19:06 -0700 (PDT) Received: from bigtime.twiddle.net (50-233-235-3-static.hfc.comcastbusiness.net. [50.233.235.3]) by smtp.gmail.com with ESMTPSA id a67sm6865912pfl.167.2017.08.12.09.19.05 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Sat, 12 Aug 2017 09:19:05 -0700 (PDT) From: Richard Henderson X-Google-Original-From: Richard Henderson To: qemu-devel@nongnu.org Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Date: Sat, 12 Aug 2017 09:19:03 -0700 Message-Id: <20170812161903.8622-1-richard.henderson@linaro.org> X-Mailer: git-send-email 2.13.4 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::244 X-Mailman-Approved-At: Sat, 12 Aug 2017 14:23:37 -0400 Subject: [Qemu-arm] [PATCH] target/arm: Avoid an extra temporary for store_exclusive X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sat, 12 Aug 2017 16:19:16 -0000 Instead of copying addr to a local temp, reuse the value (which we have just compared as equal) already saved in cpu_exclusive_addr. Signed-off-by: Richard Henderson --- target/arm/translate-a64.c | 26 +++++++++----------------- 1 file changed, 9 insertions(+), 17 deletions(-) diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index f3643ac8dc..f3a1b1cecc 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -1896,7 +1896,7 @@ static void gen_load_exclusive(DisasContext *s, int rt, int rt2, } static void gen_store_exclusive(DisasContext *s, int rd, int rt, int rt2, - TCGv_i64 inaddr, int size, int is_pair) + TCGv_i64 addr, int size, int is_pair) { /* if (env->exclusive_addr == addr && env->exclusive_val == [addr] * && (!is_pair || env->exclusive_high == [addr + datasize])) { @@ -1912,13 +1912,8 @@ static void gen_store_exclusive(DisasContext *s, int rd, int rt, int rt2, */ TCGLabel *fail_label = gen_new_label(); TCGLabel *done_label = gen_new_label(); - TCGv_i64 addr = tcg_temp_local_new_i64(); TCGv_i64 tmp; - /* Copy input into a local temp so it is not trashed when the - * basic block ends at the branch insn. - */ - tcg_gen_mov_i64(addr, inaddr); tcg_gen_brcond_i64(TCG_COND_NE, addr, cpu_exclusive_addr, fail_label); tmp = tcg_temp_new_i64(); @@ -1929,27 +1924,24 @@ static void gen_store_exclusive(DisasContext *s, int rd, int rt, int rt2, } else { tcg_gen_concat32_i64(tmp, cpu_reg(s, rt2), cpu_reg(s, rt)); } - tcg_gen_atomic_cmpxchg_i64(tmp, addr, cpu_exclusive_val, tmp, + tcg_gen_atomic_cmpxchg_i64(tmp, cpu_exclusive_addr, + cpu_exclusive_val, tmp, get_mem_index(s), MO_64 | MO_ALIGN | s->be_data); tcg_gen_setcond_i64(TCG_COND_NE, tmp, tmp, cpu_exclusive_val); } else if (s->be_data == MO_LE) { - gen_helper_paired_cmpxchg64_le(tmp, cpu_env, addr, cpu_reg(s, rt), - cpu_reg(s, rt2)); + gen_helper_paired_cmpxchg64_le(tmp, cpu_env, cpu_exclusive_addr, + cpu_reg(s, rt), cpu_reg(s, rt2)); } else { - gen_helper_paired_cmpxchg64_be(tmp, cpu_env, addr, cpu_reg(s, rt), - cpu_reg(s, rt2)); + gen_helper_paired_cmpxchg64_be(tmp, cpu_env, cpu_exclusive_addr, + cpu_reg(s, rt), cpu_reg(s, rt2)); } } else { - TCGv_i64 val = cpu_reg(s, rt); - tcg_gen_atomic_cmpxchg_i64(tmp, addr, cpu_exclusive_val, val, - get_mem_index(s), + tcg_gen_atomic_cmpxchg_i64(tmp, cpu_exclusive_addr, cpu_exclusive_val, + cpu_reg(s, rt), get_mem_index(s), size | MO_ALIGN | s->be_data); tcg_gen_setcond_i64(TCG_COND_NE, tmp, tmp, cpu_exclusive_val); } - - tcg_temp_free_i64(addr); - tcg_gen_mov_i64(cpu_reg(s, rd), tmp); tcg_temp_free_i64(tmp); tcg_gen_br(done_label); -- 2.13.4 From MAILER-DAEMON Mon Aug 14 04:59:22 2017 Received: from list by lists.gnu.org with archive (Exim 4.71) id 1dhBDW-0001zK-BQ for mharc-qemu-arm@gnu.org; Mon, 14 Aug 2017 04:59:22 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:37665) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dhBDT-0001yv-IZ for qemu-arm@nongnu.org; Mon, 14 Aug 2017 04:59:21 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dhBDQ-0005RZ-DR for qemu-arm@nongnu.org; Mon, 14 Aug 2017 04:59:19 -0400 Received: from mx1.redhat.com ([209.132.183.28]:46834) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1dhBDQ-0005Or-4B; Mon, 14 Aug 2017 04:59:16 -0400 Received: from smtp.corp.redhat.com (int-mx01.intmail.prod.int.phx2.redhat.com [10.5.11.11]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id A1B7395F27; Mon, 14 Aug 2017 08:53:27 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mx1.redhat.com A1B7395F27 Authentication-Results: ext-mx04.extmail.prod.ext.phx2.redhat.com; dmarc=none (p=none dis=none) header.from=redhat.com Authentication-Results: ext-mx04.extmail.prod.ext.phx2.redhat.com; spf=fail smtp.mailfrom=drjones@redhat.com Received: from kamzik.brq.redhat.com (unknown [10.43.2.160]) by smtp.corp.redhat.com (Postfix) with ESMTPS id C69B26047B; Mon, 14 Aug 2017 08:53:25 +0000 (UTC) Date: Mon, 14 Aug 2017 10:53:23 +0200 From: Andrew Jones To: Igor Mammedov Cc: qemu-devel@nongnu.org, Peter Maydell , Eduardo Habkost , qemu-arm@nongnu.org, Jan Kiszka , Andreas =?iso-8859-1?Q?F=E4rber?= Message-ID: <20170814085323.ethzsjtx3xse2muj@kamzik.brq.redhat.com> References: <1500040339-119465-1-git-send-email-imammedo@redhat.com> <1500040339-119465-22-git-send-email-imammedo@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1500040339-119465-22-git-send-email-imammedo@redhat.com> User-Agent: Mutt/1.6.0.1 (2016-04-01) X-Scanned-By: MIMEDefang 2.79 on 10.5.11.11 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.28]); Mon, 14 Aug 2017 08:53:27 +0000 (UTC) X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.132.183.28 Subject: Re: [Qemu-arm] [Qemu-devel] [PATCH 21/28] arm: replace cpu_arm_init() with cpu_generic_init() X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 14 Aug 2017 08:59:21 -0000 On Fri, Jul 14, 2017 at 03:52:12PM +0200, Igor Mammedov wrote: > it's just a wrapper, drop it and use cpu_generic_init() directly > > Signed-off-by: Igor Mammedov > --- > CC: Jan Kiszka > CC: Peter Maydell > CC: Andrzej Zaborowski > CC: qemu-arm@nongnu.org > --- > target/arm/cpu.h | 3 +-- > hw/arm/musicpal.c | 2 +- > hw/arm/omap1.c | 2 +- > hw/arm/omap2.c | 2 +- > hw/arm/pxa2xx.c | 4 ++-- > hw/arm/strongarm.c | 2 +- > target/arm/helper.c | 5 ----- > 7 files changed, 7 insertions(+), 13 deletions(-) > > diff --git a/target/arm/cpu.h b/target/arm/cpu.h > index 16a1e59..c9be0ac 100644 > --- a/target/arm/cpu.h > +++ b/target/arm/cpu.h > @@ -746,7 +746,6 @@ int aarch64_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg); > int aarch64_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); > #endif > > -ARMCPU *cpu_arm_init(const char *cpu_model); > target_ulong do_arm_semihosting(CPUARMState *env); > void aarch64_sync_32_to_64(CPUARMState *env); > void aarch64_sync_64_to_32(CPUARMState *env); > @@ -1999,7 +1998,7 @@ static inline bool arm_excp_unmasked(CPUState *cs, unsigned int excp_idx, > return unmasked || pstate_unmasked; > } > > -#define cpu_init(cpu_model) CPU(cpu_arm_init(cpu_model)) > +#define cpu_init(cpu_model) cpu_generic_init(TYPE_ARM_CPU, cpu_model) > > #define cpu_signal_handler cpu_arm_signal_handler > #define cpu_list arm_cpu_list > diff --git a/hw/arm/musicpal.c b/hw/arm/musicpal.c > index 9c710f7..0d519f9 100644 > --- a/hw/arm/musicpal.c > +++ b/hw/arm/musicpal.c > @@ -1593,7 +1593,7 @@ static void musicpal_init(MachineState *machine) > if (!cpu_model) { > cpu_model = "arm926"; > } > - cpu = cpu_arm_init(cpu_model); > + cpu = ARM_CPU(cpu_generic_init(TYPE_ARM_CPU, cpu_model)); > if (!cpu) { > fprintf(stderr, "Unable to find CPU definition\n"); > exit(1); > diff --git a/hw/arm/omap1.c b/hw/arm/omap1.c > index 54582bd..391eb28 100644 > --- a/hw/arm/omap1.c > +++ b/hw/arm/omap1.c > @@ -3863,7 +3863,7 @@ struct omap_mpu_state_s *omap310_mpu_init(MemoryRegion *system_memory, > > /* Core */ > s->mpu_model = omap310; > - s->cpu = cpu_arm_init(core); > + s->cpu = ARM_CPU(cpu_generic_init(TYPE_ARM_CPU, core)); > if (s->cpu == NULL) { > fprintf(stderr, "Unable to find CPU definition\n"); > exit(1); > diff --git a/hw/arm/omap2.c b/hw/arm/omap2.c > index 91f5733..a20bb1f 100644 > --- a/hw/arm/omap2.c > +++ b/hw/arm/omap2.c > @@ -2261,7 +2261,7 @@ struct omap_mpu_state_s *omap2420_mpu_init(MemoryRegion *sysmem, > > /* Core */ > s->mpu_model = omap2420; > - s->cpu = cpu_arm_init(core ?: "arm1136-r2"); > + s->cpu = ARM_CPU(cpu_generic_init(TYPE_ARM_CPU, core ?: "arm1136-r2")); > if (s->cpu == NULL) { > fprintf(stderr, "Unable to find CPU definition\n"); > exit(1); > diff --git a/hw/arm/pxa2xx.c b/hw/arm/pxa2xx.c > index 629e6c6..2f1c141 100644 > --- a/hw/arm/pxa2xx.c > +++ b/hw/arm/pxa2xx.c > @@ -2065,7 +2065,7 @@ PXA2xxState *pxa270_init(MemoryRegion *address_space, > if (!revision) > revision = "pxa270"; > > - s->cpu = cpu_arm_init(revision); > + s->cpu = ARM_CPU(cpu_generic_init(TYPE_ARM_CPU, revision)); > if (s->cpu == NULL) { > fprintf(stderr, "Unable to find CPU definition\n"); > exit(1); > @@ -2197,7 +2197,7 @@ PXA2xxState *pxa255_init(MemoryRegion *address_space, unsigned int sdram_size) > > s = g_new0(PXA2xxState, 1); > > - s->cpu = cpu_arm_init("pxa255"); > + s->cpu = ARM_CPU(cpu_generic_init(TYPE_ARM_CPU, "pxa255")); > if (s->cpu == NULL) { > fprintf(stderr, "Unable to find CPU definition\n"); > exit(1); > diff --git a/hw/arm/strongarm.c b/hw/arm/strongarm.c > index 7683edc..a27d7c8 100644 > --- a/hw/arm/strongarm.c > +++ b/hw/arm/strongarm.c > @@ -1597,7 +1597,7 @@ StrongARMState *sa1110_init(MemoryRegion *sysmem, > exit(1); > } > > - s->cpu = cpu_arm_init(rev); > + s->cpu = ARM_CPU(cpu_generic_init(TYPE_ARM_CPU, rev)); > > if (!s->cpu) { > error_report("Unable to find CPU definition"); > diff --git a/target/arm/helper.c b/target/arm/helper.c > index 2594faa..86e69a6 100644 > --- a/target/arm/helper.c > +++ b/target/arm/helper.c > @@ -5237,11 +5237,6 @@ void register_cp_regs_for_features(ARMCPU *cpu) > } > } > > -ARMCPU *cpu_arm_init(const char *cpu_model) > -{ > - return ARM_CPU(cpu_generic_init(TYPE_ARM_CPU, cpu_model)); > -} > - > void arm_cpu_register_gdb_regs_for_features(ARMCPU *cpu) > { > CPUState *cs = CPU(cpu); > -- > 2.7.4 > > I agree with the motivation described in the cover letter and the changes (which are even mostly verified by the compiler) look good to me. Reviewed-by: Andrew Jones From MAILER-DAEMON Mon Aug 14 14:23:42 2017 Received: from list by lists.gnu.org with archive (Exim 4.71) id 1dhK1d-0006kY-VX for mharc-qemu-arm@gnu.org; Mon, 14 Aug 2017 14:23:42 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:60931) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dhK1a-0006gk-T6 for qemu-arm@nongnu.org; Mon, 14 Aug 2017 14:23:40 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dhK1Z-0007En-NS for qemu-arm@nongnu.org; Mon, 14 Aug 2017 14:23:38 -0400 Received: from mail-wm0-x242.google.com ([2a00:1450:400c:c09::242]:36780) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1dhK1W-0007C8-AN; Mon, 14 Aug 2017 14:23:34 -0400 Received: by mail-wm0-x242.google.com with SMTP id d40so15318638wma.3; Mon, 14 Aug 2017 11:23:32 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=mime-version:sender:in-reply-to:references:from:date:message-id :subject:to:cc; bh=gTK2E2gWFGcWYMKnOLbj17OjyL+mT54NlZr17NPhFT8=; b=rYa4YZmcx8Dl489AKBVu1ZIVVh9iPqejrjvZ7jZ61fC9PaIty7G4OokOns4NMyrVtf i4tsDwzMiPd/Q1ftSNM5QQ9Of4Xef6uGpw8yeVsOukN5CdWWo2d+Qsb1qChEnd+kQAfu BFojKbY5ZCBfCigddxMccxbvQ85AuWA+wOXp6deSz21DJm602zvF6+djhpeG0cm/cTeg aON5pJ0HTh8Ob0LzE/WjTHd1ChFPp9uQlIVHBHAVbU1C/TYD4Hs3v+S544JS5jCJyM9p ZM/Z0lIpXduj2kWMHrGRg5zrBXF2pBIFxJxSSrLd2/eJmOOSVD8o/t9QNdtpFjGPgmON SUXw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:sender:in-reply-to:references:from :date:message-id:subject:to:cc; bh=gTK2E2gWFGcWYMKnOLbj17OjyL+mT54NlZr17NPhFT8=; b=VXgFQjpqqrhYyVFivmpELYFzWTJzo/BP+vqc3BNH++oboYOWICoF+Mpaab08jS1tPw MQBz0LKxqmTznus3Ng40ckAesyMO8F3Ye5YTr0WB9ZJAlzYw+DD1EccCh0Ep5PpYxfJ9 iu5DH4qdPY9HCJu8cFvaNVTGxI4a2aOb22TDjgr3AzX3/OkYHDK3jz0SKMOuza9/pqCV HY3omnl4lXWmQIic76zwIcDCrP68T57FpCcRi+jGzVg2Hl1QE2DepqA7w2SqV3+Hfq/F cMdVDkGB68J1SKtAiqgBGH0vILBn87kPMDGhy8voUSAVLSRyABgRLV+GwQmM3PVS3YwK n/3g== X-Gm-Message-State: AHYfb5hIRrwvixWS7iVlAI9IUuLodrTxiu/LE1wqTGxo1kCDwog8qToC hm9N4HDbSwGn7HXQtUn1sX+En48I+A== X-Received: by 10.28.45.211 with SMTP id t202mr4269212wmt.105.1502735011677; Mon, 14 Aug 2017 11:23:31 -0700 (PDT) MIME-Version: 1.0 Sender: alistair23@gmail.com Received: by 10.28.191.130 with HTTP; Mon, 14 Aug 2017 11:23:01 -0700 (PDT) In-Reply-To: <20170812154131.29372-1-richard.henderson@linaro.org> References: <20170812154131.29372-1-richard.henderson@linaro.org> From: Alistair Francis Date: Mon, 14 Aug 2017 11:23:01 -0700 X-Google-Sender-Auth: VjzovvbjQvIDCpZaQnPHvm3WFvE Message-ID: To: Richard Henderson Cc: "qemu-devel@nongnu.org Developers" , Edgar Iglesias , Peter Maydell , qemu-arm , Alistair Francis Content-Type: text/plain; charset="UTF-8" X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:400c:c09::242 Subject: Re: [Qemu-arm] [Qemu-devel] [PATCH] target/arm: Correct load/store exclusive pairing and alignment X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 14 Aug 2017 18:23:40 -0000 On Sat, Aug 12, 2017 at 8:41 AM, Richard Henderson wrote: > SetExclusiveMonitors in the pseudocode is on the address + width, > and says nothing about the manner of the load. Therefore > > ldxp w0, w1, [x2] > vs > ldxr x0, [x2] > > must record the same metadata so that either may pair with > > stxp w3, w0, w1, [x2] > vs > stxr w3, x0, [x2] > > Fix this by ignoring cpu_exclusive_high except for 64-bit LDXP/STXP. > > Also note that we were not providing the required single-copy atomic > semantics for 32-bit LDXP. This is trivially fixed alongside the > cpu_exclusive_val change. > > At the same time, exclusive loads require the same alignment as > exclusive stores. For 64-bit LDXP, this means adding MO_ALIGN_16; > for the others adding MO_ALIGN. > > Reported-by: Alistair Francis > Signed-off-by: Richard Henderson This passes the same tests that my patch series passes. Reviewed-by: Alistair Francis Tested-by: Alistair Francis Thanks, Alistair > --- > target/arm/translate-a64.c | 65 +++++++++++++++++++++++++++++----------------- > 1 file changed, 41 insertions(+), 24 deletions(-) > --- > > I have not yet constructed test cases for all of the combinations > listed above. I wanted to put this into your hands so that you could > test against your existing code using LDXP/STXP. > > > r~ > > > diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c > index 58ed4c6d05..f3643ac8dc 100644 > --- a/target/arm/translate-a64.c > +++ b/target/arm/translate-a64.c > @@ -1853,29 +1853,45 @@ static void disas_b_exc_sys(DisasContext *s, uint32_t insn) > static void gen_load_exclusive(DisasContext *s, int rt, int rt2, > TCGv_i64 addr, int size, bool is_pair) > { > - TCGv_i64 tmp = tcg_temp_new_i64(); > - TCGMemOp memop = s->be_data + size; > + int idx = get_mem_index(s); > + TCGMemOp memop = s->be_data; > > g_assert(size <= 3); > - tcg_gen_qemu_ld_i64(tmp, addr, get_mem_index(s), memop); > - > if (is_pair) { > - TCGv_i64 addr2 = tcg_temp_new_i64(); > - TCGv_i64 hitmp = tcg_temp_new_i64(); > - > g_assert(size >= 2); > - tcg_gen_addi_i64(addr2, addr, 1 << size); > - tcg_gen_qemu_ld_i64(hitmp, addr2, get_mem_index(s), memop); > - tcg_temp_free_i64(addr2); > - tcg_gen_mov_i64(cpu_exclusive_high, hitmp); > - tcg_gen_mov_i64(cpu_reg(s, rt2), hitmp); > - tcg_temp_free_i64(hitmp); > - } > + if (size == 2) { > + /* The pair must be single-copy atomic for the doubleword. */ > + memop |= MO_64 | MO_ALIGN; > + tcg_gen_qemu_ld_i64(cpu_exclusive_val, addr, idx, memop); > + if (s->be_data == MO_LE) { > + tcg_gen_extract_i64(cpu_reg(s, rt), cpu_exclusive_val, 0, 32); > + tcg_gen_extract_i64(cpu_reg(s, rt2), cpu_exclusive_val, 32, 32); > + } else { > + tcg_gen_extract_i64(cpu_reg(s, rt), cpu_exclusive_val, 32, 32); > + tcg_gen_extract_i64(cpu_reg(s, rt2), cpu_exclusive_val, 0, 32); > + } > + } else { > + /* The pair must be single-copy atomic for *each* doubleword, > + but not the entire quadword. It must, however, be aligned. */ > + TCGv_i64 addr2; > > - tcg_gen_mov_i64(cpu_exclusive_val, tmp); > - tcg_gen_mov_i64(cpu_reg(s, rt), tmp); > + memop |= MO_64; > + tcg_gen_qemu_ld_i64(cpu_exclusive_val, addr, idx, > + memop | MO_ALIGN_16); > > - tcg_temp_free_i64(tmp); > + addr2 = tcg_temp_new_i64(); > + tcg_gen_addi_i64(addr2, addr, 8); > + tcg_gen_qemu_ld_i64(cpu_exclusive_high, addr2, idx, memop); > + tcg_temp_free_i64(addr2); > + > + tcg_gen_mov_i64(cpu_reg(s, rt), cpu_exclusive_val); > + tcg_gen_mov_i64(cpu_reg(s, rt2), cpu_exclusive_high); > + } > + } else { > + memop |= size | MO_ALIGN; > + tcg_gen_qemu_ld_i64(cpu_exclusive_val, addr, idx, memop); > + tcg_gen_mov_i64(cpu_reg(s, rt), cpu_exclusive_val); > + } > tcg_gen_mov_i64(cpu_exclusive_addr, addr); > } > > @@ -1908,14 +1924,15 @@ static void gen_store_exclusive(DisasContext *s, int rd, int rt, int rt2, > tmp = tcg_temp_new_i64(); > if (is_pair) { > if (size == 2) { > - TCGv_i64 val = tcg_temp_new_i64(); > - tcg_gen_concat32_i64(tmp, cpu_reg(s, rt), cpu_reg(s, rt2)); > - tcg_gen_concat32_i64(val, cpu_exclusive_val, cpu_exclusive_high); > - tcg_gen_atomic_cmpxchg_i64(tmp, addr, val, tmp, > + if (s->be_data == MO_LE) { > + tcg_gen_concat32_i64(tmp, cpu_reg(s, rt), cpu_reg(s, rt2)); > + } else { > + tcg_gen_concat32_i64(tmp, cpu_reg(s, rt2), cpu_reg(s, rt)); > + } > + tcg_gen_atomic_cmpxchg_i64(tmp, addr, cpu_exclusive_val, tmp, > get_mem_index(s), > - size | MO_ALIGN | s->be_data); > - tcg_gen_setcond_i64(TCG_COND_NE, tmp, tmp, val); > - tcg_temp_free_i64(val); > + MO_64 | MO_ALIGN | s->be_data); > + tcg_gen_setcond_i64(TCG_COND_NE, tmp, tmp, cpu_exclusive_val); > } else if (s->be_data == MO_LE) { > gen_helper_paired_cmpxchg64_le(tmp, cpu_env, addr, cpu_reg(s, rt), > cpu_reg(s, rt2)); > -- > 2.13.4 > > From MAILER-DAEMON Thu Aug 17 06:26:01 2017 Received: from list by lists.gnu.org with archive (Exim 4.71) id 1diI01-0006UG-NJ for mharc-qemu-arm@gnu.org; Thu, 17 Aug 2017 06:26:01 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:33788) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1diHzz-0006TW-WA for qemu-arm@nongnu.org; Thu, 17 Aug 2017 06:26:00 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1diHzy-0005GE-PM for qemu-arm@nongnu.org; Thu, 17 Aug 2017 06:25:59 -0400 Received: from mail-wr0-x234.google.com ([2a00:1450:400c:c0c::234]:33583) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1diHzy-0005Fo-JK for qemu-arm@nongnu.org; Thu, 17 Aug 2017 06:25:58 -0400 Received: by mail-wr0-x234.google.com with SMTP id b65so39473699wrd.0 for ; Thu, 17 Aug 2017 03:25:58 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:in-reply-to:references:from:date:message-id:subject:to :cc:content-transfer-encoding; bh=H3QFlI++2TRFduytWBPAJelUj7cPt29yHZL6FfSY5t8=; b=W1aO8m0+ZVWI1bltZOWRaitdMrXv087SAE5xu3/9n4ZD9EqitUVMtK4fZaKQhLElK4 quI9SmsGpP89d08Zfy0r+9suDexy5QCDCrJF6i7Tzf8Gh4gbMHJfzsnace8cOJXRMlWM ay2/x7/G7wUWprTxmvrbwdryti77wswxwZ/t0= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:in-reply-to:references:from:date :message-id:subject:to:cc:content-transfer-encoding; bh=H3QFlI++2TRFduytWBPAJelUj7cPt29yHZL6FfSY5t8=; b=hXDHW6d8wmuBzeOLzhDXq7fLJCr4GLVJR6rA1YEGJyqVP+eKP7ZG5Wb0sDXB8Klk2D YZBsZIPsliLM0w7b0nJJd+hqZf/TVTyF652NnZn/ibXwsV/jy9SJlWuxMDwr4ZrFsU7/ P5Ne2F841uS7nfsvCu5GvG+2+9wXR8eBiuiGVAMPKwzo5T6rPP0fyo9QYBLG6kEpioJM OmTfQ7Ux7WQog8aTo1EdSR7QPDAxn9nxtBiQhqGM+Ngh6vLEea6Cc2YqVPfU5TB8NOQj vJG6GKYmZlUKfCr73luipg7g9wQ+WTqRKwInp8FAQNxzF2OXi+jk9i07KZJVZh8uA8YW lLmg== X-Gm-Message-State: AHYfb5h4CkAQ35VwHXJps/AxZUt5cZ3or8KFq0env6CWKgvRBDdOHGVF lq3iAQCRJHU7HgmUnBsXrA57BQfIi89z X-Received: by 10.28.22.205 with SMTP id 196mr895874wmw.39.1502965557284; Thu, 17 Aug 2017 03:25:57 -0700 (PDT) MIME-Version: 1.0 Received: by 10.223.134.54 with HTTP; Thu, 17 Aug 2017 03:25:36 -0700 (PDT) In-Reply-To: References: <1501867249-1924-1-git-send-email-peter.maydell@linaro.org> <1501867249-1924-5-git-send-email-peter.maydell@linaro.org> <50d6ba4d-cfa3-5b5f-5da1-dca2326d4f5d@amsat.org> From: Peter Maydell Date: Thu, 17 Aug 2017 11:25:36 +0100 Message-ID: To: Richard Henderson Cc: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= , qemu-arm , QEMU Developers Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:400c:c0c::234 Subject: Re: [Qemu-arm] [PATCH 4/8] boards.h: Define new flag ignore_memory_transaction_failures X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 17 Aug 2017 10:26:01 -0000 On 5 August 2017 at 11:13, Peter Maydell wrote: > On 4 August 2017 at 20:23, Richard Henderson > wrote: >> On 08/04/2017 11:09 AM, Philippe Mathieu-Daud=C3=A9 wrote: >>> Since create_unimplemented_device() register overlapped with low priori= ty, why >>> not register it as default device directly, over the whole address spac= e? >> >> That's a good suggestion. It makes more sense to me than adding a flag = on the >> MachineClass. > > Yeah, I did think about implementing it that way, but... > > That wouldn't handle the case of a device model directly > returning a MEMTX_ERROR, or a transaction dispatched to > a memory region whose MemoryRegionOps valid settings > prohibit it (eg byte accesses to a word-access-only device), > or accesses to a MemoryRegion that was created by passing > a NULL MemoryRegionOps pointer to memory_region_init_io > (I dunno why you'd do that but some code does). > > In short, there are lots of ways the memory subsystem might > end up returning a transaction error -- this mechanism > ensures that none of them start generating exceptions > when they previously did not, and is (I hope) easy to > review in the sense of being sure that it does what it > intends to do without the need to audit a lot of corner > cases. So, this question (should we have a board flag to disable reporting of tx failures to the CPU hook, or use unimplemented_device as a sort of background region) seems to be the main unanswered question for this series. I think (as outlined above) that the board flag is simpler and safer; are people happy for me to put this series in target-arm.next with that approach, or should I rethink this bit? thanks -- PMM From MAILER-DAEMON Thu Aug 17 06:42:19 2017 Received: from list by lists.gnu.org with archive (Exim 4.71) id 1diIFn-0003UW-Rt for mharc-qemu-arm@gnu.org; Thu, 17 Aug 2017 06:42:19 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:37455) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1diIFm-0003TO-Hg for qemu-arm@nongnu.org; Thu, 17 Aug 2017 06:42:19 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1diIFl-0005CB-Qh for qemu-arm@nongnu.org; Thu, 17 Aug 2017 06:42:18 -0400 Received: from mail-wr0-x231.google.com ([2a00:1450:400c:c0c::231]:33492) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1diIFl-0005Bx-Ig for qemu-arm@nongnu.org; Thu, 17 Aug 2017 06:42:17 -0400 Received: by mail-wr0-x231.google.com with SMTP id b65so39824325wrd.0 for ; Thu, 17 Aug 2017 03:42:17 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:in-reply-to:references:from:date:message-id:subject:to :cc; bh=FDBEeYIp4H4wZANhr7GKuTVSa2NyjSNsSyypF+cQnqA=; b=R3RKYcZD0NAr/Vvjrbjc3oZJb0Hz+5Pul/uaaj8QyxfFhuyt6RLWoob5tD8gFmp5dN gdsE4kphj3IDEvv23ImKLIVMFXlKkcc8ErdI8hTjgiCfxsg9HLBJjvfx9kmVZhb5+z36 ifPblQhVNQ01u1umDPCpFGB9o3mIq3drZWXs4= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:in-reply-to:references:from:date :message-id:subject:to:cc; bh=FDBEeYIp4H4wZANhr7GKuTVSa2NyjSNsSyypF+cQnqA=; b=V4eTb64e2QiRxfpKp6zruL6nsDnAyDPwmqtOO73mGvjnAbKeM0hjsdI918z07bv4Q5 Haq689gqCI4cCjMIIxNQ2h/5zGPeyHJLv4+/bi/DXUvsfZgtaeKcgTYqDE482f2wE403 OA/aMvl8b4TkC+ffwwekgepoQfV8x31NyuTFJyr2/4rQGxhcMO/JhEd+aOtdwE4slmuJ vMYwgW6ymYo5ySWWKvPGI3YjdpQ3tcRpnBXMoir4uyiMGAqGYoFQjT+9pahIVMcMFBNc fjWgj2wofOjIVrOfSa5NWTDlQ3RSsn5bdN/or34ismyB+V703DZLF7EKXhWEbzgjdYJX lM+A== X-Gm-Message-State: AHYfb5h84mUgcpKz326W/AmRdyP5rJiySgeJK9tQ+rzSY/STyFRtb4b1 pEZKffa7EynW8nif2JyzK5CSu1pph7SB X-Received: by 10.223.163.20 with SMTP id c20mr3338372wrb.173.1502966536258; Thu, 17 Aug 2017 03:42:16 -0700 (PDT) MIME-Version: 1.0 Received: by 10.223.134.54 with HTTP; Thu, 17 Aug 2017 03:41:55 -0700 (PDT) In-Reply-To: <20170808132300.uyrrmgoij4qlwy52@kamzik.brq.redhat.com> References: <1500471597-2517-1-git-send-email-drjones@redhat.com> <20170808132300.uyrrmgoij4qlwy52@kamzik.brq.redhat.com> From: Peter Maydell Date: Thu, 17 Aug 2017 11:41:55 +0100 Message-ID: To: Andrew Jones Cc: QEMU Developers , qemu-arm , Alexander Graf , Christoffer Dall Content-Type: text/plain; charset="UTF-8" X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:400c:c0c::231 Subject: Re: [Qemu-arm] [Qemu-devel] [PATCH v2 0/4] ARM: KVM: Enable in-kernel PMU with user space gic X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 17 Aug 2017 10:42:19 -0000 On 8 August 2017 at 14:23, Andrew Jones wrote: > > Peter, > > ping? I've applied this to target-arm.next ready for the first 2.11 ARM pullreq. Sorry for the delay, I'd put not-for-2.10 patch review onto the back burner since I knew nothing was going to go into master til after the release... thanks -- PMM From MAILER-DAEMON Thu Aug 17 06:42:49 2017 Received: from list by lists.gnu.org with archive (Exim 4.71) id 1diIGH-0003mF-9H for mharc-qemu-arm@gnu.org; Thu, 17 Aug 2017 06:42:49 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:37571) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1diIGF-0003ks-7U for qemu-arm@nongnu.org; Thu, 17 Aug 2017 06:42:48 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1diIGE-0005Jv-D5 for qemu-arm@nongnu.org; Thu, 17 Aug 2017 06:42:47 -0400 Received: from mail-wr0-x229.google.com ([2a00:1450:400c:c0c::229]:37391) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1diIGE-0005JW-6N for qemu-arm@nongnu.org; Thu, 17 Aug 2017 06:42:46 -0400 Received: by mail-wr0-x229.google.com with SMTP id z91so30579441wrc.4 for ; Thu, 17 Aug 2017 03:42:46 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:in-reply-to:references:from:date:message-id:subject:to :cc:content-transfer-encoding; bh=HQ826KJNO2ja6qiiNyV7Pj8xorLqNPX8q4MG4UD5C7U=; b=NCf+oR/ocEDKPFR/Rb6Kpjo3Q9q8aumzrH/E4OkJq41a/Kf+fH7DBGddLeArvIlxUb m5SqoVqiFdv2cJkeLTXKoEJ9vzh5/cgYYUDDYUyj1Jsmv59Jf++0m4qxHE3FyxtWsbD/ BeynUo0JWoH8UuDg4o5sVNGvP5hvaN8Gs0SRg= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:in-reply-to:references:from:date :message-id:subject:to:cc:content-transfer-encoding; bh=HQ826KJNO2ja6qiiNyV7Pj8xorLqNPX8q4MG4UD5C7U=; b=b2RgfmixSmdozxF2gHX3UGEFSWzRDwOp5E/PMTnWilyANAE1+58IhOYho8w2mF+eCy 1uFSCOkm+mhbAvX1pqkBXs2Js3oZPSwOoMo50AobZyIwMASL6UWSFkEEq418NLMaqBOd wl+9oB8Z8G9uH9poQnencsh+gjDgNGZS4MfWYSmkjyNn+t0WPlaruDCXnuFoa5CgA+Qr SfBc6Tjtmpa0InlIfS5uJN7pGMKkefWLYtys8V5PiG9TjeQXmabU6RDIJPw7qUbLnJwT PcXeozFYy4iLFIb3jLYeByzE3gd0Xsfj2DIeSxx+P191hbnGCz6OInEI1T1yzsI/Pcu+ tqIQ== X-Gm-Message-State: AHYfb5gZlEf4fJUFFC97NZXyIzc7aJ8/EgTxZQBRQVyOTPOBIhSFlsj6 xvhQEcDTLGTJX0UKEHQUNFJufNCa8raC X-Received: by 10.28.55.4 with SMTP id e4mr1124311wma.37.1502966565097; Thu, 17 Aug 2017 03:42:45 -0700 (PDT) MIME-Version: 1.0 Received: by 10.223.134.54 with HTTP; Thu, 17 Aug 2017 03:42:24 -0700 (PDT) In-Reply-To: References: <20170717133010.12784-1-f4bug@amsat.org> From: Peter Maydell Date: Thu, 17 Aug 2017 11:42:24 +0100 Message-ID: To: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= Cc: qemu-arm , QEMU Developers , Igor Mitsyanko , Rob Herring , "Edgar E. Iglesias" , Alistair Francis Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:400c:c0c::229 Subject: Re: [Qemu-arm] [PATCH] hw/arm: use defined type name instead of hard-coded string X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 17 Aug 2017 10:42:48 -0000 On 31 July 2017 at 13:09, Peter Maydell wrote: > On 27 July 2017 at 14:48, Philippe Mathieu-Daud=C3=A9 w= rote: >> On 07/27/2017 09:36 AM, Peter Maydell wrote: >>> >>> On 17 July 2017 at 14:30, Philippe Mathieu-Daud=C3=A9 = wrote: >>>> >>>> Signed-off-by: Philippe Mathieu-Daud=C3=A9 >>>> --- >>>> >>>> Hi Peter, this patch is waiting the IDE queue to enters since it depen= ds >>>> of >>>> commit de09efcc7b67ada3593354711b12a03dea23a9d0 to fix AHCI includes. >>> >>> >>> There's no commit with that hash in master -- do you have >>> a commit subject or something that I can use to find out >>> whether it's landed or not? >> >> >> Oops I guess the IDE queue was rebased between this patch and the merge,= or >> I messed my copy/paste :) >> >> The dependent commit is 70e2337030f and has how entered /master, do you = want >> me to send an v2 with fixed message? Anyway I delayed this patch for 2.1= 1 >> since this is not a bugfix. > > You don't need to resend, I'll just keep it on my list of things > to deal with after 2.11. (Anything below the '---' isn't really > in the commit message anyway, it gets stripped out when the > patch is applied.) Patch now in target-arm.next ready for post-2.11 pullreq. thanks -- PMM From MAILER-DAEMON Thu Aug 17 06:47:02 2017 Received: from list by lists.gnu.org with archive (Exim 4.71) id 1diIKM-00071o-Nu for mharc-qemu-arm@gnu.org; Thu, 17 Aug 2017 06:47:02 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:38511) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1diIKK-0006zG-2O for qemu-arm@nongnu.org; Thu, 17 Aug 2017 06:47:00 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1diIKJ-0006Lp-7I for qemu-arm@nongnu.org; Thu, 17 Aug 2017 06:47:00 -0400 Received: from mail-wr0-x22a.google.com ([2a00:1450:400c:c0c::22a]:33815) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1diIKJ-0006LM-0x for qemu-arm@nongnu.org; Thu, 17 Aug 2017 06:46:59 -0400 Received: by mail-wr0-x22a.google.com with SMTP id y96so36733276wrc.1 for ; Thu, 17 Aug 2017 03:46:58 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:in-reply-to:references:from:date:message-id:subject:to :cc; bh=B5SlY4HnWxa6VcmTq1fdirtO781fN0N5xrUIp3u9iiY=; b=fpM6fMnQseJqBDVSBe5LVXy1yL4KL7G+nZrZZRmENU8GlFjipTP7jVXGv3iko1GvVl CHLU9PGYop2MNpxeQs85AL0lU1kc4cQeRn5JCCIKMBd8/4akuuvqinu+QV1JInvXT4gn esqjaaY92cCK3eK2h7nheG917oNbs+YABq548= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:in-reply-to:references:from:date :message-id:subject:to:cc; bh=B5SlY4HnWxa6VcmTq1fdirtO781fN0N5xrUIp3u9iiY=; b=n2XWwdYNMOVa+KLK6ZZ1lpfpWi/tamivH1IIcaelJAdq4iMz0d/ALsGZeOCBPXO6BP aIebkrEmX3uoo9OX0BkXQ3ciOyT2r217eis2bdta+9AJYCXfVsjEHykWIlNlEiGYuHAq xke2OjY4srq1CR19TS4iYaBBWEUKfr+qEkxKRINV5kK+n8baTif+GtYbI9rTVv55sEES Xc0KF50/GaslG/E/X2o17TEupGRhYhXePcYb74VmBpOso/upFeeruw4w0s3CEXxMf3YV eftkpjG1xUScLoHQUxJWMxSd6UgZHAwBpFz16l3oAZoHI6bsUneS1llNcKN9hxS905mk R0cg== X-Gm-Message-State: AHYfb5hjH7lGufZP7E5XdmdJazEOhmcFT6QMitsmlMDidgpyp3jCKuGR ajUsXpnPDVGKqrhUlbnUDy/eGyKwD7uavQ0= X-Received: by 10.28.193.10 with SMTP id r10mr614136wmf.157.1502966817911; Thu, 17 Aug 2017 03:46:57 -0700 (PDT) MIME-Version: 1.0 Received: by 10.223.134.54 with HTTP; Thu, 17 Aug 2017 03:46:37 -0700 (PDT) In-Reply-To: <20170809062828.3673-1-andrew@aj.id.au> References: <20170809062828.3673-1-andrew@aj.id.au> From: Peter Maydell Date: Thu, 17 Aug 2017 11:46:37 +0100 Message-ID: To: Andrew Jeffery Cc: qemu-arm , QEMU Developers , =?UTF-8?Q?C=C3=A9dric_Le_Goater?= , Joel Stanley , =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= , ryan_chen@aspeedtech.com, OpenBMC Maillist Content-Type: text/plain; charset="UTF-8" X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:400c:c0c::22a Subject: Re: [Qemu-arm] [PATCH for 2.11 v2 0/2] wdt_aspeed: Support reset width patterns X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 17 Aug 2017 10:47:01 -0000 On 9 August 2017 at 07:28, Andrew Jeffery wrote: > Hello, > > These two patches add support for the reset width configuration register in the > Aspeed watchdog. Initially this was just one patch[1], but I've reworked it as > two to explicitly support the varying capabilities between Aspeed SoC versions. > > Andrew > > [1] http://patchwork.ozlabs.org/patch/796039/ > > Andrew Jeffery (2): > watchdog: wdt_aspeed: Add support for the reset width register > aspeed_soc: Propagate silicon-rev to watchdog Applied to target-arm.next ready for when 2.11 development opens, thanks. -- PMM From MAILER-DAEMON Thu Aug 17 08:30:22 2017 Received: from list by lists.gnu.org with archive (Exim 4.71) id 1diJwM-00020c-5w for mharc-qemu-arm@gnu.org; Thu, 17 Aug 2017 08:30:22 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:33494) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1diJwJ-0001zz-KR for qemu-arm@nongnu.org; Thu, 17 Aug 2017 08:30:21 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1diJwE-000365-VQ for qemu-arm@nongnu.org; Thu, 17 Aug 2017 08:30:19 -0400 Received: from mx1.redhat.com ([209.132.183.28]:55662) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1diJwE-00035g-Lw; Thu, 17 Aug 2017 08:30:14 -0400 Received: from smtp.corp.redhat.com (int-mx02.intmail.prod.int.phx2.redhat.com [10.5.11.12]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id 09EA890154; Thu, 17 Aug 2017 12:30:13 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mx1.redhat.com 09EA890154 Authentication-Results: ext-mx01.extmail.prod.ext.phx2.redhat.com; dmarc=none (p=none dis=none) header.from=redhat.com Authentication-Results: ext-mx01.extmail.prod.ext.phx2.redhat.com; spf=fail smtp.mailfrom=armbru@redhat.com Received: from blackfin.pond.sub.org (ovpn-116-90.ams2.redhat.com [10.36.116.90]) by smtp.corp.redhat.com (Postfix) with ESMTPS id 996C27901A; Thu, 17 Aug 2017 12:30:04 +0000 (UTC) Received: by blackfin.pond.sub.org (Postfix, from userid 1000) id 76D1F1138646; Thu, 17 Aug 2017 14:30:01 +0200 (CEST) From: Markus Armbruster To: =?utf-8?Q?Marc-Andr=C3=A9?= Lureau Cc: qemu-devel@nongnu.org, Peter Maydell , Eduardo Habkost , "Dr. David Alan Gilbert" , Alexander Graf , "open list\:ARM" , "open list\:PowerPC" , Paolo Bonzini , David Gibson , Richard Henderson References: <20170727154126.11339-1-marcandre.lureau@redhat.com> <20170727154126.11339-27-marcandre.lureau@redhat.com> Date: Thu, 17 Aug 2017 14:30:01 +0200 In-Reply-To: <20170727154126.11339-27-marcandre.lureau@redhat.com> (=?utf-8?Q?=22Marc-Andr=C3=A9?= Lureau"'s message of "Thu, 27 Jul 2017 17:41:26 +0200") Message-ID: <87shgqcr7a.fsf@dusky.pond.sub.org> User-Agent: Gnus/5.13 (Gnus v5.13) Emacs/25.2 (gnu/linux) MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 2.79 on 10.5.11.12 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.25]); Thu, 17 Aug 2017 12:30:13 +0000 (UTC) X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.132.183.28 Subject: Re: [Qemu-arm] [Qemu-devel] [PATCH 26/26] qapi: make query-cpu-definitions depend on specific targets X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 17 Aug 2017 12:30:21 -0000 Marc-Andr=C3=A9 Lureau writes: > It depends on TARGET_PPC || TARGET_ARM || TARGET_I386 || TARGET_S390X. > > Signed-off-by: Marc-Andr=C3=A9 Lureau > --- > qapi-schema.json | 4 +++- > include/sysemu/arch_init.h | 2 -- > monitor.c | 22 ---------------------- > qmp.c | 5 ----- > stubs/arch-query-cpu-def.c | 10 ---------- > target/arm/helper.c | 3 ++- > target/i386/cpu.c | 3 ++- > target/ppc/translate_init.c | 3 ++- > target/s390x/cpu_models.c | 2 +- > stubs/Makefile.objs | 1 - > 10 files changed, 10 insertions(+), 45 deletions(-) > delete mode 100644 stubs/arch-query-cpu-def.c > > diff --git a/qapi-schema.json b/qapi-schema.json > index f5e1acff83..8e3949bca8 100644 > --- a/qapi-schema.json > +++ b/qapi-schema.json > @@ -4433,7 +4433,9 @@ > # > # Since: 1.2.0 > ## > -{ 'command': 'query-cpu-definitions', 'returns': ['CpuDefinitionInfo'] } > +{ 'command': 'query-cpu-definitions', 'returns': ['CpuDefinitionInfo'], > + 'if': ['defined(NEED_CPU_H)', > + 'defined(TARGET_PPC) || defined(TARGET_ARM) || defined(TARGET_I= 386) || defined(TARGET_S390X)'] } >=20=20 > ## > # @CpuModelInfo: > diff --git a/include/sysemu/arch_init.h b/include/sysemu/arch_init.h > index fb3d20a1b8..e9721b9ce8 100644 > --- a/include/sysemu/arch_init.h > +++ b/include/sysemu/arch_init.h > @@ -31,6 +31,4 @@ extern const uint32_t arch_type; > int kvm_available(void); > int xen_available(void); >=20=20 > -CpuDefinitionInfoList *arch_query_cpu_definitions(Error **errp); > - > #endif > diff --git a/monitor.c b/monitor.c > index b134c39144..6600819599 100644 > --- a/monitor.c > +++ b/monitor.c > @@ -956,26 +956,6 @@ static void qmp_query_qmp_schema(QDict *qdict, QObje= ct **ret_data, > *ret_data =3D qobject_from_qlit(&qmp_schema_qlit); > } >=20=20 > -/* > - * We used to define commands in qmp-commands.hx in addition to the > - * QAPI schema. This permitted defining some of them only in certain > - * configurations. query-commands has always reflected that (good, > - * because it lets QMP clients figure out what's actually available), > - * while query-qmp-schema never did (not so good). This function is a > - * hack to keep the configuration-specific commands defined exactly as > - * before, even though qmp-commands.hx is gone. > - * > - * FIXME Educate the QAPI schema on configuration-specific commands, > - * and drop this hack. > - */ > -static void qmp_unregister_commands_hack(void) > -{ > -#if !defined(TARGET_PPC) && !defined(TARGET_ARM) && !defined(TARGET_I386= ) \ > - && !defined(TARGET_S390X) > - qmp_unregister_command(&qmp_commands, "query-cpu-definitions"); > -#endif > -} > - Very nice to see this gone. Its removal could be made a separate commit to highlight the achievement :) There are a few more candidates: * QERR_FEATURE_DISABLED leads me to - query-hotpluggable-cpus via monitor.c - x-colo-lost-heartbeat via colo-failover.c - query-rocker, query-rocker-ports, query-rocker-of-dpa-flows, query-rocker-of-dpa-groups via qmp-norocker.c * QERR_UNSUPPORTED leads me to - dump-guest-memory via dump_init() and stubs/dump.c - query-vm-generation-id via stubs/vmgenid.c - inject-nmi via nmi_monitor_handle() and s390_nmi() - query-pci via pci-stub.c * grep error_set stubs/* doesn't find more > void monitor_init_qmp_commands(void) > { > /* > @@ -995,8 +975,6 @@ void monitor_init_qmp_commands(void) > qmp_register_command(&qmp_commands, "netdev_add", qmp_netdev_add, > QCO_NO_OPTIONS); >=20=20 > - qmp_unregister_commands_hack(); > - > QTAILQ_INIT(&qmp_cap_negotiation_commands); > qmp_register_command(&qmp_cap_negotiation_commands, "qmp_capabilitie= s", > qmp_marshal_qmp_capabilities, QCO_NO_OPTIONS); > diff --git a/qmp.c b/qmp.c > index afa266ec1e..d57ccf1251 100644 > --- a/qmp.c > +++ b/qmp.c > @@ -541,11 +541,6 @@ DevicePropertyInfoList *qmp_device_list_properties(c= onst char *typename, > return prop_list; > } >=20=20 > -CpuDefinitionInfoList *qmp_query_cpu_definitions(Error **errp) > -{ > - return arch_query_cpu_definitions(errp); > -} > - > void qmp_add_client(const char *protocol, const char *fdname, > bool has_skipauth, bool skipauth, bool has_tls, bool= tls, > Error **errp) > diff --git a/stubs/arch-query-cpu-def.c b/stubs/arch-query-cpu-def.c > deleted file mode 100644 > index cefe4beb82..0000000000 > --- a/stubs/arch-query-cpu-def.c > +++ /dev/null > @@ -1,10 +0,0 @@ > -#include "qemu/osdep.h" > -#include "qemu-common.h" > -#include "sysemu/arch_init.h" > -#include "qapi/qmp/qerror.h" > - > -CpuDefinitionInfoList *arch_query_cpu_definitions(Error **errp) > -{ > - error_setg(errp, QERR_UNSUPPORTED); > - return NULL; > -} > diff --git a/target/arm/helper.c b/target/arm/helper.c > index 4ed32c56b8..ec644f3930 100644 > --- a/target/arm/helper.c > +++ b/target/arm/helper.c > @@ -15,6 +15,7 @@ > #include /* For crc32 */ > #include "exec/semihost.h" > #include "sysemu/kvm.h" > +#include "qmp-commands.h" >=20=20 > #define ARM_CPU_FREQ 1000000000 /* FIXME: 1 GHz, should be configurable = */ >=20=20 > @@ -5336,7 +5337,7 @@ static void arm_cpu_add_definition(gpointer data, g= pointer user_data) > *cpu_list =3D entry; > } >=20=20 > -CpuDefinitionInfoList *arch_query_cpu_definitions(Error **errp) > +CpuDefinitionInfoList *qmp_query_cpu_definitions(Error **errp) > { > CpuDefinitionInfoList *cpu_list =3D NULL; > GSList *list; > diff --git a/target/i386/cpu.c b/target/i386/cpu.c > index d683e70a13..e5f61f6bff 100644 > --- a/target/i386/cpu.c > +++ b/target/i386/cpu.c > @@ -36,6 +36,7 @@ > #include "qapi/visitor.h" > #include "qom/qom-qobject.h" > #include "sysemu/arch_init.h" > +#include "qmp-commands.h" >=20=20 > #if defined(CONFIG_KVM) > #include > @@ -2318,7 +2319,7 @@ static void x86_cpu_definition_entry(gpointer data,= gpointer user_data) > *cpu_list =3D entry; > } >=20=20 > -CpuDefinitionInfoList *arch_query_cpu_definitions(Error **errp) > +CpuDefinitionInfoList *qmp_query_cpu_definitions(Error **errp) > { > CpuDefinitionInfoList *cpu_list =3D NULL; > GSList *list =3D get_sorted_cpu_model_list(); > diff --git a/target/ppc/translate_init.c b/target/ppc/translate_init.c > index 01723bdfec..2a2d62e5bb 100644 > --- a/target/ppc/translate_init.c > +++ b/target/ppc/translate_init.c > @@ -34,6 +34,7 @@ > #include "hw/ppc/ppc.h" > #include "mmu-book3s-v3.h" > #include "sysemu/qtest.h" > +#include "qmp-commands.h" >=20=20 > //#define PPC_DUMP_CPU > //#define PPC_DEBUG_SPR > @@ -10391,7 +10392,7 @@ static void ppc_cpu_defs_entry(gpointer data, gpo= inter user_data) > *first =3D entry; > } >=20=20 > -CpuDefinitionInfoList *arch_query_cpu_definitions(Error **errp) > +CpuDefinitionInfoList *qmp_query_cpu_definitions(Error **errp) > { > CpuDefinitionInfoList *cpu_list =3D NULL; > GSList *list; > diff --git a/target/s390x/cpu_models.c b/target/s390x/cpu_models.c > index 863dce064f..8021dda341 100644 > --- a/target/s390x/cpu_models.c > +++ b/target/s390x/cpu_models.c > @@ -387,7 +387,7 @@ static void create_cpu_model_list(ObjectClass *klass,= void *opaque) > *cpu_list =3D entry; > } >=20=20 > -CpuDefinitionInfoList *arch_query_cpu_definitions(Error **errp) > +CpuDefinitionInfoList *qmp_query_cpu_definitions(Error **errp) > { > struct CpuDefinitionInfoListData list_data =3D { > .list =3D NULL, > diff --git a/stubs/Makefile.objs b/stubs/Makefile.objs > index dcfe6f49f9..71af433f6b 100644 > --- a/stubs/Makefile.objs > +++ b/stubs/Makefile.objs > @@ -1,4 +1,3 @@ > -stub-obj-y +=3D arch-query-cpu-def.o > stub-obj-y +=3D bdrv-next-monitor-owned.o > stub-obj-y +=3D blk-commit-all.o > stub-obj-y +=3D blockdev-close-all-bdrv-states.o From MAILER-DAEMON Thu Aug 17 09:37:15 2017 Received: from list by lists.gnu.org with archive (Exim 4.71) id 1diKz5-0001jm-Re for mharc-qemu-arm@gnu.org; Thu, 17 Aug 2017 09:37:15 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:48857) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1diKz3-0001j5-KW for qemu-arm@nongnu.org; Thu, 17 Aug 2017 09:37:14 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1diKyz-0000ui-Eq for qemu-arm@nongnu.org; Thu, 17 Aug 2017 09:37:13 -0400 Received: from foss.arm.com ([217.140.101.70]:57852) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1diKyz-0000t6-8c; Thu, 17 Aug 2017 09:37:09 -0400 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 84AA680D; Thu, 17 Aug 2017 06:37:06 -0700 (PDT) Received: from [10.1.211.72] (e106794-lin.cambridge.arm.com [10.1.211.72]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id D3FEE3F483; Thu, 17 Aug 2017 06:37:03 -0700 (PDT) To: Linu Cherian , Eric Auger Cc: eric.auger.pro@gmail.com, peter.maydell@linaro.org, alex.williamson@redhat.com, mst@redhat.com, qemu-arm@nongnu.org, qemu-devel@nongnu.org, kevin.tian@intel.com, marc.zyngier@arm.com, tn@semihalf.com, will.deacon@arm.com, drjones@redhat.com, peterx@redhat.com, bharat.bhushan@nxp.com, christoffer.dall@linaro.org, linu.cherian@cavium.com References: <1501579994-3320-1-git-send-email-eric.auger@redhat.com> <20170817112627.GA5417@virtx40> From: Jean-Philippe Brucker Message-ID: Date: Thu, 17 Aug 2017 14:39:34 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.2.1 MIME-Version: 1.0 In-Reply-To: <20170817112627.GA5417@virtx40> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 7bit X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 217.140.101.70 Subject: Re: [Qemu-arm] [RFC v3 0/8] VIRTIO-IOMMU device X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 17 Aug 2017 13:37:14 -0000 Hi Linu, On 17/08/17 12:26, Linu Cherian wrote: > Hi Eric, > > On Tue Aug 01, 2017 at 11:33:06AM +0200, Eric Auger wrote: >> This series implements the virtio-iommu device. >> >> This v3 mostly is a rebase on top of v2.10-rc0 that uses >> IOMMUMmeoryRegion plus some small fixes. >> >> This is a proof of concept based on the virtio-iommu specification >> written by Jean-Philippe Brucker [1]. >> >> The device gets instantiated using the "-device virtio-iommu-device" >> option. It currently works with ARM virt machine only, as the machine >> must handle the dt binding between the virtio-mmio "iommu" node and >> the PCI host bridge node. >> >> ACPI booting is not yet supported. >> >> Best Regards >> >> Eric >> >> This series can be found at: >> https://github.com/eauger/qemu/tree/v2.10.0-rc0-virtio-iommu-rfcv3 >> >> References: >> [1] [RFC 0/3] virtio-iommu: a paravirtualized IOMMU, >> [2] [RFC PATCH linux] iommu: Add virtio-iommu driver >> [3] [RFC PATCH kvmtool 00/15] Add virtio-iommu >> >> Testing: >> - >= 4.12 guest kernel + virtio-iommu driver [2] >> - guest using a virtio-net-pci device: >> ,vhost=off,iommu_platform,disable-modern=off,disable-legacy=on > > Was trying to test this out and facing issues. > Guest and Host Kernel - git://linux-arm.org/linux-jpb.git, Branch virtio-iommu/v0.4 > Qemu - As mentioned above. Could you try branch virtio-iommu/v0.1? It contains the UAPI headers compatible with this RFC. Thanks, Jean From MAILER-DAEMON Thu Aug 17 09:40:43 2017 Received: from list by lists.gnu.org with archive (Exim 4.71) id 1diL2R-00042z-40 for mharc-qemu-arm@gnu.org; Thu, 17 Aug 2017 09:40:43 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:47094) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1diIwv-0006zp-0O for qemu-arm@nongnu.org; Thu, 17 Aug 2017 07:26:54 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1diIwr-00029K-0V for qemu-arm@nongnu.org; Thu, 17 Aug 2017 07:26:53 -0400 Received: from mail-pg0-x243.google.com ([2607:f8b0:400e:c05::243]:34070) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1diIwq-00027x-NT; Thu, 17 Aug 2017 07:26:48 -0400 Received: by mail-pg0-x243.google.com with SMTP id y192so9427014pgd.1; Thu, 17 Aug 2017 04:26:46 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=date:from:to:cc:subject:message-id:references:mime-version :content-disposition:in-reply-to:user-agent; bh=CBz69l0beCrO0+Y18mCzFPSF8y9Tr6w/+AaCsOOqUjQ=; b=jqss9hLg3ypPxWH1uBvLBqUscgmqB5U+PqSKVN9zMDfShRqVeju8OaodkT7hmed54K zuJfCJc5tdi+6IV2+qk+zdCvHfgPyOT8Xw+1Mjw0WjbGeDwoKQb/ASGCLenDOcCyGrWd dqc5aEXhN0aH4lYc7eKBrqNvR87Oek8LjQqx2JnqtwmakMoP+w996amI6i0a+ujiJ2PA c2tRg1sym15h+z07VkSuvRMB9R0CzVWz8INZ6crF/vNpDEC0sFpj9xFHol/m9gtNxudE mzumnnrYP1yHXh1yk9OiCh3x8/HuQm1IPdAJPiBcOKfPO89m1VfdQv9w6U4VaiT8J0IR I5/A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:in-reply-to:user-agent; bh=CBz69l0beCrO0+Y18mCzFPSF8y9Tr6w/+AaCsOOqUjQ=; b=pSdRHmI5dXRgGldlDFgs36vnXGd5dFnV5xnQx9hWuGmckyjxUTMwcIV9T+0RkTSj1U XX4fchN9ETRpUyMoqpvCsHOHIOxN+7dW6rXayzoSKMmuv3/CCC6QhsKcVhRe/v5jOKb0 t+sl2YbJEvuCNM/gem1xXBfLMMjg3oPAsqMpcA4mvcPGPYGUMu8Dlf3maKBIytldvI8p 8lLVbe0fPNax76bKyR5L0jSbAUT7X95wn7aKcO+0bIt9E2lwyKrV5gTSpiGwfORStB24 OG1wHEIgzplxSon3CZ4yC14LP8k7xqZP4I5IM2CF3cM8IwjAHqMtzBbyqjp7iUvF7fQv Aa8Q== X-Gm-Message-State: AHYfb5jWRjxKkBD/uapC8QE7lIqadaKV571w4QGHppdhvtD9veU6D+cu ScmFEftjg87JCQ== X-Received: by 10.98.82.197 with SMTP id g188mr4989014pfb.34.1502969204928; Thu, 17 Aug 2017 04:26:44 -0700 (PDT) Received: from virtx40 ([111.93.218.67]) by smtp.gmail.com with ESMTPSA id q185sm6636891pfb.119.2017.08.17.04.26.38 (version=TLS1_2 cipher=AES128-SHA bits=128/128); Thu, 17 Aug 2017 04:26:43 -0700 (PDT) Date: Thu, 17 Aug 2017 16:56:27 +0530 From: Linu Cherian To: Eric Auger Cc: eric.auger.pro@gmail.com, peter.maydell@linaro.org, alex.williamson@redhat.com, mst@redhat.com, qemu-arm@nongnu.org, qemu-devel@nongnu.org, jean-philippe.brucker@arm.com, kevin.tian@intel.com, marc.zyngier@arm.com, tn@semihalf.com, will.deacon@arm.com, drjones@redhat.com, peterx@redhat.com, bharat.bhushan@nxp.com, christoffer.dall@linaro.org, linu.cherian@cavium.com Message-ID: <20170817112627.GA5417@virtx40> References: <1501579994-3320-1-git-send-email-eric.auger@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1501579994-3320-1-git-send-email-eric.auger@redhat.com> User-Agent: Mutt/1.5.21 (2010-09-15) X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::243 X-Mailman-Approved-At: Thu, 17 Aug 2017 09:40:41 -0400 Subject: Re: [Qemu-arm] [RFC v3 0/8] VIRTIO-IOMMU device X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 17 Aug 2017 11:26:54 -0000 Hi Eric, On Tue Aug 01, 2017 at 11:33:06AM +0200, Eric Auger wrote: > This series implements the virtio-iommu device. > > This v3 mostly is a rebase on top of v2.10-rc0 that uses > IOMMUMmeoryRegion plus some small fixes. > > This is a proof of concept based on the virtio-iommu specification > written by Jean-Philippe Brucker [1]. > > The device gets instantiated using the "-device virtio-iommu-device" > option. It currently works with ARM virt machine only, as the machine > must handle the dt binding between the virtio-mmio "iommu" node and > the PCI host bridge node. > > ACPI booting is not yet supported. > > Best Regards > > Eric > > This series can be found at: > https://github.com/eauger/qemu/tree/v2.10.0-rc0-virtio-iommu-rfcv3 > > References: > [1] [RFC 0/3] virtio-iommu: a paravirtualized IOMMU, > [2] [RFC PATCH linux] iommu: Add virtio-iommu driver > [3] [RFC PATCH kvmtool 00/15] Add virtio-iommu > > Testing: > - >= 4.12 guest kernel + virtio-iommu driver [2] > - guest using a virtio-net-pci device: > ,vhost=off,iommu_platform,disable-modern=off,disable-legacy=on Was trying to test this out and facing issues. Guest and Host Kernel - git://linux-arm.org/linux-jpb.git, Branch virtio-iommu/v0.4 Qemu - As mentioned above. Relevant Qemu command - -device virtio-iommu-device \ -netdev type=tap,id=eth0,ifname=tap0,vhost=off,script=no,downscript=no \ -device virtio-net-pci,netdev=eth0,iommu_platform,disable-modern=off,disable-legacy=on Issue: Though guest boots with virtio-iommu device probe succuessful, virtio net device probe gets failed. 928763] virtio_iommu virtio0: aperture: 0x0-0xffffffffffffffff [ 0.933145] virtio_iommu virtio0: page mask: 0xfffffffffffff000 [ 0.937333] virtio_iommu virtio0: probe successful ... virtio_net: probe of virtio2 failed with error -12" Even before this failure, i did saw couple of repeated warnings. 73085] ------------[ cut here ]------------ [ 2.576330] WARNING: CPU: 0 PID: 49 at drivers/iommu/dma-iommu.c:904 iommu_dma_map_msi_msg+0x1dc/0x1f4 [ 2.582963] Modules linked in: [ 2.585210] CPU: 0 PID: 49 Comm: kworker/0:1 Tainted: G W 4.13.0-rc1-gd1949df-dirty #14 [ 2.591733] Hardware name: linux,dummy-virt (DT) [ 2.595062] Workqueue: events deferred_probe_work_func [ 2.598777] task: ffff80003e0c0d80 task.stack: ffff80003e104000 [ 2.603036] PC is at iommu_dma_map_msi_msg+0x1dc/0x1f4 [ 2.606745] LR is at iommu_dma_map_msi_msg+0x1dc/0x1f4 .... snip .... 2.735988] [] iommu_dma_map_msi_msg+0x1dc/0x1f4 [ 2.740429] [] its_irq_compose_msi_msg+0x5c/0x68 [ 2.744869] [] irq_chip_compose_msi_msg+0x5c/0x74 [ 2.749378] [] msi_domain_activate+0x24/0x4c [ 2.753577] [] __irq_domain_activate_irq+0x48/0x54 [ 2.758151] [] irq_domain_activate_irq+0x2c/0x48 [ 2.762593] [] msi_domain_alloc_irqs+0x150/0x214 [ 2.767038] [] pci_msi_setup_msi_irqs+0x5c/0x68 [ 2.771560] [] __pci_enable_msix+0x41c/0x4c0 [ 2.775778] [] pci_alloc_irq_vectors_affinity+0xac/0x160 [ 2.780709] [] vp_find_vqs_msix+0x148/0x440 [ 2.784848] [] vp_find_vqs+0xb0/0x1b8 [ 2.788624] [] vp_modern_find_vqs+0x50/0xa8 [ 2.792768] [] init_vqs+0x394/0x600 [ 2.796417] [] virtnet_probe+0x3c4/0x77c [ 2.800370] [] virtio_dev_probe+0x198/0x230 [ 2.804507] [] driver_probe_device+0x298/0x440 [ 2.808827] [] __device_attach_driver+0x9c/0x140 [ 2.813269] [] bus_for_each_drv+0x68/0xa8 [ 2.817283] [] __device_attach+0xcc/0x15c [ 2.821299] [] device_initial_probe+0x24/0x30 [ 2.825558] [] bus_probe_device+0x9c/0xa4 [ 2.829574] [] device_add+0x378/0x5c8 [ 2.833344] [] device_register+0x28/0x34 [ 2.837302] [] register_virtio_device+0xbc/0x10c [ 2.841747] [] virtio_pci_probe+0xdc/0x14c [ 2.845822] [] local_pci_probe+0x50/0xb4 [ 2.849784] [] pci_device_probe+0x168/0x178 [ 2.853926] [] driver_probe_device+0x298/0x440 [ 2.858243] [] __device_attach_driver+0x9c/0x140 [ 2.862681] [] bus_for_each_drv+0x68/0xa8 [ 2.866692] [] __device_attach+0xcc/0x15c [ 2.870707] [] device_initial_probe+0x24/0x30 [ 2.874966] [] bus_probe_device+0x9c/0xa4 [ 2.878982] [] deferred_probe_work_func+0xa0/0xec [ 2.883487] [] process_one_work+0x160/0x384 [ 2.887623] [] worker_thread+0x1f4/0x3d8 [ 2.891577] [] kthread+0x10c/0x138 [ 2.895165] [] ret_from_fork+0x10/0x20 Am i missing something ? > > History: > v2 -> v3: > - rebase on top of 2.10-rc0 and especially > [PATCH qemu v9 0/2] memory/iommu: QOM'fy IOMMU MemoryRegion > - add mutex init > - fix as->mappings deletion using g_tree_ref/unref > - when a dev is attached whereas it is already attached to > another address space, first detach it > - fix some error values > - page_sizes = TARGET_PAGE_MASK; > - I haven't changed the unmap() semantics yet, waiting for the > next virtio-iommu spec revision. > > v1 -> v2: > - fix redifinition of viommu_as typedef > > > Eric Auger (8): > update-linux-headers: import virtio_iommu.h > linux-headers: Update for virtio-iommu > virtio_iommu: add skeleton > virtio-iommu: Decode the command payload > virtio_iommu: Add the iommu regions > virtio-iommu: Implement the translation and commands > hw/arm/virt: Add 2.10 machine type > hw/arm/virt: Add virtio-iommu the virt board > > hw/arm/virt.c | 116 ++++- > hw/virtio/Makefile.objs | 1 + > hw/virtio/trace-events | 14 + > hw/virtio/virtio-iommu.c | 670 ++++++++++++++++++++++++++ > include/hw/arm/virt.h | 5 + > include/hw/virtio/virtio-iommu.h | 61 +++ > include/standard-headers/linux/virtio_ids.h | 1 + > include/standard-headers/linux/virtio_iommu.h | 142 ++++++ > linux-headers/linux/virtio_iommu.h | 1 + > scripts/update-linux-headers.sh | 3 + > 10 files changed, 1005 insertions(+), 9 deletions(-) > create mode 100644 hw/virtio/virtio-iommu.c > create mode 100644 include/hw/virtio/virtio-iommu.h > create mode 100644 include/standard-headers/linux/virtio_iommu.h > create mode 100644 linux-headers/linux/virtio_iommu.h > > -- > 2.5.5 > > -- Linu cherian From MAILER-DAEMON Thu Aug 17 09:40:43 2017 Received: from list by lists.gnu.org with archive (Exim 4.71) id 1diL2R-00043F-9j for mharc-qemu-arm@gnu.org; Thu, 17 Aug 2017 09:40:43 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:36825) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1diK9I-0007kd-GH for qemu-arm@nongnu.org; Thu, 17 Aug 2017 08:43:46 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1diK9G-0001PH-2m for qemu-arm@nongnu.org; Thu, 17 Aug 2017 08:43:44 -0400 Received: from mail-ua0-x242.google.com ([2607:f8b0:400c:c08::242]:35691) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1diK9A-0001Ni-Iq; Thu, 17 Aug 2017 08:43:36 -0400 Received: by mail-ua0-x242.google.com with SMTP id r9so914827uad.2; Thu, 17 Aug 2017 05:43:34 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=6Gcrs8FLLBC+2uhdfK43BIS/XU6XfM+3fBar2PqPxFc=; b=aTeAaVpb/skhYh2viKjUb2l8mK2kU6dO6L8aP37D6hu2c41mUkUUEzPibkXiy3Ms5Z mQcP07mMuLmgFxxEOLB+YTSc13TlIwEZbOGHsnPpWtb1AMO5BDMgTJqYaG22fH3gOhSC Iq3z3340ueTJ9C6MSJlwQJNxVdv5mrNL3pWqQaeMZ7Lbk36Q+lLPaSNfWaCGxbKZxP/M 4z31IU2aWGlA+yIMoIdLbytDosNU35HauLkAmfSbItNstPEszkAdEwz43sNS3Ktn7LC6 Eap+uPrIAUVaIgT2jf89Av6W24zSyNNs2ORxz9rVB0H3sw23FmX4Bf+zRlOtBZ8sI7O/ JuqA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=6Gcrs8FLLBC+2uhdfK43BIS/XU6XfM+3fBar2PqPxFc=; b=HWvXZyvwP1Imxi08R13upIO/9Md++vAo90VUOVTt8Sey+/GtirjjuIL9Ma7R0zP5c+ 2LyYmuBQQ/AXqap6sWSW3/8NM/smRBm4gisxiYyhwphtbZZ8kR5HWWLPITBHLxZVE0nb b7BlgE1J2rh0wGTiDGcn8Dj1tCta/nFeAYxH/QemaS6v+lYdQSUlpemqo/5/8vIO+AhW v4U4ETRSvwBya+goOhfVrw2g9JCtnvTRPoW9SssH5mRYfW/gx/Gsxho8jF58avVpY8Hq 9OmnhuGSLOOuIIEEzf+18EdJZDk43dgqGNf48oTaF0zvM5CP2PQ+aCFJAXNJEYxOgB1N 0CaQ== X-Gm-Message-State: AHYfb5j2Di0ioIUKf/8C8tJRbIu8ZYoRVRHbUQWKfBIwmMVbxNUmqnXc l97BIDcW0koQcSy+J+xJZe5ilu4gCA== X-Received: by 10.176.73.10 with SMTP id z10mr3044154uac.178.1502973814403; Thu, 17 Aug 2017 05:43:34 -0700 (PDT) MIME-Version: 1.0 References: <20170727154126.11339-1-marcandre.lureau@redhat.com> <20170727154126.11339-27-marcandre.lureau@redhat.com> <87shgqcr7a.fsf@dusky.pond.sub.org> In-Reply-To: <87shgqcr7a.fsf@dusky.pond.sub.org> From: =?UTF-8?B?TWFyYy1BbmRyw6kgTHVyZWF1?= Date: Thu, 17 Aug 2017 12:43:23 +0000 Message-ID: To: Markus Armbruster Cc: Peter Maydell , Eduardo Habkost , Alexander Graf , qemu-devel@nongnu.org, "open list:ARM" , "open list:PowerPC" , Paolo Bonzini , Richard Henderson , "Dr. David Alan Gilbert" , David Gibson Content-Type: multipart/alternative; boundary="001a1145b32c507df60556f25cb9" X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400c:c08::242 X-Mailman-Approved-At: Thu, 17 Aug 2017 09:40:41 -0400 Subject: Re: [Qemu-arm] [Qemu-devel] [PATCH 26/26] qapi: make query-cpu-definitions depend on specific targets X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 17 Aug 2017 12:43:47 -0000 --001a1145b32c507df60556f25cb9 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Hi On Thu, Aug 17, 2017 at 2:30 PM Markus Armbruster wrote= : > Marc-Andr=C3=A9 Lureau writes: > > > It depends on TARGET_PPC || TARGET_ARM || TARGET_I386 || TARGET_S390X. > > > > Signed-off-by: Marc-Andr=C3=A9 Lureau > > --- > > qapi-schema.json | 4 +++- > > include/sysemu/arch_init.h | 2 -- > > monitor.c | 22 ---------------------- > > qmp.c | 5 ----- > > stubs/arch-query-cpu-def.c | 10 ---------- > > target/arm/helper.c | 3 ++- > > target/i386/cpu.c | 3 ++- > > target/ppc/translate_init.c | 3 ++- > > target/s390x/cpu_models.c | 2 +- > > stubs/Makefile.objs | 1 - > > 10 files changed, 10 insertions(+), 45 deletions(-) > > delete mode 100644 stubs/arch-query-cpu-def.c > > > > diff --git a/qapi-schema.json b/qapi-schema.json > > index f5e1acff83..8e3949bca8 100644 > > --- a/qapi-schema.json > > +++ b/qapi-schema.json > > @@ -4433,7 +4433,9 @@ > > # > > # Since: 1.2.0 > > ## > > -{ 'command': 'query-cpu-definitions', 'returns': ['CpuDefinitionInfo']= } > > +{ 'command': 'query-cpu-definitions', 'returns': ['CpuDefinitionInfo']= , > > + 'if': ['defined(NEED_CPU_H)', > > + 'defined(TARGET_PPC) || defined(TARGET_ARM) || > defined(TARGET_I386) || defined(TARGET_S390X)'] } > > > > ## > > # @CpuModelInfo: > > diff --git a/include/sysemu/arch_init.h b/include/sysemu/arch_init.h > > index fb3d20a1b8..e9721b9ce8 100644 > > --- a/include/sysemu/arch_init.h > > +++ b/include/sysemu/arch_init.h > > @@ -31,6 +31,4 @@ extern const uint32_t arch_type; > > int kvm_available(void); > > int xen_available(void); > > > > -CpuDefinitionInfoList *arch_query_cpu_definitions(Error **errp); > > - > > #endif > > diff --git a/monitor.c b/monitor.c > > index b134c39144..6600819599 100644 > > --- a/monitor.c > > +++ b/monitor.c > > @@ -956,26 +956,6 @@ static void qmp_query_qmp_schema(QDict *qdict, > QObject **ret_data, > > *ret_data =3D qobject_from_qlit(&qmp_schema_qlit); > > } > > > > -/* > > - * We used to define commands in qmp-commands.hx in addition to the > > - * QAPI schema. This permitted defining some of them only in certain > > - * configurations. query-commands has always reflected that (good, > > - * because it lets QMP clients figure out what's actually available), > > - * while query-qmp-schema never did (not so good). This function is a > > - * hack to keep the configuration-specific commands defined exactly as > > - * before, even though qmp-commands.hx is gone. > > - * > > - * FIXME Educate the QAPI schema on configuration-specific commands, > > - * and drop this hack. > > - */ > > -static void qmp_unregister_commands_hack(void) > > -{ > > -#if !defined(TARGET_PPC) && !defined(TARGET_ARM) && > !defined(TARGET_I386) \ > > - && !defined(TARGET_S390X) > > - qmp_unregister_command(&qmp_commands, "query-cpu-definitions"); > > -#endif > > -} > > - > > Very nice to see this gone. Its removal could be made a separate commit > to highlight the achievement :) > > There are a few more candidates: > > * QERR_FEATURE_DISABLED leads me to > - query-hotpluggable-cpus via monitor.c > - x-colo-lost-heartbeat via colo-failover.c > - query-rocker, query-rocker-ports, query-rocker-of-dpa-flows, > query-rocker-of-dpa-groups via qmp-norocker.c > > * QERR_UNSUPPORTED leads me to > - dump-guest-memory via dump_init() and stubs/dump.c > - query-vm-generation-id via stubs/vmgenid.c > - inject-nmi via nmi_monitor_handle() and s390_nmi() > - query-pci via pci-stub.c > > * grep error_set stubs/* doesn't find more > I have started to look at other opportunities in https://github.com/elmarco/qemu/commits/qapi-if-more, but I have to revisit that once we have that series ready. I guess this could be done case by case later, and collaboratively. Thanks for the review so far, I'll get back to it soon. > > void monitor_init_qmp_commands(void) > > { > > /* > > @@ -995,8 +975,6 @@ void monitor_init_qmp_commands(void) > > qmp_register_command(&qmp_commands, "netdev_add", qmp_netdev_add, > > QCO_NO_OPTIONS); > > > > - qmp_unregister_commands_hack(); > > - > > QTAILQ_INIT(&qmp_cap_negotiation_commands); > > qmp_register_command(&qmp_cap_negotiation_commands, > "qmp_capabilities", > > qmp_marshal_qmp_capabilities, QCO_NO_OPTIONS)= ; > > diff --git a/qmp.c b/qmp.c > > index afa266ec1e..d57ccf1251 100644 > > --- a/qmp.c > > +++ b/qmp.c > > @@ -541,11 +541,6 @@ DevicePropertyInfoList > *qmp_device_list_properties(const char *typename, > > return prop_list; > > } > > > > -CpuDefinitionInfoList *qmp_query_cpu_definitions(Error **errp) > > -{ > > - return arch_query_cpu_definitions(errp); > > -} > > - > > void qmp_add_client(const char *protocol, const char *fdname, > > bool has_skipauth, bool skipauth, bool has_tls, > bool tls, > > Error **errp) > > diff --git a/stubs/arch-query-cpu-def.c b/stubs/arch-query-cpu-def.c > > deleted file mode 100644 > > index cefe4beb82..0000000000 > > --- a/stubs/arch-query-cpu-def.c > > +++ /dev/null > > @@ -1,10 +0,0 @@ > > -#include "qemu/osdep.h" > > -#include "qemu-common.h" > > -#include "sysemu/arch_init.h" > > -#include "qapi/qmp/qerror.h" > > - > > -CpuDefinitionInfoList *arch_query_cpu_definitions(Error **errp) > > -{ > > - error_setg(errp, QERR_UNSUPPORTED); > > - return NULL; > > -} > > diff --git a/target/arm/helper.c b/target/arm/helper.c > > index 4ed32c56b8..ec644f3930 100644 > > --- a/target/arm/helper.c > > +++ b/target/arm/helper.c > > @@ -15,6 +15,7 @@ > > #include /* For crc32 */ > > #include "exec/semihost.h" > > #include "sysemu/kvm.h" > > +#include "qmp-commands.h" > > > > #define ARM_CPU_FREQ 1000000000 /* FIXME: 1 GHz, should be configurabl= e > */ > > > > @@ -5336,7 +5337,7 @@ static void arm_cpu_add_definition(gpointer data, > gpointer user_data) > > *cpu_list =3D entry; > > } > > > > -CpuDefinitionInfoList *arch_query_cpu_definitions(Error **errp) > > +CpuDefinitionInfoList *qmp_query_cpu_definitions(Error **errp) > > { > > CpuDefinitionInfoList *cpu_list =3D NULL; > > GSList *list; > > diff --git a/target/i386/cpu.c b/target/i386/cpu.c > > index d683e70a13..e5f61f6bff 100644 > > --- a/target/i386/cpu.c > > +++ b/target/i386/cpu.c > > @@ -36,6 +36,7 @@ > > #include "qapi/visitor.h" > > #include "qom/qom-qobject.h" > > #include "sysemu/arch_init.h" > > +#include "qmp-commands.h" > > > > #if defined(CONFIG_KVM) > > #include > > @@ -2318,7 +2319,7 @@ static void x86_cpu_definition_entry(gpointer > data, gpointer user_data) > > *cpu_list =3D entry; > > } > > > > -CpuDefinitionInfoList *arch_query_cpu_definitions(Error **errp) > > +CpuDefinitionInfoList *qmp_query_cpu_definitions(Error **errp) > > { > > CpuDefinitionInfoList *cpu_list =3D NULL; > > GSList *list =3D get_sorted_cpu_model_list(); > > diff --git a/target/ppc/translate_init.c b/target/ppc/translate_init.c > > index 01723bdfec..2a2d62e5bb 100644 > > --- a/target/ppc/translate_init.c > > +++ b/target/ppc/translate_init.c > > @@ -34,6 +34,7 @@ > > #include "hw/ppc/ppc.h" > > #include "mmu-book3s-v3.h" > > #include "sysemu/qtest.h" > > +#include "qmp-commands.h" > > > > //#define PPC_DUMP_CPU > > //#define PPC_DEBUG_SPR > > @@ -10391,7 +10392,7 @@ static void ppc_cpu_defs_entry(gpointer data, > gpointer user_data) > > *first =3D entry; > > } > > > > -CpuDefinitionInfoList *arch_query_cpu_definitions(Error **errp) > > +CpuDefinitionInfoList *qmp_query_cpu_definitions(Error **errp) > > { > > CpuDefinitionInfoList *cpu_list =3D NULL; > > GSList *list; > > diff --git a/target/s390x/cpu_models.c b/target/s390x/cpu_models.c > > index 863dce064f..8021dda341 100644 > > --- a/target/s390x/cpu_models.c > > +++ b/target/s390x/cpu_models.c > > @@ -387,7 +387,7 @@ static void create_cpu_model_list(ObjectClass > *klass, void *opaque) > > *cpu_list =3D entry; > > } > > > > -CpuDefinitionInfoList *arch_query_cpu_definitions(Error **errp) > > +CpuDefinitionInfoList *qmp_query_cpu_definitions(Error **errp) > > { > > struct CpuDefinitionInfoListData list_data =3D { > > .list =3D NULL, > > diff --git a/stubs/Makefile.objs b/stubs/Makefile.objs > > index dcfe6f49f9..71af433f6b 100644 > > --- a/stubs/Makefile.objs > > +++ b/stubs/Makefile.objs > > @@ -1,4 +1,3 @@ > > -stub-obj-y +=3D arch-query-cpu-def.o > > stub-obj-y +=3D bdrv-next-monitor-owned.o > > stub-obj-y +=3D blk-commit-all.o > > stub-obj-y +=3D blockdev-close-all-bdrv-states.o > > -- Marc-Andr=C3=A9 Lureau --001a1145b32c507df60556f25cb9 Content-Type: text/html; charset="UTF-8" Content-Transfer-Encoding: quoted-printable
Hi

Marc-Andr=C3=A9 Lureau <marcandre.lureau@redhat.com> writes:=

> It depends on TARGET_PPC || TARGET_ARM || TARGET_I386 || TARGET_S390X.=
>
> Signed-off-by: Marc-Andr=C3=A9 Lureau <marcandre.lureau@redhat.com> > ---
>=C2=A0 qapi-schema.json=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 |=C2= =A0 4 +++-
>=C2=A0 include/sysemu/arch_init.h=C2=A0 |=C2=A0 2 --
>=C2=A0 monitor.c=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0| 22 ----------------------
>=C2=A0 qmp.c=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0|=C2=A0 5 -----
>=C2=A0 stubs/arch-query-cpu-def.c=C2=A0 | 10 ----------
>=C2=A0 target/arm/helper.c=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0|=C2=A0 3 += +-
>=C2=A0 target/i386/cpu.c=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0|=C2= =A0 3 ++-
>=C2=A0 target/ppc/translate_init.c |=C2=A0 3 ++-
>=C2=A0 target/s390x/cpu_models.c=C2=A0 =C2=A0|=C2=A0 2 +-
>=C2=A0 stubs/Makefile.objs=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0|=C2=A0 1 -=
>=C2=A0 10 files changed, 10 insertions(+), 45 deletions(-)
>=C2=A0 delete mode 100644 stubs/arch-query-cpu-def.c
>
> diff --git a/qapi-schema.json b/qapi-schema.json
> index f5e1acff83..8e3949bca8 100644
> --- a/qapi-schema.json
> +++ b/qapi-schema.json
> @@ -4433,7 +4433,9 @@
>=C2=A0 #
>=C2=A0 # Since: 1.2.0
>=C2=A0 ##
> -{ 'command': 'query-cpu-definitions', 'returns= 9;: ['CpuDefinitionInfo'] }
> +{ 'command': 'query-cpu-definitions', 'returns= 9;: ['CpuDefinitionInfo'],
> +=C2=A0 'if': ['defined(NEED_CPU_H)',
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0'defined(TARGET_PPC) || defined= (TARGET_ARM) || defined(TARGET_I386) || defined(TARGET_S390X)'] }
>
>=C2=A0 ##
>=C2=A0 # @CpuModelInfo:
> diff --git a/include/sysemu/arch_init.h b/include/sysemu/arch_init.h > index fb3d20a1b8..e9721b9ce8 100644
> --- a/include/sysemu/arch_init.h
> +++ b/include/sysemu/arch_init.h
> @@ -31,6 +31,4 @@ extern const uint32_t arch_type;
>=C2=A0 int kvm_available(void);
>=C2=A0 int xen_available(void);
>
> -CpuDefinitionInfoList *arch_query_cpu_definitions(Error **errp);
> -
>=C2=A0 #endif
> diff --git a/monitor.c b/monitor.c
> index b134c39144..6600819599 100644
> --- a/monitor.c
> +++ b/monitor.c
> @@ -956,26 +956,6 @@ static void qmp_query_qmp_schema(QDict *qdict, QO= bject **ret_data,
>=C2=A0 =C2=A0 =C2=A0 *ret_data =3D qobject_from_qlit(&qmp_schema_ql= it);
>=C2=A0 }
>
> -/*
> - * We used to define commands in qmp-commands.hx in addition to the > - * QAPI schema.=C2=A0 This permitted defining some of them only in ce= rtain
> - * configurations.=C2=A0 query-commands has always reflected that (go= od,
> - * because it lets QMP clients figure out what's actually availab= le),
> - * while query-qmp-schema never did (not so good).=C2=A0 This functio= n is a
> - * hack to keep the configuration-specific commands defined exactly a= s
> - * before, even though qmp-commands.hx is gone.
> - *
> - * FIXME Educate the QAPI schema on configuration-specific commands,<= br> > - * and drop this hack.
> - */
> -static void qmp_unregister_commands_hack(void)
> -{
> -#if !defined(TARGET_PPC) && !defined(TARGET_ARM) && != defined(TARGET_I386) \
> -=C2=A0 =C2=A0 && !defined(TARGET_S390X)
> -=C2=A0 =C2=A0 qmp_unregister_command(&qmp_commands, "query-c= pu-definitions");
> -#endif
> -}
> -

Very nice to see this gone.=C2=A0 Its removal could be made a separate comm= it
to highlight the achievement :)

There are a few more candidates:

* QERR_FEATURE_DISABLED leads me to
=C2=A0 - query-hotpluggable-cpus via monitor.c
=C2=A0 - x-colo-lost-heartbeat via colo-failover.c
=C2=A0 - query-rocker, query-rocker-ports, query-rocker-of-dpa-flows,
=C2=A0 =C2=A0 query-rocker-of-dpa-groups via qmp-norocker.c

* QERR_UNSUPPORTED leads me to
=C2=A0 - dump-guest-memory via dump_init() and stubs/dump.c
=C2=A0 - query-vm-generation-id via stubs/vmgenid.c
=C2=A0 - inject-nmi via nmi_monitor_handle() and s390_nmi()
=C2=A0 - query-pci via pci-stub.c

* grep error_set stubs/* doesn't find more

I have started to look at other opportunities in https://github.com/elmarco/q= emu/commits/qapi-if-more, but I have to revisit that once we have that = series ready. I guess this could be done case by case later, and collaborat= ively.
=C2=A0
Thanks for the review so far, I'll get b= ack to it soon.


>=C2=A0 void monitor_init_qmp_commands(void)
>=C2=A0 {
>=C2=A0 =C2=A0 =C2=A0 /*
> @@ -995,8 +975,6 @@ void monitor_init_qmp_commands(void)
>=C2=A0 =C2=A0 =C2=A0 qmp_register_command(&qmp_commands, "netd= ev_add", qmp_netdev_add,
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0QCO_NO_OPTIONS);
>
> -=C2=A0 =C2=A0 qmp_unregister_commands_hack();
> -
>=C2=A0 =C2=A0 =C2=A0 QTAILQ_INIT(&qmp_cap_negotiation_commands); >=C2=A0 =C2=A0 =C2=A0 qmp_register_command(&qmp_cap_negotiation_comm= ands, "qmp_capabilities",
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0qmp_marshal_qmp_capabilities, QCO_NO_OPTIONS); > diff --git a/qmp.c b/qmp.c
> index afa266ec1e..d57ccf1251 100644
> --- a/qmp.c
> +++ b/qmp.c
> @@ -541,11 +541,6 @@ DevicePropertyInfoList *qmp_device_list_propertie= s(const char *typename,
>=C2=A0 =C2=A0 =C2=A0 return prop_list;
>=C2=A0 }
>
> -CpuDefinitionInfoList *qmp_query_cpu_definitions(Error **errp)
> -{
> -=C2=A0 =C2=A0 return arch_query_cpu_definitions(errp);
> -}
> -
>=C2=A0 void qmp_add_client(const char *protocol, const char *fdname, >=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 bool has_skipauth, bool skipauth, bool has_tls, bool tls,
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 Error **errp)
> diff --git a/stubs/arch-query-cpu-def.c b/stubs/arch-query-cpu-def.c > deleted file mode 100644
> index cefe4beb82..0000000000
> --- a/stubs/arch-query-cpu-def.c
> +++ /dev/null
> @@ -1,10 +0,0 @@
> -#include "qemu/osdep.h"
> -#include "qemu-common.h"
> -#include "sysemu/arch_init.h"
> -#include "qapi/qmp/qerror.h"
> -
> -CpuDefinitionInfoList *arch_query_cpu_definitions(Error **errp)
> -{
> -=C2=A0 =C2=A0 error_setg(errp, QERR_UNSUPPORTED);
> -=C2=A0 =C2=A0 return NULL;
> -}
> diff --git a/target/arm/helper.c b/target/arm/helper.c
> index 4ed32c56b8..ec644f3930 100644
> --- a/target/arm/helper.c
> +++ b/target/arm/helper.c
> @@ -15,6 +15,7 @@
>=C2=A0 #include <zlib.h> /* For crc32 */
>=C2=A0 #include "exec/semihost.h"
>=C2=A0 #include "sysemu/kvm.h"
> +#include "qmp-commands.h"
>
>=C2=A0 #define ARM_CPU_FREQ 1000000000 /* FIXME: 1 GHz, should be confi= gurable */
>
> @@ -5336,7 +5337,7 @@ static void arm_cpu_add_definition(gpointer data= , gpointer user_data)
>=C2=A0 =C2=A0 =C2=A0 *cpu_list =3D entry;
>=C2=A0 }
>
> -CpuDefinitionInfoList *arch_query_cpu_definitions(Error **errp)
> +CpuDefinitionInfoList *qmp_query_cpu_definitions(Error **errp)
>=C2=A0 {
>=C2=A0 =C2=A0 =C2=A0 CpuDefinitionInfoList *cpu_list =3D NULL;
>=C2=A0 =C2=A0 =C2=A0 GSList *list;
> diff --git a/target/i386/cpu.c b/target/i386/cpu.c
> index d683e70a13..e5f61f6bff 100644
> --- a/target/i386/cpu.c
> +++ b/target/i386/cpu.c
> @@ -36,6 +36,7 @@
>=C2=A0 #include "qapi/visitor.h"
>=C2=A0 #include "qom/qom-qobject.h"
>=C2=A0 #include "sysemu/arch_init.h"
> +#include "qmp-commands.h"
>
>=C2=A0 #if defined(CONFIG_KVM)
>=C2=A0 #include <linux/kvm_para.h>
> @@ -2318,7 +2319,7 @@ static void x86_cpu_definition_entry(gpointer da= ta, gpointer user_data)
>=C2=A0 =C2=A0 =C2=A0 *cpu_list =3D entry;
>=C2=A0 }
>
> -CpuDefinitionInfoList *arch_query_cpu_definitions(Error **errp)
> +CpuDefinitionInfoList *qmp_query_cpu_definitions(Error **errp)
>=C2=A0 {
>=C2=A0 =C2=A0 =C2=A0 CpuDefinitionInfoList *cpu_list =3D NULL;
>=C2=A0 =C2=A0 =C2=A0 GSList *list =3D get_sorted_cpu_model_list();
> diff --git a/target/ppc/translate_init.c b/target/ppc/translate_init.c=
> index 01723bdfec..2a2d62e5bb 100644
> --- a/target/ppc/translate_init.c
> +++ b/target/ppc/translate_init.c
> @@ -34,6 +34,7 @@
>=C2=A0 #include "hw/ppc/ppc.h"
>=C2=A0 #include "mmu-book3s-v3.h"
>=C2=A0 #include "sysemu/qtest.h"
> +#include "qmp-commands.h"
>
>=C2=A0 //#define PPC_DUMP_CPU
>=C2=A0 //#define PPC_DEBUG_SPR
> @@ -10391,7 +10392,7 @@ static void ppc_cpu_defs_entry(gpointer data, = gpointer user_data)
>=C2=A0 =C2=A0 =C2=A0 *first =3D entry;
>=C2=A0 }
>
> -CpuDefinitionInfoList *arch_query_cpu_definitions(Error **errp)
> +CpuDefinitionInfoList *qmp_query_cpu_definitions(Error **errp)
>=C2=A0 {
>=C2=A0 =C2=A0 =C2=A0 CpuDefinitionInfoList *cpu_list =3D NULL;
>=C2=A0 =C2=A0 =C2=A0 GSList *list;
> diff --git a/target/s390x/cpu_models.c b/target/s390x/cpu_models.c
> index 863dce064f..8021dda341 100644
> --- a/target/s390x/cpu_models.c
> +++ b/target/s390x/cpu_models.c
> @@ -387,7 +387,7 @@ static void create_cpu_model_list(ObjectClass *kla= ss, void *opaque)
>=C2=A0 =C2=A0 =C2=A0 *cpu_list =3D entry;
>=C2=A0 }
>
> -CpuDefinitionInfoList *arch_query_cpu_definitions(Error **errp)
> +CpuDefinitionInfoList *qmp_query_cpu_definitions(Error **errp)
>=C2=A0 {
>=C2=A0 =C2=A0 =C2=A0 struct CpuDefinitionInfoListData list_data =3D { >=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 .list =3D NULL,
> diff --git a/stubs/Makefile.objs b/stubs/Makefile.objs
> index dcfe6f49f9..71af433f6b 100644
> --- a/stubs/Makefile.objs
> +++ b/stubs/Makefile.objs
> @@ -1,4 +1,3 @@
> -stub-obj-y +=3D arch-query-cpu-def.o
>=C2=A0 stub-obj-y +=3D bdrv-next-monitor-owned.o
>=C2=A0 stub-obj-y +=3D blk-commit-all.o
>=C2=A0 stub-obj-y +=3D blockdev-close-all-bdrv-states.o

--
Marc-A= ndr=C3=A9 Lureau
--001a1145b32c507df60556f25cb9-- From MAILER-DAEMON Thu Aug 17 11:33:32 2017 Received: from list by lists.gnu.org with archive (Exim 4.71) id 1diMnb-0004us-VA for mharc-qemu-arm@gnu.org; Thu, 17 Aug 2017 11:33:31 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:56195) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1diMnZ-0004tz-OE for qemu-arm@nongnu.org; Thu, 17 Aug 2017 11:33:30 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1diMnW-0001SJ-KM for qemu-arm@nongnu.org; Thu, 17 Aug 2017 11:33:29 -0400 Received: from mx1.redhat.com ([209.132.183.28]:54256) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1diMnW-0001QM-Bq; Thu, 17 Aug 2017 11:33:26 -0400 Received: from smtp.corp.redhat.com (int-mx04.intmail.prod.int.phx2.redhat.com [10.5.11.14]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id 63F6D13AAD; Thu, 17 Aug 2017 15:33:22 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mx1.redhat.com 63F6D13AAD Authentication-Results: ext-mx05.extmail.prod.ext.phx2.redhat.com; dmarc=none (p=none dis=none) header.from=redhat.com Authentication-Results: ext-mx05.extmail.prod.ext.phx2.redhat.com; spf=fail smtp.mailfrom=eric.auger@redhat.com Received: from localhost.localdomain (ovpn-116-50.ams2.redhat.com [10.36.116.50]) by smtp.corp.redhat.com (Postfix) with ESMTPS id 81B055D9CC; Thu, 17 Aug 2017 15:33:12 +0000 (UTC) To: Bharat Bhushan , eric.auger.pro@gmail.com, peter.maydell@linaro.org, alex.williamson@redhat.com, mst@redhat.com, qemu-arm@nongnu.org, qemu-devel@nongnu.org References: <1500017104-3574-1-git-send-email-Bharat.Bhushan@nxp.com> <1500017104-3574-2-git-send-email-Bharat.Bhushan@nxp.com> Cc: wei@redhat.com, kevin.tian@intel.com, marc.zyngier@arm.com, tn@semihalf.com, will.deacon@arm.com, drjones@redhat.com, robin.murphy@arm.com, christoffer.dall@linaro.org From: Auger Eric Message-ID: Date: Thu, 17 Aug 2017 17:33:10 +0200 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:45.0) Gecko/20100101 Thunderbird/45.4.0 MIME-Version: 1.0 In-Reply-To: <1500017104-3574-2-git-send-email-Bharat.Bhushan@nxp.com> Content-Type: text/plain; charset=windows-1252 Content-Transfer-Encoding: 7bit X-Scanned-By: MIMEDefang 2.79 on 10.5.11.14 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.29]); Thu, 17 Aug 2017 15:33:22 +0000 (UTC) X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.132.183.28 Subject: Re: [Qemu-arm] [Qemu-devel] [RFC v2 PATCH 1/2] target/arm/kvm: Translate the MSI doorbell in kvm_arch_fixup_msi_route X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 17 Aug 2017 15:33:30 -0000 Hi Bharat, On 14/07/2017 09:25, Bharat Bhushan wrote: > Translate msi address if device is behind virtio-iommu. > This logic is similar to vSMMUv3/Intel iommu emulation. Why Intel? > > This RFC patch does not handle the case where both vsmmuv3 and > virtio-iommu are available. I think this should be hidden by the creation of a base vIOMMU object as initiated by Peter in: "[Qemu-devel] [RFC PATCH 0/8] IOMMU: introduce common IOMMUObject". I will try to rebase the virtio-iommu and vsmmuv3 series on this idea. Thanks Eric > > Signed-off-by: Bharat Bhushan > --- > v1-v2: > - Added trace events > - removed vSMMU3 link in patch description > > target/arm/kvm.c | 25 +++++++++++++++++++++++++ > target/arm/trace-events | 3 +++ > 2 files changed, 28 insertions(+) > > diff --git a/target/arm/kvm.c b/target/arm/kvm.c > index 4555468..5a28956 100644 > --- a/target/arm/kvm.c > +++ b/target/arm/kvm.c > @@ -21,7 +21,11 @@ > #include "kvm_arm.h" > #include "cpu.h" > #include "internals.h" > +#include "trace.h" > #include "hw/arm/arm.h" > +#include "hw/pci/pci.h" > +#include "hw/pci/msi.h" > +#include "hw/virtio/virtio-iommu.h" > #include "exec/memattrs.h" > #include "exec/address-spaces.h" > #include "hw/boards.h" > @@ -611,6 +615,27 @@ int kvm_arm_vgic_probe(void) > int kvm_arch_fixup_msi_route(struct kvm_irq_routing_entry *route, > uint64_t address, uint32_t data, PCIDevice *dev) > { > + AddressSpace *as = pci_device_iommu_address_space(dev); > + IOMMUTLBEntry entry; > + IOMMUDevice *sdev; > + VirtIOIOMMU *s; > + > + if (as == &address_space_memory) { > + return 0; > + } > + > + /* MSI doorbell address is translated by an IOMMU */ > + sdev = container_of(as, IOMMUDevice, as); > + s = sdev->viommu; > + > + entry = s->iommu_ops.translate(&sdev->iommu_mr, address, IOMMU_WO); > + > + route->u.msi.address_lo = entry.translated_addr; > + route->u.msi.address_hi = entry.translated_addr >> 32; > + > + trace_kvm_arm_fixup_msi_route(address, sdev->devfn, sdev->iommu_mr.name, > + entry.translated_addr); > + > return 0; > } > > diff --git a/target/arm/trace-events b/target/arm/trace-events > index e21c84f..eff2822 100644 > --- a/target/arm/trace-events > +++ b/target/arm/trace-events > @@ -8,3 +8,6 @@ arm_gt_tval_write(int timer, uint64_t value) "gt_tval_write: timer %d value %" P > arm_gt_ctl_write(int timer, uint64_t value) "gt_ctl_write: timer %d value %" PRIx64 > arm_gt_imask_toggle(int timer, int irqstate) "gt_ctl_write: timer %d IMASK toggle, new irqstate %d" > arm_gt_cntvoff_write(uint64_t value) "gt_cntvoff_write: value %" PRIx64 > + > +# target/arm/kvm.c > +kvm_arm_fixup_msi_route(uint64_t iova, uint32_t devid, const char *name, uint64_t gpa) "MSI addr = 0x%"PRIx64" is translated for devfn=%d through %s into 0x%"PRIx64 > From MAILER-DAEMON Thu Aug 17 11:33:38 2017 Received: from list by lists.gnu.org with archive (Exim 4.71) id 1diMni-0004zt-36 for mharc-qemu-arm@gnu.org; Thu, 17 Aug 2017 11:33:38 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:56243) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1diMne-0004xH-O8 for qemu-arm@nongnu.org; Thu, 17 Aug 2017 11:33:36 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1diMnd-0001Vt-0J for qemu-arm@nongnu.org; Thu, 17 Aug 2017 11:33:34 -0400 Received: from mx1.redhat.com ([209.132.183.28]:60386) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1diMnc-0001VJ-Mp; Thu, 17 Aug 2017 11:33:32 -0400 Received: from smtp.corp.redhat.com (int-mx04.intmail.prod.int.phx2.redhat.com [10.5.11.14]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id 886618764C; Thu, 17 Aug 2017 15:33:31 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mx1.redhat.com 886618764C Authentication-Results: ext-mx02.extmail.prod.ext.phx2.redhat.com; dmarc=none (p=none dis=none) header.from=redhat.com Authentication-Results: ext-mx02.extmail.prod.ext.phx2.redhat.com; spf=fail smtp.mailfrom=eric.auger@redhat.com Received: from localhost.localdomain (ovpn-116-50.ams2.redhat.com [10.36.116.50]) by smtp.corp.redhat.com (Postfix) with ESMTPS id 9E1E54FA22; Thu, 17 Aug 2017 15:33:27 +0000 (UTC) To: Bharat Bhushan , eric.auger.pro@gmail.com, peter.maydell@linaro.org, alex.williamson@redhat.com, mst@redhat.com, qemu-arm@nongnu.org, qemu-devel@nongnu.org References: <1500017104-3574-1-git-send-email-Bharat.Bhushan@nxp.com> <1500017104-3574-3-git-send-email-Bharat.Bhushan@nxp.com> Cc: wei@redhat.com, kevin.tian@intel.com, marc.zyngier@arm.com, tn@semihalf.com, will.deacon@arm.com, drjones@redhat.com, robin.murphy@arm.com, christoffer.dall@linaro.org From: Auger Eric Message-ID: <997bdcca-b84c-300c-bca0-5950c17db8d7@redhat.com> Date: Thu, 17 Aug 2017 17:33:26 +0200 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:45.0) Gecko/20100101 Thunderbird/45.4.0 MIME-Version: 1.0 In-Reply-To: <1500017104-3574-3-git-send-email-Bharat.Bhushan@nxp.com> Content-Type: text/plain; charset=windows-1252 Content-Transfer-Encoding: 7bit X-Scanned-By: MIMEDefang 2.79 on 10.5.11.14 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.26]); Thu, 17 Aug 2017 15:33:31 +0000 (UTC) X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.132.183.28 Subject: Re: [Qemu-arm] [Qemu-devel] [RFC v2 PATCH 2/2] virtio-iommu: vfio integration with virtio-iommu X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 17 Aug 2017 15:33:36 -0000 Hi Bharat, On 14/07/2017 09:25, Bharat Bhushan wrote: > This patch allows virtio-iommu protection for PCI > device-passthrough. > > MSI region is mapped by current version of virtio-iommu driver. > This MSI region mapping in not getting pushed on hw iommu > vfio_get_vaddr() allows only ram-region. Why is it an issue. As far as I understand this is not needed actually as the guest MSI doorbell is not used by the host. This RFC patch needed > to be improved. > > Signed-off-by: Bharat Bhushan > --- > v1-v2: > - Added trace events > > hw/virtio/trace-events | 5 ++ > hw/virtio/virtio-iommu.c | 133 +++++++++++++++++++++++++++++++++++++++ > include/hw/virtio/virtio-iommu.h | 6 ++ > 3 files changed, 144 insertions(+) > > diff --git a/hw/virtio/trace-events b/hw/virtio/trace-events > index 9196b63..3a3968b 100644 > --- a/hw/virtio/trace-events > +++ b/hw/virtio/trace-events > @@ -39,3 +39,8 @@ virtio_iommu_unmap_left_interval(uint64_t low, uint64_t high, uint64_t next_low, > virtio_iommu_unmap_right_interval(uint64_t low, uint64_t high, uint64_t next_low, uint64_t next_high) "Unmap right [0x%"PRIx64",0x%"PRIx64"], new interval=[0x%"PRIx64",0x%"PRIx64"]" > virtio_iommu_unmap_inc_interval(uint64_t low, uint64_t high) "Unmap inc [0x%"PRIx64",0x%"PRIx64"]" > virtio_iommu_translate_result(uint64_t virt_addr, uint64_t phys_addr, uint32_t sid) "0x%"PRIx64" -> 0x%"PRIx64 " for sid=%d" > +virtio_iommu_notify_flag_add(const char *iommu) "Add virtio-iommu notifier node for memory region %s" > +virtio_iommu_notify_flag_del(const char *iommu) "Del virtio-iommu notifier node for memory region %s" > +virtio_iommu_remap(hwaddr iova, hwaddr pa, hwaddr size) "iova=0x%"PRIx64" pa=0x%" PRIx64" size=0x%"PRIx64"" > +virtio_iommu_map_region(hwaddr iova, hwaddr paddr, hwaddr map_size) "iova=0x%"PRIx64" pa=0x%" PRIx64" size=0x%"PRIx64"" > +virtio_iommu_unmap_region(hwaddr iova, hwaddr paddr, hwaddr map_size) "iova=0x%"PRIx64" pa=0x%" PRIx64" size=0x%"PRIx64"" > diff --git a/hw/virtio/virtio-iommu.c b/hw/virtio/virtio-iommu.c > index cd188fc..61f33cb 100644 > --- a/hw/virtio/virtio-iommu.c > +++ b/hw/virtio/virtio-iommu.c > @@ -129,6 +129,48 @@ static gint interval_cmp(gconstpointer a, gconstpointer b, gpointer user_data) > } > } > > +static void virtio_iommu_map_region(VirtIOIOMMU *s, hwaddr iova, hwaddr paddr, > + hwaddr size, int map) bool map? the function name is a bit misleading to me and does not really explain what the function does. It "notifies" so why not using something like virtio_iommu_map_notify and virtio_iommu_unmap_notify. I tend to think having separate proto is cleaner and more standard. Binding should happen on a specific IOMMUmemoryRegion (see next comment). > +{ > + VirtioIOMMUNotifierNode *node; > + IOMMUTLBEntry entry; > + uint64_t map_size = (1 << 12); TODO: handle something else than 4K page. > + int npages; > + int i; > + > + npages = size / map_size; > + entry.target_as = &address_space_memory; > + entry.addr_mask = map_size - 1; > + > + for (i = 0; i < npages; i++) { Although I understand we currently fail checking the consistency between pIOMMU and vIOMMU page sizes, this will be very slow for guest DPDK use case where hugepages are used. Why not directly using the full size? vfio_iommu_map_notify will report errors if vfio_dma_map/unmap() fail. > + entry.iova = iova + (i * map_size); > + if (map) { > + trace_virtio_iommu_map_region(iova, paddr, map_size); > + entry.perm = IOMMU_RW; > + entry.translated_addr = paddr + (i * map_size); > + } else { > + trace_virtio_iommu_unmap_region(iova, paddr, map_size); > + entry.perm = IOMMU_NONE; > + entry.translated_addr = 0; > + } > + > + QLIST_FOREACH(node, &s->notifiers_list, next) { > + memory_region_notify_iommu(&node->iommu_dev->iommu_mr, entry); So as discussed this will notify *all* IOMMU memory regions and all their notifiers which is not what we want. You may have a look at vsmmuv3 v6 (or intel_iommu) where smmuv3_context_device_invalidate retrieves the mr from the sid. > + } > + } > +} > + > +static gboolean virtio_iommu_unmap_single(gpointer key, gpointer value, > + gpointer data) > +{ > + viommu_mapping *mapping = (viommu_mapping *) value; > + VirtIOIOMMU *s = (VirtIOIOMMU *) data; > + > + virtio_iommu_map_region(s, mapping->virt_addr, 0, mapping->size, 0); paddr=0? mapping->phys_addr as the trace() will be misleading. But as mentioned earlier better use unmap() separate function. > + > + return true; > +} > + > static int virtio_iommu_attach(VirtIOIOMMU *s, > struct virtio_iommu_req_attach *req) > { > @@ -170,10 +212,26 @@ static int virtio_iommu_detach(VirtIOIOMMU *s, > { > uint32_t devid = le32_to_cpu(req->device); > uint32_t reserved = le32_to_cpu(req->reserved); > + viommu_dev *dev; > int ret; > > trace_virtio_iommu_detach(devid, reserved); > > + dev = g_tree_lookup(s->devices, GUINT_TO_POINTER(devid)); > + if (!dev || !dev->as) { > + return -EINVAL; > + } > + > + dev->as->nr_devices--; > + > + /* Unmap all if this is last device detached */ > + if (dev->as->nr_devices == 0) { > + g_tree_foreach(dev->as->mappings, virtio_iommu_unmap_single, s); > + > + g_tree_remove(s->address_spaces, GUINT_TO_POINTER(dev->as->id)); > + g_tree_destroy(dev->as->mappings); > + } so this should be rebased on new ref count code. > + > ret = g_tree_remove(s->devices, GUINT_TO_POINTER(devid)); > > return ret ? VIRTIO_IOMMU_S_OK : VIRTIO_IOMMU_S_INVAL; > @@ -217,6 +275,7 @@ static int virtio_iommu_map(VirtIOIOMMU *s, > > g_tree_insert(as->mappings, interval, mapping); > > + virtio_iommu_map_region(s, virt_addr, phys_addr, size, 1); > return VIRTIO_IOMMU_S_OK; > } > > @@ -267,7 +326,9 @@ static int virtio_iommu_unmap(VirtIOIOMMU *s, > } else { > break; > } > + > if (interval.low >= interval.high) { > + virtio_iommu_map_region(s, virt_addr, 0, size, 0); > return VIRTIO_IOMMU_S_OK; > } else { > mapping = g_tree_lookup(as->mappings, (gpointer)&interval); > @@ -410,6 +471,37 @@ static void virtio_iommu_handle_command(VirtIODevice *vdev, VirtQueue *vq) > } > } > > +static void virtio_iommu_notify_flag_changed(MemoryRegion *iommu, > + IOMMUNotifierFlag old, > + IOMMUNotifierFlag new) > +{ > + IOMMUDevice *sdev = container_of(iommu, IOMMUDevice, iommu_mr); > + VirtIOIOMMU *s = sdev->viommu; > + VirtioIOMMUNotifierNode *node = NULL; > + VirtioIOMMUNotifierNode *next_node = NULL; > + > + if (old == IOMMU_NOTIFIER_NONE) { > + trace_virtio_iommu_notify_flag_add(iommu->name); > + node = g_malloc0(sizeof(*node)); > + node->iommu_dev = sdev; > + QLIST_INSERT_HEAD(&s->notifiers_list, node, next); > + return; > + } > + > + /* update notifier node with new flags */ > + QLIST_FOREACH_SAFE(node, &s->notifiers_list, next, next_node) { > + if (node->iommu_dev == sdev) { > + if (new == IOMMU_NOTIFIER_NONE) { > + trace_virtio_iommu_notify_flag_del(iommu->name); > + QLIST_REMOVE(node, next); > + g_free(node); > + } > + return; > + } > + } > +} I think all that mechanics should be factorized somewhere else as all vIOMMUs use that but this goes beyond the scope of this series. > + > + > static IOMMUTLBEntry virtio_iommu_translate(MemoryRegion *mr, hwaddr addr, > IOMMUAccessFlags flag) > { > @@ -523,11 +615,50 @@ static gint int_cmp(gconstpointer a, gconstpointer b, gpointer user_data) > return (ua > ub) - (ua < ub); > } > > +static gboolean virtio_iommu_remap(gpointer key, gpointer value, gpointer data) > +{ > + viommu_mapping *mapping = (viommu_mapping *) value; > + VirtIOIOMMU *s = (VirtIOIOMMU *) data; > + > + trace_virtio_iommu_remap(mapping->virt_addr, mapping->phys_addr, > + mapping->size); > + /* unmap previous entry and map again */ > + virtio_iommu_map_region(s, mapping->virt_addr, 0, mapping->size, 0); > + > + virtio_iommu_map_region(s, mapping->virt_addr, mapping->phys_addr, > + mapping->size, 1); > + return true; > +} > + > +static void virtio_iommu_replay(MemoryRegion *mr, IOMMUNotifier *n) > +{ > + IOMMUDevice *sdev = container_of(mr, IOMMUDevice, iommu_mr); > + VirtIOIOMMU *s = sdev->viommu; > + uint32_t sid; > + viommu_dev *dev; > + > + sid = smmu_get_sid(sdev); > + > + qemu_mutex_lock(&s->mutex); > + > + dev = g_tree_lookup(s->devices, GUINT_TO_POINTER(sid)); > + if (!dev) { > + goto unlock; > + } > + > + g_tree_foreach(dev->as->mappings, virtio_iommu_remap, s); > + > +unlock: > + qemu_mutex_unlock(&s->mutex); > + return; not needed Thanks Eric > +} > + > static void virtio_iommu_device_realize(DeviceState *dev, Error **errp) > { > VirtIODevice *vdev = VIRTIO_DEVICE(dev); > VirtIOIOMMU *s = VIRTIO_IOMMU(dev); > > + QLIST_INIT(&s->notifiers_list); > virtio_init(vdev, "virtio-iommu", VIRTIO_ID_IOMMU, > sizeof(struct virtio_iommu_config)); > > @@ -538,6 +669,8 @@ static void virtio_iommu_device_realize(DeviceState *dev, Error **errp) > s->config.input_range.end = -1UL; > > s->iommu_ops.translate = virtio_iommu_translate; > + s->iommu_ops.notify_flag_changed = virtio_iommu_notify_flag_changed; > + s->iommu_ops.replay = virtio_iommu_replay; > memset(s->as_by_bus_num, 0, sizeof(s->as_by_bus_num)); > s->as_by_busptr = g_hash_table_new_full(as_uint64_hash, > as_uint64_equal, > diff --git a/include/hw/virtio/virtio-iommu.h b/include/hw/virtio/virtio-iommu.h > index 2259413..76c758d 100644 > --- a/include/hw/virtio/virtio-iommu.h > +++ b/include/hw/virtio/virtio-iommu.h > @@ -44,6 +44,11 @@ typedef struct IOMMUPciBus { > IOMMUDevice *pbdev[0]; /* Parent array is sparse, so dynamically alloc */ > } IOMMUPciBus; > > +typedef struct VirtioIOMMUNotifierNode { > + IOMMUDevice *iommu_dev; > + QLIST_ENTRY(VirtioIOMMUNotifierNode) next; > +} VirtioIOMMUNotifierNode; > + > typedef struct VirtIOIOMMU { > VirtIODevice parent_obj; > VirtQueue *vq; > @@ -55,6 +60,7 @@ typedef struct VirtIOIOMMU { > GTree *address_spaces; > QemuMutex mutex; > GTree *devices; > + QLIST_HEAD(, VirtioIOMMUNotifierNode) notifiers_list; > } VirtIOIOMMU; > > #endif > From MAILER-DAEMON Thu Aug 17 11:33:53 2017 Received: from list by lists.gnu.org with archive (Exim 4.71) id 1diMnx-0005AH-1J for mharc-qemu-arm@gnu.org; Thu, 17 Aug 2017 11:33:53 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:56330) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1diMnu-000589-HY for qemu-arm@nongnu.org; Thu, 17 Aug 2017 11:33:51 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1diMnr-0001dy-ER for qemu-arm@nongnu.org; Thu, 17 Aug 2017 11:33:50 -0400 Received: from foss.arm.com ([217.140.101.70]:59576) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1diMnr-0001dG-95; Thu, 17 Aug 2017 11:33:47 -0400 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 71FF480D; Thu, 17 Aug 2017 08:33:45 -0700 (PDT) Received: from [10.1.211.72] (e106794-lin.cambridge.arm.com [10.1.211.72]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id B88823F3E1; Thu, 17 Aug 2017 08:33:42 -0700 (PDT) To: Auger Eric , Linu Cherian Cc: peter.maydell@linaro.org, kevin.tian@intel.com, drjones@redhat.com, mst@redhat.com, marc.zyngier@arm.com, tn@semihalf.com, will.deacon@arm.com, qemu-devel@nongnu.org, peterx@redhat.com, alex.williamson@redhat.com, qemu-arm@nongnu.org, linu.cherian@cavium.com, bharat.bhushan@nxp.com, christoffer.dall@linaro.org, eric.auger.pro@gmail.com References: <1501579994-3320-1-git-send-email-eric.auger@redhat.com> <20170817112627.GA5417@virtx40> <20c68b9d-380d-1fbc-0fae-a5af44c2cdb2@redhat.com> From: Jean-Philippe Brucker Message-ID: Date: Thu, 17 Aug 2017 16:36:13 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.2.1 MIME-Version: 1.0 In-Reply-To: <20c68b9d-380d-1fbc-0fae-a5af44c2cdb2@redhat.com> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 7bit X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 217.140.101.70 Subject: Re: [Qemu-arm] [Qemu-devel] [RFC v3 0/8] VIRTIO-IOMMU device X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 17 Aug 2017 15:33:51 -0000 On 17/08/17 16:26, Auger Eric wrote: > Hi Linu, Jean, > > On 17/08/2017 15:39, Jean-Philippe Brucker wrote: >> Hi Linu, >> >> On 17/08/17 12:26, Linu Cherian wrote: >>> Hi Eric, >>> >>> On Tue Aug 01, 2017 at 11:33:06AM +0200, Eric Auger wrote: >>>> This series implements the virtio-iommu device. >>>> >>>> This v3 mostly is a rebase on top of v2.10-rc0 that uses >>>> IOMMUMmeoryRegion plus some small fixes. >>>> >>>> This is a proof of concept based on the virtio-iommu specification >>>> written by Jean-Philippe Brucker [1]. >>>> >>>> The device gets instantiated using the "-device virtio-iommu-device" >>>> option. It currently works with ARM virt machine only, as the machine >>>> must handle the dt binding between the virtio-mmio "iommu" node and >>>> the PCI host bridge node. >>>> >>>> ACPI booting is not yet supported. >>>> >>>> Best Regards >>>> >>>> Eric >>>> >>>> This series can be found at: >>>> https://github.com/eauger/qemu/tree/v2.10.0-rc0-virtio-iommu-rfcv3 >>>> >>>> References: >>>> [1] [RFC 0/3] virtio-iommu: a paravirtualized IOMMU, >>>> [2] [RFC PATCH linux] iommu: Add virtio-iommu driver >>>> [3] [RFC PATCH kvmtool 00/15] Add virtio-iommu >>>> >>>> Testing: >>>> - >= 4.12 guest kernel + virtio-iommu driver [2] >>>> - guest using a virtio-net-pci device: >>>> ,vhost=off,iommu_platform,disable-modern=off,disable-legacy=on >>> >>> Was trying to test this out and facing issues. >>> Guest and Host Kernel - git://linux-arm.org/linux-jpb.git, Branch virtio-iommu/v0.4 >>> Qemu - As mentioned above. >> >> Could you try branch virtio-iommu/v0.1? It contains the UAPI headers >> compatible with this RFC. > Thank you Jean. Yes the QEMU virtio-iommu device is based on the first > user API written in [2]. I plan to rebase on v0.4 in short delay. Jean > can I rebase on virtio-iommu/v0.4 or shall I wait a bit more? Please go ahead, I don't have any pending changes at the moment :) Thanks, Jean From MAILER-DAEMON Thu Aug 17 11:36:17 2017 Received: from list by lists.gnu.org with archive (Exim 4.71) id 1diMqH-0007Cf-C5 for mharc-qemu-arm@gnu.org; Thu, 17 Aug 2017 11:36:17 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:56901) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1diMqF-0007AT-0M for qemu-arm@nongnu.org; Thu, 17 Aug 2017 11:36:16 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1diMqD-000342-4t for qemu-arm@nongnu.org; Thu, 17 Aug 2017 11:36:15 -0400 Received: from mx1.redhat.com ([209.132.183.28]:56266) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1diMqC-00031V-Uv; Thu, 17 Aug 2017 11:36:13 -0400 Received: from smtp.corp.redhat.com (int-mx04.intmail.prod.int.phx2.redhat.com [10.5.11.14]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id 1F72370000; Thu, 17 Aug 2017 15:27:06 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mx1.redhat.com 1F72370000 Authentication-Results: ext-mx03.extmail.prod.ext.phx2.redhat.com; dmarc=none (p=none dis=none) header.from=redhat.com Authentication-Results: ext-mx03.extmail.prod.ext.phx2.redhat.com; spf=fail smtp.mailfrom=eric.auger@redhat.com Received: from localhost.localdomain (ovpn-116-50.ams2.redhat.com [10.36.116.50]) by smtp.corp.redhat.com (Postfix) with ESMTPS id 51BCC5D9CC; Thu, 17 Aug 2017 15:26:56 +0000 (UTC) To: Jean-Philippe Brucker , Linu Cherian References: <1501579994-3320-1-git-send-email-eric.auger@redhat.com> <20170817112627.GA5417@virtx40> Cc: peter.maydell@linaro.org, kevin.tian@intel.com, drjones@redhat.com, mst@redhat.com, marc.zyngier@arm.com, tn@semihalf.com, will.deacon@arm.com, qemu-devel@nongnu.org, peterx@redhat.com, alex.williamson@redhat.com, qemu-arm@nongnu.org, linu.cherian@cavium.com, bharat.bhushan@nxp.com, christoffer.dall@linaro.org, eric.auger.pro@gmail.com From: Auger Eric Message-ID: <20c68b9d-380d-1fbc-0fae-a5af44c2cdb2@redhat.com> Date: Thu, 17 Aug 2017 17:26:53 +0200 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:45.0) Gecko/20100101 Thunderbird/45.4.0 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: 7bit X-Scanned-By: MIMEDefang 2.79 on 10.5.11.14 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.27]); Thu, 17 Aug 2017 15:27:06 +0000 (UTC) X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.132.183.28 Subject: Re: [Qemu-arm] [Qemu-devel] [RFC v3 0/8] VIRTIO-IOMMU device X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 17 Aug 2017 15:36:16 -0000 Hi Linu, Jean, On 17/08/2017 15:39, Jean-Philippe Brucker wrote: > Hi Linu, > > On 17/08/17 12:26, Linu Cherian wrote: >> Hi Eric, >> >> On Tue Aug 01, 2017 at 11:33:06AM +0200, Eric Auger wrote: >>> This series implements the virtio-iommu device. >>> >>> This v3 mostly is a rebase on top of v2.10-rc0 that uses >>> IOMMUMmeoryRegion plus some small fixes. >>> >>> This is a proof of concept based on the virtio-iommu specification >>> written by Jean-Philippe Brucker [1]. >>> >>> The device gets instantiated using the "-device virtio-iommu-device" >>> option. It currently works with ARM virt machine only, as the machine >>> must handle the dt binding between the virtio-mmio "iommu" node and >>> the PCI host bridge node. >>> >>> ACPI booting is not yet supported. >>> >>> Best Regards >>> >>> Eric >>> >>> This series can be found at: >>> https://github.com/eauger/qemu/tree/v2.10.0-rc0-virtio-iommu-rfcv3 >>> >>> References: >>> [1] [RFC 0/3] virtio-iommu: a paravirtualized IOMMU, >>> [2] [RFC PATCH linux] iommu: Add virtio-iommu driver >>> [3] [RFC PATCH kvmtool 00/15] Add virtio-iommu >>> >>> Testing: >>> - >= 4.12 guest kernel + virtio-iommu driver [2] >>> - guest using a virtio-net-pci device: >>> ,vhost=off,iommu_platform,disable-modern=off,disable-legacy=on >> >> Was trying to test this out and facing issues. >> Guest and Host Kernel - git://linux-arm.org/linux-jpb.git, Branch virtio-iommu/v0.4 >> Qemu - As mentioned above. > > Could you try branch virtio-iommu/v0.1? It contains the UAPI headers > compatible with this RFC. Thank you Jean. Yes the QEMU virtio-iommu device is based on the first user API written in [2]. I plan to rebase on v0.4 in short delay. Jean can I rebase on virtio-iommu/v0.4 or shall I wait a bit more? Thanks Eric > > Thanks, > Jean > From MAILER-DAEMON Thu Aug 17 14:04:16 2017 Received: from list by lists.gnu.org with archive (Exim 4.71) id 1diP9U-00044Z-9m for mharc-qemu-arm@gnu.org; Thu, 17 Aug 2017 14:04:16 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:37435) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1diP9R-000434-W1 for qemu-arm@nongnu.org; Thu, 17 Aug 2017 14:04:15 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1diP9N-0005GP-61 for qemu-arm@nongnu.org; Thu, 17 Aug 2017 14:04:13 -0400 Received: from mail-wr0-x229.google.com ([2a00:1450:400c:c0c::229]:33105) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1diP9M-0005Fb-VZ for qemu-arm@nongnu.org; Thu, 17 Aug 2017 14:04:09 -0400 Received: by mail-wr0-x229.google.com with SMTP id b65so50611651wrd.0 for ; Thu, 17 Aug 2017 11:04:08 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=MB+PXXB6umsS0QP7qT6V2jBQgssQbx5IiHKDlGxcoXY=; b=U56+y9+xFluDLG7d5k07kN+g1t49cBqCNAXuEMw4FKJevuSbL85oMcz2gMPiDU7x77 N6EMhwiamfYJ+3OWT7B38PB4oONlpqKpU0jKymjMSMWXLyFAY4dUmkA21/Dq3hOxXTjE B2GF4Vd4RkVBAVqNDQHZKrK/CkLcUO7hsG1zk= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=MB+PXXB6umsS0QP7qT6V2jBQgssQbx5IiHKDlGxcoXY=; b=f/0XDPHDNIrFQCYxC1IiWDoHj0PUmZgvHjBf6MQ6mrrvFGu6jmVz6DEZzTpHneU3Aq 9YNpA5OIUoYbLXEnk+6Za3Zv2Sp4iYPZUX/nc5kBGq5fQoguhPffEpJ9nP88Grql1fDi btnBV+afkvPC6lYpHEGaijVwidEH3XfYvC08DTaMbz1W47rGHTiNOACVPqXwLdy/C9Go 4KB8Rt80b1ucOibrbuuqj8LnYunzfkUcGxQ+QeQR8g7RwOL6CbDth3l5ljV0UOTlE2b2 B6fZAecwQbz+XMbo3av6IJHsnGvk/kekJ85lBtC/2+qrKaX6KbzNeNa9JuHMoA9i/5D4 OE9Q== X-Gm-Message-State: AHYfb5gKdmdHJy8w7rjQRUbxTR7OTmKmIvH4dfHJUWeE/bJHFlEIyLlO GKLdl7EEKpkkN0A3 X-Received: by 10.28.61.4 with SMTP id k4mr1697194wma.148.1502993047872; Thu, 17 Aug 2017 11:04:07 -0700 (PDT) Received: from zen.linaro.local ([81.128.185.34]) by smtp.gmail.com with ESMTPSA id f9sm3909910wmf.18.2017.08.17.11.04.04 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 17 Aug 2017 11:04:05 -0700 (PDT) Received: from zen.linaroharston (localhost [127.0.0.1]) by zen.linaro.local (Postfix) with ESMTP id B377E3E11D6; Thu, 17 Aug 2017 19:04:04 +0100 (BST) From: =?UTF-8?q?Alex=20Benn=C3=A9e?= To: rth@twiddle.net, cota@braap.org, batuzovk@ispras.ru Cc: qemu-devel@nongnu.org, qemu-arm@nongnu.org, =?UTF-8?q?Alex=20Benn=C3=A9e?= Date: Thu, 17 Aug 2017 19:03:58 +0100 Message-Id: <20170817180404.29334-4-alex.bennee@linaro.org> X-Mailer: git-send-email 2.13.0 In-Reply-To: <20170817180404.29334-1-alex.bennee@linaro.org> References: <20170817180404.29334-1-alex.bennee@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:400c:c0c::229 Subject: [Qemu-arm] [RFC PATCH 3/9] tcg: generate ptrs to vector registers X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 17 Aug 2017 18:04:15 -0000 As we operate directly on the vectors in memory we pass around the address for TCG_TYPE_VECTOR. Currently only helpers ever see these values but if we were to generate simd backend instructions they would load directly from the backing store. We also need to ensure when copying from one temp register to the other the right size is used. Signed-off-by: Alex Bennée --- tcg/tcg.c | 26 ++++++++++++++++++++++++-- 1 file changed, 24 insertions(+), 2 deletions(-) diff --git a/tcg/tcg.c b/tcg/tcg.c index 35598296c5..e16811d68d 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -2034,7 +2034,21 @@ static void temp_load(TCGContext *s, TCGTemp *ts, TCGRegSet desired_regs, break; case TEMP_VAL_MEM: reg = tcg_reg_alloc(s, desired_regs, allocated_regs, ts->indirect_base); - tcg_out_ld(s, ts->type, reg, ts->mem_base->reg, ts->mem_offset); + if (ts->type == TCG_TYPE_VECTOR) { + /* Vector registers are ptr's to the memory representation */ + TCGArg args[TCG_MAX_OP_ARGS]; + int const_args[TCG_MAX_OP_ARGS]; + args[0] = reg; + args[1] = ts->mem_base->reg; + args[2] = ts->mem_offset; + const_args[0] = 0; + const_args[1] = 0; + const_args[2] = 1; + /* FIXME: needs to by host_ptr centric */ + tcg_out_op(s, INDEX_op_add_i64, args, const_args); + } else { + tcg_out_ld(s, ts->type, reg, ts->mem_base->reg, ts->mem_offset); + } ts->mem_coherent = 1; break; case TEMP_VAL_DEAD: @@ -2196,6 +2210,10 @@ static void tcg_reg_alloc_mov(TCGContext *s, const TCGOpDef *def, ots->reg = tcg_reg_alloc(s, tcg_target_available_regs[otype], allocated_regs, ots->indirect_base); } + /* For the purposes of moving stuff about it is a host ptr */ + if (otype == TCG_TYPE_VECTOR) { + otype = TCG_TYPE_PTR; + } tcg_out_mov(s, otype, ots->reg, ts->reg); } ots->val_type = TEMP_VAL_REG; @@ -2440,7 +2458,11 @@ static void tcg_reg_alloc_call(TCGContext *s, int nb_oargs, int nb_iargs, if (ts->val_type == TEMP_VAL_REG) { if (ts->reg != reg) { - tcg_out_mov(s, ts->type, reg, ts->reg); + if (ts->type == TCG_TYPE_VECTOR) { + tcg_out_mov(s, TCG_TYPE_PTR, reg, ts->reg); + } else { + tcg_out_mov(s, ts->type, reg, ts->reg); + } } } else { TCGRegSet arg_set; -- 2.13.0 From MAILER-DAEMON Thu Aug 17 14:04:17 2017 Received: from list by lists.gnu.org with archive (Exim 4.71) id 1diP9V-00046o-J9 for mharc-qemu-arm@gnu.org; Thu, 17 Aug 2017 14:04:17 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:37434) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1diP9R-000432-W6 for qemu-arm@nongnu.org; Thu, 17 Aug 2017 14:04:15 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1diP9M-0005GC-Vu for qemu-arm@nongnu.org; Thu, 17 Aug 2017 14:04:13 -0400 Received: from mail-wr0-x232.google.com ([2a00:1450:400c:c0c::232]:33978) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1diP9M-0005Ej-Lx for qemu-arm@nongnu.org; Thu, 17 Aug 2017 14:04:08 -0400 Received: by mail-wr0-x232.google.com with SMTP id y96so47727504wrc.1 for ; Thu, 17 Aug 2017 11:04:07 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=4P+jkXBCTgown7vPVjkUDLnPmsOhagansEsA6VBqcu4=; b=iyK6CZm89UoMqFzvoDiC8WPN2kKDwXnuJtVw1A1P+exc7A7cdqg4cQ2lVYs6PhfVHi BxPpu/4kWY8JYGntC35ZSw1cYqZXA1SBI140/tzLGEQOrahssAUzYf4oxlpkVErifNpP Xwhw+nFu9PJpV64tVYwE/Ld7c4ZQ3mBbDnqow= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=4P+jkXBCTgown7vPVjkUDLnPmsOhagansEsA6VBqcu4=; b=R85OopLO2pRfDAZkIHe1qHGsxwFa963UeXntSuQlTL6qAOTnC91NjqpfdaC5waay5U ktSiTrhwH6ofn9tNVg+io2+Y+2rP8m3tJ/jjxn827MLuE1/pctKbr+UgIN5wdKh7fnQ9 kZ6r+BEwjSk7VZvVakr0yURgyrJJVhRsYZBXaG8wm3Xr5oXlw7ByhwR/UFU3tnb3Ptkc mr5otH52JASxdKlqTvE8xoWt5+JsiNyOFfljApK++TWprhcxKAezzmvpQftcZ5BjwR9c wIWHRSEM2huLj91QKOKXqKkj73++HZPPlpQkhfPkvkVJU/aTijwRl5mJpuIEaEhgpO8i /rzA== X-Gm-Message-State: AHYfb5h+5UoHm3UZYaqAUMADdsd3TnXexjE0xxufreX36ao2TYJ0r2TR HAo/99HXlpTGDs97 X-Received: by 10.223.138.237 with SMTP id z42mr4131082wrz.195.1502993045848; Thu, 17 Aug 2017 11:04:05 -0700 (PDT) Received: from zen.linaro.local ([81.128.185.34]) by smtp.gmail.com with ESMTPSA id j18sm3462879wrd.90.2017.08.17.11.04.04 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 17 Aug 2017 11:04:04 -0700 (PDT) Received: from zen.linaroharston (localhost [127.0.0.1]) by zen.linaro.local (Postfix) with ESMTP id 7FD093E00A0; Thu, 17 Aug 2017 19:04:04 +0100 (BST) From: =?UTF-8?q?Alex=20Benn=C3=A9e?= To: rth@twiddle.net, cota@braap.org, batuzovk@ispras.ru Cc: qemu-devel@nongnu.org, qemu-arm@nongnu.org, =?UTF-8?q?Alex=20Benn=C3=A9e?= Date: Thu, 17 Aug 2017 19:03:55 +0100 Message-Id: <20170817180404.29334-1-alex.bennee@linaro.org> X-Mailer: git-send-email 2.13.0 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:400c:c0c::232 Subject: [Qemu-arm] [RFC PATCH 0/9] TCG Vector types and example conversion X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 17 Aug 2017 18:04:15 -0000 Hi, With upcoming work on SVE I've been looking at the way we implement vector registers in QEMU's TCG. The current orthodoxy is to decompose the vector into a series of TCG registers, often calling a helper function the calculation of each element. The result of the helper is then is then stored back in the vector representation afterwards. There are occasional outliers like simd_tbl which access elements directly from a passed CPUFooState env pointer but these are rare. This series introduces the concept of TCGv_vec type. This is a pointer to the start of the in memory representation of an arbitrarily long vector register. This is passed to a helper function as a pointer along with a normal TCG register containing information about the actual vector length and any additional information the helper needs to do the operation. The hope* is this saves on the churn of having the TCG do things element by element and allows the compiler to use native vector operations to streamline the helpers. There are some downsides to this approach. The first is you have to be careful about register aliasing. If you are doing a same reg to same reg operation you need to make a copy of the vector so you don't trample your input data as you go. The second is this involves changing some of the assumptions the TCG makes about things. I've managed to keep all the changes within the core TCG code for now but so far it has only been tested for the tcg_call path which is the only place where TCGv_vec's should turn up. It is possible to do the same thing without touching the TCG code generation by using TCGv_ptrs and manually emitting tcg_addi ops to pass the correct address. Richard has been exploring this approach with his series. The downside of that is you do miss the ability to have named global vector registers which makes reading the TCG dumps a little easier. I've only patched one helper in this series which implements the indexed smull. This is because it appears in the profiles for my test case which was using an arm64 ffmpeg to transcode: ./ffmpeg.arm64 -i big_buck_bunny_480p_surround-fix.avi \ -threads 1 -qscale:v 3 -f null - * hope. On an earlier revision (which included sqshrn conversions) I had measured a minor saving but this had disappeared once I measured the final code. However the profile is fairly dominated by softfloat. master: 8.05% qemu-aarch64 qemu-aarch64 [.] roundAndPackFloat32 7.28% qemu-aarch64 qemu-aarch64 [.] float32_mul 6.56% qemu-aarch64 qemu-aarch64 [.] helper_lookup_tb_ptr 5.31% qemu-aarch64 qemu-aarch64 [.] float32_muladd 4.09% qemu-aarch64 qemu-aarch64 [.] helper_neon_mull_s16 4.00% qemu-aarch64 qemu-aarch64 [.] addFloat32Sigs 3.86% qemu-aarch64 qemu-aarch64 [.] subFloat32Sigs 2.26% qemu-aarch64 qemu-aarch64 [.] helper_simd_tbl 2.00% qemu-aarch64 qemu-aarch64 [.] float32_add 1.81% qemu-aarch64 qemu-aarch64 [.] helper_neon_unarrow_sat8 1.64% qemu-aarch64 qemu-aarch64 [.] float32_sub 1.43% qemu-aarch64 qemu-aarch64 [.] helper_neon_subl_u32 0.98% qemu-aarch64 qemu-aarch64 [.] helper_neon_widen_u8 tcg-native-vectors-rfc: 7.93% qemu-aarch64 qemu-aarch64 [.] roundAndPackFloat32 7.54% qemu-aarch64 qemu-aarch64 [.] float32_mul 6.29% qemu-aarch64 qemu-aarch64 [.] helper_lookup_tb_ptr 5.39% qemu-aarch64 qemu-aarch64 [.] float32_muladd 3.92% qemu-aarch64 qemu-aarch64 [.] addFloat32Sigs 3.86% qemu-aarch64 qemu-aarch64 [.] subFloat32Sigs 3.62% qemu-aarch64 qemu-aarch64 [.] helper_advsimd_smull_idx_s32 2.19% qemu-aarch64 qemu-aarch64 [.] helper_simd_tbl 2.09% qemu-aarch64 qemu-aarch64 [.] helper_neon_mull_s16 1.99% qemu-aarch64 qemu-aarch64 [.] float32_add 1.79% qemu-aarch64 qemu-aarch64 [.] helper_neon_unarrow_sat8 1.62% qemu-aarch64 qemu-aarch64 [.] float32_sub 1.43% qemu-aarch64 qemu-aarch64 [.] helper_neon_subl_u32 1.00% qemu-aarch64 qemu-aarch64 [.] helper_neon_widen_u8 0.98% qemu-aarch64 qemu-aarch64 [.] helper_neon_addl_u32 At the moment the default compiler settings don't actually vectorise the helper. I could get it to once I added some alignment guarantees but the casting I did broke the instruction emulation so I haven't included that patch in this series. Given the results why continue investigating this? Well for one thing vector sizes are growing, SVE vectors are up to 2048 bits long. Those longer vectors should offer more scope for the host compiler to generate efficient code in the helper. Also vector operations tend to be quite complex operations, being able to handle this in C code instead of TCGOps might be more preferable from a code maintainability point of view. Finally this noddy little experiment has at least shown it doesn't worsen performance. It would be nice if I could find a benchmark that made heavy use if non-floating point SIMD instructions to better measure the effect of marshalling elements vs vectorised helpers. If anyone has any suggestions I'm all ears ;-) Anyway questions, comments? Alex Bennée (9): tcg/README: listify the TCG types. tcg: introduce the concepts of a TCGv_vec register type tcg: generate ptrs to vector registers helper-head: add support for vec type arm/cpu.h: align VFP registers target/arm/translate-a64: regnames -> x_regnames target/arm/translate-a64: register global vectors target/arm/helpers: introduce ADVSIMD flags target/arm/translate-a64: vectorise smull vD.4s, vN.[48]s, vM.h[] include/exec/helper-head.h | 5 ++ target/arm/advsimd_helper_flags.h | 50 ++++++++++++++++++++ target/arm/cpu.h | 4 +- target/arm/helper-a64.c | 18 ++++++++ target/arm/helper-a64.h | 2 + target/arm/translate-a64.c | 97 +++++++++++++++++++++++++++++++++++++-- tcg/README | 10 ++-- tcg/tcg.c | 26 ++++++++++- tcg/tcg.h | 20 ++++++++ 9 files changed, 222 insertions(+), 10 deletions(-) create mode 100644 target/arm/advsimd_helper_flags.h -- 2.13.0 From MAILER-DAEMON Thu Aug 17 14:04:18 2017 Received: from list by lists.gnu.org with archive (Exim 4.71) id 1diP9W-00047Y-1l for mharc-qemu-arm@gnu.org; Thu, 17 Aug 2017 14:04:18 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:37499) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1diP9T-00043r-DF for qemu-arm@nongnu.org; Thu, 17 Aug 2017 14:04:16 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1diP9S-0005L3-5X for qemu-arm@nongnu.org; Thu, 17 Aug 2017 14:04:15 -0400 Received: from mail-wr0-x230.google.com ([2a00:1450:400c:c0c::230]:37148) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1diP9R-0005Jf-Ut for qemu-arm@nongnu.org; Thu, 17 Aug 2017 14:04:14 -0400 Received: by mail-wr0-x230.google.com with SMTP id z91so41840516wrc.4 for ; Thu, 17 Aug 2017 11:04:13 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=GgVZo7p5mIkOZRxHVwEM7z1GJnFzidDYAWt+rKTnK7Y=; b=V/mCCcbor+EvYHDTAQcaVmqe/Kjmgr/zJjQbYiJqR7X9HHUCZWbFaIaY830t5X7J5Y HOVDSwEOB/nP6kBX5uq+j1Ab2+bgLC7T6FcbGAjtiy5ofOThoW8T/I2On34DH9xXY6lt VsZ/8cMPHn+uPoQpekVQ2xIbNJihlucsUjFu4= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=GgVZo7p5mIkOZRxHVwEM7z1GJnFzidDYAWt+rKTnK7Y=; b=kkBaffn9Gy8m9usZU2lgJbbIbOdh9ASNoVr0KFP8mrVKEaJ1QNB1B9/adwhQChRZDe dVGYzlERYfMIItbg2+Ay5Y/KBFJLeRrgH1yhWx46b/T5BroOWLn/3/EyK/rK2J8l8NqR pyX/XRcqwVrWoryIHur88cIninkD/MSj7nYrvpRf+2+L1gURQsbZ3gOqWucD7g8irsrM RiglvKTH3foYcJ7KQNwS02PVYoQJzZhytaDDPf7JrQxPJDBQadpuZX9FrrY8kRXI7hCP 0caNkhjSTTUKEypHM6PMXdq+NOnjWJPN06V0Y0z0Z5fSwNz68wLd7nY0BU5l9uW9bDIo QsOw== X-Gm-Message-State: AHYfb5gxcoh4oLMktUg7J3biEq0+Kka6MerU/2OunLh/K2jEbY6OvB1I JKFwVTitI4Erde6M X-Received: by 10.28.72.133 with SMTP id v127mr1923040wma.36.1502993052833; Thu, 17 Aug 2017 11:04:12 -0700 (PDT) Received: from zen.linaro.local ([81.128.185.34]) by smtp.gmail.com with ESMTPSA id f80sm3066124wmh.16.2017.08.17.11.04.06 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 17 Aug 2017 11:04:10 -0700 (PDT) Received: from zen.linaroharston (localhost [127.0.0.1]) by zen.linaro.local (Postfix) with ESMTP id D5C7D3E12CF; Thu, 17 Aug 2017 19:04:04 +0100 (BST) From: =?UTF-8?q?Alex=20Benn=C3=A9e?= To: rth@twiddle.net, cota@braap.org, batuzovk@ispras.ru Cc: qemu-devel@nongnu.org, qemu-arm@nongnu.org, =?UTF-8?q?Alex=20Benn=C3=A9e?= , Peter Maydell Date: Thu, 17 Aug 2017 19:04:00 +0100 Message-Id: <20170817180404.29334-6-alex.bennee@linaro.org> X-Mailer: git-send-email 2.13.0 In-Reply-To: <20170817180404.29334-1-alex.bennee@linaro.org> References: <20170817180404.29334-1-alex.bennee@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:400c:c0c::230 Subject: [Qemu-arm] [RFC PATCH 5/9] arm/cpu.h: align VFP registers X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 17 Aug 2017 18:04:16 -0000 Signed-off-by: Alex Bennée --- target/arm/cpu.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index b39d64aa0b..cdd47cb868 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -457,8 +457,8 @@ typedef struct CPUARMState { * the two execution states, and means we do not need to explicitly * map these registers when changing states. */ - float64 regs[64]; - + float64 regs[64] __attribute__((aligned(16))); + /* VFP system registers */ uint32_t xregs[16]; /* We store these fpcsr fields separately for convenience. */ int vec_len; -- 2.13.0 From MAILER-DAEMON Thu Aug 17 14:04:18 2017 Received: from list by lists.gnu.org with archive (Exim 4.71) id 1diP9W-00047t-5s for mharc-qemu-arm@gnu.org; Thu, 17 Aug 2017 14:04:18 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:37439) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1diP9S-000436-0k for qemu-arm@nongnu.org; Thu, 17 Aug 2017 14:04:16 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1diP9P-0005IW-LE for qemu-arm@nongnu.org; Thu, 17 Aug 2017 14:04:13 -0400 Received: from mail-wr0-x22f.google.com ([2a00:1450:400c:c0c::22f]:34002) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1diP9P-0005I0-Et for qemu-arm@nongnu.org; Thu, 17 Aug 2017 14:04:11 -0400 Received: by mail-wr0-x22f.google.com with SMTP id y96so47729232wrc.1 for ; Thu, 17 Aug 2017 11:04:11 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=w838pJBKi9FO1w7BOjy9IbZ2bNjPtkChS6A9ODn8p/8=; b=QXmhNw6jrcADGhmvsIoAsSfoUtwltZtl0ObAepkptCNOg0pf0M+d27w7ubjqO8CKVE lGlVsMVLK0RGIxMV+dw8V7kCAS5acMkjKFYQ7RqT1AZ5fBcqe3Pq6Pf3o8WrZJ1bS1/a XLPqADRC7AwYcSQBYvwgleOrMY4CroqRt6qao= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=w838pJBKi9FO1w7BOjy9IbZ2bNjPtkChS6A9ODn8p/8=; b=V6jEWC9vm4AFnhV1hDGZCfPxiU2O1OrYGjIj+aY8gt3XzP0skBLy//8eH0J1V6sNxH atsE5NVYcQF31vOpCrapxr+gHEmL+PDd96M7FklXJ3SUmrgYwBPYXHwKkW1vkYeizHKU uhcept4qikNa/iuVdB4s1IzkqF2plgwIUxIARLACSzjEWMNa11e1p9K8y2HkIH5MUrXZ zMs2FB2ufMcNRlTV1pAUZdbjOrWZudvE0snLs8kYmA8xQCXDrZqwKryFTB4pabLxCobD dBalshD3axrjd+uymx16227HFmZWBKhItPKVPHroPAehpizMdpcfq7XeeC7ETvejyvLS 7ogQ== X-Gm-Message-State: AHYfb5iuPD5wkhjm+wb8kxC3MQBZukgwgixj5SOIQ1zt/i4Iey2Sta9G Nqp1xaRycyIDFAHR X-Received: by 10.223.199.212 with SMTP id y20mr4105289wrg.279.1502993050361; Thu, 17 Aug 2017 11:04:10 -0700 (PDT) Received: from zen.linaro.local ([81.128.185.34]) by smtp.gmail.com with ESMTPSA id l23sm3956278wrb.30.2017.08.17.11.04.05 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 17 Aug 2017 11:04:05 -0700 (PDT) Received: from zen.linaroharston (localhost [127.0.0.1]) by zen.linaro.local (Postfix) with ESMTP id C4CDA3E128A; Thu, 17 Aug 2017 19:04:04 +0100 (BST) From: =?UTF-8?q?Alex=20Benn=C3=A9e?= To: rth@twiddle.net, cota@braap.org, batuzovk@ispras.ru Cc: qemu-devel@nongnu.org, qemu-arm@nongnu.org, =?UTF-8?q?Alex=20Benn=C3=A9e?= , Paolo Bonzini , Peter Crosthwaite Date: Thu, 17 Aug 2017 19:03:59 +0100 Message-Id: <20170817180404.29334-5-alex.bennee@linaro.org> X-Mailer: git-send-email 2.13.0 In-Reply-To: <20170817180404.29334-1-alex.bennee@linaro.org> References: <20170817180404.29334-1-alex.bennee@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:400c:c0c::22f Subject: [Qemu-arm] [RFC PATCH 4/9] helper-head: add support for vec type X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 17 Aug 2017 18:04:16 -0000 --- include/exec/helper-head.h | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/include/exec/helper-head.h b/include/exec/helper-head.h index 1cfc43b9ff..3fb4c3fc39 100644 --- a/include/exec/helper-head.h +++ b/include/exec/helper-head.h @@ -23,6 +23,7 @@ #define GET_TCGV_i32 GET_TCGV_I32 #define GET_TCGV_i64 GET_TCGV_I64 #define GET_TCGV_ptr GET_TCGV_PTR +#define GET_TCGV_vec GET_TCGV_VEC /* Some types that make sense in C, but not for TCG. */ #define dh_alias_i32 i32 @@ -33,6 +34,7 @@ #define dh_alias_f32 i32 #define dh_alias_f64 i64 #define dh_alias_ptr ptr +#define dh_alias_vec vec #define dh_alias_void void #define dh_alias_noreturn noreturn #define dh_alias(t) glue(dh_alias_, t) @@ -45,6 +47,7 @@ #define dh_ctype_f32 float32 #define dh_ctype_f64 float64 #define dh_ctype_ptr void * +#define dh_ctype_vec void * #define dh_ctype_void void #define dh_ctype_noreturn void QEMU_NORETURN #define dh_ctype(t) dh_ctype_##t @@ -90,6 +93,7 @@ #define dh_is_64bit_i32 0 #define dh_is_64bit_i64 1 #define dh_is_64bit_ptr (sizeof(void *) == 8) +#define dh_is_64bit_vec (sizeof(void *) == 8) #define dh_is_64bit(t) glue(dh_is_64bit_, dh_alias(t)) #define dh_is_signed_void 0 @@ -106,6 +110,7 @@ extension instructions that may be required, e.g. ia64's addp4. But for now we don't support any 64-bit targets with 32-bit pointers. */ #define dh_is_signed_ptr 0 +#define dh_is_signed_vec dh_is_signed_ptr #define dh_is_signed_env dh_is_signed_ptr #define dh_is_signed(t) dh_is_signed_##t -- 2.13.0 From MAILER-DAEMON Thu Aug 17 14:04:21 2017 Received: from list by lists.gnu.org with archive (Exim 4.71) id 1diP9Z-0004CL-Jm for mharc-qemu-arm@gnu.org; Thu, 17 Aug 2017 14:04:21 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:37442) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1diP9S-000437-0i for qemu-arm@nongnu.org; Thu, 17 Aug 2017 14:04:15 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1diP9O-0005Hj-Lv for qemu-arm@nongnu.org; Thu, 17 Aug 2017 14:04:13 -0400 Received: from mail-wr0-x236.google.com ([2a00:1450:400c:c0c::236]:33111) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1diP9O-0005H5-FU for qemu-arm@nongnu.org; Thu, 17 Aug 2017 14:04:10 -0400 Received: by mail-wr0-x236.google.com with SMTP id b65so50612180wrd.0 for ; Thu, 17 Aug 2017 11:04:10 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=aQ5Q4N/tFeJRd7kL8iE6aNPDDKqWRl+nnZkLwu9w9+o=; b=V6rtEqXGlBKEDKDjIarb21w2nsYq2yefT/2J1YqAlS4BFvtxRh127m+XHnNJzYQ0i9 U4OQrgBGRAEetvvjzWBdLdVlHOakzwxVWTRLUmE7+LQXynV8q068p1xdv1GDfkkngFWT V1gQm2OAwMZ8liOwM/mZp8Xyw6K5+IIAJ4lVc= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=aQ5Q4N/tFeJRd7kL8iE6aNPDDKqWRl+nnZkLwu9w9+o=; b=GD4DsYc1fkVSwVY8oN1hr3YvNMhfcxt2jTzdX2H6fZCqiLRfZ3ph47J119hqDuX42L Ta55DzZp57I7RHFlbFyTqLjXYJEu+UslxWwVBZUyey4A3pKNygzVpx7ouP+nr7yBHrjS yNO313NF/ZCQ4cot++HbIXgUMkRcsh0vkirw5CGB1PZNW+wHZeEK3fOJe2JdtEnO28aU tjtX7C0d4jjD0tBJNn6kJ7VncG5kJ31YC7yd9onJkQDoQos4+PnZPSZdNSeFPFCogzfX VHhBMrFpLZe0MFmyBXMAvjNfydCnPSOSbWiHk2vA+NQMS09NPea9jqnr5c06YYek/da6 dKBQ== X-Gm-Message-State: AHYfb5jIbMz3VT+ywfRskpZD2ErsguaigFuy171Hg62rhJDm4oV4YitI 9guSej098iJkikCx X-Received: by 10.28.141.140 with SMTP id p134mr1655091wmd.84.1502993049094; Thu, 17 Aug 2017 11:04:09 -0700 (PDT) Received: from zen.linaro.local ([81.128.185.34]) by smtp.gmail.com with ESMTPSA id n17sm3690203wra.6.2017.08.17.11.04.04 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 17 Aug 2017 11:04:05 -0700 (PDT) Received: from zen.linaroharston (localhost [127.0.0.1]) by zen.linaro.local (Postfix) with ESMTP id A2A443E08D5; Thu, 17 Aug 2017 19:04:04 +0100 (BST) From: =?UTF-8?q?Alex=20Benn=C3=A9e?= To: rth@twiddle.net, cota@braap.org, batuzovk@ispras.ru Cc: qemu-devel@nongnu.org, qemu-arm@nongnu.org, =?UTF-8?q?Alex=20Benn=C3=A9e?= Date: Thu, 17 Aug 2017 19:03:57 +0100 Message-Id: <20170817180404.29334-3-alex.bennee@linaro.org> X-Mailer: git-send-email 2.13.0 In-Reply-To: <20170817180404.29334-1-alex.bennee@linaro.org> References: <20170817180404.29334-1-alex.bennee@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:400c:c0c::236 Subject: [Qemu-arm] [RFC PATCH 2/9] tcg: introduce the concepts of a TCGv_vec register type X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 17 Aug 2017 18:04:15 -0000 Currently it only makes sense for globals - i.e. registers directly mapped to CPUEnv. --- tcg/README | 1 + tcg/tcg.h | 20 ++++++++++++++++++++ 2 files changed, 21 insertions(+) diff --git a/tcg/README b/tcg/README index f116b7b694..e0868d95b4 100644 --- a/tcg/README +++ b/tcg/README @@ -57,6 +57,7 @@ typed. A number of types are supported: TCGv_i32 - 32 bit integer TCGv_i64 - 64 bit integer + TCGv_vec - an arbitrary sized vector register TCGv - target pointer (aliased to 32 or 64 bit integer) TCGv_ptr - host pointer (used for direct access to host structures) diff --git a/tcg/tcg.h b/tcg/tcg.h index 17b7750ee6..d75636b6ab 100644 --- a/tcg/tcg.h +++ b/tcg/tcg.h @@ -256,6 +256,7 @@ typedef struct TCGPool { typedef enum TCGType { TCG_TYPE_I32, TCG_TYPE_I64, + TCG_TYPE_VECTOR, TCG_TYPE_COUNT, /* number of different types */ /* An alias for the size of the host register. */ @@ -431,6 +432,7 @@ typedef tcg_target_ulong TCGArg; typedef struct TCGv_i32_d *TCGv_i32; typedef struct TCGv_i64_d *TCGv_i64; typedef struct TCGv_ptr_d *TCGv_ptr; +typedef struct TCGv_vec_d *TCGv_vec; typedef TCGv_ptr TCGv_env; #if TARGET_LONG_BITS == 32 #define TCGv TCGv_i32 @@ -450,6 +452,11 @@ static inline TCGv_i64 QEMU_ARTIFICIAL MAKE_TCGV_I64(intptr_t i) return (TCGv_i64)i; } +static inline TCGv_vec QEMU_ARTIFICIAL MAKE_TCGV_VEC(intptr_t i) +{ + return (TCGv_vec)i; +} + static inline TCGv_ptr QEMU_ARTIFICIAL MAKE_TCGV_PTR(intptr_t i) { return (TCGv_ptr)i; @@ -465,6 +472,11 @@ static inline intptr_t QEMU_ARTIFICIAL GET_TCGV_I64(TCGv_i64 t) return (intptr_t)t; } +static inline intptr_t QEMU_ARTIFICIAL GET_TCGV_VEC(TCGv_vec t) +{ + return (intptr_t)t; +} + static inline intptr_t QEMU_ARTIFICIAL GET_TCGV_PTR(TCGv_ptr t) { return (intptr_t)t; @@ -788,6 +800,7 @@ int tcg_global_mem_new_internal(TCGType, TCGv_ptr, intptr_t, const char *); TCGv_i32 tcg_global_reg_new_i32(TCGReg reg, const char *name); TCGv_i64 tcg_global_reg_new_i64(TCGReg reg, const char *name); +TCGv_vec tcg_global_reg_new_vec(TCGReg reg, const char *name); TCGv_i32 tcg_temp_new_internal_i32(int temp_local); TCGv_i64 tcg_temp_new_internal_i64(int temp_local); @@ -829,6 +842,13 @@ static inline TCGv_i64 tcg_temp_local_new_i64(void) return tcg_temp_new_internal_i64(1); } +static inline TCGv_vec tcg_global_mem_new_vec(TCGv_ptr reg, intptr_t offset, + const char *name) +{ + int idx = tcg_global_mem_new_internal(TCG_TYPE_VECTOR, reg, offset, name); + return MAKE_TCGV_VEC(idx); +} + #if defined(CONFIG_DEBUG_TCG) /* If you call tcg_clear_temp_count() at the start of a section of * code which is not supposed to leak any TCG temporaries, then -- 2.13.0 From MAILER-DAEMON Thu Aug 17 14:04:23 2017 Received: from list by lists.gnu.org with archive (Exim 4.71) id 1diP9b-0004FL-5z for mharc-qemu-arm@gnu.org; Thu, 17 Aug 2017 14:04:23 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:37430) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1diP9R-00042y-VL for qemu-arm@nongnu.org; Thu, 17 Aug 2017 14:04:18 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1diP9N-0005Gm-HY for qemu-arm@nongnu.org; Thu, 17 Aug 2017 14:04:13 -0400 Received: from mail-wr0-x22c.google.com ([2a00:1450:400c:c0c::22c]:36390) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1diP9N-0005FA-B6 for qemu-arm@nongnu.org; Thu, 17 Aug 2017 14:04:09 -0400 Received: by mail-wr0-x22c.google.com with SMTP id f8so6192319wrf.3 for ; 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Thu, 17 Aug 2017 11:04:06 -0700 (PDT) Received: from zen.linaro.local ([81.128.185.34]) by smtp.gmail.com with ESMTPSA id h190sm3716635wmd.4.2017.08.17.11.04.04 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 17 Aug 2017 11:04:05 -0700 (PDT) Received: from zen.linaroharston (localhost [127.0.0.1]) by zen.linaro.local (Postfix) with ESMTP id 90E3B3E0190; Thu, 17 Aug 2017 19:04:04 +0100 (BST) From: =?UTF-8?q?Alex=20Benn=C3=A9e?= To: rth@twiddle.net, cota@braap.org, batuzovk@ispras.ru Cc: qemu-devel@nongnu.org, qemu-arm@nongnu.org, =?UTF-8?q?Alex=20Benn=C3=A9e?= Date: Thu, 17 Aug 2017 19:03:56 +0100 Message-Id: <20170817180404.29334-2-alex.bennee@linaro.org> X-Mailer: git-send-email 2.13.0 In-Reply-To: <20170817180404.29334-1-alex.bennee@linaro.org> References: <20170817180404.29334-1-alex.bennee@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:400c:c0c::22c Subject: [Qemu-arm] [RFC PATCH 1/9] tcg/README: listify the TCG types. X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 17 Aug 2017 18:04:18 -0000 Although the other types are aliases lets make it clear what TCG types are available. Signed-off-by: Alex Bennée --- tcg/README | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/tcg/README b/tcg/README index 03bfb6acd4..f116b7b694 100644 --- a/tcg/README +++ b/tcg/README @@ -53,9 +53,12 @@ an "undefined result". TCG instructions operate on variables which are temporaries, local temporaries or globals. TCG instructions and variables are strongly -typed. Two types are supported: 32 bit integers and 64 bit -integers. Pointers are defined as an alias to 32 bit or 64 bit -integers depending on the TCG target word size. +typed. A number of types are supported: + + TCGv_i32 - 32 bit integer + TCGv_i64 - 64 bit integer + TCGv - target pointer (aliased to 32 or 64 bit integer) + TCGv_ptr - host pointer (used for direct access to host structures) Each instruction has a fixed number of output variable operands, input variable operands and always constant operands. -- 2.13.0 From MAILER-DAEMON Thu Aug 17 14:04:24 2017 Received: from list by lists.gnu.org with archive (Exim 4.71) id 1diP9c-0004Gz-Ff for mharc-qemu-arm@gnu.org; Thu, 17 Aug 2017 14:04:24 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:37579) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1diP9X-00049S-09 for qemu-arm@nongnu.org; Thu, 17 Aug 2017 14:04:23 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1diP9V-0005Ok-T8 for qemu-arm@nongnu.org; Thu, 17 Aug 2017 14:04:18 -0400 Received: from mail-wr0-x22f.google.com ([2a00:1450:400c:c0c::22f]:38359) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1diP9V-0005Nv-Gn for qemu-arm@nongnu.org; Thu, 17 Aug 2017 14:04:17 -0400 Received: by mail-wr0-x22f.google.com with SMTP id 5so25944729wrz.5 for ; Thu, 17 Aug 2017 11:04:17 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=UC4iwuAR4yeyWBSDbELSGaxnBCBHWMws/wQFfSoxQ0g=; b=FRRxoY1V+wZWgrDUDBiQAimwI4n4lFdaoYE0qCsrWD9lf0h5ocOy9utlQVqBMAg2bU AT0VFoIohLYSlqYKiHmrBHo2u00Rrt3dkXW3RHVG/WrM///P0XAlZcHBAQ6l45VIAKbK 3h6CRCNHdoR3CBV8eugaOqAjjvh3D4nDll7MM= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=UC4iwuAR4yeyWBSDbELSGaxnBCBHWMws/wQFfSoxQ0g=; b=nHNdmgLO7HOQogD5hEqDhTs5ix3SOh++XCxac3paJBsmvxx+3nALdz2xm1VxmjFqzW nuz0UCEk92ITs2K/GynCj625gkQDTl19/32Rz/HLZ0LVoNBPbzk7W+k7yLY/spldhfu7 5d8p228+CcGJGt+1Gae/xOZxXewgY34MNTOCz9lIBX5zNUGoQoPj9zgoG8v3VCWtlIPd eomgZwjQyEw5DM2KeuuUC95M2HOr08RZ1z7mHb4mdlrVjbsfT6KNl89f55O+eGiyAeJ3 iyM/x+SvqOY+RmBeG2iOivyB3h6NC+q/MMSLxMe2OE518jCGXR3ICNcKvrAaz4CqnKp+ Ox4g== X-Gm-Message-State: AHYfb5jaUSeuScRplqZ9fnBOmsaI7jWiFZvVKnYMIG6vORJKG6rZ13/Z kXE+0OFNudCBRrDR X-Received: by 10.223.152.19 with SMTP id v19mr4134516wrb.60.1502993056413; Thu, 17 Aug 2017 11:04:16 -0700 (PDT) Received: from zen.linaro.local ([81.128.185.34]) by smtp.gmail.com with ESMTPSA id f9sm3877162wmf.9.2017.08.17.11.04.08 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 17 Aug 2017 11:04:10 -0700 (PDT) Received: from zen.linaroharston (localhost [127.0.0.1]) by zen.linaro.local (Postfix) with ESMTP id 2A0ED3E1403; Thu, 17 Aug 2017 19:04:05 +0100 (BST) From: =?UTF-8?q?Alex=20Benn=C3=A9e?= To: rth@twiddle.net, cota@braap.org, batuzovk@ispras.ru Cc: qemu-devel@nongnu.org, qemu-arm@nongnu.org, =?UTF-8?q?Alex=20Benn=C3=A9e?= , Peter Maydell Date: Thu, 17 Aug 2017 19:04:04 +0100 Message-Id: <20170817180404.29334-10-alex.bennee@linaro.org> X-Mailer: git-send-email 2.13.0 In-Reply-To: <20170817180404.29334-1-alex.bennee@linaro.org> References: <20170817180404.29334-1-alex.bennee@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:400c:c0c::22f Subject: [Qemu-arm] [RFC PATCH 9/9] target/arm/translate-a64: vectorise smull vD.4s, vN.[48]s, vM.h[] X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 17 Aug 2017 18:04:24 -0000 These instructions show up in the ffmpeg profile from the ff_simple_idct_put_neon function. WARNING: this is experimental and essentially shortcuts to the vectorised helper for the one instruction that shows up a lot in the ffmpeg trace. Otherwise it falls through to the normal code generation. We also skip where rd == rn to avoid having to explicitly deal with the aliasing in the helper. Signed-off-by: Alex Bennée --- target/arm/helper-a64.c | 17 +++++++++++ target/arm/helper-a64.h | 2 ++ target/arm/translate-a64.c | 72 ++++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 91 insertions(+) diff --git a/target/arm/helper-a64.c b/target/arm/helper-a64.c index 17b1edfb5f..ae0f8da5c4 100644 --- a/target/arm/helper-a64.c +++ b/target/arm/helper-a64.c @@ -538,3 +538,20 @@ uint64_t HELPER(paired_cmpxchg64_be)(CPUARMState *env, uint64_t addr, return !success; } + +/* Multiply Long (vector, by element) */ +void HELPER(advsimd_smull_idx_s32)(void *d, void *n, uint32_t m, + uint32_t simd_data) +{ + int opr_elt = GET_SIMD_DATA(OPR_ELT, simd_data); + int doff_elt = GET_SIMD_DATA(DOFF_ELT, simd_data); + int32_t *rd = (int32_t *) d; + int16_t *rn = (int16_t *) n; + int16_t rm = (int16_t) m; + int i; + + #pragma GCC ivdep + for (i = 0; i < opr_elt; ++i) { + rd[i] = rn[i + doff_elt] * rm; + } +} diff --git a/target/arm/helper-a64.h b/target/arm/helper-a64.h index 6f9eaba533..0bd7942cec 100644 --- a/target/arm/helper-a64.h +++ b/target/arm/helper-a64.h @@ -44,3 +44,5 @@ DEF_HELPER_FLAGS_3(crc32_64, TCG_CALL_NO_RWG_SE, i64, i64, i64, i32) DEF_HELPER_FLAGS_3(crc32c_64, TCG_CALL_NO_RWG_SE, i64, i64, i64, i32) DEF_HELPER_FLAGS_4(paired_cmpxchg64_le, TCG_CALL_NO_WG, i64, env, i64, i64, i64) DEF_HELPER_FLAGS_4(paired_cmpxchg64_be, TCG_CALL_NO_WG, i64, env, i64, i64, i64) + +DEF_HELPER_4(advsimd_smull_idx_s32, void, vec, vec, i32, i32) diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index f474c5008b..3a609e571c 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -10466,6 +10466,74 @@ static void disas_simd_two_reg_misc(DisasContext *s, uint32_t insn) } } +typedef void AdvSIMDGenTwoPlusOneVectorFn(TCGv_vec, TCGv_vec, TCGv_i32, TCGv_i32); + +/* Handle [U/S]ML[S/A]L instructions + * + * This splits off from bellow only to aid experimentation. + */ +static bool handle_vec_simd_mul_addsub(DisasContext *s, uint32_t insn, int opcode, int size, bool is_q, bool u, int rn, int rm, int rd) +{ + /* fprintf(stderr, "%s: %#04x op:%x sz:%d rn:%d rm:%d rd:%d\n", __func__, */ + /* insn, opcode, size, rn, rm, rd); */ + + if (size == 1) { + AdvSIMDGenTwoPlusOneVectorFn *fn = NULL; + uint32_t simd_info = 0; + + switch (opcode) { + case 0x2: /* SMLAL, SMLAL2, UMLAL, UMLAL2 */ + break; + case 0x6: /* SMLSL, SMLSL2, UMLSL, UMLSL2 */ + break; + case 0xa: /* SMULL, SMULL2, UMULL, UMULL2 */ + if (!u) + { + /* helper assumes no aliasing */ + if (rd == rn) { + return false; + } + + fn = gen_helper_advsimd_smull_idx_s32; + simd_info = deposit32(simd_info, + ADVSIMD_OPR_ELT_SHIFT, ADVSIMD_OPR_ELT_BITS, 4); + + if (is_q) { + simd_info = deposit32(simd_info, + ADVSIMD_DOFF_ELT_SHIFT, ADVSIMD_DOFF_ELT_BITS, 4); + } + }; + break; + default: + break; + } + + /* assert(fn); */ + + if (fn) { + TCGv_i32 tcg_idx = tcg_temp_new_i32(); + TCGv_i32 tcg_simd_info = tcg_const_i32(simd_info); + int h = extract32(insn, 11, 1); + int lm = extract32(insn, 20, 2); + int index = h << 2 | lm; + + if (!fp_access_check(s)) { + return false; + } + + read_vec_element_i32(s, tcg_idx, rm, index, size); + + fn(cpu_V[rd], cpu_V[rn], tcg_idx, tcg_simd_info); + + tcg_temp_free_i32(tcg_simd_info); + tcg_temp_free_i32(tcg_idx); + return true; + } + } + + return false; +} + /* C3.6.13 AdvSIMD scalar x indexed element * 31 30 29 28 24 23 22 21 20 19 16 15 12 11 10 9 5 4 0 * +-----+---+-----------+------+---+---+------+-----+---+---+------+------+ @@ -10518,6 +10586,10 @@ static void disas_simd_indexed(DisasContext *s, uint32_t insn) unallocated_encoding(s); return; } + /* Shortcut if we have a vectorised helper */ + if (handle_vec_simd_mul_addsub(s, insn, opcode, size, is_q, u, rn, rm, rd)) { + return; + } is_long = true; break; case 0x3: /* SQDMLAL, SQDMLAL2 */ -- 2.13.0 From MAILER-DAEMON Thu Aug 17 14:04:25 2017 Received: from list by lists.gnu.org with archive (Exim 4.71) id 1diP9d-0004Hd-1a for mharc-qemu-arm@gnu.org; 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Thu, 17 Aug 2017 19:04:05 +0100 (BST) From: =?UTF-8?q?Alex=20Benn=C3=A9e?= To: rth@twiddle.net, cota@braap.org, batuzovk@ispras.ru Cc: qemu-devel@nongnu.org, qemu-arm@nongnu.org, =?UTF-8?q?Alex=20Benn=C3=A9e?= , Peter Maydell Date: Thu, 17 Aug 2017 19:04:02 +0100 Message-Id: <20170817180404.29334-8-alex.bennee@linaro.org> X-Mailer: git-send-email 2.13.0 In-Reply-To: <20170817180404.29334-1-alex.bennee@linaro.org> References: <20170817180404.29334-1-alex.bennee@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:400c:c0c::22b Subject: [Qemu-arm] [RFC PATCH 7/9] target/arm/translate-a64: register global vectors X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 17 Aug 2017 18:04:18 -0000 Register the vector registers with TCG. Signed-off-by: Alex Bennée --- target/arm/translate-a64.c | 21 +++++++++++++++++++-- 1 file changed, 19 insertions(+), 2 deletions(-) diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 805af51900..b5f48605a7 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -36,8 +36,10 @@ #include "trace-tcg.h" +/* Global registers */ static TCGv_i64 cpu_X[32]; static TCGv_i64 cpu_pc; +static TCGv_vec cpu_V[32]; /* Load/store exclusive handling */ static TCGv_i64 cpu_exclusive_high; @@ -50,6 +52,13 @@ static const char *x_regnames[] = { "x24", "x25", "x26", "x27", "x28", "x29", "lr", "sp" }; +static const char *v_regnames[] = { + "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", + "v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15", + "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", + "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31" +}; + enum a64_shift_type { A64_SHIFT_TYPE_LSL = 0, A64_SHIFT_TYPE_LSR = 1, @@ -91,10 +100,18 @@ void a64_translate_init(void) cpu_pc = tcg_global_mem_new_i64(cpu_env, offsetof(CPUARMState, pc), "pc"); - for (i = 0; i < 32; i++) { + + for (i = 0; i < ARRAY_SIZE(cpu_X); i++) { cpu_X[i] = tcg_global_mem_new_i64(cpu_env, offsetof(CPUARMState, xregs[i]), - regnames[i]); + x_regnames[i]); + } + + for (i = 0; i < ARRAY_SIZE(cpu_V); i++) { + cpu_V[i] = tcg_global_mem_new_vec(cpu_env, + offsetof(CPUARMState, + vfp.regs[i * 2]), + v_regnames[i]); } cpu_exclusive_high = tcg_global_mem_new_i64(cpu_env, -- 2.13.0 From MAILER-DAEMON Thu Aug 17 14:04:27 2017 Received: from list by lists.gnu.org with archive (Exim 4.71) id 1diP9f-0004Ii-Af for mharc-qemu-arm@gnu.org; Thu, 17 Aug 2017 14:04:27 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:37596) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1diP9Y-0004An-2z for qemu-arm@nongnu.org; Thu, 17 Aug 2017 14:04:23 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1diP9R-0005Jl-C1 for qemu-arm@nongnu.org; Thu, 17 Aug 2017 14:04:20 -0400 Received: from mail-wr0-x234.google.com ([2a00:1450:400c:c0c::234]:38335) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1diP9R-0005J8-6P for qemu-arm@nongnu.org; Thu, 17 Aug 2017 14:04:13 -0400 Received: by mail-wr0-x234.google.com with SMTP id 5so25943039wrz.5 for ; Thu, 17 Aug 2017 11:04:13 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=ieNsD6GEr3OWd7Ih++yjO7tL6HCDLmZ0Skj6lrfUXPw=; b=kdrXeD2WrZ+Jn95vSs7jaewrO3cd02UwYpETFJ2Mz3YglwTT4sCTAa6hb+fpjojt3R ZpAX2LjglYrZKZ22V8b9t8Y11eIannqgqXMj0lYOxwQOOoX6GhO++TCDFw/UBLDl6Fqh FJ5RMW6mSept+W1/UHBUE7y4idpQAeMzy50Sg= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=ieNsD6GEr3OWd7Ih++yjO7tL6HCDLmZ0Skj6lrfUXPw=; b=e6pkyoBu8otqisFPKi3BtBvM9Qw/cMvzX5NPaxVjqQZ6dtt0NaECiqIjL/bjHKTeSR HZWwdkjx4hw8dl0bqNqq62ZlrZvzGPvD+j4A+7Y115vld/gatq3tOePk7qRogP+bVOKF 6m5MVBEoBBQCj27OaiqwzNfA030jySvpXfHuHG82kEOguufQJwyww49gKj2/kqDs1FjR wsQaViTkq+NP/1EPIZ6QrTWSHZl0KSTVCDyQ049ZIxaLNpAUKRjwIfY/fnixxcMrJGL+ d508w298mfJb9XETut50/nGL0Vkmh+B2H0E6DskXYrtTvmpxfChV70jm2MniC+MOZIaB hH9Q== X-Gm-Message-State: AHYfb5ixYnUzSeldPRW47SAxMLhp8AfqXAa297gXeP33garNs4f4msfu UcQdLM99Djc+ETD3 X-Received: by 10.223.170.2 with SMTP id p2mr4296928wrd.22.1502993052079; Thu, 17 Aug 2017 11:04:12 -0700 (PDT) Received: from zen.linaro.local ([81.128.185.34]) by smtp.gmail.com with ESMTPSA id z9sm5090096wrz.0.2017.08.17.11.04.06 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 17 Aug 2017 11:04:10 -0700 (PDT) Received: from zen.linaroharston (localhost [127.0.0.1]) by zen.linaro.local (Postfix) with ESMTP id E70AD3E1337; Thu, 17 Aug 2017 19:04:04 +0100 (BST) From: =?UTF-8?q?Alex=20Benn=C3=A9e?= To: rth@twiddle.net, cota@braap.org, batuzovk@ispras.ru Cc: qemu-devel@nongnu.org, qemu-arm@nongnu.org, =?UTF-8?q?Alex=20Benn=C3=A9e?= , Peter Maydell Date: Thu, 17 Aug 2017 19:04:01 +0100 Message-Id: <20170817180404.29334-7-alex.bennee@linaro.org> X-Mailer: git-send-email 2.13.0 In-Reply-To: <20170817180404.29334-1-alex.bennee@linaro.org> References: <20170817180404.29334-1-alex.bennee@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:400c:c0c::234 Subject: [Qemu-arm] [RFC PATCH 6/9] target/arm/translate-a64: regnames -> x_regnames X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 17 Aug 2017 18:04:24 -0000 These are the integer registers as will become clear when we start declaring the vector ones. Signed-off-by: Alex Bennée --- target/arm/translate-a64.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 2200e25be0..805af51900 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -43,7 +43,7 @@ static TCGv_i64 cpu_pc; static TCGv_i64 cpu_exclusive_high; static TCGv_i64 cpu_reg(DisasContext *s, int reg); -static const char *regnames[] = { +static const char *x_regnames[] = { "x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7", "x8", "x9", "x10", "x11", "x12", "x13", "x14", "x15", "x16", "x17", "x18", "x19", "x20", "x21", "x22", "x23", -- 2.13.0 From MAILER-DAEMON Thu Aug 17 14:04:29 2017 Received: from list by lists.gnu.org with archive (Exim 4.71) id 1diP9h-0004LJ-7a for mharc-qemu-arm@gnu.org; Thu, 17 Aug 2017 14:04:29 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:37581) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1diP9X-00049t-BQ for qemu-arm@nongnu.org; Thu, 17 Aug 2017 14:04:23 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1diP9T-0005MU-88 for qemu-arm@nongnu.org; Thu, 17 Aug 2017 14:04:19 -0400 Received: from mail-wr0-x22e.google.com ([2a00:1450:400c:c0c::22e]:34022) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1diP9T-0005Li-1L for qemu-arm@nongnu.org; Thu, 17 Aug 2017 14:04:15 -0400 Received: by mail-wr0-x22e.google.com with SMTP id y96so47730566wrc.1 for ; Thu, 17 Aug 2017 11:04:14 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=1OZ/Z1R6iCyFdgPfKV/7hVu1PAMlL7gRWtPozZg3jDk=; b=feTPYjQRxGv8XofMiuQEUBzH/3p0ANcoETRYVVTtYjpAMygYse25ImpXaWJG3m4JJG qwB1rSZBOJQJmZPvOBNaiXln2NfU8xYGvLJ+83KwHW9lcJBD7SjxywVuNUEQw3VkMu+J 48kzZs44N4SS9dKk/rsHlvKXYpHCljhmmd6hk= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=1OZ/Z1R6iCyFdgPfKV/7hVu1PAMlL7gRWtPozZg3jDk=; b=ChUF+JXw0wgZHRRKpXuFBVb36hiBXuVwdAGfIg5kUVXM+4beqzdBDKoxzuLJkhmhhH dECv+NcjAwBP37aDb4dCulPcjL+aXDJe6/+4NaC2GzlwpUj9wqgrTvvhENP2vW7hJJj+ EFGen/k54dTRKrRyAfrqDL/AlUIO+5je5tMmcWWBZv78fcboxBbdZ/EVSUfEeDU+cEaS zNvQjqy5mlLQFKnHdChcYlyp5MLg/usu4GdJQQyr4z9iOehs22Xmr7KiU3ijA8MHwAl0 e5/9xF19KOHIFCx3gAQhdUNv7lOelzpE+V7p+mvRJ117Gi3YWpOoK9HvtUVVVeiaAre9 JWlQ== X-Gm-Message-State: AHYfb5jOwuEyJgXuCZVRnszK11DPy4ncrB/Zc+VjJvwVtN6GK538Jld4 1ol1WXvcc4AxULzB X-Received: by 10.28.174.209 with SMTP id x200mr1698448wme.106.1502993053921; Thu, 17 Aug 2017 11:04:13 -0700 (PDT) Received: from zen.linaro.local ([81.128.185.34]) by smtp.gmail.com with ESMTPSA id m16sm2376115wrg.11.2017.08.17.11.04.07 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 17 Aug 2017 11:04:10 -0700 (PDT) Received: from zen.linaroharston (localhost [127.0.0.1]) by zen.linaro.local (Postfix) with ESMTP id 167703E13AA; Thu, 17 Aug 2017 19:04:05 +0100 (BST) From: =?UTF-8?q?Alex=20Benn=C3=A9e?= To: rth@twiddle.net, cota@braap.org, batuzovk@ispras.ru Cc: qemu-devel@nongnu.org, qemu-arm@nongnu.org, =?UTF-8?q?Alex=20Benn=C3=A9e?= , Peter Maydell Date: Thu, 17 Aug 2017 19:04:03 +0100 Message-Id: <20170817180404.29334-9-alex.bennee@linaro.org> X-Mailer: git-send-email 2.13.0 In-Reply-To: <20170817180404.29334-1-alex.bennee@linaro.org> References: <20170817180404.29334-1-alex.bennee@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:400c:c0c::22e Subject: [Qemu-arm] [RFC PATCH 8/9] target/arm/helpers: introduce ADVSIMD flags X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 17 Aug 2017 18:04:24 -0000 This is used to pass constant information to the helper. This includes immediate data and element counts/offsets. Signed-off-by: Alex Bennée --- target/arm/advsimd_helper_flags.h | 50 +++++++++++++++++++++++++++++++++++++++ target/arm/helper-a64.c | 1 + target/arm/translate-a64.c | 2 ++ 3 files changed, 53 insertions(+) create mode 100644 target/arm/advsimd_helper_flags.h diff --git a/target/arm/advsimd_helper_flags.h b/target/arm/advsimd_helper_flags.h new file mode 100644 index 0000000000..47429e6fd1 --- /dev/null +++ b/target/arm/advsimd_helper_flags.h @@ -0,0 +1,50 @@ +/* + * AArch64 Vector Flags + * + * Copyright (c) 2017 Linaro + * Author: Alex Bennée + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, see . + */ + +/* AdvSIMD element data + * + * We pack all the additional information for elements into a single + * 32 bit constant passed by register. Hopefully for groups of + * identical operations on different registers this should propergate + * nicely in the TCG. + * + * The following control element iteration: + * ADVSIMD_OPR_ELT - the count of elements affected + * ADVSIMD_ALL_ELT - the total count of elements (e.g. clear all-opr elements) + * ADVSIMD_DOFF_ELT - the offset for the destination register (e.g. foo2 ops) + * + * We encode immediate data in: + * ADVSIMD_DATA + * + * Typically this is things like shift counts and the like. + */ + +#define ADVSIMD_OPR_ELT_BITS 5 +#define ADVSIMD_OPR_ELT_SHIFT 0 +#define ADVSIMD_ALL_ELT_BITS 5 +#define ADVSIMD_ALL_ELT_SHIFT 5 +#define ADVSIMD_DOFF_ELT_BITS 5 +#define ADVSIMD_DOFF_ELT_SHIFT 10 +#define ADVSIMD_DATA_BITS 16 +#define ADVSIMD_DATA_SHIFT 16 + +#define GET_SIMD_DATA(t, d) extract32(d, \ + ADVSIMD_ ## t ## _SHIFT, \ + ADVSIMD_ ## t ## _BITS) diff --git a/target/arm/helper-a64.c b/target/arm/helper-a64.c index d9df82cff5..17b1edfb5f 100644 --- a/target/arm/helper-a64.c +++ b/target/arm/helper-a64.c @@ -30,6 +30,7 @@ #include "exec/exec-all.h" #include "exec/cpu_ldst.h" #include "qemu/int128.h" +#include "advsimd_helper_flags.h" #include "tcg.h" #include /* For crc32 */ diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index b5f48605a7..f474c5008b 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -34,6 +34,8 @@ #include "exec/helper-gen.h" #include "exec/log.h" +#include "advsimd_helper_flags.h" + #include "trace-tcg.h" /* Global registers */ -- 2.13.0 From MAILER-DAEMON Thu Aug 17 14:33:07 2017 Received: from list by lists.gnu.org with archive (Exim 4.71) id 1diPbP-0004TS-5g for mharc-qemu-arm@gnu.org; Thu, 17 Aug 2017 14:33:07 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:45480) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1diPbM-0004Rw-7D for qemu-arm@nongnu.org; Thu, 17 Aug 2017 14:33:05 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1diPbK-0006Z9-So for qemu-arm@nongnu.org; Thu, 17 Aug 2017 14:33:04 -0400 Resent-Date: Thu, 17 Aug 2017 14:33:04 -0400 Resent-Message-Id: Received: from sender-of-o52.zoho.com ([135.84.80.217]:21336) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1diPbF-0006Xd-Mn; Thu, 17 Aug 2017 14:32:57 -0400 Received: from [172.17.0.2] (23.253.156.214 [23.253.156.214]) by mx.zohomail.com with SMTPS id 1502994760334461.6627004021169; Thu, 17 Aug 2017 11:32:40 -0700 (PDT) Message-ID: <150299475927.27.5716239824585872477@205a2245145f> Reply-To: In-Reply-To: <20170817180404.29334-1-alex.bennee@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Resent-From: From: no-reply@patchew.org To: alex.bennee@linaro.org Cc: famz@redhat.com, rth@twiddle.net, cota@braap.org, batuzovk@ispras.ru, qemu-arm@nongnu.org, alex.bennee@linaro.org, qemu-devel@nongnu.org Date: Thu, 17 Aug 2017 11:32:40 -0700 (PDT) X-ZohoMailClient: External X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [fuzzy] X-Received-From: 135.84.80.217 Subject: Re: [Qemu-arm] [Qemu-devel] [RFC PATCH 0/9] TCG Vector types and example conversion X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 17 Aug 2017 18:33:05 -0000 SGksCgpUaGlzIHNlcmllcyBzZWVtcyB0byBoYXZlIHNvbWUgY29kaW5nIHN0eWxlIHByb2JsZW1z LiBTZWUgb3V0cHV0IGJlbG93IGZvcgptb3JlIGluZm9ybWF0aW9uOgoKVHlwZTogc2VyaWVzCk1l c3NhZ2UtaWQ6IDIwMTcwODE3MTgwNDA0LjI5MzM0LTEtYWxleC5iZW5uZWVAbGluYXJvLm9yZwpT dWJqZWN0OiBbUWVtdS1kZXZlbF0gW1JGQyBQQVRDSCAwLzldIFRDRyBWZWN0b3IgdHlwZXMgYW5k IGV4YW1wbGUgY29udmVyc2lvbgoKPT09IFRFU1QgU0NSSVBUIEJFR0lOID09PQojIS9iaW4vYmFz aAoKQkFTRT1iYXNlCm49MQp0b3RhbD0kKGdpdCBsb2cgLS1vbmVsaW5lICRCQVNFLi4gfCB3YyAt bCkKZmFpbGVkPTAKCmdpdCBjb25maWcgLS1sb2NhbCBkaWZmLnJlbmFtZWxpbWl0IDAKZ2l0IGNv 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[97.126.108.236]) by smtp.gmail.com with ESMTPSA id s11sm6717399pgr.53.2017.08.17.13.05.14 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 17 Aug 2017 13:05:14 -0700 (PDT) To: =?UTF-8?Q?Alex_Benn=c3=a9e?= , rth@twiddle.net, cota@braap.org, batuzovk@ispras.ru Cc: qemu-arm@nongnu.org, qemu-devel@nongnu.org References: <20170817180404.29334-1-alex.bennee@linaro.org> <20170817180404.29334-2-alex.bennee@linaro.org> From: Richard Henderson Message-ID: <6a15c518-1091-cac7-77b6-b833efd745c6@linaro.org> Date: Thu, 17 Aug 2017 13:05:12 -0700 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.2.1 MIME-Version: 1.0 In-Reply-To: <20170817180404.29334-2-alex.bennee@linaro.org> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 8bit X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::233 Subject: Re: [Qemu-arm] [Qemu-devel] [RFC PATCH 1/9] tcg/README: listify the TCG types. X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 17 Aug 2017 20:05:25 -0000 On 08/17/2017 11:03 AM, Alex Bennée wrote: > Although the other types are aliases lets make it clear what TCG types > are available. > > Signed-off-by: Alex Bennée > --- > tcg/README | 9 ++++++--- > 1 file changed, 6 insertions(+), 3 deletions(-) Reviewed-by: Richard Henderson r~ From MAILER-DAEMON Thu Aug 17 16:07:51 2017 Received: from list by lists.gnu.org with archive (Exim 4.71) id 1diR55-0002ps-Kg for mharc-qemu-arm@gnu.org; Thu, 17 Aug 2017 16:07:51 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:35580) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1diR53-0002oJ-Kk for qemu-arm@nongnu.org; Thu, 17 Aug 2017 16:07:50 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1diR4y-000890-Lu for qemu-arm@nongnu.org; Thu, 17 Aug 2017 16:07:49 -0400 Received: from mail-pg0-x22f.google.com ([2607:f8b0:400e:c05::22f]:37784) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1diR4y-00088a-Ff for qemu-arm@nongnu.org; Thu, 17 Aug 2017 16:07:44 -0400 Received: by mail-pg0-x22f.google.com with SMTP id y129so49563250pgy.4 for ; Thu, 17 Aug 2017 13:07:44 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=subject:to:cc:references:from:message-id:date:user-agent :mime-version:in-reply-to:content-language:content-transfer-encoding; bh=rI1er1wOi3h+tnssASY7Sv9sDPJKfx3oeIr8lG/TGCE=; b=G3wtbjQ6jAQ3kTGO9QI2SiGf2yUV42zor064D36qTZso/6x5FEodT5kXk2YbbBq4Vf q2qRqYTubCe1q6ffRfkHTcnOnHh0EQ4Z20KZZL7b58vjb8/plZ3rEEUAMdmGMPJUtPzH qjbFWWbYprWO/ERbmpfromh7ZlJV6Q33mUEtk= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:subject:to:cc:references:from:message-id:date :user-agent:mime-version:in-reply-to:content-language :content-transfer-encoding; bh=rI1er1wOi3h+tnssASY7Sv9sDPJKfx3oeIr8lG/TGCE=; b=dcTCqPyyaEU3vAVB2GQR5KpbEmPG/Sf1vt7HnqRk++fAI6sfeZBcH1nrzXfwPVQfJ1 yL2JzCs102rwSMmuTa9/Zx4vwNAJynDqX+AJC9gJMGT+u1rEE580zgN8MMBhTCheb9OE wTEgl1AHg/qmBxbymhxzajqpaMw4i89b4MeIK9BBP1CWr9uwY3KHZU9lLDBQMNyY5Dhq 1euz83F4RDZ052ftrthQO//0Xri+AXXEV/LUpZ0Ogmp6k/KkAyxZwOshiCz0Nz+vMocd CeH+Fwa+X7HaMdw/x2Ybqr3JL2TdEEKnM65+NRqmlvbhnhduteZbtDepBeymaSCz4x4g /vQQ== X-Gm-Message-State: AHYfb5jiGWA8rRgC4lWp/yDAlCbbWBKYYHkwLrQDLEdhzTVkr8QSmGNt FVw3/EFu3/JUAdOCjoud3g== X-Received: by 10.84.132.44 with SMTP id 41mr7002148ple.194.1503000463638; Thu, 17 Aug 2017 13:07:43 -0700 (PDT) Received: from bigtime.twiddle.net (97-126-108-236.tukw.qwest.net. [97.126.108.236]) by smtp.gmail.com with ESMTPSA id r5sm7722628pgn.45.2017.08.17.13.07.42 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 17 Aug 2017 13:07:42 -0700 (PDT) To: =?UTF-8?Q?Alex_Benn=c3=a9e?= , rth@twiddle.net, cota@braap.org, batuzovk@ispras.ru Cc: qemu-arm@nongnu.org, qemu-devel@nongnu.org References: <20170817180404.29334-1-alex.bennee@linaro.org> <20170817180404.29334-3-alex.bennee@linaro.org> From: Richard Henderson Message-ID: <7e2fa1a2-d5e7-e6fb-3b88-6b9f1f9f76d9@linaro.org> Date: Thu, 17 Aug 2017 13:07:40 -0700 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.2.1 MIME-Version: 1.0 In-Reply-To: <20170817180404.29334-3-alex.bennee@linaro.org> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 8bit X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::22f Subject: Re: [Qemu-arm] [Qemu-devel] [RFC PATCH 2/9] tcg: introduce the concepts of a TCGv_vec register type X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 17 Aug 2017 20:07:50 -0000 On 08/17/2017 11:03 AM, Alex Bennée wrote: > Currently it only makes sense for globals - i.e. registers directly > mapped to CPUEnv. > --- > tcg/README | 1 + > tcg/tcg.h | 20 ++++++++++++++++++++ > 2 files changed, 21 insertions(+) I'm not keen on this. I know it makes for nicer intermediate dumps, but I'd rather expose the pointer addition directly (or not, and fold it into a memory offset). r~ From MAILER-DAEMON Thu Aug 17 16:13:18 2017 Received: from list by lists.gnu.org with archive (Exim 4.71) id 1diRAM-0005Dr-GS for mharc-qemu-arm@gnu.org; Thu, 17 Aug 2017 16:13:18 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:36424) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1diRAK-0005Ct-Ew for qemu-arm@nongnu.org; Thu, 17 Aug 2017 16:13:17 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1diRAF-0003Oj-GQ for qemu-arm@nongnu.org; Thu, 17 Aug 2017 16:13:16 -0400 Received: from mail-pg0-x235.google.com ([2607:f8b0:400e:c05::235]:38078) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1diRAF-0003OB-8o for qemu-arm@nongnu.org; Thu, 17 Aug 2017 16:13:11 -0400 Received: by mail-pg0-x235.google.com with SMTP id t80so22082716pgb.5 for ; Thu, 17 Aug 2017 13:13:11 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=subject:to:cc:references:from:message-id:date:user-agent :mime-version:in-reply-to:content-language:content-transfer-encoding; bh=hLSpsz1d+nb9lePdmsz6dt0E00HVSdFMa+COk5lvYpI=; b=kD2lcXfYnmq6dfrlnkJd8XitZWrvO8YBv7fYgmzaMi6lGWpXktfu/XEOUz3uyejcWK 9USz81oIFks2tddZfXEjlDZUg//SyL3zT6pP/4K7g6ttj65e/9ZoygdkmFcBt57Xmoo/ WYauzvYXNrvyN3St/ECDd3aYU2qYIzTZ7oKqQ= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:subject:to:cc:references:from:message-id:date :user-agent:mime-version:in-reply-to:content-language :content-transfer-encoding; bh=hLSpsz1d+nb9lePdmsz6dt0E00HVSdFMa+COk5lvYpI=; b=t2H/MAWT1FPPZ6sYlVimot4t5DBI+9hJT2gvF8xnrd2wDzmHQ9f40Y9158Up8NHm27 KzQ47TysjnA+16My1ZVCUTVl8l8aIbIFV4kD0j5cGRamFFdVGWtrPIRP6iNWf3yqGNZ4 RsqThO4Nvigw2djy3S7F/7G/gov2DIx7VDsQTu6OHj78+HJ0TELlziIiIWbrfiVBNLej WT8KDIioJT5oxJ1FWxiCTq6+gA4k35LDY6rPhz/9Y26B91PYUK1hvzRj2yQ6s3x5OKf6 Hg4QPbV5EfvDHs0cQUmQur83Ilc5QoUd7PrS4kX4MOc7oVYbLkj0nIWYhZ2BaZLZbbTm 36Mg== X-Gm-Message-State: AHYfb5hd8IltJjBYyD87R8g/SeCisX9lIKxgQ85KzubJkCH5Y5TaZ7KG bGr9/bbxPzRVfk74 X-Received: by 10.98.15.86 with SMTP id x83mr6280292pfi.288.1503000790239; Thu, 17 Aug 2017 13:13:10 -0700 (PDT) Received: from bigtime.twiddle.net (97-126-108-236.tukw.qwest.net. [97.126.108.236]) by smtp.gmail.com with ESMTPSA id n1sm9022249pfj.46.2017.08.17.13.13.09 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 17 Aug 2017 13:13:09 -0700 (PDT) To: =?UTF-8?Q?Alex_Benn=c3=a9e?= , rth@twiddle.net, cota@braap.org, batuzovk@ispras.ru Cc: qemu-arm@nongnu.org, qemu-devel@nongnu.org References: <20170817180404.29334-1-alex.bennee@linaro.org> <20170817180404.29334-4-alex.bennee@linaro.org> From: Richard Henderson Message-ID: <63b2dd72-90bf-d9f6-9f7c-c9919904e74e@linaro.org> Date: Thu, 17 Aug 2017 13:13:07 -0700 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.2.1 MIME-Version: 1.0 In-Reply-To: <20170817180404.29334-4-alex.bennee@linaro.org> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 8bit X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::235 Subject: Re: [Qemu-arm] [Qemu-devel] [RFC PATCH 3/9] tcg: generate ptrs to vector registers X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 17 Aug 2017 20:13:17 -0000 On 08/17/2017 11:03 AM, Alex Bennée wrote: > As we operate directly on the vectors in memory we pass around the > address for TCG_TYPE_VECTOR. Currently only helpers ever see these > values but if we were to generate simd backend instructions they would > load directly from the backing store. > > We also need to ensure when copying from one temp register to the > other the right size is used. > > Signed-off-by: Alex Bennée > --- > tcg/tcg.c | 26 ++++++++++++++++++++++++-- > 1 file changed, 24 insertions(+), 2 deletions(-) > > diff --git a/tcg/tcg.c b/tcg/tcg.c > index 35598296c5..e16811d68d 100644 > --- a/tcg/tcg.c > +++ b/tcg/tcg.c > @@ -2034,7 +2034,21 @@ static void temp_load(TCGContext *s, TCGTemp *ts, TCGRegSet desired_regs, > break; > case TEMP_VAL_MEM: > reg = tcg_reg_alloc(s, desired_regs, allocated_regs, ts->indirect_base); > - tcg_out_ld(s, ts->type, reg, ts->mem_base->reg, ts->mem_offset); > + if (ts->type == TCG_TYPE_VECTOR) { > + /* Vector registers are ptr's to the memory representation */ > + TCGArg args[TCG_MAX_OP_ARGS]; > + int const_args[TCG_MAX_OP_ARGS]; > + args[0] = reg; > + args[1] = ts->mem_base->reg; > + args[2] = ts->mem_offset; > + const_args[0] = 0; > + const_args[1] = 0; > + const_args[2] = 1; > + /* FIXME: needs to by host_ptr centric */ > + tcg_out_op(s, INDEX_op_add_i64, args, const_args); This fails when the offset is out of range for the addition, and technically if the backend does not support 3-operand addition. You didn't see this because the x86 backend does use lea, and has a 32-bit offset. Once upon a time we had a tcg_out_addi; if we go this way with TCG_TYPE_VECTOR, we should re-introduce that. r~ From MAILER-DAEMON Thu Aug 17 16:13:42 2017 Received: from list by lists.gnu.org with archive (Exim 4.71) id 1diRAk-0005RV-LT for mharc-qemu-arm@gnu.org; Thu, 17 Aug 2017 16:13:42 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:36539) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1diRAi-0005Pk-0i for qemu-arm@nongnu.org; Thu, 17 Aug 2017 16:13:40 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1diRAd-0003mZ-2c for qemu-arm@nongnu.org; Thu, 17 Aug 2017 16:13:39 -0400 Received: from mail-pg0-x22b.google.com ([2607:f8b0:400e:c05::22b]:34239) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1diRAc-0003mA-TQ for qemu-arm@nongnu.org; Thu, 17 Aug 2017 16:13:35 -0400 Received: by mail-pg0-x22b.google.com with SMTP id u185so49523403pgb.1 for ; Thu, 17 Aug 2017 13:13:34 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=subject:to:cc:references:from:message-id:date:user-agent :mime-version:in-reply-to:content-language:content-transfer-encoding; bh=fb9oZkoAPRHkBwJ0RcynOFcq9KM/TFmuvQ+uC65nRoE=; b=XdJtkmbmFzZgjQTfdiu3XqJygFmeZoFf4p4ZSiyzEJ9lbXax1m273fpnBcUUb4IpOB BlJ898X4pTS/hzri1IHASh0hfl66Tj/cYIlDuPcVNpP9WY/NwxajcMEXW/FChPizcSHD B21uDG5Xbz2APtpPtYKAQ4CKs1ERZPncsYxsU= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:subject:to:cc:references:from:message-id:date :user-agent:mime-version:in-reply-to:content-language :content-transfer-encoding; bh=fb9oZkoAPRHkBwJ0RcynOFcq9KM/TFmuvQ+uC65nRoE=; b=RcCepg7fBUOzGCn48xlBBCc3FuhxCMMUAULXfQdCtCAbhpMaFf3KFQlERY6/1VTBvA xsizYWUZWZohj3B00KSdNirJP/Masir+DY8rlMvmUGV4Fjm6WxKAUJnmyqLcMOda0cCv Iy5w7LrgBBsziGcOCxNsDUMaIlHHqx72XiHr3gQcS+eq2Ugogoji5dNjTBh5gO4hM+x/ FKAwwo5R0qraNBVywJXZUJkx/dPEaVPO4NALG8LM90Ny0vWkBnVvCHWr1ESF0BeTSqfh odVccgBXouoY1jhKv3ctfDt99BwSEMSajDIObw6Ovb4Y8aLTBwjWxieNlBTULzqX2ijg 9jqQ== X-Gm-Message-State: AHYfb5i4TBIlo9mtK/X88BRIklzJzVLZZQA8mS+HEN9tbplHvDwHPL39 OqOUddsFhGGBO9aI X-Received: by 10.98.63.145 with SMTP id z17mr6323534pfj.174.1503000814151; Thu, 17 Aug 2017 13:13:34 -0700 (PDT) Received: from bigtime.twiddle.net (97-126-108-236.tukw.qwest.net. [97.126.108.236]) by smtp.gmail.com with ESMTPSA id 17sm8837081pfp.157.2017.08.17.13.13.32 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 17 Aug 2017 13:13:33 -0700 (PDT) To: =?UTF-8?Q?Alex_Benn=c3=a9e?= , rth@twiddle.net, cota@braap.org, batuzovk@ispras.ru Cc: Peter Maydell , qemu-arm@nongnu.org, qemu-devel@nongnu.org References: <20170817180404.29334-1-alex.bennee@linaro.org> <20170817180404.29334-6-alex.bennee@linaro.org> From: Richard Henderson Message-ID: <6bfb1943-5d9f-6940-a289-86dd354ccc29@linaro.org> Date: Thu, 17 Aug 2017 13:13:31 -0700 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.2.1 MIME-Version: 1.0 In-Reply-To: <20170817180404.29334-6-alex.bennee@linaro.org> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 8bit X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::22b Subject: Re: [Qemu-arm] [Qemu-devel] [RFC PATCH 5/9] arm/cpu.h: align VFP registers X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 17 Aug 2017 20:13:41 -0000 On 08/17/2017 11:04 AM, Alex Bennée wrote: > Signed-off-by: Alex Bennée > --- > target/arm/cpu.h | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) Reviewed-by: Richard Henderson r~ From MAILER-DAEMON Thu Aug 17 16:14:30 2017 Received: from list by lists.gnu.org with archive (Exim 4.71) id 1diRBW-00067e-6e for mharc-qemu-arm@gnu.org; Thu, 17 Aug 2017 16:14:30 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:36765) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1diRBT-00064s-Ln for qemu-arm@nongnu.org; Thu, 17 Aug 2017 16:14:28 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1diRBS-0004EI-Qq for qemu-arm@nongnu.org; Thu, 17 Aug 2017 16:14:27 -0400 Received: from mail-pg0-x22e.google.com ([2607:f8b0:400e:c05::22e]:34445) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1diRBS-0004E0-Kf for qemu-arm@nongnu.org; Thu, 17 Aug 2017 16:14:26 -0400 Received: by mail-pg0-x22e.google.com with SMTP id u185so49535482pgb.1 for ; Thu, 17 Aug 2017 13:14:26 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=subject:to:cc:references:from:message-id:date:user-agent :mime-version:in-reply-to:content-language:content-transfer-encoding; bh=2hz+3hhto0pQ81nNrRWmept0WBAQPHlK2qU6cEjZt9w=; b=bnOu9DeUsnrfzteVAY9/+V7E/T6uplI/VVb7ReyIgozVVzLdmbAd/2jB6ZXnCY6NuI Ik9d/z31KuBHmzd42nucI2GlXGrv/wR0mJKM4EjE5MqKUClbM1bAUJy+6idQE4bWoncO vIOd8kCkQ1BnLobqpKYOTMzwppBDncRDsy0ro= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:subject:to:cc:references:from:message-id:date :user-agent:mime-version:in-reply-to:content-language :content-transfer-encoding; bh=2hz+3hhto0pQ81nNrRWmept0WBAQPHlK2qU6cEjZt9w=; b=ZUe4y7Nlil6dXZFpDiq6N7ME3zQn/507y8UR+jzOVY2Uu0taLWJaLQov0kOgbisSmp FSH3iQqXl+DujNZE9Vcm8JK6Nf0crmyVovh2Ho5hBSRKxpsv+MN71erPq3D3gvcNeXL2 rS48NWJj4XXdUu0sCMDh4l2pdbmJAPix4YWV1s2RMAf0e+DKsvB8ZiNqLozlnxQiL5cy tSGC0qWoG8pY9P0gaTadd0IhFULPVghXE+tX+L1pFx3AiWR/gyPm861ZbR3R0NzsaOCs DMsfSaQ3hCtQJ8RlW4r33KnBHRnC6rz+0rZqkGXmo7JYFC+pk6t1lxoIiNGvY0qwiTg0 hRHA== X-Gm-Message-State: AHYfb5gzdK5Oqg6Ct74jU1VlEZNLk/HvdGJ3X/VqD5e4Ai2zXOT975rb BhW9UeZYtqAlqJMJKmJlIw== X-Received: by 10.99.140.76 with SMTP id q12mr6346204pgn.45.1503000865859; Thu, 17 Aug 2017 13:14:25 -0700 (PDT) Received: from bigtime.twiddle.net (97-126-108-236.tukw.qwest.net. [97.126.108.236]) by smtp.gmail.com with ESMTPSA id n12sm9351750pfa.148.2017.08.17.13.14.24 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 17 Aug 2017 13:14:25 -0700 (PDT) To: =?UTF-8?Q?Alex_Benn=c3=a9e?= , rth@twiddle.net, cota@braap.org, batuzovk@ispras.ru Cc: Peter Maydell , qemu-arm@nongnu.org, qemu-devel@nongnu.org References: <20170817180404.29334-1-alex.bennee@linaro.org> <20170817180404.29334-7-alex.bennee@linaro.org> From: Richard Henderson Message-ID: <36653cbe-3043-da48-3303-864f07a428bc@linaro.org> Date: Thu, 17 Aug 2017 13:14:23 -0700 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.2.1 MIME-Version: 1.0 In-Reply-To: <20170817180404.29334-7-alex.bennee@linaro.org> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 8bit X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::22e Subject: Re: [Qemu-arm] [Qemu-devel] [RFC PATCH 6/9] target/arm/translate-a64: regnames -> x_regnames X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 17 Aug 2017 20:14:28 -0000 On 08/17/2017 11:04 AM, Alex Bennée wrote: > -static const char *regnames[] = { > +static const char *x_regnames[] = { > "x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7", > "x8", "x9", "x10", "x11", "x12", "x13", "x14", "x15", > "x16", "x17", "x18", "x19", "x20", "x21", "x22", "x23", Mis-patch? There should be uses of this array to be renamed too. r~ From MAILER-DAEMON Thu Aug 17 16:24:01 2017 Received: from list by lists.gnu.org with archive (Exim 4.71) id 1diRKh-0001nS-Va for mharc-qemu-arm@gnu.org; Thu, 17 Aug 2017 16:24:01 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:38594) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1diRKf-0001mw-Pl for qemu-arm@nongnu.org; Thu, 17 Aug 2017 16:23:58 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1diRKb-0003Pk-S4 for qemu-arm@nongnu.org; Thu, 17 Aug 2017 16:23:57 -0400 Received: from mail-pg0-x233.google.com ([2607:f8b0:400e:c05::233]:34692) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1diRKb-0003PD-L2 for qemu-arm@nongnu.org; Thu, 17 Aug 2017 16:23:53 -0400 Received: by mail-pg0-x233.google.com with SMTP id u185so49672482pgb.1 for ; Thu, 17 Aug 2017 13:23:53 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=subject:to:cc:references:from:message-id:date:user-agent :mime-version:in-reply-to:content-language:content-transfer-encoding; bh=5ntoJ6WI/p14qEKhiuzconGBr/EddIsnOiFkKGFcB70=; b=GYgpJkTLipRUQO1GJB7/7wcf5tyNXTUpQMozun7SoWMupwtOcjHDc2WScSzArNm28+ q8ePzWfDzh0pNqgq+DnCxdJEKmOor9gUX/qffBm8pZAmSjUSIHDu535uWnxsgMx/ZBO3 Oac4wLgNVQaqH04h3FJIst3hgrODRGLi4jp7Y= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:subject:to:cc:references:from:message-id:date :user-agent:mime-version:in-reply-to:content-language :content-transfer-encoding; bh=5ntoJ6WI/p14qEKhiuzconGBr/EddIsnOiFkKGFcB70=; b=n6m2T8upKN1YrsNnNDJvjg897eLapnMtjTtIGL6cjcxDlhys1j/kihpF/tkc5/qVr+ jzm4s7EIqJrJOgsBmNaR94at2q4Do7+Uv4YVqjVito77Y1QoTC/wb3YJQtW+r3SAII2w mJ0JaYlwwPDiVg0YKXLGhom7MDrtdaXowpiwycAk/u4dVxFwsZPr3J6od/skQxlT/JNf ptaIDe3T4k4zvTSqz0F0nm7sNEx5DcpC0hkFHOoyaMmj964Vnf6ln3+mHcPqEEIA0H20 zeFfwtppxZ59THs2FRr6QYqPwtkLzNC85Nvati7NDMnUUvclrksnSG/kyJi8lQsdrSbq 3isQ== X-Gm-Message-State: AHYfb5itu8f+MNHz/p5Fne4TP+9r8W1cXfT2oyTmSGJ0cqbtYvpxV3Hn 9dXwwBWYEHd08ZdM X-Received: by 10.84.236.4 with SMTP id q4mr7024449plk.423.1503001432532; Thu, 17 Aug 2017 13:23:52 -0700 (PDT) Received: from bigtime.twiddle.net (97-126-108-236.tukw.qwest.net. [97.126.108.236]) by smtp.gmail.com with ESMTPSA id z125sm2257042pfz.108.2017.08.17.13.23.51 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 17 Aug 2017 13:23:51 -0700 (PDT) To: =?UTF-8?Q?Alex_Benn=c3=a9e?= , rth@twiddle.net, cota@braap.org, batuzovk@ispras.ru Cc: Peter Maydell , qemu-arm@nongnu.org, qemu-devel@nongnu.org References: <20170817180404.29334-1-alex.bennee@linaro.org> <20170817180404.29334-10-alex.bennee@linaro.org> From: Richard Henderson Message-ID: <0aac1365-72e1-ff17-b9e2-4bdd5c34901e@linaro.org> Date: Thu, 17 Aug 2017 13:23:49 -0700 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.2.1 MIME-Version: 1.0 In-Reply-To: <20170817180404.29334-10-alex.bennee@linaro.org> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 8bit X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::233 Subject: Re: [Qemu-arm] [Qemu-devel] [RFC PATCH 9/9] target/arm/translate-a64: vectorise smull vD.4s, vN.[48]s, vM.h[] X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 17 Aug 2017 20:23:58 -0000 On 08/17/2017 11:04 AM, Alex Bennée wrote: > + int32_t *rd = (int32_t *) d; > + int16_t *rn = (int16_t *) n; > + int16_t rm = (int16_t) m; > + int i; > + > + #pragma GCC ivdep > + for (i = 0; i < opr_elt; ++i) { > + rd[i] = rn[i + doff_elt] * rm; > + } You need to run this loop backward to avoid clobbering data when rd == rn. I thought you'd put m into ADVSIMD_DATA. > > + if (is_q) { > + simd_info = deposit32(simd_info, > + ADVSIMD_DOFF_ELT_SHIFT, ADVSIMD_DOFF_ELT_BITS, 4); > + } It'd probably be useful to have a macro to clean this up: #define PUT_SIMD_DATA(t, d) \ deposit32(0, ADVSIMD_ ## t ## _SHIFT, ADVSIMD_ ## t ## _BITS, (d)) simd_info |= PUT_SIMD_DATA(DOFF_ELT, 4) that said, folding DOFF into the pointer that gets passed in the first place seems a better solution to me. r~ From MAILER-DAEMON Thu Aug 17 17:06:54 2017 Received: from list by lists.gnu.org with archive (Exim 4.71) id 1diS0E-00018Y-Lt for mharc-qemu-arm@gnu.org; Thu, 17 Aug 2017 17:06:54 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:40488) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1diNZv-0005HM-06 for qemu-arm@nongnu.org; Thu, 17 Aug 2017 12:23:28 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1diNZr-00035P-Pf for qemu-arm@nongnu.org; Thu, 17 Aug 2017 12:23:26 -0400 Received: from mail-co1nam03on0067.outbound.protection.outlook.com ([104.47.40.67]:15008 helo=NAM03-CO1-obe.outbound.protection.outlook.com) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1diNZr-00035A-7X; Thu, 17 Aug 2017 12:23:23 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=CAVIUMNETWORKS.onmicrosoft.com; s=selector1-cavium-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version; bh=JZyyBPClhAQppuzj/UfrtPTtEtiq2+IAJeP6o09cS3E=; b=nVRWAw54yBd8/FKz5cF3a7WDvU0vipPOEuyD3UVnbNO2BIJY8cxI/utlaVlPOwnfO1KXKwYraV7vC9HccLeh0gIaiRntlFaECQoF2lE5wxOUFU/Y87muxjTEZ1HrjeNRxWhnsLbHQarnAjPn2gcdbEkI+GIjT6BjRvBZjpNEbm8= Authentication-Results: spf=none (sender IP is ) smtp.mailfrom=Linu.Cherian@cavium.com; Received: from localhost (111.93.218.67) by DM5PR07MB3609.namprd07.prod.outlook.com (10.164.153.159) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384_P256) id 15.1.1341.21; Thu, 17 Aug 2017 16:23:14 +0000 Received: by localhost (sSMTP sendmail emulation); Thu, 17 Aug 2017 21:52:53 +0530 Date: Thu, 17 Aug 2017 21:52:53 +0530 From: Linu Cherian To: Auger Eric Cc: Jean-Philippe Brucker , Linu Cherian , peter.maydell@linaro.org, kevin.tian@intel.com, drjones@redhat.com, mst@redhat.com, marc.zyngier@arm.com, tn@semihalf.com, will.deacon@arm.com, qemu-devel@nongnu.org, peterx@redhat.com, alex.williamson@redhat.com, qemu-arm@nongnu.org, bharat.bhushan@nxp.com, christoffer.dall@linaro.org, eric.auger.pro@gmail.com Message-ID: <20170817162253.GA6192@virtx40> References: <1501579994-3320-1-git-send-email-eric.auger@redhat.com> <20170817112627.GA5417@virtx40> <20c68b9d-380d-1fbc-0fae-a5af44c2cdb2@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; 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It currently works with ARM virt machine only, as the machine > >>> must handle the dt binding between the virtio-mmio "iommu" node and > >>> the PCI host bridge node. > >>> > >>> ACPI booting is not yet supported. > >>> > >>> Best Regards > >>> > >>> Eric > >>> > >>> This series can be found at: > >>> https://github.com/eauger/qemu/tree/v2.10.0-rc0-virtio-iommu-rfcv3 > >>> > >>> References: > >>> [1] [RFC 0/3] virtio-iommu: a paravirtualized IOMMU, > >>> [2] [RFC PATCH linux] iommu: Add virtio-iommu driver > >>> [3] [RFC PATCH kvmtool 00/15] Add virtio-iommu > >>> > >>> Testing: > >>> - >= 4.12 guest kernel + virtio-iommu driver [2] > >>> - guest using a virtio-net-pci device: > >>> ,vhost=off,iommu_platform,disable-modern=off,disable-legacy=on > >> > >> Was trying to test this out and facing issues. > >> Guest and Host Kernel - git://linux-arm.org/linux-jpb.git, Branch virtio-iommu/v0.4 > >> Qemu - As mentioned above. > > > > Could you try branch virtio-iommu/v0.1? It contains the UAPI headers > > compatible with this RFC. > Thank you Jean. Yes the QEMU virtio-iommu device is based on the first > user API written in [2]. I plan to rebase on v0.4 in short delay. Jean > can I rebase on virtio-iommu/v0.4 or shall I wait a bit more? > > Thanks Yes, virtio-iommu/v0.1 works for me. Thanks. > > Eric > > > > Thanks, > > Jean > > -- Linu cherian From MAILER-DAEMON Thu Aug 17 19:01:25 2017 Received: from list by lists.gnu.org with archive (Exim 4.71) id 1diTn3-0004ua-A4 for mharc-qemu-arm@gnu.org; Thu, 17 Aug 2017 19:01:25 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:44461) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1diTn1-0004sp-0o for qemu-arm@nongnu.org; Thu, 17 Aug 2017 19:01:24 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1diTmz-0000q3-Ug for qemu-arm@nongnu.org; Thu, 17 Aug 2017 19:01:23 -0400 Received: from mail-pg0-x229.google.com ([2607:f8b0:400e:c05::229]:33450) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1diTmz-0000oB-OF for qemu-arm@nongnu.org; Thu, 17 Aug 2017 19:01:21 -0400 Received: by mail-pg0-x229.google.com with SMTP id t3so23903193pgt.0 for ; Thu, 17 Aug 2017 16:01:21 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=9o+4s+u+HhA1SN1wAmIK4x0UqDGVW4ct/r56gOt0Xg0=; b=ERhOP+bZ0PJ2PEOW+/ErsB9nFCLtJqJLFDUj272WDZ0MjFuhNhXwKnFnAmMUKs4A7s Hj8cuiKw2JYV52xfx6PLq7IEAaweD9doF4Md1XiAcX3CdQP0ajE6QRFcNqOvRiEh36rg Z7zWyt9Sy5eLrqYruYPWdiwWhW6ZteYTQT4tw= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=9o+4s+u+HhA1SN1wAmIK4x0UqDGVW4ct/r56gOt0Xg0=; b=WCd6AKaEx6E/in/ZxQmc2WtD0YAgSIwiVRgvUVjDZfuIoHH0MGnJnEOlHyF7KH6G2h DY+JzwO+0emsMRXt0c/PWxMG0bmZBN5MdLrlN8lj/FmnuXAU5N3qyaTeF3sww+TQAspp I6EWFihmMwRbh3dDOMmywOiu0ZPP90G1ojWhA5kMN6Br8ofG378Q/23/f5JfJyjLoZEb 9gndk0unFLlImd+mqvWXtRl6216suot+7PJJxBFYsOL91I+QCTOspG3sChB6gg+iHFLc VnUtIQlPh5gfI7fM4avsjrioaoLvq4Ke3Zid4+MsiG/Sd9q5zGuxbWHy5BFuBFn1U/UB BM+g== X-Gm-Message-State: AHYfb5hEzr+eOKvwqFUY3BHTJTv4A7SPNQQtsZCFjiAUT6or1dy66GuI I3QWImmMpX7bUKtx X-Received: by 10.98.198.145 with SMTP id x17mr6922847pfk.272.1503010880804; Thu, 17 Aug 2017 16:01:20 -0700 (PDT) Received: from bigtime.twiddle.net (97-126-108-236.tukw.qwest.net. [97.126.108.236]) by smtp.gmail.com with ESMTPSA id c23sm5190043pfc.136.2017.08.17.16.01.19 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 17 Aug 2017 16:01:19 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, alex.bennee@linaro.org Date: Thu, 17 Aug 2017 16:01:09 -0700 Message-Id: <20170817230114.3655-4-richard.henderson@linaro.org> X-Mailer: git-send-email 2.13.5 In-Reply-To: <20170817230114.3655-1-richard.henderson@linaro.org> References: <20170817230114.3655-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::229 Subject: [Qemu-arm] [PATCH 3/8] tcg: Add types for host vectors X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 17 Aug 2017 23:01:24 -0000 Nothing uses or enables them yet. Signed-off-by: Richard Henderson --- tcg/tcg.h | 5 +++++ tcg/tcg.c | 2 +- 2 files changed, 6 insertions(+), 1 deletion(-) diff --git a/tcg/tcg.h b/tcg/tcg.h index dd97095af5..1277caed3d 100644 --- a/tcg/tcg.h +++ b/tcg/tcg.h @@ -256,6 +256,11 @@ typedef struct TCGPool { typedef enum TCGType { TCG_TYPE_I32, TCG_TYPE_I64, + + TCG_TYPE_V64, + TCG_TYPE_V128, + TCG_TYPE_V256, + TCG_TYPE_COUNT, /* number of different types */ /* An alias for the size of the host register. */ diff --git a/tcg/tcg.c b/tcg/tcg.c index 787c8ba0f7..ea78d47fad 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -118,7 +118,7 @@ static TCGReg tcg_reg_alloc_new(TCGContext *s, TCGType t) static bool tcg_out_ldst_finalize(TCGContext *s); #endif -static TCGRegSet tcg_target_available_regs[2]; +static TCGRegSet tcg_target_available_regs[TCG_TYPE_COUNT]; static TCGRegSet tcg_target_call_clobber_regs; #if TCG_TARGET_INSN_UNIT_SIZE == 1 -- 2.13.5 From MAILER-DAEMON Thu Aug 17 19:01:30 2017 Received: from list by lists.gnu.org with archive (Exim 4.71) id 1diTn6-0004yB-Ai for mharc-qemu-arm@gnu.org; Thu, 17 Aug 2017 19:01:29 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:44462) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1diTn1-0004sq-0v for qemu-arm@nongnu.org; Thu, 17 Aug 2017 19:01:24 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1diTmy-0000m7-Jf for qemu-arm@nongnu.org; Thu, 17 Aug 2017 19:01:23 -0400 Received: from mail-pg0-x233.google.com ([2607:f8b0:400e:c05::233]:38797) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1diTmy-0000ki-Ao for qemu-arm@nongnu.org; Thu, 17 Aug 2017 19:01:20 -0400 Received: by mail-pg0-x233.google.com with SMTP id t80so24355443pgb.5 for ; Thu, 17 Aug 2017 16:01:20 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=aXDZ4Qr9mwfYKP1Hb4K6fjgDzUCvCw9IzsWpbOBP7G0=; b=TXNcPQ8qLiZ3cZen6iUEA4m0Jsfn/DYXvMtximn7ImIWf0YkK5RkHY5Z+lwX+gpuvm k5c4PyN7e1pAPlEPAxkLgwaCpUKDkaljzxKAVNNrSYY9R9FE0k5S+IYD+LVZbqAR40vi VJL9vyISIzfpC7MvYPE8nBnleg+IbgdwNGpIM= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=aXDZ4Qr9mwfYKP1Hb4K6fjgDzUCvCw9IzsWpbOBP7G0=; b=rfCM/pb+5Jsv7QexBAiLPUTKUBT58kzIYb06VUBbfYykGMYiiV12VQ/FngCGtwtRET c5n32lKK1dZhYAXyfA8KE/2S9yBBfTR2gzQJg4bpXyU0OzRVGq3MTAxbCgROMYacBMjK x8Kh2+68YGparlcGv95ivlYOkTbhvZBxegKMLgwQOLSdH8fb1aRRcJBLqchwOGWzykqe 0WZXFMjhonvWKWPA62YGyAnKTqiFtFp+639DyG/P7aBBdYkKM/6kSoIWQUPfJXFtvtnS 25gdjzww7OD97VMQUP0i1p7+ciCNACBDNttE2rLgWbV15clunYVBdO7Lw5EaEplN/NgY 194Q== X-Gm-Message-State: AHYfb5i9UZl983Dv0jG5oKiLxCetOEO1M8J5o3rJR9FyWpNmAQtnug/N riPN1OjtFJaqpteY X-Received: by 10.84.171.195 with SMTP id l61mr7755983plb.464.1503010879346; Thu, 17 Aug 2017 16:01:19 -0700 (PDT) Received: from bigtime.twiddle.net (97-126-108-236.tukw.qwest.net. [97.126.108.236]) by smtp.gmail.com with ESMTPSA id c23sm5190043pfc.136.2017.08.17.16.01.18 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 17 Aug 2017 16:01:18 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, alex.bennee@linaro.org Date: Thu, 17 Aug 2017 16:01:08 -0700 Message-Id: <20170817230114.3655-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.13.5 In-Reply-To: <20170817230114.3655-1-richard.henderson@linaro.org> References: <20170817230114.3655-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::233 Subject: [Qemu-arm] [PATCH 2/8] target/arm: Use generic vector infrastructure for aa64 add/sub/logic X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 17 Aug 2017 23:01:24 -0000 Signed-off-by: Richard Henderson --- target/arm/translate-a64.c | 137 ++++++++++++++++++++++++++++----------------- 1 file changed, 87 insertions(+), 50 deletions(-) diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 2200e25be0..025354f983 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -21,6 +21,7 @@ #include "cpu.h" #include "exec/exec-all.h" #include "tcg-op.h" +#include "tcg-op-gvec.h" #include "qemu/log.h" #include "arm_ldst.h" #include "translate.h" @@ -82,6 +83,7 @@ typedef void NeonGenTwoDoubleOPFn(TCGv_i64, TCGv_i64, TCGv_i64, TCGv_ptr); typedef void NeonGenOneOpFn(TCGv_i64, TCGv_i64); typedef void CryptoTwoOpEnvFn(TCGv_ptr, TCGv_i32, TCGv_i32); typedef void CryptoThreeOpEnvFn(TCGv_ptr, TCGv_i32, TCGv_i32, TCGv_i32); +typedef void GVecGenTwoFn(uint32_t, uint32_t, uint32_t, uint32_t, uint32_t); /* initialize TCG globals. */ void a64_translate_init(void) @@ -537,6 +539,21 @@ static inline int vec_reg_offset(DisasContext *s, int regno, return offs; } +/* Return the offset info CPUARMState of the "whole" vector register Qn. */ +static inline int vec_full_reg_offset(DisasContext *s, int regno) +{ + assert_fp_access_checked(s); + return offsetof(CPUARMState, vfp.regs[regno * 2]); +} + +/* Return the byte size of the "whole" vector register, VL / 8. */ +static inline int vec_full_reg_size(DisasContext *s) +{ + /* FIXME SVE: We should put the composite ZCR_EL* value into tb->flags. + In the meantime this is just the AdvSIMD length of 128. */ + return 128 / 8; +} + /* Return the offset into CPUARMState of a slice (from * the least significant end) of FP register Qn (ie * Dn, Sn, Hn or Bn). @@ -9042,11 +9059,38 @@ static void disas_simd_3same_logic(DisasContext *s, uint32_t insn) bool is_q = extract32(insn, 30, 1); TCGv_i64 tcg_op1, tcg_op2, tcg_res[2]; int pass; + GVecGenTwoFn *gvec_op; if (!fp_access_check(s)) { return; } + switch (size + 4 * is_u) { + case 0: /* AND */ + gvec_op = tcg_gen_gvec_and8; + goto do_gvec; + case 1: /* BIC */ + gvec_op = tcg_gen_gvec_andc8; + goto do_gvec; + case 2: /* ORR */ + gvec_op = tcg_gen_gvec_or8; + goto do_gvec; + case 3: /* ORN */ + gvec_op = tcg_gen_gvec_orc8; + goto do_gvec; + case 4: /* EOR */ + gvec_op = tcg_gen_gvec_xor8; + goto do_gvec; + do_gvec: + gvec_op(vec_full_reg_offset(s, rd), + vec_full_reg_offset(s, rn), + vec_full_reg_offset(s, rm), + is_q ? 16 : 8, vec_full_reg_size(s)); + return; + } + + /* Note that we've now eliminated all !is_u. */ + tcg_op1 = tcg_temp_new_i64(); tcg_op2 = tcg_temp_new_i64(); tcg_res[0] = tcg_temp_new_i64(); @@ -9056,47 +9100,27 @@ static void disas_simd_3same_logic(DisasContext *s, uint32_t insn) read_vec_element(s, tcg_op1, rn, pass, MO_64); read_vec_element(s, tcg_op2, rm, pass, MO_64); - if (!is_u) { - switch (size) { - case 0: /* AND */ - tcg_gen_and_i64(tcg_res[pass], tcg_op1, tcg_op2); - break; - case 1: /* BIC */ - tcg_gen_andc_i64(tcg_res[pass], tcg_op1, tcg_op2); - break; - case 2: /* ORR */ - tcg_gen_or_i64(tcg_res[pass], tcg_op1, tcg_op2); - break; - case 3: /* ORN */ - tcg_gen_orc_i64(tcg_res[pass], tcg_op1, tcg_op2); - break; - } - } else { - if (size != 0) { - /* B* ops need res loaded to operate on */ - read_vec_element(s, tcg_res[pass], rd, pass, MO_64); - } + /* B* ops need res loaded to operate on */ + read_vec_element(s, tcg_res[pass], rd, pass, MO_64); - switch (size) { - case 0: /* EOR */ - tcg_gen_xor_i64(tcg_res[pass], tcg_op1, tcg_op2); - break; - case 1: /* BSL bitwise select */ - tcg_gen_xor_i64(tcg_op1, tcg_op1, tcg_op2); - tcg_gen_and_i64(tcg_op1, tcg_op1, tcg_res[pass]); - tcg_gen_xor_i64(tcg_res[pass], tcg_op2, tcg_op1); - break; - case 2: /* BIT, bitwise insert if true */ - tcg_gen_xor_i64(tcg_op1, tcg_op1, tcg_res[pass]); - tcg_gen_and_i64(tcg_op1, tcg_op1, tcg_op2); - tcg_gen_xor_i64(tcg_res[pass], tcg_res[pass], tcg_op1); - break; - case 3: /* BIF, bitwise insert if false */ - tcg_gen_xor_i64(tcg_op1, tcg_op1, tcg_res[pass]); - tcg_gen_andc_i64(tcg_op1, tcg_op1, tcg_op2); - tcg_gen_xor_i64(tcg_res[pass], tcg_res[pass], tcg_op1); - break; - } + switch (size) { + case 1: /* BSL bitwise select */ + tcg_gen_xor_i64(tcg_op1, tcg_op1, tcg_op2); + tcg_gen_and_i64(tcg_op1, tcg_op1, tcg_res[pass]); + tcg_gen_xor_i64(tcg_res[pass], tcg_op2, tcg_op1); + break; + case 2: /* BIT, bitwise insert if true */ + tcg_gen_xor_i64(tcg_op1, tcg_op1, tcg_res[pass]); + tcg_gen_and_i64(tcg_op1, tcg_op1, tcg_op2); + tcg_gen_xor_i64(tcg_res[pass], tcg_res[pass], tcg_op1); + break; + case 3: /* BIF, bitwise insert if false */ + tcg_gen_xor_i64(tcg_op1, tcg_op1, tcg_res[pass]); + tcg_gen_andc_i64(tcg_op1, tcg_op1, tcg_op2); + tcg_gen_xor_i64(tcg_res[pass], tcg_res[pass], tcg_op1); + break; + default: + g_assert_not_reached(); } } @@ -9370,6 +9394,7 @@ static void disas_simd_3same_int(DisasContext *s, uint32_t insn) int rn = extract32(insn, 5, 5); int rd = extract32(insn, 0, 5); int pass; + GVecGenTwoFn *gvec_op; switch (opcode) { case 0x13: /* MUL, PMUL */ @@ -9409,6 +9434,28 @@ static void disas_simd_3same_int(DisasContext *s, uint32_t insn) return; } + switch (opcode) { + case 0x10: /* ADD, SUB */ + { + static GVecGenTwoFn * const fns[4][2] = { + { tcg_gen_gvec_add8, tcg_gen_gvec_sub8 }, + { tcg_gen_gvec_add16, tcg_gen_gvec_sub16 }, + { tcg_gen_gvec_add32, tcg_gen_gvec_sub32 }, + { tcg_gen_gvec_add64, tcg_gen_gvec_sub64 }, + }; + gvec_op = fns[size][u]; + goto do_gvec; + } + break; + + do_gvec: + gvec_op(vec_full_reg_offset(s, rd), + vec_full_reg_offset(s, rn), + vec_full_reg_offset(s, rm), + is_q ? 16 : 8, vec_full_reg_size(s)); + return; + } + if (size == 3) { assert(is_q); for (pass = 0; pass < 2; pass++) { @@ -9581,16 +9628,6 @@ static void disas_simd_3same_int(DisasContext *s, uint32_t insn) genfn = fns[size][u]; break; } - case 0x10: /* ADD, SUB */ - { - static NeonGenTwoOpFn * const fns[3][2] = { - { gen_helper_neon_add_u8, gen_helper_neon_sub_u8 }, - { gen_helper_neon_add_u16, gen_helper_neon_sub_u16 }, - { tcg_gen_add_i32, tcg_gen_sub_i32 }, - }; - genfn = fns[size][u]; - break; - } case 0x11: /* CMTST, CMEQ */ { static NeonGenTwoOpFn * const fns[3][2] = { -- 2.13.5 From MAILER-DAEMON Thu Aug 17 19:01:33 2017 Received: from list by lists.gnu.org with archive (Exim 4.71) id 1diTnA-00051f-R3 for mharc-qemu-arm@gnu.org; Thu, 17 Aug 2017 19:01:32 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:44569) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1diTn5-0004xg-Va for qemu-arm@nongnu.org; Thu, 17 Aug 2017 19:01:30 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1diTn0-0000qE-0N for qemu-arm@nongnu.org; Thu, 17 Aug 2017 19:01:28 -0400 Received: from mail-pg0-x22b.google.com ([2607:f8b0:400e:c05::22b]:36956) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1diTmz-0000nk-MB for qemu-arm@nongnu.org; Thu, 17 Aug 2017 19:01:21 -0400 Received: by mail-pg0-x22b.google.com with SMTP id y129so51924765pgy.4 for ; Thu, 17 Aug 2017 16:01:21 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=6IuCfVCVWZnbLbStTM3CUG3Tw378RJWUNZA3UpqaoME=; b=HFo6/2zN2J4WP4XpPEfxz1htFoKxrkWDoeCwSZOFFO3LDcTHQFMm4IluN8zVNDlIXT bYvyf3TgmNLlVOKVa6ThZen0jBM4gKa8AGN0hjkBM3wULth3tNGFtuawxLCNnRV8P/Sb T8IyC60YFJHgGcmj9UHeE2AIR6zgZIPaiXW6M= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=6IuCfVCVWZnbLbStTM3CUG3Tw378RJWUNZA3UpqaoME=; b=UtQ9EP+lrUZir+9V4QvtF70wmw5OCq0Aea8LWZtYJNKV+bqh2VQDjGYh4d0IrdqFOW oaWGgFraOBxEHDF0PJr0ClLxeqNW4VxZ9YjbZlMNE91g46MlX+cHrFdMTgWvmvGKguQO 6OnWzxttFyAyXzceawI1kQg8Mfhj08v308/3CddmWW1m63FeGdUyKk/MkoK1OaR31dj7 5gz2u3Ga7tp32p7vHvAYosNxvb8ykpI6PIhQ4wc+10eMRzCTepvJoGlqCPNxGaWzK0nd aKIwGmua8qkuqb3IV16FPVaaeX+621IkV4kCBRsJiDBpJgmfWXsOzWJXARauyMjekwyI bN1Q== X-Gm-Message-State: AHYfb5iq3j1mx2Dnjrl1Xyy4UrFrFo3JLIc0R26EdPQ8Wp6LlDu0Y5tL GtjCDvhGThAF6iXf X-Received: by 10.98.70.132 with SMTP id o4mr6736746pfi.104.1503010877999; Thu, 17 Aug 2017 16:01:17 -0700 (PDT) Received: from bigtime.twiddle.net (97-126-108-236.tukw.qwest.net. [97.126.108.236]) by smtp.gmail.com with ESMTPSA id c23sm5190043pfc.136.2017.08.17.16.01.16 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 17 Aug 2017 16:01:16 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, alex.bennee@linaro.org Date: Thu, 17 Aug 2017 16:01:07 -0700 Message-Id: <20170817230114.3655-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.13.5 In-Reply-To: <20170817230114.3655-1-richard.henderson@linaro.org> References: <20170817230114.3655-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::22b Subject: [Qemu-arm] [PATCH 1/8] tcg: Add generic vector infrastructure and ops for add/sub/logic X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 17 Aug 2017 23:01:31 -0000 Signed-off-by: Richard Henderson --- Makefile.target | 5 +- tcg/tcg-op-gvec.h | 88 ++++++++++ tcg/tcg-runtime.h | 16 ++ tcg/tcg-op-gvec.c | 443 +++++++++++++++++++++++++++++++++++++++++++++++++ tcg/tcg-runtime-gvec.c | 199 ++++++++++++++++++++++ 5 files changed, 749 insertions(+), 2 deletions(-) create mode 100644 tcg/tcg-op-gvec.h create mode 100644 tcg/tcg-op-gvec.c create mode 100644 tcg/tcg-runtime-gvec.c diff --git a/Makefile.target b/Makefile.target index 7f42c45db8..9ae3e904f7 100644 --- a/Makefile.target +++ b/Makefile.target @@ -93,8 +93,9 @@ all: $(PROGS) stap # cpu emulator library obj-y += exec.o obj-y += accel/ -obj-$(CONFIG_TCG) += tcg/tcg.o tcg/tcg-op.o tcg/optimize.o -obj-$(CONFIG_TCG) += tcg/tcg-common.o tcg/tcg-runtime.o +obj-$(CONFIG_TCG) += tcg/tcg.o tcg/tcg-common.o tcg/optimize.o +obj-$(CONFIG_TCG) += tcg/tcg-op.o tcg/tcg-op-gvec.o +obj-$(CONFIG_TCG) += tcg/tcg-runtime.o tcg/tcg-runtime-gvec.o obj-$(CONFIG_TCG_INTERPRETER) += tcg/tci.o obj-$(CONFIG_TCG_INTERPRETER) += disas/tci.o obj-y += fpu/softfloat.o diff --git a/tcg/tcg-op-gvec.h b/tcg/tcg-op-gvec.h new file mode 100644 index 0000000000..10db3599a5 --- /dev/null +++ b/tcg/tcg-op-gvec.h @@ -0,0 +1,88 @@ +/* + * Generic vector operation expansion + * + * Copyright (c) 2017 Linaro + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, see . + */ + +/* + * "Generic" vectors. All operands are given as offsets from ENV, + * and therefore cannot also be allocated via tcg_global_mem_new_*. + * OPSZ is the byte size of the vector upon which the operation is performed. + * CLSZ is the byte size of the full vector; bytes beyond OPSZ are cleared. + * + * All sizes must be 8 or any multiple of 16. + * When OPSZ is 8, the alignment may be 8, otherwise must be 16. + * Operands may completely, but not partially, overlap. + */ + +/* Fundamental operation expanders. These are exposed to the front ends + so that target-specific SIMD operations can be handled similarly to + the standard SIMD operations. */ + +typedef struct { + /* "Small" sizes: expand inline as a 64-bit or 32-bit lane. + Generally only one of these will be non-NULL. */ + void (*fni8)(TCGv_i64, TCGv_i64, TCGv_i64); + void (*fni4)(TCGv_i32, TCGv_i32, TCGv_i32); + /* Similarly, but load up a constant and re-use across lanes. */ + void (*fni8x)(TCGv_i64, TCGv_i64, TCGv_i64, TCGv_i64); + uint64_t extra_value; + /* Larger sizes: expand out-of-line helper w/size descriptor. */ + void (*fno)(TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_i32); +} GVecGen3; + +void tcg_gen_gvec_3(uint32_t dofs, uint32_t aofs, uint32_t bofs, + uint32_t opsz, uint32_t clsz, const GVecGen3 *); + +#define DEF_GVEC_2(X) \ + void tcg_gen_gvec_##X(uint32_t dofs, uint32_t aofs, uint32_t bofs, \ + uint32_t opsz, uint32_t clsz) + +DEF_GVEC_2(add8); +DEF_GVEC_2(add16); +DEF_GVEC_2(add32); +DEF_GVEC_2(add64); + +DEF_GVEC_2(sub8); +DEF_GVEC_2(sub16); +DEF_GVEC_2(sub32); +DEF_GVEC_2(sub64); + +DEF_GVEC_2(and8); +DEF_GVEC_2(or8); +DEF_GVEC_2(xor8); +DEF_GVEC_2(andc8); +DEF_GVEC_2(orc8); + +#undef DEF_GVEC_2 + +/* + * 64-bit vector operations. Use these when the register has been + * allocated with tcg_global_mem_new_i64. OPSZ = CLSZ = 8. + */ + +#define DEF_VEC8_2(X) \ + void tcg_gen_vec8_##X(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b) + +DEF_VEC8_2(add8); +DEF_VEC8_2(add16); +DEF_VEC8_2(add32); + +DEF_VEC8_2(sub8); +DEF_VEC8_2(sub16); +DEF_VEC8_2(sub32); + +#undef DEF_VEC8_2 diff --git a/tcg/tcg-runtime.h b/tcg/tcg-runtime.h index c41d38a557..f8d07090f8 100644 --- a/tcg/tcg-runtime.h +++ b/tcg/tcg-runtime.h @@ -134,3 +134,19 @@ GEN_ATOMIC_HELPERS(xor_fetch) GEN_ATOMIC_HELPERS(xchg) #undef GEN_ATOMIC_HELPERS + +DEF_HELPER_FLAGS_4(gvec_add8, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_4(gvec_add16, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_4(gvec_add32, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_4(gvec_add64, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) + +DEF_HELPER_FLAGS_4(gvec_sub8, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_4(gvec_sub16, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_4(gvec_sub32, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_4(gvec_sub64, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) + +DEF_HELPER_FLAGS_4(gvec_and8, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_4(gvec_or8, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_4(gvec_xor8, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_4(gvec_andc8, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_4(gvec_orc8, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) diff --git a/tcg/tcg-op-gvec.c b/tcg/tcg-op-gvec.c new file mode 100644 index 0000000000..6de49dc07f --- /dev/null +++ b/tcg/tcg-op-gvec.c @@ -0,0 +1,443 @@ +/* + * Generic vector operation expansion + * + * Copyright (c) 2017 Linaro + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, see . + */ + +#include "qemu/osdep.h" +#include "qemu-common.h" +#include "cpu.h" +#include "exec/exec-all.h" +#include "tcg.h" +#include "tcg-op.h" +#include "tcg-op-gvec.h" +#include "trace-tcg.h" +#include "trace/mem.h" + +#define REP8(x) ((x) * 0x0101010101010101ull) +#define REP16(x) ((x) * 0x0001000100010001ull) + +#define MAX_INLINE 16 + +static inline void check_size_s(uint32_t opsz, uint32_t clsz) +{ + tcg_debug_assert(opsz % 8 == 0); + tcg_debug_assert(clsz % 8 == 0); + tcg_debug_assert(opsz <= clsz); +} + +static inline void check_align_s_3(uint32_t dofs, uint32_t aofs, uint32_t bofs) +{ + tcg_debug_assert(dofs % 8 == 0); + tcg_debug_assert(aofs % 8 == 0); + tcg_debug_assert(bofs % 8 == 0); +} + +static inline void check_size_l(uint32_t opsz, uint32_t clsz) +{ + tcg_debug_assert(opsz % 16 == 0); + tcg_debug_assert(clsz % 16 == 0); + tcg_debug_assert(opsz <= clsz); +} + +static inline void check_align_l_3(uint32_t dofs, uint32_t aofs, uint32_t bofs) +{ + tcg_debug_assert(dofs % 16 == 0); + tcg_debug_assert(aofs % 16 == 0); + tcg_debug_assert(bofs % 16 == 0); +} + +static inline void check_overlap_3(uint32_t d, uint32_t a, + uint32_t b, uint32_t s) +{ + tcg_debug_assert(d == a || d + s <= a || a + s <= d); + tcg_debug_assert(d == b || d + s <= b || b + s <= d); + tcg_debug_assert(a == b || a + s <= b || b + s <= a); +} + +static void expand_clr(uint32_t dofs, uint32_t opsz, uint32_t clsz) +{ + if (clsz > opsz) { + TCGv_i64 zero = tcg_const_i64(0); + uint32_t i; + + for (i = opsz; i < clsz; i += 8) { + tcg_gen_st_i64(zero, tcg_ctx.tcg_env, dofs + i); + } + tcg_temp_free_i64(zero); + } +} + +static TCGv_i32 make_desc(uint32_t opsz, uint32_t clsz) +{ + tcg_debug_assert(opsz >= 16 && opsz <= 255 * 16 && opsz % 16 == 0); + tcg_debug_assert(clsz >= 16 && clsz <= 255 * 16 && clsz % 16 == 0); + opsz /= 16; + clsz /= 16; + opsz -= 1; + clsz -= 1; + return tcg_const_i32(deposit32(opsz, 8, 8, clsz)); +} + +static void expand_3_o(uint32_t dofs, uint32_t aofs, uint32_t bofs, + uint32_t opsz, uint32_t clsz, + void (*fno)(TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_i32)) +{ + TCGv_ptr d = tcg_temp_new_ptr(); + TCGv_ptr a = tcg_temp_new_ptr(); + TCGv_ptr b = tcg_temp_new_ptr(); + TCGv_i32 desc = make_desc(opsz, clsz); + + tcg_gen_addi_ptr(d, tcg_ctx.tcg_env, dofs); + tcg_gen_addi_ptr(a, tcg_ctx.tcg_env, aofs); + tcg_gen_addi_ptr(b, tcg_ctx.tcg_env, bofs); + fno(d, a, b, desc); + + tcg_temp_free_ptr(d); + tcg_temp_free_ptr(a); + tcg_temp_free_ptr(b); + tcg_temp_free_i32(desc); +} + +static void expand_3x4(uint32_t dofs, uint32_t aofs, + uint32_t bofs, uint32_t opsz, + void (*fni)(TCGv_i32, TCGv_i32, TCGv_i32)) +{ + TCGv_i32 t0 = tcg_temp_new_i32(); + uint32_t i; + + if (aofs == bofs) { + for (i = 0; i < opsz; i += 4) { + tcg_gen_ld_i32(t0, tcg_ctx.tcg_env, aofs + i); + fni(t0, t0, t0); + tcg_gen_st_i32(t0, tcg_ctx.tcg_env, dofs + i); + } + } else { + TCGv_i32 t1 = tcg_temp_new_i32(); + for (i = 0; i < opsz; i += 4) { + tcg_gen_ld_i32(t0, tcg_ctx.tcg_env, aofs + i); + tcg_gen_ld_i32(t1, tcg_ctx.tcg_env, bofs + i); + fni(t0, t0, t1); + tcg_gen_st_i32(t0, tcg_ctx.tcg_env, dofs + i); + } + tcg_temp_free_i32(t1); + } + tcg_temp_free_i32(t0); +} + +static void expand_3x8(uint32_t dofs, uint32_t aofs, + uint32_t bofs, uint32_t opsz, + void (*fni)(TCGv_i64, TCGv_i64, TCGv_i64)) +{ + TCGv_i64 t0 = tcg_temp_new_i64(); + uint32_t i; + + if (aofs == bofs) { + for (i = 0; i < opsz; i += 8) { + tcg_gen_ld_i64(t0, tcg_ctx.tcg_env, aofs + i); + fni(t0, t0, t0); + tcg_gen_st_i64(t0, tcg_ctx.tcg_env, dofs + i); + } + } else { + TCGv_i64 t1 = tcg_temp_new_i64(); + for (i = 0; i < opsz; i += 8) { + tcg_gen_ld_i64(t0, tcg_ctx.tcg_env, aofs + i); + tcg_gen_ld_i64(t1, tcg_ctx.tcg_env, bofs + i); + fni(t0, t0, t1); + tcg_gen_st_i64(t0, tcg_ctx.tcg_env, dofs + i); + } + tcg_temp_free_i64(t1); + } + tcg_temp_free_i64(t0); +} + +static void expand_3x8p1(uint32_t dofs, uint32_t aofs, uint32_t bofs, + uint32_t opsz, uint64_t data, + void (*fni)(TCGv_i64, TCGv_i64, TCGv_i64, TCGv_i64)) +{ + TCGv_i64 t0 = tcg_temp_new_i64(); + TCGv_i64 t2 = tcg_const_i64(data); + uint32_t i; + + if (aofs == bofs) { + for (i = 0; i < opsz; i += 8) { + tcg_gen_ld_i64(t0, tcg_ctx.tcg_env, aofs + i); + fni(t0, t0, t0, t2); + tcg_gen_st_i64(t0, tcg_ctx.tcg_env, dofs + i); + } + } else { + TCGv_i64 t1 = tcg_temp_new_i64(); + for (i = 0; i < opsz; i += 8) { + tcg_gen_ld_i64(t0, tcg_ctx.tcg_env, aofs + i); + tcg_gen_ld_i64(t1, tcg_ctx.tcg_env, bofs + i); + fni(t0, t0, t1, t2); + tcg_gen_st_i64(t0, tcg_ctx.tcg_env, dofs + i); + } + tcg_temp_free_i64(t1); + } + tcg_temp_free_i64(t0); + tcg_temp_free_i64(t2); +} + +void tcg_gen_gvec_3(uint32_t dofs, uint32_t aofs, uint32_t bofs, + uint32_t opsz, uint32_t clsz, const GVecGen3 *g) +{ + check_overlap_3(dofs, aofs, bofs, clsz); + if (opsz <= MAX_INLINE) { + check_size_s(opsz, clsz); + check_align_s_3(dofs, aofs, bofs); + if (g->fni8) { + expand_3x8(dofs, aofs, bofs, opsz, g->fni8); + } else if (g->fni4) { + expand_3x4(dofs, aofs, bofs, opsz, g->fni4); + } else if (g->fni8x) { + expand_3x8p1(dofs, aofs, bofs, opsz, g->extra_value, g->fni8x); + } else { + g_assert_not_reached(); + } + expand_clr(dofs, opsz, clsz); + } else { + check_size_l(opsz, clsz); + check_align_l_3(dofs, aofs, bofs); + expand_3_o(dofs, aofs, bofs, opsz, clsz, g->fno); + } +} + +static void gen_addv_mask(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b, TCGv_i64 m) +{ + TCGv_i64 t1 = tcg_temp_new_i64(); + TCGv_i64 t2 = tcg_temp_new_i64(); + TCGv_i64 t3 = tcg_temp_new_i64(); + + tcg_gen_andc_i64(t1, a, m); + tcg_gen_andc_i64(t2, b, m); + tcg_gen_xor_i64(t3, a, b); + tcg_gen_add_i64(d, t1, t2); + tcg_gen_and_i64(t3, t3, m); + tcg_gen_xor_i64(d, d, t3); + + tcg_temp_free_i64(t1); + tcg_temp_free_i64(t2); + tcg_temp_free_i64(t3); +} + +void tcg_gen_gvec_add8(uint32_t dofs, uint32_t aofs, uint32_t bofs, + uint32_t opsz, uint32_t clsz) +{ + static const GVecGen3 g = { + .extra_value = REP8(0x80), + .fni8x = gen_addv_mask, + .fno = gen_helper_gvec_add8, + }; + tcg_gen_gvec_3(dofs, aofs, bofs, opsz, clsz, &g); +} + +void tcg_gen_gvec_add16(uint32_t dofs, uint32_t aofs, uint32_t bofs, + uint32_t opsz, uint32_t clsz) +{ + static const GVecGen3 g = { + .extra_value = REP16(0x8000), + .fni8x = gen_addv_mask, + .fno = gen_helper_gvec_add16, + }; + tcg_gen_gvec_3(dofs, aofs, bofs, opsz, clsz, &g); +} + +void tcg_gen_gvec_add32(uint32_t dofs, uint32_t aofs, uint32_t bofs, + uint32_t opsz, uint32_t clsz) +{ + static const GVecGen3 g = { + .fni4 = tcg_gen_add_i32, + .fno = gen_helper_gvec_add32, + }; + tcg_gen_gvec_3(dofs, aofs, bofs, opsz, clsz, &g); +} + +void tcg_gen_gvec_add64(uint32_t dofs, uint32_t aofs, uint32_t bofs, + uint32_t opsz, uint32_t clsz) +{ + static const GVecGen3 g = { + .fni8 = tcg_gen_add_i64, + .fno = gen_helper_gvec_add64, + }; + tcg_gen_gvec_3(dofs, aofs, bofs, opsz, clsz, &g); +} + +void tcg_gen_vec8_add8(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b) +{ + TCGv_i64 m = tcg_const_i64(REP8(0x80)); + gen_addv_mask(d, a, b, m); + tcg_temp_free_i64(m); +} + +void tcg_gen_vec8_add16(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b) +{ + TCGv_i64 m = tcg_const_i64(REP16(0x8000)); + gen_addv_mask(d, a, b, m); + tcg_temp_free_i64(m); +} + +void tcg_gen_vec8_add32(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b) +{ + TCGv_i64 t1 = tcg_temp_new_i64(); + TCGv_i64 t2 = tcg_temp_new_i64(); + + tcg_gen_andi_i64(t1, a, ~0xffffffffull); + tcg_gen_add_i64(t2, a, b); + tcg_gen_add_i64(t1, t1, b); + tcg_gen_deposit_i64(d, t1, t2, 0, 32); + + tcg_temp_free_i64(t1); + tcg_temp_free_i64(t2); +} + +static void gen_subv_mask(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b, TCGv_i64 m) +{ + TCGv_i64 t1 = tcg_temp_new_i64(); + TCGv_i64 t2 = tcg_temp_new_i64(); + TCGv_i64 t3 = tcg_temp_new_i64(); + + tcg_gen_or_i64(t1, a, m); + tcg_gen_andc_i64(t2, b, m); + tcg_gen_eqv_i64(t3, a, b); + tcg_gen_sub_i64(d, t1, t2); + tcg_gen_and_i64(t3, t3, m); + tcg_gen_xor_i64(d, d, t3); + + tcg_temp_free_i64(t1); + tcg_temp_free_i64(t2); + tcg_temp_free_i64(t3); +} + +void tcg_gen_gvec_sub8(uint32_t dofs, uint32_t aofs, uint32_t bofs, + uint32_t opsz, uint32_t clsz) +{ + static const GVecGen3 g = { + .extra_value = REP8(0x80), + .fni8x = gen_subv_mask, + .fno = gen_helper_gvec_sub8, + }; + tcg_gen_gvec_3(dofs, aofs, bofs, opsz, clsz, &g); +} + +void tcg_gen_gvec_sub16(uint32_t dofs, uint32_t aofs, uint32_t bofs, + uint32_t opsz, uint32_t clsz) +{ + static const GVecGen3 g = { + .extra_value = REP16(0x8000), + .fni8x = gen_subv_mask, + .fno = gen_helper_gvec_sub16, + }; + tcg_gen_gvec_3(dofs, aofs, bofs, opsz, clsz, &g); +} + +void tcg_gen_gvec_sub32(uint32_t dofs, uint32_t aofs, uint32_t bofs, + uint32_t opsz, uint32_t clsz) +{ + static const GVecGen3 g = { + .fni4 = tcg_gen_sub_i32, + .fno = gen_helper_gvec_sub32, + }; + tcg_gen_gvec_3(dofs, aofs, bofs, opsz, clsz, &g); +} + +void tcg_gen_gvec_sub64(uint32_t dofs, uint32_t aofs, uint32_t bofs, + uint32_t opsz, uint32_t clsz) +{ + static const GVecGen3 g = { + .fni8 = tcg_gen_sub_i64, + .fno = gen_helper_gvec_sub64, + }; + tcg_gen_gvec_3(dofs, aofs, bofs, opsz, clsz, &g); +} + +void tcg_gen_vec8_sub8(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b) +{ + TCGv_i64 m = tcg_const_i64(REP8(0x80)); + gen_subv_mask(d, a, b, m); + tcg_temp_free_i64(m); +} + +void tcg_gen_vec8_sub16(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b) +{ + TCGv_i64 m = tcg_const_i64(REP16(0x8000)); + gen_subv_mask(d, a, b, m); + tcg_temp_free_i64(m); +} + +void tcg_gen_vec8_sub32(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b) +{ + TCGv_i64 t1 = tcg_temp_new_i64(); + TCGv_i64 t2 = tcg_temp_new_i64(); + + tcg_gen_andi_i64(t1, b, ~0xffffffffull); + tcg_gen_sub_i64(t2, a, b); + tcg_gen_sub_i64(t1, a, t1); + tcg_gen_deposit_i64(d, t1, t2, 0, 32); + + tcg_temp_free_i64(t1); + tcg_temp_free_i64(t2); +} + +void tcg_gen_gvec_and8(uint32_t dofs, uint32_t aofs, uint32_t bofs, + uint32_t opsz, uint32_t clsz) +{ + static const GVecGen3 g = { + .fni8 = tcg_gen_and_i64, + .fno = gen_helper_gvec_and8, + }; + tcg_gen_gvec_3(dofs, aofs, bofs, opsz, clsz, &g); +} + +void tcg_gen_gvec_or8(uint32_t dofs, uint32_t aofs, uint32_t bofs, + uint32_t opsz, uint32_t clsz) +{ + static const GVecGen3 g = { + .fni8 = tcg_gen_or_i64, + .fno = gen_helper_gvec_or8, + }; + tcg_gen_gvec_3(dofs, aofs, bofs, opsz, clsz, &g); +} + +void tcg_gen_gvec_xor8(uint32_t dofs, uint32_t aofs, uint32_t bofs, + uint32_t opsz, uint32_t clsz) +{ + static const GVecGen3 g = { + .fni8 = tcg_gen_xor_i64, + .fno = gen_helper_gvec_xor8, + }; + tcg_gen_gvec_3(dofs, aofs, bofs, opsz, clsz, &g); +} + +void tcg_gen_gvec_andc8(uint32_t dofs, uint32_t aofs, uint32_t bofs, + uint32_t opsz, uint32_t clsz) +{ + static const GVecGen3 g = { + .fni8 = tcg_gen_andc_i64, + .fno = gen_helper_gvec_andc8, + }; + tcg_gen_gvec_3(dofs, aofs, bofs, opsz, clsz, &g); +} + +void tcg_gen_gvec_orc8(uint32_t dofs, uint32_t aofs, uint32_t bofs, + uint32_t opsz, uint32_t clsz) +{ + static const GVecGen3 g = { + .fni8 = tcg_gen_orc_i64, + .fno = gen_helper_gvec_orc8, + }; + tcg_gen_gvec_3(dofs, aofs, bofs, opsz, clsz, &g); +} diff --git a/tcg/tcg-runtime-gvec.c b/tcg/tcg-runtime-gvec.c new file mode 100644 index 0000000000..9a37ce07a2 --- /dev/null +++ b/tcg/tcg-runtime-gvec.c @@ -0,0 +1,199 @@ +/* + * Generic vectorized operation runtime + * + * Copyright (c) 2017 Linaro + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, see . + */ + +#include "qemu/osdep.h" +#include "qemu/host-utils.h" +#include "cpu.h" +#include "exec/helper-proto.h" + +/* Virtually all hosts support 16-byte vectors. Those that don't + can emulate them via GCC's generic vector extension. + + In tcg-op-gvec.c, we asserted that both the size and alignment + of the data are multiples of 16. */ + +typedef uint8_t vec8 __attribute__((vector_size(16))); +typedef uint16_t vec16 __attribute__((vector_size(16))); +typedef uint32_t vec32 __attribute__((vector_size(16))); +typedef uint64_t vec64 __attribute__((vector_size(16))); + +static inline intptr_t extract_opsz(uint32_t desc) +{ + return ((desc & 0xff) + 1) * 16; +} + +static inline intptr_t extract_clsz(uint32_t desc) +{ + return (((desc >> 8) & 0xff) + 1) * 16; +} + +static inline void clear_high(void *d, intptr_t opsz, uint32_t desc) +{ + intptr_t clsz = extract_clsz(desc); + intptr_t i; + + if (unlikely(clsz > opsz)) { + for (i = opsz; i < clsz; i += sizeof(vec64)) { + *(vec64 *)(d + i) = (vec64){ 0 }; + } + } +} + +void HELPER(gvec_add8)(void *d, void *a, void *b, uint32_t desc) +{ + intptr_t opsz = extract_opsz(desc); + intptr_t i; + + for (i = 0; i < opsz; i += sizeof(vec8)) { + *(vec8 *)(d + i) = *(vec8 *)(a + i) + *(vec8 *)(b + i); + } + clear_high(d, opsz, desc); +} + +void HELPER(gvec_add16)(void *d, void *a, void *b, uint32_t desc) +{ + intptr_t opsz = extract_opsz(desc); + intptr_t i; + + for (i = 0; i < opsz; i += sizeof(vec16)) { + *(vec16 *)(d + i) = *(vec16 *)(a + i) + *(vec16 *)(b + i); + } + clear_high(d, opsz, desc); +} + +void HELPER(gvec_add32)(void *d, void *a, void *b, uint32_t desc) +{ + intptr_t opsz = extract_opsz(desc); + intptr_t i; + + for (i = 0; i < opsz; i += sizeof(vec32)) { + *(vec32 *)(d + i) = *(vec32 *)(a + i) + *(vec32 *)(b + i); + } + clear_high(d, opsz, desc); +} + +void HELPER(gvec_add64)(void *d, void *a, void *b, uint32_t desc) +{ + intptr_t opsz = extract_opsz(desc); + intptr_t i; + + for (i = 0; i < opsz; i += sizeof(vec64)) { + *(vec64 *)(d + i) = *(vec64 *)(a + i) + *(vec64 *)(b + i); + } + clear_high(d, opsz, desc); +} + +void HELPER(gvec_sub8)(void *d, void *a, void *b, uint32_t desc) +{ + intptr_t opsz = extract_opsz(desc); + intptr_t i; + + for (i = 0; i < opsz; i += sizeof(vec8)) { + *(vec8 *)(d + i) = *(vec8 *)(a + i) - *(vec8 *)(b + i); + } + clear_high(d, opsz, desc); +} + +void HELPER(gvec_sub16)(void *d, void *a, void *b, uint32_t desc) +{ + intptr_t opsz = extract_opsz(desc); + intptr_t i; + + for (i = 0; i < opsz; i += sizeof(vec16)) { + *(vec16 *)(d + i) = *(vec16 *)(a + i) - *(vec16 *)(b + i); + } + clear_high(d, opsz, desc); +} + +void HELPER(gvec_sub32)(void *d, void *a, void *b, uint32_t desc) +{ + intptr_t opsz = extract_opsz(desc); + intptr_t i; + + for (i = 0; i < opsz; i += sizeof(vec32)) { + *(vec32 *)(d + i) = *(vec32 *)(a + i) - *(vec32 *)(b + i); + } + clear_high(d, opsz, desc); +} + +void HELPER(gvec_sub64)(void *d, void *a, void *b, uint32_t desc) +{ + intptr_t opsz = extract_opsz(desc); + intptr_t i; + + for (i = 0; i < opsz; i += sizeof(vec64)) { + *(vec64 *)(d + i) = *(vec64 *)(a + i) - *(vec64 *)(b + i); + } + clear_high(d, opsz, desc); +} + +void HELPER(gvec_and8)(void *d, void *a, void *b, uint32_t desc) +{ + intptr_t opsz = extract_opsz(desc); + intptr_t i; + + for (i = 0; i < opsz; i += sizeof(vec64)) { + *(vec64 *)(d + i) = *(vec64 *)(a + i) & *(vec64 *)(b + i); + } + clear_high(d, opsz, desc); +} + +void HELPER(gvec_or8)(void *d, void *a, void *b, uint32_t desc) +{ + intptr_t opsz = extract_opsz(desc); + intptr_t i; + + for (i = 0; i < opsz; i += sizeof(vec64)) { + *(vec64 *)(d + i) = *(vec64 *)(a + i) | *(vec64 *)(b + i); + } + clear_high(d, opsz, desc); +} + +void HELPER(gvec_xor8)(void *d, void *a, void *b, uint32_t desc) +{ + intptr_t opsz = extract_opsz(desc); + intptr_t i; + + for (i = 0; i < opsz; i += sizeof(vec64)) { + *(vec64 *)(d + i) = *(vec64 *)(a + i) ^ *(vec64 *)(b + i); + } + clear_high(d, opsz, desc); +} + +void HELPER(gvec_andc8)(void *d, void *a, void *b, uint32_t desc) +{ + intptr_t opsz = extract_opsz(desc); + intptr_t i; + + for (i = 0; i < opsz; i += sizeof(vec64)) { + *(vec64 *)(d + i) = *(vec64 *)(a + i) &~ *(vec64 *)(b + i); + } + clear_high(d, opsz, desc); +} + +void HELPER(gvec_orc8)(void *d, void *a, void *b, uint32_t desc) +{ + intptr_t opsz = extract_opsz(desc); + intptr_t i; + + for (i = 0; i < opsz; i += sizeof(vec64)) { + *(vec64 *)(d + i) = *(vec64 *)(a + i) |~ *(vec64 *)(b + i); + } + clear_high(d, opsz, desc); +} -- 2.13.5 From MAILER-DAEMON Thu Aug 17 19:01:33 2017 Received: from list by lists.gnu.org with archive (Exim 4.71) id 1diTnB-000522-5E for mharc-qemu-arm@gnu.org; Thu, 17 Aug 2017 19:01:33 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:44490) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1diTn2-0004tu-Ki for qemu-arm@nongnu.org; Thu, 17 Aug 2017 19:01:25 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1diTn1-0000rf-Ev for qemu-arm@nongnu.org; Thu, 17 Aug 2017 19:01:24 -0400 Received: from mail-pg0-x234.google.com ([2607:f8b0:400e:c05::234]:36961) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1diTn1-0000qo-77 for qemu-arm@nongnu.org; Thu, 17 Aug 2017 19:01:23 -0400 Received: by mail-pg0-x234.google.com with SMTP id y129so51925122pgy.4 for ; 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[97.126.108.236]) by smtp.gmail.com with ESMTPSA id c23sm5190043pfc.136.2017.08.17.16.01.20 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 17 Aug 2017 16:01:21 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, alex.bennee@linaro.org Date: Thu, 17 Aug 2017 16:01:10 -0700 Message-Id: <20170817230114.3655-5-richard.henderson@linaro.org> X-Mailer: git-send-email 2.13.5 In-Reply-To: <20170817230114.3655-1-richard.henderson@linaro.org> References: <20170817230114.3655-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::234 Subject: [Qemu-arm] [PATCH 4/8] tcg: Add operations for host vectors X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 17 Aug 2017 23:01:26 -0000 Nothing uses or implements them yet. Signed-off-by: Richard Henderson --- tcg/tcg-opc.h | 89 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ tcg/tcg.h | 24 ++++++++++++++++ 2 files changed, 113 insertions(+) diff --git a/tcg/tcg-opc.h b/tcg/tcg-opc.h index 956fb1e9f3..9162125fac 100644 --- a/tcg/tcg-opc.h +++ b/tcg/tcg-opc.h @@ -206,6 +206,95 @@ DEF(qemu_st_i64, 0, TLADDR_ARGS + DATA64_ARGS, 1, #undef TLADDR_ARGS #undef DATA64_ARGS + +/* Host integer vector operations. */ +/* These opcodes are required whenever the base vector size is enabled. */ + +DEF(mov_v64, 1, 1, 0, IMPL(TCG_TARGET_HAS_v64)) +DEF(mov_v128, 1, 1, 0, IMPL(TCG_TARGET_HAS_v128)) +DEF(mov_v256, 1, 1, 0, IMPL(TCG_TARGET_HAS_v256)) + +DEF(movi_v64, 1, 0, 1, IMPL(TCG_TARGET_HAS_v64)) +DEF(movi_v128, 1, 0, 1, IMPL(TCG_TARGET_HAS_v128)) +DEF(movi_v256, 1, 0, 1, IMPL(TCG_TARGET_HAS_v256)) + +DEF(ld_v64, 1, 1, 1, IMPL(TCG_TARGET_HAS_v64)) +DEF(ld_v128, 1, 1, 1, IMPL(TCG_TARGET_HAS_v128)) +DEF(ld_v256, 1, 1, 1, IMPL(TCG_TARGET_HAS_v256)) + +DEF(st_v64, 0, 2, 1, IMPL(TCG_TARGET_HAS_v64)) +DEF(st_v128, 0, 2, 1, IMPL(TCG_TARGET_HAS_v128)) +DEF(st_v256, 0, 2, 1, IMPL(TCG_TARGET_HAS_v256)) + +DEF(and_v64, 1, 2, 0, IMPL(TCG_TARGET_HAS_v64)) +DEF(and_v128, 1, 2, 0, IMPL(TCG_TARGET_HAS_v128)) +DEF(and_v256, 1, 2, 0, IMPL(TCG_TARGET_HAS_v256)) + +DEF(or_v64, 1, 2, 0, IMPL(TCG_TARGET_HAS_v64)) +DEF(or_v128, 1, 2, 0, IMPL(TCG_TARGET_HAS_v128)) +DEF(or_v256, 1, 2, 0, IMPL(TCG_TARGET_HAS_v256)) + +DEF(xor_v64, 1, 2, 0, IMPL(TCG_TARGET_HAS_v64)) +DEF(xor_v128, 1, 2, 0, IMPL(TCG_TARGET_HAS_v128)) +DEF(xor_v256, 1, 2, 0, IMPL(TCG_TARGET_HAS_v256)) + +DEF(add8_v64, 1, 2, 0, IMPL(TCG_TARGET_HAS_v64)) +DEF(add16_v64, 1, 2, 0, IMPL(TCG_TARGET_HAS_v64)) +DEF(add32_v64, 1, 2, 0, IMPL(TCG_TARGET_HAS_v64)) + +DEF(add8_v128, 1, 2, 0, IMPL(TCG_TARGET_HAS_v128)) +DEF(add16_v128, 1, 2, 0, IMPL(TCG_TARGET_HAS_v128)) +DEF(add32_v128, 1, 2, 0, IMPL(TCG_TARGET_HAS_v128)) +DEF(add64_v128, 1, 2, 0, IMPL(TCG_TARGET_HAS_v128)) + +DEF(add8_v256, 1, 2, 0, IMPL(TCG_TARGET_HAS_v256)) +DEF(add16_v256, 1, 2, 0, IMPL(TCG_TARGET_HAS_v256)) +DEF(add32_v256, 1, 2, 0, IMPL(TCG_TARGET_HAS_v256)) +DEF(add64_v256, 1, 2, 0, IMPL(TCG_TARGET_HAS_v256)) + +DEF(sub8_v64, 1, 2, 0, IMPL(TCG_TARGET_HAS_v64)) +DEF(sub16_v64, 1, 2, 0, IMPL(TCG_TARGET_HAS_v64)) +DEF(sub32_v64, 1, 2, 0, IMPL(TCG_TARGET_HAS_v64)) + +DEF(sub8_v128, 1, 2, 0, IMPL(TCG_TARGET_HAS_v128)) +DEF(sub16_v128, 1, 2, 0, IMPL(TCG_TARGET_HAS_v128)) +DEF(sub32_v128, 1, 2, 0, IMPL(TCG_TARGET_HAS_v128)) +DEF(sub64_v128, 1, 2, 0, IMPL(TCG_TARGET_HAS_v128)) + +DEF(sub8_v256, 1, 2, 0, IMPL(TCG_TARGET_HAS_v256)) +DEF(sub16_v256, 1, 2, 0, IMPL(TCG_TARGET_HAS_v256)) +DEF(sub32_v256, 1, 2, 0, IMPL(TCG_TARGET_HAS_v256)) +DEF(sub64_v256, 1, 2, 0, IMPL(TCG_TARGET_HAS_v256)) + +/* These opcodes are optional. + All element counts must be supported if any are. */ + +DEF(not_v64, 1, 1, 0, IMPL(TCG_TARGET_HAS_not_v64)) +DEF(not_v128, 1, 1, 0, IMPL(TCG_TARGET_HAS_not_v128)) +DEF(not_v256, 1, 1, 0, IMPL(TCG_TARGET_HAS_not_v256)) + +DEF(andc_v64, 1, 2, 0, IMPL(TCG_TARGET_HAS_andc_v64)) +DEF(andc_v128, 1, 2, 0, IMPL(TCG_TARGET_HAS_andc_v128)) +DEF(andc_v256, 1, 2, 0, IMPL(TCG_TARGET_HAS_andc_v256)) + +DEF(orc_v64, 1, 2, 0, IMPL(TCG_TARGET_HAS_orc_v64)) +DEF(orc_v128, 1, 2, 0, IMPL(TCG_TARGET_HAS_orc_v128)) +DEF(orc_v256, 1, 2, 0, IMPL(TCG_TARGET_HAS_orc_v256)) + +DEF(neg8_v64, 1, 1, 0, IMPL(TCG_TARGET_HAS_neg_v64)) +DEF(neg16_v64, 1, 1, 0, IMPL(TCG_TARGET_HAS_neg_v64)) +DEF(neg32_v64, 1, 1, 0, IMPL(TCG_TARGET_HAS_neg_v64)) + +DEF(neg8_v128, 1, 1, 0, IMPL(TCG_TARGET_HAS_neg_v128)) +DEF(neg16_v128, 1, 1, 0, IMPL(TCG_TARGET_HAS_neg_v128)) +DEF(neg32_v128, 1, 1, 0, IMPL(TCG_TARGET_HAS_neg_v128)) +DEF(neg64_v128, 1, 1, 0, IMPL(TCG_TARGET_HAS_neg_v128)) + +DEF(neg8_v256, 1, 1, 0, IMPL(TCG_TARGET_HAS_neg_v256)) +DEF(neg16_v256, 1, 1, 0, IMPL(TCG_TARGET_HAS_neg_v256)) +DEF(neg32_v256, 1, 1, 0, IMPL(TCG_TARGET_HAS_neg_v256)) +DEF(neg64_v256, 1, 1, 0, IMPL(TCG_TARGET_HAS_neg_v256)) + #undef IMPL #undef IMPL64 #undef DEF diff --git a/tcg/tcg.h b/tcg/tcg.h index 1277caed3d..b9e15da13b 100644 --- a/tcg/tcg.h +++ b/tcg/tcg.h @@ -166,6 +166,30 @@ typedef uint64_t TCGRegSet; #define TCG_TARGET_HAS_rem_i64 0 #endif +#ifndef TCG_TARGET_HAS_v64 +#define TCG_TARGET_HAS_v64 0 +#define TCG_TARGET_HAS_andc_v64 0 +#define TCG_TARGET_HAS_orc_v64 0 +#define TCG_TARGET_HAS_not_v64 0 +#define TCG_TARGET_HAS_neg_v64 0 +#endif + +#ifndef TCG_TARGET_HAS_v128 +#define TCG_TARGET_HAS_v128 0 +#define TCG_TARGET_HAS_andc_v128 0 +#define TCG_TARGET_HAS_orc_v128 0 +#define TCG_TARGET_HAS_not_v128 0 +#define TCG_TARGET_HAS_neg_v128 0 +#endif + +#ifndef TCG_TARGET_HAS_v256 +#define TCG_TARGET_HAS_v256 0 +#define TCG_TARGET_HAS_andc_v256 0 +#define TCG_TARGET_HAS_orc_v256 0 +#define TCG_TARGET_HAS_not_v256 0 +#define TCG_TARGET_HAS_neg_v256 0 +#endif + /* For 32-bit targets, some sort of unsigned widening multiply is required. */ #if TCG_TARGET_REG_BITS == 32 \ && !(defined(TCG_TARGET_HAS_mulu2_i32) \ -- 2.13.5 From MAILER-DAEMON Thu Aug 17 19:01:25 2017 Received: from list by lists.gnu.org with archive (Exim 4.71) id 1diTn3-0004uS-6B for mharc-qemu-arm@gnu.org; Thu, 17 Aug 2017 19:01:25 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:44453) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1diTn0-0004sU-B1 for qemu-arm@nongnu.org; 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[97.126.108.236]) by smtp.gmail.com with ESMTPSA id c23sm5190043pfc.136.2017.08.17.16.01.15 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 17 Aug 2017 16:01:15 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, alex.bennee@linaro.org Date: Thu, 17 Aug 2017 16:01:06 -0700 Message-Id: <20170817230114.3655-1-richard.henderson@linaro.org> X-Mailer: git-send-email 2.13.5 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::233 Subject: [Qemu-arm] [PATCH 0/8] TCG vectorization and example conversion X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 17 Aug 2017 23:01:24 -0000 When Alex and I started talking about this topic, this is the direction I was thinking. The primary difference from Alex's version is that the interface on the target/cpu/ side uses offsets and not a faux temp. The secondary difference is that, for smaller vector sizes at least, I will expand to inline host vector operations. The use of explicit offsets aids that. There are a number of things that are missing in the host vector support, including register spill/fill. But in this example conversion we will never have more than 2 vector registers live at any point, and so we do not run across those issues. Some of this infrastructure cannot be exercised with existing front-ends. It will require support for ARM SVE to be written to get there. Or to add support for AVX2/AVX512 within target/i386. ;-) Unfortunately, the built-in disassembler is too old to handle AVX. So for testing purposes I disabled the built-in disas so that I could run the output assembly through an external objdump. For a trivial test case via aarch64-linux-user: IN: 0x0000000000400078: 4e208400 add v0.16b, v0.16b, v0.16b 0x000000000040007c: 4e648462 add v2.8h, v3.8h, v4.8h 0x0000000000400080: 4ea48462 add v2.4s, v3.4s, v4.4s 0x0000000000400084: 4ee48462 add v2.2d, v3.2d, v4.2d 0x0000000000400088: 0ea28462 add v2.2s, v3.2s, v2.2s 0x000000000040008c: 00000000 unallocated (Unallocated) OP after optimization and liveness analysis: ld_i32 tmp0,env,$0xffffffffffffffec dead: 1 movi_i32 tmp1,$0x0 brcond_i32 tmp0,tmp1,lt,$L0 dead: 0 1 ---- 0000000000400078 0000000000000000 0000000000000000 ld_v128 tmp2,env,$0x850 add8_v128 tmp2,tmp2,tmp2 dead: 1 2 st_v128 tmp2,env,$0x850 dead: 0 ---- 000000000040007c 0000000000000000 0000000000000000 ld_v128 tmp2,env,$0x880 ld_v128 tmp3,env,$0x890 add16_v128 tmp2,tmp2,tmp3 dead: 1 2 st_v128 tmp2,env,$0x870 dead: 0 ---- 0000000000400080 0000000000000000 0000000000000000 ld_v128 tmp2,env,$0x880 ld_v128 tmp3,env,$0x890 add32_v128 tmp2,tmp2,tmp3 dead: 1 2 st_v128 tmp2,env,$0x870 dead: 0 ---- 0000000000400084 0000000000000000 0000000000000000 ld_v128 tmp2,env,$0x880 ld_v128 tmp3,env,$0x890 add64_v128 tmp2,tmp2,tmp3 dead: 1 2 st_v128 tmp2,env,$0x870 dead: 0 ---- 0000000000400088 0000000000000000 0000000000000000 ld_v64 tmp4,env,$0x880 ld_v64 tmp5,env,$0x870 add32_v64 tmp4,tmp4,tmp5 dead: 1 2 st_v64 tmp4,env,$0x870 dead: 0 movi_i64 tmp6,$0x0 st_i64 tmp6,env,$0x878 dead: 0 ---- 000000000040008c 0000000000000000 0000000000000000 movi_i64 pc,$0x40008c sync: 0 dead: 0 movi_i32 tmp0,$0x1 movi_i32 tmp1,$0x2000000 movi_i32 tmp7,$0x1 call exception_with_syndrome,$0x0,$0,env,tmp0,tmp1,tmp7 dead: 0 1 2 3 set_label $L0 exit_tb $0x521c86683 OUT: [size=220] 521c86740: 41 8b 6e ec mov -0x14(%r14),%ebp 521c86744: 85 ed test %ebp,%ebp 521c86746: 0f 8c c4 00 00 00 jl 0x521c86810 521c8674c: c4 c1 7a 6f 86 50 08 00 00 vmovdqu 0x850(%r14),%xmm0 521c86755: c4 e1 79 fc c0 vpaddb %xmm0,%xmm0,%xmm0 521c8675a: c4 c1 7a 7f 86 50 08 00 00 vmovdqu %xmm0,0x850(%r14) 521c86763: c4 c1 7a 6f 86 80 08 00 00 vmovdqu 0x880(%r14),%xmm0 521c8676c: c4 c1 7a 6f 8e 90 08 00 00 vmovdqu 0x890(%r14),%xmm1 521c86775: c4 e1 79 fd c1 vpaddw %xmm1,%xmm0,%xmm0 521c8677a: c4 c1 7a 7f 86 70 08 00 00 vmovdqu %xmm0,0x870(%r14) 521c86783: c4 c1 7a 6f 86 80 08 00 00 vmovdqu 0x880(%r14),%xmm0 521c8678c: c4 c1 7a 6f 8e 90 08 00 00 vmovdqu 0x890(%r14),%xmm1 521c86795: c4 e1 79 fe c1 vpaddd %xmm1,%xmm0,%xmm0 521c8679a: c4 c1 7a 7f 86 70 08 00 00 vmovdqu %xmm0,0x870(%r14) 521c867a3: c4 c1 7a 6f 86 80 08 00 00 vmovdqu 0x880(%r14),%xmm0 521c867ac: c4 c1 7a 6f 8e 90 08 00 00 vmovdqu 0x890(%r14),%xmm1 521c867b5: c4 e1 79 d4 c1 vpaddq %xmm1,%xmm0,%xmm0 521c867ba: c4 c1 7a 7f 86 70 08 00 00 vmovdqu %xmm0,0x870(%r14) 521c867c3: c4 c1 7a 7e 86 80 08 00 00 vmovq 0x880(%r14),%xmm0 521c867cc: c4 c1 7a 7e 8e 70 08 00 00 vmovq 0x870(%r14),%xmm1 521c867d5: c4 e1 79 fe c1 vpaddd %xmm1,%xmm0,%xmm0 521c867da: c4 c1 79 d6 86 70 08 00 00 vmovq %xmm0,0x870(%r14) 521c867e3: 49 c7 86 78 08 00 00 movq $0x0,0x878(%r14) 521c867ea: 00 00 00 00 521c867ee: 49 c7 86 40 01 00 00 movq $0x40008c,0x140(%r14) 521c867f5: 8c 00 40 00 521c867f9: 49 8b fe mov %r14,%rdi 521c867fc: be 01 00 00 00 mov $0x1,%esi 521c86801: ba 00 00 00 02 mov $0x2000000,%edx 521c86806: b9 01 00 00 00 mov $0x1,%ecx 521c8680b: e8 90 40 c9 ff callq 0x52191a8a0 521c86810: 48 8d 05 6c fe ff ff lea -0x194(%rip),%rax 521c86817: e9 3c fe ff ff jmpq 0x521c86658 Because I already had some pending fixes to tcg/i386/ wrt VEX encoding, I've based this on an existing tree. The compete tree can be found at git://github.com/rth7680/qemu.git native-vector-registers-2 r~ Richard Henderson (8): tcg: Add generic vector infrastructure and ops for add/sub/logic target/arm: Use generic vector infrastructure for aa64 add/sub/logic tcg: Add types for host vectors tcg: Add operations for host vectors tcg: Add tcg_op_supported tcg: Add INDEX_op_invalid tcg: Expand target vector ops with host vector ops tcg/i386: Add vector operations Makefile.target | 5 +- tcg/i386/tcg-target.h | 46 +++- tcg/tcg-op-gvec.h | 92 +++++++ tcg/tcg-opc.h | 91 +++++++ tcg/tcg-runtime.h | 16 ++ tcg/tcg.h | 37 ++- target/arm/translate-a64.c | 137 +++++++---- tcg/i386/tcg-target.inc.c | 382 ++++++++++++++++++++++++++--- tcg/tcg-op-gvec.c | 583 +++++++++++++++++++++++++++++++++++++++++++++ tcg/tcg-runtime-gvec.c | 199 ++++++++++++++++ tcg/tcg.c | 323 ++++++++++++++++++++++++- 11 files changed, 1817 insertions(+), 94 deletions(-) create mode 100644 tcg/tcg-op-gvec.h create mode 100644 tcg/tcg-op-gvec.c create mode 100644 tcg/tcg-runtime-gvec.c -- 2.13.5 From MAILER-DAEMON Thu Aug 17 19:01:34 2017 Received: from list by lists.gnu.org with archive (Exim 4.71) id 1diTnC-00054I-Gj for mharc-qemu-arm@gnu.org; Thu, 17 Aug 2017 19:01:34 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:44535) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1diTn4-0004w8-D1 for qemu-arm@nongnu.org; Thu, 17 Aug 2017 19:01:27 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1diTn2-0000wO-TU for qemu-arm@nongnu.org; Thu, 17 Aug 2017 19:01:26 -0400 Received: from mail-pg0-x230.google.com ([2607:f8b0:400e:c05::230]:36553) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1diTn2-0000uB-LN for qemu-arm@nongnu.org; Thu, 17 Aug 2017 19:01:24 -0400 Received: by mail-pg0-x230.google.com with SMTP id i12so51987333pgr.3 for ; Thu, 17 Aug 2017 16:01:24 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=hIDrwc+oo2/OTeyFZIxY3GeNtfhOOi0JxoLuI/S8d1Q=; b=Y0Lsb3z60F7sB14wYzFrb59izB7AHueIXWhSfpjV9vCPDXmsE4WpCyRAZjpn7RjgFp s1cMHaKERonXYCCb5ZTfT+af5GVV+sVq4J6lOdYqrvLKAuLJxD69VdA3VwWgj9WkxFrU cQgOlf1XiQkd+YpwWxKsvz1/w4vvOwJ4YSNTw= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=hIDrwc+oo2/OTeyFZIxY3GeNtfhOOi0JxoLuI/S8d1Q=; b=kpHFIFBSHDY74rBHO/wDpqiKXhl+eT6moeHerjCm92THrbQRQYMzXCiKoJja4BEPQh UdWO0ouc/M9TmXj46W3A7R3mS6s0ICszAehlcCN9vYBBzudyZQDj42kVj2GEEBXC+bBD /xM1zTpd7amR2s8NA2FjYDYk3Mbe7vNtdU88B5Eu3vQMd1Xxxi6JyyLjg+Vka4dewKUk 05Qfzc/LlIxfPo97YWuXn+t52DvRXkUGnCtBErt5a+3ojH04Gl7k+gPY+SoJg6jZBnhy s+YuFE3VA4LfazS7+uZROgGkI6zfED4wsahbHMUtFOqMsT9kZEUrOcmpYIjZaOZPAdJ3 P/OQ== X-Gm-Message-State: AHYfb5ioWK9tPZ7SeiNPwuPTTgBsypHV6TgDEAMPDsGt+iGauyEEzXXx iNOSd8UnQRXns3LA X-Received: by 10.98.82.2 with SMTP id g2mr6749735pfb.308.1503010883573; Thu, 17 Aug 2017 16:01:23 -0700 (PDT) Received: from bigtime.twiddle.net (97-126-108-236.tukw.qwest.net. [97.126.108.236]) by smtp.gmail.com with ESMTPSA id c23sm5190043pfc.136.2017.08.17.16.01.22 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 17 Aug 2017 16:01:22 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, alex.bennee@linaro.org Date: Thu, 17 Aug 2017 16:01:11 -0700 Message-Id: <20170817230114.3655-6-richard.henderson@linaro.org> X-Mailer: git-send-email 2.13.5 In-Reply-To: <20170817230114.3655-1-richard.henderson@linaro.org> References: <20170817230114.3655-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::230 Subject: [Qemu-arm] [PATCH 5/8] tcg: Add tcg_op_supported X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 17 Aug 2017 23:01:28 -0000 Signed-off-by: Richard Henderson --- tcg/tcg.h | 2 + tcg/tcg.c | 310 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 312 insertions(+) diff --git a/tcg/tcg.h b/tcg/tcg.h index b9e15da13b..b443143b21 100644 --- a/tcg/tcg.h +++ b/tcg/tcg.h @@ -962,6 +962,8 @@ do {\ #define tcg_temp_free_ptr(T) tcg_temp_free_i64(TCGV_PTR_TO_NAT(T)) #endif +bool tcg_op_supported(TCGOpcode op); + void tcg_gen_callN(TCGContext *s, void *func, TCGArg ret, int nargs, TCGArg *args); diff --git a/tcg/tcg.c b/tcg/tcg.c index ea78d47fad..3c3cdda938 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -751,6 +751,316 @@ int tcg_check_temp_count(void) } #endif +/* Return true if OP may appear in the opcode stream. + Test the runtime variable that controls each opcode. */ +bool tcg_op_supported(TCGOpcode op) +{ + switch (op) { + case INDEX_op_discard: + case INDEX_op_set_label: + case INDEX_op_call: + case INDEX_op_br: + case INDEX_op_mb: + case INDEX_op_insn_start: + case INDEX_op_exit_tb: + case INDEX_op_goto_tb: + case INDEX_op_qemu_ld_i32: + case INDEX_op_qemu_st_i32: + case INDEX_op_qemu_ld_i64: + case INDEX_op_qemu_st_i64: + return true; + + case INDEX_op_goto_ptr: + return TCG_TARGET_HAS_goto_ptr; + + case INDEX_op_mov_i32: + case INDEX_op_movi_i32: + case INDEX_op_setcond_i32: + case INDEX_op_brcond_i32: + case INDEX_op_ld8u_i32: + case INDEX_op_ld8s_i32: + case INDEX_op_ld16u_i32: + case INDEX_op_ld16s_i32: + case INDEX_op_ld_i32: + case INDEX_op_st8_i32: + case INDEX_op_st16_i32: + case INDEX_op_st_i32: + case INDEX_op_add_i32: + case INDEX_op_sub_i32: + case INDEX_op_mul_i32: + case INDEX_op_and_i32: + case INDEX_op_or_i32: + case INDEX_op_xor_i32: + case INDEX_op_shl_i32: + case INDEX_op_shr_i32: + case INDEX_op_sar_i32: + return true; + + case INDEX_op_movcond_i32: + return TCG_TARGET_HAS_movcond_i32; + case INDEX_op_div_i32: + case INDEX_op_divu_i32: + return TCG_TARGET_HAS_div_i32; + case INDEX_op_rem_i32: + case INDEX_op_remu_i32: + return TCG_TARGET_HAS_rem_i32; + case INDEX_op_div2_i32: + case INDEX_op_divu2_i32: + return TCG_TARGET_HAS_div2_i32; + case INDEX_op_rotl_i32: + case INDEX_op_rotr_i32: + return TCG_TARGET_HAS_rot_i32; + case INDEX_op_deposit_i32: + return TCG_TARGET_HAS_deposit_i32; + case INDEX_op_extract_i32: + return TCG_TARGET_HAS_extract_i32; + case INDEX_op_sextract_i32: + return TCG_TARGET_HAS_sextract_i32; + case INDEX_op_add2_i32: + return TCG_TARGET_HAS_add2_i32; + case INDEX_op_sub2_i32: + return TCG_TARGET_HAS_sub2_i32; + case INDEX_op_mulu2_i32: + return TCG_TARGET_HAS_mulu2_i32; + case INDEX_op_muls2_i32: + return TCG_TARGET_HAS_muls2_i32; + case INDEX_op_muluh_i32: + return TCG_TARGET_HAS_muluh_i32; + case INDEX_op_mulsh_i32: + return TCG_TARGET_HAS_mulsh_i32; + case INDEX_op_ext8s_i32: + return TCG_TARGET_HAS_ext8s_i32; + case INDEX_op_ext16s_i32: + return TCG_TARGET_HAS_ext16s_i32; + case INDEX_op_ext8u_i32: + return TCG_TARGET_HAS_ext8u_i32; + case INDEX_op_ext16u_i32: + return TCG_TARGET_HAS_ext16u_i32; + case INDEX_op_bswap16_i32: + return TCG_TARGET_HAS_bswap16_i32; + case INDEX_op_bswap32_i32: + return TCG_TARGET_HAS_bswap32_i32; + case INDEX_op_not_i32: + return TCG_TARGET_HAS_not_i32; + case INDEX_op_neg_i32: + return TCG_TARGET_HAS_neg_i32; + case INDEX_op_andc_i32: + return TCG_TARGET_HAS_andc_i32; + case INDEX_op_orc_i32: + return TCG_TARGET_HAS_orc_i32; + case INDEX_op_eqv_i32: + return TCG_TARGET_HAS_eqv_i32; + case INDEX_op_nand_i32: + return TCG_TARGET_HAS_nand_i32; + case INDEX_op_nor_i32: + return TCG_TARGET_HAS_nor_i32; + case INDEX_op_clz_i32: + return TCG_TARGET_HAS_clz_i32; + case INDEX_op_ctz_i32: + return TCG_TARGET_HAS_ctz_i32; + case INDEX_op_ctpop_i32: + return TCG_TARGET_HAS_ctpop_i32; + + case INDEX_op_brcond2_i32: + case INDEX_op_setcond2_i32: + return TCG_TARGET_REG_BITS == 32; + + case INDEX_op_mov_i64: + case INDEX_op_movi_i64: + case INDEX_op_setcond_i64: + case INDEX_op_brcond_i64: + case INDEX_op_ld8u_i64: + case INDEX_op_ld8s_i64: + case INDEX_op_ld16u_i64: + case INDEX_op_ld16s_i64: + case INDEX_op_ld32u_i64: + case INDEX_op_ld32s_i64: + case INDEX_op_ld_i64: + case INDEX_op_st8_i64: + case INDEX_op_st16_i64: + case INDEX_op_st32_i64: + case INDEX_op_st_i64: + case INDEX_op_add_i64: + case INDEX_op_sub_i64: + case INDEX_op_mul_i64: + case INDEX_op_and_i64: + case INDEX_op_or_i64: + case INDEX_op_xor_i64: + case INDEX_op_shl_i64: + case INDEX_op_shr_i64: + case INDEX_op_sar_i64: + case INDEX_op_ext_i32_i64: + case INDEX_op_extu_i32_i64: + return TCG_TARGET_REG_BITS == 64; + + case INDEX_op_movcond_i64: + return TCG_TARGET_HAS_movcond_i64; + case INDEX_op_div_i64: + case INDEX_op_divu_i64: + return TCG_TARGET_HAS_div_i64; + case INDEX_op_rem_i64: + case INDEX_op_remu_i64: + return TCG_TARGET_HAS_rem_i64; + case INDEX_op_div2_i64: + case INDEX_op_divu2_i64: + return TCG_TARGET_HAS_div2_i64; + case INDEX_op_rotl_i64: + case INDEX_op_rotr_i64: + return TCG_TARGET_HAS_rot_i64; + case INDEX_op_deposit_i64: + return TCG_TARGET_HAS_deposit_i64; + case INDEX_op_extract_i64: + return TCG_TARGET_HAS_extract_i64; + case INDEX_op_sextract_i64: + return TCG_TARGET_HAS_sextract_i64; + case INDEX_op_extrl_i64_i32: + return TCG_TARGET_HAS_extrl_i64_i32; + case INDEX_op_extrh_i64_i32: + return TCG_TARGET_HAS_extrh_i64_i32; + case INDEX_op_ext8s_i64: + return TCG_TARGET_HAS_ext8s_i64; + case INDEX_op_ext16s_i64: + return TCG_TARGET_HAS_ext16s_i64; + case INDEX_op_ext32s_i64: + return TCG_TARGET_HAS_ext32s_i64; + case INDEX_op_ext8u_i64: + return TCG_TARGET_HAS_ext8u_i64; + case INDEX_op_ext16u_i64: + return TCG_TARGET_HAS_ext16u_i64; + case INDEX_op_ext32u_i64: + return TCG_TARGET_HAS_ext32u_i64; + case INDEX_op_bswap16_i64: + return TCG_TARGET_HAS_bswap16_i64; + case INDEX_op_bswap32_i64: + return TCG_TARGET_HAS_bswap32_i64; + case INDEX_op_bswap64_i64: + return TCG_TARGET_HAS_bswap64_i64; + case INDEX_op_not_i64: + return TCG_TARGET_HAS_not_i64; + case INDEX_op_neg_i64: + return TCG_TARGET_HAS_neg_i64; + case INDEX_op_andc_i64: + return TCG_TARGET_HAS_andc_i64; + case INDEX_op_orc_i64: + return TCG_TARGET_HAS_orc_i64; + case INDEX_op_eqv_i64: + return TCG_TARGET_HAS_eqv_i64; + case INDEX_op_nand_i64: + return TCG_TARGET_HAS_nand_i64; + case INDEX_op_nor_i64: + return TCG_TARGET_HAS_nor_i64; + case INDEX_op_clz_i64: + return TCG_TARGET_HAS_clz_i64; + case INDEX_op_ctz_i64: + return TCG_TARGET_HAS_ctz_i64; + case INDEX_op_ctpop_i64: + return TCG_TARGET_HAS_ctpop_i64; + case INDEX_op_add2_i64: + return TCG_TARGET_HAS_add2_i64; + case INDEX_op_sub2_i64: + return TCG_TARGET_HAS_sub2_i64; + case INDEX_op_mulu2_i64: + return TCG_TARGET_HAS_mulu2_i64; + case INDEX_op_muls2_i64: + return TCG_TARGET_HAS_muls2_i64; + case INDEX_op_muluh_i64: + return TCG_TARGET_HAS_muluh_i64; + case INDEX_op_mulsh_i64: + return TCG_TARGET_HAS_mulsh_i64; + + case INDEX_op_mov_v64: + case INDEX_op_movi_v64: + case INDEX_op_ld_v64: + case INDEX_op_st_v64: + case INDEX_op_and_v64: + case INDEX_op_or_v64: + case INDEX_op_xor_v64: + case INDEX_op_add8_v64: + case INDEX_op_add16_v64: + case INDEX_op_add32_v64: + case INDEX_op_sub8_v64: + case INDEX_op_sub16_v64: + case INDEX_op_sub32_v64: + return TCG_TARGET_HAS_v64; + + case INDEX_op_mov_v128: + case INDEX_op_movi_v128: + case INDEX_op_ld_v128: + case INDEX_op_st_v128: + case INDEX_op_and_v128: + case INDEX_op_or_v128: + case INDEX_op_xor_v128: + case INDEX_op_add8_v128: + case INDEX_op_add16_v128: + case INDEX_op_add32_v128: + case INDEX_op_add64_v128: + case INDEX_op_sub8_v128: + case INDEX_op_sub16_v128: + case INDEX_op_sub32_v128: + case INDEX_op_sub64_v128: + return TCG_TARGET_HAS_v128; + + case INDEX_op_mov_v256: + case INDEX_op_movi_v256: + case INDEX_op_ld_v256: + case INDEX_op_st_v256: + case INDEX_op_and_v256: + case INDEX_op_or_v256: + case INDEX_op_xor_v256: + case INDEX_op_add8_v256: + case INDEX_op_add16_v256: + case INDEX_op_add32_v256: + case INDEX_op_add64_v256: + case INDEX_op_sub8_v256: + case INDEX_op_sub16_v256: + case INDEX_op_sub32_v256: + case INDEX_op_sub64_v256: + return TCG_TARGET_HAS_v256; + + case INDEX_op_not_v64: + return TCG_TARGET_HAS_not_v64; + case INDEX_op_not_v128: + return TCG_TARGET_HAS_not_v128; + case INDEX_op_not_v256: + return TCG_TARGET_HAS_not_v256; + + case INDEX_op_andc_v64: + return TCG_TARGET_HAS_andc_v64; + case INDEX_op_andc_v128: + return TCG_TARGET_HAS_andc_v128; + case INDEX_op_andc_v256: + return TCG_TARGET_HAS_andc_v256; + + case INDEX_op_orc_v64: + return TCG_TARGET_HAS_orc_v64; + case INDEX_op_orc_v128: + return TCG_TARGET_HAS_orc_v128; + case INDEX_op_orc_v256: + return TCG_TARGET_HAS_orc_v256; + + case INDEX_op_neg8_v64: + case INDEX_op_neg16_v64: + case INDEX_op_neg32_v64: + return TCG_TARGET_HAS_neg_v64; + + case INDEX_op_neg8_v128: + case INDEX_op_neg16_v128: + case INDEX_op_neg32_v128: + case INDEX_op_neg64_v128: + return TCG_TARGET_HAS_neg_v128; + + case INDEX_op_neg8_v256: + case INDEX_op_neg16_v256: + case INDEX_op_neg32_v256: + case INDEX_op_neg64_v256: + return TCG_TARGET_HAS_neg_v256; + + case NB_OPS: + break; + } + g_assert_not_reached(); +} + /* Note: we convert the 64 bit args to 32 bit and do some alignment and endian swap. Maybe it would be better to do the alignment and endian swap in tcg_reg_alloc_call(). */ -- 2.13.5 From MAILER-DAEMON Thu Aug 17 19:01:36 2017 Received: from list by lists.gnu.org with archive (Exim 4.71) id 1diTnD-000556-5B for mharc-qemu-arm@gnu.org; Thu, 17 Aug 2017 19:01:35 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:44554) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1diTn5-0004xH-Fu for qemu-arm@nongnu.org; Thu, 17 Aug 2017 19:01:29 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1diTn4-0000xt-Pt for qemu-arm@nongnu.org; Thu, 17 Aug 2017 19:01:27 -0400 Received: from mail-pg0-x22d.google.com ([2607:f8b0:400e:c05::22d]:35406) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1diTn4-0000xR-LD for qemu-arm@nongnu.org; Thu, 17 Aug 2017 19:01:26 -0400 Received: by mail-pg0-x22d.google.com with SMTP id v189so51827055pgd.2 for ; Thu, 17 Aug 2017 16:01:26 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=dpdlyo3XtVpsa3ftb6C8wRlu5yzXE0Obkds6jVxb5hw=; b=NYmCuYgEnbczxXFGsRPIauPB+03hnctKKtTaOoKZa/Yek3w5jieLYsou8TgpIhmJ1o RFdWq32rcqfaZdS8/7R9H5HZPnuhWF6LajCpasBijtif4pxANchy6RgjHRZnZeX5TYRR 4aim+tHJHsAEv80MSBeZJW1bQMHHRUpXc+Ow8= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=dpdlyo3XtVpsa3ftb6C8wRlu5yzXE0Obkds6jVxb5hw=; b=gv26znoa3xHwkGgsTSVOnU6XqchJMY8JCInFuxgCLhw+ZbwwC+32P3mNRnfa5iNYBZ KT8KLU9DVa2LF+F0I9kJ+MW5YAyMsQt9oe2jRLF/KPImRAfJOYTtfZZaWIF+AXZs7iJH NcvVo5q0s8IhyD/v+eRR+Q23TsHyxXR6pFG68QkTZeVAlTYGBEwySGLt/l9EKmWsknNg 6rDsA8P81sN2W8+Is42H1PVEx2M3V2tlebEeTCaYd/g9HJ9yEZVGKv4/bCTu/KZMEiUh rklxfKl0yaJPF5j9WhoeCGB6YMdZFRvYI/1smoUHAp01k112+r3AaXMkRFcvGhgKAUAW WGOA== X-Gm-Message-State: AHYfb5imVwBvRaOgNJ0pCAblu0gwRTbNNgqZN6WOsX6JDu27mHt6uMwJ YTW6acjhcMzkd1nFKhls9Q== X-Received: by 10.98.14.93 with SMTP id w90mr6909429pfi.298.1503010885018; Thu, 17 Aug 2017 16:01:25 -0700 (PDT) Received: from bigtime.twiddle.net (97-126-108-236.tukw.qwest.net. [97.126.108.236]) by smtp.gmail.com with ESMTPSA id c23sm5190043pfc.136.2017.08.17.16.01.23 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 17 Aug 2017 16:01:24 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, alex.bennee@linaro.org Date: Thu, 17 Aug 2017 16:01:12 -0700 Message-Id: <20170817230114.3655-7-richard.henderson@linaro.org> X-Mailer: git-send-email 2.13.5 In-Reply-To: <20170817230114.3655-1-richard.henderson@linaro.org> References: <20170817230114.3655-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::22d Subject: [Qemu-arm] [PATCH 6/8] tcg: Add INDEX_op_invalid X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 17 Aug 2017 23:01:30 -0000 Add with value 0 so that structure zero initialization can indicate that the field is not present. Signed-off-by: Richard Henderson --- tcg/tcg-opc.h | 2 ++ tcg/tcg.c | 3 +++ 2 files changed, 5 insertions(+) diff --git a/tcg/tcg-opc.h b/tcg/tcg-opc.h index 9162125fac..b1445a4c24 100644 --- a/tcg/tcg-opc.h +++ b/tcg/tcg-opc.h @@ -26,6 +26,8 @@ * DEF(name, oargs, iargs, cargs, flags) */ +DEF(invalid, 0, 0, 0, TCG_OPF_NOT_PRESENT) + /* predefined ops */ DEF(discard, 1, 0, 0, TCG_OPF_NOT_PRESENT) DEF(set_label, 0, 0, 1, TCG_OPF_BB_END | TCG_OPF_NOT_PRESENT) diff --git a/tcg/tcg.c b/tcg/tcg.c index 3c3cdda938..879b29e81f 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -756,6 +756,9 @@ int tcg_check_temp_count(void) bool tcg_op_supported(TCGOpcode op) { switch (op) { + case INDEX_op_invalid: + return false; + case INDEX_op_discard: case INDEX_op_set_label: case INDEX_op_call: -- 2.13.5 From MAILER-DAEMON Thu Aug 17 19:01:37 2017 Received: from list by lists.gnu.org with archive (Exim 4.71) id 1diTnE-00056D-Nt for mharc-qemu-arm@gnu.org; Thu, 17 Aug 2017 19:01:36 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:44606) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1diTn8-0004zn-Pz for qemu-arm@nongnu.org; Thu, 17 Aug 2017 19:01:33 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1diTn6-0000yo-Nq for qemu-arm@nongnu.org; Thu, 17 Aug 2017 19:01:30 -0400 Received: from mail-pg0-x229.google.com ([2607:f8b0:400e:c05::229]:36983) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1diTn6-0000yU-FH for qemu-arm@nongnu.org; Thu, 17 Aug 2017 19:01:28 -0400 Received: by mail-pg0-x229.google.com with SMTP id y129so51926370pgy.4 for ; Thu, 17 Aug 2017 16:01:28 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=ayDUNuMxBJiB70+Pu5TZupwFTb2kohK2+QYR/Q2F6rg=; b=V4mEpb1xOMQrlcvGv1KqgEZ+kPVth2kZllsNtYaFD+kChXCtn2lwjYNfWyXJpIrLFJ 7gJyLIRWPOgAFTZUVy/76rkddSgBcQYecfccNy3Zpm8nuSokPtFo/0NPC5s+LJjhM5gS XQNTD20jWF4tLuNrw6wJAa1wZy0l2D1nhZnk8= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=ayDUNuMxBJiB70+Pu5TZupwFTb2kohK2+QYR/Q2F6rg=; b=ITj1O8QTiCWnYFDNvDDHBD6yw3UIGpZMKXHYymDovi6yK+D48sgCbp52xTWCiz2lfU UJpsTuG9ks27yxE2oViLQCb57OApS0okDAYyk1toXeaRzGCG7aGy88n8R64vZ9DTZ9MT dH3P9FzLa/9PhhnpaZBOgBIE7q0W2CF5twcYzBJUuPruFjvnb/OPqz2U1ta12DkwZkGK EQJB+ZylHVJTOqPo4rIiaWixyQ3LG5H1nGfYu+GAbiVArqrjUqXsinCg/AA53lyOPtIU gjt/fUqO28bU5Cb06VjD101BVJjffch+hh59v4rNJs5owDzSKJ1zYfzNPIsaXLVTIpLU 1VEQ== X-Gm-Message-State: AHYfb5hfprHr+ldS5EBtLnuoek2rliw2qnP/hzrcMWX0eNyYybTN5Ql7 nG9yykZdToQVX4fd3eyt5Q== X-Received: by 10.98.86.195 with SMTP id h64mr6585247pfj.99.1503010886329; Thu, 17 Aug 2017 16:01:26 -0700 (PDT) Received: from bigtime.twiddle.net (97-126-108-236.tukw.qwest.net. [97.126.108.236]) by smtp.gmail.com with ESMTPSA id c23sm5190043pfc.136.2017.08.17.16.01.25 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 17 Aug 2017 16:01:25 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, alex.bennee@linaro.org Date: Thu, 17 Aug 2017 16:01:13 -0700 Message-Id: <20170817230114.3655-8-richard.henderson@linaro.org> X-Mailer: git-send-email 2.13.5 In-Reply-To: <20170817230114.3655-1-richard.henderson@linaro.org> References: <20170817230114.3655-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::229 Subject: [Qemu-arm] [PATCH 7/8] tcg: Expand target vector ops with host vector ops X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 17 Aug 2017 23:01:34 -0000 Signed-off-by: Richard Henderson --- tcg/tcg-op-gvec.h | 4 + tcg/tcg.h | 6 +- tcg/tcg-op-gvec.c | 230 +++++++++++++++++++++++++++++++++++++++++++----------- tcg/tcg.c | 8 +- 4 files changed, 197 insertions(+), 51 deletions(-) diff --git a/tcg/tcg-op-gvec.h b/tcg/tcg-op-gvec.h index 10db3599a5..99f36d208e 100644 --- a/tcg/tcg-op-gvec.h +++ b/tcg/tcg-op-gvec.h @@ -40,6 +40,10 @@ typedef struct { /* Similarly, but load up a constant and re-use across lanes. */ void (*fni8x)(TCGv_i64, TCGv_i64, TCGv_i64, TCGv_i64); uint64_t extra_value; + /* Operations with host vector ops. */ + TCGOpcode op_v256; + TCGOpcode op_v128; + TCGOpcode op_v64; /* Larger sizes: expand out-of-line helper w/size descriptor. */ void (*fno)(TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_i32); } GVecGen3; diff --git a/tcg/tcg.h b/tcg/tcg.h index b443143b21..7f10501d31 100644 --- a/tcg/tcg.h +++ b/tcg/tcg.h @@ -825,9 +825,11 @@ int tcg_global_mem_new_internal(TCGType, TCGv_ptr, intptr_t, const char *); TCGv_i32 tcg_global_reg_new_i32(TCGReg reg, const char *name); TCGv_i64 tcg_global_reg_new_i64(TCGReg reg, const char *name); -TCGv_i32 tcg_temp_new_internal_i32(int temp_local); -TCGv_i64 tcg_temp_new_internal_i64(int temp_local); +int tcg_temp_new_internal(TCGType type, bool temp_local); +TCGv_i32 tcg_temp_new_internal_i32(bool temp_local); +TCGv_i64 tcg_temp_new_internal_i64(bool temp_local); +void tcg_temp_free_internal(int arg); void tcg_temp_free_i32(TCGv_i32 arg); void tcg_temp_free_i64(TCGv_i64 arg); diff --git a/tcg/tcg-op-gvec.c b/tcg/tcg-op-gvec.c index 6de49dc07f..3aca565dc0 100644 --- a/tcg/tcg-op-gvec.c +++ b/tcg/tcg-op-gvec.c @@ -30,54 +30,73 @@ #define REP8(x) ((x) * 0x0101010101010101ull) #define REP16(x) ((x) * 0x0001000100010001ull) -#define MAX_INLINE 16 +#define MAX_UNROLL 4 -static inline void check_size_s(uint32_t opsz, uint32_t clsz) +static inline void check_size_align(uint32_t opsz, uint32_t clsz, uint32_t ofs) { - tcg_debug_assert(opsz % 8 == 0); - tcg_debug_assert(clsz % 8 == 0); + uint32_t align = clsz > 16 || opsz >= 16 ? 15 : 7; + tcg_debug_assert(opsz > 0); tcg_debug_assert(opsz <= clsz); + tcg_debug_assert((opsz & align) == 0); + tcg_debug_assert((clsz & align) == 0); + tcg_debug_assert((ofs & align) == 0); } -static inline void check_align_s_3(uint32_t dofs, uint32_t aofs, uint32_t bofs) +static inline void check_overlap_3(uint32_t d, uint32_t a, + uint32_t b, uint32_t s) { - tcg_debug_assert(dofs % 8 == 0); - tcg_debug_assert(aofs % 8 == 0); - tcg_debug_assert(bofs % 8 == 0); + tcg_debug_assert(d == a || d + s <= a || a + s <= d); + tcg_debug_assert(d == b || d + s <= b || b + s <= d); + tcg_debug_assert(a == b || a + s <= b || b + s <= a); } -static inline void check_size_l(uint32_t opsz, uint32_t clsz) +static inline bool check_size_impl(uint32_t opsz, uint32_t lnsz) { - tcg_debug_assert(opsz % 16 == 0); - tcg_debug_assert(clsz % 16 == 0); - tcg_debug_assert(opsz <= clsz); + uint32_t lnct = opsz / lnsz; + return lnct >= 1 && lnct <= MAX_UNROLL; } -static inline void check_align_l_3(uint32_t dofs, uint32_t aofs, uint32_t bofs) +static void expand_clr_v(uint32_t dofs, uint32_t clsz, uint32_t lnsz, + TCGType type, TCGOpcode opc_mv, TCGOpcode opc_st) { - tcg_debug_assert(dofs % 16 == 0); - tcg_debug_assert(aofs % 16 == 0); - tcg_debug_assert(bofs % 16 == 0); -} + TCGArg t0 = tcg_temp_new_internal(type, 0); + TCGArg env = GET_TCGV_PTR(tcg_ctx.tcg_env); + uint32_t i; -static inline void check_overlap_3(uint32_t d, uint32_t a, - uint32_t b, uint32_t s) -{ - tcg_debug_assert(d == a || d + s <= a || a + s <= d); - tcg_debug_assert(d == b || d + s <= b || b + s <= d); - tcg_debug_assert(a == b || a + s <= b || b + s <= a); + tcg_gen_op2(&tcg_ctx, opc_mv, t0, 0); + for (i = 0; i < clsz; i += lnsz) { + tcg_gen_op3(&tcg_ctx, opc_st, t0, env, dofs + i); + } + tcg_temp_free_internal(t0); } -static void expand_clr(uint32_t dofs, uint32_t opsz, uint32_t clsz) +static void expand_clr(uint32_t dofs, uint32_t clsz) { - if (clsz > opsz) { - TCGv_i64 zero = tcg_const_i64(0); - uint32_t i; + if (clsz >= 32 && TCG_TARGET_HAS_v256) { + uint32_t done = QEMU_ALIGN_DOWN(clsz, 32); + expand_clr_v(dofs, done, 32, TCG_TYPE_V256, + INDEX_op_movi_v256, INDEX_op_st_v256); + dofs += done; + clsz -= done; + } - for (i = opsz; i < clsz; i += 8) { - tcg_gen_st_i64(zero, tcg_ctx.tcg_env, dofs + i); - } - tcg_temp_free_i64(zero); + if (clsz >= 16 && TCG_TARGET_HAS_v128) { + uint16_t done = QEMU_ALIGN_DOWN(clsz, 16); + expand_clr_v(dofs, done, 16, TCG_TYPE_V128, + INDEX_op_movi_v128, INDEX_op_st_v128); + dofs += done; + clsz -= done; + } + + if (TCG_TARGET_REG_BITS == 64) { + expand_clr_v(dofs, clsz, 8, TCG_TYPE_I64, + INDEX_op_movi_i64, INDEX_op_st_i64); + } else if (TCG_TARGET_HAS_v64) { + expand_clr_v(dofs, clsz, 8, TCG_TYPE_V64, + INDEX_op_movi_v64, INDEX_op_st_v64); + } else { + expand_clr_v(dofs, clsz, 4, TCG_TYPE_I32, + INDEX_op_movi_i32, INDEX_op_st_i32); } } @@ -164,6 +183,7 @@ static void expand_3x8(uint32_t dofs, uint32_t aofs, tcg_temp_free_i64(t0); } +/* FIXME: add CSE for constants and we can eliminate this. */ static void expand_3x8p1(uint32_t dofs, uint32_t aofs, uint32_t bofs, uint32_t opsz, uint64_t data, void (*fni)(TCGv_i64, TCGv_i64, TCGv_i64, TCGv_i64)) @@ -192,28 +212,111 @@ static void expand_3x8p1(uint32_t dofs, uint32_t aofs, uint32_t bofs, tcg_temp_free_i64(t2); } +static void expand_3_v(uint32_t dofs, uint32_t aofs, uint32_t bofs, + uint32_t opsz, uint32_t lnsz, TCGType type, + TCGOpcode opc_op, TCGOpcode opc_ld, TCGOpcode opc_st) +{ + TCGArg t0 = tcg_temp_new_internal(type, 0); + TCGArg env = GET_TCGV_PTR(tcg_ctx.tcg_env); + uint32_t i; + + if (aofs == bofs) { + for (i = 0; i < opsz; i += lnsz) { + tcg_gen_op3(&tcg_ctx, opc_ld, t0, env, aofs + i); + tcg_gen_op3(&tcg_ctx, opc_op, t0, t0, t0); + tcg_gen_op3(&tcg_ctx, opc_st, t0, env, dofs + i); + } + } else { + TCGArg t1 = tcg_temp_new_internal(type, 0); + for (i = 0; i < opsz; i += lnsz) { + tcg_gen_op3(&tcg_ctx, opc_ld, t0, env, aofs + i); + tcg_gen_op3(&tcg_ctx, opc_ld, t1, env, bofs + i); + tcg_gen_op3(&tcg_ctx, opc_op, t0, t0, t1); + tcg_gen_op3(&tcg_ctx, opc_st, t0, env, dofs + i); + } + tcg_temp_free_internal(t1); + } + tcg_temp_free_internal(t0); +} + void tcg_gen_gvec_3(uint32_t dofs, uint32_t aofs, uint32_t bofs, uint32_t opsz, uint32_t clsz, const GVecGen3 *g) { + check_size_align(opsz, clsz, dofs | aofs | bofs); check_overlap_3(dofs, aofs, bofs, clsz); - if (opsz <= MAX_INLINE) { - check_size_s(opsz, clsz); - check_align_s_3(dofs, aofs, bofs); - if (g->fni8) { - expand_3x8(dofs, aofs, bofs, opsz, g->fni8); - } else if (g->fni4) { - expand_3x4(dofs, aofs, bofs, opsz, g->fni4); + + if (opsz > MAX_UNROLL * 32 || clsz > MAX_UNROLL * 32) { + goto do_ool; + } + + /* Recall that ARM SVE allows vector sizes that are not a power of 2. + Expand with successively smaller host vector sizes. The intent is + that e.g. opsz == 80 would be expanded with 2x32 + 1x16. */ + /* ??? For clsz > opsz, the host may be able to use an op-sized + operation, zeroing the balance of the register. We can then + use a cl-sized store to implement the clearing without an extra + store operation. This is true for aarch64 and x86_64 hosts. */ + + if (check_size_impl(opsz, 32) && tcg_op_supported(g->op_v256)) { + uint32_t done = QEMU_ALIGN_DOWN(opsz, 32); + expand_3_v(dofs, aofs, bofs, done, 32, TCG_TYPE_V256, + g->op_v256, INDEX_op_ld_v256, INDEX_op_st_v256); + dofs += done; + aofs += done; + bofs += done; + opsz -= done; + clsz -= done; + } + + if (check_size_impl(opsz, 16) && tcg_op_supported(g->op_v128)) { + uint32_t done = QEMU_ALIGN_DOWN(opsz, 16); + expand_3_v(dofs, aofs, bofs, done, 16, TCG_TYPE_V128, + g->op_v128, INDEX_op_ld_v128, INDEX_op_st_v128); + dofs += done; + aofs += done; + bofs += done; + opsz -= done; + clsz -= done; + } + + if (check_size_impl(opsz, 8)) { + uint32_t done = QEMU_ALIGN_DOWN(opsz, 8); + if (tcg_op_supported(g->op_v64)) { + expand_3_v(dofs, aofs, bofs, done, 8, TCG_TYPE_V64, + g->op_v64, INDEX_op_ld_v64, INDEX_op_st_v64); + } else if (g->fni8) { + expand_3x8(dofs, aofs, bofs, done, g->fni8); } else if (g->fni8x) { - expand_3x8p1(dofs, aofs, bofs, opsz, g->extra_value, g->fni8x); + expand_3x8p1(dofs, aofs, bofs, done, g->extra_value, g->fni8x); } else { - g_assert_not_reached(); + done = 0; } - expand_clr(dofs, opsz, clsz); - } else { - check_size_l(opsz, clsz); - check_align_l_3(dofs, aofs, bofs); - expand_3_o(dofs, aofs, bofs, opsz, clsz, g->fno); + dofs += done; + aofs += done; + bofs += done; + opsz -= done; + clsz -= done; } + + if (check_size_impl(opsz, 4)) { + uint32_t done = QEMU_ALIGN_DOWN(opsz, 4); + expand_3x4(dofs, aofs, bofs, done, g->fni4); + dofs += done; + aofs += done; + bofs += done; + opsz -= done; + clsz -= done; + } + + if (opsz == 0) { + if (clsz != 0) { + expand_clr(dofs, clsz); + } + return; + } + + do_ool: + expand_3_o(dofs, aofs, bofs, opsz, clsz, g->fno); } static void gen_addv_mask(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b, TCGv_i64 m) @@ -240,6 +343,9 @@ void tcg_gen_gvec_add8(uint32_t dofs, uint32_t aofs, uint32_t bofs, static const GVecGen3 g = { .extra_value = REP8(0x80), .fni8x = gen_addv_mask, + .op_v256 = INDEX_op_add8_v256, + .op_v128 = INDEX_op_add8_v128, + .op_v64 = INDEX_op_add8_v64, .fno = gen_helper_gvec_add8, }; tcg_gen_gvec_3(dofs, aofs, bofs, opsz, clsz, &g); @@ -251,6 +357,9 @@ void tcg_gen_gvec_add16(uint32_t dofs, uint32_t aofs, uint32_t bofs, static const GVecGen3 g = { .extra_value = REP16(0x8000), .fni8x = gen_addv_mask, + .op_v256 = INDEX_op_add16_v256, + .op_v128 = INDEX_op_add16_v128, + .op_v64 = INDEX_op_add16_v64, .fno = gen_helper_gvec_add16, }; tcg_gen_gvec_3(dofs, aofs, bofs, opsz, clsz, &g); @@ -261,6 +370,9 @@ void tcg_gen_gvec_add32(uint32_t dofs, uint32_t aofs, uint32_t bofs, { static const GVecGen3 g = { .fni4 = tcg_gen_add_i32, + .op_v256 = INDEX_op_add32_v256, + .op_v128 = INDEX_op_add32_v128, + .op_v64 = INDEX_op_add32_v64, .fno = gen_helper_gvec_add32, }; tcg_gen_gvec_3(dofs, aofs, bofs, opsz, clsz, &g); @@ -271,6 +383,8 @@ void tcg_gen_gvec_add64(uint32_t dofs, uint32_t aofs, uint32_t bofs, { static const GVecGen3 g = { .fni8 = tcg_gen_add_i64, + .op_v256 = INDEX_op_add64_v256, + .op_v128 = INDEX_op_add64_v128, .fno = gen_helper_gvec_add64, }; tcg_gen_gvec_3(dofs, aofs, bofs, opsz, clsz, &g); @@ -328,6 +442,9 @@ void tcg_gen_gvec_sub8(uint32_t dofs, uint32_t aofs, uint32_t bofs, static const GVecGen3 g = { .extra_value = REP8(0x80), .fni8x = gen_subv_mask, + .op_v256 = INDEX_op_sub8_v256, + .op_v128 = INDEX_op_sub8_v128, + .op_v64 = INDEX_op_sub8_v64, .fno = gen_helper_gvec_sub8, }; tcg_gen_gvec_3(dofs, aofs, bofs, opsz, clsz, &g); @@ -339,6 +456,9 @@ void tcg_gen_gvec_sub16(uint32_t dofs, uint32_t aofs, uint32_t bofs, static const GVecGen3 g = { .extra_value = REP16(0x8000), .fni8x = gen_subv_mask, + .op_v256 = INDEX_op_sub16_v256, + .op_v128 = INDEX_op_sub16_v128, + .op_v64 = INDEX_op_sub16_v64, .fno = gen_helper_gvec_sub16, }; tcg_gen_gvec_3(dofs, aofs, bofs, opsz, clsz, &g); @@ -349,6 +469,9 @@ void tcg_gen_gvec_sub32(uint32_t dofs, uint32_t aofs, uint32_t bofs, { static const GVecGen3 g = { .fni4 = tcg_gen_sub_i32, + .op_v256 = INDEX_op_sub32_v256, + .op_v128 = INDEX_op_sub32_v128, + .op_v64 = INDEX_op_sub32_v64, .fno = gen_helper_gvec_sub32, }; tcg_gen_gvec_3(dofs, aofs, bofs, opsz, clsz, &g); @@ -359,6 +482,8 @@ void tcg_gen_gvec_sub64(uint32_t dofs, uint32_t aofs, uint32_t bofs, { static const GVecGen3 g = { .fni8 = tcg_gen_sub_i64, + .op_v256 = INDEX_op_sub64_v256, + .op_v128 = INDEX_op_sub64_v128, .fno = gen_helper_gvec_sub64, }; tcg_gen_gvec_3(dofs, aofs, bofs, opsz, clsz, &g); @@ -397,6 +522,9 @@ void tcg_gen_gvec_and8(uint32_t dofs, uint32_t aofs, uint32_t bofs, { static const GVecGen3 g = { .fni8 = tcg_gen_and_i64, + .op_v256 = INDEX_op_and_v256, + .op_v128 = INDEX_op_and_v128, + .op_v64 = INDEX_op_and_v64, .fno = gen_helper_gvec_and8, }; tcg_gen_gvec_3(dofs, aofs, bofs, opsz, clsz, &g); @@ -407,6 +535,9 @@ void tcg_gen_gvec_or8(uint32_t dofs, uint32_t aofs, uint32_t bofs, { static const GVecGen3 g = { .fni8 = tcg_gen_or_i64, + .op_v256 = INDEX_op_or_v256, + .op_v128 = INDEX_op_or_v128, + .op_v64 = INDEX_op_or_v64, .fno = gen_helper_gvec_or8, }; tcg_gen_gvec_3(dofs, aofs, bofs, opsz, clsz, &g); @@ -417,6 +548,9 @@ void tcg_gen_gvec_xor8(uint32_t dofs, uint32_t aofs, uint32_t bofs, { static const GVecGen3 g = { .fni8 = tcg_gen_xor_i64, + .op_v256 = INDEX_op_xor_v256, + .op_v128 = INDEX_op_xor_v128, + .op_v64 = INDEX_op_xor_v64, .fno = gen_helper_gvec_xor8, }; tcg_gen_gvec_3(dofs, aofs, bofs, opsz, clsz, &g); @@ -427,6 +561,9 @@ void tcg_gen_gvec_andc8(uint32_t dofs, uint32_t aofs, uint32_t bofs, { static const GVecGen3 g = { .fni8 = tcg_gen_andc_i64, + .op_v256 = INDEX_op_andc_v256, + .op_v128 = INDEX_op_andc_v128, + .op_v64 = INDEX_op_andc_v64, .fno = gen_helper_gvec_andc8, }; tcg_gen_gvec_3(dofs, aofs, bofs, opsz, clsz, &g); @@ -437,6 +574,9 @@ void tcg_gen_gvec_orc8(uint32_t dofs, uint32_t aofs, uint32_t bofs, { static const GVecGen3 g = { .fni8 = tcg_gen_orc_i64, + .op_v256 = INDEX_op_orc_v256, + .op_v128 = INDEX_op_orc_v128, + .op_v64 = INDEX_op_orc_v64, .fno = gen_helper_gvec_orc8, }; tcg_gen_gvec_3(dofs, aofs, bofs, opsz, clsz, &g); diff --git a/tcg/tcg.c b/tcg/tcg.c index 879b29e81f..86eb4214b0 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -604,7 +604,7 @@ int tcg_global_mem_new_internal(TCGType type, TCGv_ptr base, return temp_idx(s, ts); } -static int tcg_temp_new_internal(TCGType type, int temp_local) +int tcg_temp_new_internal(TCGType type, bool temp_local) { TCGContext *s = &tcg_ctx; TCGTemp *ts; @@ -650,7 +650,7 @@ static int tcg_temp_new_internal(TCGType type, int temp_local) return idx; } -TCGv_i32 tcg_temp_new_internal_i32(int temp_local) +TCGv_i32 tcg_temp_new_internal_i32(bool temp_local) { int idx; @@ -658,7 +658,7 @@ TCGv_i32 tcg_temp_new_internal_i32(int temp_local) return MAKE_TCGV_I32(idx); } -TCGv_i64 tcg_temp_new_internal_i64(int temp_local) +TCGv_i64 tcg_temp_new_internal_i64(bool temp_local) { int idx; @@ -666,7 +666,7 @@ TCGv_i64 tcg_temp_new_internal_i64(int temp_local) return MAKE_TCGV_I64(idx); } -static void tcg_temp_free_internal(int idx) +void tcg_temp_free_internal(int idx) { TCGContext *s = &tcg_ctx; TCGTemp *ts; -- 2.13.5 From MAILER-DAEMON Thu Aug 17 19:01:39 2017 Received: from list by lists.gnu.org with archive (Exim 4.71) id 1diTnH-00058n-4m for mharc-qemu-arm@gnu.org; Thu, 17 Aug 2017 19:01:39 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:44639) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1diTnB-00053P-UL for qemu-arm@nongnu.org; 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[97.126.108.236]) by smtp.gmail.com with ESMTPSA id c23sm5190043pfc.136.2017.08.17.16.01.26 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 17 Aug 2017 16:01:26 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, alex.bennee@linaro.org Date: Thu, 17 Aug 2017 16:01:14 -0700 Message-Id: <20170817230114.3655-9-richard.henderson@linaro.org> X-Mailer: git-send-email 2.13.5 In-Reply-To: <20170817230114.3655-1-richard.henderson@linaro.org> References: <20170817230114.3655-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::22c Subject: [Qemu-arm] [PATCH 8/8] tcg/i386: Add vector operations X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 17 Aug 2017 23:01:36 -0000 Signed-off-by: Richard Henderson --- tcg/i386/tcg-target.h | 46 +++++- tcg/tcg-opc.h | 12 +- tcg/i386/tcg-target.inc.c | 382 ++++++++++++++++++++++++++++++++++++++++++---- 3 files changed, 399 insertions(+), 41 deletions(-) diff --git a/tcg/i386/tcg-target.h b/tcg/i386/tcg-target.h index e512648c95..147f82062b 100644 --- a/tcg/i386/tcg-target.h +++ b/tcg/i386/tcg-target.h @@ -30,11 +30,10 @@ #ifdef __x86_64__ # define TCG_TARGET_REG_BITS 64 -# define TCG_TARGET_NB_REGS 16 #else # define TCG_TARGET_REG_BITS 32 -# define TCG_TARGET_NB_REGS 8 #endif +# define TCG_TARGET_NB_REGS 24 typedef enum { TCG_REG_EAX = 0, @@ -56,6 +55,19 @@ typedef enum { TCG_REG_R13, TCG_REG_R14, TCG_REG_R15, + + /* SSE registers; 64-bit has access to 8 more, but we won't + need more than a few and using only the first 8 minimizes + the need for a rex prefix on the sse instructions. */ + TCG_REG_XMM0, + TCG_REG_XMM1, + TCG_REG_XMM2, + TCG_REG_XMM3, + TCG_REG_XMM4, + TCG_REG_XMM5, + TCG_REG_XMM6, + TCG_REG_XMM7, + TCG_REG_RAX = TCG_REG_EAX, TCG_REG_RCX = TCG_REG_ECX, TCG_REG_RDX = TCG_REG_EDX, @@ -79,6 +91,17 @@ extern bool have_bmi1; extern bool have_bmi2; extern bool have_popcnt; +#ifdef __SSE2__ +#define have_sse2 true +#else +extern bool have_sse2; +#endif +#ifdef __AVX2__ +#define have_avx2 true +#else +extern bool have_avx2; +#endif + /* optional instructions */ #define TCG_TARGET_HAS_div2_i32 1 #define TCG_TARGET_HAS_rot_i32 1 @@ -147,6 +170,25 @@ extern bool have_popcnt; #define TCG_TARGET_HAS_mulsh_i64 0 #endif +#define TCG_TARGET_HAS_v64 have_sse2 +#define TCG_TARGET_HAS_v128 have_sse2 +#define TCG_TARGET_HAS_v256 have_avx2 + +#define TCG_TARGET_HAS_andc_v64 TCG_TARGET_HAS_v64 +#define TCG_TARGET_HAS_orc_v64 0 +#define TCG_TARGET_HAS_not_v64 0 +#define TCG_TARGET_HAS_neg_v64 0 + +#define TCG_TARGET_HAS_andc_v128 TCG_TARGET_HAS_v128 +#define TCG_TARGET_HAS_orc_v128 0 +#define TCG_TARGET_HAS_not_v128 0 +#define TCG_TARGET_HAS_neg_v128 0 + +#define TCG_TARGET_HAS_andc_v256 TCG_TARGET_HAS_v256 +#define TCG_TARGET_HAS_orc_v256 0 +#define TCG_TARGET_HAS_not_v256 0 +#define TCG_TARGET_HAS_neg_v256 0 + #define TCG_TARGET_deposit_i32_valid(ofs, len) \ (have_bmi2 || \ ((ofs) == 0 && (len) == 8) || \ diff --git a/tcg/tcg-opc.h b/tcg/tcg-opc.h index b1445a4c24..b84cd584fb 100644 --- a/tcg/tcg-opc.h +++ b/tcg/tcg-opc.h @@ -212,13 +212,13 @@ DEF(qemu_st_i64, 0, TLADDR_ARGS + DATA64_ARGS, 1, /* Host integer vector operations. */ /* These opcodes are required whenever the base vector size is enabled. */ -DEF(mov_v64, 1, 1, 0, IMPL(TCG_TARGET_HAS_v64)) -DEF(mov_v128, 1, 1, 0, IMPL(TCG_TARGET_HAS_v128)) -DEF(mov_v256, 1, 1, 0, IMPL(TCG_TARGET_HAS_v256)) +DEF(mov_v64, 1, 1, 0, TCG_OPF_NOT_PRESENT) +DEF(mov_v128, 1, 1, 0, TCG_OPF_NOT_PRESENT) +DEF(mov_v256, 1, 1, 0, TCG_OPF_NOT_PRESENT) -DEF(movi_v64, 1, 0, 1, IMPL(TCG_TARGET_HAS_v64)) -DEF(movi_v128, 1, 0, 1, IMPL(TCG_TARGET_HAS_v128)) -DEF(movi_v256, 1, 0, 1, IMPL(TCG_TARGET_HAS_v256)) +DEF(movi_v64, 1, 0, 1, TCG_OPF_NOT_PRESENT) +DEF(movi_v128, 1, 0, 1, TCG_OPF_NOT_PRESENT) +DEF(movi_v256, 1, 0, 1, TCG_OPF_NOT_PRESENT) DEF(ld_v64, 1, 1, 1, IMPL(TCG_TARGET_HAS_v64)) DEF(ld_v128, 1, 1, 1, IMPL(TCG_TARGET_HAS_v128)) diff --git a/tcg/i386/tcg-target.inc.c b/tcg/i386/tcg-target.inc.c index aeefb72aa0..0e01b54aa0 100644 --- a/tcg/i386/tcg-target.inc.c +++ b/tcg/i386/tcg-target.inc.c @@ -31,7 +31,9 @@ static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = { "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15", #else "%eax", "%ecx", "%edx", "%ebx", "%esp", "%ebp", "%esi", "%edi", + NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, #endif + "%xmm0", "%xmm1", "%xmm2", "%xmm3", "%xmm4", "%xmm5", "%xmm6", "%xmm7", }; #endif @@ -61,6 +63,14 @@ static const int tcg_target_reg_alloc_order[] = { TCG_REG_EDX, TCG_REG_EAX, #endif + TCG_REG_XMM0, + TCG_REG_XMM1, + TCG_REG_XMM2, + TCG_REG_XMM3, + TCG_REG_XMM4, + TCG_REG_XMM5, + TCG_REG_XMM6, + TCG_REG_XMM7, }; static const int tcg_target_call_iarg_regs[] = { @@ -94,7 +104,7 @@ static const int tcg_target_call_oarg_regs[] = { #define TCG_CT_CONST_I32 0x400 #define TCG_CT_CONST_WSZ 0x800 -/* Registers used with L constraint, which are the first argument +/* Registers used with L constraint, which are the first argument registers on x86_64, and two random call clobbered registers on i386. */ #if TCG_TARGET_REG_BITS == 64 @@ -127,6 +137,16 @@ bool have_bmi1; bool have_bmi2; bool have_popcnt; +#ifndef have_sse2 +bool have_sse2; +#endif +#ifdef have_avx2 +#define have_avx1 have_avx2 +#else +static bool have_avx1; +bool have_avx2; +#endif + #ifdef CONFIG_CPUID_H static bool have_movbe; static bool have_lzcnt; @@ -215,6 +235,10 @@ static const char *target_parse_constraint(TCGArgConstraint *ct, /* With TZCNT/LZCNT, we can have operand-size as an input. */ ct->ct |= TCG_CT_CONST_WSZ; break; + case 'x': + ct->ct |= TCG_CT_REG; + tcg_regset_set32(ct->u.regs, 0, 0xff0000); + break; /* qemu_ld/st address constraint */ case 'L': @@ -292,6 +316,7 @@ static inline int tcg_target_const_match(tcg_target_long val, TCGType type, #endif #define P_SIMDF3 0x20000 /* 0xf3 opcode prefix */ #define P_SIMDF2 0x40000 /* 0xf2 opcode prefix */ +#define P_VEXL 0x80000 /* Set VEX.L = 1 */ #define OPC_ARITH_EvIz (0x81) #define OPC_ARITH_EvIb (0x83) @@ -324,13 +349,31 @@ static inline int tcg_target_const_match(tcg_target_long val, TCGType type, #define OPC_MOVL_Iv (0xb8) #define OPC_MOVBE_GyMy (0xf0 | P_EXT38) #define OPC_MOVBE_MyGy (0xf1 | P_EXT38) +#define OPC_MOVDQA_GyMy (0x6f | P_EXT | P_DATA16) +#define OPC_MOVDQA_MyGy (0x7f | P_EXT | P_DATA16) +#define OPC_MOVDQU_GyMy (0x6f | P_EXT | P_SIMDF3) +#define OPC_MOVDQU_MyGy (0x7f | P_EXT | P_SIMDF3) +#define OPC_MOVQ_GyMy (0x7e | P_EXT | P_SIMDF3) +#define OPC_MOVQ_MyGy (0xd6 | P_EXT | P_DATA16) #define OPC_MOVSBL (0xbe | P_EXT) #define OPC_MOVSWL (0xbf | P_EXT) #define OPC_MOVSLQ (0x63 | P_REXW) #define OPC_MOVZBL (0xb6 | P_EXT) #define OPC_MOVZWL (0xb7 | P_EXT) +#define OPC_PADDB (0xfc | P_EXT | P_DATA16) +#define OPC_PADDW (0xfd | P_EXT | P_DATA16) +#define OPC_PADDD (0xfe | P_EXT | P_DATA16) +#define OPC_PADDQ (0xd4 | P_EXT | P_DATA16) +#define OPC_PAND (0xdb | P_EXT | P_DATA16) +#define OPC_PANDN (0xdf | P_EXT | P_DATA16) #define OPC_PDEP (0xf5 | P_EXT38 | P_SIMDF2) #define OPC_PEXT (0xf5 | P_EXT38 | P_SIMDF3) +#define OPC_POR (0xeb | P_EXT | P_DATA16) +#define OPC_PSUBB (0xf8 | P_EXT | P_DATA16) +#define OPC_PSUBW (0xf9 | P_EXT | P_DATA16) +#define OPC_PSUBD (0xfa | P_EXT | P_DATA16) +#define OPC_PSUBQ (0xfb | P_EXT | P_DATA16) +#define OPC_PXOR (0xef | P_EXT | P_DATA16) #define OPC_POP_r32 (0x58) #define OPC_POPCNT (0xb8 | P_EXT | P_SIMDF3) #define OPC_PUSH_r32 (0x50) @@ -500,7 +543,8 @@ static void tcg_out_modrm(TCGContext *s, int opc, int r, int rm) tcg_out8(s, 0xc0 | (LOWREGMASK(r) << 3) | LOWREGMASK(rm)); } -static void tcg_out_vex_pfx_opc(TCGContext *s, int opc, int r, int v, int rm) +static void tcg_out_vex_pfx_opc(TCGContext *s, int opc, int r, int v, + int rm, int index) { int tmp; @@ -515,14 +559,16 @@ static void tcg_out_vex_pfx_opc(TCGContext *s, int opc, int r, int v, int rm) } else if (opc & P_EXT) { tmp = 1; } else { - tcg_abort(); + g_assert_not_reached(); } - tmp |= 0x40; /* VEX.X */ tmp |= (r & 8 ? 0 : 0x80); /* VEX.R */ + tmp |= (index & 8 ? 0 : 0x40); /* VEX.X */ tmp |= (rm & 8 ? 0 : 0x20); /* VEX.B */ tcg_out8(s, tmp); tmp = (opc & P_REXW ? 0x80 : 0); /* VEX.W */ + tmp |= (opc & P_VEXL ? 0x04 : 0); /* VEX.L */ + /* VEX.pp */ if (opc & P_DATA16) { tmp |= 1; /* 0x66 */ @@ -538,7 +584,7 @@ static void tcg_out_vex_pfx_opc(TCGContext *s, int opc, int r, int v, int rm) static void tcg_out_vex_modrm(TCGContext *s, int opc, int r, int v, int rm) { - tcg_out_vex_pfx_opc(s, opc, r, v, rm); + tcg_out_vex_pfx_opc(s, opc, r, v, rm, 0); tcg_out8(s, 0xc0 | (LOWREGMASK(r) << 3) | LOWREGMASK(rm)); } @@ -565,7 +611,7 @@ static void tcg_out_opc_pool_imm(TCGContext *s, int opc, int r, static void tcg_out_vex_pool_imm(TCGContext *s, int opc, int r, int v, tcg_target_ulong data) { - tcg_out_vex_pfx_opc(s, opc, r, v, 0); + tcg_out_vex_pfx_opc(s, opc, r, v, 0, 0); tcg_out_sfx_pool_imm(s, r, data); } @@ -574,8 +620,8 @@ static void tcg_out_vex_pool_imm(TCGContext *s, int opc, int r, int v, mode for absolute addresses, ~RM is the size of the immediate operand that will follow the instruction. */ -static void tcg_out_modrm_sib_offset(TCGContext *s, int opc, int r, int rm, - int index, int shift, intptr_t offset) +static void tcg_out_sib_offset(TCGContext *s, int r, int rm, int index, + int shift, intptr_t offset) { int mod, len; @@ -586,7 +632,6 @@ static void tcg_out_modrm_sib_offset(TCGContext *s, int opc, int r, int rm, intptr_t pc = (intptr_t)s->code_ptr + 5 + ~rm; intptr_t disp = offset - pc; if (disp == (int32_t)disp) { - tcg_out_opc(s, opc, r, 0, 0); tcg_out8(s, (LOWREGMASK(r) << 3) | 5); tcg_out32(s, disp); return; @@ -596,7 +641,6 @@ static void tcg_out_modrm_sib_offset(TCGContext *s, int opc, int r, int rm, use of the MODRM+SIB encoding and is therefore larger than rip-relative addressing. */ if (offset == (int32_t)offset) { - tcg_out_opc(s, opc, r, 0, 0); tcg_out8(s, (LOWREGMASK(r) << 3) | 4); tcg_out8(s, (4 << 3) | 5); tcg_out32(s, offset); @@ -604,10 +648,9 @@ static void tcg_out_modrm_sib_offset(TCGContext *s, int opc, int r, int rm, } /* ??? The memory isn't directly addressable. */ - tcg_abort(); + g_assert_not_reached(); } else { /* Absolute address. */ - tcg_out_opc(s, opc, r, 0, 0); tcg_out8(s, (r << 3) | 5); tcg_out32(s, offset); return; @@ -630,7 +673,6 @@ static void tcg_out_modrm_sib_offset(TCGContext *s, int opc, int r, int rm, that would be used for %esp is the escape to the two byte form. */ if (index < 0 && LOWREGMASK(rm) != TCG_REG_ESP) { /* Single byte MODRM format. */ - tcg_out_opc(s, opc, r, rm, 0); tcg_out8(s, mod | (LOWREGMASK(r) << 3) | LOWREGMASK(rm)); } else { /* Two byte MODRM+SIB format. */ @@ -644,7 +686,6 @@ static void tcg_out_modrm_sib_offset(TCGContext *s, int opc, int r, int rm, tcg_debug_assert(index != TCG_REG_ESP); } - tcg_out_opc(s, opc, r, rm, index); tcg_out8(s, mod | (LOWREGMASK(r) << 3) | 4); tcg_out8(s, (shift << 6) | (LOWREGMASK(index) << 3) | LOWREGMASK(rm)); } @@ -656,6 +697,21 @@ static void tcg_out_modrm_sib_offset(TCGContext *s, int opc, int r, int rm, } } +static void tcg_out_modrm_sib_offset(TCGContext *s, int opc, int r, int rm, + int index, int shift, intptr_t offset) +{ + tcg_out_opc(s, opc, r, rm < 0 ? 0 : rm, index < 0 ? 0 : index); + tcg_out_sib_offset(s, r, rm, index, shift, offset); +} + +static void tcg_out_vex_modrm_sib_offset(TCGContext *s, int opc, int r, int v, + int rm, int index, int shift, + intptr_t offset) +{ + tcg_out_vex_pfx_opc(s, opc, r, v, rm < 0 ? 0 : rm, index < 0 ? 0 : index); + tcg_out_sib_offset(s, r, rm, index, shift, offset); +} + /* A simplification of the above with no index or shift. */ static inline void tcg_out_modrm_offset(TCGContext *s, int opc, int r, int rm, intptr_t offset) @@ -663,6 +719,31 @@ static inline void tcg_out_modrm_offset(TCGContext *s, int opc, int r, tcg_out_modrm_sib_offset(s, opc, r, rm, -1, 0, offset); } +static inline void tcg_out_vex_modrm_offset(TCGContext *s, int opc, int r, + int v, int rm, intptr_t offset) +{ + tcg_out_vex_modrm_sib_offset(s, opc, r, v, rm, -1, 0, offset); +} + +static void tcg_out_maybe_vex_modrm(TCGContext *s, int opc, int r, int rm) +{ + if (have_avx1) { + tcg_out_vex_modrm(s, opc, r, 0, rm); + } else { + tcg_out_modrm(s, opc, r, rm); + } +} + +static void tcg_out_maybe_vex_modrm_offset(TCGContext *s, int opc, int r, + int rm, intptr_t offset) +{ + if (have_avx1) { + tcg_out_vex_modrm_offset(s, opc, r, 0, rm, offset); + } else { + tcg_out_modrm_offset(s, opc, r, rm, offset); + } +} + /* Generate dest op= src. Uses the same ARITH_* codes as tgen_arithi. */ static inline void tgen_arithr(TCGContext *s, int subop, int dest, int src) { @@ -673,12 +754,32 @@ static inline void tgen_arithr(TCGContext *s, int subop, int dest, int src) tcg_out_modrm(s, OPC_ARITH_GvEv + (subop << 3) + ext, dest, src); } -static inline void tcg_out_mov(TCGContext *s, TCGType type, - TCGReg ret, TCGReg arg) +static void tcg_out_mov(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg) { if (arg != ret) { - int opc = OPC_MOVL_GvEv + (type == TCG_TYPE_I64 ? P_REXW : 0); - tcg_out_modrm(s, opc, ret, arg); + int opc = 0; + + switch (type) { + case TCG_TYPE_I64: + opc = P_REXW; + /* fallthru */ + case TCG_TYPE_I32: + opc |= OPC_MOVL_GvEv; + tcg_out_modrm(s, opc, ret, arg); + break; + + case TCG_TYPE_V256: + opc = P_VEXL; + /* fallthru */ + case TCG_TYPE_V128: + case TCG_TYPE_V64: + opc |= OPC_MOVDQA_GyMy; + tcg_out_maybe_vex_modrm(s, opc, ret, arg); + break; + + default: + g_assert_not_reached(); + } } } @@ -687,6 +788,27 @@ static void tcg_out_movi(TCGContext *s, TCGType type, { tcg_target_long diff; + switch (type) { + case TCG_TYPE_I32: + case TCG_TYPE_I64: + break; + + case TCG_TYPE_V64: + case TCG_TYPE_V128: + case TCG_TYPE_V256: + /* ??? Revisit this as the implementation progresses. */ + tcg_debug_assert(arg == 0); + if (have_avx1) { + tcg_out_vex_modrm(s, OPC_PXOR, ret, ret, ret); + } else { + tcg_out_modrm(s, OPC_PXOR, ret, ret); + } + return; + + default: + g_assert_not_reached(); + } + if (arg == 0) { tgen_arithr(s, ARITH_XOR, ret, ret); return; @@ -750,18 +872,54 @@ static inline void tcg_out_pop(TCGContext *s, int reg) tcg_out_opc(s, OPC_POP_r32 + LOWREGMASK(reg), 0, reg, 0); } -static inline void tcg_out_ld(TCGContext *s, TCGType type, TCGReg ret, - TCGReg arg1, intptr_t arg2) +static void tcg_out_ld(TCGContext *s, TCGType type, TCGReg ret, + TCGReg arg1, intptr_t arg2) { - int opc = OPC_MOVL_GvEv + (type == TCG_TYPE_I64 ? P_REXW : 0); - tcg_out_modrm_offset(s, opc, ret, arg1, arg2); + switch (type) { + case TCG_TYPE_I64: + tcg_out_modrm_offset(s, OPC_MOVL_GvEv | P_REXW, ret, arg1, arg2); + break; + case TCG_TYPE_I32: + tcg_out_modrm_offset(s, OPC_MOVL_GvEv, ret, arg1, arg2); + break; + case TCG_TYPE_V64: + tcg_out_maybe_vex_modrm_offset(s, OPC_MOVQ_GyMy, ret, arg1, arg2); + break; + case TCG_TYPE_V128: + tcg_out_maybe_vex_modrm_offset(s, OPC_MOVDQU_GyMy, ret, arg1, arg2); + break; + case TCG_TYPE_V256: + tcg_out_vex_modrm_offset(s, OPC_MOVDQU_GyMy | P_VEXL, + ret, 0, arg1, arg2); + break; + default: + g_assert_not_reached(); + } } -static inline void tcg_out_st(TCGContext *s, TCGType type, TCGReg arg, - TCGReg arg1, intptr_t arg2) +static void tcg_out_st(TCGContext *s, TCGType type, TCGReg arg, + TCGReg arg1, intptr_t arg2) { - int opc = OPC_MOVL_EvGv + (type == TCG_TYPE_I64 ? P_REXW : 0); - tcg_out_modrm_offset(s, opc, arg, arg1, arg2); + switch (type) { + case TCG_TYPE_I64: + tcg_out_modrm_offset(s, OPC_MOVL_EvGv | P_REXW, arg, arg1, arg2); + break; + case TCG_TYPE_I32: + tcg_out_modrm_offset(s, OPC_MOVL_EvGv, arg, arg1, arg2); + break; + case TCG_TYPE_V64: + tcg_out_maybe_vex_modrm_offset(s, OPC_MOVQ_MyGy, arg, arg1, arg2); + break; + case TCG_TYPE_V128: + tcg_out_maybe_vex_modrm_offset(s, OPC_MOVDQU_MyGy, arg, arg1, arg2); + break; + case TCG_TYPE_V256: + tcg_out_vex_modrm_offset(s, OPC_MOVDQU_MyGy | P_VEXL, + arg, 0, arg1, arg2); + break; + default: + g_assert_not_reached(); + } } static bool tcg_out_sti(TCGContext *s, TCGType type, TCGArg val, @@ -773,6 +931,8 @@ static bool tcg_out_sti(TCGContext *s, TCGType type, TCGArg val, return false; } rexw = P_REXW; + } else if (type != TCG_TYPE_I32) { + return false; } tcg_out_modrm_offset(s, OPC_MOVL_EvIz | rexw, 0, base, ofs); tcg_out32(s, val); @@ -1914,6 +2074,15 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, case glue(glue(INDEX_op_, x), _i32) #endif +#define OP_128_256(x) \ + case glue(glue(INDEX_op_, x), _v256): \ + rexw = P_VEXL; /* FALLTHRU */ \ + case glue(glue(INDEX_op_, x), _v128) + +#define OP_64_128_256(x) \ + OP_128_256(x): \ + case glue(glue(INDEX_op_, x), _v64) + /* Hoist the loads of the most common arguments. */ a0 = args[0]; a1 = args[1]; @@ -2379,19 +2548,94 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, } break; + OP_64_128_256(add8): + c = OPC_PADDB; + goto gen_simd; + OP_64_128_256(add16): + c = OPC_PADDW; + goto gen_simd; + OP_64_128_256(add32): + c = OPC_PADDD; + goto gen_simd; + OP_128_256(add64): + c = OPC_PADDQ; + goto gen_simd; + OP_64_128_256(sub8): + c = OPC_PSUBB; + goto gen_simd; + OP_64_128_256(sub16): + c = OPC_PSUBW; + goto gen_simd; + OP_64_128_256(sub32): + c = OPC_PSUBD; + goto gen_simd; + OP_128_256(sub64): + c = OPC_PSUBQ; + goto gen_simd; + OP_64_128_256(and): + c = OPC_PAND; + goto gen_simd; + OP_64_128_256(andc): + c = OPC_PANDN; + goto gen_simd; + OP_64_128_256(or): + c = OPC_POR; + goto gen_simd; + OP_64_128_256(xor): + c = OPC_PXOR; + gen_simd: + if (have_avx1) { + tcg_out_vex_modrm(s, c, a0, a1, a2); + } else { + tcg_out_modrm(s, c, a0, a2); + } + break; + + case INDEX_op_ld_v64: + c = TCG_TYPE_V64; + goto gen_simd_ld; + case INDEX_op_ld_v128: + c = TCG_TYPE_V128; + goto gen_simd_ld; + case INDEX_op_ld_v256: + c = TCG_TYPE_V256; + gen_simd_ld: + tcg_out_ld(s, c, a0, a1, a2); + break; + + case INDEX_op_st_v64: + c = TCG_TYPE_V64; + goto gen_simd_st; + case INDEX_op_st_v128: + c = TCG_TYPE_V128; + goto gen_simd_st; + case INDEX_op_st_v256: + c = TCG_TYPE_V256; + gen_simd_st: + tcg_out_st(s, c, a0, a1, a2); + break; + case INDEX_op_mb: tcg_out_mb(s, a0); break; case INDEX_op_mov_i32: /* Always emitted via tcg_out_mov. */ case INDEX_op_mov_i64: + case INDEX_op_mov_v64: + case INDEX_op_mov_v128: + case INDEX_op_mov_v256: case INDEX_op_movi_i32: /* Always emitted via tcg_out_movi. */ case INDEX_op_movi_i64: + case INDEX_op_movi_v64: + case INDEX_op_movi_v128: + case INDEX_op_movi_v256: case INDEX_op_call: /* Always emitted via tcg_out_call. */ default: tcg_abort(); } #undef OP_32_64 +#undef OP_128_256 +#undef OP_64_128_256 } static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op) @@ -2417,6 +2661,9 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op) = { .args_ct_str = { "r", "r", "L", "L" } }; static const TCGTargetOpDef L_L_L_L = { .args_ct_str = { "L", "L", "L", "L" } }; + static const TCGTargetOpDef x_0_x = { .args_ct_str = { "x", "0", "x" } }; + static const TCGTargetOpDef x_x_x = { .args_ct_str = { "x", "x", "x" } }; + static const TCGTargetOpDef x_r = { .args_ct_str = { "x", "r" } }; switch (op) { case INDEX_op_goto_ptr: @@ -2620,6 +2867,52 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op) return &s2; } + case INDEX_op_ld_v64: + case INDEX_op_ld_v128: + case INDEX_op_ld_v256: + case INDEX_op_st_v64: + case INDEX_op_st_v128: + case INDEX_op_st_v256: + return &x_r; + + case INDEX_op_add8_v64: + case INDEX_op_add8_v128: + case INDEX_op_add16_v64: + case INDEX_op_add16_v128: + case INDEX_op_add32_v64: + case INDEX_op_add32_v128: + case INDEX_op_add64_v128: + case INDEX_op_sub8_v64: + case INDEX_op_sub8_v128: + case INDEX_op_sub16_v64: + case INDEX_op_sub16_v128: + case INDEX_op_sub32_v64: + case INDEX_op_sub32_v128: + case INDEX_op_sub64_v128: + case INDEX_op_and_v64: + case INDEX_op_and_v128: + case INDEX_op_andc_v64: + case INDEX_op_andc_v128: + case INDEX_op_or_v64: + case INDEX_op_or_v128: + case INDEX_op_xor_v64: + case INDEX_op_xor_v128: + return have_avx1 ? &x_x_x : &x_0_x; + + case INDEX_op_add8_v256: + case INDEX_op_add16_v256: + case INDEX_op_add32_v256: + case INDEX_op_add64_v256: + case INDEX_op_sub8_v256: + case INDEX_op_sub16_v256: + case INDEX_op_sub32_v256: + case INDEX_op_sub64_v256: + case INDEX_op_and_v256: + case INDEX_op_andc_v256: + case INDEX_op_or_v256: + case INDEX_op_xor_v256: + return &x_x_x; + default: break; } @@ -2725,9 +3018,16 @@ static void tcg_out_nop_fill(tcg_insn_unit *p, int count) static void tcg_target_init(TCGContext *s) { #ifdef CONFIG_CPUID_H - unsigned a, b, c, d; + unsigned a, b, c, d, b7 = 0; int max = __get_cpuid_max(0, 0); + if (max >= 7) { + /* BMI1 is available on AMD Piledriver and Intel Haswell CPUs. */ + __cpuid_count(7, 0, a, b7, c, d); + have_bmi1 = (b7 & bit_BMI) != 0; + have_bmi2 = (b7 & bit_BMI2) != 0; + } + if (max >= 1) { __cpuid(1, a, b, c, d); #ifndef have_cmov @@ -2736,17 +3036,26 @@ static void tcg_target_init(TCGContext *s) available, we'll use a small forward branch. */ have_cmov = (d & bit_CMOV) != 0; #endif +#ifndef have_sse2 + have_sse2 = (d & bit_SSE2) != 0; +#endif /* MOVBE is only available on Intel Atom and Haswell CPUs, so we need to probe for it. */ have_movbe = (c & bit_MOVBE) != 0; have_popcnt = (c & bit_POPCNT) != 0; - } - if (max >= 7) { - /* BMI1 is available on AMD Piledriver and Intel Haswell CPUs. */ - __cpuid_count(7, 0, a, b, c, d); - have_bmi1 = (b & bit_BMI) != 0; - have_bmi2 = (b & bit_BMI2) != 0; +#ifndef have_avx2 + /* There are a number of things we must check before we can be + sure of not hitting invalid opcode. */ + if (c & bit_OSXSAVE) { + unsigned xcrl, xcrh; + asm ("xgetbv" : "=a" (xcrl), "=d" (xcrh) : "c" (0)); + if (xcrl & 6 == 6) { + have_avx1 = (c & bit_AVX) != 0; + have_avx2 = (b7 & bit_AVX2) != 0; + } + } +#endif } max = __get_cpuid_max(0x8000000, 0); @@ -2763,6 +3072,13 @@ static void tcg_target_init(TCGContext *s) } else { tcg_regset_set32(tcg_target_available_regs[TCG_TYPE_I32], 0, 0xff); } + if (have_sse2) { + tcg_regset_set32(tcg_target_available_regs[TCG_TYPE_V64], 0, 0xff0000); + tcg_regset_set32(tcg_target_available_regs[TCG_TYPE_V128], 0, 0xff0000); + } + if (have_avx2) { + tcg_regset_set32(tcg_target_available_regs[TCG_TYPE_V256], 0, 0xff0000); + } tcg_regset_clear(tcg_target_call_clobber_regs); tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_EAX); -- 2.13.5 From MAILER-DAEMON Thu Aug 17 19:44:58 2017 Received: from list by lists.gnu.org with archive (Exim 4.71) id 1diUTC-0006c1-3L for mharc-qemu-arm@gnu.org; Thu, 17 Aug 2017 19:44:58 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:52515) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1diUT9-0006b3-2s for qemu-arm@nongnu.org; Thu, 17 Aug 2017 19:44:56 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1diUT5-0005K4-VX for qemu-arm@nongnu.org; Thu, 17 Aug 2017 19:44:55 -0400 Received: from mail-qt0-x243.google.com ([2607:f8b0:400d:c0d::243]:34402) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1diUT5-0005Jp-Pv; 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Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.2.1 MIME-Version: 1.0 In-Reply-To: <20170817230114.3655-6-richard.henderson@linaro.org> Content-Type: text/plain; charset=utf-8; format=flowed Content-Language: en-US Content-Transfer-Encoding: 8bit X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400d:c0d::243 Subject: Re: [Qemu-arm] [Qemu-devel] [PATCH 5/8] tcg: Add tcg_op_supported X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 17 Aug 2017 23:44:56 -0000 On 08/17/2017 08:01 PM, Richard Henderson wrote: > Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daudé > --- > tcg/tcg.h | 2 + > tcg/tcg.c | 310 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > 2 files changed, 312 insertions(+) > > diff --git a/tcg/tcg.h b/tcg/tcg.h > index b9e15da13b..b443143b21 100644 > --- a/tcg/tcg.h > +++ b/tcg/tcg.h > @@ -962,6 +962,8 @@ do {\ > #define tcg_temp_free_ptr(T) tcg_temp_free_i64(TCGV_PTR_TO_NAT(T)) > #endif > > +bool tcg_op_supported(TCGOpcode op); > + > void tcg_gen_callN(TCGContext *s, void *func, > TCGArg ret, int nargs, TCGArg *args); > > diff --git a/tcg/tcg.c b/tcg/tcg.c > index ea78d47fad..3c3cdda938 100644 > --- a/tcg/tcg.c > +++ b/tcg/tcg.c > @@ -751,6 +751,316 @@ int tcg_check_temp_count(void) > } > #endif > > +/* Return true if OP may appear in the opcode stream. > + Test the runtime variable that controls each opcode. */ > +bool tcg_op_supported(TCGOpcode op) > +{ > + switch (op) { > + case INDEX_op_discard: > + case INDEX_op_set_label: > + case INDEX_op_call: > + case INDEX_op_br: > + case INDEX_op_mb: > + case INDEX_op_insn_start: > + case INDEX_op_exit_tb: > + case INDEX_op_goto_tb: > + case INDEX_op_qemu_ld_i32: > + case INDEX_op_qemu_st_i32: > + case INDEX_op_qemu_ld_i64: > + case INDEX_op_qemu_st_i64: > + return true; > + > + case INDEX_op_goto_ptr: > + return TCG_TARGET_HAS_goto_ptr; > + > + case INDEX_op_mov_i32: > + case INDEX_op_movi_i32: > + case INDEX_op_setcond_i32: > + case INDEX_op_brcond_i32: > + case INDEX_op_ld8u_i32: > + case INDEX_op_ld8s_i32: > + case INDEX_op_ld16u_i32: > + case INDEX_op_ld16s_i32: > + case INDEX_op_ld_i32: > + case INDEX_op_st8_i32: > + case INDEX_op_st16_i32: > + case INDEX_op_st_i32: > + case INDEX_op_add_i32: > + case INDEX_op_sub_i32: > + case INDEX_op_mul_i32: > + case INDEX_op_and_i32: > + case INDEX_op_or_i32: > + case INDEX_op_xor_i32: > + case INDEX_op_shl_i32: > + case INDEX_op_shr_i32: > + case INDEX_op_sar_i32: > + return true; > + > + case INDEX_op_movcond_i32: > + return TCG_TARGET_HAS_movcond_i32; > + case INDEX_op_div_i32: > + case INDEX_op_divu_i32: > + return TCG_TARGET_HAS_div_i32; > + case INDEX_op_rem_i32: > + case INDEX_op_remu_i32: > + return TCG_TARGET_HAS_rem_i32; > + case INDEX_op_div2_i32: > + case INDEX_op_divu2_i32: > + return TCG_TARGET_HAS_div2_i32; > + case INDEX_op_rotl_i32: > + case INDEX_op_rotr_i32: > + return TCG_TARGET_HAS_rot_i32; > + case INDEX_op_deposit_i32: > + return TCG_TARGET_HAS_deposit_i32; > + case INDEX_op_extract_i32: > + return TCG_TARGET_HAS_extract_i32; > + case INDEX_op_sextract_i32: > + return TCG_TARGET_HAS_sextract_i32; > + case INDEX_op_add2_i32: > + return TCG_TARGET_HAS_add2_i32; > + case INDEX_op_sub2_i32: > + return TCG_TARGET_HAS_sub2_i32; > + case INDEX_op_mulu2_i32: > + return TCG_TARGET_HAS_mulu2_i32; > + case INDEX_op_muls2_i32: > + return TCG_TARGET_HAS_muls2_i32; > + case INDEX_op_muluh_i32: > + return TCG_TARGET_HAS_muluh_i32; > + case INDEX_op_mulsh_i32: > + return TCG_TARGET_HAS_mulsh_i32; > + case INDEX_op_ext8s_i32: > + return TCG_TARGET_HAS_ext8s_i32; > + case INDEX_op_ext16s_i32: > + return TCG_TARGET_HAS_ext16s_i32; > + case INDEX_op_ext8u_i32: > + return TCG_TARGET_HAS_ext8u_i32; > + case INDEX_op_ext16u_i32: > + return TCG_TARGET_HAS_ext16u_i32; > + case INDEX_op_bswap16_i32: > + return TCG_TARGET_HAS_bswap16_i32; > + case INDEX_op_bswap32_i32: > + return TCG_TARGET_HAS_bswap32_i32; > + case INDEX_op_not_i32: > + return TCG_TARGET_HAS_not_i32; > + case INDEX_op_neg_i32: > + return TCG_TARGET_HAS_neg_i32; > + case INDEX_op_andc_i32: > + return TCG_TARGET_HAS_andc_i32; > + case INDEX_op_orc_i32: > + return TCG_TARGET_HAS_orc_i32; > + case INDEX_op_eqv_i32: > + return TCG_TARGET_HAS_eqv_i32; > + case INDEX_op_nand_i32: > + return TCG_TARGET_HAS_nand_i32; > + case INDEX_op_nor_i32: > + return TCG_TARGET_HAS_nor_i32; > + case INDEX_op_clz_i32: > + return TCG_TARGET_HAS_clz_i32; > + case INDEX_op_ctz_i32: > + return TCG_TARGET_HAS_ctz_i32; > + case INDEX_op_ctpop_i32: > + return TCG_TARGET_HAS_ctpop_i32; > + > + case INDEX_op_brcond2_i32: > + case INDEX_op_setcond2_i32: > + return TCG_TARGET_REG_BITS == 32; > + > + case INDEX_op_mov_i64: > + case INDEX_op_movi_i64: > + case INDEX_op_setcond_i64: > + case INDEX_op_brcond_i64: > + case INDEX_op_ld8u_i64: > + case INDEX_op_ld8s_i64: > + case INDEX_op_ld16u_i64: > + case INDEX_op_ld16s_i64: > + case INDEX_op_ld32u_i64: > + case INDEX_op_ld32s_i64: > + case INDEX_op_ld_i64: > + case INDEX_op_st8_i64: > + case INDEX_op_st16_i64: > + case INDEX_op_st32_i64: > + case INDEX_op_st_i64: > + case INDEX_op_add_i64: > + case INDEX_op_sub_i64: > + case INDEX_op_mul_i64: > + case INDEX_op_and_i64: > + case INDEX_op_or_i64: > + case INDEX_op_xor_i64: > + case INDEX_op_shl_i64: > + case INDEX_op_shr_i64: > + case INDEX_op_sar_i64: > + case INDEX_op_ext_i32_i64: > + case INDEX_op_extu_i32_i64: > + return TCG_TARGET_REG_BITS == 64; > + > + case INDEX_op_movcond_i64: > + return TCG_TARGET_HAS_movcond_i64; > + case INDEX_op_div_i64: > + case INDEX_op_divu_i64: > + return TCG_TARGET_HAS_div_i64; > + case INDEX_op_rem_i64: > + case INDEX_op_remu_i64: > + return TCG_TARGET_HAS_rem_i64; > + case INDEX_op_div2_i64: > + case INDEX_op_divu2_i64: > + return TCG_TARGET_HAS_div2_i64; > + case INDEX_op_rotl_i64: > + case INDEX_op_rotr_i64: > + return TCG_TARGET_HAS_rot_i64; > + case INDEX_op_deposit_i64: > + return TCG_TARGET_HAS_deposit_i64; > + case INDEX_op_extract_i64: > + return TCG_TARGET_HAS_extract_i64; > + case INDEX_op_sextract_i64: > + return TCG_TARGET_HAS_sextract_i64; > + case INDEX_op_extrl_i64_i32: > + return TCG_TARGET_HAS_extrl_i64_i32; > + case INDEX_op_extrh_i64_i32: > + return TCG_TARGET_HAS_extrh_i64_i32; > + case INDEX_op_ext8s_i64: > + return TCG_TARGET_HAS_ext8s_i64; > + case INDEX_op_ext16s_i64: > + return TCG_TARGET_HAS_ext16s_i64; > + case INDEX_op_ext32s_i64: > + return TCG_TARGET_HAS_ext32s_i64; > + case INDEX_op_ext8u_i64: > + return TCG_TARGET_HAS_ext8u_i64; > + case INDEX_op_ext16u_i64: > + return TCG_TARGET_HAS_ext16u_i64; > + case INDEX_op_ext32u_i64: > + return TCG_TARGET_HAS_ext32u_i64; > + case INDEX_op_bswap16_i64: > + return TCG_TARGET_HAS_bswap16_i64; > + case INDEX_op_bswap32_i64: > + return TCG_TARGET_HAS_bswap32_i64; > + case INDEX_op_bswap64_i64: > + return TCG_TARGET_HAS_bswap64_i64; > + case INDEX_op_not_i64: > + return TCG_TARGET_HAS_not_i64; > + case INDEX_op_neg_i64: > + return TCG_TARGET_HAS_neg_i64; > + case INDEX_op_andc_i64: > + return TCG_TARGET_HAS_andc_i64; > + case INDEX_op_orc_i64: > + return TCG_TARGET_HAS_orc_i64; > + case INDEX_op_eqv_i64: > + return TCG_TARGET_HAS_eqv_i64; > + case INDEX_op_nand_i64: > + return TCG_TARGET_HAS_nand_i64; > + case INDEX_op_nor_i64: > + return TCG_TARGET_HAS_nor_i64; > + case INDEX_op_clz_i64: > + return TCG_TARGET_HAS_clz_i64; > + case INDEX_op_ctz_i64: > + return TCG_TARGET_HAS_ctz_i64; > + case INDEX_op_ctpop_i64: > + return TCG_TARGET_HAS_ctpop_i64; > + case INDEX_op_add2_i64: > + return TCG_TARGET_HAS_add2_i64; > + case INDEX_op_sub2_i64: > + return TCG_TARGET_HAS_sub2_i64; > + case INDEX_op_mulu2_i64: > + return TCG_TARGET_HAS_mulu2_i64; > + case INDEX_op_muls2_i64: > + return TCG_TARGET_HAS_muls2_i64; > + case INDEX_op_muluh_i64: > + return TCG_TARGET_HAS_muluh_i64; > + case INDEX_op_mulsh_i64: > + return TCG_TARGET_HAS_mulsh_i64; > + > + case INDEX_op_mov_v64: > + case INDEX_op_movi_v64: > + case INDEX_op_ld_v64: > + case INDEX_op_st_v64: > + case INDEX_op_and_v64: > + case INDEX_op_or_v64: > + case INDEX_op_xor_v64: > + case INDEX_op_add8_v64: > + case INDEX_op_add16_v64: > + case INDEX_op_add32_v64: > + case INDEX_op_sub8_v64: > + case INDEX_op_sub16_v64: > + case INDEX_op_sub32_v64: > + return TCG_TARGET_HAS_v64; > + > + case INDEX_op_mov_v128: > + case INDEX_op_movi_v128: > + case INDEX_op_ld_v128: > + case INDEX_op_st_v128: > + case INDEX_op_and_v128: > + case INDEX_op_or_v128: > + case INDEX_op_xor_v128: > + case INDEX_op_add8_v128: > + case INDEX_op_add16_v128: > + case INDEX_op_add32_v128: > + case INDEX_op_add64_v128: > + case INDEX_op_sub8_v128: > + case INDEX_op_sub16_v128: > + case INDEX_op_sub32_v128: > + case INDEX_op_sub64_v128: > + return TCG_TARGET_HAS_v128; > + > + case INDEX_op_mov_v256: > + case INDEX_op_movi_v256: > + case INDEX_op_ld_v256: > + case INDEX_op_st_v256: > + case INDEX_op_and_v256: > + case INDEX_op_or_v256: > + case INDEX_op_xor_v256: > + case INDEX_op_add8_v256: > + case INDEX_op_add16_v256: > + case INDEX_op_add32_v256: > + case INDEX_op_add64_v256: > + case INDEX_op_sub8_v256: > + case INDEX_op_sub16_v256: > + case INDEX_op_sub32_v256: > + case INDEX_op_sub64_v256: > + return TCG_TARGET_HAS_v256; > + > + case INDEX_op_not_v64: > + return TCG_TARGET_HAS_not_v64; > + case INDEX_op_not_v128: > + return TCG_TARGET_HAS_not_v128; > + case INDEX_op_not_v256: > + return TCG_TARGET_HAS_not_v256; > + > + case INDEX_op_andc_v64: > + return TCG_TARGET_HAS_andc_v64; > + case INDEX_op_andc_v128: > + return TCG_TARGET_HAS_andc_v128; > + case INDEX_op_andc_v256: > + return TCG_TARGET_HAS_andc_v256; > + > + case INDEX_op_orc_v64: > + return TCG_TARGET_HAS_orc_v64; > + case INDEX_op_orc_v128: > + return TCG_TARGET_HAS_orc_v128; > + case INDEX_op_orc_v256: > + return TCG_TARGET_HAS_orc_v256; > + > + case INDEX_op_neg8_v64: > + case INDEX_op_neg16_v64: > + case INDEX_op_neg32_v64: > + return TCG_TARGET_HAS_neg_v64; > + > + case INDEX_op_neg8_v128: > + case INDEX_op_neg16_v128: > + case INDEX_op_neg32_v128: > + case INDEX_op_neg64_v128: > + return TCG_TARGET_HAS_neg_v128; > + > + case INDEX_op_neg8_v256: > + case INDEX_op_neg16_v256: > + case INDEX_op_neg32_v256: > + case INDEX_op_neg64_v256: > + return TCG_TARGET_HAS_neg_v256; > + > + case NB_OPS: > + break; > + } > + g_assert_not_reached(); > +} > + > /* Note: we convert the 64 bit args to 32 bit and do some alignment > and endian swap. Maybe it would be better to do the alignment > and endian swap in tcg_reg_alloc_call(). */ > From MAILER-DAEMON Thu Aug 17 19:45:52 2017 Received: from list by lists.gnu.org with archive (Exim 4.71) id 1diUU4-0007TL-9C for mharc-qemu-arm@gnu.org; Thu, 17 Aug 2017 19:45:52 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:52792) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1diUTz-0007Oy-Ez for qemu-arm@nongnu.org; Thu, 17 Aug 2017 19:45:51 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1diUTu-0005hs-P3 for qemu-arm@nongnu.org; Thu, 17 Aug 2017 19:45:47 -0400 Received: from mail-qt0-x244.google.com ([2607:f8b0:400d:c0d::244]:36364) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1diUTu-0005hk-GP; Thu, 17 Aug 2017 19:45:42 -0400 Received: by mail-qt0-x244.google.com with SMTP id c15so7639151qta.3; Thu, 17 Aug 2017 16:45:42 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:subject:to:cc:references:from:message-id:date:user-agent :mime-version:in-reply-to:content-language:content-transfer-encoding; bh=ZEEQ47zfaPuiBrxCSaBInTnQ1hZGhTIHMrShOgK1XZ8=; b=JXhIx3c4PKN5ODcR42ChTap7MWFUZHbgP+UciWO7429zOVsYTBXnD0EB0FY2KNaDEx J4GoRlgskY5vzBSlFcnKrCopYChZadX4LzMjr7g5ZIOaVXBqe4G1tqn1xQXOkWNDlOq0 wl1Tq++Uo2Ig0EjVvKqNz5pcyFUQWyN+jcLjWgNKZdZutWMqQTrDUFAAui8cl9Nbg3WN 71b0yT5bnGvx/UKYfE45Gbzb4VAITuWpeLx7G0PpAUA1YiC/3l6vAEhGq77VQ5zKo3jb y1pWQ/r++3mFY05XaQGZzViO006QN+OMmwKkVbBMP7UFRkg1ZXdrlYeUIwm9/aAS6lck TmlQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:subject:to:cc:references:from:message-id :date:user-agent:mime-version:in-reply-to:content-language :content-transfer-encoding; bh=ZEEQ47zfaPuiBrxCSaBInTnQ1hZGhTIHMrShOgK1XZ8=; b=fLerN6qlTDI9HaiY+RYYJTfrBA89ElvqMoLD+iIV0A/qaXakObbJwvaloVjBSpUPq5 fu9hhcBs+PSYVoXLlBQE0n1gJf66iwXdxD77B/vu0Erg6Sf861XUdMSWJnJAYO68vQ8W 40AkY5ntlvQlqMRh6WANdZKU9vFsEkxBr1fEULIs96A7/MgT+E+/Sd5lUQkvotLuNnEp r5E4RTRGh23RzkzIF6ziGTeuWVHUZfIveX08/AW/u7QuCLysxXoiXcstE1r47LBJJ/i8 pPCm3cONrDzxdLmhpf7NV8IVnggxJrYOoS735pNsXduV/3apGcxwpNG+9gR+tj+SJMTI 19Dg== X-Gm-Message-State: AHYfb5hWluYmMC4+nclmQNZemAwIQBoxEk5/ML/EU6TukY0dHwfZzz+e 5PSplLbL95sl4Q== X-Received: by 10.237.32.172 with SMTP id 41mr10535765qtb.260.1503013541921; Thu, 17 Aug 2017 16:45:41 -0700 (PDT) Received: from [192.168.1.10] ([181.93.89.178]) by smtp.gmail.com with ESMTPSA id d50sm3143893qtd.37.2017.08.17.16.45.39 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 17 Aug 2017 16:45:41 -0700 (PDT) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= To: Richard Henderson , qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, alex.bennee@linaro.org References: <20170817230114.3655-1-richard.henderson@linaro.org> <20170817230114.3655-7-richard.henderson@linaro.org> From: =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= Message-ID: Date: Thu, 17 Aug 2017 20:45:38 -0300 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.2.1 MIME-Version: 1.0 In-Reply-To: <20170817230114.3655-7-richard.henderson@linaro.org> Content-Type: text/plain; charset=utf-8; format=flowed Content-Language: en-US Content-Transfer-Encoding: 8bit X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400d:c0d::244 Subject: Re: [Qemu-arm] [Qemu-devel] [PATCH 6/8] tcg: Add INDEX_op_invalid X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 17 Aug 2017 23:45:51 -0000 On 08/17/2017 08:01 PM, Richard Henderson wrote: > Add with value 0 so that structure zero initialization can > indicate that the field is not present. > > Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daudé > --- > tcg/tcg-opc.h | 2 ++ > tcg/tcg.c | 3 +++ > 2 files changed, 5 insertions(+) > > diff --git a/tcg/tcg-opc.h b/tcg/tcg-opc.h > index 9162125fac..b1445a4c24 100644 > --- a/tcg/tcg-opc.h > +++ b/tcg/tcg-opc.h > @@ -26,6 +26,8 @@ > * DEF(name, oargs, iargs, cargs, flags) > */ > > +DEF(invalid, 0, 0, 0, TCG_OPF_NOT_PRESENT) > + > /* predefined ops */ > DEF(discard, 1, 0, 0, TCG_OPF_NOT_PRESENT) > DEF(set_label, 0, 0, 1, TCG_OPF_BB_END | TCG_OPF_NOT_PRESENT) > diff --git a/tcg/tcg.c b/tcg/tcg.c > index 3c3cdda938..879b29e81f 100644 > --- a/tcg/tcg.c > +++ b/tcg/tcg.c > @@ -756,6 +756,9 @@ int tcg_check_temp_count(void) > bool tcg_op_supported(TCGOpcode op) > { > switch (op) { > + case INDEX_op_invalid: > + return false; > + > case INDEX_op_discard: > case INDEX_op_set_label: > case INDEX_op_call: > From MAILER-DAEMON Thu Aug 17 19:46:48 2017 Received: from list by lists.gnu.org with archive (Exim 4.71) id 1diUUy-0008DY-2D for mharc-qemu-arm@gnu.org; Thu, 17 Aug 2017 19:46:48 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:52974) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1diUUv-0008BG-Jk for qemu-arm@nongnu.org; Thu, 17 Aug 2017 19:46:46 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1diUUq-0006Oj-VI for qemu-arm@nongnu.org; Thu, 17 Aug 2017 19:46:45 -0400 Received: from mail-qt0-x241.google.com ([2607:f8b0:400d:c0d::241]:38801) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1diUUq-0006Od-Qs; Thu, 17 Aug 2017 19:46:40 -0400 Received: by mail-qt0-x241.google.com with SMTP id p3so7603046qtg.5; Thu, 17 Aug 2017 16:46:40 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:subject:to:cc:references:from:message-id:date:user-agent :mime-version:in-reply-to:content-language:content-transfer-encoding; bh=mqi8s9rIvj8jdm9aO/Jh/c7H3U4oGlTCXoBQZ+vgfUw=; b=qzm6ds9bMmtKeJWkbyTHfBmI6MrQRVRGaWsiB26EvuU2VvPuvAi78AyaM9JH8lR+JR d8r+xLWWPgOyQVvv+J8fOVUENMOWneIeMTJhSREDJ+XOInOq9yEu8yFPtSnbRcmvnODz OSgP2SRohQwwBvC0HFsgG6YEgrkCBhiLEphnp4qG5F3Ryt9vglVWlVObIQZdfYGJUmXI st2wahb20vogIORwDuixnOl9WAsAYdVW4d6GiPdfiMPGRmvka1qEFqQxqISekrNrw6iW KLA0qz+GcAMHTXSdTPd4d4uIaqFFW7G5Ua1u70vLjoO1cDSuSFNq20+sUuQJAHnRKpqf F1Ag== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:subject:to:cc:references:from:message-id :date:user-agent:mime-version:in-reply-to:content-language :content-transfer-encoding; bh=mqi8s9rIvj8jdm9aO/Jh/c7H3U4oGlTCXoBQZ+vgfUw=; b=Zf6Fbh394LBzcSuihzOUq8tp4ANZInwWvb21PjosQ1VccFdVlGk9OQpT2zWJc4As6o WLbBrpZNhQkfciAvvnrh81J5ttGod2pqlBzX7+7j5E38gN4JoFuIlo9mB2SDEKIUvmMd +y3tKmP+qVSSHlkzZIFAdQH4WZkjXlxL5SbPNVSPRSi37gP5r48I9LLyo8I0XMzFbkLW 3jOZCViUVuSfnyXBH6CT/SevnH1Lezkg7p66aVhqLPKTIyGmAH92FGRmPJn5WogmBhU/ GGEZ1Js0p5ruWs/QdzguQsD+EXVVUHYlWUWnKQQtD4os3/0FW6TnD1wkOWlI482GoGNH pmNA== X-Gm-Message-State: AHYfb5geH4oCiQE+tWnJx0Zs+HFP/i8s8OFSRUGzbHHr0+0IYObb/x8o M856XM/cFcdRHA== X-Received: by 10.200.50.151 with SMTP id z23mr9830899qta.140.1503013600268; Thu, 17 Aug 2017 16:46:40 -0700 (PDT) Received: from [192.168.1.10] ([181.93.89.178]) by smtp.gmail.com with ESMTPSA id f17sm3214956qka.14.2017.08.17.16.46.37 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 17 Aug 2017 16:46:39 -0700 (PDT) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= To: Richard Henderson , qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, alex.bennee@linaro.org References: <20170817230114.3655-1-richard.henderson@linaro.org> <20170817230114.3655-4-richard.henderson@linaro.org> From: =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= Message-ID: <9ceed03c-896b-a947-0736-3ee108bec7a3@amsat.org> Date: Thu, 17 Aug 2017 20:46:36 -0300 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.2.1 MIME-Version: 1.0 In-Reply-To: <20170817230114.3655-4-richard.henderson@linaro.org> Content-Type: text/plain; charset=utf-8; format=flowed Content-Language: en-US Content-Transfer-Encoding: 8bit X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400d:c0d::241 Subject: Re: [Qemu-arm] [Qemu-devel] [PATCH 3/8] tcg: Add types for host vectors X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 17 Aug 2017 23:46:46 -0000 On 08/17/2017 08:01 PM, Richard Henderson wrote: > Nothing uses or enables them yet. > > Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daudé > --- > tcg/tcg.h | 5 +++++ > tcg/tcg.c | 2 +- > 2 files changed, 6 insertions(+), 1 deletion(-) > > diff --git a/tcg/tcg.h b/tcg/tcg.h > index dd97095af5..1277caed3d 100644 > --- a/tcg/tcg.h > +++ b/tcg/tcg.h > @@ -256,6 +256,11 @@ typedef struct TCGPool { > typedef enum TCGType { > TCG_TYPE_I32, > TCG_TYPE_I64, > + > + TCG_TYPE_V64, > + TCG_TYPE_V128, > + TCG_TYPE_V256, > + > TCG_TYPE_COUNT, /* number of different types */ > > /* An alias for the size of the host register. */ > diff --git a/tcg/tcg.c b/tcg/tcg.c > index 787c8ba0f7..ea78d47fad 100644 > --- a/tcg/tcg.c > +++ b/tcg/tcg.c > @@ -118,7 +118,7 @@ static TCGReg tcg_reg_alloc_new(TCGContext *s, TCGType t) > static bool tcg_out_ldst_finalize(TCGContext *s); > #endif > > -static TCGRegSet tcg_target_available_regs[2]; > +static TCGRegSet tcg_target_available_regs[TCG_TYPE_COUNT]; > static TCGRegSet tcg_target_call_clobber_regs; > > #if TCG_TARGET_INSN_UNIT_SIZE == 1 > From MAILER-DAEMON Fri Aug 18 00:50:05 2017 Received: from list by lists.gnu.org with archive (Exim 4.71) id 1diZET-00041a-9L for mharc-qemu-arm@gnu.org; Fri, 18 Aug 2017 00:50:05 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:42668) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1diZEP-0003yA-Go for qemu-arm@nongnu.org; Fri, 18 Aug 2017 00:50:03 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1diZEM-0000v7-8t for qemu-arm@nongnu.org; Fri, 18 Aug 2017 00:50:01 -0400 Received: from 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Fri, 18 Aug 2017 09:28:19 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:48005) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1difXB-0006xx-Qs for qemu-arm@nongnu.org; Fri, 18 Aug 2017 07:33:51 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1difX6-0002Go-TO for qemu-arm@nongnu.org; Fri, 18 Aug 2017 07:33:49 -0400 Received: from bran.ispras.ru ([83.149.199.196]:55923 helo=smtp.ispras.ru) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1difX6-0002GB-DZ; Fri, 18 Aug 2017 07:33:44 -0400 Received: from bulbul.intra.ispras.ru (bulbul.intra.ispras.ru [10.10.3.51]) by smtp.ispras.ru (Postfix) with ESMTP id 3F3BE5FB2D; Fri, 18 Aug 2017 14:33:42 +0300 (MSK) Date: Fri, 18 Aug 2017 14:33:42 +0300 (MSK) From: Kirill Batuzov To: =?ISO-8859-15?Q?Alex_Benn=E9e?= cc: rth@twiddle.net, cota@braap.org, qemu-devel@nongnu.org, qemu-arm@nongnu.org In-Reply-To: <20170817180404.29334-1-alex.bennee@linaro.org> Message-ID: References: <20170817180404.29334-1-alex.bennee@linaro.org> User-Agent: Alpine 2.20 (DEB 67 2015-01-07) MIME-Version: 1.0 Content-Type: multipart/mixed; BOUNDARY="8323329-1194898619-1503056022=:2770" X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [fuzzy] X-Received-From: 83.149.199.196 X-Mailman-Approved-At: Fri, 18 Aug 2017 09:28:18 -0400 Subject: Re: [Qemu-arm] [RFC PATCH 0/9] TCG Vector types and example conversion X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 18 Aug 2017 11:33:51 -0000 This message is in MIME format. The first part should be readable text, while the remaining parts are likely unreadable without MIME-aware tools. --8323329-1194898619-1503056022=:2770 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable On Thu, 17 Aug 2017, Alex Benn=C3=A9e wrote: > Hi, >=20 > With upcoming work on SVE I've been looking at the way we implement > vector registers in QEMU's TCG. The current orthodoxy is to decompose > the vector into a series of TCG registers, often calling a helper > function the calculation of each element. The result of the helper is > then is then stored back in the vector representation afterwards. > There are occasional outliers like simd_tbl which access elements > directly from a passed CPUFooState env pointer but these are rare. >=20 > This series introduces the concept of TCGv_vec type. This is a pointer > to the start of the in memory representation of an arbitrarily long > vector register. This is passed to a helper function as a pointer > along with a normal TCG register containing information about the > actual vector length and any additional information the helper needs > to do the operation. The hope* is this saves on the churn of having > the TCG do things element by element and allows the compiler to use > native vector operations to streamline the helpers. >=20 > There are some downsides to this approach. The first is you have to be > careful about register aliasing. If you are doing a same reg to same > reg operation you need to make a copy of the vector so you don't > trample your input data as you go. The second is this involves > changing some of the assumptions the TCG makes about things. I've > managed to keep all the changes within the core TCG code for now but > so far it has only been tested for the tcg_call path which is the only > place where TCGv_vec's should turn up. It is possible to do the same > thing without touching the TCG code generation by using TCGv_ptrs and > manually emitting tcg_addi ops to pass the correct address. Richard > has been exploring this approach with his series. The downside of that > is you do miss the ability to have named global vector registers which > makes reading the TCG dumps a little easier. >=20 > I've only patched one helper in this series which implements the > indexed smull. This is because it appears in the profiles for my test > case which was using an arm64 ffmpeg to transcode: >=20 > ./ffmpeg.arm64 -i big_buck_bunny_480p_surround-fix.avi \ > -threads 1 -qscale:v 3 -f null - >=20 > * hope. On an earlier revision (which included sqshrn conversions) I > had measured a minor saving but this had disappeared once I measured > the final code. However the profile is fairly dominated by > softfloat. >=20 > master: > 8.05% qemu-aarch64 qemu-aarch64 [.] roundAndPackFloa= t32 > 7.28% qemu-aarch64 qemu-aarch64 [.] float32_mul > 6.56% qemu-aarch64 qemu-aarch64 [.] helper_lookup_tb= _ptr > 5.31% qemu-aarch64 qemu-aarch64 [.] float32_muladd > 4.09% qemu-aarch64 qemu-aarch64 [.] helper_neon_mull= _s16 > 4.00% qemu-aarch64 qemu-aarch64 [.] addFloat32Sigs > 3.86% qemu-aarch64 qemu-aarch64 [.] subFloat32Sigs > 2.26% qemu-aarch64 qemu-aarch64 [.] helper_simd_tbl > 2.00% qemu-aarch64 qemu-aarch64 [.] float32_add > 1.81% qemu-aarch64 qemu-aarch64 [.] helper_neon_unar= row_sat8 > 1.64% qemu-aarch64 qemu-aarch64 [.] float32_sub > 1.43% qemu-aarch64 qemu-aarch64 [.] helper_neon_subl= _u32 > 0.98% qemu-aarch64 qemu-aarch64 [.] helper_neon_wide= n_u8 >=20 > tcg-native-vectors-rfc: > 7.93% qemu-aarch64 qemu-aarch64 [.] roundAndPackFloa= t32 =20 > 7.54% qemu-aarch64 qemu-aarch64 [.] float32_mul = =20 > 6.29% qemu-aarch64 qemu-aarch64 [.] helper_lookup_tb= _ptr > 5.39% qemu-aarch64 qemu-aarch64 [.] float32_muladd > 3.92% qemu-aarch64 qemu-aarch64 [.] addFloat32Sigs > 3.86% qemu-aarch64 qemu-aarch64 [.] subFloat32Sigs > 3.62% qemu-aarch64 qemu-aarch64 [.] helper_advsimd_s= mull_idx_s32 > 2.19% qemu-aarch64 qemu-aarch64 [.] helper_simd_tbl > 2.09% qemu-aarch64 qemu-aarch64 [.] helper_neon_mull= _s16 > 1.99% qemu-aarch64 qemu-aarch64 [.] float32_add > 1.79% qemu-aarch64 qemu-aarch64 [.] helper_neon_unar= row_sat8 > 1.62% qemu-aarch64 qemu-aarch64 [.] float32_sub > 1.43% qemu-aarch64 qemu-aarch64 [.] helper_neon_subl= _u32 > 1.00% qemu-aarch64 qemu-aarch64 [.] helper_neon_wide= n_u8 > 0.98% qemu-aarch64 qemu-aarch64 [.] helper_neon_addl= _u32 >=20 > At the moment the default compiler settings don't actually vectorise > the helper. I could get it to once I added some alignment guarantees > but the casting I did broke the instruction emulation so I haven't > included that patch in this series. >=20 > Given the results why continue investigating this? Well for one thing > vector sizes are growing, SVE vectors are up to 2048 bits long. Those > longer vectors should offer more scope for the host compiler to > generate efficient code in the helper. Also vector operations tend to > be quite complex operations, being able to handle this in C code > instead of TCGOps might be more preferable from a code maintainability > point of view. Finally this noddy little experiment has at least shown > it doesn't worsen performance. It would be nice if I could find a > benchmark that made heavy use if non-floating point SIMD instructions > to better measure the effect of marshalling elements vs vectorised > helpers. If anyone has any suggestions I'm all ears ;-) While doing my own vector register series I was using 1. Handwritten example (it's for ARM32 NEON, not aarch64) .cpu cortex-a8 .fpu neon .text .global test test: vld1.32 d0, [r0]! vld1.32 d1, [r0] vld1.32 d2, [r1]! vld1.32 d3, [r1] mov r0, #0xb0000000 loop: vadd.i32 q0, q0, q1 vadd.i32 q0, q0, q1 vadd.i32 q0, q0, q1 vadd.i32 q0, q0, q1 subs r0, r0, #1 bne loop vpadd.i32 d0, d0, d1 vpadd.i32 d0, d0, d1 vmov.i32 r0, d0[0] bx lr It can be adapted for aarch64 without much problems. This example shows what potential speed up you can expect, as it is nearly perfect for the optimization in question. 2. x264 video encoder. It has a lot of handwritten vector assembler for different architectures, including aarch64. You probably can access it as libx264 from within ffmpeg, if this library support was compiled. >=20 > Anyway questions, comments? >=20 >From my own experimentations some times ago, (1) translating vector instructions to vector instructions in TCG is fast= er than (2) translating vector instructions to series of scalar instructions in T= CG, which is faster than* (3) translating vector instructions to single helper calls, which is fast= er than* (4) translating vector instructions to helper calls for each vector eleme= nt. (*) (2) and (3) may change their respective places in case of some complicated instructions. ARM (at least ARM32, I have not checked aarch64 in this regard) uses the last, the slowest scheme. As far as I understand, you are want to change it to the third approach. This approach is used in SSE emulation, may be you can use similar structure of helpers? I still hope to finish my own series about implementation of the first approach. I apologize for the long delay since last update and hope to send next version somewhere next week. I do not think our series contradict each other: you are trying to optimize existing general purpose case while I'm trying to optimize case where both host and guest support vector instructions. Since I'm experimenting on ARM32, we'll not have much merge conflicts either. --=20 Kirill --8323329-1194898619-1503056022=:2770-- From MAILER-DAEMON Fri Aug 18 09:44:53 2017 Received: from list by lists.gnu.org with archive (Exim 4.71) id 1diha1-0003oF-NB for mharc-qemu-arm@gnu.org; Fri, 18 Aug 2017 09:44:53 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:47172) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dihZz-0003m9-3L for qemu-arm@nongnu.org; Fri, 18 Aug 2017 09:44:52 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dihZw-0002rX-0g for qemu-arm@nongnu.org; Fri, 18 Aug 2017 09:44:51 -0400 Received: from mail-pg0-x230.google.com ([2607:f8b0:400e:c05::230]:33064) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1dihZv-0002r1-RE for qemu-arm@nongnu.org; Fri, 18 Aug 2017 09:44:47 -0400 Received: by mail-pg0-x230.google.com with SMTP id t3so36769368pgt.0 for ; Fri, 18 Aug 2017 06:44:47 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=subject:to:cc:references:from:message-id:date:user-agent :mime-version:in-reply-to:content-language:content-transfer-encoding; bh=LAXbl6vJrxKFg/WkSAAzUGQfM83DBWo4wPymsHvm8f8=; b=OkkAoClCUcOMMz9ekIv2xfkAwDTzHm3boWFTltat5NXb+Z3zAc3PdvqYNTVred1Kb6 kLgYD1BL8v1y4OF9bnQh/aWj7qwvpZXb4hW8pNEPc6RaBzvZLz+3Xt9w8pjtBG6XIqok k/VdYsYUprWulotWU4XEgcsgfsyLoUIpiMa6M= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:subject:to:cc:references:from:message-id:date :user-agent:mime-version:in-reply-to:content-language :content-transfer-encoding; bh=LAXbl6vJrxKFg/WkSAAzUGQfM83DBWo4wPymsHvm8f8=; b=Fhe67W4IlEWGR1w/lAKQzzw6SXiltphQklJtEY1llzRSViW7ycXnNneLqusHRIYIc1 Oetu4KM5KXjCbG7upsCdvXRPMzsA1AKtsNwG6utCO/hMepTjwRHv7f/VfQ7xDlngjKjF FyOZDVG4E1CmcuNTCuxeQSeFzzBI4F+NOb/x2h0DfoexDJPgKhO9/ZvpQi0hY3wVRqZV Hxy2h/GyZE37hBKdCzYpHWqsaWEssKjs+mz+MPLVZ4+RJ1QRH+cwgMH0pb5iYuCt3XDM 9lKyoZuzG/THz6Pxpdie7Y9xILGOMF3RDcQ5z7OiHYugSrS38iI7yykAPEPEobY2rzYg PHRg== X-Gm-Message-State: AHYfb5heCGwqh3aL1NrpwWnywXsKxWT04Vuime7Wq5tLAHJSEz1EL0FE shPncfj1eROm7tLo X-Received: by 10.84.167.2 with SMTP id c2mr9714426plb.371.1503063886810; Fri, 18 Aug 2017 06:44:46 -0700 (PDT) Received: from bigtime.twiddle.net (97-126-108-236.tukw.qwest.net. [97.126.108.236]) by smtp.gmail.com with ESMTPSA id 65sm9961340pgj.23.2017.08.18.06.44.45 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 18 Aug 2017 06:44:45 -0700 (PDT) To: Kirill Batuzov , =?UTF-8?Q?Alex_Benn=c3=a9e?= Cc: cota@braap.org, qemu-devel@nongnu.org, qemu-arm@nongnu.org, rth@twiddle.net References: <20170817180404.29334-1-alex.bennee@linaro.org> From: Richard Henderson Message-ID: <64af762a-5d2b-5e33-fc8e-18244b0c6586@linaro.org> Date: Fri, 18 Aug 2017 06:44:44 -0700 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.2.1 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 7bit X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::230 Subject: Re: [Qemu-arm] [Qemu-devel] [RFC PATCH 0/9] TCG Vector types and example conversion X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 18 Aug 2017 13:44:52 -0000 On 08/18/2017 04:33 AM, Kirill Batuzov wrote: > From my own experimentations some times ago, > > (1) translating vector instructions to vector instructions in TCG is faster than > > (2) translating vector instructions to series of scalar instructions in TCG, > which is faster than* > > (3) translating vector instructions to single helper calls, which is faster > than* > > (4) translating vector instructions to helper calls for each vector element. > > (*) (2) and (3) may change their respective places in case of some > complicated instructions. This was my gut feeling as well. With the caveat that for the ARM SVE case of 2048-bit registers we cannot afford to expand inline due to generated code size. > ARM (at least ARM32, I have not checked aarch64 in this regard) uses the > last, the slowest scheme. As far as I understand, you are want to change > it to the third approach. This approach is used in SSE emulation, may be > you can use similar structure of helpers? > > I still hope to finish my own series about implementation of the first > approach. I apologize for the long delay since last update and hope to > send next version somewhere next week. I do not think our series > contradict each other: you are trying to optimize existing general > purpose case while I'm trying to optimize case where both host and guest > support vector instructions. Since I'm experimenting on ARM32, we'll not > have much merge conflicts either. I posted my own, different, take on vectorization yesterday as well. http://lists.nongnu.org/archive/html/qemu-devel/2017-08/msg03272.html The primary difference between my version and your version is that I do not allow target/cpu/translate*.c to create vector types. All of the host vector expansion is done within tcg/*.c. We also would like to settle on a common style for out-of-line helpers, if that is possible. One thing *not* to take from our current SSE emulation is that we do not yet support AVX, AVX2, or AVX512 extensions. So the current construction of helpers within target/i386/ doesn't really take into account all that should be required. The thing that's common between AVX512 and SVE is that we have multiple vector lengths, and that elements beyond the operation length are zeroed. Both Alex and I have packed operation length + full vector length into a descriptor given to the helper. (Alex allows for some other bits too; I'm not sure about that.) r~ From MAILER-DAEMON Fri Aug 18 10:02:05 2017 Received: from list by lists.gnu.org with archive (Exim 4.71) id 1dihqe-00048m-VQ for mharc-qemu-arm@gnu.org; Fri, 18 Aug 2017 10:02:05 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:51485) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dihqY-00043h-17 for qemu-arm@nongnu.org; Fri, 18 Aug 2017 10:02:02 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dihqW-0008RZ-JQ for qemu-arm@nongnu.org; Fri, 18 Aug 2017 10:01:58 -0400 Received: from szxga05-in.huawei.com ([45.249.212.191]:2235) by eggs.gnu.org with esmtps (TLS1.0:RSA_ARCFOUR_SHA1:16) (Exim 4.71) (envelope-from ) id 1dihqV-0008OJ-Mg; Fri, 18 Aug 2017 10:01:56 -0400 Received: from 172.30.72.58 (EHLO DGGEMS411-HUB.china.huawei.com) ([172.30.72.58]) by dggrg05-dlp.huawei.com (MOS 4.4.6-GA FastPath queued) with ESMTP id DFM74410; Fri, 18 Aug 2017 22:00:48 +0800 (CST) Received: from linux.huawei.com (10.67.187.203) by DGGEMS411-HUB.china.huawei.com (10.3.19.211) with Microsoft SMTP Server id 14.3.301.0; Fri, 18 Aug 2017 22:00:12 +0800 From: Dongjiu Geng To: , , , , , , , , , , , , , , , , , , , , , , , , , , , , CC: , , , , Date: Fri, 18 Aug 2017 22:23:42 +0800 Message-ID: <1503066227-18251-2-git-send-email-gengdongjiu@huawei.com> X-Mailer: git-send-email 1.7.7 In-Reply-To: <1503066227-18251-1-git-send-email-gengdongjiu@huawei.com> References: <1503066227-18251-1-git-send-email-gengdongjiu@huawei.com> MIME-Version: 1.0 Content-Type: text/plain X-Originating-IP: [10.67.187.203] X-CFilter-Loop: Reflected X-Mirapoint-Virus-RAPID-Raw: score=unknown(0), refid=str=0001.0A020201.5996F310.0190, ss=1, re=0.000, recu=0.000, reip=0.000, cl=1, cld=1, fgs=0, ip=0.0.0.0, so=2014-11-16 11:51:01, dmn=2013-03-21 17:37:32 X-Mirapoint-Loop-Id: d6bd547ab7138c2865427ea05fc33ed4 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.4.x-2.6.x [generic] [fuzzy] X-Received-From: 45.249.212.191 Subject: [Qemu-arm] [PATCH v11 1/6] ACPI: add APEI/HEST/CPER structures and macros X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 18 Aug 2017 14:02:02 -0000 (1) Add related APEI/HEST table structures and macros, these definition refer to ACPI 6.1 and UEFI 2.6 spec. (2) Add generic error status block and CPER memory section definition, user space only handle memory section errors. Signed-off-by: Dongjiu Geng --- include/hw/acpi/acpi-defs.h | 193 ++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 193 insertions(+) diff --git a/include/hw/acpi/acpi-defs.h b/include/hw/acpi/acpi-defs.h index 72be675..3b4bad7 100644 --- a/include/hw/acpi/acpi-defs.h +++ b/include/hw/acpi/acpi-defs.h @@ -297,6 +297,44 @@ typedef struct AcpiMultipleApicTable AcpiMultipleApicTable; #define ACPI_APIC_GENERIC_TRANSLATOR 15 #define ACPI_APIC_RESERVED 16 /* 16 and greater are reserved */ +/* UEFI Spec 2.6, "N.2.5 Memory Error Section */ +#define UEFI_CPER_MEM_VALID_ERROR_STATUS 0x0001 +#define UEFI_CPER_MEM_VALID_PA 0x0002 +#define UEFI_CPER_MEM_VALID_PA_MASK 0x0004 +#define UEFI_CPER_MEM_VALID_NODE 0x0008 +#define UEFI_CPER_MEM_VALID_CARD 0x0010 +#define UEFI_CPER_MEM_VALID_MODULE 0x0020 +#define UEFI_CPER_MEM_VALID_BANK 0x0040 +#define UEFI_CPER_MEM_VALID_DEVICE 0x0080 +#define UEFI_CPER_MEM_VALID_ROW 0x0100 +#define UEFI_CPER_MEM_VALID_COLUMN 0x0200 +#define UEFI_CPER_MEM_VALID_BIT_POSITION 0x0400 +#define UEFI_CPER_MEM_VALID_REQUESTOR 0x0800 +#define UEFI_CPER_MEM_VALID_RESPONDER 0x1000 +#define UEFI_CPER_MEM_VALID_TARGET 0x2000 +#define UEFI_CPER_MEM_VALID_ERROR_TYPE 0x4000 +#define UEFI_CPER_MEM_VALID_RANK_NUMBER 0x8000 +#define UEFI_CPER_MEM_VALID_CARD_HANDLE 0x10000 +#define UEFI_CPER_MEM_VALID_MODULE_HANDLE 0x20000 +#define UEFI_CPER_MEM_ERROR_TYPE_MULTI_ECC 3 + +/* From the ACPI 6.1 spec, "18.3.2.9 Hardware Error Notification" */ + +enum AcpiHestNotifyType { + ACPI_HEST_NOTIFY_POLLED = 0, + ACPI_HEST_NOTIFY_EXTERNAL = 1, + ACPI_HEST_NOTIFY_LOCAL = 2, + ACPI_HEST_NOTIFY_SCI = 3, + ACPI_HEST_NOTIFY_NMI = 4, + ACPI_HEST_NOTIFY_CMCI = 5, /* ACPI 5.0 */ + ACPI_HEST_NOTIFY_MCE = 6, /* ACPI 5.0 */ + ACPI_HEST_NOTIFY_GPIO = 7, /* ACPI 6.0 */ + ACPI_HEST_NOTIFY_SEA = 8, /* ACPI 6.1 */ + ACPI_HEST_NOTIFY_SEI = 9, /* ACPI 6.1 */ + ACPI_HEST_NOTIFY_GSIV = 10, /* ACPI 6.1 */ + ACPI_HEST_NOTIFY_RESERVED = 11 /* 11 and greater are reserved */ +}; + /* * MADT sub-structures (Follow MULTIPLE_APIC_DESCRIPTION_TABLE) */ @@ -474,6 +512,161 @@ struct AcpiSystemResourceAffinityTable { } QEMU_PACKED; typedef struct AcpiSystemResourceAffinityTable AcpiSystemResourceAffinityTable; +/* Hardware Error Notification, from the ACPI 6.1 + * spec, "18.3.2.9 Hardware Error Notification" + */ +struct AcpiHestNotify { + uint8_t type; + uint8_t length; + uint16_t config_write_enable; + uint32_t poll_interval; + uint32_t vector; + uint32_t polling_threshold_value; + uint32_t polling_threshold_window; + uint32_t error_threshold_value; + uint32_t error_threshold_window; +} QEMU_PACKED; +typedef struct AcpiHestNotify AcpiHestNotify; + +/* From ACPI 6.1, sections "18.3.2.1 IA-32 Architecture Machine + * Check Exception" through "18.3.2.8 Generic Hardware Error Source version 2". + */ +enum AcpiHestSourceType { + ACPI_HEST_SOURCE_IA32_CHECK = 0, + ACPI_HEST_SOURCE_IA32_CORRECTED_CHECK = 1, + ACPI_HEST_SOURCE_IA32_NMI = 2, + ACPI_HEST_SOURCE_AER_ROOT_PORT = 6, + ACPI_HEST_SOURCE_AER_ENDPOINT = 7, + ACPI_HEST_SOURCE_AER_BRIDGE = 8, + ACPI_HEST_SOURCE_GENERIC_ERROR = 9, + ACPI_HEST_SOURCE_GENERIC_ERROR_V2 = 10, + ACPI_HEST_SOURCE_RESERVED = 11 /* 11 and greater are reserved */ +}; + +/* Block status bitmasks from ACPI 6.1, "18.3.2.7.1 Generic Error Data" */ +#define ACPI_GEBS_UNCORRECTABLE (1) +#define ACPI_GEBS_CORRECTABLE (1 << 1) +#define ACPI_GEBS_MULTIPLE_UNCORRECTABLE (1 << 2) +#define ACPI_GEBS_MULTIPLE_CORRECTABLE (1 << 3) +/* 10 bits, error data entry count */ +#define ACPI_GEBS_ERROR_ENTRY_COUNT (0x3FF << 4) + +/* Generic Hardware Error Source Structure, refer to ACPI 6.1 + * "18.3.2.7 Generic Hardware Error Source". in this struct the + * "type" field has to be ACPI_HEST_SOURCE_GENERIC_ERROR + */ + +struct AcpiGenericHardwareErrorSource { + uint16_t type; + uint16_t source_id; + uint16_t related_source_id; + uint8_t flags; + uint8_t enabled; + uint32_t number_of_records; + uint32_t max_sections_per_record; + uint32_t max_raw_data_length; + struct AcpiGenericAddress error_status_address; + struct AcpiHestNotify notify; + uint32_t error_status_block_length; +} QEMU_PACKED; +typedef struct AcpiGenericHardwareErrorSource AcpiGenericHardwareErrorSource; + +/* Generic Hardware Error Source, version 2, ACPI 6.1, "18.3.2.8 Generic + * Hardware Error Source version 2", in this struct the "type" field has to + * be ACPI_HEST_SOURCE_GENERIC_ERROR_V2 + */ +struct AcpiGenericHardwareErrorSourceV2 { + uint16_t type; + uint16_t source_id; + uint16_t related_source_id; + uint8_t flags; + uint8_t enabled; + uint32_t number_of_records; + uint32_t max_sections_per_record; + uint32_t max_raw_data_length; + struct AcpiGenericAddress error_status_address; + struct AcpiHestNotify notify; + uint32_t error_status_block_length; + struct AcpiGenericAddress read_ack_register; + uint64_t read_ack_preserve; + uint64_t read_ack_write; +} QEMU_PACKED; +typedef struct AcpiGenericHardwareErrorSourceV2 + AcpiGenericHardwareErrorSourceV2; + +/* Generic Error Status block, from ACPI 6.1, + * "18.3.2.7.1 Generic Error Data" + */ +struct AcpiGenericErrorStatus { + /* It is a bitmask composed of ACPI_GEBS_xxx macros */ + uint32_t block_status; + uint32_t raw_data_offset; + uint32_t raw_data_length; + uint32_t data_length; + uint32_t error_severity; +} QEMU_PACKED; +typedef struct AcpiGenericErrorStatus AcpiGenericErrorStatus; + +enum AcpiGenericErrorSeverity { + ACPI_CPER_SEV_RECOVERABLE, + ACPI_CPER_SEV_FATAL, + ACPI_CPER_SEV_CORRECTED, + ACPI_CPER_SEV_NONE, +}; + +/* Generic Error Data entry, revision number is 0x0300, + * ACPI 6.1, "18.3.2.7.1 Generic Error Data" + */ +struct AcpiGenericErrorData { + uint8_t section_type_le[16]; + /* The "error_severity" fields that they take their + * values from AcpiGenericErrorSeverity + */ + uint32_t error_severity; + uint16_t revision; + uint8_t validation_bits; + uint8_t flags; + uint32_t error_data_length; + uint8_t fru_id[16]; + uint8_t fru_text[20]; + uint64_t time_stamp; +} QEMU_PACKED; +typedef struct AcpiGenericErrorData AcpiGenericErrorData; + +/* From UEFI 2.6, "N.2.5 Memory Error Section" */ +struct UefiCperSecMemErr { + uint64_t validation_bits; + uint64_t error_status; + uint64_t physical_addr; + uint64_t physical_addr_mask; + uint16_t node; + uint16_t card; + uint16_t module; + uint16_t bank; + uint16_t device; + uint16_t row; + uint16_t column; + uint16_t bit_pos; + uint64_t requestor_id; + uint64_t responder_id; + uint64_t target_id; + uint8_t error_type; + uint8_t reserved; + uint16_t rank; + uint16_t mem_array_handle; /* card handle in UEFI 2.4 */ + uint16_t mem_dev_handle; /* module handle in UEFI 2.4 */ +} QEMU_PACKED; +typedef struct UefiCperSecMemErr UefiCperSecMemErr; + +/* + * HEST Description Table + */ +struct AcpiHardwareErrorSourceTable { + ACPI_TABLE_HEADER_DEF /* ACPI common table header */ + uint32_t error_source_count; +} QEMU_PACKED; +typedef struct AcpiHardwareErrorSourceTable AcpiHardwareErrorSourceTable; + #define ACPI_SRAT_PROCESSOR_APIC 0 #define ACPI_SRAT_MEMORY 1 #define ACPI_SRAT_PROCESSOR_x2APIC 2 -- 1.8.3.1 From MAILER-DAEMON Fri Aug 18 10:02:06 2017 Received: from list by lists.gnu.org with archive (Exim 4.71) id 1dihqg-0004AB-4o for mharc-qemu-arm@gnu.org; Fri, 18 Aug 2017 10:02:06 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:51492) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dihqY-000441-Ep for qemu-arm@nongnu.org; Fri, 18 Aug 2017 10:02:03 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dihqX-0008S6-EE for qemu-arm@nongnu.org; Fri, 18 Aug 2017 10:01:58 -0400 Received: from szxga05-in.huawei.com ([45.249.212.191]:2234) by eggs.gnu.org with esmtps (TLS1.0:RSA_ARCFOUR_SHA1:16) (Exim 4.71) (envelope-from ) id 1dihqW-0008Nn-RQ; Fri, 18 Aug 2017 10:01:57 -0400 Received: from 172.30.72.58 (EHLO DGGEMS411-HUB.china.huawei.com) ([172.30.72.58]) by dggrg05-dlp.huawei.com (MOS 4.4.6-GA FastPath queued) with ESMTP id DFM74404; Fri, 18 Aug 2017 22:00:47 +0800 (CST) Received: from linux.huawei.com (10.67.187.203) by DGGEMS411-HUB.china.huawei.com (10.3.19.211) with Microsoft SMTP Server id 14.3.301.0; Fri, 18 Aug 2017 22:00:13 +0800 From: Dongjiu Geng To: , , , , , , , , , , , , , , , , , , , , , , , , , , , , CC: , , , , Date: Fri, 18 Aug 2017 22:23:45 +0800 Message-ID: <1503066227-18251-5-git-send-email-gengdongjiu@huawei.com> X-Mailer: git-send-email 1.7.7 In-Reply-To: <1503066227-18251-1-git-send-email-gengdongjiu@huawei.com> References: <1503066227-18251-1-git-send-email-gengdongjiu@huawei.com> MIME-Version: 1.0 Content-Type: text/plain X-Originating-IP: [10.67.187.203] X-CFilter-Loop: Reflected X-Mirapoint-Virus-RAPID-Raw: score=unknown(0), refid=str=0001.0A020201.5996F30F.02DB, ss=1, re=0.000, recu=0.000, reip=0.000, cl=1, cld=1, fgs=0, ip=0.0.0.0, so=2014-11-16 11:51:01, dmn=2013-03-21 17:37:32 X-Mirapoint-Loop-Id: 888d5f8d1e081f94f5dc4a02f078723a X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.4.x-2.6.x [generic] [fuzzy] X-Received-From: 45.249.212.191 Subject: [Qemu-arm] [PATCH v11 4/6] target-arm: kvm64: detect guest RAS EXTENSION feature X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 18 Aug 2017 14:02:03 -0000 check if kvm supports guest RAS EXTENSION. if so, set corresponding feature bit for vcpu. Signed-off-by: Dongjiu Geng --- linux-headers/linux/kvm.h | 1 + target/arm/cpu.h | 3 +++ target/arm/kvm64.c | 8 ++++++++ 3 files changed, 12 insertions(+) diff --git a/linux-headers/linux/kvm.h b/linux-headers/linux/kvm.h index 7971a4f..2aa176e 100644 --- a/linux-headers/linux/kvm.h +++ b/linux-headers/linux/kvm.h @@ -929,6 +929,7 @@ struct kvm_ppc_resize_hpt { #define KVM_CAP_PPC_SMT_POSSIBLE 147 #define KVM_CAP_HYPERV_SYNIC2 148 #define KVM_CAP_HYPERV_VP_INDEX 149 +#define KVM_CAP_ARM_RAS_EXTENSION 150 #ifdef KVM_CAP_IRQ_ROUTING diff --git a/target/arm/cpu.h b/target/arm/cpu.h index b39d64a..6b0961b 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -611,6 +611,8 @@ struct ARMCPU { /* CPU has memory protection unit */ bool has_mpu; + /* CPU has ras extension unit */ + bool has_ras_extension; /* PMSAv7 MPU number of supported regions */ uint32_t pmsav7_dregion; @@ -1229,6 +1231,7 @@ enum arm_features { ARM_FEATURE_THUMB_DSP, /* DSP insns supported in the Thumb encodings */ ARM_FEATURE_PMU, /* has PMU support */ ARM_FEATURE_VBAR, /* has cp15 VBAR */ + ARM_FEATURE_RAS_EXTENSION, /*has RAS extension support */ }; static inline int arm_feature(CPUARMState *env, int feature) diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c index a16abc8..0781367 100644 --- a/target/arm/kvm64.c +++ b/target/arm/kvm64.c @@ -518,6 +518,14 @@ int kvm_arch_init_vcpu(CPUState *cs) unset_feature(&env->features, ARM_FEATURE_PMU); } + if (kvm_check_extension(cs->kvm_state, KVM_CAP_ARM_RAS_EXTENSION)) { + cpu->has_ras_extension = true; + set_feature(&env->features, ARM_FEATURE_RAS_EXTENSION); + } else { + cpu->has_ras_extension = false; + unset_feature(&env->features, ARM_FEATURE_RAS_EXTENSION); + } + /* Do KVM_ARM_VCPU_INIT ioctl */ ret = kvm_arm_vcpu_init(cs); if (ret) { -- 1.8.3.1 From MAILER-DAEMON Fri Aug 18 10:02:06 2017 Received: from list by lists.gnu.org with archive (Exim 4.71) id 1dihqg-0004AM-AO for mharc-qemu-arm@gnu.org; Fri, 18 Aug 2017 10:02:06 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:51512) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dihqb-00045m-87 for qemu-arm@nongnu.org; Fri, 18 Aug 2017 10:02:03 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dihqX-0008SE-Gu for qemu-arm@nongnu.org; Fri, 18 Aug 2017 10:02:01 -0400 Received: from szxga05-in.huawei.com ([45.249.212.191]:2236) by eggs.gnu.org with esmtps (TLS1.0:RSA_ARCFOUR_SHA1:16) (Exim 4.71) (envelope-from ) id 1dihqW-0008QT-Tv; Fri, 18 Aug 2017 10:01:57 -0400 Received: from 172.30.72.58 (EHLO DGGEMS411-HUB.china.huawei.com) ([172.30.72.58]) by dggrg05-dlp.huawei.com (MOS 4.4.6-GA FastPath queued) with ESMTP id DFM74401; Fri, 18 Aug 2017 22:00:47 +0800 (CST) Received: from linux.huawei.com (10.67.187.203) by DGGEMS411-HUB.china.huawei.com (10.3.19.211) with Microsoft SMTP Server id 14.3.301.0; Fri, 18 Aug 2017 22:00:13 +0800 From: Dongjiu Geng To: , , , , , , , , , , , , , , , , , , , , , , , , , , , , CC: , , , , Date: Fri, 18 Aug 2017 22:23:44 +0800 Message-ID: <1503066227-18251-4-git-send-email-gengdongjiu@huawei.com> X-Mailer: git-send-email 1.7.7 In-Reply-To: <1503066227-18251-1-git-send-email-gengdongjiu@huawei.com> References: <1503066227-18251-1-git-send-email-gengdongjiu@huawei.com> MIME-Version: 1.0 Content-Type: text/plain X-Originating-IP: [10.67.187.203] X-CFilter-Loop: Reflected X-Mirapoint-Virus-RAPID-Raw: score=unknown(0), refid=str=0001.0A020201.5996F30F.0212, ss=1, re=0.000, recu=0.000, reip=0.000, cl=1, cld=1, fgs=0, ip=0.0.0.0, so=2014-11-16 11:51:01, dmn=2013-03-21 17:37:32 X-Mirapoint-Loop-Id: 42727865dfb62d32f4afad31125f8e15 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.4.x-2.6.x [generic] [fuzzy] X-Received-From: 45.249.212.191 Subject: [Qemu-arm] [PATCH v11 3/6] ACPI: build and enable APEI GHES in the Makefile and configuration X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 18 Aug 2017 14:02:03 -0000 Add CONFIG_ACPI_APEI configuration in the Makefile and enable it in the arm-softmmu.mak Signed-off-by: Dongjiu Geng --- default-configs/arm-softmmu.mak | 1 + hw/acpi/Makefile.objs | 1 + 2 files changed, 2 insertions(+) diff --git a/default-configs/arm-softmmu.mak b/default-configs/arm-softmmu.mak index bbdd3c1..c362113 100644 --- a/default-configs/arm-softmmu.mak +++ b/default-configs/arm-softmmu.mak @@ -129,3 +129,4 @@ CONFIG_ACPI=y CONFIG_SMBIOS=y CONFIG_ASPEED_SOC=y CONFIG_GPIO_KEY=y +CONFIG_ACPI_APEI=y diff --git a/hw/acpi/Makefile.objs b/hw/acpi/Makefile.objs index 11c35bc..bafb148 100644 --- a/hw/acpi/Makefile.objs +++ b/hw/acpi/Makefile.objs @@ -6,6 +6,7 @@ common-obj-$(CONFIG_ACPI_MEMORY_HOTPLUG) += memory_hotplug.o common-obj-$(CONFIG_ACPI_CPU_HOTPLUG) += cpu.o common-obj-$(CONFIG_ACPI_NVDIMM) += nvdimm.o common-obj-$(CONFIG_ACPI_VMGENID) += vmgenid.o +common-obj-$(CONFIG_ACPI_APEI) += hest_ghes.o common-obj-$(call lnot,$(CONFIG_ACPI_X86)) += acpi-stub.o common-obj-y += acpi_interface.o -- 1.8.3.1 From MAILER-DAEMON Fri Aug 18 10:02:13 2017 Received: from list by lists.gnu.org with archive (Exim 4.71) id 1dihqi-0004CB-3b for mharc-qemu-arm@gnu.org; Fri, 18 Aug 2017 10:02:11 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:51565) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dihqf-00049X-G7 for qemu-arm@nongnu.org; Fri, 18 Aug 2017 10:02:06 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dihqZ-0008Tm-B5 for qemu-arm@nongnu.org; Fri, 18 Aug 2017 10:02:05 -0400 Received: from szxga05-in.huawei.com ([45.249.212.191]:2237) by eggs.gnu.org with esmtps (TLS1.0:RSA_ARCFOUR_SHA1:16) (Exim 4.71) (envelope-from ) id 1dihqY-0008RQ-HQ; Fri, 18 Aug 2017 10:01:59 -0400 Received: from 172.30.72.58 (EHLO DGGEMS411-HUB.china.huawei.com) ([172.30.72.58]) by dggrg05-dlp.huawei.com (MOS 4.4.6-GA FastPath queued) with ESMTP id DFM74412; Fri, 18 Aug 2017 22:00:48 +0800 (CST) Received: from linux.huawei.com (10.67.187.203) by DGGEMS411-HUB.china.huawei.com (10.3.19.211) with Microsoft SMTP Server id 14.3.301.0; Fri, 18 Aug 2017 22:00:14 +0800 From: Dongjiu Geng To: , , , , , , , , , , , , , , , , , , , , , , , , , , , , CC: , , , , Date: Fri, 18 Aug 2017 22:23:47 +0800 Message-ID: <1503066227-18251-7-git-send-email-gengdongjiu@huawei.com> X-Mailer: git-send-email 1.7.7 In-Reply-To: <1503066227-18251-1-git-send-email-gengdongjiu@huawei.com> References: <1503066227-18251-1-git-send-email-gengdongjiu@huawei.com> MIME-Version: 1.0 Content-Type: text/plain X-Originating-IP: [10.67.187.203] X-CFilter-Loop: Reflected X-Mirapoint-Virus-RAPID-Raw: score=unknown(0), refid=str=0001.0A0B0207.5996F310.019D, ss=1, re=0.000, recu=0.000, reip=0.000, cl=1, cld=1, fgs=0, ip=0.0.0.0, so=2014-11-16 11:51:01, dmn=2013-03-21 17:37:32 X-Mirapoint-Loop-Id: a2fc3c2d8f4dd5ae8c41d992041e0951 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.4.x-2.6.x [generic] [fuzzy] X-Received-From: 45.249.212.191 Subject: [Qemu-arm] [PATCH v11 6/6] target-arm: kvm64: Handle SError interrupt for the guest OS X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 18 Aug 2017 14:02:06 -0000 When guest OS happens SError interrupt(SEI), it will trap to host. Host firstly calls memory failure to deal with this error and decide whether it needs to deliver SIGBUS signal to userspace. The advantage that using signal to notify is that it can make the notification method is general, non-KVM user can also use it. when userspace gets this signal and knows this is SError interrupt, it will translate the delivered host VA to PA and record this PA to GHES. Because ARMv8.2 adds an extension to RAS to allow system software insert implicit Error Synchronization Barrier operations to isolate the error and allow passes specified syndrome to guest OS, so after record the CPER, user space calls IOCTL to pass a specified syndrome to KVM, then switch to guest OS, guest OS can use the recorded CPER record and syndrome information to do the recovery. The steps are shown below: 1. translate the host VA to guest OS PA and record this error PA to HEST table. 2. set specified virtual SError syndrome and pass the value to KVM. Signed-off-by: Dongjiu Geng Signed-off-by: Quanming Wu --- linux-headers/linux/kvm.h | 1 + target/arm/internals.h | 1 + target/arm/kvm64.c | 28 ++++++++++++++++++++++++++++ 3 files changed, 30 insertions(+) diff --git a/linux-headers/linux/kvm.h b/linux-headers/linux/kvm.h index 2aa176e..10dfcab 100644 --- a/linux-headers/linux/kvm.h +++ b/linux-headers/linux/kvm.h @@ -1356,6 +1356,7 @@ struct kvm_s390_ucas_mapping { /* Available with KVM_CAP_S390_CMMA_MIGRATION */ #define KVM_S390_GET_CMMA_BITS _IOWR(KVMIO, 0xb8, struct kvm_s390_cmma_log) #define KVM_S390_SET_CMMA_BITS _IOW(KVMIO, 0xb9, struct kvm_s390_cmma_log) +#define KVM_ARM_SEI _IO(KVMIO, 0xb10) #define KVM_DEV_ASSIGN_ENABLE_IOMMU (1 << 0) #define KVM_DEV_ASSIGN_PCI_2_3 (1 << 1) diff --git a/target/arm/internals.h b/target/arm/internals.h index fc0ad6d..18b1cbc 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -237,6 +237,7 @@ enum arm_exception_class { #define ARM_EL_ISV (1 << ARM_EL_ISV_SHIFT) #define ARM_EL_EC_MASK ((0x3F) << ARM_EL_EC_SHIFT) #define ARM_EL_FSC_TYPE (0x3C) +#define ARM_EL_ISS_MASK ((1 << ARM_EL_IL_SHIFT) - 1) #define FSC_SEA (0x10) #define FSC_SEA_TTW0 (0x14) diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c index d3bdab2..b84cb49 100644 --- a/target/arm/kvm64.c +++ b/target/arm/kvm64.c @@ -616,6 +616,22 @@ static int kvm_arm_cpreg_value(ARMCPU *cpu, ptrdiff_t fieldoffset) return -EINVAL; } +static int kvm_inject_arm_sei(CPUState *cs) +{ + ARMCPU *cpu = ARM_CPU(cs); + CPUARMState *env = &cpu->env; + + unsigned long syndrome = env->exception.vaddress; + /* set virtual SError syndrome */ + if (arm_feature(env, ARM_FEATURE_RAS_EXTENSION)) { + syndrome = syndrome & ARM_EL_ISS_MASK; + } else { + syndrome = 0; + } + + return kvm_vcpu_ioctl(CPU(cpu), KVM_ARM_SEI, &syndrome); +} + /* Inject synchronous external abort */ static int kvm_inject_arm_sea(CPUState *c) { @@ -1007,6 +1023,15 @@ static bool is_abort_sea(unsigned long syndrome) } } +static bool is_abort_sei(unsigned long syndrome) +{ + uint8_t ec = ((syndrome & ARM_EL_EC_MASK) >> ARM_EL_EC_SHIFT); + if ((ec != EC_SERROR)) + return false; + else + return true; +} + void kvm_arch_on_sigbus_vcpu(CPUState *c, int code, void *addr) { ram_addr_t ram_addr; @@ -1024,6 +1049,9 @@ void kvm_arch_on_sigbus_vcpu(CPUState *c, int code, void *addr) if (is_abort_sea(env->exception.syndrome)) { ghes_update_guest(ACPI_HEST_NOTIFY_SEA, paddr); kvm_inject_arm_sea(c); + } else if (is_abort_sei(env->exception.syndrome)) { + ghes_update_guest(ACPI_HEST_NOTIFY_SEI, paddr); + kvm_inject_arm_sei(c); } return; } -- 1.8.3.1 From MAILER-DAEMON Fri Aug 18 10:02:16 2017 Received: from list by lists.gnu.org with archive (Exim 4.71) id 1dihqp-0004GG-TC for mharc-qemu-arm@gnu.org; Fri, 18 Aug 2017 10:02:15 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:51608) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dihqi-0004CD-MW for qemu-arm@nongnu.org; Fri, 18 Aug 2017 10:02:13 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dihqc-0008Vt-79 for qemu-arm@nongnu.org; Fri, 18 Aug 2017 10:02:08 -0400 Received: from szxga05-in.huawei.com ([45.249.212.191]:2238) by eggs.gnu.org with esmtps (TLS1.0:RSA_ARCFOUR_SHA1:16) (Exim 4.71) (envelope-from ) id 1dihqb-0008TZ-5w; Fri, 18 Aug 2017 10:02:02 -0400 Received: from 172.30.72.58 (EHLO DGGEMS411-HUB.china.huawei.com) ([172.30.72.58]) by dggrg05-dlp.huawei.com (MOS 4.4.6-GA FastPath queued) with ESMTP id DFM74399; Fri, 18 Aug 2017 22:00:47 +0800 (CST) Received: from linux.huawei.com (10.67.187.203) by DGGEMS411-HUB.china.huawei.com (10.3.19.211) with Microsoft SMTP Server id 14.3.301.0; Fri, 18 Aug 2017 22:00:12 +0800 From: Dongjiu Geng To: , , , , , , , , , , , , , , , , , , , , , , , , , , , , CC: , , , , Date: Fri, 18 Aug 2017 22:23:41 +0800 Message-ID: <1503066227-18251-1-git-send-email-gengdongjiu@huawei.com> X-Mailer: git-send-email 1.7.7 MIME-Version: 1.0 Content-Type: text/plain X-Originating-IP: [10.67.187.203] X-CFilter-Loop: Reflected X-Mirapoint-Virus-RAPID-Raw: score=unknown(0), refid=str=0001.0A020202.5996F30F.0256, ss=1, re=0.000, recu=0.000, reip=0.000, cl=1, cld=1, fgs=0, ip=0.0.0.0, so=2014-11-16 11:51:01, dmn=2013-03-21 17:37:32 X-Mirapoint-Loop-Id: 1d503d07cd6458d8860737bafded8d81 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.4.x-2.6.x [generic] [fuzzy] X-Received-From: 45.249.212.191 Subject: [Qemu-arm] [PATCH v11 0/6] Add RAS virtualization support for armv8 SEA and SEI X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 18 Aug 2017 14:02:14 -0000 In the armv8 platform, the mainly processor hardware error notification type are synchronous external abort(SEA) and SError Interrupt (SEI), For the ARMv8 SEA/SEI, KVM or host kernel will deliver SIGBUS or use other interface to notify user space. After user space gets the notification, it will record the CPER to simulate GHES for guest OS and inject the a exception(SEA/SEI) to KVM. This series patch has two parts, one part handles synchronous external abort(SEA) exception and SError Interrupt (SEI) exception; another part is generating APEI table when guest OS boot up, and dynamically record CPER for the guest OS about the generic hardware errors. Currently the userspace only handles the memory section hardware errors. Before Qemu record the CPER, it needs to check the ACK value written by the guest OS to avoid read-write race condition. In the simulated APEI/GHESV2/CPER table, the max number of error soure is 11, which is classified by notification type, now only enable the SEA/SEI notification type error source to avoid OS boot warning. About the whole solution we ever discuessed it in here before: https://patchwork.kernel.org/patch/9633105/ Below is the APEI/GHESV2/CPER table layout, the max number of error soure is 11: etc/acpi/tables etc/hardware_errors ==================== ========================================== + +--------------------------+ +------------------+ | | HEST | | address | +--------------+ | +--------------------------+ | registers | | Error Status | | | GHES0 | | +----------------+ | Data Block 0 | | +--------------------------+ +--------->| |status_address0 |------------->| +------------+ | | ................. | | | +----------------+ | | CPER | | | error_status_address-----+-+ +------->| |status_address1 |----------+ | | CPER | | | ................. | | | +----------------+ | | | .... | | | read_ack_register--------+-+ | | ............. | | | | CPER | | | read_ack_preserve | | | +------------------+ | | +------------+ | | read_ack_write | | | +----->| |status_address10|--------+ | | Error Status | + +--------------------------+ | | | | +----------------+ | | | Data Block 1 | | | GHES1 | +-+-+----->| | ack_value0 | | +-->| +------------+ + +--------------------------+ | | | +----------------+ | | | CPER | | | ................. | | | +--->| | ack_value1 | | | | CPER | | | error_status_address-----+---+ | | | +----------------+ | | | .... | | | ................. | | | | | ............. | | | | CPER | | | read_ack_register--------+-----+-+ | +----------------+ | +-+------------+ | | read_ack_preserve | | +->| | ack_value10 | | | |.......... | | | read_ack_write | | | | +----------------+ | | +------------+ + +--------------------------| | | | | Error Status | | | ............... | | | | | Data Block 10| + +--------------------------+ | | +---->| +------------+ | | GHES10 | | | | | CPER | + +--------------------------+ | | | | CPER | | | ................. | | | | | .... | | | error_status_address-----+-----+ | | | CPER | | | ................. | | +-+------------+ | | read_ack_register--------+---------+ | | read_ack_preserve | | | read_ack_write | + +--------------------------+ ---------------------------------------------------------------------------------------------- How to test guest OS do SEA/SEI recovery: 1. In the guest OS, trigger a SEA or SEI. 2. Then you will see below error log that printed by the memory failure 3. Memory failure will do the recovery for the error. Such as the below shown kernel log: [ 21.101216] Synchronous External Abort: synchronous external abort (0x96000010) at 0xffffff8008064018 [ 21.104969] {1}[Hardware Error]: Hardware error from APEI Generic Hardware Error Source: 8 [ 21.106918] {1}[Hardware Error]: event severity: recoverable [ 21.109027] {1}[Hardware Error]: Error 0, type: recoverable [ 21.110362] {1}[Hardware Error]: section_type: memory error [ 21.111705] {1}[Hardware Error]: physical_address: 0x000000007a200000 [ 21.113255] {1}[Hardware Error]: error_type: 3, multi-bit ECC [ 21.118528] Internal error: : 96000010 [#1] SMP [ 21.119587] Modules linked in: [ 21.120307] CPU: 0 PID: 509 Comm: devmem Not tainted 4.12.0-rc4ajb-00990-g954379b-dirty #67 [ 21.122307] Hardware name: QEMU KVM Virtual Machine, BIOS 0.0.0 02/06/2015 [ 21.123915] task: ffffffc03da32900 task.stack: ffffffc03dbbc000 [ 21.125302] PC is at __do_user_fault+0x58/0x110 [ 21.126370] LR is at __do_user_fault+0x54/0x110 [ 21.127433] pc : [] lr : [] pstate: 80000145 [ 21.129164] sp : ffffffc03dbbfd20 [ 21.129940] x29: ffffffc03dbbfd20 x28: ffffffc03da32900 [ 21.131204] x27: 0000000000000000 x26: 0000007f7edc5001 [ 21.132439] x25: ffffff8008648438 x24: ffffffc03dbbfec0 [ 21.133689] x23: 0000000000030001 x22: 0000007f7edc5001 [ 21.134934] x21: 0000000000000007 x20: 0000000092000021 [ 21.136195] x19: ffffffc03da32900 x18: 0000007fdd4c18f0 [ 21.137439] x17: 0000007f7ecb9ebc x16: 0000000000412058 ------------------------------------------------------------------------------------------------ how to test guest OS APTI/GHES: 1. In the guest OS, use this command to dump the APEI table: "iasl -p ./HEST -d /sys/firmware/acpi/tables/HEST" 2. And find the address for the generic error status block according to the notification type 3. then find the CPER record through the generic error status block. For example(notification type is SEA): (1) root@genericarmv8:~# iasl -p ./HEST -d /sys/firmware/acpi/tables/HEST (2) root@genericarmv8:~# cat HEST.dsl /* * Intel ACPI Component Architecture * AML/ASL+ Disassembler version 20170728 (64-bit version) * Copyright (c) 2000 - 2017 Intel Corporation * * Disassembly of /sys/firmware/acpi/tables/HEST, Mon Sep 5 07:59:17 2016 * * ACPI Data Table [HEST] * * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue */ .................................................................................. [308h 0776 2] Subtable Type : 000A [Generic Hardware Error Source V2] [30Ah 0778 2] Source Id : 0008 [30Ch 0780 2] Related Source Id : FFFF [30Eh 0782 1] Reserved : 00 [30Fh 0783 1] Enabled : 01 [310h 0784 4] Records To Preallocate : 00000001 [314h 0788 4] Max Sections Per Record : 00000001 [318h 0792 4] Max Raw Data Length : 00001000 [31Ch 0796 12] Error Status Address : [Generic Address Structure] [31Ch 0796 1] Space ID : 00 [SystemMemory] [31Dh 0797 1] Bit Width : 40 [31Eh 0798 1] Bit Offset : 00 [31Fh 0799 1] Encoded Access Width : 04 [QWord Access:64] [320h 0800 8] Address : 00000000785D0040 [328h 0808 28] Notify : [Hardware Error Notification Structure] [328h 0808 1] Notify Type : 08 [SEA] [329h 0809 1] Notify Length : 1C [32Ah 0810 2] Configuration Write Enable : 0000 [32Ch 0812 4] PollInterval : 00000000 [330h 0816 4] Vector : 00000000 [334h 0820 4] Polling Threshold Value : 00000000 [338h 0824 4] Polling Threshold Window : 00000000 [33Ch 0828 4] Error Threshold Value : 00000000 [340h 0832 4] Error Threshold Window : 00000000 [344h 0836 4] Error Status Block Length : 00001000 [348h 0840 12] Read Ack Register : [Generic Address Structure] [348h 0840 1] Space ID : 00 [SystemMemory] [349h 0841 1] Bit Width : 40 [34Ah 0842 1] Bit Offset : 00 [34Bh 0843 1] Encoded Access Width : 04 [QWord Access:64] [34Ch 0844 8] Address : 00000000785D0098 [354h 0852 8] Read Ack Preserve : 00000000FFFFFFFE [35Ch 0860 8] Read Ack Write : 0000000000000001 [364h 0868 2] Subtable Type : 000A [Generic Hardware Error Source V2] [366h 0870 2] Source Id : 0009 [368h 0872 2] Related Source Id : FFFF [36Ah 0874 1] Reserved : 00 [36Bh 0875 1] Enabled : 01 [36Ch 0876 4] Records To Preallocate : 00000001 [370h 0880 4] Max Sections Per Record : 00000001 [374h 0884 4] Max Raw Data Length : 00001000 [378h 0888 12] Error Status Address : [Generic Address Structure] [378h 0888 1] Space ID : 00 [SystemMemory] [379h 0889 1] Bit Width : 40 [37Ah 0890 1] Bit Offset : 00 [37Bh 0891 1] Encoded Access Width : 04 [QWord Access:64] [37Ch 0892 8] Address : 00000000785D0048 [384h 0900 28] Notify : [Hardware Error Notification Structure] [384h 0900 1] Notify Type : 09 [SEI] [385h 0901 1] Notify Length : 1C [386h 0902 2] Configuration Write Enable : 0000 [388h 0904 4] PollInterval : 00000000 [38Ch 0908 4] Vector : 00000000 [390h 0912 4] Polling Threshold Value : 00000000 [394h 0916 4] Polling Threshold Window : 00000000 [398h 0920 4] Error Threshold Value : 00000000 [39Ch 0924 4] Error Threshold Window : 00000000 [3A0h 0928 4] Error Status Block Length : 00001000 [3A4h 0932 12] Read Ack Register : [Generic Address Structure] [3A4h 0932 1] Space ID : 00 [SystemMemory] [3A5h 0933 1] Bit Width : 40 [3A6h 0934 1] Bit Offset : 00 [3A7h 0935 1] Encoded Access Width : 04 [QWord Access:64] [3A8h 0936 8] Address : 00000000785D00A0 [3B0h 0944 8] Read Ack Preserve : 00000000FFFFFFFE [3B8h 0952 8] Read Ack Write : 0000000000000001 ..................................................................................... (3) according to above table, the address that contains the physical address of a block of memory that holds the error status data for SEA notification error source is 0x00000000785D0040 (4) the address for SEA notification error source is 0x785d8108 (qemu) xp /1 0x00000000785D0040 00000000785d0040: 0x785d80b0 (5) check the content of generic error status block and generic error data entry (qemu) xp /100x 0x785d80b0 00000000785d80b0: 0x00000001 0x00000000 0x00000000 0x00000098 00000000785d80c0: 0x00000000 0xa5bc1114 0x4ede6f64 0x833e63b8 00000000785d80d0: 0xb1837ced 0x00000000 0x00000300 0x00000050 00000000785d80e0: 0x00000000 0x00000000 0x00000000 0x00000000 00000000785d80f0: 0x00000000 0x00000000 0x00000000 0x00000000 00000000785d8100: 0x00000000 0x00000000 0x00000000 0x00004002 00000000785d8110: 0x00000000 0x00000000 0x00000000 0x00001111 00000000785d8120: 0x00000000 0x00000000 0x00000000 0x00000000 00000000785d8130: 0x00000000 0x00000000 0x00000000 0x00000000 00000000785d8140: 0x00000000 0x00000000 0x00000000 0x00000000 00000000785d8150: 0x00000000 0x00000003 0x00000000 0x00000000 00000000785d8160: 0x00000000 0x00000000 0x00000000 0x00000000 00000000785d8170: 0x00000000 0x00000000 0x00000000 0x00000000 00000000785d8180: 0x00000000 0x00000000 0x00000000 0x00000000 00000000785d8190: 0x00000000 0x00000000 0x00000000 0x00000000 00000000785d81a0: 0x00000000 0x00000000 0x00000000 0x00000000 00000000785d81b0: 0x00000000 0x00000000 0x00000000 0x00000000 00000000785d81c0: 0x00000000 0x00000000 0x00000000 0x00000000 00000000785d81d0: 0x00000000 0x00000000 0x00000000 0x00000000 00000000785d81e0: 0x00000000 0x00000000 0x00000000 0x00000000 00000000785d81f0: 0x00000000 0x00000000 0x00000000 0x00000000 00000000785d8200: 0x00000000 0x00000000 0x00000000 0x00000000 00000000785d8210: 0x00000000 0x00000000 0x00000000 0x00000000 00000000785d8220: 0x00000000 0x00000000 0x00000000 0x00000000 00000000785d8230: 0x00000000 0x00000000 0x00000000 0x00000000 (6) check the OSPM's ACK value(for example SEA) /* Before OSPM acknowledges the error, check the ACK value */ (qemu) xp /1 0x00000000785D0098 00000000785d00f0: 0x00000000 /* After OSPM acknowledges the error, check the ACK value */ (qemu) xp /1 0x00000000785D0098 00000000785d00f0: 0x00000001 Dongjiu Geng (6): ACPI: add APEI/HEST/CPER structures and macros ACPI: Add APEI GHES Table Generation support ACPI: build and enable APEI GHES in the Makefile and configuration target-arm: kvm64: detect guest RAS EXTENSION feature target-arm: kvm64: handle SIGBUS signal for synchronous External Abort target-arm: kvm64: Handle SError interrupt from the guest OS default-configs/arm-softmmu.mak | 1 + hw/acpi/Makefile.objs | 1 + hw/acpi/aml-build.c | 2 + hw/acpi/hest_ghes.c | 345 ++++++++++++++++++++++++++++++++++++++++ hw/arm/virt-acpi-build.c | 6 + include/hw/acpi/acpi-defs.h | 193 ++++++++++++++++++++++ include/hw/acpi/aml-build.h | 1 + include/hw/acpi/hest_ghes.h | 47 ++++++ include/sysemu/kvm.h | 2 +- linux-headers/asm-arm64/kvm.h | 5 + linux-headers/linux/kvm.h | 2 + target/arm/cpu.h | 3 + target/arm/internals.h | 14 ++ target/arm/kvm.c | 34 ++++ target/arm/kvm64.c | 186 ++++++++++++++++++++++ target/arm/kvm_arm.h | 1 + 16 files changed, 842 insertions(+), 1 deletion(-) create mode 100644 hw/acpi/hest_ghes.c create mode 100644 include/hw/acpi/hest_ghes.h -- 1.8.3.1 From MAILER-DAEMON Fri Aug 18 10:02:18 2017 Received: from list by lists.gnu.org with archive (Exim 4.71) id 1dihqs-0004Ib-51 for mharc-qemu-arm@gnu.org; Fri, 18 Aug 2017 10:02:18 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:51634) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dihqm-0004CV-6c for qemu-arm@nongnu.org; Fri, 18 Aug 2017 10:02:17 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dihqh-00008J-HM for qemu-arm@nongnu.org; Fri, 18 Aug 2017 10:02:12 -0400 Received: from szxga05-in.huawei.com ([45.249.212.191]:2239) by eggs.gnu.org with esmtps (TLS1.0:RSA_ARCFOUR_SHA1:16) (Exim 4.71) (envelope-from ) id 1dihqg-00005z-Ff; Fri, 18 Aug 2017 10:02:07 -0400 Received: from 172.30.72.58 (EHLO DGGEMS411-HUB.china.huawei.com) ([172.30.72.58]) by dggrg05-dlp.huawei.com (MOS 4.4.6-GA FastPath queued) with ESMTP id DFM74406; Fri, 18 Aug 2017 22:00:47 +0800 (CST) Received: from linux.huawei.com (10.67.187.203) by DGGEMS411-HUB.china.huawei.com (10.3.19.211) with Microsoft SMTP Server id 14.3.301.0; Fri, 18 Aug 2017 22:00:13 +0800 From: Dongjiu Geng To: , , , , , , , , , , , , , , , , , , , , , , , , , , , , CC: , , , , Date: Fri, 18 Aug 2017 22:23:46 +0800 Message-ID: <1503066227-18251-6-git-send-email-gengdongjiu@huawei.com> X-Mailer: git-send-email 1.7.7 In-Reply-To: <1503066227-18251-1-git-send-email-gengdongjiu@huawei.com> References: <1503066227-18251-1-git-send-email-gengdongjiu@huawei.com> MIME-Version: 1.0 Content-Type: text/plain X-Originating-IP: [10.67.187.203] X-CFilter-Loop: Reflected X-Mirapoint-Virus-RAPID-Raw: score=unknown(0), refid=str=0001.0A020201.5996F310.00E0, ss=1, re=0.000, recu=0.000, reip=0.000, cl=1, cld=1, fgs=0, ip=0.0.0.0, so=2014-11-16 11:51:01, dmn=2013-03-21 17:37:32 X-Mirapoint-Loop-Id: dbca42ab5aec7b3a3582b2370f2434d9 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.4.x-2.6.x [generic] [fuzzy] X-Received-From: 45.249.212.191 Subject: [Qemu-arm] [PATCH v11 5/6] target-arm: kvm64: handle SIGBUS signal for synchronous External Abort X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 18 Aug 2017 14:02:17 -0000 Add SIGBUS signal handler. In this handler, it checks the exception type, translates the host VA which is delivered by host or KVM to guest PA, then fills this PA to CPER, finally injects a Error to guest OS through KVM. Add synchronous external abort injection logic, setup spsr_elx, esr_elx, PSTATE, far_elx, elr_elx etc, when switch to guest OS, it will jump to the synchronous external abort vector table entry. Signed-off-by: Dongjiu Geng Signed-off-by: Quanming Wu --- include/sysemu/kvm.h | 2 +- linux-headers/asm-arm64/kvm.h | 5 ++ target/arm/internals.h | 13 ++++ target/arm/kvm.c | 34 ++++++++++ target/arm/kvm64.c | 150 ++++++++++++++++++++++++++++++++++++++++++ target/arm/kvm_arm.h | 1 + 6 files changed, 204 insertions(+), 1 deletion(-) diff --git a/include/sysemu/kvm.h b/include/sysemu/kvm.h index 3a458f5..90c1605 100644 --- a/include/sysemu/kvm.h +++ b/include/sysemu/kvm.h @@ -361,7 +361,7 @@ bool kvm_vcpu_id_is_valid(int vcpu_id); /* Returns VCPU ID to be used on KVM_CREATE_VCPU ioctl() */ unsigned long kvm_arch_vcpu_id(CPUState *cpu); -#ifdef TARGET_I386 +#if defined(TARGET_I386) || defined(TARGET_AARCH64) #define KVM_HAVE_MCE_INJECTION 1 void kvm_arch_on_sigbus_vcpu(CPUState *cpu, int code, void *addr); #endif diff --git a/linux-headers/asm-arm64/kvm.h b/linux-headers/asm-arm64/kvm.h index d254700..5909c30 100644 --- a/linux-headers/asm-arm64/kvm.h +++ b/linux-headers/asm-arm64/kvm.h @@ -181,6 +181,11 @@ struct kvm_arch_memory_slot { #define KVM_REG_ARM64_SYSREG_OP2_MASK 0x0000000000000007 #define KVM_REG_ARM64_SYSREG_OP2_SHIFT 0 +/* AArch64 fault registers */ +#define KVM_REG_ARM64_FAULT (0x0014 << KVM_REG_ARM_COPROC_SHIFT) +#define KVM_REG_ARM64_FAULT_ESR_EC (0) +#define KVM_REG_ARM64_FAULT_FAR (1) + #define ARM64_SYS_REG_SHIFT_MASK(x,n) \ (((x) << KVM_REG_ARM64_SYSREG_ ## n ## _SHIFT) & \ KVM_REG_ARM64_SYSREG_ ## n ## _MASK) diff --git a/target/arm/internals.h b/target/arm/internals.h index 1f6efef..fc0ad6d 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -235,6 +235,19 @@ enum arm_exception_class { #define ARM_EL_ISV_SHIFT 24 #define ARM_EL_IL (1 << ARM_EL_IL_SHIFT) #define ARM_EL_ISV (1 << ARM_EL_ISV_SHIFT) +#define ARM_EL_EC_MASK ((0x3F) << ARM_EL_EC_SHIFT) +#define ARM_EL_FSC_TYPE (0x3C) + +#define FSC_SEA (0x10) +#define FSC_SEA_TTW0 (0x14) +#define FSC_SEA_TTW1 (0x15) +#define FSC_SEA_TTW2 (0x16) +#define FSC_SEA_TTW3 (0x17) +#define FSC_SECC (0x18) +#define FSC_SECC_TTW0 (0x1c) +#define FSC_SECC_TTW1 (0x1d) +#define FSC_SECC_TTW2 (0x1e) +#define FSC_SECC_TTW3 (0x1f) /* Utility functions for constructing various kinds of syndrome value. * Note that in general we follow the AArch64 syndrome values; in a diff --git a/target/arm/kvm.c b/target/arm/kvm.c index 7c17f0d..2e1716a 100644 --- a/target/arm/kvm.c +++ b/target/arm/kvm.c @@ -129,6 +129,39 @@ void kvm_arm_destroy_scratch_host_vcpu(int *fdarray) } } +typedef struct HWPoisonPage { + ram_addr_t ram_addr; + QLIST_ENTRY(HWPoisonPage) list; +} HWPoisonPage; + +static QLIST_HEAD(, HWPoisonPage) hwpoison_page_list = + QLIST_HEAD_INITIALIZER(hwpoison_page_list); + +static void kvm_unpoison_all(void *param) +{ + HWPoisonPage *page, *next_page; + + QLIST_FOREACH_SAFE(page, &hwpoison_page_list, list, next_page) { + QLIST_REMOVE(page, list); + qemu_ram_remap(page->ram_addr, TARGET_PAGE_SIZE); + g_free(page); + } +} + +void kvm_hwpoison_page_add(ram_addr_t ram_addr) +{ + HWPoisonPage *page; + + QLIST_FOREACH(page, &hwpoison_page_list, list) { + if (page->ram_addr == ram_addr) { + return; + } + } + page = g_new(HWPoisonPage, 1); + page->ram_addr = ram_addr; + QLIST_INSERT_HEAD(&hwpoison_page_list, page, list); +} + static void kvm_arm_host_cpu_class_init(ObjectClass *oc, void *data) { ARMHostCPUClass *ahcc = ARM_HOST_CPU_CLASS(oc); @@ -182,6 +215,7 @@ int kvm_arch_init(MachineState *ms, KVMState *s) cap_has_mp_state = kvm_check_extension(s, KVM_CAP_MP_STATE); + qemu_register_reset(kvm_unpoison_all, NULL); type_register_static(&host_arm_cpu_type_info); return 0; diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c index 0781367..d3bdab2 100644 --- a/target/arm/kvm64.c +++ b/target/arm/kvm64.c @@ -27,6 +27,8 @@ #include "kvm_arm.h" #include "internals.h" #include "hw/arm/arm.h" +#include "hw/acpi/acpi-defs.h" +#include "hw/acpi/hest_ghes.h" static bool have_guest_debug; @@ -590,6 +592,79 @@ int kvm_arm_cpreg_level(uint64_t regidx) return KVM_PUT_RUNTIME_STATE; } +static int kvm_arm_cpreg_value(ARMCPU *cpu, ptrdiff_t fieldoffset) +{ + int i; + + for (i = 0; i < cpu->cpreg_array_len; i++) { + uint32_t regidx = kvm_to_cpreg_id(cpu->cpreg_indexes[i]); + const ARMCPRegInfo *ri; + ri = get_arm_cp_reginfo(cpu->cp_regs, regidx); + if (!ri) { + continue; + } + + if (ri->type & ARM_CP_NO_RAW) { + continue; + } + + if (ri->fieldoffset == fieldoffset) { + cpu->cpreg_values[i] = read_raw_cp_reg(&cpu->env, ri); + return 0; + } + } + return -EINVAL; +} + +/* Inject synchronous external abort */ +static int kvm_inject_arm_sea(CPUState *c) +{ + ARMCPU *cpu = ARM_CPU(c); + CPUARMState *env = &cpu->env; + unsigned long cpsr = pstate_read(env); + uint32_t esr = 0; + int ret; + + c->exception_index = EXCP_DATA_ABORT; + /* Inject the exception to El1 */ + env->exception.target_el = 1; + CPUClass *cc = CPU_GET_CLASS(c); + + esr |= (EC_DATAABORT << ARM_EL_EC_SHIFT); + /* This exception syndrome includes {I,D}FSC in the bits [5:0] + */ + esr |= (env->exception.syndrome & 0x3f); + + /* This exception is EL0 or EL1 fault. */ + if ((cpsr & 0xf) == PSTATE_MODE_EL0t) { + esr |= (EC_INSNABORT << ARM_EL_EC_SHIFT); + } else { + esr |= (EC_INSNABORT_SAME_EL << ARM_EL_EC_SHIFT); + } + + /* In the aarch64, there is only 32-bit instruction*/ + esr |= ARM_EL_IL; + env->exception.syndrome = esr; + cc->do_interrupt(c); + + /* set ESR_EL1 */ + ret = kvm_arm_cpreg_value(cpu, offsetof(CPUARMState, cp15.esr_el[1])); + + if (ret) { + fprintf(stderr, "<%s> failed to set esr_el1\n", __func__); + abort(); + } + + /* set FAR_EL1 */ + ret = kvm_arm_cpreg_value(cpu, offsetof(CPUARMState, cp15.far_el[1])); + if (ret) { + fprintf(stderr, "<%s> failed to set far_el1\n", __func__); + abort(); + } + + return 0; +} + #define AARCH64_CORE_REG(x) (KVM_REG_ARM64 | KVM_REG_SIZE_U64 | \ KVM_REG_ARM_CORE | KVM_REG_ARM_CORE_REG(x)) @@ -599,6 +674,9 @@ int kvm_arm_cpreg_level(uint64_t regidx) #define AARCH64_SIMD_CTRL_REG(x) (KVM_REG_ARM64 | KVM_REG_SIZE_U32 | \ KVM_REG_ARM_CORE | KVM_REG_ARM_CORE_REG(x)) +#define AARCH64_FAULT_REG(x) (KVM_REG_ARM64 | KVM_REG_SIZE_U64 | \ + KVM_REG_ARM64_FAULT | (x)) + int kvm_arch_put_registers(CPUState *cs, int level) { struct kvm_one_reg reg; @@ -873,6 +951,22 @@ int kvm_arch_get_registers(CPUState *cs) } vfp_set_fpcr(env, fpr); + if (is_a64(env)) { + reg.id = AARCH64_FAULT_REG(KVM_REG_ARM64_FAULT_ESR_EC); + reg.addr = (uintptr_t)(&env->exception.syndrome); + ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, ®); + if (ret) { + return ret; + } + + reg.id = AARCH64_FAULT_REG(KVM_REG_ARM64_FAULT_FAR); + reg.addr = (uintptr_t)(&env->exception.vaddress); + ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, ®); + if (ret) { + return ret; + } + } + if (!write_kvmstate_to_list(cpu)) { return EINVAL; } @@ -887,6 +981,62 @@ int kvm_arch_get_registers(CPUState *cs) return ret; } +static bool is_abort_sea(unsigned long syndrome) +{ + unsigned long fault_status; + uint8_t ec = ((syndrome & ARM_EL_EC_MASK) >> ARM_EL_EC_SHIFT); + if ((ec != EC_INSNABORT) && (ec != EC_DATAABORT)) { + return false; + } + + fault_status = syndrome & ARM_EL_FSC_TYPE; + switch (fault_status) { + case FSC_SEA: + case FSC_SEA_TTW0: + case FSC_SEA_TTW1: + case FSC_SEA_TTW2: + case FSC_SEA_TTW3: + case FSC_SECC: + case FSC_SECC_TTW0: + case FSC_SECC_TTW1: + case FSC_SECC_TTW2: + case FSC_SECC_TTW3: + return true; + default: + return false; + } +} + +void kvm_arch_on_sigbus_vcpu(CPUState *c, int code, void *addr) +{ + ram_addr_t ram_addr; + hwaddr paddr; + + ARMCPU *cpu = ARM_CPU(c); + CPUARMState *env = &cpu->env; + assert(code == BUS_MCEERR_AR || code == BUS_MCEERR_AO); + if (addr) { + ram_addr = qemu_ram_addr_from_host(addr); + if (ram_addr != RAM_ADDR_INVALID && + kvm_physical_memory_addr_from_host(c->kvm_state, addr, &paddr)) { + kvm_cpu_synchronize_state(c); + kvm_hwpoison_page_add(ram_addr); + if (is_abort_sea(env->exception.syndrome)) { + ghes_update_guest(ACPI_HEST_NOTIFY_SEA, paddr); + kvm_inject_arm_sea(c); + } + return; + } + fprintf(stderr, "Hardware memory error for memory used by " + "QEMU itself instead of guest system!\n"); + } + + if (code == BUS_MCEERR_AR) { + fprintf(stderr, "Hardware memory error!\n"); + exit(1); + } +} + /* C6.6.29 BRK instruction */ static const uint32_t brk_insn = 0xd4200000; diff --git a/target/arm/kvm_arm.h b/target/arm/kvm_arm.h index 633d088..7cdde97 100644 --- a/target/arm/kvm_arm.h +++ b/target/arm/kvm_arm.h @@ -288,4 +288,5 @@ static inline const char *its_class_name(void) } } +void kvm_hwpoison_page_add(ram_addr_t ram_addr); #endif -- 1.8.3.1 From MAILER-DAEMON Fri Aug 18 10:02:28 2017 Received: from list by lists.gnu.org with archive (Exim 4.71) id 1dihr2-0004Qm-Ds for mharc-qemu-arm@gnu.org; Fri, 18 Aug 2017 10:02:28 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:51688) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dihqv-0004KB-EX for qemu-arm@nongnu.org; Fri, 18 Aug 2017 10:02:26 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dihqo-0000D4-6v for qemu-arm@nongnu.org; Fri, 18 Aug 2017 10:02:21 -0400 Received: from szxga05-in.huawei.com ([45.249.212.191]:2240) by eggs.gnu.org with esmtps (TLS1.0:RSA_ARCFOUR_SHA1:16) (Exim 4.71) (envelope-from ) id 1dihqm-0000AZ-Tc; Fri, 18 Aug 2017 10:02:14 -0400 Received: from 172.30.72.58 (EHLO DGGEMS411-HUB.china.huawei.com) ([172.30.72.58]) by dggrg05-dlp.huawei.com (MOS 4.4.6-GA FastPath queued) with ESMTP id DFM74384; Fri, 18 Aug 2017 22:00:42 +0800 (CST) Received: from linux.huawei.com (10.67.187.203) by DGGEMS411-HUB.china.huawei.com (10.3.19.211) with Microsoft SMTP Server id 14.3.301.0; Fri, 18 Aug 2017 22:00:12 +0800 From: Dongjiu Geng To: , , , , , , , , , , , , , , , , , , , , , , , , , , , , CC: , , , , Date: Fri, 18 Aug 2017 22:23:43 +0800 Message-ID: <1503066227-18251-3-git-send-email-gengdongjiu@huawei.com> X-Mailer: git-send-email 1.7.7 In-Reply-To: <1503066227-18251-1-git-send-email-gengdongjiu@huawei.com> References: <1503066227-18251-1-git-send-email-gengdongjiu@huawei.com> MIME-Version: 1.0 Content-Type: text/plain X-Originating-IP: [10.67.187.203] X-CFilter-Loop: Reflected X-Mirapoint-Virus-RAPID-Raw: score=unknown(0), refid=str=0001.0A020201.5996F30C.0131, ss=1, re=0.000, recu=0.000, reip=0.000, cl=1, cld=1, fgs=0, ip=0.0.0.0, so=2014-11-16 11:51:01, dmn=2013-03-21 17:37:32 X-Mirapoint-Loop-Id: fae2e80c8e9eb9944b27414a5d5592e6 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.4.x-2.6.x [generic] [fuzzy] X-Received-From: 45.249.212.191 Subject: [Qemu-arm] [PATCH v11 2/6] ACPI: Add APEI GHES Table Generation support X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 18 Aug 2017 14:02:27 -0000 This implements APEI GHES Table by passing the error CPER info to the guest via a fw_cfg_blob. After a CPER info is recorded, an SEA(Synchronous External Abort)/SEI(SError Interrupt) exception will be injected into the guest OS. Below is the table layout, the max number of error soure is 11, which is classified by notification type. etc/acpi/tables etc/hardware_errors ==================== ========================================== + +--------------------------+ +------------------+ | | HEST | | address | +--------------+ | +--------------------------+ | registers | | Error Status | | | GHES0 | | +----------------+ | Data Block 0 | | +--------------------------+ +--------->| |status_address0 |------------->| +------------+ | | ................. | | | +----------------+ | | CPER | | | error_status_address-----+-+ +------->| |status_address1 |----------+ | | CPER | | | ................. | | | +----------------+ | | | .... | | | read_ack_register--------+-+ | | ............. | | | | CPER | | | read_ack_preserve | | | +------------------+ | | +-+------------+ | | read_ack_write | | | +----->| |status_address10|--------+ | | Error Status | + +--------------------------+ | | | | +----------------+ | | | Data Block 1 | | | GHES1 | +-+-+----->| | ack_value0 | | +-->| +------------+ + +--------------------------+ | | | +----------------+ | | | CPER | | | ................. | | | +--->| | ack_value1 | | | | CPER | | | error_status_address-----+---+ | | | +----------------+ | | | .... | | | ................. | | | | | ............. | | | | CPER | | | read_ack_register--------+-----+-+ | +----------------+ | +-+------------+ | | read_ack_preserve | | +->| | ack_value10 | | | |.......... | | | read_ack_write | | | | +----------------+ | | +------------+ + +--------------------------| | | | | Error Status | | | ............... | | | | | Data Block 10| + +--------------------------+ | | +---->| +------------+ | | GHES10 | | | | | CPER | + +--------------------------+ | | | | CPER | | | ................. | | | | | .... | | | error_status_address-----+-----+ | | | CPER | | | ................. | | +-+------------+ | | read_ack_register--------+---------+ | | read_ack_preserve | | | read_ack_write | + +--------------------------+ For GHESv2 error source, the OSPM must acknowledges the error via Read Ack register. so user space must check the ack value to avoid read-write race condition. Signed-off-by: Dongjiu Geng --- hw/acpi/aml-build.c | 2 + hw/acpi/hest_ghes.c | 345 ++++++++++++++++++++++++++++++++++++++++++++ hw/arm/virt-acpi-build.c | 6 + include/hw/acpi/aml-build.h | 1 + include/hw/acpi/hest_ghes.h | 47 ++++++ 5 files changed, 401 insertions(+) create mode 100644 hw/acpi/hest_ghes.c create mode 100644 include/hw/acpi/hest_ghes.h diff --git a/hw/acpi/aml-build.c b/hw/acpi/aml-build.c index 36a6cc4..6849e5f 100644 --- a/hw/acpi/aml-build.c +++ b/hw/acpi/aml-build.c @@ -1561,6 +1561,7 @@ void acpi_build_tables_init(AcpiBuildTables *tables) tables->table_data = g_array_new(false, true /* clear */, 1); tables->tcpalog = g_array_new(false, true /* clear */, 1); tables->vmgenid = g_array_new(false, true /* clear */, 1); + tables->hardware_errors = g_array_new(false, true /* clear */, 1); tables->linker = bios_linker_loader_init(); } @@ -1571,6 +1572,7 @@ void acpi_build_tables_cleanup(AcpiBuildTables *tables, bool mfre) g_array_free(tables->table_data, true); g_array_free(tables->tcpalog, mfre); g_array_free(tables->vmgenid, mfre); + g_array_free(tables->hardware_errors, mfre); } /* Build rsdt table */ diff --git a/hw/acpi/hest_ghes.c b/hw/acpi/hest_ghes.c new file mode 100644 index 0000000..ff6b5ef --- /dev/null +++ b/hw/acpi/hest_ghes.c @@ -0,0 +1,345 @@ +/* + * APEI GHES table Generation + * + * Copyright (C) 2017 huawei. + * + * Author: Dongjiu Geng + * + * This work is licensed under the terms of the GNU GPL, version 2 or later. + * See the COPYING file in the top-level directory. + * + */ + +#include "qemu/osdep.h" +#include "qmp-commands.h" +#include "hw/acpi/acpi.h" +#include "hw/acpi/aml-build.h" +#include "hw/acpi/hest_ghes.h" +#include "hw/nvram/fw_cfg.h" +#include "sysemu/sysemu.h" +#include "qemu/error-report.h" + +/* The structure that stands for the layout + * GHES_ERRORS_FW_CFG_FILE fw_cfg blob + * + * etc/hardware_errors + * ========================================== + * +------------------+ + * | address | +--------------+ + * | registers | | Error Status | + * | +----------------+ | Data Block 0 | + * | |status_address0 |------------->| +------------+ + * | +----------------+ | | CPER | + * | |status_address1 |----------+ | | CPER | + * | +----------------+ | | | .... | + * | |............. | | | | CPER | + * | +----------------+ | | +------------+ + * | |status_address10|-----+ | | Error Status | + * | +----------------+ | | | Data Block 1 | + * | |ack_value0 | | +-->| +------------+ + * | +----------------+ | | | CPER | + * | |ack_value1 | | | | CPER | + * | +----------------+ | | | .... | + * | | ............. | | | | CPER | + * | +----------------+ | +-+------------+ + * | |ack_value10 | | | |.......... | + * | +----------------+ | | +------------+ + * | | Error Status | + * | | Data Block10 | + * +------->+------------+ + * | | CPER | + * | | CPER | + * | | .... | + * | | CPER | + * +-+------------+ + */ +struct hardware_errors_buffer { + /* Generic Error Status Block register */ + uint64_t gesb_address[GHES_ACPI_HEST_NOTIFY_RESERVED]; + uint64_t ack_value[GHES_ACPI_HEST_NOTIFY_RESERVED]; + char gesb[GHES_MAX_RAW_DATA_LENGTH][GHES_ACPI_HEST_NOTIFY_RESERVED]; +}; + +static int ghes_record_cper(uint64_t error_block_address, + uint64_t error_physical_addr) +{ + AcpiGenericErrorStatus block; + AcpiGenericErrorData *gdata; + UefiCperSecMemErr *mem_err; + uint64_t current_block_length; + unsigned char *buffer; + /* memory section */ + char mem_section_id_le[] = {0x14, 0x11, 0xBC, 0xA5, 0x64, 0x6F, 0xDE, + 0x4E, 0xB8, 0x63, 0x3E, 0x83, 0xED, 0x7C, + 0x83, 0xB1}; + + cpu_physical_memory_read(error_block_address, &block, + sizeof(AcpiGenericErrorStatus)); + + /* Get the current generic error status block length */ + current_block_length = sizeof(AcpiGenericErrorStatus) + + le32_to_cpu(block.data_length); + + /* If the Generic Error Status Block is NULL, update + * the block header + */ + if (!block.block_status) { + block.block_status = ACPI_GEBS_UNCORRECTABLE; + block.error_severity = ACPI_CPER_SEV_RECOVERABLE; + } + + block.data_length += cpu_to_le32(sizeof(AcpiGenericErrorData)); + block.data_length += cpu_to_le32(sizeof(UefiCperSecMemErr)); + + /* check whether it runs out of the preallocated memory */ + if ((le32_to_cpu(block.data_length) + sizeof(AcpiGenericErrorStatus)) > + GHES_MAX_RAW_DATA_LENGTH) { + error_report("Record CPER out of boundary!!!"); + return GHES_CPER_FAIL; + } + + /* Write back the Generic Error Status Block to guest memory */ + cpu_physical_memory_write(error_block_address, &block, + sizeof(AcpiGenericErrorStatus)); + + /* Fill in Generic Error Data Entry */ + buffer = g_malloc0(sizeof(AcpiGenericErrorData) + + sizeof(UefiCperSecMemErr)); + + + memset(buffer, 0, sizeof(AcpiGenericErrorData) + sizeof(UefiCperSecMemErr)); + gdata = (AcpiGenericErrorData *)buffer; + + /* Memory section */ + memcpy(&(gdata->section_type_le), &mem_section_id_le, + sizeof(mem_section_id_le)); + + /* error severity is recoverable */ + gdata->error_severity = ACPI_CPER_SEV_RECOVERABLE; + gdata->revision = 0x300; /* the revision number is 0x300 */ + gdata->error_data_length = cpu_to_le32(sizeof(UefiCperSecMemErr)); + + mem_err = (UefiCperSecMemErr *) (gdata + 1); + + /* User space only handle the memory section CPER */ + + /* Hard code to Multi-bit ECC error */ + mem_err->validation_bits |= cpu_to_le32(UEFI_CPER_MEM_VALID_ERROR_TYPE); + mem_err->error_type = cpu_to_le32(UEFI_CPER_MEM_ERROR_TYPE_MULTI_ECC); + + /* Record the physical address at which the memory error occurred */ + mem_err->validation_bits |= cpu_to_le32(UEFI_CPER_MEM_VALID_PA); + mem_err->physical_addr = cpu_to_le32(error_physical_addr); + + /* Write back the Generic Error Data Entry to guest memory */ + cpu_physical_memory_write(error_block_address + current_block_length, + buffer, sizeof(AcpiGenericErrorData) + sizeof(UefiCperSecMemErr)); + + g_free(buffer); + return GHES_CPER_OK; +} + +static void +build_address(GArray *table_data, BIOSLinker *linker, + uint32_t dst_patched_offset, uint32_t src_offset, + uint8_t address_space_id , uint8_t register_bit_width, + uint8_t register_bit_offset, uint8_t access_size) +{ + uint32_t address_size = sizeof(struct AcpiGenericAddress) - + offsetof(struct AcpiGenericAddress, address); + + /* Address space */ + build_append_int_noprefix(table_data, address_space_id, 1); + /* register bit width */ + build_append_int_noprefix(table_data, register_bit_width, 1); + /* register bit offset */ + build_append_int_noprefix(table_data, register_bit_offset, 1); + /* access size */ + build_append_int_noprefix(table_data, access_size, 1); + acpi_data_push(table_data, address_size); + + /* Patch address of ERRORS fw_cfg blob into the TABLE fw_cfg blob so OSPM + * can retrieve and read it. the address size is 64 bits. + */ + bios_linker_loader_add_pointer(linker, + ACPI_BUILD_TABLE_FILE, dst_patched_offset, sizeof(uint64_t), + GHES_ERRORS_FW_CFG_FILE, src_offset); +} + +void ghes_build_acpi(GArray *table_data, GArray *hardware_error, + BIOSLinker *linker) +{ + uint32_t ghes_start = table_data->len; + uint32_t address_size, error_status_address_offset; + uint32_t read_ack_register_offset, i; + + address_size = sizeof(struct AcpiGenericAddress) - + offsetof(struct AcpiGenericAddress, address); + + error_status_address_offset = ghes_start + + sizeof(AcpiHardwareErrorSourceTable) + + offsetof(AcpiGenericHardwareErrorSourceV2, error_status_address) + + offsetof(struct AcpiGenericAddress, address); + + read_ack_register_offset = ghes_start + + sizeof(AcpiHardwareErrorSourceTable) + + offsetof(AcpiGenericHardwareErrorSourceV2, read_ack_register) + + offsetof(struct AcpiGenericAddress, address); + + acpi_data_push(hardware_error, + offsetof(struct hardware_errors_buffer, ack_value)); + for (i = 0; i < GHES_ACPI_HEST_NOTIFY_RESERVED; i++) + /* Initialize read ack register */ + build_append_int_noprefix((void *)hardware_error, 1, 8); + + /* Reserved the total size for ERRORS fw_cfg blob + */ + acpi_data_push(hardware_error, sizeof(struct hardware_errors_buffer)); + + /* Allocate guest memory for the Data fw_cfg blob */ + bios_linker_loader_alloc(linker, GHES_ERRORS_FW_CFG_FILE, hardware_error, + 1, false); + /* Reserve table header size */ + acpi_data_push(table_data, sizeof(AcpiTableHeader)); + + build_append_int_noprefix(table_data, GHES_ACPI_HEST_NOTIFY_RESERVED, 4); + + for (i = 0; i < GHES_ACPI_HEST_NOTIFY_RESERVED; i++) { + build_append_int_noprefix(table_data, + ACPI_HEST_SOURCE_GENERIC_ERROR_V2, 2); /* type */ + /* source id */ + build_append_int_noprefix(table_data, cpu_to_le16(i), 2); + /* related source id */ + build_append_int_noprefix(table_data, 0xffff, 2); + build_append_int_noprefix(table_data, 0, 1); /* flags */ + + /* Currently only enable SEA notification type to avoid the kernel + * warning, reserve the space for other notification error source + */ + if (i == ACPI_HEST_NOTIFY_SEA) { + build_append_int_noprefix(table_data, 1, 1); /* enabled */ + } else { + build_append_int_noprefix(table_data, 0, 1); /* enabled */ + } + + /* The number of error status block per generic hardware error source */ + build_append_int_noprefix(table_data, 1, 4); + /* Max sections per record */ + build_append_int_noprefix(table_data, 1, 4); + /* Max raw data length */ + build_append_int_noprefix(table_data, GHES_MAX_RAW_DATA_LENGTH, 4); + + /* Build error status address*/ + build_address(table_data, linker, error_status_address_offset + i * + sizeof(AcpiGenericHardwareErrorSourceV2), i * address_size, + AML_SYSTEM_MEMORY, 0x40, 0, 4 /* QWord access */); + + /* Hardware error notification structure */ + build_append_int_noprefix(table_data, i, 1); /* type */ + /* length */ + build_append_int_noprefix(table_data, sizeof(AcpiHestNotify), 1); + build_append_int_noprefix(table_data, 0, 26); + + /* Error Status Block Length */ + build_append_int_noprefix(table_data, + cpu_to_le32(GHES_MAX_RAW_DATA_LENGTH), 4); + + /* Build read ack register */ + build_address(table_data, linker, read_ack_register_offset + i * + sizeof(AcpiGenericHardwareErrorSourceV2), + offsetof(struct hardware_errors_buffer, ack_value) + + i * address_size, AML_SYSTEM_MEMORY, 0x40, 0, + 4 /* QWord access */); + + /* Read ack preserve */ + build_append_int_noprefix(table_data, cpu_to_le64(0xfffffffe), 8); + + /* Read ack write */ + build_append_int_noprefix(table_data, cpu_to_le64(0x1), 8); + } + + for (i = 0; i < GHES_ACPI_HEST_NOTIFY_RESERVED; i++) + /* Patch address of generic error status block into + * the address register so OSPM can retrieve and read it. + */ + bios_linker_loader_add_pointer(linker, + GHES_ERRORS_FW_CFG_FILE, address_size * i, address_size, + GHES_ERRORS_FW_CFG_FILE, + offsetof(struct hardware_errors_buffer, gesb) + + i * GHES_MAX_RAW_DATA_LENGTH); + + /* Patch address of ERRORS fw_cfg blob into the ADDR fw_cfg blob + * so QEMU can write the ERRORS there. The address is expected to be + * < 4GB, but write 64 bits anyway. + */ + bios_linker_loader_write_pointer(linker, GHES_DATA_ADDR_FW_CFG_FILE, + 0, address_size, GHES_ERRORS_FW_CFG_FILE, + offsetof(struct hardware_errors_buffer, gesb)); + + build_header(linker, table_data, + (void *)(table_data->data + ghes_start), "HEST", + table_data->len - ghes_start, 1, NULL, "GHES"); +} + +static GhesState ges; +void ghes_add_fw_cfg(FWCfgState *s, GArray *hardware_error) +{ + + size_t request_block_size = sizeof(uint64_t) + GHES_MAX_RAW_DATA_LENGTH; + size_t size = GHES_ACPI_HEST_NOTIFY_RESERVED * request_block_size; + + /* Create a read-only fw_cfg file for GHES */ + fw_cfg_add_file(s, GHES_ERRORS_FW_CFG_FILE, hardware_error->data, + size); + /* Create a read-write fw_cfg file for Address */ + fw_cfg_add_file_callback(s, GHES_DATA_ADDR_FW_CFG_FILE, NULL, NULL, + &ges.ghes_addr_le, sizeof(ges.ghes_addr_le), false); +} + +bool ghes_update_guest(uint32_t notify, uint64_t physical_address) +{ + uint64_t error_block_addr; + uint64_t ack_value_addr, ack_value = 0; + int loop = 0, ack_value_size; + bool ret = GHES_CPER_FAIL; + + ack_value_size = (offsetof(struct hardware_errors_buffer, gesb) - + offsetof(struct hardware_errors_buffer, ack_value)) / + GHES_ACPI_HEST_NOTIFY_RESERVED; + + if (physical_address && notify < GHES_ACPI_HEST_NOTIFY_RESERVED) { + error_block_addr = ges.ghes_addr_le + notify * GHES_MAX_RAW_DATA_LENGTH; + error_block_addr = le32_to_cpu(error_block_addr); + + ack_value_addr = ges.ghes_addr_le - + (GHES_ACPI_HEST_NOTIFY_RESERVED - notify) * ack_value_size; +retry: + cpu_physical_memory_read(ack_value_addr, &ack_value, ack_value_size); + if (!ack_value) { + if (loop < 3) { + usleep(100 * 1000); + loop++; + goto retry; + } else { + error_report("Last time OSPM does not acknowledge the error," + " record CPER failed this time, set the ack value to" + " avoid blocking next time CPER record! exit"); + ack_value = 1; + cpu_physical_memory_write(ack_value_addr, + &ack_value, ack_value_size); + return ret; + } + } else { + /* A zero value in ghes_addr means that BIOS has not yet written + * the address + */ + if (error_block_addr) { + ack_value = 0; + cpu_physical_memory_write(ack_value_addr, + &ack_value, ack_value_size); + ret = ghes_record_cper(error_block_addr, physical_address); + } + } + } + return ret; +} diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c index 3d78ff6..def1ec1 100644 --- a/hw/arm/virt-acpi-build.c +++ b/hw/arm/virt-acpi-build.c @@ -45,6 +45,7 @@ #include "hw/arm/virt.h" #include "sysemu/numa.h" #include "kvm_arm.h" +#include "hw/acpi/hest_ghes.h" #define ARM_SPI_BASE 32 #define ACPI_POWER_BUTTON_DEVICE "PWRB" @@ -771,6 +772,9 @@ void virt_acpi_build(VirtMachineState *vms, AcpiBuildTables *tables) acpi_add_table(table_offsets, tables_blob); build_spcr(tables_blob, tables->linker, vms); + acpi_add_table(table_offsets, tables_blob); + ghes_build_acpi(tables_blob, tables->hardware_errors, tables->linker); + if (nb_numa_nodes > 0) { acpi_add_table(table_offsets, tables_blob); build_srat(tables_blob, tables->linker, vms); @@ -887,6 +891,8 @@ void virt_acpi_setup(VirtMachineState *vms) fw_cfg_add_file(vms->fw_cfg, ACPI_BUILD_TPMLOG_FILE, tables.tcpalog->data, acpi_data_len(tables.tcpalog)); + ghes_add_fw_cfg(vms->fw_cfg, tables.hardware_errors); + build_state->rsdp_mr = acpi_add_rom_blob(build_state, tables.rsdp, ACPI_BUILD_RSDP_FILE, 0); diff --git a/include/hw/acpi/aml-build.h b/include/hw/acpi/aml-build.h index 88d0738..7f7b55c 100644 --- a/include/hw/acpi/aml-build.h +++ b/include/hw/acpi/aml-build.h @@ -211,6 +211,7 @@ struct AcpiBuildTables { GArray *rsdp; GArray *tcpalog; GArray *vmgenid; + GArray *hardware_errors; BIOSLinker *linker; } AcpiBuildTables; diff --git a/include/hw/acpi/hest_ghes.h b/include/hw/acpi/hest_ghes.h new file mode 100644 index 0000000..0772756 --- /dev/null +++ b/include/hw/acpi/hest_ghes.h @@ -0,0 +1,47 @@ +/* + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Authors: + * Dongjiu Geng + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#ifndef ACPI_GHES_H +#define ACPI_GHES_H + +#include "hw/acpi/bios-linker-loader.h" + +#define GHES_ERRORS_FW_CFG_FILE "etc/hardware_errors" +#define GHES_DATA_ADDR_FW_CFG_FILE "etc/hardware_errors_addr" + +#define GHES_GAS_ADDRESS_OFFSET 4 +#define GHES_ERROR_STATUS_ADDRESS_OFFSET 20 +#define GHES_NOTIFICATION_STRUCTURE 32 + +#define GHES_CPER_OK 1 +#define GHES_CPER_FAIL 0 + +#define GHES_ACPI_HEST_NOTIFY_RESERVED 11 +/* The max size in Bytes for one error block */ +#define GHES_MAX_RAW_DATA_LENGTH 0x1000 + + +typedef struct GhesState { + uint64_t ghes_addr_le; +} GhesState; + +void ghes_build_acpi(GArray *table_data, GArray *hardware_error, + BIOSLinker *linker); +void ghes_add_fw_cfg(FWCfgState *s, GArray *hardware_errors); +bool ghes_update_guest(uint32_t notify, uint64_t error_physical_addr); +#endif -- 1.8.3.1 From MAILER-DAEMON Fri Aug 18 11:22:21 2017 Received: from list by lists.gnu.org with archive (Exim 4.71) id 1dij6L-0002w9-9D for mharc-qemu-arm@gnu.org; Fri, 18 Aug 2017 11:22:21 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:57175) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1diiBb-0005fS-B3 for qemu-arm@nongnu.org; Fri, 18 Aug 2017 10:24:01 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1diiBJ-0002qe-6m for qemu-arm@nongnu.org; Fri, 18 Aug 2017 10:23:43 -0400 Resent-Date: Fri, 18 Aug 2017 10:23:43 -0400 Resent-Message-Id: Received: from sender-of-o52.zoho.com ([135.84.80.217]:21349) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1diiAh-0002Y5-5e; Fri, 18 Aug 2017 10:22:47 -0400 Received: from [172.17.0.2] (23.253.156.214 [23.253.156.214]) by mx.zohomail.com with SMTPS id 1503066109547237.7009217449055; Fri, 18 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MAILER-DAEMON Fri Aug 18 13:08:28 2017 Received: from list by lists.gnu.org with archive (Exim 4.71) id 1dikl1-0004r5-TC for mharc-qemu-arm@gnu.org; Fri, 18 Aug 2017 13:08:27 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:41013) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dikky-0004nz-Qs for qemu-arm@nongnu.org; Fri, 18 Aug 2017 13:08:26 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dikkv-0003QG-GD for qemu-arm@nongnu.org; Fri, 18 Aug 2017 13:08:24 -0400 Received: from mx1.redhat.com ([209.132.183.28]:58100) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1dikkv-0003Pv-9d; Fri, 18 Aug 2017 13:08:21 -0400 Received: from smtp.corp.redhat.com (int-mx02.intmail.prod.int.phx2.redhat.com [10.5.11.12]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id 524B7C0587E6; Fri, 18 Aug 2017 17:08:20 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mx1.redhat.com 524B7C0587E6 Authentication-Results: ext-mx08.extmail.prod.ext.phx2.redhat.com; dmarc=none (p=none dis=none) header.from=redhat.com Authentication-Results: ext-mx08.extmail.prod.ext.phx2.redhat.com; spf=fail smtp.mailfrom=thuth@redhat.com Received: from thh440s.redhat.com (ovpn-116-94.ams2.redhat.com [10.36.116.94]) by smtp.corp.redhat.com (Postfix) with ESMTP id DBF64784B3; Fri, 18 Aug 2017 17:08:17 +0000 (UTC) From: Thomas Huth To: Beniamino Galvani , Peter Maydell Cc: qemu-arm@nongnu.org, qemu-devel@nongnu.org, Li Guang Date: Fri, 18 Aug 2017 19:08:16 +0200 Message-Id: <1503076096-14220-1-git-send-email-thuth@redhat.com> X-Scanned-By: MIMEDefang 2.79 on 10.5.11.12 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.32]); Fri, 18 Aug 2017 17:08:20 +0000 (UTC) X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.132.183.28 Subject: [Qemu-arm] [PATCH] hw/arm/allwinner: Fix crash with -nodefaults -M cubieboard X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 18 Aug 2017 17:08:26 -0000 The allwinner-a10 device uses serial_hds[0] without checking whether it is available or not. So using the cubieboard with -nodefaults currently results in a segmentation fault. Fix it by adding a proper check here. And while we're at it, mark the device as "user_creatable = false" since this apparently can not directly be used by the users but has to be wired up in code instead. Signed-off-by: Thomas Huth --- hw/arm/allwinner-a10.c | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/hw/arm/allwinner-a10.c b/hw/arm/allwinner-a10.c index f62a9a3..e152566 100644 --- a/hw/arm/allwinner-a10.c +++ b/hw/arm/allwinner-a10.c @@ -109,8 +109,10 @@ static void aw_a10_realize(DeviceState *dev, Error **errp) sysbus_connect_irq(SYS_BUS_DEVICE(&s->sata), 0, s->irq[56]); /* FIXME use a qdev chardev prop instead of serial_hds[] */ - serial_mm_init(get_system_memory(), AW_A10_UART0_REG_BASE, 2, s->irq[1], - 115200, serial_hds[0], DEVICE_NATIVE_ENDIAN); + if (serial_hds[0]) { + serial_mm_init(get_system_memory(), AW_A10_UART0_REG_BASE, 2, s->irq[1], + 115200, serial_hds[0], DEVICE_NATIVE_ENDIAN); + } } static void aw_a10_class_init(ObjectClass *oc, void *data) @@ -118,6 +120,8 @@ static void aw_a10_class_init(ObjectClass *oc, void *data) DeviceClass *dc = DEVICE_CLASS(oc); dc->realize = aw_a10_realize; + /* Reason: Needs to be wired up in code, see cubieboard_init() */ + dc->user_creatable = false; } static const TypeInfo aw_a10_type_info = { -- 1.8.3.1 From MAILER-DAEMON Fri Aug 18 13:14:36 2017 Received: from list by lists.gnu.org with archive (Exim 4.71) id 1dikqy-0001NX-90 for mharc-qemu-arm@gnu.org; Fri, 18 Aug 2017 13:14:36 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:42659) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dikqu-0001KA-T8 for qemu-arm@nongnu.org; Fri, 18 Aug 2017 13:14:34 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dikqu-0006Jh-16 for qemu-arm@nongnu.org; Fri, 18 Aug 2017 13:14:32 -0400 Received: from mail-wm0-x22e.google.com ([2a00:1450:400c:c09::22e]:36205) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1dikqt-0006Ij-PB for qemu-arm@nongnu.org; Fri, 18 Aug 2017 13:14:31 -0400 Received: by mail-wm0-x22e.google.com with SMTP id t201so4640836wmt.1 for ; Fri, 18 Aug 2017 10:14:30 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:in-reply-to:references:from:date:message-id:subject:to :cc; bh=gUxuPjrMrUPvjVT0VQgSMlJi092oU46Ayg4B9wq89V8=; b=Ig8Rj4S9lHXrHzAYLZbESDw/iQeKdacSXas6yOrJDw9k9KsHtG15Qui0SACD76SU/f 32zWf4m9aZI9KG0MGVy7TRFStt2K5XPMumi0Wat0VGUl/iDAJ7Qpi0moJ6h9Nb5NMcW6 R/1b0V5VRMBWep/QiTy5Yw490IgEG0Vp65tWU= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:in-reply-to:references:from:date :message-id:subject:to:cc; bh=gUxuPjrMrUPvjVT0VQgSMlJi092oU46Ayg4B9wq89V8=; b=Cj4aJ3eAsFYxPkaqv9DaAbOzTi7qTCnUIA9t0t5RatBAyElVv+nIpIidC1dqA/76il Zm1ZyGm+gmBE2sbAC0Nvza15m85Be0+yfm8HbLk6qpQ2PcV/EmyDffe7w1nnJ/BI4bOK BkLzDf4hWFBHKk10HTlniv2zVWZc61oW/iQXxwsVoA4RpWqVbeikTD72pYOpLU3fz8Ov s9rAVBgrCPPQxEdusx9ft1IZjY+JBjVhOttrIX5pkvYtaq4LiU8+J1xbzzXoKM0h8+XG 3QsQ5VlnmVnBh+gyMaU0H+RJGGD/fTiVOzMCYdwsjepAoyD4MfYe8anIS4/ssZv4/yxp ZCuw== X-Gm-Message-State: AHYfb5jyMJnCAKMBRe4Pt5hBK8l+GeBZYqR13XEZVSEFhSdiZDUM14eO 6Bw/G60xI0UX9O+rCQNKVrG9yNHYELJS X-Received: by 10.28.22.205 with SMTP id 196mr1763701wmw.39.1503076469359; Fri, 18 Aug 2017 10:14:29 -0700 (PDT) MIME-Version: 1.0 Received: by 10.223.134.54 with HTTP; Fri, 18 Aug 2017 10:14:08 -0700 (PDT) In-Reply-To: <1503076096-14220-1-git-send-email-thuth@redhat.com> References: <1503076096-14220-1-git-send-email-thuth@redhat.com> From: Peter Maydell Date: Fri, 18 Aug 2017 18:14:08 +0100 Message-ID: To: Thomas Huth Cc: Beniamino Galvani , qemu-arm , QEMU Developers , Li Guang Content-Type: text/plain; charset="UTF-8" X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:400c:c09::22e Subject: Re: [Qemu-arm] [PATCH] hw/arm/allwinner: Fix crash with -nodefaults -M cubieboard X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 18 Aug 2017 17:14:34 -0000 On 18 August 2017 at 18:08, Thomas Huth wrote: > The allwinner-a10 device uses serial_hds[0] without checking whether > it is available or not. So using the cubieboard with -nodefaults > currently results in a segmentation fault. Fix it by adding a > proper check here. > And while we're at it, mark the device as "user_creatable = false" > since this apparently can not directly be used by the users but has > to be wired up in code instead. > > Signed-off-by: Thomas Huth > --- > hw/arm/allwinner-a10.c | 8 ++++++-- > 1 file changed, 6 insertions(+), 2 deletions(-) > > diff --git a/hw/arm/allwinner-a10.c b/hw/arm/allwinner-a10.c > index f62a9a3..e152566 100644 > --- a/hw/arm/allwinner-a10.c > +++ b/hw/arm/allwinner-a10.c > @@ -109,8 +109,10 @@ static void aw_a10_realize(DeviceState *dev, Error **errp) > sysbus_connect_irq(SYS_BUS_DEVICE(&s->sata), 0, s->irq[56]); > > /* FIXME use a qdev chardev prop instead of serial_hds[] */ > - serial_mm_init(get_system_memory(), AW_A10_UART0_REG_BASE, 2, s->irq[1], > - 115200, serial_hds[0], DEVICE_NATIVE_ENDIAN); > + if (serial_hds[0]) { > + serial_mm_init(get_system_memory(), AW_A10_UART0_REG_BASE, 2, s->irq[1], > + 115200, serial_hds[0], DEVICE_NATIVE_ENDIAN); > + } This doesn't look like the right fix, because it means that there won't be a UART device at that point in system memory at all. What you want is for there to be a UART device there but not connected to anything, ie serial_mm_init() should cope with being passed a NULL Chardev*. thanks -- PMM From MAILER-DAEMON Sun Aug 20 21:21:47 2017 Received: from list by lists.gnu.org with archive (Exim 4.71) id 1djbPX-0006O7-LH for mharc-qemu-arm@gnu.org; Sun, 20 Aug 2017 21:21:47 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:36369) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1djbPT-0006M7-Nx for qemu-arm@nongnu.org; Sun, 20 Aug 2017 21:21:45 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1djbPL-0001kB-9R for qemu-arm@nongnu.org; Sun, 20 Aug 2017 21:21:39 -0400 Received: from mail-pg0-x241.google.com ([2607:f8b0:400e:c05::241]:32979) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1djbPK-0001fI-U2; Sun, 20 Aug 2017 21:21:35 -0400 Received: by mail-pg0-x241.google.com with SMTP id n4so6460927pgn.0; Sun, 20 Aug 2017 18:21:33 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=date:from:to:cc:subject:message-id:references:mime-version :content-disposition:in-reply-to:user-agent; bh=TtQBd1eF2MqyAKcFwBya+yhvvcb5qvzMBFTcTV5t7k0=; b=Of6kqYcWtph7JlGATZCSTVT9oV1YtOW8QhYtiv2pNRLrQ3GuqXh3QZWKnnAT1MYalH BhYsY43tx/oIZzlUUafPXj+Ko560hGYphkVSVwGwQGT7r9uyYUEqqcY+mvepcl7BZEge VfVy0AwVNCfbl145cKSB0L16jwQGB45nOv+gaII+sdKevoDfsW0Y7Uf2Q+JGNb552uN0 m/QcsBR+B1GPkHrT8wYrXnLjLEDpmSyDoluAzvFgayXyuMuX9WAIP9+HmL69NVZcRY3o ib7Mawmg8Ps3n7lOkqjXn2vhAShyNnYOm6nx0H33uMJxF2VvWlypJZmrmrQrMOoe9Yfx 2WDg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:in-reply-to:user-agent; bh=TtQBd1eF2MqyAKcFwBya+yhvvcb5qvzMBFTcTV5t7k0=; b=XwIr5e+EphyVOTL/0kWrunxjtS9jI2P8uy1h/n2tPL983iAUevmd9gpvOOEycoOGrj riNs4bSPazYzPtcMGj30YjwIMEbgIJugFN7c48wWecdgnPqzTxEWJzBzP24g5JtyZYJL fVTpVC1JvdBEInvkjPUJIardeW+yUkAYGQwGjHM+AlcBsN9Opw3CBo4kuko69tZEOZWW 4n54HqH9dXvE/rmcGNwPU7p8l6Y7CHJu2+qMsvm6Kt401d9/akwqp8xrqXeZZBPTDGTZ Z/Z2mW7GrZO7GV1VST7LH5zX67qzYl1BX2uek7S5wzBrgmDa5NQNZ6x6In5wKaIUoz6y j8yQ== X-Gm-Message-State: AHYfb5gKdB44kMJ953jrS5gcVmyaT3MG4GGPqk2e3bI20NIs44CVCdbi 2tX2Je2aGnnQ9A== X-Received: by 10.84.172.1 with SMTP id m1mr17195131plb.174.1503278492354; Sun, 20 Aug 2017 18:21:32 -0700 (PDT) Received: from virtx40 ([111.93.218.67]) by smtp.gmail.com with ESMTPSA id p10sm20043380pfk.103.2017.08.20.18.21.26 (version=TLS1_2 cipher=AES128-SHA bits=128/128); Sun, 20 Aug 2017 18:21:31 -0700 (PDT) Date: Mon, 21 Aug 2017 06:51:13 +0530 From: Linu Cherian To: Eric Auger Cc: eric.auger.pro@gmail.com, peter.maydell@linaro.org, qemu-arm@nongnu.org, qemu-devel@nongnu.org, alex.williamson@redhat.com, prem.mallappa@gmail.com, mohun106@gmail.com, drjones@redhat.com, tcain@qti.qualcomm.com, Radha.Chintakuntla@cavium.com, Sunil.Goutham@cavium.com, mst@redhat.com, jean-philippe.brucker@arm.com, tn@semihalf.com, will.deacon@arm.com, robin.murphy@arm.com, peterx@redhat.com, bharat.bhushan@nxp.com, christoffer.dall@linaro.org Message-ID: <20170821012113.GA12220@virtx40> References: <1502461354-11327-1-git-send-email-eric.auger@redhat.com> <1502461354-11327-9-git-send-email-eric.auger@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1502461354-11327-9-git-send-email-eric.auger@redhat.com> User-Agent: Mutt/1.5.21 (2010-09-15) X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::241 Subject: Re: [Qemu-arm] [RFC v6 8/9] hw/arm/smmuv3: VFIO integration X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 21 Aug 2017 01:21:46 -0000 Hi Eric, On Fri Aug 11, 2017 at 04:22:33PM +0200, Eric Auger wrote: > This patch allows doing PCIe passthrough with a guest exposed > with a vSMMUv3. It implements the replay and notify_flag_changed > iommu ops. Also on TLB and data structure invalidation commands, > we replay the mappings so that the physical IOMMU implements > updated stage 1 settings (Guest IOVA -> Guest PA) + stage 2 settings. > > This works only if the guest smmuv3 driver implements the > "tlbi-on-map" option. > > Signed-off-by: Eric Auger > Appreciate if you could point to some documentation that explains the attach, detach, map,unmap flows for a passthrough device with emulated IOMMU. Thanks. > --- > > v5 -> v6: > - use IOMMUMemoryRegion > - handle implementation defined SMMU_CMD_TLBI_NH_VA_AM cmd > (goes along with TLBI_ON_MAP FW quirk) > - replay systematically unmap the whole range first > - smmuv3_map_hook does not unmap anymore and the unmap is done > before the replay > - add and use smmuv3_context_device_invalidate instead of > blindly replaying everything > --- > hw/arm/smmuv3-internal.h | 1 + > hw/arm/smmuv3.c | 265 ++++++++++++++++++++++++++++++++++++++++++++++- > hw/arm/trace-events | 14 +++ > 3 files changed, 277 insertions(+), 3 deletions(-) > > diff --git a/hw/arm/smmuv3-internal.h b/hw/arm/smmuv3-internal.h > index e255df1..ac4628f 100644 > --- a/hw/arm/smmuv3-internal.h > +++ b/hw/arm/smmuv3-internal.h > @@ -344,6 +344,7 @@ enum { > SMMU_CMD_RESUME = 0x44, > SMMU_CMD_STALL_TERM, > SMMU_CMD_SYNC, /* 0x46 */ > + SMMU_CMD_TLBI_NH_VA_AM = 0x8F, /* VIOMMU Impl Defined */ > }; > > static const char *cmd_stringify[] = { > diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c > index e195a0e..89fb116 100644 > --- a/hw/arm/smmuv3.c > +++ b/hw/arm/smmuv3.c > @@ -25,6 +25,7 @@ > #include "exec/address-spaces.h" > #include "trace.h" > #include "qemu/error-report.h" > +#include "exec/target_page.h" > > #include "hw/arm/smmuv3.h" > #include "smmuv3-internal.h" > @@ -143,6 +144,71 @@ static MemTxResult smmu_read_cmdq(SMMUV3State *s, Cmd *cmd) > return ret; > } > > +static void smmuv3_replay_all(SMMUState *s) > +{ > + SMMUNotifierNode *node; > + > + QLIST_FOREACH(node, &s->notifiers_list, next) { > + trace_smmuv3_replay_all(node->sdev->iommu.parent_obj.name); > + memory_region_iommu_replay_all(&node->sdev->iommu); > + } > +} > + > +/* Replay the mappings for a given streamid */ > +static void smmuv3_context_device_invalidate(SMMUState *s, uint16_t sid) > +{ > + uint8_t bus_n, devfn; > + SMMUPciBus *smmu_bus; > + SMMUDevice *smmu; > + > + trace_smmuv3_context_device_invalidate(sid); > + bus_n = PCI_BUS_NUM(sid); > + smmu_bus = smmu_find_as_from_bus_num(s, bus_n); > + if (smmu_bus) { > + devfn = PCI_FUNC(sid); > + smmu = smmu_bus->pbdev[devfn]; > + if (smmu) { > + memory_region_iommu_replay_all(&smmu->iommu); > + } > + } > +} > + > +static void smmuv3_replay_single(IOMMUMemoryRegion *mr, IOMMUNotifier *n, > + uint64_t iova); > + > +static void smmuv3_replay_range(IOMMUMemoryRegion *mr, IOMMUNotifier *n, > + uint64_t iova, size_t nb_pages); > + > +static void smmuv3_notify_single(SMMUState *s, uint64_t iova) > +{ > + SMMUNotifierNode *node; > + > + QLIST_FOREACH(node, &s->notifiers_list, next) { > + IOMMUMemoryRegion *mr = &node->sdev->iommu; > + IOMMUNotifier *n; > + > + trace_smmuv3_notify_all(node->sdev->iommu.parent_obj.name, iova); > + IOMMU_NOTIFIER_FOREACH(n, mr) { > + smmuv3_replay_single(mr, n, iova); > + } > + } > +} > + > +static void smmuv3_notify_range(SMMUState *s, uint64_t iova, size_t size) > +{ > + SMMUNotifierNode *node; > + > + QLIST_FOREACH(node, &s->notifiers_list, next) { > + IOMMUMemoryRegion *mr = &node->sdev->iommu; > + IOMMUNotifier *n; > + > + trace_smmuv3_notify_all(node->sdev->iommu.parent_obj.name, iova); > + IOMMU_NOTIFIER_FOREACH(n, mr) { > + smmuv3_replay_range(mr, n, iova, size); > + } > + } > +} > + > static int smmu_cmdq_consume(SMMUV3State *s) > { > uint32_t error = SMMU_CMD_ERR_NONE; > @@ -178,28 +244,38 @@ static int smmu_cmdq_consume(SMMUV3State *s) > break; > case SMMU_CMD_PREFETCH_CONFIG: > case SMMU_CMD_PREFETCH_ADDR: > + break; > case SMMU_CMD_CFGI_STE: > { > uint32_t streamid = cmd.word[1]; > > trace_smmuv3_cmdq_cfgi_ste(streamid); > - break; > + smmuv3_context_device_invalidate(&s->smmu_state, streamid); > + break; > } > case SMMU_CMD_CFGI_STE_RANGE: /* same as SMMU_CMD_CFGI_ALL */ > { > - uint32_t start = cmd.word[1], range, end; > + uint32_t start = cmd.word[1], range, end, i; > > range = extract32(cmd.word[2], 0, 5); > end = start + (1 << (range + 1)) - 1; > trace_smmuv3_cmdq_cfgi_ste_range(start, end); > + for (i = start; i <= end; i++) { > + smmuv3_context_device_invalidate(&s->smmu_state, i); > + } > break; > } > case SMMU_CMD_CFGI_CD: > case SMMU_CMD_CFGI_CD_ALL: > + { > + uint32_t streamid = cmd.word[1]; > + > + smmuv3_context_device_invalidate(&s->smmu_state, streamid); > break; > + } > case SMMU_CMD_TLBI_NH_ALL: > case SMMU_CMD_TLBI_NH_ASID: > - printf("%s TLBI* replay\n", __func__); > + smmuv3_replay_all(&s->smmu_state); > break; > case SMMU_CMD_TLBI_NH_VA: > { > @@ -210,6 +286,20 @@ static int smmu_cmdq_consume(SMMUV3State *s) > uint64_t addr = high << 32 | (low << 12); > > trace_smmuv3_cmdq_tlbi_nh_va(asid, vmid, addr); > + smmuv3_notify_single(&s->smmu_state, addr); > + break; > + } > + case SMMU_CMD_TLBI_NH_VA_AM: > + { > + int asid = extract32(cmd.word[1], 16, 16); > + int am = extract32(cmd.word[1], 0, 16); > + uint64_t low = extract32(cmd.word[2], 12, 20); > + uint64_t high = cmd.word[3]; > + uint64_t addr = high << 32 | (low << 12); > + size_t size = am << 12; > + > + trace_smmuv3_cmdq_tlbi_nh_va_am(asid, am, addr, size); > + smmuv3_notify_range(&s->smmu_state, addr, size); > break; > } > case SMMU_CMD_TLBI_NH_VAA: > @@ -222,6 +312,7 @@ static int smmu_cmdq_consume(SMMUV3State *s) > case SMMU_CMD_TLBI_S12_VMALL: > case SMMU_CMD_TLBI_S2_IPA: > case SMMU_CMD_TLBI_NSNH_ALL: > + smmuv3_replay_all(&s->smmu_state); > break; > case SMMU_CMD_ATC_INV: > case SMMU_CMD_PRI_RESP: > @@ -804,6 +895,172 @@ out: > return entry; > } > > +static int smmuv3_replay_hook(IOMMUTLBEntry *entry, void *private) > +{ > + trace_smmuv3_replay_hook(entry->iova, entry->translated_addr, > + entry->addr_mask, entry->perm); > + memory_region_notify_one((IOMMUNotifier *)private, entry); > + return 0; > +} > + > +static int smmuv3_map_hook(IOMMUTLBEntry *entry, void *private) > +{ > + trace_smmuv3_map_hook(entry->iova, entry->translated_addr, > + entry->addr_mask, entry->perm); > + memory_region_notify_one((IOMMUNotifier *)private, entry); > + return 0; > +} > + > +/* Unmap the whole range in the notifier's scope. */ > +static void smmuv3_unmap_notifier(SMMUDevice *sdev, IOMMUNotifier *n) > +{ > + IOMMUTLBEntry entry; > + hwaddr size; > + hwaddr start = n->start; > + hwaddr end = n->end; > + > + size = end - start + 1; > + > + entry.target_as = &address_space_memory; > + /* Adjust iova for the size */ > + entry.iova = n->start & ~(size - 1); > + /* This field is meaningless for unmap */ > + entry.translated_addr = 0; > + entry.perm = IOMMU_NONE; > + entry.addr_mask = size - 1; > + > + /* TODO: check start/end/size/mask */ > + > + trace_smmuv3_unmap_notifier(pci_bus_num(sdev->bus), > + PCI_SLOT(sdev->devfn), > + PCI_FUNC(sdev->devfn), > + entry.iova, size); > + > + memory_region_notify_one(n, &entry); > +} > + > +static void smmuv3_replay(IOMMUMemoryRegion *mr, IOMMUNotifier *n) > +{ > + SMMUDevice *sdev = container_of(mr, SMMUDevice, iommu); > + SMMUV3State *s = sdev->smmu; > + SMMUBaseClass *sbc = SMMU_DEVICE_GET_CLASS(s); > + SMMUTransCfg cfg = {}; > + int ret; > + > + smmuv3_unmap_notifier(sdev, n); > + > + ret = smmuv3_decode_config(mr, &cfg); > + if (ret) { > + error_report("%s error decoding the configuration for iommu mr=%s", > + __func__, mr->parent_obj.name); > + } > + > + if (cfg.disabled || cfg.bypassed) { > + return; > + } > + /* is the smmu enabled */ > + sbc->page_walk_64(&cfg, 0, (1ULL << (64 - cfg.tsz)) - 1, false, > + smmuv3_replay_hook, n); > +} > +static void smmuv3_replay_range(IOMMUMemoryRegion *mr, IOMMUNotifier *n, > + uint64_t iova, size_t size) > +{ > + SMMUDevice *sdev = container_of(mr, SMMUDevice, iommu); > + SMMUV3State *s = sdev->smmu; > + SMMUBaseClass *sbc = SMMU_DEVICE_GET_CLASS(s); > + SMMUTransCfg cfg = {}; > + IOMMUTLBEntry entry; > + int ret; > + > + trace_smmuv3_replay_range(mr->parent_obj.name, iova, size, n); > + ret = smmuv3_decode_config(mr, &cfg); > + if (ret) { > + error_report("%s error decoding the configuration for iommu mr=%s", > + __func__, mr->parent_obj.name); > + } > + > + if (cfg.disabled || cfg.bypassed) { > + return; > + } > + > + /* first unmap */ > + entry.target_as = &address_space_memory; > + entry.iova = iova & ~(size - 1); > + entry.addr_mask = size - 1; > + entry.perm = IOMMU_NONE; > + > + memory_region_notify_one(n, &entry); > + > + /* then figure out if a new mapping needs to be applied */ > + sbc->page_walk_64(&cfg, iova, iova + entry.addr_mask , false, > + smmuv3_map_hook, n); > +} > + > +static void smmuv3_replay_single(IOMMUMemoryRegion *mr, IOMMUNotifier *n, > + uint64_t iova) > +{ > + SMMUDevice *sdev = container_of(mr, SMMUDevice, iommu); > + SMMUV3State *s = sdev->smmu; > + size_t target_page_size = qemu_target_page_size(); > + SMMUBaseClass *sbc = SMMU_DEVICE_GET_CLASS(s); > + SMMUTransCfg cfg = {}; > + IOMMUTLBEntry entry; > + int ret; > + > + trace_smmuv3_replay_single(mr->parent_obj.name, iova, n); > + ret = smmuv3_decode_config(mr, &cfg); > + if (ret) { > + error_report("%s error decoding the configuration for iommu mr=%s", > + __func__, mr->parent_obj.name); > + } > + > + if (cfg.disabled || cfg.bypassed) { > + return; > + } > + > + /* first unmap */ > + entry.target_as = &address_space_memory; > + entry.iova = iova & ~(target_page_size - 1); > + entry.addr_mask = target_page_size - 1; > + entry.perm = IOMMU_NONE; > + > + memory_region_notify_one(n, &entry); > + > + /* then figure out if a new mapping needs to be applied */ > + sbc->page_walk_64(&cfg, iova, iova + 1, false, > + smmuv3_map_hook, n); > +} > + > +static void smmuv3_notify_flag_changed(IOMMUMemoryRegion *iommu, > + IOMMUNotifierFlag old, > + IOMMUNotifierFlag new) > +{ > + SMMUDevice *sdev = container_of(iommu, SMMUDevice, iommu); > + SMMUV3State *s3 = sdev->smmu; > + SMMUState *s = &(s3->smmu_state); > + SMMUNotifierNode *node = NULL; > + SMMUNotifierNode *next_node = NULL; > + > + if (old == IOMMU_NOTIFIER_NONE) { > + trace_smmuv3_notify_flag_add(iommu->parent_obj.name); > + node = g_malloc0(sizeof(*node)); > + node->sdev = sdev; > + QLIST_INSERT_HEAD(&s->notifiers_list, node, next); > + return; > + } > + > + /* update notifier node with new flags */ > + QLIST_FOREACH_SAFE(node, &s->notifiers_list, next, next_node) { > + if (node->sdev == sdev) { > + if (new == IOMMU_NOTIFIER_NONE) { > + trace_smmuv3_notify_flag_del(iommu->parent_obj.name); > + QLIST_REMOVE(node, next); > + g_free(node); > + } > + return; > + } > + } > +} > > static inline void smmu_update_base_reg(SMMUV3State *s, uint64_t *base, > uint64_t val) > @@ -1125,6 +1382,8 @@ static void smmuv3_iommu_memory_region_class_init(ObjectClass *klass, > IOMMUMemoryRegionClass *imrc = IOMMU_MEMORY_REGION_CLASS(klass); > > imrc->translate = smmuv3_translate; > + imrc->notify_flag_changed = smmuv3_notify_flag_changed; > + imrc->replay = smmuv3_replay; > } > > static const TypeInfo smmuv3_type_info = { > diff --git a/hw/arm/trace-events b/hw/arm/trace-events > index f9b9cbe..8228e26 100644 > --- a/hw/arm/trace-events > +++ b/hw/arm/trace-events > @@ -27,6 +27,7 @@ smmuv3_cmdq_opcode(const char *opcode) "<--- %s" > smmuv3_cmdq_cfgi_ste(int streamid) " |_ streamid =%d" > smmuv3_cmdq_cfgi_ste_range(int start, int end) " |_ start=0x%d - end=0x%d" > smmuv3_cmdq_tlbi_nh_va(int asid, int vmid, uint64_t addr) " |_ asid =%d vmid =%d addr=0x%"PRIx64 > +smmuv3_cmdq_tlbi_nh_va_am(int asid, int am, size_t size, uint64_t addr) " |_ asid =%d am =%d size=0x%lx addr=0x%"PRIx64 > smmuv3_cmdq_consume_sev(void) "CMD_SYNC CS=SEV not supported, ignoring" > smmuv3_cmdq_consume_out(uint8_t prod_wrap, uint32_t prod, uint8_t cons_wrap, uint32_t cons) "prod_wrap:%d, prod:0x%x cons_wrap:%d cons:0x%x" > smmuv3_update(bool is_empty, uint32_t prod, uint32_t cons, uint8_t prod_wrap, uint8_t cons_wrap) "q empty:%d prod:%d cons:%d p.wrap:%d p.cons:%d" > @@ -50,3 +51,16 @@ smmuv3_dump_ste(int i, uint32_t word0, int j, uint32_t word1) "STE[%2d]: 0x%x\t > smmuv3_dump_cd(int i, uint32_t word0, int j, uint32_t word1) "CD[%2d]: 0x%x\t CD[%2d]: 0x%x" > smmuv3_dump_cmd(int i, uint32_t word0, int j, uint32_t word1) "CMD[%2d]: 0x%x\t CMD[%2d]: 0x%x" > smmuv3_cfg_stage(int s, uint32_t oas, uint32_t tsz, uint64_t ttbr, bool aa64, uint32_t granule_sz, int initial_level) "TransCFG stage:%d oas:%d tsz:%d ttbr:0x%"PRIx64" aa64:%d granule_sz:%d, initial_level = %d" > + > +smmuv3_replay(uint16_t sid, bool enabled) "sid=%d, enabled=%d" > +smmuv3_replay_hook(hwaddr iova, hwaddr pa, hwaddr mask, int perm) "iova=0x%"PRIx64" pa=0x%" PRIx64" mask=0x%"PRIx64" perm=%d" > +smmuv3_map_hook(hwaddr iova, hwaddr pa, hwaddr mask, int perm) "iova=0x%"PRIx64" pa=0x%" PRIx64" mask=0x%"PRIx64" perm=%d" > +smmuv3_notify_flag_add(const char *iommu) "ADD SMMUNotifier node for iommu mr=%s" > +smmuv3_notify_flag_del(const char *iommu) "DEL SMMUNotifier node for iommu mr=%s" > +smmuv3_replay_single(const char *name, uint64_t iova, void *n) "iommu mr=%s iova=0x%"PRIx64" n=%p" > +smmuv3_replay_range(const char *name, uint64_t iova, size_t size, void *n) "iommu mr=%s iova=0x%"PRIx64" size=0x%lx n=%p" > +smmuv3_replay_all(const char *name) "iommu mr=%s" > +smmuv3_notify_all(const char *name, uint64_t iova) "iommu mr=%s iova=0x%"PRIx64 > +smmuv3_unmap_notifier(uint8_t bus, uint8_t slot, uint8_t fn, uint64_t iova, uint64_t size) "Device %02x:%02x.%x start 0x%"PRIx64" size 0x%"PRIx64 > +smmuv3_context_device_invalidate(uint32_t sid) "sid=%d" > + > -- > 2.5.5 > > -- Linu cherian From MAILER-DAEMON Mon Aug 21 06:51:54 2017 Received: from list by lists.gnu.org with archive (Exim 4.71) id 1djkJG-0006HY-Kr for mharc-qemu-arm@gnu.org; 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Ip=[192.88.168.50]; Helo=[tx30smr01.am.freescale.net] X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MWHPR03MB3327 X-detected-operating-system: by eggs.gnu.org: Windows 7 or 8 [fuzzy] X-Received-From: 104.47.37.65 Subject: [Qemu-arm] [PATCH v3 0/2] virtio-iommu: VFIO integration X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 21 Aug 2017 10:51:52 -0000 This V3 version is mainly about rebasing on v3 version on Virtio-iommu device framework from Eric Augur and addresing review comments. This patch series allows PCI pass-through using virtio-iommu. This series is based on: - virtio-iommu specification written by Jean-Philippe Brucker [RFC 0/3] virtio-iommu: a paravirtualized IOMMU, - virtio-iommu driver by Jean-Philippe Brucker [RFC PATCH linux] iommu: Add virtio-iommu driver - virtio-iommu device emulation by Eric Augur. [RFC v3 0/8] VIRTIO-IOMMU device PCI device pass-through and virtio-net-pci is tested with these changes using dma-ops This patch series does not implement RESV_MEM changes proposal by Jean-Philippe "https://lists.gnu.org/archive/html/qemu-devel/2017-07/msg01796.html" v2->v3: - This series is based on "[RFC v3 0/8] VIRTIO-IOMMU device" Which is based on top of v2.10-rc0 that - Fixed issue with two PCI devices - Addressed review comments v1->v2: - Added trace events - removed vSMMU3 link in patch description Bharat Bhushan (2): target/arm/kvm: Translate the MSI doorbell in kvm_arch_fixup_msi_route virtio-iommu: vfio integration with virtio-iommu hw/virtio/trace-events | 5 ++ hw/virtio/virtio-iommu.c | 163 +++++++++++++++++++++++++++++++++++++++ include/hw/virtio/virtio-iommu.h | 6 ++ target/arm/kvm.c | 27 +++++++ target/arm/trace-events | 3 + 5 files changed, 204 insertions(+) -- 1.9.3 From MAILER-DAEMON Mon Aug 21 06:52:00 2017 Received: from list by lists.gnu.org with archive (Exim 4.71) id 1djkJM-0006Nv-L3 for mharc-qemu-arm@gnu.org; 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Ip=[192.88.168.50]; Helo=[tx30smr01.am.freescale.net] X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BN3PR03MB2259 X-detected-operating-system: by eggs.gnu.org: Windows 7 or 8 [fuzzy] X-Received-From: 104.47.37.62 Subject: [Qemu-arm] [PATCH v3 1/2] target/arm/kvm: Translate the MSI doorbell in kvm_arch_fixup_msi_route X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 21 Aug 2017 10:51:59 -0000 Translate msi address if device is behind virtio-iommu. This logic is similar to vSMMUv3/Intel iommu emulation. This RFC patch does not handle the case where both vsmmuv3 and virtio-iommu are available. Signed-off-by: Eric Auger Signed-off-by: Bharat Bhushan --- v2->v3: - Rebased to on top of 2.10-rc0 and especially [PATCH qemu v9 0/2] memory/iommu: QOM'fy IOMMU MemoryRegion v1-v2: - Added trace events - removed vSMMU3 link in patch description target/arm/kvm.c | 27 +++++++++++++++++++++++++++ target/arm/trace-events | 3 +++ 2 files changed, 30 insertions(+) diff --git a/target/arm/kvm.c b/target/arm/kvm.c index 7c17f0d..0219c9d 100644 --- a/target/arm/kvm.c +++ b/target/arm/kvm.c @@ -21,7 +21,11 @@ #include "kvm_arm.h" #include "cpu.h" #include "internals.h" +#include "trace.h" #include "hw/arm/arm.h" +#include "hw/pci/pci.h" +#include "hw/pci/msi.h" +#include "hw/virtio/virtio-iommu.h" #include "exec/memattrs.h" #include "exec/address-spaces.h" #include "hw/boards.h" @@ -662,6 +666,29 @@ int kvm_arm_vgic_probe(void) int kvm_arch_fixup_msi_route(struct kvm_irq_routing_entry *route, uint64_t address, uint32_t data, PCIDevice *dev) { + AddressSpace *as = pci_device_iommu_address_space(dev); + IOMMUTLBEntry entry; + IOMMUDevice *sdev; + IOMMUMemoryRegionClass *imrc; + + if (as == &address_space_memory) { + return 0; + } + + /* MSI doorbell address is translated by an IOMMU */ + sdev = container_of(as, IOMMUDevice, as); + + imrc = memory_region_get_iommu_class_nocheck(&sdev->iommu_mr); + + entry = imrc->translate(&sdev->iommu_mr, address, IOMMU_WO); + + route->u.msi.address_lo = entry.translated_addr; + route->u.msi.address_hi = entry.translated_addr >> 32; + + trace_kvm_arm_fixup_msi_route(address, sdev->devfn, + sdev->iommu_mr.parent_obj.name, + entry.translated_addr); + return 0; } diff --git a/target/arm/trace-events b/target/arm/trace-events index e21c84f..eff2822 100644 --- a/target/arm/trace-events +++ b/target/arm/trace-events @@ -8,3 +8,6 @@ arm_gt_tval_write(int timer, uint64_t value) "gt_tval_write: timer %d value %" P arm_gt_ctl_write(int timer, uint64_t value) "gt_ctl_write: timer %d value %" PRIx64 arm_gt_imask_toggle(int timer, int irqstate) "gt_ctl_write: timer %d IMASK toggle, new irqstate %d" arm_gt_cntvoff_write(uint64_t value) "gt_cntvoff_write: value %" PRIx64 + +# target/arm/kvm.c +kvm_arm_fixup_msi_route(uint64_t iova, uint32_t devid, const char *name, uint64_t gpa) "MSI addr = 0x%"PRIx64" is translated for devfn=%d through %s into 0x%"PRIx64 -- 1.9.3 From MAILER-DAEMON Mon Aug 21 06:52:11 2017 Received: from list by lists.gnu.org with archive (Exim 4.71) id 1djkJX-0006Vl-8v for mharc-qemu-arm@gnu.org; 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Ip=[192.88.168.50]; Helo=[tx30smr01.am.freescale.net] X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CO2PR03MB2264 X-detected-operating-system: by eggs.gnu.org: Windows 7 or 8 [fuzzy] X-Received-From: 104.47.32.48 Subject: [Qemu-arm] [PATCH v3 2/2] virtio-iommu: vfio integration with virtio-iommu X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 21 Aug 2017 10:52:09 -0000 This RFC patch allows virtio-iommu protection for PCI device-passthrough. MSI region is mapped by current version of virtio-iommu driver. This uses VFIO extension of map/unmap notification when an area of memory is mappedi/unmapped in emulated iommu device. This series is tested with 2 PCI devices to virtual machine using dma-ops and DPDK in VM is not yet tested. Also with this series we observe below prints for MSI region mapping "qemu-system-aarch64: iommu map to non memory area 0" This print comes when vfio/map-notifier is called for MSI region. vfio map/unmap notification is called for given device This assumes that devid passed in virtio_iommu_attach is same as devfn This assumption is based on 1:1 mapping of requested-id with device-id in QEMU. Signed-off-by: Bharat Bhushan --- v2->v3: - Addressed review comments: - virtio-iommu_map_region function is split in two functions virtio_iommu_notify_map/virtio_iommu_notify_unmap - use size received from driver and do not split in 4K pages - map/unmap notification is called for given device/as This relies on devid passed in virtio_iommu_attach is same as devfn This is assumed as iommu-map maps 1:1 requested-id to device-id in QEMU Looking for comment about this assumtion. - Keeping track devices in address-space - Verified with 2 PCI endpoints - some code cleanup hw/virtio/trace-events | 5 ++ hw/virtio/virtio-iommu.c | 163 +++++++++++++++++++++++++++++++++++++++ include/hw/virtio/virtio-iommu.h | 6 ++ 3 files changed, 174 insertions(+) diff --git a/hw/virtio/trace-events b/hw/virtio/trace-events index 8db3d91..7e9663f 100644 --- a/hw/virtio/trace-events +++ b/hw/virtio/trace-events @@ -39,3 +39,8 @@ virtio_iommu_unmap_left_interval(uint64_t low, uint64_t high, uint64_t next_low, virtio_iommu_unmap_right_interval(uint64_t low, uint64_t high, uint64_t next_low, uint64_t next_high) "Unmap right [0x%"PRIx64",0x%"PRIx64"], new interval=[0x%"PRIx64",0x%"PRIx64"]" virtio_iommu_unmap_inc_interval(uint64_t low, uint64_t high) "Unmap inc [0x%"PRIx64",0x%"PRIx64"]" virtio_iommu_translate_result(uint64_t virt_addr, uint64_t phys_addr, uint32_t sid) "0x%"PRIx64" -> 0x%"PRIx64 " for sid=%d" +virtio_iommu_notify_flag_add(const char *iommu) "Add virtio-iommu notifier node for memory region %s" +virtio_iommu_notify_flag_del(const char *iommu) "Del virtio-iommu notifier node for memory region %s" +virtio_iommu_remap(hwaddr iova, hwaddr pa, hwaddr size) "iova=0x%"PRIx64" pa=0x%" PRIx64" size=0x%"PRIx64"" +virtio_iommu_notify_map(hwaddr iova, hwaddr paddr, hwaddr map_size) "iova=0x%"PRIx64" pa=0x%" PRIx64" size=0x%"PRIx64"" +virtio_iommu_notify_unmap(hwaddr iova, hwaddr paddr, hwaddr map_size) "iova=0x%"PRIx64" pa=0x%" PRIx64" size=0x%"PRIx64"" diff --git a/hw/virtio/virtio-iommu.c b/hw/virtio/virtio-iommu.c index 9217587..9eae050 100644 --- a/hw/virtio/virtio-iommu.c +++ b/hw/virtio/virtio-iommu.c @@ -55,11 +55,13 @@ typedef struct viommu_interval { typedef struct viommu_dev { uint32_t id; viommu_as *as; + QLIST_ENTRY(viommu_dev) next; } viommu_dev; struct viommu_as { uint32_t id; GTree *mappings; + QLIST_HEAD(, viommu_dev) device_list; }; static inline uint16_t virtio_iommu_get_sid(IOMMUDevice *dev) @@ -133,12 +135,70 @@ static gint interval_cmp(gconstpointer a, gconstpointer b, gpointer user_data) } } +static void virtio_iommu_notify_map(IOMMUMemoryRegion *mr, hwaddr iova, + hwaddr paddr, hwaddr size) +{ + IOMMUTLBEntry entry; + + entry.target_as = &address_space_memory; + entry.addr_mask = size - 1; + + entry.iova = iova; + trace_virtio_iommu_notify_map(iova, paddr, size); + entry.perm = IOMMU_RW; + entry.translated_addr = paddr; + + memory_region_notify_iommu(mr, entry); +} + +static void virtio_iommu_notify_unmap(IOMMUMemoryRegion *mr, hwaddr iova, + hwaddr paddr, hwaddr size) +{ + IOMMUTLBEntry entry; + + entry.target_as = &address_space_memory; + entry.addr_mask = size - 1; + + entry.iova = iova; + trace_virtio_iommu_notify_unmap(iova, paddr, size); + entry.perm = IOMMU_NONE; + entry.translated_addr = 0; + + memory_region_notify_iommu(mr, entry); +} + +static gboolean virtio_iommu_maping_unmap(gpointer key, gpointer value, + gpointer data) +{ + viommu_mapping *mapping = (viommu_mapping *) value; + IOMMUMemoryRegion *mr = (IOMMUMemoryRegion *) data; + + virtio_iommu_notify_unmap(mr, mapping->virt_addr, 0, mapping->size); + + return true; +} + static void virtio_iommu_detach_dev(VirtIOIOMMU *s, viommu_dev *dev) { + VirtioIOMMUNotifierNode *node; viommu_as *as = dev->as; + int devid = dev->id; trace_virtio_iommu_detach(dev->id); + /* Remove device from address-space list */ + QLIST_REMOVE(dev, next); + /* unmap all if no devices attached to address-spaceRemove */ + if (QLIST_EMPTY(&as->device_list)) { + QLIST_FOREACH(node, &s->notifiers_list, next) { + if (devid == node->iommu_dev->devfn) { + g_tree_foreach(as->mappings, virtio_iommu_maping_unmap, + &node->iommu_dev->iommu_mr); + } + } + } + + /* Remove device from global list */ g_tree_remove(s->devices, GUINT_TO_POINTER(dev->id)); g_tree_unref(as->mappings); } @@ -171,6 +231,7 @@ static int virtio_iommu_attach(VirtIOIOMMU *s, if (!as) { as = g_malloc0(sizeof(*as)); as->id = asid; + QLIST_INIT(&as->device_list); as->mappings = g_tree_new_full((GCompareDataFunc)interval_cmp, NULL, NULL, (GDestroyNotify)g_free); g_tree_insert(s->address_spaces, GUINT_TO_POINTER(asid), as); @@ -182,6 +243,7 @@ static int virtio_iommu_attach(VirtIOIOMMU *s, dev->id = devid; trace_virtio_iommu_new_devid(devid); g_tree_insert(s->devices, GUINT_TO_POINTER(devid), dev); + QLIST_INSERT_HEAD(&as->device_list, dev, next); g_tree_ref(as->mappings); return VIRTIO_IOMMU_S_OK; @@ -219,6 +281,8 @@ static int virtio_iommu_map(VirtIOIOMMU *s, viommu_as *as; viommu_interval *interval; viommu_mapping *mapping; + VirtioIOMMUNotifierNode *node; + viommu_dev *dev; interval = g_malloc0(sizeof(*interval)); @@ -230,6 +294,11 @@ static int virtio_iommu_map(VirtIOIOMMU *s, return VIRTIO_IOMMU_S_NOENT; } + dev = QLIST_FIRST(&as->device_list); + if (!dev) { + return VIRTIO_IOMMU_S_NOENT; + } + mapping = g_tree_lookup(as->mappings, (gpointer)interval); if (mapping) { g_free(interval); @@ -246,6 +315,14 @@ static int virtio_iommu_map(VirtIOIOMMU *s, g_tree_insert(as->mappings, interval, mapping); + /* All devices in an address-space share mapping */ + QLIST_FOREACH(node, &s->notifiers_list, next) { + if (dev->id == node->iommu_dev->devfn) { + virtio_iommu_notify_map(&node->iommu_dev->iommu_mr, virt_addr, + phys_addr, size); + } + } + return VIRTIO_IOMMU_S_OK; } @@ -259,6 +336,8 @@ static int virtio_iommu_unmap(VirtIOIOMMU *s, viommu_mapping *mapping; viommu_interval interval; viommu_as *as; + VirtioIOMMUNotifierNode *node; + viommu_dev *dev; trace_virtio_iommu_unmap(asid, virt_addr, size, flags); @@ -267,6 +346,12 @@ static int virtio_iommu_unmap(VirtIOIOMMU *s, error_report("%s: no as", __func__); return VIRTIO_IOMMU_S_NOENT; } + + dev = QLIST_FIRST(&as->device_list); + if (!dev) { + return VIRTIO_IOMMU_S_NOENT; + } + interval.low = virt_addr; interval.high = virt_addr + size - 1; @@ -296,7 +381,15 @@ static int virtio_iommu_unmap(VirtIOIOMMU *s, } else { break; } + if (interval.low >= interval.high) { + /* All devices in an address-space share mapping */ + QLIST_FOREACH(node, &s->notifiers_list, next) { + if (dev->id == node->iommu_dev->devfn) { + virtio_iommu_notify_unmap(&node->iommu_dev->iommu_mr, virt_addr, + 0, size); + } + } return VIRTIO_IOMMU_S_OK; } else { mapping = g_tree_lookup(as->mappings, (gpointer)&interval); @@ -439,6 +532,36 @@ static void virtio_iommu_handle_command(VirtIODevice *vdev, VirtQueue *vq) } } +static void virtio_iommu_notify_flag_changed(IOMMUMemoryRegion *iommu_mr, + IOMMUNotifierFlag old, + IOMMUNotifierFlag new) +{ + IOMMUDevice *sdev = container_of(iommu_mr, IOMMUDevice, iommu_mr); + VirtIOIOMMU *s = sdev->viommu; + VirtioIOMMUNotifierNode *node = NULL; + VirtioIOMMUNotifierNode *next_node = NULL; + + if (old == IOMMU_NOTIFIER_NONE) { + trace_virtio_iommu_notify_flag_add(iommu_mr->parent_obj.name); + node = g_malloc0(sizeof(*node)); + node->iommu_dev = sdev; + QLIST_INSERT_HEAD(&s->notifiers_list, node, next); + return; + } + + /* update notifier node with new flags */ + QLIST_FOREACH_SAFE(node, &s->notifiers_list, next, next_node) { + if (node->iommu_dev == sdev) { + if (new == IOMMU_NOTIFIER_NONE) { + trace_virtio_iommu_notify_flag_del(iommu_mr->parent_obj.name); + QLIST_REMOVE(node, next); + g_free(node); + } + return; + } + } +} + static IOMMUTLBEntry virtio_iommu_translate(IOMMUMemoryRegion *mr, hwaddr addr, IOMMUAccessFlags flag) { @@ -553,11 +676,49 @@ static gint int_cmp(gconstpointer a, gconstpointer b, gpointer user_data) return (ua > ub) - (ua < ub); } +static gboolean virtio_iommu_remap(gpointer key, gpointer value, gpointer data) +{ + viommu_mapping *mapping = (viommu_mapping *) value; + IOMMUMemoryRegion *mr = (IOMMUMemoryRegion *) data; + + trace_virtio_iommu_remap(mapping->virt_addr, mapping->phys_addr, + mapping->size); + /* unmap previous entry and map again */ + virtio_iommu_notify_unmap(mr, mapping->virt_addr, 0, mapping->size); + + virtio_iommu_notify_map(mr, mapping->virt_addr, mapping->phys_addr, + mapping->size); + return true; +} + +static void virtio_iommu_replay(IOMMUMemoryRegion *mr, IOMMUNotifier *n) +{ + IOMMUDevice *sdev = container_of(mr, IOMMUDevice, iommu_mr); + VirtIOIOMMU *s = sdev->viommu; + uint32_t sid; + viommu_dev *dev; + + sid = virtio_iommu_get_sid(sdev); + + qemu_mutex_lock(&s->mutex); + + dev = g_tree_lookup(s->devices, GUINT_TO_POINTER(sid)); + if (!dev) { + goto unlock; + } + + g_tree_foreach(dev->as->mappings, virtio_iommu_remap, mr); + +unlock: + qemu_mutex_unlock(&s->mutex); +} + static void virtio_iommu_device_realize(DeviceState *dev, Error **errp) { VirtIODevice *vdev = VIRTIO_DEVICE(dev); VirtIOIOMMU *s = VIRTIO_IOMMU(dev); + QLIST_INIT(&s->notifiers_list); virtio_init(vdev, "virtio-iommu", VIRTIO_ID_IOMMU, sizeof(struct virtio_iommu_config)); @@ -644,6 +805,8 @@ static void virtio_iommu_memory_region_class_init(ObjectClass *klass, IOMMUMemoryRegionClass *imrc = IOMMU_MEMORY_REGION_CLASS(klass); imrc->translate = virtio_iommu_translate; + imrc->notify_flag_changed = virtio_iommu_notify_flag_changed; + imrc->replay = virtio_iommu_replay; } static const TypeInfo virtio_iommu_info = { diff --git a/include/hw/virtio/virtio-iommu.h b/include/hw/virtio/virtio-iommu.h index f9c988f..7e04184 100644 --- a/include/hw/virtio/virtio-iommu.h +++ b/include/hw/virtio/virtio-iommu.h @@ -46,6 +46,11 @@ typedef struct IOMMUPciBus { IOMMUDevice *pbdev[0]; /* Parent array is sparse, so dynamically alloc */ } IOMMUPciBus; +typedef struct VirtioIOMMUNotifierNode { + IOMMUDevice *iommu_dev; + QLIST_ENTRY(VirtioIOMMUNotifierNode) next; +} VirtioIOMMUNotifierNode; + typedef struct VirtIOIOMMU { VirtIODevice parent_obj; VirtQueue *vq; @@ -56,6 +61,7 @@ typedef struct VirtIOIOMMU { GTree *address_spaces; QemuMutex mutex; GTree *devices; + QLIST_HEAD(, VirtioIOMMUNotifierNode) notifiers_list; } VirtIOIOMMU; #endif -- 1.9.3 From MAILER-DAEMON Mon Aug 21 06:57:41 2017 Received: from list by lists.gnu.org with archive (Exim 4.71) id 1djkOr-00032I-Aj for mharc-qemu-arm@gnu.org; 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MX:1; A:1; LANG:en; received-spf: None (protection.outlook.com: nxp.com does not designate permitted sender hosts) spamdiagnosticoutput: 1:99 spamdiagnosticmetadata: NSPM Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-originalarrivaltime: 21 Aug 2017 10:57:27.6731 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM5PR0401MB2610 X-detected-operating-system: by eggs.gnu.org: Windows 7 or 8 [fuzzy] X-Received-From: 104.47.0.79 Subject: Re: [Qemu-arm] [Qemu-devel] [RFC v2 PATCH 2/2] virtio-iommu: vfio integration with virtio-iommu X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 21 Aug 2017 10:57:39 -0000 Hi Eric, > -----Original Message----- > From: Auger Eric [mailto:eric.auger@redhat.com] > Sent: Thursday, August 17, 2017 9:03 PM > To: Bharat Bhushan ; > eric.auger.pro@gmail.com; peter.maydell@linaro.org; > alex.williamson@redhat.com; mst@redhat.com; qemu-arm@nongnu.org; > qemu-devel@nongnu.org > Cc: wei@redhat.com; kevin.tian@intel.com; marc.zyngier@arm.com; > tn@semihalf.com; will.deacon@arm.com; drjones@redhat.com; > robin.murphy@arm.com; christoffer.dall@linaro.org > Subject: Re: [Qemu-devel] [RFC v2 PATCH 2/2] virtio-iommu: vfio integrati= on > with virtio-iommu >=20 > Hi Bharat, >=20 > On 14/07/2017 09:25, Bharat Bhushan wrote: > > This patch allows virtio-iommu protection for PCI device-passthrough. > > > > MSI region is mapped by current version of virtio-iommu driver. > > This MSI region mapping in not getting pushed on hw iommu > > vfio_get_vaddr() allows only ram-region. > Why is it an issue. As far as I understand this is not needed actually as= the > guest MSI doorbell is not used by the host. > This RFC patch needed > > to be improved. > > > > Signed-off-by: Bharat Bhushan > > --- > > v1-v2: > > - Added trace events > > > > hw/virtio/trace-events | 5 ++ > > hw/virtio/virtio-iommu.c | 133 > +++++++++++++++++++++++++++++++++++++++ > > include/hw/virtio/virtio-iommu.h | 6 ++ > > 3 files changed, 144 insertions(+) > > > > diff --git a/hw/virtio/trace-events b/hw/virtio/trace-events index > > 9196b63..3a3968b 100644 > > --- a/hw/virtio/trace-events > > +++ b/hw/virtio/trace-events > > @@ -39,3 +39,8 @@ virtio_iommu_unmap_left_interval(uint64_t low, > > uint64_t high, uint64_t next_low, > virtio_iommu_unmap_right_interval(uint64_t low, uint64_t high, uint64_t > next_low, uint64_t next_high) "Unmap right [0x%"PRIx64",0x%"PRIx64"], > new interval=3D[0x%"PRIx64",0x%"PRIx64"]" > > virtio_iommu_unmap_inc_interval(uint64_t low, uint64_t high) "Unmap > inc [0x%"PRIx64",0x%"PRIx64"]" > > virtio_iommu_translate_result(uint64_t virt_addr, uint64_t phys_addr, > uint32_t sid) "0x%"PRIx64" -> 0x%"PRIx64 " for sid=3D%d" > > +virtio_iommu_notify_flag_add(const char *iommu) "Add virtio-iommu > notifier node for memory region %s" > > +virtio_iommu_notify_flag_del(const char *iommu) "Del virtio-iommu > notifier node for memory region %s" > > +virtio_iommu_remap(hwaddr iova, hwaddr pa, hwaddr size) > "iova=3D0x%"PRIx64" pa=3D0x%" PRIx64" size=3D0x%"PRIx64"" > > +virtio_iommu_map_region(hwaddr iova, hwaddr paddr, hwaddr > map_size) "iova=3D0x%"PRIx64" pa=3D0x%" PRIx64" size=3D0x%"PRIx64"" > > +virtio_iommu_unmap_region(hwaddr iova, hwaddr paddr, hwaddr > map_size) "iova=3D0x%"PRIx64" pa=3D0x%" PRIx64" size=3D0x%"PRIx64"" > > diff --git a/hw/virtio/virtio-iommu.c b/hw/virtio/virtio-iommu.c index > > cd188fc..61f33cb 100644 > > --- a/hw/virtio/virtio-iommu.c > > +++ b/hw/virtio/virtio-iommu.c > > @@ -129,6 +129,48 @@ static gint interval_cmp(gconstpointer a, > gconstpointer b, gpointer user_data) > > } > > } > > > > +static void virtio_iommu_map_region(VirtIOIOMMU *s, hwaddr iova, > hwaddr paddr, > > + hwaddr size, int map) > bool map? >=20 > the function name is a bit misleading to me and does not really explain w= hat > the function does. It "notifies" so why not using something like > virtio_iommu_map_notify and virtio_iommu_unmap_notify. I tend to think > having separate proto is cleaner and more standard. >=20 > Binding should happen on a specific IOMMUmemoryRegion (see next > comment). >=20 > > +{ > > + VirtioIOMMUNotifierNode *node; > > + IOMMUTLBEntry entry; > > + uint64_t map_size =3D (1 << 12); > TODO: handle something else than 4K page. > > + int npages; > > + int i; > > + > > + npages =3D size / map_size; > > + entry.target_as =3D &address_space_memory; > > + entry.addr_mask =3D map_size - 1; > > + > > + for (i =3D 0; i < npages; i++) { > Although I understand we currently fail checking the consistency between > pIOMMU and vIOMMU page sizes, this will be very slow for guest DPDK use > case where hugepages are used. >=20 > Why not directly using the full size? vfio_iommu_map_notify will report > errors if vfio_dma_map/unmap() fail. > > + entry.iova =3D iova + (i * map_size); > > + if (map) { > > + trace_virtio_iommu_map_region(iova, paddr, map_size); > > + entry.perm =3D IOMMU_RW; > > + entry.translated_addr =3D paddr + (i * map_size); > > + } else { > > + trace_virtio_iommu_unmap_region(iova, paddr, map_size)= ; > > + entry.perm =3D IOMMU_NONE; > > + entry.translated_addr =3D 0; > > + } > > + > > + QLIST_FOREACH(node, &s->notifiers_list, next) { > > + memory_region_notify_iommu(&node->iommu_dev->iommu_mr, > > + entry); > So as discussed this will notify *all* IOMMU memory regions and all their > notifiers which is not what we want. You may have a look at > vsmmuv3 v6 (or intel_iommu) where smmuv3_context_device_invalidate > retrieves the mr from the sid. I sent out next version of the patch and I took different approach, I assum= ed that device-id in virtio_iommu_attach is stream-id, and same as requested-id. This assumption= is because the "iommu-map" property maps 1:1. Looking forward your view about this. Hopefully I addressed other comments and fixed/code-rework planned. Thanks -Bharat >=20 > > + } > > + } > > +} > > + > > +static gboolean virtio_iommu_unmap_single(gpointer key, gpointer > value, > > + gpointer data) { > > + viommu_mapping *mapping =3D (viommu_mapping *) value; > > + VirtIOIOMMU *s =3D (VirtIOIOMMU *) data; > > + > > + virtio_iommu_map_region(s, mapping->virt_addr, 0, mapping->size, > > + 0); > paddr=3D0? mapping->phys_addr as the trace() will be misleading. But as > mentioned earlier better use unmap() separate function. > > + > > + return true; > > +} > > + > > static int virtio_iommu_attach(VirtIOIOMMU *s, > > struct virtio_iommu_req_attach *req) > > { @@ -170,10 +212,26 @@ static int virtio_iommu_detach(VirtIOIOMMU > *s, > > { > > uint32_t devid =3D le32_to_cpu(req->device); > > uint32_t reserved =3D le32_to_cpu(req->reserved); > > + viommu_dev *dev; > > int ret; > > > > trace_virtio_iommu_detach(devid, reserved); > > > > + dev =3D g_tree_lookup(s->devices, GUINT_TO_POINTER(devid)); > > + if (!dev || !dev->as) { > > + return -EINVAL; > > + } > > + > > + dev->as->nr_devices--; > > + > > + /* Unmap all if this is last device detached */ > > + if (dev->as->nr_devices =3D=3D 0) { > > + g_tree_foreach(dev->as->mappings, virtio_iommu_unmap_single, > > + s); > > + > > + g_tree_remove(s->address_spaces, GUINT_TO_POINTER(dev->as- > >id)); > > + g_tree_destroy(dev->as->mappings); > > + } > so this should be rebased on new ref count code. > > + > > ret =3D g_tree_remove(s->devices, GUINT_TO_POINTER(devid)); > > > > return ret ? VIRTIO_IOMMU_S_OK : VIRTIO_IOMMU_S_INVAL; @@ - > 217,6 > > +275,7 @@ static int virtio_iommu_map(VirtIOIOMMU *s, > > > > g_tree_insert(as->mappings, interval, mapping); > > > > + virtio_iommu_map_region(s, virt_addr, phys_addr, size, 1); > > return VIRTIO_IOMMU_S_OK; > > } > > > > @@ -267,7 +326,9 @@ static int virtio_iommu_unmap(VirtIOIOMMU *s, > > } else { > > break; > > } > > + > > if (interval.low >=3D interval.high) { > > + virtio_iommu_map_region(s, virt_addr, 0, size, 0); > > return VIRTIO_IOMMU_S_OK; > > } else { > > mapping =3D g_tree_lookup(as->mappings, > > (gpointer)&interval); @@ -410,6 +471,37 @@ static void > virtio_iommu_handle_command(VirtIODevice *vdev, VirtQueue *vq) > > } > > } > > > > +static void virtio_iommu_notify_flag_changed(MemoryRegion *iommu, > > + IOMMUNotifierFlag old, > > + IOMMUNotifierFlag new) { > > + IOMMUDevice *sdev =3D container_of(iommu, IOMMUDevice, > iommu_mr); > > + VirtIOIOMMU *s =3D sdev->viommu; > > + VirtioIOMMUNotifierNode *node =3D NULL; > > + VirtioIOMMUNotifierNode *next_node =3D NULL; > > + > > + if (old =3D=3D IOMMU_NOTIFIER_NONE) { > > + trace_virtio_iommu_notify_flag_add(iommu->name); > > + node =3D g_malloc0(sizeof(*node)); > > + node->iommu_dev =3D sdev; > > + QLIST_INSERT_HEAD(&s->notifiers_list, node, next); > > + return; > > + } > > + > > + /* update notifier node with new flags */ > > + QLIST_FOREACH_SAFE(node, &s->notifiers_list, next, next_node) { > > + if (node->iommu_dev =3D=3D sdev) { > > + if (new =3D=3D IOMMU_NOTIFIER_NONE) { > > + trace_virtio_iommu_notify_flag_del(iommu->name); > > + QLIST_REMOVE(node, next); > > + g_free(node); > > + } > > + return; > > + } > > + } > > +} > I think all that mechanics should be factorized somewhere else as all > vIOMMUs use that but this goes beyond the scope of this series. > > + > > + > > static IOMMUTLBEntry virtio_iommu_translate(MemoryRegion *mr, > hwaddr addr, > > IOMMUAccessFlags flag) { > > @@ -523,11 +615,50 @@ static gint int_cmp(gconstpointer a, gconstpointe= r > b, gpointer user_data) > > return (ua > ub) - (ua < ub); > > } > > > > +static gboolean virtio_iommu_remap(gpointer key, gpointer value, > > +gpointer data) { > > + viommu_mapping *mapping =3D (viommu_mapping *) value; > > + VirtIOIOMMU *s =3D (VirtIOIOMMU *) data; > > + > > + trace_virtio_iommu_remap(mapping->virt_addr, mapping->phys_addr, > > + mapping->size); > > + /* unmap previous entry and map again */ > > + virtio_iommu_map_region(s, mapping->virt_addr, 0, mapping->size, > > + 0); > > + > > + virtio_iommu_map_region(s, mapping->virt_addr, mapping- > >phys_addr, > > + mapping->size, 1); > > + return true; > > +} > > + > > +static void virtio_iommu_replay(MemoryRegion *mr, IOMMUNotifier *n) > { > > + IOMMUDevice *sdev =3D container_of(mr, IOMMUDevice, iommu_mr); > > + VirtIOIOMMU *s =3D sdev->viommu; > > + uint32_t sid; > > + viommu_dev *dev; > > + > > + sid =3D smmu_get_sid(sdev); > > + > > + qemu_mutex_lock(&s->mutex); > > + > > + dev =3D g_tree_lookup(s->devices, GUINT_TO_POINTER(sid)); > > + if (!dev) { > > + goto unlock; > > + } > > + > > + g_tree_foreach(dev->as->mappings, virtio_iommu_remap, s); > > + > > +unlock: > > + qemu_mutex_unlock(&s->mutex); > > + return; > not needed >=20 > Thanks >=20 > Eric > > +} > > + > > static void virtio_iommu_device_realize(DeviceState *dev, Error > > **errp) { > > VirtIODevice *vdev =3D VIRTIO_DEVICE(dev); > > VirtIOIOMMU *s =3D VIRTIO_IOMMU(dev); > > > > + QLIST_INIT(&s->notifiers_list); > > virtio_init(vdev, "virtio-iommu", VIRTIO_ID_IOMMU, > > sizeof(struct virtio_iommu_config)); > > > > @@ -538,6 +669,8 @@ static void > virtio_iommu_device_realize(DeviceState *dev, Error **errp) > > s->config.input_range.end =3D -1UL; > > > > s->iommu_ops.translate =3D virtio_iommu_translate; > > + s->iommu_ops.notify_flag_changed =3D > virtio_iommu_notify_flag_changed; > > + s->iommu_ops.replay =3D virtio_iommu_replay; > > memset(s->as_by_bus_num, 0, sizeof(s->as_by_bus_num)); > > s->as_by_busptr =3D g_hash_table_new_full(as_uint64_hash, > > as_uint64_equal, diff > > --git a/include/hw/virtio/virtio-iommu.h > > b/include/hw/virtio/virtio-iommu.h > > index 2259413..76c758d 100644 > > --- a/include/hw/virtio/virtio-iommu.h > > +++ b/include/hw/virtio/virtio-iommu.h > > @@ -44,6 +44,11 @@ typedef struct IOMMUPciBus { > > IOMMUDevice *pbdev[0]; /* Parent array is sparse, so dynamically > > alloc */ } IOMMUPciBus; > > > > +typedef struct VirtioIOMMUNotifierNode { > > + IOMMUDevice *iommu_dev; > > + QLIST_ENTRY(VirtioIOMMUNotifierNode) next; } > > +VirtioIOMMUNotifierNode; > > + > > typedef struct VirtIOIOMMU { > > VirtIODevice parent_obj; > > VirtQueue *vq; > > @@ -55,6 +60,7 @@ typedef struct VirtIOIOMMU { > > GTree *address_spaces; > > QemuMutex mutex; > > GTree *devices; > > + QLIST_HEAD(, VirtioIOMMUNotifierNode) notifiers_list; > > } VirtIOIOMMU; > > > > #endif > > From MAILER-DAEMON Mon Aug 21 23:46:14 2017 Received: from list by lists.gnu.org with archive (Exim 4.71) id 1dk08s-0003Nv-Cv for mharc-qemu-arm@gnu.org; Mon, 21 Aug 2017 23:46:14 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:50668) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dk08q-0003Lx-8e for qemu-arm@nongnu.org; Mon, 21 Aug 2017 23:46:13 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dk08p-0003f9-4H for qemu-arm@nongnu.org; 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Mon, 21 Aug 2017 20:46:03 -0700 (PDT) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= To: Peter Maydell , Richard Henderson Cc: qemu-arm , QEMU Developers References: <1501867249-1924-1-git-send-email-peter.maydell@linaro.org> <1501867249-1924-5-git-send-email-peter.maydell@linaro.org> <50d6ba4d-cfa3-5b5f-5da1-dca2326d4f5d@amsat.org> From: =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= Message-ID: Date: Tue, 22 Aug 2017 00:45:59 -0300 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.2.1 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=utf-8; format=flowed Content-Language: en-US Content-Transfer-Encoding: 8bit X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400d:c09::234 Subject: Re: [Qemu-arm] [PATCH 4/8] boards.h: Define new flag ignore_memory_transaction_failures X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 22 Aug 2017 03:46:13 -0000 Hi Peter, On 08/17/2017 07:25 AM, Peter Maydell wrote: > On 5 August 2017 at 11:13, Peter Maydell wrote: >> On 4 August 2017 at 20:23, Richard Henderson >> wrote: >>> On 08/04/2017 11:09 AM, Philippe Mathieu-Daudé wrote: >>>> Since create_unimplemented_device() register overlapped with low priority, why >>>> not register it as default device directly, over the whole address space? >>> >>> That's a good suggestion. It makes more sense to me than adding a flag on the >>> MachineClass. >> >> Yeah, I did think about implementing it that way, but... >> >> That wouldn't handle the case of a device model directly >> returning a MEMTX_ERROR, or a transaction dispatched to >> a memory region whose MemoryRegionOps valid settings >> prohibit it (eg byte accesses to a word-access-only device), >> or accesses to a MemoryRegion that was created by passing >> a NULL MemoryRegionOps pointer to memory_region_init_io >> (I dunno why you'd do that but some code does). >> >> In short, there are lots of ways the memory subsystem might >> end up returning a transaction error -- this mechanism >> ensures that none of them start generating exceptions >> when they previously did not, and is (I hope) easy to >> review in the sense of being sure that it does what it >> intends to do without the need to audit a lot of corner >> cases. > > So, this question (should we have a board flag to disable reporting > of tx failures to the CPU hook, or use unimplemented_device as a > sort of background region) seems to be the main unanswered question > for this series. I think (as outlined above) that the board flag > is simpler and safer; are people happy for me to put this series > in target-arm.next with that approach, or should I rethink this bit? As remarked previously in this thread, the current QEMU behavior on transaction error isn't always matching real hardware. Matching correctly throwing errors is likely to break various current users. If we are worried about being backward compatible, defaulting background region to unimp() won't throw any transaction error. Since the default is no transaction error, users who expect hardware error can implement the correct behavior, per region/bus transaction errors. I'm somehow afraid that "ignore_memory_transaction_failures" ends up like the "cannot_instantiate_with_device_add_yet" flag - a hard to remove kludge outliving his purpose. Anyway I'm not unhappy with this approach, but I'd be very happy to have unimp() covering the whole background region. Regards, Phil. From MAILER-DAEMON Tue Aug 22 02:08:41 2017 Received: from list by lists.gnu.org with archive (Exim 4.71) id 1dk2Mj-0000rr-O3 for mharc-qemu-arm@gnu.org; Tue, 22 Aug 2017 02:08:41 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:42481) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dk2Md-0000ot-W9 for qemu-arm@nongnu.org; Tue, 22 Aug 2017 02:08:38 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dk2Mb-000266-So for qemu-arm@nongnu.org; Tue, 22 Aug 2017 02:08:35 -0400 Received: from mail-ua0-x242.google.com ([2607:f8b0:400c:c08::242]:38721) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1dk2MX-00024m-LU; Tue, 22 Aug 2017 02:08:29 -0400 Received: by mail-ua0-x242.google.com with SMTP id d12so1427045uag.5; Mon, 21 Aug 2017 23:08:28 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=mime-version:in-reply-to:references:from:date:message-id:subject:to :cc; bh=QhSpCfjBqbvNhKB20XSWujLtUzSDsKV/TqNRdpBgDXo=; b=jVSyfLIFJHV3ChS7LeWeXYTmxxVPkXfMDOsPtYbcD0hMP9kKEaw1+H3hXRRk7dDuwL e4kCehlF1u4X0Fl0veKTQ9y07+hhk1OMwaSzrEIEaRFquQHJl5XhsEvzQcMBoKqwSBJU y1iOpMhXeHcZ5M8DBAmHFt6q3XsOhnbMd0BN7fIx8kYwVA2TDTyTaHMNITtEytLW/3PW isOW1JLhIUSKUfqO6Ftc9r3hU6MAHrD9ebqPA1hAEodrUTfpm1Ww43aixtnAC8xatQJz WbGJBJNcbpuDjZHODPhmTFFsirZCi20ydklxLOPm3+CdEtCTj/KdDDGrdKHGAQ2o9rFW TB5A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:in-reply-to:references:from:date :message-id:subject:to:cc; bh=QhSpCfjBqbvNhKB20XSWujLtUzSDsKV/TqNRdpBgDXo=; b=qQ/NMy6OPKYqHKXzmPzqaNMFfO8g6CI9w4O9Ify+R59EB7U+QCUb5ieWpqAp/dfv2H ce4a6jEsEAkRgZC5JcoJ5u00iXwb7piUJWfoTsR4/b3QQrwe+6myMeBRW2EBYRY1x9LZ n2LynaKalm1dSN7L/g2I1mP4EWX15GfSrvfUD0S0F6UrE+wfAZje4If+IT72WX0HrX4s TUHOauD/0n19n+eHmAMTmzXK/u9awKpTNTLaBQbI5qAFsBnTMwwY6ZszSoCgzuSntaEO pLvcsRDBYtFF11GDyNXpEAEG1IPs0Z1ephy2ZYlEj/IJqNzcy/QGA02B23zL2CgLK3G5 DV4g== X-Gm-Message-State: AHYfb5jOT1oz94if0yflDN2ufu+lQHy8MSVfAHrPyBdVD7LzGVXHSl3C NaDI9OcqDmxvOPf5Vv9QwjtySU9suQ== X-Received: by 10.159.53.36 with SMTP id o33mr13325604uao.95.1503382107664; Mon, 21 Aug 2017 23:08:27 -0700 (PDT) MIME-Version: 1.0 Received: by 10.176.75.196 with HTTP; Mon, 21 Aug 2017 23:08:27 -0700 (PDT) In-Reply-To: References: <1499057115-6773-1-git-send-email-sundeep.lkml@gmail.com> <1499057115-6773-3-git-send-email-sundeep.lkml@gmail.com> From: sundeep subbaraya Date: Tue, 22 Aug 2017 11:38:27 +0530 Message-ID: To: Alistair Francis , =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= Cc: "qemu-devel@nongnu.org Developers" , qemu-arm , Peter Maydell , Peter Crosthwaite Content-Type: multipart/alternative; boundary="94eb2c03ce807d372b0557516c88" X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400c:c08::242 Subject: Re: [Qemu-arm] [Qemu devel v6 PATCH 2/5] msf2: Microsemi Smartfusion2 System Register block. X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 22 Aug 2017 06:08:40 -0000 --94eb2c03ce807d372b0557516c88 Content-Type: text/plain; charset="UTF-8" Hi Alistair, I will remove the abort and send next iteration. Thanks, Sundeep On Tue, Aug 1, 2017 at 11:38 AM, sundeep subbaraya wrote: > Hi Philippe, > > Ping again :) > > Thanks, > Sundeep > > On Fri, Jul 21, 2017 at 2:50 PM, sundeep subbaraya > wrote: > >> Hi, >> >> Ping >> >> On Thu, Jul 13, 2017 at 7:51 AM, sundeep subbaraya < >> sundeep.lkml@gmail.com> wrote: >> >>> Hi Phiiippe, >>> >>> Gentle reminder. >>> >>> Thanks, >>> Sundeep >>> >>> >>> On Mon, Jul 10, 2017 at 1:55 PM, sundeep subbaraya < >>> sundeep.lkml@gmail.com> wrote: >>> >>>> Hi Alistair, >>>> >>>> On Fri, Jul 7, 2017 at 10:03 PM, Alistair Francis >>> > wrote: >>>> >>>>> On Fri, Jul 7, 2017 at 12:08 AM, sundeep subbaraya >>>>> wrote: >>>>> > Hi Alistair, >>>>> > >>>>> > On Wed, Jul 5, 2017 at 11:36 PM, Alistair Francis < >>>>> alistair23@gmail.com> >>>>> > wrote: >>>>> >> >>>>> >> On Sun, Jul 2, 2017 at 9:45 PM, Subbaraya Sundeep >>>>> >> wrote: >>>>> >> > Added Sytem register block of Smartfusion2. >>>>> >> > This block has PLL registers which are accessed by guest. >>>>> >> > >>>>> >> > Signed-off-by: Subbaraya Sundeep >>>>> >> > --- >>>>> >> > hw/misc/Makefile.objs | 1 + >>>>> >> > hw/misc/msf2-sysreg.c | 200 >>>>> >> > ++++++++++++++++++++++++++++++++++++++++++ >>>>> >> > include/hw/misc/msf2-sysreg.h | 82 +++++++++++++++++ >>>>> >> > 3 files changed, 283 insertions(+) >>>>> >> > create mode 100644 hw/misc/msf2-sysreg.c >>>>> >> > create mode 100644 include/hw/misc/msf2-sysreg.h >>>>> >> > >>>>> >> > diff --git a/hw/misc/Makefile.objs b/hw/misc/Makefile.objs >>>>> >> > index c8b4893..0f52354 100644 >>>>> >> > --- a/hw/misc/Makefile.objs >>>>> >> > +++ b/hw/misc/Makefile.objs >>>>> >> > @@ -56,3 +56,4 @@ obj-$(CONFIG_EDU) += edu.o >>>>> >> > obj-$(CONFIG_HYPERV_TESTDEV) += hyperv_testdev.o >>>>> >> > obj-$(CONFIG_AUX) += auxbus.o >>>>> >> > obj-$(CONFIG_ASPEED_SOC) += aspeed_scu.o aspeed_sdmc.o >>>>> >> > +obj-$(CONFIG_MSF2) += msf2-sysreg.o >>>>> >> > diff --git a/hw/misc/msf2-sysreg.c b/hw/misc/msf2-sysreg.c >>>>> >> > new file mode 100644 >>>>> >> > index 0000000..64ee141 >>>>> >> > --- /dev/null >>>>> >> > +++ b/hw/misc/msf2-sysreg.c >>>>> >> > @@ -0,0 +1,200 @@ >>>>> >> > +/* >>>>> >> > + * System Register block model of Microsemi SmartFusion2. >>>>> >> > + * >>>>> >> > + * Copyright (c) 2017 Subbaraya Sundeep >>>>> >> > + * >>>>> >> > + * This program is free software; you can redistribute it and/or >>>>> >> > + * modify it under the terms of the GNU General Public License >>>>> >> > + * as published by the Free Software Foundation; either version >>>>> >> > + * 2 of the License, or (at your option) any later version. >>>>> >> > + * >>>>> >> > + * You should have received a copy of the GNU General Public >>>>> License >>>>> >> > along >>>>> >> > + * with this program; if not, see >>>>> . >>>>> >> > + */ >>>>> >> > + >>>>> >> > +#include "hw/misc/msf2-sysreg.h" >>>>> >> >>>>> >> Same #include comment from patch 1. >>>>> > >>>>> > >>>>> > Ok will change. >>>>> >> >>>>> >> >>>>> >> > + >>>>> >> > +#ifndef MSF2_SYSREG_ERR_DEBUG >>>>> >> > +#define MSF2_SYSREG_ERR_DEBUG 0 >>>>> >> > +#endif >>>>> >> > + >>>>> >> > +#define DB_PRINT_L(lvl, fmt, args...) do { \ >>>>> >> > + if (MSF2_SYSREG_ERR_DEBUG >= lvl) { \ >>>>> >> > + qemu_log("%s: " fmt "\n", __func__, ## args); \ >>>>> >> > + } \ >>>>> >> > +} while (0); >>>>> >> > + >>>>> >> > +#define DB_PRINT(fmt, args...) DB_PRINT_L(1, fmt, ## args) >>>>> >> > + >>>>> >> > +static inline int msf2_divbits(uint32_t div) >>>>> >> > +{ >>>>> >> > + int ret = 0; >>>>> >> > + >>>>> >> > + switch (div) { >>>>> >> > + case 1: >>>>> >> > + ret = 0; >>>>> >> > + break; >>>>> >> > + case 2: >>>>> >> > + ret = 1; >>>>> >> > + break; >>>>> >> > + case 4: >>>>> >> > + ret = 2; >>>>> >> > + break; >>>>> >> > + case 8: >>>>> >> > + ret = 4; >>>>> >> > + break; >>>>> >> > + case 16: >>>>> >> > + ret = 5; >>>>> >> > + break; >>>>> >> > + case 32: >>>>> >> > + ret = 6; >>>>> >> > + break; >>>>> >> > + default: >>>>> >> > + break; >>>>> >> > + } >>>>> >> > + >>>>> >> > + return ret; >>>>> >> > +} >>>>> >> > + >>>>> >> > +static void msf2_sysreg_reset(DeviceState *d) >>>>> >> > +{ >>>>> >> > + MSF2SysregState *s = MSF2_SYSREG(d); >>>>> >> > + >>>>> >> > + DB_PRINT("RESET"); >>>>> >> > + >>>>> >> > + s->regs[MSSDDR_PLL_STATUS_LOW_CR] = 0x021A2358; >>>>> >> > + s->regs[MSSDDR_PLL_STATUS] = 0x3; >>>>> >> > + s->regs[MSSDDR_FACC1_CR] = msf2_divbits(s->apb0div) << 5 | >>>>> >> > + msf2_divbits(s->apb1div) << 2; >>>>> >> > +} >>>>> >> > + >>>>> >> > +static uint64_t msf2_sysreg_read(void *opaque, hwaddr offset, >>>>> >> > + unsigned size) >>>>> >> > +{ >>>>> >> > + MSF2SysregState *s = opaque; >>>>> >> > + offset /= 4; >>>>> >> >>>>> >> Probably best to use a bitshift. >>>>> > >>>>> > >>>>> > Ok will change. >>>>> >> >>>>> >> >>>>> >> > + uint32_t ret = 0; >>>>> >> > + >>>>> >> > + if (offset < ARRAY_SIZE(s->regs)) { >>>>> >> > + ret = s->regs[offset]; >>>>> >> > + DB_PRINT("addr: 0x%08" HWADDR_PRIx " data: 0x%08" PRIx32, >>>>> >> > + offset * 4, ret); >>>>> >> >>>>> >> Bitshift here as well. >>>>> > >>>>> > >>>>> > Ok will change. >>>>> >> >>>>> >> >>>>> >> > + } else { >>>>> >> > + qemu_log_mask(LOG_GUEST_ERROR, >>>>> >> > + "%s: Bad offset 0x%08" HWADDR_PRIx "\n", >>>>> __func__, >>>>> >> > + offset * 4); >>>>> >> > + } >>>>> >> > + >>>>> >> > + return ret; >>>>> >> > +} >>>>> >> > + >>>>> >> > +static void msf2_sysreg_write(void *opaque, hwaddr offset, >>>>> >> > + uint64_t val, unsigned size) >>>>> >> > +{ >>>>> >> > + MSF2SysregState *s = (MSF2SysregState *)opaque; >>>>> >> > + uint32_t newval = val; >>>>> >> > + uint32_t oldval; >>>>> >> > + >>>>> >> > + DB_PRINT("addr: 0x%08" HWADDR_PRIx " data: 0x%08" PRIx64, >>>>> >> > + offset, val); >>>>> >> > + >>>>> >> > + offset /= 4; >>>>> >> >>>>> >> Same here >>>>> > >>>>> > >>>>> > Ok will change >>>>> >> >>>>> >> >>>>> >> > + >>>>> >> > + switch (offset) { >>>>> >> > + case MSSDDR_PLL_STATUS: >>>>> >> > + break; >>>>> >> > + >>>>> >> > + case ESRAM_CR: >>>>> >> > + oldval = s->regs[ESRAM_CR]; >>>>> >> > + if (oldval ^ newval) { >>>>> >> > + qemu_log_mask(LOG_GUEST_ERROR, >>>>> >> > + TYPE_MSF2_SYSREG": eSRAM remapping not >>>>> >> > supported\n"); >>>>> >> > + abort(); >>>>> >> >>>>> >> The guest should not be able to kill QEMU, a guest error should >>>>> never >>>>> >> result in an abort. >>>>> > >>>>> > >>>>> > Philippe suggested to abort because: >>>>> > If guest tries to remap since firmware do a remap, the code flow >>>>> will be >>>>> > completely wrong. >>>>> > Reporting a GUEST_ERROR here is not enough since code flow >>>>> continuing would >>>>> > be >>>>> > pretty hard to understand/debug. >>>>> >>>>> I don't see how it will be that hard to debug as QEMU will tell you >>>>> that the guest is doing something wrong. >>>>> >>>>> You can't allow the guest to abort or exit QEMU. It's a security >>>>> liability issue and specifically mentioned as not allowed: >>>>> https://github.com/qemu/qemu/blob/master/HACKING#L230 >>>>> >>>>> Ok. Lets hear from Philippe. Philippe? >>>> >>>> Thanks, >>>> Sundeep >>>> >>>> >>>>> Thanks, >>>>> Alistair >>>>> >>>>> > We decided to abort for now. >>>>> >>>> >>>> >>> >> > --94eb2c03ce807d372b0557516c88 Content-Type: text/html; charset="UTF-8" Content-Transfer-Encoding: quoted-printable
Hi Alistair,

I will remove the abort an= d send next iteration.

Thanks,
Sundeep

On Tue,= Aug 1, 2017 at 11:38 AM, sundeep subbaraya <sundeep.lkml@gmail.com= > wrote:
H= i Philippe,

Ping again :)

Thank= s,
Sundeep

On Fri, Jul 21, 2017= at 2:50 PM, sundeep subbaraya <sundeep.lkml@gmail.com>= wrote:
Hi,

Ping

On Thu, Jul 13, 2017 at 7:51 AM, sundeep subbaraya <= sundeep.lkml@gmail.com> wrote:
Hi Phiiippe,

Gentle remind= er.

Thanks,
Sundeep


On Mon, Jul 10, 2017 at 1:55 PM, sundeep= subbaraya <sundeep.lkml@gmail.com> wrote:
Hi Alistair,

On Fri, Jul 7, 2017 at 1= 0:03 PM, Alistair Francis <alistair23@gmail.com> wrote:
On Fri, Jul 7, 2017 at 12:08 AM, sundeep subbaraya
<sundeep.lkm= l@gmail.com> wrote:
> Hi Alistair,
>
> On Wed, Jul 5, 2017 at 11:36 PM, Alistair Francis <alistair23@gmail.com>
> wrote:
>>
>> On Sun, Jul 2, 2017 at 9:45 PM, Subbaraya Sundeep
>> <su= ndeep.lkml@gmail.com> wrote:
>> > Added Sytem register block of Smartfusion2.
>> > This block has PLL registers which are accessed by guest.
>> >
>> > Signed-off-by: Subbaraya Sundeep <sundeep.lkml@gmail.com>
>> > ---
>> >=C2=A0 hw/misc/Makefile.objs=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= |=C2=A0 =C2=A01 +
>> >=C2=A0 hw/misc/msf2-sysreg.c=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= | 200
>> > ++++++++++++++++++++++++++++++++++++++++++
>> >=C2=A0 include/hw/misc/msf2-sysreg.h |=C2=A0 82 ++++++++++++++= +++
>> >=C2=A0 3 files changed, 283 insertions(+)
>> >=C2=A0 create mode 100644 hw/misc/msf2-sysreg.c
>> >=C2=A0 create mode 100644 include/hw/misc/msf2-sysreg.h
>> >
>> > diff --git a/hw/misc/Makefile.objs b/hw/misc/Makefile.objs >> > index c8b4893..0f52354 100644
>> > --- a/hw/misc/Makefile.objs
>> > +++ b/hw/misc/Makefile.objs
>> > @@ -56,3 +56,4 @@ obj-$(CONFIG_EDU) +=3D edu.o
>> >=C2=A0 obj-$(CONFIG_HYPERV_TESTDEV) +=3D hyperv_testdev.o
>> >=C2=A0 obj-$(CONFIG_AUX) +=3D auxbus.o
>> >=C2=A0 obj-$(CONFIG_ASPEED_SOC) +=3D aspeed_scu.o aspeed_sdmc.= o
>> > +obj-$(CONFIG_MSF2) +=3D msf2-sysreg.o
>> > diff --git a/hw/misc/msf2-sysreg.c b/hw/misc/msf2-sysreg.c >> > new file mode 100644
>> > index 0000000..64ee141
>> > --- /dev/null
>> > +++ b/hw/misc/msf2-sysreg.c
>> > @@ -0,0 +1,200 @@
>> > +/*
>> > + * System Register block model of Microsemi SmartFusion2. >> > + *
>> > + * Copyright (c) 2017 Subbaraya Sundeep <sundeep.lkml@gmail.com><= br> >> > + *
>> > + * This program is free software; you can redistribute it an= d/or
>> > + * modify it under the terms of the GNU General Public Licen= se
>> > + * as published by the Free Software Foundation; either vers= ion
>> > + * 2 of the License, or (at your option) any later version.<= br> >> > + *
>> > + * You should have received a copy of the GNU General Public= License
>> > along
>> > + * with this program; if not, see <http://www.gnu.org/= licenses/>.
>> > + */
>> > +
>> > +#include "hw/misc/msf2-sysreg.h"
>>
>> Same #include comment from patch 1.
>
>
> Ok will change.
>>
>>
>> > +
>> > +#ifndef MSF2_SYSREG_ERR_DEBUG
>> > +#define MSF2_SYSREG_ERR_DEBUG=C2=A0 0
>> > +#endif
>> > +
>> > +#define DB_PRINT_L(lvl, fmt, args...) do { \
>> > +=C2=A0 =C2=A0 if (MSF2_SYSREG_ERR_DEBUG >=3D lvl) { \
>> > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 qemu_log("%s: " fmt &q= uot;\n", __func__, ## args); \
>> > +=C2=A0 =C2=A0 } \
>> > +} while (0);
>> > +
>> > +#define DB_PRINT(fmt, args...) DB_PRINT_L(1, fmt, ## args) >> > +
>> > +static inline int msf2_divbits(uint32_t div)
>> > +{
>> > +=C2=A0 =C2=A0 int ret =3D 0;
>> > +
>> > +=C2=A0 =C2=A0 switch (div) {
>> > +=C2=A0 =C2=A0 case 1:
>> > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 ret =3D 0;
>> > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 break;
>> > +=C2=A0 =C2=A0 case 2:
>> > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 ret =3D 1;
>> > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 break;
>> > +=C2=A0 =C2=A0 case 4:
>> > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 ret =3D 2;
>> > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 break;
>> > +=C2=A0 =C2=A0 case 8:
>> > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 ret =3D 4;
>> > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 break;
>> > +=C2=A0 =C2=A0 case 16:
>> > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 ret =3D 5;
>> > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 break;
>> > +=C2=A0 =C2=A0 case 32:
>> > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 ret =3D 6;
>> > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 break;
>> > +=C2=A0 =C2=A0 default:
>> > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 break;
>> > +=C2=A0 =C2=A0 }
>> > +
>> > +=C2=A0 =C2=A0 return ret;
>> > +}
>> > +
>> > +static void msf2_sysreg_reset(DeviceState *d)
>> > +{
>> > +=C2=A0 =C2=A0 MSF2SysregState *s =3D MSF2_SYSREG(d);
>> > +
>> > +=C2=A0 =C2=A0 DB_PRINT("RESET");
>> > +
>> > +=C2=A0 =C2=A0 s->regs[MSSDDR_PLL_STATUS_LOW_CR] =3D = 0x021A2358;
>> > +=C2=A0 =C2=A0 s->regs[MSSDDR_PLL_STATUS] =3D 0x3;
>> > +=C2=A0 =C2=A0 s->regs[MSSDDR_FACC1_CR] =3D msf2_divbits(s= ->apb0div) << 5 |
>> > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0msf2_divbits(s->apb1= div) << 2;
>> > +}
>> > +
>> > +static uint64_t msf2_sysreg_read(void *opaque, hwaddr offset= ,
>> > +=C2=A0 =C2=A0 unsigned size)
>> > +{
>> > +=C2=A0 =C2=A0 MSF2SysregState *s =3D opaque;
>> > +=C2=A0 =C2=A0 offset /=3D 4;
>>
>> Probably best to use a bitshift.
>
>
> Ok will change.
>>
>>
>> > +=C2=A0 =C2=A0 uint32_t ret =3D 0;
>> > +
>> > +=C2=A0 =C2=A0 if (offset < ARRAY_SIZE(s->regs)) {
>> > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 ret =3D s->regs[offset];
>> > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 DB_PRINT("addr: 0x%08"= HWADDR_PRIx " data: 0x%08" PRIx32,
>> > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 offset * 4, ret);
>>
>> Bitshift here as well.
>
>
> Ok will change.
>>
>>
>> > +=C2=A0 =C2=A0 } else {
>> > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 qemu_log_mask(LOG_GUEST_ERROR, >> > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 "%s: Bad offset 0x%08" HWADDR_PRIx "\n", __f= unc__,
>> > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 offset * 4);
>> > +=C2=A0 =C2=A0 }
>> > +
>> > +=C2=A0 =C2=A0 return ret;
>> > +}
>> > +
>> > +static void msf2_sysreg_write(void *opaque, hwaddr offset, >> > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 uint64_t val, unsigned size)
>> > +{
>> > +=C2=A0 =C2=A0 MSF2SysregState *s =3D (MSF2SysregState *)opaq= ue;
>> > +=C2=A0 =C2=A0 uint32_t newval =3D val;
>> > +=C2=A0 =C2=A0 uint32_t oldval;
>> > +
>> > +=C2=A0 =C2=A0 DB_PRINT("addr: 0x%08" HWADDR_PRIx &= quot; data: 0x%08" PRIx64,
>> > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 offset, val);
>> > +
>> > +=C2=A0 =C2=A0 offset /=3D 4;
>>
>> Same here
>
>
> Ok will change
>>
>>
>> > +
>> > +=C2=A0 =C2=A0 switch (offset) {
>> > +=C2=A0 =C2=A0 case MSSDDR_PLL_STATUS:
>> > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 break;
>> > +
>> > +=C2=A0 =C2=A0 case ESRAM_CR:
>> > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 oldval =3D s->regs[ESRAM_CR];=
>> > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 if (oldval ^ newval) {
>> > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 qemu_log_mask(LOG_= GUEST_ERROR,
>> > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0TYPE_MSF2_SYSREG": eSRAM remapping not
>> > supported\n");
>> > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 abort();
>>
>> The guest should not be able to kill QEMU, a guest error should ne= ver
>> result in an abort.
>
>
> Philippe suggested to abort because:
> If guest tries to remap since firmware do a remap, the code flow will = be
> completely wrong.
> Reporting a GUEST_ERROR here is not enough since code flow continuing = would
> be
> pretty hard to understand/debug.

I don't see how it will be that hard to debug as QEMU will = tell you
that the guest is doing something wrong.

You can't allow the guest to abort or exit QEMU. It's a security liability issue and specifically mentioned as not allowed:
https://github.com/qemu/qemu/blob/master/H= ACKING#L230

Ok. Lets hear from Philippe. Philippe?
Thanks,
Sundeep
=C2=A0
Thanks,
Alistair

> We decided to abort for now.





--94eb2c03ce807d372b0557516c88-- From MAILER-DAEMON Tue Aug 22 04:37:24 2017 Received: from list by lists.gnu.org with archive (Exim 4.71) id 1dk4ge-0003nT-9w for mharc-qemu-arm@gnu.org; Tue, 22 Aug 2017 04:37:24 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:41500) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dk4gb-0003mG-Pi for qemu-arm@nongnu.org; Tue, 22 Aug 2017 04:37:22 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dk4ga-0006dg-UF for qemu-arm@nongnu.org; Tue, 22 Aug 2017 04:37:21 -0400 Received: from mail-wr0-x232.google.com ([2a00:1450:400c:c0c::232]:33806) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1dk4ga-0006d0-Mb for qemu-arm@nongnu.org; Tue, 22 Aug 2017 04:37:20 -0400 Received: by mail-wr0-x232.google.com with SMTP id p14so50151932wrg.1 for ; Tue, 22 Aug 2017 01:37:20 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:in-reply-to:references:from:date:message-id:subject:to :cc:content-transfer-encoding; bh=CCc/iWJ2QXg6j/xykQjePhd6JVQ35U4HJYFOp0ZfzN0=; b=JQ1HtqVJUvZelvXcuk2v9fENhbwcFrogn+l8BIeZXomiUjVvgB8jFEuCb67CWCqJBz 8mIx6aH0oKJUsP04ksUu5yAtswsOMRMfYEkZIQupguJL0JXK5nipVBka2EnaGZXZl9oz Xy4Y3xHYPnF2gz8V4WuqHRzELhnxsg9LkE5/k= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:in-reply-to:references:from:date :message-id:subject:to:cc:content-transfer-encoding; bh=CCc/iWJ2QXg6j/xykQjePhd6JVQ35U4HJYFOp0ZfzN0=; b=N2S7vm/fGcqGVbHywiB4yMC8bk2A0IdthcQK3fTBdF2Sl6daNRCPGFrtbJeAoCfLT6 wj0dv/SBoeEN58sR5uXxR/N2557JVaLqu/rzytC/mDe5/DdDByTv44qQzuGsj3FkpS7t 19U0P74cfMgkGGbVo//Apicoer3kPC/mNj3os4gD8EtWgRRxkBUhuTYLaUCfbGGSjcyN jEadbOj1DcvMrpmiYJpe6E26RFMuiqAeoFlp291dWvMIwkSW82NAqJpc9USYToQd6zKh cXX2FdHfoimbyUqIL17cbV+3NRuH0q3yzZO8qBKL6HxaZ4mOIfAmdIEZTTjl0RRkJyAG 6krw== X-Gm-Message-State: AHYfb5hR5vgIqSqKCKRTT4NC0TIgfPvuy2jgDexZSNqUNUdZezvv+dH9 an2KVVC0l7RMf+AcOJrrYDcTvqrOrxtg X-Received: by 10.28.193.10 with SMTP id r10mr8834540wmf.157.1503391039586; Tue, 22 Aug 2017 01:37:19 -0700 (PDT) MIME-Version: 1.0 Received: by 10.223.134.54 with HTTP; Tue, 22 Aug 2017 01:36:59 -0700 (PDT) In-Reply-To: References: <1501867249-1924-1-git-send-email-peter.maydell@linaro.org> <1501867249-1924-5-git-send-email-peter.maydell@linaro.org> <50d6ba4d-cfa3-5b5f-5da1-dca2326d4f5d@amsat.org> From: Peter Maydell Date: Tue, 22 Aug 2017 09:36:59 +0100 Message-ID: To: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= Cc: Richard Henderson , qemu-arm , QEMU Developers Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:400c:c0c::232 Subject: Re: [Qemu-arm] [PATCH 4/8] boards.h: Define new flag ignore_memory_transaction_failures X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 22 Aug 2017 08:37:22 -0000 On 22 August 2017 at 04:45, Philippe Mathieu-Daud=C3=A9 w= rote: > On 08/17/2017 07:25 AM, Peter Maydell wrote: >> >> On 5 August 2017 at 11:13, Peter Maydell wrot= e: >> So, this question (should we have a board flag to disable reporting >> of tx failures to the CPU hook, or use unimplemented_device as a >> sort of background region) seems to be the main unanswered question >> for this series. I think (as outlined above) that the board flag >> is simpler and safer; are people happy for me to put this series >> in target-arm.next with that approach, or should I rethink this bit? > > As remarked previously in this thread, the current QEMU behavior on > transaction error isn't always matching real hardware. > Matching correctly throwing errors is likely to break various > current users. Yes, hence this patchseries keeping the wrong but back compatible behaviour... > If we are worried about being backward compatible, defaulting background > region to unimp() won't throw any transaction error. As I said, it will, for the cases of device model directly returning a MEMTX_ERROR, or a transaction dispatched to a memory region whose MemoryRegionOps valid settings prohibit it (eg byte accesses to a word-access-only device), etc. The only simple way to guarantee that we don't generate exceptions on transaction errors is to cause the hook not to be called (or to have the hook decide to do nothing, I suppose). > I'm somehow afraid that "ignore_memory_transaction_failures" ends up like > the "cannot_instantiate_with_device_add_yet" flag - a hard to remove klud= ge > outliving his purpose. I agree that it's going to be around for a long time, possibly forever, but that's life when we have so many old boards. Any approach we take is almost certainly going to be hanging around forever. > Anyway I'm not unhappy with this approach, but I'd be very happy to have > unimp() covering the whole background region. I think this would be a reasonable approach for converting boards away from this ignore_memory_transaction_failures hook on a board-by-board basis but you'd still want to test some common guest software for each conversion. thanks -- PMM From MAILER-DAEMON Tue Aug 22 05:04:34 2017 Received: from list by lists.gnu.org with archive (Exim 4.71) id 1dk56v-0002x0-Sl for mharc-qemu-arm@gnu.org; Tue, 22 Aug 2017 05:04:33 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:51506) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dk56t-0002vx-7F for qemu-arm@nongnu.org; Tue, 22 Aug 2017 05:04:32 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dk56o-0006PE-7h for qemu-arm@nongnu.org; Tue, 22 Aug 2017 05:04:31 -0400 Received: from bran.ispras.ru ([83.149.199.196]:46270 helo=smtp.ispras.ru) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dk56n-0006Nh-T4; Tue, 22 Aug 2017 05:04:26 -0400 Received: from bulbul.intra.ispras.ru (bulbul.intra.ispras.ru [10.10.3.51]) by smtp.ispras.ru (Postfix) with ESMTP id 9F6E15FB48; Tue, 22 Aug 2017 12:04:23 +0300 (MSK) Date: Tue, 22 Aug 2017 12:04:23 +0300 (MSK) From: Kirill Batuzov To: Richard Henderson cc: =?ISO-8859-15?Q?Alex_Benn=E9e?= , cota@braap.org, qemu-devel@nongnu.org, qemu-arm@nongnu.org, rth@twiddle.net In-Reply-To: <64af762a-5d2b-5e33-fc8e-18244b0c6586@linaro.org> Message-ID: References: <20170817180404.29334-1-alex.bennee@linaro.org> <64af762a-5d2b-5e33-fc8e-18244b0c6586@linaro.org> User-Agent: Alpine 2.20 (DEB 67 2015-01-07) MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [fuzzy] X-Received-From: 83.149.199.196 Subject: Re: [Qemu-arm] [Qemu-devel] [RFC PATCH 0/9] TCG Vector types and example conversion X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 22 Aug 2017 09:04:32 -0000 On Fri, 18 Aug 2017, Richard Henderson wrote: > On 08/18/2017 04:33 AM, Kirill Batuzov wrote: > > From my own experimentations some times ago, > > > > (1) translating vector instructions to vector instructions in TCG is faster than > > > > (2) translating vector instructions to series of scalar instructions in TCG, > > which is faster than* > > > > (3) translating vector instructions to single helper calls, which is faster > > than* > > > > (4) translating vector instructions to helper calls for each vector element. > > > > (*) (2) and (3) may change their respective places in case of some > > complicated instructions. > > This was my gut feeling as well. With the caveat that for the ARM SVE case of > 2048-bit registers we cannot afford to expand inline due to generated code size. > > > ARM (at least ARM32, I have not checked aarch64 in this regard) uses the > > last, the slowest scheme. As far as I understand, you are want to change > > it to the third approach. This approach is used in SSE emulation, may be > > you can use similar structure of helpers? > > > > I still hope to finish my own series about implementation of the first > > approach. I apologize for the long delay since last update and hope to > > send next version somewhere next week. I do not think our series > > contradict each other: you are trying to optimize existing general > > purpose case while I'm trying to optimize case where both host and guest > > support vector instructions. Since I'm experimenting on ARM32, we'll not > > have much merge conflicts either. > > I posted my own, different, take on vectorization yesterday as well. > > http://lists.nongnu.org/archive/html/qemu-devel/2017-08/msg03272.html > > The primary difference between my version and your version is that I do not > allow target/cpu/translate*.c to create vector types. All of the host vector > expansion is done within tcg/*.c. I took a look at your approach. The only problem with it is that in current implementation it does not allow to keep vector variables on register between consecutive guest instructions. But this can be changed. To do it we need to make copy propagation work with memory locations as well, and dead code elimination to be able to remove excess stores to memory. While in general case these can be troublesome if we limit analysis to addresses that are [env + Const] it becomes relatively easy. I've done similar thing in my series to track interference between memory operations and vector global variables. In case of your series this affects only performance so it does not need to be added in the initial series and can be added later as a separate patch. I can care of this once initial series are pulled to master. Overall I like your approach the most out of three: - it handles different representations of guest vectors with host vectors seamlessly (unlike my approach where I still do not know how to make it right), - it provides better performance than Alex's (and the same as mine once we add a bit of alias analysis), - it moves in the direction of representing guest vectors not as globals, but as a pair (offset, size) in a special address space (this approach was successfully used in Valgrind and it handles intersecting registers much better than what we have now; we are moving in this direction anyway). -- Kirill From MAILER-DAEMON Tue Aug 22 06:07:43 2017 Received: from list by lists.gnu.org with archive (Exim 4.71) id 1dk663-00046r-3E for mharc-qemu-arm@gnu.org; Tue, 22 Aug 2017 06:07:43 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:39353) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dk65y-00045R-9m for qemu-arm@nongnu.org; Tue, 22 Aug 2017 06:07:41 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dk65v-0001KM-2Q for qemu-arm@nongnu.org; Tue, 22 Aug 2017 06:07:38 -0400 Received: from mx1.redhat.com ([209.132.183.28]:39588) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1dk65u-0001Hm-Sd; Tue, 22 Aug 2017 06:07:35 -0400 Received: from smtp.corp.redhat.com (int-mx03.intmail.prod.int.phx2.redhat.com [10.5.11.13]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id 0358BC058EC1; Tue, 22 Aug 2017 10:07:32 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mx1.redhat.com 0358BC058EC1 Authentication-Results: ext-mx08.extmail.prod.ext.phx2.redhat.com; dmarc=none (p=none dis=none) header.from=redhat.com Authentication-Results: ext-mx08.extmail.prod.ext.phx2.redhat.com; spf=fail smtp.mailfrom=thuth@redhat.com Received: from [10.36.116.21] (ovpn-116-21.ams2.redhat.com [10.36.116.21]) by smtp.corp.redhat.com (Postfix) with ESMTPS id 9E37F614CF; Tue, 22 Aug 2017 10:07:30 +0000 (UTC) To: Peter Maydell Cc: Beniamino Galvani , qemu-arm , QEMU Developers , Li Guang References: <1503076096-14220-1-git-send-email-thuth@redhat.com> From: Thomas Huth Message-ID: Date: Tue, 22 Aug 2017 12:07:29 +0200 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.2.0 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 7bit X-Scanned-By: MIMEDefang 2.79 on 10.5.11.13 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.32]); Tue, 22 Aug 2017 10:07:32 +0000 (UTC) X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.132.183.28 Subject: Re: [Qemu-arm] [PATCH] hw/arm/allwinner: Fix crash with -nodefaults -M cubieboard X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 22 Aug 2017 10:07:41 -0000 On 18.08.2017 19:14, Peter Maydell wrote: > On 18 August 2017 at 18:08, Thomas Huth wrote: >> The allwinner-a10 device uses serial_hds[0] without checking whether >> it is available or not. So using the cubieboard with -nodefaults >> currently results in a segmentation fault. Fix it by adding a >> proper check here. >> And while we're at it, mark the device as "user_creatable = false" >> since this apparently can not directly be used by the users but has >> to be wired up in code instead. >> >> Signed-off-by: Thomas Huth >> --- >> hw/arm/allwinner-a10.c | 8 ++++++-- >> 1 file changed, 6 insertions(+), 2 deletions(-) >> >> diff --git a/hw/arm/allwinner-a10.c b/hw/arm/allwinner-a10.c >> index f62a9a3..e152566 100644 >> --- a/hw/arm/allwinner-a10.c >> +++ b/hw/arm/allwinner-a10.c >> @@ -109,8 +109,10 @@ static void aw_a10_realize(DeviceState *dev, Error **errp) >> sysbus_connect_irq(SYS_BUS_DEVICE(&s->sata), 0, s->irq[56]); >> >> /* FIXME use a qdev chardev prop instead of serial_hds[] */ >> - serial_mm_init(get_system_memory(), AW_A10_UART0_REG_BASE, 2, s->irq[1], >> - 115200, serial_hds[0], DEVICE_NATIVE_ENDIAN); >> + if (serial_hds[0]) { >> + serial_mm_init(get_system_memory(), AW_A10_UART0_REG_BASE, 2, s->irq[1], >> + 115200, serial_hds[0], DEVICE_NATIVE_ENDIAN); >> + } > > This doesn't look like the right fix, because it means that > there won't be a UART device at that point in system memory > at all. What you want is for there to be a UART device there > but not connected to anything, ie serial_mm_init() should cope > with being passed a NULL Chardev*. OK, makes sense. ... but I guess the patch to fix serial_mm_init() is going to be a bigger patch, since serial_realize_core() currently expects a char device, too, and thus needs to be reworked, too ... I'll try to come up with something when I've got some more spare time... Thomas From MAILER-DAEMON Tue Aug 22 08:47:49 2017 Received: from list by lists.gnu.org with archive (Exim 4.71) id 1dk8az-0001Ux-CT for mharc-qemu-arm@gnu.org; Tue, 22 Aug 2017 08:47:49 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:42112) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dk8ax-0001Ub-80 for qemu-arm@nongnu.org; Tue, 22 Aug 2017 08:47:48 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dk8au-0002fE-2l for qemu-arm@nongnu.org; Tue, 22 Aug 2017 08:47:47 -0400 Received: from mx1.redhat.com ([209.132.183.28]:50016) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1dk8at-0002ei-St; Tue, 22 Aug 2017 08:47:44 -0400 Received: from smtp.corp.redhat.com (int-mx06.intmail.prod.int.phx2.redhat.com [10.5.11.16]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id B32F161476; Tue, 22 Aug 2017 12:47:42 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mx1.redhat.com B32F161476 Authentication-Results: ext-mx10.extmail.prod.ext.phx2.redhat.com; dmarc=none (p=none dis=none) header.from=redhat.com Authentication-Results: ext-mx10.extmail.prod.ext.phx2.redhat.com; spf=fail smtp.mailfrom=thuth@redhat.com Received: from thh440s.redhat.com (ovpn-116-21.ams2.redhat.com [10.36.116.21]) by smtp.corp.redhat.com (Postfix) with ESMTP id EA3F4617A0; Tue, 22 Aug 2017 12:47:40 +0000 (UTC) From: Thomas Huth To: Peter Maydell , qemu-arm@nongnu.org Cc: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Andrew Jeffery , Jeremy Kerr , qemu-devel@nongnu.org Date: Tue, 22 Aug 2017 14:47:39 +0200 Message-Id: <1503406059-7280-1-git-send-email-thuth@redhat.com> X-Scanned-By: MIMEDefang 2.79 on 10.5.11.16 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.39]); Tue, 22 Aug 2017 12:47:42 +0000 (UTC) X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.132.183.28 Subject: [Qemu-arm] [PATCH] hw/arm/aspeed_soc: Mark devices as user_creatable = false X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 22 Aug 2017 12:47:48 -0000 QEMU currently aborts if the user is accidentially trying to do something like this: $ aarch64-softmmu/qemu-system-aarch64 -S -M integratorcp -nographic QEMU 2.9.93 monitor - type 'help' for more information (qemu) device_add ast2400 Unexpected error in error_set_from_qdev_prop_error() at hw/core/qdev-properties.c:1032: Aborted (core dumped) The ast2400 SoC devices are clearly not creatable by the user since they are using the serial_hds and nd_table arrays directly in their realize function, so mark them with user_creatable = false. Signed-off-by: Thomas Huth --- hw/arm/aspeed_soc.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/hw/arm/aspeed_soc.c b/hw/arm/aspeed_soc.c index 5529024..7f1be04 100644 --- a/hw/arm/aspeed_soc.c +++ b/hw/arm/aspeed_soc.c @@ -338,6 +338,8 @@ static void aspeed_soc_class_init(ObjectClass *oc, void *data) sc->info = (AspeedSoCInfo *) data; dc->realize = aspeed_soc_realize; + /* Reason: Uses serial_hds and nd_table in realize() directly */ + dc->user_creatable = false; } static const TypeInfo aspeed_soc_type_info = { -- 1.8.3.1 From MAILER-DAEMON Tue Aug 22 09:15:28 2017 Received: from list by lists.gnu.org with archive (Exim 4.71) id 1dk91k-0008Qg-Hv for mharc-qemu-arm@gnu.org; Tue, 22 Aug 2017 09:15:28 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:48919) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dk91d-0008Lo-7x for qemu-arm@nongnu.org; Tue, 22 Aug 2017 09:15:26 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dk91Y-0002sC-Sk for qemu-arm@nongnu.org; Tue, 22 Aug 2017 09:15:20 -0400 Received: from mx1.redhat.com ([209.132.183.28]:39144) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1dk91Y-0002rq-MQ; Tue, 22 Aug 2017 09:15:16 -0400 Received: from smtp.corp.redhat.com (int-mx03.intmail.prod.int.phx2.redhat.com [10.5.11.13]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id 5A9F161479; Tue, 22 Aug 2017 13:15:15 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mx1.redhat.com 5A9F161479 Authentication-Results: ext-mx10.extmail.prod.ext.phx2.redhat.com; dmarc=none (p=none dis=none) header.from=redhat.com Authentication-Results: ext-mx10.extmail.prod.ext.phx2.redhat.com; spf=fail smtp.mailfrom=thuth@redhat.com Received: from thh440s.redhat.com (ovpn-116-21.ams2.redhat.com [10.36.116.21]) by smtp.corp.redhat.com (Postfix) with ESMTP id 0778C17F55; Tue, 22 Aug 2017 13:15:13 +0000 (UTC) From: Thomas Huth To: Peter Maydell , qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Antony Pavlov Date: Tue, 22 Aug 2017 15:15:12 +0200 Message-Id: <1503407712-9894-1-git-send-email-thuth@redhat.com> X-Scanned-By: MIMEDefang 2.79 on 10.5.11.13 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.39]); Tue, 22 Aug 2017 13:15:15 +0000 (UTC) X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.132.183.28 Subject: [Qemu-arm] [PATCH] hw/arm/digic: Mark device with user_creatable = false X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 22 Aug 2017 13:15:27 -0000 QEMU currently hangs completely when the user is trying to do a "device_add digic" on an unrelated ARM machine like integratorcp. Looks like this device is not meant to be hot-pluggable at all, so let's simply mark it with "user_creatable = false" to avoid the hang. Signed-off-by: Thomas Huth --- hw/arm/digic.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/hw/arm/digic.c b/hw/arm/digic.c index 94f3263..208dfb3 100644 --- a/hw/arm/digic.c +++ b/hw/arm/digic.c @@ -101,6 +101,8 @@ static void digic_class_init(ObjectClass *oc, void *data) DeviceClass *dc = DEVICE_CLASS(oc); dc->realize = digic_realize; + /* Reason: Hangs QEMU when trying to device_add this directly */ + dc->user_creatable = false; } static const TypeInfo digic_type_info = { -- 1.8.3.1 From MAILER-DAEMON Tue Aug 22 09:16:09 2017 Received: from list by lists.gnu.org with archive (Exim 4.71) id 1dk92O-0000Ua-U0 for mharc-qemu-arm@gnu.org; Tue, 22 Aug 2017 09:16:08 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:49105) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dk92K-0000QM-5G for qemu-arm@nongnu.org; Tue, 22 Aug 2017 09:16:07 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dk92F-0003bu-Ux for qemu-arm@nongnu.org; Tue, 22 Aug 2017 09:16:04 -0400 Received: from mail-wr0-x236.google.com ([2a00:1450:400c:c0c::236]:37580) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1dk92F-0003Yv-Ha for qemu-arm@nongnu.org; Tue, 22 Aug 2017 09:15:59 -0400 Received: by mail-wr0-x236.google.com with SMTP id z91so123318847wrc.4 for ; Tue, 22 Aug 2017 06:15:59 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=references:user-agent:from:to:cc:subject:in-reply-to:date :message-id:mime-version:content-transfer-encoding; bh=g9Q7gjLORqVgt8Cxa1Q0fZMgE5CDRdLmiMd+bBTksZY=; b=EjYOXyxmB1cm8Tf3JKBlNJo6Bidkak/m8G6XgOmImVOmEkiDn5/VxxDLjgI8qLQZzE 6Odj+46sToE21Cvh7KuKJdfdNi9OsYrdWfuZRK7KSgYBuJ/81LOih7o1CHe1N0DiJBzQ /UqFD0uXO/sp+txJ6zwADCwL/pWaL3Ghz63v0= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:references:user-agent:from:to:cc:subject :in-reply-to:date:message-id:mime-version:content-transfer-encoding; bh=g9Q7gjLORqVgt8Cxa1Q0fZMgE5CDRdLmiMd+bBTksZY=; b=FuHRE/Kq+DVwQt1dMDPvk3TPcP4CkSpnPNZQuNWjTt1hEdEWv4DtDBYYItmjCOuo/E 5U2ZMzOmLCOnYHp+3HDGMaJF1atW2mRns6dX965CsENx2UvVqhH29kQMoSI7H0gTv5NX 8D2t0Gf4S+3Qld7rgsY07z9cNCuczLDToDDfEZW9PCIGGYP448c1MsB58wqWucDUctMQ USbklrAVV3C5o0/DrZYdsdYeD/aXzSn07JhgU9hgO5v+mBlxFWuzoT/XkupBTY5TYhCA L8oMvwGUD2v6TddYcJaHkyRIMPgW/noH1EJ7uMcvlJpiomnYyMmWfd5K36wHMeeF0fKt 4o3g== X-Gm-Message-State: AHYfb5hQmu9HCrdWDWvfcK614/Cm10arej4M/kA93e6OZ3VQIQ7bMQ4h MgUnpXhqvngKAhle X-Received: by 10.223.133.140 with SMTP id 12mr481955wrt.102.1503407757643; Tue, 22 Aug 2017 06:15:57 -0700 (PDT) Received: from zen.linaro.local ([81.128.185.34]) by smtp.gmail.com with ESMTPSA id 93sm13402787wro.47.2017.08.22.06.15.56 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 22 Aug 2017 06:15:56 -0700 (PDT) Received: from zen (localhost [127.0.0.1]) by zen.linaro.local (Postfix) with ESMTPS id 2D9713E00E2; Tue, 22 Aug 2017 14:15:56 +0100 (BST) References: <20170817230114.3655-1-richard.henderson@linaro.org> <20170817230114.3655-9-richard.henderson@linaro.org> User-agent: mu4e 0.9.19; emacs 25.2.50.3 From: Alex =?utf-8?Q?Benn=C3=A9e?= To: Richard Henderson Cc: qemu-devel@nongnu.org, qemu-arm@nongnu.org In-reply-to: <20170817230114.3655-9-richard.henderson@linaro.org> Date: Tue, 22 Aug 2017 14:15:56 +0100 Message-ID: <87valf4ub7.fsf@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: 8bit X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:400c:c0c::236 Subject: Re: [Qemu-arm] [PATCH 8/8] tcg/i386: Add vector operations X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 22 Aug 2017 13:16:07 -0000 Richard Henderson writes: > Signed-off-by: Richard Henderson > --- > tcg/i386/tcg-target.h | 46 +++++- > tcg/tcg-opc.h | 12 +- > tcg/i386/tcg-target.inc.c | 382 ++++++++++++++++++++++++++++++++++++++++++---- > 3 files changed, 399 insertions(+), 41 deletions(-) > > diff --git a/tcg/i386/tcg-target.h b/tcg/i386/tcg-target.h > index e512648c95..147f82062b 100644 > --- a/tcg/i386/tcg-target.h > +++ b/tcg/i386/tcg-target.h > @@ -30,11 +30,10 @@ > > #ifdef __x86_64__ > # define TCG_TARGET_REG_BITS 64 > -# define TCG_TARGET_NB_REGS 16 > #else > # define TCG_TARGET_REG_BITS 32 > -# define TCG_TARGET_NB_REGS 8 > #endif > +# define TCG_TARGET_NB_REGS 24 > > typedef enum { > TCG_REG_EAX = 0, > @@ -56,6 +55,19 @@ typedef enum { > TCG_REG_R13, > TCG_REG_R14, > TCG_REG_R15, > + > + /* SSE registers; 64-bit has access to 8 more, but we won't > + need more than a few and using only the first 8 minimizes > + the need for a rex prefix on the sse instructions. */ > + TCG_REG_XMM0, > + TCG_REG_XMM1, > + TCG_REG_XMM2, > + TCG_REG_XMM3, > + TCG_REG_XMM4, > + TCG_REG_XMM5, > + TCG_REG_XMM6, > + TCG_REG_XMM7, > + > TCG_REG_RAX = TCG_REG_EAX, > TCG_REG_RCX = TCG_REG_ECX, > TCG_REG_RDX = TCG_REG_EDX, > @@ -79,6 +91,17 @@ extern bool have_bmi1; > extern bool have_bmi2; > extern bool have_popcnt; > > +#ifdef __SSE2__ > +#define have_sse2 true > +#else > +extern bool have_sse2; > +#endif > +#ifdef __AVX2__ > +#define have_avx2 true > +#else > +extern bool have_avx2; > +#endif > + > /* optional instructions */ > #define TCG_TARGET_HAS_div2_i32 1 > #define TCG_TARGET_HAS_rot_i32 1 > @@ -147,6 +170,25 @@ extern bool have_popcnt; > #define TCG_TARGET_HAS_mulsh_i64 0 > #endif > > +#define TCG_TARGET_HAS_v64 have_sse2 > +#define TCG_TARGET_HAS_v128 have_sse2 > +#define TCG_TARGET_HAS_v256 have_avx2 > + > +#define TCG_TARGET_HAS_andc_v64 TCG_TARGET_HAS_v64 > +#define TCG_TARGET_HAS_orc_v64 0 > +#define TCG_TARGET_HAS_not_v64 0 > +#define TCG_TARGET_HAS_neg_v64 0 > + > +#define TCG_TARGET_HAS_andc_v128 TCG_TARGET_HAS_v128 > +#define TCG_TARGET_HAS_orc_v128 0 > +#define TCG_TARGET_HAS_not_v128 0 > +#define TCG_TARGET_HAS_neg_v128 0 > + > +#define TCG_TARGET_HAS_andc_v256 TCG_TARGET_HAS_v256 > +#define TCG_TARGET_HAS_orc_v256 0 > +#define TCG_TARGET_HAS_not_v256 0 > +#define TCG_TARGET_HAS_neg_v256 0 > + > #define TCG_TARGET_deposit_i32_valid(ofs, len) \ > (have_bmi2 || \ > ((ofs) == 0 && (len) == 8) || \ > diff --git a/tcg/tcg-opc.h b/tcg/tcg-opc.h > index b1445a4c24..b84cd584fb 100644 > --- a/tcg/tcg-opc.h > +++ b/tcg/tcg-opc.h > @@ -212,13 +212,13 @@ DEF(qemu_st_i64, 0, TLADDR_ARGS + DATA64_ARGS, 1, > /* Host integer vector operations. */ > /* These opcodes are required whenever the base vector size is enabled. */ > > -DEF(mov_v64, 1, 1, 0, IMPL(TCG_TARGET_HAS_v64)) > -DEF(mov_v128, 1, 1, 0, IMPL(TCG_TARGET_HAS_v128)) > -DEF(mov_v256, 1, 1, 0, IMPL(TCG_TARGET_HAS_v256)) > +DEF(mov_v64, 1, 1, 0, TCG_OPF_NOT_PRESENT) > +DEF(mov_v128, 1, 1, 0, TCG_OPF_NOT_PRESENT) > +DEF(mov_v256, 1, 1, 0, TCG_OPF_NOT_PRESENT) > > -DEF(movi_v64, 1, 0, 1, IMPL(TCG_TARGET_HAS_v64)) > -DEF(movi_v128, 1, 0, 1, IMPL(TCG_TARGET_HAS_v128)) > -DEF(movi_v256, 1, 0, 1, IMPL(TCG_TARGET_HAS_v256)) > +DEF(movi_v64, 1, 0, 1, TCG_OPF_NOT_PRESENT) > +DEF(movi_v128, 1, 0, 1, TCG_OPF_NOT_PRESENT) > +DEF(movi_v256, 1, 0, 1, TCG_OPF_NOT_PRESENT) > > DEF(ld_v64, 1, 1, 1, IMPL(TCG_TARGET_HAS_v64)) > DEF(ld_v128, 1, 1, 1, IMPL(TCG_TARGET_HAS_v128)) > diff --git a/tcg/i386/tcg-target.inc.c b/tcg/i386/tcg-target.inc.c > index aeefb72aa0..0e01b54aa0 100644 > --- a/tcg/i386/tcg-target.inc.c > +++ b/tcg/i386/tcg-target.inc.c > @@ -31,7 +31,9 @@ static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = { > "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15", > #else > "%eax", "%ecx", "%edx", "%ebx", "%esp", "%ebp", "%esi", "%edi", > + NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, > #endif > + "%xmm0", "%xmm1", "%xmm2", "%xmm3", "%xmm4", "%xmm5", "%xmm6", "%xmm7", > }; > #endif > > @@ -61,6 +63,14 @@ static const int tcg_target_reg_alloc_order[] = { > TCG_REG_EDX, > TCG_REG_EAX, > #endif > + TCG_REG_XMM0, > + TCG_REG_XMM1, > + TCG_REG_XMM2, > + TCG_REG_XMM3, > + TCG_REG_XMM4, > + TCG_REG_XMM5, > + TCG_REG_XMM6, > + TCG_REG_XMM7, > }; > > static const int tcg_target_call_iarg_regs[] = { > @@ -94,7 +104,7 @@ static const int tcg_target_call_oarg_regs[] = { > #define TCG_CT_CONST_I32 0x400 > #define TCG_CT_CONST_WSZ 0x800 > > -/* Registers used with L constraint, which are the first argument > +/* Registers used with L constraint, which are the first argument > registers on x86_64, and two random call clobbered registers on > i386. */ > #if TCG_TARGET_REG_BITS == 64 > @@ -127,6 +137,16 @@ bool have_bmi1; > bool have_bmi2; > bool have_popcnt; > > +#ifndef have_sse2 > +bool have_sse2; > +#endif > +#ifdef have_avx2 > +#define have_avx1 have_avx2 > +#else > +static bool have_avx1; > +bool have_avx2; > +#endif > + > #ifdef CONFIG_CPUID_H > static bool have_movbe; > static bool have_lzcnt; > @@ -215,6 +235,10 @@ static const char *target_parse_constraint(TCGArgConstraint *ct, > /* With TZCNT/LZCNT, we can have operand-size as an input. */ > ct->ct |= TCG_CT_CONST_WSZ; > break; > + case 'x': > + ct->ct |= TCG_CT_REG; > + tcg_regset_set32(ct->u.regs, 0, 0xff0000); > + break; > > /* qemu_ld/st address constraint */ > case 'L': > @@ -292,6 +316,7 @@ static inline int tcg_target_const_match(tcg_target_long val, TCGType type, > #endif > #define P_SIMDF3 0x20000 /* 0xf3 opcode prefix */ > #define P_SIMDF2 0x40000 /* 0xf2 opcode prefix */ > +#define P_VEXL 0x80000 /* Set VEX.L = 1 */ > > #define OPC_ARITH_EvIz (0x81) > #define OPC_ARITH_EvIb (0x83) > @@ -324,13 +349,31 @@ static inline int tcg_target_const_match(tcg_target_long val, TCGType type, > #define OPC_MOVL_Iv (0xb8) > #define OPC_MOVBE_GyMy (0xf0 | P_EXT38) > #define OPC_MOVBE_MyGy (0xf1 | P_EXT38) > +#define OPC_MOVDQA_GyMy (0x6f | P_EXT | P_DATA16) > +#define OPC_MOVDQA_MyGy (0x7f | P_EXT | P_DATA16) > +#define OPC_MOVDQU_GyMy (0x6f | P_EXT | P_SIMDF3) > +#define OPC_MOVDQU_MyGy (0x7f | P_EXT | P_SIMDF3) > +#define OPC_MOVQ_GyMy (0x7e | P_EXT | P_SIMDF3) > +#define OPC_MOVQ_MyGy (0xd6 | P_EXT | P_DATA16) > #define OPC_MOVSBL (0xbe | P_EXT) > #define OPC_MOVSWL (0xbf | P_EXT) > #define OPC_MOVSLQ (0x63 | P_REXW) > #define OPC_MOVZBL (0xb6 | P_EXT) > #define OPC_MOVZWL (0xb7 | P_EXT) > +#define OPC_PADDB (0xfc | P_EXT | P_DATA16) > +#define OPC_PADDW (0xfd | P_EXT | P_DATA16) > +#define OPC_PADDD (0xfe | P_EXT | P_DATA16) > +#define OPC_PADDQ (0xd4 | P_EXT | P_DATA16) > +#define OPC_PAND (0xdb | P_EXT | P_DATA16) > +#define OPC_PANDN (0xdf | P_EXT | P_DATA16) > #define OPC_PDEP (0xf5 | P_EXT38 | P_SIMDF2) > #define OPC_PEXT (0xf5 | P_EXT38 | P_SIMDF3) > +#define OPC_POR (0xeb | P_EXT | P_DATA16) > +#define OPC_PSUBB (0xf8 | P_EXT | P_DATA16) > +#define OPC_PSUBW (0xf9 | P_EXT | P_DATA16) > +#define OPC_PSUBD (0xfa | P_EXT | P_DATA16) > +#define OPC_PSUBQ (0xfb | P_EXT | P_DATA16) > +#define OPC_PXOR (0xef | P_EXT | P_DATA16) > #define OPC_POP_r32 (0x58) > #define OPC_POPCNT (0xb8 | P_EXT | P_SIMDF3) > #define OPC_PUSH_r32 (0x50) > @@ -500,7 +543,8 @@ static void tcg_out_modrm(TCGContext *s, int opc, int r, int rm) > tcg_out8(s, 0xc0 | (LOWREGMASK(r) << 3) | LOWREGMASK(rm)); > } > > -static void tcg_out_vex_pfx_opc(TCGContext *s, int opc, int r, int v, int rm) > +static void tcg_out_vex_pfx_opc(TCGContext *s, int opc, int r, int v, > + int rm, int index) > { > int tmp; > > @@ -515,14 +559,16 @@ static void tcg_out_vex_pfx_opc(TCGContext *s, int opc, int r, int v, int rm) > } else if (opc & P_EXT) { > tmp = 1; > } else { > - tcg_abort(); > + g_assert_not_reached(); > } > - tmp |= 0x40; /* VEX.X */ > tmp |= (r & 8 ? 0 : 0x80); /* VEX.R */ > + tmp |= (index & 8 ? 0 : 0x40); /* VEX.X */ > tmp |= (rm & 8 ? 0 : 0x20); /* VEX.B */ > tcg_out8(s, tmp); > > tmp = (opc & P_REXW ? 0x80 : 0); /* VEX.W */ > + tmp |= (opc & P_VEXL ? 0x04 : 0); /* VEX.L */ > + > /* VEX.pp */ > if (opc & P_DATA16) { > tmp |= 1; /* 0x66 */ > @@ -538,7 +584,7 @@ static void tcg_out_vex_pfx_opc(TCGContext *s, int opc, int r, int v, int rm) > > static void tcg_out_vex_modrm(TCGContext *s, int opc, int r, int v, int rm) > { > - tcg_out_vex_pfx_opc(s, opc, r, v, rm); > + tcg_out_vex_pfx_opc(s, opc, r, v, rm, 0); > tcg_out8(s, 0xc0 | (LOWREGMASK(r) << 3) | LOWREGMASK(rm)); > } > > @@ -565,7 +611,7 @@ static void tcg_out_opc_pool_imm(TCGContext *s, int opc, int r, > static void tcg_out_vex_pool_imm(TCGContext *s, int opc, int r, int v, > tcg_target_ulong data) > { > - tcg_out_vex_pfx_opc(s, opc, r, v, 0); > + tcg_out_vex_pfx_opc(s, opc, r, v, 0, 0); > tcg_out_sfx_pool_imm(s, r, data); > } > > @@ -574,8 +620,8 @@ static void tcg_out_vex_pool_imm(TCGContext *s, int opc, int r, int v, > mode for absolute addresses, ~RM is the size of the immediate operand > that will follow the instruction. */ > > -static void tcg_out_modrm_sib_offset(TCGContext *s, int opc, int r, int rm, > - int index, int shift, intptr_t offset) > +static void tcg_out_sib_offset(TCGContext *s, int r, int rm, int index, > + int shift, intptr_t offset) > { > int mod, len; > > @@ -586,7 +632,6 @@ static void tcg_out_modrm_sib_offset(TCGContext *s, int opc, int r, int rm, > intptr_t pc = (intptr_t)s->code_ptr + 5 + ~rm; > intptr_t disp = offset - pc; > if (disp == (int32_t)disp) { > - tcg_out_opc(s, opc, r, 0, 0); > tcg_out8(s, (LOWREGMASK(r) << 3) | 5); > tcg_out32(s, disp); > return; > @@ -596,7 +641,6 @@ static void tcg_out_modrm_sib_offset(TCGContext *s, int opc, int r, int rm, > use of the MODRM+SIB encoding and is therefore larger than > rip-relative addressing. */ > if (offset == (int32_t)offset) { > - tcg_out_opc(s, opc, r, 0, 0); > tcg_out8(s, (LOWREGMASK(r) << 3) | 4); > tcg_out8(s, (4 << 3) | 5); > tcg_out32(s, offset); > @@ -604,10 +648,9 @@ static void tcg_out_modrm_sib_offset(TCGContext *s, int opc, int r, int rm, > } > > /* ??? The memory isn't directly addressable. */ > - tcg_abort(); > + g_assert_not_reached(); > } else { > /* Absolute address. */ > - tcg_out_opc(s, opc, r, 0, 0); > tcg_out8(s, (r << 3) | 5); > tcg_out32(s, offset); > return; > @@ -630,7 +673,6 @@ static void tcg_out_modrm_sib_offset(TCGContext *s, int opc, int r, int rm, > that would be used for %esp is the escape to the two byte form. */ > if (index < 0 && LOWREGMASK(rm) != TCG_REG_ESP) { > /* Single byte MODRM format. */ > - tcg_out_opc(s, opc, r, rm, 0); > tcg_out8(s, mod | (LOWREGMASK(r) << 3) | LOWREGMASK(rm)); > } else { > /* Two byte MODRM+SIB format. */ > @@ -644,7 +686,6 @@ static void tcg_out_modrm_sib_offset(TCGContext *s, int opc, int r, int rm, > tcg_debug_assert(index != TCG_REG_ESP); > } > > - tcg_out_opc(s, opc, r, rm, index); > tcg_out8(s, mod | (LOWREGMASK(r) << 3) | 4); > tcg_out8(s, (shift << 6) | (LOWREGMASK(index) << 3) | LOWREGMASK(rm)); > } > @@ -656,6 +697,21 @@ static void tcg_out_modrm_sib_offset(TCGContext *s, int opc, int r, int rm, > } > } > > +static void tcg_out_modrm_sib_offset(TCGContext *s, int opc, int r, int rm, > + int index, int shift, intptr_t offset) > +{ > + tcg_out_opc(s, opc, r, rm < 0 ? 0 : rm, index < 0 ? 0 : index); > + tcg_out_sib_offset(s, r, rm, index, shift, offset); > +} > + > +static void tcg_out_vex_modrm_sib_offset(TCGContext *s, int opc, int r, int v, > + int rm, int index, int shift, > + intptr_t offset) > +{ > + tcg_out_vex_pfx_opc(s, opc, r, v, rm < 0 ? 0 : rm, index < 0 ? 0 : index); > + tcg_out_sib_offset(s, r, rm, index, shift, offset); > +} > + > /* A simplification of the above with no index or shift. */ > static inline void tcg_out_modrm_offset(TCGContext *s, int opc, int r, > int rm, intptr_t offset) > @@ -663,6 +719,31 @@ static inline void tcg_out_modrm_offset(TCGContext *s, int opc, int r, > tcg_out_modrm_sib_offset(s, opc, r, rm, -1, 0, offset); > } > > +static inline void tcg_out_vex_modrm_offset(TCGContext *s, int opc, int r, > + int v, int rm, intptr_t offset) > +{ > + tcg_out_vex_modrm_sib_offset(s, opc, r, v, rm, -1, 0, offset); > +} > + > +static void tcg_out_maybe_vex_modrm(TCGContext *s, int opc, int r, int rm) > +{ > + if (have_avx1) { > + tcg_out_vex_modrm(s, opc, r, 0, rm); > + } else { > + tcg_out_modrm(s, opc, r, rm); > + } > +} > + > +static void tcg_out_maybe_vex_modrm_offset(TCGContext *s, int opc, int r, > + int rm, intptr_t offset) > +{ > + if (have_avx1) { > + tcg_out_vex_modrm_offset(s, opc, r, 0, rm, offset); > + } else { > + tcg_out_modrm_offset(s, opc, r, rm, offset); > + } > +} > + > /* Generate dest op= src. Uses the same ARITH_* codes as tgen_arithi. */ > static inline void tgen_arithr(TCGContext *s, int subop, int dest, int src) > { > @@ -673,12 +754,32 @@ static inline void tgen_arithr(TCGContext *s, int subop, int dest, int src) > tcg_out_modrm(s, OPC_ARITH_GvEv + (subop << 3) + ext, dest, src); > } > > -static inline void tcg_out_mov(TCGContext *s, TCGType type, > - TCGReg ret, TCGReg arg) > +static void tcg_out_mov(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg) > { > if (arg != ret) { > - int opc = OPC_MOVL_GvEv + (type == TCG_TYPE_I64 ? P_REXW : 0); > - tcg_out_modrm(s, opc, ret, arg); > + int opc = 0; > + > + switch (type) { > + case TCG_TYPE_I64: > + opc = P_REXW; > + /* fallthru */ > + case TCG_TYPE_I32: > + opc |= OPC_MOVL_GvEv; > + tcg_out_modrm(s, opc, ret, arg); > + break; > + > + case TCG_TYPE_V256: > + opc = P_VEXL; > + /* fallthru */ > + case TCG_TYPE_V128: > + case TCG_TYPE_V64: > + opc |= OPC_MOVDQA_GyMy; > + tcg_out_maybe_vex_modrm(s, opc, ret, arg); > + break; > + > + default: > + g_assert_not_reached(); > + } > } > } > > @@ -687,6 +788,27 @@ static void tcg_out_movi(TCGContext *s, TCGType type, > { > tcg_target_long diff; > > + switch (type) { > + case TCG_TYPE_I32: > + case TCG_TYPE_I64: > + break; > + > + case TCG_TYPE_V64: > + case TCG_TYPE_V128: > + case TCG_TYPE_V256: > + /* ??? Revisit this as the implementation progresses. */ > + tcg_debug_assert(arg == 0); > + if (have_avx1) { > + tcg_out_vex_modrm(s, OPC_PXOR, ret, ret, ret); > + } else { > + tcg_out_modrm(s, OPC_PXOR, ret, ret); > + } > + return; > + > + default: > + g_assert_not_reached(); > + } > + > if (arg == 0) { > tgen_arithr(s, ARITH_XOR, ret, ret); > return; > @@ -750,18 +872,54 @@ static inline void tcg_out_pop(TCGContext *s, int reg) > tcg_out_opc(s, OPC_POP_r32 + LOWREGMASK(reg), 0, reg, 0); > } > > -static inline void tcg_out_ld(TCGContext *s, TCGType type, TCGReg ret, > - TCGReg arg1, intptr_t arg2) > +static void tcg_out_ld(TCGContext *s, TCGType type, TCGReg ret, > + TCGReg arg1, intptr_t arg2) > { > - int opc = OPC_MOVL_GvEv + (type == TCG_TYPE_I64 ? P_REXW : 0); > - tcg_out_modrm_offset(s, opc, ret, arg1, arg2); > + switch (type) { > + case TCG_TYPE_I64: > + tcg_out_modrm_offset(s, OPC_MOVL_GvEv | P_REXW, ret, arg1, arg2); > + break; > + case TCG_TYPE_I32: > + tcg_out_modrm_offset(s, OPC_MOVL_GvEv, ret, arg1, arg2); > + break; > + case TCG_TYPE_V64: > + tcg_out_maybe_vex_modrm_offset(s, OPC_MOVQ_GyMy, ret, arg1, arg2); > + break; > + case TCG_TYPE_V128: > + tcg_out_maybe_vex_modrm_offset(s, OPC_MOVDQU_GyMy, ret, arg1, arg2); > + break; > + case TCG_TYPE_V256: > + tcg_out_vex_modrm_offset(s, OPC_MOVDQU_GyMy | P_VEXL, > + ret, 0, arg1, arg2); > + break; > + default: > + g_assert_not_reached(); > + } > } > > -static inline void tcg_out_st(TCGContext *s, TCGType type, TCGReg arg, > - TCGReg arg1, intptr_t arg2) > +static void tcg_out_st(TCGContext *s, TCGType type, TCGReg arg, > + TCGReg arg1, intptr_t arg2) > { > - int opc = OPC_MOVL_EvGv + (type == TCG_TYPE_I64 ? P_REXW : 0); > - tcg_out_modrm_offset(s, opc, arg, arg1, arg2); > + switch (type) { > + case TCG_TYPE_I64: > + tcg_out_modrm_offset(s, OPC_MOVL_EvGv | P_REXW, arg, arg1, arg2); > + break; > + case TCG_TYPE_I32: > + tcg_out_modrm_offset(s, OPC_MOVL_EvGv, arg, arg1, arg2); > + break; > + case TCG_TYPE_V64: > + tcg_out_maybe_vex_modrm_offset(s, OPC_MOVQ_MyGy, arg, arg1, arg2); > + break; > + case TCG_TYPE_V128: > + tcg_out_maybe_vex_modrm_offset(s, OPC_MOVDQU_MyGy, arg, arg1, arg2); > + break; > + case TCG_TYPE_V256: > + tcg_out_vex_modrm_offset(s, OPC_MOVDQU_MyGy | P_VEXL, > + arg, 0, arg1, arg2); > + break; > + default: > + g_assert_not_reached(); > + } > } > > static bool tcg_out_sti(TCGContext *s, TCGType type, TCGArg val, > @@ -773,6 +931,8 @@ static bool tcg_out_sti(TCGContext *s, TCGType type, TCGArg val, > return false; > } > rexw = P_REXW; > + } else if (type != TCG_TYPE_I32) { > + return false; > } > tcg_out_modrm_offset(s, OPC_MOVL_EvIz | rexw, 0, base, ofs); > tcg_out32(s, val); > @@ -1914,6 +2074,15 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, > case glue(glue(INDEX_op_, x), _i32) > #endif > > +#define OP_128_256(x) \ > + case glue(glue(INDEX_op_, x), _v256): \ > + rexw = P_VEXL; /* FALLTHRU */ \ > + case glue(glue(INDEX_op_, x), _v128) > + > +#define OP_64_128_256(x) \ > + OP_128_256(x): \ > + case glue(glue(INDEX_op_, x), _v64) > + > /* Hoist the loads of the most common arguments. */ > a0 = args[0]; > a1 = args[1]; > @@ -2379,19 +2548,94 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, > } > break; > > + OP_64_128_256(add8): > + c = OPC_PADDB; > + goto gen_simd; > + OP_64_128_256(add16): > + c = OPC_PADDW; > + goto gen_simd; > + OP_64_128_256(add32): > + c = OPC_PADDD; > + goto gen_simd; > + OP_128_256(add64): > + c = OPC_PADDQ; > + goto gen_simd; > + OP_64_128_256(sub8): > + c = OPC_PSUBB; > + goto gen_simd; > + OP_64_128_256(sub16): > + c = OPC_PSUBW; > + goto gen_simd; > + OP_64_128_256(sub32): > + c = OPC_PSUBD; > + goto gen_simd; > + OP_128_256(sub64): > + c = OPC_PSUBQ; > + goto gen_simd; > + OP_64_128_256(and): > + c = OPC_PAND; > + goto gen_simd; > + OP_64_128_256(andc): > + c = OPC_PANDN; > + goto gen_simd; > + OP_64_128_256(or): > + c = OPC_POR; > + goto gen_simd; > + OP_64_128_256(xor): > + c = OPC_PXOR; > + gen_simd: > + if (have_avx1) { > + tcg_out_vex_modrm(s, c, a0, a1, a2); > + } else { > + tcg_out_modrm(s, c, a0, a2); > + } > + break; > + > + case INDEX_op_ld_v64: > + c = TCG_TYPE_V64; > + goto gen_simd_ld; > + case INDEX_op_ld_v128: > + c = TCG_TYPE_V128; > + goto gen_simd_ld; > + case INDEX_op_ld_v256: > + c = TCG_TYPE_V256; > + gen_simd_ld: > + tcg_out_ld(s, c, a0, a1, a2); > + break; > + > + case INDEX_op_st_v64: > + c = TCG_TYPE_V64; > + goto gen_simd_st; > + case INDEX_op_st_v128: > + c = TCG_TYPE_V128; > + goto gen_simd_st; > + case INDEX_op_st_v256: > + c = TCG_TYPE_V256; > + gen_simd_st: > + tcg_out_st(s, c, a0, a1, a2); > + break; > + > case INDEX_op_mb: > tcg_out_mb(s, a0); > break; > case INDEX_op_mov_i32: /* Always emitted via tcg_out_mov. */ > case INDEX_op_mov_i64: > + case INDEX_op_mov_v64: > + case INDEX_op_mov_v128: > + case INDEX_op_mov_v256: > case INDEX_op_movi_i32: /* Always emitted via tcg_out_movi. */ > case INDEX_op_movi_i64: > + case INDEX_op_movi_v64: > + case INDEX_op_movi_v128: > + case INDEX_op_movi_v256: > case INDEX_op_call: /* Always emitted via tcg_out_call. */ > default: > tcg_abort(); > } > > #undef OP_32_64 > +#undef OP_128_256 > +#undef OP_64_128_256 > } > > static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op) > @@ -2417,6 +2661,9 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op) > = { .args_ct_str = { "r", "r", "L", "L" } }; > static const TCGTargetOpDef L_L_L_L > = { .args_ct_str = { "L", "L", "L", "L" } }; > + static const TCGTargetOpDef x_0_x = { .args_ct_str = { "x", "0", "x" } }; > + static const TCGTargetOpDef x_x_x = { .args_ct_str = { "x", "x", "x" } }; > + static const TCGTargetOpDef x_r = { .args_ct_str = { "x", "r" } }; > > switch (op) { > case INDEX_op_goto_ptr: > @@ -2620,6 +2867,52 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op) > return &s2; > } > > + case INDEX_op_ld_v64: > + case INDEX_op_ld_v128: > + case INDEX_op_ld_v256: > + case INDEX_op_st_v64: > + case INDEX_op_st_v128: > + case INDEX_op_st_v256: > + return &x_r; > + > + case INDEX_op_add8_v64: > + case INDEX_op_add8_v128: > + case INDEX_op_add16_v64: > + case INDEX_op_add16_v128: > + case INDEX_op_add32_v64: > + case INDEX_op_add32_v128: > + case INDEX_op_add64_v128: > + case INDEX_op_sub8_v64: > + case INDEX_op_sub8_v128: > + case INDEX_op_sub16_v64: > + case INDEX_op_sub16_v128: > + case INDEX_op_sub32_v64: > + case INDEX_op_sub32_v128: > + case INDEX_op_sub64_v128: > + case INDEX_op_and_v64: > + case INDEX_op_and_v128: > + case INDEX_op_andc_v64: > + case INDEX_op_andc_v128: > + case INDEX_op_or_v64: > + case INDEX_op_or_v128: > + case INDEX_op_xor_v64: > + case INDEX_op_xor_v128: > + return have_avx1 ? &x_x_x : &x_0_x; > + > + case INDEX_op_add8_v256: > + case INDEX_op_add16_v256: > + case INDEX_op_add32_v256: > + case INDEX_op_add64_v256: > + case INDEX_op_sub8_v256: > + case INDEX_op_sub16_v256: > + case INDEX_op_sub32_v256: > + case INDEX_op_sub64_v256: > + case INDEX_op_and_v256: > + case INDEX_op_andc_v256: > + case INDEX_op_or_v256: > + case INDEX_op_xor_v256: > + return &x_x_x; > + > default: > break; > } > @@ -2725,9 +3018,16 @@ static void tcg_out_nop_fill(tcg_insn_unit *p, int count) > static void tcg_target_init(TCGContext *s) > { > #ifdef CONFIG_CPUID_H > - unsigned a, b, c, d; > + unsigned a, b, c, d, b7 = 0; > int max = __get_cpuid_max(0, 0); > > + if (max >= 7) { > + /* BMI1 is available on AMD Piledriver and Intel Haswell CPUs. */ > + __cpuid_count(7, 0, a, b7, c, d); > + have_bmi1 = (b7 & bit_BMI) != 0; > + have_bmi2 = (b7 & bit_BMI2) != 0; > + } > + > if (max >= 1) { > __cpuid(1, a, b, c, d); > #ifndef have_cmov > @@ -2736,17 +3036,26 @@ static void tcg_target_init(TCGContext *s) > available, we'll use a small forward branch. */ > have_cmov = (d & bit_CMOV) != 0; > #endif > +#ifndef have_sse2 > + have_sse2 = (d & bit_SSE2) != 0; > +#endif > /* MOVBE is only available on Intel Atom and Haswell CPUs, so we > need to probe for it. */ > have_movbe = (c & bit_MOVBE) != 0; > have_popcnt = (c & bit_POPCNT) != 0; > - } > > - if (max >= 7) { > - /* BMI1 is available on AMD Piledriver and Intel Haswell CPUs. */ > - __cpuid_count(7, 0, a, b, c, d); > - have_bmi1 = (b & bit_BMI) != 0; > - have_bmi2 = (b & bit_BMI2) != 0; > +#ifndef have_avx2 > + /* There are a number of things we must check before we can be > + sure of not hitting invalid opcode. */ > + if (c & bit_OSXSAVE) { > + unsigned xcrl, xcrh; > + asm ("xgetbv" : "=a" (xcrl), "=d" (xcrh) : "c" (0)); > + if (xcrl & 6 == 6) { My picky compiler complains: /home/alex/lsrc/qemu/qemu.git/tcg/i386/tcg-target.inc.c: In function ‘tcg_target_init’: /home/alex/lsrc/qemu/qemu.git/tcg/i386/tcg-target.inc.c:3053:22: error: suggest parentheses around comparison in operand of ‘&’ [-Werror=parentheses] if (xcrl & 6 == 6) { > + have_avx1 = (c & bit_AVX) != 0; > + have_avx2 = (b7 & bit_AVX2) != 0; > + } > + } > +#endif > } > > max = __get_cpuid_max(0x8000000, 0); > @@ -2763,6 +3072,13 @@ static void tcg_target_init(TCGContext *s) > } else { > tcg_regset_set32(tcg_target_available_regs[TCG_TYPE_I32], 0, 0xff); > } > + if (have_sse2) { > + tcg_regset_set32(tcg_target_available_regs[TCG_TYPE_V64], 0, 0xff0000); > + tcg_regset_set32(tcg_target_available_regs[TCG_TYPE_V128], 0, 0xff0000); > + } > + if (have_avx2) { > + tcg_regset_set32(tcg_target_available_regs[TCG_TYPE_V256], 0, 0xff0000); > + } > > tcg_regset_clear(tcg_target_call_clobber_regs); > tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_EAX); -- Alex Bennée From MAILER-DAEMON Tue Aug 22 09:28:11 2017 Received: from list by lists.gnu.org with archive (Exim 4.71) id 1dk9E3-0003AU-2n for mharc-qemu-arm@gnu.org; Tue, 22 Aug 2017 09:28:11 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:53293) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dk9E0-00037v-RH for qemu-arm@nongnu.org; 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Tue, 22 Aug 2017 13:27:58 +0000 (UTC) From: =?UTF-8?q?Marc-Andr=C3=A9=20Lureau?= To: qemu-devel@nongnu.org Cc: =?UTF-8?q?Marc-Andr=C3=A9=20Lureau?= , "Dr. David Alan Gilbert" , Markus Armbruster , Eric Blake , Paolo Bonzini , Peter Maydell , Richard Henderson , Eduardo Habkost , David Gibson , Alexander Graf , qemu-arm@nongnu.org (open list:ARM), qemu-ppc@nongnu.org (open list:PowerPC) Date: Tue, 22 Aug 2017 15:22:55 +0200 Message-Id: <20170822132255.23945-55-marcandre.lureau@redhat.com> In-Reply-To: <20170822132255.23945-1-marcandre.lureau@redhat.com> References: <20170822132255.23945-1-marcandre.lureau@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 X-Scanned-By: MIMEDefang 2.79 on 10.5.11.16 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.39]); Tue, 22 Aug 2017 13:28:02 +0000 (UTC) Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.132.183.28 Subject: [Qemu-arm] [PATCH v2 54/54] qapi: make query-cpu-definitions depend on specific targets X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 22 Aug 2017 13:28:10 -0000 It depends on TARGET_PPC || TARGET_ARM || TARGET_I386 || TARGET_S390X. Signed-off-by: Marc-Andr=C3=A9 Lureau --- qapi-schema.json | 4 +++- include/sysemu/arch_init.h | 2 -- monitor.c | 22 ---------------------- qmp.c | 5 ----- stubs/arch-query-cpu-def.c | 10 ---------- target/arm/helper.c | 3 ++- target/i386/cpu.c | 3 ++- target/ppc/translate_init.c | 3 ++- target/s390x/cpu_models.c | 2 +- stubs/Makefile.objs | 1 - 10 files changed, 10 insertions(+), 45 deletions(-) delete mode 100644 stubs/arch-query-cpu-def.c diff --git a/qapi-schema.json b/qapi-schema.json index 127a2c71c6..194859f683 100644 --- a/qapi-schema.json +++ b/qapi-schema.json @@ -4433,7 +4433,9 @@ # # Since: 1.2.0 ## -{ 'command': 'query-cpu-definitions', 'returns': ['CpuDefinitionInfo'] } +{ 'command': 'query-cpu-definitions', 'returns': ['CpuDefinitionInfo'], + 'if': ['defined(NEED_CPU_H)', + 'defined(TARGET_PPC) || defined(TARGET_ARM) || defined(TARGET_I= 386) || defined(TARGET_S390X)'] } =20 ## # @CpuModelInfo: diff --git a/include/sysemu/arch_init.h b/include/sysemu/arch_init.h index fb3d20a1b8..e9721b9ce8 100644 --- a/include/sysemu/arch_init.h +++ b/include/sysemu/arch_init.h @@ -31,6 +31,4 @@ extern const uint32_t arch_type; int kvm_available(void); int xen_available(void); =20 -CpuDefinitionInfoList *arch_query_cpu_definitions(Error **errp); - #endif diff --git a/monitor.c b/monitor.c index ca67a584d2..ac400e65ee 100644 --- a/monitor.c +++ b/monitor.c @@ -957,26 +957,6 @@ static void qmp_query_qmp_schema(QDict *qdict, QObje= ct **ret_data, *ret_data =3D qobject_from_qlit(&qmp_schema_qlit); } =20 -/* - * We used to define commands in qmp-commands.hx in addition to the - * QAPI schema. This permitted defining some of them only in certain - * configurations. query-commands has always reflected that (good, - * because it lets QMP clients figure out what's actually available), - * while query-qmp-schema never did (not so good). This function is a - * hack to keep the configuration-specific commands defined exactly as - * before, even though qmp-commands.hx is gone. - * - * FIXME Educate the QAPI schema on configuration-specific commands, - * and drop this hack. - */ -static void qmp_unregister_commands_hack(void) -{ -#if !defined(TARGET_PPC) && !defined(TARGET_ARM) && !defined(TARGET_I386= ) \ - && !defined(TARGET_S390X) - qmp_unregister_command(&qmp_commands, "query-cpu-definitions"); -#endif -} - void monitor_init_qmp_commands(void) { /* @@ -996,8 +976,6 @@ void monitor_init_qmp_commands(void) qmp_register_command(&qmp_commands, "netdev_add", qmp_netdev_add, QCO_NO_OPTIONS); =20 - qmp_unregister_commands_hack(); - QTAILQ_INIT(&qmp_cap_negotiation_commands); qmp_register_command(&qmp_cap_negotiation_commands, "qmp_capabilitie= s", qmp_marshal_qmp_capabilities, QCO_NO_OPTIONS); diff --git a/qmp.c b/qmp.c index afa266ec1e..d57ccf1251 100644 --- a/qmp.c +++ b/qmp.c @@ -541,11 +541,6 @@ DevicePropertyInfoList *qmp_device_list_properties(c= onst char *typename, return prop_list; } =20 -CpuDefinitionInfoList *qmp_query_cpu_definitions(Error **errp) -{ - return arch_query_cpu_definitions(errp); -} - void qmp_add_client(const char *protocol, const char *fdname, bool has_skipauth, bool skipauth, bool has_tls, bool= tls, Error **errp) diff --git a/stubs/arch-query-cpu-def.c b/stubs/arch-query-cpu-def.c deleted file mode 100644 index cefe4beb82..0000000000 --- a/stubs/arch-query-cpu-def.c +++ /dev/null @@ -1,10 +0,0 @@ -#include "qemu/osdep.h" -#include "qemu-common.h" -#include "sysemu/arch_init.h" -#include "qapi/qmp/qerror.h" - -CpuDefinitionInfoList *arch_query_cpu_definitions(Error **errp) -{ - error_setg(errp, QERR_UNSUPPORTED); - return NULL; -} diff --git a/target/arm/helper.c b/target/arm/helper.c index fa60040361..54543a0b01 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -15,6 +15,7 @@ #include /* For crc32 */ #include "exec/semihost.h" #include "sysemu/kvm.h" +#include "qmp-commands.h" =20 #define ARM_CPU_FREQ 1000000000 /* FIXME: 1 GHz, should be configurable = */ =20 @@ -5332,7 +5333,7 @@ static void arm_cpu_add_definition(gpointer data, g= pointer user_data) *cpu_list =3D entry; } =20 -CpuDefinitionInfoList *arch_query_cpu_definitions(Error **errp) +CpuDefinitionInfoList *qmp_query_cpu_definitions(Error **errp) { CpuDefinitionInfoList *cpu_list =3D NULL; GSList *list; diff --git a/target/i386/cpu.c b/target/i386/cpu.c index d683e70a13..e5f61f6bff 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -36,6 +36,7 @@ #include "qapi/visitor.h" #include "qom/qom-qobject.h" #include "sysemu/arch_init.h" +#include "qmp-commands.h" =20 #if defined(CONFIG_KVM) #include @@ -2318,7 +2319,7 @@ static void x86_cpu_definition_entry(gpointer data,= gpointer user_data) *cpu_list =3D entry; } =20 -CpuDefinitionInfoList *arch_query_cpu_definitions(Error **errp) +CpuDefinitionInfoList *qmp_query_cpu_definitions(Error **errp) { CpuDefinitionInfoList *cpu_list =3D NULL; GSList *list =3D get_sorted_cpu_model_list(); diff --git a/target/ppc/translate_init.c b/target/ppc/translate_init.c index 8fb407ed73..5845a15296 100644 --- a/target/ppc/translate_init.c +++ b/target/ppc/translate_init.c @@ -34,6 +34,7 @@ #include "hw/ppc/ppc.h" #include "mmu-book3s-v3.h" #include "sysemu/qtest.h" +#include "qmp-commands.h" =20 //#define PPC_DUMP_CPU //#define PPC_DEBUG_SPR @@ -10401,7 +10402,7 @@ static void ppc_cpu_defs_entry(gpointer data, gpo= inter user_data) *first =3D entry; } =20 -CpuDefinitionInfoList *arch_query_cpu_definitions(Error **errp) +CpuDefinitionInfoList *qmp_query_cpu_definitions(Error **errp) { CpuDefinitionInfoList *cpu_list =3D NULL; GSList *list; diff --git a/target/s390x/cpu_models.c b/target/s390x/cpu_models.c index 863dce064f..8021dda341 100644 --- a/target/s390x/cpu_models.c +++ b/target/s390x/cpu_models.c @@ -387,7 +387,7 @@ static void create_cpu_model_list(ObjectClass *klass,= void *opaque) *cpu_list =3D entry; } =20 -CpuDefinitionInfoList *arch_query_cpu_definitions(Error **errp) +CpuDefinitionInfoList *qmp_query_cpu_definitions(Error **errp) { struct CpuDefinitionInfoListData list_data =3D { .list =3D NULL, diff --git a/stubs/Makefile.objs b/stubs/Makefile.objs index eb17628ede..67bf15261d 100644 --- a/stubs/Makefile.objs +++ b/stubs/Makefile.objs @@ -1,4 +1,3 @@ -stub-obj-y +=3D arch-query-cpu-def.o stub-obj-y +=3D bdrv-next-monitor-owned.o stub-obj-y +=3D blk-commit-all.o stub-obj-y +=3D blockdev-close-all-bdrv-states.o --=20 2.14.1.146.gd35faa819 From MAILER-DAEMON Tue Aug 22 09:53:13 2017 Received: from list by lists.gnu.org with archive (Exim 4.71) id 1dk9cG-0008Ui-SD for mharc-qemu-arm@gnu.org; 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X-Received-From: 2a00:1450:400c:c0c::231 Subject: Re: [Qemu-arm] [PATCH] hw/arm/digic: Mark device with user_creatable = false X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 22 Aug 2017 13:53:09 -0000 On 22 August 2017 at 14:15, Thomas Huth wrote: > QEMU currently hangs completely when the user is trying to do a > "device_add digic" on an unrelated ARM machine like integratorcp. > Looks like this device is not meant to be hot-pluggable at all, so > let's simply mark it with "user_creatable = false" to avoid the hang. > > Signed-off-by: Thomas Huth > --- > hw/arm/digic.c | 2 ++ > 1 file changed, 2 insertions(+) > > diff --git a/hw/arm/digic.c b/hw/arm/digic.c > index 94f3263..208dfb3 100644 > --- a/hw/arm/digic.c > +++ b/hw/arm/digic.c > @@ -101,6 +101,8 @@ static void digic_class_init(ObjectClass *oc, void *data) > DeviceClass *dc = DEVICE_CLASS(oc); > > dc->realize = digic_realize; > + /* Reason: Hangs QEMU when trying to device_add this directly */ > + dc->user_creatable = false; > } Maybe "uses serial_hds[]" is a better reason, or does it hang for some other reason? I think we should identify why we don't expect it to work and state that, rather than just the empirical "didn't work for me". Not that it really makes sense to have command line creation of SoC objects at all really. thanks -- PMM From MAILER-DAEMON Tue Aug 22 10:05:20 2017 Received: from list by lists.gnu.org with archive (Exim 4.71) id 1dk9nz-0001s9-Vk for mharc-qemu-arm@gnu.org; Tue, 22 Aug 2017 10:05:20 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:35612) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dk9ns-0001iw-RF for qemu-arm@nongnu.org; Tue, 22 Aug 2017 10:05:18 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dk9nn-0000hp-4D for qemu-arm@nongnu.org; Tue, 22 Aug 2017 10:05:12 -0400 Received: from mx1.redhat.com ([209.132.183.28]:59992) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1dk9nm-0000gV-UM; Tue, 22 Aug 2017 10:05:07 -0400 Received: from smtp.corp.redhat.com (int-mx02.intmail.prod.int.phx2.redhat.com [10.5.11.12]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id 58C1D7E45A; Tue, 22 Aug 2017 14:05:05 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mx1.redhat.com 58C1D7E45A Authentication-Results: ext-mx03.extmail.prod.ext.phx2.redhat.com; dmarc=none (p=none dis=none) header.from=redhat.com Authentication-Results: ext-mx03.extmail.prod.ext.phx2.redhat.com; spf=fail smtp.mailfrom=thuth@redhat.com Received: from [10.36.116.21] (ovpn-116-21.ams2.redhat.com [10.36.116.21]) by smtp.corp.redhat.com (Postfix) with ESMTPS id 4633986E9B; Tue, 22 Aug 2017 14:05:04 +0000 (UTC) To: Peter Maydell Cc: qemu-arm , QEMU Developers , Antony Pavlov References: <1503407712-9894-1-git-send-email-thuth@redhat.com> From: Thomas Huth Message-ID: <8fb75274-09a6-dbd3-5dba-1069d790b689@redhat.com> Date: Tue, 22 Aug 2017 16:05:02 +0200 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.2.0 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 7bit X-Scanned-By: MIMEDefang 2.79 on 10.5.11.12 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.27]); Tue, 22 Aug 2017 14:05:05 +0000 (UTC) X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.132.183.28 Subject: Re: [Qemu-arm] [PATCH] hw/arm/digic: Mark device with user_creatable = false X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 22 Aug 2017 14:05:18 -0000 On 22.08.2017 15:52, Peter Maydell wrote: > On 22 August 2017 at 14:15, Thomas Huth wrote: >> QEMU currently hangs completely when the user is trying to do a >> "device_add digic" on an unrelated ARM machine like integratorcp. >> Looks like this device is not meant to be hot-pluggable at all, so >> let's simply mark it with "user_creatable = false" to avoid the hang. >> >> Signed-off-by: Thomas Huth >> --- >> hw/arm/digic.c | 2 ++ >> 1 file changed, 2 insertions(+) >> >> diff --git a/hw/arm/digic.c b/hw/arm/digic.c >> index 94f3263..208dfb3 100644 >> --- a/hw/arm/digic.c >> +++ b/hw/arm/digic.c >> @@ -101,6 +101,8 @@ static void digic_class_init(ObjectClass *oc, void *data) >> DeviceClass *dc = DEVICE_CLASS(oc); >> >> dc->realize = digic_realize; >> + /* Reason: Hangs QEMU when trying to device_add this directly */ >> + dc->user_creatable = false; >> } > > Maybe "uses serial_hds[]" is a better reason, or does it hang for > some other reason? When I kill the hanging QEMU, the stack trace looks like this: #0 0x00007ffff13afaff in ppoll () at /lib64/libc.so.6 #1 0x0000555555bb3179 in qemu_poll_ns (__ss=0x0, __timeout=0x7fffffffda60, __nfds=, __fds=) at /usr/include/bits/poll2.h:77 #2 0x0000555555bb3179 in qemu_poll_ns (fds=, nfds=, timeout=timeout@entry=1000000000) at /home/thuth/devel/qemu/util/qemu-timer.c:334 #3 0x0000555555bb3f88 in main_loop_wait (timeout=1000000000) at /home/thuth/devel/qemu/util/main-loop.c:255 #4 0x0000555555bb3f88 in main_loop_wait (nonblocking=nonblocking@entry=0) at /home/thuth/devel/qemu/util/main-loop.c:515 #5 0x000055555578d927 in main () at /home/thuth/devel/qemu/vl.c:1917 #6 0x000055555578d927 in main (argc=, argv=, envp=) at /home/thuth/devel/qemu/vl.c:4791 I haven't investigated any further, but the usage of serial_hds in the realize function could certainly be the reason. At least it certainly is a reason that this device should not be creatable by the user - so let me send a v2 with the comment changed accordingly. Thomas From MAILER-DAEMON Tue Aug 22 10:07:55 2017 Received: from list by lists.gnu.org with archive (Exim 4.71) id 1dk9qV-0003tB-99 for mharc-qemu-arm@gnu.org; Tue, 22 Aug 2017 10:07:55 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:36292) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dk9qS-0003rm-1L for qemu-arm@nongnu.org; Tue, 22 Aug 2017 10:07:53 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dk9qQ-0002zz-Ui for qemu-arm@nongnu.org; Tue, 22 Aug 2017 10:07:51 -0400 Received: from mail-wr0-x22c.google.com ([2a00:1450:400c:c0c::22c]:36257) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1dk9qQ-0002zN-Od for qemu-arm@nongnu.org; Tue, 22 Aug 2017 10:07:50 -0400 Received: by mail-wr0-x22c.google.com with SMTP id f8so90445610wrf.3 for ; Tue, 22 Aug 2017 07:07:50 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:in-reply-to:references:from:date:message-id:subject:to :cc; bh=zRvWD0ylVhcnWa/SVfGI+LL5lbQBXtMpQi4bwGqVUME=; b=fN1Xs8xKLb6KZ3gUgooxjaQjBiMiNztysmogAJe8EtwwPnK4fdgxjiBzl8TWQfGqb2 wndiuIXCkNtScBBNCxVTj4f8MwtsuzANVcHnSC7KMBiF9RhUI7GwgiXo15UQGX1PZ31X v2xBn/DjIbagQU09vv5Q1pWg2uhzopOOKcqSg= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:in-reply-to:references:from:date :message-id:subject:to:cc; bh=zRvWD0ylVhcnWa/SVfGI+LL5lbQBXtMpQi4bwGqVUME=; b=oeSC3elvBF/eCvoguVeBfunKlJx28YHhyNnBBanmyLH4n4J/mo462JYhG7jDyGA8jf vbNuQIma/FhoJDM8SWt5XqGy/XZytMjZScj1DNmK5iRc6Yr+gyNdQw7fazVi1eqMuLiv a+uvO62gBycCcyQwUVBPZvTHE5pOp8c+F3kTotCAheFTaMwEswCuzS1a3c15e3aFSnJ+ hFHhiVa6r6Q4ZEdt6r7I/RYzF0tch+2t+CRDYieRgjoP/oFR6NBuAnVghoYIQ5KoI3X1 7ctE9WGBYY4FCrLgFCr+sG3x40JhoYyt8kYhltk2vxEOR6kQwocOTaPfxHIA09JRL3xn AgUA== X-Gm-Message-State: AHYfb5jpWDwxBX2oPHReeuLeNRmrNUBGFZmgvP7yYTNCSZzx4v5lFhLY v5l84s5UxBQVbgXl5tZqB89xCjuEFjFG X-Received: by 10.223.155.132 with SMTP id d4mr554939wrc.196.1503410869477; Tue, 22 Aug 2017 07:07:49 -0700 (PDT) MIME-Version: 1.0 Received: by 10.223.134.54 with HTTP; Tue, 22 Aug 2017 07:07:28 -0700 (PDT) In-Reply-To: <8fb75274-09a6-dbd3-5dba-1069d790b689@redhat.com> References: <1503407712-9894-1-git-send-email-thuth@redhat.com> <8fb75274-09a6-dbd3-5dba-1069d790b689@redhat.com> From: Peter Maydell Date: Tue, 22 Aug 2017 15:07:28 +0100 Message-ID: To: Thomas Huth Cc: qemu-arm , QEMU Developers , Antony Pavlov Content-Type: text/plain; charset="UTF-8" X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:400c:c0c::22c Subject: Re: [Qemu-arm] [PATCH] hw/arm/digic: Mark device with user_creatable = false X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 22 Aug 2017 14:07:54 -0000 On 22 August 2017 at 15:05, Thomas Huth wrote: > On 22.08.2017 15:52, Peter Maydell wrote: >> On 22 August 2017 at 14:15, Thomas Huth wrote: >>> QEMU currently hangs completely when the user is trying to do a >>> "device_add digic" on an unrelated ARM machine like integratorcp. >>> Looks like this device is not meant to be hot-pluggable at all, so >>> let's simply mark it with "user_creatable = false" to avoid the hang. >>> >>> Signed-off-by: Thomas Huth >>> --- >>> hw/arm/digic.c | 2 ++ >>> 1 file changed, 2 insertions(+) >>> >>> diff --git a/hw/arm/digic.c b/hw/arm/digic.c >>> index 94f3263..208dfb3 100644 >>> --- a/hw/arm/digic.c >>> +++ b/hw/arm/digic.c >>> @@ -101,6 +101,8 @@ static void digic_class_init(ObjectClass *oc, void *data) >>> DeviceClass *dc = DEVICE_CLASS(oc); >>> >>> dc->realize = digic_realize; >>> + /* Reason: Hangs QEMU when trying to device_add this directly */ >>> + dc->user_creatable = false; >>> } >> >> Maybe "uses serial_hds[]" is a better reason, or does it hang for >> some other reason? > > When I kill the hanging QEMU, the stack trace looks like this: > > #0 0x00007ffff13afaff in ppoll () at /lib64/libc.so.6 > #1 0x0000555555bb3179 in qemu_poll_ns (__ss=0x0, __timeout=0x7fffffffda60, __nfds=, __fds=) > at /usr/include/bits/poll2.h:77 > #2 0x0000555555bb3179 in qemu_poll_ns (fds=, nfds=, timeout=timeout@entry=1000000000) > at /home/thuth/devel/qemu/util/qemu-timer.c:334 > #3 0x0000555555bb3f88 in main_loop_wait (timeout=1000000000) at /home/thuth/devel/qemu/util/main-loop.c:255 > #4 0x0000555555bb3f88 in main_loop_wait (nonblocking=nonblocking@entry=0) at /home/thuth/devel/qemu/util/main-loop.c:515 > #5 0x000055555578d927 in main () at /home/thuth/devel/qemu/vl.c:1917 > #6 0x000055555578d927 in main (argc=, argv=, envp=) at /home/thuth/devel/qemu/vl.c:4791 > > I haven't investigated any further, but the usage of serial_hds > in the realize function could certainly be the reason. At least > it certainly is a reason that this device should not be creatable > by the user - so let me send a v2 with the comment changed > accordingly. Has QEMU itself actually hung (no response to monitor etc), or is that just the guest sitting doing nothing? "QEMU is sat in the main loop waiting for something to happen" is what you'd expect in the latter case. The backtraces for the other threads might be of interest or might also be unhelpful. thanks -- PMM From MAILER-DAEMON Tue Aug 22 10:18:46 2017 Received: from list by lists.gnu.org with archive (Exim 4.71) id 1dkA10-0003u7-0A for mharc-qemu-arm@gnu.org; Tue, 22 Aug 2017 10:18:46 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:39596) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dkA0w-0003sL-IH for qemu-arm@nongnu.org; Tue, 22 Aug 2017 10:18:44 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dkA0t-0002wL-CI for qemu-arm@nongnu.org; Tue, 22 Aug 2017 10:18:42 -0400 Received: from mx1.redhat.com ([209.132.183.28]:44772) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1dkA0t-0002vw-3I; Tue, 22 Aug 2017 10:18:39 -0400 Received: from smtp.corp.redhat.com (int-mx02.intmail.prod.int.phx2.redhat.com [10.5.11.12]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id 2195AC047B71; Tue, 22 Aug 2017 14:18:38 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mx1.redhat.com 2195AC047B71 Authentication-Results: ext-mx07.extmail.prod.ext.phx2.redhat.com; dmarc=none (p=none dis=none) header.from=redhat.com Authentication-Results: ext-mx07.extmail.prod.ext.phx2.redhat.com; spf=fail smtp.mailfrom=thuth@redhat.com Received: from [10.36.116.21] (ovpn-116-21.ams2.redhat.com [10.36.116.21]) by smtp.corp.redhat.com (Postfix) with ESMTPS id 13C7381883; Tue, 22 Aug 2017 14:18:36 +0000 (UTC) To: Peter Maydell Cc: qemu-arm , QEMU Developers , Antony Pavlov References: <1503407712-9894-1-git-send-email-thuth@redhat.com> <8fb75274-09a6-dbd3-5dba-1069d790b689@redhat.com> From: Thomas Huth Message-ID: <6bdaf758-98d1-d99d-20ae-b0f25747d6b1@redhat.com> Date: Tue, 22 Aug 2017 16:18:35 +0200 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.2.0 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=utf-8 Content-Language: en-US X-Scanned-By: MIMEDefang 2.79 on 10.5.11.12 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.31]); Tue, 22 Aug 2017 14:18:38 +0000 (UTC) Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.132.183.28 Subject: Re: [Qemu-arm] [PATCH] hw/arm/digic: Mark device with user_creatable = false X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 22 Aug 2017 14:18:44 -0000 On 22.08.2017 16:07, Peter Maydell wrote: > On 22 August 2017 at 15:05, Thomas Huth wrote: >> On 22.08.2017 15:52, Peter Maydell wrote: >>> On 22 August 2017 at 14:15, Thomas Huth wrote: >>>> QEMU currently hangs completely when the user is trying to do a >>>> "device_add digic" on an unrelated ARM machine like integratorcp. >>>> Looks like this device is not meant to be hot-pluggable at all, so >>>> let's simply mark it with "user_creatable =3D false" to avoid the ha= ng. >>>> >>>> Signed-off-by: Thomas Huth >>>> --- >>>> hw/arm/digic.c | 2 ++ >>>> 1 file changed, 2 insertions(+) >>>> >>>> diff --git a/hw/arm/digic.c b/hw/arm/digic.c >>>> index 94f3263..208dfb3 100644 >>>> --- a/hw/arm/digic.c >>>> +++ b/hw/arm/digic.c >>>> @@ -101,6 +101,8 @@ static void digic_class_init(ObjectClass *oc, vo= id *data) >>>> DeviceClass *dc =3D DEVICE_CLASS(oc); >>>> >>>> dc->realize =3D digic_realize; >>>> + /* Reason: Hangs QEMU when trying to device_add this directly *= / >>>> + dc->user_creatable =3D false; >>>> } >>> >>> Maybe "uses serial_hds[]" is a better reason, or does it hang for >>> some other reason? >> >> When I kill the hanging QEMU, the stack trace looks like this: >> >> #0 0x00007ffff13afaff in ppoll () at /lib64/libc.so.6 >> #1 0x0000555555bb3179 in qemu_poll_ns (__ss=3D0x0, __timeout=3D0x7fff= ffffda60, __nfds=3D, __fds=3D) >> at /usr/include/bits/poll2.h:77 >> #2 0x0000555555bb3179 in qemu_poll_ns (fds=3D, nfds=3D= , timeout=3Dtimeout@entry=3D1000000000) >> at /home/thuth/devel/qemu/util/qemu-timer.c:334 >> #3 0x0000555555bb3f88 in main_loop_wait (timeout=3D1000000000) at /ho= me/thuth/devel/qemu/util/main-loop.c:255 >> #4 0x0000555555bb3f88 in main_loop_wait (nonblocking=3Dnonblocking@en= try=3D0) at /home/thuth/devel/qemu/util/main-loop.c:515 >> #5 0x000055555578d927 in main () at /home/thuth/devel/qemu/vl.c:1917 >> #6 0x000055555578d927 in main (argc=3D, argv=3D, envp=3D) at /home/thuth/devel/qemu/vl.c:4791 >> >> I haven't investigated any further, but the usage of serial_hds >> in the realize function could certainly be the reason. At least >> it certainly is a reason that this device should not be creatable >> by the user - so let me send a v2 with the comment changed >> accordingly. >=20 > Has QEMU itself actually hung (no response to monitor etc), or is > that just the guest sitting doing nothing? "QEMU is sat in the main > loop waiting for something to happen" is what you'd expect in the > latter case. The backtraces for the other threads might be of > interest or might also be unhelpful. I thought that QEMU would hang ... but now I checked again, and it's just that it does not return to the monitor prompt as expected. If I press CTRL-a c again, I can get to the monitor again. Anyway, QEMU then dies if I try to remove the device with device_del: qemu/qdev-monitor.c:872:qdev_unplug: assertion failed: (hotplug_ctrl) ... so let's simply mark it with user_creatable =3D false and call it a day... ;-) Thomas From MAILER-DAEMON Tue Aug 22 10:25:06 2017 Received: from list by lists.gnu.org with archive (Exim 4.71) id 1dkA78-0001Br-16 for mharc-qemu-arm@gnu.org; Tue, 22 Aug 2017 10:25:06 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:41267) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dkA75-00019I-A7 for qemu-arm@nongnu.org; Tue, 22 Aug 2017 10:25:04 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dkA70-0006lb-QZ for qemu-arm@nongnu.org; Tue, 22 Aug 2017 10:25:03 -0400 Received: from 1.mo68.mail-out.ovh.net ([46.105.41.146]:33930) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1dkA70-0006gu-KT for qemu-arm@nongnu.org; Tue, 22 Aug 2017 10:24:58 -0400 Received: from player789.ha.ovh.net (b9.ovh.net [213.186.33.59]) by mo68.mail-out.ovh.net (Postfix) with ESMTP id B6EFB76D9D for ; Tue, 22 Aug 2017 16:24:49 +0200 (CEST) Received: from zorba.kaod.org (i15-les03-th2-31-37-69-229.sfr.lns.abo.bbox.fr [31.37.69.229]) (Authenticated sender: postmaster@kaod.org) by player789.ha.ovh.net (Postfix) with ESMTPSA id 5AD5426007F; Tue, 22 Aug 2017 16:24:41 +0200 (CEST) To: Thomas Huth , Peter Maydell , qemu-arm@nongnu.org Cc: Andrew Jeffery , Jeremy Kerr , qemu-devel@nongnu.org References: <1503406059-7280-1-git-send-email-thuth@redhat.com> From: =?UTF-8?Q?C=c3=a9dric_Le_Goater?= Message-ID: Date: Tue, 22 Aug 2017 16:24:40 +0200 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.2.1 MIME-Version: 1.0 In-Reply-To: <1503406059-7280-1-git-send-email-thuth@redhat.com> Content-Type: text/plain; charset=utf-8 Content-Language: en-US X-Ovh-Tracer-Id: 4517391902168943424 X-VR-SPAMSTATE: OK X-VR-SPAMSCORE: -100 X-VR-SPAMCAUSE: gggruggvucftvghtrhhoucdtuddrfeelledrtddtgdehlecutefuodetggdotefrodftvfcurfhrohhfihhlvgemucfqggfjpdevjffgvefmvefgnecuuegrihhlohhuthemuceftddtnecusecvtfgvtghiphhivghnthhsucdlqddutddtmd Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 46.105.41.146 Subject: Re: [Qemu-arm] [PATCH] hw/arm/aspeed_soc: Mark devices as user_creatable = false X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 22 Aug 2017 14:25:04 -0000 On 08/22/2017 02:47 PM, Thomas Huth wrote: > QEMU currently aborts if the user is accidentially trying to > do something like this: >=20 > $ aarch64-softmmu/qemu-system-aarch64 -S -M integratorcp -nographic > QEMU 2.9.93 monitor - type 'help' for more information > (qemu) device_add ast2400 > Unexpected error in error_set_from_qdev_prop_error() > at hw/core/qdev-properties.c:1032: > Aborted (core dumped) >=20 > The ast2400 SoC devices are clearly not creatable by the user since > they are using the serial_hds and nd_table arrays directly in their > realize function, so mark them with user_creatable =3D false. yes. I suppose we don't need to instantiate such an object without=20 the machine. And even for unit tests, we would rather use the=20 individual controller models. > Signed-off-by: Thomas Huth Reviewed-by: C=C3=A9dric Le Goater Thanks, C. > --- > hw/arm/aspeed_soc.c | 2 ++ > 1 file changed, 2 insertions(+) >=20 > diff --git a/hw/arm/aspeed_soc.c b/hw/arm/aspeed_soc.c > index 5529024..7f1be04 100644 > --- a/hw/arm/aspeed_soc.c > +++ b/hw/arm/aspeed_soc.c > @@ -338,6 +338,8 @@ static void aspeed_soc_class_init(ObjectClass *oc, = void *data) > =20 > sc->info =3D (AspeedSoCInfo *) data; > dc->realize =3D aspeed_soc_realize; > + /* Reason: Uses serial_hds and nd_table in realize() directly */ > + dc->user_creatable =3D false; > } > =20 > static const TypeInfo aspeed_soc_type_info =3D { >=20 From MAILER-DAEMON Tue Aug 22 10:30:43 2017 Received: from list by lists.gnu.org with archive (Exim 4.71) id 1dkACY-0005aN-S9 for mharc-qemu-arm@gnu.org; Tue, 22 Aug 2017 10:30:42 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:42549) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dkACW-0005Xb-0y for qemu-arm@nongnu.org; Tue, 22 Aug 2017 10:30:40 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dkACR-0001qy-2y for qemu-arm@nongnu.org; Tue, 22 Aug 2017 10:30:39 -0400 Received: from mx1.redhat.com ([209.132.183.28]:35106) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1dkACQ-0001qE-SO; Tue, 22 Aug 2017 10:30:35 -0400 Received: from smtp.corp.redhat.com (int-mx03.intmail.prod.int.phx2.redhat.com [10.5.11.13]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id C739680C06; Tue, 22 Aug 2017 14:30:33 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mx1.redhat.com C739680C06 Authentication-Results: ext-mx02.extmail.prod.ext.phx2.redhat.com; dmarc=none (p=none dis=none) header.from=redhat.com Authentication-Results: ext-mx02.extmail.prod.ext.phx2.redhat.com; spf=fail smtp.mailfrom=thuth@redhat.com Received: from thh440s.redhat.com (ovpn-116-21.ams2.redhat.com [10.36.116.21]) by smtp.corp.redhat.com (Postfix) with ESMTP id 8797C60C16; Tue, 22 Aug 2017 14:30:32 +0000 (UTC) From: Thomas Huth To: Peter Maydell , qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Antony Pavlov Date: Tue, 22 Aug 2017 16:30:31 +0200 Message-Id: <1503412231-13961-1-git-send-email-thuth@redhat.com> X-Scanned-By: MIMEDefang 2.79 on 10.5.11.13 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.26]); Tue, 22 Aug 2017 14:30:33 +0000 (UTC) X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.132.183.28 Subject: [Qemu-arm] [PATCH v2] hw/arm/digic: Mark device with user_creatable = false X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 22 Aug 2017 14:30:41 -0000 QEMU currently shows some unexpected behavior when the user trys to do a "device_add digic" on an unrelated ARM machine like integratorcp in "-nographic" mode (the device_add command does not immediately return to the monitor prompt), and trying to "device_del" the device later results in a "qemu/qdev-monitor.c:872:qdev_unplug: assertion failed: (hotplug_ctrl)" error condition. Looking at the realize function of the device, it uses serial_hds directly and this means that the device can not be added a second time, so let's simply mark it with "user_creatable = false" now. Signed-off-by: Thomas Huth --- v2: Updated the comment and the patch description hw/arm/digic.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/hw/arm/digic.c b/hw/arm/digic.c index 94f3263..6184020 100644 --- a/hw/arm/digic.c +++ b/hw/arm/digic.c @@ -101,6 +101,8 @@ static void digic_class_init(ObjectClass *oc, void *data) DeviceClass *dc = DEVICE_CLASS(oc); dc->realize = digic_realize; + /* Reason: Uses serial_hds in the realize function --> not usable twice */ + dc->user_creatable = false; } static const TypeInfo digic_type_info = { -- 1.8.3.1 From MAILER-DAEMON Tue Aug 22 11:06:27 2017 Received: from list by lists.gnu.org with archive (Exim 4.71) id 1dkAl6-0003aK-Sr for mharc-qemu-arm@gnu.org; Tue, 22 Aug 2017 11:06:27 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:52280) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dkAl4-0003YG-WA for qemu-arm@nongnu.org; Tue, 22 Aug 2017 11:06:23 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dkAl1-0001m5-Pz for qemu-arm@nongnu.org; Tue, 22 Aug 2017 11:06:22 -0400 Received: from mx1.redhat.com ([209.132.183.28]:60210) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1dkAl1-0001lm-Jq; Tue, 22 Aug 2017 11:06:19 -0400 Received: from smtp.corp.redhat.com (int-mx01.intmail.prod.int.phx2.redhat.com [10.5.11.11]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id 94E4BC04D313; Tue, 22 Aug 2017 15:06:18 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mx1.redhat.com 94E4BC04D313 Authentication-Results: ext-mx07.extmail.prod.ext.phx2.redhat.com; dmarc=none (p=none dis=none) header.from=redhat.com Authentication-Results: ext-mx07.extmail.prod.ext.phx2.redhat.com; spf=fail smtp.mailfrom=thuth@redhat.com Received: from thh440s.redhat.com (ovpn-116-21.ams2.redhat.com [10.36.116.21]) by smtp.corp.redhat.com (Postfix) with ESMTP id 32C727E21E; Tue, 22 Aug 2017 15:06:16 +0000 (UTC) From: Thomas Huth To: Peter Maydell , qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: "Edgar E. Iglesias" , Alistair Francis , KONRAD Frederic , qemu-trivial@nongnu.org Date: Tue, 22 Aug 2017 17:06:15 +0200 Message-Id: <1503414375-21009-1-git-send-email-thuth@redhat.com> X-Scanned-By: MIMEDefang 2.79 on 10.5.11.11 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.31]); Tue, 22 Aug 2017 15:06:18 +0000 (UTC) X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.132.183.28 Subject: [Qemu-arm] [PATCH] hw/misc/auxbus.c: Mark the aux-to-i2c-bridge device as non-hotpluggable X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 22 Aug 2017 15:06:24 -0000 QEMU currently aborts if the user tries to do something like this: $ aarch64-softmmu/qemu-system-aarch64 -S -M integratorcp -nographic QEMU 2.9.93 monitor - type 'help' for more information (qemu) device_add aux-to-i2c-bridge,id=x (qemu) device_del x ** ERROR:qemu/qdev-monitor.c:872:qdev_unplug: assertion failed: (hotplug_ctrl) Aborted (core dumped) Looks like the device is not hot-pluggable, so let's mark it accordingly. Signed-off-by: Thomas Huth --- hw/misc/auxbus.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/hw/misc/auxbus.c b/hw/misc/auxbus.c index 8a90ddd..2c62515 100644 --- a/hw/misc/auxbus.c +++ b/hw/misc/auxbus.c @@ -222,9 +222,17 @@ static inline I2CBus *aux_bridge_get_i2c_bus(AUXTOI2CState *bridge) return bridge->i2c_bus; } +static void aux_bridge_class_init(ObjectClass *oc, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(oc); + + dc->hotpluggable = false; +} + static const TypeInfo aux_to_i2c_type_info = { .name = TYPE_AUXTOI2C, .parent = TYPE_DEVICE, + .class_init = aux_bridge_class_init, .instance_size = sizeof(AUXTOI2CState), .instance_init = aux_bridge_init }; -- 1.8.3.1 From MAILER-DAEMON Tue Aug 22 11:09:11 2017 Received: from list by lists.gnu.org with archive (Exim 4.71) id 1dkAnm-0006MY-Hn for mharc-qemu-arm@gnu.org; Tue, 22 Aug 2017 11:09:10 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:53170) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dkAni-0006JQ-4b for qemu-arm@nongnu.org; Tue, 22 Aug 2017 11:09:07 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dkAng-000371-Vk for qemu-arm@nongnu.org; Tue, 22 Aug 2017 11:09:06 -0400 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:36936) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1dkAng-00031e-Nf; Tue, 22 Aug 2017 11:09:04 -0400 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1dkAnZ-0004dW-5g; Tue, 22 Aug 2017 16:08:57 +0100 From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: patches@linaro.org Date: Tue, 22 Aug 2017 16:08:39 +0100 Message-Id: <1503414539-28762-1-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 2.7.4 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-arm] [PATCH 00/20] first steps towards v8M support X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 22 Aug 2017 15:09:07 -0000 Hi; this patchset is the first slice of work aiming at support of the ARM v8M architecture. It doesn't do anything by itself (there's no CPU yet that enables the new feature) and there's a lot more work still to do to get something actually functional, but it seems better to push the work out for review a slice at a time rather than hanging onto it and sending a 100-patch set at the end. This patchset sits on top of my target-arm.next tree, which has the 'preliminary patchset' I sent out a while back in it. It includes: * implementation of PMSAv8 * banking of most of the main CPU registers which need it (the NVIC proper also gets banked exceptions, and the systick device is banked, but neither of those are done here) * the "let secure access the NS view of the NVIC" alias region * an implementation of the BXNS instruction, mostly as the simplest thing that needs the banking of stack pointers We don't yet actually properly swap the stack pointer around on other kinds of S<->NS transition including exception entry and exit. I have some patches working in that direction, so if the BXNS patch doesn't have enough context yet to make sense I can keep it around and resend it with those later. Next thing probably will be the NVIC changes, once I've got my head around the priority related changes v8M brings... Series available also at https://git.linaro.org/people/peter.maydell/qemu-arm.git v8m (on top of the target-arm.next stuff.) thanks -- PMM Peter Maydell (20): target/arm: Implement ARMv8M's PMSAv8 registers target/arm: Implement new PMSAv8 behaviour target/arm: Add state field, feature bit and migration for v8M secure state target/arm: Register second AddressSpace for secure v8M CPUs target/arm: Add MMU indexes for secure v8M target/arm: Make BASEPRI register banked for v8M target/arm: Make PRIMASK register banked for v8M target/arm: Make FAULTMASK register banked for v8M target/arm: Make CONTROL register banked for v8M nvic: Add NS alias SCS region target/arm: Make VTOR register banked for v8M target/arm: Make MPU_MAIR0, MPU_MAIR1 registers banked for v8M target/arm: Make MPU_RBAR, MPU_RLAR banked for v8M target/arm: Make MPU_RNR register banked for v8M target/arm: Make MPU_CTRL register banked for v8M target/arm: Make CCR register banked for v8M target/arm: Make MMFAR banked for v8M target/arm: Make CFSR register banked for v8M target/arm: Move regime_is_secure() to target/arm/internals.h target/arm: Implement BXNS, and banked stack pointers include/hw/intc/armv7m_nvic.h | 1 + target/arm/cpu.h | 100 ++++++++++++-- target/arm/helper.h | 2 + target/arm/internals.h | 26 ++++ target/arm/translate.h | 1 + hw/intc/armv7m_nvic.c | 294 +++++++++++++++++++++++++++++++++------ target/arm/cpu.c | 82 ++++++++--- target/arm/helper.c | 315 +++++++++++++++++++++++++++++++++--------- target/arm/machine.c | 104 ++++++++++++-- target/arm/translate.c | 52 ++++++- 10 files changed, 820 insertions(+), 157 deletions(-) -- 2.7.4 From MAILER-DAEMON Tue Aug 22 11:09:12 2017 Received: from list by lists.gnu.org with archive (Exim 4.71) id 1dkAno-0006PT-7L for mharc-qemu-arm@gnu.org; Tue, 22 Aug 2017 11:09:12 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:53234) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dkAnl-0006Le-42 for qemu-arm@nongnu.org; Tue, 22 Aug 2017 11:09:10 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dkAnj-00039g-RV for qemu-arm@nongnu.org; Tue, 22 Aug 2017 11:09:09 -0400 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:36936) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1dkAnj-00031e-KT; Tue, 22 Aug 2017 11:09:07 -0400 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1dkAne-0004fz-9a; Tue, 22 Aug 2017 16:09:02 +0100 From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: patches@linaro.org Date: Tue, 22 Aug 2017 16:08:46 +0100 Message-Id: <1503414539-28762-8-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1503414539-28762-1-git-send-email-peter.maydell@linaro.org> References: <1503414539-28762-1-git-send-email-peter.maydell@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-arm] [PATCH 07/20] target/arm: Make PRIMASK register banked for v8M X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 22 Aug 2017 15:09:10 -0000 Make the PRIMASK register banked if v8M security extensions are enabled. Note that we do not yet implement the functionality of the new AIRCR.PRIS bit (which allows the effect of the NS copy of PRIMASK to be restricted). Signed-off-by: Peter Maydell --- target/arm/cpu.h | 2 +- hw/intc/armv7m_nvic.c | 2 +- target/arm/helper.c | 4 ++-- target/arm/machine.c | 9 +++++++-- 4 files changed, 11 insertions(+), 6 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 0c28dfd..fee337b 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -431,7 +431,7 @@ typedef struct CPUARMState { uint32_t bfar; /* BusFault Address */ unsigned mpu_ctrl; /* MPU_CTRL */ int exception; - uint32_t primask; + uint32_t primask[2]; uint32_t faultmask; uint32_t secure; /* Is CPU in Secure state? (not guest visible) */ } v7m; diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c index 2a41e5d..a654792 100644 --- a/hw/intc/armv7m_nvic.c +++ b/hw/intc/armv7m_nvic.c @@ -169,7 +169,7 @@ static inline int nvic_exec_prio(NVICState *s) if (env->v7m.faultmask) { running = -1; - } else if (env->v7m.primask) { + } else if (env->v7m.primask[env->v7m.secure]) { running = 0; } else if (env->v7m.basepri[env->v7m.secure] > 0) { running = env->v7m.basepri[env->v7m.secure] & nvic_gprio_mask(s); diff --git a/target/arm/helper.c b/target/arm/helper.c index 1087f19..c0a6dbd 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -8835,7 +8835,7 @@ uint32_t HELPER(v7m_mrs)(CPUARMState *env, uint32_t reg) return (env->v7m.control & R_V7M_CONTROL_SPSEL_MASK) ? env->regs[13] : env->v7m.other_sp; case 16: /* PRIMASK */ - return env->v7m.primask; + return env->v7m.primask[env->v7m.secure]; case 17: /* BASEPRI */ case 18: /* BASEPRI_MAX */ return env->v7m.basepri[env->v7m.secure]; @@ -8895,7 +8895,7 @@ void HELPER(v7m_msr)(CPUARMState *env, uint32_t maskreg, uint32_t val) } break; case 16: /* PRIMASK */ - env->v7m.primask = val & 1; + env->v7m.primask[env->v7m.secure] = val & 1; break; case 17: /* BASEPRI */ env->v7m.basepri[env->v7m.secure] = val & 0xff; diff --git a/target/arm/machine.c b/target/arm/machine.c index 8476efd..6f0f6c9 100644 --- a/target/arm/machine.c +++ b/target/arm/machine.c @@ -103,7 +103,7 @@ static const VMStateDescription vmstate_m_faultmask_primask = { .minimum_version_id = 1, .fields = (VMStateField[]) { VMSTATE_UINT32(env.v7m.faultmask, ARMCPU), - VMSTATE_UINT32(env.v7m.primask, ARMCPU), + VMSTATE_UINT32(env.v7m.primask[M_REG_NS], ARMCPU), VMSTATE_END_OF_LIST() } }; @@ -251,6 +251,7 @@ static const VMStateDescription vmstate_m_security = { .fields = (VMStateField[]) { VMSTATE_UINT32(env.v7m.secure, ARMCPU), VMSTATE_UINT32(env.v7m.basepri[M_REG_S], ARMCPU), + VMSTATE_UINT32(env.v7m.primask[M_REG_S], ARMCPU), VMSTATE_END_OF_LIST() } }; @@ -271,9 +272,13 @@ static int get_cpsr(QEMUFile *f, void *opaque, size_t size, * differences are that the T bit is not in the same place, the * primask/faultmask info may be in the CPSR I and F bits, and * we do not want the mode bits. + * We know that this cleanup happened before v8M, so there + * is no complication with banked primask/faultmask. */ uint32_t newval = val; + assert(!arm_feature(env, ARM_FEATURE_M_SECURITY)); + newval &= (CPSR_NZCV | CPSR_Q | CPSR_IT | CPSR_GE); if (val & CPSR_T) { newval |= XPSR_T; @@ -287,7 +292,7 @@ static int get_cpsr(QEMUFile *f, void *opaque, size_t size, env->v7m.faultmask = 1; } if (val & CPSR_I) { - env->v7m.primask = 1; + env->v7m.primask[M_REG_NS] = 1; } val = newval; } -- 2.7.4 From MAILER-DAEMON Tue Aug 22 11:09:13 2017 Received: from list by lists.gnu.org with archive (Exim 4.71) id 1dkAno-0006TM-V2 for mharc-qemu-arm@gnu.org; Tue, 22 Aug 2017 11:09:13 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:53192) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dkAnj-0006Kj-7A for qemu-arm@nongnu.org; Tue, 22 Aug 2017 11:09:10 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dkAnh-000382-TP for qemu-arm@nongnu.org; Tue, 22 Aug 2017 11:09:07 -0400 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:36936) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1dkAnh-00031e-Lj; Tue, 22 Aug 2017 11:09:05 -0400 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1dkAnf-0004gf-2e; Tue, 22 Aug 2017 16:09:03 +0100 From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: patches@linaro.org Date: Tue, 22 Aug 2017 16:08:47 +0100 Message-Id: <1503414539-28762-9-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1503414539-28762-1-git-send-email-peter.maydell@linaro.org> References: <1503414539-28762-1-git-send-email-peter.maydell@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-arm] [PATCH 08/20] target/arm: Make FAULTMASK register banked for v8M X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 22 Aug 2017 15:09:10 -0000 Make the FAULTMASK register banked if v8M security extensions are enabled. Note that we do not yet implement the functionality of the new AIRCR.PRIS bit (which allows the effect of the NS copy of FAULTMASK to be restricted). This patch includes the code to determine for v8M which copy of FAULTMASK should be updated on exception exit; further changes will be required to the exception exit code in general to support v8M, so this is just a small piece of that. The v8M ARM ARM introduces a notation where individual paragraphs are labelled with R (for rule) or I (for information) followed by a random group of subscript letters. In comments where we want to refer to a particular part of the manual we use this convention, which should be more stable across document revisions than using section or page numbers. Signed-off-by: Peter Maydell --- target/arm/cpu.h | 14 ++++++++++++-- hw/intc/armv7m_nvic.c | 9 ++++++++- target/arm/helper.c | 20 ++++++++++++++++---- target/arm/machine.c | 5 +++-- 4 files changed, 39 insertions(+), 9 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index fee337b..edd4c9e 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -432,7 +432,7 @@ typedef struct CPUARMState { unsigned mpu_ctrl; /* MPU_CTRL */ int exception; uint32_t primask[2]; - uint32_t faultmask; + uint32_t faultmask[2]; uint32_t secure; /* Is CPU in Secure state? (not guest visible) */ } v7m; @@ -1443,6 +1443,16 @@ void armv7m_nvic_acknowledge_irq(void *opaque); * (Ignoring -1, this is the same as the RETTOBASE value before completion.) */ int armv7m_nvic_complete_irq(void *opaque, int irq); +/** + * armv7m_nvic_raw_execution_priority: return the raw execution priority + * @opaque: the NVIC + * + * Returns: the raw execution priority as defined by the v8M architecture. + * This is the execution priority minus the effects of AIRCR.PRIS, + * and minus any PRIMASK/FAULTMASK/BASEPRI priority boosting. + * (v8M ARM ARM I_PKLD.) + */ +int armv7m_nvic_raw_execution_priority(void *opaque); /* Interface for defining coprocessor registers. * Registers are defined in tables of arm_cp_reginfo structs @@ -2228,7 +2238,7 @@ static inline int cpu_mmu_index(CPUARMState *env, bool ifetch) * we're in a HardFault or NMI handler. */ if ((env->v7m.exception > 0 && env->v7m.exception <= 3) - || env->v7m.faultmask) { + || env->v7m.faultmask[env->v7m.secure]) { mmu_idx = ARMMMUIdx_MNegPri; } diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c index a654792..babdc3b 100644 --- a/hw/intc/armv7m_nvic.c +++ b/hw/intc/armv7m_nvic.c @@ -167,7 +167,7 @@ static inline int nvic_exec_prio(NVICState *s) CPUARMState *env = &s->cpu->env; int running; - if (env->v7m.faultmask) { + if (env->v7m.faultmask[env->v7m.secure]) { running = -1; } else if (env->v7m.primask[env->v7m.secure]) { running = 0; @@ -187,6 +187,13 @@ bool armv7m_nvic_can_take_pending_exception(void *opaque) return nvic_exec_prio(s) > nvic_pending_prio(s); } +int armv7m_nvic_raw_execution_priority(void *opaque) +{ + NVICState *s = opaque; + + return s->exception_prio; +} + /* caller must call nvic_irq_update() after this */ static void set_prio(NVICState *s, unsigned irq, uint8_t prio) { diff --git a/target/arm/helper.c b/target/arm/helper.c index c0a6dbd..b8f3b23 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -6171,8 +6171,20 @@ static void do_v7m_exception_exit(ARMCPU *cpu) } if (env->v7m.exception != ARMV7M_EXCP_NMI) { - /* Auto-clear FAULTMASK on return from other than NMI */ - env->v7m.faultmask = 0; + /* Auto-clear FAULTMASK on return from other than NMI. + * If the security extension is implemented then this only + * happens if the raw execution priority is >= 0; the + * value of the ES bit in the exception return value indicates + * which security state's faultmask to clear. (v8M ARM ARM R_KBNF.) + */ + if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { + int es = type & 1; + if (armv7m_nvic_raw_execution_priority(env->nvic) >= 0) { + env->v7m.faultmask[es] = 0; + } + } else { + env->v7m.faultmask[M_REG_NS] = 0; + } } switch (armv7m_nvic_complete_irq(env->nvic, env->v7m.exception)) { @@ -8840,7 +8852,7 @@ uint32_t HELPER(v7m_mrs)(CPUARMState *env, uint32_t reg) case 18: /* BASEPRI_MAX */ return env->v7m.basepri[env->v7m.secure]; case 19: /* FAULTMASK */ - return env->v7m.faultmask; + return env->v7m.faultmask[env->v7m.secure]; default: qemu_log_mask(LOG_GUEST_ERROR, "Attempt to read unknown special" " register %d\n", reg); @@ -8908,7 +8920,7 @@ void HELPER(v7m_msr)(CPUARMState *env, uint32_t maskreg, uint32_t val) } break; case 19: /* FAULTMASK */ - env->v7m.faultmask = val & 1; + env->v7m.faultmask[env->v7m.secure] = val & 1; break; case 20: /* CONTROL */ /* Writing to the SPSEL bit only has an effect if we are in diff --git a/target/arm/machine.c b/target/arm/machine.c index 6f0f6c9..bd7aba1 100644 --- a/target/arm/machine.c +++ b/target/arm/machine.c @@ -102,7 +102,7 @@ static const VMStateDescription vmstate_m_faultmask_primask = { .version_id = 1, .minimum_version_id = 1, .fields = (VMStateField[]) { - VMSTATE_UINT32(env.v7m.faultmask, ARMCPU), + VMSTATE_UINT32(env.v7m.faultmask[M_REG_NS], ARMCPU), VMSTATE_UINT32(env.v7m.primask[M_REG_NS], ARMCPU), VMSTATE_END_OF_LIST() } @@ -252,6 +252,7 @@ static const VMStateDescription vmstate_m_security = { VMSTATE_UINT32(env.v7m.secure, ARMCPU), VMSTATE_UINT32(env.v7m.basepri[M_REG_S], ARMCPU), VMSTATE_UINT32(env.v7m.primask[M_REG_S], ARMCPU), + VMSTATE_UINT32(env.v7m.faultmask[M_REG_S], ARMCPU), VMSTATE_END_OF_LIST() } }; @@ -289,7 +290,7 @@ static int get_cpsr(QEMUFile *f, void *opaque, size_t size, * transferred using the vmstate_m_faultmask_primask subsection. */ if (val & CPSR_F) { - env->v7m.faultmask = 1; + env->v7m.faultmask[M_REG_NS] = 1; } if (val & CPSR_I) { env->v7m.primask[M_REG_NS] = 1; -- 2.7.4 From MAILER-DAEMON Tue Aug 22 11:09:17 2017 Received: from list by lists.gnu.org with archive (Exim 4.71) id 1dkAns-0006Wc-Kv for mharc-qemu-arm@gnu.org; Tue, 22 Aug 2017 11:09:16 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:53308) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dkAnn-0006Nr-FV for qemu-arm@nongnu.org; Tue, 22 Aug 2017 11:09:12 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dkAnl-0003Be-Op for qemu-arm@nongnu.org; Tue, 22 Aug 2017 11:09:11 -0400 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:36962) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1dkAnl-00037y-IQ; Tue, 22 Aug 2017 11:09:09 -0400 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1dkAnc-0004eU-4e; Tue, 22 Aug 2017 16:09:00 +0100 From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: patches@linaro.org Date: Tue, 22 Aug 2017 16:08:43 +0100 Message-Id: <1503414539-28762-5-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1503414539-28762-1-git-send-email-peter.maydell@linaro.org> References: <1503414539-28762-1-git-send-email-peter.maydell@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-arm] [PATCH 04/20] target/arm: Register second AddressSpace for secure v8M CPUs X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 22 Aug 2017 15:09:12 -0000 If a v8M CPU supports the security extension then we need to give it two AddressSpaces, the same way we do already for an A profile core with EL3. Signed-off-by: Peter Maydell --- target/arm/cpu.c | 13 ++++++------- 1 file changed, 6 insertions(+), 7 deletions(-) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index f32317e..ae866be 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -843,22 +843,21 @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp) init_cpreg_list(cpu); #ifndef CONFIG_USER_ONLY - if (cpu->has_el3) { - cs->num_ases = 2; - } else { - cs->num_ases = 1; - } - - if (cpu->has_el3) { + if (cpu->has_el3 || arm_feature(env, ARM_FEATURE_M_SECURITY)) { AddressSpace *as; + cs->num_ases = 2; + if (!cpu->secure_memory) { cpu->secure_memory = cs->memory; } as = address_space_init_shareable(cpu->secure_memory, "cpu-secure-memory"); cpu_address_space_init(cs, as, ARMASIdx_S); + } else { + cs->num_ases = 1; } + cpu_address_space_init(cs, address_space_init_shareable(cs->memory, "cpu-memory"), -- 2.7.4 From MAILER-DAEMON Tue Aug 22 11:09:18 2017 Received: from list by lists.gnu.org with archive (Exim 4.71) id 1dkAnu-0006Zx-24 for mharc-qemu-arm@gnu.org; Tue, 22 Aug 2017 11:09:18 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:53262) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dkAnl-0006Lh-T3 for qemu-arm@nongnu.org; Tue, 22 Aug 2017 11:09:12 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dkAnk-0003A9-Cu for qemu-arm@nongnu.org; Tue, 22 Aug 2017 11:09:09 -0400 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:36966) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1dkAnk-00039F-2M; Tue, 22 Aug 2017 11:09:08 -0400 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1dkAnj-0004j5-52; Tue, 22 Aug 2017 16:09:07 +0100 From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: patches@linaro.org Date: Tue, 22 Aug 2017 16:08:52 +0100 Message-Id: <1503414539-28762-14-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1503414539-28762-1-git-send-email-peter.maydell@linaro.org> References: <1503414539-28762-1-git-send-email-peter.maydell@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-arm] [PATCH 13/20] target/arm: Make MPU_RBAR, MPU_RLAR banked for v8M X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 22 Aug 2017 15:09:12 -0000 Make the MPU registers MPU_MAIR0 and MPU_MAIR1 banked if v8M security extensions are enabled. We can freely add more items to vmstate_m_security without breaking migration compatibility, because no CPU currently has the ARM_FEATURE_M_SECURITY bit enabled and so this subsection is not yet used by anything. Signed-off-by: Peter Maydell --- target/arm/cpu.h | 4 ++-- hw/intc/armv7m_nvic.c | 8 ++++---- target/arm/cpu.c | 26 ++++++++++++++++++++------ target/arm/helper.c | 11 ++++++----- target/arm/machine.c | 12 ++++++++---- 5 files changed, 40 insertions(+), 21 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 2f59828..12fa95e 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -543,8 +543,8 @@ typedef struct CPUARMState { * pmsav7.rnr (region number register) * pmsav7_dregion (number of configured regions) */ - uint32_t *rbar; - uint32_t *rlar; + uint32_t *rbar[2]; + uint32_t *rlar[2]; uint32_t mair0[2]; uint32_t mair1[2]; } pmsav8; diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c index e98eb95..9ced7af 100644 --- a/hw/intc/armv7m_nvic.c +++ b/hw/intc/armv7m_nvic.c @@ -564,7 +564,7 @@ static uint32_t nvic_readl(NVICState *s, uint32_t offset, MemTxAttrs attrs) if (region >= cpu->pmsav7_dregion) { return 0; } - return cpu->env.pmsav8.rbar[region]; + return cpu->env.pmsav8.rbar[attrs.secure][region]; } if (region >= cpu->pmsav7_dregion) { @@ -591,7 +591,7 @@ static uint32_t nvic_readl(NVICState *s, uint32_t offset, MemTxAttrs attrs) if (region >= cpu->pmsav7_dregion) { return 0; } - return cpu->env.pmsav8.rlar[region]; + return cpu->env.pmsav8.rlar[attrs.secure][region]; } if (region >= cpu->pmsav7_dregion) { @@ -756,7 +756,7 @@ static void nvic_writel(NVICState *s, uint32_t offset, uint32_t value, if (region >= cpu->pmsav7_dregion) { return; } - cpu->env.pmsav8.rbar[region] = value; + cpu->env.pmsav8.rbar[attrs.secure][region] = value; tlb_flush(CPU(cpu)); return; } @@ -806,7 +806,7 @@ static void nvic_writel(NVICState *s, uint32_t offset, uint32_t value, if (region >= cpu->pmsav7_dregion) { return; } - cpu->env.pmsav8.rlar[region] = value; + cpu->env.pmsav8.rlar[attrs.secure][region] = value; tlb_flush(CPU(cpu)); return; } diff --git a/target/arm/cpu.c b/target/arm/cpu.c index ae8af19..333029c 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -235,10 +235,20 @@ static void arm_cpu_reset(CPUState *s) if (arm_feature(env, ARM_FEATURE_PMSA)) { if (cpu->pmsav7_dregion > 0) { if (arm_feature(env, ARM_FEATURE_V8)) { - memset(env->pmsav8.rbar, 0, - sizeof(*env->pmsav8.rbar) * cpu->pmsav7_dregion); - memset(env->pmsav8.rlar, 0, - sizeof(*env->pmsav8.rlar) * cpu->pmsav7_dregion); + memset(env->pmsav8.rbar[M_REG_NS], 0, + sizeof(*env->pmsav8.rbar[M_REG_NS]) + * cpu->pmsav7_dregion); + memset(env->pmsav8.rlar[M_REG_NS], 0, + sizeof(*env->pmsav8.rlar[M_REG_NS]) + * cpu->pmsav7_dregion); + if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { + memset(env->pmsav8.rbar[M_REG_S], 0, + sizeof(*env->pmsav8.rbar[M_REG_S]) + * cpu->pmsav7_dregion); + memset(env->pmsav8.rlar[M_REG_S], 0, + sizeof(*env->pmsav8.rlar[M_REG_S]) + * cpu->pmsav7_dregion); + } } else if (arm_feature(env, ARM_FEATURE_V7)) { memset(env->pmsav7.drbar, 0, sizeof(*env->pmsav7.drbar) * cpu->pmsav7_dregion); @@ -823,8 +833,12 @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp) if (nr) { if (arm_feature(env, ARM_FEATURE_V8)) { /* PMSAv8 */ - env->pmsav8.rbar = g_new0(uint32_t, nr); - env->pmsav8.rlar = g_new0(uint32_t, nr); + env->pmsav8.rbar[M_REG_NS] = g_new0(uint32_t, nr); + env->pmsav8.rlar[M_REG_NS] = g_new0(uint32_t, nr); + if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { + env->pmsav8.rbar[M_REG_S] = g_new0(uint32_t, nr); + env->pmsav8.rlar[M_REG_S] = g_new0(uint32_t, nr); + } } else { env->pmsav7.drbar = g_new0(uint32_t, nr); env->pmsav7.drsr = g_new0(uint32_t, nr); diff --git a/target/arm/helper.c b/target/arm/helper.c index b1bb507..5394cef 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -8442,6 +8442,7 @@ static bool get_phys_addr_pmsav8(CPUARMState *env, uint32_t address, { ARMCPU *cpu = arm_env_get_cpu(env); bool is_user = regime_is_user(env, mmu_idx); + uint32_t secure = regime_is_secure(env, mmu_idx); int n; int matchregion = -1; bool hit = false; @@ -8468,10 +8469,10 @@ static bool get_phys_addr_pmsav8(CPUARMState *env, uint32_t address, * with bits [4:0] all zeroes, but the limit address is bits * [31:5] from the register with bits [4:0] all ones. */ - uint32_t base = env->pmsav8.rbar[n] & ~0x1f; - uint32_t limit = env->pmsav8.rlar[n] | 0x1f; + uint32_t base = env->pmsav8.rbar[secure][n] & ~0x1f; + uint32_t limit = env->pmsav8.rlar[secure][n] | 0x1f; - if (!(env->pmsav8.rlar[n] & 0x1)) { + if (!(env->pmsav8.rlar[secure][n] & 0x1)) { /* Region disabled */ continue; } @@ -8520,8 +8521,8 @@ static bool get_phys_addr_pmsav8(CPUARMState *env, uint32_t address, /* hit using the background region */ get_phys_addr_pmsav7_default(env, mmu_idx, address, prot); } else { - uint32_t ap = extract32(env->pmsav8.rbar[matchregion], 1, 2); - uint32_t xn = extract32(env->pmsav8.rbar[matchregion], 0, 1); + uint32_t ap = extract32(env->pmsav8.rbar[secure][matchregion], 1, 2); + uint32_t xn = extract32(env->pmsav8.rbar[secure][matchregion], 0, 1); if (m_is_system_region(env, address)) { /* System space is always execute never */ diff --git a/target/arm/machine.c b/target/arm/machine.c index 414a879..05c6c7a 100644 --- a/target/arm/machine.c +++ b/target/arm/machine.c @@ -225,10 +225,10 @@ static const VMStateDescription vmstate_pmsav8 = { .minimum_version_id = 1, .needed = pmsav8_needed, .fields = (VMStateField[]) { - VMSTATE_VARRAY_UINT32(env.pmsav8.rbar, ARMCPU, pmsav7_dregion, 0, - vmstate_info_uint32, uint32_t), - VMSTATE_VARRAY_UINT32(env.pmsav8.rlar, ARMCPU, pmsav7_dregion, 0, - vmstate_info_uint32, uint32_t), + VMSTATE_VARRAY_UINT32(env.pmsav8.rbar[M_REG_NS], ARMCPU, pmsav7_dregion, + 0, vmstate_info_uint32, uint32_t), + VMSTATE_VARRAY_UINT32(env.pmsav8.rlar[M_REG_NS], ARMCPU, pmsav7_dregion, + 0, vmstate_info_uint32, uint32_t), VMSTATE_UINT32(env.pmsav8.mair0[M_REG_NS], ARMCPU), VMSTATE_UINT32(env.pmsav8.mair1[M_REG_NS], ARMCPU), VMSTATE_END_OF_LIST() @@ -257,6 +257,10 @@ static const VMStateDescription vmstate_m_security = { VMSTATE_UINT32(env.v7m.vecbase[M_REG_S], ARMCPU), VMSTATE_UINT32(env.pmsav8.mair0[M_REG_S], ARMCPU), VMSTATE_UINT32(env.pmsav8.mair1[M_REG_S], ARMCPU), + VMSTATE_VARRAY_UINT32(env.pmsav8.rbar[M_REG_S], ARMCPU, pmsav7_dregion, + 0, vmstate_info_uint32, uint32_t), + VMSTATE_VARRAY_UINT32(env.pmsav8.rlar[M_REG_S], ARMCPU, pmsav7_dregion, + 0, vmstate_info_uint32, uint32_t), VMSTATE_END_OF_LIST() } }; -- 2.7.4 From MAILER-DAEMON Tue Aug 22 11:09:18 2017 Received: from list by lists.gnu.org with archive (Exim 4.71) id 1dkAnu-0006aL-7B for mharc-qemu-arm@gnu.org; Tue, 22 Aug 2017 11:09:18 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:53306) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dkAnn-0006No-Dq for qemu-arm@nongnu.org; Tue, 22 Aug 2017 11:09:12 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dkAnl-0003C0-UV for qemu-arm@nongnu.org; Tue, 22 Aug 2017 11:09:11 -0400 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:36974) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1dkAnl-0003Ah-LZ; Tue, 22 Aug 2017 11:09:09 -0400 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1dkAnk-0004jy-Mk; Tue, 22 Aug 2017 16:09:08 +0100 From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: patches@linaro.org Date: Tue, 22 Aug 2017 16:08:54 +0100 Message-Id: <1503414539-28762-16-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1503414539-28762-1-git-send-email-peter.maydell@linaro.org> References: <1503414539-28762-1-git-send-email-peter.maydell@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-arm] [PATCH 15/20] target/arm: Make MPU_CTRL register banked for v8M X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 22 Aug 2017 15:09:13 -0000 Make the MPU_CTRL register banked if v8M security extensions are enabled. Signed-off-by: Peter Maydell --- target/arm/cpu.h | 2 +- hw/intc/armv7m_nvic.c | 9 +++++---- target/arm/helper.c | 5 +++-- target/arm/machine.c | 3 ++- 4 files changed, 11 insertions(+), 8 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 43d36d6..78cd3f0 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -429,7 +429,7 @@ typedef struct CPUARMState { uint32_t dfsr; /* Debug Fault Status Register */ uint32_t mmfar; /* MemManage Fault Address */ uint32_t bfar; /* BusFault Address */ - unsigned mpu_ctrl; /* MPU_CTRL */ + unsigned mpu_ctrl[2]; /* MPU_CTRL */ int exception; uint32_t primask[2]; uint32_t faultmask[2]; diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c index c3c214c..a4c298f 100644 --- a/hw/intc/armv7m_nvic.c +++ b/hw/intc/armv7m_nvic.c @@ -541,7 +541,7 @@ static uint32_t nvic_readl(NVICState *s, uint32_t offset, MemTxAttrs attrs) return cpu->pmsav7_dregion << 8; break; case 0xd94: /* MPU_CTRL */ - return cpu->env.v7m.mpu_ctrl; + return cpu->env.v7m.mpu_ctrl[attrs.secure]; case 0xd98: /* MPU_RNR */ return cpu->env.pmsav7.rnr[attrs.secure]; case 0xd9c: /* MPU_RBAR */ @@ -720,9 +720,10 @@ static void nvic_writel(NVICState *s, uint32_t offset, uint32_t value, qemu_log_mask(LOG_GUEST_ERROR, "MPU_CTRL: HFNMIENA and !ENABLE is " "UNPREDICTABLE\n"); } - cpu->env.v7m.mpu_ctrl = value & (R_V7M_MPU_CTRL_ENABLE_MASK | - R_V7M_MPU_CTRL_HFNMIENA_MASK | - R_V7M_MPU_CTRL_PRIVDEFENA_MASK); + cpu->env.v7m.mpu_ctrl[attrs.secure] + = value & (R_V7M_MPU_CTRL_ENABLE_MASK | + R_V7M_MPU_CTRL_HFNMIENA_MASK | + R_V7M_MPU_CTRL_PRIVDEFENA_MASK); tlb_flush(CPU(cpu)); break; case 0xd98: /* MPU_RNR */ diff --git a/target/arm/helper.c b/target/arm/helper.c index 48e0fc6..4a2148c 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -7096,7 +7096,7 @@ static inline bool regime_translation_disabled(CPUARMState *env, ARMMMUIdx mmu_idx) { if (arm_feature(env, ARM_FEATURE_M)) { - switch (env->v7m.mpu_ctrl & + switch (env->v7m.mpu_ctrl[regime_is_secure(env, mmu_idx)] & (R_V7M_MPU_CTRL_ENABLE_MASK | R_V7M_MPU_CTRL_HFNMIENA_MASK)) { case R_V7M_MPU_CTRL_ENABLE_MASK: /* Enabled, but not for HardFault and NMI */ @@ -8256,7 +8256,8 @@ static bool pmsav7_use_background_region(ARMCPU *cpu, } if (arm_feature(env, ARM_FEATURE_M)) { - return env->v7m.mpu_ctrl & R_V7M_MPU_CTRL_PRIVDEFENA_MASK; + return env->v7m.mpu_ctrl[regime_is_secure(env, mmu_idx)] + & R_V7M_MPU_CTRL_PRIVDEFENA_MASK; } else { return regime_sctlr(env, mmu_idx) & SCTLR_BR; } diff --git a/target/arm/machine.c b/target/arm/machine.c index 6941e35..5cc95e8 100644 --- a/target/arm/machine.c +++ b/target/arm/machine.c @@ -123,7 +123,7 @@ static const VMStateDescription vmstate_m = { VMSTATE_UINT32(env.v7m.dfsr, ARMCPU), VMSTATE_UINT32(env.v7m.mmfar, ARMCPU), VMSTATE_UINT32(env.v7m.bfar, ARMCPU), - VMSTATE_UINT32(env.v7m.mpu_ctrl, ARMCPU), + VMSTATE_UINT32(env.v7m.mpu_ctrl[M_REG_NS], ARMCPU), VMSTATE_INT32(env.v7m.exception, ARMCPU), VMSTATE_END_OF_LIST() }, @@ -270,6 +270,7 @@ static const VMStateDescription vmstate_m_security = { 0, vmstate_info_uint32, uint32_t), VMSTATE_UINT32(env.pmsav7.rnr[M_REG_S], ARMCPU), VMSTATE_VALIDATE("secure MPU_RNR is valid", s_rnr_vmstate_validate), + VMSTATE_UINT32(env.v7m.mpu_ctrl[M_REG_S], ARMCPU), VMSTATE_END_OF_LIST() } }; -- 2.7.4 From MAILER-DAEMON Tue Aug 22 11:09:18 2017 Received: from list by lists.gnu.org with archive (Exim 4.71) id 1dkAnu-0006ai-DJ for mharc-qemu-arm@gnu.org; Tue, 22 Aug 2017 11:09:18 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:53340) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dkAno-0006PU-7K for qemu-arm@nongnu.org; Tue, 22 Aug 2017 11:09:15 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dkAnm-0003Cs-QA for qemu-arm@nongnu.org; Tue, 22 Aug 2017 11:09:12 -0400 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:36966) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1dkAnm-00039F-HW; Tue, 22 Aug 2017 11:09:10 -0400 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1dkAna-0004e0-Gg; Tue, 22 Aug 2017 16:08:58 +0100 From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: patches@linaro.org Date: Tue, 22 Aug 2017 16:08:41 +0100 Message-Id: <1503414539-28762-3-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1503414539-28762-1-git-send-email-peter.maydell@linaro.org> References: <1503414539-28762-1-git-send-email-peter.maydell@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-arm] [PATCH 02/20] target/arm: Implement new PMSAv8 behaviour X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 22 Aug 2017 15:09:16 -0000 Implement the behavioural side of the new PMSAv8 specification. Signed-off-by: Peter Maydell --- target/arm/helper.c | 111 +++++++++++++++++++++++++++++++++++++++++++++++++++- 1 file changed, 110 insertions(+), 1 deletion(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 7920153..887490a 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -8416,6 +8416,111 @@ static bool get_phys_addr_pmsav7(CPUARMState *env, uint32_t address, return !(*prot & (1 << access_type)); } +static bool get_phys_addr_pmsav8(CPUARMState *env, uint32_t address, + MMUAccessType access_type, ARMMMUIdx mmu_idx, + hwaddr *phys_ptr, int *prot, uint32_t *fsr) +{ + ARMCPU *cpu = arm_env_get_cpu(env); + bool is_user = regime_is_user(env, mmu_idx); + int n; + int matchregion = -1; + bool hit = false; + + *phys_ptr = address; + *prot = 0; + + /* Unlike the ARM ARM pseudocode, we don't need to check whether this + * was an exception vector read from the vector table (which is always + * done using the default system address map), because those accesses + * are done in arm_v7m_load_vector(), which always does a direct + * read using address_space_ldl(), rather than going via this function. + */ + if (regime_translation_disabled(env, mmu_idx)) { /* MPU disabled */ + hit = true; + } else if (m_is_ppb_region(env, address)) { + hit = true; + } else if (pmsav7_use_background_region(cpu, mmu_idx, is_user)) { + hit = true; + } else { + for (n = (int)cpu->pmsav7_dregion - 1; n >= 0; n--) { + /* region search */ + /* Note that the base address is bits [31:5] from the register + * with bits [4:0] all zeroes, but the limit address is bits + * [31:5] from the register with bits [4:0] all ones. + */ + uint32_t base = env->pmsav8.rbar[n] & ~0x1f; + uint32_t limit = env->pmsav8.rlar[n] | 0x1f; + + if (!(env->pmsav8.rlar[n] & 0x1)) { + /* Region disabled */ + continue; + } + + if (address < base || address > limit) { + continue; + } + + if (hit) { + /* Multiple regions match -- always a failure (unlike + * PMSAv7 where highest-numbered-region wins) + */ + *fsr = 0x00d; /* permission fault */ + return true; + } + + matchregion = n; + hit = true; + + if (base & ~TARGET_PAGE_MASK) { + qemu_log_mask(LOG_UNIMP, + "MPU_RBAR[%d]: No support for MPU region base" + "address of 0x%" PRIx32 ". Minimum alignment is " + "%d\n", + n, base, TARGET_PAGE_BITS); + continue; + } + if ((limit + 1) & ~TARGET_PAGE_MASK) { + qemu_log_mask(LOG_UNIMP, + "MPU_RBAR[%d]: No support for MPU region limit" + "address of 0x%" PRIx32 ". Minimum alignment is " + "%d\n", + n, limit, TARGET_PAGE_BITS); + continue; + } + } + } + + if (!hit) { + /* background fault */ + *fsr = 0; + return true; + } + + if (matchregion == -1) { + /* hit using the background region */ + get_phys_addr_pmsav7_default(env, mmu_idx, address, prot); + } else { + uint32_t ap = extract32(env->pmsav8.rbar[matchregion], 1, 2); + uint32_t xn = extract32(env->pmsav8.rbar[matchregion], 0, 1); + + if (m_is_system_region(env, address)) { + /* System space is always execute never */ + xn = 1; + } + + *prot = simple_ap_to_rw_prot(env, mmu_idx, ap); + if (*prot && !xn) { + *prot |= PAGE_EXEC; + } + /* We don't need to look the attribute up in the MAIR0/MAIR1 + * registers because that only tells us about cacheability. + */ + } + + *fsr = 0x00d; /* Permission fault */ + return !(*prot & (1 << access_type)); +} + static bool get_phys_addr_pmsav5(CPUARMState *env, uint32_t address, MMUAccessType access_type, ARMMMUIdx mmu_idx, hwaddr *phys_ptr, int *prot, uint32_t *fsr) @@ -8585,7 +8690,11 @@ static bool get_phys_addr(CPUARMState *env, target_ulong address, bool ret; *page_size = TARGET_PAGE_SIZE; - if (arm_feature(env, ARM_FEATURE_V7)) { + if (arm_feature(env, ARM_FEATURE_V8)) { + /* PMSAv8 */ + ret = get_phys_addr_pmsav8(env, address, access_type, mmu_idx, + phys_ptr, prot, fsr); + } else if (arm_feature(env, ARM_FEATURE_V7)) { /* PMSAv7 */ ret = get_phys_addr_pmsav7(env, address, access_type, mmu_idx, phys_ptr, prot, fsr); -- 2.7.4 From MAILER-DAEMON Tue Aug 22 11:09:19 2017 Received: from list by lists.gnu.org with archive (Exim 4.71) id 1dkAnu-0006bM-Qz for mharc-qemu-arm@gnu.org; Tue, 22 Aug 2017 11:09:18 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:53277) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dkAnm-0006Mh-KY for qemu-arm@nongnu.org; Tue, 22 Aug 2017 11:09:12 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dkAnk-0003AL-Q7 for qemu-arm@nongnu.org; Tue, 22 Aug 2017 11:09:10 -0400 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:36962) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1dkAnk-00037y-Hz; Tue, 22 Aug 2017 11:09:08 -0400 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1dkAni-0004in-99; Tue, 22 Aug 2017 16:09:06 +0100 From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: patches@linaro.org Date: Tue, 22 Aug 2017 16:08:51 +0100 Message-Id: <1503414539-28762-13-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1503414539-28762-1-git-send-email-peter.maydell@linaro.org> References: <1503414539-28762-1-git-send-email-peter.maydell@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-arm] [PATCH 12/20] target/arm: Make MPU_MAIR0, MPU_MAIR1 registers banked for v8M X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 22 Aug 2017 15:09:12 -0000 Make the MPU registers MPU_MAIR0 and MPU_MAIR1 banked if v8M security extensions are enabled. Signed-off-by: Peter Maydell --- target/arm/cpu.h | 4 ++-- hw/intc/armv7m_nvic.c | 8 ++++---- target/arm/cpu.c | 4 ++-- target/arm/machine.c | 6 ++++-- 4 files changed, 12 insertions(+), 10 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index d0b0936..2f59828 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -545,8 +545,8 @@ typedef struct CPUARMState { */ uint32_t *rbar; uint32_t *rlar; - uint32_t mair0; - uint32_t mair1; + uint32_t mair0[2]; + uint32_t mair1[2]; } pmsav8; void *nvic; diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c index 3a1f02d..e98eb95 100644 --- a/hw/intc/armv7m_nvic.c +++ b/hw/intc/armv7m_nvic.c @@ -604,12 +604,12 @@ static uint32_t nvic_readl(NVICState *s, uint32_t offset, MemTxAttrs attrs) if (!arm_feature(&cpu->env, ARM_FEATURE_V8)) { goto bad_offset; } - return cpu->env.pmsav8.mair0; + return cpu->env.pmsav8.mair0[attrs.secure]; case 0xdc4: /* MPU_MAIR1 */ if (!arm_feature(&cpu->env, ARM_FEATURE_V8)) { goto bad_offset; } - return cpu->env.pmsav8.mair1; + return cpu->env.pmsav8.mair1[attrs.secure]; default: bad_offset: qemu_log_mask(LOG_GUEST_ERROR, "NVIC: Bad read offset 0x%x\n", offset); @@ -826,7 +826,7 @@ static void nvic_writel(NVICState *s, uint32_t offset, uint32_t value, } if (cpu->pmsav7_dregion) { /* Register is RES0 if no MPU regions are implemented */ - cpu->env.pmsav8.mair0 = value; + cpu->env.pmsav8.mair0[attrs.secure] = value; } /* We don't need to do anything else because memory attributes * only affect cacheability, and we don't implement caching. @@ -838,7 +838,7 @@ static void nvic_writel(NVICState *s, uint32_t offset, uint32_t value, } if (cpu->pmsav7_dregion) { /* Register is RES0 if no MPU regions are implemented */ - cpu->env.pmsav8.mair1 = value; + cpu->env.pmsav8.mair1[attrs.secure] = value; } /* We don't need to do anything else because memory attributes * only affect cacheability, and we don't implement caching. diff --git a/target/arm/cpu.c b/target/arm/cpu.c index ae866be..ae8af19 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -249,8 +249,8 @@ static void arm_cpu_reset(CPUState *s) } } env->pmsav7.rnr = 0; - env->pmsav8.mair0 = 0; - env->pmsav8.mair1 = 0; + memset(env->pmsav8.mair0, 0, sizeof(env->pmsav8.mair0)); + memset(env->pmsav8.mair1, 0, sizeof(env->pmsav8.mair1)); } set_flush_to_zero(1, &env->vfp.standard_fp_status); diff --git a/target/arm/machine.c b/target/arm/machine.c index cd6b6af..414a879 100644 --- a/target/arm/machine.c +++ b/target/arm/machine.c @@ -229,8 +229,8 @@ static const VMStateDescription vmstate_pmsav8 = { vmstate_info_uint32, uint32_t), VMSTATE_VARRAY_UINT32(env.pmsav8.rlar, ARMCPU, pmsav7_dregion, 0, vmstate_info_uint32, uint32_t), - VMSTATE_UINT32(env.pmsav8.mair0, ARMCPU), - VMSTATE_UINT32(env.pmsav8.mair1, ARMCPU), + VMSTATE_UINT32(env.pmsav8.mair0[M_REG_NS], ARMCPU), + VMSTATE_UINT32(env.pmsav8.mair1[M_REG_NS], ARMCPU), VMSTATE_END_OF_LIST() } }; @@ -255,6 +255,8 @@ static const VMStateDescription vmstate_m_security = { VMSTATE_UINT32(env.v7m.faultmask[M_REG_S], ARMCPU), VMSTATE_UINT32(env.v7m.control[M_REG_S], ARMCPU), VMSTATE_UINT32(env.v7m.vecbase[M_REG_S], ARMCPU), + VMSTATE_UINT32(env.pmsav8.mair0[M_REG_S], ARMCPU), + VMSTATE_UINT32(env.pmsav8.mair1[M_REG_S], ARMCPU), VMSTATE_END_OF_LIST() } }; -- 2.7.4 From MAILER-DAEMON Tue Aug 22 11:09:19 2017 Received: from list by lists.gnu.org with archive (Exim 4.71) id 1dkAnv-0006bf-0t for mharc-qemu-arm@gnu.org; Tue, 22 Aug 2017 11:09:19 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:53300) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dkAnn-0006N9-66 for qemu-arm@nongnu.org; Tue, 22 Aug 2017 11:09:12 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dkAni-00038k-UC for qemu-arm@nongnu.org; Tue, 22 Aug 2017 11:09:11 -0400 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:36936) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1dkAni-00031e-Lm; Tue, 22 Aug 2017 11:09:06 -0400 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1dkAng-0004ho-IY; Tue, 22 Aug 2017 16:09:04 +0100 From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: patches@linaro.org Date: Tue, 22 Aug 2017 16:08:49 +0100 Message-Id: <1503414539-28762-11-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1503414539-28762-1-git-send-email-peter.maydell@linaro.org> References: <1503414539-28762-1-git-send-email-peter.maydell@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-arm] [PATCH 10/20] nvic: Add NS alias SCS region X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 22 Aug 2017 15:09:13 -0000 For v8M the range 0xe002e000..0xe002efff is an alias region which for secure accesses behaves like a NonSecure access to the main SCS region. (For nonsecure accesses including when the security extension is not implemented, it is RAZ/WI.) Signed-off-by: Peter Maydell --- include/hw/intc/armv7m_nvic.h | 1 + hw/intc/armv7m_nvic.c | 66 ++++++++++++++++++++++++++++++++++++++++++- 2 files changed, 66 insertions(+), 1 deletion(-) diff --git a/include/hw/intc/armv7m_nvic.h b/include/hw/intc/armv7m_nvic.h index 1d145fb..1a4cce7 100644 --- a/include/hw/intc/armv7m_nvic.h +++ b/include/hw/intc/armv7m_nvic.h @@ -50,6 +50,7 @@ typedef struct NVICState { int exception_prio; /* group prio of the highest prio active exception */ MemoryRegion sysregmem; + MemoryRegion sysreg_ns_mem; MemoryRegion container; uint32_t num_irq; diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c index babdc3b..2b0b328 100644 --- a/hw/intc/armv7m_nvic.c +++ b/hw/intc/armv7m_nvic.c @@ -1040,6 +1040,47 @@ static const MemoryRegionOps nvic_sysreg_ops = { .endianness = DEVICE_NATIVE_ENDIAN, }; +static MemTxResult nvic_sysreg_ns_write(void *opaque, hwaddr addr, + uint64_t value, unsigned size, + MemTxAttrs attrs) +{ + if (attrs.secure) { + /* S accesses to the alias act like NS accesses to the real region */ + attrs.secure = 0; + return nvic_sysreg_write(opaque, addr, value, size, attrs); + } else { + /* NS attrs are RAZ/WI for privileged, and BusFault for user */ + if (attrs.user) { + return MEMTX_ERROR; + } + return MEMTX_OK; + } +} + +static MemTxResult nvic_sysreg_ns_read(void *opaque, hwaddr addr, + uint64_t *data, unsigned size, + MemTxAttrs attrs) +{ + if (attrs.secure) { + /* S accesses to the alias act like NS accesses to the real region */ + attrs.secure = 0; + return nvic_sysreg_read(opaque, addr, data, size, attrs); + } else { + /* NS attrs are RAZ/WI for privileged, and BusFault for user */ + if (attrs.user) { + return MEMTX_ERROR; + } + *data = 0; + return MEMTX_OK; + } +} + +static const MemoryRegionOps nvic_sysreg_ns_ops = { + .read_with_attrs = nvic_sysreg_ns_read, + .write_with_attrs = nvic_sysreg_ns_write, + .endianness = DEVICE_NATIVE_ENDIAN, +}; + static int nvic_post_load(void *opaque, int version_id) { NVICState *s = opaque; @@ -1141,6 +1182,7 @@ static void armv7m_nvic_realize(DeviceState *dev, Error **errp) NVICState *s = NVIC(dev); SysBusDevice *systick_sbd; Error *err = NULL; + int regionlen; s->cpu = ARM_CPU(qemu_get_cpu(0)); assert(s->cpu); @@ -1173,8 +1215,23 @@ static void armv7m_nvic_realize(DeviceState *dev, Error **errp) * 0xd00..0xd3c - SCS registers * 0xd40..0xeff - Reserved or Not implemented * 0xf00 - STIR + * + * Some registers within this space are banked between security states. + * In v8M there is a second range 0xe002e000..0xe002efff which is the + * NonSecure alias SCS; secure accesses to this behave like NS accesses + * to the main SCS range, and non-secure accesses (including when + * the security extension is not implemented) are RAZ/WI. + * Note that both the main SCS range and the alias range are defined + * to be exempt from memory attribution (R_BLJT) and so the memory + * transaction attribute always matches the current CPU security + * state (attrs.secure == env->v7m.secure). In the nvic_sysreg_ns_ops + * wrappers we change attrs.secure to indicate the NS access; so + * generally code determining which banked register to use should + * use attrs.secure; code determining actual behaviour of the system + * should use env->v7m.secure. */ - memory_region_init(&s->container, OBJECT(s), "nvic", 0x1000); + regionlen = arm_feature(&s->cpu->env, ARM_FEATURE_V8) ? 0x21000 : 0x1000; + memory_region_init(&s->container, OBJECT(s), "nvic", regionlen); /* The system register region goes at the bottom of the priority * stack as it covers the whole page. */ @@ -1185,6 +1242,13 @@ static void armv7m_nvic_realize(DeviceState *dev, Error **errp) sysbus_mmio_get_region(systick_sbd, 0), 1); + if (arm_feature(&s->cpu->env, ARM_FEATURE_V8)) { + memory_region_init_io(&s->sysreg_ns_mem, OBJECT(s), + &nvic_sysreg_ns_ops, s, + "nvic_sysregs_ns", 0x1000); + memory_region_add_subregion(&s->container, 0x20000, &s->sysreg_ns_mem); + } + sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->container); } -- 2.7.4 From MAILER-DAEMON Tue Aug 22 11:09:21 2017 Received: from list by lists.gnu.org with archive (Exim 4.71) id 1dkAnw-0006e9-KF for mharc-qemu-arm@gnu.org; Tue, 22 Aug 2017 11:09:20 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:53377) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dkAnp-0006VO-Dm for qemu-arm@nongnu.org; Tue, 22 Aug 2017 11:09:16 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dkAnn-0003Do-Pv for qemu-arm@nongnu.org; Tue, 22 Aug 2017 11:09:13 -0400 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:36978) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1dkAnn-0003CS-Er; Tue, 22 Aug 2017 11:09:11 -0400 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1dkAnm-0004l3-5h; Tue, 22 Aug 2017 16:09:10 +0100 From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: patches@linaro.org Date: Tue, 22 Aug 2017 16:08:56 +0100 Message-Id: <1503414539-28762-18-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1503414539-28762-1-git-send-email-peter.maydell@linaro.org> References: <1503414539-28762-1-git-send-email-peter.maydell@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-arm] [PATCH 17/20] target/arm: Make MMFAR banked for v8M X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 22 Aug 2017 15:09:16 -0000 Make the MMFAR register banked if v8M security extensions are enabled. Signed-off-by: Peter Maydell --- target/arm/cpu.h | 2 +- hw/intc/armv7m_nvic.c | 4 ++-- target/arm/helper.c | 4 ++-- target/arm/machine.c | 3 ++- 4 files changed, 7 insertions(+), 6 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 25ebf9e..21c68d7 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -427,7 +427,7 @@ typedef struct CPUARMState { uint32_t cfsr; /* Configurable Fault Status */ uint32_t hfsr; /* HardFault Status */ uint32_t dfsr; /* Debug Fault Status Register */ - uint32_t mmfar; /* MemManage Fault Address */ + uint32_t mmfar[2]; /* MemManage Fault Address */ uint32_t bfar; /* BusFault Address */ unsigned mpu_ctrl[2]; /* MPU_CTRL */ int exception; diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c index f071649..99b62ac 100644 --- a/hw/intc/armv7m_nvic.c +++ b/hw/intc/armv7m_nvic.c @@ -506,7 +506,7 @@ static uint32_t nvic_readl(NVICState *s, uint32_t offset, MemTxAttrs attrs) case 0xd30: /* Debug Fault Status. */ return cpu->env.v7m.dfsr; case 0xd34: /* MMFAR MemManage Fault Address */ - return cpu->env.v7m.mmfar; + return cpu->env.v7m.mmfar[attrs.secure]; case 0xd38: /* Bus Fault Address. */ return cpu->env.v7m.bfar; case 0xd3c: /* Aux Fault Status. */ @@ -723,7 +723,7 @@ static void nvic_writel(NVICState *s, uint32_t offset, uint32_t value, cpu->env.v7m.dfsr &= ~value; /* W1C */ break; case 0xd34: /* Mem Manage Address. */ - cpu->env.v7m.mmfar = value; + cpu->env.v7m.mmfar[attrs.secure] = value; return; case 0xd38: /* Bus Fault Address. */ cpu->env.v7m.bfar = value; diff --git a/target/arm/helper.c b/target/arm/helper.c index 28b3d6c..e587e85 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -6380,10 +6380,10 @@ void arm_v7m_cpu_do_interrupt(CPUState *cs) case EXCP_DATA_ABORT: env->v7m.cfsr |= (R_V7M_CFSR_DACCVIOL_MASK | R_V7M_CFSR_MMARVALID_MASK); - env->v7m.mmfar = env->exception.vaddress; + env->v7m.mmfar[env->v7m.secure] = env->exception.vaddress; qemu_log_mask(CPU_LOG_INT, "...with CFSR.DACCVIOL and MMFAR 0x%x\n", - env->v7m.mmfar); + env->v7m.mmfar[env->v7m.secure]); break; } armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_MEM); diff --git a/target/arm/machine.c b/target/arm/machine.c index 4457ec6..5122e58 100644 --- a/target/arm/machine.c +++ b/target/arm/machine.c @@ -121,7 +121,7 @@ static const VMStateDescription vmstate_m = { VMSTATE_UINT32(env.v7m.cfsr, ARMCPU), VMSTATE_UINT32(env.v7m.hfsr, ARMCPU), VMSTATE_UINT32(env.v7m.dfsr, ARMCPU), - VMSTATE_UINT32(env.v7m.mmfar, ARMCPU), + VMSTATE_UINT32(env.v7m.mmfar[M_REG_NS], ARMCPU), VMSTATE_UINT32(env.v7m.bfar, ARMCPU), VMSTATE_UINT32(env.v7m.mpu_ctrl[M_REG_NS], ARMCPU), VMSTATE_INT32(env.v7m.exception, ARMCPU), @@ -272,6 +272,7 @@ static const VMStateDescription vmstate_m_security = { VMSTATE_VALIDATE("secure MPU_RNR is valid", s_rnr_vmstate_validate), VMSTATE_UINT32(env.v7m.mpu_ctrl[M_REG_S], ARMCPU), VMSTATE_UINT32(env.v7m.ccr[M_REG_S], ARMCPU), + VMSTATE_UINT32(env.v7m.mmfar[M_REG_S], ARMCPU), VMSTATE_END_OF_LIST() } }; -- 2.7.4 From MAILER-DAEMON Tue Aug 22 11:09:21 2017 Received: from list by lists.gnu.org with archive (Exim 4.71) id 1dkAnx-0006em-1G for mharc-qemu-arm@gnu.org; Tue, 22 Aug 2017 11:09:21 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:53265) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dkAnl-0006Li-WC for qemu-arm@nongnu.org; Tue, 22 Aug 2017 11:09:11 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dkAnk-0003AV-RC for qemu-arm@nongnu.org; Tue, 22 Aug 2017 11:09:09 -0400 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:36936) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1dkAnk-00031e-KS; Tue, 22 Aug 2017 11:09:08 -0400 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1dkAnd-0004fk-J2; Tue, 22 Aug 2017 16:09:01 +0100 From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: patches@linaro.org Date: Tue, 22 Aug 2017 16:08:45 +0100 Message-Id: <1503414539-28762-7-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1503414539-28762-1-git-send-email-peter.maydell@linaro.org> References: <1503414539-28762-1-git-send-email-peter.maydell@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-arm] [PATCH 06/20] target/arm: Make BASEPRI register banked for v8M X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 22 Aug 2017 15:09:11 -0000 Make the BASEPRI register banked if v8M security extensions are enabled. Note that we do not yet implement the functionality of the new AIRCR.PRIS bit (which allows the effect of the NS copy of BASEPRI to be restricted). Signed-off-by: Peter Maydell --- target/arm/cpu.h | 14 +++++++++++++- hw/intc/armv7m_nvic.c | 4 ++-- target/arm/helper.c | 10 ++++++---- target/arm/machine.c | 3 ++- 4 files changed, 23 insertions(+), 8 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 436ca0d..0c28dfd 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -72,6 +72,18 @@ #define ARMV7M_EXCP_PENDSV 14 #define ARMV7M_EXCP_SYSTICK 15 +/* For M profile, some registers are banked secure vs non-secure; + * these are represented as a 2-element array where the first element + * is the non-secure copy and the second is the secure copy. + * When the CPU does not have implement the security extension then + * only the first element is used. + * This means that the copy for the current security state can be + * accessed via env->registerfield[env->v7m.secure] (whether the security + * extension is implemented or not). + */ +#define M_REG_NS 0 +#define M_REG_S 1 + /* ARM-specific interrupt pending bits. */ #define CPU_INTERRUPT_FIQ CPU_INTERRUPT_TGT_EXT_1 #define CPU_INTERRUPT_VIRQ CPU_INTERRUPT_TGT_EXT_2 @@ -409,7 +421,7 @@ typedef struct CPUARMState { struct { uint32_t other_sp; uint32_t vecbase; - uint32_t basepri; + uint32_t basepri[2]; uint32_t control; uint32_t ccr; /* Configuration and Control */ uint32_t cfsr; /* Configurable Fault Status */ diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c index c0dbbad..2a41e5d 100644 --- a/hw/intc/armv7m_nvic.c +++ b/hw/intc/armv7m_nvic.c @@ -171,8 +171,8 @@ static inline int nvic_exec_prio(NVICState *s) running = -1; } else if (env->v7m.primask) { running = 0; - } else if (env->v7m.basepri > 0) { - running = env->v7m.basepri & nvic_gprio_mask(s); + } else if (env->v7m.basepri[env->v7m.secure] > 0) { + running = env->v7m.basepri[env->v7m.secure] & nvic_gprio_mask(s); } else { running = NVIC_NOEXC_PRIO; /* lower than any possible priority */ } diff --git a/target/arm/helper.c b/target/arm/helper.c index 1debebc..1087f19 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -8838,7 +8838,7 @@ uint32_t HELPER(v7m_mrs)(CPUARMState *env, uint32_t reg) return env->v7m.primask; case 17: /* BASEPRI */ case 18: /* BASEPRI_MAX */ - return env->v7m.basepri; + return env->v7m.basepri[env->v7m.secure]; case 19: /* FAULTMASK */ return env->v7m.faultmask; default: @@ -8898,12 +8898,14 @@ void HELPER(v7m_msr)(CPUARMState *env, uint32_t maskreg, uint32_t val) env->v7m.primask = val & 1; break; case 17: /* BASEPRI */ - env->v7m.basepri = val & 0xff; + env->v7m.basepri[env->v7m.secure] = val & 0xff; break; case 18: /* BASEPRI_MAX */ val &= 0xff; - if (val != 0 && (val < env->v7m.basepri || env->v7m.basepri == 0)) - env->v7m.basepri = val; + if (val != 0 && (val < env->v7m.basepri[env->v7m.secure] + || env->v7m.basepri[env->v7m.secure] == 0)) { + env->v7m.basepri[env->v7m.secure] = val; + } break; case 19: /* FAULTMASK */ env->v7m.faultmask = val & 1; diff --git a/target/arm/machine.c b/target/arm/machine.c index 745adae..8476efd 100644 --- a/target/arm/machine.c +++ b/target/arm/machine.c @@ -115,7 +115,7 @@ static const VMStateDescription vmstate_m = { .needed = m_needed, .fields = (VMStateField[]) { VMSTATE_UINT32(env.v7m.vecbase, ARMCPU), - VMSTATE_UINT32(env.v7m.basepri, ARMCPU), + VMSTATE_UINT32(env.v7m.basepri[M_REG_NS], ARMCPU), VMSTATE_UINT32(env.v7m.control, ARMCPU), VMSTATE_UINT32(env.v7m.ccr, ARMCPU), VMSTATE_UINT32(env.v7m.cfsr, ARMCPU), @@ -250,6 +250,7 @@ static const VMStateDescription vmstate_m_security = { .needed = m_security_needed, .fields = (VMStateField[]) { VMSTATE_UINT32(env.v7m.secure, ARMCPU), + VMSTATE_UINT32(env.v7m.basepri[M_REG_S], ARMCPU), VMSTATE_END_OF_LIST() } }; -- 2.7.4 From MAILER-DAEMON Tue Aug 22 11:09:21 2017 Received: from list by lists.gnu.org with archive (Exim 4.71) id 1dkAnx-0006fe-8C for mharc-qemu-arm@gnu.org; Tue, 22 Aug 2017 11:09:21 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:53359) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dkAno-0006RH-LL for qemu-arm@nongnu.org; Tue, 22 Aug 2017 11:09:15 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dkAni-00038W-O2 for qemu-arm@nongnu.org; Tue, 22 Aug 2017 11:09:12 -0400 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:36962) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1dkAni-00037y-Gd; Tue, 22 Aug 2017 11:09:06 -0400 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1dkAnh-0004i6-H2; Tue, 22 Aug 2017 16:09:05 +0100 From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: patches@linaro.org Date: Tue, 22 Aug 2017 16:08:50 +0100 Message-Id: <1503414539-28762-12-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1503414539-28762-1-git-send-email-peter.maydell@linaro.org> References: <1503414539-28762-1-git-send-email-peter.maydell@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-arm] [PATCH 11/20] target/arm: Make VTOR register banked for v8M X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 22 Aug 2017 15:09:16 -0000 Make the VTOR register banked if v8M security extensions are enabled. Signed-off-by: Peter Maydell --- target/arm/cpu.h | 2 +- hw/intc/armv7m_nvic.c | 13 +++++++------ target/arm/helper.c | 2 +- target/arm/machine.c | 3 ++- 4 files changed, 11 insertions(+), 9 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index e922d1f..d0b0936 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -420,7 +420,7 @@ typedef struct CPUARMState { struct { uint32_t other_sp; - uint32_t vecbase; + uint32_t vecbase[2]; uint32_t basepri[2]; uint32_t control[2]; uint32_t ccr; /* Configuration and Control */ diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c index 2b0b328..3a1f02d 100644 --- a/hw/intc/armv7m_nvic.c +++ b/hw/intc/armv7m_nvic.c @@ -403,7 +403,7 @@ static void set_irq_level(void *opaque, int n, int level) } } -static uint32_t nvic_readl(NVICState *s, uint32_t offset) +static uint32_t nvic_readl(NVICState *s, uint32_t offset, MemTxAttrs attrs) { ARMCPU *cpu = s->cpu; uint32_t val; @@ -441,7 +441,7 @@ static uint32_t nvic_readl(NVICState *s, uint32_t offset) /* ISRPREEMPT not implemented */ return val; case 0xd08: /* Vector Table Offset. */ - return cpu->env.v7m.vecbase; + return cpu->env.v7m.vecbase[attrs.secure]; case 0xd0c: /* Application Interrupt/Reset Control. */ return 0xfa050000 | (s->prigroup << 8); case 0xd10: /* System Control. */ @@ -617,7 +617,8 @@ static uint32_t nvic_readl(NVICState *s, uint32_t offset) } } -static void nvic_writel(NVICState *s, uint32_t offset, uint32_t value) +static void nvic_writel(NVICState *s, uint32_t offset, uint32_t value, + MemTxAttrs attrs) { ARMCPU *cpu = s->cpu; @@ -638,7 +639,7 @@ static void nvic_writel(NVICState *s, uint32_t offset, uint32_t value) } break; case 0xd08: /* Vector Table Offset. */ - cpu->env.v7m.vecbase = value & 0xffffff80; + cpu->env.v7m.vecbase[attrs.secure] = value & 0xffffff80; break; case 0xd0c: /* Application Interrupt/Reset Control. */ if ((value >> 16) == 0x05fa) { @@ -944,7 +945,7 @@ static MemTxResult nvic_sysreg_read(void *opaque, hwaddr addr, break; default: if (size == 4) { - val = nvic_readl(s, offset); + val = nvic_readl(s, offset, attrs); } else { qemu_log_mask(LOG_GUEST_ERROR, "NVIC: Bad read of size %d at offset 0x%x\n", @@ -1025,7 +1026,7 @@ static MemTxResult nvic_sysreg_write(void *opaque, hwaddr addr, return MEMTX_OK; } if (size == 4) { - nvic_writel(s, offset, value); + nvic_writel(s, offset, value, attrs); return MEMTX_OK; } qemu_log_mask(LOG_GUEST_ERROR, diff --git a/target/arm/helper.c b/target/arm/helper.c index 8e74b10..b1bb507 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -6072,7 +6072,7 @@ static uint32_t arm_v7m_load_vector(ARMCPU *cpu) CPUState *cs = CPU(cpu); CPUARMState *env = &cpu->env; MemTxResult result; - hwaddr vec = env->v7m.vecbase + env->v7m.exception * 4; + hwaddr vec = env->v7m.vecbase[env->v7m.secure] + env->v7m.exception * 4; uint32_t addr; addr = address_space_ldl(cs->as, vec, diff --git a/target/arm/machine.c b/target/arm/machine.c index 2cd64c5..cd6b6af 100644 --- a/target/arm/machine.c +++ b/target/arm/machine.c @@ -114,7 +114,7 @@ static const VMStateDescription vmstate_m = { .minimum_version_id = 4, .needed = m_needed, .fields = (VMStateField[]) { - VMSTATE_UINT32(env.v7m.vecbase, ARMCPU), + VMSTATE_UINT32(env.v7m.vecbase[M_REG_NS], ARMCPU), VMSTATE_UINT32(env.v7m.basepri[M_REG_NS], ARMCPU), VMSTATE_UINT32(env.v7m.control[M_REG_NS], ARMCPU), VMSTATE_UINT32(env.v7m.ccr, ARMCPU), @@ -254,6 +254,7 @@ static const VMStateDescription vmstate_m_security = { VMSTATE_UINT32(env.v7m.primask[M_REG_S], ARMCPU), VMSTATE_UINT32(env.v7m.faultmask[M_REG_S], ARMCPU), VMSTATE_UINT32(env.v7m.control[M_REG_S], ARMCPU), + VMSTATE_UINT32(env.v7m.vecbase[M_REG_S], ARMCPU), VMSTATE_END_OF_LIST() } }; -- 2.7.4 From MAILER-DAEMON Tue Aug 22 11:09:23 2017 Received: from list by lists.gnu.org with archive (Exim 4.71) id 1dkAnz-0006hl-FY for mharc-qemu-arm@gnu.org; Tue, 22 Aug 2017 11:09:23 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:53427) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dkAnq-0006Vh-KE for qemu-arm@nongnu.org; Tue, 22 Aug 2017 11:09:17 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dkAno-0003F5-Vn for qemu-arm@nongnu.org; Tue, 22 Aug 2017 11:09:14 -0400 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:36984) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1dkAno-0003E6-OL; Tue, 22 Aug 2017 11:09:12 -0400 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1dkAnn-0004m0-Pn; Tue, 22 Aug 2017 16:09:11 +0100 From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: patches@linaro.org Date: Tue, 22 Aug 2017 16:08:58 +0100 Message-Id: <1503414539-28762-20-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1503414539-28762-1-git-send-email-peter.maydell@linaro.org> References: <1503414539-28762-1-git-send-email-peter.maydell@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-arm] [PATCH 19/20] target/arm: Move regime_is_secure() to target/arm/internals.h X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 22 Aug 2017 15:09:17 -0000 Move the regime_is_secure() utility function to internals.h; we are going to want to call it from translate.c. Signed-off-by: Peter Maydell --- target/arm/internals.h | 26 ++++++++++++++++++++++++++ target/arm/helper.c | 26 -------------------------- 2 files changed, 26 insertions(+), 26 deletions(-) diff --git a/target/arm/internals.h b/target/arm/internals.h index bb06946..eb171b1 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -478,4 +478,30 @@ static inline void arm_call_el_change_hook(ARMCPU *cpu) } } +/* Return true if this address translation regime is secure */ +static inline bool regime_is_secure(CPUARMState *env, ARMMMUIdx mmu_idx) +{ + switch (mmu_idx) { + case ARMMMUIdx_S12NSE0: + case ARMMMUIdx_S12NSE1: + case ARMMMUIdx_S1NSE0: + case ARMMMUIdx_S1NSE1: + case ARMMMUIdx_S1E2: + case ARMMMUIdx_S2NS: + case ARMMMUIdx_MPriv: + case ARMMMUIdx_MNegPri: + case ARMMMUIdx_MUser: + return false; + case ARMMMUIdx_S1E3: + case ARMMMUIdx_S1SE0: + case ARMMMUIdx_S1SE1: + case ARMMMUIdx_MSPriv: + case ARMMMUIdx_MSNegPri: + case ARMMMUIdx_MSUser: + return true; + default: + g_assert_not_reached(); + } +} + #endif diff --git a/target/arm/helper.c b/target/arm/helper.c index 67b3874..b1ae73c 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -7060,32 +7060,6 @@ static inline uint32_t regime_el(CPUARMState *env, ARMMMUIdx mmu_idx) } } -/* Return true if this address translation regime is secure */ -static inline bool regime_is_secure(CPUARMState *env, ARMMMUIdx mmu_idx) -{ - switch (mmu_idx) { - case ARMMMUIdx_S12NSE0: - case ARMMMUIdx_S12NSE1: - case ARMMMUIdx_S1NSE0: - case ARMMMUIdx_S1NSE1: - case ARMMMUIdx_S1E2: - case ARMMMUIdx_S2NS: - case ARMMMUIdx_MPriv: - case ARMMMUIdx_MNegPri: - case ARMMMUIdx_MUser: - return false; - case ARMMMUIdx_S1E3: - case ARMMMUIdx_S1SE0: - case ARMMMUIdx_S1SE1: - case ARMMMUIdx_MSPriv: - case ARMMMUIdx_MSNegPri: - case ARMMMUIdx_MSUser: - return true; - default: - g_assert_not_reached(); - } -} - /* Return the SCTLR value which controls this address translation regime */ static inline uint32_t regime_sctlr(CPUARMState *env, ARMMMUIdx mmu_idx) { -- 2.7.4 From MAILER-DAEMON Tue Aug 22 11:09:24 2017 Received: from list by lists.gnu.org with archive (Exim 4.71) id 1dkAo0-0006j7-9u for mharc-qemu-arm@gnu.org; Tue, 22 Aug 2017 11:09:24 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:53431) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dkAnq-0006Vj-QL for qemu-arm@nongnu.org; Tue, 22 Aug 2017 11:09:18 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dkAnj-00039a-P2 for qemu-arm@nongnu.org; Tue, 22 Aug 2017 11:09:14 -0400 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:36962) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1dkAnj-00037y-HK; Tue, 22 Aug 2017 11:09:07 -0400 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1dkAnf-0004h9-Q5; Tue, 22 Aug 2017 16:09:03 +0100 From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: patches@linaro.org Date: Tue, 22 Aug 2017 16:08:48 +0100 Message-Id: <1503414539-28762-10-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1503414539-28762-1-git-send-email-peter.maydell@linaro.org> References: <1503414539-28762-1-git-send-email-peter.maydell@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-arm] [PATCH 09/20] target/arm: Make CONTROL register banked for v8M X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 22 Aug 2017 15:09:18 -0000 Make the CONTROL register banked if v8M security extensions are enabled. Signed-off-by: Peter Maydell --- target/arm/cpu.h | 5 +++-- target/arm/helper.c | 21 +++++++++++---------- target/arm/machine.c | 3 ++- target/arm/translate.c | 2 +- 4 files changed, 17 insertions(+), 14 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index edd4c9e..e922d1f 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -422,7 +422,7 @@ typedef struct CPUARMState { uint32_t other_sp; uint32_t vecbase; uint32_t basepri[2]; - uint32_t control; + uint32_t control[2]; uint32_t ccr; /* Configuration and Control */ uint32_t cfsr; /* Configurable Fault Status */ uint32_t hfsr; /* HardFault Status */ @@ -1682,7 +1682,8 @@ static inline bool arm_v7m_is_handler_mode(CPUARMState *env) static inline int arm_current_el(CPUARMState *env) { if (arm_feature(env, ARM_FEATURE_M)) { - return arm_v7m_is_handler_mode(env) || !(env->v7m.control & 1); + return arm_v7m_is_handler_mode(env) || + !(env->v7m.control[env->v7m.secure] & 1); } if (is_a64(env)) { diff --git a/target/arm/helper.c b/target/arm/helper.c index b8f3b23..8e74b10 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -6053,14 +6053,15 @@ static uint32_t v7m_pop(CPUARMState *env) static void switch_v7m_sp(CPUARMState *env, bool new_spsel) { uint32_t tmp; - bool old_spsel = env->v7m.control & R_V7M_CONTROL_SPSEL_MASK; + uint32_t old_control = env->v7m.control[env->v7m.secure]; + bool old_spsel = old_control & R_V7M_CONTROL_SPSEL_MASK; if (old_spsel != new_spsel) { tmp = env->v7m.other_sp; env->v7m.other_sp = env->regs[13]; env->regs[13] = tmp; - env->v7m.control = deposit32(env->v7m.control, + env->v7m.control[env->v7m.secure] = deposit32(old_control, R_V7M_CONTROL_SPSEL_SHIFT, R_V7M_CONTROL_SPSEL_LENGTH, new_spsel); } @@ -6414,7 +6415,7 @@ void arm_v7m_cpu_do_interrupt(CPUState *cs) } lr = 0xfffffff1; - if (env->v7m.control & R_V7M_CONTROL_SPSEL_MASK) { + if (env->v7m.control[env->v7m.secure] & R_V7M_CONTROL_SPSEL_MASK) { lr |= 4; } if (!arm_v7m_is_handler_mode(env)) { @@ -8832,7 +8833,7 @@ uint32_t HELPER(v7m_mrs)(CPUARMState *env, uint32_t reg) return xpsr_read(env) & mask; break; case 20: /* CONTROL */ - return env->v7m.control; + return env->v7m.control[env->v7m.secure]; } if (el == 0) { @@ -8841,10 +8842,10 @@ uint32_t HELPER(v7m_mrs)(CPUARMState *env, uint32_t reg) switch (reg) { case 8: /* MSP */ - return (env->v7m.control & R_V7M_CONTROL_SPSEL_MASK) ? + return (env->v7m.control[env->v7m.secure] & R_V7M_CONTROL_SPSEL_MASK) ? env->v7m.other_sp : env->regs[13]; case 9: /* PSP */ - return (env->v7m.control & R_V7M_CONTROL_SPSEL_MASK) ? + return (env->v7m.control[env->v7m.secure] & R_V7M_CONTROL_SPSEL_MASK) ? env->regs[13] : env->v7m.other_sp; case 16: /* PRIMASK */ return env->v7m.primask[env->v7m.secure]; @@ -8893,14 +8894,14 @@ void HELPER(v7m_msr)(CPUARMState *env, uint32_t maskreg, uint32_t val) } break; case 8: /* MSP */ - if (env->v7m.control & R_V7M_CONTROL_SPSEL_MASK) { + if (env->v7m.control[env->v7m.secure] & R_V7M_CONTROL_SPSEL_MASK) { env->v7m.other_sp = val; } else { env->regs[13] = val; } break; case 9: /* PSP */ - if (env->v7m.control & R_V7M_CONTROL_SPSEL_MASK) { + if (env->v7m.control[env->v7m.secure] & R_V7M_CONTROL_SPSEL_MASK) { env->regs[13] = val; } else { env->v7m.other_sp = val; @@ -8931,8 +8932,8 @@ void HELPER(v7m_msr)(CPUARMState *env, uint32_t maskreg, uint32_t val) if (!arm_v7m_is_handler_mode(env)) { switch_v7m_sp(env, (val & R_V7M_CONTROL_SPSEL_MASK) != 0); } - env->v7m.control &= ~R_V7M_CONTROL_NPRIV_MASK; - env->v7m.control |= val & R_V7M_CONTROL_NPRIV_MASK; + env->v7m.control[env->v7m.secure] &= ~R_V7M_CONTROL_NPRIV_MASK; + env->v7m.control[env->v7m.secure] |= val & R_V7M_CONTROL_NPRIV_MASK; break; default: qemu_log_mask(LOG_GUEST_ERROR, "Attempt to write unknown special" diff --git a/target/arm/machine.c b/target/arm/machine.c index bd7aba1..2cd64c5 100644 --- a/target/arm/machine.c +++ b/target/arm/machine.c @@ -116,7 +116,7 @@ static const VMStateDescription vmstate_m = { .fields = (VMStateField[]) { VMSTATE_UINT32(env.v7m.vecbase, ARMCPU), VMSTATE_UINT32(env.v7m.basepri[M_REG_NS], ARMCPU), - VMSTATE_UINT32(env.v7m.control, ARMCPU), + VMSTATE_UINT32(env.v7m.control[M_REG_NS], ARMCPU), VMSTATE_UINT32(env.v7m.ccr, ARMCPU), VMSTATE_UINT32(env.v7m.cfsr, ARMCPU), VMSTATE_UINT32(env.v7m.hfsr, ARMCPU), @@ -253,6 +253,7 @@ static const VMStateDescription vmstate_m_security = { VMSTATE_UINT32(env.v7m.basepri[M_REG_S], ARMCPU), VMSTATE_UINT32(env.v7m.primask[M_REG_S], ARMCPU), VMSTATE_UINT32(env.v7m.faultmask[M_REG_S], ARMCPU), + VMSTATE_UINT32(env.v7m.control[M_REG_S], ARMCPU), VMSTATE_END_OF_LIST() } }; diff --git a/target/arm/translate.c b/target/arm/translate.c index dea0a6f..6aa2d7c 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -12241,7 +12241,7 @@ void arm_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf, if (xpsr & XPSR_EXCP) { mode = "handler"; } else { - if (env->v7m.control & R_V7M_CONTROL_NPRIV_MASK) { + if (env->v7m.control[env->v7m.secure] & R_V7M_CONTROL_NPRIV_MASK) { mode = "unpriv-thread"; } else { mode = "priv-thread"; -- 2.7.4 From MAILER-DAEMON Tue Aug 22 11:09:25 2017 Received: from list by lists.gnu.org with archive (Exim 4.71) id 1dkAo0-0006k1-SV for mharc-qemu-arm@gnu.org; Tue, 22 Aug 2017 11:09:24 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:53416) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dkAnq-0006Vd-Ch for qemu-arm@nongnu.org; Tue, 22 Aug 2017 11:09:18 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dkAno-0003E1-0q for qemu-arm@nongnu.org; Tue, 22 Aug 2017 11:09:14 -0400 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:36962) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1dkAnn-00037y-Mj; Tue, 22 Aug 2017 11:09:11 -0400 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1dkAnl-0004kK-Cw; Tue, 22 Aug 2017 16:09:09 +0100 From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: patches@linaro.org Date: Tue, 22 Aug 2017 16:08:55 +0100 Message-Id: <1503414539-28762-17-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1503414539-28762-1-git-send-email-peter.maydell@linaro.org> References: <1503414539-28762-1-git-send-email-peter.maydell@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-arm] [PATCH 16/20] target/arm: Make CCR register banked for v8M X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 22 Aug 2017 15:09:18 -0000 Make the CCR register banked if v8M security extensions are enabled. This is slightly more complicated than the other "add banking" patches because there is one bit in the register which is not banked. We keep the live data in the NS copy of the register, and adjust it on register reads and writes. (Since we don't currently implement the behaviour that the bit controls, there is nowhere else that needs to care.) This patch includes the enforcement of the bits which are newly RES1 in ARMv8M. Signed-off-by: Peter Maydell --- target/arm/cpu.h | 2 +- hw/intc/armv7m_nvic.c | 36 ++++++++++++++++++++++++++++++------ target/arm/cpu.c | 12 +++++++++--- target/arm/helper.c | 5 +++-- target/arm/machine.c | 3 ++- 5 files changed, 45 insertions(+), 13 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 78cd3f0..25ebf9e 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -423,7 +423,7 @@ typedef struct CPUARMState { uint32_t vecbase[2]; uint32_t basepri[2]; uint32_t control[2]; - uint32_t ccr; /* Configuration and Control */ + uint32_t ccr[2]; /* Configuration and Control */ uint32_t cfsr; /* Configurable Fault Status */ uint32_t hfsr; /* HardFault Status */ uint32_t dfsr; /* Debug Fault Status Register */ diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c index a4c298f..f071649 100644 --- a/hw/intc/armv7m_nvic.c +++ b/hw/intc/armv7m_nvic.c @@ -448,7 +448,12 @@ static uint32_t nvic_readl(NVICState *s, uint32_t offset, MemTxAttrs attrs) /* TODO: Implement SLEEPONEXIT. */ return 0; case 0xd14: /* Configuration Control. */ - return cpu->env.v7m.ccr; + /* The BFHFNMIGN bit is the only non-banked bit; we + * keep it in the non-secure copy of the register. + */ + val = cpu->env.v7m.ccr[attrs.secure]; + val |= cpu->env.v7m.ccr[M_REG_NS] & R_V7M_CCR_BFHFNMIGN_MASK; + return val; case 0xd24: /* System Handler Status. */ val = 0; if (s->vectors[ARMV7M_EXCP_MEM].active) { @@ -673,7 +678,23 @@ static void nvic_writel(NVICState *s, uint32_t offset, uint32_t value, R_V7M_CCR_USERSETMPEND_MASK | R_V7M_CCR_NONBASETHRDENA_MASK); - cpu->env.v7m.ccr = value; + if (arm_feature(&cpu->env, ARM_FEATURE_V8)) { + /* v8M makes NONBASETHRDENA and STKALIGN be RES1 */ + value |= R_V7M_CCR_NONBASETHRDENA_MASK + | R_V7M_CCR_STKALIGN_MASK; + } + if (attrs.secure) { + /* the BFHFNMIGN bit is not banked; keep that in the NS copy */ + int new_bfhnmign = !!(value & R_V7M_CCR_BFHFNMIGN_MASK); + + cpu->env.v7m.ccr[M_REG_NS] = deposit32(cpu->env.v7m.ccr[M_REG_NS], + R_V7M_CCR_BFHFNMIGN_SHIFT, + R_V7M_CCR_BFHFNMIGN_LENGTH, + new_bfhnmign); + value &= ~R_V7M_CCR_BFHFNMIGN_MASK; + } + + cpu->env.v7m.ccr[attrs.secure] = value; break; case 0xd24: /* System Handler Control. */ s->vectors[ARMV7M_EXCP_MEM].active = (value & (1 << 0)) != 0; @@ -860,12 +881,15 @@ static void nvic_writel(NVICState *s, uint32_t offset, uint32_t value, } } -static bool nvic_user_access_ok(NVICState *s, hwaddr offset) +static bool nvic_user_access_ok(NVICState *s, hwaddr offset, MemTxAttrs attrs) { /* Return true if unprivileged access to this register is permitted. */ switch (offset) { case 0xf00: /* STIR: accessible only if CCR.USERSETMPEND permits */ - return s->cpu->env.v7m.ccr & R_V7M_CCR_USERSETMPEND_MASK; + /* For access via STIR_NS it is the NS CCR.USERSETMPEND that + * controls access even though the CPU is in Secure state (I_QDKX). + */ + return s->cpu->env.v7m.ccr[attrs.secure] & R_V7M_CCR_USERSETMPEND_MASK; default: /* All other user accesses cause a BusFault unconditionally */ return false; @@ -881,7 +905,7 @@ static MemTxResult nvic_sysreg_read(void *opaque, hwaddr addr, unsigned i, startvec, end; uint32_t val; - if (attrs.user && !nvic_user_access_ok(s, addr)) { + if (attrs.user && !nvic_user_access_ok(s, addr, attrs)) { /* Generate BusFault for unprivileged accesses */ return MEMTX_ERROR; } @@ -971,7 +995,7 @@ static MemTxResult nvic_sysreg_write(void *opaque, hwaddr addr, trace_nvic_sysreg_write(addr, value, size); - if (attrs.user && !nvic_user_access_ok(s, addr)) { + if (attrs.user && !nvic_user_access_ok(s, addr, attrs)) { /* Generate BusFault for unprivileged accesses */ return MEMTX_ERROR; } diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 11038b8..3c2ff11 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -189,11 +189,17 @@ static void arm_cpu_reset(CPUState *s) env->v7m.secure = true; } - /* The reset value of this bit is IMPDEF, but ARM recommends + /* In v7M the reset value of this bit is IMPDEF, but ARM recommends * that it resets to 1, so QEMU always does that rather than making - * it dependent on CPU model. + * it dependent on CPU model. In v8M it is RES1. */ - env->v7m.ccr = R_V7M_CCR_STKALIGN_MASK; + env->v7m.ccr[M_REG_NS] = R_V7M_CCR_STKALIGN_MASK; + env->v7m.ccr[M_REG_S] = R_V7M_CCR_STKALIGN_MASK; + if (arm_feature(env, ARM_FEATURE_V8)) { + /* in v8M the NONBASETHRDENA bit [0] is RES1 */ + env->v7m.ccr[M_REG_NS] |= R_V7M_CCR_NONBASETHRDENA_MASK; + env->v7m.ccr[M_REG_S] |= R_V7M_CCR_NONBASETHRDENA_MASK; + } /* Unlike A/R profile, M profile defines the reset LR value */ env->regs[14] = 0xffffffff; diff --git a/target/arm/helper.c b/target/arm/helper.c index 4a2148c..28b3d6c 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -6118,7 +6118,8 @@ static void v7m_push_stack(ARMCPU *cpu) uint32_t xpsr = xpsr_read(env); /* Align stack pointer if the guest wants that */ - if ((env->regs[13] & 4) && (env->v7m.ccr & R_V7M_CCR_STKALIGN_MASK)) { + if ((env->regs[13] & 4) && + (env->v7m.ccr[env->v7m.secure] & R_V7M_CCR_STKALIGN_MASK)) { env->regs[13] -= 4; xpsr |= XPSR_SPREALIGN; } @@ -6216,7 +6217,7 @@ static void do_v7m_exception_exit(ARMCPU *cpu) /* fall through */ case 9: /* Return to Thread using Main stack */ if (!rettobase && - !(env->v7m.ccr & R_V7M_CCR_NONBASETHRDENA_MASK)) { + !(env->v7m.ccr[env->v7m.secure] & R_V7M_CCR_NONBASETHRDENA_MASK)) { ufault = true; } break; diff --git a/target/arm/machine.c b/target/arm/machine.c index 5cc95e8..4457ec6 100644 --- a/target/arm/machine.c +++ b/target/arm/machine.c @@ -117,7 +117,7 @@ static const VMStateDescription vmstate_m = { VMSTATE_UINT32(env.v7m.vecbase[M_REG_NS], ARMCPU), VMSTATE_UINT32(env.v7m.basepri[M_REG_NS], ARMCPU), VMSTATE_UINT32(env.v7m.control[M_REG_NS], ARMCPU), - VMSTATE_UINT32(env.v7m.ccr, ARMCPU), + VMSTATE_UINT32(env.v7m.ccr[M_REG_NS], ARMCPU), VMSTATE_UINT32(env.v7m.cfsr, ARMCPU), VMSTATE_UINT32(env.v7m.hfsr, ARMCPU), VMSTATE_UINT32(env.v7m.dfsr, ARMCPU), @@ -271,6 +271,7 @@ static const VMStateDescription vmstate_m_security = { VMSTATE_UINT32(env.pmsav7.rnr[M_REG_S], ARMCPU), VMSTATE_VALIDATE("secure MPU_RNR is valid", s_rnr_vmstate_validate), VMSTATE_UINT32(env.v7m.mpu_ctrl[M_REG_S], ARMCPU), + VMSTATE_UINT32(env.v7m.ccr[M_REG_S], ARMCPU), VMSTATE_END_OF_LIST() } }; -- 2.7.4 From MAILER-DAEMON Tue Aug 22 11:09:27 2017 Received: from list by lists.gnu.org with archive (Exim 4.71) id 1dkAo3-0006n1-3n for mharc-qemu-arm@gnu.org; Tue, 22 Aug 2017 11:09:27 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:53413) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dkAnq-0006Vc-BC for qemu-arm@nongnu.org; Tue, 22 Aug 2017 11:09:21 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dkAnn-0003D6-4B for qemu-arm@nongnu.org; Tue, 22 Aug 2017 11:09:14 -0400 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:36962) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1dkAnm-00037y-IE; Tue, 22 Aug 2017 11:09:10 -0400 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1dkAnZ-0004dj-QG; Tue, 22 Aug 2017 16:08:57 +0100 From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: patches@linaro.org Date: Tue, 22 Aug 2017 16:08:40 +0100 Message-Id: <1503414539-28762-2-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1503414539-28762-1-git-send-email-peter.maydell@linaro.org> References: <1503414539-28762-1-git-send-email-peter.maydell@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-arm] [PATCH 01/20] target/arm: Implement ARMv8M's PMSAv8 registers X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 22 Aug 2017 15:09:21 -0000 As part of ARMv8M, we need to add support for the PMSAv8 MPU architecture. PMSAv8 differs from PMSAv7 both in register/data layout (for instance using base and limit registers rather than base and size) and also in behaviour (for example it does not have subregions); rather than trying to wedge it into the existing PMSAv7 code and data structures, we define separate ones. This commit adds the data structures which hold the state for a PMSAv8 MPU and the register interface to it. The implementation of the MPU behaviour will be added in a subsequent commit. Signed-off-by: Peter Maydell --- target/arm/cpu.h | 13 ++++++ hw/intc/armv7m_nvic.c | 122 ++++++++++++++++++++++++++++++++++++++++++++++---- target/arm/cpu.c | 36 ++++++++++----- target/arm/machine.c | 28 +++++++++++- 4 files changed, 179 insertions(+), 20 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index fe6edb7..b6bb78a 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -522,6 +522,19 @@ typedef struct CPUARMState { uint32_t rnr; } pmsav7; + /* PMSAv8 MPU */ + struct { + /* The PMSAv8 implementation also shares some PMSAv7 config + * and state: + * pmsav7.rnr (region number register) + * pmsav7_dregion (number of configured regions) + */ + uint32_t *rbar; + uint32_t *rlar; + uint32_t mair0; + uint32_t mair1; + } pmsav8; + void *nvic; const struct arm_boot_info *boot_info; /* Store GICv3CPUState to access from this struct */ diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c index bbfe2d5..c0dbbad 100644 --- a/hw/intc/armv7m_nvic.c +++ b/hw/intc/armv7m_nvic.c @@ -544,25 +544,67 @@ static uint32_t nvic_readl(NVICState *s, uint32_t offset) { int region = cpu->env.pmsav7.rnr; + if (arm_feature(&cpu->env, ARM_FEATURE_V8)) { + /* PMSAv8M handling of the aliases is different from v7M: + * aliases A1, A2, A3 override the low two bits of the region + * number in MPU_RNR, and there is no 'region' field in the + * RBAR register. + */ + int aliasno = (offset - 0xd9c) / 8; /* 0..3 */ + if (aliasno) { + region = deposit32(region, 0, 2, aliasno); + } + if (region >= cpu->pmsav7_dregion) { + return 0; + } + return cpu->env.pmsav8.rbar[region]; + } + if (region >= cpu->pmsav7_dregion) { return 0; } return (cpu->env.pmsav7.drbar[region] & 0x1f) | (region & 0xf); } - case 0xda0: /* MPU_RASR */ - case 0xda8: /* MPU_RASR_A1 */ - case 0xdb0: /* MPU_RASR_A2 */ - case 0xdb8: /* MPU_RASR_A3 */ + case 0xda0: /* MPU_RASR (v7M), MPU_RLAR (v8M) */ + case 0xda8: /* MPU_RASR_A1 (v7M), MPU_RLAR_A1 (v8M) */ + case 0xdb0: /* MPU_RASR_A2 (v7M), MPU_RLAR_A2 (v8M) */ + case 0xdb8: /* MPU_RASR_A3 (v7M), MPU_RLAR_A3 (v8M) */ { int region = cpu->env.pmsav7.rnr; + if (arm_feature(&cpu->env, ARM_FEATURE_V8)) { + /* PMSAv8M handling of the aliases is different from v7M: + * aliases A1, A2, A3 override the low two bits of the region + * number in MPU_RNR. + */ + int aliasno = (offset - 0xda0) / 8; /* 0..3 */ + if (aliasno) { + region = deposit32(region, 0, 2, aliasno); + } + if (region >= cpu->pmsav7_dregion) { + return 0; + } + return cpu->env.pmsav8.rlar[region]; + } + if (region >= cpu->pmsav7_dregion) { return 0; } return ((cpu->env.pmsav7.dracr[region] & 0xffff) << 16) | (cpu->env.pmsav7.drsr[region] & 0xffff); } + case 0xdc0: /* MPU_MAIR0 */ + if (!arm_feature(&cpu->env, ARM_FEATURE_V8)) { + goto bad_offset; + } + return cpu->env.pmsav8.mair0; + case 0xdc4: /* MPU_MAIR1 */ + if (!arm_feature(&cpu->env, ARM_FEATURE_V8)) { + goto bad_offset; + } + return cpu->env.pmsav8.mair1; default: + bad_offset: qemu_log_mask(LOG_GUEST_ERROR, "NVIC: Bad read offset 0x%x\n", offset); return 0; } @@ -691,6 +733,26 @@ static void nvic_writel(NVICState *s, uint32_t offset, uint32_t value) { int region; + if (arm_feature(&cpu->env, ARM_FEATURE_V8)) { + /* PMSAv8M handling of the aliases is different from v7M: + * aliases A1, A2, A3 override the low two bits of the region + * number in MPU_RNR, and there is no 'region' field in the + * RBAR register. + */ + int aliasno = (offset - 0xd9c) / 8; /* 0..3 */ + + region = cpu->env.pmsav7.rnr; + if (aliasno) { + region = deposit32(region, 0, 2, aliasno); + } + if (region >= cpu->pmsav7_dregion) { + return; + } + cpu->env.pmsav8.rbar[region] = value; + tlb_flush(CPU(cpu)); + return; + } + if (value & (1 << 4)) { /* VALID bit means use the region number specified in this * value and also update MPU_RNR.REGION with that value. @@ -715,13 +777,32 @@ static void nvic_writel(NVICState *s, uint32_t offset, uint32_t value) tlb_flush(CPU(cpu)); break; } - case 0xda0: /* MPU_RASR */ - case 0xda8: /* MPU_RASR_A1 */ - case 0xdb0: /* MPU_RASR_A2 */ - case 0xdb8: /* MPU_RASR_A3 */ + case 0xda0: /* MPU_RASR (v7M), MPU_RLAR (v8M) */ + case 0xda8: /* MPU_RASR_A1 (v7M), MPU_RLAR_A1 (v8M) */ + case 0xdb0: /* MPU_RASR_A2 (v7M), MPU_RLAR_A2 (v8M) */ + case 0xdb8: /* MPU_RASR_A3 (v7M), MPU_RLAR_A3 (v8M) */ { int region = cpu->env.pmsav7.rnr; + if (arm_feature(&cpu->env, ARM_FEATURE_V8)) { + /* PMSAv8M handling of the aliases is different from v7M: + * aliases A1, A2, A3 override the low two bits of the region + * number in MPU_RNR. + */ + int aliasno = (offset - 0xd9c) / 8; /* 0..3 */ + + region = cpu->env.pmsav7.rnr; + if (aliasno) { + region = deposit32(region, 0, 2, aliasno); + } + if (region >= cpu->pmsav7_dregion) { + return; + } + cpu->env.pmsav8.rlar[region] = value; + tlb_flush(CPU(cpu)); + return; + } + if (region >= cpu->pmsav7_dregion) { return; } @@ -731,6 +812,30 @@ static void nvic_writel(NVICState *s, uint32_t offset, uint32_t value) tlb_flush(CPU(cpu)); break; } + case 0xdc0: /* MPU_MAIR0 */ + if (!arm_feature(&cpu->env, ARM_FEATURE_V8)) { + goto bad_offset; + } + if (cpu->pmsav7_dregion) { + /* Register is RES0 if no MPU regions are implemented */ + cpu->env.pmsav8.mair0 = value; + } + /* We don't need to do anything else because memory attributes + * only affect cacheability, and we don't implement caching. + */ + break; + case 0xdc4: /* MPU_MAIR1 */ + if (!arm_feature(&cpu->env, ARM_FEATURE_V8)) { + goto bad_offset; + } + if (cpu->pmsav7_dregion) { + /* Register is RES0 if no MPU regions are implemented */ + cpu->env.pmsav8.mair1 = value; + } + /* We don't need to do anything else because memory attributes + * only affect cacheability, and we don't implement caching. + */ + break; case 0xf00: /* Software Triggered Interrupt Register */ { int excnum = (value & 0x1ff) + NVIC_FIRST_IRQ; @@ -740,6 +845,7 @@ static void nvic_writel(NVICState *s, uint32_t offset, uint32_t value) break; } default: + bad_offset: qemu_log_mask(LOG_GUEST_ERROR, "NVIC: Bad write offset 0x%x\n", offset); } diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 41ae6ba..8b610de 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -228,17 +228,25 @@ static void arm_cpu_reset(CPUState *s) env->vfp.xregs[ARM_VFP_FPEXC] = 0; #endif - if (arm_feature(env, ARM_FEATURE_PMSA) && - arm_feature(env, ARM_FEATURE_V7)) { + if (arm_feature(env, ARM_FEATURE_PMSA)) { if (cpu->pmsav7_dregion > 0) { - memset(env->pmsav7.drbar, 0, - sizeof(*env->pmsav7.drbar) * cpu->pmsav7_dregion); - memset(env->pmsav7.drsr, 0, - sizeof(*env->pmsav7.drsr) * cpu->pmsav7_dregion); - memset(env->pmsav7.dracr, 0, - sizeof(*env->pmsav7.dracr) * cpu->pmsav7_dregion); + if (arm_feature(env, ARM_FEATURE_V8)) { + memset(env->pmsav8.rbar, 0, + sizeof(*env->pmsav8.rbar) * cpu->pmsav7_dregion); + memset(env->pmsav8.rlar, 0, + sizeof(*env->pmsav8.rlar) * cpu->pmsav7_dregion); + } else if (arm_feature(env, ARM_FEATURE_V7)) { + memset(env->pmsav7.drbar, 0, + sizeof(*env->pmsav7.drbar) * cpu->pmsav7_dregion); + memset(env->pmsav7.drsr, 0, + sizeof(*env->pmsav7.drsr) * cpu->pmsav7_dregion); + memset(env->pmsav7.dracr, 0, + sizeof(*env->pmsav7.dracr) * cpu->pmsav7_dregion); + } } env->pmsav7.rnr = 0; + env->pmsav8.mair0 = 0; + env->pmsav8.mair1 = 0; } set_flush_to_zero(1, &env->vfp.standard_fp_status); @@ -809,9 +817,15 @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp) } if (nr) { - env->pmsav7.drbar = g_new0(uint32_t, nr); - env->pmsav7.drsr = g_new0(uint32_t, nr); - env->pmsav7.dracr = g_new0(uint32_t, nr); + if (arm_feature(env, ARM_FEATURE_V8)) { + /* PMSAv8 */ + env->pmsav8.rbar = g_new0(uint32_t, nr); + env->pmsav8.rlar = g_new0(uint32_t, nr); + } else { + env->pmsav7.drbar = g_new0(uint32_t, nr); + env->pmsav7.drsr = g_new0(uint32_t, nr); + env->pmsav7.dracr = g_new0(uint32_t, nr); + } } } diff --git a/target/arm/machine.c b/target/arm/machine.c index 3193b00..05e2909 100644 --- a/target/arm/machine.c +++ b/target/arm/machine.c @@ -159,7 +159,8 @@ static bool pmsav7_needed(void *opaque) CPUARMState *env = &cpu->env; return arm_feature(env, ARM_FEATURE_PMSA) && - arm_feature(env, ARM_FEATURE_V7); + arm_feature(env, ARM_FEATURE_V7) && + !arm_feature(env, ARM_FEATURE_V8); } static bool pmsav7_rgnr_vmstate_validate(void *opaque, int version_id) @@ -209,6 +210,31 @@ static const VMStateDescription vmstate_pmsav7_rnr = { } }; +static bool pmsav8_needed(void *opaque) +{ + ARMCPU *cpu = opaque; + CPUARMState *env = &cpu->env; + + return arm_feature(env, ARM_FEATURE_PMSA) && + arm_feature(env, ARM_FEATURE_V8); +} + +static const VMStateDescription vmstate_pmsav8 = { + .name = "cpu/pmsav8", + .version_id = 1, + .minimum_version_id = 1, + .needed = pmsav8_needed, + .fields = (VMStateField[]) { + VMSTATE_VARRAY_UINT32(env.pmsav8.rbar, ARMCPU, pmsav7_dregion, 0, + vmstate_info_uint32, uint32_t), + VMSTATE_VARRAY_UINT32(env.pmsav8.rlar, ARMCPU, pmsav7_dregion, 0, + vmstate_info_uint32, uint32_t), + VMSTATE_UINT32(env.pmsav8.mair0, ARMCPU), + VMSTATE_UINT32(env.pmsav8.mair1, ARMCPU), + VMSTATE_END_OF_LIST() + } +}; + static int get_cpsr(QEMUFile *f, void *opaque, size_t size, VMStateField *field) { -- 2.7.4 From MAILER-DAEMON Tue Aug 22 11:09:28 2017 Received: from list by lists.gnu.org with archive (Exim 4.71) id 1dkAo3-0006oe-O2 for mharc-qemu-arm@gnu.org; Tue, 22 Aug 2017 11:09:27 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:53453) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dkAnr-0006Vo-P3 for qemu-arm@nongnu.org; Tue, 22 Aug 2017 11:09:24 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dkAnl-0003BD-Cf for qemu-arm@nongnu.org; Tue, 22 Aug 2017 11:09:15 -0400 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:36966) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1dkAnl-00039F-5Y; Tue, 22 Aug 2017 11:09:09 -0400 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1dkAnc-0004fF-RV; Tue, 22 Aug 2017 16:09:00 +0100 From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: patches@linaro.org Date: Tue, 22 Aug 2017 16:08:44 +0100 Message-Id: <1503414539-28762-6-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1503414539-28762-1-git-send-email-peter.maydell@linaro.org> References: <1503414539-28762-1-git-send-email-peter.maydell@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-arm] [PATCH 05/20] target/arm: Add MMU indexes for secure v8M X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 22 Aug 2017 15:09:24 -0000 Now that MPU lookups can return different results for v8M when the CPU is in secure vs non-secure state, we need to have separate MMU indexes; add the secure counterparts to the existing three M profile MMU indexes. Signed-off-by: Peter Maydell --- target/arm/cpu.h | 19 +++++++++++++++++-- target/arm/helper.c | 9 ++++++++- 2 files changed, 25 insertions(+), 3 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 24666baa..436ca0d 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -2104,6 +2104,10 @@ static inline bool arm_excp_unmasked(CPUState *cs, unsigned int excp_idx, * Execution priority negative (this is like privileged, but the * MPU HFNMIENA bit means that it may have different access permission * check results to normal privileged code, so can't share a TLB). + * If the CPU supports the v8M Security Extension then there are also: + * Secure User + * Secure Privileged + * Secure, execution priority negative * * The ARMMMUIdx and the mmu index value used by the core QEMU TLB code * are not quite the same -- different CPU types (most notably M profile @@ -2141,6 +2145,9 @@ typedef enum ARMMMUIdx { ARMMMUIdx_MUser = 0 | ARM_MMU_IDX_M, ARMMMUIdx_MPriv = 1 | ARM_MMU_IDX_M, ARMMMUIdx_MNegPri = 2 | ARM_MMU_IDX_M, + ARMMMUIdx_MSUser = 3 | ARM_MMU_IDX_M, + ARMMMUIdx_MSPriv = 4 | ARM_MMU_IDX_M, + ARMMMUIdx_MSNegPri = 5 | ARM_MMU_IDX_M, /* Indexes below here don't have TLBs and are used only for AT system * instructions or for the first stage of an S12 page table walk. */ @@ -2162,6 +2169,9 @@ typedef enum ARMMMUIdxBit { ARMMMUIdxBit_MUser = 1 << 0, ARMMMUIdxBit_MPriv = 1 << 1, ARMMMUIdxBit_MNegPri = 1 << 2, + ARMMMUIdxBit_MSUser = 1 << 3, + ARMMMUIdxBit_MSPriv = 1 << 4, + ARMMMUIdxBit_MSNegPri = 1 << 5, } ARMMMUIdxBit; #define MMU_USER_IDX 0 @@ -2187,7 +2197,8 @@ static inline int arm_mmu_idx_to_el(ARMMMUIdx mmu_idx) case ARM_MMU_IDX_A: return mmu_idx & 3; case ARM_MMU_IDX_M: - return mmu_idx == ARMMMUIdx_MUser ? 0 : 1; + return (mmu_idx == ARMMMUIdx_MUser || mmu_idx == ARMMMUIdx_MSUser) + ? 0 : 1; default: g_assert_not_reached(); } @@ -2206,7 +2217,11 @@ static inline int cpu_mmu_index(CPUARMState *env, bool ifetch) */ if ((env->v7m.exception > 0 && env->v7m.exception <= 3) || env->v7m.faultmask) { - return arm_to_core_mmu_idx(ARMMMUIdx_MNegPri); + mmu_idx = ARMMMUIdx_MNegPri; + } + + if (env->v7m.secure) { + mmu_idx += ARMMMUIdx_MSUser; } return arm_to_core_mmu_idx(mmu_idx); diff --git a/target/arm/helper.c b/target/arm/helper.c index 887490a..1debebc 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -7037,6 +7037,9 @@ static inline uint32_t regime_el(CPUARMState *env, ARMMMUIdx mmu_idx) case ARMMMUIdx_MPriv: case ARMMMUIdx_MNegPri: case ARMMMUIdx_MUser: + case ARMMMUIdx_MSPriv: + case ARMMMUIdx_MSNegPri: + case ARMMMUIdx_MSUser: return 1; default: g_assert_not_reached(); @@ -7060,6 +7063,9 @@ static inline bool regime_is_secure(CPUARMState *env, ARMMMUIdx mmu_idx) case ARMMMUIdx_S1E3: case ARMMMUIdx_S1SE0: case ARMMMUIdx_S1SE1: + case ARMMMUIdx_MSPriv: + case ARMMMUIdx_MSNegPri: + case ARMMMUIdx_MSUser: return true; default: g_assert_not_reached(); @@ -7081,7 +7087,8 @@ static inline bool regime_translation_disabled(CPUARMState *env, (R_V7M_MPU_CTRL_ENABLE_MASK | R_V7M_MPU_CTRL_HFNMIENA_MASK)) { case R_V7M_MPU_CTRL_ENABLE_MASK: /* Enabled, but not for HardFault and NMI */ - return mmu_idx == ARMMMUIdx_MNegPri; + return mmu_idx == ARMMMUIdx_MNegPri || + mmu_idx == ARMMMUIdx_MSNegPri; case R_V7M_MPU_CTRL_ENABLE_MASK | R_V7M_MPU_CTRL_HFNMIENA_MASK: /* Enabled for all cases */ return false; -- 2.7.4 From MAILER-DAEMON Tue Aug 22 11:09:28 2017 Received: from list by lists.gnu.org with archive (Exim 4.71) id 1dkAo4-0006pS-4N for mharc-qemu-arm@gnu.org; Tue, 22 Aug 2017 11:09:28 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:53662) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dkAnz-0006ho-GP for qemu-arm@nongnu.org; Tue, 22 Aug 2017 11:09:25 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dkAnr-0003ID-9F for qemu-arm@nongnu.org; Tue, 22 Aug 2017 11:09:23 -0400 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:36984) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1dkAnq-0003E6-SR; Tue, 22 Aug 2017 11:09:15 -0400 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1dkAno-0004mp-Ir; Tue, 22 Aug 2017 16:09:12 +0100 From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: patches@linaro.org Date: Tue, 22 Aug 2017 16:08:59 +0100 Message-Id: <1503414539-28762-21-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1503414539-28762-1-git-send-email-peter.maydell@linaro.org> References: <1503414539-28762-1-git-send-email-peter.maydell@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-arm] [PATCH 20/20] target/arm: Implement BXNS, and banked stack pointers X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 22 Aug 2017 15:09:25 -0000 Implement the BXNS v8M instruction, which is like BX but will do a jump-and-switch-to-NonSecure if the branch target address has bit 0 clear. This is the first piece of code which implements "switch to the other security state", so the commit also includes the code to switch the stack pointers around, which is the only complicated part of switching security state. BLXNS is more complicated than just "BXNS but set the link register", so we leave it for a separate commit. Signed-off-by: Peter Maydell --- target/arm/cpu.h | 13 +++++++++ target/arm/helper.h | 2 ++ target/arm/translate.h | 1 + target/arm/helper.c | 79 ++++++++++++++++++++++++++++++++++++++++++++++++++ target/arm/machine.c | 2 ++ target/arm/translate.c | 42 ++++++++++++++++++++++++++- 6 files changed, 138 insertions(+), 1 deletion(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 3683537..5e7b68b 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -419,7 +419,20 @@ typedef struct CPUARMState { } cp15; struct { + /* M profile has up to 4 stack pointers: + * a Main Stack Pointer and a Process Stack Pointer for each + * of the Secure and Non-Secure states. (If the CPU doesn't support + * the security extension then it has only two SPs.) + * In QEMU we always store the currently active SP in regs[13], + * and the non-active SP for the current security state in + * v7m.other_sp. The stack pointers for the inactive security state + * are stored in other_ss_msp and other_ss_psp. + * switch_v7m_security_state() is responsible for rearranging them + * when we change security state. + */ uint32_t other_sp; + uint32_t other_ss_msp; + uint32_t other_ss_psp; uint32_t vecbase[2]; uint32_t basepri[2]; uint32_t control[2]; diff --git a/target/arm/helper.h b/target/arm/helper.h index df86bf7..64afbac 100644 --- a/target/arm/helper.h +++ b/target/arm/helper.h @@ -63,6 +63,8 @@ DEF_HELPER_1(cpsr_read, i32, env) DEF_HELPER_3(v7m_msr, void, env, i32, i32) DEF_HELPER_2(v7m_mrs, i32, env, i32) +DEF_HELPER_2(v7m_bxns, void, env, i32) + DEF_HELPER_4(access_check_cp_reg, void, env, ptr, i32, i32) DEF_HELPER_3(set_cp_reg, void, env, ptr, i32) DEF_HELPER_2(get_cp_reg, i32, env, ptr) diff --git a/target/arm/translate.h b/target/arm/translate.h index 2fe144b..ef625ad 100644 --- a/target/arm/translate.h +++ b/target/arm/translate.h @@ -32,6 +32,7 @@ typedef struct DisasContext { int vec_len; int vec_stride; bool v7m_handler_mode; + bool v8m_secure; /* true if v8M and we're in Secure mode */ /* Immediate value in AArch32 SVC insn; must be set if is_jmp == DISAS_SWI * so that top level loop can generate correct syndrome information. */ diff --git a/target/arm/helper.c b/target/arm/helper.c index b1ae73c..4489bbd 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -5875,6 +5875,12 @@ uint32_t HELPER(v7m_mrs)(CPUARMState *env, uint32_t reg) return 0; } +void HELPER(v7m_bxns)(CPUARMState *env, uint32_t dest) +{ + /* translate.c should never generate calls here in user-only mode */ + g_assert_not_reached(); +} + void switch_mode(CPUARMState *env, int mode) { ARMCPU *cpu = arm_env_get_cpu(env); @@ -6049,6 +6055,18 @@ static uint32_t v7m_pop(CPUARMState *env) return val; } +/* Return true if we're using the process stack pointer (not the MSP) */ +static bool v7m_using_psp(CPUARMState *env) +{ + /* Handler mode always uses the main stack; for thread mode + * the CONTROL.SPSEL bit determines the answer. + * Note that in v7M it is not possible to be in Handler mode with + * CONTROL.SPSEL non-zero, but in v8M it is, so we must check both. + */ + return !arm_v7m_is_handler_mode(env) && + env->v7m.control[env->v7m.secure] & R_V7M_CONTROL_SPSEL_MASK; +} + /* Switch to V7M main or process stack pointer. */ static void switch_v7m_sp(CPUARMState *env, bool new_spsel) { @@ -6067,6 +6085,67 @@ static void switch_v7m_sp(CPUARMState *env, bool new_spsel) } } +/* Switch M profile security state between NS and S */ +static void switch_v7m_security_state(CPUARMState *env, bool new_secstate) +{ + uint32_t new_ss_msp, new_ss_psp; + + if (env->v7m.secure == new_secstate) { + return; + } + + /* All the banked state is accessed by looking at env->v7m.secure + * except for the stack pointer; rearrange the SP appropriately. + */ + new_ss_msp = env->v7m.other_ss_msp; + new_ss_psp = env->v7m.other_ss_psp; + + if (v7m_using_psp(env)) { + env->v7m.other_ss_psp = env->regs[13]; + env->v7m.other_ss_msp = env->v7m.other_sp; + } else { + env->v7m.other_ss_msp = env->regs[13]; + env->v7m.other_ss_psp = env->v7m.other_sp; + } + + env->v7m.secure = new_secstate; + + if (v7m_using_psp(env)) { + env->regs[13] = new_ss_psp; + env->v7m.other_sp = new_ss_msp; + } else { + env->regs[13] = new_ss_msp; + env->v7m.other_sp = new_ss_psp; + } +} + +void HELPER(v7m_bxns)(CPUARMState *env, uint32_t dest) +{ + /* Handle v7M BXNS: + * - if the return value is a magic value, do exception return (like BX) + * - otherwise bit 0 of the return value is the target security state + */ + if (dest >= 0xff000000) { + /* This is an exception return magic value; put it where + * do_v7m_exception_exit() expects and raise EXCEPTION_EXIT. + * Note that if we ever add gen_ss_advance() singlestep support to + * M profile this should count as an "instruction execution complete" + * event (compare gen_bx_excret_final_code()). + */ + env->regs[15] = dest & ~1; + env->thumb = dest & 1; + HELPER(exception_internal)(env, EXCP_EXCEPTION_EXIT); + /* notreached */ + } + + /* translate.c should have made BXNS UNDEF unless we're secure */ + assert(env->v7m.secure); + + switch_v7m_security_state(env, dest & 1); + env->thumb = 1; + env->regs[15] = dest & ~1; +} + static uint32_t arm_v7m_load_vector(ARMCPU *cpu) { CPUState *cs = CPU(cpu); diff --git a/target/arm/machine.c b/target/arm/machine.c index 3cc94b4..1aca40d 100644 --- a/target/arm/machine.c +++ b/target/arm/machine.c @@ -257,6 +257,8 @@ static const VMStateDescription vmstate_m_security = { .needed = m_security_needed, .fields = (VMStateField[]) { VMSTATE_UINT32(env.v7m.secure, ARMCPU), + VMSTATE_UINT32(env.v7m.other_ss_msp, ARMCPU), + VMSTATE_UINT32(env.v7m.other_ss_psp, ARMCPU), VMSTATE_UINT32(env.v7m.basepri[M_REG_S], ARMCPU), VMSTATE_UINT32(env.v7m.primask[M_REG_S], ARMCPU), VMSTATE_UINT32(env.v7m.faultmask[M_REG_S], ARMCPU), diff --git a/target/arm/translate.c b/target/arm/translate.c index 6aa2d7c..e7966e2 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -994,6 +994,25 @@ static inline void gen_bx_excret_final_code(DisasContext *s) gen_exception_internal(EXCP_EXCEPTION_EXIT); } +static inline void gen_bxns(DisasContext *s, int rm) +{ + TCGv_i32 var = load_reg(s, rm); + + /* The bxns helper may raise an EXCEPTION_EXIT exception, so in theory + * we need to sync state before calling it, but: + * - we don't need to do gen_set_pc_im() because the bxns helper will + * always set the PC itself + * - we don't need to do gen_set_condexec() because BXNS is UNPREDICTABLE + * unless it's outside an IT block or the last insn in an IT block, + * so we know that condexec == 0 (already set at the top of the TB) + * is correct in the non-UNPREDICTABLE cases, and we can choose + * "zeroes the IT bits" as our UNPREDICTABLE behaviour otherwise. + */ + gen_helper_v7m_bxns(cpu_env, var); + tcg_temp_free_i32(var); + s->is_jmp = DISAS_EXIT; +} + /* Variant of store_reg which uses branch&exchange logic when storing to r15 in ARM architecture v7 and above. The source must be a temporary and will be marked as dead. */ @@ -11185,12 +11204,31 @@ static void disas_thumb_insn(CPUARMState *env, DisasContext *s) */ bool link = insn & (1 << 7); - if (insn & 7) { + if (insn & 3) { goto undef; } if (link) { ARCH(5); } + if ((insn & 4)) { + /* BXNS/BLXNS: only exists for v8M with the + * security extensions, and always UNDEF if NonSecure. + * We don't implement these in the user-only mode + * either (in theory you can use them from Secure User + * mode but they are too tied in to system emulation.) + */ + if (!s->v8m_secure || IS_USER_ONLY) { + goto undef; + } + if (link) { + /* BLXNS: not yet implemented */ + goto undef; + } else { + gen_bxns(s, rm); + } + break; + } + /* BLX/BX */ tmp = load_reg(s, rm); if (link) { val = (uint32_t)s->pc | 1; @@ -11878,6 +11916,8 @@ void gen_intermediate_code(CPUState *cs, TranslationBlock *tb) dc->vec_stride = ARM_TBFLAG_VECSTRIDE(tb->flags); dc->c15_cpar = ARM_TBFLAG_XSCALE_CPAR(tb->flags); dc->v7m_handler_mode = ARM_TBFLAG_HANDLER(tb->flags); + dc->v8m_secure = arm_feature(env, ARM_FEATURE_M_SECURITY) && + regime_is_secure(env, dc->mmu_idx); dc->cp_regs = cpu->cp_regs; dc->features = env->features; -- 2.7.4 From MAILER-DAEMON Tue Aug 22 11:09:28 2017 Received: from list by lists.gnu.org with archive (Exim 4.71) id 1dkAo4-0006qG-Ct for mharc-qemu-arm@gnu.org; Tue, 22 Aug 2017 11:09:28 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:53491) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dkAnt-0006Z8-Eu for qemu-arm@nongnu.org; Tue, 22 Aug 2017 11:09:26 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dkAnq-0003Gi-8F for qemu-arm@nongnu.org; Tue, 22 Aug 2017 11:09:17 -0400 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:36984) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1dkAnp-0003E6-RH; Tue, 22 Aug 2017 11:09:14 -0400 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1dkAnn-0004lV-1q; Tue, 22 Aug 2017 16:09:11 +0100 From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: patches@linaro.org Date: Tue, 22 Aug 2017 16:08:57 +0100 Message-Id: <1503414539-28762-19-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1503414539-28762-1-git-send-email-peter.maydell@linaro.org> References: <1503414539-28762-1-git-send-email-peter.maydell@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-arm] [PATCH 18/20] target/arm: Make CFSR register banked for v8M X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 22 Aug 2017 15:09:26 -0000 Make the CFSR register banked if v8M security extensions are enabled. Not all the bits in this register are banked: the BFSR bits [15:8] are shared between S and NS, and we store them in the NS copy of the register. Signed-off-by: Peter Maydell --- target/arm/cpu.h | 7 ++++++- hw/intc/armv7m_nvic.c | 15 +++++++++++++-- target/arm/helper.c | 18 +++++++++--------- target/arm/machine.c | 3 ++- 4 files changed, 30 insertions(+), 13 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 21c68d7..3683537 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -424,7 +424,7 @@ typedef struct CPUARMState { uint32_t basepri[2]; uint32_t control[2]; uint32_t ccr[2]; /* Configuration and Control */ - uint32_t cfsr; /* Configurable Fault Status */ + uint32_t cfsr[2]; /* Configurable Fault Status */ uint32_t hfsr; /* HardFault Status */ uint32_t dfsr; /* Debug Fault Status Register */ uint32_t mmfar[2]; /* MemManage Fault Address */ @@ -1210,6 +1210,11 @@ FIELD(V7M_CFSR, NOCP, 16 + 3, 1) FIELD(V7M_CFSR, UNALIGNED, 16 + 8, 1) FIELD(V7M_CFSR, DIVBYZERO, 16 + 9, 1) +/* V7M CFSR bit masks covering all of the subregister bits */ +FIELD(V7M_CFSR, MMFSR, 0, 8) +FIELD(V7M_CFSR, BFSR, 8, 8) +FIELD(V7M_CFSR, UFSR, 16, 16) + /* V7M HFSR bits */ FIELD(V7M_HFSR, VECTTBL, 1, 1) FIELD(V7M_HFSR, FORCED, 30, 1) diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c index 99b62ac..3c14cc8 100644 --- a/hw/intc/armv7m_nvic.c +++ b/hw/intc/armv7m_nvic.c @@ -500,7 +500,12 @@ static uint32_t nvic_readl(NVICState *s, uint32_t offset, MemTxAttrs attrs) } return val; case 0xd28: /* Configurable Fault Status. */ - return cpu->env.v7m.cfsr; + /* The BFSR bits [15:8] are shared between security states + * and we store them in the NS copy + */ + val = cpu->env.v7m.cfsr[attrs.secure]; + val |= cpu->env.v7m.cfsr[M_REG_NS] & R_V7M_CFSR_BFSR_MASK; + return val; case 0xd2c: /* Hard Fault Status. */ return cpu->env.v7m.hfsr; case 0xd30: /* Debug Fault Status. */ @@ -714,7 +719,13 @@ static void nvic_writel(NVICState *s, uint32_t offset, uint32_t value, nvic_irq_update(s); break; case 0xd28: /* Configurable Fault Status. */ - cpu->env.v7m.cfsr &= ~value; /* W1C */ + cpu->env.v7m.cfsr[attrs.secure] &= ~value; /* W1C */ + if (attrs.secure) { + /* The BFSR bits [15:8] are shared between security states + * and we store them in the NS copy. + */ + cpu->env.v7m.cfsr[M_REG_NS] &= ~(value & R_V7M_CFSR_BFSR_MASK); + } break; case 0xd2c: /* Hard Fault Status. */ cpu->env.v7m.hfsr &= ~value; /* W1C */ diff --git a/target/arm/helper.c b/target/arm/helper.c index e587e85..67b3874 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -6229,7 +6229,7 @@ static void do_v7m_exception_exit(ARMCPU *cpu) /* Bad exception return: instead of popping the exception * stack, directly take a usage fault on the current stack. */ - env->v7m.cfsr |= R_V7M_CFSR_INVPC_MASK; + env->v7m.cfsr[env->v7m.secure] |= R_V7M_CFSR_INVPC_MASK; armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE); v7m_exception_taken(cpu, type | 0xf0000000); qemu_log_mask(CPU_LOG_INT, "...taking UsageFault on existing " @@ -6271,7 +6271,7 @@ static void do_v7m_exception_exit(ARMCPU *cpu) if (return_to_handler != arm_v7m_is_handler_mode(env)) { /* Take an INVPC UsageFault by pushing the stack again. */ armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE); - env->v7m.cfsr |= R_V7M_CFSR_INVPC_MASK; + env->v7m.cfsr[env->v7m.secure] |= R_V7M_CFSR_INVPC_MASK; v7m_push_stack(cpu); v7m_exception_taken(cpu, type | 0xf0000000); qemu_log_mask(CPU_LOG_INT, "...taking UsageFault on new stackframe: " @@ -6330,15 +6330,15 @@ void arm_v7m_cpu_do_interrupt(CPUState *cs) switch (cs->exception_index) { case EXCP_UDEF: armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE); - env->v7m.cfsr |= R_V7M_CFSR_UNDEFINSTR_MASK; + env->v7m.cfsr[env->v7m.secure] |= R_V7M_CFSR_UNDEFINSTR_MASK; break; case EXCP_NOCP: armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE); - env->v7m.cfsr |= R_V7M_CFSR_NOCP_MASK; + env->v7m.cfsr[env->v7m.secure] |= R_V7M_CFSR_NOCP_MASK; break; case EXCP_INVSTATE: armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE); - env->v7m.cfsr |= R_V7M_CFSR_INVSTATE_MASK; + env->v7m.cfsr[env->v7m.secure] |= R_V7M_CFSR_INVSTATE_MASK; break; case EXCP_SWI: /* The PC already points to the next instruction. */ @@ -6354,11 +6354,11 @@ void arm_v7m_cpu_do_interrupt(CPUState *cs) case 0x8: /* External Abort */ switch (cs->exception_index) { case EXCP_PREFETCH_ABORT: - env->v7m.cfsr |= R_V7M_CFSR_PRECISERR_MASK; + env->v7m.cfsr[M_REG_NS] |= R_V7M_CFSR_PRECISERR_MASK; qemu_log_mask(CPU_LOG_INT, "...with CFSR.PRECISERR\n"); break; case EXCP_DATA_ABORT: - env->v7m.cfsr |= + env->v7m.cfsr[M_REG_NS] |= (R_V7M_CFSR_IBUSERR_MASK | R_V7M_CFSR_BFARVALID_MASK); env->v7m.bfar = env->exception.vaddress; qemu_log_mask(CPU_LOG_INT, @@ -6374,11 +6374,11 @@ void arm_v7m_cpu_do_interrupt(CPUState *cs) */ switch (cs->exception_index) { case EXCP_PREFETCH_ABORT: - env->v7m.cfsr |= R_V7M_CFSR_IACCVIOL_MASK; + env->v7m.cfsr[env->v7m.secure] |= R_V7M_CFSR_IACCVIOL_MASK; qemu_log_mask(CPU_LOG_INT, "...with CFSR.IACCVIOL\n"); break; case EXCP_DATA_ABORT: - env->v7m.cfsr |= + env->v7m.cfsr[env->v7m.secure] |= (R_V7M_CFSR_DACCVIOL_MASK | R_V7M_CFSR_MMARVALID_MASK); env->v7m.mmfar[env->v7m.secure] = env->exception.vaddress; qemu_log_mask(CPU_LOG_INT, diff --git a/target/arm/machine.c b/target/arm/machine.c index 5122e58..3cc94b4 100644 --- a/target/arm/machine.c +++ b/target/arm/machine.c @@ -118,7 +118,7 @@ static const VMStateDescription vmstate_m = { VMSTATE_UINT32(env.v7m.basepri[M_REG_NS], ARMCPU), VMSTATE_UINT32(env.v7m.control[M_REG_NS], ARMCPU), VMSTATE_UINT32(env.v7m.ccr[M_REG_NS], ARMCPU), - VMSTATE_UINT32(env.v7m.cfsr, ARMCPU), + VMSTATE_UINT32(env.v7m.cfsr[M_REG_NS], ARMCPU), VMSTATE_UINT32(env.v7m.hfsr, ARMCPU), VMSTATE_UINT32(env.v7m.dfsr, ARMCPU), VMSTATE_UINT32(env.v7m.mmfar[M_REG_NS], ARMCPU), @@ -273,6 +273,7 @@ static const VMStateDescription vmstate_m_security = { VMSTATE_UINT32(env.v7m.mpu_ctrl[M_REG_S], ARMCPU), VMSTATE_UINT32(env.v7m.ccr[M_REG_S], ARMCPU), VMSTATE_UINT32(env.v7m.mmfar[M_REG_S], ARMCPU), + VMSTATE_UINT32(env.v7m.cfsr[M_REG_S], ARMCPU), VMSTATE_END_OF_LIST() } }; -- 2.7.4 From MAILER-DAEMON Tue Aug 22 11:09:31 2017 Received: from list by lists.gnu.org with archive (Exim 4.71) id 1dkAo7-0006uP-3y for mharc-qemu-arm@gnu.org; Tue, 22 Aug 2017 11:09:31 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:53421) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dkAnq-0006Ve-GF for qemu-arm@nongnu.org; Tue, 22 Aug 2017 11:09:17 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dkAnl-0003Bv-Sv for qemu-arm@nongnu.org; Tue, 22 Aug 2017 11:09:14 -0400 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:36936) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1dkAnl-00031e-LI; Tue, 22 Aug 2017 11:09:09 -0400 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1dkAnb-0004eF-6B; Tue, 22 Aug 2017 16:08:59 +0100 From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: patches@linaro.org Date: Tue, 22 Aug 2017 16:08:42 +0100 Message-Id: <1503414539-28762-4-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1503414539-28762-1-git-send-email-peter.maydell@linaro.org> References: <1503414539-28762-1-git-send-email-peter.maydell@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-arm] [PATCH 03/20] target/arm: Add state field, feature bit and migration for v8M secure state X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 22 Aug 2017 15:09:17 -0000 As the first step in implementing ARM v8M's security extension: * add a new feature bit ARM_FEATURE_M_SECURITY * add the CPU state field that indicates whether the CPU is currently in the secure state * add a migration subsection for this new state (we will add the Secure copies of banked register state to this subsection in later patches) * add a #define for the one new-in-v8M exception type * make the CPU debug log print S/NS status Signed-off-by: Peter Maydell --- target/arm/cpu.h | 3 +++ target/arm/cpu.c | 4 ++++ target/arm/machine.c | 20 ++++++++++++++++++++ target/arm/translate.c | 8 +++++++- 4 files changed, 34 insertions(+), 1 deletion(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index b6bb78a..24666baa 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -66,6 +66,7 @@ #define ARMV7M_EXCP_MEM 4 #define ARMV7M_EXCP_BUS 5 #define ARMV7M_EXCP_USAGE 6 +#define ARMV7M_EXCP_SECURE 7 #define ARMV7M_EXCP_SVC 11 #define ARMV7M_EXCP_DEBUG 12 #define ARMV7M_EXCP_PENDSV 14 @@ -420,6 +421,7 @@ typedef struct CPUARMState { int exception; uint32_t primask; uint32_t faultmask; + uint32_t secure; /* Is CPU in Secure state? (not guest visible) */ } v7m; /* Information associated with an exception about to be taken: @@ -1264,6 +1266,7 @@ enum arm_features { ARM_FEATURE_THUMB_DSP, /* DSP insns supported in the Thumb encodings */ ARM_FEATURE_PMU, /* has PMU support */ ARM_FEATURE_VBAR, /* has cp15 VBAR */ + ARM_FEATURE_M_SECURITY, /* M profile Security Extension */ }; static inline int arm_feature(CPUARMState *env, int feature) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 8b610de..f32317e 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -185,6 +185,10 @@ static void arm_cpu_reset(CPUState *s) uint32_t initial_pc; /* Loaded from 0x4 */ uint8_t *rom; + if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { + env->v7m.secure = true; + } + /* The reset value of this bit is IMPDEF, but ARM recommends * that it resets to 1, so QEMU always does that rather than making * it dependent on CPU model. diff --git a/target/arm/machine.c b/target/arm/machine.c index 05e2909..745adae 100644 --- a/target/arm/machine.c +++ b/target/arm/machine.c @@ -235,6 +235,25 @@ static const VMStateDescription vmstate_pmsav8 = { } }; +static bool m_security_needed(void *opaque) +{ + ARMCPU *cpu = opaque; + CPUARMState *env = &cpu->env; + + return arm_feature(env, ARM_FEATURE_M_SECURITY); +} + +static const VMStateDescription vmstate_m_security = { + .name = "cpu/m-security", + .version_id = 1, + .minimum_version_id = 1, + .needed = m_security_needed, + .fields = (VMStateField[]) { + VMSTATE_UINT32(env.v7m.secure, ARMCPU), + VMSTATE_END_OF_LIST() + } +}; + static int get_cpsr(QEMUFile *f, void *opaque, size_t size, VMStateField *field) { @@ -484,6 +503,7 @@ const VMStateDescription vmstate_arm_cpu = { */ &vmstate_pmsav7_rnr, &vmstate_pmsav7, + &vmstate_m_security, NULL } }; diff --git a/target/arm/translate.c b/target/arm/translate.c index e52a6d7..dea0a6f 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -12232,6 +12232,11 @@ void arm_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf, if (arm_feature(env, ARM_FEATURE_M)) { uint32_t xpsr = xpsr_read(env); const char *mode; + const char *ns_status = ""; + + if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { + ns_status = env->v7m.secure ? "S " : "NS "; + } if (xpsr & XPSR_EXCP) { mode = "handler"; @@ -12243,13 +12248,14 @@ void arm_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf, } } - cpu_fprintf(f, "XPSR=%08x %c%c%c%c %c %s\n", + cpu_fprintf(f, "XPSR=%08x %c%c%c%c %c %s%s\n", xpsr, xpsr & XPSR_N ? 'N' : '-', xpsr & XPSR_Z ? 'Z' : '-', xpsr & XPSR_C ? 'C' : '-', xpsr & XPSR_V ? 'V' : '-', xpsr & XPSR_T ? 'T' : 'A', + ns_status, mode); } else { uint32_t psr = cpsr_read(env); -- 2.7.4 From MAILER-DAEMON Tue Aug 22 11:09:33 2017 Received: from list by lists.gnu.org with archive (Exim 4.71) id 1dkAo9-000703-9W for mharc-qemu-arm@gnu.org; Tue, 22 Aug 2017 11:09:33 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:53569) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dkAnw-0006dv-IN for qemu-arm@nongnu.org; Tue, 22 Aug 2017 11:09:23 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dkAns-0003Iz-CH for qemu-arm@nongnu.org; Tue, 22 Aug 2017 11:09:20 -0400 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:36984) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1dkAnr-0003E6-Ux; Tue, 22 Aug 2017 11:09:16 -0400 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1dkAnj-0004jb-UZ; Tue, 22 Aug 2017 16:09:07 +0100 From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: patches@linaro.org Date: Tue, 22 Aug 2017 16:08:53 +0100 Message-Id: <1503414539-28762-15-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1503414539-28762-1-git-send-email-peter.maydell@linaro.org> References: <1503414539-28762-1-git-send-email-peter.maydell@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-arm] [PATCH 14/20] target/arm: Make MPU_RNR register banked for v8M X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 22 Aug 2017 15:09:23 -0000 Make the MPU_RNR register banked if v8M security extensions are enabled. Signed-off-by: Peter Maydell --- target/arm/cpu.h | 2 +- hw/intc/armv7m_nvic.c | 18 +++++++++--------- target/arm/cpu.c | 3 ++- target/arm/helper.c | 6 +++--- target/arm/machine.c | 13 +++++++++++-- 5 files changed, 26 insertions(+), 16 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 12fa95e..43d36d6 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -533,7 +533,7 @@ typedef struct CPUARMState { uint32_t *drbar; uint32_t *drsr; uint32_t *dracr; - uint32_t rnr; + uint32_t rnr[2]; } pmsav7; /* PMSAv8 MPU */ diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c index 9ced7af..c3c214c 100644 --- a/hw/intc/armv7m_nvic.c +++ b/hw/intc/armv7m_nvic.c @@ -543,13 +543,13 @@ static uint32_t nvic_readl(NVICState *s, uint32_t offset, MemTxAttrs attrs) case 0xd94: /* MPU_CTRL */ return cpu->env.v7m.mpu_ctrl; case 0xd98: /* MPU_RNR */ - return cpu->env.pmsav7.rnr; + return cpu->env.pmsav7.rnr[attrs.secure]; case 0xd9c: /* MPU_RBAR */ case 0xda4: /* MPU_RBAR_A1 */ case 0xdac: /* MPU_RBAR_A2 */ case 0xdb4: /* MPU_RBAR_A3 */ { - int region = cpu->env.pmsav7.rnr; + int region = cpu->env.pmsav7.rnr[attrs.secure]; if (arm_feature(&cpu->env, ARM_FEATURE_V8)) { /* PMSAv8M handling of the aliases is different from v7M: @@ -577,7 +577,7 @@ static uint32_t nvic_readl(NVICState *s, uint32_t offset, MemTxAttrs attrs) case 0xdb0: /* MPU_RASR_A2 (v7M), MPU_RLAR_A2 (v8M) */ case 0xdb8: /* MPU_RASR_A3 (v7M), MPU_RLAR_A3 (v8M) */ { - int region = cpu->env.pmsav7.rnr; + int region = cpu->env.pmsav7.rnr[attrs.secure]; if (arm_feature(&cpu->env, ARM_FEATURE_V8)) { /* PMSAv8M handling of the aliases is different from v7M: @@ -731,7 +731,7 @@ static void nvic_writel(NVICState *s, uint32_t offset, uint32_t value, PRIu32 "/%" PRIu32 "\n", value, cpu->pmsav7_dregion); } else { - cpu->env.pmsav7.rnr = value; + cpu->env.pmsav7.rnr[attrs.secure] = value; } break; case 0xd9c: /* MPU_RBAR */ @@ -749,7 +749,7 @@ static void nvic_writel(NVICState *s, uint32_t offset, uint32_t value, */ int aliasno = (offset - 0xd9c) / 8; /* 0..3 */ - region = cpu->env.pmsav7.rnr; + region = cpu->env.pmsav7.rnr[attrs.secure]; if (aliasno) { region = deposit32(region, 0, 2, aliasno); } @@ -772,9 +772,9 @@ static void nvic_writel(NVICState *s, uint32_t offset, uint32_t value, region, cpu->pmsav7_dregion); return; } - cpu->env.pmsav7.rnr = region; + cpu->env.pmsav7.rnr[attrs.secure] = region; } else { - region = cpu->env.pmsav7.rnr; + region = cpu->env.pmsav7.rnr[attrs.secure]; } if (region >= cpu->pmsav7_dregion) { @@ -790,7 +790,7 @@ static void nvic_writel(NVICState *s, uint32_t offset, uint32_t value, case 0xdb0: /* MPU_RASR_A2 (v7M), MPU_RLAR_A2 (v8M) */ case 0xdb8: /* MPU_RASR_A3 (v7M), MPU_RLAR_A3 (v8M) */ { - int region = cpu->env.pmsav7.rnr; + int region = cpu->env.pmsav7.rnr[attrs.secure]; if (arm_feature(&cpu->env, ARM_FEATURE_V8)) { /* PMSAv8M handling of the aliases is different from v7M: @@ -799,7 +799,7 @@ static void nvic_writel(NVICState *s, uint32_t offset, uint32_t value, */ int aliasno = (offset - 0xd9c) / 8; /* 0..3 */ - region = cpu->env.pmsav7.rnr; + region = cpu->env.pmsav7.rnr[attrs.secure]; if (aliasno) { region = deposit32(region, 0, 2, aliasno); } diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 333029c..11038b8 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -258,7 +258,8 @@ static void arm_cpu_reset(CPUState *s) sizeof(*env->pmsav7.dracr) * cpu->pmsav7_dregion); } } - env->pmsav7.rnr = 0; + env->pmsav7.rnr[M_REG_NS] = 0; + env->pmsav7.rnr[M_REG_S] = 0; memset(env->pmsav8.mair0, 0, sizeof(env->pmsav8.mair0)); memset(env->pmsav8.mair1, 0, sizeof(env->pmsav8.mair1)); } diff --git a/target/arm/helper.c b/target/arm/helper.c index 5394cef..48e0fc6 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -2385,7 +2385,7 @@ static uint64_t pmsav7_read(CPUARMState *env, const ARMCPRegInfo *ri) return 0; } - u32p += env->pmsav7.rnr; + u32p += env->pmsav7.rnr[M_REG_NS]; return *u32p; } @@ -2399,7 +2399,7 @@ static void pmsav7_write(CPUARMState *env, const ARMCPRegInfo *ri, return; } - u32p += env->pmsav7.rnr; + u32p += env->pmsav7.rnr[M_REG_NS]; tlb_flush(CPU(cpu)); /* Mappings may have changed - purge! */ *u32p = value; } @@ -2442,7 +2442,7 @@ static const ARMCPRegInfo pmsav7_cp_reginfo[] = { .resetfn = arm_cp_reset_ignore }, { .name = "RGNR", .cp = 15, .crn = 6, .opc1 = 0, .crm = 2, .opc2 = 0, .access = PL1_RW, - .fieldoffset = offsetof(CPUARMState, pmsav7.rnr), + .fieldoffset = offsetof(CPUARMState, pmsav7.rnr[M_REG_NS]), .writefn = pmsav7_rgnr_write, .resetfn = arm_cp_reset_ignore }, REGINFO_SENTINEL diff --git a/target/arm/machine.c b/target/arm/machine.c index 05c6c7a..6941e35 100644 --- a/target/arm/machine.c +++ b/target/arm/machine.c @@ -167,7 +167,7 @@ static bool pmsav7_rgnr_vmstate_validate(void *opaque, int version_id) { ARMCPU *cpu = opaque; - return cpu->env.pmsav7.rnr < cpu->pmsav7_dregion; + return cpu->env.pmsav7.rnr[M_REG_NS] < cpu->pmsav7_dregion; } static const VMStateDescription vmstate_pmsav7 = { @@ -205,7 +205,7 @@ static const VMStateDescription vmstate_pmsav7_rnr = { .minimum_version_id = 1, .needed = pmsav7_rnr_needed, .fields = (VMStateField[]) { - VMSTATE_UINT32(env.pmsav7.rnr, ARMCPU), + VMSTATE_UINT32(env.pmsav7.rnr[M_REG_NS], ARMCPU), VMSTATE_END_OF_LIST() } }; @@ -235,6 +235,13 @@ static const VMStateDescription vmstate_pmsav8 = { } }; +static bool s_rnr_vmstate_validate(void *opaque, int version_id) +{ + ARMCPU *cpu = opaque; + + return cpu->env.pmsav7.rnr[M_REG_S] < cpu->pmsav7_dregion; +} + static bool m_security_needed(void *opaque) { ARMCPU *cpu = opaque; @@ -261,6 +268,8 @@ static const VMStateDescription vmstate_m_security = { 0, vmstate_info_uint32, uint32_t), VMSTATE_VARRAY_UINT32(env.pmsav8.rlar[M_REG_S], ARMCPU, pmsav7_dregion, 0, vmstate_info_uint32, uint32_t), + VMSTATE_UINT32(env.pmsav7.rnr[M_REG_S], ARMCPU), + VMSTATE_VALIDATE("secure MPU_RNR is valid", s_rnr_vmstate_validate), VMSTATE_END_OF_LIST() } }; -- 2.7.4 From MAILER-DAEMON Tue Aug 22 11:13:14 2017 Received: from list by lists.gnu.org with archive (Exim 4.71) id 1dkArh-0001vl-U2 for mharc-qemu-arm@gnu.org; Tue, 22 Aug 2017 11:13:13 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:55004) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dkArd-0001sl-0u for qemu-arm@nongnu.org; Tue, 22 Aug 2017 11:13:09 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dkArZ-0007wG-6b for qemu-arm@nongnu.org; Tue, 22 Aug 2017 11:13:09 -0400 Received: from mail-wm0-x22d.google.com ([2a00:1450:400c:c09::22d]:37870) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1dkArY-0007vL-UC for qemu-arm@nongnu.org; Tue, 22 Aug 2017 11:13:05 -0400 Received: by mail-wm0-x22d.google.com with SMTP id b189so207661wmd.0 for ; Tue, 22 Aug 2017 08:13:04 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:in-reply-to:references:from:date:message-id:subject:to :cc; bh=PYKdjk/4qP94bgsbUz0gGB53KNSF1nXEATAQQuLXYJs=; b=VO5r4LkvmWbPEXpYagnBbI2h5jbFZichfuAG79ZHsF397QpGnJM0fNdM4BdebEnENm w3l6YVhjaVORKJkT7i4/hlZvZ0PDfg5c0BSwI+qI3hHVjXX//IfyLMHeT2oeSMd0Pa3j Q4ojIt8AuvisPASK0IZdc8kQEKEy2JVWUj6JY= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:in-reply-to:references:from:date :message-id:subject:to:cc; bh=PYKdjk/4qP94bgsbUz0gGB53KNSF1nXEATAQQuLXYJs=; b=qt0CvqK3P6TRWQMtQ5wdoEqKv8g++bTuS3ztap7ue9ssTMyya+R/BCRL13XnAf3Bqg X4AZ876f0mPqDPB0d9VrdSqtfX2iZInt6o3Jm+BoWwNqc4+IeYs9zKwQEHJ8O49LU64+ nvtiKjTDnEcHliKPWInMBQW07XDAfPAEROLCitPD+C9RHTEsDIi76Vm/Nqk89hROxIO7 80SdQpzGXTudMGycv4H3nQqL2myvgpmeFH31MWFpirB6kSQWQJbGks5XKtJHMdEzFUI3 ev3dnNimWPvGh0yOO115kVk6dKC9twp4QtsNKz2ZeZcekyke/bOHBFqR777iUFeC5TbW 6Zrg== X-Gm-Message-State: AHYfb5h6iAdyf60AH41I91NgN8umgZpPgH2fcmv9CEQZCsBYx2lc9T1V a38fs8Eofcai+ZvtHzwFSKJTViejndyT X-Received: by 10.28.134.201 with SMTP id i192mr4366wmd.124.1503414783874; Tue, 22 Aug 2017 08:13:03 -0700 (PDT) MIME-Version: 1.0 Received: by 10.223.134.54 with HTTP; Tue, 22 Aug 2017 08:12:43 -0700 (PDT) In-Reply-To: <1503414375-21009-1-git-send-email-thuth@redhat.com> References: <1503414375-21009-1-git-send-email-thuth@redhat.com> From: Peter Maydell Date: Tue, 22 Aug 2017 16:12:43 +0100 Message-ID: To: Thomas Huth Cc: qemu-arm , QEMU Developers , "Edgar E. Iglesias" , Alistair Francis , KONRAD Frederic , QEMU Trivial Content-Type: text/plain; charset="UTF-8" X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:400c:c09::22d Subject: Re: [Qemu-arm] [PATCH] hw/misc/auxbus.c: Mark the aux-to-i2c-bridge device as non-hotpluggable X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 22 Aug 2017 15:13:10 -0000 On 22 August 2017 at 16:06, Thomas Huth wrote: > QEMU currently aborts if the user tries to do something like this: > > $ aarch64-softmmu/qemu-system-aarch64 -S -M integratorcp -nographic > QEMU 2.9.93 monitor - type 'help' for more information > (qemu) device_add aux-to-i2c-bridge,id=x > (qemu) device_del x > ** > ERROR:qemu/qdev-monitor.c:872:qdev_unplug: assertion failed: (hotplug_ctrl) > Aborted (core dumped) > > Looks like the device is not hot-pluggable, so let's mark it > accordingly. > > Signed-off-by: Thomas Huth > --- > hw/misc/auxbus.c | 8 ++++++++ > 1 file changed, 8 insertions(+) > > diff --git a/hw/misc/auxbus.c b/hw/misc/auxbus.c > index 8a90ddd..2c62515 100644 > --- a/hw/misc/auxbus.c > +++ b/hw/misc/auxbus.c > @@ -222,9 +222,17 @@ static inline I2CBus *aux_bridge_get_i2c_bus(AUXTOI2CState *bridge) > return bridge->i2c_bus; > } > > +static void aux_bridge_class_init(ObjectClass *oc, void *data) > +{ > + DeviceClass *dc = DEVICE_CLASS(oc); > + > + dc->hotpluggable = false; > +} Why is our default "hotpluggable" rather than "not hotpluggable" ? We must have way more non-hotpluggable devices than hotpluggable ones, and it takes active effort to make a hotpluggable device model, so it seems like it would be much less bug-prone to require hotpluggable devices to set dc->hotpluggable true rather than all the non-hotpluggable ones to set it false... thanks -- PMM From MAILER-DAEMON Tue Aug 22 11:14:19 2017 Received: from list by lists.gnu.org with archive (Exim 4.71) id 1dkAsk-0002wb-Vl for mharc-qemu-arm@gnu.org; Tue, 22 Aug 2017 11:14:19 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:55458) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dkAsg-0002rZ-AG for qemu-arm@nongnu.org; Tue, 22 Aug 2017 11:14:17 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dkAsd-0000Mp-Th for qemu-arm@nongnu.org; Tue, 22 Aug 2017 11:14:14 -0400 Received: from mail-he1eur01on0059.outbound.protection.outlook.com ([104.47.0.59]:58592 helo=EUR01-HE1-obe.outbound.protection.outlook.com) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1dkAsV-0000GN-Gr; Tue, 22 Aug 2017 11:14:04 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nxp.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version; bh=Cv7+ceP0hVICxIKgWZXjbYu1zFvBwMeajt0vbkEW2uA=; b=VbTPHz5vA9CyfClAc5bbpEH+nCaI94W8zCKTgO5IHOR7OkZR55lBmpJpnl53Fw6QF6jy34mfVpJZIPMA012Wjh3Xr2+uNB0FGorHidzvhMpHoYYGkXONgJ5G1Dj4j3qSVqJMZ1l/AN5xdW/B/MsO1Rksk+B6C/+8yspKmNiSAjc= Received: from AM3PR04MB0616.eurprd04.prod.outlook.com (10.255.133.15) by AM3PR04MB1412.eurprd04.prod.outlook.com (10.163.185.154) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384_P256) id 15.1.1362.18; Tue, 22 Aug 2017 15:13:58 +0000 Received: from AM3PR04MB0616.eurprd04.prod.outlook.com ([fe80::414d:bebc:b19d:3f35]) by AM3PR04MB0616.eurprd04.prod.outlook.com ([fe80::414d:bebc:b19d:3f35%13]) with mapi id 15.01.1362.019; Tue, 22 Aug 2017 15:13:57 +0000 From: Diana Madalina Craciun To: "Edgar E. Iglesias" CC: Auger Eric , "qemu-devel@nongnu.org" , "mst@redhat.com" , Mike Caraman , "qemu-arm@nongnu.org" , "marcel@redhat.com" , Bharat Bhushan , "christoffer.dall@linaro.org" , Laurentiu Tudor Thread-Topic: [Qemu-devel] [PATCH v2 2/2] Add a unique ID in the virt machine to be used as device ID Thread-Index: AQHS07WQhQaf1stp7kus9qldhP1WKg== Date: Tue, 22 Aug 2017 15:13:57 +0000 Message-ID: References: <1495537965-4187-1-git-send-email-diana.craciun@nxp.com> <1495537965-4187-3-git-send-email-diana.craciun@nxp.com> <20170731151602.GU4859@toto> <20170811155027.GO4859@toto> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: authentication-results: spf=none (sender IP is ) smtp.mailfrom=diana.craciun@nxp.com; x-originating-ip: [192.88.146.1] x-ms-publictraffictype: Email x-microsoft-exchange-diagnostics: 1; AM3PR04MB1412; 6:Y/+QIemQDERexlI5rePS7s8lIDNEXnhfan/RebBiyNkAIUopPZHdRrwL84eM9viLX4q8YJgpAGKub+tKHpazOkRvh8jnizxXCjGL+hTfQuMQ7HyNIlNr40le68suoJV1kcjpl3PbRY5HBKAKcprmE0OvrQImUNhgQVGYJEho8m+wvq7f4VryhQ3CGXYfI1NRusXx1pPZ7JpYFz/jPyC1bVRj2bMq57MXWtEQ0vp4JK9Buboc747hDR/D6OYOv5YL3P5Jh+xDSIibj03dbn/JcEyUmvuCWj/ROEpBy4APCMNkqySrOMV5znmWj7DbXJmwKYESs7bBEpYNVkE28FmiOA==; 5:RxEDY4GAiJZ5NzZd7VrmVpbZFPON6O1GbzTJHO95RNRz1vMUDQhXTRSOoQxfmoI4ZgTVh61OcT8pEXGnJTxAwZVOz3ru24U8V3vb6NjzpzXKzm8MEID/RXIuXiEsxn4hcbftjkx8oRmNUdrNeQ9NtQ==; 24:tnZQ0XYXmlrXYoJ5G5uBOC8ClKb++O7cgqp7vodVsma6/s4fV8jZ1z3g4n0C1lxY2d7s/eXPcUCjqNv0xpidHkRg4gX6EbGB2D1Vxc1ZIjY=; 7:C8kr49jDuHtQui32969rGxOUvi/7oLOQjMIgbSu6kQ687LoAxgc79z8iptoa47JqWXjK9xorjS0rFWOeHXSuxLXCM0206JdBwfyz93M0qa02pwVNbDfiq9gSLNZKJB0/fbJaTVM/cij2nJApxgUA89IhyUUGD7u0rnUtVwSU1VPn1c2Pr+DaqEp3sYLtnqYAPQry3QIqRVR8yg8vFfyK2b73YRJuWu8talXaVCZ525o= x-ms-exchange-antispam-srfa-diagnostics: SSOS;SSOR; x-forefront-antispam-report: SFV:SKI; SCL:-1; SFV:NSPM; SFS:(10009020)(6009001)(39860400002)(189002)(51444003)(199003)(377454003)(24454002)(3846002)(105586002)(106356001)(68736007)(102836003)(53546010)(66066001)(25786009)(14454004)(97736004)(86362001)(966005)(4326008)(6246003)(93886005)(33656002)(3660700001)(478600001)(6116002)(6306002)(9686003)(575784001)(99286003)(53936002)(53946003)(110136004)(39060400002)(54906002)(55016002)(189998001)(229853002)(8676002)(8936002)(81156014)(6916009)(81166006)(305945005)(50986999)(74316002)(76176999)(54356999)(7696004)(5660300001)(3280700002)(101416001)(2906002)(6436002)(5250100002)(2900100001)(551934003)(6506006)(7736002); DIR:OUT; SFP:1101; SCL:1; SRVR:AM3PR04MB1412; H:AM3PR04MB0616.eurprd04.prod.outlook.com; FPR:; SPF:None; PTR:InfoNoRecords; MX:1; A:1; LANG:en; x-ms-office365-filtering-correlation-id: 647c038d-a319-46e4-eaf5-08d4e9706965 x-ms-office365-filtering-ht: Tenant x-microsoft-antispam: UriScan:; BCL:0; PCL:0; RULEID:(300000500095)(300135000095)(300000501095)(300135300095)(22001)(300000502095)(300135100095)(2017030254152)(300000503095)(300135400095)(48565401081)(2017052603170)(201703131423075)(201703031133081)(201702281549075)(300000504095)(300135200095)(300000505095)(300135600095)(300000506095)(300135500095); SRVR:AM3PR04MB1412; x-ms-traffictypediagnostic: AM3PR04MB1412: x-exchange-antispam-report-test: UriScan:(166708455590820)(185117386973197); x-microsoft-antispam-prvs: x-exchange-antispam-report-cfa-test: BCL:0; PCL:0; RULEID:(100000700101)(100105000095)(100000701101)(100105300095)(100000702101)(100105100095)(6040450)(601004)(2401047)(8121501046)(5005006)(3002001)(93006095)(93001095)(100000703101)(100105400095)(10201501046)(6055026)(6041248)(20161123555025)(20161123558100)(20161123560025)(20161123564025)(20161123562025)(201703131423075)(201702281528075)(201703061421075)(201703061406153)(6072148)(201708071742011)(100000704101)(100105200095)(100000705101)(100105500095); SRVR:AM3PR04MB1412; BCL:0; PCL:0; RULEID:(100000800101)(100110000095)(100000801101)(100110300095)(100000802101)(100110100095)(100000803101)(100110400095)(100000804101)(100110200095)(100000805101)(100110500095); SRVR:AM3PR04MB1412; x-forefront-prvs: 04073E895A received-spf: None (protection.outlook.com: nxp.com does not designate permitted sender hosts) spamdiagnosticoutput: 1:99 spamdiagnosticmetadata: NSPM Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-originalarrivaltime: 22 Aug 2017 15:13:57.8103 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM3PR04MB1412 X-detected-operating-system: by eggs.gnu.org: Windows 7 or 8 [fuzzy] X-Received-From: 104.47.0.59 Subject: Re: [Qemu-arm] [Qemu-devel] [PATCH v2 2/2] Add a unique ID in the virt machine to be used as device ID X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 22 Aug 2017 15:14:17 -0000 On 08/11/2017 06:50 PM, Edgar E. Iglesias wrote:=0A= > On Fri, Aug 11, 2017 at 02:35:28PM +0000, Diana Madalina Craciun wrote:= =0A= >> Hi Edgar,=0A= >>=0A= >> On 07/31/2017 06:16 PM, Edgar E. Iglesias wrote:=0A= >>> On Wed, Jul 26, 2017 at 02:22:28PM +0200, Auger Eric wrote:=0A= >>>> Hi Diana,=0A= >>>> On 23/05/2017 13:12, Diana Craciun wrote:=0A= >>>>> Device IDs are required by the ARM GICv3 ITS for IRQ remapping.=0A= >>>>> Currently, for PCI devices, the requester ID was used as device=0A= >>>>> ID in the virt machine. If the system has multiple masters that=0A= >>>> if the system has multiple root complex?=0A= >>>>> use MSIs a unique ID accross the platform is needed.=0A= >>>> across=0A= >>>>> A static scheme is used and each master is allocated a range of IDs= =0A= >>>>> with the formula:=0A= >>>>> DeviceID =3D zero_extend( RequesterID[15:0] ) + 0x10000*Constant (as= =0A= >>>>> recommended by SBSA).=0A= >>>>>=0A= >>>>> This ID will be configured in the machine creation and if not configu= red=0A= >>>>> the PCI requester ID will be used insteead.=0A= >>>> instead=0A= >>>>> Signed-off-by: Diana Craciun =0A= >>>>> ---=0A= >>>>> hw/arm/virt.c | 26 ++++++++++++++++++++++++++=0A= >>>>> hw/pci-host/gpex.c | 6 ++++++=0A= >>>>> hw/pci/msi.c | 2 +-=0A= >>>>> hw/pci/pci.c | 25 +++++++++++++++++++++++++=0A= >>>>> include/hw/arm/virt.h | 1 +=0A= >>>>> include/hw/pci-host/gpex.h | 2 ++=0A= >>>>> include/hw/pci/pci.h | 8 ++++++++=0A= >>>>> kvm-all.c | 4 ++--=0A= >>>>> 8 files changed, 71 insertions(+), 3 deletions(-)=0A= >>>>>=0A= >>>>> diff --git a/hw/arm/virt.c b/hw/arm/virt.c=0A= >>>>> index 5f62a03..a969694 100644=0A= >>>>> --- a/hw/arm/virt.c=0A= >>>>> +++ b/hw/arm/virt.c=0A= >>>>> @@ -110,6 +110,8 @@ static ARMPlatformBusSystemParams platform_bus_pa= rams;=0A= >>>>> #define RAMLIMIT_GB 255=0A= >>>>> #define RAMLIMIT_BYTES (RAMLIMIT_GB * 1024ULL * 1024 * 1024)=0A= >>>>> =0A= >>>>> +#define STREAM_ID_RANGE_SIZE 0x10000=0A= >>>>> +=0A= >>>>> /* Addresses and sizes of our components.=0A= >>>>> * 0..128MB is space for a flash device so we can run bootrom code s= uch as UEFI.=0A= >>>>> * 128MB..256MB is used for miscellaneous device I/O.=0A= >>>>> @@ -162,6 +164,22 @@ static const int a15irqmap[] =3D {=0A= >>>>> [VIRT_PLATFORM_BUS] =3D 112, /* ...to 112 + PLATFORM_BUS_NUM_IRQ= S -1 */=0A= >>>>> };=0A= >>>>> =0A= >>>>> +/* Device IDs are required by the ARM GICV3 ITS for IRQ remapping. C= urrently=0A= >>>>> + * for PCI devices the requester ID was used as device ID. But if th= e system has=0A= >>>>> + * multiple masters that use MSIs, the requester ID may cause device= ID clashes.=0A= >>>>> + * So a unique number is needed accross the system.=0A= >>>>> + * We are using the following formula:=0A= >>>>> + * DeviceID =3D zero_extend( RequesterID[15:0] ) + 0x10000*Constant= =0A= >>>>> + * (as recommanded by SBSA). Currently we do not have an SMMU emulat= ion, but the=0A= >>>>> + * same formula can be used for the generation of the streamID as we= ll.=0A= >>>>> + * For each master the device ID will be derrived from the requester= ID using=0A= >>>>> + * the abovemntione formula.=0A= >>>>> + */=0A= >>>> I think most of this comment should only be in the commit message. typ= os=0A= >>>> in derived and above mentioned.=0A= >>>>=0A= >>>> stream id is the terminology for the id space at the input of the smmu= .=0A= >>>> device id is the terminology for the id space at the input of the msi= =0A= >>>> controller I think.=0A= >>>>=0A= >>>> RID -> deviceID (no IOMMU)=0A= >>>> RID -> streamID -> deviceID (IOMMU)=0A= >>>>=0A= >>>> I would personally get rid of all streamid uses as the smmu is not yet= =0A= >>>> supported and stick to the=0A= >>>> Documentation/devicetree/bindings/pci/pci-msi.txt terminology?=0A= >>>>=0A= >>>>> +=0A= >>>>> +static const uint32_t streamidmap[] =3D {=0A= >>>>> + [VIRT_PCIE] =3D 0, /* currently only one PCI controller = */=0A= >>>>> +};=0A= >>>>> +=0A= >>>>> static const char *valid_cpus[] =3D {=0A= >>>>> "cortex-a15",=0A= >>>>> "cortex-a53",=0A= >>>>> @@ -980,6 +998,7 @@ static void create_pcie(const VirtMachineState *v= ms, qemu_irq *pic)=0A= >>>>> hwaddr base_ecam =3D vms->memmap[VIRT_PCIE_ECAM].base;=0A= >>>>> hwaddr size_ecam =3D vms->memmap[VIRT_PCIE_ECAM].size;=0A= >>>>> hwaddr base =3D base_mmio;=0A= >>>>> + uint32_t stream_id =3D vms->streamidmap[VIRT_PCIE] * STREAM_ID_R= ANGE_SIZE;=0A= >>>> msi-base?=0A= >>>> STREAM_ID_RANGE_SIZE ~ MSI_MAP_LENGTH?=0A= >>>>> int nr_pcie_buses =3D size_ecam / PCIE_MMCFG_SIZE_MIN;=0A= >>>>> int irq =3D vms->irqmap[VIRT_PCIE];=0A= >>>>> MemoryRegion *mmio_alias;=0A= >>>>> @@ -992,6 +1011,7 @@ static void create_pcie(const VirtMachineState *= vms, qemu_irq *pic)=0A= >>>>> PCIHostState *pci;=0A= >>>>> =0A= >>>>> dev =3D qdev_create(NULL, TYPE_GPEX_HOST);=0A= >>>>> + qdev_prop_set_uint32(dev, "stream-id-base", stream_id);=0A= >>>>> qdev_init_nofail(dev);=0A= >>>>> =0A= >>>>> /* Map only the first size_ecam bytes of ECAM space */=0A= >>>>> @@ -1056,6 +1076,11 @@ static void create_pcie(const VirtMachineState= *vms, qemu_irq *pic)=0A= >>>>> if (vms->msi_phandle) {=0A= >>>>> qemu_fdt_setprop_cells(vms->fdt, nodename, "msi-parent",=0A= >>>>> vms->msi_phandle);=0A= >>>>> + qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "msi-map",= =0A= >>>>> + 1, 0,=0A= >>>>> + 1, vms->msi_phandle,=0A= >>>>> + 1, stream_id,=0A= >>>>> + 1, STREAM_ID_RANGE_SIZE);=0A= >>>>> }=0A= >>>>> =0A= >>>>> qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg",=0A= >>>>> @@ -1609,6 +1634,7 @@ static void virt_2_9_instance_init(Object *obj)= =0A= >>>>> =0A= >>>>> vms->memmap =3D a15memmap;=0A= >>>>> vms->irqmap =3D a15irqmap;=0A= >>>>> + vms->streamidmap =3D streamidmap;=0A= >>>>> }=0A= >>>>> =0A= >>>>> static void virt_machine_2_9_options(MachineClass *mc)=0A= >>>>> diff --git a/hw/pci-host/gpex.c b/hw/pci-host/gpex.c=0A= >>>>> index 66055ee..de72408 100644=0A= >>>>> --- a/hw/pci-host/gpex.c=0A= >>>>> +++ b/hw/pci-host/gpex.c=0A= >>>>> @@ -43,6 +43,11 @@ static void gpex_set_irq(void *opaque, int irq_num= , int level)=0A= >>>>> qemu_set_irq(s->irq[irq_num], level);=0A= >>>>> }=0A= >>>>> =0A= >>>>> +static Property gpex_props[] =3D {=0A= >>>>> + DEFINE_PROP_UINT32("stream-id-base", GPEXHost, stream_id_base, 0= ),=0A= >>>> msi_base_base=0A= >>>>> + DEFINE_PROP_END_OF_LIST(),=0A= >>>>> +};=0A= >>>>> +=0A= >>>>> static void gpex_host_realize(DeviceState *dev, Error **errp)=0A= >>>>> {=0A= >>>>> PCIHostState *pci =3D PCI_HOST_BRIDGE(dev);=0A= >>>>> @@ -83,6 +88,7 @@ static void gpex_host_class_init(ObjectClass *klass= , void *data)=0A= >>>>> =0A= >>>>> hc->root_bus_path =3D gpex_host_root_bus_path;=0A= >>>>> dc->realize =3D gpex_host_realize;=0A= >>>>> + dc->props =3D gpex_props;=0A= >>>>> set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories);=0A= >>>>> dc->fw_name =3D "pci";=0A= >>>>> }=0A= >>>>> diff --git a/hw/pci/msi.c b/hw/pci/msi.c=0A= >>>>> index 7925851..b60a410 100644=0A= >>>>> --- a/hw/pci/msi.c=0A= >>>>> +++ b/hw/pci/msi.c=0A= >>>>> @@ -336,7 +336,7 @@ void msi_send_message(PCIDevice *dev, MSIMessage = msg)=0A= >>>>> {=0A= >>>>> MemTxAttrs attrs =3D {};=0A= >>>>> =0A= >>>>> - attrs.stream_id =3D pci_requester_id(dev);=0A= >>>>> + attrs.stream_id =3D pci_stream_id(dev);=0A= >>>>> address_space_stl_le(&dev->bus_master_as, msg.address, msg.data,= =0A= >>>>> attrs, NULL);=0A= >>>>> }=0A= >>>>> diff --git a/hw/pci/pci.c b/hw/pci/pci.c=0A= >>>>> index 259483b..92e9a2b 100644=0A= >>>>> --- a/hw/pci/pci.c=0A= >>>>> +++ b/hw/pci/pci.c=0A= >>>>> @@ -951,6 +951,30 @@ uint16_t pci_requester_id(PCIDevice *dev)=0A= >>>>> return pci_req_id_cache_extract(&dev->requester_id_cache);=0A= >>>>> }=0A= >>>>> =0A= >>>>> +static uint32_t pci_get_stream_id_base(PCIDevice *dev)=0A= >>>>> +{=0A= >>>>> + PCIBus *rootbus =3D pci_device_root_bus(dev);=0A= >>>>> + PCIHostState *host_bridge =3D PCI_HOST_BRIDGE(rootbus->qbus.pare= nt);=0A= >>>>> + Error *err =3D NULL;=0A= >>>>> + int64_t stream_id;=0A= >>>>> +=0A= >>>>> + stream_id =3D object_property_get_int(OBJECT(host_bridge), "stre= am-id-base",=0A= >>>>> + &err);=0A= >>>>> + if (stream_id < 0) {=0A= >>>>> + stream_id =3D 0;=0A= >>>>> + }=0A= >>>>> +=0A= >>>>> + return stream_id;=0A= >>>>> +}=0A= >>>>> +=0A= >>>>> +uint32_t pci_stream_id(PCIDevice *dev)=0A= >>>>> +{=0A= >>>>> + /* Stream ID =3D RequesterID[15:0] + stream_id_base. stream_id_b= ase may=0A= >>>>> + * be 0 for devices that are not using any translation between r= equester_id=0A= >>>>> + * and stream_id */=0A= >>>>> + return (uint16_t)pci_requester_id(dev) + dev->stream_id_base;= =0A= >>>>> +}=0A= >>>> I think you should split the changes in virt from pci/gpex generic cha= nges.=0A= >>>>=0A= >>>>> +=0A= >>>>> /* -1 for devfn means auto assign */=0A= >>>>> static PCIDevice *do_pci_register_device(PCIDevice *pci_dev, PCIBus = *bus,=0A= >>>>> const char *name, int devfn= ,=0A= >>>>> @@ -1000,6 +1024,7 @@ static PCIDevice *do_pci_register_device(PCIDev= ice *pci_dev, PCIBus *bus,=0A= >>>>> =0A= >>>>> pci_dev->devfn =3D devfn;=0A= >>>>> pci_dev->requester_id_cache =3D pci_req_id_cache_get(pci_dev);= =0A= >>>>> + pci_dev->stream_id_base =3D pci_get_stream_id_base(pci_dev);=0A= >>>> looks strange to me to store the rid base in the end point as this is= =0A= >>>> rather a property of the PCI complex. I acknowledge this is much more= =0A= >>> I agree.=0A= >> The reason I have changed was to avoid traversing the entire hierarchy= =0A= >> each time the ID is needed (for example each time when a MSI is sent).= =0A= >>=0A= >>> I think that what we need is to add support for allowing PCI RCs=0A= >>> to transform requesterIDs in transactions attributes according to the= =0A= >>> implementation specifics.=0A= >> Do you mean that you need more than a linear offset between requesterID= =0A= >> and whatever other ID?=0A= >=0A= > Yes.=0A= >=0A= > This is my understanding for the ARM platforms I'm familiar with:=0A= >=0A= > Since AXI busses don't have a defined way to carry Master IDs, these=0A= > are typically carried on the AXI user signals. I'll just refer to=0A= > these signals as AXI Master IDs.=0A= >=0A= > 1. An endpoint issues an MSI (or any) transaction on the PCI bus.=0A= > In QEMU, these trasactions carry the requester ID in their attributes.= =0A= >=0A= > 2. The transaction hits the PCI "host" bridge to the SoC internal=0A= > interconnect (typically AXI). This bridge needs to forward the=0A= > PCI transaction onto the AXI bus. Including mapping the PCI=0A= > RequesterID into an AXI MasterID.=0A= >=0A= > 3. The AXI transaction hits the IOMMU and the MasterID is mapped=0A= > into a streamID to identify the origin of the transaction=0A= > and apply address translation accordingly. If the SMMU=0A= > allows the transaction to pass, the stream ID is mapped back=0A= > into the transactions MasterID.=0A= >=0A= > 4. The AXI transaction continues down the interconnect and hits=0A= > the MSI doorbell and the MasterID is mapped into a DeviceID to=0A= > identify the origin of the MSI and apply possible interrupt translatio= n.=0A= >=0A= > Adding streamID fields to a PCI endpoint doesn't make any sense to me.=0A= > The requester ID is already there and is IMO enough.=0A= > StreamIDs are a concept of ARM System MMUs, not of PCI endpoints.=0A= =0A= What I have added into the endpoint is actually the Master ID (in QEMU=0A= it is actually equal with the streamID). I agree that this is a property=0A= of the root complex, the only reason I have put it into the endpoint was=0A= to avoid traversing the PCI hierarchy each time an MSI is sent.=0A= =0A= >=0A= > When modelling #2, hardcoding a specific linear mapping between=0A= > PCI requester IDs and AXI Master IDs may work for one platform=0A= > but it won't work for all platforms. There is no one mapping for all.=0A= > It can even be run-time programmable in the bridge.=0A= =0A= One solution might be defining a function in the generic host bridge=0A= which by default returns the requesterIDs (assumes that requesterID is=0A= the same with the masterID). This function can be over overridden by=0A= each specific implementation.=0A= =0A= >=0A= > IIRC, the SMMUv3 docs have a section that suggest how these ReqID to AXI = Master ID mappings can be done.=0A= =0A= I did not find the specific section, just that the streamID should be=0A= derived from requesterID.=0A= =0A= =0A= Thanks,=0A= =0A= Diana=0A= =0A= =0A= >=0A= >=0A= >>> The way we did it when modelling the ZynqMP is by adding support for=0A= >>> transaction attribute translation in QEMU's IOMMU interface.=0A= >>> In our PCI RC, we have an IOMMU covering the entire AS that PCI devs DM= A into.=0A= >>> This IOMMU doesn't do address-translation, only RequesterID -> StreamID= =0A= >>> transforms according to how the ZynqMP PCI RC derives StreamIDs from Re= questerIDs.=0A= >> Are there any patches for this support in order for me to better underst= and?=0A= > It's currently on the Xilinx QEMU fork on GitHub.=0A= > https://github.com/Xilinx/qemu/blob/master/hw/pci-host/xlnx-nwl-pcie-main= .c=0A= >=0A= > In the current ZynqMP, all RequesterIDs map to a single MasterID (it's a = HW limitation).=0A= > In future versions of the HW, another mapping will be used.=0A= > I can't share code for the latter yet though....=0A= >=0A= > Best regards,=0A= > Edgar=0A= >=0A= > =0A= >=0A= >> Thanks,=0A= >>=0A= >> Diana=0A= >>=0A= >>=0A= >>> This is useful not only to model PCI RequesterID to AXI Master ID mappi= ngs but=0A= >>> also for modelling things like the ARM TZC (or the Xilinx ZynqMP XMPU/X= PPUs).=0A= >>>=0A= >>> Cheers,=0A= >>> Edgar=0A= >>>=0A= >>>=0A= >>>> simple than reworking pci_requester_id() though.=0A= >>>>> =0A= >>>>> memory_region_init(&pci_dev->bus_master_container_region, OBJECT= (pci_dev),=0A= >>>>> "bus master container", UINT64_MAX);=0A= >>>>> diff --git a/include/hw/arm/virt.h b/include/hw/arm/virt.h=0A= >>>>> index 33b0ff3..94c007a 100644=0A= >>>>> --- a/include/hw/arm/virt.h=0A= >>>>> +++ b/include/hw/arm/virt.h=0A= >>>>> @@ -99,6 +99,7 @@ typedef struct {=0A= >>>>> struct arm_boot_info bootinfo;=0A= >>>>> const MemMapEntry *memmap;=0A= >>>>> const int *irqmap;=0A= >>>>> + const uint32_t *streamidmap;=0A= >>>>> int smp_cpus;=0A= >>>>> void *fdt;=0A= >>>>> int fdt_size;=0A= >>>>> diff --git a/include/hw/pci-host/gpex.h b/include/hw/pci-host/gpex.h= =0A= >>>>> index 68c9348..47df01a 100644=0A= >>>>> --- a/include/hw/pci-host/gpex.h=0A= >>>>> +++ b/include/hw/pci-host/gpex.h=0A= >>>>> @@ -48,6 +48,8 @@ typedef struct GPEXHost {=0A= >>>>> =0A= >>>>> GPEXRootState gpex_root;=0A= >>>>> =0A= >>>>> + uint32_t stream_id_base;=0A= >>>>> +=0A= >>>>> MemoryRegion io_ioport;=0A= >>>>> MemoryRegion io_mmio;=0A= >>>>> qemu_irq irq[GPEX_NUM_IRQS];=0A= >>>>> diff --git a/include/hw/pci/pci.h b/include/hw/pci/pci.h=0A= >>>>> index a37a2d5..e6e9334 100644=0A= >>>>> --- a/include/hw/pci/pci.h=0A= >>>>> +++ b/include/hw/pci/pci.h=0A= >>>>> @@ -283,6 +283,12 @@ struct PCIDevice {=0A= >>>>> * MSI). For conventional PCI root complex, this field is=0A= >>>>> * meaningless. */=0A= >>>>> PCIReqIDCache requester_id_cache;=0A= >>>>> + /* Some platforms need a unique ID for IOMMU source identificati= on=0A= >>>>> + * or MSI source identification. QEMU implements a simple scheme= :=0A= >>>>> + * stream_id =3D stream_id_base + requester_id. The stream_id_b= ase will=0A= >>>>> + * ensure that all the devices in the system have different stre= am ID=0A= >>>>> + * domains */=0A= >>>>> + uint32_t stream_id_base;=0A= >>>> get rid of IOMMU terminology?=0A= >>>>=0A= >>>> Note that when adding other sub-systems you will need to address the= =0A= >>>> ACPI side as the IORT table built by hw/arm/virt-acpi-build.c currentl= y=0A= >>>> defines an RID mapping for the single root complex.=0A= >>>>=0A= >>>> Thanks=0A= >>>>=0A= >>>> Eric=0A= >>>>> char name[64];=0A= >>>>> PCIIORegion io_regions[PCI_NUM_REGIONS];=0A= >>>>> AddressSpace bus_master_as;=0A= >>>>> @@ -737,6 +743,8 @@ static inline uint16_t pci_get_bdf(PCIDevice *dev= )=0A= >>>>> =0A= >>>>> uint16_t pci_requester_id(PCIDevice *dev);=0A= >>>>> =0A= >>>>> +uint32_t pci_stream_id(PCIDevice *dev);=0A= >>>>> +=0A= >>>>> /* DMA access functions */=0A= >>>>> static inline AddressSpace *pci_get_address_space(PCIDevice *dev)=0A= >>>>> {=0A= >>>>> diff --git a/kvm-all.c b/kvm-all.c=0A= >>>>> index 90b8573..5a508c3 100644=0A= >>>>> --- a/kvm-all.c=0A= >>>>> +++ b/kvm-all.c=0A= >>>>> @@ -1280,7 +1280,7 @@ int kvm_irqchip_add_msi_route(KVMState *s, int = vector, PCIDevice *dev)=0A= >>>>> kroute.u.msi.data =3D le32_to_cpu(msg.data);=0A= >>>>> if (kvm_msi_devid_required()) {=0A= >>>>> kroute.flags =3D KVM_MSI_VALID_DEVID;=0A= >>>>> - kroute.u.msi.devid =3D pci_requester_id(dev);=0A= >>>>> + kroute.u.msi.devid =3D pci_stream_id(dev);=0A= >>>>> }=0A= >>>>> if (kvm_arch_fixup_msi_route(&kroute, msg.address, msg.data, dev= )) {=0A= >>>>> kvm_irqchip_release_virq(s, virq);=0A= >>>>> @@ -1317,7 +1317,7 @@ int kvm_irqchip_update_msi_route(KVMState *s, i= nt virq, MSIMessage msg,=0A= >>>>> kroute.u.msi.data =3D le32_to_cpu(msg.data);=0A= >>>>> if (kvm_msi_devid_required()) {=0A= >>>>> kroute.flags =3D KVM_MSI_VALID_DEVID;=0A= >>>>> - kroute.u.msi.devid =3D pci_requester_id(dev);=0A= >>>>> + kroute.u.msi.devid =3D pci_stream_id(dev);=0A= >>>>> }=0A= >>>>> if (kvm_arch_fixup_msi_route(&kroute, msg.address, msg.data, dev= )) {=0A= >>>>> return -EINVAL;=0A= >>>>>=0A= =0A= From MAILER-DAEMON Tue Aug 22 11:26:25 2017 Received: from list by lists.gnu.org with archive (Exim 4.71) id 1dkB4T-0004hn-56 for mharc-qemu-arm@gnu.org; Tue, 22 Aug 2017 11:26:25 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:59039) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dkB4O-0004eu-Ah for qemu-arm@nongnu.org; Tue, 22 Aug 2017 11:26:24 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dkB4K-0000uI-9O for qemu-arm@nongnu.org; Tue, 22 Aug 2017 11:26:20 -0400 Received: from mx1.redhat.com ([209.132.183.28]:45374) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1dkB4K-0000tl-0t; Tue, 22 Aug 2017 11:26:16 -0400 Received: from smtp.corp.redhat.com (int-mx06.intmail.prod.int.phx2.redhat.com [10.5.11.16]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id CE2697EA8D; Tue, 22 Aug 2017 15:26:14 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mx1.redhat.com CE2697EA8D Authentication-Results: ext-mx04.extmail.prod.ext.phx2.redhat.com; dmarc=none (p=none dis=none) header.from=redhat.com Authentication-Results: ext-mx04.extmail.prod.ext.phx2.redhat.com; spf=fail smtp.mailfrom=thuth@redhat.com Received: from [10.36.116.21] (ovpn-116-21.ams2.redhat.com [10.36.116.21]) by smtp.corp.redhat.com (Postfix) with ESMTPS id BBAF61715B; Tue, 22 Aug 2017 15:26:12 +0000 (UTC) To: Peter Maydell Cc: qemu-arm , QEMU Developers , "Edgar E. Iglesias" , Alistair Francis , KONRAD Frederic , QEMU Trivial , Markus Armbruster , Eduardo Habkost References: <1503414375-21009-1-git-send-email-thuth@redhat.com> From: Thomas Huth Message-ID: <443135b4-4b36-bae6-b50a-12fb4a55a858@redhat.com> Date: Tue, 22 Aug 2017 17:26:11 +0200 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.2.0 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=utf-8 Content-Language: en-US X-Scanned-By: MIMEDefang 2.79 on 10.5.11.16 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.28]); Tue, 22 Aug 2017 15:26:15 +0000 (UTC) Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.132.183.28 Subject: Re: [Qemu-arm] [PATCH] hw/misc/auxbus.c: Mark the aux-to-i2c-bridge device as non-hotpluggable X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 22 Aug 2017 15:26:24 -0000 On 22.08.2017 17:12, Peter Maydell wrote: > On 22 August 2017 at 16:06, Thomas Huth wrote: >> QEMU currently aborts if the user tries to do something like this: >> >> $ aarch64-softmmu/qemu-system-aarch64 -S -M integratorcp -nographic >> QEMU 2.9.93 monitor - type 'help' for more information >> (qemu) device_add aux-to-i2c-bridge,id=3Dx >> (qemu) device_del x >> ** >> ERROR:qemu/qdev-monitor.c:872:qdev_unplug: assertion failed: (hotplug_= ctrl) >> Aborted (core dumped) >> >> Looks like the device is not hot-pluggable, so let's mark it >> accordingly. >> >> Signed-off-by: Thomas Huth >> --- >> hw/misc/auxbus.c | 8 ++++++++ >> 1 file changed, 8 insertions(+) >> >> diff --git a/hw/misc/auxbus.c b/hw/misc/auxbus.c >> index 8a90ddd..2c62515 100644 >> --- a/hw/misc/auxbus.c >> +++ b/hw/misc/auxbus.c >> @@ -222,9 +222,17 @@ static inline I2CBus *aux_bridge_get_i2c_bus(AUXT= OI2CState *bridge) >> return bridge->i2c_bus; >> } >> >> +static void aux_bridge_class_init(ObjectClass *oc, void *data) >> +{ >> + DeviceClass *dc =3D DEVICE_CLASS(oc); >> + >> + dc->hotpluggable =3D false; >> +} >=20 > Why is our default "hotpluggable" rather than "not hotpluggable" ? > We must have way more non-hotpluggable devices than hotpluggable > ones, and it takes active effort to make a hotpluggable device > model, so it seems like it would be much less bug-prone to > require hotpluggable devices to set dc->hotpluggable true > rather than all the non-hotpluggable ones to set it false... I think most devices are already non-hotpluggable automatically because they sit on a bus that is not hot-pluggable (e.g. sysbus devices). The problematic ones are the devices with .parent =3D TYPE_DEVICE. And for these, I think it is quite hard to say whether they should be hot-pluggable by default or not? Anyway, according to my tests (I'm currently working on a test that automatically does device_add + device_del for all devices, as you might have guessed already), there are not that many devices that cause problems here, so I guess marking some few with hotpluggable =3D false should be OK? Thomas From MAILER-DAEMON Tue Aug 22 11:30:51 2017 Received: from list by lists.gnu.org with archive (Exim 4.71) id 1dkB8l-0008VX-CR for mharc-qemu-arm@gnu.org; Tue, 22 Aug 2017 11:30:51 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:60167) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dkB8h-0008QY-Ur for qemu-arm@nongnu.org; Tue, 22 Aug 2017 11:30:48 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dkB8g-0003TF-94 for qemu-arm@nongnu.org; Tue, 22 Aug 2017 11:30:47 -0400 Received: from mail-wr0-x234.google.com ([2a00:1450:400c:c0c::234]:33364) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1dkB8g-0003Se-2V for qemu-arm@nongnu.org; Tue, 22 Aug 2017 11:30:46 -0400 Received: by mail-wr0-x234.google.com with SMTP id a47so14345764wra.0 for ; Tue, 22 Aug 2017 08:30:45 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:in-reply-to:references:from:date:message-id:subject:to :cc; bh=K689UJ20caYraXmMmfDxf9wN8+vASUJEbWGNufvR6Xw=; b=AHu+XPlTpEUu+3CKIhB8x93ocMFtRZ1JRsO3eggImBkOdwyerUjRbVw3O4GJEVFsyN YPf+t6nlzqrQeL5IpYOraQcjC2OLMzDiV7y1byjLc1ZYhTTtkT6RpccPe9W912wHBLLp 9vbCvFSBWGAR9Gjg59waxoG3amkEoCBjovTmg= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:in-reply-to:references:from:date :message-id:subject:to:cc; bh=K689UJ20caYraXmMmfDxf9wN8+vASUJEbWGNufvR6Xw=; b=RLAQkEi9nGEkUOz44XUiNgbr1KBDj5/fraMySju7vkeGMlTkM1frfX/jffpp3vf5Rk zF4jqn6+gAQX9nF7Ws/2oBEZ7yEidMp4fpflYEITptowiWEoZLlG0+BRndT7uepwIzLx qAo/A87s7qrNqb5A7rjc7ywyl4m1cGjA4Wc7zyQQRnhos2RnxZzJ7QoI6B3TqZEv+DWg Q2MFOKWPyBBEL7AS3Kv6eIxdusoK2LIcy7zlhHGUr93wc2vds6V2K+d7RD2lab5T//Ji aSMxra7Dke3Czohy5jU/G6Qqu8FogFzfkvdnAntSnyBHaTJ8fllgdZkw13tP/OBrGjNS 7McA== X-Gm-Message-State: AHYfb5imsy1mXfrkF6HjQAprzilAbObg5C6RiZvS5BIutWbmmfwFGWuc U1tBdQKh83qci1BWGn7k1kpkQfMP4D9l X-Received: by 10.223.167.138 with SMTP id j10mr682990wrc.97.1503415844860; Tue, 22 Aug 2017 08:30:44 -0700 (PDT) MIME-Version: 1.0 Received: by 10.223.134.54 with HTTP; Tue, 22 Aug 2017 08:30:24 -0700 (PDT) In-Reply-To: <443135b4-4b36-bae6-b50a-12fb4a55a858@redhat.com> References: <1503414375-21009-1-git-send-email-thuth@redhat.com> <443135b4-4b36-bae6-b50a-12fb4a55a858@redhat.com> From: Peter Maydell Date: Tue, 22 Aug 2017 16:30:24 +0100 Message-ID: To: Thomas Huth Cc: qemu-arm , QEMU Developers , "Edgar E. Iglesias" , Alistair Francis , KONRAD Frederic , QEMU Trivial , Markus Armbruster , Eduardo Habkost Content-Type: text/plain; charset="UTF-8" X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:400c:c0c::234 Subject: Re: [Qemu-arm] [PATCH] hw/misc/auxbus.c: Mark the aux-to-i2c-bridge device as non-hotpluggable X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 22 Aug 2017 15:30:49 -0000 On 22 August 2017 at 16:26, Thomas Huth wrote: > On 22.08.2017 17:12, Peter Maydell wrote: >> Why is our default "hotpluggable" rather than "not hotpluggable" ? >> We must have way more non-hotpluggable devices than hotpluggable >> ones, and it takes active effort to make a hotpluggable device >> model, so it seems like it would be much less bug-prone to >> require hotpluggable devices to set dc->hotpluggable true >> rather than all the non-hotpluggable ones to set it false... > > I think most devices are already non-hotpluggable automatically because > they sit on a bus that is not hot-pluggable (e.g. sysbus devices). The > problematic ones are the devices with .parent = TYPE_DEVICE. And for > these, I think it is quite hard to say whether they should be > hot-pluggable by default or not? To implement hotplug you need to write extra code (notably some kind of unrealize method to undo whatever you did in realize), at which point also setting the hotpluggable flag is trivial. > Anyway, according to my tests (I'm currently working on a test that > automatically does device_add + device_del for all devices, as you might > have guessed already), there are not that many devices that cause > problems here, so I guess marking some few with hotpluggable = false > should be OK? The problem is not the devices we have today but the ones we're going to write tomorrow. Having hotpluggable default to false "fails safe" -- the worst that happens is that somebody writing a hotpluggable device finds in their testing that they need to set the flag to make it work. Having it default to true fails non-safely -- as you've found, people writing devices that were never expected to be hotplugged don't try to test the error case of attempting hotplug anyway, and in code review the absence of a line of code is very hard to reliably spot, so we get devices in tree that crash QEMU if you try to hotplug them. If we make the default be not-hotpluggable we fix this not just today but forever. thanks -- PMM From MAILER-DAEMON Tue Aug 22 11:43:11 2017 Received: from list by lists.gnu.org with archive (Exim 4.71) id 1dkBKh-0004Dg-FY for mharc-qemu-arm@gnu.org; Tue, 22 Aug 2017 11:43:11 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:35631) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dkBKe-0004Ao-Fx for qemu-arm@nongnu.org; Tue, 22 Aug 2017 11:43:09 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dkBKb-0003JQ-A1 for qemu-arm@nongnu.org; Tue, 22 Aug 2017 11:43:08 -0400 Received: from mx1.redhat.com ([209.132.183.28]:34886) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1dkBKb-0003Iu-0e; Tue, 22 Aug 2017 11:43:05 -0400 Received: from smtp.corp.redhat.com (int-mx01.intmail.prod.int.phx2.redhat.com [10.5.11.11]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id AD3D368C2; Tue, 22 Aug 2017 15:43:03 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mx1.redhat.com AD3D368C2 Authentication-Results: ext-mx09.extmail.prod.ext.phx2.redhat.com; dmarc=none (p=none dis=none) header.from=redhat.com Authentication-Results: ext-mx09.extmail.prod.ext.phx2.redhat.com; spf=fail smtp.mailfrom=thuth@redhat.com Received: from [10.36.116.21] (ovpn-116-21.ams2.redhat.com [10.36.116.21]) by smtp.corp.redhat.com (Postfix) with ESMTPS id 4D2B85C6DC; Tue, 22 Aug 2017 15:43:01 +0000 (UTC) To: Peter Maydell Cc: qemu-arm , QEMU Developers , "Edgar E. Iglesias" , Alistair Francis , KONRAD Frederic , QEMU Trivial , Markus Armbruster , Eduardo Habkost References: <1503414375-21009-1-git-send-email-thuth@redhat.com> <443135b4-4b36-bae6-b50a-12fb4a55a858@redhat.com> From: Thomas Huth Message-ID: <06c16109-cdd2-0732-176d-6ec80b1f7f4e@redhat.com> Date: Tue, 22 Aug 2017 17:42:59 +0200 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.2.0 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 7bit X-Scanned-By: MIMEDefang 2.79 on 10.5.11.11 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.38]); Tue, 22 Aug 2017 15:43:03 +0000 (UTC) X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.132.183.28 Subject: Re: [Qemu-arm] [PATCH] hw/misc/auxbus.c: Mark the aux-to-i2c-bridge device as non-hotpluggable X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 22 Aug 2017 15:43:09 -0000 On 22.08.2017 17:30, Peter Maydell wrote: > On 22 August 2017 at 16:26, Thomas Huth wrote: >> On 22.08.2017 17:12, Peter Maydell wrote: >>> Why is our default "hotpluggable" rather than "not hotpluggable" ? >>> We must have way more non-hotpluggable devices than hotpluggable >>> ones, and it takes active effort to make a hotpluggable device >>> model, so it seems like it would be much less bug-prone to >>> require hotpluggable devices to set dc->hotpluggable true >>> rather than all the non-hotpluggable ones to set it false... >> >> I think most devices are already non-hotpluggable automatically because >> they sit on a bus that is not hot-pluggable (e.g. sysbus devices). The >> problematic ones are the devices with .parent = TYPE_DEVICE. And for >> these, I think it is quite hard to say whether they should be >> hot-pluggable by default or not? > > To implement hotplug you need to write extra code (notably some > kind of unrealize method to undo whatever you did in realize), > at which point also setting the hotpluggable flag is trivial. > >> Anyway, according to my tests (I'm currently working on a test that >> automatically does device_add + device_del for all devices, as you might >> have guessed already), there are not that many devices that cause >> problems here, so I guess marking some few with hotpluggable = false >> should be OK? > > The problem is not the devices we have today but the ones we're > going to write tomorrow. Having hotpluggable default to false > "fails safe" -- the worst that happens is that somebody writing > a hotpluggable device finds in their testing that they need to > set the flag to make it work. Having it default to true fails > non-safely -- as you've found, people writing devices that > were never expected to be hotplugged don't try to test the > error case of attempting hotplug anyway, and in code review > the absence of a line of code is very hard to reliably spot, > so we get devices in tree that crash QEMU if you try to > hotplug them. If we make the default be not-hotpluggable > we fix this not just today but forever. OK, you've got a point. I'll ponder about this a little bit and will try to come up with a patch / some patches ... Thomas From MAILER-DAEMON Tue Aug 22 11:46:40 2017 Received: from list by lists.gnu.org with archive (Exim 4.71) id 1dkBO3-0007If-6b for mharc-qemu-arm@gnu.org; Tue, 22 Aug 2017 11:46:39 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:36742) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dkBO0-0007HX-Hm for qemu-arm@nongnu.org; Tue, 22 Aug 2017 11:46:37 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dkBNx-0005bw-Cu for qemu-arm@nongnu.org; Tue, 22 Aug 2017 11:46:36 -0400 Received: from mx1.redhat.com ([209.132.183.28]:56910) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1dkBNx-0005bW-6X; Tue, 22 Aug 2017 11:46:33 -0400 Received: from smtp.corp.redhat.com (int-mx04.intmail.prod.int.phx2.redhat.com [10.5.11.14]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id 1995981DFC; Tue, 22 Aug 2017 15:46:32 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mx1.redhat.com 1995981DFC Authentication-Results: ext-mx01.extmail.prod.ext.phx2.redhat.com; dmarc=none (p=none dis=none) header.from=redhat.com Authentication-Results: ext-mx01.extmail.prod.ext.phx2.redhat.com; spf=fail smtp.mailfrom=thuth@redhat.com Received: from thh440s.redhat.com (ovpn-116-21.ams2.redhat.com [10.36.116.21]) by smtp.corp.redhat.com (Postfix) with ESMTP id 956075D724; Tue, 22 Aug 2017 15:46:30 +0000 (UTC) From: Thomas Huth To: Peter Maydell , qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Eduardo Habkost , Beniamino Galvani Date: Tue, 22 Aug 2017 17:46:29 +0200 Message-Id: <1503416789-32080-1-git-send-email-thuth@redhat.com> X-Scanned-By: MIMEDefang 2.79 on 10.5.11.14 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.25]); Tue, 22 Aug 2017 15:46:32 +0000 (UTC) X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.132.183.28 Subject: [Qemu-arm] [PATCH] hw/arm/allwinner-a10: Mark the allwinner-a10 device with user_creatable = false X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 22 Aug 2017 15:46:38 -0000 QEMU currently exits unexpectedly when the user accidentially tries to do something like this: $ aarch64-softmmu/qemu-system-aarch64 -S -M integratorcp -nographic QEMU 2.9.93 monitor - type 'help' for more information (qemu) device_add allwinner-a10 Unsupported NIC model: smc91c111 Exiting just due to a "device_add" should not happen. Looking closer at the the realize and instance_init function of this device also reveals that it is using serial_hds and nd_table directly there, so this device is clearly not creatable by the user and should be marked accordingly. Signed-off-by: Thomas Huth --- hw/arm/allwinner-a10.c | 2 ++ scripts/device-crash-test | 1 - 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/hw/arm/allwinner-a10.c b/hw/arm/allwinner-a10.c index f62a9a3..43a3f01 100644 --- a/hw/arm/allwinner-a10.c +++ b/hw/arm/allwinner-a10.c @@ -118,6 +118,8 @@ static void aw_a10_class_init(ObjectClass *oc, void *data) DeviceClass *dc = DEVICE_CLASS(oc); dc->realize = aw_a10_realize; + /* Reason: Uses serial_hds in realize and nd_table in instance_init */ + dc->user_creatable = false; } static const TypeInfo aw_a10_type_info = { diff --git a/scripts/device-crash-test b/scripts/device-crash-test index 8eb2d02..74aee68 100755 --- a/scripts/device-crash-test +++ b/scripts/device-crash-test @@ -187,7 +187,6 @@ ERROR_WHITELIST = [ {'log':r"Device [\w.,-]+ can not be dynamically instantiated"}, {'log':r"Platform Bus: Can not fit MMIO region of size "}, # other more specific errors we will ignore: - {'device':'allwinner-a10', 'log':"Unsupported NIC model:"}, {'device':'.*-spapr-cpu-core', 'log':r"CPU core type should be"}, {'log':r"MSI(-X)? is not supported by interrupt controller"}, {'log':r"pxb-pcie? devices cannot reside on a PCIe? bus"}, -- 1.8.3.1 From MAILER-DAEMON Tue Aug 22 13:31:19 2017 Received: from list by lists.gnu.org with archive (Exim 4.71) id 1dkD1L-00060k-82 for mharc-qemu-arm@gnu.org; Tue, 22 Aug 2017 13:31:19 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:44148) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dkD1J-00060A-Fa for qemu-arm@nongnu.org; Tue, 22 Aug 2017 13:31:18 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dkD1I-0004vx-IP for qemu-arm@nongnu.org; Tue, 22 Aug 2017 13:31:17 -0400 Received: from mail-wr0-x231.google.com ([2a00:1450:400c:c0c::231]:37039) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1dkD1I-0004vi-Au for qemu-arm@nongnu.org; Tue, 22 Aug 2017 13:31:16 -0400 Received: by mail-wr0-x231.google.com with SMTP id z91so127660478wrc.4 for ; Tue, 22 Aug 2017 10:31:16 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:in-reply-to:references:from:date:message-id:subject:to :cc; bh=YvWLWENi61GKyC/f9oCziRf4UglrxZshvcQaYUSLPuM=; b=aYnOVUjFR2Wd4kzHG67N6e2LM77Qsis2Wg0tJLCAHetGU1GFBsSZh1Mgs6fsj0pILn ZRJA1cvthUtktcmdi/iR5sxT1gTqCN3uyuTcmz1fekYv509NYDynyD8MpgpGfFQL1Hgs hi3egSjjlzQl8Iy33ac5DS8xLczmwqP2XMdlk= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:in-reply-to:references:from:date :message-id:subject:to:cc; bh=YvWLWENi61GKyC/f9oCziRf4UglrxZshvcQaYUSLPuM=; b=lTdsy14eV+kwjPVMmNE2jqOGwzxMt0iPQGnmtjQ+35YcnEyODFvs3KojuSvzYHi3PY IVcjPzsP7qNqe0DRJiQRKursaOigvm6IWUcyqqsoxlc2Ot+XGvqTegl1pkTbmBra0AsL gdQx7EDsyYFuG3IaCK52AKwvTwd+M5LiUNhGocK+aKm2+LRI+cv1frbSFdw48W1mKSON kj5+NarlBYnZYmfWepumOTl+fWiIXORCpO7Ghn6ZDW8pDcCNWTX4atsWYzqEi7vthtK1 trLcbu9RCzuVvzulTt2nkzpj4H1ZGtkQEptvgAskrmD5dbQM5C/j0yUnlbjyJmsmvPmH wRBw== X-Gm-Message-State: AHYfb5j5HoayI5ONv1LCswZeiu0uXMGGM2K2ee5XBScYN0XTAihzGktw YVf6gdoiPiwzIkbcMOLgLIXkt+O9RGVa X-Received: by 10.223.169.201 with SMTP id b67mr765969wrd.314.1503423074840; Tue, 22 Aug 2017 10:31:14 -0700 (PDT) MIME-Version: 1.0 Received: by 10.223.134.54 with HTTP; Tue, 22 Aug 2017 10:30:54 -0700 (PDT) In-Reply-To: <1503412231-13961-1-git-send-email-thuth@redhat.com> References: <1503412231-13961-1-git-send-email-thuth@redhat.com> From: Peter Maydell Date: Tue, 22 Aug 2017 18:30:54 +0100 Message-ID: To: Thomas Huth Cc: qemu-arm , QEMU Developers , Antony Pavlov Content-Type: text/plain; charset="UTF-8" X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:400c:c0c::231 Subject: Re: [Qemu-arm] [PATCH v2] hw/arm/digic: Mark device with user_creatable = false X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 22 Aug 2017 17:31:18 -0000 On 22 August 2017 at 15:30, Thomas Huth wrote: > QEMU currently shows some unexpected behavior when the user trys to > do a "device_add digic" on an unrelated ARM machine like integratorcp > in "-nographic" mode (the device_add command does not immediately > return to the monitor prompt), and trying to "device_del" the device > later results in a "qemu/qdev-monitor.c:872:qdev_unplug: assertion > failed: (hotplug_ctrl)" error condition. > Looking at the realize function of the device, it uses serial_hds > directly and this means that the device can not be added a second > time, so let's simply mark it with "user_creatable = false" now. > > Signed-off-by: Thomas Huth > --- > v2: Updated the comment and the patch description > > hw/arm/digic.c | 2 ++ > 1 file changed, 2 insertions(+) > > diff --git a/hw/arm/digic.c b/hw/arm/digic.c > index 94f3263..6184020 100644 > --- a/hw/arm/digic.c > +++ b/hw/arm/digic.c > @@ -101,6 +101,8 @@ static void digic_class_init(ObjectClass *oc, void *data) > DeviceClass *dc = DEVICE_CLASS(oc); > > dc->realize = digic_realize; > + /* Reason: Uses serial_hds in the realize function --> not usable twice */ > + dc->user_creatable = false; > } > > static const TypeInfo digic_type_info = { Applied to target-arm.next for 2.11, thanks. -- PMM From MAILER-DAEMON Tue Aug 22 13:31:53 2017 Received: from list by lists.gnu.org with archive (Exim 4.71) id 1dkD1t-0006MJ-Fz for mharc-qemu-arm@gnu.org; Tue, 22 Aug 2017 13:31:53 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:44233) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dkD1q-0006KA-Vy for qemu-arm@nongnu.org; Tue, 22 Aug 2017 13:31:52 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dkD1o-00051e-DS for qemu-arm@nongnu.org; Tue, 22 Aug 2017 13:31:49 -0400 Received: from mail-wr0-x22c.google.com ([2a00:1450:400c:c0c::22c]:33718) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1dkD1o-000515-7v for qemu-arm@nongnu.org; Tue, 22 Aug 2017 13:31:48 -0400 Received: by mail-wr0-x22c.google.com with SMTP id a47so15414018wra.0 for ; Tue, 22 Aug 2017 10:31:48 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:in-reply-to:references:from:date:message-id:subject:to :cc; bh=XCb1wrsNeDmPagpZ3TTUCDB+4vZDldV7iKdA+aF2Xm4=; b=OGgEk0MVCrgr+5BwjusxHsxaqbBii3STGkBez+LCzwcaVi1dfYF8XQJ2so/04GCrKu 4hza7Azu9H2/fTg6oD5mtgSLhfztAQ7VAGHuemuN7Uiw0qdYlC9S5GsqrhwDEWkcIU2+ VqKEuogkXXTsxG2L49a0EQ7kMruaYNJLQuQ0A= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:in-reply-to:references:from:date :message-id:subject:to:cc; bh=XCb1wrsNeDmPagpZ3TTUCDB+4vZDldV7iKdA+aF2Xm4=; b=avPC6CP5+8y7TI91gHBsdZ722eg4WHMjWEC5dz7XxfFMo7i4QOYPQD+qrY0Tfc/SvT qm4g7/uB7TZODDygrKmkaA0YjENgtiLH0uaoKnm+giS6FPyQkHAmgL/Rb8to1dFfe5TO Igl9OuhOlkHMN2dv1h3oiYNmhorVzqG0LMrEfB51D5cmJTvR5yavBPaquzSdzH49cmWz krtKsYOk+G/8hS7KeSHeCi7LvkGnwd6WqS/W1qLQjEWXeB4TCdj1hLwxc7Av5+MLbk/m t2D5SNZEP7r9uKtaLfMzIiWaejHFHEJY2UBWuSLHjMCZjTgJK1HGTw1eMuk/leCWBHGE ilRQ== X-Gm-Message-State: AHYfb5jyPJiqXb14T1WQF60Wgs8Oww4/mbC8z2YtHl1s7MweH4dsfzQ5 3eDhlNL9xBmBRXS8aLbU57Jg1vtqjMaKN0w= X-Received: by 10.223.131.197 with SMTP id 63mr976116wre.161.1503423107139; Tue, 22 Aug 2017 10:31:47 -0700 (PDT) MIME-Version: 1.0 Received: by 10.223.134.54 with HTTP; Tue, 22 Aug 2017 10:31:26 -0700 (PDT) In-Reply-To: <1503406059-7280-1-git-send-email-thuth@redhat.com> References: <1503406059-7280-1-git-send-email-thuth@redhat.com> From: Peter Maydell Date: Tue, 22 Aug 2017 18:31:26 +0100 Message-ID: To: Thomas Huth Cc: qemu-arm , =?UTF-8?Q?C=C3=A9dric_Le_Goater?= , Andrew Jeffery , Jeremy Kerr , QEMU Developers Content-Type: text/plain; charset="UTF-8" X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:400c:c0c::22c Subject: Re: [Qemu-arm] [PATCH] hw/arm/aspeed_soc: Mark devices as user_creatable = false X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 22 Aug 2017 17:31:52 -0000 On 22 August 2017 at 13:47, Thomas Huth wrote: > QEMU currently aborts if the user is accidentially trying to > do something like this: > > $ aarch64-softmmu/qemu-system-aarch64 -S -M integratorcp -nographic > QEMU 2.9.93 monitor - type 'help' for more information > (qemu) device_add ast2400 > Unexpected error in error_set_from_qdev_prop_error() > at hw/core/qdev-properties.c:1032: > Aborted (core dumped) > > The ast2400 SoC devices are clearly not creatable by the user since > they are using the serial_hds and nd_table arrays directly in their > realize function, so mark them with user_creatable = false. > > Signed-off-by: Thomas Huth > --- > hw/arm/aspeed_soc.c | 2 ++ > 1 file changed, 2 insertions(+) > > diff --git a/hw/arm/aspeed_soc.c b/hw/arm/aspeed_soc.c > index 5529024..7f1be04 100644 > --- a/hw/arm/aspeed_soc.c > +++ b/hw/arm/aspeed_soc.c > @@ -338,6 +338,8 @@ static void aspeed_soc_class_init(ObjectClass *oc, void *data) > > sc->info = (AspeedSoCInfo *) data; > dc->realize = aspeed_soc_realize; > + /* Reason: Uses serial_hds and nd_table in realize() directly */ > + dc->user_creatable = false; > } > > static const TypeInfo aspeed_soc_type_info = { > -- > 1.8.3.1 Applied to target-arm.next for 2.11, thanks. -- PMM From MAILER-DAEMON Tue Aug 22 14:15:51 2017 Received: from list by lists.gnu.org with archive (Exim 4.71) id 1dkDiQ-0004YG-Vz for mharc-qemu-arm@gnu.org; Tue, 22 Aug 2017 14:15:51 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:54594) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dkDiO-0004Wv-Or for qemu-arm@nongnu.org; Tue, 22 Aug 2017 14:15:49 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dkDiK-0005Qu-OS for qemu-arm@nongnu.org; Tue, 22 Aug 2017 14:15:48 -0400 Received: from mel.act-europe.fr ([194.98.77.210]:49198 helo=smtp.eu.adacore.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1dkDiK-0005NE-Hz; Tue, 22 Aug 2017 14:15:44 -0400 Received: from localhost (localhost [127.0.0.1]) by filtered-smtp.eu.adacore.com (Postfix) with ESMTP id 3496D82422; Tue, 22 Aug 2017 20:15:43 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at eu.adacore.com Received: from smtp.eu.adacore.com ([127.0.0.1]) by localhost (smtp.eu.adacore.com [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id ULt-5F_Qv4_9; Tue, 22 Aug 2017 20:15:43 +0200 (CEST) Received: from localhost.localdomain (182667ea.cst.lightpath.net [24.38.103.234]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.eu.adacore.com (Postfix) with ESMTPSA id 1B3C6822CE; Tue, 22 Aug 2017 20:15:42 +0200 (CEST) To: Thomas Huth Cc: Peter Maydell , qemu-arm@nongnu.org, qemu-devel@nongnu.org, "Edgar E. Iglesias" , Alistair Francis , qemu-trivial@nongnu.org References: <1503414375-21009-1-git-send-email-thuth@redhat.com> From: KONRAD Frederic Message-ID: <27da1dae-1e2f-559a-d8f0-c7e15289363e@adacore.com> Date: Tue, 22 Aug 2017 20:15:41 +0200 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.2.1 MIME-Version: 1.0 In-Reply-To: <1503414375-21009-1-git-send-email-thuth@redhat.com> Content-Type: text/plain; charset=utf-8; format=flowed Content-Language: en-US Content-Transfer-Encoding: 7bit X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [fuzzy] X-Received-From: 194.98.77.210 Subject: Re: [Qemu-arm] [PATCH] hw/misc/auxbus.c: Mark the aux-to-i2c-bridge device as non-hotpluggable X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 22 Aug 2017 18:15:50 -0000 Hi Thomas, Looking to this seems there is a second issue: The aux-to-i2c-bridge device should connect on a TYPE_AUX_BUS. I don't think there isn't any on integratorcp.. Anyway the patch you sent fix this issue indirectly and as far as I remember I wasn't able to make this I2C bridge an TYPE_AUX_DEVICE as it's a special device and it is internal (only instantiated at the bus creation). Thanks, Fred On 08/22/2017 05:06 PM, Thomas Huth wrote: > QEMU currently aborts if the user tries to do something like this: > > $ aarch64-softmmu/qemu-system-aarch64 -S -M integratorcp -nographic > QEMU 2.9.93 monitor - type 'help' for more information > (qemu) device_add aux-to-i2c-bridge,id=x > (qemu) device_del x > ** > ERROR:qemu/qdev-monitor.c:872:qdev_unplug: assertion failed: (hotplug_ctrl) > Aborted (core dumped) > > Looks like the device is not hot-pluggable, so let's mark it > accordingly. > > Signed-off-by: Thomas Huth > --- > hw/misc/auxbus.c | 8 ++++++++ > 1 file changed, 8 insertions(+) > > diff --git a/hw/misc/auxbus.c b/hw/misc/auxbus.c > index 8a90ddd..2c62515 100644 > --- a/hw/misc/auxbus.c > +++ b/hw/misc/auxbus.c > @@ -222,9 +222,17 @@ static inline I2CBus *aux_bridge_get_i2c_bus(AUXTOI2CState *bridge) > return bridge->i2c_bus; > } > > +static void aux_bridge_class_init(ObjectClass *oc, void *data) > +{ > + DeviceClass *dc = DEVICE_CLASS(oc); > + > + dc->hotpluggable = false; > +} > + > static const TypeInfo aux_to_i2c_type_info = { > .name = TYPE_AUXTOI2C, > .parent = TYPE_DEVICE, > + .class_init = aux_bridge_class_init, > .instance_size = sizeof(AUXTOI2CState), > .instance_init = aux_bridge_init > }; > From MAILER-DAEMON Tue Aug 22 15:04:40 2017 Received: from list by lists.gnu.org with archive (Exim 4.71) id 1dkETg-0004Bd-I9 for mharc-qemu-arm@gnu.org; Tue, 22 Aug 2017 15:04:40 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:34966) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dkETb-00049f-Hy for qemu-arm@nongnu.org; Tue, 22 Aug 2017 15:04:38 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dkETY-0005tP-Bq for qemu-arm@nongnu.org; Tue, 22 Aug 2017 15:04:35 -0400 Received: from mx1.redhat.com ([209.132.183.28]:36614) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1dkETY-0005se-2S; Tue, 22 Aug 2017 15:04:32 -0400 Received: from smtp.corp.redhat.com (int-mx04.intmail.prod.int.phx2.redhat.com [10.5.11.14]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id EE1FF13AAB; Tue, 22 Aug 2017 19:04:30 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mx1.redhat.com EE1FF13AAB Authentication-Results: ext-mx05.extmail.prod.ext.phx2.redhat.com; dmarc=none (p=none dis=none) header.from=redhat.com Authentication-Results: ext-mx05.extmail.prod.ext.phx2.redhat.com; spf=fail smtp.mailfrom=mst@redhat.com Received: from redhat.com (ovpn-125-55.rdu2.redhat.com [10.10.125.55]) by smtp.corp.redhat.com (Postfix) with SMTP id 1DE9B5D724; Tue, 22 Aug 2017 19:04:25 +0000 (UTC) Date: Tue, 22 Aug 2017 22:04:25 +0300 From: "Michael S. Tsirkin" To: Diana Madalina Craciun Cc: "Edgar E. Iglesias" , Auger Eric , "qemu-devel@nongnu.org" , Mike Caraman , "qemu-arm@nongnu.org" , "marcel@redhat.com" , Bharat Bhushan , "christoffer.dall@linaro.org" , Laurentiu Tudor Message-ID: <20170822214318-mutt-send-email-mst@kernel.org> References: <1495537965-4187-1-git-send-email-diana.craciun@nxp.com> <1495537965-4187-3-git-send-email-diana.craciun@nxp.com> <20170731151602.GU4859@toto> <20170811155027.GO4859@toto> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: X-Scanned-By: MIMEDefang 2.79 on 10.5.11.14 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.29]); Tue, 22 Aug 2017 19:04:31 +0000 (UTC) X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.132.183.28 Subject: Re: [Qemu-arm] [Qemu-devel] [PATCH v2 2/2] Add a unique ID in the virt machine to be used as device ID X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 22 Aug 2017 19:04:38 -0000 On Tue, Aug 22, 2017 at 03:13:57PM +0000, Diana Madalina Craciun wrote: > On 08/11/2017 06:50 PM, Edgar E. Iglesias wrote: > > On Fri, Aug 11, 2017 at 02:35:28PM +0000, Diana Madalina Craciun wrote: > >> Hi Edgar, > >> > >> On 07/31/2017 06:16 PM, Edgar E. Iglesias wrote: > >>> On Wed, Jul 26, 2017 at 02:22:28PM +0200, Auger Eric wrote: > >>>> Hi Diana, > >>>> On 23/05/2017 13:12, Diana Craciun wrote: > >>>>> Device IDs are required by the ARM GICv3 ITS for IRQ remapping. > >>>>> Currently, for PCI devices, the requester ID was used as device > >>>>> ID in the virt machine. If the system has multiple masters that > >>>> if the system has multiple root complex? > >>>>> use MSIs a unique ID accross the platform is needed. > >>>> across > >>>>> A static scheme is used and each master is allocated a range of IDs > >>>>> with the formula: > >>>>> DeviceID = zero_extend( RequesterID[15:0] ) + 0x10000*Constant (as > >>>>> recommended by SBSA). > >>>>> > >>>>> This ID will be configured in the machine creation and if not configured > >>>>> the PCI requester ID will be used insteead. > >>>> instead > >>>>> Signed-off-by: Diana Craciun > >>>>> --- > >>>>> hw/arm/virt.c | 26 ++++++++++++++++++++++++++ > >>>>> hw/pci-host/gpex.c | 6 ++++++ > >>>>> hw/pci/msi.c | 2 +- > >>>>> hw/pci/pci.c | 25 +++++++++++++++++++++++++ > >>>>> include/hw/arm/virt.h | 1 + > >>>>> include/hw/pci-host/gpex.h | 2 ++ > >>>>> include/hw/pci/pci.h | 8 ++++++++ > >>>>> kvm-all.c | 4 ++-- > >>>>> 8 files changed, 71 insertions(+), 3 deletions(-) > >>>>> > >>>>> diff --git a/hw/arm/virt.c b/hw/arm/virt.c > >>>>> index 5f62a03..a969694 100644 > >>>>> --- a/hw/arm/virt.c > >>>>> +++ b/hw/arm/virt.c > >>>>> @@ -110,6 +110,8 @@ static ARMPlatformBusSystemParams platform_bus_params; > >>>>> #define RAMLIMIT_GB 255 > >>>>> #define RAMLIMIT_BYTES (RAMLIMIT_GB * 1024ULL * 1024 * 1024) > >>>>> > >>>>> +#define STREAM_ID_RANGE_SIZE 0x10000 > >>>>> + > >>>>> /* Addresses and sizes of our components. > >>>>> * 0..128MB is space for a flash device so we can run bootrom code such as UEFI. > >>>>> * 128MB..256MB is used for miscellaneous device I/O. > >>>>> @@ -162,6 +164,22 @@ static const int a15irqmap[] = { > >>>>> [VIRT_PLATFORM_BUS] = 112, /* ...to 112 + PLATFORM_BUS_NUM_IRQS -1 */ > >>>>> }; > >>>>> > >>>>> +/* Device IDs are required by the ARM GICV3 ITS for IRQ remapping. Currently > >>>>> + * for PCI devices the requester ID was used as device ID. But if the system has > >>>>> + * multiple masters that use MSIs, the requester ID may cause deviceID clashes. > >>>>> + * So a unique number is needed accross the system. > >>>>> + * We are using the following formula: > >>>>> + * DeviceID = zero_extend( RequesterID[15:0] ) + 0x10000*Constant > >>>>> + * (as recommanded by SBSA). Currently we do not have an SMMU emulation, but the > >>>>> + * same formula can be used for the generation of the streamID as well. > >>>>> + * For each master the device ID will be derrived from the requester ID using > >>>>> + * the abovemntione formula. > >>>>> + */ > >>>> I think most of this comment should only be in the commit message. typos > >>>> in derived and above mentioned. > >>>> > >>>> stream id is the terminology for the id space at the input of the smmu. > >>>> device id is the terminology for the id space at the input of the msi > >>>> controller I think. > >>>> > >>>> RID -> deviceID (no IOMMU) > >>>> RID -> streamID -> deviceID (IOMMU) > >>>> > >>>> I would personally get rid of all streamid uses as the smmu is not yet > >>>> supported and stick to the > >>>> Documentation/devicetree/bindings/pci/pci-msi.txt terminology? > >>>> > >>>>> + > >>>>> +static const uint32_t streamidmap[] = { > >>>>> + [VIRT_PCIE] = 0, /* currently only one PCI controller */ > >>>>> +}; > >>>>> + > >>>>> static const char *valid_cpus[] = { > >>>>> "cortex-a15", > >>>>> "cortex-a53", > >>>>> @@ -980,6 +998,7 @@ static void create_pcie(const VirtMachineState *vms, qemu_irq *pic) > >>>>> hwaddr base_ecam = vms->memmap[VIRT_PCIE_ECAM].base; > >>>>> hwaddr size_ecam = vms->memmap[VIRT_PCIE_ECAM].size; > >>>>> hwaddr base = base_mmio; > >>>>> + uint32_t stream_id = vms->streamidmap[VIRT_PCIE] * STREAM_ID_RANGE_SIZE; > >>>> msi-base? > >>>> STREAM_ID_RANGE_SIZE ~ MSI_MAP_LENGTH? > >>>>> int nr_pcie_buses = size_ecam / PCIE_MMCFG_SIZE_MIN; > >>>>> int irq = vms->irqmap[VIRT_PCIE]; > >>>>> MemoryRegion *mmio_alias; > >>>>> @@ -992,6 +1011,7 @@ static void create_pcie(const VirtMachineState *vms, qemu_irq *pic) > >>>>> PCIHostState *pci; > >>>>> > >>>>> dev = qdev_create(NULL, TYPE_GPEX_HOST); > >>>>> + qdev_prop_set_uint32(dev, "stream-id-base", stream_id); > >>>>> qdev_init_nofail(dev); > >>>>> > >>>>> /* Map only the first size_ecam bytes of ECAM space */ > >>>>> @@ -1056,6 +1076,11 @@ static void create_pcie(const VirtMachineState *vms, qemu_irq *pic) > >>>>> if (vms->msi_phandle) { > >>>>> qemu_fdt_setprop_cells(vms->fdt, nodename, "msi-parent", > >>>>> vms->msi_phandle); > >>>>> + qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "msi-map", > >>>>> + 1, 0, > >>>>> + 1, vms->msi_phandle, > >>>>> + 1, stream_id, > >>>>> + 1, STREAM_ID_RANGE_SIZE); > >>>>> } > >>>>> > >>>>> qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg", > >>>>> @@ -1609,6 +1634,7 @@ static void virt_2_9_instance_init(Object *obj) > >>>>> > >>>>> vms->memmap = a15memmap; > >>>>> vms->irqmap = a15irqmap; > >>>>> + vms->streamidmap = streamidmap; > >>>>> } > >>>>> > >>>>> static void virt_machine_2_9_options(MachineClass *mc) > >>>>> diff --git a/hw/pci-host/gpex.c b/hw/pci-host/gpex.c > >>>>> index 66055ee..de72408 100644 > >>>>> --- a/hw/pci-host/gpex.c > >>>>> +++ b/hw/pci-host/gpex.c > >>>>> @@ -43,6 +43,11 @@ static void gpex_set_irq(void *opaque, int irq_num, int level) > >>>>> qemu_set_irq(s->irq[irq_num], level); > >>>>> } > >>>>> > >>>>> +static Property gpex_props[] = { > >>>>> + DEFINE_PROP_UINT32("stream-id-base", GPEXHost, stream_id_base, 0), > >>>> msi_base_base > >>>>> + DEFINE_PROP_END_OF_LIST(), > >>>>> +}; > >>>>> + > >>>>> static void gpex_host_realize(DeviceState *dev, Error **errp) > >>>>> { > >>>>> PCIHostState *pci = PCI_HOST_BRIDGE(dev); > >>>>> @@ -83,6 +88,7 @@ static void gpex_host_class_init(ObjectClass *klass, void *data) > >>>>> > >>>>> hc->root_bus_path = gpex_host_root_bus_path; > >>>>> dc->realize = gpex_host_realize; > >>>>> + dc->props = gpex_props; > >>>>> set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories); > >>>>> dc->fw_name = "pci"; > >>>>> } > >>>>> diff --git a/hw/pci/msi.c b/hw/pci/msi.c > >>>>> index 7925851..b60a410 100644 > >>>>> --- a/hw/pci/msi.c > >>>>> +++ b/hw/pci/msi.c > >>>>> @@ -336,7 +336,7 @@ void msi_send_message(PCIDevice *dev, MSIMessage msg) > >>>>> { > >>>>> MemTxAttrs attrs = {}; > >>>>> > >>>>> - attrs.stream_id = pci_requester_id(dev); > >>>>> + attrs.stream_id = pci_stream_id(dev); > >>>>> address_space_stl_le(&dev->bus_master_as, msg.address, msg.data, > >>>>> attrs, NULL); > >>>>> } > >>>>> diff --git a/hw/pci/pci.c b/hw/pci/pci.c > >>>>> index 259483b..92e9a2b 100644 > >>>>> --- a/hw/pci/pci.c > >>>>> +++ b/hw/pci/pci.c > >>>>> @@ -951,6 +951,30 @@ uint16_t pci_requester_id(PCIDevice *dev) > >>>>> return pci_req_id_cache_extract(&dev->requester_id_cache); > >>>>> } > >>>>> > >>>>> +static uint32_t pci_get_stream_id_base(PCIDevice *dev) > >>>>> +{ > >>>>> + PCIBus *rootbus = pci_device_root_bus(dev); > >>>>> + PCIHostState *host_bridge = PCI_HOST_BRIDGE(rootbus->qbus.parent); > >>>>> + Error *err = NULL; > >>>>> + int64_t stream_id; > >>>>> + > >>>>> + stream_id = object_property_get_int(OBJECT(host_bridge), "stream-id-base", > >>>>> + &err); > >>>>> + if (stream_id < 0) { > >>>>> + stream_id = 0; > >>>>> + } > >>>>> + > >>>>> + return stream_id; > >>>>> +} > >>>>> + > >>>>> +uint32_t pci_stream_id(PCIDevice *dev) > >>>>> +{ > >>>>> + /* Stream ID = RequesterID[15:0] + stream_id_base. stream_id_base may > >>>>> + * be 0 for devices that are not using any translation between requester_id > >>>>> + * and stream_id */ > >>>>> + return (uint16_t)pci_requester_id(dev) + dev->stream_id_base; > >>>>> +} > >>>> I think you should split the changes in virt from pci/gpex generic changes. > >>>> > >>>>> + > >>>>> /* -1 for devfn means auto assign */ > >>>>> static PCIDevice *do_pci_register_device(PCIDevice *pci_dev, PCIBus *bus, > >>>>> const char *name, int devfn, > >>>>> @@ -1000,6 +1024,7 @@ static PCIDevice *do_pci_register_device(PCIDevice *pci_dev, PCIBus *bus, > >>>>> > >>>>> pci_dev->devfn = devfn; > >>>>> pci_dev->requester_id_cache = pci_req_id_cache_get(pci_dev); > >>>>> + pci_dev->stream_id_base = pci_get_stream_id_base(pci_dev); > >>>> looks strange to me to store the rid base in the end point as this is > >>>> rather a property of the PCI complex. I acknowledge this is much more > >>> I agree. > >> The reason I have changed was to avoid traversing the entire hierarchy > >> each time the ID is needed (for example each time when a MSI is sent). > >> > >>> I think that what we need is to add support for allowing PCI RCs > >>> to transform requesterIDs in transactions attributes according to the > >>> implementation specifics. > >> Do you mean that you need more than a linear offset between requesterID > >> and whatever other ID? > > > > Yes. > > > > This is my understanding for the ARM platforms I'm familiar with: > > > > Since AXI busses don't have a defined way to carry Master IDs, these > > are typically carried on the AXI user signals. I'll just refer to > > these signals as AXI Master IDs. > > > > 1. An endpoint issues an MSI (or any) transaction on the PCI bus. > > In QEMU, these trasactions carry the requester ID in their attributes. > > > > 2. The transaction hits the PCI "host" bridge to the SoC internal > > interconnect (typically AXI). This bridge needs to forward the > > PCI transaction onto the AXI bus. Including mapping the PCI > > RequesterID into an AXI MasterID. > > > > 3. The AXI transaction hits the IOMMU and the MasterID is mapped > > into a streamID to identify the origin of the transaction > > and apply address translation accordingly. If the SMMU > > allows the transaction to pass, the stream ID is mapped back > > into the transactions MasterID. > > > > 4. The AXI transaction continues down the interconnect and hits > > the MSI doorbell and the MasterID is mapped into a DeviceID to > > identify the origin of the MSI and apply possible interrupt translation. > > > > Adding streamID fields to a PCI endpoint doesn't make any sense to me. > > The requester ID is already there and is IMO enough. > > StreamIDs are a concept of ARM System MMUs, not of PCI endpoints. > > What I have added into the endpoint is actually the Master ID (in QEMU > it is actually equal with the streamID). I agree that this is a property > of the root complex, the only reason I have put it into the endpoint was > to avoid traversing the PCI hierarchy each time an MSI is sent. Can all this be folded into the IOMMU? Then you might be able to get by with defining an iommu function. pci_device_iommu_address_space already walks the hierarchy. > > > > When modelling #2, hardcoding a specific linear mapping between > > PCI requester IDs and AXI Master IDs may work for one platform > > but it won't work for all platforms. There is no one mapping for all. > > It can even be run-time programmable in the bridge. OK but how does it work with the specific bridge that you emulate? There is no need to model advanced bridges with super flexible programmable mappings if guests do not need them to run. > > One solution might be defining a function in the generic host bridge > which by default returns the requesterIDs (assumes that requesterID is > the same with the masterID). This function can be over overridden by > each specific implementation. > > > > > IIRC, the SMMUv3 docs have a section that suggest how these ReqID to AXI Master ID mappings can be done. > > I did not find the specific section, just that the streamID should be > derived from requesterID. > > > Thanks, > > Diana > > > > > >>> The way we did it when modelling the ZynqMP is by adding support for > >>> transaction attribute translation in QEMU's IOMMU interface. > >>> In our PCI RC, we have an IOMMU covering the entire AS that PCI devs DMA into. > >>> This IOMMU doesn't do address-translation, only RequesterID -> StreamID > >>> transforms according to how the ZynqMP PCI RC derives StreamIDs from RequesterIDs. > >> Are there any patches for this support in order for me to better understand? > > It's currently on the Xilinx QEMU fork on GitHub. > > https://github.com/Xilinx/qemu/blob/master/hw/pci-host/xlnx-nwl-pcie-main.c > > > > In the current ZynqMP, all RequesterIDs map to a single MasterID (it's a HW limitation). > > In future versions of the HW, another mapping will be used. > > I can't share code for the latter yet though.... > > > > Best regards, > > Edgar > > > > > > > >> Thanks, > >> > >> Diana > >> > >> > >>> This is useful not only to model PCI RequesterID to AXI Master ID mappings but > >>> also for modelling things like the ARM TZC (or the Xilinx ZynqMP XMPU/XPPUs). > >>> > >>> Cheers, > >>> Edgar > >>> > >>> > >>>> simple than reworking pci_requester_id() though. > >>>>> > >>>>> memory_region_init(&pci_dev->bus_master_container_region, OBJECT(pci_dev), > >>>>> "bus master container", UINT64_MAX); > >>>>> diff --git a/include/hw/arm/virt.h b/include/hw/arm/virt.h > >>>>> index 33b0ff3..94c007a 100644 > >>>>> --- a/include/hw/arm/virt.h > >>>>> +++ b/include/hw/arm/virt.h > >>>>> @@ -99,6 +99,7 @@ typedef struct { > >>>>> struct arm_boot_info bootinfo; > >>>>> const MemMapEntry *memmap; > >>>>> const int *irqmap; > >>>>> + const uint32_t *streamidmap; > >>>>> int smp_cpus; > >>>>> void *fdt; > >>>>> int fdt_size; > >>>>> diff --git a/include/hw/pci-host/gpex.h b/include/hw/pci-host/gpex.h > >>>>> index 68c9348..47df01a 100644 > >>>>> --- a/include/hw/pci-host/gpex.h > >>>>> +++ b/include/hw/pci-host/gpex.h > >>>>> @@ -48,6 +48,8 @@ typedef struct GPEXHost { > >>>>> > >>>>> GPEXRootState gpex_root; > >>>>> > >>>>> + uint32_t stream_id_base; > >>>>> + > >>>>> MemoryRegion io_ioport; > >>>>> MemoryRegion io_mmio; > >>>>> qemu_irq irq[GPEX_NUM_IRQS]; > >>>>> diff --git a/include/hw/pci/pci.h b/include/hw/pci/pci.h > >>>>> index a37a2d5..e6e9334 100644 > >>>>> --- a/include/hw/pci/pci.h > >>>>> +++ b/include/hw/pci/pci.h > >>>>> @@ -283,6 +283,12 @@ struct PCIDevice { > >>>>> * MSI). For conventional PCI root complex, this field is > >>>>> * meaningless. */ > >>>>> PCIReqIDCache requester_id_cache; > >>>>> + /* Some platforms need a unique ID for IOMMU source identification > >>>>> + * or MSI source identification. QEMU implements a simple scheme: > >>>>> + * stream_id = stream_id_base + requester_id. The stream_id_base will > >>>>> + * ensure that all the devices in the system have different stream ID > >>>>> + * domains */ > >>>>> + uint32_t stream_id_base; > >>>> get rid of IOMMU terminology? > >>>> > >>>> Note that when adding other sub-systems you will need to address the > >>>> ACPI side as the IORT table built by hw/arm/virt-acpi-build.c currently > >>>> defines an RID mapping for the single root complex. > >>>> > >>>> Thanks > >>>> > >>>> Eric > >>>>> char name[64]; > >>>>> PCIIORegion io_regions[PCI_NUM_REGIONS]; > >>>>> AddressSpace bus_master_as; > >>>>> @@ -737,6 +743,8 @@ static inline uint16_t pci_get_bdf(PCIDevice *dev) > >>>>> > >>>>> uint16_t pci_requester_id(PCIDevice *dev); > >>>>> > >>>>> +uint32_t pci_stream_id(PCIDevice *dev); > >>>>> + > >>>>> /* DMA access functions */ > >>>>> static inline AddressSpace *pci_get_address_space(PCIDevice *dev) > >>>>> { > >>>>> diff --git a/kvm-all.c b/kvm-all.c > >>>>> index 90b8573..5a508c3 100644 > >>>>> --- a/kvm-all.c > >>>>> +++ b/kvm-all.c > >>>>> @@ -1280,7 +1280,7 @@ int kvm_irqchip_add_msi_route(KVMState *s, int vector, PCIDevice *dev) > >>>>> kroute.u.msi.data = le32_to_cpu(msg.data); > >>>>> if (kvm_msi_devid_required()) { > >>>>> kroute.flags = KVM_MSI_VALID_DEVID; > >>>>> - kroute.u.msi.devid = pci_requester_id(dev); > >>>>> + kroute.u.msi.devid = pci_stream_id(dev); > >>>>> } > >>>>> if (kvm_arch_fixup_msi_route(&kroute, msg.address, msg.data, dev)) { > >>>>> kvm_irqchip_release_virq(s, virq); > >>>>> @@ -1317,7 +1317,7 @@ int kvm_irqchip_update_msi_route(KVMState *s, int virq, MSIMessage msg, > >>>>> kroute.u.msi.data = le32_to_cpu(msg.data); > >>>>> if (kvm_msi_devid_required()) { > >>>>> kroute.flags = KVM_MSI_VALID_DEVID; > >>>>> - kroute.u.msi.devid = pci_requester_id(dev); > >>>>> + kroute.u.msi.devid = pci_stream_id(dev); > >>>>> } > >>>>> if (kvm_arch_fixup_msi_route(&kroute, msg.address, msg.data, dev)) { > >>>>> return -EINVAL; > >>>>> > From MAILER-DAEMON Wed Aug 23 00:25:24 2017 Received: from list by lists.gnu.org with archive (Exim 4.71) id 1dkNEK-00087g-9c for mharc-qemu-arm@gnu.org; Wed, 23 Aug 2017 00:25:24 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:57377) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dkNEG-00086g-M0 for qemu-arm@nongnu.org; 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X-Received-From: 2607:f8b0:400e:c00::242 Subject: Re: [Qemu-arm] [RFC v6 8/9] hw/arm/smmuv3: VFIO integration X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 23 Aug 2017 04:25:23 -0000 Hi Eric, On Fri Aug 11, 2017 at 04:22:33PM +0200, Eric Auger wrote: > This patch allows doing PCIe passthrough with a guest exposed > with a vSMMUv3. It implements the replay and notify_flag_changed > iommu ops. Also on TLB and data structure invalidation commands, > we replay the mappings so that the physical IOMMU implements > updated stage 1 settings (Guest IOVA -> Guest PA) + stage 2 settings. > > This works only if the guest smmuv3 driver implements the > "tlbi-on-map" option. > > Signed-off-by: Eric Auger Tried out launching a guest with Qemu option "-machine virt-2.10,smmu" and a 1G Ethernet controller as vfio-pci device. It works fine for me. Qemu source: https://github.com/eauger/qemu.git Branch: v2.10.0-rc2-SMMU-v6 But had to make this change, --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -1806,7 +1806,7 @@ static void virt_machine_2_10_options(MachineClass *mc) virt_machine_2_11_options(mc); SET_MACHINE_COMPAT(mc, VIRT_COMPAT_2_10); - vmc->no_smmu = true; + vmc->no_smmu = false; } DEFINE_VIRT_MACHINE(2, 10) so that qemu doesnt complain about "Property .smmu not found" Will let you know if i have updates on further testing. Thanks. > > --- > > v5 -> v6: > - use IOMMUMemoryRegion > - handle implementation defined SMMU_CMD_TLBI_NH_VA_AM cmd > (goes along with TLBI_ON_MAP FW quirk) > - replay systematically unmap the whole range first > - smmuv3_map_hook does not unmap anymore and the unmap is done > before the replay > - add and use smmuv3_context_device_invalidate instead of > blindly replaying everything > --- > hw/arm/smmuv3-internal.h | 1 + > hw/arm/smmuv3.c | 265 ++++++++++++++++++++++++++++++++++++++++++++++- > hw/arm/trace-events | 14 +++ > 3 files changed, 277 insertions(+), 3 deletions(-) > > diff --git a/hw/arm/smmuv3-internal.h b/hw/arm/smmuv3-internal.h > index e255df1..ac4628f 100644 > --- a/hw/arm/smmuv3-internal.h > +++ b/hw/arm/smmuv3-internal.h > @@ -344,6 +344,7 @@ enum { > SMMU_CMD_RESUME = 0x44, > SMMU_CMD_STALL_TERM, > SMMU_CMD_SYNC, /* 0x46 */ > + SMMU_CMD_TLBI_NH_VA_AM = 0x8F, /* VIOMMU Impl Defined */ > }; > > static const char *cmd_stringify[] = { > diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c > index e195a0e..89fb116 100644 > --- a/hw/arm/smmuv3.c > +++ b/hw/arm/smmuv3.c > @@ -25,6 +25,7 @@ > #include "exec/address-spaces.h" > #include "trace.h" > #include "qemu/error-report.h" > +#include "exec/target_page.h" > > #include "hw/arm/smmuv3.h" > #include "smmuv3-internal.h" > @@ -143,6 +144,71 @@ static MemTxResult smmu_read_cmdq(SMMUV3State *s, Cmd *cmd) > return ret; > } > > +static void smmuv3_replay_all(SMMUState *s) > +{ > + SMMUNotifierNode *node; > + > + QLIST_FOREACH(node, &s->notifiers_list, next) { > + trace_smmuv3_replay_all(node->sdev->iommu.parent_obj.name); > + memory_region_iommu_replay_all(&node->sdev->iommu); > + } > +} > + > +/* Replay the mappings for a given streamid */ > +static void smmuv3_context_device_invalidate(SMMUState *s, uint16_t sid) > +{ > + uint8_t bus_n, devfn; > + SMMUPciBus *smmu_bus; > + SMMUDevice *smmu; > + > + trace_smmuv3_context_device_invalidate(sid); > + bus_n = PCI_BUS_NUM(sid); > + smmu_bus = smmu_find_as_from_bus_num(s, bus_n); > + if (smmu_bus) { > + devfn = PCI_FUNC(sid); > + smmu = smmu_bus->pbdev[devfn]; > + if (smmu) { > + memory_region_iommu_replay_all(&smmu->iommu); > + } > + } > +} > + > +static void smmuv3_replay_single(IOMMUMemoryRegion *mr, IOMMUNotifier *n, > + uint64_t iova); > + > +static void smmuv3_replay_range(IOMMUMemoryRegion *mr, IOMMUNotifier *n, > + uint64_t iova, size_t nb_pages); > + > +static void smmuv3_notify_single(SMMUState *s, uint64_t iova) > +{ > + SMMUNotifierNode *node; > + > + QLIST_FOREACH(node, &s->notifiers_list, next) { > + IOMMUMemoryRegion *mr = &node->sdev->iommu; > + IOMMUNotifier *n; > + > + trace_smmuv3_notify_all(node->sdev->iommu.parent_obj.name, iova); > + IOMMU_NOTIFIER_FOREACH(n, mr) { > + smmuv3_replay_single(mr, n, iova); > + } > + } > +} > + > +static void smmuv3_notify_range(SMMUState *s, uint64_t iova, size_t size) > +{ > + SMMUNotifierNode *node; > + > + QLIST_FOREACH(node, &s->notifiers_list, next) { > + IOMMUMemoryRegion *mr = &node->sdev->iommu; > + IOMMUNotifier *n; > + > + trace_smmuv3_notify_all(node->sdev->iommu.parent_obj.name, iova); > + IOMMU_NOTIFIER_FOREACH(n, mr) { > + smmuv3_replay_range(mr, n, iova, size); > + } > + } > +} > + > static int smmu_cmdq_consume(SMMUV3State *s) > { > uint32_t error = SMMU_CMD_ERR_NONE; > @@ -178,28 +244,38 @@ static int smmu_cmdq_consume(SMMUV3State *s) > break; > case SMMU_CMD_PREFETCH_CONFIG: > case SMMU_CMD_PREFETCH_ADDR: > + break; > case SMMU_CMD_CFGI_STE: > { > uint32_t streamid = cmd.word[1]; > > trace_smmuv3_cmdq_cfgi_ste(streamid); > - break; > + smmuv3_context_device_invalidate(&s->smmu_state, streamid); > + break; > } > case SMMU_CMD_CFGI_STE_RANGE: /* same as SMMU_CMD_CFGI_ALL */ > { > - uint32_t start = cmd.word[1], range, end; > + uint32_t start = cmd.word[1], range, end, i; > > range = extract32(cmd.word[2], 0, 5); > end = start + (1 << (range + 1)) - 1; > trace_smmuv3_cmdq_cfgi_ste_range(start, end); > + for (i = start; i <= end; i++) { > + smmuv3_context_device_invalidate(&s->smmu_state, i); > + } > break; > } > case SMMU_CMD_CFGI_CD: > case SMMU_CMD_CFGI_CD_ALL: > + { > + uint32_t streamid = cmd.word[1]; > + > + smmuv3_context_device_invalidate(&s->smmu_state, streamid); > break; > + } > case SMMU_CMD_TLBI_NH_ALL: > case SMMU_CMD_TLBI_NH_ASID: > - printf("%s TLBI* replay\n", __func__); > + smmuv3_replay_all(&s->smmu_state); > break; > case SMMU_CMD_TLBI_NH_VA: > { > @@ -210,6 +286,20 @@ static int smmu_cmdq_consume(SMMUV3State *s) > uint64_t addr = high << 32 | (low << 12); > > trace_smmuv3_cmdq_tlbi_nh_va(asid, vmid, addr); > + smmuv3_notify_single(&s->smmu_state, addr); > + break; > + } > + case SMMU_CMD_TLBI_NH_VA_AM: > + { > + int asid = extract32(cmd.word[1], 16, 16); > + int am = extract32(cmd.word[1], 0, 16); > + uint64_t low = extract32(cmd.word[2], 12, 20); > + uint64_t high = cmd.word[3]; > + uint64_t addr = high << 32 | (low << 12); > + size_t size = am << 12; > + > + trace_smmuv3_cmdq_tlbi_nh_va_am(asid, am, addr, size); > + smmuv3_notify_range(&s->smmu_state, addr, size); > break; > } > case SMMU_CMD_TLBI_NH_VAA: > @@ -222,6 +312,7 @@ static int smmu_cmdq_consume(SMMUV3State *s) > case SMMU_CMD_TLBI_S12_VMALL: > case SMMU_CMD_TLBI_S2_IPA: > case SMMU_CMD_TLBI_NSNH_ALL: > + smmuv3_replay_all(&s->smmu_state); > break; > case SMMU_CMD_ATC_INV: > case SMMU_CMD_PRI_RESP: > @@ -804,6 +895,172 @@ out: > return entry; > } > > +static int smmuv3_replay_hook(IOMMUTLBEntry *entry, void *private) > +{ > + trace_smmuv3_replay_hook(entry->iova, entry->translated_addr, > + entry->addr_mask, entry->perm); > + memory_region_notify_one((IOMMUNotifier *)private, entry); > + return 0; > +} > + > +static int smmuv3_map_hook(IOMMUTLBEntry *entry, void *private) > +{ > + trace_smmuv3_map_hook(entry->iova, entry->translated_addr, > + entry->addr_mask, entry->perm); > + memory_region_notify_one((IOMMUNotifier *)private, entry); > + return 0; > +} > + > +/* Unmap the whole range in the notifier's scope. */ > +static void smmuv3_unmap_notifier(SMMUDevice *sdev, IOMMUNotifier *n) > +{ > + IOMMUTLBEntry entry; > + hwaddr size; > + hwaddr start = n->start; > + hwaddr end = n->end; > + > + size = end - start + 1; > + > + entry.target_as = &address_space_memory; > + /* Adjust iova for the size */ > + entry.iova = n->start & ~(size - 1); > + /* This field is meaningless for unmap */ > + entry.translated_addr = 0; > + entry.perm = IOMMU_NONE; > + entry.addr_mask = size - 1; > + > + /* TODO: check start/end/size/mask */ > + > + trace_smmuv3_unmap_notifier(pci_bus_num(sdev->bus), > + PCI_SLOT(sdev->devfn), > + PCI_FUNC(sdev->devfn), > + entry.iova, size); > + > + memory_region_notify_one(n, &entry); > +} > + > +static void smmuv3_replay(IOMMUMemoryRegion *mr, IOMMUNotifier *n) > +{ > + SMMUDevice *sdev = container_of(mr, SMMUDevice, iommu); > + SMMUV3State *s = sdev->smmu; > + SMMUBaseClass *sbc = SMMU_DEVICE_GET_CLASS(s); > + SMMUTransCfg cfg = {}; > + int ret; > + > + smmuv3_unmap_notifier(sdev, n); > + > + ret = smmuv3_decode_config(mr, &cfg); > + if (ret) { > + error_report("%s error decoding the configuration for iommu mr=%s", > + __func__, mr->parent_obj.name); > + } > + > + if (cfg.disabled || cfg.bypassed) { > + return; > + } > + /* is the smmu enabled */ > + sbc->page_walk_64(&cfg, 0, (1ULL << (64 - cfg.tsz)) - 1, false, > + smmuv3_replay_hook, n); > +} > +static void smmuv3_replay_range(IOMMUMemoryRegion *mr, IOMMUNotifier *n, > + uint64_t iova, size_t size) > +{ > + SMMUDevice *sdev = container_of(mr, SMMUDevice, iommu); > + SMMUV3State *s = sdev->smmu; > + SMMUBaseClass *sbc = SMMU_DEVICE_GET_CLASS(s); > + SMMUTransCfg cfg = {}; > + IOMMUTLBEntry entry; > + int ret; > + > + trace_smmuv3_replay_range(mr->parent_obj.name, iova, size, n); > + ret = smmuv3_decode_config(mr, &cfg); > + if (ret) { > + error_report("%s error decoding the configuration for iommu mr=%s", > + __func__, mr->parent_obj.name); > + } > + > + if (cfg.disabled || cfg.bypassed) { > + return; > + } > + > + /* first unmap */ > + entry.target_as = &address_space_memory; > + entry.iova = iova & ~(size - 1); > + entry.addr_mask = size - 1; > + entry.perm = IOMMU_NONE; > + > + memory_region_notify_one(n, &entry); > + > + /* then figure out if a new mapping needs to be applied */ > + sbc->page_walk_64(&cfg, iova, iova + entry.addr_mask , false, > + smmuv3_map_hook, n); > +} > + > +static void smmuv3_replay_single(IOMMUMemoryRegion *mr, IOMMUNotifier *n, > + uint64_t iova) > +{ > + SMMUDevice *sdev = container_of(mr, SMMUDevice, iommu); > + SMMUV3State *s = sdev->smmu; > + size_t target_page_size = qemu_target_page_size(); > + SMMUBaseClass *sbc = SMMU_DEVICE_GET_CLASS(s); > + SMMUTransCfg cfg = {}; > + IOMMUTLBEntry entry; > + int ret; > + > + trace_smmuv3_replay_single(mr->parent_obj.name, iova, n); > + ret = smmuv3_decode_config(mr, &cfg); > + if (ret) { > + error_report("%s error decoding the configuration for iommu mr=%s", > + __func__, mr->parent_obj.name); > + } > + > + if (cfg.disabled || cfg.bypassed) { > + return; > + } > + > + /* first unmap */ > + entry.target_as = &address_space_memory; > + entry.iova = iova & ~(target_page_size - 1); > + entry.addr_mask = target_page_size - 1; > + entry.perm = IOMMU_NONE; > + > + memory_region_notify_one(n, &entry); > + > + /* then figure out if a new mapping needs to be applied */ > + sbc->page_walk_64(&cfg, iova, iova + 1, false, > + smmuv3_map_hook, n); > +} > + > +static void smmuv3_notify_flag_changed(IOMMUMemoryRegion *iommu, > + IOMMUNotifierFlag old, > + IOMMUNotifierFlag new) > +{ > + SMMUDevice *sdev = container_of(iommu, SMMUDevice, iommu); > + SMMUV3State *s3 = sdev->smmu; > + SMMUState *s = &(s3->smmu_state); > + SMMUNotifierNode *node = NULL; > + SMMUNotifierNode *next_node = NULL; > + > + if (old == IOMMU_NOTIFIER_NONE) { > + trace_smmuv3_notify_flag_add(iommu->parent_obj.name); > + node = g_malloc0(sizeof(*node)); > + node->sdev = sdev; > + QLIST_INSERT_HEAD(&s->notifiers_list, node, next); > + return; > + } > + > + /* update notifier node with new flags */ > + QLIST_FOREACH_SAFE(node, &s->notifiers_list, next, next_node) { > + if (node->sdev == sdev) { > + if (new == IOMMU_NOTIFIER_NONE) { > + trace_smmuv3_notify_flag_del(iommu->parent_obj.name); > + QLIST_REMOVE(node, next); > + g_free(node); > + } > + return; > + } > + } > +} > > static inline void smmu_update_base_reg(SMMUV3State *s, uint64_t *base, > uint64_t val) > @@ -1125,6 +1382,8 @@ static void smmuv3_iommu_memory_region_class_init(ObjectClass *klass, > IOMMUMemoryRegionClass *imrc = IOMMU_MEMORY_REGION_CLASS(klass); > > imrc->translate = smmuv3_translate; > + imrc->notify_flag_changed = smmuv3_notify_flag_changed; > + imrc->replay = smmuv3_replay; > } > > static const TypeInfo smmuv3_type_info = { > diff --git a/hw/arm/trace-events b/hw/arm/trace-events > index f9b9cbe..8228e26 100644 > --- a/hw/arm/trace-events > +++ b/hw/arm/trace-events > @@ -27,6 +27,7 @@ smmuv3_cmdq_opcode(const char *opcode) "<--- %s" > smmuv3_cmdq_cfgi_ste(int streamid) " |_ streamid =%d" > smmuv3_cmdq_cfgi_ste_range(int start, int end) " |_ start=0x%d - end=0x%d" > smmuv3_cmdq_tlbi_nh_va(int asid, int vmid, uint64_t addr) " |_ asid =%d vmid =%d addr=0x%"PRIx64 > +smmuv3_cmdq_tlbi_nh_va_am(int asid, int am, size_t size, uint64_t addr) " |_ asid =%d am =%d size=0x%lx addr=0x%"PRIx64 > smmuv3_cmdq_consume_sev(void) "CMD_SYNC CS=SEV not supported, ignoring" > smmuv3_cmdq_consume_out(uint8_t prod_wrap, uint32_t prod, uint8_t cons_wrap, uint32_t cons) "prod_wrap:%d, prod:0x%x cons_wrap:%d cons:0x%x" > smmuv3_update(bool is_empty, uint32_t prod, uint32_t cons, uint8_t prod_wrap, uint8_t cons_wrap) "q empty:%d prod:%d cons:%d p.wrap:%d p.cons:%d" > @@ -50,3 +51,16 @@ smmuv3_dump_ste(int i, uint32_t word0, int j, uint32_t word1) "STE[%2d]: 0x%x\t > smmuv3_dump_cd(int i, uint32_t word0, int j, uint32_t word1) "CD[%2d]: 0x%x\t CD[%2d]: 0x%x" > smmuv3_dump_cmd(int i, uint32_t word0, int j, uint32_t word1) "CMD[%2d]: 0x%x\t CMD[%2d]: 0x%x" > smmuv3_cfg_stage(int s, uint32_t oas, uint32_t tsz, uint64_t ttbr, bool aa64, uint32_t granule_sz, int initial_level) "TransCFG stage:%d oas:%d tsz:%d ttbr:0x%"PRIx64" aa64:%d granule_sz:%d, initial_level = %d" > + > +smmuv3_replay(uint16_t sid, bool enabled) "sid=%d, enabled=%d" > +smmuv3_replay_hook(hwaddr iova, hwaddr pa, hwaddr mask, int perm) "iova=0x%"PRIx64" pa=0x%" PRIx64" mask=0x%"PRIx64" perm=%d" > +smmuv3_map_hook(hwaddr iova, hwaddr pa, hwaddr mask, int perm) "iova=0x%"PRIx64" pa=0x%" PRIx64" mask=0x%"PRIx64" perm=%d" > +smmuv3_notify_flag_add(const char *iommu) "ADD SMMUNotifier node for iommu mr=%s" > +smmuv3_notify_flag_del(const char *iommu) "DEL SMMUNotifier node for iommu mr=%s" > +smmuv3_replay_single(const char *name, uint64_t iova, void *n) "iommu mr=%s iova=0x%"PRIx64" n=%p" > +smmuv3_replay_range(const char *name, uint64_t iova, size_t size, void *n) "iommu mr=%s iova=0x%"PRIx64" size=0x%lx n=%p" > +smmuv3_replay_all(const char *name) "iommu mr=%s" > +smmuv3_notify_all(const char *name, uint64_t iova) "iommu mr=%s iova=0x%"PRIx64 > +smmuv3_unmap_notifier(uint8_t bus, uint8_t slot, uint8_t fn, uint64_t iova, uint64_t size) "Device %02x:%02x.%x start 0x%"PRIx64" size 0x%"PRIx64 > +smmuv3_context_device_invalidate(uint32_t sid) "sid=%d" > + > -- > 2.5.5 > > -- Linu cherian From MAILER-DAEMON Wed Aug 23 01:22:36 2017 Received: from list by lists.gnu.org with archive (Exim 4.71) id 1dkO7g-00084k-Q5 for mharc-qemu-arm@gnu.org; Wed, 23 Aug 2017 01:22:36 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:36212) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dkO7d-00082b-Vv for qemu-arm@nongnu.org; Wed, 23 Aug 2017 01:22:34 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dkO7a-0005eQ-1b for qemu-arm@nongnu.org; Wed, 23 Aug 2017 01:22:33 -0400 Received: from mx1.redhat.com ([209.132.183.28]:40166) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1dkO7Z-0005dv-RA; Wed, 23 Aug 2017 01:22:29 -0400 Received: from smtp.corp.redhat.com (int-mx02.intmail.prod.int.phx2.redhat.com [10.5.11.12]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id 6F6A780B2A; Wed, 23 Aug 2017 05:22:28 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mx1.redhat.com 6F6A780B2A Authentication-Results: ext-mx04.extmail.prod.ext.phx2.redhat.com; dmarc=none (p=none dis=none) header.from=redhat.com Authentication-Results: ext-mx04.extmail.prod.ext.phx2.redhat.com; spf=fail smtp.mailfrom=thuth@redhat.com Received: from [10.36.116.93] (ovpn-116-93.ams2.redhat.com [10.36.116.93]) by smtp.corp.redhat.com (Postfix) with ESMTPS id A59F0619A0; Wed, 23 Aug 2017 05:22:26 +0000 (UTC) To: KONRAD Frederic Cc: Peter Maydell , qemu-arm@nongnu.org, qemu-devel@nongnu.org, "Edgar E. Iglesias" , Alistair Francis , qemu-trivial@nongnu.org References: <1503414375-21009-1-git-send-email-thuth@redhat.com> <27da1dae-1e2f-559a-d8f0-c7e15289363e@adacore.com> From: Thomas Huth Message-ID: Date: Wed, 23 Aug 2017 07:22:25 +0200 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.2.0 MIME-Version: 1.0 In-Reply-To: <27da1dae-1e2f-559a-d8f0-c7e15289363e@adacore.com> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 7bit X-Scanned-By: MIMEDefang 2.79 on 10.5.11.12 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.28]); Wed, 23 Aug 2017 05:22:28 +0000 (UTC) X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.132.183.28 Subject: Re: [Qemu-arm] [PATCH] hw/misc/auxbus.c: Mark the aux-to-i2c-bridge device as non-hotpluggable X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 23 Aug 2017 05:22:34 -0000 On 22.08.2017 20:15, KONRAD Frederic wrote: > Hi Thomas, > > Looking to this seems there is a second issue: > The aux-to-i2c-bridge device should connect on a TYPE_AUX_BUS. > > I don't think there isn't any on integratorcp.. > > Anyway the patch you sent fix this issue indirectly and as far as > I remember I wasn't able to make this I2C bridge an > TYPE_AUX_DEVICE as it's a special device and it is internal (only > instantiated at the bus creation). If it is intended to be completely internal only (i.e. also not for use with the "-device" parameter), then it should even be marked with "user_creatable = false"! ... if you got some spare minutes, could you maybe sent a patch for that? I'm not familiar with that code, so I'm always having trouble to give the reasoning for setting a "user_creatable = false" somewhere... Thanks, Thomas From MAILER-DAEMON Wed Aug 23 02:47:12 2017 Received: from list by lists.gnu.org with archive (Exim 4.71) id 1dkPRY-0000aL-7B for mharc-qemu-arm@gnu.org; Wed, 23 Aug 2017 02:47:12 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:49266) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dkPRU-0000Zr-Ar for qemu-arm@nongnu.org; Wed, 23 Aug 2017 02:47:10 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dkPRQ-0005Mu-9O for qemu-arm@nongnu.org; Wed, 23 Aug 2017 02:47:08 -0400 Received: from mx1.redhat.com ([209.132.183.28]:57214) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1dkPRQ-0005M2-0B; Wed, 23 Aug 2017 02:47:04 -0400 Received: from smtp.corp.redhat.com (int-mx04.intmail.prod.int.phx2.redhat.com [10.5.11.14]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id 1E51581DE7; Wed, 23 Aug 2017 06:39:30 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mx1.redhat.com 1E51581DE7 Authentication-Results: ext-mx01.extmail.prod.ext.phx2.redhat.com; dmarc=none (p=none dis=none) header.from=redhat.com Authentication-Results: ext-mx01.extmail.prod.ext.phx2.redhat.com; spf=fail smtp.mailfrom=eric.auger@redhat.com Received: from localhost.localdomain (ovpn-116-92.ams2.redhat.com [10.36.116.92]) by smtp.corp.redhat.com (Postfix) with ESMTPS id 9DECB17AF5; Wed, 23 Aug 2017 06:39:19 +0000 (UTC) To: Linu Cherian References: <1502461354-11327-1-git-send-email-eric.auger@redhat.com> <1502461354-11327-9-git-send-email-eric.auger@redhat.com> <20170823042453.GA4682@virtx40> Cc: peter.maydell@linaro.org, drjones@redhat.com, tcain@qti.qualcomm.com, Radha.Chintakuntla@cavium.com, Sunil.Goutham@cavium.com, mohun106@gmail.com, jean-philippe.brucker@arm.com, tn@semihalf.com, bharat.bhushan@nxp.com, mst@redhat.com, will.deacon@arm.com, qemu-devel@nongnu.org, peterx@redhat.com, alex.williamson@redhat.com, qemu-arm@nongnu.org, christoffer.dall@linaro.org, linu.cherian@cavium.com, robin.murphy@arm.com, prem.mallappa@gmail.com, eric.auger.pro@gmail.com From: Auger Eric Message-ID: Date: Wed, 23 Aug 2017 08:39:18 +0200 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:45.0) Gecko/20100101 Thunderbird/45.4.0 MIME-Version: 1.0 In-Reply-To: <20170823042453.GA4682@virtx40> Content-Type: text/plain; charset=windows-1252 Content-Transfer-Encoding: 7bit X-Scanned-By: MIMEDefang 2.79 on 10.5.11.14 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.25]); Wed, 23 Aug 2017 06:39:30 +0000 (UTC) X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.132.183.28 Subject: Re: [Qemu-arm] [Qemu-devel] [RFC v6 8/9] hw/arm/smmuv3: VFIO integration X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 23 Aug 2017 06:47:10 -0000 Hi Linu, On 23/08/2017 06:24, Linu Cherian wrote: > Hi Eric, > > > On Fri Aug 11, 2017 at 04:22:33PM +0200, Eric Auger wrote: >> This patch allows doing PCIe passthrough with a guest exposed >> with a vSMMUv3. It implements the replay and notify_flag_changed >> iommu ops. Also on TLB and data structure invalidation commands, >> we replay the mappings so that the physical IOMMU implements >> updated stage 1 settings (Guest IOVA -> Guest PA) + stage 2 settings. >> >> This works only if the guest smmuv3 driver implements the >> "tlbi-on-map" option. >> >> Signed-off-by: Eric Auger > > Tried out launching a guest with Qemu option "-machine virt-2.10,smmu" > and a 1G Ethernet controller as vfio-pci device. It works fine for me. Hum sorry, I forgot to update the cover letter. You need to use -machine virt-2.11,smmu for the instantiation as the 2.10 machine was released as part of 2.10 and those changes only apply on 2.11 mach virt introduced in this series. Please apologize for the pain. I am going to release a new version this week fixing my last DPDK bug (at least I am aware of ). In this new version, the instantiation method will change to -device smmuv3 which is closer to what is done on Intel. By the way I will also take time to provide some more info about the VFIO integration as it is implemented in this series although this latter may evolve due to NAK of kernel FW quirk. Thank you for testing! Best Regards Eric > > Qemu source: https://github.com/eauger/qemu.git Branch: v2.10.0-rc2-SMMU-v6 > > But had to make this change, > > --- a/hw/arm/virt.c > +++ b/hw/arm/virt.c > @@ -1806,7 +1806,7 @@ static void virt_machine_2_10_options(MachineClass *mc) > virt_machine_2_11_options(mc); > SET_MACHINE_COMPAT(mc, VIRT_COMPAT_2_10); > > - vmc->no_smmu = true; > + vmc->no_smmu = false; > } > DEFINE_VIRT_MACHINE(2, 10) > > so that qemu doesnt complain about "Property .smmu not found" > > Will let you know if i have updates on further testing. > > Thanks. > >> >> --- >> >> v5 -> v6: >> - use IOMMUMemoryRegion >> - handle implementation defined SMMU_CMD_TLBI_NH_VA_AM cmd >> (goes along with TLBI_ON_MAP FW quirk) >> - replay systematically unmap the whole range first >> - smmuv3_map_hook does not unmap anymore and the unmap is done >> before the replay >> - add and use smmuv3_context_device_invalidate instead of >> blindly replaying everything >> --- >> hw/arm/smmuv3-internal.h | 1 + >> hw/arm/smmuv3.c | 265 ++++++++++++++++++++++++++++++++++++++++++++++- >> hw/arm/trace-events | 14 +++ >> 3 files changed, 277 insertions(+), 3 deletions(-) >> >> diff --git a/hw/arm/smmuv3-internal.h b/hw/arm/smmuv3-internal.h >> index e255df1..ac4628f 100644 >> --- a/hw/arm/smmuv3-internal.h >> +++ b/hw/arm/smmuv3-internal.h >> @@ -344,6 +344,7 @@ enum { >> SMMU_CMD_RESUME = 0x44, >> SMMU_CMD_STALL_TERM, >> SMMU_CMD_SYNC, /* 0x46 */ >> + SMMU_CMD_TLBI_NH_VA_AM = 0x8F, /* VIOMMU Impl Defined */ >> }; >> >> static const char *cmd_stringify[] = { >> diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c >> index e195a0e..89fb116 100644 >> --- a/hw/arm/smmuv3.c >> +++ b/hw/arm/smmuv3.c >> @@ -25,6 +25,7 @@ >> #include "exec/address-spaces.h" >> #include "trace.h" >> #include "qemu/error-report.h" >> +#include "exec/target_page.h" >> >> #include "hw/arm/smmuv3.h" >> #include "smmuv3-internal.h" >> @@ -143,6 +144,71 @@ static MemTxResult smmu_read_cmdq(SMMUV3State *s, Cmd *cmd) >> return ret; >> } >> >> +static void smmuv3_replay_all(SMMUState *s) >> +{ >> + SMMUNotifierNode *node; >> + >> + QLIST_FOREACH(node, &s->notifiers_list, next) { >> + trace_smmuv3_replay_all(node->sdev->iommu.parent_obj.name); >> + memory_region_iommu_replay_all(&node->sdev->iommu); >> + } >> +} >> + >> +/* Replay the mappings for a given streamid */ >> +static void smmuv3_context_device_invalidate(SMMUState *s, uint16_t sid) >> +{ >> + uint8_t bus_n, devfn; >> + SMMUPciBus *smmu_bus; >> + SMMUDevice *smmu; >> + >> + trace_smmuv3_context_device_invalidate(sid); >> + bus_n = PCI_BUS_NUM(sid); >> + smmu_bus = smmu_find_as_from_bus_num(s, bus_n); >> + if (smmu_bus) { >> + devfn = PCI_FUNC(sid); >> + smmu = smmu_bus->pbdev[devfn]; >> + if (smmu) { >> + memory_region_iommu_replay_all(&smmu->iommu); >> + } >> + } >> +} >> + >> +static void smmuv3_replay_single(IOMMUMemoryRegion *mr, IOMMUNotifier *n, >> + uint64_t iova); >> + >> +static void smmuv3_replay_range(IOMMUMemoryRegion *mr, IOMMUNotifier *n, >> + uint64_t iova, size_t nb_pages); >> + >> +static void smmuv3_notify_single(SMMUState *s, uint64_t iova) >> +{ >> + SMMUNotifierNode *node; >> + >> + QLIST_FOREACH(node, &s->notifiers_list, next) { >> + IOMMUMemoryRegion *mr = &node->sdev->iommu; >> + IOMMUNotifier *n; >> + >> + trace_smmuv3_notify_all(node->sdev->iommu.parent_obj.name, iova); >> + IOMMU_NOTIFIER_FOREACH(n, mr) { >> + smmuv3_replay_single(mr, n, iova); >> + } >> + } >> +} >> + >> +static void smmuv3_notify_range(SMMUState *s, uint64_t iova, size_t size) >> +{ >> + SMMUNotifierNode *node; >> + >> + QLIST_FOREACH(node, &s->notifiers_list, next) { >> + IOMMUMemoryRegion *mr = &node->sdev->iommu; >> + IOMMUNotifier *n; >> + >> + trace_smmuv3_notify_all(node->sdev->iommu.parent_obj.name, iova); >> + IOMMU_NOTIFIER_FOREACH(n, mr) { >> + smmuv3_replay_range(mr, n, iova, size); >> + } >> + } >> +} >> + >> static int smmu_cmdq_consume(SMMUV3State *s) >> { >> uint32_t error = SMMU_CMD_ERR_NONE; >> @@ -178,28 +244,38 @@ static int smmu_cmdq_consume(SMMUV3State *s) >> break; >> case SMMU_CMD_PREFETCH_CONFIG: >> case SMMU_CMD_PREFETCH_ADDR: >> + break; >> case SMMU_CMD_CFGI_STE: >> { >> uint32_t streamid = cmd.word[1]; >> >> trace_smmuv3_cmdq_cfgi_ste(streamid); >> - break; >> + smmuv3_context_device_invalidate(&s->smmu_state, streamid); >> + break; >> } >> case SMMU_CMD_CFGI_STE_RANGE: /* same as SMMU_CMD_CFGI_ALL */ >> { >> - uint32_t start = cmd.word[1], range, end; >> + uint32_t start = cmd.word[1], range, end, i; >> >> range = extract32(cmd.word[2], 0, 5); >> end = start + (1 << (range + 1)) - 1; >> trace_smmuv3_cmdq_cfgi_ste_range(start, end); >> + for (i = start; i <= end; i++) { >> + smmuv3_context_device_invalidate(&s->smmu_state, i); >> + } >> break; >> } >> case SMMU_CMD_CFGI_CD: >> case SMMU_CMD_CFGI_CD_ALL: >> + { >> + uint32_t streamid = cmd.word[1]; >> + >> + smmuv3_context_device_invalidate(&s->smmu_state, streamid); >> break; >> + } >> case SMMU_CMD_TLBI_NH_ALL: >> case SMMU_CMD_TLBI_NH_ASID: >> - printf("%s TLBI* replay\n", __func__); >> + smmuv3_replay_all(&s->smmu_state); >> break; >> case SMMU_CMD_TLBI_NH_VA: >> { >> @@ -210,6 +286,20 @@ static int smmu_cmdq_consume(SMMUV3State *s) >> uint64_t addr = high << 32 | (low << 12); >> >> trace_smmuv3_cmdq_tlbi_nh_va(asid, vmid, addr); >> + smmuv3_notify_single(&s->smmu_state, addr); >> + break; >> + } >> + case SMMU_CMD_TLBI_NH_VA_AM: >> + { >> + int asid = extract32(cmd.word[1], 16, 16); >> + int am = extract32(cmd.word[1], 0, 16); >> + uint64_t low = extract32(cmd.word[2], 12, 20); >> + uint64_t high = cmd.word[3]; >> + uint64_t addr = high << 32 | (low << 12); >> + size_t size = am << 12; >> + >> + trace_smmuv3_cmdq_tlbi_nh_va_am(asid, am, addr, size); >> + smmuv3_notify_range(&s->smmu_state, addr, size); >> break; >> } >> case SMMU_CMD_TLBI_NH_VAA: >> @@ -222,6 +312,7 @@ static int smmu_cmdq_consume(SMMUV3State *s) >> case SMMU_CMD_TLBI_S12_VMALL: >> case SMMU_CMD_TLBI_S2_IPA: >> case SMMU_CMD_TLBI_NSNH_ALL: >> + smmuv3_replay_all(&s->smmu_state); >> break; >> case SMMU_CMD_ATC_INV: >> case SMMU_CMD_PRI_RESP: >> @@ -804,6 +895,172 @@ out: >> return entry; >> } >> >> +static int smmuv3_replay_hook(IOMMUTLBEntry *entry, void *private) >> +{ >> + trace_smmuv3_replay_hook(entry->iova, entry->translated_addr, >> + entry->addr_mask, entry->perm); >> + memory_region_notify_one((IOMMUNotifier *)private, entry); >> + return 0; >> +} >> + >> +static int smmuv3_map_hook(IOMMUTLBEntry *entry, void *private) >> +{ >> + trace_smmuv3_map_hook(entry->iova, entry->translated_addr, >> + entry->addr_mask, entry->perm); >> + memory_region_notify_one((IOMMUNotifier *)private, entry); >> + return 0; >> +} >> + >> +/* Unmap the whole range in the notifier's scope. */ >> +static void smmuv3_unmap_notifier(SMMUDevice *sdev, IOMMUNotifier *n) >> +{ >> + IOMMUTLBEntry entry; >> + hwaddr size; >> + hwaddr start = n->start; >> + hwaddr end = n->end; >> + >> + size = end - start + 1; >> + >> + entry.target_as = &address_space_memory; >> + /* Adjust iova for the size */ >> + entry.iova = n->start & ~(size - 1); >> + /* This field is meaningless for unmap */ >> + entry.translated_addr = 0; >> + entry.perm = IOMMU_NONE; >> + entry.addr_mask = size - 1; >> + >> + /* TODO: check start/end/size/mask */ >> + >> + trace_smmuv3_unmap_notifier(pci_bus_num(sdev->bus), >> + PCI_SLOT(sdev->devfn), >> + PCI_FUNC(sdev->devfn), >> + entry.iova, size); >> + >> + memory_region_notify_one(n, &entry); >> +} >> + >> +static void smmuv3_replay(IOMMUMemoryRegion *mr, IOMMUNotifier *n) >> +{ >> + SMMUDevice *sdev = container_of(mr, SMMUDevice, iommu); >> + SMMUV3State *s = sdev->smmu; >> + SMMUBaseClass *sbc = SMMU_DEVICE_GET_CLASS(s); >> + SMMUTransCfg cfg = {}; >> + int ret; >> + >> + smmuv3_unmap_notifier(sdev, n); >> + >> + ret = smmuv3_decode_config(mr, &cfg); >> + if (ret) { >> + error_report("%s error decoding the configuration for iommu mr=%s", >> + __func__, mr->parent_obj.name); >> + } >> + >> + if (cfg.disabled || cfg.bypassed) { >> + return; >> + } >> + /* is the smmu enabled */ >> + sbc->page_walk_64(&cfg, 0, (1ULL << (64 - cfg.tsz)) - 1, false, >> + smmuv3_replay_hook, n); >> +} >> +static void smmuv3_replay_range(IOMMUMemoryRegion *mr, IOMMUNotifier *n, >> + uint64_t iova, size_t size) >> +{ >> + SMMUDevice *sdev = container_of(mr, SMMUDevice, iommu); >> + SMMUV3State *s = sdev->smmu; >> + SMMUBaseClass *sbc = SMMU_DEVICE_GET_CLASS(s); >> + SMMUTransCfg cfg = {}; >> + IOMMUTLBEntry entry; >> + int ret; >> + >> + trace_smmuv3_replay_range(mr->parent_obj.name, iova, size, n); >> + ret = smmuv3_decode_config(mr, &cfg); >> + if (ret) { >> + error_report("%s error decoding the configuration for iommu mr=%s", >> + __func__, mr->parent_obj.name); >> + } >> + >> + if (cfg.disabled || cfg.bypassed) { >> + return; >> + } >> + >> + /* first unmap */ >> + entry.target_as = &address_space_memory; >> + entry.iova = iova & ~(size - 1); >> + entry.addr_mask = size - 1; >> + entry.perm = IOMMU_NONE; >> + >> + memory_region_notify_one(n, &entry); >> + >> + /* then figure out if a new mapping needs to be applied */ >> + sbc->page_walk_64(&cfg, iova, iova + entry.addr_mask , false, >> + smmuv3_map_hook, n); >> +} >> + >> +static void smmuv3_replay_single(IOMMUMemoryRegion *mr, IOMMUNotifier *n, >> + uint64_t iova) >> +{ >> + SMMUDevice *sdev = container_of(mr, SMMUDevice, iommu); >> + SMMUV3State *s = sdev->smmu; >> + size_t target_page_size = qemu_target_page_size(); >> + SMMUBaseClass *sbc = SMMU_DEVICE_GET_CLASS(s); >> + SMMUTransCfg cfg = {}; >> + IOMMUTLBEntry entry; >> + int ret; >> + >> + trace_smmuv3_replay_single(mr->parent_obj.name, iova, n); >> + ret = smmuv3_decode_config(mr, &cfg); >> + if (ret) { >> + error_report("%s error decoding the configuration for iommu mr=%s", >> + __func__, mr->parent_obj.name); >> + } >> + >> + if (cfg.disabled || cfg.bypassed) { >> + return; >> + } >> + >> + /* first unmap */ >> + entry.target_as = &address_space_memory; >> + entry.iova = iova & ~(target_page_size - 1); >> + entry.addr_mask = target_page_size - 1; >> + entry.perm = IOMMU_NONE; >> + >> + memory_region_notify_one(n, &entry); >> + >> + /* then figure out if a new mapping needs to be applied */ >> + sbc->page_walk_64(&cfg, iova, iova + 1, false, >> + smmuv3_map_hook, n); >> +} >> + >> +static void smmuv3_notify_flag_changed(IOMMUMemoryRegion *iommu, >> + IOMMUNotifierFlag old, >> + IOMMUNotifierFlag new) >> +{ >> + SMMUDevice *sdev = container_of(iommu, SMMUDevice, iommu); >> + SMMUV3State *s3 = sdev->smmu; >> + SMMUState *s = &(s3->smmu_state); >> + SMMUNotifierNode *node = NULL; >> + SMMUNotifierNode *next_node = NULL; >> + >> + if (old == IOMMU_NOTIFIER_NONE) { >> + trace_smmuv3_notify_flag_add(iommu->parent_obj.name); >> + node = g_malloc0(sizeof(*node)); >> + node->sdev = sdev; >> + QLIST_INSERT_HEAD(&s->notifiers_list, node, next); >> + return; >> + } >> + >> + /* update notifier node with new flags */ >> + QLIST_FOREACH_SAFE(node, &s->notifiers_list, next, next_node) { >> + if (node->sdev == sdev) { >> + if (new == IOMMU_NOTIFIER_NONE) { >> + trace_smmuv3_notify_flag_del(iommu->parent_obj.name); >> + QLIST_REMOVE(node, next); >> + g_free(node); >> + } >> + return; >> + } >> + } >> +} >> >> static inline void smmu_update_base_reg(SMMUV3State *s, uint64_t *base, >> uint64_t val) >> @@ -1125,6 +1382,8 @@ static void smmuv3_iommu_memory_region_class_init(ObjectClass *klass, >> IOMMUMemoryRegionClass *imrc = IOMMU_MEMORY_REGION_CLASS(klass); >> >> imrc->translate = smmuv3_translate; >> + imrc->notify_flag_changed = smmuv3_notify_flag_changed; >> + imrc->replay = smmuv3_replay; >> } >> >> static const TypeInfo smmuv3_type_info = { >> diff --git a/hw/arm/trace-events b/hw/arm/trace-events >> index f9b9cbe..8228e26 100644 >> --- a/hw/arm/trace-events >> +++ b/hw/arm/trace-events >> @@ -27,6 +27,7 @@ smmuv3_cmdq_opcode(const char *opcode) "<--- %s" >> smmuv3_cmdq_cfgi_ste(int streamid) " |_ streamid =%d" >> smmuv3_cmdq_cfgi_ste_range(int start, int end) " |_ start=0x%d - end=0x%d" >> smmuv3_cmdq_tlbi_nh_va(int asid, int vmid, uint64_t addr) " |_ asid =%d vmid =%d addr=0x%"PRIx64 >> +smmuv3_cmdq_tlbi_nh_va_am(int asid, int am, size_t size, uint64_t addr) " |_ asid =%d am =%d size=0x%lx addr=0x%"PRIx64 >> smmuv3_cmdq_consume_sev(void) "CMD_SYNC CS=SEV not supported, ignoring" >> smmuv3_cmdq_consume_out(uint8_t prod_wrap, uint32_t prod, uint8_t cons_wrap, uint32_t cons) "prod_wrap:%d, prod:0x%x cons_wrap:%d cons:0x%x" >> smmuv3_update(bool is_empty, uint32_t prod, uint32_t cons, uint8_t prod_wrap, uint8_t cons_wrap) "q empty:%d prod:%d cons:%d p.wrap:%d p.cons:%d" >> @@ -50,3 +51,16 @@ smmuv3_dump_ste(int i, uint32_t word0, int j, uint32_t word1) "STE[%2d]: 0x%x\t >> smmuv3_dump_cd(int i, uint32_t word0, int j, uint32_t word1) "CD[%2d]: 0x%x\t CD[%2d]: 0x%x" >> smmuv3_dump_cmd(int i, uint32_t word0, int j, uint32_t word1) "CMD[%2d]: 0x%x\t CMD[%2d]: 0x%x" >> smmuv3_cfg_stage(int s, uint32_t oas, uint32_t tsz, uint64_t ttbr, bool aa64, uint32_t granule_sz, int initial_level) "TransCFG stage:%d oas:%d tsz:%d ttbr:0x%"PRIx64" aa64:%d granule_sz:%d, initial_level = %d" >> + >> +smmuv3_replay(uint16_t sid, bool enabled) "sid=%d, enabled=%d" >> +smmuv3_replay_hook(hwaddr iova, hwaddr pa, hwaddr mask, int perm) "iova=0x%"PRIx64" pa=0x%" PRIx64" mask=0x%"PRIx64" perm=%d" >> +smmuv3_map_hook(hwaddr iova, hwaddr pa, hwaddr mask, int perm) "iova=0x%"PRIx64" pa=0x%" PRIx64" mask=0x%"PRIx64" perm=%d" >> +smmuv3_notify_flag_add(const char *iommu) "ADD SMMUNotifier node for iommu mr=%s" >> +smmuv3_notify_flag_del(const char *iommu) "DEL SMMUNotifier node for iommu mr=%s" >> +smmuv3_replay_single(const char *name, uint64_t iova, void *n) "iommu mr=%s iova=0x%"PRIx64" n=%p" >> +smmuv3_replay_range(const char *name, uint64_t iova, size_t size, void *n) "iommu mr=%s iova=0x%"PRIx64" size=0x%lx n=%p" >> +smmuv3_replay_all(const char *name) "iommu mr=%s" >> +smmuv3_notify_all(const char *name, uint64_t iova) "iommu mr=%s iova=0x%"PRIx64 >> +smmuv3_unmap_notifier(uint8_t bus, uint8_t slot, uint8_t fn, uint64_t iova, uint64_t size) "Device %02x:%02x.%x start 0x%"PRIx64" size 0x%"PRIx64 >> +smmuv3_context_device_invalidate(uint32_t sid) "sid=%d" >> + >> -- >> 2.5.5 >> >> > From MAILER-DAEMON Wed Aug 23 12:42:17 2017 Received: from list by lists.gnu.org with archive (Exim 4.71) id 1dkYjQ-0008Cf-TK for mharc-qemu-arm@gnu.org; Wed, 23 Aug 2017 12:42:16 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:50495) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dkYjN-00089x-Tw for qemu-arm@nongnu.org; Wed, 23 Aug 2017 12:42:14 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dkYjM-0000zn-VU for qemu-arm@nongnu.org; Wed, 23 Aug 2017 12:42:13 -0400 Received: from mx1.redhat.com ([209.132.183.28]:52868) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1dkYjM-0000zZ-Oa; Wed, 23 Aug 2017 12:42:12 -0400 Received: from smtp.corp.redhat.com (int-mx02.intmail.prod.int.phx2.redhat.com [10.5.11.12]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id 4FD816197E; Wed, 23 Aug 2017 16:42:11 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mx1.redhat.com 4FD816197E Authentication-Results: ext-mx09.extmail.prod.ext.phx2.redhat.com; dmarc=none (p=none dis=none) header.from=redhat.com Authentication-Results: ext-mx09.extmail.prod.ext.phx2.redhat.com; spf=fail smtp.mailfrom=eric.auger@redhat.com Received: from localhost.localdomain (ovpn-116-92.ams2.redhat.com [10.36.116.92]) by smtp.corp.redhat.com (Postfix) with ESMTPS id F006493BB6; Wed, 23 Aug 2017 16:41:36 +0000 (UTC) To: Bharat Bhushan , eric.auger.pro@gmail.com, peter.maydell@linaro.org, alex.williamson@redhat.com, mst@redhat.com, qemu-arm@nongnu.org, qemu-devel@nongnu.org References: <1503312534-6642-1-git-send-email-Bharat.Bhushan@nxp.com> Cc: wei@redhat.com, kevin.tian@intel.com, marc.zyngier@arm.com, tn@semihalf.com, will.deacon@arm.com, drjones@redhat.com, robin.murphy@arm.com, christoffer.dall@linaro.org From: Auger Eric Message-ID: <2e23327a-3e5e-abaf-387f-d23462d8aba7@redhat.com> Date: Wed, 23 Aug 2017 18:41:35 +0200 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:45.0) Gecko/20100101 Thunderbird/45.4.0 MIME-Version: 1.0 In-Reply-To: <1503312534-6642-1-git-send-email-Bharat.Bhushan@nxp.com> Content-Type: text/plain; charset=windows-1252 Content-Transfer-Encoding: 7bit X-Scanned-By: MIMEDefang 2.79 on 10.5.11.12 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.38]); Wed, 23 Aug 2017 16:42:11 +0000 (UTC) X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.132.183.28 Subject: Re: [Qemu-arm] [PATCH v3 0/2] virtio-iommu: VFIO integration X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 23 Aug 2017 16:42:15 -0000 Hi Bharat, On 21/08/2017 12:48, Bharat Bhushan wrote: > This V3 version is mainly about rebasing on v3 version on Virtio-iommu device > framework from Eric Augur and addresing review comments. s/Augur/Auger ;-) > > This patch series allows PCI pass-through using virtio-iommu. > > This series is based on: > - virtio-iommu specification written by Jean-Philippe Brucker > [RFC 0/3] virtio-iommu: a paravirtualized IOMMU, > > - virtio-iommu driver by Jean-Philippe Brucker > [RFC PATCH linux] iommu: Add virtio-iommu driver > > - virtio-iommu device emulation by Eric Augur. > [RFC v3 0/8] VIRTIO-IOMMU device > > PCI device pass-through and virtio-net-pci is tested with these changes using dma-ops I confirm it works fine now with 2 assigned VFs. However at the moment DPDK testpmd using those 2 VFs does not work for me: 1: [/home/augere/UPSTREAM/dpdk/install/bin/testpmd(rte_dump_stack+0x24) [0x4a8a78]] I haven't investigated yet... Thanks Eric > > This patch series does not implement RESV_MEM changes proposal by Jean-Philippe "https://lists.gnu.org/archive/html/qemu-devel/2017-07/msg01796.html" > > v2->v3: > - This series is based on "[RFC v3 0/8] VIRTIO-IOMMU device" > Which is based on top of v2.10-rc0 that > - Fixed issue with two PCI devices > - Addressed review comments > > v1->v2: > - Added trace events > - removed vSMMU3 link in patch description > > Bharat Bhushan (2): > target/arm/kvm: Translate the MSI doorbell in kvm_arch_fixup_msi_route > virtio-iommu: vfio integration with virtio-iommu > > hw/virtio/trace-events | 5 ++ > hw/virtio/virtio-iommu.c | 163 +++++++++++++++++++++++++++++++++++++++ > include/hw/virtio/virtio-iommu.h | 6 ++ > target/arm/kvm.c | 27 +++++++ > target/arm/trace-events | 3 + > 5 files changed, 204 insertions(+) > From MAILER-DAEMON Wed Aug 23 13:21:28 2017 Received: from list by lists.gnu.org with archive (Exim 4.71) id 1dkZLM-0003IY-Lr for mharc-qemu-arm@gnu.org; Wed, 23 Aug 2017 13:21:28 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:59973) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dkZLK-0003Hn-LP for qemu-arm@nongnu.org; Wed, 23 Aug 2017 13:21:27 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dkZLF-00008p-Mu for qemu-arm@nongnu.org; Wed, 23 Aug 2017 13:21:26 -0400 Received: from mx1.redhat.com ([209.132.183.28]:57642) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1dkZLF-000089-GD; Wed, 23 Aug 2017 13:21:21 -0400 Received: from smtp.corp.redhat.com (int-mx01.intmail.prod.int.phx2.redhat.com [10.5.11.11]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id 7D91E806C0; Wed, 23 Aug 2017 17:21:20 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mx1.redhat.com 7D91E806C0 Authentication-Results: ext-mx02.extmail.prod.ext.phx2.redhat.com; dmarc=none (p=none dis=none) header.from=redhat.com Authentication-Results: ext-mx02.extmail.prod.ext.phx2.redhat.com; spf=fail smtp.mailfrom=ehabkost@redhat.com Received: from localhost (ovpn-116-4.gru2.redhat.com [10.97.116.4]) by smtp.corp.redhat.com (Postfix) with ESMTP id 56E558260F; Wed, 23 Aug 2017 17:21:19 +0000 (UTC) Date: Wed, 23 Aug 2017 14:21:18 -0300 From: Eduardo Habkost To: Thomas Huth Cc: Peter Maydell , qemu-arm@nongnu.org, qemu-devel@nongnu.org, Beniamino Galvani Message-ID: <20170823172118.GQ19998@localhost.localdomain> References: <1503416789-32080-1-git-send-email-thuth@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1503416789-32080-1-git-send-email-thuth@redhat.com> X-Fnord: you can see the fnord User-Agent: Mutt/1.8.0 (2017-02-23) X-Scanned-By: MIMEDefang 2.79 on 10.5.11.11 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.26]); Wed, 23 Aug 2017 17:21:20 +0000 (UTC) X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.132.183.28 Subject: Re: [Qemu-arm] [PATCH] hw/arm/allwinner-a10: Mark the allwinner-a10 device with user_creatable = false X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 23 Aug 2017 17:21:27 -0000 On Tue, Aug 22, 2017 at 05:46:29PM +0200, Thomas Huth wrote: > QEMU currently exits unexpectedly when the user accidentially > tries to do something like this: > > $ aarch64-softmmu/qemu-system-aarch64 -S -M integratorcp -nographic > QEMU 2.9.93 monitor - type 'help' for more information > (qemu) device_add allwinner-a10 > Unsupported NIC model: smc91c111 > > Exiting just due to a "device_add" should not happen. Looking closer > at the the realize and instance_init function of this device also > reveals that it is using serial_hds and nd_table directly there, so > this device is clearly not creatable by the user and should be marked > accordingly. > > Signed-off-by: Thomas Huth > --- > hw/arm/allwinner-a10.c | 2 ++ > scripts/device-crash-test | 1 - > 2 files changed, 2 insertions(+), 1 deletion(-) > > diff --git a/hw/arm/allwinner-a10.c b/hw/arm/allwinner-a10.c > index f62a9a3..43a3f01 100644 > --- a/hw/arm/allwinner-a10.c > +++ b/hw/arm/allwinner-a10.c > @@ -118,6 +118,8 @@ static void aw_a10_class_init(ObjectClass *oc, void *data) > DeviceClass *dc = DEVICE_CLASS(oc); > > dc->realize = aw_a10_realize; > + /* Reason: Uses serial_hds in realize and nd_table in instance_init */ > + dc->user_creatable = false; I assume this patch will be replaced by one changing TYPE_DEVICE to default to user_creatable=false, based on the replies to the hw/misc/auxbus.c patch? > } > > static const TypeInfo aw_a10_type_info = { > diff --git a/scripts/device-crash-test b/scripts/device-crash-test > index 8eb2d02..74aee68 100755 > --- a/scripts/device-crash-test > +++ b/scripts/device-crash-test > @@ -187,7 +187,6 @@ ERROR_WHITELIST = [ > {'log':r"Device [\w.,-]+ can not be dynamically instantiated"}, > {'log':r"Platform Bus: Can not fit MMIO region of size "}, > # other more specific errors we will ignore: > - {'device':'allwinner-a10', 'log':"Unsupported NIC model:"}, > {'device':'.*-spapr-cpu-core', 'log':r"CPU core type should be"}, > {'log':r"MSI(-X)? is not supported by interrupt controller"}, > {'log':r"pxb-pcie? devices cannot reside on a PCIe? bus"}, > -- > 1.8.3.1 > -- Eduardo From MAILER-DAEMON Wed Aug 23 13:51:53 2017 Received: from list by lists.gnu.org with archive (Exim 4.71) id 1dkZon-0000fc-M8 for mharc-qemu-arm@gnu.org; Wed, 23 Aug 2017 13:51:53 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:39860) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dkZol-0000eF-Qq for qemu-arm@nongnu.org; Wed, 23 Aug 2017 13:51:52 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dkZok-0006g3-Uo for qemu-arm@nongnu.org; Wed, 23 Aug 2017 13:51:51 -0400 Received: from mail-wr0-x22b.google.com ([2a00:1450:400c:c0c::22b]:33887) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1dkZok-0006fZ-MV for qemu-arm@nongnu.org; Wed, 23 Aug 2017 13:51:50 -0400 Received: by mail-wr0-x22b.google.com with SMTP id p14so2785444wrg.1 for ; Wed, 23 Aug 2017 10:51:50 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:in-reply-to:references:from:date:message-id:subject:to :cc; bh=8PfwyriEYNa0zGIVRQ6YaRuwPvb+aq0huFvVPvxmpOQ=; b=X6eshzMfQ+6AoLwfQKwdaw9oJ+SUIQwDYAENleRpSaOs0fLVzvwOHw1Pa+2p6uNfeJ rj47mEE3mpxI0xIRHnPeuDm/nI6rHrIUEixjil+iL19uTIXPh9RGFdnOOYOVP9GEpnVX mu7NtsuS8qm0244ofmpiNLJiN0wWxjUv804go= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:in-reply-to:references:from:date :message-id:subject:to:cc; bh=8PfwyriEYNa0zGIVRQ6YaRuwPvb+aq0huFvVPvxmpOQ=; b=nKaa3kZdh4W79iQqc9/FOXMOEVQNAZrr9O0RhPUBvslvva0tBQ2TanldEc+0qRS5SZ 1TnzPbduwmDp0FFNUxz2bw1lh2KWfCxliEbb2cNDdFfd1R/HnPphp5GCCn27j9GDtQUW wVgfyu581ZDrIpL4poS4bIeqz/hs5AC7YNPsHrxUQP3u8OKpaR1LWLT0LkglaQEnq1eX 3D4OfMnk7DfgN5oKkKQ821bECTXyGFOFWw76IMn6Y/3dWX32x/KhZeqzy5+4yEm53Yik eoYrHkuurbgatNDf5SafVSsBpiFUxYXJgWinxOr7ks377CownBPcRbovSBWqsuYak+a5 CzPA== X-Gm-Message-State: AHYfb5iswCL5GPQ1rANEq18XoRLEhKnjoCejCvWgNl9SS0uY52/ic327 tVC9Xor9sT0pJJnhSHLs3e0Pep/3u20Y X-Received: by 10.223.129.135 with SMTP id 7mr1955578wra.11.1503510709451; Wed, 23 Aug 2017 10:51:49 -0700 (PDT) MIME-Version: 1.0 Received: by 10.223.134.54 with HTTP; Wed, 23 Aug 2017 10:51:28 -0700 (PDT) In-Reply-To: <20170823172118.GQ19998@localhost.localdomain> References: <1503416789-32080-1-git-send-email-thuth@redhat.com> <20170823172118.GQ19998@localhost.localdomain> From: Peter Maydell Date: Wed, 23 Aug 2017 18:51:28 +0100 Message-ID: To: Eduardo Habkost Cc: Thomas Huth , qemu-arm , QEMU Developers , Beniamino Galvani Content-Type: text/plain; charset="UTF-8" X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:400c:c0c::22b Subject: Re: [Qemu-arm] [PATCH] hw/arm/allwinner-a10: Mark the allwinner-a10 device with user_creatable = false X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 23 Aug 2017 17:51:52 -0000 On 23 August 2017 at 18:21, Eduardo Habkost wrote: > On Tue, Aug 22, 2017 at 05:46:29PM +0200, Thomas Huth wrote: >> QEMU currently exits unexpectedly when the user accidentially >> tries to do something like this: >> >> $ aarch64-softmmu/qemu-system-aarch64 -S -M integratorcp -nographic >> QEMU 2.9.93 monitor - type 'help' for more information >> (qemu) device_add allwinner-a10 >> Unsupported NIC model: smc91c111 >> >> Exiting just due to a "device_add" should not happen. Looking closer >> at the the realize and instance_init function of this device also >> reveals that it is using serial_hds and nd_table directly there, so >> this device is clearly not creatable by the user and should be marked >> accordingly. >> >> Signed-off-by: Thomas Huth >> --- >> hw/arm/allwinner-a10.c | 2 ++ >> scripts/device-crash-test | 1 - >> 2 files changed, 2 insertions(+), 1 deletion(-) >> >> diff --git a/hw/arm/allwinner-a10.c b/hw/arm/allwinner-a10.c >> index f62a9a3..43a3f01 100644 >> --- a/hw/arm/allwinner-a10.c >> +++ b/hw/arm/allwinner-a10.c >> @@ -118,6 +118,8 @@ static void aw_a10_class_init(ObjectClass *oc, void *data) >> DeviceClass *dc = DEVICE_CLASS(oc); >> >> dc->realize = aw_a10_realize; >> + /* Reason: Uses serial_hds in realize and nd_table in instance_init */ >> + dc->user_creatable = false; > > I assume this patch will be replaced by one changing TYPE_DEVICE > to default to user_creatable=false, based on the replies to the > hw/misc/auxbus.c patch? user-creatable and hotplug are different things -- most devices are user-creatable, many fewer are hotpluggable. So the tradeoff for the default doesn't *necessarily* go the same way. thanks -- PMM From MAILER-DAEMON Wed Aug 23 14:00:48 2017 Received: from list by lists.gnu.org with archive (Exim 4.71) id 1dkZxP-0007Sd-Rp for mharc-qemu-arm@gnu.org; Wed, 23 Aug 2017 14:00:47 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:42008) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dkZxN-0007Qs-63 for qemu-arm@nongnu.org; Wed, 23 Aug 2017 14:00:46 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dkZxI-0002xd-CE for qemu-arm@nongnu.org; Wed, 23 Aug 2017 14:00:45 -0400 Received: from mx1.redhat.com ([209.132.183.28]:36740) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1dkZxI-0002xJ-6N; Wed, 23 Aug 2017 14:00:40 -0400 Received: from smtp.corp.redhat.com (int-mx04.intmail.prod.int.phx2.redhat.com [10.5.11.14]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id 113D2C0587C1; Wed, 23 Aug 2017 18:00:39 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mx1.redhat.com 113D2C0587C1 Authentication-Results: ext-mx08.extmail.prod.ext.phx2.redhat.com; dmarc=none (p=none dis=none) header.from=redhat.com Authentication-Results: ext-mx08.extmail.prod.ext.phx2.redhat.com; spf=fail smtp.mailfrom=ehabkost@redhat.com Received: from localhost (ovpn-116-4.gru2.redhat.com [10.97.116.4]) by smtp.corp.redhat.com (Postfix) with ESMTP id 9C9065D98B; Wed, 23 Aug 2017 18:00:38 +0000 (UTC) Date: Wed, 23 Aug 2017 15:00:37 -0300 From: Eduardo Habkost To: Peter Maydell Cc: Thomas Huth , qemu-arm , QEMU Developers , Beniamino Galvani Message-ID: <20170823180037.GU19998@localhost.localdomain> References: <1503416789-32080-1-git-send-email-thuth@redhat.com> <20170823172118.GQ19998@localhost.localdomain> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: X-Fnord: you can see the fnord User-Agent: Mutt/1.8.0 (2017-02-23) X-Scanned-By: MIMEDefang 2.79 on 10.5.11.14 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.32]); Wed, 23 Aug 2017 18:00:39 +0000 (UTC) X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.132.183.28 Subject: Re: [Qemu-arm] [PATCH] hw/arm/allwinner-a10: Mark the allwinner-a10 device with user_creatable = false X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 23 Aug 2017 18:00:46 -0000 On Wed, Aug 23, 2017 at 06:51:28PM +0100, Peter Maydell wrote: > On 23 August 2017 at 18:21, Eduardo Habkost wrote: > > On Tue, Aug 22, 2017 at 05:46:29PM +0200, Thomas Huth wrote: > >> QEMU currently exits unexpectedly when the user accidentially > >> tries to do something like this: > >> > >> $ aarch64-softmmu/qemu-system-aarch64 -S -M integratorcp -nographic > >> QEMU 2.9.93 monitor - type 'help' for more information > >> (qemu) device_add allwinner-a10 > >> Unsupported NIC model: smc91c111 > >> > >> Exiting just due to a "device_add" should not happen. Looking closer > >> at the the realize and instance_init function of this device also > >> reveals that it is using serial_hds and nd_table directly there, so > >> this device is clearly not creatable by the user and should be marked > >> accordingly. > >> > >> Signed-off-by: Thomas Huth > >> --- > >> hw/arm/allwinner-a10.c | 2 ++ > >> scripts/device-crash-test | 1 - > >> 2 files changed, 2 insertions(+), 1 deletion(-) > >> > >> diff --git a/hw/arm/allwinner-a10.c b/hw/arm/allwinner-a10.c > >> index f62a9a3..43a3f01 100644 > >> --- a/hw/arm/allwinner-a10.c > >> +++ b/hw/arm/allwinner-a10.c > >> @@ -118,6 +118,8 @@ static void aw_a10_class_init(ObjectClass *oc, void *data) > >> DeviceClass *dc = DEVICE_CLASS(oc); > >> > >> dc->realize = aw_a10_realize; > >> + /* Reason: Uses serial_hds in realize and nd_table in instance_init */ > >> + dc->user_creatable = false; > > > > I assume this patch will be replaced by one changing TYPE_DEVICE > > to default to user_creatable=false, based on the replies to the > > hw/misc/auxbus.c patch? > > user-creatable and hotplug are different things -- most > devices are user-creatable, many fewer are hotpluggable. > So the tradeoff for the default doesn't *necessarily* go > the same way. You're right, I mixed things up when reading this patch. Reviewed-by: Eduardo Habkost -- Eduardo From MAILER-DAEMON Wed Aug 23 15:03:02 2017 Received: from list by lists.gnu.org with archive (Exim 4.71) id 1dkave-00017X-M8 for mharc-qemu-arm@gnu.org; Wed, 23 Aug 2017 15:03:02 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:54870) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dkavc-00017C-33 for qemu-arm@nongnu.org; Wed, 23 Aug 2017 15:03:01 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dkavY-0004jd-JS for qemu-arm@nongnu.org; Wed, 23 Aug 2017 15:03:00 -0400 Received: from mail-pg0-x22c.google.com ([2607:f8b0:400e:c05::22c]:34363) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1dkavY-0004iK-Dr for qemu-arm@nongnu.org; Wed, 23 Aug 2017 15:02:56 -0400 Received: by mail-pg0-x22c.google.com with SMTP id s14so3766045pgs.1 for ; Wed, 23 Aug 2017 12:02:54 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=subject:to:cc:references:from:message-id:date:user-agent :mime-version:in-reply-to:content-language:content-transfer-encoding; bh=AaZnFRLqz8QV8y0l804ii/Feh4zZXvTLHkEjsBf7vKM=; b=Is7j7TCWyPhjcQulPwL/wh7nYIVR9snS9oM6A96wqH3EmFGCikmTN9FNTnU5ZScbMw yTuz3BVeSyhynmhdmql85rCeAb1qPeTpXCjoWS4Mh2hI2Rob7GkR2pe/9W2H4qxlCPp6 W2CXH+1XHsUBZuf3l7wdPByPXP+P+8hNBMBRI= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:subject:to:cc:references:from:message-id:date :user-agent:mime-version:in-reply-to:content-language :content-transfer-encoding; bh=AaZnFRLqz8QV8y0l804ii/Feh4zZXvTLHkEjsBf7vKM=; b=XsElHwWzqxIzBrVsZluu5PYOXjEhlAelK0IajMCyPKJvQpJEzOpv30ae4pI91el8SW lMKuHR/yWw1HlME/OodBSLz3lhc+sksEjv2Eu9/IY0Yinyjy5q13y9rrOrDte6ouuIPj GzgKbUJvF/a9nwXDf0adNt5T6MRVY1Ifb0UvuoHzN5lwP5JUqqhUlNAZuXuM4DKbDqZW 4YlK0WhC79eTO59gBgKN2/jG0lsILBr2HpPow0837cB/18upZUom+w5Q51hdozJuaJvl sIUPRDKWrCMdBymYmFIPR7F5IJKZu6Ia9CRdcJrGhcDEjIgejmbfoJhkOwHE8p+77c/f w9dg== X-Gm-Message-State: AHYfb5j449bsCyZNUbCNDmlLgILf/QoVnijDu6FqVA3Ml2vFazbIfei+ tJOmXiHjLAIvx6cuVLZXpA== X-Received: by 10.84.218.68 with SMTP id f4mr4062933plm.214.1503514973682; Wed, 23 Aug 2017 12:02:53 -0700 (PDT) Received: from bigtime.twiddle.net ([172.92.59.166]) by smtp.gmail.com with ESMTPSA id o4sm3763408pga.47.2017.08.23.12.02.50 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 23 Aug 2017 12:02:52 -0700 (PDT) To: =?UTF-8?Q?Alex_Benn=c3=a9e?= Cc: qemu-devel@nongnu.org, qemu-arm@nongnu.org References: <20170817230114.3655-1-richard.henderson@linaro.org> <20170817230114.3655-9-richard.henderson@linaro.org> <87valf4ub7.fsf@linaro.org> From: Richard Henderson Message-ID: Date: Wed, 23 Aug 2017 12:02:47 -0700 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.2.1 MIME-Version: 1.0 In-Reply-To: <87valf4ub7.fsf@linaro.org> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 8bit X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::22c Subject: Re: [Qemu-arm] [PATCH 8/8] tcg/i386: Add vector operations X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 23 Aug 2017 19:03:01 -0000 On 08/22/2017 06:15 AM, Alex Bennée wrote: >> +#ifndef have_avx2 >> + /* There are a number of things we must check before we can be >> + sure of not hitting invalid opcode. */ >> + if (c & bit_OSXSAVE) { >> + unsigned xcrl, xcrh; >> + asm ("xgetbv" : "=a" (xcrl), "=d" (xcrh) : "c" (0)); >> + if (xcrl & 6 == 6) { > > My picky compiler complains: > > /home/alex/lsrc/qemu/qemu.git/tcg/i386/tcg-target.inc.c: In function ‘tcg_target_init’: > /home/alex/lsrc/qemu/qemu.git/tcg/i386/tcg-target.inc.c:3053:22: error: suggest parentheses around comparison in operand of ‘&’ [-Werror=parentheses] > if (xcrl & 6 == 6) { Bah. I forgot that my default build uses -march=native, and my laptop has AVX2, so this bit wouldn't have been compile tested at all. Fixed on the branch. r~ From MAILER-DAEMON Wed Aug 23 15:26:31 2017 Received: from list by lists.gnu.org with archive (Exim 4.71) id 1dkbIN-0003Ta-HV for mharc-qemu-arm@gnu.org; Wed, 23 Aug 2017 15:26:31 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:60252) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dkbIL-0003SC-QW for qemu-arm@nongnu.org; Wed, 23 Aug 2017 15:26:30 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dkbII-0002Lh-Kr for qemu-arm@nongnu.org; Wed, 23 Aug 2017 15:26:29 -0400 Received: from mel.act-europe.fr ([194.98.77.210]:44199 helo=smtp.eu.adacore.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1dkbII-0002LN-Dk; Wed, 23 Aug 2017 15:26:26 -0400 Received: from localhost (localhost [127.0.0.1]) by filtered-smtp.eu.adacore.com (Postfix) with ESMTP id 9675A82439; Wed, 23 Aug 2017 21:26:25 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at eu.adacore.com Received: from smtp.eu.adacore.com ([127.0.0.1]) by localhost (smtp.eu.adacore.com [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id uKLUyB8BwMyu; Wed, 23 Aug 2017 21:26:25 +0200 (CEST) Received: from localhost.localdomain (182667ea.cst.lightpath.net [24.38.103.234]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.eu.adacore.com (Postfix) with ESMTPSA id 4093A8137A; Wed, 23 Aug 2017 21:26:24 +0200 (CEST) To: Thomas Huth Cc: Peter Maydell , qemu-arm@nongnu.org, qemu-devel@nongnu.org, "Edgar E. Iglesias" , Alistair Francis , qemu-trivial@nongnu.org References: <1503414375-21009-1-git-send-email-thuth@redhat.com> <27da1dae-1e2f-559a-d8f0-c7e15289363e@adacore.com> From: KONRAD Frederic Message-ID: Date: Wed, 23 Aug 2017 21:26:23 +0200 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.2.1 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=utf-8; format=flowed Content-Language: en-US Content-Transfer-Encoding: 7bit X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [fuzzy] X-Received-From: 194.98.77.210 Subject: Re: [Qemu-arm] [PATCH] hw/misc/auxbus.c: Mark the aux-to-i2c-bridge device as non-hotpluggable X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 23 Aug 2017 19:26:30 -0000 On 08/23/2017 07:22 AM, Thomas Huth wrote: > On 22.08.2017 20:15, KONRAD Frederic wrote: >> Hi Thomas, >> >> Looking to this seems there is a second issue: >> The aux-to-i2c-bridge device should connect on a TYPE_AUX_BUS. >> >> I don't think there isn't any on integratorcp.. >> >> Anyway the patch you sent fix this issue indirectly and as far as >> I remember I wasn't able to make this I2C bridge an >> TYPE_AUX_DEVICE as it's a special device and it is internal (only >> instantiated at the bus creation). > > If it is intended to be completely internal only (i.e. also not for use > with the "-device" parameter), then it should even be marked with > "user_creatable = false"! ... if you got some spare minutes, could you > maybe sent a patch for that? I'm not familiar with that code, so I'm > always having trouble to give the reasoning for setting a > "user_creatable = false" somewhere... > > Thanks, > Thomas > Ok will do! Thanks, Fred From MAILER-DAEMON Wed Aug 23 16:29:40 2017 Received: from list by lists.gnu.org with archive (Exim 4.71) id 1dkcHU-0008SE-CL for mharc-qemu-arm@gnu.org; Wed, 23 Aug 2017 16:29:40 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:43058) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dkcHQ-0008Om-Al for qemu-arm@nongnu.org; Wed, 23 Aug 2017 16:29:39 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dkcHN-0008GL-KV for qemu-arm@nongnu.org; Wed, 23 Aug 2017 16:29:36 -0400 Received: from mail-pg0-x241.google.com ([2607:f8b0:400e:c05::241]:33288) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1dkcHG-0008CL-6V; Wed, 23 Aug 2017 16:29:26 -0400 Received: by mail-pg0-x241.google.com with SMTP id 189so679719pgj.0; Wed, 23 Aug 2017 13:29:24 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=date:from:to:cc:subject:message-id:references:mime-version :content-disposition:in-reply-to:user-agent; bh=ooqqCbGesu+jqE5bvsOt8RigjRMCS/ktfPfPll1YPOI=; b=XMsYBscu91gEm2hAEHNQe3qY/CHFffcHIZXslQRXp2X2fr0SInvZk0NCBfsTv+UKi7 h3CCvYol4QpFyYz5OT4ZqUeDr3GncKVzMz5T/bgprmWjOV5xTK+D38xFjW3edPvadhyy 7Vu6orhNtObaWh4XCotJd7UvLWXpELYxiOqif2Hp+sS8Z7/jB0YlYnQUVNjl6pMd5VjF tPOe7d4516Ja7L1SAAAixuUPugpkkkb/zKu0IC9aFUun0ARo4+Mny9gNnsc1G4scPxMH fcjtgS7JU5oqEJuSXAE3KA2ac1VA+1aRJ678K3hydxjfq5cEJmJ6SiICcXtCc80CeaJS JH+g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:in-reply-to:user-agent; bh=ooqqCbGesu+jqE5bvsOt8RigjRMCS/ktfPfPll1YPOI=; b=e2LKs7Pp7lTj4nQsaVgZOcOl1EnCWN6/vWjkt8wPKXnYHqUaoW4z/Ym5/c18sZohUz 2cMu/T7uwFR+hJvRKJHRKrfe8GqzSlik0rZJJIlzNiDw128+9v17s6F/guQmy9Q0TtYk UbT5N32J/25j9vkiJhKLV/fShWCQHNxOppcXIDccoA/cPbRXKIu+eT/xNtqToHOiUE1V Dqxy5xCsS6cV/y2t/qyrR8D7Cq+vwfSUsZWhF/iVhDvMsC9K5Jj9t9Gen1WLzjHgi66s PZdGyJuGP3cjUF66+uLN9BwJ+jQoz7gmiFXmTGsBNYmk3YzvuWyI3ZszVfJCEiXfdujZ x4Lg== X-Gm-Message-State: AHYfb5gVHGAIDGe+52HTG+YaWAgF2XmEOECLHr+2AAUYhWxftI5gizOa 7wUhu09ect/4Ow== X-Received: by 10.98.75.2 with SMTP id y2mr4052387pfa.193.1503520163389; Wed, 23 Aug 2017 13:29:23 -0700 (PDT) Received: from localhost ([149.199.62.254]) by smtp.gmail.com with ESMTPSA id a22sm4542887pfj.94.2017.08.23.13.29.21 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 23 Aug 2017 13:29:22 -0700 (PDT) Date: Thu, 24 Aug 2017 03:09:27 +0700 From: "Edgar E. Iglesias" To: "Michael S. Tsirkin" Cc: Diana Madalina Craciun , Auger Eric , "qemu-devel@nongnu.org" , Mike Caraman , "qemu-arm@nongnu.org" , "marcel@redhat.com" , Bharat Bhushan , "christoffer.dall@linaro.org" , Laurentiu Tudor Message-ID: <20170823200927.GA9911@toto> References: <1495537965-4187-1-git-send-email-diana.craciun@nxp.com> <1495537965-4187-3-git-send-email-diana.craciun@nxp.com> <20170731151602.GU4859@toto> <20170811155027.GO4859@toto> <20170822214318-mutt-send-email-mst@kernel.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20170822214318-mutt-send-email-mst@kernel.org> User-Agent: Mutt/1.5.24 (2015-08-30) X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::241 Subject: Re: [Qemu-arm] [Qemu-devel] [PATCH v2 2/2] Add a unique ID in the virt machine to be used as device ID X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 23 Aug 2017 20:29:39 -0000 On Tue, Aug 22, 2017 at 10:04:25PM +0300, Michael S. Tsirkin wrote: > On Tue, Aug 22, 2017 at 03:13:57PM +0000, Diana Madalina Craciun wrote: > > On 08/11/2017 06:50 PM, Edgar E. Iglesias wrote: > > > On Fri, Aug 11, 2017 at 02:35:28PM +0000, Diana Madalina Craciun wrote: > > >> Hi Edgar, > > >> > > >> On 07/31/2017 06:16 PM, Edgar E. Iglesias wrote: > > >>> On Wed, Jul 26, 2017 at 02:22:28PM +0200, Auger Eric wrote: > > >>>> Hi Diana, > > >>>> On 23/05/2017 13:12, Diana Craciun wrote: > > >>>>> Device IDs are required by the ARM GICv3 ITS for IRQ remapping. > > >>>>> Currently, for PCI devices, the requester ID was used as device > > >>>>> ID in the virt machine. If the system has multiple masters that > > >>>> if the system has multiple root complex? > > >>>>> use MSIs a unique ID accross the platform is needed. > > >>>> across > > >>>>> A static scheme is used and each master is allocated a range of IDs > > >>>>> with the formula: > > >>>>> DeviceID = zero_extend( RequesterID[15:0] ) + 0x10000*Constant (as > > >>>>> recommended by SBSA). > > >>>>> > > >>>>> This ID will be configured in the machine creation and if not configured > > >>>>> the PCI requester ID will be used insteead. > > >>>> instead > > >>>>> Signed-off-by: Diana Craciun > > >>>>> --- > > >>>>> hw/arm/virt.c | 26 ++++++++++++++++++++++++++ > > >>>>> hw/pci-host/gpex.c | 6 ++++++ > > >>>>> hw/pci/msi.c | 2 +- > > >>>>> hw/pci/pci.c | 25 +++++++++++++++++++++++++ > > >>>>> include/hw/arm/virt.h | 1 + > > >>>>> include/hw/pci-host/gpex.h | 2 ++ > > >>>>> include/hw/pci/pci.h | 8 ++++++++ > > >>>>> kvm-all.c | 4 ++-- > > >>>>> 8 files changed, 71 insertions(+), 3 deletions(-) > > >>>>> > > >>>>> diff --git a/hw/arm/virt.c b/hw/arm/virt.c > > >>>>> index 5f62a03..a969694 100644 > > >>>>> --- a/hw/arm/virt.c > > >>>>> +++ b/hw/arm/virt.c > > >>>>> @@ -110,6 +110,8 @@ static ARMPlatformBusSystemParams platform_bus_params; > > >>>>> #define RAMLIMIT_GB 255 > > >>>>> #define RAMLIMIT_BYTES (RAMLIMIT_GB * 1024ULL * 1024 * 1024) > > >>>>> > > >>>>> +#define STREAM_ID_RANGE_SIZE 0x10000 > > >>>>> + > > >>>>> /* Addresses and sizes of our components. > > >>>>> * 0..128MB is space for a flash device so we can run bootrom code such as UEFI. > > >>>>> * 128MB..256MB is used for miscellaneous device I/O. > > >>>>> @@ -162,6 +164,22 @@ static const int a15irqmap[] = { > > >>>>> [VIRT_PLATFORM_BUS] = 112, /* ...to 112 + PLATFORM_BUS_NUM_IRQS -1 */ > > >>>>> }; > > >>>>> > > >>>>> +/* Device IDs are required by the ARM GICV3 ITS for IRQ remapping. Currently > > >>>>> + * for PCI devices the requester ID was used as device ID. But if the system has > > >>>>> + * multiple masters that use MSIs, the requester ID may cause deviceID clashes. > > >>>>> + * So a unique number is needed accross the system. > > >>>>> + * We are using the following formula: > > >>>>> + * DeviceID = zero_extend( RequesterID[15:0] ) + 0x10000*Constant > > >>>>> + * (as recommanded by SBSA). Currently we do not have an SMMU emulation, but the > > >>>>> + * same formula can be used for the generation of the streamID as well. > > >>>>> + * For each master the device ID will be derrived from the requester ID using > > >>>>> + * the abovemntione formula. > > >>>>> + */ > > >>>> I think most of this comment should only be in the commit message. typos > > >>>> in derived and above mentioned. > > >>>> > > >>>> stream id is the terminology for the id space at the input of the smmu. > > >>>> device id is the terminology for the id space at the input of the msi > > >>>> controller I think. > > >>>> > > >>>> RID -> deviceID (no IOMMU) > > >>>> RID -> streamID -> deviceID (IOMMU) > > >>>> > > >>>> I would personally get rid of all streamid uses as the smmu is not yet > > >>>> supported and stick to the > > >>>> Documentation/devicetree/bindings/pci/pci-msi.txt terminology? > > >>>> > > >>>>> + > > >>>>> +static const uint32_t streamidmap[] = { > > >>>>> + [VIRT_PCIE] = 0, /* currently only one PCI controller */ > > >>>>> +}; > > >>>>> + > > >>>>> static const char *valid_cpus[] = { > > >>>>> "cortex-a15", > > >>>>> "cortex-a53", > > >>>>> @@ -980,6 +998,7 @@ static void create_pcie(const VirtMachineState *vms, qemu_irq *pic) > > >>>>> hwaddr base_ecam = vms->memmap[VIRT_PCIE_ECAM].base; > > >>>>> hwaddr size_ecam = vms->memmap[VIRT_PCIE_ECAM].size; > > >>>>> hwaddr base = base_mmio; > > >>>>> + uint32_t stream_id = vms->streamidmap[VIRT_PCIE] * STREAM_ID_RANGE_SIZE; > > >>>> msi-base? > > >>>> STREAM_ID_RANGE_SIZE ~ MSI_MAP_LENGTH? > > >>>>> int nr_pcie_buses = size_ecam / PCIE_MMCFG_SIZE_MIN; > > >>>>> int irq = vms->irqmap[VIRT_PCIE]; > > >>>>> MemoryRegion *mmio_alias; > > >>>>> @@ -992,6 +1011,7 @@ static void create_pcie(const VirtMachineState *vms, qemu_irq *pic) > > >>>>> PCIHostState *pci; > > >>>>> > > >>>>> dev = qdev_create(NULL, TYPE_GPEX_HOST); > > >>>>> + qdev_prop_set_uint32(dev, "stream-id-base", stream_id); > > >>>>> qdev_init_nofail(dev); > > >>>>> > > >>>>> /* Map only the first size_ecam bytes of ECAM space */ > > >>>>> @@ -1056,6 +1076,11 @@ static void create_pcie(const VirtMachineState *vms, qemu_irq *pic) > > >>>>> if (vms->msi_phandle) { > > >>>>> qemu_fdt_setprop_cells(vms->fdt, nodename, "msi-parent", > > >>>>> vms->msi_phandle); > > >>>>> + qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "msi-map", > > >>>>> + 1, 0, > > >>>>> + 1, vms->msi_phandle, > > >>>>> + 1, stream_id, > > >>>>> + 1, STREAM_ID_RANGE_SIZE); > > >>>>> } > > >>>>> > > >>>>> qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg", > > >>>>> @@ -1609,6 +1634,7 @@ static void virt_2_9_instance_init(Object *obj) > > >>>>> > > >>>>> vms->memmap = a15memmap; > > >>>>> vms->irqmap = a15irqmap; > > >>>>> + vms->streamidmap = streamidmap; > > >>>>> } > > >>>>> > > >>>>> static void virt_machine_2_9_options(MachineClass *mc) > > >>>>> diff --git a/hw/pci-host/gpex.c b/hw/pci-host/gpex.c > > >>>>> index 66055ee..de72408 100644 > > >>>>> --- a/hw/pci-host/gpex.c > > >>>>> +++ b/hw/pci-host/gpex.c > > >>>>> @@ -43,6 +43,11 @@ static void gpex_set_irq(void *opaque, int irq_num, int level) > > >>>>> qemu_set_irq(s->irq[irq_num], level); > > >>>>> } > > >>>>> > > >>>>> +static Property gpex_props[] = { > > >>>>> + DEFINE_PROP_UINT32("stream-id-base", GPEXHost, stream_id_base, 0), > > >>>> msi_base_base > > >>>>> + DEFINE_PROP_END_OF_LIST(), > > >>>>> +}; > > >>>>> + > > >>>>> static void gpex_host_realize(DeviceState *dev, Error **errp) > > >>>>> { > > >>>>> PCIHostState *pci = PCI_HOST_BRIDGE(dev); > > >>>>> @@ -83,6 +88,7 @@ static void gpex_host_class_init(ObjectClass *klass, void *data) > > >>>>> > > >>>>> hc->root_bus_path = gpex_host_root_bus_path; > > >>>>> dc->realize = gpex_host_realize; > > >>>>> + dc->props = gpex_props; > > >>>>> set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories); > > >>>>> dc->fw_name = "pci"; > > >>>>> } > > >>>>> diff --git a/hw/pci/msi.c b/hw/pci/msi.c > > >>>>> index 7925851..b60a410 100644 > > >>>>> --- a/hw/pci/msi.c > > >>>>> +++ b/hw/pci/msi.c > > >>>>> @@ -336,7 +336,7 @@ void msi_send_message(PCIDevice *dev, MSIMessage msg) > > >>>>> { > > >>>>> MemTxAttrs attrs = {}; > > >>>>> > > >>>>> - attrs.stream_id = pci_requester_id(dev); > > >>>>> + attrs.stream_id = pci_stream_id(dev); > > >>>>> address_space_stl_le(&dev->bus_master_as, msg.address, msg.data, > > >>>>> attrs, NULL); > > >>>>> } > > >>>>> diff --git a/hw/pci/pci.c b/hw/pci/pci.c > > >>>>> index 259483b..92e9a2b 100644 > > >>>>> --- a/hw/pci/pci.c > > >>>>> +++ b/hw/pci/pci.c > > >>>>> @@ -951,6 +951,30 @@ uint16_t pci_requester_id(PCIDevice *dev) > > >>>>> return pci_req_id_cache_extract(&dev->requester_id_cache); > > >>>>> } > > >>>>> > > >>>>> +static uint32_t pci_get_stream_id_base(PCIDevice *dev) > > >>>>> +{ > > >>>>> + PCIBus *rootbus = pci_device_root_bus(dev); > > >>>>> + PCIHostState *host_bridge = PCI_HOST_BRIDGE(rootbus->qbus.parent); > > >>>>> + Error *err = NULL; > > >>>>> + int64_t stream_id; > > >>>>> + > > >>>>> + stream_id = object_property_get_int(OBJECT(host_bridge), "stream-id-base", > > >>>>> + &err); > > >>>>> + if (stream_id < 0) { > > >>>>> + stream_id = 0; > > >>>>> + } > > >>>>> + > > >>>>> + return stream_id; > > >>>>> +} > > >>>>> + > > >>>>> +uint32_t pci_stream_id(PCIDevice *dev) > > >>>>> +{ > > >>>>> + /* Stream ID = RequesterID[15:0] + stream_id_base. stream_id_base may > > >>>>> + * be 0 for devices that are not using any translation between requester_id > > >>>>> + * and stream_id */ > > >>>>> + return (uint16_t)pci_requester_id(dev) + dev->stream_id_base; > > >>>>> +} > > >>>> I think you should split the changes in virt from pci/gpex generic changes. > > >>>> > > >>>>> + > > >>>>> /* -1 for devfn means auto assign */ > > >>>>> static PCIDevice *do_pci_register_device(PCIDevice *pci_dev, PCIBus *bus, > > >>>>> const char *name, int devfn, > > >>>>> @@ -1000,6 +1024,7 @@ static PCIDevice *do_pci_register_device(PCIDevice *pci_dev, PCIBus *bus, > > >>>>> > > >>>>> pci_dev->devfn = devfn; > > >>>>> pci_dev->requester_id_cache = pci_req_id_cache_get(pci_dev); > > >>>>> + pci_dev->stream_id_base = pci_get_stream_id_base(pci_dev); > > >>>> looks strange to me to store the rid base in the end point as this is > > >>>> rather a property of the PCI complex. I acknowledge this is much more > > >>> I agree. > > >> The reason I have changed was to avoid traversing the entire hierarchy > > >> each time the ID is needed (for example each time when a MSI is sent). > > >> > > >>> I think that what we need is to add support for allowing PCI RCs > > >>> to transform requesterIDs in transactions attributes according to the > > >>> implementation specifics. > > >> Do you mean that you need more than a linear offset between requesterID > > >> and whatever other ID? > > > > > > Yes. > > > > > > This is my understanding for the ARM platforms I'm familiar with: > > > > > > Since AXI busses don't have a defined way to carry Master IDs, these > > > are typically carried on the AXI user signals. I'll just refer to > > > these signals as AXI Master IDs. > > > > > > 1. An endpoint issues an MSI (or any) transaction on the PCI bus. > > > In QEMU, these trasactions carry the requester ID in their attributes. > > > > > > 2. The transaction hits the PCI "host" bridge to the SoC internal > > > interconnect (typically AXI). This bridge needs to forward the > > > PCI transaction onto the AXI bus. Including mapping the PCI > > > RequesterID into an AXI MasterID. > > > > > > 3. The AXI transaction hits the IOMMU and the MasterID is mapped > > > into a streamID to identify the origin of the transaction > > > and apply address translation accordingly. If the SMMU > > > allows the transaction to pass, the stream ID is mapped back > > > into the transactions MasterID. > > > > > > 4. The AXI transaction continues down the interconnect and hits > > > the MSI doorbell and the MasterID is mapped into a DeviceID to > > > identify the origin of the MSI and apply possible interrupt translation. > > > > > > Adding streamID fields to a PCI endpoint doesn't make any sense to me. > > > The requester ID is already there and is IMO enough. > > > StreamIDs are a concept of ARM System MMUs, not of PCI endpoints. > > > > What I have added into the endpoint is actually the Master ID (in QEMU > > it is actually equal with the streamID). I agree that this is a property > > of the root complex, the only reason I have put it into the endpoint was > > to avoid traversing the PCI hierarchy each time an MSI is sent. > > Can all this be folded into the IOMMU? Then you might be able to get by > with defining an iommu function. pci_device_iommu_address_space already > walks the hierarchy. Hmm, perhaps. I guess iommu_fn's would have to be able to return modified transaction attributes. That would work, I think, I was first thinking that if we change the IOMMU translate() method to allow IOMMUs to modify memory attributes, Diana could register an IOMMU memory-region with pci_setup_iommu() that modifies the attributes and returns a new attribute with the AS that originally would have been set with pci_setup_iommu(). Adding support for IOMMU translate() to modify attributes is something we need to do anyway IMO. > > > > > > When modelling #2, hardcoding a specific linear mapping between > > > PCI requester IDs and AXI Master IDs may work for one platform > > > but it won't work for all platforms. There is no one mapping for all. > > > It can even be run-time programmable in the bridge. > > OK but how does it work with the specific bridge that you emulate? > There is no need to model advanced bridges with super flexible > programmable mappings if guests do not need them to run. Diana can answer for the details of the bridge she wants to model. I was mostly trying to make a point that we should avoid hardcoding a specific mapping that cannot be overriden by other host bridge models. > > > > > One solution might be defining a function in the generic host bridge > > which by default returns the requesterIDs (assumes that requesterID is > > the same with the masterID). This function can be over overridden by > > each specific implementation. > > > > > > > > IIRC, the SMMUv3 docs have a section that suggest how these ReqID to AXI Master ID mappings can be done. > > > > I did not find the specific section, just that the streamID should be > > derived from requesterID. In my version of the spec, it's section 4.2 Stream Numbering. At the end of that secion there are some recomendations on how to map PCI ReqIDs into Stream IDs. Cheers, Edgar > > > > > > Thanks, > > > > Diana > > > > > > > > > >>> The way we did it when modelling the ZynqMP is by adding support for > > >>> transaction attribute translation in QEMU's IOMMU interface. > > >>> In our PCI RC, we have an IOMMU covering the entire AS that PCI devs DMA into. > > >>> This IOMMU doesn't do address-translation, only RequesterID -> StreamID > > >>> transforms according to how the ZynqMP PCI RC derives StreamIDs from RequesterIDs. > > >> Are there any patches for this support in order for me to better understand? > > > It's currently on the Xilinx QEMU fork on GitHub. > > > https://github.com/Xilinx/qemu/blob/master/hw/pci-host/xlnx-nwl-pcie-main.c > > > > > > In the current ZynqMP, all RequesterIDs map to a single MasterID (it's a HW limitation). > > > In future versions of the HW, another mapping will be used. > > > I can't share code for the latter yet though.... > > > > > > Best regards, > > > Edgar > > > > > > > > > > > >> Thanks, > > >> > > >> Diana > > >> > > >> > > >>> This is useful not only to model PCI RequesterID to AXI Master ID mappings but > > >>> also for modelling things like the ARM TZC (or the Xilinx ZynqMP XMPU/XPPUs). > > >>> > > >>> Cheers, > > >>> Edgar > > >>> > > >>> > > >>>> simple than reworking pci_requester_id() though. > > >>>>> > > >>>>> memory_region_init(&pci_dev->bus_master_container_region, OBJECT(pci_dev), > > >>>>> "bus master container", UINT64_MAX); > > >>>>> diff --git a/include/hw/arm/virt.h b/include/hw/arm/virt.h > > >>>>> index 33b0ff3..94c007a 100644 > > >>>>> --- a/include/hw/arm/virt.h > > >>>>> +++ b/include/hw/arm/virt.h > > >>>>> @@ -99,6 +99,7 @@ typedef struct { > > >>>>> struct arm_boot_info bootinfo; > > >>>>> const MemMapEntry *memmap; > > >>>>> const int *irqmap; > > >>>>> + const uint32_t *streamidmap; > > >>>>> int smp_cpus; > > >>>>> void *fdt; > > >>>>> int fdt_size; > > >>>>> diff --git a/include/hw/pci-host/gpex.h b/include/hw/pci-host/gpex.h > > >>>>> index 68c9348..47df01a 100644 > > >>>>> --- a/include/hw/pci-host/gpex.h > > >>>>> +++ b/include/hw/pci-host/gpex.h > > >>>>> @@ -48,6 +48,8 @@ typedef struct GPEXHost { > > >>>>> > > >>>>> GPEXRootState gpex_root; > > >>>>> > > >>>>> + uint32_t stream_id_base; > > >>>>> + > > >>>>> MemoryRegion io_ioport; > > >>>>> MemoryRegion io_mmio; > > >>>>> qemu_irq irq[GPEX_NUM_IRQS]; > > >>>>> diff --git a/include/hw/pci/pci.h b/include/hw/pci/pci.h > > >>>>> index a37a2d5..e6e9334 100644 > > >>>>> --- a/include/hw/pci/pci.h > > >>>>> +++ b/include/hw/pci/pci.h > > >>>>> @@ -283,6 +283,12 @@ struct PCIDevice { > > >>>>> * MSI). For conventional PCI root complex, this field is > > >>>>> * meaningless. */ > > >>>>> PCIReqIDCache requester_id_cache; > > >>>>> + /* Some platforms need a unique ID for IOMMU source identification > > >>>>> + * or MSI source identification. QEMU implements a simple scheme: > > >>>>> + * stream_id = stream_id_base + requester_id. The stream_id_base will > > >>>>> + * ensure that all the devices in the system have different stream ID > > >>>>> + * domains */ > > >>>>> + uint32_t stream_id_base; > > >>>> get rid of IOMMU terminology? > > >>>> > > >>>> Note that when adding other sub-systems you will need to address the > > >>>> ACPI side as the IORT table built by hw/arm/virt-acpi-build.c currently > > >>>> defines an RID mapping for the single root complex. > > >>>> > > >>>> Thanks > > >>>> > > >>>> Eric > > >>>>> char name[64]; > > >>>>> PCIIORegion io_regions[PCI_NUM_REGIONS]; > > >>>>> AddressSpace bus_master_as; > > >>>>> @@ -737,6 +743,8 @@ static inline uint16_t pci_get_bdf(PCIDevice *dev) > > >>>>> > > >>>>> uint16_t pci_requester_id(PCIDevice *dev); > > >>>>> > > >>>>> +uint32_t pci_stream_id(PCIDevice *dev); > > >>>>> + > > >>>>> /* DMA access functions */ > > >>>>> static inline AddressSpace *pci_get_address_space(PCIDevice *dev) > > >>>>> { > > >>>>> diff --git a/kvm-all.c b/kvm-all.c > > >>>>> index 90b8573..5a508c3 100644 > > >>>>> --- a/kvm-all.c > > >>>>> +++ b/kvm-all.c > > >>>>> @@ -1280,7 +1280,7 @@ int kvm_irqchip_add_msi_route(KVMState *s, int vector, PCIDevice *dev) > > >>>>> kroute.u.msi.data = le32_to_cpu(msg.data); > > >>>>> if (kvm_msi_devid_required()) { > > >>>>> kroute.flags = KVM_MSI_VALID_DEVID; > > >>>>> - kroute.u.msi.devid = pci_requester_id(dev); > > >>>>> + kroute.u.msi.devid = pci_stream_id(dev); > > >>>>> } > > >>>>> if (kvm_arch_fixup_msi_route(&kroute, msg.address, msg.data, dev)) { > > >>>>> kvm_irqchip_release_virq(s, virq); > > >>>>> @@ -1317,7 +1317,7 @@ int kvm_irqchip_update_msi_route(KVMState *s, int virq, MSIMessage msg, > > >>>>> kroute.u.msi.data = le32_to_cpu(msg.data); > > >>>>> if (kvm_msi_devid_required()) { > > >>>>> kroute.flags = KVM_MSI_VALID_DEVID; > > >>>>> - kroute.u.msi.devid = pci_requester_id(dev); > > >>>>> + kroute.u.msi.devid = pci_stream_id(dev); > > >>>>> } > > >>>>> if (kvm_arch_fixup_msi_route(&kroute, msg.address, msg.data, dev)) { > > >>>>> return -EINVAL; > > >>>>> > > From MAILER-DAEMON Wed Aug 23 21:09:15 2017 Received: from list by lists.gnu.org with archive (Exim 4.71) id 1dkge3-0002W9-2i for mharc-qemu-arm@gnu.org; Wed, 23 Aug 2017 21:09:15 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:39536) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dkSoh-0008A0-4G for qemu-arm@nongnu.org; Wed, 23 Aug 2017 06:23:20 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dkSoc-0007cT-Bl for qemu-arm@nongnu.org; Wed, 23 Aug 2017 06:23:19 -0400 Received: from szxga04-in.huawei.com ([45.249.212.190]:2297) by eggs.gnu.org with esmtps (TLS1.0:RSA_ARCFOUR_SHA1:16) (Exim 4.71) (envelope-from ) id 1dkSob-0007ay-OO for qemu-arm@nongnu.org; Wed, 23 Aug 2017 06:23:14 -0400 Received: from 172.30.72.59 (EHLO DGGEMS405-HUB.china.huawei.com) ([172.30.72.59]) by dggrg04-dlp.huawei.com (MOS 4.4.6-GA FastPath queued) with ESMTP id DFS41564; Wed, 23 Aug 2017 18:23:02 +0800 (CST) Received: from localhost (10.177.27.144) by DGGEMS405-HUB.china.huawei.com (10.3.19.205) with Microsoft SMTP Server id 14.3.301.0; Wed, 23 Aug 2017 18:22:55 +0800 From: wanghaibin To: , , , CC: , , wanghaibin Date: Wed, 23 Aug 2017 18:22:33 +0800 Message-ID: <1503483753-12384-1-git-send-email-wanghaibin.wang@huawei.com> X-Mailer: git-send-email 2.7.2.windows.1 MIME-Version: 1.0 Content-Type: text/plain X-Originating-IP: [10.177.27.144] X-CFilter-Loop: Reflected X-Mirapoint-Virus-RAPID-Raw: score=unknown(0), refid=str=0001.0A090204.599D5787.00EB, ss=1, re=0.000, recu=0.000, reip=0.000, cl=1, cld=1, fgs=0, ip=0.0.0.0, so=2014-11-16 11:51:01, dmn=2013-03-21 17:37:32 X-Mirapoint-Loop-Id: 58dfff39be03c63925f8a226ad986ecc X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.4.x-2.6.x [generic] [fuzzy] X-Received-From: 45.249.212.190 X-Mailman-Approved-At: Wed, 23 Aug 2017 21:09:13 -0400 Subject: [Qemu-arm] [RFC PATCH] hw/intc/arm_gic_kvm.c: access the implemented APRn X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 23 Aug 2017 10:23:20 -0000 Whether the APRn is implemented depends on how many priority bits support. Compared with GICv3, There is no way to retrieve this information directly from the register, so GICD_IPRIORITYR access method is used here according to the SPEC: To determine the number of priority bits implemented for SPIs, software can write 0xFF to a writable GICD_IPRIORITYR priority field and read back the value stored. Signed-off-by: wanghaibin --- hw/intc/arm_gic_kvm.c | 56 ++++++++++++++++++++++++++++++++++++++++++--------- 1 file changed, 47 insertions(+), 9 deletions(-) diff --git a/hw/intc/arm_gic_kvm.c b/hw/intc/arm_gic_kvm.c index ae095d0..a2f3139 100644 --- a/hw/intc/arm_gic_kvm.c +++ b/hw/intc/arm_gic_kvm.c @@ -290,13 +290,30 @@ static void kvm_dist_put(GICState *s, uint32_t offset, int width, } } +static int kvm_arm_gic_get_pri_bits(GICState *s) +{ + uint32_t reg = 0xff; + + /* + * To determine the number of priority bits implemented, Just wirte the 0xff to + * the first SPI(32) GICD_IPRIORITYR priority field and read back the value + * stored. + * Note: Assume that implementations support the same number of priority + * bits for each PE + */ + kvm_gicd_access(s, 0x400 + 0x20, 0, ®, true); + kvm_gicd_access(s, 0x400 + 0x20, 0, ®, false); + + return 8 - ctz32(reg); +} + static void kvm_arm_gic_put(GICState *s) { uint32_t reg; - int i; int cpu; int num_cpu; int num_irq; + int num_pri_bits; /* Note: We do the restore in a slightly different order than the save * (where the order doesn't matter and is simply ordered according to the @@ -326,6 +343,8 @@ static void kvm_arm_gic_put(GICState *s) abort(); } + num_pri_bits = kvm_arm_gic_get_pri_bits(s); + /* TODO: Consider checking compatibility with the IIDR ? */ /* irq_state[n].enabled -> GICD_ISENABLERn */ @@ -353,7 +372,6 @@ static void kvm_arm_gic_put(GICState *s) kvm_dist_put(s, 0x380, 1, s->num_irq, translate_clear); kvm_dist_put(s, 0x300, 1, s->num_irq, translate_active); - /* s->priorityX[irq] -> ICD_IPRIORITYRn */ kvm_dist_put(s, 0x400, 8, s->num_irq, translate_priority); @@ -384,9 +402,18 @@ static void kvm_arm_gic_put(GICState *s) kvm_gicc_access(s, 0x1c, cpu, ®, true); /* s->apr[n][cpu] -> GICC_APRn */ - for (i = 0; i < 4; i++) { - reg = s->apr[i][cpu]; - kvm_gicc_access(s, 0xd0 + i * 4, cpu, ®, true); + switch (num_pri_bits) { + case 7: + reg = s->apr[3][cpu]; + kvm_gicc_access(s, 0xd0 + 3 * 4, cpu, ®, true); + reg = s->apr[2][cpu]; + kvm_gicc_access(s, 0xd0 + 2 * 4, cpu, ®, true); + case 6: + reg = s->apr[1][cpu]; + kvm_gicc_access(s, 0xd0 + 1 * 4, cpu, ®, true); + default: + reg = s->apr[0][cpu]; + kvm_gicc_access(s, 0xd0, cpu, ®, true); } } } @@ -396,6 +423,7 @@ static void kvm_arm_gic_get(GICState *s) uint32_t reg; int i; int cpu; + int num_pri_bits; /***************************************************************** * Distributor State @@ -448,6 +476,7 @@ static void kvm_arm_gic_get(GICState *s) /* GICD_CPENDSGIRn -> s->sgi_pending */ kvm_dist_get(s, 0xf10, 8, GIC_NR_SGIS, translate_sgisource); + num_pri_bits = kvm_arm_gic_get_pri_bits(s); /***************************************************************** * CPU Interface(s) State @@ -470,10 +499,19 @@ static void kvm_arm_gic_get(GICState *s) kvm_gicc_access(s, 0x1c, cpu, ®, false); s->abpr[cpu] = (reg & 0x7); - /* GICC_APRn -> s->apr[n][cpu] */ - for (i = 0; i < 4; i++) { - kvm_gicc_access(s, 0xd0 + i * 4, cpu, ®, false); - s->apr[i][cpu] = reg; + /* s->apr[n][cpu] -> GICC_APRn */ + switch (num_pri_bits) { + case 7: + kvm_gicc_access(s, 0xd0 + 3 * 4, cpu, ®, false); + s->apr[3][cpu] = reg; + kvm_gicc_access(s, 0xd0 + 2 * 4, cpu, ®, false); + s->apr[2][cpu] = reg; + case 6: + kvm_gicc_access(s, 0xd0 + 1 * 4, cpu, ®, false); + s->apr[1][cpu] = reg; + default: + kvm_gicc_access(s, 0xd0, cpu, ®, false); + s->apr[0][cpu] = reg; } } } -- 1.8.3.1 From MAILER-DAEMON Wed Aug 23 23:03:17 2017 Received: from list by lists.gnu.org with archive (Exim 4.71) id 1dkiQO-0002Nn-Uk for mharc-qemu-arm@gnu.org; Wed, 23 Aug 2017 23:03:16 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:47593) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dkiQM-0002Ng-FK for qemu-arm@nongnu.org; Wed, 23 Aug 2017 23:03:15 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dkiQH-0000uH-Kg for qemu-arm@nongnu.org; Wed, 23 Aug 2017 23:03:14 -0400 Received: from mx1.redhat.com ([209.132.183.28]:48436) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1dkiQH-0000u5-E0; Wed, 23 Aug 2017 23:03:09 -0400 Received: from smtp.corp.redhat.com (int-mx06.intmail.prod.int.phx2.redhat.com [10.5.11.16]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id 2762C356DA; Thu, 24 Aug 2017 03:03:08 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mx1.redhat.com 2762C356DA Authentication-Results: ext-mx06.extmail.prod.ext.phx2.redhat.com; dmarc=none (p=none dis=none) header.from=redhat.com Authentication-Results: ext-mx06.extmail.prod.ext.phx2.redhat.com; spf=fail smtp.mailfrom=thuth@redhat.com Received: from thh440s.redhat.com (ovpn-116-37.ams2.redhat.com [10.36.116.37]) by smtp.corp.redhat.com (Postfix) with ESMTP id 3AAD689D29; Thu, 24 Aug 2017 03:03:03 +0000 (UTC) From: Thomas Huth To: qemu-block@nongnu.org, John Snow Cc: qemu-devel@nongnu.org, qemu-arm@nongnu.org, Andrzej Zaborowski Date: Thu, 24 Aug 2017 05:03:03 +0200 Message-Id: <1503543783-17192-1-git-send-email-thuth@redhat.com> X-Scanned-By: MIMEDefang 2.79 on 10.5.11.16 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.30]); Thu, 24 Aug 2017 03:03:08 +0000 (UTC) X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.132.183.28 Subject: [Qemu-arm] [PATCH for-2.11] hw/ide/microdrive: Mark the dscm1xxxx device with user_creatable = false X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 24 Aug 2017 03:03:15 -0000 QEMU currently aborts with an assertion message when the user is trying to remove a dscm1xxxx again: $ aarch64-softmmu/qemu-system-aarch64 -S -M integratorcp -nographic QEMU 2.9.93 monitor - type 'help' for more information (qemu) device_add dscm1xxxx,id=xyz (qemu) device_del xyz ** ERROR:qemu/qdev-monitor.c:872:qdev_unplug: assertion failed: (hotplug_ctrl) Aborted (core dumped) Looks like this device has to be wired up in code and is not meant to be hot-pluggable, so let's mark it with user_creatable = false. Signed-off-by: Thomas Huth --- hw/ide/microdrive.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/hw/ide/microdrive.c b/hw/ide/microdrive.c index e3fd30e..17917c0 100644 --- a/hw/ide/microdrive.c +++ b/hw/ide/microdrive.c @@ -575,12 +575,15 @@ PCMCIACardState *dscm1xxxx_init(DriveInfo *dinfo) static void dscm1xxxx_class_init(ObjectClass *oc, void *data) { PCMCIACardClass *pcc = PCMCIA_CARD_CLASS(oc); + DeviceClass *dc = DEVICE_CLASS(oc); pcc->cis = dscm1xxxx_cis; pcc->cis_len = sizeof(dscm1xxxx_cis); pcc->attach = dscm1xxxx_attach; pcc->detach = dscm1xxxx_detach; + /* Reason: Needs to be wired-up in code, see dscm1xxxx_init() */ + dc->user_creatable = false; } static const TypeInfo dscm1xxxx_type_info = { -- 1.8.3.1 From MAILER-DAEMON Thu Aug 24 01:31:33 2017 Received: from list by lists.gnu.org with archive (Exim 4.71) id 1dkkjt-00033L-DM for mharc-qemu-arm@gnu.org; Thu, 24 Aug 2017 01:31:33 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:34042) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dkkjq-00031C-JV for qemu-arm@nongnu.org; Thu, 24 Aug 2017 01:31:31 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dkkjp-000815-PC for qemu-arm@nongnu.org; Thu, 24 Aug 2017 01:31:30 -0400 Received: from mail-wr0-x22e.google.com ([2a00:1450:400c:c0c::22e]:35651) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1dkkjl-00080N-9s; Thu, 24 Aug 2017 01:31:25 -0400 Received: by mail-wr0-x22e.google.com with SMTP id k46so6451775wre.2; Wed, 23 Aug 2017 22:31:23 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:subject:to:cc:references:from:message-id:date:user-agent :mime-version:in-reply-to:content-language:content-transfer-encoding; bh=urOGyN8b8HvtuVErrl3FqifFCs7eOksfCiAwWv/qC38=; b=WaF93beKgMK199M8Q0/2niKa3zwqcZsFRBBwKMpU6+X8Y+azbjLWy/NSaz5iWpU8qu n2Xs5L8JdawH/tcPyG7SNM6KeubDWdALiq3lG74U91YceGdXM1nmFFb1vc86GUx8g+ox he4zbFDaTJ09ZvMlrDmBfD7dahj2DxQS2v1MRs68VOejOnxyJlFkpjJUsX/NFTEZ8iwF 82KoXg+JL4Inred4/wqB2t9w/HHX0isp9gQl3G04D41/kpk8J6zNQ/zJZXbXv6he7nJ6 Gzvsb3FkN/MreiHeMS39asmQICavLs3mYxwvnoKuQYzp2qrq0YFUE9cFwJUFk9ooQ/zP 6tJw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:subject:to:cc:references:from:message-id :date:user-agent:mime-version:in-reply-to:content-language :content-transfer-encoding; bh=urOGyN8b8HvtuVErrl3FqifFCs7eOksfCiAwWv/qC38=; b=a5loD+TXrfcAP9a7vXHnezMnI1mMV0GZnL/VcGl+hIISCEwEiSgPX7GBQGav00E2G+ sjga/j/si+hHWsfCVJGe1TRwwVAe0t6EdesgcUYhwTKvLmxP8BvOrjTlIxw9M3tMhSpj kUCdPxeusAv97VtWl6aXedzEvOWNaIcP0KFD0Z/8q6vYDH3zYCh3XUTLZ2Ep4cpKBv4p 8rniB0QzOu7RHb/xD/eN0es3uZDjxHOempAmrR1HSEz/C6hHeVfK4fIpkyYBkE7eSeiT 6w96jzmJMomYiUQzYyR2j49j/ChFrHePzRtXfXnrp70iFhZS4zgTm98NNJ/u94S8KyXo JqwQ== X-Gm-Message-State: AHYfb5jObEvE91x8oE8MmxPyg9aGk/wkCr6ARc47kL/cmTHQJnGWjbhk FHHRDq5wXnKqFc7xm60= X-Received: by 10.223.142.168 with SMTP id q37mr3249003wrb.254.1503552682612; Wed, 23 Aug 2017 22:31:22 -0700 (PDT) Received: from [192.168.10.165] (94-39-192-75.adsl-ull.clienti.tiscali.it. [94.39.192.75]) by smtp.googlemail.com with ESMTPSA id w16sm6039311wrc.84.2017.08.23.22.31.19 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 23 Aug 2017 22:31:21 -0700 (PDT) Sender: Paolo Bonzini To: Thomas Huth , qemu-block@nongnu.org, John Snow Cc: qemu-arm@nongnu.org, Andrzej Zaborowski , qemu-devel@nongnu.org References: <1503543783-17192-1-git-send-email-thuth@redhat.com> From: Paolo Bonzini Message-ID: <7995c721-963c-2552-e1a1-767f461ae63a@redhat.com> Date: Thu, 24 Aug 2017 07:31:18 +0200 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.2.1 MIME-Version: 1.0 In-Reply-To: <1503543783-17192-1-git-send-email-thuth@redhat.com> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 8bit X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:400c:c0c::22e Subject: Re: [Qemu-arm] [PATCH for-2.11] hw/ide/microdrive: Mark the dscm1xxxx device with user_creatable = false X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 24 Aug 2017 05:31:31 -0000 On 24/08/2017 05:03, Thomas Huth wrote: > QEMU currently aborts with an assertion message when the user is trying > to remove a dscm1xxxx again: > > $ aarch64-softmmu/qemu-system-aarch64 -S -M integratorcp -nographic > QEMU 2.9.93 monitor - type 'help' for more information > (qemu) device_add dscm1xxxx,id=xyz > (qemu) device_del xyz > ** > ERROR:qemu/qdev-monitor.c:872:qdev_unplug: assertion failed: (hotplug_ctrl) > Aborted (core dumped) > > Looks like this device has to be wired up in code and is not meant > to be hot-pluggable, so let's mark it with user_creatable = false. The hotpluggable flag should be just a hint from the device, independent of any knowledge of the board's behavior. So a better question is why qbus_is_hotpluggable was true at device_add time (I suppose qdev_get_hotplug_handler was NULL at device_add time). BTW, maybe we can get rid of qbus_is_hotpluggable by doing something like this: 1) This code in device_set_realized: hotplug_ctrl = qdev_get_hotplug_handler(dev); if (hotplug_ctrl) { hotplug_handler_pre_plug(hotplug_ctrl, dev, &local_err); if (local_err != NULL) { goto fail; } } can fail with an error (QERR_DEVICE_NO_HOTPLUG is already there) if dev->hotplugged && !hotplug_ctrl. 2) In device_add, this code is now superfluous: if (qdev_hotplug && bus && !qbus_is_hotpluggable(bus)) { error_setg(errp, QERR_BUS_NO_HOTPLUG, bus->name); return NULL; } 3) in device_get_hotpluggable, the right side of the && can be replaced with "qdev_get_hotplug_handler(dev) != NULL", getting rid of qbus_is_hotpluggable. Paolo From MAILER-DAEMON Thu Aug 24 01:57:32 2017 Received: from list by lists.gnu.org with archive (Exim 4.71) id 1dkl92-0000Wb-F2 for mharc-qemu-arm@gnu.org; Thu, 24 Aug 2017 01:57:32 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:36808) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dkl8z-0000V5-LQ for qemu-arm@nongnu.org; Thu, 24 Aug 2017 01:57:30 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dkl8v-0007E9-IJ for qemu-arm@nongnu.org; Thu, 24 Aug 2017 01:57:29 -0400 Received: from mail-db5eur01on0058.outbound.protection.outlook.com ([104.47.2.58]:14174 helo=EUR01-DB5-obe.outbound.protection.outlook.com) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1dkl8v-0007DG-4n; Thu, 24 Aug 2017 01:57:25 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nxp.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version; bh=4nT4aZFO3QV0VItFL9IlSsjdwp/HKrEIBKX95nATxuk=; b=XHLb7/jmpi4MX9Ky76//NgHy+VVo3ZyxgxY1rYNRPaqIDcy7FCMqZu4Z870IqN2JN4a7qrAcGCzgzJYOzJV+tLFV8C4m13yuHZiTKSOyhqEnriTKIGgn+CPunPVGgxLEQ3/k0eZgrxiCfHQdsl+1cxh2ZdNfrGucyqWU9914gV8= Received: from AM5PR0401MB2545.eurprd04.prod.outlook.com (10.169.245.8) by AM5PR0401MB2484.eurprd04.prod.outlook.com (10.169.244.140) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384_P256) id 15.1.1385.9; Thu, 24 Aug 2017 05:57:21 +0000 Received: from AM5PR0401MB2545.eurprd04.prod.outlook.com ([fe80::e5cb:77cb:372c:4817]) by AM5PR0401MB2545.eurprd04.prod.outlook.com ([fe80::e5cb:77cb:372c:4817%17]) with mapi id 15.01.1385.009; Thu, 24 Aug 2017 05:57:20 +0000 From: Bharat Bhushan To: Auger Eric , "eric.auger.pro@gmail.com" , "peter.maydell@linaro.org" , "alex.williamson@redhat.com" , "mst@redhat.com" , "qemu-arm@nongnu.org" , "qemu-devel@nongnu.org" CC: "wei@redhat.com" , "kevin.tian@intel.com" , "marc.zyngier@arm.com" , "tn@semihalf.com" , "will.deacon@arm.com" , "drjones@redhat.com" , "robin.murphy@arm.com" , "christoffer.dall@linaro.org" Thread-Topic: [PATCH v3 0/2] virtio-iommu: VFIO integration Thread-Index: AQHTGmt5KHc5JuRSYUG3gkO3aouxUKKSKIaAgADG4IA= Date: Thu, 24 Aug 2017 05:57:20 +0000 Message-ID: References: <1503312534-6642-1-git-send-email-Bharat.Bhushan@nxp.com> <2e23327a-3e5e-abaf-387f-d23462d8aba7@redhat.com> In-Reply-To: <2e23327a-3e5e-abaf-387f-d23462d8aba7@redhat.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: authentication-results: spf=none (sender IP is ) smtp.mailfrom=bharat.bhushan@nxp.com; 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MX:1; A:1; LANG:en; received-spf: None (protection.outlook.com: nxp.com does not designate permitted sender hosts) spamdiagnosticoutput: 1:99 spamdiagnosticmetadata: NSPM Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-originalarrivaltime: 24 Aug 2017 05:57:20.6022 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM5PR0401MB2484 X-detected-operating-system: by eggs.gnu.org: Windows 7 or 8 [fuzzy] X-Received-From: 104.47.2.58 Subject: Re: [Qemu-arm] [PATCH v3 0/2] virtio-iommu: VFIO integration X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 24 Aug 2017 05:57:31 -0000 Hi Eric, > -----Original Message----- > From: Auger Eric [mailto:eric.auger@redhat.com] > Sent: Wednesday, August 23, 2017 10:12 PM > To: Bharat Bhushan ; > eric.auger.pro@gmail.com; peter.maydell@linaro.org; > alex.williamson@redhat.com; mst@redhat.com; qemu-arm@nongnu.org; > qemu-devel@nongnu.org > Cc: wei@redhat.com; kevin.tian@intel.com; marc.zyngier@arm.com; > tn@semihalf.com; will.deacon@arm.com; drjones@redhat.com; > robin.murphy@arm.com; christoffer.dall@linaro.org > Subject: Re: [PATCH v3 0/2] virtio-iommu: VFIO integration >=20 > Hi Bharat, >=20 > On 21/08/2017 12:48, Bharat Bhushan wrote: > > This V3 version is mainly about rebasing on v3 version on Virtio-iommu > > device framework from Eric Augur and addresing review comments. > s/Augur/Auger ;-) I am sorry, > > > > This patch series allows PCI pass-through using virtio-iommu. > > > > This series is based on: > > - virtio-iommu specification written by Jean-Philippe Brucker > > [RFC 0/3] virtio-iommu: a paravirtualized IOMMU, > > > > - virtio-iommu driver by Jean-Philippe Brucker > > [RFC PATCH linux] iommu: Add virtio-iommu driver > > > > - virtio-iommu device emulation by Eric Augur. > > [RFC v3 0/8] VIRTIO-IOMMU device > > > > PCI device pass-through and virtio-net-pci is tested with these > > changes using dma-ops >=20 > I confirm it works fine now with 2 assigned VFs. >=20 > However at the moment DPDK testpmd using those 2 VFs does not work for > me: > 1: > [/home/augere/UPSTREAM/dpdk/install/bin/testpmd(rte_dump_stack+0x2 > 4) > [0x4a8a78]] >=20 > I haven't investigated yet... I have not run DPDK before, I am compiling right now and run. Thanks -Bharat >=20 > Thanks >=20 > Eric > > > > This patch series does not implement RESV_MEM changes proposal by > Jean-Philippe "https://lists.gnu.org/archive/html/qemu-devel/2017- > 07/msg01796.html" > > > > v2->v3: > > - This series is based on "[RFC v3 0/8] VIRTIO-IOMMU device" > > Which is based on top of v2.10-rc0 that > > - Fixed issue with two PCI devices > > - Addressed review comments > > > > v1->v2: > > - Added trace events > > - removed vSMMU3 link in patch description > > > > Bharat Bhushan (2): > > target/arm/kvm: Translate the MSI doorbell in > kvm_arch_fixup_msi_route > > virtio-iommu: vfio integration with virtio-iommu > > > > hw/virtio/trace-events | 5 ++ > > hw/virtio/virtio-iommu.c | 163 > +++++++++++++++++++++++++++++++++++++++ > > include/hw/virtio/virtio-iommu.h | 6 ++ > > target/arm/kvm.c | 27 +++++++ > > target/arm/trace-events | 3 + > > 5 files changed, 204 insertions(+) > > From MAILER-DAEMON Thu Aug 24 08:35:43 2017 Received: from list by lists.gnu.org with archive (Exim 4.71) id 1dkrMN-0001Vc-BK for mharc-qemu-arm@gnu.org; Thu, 24 Aug 2017 08:35:43 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:58035) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dkrMK-0001Sx-Ej for qemu-arm@nongnu.org; Thu, 24 Aug 2017 08:35:42 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dkrMD-00030F-Vn for qemu-arm@nongnu.org; Thu, 24 Aug 2017 08:35:40 -0400 Received: from szxga05-in.huawei.com ([45.249.212.191]:2241) by eggs.gnu.org with esmtps (TLS1.0:RSA_ARCFOUR_SHA1:16) (Exim 4.71) (envelope-from ) id 1dkrMD-0002uF-3K; Thu, 24 Aug 2017 08:35:33 -0400 Received: from 172.30.72.58 (EHLO DGGEMS409-HUB.china.huawei.com) ([172.30.72.58]) by dggrg05-dlp.huawei.com (MOS 4.4.6-GA FastPath queued) with ESMTP id DFW36361; Thu, 24 Aug 2017 20:34:10 +0800 (CST) Received: from [127.0.0.1] (10.177.16.142) by DGGEMS409-HUB.china.huawei.com (10.3.19.209) with Microsoft SMTP Server id 14.3.301.0; Thu, 24 Aug 2017 20:34:01 +0800 Message-ID: <599EC7AB.3080604@huawei.com> Date: Thu, 24 Aug 2017 20:33:47 +0800 From: Shannon Zhao User-Agent: Mozilla/5.0 (Windows NT 6.1; rv:24.0) Gecko/20100101 Thunderbird/24.4.0 MIME-Version: 1.0 To: Dongjiu Geng , , , , , , , , , , , , , , , , , , , , , , , , , , , , CC: , , , References: <1503066227-18251-1-git-send-email-gengdongjiu@huawei.com> <1503066227-18251-2-git-send-email-gengdongjiu@huawei.com> In-Reply-To: <1503066227-18251-2-git-send-email-gengdongjiu@huawei.com> Content-Type: text/plain; charset="ISO-8859-1" Content-Transfer-Encoding: 7bit X-Originating-IP: [10.177.16.142] X-CFilter-Loop: Reflected X-Mirapoint-Virus-RAPID-Raw: score=unknown(0), refid=str=0001.0A090206.599EC7C7.001B, ss=1, re=0.000, recu=0.000, reip=0.000, cl=1, cld=1, fgs=0, ip=0.0.0.0, so=2014-11-16 11:51:01, dmn=2013-03-21 17:37:32 X-Mirapoint-Loop-Id: c1335e206e8c45edacacb8cba8c0d529 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.4.x-2.6.x [generic] [fuzzy] X-Received-From: 45.249.212.191 Subject: Re: [Qemu-arm] [PATCH v11 1/6] ACPI: add APEI/HEST/CPER structures and macros X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 24 Aug 2017 12:35:42 -0000 On 2017/8/18 22:23, Dongjiu Geng wrote: > (1) Add related APEI/HEST table structures and macros, these > definition refer to ACPI 6.1 and UEFI 2.6 spec. > (2) Add generic error status block and CPER memory section > definition, user space only handle memory section errors. > > Signed-off-by: Dongjiu Geng > --- > include/hw/acpi/acpi-defs.h | 193 ++++++++++++++++++++++++++++++++++++++++++++ > 1 file changed, 193 insertions(+) > > diff --git a/include/hw/acpi/acpi-defs.h b/include/hw/acpi/acpi-defs.h > index 72be675..3b4bad7 100644 > --- a/include/hw/acpi/acpi-defs.h > +++ b/include/hw/acpi/acpi-defs.h > @@ -297,6 +297,44 @@ typedef struct AcpiMultipleApicTable AcpiMultipleApicTable; > #define ACPI_APIC_GENERIC_TRANSLATOR 15 > #define ACPI_APIC_RESERVED 16 /* 16 and greater are reserved */ > > +/* UEFI Spec 2.6, "N.2.5 Memory Error Section */ missing " > +#define UEFI_CPER_MEM_VALID_ERROR_STATUS 0x0001 > +#define UEFI_CPER_MEM_VALID_PA 0x0002 > +#define UEFI_CPER_MEM_VALID_PA_MASK 0x0004 > +#define UEFI_CPER_MEM_VALID_NODE 0x0008 > +#define UEFI_CPER_MEM_VALID_CARD 0x0010 > +#define UEFI_CPER_MEM_VALID_MODULE 0x0020 > +#define UEFI_CPER_MEM_VALID_BANK 0x0040 > +#define UEFI_CPER_MEM_VALID_DEVICE 0x0080 > +#define UEFI_CPER_MEM_VALID_ROW 0x0100 > +#define UEFI_CPER_MEM_VALID_COLUMN 0x0200 > +#define UEFI_CPER_MEM_VALID_BIT_POSITION 0x0400 > +#define UEFI_CPER_MEM_VALID_REQUESTOR 0x0800 > +#define UEFI_CPER_MEM_VALID_RESPONDER 0x1000 > +#define UEFI_CPER_MEM_VALID_TARGET 0x2000 > +#define UEFI_CPER_MEM_VALID_ERROR_TYPE 0x4000 > +#define UEFI_CPER_MEM_VALID_RANK_NUMBER 0x8000 > +#define UEFI_CPER_MEM_VALID_CARD_HANDLE 0x10000 > +#define UEFI_CPER_MEM_VALID_MODULE_HANDLE 0x20000 > +#define UEFI_CPER_MEM_ERROR_TYPE_MULTI_ECC 3 > + > +/* From the ACPI 6.1 spec, "18.3.2.9 Hardware Error Notification" */ > + It's better to refer to the first spec version of this structure and same with others you define. > +enum AcpiHestNotifyType { > + ACPI_HEST_NOTIFY_POLLED = 0, > + ACPI_HEST_NOTIFY_EXTERNAL = 1, > + ACPI_HEST_NOTIFY_LOCAL = 2, > + ACPI_HEST_NOTIFY_SCI = 3, > + ACPI_HEST_NOTIFY_NMI = 4, > + ACPI_HEST_NOTIFY_CMCI = 5, /* ACPI 5.0 */ > + ACPI_HEST_NOTIFY_MCE = 6, /* ACPI 5.0 */ > + ACPI_HEST_NOTIFY_GPIO = 7, /* ACPI 6.0 */ > + ACPI_HEST_NOTIFY_SEA = 8, /* ACPI 6.1 */ > + ACPI_HEST_NOTIFY_SEI = 9, /* ACPI 6.1 */ > + ACPI_HEST_NOTIFY_GSIV = 10, /* ACPI 6.1 */ > + ACPI_HEST_NOTIFY_RESERVED = 11 /* 11 and greater are reserved */ In ACPI 6.2, 11 is for Software Delegated Exception, is this useful for your patchset? > +}; > + > /* > * MADT sub-structures (Follow MULTIPLE_APIC_DESCRIPTION_TABLE) > */ > @@ -474,6 +512,161 @@ struct AcpiSystemResourceAffinityTable { > } QEMU_PACKED; > typedef struct AcpiSystemResourceAffinityTable AcpiSystemResourceAffinityTable; > > +/* Hardware Error Notification, from the ACPI 6.1 > + * spec, "18.3.2.9 Hardware Error Notification" > + */ Use below style for multiple comment lines /* * XXX */ > +struct AcpiHestNotify { > + uint8_t type; > + uint8_t length; > + uint16_t config_write_enable; > + uint32_t poll_interval; > + uint32_t vector; > + uint32_t polling_threshold_value; > + uint32_t polling_threshold_window; > + uint32_t error_threshold_value; > + uint32_t error_threshold_window; > +} QEMU_PACKED; > +typedef struct AcpiHestNotify AcpiHestNotify; > + > +/* From ACPI 6.1, sections "18.3.2.1 IA-32 Architecture Machine > + * Check Exception" through "18.3.2.8 Generic Hardware Error Source version 2". > + */ > +enum AcpiHestSourceType { > + ACPI_HEST_SOURCE_IA32_CHECK = 0, > + ACPI_HEST_SOURCE_IA32_CORRECTED_CHECK = 1, > + ACPI_HEST_SOURCE_IA32_NMI = 2, What's 3, 4, 5 for? > + ACPI_HEST_SOURCE_AER_ROOT_PORT = 6, > + ACPI_HEST_SOURCE_AER_ENDPOINT = 7, > + ACPI_HEST_SOURCE_AER_BRIDGE = 8, > + ACPI_HEST_SOURCE_GENERIC_ERROR = 9, > + ACPI_HEST_SOURCE_GENERIC_ERROR_V2 = 10, > + ACPI_HEST_SOURCE_RESERVED = 11 /* 11 and greater are reserved */ > +}; > + > +/* Block status bitmasks from ACPI 6.1, "18.3.2.7.1 Generic Error Data" */ > +#define ACPI_GEBS_UNCORRECTABLE (1) > +#define ACPI_GEBS_CORRECTABLE (1 << 1) > +#define ACPI_GEBS_MULTIPLE_UNCORRECTABLE (1 << 2) > +#define ACPI_GEBS_MULTIPLE_CORRECTABLE (1 << 3) > +/* 10 bits, error data entry count */ > +#define ACPI_GEBS_ERROR_ENTRY_COUNT (0x3FF << 4) > + > +/* Generic Hardware Error Source Structure, refer to ACPI 6.1 > + * "18.3.2.7 Generic Hardware Error Source". in this struct the > + * "type" field has to be ACPI_HEST_SOURCE_GENERIC_ERROR > + */ > + > +struct AcpiGenericHardwareErrorSource { > + uint16_t type; > + uint16_t source_id; > + uint16_t related_source_id; > + uint8_t flags; > + uint8_t enabled; > + uint32_t number_of_records; > + uint32_t max_sections_per_record; > + uint32_t max_raw_data_length; > + struct AcpiGenericAddress error_status_address; > + struct AcpiHestNotify notify; > + uint32_t error_status_block_length; > +} QEMU_PACKED; > +typedef struct AcpiGenericHardwareErrorSource AcpiGenericHardwareErrorSource; > + > +/* Generic Hardware Error Source, version 2, ACPI 6.1, "18.3.2.8 Generic > + * Hardware Error Source version 2", in this struct the "type" field has to > + * be ACPI_HEST_SOURCE_GENERIC_ERROR_V2 > + */ > +struct AcpiGenericHardwareErrorSourceV2 { > + uint16_t type; > + uint16_t source_id; > + uint16_t related_source_id; > + uint8_t flags; > + uint8_t enabled; > + uint32_t number_of_records; > + uint32_t max_sections_per_record; > + uint32_t max_raw_data_length; > + struct AcpiGenericAddress error_status_address; > + struct AcpiHestNotify notify; > + uint32_t error_status_block_length; > + struct AcpiGenericAddress read_ack_register; > + uint64_t read_ack_preserve; > + uint64_t read_ack_write; > +} QEMU_PACKED; > +typedef struct AcpiGenericHardwareErrorSourceV2 > + AcpiGenericHardwareErrorSourceV2; > + > +/* Generic Error Status block, from ACPI 6.1, > + * "18.3.2.7.1 Generic Error Data" > + */ > +struct AcpiGenericErrorStatus { > + /* It is a bitmask composed of ACPI_GEBS_xxx macros */ > + uint32_t block_status; > + uint32_t raw_data_offset; > + uint32_t raw_data_length; > + uint32_t data_length; > + uint32_t error_severity; > +} QEMU_PACKED; > +typedef struct AcpiGenericErrorStatus AcpiGenericErrorStatus; > + > +enum AcpiGenericErrorSeverity { > + ACPI_CPER_SEV_RECOVERABLE, > + ACPI_CPER_SEV_FATAL, > + ACPI_CPER_SEV_CORRECTED, > + ACPI_CPER_SEV_NONE, > +}; > + > +/* Generic Error Data entry, revision number is 0x0300, > + * ACPI 6.1, "18.3.2.7.1 Generic Error Data" > + */ > +struct AcpiGenericErrorData { > + uint8_t section_type_le[16]; > + /* The "error_severity" fields that they take their > + * values from AcpiGenericErrorSeverity > + */ > + uint32_t error_severity; > + uint16_t revision; > + uint8_t validation_bits; > + uint8_t flags; > + uint32_t error_data_length; > + uint8_t fru_id[16]; > + uint8_t fru_text[20]; > + uint64_t time_stamp; > +} QEMU_PACKED; > +typedef struct AcpiGenericErrorData AcpiGenericErrorData; > + > +/* From UEFI 2.6, "N.2.5 Memory Error Section" */ > +struct UefiCperSecMemErr { > + uint64_t validation_bits; > + uint64_t error_status; > + uint64_t physical_addr; > + uint64_t physical_addr_mask; > + uint16_t node; > + uint16_t card; > + uint16_t module; > + uint16_t bank; > + uint16_t device; > + uint16_t row; > + uint16_t column; > + uint16_t bit_pos; > + uint64_t requestor_id; > + uint64_t responder_id; > + uint64_t target_id; > + uint8_t error_type; > + uint8_t reserved; > + uint16_t rank; > + uint16_t mem_array_handle; /* card handle in UEFI 2.4 */ > + uint16_t mem_dev_handle; /* module handle in UEFI 2.4 */ > +} QEMU_PACKED; > +typedef struct UefiCperSecMemErr UefiCperSecMemErr; > + > +/* > + * HEST Description Table > + */ > +struct AcpiHardwareErrorSourceTable { > + ACPI_TABLE_HEADER_DEF /* ACPI common table header */ > + uint32_t error_source_count; > +} QEMU_PACKED; > +typedef struct AcpiHardwareErrorSourceTable AcpiHardwareErrorSourceTable; > + > #define ACPI_SRAT_PROCESSOR_APIC 0 > #define ACPI_SRAT_MEMORY 1 > #define ACPI_SRAT_PROCESSOR_x2APIC 2 > -- Shannon From MAILER-DAEMON Thu Aug 24 09:06:18 2017 Received: from list by lists.gnu.org with archive (Exim 4.71) id 1dkrpy-00026k-Id for mharc-qemu-arm@gnu.org; Thu, 24 Aug 2017 09:06:18 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:35039) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dkrpr-00026K-9r for qemu-arm@nongnu.org; Thu, 24 Aug 2017 09:06:17 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dkrpk-0008HX-6S for qemu-arm@nongnu.org; Thu, 24 Aug 2017 09:06:11 -0400 Received: from szxga04-in.huawei.com ([45.249.212.190]:2298) by eggs.gnu.org with esmtps (TLS1.0:RSA_ARCFOUR_SHA1:16) (Exim 4.71) (envelope-from ) id 1dkrpi-0008Cc-RW; Thu, 24 Aug 2017 09:06:04 -0400 Received: from 172.30.72.59 (EHLO DGGEMS409-HUB.china.huawei.com) ([172.30.72.59]) by dggrg04-dlp.huawei.com (MOS 4.4.6-GA FastPath queued) with ESMTP id DFU39985; Thu, 24 Aug 2017 21:04:41 +0800 (CST) Received: from [127.0.0.1] (10.177.16.142) by DGGEMS409-HUB.china.huawei.com (10.3.19.209) with Microsoft SMTP Server id 14.3.301.0; Thu, 24 Aug 2017 21:04:31 +0800 Message-ID: <599ECE95.10205@huawei.com> Date: Thu, 24 Aug 2017 21:03:17 +0800 From: Shannon Zhao User-Agent: Mozilla/5.0 (Windows NT 6.1; rv:24.0) Gecko/20100101 Thunderbird/24.4.0 MIME-Version: 1.0 To: Dongjiu Geng , , , , , , , , , , , , , , , , , , , , , , , , , , , , CC: , , , References: <1503066227-18251-1-git-send-email-gengdongjiu@huawei.com> <1503066227-18251-3-git-send-email-gengdongjiu@huawei.com> In-Reply-To: <1503066227-18251-3-git-send-email-gengdongjiu@huawei.com> Content-Type: text/plain; charset="ISO-8859-1" Content-Transfer-Encoding: 7bit X-Originating-IP: [10.177.16.142] X-CFilter-Loop: Reflected X-Mirapoint-Virus-RAPID-Raw: score=unknown(0), refid=str=0001.0A090204.599ECEEA.00B8, ss=1, re=0.000, recu=0.000, reip=0.000, cl=1, cld=1, fgs=0, ip=0.0.0.0, so=2014-11-16 11:51:01, dmn=2013-03-21 17:37:32 X-Mirapoint-Loop-Id: 72b1c22ab38c0022a5c2d9e53ed95867 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.4.x-2.6.x [generic] [fuzzy] X-Received-From: 45.249.212.190 Subject: Re: [Qemu-arm] [PATCH v11 2/6] ACPI: Add APEI GHES Table Generation support X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 24 Aug 2017 13:06:17 -0000 On 2017/8/18 22:23, Dongjiu Geng wrote: > This implements APEI GHES Table by passing the error CPER info > to the guest via a fw_cfg_blob. After a CPER info is recorded, an > SEA(Synchronous External Abort)/SEI(SError Interrupt) exception > will be injected into the guest OS. > > Below is the table layout, the max number of error soure is 11, > which is classified by notification type. > > etc/acpi/tables etc/hardware_errors > ==================== ========================================== > + +--------------------------+ +------------------+ > | | HEST | | address | +--------------+ > | +--------------------------+ | registers | | Error Status | > | | GHES0 | | +----------------+ | Data Block 0 | > | +--------------------------+ +--------->| |status_address0 |------------->| +------------+ > | | ................. | | | +----------------+ | | CPER | > | | error_status_address-----+-+ +------->| |status_address1 |----------+ | | CPER | > | | ................. | | | +----------------+ | | | .... | > | | read_ack_register--------+-+ | | ............. | | | | CPER | > | | read_ack_preserve | | | +------------------+ | | +-+------------+ > | | read_ack_write | | | +----->| |status_address10|--------+ | | Error Status | > + +--------------------------+ | | | | +----------------+ | | | Data Block 1 | > | | GHES1 | +-+-+----->| | ack_value0 | | +-->| +------------+ > + +--------------------------+ | | | +----------------+ | | | CPER | > | | ................. | | | +--->| | ack_value1 | | | | CPER | > | | error_status_address-----+---+ | | | +----------------+ | | | .... | > | | ................. | | | | | ............. | | | | CPER | > | | read_ack_register--------+-----+-+ | +----------------+ | +-+------------+ > | | read_ack_preserve | | +->| | ack_value10 | | | |.......... | > | | read_ack_write | | | | +----------------+ | | +------------+ > + +--------------------------| | | | | Error Status | > | | ............... | | | | | Data Block 10| > + +--------------------------+ | | +---->| +------------+ > | | GHES10 | | | | | CPER | > + +--------------------------+ | | | | CPER | > | | ................. | | | | | .... | > | | error_status_address-----+-----+ | | | CPER | > | | ................. | | +-+------------+ > | | read_ack_register--------+---------+ > | | read_ack_preserve | > | | read_ack_write | > + +--------------------------+ > > For GHESv2 error source, the OSPM must acknowledges the error via Read Ack register. > so user space must check the ack value to avoid read-write race condition. > > Signed-off-by: Dongjiu Geng > --- > hw/acpi/aml-build.c | 2 + > hw/acpi/hest_ghes.c | 345 ++++++++++++++++++++++++++++++++++++++++++++ > hw/arm/virt-acpi-build.c | 6 + > include/hw/acpi/aml-build.h | 1 + > include/hw/acpi/hest_ghes.h | 47 ++++++ > 5 files changed, 401 insertions(+) > create mode 100644 hw/acpi/hest_ghes.c Don't need to add the new file to hw/acpi/Makefile.objs? > create mode 100644 include/hw/acpi/hest_ghes.h > > diff --git a/hw/acpi/aml-build.c b/hw/acpi/aml-build.c > index 36a6cc4..6849e5f 100644 > --- a/hw/acpi/aml-build.c > +++ b/hw/acpi/aml-build.c > @@ -1561,6 +1561,7 @@ void acpi_build_tables_init(AcpiBuildTables *tables) > tables->table_data = g_array_new(false, true /* clear */, 1); > tables->tcpalog = g_array_new(false, true /* clear */, 1); > tables->vmgenid = g_array_new(false, true /* clear */, 1); > + tables->hardware_errors = g_array_new(false, true /* clear */, 1); > tables->linker = bios_linker_loader_init(); > } > > @@ -1571,6 +1572,7 @@ void acpi_build_tables_cleanup(AcpiBuildTables *tables, bool mfre) > g_array_free(tables->table_data, true); > g_array_free(tables->tcpalog, mfre); > g_array_free(tables->vmgenid, mfre); > + g_array_free(tables->hardware_errors, mfre); > } > > /* Build rsdt table */ > diff --git a/hw/acpi/hest_ghes.c b/hw/acpi/hest_ghes.c > new file mode 100644 > index 0000000..ff6b5ef > --- /dev/null > +++ b/hw/acpi/hest_ghes.c > @@ -0,0 +1,345 @@ > +/* > + * APEI GHES table Generation > + * > + * Copyright (C) 2017 huawei. > + * > + * Author: Dongjiu Geng > + * > + * This work is licensed under the terms of the GNU GPL, version 2 or later. > + * See the COPYING file in the top-level directory. > + * > + */ Please unify this of this file and hest_ghes.h by refering to other files. > + > +#include "qemu/osdep.h" > +#include "qmp-commands.h" unnecessary including > +#include "hw/acpi/acpi.h" > +#include "hw/acpi/aml-build.h" > +#include "hw/acpi/hest_ghes.h" > +#include "hw/nvram/fw_cfg.h" > +#include "sysemu/sysemu.h" > +#include "qemu/error-report.h" > + > +/* The structure that stands for the layout > + * GHES_ERRORS_FW_CFG_FILE fw_cfg blob > + * > + * etc/hardware_errors > + * ========================================== > + * +------------------+ > + * | address | +--------------+ > + * | registers | | Error Status | > + * | +----------------+ | Data Block 0 | > + * | |status_address0 |------------->| +------------+ > + * | +----------------+ | | CPER | > + * | |status_address1 |----------+ | | CPER | > + * | +----------------+ | | | .... | > + * | |............. | | | | CPER | > + * | +----------------+ | | +------------+ > + * | |status_address10|-----+ | | Error Status | > + * | +----------------+ | | | Data Block 1 | > + * | |ack_value0 | | +-->| +------------+ > + * | +----------------+ | | | CPER | > + * | |ack_value1 | | | | CPER | > + * | +----------------+ | | | .... | > + * | | ............. | | | | CPER | > + * | +----------------+ | +-+------------+ > + * | |ack_value10 | | | |.......... | > + * | +----------------+ | | +------------+ > + * | | Error Status | > + * | | Data Block10 | > + * +------->+------------+ > + * | | CPER | > + * | | CPER | > + * | | .... | > + * | | CPER | > + * +-+------------+ > + */ > +struct hardware_errors_buffer { > + /* Generic Error Status Block register */ > + uint64_t gesb_address[GHES_ACPI_HEST_NOTIFY_RESERVED]; > + uint64_t ack_value[GHES_ACPI_HEST_NOTIFY_RESERVED]; > + char gesb[GHES_MAX_RAW_DATA_LENGTH][GHES_ACPI_HEST_NOTIFY_RESERVED]; > +}; > + > +static int ghes_record_cper(uint64_t error_block_address, > + uint64_t error_physical_addr) > +{ > + AcpiGenericErrorStatus block; > + AcpiGenericErrorData *gdata; > + UefiCperSecMemErr *mem_err; > + uint64_t current_block_length; > + unsigned char *buffer; > + /* memory section */ > + char mem_section_id_le[] = {0x14, 0x11, 0xBC, 0xA5, 0x64, 0x6F, 0xDE, > + 0x4E, 0xB8, 0x63, 0x3E, 0x83, 0xED, 0x7C, > + 0x83, 0xB1}; > + > + cpu_physical_memory_read(error_block_address, &block, > + sizeof(AcpiGenericErrorStatus)); > + > + /* Get the current generic error status block length */ > + current_block_length = sizeof(AcpiGenericErrorStatus) + > + le32_to_cpu(block.data_length); > + > + /* If the Generic Error Status Block is NULL, update > + * the block header > + */ > + if (!block.block_status) { > + block.block_status = ACPI_GEBS_UNCORRECTABLE; > + block.error_severity = ACPI_CPER_SEV_RECOVERABLE; > + } > + > + block.data_length += cpu_to_le32(sizeof(AcpiGenericErrorData)); > + block.data_length += cpu_to_le32(sizeof(UefiCperSecMemErr)); > + > + /* check whether it runs out of the preallocated memory */ > + if ((le32_to_cpu(block.data_length) + sizeof(AcpiGenericErrorStatus)) > > + GHES_MAX_RAW_DATA_LENGTH) { > + error_report("Record CPER out of boundary!!!"); > + return GHES_CPER_FAIL; > + } > + > + /* Write back the Generic Error Status Block to guest memory */ > + cpu_physical_memory_write(error_block_address, &block, > + sizeof(AcpiGenericErrorStatus)); > + > + /* Fill in Generic Error Data Entry */ > + buffer = g_malloc0(sizeof(AcpiGenericErrorData) + > + sizeof(UefiCperSecMemErr)); > + > + > + memset(buffer, 0, sizeof(AcpiGenericErrorData) + sizeof(UefiCperSecMemErr)); > + gdata = (AcpiGenericErrorData *)buffer; > + > + /* Memory section */ > + memcpy(&(gdata->section_type_le), &mem_section_id_le, > + sizeof(mem_section_id_le)); > + > + /* error severity is recoverable */ > + gdata->error_severity = ACPI_CPER_SEV_RECOVERABLE; > + gdata->revision = 0x300; /* the revision number is 0x300 */ > + gdata->error_data_length = cpu_to_le32(sizeof(UefiCperSecMemErr)); > + > + mem_err = (UefiCperSecMemErr *) (gdata + 1); > + > + /* User space only handle the memory section CPER */ > + > + /* Hard code to Multi-bit ECC error */ > + mem_err->validation_bits |= cpu_to_le32(UEFI_CPER_MEM_VALID_ERROR_TYPE); > + mem_err->error_type = cpu_to_le32(UEFI_CPER_MEM_ERROR_TYPE_MULTI_ECC); > + > + /* Record the physical address at which the memory error occurred */ > + mem_err->validation_bits |= cpu_to_le32(UEFI_CPER_MEM_VALID_PA); > + mem_err->physical_addr = cpu_to_le32(error_physical_addr); > + > + /* Write back the Generic Error Data Entry to guest memory */ > + cpu_physical_memory_write(error_block_address + current_block_length, > + buffer, sizeof(AcpiGenericErrorData) + sizeof(UefiCperSecMemErr)); > + > + g_free(buffer); > + return GHES_CPER_OK; > +} > + > +static void > +build_address(GArray *table_data, BIOSLinker *linker, > + uint32_t dst_patched_offset, uint32_t src_offset, > + uint8_t address_space_id , uint8_t register_bit_width, > + uint8_t register_bit_offset, uint8_t access_size) > +{ > + uint32_t address_size = sizeof(struct AcpiGenericAddress) - > + offsetof(struct AcpiGenericAddress, address); > + > + /* Address space */ > + build_append_int_noprefix(table_data, address_space_id, 1); > + /* register bit width */ > + build_append_int_noprefix(table_data, register_bit_width, 1); > + /* register bit offset */ > + build_append_int_noprefix(table_data, register_bit_offset, 1); > + /* access size */ > + build_append_int_noprefix(table_data, access_size, 1); > + acpi_data_push(table_data, address_size); > + > + /* Patch address of ERRORS fw_cfg blob into the TABLE fw_cfg blob so OSPM > + * can retrieve and read it. the address size is 64 bits. > + */ > + bios_linker_loader_add_pointer(linker, > + ACPI_BUILD_TABLE_FILE, dst_patched_offset, sizeof(uint64_t), > + GHES_ERRORS_FW_CFG_FILE, src_offset); > +} > + > +void ghes_build_acpi(GArray *table_data, GArray *hardware_error, > + BIOSLinker *linker) > +{ > + uint32_t ghes_start = table_data->len; > + uint32_t address_size, error_status_address_offset; > + uint32_t read_ack_register_offset, i; > + > + address_size = sizeof(struct AcpiGenericAddress) - > + offsetof(struct AcpiGenericAddress, address); > + > + error_status_address_offset = ghes_start + > + sizeof(AcpiHardwareErrorSourceTable) + > + offsetof(AcpiGenericHardwareErrorSourceV2, error_status_address) + > + offsetof(struct AcpiGenericAddress, address); > + > + read_ack_register_offset = ghes_start + > + sizeof(AcpiHardwareErrorSourceTable) + > + offsetof(AcpiGenericHardwareErrorSourceV2, read_ack_register) + > + offsetof(struct AcpiGenericAddress, address); > + > + acpi_data_push(hardware_error, > + offsetof(struct hardware_errors_buffer, ack_value)); > + for (i = 0; i < GHES_ACPI_HEST_NOTIFY_RESERVED; i++) > + /* Initialize read ack register */ > + build_append_int_noprefix((void *)hardware_error, 1, 8); > + > + /* Reserved the total size for ERRORS fw_cfg blob > + */ > + acpi_data_push(hardware_error, sizeof(struct hardware_errors_buffer)); > + > + /* Allocate guest memory for the Data fw_cfg blob */ > + bios_linker_loader_alloc(linker, GHES_ERRORS_FW_CFG_FILE, hardware_error, > + 1, false); > + /* Reserve table header size */ > + acpi_data_push(table_data, sizeof(AcpiTableHeader)); > + > + build_append_int_noprefix(table_data, GHES_ACPI_HEST_NOTIFY_RESERVED, 4); > + > + for (i = 0; i < GHES_ACPI_HEST_NOTIFY_RESERVED; i++) { > + build_append_int_noprefix(table_data, > + ACPI_HEST_SOURCE_GENERIC_ERROR_V2, 2); /* type */ > + /* source id */ > + build_append_int_noprefix(table_data, cpu_to_le16(i), 2); > + /* related source id */ > + build_append_int_noprefix(table_data, 0xffff, 2); > + build_append_int_noprefix(table_data, 0, 1); /* flags */ > + > + /* Currently only enable SEA notification type to avoid the kernel > + * warning, reserve the space for other notification error source > + */ > + if (i == ACPI_HEST_NOTIFY_SEA) { > + build_append_int_noprefix(table_data, 1, 1); /* enabled */ > + } else { > + build_append_int_noprefix(table_data, 0, 1); /* enabled */ > + } > + > + /* The number of error status block per generic hardware error source */ > + build_append_int_noprefix(table_data, 1, 4); > + /* Max sections per record */ > + build_append_int_noprefix(table_data, 1, 4); > + /* Max raw data length */ > + build_append_int_noprefix(table_data, GHES_MAX_RAW_DATA_LENGTH, 4); > + > + /* Build error status address*/ > + build_address(table_data, linker, error_status_address_offset + i * > + sizeof(AcpiGenericHardwareErrorSourceV2), i * address_size, > + AML_SYSTEM_MEMORY, 0x40, 0, 4 /* QWord access */); > + > + /* Hardware error notification structure */ > + build_append_int_noprefix(table_data, i, 1); /* type */ > + /* length */ > + build_append_int_noprefix(table_data, sizeof(AcpiHestNotify), 1); > + build_append_int_noprefix(table_data, 0, 26); > + > + /* Error Status Block Length */ > + build_append_int_noprefix(table_data, > + cpu_to_le32(GHES_MAX_RAW_DATA_LENGTH), 4); > + > + /* Build read ack register */ > + build_address(table_data, linker, read_ack_register_offset + i * > + sizeof(AcpiGenericHardwareErrorSourceV2), > + offsetof(struct hardware_errors_buffer, ack_value) + > + i * address_size, AML_SYSTEM_MEMORY, 0x40, 0, > + 4 /* QWord access */); > + > + /* Read ack preserve */ > + build_append_int_noprefix(table_data, cpu_to_le64(0xfffffffe), 8); > + > + /* Read ack write */ > + build_append_int_noprefix(table_data, cpu_to_le64(0x1), 8); > + } > + > + for (i = 0; i < GHES_ACPI_HEST_NOTIFY_RESERVED; i++) > + /* Patch address of generic error status block into > + * the address register so OSPM can retrieve and read it. > + */ > + bios_linker_loader_add_pointer(linker, > + GHES_ERRORS_FW_CFG_FILE, address_size * i, address_size, > + GHES_ERRORS_FW_CFG_FILE, > + offsetof(struct hardware_errors_buffer, gesb) + > + i * GHES_MAX_RAW_DATA_LENGTH); > + > + /* Patch address of ERRORS fw_cfg blob into the ADDR fw_cfg blob > + * so QEMU can write the ERRORS there. The address is expected to be > + * < 4GB, but write 64 bits anyway. > + */ > + bios_linker_loader_write_pointer(linker, GHES_DATA_ADDR_FW_CFG_FILE, > + 0, address_size, GHES_ERRORS_FW_CFG_FILE, > + offsetof(struct hardware_errors_buffer, gesb)); > + > + build_header(linker, table_data, > + (void *)(table_data->data + ghes_start), "HEST", > + table_data->len - ghes_start, 1, NULL, "GHES"); > +} > + > +static GhesState ges; > +void ghes_add_fw_cfg(FWCfgState *s, GArray *hardware_error) > +{ > + > + size_t request_block_size = sizeof(uint64_t) + GHES_MAX_RAW_DATA_LENGTH; > + size_t size = GHES_ACPI_HEST_NOTIFY_RESERVED * request_block_size; > + > + /* Create a read-only fw_cfg file for GHES */ > + fw_cfg_add_file(s, GHES_ERRORS_FW_CFG_FILE, hardware_error->data, > + size); > + /* Create a read-write fw_cfg file for Address */ > + fw_cfg_add_file_callback(s, GHES_DATA_ADDR_FW_CFG_FILE, NULL, NULL, > + &ges.ghes_addr_le, sizeof(ges.ghes_addr_le), false); > +} > + > +bool ghes_update_guest(uint32_t notify, uint64_t physical_address) > +{ > + uint64_t error_block_addr; > + uint64_t ack_value_addr, ack_value = 0; > + int loop = 0, ack_value_size; > + bool ret = GHES_CPER_FAIL; > + > + ack_value_size = (offsetof(struct hardware_errors_buffer, gesb) - > + offsetof(struct hardware_errors_buffer, ack_value)) / > + GHES_ACPI_HEST_NOTIFY_RESERVED; > + > + if (physical_address && notify < GHES_ACPI_HEST_NOTIFY_RESERVED) { > + error_block_addr = ges.ghes_addr_le + notify * GHES_MAX_RAW_DATA_LENGTH; > + error_block_addr = le32_to_cpu(error_block_addr); > + > + ack_value_addr = ges.ghes_addr_le - > + (GHES_ACPI_HEST_NOTIFY_RESERVED - notify) * ack_value_size; > +retry: > + cpu_physical_memory_read(ack_value_addr, &ack_value, ack_value_size); > + if (!ack_value) { > + if (loop < 3) { > + usleep(100 * 1000); > + loop++; > + goto retry; > + } else { > + error_report("Last time OSPM does not acknowledge the error," > + " record CPER failed this time, set the ack value to" > + " avoid blocking next time CPER record! exit"); > + ack_value = 1; > + cpu_physical_memory_write(ack_value_addr, > + &ack_value, ack_value_size); > + return ret; > + } > + } else { > + /* A zero value in ghes_addr means that BIOS has not yet written > + * the address > + */ > + if (error_block_addr) { > + ack_value = 0; > + cpu_physical_memory_write(ack_value_addr, > + &ack_value, ack_value_size); > + ret = ghes_record_cper(error_block_addr, physical_address); > + } > + } > + } > + return ret; > +} > diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c > index 3d78ff6..def1ec1 100644 > --- a/hw/arm/virt-acpi-build.c > +++ b/hw/arm/virt-acpi-build.c > @@ -45,6 +45,7 @@ > #include "hw/arm/virt.h" > #include "sysemu/numa.h" > #include "kvm_arm.h" > +#include "hw/acpi/hest_ghes.h" > > #define ARM_SPI_BASE 32 > #define ACPI_POWER_BUTTON_DEVICE "PWRB" > @@ -771,6 +772,9 @@ void virt_acpi_build(VirtMachineState *vms, AcpiBuildTables *tables) > acpi_add_table(table_offsets, tables_blob); > build_spcr(tables_blob, tables->linker, vms); > > + acpi_add_table(table_offsets, tables_blob); > + ghes_build_acpi(tables_blob, tables->hardware_errors, tables->linker); > + So we add this table unconditionally. Is there any bad impact if QEMU runs on old kvm? Does it need to check whether KVM supports RAS? > if (nb_numa_nodes > 0) { > acpi_add_table(table_offsets, tables_blob); > build_srat(tables_blob, tables->linker, vms); > @@ -887,6 +891,8 @@ void virt_acpi_setup(VirtMachineState *vms) > fw_cfg_add_file(vms->fw_cfg, ACPI_BUILD_TPMLOG_FILE, tables.tcpalog->data, > acpi_data_len(tables.tcpalog)); > > + ghes_add_fw_cfg(vms->fw_cfg, tables.hardware_errors); > + > build_state->rsdp_mr = acpi_add_rom_blob(build_state, tables.rsdp, > ACPI_BUILD_RSDP_FILE, 0); > > diff --git a/include/hw/acpi/aml-build.h b/include/hw/acpi/aml-build.h > index 88d0738..7f7b55c 100644 > --- a/include/hw/acpi/aml-build.h > +++ b/include/hw/acpi/aml-build.h > @@ -211,6 +211,7 @@ struct AcpiBuildTables { > GArray *rsdp; > GArray *tcpalog; > GArray *vmgenid; > + GArray *hardware_errors; > BIOSLinker *linker; > } AcpiBuildTables; > > diff --git a/include/hw/acpi/hest_ghes.h b/include/hw/acpi/hest_ghes.h > new file mode 100644 > index 0000000..0772756 > --- /dev/null > +++ b/include/hw/acpi/hest_ghes.h > @@ -0,0 +1,47 @@ > +/* > + * This program is free software; you can redistribute it and/or modify > + * it under the terms of the GNU General Public License as published by > + * the Free Software Foundation; either version 2 of the License, or > + * (at your option) any later version. > + > + * This program is distributed in the hope that it will be useful, > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > + * GNU General Public License for more details. > + * > + * Authors: > + * Dongjiu Geng > + * > + * You should have received a copy of the GNU General Public License along > + * with this program; if not, see . > + */ > + > +#ifndef ACPI_GHES_H > +#define ACPI_GHES_H > + > +#include "hw/acpi/bios-linker-loader.h" > + > +#define GHES_ERRORS_FW_CFG_FILE "etc/hardware_errors" > +#define GHES_DATA_ADDR_FW_CFG_FILE "etc/hardware_errors_addr" > + > +#define GHES_GAS_ADDRESS_OFFSET 4 > +#define GHES_ERROR_STATUS_ADDRESS_OFFSET 20 > +#define GHES_NOTIFICATION_STRUCTURE 32 > + > +#define GHES_CPER_OK 1 > +#define GHES_CPER_FAIL 0 > + > +#define GHES_ACPI_HEST_NOTIFY_RESERVED 11 > +/* The max size in Bytes for one error block */ > +#define GHES_MAX_RAW_DATA_LENGTH 0x1000 > + > + > +typedef struct GhesState { > + uint64_t ghes_addr_le; > +} GhesState; > + > +void ghes_build_acpi(GArray *table_data, GArray *hardware_error, > + BIOSLinker *linker); > +void ghes_add_fw_cfg(FWCfgState *s, GArray *hardware_errors); > +bool ghes_update_guest(uint32_t notify, uint64_t error_physical_addr); > +#endif > -- Shannon From MAILER-DAEMON Thu Aug 24 09:07:25 2017 Received: from list by lists.gnu.org with archive (Exim 4.71) id 1dkrr3-0002aL-PU for mharc-qemu-arm@gnu.org; Thu, 24 Aug 2017 09:07:25 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:35430) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dkrr2-0002ZH-0I for qemu-arm@nongnu.org; Thu, 24 Aug 2017 09:07:25 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dkrqx-0000pz-7s for qemu-arm@nongnu.org; Thu, 24 Aug 2017 09:07:23 -0400 Received: from szxga05-in.huawei.com ([45.249.212.191]:2242) by eggs.gnu.org with esmtps (TLS1.0:RSA_ARCFOUR_SHA1:16) (Exim 4.71) (envelope-from ) id 1dkrqw-0000nx-6S; Thu, 24 Aug 2017 09:07:19 -0400 Received: from 172.30.72.58 (EHLO DGGEMS414-HUB.china.huawei.com) ([172.30.72.58]) by dggrg05-dlp.huawei.com (MOS 4.4.6-GA FastPath queued) with ESMTP id DFW40217; Thu, 24 Aug 2017 21:06:18 +0800 (CST) Received: from [127.0.0.1] (10.177.16.142) by DGGEMS414-HUB.china.huawei.com (10.3.19.214) with Microsoft SMTP Server id 14.3.301.0; Thu, 24 Aug 2017 21:06:09 +0800 Message-ID: <599ECEF3.80001@huawei.com> Date: Thu, 24 Aug 2017 21:04:51 +0800 From: Shannon Zhao User-Agent: Mozilla/5.0 (Windows NT 6.1; rv:24.0) Gecko/20100101 Thunderbird/24.4.0 MIME-Version: 1.0 To: Dongjiu Geng , , , , , , , , , , , , , , , , , , , , , , , , , , , , CC: , , , References: <1503066227-18251-1-git-send-email-gengdongjiu@huawei.com> <1503066227-18251-4-git-send-email-gengdongjiu@huawei.com> In-Reply-To: <1503066227-18251-4-git-send-email-gengdongjiu@huawei.com> Content-Type: text/plain; charset="ISO-8859-1" Content-Transfer-Encoding: 7bit X-Originating-IP: [10.177.16.142] X-CFilter-Loop: Reflected X-Mirapoint-Virus-RAPID-Raw: score=unknown(0), refid=str=0001.0A090206.599ECF4A.00EA, ss=1, re=0.000, recu=0.000, reip=0.000, cl=1, cld=1, fgs=0, ip=0.0.0.0, so=2014-11-16 11:51:01, dmn=2013-03-21 17:37:32 X-Mirapoint-Loop-Id: 7e0f88feab02fe4188c23b25bdb7134b X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.4.x-2.6.x [generic] [fuzzy] X-Received-From: 45.249.212.191 Subject: Re: [Qemu-arm] [PATCH v11 3/6] ACPI: build and enable APEI GHES in the Makefile and configuration X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 24 Aug 2017 13:07:25 -0000 On 2017/8/18 22:23, Dongjiu Geng wrote: > Add CONFIG_ACPI_APEI configuration in the Makefile and > enable it in the arm-softmmu.mak > > Signed-off-by: Dongjiu Geng > --- > default-configs/arm-softmmu.mak | 1 + > hw/acpi/Makefile.objs | 1 + > 2 files changed, 2 insertions(+) > > diff --git a/default-configs/arm-softmmu.mak b/default-configs/arm-softmmu.mak > index bbdd3c1..c362113 100644 > --- a/default-configs/arm-softmmu.mak > +++ b/default-configs/arm-softmmu.mak > @@ -129,3 +129,4 @@ CONFIG_ACPI=y > CONFIG_SMBIOS=y > CONFIG_ASPEED_SOC=y > CONFIG_GPIO_KEY=y > +CONFIG_ACPI_APEI=y > diff --git a/hw/acpi/Makefile.objs b/hw/acpi/Makefile.objs > index 11c35bc..bafb148 100644 > --- a/hw/acpi/Makefile.objs > +++ b/hw/acpi/Makefile.objs > @@ -6,6 +6,7 @@ common-obj-$(CONFIG_ACPI_MEMORY_HOTPLUG) += memory_hotplug.o > common-obj-$(CONFIG_ACPI_CPU_HOTPLUG) += cpu.o > common-obj-$(CONFIG_ACPI_NVDIMM) += nvdimm.o > common-obj-$(CONFIG_ACPI_VMGENID) += vmgenid.o > +common-obj-$(CONFIG_ACPI_APEI) += hest_ghes.o > common-obj-$(call lnot,$(CONFIG_ACPI_X86)) += acpi-stub.o > > common-obj-y += acpi_interface.o > Fold this patch into previous one. Thanks, -- Shannon From MAILER-DAEMON Thu Aug 24 11:59:27 2017 Received: from list by lists.gnu.org with archive (Exim 4.71) id 1dkuXX-0003eG-OV for mharc-qemu-arm@gnu.org; Thu, 24 Aug 2017 11:59:27 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:48142) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dkuXU-0003cV-Re for qemu-arm@nongnu.org; Thu, 24 Aug 2017 11:59:26 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dkuXT-00063M-Mk for qemu-arm@nongnu.org; Thu, 24 Aug 2017 11:59:24 -0400 Received: from mail-yw0-x244.google.com ([2607:f8b0:4002:c05::244]:33264) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1dkuXO-0005za-Q2; Thu, 24 Aug 2017 11:59:18 -0400 Received: by mail-yw0-x244.google.com with SMTP id u133so1681501ywc.0; Thu, 24 Aug 2017 08:59:17 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id; bh=mCxoU6s2fGfnIbm2+bkacaR6glyHPvo3dQvfOD99Mfo=; b=KayGvoe192mKxXt+jBmEa4kyERXaPW2Ij2TpiKufeWfsH+J7pgpn05fkJgIqQu41Bo J5/wQYubfCHKoVmOipyqyqXUm6gEMISiuXHIHoKqZTVvAKZSLKKGbnZclyG1ESTJpv3e z73HTH1yco1VK0E+KLQkmnpSfa/dq66sVS42kSmuyGcDp7NlP9SxUSUjUtHTAaZ1d1zq 1aR+WQSLlHK6egDUUW/SgtVtMFifyuQRPQJE7Ce6yDxEvR7qoKCHrVDVcN5YyrK9RLxN zGez+DDGjz7ckDEpeNxZVTBUsYEjI1DXorzWYWBDmLUWstZDxMlkTrVNQeEPAjuum4lo Wt8w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=mCxoU6s2fGfnIbm2+bkacaR6glyHPvo3dQvfOD99Mfo=; b=bnseGStBhrbtXZ26GZfXG5n5iG6ECs9MNxQN3fJSoRHu5C3yGhj/dIz0fYykdG5FH/ D0lwZLzK740YhkK0+6wjT7PdSh52mHIR9Ic81CaC/5Y4OMXGp0fAce/82pSw1KcaHVeh RfnX9CDpuefg+Ts7+4jVF1TLQxGxvycDQzCEmr0vNLCsO8y5YbjDZeXr8NrACLZlE5Vf tJJL/VQQ/yRNwgB5YC2m3FKzFThR9u8ZLOS5RIOjw1FdtHWLZR08QdUmKWTLe1H9LLWn VHQkhesA4yz3dmpBl+6FL+VoQerARuxrT7tie7W7ev2SYn1RzZs9GWBY2Vkn0HCgmdov QWuw== X-Gm-Message-State: AHYfb5jr1y/lM2UyA1QoviC4ulC3hdUurLai6pWjbA2HqhzBFCrEZW+S fkCwnUrhb85Org== X-Received: by 10.37.244.13 with SMTP id q13mr5323445ybd.152.1503590356690; Thu, 24 Aug 2017 08:59:16 -0700 (PDT) Received: from localhost.localdomain ([98.192.46.210]) by smtp.gmail.com with ESMTPSA id v187sm1636867ywb.78.2017.08.24.08.59.15 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 24 Aug 2017 08:59:16 -0700 (PDT) From: Pranith Kumar To: alex.bennee@linaro.org, Paolo Bonzini , Peter Crosthwaite , Richard Henderson , Claudio Fontana , Andrzej Zaborowski , Aurelien Jarno , Alexander Graf , Stefan Weil , qemu-devel@nongnu.org (open list:Overall), qemu-arm@nongnu.org (open list:AArch64 target) Cc: qemu-devel@nongnu.org Date: Thu, 24 Aug 2017 11:58:49 -0400 Message-Id: <20170824155849.30799-1-bobby.prani@gmail.com> X-Mailer: git-send-email 2.13.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4002:c05::244 Subject: [Qemu-arm] [RFC v2 PATCH] tcg/softmmu: Increase size of TLB caches X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 24 Aug 2017 15:59:26 -0000 This patch increases the number of entries cached in the TLB. I went over a few architectures to see if increasing it is problematic. Only armv6 seems to have a limitation that only 8 bits can be used for indexing these entries. For other architectures, the number of TLB entries is increased to a 4K-sized cache. The patch also doubles the number of victim TLB entries. A few statistics collected from a build benchmark for various cache sizes is below: | TLB bits\vTLB entires | 8 | 16 | 32 | | 8 | 952.94(+0.0%) | 929.99(+2.4%) | 919.02(+3.6%) | | 10 | 898.92(+5.6%) | 886.13(+7.0%) | 887.03(+6.9%) | | 12 | 878.56(+7.8%) | 873.53(+8.3%)* | 875.34(+8.1%) | The best combination for this workload came out to be 12 bits for the TLB and a 16 entry vTLB cache. Signed-off-by: Pranith Kumar --- include/exec/cpu-defs.h | 6 +++--- tcg/aarch64/tcg-target.h | 1 + tcg/arm/tcg-target.h | 1 + tcg/i386/tcg-target.h | 2 ++ tcg/ia64/tcg-target.h | 1 + tcg/mips/tcg-target.h | 1 + tcg/ppc/tcg-target.h | 1 + tcg/s390/tcg-target.h | 1 + tcg/sparc/tcg-target.h | 1 + tcg/tci/tcg-target.h | 1 + 10 files changed, 13 insertions(+), 3 deletions(-) diff --git a/include/exec/cpu-defs.h b/include/exec/cpu-defs.h index bc8e7f848d..a5e1ad6cea 100644 --- a/include/exec/cpu-defs.h +++ b/include/exec/cpu-defs.h @@ -57,8 +57,8 @@ typedef uint64_t target_ulong; #endif #if !defined(CONFIG_USER_ONLY) && defined(CONFIG_TCG) -/* use a fully associative victim tlb of 8 entries */ -#define CPU_VTLB_SIZE 8 +/* use a fully associative victim tlb of 16 entries */ +#define CPU_VTLB_SIZE 16 #if HOST_LONG_BITS == 32 && TARGET_LONG_BITS == 32 #define CPU_TLB_ENTRY_BITS 4 @@ -89,7 +89,7 @@ typedef uint64_t target_ulong; * of tlb_table inside env (which is non-trivial but not huge). */ #define CPU_TLB_BITS \ - MIN(8, \ + MIN(CPU_TLB_BITS_MAX, \ TCG_TARGET_TLB_DISPLACEMENT_BITS - CPU_TLB_ENTRY_BITS - \ (NB_MMU_MODES <= 1 ? 0 : \ NB_MMU_MODES <= 2 ? 1 : \ diff --git a/tcg/aarch64/tcg-target.h b/tcg/aarch64/tcg-target.h index 55a46ac825..f428e09c98 100644 --- a/tcg/aarch64/tcg-target.h +++ b/tcg/aarch64/tcg-target.h @@ -15,6 +15,7 @@ #define TCG_TARGET_INSN_UNIT_SIZE 4 #define TCG_TARGET_TLB_DISPLACEMENT_BITS 24 +#define CPU_TLB_BITS_MAX 12 #undef TCG_TARGET_STACK_GROWSUP typedef enum { diff --git a/tcg/arm/tcg-target.h b/tcg/arm/tcg-target.h index 5ef1086710..69414be393 100644 --- a/tcg/arm/tcg-target.h +++ b/tcg/arm/tcg-target.h @@ -60,6 +60,7 @@ extern int arm_arch; #undef TCG_TARGET_STACK_GROWSUP #define TCG_TARGET_INSN_UNIT_SIZE 4 #define TCG_TARGET_TLB_DISPLACEMENT_BITS 16 +#define CPU_TLB_BITS_MAX 8 typedef enum { TCG_REG_R0 = 0, diff --git a/tcg/i386/tcg-target.h b/tcg/i386/tcg-target.h index 73a15f7e80..35c27a977b 100644 --- a/tcg/i386/tcg-target.h +++ b/tcg/i386/tcg-target.h @@ -162,6 +162,8 @@ extern bool have_popcnt; # define TCG_AREG0 TCG_REG_EBP #endif +#define CPU_TLB_BITS_MAX 12 + static inline void flush_icache_range(uintptr_t start, uintptr_t stop) { } diff --git a/tcg/ia64/tcg-target.h b/tcg/ia64/tcg-target.h index 901bb7575d..fd713f7adf 100644 --- a/tcg/ia64/tcg-target.h +++ b/tcg/ia64/tcg-target.h @@ -28,6 +28,7 @@ #define TCG_TARGET_INSN_UNIT_SIZE 16 #define TCG_TARGET_TLB_DISPLACEMENT_BITS 21 +#define CPU_TLB_BITS_MAX 8 typedef struct { uint64_t lo __attribute__((aligned(16))); diff --git a/tcg/mips/tcg-target.h b/tcg/mips/tcg-target.h index d75cb63ed3..fd9046b7ad 100644 --- a/tcg/mips/tcg-target.h +++ b/tcg/mips/tcg-target.h @@ -37,6 +37,7 @@ #define TCG_TARGET_INSN_UNIT_SIZE 4 #define TCG_TARGET_TLB_DISPLACEMENT_BITS 16 +#define CPU_TLB_BITS_MAX 12 #define TCG_TARGET_NB_REGS 32 typedef enum { diff --git a/tcg/ppc/tcg-target.h b/tcg/ppc/tcg-target.h index 5f4a40a5b4..f5071f706d 100644 --- a/tcg/ppc/tcg-target.h +++ b/tcg/ppc/tcg-target.h @@ -34,6 +34,7 @@ #define TCG_TARGET_NB_REGS 32 #define TCG_TARGET_INSN_UNIT_SIZE 4 #define TCG_TARGET_TLB_DISPLACEMENT_BITS 16 +#define CPU_TLB_BITS_MAX 8 typedef enum { TCG_REG_R0, TCG_REG_R1, TCG_REG_R2, TCG_REG_R3, diff --git a/tcg/s390/tcg-target.h b/tcg/s390/tcg-target.h index 957f0c0afe..218be322ad 100644 --- a/tcg/s390/tcg-target.h +++ b/tcg/s390/tcg-target.h @@ -27,6 +27,7 @@ #define TCG_TARGET_INSN_UNIT_SIZE 2 #define TCG_TARGET_TLB_DISPLACEMENT_BITS 19 +#define CPU_TLB_BITS_MAX 12 typedef enum TCGReg { TCG_REG_R0 = 0, diff --git a/tcg/sparc/tcg-target.h b/tcg/sparc/tcg-target.h index 854a0afd70..9fd59a64f2 100644 --- a/tcg/sparc/tcg-target.h +++ b/tcg/sparc/tcg-target.h @@ -29,6 +29,7 @@ #define TCG_TARGET_INSN_UNIT_SIZE 4 #define TCG_TARGET_TLB_DISPLACEMENT_BITS 32 +#define CPU_TLB_BITS_MAX 12 #define TCG_TARGET_NB_REGS 32 typedef enum { diff --git a/tcg/tci/tcg-target.h b/tcg/tci/tcg-target.h index 06963288dc..3d39d479ea 100644 --- a/tcg/tci/tcg-target.h +++ b/tcg/tci/tcg-target.h @@ -43,6 +43,7 @@ #define TCG_TARGET_INTERPRETER 1 #define TCG_TARGET_INSN_UNIT_SIZE 1 #define TCG_TARGET_TLB_DISPLACEMENT_BITS 32 +#define CPU_TLB_BITS_MAX 8 #if UINTPTR_MAX == UINT32_MAX # define TCG_TARGET_REG_BITS 32 -- 2.13.0 From MAILER-DAEMON Thu Aug 24 12:02:58 2017 Received: from list by lists.gnu.org with archive (Exim 4.71) id 1dkuaw-0006XY-Hs for mharc-qemu-arm@gnu.org; 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X-Received-From: 2607:f8b0:4001:c06::230 Subject: Re: [Qemu-arm] [RFC v2 PATCH] tcg/softmmu: Increase size of TLB caches X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 24 Aug 2017 16:02:57 -0000 On Thu, Aug 24, 2017 at 11:58 AM, Pranith Kumar wrote: > This patch increases the number of entries cached in the TLB. I went > over a few architectures to see if increasing it is problematic. Only > armv6 seems to have a limitation that only 8 bits can be used for > indexing these entries. For other architectures, the number of TLB > entries is increased to a 4K-sized cache. The patch also doubles the > number of victim TLB entries. > > A few statistics collected from a build benchmark for various cache > sizes is below: > > | TLB bits\vTLB entires | 8 | 16 | 32 | > | 8 | 952.94(+0.0%) | 929.99(+2.4%) | 919.02(+3.6%) | > | 10 | 898.92(+5.6%) | 886.13(+7.0%) | 887.03(+6.9%) | > | 12 | 878.56(+7.8%) | 873.53(+8.3%)* | 875.34(+8.1%) | > > The best combination for this workload came out to be 12 bits for the > TLB and a 16 entry vTLB cache. You can find the raw data here: http://paste.ubuntu.com/25383585/ Thanks, -- Pranith From MAILER-DAEMON Fri Aug 25 05:34:27 2017 Received: from list by lists.gnu.org with archive (Exim 4.71) id 1dlB0V-0001NO-36 for mharc-qemu-arm@gnu.org; Fri, 25 Aug 2017 05:34:27 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:46671) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dlB0Q-0001Lg-QB for qemu-arm@nongnu.org; Fri, 25 Aug 2017 05:34:24 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dlB0Q-0001ST-19 for qemu-arm@nongnu.org; Fri, 25 Aug 2017 05:34:22 -0400 Received: from mail-wm0-x233.google.com ([2a00:1450:400c:c09::233]:34333) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1dlB0P-0001Rw-RF for qemu-arm@nongnu.org; Fri, 25 Aug 2017 05:34:21 -0400 Received: by mail-wm0-x233.google.com with SMTP id r187so3672428wma.1 for ; Fri, 25 Aug 2017 02:34:21 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:in-reply-to:references:from:date:message-id:subject:to :cc; bh=Q0ox92N4cjNhzJTdHkjnIMOois3yAbWo+/egkS4GKc0=; b=OeGUC0gzmejDnlKd+7pfE9FVs2s2sTCMgRhfJ/FgftwdHEdrGYoTHAqh+UIjdubMTV fTB6XWSaAWHQszvL9IZDUBtt8ww234mApxWDidUR4pwI2Fd8ypRSQksQD+t54UeFt9gC pzlkkdnXDGEmAkzeoiRLnqmzyCSyfo0dMXcsc= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:in-reply-to:references:from:date :message-id:subject:to:cc; bh=Q0ox92N4cjNhzJTdHkjnIMOois3yAbWo+/egkS4GKc0=; b=YPLHs4/3nk9Yj7EgB5YXK1XdIjJ1QEK8QtHPrsa/hsFm9c9O1mv7hFf+yp44r6f5f7 Hrg94q1TQ+aKfSRzERT39oWcgmOEbybAyZAVDcaZB7NcDmdQhIsNRRI/+7Qk+c0Lx8wD 7hzJFlUdS742QdwDOVUyGdO/95cQOIH6G3pggvfmuP4HfVj/njlPM44+Q2f32rqOI5R5 SalnsyCuZUARSAIJpd1D9/erB+3gNnpUl5MRe5uOy+v2KqOT8yKF32cyzoKfLqse0Qcb 8WLb52Ing7FGrCyp1bFHVSsXC1hlUr4x/u1oFW6Vt2rtpx9y55NpUbw/HZW2G/6ZTSUh xvKQ== X-Gm-Message-State: AHYfb5jt8VrJT/y1SgXJm0wWm2k5adSSBT/vY60HV00GbcFv90HBTdPC OXf3diqXvvpd/ArqkPh3LNoctiOX/WYzIlo= X-Received: by 10.28.152.87 with SMTP id a84mr845150wme.130.1503653660603; Fri, 25 Aug 2017 02:34:20 -0700 (PDT) MIME-Version: 1.0 Received: by 10.223.134.54 with HTTP; Fri, 25 Aug 2017 02:34:00 -0700 (PDT) In-Reply-To: <1503414539-28762-6-git-send-email-peter.maydell@linaro.org> References: <1503414539-28762-1-git-send-email-peter.maydell@linaro.org> <1503414539-28762-6-git-send-email-peter.maydell@linaro.org> From: Peter Maydell Date: Fri, 25 Aug 2017 10:34:00 +0100 Message-ID: To: qemu-arm , QEMU Developers Cc: "patches@linaro.org" Content-Type: text/plain; charset="UTF-8" X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:400c:c09::233 Subject: Re: [Qemu-arm] [PATCH 05/20] target/arm: Add MMU indexes for secure v8M X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 25 Aug 2017 09:34:24 -0000 On 22 August 2017 at 16:08, Peter Maydell wrote: > Now that MPU lookups can return different results for v8M > when the CPU is in secure vs non-secure state, we need to > have separate MMU indexes; add the secure counterparts > to the existing three M profile MMU indexes. > @@ -2206,7 +2217,11 @@ static inline int cpu_mmu_index(CPUARMState *env, bool ifetch) > */ > if ((env->v7m.exception > 0 && env->v7m.exception <= 3) > || env->v7m.faultmask) { > - return arm_to_core_mmu_idx(ARMMMUIdx_MNegPri); > + mmu_idx = ARMMMUIdx_MNegPri; > + } Incidentally this is not exactly the right check to make when the security extension is present, but at this point in the series it's the best we can do (the right check requires us to have exception banking support in the NVIC so we can check secure HF and nonsecure HF separately); the patch to do it right will come after the NVIC patches. thanks -- PMM From MAILER-DAEMON Fri Aug 25 06:38:52 2017 Received: from list by lists.gnu.org with archive (Exim 4.71) id 1dlC0q-0002qj-DC for mharc-qemu-arm@gnu.org; Fri, 25 Aug 2017 06:38:52 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:39531) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dlC0l-0002oD-E1 for qemu-arm@nongnu.org; Fri, 25 Aug 2017 06:38:50 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dlC0k-0003Xa-0h for qemu-arm@nongnu.org; Fri, 25 Aug 2017 06:38:47 -0400 Received: from szxga05-in.huawei.com ([45.249.212.191]:2243) by eggs.gnu.org with esmtps (TLS1.0:RSA_ARCFOUR_SHA1:16) (Exim 4.71) (envelope-from ) id 1dlC0i-0003VI-Sg; Fri, 25 Aug 2017 06:38:45 -0400 Received: from 172.30.72.59 (EHLO DGGEMS412-HUB.china.huawei.com) ([172.30.72.59]) by dggrg05-dlp.huawei.com (MOS 4.4.6-GA FastPath queued) with ESMTP id DFY09918; Fri, 25 Aug 2017 18:37:57 +0800 (CST) Received: from [127.0.0.1] (10.142.68.147) by DGGEMS412-HUB.china.huawei.com (10.3.19.212) with Microsoft SMTP Server id 14.3.301.0; Fri, 25 Aug 2017 18:37:48 +0800 To: Shannon Zhao , , , , , , , , , , , , , , , , , , , , , , , , , , , , , References: <1503066227-18251-1-git-send-email-gengdongjiu@huawei.com> <1503066227-18251-2-git-send-email-gengdongjiu@huawei.com> <599EC7AB.3080604@huawei.com> CC: , , , From: gengdongjiu Message-ID: <69090a96-ce90-4b2b-a419-c8d847d56093@huawei.com> Date: Fri, 25 Aug 2017 18:37:44 +0800 User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:45.0) Gecko/20100101 Thunderbird/45.7.1 MIME-Version: 1.0 In-Reply-To: <599EC7AB.3080604@huawei.com> Content-Type: text/plain; charset="windows-1252" Content-Transfer-Encoding: 7bit X-Originating-IP: [10.142.68.147] X-CFilter-Loop: Reflected X-Mirapoint-Virus-RAPID-Raw: score=unknown(0), refid=str=0001.0A090206.599FFE07.0131, ss=1, re=0.000, recu=0.000, reip=0.000, cl=1, cld=1, fgs=0, ip=0.0.0.0, so=2014-11-16 11:51:01, dmn=2013-03-21 17:37:32 X-Mirapoint-Loop-Id: c1335e206e8c45edacacb8cba8c0d529 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.4.x-2.6.x [generic] [fuzzy] X-Received-From: 45.249.212.191 Subject: Re: [Qemu-arm] [PATCH v11 1/6] ACPI: add APEI/HEST/CPER structures and macros X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 25 Aug 2017 10:38:50 -0000 Shannon, Thanks for the review. please see my reply. On 2017/8/24 20:33, Shannon Zhao wrote: > > > On 2017/8/18 22:23, Dongjiu Geng wrote: >> (1) Add related APEI/HEST table structures and macros, these >> definition refer to ACPI 6.1 and UEFI 2.6 spec. >> (2) Add generic error status block and CPER memory section >> definition, user space only handle memory section errors. >> >> Signed-off-by: Dongjiu Geng >> --- >> include/hw/acpi/acpi-defs.h | 193 ++++++++++++++++++++++++++++++++++++++++++++ >> 1 file changed, 193 insertions(+) >> >> diff --git a/include/hw/acpi/acpi-defs.h b/include/hw/acpi/acpi-defs.h >> index 72be675..3b4bad7 100644 >> --- a/include/hw/acpi/acpi-defs.h >> +++ b/include/hw/acpi/acpi-defs.h >> @@ -297,6 +297,44 @@ typedef struct AcpiMultipleApicTable AcpiMultipleApicTable; >> #define ACPI_APIC_GENERIC_TRANSLATOR 15 >> #define ACPI_APIC_RESERVED 16 /* 16 and greater are reserved */ >> >> +/* UEFI Spec 2.6, "N.2.5 Memory Error Section */ > missing " thanks for the pointing out. > >> +#define UEFI_CPER_MEM_VALID_ERROR_STATUS 0x0001 >> +#define UEFI_CPER_MEM_VALID_PA 0x0002 >> +#define UEFI_CPER_MEM_VALID_PA_MASK 0x0004 >> +#define UEFI_CPER_MEM_VALID_NODE 0x0008 >> +#define UEFI_CPER_MEM_VALID_CARD 0x0010 >> +#define UEFI_CPER_MEM_VALID_MODULE 0x0020 >> +#define UEFI_CPER_MEM_VALID_BANK 0x0040 >> +#define UEFI_CPER_MEM_VALID_DEVICE 0x0080 >> +#define UEFI_CPER_MEM_VALID_ROW 0x0100 >> +#define UEFI_CPER_MEM_VALID_COLUMN 0x0200 >> +#define UEFI_CPER_MEM_VALID_BIT_POSITION 0x0400 >> +#define UEFI_CPER_MEM_VALID_REQUESTOR 0x0800 >> +#define UEFI_CPER_MEM_VALID_RESPONDER 0x1000 >> +#define UEFI_CPER_MEM_VALID_TARGET 0x2000 >> +#define UEFI_CPER_MEM_VALID_ERROR_TYPE 0x4000 >> +#define UEFI_CPER_MEM_VALID_RANK_NUMBER 0x8000 >> +#define UEFI_CPER_MEM_VALID_CARD_HANDLE 0x10000 >> +#define UEFI_CPER_MEM_VALID_MODULE_HANDLE 0x20000 >> +#define UEFI_CPER_MEM_ERROR_TYPE_MULTI_ECC 3 >> + >> +/* From the ACPI 6.1 spec, "18.3.2.9 Hardware Error Notification" */ >> + > It's better to refer to the first spec version of this structure and > same with others you define. do you mean which spec version? the definition is aligned with the linux kernel. > >> +enum AcpiHestNotifyType { >> + ACPI_HEST_NOTIFY_POLLED = 0, >> + ACPI_HEST_NOTIFY_EXTERNAL = 1, >> + ACPI_HEST_NOTIFY_LOCAL = 2, >> + ACPI_HEST_NOTIFY_SCI = 3, >> + ACPI_HEST_NOTIFY_NMI = 4, >> + ACPI_HEST_NOTIFY_CMCI = 5, /* ACPI 5.0 */ >> + ACPI_HEST_NOTIFY_MCE = 6, /* ACPI 5.0 */ >> + ACPI_HEST_NOTIFY_GPIO = 7, /* ACPI 6.0 */ >> + ACPI_HEST_NOTIFY_SEA = 8, /* ACPI 6.1 */ >> + ACPI_HEST_NOTIFY_SEI = 9, /* ACPI 6.1 */ >> + ACPI_HEST_NOTIFY_GSIV = 10, /* ACPI 6.1 */ >> + ACPI_HEST_NOTIFY_RESERVED = 11 /* 11 and greater are reserved */ > In ACPI 6.2, 11 is for Software Delegated Exception, is this useful for > your patchset? it is usefull, for all the error source, I reserved the space for them. Because the space is allocated one time, is not dynamically allocated. so I use the ACPI_HEST_NOTIFY_RESERVED to specify that there is 11 error source. > >> +}; >> + >> /* >> * MADT sub-structures (Follow MULTIPLE_APIC_DESCRIPTION_TABLE) >> */ >> @@ -474,6 +512,161 @@ struct AcpiSystemResourceAffinityTable { >> } QEMU_PACKED; >> typedef struct AcpiSystemResourceAffinityTable AcpiSystemResourceAffinityTable; >> >> +/* Hardware Error Notification, from the ACPI 6.1 >> + * spec, "18.3.2.9 Hardware Error Notification" >> + */ > Use below style for multiple comment lines > /* > * XXX > */ you are right, thanks for the pointing out. > >> +struct AcpiHestNotify { >> + uint8_t type; >> + uint8_t length; >> + uint16_t config_write_enable; >> + uint32_t poll_interval; >> + uint32_t vector; >> + uint32_t polling_threshold_value; >> + uint32_t polling_threshold_window; >> + uint32_t error_threshold_value; >> + uint32_t error_threshold_window; >> +} QEMU_PACKED; >> +typedef struct AcpiHestNotify AcpiHestNotify; >> + >> +/* From ACPI 6.1, sections "18.3.2.1 IA-32 Architecture Machine >> + * Check Exception" through "18.3.2.8 Generic Hardware Error Source version 2". >> + */ >> +enum AcpiHestSourceType { >> + ACPI_HEST_SOURCE_IA32_CHECK = 0, >> + ACPI_HEST_SOURCE_IA32_CORRECTED_CHECK = 1, >> + ACPI_HEST_SOURCE_IA32_NMI = 2, > What's 3, 4, 5 for? the ACPI spec do not use 3, 4, 5, so we not define them. > >> + ACPI_HEST_SOURCE_AER_ROOT_PORT = 6, >> + ACPI_HEST_SOURCE_AER_ENDPOINT = 7, >> + ACPI_HEST_SOURCE_AER_BRIDGE = 8, >> + ACPI_HEST_SOURCE_GENERIC_ERROR = 9, >> + ACPI_HEST_SOURCE_GENERIC_ERROR_V2 = 10, >> + ACPI_HEST_SOURCE_RESERVED = 11 /* 11 and greater are reserved */ >> +}; >> + >> +/* Block status bitmasks from ACPI 6.1, "18.3.2.7.1 Generic Error Data" */ >> +#define ACPI_GEBS_UNCORRECTABLE (1) >> +#define ACPI_GEBS_CORRECTABLE (1 << 1) >> +#define ACPI_GEBS_MULTIPLE_UNCORRECTABLE (1 << 2) >> +#define ACPI_GEBS_MULTIPLE_CORRECTABLE (1 << 3) >> +/* 10 bits, error data entry count */ >> +#define ACPI_GEBS_ERROR_ENTRY_COUNT (0x3FF << 4) >> + >> +/* Generic Hardware Error Source Structure, refer to ACPI 6.1 >> + * "18.3.2.7 Generic Hardware Error Source". in this struct the >> + * "type" field has to be ACPI_HEST_SOURCE_GENERIC_ERROR >> + */ >> + >> +struct AcpiGenericHardwareErrorSource { >> + uint16_t type; >> + uint16_t source_id; >> + uint16_t related_source_id; >> + uint8_t flags; >> + uint8_t enabled; >> + uint32_t number_of_records; >> + uint32_t max_sections_per_record; >> + uint32_t max_raw_data_length; >> + struct AcpiGenericAddress error_status_address; >> + struct AcpiHestNotify notify; >> + uint32_t error_status_block_length; >> +} QEMU_PACKED; >> +typedef struct AcpiGenericHardwareErrorSource AcpiGenericHardwareErrorSource; >> + >> +/* Generic Hardware Error Source, version 2, ACPI 6.1, "18.3.2.8 Generic >> + * Hardware Error Source version 2", in this struct the "type" field has to >> + * be ACPI_HEST_SOURCE_GENERIC_ERROR_V2 >> + */ >> +struct AcpiGenericHardwareErrorSourceV2 { >> + uint16_t type; >> + uint16_t source_id; >> + uint16_t related_source_id; >> + uint8_t flags; >> + uint8_t enabled; >> + uint32_t number_of_records; >> + uint32_t max_sections_per_record; >> + uint32_t max_raw_data_length; >> + struct AcpiGenericAddress error_status_address; >> + struct AcpiHestNotify notify; >> + uint32_t error_status_block_length; >> + struct AcpiGenericAddress read_ack_register; >> + uint64_t read_ack_preserve; >> + uint64_t read_ack_write; >> +} QEMU_PACKED; >> +typedef struct AcpiGenericHardwareErrorSourceV2 >> + AcpiGenericHardwareErrorSourceV2; >> + >> +/* Generic Error Status block, from ACPI 6.1, >> + * "18.3.2.7.1 Generic Error Data" >> + */ >> +struct AcpiGenericErrorStatus { >> + /* It is a bitmask composed of ACPI_GEBS_xxx macros */ >> + uint32_t block_status; >> + uint32_t raw_data_offset; >> + uint32_t raw_data_length; >> + uint32_t data_length; >> + uint32_t error_severity; >> +} QEMU_PACKED; >> +typedef struct AcpiGenericErrorStatus AcpiGenericErrorStatus; >> + >> +enum AcpiGenericErrorSeverity { >> + ACPI_CPER_SEV_RECOVERABLE, >> + ACPI_CPER_SEV_FATAL, >> + ACPI_CPER_SEV_CORRECTED, >> + ACPI_CPER_SEV_NONE, >> +}; >> + >> +/* Generic Error Data entry, revision number is 0x0300, >> + * ACPI 6.1, "18.3.2.7.1 Generic Error Data" >> + */ >> +struct AcpiGenericErrorData { >> + uint8_t section_type_le[16]; >> + /* The "error_severity" fields that they take their >> + * values from AcpiGenericErrorSeverity >> + */ >> + uint32_t error_severity; >> + uint16_t revision; >> + uint8_t validation_bits; >> + uint8_t flags; >> + uint32_t error_data_length; >> + uint8_t fru_id[16]; >> + uint8_t fru_text[20]; >> + uint64_t time_stamp; >> +} QEMU_PACKED; >> +typedef struct AcpiGenericErrorData AcpiGenericErrorData; >> + >> +/* From UEFI 2.6, "N.2.5 Memory Error Section" */ >> +struct UefiCperSecMemErr { >> + uint64_t validation_bits; >> + uint64_t error_status; >> + uint64_t physical_addr; >> + uint64_t physical_addr_mask; >> + uint16_t node; >> + uint16_t card; >> + uint16_t module; >> + uint16_t bank; >> + uint16_t device; >> + uint16_t row; >> + uint16_t column; >> + uint16_t bit_pos; >> + uint64_t requestor_id; >> + uint64_t responder_id; >> + uint64_t target_id; >> + uint8_t error_type; >> + uint8_t reserved; >> + uint16_t rank; >> + uint16_t mem_array_handle; /* card handle in UEFI 2.4 */ >> + uint16_t mem_dev_handle; /* module handle in UEFI 2.4 */ >> +} QEMU_PACKED; >> +typedef struct UefiCperSecMemErr UefiCperSecMemErr; >> + >> +/* >> + * HEST Description Table >> + */ >> +struct AcpiHardwareErrorSourceTable { >> + ACPI_TABLE_HEADER_DEF /* ACPI common table header */ >> + uint32_t error_source_count; >> +} QEMU_PACKED; >> +typedef struct AcpiHardwareErrorSourceTable AcpiHardwareErrorSourceTable; >> + >> #define ACPI_SRAT_PROCESSOR_APIC 0 >> #define ACPI_SRAT_MEMORY 1 >> #define ACPI_SRAT_PROCESSOR_x2APIC 2 >> > From MAILER-DAEMON Fri Aug 25 07:21:11 2017 Received: from list by lists.gnu.org with archive (Exim 4.71) id 1dlCfn-0008NP-LJ for mharc-qemu-arm@gnu.org; Fri, 25 Aug 2017 07:21:11 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:55875) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dlCfj-0008LF-MK for qemu-arm@nongnu.org; Fri, 25 Aug 2017 07:21:10 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dlCfg-0006wO-UG for qemu-arm@nongnu.org; Fri, 25 Aug 2017 07:21:07 -0400 Received: from szxga04-in.huawei.com ([45.249.212.190]:2299) by eggs.gnu.org with esmtps (TLS1.0:RSA_ARCFOUR_SHA1:16) (Exim 4.71) (envelope-from ) id 1dlCff-0006op-Ig; Fri, 25 Aug 2017 07:21:04 -0400 Received: from 172.30.72.59 (EHLO DGGEMS409-HUB.china.huawei.com) ([172.30.72.59]) by dggrg04-dlp.huawei.com (MOS 4.4.6-GA FastPath queued) with ESMTP id DFW14958; Fri, 25 Aug 2017 19:20:23 +0800 (CST) Received: from [127.0.0.1] (10.142.68.147) by DGGEMS409-HUB.china.huawei.com (10.3.19.209) with Microsoft SMTP Server id 14.3.301.0; Fri, 25 Aug 2017 19:20:07 +0800 To: Shannon Zhao , , , , , , , , , , , , , , , , , , , , , , , , , , , , , References: <1503066227-18251-1-git-send-email-gengdongjiu@huawei.com> <1503066227-18251-3-git-send-email-gengdongjiu@huawei.com> <599ECE95.10205@huawei.com> CC: , , , From: gengdongjiu Message-ID: <9a878b42-c480-2c7b-0f04-202193d8c56b@huawei.com> Date: Fri, 25 Aug 2017 19:20:01 +0800 User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:45.0) Gecko/20100101 Thunderbird/45.7.1 MIME-Version: 1.0 In-Reply-To: <599ECE95.10205@huawei.com> Content-Type: text/plain; charset="windows-1252" Content-Transfer-Encoding: 7bit X-Originating-IP: [10.142.68.147] X-CFilter-Loop: Reflected X-Mirapoint-Virus-RAPID-Raw: score=unknown(0), refid=str=0001.0A090204.59A007F8.03C4, ss=1, re=0.000, recu=0.000, reip=0.000, cl=1, cld=1, fgs=0, ip=0.0.0.0, so=2014-11-16 11:51:01, dmn=2013-03-21 17:37:32 X-Mirapoint-Loop-Id: 72b1c22ab38c0022a5c2d9e53ed95867 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.4.x-2.6.x [generic] [fuzzy] X-Received-From: 45.249.212.190 Subject: Re: [Qemu-arm] [PATCH v11 2/6] ACPI: Add APEI GHES Table Generation support X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 25 Aug 2017 11:21:10 -0000 Hi Shannon, On 2017/8/24 21:03, Shannon Zhao wrote: > > > On 2017/8/18 22:23, Dongjiu Geng wrote: >> This implements APEI GHES Table by passing the error CPER info >> to the guest via a fw_cfg_blob. After a CPER info is recorded, an >> SEA(Synchronous External Abort)/SEI(SError Interrupt) exception >> will be injected into the guest OS. >> >> Below is the table layout, the max number of error soure is 11, >> which is classified by notification type. >> >> etc/acpi/tables etc/hardware_errors >> ==================== ========================================== >> + +--------------------------+ +------------------+ >> | | HEST | | address | +--------------+ >> | +--------------------------+ | registers | | Error Status | >> | | GHES0 | | +----------------+ | Data Block 0 | >> | +--------------------------+ +--------->| |status_address0 |------------->| +------------+ >> | | ................. | | | +----------------+ | | CPER | >> | | error_status_address-----+-+ +------->| |status_address1 |----------+ | | CPER | >> | | ................. | | | +----------------+ | | | .... | >> | | read_ack_register--------+-+ | | ............. | | | | CPER | >> | | read_ack_preserve | | | +------------------+ | | +-+------------+ >> | | read_ack_write | | | +----->| |status_address10|--------+ | | Error Status | >> + +--------------------------+ | | | | +----------------+ | | | Data Block 1 | >> | | GHES1 | +-+-+----->| | ack_value0 | | +-->| +------------+ >> + +--------------------------+ | | | +----------------+ | | | CPER | >> | | ................. | | | +--->| | ack_value1 | | | | CPER | >> | | error_status_address-----+---+ | | | +----------------+ | | | .... | >> | | ................. | | | | | ............. | | | | CPER | >> | | read_ack_register--------+-----+-+ | +----------------+ | +-+------------+ >> | | read_ack_preserve | | +->| | ack_value10 | | | |.......... | >> | | read_ack_write | | | | +----------------+ | | +------------+ >> + +--------------------------| | | | | Error Status | >> | | ............... | | | | | Data Block 10| >> + +--------------------------+ | | +---->| +------------+ >> | | GHES10 | | | | | CPER | >> + +--------------------------+ | | | | CPER | >> | | ................. | | | | | .... | >> | | error_status_address-----+-----+ | | | CPER | >> | | ................. | | +-+------------+ >> | | read_ack_register--------+---------+ >> | | read_ack_preserve | >> | | read_ack_write | >> + +--------------------------+ >> >> For GHESv2 error source, the OSPM must acknowledges the error via Read Ack register. >> so user space must check the ack value to avoid read-write race condition. >> >> Signed-off-by: Dongjiu Geng >> --- >> hw/acpi/aml-build.c | 2 + >> hw/acpi/hest_ghes.c | 345 ++++++++++++++++++++++++++++++++++++++++++++ >> hw/arm/virt-acpi-build.c | 6 + >> include/hw/acpi/aml-build.h | 1 + >> include/hw/acpi/hest_ghes.h | 47 ++++++ >> 5 files changed, 401 insertions(+) >> create mode 100644 hw/acpi/hest_ghes.c > Don't need to add the new file to hw/acpi/Makefile.objs? I modified the Makefile.objs in another patch. > >> create mode 100644 include/hw/acpi/hest_ghes.h >> >> diff --git a/hw/acpi/aml-build.c b/hw/acpi/aml-build.c >> index 36a6cc4..6849e5f 100644 >> --- a/hw/acpi/aml-build.c >> +++ b/hw/acpi/aml-build.c >> @@ -1561,6 +1561,7 @@ void acpi_build_tables_init(AcpiBuildTables *tables) >> tables->table_data = g_array_new(false, true /* clear */, 1); >> tables->tcpalog = g_array_new(false, true /* clear */, 1); >> tables->vmgenid = g_array_new(false, true /* clear */, 1); >> + tables->hardware_errors = g_array_new(false, true /* clear */, 1); >> tables->linker = bios_linker_loader_init(); >> } >> >> @@ -1571,6 +1572,7 @@ void acpi_build_tables_cleanup(AcpiBuildTables *tables, bool mfre) >> g_array_free(tables->table_data, true); >> g_array_free(tables->tcpalog, mfre); >> g_array_free(tables->vmgenid, mfre); >> + g_array_free(tables->hardware_errors, mfre); >> } >> >> /* Build rsdt table */ >> diff --git a/hw/acpi/hest_ghes.c b/hw/acpi/hest_ghes.c >> new file mode 100644 >> index 0000000..ff6b5ef >> --- /dev/null >> +++ b/hw/acpi/hest_ghes.c >> @@ -0,0 +1,345 @@ >> +/* >> + * APEI GHES table Generation >> + * >> + * Copyright (C) 2017 huawei. >> + * >> + * Author: Dongjiu Geng >> + * >> + * This work is licensed under the terms of the GNU GPL, version 2 or later. >> + * See the COPYING file in the top-level directory. >> + * >> + */ > Please unify this of this file and hest_ghes.h by refering to other files. Ok, thanks. > >> + >> +#include "qemu/osdep.h" >> +#include "qmp-commands.h" > unnecessary including I will remove it. > >> +#include "hw/acpi/acpi.h" >> +#include "hw/acpi/aml-build.h" >> +#include "hw/acpi/hest_ghes.h" >> +#include "hw/nvram/fw_cfg.h" >> +#include "sysemu/sysemu.h" >> +#include "qemu/error-report.h" >> + >> +/* The structure that stands for the layout >> + * GHES_ERRORS_FW_CFG_FILE fw_cfg blob >> + * >> + * etc/hardware_errors >> + * ========================================== >> + * +------------------+ >> + * | address | +--------------+ >> + * | registers | | Error Status | >> + * | +----------------+ | Data Block 0 | >> + * | |status_address0 |------------->| +------------+ >> + * | +----------------+ | | CPER | >> + * | |status_address1 |----------+ | | CPER | >> + * | +----------------+ | | | .... | >> + * | |............. | | | | CPER | >> + * | +----------------+ | | +------------+ >> + * | |status_address10|-----+ | | Error Status | >> + * | +----------------+ | | | Data Block 1 | >> + * | |ack_value0 | | +-->| +------------+ >> + * | +----------------+ | | | CPER | >> + * | |ack_value1 | | | | CPER | >> + * | +----------------+ | | | .... | >> + * | | ............. | | | | CPER | >> + * | +----------------+ | +-+------------+ >> + * | |ack_value10 | | | |.......... | >> + * | +----------------+ | | +------------+ >> + * | | Error Status | >> + * | | Data Block10 | >> + * +------->+------------+ >> + * | | CPER | >> + * | | CPER | >> + * | | .... | >> + * | | CPER | >> + * +-+------------+ >> + */ >> +struct hardware_errors_buffer { >> + /* Generic Error Status Block register */ >> + uint64_t gesb_address[GHES_ACPI_HEST_NOTIFY_RESERVED]; >> + uint64_t ack_value[GHES_ACPI_HEST_NOTIFY_RESERVED]; >> + char gesb[GHES_MAX_RAW_DATA_LENGTH][GHES_ACPI_HEST_NOTIFY_RESERVED]; >> +}; >> + >> +static int ghes_record_cper(uint64_t error_block_address, >> + uint64_t error_physical_addr) >> +{ >> + AcpiGenericErrorStatus block; >> + AcpiGenericErrorData *gdata; >> + UefiCperSecMemErr *mem_err; >> + uint64_t current_block_length; >> + unsigned char *buffer; >> + /* memory section */ >> + char mem_section_id_le[] = {0x14, 0x11, 0xBC, 0xA5, 0x64, 0x6F, 0xDE, >> + 0x4E, 0xB8, 0x63, 0x3E, 0x83, 0xED, 0x7C, >> + 0x83, 0xB1}; >> + >> + cpu_physical_memory_read(error_block_address, &block, >> + sizeof(AcpiGenericErrorStatus)); >> + >> + /* Get the current generic error status block length */ >> + current_block_length = sizeof(AcpiGenericErrorStatus) + >> + le32_to_cpu(block.data_length); >> + >> + /* If the Generic Error Status Block is NULL, update >> + * the block header >> + */ >> + if (!block.block_status) { >> + block.block_status = ACPI_GEBS_UNCORRECTABLE; >> + block.error_severity = ACPI_CPER_SEV_RECOVERABLE; >> + } >> + >> + block.data_length += cpu_to_le32(sizeof(AcpiGenericErrorData)); >> + block.data_length += cpu_to_le32(sizeof(UefiCperSecMemErr)); >> + >> + /* check whether it runs out of the preallocated memory */ >> + if ((le32_to_cpu(block.data_length) + sizeof(AcpiGenericErrorStatus)) > >> + GHES_MAX_RAW_DATA_LENGTH) { >> + error_report("Record CPER out of boundary!!!"); >> + return GHES_CPER_FAIL; >> + } >> + >> + /* Write back the Generic Error Status Block to guest memory */ >> + cpu_physical_memory_write(error_block_address, &block, >> + sizeof(AcpiGenericErrorStatus)); >> + >> + /* Fill in Generic Error Data Entry */ >> + buffer = g_malloc0(sizeof(AcpiGenericErrorData) + >> + sizeof(UefiCperSecMemErr)); >> + >> + >> + memset(buffer, 0, sizeof(AcpiGenericErrorData) + sizeof(UefiCperSecMemErr)); >> + gdata = (AcpiGenericErrorData *)buffer; >> + >> + /* Memory section */ >> + memcpy(&(gdata->section_type_le), &mem_section_id_le, >> + sizeof(mem_section_id_le)); >> + >> + /* error severity is recoverable */ >> + gdata->error_severity = ACPI_CPER_SEV_RECOVERABLE; >> + gdata->revision = 0x300; /* the revision number is 0x300 */ >> + gdata->error_data_length = cpu_to_le32(sizeof(UefiCperSecMemErr)); >> + >> + mem_err = (UefiCperSecMemErr *) (gdata + 1); >> + >> + /* User space only handle the memory section CPER */ >> + >> + /* Hard code to Multi-bit ECC error */ >> + mem_err->validation_bits |= cpu_to_le32(UEFI_CPER_MEM_VALID_ERROR_TYPE); >> + mem_err->error_type = cpu_to_le32(UEFI_CPER_MEM_ERROR_TYPE_MULTI_ECC); >> + >> + /* Record the physical address at which the memory error occurred */ >> + mem_err->validation_bits |= cpu_to_le32(UEFI_CPER_MEM_VALID_PA); >> + mem_err->physical_addr = cpu_to_le32(error_physical_addr); >> + >> + /* Write back the Generic Error Data Entry to guest memory */ >> + cpu_physical_memory_write(error_block_address + current_block_length, >> + buffer, sizeof(AcpiGenericErrorData) + sizeof(UefiCperSecMemErr)); >> + >> + g_free(buffer); >> + return GHES_CPER_OK; >> +} >> + >> +static void >> +build_address(GArray *table_data, BIOSLinker *linker, >> + uint32_t dst_patched_offset, uint32_t src_offset, >> + uint8_t address_space_id , uint8_t register_bit_width, >> + uint8_t register_bit_offset, uint8_t access_size) >> +{ >> + uint32_t address_size = sizeof(struct AcpiGenericAddress) - >> + offsetof(struct AcpiGenericAddress, address); >> + >> + /* Address space */ >> + build_append_int_noprefix(table_data, address_space_id, 1); >> + /* register bit width */ >> + build_append_int_noprefix(table_data, register_bit_width, 1); >> + /* register bit offset */ >> + build_append_int_noprefix(table_data, register_bit_offset, 1); >> + /* access size */ >> + build_append_int_noprefix(table_data, access_size, 1); >> + acpi_data_push(table_data, address_size); >> + >> + /* Patch address of ERRORS fw_cfg blob into the TABLE fw_cfg blob so OSPM >> + * can retrieve and read it. the address size is 64 bits. >> + */ >> + bios_linker_loader_add_pointer(linker, >> + ACPI_BUILD_TABLE_FILE, dst_patched_offset, sizeof(uint64_t), >> + GHES_ERRORS_FW_CFG_FILE, src_offset); >> +} >> + >> +void ghes_build_acpi(GArray *table_data, GArray *hardware_error, >> + BIOSLinker *linker) >> +{ >> + uint32_t ghes_start = table_data->len; >> + uint32_t address_size, error_status_address_offset; >> + uint32_t read_ack_register_offset, i; >> + >> + address_size = sizeof(struct AcpiGenericAddress) - >> + offsetof(struct AcpiGenericAddress, address); >> + >> + error_status_address_offset = ghes_start + >> + sizeof(AcpiHardwareErrorSourceTable) + >> + offsetof(AcpiGenericHardwareErrorSourceV2, error_status_address) + >> + offsetof(struct AcpiGenericAddress, address); >> + >> + read_ack_register_offset = ghes_start + >> + sizeof(AcpiHardwareErrorSourceTable) + >> + offsetof(AcpiGenericHardwareErrorSourceV2, read_ack_register) + >> + offsetof(struct AcpiGenericAddress, address); >> + >> + acpi_data_push(hardware_error, >> + offsetof(struct hardware_errors_buffer, ack_value)); >> + for (i = 0; i < GHES_ACPI_HEST_NOTIFY_RESERVED; i++) >> + /* Initialize read ack register */ >> + build_append_int_noprefix((void *)hardware_error, 1, 8); >> + >> + /* Reserved the total size for ERRORS fw_cfg blob >> + */ >> + acpi_data_push(hardware_error, sizeof(struct hardware_errors_buffer)); >> + >> + /* Allocate guest memory for the Data fw_cfg blob */ >> + bios_linker_loader_alloc(linker, GHES_ERRORS_FW_CFG_FILE, hardware_error, >> + 1, false); >> + /* Reserve table header size */ >> + acpi_data_push(table_data, sizeof(AcpiTableHeader)); >> + >> + build_append_int_noprefix(table_data, GHES_ACPI_HEST_NOTIFY_RESERVED, 4); >> + >> + for (i = 0; i < GHES_ACPI_HEST_NOTIFY_RESERVED; i++) { >> + build_append_int_noprefix(table_data, >> + ACPI_HEST_SOURCE_GENERIC_ERROR_V2, 2); /* type */ >> + /* source id */ >> + build_append_int_noprefix(table_data, cpu_to_le16(i), 2); >> + /* related source id */ >> + build_append_int_noprefix(table_data, 0xffff, 2); >> + build_append_int_noprefix(table_data, 0, 1); /* flags */ >> + >> + /* Currently only enable SEA notification type to avoid the kernel >> + * warning, reserve the space for other notification error source >> + */ >> + if (i == ACPI_HEST_NOTIFY_SEA) { >> + build_append_int_noprefix(table_data, 1, 1); /* enabled */ >> + } else { >> + build_append_int_noprefix(table_data, 0, 1); /* enabled */ >> + } >> + >> + /* The number of error status block per generic hardware error source */ >> + build_append_int_noprefix(table_data, 1, 4); >> + /* Max sections per record */ >> + build_append_int_noprefix(table_data, 1, 4); >> + /* Max raw data length */ >> + build_append_int_noprefix(table_data, GHES_MAX_RAW_DATA_LENGTH, 4); >> + >> + /* Build error status address*/ >> + build_address(table_data, linker, error_status_address_offset + i * >> + sizeof(AcpiGenericHardwareErrorSourceV2), i * address_size, >> + AML_SYSTEM_MEMORY, 0x40, 0, 4 /* QWord access */); >> + >> + /* Hardware error notification structure */ >> + build_append_int_noprefix(table_data, i, 1); /* type */ >> + /* length */ >> + build_append_int_noprefix(table_data, sizeof(AcpiHestNotify), 1); >> + build_append_int_noprefix(table_data, 0, 26); >> + >> + /* Error Status Block Length */ >> + build_append_int_noprefix(table_data, >> + cpu_to_le32(GHES_MAX_RAW_DATA_LENGTH), 4); >> + >> + /* Build read ack register */ >> + build_address(table_data, linker, read_ack_register_offset + i * >> + sizeof(AcpiGenericHardwareErrorSourceV2), >> + offsetof(struct hardware_errors_buffer, ack_value) + >> + i * address_size, AML_SYSTEM_MEMORY, 0x40, 0, >> + 4 /* QWord access */); >> + >> + /* Read ack preserve */ >> + build_append_int_noprefix(table_data, cpu_to_le64(0xfffffffe), 8); >> + >> + /* Read ack write */ >> + build_append_int_noprefix(table_data, cpu_to_le64(0x1), 8); >> + } >> + >> + for (i = 0; i < GHES_ACPI_HEST_NOTIFY_RESERVED; i++) >> + /* Patch address of generic error status block into >> + * the address register so OSPM can retrieve and read it. >> + */ >> + bios_linker_loader_add_pointer(linker, >> + GHES_ERRORS_FW_CFG_FILE, address_size * i, address_size, >> + GHES_ERRORS_FW_CFG_FILE, >> + offsetof(struct hardware_errors_buffer, gesb) + >> + i * GHES_MAX_RAW_DATA_LENGTH); >> + >> + /* Patch address of ERRORS fw_cfg blob into the ADDR fw_cfg blob >> + * so QEMU can write the ERRORS there. The address is expected to be >> + * < 4GB, but write 64 bits anyway. >> + */ >> + bios_linker_loader_write_pointer(linker, GHES_DATA_ADDR_FW_CFG_FILE, >> + 0, address_size, GHES_ERRORS_FW_CFG_FILE, >> + offsetof(struct hardware_errors_buffer, gesb)); >> + >> + build_header(linker, table_data, >> + (void *)(table_data->data + ghes_start), "HEST", >> + table_data->len - ghes_start, 1, NULL, "GHES"); >> +} >> + >> +static GhesState ges; >> +void ghes_add_fw_cfg(FWCfgState *s, GArray *hardware_error) >> +{ >> + >> + size_t request_block_size = sizeof(uint64_t) + GHES_MAX_RAW_DATA_LENGTH; >> + size_t size = GHES_ACPI_HEST_NOTIFY_RESERVED * request_block_size; >> + >> + /* Create a read-only fw_cfg file for GHES */ >> + fw_cfg_add_file(s, GHES_ERRORS_FW_CFG_FILE, hardware_error->data, >> + size); >> + /* Create a read-write fw_cfg file for Address */ >> + fw_cfg_add_file_callback(s, GHES_DATA_ADDR_FW_CFG_FILE, NULL, NULL, >> + &ges.ghes_addr_le, sizeof(ges.ghes_addr_le), false); >> +} >> + >> +bool ghes_update_guest(uint32_t notify, uint64_t physical_address) >> +{ >> + uint64_t error_block_addr; >> + uint64_t ack_value_addr, ack_value = 0; >> + int loop = 0, ack_value_size; >> + bool ret = GHES_CPER_FAIL; >> + >> + ack_value_size = (offsetof(struct hardware_errors_buffer, gesb) - >> + offsetof(struct hardware_errors_buffer, ack_value)) / >> + GHES_ACPI_HEST_NOTIFY_RESERVED; >> + >> + if (physical_address && notify < GHES_ACPI_HEST_NOTIFY_RESERVED) { >> + error_block_addr = ges.ghes_addr_le + notify * GHES_MAX_RAW_DATA_LENGTH; >> + error_block_addr = le32_to_cpu(error_block_addr); >> + >> + ack_value_addr = ges.ghes_addr_le - >> + (GHES_ACPI_HEST_NOTIFY_RESERVED - notify) * ack_value_size; >> +retry: >> + cpu_physical_memory_read(ack_value_addr, &ack_value, ack_value_size); >> + if (!ack_value) { >> + if (loop < 3) { >> + usleep(100 * 1000); >> + loop++; >> + goto retry; >> + } else { >> + error_report("Last time OSPM does not acknowledge the error," >> + " record CPER failed this time, set the ack value to" >> + " avoid blocking next time CPER record! exit"); >> + ack_value = 1; >> + cpu_physical_memory_write(ack_value_addr, >> + &ack_value, ack_value_size); >> + return ret; >> + } >> + } else { >> + /* A zero value in ghes_addr means that BIOS has not yet written >> + * the address >> + */ >> + if (error_block_addr) { >> + ack_value = 0; >> + cpu_physical_memory_write(ack_value_addr, >> + &ack_value, ack_value_size); >> + ret = ghes_record_cper(error_block_addr, physical_address); >> + } >> + } >> + } >> + return ret; >> +} >> diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c >> index 3d78ff6..def1ec1 100644 >> --- a/hw/arm/virt-acpi-build.c >> +++ b/hw/arm/virt-acpi-build.c >> @@ -45,6 +45,7 @@ >> #include "hw/arm/virt.h" >> #include "sysemu/numa.h" >> #include "kvm_arm.h" >> +#include "hw/acpi/hest_ghes.h" >> >> #define ARM_SPI_BASE 32 >> #define ACPI_POWER_BUTTON_DEVICE "PWRB" >> @@ -771,6 +772,9 @@ void virt_acpi_build(VirtMachineState *vms, AcpiBuildTables *tables) >> acpi_add_table(table_offsets, tables_blob); >> build_spcr(tables_blob, tables->linker, vms); >> >> + acpi_add_table(table_offsets, tables_blob); >> + ghes_build_acpi(tables_blob, tables->hardware_errors, tables->linker); >> + > So we add this table unconditionally. Is there any bad impact if QEMU > runs on old kvm? Does it need to check whether KVM supports RAS? this table is added before guest OS boot. so can not use KVM to check it. if the old kvm does not support RAS, it does not have bad impact. only waste table memory. May be we can make it as device? if this device is enabled in the qemu boot parameters, then we will add this table? > >> if (nb_numa_nodes > 0) { >> acpi_add_table(table_offsets, tables_blob); >> build_srat(tables_blob, tables->linker, vms); >> @@ -887,6 +891,8 @@ void virt_acpi_setup(VirtMachineState *vms) >> fw_cfg_add_file(vms->fw_cfg, ACPI_BUILD_TPMLOG_FILE, tables.tcpalog->data, >> acpi_data_len(tables.tcpalog)); >> >> + ghes_add_fw_cfg(vms->fw_cfg, tables.hardware_errors); >> + >> build_state->rsdp_mr = acpi_add_rom_blob(build_state, tables.rsdp, >> ACPI_BUILD_RSDP_FILE, 0); >> >> diff --git a/include/hw/acpi/aml-build.h b/include/hw/acpi/aml-build.h >> index 88d0738..7f7b55c 100644 >> --- a/include/hw/acpi/aml-build.h >> +++ b/include/hw/acpi/aml-build.h >> @@ -211,6 +211,7 @@ struct AcpiBuildTables { >> GArray *rsdp; >> GArray *tcpalog; >> GArray *vmgenid; >> + GArray *hardware_errors; >> BIOSLinker *linker; >> } AcpiBuildTables; >> >> diff --git a/include/hw/acpi/hest_ghes.h b/include/hw/acpi/hest_ghes.h >> new file mode 100644 >> index 0000000..0772756 >> --- /dev/null >> +++ b/include/hw/acpi/hest_ghes.h >> @@ -0,0 +1,47 @@ >> +/* >> + * This program is free software; you can redistribute it and/or modify >> + * it under the terms of the GNU General Public License as published by >> + * the Free Software Foundation; either version 2 of the License, or >> + * (at your option) any later version. >> + >> + * This program is distributed in the hope that it will be useful, >> + * but WITHOUT ANY WARRANTY; without even the implied warranty of >> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the >> + * GNU General Public License for more details. >> + * >> + * Authors: >> + * Dongjiu Geng >> + * >> + * You should have received a copy of the GNU General Public License along >> + * with this program; if not, see . >> + */ >> + >> +#ifndef ACPI_GHES_H >> +#define ACPI_GHES_H >> + >> +#include "hw/acpi/bios-linker-loader.h" >> + >> +#define GHES_ERRORS_FW_CFG_FILE "etc/hardware_errors" >> +#define GHES_DATA_ADDR_FW_CFG_FILE "etc/hardware_errors_addr" >> + >> +#define GHES_GAS_ADDRESS_OFFSET 4 >> +#define GHES_ERROR_STATUS_ADDRESS_OFFSET 20 >> +#define GHES_NOTIFICATION_STRUCTURE 32 >> + >> +#define GHES_CPER_OK 1 >> +#define GHES_CPER_FAIL 0 >> + >> +#define GHES_ACPI_HEST_NOTIFY_RESERVED 11 >> +/* The max size in Bytes for one error block */ >> +#define GHES_MAX_RAW_DATA_LENGTH 0x1000 >> + >> + >> +typedef struct GhesState { >> + uint64_t ghes_addr_le; >> +} GhesState; >> + >> +void ghes_build_acpi(GArray *table_data, GArray *hardware_error, >> + BIOSLinker *linker); >> +void ghes_add_fw_cfg(FWCfgState *s, GArray *hardware_errors); >> +bool ghes_update_guest(uint32_t notify, uint64_t error_physical_addr); >> +#endif >> > From MAILER-DAEMON Fri Aug 25 07:21:38 2017 Received: from list by lists.gnu.org with archive (Exim 4.71) id 1dlCgE-0000Gk-0f for mharc-qemu-arm@gnu.org; Fri, 25 Aug 2017 07:21:38 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:56027) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dlCgA-0000FE-9H for qemu-arm@nongnu.org; Fri, 25 Aug 2017 07:21:37 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dlCg9-0007BE-Ch for qemu-arm@nongnu.org; Fri, 25 Aug 2017 07:21:34 -0400 Received: from szxga05-in.huawei.com ([45.249.212.191]:2244) by eggs.gnu.org with esmtps (TLS1.0:RSA_ARCFOUR_SHA1:16) (Exim 4.71) (envelope-from ) id 1dlCg8-000772-PU; Fri, 25 Aug 2017 07:21:33 -0400 Received: from 172.30.72.60 (EHLO DGGEMS405-HUB.china.huawei.com) ([172.30.72.60]) by dggrg05-dlp.huawei.com (MOS 4.4.6-GA FastPath queued) with ESMTP id DFY15883; Fri, 25 Aug 2017 19:21:08 +0800 (CST) Received: from [127.0.0.1] (10.142.68.147) by DGGEMS405-HUB.china.huawei.com (10.3.19.205) with Microsoft SMTP Server id 14.3.301.0; Fri, 25 Aug 2017 19:21:02 +0800 To: Shannon Zhao , , , , , , , , , , , , , , , , , , , , , , , , , , , , , References: <1503066227-18251-1-git-send-email-gengdongjiu@huawei.com> <1503066227-18251-4-git-send-email-gengdongjiu@huawei.com> <599ECEF3.80001@huawei.com> CC: , , , From: gengdongjiu Message-ID: <6afc4dfa-5ad1-8df1-7dce-4704a796d8aa@huawei.com> Date: Fri, 25 Aug 2017 19:20:57 +0800 User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:45.0) Gecko/20100101 Thunderbird/45.7.1 MIME-Version: 1.0 In-Reply-To: <599ECEF3.80001@huawei.com> Content-Type: text/plain; charset="windows-1252" Content-Transfer-Encoding: 7bit X-Originating-IP: [10.142.68.147] X-CFilter-Loop: Reflected X-Mirapoint-Virus-RAPID-Raw: score=unknown(0), refid=str=0001.0A090203.59A00825.0081, ss=1, re=0.000, recu=0.000, reip=0.000, cl=1, cld=1, fgs=0, ip=0.0.0.0, so=2014-11-16 11:51:01, dmn=2013-03-21 17:37:32 X-Mirapoint-Loop-Id: 7e0f88feab02fe4188c23b25bdb7134b X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.4.x-2.6.x [generic] [fuzzy] X-Received-From: 45.249.212.191 Subject: Re: [Qemu-arm] [PATCH v11 3/6] ACPI: build and enable APEI GHES in the Makefile and configuration X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 25 Aug 2017 11:21:37 -0000 On 2017/8/24 21:04, Shannon Zhao wrote: > > > On 2017/8/18 22:23, Dongjiu Geng wrote: >> Add CONFIG_ACPI_APEI configuration in the Makefile and >> enable it in the arm-softmmu.mak >> >> Signed-off-by: Dongjiu Geng >> --- >> default-configs/arm-softmmu.mak | 1 + >> hw/acpi/Makefile.objs | 1 + >> 2 files changed, 2 insertions(+) >> >> diff --git a/default-configs/arm-softmmu.mak b/default-configs/arm-softmmu.mak >> index bbdd3c1..c362113 100644 >> --- a/default-configs/arm-softmmu.mak >> +++ b/default-configs/arm-softmmu.mak >> @@ -129,3 +129,4 @@ CONFIG_ACPI=y >> CONFIG_SMBIOS=y >> CONFIG_ASPEED_SOC=y >> CONFIG_GPIO_KEY=y >> +CONFIG_ACPI_APEI=y >> diff --git a/hw/acpi/Makefile.objs b/hw/acpi/Makefile.objs >> index 11c35bc..bafb148 100644 >> --- a/hw/acpi/Makefile.objs >> +++ b/hw/acpi/Makefile.objs >> @@ -6,6 +6,7 @@ common-obj-$(CONFIG_ACPI_MEMORY_HOTPLUG) += memory_hotplug.o >> common-obj-$(CONFIG_ACPI_CPU_HOTPLUG) += cpu.o >> common-obj-$(CONFIG_ACPI_NVDIMM) += nvdimm.o >> common-obj-$(CONFIG_ACPI_VMGENID) += vmgenid.o >> +common-obj-$(CONFIG_ACPI_APEI) += hest_ghes.o >> common-obj-$(call lnot,$(CONFIG_ACPI_X86)) += acpi-stub.o >> >> common-obj-y += acpi_interface.o >> > Fold this patch into previous one. Ok, thanks > > Thanks, > From MAILER-DAEMON Fri Aug 25 13:13:31 2017 Received: from list by lists.gnu.org with archive (Exim 4.71) id 1dlIAl-00010C-C9 for mharc-qemu-arm@gnu.org; Fri, 25 Aug 2017 13:13:31 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:37336) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dlIAh-0000zx-PH for qemu-arm@nongnu.org; Fri, 25 Aug 2017 13:13:30 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dlIAe-00056b-ES for qemu-arm@nongnu.org; Fri, 25 Aug 2017 13:13:27 -0400 Received: from mx1.redhat.com ([209.132.183.28]:49768) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1dlIAe-00055J-1e; Fri, 25 Aug 2017 13:13:24 -0400 Received: from smtp.corp.redhat.com (int-mx04.intmail.prod.int.phx2.redhat.com [10.5.11.14]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id EAB3780F79; Fri, 25 Aug 2017 17:13:22 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mx1.redhat.com EAB3780F79 Authentication-Results: ext-mx03.extmail.prod.ext.phx2.redhat.com; dmarc=none (p=none dis=none) header.from=redhat.com Authentication-Results: ext-mx03.extmail.prod.ext.phx2.redhat.com; spf=fail smtp.mailfrom=mst@redhat.com Received: from redhat.com (ovpn-121-154.rdu2.redhat.com [10.10.121.154]) by smtp.corp.redhat.com (Postfix) with SMTP id 6980C61B60; Fri, 25 Aug 2017 17:13:10 +0000 (UTC) Date: Fri, 25 Aug 2017 20:13:09 +0300 From: "Michael S. Tsirkin" To: Auger Eric Cc: Linu Cherian , peter.maydell@linaro.org, drjones@redhat.com, tcain@qti.qualcomm.com, Radha.Chintakuntla@cavium.com, Sunil.Goutham@cavium.com, mohun106@gmail.com, jean-philippe.brucker@arm.com, tn@semihalf.com, bharat.bhushan@nxp.com, will.deacon@arm.com, qemu-devel@nongnu.org, peterx@redhat.com, alex.williamson@redhat.com, qemu-arm@nongnu.org, christoffer.dall@linaro.org, linu.cherian@cavium.com, robin.murphy@arm.com, prem.mallappa@gmail.com, eric.auger.pro@gmail.com Message-ID: <20170825201005-mutt-send-email-mst@kernel.org> References: <1502461354-11327-1-git-send-email-eric.auger@redhat.com> <1502461354-11327-9-git-send-email-eric.auger@redhat.com> <20170823042453.GA4682@virtx40> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: X-Scanned-By: MIMEDefang 2.79 on 10.5.11.14 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.27]); Fri, 25 Aug 2017 17:13:23 +0000 (UTC) X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.132.183.28 Subject: Re: [Qemu-arm] [Qemu-devel] [RFC v6 8/9] hw/arm/smmuv3: VFIO integration X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 25 Aug 2017 17:13:30 -0000 On Wed, Aug 23, 2017 at 08:39:18AM +0200, Auger Eric wrote: > Hi Linu, > > On 23/08/2017 06:24, Linu Cherian wrote: > > Hi Eric, > > > > > > On Fri Aug 11, 2017 at 04:22:33PM +0200, Eric Auger wrote: > >> This patch allows doing PCIe passthrough with a guest exposed > >> with a vSMMUv3. It implements the replay and notify_flag_changed > >> iommu ops. Also on TLB and data structure invalidation commands, > >> we replay the mappings so that the physical IOMMU implements > >> updated stage 1 settings (Guest IOVA -> Guest PA) + stage 2 settings. > >> > >> This works only if the guest smmuv3 driver implements the > >> "tlbi-on-map" option. > >> > >> Signed-off-by: Eric Auger > > > > Tried out launching a guest with Qemu option "-machine virt-2.10,smmu" > > and a 1G Ethernet controller as vfio-pci device. It works fine for me. > > Hum sorry, I forgot to update the cover letter. You need to use -machine > virt-2.11,smmu for the instantiation as the 2.10 machine was released as > part of 2.10 and those changes only apply on 2.11 mach virt introduced > in this series. Please apologize for the pain. > > I am going to release a new version this week fixing my last DPDK bug > (at least I am aware of ). In this new version, the instantiation method > will change to -device smmuv3 which is closer to what is done on Intel. > > By the way I will also take time to provide some more info about the > VFIO integration as it is implemented in this series although this > latter may evolve due to NAK of kernel FW quirk. Yes I think changing compat string to avoid pretending this is smmuv3 was a hard requirement. So you might need to do -device qemu-smmuv3 if you want VFIO support with this PV quirk. For now, how about a subset of the functionality with VFIO disabled? People can use it with virtio for now. > Thank you for testing! > > Best Regards > > Eric > > > > Qemu source: https://github.com/eauger/qemu.git Branch: v2.10.0-rc2-SMMU-v6 > > > > But had to make this change, > > > > --- a/hw/arm/virt.c > > +++ b/hw/arm/virt.c > > @@ -1806,7 +1806,7 @@ static void virt_machine_2_10_options(MachineClass *mc) > > virt_machine_2_11_options(mc); > > SET_MACHINE_COMPAT(mc, VIRT_COMPAT_2_10); > > > > - vmc->no_smmu = true; > > + vmc->no_smmu = false; > > } > > DEFINE_VIRT_MACHINE(2, 10) > > > > so that qemu doesnt complain about "Property .smmu not found" > > > > Will let you know if i have updates on further testing. > > > > Thanks. > > > >> > >> --- > >> > >> v5 -> v6: > >> - use IOMMUMemoryRegion > >> - handle implementation defined SMMU_CMD_TLBI_NH_VA_AM cmd > >> (goes along with TLBI_ON_MAP FW quirk) > >> - replay systematically unmap the whole range first > >> - smmuv3_map_hook does not unmap anymore and the unmap is done > >> before the replay > >> - add and use smmuv3_context_device_invalidate instead of > >> blindly replaying everything > >> --- > >> hw/arm/smmuv3-internal.h | 1 + > >> hw/arm/smmuv3.c | 265 ++++++++++++++++++++++++++++++++++++++++++++++- > >> hw/arm/trace-events | 14 +++ > >> 3 files changed, 277 insertions(+), 3 deletions(-) > >> > >> diff --git a/hw/arm/smmuv3-internal.h b/hw/arm/smmuv3-internal.h > >> index e255df1..ac4628f 100644 > >> --- a/hw/arm/smmuv3-internal.h > >> +++ b/hw/arm/smmuv3-internal.h > >> @@ -344,6 +344,7 @@ enum { > >> SMMU_CMD_RESUME = 0x44, > >> SMMU_CMD_STALL_TERM, > >> SMMU_CMD_SYNC, /* 0x46 */ > >> + SMMU_CMD_TLBI_NH_VA_AM = 0x8F, /* VIOMMU Impl Defined */ > >> }; > >> > >> static const char *cmd_stringify[] = { > >> diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c > >> index e195a0e..89fb116 100644 > >> --- a/hw/arm/smmuv3.c > >> +++ b/hw/arm/smmuv3.c > >> @@ -25,6 +25,7 @@ > >> #include "exec/address-spaces.h" > >> #include "trace.h" > >> #include "qemu/error-report.h" > >> +#include "exec/target_page.h" > >> > >> #include "hw/arm/smmuv3.h" > >> #include "smmuv3-internal.h" > >> @@ -143,6 +144,71 @@ static MemTxResult smmu_read_cmdq(SMMUV3State *s, Cmd *cmd) > >> return ret; > >> } > >> > >> +static void smmuv3_replay_all(SMMUState *s) > >> +{ > >> + SMMUNotifierNode *node; > >> + > >> + QLIST_FOREACH(node, &s->notifiers_list, next) { > >> + trace_smmuv3_replay_all(node->sdev->iommu.parent_obj.name); > >> + memory_region_iommu_replay_all(&node->sdev->iommu); > >> + } > >> +} > >> + > >> +/* Replay the mappings for a given streamid */ > >> +static void smmuv3_context_device_invalidate(SMMUState *s, uint16_t sid) > >> +{ > >> + uint8_t bus_n, devfn; > >> + SMMUPciBus *smmu_bus; > >> + SMMUDevice *smmu; > >> + > >> + trace_smmuv3_context_device_invalidate(sid); > >> + bus_n = PCI_BUS_NUM(sid); > >> + smmu_bus = smmu_find_as_from_bus_num(s, bus_n); > >> + if (smmu_bus) { > >> + devfn = PCI_FUNC(sid); > >> + smmu = smmu_bus->pbdev[devfn]; > >> + if (smmu) { > >> + memory_region_iommu_replay_all(&smmu->iommu); > >> + } > >> + } > >> +} > >> + > >> +static void smmuv3_replay_single(IOMMUMemoryRegion *mr, IOMMUNotifier *n, > >> + uint64_t iova); > >> + > >> +static void smmuv3_replay_range(IOMMUMemoryRegion *mr, IOMMUNotifier *n, > >> + uint64_t iova, size_t nb_pages); > >> + > >> +static void smmuv3_notify_single(SMMUState *s, uint64_t iova) > >> +{ > >> + SMMUNotifierNode *node; > >> + > >> + QLIST_FOREACH(node, &s->notifiers_list, next) { > >> + IOMMUMemoryRegion *mr = &node->sdev->iommu; > >> + IOMMUNotifier *n; > >> + > >> + trace_smmuv3_notify_all(node->sdev->iommu.parent_obj.name, iova); > >> + IOMMU_NOTIFIER_FOREACH(n, mr) { > >> + smmuv3_replay_single(mr, n, iova); > >> + } > >> + } > >> +} > >> + > >> +static void smmuv3_notify_range(SMMUState *s, uint64_t iova, size_t size) > >> +{ > >> + SMMUNotifierNode *node; > >> + > >> + QLIST_FOREACH(node, &s->notifiers_list, next) { > >> + IOMMUMemoryRegion *mr = &node->sdev->iommu; > >> + IOMMUNotifier *n; > >> + > >> + trace_smmuv3_notify_all(node->sdev->iommu.parent_obj.name, iova); > >> + IOMMU_NOTIFIER_FOREACH(n, mr) { > >> + smmuv3_replay_range(mr, n, iova, size); > >> + } > >> + } > >> +} > >> + > >> static int smmu_cmdq_consume(SMMUV3State *s) > >> { > >> uint32_t error = SMMU_CMD_ERR_NONE; > >> @@ -178,28 +244,38 @@ static int smmu_cmdq_consume(SMMUV3State *s) > >> break; > >> case SMMU_CMD_PREFETCH_CONFIG: > >> case SMMU_CMD_PREFETCH_ADDR: > >> + break; > >> case SMMU_CMD_CFGI_STE: > >> { > >> uint32_t streamid = cmd.word[1]; > >> > >> trace_smmuv3_cmdq_cfgi_ste(streamid); > >> - break; > >> + smmuv3_context_device_invalidate(&s->smmu_state, streamid); > >> + break; > >> } > >> case SMMU_CMD_CFGI_STE_RANGE: /* same as SMMU_CMD_CFGI_ALL */ > >> { > >> - uint32_t start = cmd.word[1], range, end; > >> + uint32_t start = cmd.word[1], range, end, i; > >> > >> range = extract32(cmd.word[2], 0, 5); > >> end = start + (1 << (range + 1)) - 1; > >> trace_smmuv3_cmdq_cfgi_ste_range(start, end); > >> + for (i = start; i <= end; i++) { > >> + smmuv3_context_device_invalidate(&s->smmu_state, i); > >> + } > >> break; > >> } > >> case SMMU_CMD_CFGI_CD: > >> case SMMU_CMD_CFGI_CD_ALL: > >> + { > >> + uint32_t streamid = cmd.word[1]; > >> + > >> + smmuv3_context_device_invalidate(&s->smmu_state, streamid); > >> break; > >> + } > >> case SMMU_CMD_TLBI_NH_ALL: > >> case SMMU_CMD_TLBI_NH_ASID: > >> - printf("%s TLBI* replay\n", __func__); > >> + smmuv3_replay_all(&s->smmu_state); > >> break; > >> case SMMU_CMD_TLBI_NH_VA: > >> { > >> @@ -210,6 +286,20 @@ static int smmu_cmdq_consume(SMMUV3State *s) > >> uint64_t addr = high << 32 | (low << 12); > >> > >> trace_smmuv3_cmdq_tlbi_nh_va(asid, vmid, addr); > >> + smmuv3_notify_single(&s->smmu_state, addr); > >> + break; > >> + } > >> + case SMMU_CMD_TLBI_NH_VA_AM: > >> + { > >> + int asid = extract32(cmd.word[1], 16, 16); > >> + int am = extract32(cmd.word[1], 0, 16); > >> + uint64_t low = extract32(cmd.word[2], 12, 20); > >> + uint64_t high = cmd.word[3]; > >> + uint64_t addr = high << 32 | (low << 12); > >> + size_t size = am << 12; > >> + > >> + trace_smmuv3_cmdq_tlbi_nh_va_am(asid, am, addr, size); > >> + smmuv3_notify_range(&s->smmu_state, addr, size); > >> break; > >> } > >> case SMMU_CMD_TLBI_NH_VAA: > >> @@ -222,6 +312,7 @@ static int smmu_cmdq_consume(SMMUV3State *s) > >> case SMMU_CMD_TLBI_S12_VMALL: > >> case SMMU_CMD_TLBI_S2_IPA: > >> case SMMU_CMD_TLBI_NSNH_ALL: > >> + smmuv3_replay_all(&s->smmu_state); > >> break; > >> case SMMU_CMD_ATC_INV: > >> case SMMU_CMD_PRI_RESP: > >> @@ -804,6 +895,172 @@ out: > >> return entry; > >> } > >> > >> +static int smmuv3_replay_hook(IOMMUTLBEntry *entry, void *private) > >> +{ > >> + trace_smmuv3_replay_hook(entry->iova, entry->translated_addr, > >> + entry->addr_mask, entry->perm); > >> + memory_region_notify_one((IOMMUNotifier *)private, entry); > >> + return 0; > >> +} > >> + > >> +static int smmuv3_map_hook(IOMMUTLBEntry *entry, void *private) > >> +{ > >> + trace_smmuv3_map_hook(entry->iova, entry->translated_addr, > >> + entry->addr_mask, entry->perm); > >> + memory_region_notify_one((IOMMUNotifier *)private, entry); > >> + return 0; > >> +} > >> + > >> +/* Unmap the whole range in the notifier's scope. */ > >> +static void smmuv3_unmap_notifier(SMMUDevice *sdev, IOMMUNotifier *n) > >> +{ > >> + IOMMUTLBEntry entry; > >> + hwaddr size; > >> + hwaddr start = n->start; > >> + hwaddr end = n->end; > >> + > >> + size = end - start + 1; > >> + > >> + entry.target_as = &address_space_memory; > >> + /* Adjust iova for the size */ > >> + entry.iova = n->start & ~(size - 1); > >> + /* This field is meaningless for unmap */ > >> + entry.translated_addr = 0; > >> + entry.perm = IOMMU_NONE; > >> + entry.addr_mask = size - 1; > >> + > >> + /* TODO: check start/end/size/mask */ > >> + > >> + trace_smmuv3_unmap_notifier(pci_bus_num(sdev->bus), > >> + PCI_SLOT(sdev->devfn), > >> + PCI_FUNC(sdev->devfn), > >> + entry.iova, size); > >> + > >> + memory_region_notify_one(n, &entry); > >> +} > >> + > >> +static void smmuv3_replay(IOMMUMemoryRegion *mr, IOMMUNotifier *n) > >> +{ > >> + SMMUDevice *sdev = container_of(mr, SMMUDevice, iommu); > >> + SMMUV3State *s = sdev->smmu; > >> + SMMUBaseClass *sbc = SMMU_DEVICE_GET_CLASS(s); > >> + SMMUTransCfg cfg = {}; > >> + int ret; > >> + > >> + smmuv3_unmap_notifier(sdev, n); > >> + > >> + ret = smmuv3_decode_config(mr, &cfg); > >> + if (ret) { > >> + error_report("%s error decoding the configuration for iommu mr=%s", > >> + __func__, mr->parent_obj.name); > >> + } > >> + > >> + if (cfg.disabled || cfg.bypassed) { > >> + return; > >> + } > >> + /* is the smmu enabled */ > >> + sbc->page_walk_64(&cfg, 0, (1ULL << (64 - cfg.tsz)) - 1, false, > >> + smmuv3_replay_hook, n); > >> +} > >> +static void smmuv3_replay_range(IOMMUMemoryRegion *mr, IOMMUNotifier *n, > >> + uint64_t iova, size_t size) > >> +{ > >> + SMMUDevice *sdev = container_of(mr, SMMUDevice, iommu); > >> + SMMUV3State *s = sdev->smmu; > >> + SMMUBaseClass *sbc = SMMU_DEVICE_GET_CLASS(s); > >> + SMMUTransCfg cfg = {}; > >> + IOMMUTLBEntry entry; > >> + int ret; > >> + > >> + trace_smmuv3_replay_range(mr->parent_obj.name, iova, size, n); > >> + ret = smmuv3_decode_config(mr, &cfg); > >> + if (ret) { > >> + error_report("%s error decoding the configuration for iommu mr=%s", > >> + __func__, mr->parent_obj.name); > >> + } > >> + > >> + if (cfg.disabled || cfg.bypassed) { > >> + return; > >> + } > >> + > >> + /* first unmap */ > >> + entry.target_as = &address_space_memory; > >> + entry.iova = iova & ~(size - 1); > >> + entry.addr_mask = size - 1; > >> + entry.perm = IOMMU_NONE; > >> + > >> + memory_region_notify_one(n, &entry); > >> + > >> + /* then figure out if a new mapping needs to be applied */ > >> + sbc->page_walk_64(&cfg, iova, iova + entry.addr_mask , false, > >> + smmuv3_map_hook, n); > >> +} > >> + > >> +static void smmuv3_replay_single(IOMMUMemoryRegion *mr, IOMMUNotifier *n, > >> + uint64_t iova) > >> +{ > >> + SMMUDevice *sdev = container_of(mr, SMMUDevice, iommu); > >> + SMMUV3State *s = sdev->smmu; > >> + size_t target_page_size = qemu_target_page_size(); > >> + SMMUBaseClass *sbc = SMMU_DEVICE_GET_CLASS(s); > >> + SMMUTransCfg cfg = {}; > >> + IOMMUTLBEntry entry; > >> + int ret; > >> + > >> + trace_smmuv3_replay_single(mr->parent_obj.name, iova, n); > >> + ret = smmuv3_decode_config(mr, &cfg); > >> + if (ret) { > >> + error_report("%s error decoding the configuration for iommu mr=%s", > >> + __func__, mr->parent_obj.name); > >> + } > >> + > >> + if (cfg.disabled || cfg.bypassed) { > >> + return; > >> + } > >> + > >> + /* first unmap */ > >> + entry.target_as = &address_space_memory; > >> + entry.iova = iova & ~(target_page_size - 1); > >> + entry.addr_mask = target_page_size - 1; > >> + entry.perm = IOMMU_NONE; > >> + > >> + memory_region_notify_one(n, &entry); > >> + > >> + /* then figure out if a new mapping needs to be applied */ > >> + sbc->page_walk_64(&cfg, iova, iova + 1, false, > >> + smmuv3_map_hook, n); > >> +} > >> + > >> +static void smmuv3_notify_flag_changed(IOMMUMemoryRegion *iommu, > >> + IOMMUNotifierFlag old, > >> + IOMMUNotifierFlag new) > >> +{ > >> + SMMUDevice *sdev = container_of(iommu, SMMUDevice, iommu); > >> + SMMUV3State *s3 = sdev->smmu; > >> + SMMUState *s = &(s3->smmu_state); > >> + SMMUNotifierNode *node = NULL; > >> + SMMUNotifierNode *next_node = NULL; > >> + > >> + if (old == IOMMU_NOTIFIER_NONE) { > >> + trace_smmuv3_notify_flag_add(iommu->parent_obj.name); > >> + node = g_malloc0(sizeof(*node)); > >> + node->sdev = sdev; > >> + QLIST_INSERT_HEAD(&s->notifiers_list, node, next); > >> + return; > >> + } > >> + > >> + /* update notifier node with new flags */ > >> + QLIST_FOREACH_SAFE(node, &s->notifiers_list, next, next_node) { > >> + if (node->sdev == sdev) { > >> + if (new == IOMMU_NOTIFIER_NONE) { > >> + trace_smmuv3_notify_flag_del(iommu->parent_obj.name); > >> + QLIST_REMOVE(node, next); > >> + g_free(node); > >> + } > >> + return; > >> + } > >> + } > >> +} > >> > >> static inline void smmu_update_base_reg(SMMUV3State *s, uint64_t *base, > >> uint64_t val) > >> @@ -1125,6 +1382,8 @@ static void smmuv3_iommu_memory_region_class_init(ObjectClass *klass, > >> IOMMUMemoryRegionClass *imrc = IOMMU_MEMORY_REGION_CLASS(klass); > >> > >> imrc->translate = smmuv3_translate; > >> + imrc->notify_flag_changed = smmuv3_notify_flag_changed; > >> + imrc->replay = smmuv3_replay; > >> } > >> > >> static const TypeInfo smmuv3_type_info = { > >> diff --git a/hw/arm/trace-events b/hw/arm/trace-events > >> index f9b9cbe..8228e26 100644 > >> --- a/hw/arm/trace-events > >> +++ b/hw/arm/trace-events > >> @@ -27,6 +27,7 @@ smmuv3_cmdq_opcode(const char *opcode) "<--- %s" > >> smmuv3_cmdq_cfgi_ste(int streamid) " |_ streamid =%d" > >> smmuv3_cmdq_cfgi_ste_range(int start, int end) " |_ start=0x%d - end=0x%d" > >> smmuv3_cmdq_tlbi_nh_va(int asid, int vmid, uint64_t addr) " |_ asid =%d vmid =%d addr=0x%"PRIx64 > >> +smmuv3_cmdq_tlbi_nh_va_am(int asid, int am, size_t size, uint64_t addr) " |_ asid =%d am =%d size=0x%lx addr=0x%"PRIx64 > >> smmuv3_cmdq_consume_sev(void) "CMD_SYNC CS=SEV not supported, ignoring" > >> smmuv3_cmdq_consume_out(uint8_t prod_wrap, uint32_t prod, uint8_t cons_wrap, uint32_t cons) "prod_wrap:%d, prod:0x%x cons_wrap:%d cons:0x%x" > >> smmuv3_update(bool is_empty, uint32_t prod, uint32_t cons, uint8_t prod_wrap, uint8_t cons_wrap) "q empty:%d prod:%d cons:%d p.wrap:%d p.cons:%d" > >> @@ -50,3 +51,16 @@ smmuv3_dump_ste(int i, uint32_t word0, int j, uint32_t word1) "STE[%2d]: 0x%x\t > >> smmuv3_dump_cd(int i, uint32_t word0, int j, uint32_t word1) "CD[%2d]: 0x%x\t CD[%2d]: 0x%x" > >> smmuv3_dump_cmd(int i, uint32_t word0, int j, uint32_t word1) "CMD[%2d]: 0x%x\t CMD[%2d]: 0x%x" > >> smmuv3_cfg_stage(int s, uint32_t oas, uint32_t tsz, uint64_t ttbr, bool aa64, uint32_t granule_sz, int initial_level) "TransCFG stage:%d oas:%d tsz:%d ttbr:0x%"PRIx64" aa64:%d granule_sz:%d, initial_level = %d" > >> + > >> +smmuv3_replay(uint16_t sid, bool enabled) "sid=%d, enabled=%d" > >> +smmuv3_replay_hook(hwaddr iova, hwaddr pa, hwaddr mask, int perm) "iova=0x%"PRIx64" pa=0x%" PRIx64" mask=0x%"PRIx64" perm=%d" > >> +smmuv3_map_hook(hwaddr iova, hwaddr pa, hwaddr mask, int perm) "iova=0x%"PRIx64" pa=0x%" PRIx64" mask=0x%"PRIx64" perm=%d" > >> +smmuv3_notify_flag_add(const char *iommu) "ADD SMMUNotifier node for iommu mr=%s" > >> +smmuv3_notify_flag_del(const char *iommu) "DEL SMMUNotifier node for iommu mr=%s" > >> +smmuv3_replay_single(const char *name, uint64_t iova, void *n) "iommu mr=%s iova=0x%"PRIx64" n=%p" > >> +smmuv3_replay_range(const char *name, uint64_t iova, size_t size, void *n) "iommu mr=%s iova=0x%"PRIx64" size=0x%lx n=%p" > >> +smmuv3_replay_all(const char *name) "iommu mr=%s" > >> +smmuv3_notify_all(const char *name, uint64_t iova) "iommu mr=%s iova=0x%"PRIx64 > >> +smmuv3_unmap_notifier(uint8_t bus, uint8_t slot, uint8_t fn, uint64_t iova, uint64_t size) "Device %02x:%02x.%x start 0x%"PRIx64" size 0x%"PRIx64 > >> +smmuv3_context_device_invalidate(uint32_t sid) "sid=%d" > >> + > >> -- > >> 2.5.5 > >> > >> > > From MAILER-DAEMON Fri Aug 25 15:39:50 2017 Received: from list by lists.gnu.org with archive (Exim 4.71) id 1dlKSM-0000me-0P for mharc-qemu-arm@gnu.org; Fri, 25 Aug 2017 15:39:50 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:34983) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dlKSH-0000ge-BL for qemu-arm@nongnu.org; Fri, 25 Aug 2017 15:39:49 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dlKSD-0001Rn-FB for qemu-arm@nongnu.org; Fri, 25 Aug 2017 15:39:45 -0400 Received: from mx1.redhat.com ([209.132.183.28]:53718) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1dlKSC-0001Rb-UM; Fri, 25 Aug 2017 15:39:41 -0400 Received: from smtp.corp.redhat.com (int-mx03.intmail.prod.int.phx2.redhat.com [10.5.11.13]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id 9742E404333; Fri, 25 Aug 2017 19:39:39 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mx1.redhat.com 9742E404333 Authentication-Results: ext-mx09.extmail.prod.ext.phx2.redhat.com; dmarc=none (p=none dis=none) header.from=redhat.com Authentication-Results: ext-mx09.extmail.prod.ext.phx2.redhat.com; spf=fail smtp.mailfrom=ehabkost@redhat.com Received: from localhost (ovpn-116-18.gru2.redhat.com [10.97.116.18]) by smtp.corp.redhat.com (Postfix) with ESMTP id 481576E513; Fri, 25 Aug 2017 19:39:24 +0000 (UTC) Date: Fri, 25 Aug 2017 16:39:22 -0300 From: Eduardo Habkost To: qemu-devel@nongnu.org Cc: Marcel Apfelbaum , Laine Stump , "Michael S. Tsirkin" , Igor Mammedov , Gerd Hoffmann , Paolo Bonzini , Richard Henderson , Eduardo Habkost , Stefano Stabellini , Anthony Perard , John Snow , Alberto Garcia , Aurelien Jarno , Yongbok Kim , Jiri Slaby , Alexander Graf , Jason Wang , Jiri Pirko , =?iso-8859-1?Q?Herv=E9?= Poussineau , Peter Maydell , David Gibson , Hannes Reinecke , Mark Cave-Ayland , Artyom Tarasenko , Alex Williamson , xen-devel@lists.xenproject.org, qemu-block@nongnu.org, qemu-ppc@nongnu.org, qemu-arm@nongnu.org Message-ID: <20170825193922.GN27715@localhost.localdomain> References: <20170823221445.15243-1-ehabkost@redhat.com> <20170823221445.15243-5-ehabkost@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20170823221445.15243-5-ehabkost@redhat.com> X-Fnord: you can see the fnord User-Agent: Mutt/1.8.0 (2017-02-23) X-Scanned-By: MIMEDefang 2.79 on 10.5.11.13 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.38]); Fri, 25 Aug 2017 19:39:40 +0000 (UTC) X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.132.183.28 Subject: Re: [Qemu-arm] [Qemu-devel] [PATCH 4/5] pci: Add INTERFACE_LEGACY_PCI_DEVICE to legacy PCI devices X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 25 Aug 2017 19:39:49 -0000 CCing maintainers of affected devices (sorry for not CCing you before). On Wed, Aug 23, 2017 at 07:14:44PM -0300, Eduardo Habkost wrote: > Add INTERFACE_LEGACY_PCI_DEVICE to all direct subtypes of > TYPE_PCI_DEVICE, except: > > 1) The ones that already have INTERFACE_PCIE_DEVICE set: > > * base-xhci > * e1000e > * nvme > * pvscsi > * vfio-pci > * virtio-pci > * vmxnet3 > > 2) base-pci-bridge > > Not all PCI bridges are legacy PCI devices, so > INTERFACE_LEGACY_PCI_DEVICE is added only to the subtypes that > are actually legacy PCI devices: > > * dec-21154-p2p-bridge > * i82801b11-bridge > * pbm-bridge > * pci-bridge > > The direct subtypes of base-pci-bridge not touched by this patch > are: > > * xilinx-pcie-root: Already marked as PCIe-only device. > * pcie-port: all non-abstract subtypes of pcie-port are already > marked as PCIe-only devices. > > 3) megasas-base > > Not all megasas devices are legacy PCI devices, so the interface > names are added to the subclasses registered by > megasas_register_types(), according to information in the > megasas_devices[] array. > > "megasas-gen2" already implements INTERFACE_PCIE_DEVICE, so add > INTERFACE_LEGACY_PCI_DEVICE only to "megasas". > > Signed-off-by: Eduardo Habkost > --- > hw/acpi/piix4.c | 1 + > hw/audio/ac97.c | 4 ++++ > hw/audio/es1370.c | 4 ++++ > hw/audio/intel-hda.c | 4 ++++ > hw/char/serial-pci.c | 12 ++++++++++++ > hw/display/cirrus_vga.c | 4 ++++ > hw/display/qxl.c | 4 ++++ > hw/display/sm501.c | 4 ++++ > hw/display/vga-pci.c | 4 ++++ > hw/display/vmware_vga.c | 4 ++++ > hw/i2c/smbus_ich9.c | 4 ++++ > hw/i386/amd_iommu.c | 4 ++++ > hw/i386/kvm/pci-assign.c | 4 ++++ > hw/i386/pc_piix.c | 4 ++++ > hw/i386/xen/xen_platform.c | 4 ++++ > hw/i386/xen/xen_pvdevice.c | 4 ++++ > hw/ide/ich.c | 4 ++++ > hw/ide/pci.c | 4 ++++ > hw/ipack/tpci200.c | 4 ++++ > hw/isa/i82378.c | 4 ++++ > hw/isa/lpc_ich9.c | 1 + > hw/isa/piix4.c | 4 ++++ > hw/isa/vt82c686.c | 16 ++++++++++++++++ > hw/mips/gt64xxx_pci.c | 4 ++++ > hw/misc/edu.c | 5 +++++ > hw/misc/ivshmem.c | 4 ++++ > hw/misc/macio/macio.c | 4 ++++ > hw/misc/pci-testdev.c | 4 ++++ > hw/net/e1000.c | 4 ++++ > hw/net/eepro100.c | 4 ++++ > hw/net/ne2000.c | 4 ++++ > hw/net/pcnet-pci.c | 4 ++++ > hw/net/rocker/rocker.c | 4 ++++ > hw/net/rtl8139.c | 4 ++++ > hw/pci-bridge/dec.c | 8 ++++++++ > hw/pci-bridge/i82801b11.c | 4 ++++ > hw/pci-bridge/pci_bridge_dev.c | 1 + > hw/pci-bridge/pci_expander_bridge.c | 8 ++++++++ > hw/pci-host/apb.c | 8 ++++++++ > hw/pci-host/bonito.c | 4 ++++ > hw/pci-host/gpex.c | 4 ++++ > hw/pci-host/grackle.c | 4 ++++ > hw/pci-host/piix.c | 8 ++++++++ > hw/pci-host/ppce500.c | 4 ++++ > hw/pci-host/prep.c | 4 ++++ > hw/pci-host/q35.c | 4 ++++ > hw/pci-host/uninorth.c | 16 ++++++++++++++++ > hw/pci-host/versatile.c | 4 ++++ > hw/ppc/ppc4xx_pci.c | 4 ++++ > hw/scsi/esp-pci.c | 4 ++++ > hw/scsi/lsi53c895a.c | 4 ++++ > hw/scsi/megasas.c | 4 ++++ > hw/scsi/mptsas.c | 4 ++++ > hw/sd/sdhci.c | 4 ++++ > hw/sh4/sh_pci.c | 4 ++++ > hw/sparc64/sun4u.c | 4 ++++ > hw/usb/hcd-ehci-pci.c | 4 ++++ > hw/usb/hcd-ohci.c | 4 ++++ > hw/usb/hcd-uhci.c | 4 ++++ > hw/vfio/pci-quirks.c | 4 ++++ > hw/watchdog/wdt_i6300esb.c | 4 ++++ > hw/xen/xen_pt.c | 4 ++++ > 62 files changed, 288 insertions(+) > > diff --git a/hw/acpi/piix4.c b/hw/acpi/piix4.c > index f276967..defe98a 100644 > --- a/hw/acpi/piix4.c > +++ b/hw/acpi/piix4.c > @@ -723,6 +723,7 @@ static const TypeInfo piix4_pm_info = { > .interfaces = (InterfaceInfo[]) { > { TYPE_HOTPLUG_HANDLER }, > { TYPE_ACPI_DEVICE_IF }, > + { INTERFACE_LEGACY_PCI_DEVICE }, > { } > } > }; > diff --git a/hw/audio/ac97.c b/hw/audio/ac97.c > index 959c786..6027e15 100644 > --- a/hw/audio/ac97.c > +++ b/hw/audio/ac97.c > @@ -1431,6 +1431,10 @@ static const TypeInfo ac97_info = { > .parent = TYPE_PCI_DEVICE, > .instance_size = sizeof (AC97LinkState), > .class_init = ac97_class_init, > + .interfaces = (InterfaceInfo[]) { > + { INTERFACE_LEGACY_PCI_DEVICE }, > + { }, > + }, > }; > > static void ac97_register_types (void) > diff --git a/hw/audio/es1370.c b/hw/audio/es1370.c > index dd7c23d..ed14ec3 100644 > --- a/hw/audio/es1370.c > +++ b/hw/audio/es1370.c > @@ -1082,6 +1082,10 @@ static const TypeInfo es1370_info = { > .parent = TYPE_PCI_DEVICE, > .instance_size = sizeof (ES1370State), > .class_init = es1370_class_init, > + .interfaces = (InterfaceInfo[]) { > + { INTERFACE_LEGACY_PCI_DEVICE }, > + { }, > + }, > }; > > static void es1370_register_types (void) > diff --git a/hw/audio/intel-hda.c b/hw/audio/intel-hda.c > index 06acc98..e2b9bf5 100644 > --- a/hw/audio/intel-hda.c > +++ b/hw/audio/intel-hda.c > @@ -1299,6 +1299,10 @@ static const TypeInfo intel_hda_info = { > .instance_size = sizeof(IntelHDAState), > .class_init = intel_hda_class_init, > .abstract = true, > + .interfaces = (InterfaceInfo[]) { > + { INTERFACE_LEGACY_PCI_DEVICE }, > + { }, > + }, > }; > > static const TypeInfo intel_hda_info_ich6 = { > diff --git a/hw/char/serial-pci.c b/hw/char/serial-pci.c > index 303104d..c2dbcc0 100644 > --- a/hw/char/serial-pci.c > +++ b/hw/char/serial-pci.c > @@ -250,6 +250,10 @@ static const TypeInfo serial_pci_info = { > .parent = TYPE_PCI_DEVICE, > .instance_size = sizeof(PCISerialState), > .class_init = serial_pci_class_initfn, > + .interfaces = (InterfaceInfo[]) { > + { INTERFACE_LEGACY_PCI_DEVICE }, > + { }, > + }, > }; > > static const TypeInfo multi_2x_serial_pci_info = { > @@ -257,6 +261,10 @@ static const TypeInfo multi_2x_serial_pci_info = { > .parent = TYPE_PCI_DEVICE, > .instance_size = sizeof(PCIMultiSerialState), > .class_init = multi_2x_serial_pci_class_initfn, > + .interfaces = (InterfaceInfo[]) { > + { INTERFACE_LEGACY_PCI_DEVICE }, > + { }, > + }, > }; > > static const TypeInfo multi_4x_serial_pci_info = { > @@ -264,6 +272,10 @@ static const TypeInfo multi_4x_serial_pci_info = { > .parent = TYPE_PCI_DEVICE, > .instance_size = sizeof(PCIMultiSerialState), > .class_init = multi_4x_serial_pci_class_initfn, > + .interfaces = (InterfaceInfo[]) { > + { INTERFACE_LEGACY_PCI_DEVICE }, > + { }, > + }, > }; > > static void serial_pci_register_types(void) > diff --git a/hw/display/cirrus_vga.c b/hw/display/cirrus_vga.c > index afc290a..9a39fa0 100644 > --- a/hw/display/cirrus_vga.c > +++ b/hw/display/cirrus_vga.c > @@ -3162,6 +3162,10 @@ static const TypeInfo cirrus_vga_info = { > .parent = TYPE_PCI_DEVICE, > .instance_size = sizeof(PCICirrusVGAState), > .class_init = cirrus_vga_class_init, > + .interfaces = (InterfaceInfo[]) { > + { INTERFACE_LEGACY_PCI_DEVICE }, > + { }, > + }, > }; > > static void cirrus_vga_register_types(void) > diff --git a/hw/display/qxl.c b/hw/display/qxl.c > index ae3677f..1a010e8 100644 > --- a/hw/display/qxl.c > +++ b/hw/display/qxl.c > @@ -2430,6 +2430,10 @@ static const TypeInfo qxl_pci_type_info = { > .instance_size = sizeof(PCIQXLDevice), > .abstract = true, > .class_init = qxl_pci_class_init, > + .interfaces = (InterfaceInfo[]) { > + { INTERFACE_LEGACY_PCI_DEVICE }, > + { }, > + }, > }; > > static void qxl_primary_class_init(ObjectClass *klass, void *data) > diff --git a/hw/display/sm501.c b/hw/display/sm501.c > index 9aa515b..7538f0c 100644 > --- a/hw/display/sm501.c > +++ b/hw/display/sm501.c > @@ -1843,6 +1843,10 @@ static const TypeInfo sm501_pci_info = { > .parent = TYPE_PCI_DEVICE, > .instance_size = sizeof(SM501PCIState), > .class_init = sm501_pci_class_init, > + .interfaces = (InterfaceInfo[]) { > + { INTERFACE_LEGACY_PCI_DEVICE }, > + { }, > + }, > }; > > static void sm501_register_types(void) > diff --git a/hw/display/vga-pci.c b/hw/display/vga-pci.c > index ac9a764..72477e4 100644 > --- a/hw/display/vga-pci.c > +++ b/hw/display/vga-pci.c > @@ -338,6 +338,10 @@ static const TypeInfo vga_pci_type_info = { > .instance_size = sizeof(PCIVGAState), > .abstract = true, > .class_init = vga_pci_class_init, > + .interfaces = (InterfaceInfo[]) { > + { INTERFACE_LEGACY_PCI_DEVICE }, > + { }, > + }, > }; > > static void vga_class_init(ObjectClass *klass, void *data) > diff --git a/hw/display/vmware_vga.c b/hw/display/vmware_vga.c > index 4a64b41..9c2aa2d 100644 > --- a/hw/display/vmware_vga.c > +++ b/hw/display/vmware_vga.c > @@ -1350,6 +1350,10 @@ static const TypeInfo vmsvga_info = { > .parent = TYPE_PCI_DEVICE, > .instance_size = sizeof(struct pci_vmsvga_state_s), > .class_init = vmsvga_class_init, > + .interfaces = (InterfaceInfo[]) { > + { INTERFACE_LEGACY_PCI_DEVICE }, > + { }, > + }, > }; > > static void vmsvga_register_types(void) > diff --git a/hw/i2c/smbus_ich9.c b/hw/i2c/smbus_ich9.c > index ea51e09..83b0512 100644 > --- a/hw/i2c/smbus_ich9.c > +++ b/hw/i2c/smbus_ich9.c > @@ -119,6 +119,10 @@ static const TypeInfo ich9_smb_info = { > .parent = TYPE_PCI_DEVICE, > .instance_size = sizeof(ICH9SMBState), > .class_init = ich9_smb_class_init, > + .interfaces = (InterfaceInfo[]) { > + { INTERFACE_LEGACY_PCI_DEVICE }, > + { }, > + }, > }; > > static void ich9_smb_register(void) > diff --git a/hw/i386/amd_iommu.c b/hw/i386/amd_iommu.c > index 334938a..471c7a9 100644 > --- a/hw/i386/amd_iommu.c > +++ b/hw/i386/amd_iommu.c > @@ -1227,6 +1227,10 @@ static const TypeInfo amdviPCI = { > .name = "AMDVI-PCI", > .parent = TYPE_PCI_DEVICE, > .instance_size = sizeof(AMDVIPCIState), > + .interfaces = (InterfaceInfo[]) { > + { INTERFACE_LEGACY_PCI_DEVICE }, > + { }, > + }, > }; > > static void amdvi_iommu_memory_region_class_init(ObjectClass *klass, void *data) > diff --git a/hw/i386/kvm/pci-assign.c b/hw/i386/kvm/pci-assign.c > index 33e20cb..57800d3 100644 > --- a/hw/i386/kvm/pci-assign.c > +++ b/hw/i386/kvm/pci-assign.c > @@ -1864,6 +1864,10 @@ static const TypeInfo assign_info = { > .instance_size = sizeof(AssignedDevice), > .class_init = assign_class_init, > .instance_init = assigned_dev_instance_init, > + .interfaces = (InterfaceInfo[]) { > + { INTERFACE_LEGACY_PCI_DEVICE }, > + { }, > + }, > }; > > static void assign_register_types(void) > diff --git a/hw/i386/pc_piix.c b/hw/i386/pc_piix.c > index 46dfd2c..eafc207 100644 > --- a/hw/i386/pc_piix.c > +++ b/hw/i386/pc_piix.c > @@ -1049,6 +1049,10 @@ static TypeInfo isa_bridge_info = { > .parent = TYPE_PCI_DEVICE, > .instance_size = sizeof(PCIDevice), > .class_init = isa_bridge_class_init, > + .interfaces = (InterfaceInfo[]) { > + { INTERFACE_LEGACY_PCI_DEVICE }, > + { }, > + }, > }; > > static void pt_graphics_register_types(void) > diff --git a/hw/i386/xen/xen_platform.c b/hw/i386/xen/xen_platform.c > index 9ba7474..2113bd0 100644 > --- a/hw/i386/xen/xen_platform.c > +++ b/hw/i386/xen/xen_platform.c > @@ -517,6 +517,10 @@ static const TypeInfo xen_platform_info = { > .parent = TYPE_PCI_DEVICE, > .instance_size = sizeof(PCIXenPlatformState), > .class_init = xen_platform_class_init, > + .interfaces = (InterfaceInfo[]) { > + { INTERFACE_LEGACY_PCI_DEVICE }, > + { }, > + }, > }; > > static void xen_platform_register_types(void) > diff --git a/hw/i386/xen/xen_pvdevice.c b/hw/i386/xen/xen_pvdevice.c > index c093b34..e2ae81b 100644 > --- a/hw/i386/xen/xen_pvdevice.c > +++ b/hw/i386/xen/xen_pvdevice.c > @@ -127,6 +127,10 @@ static const TypeInfo xen_pv_type_info = { > .parent = TYPE_PCI_DEVICE, > .instance_size = sizeof(XenPVDevice), > .class_init = xen_pv_class_init, > + .interfaces = (InterfaceInfo[]) { > + { INTERFACE_LEGACY_PCI_DEVICE }, > + { }, > + }, > }; > > static void xen_pv_register_types(void) > diff --git a/hw/ide/ich.c b/hw/ide/ich.c > index 9472a60..0c60aa3 100644 > --- a/hw/ide/ich.c > +++ b/hw/ide/ich.c > @@ -184,6 +184,10 @@ static const TypeInfo ich_ahci_info = { > .instance_size = sizeof(AHCIPCIState), > .instance_init = pci_ich9_ahci_init, > .class_init = ich_ahci_class_init, > + .interfaces = (InterfaceInfo[]) { > + { INTERFACE_LEGACY_PCI_DEVICE }, > + { }, > + }, > }; > > static void ich_ahci_register_types(void) > diff --git a/hw/ide/pci.c b/hw/ide/pci.c > index 3cfb510..f437298 100644 > --- a/hw/ide/pci.c > +++ b/hw/ide/pci.c > @@ -458,6 +458,10 @@ static const TypeInfo pci_ide_type_info = { > .parent = TYPE_PCI_DEVICE, > .instance_size = sizeof(PCIIDEState), > .abstract = true, > + .interfaces = (InterfaceInfo[]) { > + { INTERFACE_LEGACY_PCI_DEVICE }, > + { }, > + }, > }; > > static void pci_ide_register_types(void) > diff --git a/hw/ipack/tpci200.c b/hw/ipack/tpci200.c > index 4dfa6b3..e380378 100644 > --- a/hw/ipack/tpci200.c > +++ b/hw/ipack/tpci200.c > @@ -646,6 +646,10 @@ static const TypeInfo tpci200_info = { > .parent = TYPE_PCI_DEVICE, > .instance_size = sizeof(TPCI200State), > .class_init = tpci200_class_init, > + .interfaces = (InterfaceInfo[]) { > + { INTERFACE_LEGACY_PCI_DEVICE }, > + { }, > + }, > }; > > static void tpci200_register_types(void) > diff --git a/hw/isa/i82378.c b/hw/isa/i82378.c > index 4d29a99..13702b8 100644 > --- a/hw/isa/i82378.c > +++ b/hw/isa/i82378.c > @@ -138,6 +138,10 @@ static const TypeInfo i82378_type_info = { > .instance_size = sizeof(I82378State), > .instance_init = i82378_init, > .class_init = i82378_class_init, > + .interfaces = (InterfaceInfo[]) { > + { INTERFACE_LEGACY_PCI_DEVICE }, > + { }, > + }, > }; > > static void i82378_register_types(void) > diff --git a/hw/isa/lpc_ich9.c b/hw/isa/lpc_ich9.c > index ac8416d..dcde152 100644 > --- a/hw/isa/lpc_ich9.c > +++ b/hw/isa/lpc_ich9.c > @@ -823,6 +823,7 @@ static const TypeInfo ich9_lpc_info = { > .interfaces = (InterfaceInfo[]) { > { TYPE_HOTPLUG_HANDLER }, > { TYPE_ACPI_DEVICE_IF }, > + { INTERFACE_LEGACY_PCI_DEVICE }, > { } > } > }; > diff --git a/hw/isa/piix4.c b/hw/isa/piix4.c > index f811eba..515e55d 100644 > --- a/hw/isa/piix4.c > +++ b/hw/isa/piix4.c > @@ -132,6 +132,10 @@ static const TypeInfo piix4_info = { > .parent = TYPE_PCI_DEVICE, > .instance_size = sizeof(PIIX4State), > .class_init = piix4_class_init, > + .interfaces = (InterfaceInfo[]) { > + { INTERFACE_LEGACY_PCI_DEVICE }, > + { }, > + }, > }; > > static void piix4_register_types(void) > diff --git a/hw/isa/vt82c686.c b/hw/isa/vt82c686.c > index 50dc83d..319dc7f 100644 > --- a/hw/isa/vt82c686.c > +++ b/hw/isa/vt82c686.c > @@ -301,6 +301,10 @@ static const TypeInfo via_ac97_info = { > .parent = TYPE_PCI_DEVICE, > .instance_size = sizeof(VT686AC97State), > .class_init = via_ac97_class_init, > + .interfaces = (InterfaceInfo[]) { > + { INTERFACE_LEGACY_PCI_DEVICE }, > + { }, > + }, > }; > > static void vt82c686b_mc97_realize(PCIDevice *dev, Error **errp) > @@ -341,6 +345,10 @@ static const TypeInfo via_mc97_info = { > .parent = TYPE_PCI_DEVICE, > .instance_size = sizeof(VT686MC97State), > .class_init = via_mc97_class_init, > + .interfaces = (InterfaceInfo[]) { > + { INTERFACE_LEGACY_PCI_DEVICE }, > + { }, > + }, > }; > > /* vt82c686 pm init */ > @@ -419,6 +427,10 @@ static const TypeInfo via_pm_info = { > .parent = TYPE_PCI_DEVICE, > .instance_size = sizeof(VT686PMState), > .class_init = via_pm_class_init, > + .interfaces = (InterfaceInfo[]) { > + { INTERFACE_LEGACY_PCI_DEVICE }, > + { }, > + }, > }; > > static const VMStateDescription vmstate_via = { > @@ -502,6 +514,10 @@ static const TypeInfo via_info = { > .parent = TYPE_PCI_DEVICE, > .instance_size = sizeof(VT82C686BState), > .class_init = via_class_init, > + .interfaces = (InterfaceInfo[]) { > + { INTERFACE_LEGACY_PCI_DEVICE }, > + { }, > + }, > }; > > static void vt82c686b_register_types(void) > diff --git a/hw/mips/gt64xxx_pci.c b/hw/mips/gt64xxx_pci.c > index e8b2eef..96d8cd0 100644 > --- a/hw/mips/gt64xxx_pci.c > +++ b/hw/mips/gt64xxx_pci.c > @@ -1232,6 +1232,10 @@ static const TypeInfo gt64120_pci_info = { > .parent = TYPE_PCI_DEVICE, > .instance_size = sizeof(PCIDevice), > .class_init = gt64120_pci_class_init, > + .interfaces = (InterfaceInfo[]) { > + { INTERFACE_LEGACY_PCI_DEVICE }, > + { }, > + }, > }; > > static void gt64120_class_init(ObjectClass *klass, void *data) > diff --git a/hw/misc/edu.c b/hw/misc/edu.c > index 01acacf..64b12b3 100644 > --- a/hw/misc/edu.c > +++ b/hw/misc/edu.c > @@ -408,12 +408,17 @@ static void edu_class_init(ObjectClass *class, void *data) > > static void pci_edu_register_types(void) > { > + static InterfaceInfo interfaces[] = { > + { INTERFACE_LEGACY_PCI_DEVICE }, > + { }, > + }; > static const TypeInfo edu_info = { > .name = "edu", > .parent = TYPE_PCI_DEVICE, > .instance_size = sizeof(EduState), > .instance_init = edu_instance_init, > .class_init = edu_class_init, > + .interfaces = interfaces, > }; > > type_register_static(&edu_info); > diff --git a/hw/misc/ivshmem.c b/hw/misc/ivshmem.c > index 47a015f..da63c90 100644 > --- a/hw/misc/ivshmem.c > +++ b/hw/misc/ivshmem.c > @@ -1010,6 +1010,10 @@ static const TypeInfo ivshmem_common_info = { > .instance_size = sizeof(IVShmemState), > .abstract = true, > .class_init = ivshmem_common_class_init, > + .interfaces = (InterfaceInfo[]) { > + { INTERFACE_LEGACY_PCI_DEVICE }, > + { }, > + }, > }; > > static const VMStateDescription ivshmem_plain_vmsd = { > diff --git a/hw/misc/macio/macio.c b/hw/misc/macio/macio.c > index 5d57f45..fa163e3 100644 > --- a/hw/misc/macio/macio.c > +++ b/hw/misc/macio/macio.c > @@ -415,6 +415,10 @@ static const TypeInfo macio_type_info = { > .instance_init = macio_instance_init, > .abstract = true, > .class_init = macio_class_init, > + .interfaces = (InterfaceInfo[]) { > + { INTERFACE_LEGACY_PCI_DEVICE }, > + { }, > + }, > }; > > static void macio_register_types(void) > diff --git a/hw/misc/pci-testdev.c b/hw/misc/pci-testdev.c > index 7d59902..992157f 100644 > --- a/hw/misc/pci-testdev.c > +++ b/hw/misc/pci-testdev.c > @@ -326,6 +326,10 @@ static const TypeInfo pci_testdev_info = { > .parent = TYPE_PCI_DEVICE, > .instance_size = sizeof(PCITestDevState), > .class_init = pci_testdev_class_init, > + .interfaces = (InterfaceInfo[]) { > + { INTERFACE_LEGACY_PCI_DEVICE }, > + { }, > + }, > }; > > static void pci_testdev_register_types(void) > diff --git a/hw/net/e1000.c b/hw/net/e1000.c > index f2e5072..51ab83d 100644 > --- a/hw/net/e1000.c > +++ b/hw/net/e1000.c > @@ -1685,6 +1685,10 @@ static const TypeInfo e1000_base_info = { > .instance_init = e1000_instance_init, > .class_size = sizeof(E1000BaseClass), > .abstract = true, > + .interfaces = (InterfaceInfo[]) { > + { INTERFACE_LEGACY_PCI_DEVICE }, > + { }, > + }, > }; > > static const E1000Info e1000_devices[] = { > diff --git a/hw/net/eepro100.c b/hw/net/eepro100.c > index 5a4774a..8f5c567 100644 > --- a/hw/net/eepro100.c > +++ b/hw/net/eepro100.c > @@ -2117,6 +2117,10 @@ static void eepro100_register_types(void) > type_info.class_init = eepro100_class_init; > type_info.instance_size = sizeof(EEPRO100State); > type_info.instance_init = eepro100_instance_init; > + type_info.interfaces = (InterfaceInfo[]) { > + { INTERFACE_LEGACY_PCI_DEVICE }, > + { }, > + }; > > type_register(&type_info); > } > diff --git a/hw/net/ne2000.c b/hw/net/ne2000.c > index 798d681..fce3420 100644 > --- a/hw/net/ne2000.c > +++ b/hw/net/ne2000.c > @@ -786,6 +786,10 @@ static const TypeInfo ne2000_info = { > .instance_size = sizeof(PCINE2000State), > .class_init = ne2000_class_init, > .instance_init = ne2000_instance_init, > + .interfaces = (InterfaceInfo[]) { > + { INTERFACE_LEGACY_PCI_DEVICE }, > + { }, > + }, > }; > > static void ne2000_register_types(void) > diff --git a/hw/net/pcnet-pci.c b/hw/net/pcnet-pci.c > index 0acf8a4..cbe6e99 100644 > --- a/hw/net/pcnet-pci.c > +++ b/hw/net/pcnet-pci.c > @@ -365,6 +365,10 @@ static const TypeInfo pcnet_info = { > .instance_size = sizeof(PCIPCNetState), > .class_init = pcnet_class_init, > .instance_init = pcnet_instance_init, > + .interfaces = (InterfaceInfo[]) { > + { INTERFACE_LEGACY_PCI_DEVICE }, > + { }, > + }, > }; > > static void pci_pcnet_register_types(void) > diff --git a/hw/net/rocker/rocker.c b/hw/net/rocker/rocker.c > index 4f0f6d7..2eb53ad 100644 > --- a/hw/net/rocker/rocker.c > +++ b/hw/net/rocker/rocker.c > @@ -1573,6 +1573,10 @@ static const TypeInfo rocker_info = { > .parent = TYPE_PCI_DEVICE, > .instance_size = sizeof(Rocker), > .class_init = rocker_class_init, > + .interfaces = (InterfaceInfo[]) { > + { INTERFACE_LEGACY_PCI_DEVICE }, > + { }, > + }, > }; > > static void rocker_register_types(void) > diff --git a/hw/net/rtl8139.c b/hw/net/rtl8139.c > index 671c7e4..3371318 100644 > --- a/hw/net/rtl8139.c > +++ b/hw/net/rtl8139.c > @@ -3489,6 +3489,10 @@ static const TypeInfo rtl8139_info = { > .instance_size = sizeof(RTL8139State), > .class_init = rtl8139_class_init, > .instance_init = rtl8139_instance_init, > + .interfaces = (InterfaceInfo[]) { > + { INTERFACE_LEGACY_PCI_DEVICE }, > + { }, > + }, > }; > > static void rtl8139_register_types(void) > diff --git a/hw/pci-bridge/dec.c b/hw/pci-bridge/dec.c > index eb275e1..77a07d0 100644 > --- a/hw/pci-bridge/dec.c > +++ b/hw/pci-bridge/dec.c > @@ -79,6 +79,10 @@ static const TypeInfo dec_21154_pci_bridge_info = { > .parent = TYPE_PCI_BRIDGE, > .instance_size = sizeof(PCIBridge), > .class_init = dec_21154_pci_bridge_class_init, > + .interfaces = (InterfaceInfo[]) { > + { INTERFACE_LEGACY_PCI_DEVICE }, > + { }, > + }, > }; > > PCIBus *pci_dec_21154_init(PCIBus *parent_bus, int devfn) > @@ -138,6 +142,10 @@ static const TypeInfo dec_21154_pci_host_info = { > .parent = TYPE_PCI_DEVICE, > .instance_size = sizeof(PCIDevice), > .class_init = dec_21154_pci_host_class_init, > + .interfaces = (InterfaceInfo[]) { > + { INTERFACE_LEGACY_PCI_DEVICE }, > + { }, > + }, > }; > > static void pci_dec_21154_device_class_init(ObjectClass *klass, void *data) > diff --git a/hw/pci-bridge/i82801b11.c b/hw/pci-bridge/i82801b11.c > index 2c1b747..baac63b 100644 > --- a/hw/pci-bridge/i82801b11.c > +++ b/hw/pci-bridge/i82801b11.c > @@ -106,6 +106,10 @@ static const TypeInfo i82801b11_bridge_info = { > .parent = TYPE_PCI_BRIDGE, > .instance_size = sizeof(I82801b11Bridge), > .class_init = i82801b11_bridge_class_init, > + .interfaces = (InterfaceInfo[]) { > + { INTERFACE_LEGACY_PCI_DEVICE }, > + { }, > + }, > }; > > static void d2pbr_register(void) > diff --git a/hw/pci-bridge/pci_bridge_dev.c b/hw/pci-bridge/pci_bridge_dev.c > index 4373f1d..d83824b 100644 > --- a/hw/pci-bridge/pci_bridge_dev.c > +++ b/hw/pci-bridge/pci_bridge_dev.c > @@ -238,6 +238,7 @@ static const TypeInfo pci_bridge_dev_info = { > .instance_finalize = pci_bridge_dev_instance_finalize, > .interfaces = (InterfaceInfo[]) { > { TYPE_HOTPLUG_HANDLER }, > + { INTERFACE_LEGACY_PCI_DEVICE }, > { } > } > }; > diff --git a/hw/pci-bridge/pci_expander_bridge.c b/hw/pci-bridge/pci_expander_bridge.c > index ff59abf..cc9ec88 100644 > --- a/hw/pci-bridge/pci_expander_bridge.c > +++ b/hw/pci-bridge/pci_expander_bridge.c > @@ -316,6 +316,10 @@ static const TypeInfo pxb_dev_info = { > .parent = TYPE_PCI_DEVICE, > .instance_size = sizeof(PXBDev), > .class_init = pxb_dev_class_init, > + .interfaces = (InterfaceInfo[]) { > + { INTERFACE_LEGACY_PCI_DEVICE }, > + { }, > + }, > }; > > static void pxb_pcie_dev_realize(PCIDevice *dev, Error **errp) > @@ -350,6 +354,10 @@ static const TypeInfo pxb_pcie_dev_info = { > .parent = TYPE_PCI_DEVICE, > .instance_size = sizeof(PXBDev), > .class_init = pxb_pcie_dev_class_init, > + .interfaces = (InterfaceInfo[]) { > + { INTERFACE_LEGACY_PCI_DEVICE }, > + { }, > + }, > }; > > static void pxb_register_types(void) > diff --git a/hw/pci-host/apb.c b/hw/pci-host/apb.c > index 96e5d0b..c2c8c6d 100644 > --- a/hw/pci-host/apb.c > +++ b/hw/pci-host/apb.c > @@ -817,6 +817,10 @@ static const TypeInfo pbm_pci_host_info = { > .parent = TYPE_PCI_DEVICE, > .instance_size = sizeof(PCIDevice), > .class_init = pbm_pci_host_class_init, > + .interfaces = (InterfaceInfo[]) { > + { INTERFACE_LEGACY_PCI_DEVICE }, > + { }, > + }, > }; > > static void pbm_host_class_init(ObjectClass *klass, void *data) > @@ -857,6 +861,10 @@ static const TypeInfo pbm_pci_bridge_info = { > .name = "pbm-bridge", > .parent = TYPE_PCI_BRIDGE, > .class_init = pbm_pci_bridge_class_init, > + .interfaces = (InterfaceInfo[]) { > + { INTERFACE_LEGACY_PCI_DEVICE }, > + { }, > + }, > }; > > static void pbm_iommu_memory_region_class_init(ObjectClass *klass, void *data) > diff --git a/hw/pci-host/bonito.c b/hw/pci-host/bonito.c > index 89133a9..f037378 100644 > --- a/hw/pci-host/bonito.c > +++ b/hw/pci-host/bonito.c > @@ -833,6 +833,10 @@ static const TypeInfo bonito_info = { > .parent = TYPE_PCI_DEVICE, > .instance_size = sizeof(PCIBonitoState), > .class_init = bonito_class_init, > + .interfaces = (InterfaceInfo[]) { > + { INTERFACE_LEGACY_PCI_DEVICE }, > + { }, > + }, > }; > > static void bonito_pcihost_class_init(ObjectClass *klass, void *data) > diff --git a/hw/pci-host/gpex.c b/hw/pci-host/gpex.c > index 83084b9..c348e84 100644 > --- a/hw/pci-host/gpex.c > +++ b/hw/pci-host/gpex.c > @@ -144,6 +144,10 @@ static const TypeInfo gpex_root_info = { > .parent = TYPE_PCI_DEVICE, > .instance_size = sizeof(GPEXRootState), > .class_init = gpex_root_class_init, > + .interfaces = (InterfaceInfo[]) { > + { INTERFACE_LEGACY_PCI_DEVICE }, > + { }, > + }, > }; > > static void gpex_register(void) > diff --git a/hw/pci-host/grackle.c b/hw/pci-host/grackle.c > index 2e281f6..01d3edc 100644 > --- a/hw/pci-host/grackle.c > +++ b/hw/pci-host/grackle.c > @@ -142,6 +142,10 @@ static const TypeInfo grackle_pci_info = { > .parent = TYPE_PCI_DEVICE, > .instance_size = sizeof(PCIDevice), > .class_init = grackle_pci_class_init, > + .interfaces = (InterfaceInfo[]) { > + { INTERFACE_LEGACY_PCI_DEVICE }, > + { }, > + }, > }; > > static void pci_grackle_class_init(ObjectClass *klass, void *data) > diff --git a/hw/pci-host/piix.c b/hw/pci-host/piix.c > index 072a04e..d35520e 100644 > --- a/hw/pci-host/piix.c > +++ b/hw/pci-host/piix.c > @@ -694,6 +694,10 @@ static const TypeInfo piix3_pci_type_info = { > .instance_size = sizeof(PIIX3State), > .abstract = true, > .class_init = pci_piix3_class_init, > + .interfaces = (InterfaceInfo[]) { > + { INTERFACE_LEGACY_PCI_DEVICE }, > + { }, > + }, > }; > > static void piix3_class_init(ObjectClass *klass, void *data) > @@ -748,6 +752,10 @@ static const TypeInfo i440fx_info = { > .parent = TYPE_PCI_DEVICE, > .instance_size = sizeof(PCII440FXState), > .class_init = i440fx_class_init, > + .interfaces = (InterfaceInfo[]) { > + { INTERFACE_LEGACY_PCI_DEVICE }, > + { }, > + }, > }; > > /* IGD Passthrough Host Bridge. */ > diff --git a/hw/pci-host/ppce500.c b/hw/pci-host/ppce500.c > index becc0ee..6dd66c4 100644 > --- a/hw/pci-host/ppce500.c > +++ b/hw/pci-host/ppce500.c > @@ -516,6 +516,10 @@ static const TypeInfo e500_host_bridge_info = { > .parent = TYPE_PCI_DEVICE, > .instance_size = sizeof(PPCE500PCIBridgeState), > .class_init = e500_host_bridge_class_init, > + .interfaces = (InterfaceInfo[]) { > + { INTERFACE_LEGACY_PCI_DEVICE }, > + { }, > + }, > }; > > static Property pcihost_properties[] = { > diff --git a/hw/pci-host/prep.c b/hw/pci-host/prep.c > index 8b293ba..bb19b6d 100644 > --- a/hw/pci-host/prep.c > +++ b/hw/pci-host/prep.c > @@ -372,6 +372,10 @@ static const TypeInfo raven_info = { > .parent = TYPE_PCI_DEVICE, > .instance_size = sizeof(RavenPCIState), > .class_init = raven_class_init, > + .interfaces = (InterfaceInfo[]) { > + { INTERFACE_LEGACY_PCI_DEVICE }, > + { }, > + }, > }; > > static Property raven_pcihost_properties[] = { > diff --git a/hw/pci-host/q35.c b/hw/pci-host/q35.c > index 0e472f2..a6f93f1 100644 > --- a/hw/pci-host/q35.c > +++ b/hw/pci-host/q35.c > @@ -591,6 +591,10 @@ static const TypeInfo mch_info = { > .parent = TYPE_PCI_DEVICE, > .instance_size = sizeof(MCHPCIState), > .class_init = mch_class_init, > + .interfaces = (InterfaceInfo[]) { > + { INTERFACE_LEGACY_PCI_DEVICE }, > + { }, > + }, > }; > > static void q35_register(void) > diff --git a/hw/pci-host/uninorth.c b/hw/pci-host/uninorth.c > index 6cf5e59..3b40a9a 100644 > --- a/hw/pci-host/uninorth.c > +++ b/hw/pci-host/uninorth.c > @@ -374,6 +374,10 @@ static const TypeInfo unin_main_pci_host_info = { > .parent = TYPE_PCI_DEVICE, > .instance_size = sizeof(PCIDevice), > .class_init = unin_main_pci_host_class_init, > + .interfaces = (InterfaceInfo[]) { > + { INTERFACE_LEGACY_PCI_DEVICE }, > + { }, > + }, > }; > > static void u3_agp_pci_host_class_init(ObjectClass *klass, void *data) > @@ -398,6 +402,10 @@ static const TypeInfo u3_agp_pci_host_info = { > .parent = TYPE_PCI_DEVICE, > .instance_size = sizeof(PCIDevice), > .class_init = u3_agp_pci_host_class_init, > + .interfaces = (InterfaceInfo[]) { > + { INTERFACE_LEGACY_PCI_DEVICE }, > + { }, > + }, > }; > > static void unin_agp_pci_host_class_init(ObjectClass *klass, void *data) > @@ -422,6 +430,10 @@ static const TypeInfo unin_agp_pci_host_info = { > .parent = TYPE_PCI_DEVICE, > .instance_size = sizeof(PCIDevice), > .class_init = unin_agp_pci_host_class_init, > + .interfaces = (InterfaceInfo[]) { > + { INTERFACE_LEGACY_PCI_DEVICE }, > + { }, > + }, > }; > > static void unin_internal_pci_host_class_init(ObjectClass *klass, void *data) > @@ -446,6 +458,10 @@ static const TypeInfo unin_internal_pci_host_info = { > .parent = TYPE_PCI_DEVICE, > .instance_size = sizeof(PCIDevice), > .class_init = unin_internal_pci_host_class_init, > + .interfaces = (InterfaceInfo[]) { > + { INTERFACE_LEGACY_PCI_DEVICE }, > + { }, > + }, > }; > > static void pci_unin_main_class_init(ObjectClass *klass, void *data) > diff --git a/hw/pci-host/versatile.c b/hw/pci-host/versatile.c > index aa1fdf7..e1ba6f4 100644 > --- a/hw/pci-host/versatile.c > +++ b/hw/pci-host/versatile.c > @@ -487,6 +487,10 @@ static const TypeInfo versatile_pci_host_info = { > .parent = TYPE_PCI_DEVICE, > .instance_size = sizeof(PCIDevice), > .class_init = versatile_pci_host_class_init, > + .interfaces = (InterfaceInfo[]) { > + { INTERFACE_LEGACY_PCI_DEVICE }, > + { }, > + }, > }; > > static Property pci_vpb_properties[] = { > diff --git a/hw/ppc/ppc4xx_pci.c b/hw/ppc/ppc4xx_pci.c > index 6953f8b..92027c3 100644 > --- a/hw/ppc/ppc4xx_pci.c > +++ b/hw/ppc/ppc4xx_pci.c > @@ -359,6 +359,10 @@ static const TypeInfo ppc4xx_host_bridge_info = { > .parent = TYPE_PCI_DEVICE, > .instance_size = sizeof(PCIDevice), > .class_init = ppc4xx_host_bridge_class_init, > + .interfaces = (InterfaceInfo[]) { > + { INTERFACE_LEGACY_PCI_DEVICE }, > + { }, > + }, > }; > > static void ppc4xx_pcihost_class_init(ObjectClass *klass, void *data) > diff --git a/hw/scsi/esp-pci.c b/hw/scsi/esp-pci.c > index e295d88..2f0c659 100644 > --- a/hw/scsi/esp-pci.c > +++ b/hw/scsi/esp-pci.c > @@ -398,6 +398,10 @@ static const TypeInfo esp_pci_info = { > .parent = TYPE_PCI_DEVICE, > .instance_size = sizeof(PCIESPState), > .class_init = esp_pci_class_init, > + .interfaces = (InterfaceInfo[]) { > + { INTERFACE_LEGACY_PCI_DEVICE }, > + { }, > + }, > }; > > typedef struct { > diff --git a/hw/scsi/lsi53c895a.c b/hw/scsi/lsi53c895a.c > index 3e56ab2..788bfc3 100644 > --- a/hw/scsi/lsi53c895a.c > +++ b/hw/scsi/lsi53c895a.c > @@ -2244,6 +2244,10 @@ static const TypeInfo lsi_info = { > .parent = TYPE_PCI_DEVICE, > .instance_size = sizeof(LSIState), > .class_init = lsi_class_init, > + .interfaces = (InterfaceInfo[]) { > + { INTERFACE_LEGACY_PCI_DEVICE }, > + { }, > + }, > }; > > static void lsi53c810_class_init(ObjectClass *klass, void *data) > diff --git a/hw/scsi/megasas.c b/hw/scsi/megasas.c > index 3641c30..cf69b56 100644 > --- a/hw/scsi/megasas.c > +++ b/hw/scsi/megasas.c > @@ -2468,6 +2468,10 @@ static struct MegasasInfo megasas_devices[] = { > .is_express = false, > .vmsd = &vmstate_megasas_gen1, > .props = megasas_properties_gen1, > + .interfaces = (InterfaceInfo[]) { > + { INTERFACE_LEGACY_PCI_DEVICE }, > + { }, > + }, > },{ > .name = TYPE_MEGASAS_GEN2, > .desc = "LSI MegaRAID SAS 2108", > diff --git a/hw/scsi/mptsas.c b/hw/scsi/mptsas.c > index 765ab53..6ff773e 100644 > --- a/hw/scsi/mptsas.c > +++ b/hw/scsi/mptsas.c > @@ -1441,6 +1441,10 @@ static const TypeInfo mptsas_info = { > .parent = TYPE_PCI_DEVICE, > .instance_size = sizeof(MPTSASState), > .class_init = mptsas1068_class_init, > + .interfaces = (InterfaceInfo[]) { > + { INTERFACE_LEGACY_PCI_DEVICE }, > + { }, > + }, > }; > > static void mptsas_register_types(void) > diff --git a/hw/sd/sdhci.c b/hw/sd/sdhci.c > index 6d6a791..f6b18d6 100644 > --- a/hw/sd/sdhci.c > +++ b/hw/sd/sdhci.c > @@ -1315,6 +1315,10 @@ static const TypeInfo sdhci_pci_info = { > .parent = TYPE_PCI_DEVICE, > .instance_size = sizeof(SDHCIState), > .class_init = sdhci_pci_class_init, > + .interfaces = (InterfaceInfo[]) { > + { INTERFACE_LEGACY_PCI_DEVICE }, > + { }, > + }, > }; > > static Property sdhci_sysbus_properties[] = { > diff --git a/hw/sh4/sh_pci.c b/hw/sh4/sh_pci.c > index 38395c0..6cec225 100644 > --- a/hw/sh4/sh_pci.c > +++ b/hw/sh4/sh_pci.c > @@ -179,6 +179,10 @@ static const TypeInfo sh_pci_host_info = { > .parent = TYPE_PCI_DEVICE, > .instance_size = sizeof(PCIDevice), > .class_init = sh_pci_host_class_init, > + .interfaces = (InterfaceInfo[]) { > + { INTERFACE_LEGACY_PCI_DEVICE }, > + { }, > + }, > }; > > static void sh_pci_device_class_init(ObjectClass *klass, void *data) > diff --git a/hw/sparc64/sun4u.c b/hw/sparc64/sun4u.c > index bbdb40c..b2b3bab 100644 > --- a/hw/sparc64/sun4u.c > +++ b/hw/sparc64/sun4u.c > @@ -277,6 +277,10 @@ static const TypeInfo ebus_info = { > .parent = TYPE_PCI_DEVICE, > .instance_size = sizeof(EbusState), > .class_init = ebus_class_init, > + .interfaces = (InterfaceInfo[]) { > + { INTERFACE_LEGACY_PCI_DEVICE }, > + { }, > + }, > }; > > #define TYPE_OPENPROM "openprom" > diff --git a/hw/usb/hcd-ehci-pci.c b/hw/usb/hcd-ehci-pci.c > index 6dedcb8..464178d 100644 > --- a/hw/usb/hcd-ehci-pci.c > +++ b/hw/usb/hcd-ehci-pci.c > @@ -170,6 +170,10 @@ static const TypeInfo ehci_pci_type_info = { > .instance_finalize = usb_ehci_pci_finalize, > .abstract = true, > .class_init = ehci_class_init, > + .interfaces = (InterfaceInfo[]) { > + { INTERFACE_LEGACY_PCI_DEVICE }, > + { }, > + }, > }; > > static void ehci_data_class_init(ObjectClass *klass, void *data) > diff --git a/hw/usb/hcd-ohci.c b/hw/usb/hcd-ohci.c > index 267982e..8b5e579 100644 > --- a/hw/usb/hcd-ohci.c > +++ b/hw/usb/hcd-ohci.c > @@ -2139,6 +2139,10 @@ static const TypeInfo ohci_pci_info = { > .parent = TYPE_PCI_DEVICE, > .instance_size = sizeof(OHCIPCIState), > .class_init = ohci_pci_class_init, > + .interfaces = (InterfaceInfo[]) { > + { INTERFACE_LEGACY_PCI_DEVICE }, > + { }, > + }, > }; > > static Property ohci_sysbus_properties[] = { > diff --git a/hw/usb/hcd-uhci.c b/hw/usb/hcd-uhci.c > index e3562a4..8842ea6 100644 > --- a/hw/usb/hcd-uhci.c > +++ b/hw/usb/hcd-uhci.c > @@ -1323,6 +1323,10 @@ static const TypeInfo uhci_pci_type_info = { > .class_size = sizeof(UHCIPCIDeviceClass), > .abstract = true, > .class_init = uhci_class_init, > + .interfaces = (InterfaceInfo[]) { > + { INTERFACE_LEGACY_PCI_DEVICE }, > + { }, > + }, > }; > > static void uhci_data_class_init(ObjectClass *klass, void *data) > diff --git a/hw/vfio/pci-quirks.c b/hw/vfio/pci-quirks.c > index 349085e..83a820a 100644 > --- a/hw/vfio/pci-quirks.c > +++ b/hw/vfio/pci-quirks.c > @@ -1197,6 +1197,10 @@ static TypeInfo vfio_pci_igd_lpc_bridge_info = { > .name = "vfio-pci-igd-lpc-bridge", > .parent = TYPE_PCI_DEVICE, > .class_init = vfio_pci_igd_lpc_bridge_class_init, > + .interfaces = (InterfaceInfo[]) { > + { INTERFACE_LEGACY_PCI_DEVICE }, > + { }, > + }, > }; > > static void vfio_pci_igd_register_types(void) > diff --git a/hw/watchdog/wdt_i6300esb.c b/hw/watchdog/wdt_i6300esb.c > index 49b3cd1..f8b7e0c 100644 > --- a/hw/watchdog/wdt_i6300esb.c > +++ b/hw/watchdog/wdt_i6300esb.c > @@ -463,6 +463,10 @@ static const TypeInfo i6300esb_info = { > .parent = TYPE_PCI_DEVICE, > .instance_size = sizeof(I6300State), > .class_init = i6300esb_class_init, > + .interfaces = (InterfaceInfo[]) { > + { INTERFACE_LEGACY_PCI_DEVICE }, > + { }, > + }, > }; > > static void i6300esb_register_types(void) > diff --git a/hw/xen/xen_pt.c b/hw/xen/xen_pt.c > index 375efa6..66664fc 100644 > --- a/hw/xen/xen_pt.c > +++ b/hw/xen/xen_pt.c > @@ -964,6 +964,10 @@ static const TypeInfo xen_pci_passthrough_info = { > .instance_size = sizeof(XenPCIPassthroughState), > .instance_finalize = xen_pci_passthrough_finalize, > .class_init = xen_pci_passthrough_class_init, > + .interfaces = (InterfaceInfo[]) { > + { INTERFACE_LEGACY_PCI_DEVICE }, > + { }, > + }, > }; > > static void xen_pci_passthrough_register_types(void) > -- > 2.9.4 > > -- Eduardo From MAILER-DAEMON Fri Aug 25 18:48:42 2017 Received: from list by lists.gnu.org with archive (Exim 4.71) id 1dlNP8-0004X6-Ni for mharc-qemu-arm@gnu.org; Fri, 25 Aug 2017 18:48:42 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:43910) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dlNP6-0004Wa-GJ for qemu-arm@nongnu.org; Fri, 25 Aug 2017 18:48:41 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dlNP5-0001wS-Bc for qemu-arm@nongnu.org; Fri, 25 Aug 2017 18:48:40 -0400 Received: from mail-pg0-x22d.google.com ([2607:f8b0:400e:c05::22d]:35507) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1dlNP5-0001sX-4h for qemu-arm@nongnu.org; Fri, 25 Aug 2017 18:48:39 -0400 Received: by mail-pg0-x22d.google.com with SMTP id 63so5941856pgc.2 for ; Fri, 25 Aug 2017 15:48:37 -0700 (PDT) DKIM-Signature: v=1; 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Fri, 25 Aug 2017 15:48:36 -0700 (PDT) Received: from bigtime.twiddle.net.net ([2603:3004:4:2500::22fc]) by smtp.gmail.com with ESMTPSA id o10sm14346641pgc.81.2017.08.25.15.48.35 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 25 Aug 2017 15:48:35 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-stable@nongnu.org Date: Fri, 25 Aug 2017 15:48:33 -0700 Message-Id: <20170825224833.4463-1-richard.henderson@linaro.org> X-Mailer: git-send-email 2.13.5 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::22d Subject: [Qemu-arm] [PATCH] target/arm: Fix aa64 ldp register writeback X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 25 Aug 2017 22:48:41 -0000 For "ldp x0, x1, [x0]", if the second load is on a second page and the second page is unmapped, the exception would be raised with x0 already modified. This means the instruction couldn't be restarted. Cc: qemu-arm@nongnu.org Cc: qemu-stable@nongnu.org Reported-by: Andrew Fixes: https://bugs.launchpad.net/qemu/+bug/1713066 Signed-off-by: Richard Henderson --- target/arm/translate-a64.c | 28 ++++++++++++++++------------ 1 file changed, 16 insertions(+), 12 deletions(-) diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index c596025b04..bfba816a77 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -2217,29 +2217,33 @@ static void disas_ldst_pair(DisasContext *s, uint32_t insn) } else { do_fp_st(s, rt, tcg_addr, size); } - } else { - TCGv_i64 tcg_rt = cpu_reg(s, rt); - if (is_load) { - do_gpr_ld(s, tcg_rt, tcg_addr, size, is_signed, false, - false, 0, false, false); - } else { - do_gpr_st(s, tcg_rt, tcg_addr, size, - false, 0, false, false); - } - } - tcg_gen_addi_i64(tcg_addr, tcg_addr, 1 << size); - if (is_vector) { + tcg_gen_addi_i64(tcg_addr, tcg_addr, 1 << size); if (is_load) { do_fp_ld(s, rt2, tcg_addr, size); } else { do_fp_st(s, rt2, tcg_addr, size); } } else { + TCGv_i64 tcg_rt = cpu_reg(s, rt); TCGv_i64 tcg_rt2 = cpu_reg(s, rt2); + if (is_load) { + TCGv_i64 tmp = tcg_temp_new_i64(); + + /* Do not modify tcg_rt before recognizing any exception + from the second load. */ + do_gpr_ld(s, tmp, tcg_addr, size, is_signed, false, + false, 0, false, false); + tcg_gen_addi_i64(tcg_addr, tcg_addr, 1 << size); do_gpr_ld(s, tcg_rt2, tcg_addr, size, is_signed, false, false, 0, false, false); + + tcg_gen_mov_i64(tcg_rt, tmp); + tcg_temp_free_i64(tmp); } else { + do_gpr_st(s, tcg_rt, tcg_addr, size, + false, 0, false, false); + tcg_gen_addi_i64(tcg_addr, tcg_addr, 1 << size); do_gpr_st(s, tcg_rt2, tcg_addr, size, false, 0, false, false); } -- 2.13.5 From MAILER-DAEMON Fri Aug 25 21:02:10 2017 Received: from list by lists.gnu.org with archive (Exim 4.71) id 1dlPUI-0000S6-FN for mharc-qemu-arm@gnu.org; Fri, 25 Aug 2017 21:02:10 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:60922) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dlPUF-0000Rq-VL for qemu-arm@nongnu.org; Fri, 25 Aug 2017 21:02:08 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dlPUC-0007hY-V8 for qemu-arm@nongnu.org; Fri, 25 Aug 2017 21:02:08 -0400 Received: from szxga04-in.huawei.com ([45.249.212.190]:2300) by eggs.gnu.org with esmtps (TLS1.0:RSA_ARCFOUR_SHA1:16) (Exim 4.71) (envelope-from ) id 1dlPUC-0007dm-B6; Fri, 25 Aug 2017 21:02:04 -0400 Received: from 172.30.72.60 (EHLO DGGEMS405-HUB.china.huawei.com) ([172.30.72.60]) by dggrg04-dlp.huawei.com (MOS 4.4.6-GA FastPath queued) with ESMTP id DFX08833; Sat, 26 Aug 2017 09:00:17 +0800 (CST) Received: from [127.0.0.1] (10.177.16.142) by DGGEMS405-HUB.china.huawei.com (10.3.19.205) with Microsoft SMTP Server id 14.3.301.0; Sat, 26 Aug 2017 09:00:08 +0800 Message-ID: <59A0C813.2060201@huawei.com> Date: Sat, 26 Aug 2017 09:00:03 +0800 From: Shannon Zhao User-Agent: Mozilla/5.0 (Windows NT 6.1; rv:24.0) Gecko/20100101 Thunderbird/24.4.0 MIME-Version: 1.0 To: gengdongjiu , , , , , , , , , , , , , , , , , , , , , , , , , , , , , CC: , , , References: <1503066227-18251-1-git-send-email-gengdongjiu@huawei.com> <1503066227-18251-2-git-send-email-gengdongjiu@huawei.com> <599EC7AB.3080604@huawei.com> <69090a96-ce90-4b2b-a419-c8d847d56093@huawei.com> In-Reply-To: <69090a96-ce90-4b2b-a419-c8d847d56093@huawei.com> Content-Type: text/plain; charset="windows-1252" Content-Transfer-Encoding: 7bit X-Originating-IP: [10.177.16.142] X-CFilter-Loop: Reflected X-Mirapoint-Virus-RAPID-Raw: score=unknown(0), refid=str=0001.0A090205.59A0C824.0040, ss=1, re=0.000, recu=0.000, reip=0.000, cl=1, cld=1, fgs=0, ip=0.0.0.0, so=2014-11-16 11:51:01, dmn=2013-03-21 17:37:32 X-Mirapoint-Loop-Id: 3dc7720de09a1a930da2bd11f60d6ba9 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.4.x-2.6.x [generic] [fuzzy] X-Received-From: 45.249.212.190 Subject: Re: [Qemu-arm] [PATCH v11 1/6] ACPI: add APEI/HEST/CPER structures and macros X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sat, 26 Aug 2017 01:02:09 -0000 On 2017/8/25 18:37, gengdongjiu wrote: >>> + >>> >> +/* From the ACPI 6.1 spec, "18.3.2.9 Hardware Error Notification" */ >>> >> + >> > It's better to refer to the first spec version of this structure and >> > same with others you define. > do you mean which spec version? the definition is aligned with the linux kernel. What I mean here is that it's better to refer to the ACPI spec version which introduces Hardware Error Notification first time. >> > >>> >> +enum AcpiHestNotifyType { >>> >> + ACPI_HEST_NOTIFY_POLLED = 0, >>> >> + ACPI_HEST_NOTIFY_EXTERNAL = 1, >>> >> + ACPI_HEST_NOTIFY_LOCAL = 2, >>> >> + ACPI_HEST_NOTIFY_SCI = 3, >>> >> + ACPI_HEST_NOTIFY_NMI = 4, >>> >> + ACPI_HEST_NOTIFY_CMCI = 5, /* ACPI 5.0 */ >>> >> + ACPI_HEST_NOTIFY_MCE = 6, /* ACPI 5.0 */ >>> >> + ACPI_HEST_NOTIFY_GPIO = 7, /* ACPI 6.0 */ >>> >> + ACPI_HEST_NOTIFY_SEA = 8, /* ACPI 6.1 */ >>> >> + ACPI_HEST_NOTIFY_SEI = 9, /* ACPI 6.1 */ >>> >> + ACPI_HEST_NOTIFY_GSIV = 10, /* ACPI 6.1 */ >>> >> + ACPI_HEST_NOTIFY_RESERVED = 11 /* 11 and greater are reserved */ >> > In ACPI 6.2, 11 is for Software Delegated Exception, is this useful for >> > your patchset? > it is usefull, for all the error source, I reserved the space for them. > Because the space is allocated one time, is not dynamically allocated. > so I use the ACPI_HEST_NOTIFY_RESERVED to specify that there is 11 error source. > I mean whether the new type Software Delegated Exception is useful for RAS. If so, we could add this new type here. Thanks, -- Shannon From MAILER-DAEMON Fri Aug 25 21:09:53 2017 Received: from list by lists.gnu.org with archive (Exim 4.71) id 1dlPbl-0002EF-Ae for mharc-qemu-arm@gnu.org; Fri, 25 Aug 2017 21:09:53 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:33529) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dlPbj-00025f-7y for qemu-arm@nongnu.org; Fri, 25 Aug 2017 21:09:52 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dlPbg-00023a-3v for qemu-arm@nongnu.org; Fri, 25 Aug 2017 21:09:51 -0400 Received: from szxga04-in.huawei.com ([45.249.212.190]:2301) by eggs.gnu.org with esmtps (TLS1.0:RSA_ARCFOUR_SHA1:16) (Exim 4.71) (envelope-from ) id 1dlPbf-00023C-Hk; Fri, 25 Aug 2017 21:09:48 -0400 Received: from 172.30.72.60 (EHLO DGGEMS413-HUB.china.huawei.com) ([172.30.72.60]) by dggrg04-dlp.huawei.com (MOS 4.4.6-GA FastPath queued) with ESMTP id DFX10032; Sat, 26 Aug 2017 09:08:29 +0800 (CST) Received: from [127.0.0.1] (10.177.16.142) by DGGEMS413-HUB.china.huawei.com (10.3.19.213) with Microsoft SMTP Server id 14.3.301.0; Sat, 26 Aug 2017 09:08:18 +0800 Message-ID: <59A0C9FE.5010204@huawei.com> Date: Sat, 26 Aug 2017 09:08:14 +0800 From: Shannon Zhao User-Agent: Mozilla/5.0 (Windows NT 6.1; rv:24.0) Gecko/20100101 Thunderbird/24.4.0 MIME-Version: 1.0 To: gengdongjiu , , , , , , , , , , , , , , , , , , , , , , , , , , , , , CC: , , , References: <1503066227-18251-1-git-send-email-gengdongjiu@huawei.com> <1503066227-18251-3-git-send-email-gengdongjiu@huawei.com> <599ECE95.10205@huawei.com> <9a878b42-c480-2c7b-0f04-202193d8c56b@huawei.com> In-Reply-To: <9a878b42-c480-2c7b-0f04-202193d8c56b@huawei.com> Content-Type: text/plain; charset="windows-1252" Content-Transfer-Encoding: 7bit X-Originating-IP: [10.177.16.142] X-CFilter-Loop: Reflected X-Mirapoint-Virus-RAPID-Raw: score=unknown(0), refid=str=0001.0A090204.59A0CA0D.0049, ss=1, re=0.000, recu=0.000, reip=0.000, cl=1, cld=1, fgs=0, ip=0.0.0.0, so=2014-11-16 11:51:01, dmn=2013-03-21 17:37:32 X-Mirapoint-Loop-Id: 72b1c22ab38c0022a5c2d9e53ed95867 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.4.x-2.6.x [generic] [fuzzy] X-Received-From: 45.249.212.190 Subject: Re: [Qemu-arm] [PATCH v11 2/6] ACPI: Add APEI GHES Table Generation support X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sat, 26 Aug 2017 01:09:52 -0000 On 2017/8/25 19:20, gengdongjiu wrote: >>> diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c >>> >> index 3d78ff6..def1ec1 100644 >>> >> --- a/hw/arm/virt-acpi-build.c >>> >> +++ b/hw/arm/virt-acpi-build.c >>> >> @@ -45,6 +45,7 @@ >>> >> #include "hw/arm/virt.h" >>> >> #include "sysemu/numa.h" >>> >> #include "kvm_arm.h" >>> >> +#include "hw/acpi/hest_ghes.h" >>> >> >>> >> #define ARM_SPI_BASE 32 >>> >> #define ACPI_POWER_BUTTON_DEVICE "PWRB" >>> >> @@ -771,6 +772,9 @@ void virt_acpi_build(VirtMachineState *vms, AcpiBuildTables *tables) >>> >> acpi_add_table(table_offsets, tables_blob); >>> >> build_spcr(tables_blob, tables->linker, vms); >>> >> >>> >> + acpi_add_table(table_offsets, tables_blob); >>> >> + ghes_build_acpi(tables_blob, tables->hardware_errors, tables->linker); >>> >> + >> > So we add this table unconditionally. Is there any bad impact if QEMU >> > runs on old kvm? Does it need to check whether KVM supports RAS? > this table is added before guest OS boot. so can not use KVM to check it. No, we can check the RAS capability when we create vcpus like you done in another patch ans can use that in table generation. > if the old kvm does not support RAS, it does not have bad impact. only waste table memory. > May be we can make it as device? if this device is enabled in the qemu > boot parameters, then we will add this table? > And you need to add a option to virt machine for (migration) compatibility. On new virt machine it's on by default while off for old ones. Thanks, -- Shannon From MAILER-DAEMON Fri Aug 25 21:49:18 2017 Received: from list by lists.gnu.org with archive (Exim 4.71) id 1dlQDu-000110-1A for mharc-qemu-arm@gnu.org; Fri, 25 Aug 2017 21:49:18 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:37921) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dlQDs-00010l-0M for qemu-arm@nongnu.org; Fri, 25 Aug 2017 21:49:16 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dlQDr-0006KV-3H for qemu-arm@nongnu.org; Fri, 25 Aug 2017 21:49:16 -0400 Received: from szxga04-in.huawei.com ([45.249.212.190]:2302) by eggs.gnu.org with esmtps (TLS1.0:RSA_ARCFOUR_SHA1:16) (Exim 4.71) (envelope-from ) id 1dlQDq-0006JB-Fw; Fri, 25 Aug 2017 21:49:15 -0400 Received: from 172.30.72.58 (EHLO DGGEMS406-HUB.china.huawei.com) ([172.30.72.58]) by dggrg04-dlp.huawei.com (MOS 4.4.6-GA FastPath queued) with ESMTP id DFX14448; Sat, 26 Aug 2017 09:45:28 +0800 (CST) Received: from [127.0.0.1] (10.142.68.147) by DGGEMS406-HUB.china.huawei.com (10.3.19.206) with Microsoft SMTP Server id 14.3.301.0; Sat, 26 Aug 2017 09:45:16 +0800 To: Shannon Zhao , , , , , , , , , , , , , , , , , , , , , , , , , , , , , References: <1503066227-18251-1-git-send-email-gengdongjiu@huawei.com> <1503066227-18251-2-git-send-email-gengdongjiu@huawei.com> <599EC7AB.3080604@huawei.com> <69090a96-ce90-4b2b-a419-c8d847d56093@huawei.com> <59A0C813.2060201@huawei.com> CC: , , , From: gengdongjiu Message-ID: <03f2f404-2718-75c7-d0eb-7bdeba146a2e@huawei.com> Date: Sat, 26 Aug 2017 09:45:02 +0800 User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:45.0) Gecko/20100101 Thunderbird/45.7.1 MIME-Version: 1.0 In-Reply-To: <59A0C813.2060201@huawei.com> Content-Type: text/plain; charset="windows-1252" Content-Transfer-Encoding: 7bit X-Originating-IP: [10.142.68.147] X-CFilter-Loop: Reflected X-Mirapoint-Virus-RAPID-Raw: score=unknown(0), refid=str=0001.0A020205.59A0D2B8.00DE, ss=1, re=0.000, recu=0.000, reip=0.000, cl=1, cld=1, fgs=0, ip=0.0.0.0, so=2014-11-16 11:51:01, dmn=2013-03-21 17:37:32 X-Mirapoint-Loop-Id: 3dc7720de09a1a930da2bd11f60d6ba9 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.4.x-2.6.x [generic] [fuzzy] X-Received-From: 45.249.212.190 Subject: Re: [Qemu-arm] [PATCH v11 1/6] ACPI: add APEI/HEST/CPER structures and macros X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sat, 26 Aug 2017 01:49:17 -0000 On 2017/8/26 9:00, Shannon Zhao wrote: > > > On 2017/8/25 18:37, gengdongjiu wrote: >>>> + >>>>>> +/* From the ACPI 6.1 spec, "18.3.2.9 Hardware Error Notification" */ >>>>>> + >>>> It's better to refer to the first spec version of this structure and >>>> same with others you define. >> do you mean which spec version? the definition is aligned with the linux kernel. > What I mean here is that it's better to refer to the ACPI spec version > which introduces Hardware Error Notification first time. Ok, I basically understand your meaning. I will clear that. thanks. > >>>> >>>>>> +enum AcpiHestNotifyType { >>>>>> + ACPI_HEST_NOTIFY_POLLED = 0, >>>>>> + ACPI_HEST_NOTIFY_EXTERNAL = 1, >>>>>> + ACPI_HEST_NOTIFY_LOCAL = 2, >>>>>> + ACPI_HEST_NOTIFY_SCI = 3, >>>>>> + ACPI_HEST_NOTIFY_NMI = 4, >>>>>> + ACPI_HEST_NOTIFY_CMCI = 5, /* ACPI 5.0 */ >>>>>> + ACPI_HEST_NOTIFY_MCE = 6, /* ACPI 5.0 */ >>>>>> + ACPI_HEST_NOTIFY_GPIO = 7, /* ACPI 6.0 */ >>>>>> + ACPI_HEST_NOTIFY_SEA = 8, /* ACPI 6.1 */ >>>>>> + ACPI_HEST_NOTIFY_SEI = 9, /* ACPI 6.1 */ >>>>>> + ACPI_HEST_NOTIFY_GSIV = 10, /* ACPI 6.1 */ >>>>>> + ACPI_HEST_NOTIFY_RESERVED = 11 /* 11 and greater are reserved */ >>>> In ACPI 6.2, 11 is for Software Delegated Exception, is this useful for >>>> your patchset? >> it is usefull, for all the error source, I reserved the space for them. >> Because the space is allocated one time, is not dynamically allocated. >> so I use the ACPI_HEST_NOTIFY_RESERVED to specify that there is 11 error source. >> > I mean whether the new type Software Delegated Exception is useful for > RAS. If so, we could add this new type here. Just now I check the ACPI 6.2 spec, it indeed introduced the new type SDEI. currently we do not use the type Software Delegated Exception which introduced by ACPI 6.2, so may not need to add a new type. > > Thanks, > From MAILER-DAEMON Fri Aug 25 22:50:45 2017 Received: from list by lists.gnu.org with archive (Exim 4.71) id 1dlRBN-0003ly-RO for mharc-qemu-arm@gnu.org; Fri, 25 Aug 2017 22:50:45 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:48412) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dlRBK-0003ll-4D for qemu-arm@nongnu.org; Fri, 25 Aug 2017 22:50:43 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dlRBI-0002Be-DO for qemu-arm@nongnu.org; Fri, 25 Aug 2017 22:50:42 -0400 Received: from szxga05-in.huawei.com ([45.249.212.191]:2245) by eggs.gnu.org with esmtps (TLS1.0:RSA_ARCFOUR_SHA1:16) (Exim 4.71) (envelope-from ) id 1dlRBH-0002AX-Q2; Fri, 25 Aug 2017 22:50:40 -0400 Received: from 172.30.72.60 (EHLO DGGEMS408-HUB.china.huawei.com) ([172.30.72.60]) by dggrg05-dlp.huawei.com (MOS 4.4.6-GA FastPath queued) with ESMTP id DFZ24726; Sat, 26 Aug 2017 10:50:06 +0800 (CST) Received: from [127.0.0.1] (10.142.68.147) by DGGEMS408-HUB.china.huawei.com (10.3.19.208) with Microsoft SMTP Server id 14.3.301.0; Sat, 26 Aug 2017 10:49:51 +0800 To: Shannon Zhao , , , , , , , , , , , , , , , , , , , , , , , , , , , , , References: <1503066227-18251-1-git-send-email-gengdongjiu@huawei.com> <1503066227-18251-3-git-send-email-gengdongjiu@huawei.com> <599ECE95.10205@huawei.com> <9a878b42-c480-2c7b-0f04-202193d8c56b@huawei.com> <59A0C9FE.5010204@huawei.com> CC: , , , From: gengdongjiu Message-ID: <27894653-ff09-7839-a46d-b41b9ee8ae48@huawei.com> Date: Sat, 26 Aug 2017 10:49:44 +0800 User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:45.0) Gecko/20100101 Thunderbird/45.7.1 MIME-Version: 1.0 In-Reply-To: <59A0C9FE.5010204@huawei.com> Content-Type: text/plain; charset="windows-1252" Content-Transfer-Encoding: 7bit X-Originating-IP: [10.142.68.147] X-CFilter-Loop: Reflected X-Mirapoint-Virus-RAPID-Raw: score=unknown(0), refid=str=0001.0A090203.59A0E1DF.001C, ss=1, re=0.000, recu=0.000, reip=0.000, cl=1, cld=1, fgs=0, ip=0.0.0.0, so=2014-11-16 11:51:01, dmn=2013-03-21 17:37:32 X-Mirapoint-Loop-Id: c402118da617b6014ffafdba62dacbd2 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.4.x-2.6.x [generic] [fuzzy] X-Received-From: 45.249.212.191 Subject: Re: [Qemu-arm] [PATCH v11 2/6] ACPI: Add APEI GHES Table Generation support X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sat, 26 Aug 2017 02:50:43 -0000 Hi Shannon, On 2017/8/26 9:08, Shannon Zhao wrote: > > > On 2017/8/25 19:20, gengdongjiu wrote: >>>> diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c >>>>>> index 3d78ff6..def1ec1 100644 >>>>>> --- a/hw/arm/virt-acpi-build.c >>>>>> +++ b/hw/arm/virt-acpi-build.c >>>>>> @@ -45,6 +45,7 @@ >>>>>> #include "hw/arm/virt.h" >>>>>> #include "sysemu/numa.h" >>>>>> #include "kvm_arm.h" >>>>>> +#include "hw/acpi/hest_ghes.h" >>>>>> >>>>>> #define ARM_SPI_BASE 32 >>>>>> #define ACPI_POWER_BUTTON_DEVICE "PWRB" >>>>>> @@ -771,6 +772,9 @@ void virt_acpi_build(VirtMachineState *vms, AcpiBuildTables *tables) >>>>>> acpi_add_table(table_offsets, tables_blob); >>>>>> build_spcr(tables_blob, tables->linker, vms); >>>>>> >>>>>> + acpi_add_table(table_offsets, tables_blob); >>>>>> + ghes_build_acpi(tables_blob, tables->hardware_errors, tables->linker); >>>>>> + >>>> So we add this table unconditionally. Is there any bad impact if QEMU >>>> runs on old kvm? Does it need to check whether KVM supports RAS? >> this table is added before guest OS boot. so can not use KVM to check it. > No, we can check the RAS capability when we create vcpus like you done > in another patch ans can use that in table generation. understand your meaning. ARM James ever have below comments about the table generation. ---------------------------------------------------------------------------------- But you can use APEI in a guest on CPUs without the RAS extensions: the host may signal memory errors to Qemu for any number of reasons, user-space shouldn't care how it knows. Examples are PCI-AER, any APEI event notified by polling or one of the flavours of irq. I would expect Qemu to generate a HEST based on its abilities, i.e. if it supports any mechanism of notifying the guest about errors. Choosing the mechanism then depends on the type of error. Ideally the Qemu code for HEST/GHES/CPER generation code using some of the irqs and polling could be shared with x86, as these should be possible using common KVM APIs. ----------------------------------------------------------------------------------- He means we can use APEI on CPUs without RAS and may be share this code with x86, if Qemu can support any mechanism of notifying the guest about errors, it should be generate the table. Now we depend on the macro KVM_HAVE_MCE_INJECTION to decide whether Qemu can support notifying the guest. what do you think which we should be dependent on to generate the table? > >> if the old kvm does not support RAS, it does not have bad impact. only waste table memory. >> May be we can make it as device? if this device is enabled in the qemu >> boot parameters, then we will add this table? >> > > And you need to add a option to virt machine for (migration) > compatibility. On new virt machine it's on by default while off for old > ones. ok. > > Thanks, > From MAILER-DAEMON Sun Aug 27 23:53:35 2017 Received: from list by lists.gnu.org with archive (Exim 4.71) id 1dmB7G-0003iC-Vr for mharc-qemu-arm@gnu.org; Sun, 27 Aug 2017 23:53:35 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:55711) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dmB7E-0003ha-Dj for qemu-arm@nongnu.org; Sun, 27 Aug 2017 23:53:33 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dmB7B-0003vi-CD for qemu-arm@nongnu.org; Sun, 27 Aug 2017 23:53:32 -0400 Received: from mail-yw0-x242.google.com ([2607:f8b0:4002:c05::242]:38795) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1dmB7B-0003vR-7u; Sun, 27 Aug 2017 23:53:29 -0400 Received: by mail-yw0-x242.google.com with SMTP id e9so2724751ywh.5; Sun, 27 Aug 2017 20:53:29 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id; bh=t8FBrkfB07s9pw9b9O6Qh9ZHCadicrTF8TnZ05hruSc=; b=LKGFub7dnIPwx8uoYb1+mfGm2tg2I4Ql0Op0utRS1GLMKmBiO5VBNkWoK+1E6G3LYE ND3iUr9ksJ5CdtQ8mKctCchdzNCpVmnYGIaG+Re6YTR0VQlrRsJw1D/IQkbeLvFiR4CZ 9h7msevX2u6sqlhSm37O3Up8VvTVQU7cBBn2cAigQOAGRGMUU5LqtH299W+f7HNUK918 vh7qt8ZbSzfiffsnLryUQ7/ORcj2rbI7g/LRmOB1/J2BXMo6TbgiYgSFY4scDeHBlMr0 9OwGmoelbaOwCXOCnOUBTKD59YnRgPhAfiA4kPCsHx7TwjSvmNT5o746SRhCY94brZU0 3+Jg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=t8FBrkfB07s9pw9b9O6Qh9ZHCadicrTF8TnZ05hruSc=; b=d2kVuFaFq/jNSUgixFwqE+j+NrUKQr96ol5THLQEW2Aa5lttHL7Dtl2BvkUhRng8kU jJJv8UcovIBvjZChKzhuRLIZxKOUXgt8TEhU9uumILSug3tj46fh/m0NrtjDwfl+DDYs sdf//lZid75pWKRlA0ZtS4s45QTMieP3SdLlK9SL3eG+OoeQimAtFJ6+gK63yD7amKl4 7cA5rG6Z9LrXbklmoeudtRmUdk10eauOAVKjCu0dN0UN/VFh8JP0ivKtiwaL+28+KyXG ZzMArWJ1bxXDaBlJjEtCW1sZea7hAlhvfSO0gYy+qVDIlBh0Nip0AatxOn/xRERaqXcQ e5GQ== X-Gm-Message-State: AHYfb5jypevmaGL60Kk5hTwWLqW2UafKAQocA0+MeyFiBTsBuPvKq9xw 3Ir6jJjjkz2SEQ== X-Received: by 10.37.183.196 with SMTP id u4mr5145423ybj.39.1503892408517; Sun, 27 Aug 2017 20:53:28 -0700 (PDT) Received: from localhost.localdomain ([98.192.46.210]) by smtp.gmail.com with ESMTPSA id i64sm4820865ywi.64.2017.08.27.20.53.27 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sun, 27 Aug 2017 20:53:27 -0700 (PDT) From: Pranith Kumar To: alex.bennee@linaro.org, Peter Maydell , qemu-arm@nongnu.org (open list:ARM), qemu-devel@nongnu.org (open list:All patches CC here) Cc: qemu-devel@nongnu.org, rth@twiddle.net, pbonzini@redhat.com Date: Sun, 27 Aug 2017 23:53:24 -0400 Message-Id: <20170828035327.17146-1-bobby.prani@gmail.com> X-Mailer: git-send-email 2.13.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4002:c05::242 Subject: [Qemu-arm] [PATCH 1/3] target/arm: Remove stale comment X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 28 Aug 2017 03:53:33 -0000 Update the comment which is not true since MTTCG. Signed-off-by: Pranith Kumar --- target/arm/translate-a64.c | 4 ---- 1 file changed, 4 deletions(-) diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 2200e25be0..f42b155d7d 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -2012,10 +2012,6 @@ static void disas_ldst_excl(DisasContext *s, uint32_t insn) } tcg_addr = read_cpu_reg_sp(s, rn, 1); - /* Note that since TCG is single threaded load-acquire/store-release - * semantics require no extra if (is_lasr) { ... } handling. - */ - if (is_excl) { if (!is_store) { s->is_ldex = true; -- 2.13.0 From MAILER-DAEMON Sun Aug 27 23:53:36 2017 Received: from list by lists.gnu.org with archive (Exim 4.71) id 1dmB7H-0003jA-V2 for mharc-qemu-arm@gnu.org; Sun, 27 Aug 2017 23:53:35 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:55733) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dmB7F-0003hf-F0 for qemu-arm@nongnu.org; Sun, 27 Aug 2017 23:53:34 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dmB7D-0003yf-GY for qemu-arm@nongnu.org; Sun, 27 Aug 2017 23:53:33 -0400 Received: from mail-yw0-x242.google.com ([2607:f8b0:4002:c05::242]:34179) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1dmB7D-0003xh-AP; Sun, 27 Aug 2017 23:53:31 -0400 Received: by mail-yw0-x242.google.com with SMTP id h127so2734835ywf.1; Sun, 27 Aug 2017 20:53:31 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=NKneIklgXd1r8SxdWzvYWVqIn/IWKcCDCp5OlI41SWU=; b=HwAHAtEtDIZQHZHlwbzcsSIOxxnA54XSXqkewVNX28Kv5f15J1hh8ZA6DfQyqKIqCd Qe54VTIarZeQF2XZWprouccFPkKq00SiWEXxdbuUxokG/3YusYDSiAs/GrR5kqOGhW3b GeRbBXn6KmGnBWix0BuZmyS80o8kYvN68f45H5Aqgl8W6Yw7EBRTa3CJmrS1f4Lywr0E UCSaZujo5H8/xUcAPEQ3Y6Af/nr/4wUXHB2ligsC//z060azMW5Pl4HrTHdxd45AonHx nPQ9HNZxDSqPE3EUmO6wrEVNsL7JPZN8+hASITWHSDYXt5HY6n9rZxMcmTuX1NamxWnW BhKg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=NKneIklgXd1r8SxdWzvYWVqIn/IWKcCDCp5OlI41SWU=; b=H55lNEfAy/sN72TQ8/HopOof0JUZS8dK/Y/qzWPqiU/TuBksAvTr9e1mpfYHNZWmLt d9f807zjFIzJuTWurlJAP6ZE2sqca0qAgNfcIiZxlKz3qkEwUxRjfrli9l+7o57dMvv6 fFSoxx8inSnOCs+2LkB4nLsRfaPbUNFUrpHbJecDQ3APcfCPasRhl7xWPLDWLSq92Oy4 1tkqUuxgWbI6V9KVua6eV3KQSpYxIZ9KKxHKOVZaoZa1OUrIopjVxmGqi4V9vqjWsetX fnp7KSlJReM7+VMGiSs65UjCdBCasce4Mpm7CutMOeEDiBBXJ2EnH0Gvl+c05TMy2mTi oYHQ== X-Gm-Message-State: AHYfb5g9wXiNd4ZiHsEATG6y1sKYrtCoC4N4mIxisqsHGstl7Cd9u0Uv mfy1hI1VcWqWlQ== X-Received: by 10.37.14.212 with SMTP id 203mr4858559ybo.164.1503892410621; Sun, 27 Aug 2017 20:53:30 -0700 (PDT) Received: from localhost.localdomain ([98.192.46.210]) by smtp.gmail.com with ESMTPSA id i64sm4820865ywi.64.2017.08.27.20.53.29 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sun, 27 Aug 2017 20:53:30 -0700 (PDT) From: Pranith Kumar To: alex.bennee@linaro.org, Claudio Fontana , Richard Henderson , Andrzej Zaborowski , Aurelien Jarno , qemu-arm@nongnu.org (open list:AArch64 target), qemu-devel@nongnu.org (open list:All patches CC here) Cc: qemu-devel@nongnu.org, pbonzini@redhat.com Date: Sun, 27 Aug 2017 23:53:26 -0400 Message-Id: <20170828035327.17146-3-bobby.prani@gmail.com> X-Mailer: git-send-email 2.13.0 In-Reply-To: <20170828035327.17146-1-bobby.prani@gmail.com> References: <20170828035327.17146-1-bobby.prani@gmail.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4002:c05::242 Subject: [Qemu-arm] [RFC PATCH 3/3] mttcg: Implement implicit ordering semantics X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 28 Aug 2017 03:53:34 -0000 Currently, we cannot use mttcg for running strong memory model guests on weak memory model hosts due to missing ordering semantics. We implicitly generate fence instructions for stronger guests if an ordering mismatch is detected. We generate fences only for the orders for which fence instructions are necessary, for example a fence is not necessary between a store and a subsequent load on x86 since its absence in the guest binary tells that ordering need not be ensured. Also note that if we find multiple subsequent fence instructions in the generated IR, we combine them in the TCG optimization pass. This patch allows us to boot an x86 guest on ARM64 hosts using mttcg. Signed-off-by: Pranith Kumar --- tcg/aarch64/tcg-target.h | 2 ++ tcg/arm/tcg-target.h | 2 ++ tcg/mips/tcg-target.h | 2 ++ tcg/ppc/tcg-target.h | 2 ++ tcg/tcg-op.c | 17 +++++++++++++++++ tcg/tcg-op.h | 1 + 6 files changed, 26 insertions(+) diff --git a/tcg/aarch64/tcg-target.h b/tcg/aarch64/tcg-target.h index 55a46ac825..b41a248bee 100644 --- a/tcg/aarch64/tcg-target.h +++ b/tcg/aarch64/tcg-target.h @@ -117,4 +117,6 @@ static inline void flush_icache_range(uintptr_t start, uintptr_t stop) __builtin___clear_cache((char *)start, (char *)stop); } +#define TCG_TARGET_DEFAULT_MO (0) + #endif /* AARCH64_TCG_TARGET_H */ diff --git a/tcg/arm/tcg-target.h b/tcg/arm/tcg-target.h index 5ef1086710..a38be15a39 100644 --- a/tcg/arm/tcg-target.h +++ b/tcg/arm/tcg-target.h @@ -134,4 +134,6 @@ static inline void flush_icache_range(uintptr_t start, uintptr_t stop) __builtin___clear_cache((char *) start, (char *) stop); } +#define TCG_TARGET_DEFAULT_MO (0) + #endif diff --git a/tcg/mips/tcg-target.h b/tcg/mips/tcg-target.h index d75cb63ed3..e9558d15bc 100644 --- a/tcg/mips/tcg-target.h +++ b/tcg/mips/tcg-target.h @@ -206,4 +206,6 @@ static inline void flush_icache_range(uintptr_t start, uintptr_t stop) cacheflush ((void *)start, stop-start, ICACHE); } +#define TCG_TARGET_DEFAULT_MO (0) + #endif diff --git a/tcg/ppc/tcg-target.h b/tcg/ppc/tcg-target.h index 5f4a40a5b4..5a092b038a 100644 --- a/tcg/ppc/tcg-target.h +++ b/tcg/ppc/tcg-target.h @@ -125,4 +125,6 @@ extern bool have_isa_3_00; void flush_icache_range(uintptr_t start, uintptr_t stop); +#define TCG_TARGET_DEFAULT_MO (0) + #endif diff --git a/tcg/tcg-op.c b/tcg/tcg-op.c index 87f673ef49..085fe66fb2 100644 --- a/tcg/tcg-op.c +++ b/tcg/tcg-op.c @@ -28,6 +28,7 @@ #include "exec/exec-all.h" #include "tcg.h" #include "tcg-op.h" +#include "tcg-mo.h" #include "trace-tcg.h" #include "trace/mem.h" @@ -2662,8 +2663,21 @@ static void gen_ldst_i64(TCGOpcode opc, TCGv_i64 val, TCGv addr, #endif } +void tcg_gen_req_mo(TCGBar type) +{ +#if defined(TCG_GUEST_DEFAULT_MO) && defined(TCG_TARGET_DEFAULT_MO) + TCGBar order_mismatch = type & (TCG_GUEST_DEFAULT_MO & ~TCG_TARGET_DEFAULT_MO); + if (order_mismatch) { + tcg_gen_mb(order_mismatch | TCG_BAR_SC); + } +#else + tcg_gen_mb(TCG_MO_ALL | TCG_BAR_SC); +#endif +} + void tcg_gen_qemu_ld_i32(TCGv_i32 val, TCGv addr, TCGArg idx, TCGMemOp memop) { + tcg_gen_req_mo(TCG_MO_LD_LD | TCG_MO_LD_ST); memop = tcg_canonicalize_memop(memop, 0, 0); trace_guest_mem_before_tcg(tcg_ctx.cpu, tcg_ctx.tcg_env, addr, trace_mem_get_info(memop, 0)); @@ -2672,6 +2686,7 @@ void tcg_gen_qemu_ld_i32(TCGv_i32 val, TCGv addr, TCGArg idx, TCGMemOp memop) void tcg_gen_qemu_st_i32(TCGv_i32 val, TCGv addr, TCGArg idx, TCGMemOp memop) { + tcg_gen_req_mo(TCG_MO_ST_LD | TCG_MO_ST_ST); memop = tcg_canonicalize_memop(memop, 0, 1); trace_guest_mem_before_tcg(tcg_ctx.cpu, tcg_ctx.tcg_env, addr, trace_mem_get_info(memop, 1)); @@ -2680,6 +2695,7 @@ void tcg_gen_qemu_st_i32(TCGv_i32 val, TCGv addr, TCGArg idx, TCGMemOp memop) void tcg_gen_qemu_ld_i64(TCGv_i64 val, TCGv addr, TCGArg idx, TCGMemOp memop) { + tcg_gen_req_mo(TCG_MO_LD_LD | TCG_MO_LD_ST); if (TCG_TARGET_REG_BITS == 32 && (memop & MO_SIZE) < MO_64) { tcg_gen_qemu_ld_i32(TCGV_LOW(val), addr, idx, memop); if (memop & MO_SIGN) { @@ -2698,6 +2714,7 @@ void tcg_gen_qemu_ld_i64(TCGv_i64 val, TCGv addr, TCGArg idx, TCGMemOp memop) void tcg_gen_qemu_st_i64(TCGv_i64 val, TCGv addr, TCGArg idx, TCGMemOp memop) { + tcg_gen_req_mo(TCG_MO_ST_LD | TCG_MO_ST_ST); if (TCG_TARGET_REG_BITS == 32 && (memop & MO_SIZE) < MO_64) { tcg_gen_qemu_st_i32(TCGV_LOW(val), addr, idx, memop); return; diff --git a/tcg/tcg-op.h b/tcg/tcg-op.h index 5d3278f243..6ad2c6d60e 100644 --- a/tcg/tcg-op.h +++ b/tcg/tcg-op.h @@ -262,6 +262,7 @@ static inline void tcg_gen_br(TCGLabel *l) } void tcg_gen_mb(TCGBar); +void tcg_gen_req_mo(TCGBar type); /* Helper calls. */ -- 2.13.0 From MAILER-DAEMON Mon Aug 28 09:09:55 2017 Received: from list by lists.gnu.org with archive (Exim 4.71) id 1dmJnf-0007TW-Dj for mharc-qemu-arm@gnu.org; Mon, 28 Aug 2017 09:09:55 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:35897) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dmFbO-0003Mx-VL for qemu-arm@nongnu.org; Mon, 28 Aug 2017 04:41:03 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dmFbO-0006de-Am for qemu-arm@nongnu.org; Mon, 28 Aug 2017 04:40:58 -0400 Received: from fanzine.igalia.com ([91.117.99.155]:59388) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1dmFbE-0006QS-Gk; Mon, 28 Aug 2017 04:40:48 -0400 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=igalia.com; s=20170329; h=Content-Type:MIME-Version:Message-ID:Date:References:In-Reply-To:Subject:Cc:To:From; bh=MQM0k6tQuFVr+P19nPvulRPRjSnfAvTd/nalCOe9akM=; b=o6Ei9uuaayWoGQYIxznxbYphd9bBN1zc5nfr3S//a+1A7J1O0zbxdIpGvzLFVl6MjrLzK43AniwMkURSDquF4T9wx82qgKFmNZ5EYibGQ+K3C56iSvRmcefWS9GG7yy2Y1ESwYzSaivyICulA8EmJdzSyEMDn6/whi4xoNBp5C6gfizBEs5NHhVSR2zCidVPAhXH+9Yr4wkIkQmaWM5z6noiQlWpmITs4+XjbwOQMVeZLhhUjtZMP84FG+hYlZl25o3bdpr7DPsUl5//HjPcoCa4GgD04LTA7IUE9QsFDmK3zZihxVcxqSPBoCGGDSpgst+C68M3JFi3cyAg/Vkiyg==; Received: from maestria.local.igalia.com ([192.168.10.14] helo=mail.igalia.com) by fanzine.igalia.com with esmtps (Cipher TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim) id 1dmFac-0004HA-7X; Mon, 28 Aug 2017 10:40:10 +0200 Received: from berto by mail.igalia.com with local (Exim) id 1dmFac-0005d1-53; Mon, 28 Aug 2017 10:40:10 +0200 From: Alberto Garcia To: Eduardo Habkost , qemu-devel@nongnu.org Cc: xen-devel@lists.xenproject.org, qemu-block@nongnu.org, qemu-ppc@nongnu.org, qemu-arm@nongnu.org In-Reply-To: <20170825193922.GN27715@localhost.localdomain> References: <20170823221445.15243-1-ehabkost@redhat.com> <20170823221445.15243-5-ehabkost@redhat.com> <20170825193922.GN27715@localhost.localdomain> User-Agent: Notmuch/0.18.2 (http://notmuchmail.org) Emacs/24.4.1 (i586-pc-linux-gnu) Date: Mon, 28 Aug 2017 10:40:10 +0200 Message-ID: MIME-Version: 1.0 Content-Type: text/plain X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x (no timestamps) [generic] [fuzzy] X-Received-From: 91.117.99.155 X-Mailman-Approved-At: Mon, 28 Aug 2017 09:09:54 -0400 Subject: Re: [Qemu-arm] [Qemu-devel] [PATCH 4/5] pci: Add INTERFACE_LEGACY_PCI_DEVICE to legacy PCI devices X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 28 Aug 2017 08:41:04 -0000 On Fri 25 Aug 2017 09:39:22 PM CEST, Eduardo Habkost wrote: > CCing maintainers of affected devices (sorry for not CCing you > before). >> diff --git a/hw/ipack/tpci200.c b/hw/ipack/tpci200.c >> index 4dfa6b3..e380378 100644 >> --- a/hw/ipack/tpci200.c >> +++ b/hw/ipack/tpci200.c >> @@ -646,6 +646,10 @@ static const TypeInfo tpci200_info = { >> .parent = TYPE_PCI_DEVICE, >> .instance_size = sizeof(TPCI200State), >> .class_init = tpci200_class_init, >> + .interfaces = (InterfaceInfo[]) { >> + { INTERFACE_LEGACY_PCI_DEVICE }, >> + { }, >> + }, >> }; Acked-by: Alberto Garcia Berto From MAILER-DAEMON Mon Aug 28 12:38:28 2017 Received: from list by lists.gnu.org with archive (Exim 4.71) id 1dmN3U-0001zk-8g for mharc-qemu-arm@gnu.org; Mon, 28 Aug 2017 12:38:28 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:45167) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dmN3R-0001xa-Da for qemu-arm@nongnu.org; Mon, 28 Aug 2017 12:38:26 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dmN3Q-0003Bt-61 for qemu-arm@nongnu.org; Mon, 28 Aug 2017 12:38:25 -0400 Received: from mail-pg0-x244.google.com ([2607:f8b0:400e:c05::244]:38342) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1dmN3L-0002iZ-7V; Mon, 28 Aug 2017 12:38:19 -0400 Received: by mail-pg0-x244.google.com with SMTP id t3so728070pgt.5; Mon, 28 Aug 2017 09:38:17 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id; 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Mon, 28 Aug 2017 09:38:16 -0700 (PDT) Received: from localhost.localdomain ([124.123.70.3]) by smtp.gmail.com with ESMTPSA id n66sm1935015pfi.44.2017.08.28.09.38.14 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 28 Aug 2017 09:38:16 -0700 (PDT) From: Subbaraya Sundeep To: qemu-devel@nongnu.org, qemu-arm@nongnu.org Cc: peter.maydell@linaro.org, crosthwaite.peter@gmail.com, alistair23@gmail.com, f4bug@amsat.org, Subbaraya Sundeep Date: Mon, 28 Aug 2017 22:07:58 +0530 Message-Id: <1503938283-12404-1-git-send-email-sundeep.lkml@gmail.com> X-Mailer: git-send-email 2.5.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::244 Subject: [Qemu-arm] [Qemu devel v7 PATCH 0/5] Add support for Smartfusion2 SoC X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 28 Aug 2017 16:38:26 -0000 Hi Qemu-devel, I am trying to add Smartfusion2 SoC. SoC is from Microsemi and System on Module(SOM) board is from Emcraft systems. Smartfusion2 has hardened Microcontroller(Cortex-M3)based Sub System and FPGA fabric. At the moment only system timer, sysreg and SPI controller are modelled. Testing: ./arm-softmmu/qemu-system-arm -M smartfusion2-som -serial mon:stdio \ -kernel u-boot.bin -display none -drive file=spi.bin,if=mtd,format=raw Binaries u-boot.bin and spi.bin are at: https://github.com/Subbaraya-Sundeep/qemu-test-binaries.git U-boot is from Emcraft with modified - SPI driver not to use PDMA. - ugly hack to pass dtb to kernel in r1. @ https://github.com/Subbaraya-Sundeep/emcraft-uboot-sf2.git Linux is 4.5 linux with Smartfusion2 SoC dts and clocksource driver added by myself @ https://github.com/Subbaraya-Sundeep/linux.git v7: Removed vmstate_register_ram_global as per latest commit Moved header files to C which are local to C source files Removed abort() from msf2-sysreg.c Added VMStateDescription in mss-timer.c v6: Moved some defines from header files to source files Added properties m3clk, apb0div, apb0div1 properties to soc. Added properties apb0divisor, apb1divisor to sysreg Update system_clock_source in msf2-soc.c Changed machine name smartfusion2-som->emcraft-sf2 v5 As per Philippe comments: Added abort in Sysreg if guest tries to remap memory other than default mapping. Use of CONFIG_MSF2 in Makefile for soc.c Fixed incorrect logic in timer model. Renamed msf2-timer.c -> mss-timer.c msf2-spi.c -> mss-spi.c also type names Renamed function msf2_init->emcraft_sf2_init in msf2-som.c Added part-name,eNVM-size,eSRAM-size,pclk0 and pclk1 properties to soc. Pass soc part-name,memory size and clock rate properties from som. v4: Fixed build failure by using PRIx macros. v3: Added SoC file and board file as per Alistair comments. v2: Added SPI controller so that u-boot loads kernel from spi flash. v1: Initial patch set with timer and sysreg Thanks, Sundeep Subbaraya Sundeep (5): msf2: Add Smartfusion2 System timer msf2: Microsemi Smartfusion2 System Register block msf2: Add Smartfusion2 SPI controller msf2: Add Smartfusion2 SoC msf2: Add Emcraft's Smartfusion2 SOM kit default-configs/arm-softmmu.mak | 1 + hw/arm/Makefile.objs | 1 + hw/arm/msf2-soc.c | 215 +++++++++++++++++++++ hw/arm/msf2-som.c | 94 +++++++++ hw/misc/Makefile.objs | 1 + hw/misc/msf2-sysreg.c | 199 +++++++++++++++++++ hw/ssi/Makefile.objs | 1 + hw/ssi/mss-spi.c | 409 ++++++++++++++++++++++++++++++++++++++++ hw/timer/Makefile.objs | 1 + hw/timer/mss-timer.c | 289 ++++++++++++++++++++++++++++ include/hw/arm/msf2-soc.h | 66 +++++++ include/hw/misc/msf2-sysreg.h | 78 ++++++++ include/hw/ssi/mss-spi.h | 58 ++++++ include/hw/timer/mss-timer.h | 64 +++++++ 14 files changed, 1477 insertions(+) create mode 100644 hw/arm/msf2-soc.c create mode 100644 hw/arm/msf2-som.c create mode 100644 hw/misc/msf2-sysreg.c create mode 100644 hw/ssi/mss-spi.c create mode 100644 hw/timer/mss-timer.c create mode 100644 include/hw/arm/msf2-soc.h create mode 100644 include/hw/misc/msf2-sysreg.h create mode 100644 include/hw/ssi/mss-spi.h create mode 100644 include/hw/timer/mss-timer.h -- 2.5.0 From MAILER-DAEMON Mon Aug 28 12:38:30 2017 Received: from list by lists.gnu.org with archive (Exim 4.71) id 1dmN3W-00021k-K3 for mharc-qemu-arm@gnu.org; Mon, 28 Aug 2017 12:38:30 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:45191) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dmN3T-0001z7-8z for qemu-arm@nongnu.org; Mon, 28 Aug 2017 12:38:29 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dmN3R-0003Gg-8A for qemu-arm@nongnu.org; Mon, 28 Aug 2017 12:38:27 -0400 Received: from mail-pf0-x244.google.com ([2607:f8b0:400e:c00::244]:37579) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1dmN3M-0002vA-Qi; Mon, 28 Aug 2017 12:38:20 -0400 Received: by mail-pf0-x244.google.com with SMTP id a2so631677pfj.4; Mon, 28 Aug 2017 09:38:20 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=Etg/ixnIntw5HFEkH4RhXDcqeV2dbyLB+Pq1OA/+DCI=; b=CrhLQyNUjDURrEn0tskT4yiJUELTCsB663xabvc5FJhcj8TtkzWHwHW2rkaiCGhtyX iJDD5ic9XG73d6RPM6Jeggn1rf7Fwb9pJKhOWnfEB3qPUcaX+1Oo24QU+Xfuv6c36hhX uHPAQA79zU8mXtmOe0p6zM+rppq6iK9vZ58v+KUlprdLspsQQfeJSbuitI/H0YeWUnRU HNTd+Fnqa/VfznAIG9oNEkSscZ3tPCgaEbNQcoVt54Ev/tQ0wWeBF5KxAwJfIMpP7oD+ 6eSvVtoEmtC4WGk2JewxQMKNhpuMqTwjiuN8OD2JaZjNpn+OVCXykhAAogkTnEIA8jcS /x5w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=Etg/ixnIntw5HFEkH4RhXDcqeV2dbyLB+Pq1OA/+DCI=; b=MZsFnTiOS1DVqr8NbnQ4NZeb83NinqVcao1u29C3ayZZOXmwIfT8gYMiulv7RTQdNc 8bv9xAqLbwhGS5FAIWdY2ZLRH7L6+TepfdYSNQJfb5Jy6sf+6HSkl1NBIMqg4wZHzGdD 2wahJ6PaWnB+w91e+k2KEVZ+azg86bQ3sPoJRfrCnFzAL8vF57x993P91+/3/ATOGrxB MZGXVRRfNRiNXP7I7tMMhhXdGR5mtbDUzk4cDSr6awk938ltiNNfW1sUhhv9AuxFvYnt pUxY2UzKUt79iHN2BRMsBdkq7h1ekDebtJFH338y980hNCgLYYj696AgS/psP6VzwOHa nFNg== X-Gm-Message-State: AHYfb5hLZrw/55YiWqAmm6W0fmVbpkswjjdrT4FN0YUegCjgADAUqrus mAZiLW3dnAA32xzm X-Google-Smtp-Source: ADKCNb58TOokpWAYEx0vCY5GPAW1wlyZe4dC4Ll3Qu6xpwF7djVXahll6hdJFhNC4txWRrDXHs1uqg== X-Received: by 10.84.216.93 with SMTP id f29mr1466095plj.223.1503938299464; Mon, 28 Aug 2017 09:38:19 -0700 (PDT) Received: from localhost.localdomain ([124.123.70.3]) by smtp.gmail.com with ESMTPSA id n66sm1935015pfi.44.2017.08.28.09.38.17 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 28 Aug 2017 09:38:19 -0700 (PDT) From: Subbaraya Sundeep To: qemu-devel@nongnu.org, qemu-arm@nongnu.org Cc: peter.maydell@linaro.org, crosthwaite.peter@gmail.com, alistair23@gmail.com, f4bug@amsat.org, Subbaraya Sundeep Date: Mon, 28 Aug 2017 22:07:59 +0530 Message-Id: <1503938283-12404-2-git-send-email-sundeep.lkml@gmail.com> X-Mailer: git-send-email 2.5.0 In-Reply-To: <1503938283-12404-1-git-send-email-sundeep.lkml@gmail.com> References: <1503938283-12404-1-git-send-email-sundeep.lkml@gmail.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::244 Subject: [Qemu-arm] [Qemu devel v7 PATCH 1/5] msf2: Add Smartfusion2 System timer X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 28 Aug 2017 16:38:29 -0000 Modelled System Timer in Microsemi's Smartfusion2 Soc. Timer has two 32bit down counters and two interrupts. Signed-off-by: Subbaraya Sundeep --- hw/timer/Makefile.objs | 1 + hw/timer/mss-timer.c | 289 +++++++++++++++++++++++++++++++++++++++++++ include/hw/timer/mss-timer.h | 64 ++++++++++ 3 files changed, 354 insertions(+) create mode 100644 hw/timer/mss-timer.c create mode 100644 include/hw/timer/mss-timer.h diff --git a/hw/timer/Makefile.objs b/hw/timer/Makefile.objs index 15cce1c..8c19eac 100644 --- a/hw/timer/Makefile.objs +++ b/hw/timer/Makefile.objs @@ -42,3 +42,4 @@ common-obj-$(CONFIG_ASPEED_SOC) += aspeed_timer.o common-obj-$(CONFIG_SUN4V_RTC) += sun4v-rtc.o common-obj-$(CONFIG_CMSDK_APB_TIMER) += cmsdk-apb-timer.o +common-obj-$(CONFIG_MSF2) += mss-timer.o diff --git a/hw/timer/mss-timer.c b/hw/timer/mss-timer.c new file mode 100644 index 0000000..60f1213 --- /dev/null +++ b/hw/timer/mss-timer.c @@ -0,0 +1,289 @@ +/* + * Block model of System timer present in + * Microsemi's SmartFusion2 and SmartFusion SoCs. + * + * Copyright (c) 2017 Subbaraya Sundeep . + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#include "qemu/osdep.h" +#include "qemu/main-loop.h" +#include "qemu/log.h" +#include "hw/timer/mss-timer.h" + +#ifndef MSS_TIMER_ERR_DEBUG +#define MSS_TIMER_ERR_DEBUG 0 +#endif + +#define DB_PRINT_L(lvl, fmt, args...) do { \ + if (MSS_TIMER_ERR_DEBUG >= lvl) { \ + qemu_log("%s: " fmt "\n", __func__, ## args); \ + } \ +} while (0); + +#define DB_PRINT(fmt, args...) DB_PRINT_L(1, fmt, ## args) + +#define R_TIM_VAL 0 +#define R_TIM_LOADVAL 1 +#define R_TIM_BGLOADVAL 2 +#define R_TIM_CTRL 3 +#define R_TIM_RIS 4 +#define R_TIM_MIS 5 + +#define TIMER_CTRL_ENBL (1 << 0) +#define TIMER_CTRL_ONESHOT (1 << 1) +#define TIMER_CTRL_INTR (1 << 2) +#define TIMER_RIS_ACK (1 << 0) +#define TIMER_RST_CLR (1 << 6) +#define TIMER_MODE (1 << 0) + +static void timer_update_irq(struct Msf2Timer *st) +{ + bool isr, ier; + + isr = !!(st->regs[R_TIM_RIS] & TIMER_RIS_ACK); + ier = !!(st->regs[R_TIM_CTRL] & TIMER_CTRL_INTR); + qemu_set_irq(st->irq, (ier && isr)); +} + +static void timer_update(struct Msf2Timer *st) +{ + uint64_t count; + + if (!(st->regs[R_TIM_CTRL] & TIMER_CTRL_ENBL)) { + ptimer_stop(st->ptimer); + return; + } + + count = st->regs[R_TIM_LOADVAL]; + ptimer_set_limit(st->ptimer, count, 1); + ptimer_run(st->ptimer, 1); +} + +static uint64_t +timer_read(void *opaque, hwaddr offset, unsigned int size) +{ + MSSTimerState *t = opaque; + hwaddr addr; + struct Msf2Timer *st; + uint32_t ret = 0; + int timer = 0; + int isr; + int ier; + + addr = offset >> 2; + /* + * Two independent timers has same base address. + * Based on address passed figure out which timer is being used. + */ + if ((addr >= R_TIM1_MAX) && (addr < NUM_TIMERS * R_TIM1_MAX)) { + timer = 1; + addr -= R_TIM1_MAX; + } + + st = &t->timers[timer]; + + switch (addr) { + case R_TIM_VAL: + ret = ptimer_get_count(st->ptimer); + break; + + case R_TIM_MIS: + isr = !!(st->regs[R_TIM_RIS] & TIMER_RIS_ACK); + ier = !!(st->regs[R_TIM_CTRL] & TIMER_CTRL_INTR); + ret = ier & isr; + break; + + default: + if (addr < R_TIM1_MAX) { + ret = st->regs[addr]; + } else { + qemu_log_mask(LOG_GUEST_ERROR, + TYPE_MSS_TIMER": 64-bit mode not supported\n"); + return ret; + } + break; + } + + DB_PRINT("timer=%d 0x%" HWADDR_PRIx "=0x%" PRIx32, timer, offset, + ret); + return ret; +} + +static void +timer_write(void *opaque, hwaddr offset, + uint64_t val64, unsigned int size) +{ + MSSTimerState *t = opaque; + hwaddr addr; + struct Msf2Timer *st; + int timer = 0; + uint32_t value = val64; + + addr = offset >> 2; + /* + * Two independent timers has same base address. + * Based on addr passed figure out which timer is being used. + */ + if ((addr >= R_TIM1_MAX) && (addr < NUM_TIMERS * R_TIM1_MAX)) { + timer = 1; + addr -= R_TIM1_MAX; + } + + st = &t->timers[timer]; + + DB_PRINT("addr=0x%" HWADDR_PRIx " val=0x%" PRIx32 " (timer=%d)", offset, + value, timer); + + switch (addr) { + case R_TIM_CTRL: + st->regs[R_TIM_CTRL] = value; + timer_update(st); + break; + + case R_TIM_RIS: + if (value & TIMER_RIS_ACK) { + st->regs[R_TIM_RIS] &= ~TIMER_RIS_ACK; + } + break; + + case R_TIM_LOADVAL: + st->regs[R_TIM_LOADVAL] = value; + if (st->regs[R_TIM_CTRL] & TIMER_CTRL_ENBL) { + timer_update(st); + } + break; + + case R_TIM_BGLOADVAL: + st->regs[R_TIM_BGLOADVAL] = value; + st->regs[R_TIM_LOADVAL] = value; + break; + + case R_TIM_VAL: + case R_TIM_MIS: + break; + + default: + if (addr < R_TIM1_MAX) { + st->regs[addr] = value; + } else { + qemu_log_mask(LOG_GUEST_ERROR, + TYPE_MSS_TIMER": 64-bit mode not supported\n"); + return; + } + break; + } + timer_update_irq(st); +} + +static const MemoryRegionOps timer_ops = { + .read = timer_read, + .write = timer_write, + .endianness = DEVICE_NATIVE_ENDIAN, + .valid = { + .min_access_size = 1, + .max_access_size = 4 + } +}; + +static void timer_hit(void *opaque) +{ + struct Msf2Timer *st = opaque; + + st->regs[R_TIM_RIS] |= TIMER_RIS_ACK; + + if (!(st->regs[R_TIM_CTRL] & TIMER_CTRL_ONESHOT)) { + timer_update(st); + } + timer_update_irq(st); +} + +static void mss_timer_init(Object *obj) +{ + MSSTimerState *t = MSS_TIMER(obj); + int i; + + /* Init all the ptimers. */ + for (i = 0; i < NUM_TIMERS; i++) { + struct Msf2Timer *st = &t->timers[i]; + + st->bh = qemu_bh_new(timer_hit, st); + st->ptimer = ptimer_init(st->bh, PTIMER_POLICY_DEFAULT); + ptimer_set_freq(st->ptimer, t->freq_hz); + sysbus_init_irq(SYS_BUS_DEVICE(obj), &st->irq); + } + + memory_region_init_io(&t->mmio, OBJECT(t), &timer_ops, t, TYPE_MSS_TIMER, + NUM_TIMERS * R_TIM1_MAX * 4); + sysbus_init_mmio(SYS_BUS_DEVICE(obj), &t->mmio); +} + +static const VMStateDescription vmstate_timers = { + .name = "mss-timer-block", + .version_id = 1, + .minimum_version_id = 1, + .fields = (VMStateField[]) { + VMSTATE_PTIMER(ptimer, struct Msf2Timer), + VMSTATE_UINT32_ARRAY(regs, struct Msf2Timer, R_TIM1_MAX), + VMSTATE_END_OF_LIST() + } +}; + +static const VMStateDescription vmstate_mss_timer = { + .name = TYPE_MSS_TIMER, + .version_id = 1, + .minimum_version_id = 1, + .fields = (VMStateField[]) { + VMSTATE_UINT32(freq_hz, MSSTimerState), + VMSTATE_STRUCT_ARRAY(timers, MSSTimerState, NUM_TIMERS, 0, + vmstate_timers, struct Msf2Timer), + VMSTATE_END_OF_LIST() + } +}; + +static Property mss_timer_properties[] = { + /* Libero GUI shows 100Mhz as default for clocks */ + DEFINE_PROP_UINT32("clock-frequency", MSSTimerState, freq_hz, + 100 * 1000000), + DEFINE_PROP_END_OF_LIST(), +}; + +static void mss_timer_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + + dc->props = mss_timer_properties; + dc->vmsd = &vmstate_mss_timer; +} + +static const TypeInfo mss_timer_info = { + .name = TYPE_MSS_TIMER, + .parent = TYPE_SYS_BUS_DEVICE, + .instance_size = sizeof(MSSTimerState), + .instance_init = mss_timer_init, + .class_init = mss_timer_class_init, +}; + +static void mss_timer_register_types(void) +{ + type_register_static(&mss_timer_info); +} + +type_init(mss_timer_register_types) diff --git a/include/hw/timer/mss-timer.h b/include/hw/timer/mss-timer.h new file mode 100644 index 0000000..d15d173 --- /dev/null +++ b/include/hw/timer/mss-timer.h @@ -0,0 +1,64 @@ +/* + * Microsemi SmartFusion2 Timer. + * + * Copyright (c) 2017 Subbaraya Sundeep + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#ifndef HW_MSS_TIMER_H +#define HW_MSS_TIMER_H + +#include "hw/sysbus.h" +#include "hw/ptimer.h" + +#define TYPE_MSS_TIMER "mss-timer" +#define MSS_TIMER(obj) OBJECT_CHECK(MSSTimerState, \ + (obj), TYPE_MSS_TIMER) + +/* + * There are two 32-bit down counting timers. + * Timers 1 and 2 can be concatenated into a single 64-bit Timer + * that operates either in Periodic mode or in One-shot mode. + * Writing 1 to the TIM64_MODE register bit 0 sets the Timers in 64-bit mode. + * In 64-bit mode, writing to the 32-bit registers has no effect. + * Similarly, in 32-bit mode, writing to the 64-bit mode registers + * has no effect. Only two 32-bit timers are supported currently. + */ +#define NUM_TIMERS 2 + +#define R_TIM1_MAX 6 + +struct Msf2Timer { + QEMUBH *bh; + ptimer_state *ptimer; + + uint32_t regs[R_TIM1_MAX]; + qemu_irq irq; +}; + +typedef struct MSSTimerState { + SysBusDevice parent_obj; + + MemoryRegion mmio; + uint32_t freq_hz; + struct Msf2Timer timers[NUM_TIMERS]; +} MSSTimerState; + +#endif /* HW_MSS_TIMER_H */ -- 2.5.0 From MAILER-DAEMON Mon Aug 28 12:38:36 2017 Received: from list by lists.gnu.org with archive (Exim 4.71) id 1dmN3b-00026I-Vt for mharc-qemu-arm@gnu.org; Mon, 28 Aug 2017 12:38:36 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:45208) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dmN3V-00020g-5c for qemu-arm@nongnu.org; Mon, 28 Aug 2017 12:38:33 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dmN3T-0003Pi-BT for qemu-arm@nongnu.org; Mon, 28 Aug 2017 12:38:29 -0400 Received: from mail-pf0-x243.google.com ([2607:f8b0:400e:c00::243]:35399) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1dmN3P-00035t-8N; Mon, 28 Aug 2017 12:38:23 -0400 Received: by mail-pf0-x243.google.com with SMTP id g13so639906pfm.2; Mon, 28 Aug 2017 09:38:23 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=BQAgqzIMWsJa3UCJkaq93RV6GILFbBbQfxQBdsI78B0=; b=CXW0FBZ6NVdhp4q4Uwdk+n/IofJnByK2bgtsH896G51nkwXj+8oednGPEYODnCiHdk EpUg2LLqG89cqiGNf8qyrXcH6fo4+f+gTbhpoTMlgeaja3JbWuQdNPm+xzplwKnhOIdT I41bQdlTWMb/lnFmbAzfnmwKpMDWu+tnruqlZpdB94RmeCNx3u39APqS0dNQlRFYQTCj NuE2t+315Flsg5C1dtRbC+PNM1+ouK4JNQUOIrGZ788b+j3BTj3MYcmODJnKe1+H0N0z V7vsqd5Bnbc/kPxkFf785TjqlR9uwFMSgw/9n/0CFEPaQJGZGCI6qDtxdZyqZ0l8jxr9 pRLA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=BQAgqzIMWsJa3UCJkaq93RV6GILFbBbQfxQBdsI78B0=; b=eV2+4y3I24ZStURMVXQMHJ87IehY0/ljqfWunxApKJLvwnTUeofdQeOywTwKLK93e0 d6WexjBH9IJcsniekPP4C8HZxWSGNIy0n/REpSYXp3/j2HX+xLNvu2APA0k/1uEuqYxy v9S6xdeWLAZh/Wt4ToFxMWwsHtK28cl5UfcE6FymuqafoWbP1Q9EzX4sYBo/Ta+4DNca tcfh/grkYoZDFSZ6rF45og5jFML5CJFn6BzBkh+mU6rS7dwfnEr/1V1qNC5aAFLTjkXN tonCHqsC3aknWBKEyNw9/v2X9wm7BC8gsRq1S7Vr/APexMxhlnzQq8CbFjGQt28/Z4FS pJAA== X-Gm-Message-State: AHYfb5joMJ1qi/2kDxqlJHUnZWvUmU8T7YRraADNqx1Vv9yoIgkS55Uf KkB2MP5m3B6ZB+p/ X-Google-Smtp-Source: ADKCNb4vl0bVTTSfJ71wvmOaNPGwjYVWwcos+CRt6v/GaOtPeV2SJseWkG8RC/+Op33lzugxjvQ/3g== X-Received: by 10.84.129.47 with SMTP id 44mr1480087plb.40.1503938302107; Mon, 28 Aug 2017 09:38:22 -0700 (PDT) Received: from localhost.localdomain ([124.123.70.3]) by smtp.gmail.com with ESMTPSA id n66sm1935015pfi.44.2017.08.28.09.38.19 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 28 Aug 2017 09:38:21 -0700 (PDT) From: Subbaraya Sundeep To: qemu-devel@nongnu.org, qemu-arm@nongnu.org Cc: peter.maydell@linaro.org, crosthwaite.peter@gmail.com, alistair23@gmail.com, f4bug@amsat.org, Subbaraya Sundeep Date: Mon, 28 Aug 2017 22:08:00 +0530 Message-Id: <1503938283-12404-3-git-send-email-sundeep.lkml@gmail.com> X-Mailer: git-send-email 2.5.0 In-Reply-To: <1503938283-12404-1-git-send-email-sundeep.lkml@gmail.com> References: <1503938283-12404-1-git-send-email-sundeep.lkml@gmail.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::243 Subject: [Qemu-arm] [Qemu devel v7 PATCH 2/5] msf2: Microsemi Smartfusion2 System Register block X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 28 Aug 2017 16:38:33 -0000 Added Sytem register block of Smartfusion2. This block has PLL registers which are accessed by guest. Signed-off-by: Subbaraya Sundeep --- hw/misc/Makefile.objs | 1 + hw/misc/msf2-sysreg.c | 199 ++++++++++++++++++++++++++++++++++++++++++ include/hw/misc/msf2-sysreg.h | 78 +++++++++++++++++ 3 files changed, 278 insertions(+) create mode 100644 hw/misc/msf2-sysreg.c create mode 100644 include/hw/misc/msf2-sysreg.h diff --git a/hw/misc/Makefile.objs b/hw/misc/Makefile.objs index 29fb922..e8f0a02 100644 --- a/hw/misc/Makefile.objs +++ b/hw/misc/Makefile.objs @@ -59,3 +59,4 @@ obj-$(CONFIG_HYPERV_TESTDEV) += hyperv_testdev.o obj-$(CONFIG_AUX) += auxbus.o obj-$(CONFIG_ASPEED_SOC) += aspeed_scu.o aspeed_sdmc.o obj-y += mmio_interface.o +obj-$(CONFIG_MSF2) += msf2-sysreg.o diff --git a/hw/misc/msf2-sysreg.c b/hw/misc/msf2-sysreg.c new file mode 100644 index 0000000..2aeb555 --- /dev/null +++ b/hw/misc/msf2-sysreg.c @@ -0,0 +1,199 @@ +/* + * System Register block model of Microsemi SmartFusion2. + * + * Copyright (c) 2017 Subbaraya Sundeep + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version + * 2 of the License, or (at your option) any later version. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#include "qemu/osdep.h" +#include "qemu/log.h" +#include "hw/misc/msf2-sysreg.h" + +#ifndef MSF2_SYSREG_ERR_DEBUG +#define MSF2_SYSREG_ERR_DEBUG 0 +#endif + +#define DB_PRINT_L(lvl, fmt, args...) do { \ + if (MSF2_SYSREG_ERR_DEBUG >= lvl) { \ + qemu_log("%s: " fmt "\n", __func__, ## args); \ + } \ +} while (0); + +#define DB_PRINT(fmt, args...) DB_PRINT_L(1, fmt, ## args) + +static inline int msf2_divbits(uint32_t div) +{ + int ret = 0; + + switch (div) { + case 1: + ret = 0; + break; + case 2: + ret = 1; + break; + case 4: + ret = 2; + break; + case 8: + ret = 4; + break; + case 16: + ret = 5; + break; + case 32: + ret = 6; + break; + default: + break; + } + + return ret; +} + +static void msf2_sysreg_reset(DeviceState *d) +{ + MSF2SysregState *s = MSF2_SYSREG(d); + + DB_PRINT("RESET"); + + s->regs[MSSDDR_PLL_STATUS_LOW_CR] = 0x021A2358; + s->regs[MSSDDR_PLL_STATUS] = 0x3; + s->regs[MSSDDR_FACC1_CR] = msf2_divbits(s->apb0div) << 5 | + msf2_divbits(s->apb1div) << 2; +} + +static uint64_t msf2_sysreg_read(void *opaque, hwaddr offset, + unsigned size) +{ + MSF2SysregState *s = opaque; + uint32_t ret = 0; + + offset >>= 2; + if (offset < ARRAY_SIZE(s->regs)) { + ret = s->regs[offset]; + DB_PRINT("addr: 0x%08" HWADDR_PRIx " data: 0x%08" PRIx32, + offset << 2, ret); + } else { + qemu_log_mask(LOG_GUEST_ERROR, + "%s: Bad offset 0x%08" HWADDR_PRIx "\n", __func__, + offset << 2); + } + + return ret; +} + +static void msf2_sysreg_write(void *opaque, hwaddr offset, + uint64_t val, unsigned size) +{ + MSF2SysregState *s = (MSF2SysregState *)opaque; + uint32_t newval = val; + uint32_t oldval; + + DB_PRINT("addr: 0x%08" HWADDR_PRIx " data: 0x%08" PRIx64, + offset, val); + + offset >>= 2; + + switch (offset) { + case MSSDDR_PLL_STATUS: + break; + + case ESRAM_CR: + oldval = s->regs[ESRAM_CR]; + if (oldval ^ newval) { + qemu_log_mask(LOG_GUEST_ERROR, + TYPE_MSF2_SYSREG": eSRAM remapping not supported\n"); + } + break; + + case DDR_CR: + oldval = s->regs[DDR_CR]; + if (oldval ^ newval) { + qemu_log_mask(LOG_GUEST_ERROR, + TYPE_MSF2_SYSREG": DDR remapping not supported\n"); + } + break; + + case ENVM_REMAP_BASE_CR: + oldval = s->regs[ENVM_REMAP_BASE_CR]; + if (oldval ^ newval) { + qemu_log_mask(LOG_GUEST_ERROR, + TYPE_MSF2_SYSREG": eNVM remapping not supported\n"); + } + break; + + default: + if (offset < ARRAY_SIZE(s->regs)) { + s->regs[offset] = val; + } else { + qemu_log_mask(LOG_GUEST_ERROR, + "%s: Bad offset 0x%08" HWADDR_PRIx "\n", __func__, + offset << 2); + } + break; + } +} + +static const MemoryRegionOps sysreg_ops = { + .read = msf2_sysreg_read, + .write = msf2_sysreg_write, + .endianness = DEVICE_NATIVE_ENDIAN, +}; + +static void msf2_sysreg_init(Object *obj) +{ + MSF2SysregState *s = MSF2_SYSREG(obj); + + memory_region_init_io(&s->iomem, obj, &sysreg_ops, s, TYPE_MSF2_SYSREG, + MSF2_SYSREG_MMIO_SIZE); + sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->iomem); +} + +static const VMStateDescription vmstate_msf2_sysreg = { + .name = TYPE_MSF2_SYSREG, + .version_id = 1, + .minimum_version_id = 1, + .fields = (VMStateField[]) { + VMSTATE_UINT32_ARRAY(regs, MSF2SysregState, MSF2_SYSREG_MMIO_SIZE / 4), + VMSTATE_END_OF_LIST() + } +}; + +static Property msf2_sysreg_properties[] = { + /* default divisors in Libero GUI */ + DEFINE_PROP_UINT32("apb0divisor", MSF2SysregState, apb0div, 2), + DEFINE_PROP_UINT32("apb1divisor", MSF2SysregState, apb1div, 2), + DEFINE_PROP_END_OF_LIST(), +}; + +static void msf2_sysreg_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + + dc->vmsd = &vmstate_msf2_sysreg; + dc->reset = msf2_sysreg_reset; + dc->props = msf2_sysreg_properties; +} + +static const TypeInfo msf2_sysreg_info = { + .name = TYPE_MSF2_SYSREG, + .parent = TYPE_SYS_BUS_DEVICE, + .class_init = msf2_sysreg_class_init, + .instance_size = sizeof(MSF2SysregState), + .instance_init = msf2_sysreg_init, +}; + +static void msf2_sysreg_register_types(void) +{ + type_register_static(&msf2_sysreg_info); +} + +type_init(msf2_sysreg_register_types) diff --git a/include/hw/misc/msf2-sysreg.h b/include/hw/misc/msf2-sysreg.h new file mode 100644 index 0000000..f39cc41 --- /dev/null +++ b/include/hw/misc/msf2-sysreg.h @@ -0,0 +1,78 @@ +/* + * Microsemi SmartFusion2 SYSREG + * + * Copyright (c) 2017 Subbaraya Sundeep + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#ifndef HW_MSF2_SYSREG_H +#define HW_MSF2_SYSREG_H + +#include "hw/sysbus.h" + +enum { + ESRAM_CR = 0x00 / 4, + ESRAM_MAX_LAT, + DDR_CR, + ENVM_CR, + ENVM_REMAP_BASE_CR, + ENVM_REMAP_FAB_CR, + CC_CR, + CC_REGION_CR, + CC_LOCK_BASE_ADDR_CR, + CC_FLUSH_INDX_CR, + DDRB_BUF_TIMER_CR, + DDRB_NB_ADDR_CR, + DDRB_NB_SIZE_CR, + DDRB_CR, + + SOFT_RESET_CR = 0x48 / 4, + M3_CR, + + GPIO_SYSRESET_SEL_CR = 0x58 / 4, + + MDDR_CR = 0x60 / 4, + + MSSDDR_PLL_STATUS_LOW_CR = 0x90 / 4, + MSSDDR_PLL_STATUS_HIGH_CR, + MSSDDR_FACC1_CR, + MSSDDR_FACC2_CR, + + MSSDDR_PLL_STATUS = 0x150 / 4, + +}; + +#define MSF2_SYSREG_MMIO_SIZE 0x300 + +#define TYPE_MSF2_SYSREG "msf2-sysreg" +#define MSF2_SYSREG(obj) OBJECT_CHECK(MSF2SysregState, (obj), TYPE_MSF2_SYSREG) + +typedef struct MSF2SysregState { + SysBusDevice parent_obj; + + MemoryRegion iomem; + + uint32_t apb0div; + uint32_t apb1div; + + uint32_t regs[MSF2_SYSREG_MMIO_SIZE / 4]; +} MSF2SysregState; + +#endif /* HW_MSF2_SYSREG_H */ -- 2.5.0 From MAILER-DAEMON Mon Aug 28 12:38:38 2017 Received: from list by lists.gnu.org with archive (Exim 4.71) id 1dmN3e-00028Q-Bi for mharc-qemu-arm@gnu.org; Mon, 28 Aug 2017 12:38:38 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:45267) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dmN3b-00025f-8a for qemu-arm@nongnu.org; Mon, 28 Aug 2017 12:38:36 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dmN3a-0003sh-3W for qemu-arm@nongnu.org; Mon, 28 Aug 2017 12:38:35 -0400 Received: from mail-pg0-x244.google.com ([2607:f8b0:400e:c05::244]:32803) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1dmN3X-0003eB-87; Mon, 28 Aug 2017 12:38:31 -0400 Received: by mail-pg0-x244.google.com with SMTP id m15so749568pgc.0; Mon, 28 Aug 2017 09:38:31 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=yBMbxk0owmgYZeQbWPEv6cWTGrUk61tkgpxfm3/VIFg=; b=qIj7RppnyrVEDm3QRwAt6ol03ZjSUY21TZgdNcevNnaGmc9TziT2EUq7VoSs8wVQK2 +y1N3lpCR9punJDD/UGnz7NaWlyC/Aszh4NbXPgOnXmT/T+9QHG2lROsXUdWCvSD8qYy BziOLPAzt97H2hiNEnAIioUEV7fex+vzIYRizsHVaoZ3hdPUVqpGdCdGhSK+k85AK8iv IZBZ8zCcLn1ArkLcA5e3xAKxkGfzjtnBjRm/30swcZdJtD6XOTviYTExtOhOz00Vg7dF 5ajzSpis5pOB0uJx6zWKRb7hSQYblpr/pp5Wbn3+ZGZCpIAie8WQrBXHjkv4L93CFrJA 0CCg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=yBMbxk0owmgYZeQbWPEv6cWTGrUk61tkgpxfm3/VIFg=; b=GaFht+9PBhPtLfsov2Hgt81rNZNzLSVQxjx2t/wpAoguU32AwF5MQSNofleb/8wnCI GWND3HTqQrZ2mYks0/XJhLFMpGvSRrMYQ2kyuGApgsXL1ZwY9EzzktHrocs/43/P4Uc7 gMZZXpHc4RZ7cvvam3l36kZgc56we6za7afXyPLXqxaUQXBNdjr7rvtu9mY6eMuwWRVR SvoH9vDiB89JV7T7mkWKKNvWaPIzr5TKel1NmyO+uoAD1kB6bYeNj48lbH3S6Yme89sA AnLx7hpIrUiP1vYE/yNOJO3Q3NqyhStvfiwpyAfRw/0LpzBLf9qVR9+o3sYEV66nJloh +SOQ== X-Gm-Message-State: AHYfb5jpwtE2f99d/mAy3IozSUT75DvZVOAEE4Jy7y4/A4XyKiPf/x8C hZsbqnodBPze10hw X-Google-Smtp-Source: ADKCNb5UNyYa3A+HgdATUc4z6aTTA9b79/HKmuoCXnuFZ0pMOoddZ5oR08zppTGrseGUDMguhXYhhw== X-Received: by 10.84.238.134 with SMTP id v6mr1432828plk.187.1503938310221; Mon, 28 Aug 2017 09:38:30 -0700 (PDT) Received: from localhost.localdomain ([124.123.70.3]) by smtp.gmail.com with ESMTPSA id n66sm1935015pfi.44.2017.08.28.09.38.27 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 28 Aug 2017 09:38:29 -0700 (PDT) From: Subbaraya Sundeep To: qemu-devel@nongnu.org, qemu-arm@nongnu.org Cc: peter.maydell@linaro.org, crosthwaite.peter@gmail.com, alistair23@gmail.com, f4bug@amsat.org, Subbaraya Sundeep Date: Mon, 28 Aug 2017 22:08:03 +0530 Message-Id: <1503938283-12404-6-git-send-email-sundeep.lkml@gmail.com> X-Mailer: git-send-email 2.5.0 In-Reply-To: <1503938283-12404-1-git-send-email-sundeep.lkml@gmail.com> References: <1503938283-12404-1-git-send-email-sundeep.lkml@gmail.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::244 Subject: [Qemu-arm] [Qemu devel v7 PATCH 5/5] msf2: Add Emcraft's Smartfusion2 SOM kit X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 28 Aug 2017 16:38:36 -0000 Emulated Emcraft's Smartfusion2 System On Module starter kit. Signed-off-by: Subbaraya Sundeep --- hw/arm/Makefile.objs | 2 +- hw/arm/msf2-som.c | 94 ++++++++++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 95 insertions(+), 1 deletion(-) create mode 100644 hw/arm/msf2-som.c diff --git a/hw/arm/Makefile.objs b/hw/arm/Makefile.objs index df36a03..e81a7dc 100644 --- a/hw/arm/Makefile.objs +++ b/hw/arm/Makefile.objs @@ -19,4 +19,4 @@ obj-$(CONFIG_FSL_IMX31) += fsl-imx31.o kzm.o obj-$(CONFIG_FSL_IMX6) += fsl-imx6.o sabrelite.o obj-$(CONFIG_ASPEED_SOC) += aspeed_soc.o aspeed.o obj-$(CONFIG_MPS2) += mps2.o -obj-$(CONFIG_MSF2) += msf2-soc.o +obj-$(CONFIG_MSF2) += msf2-soc.o msf2-som.o diff --git a/hw/arm/msf2-som.c b/hw/arm/msf2-som.c new file mode 100644 index 0000000..fd89ba9 --- /dev/null +++ b/hw/arm/msf2-som.c @@ -0,0 +1,94 @@ +/* + * SmartFusion2 SOM starter kit(from Emcraft) emulation. + * + * Copyright (c) 2017 Subbaraya Sundeep + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#include "qemu/osdep.h" +#include "qapi/error.h" +#include "hw/boards.h" +#include "hw/arm/arm.h" +#include "exec/address-spaces.h" +#include "qemu/cutils.h" +#include "hw/arm/msf2-soc.h" + +#define DDR_BASE_ADDRESS 0xA0000000 +#define DDR_SIZE (64 * M_BYTE) + +#define M2S010_ENVM_SIZE (256 * K_BYTE) +#define M2S010_ESRAM_SIZE (64 * K_BYTE) + +static void emcraft_sf2_init(MachineState *machine) +{ + DeviceState *dev; + DeviceState *spi_flash; + MSF2State *soc; + DriveInfo *dinfo = drive_get_next(IF_MTD); + qemu_irq cs_line; + SSIBus *spi_bus; + MemoryRegion *sysmem = get_system_memory(); + MemoryRegion *ddr = g_new(MemoryRegion, 1); + + memory_region_init_ram(ddr, NULL, "ddr-ram", DDR_SIZE, + &error_fatal); + memory_region_add_subregion(sysmem, DDR_BASE_ADDRESS, ddr); + + dev = qdev_create(NULL, TYPE_MSF2_SOC); + qdev_prop_set_string(dev, "part-name", "M2S010"); + qdev_prop_set_uint64(dev, "eNVM-size", M2S010_ENVM_SIZE); + qdev_prop_set_uint64(dev, "eSRAM-size", M2S010_ESRAM_SIZE); + + /* + * CPU clock and peripheral clocks(APB0, APB1)are configurable + * in Libero. CPU clock is divided by APB0 and APB1 divisors for + * peripherals. Emcraft's SoM kit comes with these settings by default. + */ + qdev_prop_set_uint32(dev, "m3clk", 142 * 1000000); + qdev_prop_set_uint32(dev, "apb0div", 2); + qdev_prop_set_uint32(dev, "apb1div", 2); + + object_property_set_bool(OBJECT(dev), true, "realized", &error_fatal); + + soc = MSF2_SOC(dev); + + /* Attach SPI flash to SPI0 controller */ + spi_bus = (SSIBus *)qdev_get_child_bus(dev, "spi0"); + spi_flash = ssi_create_slave_no_init(spi_bus, "s25sl12801"); + qdev_prop_set_uint8(spi_flash, "spansion-cr2nv", 1); + if (dinfo) { + qdev_prop_set_drive(spi_flash, "drive", blk_by_legacy_dinfo(dinfo), + &error_fatal); + } + qdev_init_nofail(spi_flash); + cs_line = qdev_get_gpio_in_named(spi_flash, SSI_GPIO_CS, 0); + sysbus_connect_irq(SYS_BUS_DEVICE(&soc->spi[0]), 1, cs_line); + + armv7m_load_kernel(ARM_CPU(first_cpu), machine->kernel_filename, + soc->envm_size); +} + +static void emcraft_sf2_machine_init(MachineClass *mc) +{ + mc->desc = "SmartFusion2 SOM kit from Emcraft"; + mc->init = emcraft_sf2_init; +} + +DEFINE_MACHINE("emcraft-sf2", emcraft_sf2_machine_init) -- 2.5.0 From MAILER-DAEMON Mon Aug 28 12:38:38 2017 Received: from list by lists.gnu.org with archive (Exim 4.71) id 1dmN3e-00028a-I8 for mharc-qemu-arm@gnu.org; Mon, 28 Aug 2017 12:38:38 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:45256) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dmN3a-000257-HT for qemu-arm@nongnu.org; Mon, 28 Aug 2017 12:38:36 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dmN3Y-0003kE-6x for qemu-arm@nongnu.org; Mon, 28 Aug 2017 12:38:34 -0400 Received: from mail-pf0-x241.google.com ([2607:f8b0:400e:c00::241]:36114) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1dmN3S-0003IP-3F; Mon, 28 Aug 2017 12:38:26 -0400 Received: by mail-pf0-x241.google.com with SMTP id k3so635423pfc.3; Mon, 28 Aug 2017 09:38:25 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=CZt6smooU+cMTU7VsxO7IJ0GNR4+qZuX1H3rZD8U3uo=; b=tTcGsDqLoRAURyTnbozm+vl6Ab9s59szVSHsssJoU0z3mVt0LWCMhUXD5uzx2AjvUV gmB9xMK/aYe8Fb2VDFRRrEomrQJh4AANoACKY4KxdzbCC7vTefbEvn0O+6rPLK5K5Wgl 14GIvg1lI1BauLTwknqP/MN0MjZ0ytp9/OiWb32s5tVnzKczcIEoS5nxBBH1Kg36GKIs +sb6JbyYIBVpwGIcqIaoxt/2oBRvQUI71ggSZ2r48bGPykllNgymvmt7Dg4QlLu09muJ uEGFQ9vZ29PO0GGOd8/x7hIojfka9aVP6sMKaxBldQR/GlfnEqxnzR2jStDeFNjnup2l qcyw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=CZt6smooU+cMTU7VsxO7IJ0GNR4+qZuX1H3rZD8U3uo=; b=Bf8GbdYI/hleSn1K8OPObg5+gYeEfEoac6FZPaCI3ICpwMhTa5oZr/b3gIjB7YyLKT O4iE/2/uFqVRk4iPJU/b5wmrfDUb6d2zJ5rJHXu/Ufg37s00MavkesDhHq8fCNfwwwIv s22wycxZf9IZjDosvsZzX+naIO4zxZAMmafwRErgtQrWB7xIwgaEwioqWJXe/PhPZULv Srg7k7o1xMrnDW3ZvygYqCsmLeISCVUJ6hyFBvqPEPqyq2UrrzKkDmeTy5hj6raTRfLg zzjJEB6nHUX0scyij8qFBzXa8jqaX3/RGgyuUQCbaEU2+CMFoz4nyfMM2vRt8VjvvQSW kiEQ== X-Gm-Message-State: AHYfb5jqMh8bjadugBTS9IwTKf489Xy2Ck2qJ6eMaXLZk+tnuHHlk+8l z8kQLZxHTwfXup64 X-Google-Smtp-Source: ADKCNb40pM/Z8COCQ80h27R8BdC9DIgD0hJHQF0sEwBrathU+twmtS/N8vldrtwnemNxr+a88WOaLQ== X-Received: by 10.99.49.194 with SMTP id x185mr1165763pgx.416.1503938304851; Mon, 28 Aug 2017 09:38:24 -0700 (PDT) Received: from localhost.localdomain ([124.123.70.3]) by smtp.gmail.com with ESMTPSA id n66sm1935015pfi.44.2017.08.28.09.38.22 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 28 Aug 2017 09:38:24 -0700 (PDT) From: Subbaraya Sundeep To: qemu-devel@nongnu.org, qemu-arm@nongnu.org Cc: peter.maydell@linaro.org, crosthwaite.peter@gmail.com, alistair23@gmail.com, f4bug@amsat.org, Subbaraya Sundeep Date: Mon, 28 Aug 2017 22:08:01 +0530 Message-Id: <1503938283-12404-4-git-send-email-sundeep.lkml@gmail.com> X-Mailer: git-send-email 2.5.0 In-Reply-To: <1503938283-12404-1-git-send-email-sundeep.lkml@gmail.com> References: <1503938283-12404-1-git-send-email-sundeep.lkml@gmail.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::241 Subject: [Qemu-arm] [Qemu devel v7 PATCH 3/5] msf2: Add Smartfusion2 SPI controller X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 28 Aug 2017 16:38:37 -0000 Modelled Microsemi's Smartfusion2 SPI controller. Signed-off-by: Subbaraya Sundeep --- hw/ssi/Makefile.objs | 1 + hw/ssi/mss-spi.c | 409 +++++++++++++++++++++++++++++++++++++++++++++++ include/hw/ssi/mss-spi.h | 58 +++++++ 3 files changed, 468 insertions(+) create mode 100644 hw/ssi/mss-spi.c create mode 100644 include/hw/ssi/mss-spi.h diff --git a/hw/ssi/Makefile.objs b/hw/ssi/Makefile.objs index 487add2..f5bcc65 100644 --- a/hw/ssi/Makefile.objs +++ b/hw/ssi/Makefile.objs @@ -4,6 +4,7 @@ common-obj-$(CONFIG_XILINX_SPI) += xilinx_spi.o common-obj-$(CONFIG_XILINX_SPIPS) += xilinx_spips.o common-obj-$(CONFIG_ASPEED_SOC) += aspeed_smc.o common-obj-$(CONFIG_STM32F2XX_SPI) += stm32f2xx_spi.o +common-obj-$(CONFIG_MSF2) += mss-spi.o obj-$(CONFIG_OMAP) += omap_spi.o obj-$(CONFIG_IMX) += imx_spi.o diff --git a/hw/ssi/mss-spi.c b/hw/ssi/mss-spi.c new file mode 100644 index 0000000..7209363 --- /dev/null +++ b/hw/ssi/mss-spi.c @@ -0,0 +1,409 @@ +/* + * Block model of SPI controller present in + * Microsemi's SmartFusion2 and SmartFusion SoCs. + * + * Copyright (C) 2017 Subbaraya Sundeep + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#include "qemu/osdep.h" +#include "hw/ssi/mss-spi.h" +#include "qemu/log.h" + +#ifndef MSS_SPI_ERR_DEBUG +#define MSS_SPI_ERR_DEBUG 0 +#endif + +#define DB_PRINT_L(lvl, fmt, args...) do { \ + if (MSS_SPI_ERR_DEBUG >= lvl) { \ + qemu_log("%s: " fmt "\n", __func__, ## args); \ + } \ +} while (0); + +#define DB_PRINT(fmt, args...) DB_PRINT_L(1, fmt, ## args) + +#define FIFO_CAPACITY 32 +#define FIFO_CAPACITY 32 + +#define R_SPI_CONTROL 0 +#define R_SPI_DFSIZE 1 +#define R_SPI_STATUS 2 +#define R_SPI_INTCLR 3 +#define R_SPI_RX 4 +#define R_SPI_TX 5 +#define R_SPI_CLKGEN 6 +#define R_SPI_SS 7 +#define R_SPI_MIS 8 +#define R_SPI_RIS 9 + +#define S_TXDONE (1 << 0) +#define S_RXRDY (1 << 1) +#define S_RXCHOVRF (1 << 2) +#define S_RXFIFOFUL (1 << 4) +#define S_RXFIFOFULNXT (1 << 5) +#define S_RXFIFOEMP (1 << 6) +#define S_RXFIFOEMPNXT (1 << 7) +#define S_TXFIFOFUL (1 << 8) +#define S_TXFIFOFULNXT (1 << 9) +#define S_TXFIFOEMP (1 << 10) +#define S_TXFIFOEMPNXT (1 << 11) +#define S_FRAMESTART (1 << 12) +#define S_SSEL (1 << 13) +#define S_ACTIVE (1 << 14) + +#define C_ENABLE (1 << 0) +#define C_MODE (1 << 1) +#define C_INTRXDATA (1 << 4) +#define C_INTTXDATA (1 << 5) +#define C_INTRXOVRFLO (1 << 6) +#define C_SPS (1 << 26) +#define C_BIGFIFO (1 << 29) +#define C_RESET (1 << 31) + +#define FRAMESZ_MASK 0x1F +#define FMCOUNT_MASK 0x00FFFF00 +#define FMCOUNT_SHIFT 8 + +static void txfifo_reset(MSSSpiState *s) +{ + fifo32_reset(&s->tx_fifo); + + s->regs[R_SPI_STATUS] &= ~S_TXFIFOFUL; + s->regs[R_SPI_STATUS] |= S_TXFIFOEMP; +} + +static void rxfifo_reset(MSSSpiState *s) +{ + fifo32_reset(&s->rx_fifo); + + s->regs[R_SPI_STATUS] &= ~S_RXFIFOFUL; + s->regs[R_SPI_STATUS] |= S_RXFIFOEMP; +} + +static void set_fifodepth(MSSSpiState *s) +{ + unsigned int size = s->regs[R_SPI_DFSIZE] & FRAMESZ_MASK; + + if (size <= 8) { + s->fifo_depth = 32; + } else if (size <= 16) { + s->fifo_depth = 16; + } else if (size <= 32) { + s->fifo_depth = 8; + } else { + s->fifo_depth = 4; + } +} + +static void mss_spi_do_reset(MSSSpiState *s) +{ + memset(s->regs, 0, sizeof s->regs); + s->regs[R_SPI_CONTROL] = 0x80000102; + s->regs[R_SPI_DFSIZE] = 0x4; + s->regs[R_SPI_STATUS] = S_SSEL | S_TXFIFOEMP | S_RXFIFOEMP; + s->regs[R_SPI_CLKGEN] = 0x7; + s->regs[R_SPI_RIS] = 0x0; + + s->fifo_depth = 4; + s->frame_count = 1; + s->enabled = false; + + rxfifo_reset(s); + txfifo_reset(s); +} + +static void update_mis(MSSSpiState *s) +{ + uint32_t reg = s->regs[R_SPI_CONTROL]; + uint32_t tmp; + + /* + * form the Control register interrupt enable bits + * same as RIS, MIS and Interrupt clear registers for simplicity + */ + tmp = ((reg & C_INTRXOVRFLO) >> 4) | ((reg & C_INTRXDATA) >> 3) | + ((reg & C_INTTXDATA) >> 5); + s->regs[R_SPI_MIS] |= tmp & s->regs[R_SPI_RIS]; +} + +static void spi_update_irq(MSSSpiState *s) +{ + int irq; + + update_mis(s); + irq = !!(s->regs[R_SPI_MIS]); + + qemu_set_irq(s->irq, irq); +} + +static void mss_spi_reset(DeviceState *d) +{ + mss_spi_do_reset(MSS_SPI(d)); +} + +static uint64_t +spi_read(void *opaque, hwaddr addr, unsigned int size) +{ + MSSSpiState *s = opaque; + uint32_t ret = 0; + + addr >>= 2; + switch (addr) { + case R_SPI_RX: + s->regs[R_SPI_STATUS] &= ~S_RXFIFOFUL; + s->regs[R_SPI_STATUS] &= ~S_RXCHOVRF; + ret = fifo32_pop(&s->rx_fifo); + if (fifo32_is_empty(&s->rx_fifo)) { + s->regs[R_SPI_STATUS] |= S_RXFIFOEMP; + } + break; + + case R_SPI_MIS: + update_mis(s); + ret = s->regs[R_SPI_MIS]; + break; + + default: + if (addr < ARRAY_SIZE(s->regs)) { + ret = s->regs[addr]; + } else { + qemu_log_mask(LOG_GUEST_ERROR, + "%s: Bad offset 0x%" HWADDR_PRIx "\n", __func__, + addr * 4); + } + break; + } + + DB_PRINT("addr=0x%" HWADDR_PRIx " = 0x%" PRIx32, addr * 4, ret); + spi_update_irq(s); + return ret; +} + +static void assert_cs(MSSSpiState *s) +{ + qemu_set_irq(s->cs_line, 0); +} + +static void deassert_cs(MSSSpiState *s) +{ + qemu_set_irq(s->cs_line, 1); +} + +static void spi_flush_txfifo(MSSSpiState *s) +{ + uint32_t tx; + uint32_t rx; + bool sps = !!(s->regs[R_SPI_CONTROL] & C_SPS); + + /* + * Chip Select(CS) is automatically controlled by this controller. + * If SPS bit is set in Control register then CS is asserted + * until all the frames set in frame count of Control register are + * transferred. If SPS is not set then CS pulses between frames. + * Note that Slave Select register specifies which of the CS line + * has to be controlled automatically by controller. Bits SS[7:1] are for + * masters in FPGA fabric since we model only Microcontroller subsystem + * of Smartfusion2 we control only one CS(SS[0]) line. + */ + while (!fifo32_is_empty(&s->tx_fifo) && s->frame_count) { + assert_cs(s); + + s->regs[R_SPI_STATUS] &= ~(S_TXDONE | S_RXRDY); + + tx = fifo32_pop(&s->tx_fifo); + DB_PRINT("data tx:0x%" PRIx32, tx); + rx = ssi_transfer(s->spi, tx); + DB_PRINT("data rx:0x%" PRIx32, rx); + + if (fifo32_num_used(&s->rx_fifo) == s->fifo_depth) { + s->regs[R_SPI_STATUS] |= S_RXCHOVRF; + s->regs[R_SPI_RIS] |= S_RXCHOVRF; + } else { + fifo32_push(&s->rx_fifo, rx); + s->regs[R_SPI_STATUS] &= ~S_RXFIFOEMP; + if (fifo32_num_used(&s->rx_fifo) == (s->fifo_depth - 1)) { + s->regs[R_SPI_STATUS] |= S_RXFIFOFULNXT; + } else if (fifo32_num_used(&s->rx_fifo) == s->fifo_depth) { + s->regs[R_SPI_STATUS] |= S_RXFIFOFUL; + } + } + s->frame_count--; + if (!sps) { + deassert_cs(s); + } + } + + if (!s->frame_count) { + s->frame_count = (s->regs[R_SPI_CONTROL] & FMCOUNT_MASK) >> + FMCOUNT_SHIFT; + if (sps) { + deassert_cs(s); + } + s->regs[R_SPI_RIS] |= S_TXDONE | S_RXRDY; + s->regs[R_SPI_STATUS] |= S_TXDONE | S_RXRDY; + } +} + +static void spi_write(void *opaque, hwaddr addr, + uint64_t val64, unsigned int size) +{ + MSSSpiState *s = opaque; + uint32_t value = val64; + + DB_PRINT("addr=0x%" HWADDR_PRIx " =0x%" PRIx32, addr, value); + addr >>= 2; + + switch (addr) { + case R_SPI_TX: + /* adding to already full FIFO */ + if (fifo32_num_used(&s->tx_fifo) == s->fifo_depth) { + break; + } + s->regs[R_SPI_STATUS] &= ~S_TXFIFOEMP; + fifo32_push(&s->tx_fifo, value); + if (fifo32_num_used(&s->tx_fifo) == (s->fifo_depth - 1)) { + s->regs[R_SPI_STATUS] |= S_TXFIFOFULNXT; + } else if (fifo32_num_used(&s->tx_fifo) == s->fifo_depth) { + s->regs[R_SPI_STATUS] |= S_TXFIFOFUL; + } + if (s->enabled) { + spi_flush_txfifo(s); + } + break; + + case R_SPI_CONTROL: + s->regs[R_SPI_CONTROL] = value; + if (value & C_BIGFIFO) { + set_fifodepth(s); + } else { + s->fifo_depth = 4; + } + s->enabled = value & C_ENABLE; + s->frame_count = (value & FMCOUNT_MASK) >> FMCOUNT_SHIFT; + if (value & C_RESET) { + mss_spi_do_reset(s); + } + break; + + case R_SPI_DFSIZE: + if (s->enabled) { + break; + } + s->regs[R_SPI_DFSIZE] = value; + break; + + case R_SPI_INTCLR: + s->regs[R_SPI_INTCLR] = value; + if (value & S_TXDONE) { + s->regs[R_SPI_RIS] &= ~S_TXDONE; + } + if (value & S_RXRDY) { + s->regs[R_SPI_RIS] &= ~S_RXRDY; + } + if (value & S_RXCHOVRF) { + s->regs[R_SPI_RIS] &= ~S_RXCHOVRF; + } + break; + + case R_SPI_MIS: + case R_SPI_STATUS: + case R_SPI_RIS: + qemu_log_mask(LOG_GUEST_ERROR, + "%s: Write to read only register 0x%" HWADDR_PRIx "\n", + __func__, addr * 4); + break; + + default: + if (addr < ARRAY_SIZE(s->regs)) { + s->regs[addr] = value; + } else { + qemu_log_mask(LOG_GUEST_ERROR, + "%s: Bad offset 0x%" HWADDR_PRIx "\n", __func__, + addr * 4); + } + break; + } + + spi_update_irq(s); +} + +static const MemoryRegionOps spi_ops = { + .read = spi_read, + .write = spi_write, + .endianness = DEVICE_NATIVE_ENDIAN, + .valid = { + .min_access_size = 1, + .max_access_size = 4 + } +}; + +static void mss_spi_realize(DeviceState *dev, Error **errp) +{ + MSSSpiState *s = MSS_SPI(dev); + SysBusDevice *sbd = SYS_BUS_DEVICE(dev); + + s->spi = ssi_create_bus(dev, "spi"); + + sysbus_init_irq(sbd, &s->irq); + ssi_auto_connect_slaves(dev, &s->cs_line, s->spi); + sysbus_init_irq(sbd, &s->cs_line); + + memory_region_init_io(&s->mmio, OBJECT(s), &spi_ops, s, + TYPE_MSS_SPI, R_SPI_MAX * 4); + sysbus_init_mmio(sbd, &s->mmio); + + fifo32_create(&s->tx_fifo, FIFO_CAPACITY); + fifo32_create(&s->rx_fifo, FIFO_CAPACITY); +} + +static const VMStateDescription vmstate_mss_spi = { + .name = TYPE_MSS_SPI, + .version_id = 1, + .minimum_version_id = 1, + .fields = (VMStateField[]) { + VMSTATE_FIFO32(tx_fifo, MSSSpiState), + VMSTATE_FIFO32(rx_fifo, MSSSpiState), + VMSTATE_UINT32_ARRAY(regs, MSSSpiState, R_SPI_MAX), + VMSTATE_END_OF_LIST() + } +}; + +static void mss_spi_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + + dc->realize = mss_spi_realize; + dc->reset = mss_spi_reset; + dc->vmsd = &vmstate_mss_spi; +} + +static const TypeInfo mss_spi_info = { + .name = TYPE_MSS_SPI, + .parent = TYPE_SYS_BUS_DEVICE, + .instance_size = sizeof(MSSSpiState), + .class_init = mss_spi_class_init, +}; + +static void mss_spi_register_types(void) +{ + type_register_static(&mss_spi_info); +} + +type_init(mss_spi_register_types) diff --git a/include/hw/ssi/mss-spi.h b/include/hw/ssi/mss-spi.h new file mode 100644 index 0000000..f0cf324 --- /dev/null +++ b/include/hw/ssi/mss-spi.h @@ -0,0 +1,58 @@ +/* + * Microsemi SmartFusion2 SPI + * + * Copyright (c) 2017 Subbaraya Sundeep + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#ifndef HW_MSS_SPI_H +#define HW_MSS_SPI_H + +#include "hw/sysbus.h" +#include "hw/ssi/ssi.h" +#include "qemu/fifo32.h" + +#define TYPE_MSS_SPI "mss-spi" +#define MSS_SPI(obj) OBJECT_CHECK(MSSSpiState, (obj), TYPE_MSS_SPI) + +#define R_SPI_MAX 16 + +typedef struct MSSSpiState { + SysBusDevice parent_obj; + + MemoryRegion mmio; + + qemu_irq irq; + + qemu_irq cs_line; + + SSIBus *spi; + + Fifo32 rx_fifo; + Fifo32 tx_fifo; + + int fifo_depth; + uint32_t frame_count; + bool enabled; + + uint32_t regs[R_SPI_MAX]; +} MSSSpiState; + +#endif /* HW_MSS_SPI_H */ -- 2.5.0 From MAILER-DAEMON Mon Aug 28 12:38:43 2017 Received: from list by lists.gnu.org with archive (Exim 4.71) id 1dmN3i-0002Cl-Pf for mharc-qemu-arm@gnu.org; Mon, 28 Aug 2017 12:38:42 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:45310) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dmN3e-00028M-9g for qemu-arm@nongnu.org; Mon, 28 Aug 2017 12:38:41 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dmN3c-00042h-9d for qemu-arm@nongnu.org; Mon, 28 Aug 2017 12:38:38 -0400 Received: from mail-pf0-x242.google.com ([2607:f8b0:400e:c00::242]:37588) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1dmN3U-0003Te-Nx; Mon, 28 Aug 2017 12:38:28 -0400 Received: by mail-pf0-x242.google.com with SMTP id a2so632127pfj.4; Mon, 28 Aug 2017 09:38:28 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=C29pAoMUIO8yNG/Bc17m+TaC8keaLeE1eM6hYI5J6mU=; b=uKrA93y7C4vd52AoCYOgzTyMcFRLXzSjpNNUX3uTn9gMiRxY6iH3Cxqq1byS1jrisn 1p8jDzE+PX1xpbnvBPkPxED2F2krGztR8Ofg029X6BD/E/IOVZlqS89WyPwIkPEQHtfk 6KUNAWOeneFYVXB8ZOOK/5Bb3zGH7dX4qW5+u0O8U8A4jdLFfEBWnUgQVFmYHP+/wXb0 HgRNYM7Ou7pldqrJIWW47KCAhULmbthWBOeP6xbyEYtn5ehjOWdtu3QuS3YmmYmtLGE2 Ko88VH7rSnjpRYImDPDNaqwJ0gnhVN4Q+08Qum+TV82NEXykzlSmqeW7SL4CwO6pQxW4 aueg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=C29pAoMUIO8yNG/Bc17m+TaC8keaLeE1eM6hYI5J6mU=; b=eV5K4JrEuTaBDzm87FY8CWAOR2U4FD48QdmHYiuU6IUvXvrzZp+hF2n1bDFBvX7Gf/ jmmd+Rrfuph9JbikoABaBEwhuQt4k7H0YQfDR7saRMoeX/mzFOXLux4Bm9F4N3RxF4hM xj30RNUPUZqh0zfMTKbnYxb1fSJaKFIL3c7wS85Tl3XMPDV2eTtZziB5x9IiqZpwtIwG ThubvGjG38eJeo77A5XXj6RVUCOY55S2qTNM3FLAGf7EuHMWupqQCZIcU/zc3Cl4WDws 6Xvrrbm6409xHTVIa3A8e6dreyJ9pN/ZKCDkM6IIQzbpygMjj0uUXOHbe8Fc6yOft/Ht 3yTw== X-Gm-Message-State: AHYfb5h4ScRvAFQRjTTm/76gmqa775D8i3yBIW1z+dVRBgawuI1pG48g 1+0oV64Ac7divKz8 X-Google-Smtp-Source: ADKCNb5Z9UaLMioDhhrWhOudknKRPRwMDk0Rs4jUjtP964xaGEZwisGqLqkNjwYFdXa9sEJ3L8d+3w== X-Received: by 10.99.2.2 with SMTP id 2mr1158328pgc.382.1503938307540; Mon, 28 Aug 2017 09:38:27 -0700 (PDT) Received: from localhost.localdomain ([124.123.70.3]) by smtp.gmail.com with ESMTPSA id n66sm1935015pfi.44.2017.08.28.09.38.25 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 28 Aug 2017 09:38:27 -0700 (PDT) From: Subbaraya Sundeep To: qemu-devel@nongnu.org, qemu-arm@nongnu.org Cc: peter.maydell@linaro.org, crosthwaite.peter@gmail.com, alistair23@gmail.com, f4bug@amsat.org, Subbaraya Sundeep Date: Mon, 28 Aug 2017 22:08:02 +0530 Message-Id: <1503938283-12404-5-git-send-email-sundeep.lkml@gmail.com> X-Mailer: git-send-email 2.5.0 In-Reply-To: <1503938283-12404-1-git-send-email-sundeep.lkml@gmail.com> References: <1503938283-12404-1-git-send-email-sundeep.lkml@gmail.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::242 Subject: [Qemu-arm] [Qemu devel v7 PATCH 4/5] msf2: Add Smartfusion2 SoC X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 28 Aug 2017 16:38:41 -0000 Smartfusion2 SoC has hardened Microcontroller subsystem and flash based FPGA fabric. This patch adds support for Microcontroller subsystem in the SoC. Signed-off-by: Subbaraya Sundeep --- default-configs/arm-softmmu.mak | 1 + hw/arm/Makefile.objs | 1 + hw/arm/msf2-soc.c | 215 ++++++++++++++++++++++++++++++++++++++++ include/hw/arm/msf2-soc.h | 66 ++++++++++++ 4 files changed, 283 insertions(+) create mode 100644 hw/arm/msf2-soc.c create mode 100644 include/hw/arm/msf2-soc.h diff --git a/default-configs/arm-softmmu.mak b/default-configs/arm-softmmu.mak index bbdd3c1..5059d13 100644 --- a/default-configs/arm-softmmu.mak +++ b/default-configs/arm-softmmu.mak @@ -129,3 +129,4 @@ CONFIG_ACPI=y CONFIG_SMBIOS=y CONFIG_ASPEED_SOC=y CONFIG_GPIO_KEY=y +CONFIG_MSF2=y diff --git a/hw/arm/Makefile.objs b/hw/arm/Makefile.objs index a2e56ec..df36a03 100644 --- a/hw/arm/Makefile.objs +++ b/hw/arm/Makefile.objs @@ -19,3 +19,4 @@ obj-$(CONFIG_FSL_IMX31) += fsl-imx31.o kzm.o obj-$(CONFIG_FSL_IMX6) += fsl-imx6.o sabrelite.o obj-$(CONFIG_ASPEED_SOC) += aspeed_soc.o aspeed.o obj-$(CONFIG_MPS2) += mps2.o +obj-$(CONFIG_MSF2) += msf2-soc.o diff --git a/hw/arm/msf2-soc.c b/hw/arm/msf2-soc.c new file mode 100644 index 0000000..276eec5 --- /dev/null +++ b/hw/arm/msf2-soc.c @@ -0,0 +1,215 @@ +/* + * SmartFusion2 SoC emulation. + * + * Copyright (c) 2017 Subbaraya Sundeep + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#include "qemu/osdep.h" +#include "qapi/error.h" +#include "qemu-common.h" +#include "hw/arm/arm.h" +#include "exec/address-spaces.h" +#include "hw/char/serial.h" +#include "hw/boards.h" +#include "sysemu/block-backend.h" +#include "qemu/cutils.h" +#include "hw/arm/msf2-soc.h" + +#define MSF2_TIMER_BASE 0x40004000 +#define MSF2_SYSREG_BASE 0x40038000 + +#define ENVM_BASE_ADDRESS 0x60000000 + +#define SRAM_BASE_ADDRESS 0x20000000 + +#define MSF2_ENVM_SIZE (512 * K_BYTE) +#define MSF2_ESRAM_SIZE (64 * K_BYTE) + +static const uint32_t spi_addr[MSF2_NUM_SPIS] = { 0x40001000 , 0x40011000 }; +static const uint32_t uart_addr[MSF2_NUM_UARTS] = { 0x40000000 , 0x40010000 }; + +static const int spi_irq[MSF2_NUM_SPIS] = { 2, 3 }; +static const int uart_irq[MSF2_NUM_UARTS] = { 10, 11 }; +static const int timer_irq[MSF2_NUM_TIMERS] = { 14, 15 }; + +static void m2sxxx_soc_initfn(Object *obj) +{ + MSF2State *s = MSF2_SOC(obj); + int i; + + object_initialize(&s->armv7m, sizeof(s->armv7m), TYPE_ARMV7M); + qdev_set_parent_bus(DEVICE(&s->armv7m), sysbus_get_default()); + + object_initialize(&s->sysreg, sizeof(s->sysreg), TYPE_MSF2_SYSREG); + qdev_set_parent_bus(DEVICE(&s->sysreg), sysbus_get_default()); + + object_initialize(&s->timer, sizeof(s->timer), TYPE_MSS_TIMER); + qdev_set_parent_bus(DEVICE(&s->timer), sysbus_get_default()); + + for (i = 0; i < MSF2_NUM_SPIS; i++) { + object_initialize(&s->spi[i], sizeof(s->spi[i]), + TYPE_MSS_SPI); + qdev_set_parent_bus(DEVICE(&s->spi[i]), sysbus_get_default()); + } +} + +static void m2sxxx_soc_realize(DeviceState *dev_soc, Error **errp) +{ + MSF2State *s = MSF2_SOC(dev_soc); + DeviceState *dev, *armv7m; + SysBusDevice *busdev; + Error *err = NULL; + int i; + + MemoryRegion *system_memory = get_system_memory(); + MemoryRegion *nvm = g_new(MemoryRegion, 1); + MemoryRegion *nvm_alias = g_new(MemoryRegion, 1); + MemoryRegion *sram = g_new(MemoryRegion, 1); + + memory_region_init_ram(nvm, NULL, "MSF2.eNVM", s->envm_size, + &error_fatal); + + /* + * On power-on, the eNVM region 0x60000000 is automatically + * remapped to the Cortex-M3 processor executable region + * start address (0x0). We do not support remapping other eNVM, + * eSRAM and DDR regions by guest(via Sysreg) currently. + */ + memory_region_init_alias(nvm_alias, NULL, "MSF2.eNVM.alias", + nvm, 0, s->envm_size); + + memory_region_set_readonly(nvm, true); + memory_region_set_readonly(nvm_alias, true); + + memory_region_add_subregion(system_memory, ENVM_BASE_ADDRESS, nvm); + memory_region_add_subregion(system_memory, 0, nvm_alias); + + memory_region_init_ram(sram, NULL, "MSF2.eSRAM", s->esram_size, + &error_fatal); + memory_region_add_subregion(system_memory, SRAM_BASE_ADDRESS, sram); + + armv7m = DEVICE(&s->armv7m); + qdev_prop_set_uint32(armv7m, "num-irq", 81); + qdev_prop_set_string(armv7m, "cpu-model", "cortex-m3"); + object_property_set_link(OBJECT(&s->armv7m), OBJECT(get_system_memory()), + "memory", &error_abort); + object_property_set_bool(OBJECT(&s->armv7m), true, "realized", &err); + if (err != NULL) { + error_propagate(errp, err); + return; + } + + system_clock_scale = NANOSECONDS_PER_SECOND / s->m3clk; + + for (i = 0; i < MSF2_NUM_UARTS; i++) { + if (serial_hds[i]) { + serial_mm_init(get_system_memory(), uart_addr[i], 2, + qdev_get_gpio_in(armv7m, uart_irq[i]), + 115200, serial_hds[i], DEVICE_NATIVE_ENDIAN); + } + } + + dev = DEVICE(&s->timer); + /* APB0 clock is the timer input clock */ + qdev_prop_set_uint32(dev, "clock-frequency", s->m3clk / s->apb0div); + object_property_set_bool(OBJECT(&s->timer), true, "realized", &err); + if (err != NULL) { + error_propagate(errp, err); + return; + } + busdev = SYS_BUS_DEVICE(dev); + sysbus_mmio_map(busdev, 0, MSF2_TIMER_BASE); + sysbus_connect_irq(busdev, 0, + qdev_get_gpio_in(armv7m, timer_irq[0])); + sysbus_connect_irq(busdev, 1, + qdev_get_gpio_in(armv7m, timer_irq[1])); + + dev = DEVICE(&s->sysreg); + qdev_prop_set_uint32(dev, "apb0divisor", s->apb0div); + qdev_prop_set_uint32(dev, "apb1divisor", s->apb1div); + object_property_set_bool(OBJECT(&s->sysreg), true, "realized", &err); + if (err != NULL) { + error_propagate(errp, err); + return; + } + busdev = SYS_BUS_DEVICE(dev); + sysbus_mmio_map(busdev, 0, MSF2_SYSREG_BASE); + + for (i = 0; i < MSF2_NUM_SPIS; i++) { + gchar *bus_name = g_strdup_printf("spi%d", i); + + object_property_set_bool(OBJECT(&s->spi[i]), true, "realized", &err); + if (err != NULL) { + g_free(bus_name); + error_propagate(errp, err); + return; + } + + sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi[i]), 0, spi_addr[i]); + sysbus_connect_irq(SYS_BUS_DEVICE(&s->spi[i]), 0, + qdev_get_gpio_in(armv7m, spi_irq[i])); + + /* Alias controller SPI bus to the SoC itself */ + object_property_add_alias(OBJECT(s), bus_name, + OBJECT(&s->spi[i]), "spi", + &error_abort); + g_free(bus_name); + } +} + +static Property m2sxxx_soc_properties[] = { + /* + * part name specifies the type of SmartFusion2 device variant(this + * property is for information purpose only. + */ + DEFINE_PROP_STRING("part-name", MSF2State, part_name), + DEFINE_PROP_UINT64("eNVM-size", MSF2State, envm_size, MSF2_ENVM_SIZE), + DEFINE_PROP_UINT64("eSRAM-size", MSF2State, esram_size, MSF2_ESRAM_SIZE), + /* Libero GUI shows 100Mhz as default for clocks */ + DEFINE_PROP_UINT32("m3clk", MSF2State, m3clk, 100 * 1000000), + /* default divisors in Libero GUI */ + DEFINE_PROP_UINT32("apb0div", MSF2State, apb0div, 2), + DEFINE_PROP_UINT32("apb1div", MSF2State, apb1div, 2), + DEFINE_PROP_END_OF_LIST(), +}; + +static void m2sxxx_soc_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + + dc->realize = m2sxxx_soc_realize; + dc->props = m2sxxx_soc_properties; +} + +static const TypeInfo m2sxxx_soc_info = { + .name = TYPE_MSF2_SOC, + .parent = TYPE_SYS_BUS_DEVICE, + .instance_size = sizeof(MSF2State), + .instance_init = m2sxxx_soc_initfn, + .class_init = m2sxxx_soc_class_init, +}; + +static void m2sxxx_soc_types(void) +{ + type_register_static(&m2sxxx_soc_info); +} + +type_init(m2sxxx_soc_types) diff --git a/include/hw/arm/msf2-soc.h b/include/hw/arm/msf2-soc.h new file mode 100644 index 0000000..eb239fa --- /dev/null +++ b/include/hw/arm/msf2-soc.h @@ -0,0 +1,66 @@ +/* + * Microsemi Smartfusion2 SoC + * + * Copyright (c) 2017 Subbaraya Sundeep + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#ifndef HW_ARM_MSF2_SOC_H +#define HW_ARM_MSF2_SOC_H + +#include "hw/arm/armv7m.h" +#include "hw/timer/mss-timer.h" +#include "hw/misc/msf2-sysreg.h" +#include "hw/ssi/mss-spi.h" + +#define TYPE_MSF2_SOC "msf2-soc" +#define MSF2_SOC(obj) OBJECT_CHECK(MSF2State, (obj), TYPE_MSF2_SOC) + +#define MSF2_NUM_SPIS 2 +#define MSF2_NUM_UARTS 2 + +/* + * System timer consists of two programmable 32-bit + * decrementing counters that generate individual interrupts to + * the Cortex-M3 processor + */ +#define MSF2_NUM_TIMERS 2 + +typedef struct MSF2State { + /*< private >*/ + SysBusDevice parent_obj; + /*< public >*/ + + ARMv7MState armv7m; + + char *part_name; + uint64_t envm_size; + uint64_t esram_size; + + uint32_t m3clk; + uint32_t apb0div; + uint32_t apb1div; + + MSF2SysregState sysreg; + MSSTimerState timer; + MSSSpiState spi[MSF2_NUM_SPIS]; +} MSF2State; + +#endif -- 2.5.0 From MAILER-DAEMON Mon Aug 28 13:42:55 2017 Received: from list by lists.gnu.org with archive (Exim 4.71) id 1dmO3r-0004Lh-Ta for mharc-qemu-arm@gnu.org; Mon, 28 Aug 2017 13:42:55 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:59758) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dmO3p-0004LU-Vm for qemu-arm@nongnu.org; Mon, 28 Aug 2017 13:42:54 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dmO3m-0006iI-S2 for qemu-arm@nongnu.org; Mon, 28 Aug 2017 13:42:54 -0400 Received: from mail-io0-x22f.google.com ([2607:f8b0:4001:c06::22f]:38272) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1dmO3m-0006hg-MS for qemu-arm@nongnu.org; Mon, 28 Aug 2017 13:42:50 -0400 Received: by mail-io0-x22f.google.com with SMTP id 81so4463284ioj.5 for ; Mon, 28 Aug 2017 10:42:49 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=subject:to:cc:references:from:message-id:date:user-agent :mime-version:in-reply-to:content-language:content-transfer-encoding; bh=7qwJNpqkwm1Rye4DpAHu3F1U2tZ9LXf4PsTtVkgibWI=; b=XqdW22XfF/ojzg86PSIm+J1wkQkIl2wf3h8I+llbCHTiQ6/hC8esqhQz21g2Qp2kq/ IbawlfQZYJoETy6UwJMOTnP8Tnq5DE+Q4+/T+3xG/KaLUNCR4zCULVGUMvdrxNgXwWFD WQbSLKjHDZ8C37pyQqKSFc9QzHnM2vKmUS5LU= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:subject:to:cc:references:from:message-id:date :user-agent:mime-version:in-reply-to:content-language :content-transfer-encoding; bh=7qwJNpqkwm1Rye4DpAHu3F1U2tZ9LXf4PsTtVkgibWI=; b=gKiZmPH+zkL6XBR4DySCDks4iKKDMyvF0DttD/kxuLeNNqedcJPah4EBnNOtPp/Ky8 ubyoO+v99uVXrbVWvAJKc0OvrJp/cDfMtYOfhHh+7so/NqhBdxVvluNoXU9Sthuqpq8E xPDyhqSlxHJmQKVJr6kC3aW0YDImjtoheNsSrYb4+Opk5NSNWwMqEQu59sMSuQ/b9i0B Mz0EQk8BEaeNTtT05hcmV2M4vv1rPNWpb5huss3jNb9vJwvdbUAOb/f5VwL4e4Fnslv0 JOiPPqCSia7L9KBdo9BDGU/MnyThUVSjtLjZ7UJXuFh483QCEJ4A2ZqOM0P1QI3ec6Cy S3/w== X-Gm-Message-State: AHYfb5izIOJ5l5diWUZgXznAZhBH7mJ3MfjODQXIRTWBHFKo8a9CdkRW PEGJwTtKVcfLuvBN X-Received: by 10.36.115.70 with SMTP id y67mr1307280itb.1.1503942168478; Mon, 28 Aug 2017 10:42:48 -0700 (PDT) Received: from bigtime.twiddle.net ([172.56.42.6]) by smtp.gmail.com with ESMTPSA id e97sm404574ioi.37.2017.08.28.10.42.46 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 28 Aug 2017 10:42:47 -0700 (PDT) To: Pranith Kumar , alex.bennee@linaro.org, Peter Maydell , "open list:ARM" , "open list:All patches CC here" Cc: pbonzini@redhat.com References: <20170828035327.17146-1-bobby.prani@gmail.com> From: Richard Henderson Message-ID: <367db2c6-86dc-288e-c020-80d99a755f51@linaro.org> Date: Mon, 28 Aug 2017 10:42:44 -0700 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.2.1 MIME-Version: 1.0 In-Reply-To: <20170828035327.17146-1-bobby.prani@gmail.com> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 7bit X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4001:c06::22f Subject: Re: [Qemu-arm] [PATCH 1/3] target/arm: Remove stale comment X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 28 Aug 2017 17:42:55 -0000 On 08/27/2017 08:53 PM, Pranith Kumar wrote: > Update the comment which is not true since MTTCG. > > Signed-off-by: Pranith Kumar > --- > target/arm/translate-a64.c | 4 ---- > 1 file changed, 4 deletions(-) Reviewed-by: Richard Henderson r~ From MAILER-DAEMON Mon Aug 28 13:57:42 2017 Received: from list by lists.gnu.org with archive (Exim 4.71) id 1dmOIA-0006iq-D1 for mharc-qemu-arm@gnu.org; Mon, 28 Aug 2017 13:57:42 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:35887) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dmOI8-0006gq-D3 for qemu-arm@nongnu.org; Mon, 28 Aug 2017 13:57:41 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dmOI7-0007Af-L7 for qemu-arm@nongnu.org; Mon, 28 Aug 2017 13:57:40 -0400 Received: from mail-io0-x244.google.com ([2607:f8b0:4001:c06::244]:33591) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1dmOI1-00076j-Eo; Mon, 28 Aug 2017 13:57:33 -0400 Received: by mail-io0-x244.google.com with SMTP id s101so887165ioe.0; Mon, 28 Aug 2017 10:57:32 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:subject:to:cc:references:from:message-id:date:user-agent :mime-version:in-reply-to:content-language:content-transfer-encoding; bh=qfUUuZ85ZNgir7XkdARO4NCsxrdRBfR315bqf96jk8A=; b=Mfzj584AeJ9+xxw2St/xQs+LRmxfAEUQzmBIVRkoi+/WwLA0Ur0O619/cjmyIwfOhz oRXIRHq5dOtM37WbP8WOlYlHFeOmnpq29nIAh2zAcKKz3juh8CtZfUY2F9TyCSZjlFAl wvURsxD2/p5etQ7xt+MT1qOfo8fZkutcqvxpN/2pbqoQf7mX6HS/IZ0LVCXqmWVyRv6G YUMy9jc/n+qrfkb58sihYqrih9kDiK5FHO0GHUyEYOX1uDnitU8xRrlVcd9i7FAi4OQ6 UkVbbR2qr+z09yuk90ALO9nff0D0he104CE0JD0wuhXPf+wtuUX6WFtSdx3wpm7Dl86U U2jw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:subject:to:cc:references:from:message-id :date:user-agent:mime-version:in-reply-to:content-language :content-transfer-encoding; bh=qfUUuZ85ZNgir7XkdARO4NCsxrdRBfR315bqf96jk8A=; b=mA6Az1OxLW6RpKqUhgNG1OLOiikVtvYpwv9Eg2TL8whLLOLUPBYiiNtRhJrX0v1kKk iwQEeQYkEiFF7WjIQAVR+dd/HCypnQQKUZVXvoHA64aF8cLJaJc95BeG+fvKEDP+0vi6 0bhRF56dzPFil8RmYNIQ4UH0KsfA6cZhrBsX5R+ZNuXfSDCuGIr0oFeHEiBpm+bg1oMy mf+QqLShuy9CI7XUTmZOoAm5H0ub1uUFGxakTZtPz5sMLjlA0vnC2q0JhHSnyVID5vtZ LHI12Qy5enMBzP+zX6xSlrUj5RHPzg6qNP5mklq0GtMMqNV/evAAojyH/+bm7Gr0JuMZ gg5Q== X-Gm-Message-State: AHYfb5i+iWWhhyQFE58HMIzZY3YeIoChJmXPVu+PMKxeNBjdJhHoP9S/ gwP/uYezE9NX6w== X-Received: by 10.36.51.72 with SMTP id k69mr1434146itk.145.1503943051291; Mon, 28 Aug 2017 10:57:31 -0700 (PDT) Received: from bigtime.twiddle.net ([172.56.42.6]) by smtp.googlemail.com with ESMTPSA id g20sm243312itb.21.2017.08.28.10.57.27 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 28 Aug 2017 10:57:29 -0700 (PDT) Sender: Richard Henderson To: Pranith Kumar , alex.bennee@linaro.org, Claudio Fontana , Andrzej Zaborowski , Aurelien Jarno , "open list:AArch64 target" , "open list:All patches CC here" Cc: pbonzini@redhat.com References: <20170828035327.17146-1-bobby.prani@gmail.com> <20170828035327.17146-3-bobby.prani@gmail.com> From: Richard Henderson Message-ID: <03c05a60-d697-500b-c2fc-d99b24f3f64c@twiddle.net> Date: Mon, 28 Aug 2017 10:57:25 -0700 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.2.1 MIME-Version: 1.0 In-Reply-To: <20170828035327.17146-3-bobby.prani@gmail.com> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 7bit X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4001:c06::244 Subject: Re: [Qemu-arm] [RFC PATCH 3/3] mttcg: Implement implicit ordering semantics X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 28 Aug 2017 17:57:41 -0000 On 08/27/2017 08:53 PM, Pranith Kumar wrote: > diff --git a/tcg/aarch64/tcg-target.h b/tcg/aarch64/tcg-target.h > index 55a46ac825..b41a248bee 100644 > --- a/tcg/aarch64/tcg-target.h > +++ b/tcg/aarch64/tcg-target.h > @@ -117,4 +117,6 @@ static inline void flush_icache_range(uintptr_t start, uintptr_t stop) > __builtin___clear_cache((char *)start, (char *)stop); > } > > +#define TCG_TARGET_DEFAULT_MO (0) > + > #endif /* AARCH64_TCG_TARGET_H */ Please add all of these in one patch, separate from the tcg-op.c changes. We should also just make this mandatory and remove any related #ifdefs. > +void tcg_gen_req_mo(TCGBar type) static, until we find that we need it somewhere else. > +#if defined(TCG_GUEST_DEFAULT_MO) && defined(TCG_TARGET_DEFAULT_MO) > + TCGBar order_mismatch = type & (TCG_GUEST_DEFAULT_MO & ~TCG_TARGET_DEFAULT_MO); > + if (order_mismatch) { > + tcg_gen_mb(order_mismatch | TCG_BAR_SC); > + } > +#else > + tcg_gen_mb(TCG_MO_ALL | TCG_BAR_SC); > +#endif Hmm. How about static void tcg_gen_reg_mo(TCGBar type) { #ifdef TCG_GUEST_DEFAULT_MO type &= TCG_GUEST_DEFAULT_MO; #endif #ifdef TCG_TARGET_DEFAULT_MO type &= ~TCG_TARGET_DEFAULT_MO; #endif if (type) { tcg_gen_mb(type | TCG_BAR_SC); } } Just because one of those is undefined doesn't mean we can't infer tighter barriers from the others, including the initial value of TYPE. > void tcg_gen_qemu_ld_i32(TCGv_i32 val, TCGv addr, TCGArg idx, TCGMemOp memop) > { > + tcg_gen_req_mo(TCG_MO_LD_LD | TCG_MO_LD_ST); > memop = tcg_canonicalize_memop(memop, 0, 0); You're putting the barrier before the load, so that should be TCG_MO_LD_LD | TCG_MO_ST_LD i.e. TCG_MO__ If you were putting the barrier afterward (an equally reasonable option), you'd reverse that and use what you have above. r~ From MAILER-DAEMON Mon Aug 28 14:08:16 2017 Received: from list by lists.gnu.org with archive (Exim 4.71) id 1dmOSO-00040A-3k for mharc-qemu-arm@gnu.org; Mon, 28 Aug 2017 14:08:16 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:38946) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dmOSL-0003zg-Dv for qemu-arm@nongnu.org; Mon, 28 Aug 2017 14:08:14 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dmOSH-0004d0-Bt for qemu-arm@nongnu.org; Mon, 28 Aug 2017 14:08:13 -0400 Received: from mail-pg0-x244.google.com ([2607:f8b0:400e:c05::244]:33098) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1dmOSH-0004cX-5S; Mon, 28 Aug 2017 14:08:09 -0400 Received: by mail-pg0-x244.google.com with SMTP id m15so906655pgc.0; Mon, 28 Aug 2017 11:08:09 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:subject:to:references:from:message-id:date:user-agent :mime-version:in-reply-to:content-language:content-transfer-encoding; bh=omy4xWpeOupyA2rLXxgMwKUL4Dnl3JvLpxki57+EgIc=; b=mumHNLNb5TFdEeI0gdmo2Q9nXubOXb01gGG2n74w/nBtfm0Ipk5vTcIvsIVr7ZWV1J Os0CXEWBiZMmSj9Aon+XQW0SgrDvSyEFdtRLVt9TNyifBmZT0Uii8DfIq+7Luyy7xb32 d40EzzP5HU5FAEX9evM2Juzo2zbdf+75ry2whB+SCzqmIjArXMEK1XU4UQPXnfqfmfiU FjG+fQ4XG0ggGXZvCnT8i4y9MAUwZs4xGk+N8J/sJNLiYhmkCoWVpeV65d/He2BTEQj3 D0oFcishXqq+ZaEBJsM2Q/F4hOfBHOm55UCd8rbQ7urra/+vx4+SscQWQ40k1kqL3+7f HeMg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:subject:to:references:from:message-id :date:user-agent:mime-version:in-reply-to:content-language :content-transfer-encoding; bh=omy4xWpeOupyA2rLXxgMwKUL4Dnl3JvLpxki57+EgIc=; b=GXRcLaT7vIfyS+ZeXejCZYkR/sDipn3N8KvybQ95dM6Ohzwb7rkGSsQkkq5VySDj/p BiyJzBr7+Ij5n9jG2389aD129pR5smW3Nzkx0Lv1KlndqwYB95dm6pECilEQNVtBs2gf 5JskcnfWQMwlr21/U4ExHxaqeoz2uAKHOOW8elDf92tlxHqkROZoqRJBH8ZupBN3kFSH VLMUGOgAsN8c63ktlplz4NoqdOmRwD3OKKM0dVo9SBYcpCVPZDuMJ81zW6aL3d6qu2PC 7qXRDW0oqteUL7aELT0boOLoIftJoYwg2UklEfwpIQI2lw53DBsE79zkf/8DieqFUteq 3E7Q== X-Gm-Message-State: AHYfb5jYMo0VZT6w/cS59ofNN3RTnOZqDvqs/we6yzd2o4Wb1YZ53Hrt B+fwMue1av6MRhphysM= X-Received: by 10.98.16.72 with SMTP id y69mr1456230pfi.78.1503943687886; Mon, 28 Aug 2017 11:08:07 -0700 (PDT) Received: from bigtime.twiddle.net ([172.56.42.6]) by smtp.googlemail.com with ESMTPSA id m21sm1694609pfg.28.2017.08.28.11.08.06 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 28 Aug 2017 11:08:07 -0700 (PDT) Sender: Richard Henderson To: Pranith Kumar , alex.bennee@linaro.org, Paolo Bonzini , Peter Crosthwaite , Claudio Fontana , Andrzej Zaborowski , Aurelien Jarno , Alexander Graf , Stefan Weil , "open list:Overall" , "open list:AArch64 target" References: <20170824155849.30799-1-bobby.prani@gmail.com> From: Richard Henderson Message-ID: <34d6f244-4dd7-1701-30b8-bb9cdc089681@twiddle.net> Date: Mon, 28 Aug 2017 11:08:04 -0700 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.2.1 MIME-Version: 1.0 In-Reply-To: <20170824155849.30799-1-bobby.prani@gmail.com> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 7bit X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::244 Subject: Re: [Qemu-arm] [RFC v2 PATCH] tcg/softmmu: Increase size of TLB caches X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 28 Aug 2017 18:08:14 -0000 On 08/24/2017 08:58 AM, Pranith Kumar wrote: > | TLB bits\vTLB entires | 8 | 16 | 32 | > | 8 | 952.94(+0.0%) | 929.99(+2.4%) | 919.02(+3.6%) | > | 10 | 898.92(+5.6%) | 886.13(+7.0%) | 887.03(+6.9%) | > | 12 | 878.56(+7.8%) | 873.53(+8.3%)* | 875.34(+8.1%) | Thanks for collecting this. > @@ -89,7 +89,7 @@ typedef uint64_t target_ulong; > * of tlb_table inside env (which is non-trivial but not huge). > */ > #define CPU_TLB_BITS \ > - MIN(8, \ > + MIN(CPU_TLB_BITS_MAX, \ > TCG_TARGET_TLB_DISPLACEMENT_BITS - CPU_TLB_ENTRY_BITS - \ > (NB_MMU_MODES <= 1 ? 0 : \ > NB_MMU_MODES <= 2 ? 1 : \ > diff --git a/tcg/aarch64/tcg-target.h b/tcg/aarch64/tcg-target.h > index 55a46ac825..f428e09c98 100644 > --- a/tcg/aarch64/tcg-target.h > +++ b/tcg/aarch64/tcg-target.h > @@ -15,6 +15,7 @@ > > #define TCG_TARGET_INSN_UNIT_SIZE 4 > #define TCG_TARGET_TLB_DISPLACEMENT_BITS 24 > +#define CPU_TLB_BITS_MAX 12 I'd rather the definition in tcg-target.h reflect the actual maximum and limit that to what we want (12) within cpu-defs.h. So, here maybe #define TCG_TARGET_TLB_MAX_INDEX_BITS 32 etc. r~ From MAILER-DAEMON Mon Aug 28 16:45:53 2017 Received: from list by lists.gnu.org with archive (Exim 4.71) id 1dmQuv-0006Cy-NG for mharc-qemu-arm@gnu.org; Mon, 28 Aug 2017 16:45:53 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:41356) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dmQut-0006Cp-3Q for qemu-arm@nongnu.org; Mon, 28 Aug 2017 16:45:51 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dmQuq-0000md-1d for qemu-arm@nongnu.org; Mon, 28 Aug 2017 16:45:51 -0400 Received: from mail-pg0-x244.google.com ([2607:f8b0:400e:c05::244]:36413) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1dmQup-0000mL-M0; Mon, 28 Aug 2017 16:45:47 -0400 Received: by mail-pg0-x244.google.com with SMTP id 83so1151052pgb.3; Mon, 28 Aug 2017 13:45:47 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:subject:to:references:from:message-id:date:user-agent :mime-version:in-reply-to:content-language:content-transfer-encoding; bh=fAZxB6alhsZN2rl6SzmfkXg+pG4cxsev+NTypUhbmpg=; b=ICLLnLBUGSZj/mcDN/vrkM1gWCpO9QZnEEZFmtuOY5pXrBqRO+scenpkmeKXI4Uyx5 GIscH3WtyTFh2J+FGPQROzFCin93L1P7tDivEkx2ny/Min5T2GHXJmmUlq/i3MBkJ48k PUAgUZgnB+jBY8rY7VcB4BnF9Pl5yNoA6cP1k29w0ucw832e/ETOBoLLxBhOXg6qcrhy TFU2arTemarJj4AxPYQ+uTdkGHpyokgd3lJyIgxE/l8QKPe1B4Mti6j+bbTKqIUmJ6gM qYZp6jCShIvRS1kTyhka8l0wBkct01lXuTUgfvB+ktmum15/flXF8UQqciD1vZaDKdyv e1QQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:subject:to:references:from:message-id :date:user-agent:mime-version:in-reply-to:content-language :content-transfer-encoding; bh=fAZxB6alhsZN2rl6SzmfkXg+pG4cxsev+NTypUhbmpg=; b=AlpWGHltpxqy/ajaXePLEe3UsnY26T3PYKj9RIQ0roQnlQMqxcmRfG4rZ3rLXUzBms N+7ov/A+AbL9Ieh2MvcDDwn/1z9xJNkTDyUU9ltJZzh8Z81W61sES8LAnrVVunYavMiC AcT0DJ2Z1He5Ke9bwA6EgmYUadyeQZM8G+3AhpUodPdi7cUgw4SpIPFpSCDKW9AMjeba 8RcXhnlIQOakcg5yF9ly5iED9IjIow9jDOC96KRmaitjwCatIyl1iLD3zHOun/nyvFqU VkQiRZNxtoUoMPcTFrQlb/Sil8f+qayk/VuwHbhhwsXOnIQD2ekrEoUhaLV0uiayiqTY O7fA== X-Gm-Message-State: AHYfb5g/ayb75GwgSuPQsTC13uOWKh7c41ImOBDjvJdz1U45tkmPE4B4 shvsN8LChIeMpBi4Wdw= X-Received: by 10.84.217.200 with SMTP id d8mr2302068plj.264.1503953146242; Mon, 28 Aug 2017 13:45:46 -0700 (PDT) Received: from bigtime.twiddle.net (97-126-108-236.tukw.qwest.net. [97.126.108.236]) by smtp.googlemail.com with ESMTPSA id i187sm2412283pfe.67.2017.08.28.13.45.44 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 28 Aug 2017 13:45:44 -0700 (PDT) Sender: Richard Henderson To: Pranith Kumar , alex.bennee@linaro.org, Paolo Bonzini , Peter Crosthwaite , Claudio Fontana , Andrzej Zaborowski , Aurelien Jarno , Alexander Graf , Stefan Weil , "open list:Overall" , "open list:AArch64 target" References: <20170824155849.30799-1-bobby.prani@gmail.com> From: Richard Henderson Message-ID: <14b3bf90-2c45-4c6b-3c26-9422eaeff88d@twiddle.net> Date: Mon, 28 Aug 2017 13:45:42 -0700 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.2.1 MIME-Version: 1.0 In-Reply-To: <20170824155849.30799-1-bobby.prani@gmail.com> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 7bit X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::244 Subject: Re: [Qemu-arm] [RFC v2 PATCH] tcg/softmmu: Increase size of TLB caches X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 28 Aug 2017 20:45:52 -0000 On 08/24/2017 08:58 AM, Pranith Kumar wrote: > +#define CPU_TLB_BITS_MAX 12 Following up on our IRC conversation, host maximums are: aarch64: unlimited (32) arm: 8 (patch exists to increase to 32 for armv7) i386: 32 - CPU_TLB_ENTRY_BITS ia64: unlimited (32) mips: 16 - CPU_TLB_ENTRY_BITS ppc: unlimited (32) s390: unlimited (32) sparc: 12 tci: unlimited (32) r~ From MAILER-DAEMON Mon Aug 28 17:42:04 2017 Received: from list by lists.gnu.org with archive (Exim 4.71) id 1dmRnI-0006rQ-P8 for mharc-qemu-arm@gnu.org; Mon, 28 Aug 2017 17:42:04 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:50906) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dmRnG-0006q8-G1 for qemu-arm@nongnu.org; Mon, 28 Aug 2017 17:42:03 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dmRnF-0003LB-GC for qemu-arm@nongnu.org; Mon, 28 Aug 2017 17:42:02 -0400 Received: from mail-io0-x243.google.com ([2607:f8b0:4001:c06::243]:32866) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1dmRnF-0003Kt-Bz; Mon, 28 Aug 2017 17:42:01 -0400 Received: by mail-io0-x243.google.com with SMTP id s101so1556059ioe.0; Mon, 28 Aug 2017 14:42:01 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=mime-version:in-reply-to:references:from:date:message-id:subject:to :cc; bh=KpqDEs4yddDa+0pSUfedxZ0ZC3zqn+E22PLNFI1qOcs=; b=OkA07d68CyfvvibofnL0zR0ZbarLoK6NPRfLwOQMqEc+5wLPCt5GO5vYK/p/JlNXgJ m6xR1vu0tSP1y9joSxLWZSxqvB+a4WRfZXderifkYeNX2C7nLUWpq4OLZYCyUoVTIRA4 GuwojR6DqwW5pHznX8I4Il9clZj7vbpJMCH0qBkm3vhPa3XP39Y1OJs0lcdcDRFcw3XT OgV5J59TOsiV3vlYhs18NBQtVus/attVWJF2WOvwOBS54RUuGgaUI6PpzDgfhu248Aiy EQLX6M9xknM7ULGiq5+MYmUVpS2w+4dZ7EUg32rTzO8Ij6KP3las01sHDpQgu9o5L2y+ WwJw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:in-reply-to:references:from:date :message-id:subject:to:cc; bh=KpqDEs4yddDa+0pSUfedxZ0ZC3zqn+E22PLNFI1qOcs=; b=cjMMDOjg3Z0xUxvWpbQ0AKnpw5K25IvGmkXt3xFga8LLw+Hss1E3xvuUuiA05FL2vP gV3G7xIZsGwoVub9nDE/9YwvihZwY2vXsJh5CuCMT5t4xwIW89evGl4xyMyVYjm8yg7C g3VJW37VPiKlQuFpmP6gkPVTpOTsv6FonrxJu344fsg0jR2F4K8jEqanpMjkjb2GwI/Y EM0/aZiPzPSP/z2WzqtXoMW06/6Zn0cKa5Gp4pTgHIV0BM+Mcn9Z6iMx5DjZwplHXNZI ZukA4nyV8ZMs0fkVIc8KsoRBuyUWpeU2eh8ktRQIBZWgBUoo6MCBUIc8gesE64THmtfI bDAA== X-Gm-Message-State: AHYfb5hr4TE20WVN8U1JkSZy3LgXmeH125lFx8KceNSobXSSX7EkqRch RhdzDu8oZzHDVFuXJr8KYE24ZfMboQ== X-Received: by 10.107.205.194 with SMTP id d185mr2015929iog.8.1503956520172; Mon, 28 Aug 2017 14:42:00 -0700 (PDT) MIME-Version: 1.0 Received: by 10.79.166.2 with HTTP; Mon, 28 Aug 2017 14:41:29 -0700 (PDT) In-Reply-To: <03c05a60-d697-500b-c2fc-d99b24f3f64c@twiddle.net> References: <20170828035327.17146-1-bobby.prani@gmail.com> <20170828035327.17146-3-bobby.prani@gmail.com> <03c05a60-d697-500b-c2fc-d99b24f3f64c@twiddle.net> From: Pranith Kumar Date: Mon, 28 Aug 2017 17:41:29 -0400 Message-ID: To: Richard Henderson Cc: =?UTF-8?B?QWxleCBCZW5uw6ll?= , Andrzej Zaborowski , Aurelien Jarno , "open list:AArch64 target" , "open list:All patches CC here" , Paolo Bonzini Content-Type: text/plain; charset="UTF-8" X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4001:c06::243 Subject: Re: [Qemu-arm] [RFC PATCH 3/3] mttcg: Implement implicit ordering semantics X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 28 Aug 2017 21:42:03 -0000 On Mon, Aug 28, 2017 at 1:57 PM, Richard Henderson wrote: > On 08/27/2017 08:53 PM, Pranith Kumar wrote: >> diff --git a/tcg/aarch64/tcg-target.h b/tcg/aarch64/tcg-target.h >> index 55a46ac825..b41a248bee 100644 >> --- a/tcg/aarch64/tcg-target.h >> +++ b/tcg/aarch64/tcg-target.h >> @@ -117,4 +117,6 @@ static inline void flush_icache_range(uintptr_t start, uintptr_t stop) >> __builtin___clear_cache((char *)start, (char *)stop); >> } >> >> +#define TCG_TARGET_DEFAULT_MO (0) >> + >> #endif /* AARCH64_TCG_TARGET_H */ > > Please add all of these in one patch, separate from the tcg-op.c changes. > We should also just make this mandatory and remove any related #ifdefs. I tried looking up ordering semantics for architectures like ia64 and s390. It is not really clear. I think every arch but for x86 can be defined as weak, even though archs like sparc can also be configured as TSO. Is this right? > >> +void tcg_gen_req_mo(TCGBar type) > > static, until we find that we need it somewhere else. > Will fix. >> +#if defined(TCG_GUEST_DEFAULT_MO) && defined(TCG_TARGET_DEFAULT_MO) >> + TCGBar order_mismatch = type & (TCG_GUEST_DEFAULT_MO & ~TCG_TARGET_DEFAULT_MO); >> + if (order_mismatch) { >> + tcg_gen_mb(order_mismatch | TCG_BAR_SC); >> + } >> +#else >> + tcg_gen_mb(TCG_MO_ALL | TCG_BAR_SC); >> +#endif > > Hmm. How about > > static void tcg_gen_reg_mo(TCGBar type) > { > #ifdef TCG_GUEST_DEFAULT_MO > type &= TCG_GUEST_DEFAULT_MO; > #endif > #ifdef TCG_TARGET_DEFAULT_MO > type &= ~TCG_TARGET_DEFAULT_MO; > #endif > if (type) { > tcg_gen_mb(type | TCG_BAR_SC); > } > } Yes, this looks better and until we can get all the possible definitions of TCG_GUEST_DEFAULT_MO and TCG_TARGET_DEFAULT_MO figured out I would like to keep the #ifdefs. > > Just because one of those is undefined doesn't mean we can't infer tighter > barriers from the others, including the initial value of TYPE. > >> void tcg_gen_qemu_ld_i32(TCGv_i32 val, TCGv addr, TCGArg idx, TCGMemOp memop) >> { >> + tcg_gen_req_mo(TCG_MO_LD_LD | TCG_MO_LD_ST); >> memop = tcg_canonicalize_memop(memop, 0, 0); > > You're putting the barrier before the load, so that should be > > TCG_MO_LD_LD | TCG_MO_ST_LD > > i.e. TCG_MO__ > > If you were putting the barrier afterward (an equally reasonable option), you'd > reverse that and use what you have above. OK, will fix this. Thanks for the review. -- Pranith From MAILER-DAEMON Mon Aug 28 17:54:40 2017 Received: from list by lists.gnu.org with archive (Exim 4.71) id 1dmRzU-0001lA-17 for mharc-qemu-arm@gnu.org; Mon, 28 Aug 2017 17:54:40 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:52974) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dmRzQ-0001jW-Qz for qemu-arm@nongnu.org; Mon, 28 Aug 2017 17:54:38 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dmRzO-0000td-TU for qemu-arm@nongnu.org; Mon, 28 Aug 2017 17:54:36 -0400 Received: from mail-wr0-x241.google.com ([2a00:1450:400c:c0c::241]:35107) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1dmRzJ-0000qh-4b; Mon, 28 Aug 2017 17:54:30 -0400 Received: by mail-wr0-x241.google.com with SMTP id a47so1140393wra.2; Mon, 28 Aug 2017 14:54:27 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=mime-version:in-reply-to:references:from:date:message-id:subject:to :cc; bh=efiokcck4c44RGaGW1ffsSjJ0PciYGBZoeGcb7lfxZM=; b=Xa3LSXdJtO0eSgiyxJm5/zNZffws525xSQ1VZRtoH6ehh+MA8klmf3+5o+AKK/2Vlg 8Yqt11JJhh5VU4wSpOwC3TpTic85jfkxF0NkS5ukCLU7nsYUWiepGHbh+bzmVYyPMDj2 NOPSAKufCNLXLGemguA4ob16x1kvTpqcz8GRh+FKO1N7Jugj6evUHFrnbsB99poTB6df 6bptu3l4P273zmy4OgUbDK3lTCSZRzHjvI/1hpQRelbaBYCr3CUiR/k3Un3d0VLVupLt lskoJgniMjcy+2QOSJ5rerddnoU95lS/+aXY3yh7ZuRdayshxOIX3wlMxGNiBm9kdERW LUPQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:in-reply-to:references:from:date :message-id:subject:to:cc; bh=efiokcck4c44RGaGW1ffsSjJ0PciYGBZoeGcb7lfxZM=; b=taRFAAdMNec3aE/Df9raKHzAsSJIz1tkfIBdhit2dUWLPr99hm9E0iXvw05PNioYuz OzET10hQRjn1iEooSNwsR9dhvttiNCwFtBKxr3YovTY9MHX91hv7SZgSC+HMF0acZXka 5h7vtB0YC74ISiDqz40UESsXzaThuCxyGy+XcUVZK/WTl3yKGnHkGXjfPrA6kUa4lzZf 4t35LxW1ZuCi8wqFiv+zPbGRzNSqyEgLnSDz/K2ie5LtIP8BIaTh40b85hkadjrEdLFw aKuPuRkC3NKluu9kmnQxkZrG+3xfmR3j5ZmwaMijXjAmF/aA0YOdkaVNjBRPkvGJW+6C HU6g== X-Gm-Message-State: AHYfb5gNLinpA3R4xr+sh1cp1mdZgqWZNxV7MF/ymk6RblmAD4ttyTvT k2cuIim+5/qY/Sj7suAWRL1OpyL18A== X-Received: by 10.223.163.87 with SMTP id d23mr1115054wrb.84.1503957265872; Mon, 28 Aug 2017 14:54:25 -0700 (PDT) MIME-Version: 1.0 Received: by 10.28.191.130 with HTTP; Mon, 28 Aug 2017 14:53:55 -0700 (PDT) In-Reply-To: <1503938283-12404-2-git-send-email-sundeep.lkml@gmail.com> References: <1503938283-12404-1-git-send-email-sundeep.lkml@gmail.com> <1503938283-12404-2-git-send-email-sundeep.lkml@gmail.com> From: Alistair Francis Date: Mon, 28 Aug 2017 14:53:55 -0700 Message-ID: To: Subbaraya Sundeep Cc: "qemu-devel@nongnu.org Developers" , qemu-arm , Peter Maydell , Peter Crosthwaite , =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= Content-Type: text/plain; charset="UTF-8" X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:400c:c0c::241 Subject: Re: [Qemu-arm] [Qemu devel v7 PATCH 1/5] msf2: Add Smartfusion2 System timer X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 28 Aug 2017 21:54:38 -0000 On Mon, Aug 28, 2017 at 9:37 AM, Subbaraya Sundeep wrote: > Modelled System Timer in Microsemi's Smartfusion2 Soc. > Timer has two 32bit down counters and two interrupts. > > Signed-off-by: Subbaraya Sundeep I had already reviewed this patch in v6. As long as you have made all of the changes mentioned their you can add my reviewed-by to the next version (as long as there are no other significant changes). Can you please ensure you do add and keep reviewed-by tags, it's a pain to have to do it multiple times. Thanks, Alistair > --- > hw/timer/Makefile.objs | 1 + > hw/timer/mss-timer.c | 289 +++++++++++++++++++++++++++++++++++++++++++ > include/hw/timer/mss-timer.h | 64 ++++++++++ > 3 files changed, 354 insertions(+) > create mode 100644 hw/timer/mss-timer.c > create mode 100644 include/hw/timer/mss-timer.h > > diff --git a/hw/timer/Makefile.objs b/hw/timer/Makefile.objs > index 15cce1c..8c19eac 100644 > --- a/hw/timer/Makefile.objs > +++ b/hw/timer/Makefile.objs > @@ -42,3 +42,4 @@ common-obj-$(CONFIG_ASPEED_SOC) += aspeed_timer.o > > common-obj-$(CONFIG_SUN4V_RTC) += sun4v-rtc.o > common-obj-$(CONFIG_CMSDK_APB_TIMER) += cmsdk-apb-timer.o > +common-obj-$(CONFIG_MSF2) += mss-timer.o > diff --git a/hw/timer/mss-timer.c b/hw/timer/mss-timer.c > new file mode 100644 > index 0000000..60f1213 > --- /dev/null > +++ b/hw/timer/mss-timer.c > @@ -0,0 +1,289 @@ > +/* > + * Block model of System timer present in > + * Microsemi's SmartFusion2 and SmartFusion SoCs. > + * > + * Copyright (c) 2017 Subbaraya Sundeep . > + * > + * Permission is hereby granted, free of charge, to any person obtaining a copy > + * of this software and associated documentation files (the "Software"), to deal > + * in the Software without restriction, including without limitation the rights > + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell > + * copies of the Software, and to permit persons to whom the Software is > + * furnished to do so, subject to the following conditions: > + * > + * The above copyright notice and this permission notice shall be included in > + * all copies or substantial portions of the Software. > + * > + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR > + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, > + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL > + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER > + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, > + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN > + * THE SOFTWARE. > + */ > + > +#include "qemu/osdep.h" > +#include "qemu/main-loop.h" > +#include "qemu/log.h" > +#include "hw/timer/mss-timer.h" > + > +#ifndef MSS_TIMER_ERR_DEBUG > +#define MSS_TIMER_ERR_DEBUG 0 > +#endif > + > +#define DB_PRINT_L(lvl, fmt, args...) do { \ > + if (MSS_TIMER_ERR_DEBUG >= lvl) { \ > + qemu_log("%s: " fmt "\n", __func__, ## args); \ > + } \ > +} while (0); > + > +#define DB_PRINT(fmt, args...) DB_PRINT_L(1, fmt, ## args) > + > +#define R_TIM_VAL 0 > +#define R_TIM_LOADVAL 1 > +#define R_TIM_BGLOADVAL 2 > +#define R_TIM_CTRL 3 > +#define R_TIM_RIS 4 > +#define R_TIM_MIS 5 > + > +#define TIMER_CTRL_ENBL (1 << 0) > +#define TIMER_CTRL_ONESHOT (1 << 1) > +#define TIMER_CTRL_INTR (1 << 2) > +#define TIMER_RIS_ACK (1 << 0) > +#define TIMER_RST_CLR (1 << 6) > +#define TIMER_MODE (1 << 0) > + > +static void timer_update_irq(struct Msf2Timer *st) > +{ > + bool isr, ier; > + > + isr = !!(st->regs[R_TIM_RIS] & TIMER_RIS_ACK); > + ier = !!(st->regs[R_TIM_CTRL] & TIMER_CTRL_INTR); > + qemu_set_irq(st->irq, (ier && isr)); > +} > + > +static void timer_update(struct Msf2Timer *st) > +{ > + uint64_t count; > + > + if (!(st->regs[R_TIM_CTRL] & TIMER_CTRL_ENBL)) { > + ptimer_stop(st->ptimer); > + return; > + } > + > + count = st->regs[R_TIM_LOADVAL]; > + ptimer_set_limit(st->ptimer, count, 1); > + ptimer_run(st->ptimer, 1); > +} > + > +static uint64_t > +timer_read(void *opaque, hwaddr offset, unsigned int size) > +{ > + MSSTimerState *t = opaque; > + hwaddr addr; > + struct Msf2Timer *st; > + uint32_t ret = 0; > + int timer = 0; > + int isr; > + int ier; > + > + addr = offset >> 2; > + /* > + * Two independent timers has same base address. > + * Based on address passed figure out which timer is being used. > + */ > + if ((addr >= R_TIM1_MAX) && (addr < NUM_TIMERS * R_TIM1_MAX)) { > + timer = 1; > + addr -= R_TIM1_MAX; > + } > + > + st = &t->timers[timer]; > + > + switch (addr) { > + case R_TIM_VAL: > + ret = ptimer_get_count(st->ptimer); > + break; > + > + case R_TIM_MIS: > + isr = !!(st->regs[R_TIM_RIS] & TIMER_RIS_ACK); > + ier = !!(st->regs[R_TIM_CTRL] & TIMER_CTRL_INTR); > + ret = ier & isr; > + break; > + > + default: > + if (addr < R_TIM1_MAX) { > + ret = st->regs[addr]; > + } else { > + qemu_log_mask(LOG_GUEST_ERROR, > + TYPE_MSS_TIMER": 64-bit mode not supported\n"); > + return ret; > + } > + break; > + } > + > + DB_PRINT("timer=%d 0x%" HWADDR_PRIx "=0x%" PRIx32, timer, offset, > + ret); > + return ret; > +} > + > +static void > +timer_write(void *opaque, hwaddr offset, > + uint64_t val64, unsigned int size) > +{ > + MSSTimerState *t = opaque; > + hwaddr addr; > + struct Msf2Timer *st; > + int timer = 0; > + uint32_t value = val64; > + > + addr = offset >> 2; > + /* > + * Two independent timers has same base address. > + * Based on addr passed figure out which timer is being used. > + */ > + if ((addr >= R_TIM1_MAX) && (addr < NUM_TIMERS * R_TIM1_MAX)) { > + timer = 1; > + addr -= R_TIM1_MAX; > + } > + > + st = &t->timers[timer]; > + > + DB_PRINT("addr=0x%" HWADDR_PRIx " val=0x%" PRIx32 " (timer=%d)", offset, > + value, timer); > + > + switch (addr) { > + case R_TIM_CTRL: > + st->regs[R_TIM_CTRL] = value; > + timer_update(st); > + break; > + > + case R_TIM_RIS: > + if (value & TIMER_RIS_ACK) { > + st->regs[R_TIM_RIS] &= ~TIMER_RIS_ACK; > + } > + break; > + > + case R_TIM_LOADVAL: > + st->regs[R_TIM_LOADVAL] = value; > + if (st->regs[R_TIM_CTRL] & TIMER_CTRL_ENBL) { > + timer_update(st); > + } > + break; > + > + case R_TIM_BGLOADVAL: > + st->regs[R_TIM_BGLOADVAL] = value; > + st->regs[R_TIM_LOADVAL] = value; > + break; > + > + case R_TIM_VAL: > + case R_TIM_MIS: > + break; > + > + default: > + if (addr < R_TIM1_MAX) { > + st->regs[addr] = value; > + } else { > + qemu_log_mask(LOG_GUEST_ERROR, > + TYPE_MSS_TIMER": 64-bit mode not supported\n"); > + return; > + } > + break; > + } > + timer_update_irq(st); > +} > + > +static const MemoryRegionOps timer_ops = { > + .read = timer_read, > + .write = timer_write, > + .endianness = DEVICE_NATIVE_ENDIAN, > + .valid = { > + .min_access_size = 1, > + .max_access_size = 4 > + } > +}; > + > +static void timer_hit(void *opaque) > +{ > + struct Msf2Timer *st = opaque; > + > + st->regs[R_TIM_RIS] |= TIMER_RIS_ACK; > + > + if (!(st->regs[R_TIM_CTRL] & TIMER_CTRL_ONESHOT)) { > + timer_update(st); > + } > + timer_update_irq(st); > +} > + > +static void mss_timer_init(Object *obj) > +{ > + MSSTimerState *t = MSS_TIMER(obj); > + int i; > + > + /* Init all the ptimers. */ > + for (i = 0; i < NUM_TIMERS; i++) { > + struct Msf2Timer *st = &t->timers[i]; > + > + st->bh = qemu_bh_new(timer_hit, st); > + st->ptimer = ptimer_init(st->bh, PTIMER_POLICY_DEFAULT); > + ptimer_set_freq(st->ptimer, t->freq_hz); > + sysbus_init_irq(SYS_BUS_DEVICE(obj), &st->irq); > + } > + > + memory_region_init_io(&t->mmio, OBJECT(t), &timer_ops, t, TYPE_MSS_TIMER, > + NUM_TIMERS * R_TIM1_MAX * 4); > + sysbus_init_mmio(SYS_BUS_DEVICE(obj), &t->mmio); > +} > + > +static const VMStateDescription vmstate_timers = { > + .name = "mss-timer-block", > + .version_id = 1, > + .minimum_version_id = 1, > + .fields = (VMStateField[]) { > + VMSTATE_PTIMER(ptimer, struct Msf2Timer), > + VMSTATE_UINT32_ARRAY(regs, struct Msf2Timer, R_TIM1_MAX), > + VMSTATE_END_OF_LIST() > + } > +}; > + > +static const VMStateDescription vmstate_mss_timer = { > + .name = TYPE_MSS_TIMER, > + .version_id = 1, > + .minimum_version_id = 1, > + .fields = (VMStateField[]) { > + VMSTATE_UINT32(freq_hz, MSSTimerState), > + VMSTATE_STRUCT_ARRAY(timers, MSSTimerState, NUM_TIMERS, 0, > + vmstate_timers, struct Msf2Timer), > + VMSTATE_END_OF_LIST() > + } > +}; > + > +static Property mss_timer_properties[] = { > + /* Libero GUI shows 100Mhz as default for clocks */ > + DEFINE_PROP_UINT32("clock-frequency", MSSTimerState, freq_hz, > + 100 * 1000000), > + DEFINE_PROP_END_OF_LIST(), > +}; > + > +static void mss_timer_class_init(ObjectClass *klass, void *data) > +{ > + DeviceClass *dc = DEVICE_CLASS(klass); > + > + dc->props = mss_timer_properties; > + dc->vmsd = &vmstate_mss_timer; > +} > + > +static const TypeInfo mss_timer_info = { > + .name = TYPE_MSS_TIMER, > + .parent = TYPE_SYS_BUS_DEVICE, > + .instance_size = sizeof(MSSTimerState), > + .instance_init = mss_timer_init, > + .class_init = mss_timer_class_init, > +}; > + > +static void mss_timer_register_types(void) > +{ > + type_register_static(&mss_timer_info); > +} > + > +type_init(mss_timer_register_types) > diff --git a/include/hw/timer/mss-timer.h b/include/hw/timer/mss-timer.h > new file mode 100644 > index 0000000..d15d173 > --- /dev/null > +++ b/include/hw/timer/mss-timer.h > @@ -0,0 +1,64 @@ > +/* > + * Microsemi SmartFusion2 Timer. > + * > + * Copyright (c) 2017 Subbaraya Sundeep > + * > + * Permission is hereby granted, free of charge, to any person obtaining a copy > + * of this software and associated documentation files (the "Software"), to deal > + * in the Software without restriction, including without limitation the rights > + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell > + * copies of the Software, and to permit persons to whom the Software is > + * furnished to do so, subject to the following conditions: > + * > + * The above copyright notice and this permission notice shall be included in > + * all copies or substantial portions of the Software. > + * > + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR > + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, > + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL > + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER > + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, > + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN > + * THE SOFTWARE. > + */ > + > +#ifndef HW_MSS_TIMER_H > +#define HW_MSS_TIMER_H > + > +#include "hw/sysbus.h" > +#include "hw/ptimer.h" > + > +#define TYPE_MSS_TIMER "mss-timer" > +#define MSS_TIMER(obj) OBJECT_CHECK(MSSTimerState, \ > + (obj), TYPE_MSS_TIMER) > + > +/* > + * There are two 32-bit down counting timers. > + * Timers 1 and 2 can be concatenated into a single 64-bit Timer > + * that operates either in Periodic mode or in One-shot mode. > + * Writing 1 to the TIM64_MODE register bit 0 sets the Timers in 64-bit mode. > + * In 64-bit mode, writing to the 32-bit registers has no effect. > + * Similarly, in 32-bit mode, writing to the 64-bit mode registers > + * has no effect. Only two 32-bit timers are supported currently. > + */ > +#define NUM_TIMERS 2 > + > +#define R_TIM1_MAX 6 > + > +struct Msf2Timer { > + QEMUBH *bh; > + ptimer_state *ptimer; > + > + uint32_t regs[R_TIM1_MAX]; > + qemu_irq irq; > +}; > + > +typedef struct MSSTimerState { > + SysBusDevice parent_obj; > + > + MemoryRegion mmio; > + uint32_t freq_hz; > + struct Msf2Timer timers[NUM_TIMERS]; > +} MSSTimerState; > + > +#endif /* HW_MSS_TIMER_H */ > -- > 2.5.0 > From MAILER-DAEMON Mon Aug 28 17:58:35 2017 Received: from list by lists.gnu.org with archive (Exim 4.71) id 1dmS3H-0002xW-2K for mharc-qemu-arm@gnu.org; Mon, 28 Aug 2017 17:58:35 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:53835) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dmS3E-0002uz-0s for qemu-arm@nongnu.org; Mon, 28 Aug 2017 17:58:33 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dmS3C-0002xQ-8n for qemu-arm@nongnu.org; Mon, 28 Aug 2017 17:58:32 -0400 Received: from mail-wr0-x244.google.com ([2a00:1450:400c:c0c::244]:36321) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1dmS37-0002u0-VQ; Mon, 28 Aug 2017 17:58:26 -0400 Received: by mail-wr0-x244.google.com with SMTP id 40so932886wrv.3; Mon, 28 Aug 2017 14:58:25 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=mime-version:in-reply-to:references:from:date:message-id:subject:to :cc; bh=2aMOE980Guuyg+v4W3Xc81x0SMaa2kf9z8x6jNf18T8=; b=DmfP+oe/70M3YVgjpeoqwkCv1i0eY/pNvasPZlAUWr70xqhecMgAImrBgy6/m5m3kQ zFBflPEuOeXW3+5Y9gg5EABXoQMLt9ol1Yc/QidtVG5CY0M++EwiK8M+zDpoSpqlhq8J Swpxkr2QwwJPqZcH4qoPpKVyuEpQ5ZezDtm+/6tugdxdBRCOdDppnun+xVJpfGzmAFwr O1bTu5MmTa5Pr3ItKHiHL3jogNQnRKuosf1f+RswckgKFgxBwxxh3KiY/hlOvll6fwL1 7Hix9Y5AVTT2YYDHbN2TF5aYPzoMjvuYm6TiMmZSWHi5ikvR6dllRhUfxbDF+G3bAyqR AUTg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:in-reply-to:references:from:date :message-id:subject:to:cc; bh=2aMOE980Guuyg+v4W3Xc81x0SMaa2kf9z8x6jNf18T8=; b=MaGipeS5hgDuef2YZ74WS3sFbiRDBC1qDPD230iZwQDwV4ptNJhPPuuvV9GuF69qNW 0eZ4I2wYGqOg1WHWetgcE+XB7VXY7P2QBpUS/6nZf8Bk+rFFy0ilDXLgviUtcGXOtMif 4dQKtswI2ExcavkM+WI+dN32R2AVsJP9P/ZYGOkJ37Aaxma4IZaNJvnBNwoc6xvTL7BK s4a2l8m6XFwCDWQ9YDn8DDsmgbXEB7dUdtmtVrYjdPZw4kZuE5VJdLJCBIAuD89ftpHl /Ey6hvcjlEd7U4lOxCD51FsBluO8P4URbVSd+IGrUSoo0aXUlY3+YgsN9g83uFyikwDf BSVg== X-Gm-Message-State: AHYfb5i5SPP0D79A8k5WHqJm+9KIA94uEYt6VgykqL6DlX19zhbnb+0K xJNrhT6KCL4rbOb7lm55kHzjRav6XA== X-Received: by 10.223.163.87 with SMTP id d23mr1118178wrb.84.1503957504716; Mon, 28 Aug 2017 14:58:24 -0700 (PDT) MIME-Version: 1.0 Received: by 10.28.191.130 with HTTP; Mon, 28 Aug 2017 14:57:54 -0700 (PDT) In-Reply-To: <1503938283-12404-5-git-send-email-sundeep.lkml@gmail.com> References: <1503938283-12404-1-git-send-email-sundeep.lkml@gmail.com> <1503938283-12404-5-git-send-email-sundeep.lkml@gmail.com> From: Alistair Francis Date: Mon, 28 Aug 2017 14:57:54 -0700 Message-ID: To: Subbaraya Sundeep Cc: "qemu-devel@nongnu.org Developers" , qemu-arm , Peter Maydell , Peter Crosthwaite , =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= Content-Type: text/plain; charset="UTF-8" X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:400c:c0c::244 Subject: Re: [Qemu-arm] [Qemu devel v7 PATCH 4/5] msf2: Add Smartfusion2 SoC X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 28 Aug 2017 21:58:34 -0000 On Mon, Aug 28, 2017 at 9:38 AM, Subbaraya Sundeep wrote: > Smartfusion2 SoC has hardened Microcontroller subsystem > and flash based FPGA fabric. This patch adds support for > Microcontroller subsystem in the SoC. > > Signed-off-by: Subbaraya Sundeep It looks like I have reviewed this one previously as well. Unless there were any major changes since then you can re-add my reviewed by tag. Thanks, Alistair > --- > default-configs/arm-softmmu.mak | 1 + > hw/arm/Makefile.objs | 1 + > hw/arm/msf2-soc.c | 215 ++++++++++++++++++++++++++++++++++++++++ > include/hw/arm/msf2-soc.h | 66 ++++++++++++ > 4 files changed, 283 insertions(+) > create mode 100644 hw/arm/msf2-soc.c > create mode 100644 include/hw/arm/msf2-soc.h > > diff --git a/default-configs/arm-softmmu.mak b/default-configs/arm-softmmu.mak > index bbdd3c1..5059d13 100644 > --- a/default-configs/arm-softmmu.mak > +++ b/default-configs/arm-softmmu.mak > @@ -129,3 +129,4 @@ CONFIG_ACPI=y > CONFIG_SMBIOS=y > CONFIG_ASPEED_SOC=y > CONFIG_GPIO_KEY=y > +CONFIG_MSF2=y > diff --git a/hw/arm/Makefile.objs b/hw/arm/Makefile.objs > index a2e56ec..df36a03 100644 > --- a/hw/arm/Makefile.objs > +++ b/hw/arm/Makefile.objs > @@ -19,3 +19,4 @@ obj-$(CONFIG_FSL_IMX31) += fsl-imx31.o kzm.o > obj-$(CONFIG_FSL_IMX6) += fsl-imx6.o sabrelite.o > obj-$(CONFIG_ASPEED_SOC) += aspeed_soc.o aspeed.o > obj-$(CONFIG_MPS2) += mps2.o > +obj-$(CONFIG_MSF2) += msf2-soc.o > diff --git a/hw/arm/msf2-soc.c b/hw/arm/msf2-soc.c > new file mode 100644 > index 0000000..276eec5 > --- /dev/null > +++ b/hw/arm/msf2-soc.c > @@ -0,0 +1,215 @@ > +/* > + * SmartFusion2 SoC emulation. > + * > + * Copyright (c) 2017 Subbaraya Sundeep > + * > + * Permission is hereby granted, free of charge, to any person obtaining a copy > + * of this software and associated documentation files (the "Software"), to deal > + * in the Software without restriction, including without limitation the rights > + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell > + * copies of the Software, and to permit persons to whom the Software is > + * furnished to do so, subject to the following conditions: > + * > + * The above copyright notice and this permission notice shall be included in > + * all copies or substantial portions of the Software. > + * > + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR > + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, > + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL > + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER > + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, > + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN > + * THE SOFTWARE. > + */ > + > +#include "qemu/osdep.h" > +#include "qapi/error.h" > +#include "qemu-common.h" > +#include "hw/arm/arm.h" > +#include "exec/address-spaces.h" > +#include "hw/char/serial.h" > +#include "hw/boards.h" > +#include "sysemu/block-backend.h" > +#include "qemu/cutils.h" > +#include "hw/arm/msf2-soc.h" > + > +#define MSF2_TIMER_BASE 0x40004000 > +#define MSF2_SYSREG_BASE 0x40038000 > + > +#define ENVM_BASE_ADDRESS 0x60000000 > + > +#define SRAM_BASE_ADDRESS 0x20000000 > + > +#define MSF2_ENVM_SIZE (512 * K_BYTE) > +#define MSF2_ESRAM_SIZE (64 * K_BYTE) > + > +static const uint32_t spi_addr[MSF2_NUM_SPIS] = { 0x40001000 , 0x40011000 }; > +static const uint32_t uart_addr[MSF2_NUM_UARTS] = { 0x40000000 , 0x40010000 }; > + > +static const int spi_irq[MSF2_NUM_SPIS] = { 2, 3 }; > +static const int uart_irq[MSF2_NUM_UARTS] = { 10, 11 }; > +static const int timer_irq[MSF2_NUM_TIMERS] = { 14, 15 }; > + > +static void m2sxxx_soc_initfn(Object *obj) > +{ > + MSF2State *s = MSF2_SOC(obj); > + int i; > + > + object_initialize(&s->armv7m, sizeof(s->armv7m), TYPE_ARMV7M); > + qdev_set_parent_bus(DEVICE(&s->armv7m), sysbus_get_default()); > + > + object_initialize(&s->sysreg, sizeof(s->sysreg), TYPE_MSF2_SYSREG); > + qdev_set_parent_bus(DEVICE(&s->sysreg), sysbus_get_default()); > + > + object_initialize(&s->timer, sizeof(s->timer), TYPE_MSS_TIMER); > + qdev_set_parent_bus(DEVICE(&s->timer), sysbus_get_default()); > + > + for (i = 0; i < MSF2_NUM_SPIS; i++) { > + object_initialize(&s->spi[i], sizeof(s->spi[i]), > + TYPE_MSS_SPI); > + qdev_set_parent_bus(DEVICE(&s->spi[i]), sysbus_get_default()); > + } > +} > + > +static void m2sxxx_soc_realize(DeviceState *dev_soc, Error **errp) > +{ > + MSF2State *s = MSF2_SOC(dev_soc); > + DeviceState *dev, *armv7m; > + SysBusDevice *busdev; > + Error *err = NULL; > + int i; > + > + MemoryRegion *system_memory = get_system_memory(); > + MemoryRegion *nvm = g_new(MemoryRegion, 1); > + MemoryRegion *nvm_alias = g_new(MemoryRegion, 1); > + MemoryRegion *sram = g_new(MemoryRegion, 1); > + > + memory_region_init_ram(nvm, NULL, "MSF2.eNVM", s->envm_size, > + &error_fatal); > + > + /* > + * On power-on, the eNVM region 0x60000000 is automatically > + * remapped to the Cortex-M3 processor executable region > + * start address (0x0). We do not support remapping other eNVM, > + * eSRAM and DDR regions by guest(via Sysreg) currently. > + */ > + memory_region_init_alias(nvm_alias, NULL, "MSF2.eNVM.alias", > + nvm, 0, s->envm_size); > + > + memory_region_set_readonly(nvm, true); > + memory_region_set_readonly(nvm_alias, true); > + > + memory_region_add_subregion(system_memory, ENVM_BASE_ADDRESS, nvm); > + memory_region_add_subregion(system_memory, 0, nvm_alias); > + > + memory_region_init_ram(sram, NULL, "MSF2.eSRAM", s->esram_size, > + &error_fatal); > + memory_region_add_subregion(system_memory, SRAM_BASE_ADDRESS, sram); > + > + armv7m = DEVICE(&s->armv7m); > + qdev_prop_set_uint32(armv7m, "num-irq", 81); > + qdev_prop_set_string(armv7m, "cpu-model", "cortex-m3"); > + object_property_set_link(OBJECT(&s->armv7m), OBJECT(get_system_memory()), > + "memory", &error_abort); > + object_property_set_bool(OBJECT(&s->armv7m), true, "realized", &err); > + if (err != NULL) { > + error_propagate(errp, err); > + return; > + } > + > + system_clock_scale = NANOSECONDS_PER_SECOND / s->m3clk; > + > + for (i = 0; i < MSF2_NUM_UARTS; i++) { > + if (serial_hds[i]) { > + serial_mm_init(get_system_memory(), uart_addr[i], 2, > + qdev_get_gpio_in(armv7m, uart_irq[i]), > + 115200, serial_hds[i], DEVICE_NATIVE_ENDIAN); > + } > + } > + > + dev = DEVICE(&s->timer); > + /* APB0 clock is the timer input clock */ > + qdev_prop_set_uint32(dev, "clock-frequency", s->m3clk / s->apb0div); > + object_property_set_bool(OBJECT(&s->timer), true, "realized", &err); > + if (err != NULL) { > + error_propagate(errp, err); > + return; > + } > + busdev = SYS_BUS_DEVICE(dev); > + sysbus_mmio_map(busdev, 0, MSF2_TIMER_BASE); > + sysbus_connect_irq(busdev, 0, > + qdev_get_gpio_in(armv7m, timer_irq[0])); > + sysbus_connect_irq(busdev, 1, > + qdev_get_gpio_in(armv7m, timer_irq[1])); > + > + dev = DEVICE(&s->sysreg); > + qdev_prop_set_uint32(dev, "apb0divisor", s->apb0div); > + qdev_prop_set_uint32(dev, "apb1divisor", s->apb1div); > + object_property_set_bool(OBJECT(&s->sysreg), true, "realized", &err); > + if (err != NULL) { > + error_propagate(errp, err); > + return; > + } > + busdev = SYS_BUS_DEVICE(dev); > + sysbus_mmio_map(busdev, 0, MSF2_SYSREG_BASE); > + > + for (i = 0; i < MSF2_NUM_SPIS; i++) { > + gchar *bus_name = g_strdup_printf("spi%d", i); > + > + object_property_set_bool(OBJECT(&s->spi[i]), true, "realized", &err); > + if (err != NULL) { > + g_free(bus_name); > + error_propagate(errp, err); > + return; > + } > + > + sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi[i]), 0, spi_addr[i]); > + sysbus_connect_irq(SYS_BUS_DEVICE(&s->spi[i]), 0, > + qdev_get_gpio_in(armv7m, spi_irq[i])); > + > + /* Alias controller SPI bus to the SoC itself */ > + object_property_add_alias(OBJECT(s), bus_name, > + OBJECT(&s->spi[i]), "spi", > + &error_abort); > + g_free(bus_name); > + } > +} > + > +static Property m2sxxx_soc_properties[] = { > + /* > + * part name specifies the type of SmartFusion2 device variant(this > + * property is for information purpose only. > + */ > + DEFINE_PROP_STRING("part-name", MSF2State, part_name), > + DEFINE_PROP_UINT64("eNVM-size", MSF2State, envm_size, MSF2_ENVM_SIZE), > + DEFINE_PROP_UINT64("eSRAM-size", MSF2State, esram_size, MSF2_ESRAM_SIZE), > + /* Libero GUI shows 100Mhz as default for clocks */ > + DEFINE_PROP_UINT32("m3clk", MSF2State, m3clk, 100 * 1000000), > + /* default divisors in Libero GUI */ > + DEFINE_PROP_UINT32("apb0div", MSF2State, apb0div, 2), > + DEFINE_PROP_UINT32("apb1div", MSF2State, apb1div, 2), > + DEFINE_PROP_END_OF_LIST(), > +}; > + > +static void m2sxxx_soc_class_init(ObjectClass *klass, void *data) > +{ > + DeviceClass *dc = DEVICE_CLASS(klass); > + > + dc->realize = m2sxxx_soc_realize; > + dc->props = m2sxxx_soc_properties; > +} > + > +static const TypeInfo m2sxxx_soc_info = { > + .name = TYPE_MSF2_SOC, > + .parent = TYPE_SYS_BUS_DEVICE, > + .instance_size = sizeof(MSF2State), > + .instance_init = m2sxxx_soc_initfn, > + .class_init = m2sxxx_soc_class_init, > +}; > + > +static void m2sxxx_soc_types(void) > +{ > + type_register_static(&m2sxxx_soc_info); > +} > + > +type_init(m2sxxx_soc_types) > diff --git a/include/hw/arm/msf2-soc.h b/include/hw/arm/msf2-soc.h > new file mode 100644 > index 0000000..eb239fa > --- /dev/null > +++ b/include/hw/arm/msf2-soc.h > @@ -0,0 +1,66 @@ > +/* > + * Microsemi Smartfusion2 SoC > + * > + * Copyright (c) 2017 Subbaraya Sundeep > + * > + * Permission is hereby granted, free of charge, to any person obtaining a copy > + * of this software and associated documentation files (the "Software"), to deal > + * in the Software without restriction, including without limitation the rights > + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell > + * copies of the Software, and to permit persons to whom the Software is > + * furnished to do so, subject to the following conditions: > + * > + * The above copyright notice and this permission notice shall be included in > + * all copies or substantial portions of the Software. > + * > + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR > + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, > + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL > + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER > + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, > + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN > + * THE SOFTWARE. > + */ > + > +#ifndef HW_ARM_MSF2_SOC_H > +#define HW_ARM_MSF2_SOC_H > + > +#include "hw/arm/armv7m.h" > +#include "hw/timer/mss-timer.h" > +#include "hw/misc/msf2-sysreg.h" > +#include "hw/ssi/mss-spi.h" > + > +#define TYPE_MSF2_SOC "msf2-soc" > +#define MSF2_SOC(obj) OBJECT_CHECK(MSF2State, (obj), TYPE_MSF2_SOC) > + > +#define MSF2_NUM_SPIS 2 > +#define MSF2_NUM_UARTS 2 > + > +/* > + * System timer consists of two programmable 32-bit > + * decrementing counters that generate individual interrupts to > + * the Cortex-M3 processor > + */ > +#define MSF2_NUM_TIMERS 2 > + > +typedef struct MSF2State { > + /*< private >*/ > + SysBusDevice parent_obj; > + /*< public >*/ > + > + ARMv7MState armv7m; > + > + char *part_name; > + uint64_t envm_size; > + uint64_t esram_size; > + > + uint32_t m3clk; > + uint32_t apb0div; > + uint32_t apb1div; > + > + MSF2SysregState sysreg; > + MSSTimerState timer; > + MSSSpiState spi[MSF2_NUM_SPIS]; > +} MSF2State; > + > +#endif > -- > 2.5.0 > From MAILER-DAEMON Mon Aug 28 18:21:11 2017 Received: from list by lists.gnu.org with archive (Exim 4.71) id 1dmSP9-0008Mh-Hn for mharc-qemu-arm@gnu.org; Mon, 28 Aug 2017 18:21:11 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:57105) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dmSP7-0008LU-Jr for qemu-arm@nongnu.org; Mon, 28 Aug 2017 18:21:10 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dmSP6-00040U-MR for qemu-arm@nongnu.org; Mon, 28 Aug 2017 18:21:09 -0400 Received: from mail-bn3nam01on0074.outbound.protection.outlook.com ([104.47.33.74]:43487 helo=NAM01-BN3-obe.outbound.protection.outlook.com) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1dmSP0-0003wl-2a; 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Ip=[149.199.60.100]; Helo=[xsj-pvapsmtpgw02] X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BN3PR02MB1126 X-detected-operating-system: by eggs.gnu.org: Windows 7 or 8 [fuzzy] X-Received-From: 104.47.33.74 Subject: [Qemu-arm] [PATCH] target/arm: Remove 5J architecture X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 28 Aug 2017 22:21:10 -0000 This fixes the issue that any BXJ instruction will result in an illegal_op. This is because the 5J archiecture is always unsupported. 5J architecture doesn't have a feature set and ENABLE_ARCH_5J is hardcoded to 0, causing any ARCH(5J) to result in an illegal_op. The only use of ARCH(5J) is in the BXJ instruction disassembly. This patch replaces that ARCH(5J) with ARCH(6) and removes the 5J architecture, this isn't technically correct since the v5J ISA does support the BXJ instruction. This change means that running a BXJ instruction on any v5 will cause an illegal_op but it is better than the current state where any architecture running a BXJ would cause an illegal_op. The correct solution would be to create a feature set for v5J but that doesn't seem worth it as the v5J is so old. Signed-off-by: Portia Stephens Reviewed-by: Alistair Francis --- target/arm/translate.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/target/arm/translate.c b/target/arm/translate.c index d1a5f56998..4a30c0d7e0 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -41,7 +41,6 @@ #define ENABLE_ARCH_5 arm_dc_feature(s, ARM_FEATURE_V5) /* currently all emulated v5 cores are also v5TE, so don't bother */ #define ENABLE_ARCH_5TE arm_dc_feature(s, ARM_FEATURE_V5) -#define ENABLE_ARCH_5J 0 #define ENABLE_ARCH_6 arm_dc_feature(s, ARM_FEATURE_V6) #define ENABLE_ARCH_6K arm_dc_feature(s, ARM_FEATURE_V6K) #define ENABLE_ARCH_6T2 arm_dc_feature(s, ARM_FEATURE_THUMB2) @@ -8389,7 +8388,10 @@ static void disas_arm_insn(DisasContext *s, unsigned int insn) break; case 0x2: if (op1 == 1) { - ARCH(5J); /* bxj */ + /* This should actually be ARCH(5J) but there is currently no + * 5J architecture in QEMU. + */ + ARCH(6); /* bxj */ /* Trivial implementation equivalent to bx. */ tmp = load_reg(s, rm); gen_bx(s, tmp); -- 2.14.1 From MAILER-DAEMON Mon Aug 28 18:39:46 2017 Received: from list by lists.gnu.org with archive (Exim 4.71) id 1dmSh7-0002Lx-S7 for mharc-qemu-arm@gnu.org; Mon, 28 Aug 2017 18:39:45 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:59420) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dmSh3-0002L0-Pr for qemu-arm@nongnu.org; Mon, 28 Aug 2017 18:39:42 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dmSh3-0004g4-0W for qemu-arm@nongnu.org; Mon, 28 Aug 2017 18:39:41 -0400 Received: from mail-pg0-x242.google.com ([2607:f8b0:400e:c05::242]:37562) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1dmSgx-0004eA-Q3; Mon, 28 Aug 2017 18:39:35 -0400 Received: by mail-pg0-x242.google.com with SMTP id t193so1318516pgc.4; Mon, 28 Aug 2017 15:39:35 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:subject:to:cc:references:from:message-id:date:user-agent :mime-version:in-reply-to:content-language:content-transfer-encoding; bh=XLzMEP7Fz7DiRz+FpBx2maCBGvrQGrkE2p3b6IvgSoQ=; b=fMrtAJl3MC3+lxrqyC4AwZjfEFZh3mjDR4Dzf6bY0nMmdxsEOQuN/DkWj004ylT3Nx SJflr6Pbm31aJWzMufCnhrO8RusE8epVsT/wiTwJPNE70iyxMH8QGsSeeTNUQPMZkMx6 JV2ZYO8BQvbsA+cvXpP2ZJNQiXOLaedd2S6WHt5xpx6TXC5k4JKLpwDaHwIAlq8nzigC lgWJbJ+lEKcBhNxsnF4M2+JNOIyDWNcod+E3LcySVgYQIhicFYCsFz5eu2JYqyQwXJJN 7jnizGG35jGBBnANpSrBpOGSLvC7mg5/cR4uhf3vY1jIA3CbtBrB2VvYMAnL2dO3GQrz b0rA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:subject:to:cc:references:from:message-id :date:user-agent:mime-version:in-reply-to:content-language :content-transfer-encoding; bh=XLzMEP7Fz7DiRz+FpBx2maCBGvrQGrkE2p3b6IvgSoQ=; b=hk/oA/DJPdXwx9JaWtLD5vA67IjW6NSGyQauQMB8XfrF0lXO7HLM4lH0kLq25NyDKm UgFc4Xvo6VC5gxJmsQjsbBQMebwG+LfAOaZzynDchsAuwuKpL7GAHCfz+jl5QoHcdegq XzpDejDsFxxz9AM9cBZLVx8sAPioie6VAM+aciceDEhe2gJ8FujeMz7dqVco0Y2SJ7Qp sTPoKYyiGxlV74HJ490E3SqpYLgSng8twCyGfmvMOYeGZjSRbPxEw9QEZKpABQcULPMA XdgqkLFVnrqLJnsuogrITQ+DbJOdlVpNVs1TlKd7ah28HtJf6BtU5qPJtXg5v0TvNnwc GsyA== X-Gm-Message-State: AHYfb5jMmfJ0KbmI22fAVshi9kvqbYFMiRtU19RkuqYsR/BQBbinLTn2 KweEIpl5IfrDtw== X-Received: by 10.84.132.14 with SMTP id 14mr2572393ple.150.1503959974686; Mon, 28 Aug 2017 15:39:34 -0700 (PDT) Received: from bigtime.twiddle.net (97-126-108-236.tukw.qwest.net. [97.126.108.236]) by smtp.googlemail.com with ESMTPSA id i72sm2210205pfi.124.2017.08.28.15.39.33 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 28 Aug 2017 15:39:33 -0700 (PDT) Sender: Richard Henderson To: Pranith Kumar Cc: =?UTF-8?Q?Alex_Benn=c3=a9e?= , Andrzej Zaborowski , Aurelien Jarno , "open list:AArch64 target" , "open list:All patches CC here" , Paolo Bonzini References: <20170828035327.17146-1-bobby.prani@gmail.com> <20170828035327.17146-3-bobby.prani@gmail.com> <03c05a60-d697-500b-c2fc-d99b24f3f64c@twiddle.net> From: Richard Henderson Message-ID: <45959c2a-94c3-7899-eaba-bf13ca85d052@twiddle.net> Date: Mon, 28 Aug 2017 15:39:31 -0700 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.2.1 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 7bit X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::242 Subject: Re: [Qemu-arm] [RFC PATCH 3/3] mttcg: Implement implicit ordering semantics X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 28 Aug 2017 22:39:42 -0000 On 08/28/2017 02:41 PM, Pranith Kumar wrote: > On Mon, Aug 28, 2017 at 1:57 PM, Richard Henderson wrote: >> On 08/27/2017 08:53 PM, Pranith Kumar wrote: >>> diff --git a/tcg/aarch64/tcg-target.h b/tcg/aarch64/tcg-target.h >>> index 55a46ac825..b41a248bee 100644 >>> --- a/tcg/aarch64/tcg-target.h >>> +++ b/tcg/aarch64/tcg-target.h >>> @@ -117,4 +117,6 @@ static inline void flush_icache_range(uintptr_t start, uintptr_t stop) >>> __builtin___clear_cache((char *)start, (char *)stop); >>> } >>> >>> +#define TCG_TARGET_DEFAULT_MO (0) >>> + >>> #endif /* AARCH64_TCG_TARGET_H */ >> >> Please add all of these in one patch, separate from the tcg-op.c changes. >> We should also just make this mandatory and remove any related #ifdefs. > > I tried looking up ordering semantics for architectures like ia64 and > s390. It is not really clear. I think every arch but for x86 can be > defined as weak, even though archs like sparc can also be configured > as TSO. Is this right? s390 has the same memory ordering as i386. But you're right that the risc chips should generally be 0. I'll try and figure out when sparc can use PSO (loosest for sparc < 8, and modern niagara), but leave it 0 for now. r~ From MAILER-DAEMON Mon Aug 28 18:58:46 2017 Received: from list by lists.gnu.org with archive (Exim 4.71) id 1dmSzW-0005dS-0J for mharc-qemu-arm@gnu.org; Mon, 28 Aug 2017 18:58:46 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:34172) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dmSzT-0005dI-HD for qemu-arm@nongnu.org; Mon, 28 Aug 2017 18:58:44 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dmSzQ-0004ZB-FL for qemu-arm@nongnu.org; Mon, 28 Aug 2017 18:58:43 -0400 Received: from mx1.redhat.com ([209.132.183.28]:40986) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1dmSzQ-0004Z0-8q; Mon, 28 Aug 2017 18:58:40 -0400 Received: from smtp.corp.redhat.com (int-mx02.intmail.prod.int.phx2.redhat.com [10.5.11.12]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id F40C57EA89; Mon, 28 Aug 2017 22:58:38 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mx1.redhat.com F40C57EA89 Authentication-Results: ext-mx04.extmail.prod.ext.phx2.redhat.com; dmarc=none (p=none dis=none) header.from=redhat.com Authentication-Results: ext-mx04.extmail.prod.ext.phx2.redhat.com; spf=fail smtp.mailfrom=jsnow@redhat.com Received: from [10.18.17.231] (dhcp-17-231.bos.redhat.com [10.18.17.231]) by smtp.corp.redhat.com (Postfix) with ESMTP id 157B018A74; Mon, 28 Aug 2017 22:58:37 +0000 (UTC) To: Eduardo Habkost , qemu-devel@nongnu.org Cc: xen-devel@lists.xenproject.org, qemu-block@nongnu.org, qemu-ppc@nongnu.org, qemu-arm@nongnu.org References: <20170823221445.15243-1-ehabkost@redhat.com> <20170823221445.15243-5-ehabkost@redhat.com> <20170825193922.GN27715@localhost.localdomain> From: John Snow Message-ID: <8ad06170-3409-f9aa-dbaf-380c2ca35fd9@redhat.com> Date: Mon, 28 Aug 2017 18:58:37 -0400 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.2.1 MIME-Version: 1.0 In-Reply-To: <20170825193922.GN27715@localhost.localdomain> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 7bit X-Scanned-By: MIMEDefang 2.79 on 10.5.11.12 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.28]); Mon, 28 Aug 2017 22:58:39 +0000 (UTC) X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.132.183.28 Subject: Re: [Qemu-arm] [Qemu-devel] [PATCH 4/5] pci: Add INTERFACE_LEGACY_PCI_DEVICE to legacy PCI devices X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 28 Aug 2017 22:58:44 -0000 On 08/25/2017 03:39 PM, Eduardo Habkost wrote: > CCing maintainers of affected devices (sorry for not CCing you > before). > > On Wed, Aug 23, 2017 at 07:14:44PM -0300, Eduardo Habkost wrote: >> Add INTERFACE_LEGACY_PCI_DEVICE to all direct subtypes of >> TYPE_PCI_DEVICE, except: >> >> 1) The ones that already have INTERFACE_PCIE_DEVICE set: >> >> * base-xhci >> * e1000e >> * nvme >> * pvscsi >> * vfio-pci >> * virtio-pci >> * vmxnet3 >> >> 2) base-pci-bridge >> >> Not all PCI bridges are legacy PCI devices, so >> INTERFACE_LEGACY_PCI_DEVICE is added only to the subtypes that >> are actually legacy PCI devices: >> >> * dec-21154-p2p-bridge >> * i82801b11-bridge >> * pbm-bridge >> * pci-bridge >> >> The direct subtypes of base-pci-bridge not touched by this patch >> are: >> >> * xilinx-pcie-root: Already marked as PCIe-only device. >> * pcie-port: all non-abstract subtypes of pcie-port are already >> marked as PCIe-only devices. >> >> 3) megasas-base >> >> Not all megasas devices are legacy PCI devices, so the interface >> names are added to the subclasses registered by >> megasas_register_types(), according to information in the >> megasas_devices[] array. >> >> "megasas-gen2" already implements INTERFACE_PCIE_DEVICE, so add >> INTERFACE_LEGACY_PCI_DEVICE only to "megasas". >> >> Signed-off-by: Eduardo Habkost >> --- [...] >> hw/ide/ich.c | 4 ++++ >> hw/ide/pci.c | 4 ++++ Acked-by: John Snow (Random fly-by comment without looking at the other patches: I assume there are reasons it's not appropriate or good to add a legacy PCI device parent that we inherit from, and it's instead better to manually add the property to all children?) From MAILER-DAEMON Mon Aug 28 19:20:36 2017 Received: from list by lists.gnu.org with archive (Exim 4.71) id 1dmTKe-0001MH-Kz for mharc-qemu-arm@gnu.org; Mon, 28 Aug 2017 19:20:36 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:39341) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dmTKc-0001Lr-0U for qemu-arm@nongnu.org; Mon, 28 Aug 2017 19:20:35 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dmTKY-00077T-1Y for qemu-arm@nongnu.org; Mon, 28 Aug 2017 19:20:34 -0400 Received: from mx1.redhat.com ([209.132.183.28]:36972) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1dmTKX-00076L-RR; Mon, 28 Aug 2017 19:20:29 -0400 Received: from smtp.corp.redhat.com (int-mx06.intmail.prod.int.phx2.redhat.com [10.5.11.16]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id 8F40E285B2; Mon, 28 Aug 2017 23:20:28 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mx1.redhat.com 8F40E285B2 Authentication-Results: ext-mx06.extmail.prod.ext.phx2.redhat.com; dmarc=none (p=none dis=none) header.from=redhat.com Authentication-Results: ext-mx06.extmail.prod.ext.phx2.redhat.com; spf=fail smtp.mailfrom=jsnow@redhat.com Received: from [10.18.17.231] (dhcp-17-231.bos.redhat.com [10.18.17.231]) by smtp.corp.redhat.com (Postfix) with ESMTP id D4D395C588; Mon, 28 Aug 2017 23:20:27 +0000 (UTC) To: Thomas Huth , qemu-block@nongnu.org Cc: qemu-arm@nongnu.org, qemu-devel@nongnu.org References: <1503543783-17192-1-git-send-email-thuth@redhat.com> From: John Snow Message-ID: <085793af-0342-c36e-53fd-e30eb23ef722@redhat.com> Date: Mon, 28 Aug 2017 19:20:27 -0400 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.2.1 MIME-Version: 1.0 In-Reply-To: <1503543783-17192-1-git-send-email-thuth@redhat.com> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 7bit X-Scanned-By: MIMEDefang 2.79 on 10.5.11.16 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.30]); Mon, 28 Aug 2017 23:20:28 +0000 (UTC) X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.132.183.28 Subject: Re: [Qemu-arm] [Qemu-devel] [PATCH for-2.11] hw/ide/microdrive: Mark the dscm1xxxx device with user_creatable = false X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 28 Aug 2017 23:20:35 -0000 On 08/23/2017 11:03 PM, Thomas Huth wrote: > QEMU currently aborts with an assertion message when the user is trying > to remove a dscm1xxxx again: > > $ aarch64-softmmu/qemu-system-aarch64 -S -M integratorcp -nographic > QEMU 2.9.93 monitor - type 'help' for more information > (qemu) device_add dscm1xxxx,id=xyz > (qemu) device_del xyz > ** > ERROR:qemu/qdev-monitor.c:872:qdev_unplug: assertion failed: (hotplug_ctrl) > Aborted (core dumped) > > Looks like this device has to be wired up in code and is not meant > to be hot-pluggable, so let's mark it with user_creatable = false. > > Signed-off-by: Thomas Huth > --- > hw/ide/microdrive.c | 3 +++ > 1 file changed, 3 insertions(+) > > diff --git a/hw/ide/microdrive.c b/hw/ide/microdrive.c > index e3fd30e..17917c0 100644 > --- a/hw/ide/microdrive.c > +++ b/hw/ide/microdrive.c > @@ -575,12 +575,15 @@ PCMCIACardState *dscm1xxxx_init(DriveInfo *dinfo) > static void dscm1xxxx_class_init(ObjectClass *oc, void *data) > { > PCMCIACardClass *pcc = PCMCIA_CARD_CLASS(oc); > + DeviceClass *dc = DEVICE_CLASS(oc); > > pcc->cis = dscm1xxxx_cis; > pcc->cis_len = sizeof(dscm1xxxx_cis); > > pcc->attach = dscm1xxxx_attach; > pcc->detach = dscm1xxxx_detach; > + /* Reason: Needs to be wired-up in code, see dscm1xxxx_init() */ > + dc->user_creatable = false; > } > > static const TypeInfo dscm1xxxx_type_info = { > OK; I'll look into Paolo's suggestion as a further fix, but whether or not we treat this property as a hint, it should be set anyway as you say. Reviewed-by: John Snow Thanks, applied to my IDE tree: https://github.com/jnsnow/qemu/commits/ide https://github.com/jnsnow/qemu.git --js From MAILER-DAEMON Mon Aug 28 23:43:41 2017 Received: from list by lists.gnu.org with archive (Exim 4.71) id 1dmXRF-0000V0-16 for mharc-qemu-arm@gnu.org; Mon, 28 Aug 2017 23:43:41 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:40967) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dmXRC-0000Ul-FP for qemu-arm@nongnu.org; Mon, 28 Aug 2017 23:43:39 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dmXR9-00010C-9i for qemu-arm@nongnu.org; Mon, 28 Aug 2017 23:43:38 -0400 Received: from mx1.redhat.com ([209.132.183.28]:40690) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1dmXR9-0000yd-2R; Mon, 28 Aug 2017 23:43:35 -0400 Received: from smtp.corp.redhat.com (int-mx02.intmail.prod.int.phx2.redhat.com [10.5.11.12]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id A0A3D7E42B; Tue, 29 Aug 2017 03:43:33 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mx1.redhat.com A0A3D7E42B Authentication-Results: ext-mx03.extmail.prod.ext.phx2.redhat.com; dmarc=none (p=none dis=none) header.from=redhat.com Authentication-Results: ext-mx03.extmail.prod.ext.phx2.redhat.com; spf=fail smtp.mailfrom=ehabkost@redhat.com Received: from localhost (ovpn-116-18.gru2.redhat.com [10.97.116.18]) by smtp.corp.redhat.com (Postfix) with ESMTP id EC78E183D7; Tue, 29 Aug 2017 03:43:30 +0000 (UTC) Date: Tue, 29 Aug 2017 00:43:29 -0300 From: Eduardo Habkost To: John Snow Cc: qemu-devel@nongnu.org, xen-devel@lists.xenproject.org, qemu-block@nongnu.org, qemu-ppc@nongnu.org, qemu-arm@nongnu.org Message-ID: <20170829034329.GV15315@localhost.localdomain> References: <20170823221445.15243-1-ehabkost@redhat.com> <20170823221445.15243-5-ehabkost@redhat.com> <20170825193922.GN27715@localhost.localdomain> <8ad06170-3409-f9aa-dbaf-380c2ca35fd9@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <8ad06170-3409-f9aa-dbaf-380c2ca35fd9@redhat.com> X-Fnord: you can see the fnord User-Agent: Mutt/1.8.0 (2017-02-23) X-Scanned-By: MIMEDefang 2.79 on 10.5.11.12 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.27]); Tue, 29 Aug 2017 03:43:33 +0000 (UTC) X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.132.183.28 Subject: Re: [Qemu-arm] [Qemu-devel] [PATCH 4/5] pci: Add INTERFACE_LEGACY_PCI_DEVICE to legacy PCI devices X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 29 Aug 2017 03:43:39 -0000 On Mon, Aug 28, 2017 at 06:58:37PM -0400, John Snow wrote: > > > On 08/25/2017 03:39 PM, Eduardo Habkost wrote: > > CCing maintainers of affected devices (sorry for not CCing you > > before). > > > > On Wed, Aug 23, 2017 at 07:14:44PM -0300, Eduardo Habkost wrote: > >> Add INTERFACE_LEGACY_PCI_DEVICE to all direct subtypes of > >> TYPE_PCI_DEVICE, except: > >> > >> 1) The ones that already have INTERFACE_PCIE_DEVICE set: > >> > >> * base-xhci > >> * e1000e > >> * nvme > >> * pvscsi > >> * vfio-pci > >> * virtio-pci > >> * vmxnet3 > >> > >> 2) base-pci-bridge > >> > >> Not all PCI bridges are legacy PCI devices, so > >> INTERFACE_LEGACY_PCI_DEVICE is added only to the subtypes that > >> are actually legacy PCI devices: > >> > >> * dec-21154-p2p-bridge > >> * i82801b11-bridge > >> * pbm-bridge > >> * pci-bridge > >> > >> The direct subtypes of base-pci-bridge not touched by this patch > >> are: > >> > >> * xilinx-pcie-root: Already marked as PCIe-only device. > >> * pcie-port: all non-abstract subtypes of pcie-port are already > >> marked as PCIe-only devices. > >> > >> 3) megasas-base > >> > >> Not all megasas devices are legacy PCI devices, so the interface > >> names are added to the subclasses registered by > >> megasas_register_types(), according to information in the > >> megasas_devices[] array. > >> > >> "megasas-gen2" already implements INTERFACE_PCIE_DEVICE, so add > >> INTERFACE_LEGACY_PCI_DEVICE only to "megasas". > >> > >> Signed-off-by: Eduardo Habkost > >> --- > > [...] > > >> hw/ide/ich.c | 4 ++++ > >> hw/ide/pci.c | 4 ++++ > > Acked-by: John Snow > > > (Random fly-by comment without looking at the other patches: I assume > there are reasons it's not appropriate or good to add a legacy PCI > device parent that we inherit from, and it's instead better to manually > add the property to all children?) Yes, the reason I'm using interfaces instead of regular inheritance is the existence of hybrid devices (see patch 2/5). -- Eduardo From MAILER-DAEMON Tue Aug 29 01:32:42 2017 Received: from list by lists.gnu.org with archive (Exim 4.71) id 1dmZ8j-0003u3-H4 for mharc-qemu-arm@gnu.org; Tue, 29 Aug 2017 01:32:42 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:56270) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dmZ8f-0003r2-6p for qemu-arm@nongnu.org; Tue, 29 Aug 2017 01:32:40 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dmZ8c-00083V-6I for qemu-arm@nongnu.org; Tue, 29 Aug 2017 01:32:37 -0400 Received: from mail-ua0-x243.google.com ([2607:f8b0:400c:c08::243]:35659) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1dmZ8V-00080z-L4; Tue, 29 Aug 2017 01:32:27 -0400 Received: by mail-ua0-x243.google.com with SMTP id 37so1048854ual.2; Mon, 28 Aug 2017 22:32:27 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=mime-version:in-reply-to:references:from:date:message-id:subject:to :cc; bh=dogtuECe8kgKPJ+oTM5EJMCHdrnQr4ttO3ZRldjeii8=; b=TT6NbNFlXxvI9LWbP1wTrbJVHlSl+mNc8vLehaZ/P6C6IH3Vx1eAN1nM1MdhYCqbny ayEAjBZmn8FpMfil8fMQKT6/+O277xZ0hGVdZ3nOxhhF51iMk8y6DWQx/VxepgM53PUN a3fWfvAk3iIoR7stOad6ipchO9g51IiOpAK8jR+bJt64SrC15A5ZeAufU9wPo3B+AqMW reIbX4Ubmg2li49PIaWGOLylHJGZohIqgzoP6VNbLQ87tRSvyeDonrXe8cqONCF70/aQ VN8AjaUdBUUuGuVHXHnZv4rqvxsdb3fOHF97jgcPpXV7dya3LFEOWmtlVdB6XS3f7Ghu 7qSA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:in-reply-to:references:from:date :message-id:subject:to:cc; bh=dogtuECe8kgKPJ+oTM5EJMCHdrnQr4ttO3ZRldjeii8=; b=R4rZEQIurWUq52T8sprBgQcLJxrtcuVA6BOLj8L/FHw9nWniv/ymcDl17XWPP+Zun8 /k7vufDRPOc+/E4ZQnQSFlUe67Y38IVodr1SIJdwlP8t+gEU18Dkv/gqt2JIW6KfB5CF Bg2BAJDDKmBBJ4l0YKxHwFvQysbzNUyARDWFz6t+iwaOwVKO7+xQN0efebg5FTINFOA4 LfOPo3SG142FEniOGr338afl1tqKV5Vmpm5GSt84KsZeegcymE82N4WnjYYnEMAZQQnn NXCgHobYgNkZ08sWK6cuDEQUHs1OvDrSnsaRtsdHo/22Xq+E4zqqEHW/82vFSYw3hc7L 5+xw== X-Gm-Message-State: AHYfb5ijLt9qF8CAeOe9ShPkW1yLgs5n8cS/7OT03Z54gHCoMhTyryH0 U6iRQVMq2R44DAVgRTW3FpP/9JfF6A== X-Google-Smtp-Source: ADKCNb6ktnkmqCq0x52kf+Zrf3sEKV6YSKT18zl3m9u8+rAvkLYVhJf2MtG0nLLzPpJWPDxGwBEVPrAqpyyb0e3UBNk= X-Received: by 10.176.68.102 with SMTP id m93mr1599075uam.133.1503984746875; Mon, 28 Aug 2017 22:32:26 -0700 (PDT) MIME-Version: 1.0 Received: by 10.176.75.196 with HTTP; Mon, 28 Aug 2017 22:32:26 -0700 (PDT) In-Reply-To: References: <1503938283-12404-1-git-send-email-sundeep.lkml@gmail.com> <1503938283-12404-2-git-send-email-sundeep.lkml@gmail.com> From: sundeep subbaraya Date: Tue, 29 Aug 2017 11:02:26 +0530 Message-ID: To: Alistair Francis Cc: "qemu-devel@nongnu.org Developers" , qemu-arm , Peter Maydell , Peter Crosthwaite , =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= Content-Type: multipart/alternative; boundary="001a114ccd3295d0c40557ddbc05" X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400c:c08::243 Subject: Re: [Qemu-arm] [Qemu devel v7 PATCH 1/5] msf2: Add Smartfusion2 System timer X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 29 Aug 2017 05:32:40 -0000 --001a114ccd3295d0c40557ddbc05 Content-Type: text/plain; charset="UTF-8" Hi Alistair, On Tue, Aug 29, 2017 at 3:23 AM, Alistair Francis wrote: > On Mon, Aug 28, 2017 at 9:37 AM, Subbaraya Sundeep > wrote: > > Modelled System Timer in Microsemi's Smartfusion2 Soc. > > Timer has two 32bit down counters and two interrupts. > > > > Signed-off-by: Subbaraya Sundeep > > I had already reviewed this patch in v6. As long as you have made all > of the changes mentioned their you can add my reviewed-by to the next > version (as long as there are no other significant changes). > > Can you please ensure you do add and keep reviewed-by tags, it's a > pain to have to do it multiple times. > Sorry I was not aware that I can add reviewed by tag myself and send. I will add your reviewed by since I fixed all your comments. Do I need to send another version v8 with your Reviewed-by ? Thanks, Sundeep > > Thanks, > Alistair > > > --- > > hw/timer/Makefile.objs | 1 + > > hw/timer/mss-timer.c | 289 ++++++++++++++++++++++++++++++ > +++++++++++++ > > include/hw/timer/mss-timer.h | 64 ++++++++++ > > 3 files changed, 354 insertions(+) > > create mode 100644 hw/timer/mss-timer.c > > create mode 100644 include/hw/timer/mss-timer.h > > > > diff --git a/hw/timer/Makefile.objs b/hw/timer/Makefile.objs > > index 15cce1c..8c19eac 100644 > > --- a/hw/timer/Makefile.objs > > +++ b/hw/timer/Makefile.objs > > @@ -42,3 +42,4 @@ common-obj-$(CONFIG_ASPEED_SOC) += aspeed_timer.o > > > > common-obj-$(CONFIG_SUN4V_RTC) += sun4v-rtc.o > > common-obj-$(CONFIG_CMSDK_APB_TIMER) += cmsdk-apb-timer.o > > +common-obj-$(CONFIG_MSF2) += mss-timer.o > > diff --git a/hw/timer/mss-timer.c b/hw/timer/mss-timer.c > > new file mode 100644 > > index 0000000..60f1213 > > --- /dev/null > > +++ b/hw/timer/mss-timer.c > > @@ -0,0 +1,289 @@ > > +/* > > + * Block model of System timer present in > > + * Microsemi's SmartFusion2 and SmartFusion SoCs. > > + * > > + * Copyright (c) 2017 Subbaraya Sundeep . > > + * > > + * Permission is hereby granted, free of charge, to any person > obtaining a copy > > + * of this software and associated documentation files (the > "Software"), to deal > > + * in the Software without restriction, including without limitation > the rights > > + * to use, copy, modify, merge, publish, distribute, sublicense, and/or > sell > > + * copies of the Software, and to permit persons to whom the Software is > > + * furnished to do so, subject to the following conditions: > > + * > > + * The above copyright notice and this permission notice shall be > included in > > + * all copies or substantial portions of the Software. > > + * > > + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, > EXPRESS OR > > + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF > MERCHANTABILITY, > > + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT > SHALL > > + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR > OTHER > > + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, > ARISING FROM, > > + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER > DEALINGS IN > > + * THE SOFTWARE. > > + */ > > + > > +#include "qemu/osdep.h" > > +#include "qemu/main-loop.h" > > +#include "qemu/log.h" > > +#include "hw/timer/mss-timer.h" > > + > > +#ifndef MSS_TIMER_ERR_DEBUG > > +#define MSS_TIMER_ERR_DEBUG 0 > > +#endif > > + > > +#define DB_PRINT_L(lvl, fmt, args...) do { \ > > + if (MSS_TIMER_ERR_DEBUG >= lvl) { \ > > + qemu_log("%s: " fmt "\n", __func__, ## args); \ > > + } \ > > +} while (0); > > + > > +#define DB_PRINT(fmt, args...) DB_PRINT_L(1, fmt, ## args) > > + > > +#define R_TIM_VAL 0 > > +#define R_TIM_LOADVAL 1 > > +#define R_TIM_BGLOADVAL 2 > > +#define R_TIM_CTRL 3 > > +#define R_TIM_RIS 4 > > +#define R_TIM_MIS 5 > > + > > +#define TIMER_CTRL_ENBL (1 << 0) > > +#define TIMER_CTRL_ONESHOT (1 << 1) > > +#define TIMER_CTRL_INTR (1 << 2) > > +#define TIMER_RIS_ACK (1 << 0) > > +#define TIMER_RST_CLR (1 << 6) > > +#define TIMER_MODE (1 << 0) > > + > > +static void timer_update_irq(struct Msf2Timer *st) > > +{ > > + bool isr, ier; > > + > > + isr = !!(st->regs[R_TIM_RIS] & TIMER_RIS_ACK); > > + ier = !!(st->regs[R_TIM_CTRL] & TIMER_CTRL_INTR); > > + qemu_set_irq(st->irq, (ier && isr)); > > +} > > + > > +static void timer_update(struct Msf2Timer *st) > > +{ > > + uint64_t count; > > + > > + if (!(st->regs[R_TIM_CTRL] & TIMER_CTRL_ENBL)) { > > + ptimer_stop(st->ptimer); > > + return; > > + } > > + > > + count = st->regs[R_TIM_LOADVAL]; > > + ptimer_set_limit(st->ptimer, count, 1); > > + ptimer_run(st->ptimer, 1); > > +} > > + > > +static uint64_t > > +timer_read(void *opaque, hwaddr offset, unsigned int size) > > +{ > > + MSSTimerState *t = opaque; > > + hwaddr addr; > > + struct Msf2Timer *st; > > + uint32_t ret = 0; > > + int timer = 0; > > + int isr; > > + int ier; > > + > > + addr = offset >> 2; > > + /* > > + * Two independent timers has same base address. > > + * Based on address passed figure out which timer is being used. > > + */ > > + if ((addr >= R_TIM1_MAX) && (addr < NUM_TIMERS * R_TIM1_MAX)) { > > + timer = 1; > > + addr -= R_TIM1_MAX; > > + } > > + > > + st = &t->timers[timer]; > > + > > + switch (addr) { > > + case R_TIM_VAL: > > + ret = ptimer_get_count(st->ptimer); > > + break; > > + > > + case R_TIM_MIS: > > + isr = !!(st->regs[R_TIM_RIS] & TIMER_RIS_ACK); > > + ier = !!(st->regs[R_TIM_CTRL] & TIMER_CTRL_INTR); > > + ret = ier & isr; > > + break; > > + > > + default: > > + if (addr < R_TIM1_MAX) { > > + ret = st->regs[addr]; > > + } else { > > + qemu_log_mask(LOG_GUEST_ERROR, > > + TYPE_MSS_TIMER": 64-bit mode not supported\n"); > > + return ret; > > + } > > + break; > > + } > > + > > + DB_PRINT("timer=%d 0x%" HWADDR_PRIx "=0x%" PRIx32, timer, offset, > > + ret); > > + return ret; > > +} > > + > > +static void > > +timer_write(void *opaque, hwaddr offset, > > + uint64_t val64, unsigned int size) > > +{ > > + MSSTimerState *t = opaque; > > + hwaddr addr; > > + struct Msf2Timer *st; > > + int timer = 0; > > + uint32_t value = val64; > > + > > + addr = offset >> 2; > > + /* > > + * Two independent timers has same base address. > > + * Based on addr passed figure out which timer is being used. > > + */ > > + if ((addr >= R_TIM1_MAX) && (addr < NUM_TIMERS * R_TIM1_MAX)) { > > + timer = 1; > > + addr -= R_TIM1_MAX; > > + } > > + > > + st = &t->timers[timer]; > > + > > + DB_PRINT("addr=0x%" HWADDR_PRIx " val=0x%" PRIx32 " (timer=%d)", > offset, > > + value, timer); > > + > > + switch (addr) { > > + case R_TIM_CTRL: > > + st->regs[R_TIM_CTRL] = value; > > + timer_update(st); > > + break; > > + > > + case R_TIM_RIS: > > + if (value & TIMER_RIS_ACK) { > > + st->regs[R_TIM_RIS] &= ~TIMER_RIS_ACK; > > + } > > + break; > > + > > + case R_TIM_LOADVAL: > > + st->regs[R_TIM_LOADVAL] = value; > > + if (st->regs[R_TIM_CTRL] & TIMER_CTRL_ENBL) { > > + timer_update(st); > > + } > > + break; > > + > > + case R_TIM_BGLOADVAL: > > + st->regs[R_TIM_BGLOADVAL] = value; > > + st->regs[R_TIM_LOADVAL] = value; > > + break; > > + > > + case R_TIM_VAL: > > + case R_TIM_MIS: > > + break; > > + > > + default: > > + if (addr < R_TIM1_MAX) { > > + st->regs[addr] = value; > > + } else { > > + qemu_log_mask(LOG_GUEST_ERROR, > > + TYPE_MSS_TIMER": 64-bit mode not supported\n"); > > + return; > > + } > > + break; > > + } > > + timer_update_irq(st); > > +} > > + > > +static const MemoryRegionOps timer_ops = { > > + .read = timer_read, > > + .write = timer_write, > > + .endianness = DEVICE_NATIVE_ENDIAN, > > + .valid = { > > + .min_access_size = 1, > > + .max_access_size = 4 > > + } > > +}; > > + > > +static void timer_hit(void *opaque) > > +{ > > + struct Msf2Timer *st = opaque; > > + > > + st->regs[R_TIM_RIS] |= TIMER_RIS_ACK; > > + > > + if (!(st->regs[R_TIM_CTRL] & TIMER_CTRL_ONESHOT)) { > > + timer_update(st); > > + } > > + timer_update_irq(st); > > +} > > + > > +static void mss_timer_init(Object *obj) > > +{ > > + MSSTimerState *t = MSS_TIMER(obj); > > + int i; > > + > > + /* Init all the ptimers. */ > > + for (i = 0; i < NUM_TIMERS; i++) { > > + struct Msf2Timer *st = &t->timers[i]; > > + > > + st->bh = qemu_bh_new(timer_hit, st); > > + st->ptimer = ptimer_init(st->bh, PTIMER_POLICY_DEFAULT); > > + ptimer_set_freq(st->ptimer, t->freq_hz); > > + sysbus_init_irq(SYS_BUS_DEVICE(obj), &st->irq); > > + } > > + > > + memory_region_init_io(&t->mmio, OBJECT(t), &timer_ops, t, > TYPE_MSS_TIMER, > > + NUM_TIMERS * R_TIM1_MAX * 4); > > + sysbus_init_mmio(SYS_BUS_DEVICE(obj), &t->mmio); > > +} > > + > > +static const VMStateDescription vmstate_timers = { > > + .name = "mss-timer-block", > > + .version_id = 1, > > + .minimum_version_id = 1, > > + .fields = (VMStateField[]) { > > + VMSTATE_PTIMER(ptimer, struct Msf2Timer), > > + VMSTATE_UINT32_ARRAY(regs, struct Msf2Timer, R_TIM1_MAX), > > + VMSTATE_END_OF_LIST() > > + } > > +}; > > + > > +static const VMStateDescription vmstate_mss_timer = { > > + .name = TYPE_MSS_TIMER, > > + .version_id = 1, > > + .minimum_version_id = 1, > > + .fields = (VMStateField[]) { > > + VMSTATE_UINT32(freq_hz, MSSTimerState), > > + VMSTATE_STRUCT_ARRAY(timers, MSSTimerState, NUM_TIMERS, 0, > > + vmstate_timers, struct Msf2Timer), > > + VMSTATE_END_OF_LIST() > > + } > > +}; > > + > > +static Property mss_timer_properties[] = { > > + /* Libero GUI shows 100Mhz as default for clocks */ > > + DEFINE_PROP_UINT32("clock-frequency", MSSTimerState, freq_hz, > > + 100 * 1000000), > > + DEFINE_PROP_END_OF_LIST(), > > +}; > > + > > +static void mss_timer_class_init(ObjectClass *klass, void *data) > > +{ > > + DeviceClass *dc = DEVICE_CLASS(klass); > > + > > + dc->props = mss_timer_properties; > > + dc->vmsd = &vmstate_mss_timer; > > +} > > + > > +static const TypeInfo mss_timer_info = { > > + .name = TYPE_MSS_TIMER, > > + .parent = TYPE_SYS_BUS_DEVICE, > > + .instance_size = sizeof(MSSTimerState), > > + .instance_init = mss_timer_init, > > + .class_init = mss_timer_class_init, > > +}; > > + > > +static void mss_timer_register_types(void) > > +{ > > + type_register_static(&mss_timer_info); > > +} > > + > > +type_init(mss_timer_register_types) > > diff --git a/include/hw/timer/mss-timer.h b/include/hw/timer/mss-timer.h > > new file mode 100644 > > index 0000000..d15d173 > > --- /dev/null > > +++ b/include/hw/timer/mss-timer.h > > @@ -0,0 +1,64 @@ > > +/* > > + * Microsemi SmartFusion2 Timer. > > + * > > + * Copyright (c) 2017 Subbaraya Sundeep > > + * > > + * Permission is hereby granted, free of charge, to any person > obtaining a copy > > + * of this software and associated documentation files (the > "Software"), to deal > > + * in the Software without restriction, including without limitation > the rights > > + * to use, copy, modify, merge, publish, distribute, sublicense, and/or > sell > > + * copies of the Software, and to permit persons to whom the Software is > > + * furnished to do so, subject to the following conditions: > > + * > > + * The above copyright notice and this permission notice shall be > included in > > + * all copies or substantial portions of the Software. > > + * > > + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, > EXPRESS OR > > + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF > MERCHANTABILITY, > > + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT > SHALL > > + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR > OTHER > > + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, > ARISING FROM, > > + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER > DEALINGS IN > > + * THE SOFTWARE. > > + */ > > + > > +#ifndef HW_MSS_TIMER_H > > +#define HW_MSS_TIMER_H > > + > > +#include "hw/sysbus.h" > > +#include "hw/ptimer.h" > > + > > +#define TYPE_MSS_TIMER "mss-timer" > > +#define MSS_TIMER(obj) OBJECT_CHECK(MSSTimerState, \ > > + (obj), TYPE_MSS_TIMER) > > + > > +/* > > + * There are two 32-bit down counting timers. > > + * Timers 1 and 2 can be concatenated into a single 64-bit Timer > > + * that operates either in Periodic mode or in One-shot mode. > > + * Writing 1 to the TIM64_MODE register bit 0 sets the Timers in 64-bit > mode. > > + * In 64-bit mode, writing to the 32-bit registers has no effect. > > + * Similarly, in 32-bit mode, writing to the 64-bit mode registers > > + * has no effect. Only two 32-bit timers are supported currently. > > + */ > > +#define NUM_TIMERS 2 > > + > > +#define R_TIM1_MAX 6 > > + > > +struct Msf2Timer { > > + QEMUBH *bh; > > + ptimer_state *ptimer; > > + > > + uint32_t regs[R_TIM1_MAX]; > > + qemu_irq irq; > > +}; > > + > > +typedef struct MSSTimerState { > > + SysBusDevice parent_obj; > > + > > + MemoryRegion mmio; > > + uint32_t freq_hz; > > + struct Msf2Timer timers[NUM_TIMERS]; > > +} MSSTimerState; > > + > > +#endif /* HW_MSS_TIMER_H */ > > -- > > 2.5.0 > > > --001a114ccd3295d0c40557ddbc05 Content-Type: text/html; charset="UTF-8" Content-Transfer-Encoding: quoted-printable
Hi Alistair,

On Tue, Aug 29, 2017 at 3:23 AM, Alistair Francis <alistair= 23@gmail.com> wrote:
On Mon, Aug 28, 2017 at 9:37 AM, Subbaraya Sundeep
<sundeep.lkml@gmail.com>= ; wrote:
> Modelled System Timer in Microsemi's Smartfusion2 Soc.
> Timer has two 32bit down counters and two interrupts.
>
> Signed-off-by: Subbaraya Sundeep <sundeep.lkml@gmail.com>

I had already reviewed this patch in v6. As long as you have made al= l
of the changes mentioned their you can add my reviewed-by to the next
version (as long as there are no other significant changes).

Can you please ensure you do add and keep reviewed-by tags, it's a
pain to have to do it multiple times.

S= orry I was not aware that I can add reviewed by tag myself and send.
<= div>I will add your reviewed by since I fixed all your comments.
= Do I need to send another version v8 with your Reviewed-by ?

=
Thanks,
Sundeep
=C2=A0

Thanks,
Alistair

> ---
>=C2=A0 hw/timer/Makefile.objs=C2=A0 =C2=A0 =C2=A0 =C2=A0|=C2=A0 =C2=A01= +
>=C2=A0 hw/timer/mss-timer.c=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0| 289 ++++= +++++++++++++++++++++++++++++++++++++++
>=C2=A0 include/hw/timer/mss-timer.h |=C2=A0 64 ++++++++++
>=C2=A0 3 files changed, 354 insertions(+)
>=C2=A0 create mode 100644 hw/timer/mss-timer.c
>=C2=A0 create mode 100644 include/hw/timer/mss-timer.h
>
> diff --git a/hw/timer/Makefile.objs b/hw/timer/Makefile.objs
> index 15cce1c..8c19eac 100644
> --- a/hw/timer/Makefile.objs
> +++ b/hw/timer/Makefile.objs
> @@ -42,3 +42,4 @@ common-obj-$(CONFIG_ASPEED_SOC) +=3D aspeed_tim= er.o
>
>=C2=A0 common-obj-$(CONFIG_SUN4V_RTC) +=3D sun4v-rtc.o
>=C2=A0 common-obj-$(CONFIG_CMSDK_APB_TIMER) +=3D cmsdk-apb-timer.o=
> +common-obj-$(CONFIG_MSF2) +=3D mss-timer.o
> diff --git a/hw/timer/mss-timer.c b/hw/timer/mss-timer.c
> new file mode 100644
> index 0000000..60f1213
> --- /dev/null
> +++ b/hw/timer/mss-timer.c
> @@ -0,0 +1,289 @@
> +/*
> + * Block model of System timer present in
> + * Microsemi's SmartFusion2 and SmartFusion SoCs.
> + *
> + * Copyright (c) 2017 Subbaraya Sundeep <sundeep.lkml@gmail.com>.
> + *
> + * Permission is hereby granted, free of charge, to any person obtain= ing a copy
> + * of this software and associated documentation files (the "Sof= tware"), to deal
> + * in the Software without restriction, including without limitation = the rights
> + * to use, copy, modify, merge, publish, distribute, sublicense, and/= or sell
> + * copies of the Software, and to permit persons to whom the Software= is
> + * furnished to do so, subject to the following conditions:
> + *
> + * The above copyright notice and this permission notice shall be inc= luded in
> + * all copies or substantial portions of the Software.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF AN= Y KIND, EXPRESS OR
> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTAB= ILITY,
> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT = SHALL
> + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES = OR OTHER
> + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, AR= ISING FROM,
> + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEAL= INGS IN
> + * THE SOFTWARE.
> + */
> +
> +#include "qemu/osdep.h"
> +#include "qemu/main-loop.h"
> +#include "qemu/log.h"
> +#include "hw/timer/mss-timer.h"
> +
> +#ifndef MSS_TIMER_ERR_DEBUG
> +#define MSS_TIMER_ERR_DEBUG=C2=A0 0
> +#endif
> +
> +#define DB_PRINT_L(lvl, fmt, args...) do { \
> +=C2=A0 =C2=A0 if (MSS_TIMER_ERR_DEBUG >=3D lvl) { \
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 qemu_log("%s: " fmt "\n&qu= ot;, __func__, ## args); \
> +=C2=A0 =C2=A0 } \
> +} while (0);
> +
> +#define DB_PRINT(fmt, args...) DB_PRINT_L(1, fmt, ## args)
> +
> +#define R_TIM_VAL=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A00
> +#define R_TIM_LOADVAL=C2=A0 =C2=A0 =C2=A01
> +#define R_TIM_BGLOADVAL=C2=A0 =C2=A02
> +#define R_TIM_CTRL=C2=A0 =C2=A0 =C2=A0 =C2=A0 3
> +#define R_TIM_RIS=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A04
> +#define R_TIM_MIS=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A05
> +
> +#define TIMER_CTRL_ENBL=C2=A0 =C2=A0 =C2=A0(1 << 0)
> +#define TIMER_CTRL_ONESHOT=C2=A0 (1 << 1)
> +#define TIMER_CTRL_INTR=C2=A0 =C2=A0 =C2=A0(1 << 2)
> +#define TIMER_RIS_ACK=C2=A0 =C2=A0 =C2=A0 =C2=A0(1 << 0)
> +#define TIMER_RST_CLR=C2=A0 =C2=A0 =C2=A0 =C2=A0(1 << 6)
> +#define TIMER_MODE=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 (1 << 0) > +
> +static void timer_update_irq(struct Msf2Timer *st)
> +{
> +=C2=A0 =C2=A0 bool isr, ier;
> +
> +=C2=A0 =C2=A0 isr =3D !!(st->regs[R_TIM_RIS] & TIMER_RIS_ACK);=
> +=C2=A0 =C2=A0 ier =3D !!(st->regs[R_TIM_CTRL] & TIMER_CTRL_INT= R);
> +=C2=A0 =C2=A0 qemu_set_irq(st->irq, (ier && isr));
> +}
> +
> +static void timer_update(struct Msf2Timer *st)
> +{
> +=C2=A0 =C2=A0 uint64_t count;
> +
> +=C2=A0 =C2=A0 if (!(st->regs[R_TIM_CTRL] & TIMER_CTRL_ENBL)) {=
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 ptimer_stop(st->ptimer);
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 return;
> +=C2=A0 =C2=A0 }
> +
> +=C2=A0 =C2=A0 count =3D st->regs[R_TIM_LOADVAL];
> +=C2=A0 =C2=A0 ptimer_set_limit(st->ptimer, count, 1);
> +=C2=A0 =C2=A0 ptimer_run(st->ptimer, 1);
> +}
> +
> +static uint64_t
> +timer_read(void *opaque, hwaddr offset, unsigned int size)
> +{
> +=C2=A0 =C2=A0 MSSTimerState *t =3D opaque;
> +=C2=A0 =C2=A0 hwaddr addr;
> +=C2=A0 =C2=A0 struct Msf2Timer *st;
> +=C2=A0 =C2=A0 uint32_t ret =3D 0;
> +=C2=A0 =C2=A0 int timer =3D 0;
> +=C2=A0 =C2=A0 int isr;
> +=C2=A0 =C2=A0 int ier;
> +
> +=C2=A0 =C2=A0 addr =3D offset >> 2;
> +=C2=A0 =C2=A0 /*
> +=C2=A0 =C2=A0 =C2=A0* Two independent timers has same base address. > +=C2=A0 =C2=A0 =C2=A0* Based on address passed figure out which timer = is being used.
> +=C2=A0 =C2=A0 =C2=A0*/
> +=C2=A0 =C2=A0 if ((addr >=3D R_TIM1_MAX) && (addr < NUM= _TIMERS * R_TIM1_MAX)) {
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 timer =3D 1;
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 addr -=3D R_TIM1_MAX;
> +=C2=A0 =C2=A0 }
> +
> +=C2=A0 =C2=A0 st =3D &t->timers[timer];
> +
> +=C2=A0 =C2=A0 switch (addr) {
> +=C2=A0 =C2=A0 case R_TIM_VAL:
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 ret =3D ptimer_get_count(st->ptimer);<= br> > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 break;
> +
> +=C2=A0 =C2=A0 case R_TIM_MIS:
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 isr =3D !!(st->regs[R_TIM_RIS] & T= IMER_RIS_ACK);
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 ier =3D !!(st->regs[R_TIM_CTRL] & = TIMER_CTRL_INTR);
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 ret =3D ier & isr;
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 break;
> +
> +=C2=A0 =C2=A0 default:
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 if (addr < R_TIM1_MAX) {
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 ret =3D st->regs[addr];<= br> > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 } else {
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 qemu_log_mask(LOG_GUEST_ERR= OR,
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0 TYPE_MSS_TIMER": 64-bit mode not supported\n"); > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 return ret;
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 }
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 break;
> +=C2=A0 =C2=A0 }
> +
> +=C2=A0 =C2=A0 DB_PRINT("timer=3D%d 0x%" HWADDR_PRIx "= =3D0x%" PRIx32, timer, offset,
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 ret);
> +=C2=A0 =C2=A0 return ret;
> +}
> +
> +static void
> +timer_write(void *opaque, hwaddr offset,
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 uint64_t val64, unsigned in= t size)
> +{
> +=C2=A0 =C2=A0 MSSTimerState *t =3D opaque;
> +=C2=A0 =C2=A0 hwaddr addr;
> +=C2=A0 =C2=A0 struct Msf2Timer *st;
> +=C2=A0 =C2=A0 int timer =3D 0;
> +=C2=A0 =C2=A0 uint32_t value =3D val64;
> +
> +=C2=A0 =C2=A0 addr =3D offset >> 2;
> +=C2=A0 =C2=A0 /*
> +=C2=A0 =C2=A0 =C2=A0* Two independent timers has same base address. > +=C2=A0 =C2=A0 =C2=A0* Based on addr passed figure out which timer is = being used.
> +=C2=A0 =C2=A0 =C2=A0*/
> +=C2=A0 =C2=A0 if ((addr >=3D R_TIM1_MAX) && (addr < NUM= _TIMERS * R_TIM1_MAX)) {
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 timer =3D 1;
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 addr -=3D R_TIM1_MAX;
> +=C2=A0 =C2=A0 }
> +
> +=C2=A0 =C2=A0 st =3D &t->timers[timer];
> +
> +=C2=A0 =C2=A0 DB_PRINT("addr=3D0x%" HWADDR_PRIx " val= =3D0x%" PRIx32 " (timer=3D%d)", offset,
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 value, timer);
> +
> +=C2=A0 =C2=A0 switch (addr) {
> +=C2=A0 =C2=A0 case R_TIM_CTRL:
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 st->regs[R_TIM_CTRL] =3D value;
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 timer_update(st);
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 break;
> +
> +=C2=A0 =C2=A0 case R_TIM_RIS:
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 if (value & TIMER_RIS_ACK) {
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 st->regs[R_TIM_RIS] &= ;=3D ~TIMER_RIS_ACK;
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 }
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 break;
> +
> +=C2=A0 =C2=A0 case R_TIM_LOADVAL:
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 st->regs[R_TIM_LOADVAL] =3D value;
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 if (st->regs[R_TIM_CTRL] & TIMER_C= TRL_ENBL) {
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 timer_update(st);
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 }
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 break;
> +
> +=C2=A0 =C2=A0 case R_TIM_BGLOADVAL:
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 st->regs[R_TIM_BGLOADVAL] =3D value; > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 st->regs[R_TIM_LOADVAL] =3D value;
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 break;
> +
> +=C2=A0 =C2=A0 case R_TIM_VAL:
> +=C2=A0 =C2=A0 case R_TIM_MIS:
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 break;
> +
> +=C2=A0 =C2=A0 default:
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 if (addr < R_TIM1_MAX) {
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 st->regs[addr] =3D value= ;
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 } else {
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 qemu_log_mask(LOG_GUEST_ERR= OR,
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0 TYPE_MSS_TIMER": 64-bit mode not supported\n"); > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 return;
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 }
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 break;
> +=C2=A0 =C2=A0 }
> +=C2=A0 =C2=A0 timer_update_irq(st);
> +}
> +
> +static const MemoryRegionOps timer_ops =3D {
> +=C2=A0 =C2=A0 .read =3D timer_read,
> +=C2=A0 =C2=A0 .write =3D timer_write,
> +=C2=A0 =C2=A0 .endianness =3D DEVICE_NATIVE_ENDIAN,
> +=C2=A0 =C2=A0 .valid =3D {
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 .min_access_size =3D 1,
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 .max_access_size =3D 4
> +=C2=A0 =C2=A0 }
> +};
> +
> +static void timer_hit(void *opaque)
> +{
> +=C2=A0 =C2=A0 struct Msf2Timer *st =3D opaque;
> +
> +=C2=A0 =C2=A0 st->regs[R_TIM_RIS] |=3D TIMER_RIS_ACK;
> +
> +=C2=A0 =C2=A0 if (!(st->regs[R_TIM_CTRL] & TIMER_CTRL_ONESHOT)= ) {
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 timer_update(st);
> +=C2=A0 =C2=A0 }
> +=C2=A0 =C2=A0 timer_update_irq(st);
> +}
> +
> +static void mss_timer_init(Object *obj)
> +{
> +=C2=A0 =C2=A0 MSSTimerState *t =3D MSS_TIMER(obj);
> +=C2=A0 =C2=A0 int i;
> +
> +=C2=A0 =C2=A0 /* Init all the ptimers.=C2=A0 */
> +=C2=A0 =C2=A0 for (i =3D 0; i < NUM_TIMERS; i++) {
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 struct Msf2Timer *st =3D &t->timer= s[i];
> +
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 st->bh =3D qemu_bh_new(timer_hit, st);=
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 st->ptimer =3D ptimer_init(st->bh, = PTIMER_POLICY_DEFAULT);
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 ptimer_set_freq(st->ptimer, t->freq= _hz);
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 sysbus_init_irq(SYS_BUS_DEVICE(obj),= &st->irq);
> +=C2=A0 =C2=A0 }
> +
> +=C2=A0 =C2=A0 memory_region_init_io(&t->mmio, OBJECT(t), = &timer_ops, t, TYPE_MSS_TIMER,
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0 =C2=A0 NUM_TIMERS * R_TIM1_MAX * 4);
> +=C2=A0 =C2=A0 sysbus_init_mmio(SYS_BUS_DEVICE(obj), &t->m= mio);
> +}
> +
> +static const VMStateDescription vmstate_timers =3D {
> +=C2=A0 =C2=A0 .name =3D "mss-timer-block",
> +=C2=A0 =C2=A0 .version_id =3D 1,
> +=C2=A0 =C2=A0 .minimum_version_id =3D 1,
> +=C2=A0 =C2=A0 .fields =3D (VMStateField[]) {
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 VMSTATE_PTIMER(ptimer, struct Msf2Timer),=
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 VMSTATE_UINT32_ARRAY(regs, struct Msf2Tim= er, R_TIM1_MAX),
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 VMSTATE_END_OF_LIST()
> +=C2=A0 =C2=A0 }
> +};
> +
> +static const VMStateDescription vmstate_mss_timer =3D {
> +=C2=A0 =C2=A0 .name =3D TYPE_MSS_TIMER,
> +=C2=A0 =C2=A0 .version_id =3D 1,
> +=C2=A0 =C2=A0 .minimum_version_id =3D 1,
> +=C2=A0 =C2=A0 .fields =3D (VMStateField[]) {
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 VMSTATE_UINT32(freq_hz, MSSTimerState), > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 VMSTATE_STRUCT_ARRAY(timers, MSSTimerStat= e, NUM_TIMERS, 0,
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 vmstate_timer= s, struct Msf2Timer),
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 VMSTATE_END_OF_LIST()
> +=C2=A0 =C2=A0 }
> +};
> +
> +static Property mss_timer_properties[] =3D {
> +=C2=A0 =C2=A0 /* Libero GUI shows 100Mhz as default for clocks */
> +=C2=A0 =C2=A0 DEFINE_PROP_UINT32("clock-frequency", MS= STimerState, freq_hz,
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 100 * 1000000),
> +=C2=A0 =C2=A0 DEFINE_PROP_END_OF_LIST(),
> +};
> +
> +static void mss_timer_class_init(ObjectClass *klass, void *data)=
> +{
> +=C2=A0 =C2=A0 DeviceClass *dc =3D DEVICE_CLASS(klass);
> +
> +=C2=A0 =C2=A0 dc->props =3D mss_timer_properties;
> +=C2=A0 =C2=A0 dc->vmsd =3D &vmstate_mss_timer;
> +}
> +
> +static const TypeInfo mss_timer_info =3D {
> +=C2=A0 =C2=A0 .name=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =3D TYPE_MSS_TI= MER,
> +=C2=A0 =C2=A0 .parent=C2=A0 =C2=A0 =C2=A0 =C2=A0 =3D TYPE_SYS_BUS_DEV= ICE,
> +=C2=A0 =C2=A0 .instance_size =3D sizeof(MSSTimerState),
> +=C2=A0 =C2=A0 .instance_init =3D mss_timer_init,
> +=C2=A0 =C2=A0 .class_init=C2=A0 =C2=A0 =3D mss_timer_class_init,
> +};
> +
> +static void mss_timer_register_types(void)
> +{
> +=C2=A0 =C2=A0 type_register_static(&mss_timer_info);
> +}
> +
> +type_init(mss_timer_register_types)
> diff --git a/include/hw/timer/mss-timer.h b/include/hw/timer/mss-timer= .h
> new file mode 100644
> index 0000000..d15d173
> --- /dev/null
> +++ b/include/hw/timer/mss-timer.h
> @@ -0,0 +1,64 @@
> +/*
> + * Microsemi SmartFusion2 Timer.
> + *
> + * Copyright (c) 2017 Subbaraya Sundeep <sundeep.lkml@gmail.com>
> + *
> + * Permission is hereby granted, free of charge, to any person obtain= ing a copy
> + * of this software and associated documentation files (the "Sof= tware"), to deal
> + * in the Software without restriction, including without limitation = the rights
> + * to use, copy, modify, merge, publish, distribute, sublicense, and/= or sell
> + * copies of the Software, and to permit persons to whom the Software= is
> + * furnished to do so, subject to the following conditions:
> + *
> + * The above copyright notice and this permission notice shall be inc= luded in
> + * all copies or substantial portions of the Software.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF AN= Y KIND, EXPRESS OR
> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTAB= ILITY,
> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT = SHALL
> + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES = OR OTHER
> + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, AR= ISING FROM,
> + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEAL= INGS IN
> + * THE SOFTWARE.
> + */
> +
> +#ifndef HW_MSS_TIMER_H
> +#define HW_MSS_TIMER_H
> +
> +#include "hw/sysbus.h"
> +#include "hw/ptimer.h"
> +
> +#define TYPE_MSS_TIMER=C2=A0 =C2=A0 =C2=A0"mss-timer"
> +#define MSS_TIMER(obj)=C2=A0 =C2=A0 =C2=A0OBJECT_CHECK(MSSTimerState,= \
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 (obj), TYPE_MSS_TIMER)
> +
> +/*
> + * There are two 32-bit down counting timers.
> + * Timers 1 and 2 can be concatenated into a single 64-bit Timer
> + * that operates either in Periodic mode or in One-shot mode.
> + * Writing 1 to the TIM64_MODE register bit 0 sets the Timers in 64-b= it mode.
> + * In 64-bit mode, writing to the 32-bit registers has no effect.
> + * Similarly, in 32-bit mode, writing to the 64-bit mode registers > + * has no effect. Only two 32-bit timers are supported currently.
> + */
> +#define NUM_TIMERS=C2=A0 =C2=A0 =C2=A0 =C2=A0 2
> +
> +#define R_TIM1_MAX=C2=A0 =C2=A0 =C2=A0 =C2=A0 6
> +
> +struct Msf2Timer {
> +=C2=A0 =C2=A0 QEMUBH *bh;
> +=C2=A0 =C2=A0 ptimer_state *ptimer;
> +
> +=C2=A0 =C2=A0 uint32_t regs[R_TIM1_MAX];
> +=C2=A0 =C2=A0 qemu_irq irq;
> +};
> +
> +typedef struct MSSTimerState {
> +=C2=A0 =C2=A0 SysBusDevice parent_obj;
> +
> +=C2=A0 =C2=A0 MemoryRegion mmio;
> +=C2=A0 =C2=A0 uint32_t freq_hz;
> +=C2=A0 =C2=A0 struct Msf2Timer timers[NUM_TIMERS];
> +} MSSTimerState;
> +
> +#endif /* HW_MSS_TIMER_H */
> --
> 2.5.0
>

--001a114ccd3295d0c40557ddbc05-- From MAILER-DAEMON Tue Aug 29 02:33:24 2017 Received: from list by lists.gnu.org with archive (Exim 4.71) id 1dma5U-0000QT-24 for mharc-qemu-arm@gnu.org; Tue, 29 Aug 2017 02:33:24 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:38836) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dma5Q-0000Oy-II for qemu-arm@nongnu.org; Tue, 29 Aug 2017 02:33:21 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dma5N-00041j-Bx for qemu-arm@nongnu.org; Tue, 29 Aug 2017 02:33:20 -0400 Received: from mail-yw0-x243.google.com ([2607:f8b0:4002:c05::243]:35714) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1dma5N-00041I-7U; Tue, 29 Aug 2017 02:33:17 -0400 Received: by mail-yw0-x243.google.com with SMTP id s187so1493335ywf.2; Mon, 28 Aug 2017 23:33:15 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id; bh=EeJB1MzeDnxqmqJAMcJ2s+Y6u9V1bZlXzyvC5M7QcVw=; b=WyZahPOg51JBo5OT8Qi478vvJxn1nGwJHZbzFUznVj2iqDlfJYHGn9+MqjMXyrPrhw tSqKPm6H2Gxxgkb6zIovIjlz36cTq0U/VwctF3DW8TLT0ONPtw+sRKx34Ov2DOT+/lFP DPDZ5QF1YcBWgqXAax/gyA0osJZiT8rmF8w/Ngliyy/5JWC2O4Jp81+YNoaORbEztQem O+4K1pc/CNxQt+4htjGT211uUl0MzmMOhfdmq17t6MolL03A8nhjzwNRLmHp28CWIlb3 EDbqJMCjgEXDBY2y+VT7l4ClElKpXBDOSdt4Li9j95gtfZr8z/paFWR5w9HI93IdHBQ9 iTag== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=EeJB1MzeDnxqmqJAMcJ2s+Y6u9V1bZlXzyvC5M7QcVw=; b=Ll+33TpEqbzrqvP9fKE3dqduL2pSLKm7CgDDI4eHfCjy9D0fTKuFibTaNlFwimFeFM SdRj7jZGFEpipDvjOI2VXAGWScoj3QQkLLGE5JjnO/fDPEFg9HnOb92Yeym1yhU0okiN IvF929zbS8mLqL+7YySnxbP55E6RJ9UFtQSZ1r53Q5fVrpNgt2r4siFVJe8aOaFeEtqt hbi0HYIVCyG6TErotu75n5d/Ld3p/fJGiDJ83rc5KpAOq5hXMbvfnd4wgjb+9rP0lEOe 0FpCSxMuvNZUAyCZ2CFFFx0WkSg3ITxAdoIoTvAlcrjg1gWB+uoeVU1wVv3/DzZlF2vG RUXQ== X-Gm-Message-State: AHYfb5iHdyBClfMkZ4t6WQsAR2I7IKpgzQxvpWjhDmFN14uQ8SkQEB34 jL1QUFl4WEfu3A== X-Received: by 10.129.109.18 with SMTP id i18mr2557944ywc.271.1503988395299; Mon, 28 Aug 2017 23:33:15 -0700 (PDT) Received: from localhost.localdomain ([98.192.46.210]) by smtp.gmail.com with ESMTPSA id x4sm817923ywa.44.2017.08.28.23.33.14 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 28 Aug 2017 23:33:14 -0700 (PDT) From: Pranith Kumar To: alex.bennee@linaro.org, Peter Maydell , qemu-arm@nongnu.org (open list:ARM), qemu-devel@nongnu.org (open list:All patches CC here) Cc: qemu-devel@nongnu.org, rth@twiddle.net, pbonzini@redhat.com Date: Tue, 29 Aug 2017 02:33:09 -0400 Message-Id: <20170829063313.10237-1-bobby.prani@gmail.com> X-Mailer: git-send-email 2.13.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4002:c05::243 Subject: [Qemu-arm] [PATCH 1/5] target/arm: Remove stale comment X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 29 Aug 2017 06:33:21 -0000 Update the comment which is not true since MTTCG. Reviewed-by: Richard Henderson Signed-off-by: Pranith Kumar --- target/arm/translate-a64.c | 4 ---- 1 file changed, 4 deletions(-) diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 2200e25be0..f42b155d7d 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -2012,10 +2012,6 @@ static void disas_ldst_excl(DisasContext *s, uint32_t insn) } tcg_addr = read_cpu_reg_sp(s, rn, 1); - /* Note that since TCG is single threaded load-acquire/store-release - * semantics require no extra if (is_lasr) { ... } handling. - */ - if (is_excl) { if (!is_store) { s->is_ldex = true; -- 2.13.0 From MAILER-DAEMON Tue Aug 29 02:33:24 2017 Received: from list by lists.gnu.org with archive (Exim 4.71) id 1dma5U-0000Qd-5F for mharc-qemu-arm@gnu.org; Tue, 29 Aug 2017 02:33:24 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:38838) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dma5Q-0000P0-Ih for qemu-arm@nongnu.org; Tue, 29 Aug 2017 02:33:21 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dma5P-00042C-5m for qemu-arm@nongnu.org; Tue, 29 Aug 2017 02:33:20 -0400 Received: from mail-yw0-x241.google.com ([2607:f8b0:4002:c05::241]:37238) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1dma5P-000427-19; Tue, 29 Aug 2017 02:33:19 -0400 Received: by mail-yw0-x241.google.com with SMTP id s143so1484892ywg.4; Mon, 28 Aug 2017 23:33:18 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=7cyqdcqT7XR/NRo3PwV57yOZ8y6Or0EHZ7FWsTFdhh4=; b=H/nljru4Bbz8uSXStjX0osnHR2stHKc2Ih1NZqthue6gFvGx2+/rD/LoN4biNch9V5 WjWwiSXB+bb5uF6j7Om7eSJ6o3ESE51eP599e2K1JElzhfU716GnAshdsgNwBvZFbVgx 8RKNLjm23cXM7CEXohWKrU1udksYu75K3BmemrO0nLum9CmgZygA6gLIPLMAOehQsQTr eq86r5uxrsICwdIrzJD886sseAIiVqQlcK67DOCT6tFitMzMg8aGDtdY6cJGQkgQFJgg yoBFkNGFlGkBZJ9zIkq6PCjH+dG2S74hTCvWssQlUujPCoTQ2L6A9FgkJ6WiBICJKMaE H9ug== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=7cyqdcqT7XR/NRo3PwV57yOZ8y6Or0EHZ7FWsTFdhh4=; b=L9tLdV9YOF5b2F0FLfCTNaxOhWGLI6n/BJN6o1wLHvR9Y7/WikV7dB/P67+eAeNV6p XLTeTqm2GAuu+0uU0ubb8r4CRLiOZefOiP+K2rzD8I3cCekZWBx6Vw7jawGzygvzbywK AYKCeeiE6TBb5XOrndYpueKVW2HBqaP6DApkFw7f9wuMwyXUtOGPh6J6fHxg45PsV4m5 cfZ2Bj631C3etF7Gqel0S1oy1EOB1OKE7bGX+eFFcUliCIemciTkJJQRUp7Kd4Q96bHY 0Y2XUeJJMNpxUHfUwKRcSU0kvYxJBwqn7XL+nC1PsM2/hb68rEurwnHw6Qr8VFh9eghM 4rtg== X-Gm-Message-State: AHYfb5h+H0BTApo7lxuzUELj5TFvqRZ6RHPzOLOpHEvpALxgQQRVDS4n 3y41cf4GoT6IuA== X-Received: by 10.13.225.71 with SMTP id k68mr2537649ywe.33.1503988398387; Mon, 28 Aug 2017 23:33:18 -0700 (PDT) Received: from localhost.localdomain ([98.192.46.210]) by smtp.gmail.com with ESMTPSA id x4sm817923ywa.44.2017.08.28.23.33.16 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 28 Aug 2017 23:33:17 -0700 (PDT) From: Pranith Kumar To: alex.bennee@linaro.org, Claudio Fontana , Richard Henderson , Andrzej Zaborowski , Aurelien Jarno , Alexander Graf , qemu-arm@nongnu.org (open list:AArch64 target), qemu-devel@nongnu.org (open list:All patches CC here) Cc: qemu-devel@nongnu.org, pbonzini@redhat.com Date: Tue, 29 Aug 2017 02:33:11 -0400 Message-Id: <20170829063313.10237-3-bobby.prani@gmail.com> X-Mailer: git-send-email 2.13.0 In-Reply-To: <20170829063313.10237-1-bobby.prani@gmail.com> References: <20170829063313.10237-1-bobby.prani@gmail.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4002:c05::241 Subject: [Qemu-arm] [RFC v3 PATCH 3/5] mttcg: Add tcg target default memory ordering X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 29 Aug 2017 06:33:21 -0000 Signed-off-by: Pranith Kumar --- tcg/aarch64/tcg-target.h | 2 ++ tcg/arm/tcg-target.h | 2 ++ tcg/ia64/tcg-target.h | 2 ++ tcg/mips/tcg-target.h | 2 ++ tcg/ppc/tcg-target.h | 2 ++ tcg/s390/tcg-target.h | 2 ++ tcg/sparc/tcg-target.h | 2 ++ 7 files changed, 14 insertions(+) diff --git a/tcg/aarch64/tcg-target.h b/tcg/aarch64/tcg-target.h index 55a46ac825..b41a248bee 100644 --- a/tcg/aarch64/tcg-target.h +++ b/tcg/aarch64/tcg-target.h @@ -117,4 +117,6 @@ static inline void flush_icache_range(uintptr_t start, uintptr_t stop) __builtin___clear_cache((char *)start, (char *)stop); } +#define TCG_TARGET_DEFAULT_MO (0) + #endif /* AARCH64_TCG_TARGET_H */ diff --git a/tcg/arm/tcg-target.h b/tcg/arm/tcg-target.h index 5ef1086710..a38be15a39 100644 --- a/tcg/arm/tcg-target.h +++ b/tcg/arm/tcg-target.h @@ -134,4 +134,6 @@ static inline void flush_icache_range(uintptr_t start, uintptr_t stop) __builtin___clear_cache((char *) start, (char *) stop); } +#define TCG_TARGET_DEFAULT_MO (0) + #endif diff --git a/tcg/ia64/tcg-target.h b/tcg/ia64/tcg-target.h index 901bb7575d..8f475fe742 100644 --- a/tcg/ia64/tcg-target.h +++ b/tcg/ia64/tcg-target.h @@ -195,4 +195,6 @@ static inline void flush_icache_range(uintptr_t start, uintptr_t stop) asm volatile (";;sync.i;;srlz.i;;"); } +#define TCG_TARGET_DEFAULT_MO (0) + #endif diff --git a/tcg/mips/tcg-target.h b/tcg/mips/tcg-target.h index d75cb63ed3..e9558d15bc 100644 --- a/tcg/mips/tcg-target.h +++ b/tcg/mips/tcg-target.h @@ -206,4 +206,6 @@ static inline void flush_icache_range(uintptr_t start, uintptr_t stop) cacheflush ((void *)start, stop-start, ICACHE); } +#define TCG_TARGET_DEFAULT_MO (0) + #endif diff --git a/tcg/ppc/tcg-target.h b/tcg/ppc/tcg-target.h index 5f4a40a5b4..5a092b038a 100644 --- a/tcg/ppc/tcg-target.h +++ b/tcg/ppc/tcg-target.h @@ -125,4 +125,6 @@ extern bool have_isa_3_00; void flush_icache_range(uintptr_t start, uintptr_t stop); +#define TCG_TARGET_DEFAULT_MO (0) + #endif diff --git a/tcg/s390/tcg-target.h b/tcg/s390/tcg-target.h index 957f0c0afe..dc0e59193c 100644 --- a/tcg/s390/tcg-target.h +++ b/tcg/s390/tcg-target.h @@ -133,6 +133,8 @@ extern uint64_t s390_facilities; #define TCG_TARGET_EXTEND_ARGS 1 +#define TCG_TARGET_DEFAULT_MO (TCG_MO_ALL & ~TCG_MO_ST_LD) + enum { TCG_AREG0 = TCG_REG_R10, }; diff --git a/tcg/sparc/tcg-target.h b/tcg/sparc/tcg-target.h index 854a0afd70..4515c9ab48 100644 --- a/tcg/sparc/tcg-target.h +++ b/tcg/sparc/tcg-target.h @@ -162,6 +162,8 @@ extern bool use_vis3_instructions; #define TCG_AREG0 TCG_REG_I0 +#define TCG_TARGET_DEFAULT_MO (0) + static inline void flush_icache_range(uintptr_t start, uintptr_t stop) { uintptr_t p; -- 2.13.0 From MAILER-DAEMON Tue Aug 29 02:33:31 2017 Received: from list by lists.gnu.org with archive (Exim 4.71) id 1dma5b-0000WX-4J for mharc-qemu-arm@gnu.org; Tue, 29 Aug 2017 02:33:31 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:38903) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dma5W-0000T4-8r for qemu-arm@nongnu.org; Tue, 29 Aug 2017 02:33:29 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dma5U-000444-Nh for qemu-arm@nongnu.org; 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X-Received-From: 2607:f8b0:4002:c05::244 Subject: [Qemu-arm] [RFC v3 PATCH 5/5] tcg/softmmu: Increase size of TLB caches X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 29 Aug 2017 06:33:29 -0000 This patch increases the number of entries cached in the TLB. I went over a few architectures to see if increasing it is problematic. Only armv6 seems to have a limitation that only 8 bits can be used for indexing these entries. For other architectures, the number of TLB entries is increased to a 4K-sized cache. The patch also doubles the number of victim TLB entries. Some statistics collected from a build benchmark for various cache sizes is listed below: | TLB bits\vTLB entires | 8 | 16 | 32 | | 8 | 952.94(+0.0%) | 929.99(+2.4%) | 919.02(+3.6%) | | 10 | 898.92(+5.6%) | 886.13(+7.0%) | 887.03(+6.9%) | | 12 | 878.56(+7.8%) | 873.53(+8.3%)* | 875.34(+8.1%) | The best combination for this workload came out to be 12 bits for the TLB and a 16 entry vTLB cache. Signed-off-by: Pranith Kumar --- include/exec/cpu-defs.h | 13 ++++--------- tcg/aarch64/tcg-target.h | 1 + tcg/arm/tcg-target.h | 1 + tcg/i386/tcg-target.h | 6 ++++++ tcg/ia64/tcg-target.h | 1 + tcg/mips/tcg-target.h | 6 ++++++ tcg/ppc/tcg-target.h | 1 + tcg/s390/tcg-target.h | 1 + tcg/sparc/tcg-target.h | 1 + tcg/tci/tcg-target.h | 2 ++ 10 files changed, 24 insertions(+), 9 deletions(-) diff --git a/include/exec/cpu-defs.h b/include/exec/cpu-defs.h index bc8e7f848d..33b0ac6fe0 100644 --- a/include/exec/cpu-defs.h +++ b/include/exec/cpu-defs.h @@ -57,8 +57,8 @@ typedef uint64_t target_ulong; #endif #if !defined(CONFIG_USER_ONLY) && defined(CONFIG_TCG) -/* use a fully associative victim tlb of 8 entries */ -#define CPU_VTLB_SIZE 8 +/* use a fully associative victim tlb of 16 entries */ +#define CPU_VTLB_SIZE 16 #if HOST_LONG_BITS == 32 && TARGET_LONG_BITS == 32 #define CPU_TLB_ENTRY_BITS 4 @@ -87,14 +87,9 @@ typedef uint64_t target_ulong; * could be something like 0xC000 (the offset of the last TLB table) plus * 0x18 (the offset of the addend field in each TLB entry) plus the offset * of tlb_table inside env (which is non-trivial but not huge). + * TODO: rewrite this comment */ -#define CPU_TLB_BITS \ - MIN(8, \ - TCG_TARGET_TLB_DISPLACEMENT_BITS - CPU_TLB_ENTRY_BITS - \ - (NB_MMU_MODES <= 1 ? 0 : \ - NB_MMU_MODES <= 2 ? 1 : \ - NB_MMU_MODES <= 4 ? 2 : \ - NB_MMU_MODES <= 8 ? 3 : 4)) +#define CPU_TLB_BITS MIN(12, TCG_TARGET_TLB_MAX_INDEX_BITS) #define CPU_TLB_SIZE (1 << CPU_TLB_BITS) diff --git a/tcg/aarch64/tcg-target.h b/tcg/aarch64/tcg-target.h index b41a248bee..9f4558cd83 100644 --- a/tcg/aarch64/tcg-target.h +++ b/tcg/aarch64/tcg-target.h @@ -15,6 +15,7 @@ #define TCG_TARGET_INSN_UNIT_SIZE 4 #define TCG_TARGET_TLB_DISPLACEMENT_BITS 24 +#define TCG_TARGET_TLB_MAX_INDEX_BITS 32 #undef TCG_TARGET_STACK_GROWSUP typedef enum { diff --git a/tcg/arm/tcg-target.h b/tcg/arm/tcg-target.h index a38be15a39..ebe27991f3 100644 --- a/tcg/arm/tcg-target.h +++ b/tcg/arm/tcg-target.h @@ -60,6 +60,7 @@ extern int arm_arch; #undef TCG_TARGET_STACK_GROWSUP #define TCG_TARGET_INSN_UNIT_SIZE 4 #define TCG_TARGET_TLB_DISPLACEMENT_BITS 16 +#define TCG_TARGET_TLB_MAX_INDEX_BITS 8 typedef enum { TCG_REG_R0 = 0, diff --git a/tcg/i386/tcg-target.h b/tcg/i386/tcg-target.h index 73a15f7e80..456d57115c 100644 --- a/tcg/i386/tcg-target.h +++ b/tcg/i386/tcg-target.h @@ -162,6 +162,12 @@ extern bool have_popcnt; # define TCG_AREG0 TCG_REG_EBP #endif +#if HOST_LONG_BITS == 32 && TARGET_LONG_BITS == 32 +#define TCG_TARGET_TLB_MAX_INDEX_BITS 28 +#else +#define TCG_TARGET_TLB_MAX_INDEX_BITS 27 +#endif + static inline void flush_icache_range(uintptr_t start, uintptr_t stop) { } diff --git a/tcg/ia64/tcg-target.h b/tcg/ia64/tcg-target.h index 8f475fe742..35878e20c7 100644 --- a/tcg/ia64/tcg-target.h +++ b/tcg/ia64/tcg-target.h @@ -28,6 +28,7 @@ #define TCG_TARGET_INSN_UNIT_SIZE 16 #define TCG_TARGET_TLB_DISPLACEMENT_BITS 21 +#define TCG_TARGET_TLB_MAX_INDEX_BITS 32 typedef struct { uint64_t lo __attribute__((aligned(16))); diff --git a/tcg/mips/tcg-target.h b/tcg/mips/tcg-target.h index e9558d15bc..0c7c5cf64c 100644 --- a/tcg/mips/tcg-target.h +++ b/tcg/mips/tcg-target.h @@ -39,6 +39,12 @@ #define TCG_TARGET_TLB_DISPLACEMENT_BITS 16 #define TCG_TARGET_NB_REGS 32 +#if HOST_LONG_BITS == 32 && TARGET_LONG_BITS == 32 +#define TCG_TARGET_TLB_MAX_INDEX_BITS 12 +#else +#define TCG_TARGET_TLB_MAX_INDEX_BITS 11 +#endif + typedef enum { TCG_REG_ZERO = 0, TCG_REG_AT, diff --git a/tcg/ppc/tcg-target.h b/tcg/ppc/tcg-target.h index 5a092b038a..82e10c9471 100644 --- a/tcg/ppc/tcg-target.h +++ b/tcg/ppc/tcg-target.h @@ -34,6 +34,7 @@ #define TCG_TARGET_NB_REGS 32 #define TCG_TARGET_INSN_UNIT_SIZE 4 #define TCG_TARGET_TLB_DISPLACEMENT_BITS 16 +#define TCG_TARGET_TLB_MAX_INDEX_BITS 32 typedef enum { TCG_REG_R0, TCG_REG_R1, TCG_REG_R2, TCG_REG_R3, diff --git a/tcg/s390/tcg-target.h b/tcg/s390/tcg-target.h index dc0e59193c..57f0e22532 100644 --- a/tcg/s390/tcg-target.h +++ b/tcg/s390/tcg-target.h @@ -27,6 +27,7 @@ #define TCG_TARGET_INSN_UNIT_SIZE 2 #define TCG_TARGET_TLB_DISPLACEMENT_BITS 19 +#define TCG_TARGET_TLB_MAX_INDEX_BITS 32 typedef enum TCGReg { TCG_REG_R0 = 0, diff --git a/tcg/sparc/tcg-target.h b/tcg/sparc/tcg-target.h index 4515c9ab48..378d218923 100644 --- a/tcg/sparc/tcg-target.h +++ b/tcg/sparc/tcg-target.h @@ -29,6 +29,7 @@ #define TCG_TARGET_INSN_UNIT_SIZE 4 #define TCG_TARGET_TLB_DISPLACEMENT_BITS 32 +#define TCG_TARGET_TLB_MAX_INDEX_BITS 12 #define TCG_TARGET_NB_REGS 32 typedef enum { diff --git a/tcg/tci/tcg-target.h b/tcg/tci/tcg-target.h index 06963288dc..456a4fc4e1 100644 --- a/tcg/tci/tcg-target.h +++ b/tcg/tci/tcg-target.h @@ -40,9 +40,11 @@ #ifndef TCG_TARGET_H #define TCG_TARGET_H + #define TCG_TARGET_INTERPRETER 1 #define TCG_TARGET_INSN_UNIT_SIZE 1 #define TCG_TARGET_TLB_DISPLACEMENT_BITS 32 +#define TCG_TARGET_TLB_MAX_INDEX_BITS 32 #if UINTPTR_MAX == UINT32_MAX # define TCG_TARGET_REG_BITS 32 -- 2.13.0 From MAILER-DAEMON Tue Aug 29 06:21:18 2017 Received: from list by lists.gnu.org with archive (Exim 4.71) id 1dmde2-0002y0-6g for mharc-qemu-arm@gnu.org; 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dmarc=none (p=none dis=none) header.from=redhat.com Authentication-Results: ext-mx04.extmail.prod.ext.phx2.redhat.com; spf=fail smtp.mailfrom=imammedo@redhat.com Received: from nial.brq.redhat.com (ovpn-204-70.brq.redhat.com [10.40.204.70]) by smtp.corp.redhat.com (Postfix) with ESMTP id A1F945D9C8; Tue, 29 Aug 2017 10:20:55 +0000 (UTC) Date: Tue, 29 Aug 2017 12:20:53 +0200 From: Igor Mammedov To: Dongjiu Geng Cc: , , , , , , , , , , , , , , , , , , , , , , , , , , , , zhengqiang10@huawei.com, wuquanming@huawei.com, huangshaoyu@huawei.com, linuxarm@huawei.com Message-ID: <20170829122053.36cf550c@nial.brq.redhat.com> In-Reply-To: <1503066227-18251-3-git-send-email-gengdongjiu@huawei.com> References: <1503066227-18251-1-git-send-email-gengdongjiu@huawei.com> <1503066227-18251-3-git-send-email-gengdongjiu@huawei.com> MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit X-Scanned-By: MIMEDefang 2.79 on 10.5.11.14 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.28]); Tue, 29 Aug 2017 10:21:09 +0000 (UTC) X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.132.183.28 Subject: Re: [Qemu-arm] [Qemu-devel] [PATCH v11 2/6] ACPI: Add APEI GHES Table Generation support X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 29 Aug 2017 10:21:17 -0000 On Fri, 18 Aug 2017 22:23:43 +0800 Dongjiu Geng wrote: > This implements APEI GHES Table by passing the error CPER info > to the guest via a fw_cfg_blob. After a CPER info is recorded, an > SEA(Synchronous External Abort)/SEI(SError Interrupt) exception > will be injected into the guest OS. it's a bit complex patch/functionality so I've just mosty skimmed and commented only on structure of the patch and changes I'd like to see so it would be more structured and review-able. I'd suggest to add doc patch first which will describe how it's supposed to work between QEMU/firmware/guest OS with expected flows. > Below is the table layout, the max number of error soure is 11, > which is classified by notification type. > > etc/acpi/tables etc/hardware_errors > ==================== ========================================== > + +--------------------------+ +------------------+ > | | HEST | | address | +--------------+ > | +--------------------------+ | registers | | Error Status | > | | GHES0 | | +----------------+ | Data Block 0 | > | +--------------------------+ +--------->| |status_address0 |------------->| +------------+ > | | ................. | | | +----------------+ | | CPER | > | | error_status_address-----+-+ +------->| |status_address1 |----------+ | | CPER | > | | ................. | | | +----------------+ | | | .... | > | | read_ack_register--------+-+ | | ............. | | | | CPER | > | | read_ack_preserve | | | +------------------+ | | +-+------------+ > | | read_ack_write | | | +----->| |status_address10|--------+ | | Error Status | > + +--------------------------+ | | | | +----------------+ | | | Data Block 1 | > | | GHES1 | +-+-+----->| | ack_value0 | | +-->| +------------+ > + +--------------------------+ | | | +----------------+ | | | CPER | > | | ................. | | | +--->| | ack_value1 | | | | CPER | > | | error_status_address-----+---+ | | | +----------------+ | | | .... | > | | ................. | | | | | ............. | | | | CPER | > | | read_ack_register--------+-----+-+ | +----------------+ | +-+------------+ > | | read_ack_preserve | | +->| | ack_value10 | | | |.......... | > | | read_ack_write | | | | +----------------+ | | +------------+ > + +--------------------------| | | | | Error Status | > | | ............... | | | | | Data Block 10| > + +--------------------------+ | | +---->| +------------+ > | | GHES10 | | | | | CPER | > + +--------------------------+ | | | | CPER | > | | ................. | | | | | .... | > | | error_status_address-----+-----+ | | | CPER | > | | ................. | | +-+------------+ > | | read_ack_register--------+---------+ > | | read_ack_preserve | > | | read_ack_write | > + +--------------------------+ these diagram shows relations between tables which not necessarily bad but as layout it's useless. * Probably there is not much sense to have HEST table here, it's described well enough in spec. You might just put reference here. * these diagrams should go into doc/spec patch * when you describe layout you need to show what and at what offsets in which order in which blob/file is located. See ACPI spec for example and/or docs/specs/acpi_nvdimm.txt docs/specs/acpi_mem_hotplug.txt for inspiration. > For GHESv2 error source, the OSPM must acknowledges the error via Read Ack register. > so user space must check the ack value to avoid read-write race condition. > > Signed-off-by: Dongjiu Geng > --- > hw/acpi/aml-build.c | 2 + > hw/acpi/hest_ghes.c | 345 ++++++++++++++++++++++++++++++++++++++++++++ > hw/arm/virt-acpi-build.c | 6 + > include/hw/acpi/aml-build.h | 1 + > include/hw/acpi/hest_ghes.h | 47 ++++++ > 5 files changed, 401 insertions(+) > create mode 100644 hw/acpi/hest_ghes.c > create mode 100644 include/hw/acpi/hest_ghes.h > > diff --git a/hw/acpi/aml-build.c b/hw/acpi/aml-build.c > index 36a6cc4..6849e5f 100644 > --- a/hw/acpi/aml-build.c > +++ b/hw/acpi/aml-build.c > @@ -1561,6 +1561,7 @@ void acpi_build_tables_init(AcpiBuildTables *tables) > tables->table_data = g_array_new(false, true /* clear */, 1); > tables->tcpalog = g_array_new(false, true /* clear */, 1); > tables->vmgenid = g_array_new(false, true /* clear */, 1); > + tables->hardware_errors = g_array_new(false, true /* clear */, 1); > tables->linker = bios_linker_loader_init(); > } > > @@ -1571,6 +1572,7 @@ void acpi_build_tables_cleanup(AcpiBuildTables *tables, bool mfre) > g_array_free(tables->table_data, true); > g_array_free(tables->tcpalog, mfre); > g_array_free(tables->vmgenid, mfre); > + g_array_free(tables->hardware_errors, mfre); > } > > /* Build rsdt table */ > diff --git a/hw/acpi/hest_ghes.c b/hw/acpi/hest_ghes.c > new file mode 100644 > index 0000000..ff6b5ef > --- /dev/null > +++ b/hw/acpi/hest_ghes.c > @@ -0,0 +1,345 @@ > +/* > + * APEI GHES table Generation > + * > + * Copyright (C) 2017 huawei. > + * > + * Author: Dongjiu Geng > + * > + * This work is licensed under the terms of the GNU GPL, version 2 or later. > + * See the COPYING file in the top-level directory. > + * > + */ > + > +#include "qemu/osdep.h" > +#include "qmp-commands.h" > +#include "hw/acpi/acpi.h" > +#include "hw/acpi/aml-build.h" > +#include "hw/acpi/hest_ghes.h" > +#include "hw/nvram/fw_cfg.h" > +#include "sysemu/sysemu.h" > +#include "qemu/error-report.h" > + > +/* The structure that stands for the layout > + * GHES_ERRORS_FW_CFG_FILE fw_cfg blob > + * > + * etc/hardware_errors > + * ========================================== > + * +------------------+ > + * | address | +--------------+ > + * | registers | | Error Status | > + * | +----------------+ | Data Block 0 | > + * | |status_address0 |------------->| +------------+ > + * | +----------------+ | | CPER | > + * | |status_address1 |----------+ | | CPER | > + * | +----------------+ | | | .... | > + * | |............. | | | | CPER | > + * | +----------------+ | | +------------+ > + * | |status_address10|-----+ | | Error Status | > + * | +----------------+ | | | Data Block 1 | > + * | |ack_value0 | | +-->| +------------+ > + * | +----------------+ | | | CPER | > + * | |ack_value1 | | | | CPER | > + * | +----------------+ | | | .... | > + * | | ............. | | | | CPER | > + * | +----------------+ | +-+------------+ > + * | |ack_value10 | | | |.......... | > + * | +----------------+ | | +------------+ > + * | | Error Status | > + * | | Data Block10 | > + * +------->+------------+ > + * | | CPER | > + * | | CPER | > + * | | .... | > + * | | CPER | > + * +-+------------+ > + */ > +struct hardware_errors_buffer { > + /* Generic Error Status Block register */ > + uint64_t gesb_address[GHES_ACPI_HEST_NOTIFY_RESERVED]; > + uint64_t ack_value[GHES_ACPI_HEST_NOTIFY_RESERVED]; > + char gesb[GHES_MAX_RAW_DATA_LENGTH][GHES_ACPI_HEST_NOTIFY_RESERVED]; > +}; > + > +static int ghes_record_cper(uint64_t error_block_address, > + uint64_t error_physical_addr) > +{ > + AcpiGenericErrorStatus block; > + AcpiGenericErrorData *gdata; > + UefiCperSecMemErr *mem_err; > + uint64_t current_block_length; > + unsigned char *buffer; > + /* memory section */ > + char mem_section_id_le[] = {0x14, 0x11, 0xBC, 0xA5, 0x64, 0x6F, 0xDE, > + 0x4E, 0xB8, 0x63, 0x3E, 0x83, 0xED, 0x7C, > + 0x83, 0xB1}; > + > + cpu_physical_memory_read(error_block_address, &block, > + sizeof(AcpiGenericErrorStatus)); > + > + /* Get the current generic error status block length */ > + current_block_length = sizeof(AcpiGenericErrorStatus) + > + le32_to_cpu(block.data_length); > + > + /* If the Generic Error Status Block is NULL, update > + * the block header > + */ > + if (!block.block_status) { > + block.block_status = ACPI_GEBS_UNCORRECTABLE; > + block.error_severity = ACPI_CPER_SEV_RECOVERABLE; > + } > + > + block.data_length += cpu_to_le32(sizeof(AcpiGenericErrorData)); > + block.data_length += cpu_to_le32(sizeof(UefiCperSecMemErr)); > + > + /* check whether it runs out of the preallocated memory */ > + if ((le32_to_cpu(block.data_length) + sizeof(AcpiGenericErrorStatus)) > > + GHES_MAX_RAW_DATA_LENGTH) { > + error_report("Record CPER out of boundary!!!"); > + return GHES_CPER_FAIL; > + } > + > + /* Write back the Generic Error Status Block to guest memory */ > + cpu_physical_memory_write(error_block_address, &block, > + sizeof(AcpiGenericErrorStatus)); > + > + /* Fill in Generic Error Data Entry */ > + buffer = g_malloc0(sizeof(AcpiGenericErrorData) + > + sizeof(UefiCperSecMemErr)); > + > + > + memset(buffer, 0, sizeof(AcpiGenericErrorData) + sizeof(UefiCperSecMemErr)); looks redundant, g_malloc0 does it for you > + gdata = (AcpiGenericErrorData *)buffer; > + > + /* Memory section */ > + memcpy(&(gdata->section_type_le), &mem_section_id_le, > + sizeof(mem_section_id_le)); > + > + /* error severity is recoverable */ > + gdata->error_severity = ACPI_CPER_SEV_RECOVERABLE; > + gdata->revision = 0x300; /* the revision number is 0x300 */ > + gdata->error_data_length = cpu_to_le32(sizeof(UefiCperSecMemErr)); > + > + mem_err = (UefiCperSecMemErr *) (gdata + 1); > + > + /* User space only handle the memory section CPER */ > + > + /* Hard code to Multi-bit ECC error */ > + mem_err->validation_bits |= cpu_to_le32(UEFI_CPER_MEM_VALID_ERROR_TYPE); > + mem_err->error_type = cpu_to_le32(UEFI_CPER_MEM_ERROR_TYPE_MULTI_ECC); > + > + /* Record the physical address at which the memory error occurred */ > + mem_err->validation_bits |= cpu_to_le32(UEFI_CPER_MEM_VALID_PA); > + mem_err->physical_addr = cpu_to_le32(error_physical_addr); I'd prefer for you to use build_append_int_noprefix() API to compose whole error status block and try to get rid of most structures you introduce in patch 1/6, as they will be left unused after that. > + > + /* Write back the Generic Error Data Entry to guest memory */ > + cpu_physical_memory_write(error_block_address + current_block_length, > + buffer, sizeof(AcpiGenericErrorData) + sizeof(UefiCperSecMemErr)); > + > + g_free(buffer); > + return GHES_CPER_OK; > +} > + > +static void > +build_address(GArray *table_data, BIOSLinker *linker, > + uint32_t dst_patched_offset, uint32_t src_offset, > + uint8_t address_space_id , uint8_t register_bit_width, > + uint8_t register_bit_offset, uint8_t access_size) > +{ > + uint32_t address_size = sizeof(struct AcpiGenericAddress) - > + offsetof(struct AcpiGenericAddress, address); > + > + /* Address space */ > + build_append_int_noprefix(table_data, address_space_id, 1); > + /* register bit width */ > + build_append_int_noprefix(table_data, register_bit_width, 1); > + /* register bit offset */ > + build_append_int_noprefix(table_data, register_bit_offset, 1); > + /* access size */ > + build_append_int_noprefix(table_data, access_size, 1); > + acpi_data_push(table_data, address_size); > + > + /* Patch address of ERRORS fw_cfg blob into the TABLE fw_cfg blob so OSPM > + * can retrieve and read it. the address size is 64 bits. > + */ > + bios_linker_loader_add_pointer(linker, > + ACPI_BUILD_TABLE_FILE, dst_patched_offset, sizeof(uint64_t), > + GHES_ERRORS_FW_CFG_FILE, src_offset); > +} It's mostly generic GAS structure with linker addition. I'd suggest to reuse something like https://github.com/imammedo/qemu/commit/3d2fd6d13a3ea298d2ee814835495ce6241d085c to build GAS and use bios_linker_loader_add_pointer() directly in ghes_build_acpi(). > +void ghes_build_acpi(GArray *table_data, GArray *hardware_error, > + BIOSLinker *linker) > +{ > + uint32_t ghes_start = table_data->len; > + uint32_t address_size, error_status_address_offset; > + uint32_t read_ack_register_offset, i; > + > + address_size = sizeof(struct AcpiGenericAddress) - > + offsetof(struct AcpiGenericAddress, address); it's confusing name for var, AcpiGenericAddress::address is fixed unsigned 64 bit integer per spec also, I'm not sure why it's needed at all. > + > + error_status_address_offset = ghes_start + > + sizeof(AcpiHardwareErrorSourceTable) + > + offsetof(AcpiGenericHardwareErrorSourceV2, error_status_address) + > + offsetof(struct AcpiGenericAddress, address); > + > + read_ack_register_offset = ghes_start + > + sizeof(AcpiHardwareErrorSourceTable) + > + offsetof(AcpiGenericHardwareErrorSourceV2, read_ack_register) + > + offsetof(struct AcpiGenericAddress, address); it's really hard to get why you use offsetof() so much in this function, to me above code totally unreadable. > + acpi_data_push(hardware_error, > + offsetof(struct hardware_errors_buffer, ack_value)); it looks like you are trying to build several tables within one function, so it's hard to get what's going on. I'd suggest to build separate table independently where it's possible. i.e. build independent tables first and only then build dependent tables passing to it pointers to previously build table if necessary. > + for (i = 0; i < GHES_ACPI_HEST_NOTIFY_RESERVED; i++) > + /* Initialize read ack register */ > + build_append_int_noprefix((void *)hardware_error, 1, 8); > + > + /* Reserved the total size for ERRORS fw_cfg blob > + */ > + acpi_data_push(hardware_error, sizeof(struct hardware_errors_buffer)); > + > + /* Allocate guest memory for the Data fw_cfg blob */ > + bios_linker_loader_alloc(linker, GHES_ERRORS_FW_CFG_FILE, hardware_error, > + 1, false); > + /* Reserve table header size */ > + acpi_data_push(table_data, sizeof(AcpiTableHeader)); > + > + build_append_int_noprefix(table_data, GHES_ACPI_HEST_NOTIFY_RESERVED, 4); GHES_ACPI_HEST_NOTIFY_RESERVED - name doesn't actually tell what it is I'd suggest to use spec field name wit table prefix, ex: ACPI_HEST_ERROR_SOURCE_COUNT also, beside build_append_int_noprefix() you need to at least add comment that exactly matches field from spec. the same applies to other fields you are adding in this patch > + > + for (i = 0; i < GHES_ACPI_HEST_NOTIFY_RESERVED; i++) { > + build_append_int_noprefix(table_data, > + ACPI_HEST_SOURCE_GENERIC_ERROR_V2, 2); /* type */ > + /* source id */ > + build_append_int_noprefix(table_data, cpu_to_le16(i), 2); > + /* related source id */ > + build_append_int_noprefix(table_data, 0xffff, 2); > + build_append_int_noprefix(table_data, 0, 1); /* flags */ > + > + /* Currently only enable SEA notification type to avoid the kernel > + * warning, reserve the space for other notification error source > + */ > + if (i == ACPI_HEST_NOTIFY_SEA) { > + build_append_int_noprefix(table_data, 1, 1); /* enabled */ > + } else { > + build_append_int_noprefix(table_data, 0, 1); /* enabled */ > + } > + > + /* The number of error status block per generic hardware error source */ > + build_append_int_noprefix(table_data, 1, 4); > + /* Max sections per record */ > + build_append_int_noprefix(table_data, 1, 4); > + /* Max raw data length */ > + build_append_int_noprefix(table_data, GHES_MAX_RAW_DATA_LENGTH, 4); > + > + /* Build error status address*/ > + build_address(table_data, linker, error_status_address_offset + i * > + sizeof(AcpiGenericHardwareErrorSourceV2), i * address_size, > + AML_SYSTEM_MEMORY, 0x40, 0, 4 /* QWord access */); just do something like this instead of build_address(): build_append_gas() bios_linker_loader_add_pointer() also register width 0x40 looks suspicious, where does it come from? While at it do you have a real hardware which has HEST table that you re trying to model after? I'd like to see HEST and other related tables from it. > + > + /* Hardware error notification structure */ > + build_append_int_noprefix(table_data, i, 1); /* type */ > + /* length */ > + build_append_int_noprefix(table_data, sizeof(AcpiHestNotify), 1); > + build_append_int_noprefix(table_data, 0, 26); > + > + /* Error Status Block Length */ > + build_append_int_noprefix(table_data, > + cpu_to_le32(GHES_MAX_RAW_DATA_LENGTH), 4); > + > + /* Build read ack register */ > + build_address(table_data, linker, read_ack_register_offset + i * > + sizeof(AcpiGenericHardwareErrorSourceV2), > + offsetof(struct hardware_errors_buffer, ack_value) + > + i * address_size, AML_SYSTEM_MEMORY, 0x40, 0, > + 4 /* QWord access */); > + > + /* Read ack preserve */ > + build_append_int_noprefix(table_data, cpu_to_le64(0xfffffffe), 8); > + > + /* Read ack write */ > + build_append_int_noprefix(table_data, cpu_to_le64(0x1), 8); > + } > + > + for (i = 0; i < GHES_ACPI_HEST_NOTIFY_RESERVED; i++) > + /* Patch address of generic error status block into > + * the address register so OSPM can retrieve and read it. > + */ > + bios_linker_loader_add_pointer(linker, > + GHES_ERRORS_FW_CFG_FILE, address_size * i, address_size, > + GHES_ERRORS_FW_CFG_FILE, > + offsetof(struct hardware_errors_buffer, gesb) + > + i * GHES_MAX_RAW_DATA_LENGTH); > + > + /* Patch address of ERRORS fw_cfg blob into the ADDR fw_cfg blob > + * so QEMU can write the ERRORS there. The address is expected to be > + * < 4GB, but write 64 bits anyway. > + */ > + bios_linker_loader_write_pointer(linker, GHES_DATA_ADDR_FW_CFG_FILE, > + 0, address_size, GHES_ERRORS_FW_CFG_FILE, > + offsetof(struct hardware_errors_buffer, gesb)); > + > + build_header(linker, table_data, > + (void *)(table_data->data + ghes_start), "HEST", > + table_data->len - ghes_start, 1, NULL, "GHES"); > +} > + > +static GhesState ges; > +void ghes_add_fw_cfg(FWCfgState *s, GArray *hardware_error) > +{ > + > + size_t request_block_size = sizeof(uint64_t) + GHES_MAX_RAW_DATA_LENGTH; > + size_t size = GHES_ACPI_HEST_NOTIFY_RESERVED * request_block_size; > + > + /* Create a read-only fw_cfg file for GHES */ > + fw_cfg_add_file(s, GHES_ERRORS_FW_CFG_FILE, hardware_error->data, > + size); > + /* Create a read-write fw_cfg file for Address */ > + fw_cfg_add_file_callback(s, GHES_DATA_ADDR_FW_CFG_FILE, NULL, NULL, > + &ges.ghes_addr_le, sizeof(ges.ghes_addr_le), false); > +} > + > +bool ghes_update_guest(uint32_t notify, uint64_t physical_address) > +{ > + uint64_t error_block_addr; > + uint64_t ack_value_addr, ack_value = 0; > + int loop = 0, ack_value_size; > + bool ret = GHES_CPER_FAIL; > + > + ack_value_size = (offsetof(struct hardware_errors_buffer, gesb) - > + offsetof(struct hardware_errors_buffer, ack_value)) / > + GHES_ACPI_HEST_NOTIFY_RESERVED; > + > + if (physical_address && notify < GHES_ACPI_HEST_NOTIFY_RESERVED) { > + error_block_addr = ges.ghes_addr_le + notify * GHES_MAX_RAW_DATA_LENGTH; > + error_block_addr = le32_to_cpu(error_block_addr); > + > + ack_value_addr = ges.ghes_addr_le - > + (GHES_ACPI_HEST_NOTIFY_RESERVED - notify) * ack_value_size; > +retry: > + cpu_physical_memory_read(ack_value_addr, &ack_value, ack_value_size); > + if (!ack_value) { > + if (loop < 3) { > + usleep(100 * 1000); > + loop++; > + goto retry; > + } else { > + error_report("Last time OSPM does not acknowledge the error," > + " record CPER failed this time, set the ack value to" > + " avoid blocking next time CPER record! exit"); > + ack_value = 1; > + cpu_physical_memory_write(ack_value_addr, > + &ack_value, ack_value_size); > + return ret; > + } > + } else { > + /* A zero value in ghes_addr means that BIOS has not yet written > + * the address > + */ > + if (error_block_addr) { > + ack_value = 0; > + cpu_physical_memory_write(ack_value_addr, > + &ack_value, ack_value_size); > + ret = ghes_record_cper(error_block_addr, physical_address); > + } > + } > + } > + return ret; > +} > diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c > index 3d78ff6..def1ec1 100644 > --- a/hw/arm/virt-acpi-build.c > +++ b/hw/arm/virt-acpi-build.c > @@ -45,6 +45,7 @@ > #include "hw/arm/virt.h" > #include "sysemu/numa.h" > #include "kvm_arm.h" > +#include "hw/acpi/hest_ghes.h" > > #define ARM_SPI_BASE 32 > #define ACPI_POWER_BUTTON_DEVICE "PWRB" > @@ -771,6 +772,9 @@ void virt_acpi_build(VirtMachineState *vms, AcpiBuildTables *tables) > acpi_add_table(table_offsets, tables_blob); > build_spcr(tables_blob, tables->linker, vms); > > + acpi_add_table(table_offsets, tables_blob); > + ghes_build_acpi(tables_blob, tables->hardware_errors, tables->linker); > + > if (nb_numa_nodes > 0) { > acpi_add_table(table_offsets, tables_blob); > build_srat(tables_blob, tables->linker, vms); > @@ -887,6 +891,8 @@ void virt_acpi_setup(VirtMachineState *vms) > fw_cfg_add_file(vms->fw_cfg, ACPI_BUILD_TPMLOG_FILE, tables.tcpalog->data, > acpi_data_len(tables.tcpalog)); > > + ghes_add_fw_cfg(vms->fw_cfg, tables.hardware_errors); > + > build_state->rsdp_mr = acpi_add_rom_blob(build_state, tables.rsdp, > ACPI_BUILD_RSDP_FILE, 0); > > diff --git a/include/hw/acpi/aml-build.h b/include/hw/acpi/aml-build.h > index 88d0738..7f7b55c 100644 > --- a/include/hw/acpi/aml-build.h > +++ b/include/hw/acpi/aml-build.h > @@ -211,6 +211,7 @@ struct AcpiBuildTables { > GArray *rsdp; > GArray *tcpalog; > GArray *vmgenid; > + GArray *hardware_errors; > BIOSLinker *linker; > } AcpiBuildTables; > > diff --git a/include/hw/acpi/hest_ghes.h b/include/hw/acpi/hest_ghes.h > new file mode 100644 > index 0000000..0772756 > --- /dev/null > +++ b/include/hw/acpi/hest_ghes.h > @@ -0,0 +1,47 @@ > +/* > + * This program is free software; you can redistribute it and/or modify > + * it under the terms of the GNU General Public License as published by > + * the Free Software Foundation; either version 2 of the License, or > + * (at your option) any later version. > + > + * This program is distributed in the hope that it will be useful, > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > + * GNU General Public License for more details. > + * > + * Authors: > + * Dongjiu Geng > + * > + * You should have received a copy of the GNU General Public License along > + * with this program; if not, see . > + */ > + > +#ifndef ACPI_GHES_H > +#define ACPI_GHES_H > + > +#include "hw/acpi/bios-linker-loader.h" > + > +#define GHES_ERRORS_FW_CFG_FILE "etc/hardware_errors" > +#define GHES_DATA_ADDR_FW_CFG_FILE "etc/hardware_errors_addr" > + > +#define GHES_GAS_ADDRESS_OFFSET 4 > +#define GHES_ERROR_STATUS_ADDRESS_OFFSET 20 > +#define GHES_NOTIFICATION_STRUCTURE 32 > + > +#define GHES_CPER_OK 1 > +#define GHES_CPER_FAIL 0 > + > +#define GHES_ACPI_HEST_NOTIFY_RESERVED 11 > +/* The max size in Bytes for one error block */ > +#define GHES_MAX_RAW_DATA_LENGTH 0x1000 > + > + > +typedef struct GhesState { > + uint64_t ghes_addr_le; > +} GhesState; > + > +void ghes_build_acpi(GArray *table_data, GArray *hardware_error, > + BIOSLinker *linker); > +void ghes_add_fw_cfg(FWCfgState *s, GArray *hardware_errors); > +bool ghes_update_guest(uint32_t notify, uint64_t error_physical_addr); > +#endif From MAILER-DAEMON Tue Aug 29 07:20:34 2017 Received: from list by lists.gnu.org with archive (Exim 4.71) id 1dmeZO-00052W-Cy for mharc-qemu-arm@gnu.org; Tue, 29 Aug 2017 07:20:34 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:55873) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dmeZI-000526-NK for qemu-arm@nongnu.org; Tue, 29 Aug 2017 07:20:32 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dmeZF-0008EK-E1 for qemu-arm@nongnu.org; Tue, 29 Aug 2017 07:20:28 -0400 Received: from szxga05-in.huawei.com ([45.249.212.191]:2248) by eggs.gnu.org with esmtps (TLS1.0:RSA_ARCFOUR_SHA1:16) (Exim 4.71) (envelope-from ) id 1dmeZD-0008Aa-VV; Tue, 29 Aug 2017 07:20:25 -0400 Received: from 172.30.72.60 (EHLO DGGEMS414-HUB.china.huawei.com) ([172.30.72.60]) by dggrg05-dlp.huawei.com (MOS 4.4.6-GA FastPath queued) with ESMTP id DGE92841; Tue, 29 Aug 2017 19:16:09 +0800 (CST) Received: from [127.0.0.1] (10.142.68.147) by DGGEMS414-HUB.china.huawei.com (10.3.19.214) with Microsoft SMTP Server id 14.3.301.0; Tue, 29 Aug 2017 19:15:56 +0800 To: Igor Mammedov References: <1503066227-18251-1-git-send-email-gengdongjiu@huawei.com> <1503066227-18251-3-git-send-email-gengdongjiu@huawei.com> <20170829122053.36cf550c@nial.brq.redhat.com> CC: , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , From: gengdongjiu Message-ID: Date: Tue, 29 Aug 2017 19:15:36 +0800 User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:45.0) Gecko/20100101 Thunderbird/45.7.1 MIME-Version: 1.0 In-Reply-To: <20170829122053.36cf550c@nial.brq.redhat.com> Content-Type: text/plain; charset="windows-1252" Content-Transfer-Encoding: 7bit X-Originating-IP: [10.142.68.147] X-CFilter-Loop: Reflected X-Mirapoint-Virus-RAPID-Raw: score=unknown(0), refid=str=0001.0A090203.59A54CFA.0092, ss=1, re=0.000, recu=0.000, reip=0.000, cl=1, cld=1, fgs=0, ip=0.0.0.0, so=2014-11-16 11:51:01, dmn=2013-03-21 17:37:32 X-Mirapoint-Loop-Id: 4783d4ae485d8d4fa5310e9ce3849844 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.4.x-2.6.x [generic] [fuzzy] X-Received-From: 45.249.212.191 Subject: Re: [Qemu-arm] [Qemu-devel] [PATCH v11 2/6] ACPI: Add APEI GHES Table Generation support X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 29 Aug 2017 11:20:32 -0000 Igor, Thank you very much for your review and comments, I will check your comments in detail and reply to you. On 2017/8/29 18:20, Igor Mammedov wrote: > On Fri, 18 Aug 2017 22:23:43 +0800 > Dongjiu Geng wrote: > >> This implements APEI GHES Table by passing the error CPER info >> to the guest via a fw_cfg_blob. After a CPER info is recorded, an >> SEA(Synchronous External Abort)/SEI(SError Interrupt) exception >> will be injected into the guest OS. > > it's a bit complex patch/functionality so I've just mosty skimmed and > commented only on structure of the patch and changes I'd like to see > so it would be more structured and review-able. > > I'd suggest to add doc patch first which will describe how it's > supposed to work between QEMU/firmware/guest OS with expected > flows. > >> Below is the table layout, the max number of error soure is 11, >> which is classified by notification type. >> >> etc/acpi/tables etc/hardware_errors >> ==================== ========================================== >> + +--------------------------+ +------------------+ >> | | HEST | | address | +--------------+ >> | +--------------------------+ | registers | | Error Status | >> | | GHES0 | | +----------------+ | Data Block 0 | >> | +--------------------------+ +--------->| |status_address0 |------------->| +------------+ >> | | ................. | | | +----------------+ | | CPER | >> | | error_status_address-----+-+ +------->| |status_address1 |----------+ | | CPER | >> | | ................. | | | +----------------+ | | | .... | >> | | read_ack_register--------+-+ | | ............. | | | | CPER | >> | | read_ack_preserve | | | +------------------+ | | +-+------------+ >> | | read_ack_write | | | +----->| |status_address10|--------+ | | Error Status | >> + +--------------------------+ | | | | +----------------+ | | | Data Block 1 | >> | | GHES1 | +-+-+----->| | ack_value0 | | +-->| +------------+ >> + +--------------------------+ | | | +----------------+ | | | CPER | >> | | ................. | | | +--->| | ack_value1 | | | | CPER | >> | | error_status_address-----+---+ | | | +----------------+ | | | .... | >> | | ................. | | | | | ............. | | | | CPER | >> | | read_ack_register--------+-----+-+ | +----------------+ | +-+------------+ >> | | read_ack_preserve | | +->| | ack_value10 | | | |.......... | >> | | read_ack_write | | | | +----------------+ | | +------------+ >> + +--------------------------| | | | | Error Status | >> | | ............... | | | | | Data Block 10| >> + +--------------------------+ | | +---->| +------------+ >> | | GHES10 | | | | | CPER | >> + +--------------------------+ | | | | CPER | >> | | ................. | | | | | .... | >> | | error_status_address-----+-----+ | | | CPER | >> | | ................. | | +-+------------+ >> | | read_ack_register--------+---------+ >> | | read_ack_preserve | >> | | read_ack_write | >> + +--------------------------+ > these diagram shows relations between tables which not necessarily bad > but as layout it's useless. > * Probably there is not much sense to have HEST table here, it's described > well enough in spec. You might just put reference here. > * these diagrams should go into doc/spec patch > * when you describe layout you need to show what and at what offsets > in which order in which blob/file is located. See ACPI spec for example > and/or docs/specs/acpi_nvdimm.txt docs/specs/acpi_mem_hotplug.txt for inspiration. > >> For GHESv2 error source, the OSPM must acknowledges the error via Read Ack register. >> so user space must check the ack value to avoid read-write race condition. >> >> Signed-off-by: Dongjiu Geng >> --- >> hw/acpi/aml-build.c | 2 + >> hw/acpi/hest_ghes.c | 345 ++++++++++++++++++++++++++++++++++++++++++++ >> hw/arm/virt-acpi-build.c | 6 + >> include/hw/acpi/aml-build.h | 1 + >> include/hw/acpi/hest_ghes.h | 47 ++++++ >> 5 files changed, 401 insertions(+) >> create mode 100644 hw/acpi/hest_ghes.c >> create mode 100644 include/hw/acpi/hest_ghes.h >> >> diff --git a/hw/acpi/aml-build.c b/hw/acpi/aml-build.c >> index 36a6cc4..6849e5f 100644 >> --- a/hw/acpi/aml-build.c >> +++ b/hw/acpi/aml-build.c >> @@ -1561,6 +1561,7 @@ void acpi_build_tables_init(AcpiBuildTables *tables) >> tables->table_data = g_array_new(false, true /* clear */, 1); >> tables->tcpalog = g_array_new(false, true /* clear */, 1); >> tables->vmgenid = g_array_new(false, true /* clear */, 1); >> + tables->hardware_errors = g_array_new(false, true /* clear */, 1); >> tables->linker = bios_linker_loader_init(); >> } >> >> @@ -1571,6 +1572,7 @@ void acpi_build_tables_cleanup(AcpiBuildTables *tables, bool mfre) >> g_array_free(tables->table_data, true); >> g_array_free(tables->tcpalog, mfre); >> g_array_free(tables->vmgenid, mfre); >> + g_array_free(tables->hardware_errors, mfre); >> } >> >> /* Build rsdt table */ >> diff --git a/hw/acpi/hest_ghes.c b/hw/acpi/hest_ghes.c >> new file mode 100644 >> index 0000000..ff6b5ef >> --- /dev/null >> +++ b/hw/acpi/hest_ghes.c >> @@ -0,0 +1,345 @@ >> +/* >> + * APEI GHES table Generation >> + * >> + * Copyright (C) 2017 huawei. >> + * >> + * Author: Dongjiu Geng >> + * >> + * This work is licensed under the terms of the GNU GPL, version 2 or later. >> + * See the COPYING file in the top-level directory. >> + * >> + */ >> + >> +#include "qemu/osdep.h" >> +#include "qmp-commands.h" >> +#include "hw/acpi/acpi.h" >> +#include "hw/acpi/aml-build.h" >> +#include "hw/acpi/hest_ghes.h" >> +#include "hw/nvram/fw_cfg.h" >> +#include "sysemu/sysemu.h" >> +#include "qemu/error-report.h" >> + >> +/* The structure that stands for the layout >> + * GHES_ERRORS_FW_CFG_FILE fw_cfg blob >> + * >> + * etc/hardware_errors >> + * ========================================== >> + * +------------------+ >> + * | address | +--------------+ >> + * | registers | | Error Status | >> + * | +----------------+ | Data Block 0 | >> + * | |status_address0 |------------->| +------------+ >> + * | +----------------+ | | CPER | >> + * | |status_address1 |----------+ | | CPER | >> + * | +----------------+ | | | .... | >> + * | |............. | | | | CPER | >> + * | +----------------+ | | +------------+ >> + * | |status_address10|-----+ | | Error Status | >> + * | +----------------+ | | | Data Block 1 | >> + * | |ack_value0 | | +-->| +------------+ >> + * | +----------------+ | | | CPER | >> + * | |ack_value1 | | | | CPER | >> + * | +----------------+ | | | .... | >> + * | | ............. | | | | CPER | >> + * | +----------------+ | +-+------------+ >> + * | |ack_value10 | | | |.......... | >> + * | +----------------+ | | +------------+ >> + * | | Error Status | >> + * | | Data Block10 | >> + * +------->+------------+ >> + * | | CPER | >> + * | | CPER | >> + * | | .... | >> + * | | CPER | >> + * +-+------------+ >> + */ >> +struct hardware_errors_buffer { >> + /* Generic Error Status Block register */ >> + uint64_t gesb_address[GHES_ACPI_HEST_NOTIFY_RESERVED]; >> + uint64_t ack_value[GHES_ACPI_HEST_NOTIFY_RESERVED]; >> + char gesb[GHES_MAX_RAW_DATA_LENGTH][GHES_ACPI_HEST_NOTIFY_RESERVED]; >> +}; >> + >> +static int ghes_record_cper(uint64_t error_block_address, >> + uint64_t error_physical_addr) >> +{ >> + AcpiGenericErrorStatus block; >> + AcpiGenericErrorData *gdata; >> + UefiCperSecMemErr *mem_err; >> + uint64_t current_block_length; >> + unsigned char *buffer; >> + /* memory section */ >> + char mem_section_id_le[] = {0x14, 0x11, 0xBC, 0xA5, 0x64, 0x6F, 0xDE, >> + 0x4E, 0xB8, 0x63, 0x3E, 0x83, 0xED, 0x7C, >> + 0x83, 0xB1}; >> + >> + cpu_physical_memory_read(error_block_address, &block, >> + sizeof(AcpiGenericErrorStatus)); >> + >> + /* Get the current generic error status block length */ >> + current_block_length = sizeof(AcpiGenericErrorStatus) + >> + le32_to_cpu(block.data_length); >> + >> + /* If the Generic Error Status Block is NULL, update >> + * the block header >> + */ >> + if (!block.block_status) { >> + block.block_status = ACPI_GEBS_UNCORRECTABLE; >> + block.error_severity = ACPI_CPER_SEV_RECOVERABLE; >> + } >> + >> + block.data_length += cpu_to_le32(sizeof(AcpiGenericErrorData)); >> + block.data_length += cpu_to_le32(sizeof(UefiCperSecMemErr)); >> + >> + /* check whether it runs out of the preallocated memory */ >> + if ((le32_to_cpu(block.data_length) + sizeof(AcpiGenericErrorStatus)) > >> + GHES_MAX_RAW_DATA_LENGTH) { >> + error_report("Record CPER out of boundary!!!"); >> + return GHES_CPER_FAIL; >> + } >> + >> + /* Write back the Generic Error Status Block to guest memory */ >> + cpu_physical_memory_write(error_block_address, &block, >> + sizeof(AcpiGenericErrorStatus)); >> + >> + /* Fill in Generic Error Data Entry */ >> + buffer = g_malloc0(sizeof(AcpiGenericErrorData) + >> + sizeof(UefiCperSecMemErr)); >> + >> + >> + memset(buffer, 0, sizeof(AcpiGenericErrorData) + sizeof(UefiCperSecMemErr)); > looks redundant, g_malloc0 does it for you > >> + gdata = (AcpiGenericErrorData *)buffer; >> + >> + /* Memory section */ >> + memcpy(&(gdata->section_type_le), &mem_section_id_le, >> + sizeof(mem_section_id_le)); >> + >> + /* error severity is recoverable */ >> + gdata->error_severity = ACPI_CPER_SEV_RECOVERABLE; >> + gdata->revision = 0x300; /* the revision number is 0x300 */ >> + gdata->error_data_length = cpu_to_le32(sizeof(UefiCperSecMemErr)); >> + >> + mem_err = (UefiCperSecMemErr *) (gdata + 1); >> + >> + /* User space only handle the memory section CPER */ >> + >> + /* Hard code to Multi-bit ECC error */ >> + mem_err->validation_bits |= cpu_to_le32(UEFI_CPER_MEM_VALID_ERROR_TYPE); >> + mem_err->error_type = cpu_to_le32(UEFI_CPER_MEM_ERROR_TYPE_MULTI_ECC); >> + >> + /* Record the physical address at which the memory error occurred */ >> + mem_err->validation_bits |= cpu_to_le32(UEFI_CPER_MEM_VALID_PA); >> + mem_err->physical_addr = cpu_to_le32(error_physical_addr); > > I'd prefer for you to use build_append_int_noprefix() API to compose > whole error status block > > and try to get rid of most structures you introduce in patch 1/6, > as they will be left unused after that. > >> + >> + /* Write back the Generic Error Data Entry to guest memory */ >> + cpu_physical_memory_write(error_block_address + current_block_length, >> + buffer, sizeof(AcpiGenericErrorData) + sizeof(UefiCperSecMemErr)); >> + >> + g_free(buffer); >> + return GHES_CPER_OK; >> +} >> + >> +static void >> +build_address(GArray *table_data, BIOSLinker *linker, >> + uint32_t dst_patched_offset, uint32_t src_offset, >> + uint8_t address_space_id , uint8_t register_bit_width, >> + uint8_t register_bit_offset, uint8_t access_size) >> +{ >> + uint32_t address_size = sizeof(struct AcpiGenericAddress) - >> + offsetof(struct AcpiGenericAddress, address); >> + >> + /* Address space */ >> + build_append_int_noprefix(table_data, address_space_id, 1); >> + /* register bit width */ >> + build_append_int_noprefix(table_data, register_bit_width, 1); >> + /* register bit offset */ >> + build_append_int_noprefix(table_data, register_bit_offset, 1); >> + /* access size */ >> + build_append_int_noprefix(table_data, access_size, 1); >> + acpi_data_push(table_data, address_size); >> + >> + /* Patch address of ERRORS fw_cfg blob into the TABLE fw_cfg blob so OSPM >> + * can retrieve and read it. the address size is 64 bits. >> + */ >> + bios_linker_loader_add_pointer(linker, >> + ACPI_BUILD_TABLE_FILE, dst_patched_offset, sizeof(uint64_t), >> + GHES_ERRORS_FW_CFG_FILE, src_offset); >> +} > It's mostly generic GAS structure with linker addition. > I'd suggest to reuse something like > https://github.com/imammedo/qemu/commit/3d2fd6d13a3ea298d2ee814835495ce6241d085c > to build GAS and use bios_linker_loader_add_pointer() directly in ghes_build_acpi(). > >> +void ghes_build_acpi(GArray *table_data, GArray *hardware_error, >> + BIOSLinker *linker) >> +{ >> + uint32_t ghes_start = table_data->len; >> + uint32_t address_size, error_status_address_offset; >> + uint32_t read_ack_register_offset, i; >> + >> + address_size = sizeof(struct AcpiGenericAddress) - >> + offsetof(struct AcpiGenericAddress, address); > it's confusing name for var, > AcpiGenericAddress::address is fixed unsigned 64 bit integer per spec > also, I'm not sure why it's needed at all. > >> + >> + error_status_address_offset = ghes_start + >> + sizeof(AcpiHardwareErrorSourceTable) + >> + offsetof(AcpiGenericHardwareErrorSourceV2, error_status_address) + >> + offsetof(struct AcpiGenericAddress, address); >> + >> + read_ack_register_offset = ghes_start + >> + sizeof(AcpiHardwareErrorSourceTable) + >> + offsetof(AcpiGenericHardwareErrorSourceV2, read_ack_register) + >> + offsetof(struct AcpiGenericAddress, address); > it's really hard to get why you use offsetof() so much in this function, > to me above code totally unreadable. > >> + acpi_data_push(hardware_error, >> + offsetof(struct hardware_errors_buffer, ack_value)); > it looks like you are trying to build several tables within one function, > so it's hard to get what's going on. > I'd suggest to build separate table independently where it's possible. > > i.e. build independent tables first > and only then build dependent tables passing to it pointers > to previously build table if necessary. > >> + for (i = 0; i < GHES_ACPI_HEST_NOTIFY_RESERVED; i++) >> + /* Initialize read ack register */ >> + build_append_int_noprefix((void *)hardware_error, 1, 8); >> + >> + /* Reserved the total size for ERRORS fw_cfg blob >> + */ >> + acpi_data_push(hardware_error, sizeof(struct hardware_errors_buffer)); >> + >> + /* Allocate guest memory for the Data fw_cfg blob */ >> + bios_linker_loader_alloc(linker, GHES_ERRORS_FW_CFG_FILE, hardware_error, >> + 1, false); >> + /* Reserve table header size */ >> + acpi_data_push(table_data, sizeof(AcpiTableHeader)); >> + >> + build_append_int_noprefix(table_data, GHES_ACPI_HEST_NOTIFY_RESERVED, 4); > GHES_ACPI_HEST_NOTIFY_RESERVED - name doesn't actually tell what it is > I'd suggest to use spec field name wit table prefix, ex: > ACPI_HEST_ERROR_SOURCE_COUNT > > also, beside build_append_int_noprefix() you need to at least > add comment that exactly matches field from spec. > > the same applies to other fields you are adding in this patch > >> + >> + for (i = 0; i < GHES_ACPI_HEST_NOTIFY_RESERVED; i++) { >> + build_append_int_noprefix(table_data, >> + ACPI_HEST_SOURCE_GENERIC_ERROR_V2, 2); /* type */ >> + /* source id */ >> + build_append_int_noprefix(table_data, cpu_to_le16(i), 2); >> + /* related source id */ >> + build_append_int_noprefix(table_data, 0xffff, 2); >> + build_append_int_noprefix(table_data, 0, 1); /* flags */ >> + >> + /* Currently only enable SEA notification type to avoid the kernel >> + * warning, reserve the space for other notification error source >> + */ >> + if (i == ACPI_HEST_NOTIFY_SEA) { >> + build_append_int_noprefix(table_data, 1, 1); /* enabled */ >> + } else { >> + build_append_int_noprefix(table_data, 0, 1); /* enabled */ >> + } >> + >> + /* The number of error status block per generic hardware error source */ >> + build_append_int_noprefix(table_data, 1, 4); >> + /* Max sections per record */ >> + build_append_int_noprefix(table_data, 1, 4); >> + /* Max raw data length */ >> + build_append_int_noprefix(table_data, GHES_MAX_RAW_DATA_LENGTH, 4); >> + >> + /* Build error status address*/ >> + build_address(table_data, linker, error_status_address_offset + i * >> + sizeof(AcpiGenericHardwareErrorSourceV2), i * address_size, >> + AML_SYSTEM_MEMORY, 0x40, 0, 4 /* QWord access */); > just do something like this instead of build_address(): > build_append_gas() > bios_linker_loader_add_pointer() > > also register width 0x40 looks suspicious, where does it come from? > While at it do you have a real hardware which has HEST table that you re trying to model after? > I'd like to see HEST and other related tables from it. > >> + >> + /* Hardware error notification structure */ >> + build_append_int_noprefix(table_data, i, 1); /* type */ >> + /* length */ >> + build_append_int_noprefix(table_data, sizeof(AcpiHestNotify), 1); >> + build_append_int_noprefix(table_data, 0, 26); >> + >> + /* Error Status Block Length */ >> + build_append_int_noprefix(table_data, >> + cpu_to_le32(GHES_MAX_RAW_DATA_LENGTH), 4); >> + >> + /* Build read ack register */ >> + build_address(table_data, linker, read_ack_register_offset + i * >> + sizeof(AcpiGenericHardwareErrorSourceV2), >> + offsetof(struct hardware_errors_buffer, ack_value) + >> + i * address_size, AML_SYSTEM_MEMORY, 0x40, 0, >> + 4 /* QWord access */); >> + >> + /* Read ack preserve */ >> + build_append_int_noprefix(table_data, cpu_to_le64(0xfffffffe), 8); >> + >> + /* Read ack write */ >> + build_append_int_noprefix(table_data, cpu_to_le64(0x1), 8); >> + } >> + >> + for (i = 0; i < GHES_ACPI_HEST_NOTIFY_RESERVED; i++) >> + /* Patch address of generic error status block into >> + * the address register so OSPM can retrieve and read it. >> + */ >> + bios_linker_loader_add_pointer(linker, >> + GHES_ERRORS_FW_CFG_FILE, address_size * i, address_size, >> + GHES_ERRORS_FW_CFG_FILE, >> + offsetof(struct hardware_errors_buffer, gesb) + >> + i * GHES_MAX_RAW_DATA_LENGTH); >> + >> + /* Patch address of ERRORS fw_cfg blob into the ADDR fw_cfg blob >> + * so QEMU can write the ERRORS there. The address is expected to be >> + * < 4GB, but write 64 bits anyway. >> + */ >> + bios_linker_loader_write_pointer(linker, GHES_DATA_ADDR_FW_CFG_FILE, >> + 0, address_size, GHES_ERRORS_FW_CFG_FILE, >> + offsetof(struct hardware_errors_buffer, gesb)); >> + >> + build_header(linker, table_data, >> + (void *)(table_data->data + ghes_start), "HEST", >> + table_data->len - ghes_start, 1, NULL, "GHES"); >> +} >> + >> +static GhesState ges; >> +void ghes_add_fw_cfg(FWCfgState *s, GArray *hardware_error) >> +{ >> + >> + size_t request_block_size = sizeof(uint64_t) + GHES_MAX_RAW_DATA_LENGTH; >> + size_t size = GHES_ACPI_HEST_NOTIFY_RESERVED * request_block_size; >> + >> + /* Create a read-only fw_cfg file for GHES */ >> + fw_cfg_add_file(s, GHES_ERRORS_FW_CFG_FILE, hardware_error->data, >> + size); >> + /* Create a read-write fw_cfg file for Address */ >> + fw_cfg_add_file_callback(s, GHES_DATA_ADDR_FW_CFG_FILE, NULL, NULL, >> + &ges.ghes_addr_le, sizeof(ges.ghes_addr_le), false); >> +} >> + >> +bool ghes_update_guest(uint32_t notify, uint64_t physical_address) >> +{ >> + uint64_t error_block_addr; >> + uint64_t ack_value_addr, ack_value = 0; >> + int loop = 0, ack_value_size; >> + bool ret = GHES_CPER_FAIL; >> + >> + ack_value_size = (offsetof(struct hardware_errors_buffer, gesb) - >> + offsetof(struct hardware_errors_buffer, ack_value)) / >> + GHES_ACPI_HEST_NOTIFY_RESERVED; >> + >> + if (physical_address && notify < GHES_ACPI_HEST_NOTIFY_RESERVED) { >> + error_block_addr = ges.ghes_addr_le + notify * GHES_MAX_RAW_DATA_LENGTH; >> + error_block_addr = le32_to_cpu(error_block_addr); >> + >> + ack_value_addr = ges.ghes_addr_le - >> + (GHES_ACPI_HEST_NOTIFY_RESERVED - notify) * ack_value_size; >> +retry: >> + cpu_physical_memory_read(ack_value_addr, &ack_value, ack_value_size); >> + if (!ack_value) { >> + if (loop < 3) { >> + usleep(100 * 1000); >> + loop++; >> + goto retry; >> + } else { >> + error_report("Last time OSPM does not acknowledge the error," >> + " record CPER failed this time, set the ack value to" >> + " avoid blocking next time CPER record! exit"); >> + ack_value = 1; >> + cpu_physical_memory_write(ack_value_addr, >> + &ack_value, ack_value_size); >> + return ret; >> + } >> + } else { >> + /* A zero value in ghes_addr means that BIOS has not yet written >> + * the address >> + */ >> + if (error_block_addr) { >> + ack_value = 0; >> + cpu_physical_memory_write(ack_value_addr, >> + &ack_value, ack_value_size); >> + ret = ghes_record_cper(error_block_addr, physical_address); >> + } >> + } >> + } >> + return ret; >> +} >> diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c >> index 3d78ff6..def1ec1 100644 >> --- a/hw/arm/virt-acpi-build.c >> +++ b/hw/arm/virt-acpi-build.c >> @@ -45,6 +45,7 @@ >> #include "hw/arm/virt.h" >> #include "sysemu/numa.h" >> #include "kvm_arm.h" >> +#include "hw/acpi/hest_ghes.h" >> >> #define ARM_SPI_BASE 32 >> #define ACPI_POWER_BUTTON_DEVICE "PWRB" >> @@ -771,6 +772,9 @@ void virt_acpi_build(VirtMachineState *vms, AcpiBuildTables *tables) >> acpi_add_table(table_offsets, tables_blob); >> build_spcr(tables_blob, tables->linker, vms); >> >> + acpi_add_table(table_offsets, tables_blob); >> + ghes_build_acpi(tables_blob, tables->hardware_errors, tables->linker); >> + >> if (nb_numa_nodes > 0) { >> acpi_add_table(table_offsets, tables_blob); >> build_srat(tables_blob, tables->linker, vms); >> @@ -887,6 +891,8 @@ void virt_acpi_setup(VirtMachineState *vms) >> fw_cfg_add_file(vms->fw_cfg, ACPI_BUILD_TPMLOG_FILE, tables.tcpalog->data, >> acpi_data_len(tables.tcpalog)); >> >> + ghes_add_fw_cfg(vms->fw_cfg, tables.hardware_errors); >> + >> build_state->rsdp_mr = acpi_add_rom_blob(build_state, tables.rsdp, >> ACPI_BUILD_RSDP_FILE, 0); >> >> diff --git a/include/hw/acpi/aml-build.h b/include/hw/acpi/aml-build.h >> index 88d0738..7f7b55c 100644 >> --- a/include/hw/acpi/aml-build.h >> +++ b/include/hw/acpi/aml-build.h >> @@ -211,6 +211,7 @@ struct AcpiBuildTables { >> GArray *rsdp; >> GArray *tcpalog; >> GArray *vmgenid; >> + GArray *hardware_errors; >> BIOSLinker *linker; >> } AcpiBuildTables; >> >> diff --git a/include/hw/acpi/hest_ghes.h b/include/hw/acpi/hest_ghes.h >> new file mode 100644 >> index 0000000..0772756 >> --- /dev/null >> +++ b/include/hw/acpi/hest_ghes.h >> @@ -0,0 +1,47 @@ >> +/* >> + * This program is free software; you can redistribute it and/or modify >> + * it under the terms of the GNU General Public License as published by >> + * the Free Software Foundation; either version 2 of the License, or >> + * (at your option) any later version. >> + >> + * This program is distributed in the hope that it will be useful, >> + * but WITHOUT ANY WARRANTY; without even the implied warranty of >> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the >> + * GNU General Public License for more details. >> + * >> + * Authors: >> + * Dongjiu Geng >> + * >> + * You should have received a copy of the GNU General Public License along >> + * with this program; if not, see . >> + */ >> + >> +#ifndef ACPI_GHES_H >> +#define ACPI_GHES_H >> + >> +#include "hw/acpi/bios-linker-loader.h" >> + >> +#define GHES_ERRORS_FW_CFG_FILE "etc/hardware_errors" >> +#define GHES_DATA_ADDR_FW_CFG_FILE "etc/hardware_errors_addr" >> + >> +#define GHES_GAS_ADDRESS_OFFSET 4 >> +#define GHES_ERROR_STATUS_ADDRESS_OFFSET 20 >> +#define GHES_NOTIFICATION_STRUCTURE 32 >> + >> +#define GHES_CPER_OK 1 >> +#define GHES_CPER_FAIL 0 >> + >> +#define GHES_ACPI_HEST_NOTIFY_RESERVED 11 >> +/* The max size in Bytes for one error block */ >> +#define GHES_MAX_RAW_DATA_LENGTH 0x1000 >> + >> + >> +typedef struct GhesState { >> + uint64_t ghes_addr_le; >> +} GhesState; >> + >> +void ghes_build_acpi(GArray *table_data, GArray *hardware_error, >> + BIOSLinker *linker); >> +void ghes_add_fw_cfg(FWCfgState *s, GArray *hardware_errors); >> +bool ghes_update_guest(uint32_t notify, uint64_t error_physical_addr); >> +#endif > > > . > From MAILER-DAEMON Tue Aug 29 10:51:59 2017 Received: from list by lists.gnu.org with archive (Exim 4.71) id 1dmhrz-0007dQ-Ml for mharc-qemu-arm@gnu.org; Tue, 29 Aug 2017 10:51:59 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:35405) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dmhrx-0007bb-4a for qemu-arm@nongnu.org; Tue, 29 Aug 2017 10:51:57 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dmhrt-0002kT-8G for qemu-arm@nongnu.org; Tue, 29 Aug 2017 10:51:57 -0400 Received: from mail-pg0-x235.google.com ([2607:f8b0:400e:c05::235]:34572) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1dmhrt-0002kJ-0W for qemu-arm@nongnu.org; Tue, 29 Aug 2017 10:51:53 -0400 Received: by mail-pg0-x235.google.com with SMTP id y15so11537808pgc.1 for ; Tue, 29 Aug 2017 07:51:52 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=subject:to:cc:references:from:message-id:date:user-agent :mime-version:in-reply-to:content-language:content-transfer-encoding; bh=thpuyTi89PF/MxBd8Kqwj95uNLxUhqR4tu6B8ByJmxU=; b=dBRbL7TR6FgrW2FZbdmwL30Hf3oHd+y7UIt0YMaFBSkPvlXF8hd23ZvNsI30ayDomb 6OQg0gAP6o0aKx42f6X60yzcv/tGSIef4HabEp9ApxGs2CKy7TStQCtSiNBulFKYHTQd V9Kq7HLiyvvs3meoai5/Fc0+y9XeGmwDs/2BQ= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:subject:to:cc:references:from:message-id:date :user-agent:mime-version:in-reply-to:content-language :content-transfer-encoding; bh=thpuyTi89PF/MxBd8Kqwj95uNLxUhqR4tu6B8ByJmxU=; b=fVZRjZf6Uz/jU+ZHgwKNF2qyL+lYuYo1wkadsK/PFYsaUvop/RwVHnJBvzK509gntx g02Rb7ao+1UCwnL7+X1MQsv6tUVCnXEAyMDEbwztnnuZFB683RyHV6hW0Y9cRBb+gmvs WWQefTDpAcb4doCR6XjTsVjvQT7kPFPNipjopWLmGaagJDimCfNaLYm/WEVUo2/EyZ1a +JjKFaxwl/yx8H8lAjCRg93/rF7qMdhZxNDApX+G4YwxD3urqrIuzUKxY9Z9H5vh2kDR Z2nX124nqgYN5bR4OZ77CHsz/cIqJTj+PuBz9o6drcJJz7ihdN1ModW5b01UXWIw+oDJ pdfA== X-Gm-Message-State: AHYfb5ide/HdP3zxuqSmkwq3uXIsKMu70hx91/+c3yXMd1L2KvJD7rt8 qpdm7rMpjVTYZ36A X-Received: by 10.99.67.130 with SMTP id q124mr555170pga.73.1504018311734; Tue, 29 Aug 2017 07:51:51 -0700 (PDT) Received: from bigtime.twiddle.net (97-126-108-236.tukw.qwest.net. [97.126.108.236]) by smtp.gmail.com with ESMTPSA id s81sm5752498pfg.78.2017.08.29.07.51.50 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 29 Aug 2017 07:51:50 -0700 (PDT) To: Pranith Kumar , alex.bennee@linaro.org, Claudio Fontana , Andrzej Zaborowski , Aurelien Jarno , Alexander Graf , "open list:AArch64 target" , "open list:All patches CC here" Cc: pbonzini@redhat.com References: <20170829063313.10237-1-bobby.prani@gmail.com> <20170829063313.10237-3-bobby.prani@gmail.com> From: Richard Henderson Message-ID: <0ad72a04-83d2-8db8-2375-0380642cbd66@linaro.org> Date: Tue, 29 Aug 2017 07:51:48 -0700 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.2.1 MIME-Version: 1.0 In-Reply-To: <20170829063313.10237-3-bobby.prani@gmail.com> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 7bit X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::235 Subject: Re: [Qemu-arm] [RFC v3 PATCH 3/5] mttcg: Add tcg target default memory ordering X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 29 Aug 2017 14:51:58 -0000 On 08/28/2017 11:33 PM, Pranith Kumar wrote: > Signed-off-by: Pranith Kumar > --- > tcg/aarch64/tcg-target.h | 2 ++ > tcg/arm/tcg-target.h | 2 ++ > tcg/ia64/tcg-target.h | 2 ++ > tcg/mips/tcg-target.h | 2 ++ > tcg/ppc/tcg-target.h | 2 ++ > tcg/s390/tcg-target.h | 2 ++ > tcg/sparc/tcg-target.h | 2 ++ > 7 files changed, 14 insertions(+) Reviewed-by: Richard Henderson r~ From MAILER-DAEMON Tue Aug 29 11:02:03 2017 Received: from list by lists.gnu.org with archive (Exim 4.71) id 1dmi1j-0003gt-Fu for mharc-qemu-arm@gnu.org; Tue, 29 Aug 2017 11:02:03 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:38774) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dmi1g-0003ex-O1 for qemu-arm@nongnu.org; Tue, 29 Aug 2017 11:02:01 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dmi1b-00072t-6l for qemu-arm@nongnu.org; Tue, 29 Aug 2017 11:02:00 -0400 Received: from mail-pf0-x230.google.com ([2607:f8b0:400e:c00::230]:36517) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1dmi1b-00072Y-1S for qemu-arm@nongnu.org; Tue, 29 Aug 2017 11:01:55 -0400 Received: by mail-pf0-x230.google.com with SMTP id z87so10958804pfi.3 for ; Tue, 29 Aug 2017 08:01:54 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=subject:to:references:from:message-id:date:user-agent:mime-version :in-reply-to:content-language:content-transfer-encoding; bh=LKBU0WUKPMb/q3fXiJRYxg3Mc4KrXwkY+17UOZ/wFzI=; b=MH+azhuRaoUPIRw83JrRLvOujt3WzSkPjhFSZ3e6XJIHE8aAxreuSLCmf2akHBNtzl VyMysuIAEvg69MpcoYN4XYNPZ+81Y5fIDH9rc0zaTagzFF+a7tMJdolNF8Ii+trfNt1Q RelyxpAfsPkBJsmZnhSiqyqtcOPbN505bM8GI= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:subject:to:references:from:message-id:date :user-agent:mime-version:in-reply-to:content-language :content-transfer-encoding; bh=LKBU0WUKPMb/q3fXiJRYxg3Mc4KrXwkY+17UOZ/wFzI=; b=CU5zIwW2XmLtgK0DQI6TA3KBumZy8ca1ohOsXIonNdpEHmBzZNBMeNK8McWRyI7xOU 9+Shti7V7r+TX46CgRRtn2c67hDbDdlMmqSr6CBjgFSNNn66WE3ZOLUG11noV/gwyDeC K48JomE6drMm0i5stUWk9RvpdOhdUDGqM4HBzqloty8IIieKRqtVxgdvCtazo1egHyS1 u/zA4jL/C0sx6m7PcgIrIwc6LTDLDL+qVlNoPrmJ0ngr45CtKwrnFxEq7p3hK363kgOX GB2xhE8+o8XF5GA6nHv5KceU2kIZVR5YB0fCEDZxoPdKmiRFVJgObjFpyhtkFU6jRQ7Q ItDw== X-Gm-Message-State: AHYfb5j8TDZKFOGI4EbtTWR4Nj75FL96PUC30Dz6k/U+CGJ0XTSo0cqN ai7l0yEqVp/yU0iox07Q7w== X-Received: by 10.99.175.10 with SMTP id w10mr561692pge.373.1504018913503; Tue, 29 Aug 2017 08:01:53 -0700 (PDT) Received: from bigtime.twiddle.net (97-126-108-236.tukw.qwest.net. [97.126.108.236]) by smtp.gmail.com with ESMTPSA id s186sm5849280pfb.110.2017.08.29.08.01.51 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 29 Aug 2017 08:01:52 -0700 (PDT) To: Pranith Kumar , alex.bennee@linaro.org, Paolo Bonzini , Peter Crosthwaite , Claudio Fontana , Andrzej Zaborowski , Aurelien Jarno , Alexander Graf , Stefan Weil , "open list:Overall" , "open list:AArch64 target" References: <20170829063313.10237-1-bobby.prani@gmail.com> <20170829063313.10237-5-bobby.prani@gmail.com> From: Richard Henderson Message-ID: <3148d084-9bff-2d8e-f1a7-fba94a1e7f87@linaro.org> Date: Tue, 29 Aug 2017 08:01:50 -0700 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.2.1 MIME-Version: 1.0 In-Reply-To: <20170829063313.10237-5-bobby.prani@gmail.com> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 7bit X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::230 Subject: Re: [Qemu-arm] [RFC v3 PATCH 5/5] tcg/softmmu: Increase size of TLB caches X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 29 Aug 2017 15:02:01 -0000 On 08/28/2017 11:33 PM, Pranith Kumar wrote: > + * TODO: rewrite this comment > */ > -#define CPU_TLB_BITS \ > - MIN(8, \ > - TCG_TARGET_TLB_DISPLACEMENT_BITS - CPU_TLB_ENTRY_BITS - \ > - (NB_MMU_MODES <= 1 ? 0 : \ > - NB_MMU_MODES <= 2 ? 1 : \ > - NB_MMU_MODES <= 4 ? 2 : \ > - NB_MMU_MODES <= 8 ? 3 : 4)) > +#define CPU_TLB_BITS MIN(12, TCG_TARGET_TLB_MAX_INDEX_BITS) > Ah, no. This will cause several builds to fail. You still need to restrict the *total* size of the TLB to TCG_TARGET_TLB_DISPLACEMENT_BITS. (That's not a 100% accurate statement, but is close. See the QEMU_BUILD_BUG_ON in tcg/*/*.c for specifics.) The upshot is that if a target has 2 MMU modes, we can allow them to be bigger. But if it has 8, we have to make them smaller. I was expecting you to write MIN(MIN(12, TCG_TARGET_TLB_MAX_INDEX_BITS) TCG_TARGET_TLB_DISPLACEMENT_BITS - CPU_TLB_ENTRY_BITS - ...) r~ From MAILER-DAEMON Tue Aug 29 11:03:51 2017 Received: from list by lists.gnu.org with archive (Exim 4.71) id 1dmi3T-0004ls-NV for mharc-qemu-arm@gnu.org; Tue, 29 Aug 2017 11:03:51 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:39366) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dmi3P-0004ib-6U for qemu-arm@nongnu.org; Tue, 29 Aug 2017 11:03:51 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dmi3M-0007kj-8A for qemu-arm@nongnu.org; Tue, 29 Aug 2017 11:03:47 -0400 Received: from mail-pg0-x232.google.com ([2607:f8b0:400e:c05::232]:35378) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1dmi3M-0007kF-2e for qemu-arm@nongnu.org; Tue, 29 Aug 2017 11:03:44 -0400 Received: by mail-pg0-x232.google.com with SMTP id 63so11549167pgc.2 for ; Tue, 29 Aug 2017 08:03:43 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=subject:to:references:from:message-id:date:user-agent:mime-version :in-reply-to:content-language:content-transfer-encoding; bh=OtEDM/6KDcpI0YwzzJLiL5pla6GOa8b5egPWrLCFX4E=; b=ePMpQ46Htn1RsDKT0XbzqcC/QNSAx/B6g1f+OCG2dVDLyiOjxMFsBGqzl7AsIrvmTa KiViLIz37O6gKXkMJkqkEQe52Lt2qaePZyiLhmWXhgqhzj8h8xywSwYELl8dgx0p4a69 x/i8nro/I9JPgsiP3qsTUvSJWLNBh9ktmu6P0= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:subject:to:references:from:message-id:date :user-agent:mime-version:in-reply-to:content-language :content-transfer-encoding; bh=OtEDM/6KDcpI0YwzzJLiL5pla6GOa8b5egPWrLCFX4E=; b=rGR48IGDHvyju60erh/NFn+8AcoMY2PcEGg4uTMBrPDDMoHp6f+2qBKiVfa8mwKSpi 52i2jAPtQ1DCpQp1unFQGkJ7vzW+Zk5ZvH60/DjLPFNyb64N5ElpzxYTh7St1FGFVQEr G2ijLNDa74fEAeosX5oHeWBvapc9CajAkknKwpI2iDOgF3HWFABWhooZ+s8OIIoXLekZ fg25zPsiul8+GtI+77WI9Dt2loEyaeGfXgbGM7/GGyNEHcFZm894W67EaIMnZrx5fKXT uZn5fhYJYzVpYjtAScCcnXiIWJSaJjg76ad61TGHCuOm6ob7w9xZ3afIq7BSL1zs1qRU XtJw== X-Gm-Message-State: AHYfb5hBvleRTaBT32mOABxq2lSQfXzpzU6/OLqBf0CyG5WNGcj5dp+l 31lZ6ECeLme/sRi30uZl5w== X-Received: by 10.98.196.152 with SMTP id h24mr627534pfk.43.1504019022685; Tue, 29 Aug 2017 08:03:42 -0700 (PDT) Received: from bigtime.twiddle.net (97-126-108-236.tukw.qwest.net. [97.126.108.236]) by smtp.gmail.com with ESMTPSA id 23sm5187872pfh.183.2017.08.29.08.03.40 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 29 Aug 2017 08:03:40 -0700 (PDT) To: Pranith Kumar , alex.bennee@linaro.org, Paolo Bonzini , Peter Crosthwaite , Claudio Fontana , Andrzej Zaborowski , Aurelien Jarno , Alexander Graf , Stefan Weil , "open list:Overall" , "open list:AArch64 target" References: <20170829063313.10237-1-bobby.prani@gmail.com> <20170829063313.10237-5-bobby.prani@gmail.com> From: Richard Henderson Message-ID: <125ae0ee-8104-5b52-6b4b-22622ba56191@linaro.org> Date: Tue, 29 Aug 2017 08:03:39 -0700 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.2.1 MIME-Version: 1.0 In-Reply-To: <20170829063313.10237-5-bobby.prani@gmail.com> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 7bit X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::232 Subject: Re: [Qemu-arm] [RFC v3 PATCH 5/5] tcg/softmmu: Increase size of TLB caches X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 29 Aug 2017 15:03:51 -0000 On 08/28/2017 11:33 PM, Pranith Kumar wrote: > +#if HOST_LONG_BITS == 32 && TARGET_LONG_BITS == 32 > +#define TCG_TARGET_TLB_MAX_INDEX_BITS 28 > +#else > +#define TCG_TARGET_TLB_MAX_INDEX_BITS 27 > +#endif > + For the record, did it not work to actually write (32 - CPU_TLB_BITS)? I'm not fond of repeating the conditions that go into computing CPU_TLB_BITS. r~ From MAILER-DAEMON Tue Aug 29 11:21:36 2017 Received: from list by lists.gnu.org with archive (Exim 4.71) id 1dmiKe-0004bM-TR for mharc-qemu-arm@gnu.org; Tue, 29 Aug 2017 11:21:36 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:44061) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dmiKb-0004aF-Pq for qemu-arm@nongnu.org; Tue, 29 Aug 2017 11:21:35 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dmiKY-0007YJ-Lp for qemu-arm@nongnu.org; Tue, 29 Aug 2017 11:21:33 -0400 Received: from mail-pf0-x236.google.com ([2607:f8b0:400e:c00::236]:34494) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1dmiKY-0007Xi-F5 for qemu-arm@nongnu.org; Tue, 29 Aug 2017 11:21:30 -0400 Received: by mail-pf0-x236.google.com with SMTP id l87so1317589pfj.1 for ; Tue, 29 Aug 2017 08:21:30 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=subject:to:cc:references:from:message-id:date:user-agent :mime-version:in-reply-to:content-language:content-transfer-encoding; bh=UtM30ibO1gUisbAZUs4Adrd9tiargeZanA7vLL7Ykgg=; b=ea13pXv83zRDkctMEwulWxU4cnOk9DjDLd8PoU9KvdQiwLnbnJtEjM48Jq6t4s0WK2 rtnXIobYmrKv/TAyDdTWzZanpSFlcI6a95hP2AjBWhnmxo0rY+axpTt75kgdCguAceI/ O3wiyi9gopsD1bEFELu/Oj6alFZv/RGko9dKA= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:subject:to:cc:references:from:message-id:date :user-agent:mime-version:in-reply-to:content-language :content-transfer-encoding; bh=UtM30ibO1gUisbAZUs4Adrd9tiargeZanA7vLL7Ykgg=; b=priSMN03mg+koTY1MFGP7mJR1CJgBV3q4EmwMFHcorQf4UcErU22+xfSYMqiSgWyrN QiRcnTqPF40+PRGLU1aGa7sTUOZZPlKusjLw32SsQMp40TVUIobmwuPJRATrnBWSJWB7 kXXiAoOi9lGxQ+HJO5Vru2Mld5uBDFJK0Ub8bPZ2a2u71b8ikv8cREI1v/jOZCB+3LS8 xTja+UVN0hRxWszQVf3a9x9OwF0Q9iBMUW8OyzhsPHsQ48aWQMoqp7CerkGbCe1KE6QU IVcJqZbkAGHj2Hx5KcyVwFTScjWaHKuNO3ISMt0AraeqnbLRcyoMdGicJi0tun913Nic ePbA== X-Gm-Message-State: AHYfb5go0b+Jo2d7d+zEcg9HQJSkmU0+xdY64CxBaw5b76NXD37mU7IT /2yF7WnMLDDSyq2u X-Received: by 10.84.217.71 with SMTP id e7mr895959plj.103.1504020089451; Tue, 29 Aug 2017 08:21:29 -0700 (PDT) Received: from bigtime.twiddle.net (97-126-108-236.tukw.qwest.net. [97.126.108.236]) by smtp.gmail.com with ESMTPSA id m10sm5332786pgs.70.2017.08.29.08.21.28 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 29 Aug 2017 08:21:28 -0700 (PDT) To: Peter Maydell , qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: patches@linaro.org References: <1503414539-28762-1-git-send-email-peter.maydell@linaro.org> <1503414539-28762-2-git-send-email-peter.maydell@linaro.org> From: Richard Henderson Message-ID: <54b68f0d-5ef2-7d1c-3c1a-5b114dfb4921@linaro.org> Date: Tue, 29 Aug 2017 08:21:26 -0700 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.2.1 MIME-Version: 1.0 In-Reply-To: <1503414539-28762-2-git-send-email-peter.maydell@linaro.org> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 7bit X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::236 Subject: Re: [Qemu-arm] [Qemu-devel] [PATCH 01/20] target/arm: Implement ARMv8M's PMSAv8 registers X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 29 Aug 2017 15:21:35 -0000 On 08/22/2017 08:08 AM, Peter Maydell wrote: > As part of ARMv8M, we need to add support for the PMSAv8 MPU > architecture. > > PMSAv8 differs from PMSAv7 both in register/data layout (for instance > using base and limit registers rather than base and size) and also in > behaviour (for example it does not have subregions); rather than > trying to wedge it into the existing PMSAv7 code and data structures, > we define separate ones. > > This commit adds the data structures which hold the state for a > PMSAv8 MPU and the register interface to it. The implementation of > the MPU behaviour will be added in a subsequent commit. > > Signed-off-by: Peter Maydell > --- > target/arm/cpu.h | 13 ++++++ > hw/intc/armv7m_nvic.c | 122 ++++++++++++++++++++++++++++++++++++++++++++++---- > target/arm/cpu.c | 36 ++++++++++----- > target/arm/machine.c | 28 +++++++++++- > 4 files changed, 179 insertions(+), 20 deletions(-) Reviewed-by: Richard Henderson r~ From MAILER-DAEMON Tue Aug 29 11:25:32 2017 Received: from list by lists.gnu.org with archive (Exim 4.71) id 1dmiOS-0006Yr-DG for mharc-qemu-arm@gnu.org; Tue, 29 Aug 2017 11:25:32 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:45124) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dmiOQ-0006Yb-De for qemu-arm@nongnu.org; Tue, 29 Aug 2017 11:25:31 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dmiON-0000WU-Aw for qemu-arm@nongnu.org; Tue, 29 Aug 2017 11:25:30 -0400 Received: from mail-pg0-x231.google.com ([2607:f8b0:400e:c05::231]:34371) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1dmiON-0000Vy-4F for qemu-arm@nongnu.org; Tue, 29 Aug 2017 11:25:27 -0400 Received: by mail-pg0-x231.google.com with SMTP id y15so11803509pgc.1 for ; Tue, 29 Aug 2017 08:25:27 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=subject:to:cc:references:from:message-id:date:user-agent :mime-version:in-reply-to:content-language:content-transfer-encoding; bh=hJQ1Gy2Y8g7IAOVpsDlNACaufiG83gLiFi5RCc2hQ2w=; b=CTgyye/f7He9yMJf+oRTKsjt2RIkR2k/oCbgyr9EMrPmJEQJFdSfcspcC6dHyg7GCK P4g+wVeblddXKWlFFvbQoaZBoOpf0BuMr2jIwYvbRKgzPfsVv2JVP3t3sSYsg4Ht5p45 1EG3NaU2pHLXUibAe4miu8CVEuwhCPqcR46K4= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:subject:to:cc:references:from:message-id:date :user-agent:mime-version:in-reply-to:content-language :content-transfer-encoding; bh=hJQ1Gy2Y8g7IAOVpsDlNACaufiG83gLiFi5RCc2hQ2w=; b=El4QcbATGhvIUjiqxsgeJ0K9FBIAmx3DvQriUhC5cRaIW/Z8RUuZNACtgYGHHRaMhc 3QUDjIyFfthVenDBfvupSUOY93yKEmWbFlR+4sEagesHlKVrsJtdmnzQmhhFuxlt0Vyz mfJ64D5EET806mP1sIFFBEH42U4FBnhHALHFuywOY1/AQLznMpG0YEhIGsyn0AvxnanS ARS1P999gpgWCQufSk4I2DRWOO+BeyE0cAemJajQT7V3iqsADKf5KIbjC+TxS0WQ138d JOFaUEMqG2RKV3hXQ/3fkOad2dg5ld7Eaov8slGIxeKKwUl6nAexL21/PTGsQPpjP4eN 5j0A== X-Gm-Message-State: AHYfb5hv13c6q1BoiwIYTLSO/U/zhNZ0X945Ur2OHWCAC0YKmeMPdRHN h5ehsflL0ISZ/Erh X-Received: by 10.99.126.91 with SMTP id o27mr636598pgn.297.1504020326240; Tue, 29 Aug 2017 08:25:26 -0700 (PDT) Received: from bigtime.twiddle.net (97-126-108-236.tukw.qwest.net. [97.126.108.236]) by smtp.gmail.com with ESMTPSA id a13sm5172825pgd.71.2017.08.29.08.25.25 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 29 Aug 2017 08:25:25 -0700 (PDT) To: Peter Maydell , qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: patches@linaro.org References: <1503414539-28762-1-git-send-email-peter.maydell@linaro.org> <1503414539-28762-3-git-send-email-peter.maydell@linaro.org> From: Richard Henderson Message-ID: <7eefa11e-5daa-1748-0a0f-ab99c8d1cdf0@linaro.org> Date: Tue, 29 Aug 2017 08:25:23 -0700 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.2.1 MIME-Version: 1.0 In-Reply-To: <1503414539-28762-3-git-send-email-peter.maydell@linaro.org> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 7bit X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::231 Subject: Re: [Qemu-arm] [Qemu-devel] [PATCH 02/20] target/arm: Implement new PMSAv8 behaviour X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 29 Aug 2017 15:25:31 -0000 On 08/22/2017 08:08 AM, Peter Maydell wrote: > Implement the behavioural side of the new PMSAv8 specification. > > Signed-off-by: Peter Maydell > --- > target/arm/helper.c | 111 +++++++++++++++++++++++++++++++++++++++++++++++++++- > 1 file changed, 110 insertions(+), 1 deletion(-) Reviewed-by: Richard Henderson r~ From MAILER-DAEMON Tue Aug 29 11:28:54 2017 Received: from list by lists.gnu.org with archive (Exim 4.71) id 1dmiRh-0008Qb-S8 for mharc-qemu-arm@gnu.org; Tue, 29 Aug 2017 11:28:53 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:46178) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dmiRc-0008MK-Og for qemu-arm@nongnu.org; Tue, 29 Aug 2017 11:28:52 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dmiRZ-00021H-Le for qemu-arm@nongnu.org; Tue, 29 Aug 2017 11:28:48 -0400 Received: from mail-pg0-x22a.google.com ([2607:f8b0:400e:c05::22a]:34739) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1dmiRZ-00020u-Eg for qemu-arm@nongnu.org; Tue, 29 Aug 2017 11:28:45 -0400 Received: by mail-pg0-x22a.google.com with SMTP id y15so11828925pgc.1 for ; Tue, 29 Aug 2017 08:28:45 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=subject:to:cc:references:from:message-id:date:user-agent :mime-version:in-reply-to:content-language:content-transfer-encoding; bh=rv5kE7AHaY3Uyg3Te8j9gugxfMHxFd8j++m8sBEOCRA=; b=QbyUPrHsmIzPLwmf3mOxSL/0nhfoAj50laG9NKlA48scFvNM+oVzDoCZ3ZRDPzW8HO 2U1wEVmYk7fvW7FDJaF1THSiy23wflvw2CKD/YliNX9nGhanslqEW+j6ZdU9zCfA4vSb zQM49cud4kVLGR22AvvnzOAlOt/MzQFVt3l6w= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:subject:to:cc:references:from:message-id:date :user-agent:mime-version:in-reply-to:content-language :content-transfer-encoding; bh=rv5kE7AHaY3Uyg3Te8j9gugxfMHxFd8j++m8sBEOCRA=; b=GPwSMb/9cpQL5mbdAa+rtlilS+Ce5rVy/lPHSSBV6/LW1aBGLI8MGulqNU+V3nsM/Y Gflgm4XKYaOZdvAAxYAYzu2slq79SZWCYxj3AdgeRevtcwpKe2Zp/EPQTvI+PVuFGmEz NaLKn0xcKygCPc5zHj5e0RIcCkLpurTgAtRfvEYf0MByRShe6MITf3i6B2BHiLdBxbDw 2r5XDNe82muJzr/4i8MILZmDK4yVVFDQTmROB5sO/23xth2XBsMrgCWFFrepFV37HLmH J1ZmFfviB9GjYCpO64ScKbl7p29uYcJ1ccjIXVEsE0oshYTc/ove/3TvOfKqj/5f84Fx S8EQ== X-Gm-Message-State: AHYfb5jiZyPPdbPz6Gv1HmbjKRBbA/yZEDpNKwqMXYf5YkWX/qn3huTM 6wCtTA+5Y7eX83cd08Z+AA== X-Received: by 10.99.100.65 with SMTP id y62mr666588pgb.233.1504020524523; Tue, 29 Aug 2017 08:28:44 -0700 (PDT) Received: from bigtime.twiddle.net (97-126-108-236.tukw.qwest.net. [97.126.108.236]) by smtp.gmail.com with ESMTPSA id y70sm6491689pfg.53.2017.08.29.08.28.43 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 29 Aug 2017 08:28:43 -0700 (PDT) To: Peter Maydell , qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: patches@linaro.org References: <1503414539-28762-1-git-send-email-peter.maydell@linaro.org> <1503414539-28762-4-git-send-email-peter.maydell@linaro.org> From: Richard Henderson Message-ID: <9af3401e-031a-3ae3-d2fc-315dab3ef9e1@linaro.org> Date: Tue, 29 Aug 2017 08:28:41 -0700 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.2.1 MIME-Version: 1.0 In-Reply-To: <1503414539-28762-4-git-send-email-peter.maydell@linaro.org> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 7bit X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::22a Subject: Re: [Qemu-arm] [Qemu-devel] [PATCH 03/20] target/arm: Add state field, feature bit and migration for v8M secure state X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 29 Aug 2017 15:28:52 -0000 On 08/22/2017 08:08 AM, Peter Maydell wrote: > As the first step in implementing ARM v8M's security extension: > * add a new feature bit ARM_FEATURE_M_SECURITY > * add the CPU state field that indicates whether the CPU is > currently in the secure state > * add a migration subsection for this new state > (we will add the Secure copies of banked register state > to this subsection in later patches) > * add a #define for the one new-in-v8M exception type > * make the CPU debug log print S/NS status > > Signed-off-by: Peter Maydell > --- > target/arm/cpu.h | 3 +++ > target/arm/cpu.c | 4 ++++ > target/arm/machine.c | 20 ++++++++++++++++++++ > target/arm/translate.c | 8 +++++++- > 4 files changed, 34 insertions(+), 1 deletion(-) Reviewed-by: Richard Henderson r~ From MAILER-DAEMON Tue Aug 29 11:29:54 2017 Received: from list by lists.gnu.org with archive (Exim 4.71) id 1dmiSg-0000uE-3s for mharc-qemu-arm@gnu.org; Tue, 29 Aug 2017 11:29:54 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:46462) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dmiSc-0000nC-EY for qemu-arm@nongnu.org; Tue, 29 Aug 2017 11:29:52 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dmiSZ-0002v0-B8 for qemu-arm@nongnu.org; Tue, 29 Aug 2017 11:29:50 -0400 Received: from mail-pg0-x22a.google.com ([2607:f8b0:400e:c05::22a]:32922) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1dmiSZ-0002u8-5a for qemu-arm@nongnu.org; Tue, 29 Aug 2017 11:29:47 -0400 Received: by mail-pg0-x22a.google.com with SMTP id t3so11837620pgt.0 for ; Tue, 29 Aug 2017 08:29:47 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=subject:to:cc:references:from:message-id:date:user-agent :mime-version:in-reply-to:content-language:content-transfer-encoding; bh=I3NcubL//tMSU7UPk3eAg4rfEj/O4BiG3j+gmxxhq8E=; b=ZYvRfg0xhvVcvQ0/vwANwDslIgNYmjiuIg/VGsFXILT/I10ko4AduLjdnuMGXreSZg YYGEC6vzBaI58fUOY7H6fV7P56zqmx+ql9U7PQV6IdmV68tVKL+Owj9z1m3ifGpFDB/B /WSBAVMNcdW+FHVBkCr/FGf2QrPS08kACGtqo= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:subject:to:cc:references:from:message-id:date :user-agent:mime-version:in-reply-to:content-language :content-transfer-encoding; bh=I3NcubL//tMSU7UPk3eAg4rfEj/O4BiG3j+gmxxhq8E=; b=thqAL0Ig1NP9neoot9FLk2UYbzZcQkhZzealNtg3+3iDOqC+oSWDFUZQ/6Ac1MN15n ijEWE3Xk5jbCy51REQmGe9hYNDb+BYq93Mav0frSjY4Vrtn5y9gfV0GHViRRxP6ixZk0 EEmdBgLcXTFcTXqgQ3IG7ce1IcOO+BepQwGuu8gSE7NL3MPfxVx8zFG/xOkKenpKgxCg ja0I4Ker9UIPOfESF/TXbq/sI8lVHx8pTPdpXwIpoa8FdvGBDlVyWxMaJyv+CIdJqV0f kTYEI9c9/AFbNWmWXqjkBFQhmsUyh+4QVbfjNyVuyHNi1vqQpaH2iOU6Xi6WDGUtwL8j Of4g== X-Gm-Message-State: AHYfb5ht+/7Ipo0l9goF+kgL4aOp4Kgkh5HLBlHLfAhSDmAPVU0xTyew z4bO7KJfsVeZhjH2 X-Received: by 10.84.141.1 with SMTP id 1mr911686plu.189.1504020586404; Tue, 29 Aug 2017 08:29:46 -0700 (PDT) Received: from bigtime.twiddle.net (97-126-108-236.tukw.qwest.net. [97.126.108.236]) by smtp.gmail.com with ESMTPSA id 187sm5184567pgj.22.2017.08.29.08.29.45 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 29 Aug 2017 08:29:45 -0700 (PDT) To: Peter Maydell , qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: patches@linaro.org References: <1503414539-28762-1-git-send-email-peter.maydell@linaro.org> <1503414539-28762-5-git-send-email-peter.maydell@linaro.org> From: Richard Henderson Message-ID: Date: Tue, 29 Aug 2017 08:29:43 -0700 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.2.1 MIME-Version: 1.0 In-Reply-To: <1503414539-28762-5-git-send-email-peter.maydell@linaro.org> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 7bit X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::22a Subject: Re: [Qemu-arm] [Qemu-devel] [PATCH 04/20] target/arm: Register second AddressSpace for secure v8M CPUs X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 29 Aug 2017 15:29:52 -0000 On 08/22/2017 08:08 AM, Peter Maydell wrote: > If a v8M CPU supports the security extension then we need to > give it two AddressSpaces, the same way we do already for > an A profile core with EL3. > > Signed-off-by: Peter Maydell > --- > target/arm/cpu.c | 13 ++++++------- > 1 file changed, 6 insertions(+), 7 deletions(-) Reviewed-by: Richard Henderson r~ From MAILER-DAEMON Tue Aug 29 11:36:26 2017 Received: from list by lists.gnu.org with archive (Exim 4.71) id 1dmiZ0-0006b0-MT for mharc-qemu-arm@gnu.org; Tue, 29 Aug 2017 11:36:26 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:48971) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dmiYx-0006YC-5i for qemu-arm@nongnu.org; Tue, 29 Aug 2017 11:36:24 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dmiYr-0006EK-O0 for qemu-arm@nongnu.org; Tue, 29 Aug 2017 11:36:23 -0400 Received: from mail-pf0-x234.google.com ([2607:f8b0:400e:c00::234]:33334) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1dmiYr-0006DA-ID for qemu-arm@nongnu.org; Tue, 29 Aug 2017 11:36:17 -0400 Received: by mail-pf0-x234.google.com with SMTP id r62so11287534pfj.0 for ; Tue, 29 Aug 2017 08:36:17 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=subject:to:cc:references:from:message-id:date:user-agent :mime-version:in-reply-to:content-language:content-transfer-encoding; bh=t8VSKlByIYGuqNpJUT1NlBKJCWnKklAfxtKjj4qfaB4=; b=LksY/OfGNTqIX33guFy8UNnd+M7BiB6m5/dRLMOEA9oUaLj3qMHmv6neq0KVz+v2r+ aaxNYeR9ld5atBPqt2xp6ZyvzPUzpRil6vO9egjkR/EYKe60tk8jT/LP48t4NPD3OMVv KFs4Sh5k2yDsXszyeRouaiw8PWqmia6SdNi7g= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:subject:to:cc:references:from:message-id:date :user-agent:mime-version:in-reply-to:content-language :content-transfer-encoding; bh=t8VSKlByIYGuqNpJUT1NlBKJCWnKklAfxtKjj4qfaB4=; b=N2GK2ZNVkZLcQRWBUh808wC60t3HPqJMWtQB11lXRVTGCBmCOgUZAfppjWgh+KaKhQ SJANkLDcGHWqsCX0gAXolSVu3q1Q4TuIic3iaxSshfSHg9A+J6zD2+kZKwjN+qMhaTwU b3oTxG0OGYA8lL4P0GJ/xcZ1n2lSj8A3KsWrqkTxsUVMZAqfJa4GZJUCzDb17KttHtI+ GvMfeu5Qaqovjh08uImx0d6JORxpvQK2BXFVjhJnSuD4maV2sIAIq7iMo0sQJh3dJ9v5 bdmlzovcx/L1Y43hFQdCS6RnNuXNAPOpDRLSCzernX4KkQi8PkwoXLyi//Sq0MzgG51o Emdg== X-Gm-Message-State: AHYfb5hudzHz8Ij8iJiJOp9irL8oLEISvUDDIl7cmhXwDAXyEmgmPY52 SIWCTICm36yRatQR X-Received: by 10.98.13.28 with SMTP id v28mr741453pfi.174.1504020976542; Tue, 29 Aug 2017 08:36:16 -0700 (PDT) Received: from bigtime.twiddle.net (97-126-108-236.tukw.qwest.net. [97.126.108.236]) by smtp.gmail.com with ESMTPSA id l67sm5633053pfb.178.2017.08.29.08.36.14 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 29 Aug 2017 08:36:15 -0700 (PDT) To: Peter Maydell , qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: patches@linaro.org References: <1503414539-28762-1-git-send-email-peter.maydell@linaro.org> <1503414539-28762-6-git-send-email-peter.maydell@linaro.org> From: Richard Henderson Message-ID: <472c8319-b1d3-c91c-c9eb-6e138d8ba82f@linaro.org> Date: Tue, 29 Aug 2017 08:36:13 -0700 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.2.1 MIME-Version: 1.0 In-Reply-To: <1503414539-28762-6-git-send-email-peter.maydell@linaro.org> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 7bit X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::234 Subject: Re: [Qemu-arm] [Qemu-devel] [PATCH 05/20] target/arm: Add MMU indexes for secure v8M X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 29 Aug 2017 15:36:24 -0000 On 08/22/2017 08:08 AM, Peter Maydell wrote: > Now that MPU lookups can return different results for v8M > when the CPU is in secure vs non-secure state, we need to > have separate MMU indexes; add the secure counterparts > to the existing three M profile MMU indexes. > > Signed-off-by: Peter Maydell > --- > target/arm/cpu.h | 19 +++++++++++++++++-- > target/arm/helper.c | 9 ++++++++- > 2 files changed, 25 insertions(+), 3 deletions(-) Reviewed-by: Richard Henderson r~ From MAILER-DAEMON Tue Aug 29 11:37:49 2017 Received: from list by lists.gnu.org with archive (Exim 4.71) id 1dmiaL-0007iv-Ay for mharc-qemu-arm@gnu.org; Tue, 29 Aug 2017 11:37:49 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:49565) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dmiaJ-0007hL-At for qemu-arm@nongnu.org; Tue, 29 Aug 2017 11:37:48 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dmiaE-00079e-ED for qemu-arm@nongnu.org; Tue, 29 Aug 2017 11:37:47 -0400 Received: from mail-pg0-x235.google.com ([2607:f8b0:400e:c05::235]:35172) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1dmiaE-00079F-7z for qemu-arm@nongnu.org; Tue, 29 Aug 2017 11:37:42 -0400 Received: by mail-pg0-x235.google.com with SMTP id 63so11814161pgc.2 for ; Tue, 29 Aug 2017 08:37:42 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=subject:to:cc:references:from:message-id:date:user-agent :mime-version:in-reply-to:content-language:content-transfer-encoding; bh=siwc8mTYIiXQFvEUUF7VBAlVc62d8N3iC3uvmIZArus=; b=BfHntFYHhMJzFa6jSAXrbKmGy5zZN8K+I40JEB5BsJatHTL1G5yAKQDysVeIBGjCuB B5VSmBa7YT6pnSmPBx/k3ISmEfkytuXnr3npv2V9NCqDOKRAZSRtKnYsvFV/mQCB1huI DT0Ro9MhtGqPkEw/CPIkX7e4diDSKO4dTYJrQ= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:subject:to:cc:references:from:message-id:date :user-agent:mime-version:in-reply-to:content-language :content-transfer-encoding; bh=siwc8mTYIiXQFvEUUF7VBAlVc62d8N3iC3uvmIZArus=; b=mjCETUAUTOD+kbXxwqa2KqUHt29j+8kud5fuMRFR8Lr/4BllEADV03RW84XGfJYerB PbthoJyAuc/b01X9WxikNeWA1h36imP79e1Mbd2V96e5w0zqclLRavM1X6KdLb8CfzZn waGrz3z2iBpXeY85JfJGKVDFeFiOQaFIZLG4sXi7B7B4f1UsMOXzGbrs0OO7cPw9gbiE Il6aadC47+YPlYOXpwc3seGot9gtz2cb6l6dBbW3bmzLHN2vGbSJisTRGAwp3B51I48R xyzcAAsVsDnOGimqLLi2T1IySLYKLthtQLRNDcaORmtoSPAhrcooPzvLz7SdFDfz2wah Sq7Q== X-Gm-Message-State: AHYfb5jSKCXabQ26mhoK64gqQFDHHzkK4I48pt5k0aZQfYBXa+TQKUVx w2TVixI6eJPEs8IV X-Received: by 10.84.217.74 with SMTP id e10mr934283plj.119.1504021061328; Tue, 29 Aug 2017 08:37:41 -0700 (PDT) Received: from bigtime.twiddle.net (97-126-108-236.tukw.qwest.net. [97.126.108.236]) by smtp.gmail.com with ESMTPSA id s77sm4898683pfa.163.2017.08.29.08.37.40 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 29 Aug 2017 08:37:40 -0700 (PDT) To: Peter Maydell , qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: patches@linaro.org References: <1503414539-28762-1-git-send-email-peter.maydell@linaro.org> <1503414539-28762-7-git-send-email-peter.maydell@linaro.org> From: Richard Henderson Message-ID: Date: Tue, 29 Aug 2017 08:37:38 -0700 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.2.1 MIME-Version: 1.0 In-Reply-To: <1503414539-28762-7-git-send-email-peter.maydell@linaro.org> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 7bit X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::235 Subject: Re: [Qemu-arm] [Qemu-devel] [PATCH 06/20] target/arm: Make BASEPRI register banked for v8M X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 29 Aug 2017 15:37:48 -0000 On 08/22/2017 08:08 AM, Peter Maydell wrote: > Make the BASEPRI register banked if v8M security extensions are enabled. > > Note that we do not yet implement the functionality of the new > AIRCR.PRIS bit (which allows the effect of the NS copy of BASEPRI to > be restricted). > > Signed-off-by: Peter Maydell > --- > target/arm/cpu.h | 14 +++++++++++++- > hw/intc/armv7m_nvic.c | 4 ++-- > target/arm/helper.c | 10 ++++++---- > target/arm/machine.c | 3 ++- > 4 files changed, 23 insertions(+), 8 deletions(-) Reviewed-by: Richard Henderson r~ From MAILER-DAEMON Tue Aug 29 11:39:07 2017 Received: from list by lists.gnu.org with archive (Exim 4.71) id 1dmibb-00007S-2a for mharc-qemu-arm@gnu.org; Tue, 29 Aug 2017 11:39:07 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:49963) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dmibV-0008V7-Nn for qemu-arm@nongnu.org; Tue, 29 Aug 2017 11:39:05 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dmibU-0007cw-Us for qemu-arm@nongnu.org; Tue, 29 Aug 2017 11:39:01 -0400 Received: from mail-pf0-x229.google.com ([2607:f8b0:400e:c00::229]:34433) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1dmibU-0007cS-Ox for qemu-arm@nongnu.org; Tue, 29 Aug 2017 11:39:00 -0400 Received: by mail-pf0-x229.google.com with SMTP id l87so1450573pfj.1 for ; Tue, 29 Aug 2017 08:39:00 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=subject:to:cc:references:from:message-id:date:user-agent :mime-version:in-reply-to:content-language:content-transfer-encoding; bh=BupQuUJiOSTTbgIOk4J42UtplyPtwA3G5+nl7RYwaEU=; b=NucB+FdjGYQ5Mn/UEo5yMyN/FgqlYnkzzPhBZbsjWcrhpiUzpVVQlDDQw1KmnCtXzn MKm5ToA51EGGnuD0k1j4vTnTe91rBCyQ3wYUVpebNQ0JLwSZxQLNHmf3vlBgV1M4esSZ ZWHtkBjgcS3zEIaAamMa/ALJ1syFgmq704lQ8= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:subject:to:cc:references:from:message-id:date :user-agent:mime-version:in-reply-to:content-language :content-transfer-encoding; bh=BupQuUJiOSTTbgIOk4J42UtplyPtwA3G5+nl7RYwaEU=; b=W0a2S215uowUO4uTaH6ecYO3fio75OFR6IALYYy4wyhYUDVv5l+BArAfhEZBUJ8OIY WcwKPe1GsyouV2EExlFGyDHq/GuoO+GR/nLZ7Wli+Oue4TbN5UR2hqXC669jH6/PdGY9 SPW9Fve6BIUs7PyJluKb9uVnKLeFcKoz16K7tV4tz5oDoi5eDH04mTXfdgwKgM7yHTvZ FUGyx5H7wFdBOOvZctk3Ju8DvqqmOANcrbjztIBX7sbNVxD+Wh88rgl5rPvHGBMpEMA4 zRDVwwe67GKZgSN8jnUuWKMDe+8OFyZvFWf77n9VZ1EvgLzonQIj354DrSYJOtVMfirS ss2w== X-Gm-Message-State: AHYfb5gNMajcskDRUucvUVr32GweLEsDttLP6Mp9SCE2Z/gKwLByCFgN jNKLWmTKrbNDOvQK X-Received: by 10.98.1.74 with SMTP id 71mr769004pfb.126.1504021139834; Tue, 29 Aug 2017 08:38:59 -0700 (PDT) Received: from bigtime.twiddle.net (97-126-108-236.tukw.qwest.net. [97.126.108.236]) by smtp.gmail.com with ESMTPSA id n18sm5647143pgd.13.2017.08.29.08.38.58 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 29 Aug 2017 08:38:58 -0700 (PDT) To: Peter Maydell , qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: patches@linaro.org References: <1503414539-28762-1-git-send-email-peter.maydell@linaro.org> <1503414539-28762-8-git-send-email-peter.maydell@linaro.org> From: Richard Henderson Message-ID: <918b7d17-8a0a-1ff5-d31a-5ee09479ee2f@linaro.org> Date: Tue, 29 Aug 2017 08:38:57 -0700 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.2.1 MIME-Version: 1.0 In-Reply-To: <1503414539-28762-8-git-send-email-peter.maydell@linaro.org> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 7bit X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::229 Subject: Re: [Qemu-arm] [Qemu-devel] [PATCH 07/20] target/arm: Make PRIMASK register banked for v8M X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 29 Aug 2017 15:39:05 -0000 On 08/22/2017 08:08 AM, Peter Maydell wrote: > Make the PRIMASK register banked if v8M security extensions are enabled. > > Note that we do not yet implement the functionality of the new > AIRCR.PRIS bit (which allows the effect of the NS copy of PRIMASK to > be restricted). > > Signed-off-by: Peter Maydell > --- > target/arm/cpu.h | 2 +- > hw/intc/armv7m_nvic.c | 2 +- > target/arm/helper.c | 4 ++-- > target/arm/machine.c | 9 +++++++-- > 4 files changed, 11 insertions(+), 6 deletions(-) Reviewed-by: Richard Henderson r~ From MAILER-DAEMON Tue Aug 29 11:42:08 2017 Received: from list by lists.gnu.org with archive (Exim 4.71) id 1dmieW-0002jK-MJ for mharc-qemu-arm@gnu.org; Tue, 29 Aug 2017 11:42:08 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:51378) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dmieT-0002hJ-R7 for qemu-arm@nongnu.org; Tue, 29 Aug 2017 11:42:06 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dmieP-000137-41 for qemu-arm@nongnu.org; Tue, 29 Aug 2017 11:42:05 -0400 Received: from mail-pf0-x233.google.com ([2607:f8b0:400e:c00::233]:35808) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1dmieO-00012M-Tn for qemu-arm@nongnu.org; Tue, 29 Aug 2017 11:42:01 -0400 Received: by mail-pf0-x233.google.com with SMTP id g13so11317975pfm.2 for ; Tue, 29 Aug 2017 08:42:00 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=subject:to:cc:references:from:message-id:date:user-agent :mime-version:in-reply-to:content-language:content-transfer-encoding; bh=lT+jX1KJfRO/lAzVbolV34pyqGo0oHa7JuixH6tM2kk=; b=DN97c4ay1IdtvdZf8h2ZSCG5IxPhMM0CM2qBdFMMcfMibk4dG/NDo0fKSbIpY8tA0L J+LrtAHhKAlY620Ku9IxJGnpZtyNoO4zYP068fJ4HW0IBHjaY9L2kN8hiJ/5rMxfLzk4 icTKW2/F1qJRjinUQAogoINgxMqu5KYP4VzTI= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:subject:to:cc:references:from:message-id:date :user-agent:mime-version:in-reply-to:content-language :content-transfer-encoding; bh=lT+jX1KJfRO/lAzVbolV34pyqGo0oHa7JuixH6tM2kk=; b=hDzt3GIXZQWMVRFCi6zA9Qn6WqFGih0lMcuVU9uTYv6wpNFX87WNtVLXbfbXveB1nk s8836smzLd7Da4/mSatDQmpbHuYWBn2LGk42etZn9Lcl0M3QqHSs3k2HfTfQVYwp6aKO lXdmNWq0gV3qIhp8xaroop/f3GWBUdGlyMoQeE1wOlEeW9RCFdrvSh3xWeWC1ML0vjHP yNhdqg0MlVjv+Hw/Z4SLkluty1MGuFXrHzUcYcFIN7KADzDIErndAb5wT1bxMlJ14Dkg jV1NmtCGnA0Qk7hgnTf4yBb/zGkl/0ZOCSgwuwo9YniwWOL1XdO2VoDXNvy2Iie4zuZW dtXA== X-Gm-Message-State: AHYfb5jsVUBZyM2o25bFP0h/3xnZ7kcIo1UWFcty97qUYc8r22KCXicP 23btCQzUbA5PMkxa X-Received: by 10.84.194.131 with SMTP id h3mr1008854pld.100.1504021319642; Tue, 29 Aug 2017 08:41:59 -0700 (PDT) Received: from bigtime.twiddle.net (97-126-108-236.tukw.qwest.net. [97.126.108.236]) by smtp.gmail.com with ESMTPSA id i128sm5802754pfg.81.2017.08.29.08.41.58 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 29 Aug 2017 08:41:58 -0700 (PDT) To: Peter Maydell , qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: patches@linaro.org References: <1503414539-28762-1-git-send-email-peter.maydell@linaro.org> <1503414539-28762-9-git-send-email-peter.maydell@linaro.org> From: Richard Henderson Message-ID: <243eea50-7167-ba35-9481-9c919e446371@linaro.org> Date: Tue, 29 Aug 2017 08:41:56 -0700 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.2.1 MIME-Version: 1.0 In-Reply-To: <1503414539-28762-9-git-send-email-peter.maydell@linaro.org> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 7bit X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::233 Subject: Re: [Qemu-arm] [Qemu-devel] [PATCH 08/20] target/arm: Make FAULTMASK register banked for v8M X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 29 Aug 2017 15:42:07 -0000 On 08/22/2017 08:08 AM, Peter Maydell wrote: > Make the FAULTMASK register banked if v8M security extensions are enabled. > > Note that we do not yet implement the functionality of the new > AIRCR.PRIS bit (which allows the effect of the NS copy of FAULTMASK to > be restricted). > > This patch includes the code to determine for v8M which copy > of FAULTMASK should be updated on exception exit; further > changes will be required to the exception exit code in general > to support v8M, so this is just a small piece of that. > > The v8M ARM ARM introduces a notation where individual paragraphs > are labelled with R (for rule) or I (for information) followed > by a random group of subscript letters. In comments where we want > to refer to a particular part of the manual we use this convention, > which should be more stable across document revisions than using > section or page numbers. > > Signed-off-by: Peter Maydell > --- > target/arm/cpu.h | 14 ++++++++++++-- > hw/intc/armv7m_nvic.c | 9 ++++++++- > target/arm/helper.c | 20 ++++++++++++++++---- > target/arm/machine.c | 5 +++-- > 4 files changed, 39 insertions(+), 9 deletions(-) Reviewed-by: Richard Henderson r~ From MAILER-DAEMON Tue Aug 29 11:43:32 2017 Received: from list by lists.gnu.org with archive (Exim 4.71) id 1dmifs-0003aM-3e for mharc-qemu-arm@gnu.org; Tue, 29 Aug 2017 11:43:32 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:51771) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dmifp-0003Xq-3y for qemu-arm@nongnu.org; Tue, 29 Aug 2017 11:43:30 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dmifk-0001vH-7m for qemu-arm@nongnu.org; Tue, 29 Aug 2017 11:43:29 -0400 Received: from mail-pg0-x22a.google.com ([2607:f8b0:400e:c05::22a]:34387) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1dmifk-0001us-1s for qemu-arm@nongnu.org; Tue, 29 Aug 2017 11:43:24 -0400 Received: by mail-pg0-x22a.google.com with SMTP id y15so11941885pgc.1 for ; Tue, 29 Aug 2017 08:43:23 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=subject:to:cc:references:from:message-id:date:user-agent :mime-version:in-reply-to:content-language:content-transfer-encoding; bh=Uly2EKymgeQg3zhXWlb4QD5E3fgWMCgpk3TGokagzAs=; b=DGhaXIJp+FoteRTNSBMhGf7JqWdyTzKRCSZ19sIVf4huk8XvRYvQPMceXHcFQ3fy9v CWmX1+UIDn1p+4TnJoz5UXEjucSoSIFAOkd9uyEi6UgN8tZG8AAcMzJSKHG7sUWqrxMn bddQ/Zp7U/C/c58fxuI4wqxCuHQybqMKHhkaY= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:subject:to:cc:references:from:message-id:date :user-agent:mime-version:in-reply-to:content-language :content-transfer-encoding; bh=Uly2EKymgeQg3zhXWlb4QD5E3fgWMCgpk3TGokagzAs=; b=Lp9mbIcu0b5Egsta65HaETUpy46aMe+7DmpTuYruMA+j4d4PaQdn7nzdk5OLkpSN8L XzWDIcwjjpVXMWOxGnxFyKP7LwcTqzSBepR9Gg4GyXhRfLzorqmUmkCb3qAfLPuCOYSm 1OeKJTa3gFPEZFhUJX1LA+xVgeGRQMXoF44GW+t/yWbl8hqmVLCaWdsaW67rut7Lbamn xCKHFBAw+5+XMvmyK6vYIh3Ov4l+FEaUlWHTIyYiYUq2c3M3HlWZ1fHv16sKbCYQ2Smo PvtmoZZz80ISA/ik3LEQ3q9tL2m/PBvWwTK53yj4WaM3/7Ozfssv81+h+oicdTIaXzjc ZaCw== X-Gm-Message-State: AHYfb5iIlPwQs/qBtGs9dpYdblNUAoIXWjxfmwf+Z/F5YqH834N5OCkV S0jX/6VWjqy81Me6 X-Received: by 10.99.125.18 with SMTP id y18mr700642pgc.223.1504021403038; Tue, 29 Aug 2017 08:43:23 -0700 (PDT) Received: from bigtime.twiddle.net (97-126-108-236.tukw.qwest.net. [97.126.108.236]) by smtp.gmail.com with ESMTPSA id a21sm6120914pfj.89.2017.08.29.08.43.21 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 29 Aug 2017 08:43:22 -0700 (PDT) To: Peter Maydell , qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: patches@linaro.org References: <1503414539-28762-1-git-send-email-peter.maydell@linaro.org> <1503414539-28762-10-git-send-email-peter.maydell@linaro.org> From: Richard Henderson Message-ID: <66795cd3-db3d-4d6c-6012-0886d95c5352@linaro.org> Date: Tue, 29 Aug 2017 08:43:20 -0700 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.2.1 MIME-Version: 1.0 In-Reply-To: <1503414539-28762-10-git-send-email-peter.maydell@linaro.org> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 7bit X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::22a Subject: Re: [Qemu-arm] [Qemu-devel] [PATCH 09/20] target/arm: Make CONTROL register banked for v8M X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 29 Aug 2017 15:43:30 -0000 On 08/22/2017 08:08 AM, Peter Maydell wrote: > Make the CONTROL register banked if v8M security extensions are enabled. > > Signed-off-by: Peter Maydell > --- > target/arm/cpu.h | 5 +++-- > target/arm/helper.c | 21 +++++++++++---------- > target/arm/machine.c | 3 ++- > target/arm/translate.c | 2 +- > 4 files changed, 17 insertions(+), 14 deletions(-) Reviewed-by: Richard Henderson r~ From MAILER-DAEMON Tue Aug 29 12:00:24 2017 Received: from list by lists.gnu.org with archive (Exim 4.71) id 1dmiwB-0003tU-V3 for mharc-qemu-arm@gnu.org; Tue, 29 Aug 2017 12:00:24 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:57353) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dmiwA-0003sG-B9 for qemu-arm@nongnu.org; Tue, 29 Aug 2017 12:00:23 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dmiw4-0007Rf-OU for qemu-arm@nongnu.org; Tue, 29 Aug 2017 12:00:22 -0400 Received: from mail-pf0-x22e.google.com ([2607:f8b0:400e:c00::22e]:35944) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1dmiw4-0007QM-Ja for qemu-arm@nongnu.org; Tue, 29 Aug 2017 12:00:16 -0400 Received: by mail-pf0-x22e.google.com with SMTP id z87so11403707pfi.3 for ; Tue, 29 Aug 2017 09:00:16 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=subject:to:cc:references:from:message-id:date:user-agent :mime-version:in-reply-to:content-language:content-transfer-encoding; bh=K7+1rq8/s+I2NsIQD4gjg5EPOvjiD2MdJrw85QxbauI=; b=GsNiOt7gazJd5tyoO12YpufqEw9Y0mwZgrIerbvk+Qe7DJ9N8+rBKj8O1O7Ui0MIH9 EYdOIg9nUjpcaEkzQtAsjew3Xid8C8Yr8xua4jgfipp5lLotb1O0HOCV8FaodCPaEw11 KCiQQddmJun/pYG3rsLlGqFmXNY9OjjfFa29U= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:subject:to:cc:references:from:message-id:date :user-agent:mime-version:in-reply-to:content-language :content-transfer-encoding; bh=K7+1rq8/s+I2NsIQD4gjg5EPOvjiD2MdJrw85QxbauI=; b=EOsIOaC+QfMHtl2Qe1qE5w49HkRzGvRb4UVgIJ8FQ01KxIj4jCKwE2/o+5eyvETqib wTaIpk0VsqEXYsgLZDKeimDLtKiJflHsH5jC/ZARz7/SiXHJMBIwLwKxAUy6MXMLpRf2 7s8BBQSb7n9xFaWZW2PdAIDdl7qG0ndBQ5Oq1Ql0j/ZhLX/qeCbCyICKNrEK7MXsgnGd 0HoW45CBQuLmgzrO42htSoZJ27HXrqGAnsux+U2OGO2QeZI1EYFBBiWxWr2RUzRRF8ys YrwZkT6m73zAlMBNNcPZaR4G2w78QMM3tT02WeI0iqahp9s3L/p+S2OgVoAzBBkClIKR aLNA== X-Gm-Message-State: AHYfb5iqTaN0YcEJskW3aVCFkYJy5rRQaK1vwPF4BXOjFgIZINIoFB6h pJI7o/E6xBTnl43d X-Received: by 10.98.214.203 with SMTP id a72mr803097pfl.123.1504022415272; Tue, 29 Aug 2017 09:00:15 -0700 (PDT) Received: from bigtime.twiddle.net (97-126-108-236.tukw.qwest.net. [97.126.108.236]) by smtp.gmail.com with ESMTPSA id y124sm5448240pfy.116.2017.08.29.09.00.13 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 29 Aug 2017 09:00:13 -0700 (PDT) To: Peter Maydell , qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: patches@linaro.org References: <1503414539-28762-1-git-send-email-peter.maydell@linaro.org> <1503414539-28762-11-git-send-email-peter.maydell@linaro.org> From: Richard Henderson Message-ID: Date: Tue, 29 Aug 2017 09:00:12 -0700 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.2.1 MIME-Version: 1.0 In-Reply-To: <1503414539-28762-11-git-send-email-peter.maydell@linaro.org> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 7bit X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::22e Subject: Re: [Qemu-arm] [Qemu-devel] [PATCH 10/20] nvic: Add NS alias SCS region X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 29 Aug 2017 16:00:23 -0000 On 08/22/2017 08:08 AM, Peter Maydell wrote: > + regionlen = arm_feature(&s->cpu->env, ARM_FEATURE_V8) ? 0x21000 : 0x1000; > + memory_region_init(&s->container, OBJECT(s), "nvic", regionlen); > /* The system register region goes at the bottom of the priority > * stack as it covers the whole page. > */ > @@ -1185,6 +1242,13 @@ static void armv7m_nvic_realize(DeviceState *dev, Error **errp) > sysbus_mmio_get_region(systick_sbd, 0), > 1); > > + if (arm_feature(&s->cpu->env, ARM_FEATURE_V8)) { > + memory_region_init_io(&s->sysreg_ns_mem, OBJECT(s), > + &nvic_sysreg_ns_ops, s, > + "nvic_sysregs_ns", 0x1000); > + memory_region_add_subregion(&s->container, 0x20000, &s->sysreg_ns_mem); There's a whole in between the two regions, which you are leaving mapped. Why create a sub-region instead of two separate top-level regions for which you can leave the whole unmapped? r~ From MAILER-DAEMON Tue Aug 29 12:02:29 2017 Received: from list by lists.gnu.org with archive (Exim 4.71) id 1dmiyD-0005jy-9b for mharc-qemu-arm@gnu.org; Tue, 29 Aug 2017 12:02:29 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:58108) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dmiyA-0005hU-9b for qemu-arm@nongnu.org; Tue, 29 Aug 2017 12:02:27 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dmiy6-0000dE-Ea for qemu-arm@nongnu.org; Tue, 29 Aug 2017 12:02:26 -0400 Received: from mail-pg0-x22d.google.com ([2607:f8b0:400e:c05::22d]:36647) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1dmiy6-0000cf-8r for qemu-arm@nongnu.org; Tue, 29 Aug 2017 12:02:22 -0400 Received: by mail-pg0-x22d.google.com with SMTP id r133so12001802pgr.3 for ; Tue, 29 Aug 2017 09:02:22 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=subject:to:cc:references:from:message-id:date:user-agent :mime-version:in-reply-to:content-language:content-transfer-encoding; bh=8UBmNmw5bz0k4tqdgk2sZeW+QEoyzT2JUfup9LkW6Jk=; b=ZWBZ2LXex5VIpNe/0zaVUsZo+JLTHa6/gBrNKZJQYcUyORnrLqFsofDAEK2Gf512tR JCrL6DJS2X7TV5/qLRy/g9Iz3J5XEb/kVr8CG8kS8H67FOuMOQWYfTiwjPId94LBD6GY 7ZG/RSizHVyEyQa3IjNkS1vUB0sD24K3pIPg4= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:subject:to:cc:references:from:message-id:date :user-agent:mime-version:in-reply-to:content-language :content-transfer-encoding; bh=8UBmNmw5bz0k4tqdgk2sZeW+QEoyzT2JUfup9LkW6Jk=; b=WU3smHADBdon5d9VVGbHTGn8xlEDfCTWuC4cs6Y/TZSSefixAzGzaY4cx7tivzu+I9 3+sU15ZKCG5OceHHkIDS6ATYuCxj+j23Pyh4uQX6wCykZj2fCiSDuPOVNFa1/NojIoKT okvGHpWMs9UGMb4YUCXmCC0LZtcxmcfX2KHcHV4feznVI6ChwU69dSn4PD+dE8ViCBBj AVCVuY9psmgSOVgn1Kjx/AGBdDYgPuqdVUwF+v36Yh/EE0xvEd5PdVs3EqP20eYeA+wh 4v3XAWWY8vdbd0KyU5Zrre7WjTzYYC4NsRSwmi/nnDtaLK38aXpP6ylXeGD+fdFYPxGC PUhQ== X-Gm-Message-State: AHYfb5i6iXvCZqVZNPkWikj9hVY3PhIETrsa+TR9AYRJs2fBz2rLdqLh D1YuOW/XF+ToEeeK X-Received: by 10.84.215.206 with SMTP id g14mr997730plj.345.1504022540962; Tue, 29 Aug 2017 09:02:20 -0700 (PDT) Received: from bigtime.twiddle.net (97-126-108-236.tukw.qwest.net. [97.126.108.236]) by smtp.gmail.com with ESMTPSA id 73sm6640788pfu.3.2017.08.29.09.02.19 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 29 Aug 2017 09:02:19 -0700 (PDT) To: Peter Maydell , qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: patches@linaro.org References: <1503414539-28762-1-git-send-email-peter.maydell@linaro.org> <1503414539-28762-12-git-send-email-peter.maydell@linaro.org> From: Richard Henderson Message-ID: <4f8b56f1-7bd3-6485-37f4-02de5af5f90c@linaro.org> Date: Tue, 29 Aug 2017 09:02:18 -0700 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.2.1 MIME-Version: 1.0 In-Reply-To: <1503414539-28762-12-git-send-email-peter.maydell@linaro.org> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 7bit X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::22d Subject: Re: [Qemu-arm] [Qemu-devel] [PATCH 11/20] target/arm: Make VTOR register banked for v8M X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 29 Aug 2017 16:02:27 -0000 On 08/22/2017 08:08 AM, Peter Maydell wrote: > Make the VTOR register banked if v8M security extensions are enabled. > > Signed-off-by: Peter Maydell > --- > target/arm/cpu.h | 2 +- > hw/intc/armv7m_nvic.c | 13 +++++++------ > target/arm/helper.c | 2 +- > target/arm/machine.c | 3 ++- > 4 files changed, 11 insertions(+), 9 deletions(-) Reviewed-by: Richard Henderson r~ From MAILER-DAEMON Tue Aug 29 12:03:06 2017 Received: from list by lists.gnu.org with archive (Exim 4.71) id 1dmiyo-0006DQ-2G for mharc-qemu-arm@gnu.org; Tue, 29 Aug 2017 12:03:06 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:58697) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dmiyh-00067x-5r for qemu-arm@nongnu.org; Tue, 29 Aug 2017 12:03:04 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dmiye-0001ER-2k for qemu-arm@nongnu.org; Tue, 29 Aug 2017 12:02:59 -0400 Received: from mail-pf0-x236.google.com ([2607:f8b0:400e:c00::236]:36266) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1dmiyd-0001DX-Sg for qemu-arm@nongnu.org; Tue, 29 Aug 2017 12:02:55 -0400 Received: by mail-pf0-x236.google.com with SMTP id z87so11426224pfi.3 for ; Tue, 29 Aug 2017 09:02:55 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=subject:to:cc:references:from:message-id:date:user-agent :mime-version:in-reply-to:content-language:content-transfer-encoding; bh=2YSs96hyE/cSGrv8tdW7tSR0G1tV2O/iJpjE6YSPDqE=; b=cGHSMXw/oqNc2J1FSF2CUrm+uPTPPBWeC8WQW2tjn64jj/mvtoTAWgE51J9uzXTSRt aEyG8n7mcRy0mhZoPNkmEKFNzVVDe6WAeD3IN0gLdc0THu1tEr+WMWQNolL2PTgAfr3O q8nLbZfU/xJBe0KUbPxNdiqBpH4P+m+8F+nSQ= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:subject:to:cc:references:from:message-id:date :user-agent:mime-version:in-reply-to:content-language :content-transfer-encoding; bh=2YSs96hyE/cSGrv8tdW7tSR0G1tV2O/iJpjE6YSPDqE=; b=cCoR5r77E5jq4ITzot7slrNqMRj4zqlL13BNZOd8Hu5WDOEhDLkEEC2JlLO1mfH1YU 0ZLGlcHckUT92gXkckisSRfV1IxLtlAZN12YCMSoHOsh2dOonLFuQNrpxxNH7e3XTOBq RJK6mD7gVNrEzxJ6COwOQSWXnVaI5WZ+xS3xUG9gVTqjTW9LIOqsYW9ijOP+QLFis3mu TfXIhp4zdx1Yi1T9+FCx1AWbZNU12x245ekxCos/+nXFFbZqDWvB9t3dNHyYHxVEHgnN zuyviZo49TNC0xRbtdU2s1g/OW+IN9TmFzhDgL6CRJiyweDOYUwT7Upm2RpxU2uz7sI0 AlUg== X-Gm-Message-State: AHYfb5jmPrRLMaQkizHD48U+AIKoUBb7238/mxYLg4AAa1G2P+IdVCIe 1abxPsBBAtFOvJz0 X-Received: by 10.84.216.92 with SMTP id f28mr996104plj.255.1504022574778; Tue, 29 Aug 2017 09:02:54 -0700 (PDT) Received: from bigtime.twiddle.net (97-126-108-236.tukw.qwest.net. [97.126.108.236]) by smtp.gmail.com with ESMTPSA id p5sm3726339pgn.91.2017.08.29.09.02.53 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 29 Aug 2017 09:02:53 -0700 (PDT) To: Peter Maydell , qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: patches@linaro.org References: <1503414539-28762-1-git-send-email-peter.maydell@linaro.org> <1503414539-28762-13-git-send-email-peter.maydell@linaro.org> From: Richard Henderson Message-ID: Date: Tue, 29 Aug 2017 09:02:51 -0700 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.2.1 MIME-Version: 1.0 In-Reply-To: <1503414539-28762-13-git-send-email-peter.maydell@linaro.org> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 7bit X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::236 Subject: Re: [Qemu-arm] [Qemu-devel] [PATCH 12/20] target/arm: Make MPU_MAIR0, MPU_MAIR1 registers banked for v8M X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 29 Aug 2017 16:03:04 -0000 On 08/22/2017 08:08 AM, Peter Maydell wrote: > Make the MPU registers MPU_MAIR0 and MPU_MAIR1 banked if v8M security > extensions are enabled. > > Signed-off-by: Peter Maydell > --- > target/arm/cpu.h | 4 ++-- > hw/intc/armv7m_nvic.c | 8 ++++---- > target/arm/cpu.c | 4 ++-- > target/arm/machine.c | 6 ++++-- > 4 files changed, 12 insertions(+), 10 deletions(-) Reviewed-by: Richard Henderson r~ From MAILER-DAEMON Tue Aug 29 12:04:31 2017 Received: from list by lists.gnu.org with archive (Exim 4.71) id 1dmj0A-0007D8-O4 for mharc-qemu-arm@gnu.org; Tue, 29 Aug 2017 12:04:30 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:59338) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dmj08-0007Az-Ch for qemu-arm@nongnu.org; Tue, 29 Aug 2017 12:04:29 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dmj05-00026Q-7k for qemu-arm@nongnu.org; Tue, 29 Aug 2017 12:04:28 -0400 Received: from mail-pg0-x229.google.com ([2607:f8b0:400e:c05::229]:35869) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1dmj05-000268-2l for qemu-arm@nongnu.org; Tue, 29 Aug 2017 12:04:25 -0400 Received: by mail-pg0-x229.google.com with SMTP id r133so12018625pgr.3 for ; Tue, 29 Aug 2017 09:04:24 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=subject:to:cc:references:from:message-id:date:user-agent :mime-version:in-reply-to:content-language:content-transfer-encoding; bh=1sJhxCObsGVu9KyQC3vD3oOb2M87yex/ftk005s7anM=; b=SVAVKzZ2u1Qn/q6k0/VPmYML6C2ga2JfmNxTnI7VAzLkODgk7FrSHyz1ReeieDfh3s SrtyoINtAiZ0JK1DapkT7sUTh++nVu+40rB4NFJ+myxc6i7bsWiATkU9yvM7zVEtM3ZQ O9w9adx4bi7zJrkVz4KdULJvK7RkfJnG2c+Do= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:subject:to:cc:references:from:message-id:date :user-agent:mime-version:in-reply-to:content-language :content-transfer-encoding; bh=1sJhxCObsGVu9KyQC3vD3oOb2M87yex/ftk005s7anM=; b=k9k7wezLqZfnJ2RDWafa5d35sn6QV7jfWL48xlJYzTCbMx8qdJka6gSMOM1S9M6/3G mROAIdpn7DMfDT7aRymVREqv27eCDUifVVYJIhRq/saJcqx1gC0eGJlETzEW1E+RB0WF ZlKAy246mHXbQa2tVzr0FtEsaBqf5z479bh48fg33x88WcMiGHAnsfOcBoy54/p7OgU0 +qgslsvAFsYuwnAe/ATgs2TGRGs5SiR82EqhWqfqD1xvvZsWOIzSCribx2Ht0+yRe9he 7MXZSz1c8NKYstY8t4oZdpPmUQ+RaNQJfWZhFi2WebV74KEcapofRFtLtimhD9FrR+2K EeLA== X-Gm-Message-State: AHYfb5jNKSvxmtPvnXGpfc/TBAiJMVQe8qBF2scU86yV4rTYg1R7uTrL thSTEtnXo/XjhfNpS86yiA== X-Received: by 10.84.215.149 with SMTP id l21mr1045606pli.308.1504022664055; Tue, 29 Aug 2017 09:04:24 -0700 (PDT) Received: from bigtime.twiddle.net (97-126-108-236.tukw.qwest.net. [97.126.108.236]) by smtp.gmail.com with ESMTPSA id 186sm4858480pgi.11.2017.08.29.09.04.22 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 29 Aug 2017 09:04:22 -0700 (PDT) To: Peter Maydell , qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: patches@linaro.org References: <1503414539-28762-1-git-send-email-peter.maydell@linaro.org> <1503414539-28762-14-git-send-email-peter.maydell@linaro.org> From: Richard Henderson Message-ID: <0777d69a-88cf-4441-df0a-d7bb30571e80@linaro.org> Date: Tue, 29 Aug 2017 09:04:21 -0700 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.2.1 MIME-Version: 1.0 In-Reply-To: <1503414539-28762-14-git-send-email-peter.maydell@linaro.org> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 7bit X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::229 Subject: Re: [Qemu-arm] [Qemu-devel] [PATCH 13/20] target/arm: Make MPU_RBAR, MPU_RLAR banked for v8M X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 29 Aug 2017 16:04:29 -0000 On 08/22/2017 08:08 AM, Peter Maydell wrote: > Make the MPU registers MPU_MAIR0 and MPU_MAIR1 banked if v8M security > extensions are enabled. > > We can freely add more items to vmstate_m_security without > breaking migration compatibility, because no CPU currently > has the ARM_FEATURE_M_SECURITY bit enabled and so this > subsection is not yet used by anything. > > Signed-off-by: Peter Maydell > --- > target/arm/cpu.h | 4 ++-- > hw/intc/armv7m_nvic.c | 8 ++++---- > target/arm/cpu.c | 26 ++++++++++++++++++++------ > target/arm/helper.c | 11 ++++++----- > target/arm/machine.c | 12 ++++++++---- > 5 files changed, 40 insertions(+), 21 deletions(-) Reviewed-by: Richard Henderson r~ From MAILER-DAEMON Tue Aug 29 12:05:38 2017 Received: from list by lists.gnu.org with archive (Exim 4.71) id 1dmj1G-0008Ua-DT for mharc-qemu-arm@gnu.org; Tue, 29 Aug 2017 12:05:38 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:59614) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dmj1D-0008QG-NE for qemu-arm@nongnu.org; Tue, 29 Aug 2017 12:05:37 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dmj1A-0002Yp-HT for qemu-arm@nongnu.org; Tue, 29 Aug 2017 12:05:35 -0400 Received: from mail-pf0-x233.google.com ([2607:f8b0:400e:c00::233]:36571) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1dmj1A-0002YW-AQ for qemu-arm@nongnu.org; Tue, 29 Aug 2017 12:05:32 -0400 Received: by mail-pf0-x233.google.com with SMTP id z87so11446963pfi.3 for ; Tue, 29 Aug 2017 09:05:32 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=subject:to:cc:references:from:message-id:date:user-agent :mime-version:in-reply-to:content-language:content-transfer-encoding; bh=eD5CUfsaOy3J+0yQ/JMlWwZA49mkbtVU1AlJUFdjjd8=; b=RL6MyOu2x7hV6X4uAvctn3tiga+OlnrB/4lyGL+OyKheSR+f1ze+HC8vspa2g5U08b S/GAjA2yRF0/3v1BPuosXJQbsCnQeUmriHc1CM2szsE9Ewr18poyAyCiZNKaWo3JvAaJ P/uK8ribXSaB6aney1K10E68cwHQV0mq1qf+Y= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:subject:to:cc:references:from:message-id:date :user-agent:mime-version:in-reply-to:content-language :content-transfer-encoding; bh=eD5CUfsaOy3J+0yQ/JMlWwZA49mkbtVU1AlJUFdjjd8=; b=XUhbemDPGSNVPRGIlFpYIX0DhAgzIhRyTSSYECbm5/0sG/ttY1jyM57HH+zYCYuN+f ZWtEYy4urHCajPczyD/kh2CjGz5MhyPPtw8tnA38JgTuC30uJCXiGI2yiL+7hyuQHa8A 7OYP+h6FL++2ux/t3UJpGQfpiUbjyjhnNZPFE+w2o1rREmGiNiiocIVwEKHLdDcX4jiU YavdLDENiLRtIpKzHR2vtSHjwN1tzDv2ll1Rt5gPIg3vXMKCVreX5UJig+SEQ8LTxiEe AXPDocIxCiBZm7jlGM1/dCQjJmF+K0NGw1dN/lrHJ1T2L3lZETlgegYou6Z3klBNRTfk lCAQ== X-Gm-Message-State: AHYfb5gyPhxdlEr+XeYdCeKXL+4euZrmguQbcIyZJZbQmbu1PfjnVOZe k9c3dvufzN1H60vi X-Received: by 10.98.223.85 with SMTP id u82mr804357pfg.347.1504022731374; Tue, 29 Aug 2017 09:05:31 -0700 (PDT) Received: from bigtime.twiddle.net (97-126-108-236.tukw.qwest.net. [97.126.108.236]) by smtp.gmail.com with ESMTPSA id t190sm659540pgb.76.2017.08.29.09.05.29 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 29 Aug 2017 09:05:29 -0700 (PDT) To: Peter Maydell , qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: patches@linaro.org References: <1503414539-28762-1-git-send-email-peter.maydell@linaro.org> <1503414539-28762-15-git-send-email-peter.maydell@linaro.org> From: Richard Henderson Message-ID: Date: Tue, 29 Aug 2017 09:05:27 -0700 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.2.1 MIME-Version: 1.0 In-Reply-To: <1503414539-28762-15-git-send-email-peter.maydell@linaro.org> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 7bit X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::233 Subject: Re: [Qemu-arm] [Qemu-devel] [PATCH 14/20] target/arm: Make MPU_RNR register banked for v8M X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 29 Aug 2017 16:05:37 -0000 On 08/22/2017 08:08 AM, Peter Maydell wrote: > + env->pmsav7.rnr[M_REG_NS] = 0; > + env->pmsav7.rnr[M_REG_S] = 0; > memset(env->pmsav8.mair0, 0, sizeof(env->pmsav8.mair0)); > memset(env->pmsav8.mair1, 0, sizeof(env->pmsav8.mair1)); Why some memset and some by-element? Otherwise, Reviewed-by: Richard Henderson r~ From MAILER-DAEMON Tue Aug 29 12:06:20 2017 Received: from list by lists.gnu.org with archive (Exim 4.71) id 1dmj1w-0000dG-Im for mharc-qemu-arm@gnu.org; Tue, 29 Aug 2017 12:06:20 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:59845) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dmj1q-0000WL-In for qemu-arm@nongnu.org; Tue, 29 Aug 2017 12:06:19 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dmj1n-00033c-CA for qemu-arm@nongnu.org; Tue, 29 Aug 2017 12:06:14 -0400 Received: from mail-pg0-x233.google.com ([2607:f8b0:400e:c05::233]:37298) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1dmj1n-00032o-6K for qemu-arm@nongnu.org; Tue, 29 Aug 2017 12:06:11 -0400 Received: by mail-pg0-x233.google.com with SMTP id 83so11999344pgb.4 for ; Tue, 29 Aug 2017 09:06:11 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=subject:to:cc:references:from:message-id:date:user-agent :mime-version:in-reply-to:content-language:content-transfer-encoding; bh=RGafltpbcJxiBtrqdJ/wjqx1rIAr+DGZphoUMM+hF5g=; b=Ax0pFmTOipzR+hFt0GkI551VhnLyKnt22l+o2gpVddAn2AVGK9RLAATIs+8jN0puIZ 4DpqtQCZ7wHMY0NJ3HHqMosBBcxwDpCUHfcet7+HtiU5cn0RXYxOVNE9/v7jr7Vl37mW XSvzAWY+Uo7glIPZ8KZylXWbqSIWwa/mfNtg8= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:subject:to:cc:references:from:message-id:date :user-agent:mime-version:in-reply-to:content-language :content-transfer-encoding; bh=RGafltpbcJxiBtrqdJ/wjqx1rIAr+DGZphoUMM+hF5g=; b=XQ0Ej+Y0NC4liSOu2bxYJ5zpO0we1zmJSeArx3HpzW8YOsZNj8LiA/4ESWzJiFvAIA hhVZ7Upo5pwYFxkPNHS5zO0QKrmFdBmSputCWkqYUy8+3jIiiH4UiydV02aoC+UHZ+Tw GJw/D99ZgTNeeAD6SgZ7lG0aT0BhG/saSDnDBLFNzKRe+RhqP2mpGg+xtdF3RZBgbxfw pG7zjW2GM1rCL1Hpb4eT2y+NKDiCwfOjh1jh8nVwa9d7KA+DZl9iupiUHiD8Fy/zxrLT gOdn+A9mI6TYe/RWD1kGKTdn8Ficb6KbMqlkXVVRihTo9g3mnKXS1H8/D9lHUNxdUPzr SNFQ== X-Gm-Message-State: AHYfb5iKePy6u3NejZQecEqSiHOHCmbGrmpatZCo4H9k7nB5whmHJc7o DhsYO7w9xVFEMNh/ X-Received: by 10.98.82.66 with SMTP id g63mr798967pfb.271.1504022770168; Tue, 29 Aug 2017 09:06:10 -0700 (PDT) Received: from bigtime.twiddle.net (97-126-108-236.tukw.qwest.net. [97.126.108.236]) by smtp.gmail.com with ESMTPSA id 13sm6016186pfm.114.2017.08.29.09.06.08 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 29 Aug 2017 09:06:09 -0700 (PDT) To: Peter Maydell , qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: patches@linaro.org References: <1503414539-28762-1-git-send-email-peter.maydell@linaro.org> <1503414539-28762-16-git-send-email-peter.maydell@linaro.org> From: Richard Henderson Message-ID: <2fb5131c-e4a5-3700-4fad-f4fbfb0a23d8@linaro.org> Date: Tue, 29 Aug 2017 09:06:07 -0700 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.2.1 MIME-Version: 1.0 In-Reply-To: <1503414539-28762-16-git-send-email-peter.maydell@linaro.org> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 7bit X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::233 Subject: Re: [Qemu-arm] [Qemu-devel] [PATCH 15/20] target/arm: Make MPU_CTRL register banked for v8M X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 29 Aug 2017 16:06:19 -0000 On 08/22/2017 08:08 AM, Peter Maydell wrote: > Make the MPU_CTRL register banked if v8M security extensions are > enabled. > > Signed-off-by: Peter Maydell > --- > target/arm/cpu.h | 2 +- > hw/intc/armv7m_nvic.c | 9 +++++---- > target/arm/helper.c | 5 +++-- > target/arm/machine.c | 3 ++- > 4 files changed, 11 insertions(+), 8 deletions(-) Reviewed-by: Richard Henderson r~ From MAILER-DAEMON Tue Aug 29 12:07:10 2017 Received: from list by lists.gnu.org with archive (Exim 4.71) id 1dmj2k-0001CX-LQ for mharc-qemu-arm@gnu.org; Tue, 29 Aug 2017 12:07:10 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:60131) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dmj2i-0001AL-Cn for qemu-arm@nongnu.org; Tue, 29 Aug 2017 12:07:09 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dmj2h-0003gF-I5 for qemu-arm@nongnu.org; Tue, 29 Aug 2017 12:07:08 -0400 Received: from mail-wr0-x230.google.com ([2a00:1450:400c:c0c::230]:36149) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1dmj2h-0003fp-Cl for qemu-arm@nongnu.org; Tue, 29 Aug 2017 12:07:07 -0400 Received: by mail-wr0-x230.google.com with SMTP id p14so11664609wrg.3 for ; Tue, 29 Aug 2017 09:07:07 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:in-reply-to:references:from:date:message-id:subject:to :cc; bh=nAOBTxhaH7b2dqbDJpVQHxqc6V4w8QsmxubnNal6448=; b=JiS8AqH9tKgkeuBdV/UFS0MD0by4C65dUs6NwzOGdRI/hbghiJWKFgy4h5ZcDzMz9o jk0/wYfbix02UyUqiLfIX0lRBrfPOPde0P8hxzy01eCak36VtWeXdTGfv0NnA3DbDnrs jpEUaD64mQJDMEz+MPRDF8Mxib7D717PD8bao= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:in-reply-to:references:from:date :message-id:subject:to:cc; bh=nAOBTxhaH7b2dqbDJpVQHxqc6V4w8QsmxubnNal6448=; b=EF7eRXq28xqiy1h1FOMqPJ7Ifgw3AgPIccnjN4dQYXob3tg7/rBjiJ57VbxZUWMQ1k ciILa5HBTS6CowKPol2IsaL2327HwTBX6nVyEl9Sy2nI3bPVRg1GFBOccoWnqSMWNJi0 ppuJTqbYQO8GN84cpvzl6ShnmVlAIWZbcgCra1pRZfpTb+2x3rXkefnkOELn5uTXNiQ6 xBgmFPlonIMqLbzpwAF31IVG/qOsfTnlILmiO5JS3JJC7uLTK3XRQ5DUdD9b3wQKFJ8/ ckp/JUSdbfUtVphnghqXzHdNgoaBwMXMQs0aBF6x+GIrxRq0rMaelXhXi3LeZlFzttsN x+zQ== X-Gm-Message-State: AHYfb5hwMeTnY2v6peh4jBBfmZVHVj4YnVgZdDBXDyVY6IzPvug6vvkO SO1QOCf5iIAhR8QwmAq/mNiyJattp6Vg X-Received: by 10.223.184.102 with SMTP id u35mr531547wrf.196.1504022826383; Tue, 29 Aug 2017 09:07:06 -0700 (PDT) MIME-Version: 1.0 Received: by 10.223.134.54 with HTTP; Tue, 29 Aug 2017 09:06:45 -0700 (PDT) In-Reply-To: References: <1503414539-28762-1-git-send-email-peter.maydell@linaro.org> <1503414539-28762-15-git-send-email-peter.maydell@linaro.org> From: Peter Maydell Date: Tue, 29 Aug 2017 17:06:45 +0100 Message-ID: To: Richard Henderson Cc: qemu-arm , QEMU Developers , "patches@linaro.org" Content-Type: text/plain; charset="UTF-8" X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:400c:c0c::230 Subject: Re: [Qemu-arm] [Qemu-devel] [PATCH 14/20] target/arm: Make MPU_RNR register banked for v8M X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 29 Aug 2017 16:07:09 -0000 On 29 August 2017 at 17:05, Richard Henderson wrote: > On 08/22/2017 08:08 AM, Peter Maydell wrote: >> + env->pmsav7.rnr[M_REG_NS] = 0; >> + env->pmsav7.rnr[M_REG_S] = 0; >> memset(env->pmsav8.mair0, 0, sizeof(env->pmsav8.mair0)); >> memset(env->pmsav8.mair1, 0, sizeof(env->pmsav8.mair1)); > > Why some memset and some by-element? Roughly, memset where I would otherwise have to write a for loop (ie where there's more than 2 elements). thanks -- PMM From MAILER-DAEMON Tue Aug 29 12:08:56 2017 Received: from list by lists.gnu.org with archive (Exim 4.71) id 1dmj4R-0002VI-MF for mharc-qemu-arm@gnu.org; Tue, 29 Aug 2017 12:08:56 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:60666) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dmj4M-0002Sq-QN for qemu-arm@nongnu.org; Tue, 29 Aug 2017 12:08:52 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dmj4M-0004JO-1B for qemu-arm@nongnu.org; Tue, 29 Aug 2017 12:08:50 -0400 Received: from mail-pg0-x22e.google.com ([2607:f8b0:400e:c05::22e]:33324) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1dmj4L-0004J0-RY for qemu-arm@nongnu.org; Tue, 29 Aug 2017 12:08:49 -0400 Received: by mail-pg0-x22e.google.com with SMTP id t3so12141564pgt.0 for ; Tue, 29 Aug 2017 09:08:49 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=subject:to:cc:references:from:message-id:date:user-agent :mime-version:in-reply-to:content-language:content-transfer-encoding; bh=3O5WB6Sbl085S5/uhB7w/vp+BUovSXHq/kTXFlAnPjM=; b=GM78ayJ3GRZqF/ddXzm+MPg3tUUtcHedGgpukvWakPi8Tn/oBlahRZTuMAgzusfk3J B0PE7HoUed5vm73THtFzmHxXvLp1BTTQQZCwQcEUxLsG1V3brOurfn9tECHZ+fvw+Jzf J7/kLCtppy9jM+Gs0ynlLGDFgxOZ8duKOzmoA= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:subject:to:cc:references:from:message-id:date :user-agent:mime-version:in-reply-to:content-language :content-transfer-encoding; bh=3O5WB6Sbl085S5/uhB7w/vp+BUovSXHq/kTXFlAnPjM=; b=qcEEm4d7b8Xn1Rk+woIYRgVO175w21AsNGrttt3Ztn1lG382lugwUt0My7pIDUljdn N8JIqTtkGujbtEV5FhnfoAfYY6nd0HF0OMHaNORjCRSh3cQNQahzf7Bcwdg3CnjYtmLg wK4eZDQm1Mb9HIUH5tQcUIQnZHojTqGyZUm1D7UBmFe4li5W8ALlAIUEuE3Jy6jOzFPJ QQcF6JRikTPf52Mr6yvPo6J7LMpnzUVi/XcoGpu4PLVHisgvwfvEAaEt1K6IKQ6rswCg dM3JLYyHjhSvjli8FftAaGHUrTs7KLEXxdKyzz1G7ckl3ZqmKAJSc1NJFDdPwD2qxXon tjGQ== X-Gm-Message-State: AHYfb5jh1Q3Dz1f98dhHTFjywl49wg72IEgXhriWhIrcvbR71vXPLxLi jVbwj73tr/xT6YDB X-Received: by 10.98.35.89 with SMTP id j86mr862770pfj.232.1504022928993; Tue, 29 Aug 2017 09:08:48 -0700 (PDT) Received: from bigtime.twiddle.net (97-126-108-236.tukw.qwest.net. [97.126.108.236]) by smtp.gmail.com with ESMTPSA id c9sm5595941pfe.155.2017.08.29.09.08.47 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 29 Aug 2017 09:08:48 -0700 (PDT) To: Peter Maydell , qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: patches@linaro.org References: <1503414539-28762-1-git-send-email-peter.maydell@linaro.org> <1503414539-28762-17-git-send-email-peter.maydell@linaro.org> From: Richard Henderson Message-ID: <93e924b9-e8db-124b-8a17-a16f6abf5e0a@linaro.org> Date: Tue, 29 Aug 2017 09:08:46 -0700 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.2.1 MIME-Version: 1.0 In-Reply-To: <1503414539-28762-17-git-send-email-peter.maydell@linaro.org> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 7bit X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::22e Subject: Re: [Qemu-arm] [Qemu-devel] [PATCH 16/20] target/arm: Make CCR register banked for v8M X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 29 Aug 2017 16:08:53 -0000 On 08/22/2017 08:08 AM, Peter Maydell wrote: > + if (attrs.secure) { > + /* the BFHFNMIGN bit is not banked; keep that in the NS copy */ > + int new_bfhnmign = !!(value & R_V7M_CCR_BFHFNMIGN_MASK); > + > + cpu->env.v7m.ccr[M_REG_NS] = deposit32(cpu->env.v7m.ccr[M_REG_NS], > + R_V7M_CCR_BFHFNMIGN_SHIFT, > + R_V7M_CCR_BFHFNMIGN_LENGTH, > + new_bfhnmign); > + value &= ~R_V7M_CCR_BFHFNMIGN_MASK; > + } No need to extract and then redeposit, just use the mask. cpu->env.v7m.ccr[M_REG_NS] = (cpu->env.v7m.ccr[M_REG_NS] & ~R_V7M_CCR_BFHFNMIGN_MASK) | (value & R_V7M_CCR_BFHFNMIGN_MASK); r~ From MAILER-DAEMON Tue Aug 29 12:09:39 2017 Received: from list by lists.gnu.org with archive (Exim 4.71) id 1dmj59-00033i-6d for mharc-qemu-arm@gnu.org; Tue, 29 Aug 2017 12:09:39 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:32969) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dmj54-0002zB-5w for qemu-arm@nongnu.org; Tue, 29 Aug 2017 12:09:37 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dmj51-0004ey-0A for qemu-arm@nongnu.org; Tue, 29 Aug 2017 12:09:34 -0400 Received: from mail-pg0-x229.google.com ([2607:f8b0:400e:c05::229]:33395) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1dmj50-0004eH-QW for qemu-arm@nongnu.org; Tue, 29 Aug 2017 12:09:30 -0400 Received: by mail-pg0-x229.google.com with SMTP id t3so12146575pgt.0 for ; Tue, 29 Aug 2017 09:09:30 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=subject:to:cc:references:from:message-id:date:user-agent :mime-version:in-reply-to:content-language:content-transfer-encoding; bh=wt+/ztlafTzzpElGd3ld+0VrtV1ou/3/zbXaRkFOZgw=; b=C8VBFdo7MQtqW2OpNJSsiMmGCoZcCIBcxax0zhP/9E9PrwQxPnXsguq939aK936/0s ihW0zs9DOhZadIk0dYT9IEj2m5N4WFsFzW37s+ueYd65z1B7YVhazLluunbVFW1Qzrc2 SV7AQUUvpZ4qCpugCo3mBKGyOtVyOrjiumpno= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:subject:to:cc:references:from:message-id:date :user-agent:mime-version:in-reply-to:content-language :content-transfer-encoding; bh=wt+/ztlafTzzpElGd3ld+0VrtV1ou/3/zbXaRkFOZgw=; b=TjKOVBEa4DIY6xJE7pxA/BMGb6eI4yKDApow21D1jm3q0NzP8+5I+gDffm9SIY1crN dJ/5kjosOK5EPQt+3nBM8W8kzk/GnR/FbwxGtaiKtmqhCtItUR++PXYAaRA4lSNJUTvR +FNq/8/mEARQKbv6MTyRDmGMA7m5Bh0389f5w6+wUEWLHnnBHvN1JAshG9Vf1c7KO0eg 9dRrmadSDV4BMXhKbpOe8K+jUSFFUCpMkqg/EL1cxYkdThrmb1L7FmCuuhEeo8hauUAj Zja7K97JxFBq4VcpGo473gOgyIMN6Fyonh/YP/DxPeK4UfGUwkTJlxsqZwLriX2iXBER O+FA== X-Gm-Message-State: AHYfb5jXshmwMI6A3041U1CHHdZJv5mEJ9oD2iJEZXqLGlv4ZPIUVrWG pgeYS2REEt53SCvQgVLiHQ== X-Received: by 10.99.112.20 with SMTP id l20mr812178pgc.86.1504022970048; Tue, 29 Aug 2017 09:09:30 -0700 (PDT) Received: from bigtime.twiddle.net (97-126-108-236.tukw.qwest.net. [97.126.108.236]) by smtp.gmail.com with ESMTPSA id v75sm6506096pfi.134.2017.08.29.09.09.28 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 29 Aug 2017 09:09:28 -0700 (PDT) To: Peter Maydell Cc: qemu-arm , QEMU Developers , "patches@linaro.org" References: <1503414539-28762-1-git-send-email-peter.maydell@linaro.org> <1503414539-28762-15-git-send-email-peter.maydell@linaro.org> From: Richard Henderson Message-ID: Date: Tue, 29 Aug 2017 09:09:27 -0700 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.2.1 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 7bit X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::229 Subject: Re: [Qemu-arm] [Qemu-devel] [PATCH 14/20] target/arm: Make MPU_RNR register banked for v8M X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 29 Aug 2017 16:09:38 -0000 On 08/29/2017 09:06 AM, Peter Maydell wrote: > On 29 August 2017 at 17:05, Richard Henderson > wrote: >> On 08/22/2017 08:08 AM, Peter Maydell wrote: >>> + env->pmsav7.rnr[M_REG_NS] = 0; >>> + env->pmsav7.rnr[M_REG_S] = 0; >>> memset(env->pmsav8.mair0, 0, sizeof(env->pmsav8.mair0)); >>> memset(env->pmsav8.mair1, 0, sizeof(env->pmsav8.mair1)); >> >> Why some memset and some by-element? > > Roughly, memset where I would otherwise have to write a > for loop (ie where there's more than 2 elements). There's only 2 elements of mair0 and mair1... r~ From MAILER-DAEMON Tue Aug 29 12:11:08 2017 Received: from list by lists.gnu.org with archive (Exim 4.71) id 1dmj6a-0004bq-9O for mharc-qemu-arm@gnu.org; Tue, 29 Aug 2017 12:11:08 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:33679) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dmj6U-0004XY-OO for qemu-arm@nongnu.org; Tue, 29 Aug 2017 12:11:06 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dmj6P-0005bD-1x for qemu-arm@nongnu.org; Tue, 29 Aug 2017 12:11:02 -0400 Received: from mail-pf0-x229.google.com ([2607:f8b0:400e:c00::229]:33064) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1dmj6O-0005Zd-SX for qemu-arm@nongnu.org; Tue, 29 Aug 2017 12:10:56 -0400 Received: by mail-pf0-x229.google.com with SMTP id r62so11547622pfj.0 for ; Tue, 29 Aug 2017 09:10:56 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=subject:to:cc:references:from:message-id:date:user-agent :mime-version:in-reply-to:content-language:content-transfer-encoding; bh=Y6nP+QcGxQdX5ZzJmphXBBeVVF9Q7p7MHjnKRVyTrmI=; b=MCsXHbd/Hv6ApU5Q5h8SJhesxj+1NCpUV8st34ncmp79UvFustphn1430xvvcaRNGV 9msCqXdKmMo8k8Cm2404PJdyC4OZveidfaLDznqI8neHmg0c6K/Mc5KOzb1OcMA7ojBt 54HMJBDHskGnSeAQesOn1iL+6m2yO5Nxo53Os= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:subject:to:cc:references:from:message-id:date :user-agent:mime-version:in-reply-to:content-language :content-transfer-encoding; bh=Y6nP+QcGxQdX5ZzJmphXBBeVVF9Q7p7MHjnKRVyTrmI=; b=L18HRTTy8wrqt/+ulq9iyl0hyuUcbiCV3WMuCIVYqEI44H9ZDRrlKXg+JtoScgwcRt f3Uu6i6pqNLIkKnz+CxQUVxzV88b2cSVgLQdM0IHz6aZzv3s/y+kjIX4nCIRDDNgzqwm MDL1clZXYTkIUPpl0s+r6u20/wGHBN5E18OeU/W+fuwqQ632279rAZBs4DrUb7Saztg4 Uxf22XXzBPq/2Mel8uJJp/E+FhXoroSnESBz1YDZIi1Kvdu6YKuqcxkgkJ3322O0HWtt /lwIyCMMqWBxy3yPih4nOmb4tLy9IH/MxHp6C8PrgHxPlIZA+wutEtJ1s9fIcPuz5mNP 3xRQ== X-Gm-Message-State: AHYfb5iH8lGqTKeDz6MMwaeQbKNtZXmbJNcig4OJevAbEH2CH/zmQ7Xs G1lEuBia71BvUVnp X-Received: by 10.84.130.42 with SMTP id 39mr1095297plc.260.1504023055979; Tue, 29 Aug 2017 09:10:55 -0700 (PDT) Received: from bigtime.twiddle.net (97-126-108-236.tukw.qwest.net. [97.126.108.236]) by smtp.gmail.com with ESMTPSA id l6sm5964950pgo.27.2017.08.29.09.10.54 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 29 Aug 2017 09:10:55 -0700 (PDT) To: Peter Maydell , qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: patches@linaro.org References: <1503414539-28762-1-git-send-email-peter.maydell@linaro.org> <1503414539-28762-18-git-send-email-peter.maydell@linaro.org> From: Richard Henderson Message-ID: Date: Tue, 29 Aug 2017 09:10:53 -0700 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.2.1 MIME-Version: 1.0 In-Reply-To: <1503414539-28762-18-git-send-email-peter.maydell@linaro.org> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 7bit X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::229 Subject: Re: [Qemu-arm] [Qemu-devel] [PATCH 17/20] target/arm: Make MMFAR banked for v8M X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 29 Aug 2017 16:11:06 -0000 On 08/22/2017 08:08 AM, Peter Maydell wrote: > Make the MMFAR register banked if v8M security extensions are > enabled. > > Signed-off-by: Peter Maydell > --- > target/arm/cpu.h | 2 +- > hw/intc/armv7m_nvic.c | 4 ++-- > target/arm/helper.c | 4 ++-- > target/arm/machine.c | 3 ++- > 4 files changed, 7 insertions(+), 6 deletions(-) Reviewed-by: Richard Henderson r~ From MAILER-DAEMON Tue Aug 29 12:12:48 2017 Received: from list by lists.gnu.org with archive (Exim 4.71) id 1dmj8C-0005qU-2X for mharc-qemu-arm@gnu.org; Tue, 29 Aug 2017 12:12:48 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:34440) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dmj8A-0005oc-2t for qemu-arm@nongnu.org; Tue, 29 Aug 2017 12:12:46 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dmj86-0006Xc-UU for qemu-arm@nongnu.org; Tue, 29 Aug 2017 12:12:46 -0400 Received: from mail-pg0-x22f.google.com ([2607:f8b0:400e:c05::22f]:35035) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1dmj86-0006X5-OG for qemu-arm@nongnu.org; Tue, 29 Aug 2017 12:12:42 -0400 Received: by mail-pg0-x22f.google.com with SMTP id 63so12083228pgc.2 for ; Tue, 29 Aug 2017 09:12:42 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=subject:to:cc:references:from:message-id:date:user-agent :mime-version:in-reply-to:content-language:content-transfer-encoding; bh=jbCgybhAV2ZhJZe/vZv8426ein4z0XCjc4IhTMt9noE=; b=Yu2CVoRhwOTavLNRMNcUF+F0lMnY6gS7wmqBJVKV4vPA91oRcl4hnbdy/RiCJnY+Ve ScU1tomZgShi5l2UdpGmQeCj/oi4n3aYkC5KLbjuQIy3rpXOKeyNUjFy/GlWriFRKX6i 7KLAgQafA2wIaEhuFNxihNq+MYWUrOnB4KzXE= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:subject:to:cc:references:from:message-id:date :user-agent:mime-version:in-reply-to:content-language :content-transfer-encoding; bh=jbCgybhAV2ZhJZe/vZv8426ein4z0XCjc4IhTMt9noE=; b=ZjVmpHITVAsAQ+V7ZBKk+sfb4URI2dO9cSAW5Zkbaql2fzz6dCf1rnakBqLGMVKeSB OVT55brzCbYvkPb1FoPB8L4J7HwNQOT3uzAWqOFxnPlIbjjuNBmpnqzRY+zemoRj/LKV EA5cYJ0Fopk0SPEblsL4862dUBkn3x296iNyjy9ZeiCc4Q5rSpf/U6iGc/XdAWSR2xuR G4P11ML+B130zZAkPYvJAtRDn6fYPe0SPfjLA6brN2Y2Ex1DfV2GAqykqCZGJSM9Z75N yX7+CAU4AtBgOGTRRLDFdIK+VxNi2EXSaPZiWL43K3d8+YAOZS2I0PIrz4txwrAkbaWh wFAA== X-Gm-Message-State: AHYfb5hcLZzZl9wS05C/U9TehcSxJHuUA1jlF9Y1XG0jDvUaIs9yUTcK 9TKU0p3OdBjzrf8T X-Received: by 10.99.55.22 with SMTP id e22mr852870pga.101.1504023161905; Tue, 29 Aug 2017 09:12:41 -0700 (PDT) Received: from bigtime.twiddle.net (97-126-108-236.tukw.qwest.net. [97.126.108.236]) by smtp.gmail.com with ESMTPSA id t29sm6311560pgo.4.2017.08.29.09.12.40 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 29 Aug 2017 09:12:40 -0700 (PDT) To: Peter Maydell , qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: patches@linaro.org References: <1503414539-28762-1-git-send-email-peter.maydell@linaro.org> <1503414539-28762-19-git-send-email-peter.maydell@linaro.org> From: Richard Henderson Message-ID: <4cdccf07-6786-2e01-04c1-1c06151acd5a@linaro.org> Date: Tue, 29 Aug 2017 09:12:39 -0700 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.2.1 MIME-Version: 1.0 In-Reply-To: <1503414539-28762-19-git-send-email-peter.maydell@linaro.org> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 7bit X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::22f Subject: Re: [Qemu-arm] [Qemu-devel] [PATCH 18/20] target/arm: Make CFSR register banked for v8M X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 29 Aug 2017 16:12:47 -0000 On 08/22/2017 08:08 AM, Peter Maydell wrote: > Make the CFSR register banked if v8M security extensions are enabled. > > Not all the bits in this register are banked: the BFSR > bits [15:8] are shared between S and NS, and we store them > in the NS copy of the register. > > Signed-off-by: Peter Maydell > --- > target/arm/cpu.h | 7 ++++++- > hw/intc/armv7m_nvic.c | 15 +++++++++++++-- > target/arm/helper.c | 18 +++++++++--------- > target/arm/machine.c | 3 ++- > 4 files changed, 30 insertions(+), 13 deletions(-) Reviewed-by: Richard Henderson r~ From MAILER-DAEMON Tue Aug 29 12:13:07 2017 Received: from list by lists.gnu.org with archive (Exim 4.71) id 1dmj8V-00066q-6S for mharc-qemu-arm@gnu.org; Tue, 29 Aug 2017 12:13:07 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:34582) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dmj8S-00064V-JY for qemu-arm@nongnu.org; Tue, 29 Aug 2017 12:13:05 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dmj8P-0006eX-Dp for qemu-arm@nongnu.org; Tue, 29 Aug 2017 12:13:04 -0400 Received: from mail-pf0-x22f.google.com ([2607:f8b0:400e:c00::22f]:34141) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1dmj8P-0006e8-7v for qemu-arm@nongnu.org; Tue, 29 Aug 2017 12:13:01 -0400 Received: by mail-pf0-x22f.google.com with SMTP id l87so1709473pfj.1 for ; Tue, 29 Aug 2017 09:13:01 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=subject:to:cc:references:from:message-id:date:user-agent :mime-version:in-reply-to:content-language:content-transfer-encoding; bh=OvFU/Orb7pxuvhFgu7HUkbM/F+RVC95ULLlBzdvJjDg=; b=aLgMe1aa0OKcm5+JJ1zlAmjE7+IahixH6C5v0+RUH3IhH7AFS0wsJ9wnlt1uMbJ5us VlISrYYE+Ct2sAQOey8LGAlvyBNOIFf+YHsNZ8kg/f2KvMGbIqxg4gWxaluXys5TS211 I/kUgRQtEOBnv0Vh85/31AJ5xFVd7DQ6vBbsk= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:subject:to:cc:references:from:message-id:date :user-agent:mime-version:in-reply-to:content-language :content-transfer-encoding; bh=OvFU/Orb7pxuvhFgu7HUkbM/F+RVC95ULLlBzdvJjDg=; b=mG9koepYs1bbPMXSF1sSby3N4XSbrpSCW3poAlGK7qroe7q7uEfToHeDk5pHg67fEK 6eVM49MS4cjVBfdheeLFlK0N84ATVaIbulohfuFITZagi849yXczY0f6hz1+1wuDT6w/ mzbgpbFZE7x+7gulMoU+a6bIS2WFwDCYrVClIUGHskB0rMo1PVgRus9YlcCLuUlFznt+ 0aIrKePYGmigymMRL+KtU+7aFNj5zPw2grmMgQRZI9dkV+kgZPHWHUVlCb2p30owsfxj QrfLOOR2ojKMBwTkD10+xuNWPPLbYT9EGq/2pZ2NjsMGUsN1tooTpw+76hKgbuEwTIk7 yVqw== X-Gm-Message-State: AHYfb5gDlsp/0eI9aO56O8TIxCEG4obGNzC+YTsED5AtbnLgwO98YlhH vyC4wN8mR928sOqh X-Received: by 10.99.49.210 with SMTP id x201mr791119pgx.151.1504023180460; Tue, 29 Aug 2017 09:13:00 -0700 (PDT) Received: from bigtime.twiddle.net (97-126-108-236.tukw.qwest.net. [97.126.108.236]) by smtp.gmail.com with ESMTPSA id i2sm5617247pgn.73.2017.08.29.09.12.59 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 29 Aug 2017 09:12:59 -0700 (PDT) To: Peter Maydell , qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: patches@linaro.org References: <1503414539-28762-1-git-send-email-peter.maydell@linaro.org> <1503414539-28762-20-git-send-email-peter.maydell@linaro.org> From: Richard Henderson Message-ID: Date: Tue, 29 Aug 2017 09:12:57 -0700 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.2.1 MIME-Version: 1.0 In-Reply-To: <1503414539-28762-20-git-send-email-peter.maydell@linaro.org> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 7bit X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::22f Subject: Re: [Qemu-arm] [Qemu-devel] [PATCH 19/20] target/arm: Move regime_is_secure() to target/arm/internals.h X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 29 Aug 2017 16:13:05 -0000 On 08/22/2017 08:08 AM, Peter Maydell wrote: > Move the regime_is_secure() utility function to internals.h; > we are going to want to call it from translate.c. > > Signed-off-by: Peter Maydell > --- > target/arm/internals.h | 26 ++++++++++++++++++++++++++ > target/arm/helper.c | 26 -------------------------- > 2 files changed, 26 insertions(+), 26 deletions(-) Reviewed-by: Richard Henderson r~ From MAILER-DAEMON Tue Aug 29 12:23:46 2017 Received: from list by lists.gnu.org with archive (Exim 4.71) id 1dmjIo-0004HV-C8 for mharc-qemu-arm@gnu.org; Tue, 29 Aug 2017 12:23:46 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:38008) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dmjIm-0004G0-De for qemu-arm@nongnu.org; Tue, 29 Aug 2017 12:23:45 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dmjIl-0004WP-NT for qemu-arm@nongnu.org; Tue, 29 Aug 2017 12:23:44 -0400 Received: from mail-io0-x22e.google.com ([2607:f8b0:4001:c06::22e]:34526) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1dmjIf-0004TE-1V; Tue, 29 Aug 2017 12:23:37 -0400 Received: by mail-io0-x22e.google.com with SMTP id n71so22721276iod.1; Tue, 29 Aug 2017 09:23:36 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=mime-version:in-reply-to:references:from:date:message-id:subject:to :cc; bh=HnEhVX+CaccwHelxmc9rI/oYb9aI6gtC5xOmbl5wEQI=; b=nraI+4jnHMFkVfhUTF4jIfx+pf0xoaVN9qFTIbBuw/QLM5NISof6zv33UR0hHbUVAx WjlesO7lf/YwlNQUuPui/BC2dbDQfI+woYroNqSsbqARY4dR3Z8IaQnxq32vrwkk4VcL Qka5k0jhjgPOYPuO0CrrGQF7Z27K1SAJ+37viXyhxd1+M46FNbckG/cdgEdfKUD9TO1h cLkgvuULahS/TIzcnbKX2fZqyw5i046D9PZyPODRDi/9ok6l+dDDQnW+LbaJcTxKl+ml hxWf1d//JY0jzqUq9C17MgLpJ/4S/ISGvX8yoaKdVpUTe7BBk2ONg6bOwL2c/MAzpgJR olIg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:in-reply-to:references:from:date :message-id:subject:to:cc; bh=HnEhVX+CaccwHelxmc9rI/oYb9aI6gtC5xOmbl5wEQI=; b=eZJlxFlmnBk8UgWspmMwaQqgjtCe9M13er0Yr5SHV3RRGWY03PqNl3N3+E34IAWPQS AQQy/4ugy2l8cpzJdr760jMEdOdCejA9bBbiOMSLMQtXZwyzH74tfMKgiNMkX7HGFnwC azJmPbvr+omo2NI8eX5+2KMqrY0ez5xZSKIdF/N6Jxrd5h/FrBVmVvtgwAd+U6pblJWK gxv0K4XnY1sglSCy6rNEVw/WZqH9eaWdgj92vx2KQ13ASCvidnj6CyVqU57x0XkAsDIA vxkrklBP4BxHbsZPJ1t+ScmjWoYwVkfee6ir5bSqZDulxBXPQdjJ6yguJ8efX9AWKfx4 hRpA== X-Gm-Message-State: AHYfb5gG605RWBZdQMvSWQOj8k9eNAqpVzIEtFVNfGRMFLxaqX49Xofl 9eUZmQ4U7ylQ2TG7EvMF/sB3Ts6tNA== X-Received: by 10.107.129.11 with SMTP id c11mr4464867iod.17.1504023816354; Tue, 29 Aug 2017 09:23:36 -0700 (PDT) MIME-Version: 1.0 Received: by 10.79.166.2 with HTTP; Tue, 29 Aug 2017 09:23:05 -0700 (PDT) In-Reply-To: <3148d084-9bff-2d8e-f1a7-fba94a1e7f87@linaro.org> References: <20170829063313.10237-1-bobby.prani@gmail.com> <20170829063313.10237-5-bobby.prani@gmail.com> <3148d084-9bff-2d8e-f1a7-fba94a1e7f87@linaro.org> From: Pranith Kumar Date: Tue, 29 Aug 2017 12:23:05 -0400 Message-ID: To: Richard Henderson Cc: =?UTF-8?B?QWxleCBCZW5uw6ll?= , Paolo Bonzini , Peter Crosthwaite , Claudio Fontana , Andrzej Zaborowski , Aurelien Jarno , Alexander Graf , Stefan Weil , "open list:Overall" , "open list:AArch64 target" Content-Type: text/plain; charset="UTF-8" X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4001:c06::22e Subject: Re: [Qemu-arm] [RFC v3 PATCH 5/5] tcg/softmmu: Increase size of TLB caches X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 29 Aug 2017 16:23:45 -0000 On Tue, Aug 29, 2017 at 11:01 AM, Richard Henderson wrote: > On 08/28/2017 11:33 PM, Pranith Kumar wrote: >> + * TODO: rewrite this comment >> */ >> -#define CPU_TLB_BITS \ >> - MIN(8, \ >> - TCG_TARGET_TLB_DISPLACEMENT_BITS - CPU_TLB_ENTRY_BITS - \ >> - (NB_MMU_MODES <= 1 ? 0 : \ >> - NB_MMU_MODES <= 2 ? 1 : \ >> - NB_MMU_MODES <= 4 ? 2 : \ >> - NB_MMU_MODES <= 8 ? 3 : 4)) >> +#define CPU_TLB_BITS MIN(12, TCG_TARGET_TLB_MAX_INDEX_BITS) >> > > Ah, no. This will cause several builds to fail. > You still need to restrict the *total* size of > the TLB to TCG_TARGET_TLB_DISPLACEMENT_BITS. > > (That's not a 100% accurate statement, but is close. > See the QEMU_BUILD_BUG_ON in tcg/*/*.c for specifics.) > > The upshot is that if a target has 2 MMU modes, > we can allow them to be bigger. But if it has 8, > we have to make them smaller. > > I was expecting you to write > > MIN(MIN(12, TCG_TARGET_TLB_MAX_INDEX_BITS) > TCG_TARGET_TLB_DISPLACEMENT_BITS - CPU_TLB_ENTRY_BITS - > ...) I see what you mean. I will fix the blunder and send an updated patch. Thanks! -- Pranith From MAILER-DAEMON Tue Aug 29 12:31:48 2017 Received: from list by lists.gnu.org with archive (Exim 4.71) id 1dmjQa-00088P-NX for mharc-qemu-arm@gnu.org; Tue, 29 Aug 2017 12:31:48 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:40390) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dmjQV-000832-C6 for qemu-arm@nongnu.org; Tue, 29 Aug 2017 12:31:47 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dmjQQ-0008Rf-Cu for qemu-arm@nongnu.org; Tue, 29 Aug 2017 12:31:43 -0400 Received: from mail-pg0-x22b.google.com ([2607:f8b0:400e:c05::22b]:35046) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1dmjQQ-0008QS-5l for qemu-arm@nongnu.org; Tue, 29 Aug 2017 12:31:38 -0400 Received: by mail-pg0-x22b.google.com with SMTP id 63so12224097pgc.2 for ; Tue, 29 Aug 2017 09:31:38 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=subject:to:cc:references:from:message-id:date:user-agent :mime-version:in-reply-to:content-language:content-transfer-encoding; bh=Fvqp4ys7VgciDinI6si6BGnKGD8DLWuR6r4pQSVpgnc=; b=jknWT1g/P+joOrHAZqL9BGsEwZADRI/59AF8wGYWkL/6eRRYbW6YmMlQvZrN1xOdJP B8mq/HWSTtIxPWP3UvJpomz7ARz4Kj8K5D1nLgoIypnLyvhMuJ1Kk4YQTzpAnn38K8Ar Q6OqxmeeFl1C4glfkEvCFFfi83/XLvo/841r8= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:subject:to:cc:references:from:message-id:date :user-agent:mime-version:in-reply-to:content-language :content-transfer-encoding; bh=Fvqp4ys7VgciDinI6si6BGnKGD8DLWuR6r4pQSVpgnc=; b=jNUSJMcx8ZM2x+sy4GkbiLCwyd15bw3qot1m6h7nD4SxNTsA5YYlt5Jq2byNnu9u7W wEeuB+Ua82YBEzD40tuRX1spkyKTB64+OZ4vKxISp8B8LhSoOM/PL+6f+XgWjoXYi5Bm my0A0OFT0M6vG9O8KTn2hExQ6FlgJxfSqQQ9uFfhu2zZcAXph0041eenjpVUZgqBxJ3Q IrR4A19n6AlMBphYomVuH4unE8+oENxbpqUmjItqhm23vQN2jbY5LiaSwZ8XTmHAoF13 BQbmYr+Mkgd85N9cLqtsS0FUvtlWbWnx3CeYG+hsOPmfwVEVg5BxiQO4C8G7ZGckeztQ V/NA== X-Gm-Message-State: AHYfb5iVf66vY5k7RGa901d8U087/qphtI3xW9KYE+DCgABGEEywravw OqJKlBxYOPQxmkfs X-Received: by 10.84.232.6 with SMTP id h6mr1171900plk.70.1504024297042; Tue, 29 Aug 2017 09:31:37 -0700 (PDT) Received: from bigtime.twiddle.net (97-126-108-236.tukw.qwest.net. [97.126.108.236]) by smtp.gmail.com with ESMTPSA id m68sm5891011pfk.15.2017.08.29.09.31.35 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 29 Aug 2017 09:31:36 -0700 (PDT) To: Peter Maydell , qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: patches@linaro.org References: <1503414539-28762-1-git-send-email-peter.maydell@linaro.org> <1503414539-28762-21-git-send-email-peter.maydell@linaro.org> From: Richard Henderson Message-ID: <7cdc8025-089e-2a02-24cf-e8a02ae42bb6@linaro.org> Date: Tue, 29 Aug 2017 09:31:34 -0700 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.2.1 MIME-Version: 1.0 In-Reply-To: <1503414539-28762-21-git-send-email-peter.maydell@linaro.org> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 7bit X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::22b Subject: Re: [Qemu-arm] [Qemu-devel] [PATCH 20/20] target/arm: Implement BXNS, and banked stack pointers X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 29 Aug 2017 16:31:47 -0000 On 08/22/2017 08:08 AM, Peter Maydell wrote: > Implement the BXNS v8M instruction, which is like BX but will do a > jump-and-switch-to-NonSecure if the branch target address has bit 0 > clear. > > This is the first piece of code which implements "switch to the > other security state", so the commit also includes the code to > switch the stack pointers around, which is the only complicated > part of switching security state. > > BLXNS is more complicated than just "BXNS but set the link register", > so we leave it for a separate commit. > > Signed-off-by: Peter Maydell > --- > target/arm/cpu.h | 13 +++++++++ > target/arm/helper.h | 2 ++ > target/arm/translate.h | 1 + > target/arm/helper.c | 79 ++++++++++++++++++++++++++++++++++++++++++++++++++ > target/arm/machine.c | 2 ++ > target/arm/translate.c | 42 ++++++++++++++++++++++++++- > 6 files changed, 138 insertions(+), 1 deletion(-) Reviewed-by: Richard Henderson r~ From MAILER-DAEMON Tue Aug 29 13:06:47 2017 Received: from list by lists.gnu.org with archive (Exim 4.71) id 1dmjyR-0002YE-7O for mharc-qemu-arm@gnu.org; Tue, 29 Aug 2017 13:06:47 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:57704) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dmjyO-0002Y6-Pm for qemu-arm@nongnu.org; Tue, 29 Aug 2017 13:06:46 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dmjyL-0001RI-Lp for qemu-arm@nongnu.org; Tue, 29 Aug 2017 13:06:44 -0400 Received: from mail-pf0-x244.google.com ([2607:f8b0:400e:c00::244]:38574) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1dmjyL-0001QL-Fl; Tue, 29 Aug 2017 13:06:41 -0400 Received: by mail-pf0-x244.google.com with SMTP id r187so2694160pfr.5; Tue, 29 Aug 2017 10:06:40 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=date:from:to:cc:subject:message-id:references:mime-version :content-disposition:in-reply-to:user-agent; bh=jXvf8iSmtBPWk6QCl9PSMt2g6/xg709lpx2ZZjm1OPA=; b=cz1gT97x0BiVRRave4z2mIH1ob3CcU4y9+XwyhWegU+CwOxp4xib3Wg+e/xhroPxFa opjs+1+VV99liqyvDuACGe1BLleAXtfD1se/62fudzQ6fUe76YWDZcRNGeU6SgyUAh4l hedTV3nyOVXc96mWbTsKbSJJG6Pavqt4uR/v4a7+cF/4B+xOXiITb+A2AknY3+JurTEU TzJw2oo5A+cV15rTjKScCZaioHHJ1wCQ5yjF7/AMJbXGiN2kcXdkyktJFJUo9OxoxT/d I+OoGxPTOYHSFO3jcJ70+5INYe9aqADxxqEXFkayXTVDle1U+eCqMLygtcnLTAVHyJxT 6bFw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:in-reply-to:user-agent; bh=jXvf8iSmtBPWk6QCl9PSMt2g6/xg709lpx2ZZjm1OPA=; b=jMSBfLt/NeLYs8oacP1RloJFp6tRb613Sf6pBeSAXb1zv9nNX5a7k6q/VQ6/oeCInR 3ZexBHrBgOfpoMB0oIW+SPq1eET2NqnBjsxik0vkSH3fxFS5l8sRS6LotaE1pI/RD0Jq 9k98f6W0cNuwbkmkOLWwSuELmRDSmGcs9H+EHS0jFezBmEqRGr39ya1R8o/Hp5z6E1YP 7GA9BzNlW9bp+mZLf1z4/5UfWsJ6eBu085Tag151pHJfy9z1KfVnQ7d/je1J8HxE4vUC P5pDZQIuOdSJIE2INN+2uFSiKG69hURVlXrxm5+aH8Dtr1IdICzC6uE8C1Sz88VvxUDq hMag== X-Gm-Message-State: AHYfb5iF4Lvt9RP0iSB20zb8P7b4DcPA2XPDkKD+z9Na9QLP3JCuF6Nj 6gVR86X11Heu1g== X-Received: by 10.98.58.220 with SMTP id v89mr999625pfj.19.1504026399129; Tue, 29 Aug 2017 10:06:39 -0700 (PDT) Received: from virtx40 ([111.93.218.67]) by smtp.gmail.com with ESMTPSA id u187sm5454528pfu.140.2017.08.29.10.06.33 (version=TLS1_2 cipher=AES128-SHA bits=128/128); Tue, 29 Aug 2017 10:06:37 -0700 (PDT) Date: Tue, 29 Aug 2017 22:36:30 +0530 From: Linu Cherian To: Bharat Bhushan Cc: eric.auger@redhat.com, eric.auger.pro@gmail.com, peter.maydell@linaro.org, alex.williamson@redhat.com, mst@redhat.com, qemu-arm@nongnu.org, qemu-devel@nongnu.org, kevin.tian@intel.com, marc.zyngier@arm.com, tn@semihalf.com, will.deacon@arm.com, drjones@redhat.com, robin.murphy@arm.com, christoffer.dall@linaro.org, linu.cherian@cavium.com Message-ID: <20170829170630.GA2622@virtx40> References: <1503312534-6642-1-git-send-email-Bharat.Bhushan@nxp.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1503312534-6642-1-git-send-email-Bharat.Bhushan@nxp.com> User-Agent: Mutt/1.5.21 (2010-09-15) X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::244 Subject: Re: [Qemu-arm] [PATCH v3 0/2] virtio-iommu: VFIO integration X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 29 Aug 2017 17:06:46 -0000 Hi, On Mon Aug 21, 2017 at 04:18:52PM +0530, Bharat Bhushan wrote: > This V3 version is mainly about rebasing on v3 version on Virtio-iommu device > framework from Eric Augur and addresing review comments. > > This patch series allows PCI pass-through using virtio-iommu. > > This series is based on: > - virtio-iommu specification written by Jean-Philippe Brucker > [RFC 0/3] virtio-iommu: a paravirtualized IOMMU, > > - virtio-iommu driver by Jean-Philippe Brucker > [RFC PATCH linux] iommu: Add virtio-iommu driver > > - virtio-iommu device emulation by Eric Augur. > [RFC v3 0/8] VIRTIO-IOMMU device > > PCI device pass-through and virtio-net-pci is tested with these changes using dma-ops > Facing issues while trying to test with VFIO. vfio_dma_map fails as below, qemu-system-aarch64: vfio_dma_map(0x1ff0da0, 0xfdfc7000, 0x1000, 0xffff79acc000) = -22 (Invalid argument) Very likely this seem to be an issue with map size. Kernel PAGE_SIZE is 64k on my host and hence the map size for the physical SMMU also will start with 64k. Qemu source: https://github.com/eauger/qemu.git + this patch series on branch v2.10.0-rc0-virtio-iommu-rfcv3 Linux source: git://linux-arm.org/linux-jpb.git on branch virtio-iommu/v0.1 Any pointers ? The other related questions i had, 1. In, virtio_iommu_device_realize in qemu, s->config.page_sizes = TARGET_PAGE_MASK; Same is being taken as pgsize_bitmap in virtio_iommu guest kernel driver. In, viommu_probe virtio_cread(vdev, struct virtio_iommu_config, page_sizes, &viommu->pgsize_bitmap); Should s->config.page_sizes be initialized with page bitmap instead of page mask ? 2. Should we not populate the supported page sizes based on host kernel size and SMMU hardware capability rather than based on the machine emulated on qemu? Atleast that makes sense for VFIO case. > This patch series does not implement RESV_MEM changes proposal by Jean-Philippe "https://lists.gnu.org/archive/html/qemu-devel/2017-07/msg01796.html" > > v2->v3: > - This series is based on "[RFC v3 0/8] VIRTIO-IOMMU device" > Which is based on top of v2.10-rc0 that > - Fixed issue with two PCI devices > - Addressed review comments > > v1->v2: > - Added trace events > - removed vSMMU3 link in patch description > > Bharat Bhushan (2): > target/arm/kvm: Translate the MSI doorbell in kvm_arch_fixup_msi_route > virtio-iommu: vfio integration with virtio-iommu > > hw/virtio/trace-events | 5 ++ > hw/virtio/virtio-iommu.c | 163 +++++++++++++++++++++++++++++++++++++++ > include/hw/virtio/virtio-iommu.h | 6 ++ > target/arm/kvm.c | 27 +++++++ > target/arm/trace-events | 3 + > 5 files changed, 204 insertions(+) > > -- > 1.9.3 > > -- Linu cherian From MAILER-DAEMON Tue Aug 29 13:20:23 2017 Received: from list by lists.gnu.org with archive (Exim 4.71) id 1dmkBb-00078u-5F for mharc-qemu-arm@gnu.org; Tue, 29 Aug 2017 13:20:23 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:43908) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dmiKF-0004Jm-Ez for qemu-arm@nongnu.org; Tue, 29 Aug 2017 11:21:12 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dmiKC-0007Nx-9W for qemu-arm@nongnu.org; Tue, 29 Aug 2017 11:21:11 -0400 Received: from mail-c.ads.isi.edu ([128.9.180.198]:36101) by eggs.gnu.org with esmtps (TLS1.0:RSA_ARCFOUR_SHA1:16) (Exim 4.71) (envelope-from ) id 1dmiKB-0007HN-Tq for qemu-arm@nongnu.org; Tue, 29 Aug 2017 11:21:08 -0400 X-IronPort-AV: E=Sophos;i="5.41,445,1498546800"; d="scan'208,217";a="1137430" Received: from usmdrmbx01.ads.isi.edu ([10.100.2.77]) by usmdrip03-mgmt.ads.isi.edu with ESMTP; 29 Aug 2017 08:20:56 -0700 Received: from usarlmbx03.ads.isi.edu (10.13.52.79) by usmdrmbx01.ads.isi.edu (10.100.2.77) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1034.26; Tue, 29 Aug 2017 08:21:01 -0700 Received: from usarlmbx01.ads.isi.edu (10.13.52.77) by usarlmbx03.ads.isi.edu (10.13.52.79) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1034.26; Tue, 29 Aug 2017 08:20:53 -0700 Received: from usarlmbx01.ads.isi.edu ([fe80::71d5:b7e4:2bfe:8a5b]) by usarlmbx01.ads.isi.edu ([fe80::71d5:b7e4:2bfe:8a5b%17]) with mapi id 15.01.1034.026; Tue, 29 Aug 2017 08:20:53 -0700 From: Dong-In Kang To: "qemu-arm@nongnu.org" Thread-Topic: Qemu interrupt handling latency Thread-Index: AQHTINpnBG3SbDvvLkOz20Y3t4GziQ== Date: Tue, 29 Aug 2017 15:20:52 +0000 Message-ID: <2D29846F-5540-4072-B9C9-CA3241E469EC@isi.edu> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [128.9.47.101] Content-Type: multipart/alternative; boundary="_000_2D29846F55404072B9C9CA3241E469ECisiedu_" MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. 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n77sm1259513ywd.42.2017.08.29.10.32.27 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 29 Aug 2017 10:32:27 -0700 (PDT) From: Pranith Kumar To: Peter Maydell , qemu-arm@nongnu.org (open list:ARM cores), qemu-devel@nongnu.org (open list:All patches CC here) Date: Tue, 29 Aug 2017 13:32:26 -0400 Message-Id: <20170829173226.7625-1-bobby.prani@gmail.com> X-Mailer: git-send-email 2.13.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4002:c05::241 Subject: [Qemu-arm] [PATCH] arm_gicv3_kvm: Fix compile warning X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 29 Aug 2017 17:32:34 -0000 Fix the following warning: /home/pranith/qemu/hw/intc/arm_gicv3_kvm.c:296:17: warning: logical not is only applied to the left hand side of this bitwise operator [-Wlogical-not-parentheses] if (!c->gicr_ctlr & GICR_CTLR_ENABLE_LPIS) { ^ ~ /home/pranith/qemu/hw/intc/arm_gicv3_kvm.c:296:17: note: add parentheses after the '!' to evaluate the bitwise operator first if (!c->gicr_ctlr & GICR_CTLR_ENABLE_LPIS) { ^ /home/pranith/qemu/hw/intc/arm_gicv3_kvm.c:296:17: note: add parentheses around left hand side expression to silence this warning if (!c->gicr_ctlr & GICR_CTLR_ENABLE_LPIS) { ^ Signed-off-by: Pranith Kumar --- hw/intc/arm_gicv3_kvm.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/intc/arm_gicv3_kvm.c b/hw/intc/arm_gicv3_kvm.c index 6051c77705..481fe5405a 100644 --- a/hw/intc/arm_gicv3_kvm.c +++ b/hw/intc/arm_gicv3_kvm.c @@ -293,7 +293,7 @@ static void kvm_arm_gicv3_put(GICv3State *s) kvm_gicr_access(s, GICR_PROPBASER + 4, ncpu, ®h, true); reg64 = c->gicr_pendbaser; - if (!c->gicr_ctlr & GICR_CTLR_ENABLE_LPIS) { + if (!(c->gicr_ctlr & GICR_CTLR_ENABLE_LPIS)) { /* Setting PTZ is advised if LPIs are disabled, to reduce * GIC initialization time. */ -- 2.11.0 From MAILER-DAEMON Tue Aug 29 13:56:41 2017 Received: from list by lists.gnu.org with archive (Exim 4.71) id 1dmkki-00019p-Ut for mharc-qemu-arm@gnu.org; Tue, 29 Aug 2017 13:56:40 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:43167) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dmkkg-00019a-LK for qemu-arm@nongnu.org; Tue, 29 Aug 2017 13:56:39 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dmkkf-00007Y-RX for qemu-arm@nongnu.org; Tue, 29 Aug 2017 13:56:38 -0400 Received: from mail-io0-x243.google.com ([2607:f8b0:4001:c06::243]:34012) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1dmkkf-00007C-Lg; Tue, 29 Aug 2017 13:56:37 -0400 Received: by mail-io0-x243.google.com with SMTP id d81so3786426ioj.1; Tue, 29 Aug 2017 10:56:37 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=mime-version:in-reply-to:references:from:date:message-id:subject:to; bh=6CIsojfZPX1L6DFkMiwLmYU1O1TJMQZKXTbC+QcUu2g=; b=hkNIrXNgL1j8PtISbBJv/Kb88xqZlZ3pEp6o01RWV8AmZl6AcCZcZLlpFv2y5+y0Kk zkevnVYpYaaEYNgjOJRzFYVWpMOQTU7YyWcZd8ns39EDkaiXk/iScnlJkwVRPGpbwAQX 7vRelx0cJlahjewDvLO1XoNCXAEDkB8JsKTUUdew1X4k4cUHoJn5OQ4ddyyxPn/ml+FS c6OUH2h4tFZQ3Feb4eGdUjs5yuhJtIBOrkekumEY3denbqRc0lm10ReGxLPmRjXQLoAl bile3PUyBkaETtLGLo4x/xVpnY5NWouAs2GWgsSI/heUkcF3sQY3FT09TI9oCSh8plUH Y+/A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:in-reply-to:references:from:date :message-id:subject:to; bh=6CIsojfZPX1L6DFkMiwLmYU1O1TJMQZKXTbC+QcUu2g=; b=S13nm1W3hohvqz6wFsLaMEB2xMq5PtUPmZie8mzIUEFeSoPAy/ux3/smkS/6BE7AbU /LeDg0zcvIjhaVivlpfD5oqAjAQEl7Ceg25tg/4T1tE8G+zOP4IZqYWww/CTK/7Vlnie 891/qIo3OkaTPysxiMBI5hHJpM90KEEYXJJZuzniF1DHSSpdfYuuDs7nZxKKbUtuybZb PV3c16Mf2L+j3QL3sn+rZVFK1rMtPdjj6UD0wDIZx35vhoMcG2o6afOVV356cu6KV+nC ij1q1KTjImxrSX+pjoFDlBxKwO/ZQbca9g1KcLY6b1RVeM+ispMZ0/4bb0Z71WsErxW6 7eiA== X-Gm-Message-State: AHYfb5jnGDyRBB+QZETdXPmS7SRVy32FU+mcc+S8dtIMnR/y3p0Vs7nO Hr9BSS6uUWtqwcJwyW31/gX+xnImPA== X-Received: by 10.107.205.194 with SMTP id d185mr4801617iog.8.1504029396678; Tue, 29 Aug 2017 10:56:36 -0700 (PDT) MIME-Version: 1.0 Received: by 10.79.166.2 with HTTP; Tue, 29 Aug 2017 10:56:06 -0700 (PDT) In-Reply-To: <20170829173226.7625-1-bobby.prani@gmail.com> References: <20170829173226.7625-1-bobby.prani@gmail.com> From: Pranith Kumar Date: Tue, 29 Aug 2017 13:56:06 -0400 Message-ID: To: Peter Maydell , "open list:ARM cores" , "open list:All patches CC here" Content-Type: text/plain; charset="UTF-8" X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4001:c06::243 Subject: Re: [Qemu-arm] [PATCH] arm_gicv3_kvm: Fix compile warning X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 29 Aug 2017 17:56:39 -0000 I should have worded the subject better. The warning is pointing to an actual bug. On Tue, Aug 29, 2017 at 1:32 PM, Pranith Kumar wrote: > Fix the following warning: > > /home/pranith/qemu/hw/intc/arm_gicv3_kvm.c:296:17: warning: logical not is only applied to the left hand side of this bitwise operator [-Wlogical-not-parentheses] > if (!c->gicr_ctlr & GICR_CTLR_ENABLE_LPIS) { > ^ ~ > /home/pranith/qemu/hw/intc/arm_gicv3_kvm.c:296:17: note: add parentheses after the '!' to evaluate the bitwise operator first > if (!c->gicr_ctlr & GICR_CTLR_ENABLE_LPIS) { > ^ > /home/pranith/qemu/hw/intc/arm_gicv3_kvm.c:296:17: note: add parentheses around left hand side expression to silence this warning > if (!c->gicr_ctlr & GICR_CTLR_ENABLE_LPIS) { > ^ > > Signed-off-by: Pranith Kumar > --- > hw/intc/arm_gicv3_kvm.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/hw/intc/arm_gicv3_kvm.c b/hw/intc/arm_gicv3_kvm.c > index 6051c77705..481fe5405a 100644 > --- a/hw/intc/arm_gicv3_kvm.c > +++ b/hw/intc/arm_gicv3_kvm.c > @@ -293,7 +293,7 @@ static void kvm_arm_gicv3_put(GICv3State *s) > kvm_gicr_access(s, GICR_PROPBASER + 4, ncpu, ®h, true); > > reg64 = c->gicr_pendbaser; > - if (!c->gicr_ctlr & GICR_CTLR_ENABLE_LPIS) { > + if (!(c->gicr_ctlr & GICR_CTLR_ENABLE_LPIS)) { > /* Setting PTZ is advised if LPIs are disabled, to reduce > * GIC initialization time. > */ > -- > 2.11.0 > -- Pranith From MAILER-DAEMON Tue Aug 29 15:43:15 2017 Received: from list by lists.gnu.org with archive (Exim 4.71) id 1dmmPr-0003Bl-8p for mharc-qemu-arm@gnu.org; Tue, 29 Aug 2017 15:43:15 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:37977) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dmmPp-0003BY-8z for qemu-arm@nongnu.org; Tue, 29 Aug 2017 15:43:14 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dmmPl-0007nE-Cl for qemu-arm@nongnu.org; Tue, 29 Aug 2017 15:43:13 -0400 Received: from mx1.redhat.com ([209.132.183.28]:35182) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1dmmPl-0007mW-21; Tue, 29 Aug 2017 15:43:09 -0400 Received: from smtp.corp.redhat.com (int-mx04.intmail.prod.int.phx2.redhat.com [10.5.11.14]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id B37DA5D686; Tue, 29 Aug 2017 19:43:06 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mx1.redhat.com B37DA5D686 Authentication-Results: ext-mx10.extmail.prod.ext.phx2.redhat.com; dmarc=none (p=none dis=none) header.from=redhat.com Authentication-Results: ext-mx10.extmail.prod.ext.phx2.redhat.com; spf=fail smtp.mailfrom=eric.auger@redhat.com Received: from localhost.localdomain (ovpn-116-92.ams2.redhat.com [10.36.116.92]) by smtp.corp.redhat.com (Postfix) with ESMTPS id 4D4995D732; Tue, 29 Aug 2017 19:42:57 +0000 (UTC) To: Linu Cherian , Bharat Bhushan References: <1503312534-6642-1-git-send-email-Bharat.Bhushan@nxp.com> <20170829170630.GA2622@virtx40> Cc: peter.maydell@linaro.org, kevin.tian@intel.com, drjones@redhat.com, mst@redhat.com, marc.zyngier@arm.com, tn@semihalf.com, will.deacon@arm.com, qemu-devel@nongnu.org, alex.williamson@redhat.com, qemu-arm@nongnu.org, linu.cherian@cavium.com, robin.murphy@arm.com, christoffer.dall@linaro.org, eric.auger.pro@gmail.com From: Auger Eric Message-ID: <1698021f-3b2b-84aa-01de-ba042097a9ee@redhat.com> Date: Tue, 29 Aug 2017 21:42:49 +0200 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:45.0) Gecko/20100101 Thunderbird/45.4.0 MIME-Version: 1.0 In-Reply-To: <20170829170630.GA2622@virtx40> Content-Type: text/plain; charset=windows-1252 Content-Transfer-Encoding: 7bit X-Scanned-By: MIMEDefang 2.79 on 10.5.11.14 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.39]); Tue, 29 Aug 2017 19:43:07 +0000 (UTC) X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.132.183.28 Subject: Re: [Qemu-arm] [Qemu-devel] [PATCH v3 0/2] virtio-iommu: VFIO integration X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 29 Aug 2017 19:43:14 -0000 Hi Linu, On 29/08/2017 19:06, Linu Cherian wrote: > Hi, > > On Mon Aug 21, 2017 at 04:18:52PM +0530, Bharat Bhushan wrote: >> This V3 version is mainly about rebasing on v3 version on Virtio-iommu device >> framework from Eric Augur and addresing review comments. >> >> This patch series allows PCI pass-through using virtio-iommu. >> >> This series is based on: >> - virtio-iommu specification written by Jean-Philippe Brucker >> [RFC 0/3] virtio-iommu: a paravirtualized IOMMU, >> >> - virtio-iommu driver by Jean-Philippe Brucker >> [RFC PATCH linux] iommu: Add virtio-iommu driver >> >> - virtio-iommu device emulation by Eric Augur. >> [RFC v3 0/8] VIRTIO-IOMMU device >> >> PCI device pass-through and virtio-net-pci is tested with these changes using dma-ops >> > > Facing issues while trying to test with VFIO. > > vfio_dma_map fails as below, > qemu-system-aarch64: vfio_dma_map(0x1ff0da0, 0xfdfc7000, 0x1000, 0xffff79acc000) = -22 (Invalid argument) > Very likely this seem to be an issue with map size. Kernel PAGE_SIZE > is 64k on my host and hence the map size for the physical SMMU also will > start with 64k. Most probably. I currently use 4KB on both host/guest. Also the devices I assign have BARs smaller than 64kB and this causes issue with DPDK. > > Qemu source: https://github.com/eauger/qemu.git + this patch series > on branch v2.10.0-rc0-virtio-iommu-rfcv3 > Linux source: git://linux-arm.org/linux-jpb.git > on branch virtio-iommu/v0.1 > Any pointers ? Looks good. > > The other related questions i had, > 1. In, virtio_iommu_device_realize in qemu, > s->config.page_sizes = TARGET_PAGE_MASK; > > Same is being taken as pgsize_bitmap in virtio_iommu guest kernel driver. > In, viommu_probe > virtio_cread(vdev, struct virtio_iommu_config, page_sizes, > &viommu->pgsize_bitmap); > > Should s->config.page_sizes be initialized with page bitmap instead > of page mask ? We currently support all page size bits greater or equal than the guest page size define TARGET_PAGE_MASK ~(TARGET_PAGE_SIZE - 1) We evoked the problem you seem to face in https://lists.gnu.org/archive/html/qemu-devel/2017-06/msg05308.html and the temporary solution was to use TARGET_PAGE_MASK > > 2. Should we not populate the supported page sizes based on > host kernel size and SMMU hardware capability rather than > based on the machine emulated on qemu? Atleast that makes > sense for VFIO case. I think Jean's proposal to address this issue is to enhance the PROBE API. The driver would fetch for each device an accurate page_size_mask that would characterize either the virtual iommu or the underlying physical iommu. This would override the global page_size_mask. I think the plan was to issue that for v0.5 Thanks Eric > >> This patch series does not implement RESV_MEM changes proposal by Jean-Philippe "https://lists.gnu.org/archive/html/qemu-devel/2017-07/msg01796.html" >> >> v2->v3: >> - This series is based on "[RFC v3 0/8] VIRTIO-IOMMU device" >> Which is based on top of v2.10-rc0 that >> - Fixed issue with two PCI devices >> - Addressed review comments >> >> v1->v2: >> - Added trace events >> - removed vSMMU3 link in patch description >> >> Bharat Bhushan (2): >> target/arm/kvm: Translate the MSI doorbell in kvm_arch_fixup_msi_route >> virtio-iommu: vfio integration with virtio-iommu >> >> hw/virtio/trace-events | 5 ++ >> hw/virtio/virtio-iommu.c | 163 +++++++++++++++++++++++++++++++++++++++ >> include/hw/virtio/virtio-iommu.h | 6 ++ >> target/arm/kvm.c | 27 +++++++ >> target/arm/trace-events | 3 + >> 5 files changed, 204 insertions(+) >> >> -- >> 1.9.3 >> >> > From MAILER-DAEMON Tue Aug 29 17:58:57 2017 Received: from list by lists.gnu.org with archive (Exim 4.71) id 1dmoXB-0003C3-6e for mharc-qemu-arm@gnu.org; Tue, 29 Aug 2017 17:58:57 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:37193) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dmoX7-00039x-2X for qemu-arm@nongnu.org; Tue, 29 Aug 2017 17:58:55 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dmoX4-0006pk-Tv for qemu-arm@nongnu.org; Tue, 29 Aug 2017 17:58:53 -0400 Received: from mail-wr0-x244.google.com ([2a00:1450:400c:c0c::244]:33423) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1dmoX0-0006no-Hi; Tue, 29 Aug 2017 17:58:46 -0400 Received: by mail-wr0-x244.google.com with SMTP id k94so3100688wrc.0; Tue, 29 Aug 2017 14:58:44 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=mime-version:in-reply-to:references:from:date:message-id:subject:to :cc; bh=0mMaRvQMLvANVKS8/1TyDDjz1flSBsv3PqyDI0cY/bM=; b=mXHF0XBbIbbvkgMvcYeb/ZWwZtqjGtVHKJi/sQzZGr9VyQ/FmNKCLVX59wHjypLmzo XPDCnhuABIEkLFhUkuea52hVJZ7jd147aiAZgn65Wt2eiSL5XFmLiMvCFZEd2GYlK718 o0T+wXuKvMlNxkSkYduVFVAFkiPU+hJU2w9YlCy/zDMTKLmjY3xIwo73raf3jBPNV1li ovFGjuCPAVj0cgEDn40odj5dD8DMDeinwGO04masJFiMkuevXJ2WKj3Bmp2cZqcpLZOX f3ZEE2IlEuV0pIFvd4LVqq+9eVLVUguCF/rDlJOK6/wXpNMeZYDMTnHp1ID3UYvWXpdh zIJw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:in-reply-to:references:from:date :message-id:subject:to:cc; bh=0mMaRvQMLvANVKS8/1TyDDjz1flSBsv3PqyDI0cY/bM=; b=skvREKzxfVaQiF1/k/r/Nj44nsYVnlnVTeqWfi2ek25rSbJWEfweN9quoQi9Eb5BL7 UhoCoPu1byQ1HYg3YtivjQoEN8BRVrlsv3iVf3PCT+0g6ZQuX+HYiUlDeeWSce8SLwWR N/nohFiKAoE8o6rc/NNL7SKSql5BjjTNmzFi13eg1JnoSfsfSU4IH6fuB9Ms1tCk/Xym 64ykQd/xqocbqavjIjscpBG6eDgpCZgQdoBkKBtzpTOiyyKyE4Ee6EWwgwxcoc9+NdBP w3RoAqcPIhhNmXDOqDHQ9puZ636ha7bV9ruuBQgnKGE0q/G/kdLH3yjWXuXPe3G7bXhr PIMw== X-Gm-Message-State: AHYfb5gyhCuR+q4WoTR+8hi7IOW4sMnX47oDkQGLsAY8cXbJg/mJvP3c 3gTcez+08I6X71FIdR5aJDVnxYCdUA== X-Received: by 10.223.163.87 with SMTP id d23mr953124wrb.84.1504043923639; Tue, 29 Aug 2017 14:58:43 -0700 (PDT) MIME-Version: 1.0 Received: by 10.28.191.130 with HTTP; Tue, 29 Aug 2017 14:58:12 -0700 (PDT) In-Reply-To: References: <1503938283-12404-1-git-send-email-sundeep.lkml@gmail.com> <1503938283-12404-2-git-send-email-sundeep.lkml@gmail.com> From: Alistair Francis Date: Tue, 29 Aug 2017 14:58:12 -0700 Message-ID: To: sundeep subbaraya Cc: "qemu-devel@nongnu.org Developers" , qemu-arm , Peter Maydell , Peter Crosthwaite , =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= Content-Type: text/plain; charset="UTF-8" X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:400c:c0c::244 Subject: Re: [Qemu-arm] [Qemu devel v7 PATCH 1/5] msf2: Add Smartfusion2 System timer X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 29 Aug 2017 21:58:55 -0000 On Mon, Aug 28, 2017 at 10:32 PM, sundeep subbaraya wrote: > Hi Alistair, > > On Tue, Aug 29, 2017 at 3:23 AM, Alistair Francis > wrote: >> >> On Mon, Aug 28, 2017 at 9:37 AM, Subbaraya Sundeep >> wrote: >> > Modelled System Timer in Microsemi's Smartfusion2 Soc. >> > Timer has two 32bit down counters and two interrupts. >> > >> > Signed-off-by: Subbaraya Sundeep >> >> I had already reviewed this patch in v6. As long as you have made all >> of the changes mentioned their you can add my reviewed-by to the next >> version (as long as there are no other significant changes). >> >> Can you please ensure you do add and keep reviewed-by tags, it's a >> pain to have to do it multiple times. > > > Sorry I was not aware that I can add reviewed by tag myself and send. You can't just add them, but if someone has reviewded your patch you should keep it on that patch. > I will add your reviewed by since I fixed all your comments. > Do I need to send another version v8 with your Reviewed-by ? No it's ok. I'll have a look at the other patches. When you do send a new version just include them then. Thanks, Alistair > > Thanks, > Sundeep > >> >> >> Thanks, >> Alistair >> >> > --- >> > hw/timer/Makefile.objs | 1 + >> > hw/timer/mss-timer.c | 289 >> > +++++++++++++++++++++++++++++++++++++++++++ >> > include/hw/timer/mss-timer.h | 64 ++++++++++ >> > 3 files changed, 354 insertions(+) >> > create mode 100644 hw/timer/mss-timer.c >> > create mode 100644 include/hw/timer/mss-timer.h >> > >> > diff --git a/hw/timer/Makefile.objs b/hw/timer/Makefile.objs >> > index 15cce1c..8c19eac 100644 >> > --- a/hw/timer/Makefile.objs >> > +++ b/hw/timer/Makefile.objs >> > @@ -42,3 +42,4 @@ common-obj-$(CONFIG_ASPEED_SOC) += aspeed_timer.o >> > >> > common-obj-$(CONFIG_SUN4V_RTC) += sun4v-rtc.o >> > common-obj-$(CONFIG_CMSDK_APB_TIMER) += cmsdk-apb-timer.o >> > +common-obj-$(CONFIG_MSF2) += mss-timer.o >> > diff --git a/hw/timer/mss-timer.c b/hw/timer/mss-timer.c >> > new file mode 100644 >> > index 0000000..60f1213 >> > --- /dev/null >> > +++ b/hw/timer/mss-timer.c >> > @@ -0,0 +1,289 @@ >> > +/* >> > + * Block model of System timer present in >> > + * Microsemi's SmartFusion2 and SmartFusion SoCs. >> > + * >> > + * Copyright (c) 2017 Subbaraya Sundeep . >> > + * >> > + * Permission is hereby granted, free of charge, to any person >> > obtaining a copy >> > + * of this software and associated documentation files (the >> > "Software"), to deal >> > + * in the Software without restriction, including without limitation >> > the rights >> > + * to use, copy, modify, merge, publish, distribute, sublicense, and/or >> > sell >> > + * copies of the Software, and to permit persons to whom the Software >> > is >> > + * furnished to do so, subject to the following conditions: >> > + * >> > + * The above copyright notice and this permission notice shall be >> > included in >> > + * all copies or substantial portions of the Software. >> > + * >> > + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, >> > EXPRESS OR >> > + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF >> > MERCHANTABILITY, >> > + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT >> > SHALL >> > + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR >> > OTHER >> > + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, >> > ARISING FROM, >> > + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER >> > DEALINGS IN >> > + * THE SOFTWARE. >> > + */ >> > + >> > +#include "qemu/osdep.h" >> > +#include "qemu/main-loop.h" >> > +#include "qemu/log.h" >> > +#include "hw/timer/mss-timer.h" >> > + >> > +#ifndef MSS_TIMER_ERR_DEBUG >> > +#define MSS_TIMER_ERR_DEBUG 0 >> > +#endif >> > + >> > +#define DB_PRINT_L(lvl, fmt, args...) do { \ >> > + if (MSS_TIMER_ERR_DEBUG >= lvl) { \ >> > + qemu_log("%s: " fmt "\n", __func__, ## args); \ >> > + } \ >> > +} while (0); >> > + >> > +#define DB_PRINT(fmt, args...) DB_PRINT_L(1, fmt, ## args) >> > + >> > +#define R_TIM_VAL 0 >> > +#define R_TIM_LOADVAL 1 >> > +#define R_TIM_BGLOADVAL 2 >> > +#define R_TIM_CTRL 3 >> > +#define R_TIM_RIS 4 >> > +#define R_TIM_MIS 5 >> > + >> > +#define TIMER_CTRL_ENBL (1 << 0) >> > +#define TIMER_CTRL_ONESHOT (1 << 1) >> > +#define TIMER_CTRL_INTR (1 << 2) >> > +#define TIMER_RIS_ACK (1 << 0) >> > +#define TIMER_RST_CLR (1 << 6) >> > +#define TIMER_MODE (1 << 0) >> > + >> > +static void timer_update_irq(struct Msf2Timer *st) >> > +{ >> > + bool isr, ier; >> > + >> > + isr = !!(st->regs[R_TIM_RIS] & TIMER_RIS_ACK); >> > + ier = !!(st->regs[R_TIM_CTRL] & TIMER_CTRL_INTR); >> > + qemu_set_irq(st->irq, (ier && isr)); >> > +} >> > + >> > +static void timer_update(struct Msf2Timer *st) >> > +{ >> > + uint64_t count; >> > + >> > + if (!(st->regs[R_TIM_CTRL] & TIMER_CTRL_ENBL)) { >> > + ptimer_stop(st->ptimer); >> > + return; >> > + } >> > + >> > + count = st->regs[R_TIM_LOADVAL]; >> > + ptimer_set_limit(st->ptimer, count, 1); >> > + ptimer_run(st->ptimer, 1); >> > +} >> > + >> > +static uint64_t >> > +timer_read(void *opaque, hwaddr offset, unsigned int size) >> > +{ >> > + MSSTimerState *t = opaque; >> > + hwaddr addr; >> > + struct Msf2Timer *st; >> > + uint32_t ret = 0; >> > + int timer = 0; >> > + int isr; >> > + int ier; >> > + >> > + addr = offset >> 2; >> > + /* >> > + * Two independent timers has same base address. >> > + * Based on address passed figure out which timer is being used. >> > + */ >> > + if ((addr >= R_TIM1_MAX) && (addr < NUM_TIMERS * R_TIM1_MAX)) { >> > + timer = 1; >> > + addr -= R_TIM1_MAX; >> > + } >> > + >> > + st = &t->timers[timer]; >> > + >> > + switch (addr) { >> > + case R_TIM_VAL: >> > + ret = ptimer_get_count(st->ptimer); >> > + break; >> > + >> > + case R_TIM_MIS: >> > + isr = !!(st->regs[R_TIM_RIS] & TIMER_RIS_ACK); >> > + ier = !!(st->regs[R_TIM_CTRL] & TIMER_CTRL_INTR); >> > + ret = ier & isr; >> > + break; >> > + >> > + default: >> > + if (addr < R_TIM1_MAX) { >> > + ret = st->regs[addr]; >> > + } else { >> > + qemu_log_mask(LOG_GUEST_ERROR, >> > + TYPE_MSS_TIMER": 64-bit mode not supported\n"); >> > + return ret; >> > + } >> > + break; >> > + } >> > + >> > + DB_PRINT("timer=%d 0x%" HWADDR_PRIx "=0x%" PRIx32, timer, offset, >> > + ret); >> > + return ret; >> > +} >> > + >> > +static void >> > +timer_write(void *opaque, hwaddr offset, >> > + uint64_t val64, unsigned int size) >> > +{ >> > + MSSTimerState *t = opaque; >> > + hwaddr addr; >> > + struct Msf2Timer *st; >> > + int timer = 0; >> > + uint32_t value = val64; >> > + >> > + addr = offset >> 2; >> > + /* >> > + * Two independent timers has same base address. >> > + * Based on addr passed figure out which timer is being used. >> > + */ >> > + if ((addr >= R_TIM1_MAX) && (addr < NUM_TIMERS * R_TIM1_MAX)) { >> > + timer = 1; >> > + addr -= R_TIM1_MAX; >> > + } >> > + >> > + st = &t->timers[timer]; >> > + >> > + DB_PRINT("addr=0x%" HWADDR_PRIx " val=0x%" PRIx32 " (timer=%d)", >> > offset, >> > + value, timer); >> > + >> > + switch (addr) { >> > + case R_TIM_CTRL: >> > + st->regs[R_TIM_CTRL] = value; >> > + timer_update(st); >> > + break; >> > + >> > + case R_TIM_RIS: >> > + if (value & TIMER_RIS_ACK) { >> > + st->regs[R_TIM_RIS] &= ~TIMER_RIS_ACK; >> > + } >> > + break; >> > + >> > + case R_TIM_LOADVAL: >> > + st->regs[R_TIM_LOADVAL] = value; >> > + if (st->regs[R_TIM_CTRL] & TIMER_CTRL_ENBL) { >> > + timer_update(st); >> > + } >> > + break; >> > + >> > + case R_TIM_BGLOADVAL: >> > + st->regs[R_TIM_BGLOADVAL] = value; >> > + st->regs[R_TIM_LOADVAL] = value; >> > + break; >> > + >> > + case R_TIM_VAL: >> > + case R_TIM_MIS: >> > + break; >> > + >> > + default: >> > + if (addr < R_TIM1_MAX) { >> > + st->regs[addr] = value; >> > + } else { >> > + qemu_log_mask(LOG_GUEST_ERROR, >> > + TYPE_MSS_TIMER": 64-bit mode not supported\n"); >> > + return; >> > + } >> > + break; >> > + } >> > + timer_update_irq(st); >> > +} >> > + >> > +static const MemoryRegionOps timer_ops = { >> > + .read = timer_read, >> > + .write = timer_write, >> > + .endianness = DEVICE_NATIVE_ENDIAN, >> > + .valid = { >> > + .min_access_size = 1, >> > + .max_access_size = 4 >> > + } >> > +}; >> > + >> > +static void timer_hit(void *opaque) >> > +{ >> > + struct Msf2Timer *st = opaque; >> > + >> > + st->regs[R_TIM_RIS] |= TIMER_RIS_ACK; >> > + >> > + if (!(st->regs[R_TIM_CTRL] & TIMER_CTRL_ONESHOT)) { >> > + timer_update(st); >> > + } >> > + timer_update_irq(st); >> > +} >> > + >> > +static void mss_timer_init(Object *obj) >> > +{ >> > + MSSTimerState *t = MSS_TIMER(obj); >> > + int i; >> > + >> > + /* Init all the ptimers. */ >> > + for (i = 0; i < NUM_TIMERS; i++) { >> > + struct Msf2Timer *st = &t->timers[i]; >> > + >> > + st->bh = qemu_bh_new(timer_hit, st); >> > + st->ptimer = ptimer_init(st->bh, PTIMER_POLICY_DEFAULT); >> > + ptimer_set_freq(st->ptimer, t->freq_hz); >> > + sysbus_init_irq(SYS_BUS_DEVICE(obj), &st->irq); >> > + } >> > + >> > + memory_region_init_io(&t->mmio, OBJECT(t), &timer_ops, t, >> > TYPE_MSS_TIMER, >> > + NUM_TIMERS * R_TIM1_MAX * 4); >> > + sysbus_init_mmio(SYS_BUS_DEVICE(obj), &t->mmio); >> > +} >> > + >> > +static const VMStateDescription vmstate_timers = { >> > + .name = "mss-timer-block", >> > + .version_id = 1, >> > + .minimum_version_id = 1, >> > + .fields = (VMStateField[]) { >> > + VMSTATE_PTIMER(ptimer, struct Msf2Timer), >> > + VMSTATE_UINT32_ARRAY(regs, struct Msf2Timer, R_TIM1_MAX), >> > + VMSTATE_END_OF_LIST() >> > + } >> > +}; >> > + >> > +static const VMStateDescription vmstate_mss_timer = { >> > + .name = TYPE_MSS_TIMER, >> > + .version_id = 1, >> > + .minimum_version_id = 1, >> > + .fields = (VMStateField[]) { >> > + VMSTATE_UINT32(freq_hz, MSSTimerState), >> > + VMSTATE_STRUCT_ARRAY(timers, MSSTimerState, NUM_TIMERS, 0, >> > + vmstate_timers, struct Msf2Timer), >> > + VMSTATE_END_OF_LIST() >> > + } >> > +}; >> > + >> > +static Property mss_timer_properties[] = { >> > + /* Libero GUI shows 100Mhz as default for clocks */ >> > + DEFINE_PROP_UINT32("clock-frequency", MSSTimerState, freq_hz, >> > + 100 * 1000000), >> > + DEFINE_PROP_END_OF_LIST(), >> > +}; >> > + >> > +static void mss_timer_class_init(ObjectClass *klass, void *data) >> > +{ >> > + DeviceClass *dc = DEVICE_CLASS(klass); >> > + >> > + dc->props = mss_timer_properties; >> > + dc->vmsd = &vmstate_mss_timer; >> > +} >> > + >> > +static const TypeInfo mss_timer_info = { >> > + .name = TYPE_MSS_TIMER, >> > + .parent = TYPE_SYS_BUS_DEVICE, >> > + .instance_size = sizeof(MSSTimerState), >> > + .instance_init = mss_timer_init, >> > + .class_init = mss_timer_class_init, >> > +}; >> > + >> > +static void mss_timer_register_types(void) >> > +{ >> > + type_register_static(&mss_timer_info); >> > +} >> > + >> > +type_init(mss_timer_register_types) >> > diff --git a/include/hw/timer/mss-timer.h b/include/hw/timer/mss-timer.h >> > new file mode 100644 >> > index 0000000..d15d173 >> > --- /dev/null >> > +++ b/include/hw/timer/mss-timer.h >> > @@ -0,0 +1,64 @@ >> > +/* >> > + * Microsemi SmartFusion2 Timer. >> > + * >> > + * Copyright (c) 2017 Subbaraya Sundeep >> > + * >> > + * Permission is hereby granted, free of charge, to any person >> > obtaining a copy >> > + * of this software and associated documentation files (the >> > "Software"), to deal >> > + * in the Software without restriction, including without limitation >> > the rights >> > + * to use, copy, modify, merge, publish, distribute, sublicense, and/or >> > sell >> > + * copies of the Software, and to permit persons to whom the Software >> > is >> > + * furnished to do so, subject to the following conditions: >> > + * >> > + * The above copyright notice and this permission notice shall be >> > included in >> > + * all copies or substantial portions of the Software. >> > + * >> > + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, >> > EXPRESS OR >> > + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF >> > MERCHANTABILITY, >> > + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT >> > SHALL >> > + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR >> > OTHER >> > + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, >> > ARISING FROM, >> > + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER >> > DEALINGS IN >> > + * THE SOFTWARE. >> > + */ >> > + >> > +#ifndef HW_MSS_TIMER_H >> > +#define HW_MSS_TIMER_H >> > + >> > +#include "hw/sysbus.h" >> > +#include "hw/ptimer.h" >> > + >> > +#define TYPE_MSS_TIMER "mss-timer" >> > +#define MSS_TIMER(obj) OBJECT_CHECK(MSSTimerState, \ >> > + (obj), TYPE_MSS_TIMER) >> > + >> > +/* >> > + * There are two 32-bit down counting timers. >> > + * Timers 1 and 2 can be concatenated into a single 64-bit Timer >> > + * that operates either in Periodic mode or in One-shot mode. >> > + * Writing 1 to the TIM64_MODE register bit 0 sets the Timers in 64-bit >> > mode. >> > + * In 64-bit mode, writing to the 32-bit registers has no effect. >> > + * Similarly, in 32-bit mode, writing to the 64-bit mode registers >> > + * has no effect. Only two 32-bit timers are supported currently. >> > + */ >> > +#define NUM_TIMERS 2 >> > + >> > +#define R_TIM1_MAX 6 >> > + >> > +struct Msf2Timer { >> > + QEMUBH *bh; >> > + ptimer_state *ptimer; >> > + >> > + uint32_t regs[R_TIM1_MAX]; >> > + qemu_irq irq; >> > +}; >> > + >> > +typedef struct MSSTimerState { >> > + SysBusDevice parent_obj; >> > + >> > + MemoryRegion mmio; >> > + uint32_t freq_hz; >> > + struct Msf2Timer timers[NUM_TIMERS]; >> > +} MSSTimerState; >> > + >> > +#endif /* HW_MSS_TIMER_H */ >> > -- >> > 2.5.0 >> > > > From MAILER-DAEMON Tue Aug 29 23:49:24 2017 Received: from list by lists.gnu.org with archive (Exim 4.71) id 1dmu0K-0003S1-LV for mharc-qemu-arm@gnu.org; Tue, 29 Aug 2017 23:49:24 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:40574) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dmu0E-0003Oy-NN for qemu-arm@nongnu.org; Tue, 29 Aug 2017 23:49:23 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dmu0B-0001JK-DL for qemu-arm@nongnu.org; Tue, 29 Aug 2017 23:49:18 -0400 Received: from mail-qk0-x244.google.com ([2607:f8b0:400d:c09::244]:37346) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1dmu0B-0001J6-6w; Tue, 29 Aug 2017 23:49:15 -0400 Received: by mail-qk0-x244.google.com with SMTP id m4so4443719qke.4; Tue, 29 Aug 2017 20:49:15 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:subject:to:cc:references:from:message-id:date:user-agent :mime-version:in-reply-to:content-language:content-transfer-encoding; bh=wK7jz7uf+bqSfXjQoobZnIBxxkzo76HysDvg4A1B8js=; b=HohycolZlbaXcGdhk57M2hU+SgEH6NHW9vuyiQdSBdVeRN9xYlzu9AXTLHWhNMlkf0 ANpWhksIy7OneOMP6sx6M0kfTav7R0XteWF1Z8KNiKQT0Ri0RHZSYdumQaJVydLEQbLR cuwGhIg0SgEMN2EVgU3aB8u7cS6YQlimmJTYFyVChc6yYXl4zvU5B2MPDJ14IWCBjGiP +uQselExkJ/KYFS44SYKvjXIWbUFrvc6LIKoZA51nOgsXiFUe3dYWin+EQG8zrALdCoa k6bxI2FNaA0ECx2Sbm8zAurszDEx52o5xFC0QGGmG1zY1MbN9S1CL4svV7iPjCDfXGmO KISQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:subject:to:cc:references:from:message-id :date:user-agent:mime-version:in-reply-to:content-language :content-transfer-encoding; bh=wK7jz7uf+bqSfXjQoobZnIBxxkzo76HysDvg4A1B8js=; b=Qrg3GFBl1q2r/fDAEECuIxAeDEGeoeDXv1skVyqxvRfhLMNnLXsioafmNnejd0dG1R glGf0WdqB+b91oqCtaYkAVh5cjDaocR+ykrvSak3qmlOI73cHJssGa+2TAML3xQkS3Kq mpIq64tUqgSZvRGy3U5OeOaac/eitWadD2iEL+x7F7cyoqvOgZYFfzQt2PZMywzoJq19 yKq6hX7Kxcaf7c5baQXu18UHBpXBtr8ARJ2NUFQWtMbQSuhXx6X3DCWPFPQClmP+gAGG FJJobRL6Hch9zIq3fIidVv9h9DNadyrQmkIJBS17432UchZnqQMmDhKSjzGkU+PMok7K 7bSQ== X-Gm-Message-State: AHYfb5hTpSgxp9H0AidagzCI7qW+ZPeaBj0Wh6XipUmdCN3/McbiapIr vGUGQUhj3CGolkJMtPZo7w== X-Received: by 10.55.20.212 with SMTP id 81mr8211762qku.213.1504064954214; Tue, 29 Aug 2017 20:49:14 -0700 (PDT) Received: from [192.168.43.33] ([170.51.33.248]) by smtp.gmail.com with ESMTPSA id 20sm3062981qtu.52.2017.08.29.20.49.11 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 29 Aug 2017 20:49:13 -0700 (PDT) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= To: Richard Henderson , qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, alex.bennee@linaro.org References: <20170817230114.3655-1-richard.henderson@linaro.org> <20170817230114.3655-2-richard.henderson@linaro.org> From: =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= Message-ID: Date: Tue, 29 Aug 2017 22:31:40 -0300 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.3.0 MIME-Version: 1.0 In-Reply-To: <20170817230114.3655-2-richard.henderson@linaro.org> Content-Type: text/plain; charset=utf-8; format=flowed Content-Language: en-US Content-Transfer-Encoding: 8bit X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400d:c09::244 Subject: Re: [Qemu-arm] [Qemu-devel] [PATCH 1/8] tcg: Add generic vector infrastructure and ops for add/sub/logic X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 30 Aug 2017 03:49:23 -0000 Hi Richard, I can't find anything to say about this patch... Hardcore stuff. Some part could be more a bit more verbose but after a while focusing it makes sens. I wonder how long it took you to write this :) "roughly 2h" On 08/17/2017 08:01 PM, Richard Henderson wrote: > Signed-off-by: Richard Henderson Hoping I didn't miss anything: Reviewed-by: Philippe Mathieu-Daudé > --- > Makefile.target | 5 +- > tcg/tcg-op-gvec.h | 88 ++++++++++ > tcg/tcg-runtime.h | 16 ++ > tcg/tcg-op-gvec.c | 443 +++++++++++++++++++++++++++++++++++++++++++++++++ > tcg/tcg-runtime-gvec.c | 199 ++++++++++++++++++++++ > 5 files changed, 749 insertions(+), 2 deletions(-) > create mode 100644 tcg/tcg-op-gvec.h > create mode 100644 tcg/tcg-op-gvec.c > create mode 100644 tcg/tcg-runtime-gvec.c > > diff --git a/Makefile.target b/Makefile.target > index 7f42c45db8..9ae3e904f7 100644 > --- a/Makefile.target > +++ b/Makefile.target > @@ -93,8 +93,9 @@ all: $(PROGS) stap > # cpu emulator library > obj-y += exec.o > obj-y += accel/ > -obj-$(CONFIG_TCG) += tcg/tcg.o tcg/tcg-op.o tcg/optimize.o > -obj-$(CONFIG_TCG) += tcg/tcg-common.o tcg/tcg-runtime.o > +obj-$(CONFIG_TCG) += tcg/tcg.o tcg/tcg-common.o tcg/optimize.o > +obj-$(CONFIG_TCG) += tcg/tcg-op.o tcg/tcg-op-gvec.o > +obj-$(CONFIG_TCG) += tcg/tcg-runtime.o tcg/tcg-runtime-gvec.o > obj-$(CONFIG_TCG_INTERPRETER) += tcg/tci.o > obj-$(CONFIG_TCG_INTERPRETER) += disas/tci.o > obj-y += fpu/softfloat.o > diff --git a/tcg/tcg-op-gvec.h b/tcg/tcg-op-gvec.h > new file mode 100644 > index 0000000000..10db3599a5 > --- /dev/null > +++ b/tcg/tcg-op-gvec.h > @@ -0,0 +1,88 @@ > +/* > + * Generic vector operation expansion > + * > + * Copyright (c) 2017 Linaro > + * > + * This library is free software; you can redistribute it and/or > + * modify it under the terms of the GNU Lesser General Public > + * License as published by the Free Software Foundation; either > + * version 2 of the License, or (at your option) any later version. > + * > + * This library is distributed in the hope that it will be useful, > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU > + * Lesser General Public License for more details. > + * > + * You should have received a copy of the GNU Lesser General Public > + * License along with this library; if not, see . > + */ > + > +/* > + * "Generic" vectors. All operands are given as offsets from ENV, > + * and therefore cannot also be allocated via tcg_global_mem_new_*. > + * OPSZ is the byte size of the vector upon which the operation is performed. > + * CLSZ is the byte size of the full vector; bytes beyond OPSZ are cleared. > + * > + * All sizes must be 8 or any multiple of 16. > + * When OPSZ is 8, the alignment may be 8, otherwise must be 16. > + * Operands may completely, but not partially, overlap. > + */ > + > +/* Fundamental operation expanders. These are exposed to the front ends > + so that target-specific SIMD operations can be handled similarly to > + the standard SIMD operations. */ > + > +typedef struct { > + /* "Small" sizes: expand inline as a 64-bit or 32-bit lane. > + Generally only one of these will be non-NULL. */ > + void (*fni8)(TCGv_i64, TCGv_i64, TCGv_i64); > + void (*fni4)(TCGv_i32, TCGv_i32, TCGv_i32); > + /* Similarly, but load up a constant and re-use across lanes. */ > + void (*fni8x)(TCGv_i64, TCGv_i64, TCGv_i64, TCGv_i64); > + uint64_t extra_value; > + /* Larger sizes: expand out-of-line helper w/size descriptor. */ > + void (*fno)(TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_i32); > +} GVecGen3; > + > +void tcg_gen_gvec_3(uint32_t dofs, uint32_t aofs, uint32_t bofs, > + uint32_t opsz, uint32_t clsz, const GVecGen3 *); > + > +#define DEF_GVEC_2(X) \ > + void tcg_gen_gvec_##X(uint32_t dofs, uint32_t aofs, uint32_t bofs, \ > + uint32_t opsz, uint32_t clsz) > + > +DEF_GVEC_2(add8); > +DEF_GVEC_2(add16); > +DEF_GVEC_2(add32); > +DEF_GVEC_2(add64); > + > +DEF_GVEC_2(sub8); > +DEF_GVEC_2(sub16); > +DEF_GVEC_2(sub32); > +DEF_GVEC_2(sub64); > + > +DEF_GVEC_2(and8); > +DEF_GVEC_2(or8); > +DEF_GVEC_2(xor8); > +DEF_GVEC_2(andc8); > +DEF_GVEC_2(orc8); > + > +#undef DEF_GVEC_2 > + > +/* > + * 64-bit vector operations. Use these when the register has been > + * allocated with tcg_global_mem_new_i64. OPSZ = CLSZ = 8. > + */ > + > +#define DEF_VEC8_2(X) \ > + void tcg_gen_vec8_##X(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b) > + > +DEF_VEC8_2(add8); > +DEF_VEC8_2(add16); > +DEF_VEC8_2(add32); > + > +DEF_VEC8_2(sub8); > +DEF_VEC8_2(sub16); > +DEF_VEC8_2(sub32); > + > +#undef DEF_VEC8_2 > diff --git a/tcg/tcg-runtime.h b/tcg/tcg-runtime.h > index c41d38a557..f8d07090f8 100644 > --- a/tcg/tcg-runtime.h > +++ b/tcg/tcg-runtime.h > @@ -134,3 +134,19 @@ GEN_ATOMIC_HELPERS(xor_fetch) > GEN_ATOMIC_HELPERS(xchg) > > #undef GEN_ATOMIC_HELPERS > + > +DEF_HELPER_FLAGS_4(gvec_add8, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) > +DEF_HELPER_FLAGS_4(gvec_add16, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) > +DEF_HELPER_FLAGS_4(gvec_add32, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) > +DEF_HELPER_FLAGS_4(gvec_add64, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) > + > +DEF_HELPER_FLAGS_4(gvec_sub8, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) > +DEF_HELPER_FLAGS_4(gvec_sub16, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) > +DEF_HELPER_FLAGS_4(gvec_sub32, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) > +DEF_HELPER_FLAGS_4(gvec_sub64, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) > + > +DEF_HELPER_FLAGS_4(gvec_and8, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) > +DEF_HELPER_FLAGS_4(gvec_or8, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) > +DEF_HELPER_FLAGS_4(gvec_xor8, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) > +DEF_HELPER_FLAGS_4(gvec_andc8, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) > +DEF_HELPER_FLAGS_4(gvec_orc8, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) > diff --git a/tcg/tcg-op-gvec.c b/tcg/tcg-op-gvec.c > new file mode 100644 > index 0000000000..6de49dc07f > --- /dev/null > +++ b/tcg/tcg-op-gvec.c > @@ -0,0 +1,443 @@ > +/* > + * Generic vector operation expansion > + * > + * Copyright (c) 2017 Linaro > + * > + * This library is free software; you can redistribute it and/or > + * modify it under the terms of the GNU Lesser General Public > + * License as published by the Free Software Foundation; either > + * version 2 of the License, or (at your option) any later version. > + * > + * This library is distributed in the hope that it will be useful, > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU > + * Lesser General Public License for more details. > + * > + * You should have received a copy of the GNU Lesser General Public > + * License along with this library; if not, see . > + */ > + > +#include "qemu/osdep.h" > +#include "qemu-common.h" > +#include "cpu.h" > +#include "exec/exec-all.h" > +#include "tcg.h" > +#include "tcg-op.h" > +#include "tcg-op-gvec.h" > +#include "trace-tcg.h" > +#include "trace/mem.h" > + > +#define REP8(x) ((x) * 0x0101010101010101ull) > +#define REP16(x) ((x) * 0x0001000100010001ull) > + > +#define MAX_INLINE 16 > + > +static inline void check_size_s(uint32_t opsz, uint32_t clsz) > +{ > + tcg_debug_assert(opsz % 8 == 0); > + tcg_debug_assert(clsz % 8 == 0); > + tcg_debug_assert(opsz <= clsz); > +} > + > +static inline void check_align_s_3(uint32_t dofs, uint32_t aofs, uint32_t bofs) > +{ > + tcg_debug_assert(dofs % 8 == 0); > + tcg_debug_assert(aofs % 8 == 0); > + tcg_debug_assert(bofs % 8 == 0); > +} > + > +static inline void check_size_l(uint32_t opsz, uint32_t clsz) > +{ > + tcg_debug_assert(opsz % 16 == 0); > + tcg_debug_assert(clsz % 16 == 0); > + tcg_debug_assert(opsz <= clsz); > +} > + > +static inline void check_align_l_3(uint32_t dofs, uint32_t aofs, uint32_t bofs) > +{ > + tcg_debug_assert(dofs % 16 == 0); > + tcg_debug_assert(aofs % 16 == 0); > + tcg_debug_assert(bofs % 16 == 0); > +} > + > +static inline void check_overlap_3(uint32_t d, uint32_t a, > + uint32_t b, uint32_t s) > +{ > + tcg_debug_assert(d == a || d + s <= a || a + s <= d); > + tcg_debug_assert(d == b || d + s <= b || b + s <= d); > + tcg_debug_assert(a == b || a + s <= b || b + s <= a); > +} > + > +static void expand_clr(uint32_t dofs, uint32_t opsz, uint32_t clsz) > +{ > + if (clsz > opsz) { > + TCGv_i64 zero = tcg_const_i64(0); > + uint32_t i; > + > + for (i = opsz; i < clsz; i += 8) { > + tcg_gen_st_i64(zero, tcg_ctx.tcg_env, dofs + i); > + } > + tcg_temp_free_i64(zero); > + } > +} > + > +static TCGv_i32 make_desc(uint32_t opsz, uint32_t clsz) > +{ > + tcg_debug_assert(opsz >= 16 && opsz <= 255 * 16 && opsz % 16 == 0); > + tcg_debug_assert(clsz >= 16 && clsz <= 255 * 16 && clsz % 16 == 0); > + opsz /= 16; > + clsz /= 16; > + opsz -= 1; > + clsz -= 1; > + return tcg_const_i32(deposit32(opsz, 8, 8, clsz)); > +} > + > +static void expand_3_o(uint32_t dofs, uint32_t aofs, uint32_t bofs, > + uint32_t opsz, uint32_t clsz, > + void (*fno)(TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_i32)) > +{ > + TCGv_ptr d = tcg_temp_new_ptr(); > + TCGv_ptr a = tcg_temp_new_ptr(); > + TCGv_ptr b = tcg_temp_new_ptr(); > + TCGv_i32 desc = make_desc(opsz, clsz); > + > + tcg_gen_addi_ptr(d, tcg_ctx.tcg_env, dofs); > + tcg_gen_addi_ptr(a, tcg_ctx.tcg_env, aofs); > + tcg_gen_addi_ptr(b, tcg_ctx.tcg_env, bofs); > + fno(d, a, b, desc); > + > + tcg_temp_free_ptr(d); > + tcg_temp_free_ptr(a); > + tcg_temp_free_ptr(b); > + tcg_temp_free_i32(desc); > +} > + > +static void expand_3x4(uint32_t dofs, uint32_t aofs, > + uint32_t bofs, uint32_t opsz, > + void (*fni)(TCGv_i32, TCGv_i32, TCGv_i32)) > +{ > + TCGv_i32 t0 = tcg_temp_new_i32(); > + uint32_t i; > + > + if (aofs == bofs) { > + for (i = 0; i < opsz; i += 4) { > + tcg_gen_ld_i32(t0, tcg_ctx.tcg_env, aofs + i); > + fni(t0, t0, t0); > + tcg_gen_st_i32(t0, tcg_ctx.tcg_env, dofs + i); > + } > + } else { > + TCGv_i32 t1 = tcg_temp_new_i32(); > + for (i = 0; i < opsz; i += 4) { > + tcg_gen_ld_i32(t0, tcg_ctx.tcg_env, aofs + i); > + tcg_gen_ld_i32(t1, tcg_ctx.tcg_env, bofs + i); > + fni(t0, t0, t1); > + tcg_gen_st_i32(t0, tcg_ctx.tcg_env, dofs + i); > + } > + tcg_temp_free_i32(t1); > + } > + tcg_temp_free_i32(t0); > +} > + > +static void expand_3x8(uint32_t dofs, uint32_t aofs, > + uint32_t bofs, uint32_t opsz, > + void (*fni)(TCGv_i64, TCGv_i64, TCGv_i64)) > +{ > + TCGv_i64 t0 = tcg_temp_new_i64(); > + uint32_t i; > + > + if (aofs == bofs) { > + for (i = 0; i < opsz; i += 8) { > + tcg_gen_ld_i64(t0, tcg_ctx.tcg_env, aofs + i); > + fni(t0, t0, t0); > + tcg_gen_st_i64(t0, tcg_ctx.tcg_env, dofs + i); > + } > + } else { > + TCGv_i64 t1 = tcg_temp_new_i64(); > + for (i = 0; i < opsz; i += 8) { > + tcg_gen_ld_i64(t0, tcg_ctx.tcg_env, aofs + i); > + tcg_gen_ld_i64(t1, tcg_ctx.tcg_env, bofs + i); > + fni(t0, t0, t1); > + tcg_gen_st_i64(t0, tcg_ctx.tcg_env, dofs + i); > + } > + tcg_temp_free_i64(t1); > + } > + tcg_temp_free_i64(t0); > +} > + > +static void expand_3x8p1(uint32_t dofs, uint32_t aofs, uint32_t bofs, > + uint32_t opsz, uint64_t data, > + void (*fni)(TCGv_i64, TCGv_i64, TCGv_i64, TCGv_i64)) > +{ > + TCGv_i64 t0 = tcg_temp_new_i64(); > + TCGv_i64 t2 = tcg_const_i64(data); > + uint32_t i; > + > + if (aofs == bofs) { > + for (i = 0; i < opsz; i += 8) { > + tcg_gen_ld_i64(t0, tcg_ctx.tcg_env, aofs + i); > + fni(t0, t0, t0, t2); > + tcg_gen_st_i64(t0, tcg_ctx.tcg_env, dofs + i); > + } > + } else { > + TCGv_i64 t1 = tcg_temp_new_i64(); > + for (i = 0; i < opsz; i += 8) { > + tcg_gen_ld_i64(t0, tcg_ctx.tcg_env, aofs + i); > + tcg_gen_ld_i64(t1, tcg_ctx.tcg_env, bofs + i); > + fni(t0, t0, t1, t2); > + tcg_gen_st_i64(t0, tcg_ctx.tcg_env, dofs + i); > + } > + tcg_temp_free_i64(t1); > + } > + tcg_temp_free_i64(t0); > + tcg_temp_free_i64(t2); > +} > + > +void tcg_gen_gvec_3(uint32_t dofs, uint32_t aofs, uint32_t bofs, > + uint32_t opsz, uint32_t clsz, const GVecGen3 *g) > +{ > + check_overlap_3(dofs, aofs, bofs, clsz); > + if (opsz <= MAX_INLINE) { > + check_size_s(opsz, clsz); > + check_align_s_3(dofs, aofs, bofs); > + if (g->fni8) { > + expand_3x8(dofs, aofs, bofs, opsz, g->fni8); > + } else if (g->fni4) { > + expand_3x4(dofs, aofs, bofs, opsz, g->fni4); > + } else if (g->fni8x) { > + expand_3x8p1(dofs, aofs, bofs, opsz, g->extra_value, g->fni8x); > + } else { > + g_assert_not_reached(); > + } > + expand_clr(dofs, opsz, clsz); > + } else { > + check_size_l(opsz, clsz); > + check_align_l_3(dofs, aofs, bofs); > + expand_3_o(dofs, aofs, bofs, opsz, clsz, g->fno); > + } > +} > + > +static void gen_addv_mask(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b, TCGv_i64 m) > +{ > + TCGv_i64 t1 = tcg_temp_new_i64(); > + TCGv_i64 t2 = tcg_temp_new_i64(); > + TCGv_i64 t3 = tcg_temp_new_i64(); > + > + tcg_gen_andc_i64(t1, a, m); > + tcg_gen_andc_i64(t2, b, m); > + tcg_gen_xor_i64(t3, a, b); > + tcg_gen_add_i64(d, t1, t2); > + tcg_gen_and_i64(t3, t3, m); > + tcg_gen_xor_i64(d, d, t3); > + > + tcg_temp_free_i64(t1); > + tcg_temp_free_i64(t2); > + tcg_temp_free_i64(t3); > +} > + > +void tcg_gen_gvec_add8(uint32_t dofs, uint32_t aofs, uint32_t bofs, > + uint32_t opsz, uint32_t clsz) > +{ > + static const GVecGen3 g = { > + .extra_value = REP8(0x80), > + .fni8x = gen_addv_mask, > + .fno = gen_helper_gvec_add8, > + }; > + tcg_gen_gvec_3(dofs, aofs, bofs, opsz, clsz, &g); > +} > + > +void tcg_gen_gvec_add16(uint32_t dofs, uint32_t aofs, uint32_t bofs, > + uint32_t opsz, uint32_t clsz) > +{ > + static const GVecGen3 g = { > + .extra_value = REP16(0x8000), > + .fni8x = gen_addv_mask, > + .fno = gen_helper_gvec_add16, > + }; > + tcg_gen_gvec_3(dofs, aofs, bofs, opsz, clsz, &g); > +} > + > +void tcg_gen_gvec_add32(uint32_t dofs, uint32_t aofs, uint32_t bofs, > + uint32_t opsz, uint32_t clsz) > +{ > + static const GVecGen3 g = { > + .fni4 = tcg_gen_add_i32, > + .fno = gen_helper_gvec_add32, > + }; > + tcg_gen_gvec_3(dofs, aofs, bofs, opsz, clsz, &g); > +} > + > +void tcg_gen_gvec_add64(uint32_t dofs, uint32_t aofs, uint32_t bofs, > + uint32_t opsz, uint32_t clsz) > +{ > + static const GVecGen3 g = { > + .fni8 = tcg_gen_add_i64, > + .fno = gen_helper_gvec_add64, > + }; > + tcg_gen_gvec_3(dofs, aofs, bofs, opsz, clsz, &g); > +} > + > +void tcg_gen_vec8_add8(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b) > +{ > + TCGv_i64 m = tcg_const_i64(REP8(0x80)); > + gen_addv_mask(d, a, b, m); > + tcg_temp_free_i64(m); > +} > + > +void tcg_gen_vec8_add16(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b) > +{ > + TCGv_i64 m = tcg_const_i64(REP16(0x8000)); > + gen_addv_mask(d, a, b, m); > + tcg_temp_free_i64(m); > +} > + > +void tcg_gen_vec8_add32(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b) > +{ > + TCGv_i64 t1 = tcg_temp_new_i64(); > + TCGv_i64 t2 = tcg_temp_new_i64(); > + > + tcg_gen_andi_i64(t1, a, ~0xffffffffull); > + tcg_gen_add_i64(t2, a, b); > + tcg_gen_add_i64(t1, t1, b); > + tcg_gen_deposit_i64(d, t1, t2, 0, 32); > + > + tcg_temp_free_i64(t1); > + tcg_temp_free_i64(t2); > +} > + > +static void gen_subv_mask(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b, TCGv_i64 m) > +{ > + TCGv_i64 t1 = tcg_temp_new_i64(); > + TCGv_i64 t2 = tcg_temp_new_i64(); > + TCGv_i64 t3 = tcg_temp_new_i64(); > + > + tcg_gen_or_i64(t1, a, m); > + tcg_gen_andc_i64(t2, b, m); > + tcg_gen_eqv_i64(t3, a, b); > + tcg_gen_sub_i64(d, t1, t2); > + tcg_gen_and_i64(t3, t3, m); > + tcg_gen_xor_i64(d, d, t3); > + > + tcg_temp_free_i64(t1); > + tcg_temp_free_i64(t2); > + tcg_temp_free_i64(t3); > +} > + > +void tcg_gen_gvec_sub8(uint32_t dofs, uint32_t aofs, uint32_t bofs, > + uint32_t opsz, uint32_t clsz) > +{ > + static const GVecGen3 g = { > + .extra_value = REP8(0x80), > + .fni8x = gen_subv_mask, > + .fno = gen_helper_gvec_sub8, > + }; > + tcg_gen_gvec_3(dofs, aofs, bofs, opsz, clsz, &g); > +} > + > +void tcg_gen_gvec_sub16(uint32_t dofs, uint32_t aofs, uint32_t bofs, > + uint32_t opsz, uint32_t clsz) > +{ > + static const GVecGen3 g = { > + .extra_value = REP16(0x8000), > + .fni8x = gen_subv_mask, > + .fno = gen_helper_gvec_sub16, > + }; > + tcg_gen_gvec_3(dofs, aofs, bofs, opsz, clsz, &g); > +} > + > +void tcg_gen_gvec_sub32(uint32_t dofs, uint32_t aofs, uint32_t bofs, > + uint32_t opsz, uint32_t clsz) > +{ > + static const GVecGen3 g = { > + .fni4 = tcg_gen_sub_i32, > + .fno = gen_helper_gvec_sub32, > + }; > + tcg_gen_gvec_3(dofs, aofs, bofs, opsz, clsz, &g); > +} > + > +void tcg_gen_gvec_sub64(uint32_t dofs, uint32_t aofs, uint32_t bofs, > + uint32_t opsz, uint32_t clsz) > +{ > + static const GVecGen3 g = { > + .fni8 = tcg_gen_sub_i64, > + .fno = gen_helper_gvec_sub64, > + }; > + tcg_gen_gvec_3(dofs, aofs, bofs, opsz, clsz, &g); > +} > + > +void tcg_gen_vec8_sub8(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b) > +{ > + TCGv_i64 m = tcg_const_i64(REP8(0x80)); > + gen_subv_mask(d, a, b, m); > + tcg_temp_free_i64(m); > +} > + > +void tcg_gen_vec8_sub16(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b) > +{ > + TCGv_i64 m = tcg_const_i64(REP16(0x8000)); > + gen_subv_mask(d, a, b, m); > + tcg_temp_free_i64(m); > +} > + > +void tcg_gen_vec8_sub32(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b) > +{ > + TCGv_i64 t1 = tcg_temp_new_i64(); > + TCGv_i64 t2 = tcg_temp_new_i64(); > + > + tcg_gen_andi_i64(t1, b, ~0xffffffffull); > + tcg_gen_sub_i64(t2, a, b); > + tcg_gen_sub_i64(t1, a, t1); > + tcg_gen_deposit_i64(d, t1, t2, 0, 32); > + > + tcg_temp_free_i64(t1); > + tcg_temp_free_i64(t2); > +} > + > +void tcg_gen_gvec_and8(uint32_t dofs, uint32_t aofs, uint32_t bofs, > + uint32_t opsz, uint32_t clsz) > +{ > + static const GVecGen3 g = { > + .fni8 = tcg_gen_and_i64, > + .fno = gen_helper_gvec_and8, > + }; > + tcg_gen_gvec_3(dofs, aofs, bofs, opsz, clsz, &g); > +} > + > +void tcg_gen_gvec_or8(uint32_t dofs, uint32_t aofs, uint32_t bofs, > + uint32_t opsz, uint32_t clsz) > +{ > + static const GVecGen3 g = { > + .fni8 = tcg_gen_or_i64, > + .fno = gen_helper_gvec_or8, > + }; > + tcg_gen_gvec_3(dofs, aofs, bofs, opsz, clsz, &g); > +} > + > +void tcg_gen_gvec_xor8(uint32_t dofs, uint32_t aofs, uint32_t bofs, > + uint32_t opsz, uint32_t clsz) > +{ > + static const GVecGen3 g = { > + .fni8 = tcg_gen_xor_i64, > + .fno = gen_helper_gvec_xor8, > + }; > + tcg_gen_gvec_3(dofs, aofs, bofs, opsz, clsz, &g); > +} > + > +void tcg_gen_gvec_andc8(uint32_t dofs, uint32_t aofs, uint32_t bofs, > + uint32_t opsz, uint32_t clsz) > +{ > + static const GVecGen3 g = { > + .fni8 = tcg_gen_andc_i64, > + .fno = gen_helper_gvec_andc8, > + }; > + tcg_gen_gvec_3(dofs, aofs, bofs, opsz, clsz, &g); > +} > + > +void tcg_gen_gvec_orc8(uint32_t dofs, uint32_t aofs, uint32_t bofs, > + uint32_t opsz, uint32_t clsz) > +{ > + static const GVecGen3 g = { > + .fni8 = tcg_gen_orc_i64, > + .fno = gen_helper_gvec_orc8, > + }; > + tcg_gen_gvec_3(dofs, aofs, bofs, opsz, clsz, &g); > +} > diff --git a/tcg/tcg-runtime-gvec.c b/tcg/tcg-runtime-gvec.c > new file mode 100644 > index 0000000000..9a37ce07a2 > --- /dev/null > +++ b/tcg/tcg-runtime-gvec.c > @@ -0,0 +1,199 @@ > +/* > + * Generic vectorized operation runtime > + * > + * Copyright (c) 2017 Linaro > + * > + * This library is free software; you can redistribute it and/or > + * modify it under the terms of the GNU Lesser General Public > + * License as published by the Free Software Foundation; either > + * version 2 of the License, or (at your option) any later version. > + * > + * This library is distributed in the hope that it will be useful, > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU > + * Lesser General Public License for more details. > + * > + * You should have received a copy of the GNU Lesser General Public > + * License along with this library; if not, see . > + */ > + > +#include "qemu/osdep.h" > +#include "qemu/host-utils.h" > +#include "cpu.h" > +#include "exec/helper-proto.h" > + > +/* Virtually all hosts support 16-byte vectors. Those that don't > + can emulate them via GCC's generic vector extension. > + > + In tcg-op-gvec.c, we asserted that both the size and alignment > + of the data are multiples of 16. */ > + > +typedef uint8_t vec8 __attribute__((vector_size(16))); > +typedef uint16_t vec16 __attribute__((vector_size(16))); > +typedef uint32_t vec32 __attribute__((vector_size(16))); > +typedef uint64_t vec64 __attribute__((vector_size(16))); > + > +static inline intptr_t extract_opsz(uint32_t desc) > +{ > + return ((desc & 0xff) + 1) * 16; > +} > + > +static inline intptr_t extract_clsz(uint32_t desc) > +{ > + return (((desc >> 8) & 0xff) + 1) * 16; > +} > + > +static inline void clear_high(void *d, intptr_t opsz, uint32_t desc) > +{ > + intptr_t clsz = extract_clsz(desc); > + intptr_t i; > + > + if (unlikely(clsz > opsz)) { > + for (i = opsz; i < clsz; i += sizeof(vec64)) { > + *(vec64 *)(d + i) = (vec64){ 0 }; > + } > + } > +} > + > +void HELPER(gvec_add8)(void *d, void *a, void *b, uint32_t desc) > +{ > + intptr_t opsz = extract_opsz(desc); > + intptr_t i; > + > + for (i = 0; i < opsz; i += sizeof(vec8)) { > + *(vec8 *)(d + i) = *(vec8 *)(a + i) + *(vec8 *)(b + i); > + } > + clear_high(d, opsz, desc); > +} > + > +void HELPER(gvec_add16)(void *d, void *a, void *b, uint32_t desc) > +{ > + intptr_t opsz = extract_opsz(desc); > + intptr_t i; > + > + for (i = 0; i < opsz; i += sizeof(vec16)) { > + *(vec16 *)(d + i) = *(vec16 *)(a + i) + *(vec16 *)(b + i); > + } > + clear_high(d, opsz, desc); > +} > + > +void HELPER(gvec_add32)(void *d, void *a, void *b, uint32_t desc) > +{ > + intptr_t opsz = extract_opsz(desc); > + intptr_t i; > + > + for (i = 0; i < opsz; i += sizeof(vec32)) { > + *(vec32 *)(d + i) = *(vec32 *)(a + i) + *(vec32 *)(b + i); > + } > + clear_high(d, opsz, desc); > +} > + > +void HELPER(gvec_add64)(void *d, void *a, void *b, uint32_t desc) > +{ > + intptr_t opsz = extract_opsz(desc); > + intptr_t i; > + > + for (i = 0; i < opsz; i += sizeof(vec64)) { > + *(vec64 *)(d + i) = *(vec64 *)(a + i) + *(vec64 *)(b + i); > + } > + clear_high(d, opsz, desc); > +} > + > +void HELPER(gvec_sub8)(void *d, void *a, void *b, uint32_t desc) > +{ > + intptr_t opsz = extract_opsz(desc); > + intptr_t i; > + > + for (i = 0; i < opsz; i += sizeof(vec8)) { > + *(vec8 *)(d + i) = *(vec8 *)(a + i) - *(vec8 *)(b + i); > + } > + clear_high(d, opsz, desc); > +} > + > +void HELPER(gvec_sub16)(void *d, void *a, void *b, uint32_t desc) > +{ > + intptr_t opsz = extract_opsz(desc); > + intptr_t i; > + > + for (i = 0; i < opsz; i += sizeof(vec16)) { > + *(vec16 *)(d + i) = *(vec16 *)(a + i) - *(vec16 *)(b + i); > + } > + clear_high(d, opsz, desc); > +} > + > +void HELPER(gvec_sub32)(void *d, void *a, void *b, uint32_t desc) > +{ > + intptr_t opsz = extract_opsz(desc); > + intptr_t i; > + > + for (i = 0; i < opsz; i += sizeof(vec32)) { > + *(vec32 *)(d + i) = *(vec32 *)(a + i) - *(vec32 *)(b + i); > + } > + clear_high(d, opsz, desc); > +} > + > +void HELPER(gvec_sub64)(void *d, void *a, void *b, uint32_t desc) > +{ > + intptr_t opsz = extract_opsz(desc); > + intptr_t i; > + > + for (i = 0; i < opsz; i += sizeof(vec64)) { > + *(vec64 *)(d + i) = *(vec64 *)(a + i) - *(vec64 *)(b + i); > + } > + clear_high(d, opsz, desc); > +} > + > +void HELPER(gvec_and8)(void *d, void *a, void *b, uint32_t desc) > +{ > + intptr_t opsz = extract_opsz(desc); > + intptr_t i; > + > + for (i = 0; i < opsz; i += sizeof(vec64)) { > + *(vec64 *)(d + i) = *(vec64 *)(a + i) & *(vec64 *)(b + i); > + } > + clear_high(d, opsz, desc); > +} > + > +void HELPER(gvec_or8)(void *d, void *a, void *b, uint32_t desc) > +{ > + intptr_t opsz = extract_opsz(desc); > + intptr_t i; > + > + for (i = 0; i < opsz; i += sizeof(vec64)) { > + *(vec64 *)(d + i) = *(vec64 *)(a + i) | *(vec64 *)(b + i); > + } > + clear_high(d, opsz, desc); > +} > + > +void HELPER(gvec_xor8)(void *d, void *a, void *b, uint32_t desc) > +{ > + intptr_t opsz = extract_opsz(desc); > + intptr_t i; > + > + for (i = 0; i < opsz; i += sizeof(vec64)) { > + *(vec64 *)(d + i) = *(vec64 *)(a + i) ^ *(vec64 *)(b + i); > + } > + clear_high(d, opsz, desc); > +} > + > +void HELPER(gvec_andc8)(void *d, void *a, void *b, uint32_t desc) > +{ > + intptr_t opsz = extract_opsz(desc); > + intptr_t i; > + > + for (i = 0; i < opsz; i += sizeof(vec64)) { > + *(vec64 *)(d + i) = *(vec64 *)(a + i) &~ *(vec64 *)(b + i); > + } > + clear_high(d, opsz, desc); > +} > + > +void HELPER(gvec_orc8)(void *d, void *a, void *b, uint32_t desc) > +{ > + intptr_t opsz = extract_opsz(desc); > + intptr_t i; > + > + for (i = 0; i < opsz; i += sizeof(vec64)) { > + *(vec64 *)(d + i) = *(vec64 *)(a + i) |~ *(vec64 *)(b + i); > + } > + clear_high(d, opsz, desc); > +} > From MAILER-DAEMON Tue Aug 29 23:49:28 2017 Received: from list by lists.gnu.org with archive (Exim 4.71) id 1dmu0N-0003Uj-T3 for mharc-qemu-arm@gnu.org; Tue, 29 Aug 2017 23:49:27 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:40604) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dmu0L-0003So-DN for qemu-arm@nongnu.org; Tue, 29 Aug 2017 23:49:26 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dmu0G-0001LU-Nn for qemu-arm@nongnu.org; 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Tue, 29 Aug 2017 20:49:19 -0700 (PDT) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= To: Richard Henderson , qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, alex.bennee@linaro.org References: <20170817230114.3655-1-richard.henderson@linaro.org> <20170817230114.3655-5-richard.henderson@linaro.org> From: =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= Message-ID: Date: Tue, 29 Aug 2017 22:34:01 -0300 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.3.0 MIME-Version: 1.0 In-Reply-To: <20170817230114.3655-5-richard.henderson@linaro.org> Content-Type: text/plain; charset=utf-8; format=flowed Content-Language: en-US Content-Transfer-Encoding: 8bit X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400d:c09::242 Subject: Re: [Qemu-arm] [Qemu-devel] [PATCH 4/8] tcg: Add operations for host vectors X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 30 Aug 2017 03:49:26 -0000 On 08/17/2017 08:01 PM, Richard Henderson wrote: > Nothing uses or implements them yet. > > Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daudé > --- > tcg/tcg-opc.h | 89 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > tcg/tcg.h | 24 ++++++++++++++++ > 2 files changed, 113 insertions(+) > > diff --git a/tcg/tcg-opc.h b/tcg/tcg-opc.h > index 956fb1e9f3..9162125fac 100644 > --- a/tcg/tcg-opc.h > +++ b/tcg/tcg-opc.h > @@ -206,6 +206,95 @@ DEF(qemu_st_i64, 0, TLADDR_ARGS + DATA64_ARGS, 1, > > #undef TLADDR_ARGS > #undef DATA64_ARGS > + > +/* Host integer vector operations. */ > +/* These opcodes are required whenever the base vector size is enabled. */ > + > +DEF(mov_v64, 1, 1, 0, IMPL(TCG_TARGET_HAS_v64)) > +DEF(mov_v128, 1, 1, 0, IMPL(TCG_TARGET_HAS_v128)) > +DEF(mov_v256, 1, 1, 0, IMPL(TCG_TARGET_HAS_v256)) > + > +DEF(movi_v64, 1, 0, 1, IMPL(TCG_TARGET_HAS_v64)) > +DEF(movi_v128, 1, 0, 1, IMPL(TCG_TARGET_HAS_v128)) > +DEF(movi_v256, 1, 0, 1, IMPL(TCG_TARGET_HAS_v256)) > + > +DEF(ld_v64, 1, 1, 1, IMPL(TCG_TARGET_HAS_v64)) > +DEF(ld_v128, 1, 1, 1, IMPL(TCG_TARGET_HAS_v128)) > +DEF(ld_v256, 1, 1, 1, IMPL(TCG_TARGET_HAS_v256)) > + > +DEF(st_v64, 0, 2, 1, IMPL(TCG_TARGET_HAS_v64)) > +DEF(st_v128, 0, 2, 1, IMPL(TCG_TARGET_HAS_v128)) > +DEF(st_v256, 0, 2, 1, IMPL(TCG_TARGET_HAS_v256)) > + > +DEF(and_v64, 1, 2, 0, IMPL(TCG_TARGET_HAS_v64)) > +DEF(and_v128, 1, 2, 0, IMPL(TCG_TARGET_HAS_v128)) > +DEF(and_v256, 1, 2, 0, IMPL(TCG_TARGET_HAS_v256)) > + > +DEF(or_v64, 1, 2, 0, IMPL(TCG_TARGET_HAS_v64)) > +DEF(or_v128, 1, 2, 0, IMPL(TCG_TARGET_HAS_v128)) > +DEF(or_v256, 1, 2, 0, IMPL(TCG_TARGET_HAS_v256)) > + > +DEF(xor_v64, 1, 2, 0, IMPL(TCG_TARGET_HAS_v64)) > +DEF(xor_v128, 1, 2, 0, IMPL(TCG_TARGET_HAS_v128)) > +DEF(xor_v256, 1, 2, 0, IMPL(TCG_TARGET_HAS_v256)) > + > +DEF(add8_v64, 1, 2, 0, IMPL(TCG_TARGET_HAS_v64)) > +DEF(add16_v64, 1, 2, 0, IMPL(TCG_TARGET_HAS_v64)) > +DEF(add32_v64, 1, 2, 0, IMPL(TCG_TARGET_HAS_v64)) > + > +DEF(add8_v128, 1, 2, 0, IMPL(TCG_TARGET_HAS_v128)) > +DEF(add16_v128, 1, 2, 0, IMPL(TCG_TARGET_HAS_v128)) > +DEF(add32_v128, 1, 2, 0, IMPL(TCG_TARGET_HAS_v128)) > +DEF(add64_v128, 1, 2, 0, IMPL(TCG_TARGET_HAS_v128)) > + > +DEF(add8_v256, 1, 2, 0, IMPL(TCG_TARGET_HAS_v256)) > +DEF(add16_v256, 1, 2, 0, IMPL(TCG_TARGET_HAS_v256)) > +DEF(add32_v256, 1, 2, 0, IMPL(TCG_TARGET_HAS_v256)) > +DEF(add64_v256, 1, 2, 0, IMPL(TCG_TARGET_HAS_v256)) > + > +DEF(sub8_v64, 1, 2, 0, IMPL(TCG_TARGET_HAS_v64)) > +DEF(sub16_v64, 1, 2, 0, IMPL(TCG_TARGET_HAS_v64)) > +DEF(sub32_v64, 1, 2, 0, IMPL(TCG_TARGET_HAS_v64)) > + > +DEF(sub8_v128, 1, 2, 0, IMPL(TCG_TARGET_HAS_v128)) > +DEF(sub16_v128, 1, 2, 0, IMPL(TCG_TARGET_HAS_v128)) > +DEF(sub32_v128, 1, 2, 0, IMPL(TCG_TARGET_HAS_v128)) > +DEF(sub64_v128, 1, 2, 0, IMPL(TCG_TARGET_HAS_v128)) > + > +DEF(sub8_v256, 1, 2, 0, IMPL(TCG_TARGET_HAS_v256)) > +DEF(sub16_v256, 1, 2, 0, IMPL(TCG_TARGET_HAS_v256)) > +DEF(sub32_v256, 1, 2, 0, IMPL(TCG_TARGET_HAS_v256)) > +DEF(sub64_v256, 1, 2, 0, IMPL(TCG_TARGET_HAS_v256)) > + > +/* These opcodes are optional. > + All element counts must be supported if any are. */ > + > +DEF(not_v64, 1, 1, 0, IMPL(TCG_TARGET_HAS_not_v64)) > +DEF(not_v128, 1, 1, 0, IMPL(TCG_TARGET_HAS_not_v128)) > +DEF(not_v256, 1, 1, 0, IMPL(TCG_TARGET_HAS_not_v256)) > + > +DEF(andc_v64, 1, 2, 0, IMPL(TCG_TARGET_HAS_andc_v64)) > +DEF(andc_v128, 1, 2, 0, IMPL(TCG_TARGET_HAS_andc_v128)) > +DEF(andc_v256, 1, 2, 0, IMPL(TCG_TARGET_HAS_andc_v256)) > + > +DEF(orc_v64, 1, 2, 0, IMPL(TCG_TARGET_HAS_orc_v64)) > +DEF(orc_v128, 1, 2, 0, IMPL(TCG_TARGET_HAS_orc_v128)) > +DEF(orc_v256, 1, 2, 0, IMPL(TCG_TARGET_HAS_orc_v256)) > + > +DEF(neg8_v64, 1, 1, 0, IMPL(TCG_TARGET_HAS_neg_v64)) > +DEF(neg16_v64, 1, 1, 0, IMPL(TCG_TARGET_HAS_neg_v64)) > +DEF(neg32_v64, 1, 1, 0, IMPL(TCG_TARGET_HAS_neg_v64)) > + > +DEF(neg8_v128, 1, 1, 0, IMPL(TCG_TARGET_HAS_neg_v128)) > +DEF(neg16_v128, 1, 1, 0, IMPL(TCG_TARGET_HAS_neg_v128)) > +DEF(neg32_v128, 1, 1, 0, IMPL(TCG_TARGET_HAS_neg_v128)) > +DEF(neg64_v128, 1, 1, 0, IMPL(TCG_TARGET_HAS_neg_v128)) > + > +DEF(neg8_v256, 1, 1, 0, IMPL(TCG_TARGET_HAS_neg_v256)) > +DEF(neg16_v256, 1, 1, 0, IMPL(TCG_TARGET_HAS_neg_v256)) > +DEF(neg32_v256, 1, 1, 0, IMPL(TCG_TARGET_HAS_neg_v256)) > +DEF(neg64_v256, 1, 1, 0, IMPL(TCG_TARGET_HAS_neg_v256)) > + > #undef IMPL > #undef IMPL64 > #undef DEF > diff --git a/tcg/tcg.h b/tcg/tcg.h > index 1277caed3d..b9e15da13b 100644 > --- a/tcg/tcg.h > +++ b/tcg/tcg.h > @@ -166,6 +166,30 @@ typedef uint64_t TCGRegSet; > #define TCG_TARGET_HAS_rem_i64 0 > #endif > > +#ifndef TCG_TARGET_HAS_v64 > +#define TCG_TARGET_HAS_v64 0 > +#define TCG_TARGET_HAS_andc_v64 0 > +#define TCG_TARGET_HAS_orc_v64 0 > +#define TCG_TARGET_HAS_not_v64 0 > +#define TCG_TARGET_HAS_neg_v64 0 > +#endif > + > +#ifndef TCG_TARGET_HAS_v128 > +#define TCG_TARGET_HAS_v128 0 > +#define TCG_TARGET_HAS_andc_v128 0 > +#define TCG_TARGET_HAS_orc_v128 0 > +#define TCG_TARGET_HAS_not_v128 0 > +#define TCG_TARGET_HAS_neg_v128 0 > +#endif > + > +#ifndef TCG_TARGET_HAS_v256 > +#define TCG_TARGET_HAS_v256 0 > +#define TCG_TARGET_HAS_andc_v256 0 > +#define TCG_TARGET_HAS_orc_v256 0 > +#define TCG_TARGET_HAS_not_v256 0 > +#define TCG_TARGET_HAS_neg_v256 0 > +#endif > + > /* For 32-bit targets, some sort of unsigned widening multiply is required. */ > #if TCG_TARGET_REG_BITS == 32 \ > && !(defined(TCG_TARGET_HAS_mulu2_i32) \ > From MAILER-DAEMON Tue Aug 29 23:50:03 2017 Received: from list by lists.gnu.org with archive (Exim 4.71) id 1dmu0w-0003zH-7n for mharc-qemu-arm@gnu.org; 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Tue, 29 Aug 2017 20:49:49 -0700 (PDT) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= To: Subbaraya Sundeep , qemu-devel@nongnu.org, qemu-arm@nongnu.org Cc: peter.maydell@linaro.org, crosthwaite.peter@gmail.com, alistair23@gmail.com References: <1503938283-12404-1-git-send-email-sundeep.lkml@gmail.com> <1503938283-12404-6-git-send-email-sundeep.lkml@gmail.com> From: =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= Message-ID: Date: Tue, 29 Aug 2017 22:48:59 -0300 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.3.0 MIME-Version: 1.0 In-Reply-To: <1503938283-12404-6-git-send-email-sundeep.lkml@gmail.com> Content-Type: text/plain; charset=utf-8; format=flowed Content-Language: en-US Content-Transfer-Encoding: 8bit X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400d:c0d::243 Subject: Re: [Qemu-arm] [Qemu devel v7 PATCH 5/5] msf2: Add Emcraft's Smartfusion2 SOM kit X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 30 Aug 2017 03:50:00 -0000 Hi Subbaraya, On 08/28/2017 01:38 PM, Subbaraya Sundeep wrote: > Emulated Emcraft's Smartfusion2 System On Module starter > kit. > > Signed-off-by: Subbaraya Sundeep > --- > hw/arm/Makefile.objs | 2 +- > hw/arm/msf2-som.c | 94 ++++++++++++++++++++++++++++++++++++++++++++++++++++ > 2 files changed, 95 insertions(+), 1 deletion(-) > create mode 100644 hw/arm/msf2-som.c > > diff --git a/hw/arm/Makefile.objs b/hw/arm/Makefile.objs > index df36a03..e81a7dc 100644 > --- a/hw/arm/Makefile.objs > +++ b/hw/arm/Makefile.objs > @@ -19,4 +19,4 @@ obj-$(CONFIG_FSL_IMX31) += fsl-imx31.o kzm.o > obj-$(CONFIG_FSL_IMX6) += fsl-imx6.o sabrelite.o > obj-$(CONFIG_ASPEED_SOC) += aspeed_soc.o aspeed.o > obj-$(CONFIG_MPS2) += mps2.o > -obj-$(CONFIG_MSF2) += msf2-soc.o > +obj-$(CONFIG_MSF2) += msf2-soc.o msf2-som.o > diff --git a/hw/arm/msf2-som.c b/hw/arm/msf2-som.c > new file mode 100644 > index 0000000..fd89ba9 > --- /dev/null > +++ b/hw/arm/msf2-som.c > @@ -0,0 +1,94 @@ > +/* > + * SmartFusion2 SOM starter kit(from Emcraft) emulation. > + * > + * Copyright (c) 2017 Subbaraya Sundeep > + * > + * Permission is hereby granted, free of charge, to any person obtaining a copy > + * of this software and associated documentation files (the "Software"), to deal > + * in the Software without restriction, including without limitation the rights > + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell > + * copies of the Software, and to permit persons to whom the Software is > + * furnished to do so, subject to the following conditions: > + * > + * The above copyright notice and this permission notice shall be included in > + * all copies or substantial portions of the Software. > + * > + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR > + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, > + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL > + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER > + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, > + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN > + * THE SOFTWARE. > + */ > + > +#include "qemu/osdep.h" > +#include "qapi/error.h" > +#include "hw/boards.h" > +#include "hw/arm/arm.h" > +#include "exec/address-spaces.h" > +#include "qemu/cutils.h" > +#include "hw/arm/msf2-soc.h" > + > +#define DDR_BASE_ADDRESS 0xA0000000 > +#define DDR_SIZE (64 * M_BYTE) > + > +#define M2S010_ENVM_SIZE (256 * K_BYTE) > +#define M2S010_ESRAM_SIZE (64 * K_BYTE) > + > +static void emcraft_sf2_init(MachineState *machine) Since Emcraft can produce an upgraded SF2 SoC based on a different MCU, I prefer you rename it: static void emcraft_sf2_s2s010_init(MachineState *machine) > +{ > + DeviceState *dev; > + DeviceState *spi_flash; > + MSF2State *soc; > + DriveInfo *dinfo = drive_get_next(IF_MTD); > + qemu_irq cs_line; > + SSIBus *spi_bus; > + MemoryRegion *sysmem = get_system_memory(); > + MemoryRegion *ddr = g_new(MemoryRegion, 1); > + > + memory_region_init_ram(ddr, NULL, "ddr-ram", DDR_SIZE, > + &error_fatal); > + memory_region_add_subregion(sysmem, DDR_BASE_ADDRESS, ddr); > + > + dev = qdev_create(NULL, TYPE_MSF2_SOC); > + qdev_prop_set_string(dev, "part-name", "M2S010"); > + qdev_prop_set_uint64(dev, "eNVM-size", M2S010_ENVM_SIZE); > + qdev_prop_set_uint64(dev, "eSRAM-size", M2S010_ESRAM_SIZE); > + > + /* > + * CPU clock and peripheral clocks(APB0, APB1)are configurable > + * in Libero. CPU clock is divided by APB0 and APB1 divisors for > + * peripherals. Emcraft's SoM kit comes with these settings by default. > + */ > + qdev_prop_set_uint32(dev, "m3clk", 142 * 1000000); > + qdev_prop_set_uint32(dev, "apb0div", 2); > + qdev_prop_set_uint32(dev, "apb1div", 2); > + > + object_property_set_bool(OBJECT(dev), true, "realized", &error_fatal); > + > + soc = MSF2_SOC(dev); > + > + /* Attach SPI flash to SPI0 controller */ > + spi_bus = (SSIBus *)qdev_get_child_bus(dev, "spi0"); > + spi_flash = ssi_create_slave_no_init(spi_bus, "s25sl12801"); > + qdev_prop_set_uint8(spi_flash, "spansion-cr2nv", 1); > + if (dinfo) { > + qdev_prop_set_drive(spi_flash, "drive", blk_by_legacy_dinfo(dinfo), > + &error_fatal); > + } > + qdev_init_nofail(spi_flash); > + cs_line = qdev_get_gpio_in_named(spi_flash, SSI_GPIO_CS, 0); > + sysbus_connect_irq(SYS_BUS_DEVICE(&soc->spi[0]), 1, cs_line); > + > + armv7m_load_kernel(ARM_CPU(first_cpu), machine->kernel_filename, > + soc->envm_size); > +} > + > +static void emcraft_sf2_machine_init(MachineClass *mc) > +{ > + mc->desc = "SmartFusion2 SOM kit from Emcraft"; mc->desc = "SmartFusion2 SOM kit from Emcraft (M2S010)"; > + mc->init = emcraft_sf2_init; mc->init = emcraft_sf2_s2s010_init; > +} > + > +DEFINE_MACHINE("emcraft-sf2", emcraft_sf2_machine_init) Good work :) With the changes: Reviewed-by: Philippe Mathieu-Daudé From MAILER-DAEMON Tue Aug 29 23:50:05 2017 Received: from list by lists.gnu.org with archive (Exim 4.71) id 1dmu0z-00041R-BP for mharc-qemu-arm@gnu.org; Tue, 29 Aug 2017 23:50:05 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:40714) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dmu0t-0003xl-I7 for qemu-arm@nongnu.org; Tue, 29 Aug 2017 23:50:03 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dmu0r-0001cz-Jb for qemu-arm@nongnu.org; Tue, 29 Aug 2017 23:49:59 -0400 Received: from mail-qk0-x241.google.com ([2607:f8b0:400d:c09::241]:37373) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1dmu0r-0001cZ-Cz; Tue, 29 Aug 2017 23:49:57 -0400 Received: by mail-qk0-x241.google.com with SMTP id m4so4444444qke.4; Tue, 29 Aug 2017 20:49:57 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:subject:to:cc:references:from:message-id:date:user-agent :mime-version:in-reply-to:content-language:content-transfer-encoding; bh=2BEutEwgd9IHq5OewXgxB3IXf5P5qT1P4R2QMgV6IVU=; b=dTgj56mbmi5TVk1ZEnh08PxqHSEddSGyzabCag4zPyLv5yrHbqc9/R5yCB7DpjWRt4 CM3XPMCaNLWfIv7/UYkKRGlt4craceobFYr8IIhDUfR1XZ7gH3eqmPu9zllIDTIqePSn nTyOgAw1+lxs2aovn80pRMEAJzk+DdUZ5m/AUZ11g23shUyiVC5D5j0wwwFvInmnKJqB 0BWc5+wiDh/2qwDkYNo2/pWYG0bMj5ub32p0Un2a5ygOJa9OnV/T5zU4aDg6sphnd2df Xq+Ou+r2cayHDW+SRe2NC3WNUpAgbrPCYoFnuU6x50KHCvd0n+fg8GES+EsIQ3puGD6l XhKQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:subject:to:cc:references:from:message-id :date:user-agent:mime-version:in-reply-to:content-language :content-transfer-encoding; bh=2BEutEwgd9IHq5OewXgxB3IXf5P5qT1P4R2QMgV6IVU=; b=aAPso7LjauQw/qnJvBl9ldBQDIdNMilR4nyP45eh2MlEtNPdVXZDYIUjQYgYLPmw9/ 0nUu0XtE3Lb2touGxibVyQNm7FYQ0UtbryJLilQq/f5s4KG12/+HFIWzkj1qs9bzJCMK iJZfDLwxQmuwGHfByi1vxKtsAoencN2I3nejsFwmi8tCYAgaT6t4RxdKoWR6RZF/lCN4 zR3YtPHmd3MhC+U1vj81rdo4LJtBAdHspZfHcGedOPo3mziCsG9KU2VwyRTvsGwgQIxn XYE7DnsHyEJkow0Bj+6PXfcVLYbHPX9u17RRN/5gdGhH2GQLjJhqUEGgZunPn5pJYgOc h6fg== X-Gm-Message-State: AHYfb5jmqrWg8i+FN11OCo8Cv4/siIdy1Sqj5Tvho8I9kOhzqAwVKvlY R7By78duqJWYUw== X-Received: by 10.55.124.67 with SMTP id x64mr8262160qkc.108.1504064996606; Tue, 29 Aug 2017 20:49:56 -0700 (PDT) Received: from [192.168.43.33] ([170.51.33.248]) by smtp.gmail.com with ESMTPSA id r22sm3132973qkl.12.2017.08.29.20.49.53 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 29 Aug 2017 20:49:56 -0700 (PDT) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= To: Subbaraya Sundeep , qemu-devel@nongnu.org, qemu-arm@nongnu.org Cc: peter.maydell@linaro.org, crosthwaite.peter@gmail.com, alistair23@gmail.com References: <1503938283-12404-1-git-send-email-sundeep.lkml@gmail.com> <1503938283-12404-5-git-send-email-sundeep.lkml@gmail.com> From: =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= Message-ID: <10da5552-c90a-21e6-43ac-829932f64930@amsat.org> Date: Tue, 29 Aug 2017 23:45:38 -0300 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.3.0 MIME-Version: 1.0 In-Reply-To: <1503938283-12404-5-git-send-email-sundeep.lkml@gmail.com> Content-Type: text/plain; charset=utf-8; format=flowed Content-Language: en-US Content-Transfer-Encoding: 7bit X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400d:c09::241 Subject: Re: [Qemu-arm] [Qemu devel v7 PATCH 4/5] msf2: Add Smartfusion2 SoC X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 30 Aug 2017 03:50:03 -0000 Hi Subbaraya, On 08/28/2017 01:38 PM, Subbaraya Sundeep wrote: > Smartfusion2 SoC has hardened Microcontroller subsystem > and flash based FPGA fabric. This patch adds support for > Microcontroller subsystem in the SoC. > > Signed-off-by: Subbaraya Sundeep > --- > default-configs/arm-softmmu.mak | 1 + > hw/arm/Makefile.objs | 1 + > hw/arm/msf2-soc.c | 215 ++++++++++++++++++++++++++++++++++++++++ > include/hw/arm/msf2-soc.h | 66 ++++++++++++ > 4 files changed, 283 insertions(+) > create mode 100644 hw/arm/msf2-soc.c > create mode 100644 include/hw/arm/msf2-soc.h > > diff --git a/default-configs/arm-softmmu.mak b/default-configs/arm-softmmu.mak > index bbdd3c1..5059d13 100644 > --- a/default-configs/arm-softmmu.mak > +++ b/default-configs/arm-softmmu.mak > @@ -129,3 +129,4 @@ CONFIG_ACPI=y > CONFIG_SMBIOS=y > CONFIG_ASPEED_SOC=y > CONFIG_GPIO_KEY=y > +CONFIG_MSF2=y > diff --git a/hw/arm/Makefile.objs b/hw/arm/Makefile.objs > index a2e56ec..df36a03 100644 > --- a/hw/arm/Makefile.objs > +++ b/hw/arm/Makefile.objs > @@ -19,3 +19,4 @@ obj-$(CONFIG_FSL_IMX31) += fsl-imx31.o kzm.o > obj-$(CONFIG_FSL_IMX6) += fsl-imx6.o sabrelite.o > obj-$(CONFIG_ASPEED_SOC) += aspeed_soc.o aspeed.o > obj-$(CONFIG_MPS2) += mps2.o > +obj-$(CONFIG_MSF2) += msf2-soc.o > diff --git a/hw/arm/msf2-soc.c b/hw/arm/msf2-soc.c > new file mode 100644 > index 0000000..276eec5 > --- /dev/null > +++ b/hw/arm/msf2-soc.c > @@ -0,0 +1,215 @@ > +/* > + * SmartFusion2 SoC emulation. > + * > + * Copyright (c) 2017 Subbaraya Sundeep > + * > + * Permission is hereby granted, free of charge, to any person obtaining a copy > + * of this software and associated documentation files (the "Software"), to deal > + * in the Software without restriction, including without limitation the rights > + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell > + * copies of the Software, and to permit persons to whom the Software is > + * furnished to do so, subject to the following conditions: > + * > + * The above copyright notice and this permission notice shall be included in > + * all copies or substantial portions of the Software. > + * > + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR > + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, > + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL > + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER > + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, > + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN > + * THE SOFTWARE. > + */ > + > +#include "qemu/osdep.h" > +#include "qapi/error.h" > +#include "qemu-common.h" > +#include "hw/arm/arm.h" > +#include "exec/address-spaces.h" > +#include "hw/char/serial.h" > +#include "hw/boards.h" > +#include "sysemu/block-backend.h" > +#include "qemu/cutils.h" > +#include "hw/arm/msf2-soc.h" > + > +#define MSF2_TIMER_BASE 0x40004000 > +#define MSF2_SYSREG_BASE 0x40038000 > + > +#define ENVM_BASE_ADDRESS 0x60000000 > + > +#define SRAM_BASE_ADDRESS 0x20000000 > + > +#define MSF2_ENVM_SIZE (512 * K_BYTE) > +#define MSF2_ESRAM_SIZE (64 * K_BYTE) Eventually you should name those _SIZE_MAX. I miscorrected you in v4, 64kB is true with SECDED disabled, else the SoC is designed for 80kB. Not a big deal, we can add a "SECDED not supported" warning later. Can you add a comment about it? > + > +static const uint32_t spi_addr[MSF2_NUM_SPIS] = { 0x40001000 , 0x40011000 }; > +static const uint32_t uart_addr[MSF2_NUM_UARTS] = { 0x40000000 , 0x40010000 }; > + > +static const int spi_irq[MSF2_NUM_SPIS] = { 2, 3 }; > +static const int uart_irq[MSF2_NUM_UARTS] = { 10, 11 }; > +static const int timer_irq[MSF2_NUM_TIMERS] = { 14, 15 }; > + > +static void m2sxxx_soc_initfn(Object *obj) > +{ > + MSF2State *s = MSF2_SOC(obj); > + int i; > + > + object_initialize(&s->armv7m, sizeof(s->armv7m), TYPE_ARMV7M); > + qdev_set_parent_bus(DEVICE(&s->armv7m), sysbus_get_default()); > + > + object_initialize(&s->sysreg, sizeof(s->sysreg), TYPE_MSF2_SYSREG); > + qdev_set_parent_bus(DEVICE(&s->sysreg), sysbus_get_default()); > + > + object_initialize(&s->timer, sizeof(s->timer), TYPE_MSS_TIMER); > + qdev_set_parent_bus(DEVICE(&s->timer), sysbus_get_default()); > + What about the UARTs? > + for (i = 0; i < MSF2_NUM_SPIS; i++) { > + object_initialize(&s->spi[i], sizeof(s->spi[i]), > + TYPE_MSS_SPI); > + qdev_set_parent_bus(DEVICE(&s->spi[i]), sysbus_get_default()); > + } > +} > + > +static void m2sxxx_soc_realize(DeviceState *dev_soc, Error **errp) > +{ > + MSF2State *s = MSF2_SOC(dev_soc); > + DeviceState *dev, *armv7m; > + SysBusDevice *busdev; > + Error *err = NULL; > + int i; > + > + MemoryRegion *system_memory = get_system_memory(); > + MemoryRegion *nvm = g_new(MemoryRegion, 1); > + MemoryRegion *nvm_alias = g_new(MemoryRegion, 1); > + MemoryRegion *sram = g_new(MemoryRegion, 1); > + > + memory_region_init_ram(nvm, NULL, "MSF2.eNVM", s->envm_size, > + &error_fatal); Why do you initialize as RAM? I'd rather use memory_region_init_rom_device() here, so you can boot a dumped eNVM flash. > + > + /* > + * On power-on, the eNVM region 0x60000000 is automatically > + * remapped to the Cortex-M3 processor executable region > + * start address (0x0). We do not support remapping other eNVM, > + * eSRAM and DDR regions by guest(via Sysreg) currently. > + */ > + memory_region_init_alias(nvm_alias, NULL, "MSF2.eNVM.alias", > + nvm, 0, s->envm_size); > + > + memory_region_set_readonly(nvm, true); > + memory_region_set_readonly(nvm_alias, true); Hmmm not sure the alias needs this. > + > + memory_region_add_subregion(system_memory, ENVM_BASE_ADDRESS, nvm); > + memory_region_add_subregion(system_memory, 0, nvm_alias); > + > + memory_region_init_ram(sram, NULL, "MSF2.eSRAM", s->esram_size, > + &error_fatal); > + memory_region_add_subregion(system_memory, SRAM_BASE_ADDRESS, sram); > + > + armv7m = DEVICE(&s->armv7m); > + qdev_prop_set_uint32(armv7m, "num-irq", 81); > + qdev_prop_set_string(armv7m, "cpu-model", "cortex-m3"); > + object_property_set_link(OBJECT(&s->armv7m), OBJECT(get_system_memory()), > + "memory", &error_abort); > + object_property_set_bool(OBJECT(&s->armv7m), true, "realized", &err); > + if (err != NULL) { > + error_propagate(errp, err); > + return; > + } > + > + system_clock_scale = NANOSECONDS_PER_SECOND / s->m3clk; > + > + for (i = 0; i < MSF2_NUM_UARTS; i++) { > + if (serial_hds[i]) { I think they might be issues if you start QEMU without -serial and then use a firmware polling for an uart, the device won't be mapped and the memory accesses are mostly ignored. I'd rather use: for (i = 0; i < MSF2_NUM_UARTS && i < MAX_SERIAL_PORTS; i++) { static const char *serial[] = {"serial0", "serial1"}; if (!serial_hds[i]) { serial_hds[i] = qemu_chr_new(serial[i], "null"); } > + serial_mm_init(get_system_memory(), uart_addr[i], 2, > + qdev_get_gpio_in(armv7m, uart_irq[i]), > + 115200, serial_hds[i], DEVICE_NATIVE_ENDIAN); > + } > + } > + > + dev = DEVICE(&s->timer); > + /* APB0 clock is the timer input clock */ > + qdev_prop_set_uint32(dev, "clock-frequency", s->m3clk / s->apb0div); > + object_property_set_bool(OBJECT(&s->timer), true, "realized", &err); > + if (err != NULL) { > + error_propagate(errp, err); > + return; > + } > + busdev = SYS_BUS_DEVICE(dev); > + sysbus_mmio_map(busdev, 0, MSF2_TIMER_BASE); > + sysbus_connect_irq(busdev, 0, > + qdev_get_gpio_in(armv7m, timer_irq[0])); > + sysbus_connect_irq(busdev, 1, > + qdev_get_gpio_in(armv7m, timer_irq[1])); > + > + dev = DEVICE(&s->sysreg); > + qdev_prop_set_uint32(dev, "apb0divisor", s->apb0div); > + qdev_prop_set_uint32(dev, "apb1divisor", s->apb1div); > + object_property_set_bool(OBJECT(&s->sysreg), true, "realized", &err); > + if (err != NULL) { > + error_propagate(errp, err); > + return; > + } > + busdev = SYS_BUS_DEVICE(dev); > + sysbus_mmio_map(busdev, 0, MSF2_SYSREG_BASE); > + > + for (i = 0; i < MSF2_NUM_SPIS; i++) { > + gchar *bus_name = g_strdup_printf("spi%d", i); move g_strdup_printf() down ... > + > + object_property_set_bool(OBJECT(&s->spi[i]), true, "realized", &err); > + if (err != NULL) { > + g_free(bus_name); so this g_free() is not needed. > + error_propagate(errp, err); > + return; > + } > + > + sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi[i]), 0, spi_addr[i]); > + sysbus_connect_irq(SYS_BUS_DEVICE(&s->spi[i]), 0, > + qdev_get_gpio_in(armv7m, spi_irq[i])); > + > + /* Alias controller SPI bus to the SoC itself */ Here: bus_name = g_strdup_printf("spi%d", i); > + object_property_add_alias(OBJECT(s), bus_name, > + OBJECT(&s->spi[i]), "spi", > + &error_abort); > + g_free(bus_name); > + } > +} > + > +static Property m2sxxx_soc_properties[] = { > + /* > + * part name specifies the type of SmartFusion2 device variant(this > + * property is for information purpose only. > + */ > + DEFINE_PROP_STRING("part-name", MSF2State, part_name), > + DEFINE_PROP_UINT64("eNVM-size", MSF2State, envm_size, MSF2_ENVM_SIZE), > + DEFINE_PROP_UINT64("eSRAM-size", MSF2State, esram_size, MSF2_ESRAM_SIZE), > + /* Libero GUI shows 100Mhz as default for clocks */ > + DEFINE_PROP_UINT32("m3clk", MSF2State, m3clk, 100 * 1000000), > + /* default divisors in Libero GUI */ > + DEFINE_PROP_UINT32("apb0div", MSF2State, apb0div, 2), > + DEFINE_PROP_UINT32("apb1div", MSF2State, apb1div, 2), > + DEFINE_PROP_END_OF_LIST(), > +}; > + > +static void m2sxxx_soc_class_init(ObjectClass *klass, void *data) > +{ > + DeviceClass *dc = DEVICE_CLASS(klass); > + > + dc->realize = m2sxxx_soc_realize; > + dc->props = m2sxxx_soc_properties; > +} > + > +static const TypeInfo m2sxxx_soc_info = { > + .name = TYPE_MSF2_SOC, > + .parent = TYPE_SYS_BUS_DEVICE, > + .instance_size = sizeof(MSF2State), > + .instance_init = m2sxxx_soc_initfn, > + .class_init = m2sxxx_soc_class_init, > +}; > + > +static void m2sxxx_soc_types(void) > +{ > + type_register_static(&m2sxxx_soc_info); > +} > + > +type_init(m2sxxx_soc_types) > diff --git a/include/hw/arm/msf2-soc.h b/include/hw/arm/msf2-soc.h > new file mode 100644 > index 0000000..eb239fa > --- /dev/null > +++ b/include/hw/arm/msf2-soc.h > @@ -0,0 +1,66 @@ > +/* > + * Microsemi Smartfusion2 SoC > + * > + * Copyright (c) 2017 Subbaraya Sundeep > + * > + * Permission is hereby granted, free of charge, to any person obtaining a copy > + * of this software and associated documentation files (the "Software"), to deal > + * in the Software without restriction, including without limitation the rights > + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell > + * copies of the Software, and to permit persons to whom the Software is > + * furnished to do so, subject to the following conditions: > + * > + * The above copyright notice and this permission notice shall be included in > + * all copies or substantial portions of the Software. > + * > + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR > + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, > + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL > + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER > + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, > + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN > + * THE SOFTWARE. > + */ > + > +#ifndef HW_ARM_MSF2_SOC_H > +#define HW_ARM_MSF2_SOC_H > + > +#include "hw/arm/armv7m.h" > +#include "hw/timer/mss-timer.h" > +#include "hw/misc/msf2-sysreg.h" > +#include "hw/ssi/mss-spi.h" > + > +#define TYPE_MSF2_SOC "msf2-soc" > +#define MSF2_SOC(obj) OBJECT_CHECK(MSF2State, (obj), TYPE_MSF2_SOC) > + > +#define MSF2_NUM_SPIS 2 > +#define MSF2_NUM_UARTS 2 > + > +/* > + * System timer consists of two programmable 32-bit > + * decrementing counters that generate individual interrupts to > + * the Cortex-M3 processor > + */ > +#define MSF2_NUM_TIMERS 2 > + > +typedef struct MSF2State { > + /*< private >*/ > + SysBusDevice parent_obj; > + /*< public >*/ > + > + ARMv7MState armv7m; > + > + char *part_name; > + uint64_t envm_size; > + uint64_t esram_size; > + > + uint32_t m3clk; > + uint32_t apb0div; > + uint32_t apb1div; > + > + MSF2SysregState sysreg; > + MSSTimerState timer; > + MSSSpiState spi[MSF2_NUM_SPIS]; > +} MSF2State; > + > +#endif Almost there :) Are you OK to: - register eNVM as ROM - check UARTs? Regards, Phil. From MAILER-DAEMON Wed Aug 30 08:23:36 2017 Received: from list by lists.gnu.org with archive (Exim 4.71) id 1dn21w-0007o8-RL for mharc-qemu-arm@gnu.org; Wed, 30 Aug 2017 08:23:36 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:36161) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dn21r-0007lR-Tk for qemu-arm@nongnu.org; Wed, 30 Aug 2017 08:23:35 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dn21o-0002IU-75 for qemu-arm@nongnu.org; Wed, 30 Aug 2017 08:23:31 -0400 Received: from mail-vk0-x229.google.com ([2607:f8b0:400c:c05::229]:34621) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1dn21g-0002FY-RN; Wed, 30 Aug 2017 08:23:21 -0400 Received: by mail-vk0-x229.google.com with SMTP id s199so17020043vke.1; Wed, 30 Aug 2017 05:23:19 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=mime-version:in-reply-to:references:from:date:message-id:subject:to :cc; bh=be691IAXlGJNnVAnxRCM1D6gS+Bima6Md/f67Fog8WQ=; b=OaTkboEOohPy2gLM0FLNjfKXJyTN4KUP6NXVx90jNSqsGfg06ENZ+RVGEpOXfQRRMF cwotNZVkggdfceXvCRl8z8/pHVRnczXd+pZR9rPaiR+s4s5HJjq5TPnGiDw7WmwrA/7N 8I9xL9eMBnPk6Lvn+YNG/6cKx/TxFP1phznllPwwx2w4jb9buw3ICMeU1m9FdiT5E00v dnByMwA+Z61B4g3DMkzJcO9qUO6Dh+fSW0UU7Zj8WAcDYV1jg1+FBGtvKNihAeahAdMV IvrSNMH2oGUvHqtEzQGgyLJwv1LJY714hVqU9ef+NdN2auNh+zdm8UOCUXO9i/duptGB zI4A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:in-reply-to:references:from:date :message-id:subject:to:cc; bh=be691IAXlGJNnVAnxRCM1D6gS+Bima6Md/f67Fog8WQ=; b=SgV/aVt0A28T4sIZwGR7UgbyL8E8xpppT34YvEcuUsgtF6ltiPhMW56oKwFLchoHfY 5DOKYZqE/dXgaTlzdy3tbTNSREuwJle7Q0jxOaih2NHPvkBsXjyKaE/D3huezMMSdipg DH14//1x8n3eLmQrw0sxNcUBs5TJ4ToPzar4SVOGIcO8fT3B6d6rZjggIF9CleBZSjoJ nQPy1ptkAmMvayDG95nZLcRpWNkIE66Ya2FVmNp2JI9mJjkZ6NNXU/IYbCqA7wOQyo1O l+TDLrEBXkpYYRVkQysz6Zo5HoRmM1IrPWAsUmFoOf6xyT5DBaP2Mrdxs3wVa2pjbn3C xY7A== X-Gm-Message-State: AHPjjUg8kjdJanoN8xa0u6k/FBMbunZ8B+56rTt5fSrx9kOmeWxlV7Uy SC72rBvSei5/ouc/fR5RvwEEsbOLDA== X-Google-Smtp-Source: ADKCNb7ophkxlvhAu8hW82nARvYGNCaWgoqRWYWouBgxOL82B0kx9qYN1xEAvgw/hlcnGob3G/aP28UsJO1uz7QYZBk= X-Received: by 10.31.148.72 with SMTP id w69mr740139vkd.55.1504095798714; Wed, 30 Aug 2017 05:23:18 -0700 (PDT) MIME-Version: 1.0 Received: by 10.176.75.196 with HTTP; Wed, 30 Aug 2017 05:23:18 -0700 (PDT) In-Reply-To: <10da5552-c90a-21e6-43ac-829932f64930@amsat.org> References: <1503938283-12404-1-git-send-email-sundeep.lkml@gmail.com> <1503938283-12404-5-git-send-email-sundeep.lkml@gmail.com> <10da5552-c90a-21e6-43ac-829932f64930@amsat.org> From: sundeep subbaraya Date: Wed, 30 Aug 2017 17:53:18 +0530 Message-ID: To: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= Cc: QEMU Developers , qemu-arm , Peter Maydell , Peter Crosthwaite , Alistair Francis Content-Type: multipart/alternative; boundary="001a11425890ca68b80557f79757" X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400c:c05::229 Subject: Re: [Qemu-arm] [Qemu devel v7 PATCH 4/5] msf2: Add Smartfusion2 SoC X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 30 Aug 2017 12:23:35 -0000 --001a11425890ca68b80557f79757 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Hi Philippe, On Wed, Aug 30, 2017 at 8:15 AM, Philippe Mathieu-Daud=C3=A9 wrote: > Hi Subbaraya, > > > On 08/28/2017 01:38 PM, Subbaraya Sundeep wrote: > >> Smartfusion2 SoC has hardened Microcontroller subsystem >> and flash based FPGA fabric. This patch adds support for >> Microcontroller subsystem in the SoC. >> >> Signed-off-by: Subbaraya Sundeep >> --- >> default-configs/arm-softmmu.mak | 1 + >> hw/arm/Makefile.objs | 1 + >> hw/arm/msf2-soc.c | 215 ++++++++++++++++++++++++++++++ >> ++++++++++ >> include/hw/arm/msf2-soc.h | 66 ++++++++++++ >> 4 files changed, 283 insertions(+) >> create mode 100644 hw/arm/msf2-soc.c >> create mode 100644 include/hw/arm/msf2-soc.h >> >> diff --git a/default-configs/arm-softmmu.mak >> b/default-configs/arm-softmmu.mak >> index bbdd3c1..5059d13 100644 >> --- a/default-configs/arm-softmmu.mak >> +++ b/default-configs/arm-softmmu.mak >> @@ -129,3 +129,4 @@ CONFIG_ACPI=3Dy >> CONFIG_SMBIOS=3Dy >> CONFIG_ASPEED_SOC=3Dy >> CONFIG_GPIO_KEY=3Dy >> +CONFIG_MSF2=3Dy >> diff --git a/hw/arm/Makefile.objs b/hw/arm/Makefile.objs >> index a2e56ec..df36a03 100644 >> --- a/hw/arm/Makefile.objs >> +++ b/hw/arm/Makefile.objs >> @@ -19,3 +19,4 @@ obj-$(CONFIG_FSL_IMX31) +=3D fsl-imx31.o kzm.o >> obj-$(CONFIG_FSL_IMX6) +=3D fsl-imx6.o sabrelite.o >> obj-$(CONFIG_ASPEED_SOC) +=3D aspeed_soc.o aspeed.o >> obj-$(CONFIG_MPS2) +=3D mps2.o >> +obj-$(CONFIG_MSF2) +=3D msf2-soc.o >> diff --git a/hw/arm/msf2-soc.c b/hw/arm/msf2-soc.c >> new file mode 100644 >> index 0000000..276eec5 >> --- /dev/null >> +++ b/hw/arm/msf2-soc.c >> @@ -0,0 +1,215 @@ >> +/* >> + * SmartFusion2 SoC emulation. >> + * >> + * Copyright (c) 2017 Subbaraya Sundeep >> + * >> + * Permission is hereby granted, free of charge, to any person obtainin= g >> a copy >> + * of this software and associated documentation files (the "Software")= , >> to deal >> + * in the Software without restriction, including without limitation th= e >> rights >> + * to use, copy, modify, merge, publish, distribute, sublicense, and/or >> sell >> + * copies of the Software, and to permit persons to whom the Software i= s >> + * furnished to do so, subject to the following conditions: >> + * >> + * The above copyright notice and this permission notice shall be >> included in >> + * all copies or substantial portions of the Software. >> + * >> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, >> EXPRESS OR >> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF >> MERCHANTABILITY, >> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT >> SHALL >> + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR >> OTHER >> + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, >> ARISING FROM, >> + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER >> DEALINGS IN >> + * THE SOFTWARE. >> + */ >> + >> +#include "qemu/osdep.h" >> +#include "qapi/error.h" >> +#include "qemu-common.h" >> +#include "hw/arm/arm.h" >> +#include "exec/address-spaces.h" >> +#include "hw/char/serial.h" >> +#include "hw/boards.h" >> +#include "sysemu/block-backend.h" >> +#include "qemu/cutils.h" >> +#include "hw/arm/msf2-soc.h" >> + >> +#define MSF2_TIMER_BASE 0x40004000 >> +#define MSF2_SYSREG_BASE 0x40038000 >> + >> +#define ENVM_BASE_ADDRESS 0x60000000 >> + >> +#define SRAM_BASE_ADDRESS 0x20000000 >> + >> +#define MSF2_ENVM_SIZE (512 * K_BYTE) >> +#define MSF2_ESRAM_SIZE (64 * K_BYTE) >> > > Eventually you should name those _SIZE_MAX. I agree and will change to SIZE_MAX > > I miscorrected you in v4, 64kB is true with SECDED disabled, else the SoC > is designed for 80kB. Not a big deal, we can add a "SECDED not supported" > warning later. > Can you add a comment about it? Sure will add a comment about it. > > > + >> +static const uint32_t spi_addr[MSF2_NUM_SPIS] =3D { 0x40001000 , >> 0x40011000 }; >> +static const uint32_t uart_addr[MSF2_NUM_UARTS] =3D { 0x40000000 , >> 0x40010000 }; >> + >> +static const int spi_irq[MSF2_NUM_SPIS] =3D { 2, 3 }; >> +static const int uart_irq[MSF2_NUM_UARTS] =3D { 10, 11 }; >> +static const int timer_irq[MSF2_NUM_TIMERS] =3D { 14, 15 }; >> + >> +static void m2sxxx_soc_initfn(Object *obj) >> +{ >> + MSF2State *s =3D MSF2_SOC(obj); >> + int i; >> + >> + object_initialize(&s->armv7m, sizeof(s->armv7m), TYPE_ARMV7M); >> + qdev_set_parent_bus(DEVICE(&s->armv7m), sysbus_get_default()); >> + >> + object_initialize(&s->sysreg, sizeof(s->sysreg), TYPE_MSF2_SYSREG); >> + qdev_set_parent_bus(DEVICE(&s->sysreg), sysbus_get_default()); >> + >> + object_initialize(&s->timer, sizeof(s->timer), TYPE_MSS_TIMER); >> + qdev_set_parent_bus(DEVICE(&s->timer), sysbus_get_default()); >> + >> > > What about the UARTs? > > + for (i =3D 0; i < MSF2_NUM_SPIS; i++) { >> + object_initialize(&s->spi[i], sizeof(s->spi[i]), >> + TYPE_MSS_SPI); >> + qdev_set_parent_bus(DEVICE(&s->spi[i]), sysbus_get_default()); >> + } >> +} >> + >> +static void m2sxxx_soc_realize(DeviceState *dev_soc, Error **errp) >> +{ >> + MSF2State *s =3D MSF2_SOC(dev_soc); >> + DeviceState *dev, *armv7m; >> + SysBusDevice *busdev; >> + Error *err =3D NULL; >> + int i; >> + >> + MemoryRegion *system_memory =3D get_system_memory(); >> + MemoryRegion *nvm =3D g_new(MemoryRegion, 1); >> + MemoryRegion *nvm_alias =3D g_new(MemoryRegion, 1); >> + MemoryRegion *sram =3D g_new(MemoryRegion, 1); >> + >> + memory_region_init_ram(nvm, NULL, "MSF2.eNVM", s->envm_size, >> + &error_fatal); >> > > Why do you initialize as RAM? I'd rather use memory_region_init_rom_devic= e() > here, so you can boot a dumped eNVM flash. Just followed other SoC(like stm32), booting a dumped eNVM flash? I am not clear about this how to do that? > > > + >> + /* >> + * On power-on, the eNVM region 0x60000000 is automatically >> + * remapped to the Cortex-M3 processor executable region >> + * start address (0x0). We do not support remapping other eNVM, >> + * eSRAM and DDR regions by guest(via Sysreg) currently. >> + */ >> + memory_region_init_alias(nvm_alias, NULL, "MSF2.eNVM.alias", >> + nvm, 0, s->envm_size); >> + >> + memory_region_set_readonly(nvm, true); >> + memory_region_set_readonly(nvm_alias, true); >> > > Hmmm not sure the alias needs this. Once we change to rom then memory_region_set_readonly will go away. > > > + >> + memory_region_add_subregion(system_memory, ENVM_BASE_ADDRESS, nvm); >> + memory_region_add_subregion(system_memory, 0, nvm_alias); >> + >> + memory_region_init_ram(sram, NULL, "MSF2.eSRAM", s->esram_size, >> + &error_fatal); >> + memory_region_add_subregion(system_memory, SRAM_BASE_ADDRESS, sram)= ; >> + >> + armv7m =3D DEVICE(&s->armv7m); >> + qdev_prop_set_uint32(armv7m, "num-irq", 81); >> + qdev_prop_set_string(armv7m, "cpu-model", "cortex-m3"); >> + object_property_set_link(OBJECT(&s->armv7m), >> OBJECT(get_system_memory()), >> + "memory", &error_abort); >> + object_property_set_bool(OBJECT(&s->armv7m), true, "realized", >> &err); >> + if (err !=3D NULL) { >> + error_propagate(errp, err); >> + return; >> + } >> + >> + system_clock_scale =3D NANOSECONDS_PER_SECOND / s->m3clk; >> + >> + for (i =3D 0; i < MSF2_NUM_UARTS; i++) { >> + if (serial_hds[i]) { >> > > I think they might be issues if you start QEMU without -serial and then > use a firmware polling for an uart, the device won't be mapped and the > memory accesses are mostly ignored. > > I'd rather use: > > for (i =3D 0; i < MSF2_NUM_UARTS && i < MAX_SERIAL_PORTS; i++) { > static const char *serial[] =3D {"serial0", "serial1"}; > > if (!serial_hds[i]) { > serial_hds[i] =3D qemu_chr_new(serial[i], "null"); > > } > I agree. I will go through this and change. > > + serial_mm_init(get_system_memory(), uart_addr[i], 2, >> + qdev_get_gpio_in(armv7m, uart_irq[i]), >> + 115200, serial_hds[i], DEVICE_NATIVE_ENDIAN)= ; >> + } >> + } >> + >> + dev =3D DEVICE(&s->timer); >> + /* APB0 clock is the timer input clock */ >> + qdev_prop_set_uint32(dev, "clock-frequency", s->m3clk / s->apb0div)= ; >> + object_property_set_bool(OBJECT(&s->timer), true, "realized", &err)= ; >> + if (err !=3D NULL) { >> + error_propagate(errp, err); >> + return; >> + } >> + busdev =3D SYS_BUS_DEVICE(dev); >> + sysbus_mmio_map(busdev, 0, MSF2_TIMER_BASE); >> + sysbus_connect_irq(busdev, 0, >> + qdev_get_gpio_in(armv7m, timer_irq[0])); >> + sysbus_connect_irq(busdev, 1, >> + qdev_get_gpio_in(armv7m, timer_irq[1])); >> + >> + dev =3D DEVICE(&s->sysreg); >> + qdev_prop_set_uint32(dev, "apb0divisor", s->apb0div); >> + qdev_prop_set_uint32(dev, "apb1divisor", s->apb1div); >> + object_property_set_bool(OBJECT(&s->sysreg), true, "realized", >> &err); >> + if (err !=3D NULL) { >> + error_propagate(errp, err); >> + return; >> + } >> + busdev =3D SYS_BUS_DEVICE(dev); >> + sysbus_mmio_map(busdev, 0, MSF2_SYSREG_BASE); >> + >> + for (i =3D 0; i < MSF2_NUM_SPIS; i++) { >> + gchar *bus_name =3D g_strdup_printf("spi%d", i); >> > > move g_strdup_printf() down ... > > + >> + object_property_set_bool(OBJECT(&s->spi[i]), true, "realized", >> &err); >> + if (err !=3D NULL) { >> + g_free(bus_name); >> > > so this g_free() is not needed. > > + error_propagate(errp, err); >> + return; >> + } >> + >> + sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi[i]), 0, spi_addr[i]); >> + sysbus_connect_irq(SYS_BUS_DEVICE(&s->spi[i]), 0, >> + qdev_get_gpio_in(armv7m, spi_irq[i])); >> + >> + /* Alias controller SPI bus to the SoC itself */ >> > > Here: > bus_name =3D g_strdup_printf("spi%d", i); Ok will modify. > > + object_property_add_alias(OBJECT(s), bus_name, >> >> + OBJECT(&s->spi[i]), "spi", >> + &error_abort); >> + g_free(bus_name); >> + } >> +} >> + >> +static Property m2sxxx_soc_properties[] =3D { >> + /* >> + * part name specifies the type of SmartFusion2 device variant(this >> + * property is for information purpose only. >> + */ >> + DEFINE_PROP_STRING("part-name", MSF2State, part_name), >> + DEFINE_PROP_UINT64("eNVM-size", MSF2State, envm_size, >> MSF2_ENVM_SIZE), >> + DEFINE_PROP_UINT64("eSRAM-size", MSF2State, esram_size, >> MSF2_ESRAM_SIZE), >> + /* Libero GUI shows 100Mhz as default for clocks */ >> + DEFINE_PROP_UINT32("m3clk", MSF2State, m3clk, 100 * 1000000), >> + /* default divisors in Libero GUI */ >> + DEFINE_PROP_UINT32("apb0div", MSF2State, apb0div, 2), >> + DEFINE_PROP_UINT32("apb1div", MSF2State, apb1div, 2), >> + DEFINE_PROP_END_OF_LIST(), >> +}; >> + >> +static void m2sxxx_soc_class_init(ObjectClass *klass, void *data) >> +{ >> + DeviceClass *dc =3D DEVICE_CLASS(klass); >> + >> + dc->realize =3D m2sxxx_soc_realize; >> + dc->props =3D m2sxxx_soc_properties; >> +} >> + >> +static const TypeInfo m2sxxx_soc_info =3D { >> + .name =3D TYPE_MSF2_SOC, >> + .parent =3D TYPE_SYS_BUS_DEVICE, >> + .instance_size =3D sizeof(MSF2State), >> + .instance_init =3D m2sxxx_soc_initfn, >> + .class_init =3D m2sxxx_soc_class_init, >> +}; >> + >> +static void m2sxxx_soc_types(void) >> +{ >> + type_register_static(&m2sxxx_soc_info); >> +} >> + >> +type_init(m2sxxx_soc_types) >> diff --git a/include/hw/arm/msf2-soc.h b/include/hw/arm/msf2-soc.h >> new file mode 100644 >> index 0000000..eb239fa >> --- /dev/null >> +++ b/include/hw/arm/msf2-soc.h >> @@ -0,0 +1,66 @@ >> +/* >> + * Microsemi Smartfusion2 SoC >> + * >> + * Copyright (c) 2017 Subbaraya Sundeep >> + * >> + * Permission is hereby granted, free of charge, to any person obtainin= g >> a copy >> + * of this software and associated documentation files (the "Software")= , >> to deal >> + * in the Software without restriction, including without limitation th= e >> rights >> + * to use, copy, modify, merge, publish, distribute, sublicense, and/or >> sell >> + * copies of the Software, and to permit persons to whom the Software i= s >> + * furnished to do so, subject to the following conditions: >> + * >> + * The above copyright notice and this permission notice shall be >> included in >> + * all copies or substantial portions of the Software. >> + * >> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, >> EXPRESS OR >> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF >> MERCHANTABILITY, >> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT >> SHALL >> + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR >> OTHER >> + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, >> ARISING FROM, >> + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER >> DEALINGS IN >> + * THE SOFTWARE. >> + */ >> + >> +#ifndef HW_ARM_MSF2_SOC_H >> +#define HW_ARM_MSF2_SOC_H >> + >> +#include "hw/arm/armv7m.h" >> +#include "hw/timer/mss-timer.h" >> +#include "hw/misc/msf2-sysreg.h" >> +#include "hw/ssi/mss-spi.h" >> + >> +#define TYPE_MSF2_SOC "msf2-soc" >> +#define MSF2_SOC(obj) OBJECT_CHECK(MSF2State, (obj), TYPE_MSF2_SOC) >> + >> +#define MSF2_NUM_SPIS 2 >> +#define MSF2_NUM_UARTS 2 >> + >> +/* >> + * System timer consists of two programmable 32-bit >> + * decrementing counters that generate individual interrupts to >> + * the Cortex-M3 processor >> + */ >> +#define MSF2_NUM_TIMERS 2 >> + >> +typedef struct MSF2State { >> + /*< private >*/ >> + SysBusDevice parent_obj; >> + /*< public >*/ >> + >> + ARMv7MState armv7m; >> + >> + char *part_name; >> + uint64_t envm_size; >> + uint64_t esram_size; >> + >> + uint32_t m3clk; >> + uint32_t apb0div; >> + uint32_t apb1div; >> + >> + MSF2SysregState sysreg; >> + MSSTimerState timer; >> + MSSSpiState spi[MSF2_NUM_SPIS]; >> +} MSF2State; >> + >> +#endif >> > > Almost there :) > > Are you OK to: > - register eNVM as ROM > - check UARTs? > Yeah I will change. Thank you :) Sundeep > > Regards, > > Phil. > --001a11425890ca68b80557f79757 Content-Type: text/html; charset="UTF-8" Content-Transfer-Encoding: quoted-printable
Hi Philippe,

On Wed, Aug 30, 2017 at 8:15 AM, Philippe Mathieu-Daud=C3=A9 <f4= bug@amsat.org> wrote:
Hi Subbaraya,


On 08/28/2017 01:38 PM, Subbaraya Sundeep wrote:
Smartfusion2 SoC has hardened Microcontroller subsystem
and flash based FPGA fabric. This patch adds support for
Microcontroller subsystem in the SoC.

Signed-off-by: Subbaraya Sundeep <sundeep.lkml@gmail.com>
---
=C2=A0 default-configs/arm-softmmu.ma= k |=C2=A0 =C2=A01 +
=C2=A0 hw/arm/Makefile.objs=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 |=C2= =A0 =C2=A01 +
=C2=A0 hw/arm/msf2-soc.c=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0| 215 ++++++++++++++++++++++++++++++++++++++++
=C2=A0 include/hw/arm/msf2-soc.h=C2=A0 =C2=A0 =C2=A0 =C2=A0|=C2=A0 66 +++++= +++++++
=C2=A0 4 files changed, 283 insertions(+)
=C2=A0 create mode 100644 hw/arm/msf2-soc.c
=C2=A0 create mode 100644 include/hw/arm/msf2-soc.h

diff --git a/default-configs/arm-softmmu.mak b/default-configs/arm-sof= tmmu.mak
index bbdd3c1..5059d13 100644
--- a/default-configs/arm-softmmu.mak
+++ b/default-configs/arm-softmmu.mak
@@ -129,3 +129,4 @@ CONFIG_ACPI=3Dy
=C2=A0 CONFIG_SMBIOS=3Dy
=C2=A0 CONFIG_ASPEED_SOC=3Dy
=C2=A0 CONFIG_GPIO_KEY=3Dy
+CONFIG_MSF2=3Dy
diff --git a/hw/arm/Makefile.objs b/hw/arm/Makefile.objs
index a2e56ec..df36a03 100644
--- a/hw/arm/Makefile.objs
+++ b/hw/arm/Makefile.objs
@@ -19,3 +19,4 @@ obj-$(CONFIG_FSL_IMX31) +=3D fsl-imx31.o kzm.o
=C2=A0 obj-$(CONFIG_FSL_IMX6) +=3D fsl-imx6.o sabrelite.o
=C2=A0 obj-$(CONFIG_ASPEED_SOC) +=3D aspeed_soc.o aspeed.o
=C2=A0 obj-$(CONFIG_MPS2) +=3D mps2.o
+obj-$(CONFIG_MSF2) +=3D msf2-soc.o
diff --git a/hw/arm/msf2-soc.c b/hw/arm/msf2-soc.c
new file mode 100644
index 0000000..276eec5
--- /dev/null
+++ b/hw/arm/msf2-soc.c
@@ -0,0 +1,215 @@
+/*
+ * SmartFusion2 SoC emulation.
+ *
+ * Copyright (c) 2017 Subbaraya Sundeep <sundeep.lkml@gmail.com>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a= copy
+ * of this software and associated documentation files (the "Software= "), to deal
+ * in the Software without restriction, including without limitation the r= ights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or se= ll
+ * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included= in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIN= D, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY= ,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL=
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OT= HER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING= FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS = IN
+ * THE SOFTWARE.
+ */
+
+#include "qemu/osdep.h"
+#include "qapi/error.h"
+#include "qemu-common.h"
+#include "hw/arm/arm.h"
+#include "exec/address-spaces.h"
+#include "hw/char/serial.h"
+#include "hw/boards.h"
+#include "sysemu/block-backend.h"
+#include "qemu/cutils.h"
+#include "hw/arm/msf2-soc.h"
+
+#define MSF2_TIMER_BASE=C2=A0 =C2=A0 =C2=A0 =C2=A00x40004000
+#define MSF2_SYSREG_BASE=C2=A0 =C2=A0 =C2=A0 0x40038000
+
+#define ENVM_BASE_ADDRESS=C2=A0 =C2=A0 =C2=A00x60000000
+
+#define SRAM_BASE_ADDRESS=C2=A0 =C2=A0 =C2=A00x20000000
+
+#define MSF2_ENVM_SIZE=C2=A0 =C2=A0 =C2=A0 =C2=A0 (512 * K_BYTE)
+#define MSF2_ESRAM_SIZE=C2=A0 =C2=A0 =C2=A0 =C2=A0(64 * K_BYTE)

Eventually you should name those _SIZE_MAX.

I agree and will change to SIZE_MAX=C2=A0
=C2=A0

I miscorrected you in v4, 64kB is true with SECDED disabled, else the SoC i= s designed for 80kB. Not a big deal, we can add a "SECDED not supporte= d" warning later.
Can you add a comment about it?

Sure will a= dd a comment about it. =C2=A0


+
+static const uint32_t spi_addr[MSF2_NUM_SPIS] =3D { 0x40001000 , 0x4001100= 0 };
+static const uint32_t uart_addr[MSF2_NUM_UARTS] =3D { 0x40000000 , 0x40010= 000 };
+
+static const int spi_irq[MSF2_NUM_SPIS] =3D { 2, 3 };
+static const int uart_irq[MSF2_NUM_UARTS] =3D { 10, 11 };
+static const int timer_irq[MSF2_NUM_TIMERS] =3D { 14, 15 };
+
+static void m2sxxx_soc_initfn(Object *obj)
+{
+=C2=A0 =C2=A0 MSF2State *s =3D MSF2_SOC(obj);
+=C2=A0 =C2=A0 int i;
+
+=C2=A0 =C2=A0 object_initialize(&s->armv7m, sizeof(s->armv7m), T= YPE_ARMV7M);
+=C2=A0 =C2=A0 qdev_set_parent_bus(DEVICE(&s->armv7m), sysbus_g= et_default());
+
+=C2=A0 =C2=A0 object_initialize(&s->sysreg, sizeof(s->sysreg), T= YPE_MSF2_SYSREG);
+=C2=A0 =C2=A0 qdev_set_parent_bus(DEVICE(&s->sysreg), sysbus_g= et_default());
+
+=C2=A0 =C2=A0 object_initialize(&s->timer, sizeof(s->timer), TYP= E_MSS_TIMER);
+=C2=A0 =C2=A0 qdev_set_parent_bus(DEVICE(&s->timer), sysbus_ge= t_default());
+

What about the UARTs?

+=C2=A0 =C2=A0 for (i =3D 0; i < MSF2_NUM_SPIS; i++) {
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 object_initialize(&s->spi[i], sizeof(s-= >spi[i]),
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 TYPE_MSS_SPI);
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 qdev_set_parent_bus(DEVICE(&s->spi= [i]), sysbus_get_default());
+=C2=A0 =C2=A0 }
+}
+
+static void m2sxxx_soc_realize(DeviceState *dev_soc, Error **errp)
+{
+=C2=A0 =C2=A0 MSF2State *s =3D MSF2_SOC(dev_soc);
+=C2=A0 =C2=A0 DeviceState *dev, *armv7m;
+=C2=A0 =C2=A0 SysBusDevice *busdev;
+=C2=A0 =C2=A0 Error *err =3D NULL;
+=C2=A0 =C2=A0 int i;
+
+=C2=A0 =C2=A0 MemoryRegion *system_memory =3D get_system_memory();
+=C2=A0 =C2=A0 MemoryRegion *nvm =3D g_new(MemoryRegion, 1);
+=C2=A0 =C2=A0 MemoryRegion *nvm_alias =3D g_new(MemoryRegion, 1);
+=C2=A0 =C2=A0 MemoryRegion *sram =3D g_new(MemoryRegion, 1);
+
+=C2=A0 =C2=A0 memory_region_init_ram(nvm, NULL, "MSF2.eNVM", s-&= gt;envm_size,
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0&error_fatal);

Why do you initialize as RAM? I'd rather use memory_region_init_rom_dev= ice() here, so you can boot a dumped eNVM flash.

=
Just followed other SoC(like stm32), booting a dumped eNVM flash= ? I am not clear about this how to do that?=C2=A0


+
+=C2=A0 =C2=A0 /*
+=C2=A0 =C2=A0 =C2=A0* On power-on, the eNVM region 0x60000000 is automatic= ally
+=C2=A0 =C2=A0 =C2=A0* remapped to the Cortex-M3 processor executable regio= n
+=C2=A0 =C2=A0 =C2=A0* start address (0x0). We do not support remapping oth= er eNVM,
+=C2=A0 =C2=A0 =C2=A0* eSRAM and DDR regions by guest(via Sysreg) currently= .
+=C2=A0 =C2=A0 =C2=A0*/
+=C2=A0 =C2=A0 memory_region_init_alias(nvm_alias, NULL, "MSF2.eN= VM.alias",
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0nvm, 0, s->envm_size);
+
+=C2=A0 =C2=A0 memory_region_set_readonly(nvm, true);
+=C2=A0 =C2=A0 memory_region_set_readonly(nvm_alias, true);

Hmmm not sure the alias needs this.

Once we= change to rom then memory_region_set_readonly =C2=A0will go away.


+
+=C2=A0 =C2=A0 memory_region_add_subregion(system_memory, ENVM_BASE_AD= DRESS, nvm);
+=C2=A0 =C2=A0 memory_region_add_subregion(system_memory, 0, nvm_alias= );
+
+=C2=A0 =C2=A0 memory_region_init_ram(sram, NULL, "MSF2.eSRAM", s= ->esram_size,
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0&error_fatal);
+=C2=A0 =C2=A0 memory_region_add_subregion(system_memory, SRAM_BASE_AD= DRESS, sram);
+
+=C2=A0 =C2=A0 armv7m =3D DEVICE(&s->armv7m);
+=C2=A0 =C2=A0 qdev_prop_set_uint32(armv7m, "num-irq", 81);
+=C2=A0 =C2=A0 qdev_prop_set_string(armv7m, "cpu-model", "co= rtex-m3");
+=C2=A0 =C2=A0 object_property_set_link(OBJECT(&s->armv7m), OBJ= ECT(get_system_memory()),
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0"memory&quo= t;, &error_abort);
+=C2=A0 =C2=A0 object_property_set_bool(OBJECT(&s->armv7m), tru= e, "realized", &err);
+=C2=A0 =C2=A0 if (err !=3D NULL) {
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 error_propagate(errp, err);
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 return;
+=C2=A0 =C2=A0 }
+
+=C2=A0 =C2=A0 system_clock_scale =3D NANOSECONDS_PER_SECOND / s->m3clk;=
+
+=C2=A0 =C2=A0 for (i =3D 0; i < MSF2_NUM_UARTS; i++) {
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 if (serial_hds[i]) {

I think they might be issues if you start QEMU without -serial and then use= a firmware polling for an uart, the device won't be mapped and the mem= ory accesses are mostly ignored.

I'd rather use:

=C2=A0 =C2=A0 for (i =3D 0; i < MSF2_NUM_UARTS && i < MAX_SER= IAL_PORTS; i++) {
=C2=A0 =C2=A0 =C2=A0 =C2=A0 static const char *serial[] =3D {"serial0&= quot;, "serial1"};

=C2=A0 =C2=A0 =C2=A0 =C2=A0 if (!serial_hds[i]) {
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 serial_hds[i] =3D qemu_chr_new(se= rial[i], "null");

=C2=A0 =C2=A0 =C2=A0 =C2=A0 }

I agree. I will go through this and change.=C2=A0

+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 serial_mm_init(get_system_memory(), uart_addr[i], 2,
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0qdev_get_gpio_in(armv7m, uart_irq[i]),
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0115200, serial_hds[i], DEVICE_NATIVE_ENDIAN);
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 }
+=C2=A0 =C2=A0 }
+
+=C2=A0 =C2=A0 dev =3D DEVICE(&s->timer);
+=C2=A0 =C2=A0 /* APB0 clock is the timer input clock */
+=C2=A0 =C2=A0 qdev_prop_set_uint32(dev, "clock-frequency", s->= ;m3clk / s->apb0div);
+=C2=A0 =C2=A0 object_property_set_bool(OBJECT(&s->timer), true= , "realized", &err);
+=C2=A0 =C2=A0 if (err !=3D NULL) {
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 error_propagate(errp, err);
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 return;
+=C2=A0 =C2=A0 }
+=C2=A0 =C2=A0 busdev =3D SYS_BUS_DEVICE(dev);
+=C2=A0 =C2=A0 sysbus_mmio_map(busdev, 0, MSF2_TIMER_BASE);
+=C2=A0 =C2=A0 sysbus_connect_irq(busdev, 0,
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0qdev_get_gpio_in(armv7m, timer_irq[0]));
+=C2=A0 =C2=A0 sysbus_connect_irq(busdev, 1,
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0qdev_get_gpio_in(armv7m, timer_irq[1]));
+
+=C2=A0 =C2=A0 dev =3D DEVICE(&s->sysreg);
+=C2=A0 =C2=A0 qdev_prop_set_uint32(dev, "apb0divisor", s->apb= 0div);
+=C2=A0 =C2=A0 qdev_prop_set_uint32(dev, "apb1divisor", s->apb= 1div);
+=C2=A0 =C2=A0 object_property_set_bool(OBJECT(&s->sysreg), tru= e, "realized", &err);
+=C2=A0 =C2=A0 if (err !=3D NULL) {
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 error_propagate(errp, err);
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 return;
+=C2=A0 =C2=A0 }
+=C2=A0 =C2=A0 busdev =3D SYS_BUS_DEVICE(dev);
+=C2=A0 =C2=A0 sysbus_mmio_map(busdev, 0, MSF2_SYSREG_BASE);
+
+=C2=A0 =C2=A0 for (i =3D 0; i < MSF2_NUM_SPIS; i++) {
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 gchar *bus_name =3D g_strdup_printf("spi%= d", i);

move g_strdup_printf() down ...

+
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 object_property_set_bool(OBJECT(&s-&g= t;spi[i]), true, "realized", &err);
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 if (err !=3D NULL) {
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 g_free(bus_name);

so this g_free() is not needed.

+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 error_propagate(errp, err);
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 return;
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 }
+
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 sysbus_mmio_map(SYS_BUS_DEVICE(&s->= ;spi[i]), 0, spi_addr[i]);
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 sysbus_connect_irq(SYS_BUS_DEVICE(&s-= >spi[i]), 0,
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0qdev_get_gpio_in(armv7m, spi_irq[i]));
+
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 /* Alias controller SPI bus to the SoC itself = */

Here:
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0bus_name =3D g_strdup_printf("= ;spi%d", i);
=C2=A0
Ok will modify.= =C2=A0

+=C2=A0 =C2=A0 =C2=A0 =C2=A0 object_property_add_alias(OBJECT(s), bus_= name,

+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 OBJECT(&s->spi[i]), &q= uot;spi",
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 &error_abort);
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 g_free(bus_name);
+=C2=A0 =C2=A0 }
+}
+
+static Property m2sxxx_soc_properties[] =3D {
+=C2=A0 =C2=A0 /*
+=C2=A0 =C2=A0 =C2=A0* part name specifies the type of SmartFusion2 device = variant(this
+=C2=A0 =C2=A0 =C2=A0* property is for information purpose only.
+=C2=A0 =C2=A0 =C2=A0*/
+=C2=A0 =C2=A0 DEFINE_PROP_STRING("part-name", MSF2State, pa= rt_name),
+=C2=A0 =C2=A0 DEFINE_PROP_UINT64("eNVM-size", MSF2State, en= vm_size, MSF2_ENVM_SIZE),
+=C2=A0 =C2=A0 DEFINE_PROP_UINT64("eSRAM-size", MSF2State, e= sram_size, MSF2_ESRAM_SIZE),
+=C2=A0 =C2=A0 /* Libero GUI shows 100Mhz as default for clocks */
+=C2=A0 =C2=A0 DEFINE_PROP_UINT32("m3clk", MSF2State, m3clk, 100 = * 1000000),
+=C2=A0 =C2=A0 /* default divisors in Libero GUI */
+=C2=A0 =C2=A0 DEFINE_PROP_UINT32("apb0div", MSF2State, apb0div, = 2),
+=C2=A0 =C2=A0 DEFINE_PROP_UINT32("apb1div", MSF2State, apb1div, = 2),
+=C2=A0 =C2=A0 DEFINE_PROP_END_OF_LIST(),
+};
+
+static void m2sxxx_soc_class_init(ObjectClass *klass, void *data)
+{
+=C2=A0 =C2=A0 DeviceClass *dc =3D DEVICE_CLASS(klass);
+
+=C2=A0 =C2=A0 dc->realize =3D m2sxxx_soc_realize;
+=C2=A0 =C2=A0 dc->props =3D m2sxxx_soc_properties;
+}
+
+static const TypeInfo m2sxxx_soc_info =3D {
+=C2=A0 =C2=A0 .name=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =3D TYPE_MSF2_SOC, +=C2=A0 =C2=A0 .parent=C2=A0 =C2=A0 =C2=A0 =C2=A0 =3D TYPE_SYS_BUS_DEVICE,<= br> +=C2=A0 =C2=A0 .instance_size =3D sizeof(MSF2State),
+=C2=A0 =C2=A0 .instance_init =3D m2sxxx_soc_initfn,
+=C2=A0 =C2=A0 .class_init=C2=A0 =C2=A0 =3D m2sxxx_soc_class_init,
+};
+
+static void m2sxxx_soc_types(void)
+{
+=C2=A0 =C2=A0 type_register_static(&m2sxxx_soc_info);
+}
+
+type_init(m2sxxx_soc_types)
diff --git a/include/hw/arm/msf2-soc.h b/include/hw/arm/msf2-soc.h
new file mode 100644
index 0000000..eb239fa
--- /dev/null
+++ b/include/hw/arm/msf2-soc.h
@@ -0,0 +1,66 @@
+/*
+ * Microsemi Smartfusion2 SoC
+ *
+ * Copyright (c) 2017 Subbaraya Sundeep <sundeep.lkml@gmail.com>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a= copy
+ * of this software and associated documentation files (the "Software= "), to deal
+ * in the Software without restriction, including without limitation the r= ights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or se= ll
+ * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included= in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIN= D, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY= ,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL=
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OT= HER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING= FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS = IN
+ * THE SOFTWARE.
+ */
+
+#ifndef HW_ARM_MSF2_SOC_H
+#define HW_ARM_MSF2_SOC_H
+
+#include "hw/arm/armv7m.h"
+#include "hw/timer/mss-timer.h"
+#include "hw/misc/msf2-sysreg.h"
+#include "hw/ssi/mss-spi.h"
+
+#define TYPE_MSF2_SOC=C2=A0 =C2=A0 =C2=A0"msf2-soc"
+#define MSF2_SOC(obj)=C2=A0 =C2=A0 =C2=A0OBJECT_CHECK(MSF2State, (obj), TY= PE_MSF2_SOC)
+
+#define MSF2_NUM_SPIS=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A02
+#define MSF2_NUM_UARTS=C2=A0 =C2=A0 =C2=A0 =C2=A0 2
+
+/*
+ * System timer consists of two programmable 32-bit
+ * decrementing counters that generate individual interrupts to
+ * the Cortex-M3 processor
+ */
+#define MSF2_NUM_TIMERS=C2=A0 =C2=A0 =C2=A0 =C2=A02
+
+typedef struct MSF2State {
+=C2=A0 =C2=A0 /*< private >*/
+=C2=A0 =C2=A0 SysBusDevice parent_obj;
+=C2=A0 =C2=A0 /*< public >*/
+
+=C2=A0 =C2=A0 ARMv7MState armv7m;
+
+=C2=A0 =C2=A0 char *part_name;
+=C2=A0 =C2=A0 uint64_t envm_size;
+=C2=A0 =C2=A0 uint64_t esram_size;
+
+=C2=A0 =C2=A0 uint32_t m3clk;
+=C2=A0 =C2=A0 uint32_t apb0div;
+=C2=A0 =C2=A0 uint32_t apb1div;
+
+=C2=A0 =C2=A0 MSF2SysregState sysreg;
+=C2=A0 =C2=A0 MSSTimerState timer;
+=C2=A0 =C2=A0 MSSSpiState spi[MSF2_NUM_SPIS];
+} MSF2State;
+
+#endif

Almost there :)

Are you OK to:
- register eNVM as ROM
- check UARTs?

Yeah I will change. Than= k you :)

Sundeep
=C2=A0

Regards,

Phil.

--001a11425890ca68b80557f79757-- From MAILER-DAEMON Wed Aug 30 08:24:55 2017 Received: from list by lists.gnu.org with archive (Exim 4.71) id 1dn23D-0000Jz-Mr for mharc-qemu-arm@gnu.org; Wed, 30 Aug 2017 08:24:55 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:36595) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dn23A-0000H9-Ex for qemu-arm@nongnu.org; Wed, 30 Aug 2017 08:24:54 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dn238-0002mt-IP for qemu-arm@nongnu.org; Wed, 30 Aug 2017 08:24:52 -0400 Received: from mail-vk0-x22b.google.com ([2607:f8b0:400c:c05::22b]:34854) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1dn234-0002lS-AV; Wed, 30 Aug 2017 08:24:46 -0400 Received: by mail-vk0-x22b.google.com with SMTP id z187so17019617vkd.2; Wed, 30 Aug 2017 05:24:46 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=mime-version:in-reply-to:references:from:date:message-id:subject:to :cc; bh=nRPmrAoUz/kOGFdyV0l+r+3O1F7We0SgwqTq6eaJL5c=; b=NJxfMyJic+zV+aG2AISGmJSgMfBq2gsdQxOJBAuE3US9bx1ZuwPscv89Y63FgLSoGM A+ve7eREjjej058Q1MmnKM5KGIKFk3nj6zT6CE2458TT54aSHg4cmHep+LzH7MeacJJM 40zqy+4ERbuy3BIo6IWWdHlWVrx3lJoYYC3xYDVA+FCdd5QYZJaWvIPAbsG+YdrnhB9+ FDZ1cIKs2FohVddwQ3Bahn7S5vJaNM/M+QPylPyzH7NCmfwk6cSRYYoZY5RKhNcz9rr0 LzhbKG3cLlNbQ4BksvcxEZT2VBNwP0WRFS9WCnuezQt/q1kxCORuzt6oue24EzFxuGTk gLMQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:in-reply-to:references:from:date :message-id:subject:to:cc; bh=nRPmrAoUz/kOGFdyV0l+r+3O1F7We0SgwqTq6eaJL5c=; b=pocIhCT4OWlOzAyMU+JrgDkLsg241mjr+f6fsrwW82JBmeZfJlMnDTKvAsgheNa8UO zhRp2jCkGaWjo3vVKt2lvJBXUV7nX3Bvrbk7AA6xCAE5dizVjV9TNxFrMC4jxs12TAtN 18jbRw06E3at6f1fnopoVtat/SUOtHuzNPHBl4X5UZRO6Gfbk02LGHjp4zzrDF07cu+D +NkckTzytY7XpebM8O9dAQ0/Cq4JJZmeV4EpWV+tJESaAJx/BP2e+M8DWPY1bgEh99AF LcytB3SjdZlsv0PvLIR0nrzf1Z4tJ3SbFvmYKL5mjuM3kAbWMq8gH6uNuAko7p49Fb6j /zpA== X-Gm-Message-State: AHYfb5jZV8F86EOJnaKoZbwP7lmokRoIT1QaR4GLzjQ5bKt6Cg+ohWo0 0u4XeuxskPT7vQ4Qsrvp5gNAMUO07A== X-Google-Smtp-Source: ADKCNb42mrVpRtxoud6t6POxoa/TzdQf4IQfPFIL3kqxZAztdqRnuyZWhXGP6Iz+UT7DDkUMCUiN8xPS9bzItZJ8pUk= X-Received: by 10.31.248.3 with SMTP id w3mr764782vkh.53.1504095885661; Wed, 30 Aug 2017 05:24:45 -0700 (PDT) MIME-Version: 1.0 Received: by 10.176.75.196 with HTTP; Wed, 30 Aug 2017 05:24:45 -0700 (PDT) In-Reply-To: References: <1503938283-12404-1-git-send-email-sundeep.lkml@gmail.com> <1503938283-12404-6-git-send-email-sundeep.lkml@gmail.com> From: sundeep subbaraya Date: Wed, 30 Aug 2017 17:54:45 +0530 Message-ID: To: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= Cc: QEMU Developers , qemu-arm , Peter Maydell , Peter Crosthwaite , Alistair Francis Content-Type: multipart/alternative; boundary="94eb2c149c6cf91bf10557f79c92" X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400c:c05::22b Subject: Re: [Qemu-arm] [Qemu devel v7 PATCH 5/5] msf2: Add Emcraft's Smartfusion2 SOM kit X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 30 Aug 2017 12:24:54 -0000 --94eb2c149c6cf91bf10557f79c92 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Hi Philippe, On Wed, Aug 30, 2017 at 7:18 AM, Philippe Mathieu-Daud=C3=A9 wrote: > Hi Subbaraya, > > > On 08/28/2017 01:38 PM, Subbaraya Sundeep wrote: > >> Emulated Emcraft's Smartfusion2 System On Module starter >> kit. >> >> Signed-off-by: Subbaraya Sundeep >> --- >> hw/arm/Makefile.objs | 2 +- >> hw/arm/msf2-som.c | 94 ++++++++++++++++++++++++++++++ >> ++++++++++++++++++++++ >> 2 files changed, 95 insertions(+), 1 deletion(-) >> create mode 100644 hw/arm/msf2-som.c >> >> diff --git a/hw/arm/Makefile.objs b/hw/arm/Makefile.objs >> index df36a03..e81a7dc 100644 >> --- a/hw/arm/Makefile.objs >> +++ b/hw/arm/Makefile.objs >> @@ -19,4 +19,4 @@ obj-$(CONFIG_FSL_IMX31) +=3D fsl-imx31.o kzm.o >> obj-$(CONFIG_FSL_IMX6) +=3D fsl-imx6.o sabrelite.o >> obj-$(CONFIG_ASPEED_SOC) +=3D aspeed_soc.o aspeed.o >> obj-$(CONFIG_MPS2) +=3D mps2.o >> -obj-$(CONFIG_MSF2) +=3D msf2-soc.o >> +obj-$(CONFIG_MSF2) +=3D msf2-soc.o msf2-som.o >> diff --git a/hw/arm/msf2-som.c b/hw/arm/msf2-som.c >> new file mode 100644 >> index 0000000..fd89ba9 >> --- /dev/null >> +++ b/hw/arm/msf2-som.c >> @@ -0,0 +1,94 @@ >> +/* >> + * SmartFusion2 SOM starter kit(from Emcraft) emulation. >> + * >> + * Copyright (c) 2017 Subbaraya Sundeep >> + * >> + * Permission is hereby granted, free of charge, to any person obtainin= g >> a copy >> + * of this software and associated documentation files (the "Software")= , >> to deal >> + * in the Software without restriction, including without limitation th= e >> rights >> + * to use, copy, modify, merge, publish, distribute, sublicense, and/or >> sell >> + * copies of the Software, and to permit persons to whom the Software i= s >> + * furnished to do so, subject to the following conditions: >> + * >> + * The above copyright notice and this permission notice shall be >> included in >> + * all copies or substantial portions of the Software. >> + * >> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, >> EXPRESS OR >> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF >> MERCHANTABILITY, >> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT >> SHALL >> + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR >> OTHER >> + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, >> ARISING FROM, >> + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER >> DEALINGS IN >> + * THE SOFTWARE. >> + */ >> + >> +#include "qemu/osdep.h" >> +#include "qapi/error.h" >> +#include "hw/boards.h" >> +#include "hw/arm/arm.h" >> +#include "exec/address-spaces.h" >> +#include "qemu/cutils.h" >> +#include "hw/arm/msf2-soc.h" >> + >> +#define DDR_BASE_ADDRESS 0xA0000000 >> +#define DDR_SIZE (64 * M_BYTE) >> + >> +#define M2S010_ENVM_SIZE (256 * K_BYTE) >> +#define M2S010_ESRAM_SIZE (64 * K_BYTE) >> + >> +static void emcraft_sf2_init(MachineState *machine) >> > > Since Emcraft can produce an upgraded SF2 SoC based on a different MCU, I > prefer you rename it: > > static void emcraft_sf2_s2s010_init(MachineState *machine) Ok will change. > > > +{ >> + DeviceState *dev; >> + DeviceState *spi_flash; >> + MSF2State *soc; >> + DriveInfo *dinfo =3D drive_get_next(IF_MTD); >> + qemu_irq cs_line; >> + SSIBus *spi_bus; >> + MemoryRegion *sysmem =3D get_system_memory(); >> + MemoryRegion *ddr =3D g_new(MemoryRegion, 1); >> + >> + memory_region_init_ram(ddr, NULL, "ddr-ram", DDR_SIZE, >> + &error_fatal); >> + memory_region_add_subregion(sysmem, DDR_BASE_ADDRESS, ddr); >> + >> + dev =3D qdev_create(NULL, TYPE_MSF2_SOC); >> + qdev_prop_set_string(dev, "part-name", "M2S010"); >> + qdev_prop_set_uint64(dev, "eNVM-size", M2S010_ENVM_SIZE); >> + qdev_prop_set_uint64(dev, "eSRAM-size", M2S010_ESRAM_SIZE); >> + >> + /* >> + * CPU clock and peripheral clocks(APB0, APB1)are configurable >> + * in Libero. CPU clock is divided by APB0 and APB1 divisors for >> + * peripherals. Emcraft's SoM kit comes with these settings by >> default. >> + */ >> + qdev_prop_set_uint32(dev, "m3clk", 142 * 1000000); >> + qdev_prop_set_uint32(dev, "apb0div", 2); >> + qdev_prop_set_uint32(dev, "apb1div", 2); >> + >> + object_property_set_bool(OBJECT(dev), true, "realized", >> &error_fatal); >> + >> + soc =3D MSF2_SOC(dev); >> + >> + /* Attach SPI flash to SPI0 controller */ >> + spi_bus =3D (SSIBus *)qdev_get_child_bus(dev, "spi0"); >> + spi_flash =3D ssi_create_slave_no_init(spi_bus, "s25sl12801"); >> + qdev_prop_set_uint8(spi_flash, "spansion-cr2nv", 1); >> + if (dinfo) { >> + qdev_prop_set_drive(spi_flash, "drive", >> blk_by_legacy_dinfo(dinfo), >> + &error_fatal); >> + } >> + qdev_init_nofail(spi_flash); >> + cs_line =3D qdev_get_gpio_in_named(spi_flash, SSI_GPIO_CS, 0); >> + sysbus_connect_irq(SYS_BUS_DEVICE(&soc->spi[0]), 1, cs_line); >> + >> + armv7m_load_kernel(ARM_CPU(first_cpu), machine->kernel_filename, >> + soc->envm_size); >> +} >> + >> +static void emcraft_sf2_machine_init(MachineClass *mc) >> +{ >> + mc->desc =3D "SmartFusion2 SOM kit from Emcraft"; >> > > mc->desc =3D "SmartFusion2 SOM kit from Emcraft (M2S010)"; > > + mc->init =3D emcraft_sf2_init; >> > > mc->init =3D emcraft_sf2_s2s010_init; > > +} >> + >> +DEFINE_MACHINE("emcraft-sf2", emcraft_sf2_machine_init) >> > > Good work :) > With the changes: > Reviewed-by: Philippe Mathieu-Daud=C3=A9 > Thank you :) Sundeep --94eb2c149c6cf91bf10557f79c92 Content-Type: text/html; charset="UTF-8" Content-Transfer-Encoding: quoted-printable
Hi Philippe,

On Wed, Aug 30, 2017 at 7:18 AM, Philippe Mathieu-Daud=C3=A9 <f4= bug@amsat.org> wrote:
Hi Su= bbaraya,


On 08/28/2017 01:38 PM, Subbaraya Sundeep wrote:
Emulated Emcraft's Smartfusion2 System On Module starter
kit.

Signed-off-by: Subbaraya Sundeep <sundeep.lkml@gmail.com>
---
=C2=A0 hw/arm/Makefile.objs |=C2=A0 2 +-
=C2=A0 hw/arm/msf2-som.c=C2=A0 =C2=A0 | 94 ++++++++++++++++++++++++++++++++++++++++++++++++++++
=C2=A0 2 files changed, 95 insertions(+), 1 deletion(-)
=C2=A0 create mode 100644 hw/arm/msf2-som.c

diff --git a/hw/arm/Makefile.objs b/hw/arm/Makefile.objs
index df36a03..e81a7dc 100644
--- a/hw/arm/Makefile.objs
+++ b/hw/arm/Makefile.objs
@@ -19,4 +19,4 @@ obj-$(CONFIG_FSL_IMX31) +=3D fsl-imx31.o kzm.o
=C2=A0 obj-$(CONFIG_FSL_IMX6) +=3D fsl-imx6.o sabrelite.o
=C2=A0 obj-$(CONFIG_ASPEED_SOC) +=3D aspeed_soc.o aspeed.o
=C2=A0 obj-$(CONFIG_MPS2) +=3D mps2.o
-obj-$(CONFIG_MSF2) +=3D msf2-soc.o
+obj-$(CONFIG_MSF2) +=3D msf2-soc.o msf2-som.o
diff --git a/hw/arm/msf2-som.c b/hw/arm/msf2-som.c
new file mode 100644
index 0000000..fd89ba9
--- /dev/null
+++ b/hw/arm/msf2-som.c
@@ -0,0 +1,94 @@
+/*
+ * SmartFusion2 SOM starter kit(from Emcraft) emulation.
+ *
+ * Copyright (c) 2017 Subbaraya Sundeep <sundeep.lkml@gmail.com>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a= copy
+ * of this software and associated documentation files (the "Software= "), to deal
+ * in the Software without restriction, including without limitation the r= ights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or se= ll
+ * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included= in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIN= D, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY= ,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL=
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OT= HER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING= FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS = IN
+ * THE SOFTWARE.
+ */
+
+#include "qemu/osdep.h"
+#include "qapi/error.h"
+#include "hw/boards.h"
+#include "hw/arm/arm.h"
+#include "exec/address-spaces.h"
+#include "qemu/cutils.h"
+#include "hw/arm/msf2-soc.h"
+
+#define DDR_BASE_ADDRESS=C2=A0 =C2=A0 =C2=A0 0xA0000000
+#define DDR_SIZE=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 (64 * M_B= YTE)
+
+#define M2S010_ENVM_SIZE=C2=A0 =C2=A0 =C2=A0 (256 * K_BYTE)
+#define M2S010_ESRAM_SIZE=C2=A0 =C2=A0 =C2=A0(64 * K_BYTE)
+
+static void emcraft_sf2_init(MachineState *machine)

Since Emcraft can produce an upgraded SF2 SoC based on a different MCU, I p= refer you rename it:

static void emcraft_sf2_s2s010_init(MachineState *machine)

Ok will change.=C2=A0


+{
+=C2=A0 =C2=A0 DeviceState *dev;
+=C2=A0 =C2=A0 DeviceState *spi_flash;
+=C2=A0 =C2=A0 MSF2State *soc;
+=C2=A0 =C2=A0 DriveInfo *dinfo =3D drive_get_next(IF_MTD);
+=C2=A0 =C2=A0 qemu_irq cs_line;
+=C2=A0 =C2=A0 SSIBus *spi_bus;
+=C2=A0 =C2=A0 MemoryRegion *sysmem =3D get_system_memory();
+=C2=A0 =C2=A0 MemoryRegion *ddr =3D g_new(MemoryRegion, 1);
+
+=C2=A0 =C2=A0 memory_region_init_ram(ddr, NULL, "ddr-ram", DDR_S= IZE,
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0&error_fatal);
+=C2=A0 =C2=A0 memory_region_add_subregion(sysmem, DDR_BASE_ADDRESS, d= dr);
+
+=C2=A0 =C2=A0 dev =3D qdev_create(NULL, TYPE_MSF2_SOC);
+=C2=A0 =C2=A0 qdev_prop_set_string(dev, "part-name", "M2S01= 0");
+=C2=A0 =C2=A0 qdev_prop_set_uint64(dev, "eNVM-size", M2S010_ENVM= _SIZE);
+=C2=A0 =C2=A0 qdev_prop_set_uint64(dev, "eSRAM-size", M2S010_ESR= AM_SIZE);
+
+=C2=A0 =C2=A0 /*
+=C2=A0 =C2=A0 =C2=A0* CPU clock and peripheral clocks(APB0, APB1)are confi= gurable
+=C2=A0 =C2=A0 =C2=A0* in Libero. CPU clock is divided by APB0 and APB1 div= isors for
+=C2=A0 =C2=A0 =C2=A0* peripherals. Emcraft's SoM kit comes with these = settings by default.
+=C2=A0 =C2=A0 =C2=A0*/
+=C2=A0 =C2=A0 qdev_prop_set_uint32(dev, "m3clk", 142 * 1000000);=
+=C2=A0 =C2=A0 qdev_prop_set_uint32(dev, "apb0div", 2);
+=C2=A0 =C2=A0 qdev_prop_set_uint32(dev, "apb1div", 2);
+
+=C2=A0 =C2=A0 object_property_set_bool(OBJECT(dev), true, "reali= zed", &error_fatal);
+
+=C2=A0 =C2=A0 soc =3D MSF2_SOC(dev);
+
+=C2=A0 =C2=A0 /* Attach SPI flash to SPI0 controller */
+=C2=A0 =C2=A0 spi_bus =3D (SSIBus *)qdev_get_child_bus(dev, "spi0&quo= t;);
+=C2=A0 =C2=A0 spi_flash =3D ssi_create_slave_no_init(spi_bus, "s= 25sl12801");
+=C2=A0 =C2=A0 qdev_prop_set_uint8(spi_flash, "spansion-cr2nv", 1= );
+=C2=A0 =C2=A0 if (dinfo) {
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 qdev_prop_set_drive(spi_flash, "drive&quo= t;, blk_by_legacy_dinfo(dinfo),
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 &error_fatal);
+=C2=A0 =C2=A0 }
+=C2=A0 =C2=A0 qdev_init_nofail(spi_flash);
+=C2=A0 =C2=A0 cs_line =3D qdev_get_gpio_in_named(spi_flash, SSI_GPIO_= CS, 0);
+=C2=A0 =C2=A0 sysbus_connect_irq(SYS_BUS_DEVICE(&soc->spi[0]),= 1, cs_line);
+
+=C2=A0 =C2=A0 armv7m_load_kernel(ARM_CPU(first_cpu), machine->kern= el_filename,
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0soc->envm_size);
+}
+
+static void emcraft_sf2_machine_init(MachineClass *mc)
+{
+=C2=A0 =C2=A0 mc->desc =3D "SmartFusion2 SOM kit from Emcraft"= ;;

=C2=A0 =C2=A0 mc->desc =3D "SmartFusion2 SOM kit from Emcraft (M2S0= 10)";

+=C2=A0 =C2=A0 mc->init =3D emcraft_sf2_init;

=C2=A0 =C2=A0 mc->init =3D emcraft_sf2_s2s010_init;

+}
+
+DEFINE_MACHINE("emcraft-sf2", emcraft_sf2_machine_init)

Good work :)=C2=A0
With the changes:
Reviewed-by: Philippe Mathieu-Daud=C3=A9 <f4bug@amsat.org>

Thank you :)
Sundeep=C2=A0
=C2=A0

--94eb2c149c6cf91bf10557f79c92-- From MAILER-DAEMON Wed Aug 30 08:26:38 2017 Received: from list by lists.gnu.org with archive (Exim 4.71) id 1dn24s-00022n-4i for mharc-qemu-arm@gnu.org; Wed, 30 Aug 2017 08:26:38 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:37105) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dn24p-00021B-Hs for qemu-arm@nongnu.org; Wed, 30 Aug 2017 08:26:36 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dn24o-0003o3-KQ for qemu-arm@nongnu.org; Wed, 30 Aug 2017 08:26:35 -0400 Received: from mail-wr0-x229.google.com ([2a00:1450:400c:c0c::229]:37390) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1dn24o-0003nW-Db for qemu-arm@nongnu.org; Wed, 30 Aug 2017 08:26:34 -0400 Received: by mail-wr0-x229.google.com with SMTP id k9so5754928wre.4 for ; Wed, 30 Aug 2017 05:26:34 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:in-reply-to:references:from:date:message-id:subject:to :cc:content-transfer-encoding; bh=jXHr+IKuv1yS95nGXKo/6DvOBiIBnwQcIBujEx8i9G8=; b=b3hHJWJFpysuKaX46WnLMQ2FzKX7PXejQjLMylKo0fEkbMSYqlSzwXUcfdf746TKfL fqT7Ie3va9TZxfky73xsWZKFSgX4WV6Zff+E6CmHw3G/+37MLLTyr2uQHEmYopYPd6mO +l5toFCYmtU/6mkItqtIWcwkHopGh1TYISX2k= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:in-reply-to:references:from:date :message-id:subject:to:cc:content-transfer-encoding; bh=jXHr+IKuv1yS95nGXKo/6DvOBiIBnwQcIBujEx8i9G8=; b=EDMhXVKpfg5MRTOEWT8xrPopE99p89ijySs1vq3iBSxwhm2Gd/m+00XMY5Z3TT0a8n 0InUK5FWNaq0DNB5QMx8g2l5eUPwjwzxRqcOxblWQalRvh6B29GHIEYOppt/ql5uAkld I2PazcIBskO9PeB8TiPW7Jqeit7gGRB0++YN/QEofkKWQ2T5KXk8fawcxo7zpNAyM0SJ S+YH8kwVHVqF/9VUAil8KNxHc86M8/ODPi/pKmg91lMQ58rCCJOHLYMwz34QVzji+kgw 2OKaYocHfYvdE0Eej1dEaSVoC/DUr5mLmdhwOMkQFhgWBCyo7CjAdSFMioyRnn6WaLwz fCRg== X-Gm-Message-State: AHYfb5iexX0S4WMcnPDuu694Z55pvQ2OyGTVLLqUxZ9+jjjtKj87vyv2 5fF8tx6dqyb/p3mbX+W49PiD23i7j6Dn X-Received: by 10.223.128.39 with SMTP id 36mr934464wrk.11.1504095993324; Wed, 30 Aug 2017 05:26:33 -0700 (PDT) MIME-Version: 1.0 Received: by 10.223.134.54 with HTTP; Wed, 30 Aug 2017 05:26:12 -0700 (PDT) In-Reply-To: <10da5552-c90a-21e6-43ac-829932f64930@amsat.org> References: <1503938283-12404-1-git-send-email-sundeep.lkml@gmail.com> <1503938283-12404-5-git-send-email-sundeep.lkml@gmail.com> <10da5552-c90a-21e6-43ac-829932f64930@amsat.org> From: Peter Maydell Date: Wed, 30 Aug 2017 13:26:12 +0100 Message-ID: To: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= Cc: Subbaraya Sundeep , QEMU Developers , qemu-arm , Peter Crosthwaite , Alistair Francis Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:400c:c0c::229 Subject: Re: [Qemu-arm] [Qemu devel v7 PATCH 4/5] msf2: Add Smartfusion2 SoC X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 30 Aug 2017 12:26:36 -0000 On 30 August 2017 at 03:45, Philippe Mathieu-Daud=C3=A9 w= rote: > I think they might be issues if you start QEMU without -serial and then u= se > a firmware polling for an uart, the device won't be mapped and the memory > accesses are mostly ignored. > > I'd rather use: > > for (i =3D 0; i < MSF2_NUM_UARTS && i < MAX_SERIAL_PORTS; i++) { > static const char *serial[] =3D {"serial0", "serial1"}; > > if (!serial_hds[i]) { > serial_hds[i] =3D qemu_chr_new(serial[i], "null"); > > } > >> + serial_mm_init(get_system_memory(), uart_addr[i], 2, >> + qdev_get_gpio_in(armv7m, uart_irq[i]), >> + 115200, serial_hds[i], DEVICE_NATIVE_ENDIAN)= ; >> + } >> + } It would be better to fix serial_mm_init() to handle having a NULL chardev pointer, because we already have a lot of SoC code that just passes it serial_hds[] regardless. I'd leave this code as it is and we can fix serial_mm_init separately (somebody pointed out this issue for a xilinx board recently). thanks -- PMM From MAILER-DAEMON Wed Aug 30 10:47:20 2017 Received: from list by lists.gnu.org with archive (Exim 4.71) id 1dn4H2-0007Gn-O9 for mharc-qemu-arm@gnu.org; Wed, 30 Aug 2017 10:47:20 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:49918) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dn4H1-0007Fo-2D for qemu-arm@nongnu.org; Wed, 30 Aug 2017 10:47:19 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dn4Gy-0008T6-EW for qemu-arm@nongnu.org; Wed, 30 Aug 2017 10:47:19 -0400 Received: from mail-qt0-x242.google.com ([2607:f8b0:400d:c0d::242]:36358) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1dn4Gy-0008Sn-AC; Wed, 30 Aug 2017 10:47:16 -0400 Received: by mail-qt0-x242.google.com with SMTP id e2so5303442qta.3; Wed, 30 Aug 2017 07:47:16 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:subject:to:cc:references:from:message-id:date:user-agent :mime-version:in-reply-to:content-language:content-transfer-encoding; bh=hA/ke2mx4cc+kJjjRICjPgxunFfp01dcoUEQZKg9UsI=; b=rb+gg0a0Ul8V+wqIwWWokmzRuvztzH7sL/kqNr1yu/sLG8seF5NqM8yn24C8ebeWct tJe1NUTTd9ZkPYvCla7+fIrN1N4kf4OUwo40iNmCnk54Dr8em1/Ekr5Sp6DXLsinDdEl I1giz7BHrYfAVJaEHJZw9OrEDEMC1yIG51Xjc54rnW/2MpnluEw9h8LYH/+dlVsi+FsS Ew/7r8EG/ehH65Z2l36y0Lo5ki/R7XGVXnm7t8+rZJtOHPgmfdNq4PLfSw7nUDWjPxkw U5HOc2Cy2G0asqdSGqZLTkTe5qj7rVdQKQXo2wyYvaYZiBaWaB3+32qY6dAxULmzgpnu zWBA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:subject:to:cc:references:from:message-id :date:user-agent:mime-version:in-reply-to:content-language :content-transfer-encoding; bh=hA/ke2mx4cc+kJjjRICjPgxunFfp01dcoUEQZKg9UsI=; b=WonQlFn/Gv+sLi3NCLQKnjOaRqDC94jYzn1w6fZECAEMojgO6/yLeTauMWBfh2oHhC OKtxsgw5bv1+u/jOTJgvdyImB5LJAy20Ij4meyePM+XXYoeHP+Zr0Ee8uYcPeakaD6uM Pm8Uh+2utkjEJ9u9RegwTUkq3T6hvwn0xM+r0ajs62M5enKXLZXPZ+ELMRKJnoywTYGR E914ygRinSoSs+X3ATI0iuC4lY/ySMTjOqaeyNXnPTN9D5y/EGkzTeX5eakZEpxF5Skm CsP2gG3WK4Yyd7C5l4LAyvn1ATG/v7nFSQnE4NW6FpPqzbjiMJfRFJJ9dx8YcV/r5FMH 2QfA== X-Gm-Message-State: AHYfb5i4V1StAAsbsbsD1U24EUQkProtWFxsfmqdtOY+uIniN0RMYF15 3K2hUYbb6Ly4Og== X-Received: by 10.200.41.15 with SMTP id y15mr2285918qty.82.1504104435609; Wed, 30 Aug 2017 07:47:15 -0700 (PDT) Received: from [192.168.43.33] ([170.51.34.109]) by smtp.gmail.com with ESMTPSA id e30sm3693963qtg.54.2017.08.30.07.47.12 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 30 Aug 2017 07:47:14 -0700 (PDT) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= To: Peter Maydell Cc: Subbaraya Sundeep , QEMU Developers , qemu-arm , Peter Crosthwaite , Alistair Francis References: <1503938283-12404-1-git-send-email-sundeep.lkml@gmail.com> <1503938283-12404-5-git-send-email-sundeep.lkml@gmail.com> <10da5552-c90a-21e6-43ac-829932f64930@amsat.org> From: =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= Message-ID: <40ca8d07-75e5-e0b3-021e-5abaffd16b78@amsat.org> Date: Wed, 30 Aug 2017 11:47:07 -0300 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.3.0 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=utf-8; format=flowed Content-Language: en-US Content-Transfer-Encoding: 8bit X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400d:c0d::242 Subject: Re: [Qemu-arm] [Qemu devel v7 PATCH 4/5] msf2: Add Smartfusion2 SoC X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 30 Aug 2017 14:47:20 -0000 On 08/30/2017 09:26 AM, Peter Maydell wrote: > On 30 August 2017 at 03:45, Philippe Mathieu-Daudé wrote: >> I think they might be issues if you start QEMU without -serial and then use >> a firmware polling for an uart, the device won't be mapped and the memory >> accesses are mostly ignored. >> >> I'd rather use: >> >> for (i = 0; i < MSF2_NUM_UARTS && i < MAX_SERIAL_PORTS; i++) { >> static const char *serial[] = {"serial0", "serial1"}; >> >> if (!serial_hds[i]) { >> serial_hds[i] = qemu_chr_new(serial[i], "null"); >> >> } >> >>> + serial_mm_init(get_system_memory(), uart_addr[i], 2, >>> + qdev_get_gpio_in(armv7m, uart_irq[i]), >>> + 115200, serial_hds[i], DEVICE_NATIVE_ENDIAN); >>> + } >>> + } > > It would be better to fix serial_mm_init() to handle having > a NULL chardev pointer, because we already have a lot of > SoC code that just passes it serial_hds[] regardless. clever :) > I'd leave this code as it is and we can fix serial_mm_init > separately (somebody pointed out this issue for a xilinx > board recently). Sure. From MAILER-DAEMON Wed Aug 30 17:14:45 2017 Received: from list by lists.gnu.org with archive (Exim 4.71) id 1dnAJx-0003K1-Et for mharc-qemu-arm@gnu.org; Wed, 30 Aug 2017 17:14:45 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:39584) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dnAJu-0003HV-Qe for qemu-arm@nongnu.org; Wed, 30 Aug 2017 17:14:44 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dnAJt-000256-Qk for qemu-arm@nongnu.org; Wed, 30 Aug 2017 17:14:42 -0400 Received: from mail-qt0-x242.google.com ([2607:f8b0:400d:c0d::242]:36583) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1dnAJp-00023b-4N; Wed, 30 Aug 2017 17:14:37 -0400 Received: by mail-qt0-x242.google.com with SMTP id e2so6182449qta.3; Wed, 30 Aug 2017 14:14:37 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:subject:to:cc:references:from:message-id:date:user-agent :mime-version:in-reply-to:content-language:content-transfer-encoding; bh=ewGsQBQ5Opu++IcyvbcrCoJV6ozE5fgOJz+Gg1nz8Do=; b=iLS17Cjxj+yspVHRcatHmq12CeXLzMxTcyuJB2l1C2IleU7UtCu8QDC0VAez3NBMs9 6qDW6fPv9GdGHn3M5SLMhXQ3kOK5u40iVSILZfkFjus1M/fo21eqf5eaxB8rduToDEpL 8jNYbzLYOf8OWuO2QG0LN754z5tsngqpUedvBe+6cPt/vBiLpWGlt4AF257U0FSah/tx 8EOZ8jEDffaR9PknicXp7mUJqNtN5hZfI+A3lq2kJaQbtqTsBVU8uCcV+j93Q3VZf2h2 3qVT8U5R4uLEyHsx/o4bBO0PuQPpYsK2Jp80vA8JyOUDyB+1r599gnFEb3PBZLLskqMs ZrCA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:subject:to:cc:references:from:message-id :date:user-agent:mime-version:in-reply-to:content-language :content-transfer-encoding; bh=ewGsQBQ5Opu++IcyvbcrCoJV6ozE5fgOJz+Gg1nz8Do=; b=JSMF2Rs5TDccCZykkpL7Po3CIbe9QHWVauYXlR4q0ZgbW8e4+0MX7qb8gxsg1jC+3p a3BHDjnMVcKM1WO1zyVmhsgRIrLeTDvglQPWGmlOttRfH69lXw0ve02Rt18yGeA4qqxT 6j18nEYG4yS3Bc44NzkPkDv9ftFLQ4gidsnkKeF9XrUtJcqPT7zq97VrCBVFlAVpe+un u7Ptnepa3+JH/x9BSl/3afOLYlDfdRCPm7Mk8uBKXt0vYDMMQMI+O7L3EMC87Bf/7ZAB DMlQGmJU9FgHtRdMViEL3+U18rAsf9re7xKwwmBMhYxpb0CnzZr4o57P3H/13/I94UCM fdMQ== X-Gm-Message-State: AHYfb5g4TOawN9pVxR2ZPwe+S4Gp5xGjrNX3Pptje8kCzASS2CGMgmKM h6ij/vErNmzlB9oOkRc3rQ== X-Received: by 10.237.36.205 with SMTP id u13mr4058937qtc.124.1504127676343; Wed, 30 Aug 2017 14:14:36 -0700 (PDT) Received: from [192.168.1.10] ([181.93.89.178]) by smtp.gmail.com with ESMTPSA id a8sm4521048qtb.93.2017.08.30.14.14.34 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 30 Aug 2017 14:14:35 -0700 (PDT) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= To: Thomas Huth , Peter Maydell Cc: qemu-trivial@nongnu.org, qemu-arm@nongnu.org, qemu-devel@nongnu.org References: <20170728053610.15770-1-f4bug@amsat.org> <20170728053610.15770-3-f4bug@amsat.org> From: =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= Message-ID: Date: Wed, 30 Aug 2017 18:14:33 -0300 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.3.0 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=utf-8; format=flowed Content-Language: en-US Content-Transfer-Encoding: 8bit X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400d:c0d::242 Subject: Re: [Qemu-arm] [Qemu-devel] [PATCH 02/47] MAINTAINERS: add missing ARM entries X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 30 Aug 2017 21:14:44 -0000 On 07/28/2017 03:55 AM, Thomas Huth wrote: > On 28.07.2017 07:35, Philippe Mathieu-Daudé wrote: >> Signed-off-by: Philippe Mathieu-Daudé >> --- >> MAINTAINERS | 8 ++++++++ >> 1 file changed, 8 insertions(+) >> >> diff --git a/MAINTAINERS b/MAINTAINERS >> index 972118e70b..795f89f709 100644 >> --- a/MAINTAINERS >> +++ b/MAINTAINERS >> @@ -120,6 +120,8 @@ F: include/hw/cpu/a*mpcore.h >> F: disas/arm.c >> F: disas/arm-a64.cc >> F: disas/libvixl/ >> +F: default-configs/arm-softmmu.mak >> +F: default-configs/aarch64-softmmu.mak > > You've added this to the TCG CPU core section, but strictly speaking > these files are also used for the machine emulation in general (and also > for KVM). So not sure whether this is a good fit here ... up to Peter to > decide. You are right. > >> CRIS >> M: Edgar E. Iglesias >> @@ -380,6 +382,7 @@ M: Peter Maydell >> L: qemu-arm@nongnu.org >> S: Maintained >> F: hw/char/pl011.c >> +F: include/hw/char/pl011.h >> F: hw/display/pl110* >> F: hw/dma/pl080.c >> F: hw/dma/pl330.c >> @@ -402,14 +405,19 @@ F: hw/intc/arm* >> F: hw/intc/gic_internal.h >> F: hw/misc/a9scu.c >> F: hw/misc/arm11scu.c >> +F: hw/misc/arm_sysctl.c > > According to a comment in that file, it is about RealView/Versatile > boards instead, so this is the wrong section here? Wrong section indeed. > >> F: hw/timer/a9gtimer* >> F: hw/timer/arm_* >> +F: hw/timer/armv7m_systick.c > > How about rather removing the underscore in the previous wildcard entry? I also wondered, because I'm a slowly working branch where I try to boot some Marvell SoC, and I named the timer "armada_timer.c" following the Linux device-tree naming: https://www.kernel.org/doc/Documentation/devicetree/bindings/timer/marvell%2Carmada-370-xp-timer.txt But if I ever finish it I can add an exclude entry, so I'll follow your advice. > >> F: include/hw/arm/arm.h >> +F: include/hw/arm/armv7m*.h >> F: include/hw/intc/arm* >> F: include/hw/misc/a9scu.h >> F: include/hw/misc/arm11scu.h >> F: include/hw/timer/a9gtimer.h >> F: include/hw/timer/arm_mptimer.h >> +F: include/hw/timer/armv7m_systick.h >> +F: tests/test-arm-mptimer.c >> >> Exynos >> M: Igor Mitsyanko >> > > Thomas > From MAILER-DAEMON Wed Aug 30 17:55:50 2017 Received: from list by lists.gnu.org with archive (Exim 4.71) id 1dnAxh-0005Ep-T9 for mharc-qemu-arm@gnu.org; Wed, 30 Aug 2017 17:55:49 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:48730) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dnAxf-0005CV-ND for qemu-arm@nongnu.org; Wed, 30 Aug 2017 17:55:48 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dnAxe-0007Ys-Qi for qemu-arm@nongnu.org; Wed, 30 Aug 2017 17:55:47 -0400 Received: from mail-qt0-x242.google.com ([2607:f8b0:400d:c0d::242]:35372) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1dnAxa-0007RW-3e; Wed, 30 Aug 2017 17:55:42 -0400 Received: by mail-qt0-x242.google.com with SMTP id u11so6269513qtu.2; Wed, 30 Aug 2017 14:55:41 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=i7DICPMjD1LkEeBKl04nBKD47wy864nsi72KEboM26o=; b=jeh3tYU5epWh1U64H/vTahGgKgs+DJG6mmQxFBOr210l6E6NQlu7L2IyenFwj8Ye9F 7yTXuKiS2gAEu4Rawupf5u0Gl/ktL7Z7GalfrjqMKCbf1Q2oR+rrVR9xmZ/Fg+YFoJ3v aYteg3ZsGNNQ1LSt9CDP+OLce43FvgWMYN4MG23RjFvZ8vv/sxji1ZaTERZ4PnOUpWdS yQFmT1nKuzAGY7vnBDw2PnI1H05+DfssdUdTeaN7BkyIVa74+YdbXrWECw2bkWw7Mq7N qg2k3k28bK9D1fKqtOS+82aRwqOdEZI8gYRgYArcD+KeyuRK173jU07mdWpdZwbvbNHT Rjfw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=i7DICPMjD1LkEeBKl04nBKD47wy864nsi72KEboM26o=; b=uEN0e1oLYJ2DHWr359ybdA1cxEceBZCFeR1X7hih8X6w6ZvEOSPoNbwoMewkDVFClX HUDKPnGMYCtvbGaHFb3/6yH4+w2tigX7a6Ie/AcmaA14YpIMFV6Bu2AVz/b8dzGIeQ5x KEoiRviRjuSQOyw6w/1FNrP99PY1i3LYeOr+19rX2GBk2VykKMiZh2wlFodpsvumrc/+ oygYzA7MJSv1Uix+A6IuucfvaLx5PQGwv3wNCXSr/p6Nr07PhZQoRVm8UZOP8FvrkisD ZNqBu6aQ3VZMUfjvlC0iaZoAaOXBqlw5C5OZG8Lb0u/zQqNgqr96DCRjOg7Z02YG6VEp 0TuQ== X-Gm-Message-State: AHYfb5hIsyZZ9I0uvoCLBuiZ2ItN8ztjn9Fym/jHupIDI01qul/rmjmT tWrfb1bYVKv0zA== X-Received: by 10.200.22.34 with SMTP id p31mr4388556qtj.310.1504130141468; Wed, 30 Aug 2017 14:55:41 -0700 (PDT) Received: from yoga.offpageads.com ([181.93.89.178]) by smtp.gmail.com with ESMTPSA id w131sm4298690qkb.85.2017.08.30.14.55.38 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 30 Aug 2017 14:55:40 -0700 (PDT) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: Peter Maydell , Thomas Huth Cc: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , qemu-devel@nongnu.org, qemu-trivial@nongnu.org, qemu-arm@nongnu.org Date: Wed, 30 Aug 2017 18:55:07 -0300 Message-Id: <20170830215523.25278-2-f4bug@amsat.org> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20170830215523.25278-1-f4bug@amsat.org> References: <20170830215523.25278-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400d:c0d::242 Subject: [Qemu-arm] [PATCH v2 01/17] MAINTAINERS: add missing ARM entries X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 30 Aug 2017 21:55:48 -0000 Signed-off-by: Philippe Mathieu-Daudé --- MAINTAINERS | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/MAINTAINERS b/MAINTAINERS index ccee28b12d..b363e1b9c9 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -380,6 +380,7 @@ M: Peter Maydell L: qemu-arm@nongnu.org S: Maintained F: hw/char/pl011.c +F: include/hw/char/pl011.h F: hw/display/pl110* F: hw/dma/pl080.c F: hw/dma/pl330.c @@ -403,13 +404,15 @@ F: hw/intc/gic_internal.h F: hw/misc/a9scu.c F: hw/misc/arm11scu.c F: hw/timer/a9gtimer* -F: hw/timer/arm_* -F: include/hw/arm/arm.h +F: hw/timer/arm* +F: include/hw/arm/arm*.h F: include/hw/intc/arm* F: include/hw/misc/a9scu.h F: include/hw/misc/arm11scu.h F: include/hw/timer/a9gtimer.h F: include/hw/timer/arm_mptimer.h +F: include/hw/timer/armv7m_systick.h +F: tests/test-arm-mptimer.c Exynos M: Igor Mitsyanko -- 2.14.1 From MAILER-DAEMON Wed Aug 30 17:56:00 2017 Received: from list by lists.gnu.org with archive (Exim 4.71) id 1dnAxs-0005Sb-Lp for mharc-qemu-arm@gnu.org; Wed, 30 Aug 2017 17:56:00 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:48842) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dnAxp-0005P9-Gk for qemu-arm@nongnu.org; Wed, 30 Aug 2017 17:56:00 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dnAxl-0007bF-2f for qemu-arm@nongnu.org; Wed, 30 Aug 2017 17:55:57 -0400 Received: from mail-qk0-x242.google.com ([2607:f8b0:400d:c09::242]:36531) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1dnAxd-0007Wh-EC; Wed, 30 Aug 2017 17:55:45 -0400 Received: by mail-qk0-x242.google.com with SMTP id l65so6401130qkc.3; Wed, 30 Aug 2017 14:55:45 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=0lrX+2zmS/E/Mg9DUDtpbSnHfrsMuZMmPaZOxWswPzs=; b=M3HWq5F4xVrcpAbJt7H32dBaOfEQ04ernV191kRlVq0FoxjnMKoTRHbd36aSXkuIc2 Xjmao34m8bcc9jX0nQUB2fjrx9enlApiNjN/OziNL19YOJ3U75cBjIvNlAt8q7slEm07 mwncPO2pjWj5bYwWG7V5FZj+zZNb6vae5kV5hvvJmHIZRlGHD6WlXvsZ0zxVQERhl7oF bI8oSrNHMCZDVxk/NI3NSvwIwtzzHvc8fjOkSQZFnsoYZ6FVIna38LshsHbatD20tIyd CjV/SXO4618Y6Req2J2Tvna7s6W0tmSmLVWW/4W35iSFm6udk3UTn/5Bti1XxEMse6y/ GEow== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=0lrX+2zmS/E/Mg9DUDtpbSnHfrsMuZMmPaZOxWswPzs=; b=DOuJdWMQP9xYXn3MDJAJ4aOgIzCU+NrmcnVjLShSQCuJJ2/9HHkK7iBgXTbfhrXBEo 6k0BIdlOpuO0SFo5pVoDX4K1v5l6o0sO/NpWEV34aLHlv1Zir/JU6N5dN7bh/rGfLHq4 caZcr4MLsH1czjwZG5RNnf6LWGCtT8gUQZk6gpbauRsrSP9B3wMu/184bdywi/Q6DC6T ZyQP53ZnxvEvHMNguz8xSauPheN28kzYroZqK0NNCDl1MbrFap1mQl/xEfIkdC3olAfR HfE2RqenQbrnwKuZAlXT7rf6gl5hMGvzL0/qPTP2l1moR4MhJC08ql5Zek+22aN6yxnX /lNA== X-Gm-Message-State: AHYfb5iXDFqKC9PRqbj19DsV2/RqHGP0IRZjV07vRVEE4C5Nt0HAoVZ6 VBT7h16cjh9GKg== X-Received: by 10.55.126.195 with SMTP id z186mr1077195qkc.210.1504130144872; Wed, 30 Aug 2017 14:55:44 -0700 (PDT) Received: from yoga.offpageads.com ([181.93.89.178]) by smtp.gmail.com with ESMTPSA id w131sm4298690qkb.85.2017.08.30.14.55.41 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 30 Aug 2017 14:55:44 -0700 (PDT) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: Peter Maydell , Thomas Huth Cc: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , qemu-devel@nongnu.org, qemu-trivial@nongnu.org, qemu-arm@nongnu.org Date: Wed, 30 Aug 2017 18:55:08 -0300 Message-Id: <20170830215523.25278-3-f4bug@amsat.org> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20170830215523.25278-1-f4bug@amsat.org> References: <20170830215523.25278-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400d:c09::242 Subject: [Qemu-arm] [PATCH v2 02/17] MAINTAINERS: add missing Versatile PB entry X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 30 Aug 2017 21:56:00 -0000 Signed-off-by: Philippe Mathieu-Daudé --- MAINTAINERS | 1 + 1 file changed, 1 insertion(+) diff --git a/MAINTAINERS b/MAINTAINERS index b363e1b9c9..5b7891addc 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -515,6 +515,7 @@ M: Peter Maydell L: qemu-arm@nongnu.org S: Maintained F: hw/*/versatile* +F: hw/misc/arm_sysctl.c Xilinx Zynq M: Edgar E. Iglesias -- 2.14.1 From MAILER-DAEMON Wed Aug 30 23:53:32 2017 Received: from list by lists.gnu.org with archive (Exim 4.71) id 1dnGXs-0000lm-66 for mharc-qemu-arm@gnu.org; Wed, 30 Aug 2017 23:53:32 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:55573) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dnGXq-0000kS-Dy for qemu-arm@nongnu.org; Wed, 30 Aug 2017 23:53:31 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dnGXl-0006a3-Fy for qemu-arm@nongnu.org; Wed, 30 Aug 2017 23:53:30 -0400 Received: from mail-qt0-x243.google.com ([2607:f8b0:400d:c0d::243]:37251) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1dnGXj-0006ZH-Ao; Wed, 30 Aug 2017 23:53:23 -0400 Received: by mail-qt0-x243.google.com with SMTP id g13so6737605qta.4; Wed, 30 Aug 2017 20:53:23 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=Ptbb2tioMzNVHjabPeB1RPen2CnJsOp8RPHysN7rXAc=; b=D/FvpPx4CfFnNugnyZi/97vBkjNc6rNSELPe5B3VhwIMQm6SyMVP4v/qzvK2oPM4K7 gIvtCQFYdiMzOFfidBr3BsVFWuDdLXekLUFLdAPCAhE1Zyv3Y4pNx36GRlOmk1puk+s5 gv4gBPanHoPzexehEVGv0mwqWjEv53np5gdARKanj4XVm205gC2fuA6tjTZn2vzyEK5r GZs2UbABcmfStiM5vk/wYX+sKiFBWXyWroC5wPnhOSzGPCyePjjMtgyCithr1UMMJ7LI 44QXyjZxW5I284hMh8c9edn9MVisE1lG5iW2BVgWzrHRVSK7niggrYi482p/vOXYoeY4 8J6w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=Ptbb2tioMzNVHjabPeB1RPen2CnJsOp8RPHysN7rXAc=; b=qXqmaUKBdPisXE0RJytBTpIGe4CrbWEukE/bfGlf3q2C/DpoUelIgWRnfe+DUi5Ov6 y20Hk3eA5KOplJX+YkD6NwyritBWC0Q5+0nrqAtkzaLUNXrYpVaROHE0ZDAzpU9Zt+Kl 0+g0ibz3R3z90CsQFqFRw7JC1WXecHnrs8qEfllJF2icUiVyn5Yi+pw3D8gfj7JZ6Tdo Gr6w1q4p61F30rf6F/vVLCHpAJYmoIgMZmXsw8qDx7OWor2dGRnII3cM4hhN+2r7mEcQ hfmnOdMdbwuJXcIOy01p8nyHXYJYkPCvpPGeQvxhqxhmY730Tlu/BNBbvDMIu8keKNPO QpiA== X-Gm-Message-State: AHYfb5jSDvMZT9n1Db0+qlqn4lTWKM0+nPMFb+BUp8W23w4Iy6sMposU W1A7E6FYb0BiEw== X-Received: by 10.200.45.243 with SMTP id q48mr5097763qta.133.1504151602740; Wed, 30 Aug 2017 20:53:22 -0700 (PDT) Received: from yoga.offpageads.com ([181.93.89.178]) by smtp.gmail.com with ESMTPSA id x20sm5072398qtb.5.2017.08.30.20.53.20 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 30 Aug 2017 20:53:22 -0700 (PDT) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: Paolo Bonzini , Peter Maydell , Peter Chubb Cc: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , qemu-devel@nongnu.org, qemu-arm@nongnu.org Date: Thu, 31 Aug 2017 00:53:02 -0300 Message-Id: <20170831035306.29170-4-f4bug@amsat.org> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20170831035306.29170-1-f4bug@amsat.org> References: <20170831035306.29170-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400d:c0d::243 Subject: [Qemu-arm] [PATCH 3/7] hw/arm/fsl_imx*: use serial_chr_nonnull() X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 31 Aug 2017 03:53:31 -0000 Signed-off-by: Philippe Mathieu-Daudé --- include/hw/char/imx_serial.h | 1 + hw/arm/fsl-imx25.c | 9 +-------- hw/arm/fsl-imx31.c | 9 +-------- hw/arm/fsl-imx6.c | 10 +--------- 4 files changed, 4 insertions(+), 25 deletions(-) diff --git a/include/hw/char/imx_serial.h b/include/hw/char/imx_serial.h index baeec3183f..55139dc6ec 100644 --- a/include/hw/char/imx_serial.h +++ b/include/hw/char/imx_serial.h @@ -20,6 +20,7 @@ #include "hw/sysbus.h" #include "chardev/char-fe.h" +#include "hw/char/serial.h" #define TYPE_IMX_SERIAL "imx.serial" #define IMX_SERIAL(obj) OBJECT_CHECK(IMXSerialState, (obj), TYPE_IMX_SERIAL) diff --git a/hw/arm/fsl-imx25.c b/hw/arm/fsl-imx25.c index 3b97eceb3c..425a9edc36 100644 --- a/hw/arm/fsl-imx25.c +++ b/hw/arm/fsl-imx25.c @@ -120,14 +120,7 @@ static void fsl_imx25_realize(DeviceState *dev, Error **errp) if (i < MAX_SERIAL_PORTS) { Chardev *chr; - chr = serial_hds[i]; - - if (!chr) { - char label[20]; - snprintf(label, sizeof(label), "imx31.uart%d", i); - chr = qemu_chr_new(label, "null"); - } - + chr = serial_chr_nonnull(serial_hds[i]); qdev_prop_set_chr(DEVICE(&s->uart[i]), "chardev", chr); } diff --git a/hw/arm/fsl-imx31.c b/hw/arm/fsl-imx31.c index 0f2ebe8161..8d4535a536 100644 --- a/hw/arm/fsl-imx31.c +++ b/hw/arm/fsl-imx31.c @@ -109,14 +109,7 @@ static void fsl_imx31_realize(DeviceState *dev, Error **errp) if (i < MAX_SERIAL_PORTS) { Chardev *chr; - chr = serial_hds[i]; - - if (!chr) { - char label[20]; - snprintf(label, sizeof(label), "imx31.uart%d", i); - chr = qemu_chr_new(label, "null"); - } - + chr = serial_chr_nonnull(serial_hds[i]); qdev_prop_set_chr(DEVICE(&s->uart[i]), "chardev", chr); } diff --git a/hw/arm/fsl-imx6.c b/hw/arm/fsl-imx6.c index 26fd214004..7bc1aa1fbe 100644 --- a/hw/arm/fsl-imx6.c +++ b/hw/arm/fsl-imx6.c @@ -189,15 +189,7 @@ static void fsl_imx6_realize(DeviceState *dev, Error **errp) if (i < MAX_SERIAL_PORTS) { Chardev *chr; - chr = serial_hds[i]; - - if (!chr) { - char *label = g_strdup_printf("imx6.uart%d", i + 1); - chr = qemu_chr_new(label, "null"); - g_free(label); - serial_hds[i] = chr; - } - + chr = serial_chr_nonnull(serial_hds[i]); qdev_prop_set_chr(DEVICE(&s->uart[i]), "chardev", chr); } -- 2.14.1 From MAILER-DAEMON Wed Aug 30 23:53:38 2017 Received: from list by lists.gnu.org with archive (Exim 4.71) id 1dnGXy-0000pf-Fm for mharc-qemu-arm@gnu.org; Wed, 30 Aug 2017 23:53:38 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:55647) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dnGXv-0000oO-4j for qemu-arm@nongnu.org; Wed, 30 Aug 2017 23:53:37 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dnGXu-0006d5-As for qemu-arm@nongnu.org; Wed, 30 Aug 2017 23:53:35 -0400 Received: from mail-qk0-x244.google.com ([2607:f8b0:400d:c09::244]:34960) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1dnGXo-0006aq-QC; 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X-Received-From: 2607:f8b0:400d:c09::244 Subject: [Qemu-arm] [PATCH 5/7] hw/char/exynos4210_uart: use serial_chr_nonnull() X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 31 Aug 2017 03:53:37 -0000 Signed-off-by: Philippe Mathieu-Daudé --- This ARRAY_SIZE() first surprised me but was valid :) hw/char/exynos4210_uart.c | 14 ++------------ 1 file changed, 2 insertions(+), 12 deletions(-) diff --git a/hw/char/exynos4210_uart.c b/hw/char/exynos4210_uart.c index 3957e78abf..b6cdfc3006 100644 --- a/hw/char/exynos4210_uart.c +++ b/hw/char/exynos4210_uart.c @@ -27,6 +27,7 @@ #include "chardev/char-serial.h" #include "hw/arm/exynos4210.h" +#include "hw/char/serial.h" #undef DEBUG_UART #undef DEBUG_UART_EXTEND @@ -589,9 +590,6 @@ DeviceState *exynos4210_uart_create(hwaddr addr, DeviceState *dev; SysBusDevice *bus; - const char chr_name[] = "serial"; - char label[ARRAY_SIZE(chr_name) + 1]; - dev = qdev_create(NULL, TYPE_EXYNOS4210_UART); if (!chr) { @@ -600,15 +598,7 @@ DeviceState *exynos4210_uart_create(hwaddr addr, MAX_SERIAL_PORTS); exit(1); } - chr = serial_hds[channel]; - if (!chr) { - snprintf(label, ARRAY_SIZE(label), "%s%d", chr_name, channel); - chr = qemu_chr_new(label, "null"); - if (!(chr)) { - error_report("Can't assign serial port to UART%d", channel); - exit(1); - } - } + chr = serial_chr_nonnull(serial_hds[channel]); } qdev_prop_set_chr(dev, "chardev", chr); -- 2.14.1 From MAILER-DAEMON Wed Aug 30 23:53:40 2017 Received: from list by lists.gnu.org with archive (Exim 4.71) id 1dnGY0-0000ra-D1 for mharc-qemu-arm@gnu.org; Wed, 30 Aug 2017 23:53:40 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:55625) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dnGXt-0000nD-Rv for qemu-arm@nongnu.org; Wed, 30 Aug 2017 23:53:34 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dnGXt-0006cQ-3z for qemu-arm@nongnu.org; Wed, 30 Aug 2017 23:53:33 -0400 Received: from mail-qk0-x242.google.com ([2607:f8b0:400d:c09::242]:33896) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1dnGXr-0006bf-3k; Wed, 30 Aug 2017 23:53:31 -0400 Received: by mail-qk0-x242.google.com with SMTP id a77so6862452qkb.1; Wed, 30 Aug 2017 20:53:30 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=KIodJgPfyDNKVJDKXwpUl9qXpUSHSusQbEpLvuy+wCM=; b=AUz8fd82/Y7Bmt9Cs5c6V4dHbIBAtchd8VzAHpA46xMEeYOTMqstyjlwww1DPyHxS2 CC/oNb9z9PVJPb8HUBFj+b8QvBcW3/Toj9MjLd+/ofDyr9p5joLH/GNrZw1UCD5eJMak 9vtqS9kjd7YCJx2B2HNO4w7qXuN2jrSXHANJk99P930E7Ns0I1TLdMposb+ifK+X4s/3 fkQMGZjZzwH6MiK2sZylstHisdVhjBMc5okkpg0A2eWiqJLBGgJX0TVHAwJWsMudvS9W VUZ5fQAaGL1lw5DksmJQqRPTGfdN9SKiO0g+lDggMQB4N2zn/3Kk1T7oytIbCdwKImeV e2Dw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=KIodJgPfyDNKVJDKXwpUl9qXpUSHSusQbEpLvuy+wCM=; b=nHyX4g98meCY2XhrWUws/Pp+kIW+11YnstD9waf+6P5eA0u3FVD7JZYxxJq4H3FRGK 8DRkazZOSdIOD1upqSzknaKTTSbdmvzT57GBUiuY/bHhXE8ypZxRwvA6rVeVGSDH1KW9 Y6J/ZLOKOg0yYiLCzcR0vRZRmvtYhLIhgruVh0D4tDaR5IjBHaSeUEqJiBrW6mEm26QK r+grfq/F2g0KfHAo4/iHZzHCXhvd/sbhFgH49bh/RgvNBzmrCcat/aRUGRNbCFGNIBVx C68Pq2VPXVGXYs4+cM6eCLhzX2uI3UF73aP8Fc2Y4lqpeZupzOCTIQBsoT4RemKKh/72 k/XQ== X-Gm-Message-State: AHYfb5iE2nHsqyqkHKBRKLraeRtOPV2YWZPbAxOw7KIu2smahFy4ETwF mzrYC7yY9Syog/nxqftG0w== X-Received: by 10.55.74.194 with SMTP id x185mr1965505qka.237.1504151610556; Wed, 30 Aug 2017 20:53:30 -0700 (PDT) Received: from yoga.offpageads.com ([181.93.89.178]) by smtp.gmail.com with ESMTPSA id x20sm5072398qtb.5.2017.08.30.20.53.28 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 30 Aug 2017 20:53:30 -0700 (PDT) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: Paolo Bonzini , Peter Maydell Cc: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , qemu-devel@nongnu.org, qemu-arm@nongnu.org Date: Thu, 31 Aug 2017 00:53:05 -0300 Message-Id: <20170831035306.29170-7-f4bug@amsat.org> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20170831035306.29170-1-f4bug@amsat.org> References: <20170831035306.29170-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400d:c09::242 Subject: [Qemu-arm] [PATCH 6/7] hw/char/omap_uart: serial_mm_init() already check for null chr X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 31 Aug 2017 03:53:34 -0000 Signed-off-by: Philippe Mathieu-Daudé --- hw/char/omap_uart.c | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/hw/char/omap_uart.c b/hw/char/omap_uart.c index 6fd1b9cf6b..1f0ac0a053 100644 --- a/hw/char/omap_uart.c +++ b/hw/char/omap_uart.c @@ -63,8 +63,7 @@ struct omap_uart_s *omap_uart_init(hwaddr base, s->irq = irq; s->serial = serial_mm_init(get_system_memory(), base, 2, irq, omap_clk_getrate(fclk)/16, - chr ?: qemu_chr_new(label, "null"), - DEVICE_NATIVE_ENDIAN); + chr, DEVICE_NATIVE_ENDIAN); return s; } @@ -183,6 +182,5 @@ void omap_uart_attach(struct omap_uart_s *s, Chardev *chr) /* TODO: Should reuse or destroy current s->serial */ s->serial = serial_mm_init(get_system_memory(), s->base, 2, s->irq, omap_clk_getrate(s->fclk) / 16, - chr ?: qemu_chr_new("null", "null"), - DEVICE_NATIVE_ENDIAN); + chr, DEVICE_NATIVE_ENDIAN); } -- 2.14.1 From MAILER-DAEMON Thu Aug 31 01:07:47 2017 Received: from list by lists.gnu.org with archive (Exim 4.71) id 1dnHhj-0005rt-0h for mharc-qemu-arm@gnu.org; Thu, 31 Aug 2017 01:07:47 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:38254) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dnHhg-0005rm-P6 for qemu-arm@nongnu.org; Thu, 31 Aug 2017 01:07:45 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dnHhd-0006B0-Ks for qemu-arm@nongnu.org; Thu, 31 Aug 2017 01:07:44 -0400 Received: from mx1.redhat.com ([209.132.183.28]:33272) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1dnHhd-0006Ap-EK; Thu, 31 Aug 2017 01:07:41 -0400 Received: from smtp.corp.redhat.com (int-mx02.intmail.prod.int.phx2.redhat.com [10.5.11.12]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id 3B5C080E7A; Thu, 31 Aug 2017 05:07:40 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mx1.redhat.com 3B5C080E7A Authentication-Results: ext-mx01.extmail.prod.ext.phx2.redhat.com; dmarc=none (p=none dis=none) header.from=redhat.com Authentication-Results: ext-mx01.extmail.prod.ext.phx2.redhat.com; spf=fail smtp.mailfrom=thuth@redhat.com Received: from [10.36.116.27] (ovpn-116-27.ams2.redhat.com [10.36.116.27]) by smtp.corp.redhat.com (Postfix) with ESMTPS id B6F9B18B2A; Thu, 31 Aug 2017 05:07:38 +0000 (UTC) To: =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= , Peter Maydell Cc: qemu-devel@nongnu.org, qemu-trivial@nongnu.org, qemu-arm@nongnu.org References: <20170830215523.25278-1-f4bug@amsat.org> <20170830215523.25278-2-f4bug@amsat.org> From: Thomas Huth Message-ID: <3fae2ca1-90d0-b62a-d932-8c0d2cf2b62c@redhat.com> Date: Thu, 31 Aug 2017 07:07:36 +0200 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.3.0 MIME-Version: 1.0 In-Reply-To: <20170830215523.25278-2-f4bug@amsat.org> Content-Type: text/plain; charset=utf-8 Content-Language: en-US X-Scanned-By: MIMEDefang 2.79 on 10.5.11.12 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.25]); Thu, 31 Aug 2017 05:07:40 +0000 (UTC) Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.132.183.28 Subject: Re: [Qemu-arm] [PATCH v2 01/17] MAINTAINERS: add missing ARM entries X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 31 Aug 2017 05:07:45 -0000 On 30.08.2017 23:55, Philippe Mathieu-Daud=C3=A9 wrote: > Signed-off-by: Philippe Mathieu-Daud=C3=A9 > --- > MAINTAINERS | 7 +++++-- > 1 file changed, 5 insertions(+), 2 deletions(-) >=20 > diff --git a/MAINTAINERS b/MAINTAINERS > index ccee28b12d..b363e1b9c9 100644 > --- a/MAINTAINERS > +++ b/MAINTAINERS > @@ -380,6 +380,7 @@ M: Peter Maydell > L: qemu-arm@nongnu.org > S: Maintained > F: hw/char/pl011.c > +F: include/hw/char/pl011.h > F: hw/display/pl110* > F: hw/dma/pl080.c > F: hw/dma/pl330.c > @@ -403,13 +404,15 @@ F: hw/intc/gic_internal.h > F: hw/misc/a9scu.c > F: hw/misc/arm11scu.c > F: hw/timer/a9gtimer* > -F: hw/timer/arm_* > -F: include/hw/arm/arm.h > +F: hw/timer/arm* > +F: include/hw/arm/arm*.h > F: include/hw/intc/arm* > F: include/hw/misc/a9scu.h > F: include/hw/misc/arm11scu.h > F: include/hw/timer/a9gtimer.h > F: include/hw/timer/arm_mptimer.h > +F: include/hw/timer/armv7m_systick.h > +F: tests/test-arm-mptimer.c > =20 > Exynos > M: Igor Mitsyanko Reviewed-by: Thomas Huth From MAILER-DAEMON Thu Aug 31 01:23:07 2017 Received: from list by lists.gnu.org with archive (Exim 4.71) id 1dnHwZ-0002QC-MG for mharc-qemu-arm@gnu.org; Thu, 31 Aug 2017 01:23:07 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:40619) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dnHwX-0002Q0-73 for qemu-arm@nongnu.org; Thu, 31 Aug 2017 01:23:06 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dnHwS-0003gT-Vp for qemu-arm@nongnu.org; Thu, 31 Aug 2017 01:23:05 -0400 Received: from mx1.redhat.com ([209.132.183.28]:50840) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1dnHwS-0003fk-Pm; Thu, 31 Aug 2017 01:23:00 -0400 Received: from smtp.corp.redhat.com (int-mx06.intmail.prod.int.phx2.redhat.com [10.5.11.16]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id BCC0481DEE; Thu, 31 Aug 2017 05:22:59 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mx1.redhat.com BCC0481DEE Authentication-Results: ext-mx01.extmail.prod.ext.phx2.redhat.com; dmarc=none (p=none dis=none) header.from=redhat.com Authentication-Results: ext-mx01.extmail.prod.ext.phx2.redhat.com; spf=fail smtp.mailfrom=thuth@redhat.com Received: from [10.36.116.27] (ovpn-116-27.ams2.redhat.com [10.36.116.27]) by smtp.corp.redhat.com (Postfix) with ESMTPS id 95A825C881; Thu, 31 Aug 2017 05:22:57 +0000 (UTC) To: =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= , Peter Maydell Cc: qemu-devel@nongnu.org, qemu-trivial@nongnu.org, qemu-arm@nongnu.org References: <20170830215523.25278-1-f4bug@amsat.org> <20170830215523.25278-3-f4bug@amsat.org> From: Thomas Huth Message-ID: <3b185bc6-d5ea-85dc-8635-e9d21914d011@redhat.com> Date: Thu, 31 Aug 2017 07:22:56 +0200 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.3.0 MIME-Version: 1.0 In-Reply-To: <20170830215523.25278-3-f4bug@amsat.org> Content-Type: text/plain; charset=utf-8 Content-Language: en-US X-Scanned-By: MIMEDefang 2.79 on 10.5.11.16 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.25]); Thu, 31 Aug 2017 05:22:59 +0000 (UTC) Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.132.183.28 Subject: Re: [Qemu-arm] [PATCH v2 02/17] MAINTAINERS: add missing Versatile PB entry X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 31 Aug 2017 05:23:06 -0000 On 30.08.2017 23:55, Philippe Mathieu-Daud=C3=A9 wrote: > Signed-off-by: Philippe Mathieu-Daud=C3=A9 > --- > MAINTAINERS | 1 + > 1 file changed, 1 insertion(+) >=20 > diff --git a/MAINTAINERS b/MAINTAINERS > index b363e1b9c9..5b7891addc 100644 > --- a/MAINTAINERS > +++ b/MAINTAINERS > @@ -515,6 +515,7 @@ M: Peter Maydell > L: qemu-arm@nongnu.org > S: Maintained > F: hw/*/versatile* > +F: hw/misc/arm_sysctl.c I think you could also merge this into the previous patch. Anyway: Reviewed-by: Thomas Huth From MAILER-DAEMON Thu Aug 31 12:57:20 2017 Received: from list by lists.gnu.org with archive (Exim 4.71) id 1dnSmO-0001Bd-9S for mharc-qemu-arm@gnu.org; Thu, 31 Aug 2017 12:57:20 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:57944) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dnSmM-0001BS-E9 for qemu-arm@nongnu.org; Thu, 31 Aug 2017 12:57:19 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dnSmL-0007Zb-HQ for qemu-arm@nongnu.org; Thu, 31 Aug 2017 12:57:18 -0400 Received: from mail-io0-x241.google.com ([2607:f8b0:4001:c06::241]:32977) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1dnSmL-0007Yz-CE; Thu, 31 Aug 2017 12:57:17 -0400 Received: by mail-io0-x241.google.com with SMTP id f99so260299ioi.0; Thu, 31 Aug 2017 09:57:16 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=mime-version:in-reply-to:references:from:date:message-id:subject:to :cc; bh=bmm3AQfywmOOHoWfTukL1SCXKbIZfNJYwR7KWDUQr5M=; b=fPTnhIy/SlgVvlobBN8LKCLVvUxZCIloSfV0dxxAHyMp85YRSj24DXOO6dRDXEoHbu nOeWHNsCYolBSAlC5AOy4UIntSH0RV3akBmGIw0USWhtzSBXBEuxz7rsSdFhhhCBlXvT z5uPpZqapek9AoKv0jGtNnwkOyHLSwDu0z8pWu8HuxkEO6wvGWmWH6RkScf75F/JoQpV O2Z+5uADfjMNtd0RspM/d4uKanFET9eBo1nF98EPqTbGS7nwnjq0d6pDyWbcObCtliOQ zaZf2OTXRvplwshReC6MTl97dauz1iWYog/LR8QP5PHbB4P1LUL5MFVERKegDtCSRqrQ BULQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:in-reply-to:references:from:date :message-id:subject:to:cc; bh=bmm3AQfywmOOHoWfTukL1SCXKbIZfNJYwR7KWDUQr5M=; b=EFodRmYF65gWi9zxp6aJe0cTndzc015eVPRG4sAZljYwTZNIQ/6sh3nfZ9f1zqmJH2 aaIwWuEhXdNXGduFbt/BruLyuIckXpzlDx7994RboVVN7D83LebEA1pUGAx1M0FIkGOp WMrNvv8oNjWEFT/4/Um7xbf/FDa1RdmwktNjGyKQ5xzQ2PETmvIHvQlAmr8EWDTJ8RMB fjyDQpsC8NrJrMkCdJmxKfKQUswDCqKw0fxXvcFYoERNOB61d9agxrnXVXubByCzzcQQ 6GanslMHP1fWmx1mkxVdYostmqb2+Zu2D5T9xIjeuXUF7/ElyvWTI1HlsumSv+Knfzxd jYHA== X-Gm-Message-State: AHPjjUigsihl82iIEQEXPcxAL4BbJAzs/Z6Lw9sChoozLZ1TFYq49+5U uxjxU9oxDlTY+Chva2JhXcaZ8QRztQ== X-Google-Smtp-Source: ADKCNb6z8qqhQm4twEl0Y9z2swWKPhPuge3ZSwqxdo28wdkAgnOWhKF8BY+mQyLZlo8bulRsnLAVEwAnnCmS15DMvR0= X-Received: by 10.107.129.85 with SMTP id c82mr5218968iod.17.1504198635773; Thu, 31 Aug 2017 09:57:15 -0700 (PDT) MIME-Version: 1.0 Received: by 10.79.166.2 with HTTP; Thu, 31 Aug 2017 09:56:45 -0700 (PDT) In-Reply-To: <20170829173226.7625-1-bobby.prani@gmail.com> References: <20170829173226.7625-1-bobby.prani@gmail.com> From: Pranith Kumar Date: Thu, 31 Aug 2017 12:56:45 -0400 Message-ID: To: Peter Maydell , "open list:ARM cores" , "open list:All patches CC here" Cc: qemu-stable@nongnu.org Content-Type: text/plain; charset="UTF-8" X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4001:c06::241 Subject: Re: [Qemu-arm] [PATCH] arm_gicv3_kvm: Fix compile warning X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 31 Aug 2017 16:57:19 -0000 CC'ing stable for 2.10. On Tue, Aug 29, 2017 at 1:32 PM, Pranith Kumar wrote: > Fix the following warning: > > /home/pranith/qemu/hw/intc/arm_gicv3_kvm.c:296:17: warning: logical not is only applied to the left hand side of this bitwise operator [-Wlogical-not-parentheses] > if (!c->gicr_ctlr & GICR_CTLR_ENABLE_LPIS) { > ^ ~ > /home/pranith/qemu/hw/intc/arm_gicv3_kvm.c:296:17: note: add parentheses after the '!' to evaluate the bitwise operator first > if (!c->gicr_ctlr & GICR_CTLR_ENABLE_LPIS) { > ^ > /home/pranith/qemu/hw/intc/arm_gicv3_kvm.c:296:17: note: add parentheses around left hand side expression to silence this warning > if (!c->gicr_ctlr & GICR_CTLR_ENABLE_LPIS) { > ^ > > Signed-off-by: Pranith Kumar > --- > hw/intc/arm_gicv3_kvm.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/hw/intc/arm_gicv3_kvm.c b/hw/intc/arm_gicv3_kvm.c > index 6051c77705..481fe5405a 100644 > --- a/hw/intc/arm_gicv3_kvm.c > +++ b/hw/intc/arm_gicv3_kvm.c > @@ -293,7 +293,7 @@ static void kvm_arm_gicv3_put(GICv3State *s) > kvm_gicr_access(s, GICR_PROPBASER + 4, ncpu, ®h, true); > > reg64 = c->gicr_pendbaser; > - if (!c->gicr_ctlr & GICR_CTLR_ENABLE_LPIS) { > + if (!(c->gicr_ctlr & GICR_CTLR_ENABLE_LPIS)) { > /* Setting PTZ is advised if LPIs are disabled, to reduce > * GIC initialization time. > */ > -- > 2.11.0 > -- Pranith From MAILER-DAEMON Thu Aug 31 18:59:00 2017 Received: from list by lists.gnu.org with archive (Exim 4.71) id 1dnYQO-00087T-8K for mharc-qemu-arm@gnu.org; Thu, 31 Aug 2017 18:59:00 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:39488) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dnYQL-00085h-VM for qemu-arm@nongnu.org; Thu, 31 Aug 2017 18:58:59 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dnYQK-0004vV-FJ for qemu-arm@nongnu.org; Thu, 31 Aug 2017 18:58:58 -0400 Received: from mail-wr0-x244.google.com ([2a00:1450:400c:c0c::244]:35924) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1dnYQG-0004ty-Qb; Thu, 31 Aug 2017 18:58:53 -0400 Received: by mail-wr0-x244.google.com with SMTP id 40so482516wrv.3; Thu, 31 Aug 2017 15:58:52 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=mime-version:in-reply-to:references:from:date:message-id:subject:to :cc; bh=8WgloJuf6jRJSmw79sI39Xe1A8WyCVAz1lal+wEUHqk=; b=qIXsZV8rzlIil8iROfrgTM0QIPyzt/KWUii8VHz8ZvjUsF1yNFfPyXYsLoB6P0kYQt 5M5qMyNKtEXNROE6HXvYjZRiHluZkpyfK4IKQcvgh1tT2uEMm0MJ9Kev14bABDJfne1i UNHqKv+65Ug+lPvwcmtKxATEZ+oMdYF0aaOeBSPTgvBDR8OJ0qsxctV7z2kHYrc8ULKd WnBv/7QuxOTY4fw+L/6p6ukZuz3RNhtQ8O76saucYcxhHt1HN+MONR53I3GA+bY/+VU+ yZhOvnWcSzqDbkwmhC2IBxYGJiY1FFt4ZfZ7MnuJQ5ut4b38ATSofSlhhg4MsSr8QAvj psxw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:in-reply-to:references:from:date :message-id:subject:to:cc; bh=8WgloJuf6jRJSmw79sI39Xe1A8WyCVAz1lal+wEUHqk=; b=rCJ31T29VLAYaenLZYBseh+Ord4H21S6MYjMsvRhmR/QiPc1wCE9sWptz3JfxYka+u G6LqUVRyKF+xGcYrQPn0QHHq0u5HhBg70H9QcVxxwJGDDAiYZk5q0OY11+2XqJASvnGk K+leymVDNEDot3Qdt0U8/IAeKnWdUFko2OJfSC0/olbZjEbpKASVaf1Iqz6hZD0Cri+K HQ5XRk92ATiKw7Fa6FbMblKx3DNu/8HI+bOYcq0WyBmWfLQScbtPNkTh58FbfukPc4ci v0OgjB+IBdCHcWz3+0tO/KkrKAu5K+OVpzOuZQnBB1iVXU8SKEQStVcSQLjs8T+m6O7o nn7w== X-Gm-Message-State: AHPjjUiRZNd/1jH0/WWao4hP7RAn+1Ye7pAFUlQVbX9+kJ7frWQ85QM8 +FRXJS2XeghZrVImN0v+yEKFKFc2oQ== X-Google-Smtp-Source: ADKCNb4upm/37eL03uTofAialeP0KMdu871ufgBe/xEdQt3IsdFFlm7gLLB9Zj1LOTq3OKhgzZs5a1j2aeiRFALTHvI= X-Received: by 10.223.163.87 with SMTP id d23mr16601wrb.84.1504220331502; Thu, 31 Aug 2017 15:58:51 -0700 (PDT) MIME-Version: 1.0 Received: by 10.28.191.130 with HTTP; Thu, 31 Aug 2017 15:58:20 -0700 (PDT) In-Reply-To: <1503938283-12404-3-git-send-email-sundeep.lkml@gmail.com> References: <1503938283-12404-1-git-send-email-sundeep.lkml@gmail.com> <1503938283-12404-3-git-send-email-sundeep.lkml@gmail.com> From: Alistair Francis Date: Thu, 31 Aug 2017 15:58:20 -0700 Message-ID: To: Subbaraya Sundeep Cc: "qemu-devel@nongnu.org Developers" , qemu-arm , Peter Maydell , Peter Crosthwaite , =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= Content-Type: text/plain; charset="UTF-8" X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:400c:c0c::244 Subject: Re: [Qemu-arm] [Qemu devel v7 PATCH 2/5] msf2: Microsemi Smartfusion2 System Register block X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 31 Aug 2017 22:58:59 -0000 On Mon, Aug 28, 2017 at 9:38 AM, Subbaraya Sundeep wrote: > Added Sytem register block of Smartfusion2. > This block has PLL registers which are accessed by guest. > > Signed-off-by: Subbaraya Sundeep > --- > hw/misc/Makefile.objs | 1 + > hw/misc/msf2-sysreg.c | 199 ++++++++++++++++++++++++++++++++++++++++++ > include/hw/misc/msf2-sysreg.h | 78 +++++++++++++++++ > 3 files changed, 278 insertions(+) > create mode 100644 hw/misc/msf2-sysreg.c > create mode 100644 include/hw/misc/msf2-sysreg.h > > diff --git a/hw/misc/Makefile.objs b/hw/misc/Makefile.objs > index 29fb922..e8f0a02 100644 > --- a/hw/misc/Makefile.objs > +++ b/hw/misc/Makefile.objs > @@ -59,3 +59,4 @@ obj-$(CONFIG_HYPERV_TESTDEV) += hyperv_testdev.o > obj-$(CONFIG_AUX) += auxbus.o > obj-$(CONFIG_ASPEED_SOC) += aspeed_scu.o aspeed_sdmc.o > obj-y += mmio_interface.o > +obj-$(CONFIG_MSF2) += msf2-sysreg.o > diff --git a/hw/misc/msf2-sysreg.c b/hw/misc/msf2-sysreg.c > new file mode 100644 > index 0000000..2aeb555 > --- /dev/null > +++ b/hw/misc/msf2-sysreg.c > @@ -0,0 +1,199 @@ > +/* > + * System Register block model of Microsemi SmartFusion2. > + * > + * Copyright (c) 2017 Subbaraya Sundeep > + * > + * This program is free software; you can redistribute it and/or > + * modify it under the terms of the GNU General Public License > + * as published by the Free Software Foundation; either version > + * 2 of the License, or (at your option) any later version. > + * > + * You should have received a copy of the GNU General Public License along > + * with this program; if not, see . > + */ > + > +#include "qemu/osdep.h" > +#include "qemu/log.h" > +#include "hw/misc/msf2-sysreg.h" > + > +#ifndef MSF2_SYSREG_ERR_DEBUG > +#define MSF2_SYSREG_ERR_DEBUG 0 > +#endif > + > +#define DB_PRINT_L(lvl, fmt, args...) do { \ > + if (MSF2_SYSREG_ERR_DEBUG >= lvl) { \ > + qemu_log("%s: " fmt "\n", __func__, ## args); \ > + } \ > +} while (0); > + > +#define DB_PRINT(fmt, args...) DB_PRINT_L(1, fmt, ## args) > + > +static inline int msf2_divbits(uint32_t div) > +{ > + int ret = 0; > + > + switch (div) { > + case 1: > + ret = 0; > + break; > + case 2: > + ret = 1; > + break; > + case 4: > + ret = 2; > + break; > + case 8: > + ret = 4; > + break; > + case 16: > + ret = 5; > + break; > + case 32: > + ret = 6; > + break; > + default: > + break; > + } > + > + return ret; > +} > + > +static void msf2_sysreg_reset(DeviceState *d) > +{ > + MSF2SysregState *s = MSF2_SYSREG(d); > + > + DB_PRINT("RESET"); > + > + s->regs[MSSDDR_PLL_STATUS_LOW_CR] = 0x021A2358; > + s->regs[MSSDDR_PLL_STATUS] = 0x3; > + s->regs[MSSDDR_FACC1_CR] = msf2_divbits(s->apb0div) << 5 | > + msf2_divbits(s->apb1div) << 2; > +} > + > +static uint64_t msf2_sysreg_read(void *opaque, hwaddr offset, > + unsigned size) > +{ > + MSF2SysregState *s = opaque; > + uint32_t ret = 0; > + > + offset >>= 2; > + if (offset < ARRAY_SIZE(s->regs)) { > + ret = s->regs[offset]; > + DB_PRINT("addr: 0x%08" HWADDR_PRIx " data: 0x%08" PRIx32, > + offset << 2, ret); > + } else { > + qemu_log_mask(LOG_GUEST_ERROR, > + "%s: Bad offset 0x%08" HWADDR_PRIx "\n", __func__, > + offset << 2); > + } > + > + return ret; > +} > + > +static void msf2_sysreg_write(void *opaque, hwaddr offset, > + uint64_t val, unsigned size) > +{ > + MSF2SysregState *s = (MSF2SysregState *)opaque; Drop this cast > + uint32_t newval = val; > + uint32_t oldval; > + > + DB_PRINT("addr: 0x%08" HWADDR_PRIx " data: 0x%08" PRIx64, > + offset, val); > + > + offset >>= 2; > + > + switch (offset) { > + case MSSDDR_PLL_STATUS: > + break; > + > + case ESRAM_CR: > + oldval = s->regs[ESRAM_CR]; > + if (oldval ^ newval) { Isn't this just: if (newval != s->regs[ESRAM_CR]) I think putting it all in the if makes it clearer. > + qemu_log_mask(LOG_GUEST_ERROR, > + TYPE_MSF2_SYSREG": eSRAM remapping not supported\n"); > + } > + break; > + > + case DDR_CR: > + oldval = s->regs[DDR_CR]; > + if (oldval ^ newval) { > + qemu_log_mask(LOG_GUEST_ERROR, > + TYPE_MSF2_SYSREG": DDR remapping not supported\n"); > + } > + break; > + > + case ENVM_REMAP_BASE_CR: > + oldval = s->regs[ENVM_REMAP_BASE_CR]; > + if (oldval ^ newval) { > + qemu_log_mask(LOG_GUEST_ERROR, > + TYPE_MSF2_SYSREG": eNVM remapping not supported\n"); > + } > + break; > + > + default: > + if (offset < ARRAY_SIZE(s->regs)) { > + s->regs[offset] = val; Use newval instead. With those all fixed up you can include this in the next version: Reviewed-by: Alistair Francis Thanks, Alistair > + } else { > + qemu_log_mask(LOG_GUEST_ERROR, > + "%s: Bad offset 0x%08" HWADDR_PRIx "\n", __func__, > + offset << 2); > + } > + break; > + } > +} > + > +static const MemoryRegionOps sysreg_ops = { > + .read = msf2_sysreg_read, > + .write = msf2_sysreg_write, > + .endianness = DEVICE_NATIVE_ENDIAN, > +}; > + > +static void msf2_sysreg_init(Object *obj) > +{ > + MSF2SysregState *s = MSF2_SYSREG(obj); > + > + memory_region_init_io(&s->iomem, obj, &sysreg_ops, s, TYPE_MSF2_SYSREG, > + MSF2_SYSREG_MMIO_SIZE); > + sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->iomem); > +} > + > +static const VMStateDescription vmstate_msf2_sysreg = { > + .name = TYPE_MSF2_SYSREG, > + .version_id = 1, > + .minimum_version_id = 1, > + .fields = (VMStateField[]) { > + VMSTATE_UINT32_ARRAY(regs, MSF2SysregState, MSF2_SYSREG_MMIO_SIZE / 4), > + VMSTATE_END_OF_LIST() > + } > +}; > + > +static Property msf2_sysreg_properties[] = { > + /* default divisors in Libero GUI */ > + DEFINE_PROP_UINT32("apb0divisor", MSF2SysregState, apb0div, 2), > + DEFINE_PROP_UINT32("apb1divisor", MSF2SysregState, apb1div, 2), > + DEFINE_PROP_END_OF_LIST(), > +}; > + > +static void msf2_sysreg_class_init(ObjectClass *klass, void *data) > +{ > + DeviceClass *dc = DEVICE_CLASS(klass); > + > + dc->vmsd = &vmstate_msf2_sysreg; > + dc->reset = msf2_sysreg_reset; > + dc->props = msf2_sysreg_properties; > +} > + > +static const TypeInfo msf2_sysreg_info = { > + .name = TYPE_MSF2_SYSREG, > + .parent = TYPE_SYS_BUS_DEVICE, > + .class_init = msf2_sysreg_class_init, > + .instance_size = sizeof(MSF2SysregState), > + .instance_init = msf2_sysreg_init, > +}; > + > +static void msf2_sysreg_register_types(void) > +{ > + type_register_static(&msf2_sysreg_info); > +} > + > +type_init(msf2_sysreg_register_types) > diff --git a/include/hw/misc/msf2-sysreg.h b/include/hw/misc/msf2-sysreg.h > new file mode 100644 > index 0000000..f39cc41 > --- /dev/null > +++ b/include/hw/misc/msf2-sysreg.h > @@ -0,0 +1,78 @@ > +/* > + * Microsemi SmartFusion2 SYSREG > + * > + * Copyright (c) 2017 Subbaraya Sundeep > + * > + * Permission is hereby granted, free of charge, to any person obtaining a copy > + * of this software and associated documentation files (the "Software"), to deal > + * in the Software without restriction, including without limitation the rights > + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell > + * copies of the Software, and to permit persons to whom the Software is > + * furnished to do so, subject to the following conditions: > + * > + * The above copyright notice and this permission notice shall be included in > + * all copies or substantial portions of the Software. > + * > + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR > + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, > + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL > + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER > + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, > + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN > + * THE SOFTWARE. > + */ > + > +#ifndef HW_MSF2_SYSREG_H > +#define HW_MSF2_SYSREG_H > + > +#include "hw/sysbus.h" > + > +enum { > + ESRAM_CR = 0x00 / 4, > + ESRAM_MAX_LAT, > + DDR_CR, > + ENVM_CR, > + ENVM_REMAP_BASE_CR, > + ENVM_REMAP_FAB_CR, > + CC_CR, > + CC_REGION_CR, > + CC_LOCK_BASE_ADDR_CR, > + CC_FLUSH_INDX_CR, > + DDRB_BUF_TIMER_CR, > + DDRB_NB_ADDR_CR, > + DDRB_NB_SIZE_CR, > + DDRB_CR, > + > + SOFT_RESET_CR = 0x48 / 4, > + M3_CR, > + > + GPIO_SYSRESET_SEL_CR = 0x58 / 4, > + > + MDDR_CR = 0x60 / 4, > + > + MSSDDR_PLL_STATUS_LOW_CR = 0x90 / 4, > + MSSDDR_PLL_STATUS_HIGH_CR, > + MSSDDR_FACC1_CR, > + MSSDDR_FACC2_CR, > + > + MSSDDR_PLL_STATUS = 0x150 / 4, > + > +}; > + > +#define MSF2_SYSREG_MMIO_SIZE 0x300 > + > +#define TYPE_MSF2_SYSREG "msf2-sysreg" > +#define MSF2_SYSREG(obj) OBJECT_CHECK(MSF2SysregState, (obj), TYPE_MSF2_SYSREG) > + > +typedef struct MSF2SysregState { > + SysBusDevice parent_obj; > + > + MemoryRegion iomem; > + > + uint32_t apb0div; > + uint32_t apb1div; > + > + uint32_t regs[MSF2_SYSREG_MMIO_SIZE / 4]; > +} MSF2SysregState; > + > +#endif /* HW_MSF2_SYSREG_H */ > -- > 2.5.0 > From MAILER-DAEMON Thu Aug 31 19:02:39 2017 Received: from list by lists.gnu.org with archive (Exim 4.71) id 1dnYTv-0001Ik-MO for mharc-qemu-arm@gnu.org; Thu, 31 Aug 2017 19:02:39 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:40505) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dnYTt-0001HO-IA for qemu-arm@nongnu.org; Thu, 31 Aug 2017 19:02:38 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dnYTs-0006i5-TV for qemu-arm@nongnu.org; Thu, 31 Aug 2017 19:02:37 -0400 Received: from mail-wr0-x243.google.com ([2a00:1450:400c:c0c::243]:33324) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1dnYTr-0006fC-1K; Thu, 31 Aug 2017 19:02:35 -0400 Received: by mail-wr0-x243.google.com with SMTP id k94so496782wrc.0; Thu, 31 Aug 2017 16:02:34 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=mime-version:in-reply-to:references:from:date:message-id:subject:to :cc:content-transfer-encoding; bh=zI0Lb9aMIMGCk0z5/DK5DbjlRhh2v/fea/e9g6xI8uA=; b=M+CG/ggMryiBKm2QO5NrxCwQtNAwRuPyv8PRTLF+LMMZrklfH3xCiKGhJ+pX7xZPbc pFDRUmBr7DbzGZrEQ0H6iXKGqwEpRMpg9SwiGAyQLpBhyfb/3IQ3QtA2OiYIckghl2yZ RT45TK3oRVjcwJtAMa0wTKZoN43nbwVGNs7MFnaElIae0KSPfDidPnu2IJ13I7N3T0qG VpVPMhB/DIjXIlb3R24KI2uMv+epvOc/lyJYNMKTwA6/EnwuypeSuPkJEr7lUt+DvJSY DcviL3lNEpswCNBkxtCgOtRpExgjBzBLvt4ejHN5MHe/LpMc/GNryO/YsHOmrhNRqkET H7ow== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:in-reply-to:references:from:date :message-id:subject:to:cc:content-transfer-encoding; bh=zI0Lb9aMIMGCk0z5/DK5DbjlRhh2v/fea/e9g6xI8uA=; b=a1OegRNusCZvaDBk8EVaoYwEpt6uTIzEfxgGAIdRPjHx6us4sj5ZmFaJUaAIn4hklV d47YoX93exy3OarrhTdRdlskmenieeIz8mrHKxD240LuAad+XtO/130ExlG9gDcR1LNL OFXF14sua14kJterhpEwP0JOBwcgdxbK9Nqu4WjWcV23AwhBakie1iwnK0d9C7ZCjuAp NRHjdoWD+aTZupNpbHJv0BRpstRX4BXxPKm+LUPB68sIOHLDG141/i17MmpSoNVO2+9l 9wJ2JhR2cC/PQ3nN6wZhHPPKl8jQZZfupsfPzB0tkP/z823sI8L0RoyL6CZaCVKi3T91 GDWw== X-Gm-Message-State: AHPjjUhySWI2Xhe5Vfw1UNYXw+sZdU534iDd4TPyIIBFm7p6p1e6bmLB a4xMd5Lq6LynIj67g0ay4l/ydq9fwg== X-Google-Smtp-Source: ADKCNb5R1KFOWSXS+RKTAwFWo3FyjMvUAeVyW46DG5JuKIAedf5UGIVN+qh9f4Ls+gDVwD8+p5OkuRxelM+zVLH9jJA= X-Received: by 10.223.146.195 with SMTP id 61mr15316wrn.318.1504220553968; Thu, 31 Aug 2017 16:02:33 -0700 (PDT) MIME-Version: 1.0 Received: by 10.28.191.130 with HTTP; Thu, 31 Aug 2017 16:02:03 -0700 (PDT) In-Reply-To: <40ca8d07-75e5-e0b3-021e-5abaffd16b78@amsat.org> References: <1503938283-12404-1-git-send-email-sundeep.lkml@gmail.com> <1503938283-12404-5-git-send-email-sundeep.lkml@gmail.com> <10da5552-c90a-21e6-43ac-829932f64930@amsat.org> <40ca8d07-75e5-e0b3-021e-5abaffd16b78@amsat.org> From: Alistair Francis Date: Thu, 31 Aug 2017 16:02:03 -0700 Message-ID: To: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= Cc: Peter Maydell , Subbaraya Sundeep , QEMU Developers , qemu-arm , Peter Crosthwaite Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:400c:c0c::243 Subject: Re: [Qemu-arm] [Qemu devel v7 PATCH 4/5] msf2: Add Smartfusion2 SoC X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 31 Aug 2017 23:02:38 -0000 On Wed, Aug 30, 2017 at 7:47 AM, Philippe Mathieu-Daud=C3=A9 wrote: > On 08/30/2017 09:26 AM, Peter Maydell wrote: >> >> On 30 August 2017 at 03:45, Philippe Mathieu-Daud=C3=A9 >> wrote: >>> >>> I think they might be issues if you start QEMU without -serial and then >>> use >>> a firmware polling for an uart, the device won't be mapped and the memo= ry >>> accesses are mostly ignored. >>> >>> I'd rather use: >>> >>> for (i =3D 0; i < MSF2_NUM_UARTS && i < MAX_SERIAL_PORTS; i++) { >>> static const char *serial[] =3D {"serial0", "serial1"}; >>> >>> if (!serial_hds[i]) { >>> serial_hds[i] =3D qemu_chr_new(serial[i], "null"); >>> >>> } >>> >>>> + serial_mm_init(get_system_memory(), uart_addr[i], 2, >>>> + qdev_get_gpio_in(armv7m, uart_irq[i]), >>>> + 115200, serial_hds[i], >>>> DEVICE_NATIVE_ENDIAN); >>>> + } >>>> + } >> >> >> It would be better to fix serial_mm_init() to handle having >> a NULL chardev pointer, because we already have a lot of >> SoC code that just passes it serial_hds[] regardless. > > > clever :) > >> I'd leave this code as it is and we can fix serial_mm_init >> separately (somebody pointed out this issue for a xilinx >> board recently). Ah, I'll look into this then. Thanks, Alistair > > > Sure. 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Ip=[149.199.60.83]; Helo=[xsj-pvapsmtpgw01] X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BLUPR0201MB1924 X-detected-operating-system: by eggs.gnu.org: Windows 7 or 8 [fuzzy] X-Received-From: 104.47.41.63 Subject: [Qemu-arm] [PATCH v2 0/5] Expose the secure and virt properties to the X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 31 Aug 2017 23:38:03 -0000 The EL2 and EL3 work is working well now and interanlly we now have tests that expect to start in EL3 and transition through EL2 to EL1. To make this easy to run let's expose the secure property to the machine and also add a virt property that can enable EL2. This series also does some machine/name tidying up and makes the first move to deprecating the EP108 machine, which was just an early access development board. V2: - Add a virt option for setting EL2 Alistair Francis (5): xlnx-ep108: Rename to ZCU102 xlnx-zcu102: Manually create the machines xlnx-zcu102: Add a machine level secure property xlnx-zcu102: Add a machine level virtualization property xlnx-zcu102: Mark the EP108 machine as deprecated hw/arm/Makefile.objs | 2 +- hw/arm/xlnx-ep108.c | 137 ----------------------- hw/arm/xlnx-zcu102.c | 257 +++++++++++++++++++++++++++++++++++++++++++ hw/arm/xlnx-zynqmp.c | 3 +- include/hw/arm/xlnx-zynqmp.h | 2 + 5 files changed, 262 insertions(+), 139 deletions(-) delete mode 100644 hw/arm/xlnx-ep108.c create mode 100644 hw/arm/xlnx-zcu102.c -- 2.11.0 From MAILER-DAEMON Thu Aug 31 19:38:16 2017 Received: from list by lists.gnu.org with archive (Exim 4.71) id 1dnZ2O-0003MZ-Mc for mharc-qemu-arm@gnu.org; Thu, 31 Aug 2017 19:38:16 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:46023) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dnZ2K-0003L3-Mn for qemu-arm@nongnu.org; Thu, 31 Aug 2017 19:38:15 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dnZ2F-0003gR-N3 for qemu-arm@nongnu.org; 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Ip=[149.199.60.100]; Helo=[xsj-pvapsmtpgw02] X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BLUPR0201MB1921 X-detected-operating-system: by eggs.gnu.org: Windows 7 or 8 [fuzzy] X-Received-From: 104.47.41.42 Subject: [Qemu-arm] [PATCH v2 4/5] xlnx-zcu102: Add a machine level virtualization property X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 31 Aug 2017 23:38:15 -0000 Add a machine level virtualization property. This defaults to false and can be set to true using this machine command line argument: -machine xlnx-zcu102,virtualization=on This follows what the ARM virt machine does. This property only applies to the ZCU102 machine. The EP108 machine does not have this property. Signed-off-by: Alistair Francis --- hw/arm/xlnx-zcu102.c | 30 +++++++++++++++++++++++++++++- hw/arm/xlnx-zynqmp.c | 3 ++- include/hw/arm/xlnx-zynqmp.h | 2 ++ 3 files changed, 33 insertions(+), 2 deletions(-) diff --git a/hw/arm/xlnx-zcu102.c b/hw/arm/xlnx-zcu102.c index 080507831a..40c1f5bbf6 100644 --- a/hw/arm/xlnx-zcu102.c +++ b/hw/arm/xlnx-zcu102.c @@ -32,6 +32,7 @@ typedef struct XlnxZCU102 { MemoryRegion ddr_ram; bool secure; + bool virt; } XlnxZCU102; #define TYPE_ZCU102_MACHINE MACHINE_TYPE_NAME("xlnx-zcu102") @@ -58,6 +59,20 @@ static void zcu102_set_secure(Object *obj, bool value, Error **errp) s->secure = value; } +static bool zcu102_get_virt(Object *obj, Error **errp) +{ + XlnxZCU102 *s = ZCU102_MACHINE(obj); + + return s->virt; +} + +static void zcu102_set_virt(Object *obj, bool value, Error **errp) +{ + XlnxZCU102 *s = ZCU102_MACHINE(obj); + + s->virt = value; +} + static void xlnx_zynqmp_init(XlnxZCU102 *s, MachineState *machine) { int i; @@ -87,6 +102,8 @@ static void xlnx_zynqmp_init(XlnxZCU102 *s, MachineState *machine) "ddr-ram", &error_abort); object_property_set_bool(OBJECT(&s->soc), s->secure, "secure", &error_fatal); + object_property_set_bool(OBJECT(&s->soc), s->virt, "virtualization", + &error_fatal); object_property_set_bool(OBJECT(&s->soc), true, "realized", &error_fatal); @@ -154,8 +171,9 @@ static void xlnx_ep108_machine_instance_init(Object *obj) { XlnxZCU102 *s = EP108_MACHINE(obj); - /* EP108, we don't support setting secure */ + /* EP108, we don't support setting secure or virt */ s->secure = false; + s->virt = false; } static void xlnx_ep108_machine_class_init(ObjectClass *oc, void *data) @@ -200,6 +218,16 @@ static void xlnx_zcu102_machine_instance_init(Object *obj) "Set on/off to enable/disable the ARM " "Security Extensions (TrustZone)", NULL); + + /* Default to virt (EL2) being disabled */ + s->virt = false; + object_property_add_bool(obj, "virtualization", zcu102_get_virt, + zcu102_set_virt, NULL); + object_property_set_description(obj, "virtualization", + "Set on/off to enable/disable emulating a " + "guest CPU which implements the ARM " + "Virtualization Extensions", + NULL); } static void xlnx_zcu102_machine_class_init(ObjectClass *oc, void *data) diff --git a/hw/arm/xlnx-zynqmp.c b/hw/arm/xlnx-zynqmp.c index 9eceadbdc8..37a8bf2ccd 100644 --- a/hw/arm/xlnx-zynqmp.c +++ b/hw/arm/xlnx-zynqmp.c @@ -260,7 +260,7 @@ static void xlnx_zynqmp_realize(DeviceState *dev, Error **errp) object_property_set_bool(OBJECT(&s->apu_cpu[i]), s->secure, "has_el3", NULL); object_property_set_bool(OBJECT(&s->apu_cpu[i]), - false, "has_el2", NULL); + s->virt, "has_el2", NULL); object_property_set_int(OBJECT(&s->apu_cpu[i]), GIC_BASE_ADDR, "reset-cbar", &error_abort); object_property_set_bool(OBJECT(&s->apu_cpu[i]), true, "realized", @@ -432,6 +432,7 @@ static void xlnx_zynqmp_realize(DeviceState *dev, Error **errp) static Property xlnx_zynqmp_props[] = { DEFINE_PROP_STRING("boot-cpu", XlnxZynqMPState, boot_cpu), DEFINE_PROP_BOOL("secure", XlnxZynqMPState, secure, false), + DEFINE_PROP_BOOL("virtualization", XlnxZynqMPState, virt, false), DEFINE_PROP_BOOL("has_rpu", XlnxZynqMPState, has_rpu, false), DEFINE_PROP_END_OF_LIST() }; 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Ip=[149.199.60.83]; Helo=[xsj-pvapsmtpgw01] X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BY1PR02MB1130 X-detected-operating-system: by eggs.gnu.org: Windows 7 or 8 [fuzzy] X-Received-From: 104.47.40.44 Subject: [Qemu-arm] [PATCH v2 2/5] xlnx-zcu102: Manually create the machines X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 31 Aug 2017 23:38:16 -0000 In preperation for future work let's manually create the Xilnx machines. This will allow us to set properties for the machines in the future. Signed-off-by: Alistair Francis --- V2: - Remove stray newline hw/arm/xlnx-zcu102.c | 74 +++++++++++++++++++++++++++++++++++++++++++++++----- 1 file changed, 67 insertions(+), 7 deletions(-) diff --git a/hw/arm/xlnx-zcu102.c b/hw/arm/xlnx-zcu102.c index 133a6a31a8..03dcd67bd8 100644 --- a/hw/arm/xlnx-zcu102.c +++ b/hw/arm/xlnx-zcu102.c @@ -26,15 +26,24 @@ #include "qemu/log.h" typedef struct XlnxZCU102 { + MachineState parent_obj; + XlnxZynqMPState soc; MemoryRegion ddr_ram; } XlnxZCU102; +#define TYPE_ZCU102_MACHINE MACHINE_TYPE_NAME("xlnx-zcu102") +#define ZCU102_MACHINE(obj) \ + OBJECT_CHECK(XlnxZCU102, (obj), TYPE_ZCU102_MACHINE) + +#define TYPE_EP108_MACHINE MACHINE_TYPE_NAME("xlnx-ep108") +#define EP108_MACHINE(obj) \ + OBJECT_CHECK(XlnxZCU102, (obj), TYPE_EP108_MACHINE) + static struct arm_boot_info xlnx_zcu102_binfo; -static void xlnx_zcu102_init(MachineState *machine) +static void xlnx_zynqmp_init(XlnxZCU102 *s, MachineState *machine) { - XlnxZCU102 *s = g_new0(XlnxZCU102, 1); int i; uint64_t ram_size = machine->ram_size; @@ -116,22 +125,73 @@ static void xlnx_zcu102_init(MachineState *machine) arm_load_kernel(s->soc.boot_cpu_ptr, &xlnx_zcu102_binfo); } -static void xlnx_ep108_machine_init(MachineClass *mc) +static void xlnx_ep108_init(MachineState *machine) +{ + XlnxZCU102 *s = EP108_MACHINE(machine); + + xlnx_zynqmp_init(s, machine); +} + +static void xlnx_ep108_machine_instance_init(Object *obj) { +} + +static void xlnx_ep108_machine_class_init(ObjectClass *oc, void *data) +{ + MachineClass *mc = MACHINE_CLASS(oc); + mc->desc = "Xilinx ZynqMP EP108 board"; - mc->init = xlnx_zcu102_init; + mc->init = xlnx_ep108_init; mc->block_default_type = IF_IDE; mc->units_per_default_bus = 1; } -DEFINE_MACHINE("xlnx-ep108", xlnx_ep108_machine_init) +static const TypeInfo xlnx_ep108_machine_init_typeinfo = { + .name = MACHINE_TYPE_NAME("xlnx-ep108"), + .parent = TYPE_MACHINE, + .class_init = xlnx_ep108_machine_class_init, + .instance_init = xlnx_ep108_machine_instance_init, + .instance_size = sizeof(XlnxZCU102), +}; -static void xlnx_zcu102_machine_init(MachineClass *mc) +static void xlnx_ep108_machine_init_register_types(void) { + type_register_static(&xlnx_ep108_machine_init_typeinfo); +} + +static void xlnx_zcu102_init(MachineState *machine) +{ + XlnxZCU102 *s = ZCU102_MACHINE(machine); + + xlnx_zynqmp_init(s, machine); +} + +static void xlnx_zcu102_machine_instance_init(Object *obj) +{ +} + +static void xlnx_zcu102_machine_class_init(ObjectClass *oc, void *data) +{ + MachineClass *mc = MACHINE_CLASS(oc); + mc->desc = "Xilinx ZynqMP ZCU102 board"; mc->init = xlnx_zcu102_init; mc->block_default_type = IF_IDE; mc->units_per_default_bus = 1; } -DEFINE_MACHINE("xlnx-zcu102", xlnx_zcu102_machine_init) +static const TypeInfo xlnx_zcu102_machine_init_typeinfo = { + .name = MACHINE_TYPE_NAME("xlnx-zcu102"), + .parent = TYPE_MACHINE, + .class_init = xlnx_zcu102_machine_class_init, + .instance_init = xlnx_zcu102_machine_instance_init, + .instance_size = sizeof(XlnxZCU102), +}; + +static void xlnx_zcu102_machine_init_register_types(void) +{ + type_register_static(&xlnx_zcu102_machine_init_typeinfo); +} + +type_init(xlnx_zcu102_machine_init_register_types) +type_init(xlnx_ep108_machine_init_register_types) -- 2.11.0 From MAILER-DAEMON Thu Aug 31 19:38:28 2017 Received: from list by lists.gnu.org with archive (Exim 4.71) id 1dnZ2Z-0003W9-TM for mharc-qemu-arm@gnu.org; Thu, 31 Aug 2017 19:38:27 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:46119) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dnZ2T-0003Qt-R7 for qemu-arm@nongnu.org; Thu, 31 Aug 2017 19:38:26 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dnZ2P-0003kG-Ku for qemu-arm@nongnu.org; Thu, 31 Aug 2017 19:38:21 -0400 Received: from mail-bl2nam02on0043.outbound.protection.outlook.com ([104.47.38.43]:58304 helo=NAM02-BL2-obe.outbound.protection.outlook.com) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1dnZ2P-0003jg-Eu; Thu, 31 Aug 2017 19:38:17 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; 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Ip=[149.199.60.100]; Helo=[xsj-pvapsmtpgw02] X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY1PR02MB1136 X-detected-operating-system: by eggs.gnu.org: Windows 7 or 8 [fuzzy] X-Received-From: 104.47.38.43 Subject: [Qemu-arm] [PATCH v2 5/5] xlnx-zcu102: Mark the EP108 machine as deprecated X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 31 Aug 2017 23:38:26 -0000 The EP108 is the same as the ZCU102, mark it as deprecated as we don't need two machines. Signed-off-by: Alistair Francis --- hw/arm/xlnx-zcu102.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/arm/xlnx-zcu102.c b/hw/arm/xlnx-zcu102.c index 40c1f5bbf6..d3694f67db 100644 --- a/hw/arm/xlnx-zcu102.c +++ b/hw/arm/xlnx-zcu102.c @@ -180,7 +180,7 @@ static void xlnx_ep108_machine_class_init(ObjectClass *oc, void *data) { MachineClass *mc = MACHINE_CLASS(oc); - mc->desc = "Xilinx ZynqMP EP108 board"; + mc->desc = "Xilinx ZynqMP EP108 board (Deprecated, please use xlnx-zcu102)"; mc->init = xlnx_ep108_init; mc->block_default_type = IF_IDE; mc->units_per_default_bus = 1; -- 2.11.0 From MAILER-DAEMON Thu Aug 31 19:40:45 2017 Received: from list by lists.gnu.org with archive (Exim 4.71) id 1dnZ4n-0005Iw-Dy for mharc-qemu-arm@gnu.org; Thu, 31 Aug 2017 19:40:45 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:46634) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dnZ4l-0005Da-1x for qemu-arm@nongnu.org; Thu, 31 Aug 2017 19:40:43 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dnZ4f-0004gk-SS for qemu-arm@nongnu.org; Thu, 31 Aug 2017 19:40:42 -0400 Received: from mail-qk0-x243.google.com ([2607:f8b0:400d:c09::243]:34556) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1dnZ4f-0004g4-FP; Thu, 31 Aug 2017 19:40:37 -0400 Received: by mail-qk0-x243.google.com with SMTP id a77so856702qkb.1; Thu, 31 Aug 2017 16:40:37 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:subject:to:cc:references:from:message-id:date:user-agent :mime-version:in-reply-to:content-language:content-transfer-encoding; bh=grex/scWDItlhlGFXvO1kPgEMarCyOey7CuOC+Bd9Lw=; b=A9Nz23oejYKaUAsHYkRdekH/t6e/HwNDO/GJKGI6sj24lndXRgDpxdRMibw2Du4Q0F 7Ux9mGGnbRJt5i3GS2Zg9SLx+sxwS1NozUfgJskwTle0pVXHEz/rM3HqwJBYO9TgRebV P2qYrdzk7eOoaqAy8h4VRGXjJNWqrc17MiC71LdrqoeT3tyqBwjqNt6uPhBOqVwtAUPK jLNiz/h3pWnuPylSN6L7l6IgxXkuaxc4jDThDqYPwdrfDy8LoS2fpJqopzIGd+Huqldv 6Amjk5OoGsd+i09phB5dVDCxxMmTHHitV+i1kv8F6kYYAoSsoZ7VVv+h/VOC4Smz4sPQ YKeA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:subject:to:cc:references:from:message-id :date:user-agent:mime-version:in-reply-to:content-language :content-transfer-encoding; bh=grex/scWDItlhlGFXvO1kPgEMarCyOey7CuOC+Bd9Lw=; b=UQeN8UeF47wm3+u9NGZcaCjWEg7WEe9nq/GSasc+YwmBR45ehtLYAFR20nfhn58+Br s+V+5qaA/sPG1Rnv8EH2SlWBbpLwXZYbBiTAn5NXHytoYlzCCEX69N5rSWsWM0En1DhK PoDbXyu0MwDR82jb6JImUI9ZqcTJilFYCaJr36gk0mjtca/i7aoDolg6FTmKZ6qVRg1L MxEcINBgaKtV3h2r6Lb6Oo46T6KOtfOKLpDVa4RxqrGs2QXSGZxYqfi30gjRoMxHGOcC LOpxCK3wxOdt0O7yF0vU2J7Wcybz5zrQPDi9UqCfPbURs2t8eGSXn/XCPq22bPq39X16 EU5w== X-Gm-Message-State: AHPjjUhxrYBemS9dlCaL432XmbFrf0nw2ow6QYfiV0TfH+Y99V8QBsSR XrGgM4alISVA+g== X-Google-Smtp-Source: ADKCNb7FC9a5Ed3u0vuJXf7cRhmZZ6UijkaP09p5tHw+kYOwXRvyRPy8p+76sXwrhF/0xqoeu134Mw== X-Received: by 10.55.78.140 with SMTP id c134mr165555qkb.185.1504222836660; Thu, 31 Aug 2017 16:40:36 -0700 (PDT) Received: from [192.168.1.10] ([181.93.89.178]) by smtp.gmail.com with ESMTPSA id t5sm6376025qkl.59.2017.08.31.16.40.34 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 31 Aug 2017 16:40:36 -0700 (PDT) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= To: Alistair Francis Cc: Peter Maydell , Subbaraya Sundeep , QEMU Developers , qemu-arm , Peter Crosthwaite References: <1503938283-12404-1-git-send-email-sundeep.lkml@gmail.com> <1503938283-12404-5-git-send-email-sundeep.lkml@gmail.com> <10da5552-c90a-21e6-43ac-829932f64930@amsat.org> <40ca8d07-75e5-e0b3-021e-5abaffd16b78@amsat.org> From: =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= Message-ID: Date: Thu, 31 Aug 2017 20:40:32 -0300 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.3.0 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=utf-8; format=flowed Content-Language: en-US Content-Transfer-Encoding: 8bit X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400d:c09::243 Subject: Re: [Qemu-arm] [Qemu devel v7 PATCH 4/5] msf2: Add Smartfusion2 SoC X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 31 Aug 2017 23:40:44 -0000 Hi Alistair, On 08/31/2017 08:02 PM, Alistair Francis wrote: > On Wed, Aug 30, 2017 at 7:47 AM, Philippe Mathieu-Daudé wrote: >> On 08/30/2017 09:26 AM, Peter Maydell wrote: >>> >>> On 30 August 2017 at 03:45, Philippe Mathieu-Daudé >>> wrote: >>>> >>>> I think they might be issues if you start QEMU without -serial and then >>>> use >>>> a firmware polling for an uart, the device won't be mapped and the memory >>>> accesses are mostly ignored. >>>> >>>> I'd rather use: >>>> >>>> for (i = 0; i < MSF2_NUM_UARTS && i < MAX_SERIAL_PORTS; i++) { >>>> static const char *serial[] = {"serial0", "serial1"}; >>>> >>>> if (!serial_hds[i]) { >>>> serial_hds[i] = qemu_chr_new(serial[i], "null"); >>>> >>>> } >>>> >>>>> + serial_mm_init(get_system_memory(), uart_addr[i], 2, >>>>> + qdev_get_gpio_in(armv7m, uart_irq[i]), >>>>> + 115200, serial_hds[i], >>>>> DEVICE_NATIVE_ENDIAN); >>>>> + } >>>>> + } >>> >>> >>> It would be better to fix serial_mm_init() to handle having >>> a NULL chardev pointer, because we already have a lot of >>> SoC code that just passes it serial_hds[] regardless. >> >> >> clever :) >> >>> I'd leave this code as it is and we can fix serial_mm_init >>> separately (somebody pointed out this issue for a xilinx >>> board recently). > > Ah, I'll look into this then. I already sent a series to take care of this: http://lists.nongnu.org/archive/html/qemu-devel/2017-08/msg06325.html I'll respin a v2 shortly. From MAILER-DAEMON Thu Aug 31 19:44:32 2017 Received: from list by lists.gnu.org with archive (Exim 4.71) id 1dnZ8S-0007De-8h for mharc-qemu-arm@gnu.org; Thu, 31 Aug 2017 19:44:32 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:47625) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dnZ8Q-0007C2-1d for qemu-arm@nongnu.org; Thu, 31 Aug 2017 19:44:31 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dnZ8P-0006Hu-1R for qemu-arm@nongnu.org; Thu, 31 Aug 2017 19:44:30 -0400 Received: from mail-wm0-x22f.google.com ([2a00:1450:400c:c09::22f]:38881) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1dnZ8M-0006GE-JH; Thu, 31 Aug 2017 19:44:26 -0400 Received: by mail-wm0-x22f.google.com with SMTP id 187so6276261wmn.1; Thu, 31 Aug 2017 16:44:25 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=mime-version:in-reply-to:references:from:date:message-id:subject:to :cc:content-transfer-encoding; bh=NPOlzsPv66RU/we83NWp1iZ3CB9TROLc8LPTS2ltmOA=; b=O1o0vjZG4DFd5i1kwthyH0HI+VVoPUAW8kW92/+/8EHPYK8zldmG09xcjQ1wZEanBt 66CCNjOJsUMP36Cp46KFP+kbndOxTtB3c9/k0HSkvASfxhzaggOjY++ZryPmpcjVpMRM NCYcfYTHfrN8NSUUy3YjzfJIw6y0V8drIUO7KzzS0XZDEqlwqJyzR63E4SOUsn5wvsGi qtDF4fAPvlKd1gK2QmvDre2sFPLYxJuZsUsweIyjy4aIboW21c5s4njF0zP/o8Z21Pjm AAMzO+ZtHh2etKXanpGPV8GY7rSukqFMMA19z+XDyvYoYkPvSCxHgwsz26sd2jAMjAJR NSRw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:in-reply-to:references:from:date :message-id:subject:to:cc:content-transfer-encoding; bh=NPOlzsPv66RU/we83NWp1iZ3CB9TROLc8LPTS2ltmOA=; b=IMoHPkff7BBNlrLrtyEcH66tukXH7aUoFmsaeNwd6O1JSYN4LSQfQ24tfu7iSdyoD/ IpGxBbQTUcSgMYGdFeuBAUP2LpqEDGoNVWAdis4DowTdOkXfG/TqqHPClY1mfKXbBQGb lgFiJaaP1W5VqFY2iWKVl+4MjeSxr40KdayplqXiXP7MM4iOg17BdSboWuZJJ77kZqrT OEFu4h6NBjUxwr6MC04euJhLkyaZU+y3QYA4Ud4pkwzwA2/sCv68G+NLZP3EnLfpJuDE ViQeURrdwLaCIlerzzpTmM3KjzWES4BH2ra/1GUsxtbPvCIlOeMt4HN7W/L3oNxiLIOx fXkA== X-Gm-Message-State: AHPjjUiIRQoDxpymuOzUBg6Pn8UNayt/UlsxJ6qSVPBL9EwJlnOPwKux ZcDPUGPgb02TrVVl1sh31eo/gY+YrViK X-Google-Smtp-Source: ADKCNb4dmKakomz8nlQsedE23OWX/oHY0H9psp5b/cBQhyqiv2zGp43az/DXrKK8A1FbqDylg0ZTzIxRJ173zARYaKI= X-Received: by 10.28.67.197 with SMTP id q188mr1589360wma.156.1504223064223; Thu, 31 Aug 2017 16:44:24 -0700 (PDT) MIME-Version: 1.0 Received: by 10.28.191.130 with HTTP; Thu, 31 Aug 2017 16:43:53 -0700 (PDT) In-Reply-To: References: <1503938283-12404-1-git-send-email-sundeep.lkml@gmail.com> <1503938283-12404-5-git-send-email-sundeep.lkml@gmail.com> <10da5552-c90a-21e6-43ac-829932f64930@amsat.org> <40ca8d07-75e5-e0b3-021e-5abaffd16b78@amsat.org> From: Alistair Francis Date: Thu, 31 Aug 2017 16:43:53 -0700 Message-ID: To: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= Cc: Peter Maydell , Subbaraya Sundeep , QEMU Developers , qemu-arm , Peter Crosthwaite Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:400c:c09::22f Subject: Re: [Qemu-arm] [Qemu devel v7 PATCH 4/5] msf2: Add Smartfusion2 SoC X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 31 Aug 2017 23:44:31 -0000 On Thu, Aug 31, 2017 at 4:40 PM, Philippe Mathieu-Daud=C3=A9 wrote: > Hi Alistair, > > > On 08/31/2017 08:02 PM, Alistair Francis wrote: >> >> On Wed, Aug 30, 2017 at 7:47 AM, Philippe Mathieu-Daud=C3=A9 >> wrote: >>> >>> On 08/30/2017 09:26 AM, Peter Maydell wrote: >>>> >>>> >>>> On 30 August 2017 at 03:45, Philippe Mathieu-Daud=C3=A9 >>>> wrote: >>>>> >>>>> >>>>> I think they might be issues if you start QEMU without -serial and th= en >>>>> use >>>>> a firmware polling for an uart, the device won't be mapped and the >>>>> memory >>>>> accesses are mostly ignored. >>>>> >>>>> I'd rather use: >>>>> >>>>> for (i =3D 0; i < MSF2_NUM_UARTS && i < MAX_SERIAL_PORTS; i++) = { >>>>> static const char *serial[] =3D {"serial0", "serial1"}; >>>>> >>>>> if (!serial_hds[i]) { >>>>> serial_hds[i] =3D qemu_chr_new(serial[i], "null"); >>>>> >>>>> } >>>>> >>>>>> + serial_mm_init(get_system_memory(), uart_addr[i], 2, >>>>>> + qdev_get_gpio_in(armv7m, uart_irq[i]), >>>>>> + 115200, serial_hds[i], >>>>>> DEVICE_NATIVE_ENDIAN); >>>>>> + } >>>>>> + } >>>> >>>> >>>> >>>> It would be better to fix serial_mm_init() to handle having >>>> a NULL chardev pointer, because we already have a lot of >>>> SoC code that just passes it serial_hds[] regardless. >>> >>> >>> >>> clever :) >>> >>>> I'd leave this code as it is and we can fix serial_mm_init >>>> separately (somebody pointed out this issue for a xilinx >>>> board recently). >> >> >> Ah, I'll look into this then. > > > I already sent a series to take care of this: > > http://lists.nongnu.org/archive/html/qemu-devel/2017-08/msg06325.html That was quick. Can you CC me on the next version? Thanks, Alistair > > I'll respin a v2 shortly.