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Sun, 01 Dec 2019 12:05:24 -0800 (PST) X-Google-Smtp-Source: APXvYqy4jTyXyxeHgy0eg7V/dgHnDVwjfOAayTAZjtw4jDTRZt3In4A0/hAB8CO6XLvX/GuyUCVAHA== X-Received: by 2002:a5d:4cc9:: with SMTP id c9mr17016390wrt.70.1575230724270; Sun, 01 Dec 2019 12:05:24 -0800 (PST) Received: from [10.101.1.81] ([176.12.107.132]) by smtp.gmail.com with ESMTPSA id x17sm15198809wrt.74.2019.12.01.12.05.23 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Sun, 01 Dec 2019 12:05:23 -0800 (PST) Subject: Re: [PATCH v2 06/14] target/arm: use gdb_get_reg helpers To: =?UTF-8?Q?Alex_Benn=c3=a9e?= , qemu-devel@nongnu.org Cc: damien.hedde@greensocs.com, Peter Maydell , luis.machado@linaro.org, richard.henderson@linaro.org, "open list:ARM TCG CPUs" , alan.hayward@arm.com References: <20191130084602.10818-1-alex.bennee@linaro.org> <20191130084602.10818-7-alex.bennee@linaro.org> From: =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= Message-ID: <987465d3-3b13-e675-9622-c13e2d5205c2@redhat.com> Date: Sun, 1 Dec 2019 21:05:22 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.1.1 MIME-Version: 1.0 In-Reply-To: <20191130084602.10818-7-alex.bennee@linaro.org> Content-Language: en-US X-MC-Unique: T478qlUdPgyjqOePAkDKMA-1 X-Mimecast-Spam-Score: 0 Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 205.139.110.120 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sun, 01 Dec 2019 20:05:29 -0000 On 11/30/19 9:45 AM, Alex Benn=C3=A9e wrote: > This is cleaner than poking memory directly and will make later > clean-ups easier. >=20 > Signed-off-by: Alex Benn=C3=A9e >=20 > --- > v2 > - make sure we pass hi/lo correctly as quads are stored in LE order > --- > target/arm/helper.c | 18 +++++++----------- > 1 file changed, 7 insertions(+), 11 deletions(-) >=20 > diff --git a/target/arm/helper.c b/target/arm/helper.c > index 0bf8f53d4b8..0ac950d6c71 100644 > --- a/target/arm/helper.c > +++ b/target/arm/helper.c > @@ -105,21 +105,17 @@ static int aarch64_fpu_gdb_get_reg(CPUARMState *env= , uint8_t *buf, int reg) > { > switch (reg) { > case 0 ... 31: > - /* 128 bit FP register */ > - { > - uint64_t *q =3D aa64_vfp_qreg(env, reg); > - stq_le_p(buf, q[0]); > - stq_le_p(buf + 8, q[1]); > - return 16; > - } > + { > + /* 128 bit FP register - quads are in LE order */ Oh, this was always wrong on BE :( Reviewed-by: Philippe Mathieu-Daud=C3=A9 > + uint64_t *q =3D aa64_vfp_qreg(env, reg); > + return gdb_get_reg128(buf, q[1], q[0]); > + } > case 32: > /* FPSR */ > - stl_p(buf, vfp_get_fpsr(env)); > - return 4; > + return gdb_get_reg32(buf, vfp_get_fpsr(env)); > case 33: > /* FPCR */ > - stl_p(buf, vfp_get_fpcr(env)); > - return 4; > + return gdb_get_reg32(buf,vfp_get_fpcr(env)); > default: > return 0; > } >=20 From MAILER-DAEMON Sun Dec 01 15:13:13 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1ibVaj-0004sI-NW for mharc-qemu-arm@gnu.org; Sun, 01 Dec 2019 15:13:13 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:41176) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ibVah-0004rr-AE for qemu-arm@nongnu.org; Sun, 01 Dec 2019 15:13:12 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ibVag-0008WS-2h for qemu-arm@nongnu.org; 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[97.113.7.119]) by smtp.gmail.com with ESMTPSA id g30sm30333407pgm.23.2019.12.01.12.13.06 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Sun, 01 Dec 2019 12:13:06 -0800 (PST) Subject: Re: [PATCH] target/arm: Allow loading elf from aliased ROM regions To: =?UTF-8?Q?Jean-Hugues_Desch=c3=aanes?= , "qemu-arm@nongnu.org" , "qemu-devel@nongnu.org" Cc: "peter.maydell@linaro.org" , "martin.galvan@tallertechnologies.com" , "thuth@redhat.com" References: <20191125124055.19286-1-jean-hugues.deschenes@ossiaco.com> From: Richard Henderson Message-ID: <3e2857fd-aa5e-acc5-edd6-359715a636a6@linaro.org> Date: Sun, 1 Dec 2019 12:13:05 -0800 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.2.1 MIME-Version: 1.0 In-Reply-To: <20191125124055.19286-1-jean-hugues.deschenes@ossiaco.com> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 8bit X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::1041 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sun, 01 Dec 2019 20:13:12 -0000 On 11/25/19 12:41 PM, Jean-Hugues Deschênes wrote: > initial_msp = ldl_p(rom); > initial_pc = ldl_p(rom + 4); > } else { > - /* Address zero not covered by a ROM blob, or the ROM blob > - * is in non-modifiable memory and this is a second reset after > - * it got copied into memory. In the latter case, rom_ptr > - * will return a NULL pointer and we should use ldl_phys instead. > - */ > - initial_msp = ldl_phys(s->as, vecbase); > - initial_pc = ldl_phys(s->as, vecbase + 4); > + /* See if the ROM blob is aliased somewhere */ > + hwaddr len = 0, xlat = 0; > + MemoryRegion *mr = address_space_translate(s->as, vecbase, &xlat, > + &len, false, MEMTXATTRS_UNSPECIFIED); > + > + if (mr) { > + rom = rom_ptr(mr->addr + xlat, 8); > + } else { > + rom = NULL; > + } > + > + if (rom) { > + initial_msp = ldl_p(rom); > + initial_pc = ldl_p(rom + 4); > + } else { > + > + /* > + * Address zero not covered by a ROM blob, or the ROM blob > + * is in non-modifiable memory and this is a second reset after > + * it got copied into memory. In the latter case, rom_ptr > + * will return a NULL pointer and we should use ldl_phys > + * instead. > + */ > + initial_msp = ldl_phys(s->as, vecbase); > + initial_pc = ldl_phys(s->as, vecbase + 4); > + } > } Can this entire section, including the rom_ptr thing just above, be replaced with two address_space_read()? r~ From MAILER-DAEMON Sun Dec 01 17:31:39 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1ibXkh-00040Q-Bl for mharc-qemu-arm@gnu.org; Sun, 01 Dec 2019 17:31:39 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:60352) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ibXke-000401-9Y for qemu-arm@nongnu.org; Sun, 01 Dec 2019 17:31:37 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ibXkc-0006KT-U5 for qemu-arm@nongnu.org; Sun, 01 Dec 2019 17:31:36 -0500 Received: from mail-oi1-x242.google.com ([2607:f8b0:4864:20::242]:46572) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ibXkc-0006KA-Ow for qemu-arm@nongnu.org; Sun, 01 Dec 2019 17:31:34 -0500 Received: by mail-oi1-x242.google.com with SMTP id a124so6998296oii.13 for ; Sun, 01 Dec 2019 14:31:34 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc:content-transfer-encoding; bh=w7F4VBjJzLVDVvrTxAEbhzicn/QifA6Kt+COVO7sJEY=; b=z4ZGH9a1AFSpuYwTuzSu5tCiP/SwhHW8TzxS2JG04NJ0Ybbgrn2AyMDAY0MbJBr5AN THpWmOXpFG8icza/X3kyrQkOB0bekH7a3Rg9CYaGQE6UNcp3d/mINh2RajVursy+v1SP qgqhG3G8I1vQOg27kBqKUYw1vzMgY8CMquFI4z7aV9/c5BDM2nIi3ooEjLj+RRpiVZWY O/ZwbWPiT422GnMaQs6+4WGoBoCbR9HCDmJxDaW9ZwL1Huq4qNUel11Pn59pkh+DekvZ yVHQYY5wm167TE6tUw3g/yTKua2qkhgUCVyCCpQO0HSXj9irc5geQZ5Z9LrHf+I1VUmj EXmw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc:content-transfer-encoding; bh=w7F4VBjJzLVDVvrTxAEbhzicn/QifA6Kt+COVO7sJEY=; b=QsQ05YASbM5XZGDQAb/IP1jT44vDr7c6xSvMxxnHaGQzSnejge66D/xuiSxTITI3QA tW2wgxQ/ukLRqs3G0M8JbR9MIM/WRDJeWS9K1Xx1SH28l2ULrceqqSSwBG9RB/xjxREE QO4Z8yK0s3ZamHJ+e+NEoW/zxaGJGUofTqxRFT5wxuzc7Vh/XDctr5AYE+CcDZsiZMvL n9nuugFs2+p8FPgTU22M1R6HNycTTpt3uVS58W/r88FctR38JHXcTUI4Lw1HLbjaly31 XmJMORNj19mFFS0U7GWZtU7XATjEoBk2oOQcH/8Rx1hf2jpMvZcLA2rzmgnhpX6lUG3p +aKQ== X-Gm-Message-State: APjAAAWwSx+4SK+dg5SBYF2OtRhFY+wvfsj67cdrGlGPZmUpLqkKVgIa /LCkVWW1hkgD35OujppxrJFO9AXVHTRtxcxlq/WJ4Q== X-Google-Smtp-Source: APXvYqy0sUyVSR/xwo4pjRRKuoPEtZ8KuA3KXTPeI/v8/tjIkzCtbgLrg6D+10AMK5CAxRj7MfUlBmY1xMLYYqv9oWM= X-Received: by 2002:aca:edd5:: with SMTP id l204mr10040049oih.98.1575239493528; Sun, 01 Dec 2019 14:31:33 -0800 (PST) MIME-Version: 1.0 References: <20191125124055.19286-1-jean-hugues.deschenes@ossiaco.com> <3e2857fd-aa5e-acc5-edd6-359715a636a6@linaro.org> In-Reply-To: <3e2857fd-aa5e-acc5-edd6-359715a636a6@linaro.org> From: Peter Maydell Date: Sun, 1 Dec 2019 22:31:22 +0000 Message-ID: Subject: Re: [PATCH] target/arm: Allow loading elf from aliased ROM regions To: Richard Henderson Cc: =?UTF-8?Q?Jean=2DHugues_Desch=C3=AAnes?= , "qemu-arm@nongnu.org" , "qemu-devel@nongnu.org" , "martin.galvan@tallertechnologies.com" , "thuth@redhat.com" Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::242 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sun, 01 Dec 2019 22:31:37 -0000 On Sun, 1 Dec 2019 at 20:13, Richard Henderson wrote: > > On 11/25/19 12:41 PM, Jean-Hugues Desch=C3=AAnes wrote: > > initial_msp =3D ldl_p(rom); > > initial_pc =3D ldl_p(rom + 4); > > } else { > > - /* Address zero not covered by a ROM blob, or the ROM blob > > - * is in non-modifiable memory and this is a second reset = after > > - * it got copied into memory. In the latter case, rom_ptr > > - * will return a NULL pointer and we should use ldl_phys i= nstead. > > - */ > > - initial_msp =3D ldl_phys(s->as, vecbase); > > - initial_pc =3D ldl_phys(s->as, vecbase + 4); > > + /* See if the ROM blob is aliased somewhere */ > > + hwaddr len =3D 0, xlat =3D 0; > > + MemoryRegion *mr =3D address_space_translate(s->as, vecbas= e, &xlat, > > + &len, false, MEMTXATTRS_UNSPECIFIED); > > + > > + if (mr) { > > + rom =3D rom_ptr(mr->addr + xlat, 8); > > + } else { > > + rom =3D NULL; > > + } > > + > > + if (rom) { > > + initial_msp =3D ldl_p(rom); > > + initial_pc =3D ldl_p(rom + 4); > > + } else { > > + > > + /* > > + * Address zero not covered by a ROM blob, or the ROM = blob > > + * is in non-modifiable memory and this is a second re= set after > > + * it got copied into memory. In the latter case, rom_= ptr > > + * will return a NULL pointer and we should use ldl_ph= ys > > + * instead. > > + */ > > + initial_msp =3D ldl_phys(s->as, vecbase); > > + initial_pc =3D ldl_phys(s->as, vecbase + 4); > > + } > > } > > Can this entire section, including the rom_ptr thing just above, be repla= ced > with two address_space_read()? No. This is a reset ordering problem. The CPU reset happens before the 'rom blob loader' reset, so at this point the rom data (usually an ELF file segment) has not been written into ram, and doing an address_space_read() will just read zeroes. This is also why the aliasing issue happens at all -- the rom blob is at a particular address, but if the address we use here to try to read the data is an aliased variant of it then rom_ptr() does the wrong thing. My preference for fixing this properly is: * get Damien's three-phase-reset patchset into master * make the ROM blob loader write its data into ram in phase 2 ('hold') * make the arm CPU reset read the data in phase 3 ('exit') This last matches better what the hardware does -- the M-profile CPU reads the vector table in the first couple of clock cycles when it *leaves* reset, not while the CPU is being *held* in reset. This kind of thing is always awkward to model in an emulator, especially if you were hoping to also handle allowing the PC to be set from an ELF file entrypoint or by the user in the gdbstub on startup... thanks -- PMM From MAILER-DAEMON Sun Dec 01 17:50:12 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1ibY2c-0002xT-VE for mharc-qemu-arm@gnu.org; Sun, 01 Dec 2019 17:50:12 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:34208) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ibY2V-0002wN-TA for qemu-arm@nongnu.org; Sun, 01 Dec 2019 17:50:05 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ibY2U-0006vr-3V for qemu-arm@nongnu.org; Sun, 01 Dec 2019 17:50:03 -0500 Received: from mail-eopbgr660061.outbound.protection.outlook.com ([40.107.66.61]:6464 helo=CAN01-QB1-obe.outbound.protection.outlook.com) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1ibY2T-0006uu-Q5; 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charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::243 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sun, 01 Dec 2019 22:52:08 -0000 On Sun, 1 Dec 2019 at 22:50, Jean-Hugues Desch=C3=AAnes wrote: > > My preference for fixing this properly is: > > * get Damien's three-phase-reset patchset into master > > * make the ROM blob loader write its data into ram > > in phase 2 ('hold') > > * make the arm CPU reset read the data in phase 3 ('exit') > Makes perfect sense. Feel free to drop the patch. Well, I'm still vaguely tracking this patch; we might want a temporary-fix if it looks like the phased-reset approach is going to take too long to get into master. thanks -- PMM From MAILER-DAEMON Sun Dec 01 21:20:37 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1ibbKH-0002pb-PY for mharc-qemu-arm@gnu.org; Sun, 01 Dec 2019 21:20:37 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:58526) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ibbKE-0002mi-VN for qemu-arm@nongnu.org; Sun, 01 Dec 2019 21:20:35 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ibbKD-0003zC-Tj for qemu-arm@nongnu.org; Sun, 01 Dec 2019 21:20:34 -0500 Received: from mail-pl1-x644.google.com ([2607:f8b0:4864:20::644]:33642) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ibbKD-0003yq-ON for qemu-arm@nongnu.org; Sun, 01 Dec 2019 21:20:33 -0500 Received: by mail-pl1-x644.google.com with SMTP id ay6so15570173plb.0 for ; Sun, 01 Dec 2019 18:20:33 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=subject:to:cc:references:from:message-id:date:user-agent :mime-version:in-reply-to:content-language:content-transfer-encoding; bh=5hUapDdSTy6UoCaM66PJkqib1gmdUsvni7at3Ufdd7s=; b=jHYnvDBVn58Ny1PQUdsLQnJQpPYnabVyORpefXghJEcMTp7k4NYdar5CnmOMda27XM GT6yYXdrwrLII+FwZrurAeY8wq3XhhRTMM1SebX/zEjLTMursTOHxibXwWCc7xDbtB9Q 5Iy4Usnd+d2xeKoa8SkQ4QtE5EYvTmzOW24EawViHoBQtr0bF+HPe332P6RR2QM125k5 1hB1Re7CEYWSMCN4O2nzUUS9hKjT7rR7QRDjMlLvVqfyLOd0mZQ0+EcnKIV6iXlZ8xU6 G5P0IclncwYpW7g9Qp5iDC+ShhFmcc8g69hYDLgGJvYN4jrLVAhFoHXnVANQp29RoouN UO9Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:subject:to:cc:references:from:message-id:date :user-agent:mime-version:in-reply-to:content-language :content-transfer-encoding; bh=5hUapDdSTy6UoCaM66PJkqib1gmdUsvni7at3Ufdd7s=; b=C21F94jPBI09xKi3DgpIPqpBjdi7gmuy/sMfTIv16AIYVWv2JMeUK8wDFFCmwz7BHi ENXlYkthFjug5Ij92xm++zrfQbuuTI8tybVtvlTS1WdOmz4ETnsr3wkpabtpxbNAWG+I FGl44vxA7Syva95J8BedNK2K9tRs8sowKdJ1q9l2+ZGcsZPM+WCSYe3r4HHLtTk7DjSb hLnoPXNcOJ2o1YxBzGYUWFqBpI7sxdSleuOIceWduavAAK86oWwx/xXOm2x7UV64P8tn pAI1mnTodbITn9ly7gqiXrFdBswRRsvO2ImxQnVK6qM9MZIX0rnEptHzKkTOd+fnsBqf s4gQ== X-Gm-Message-State: APjAAAVtQxLizpYgg6V8gUDWjkJgYKZK0h5nGisyNMn89iwi2Kq2ofN9 QHlZeown+6rL62n7bhiliBT4mk/sUPc= X-Google-Smtp-Source: APXvYqzcXDYGSuCRSjKxq1xJuolroMKTSgTJZV9U8azUqGUsCSbKV2uX9/86J7AjdunGuI+f6h+ZnQ== X-Received: by 2002:a17:90a:650c:: with SMTP id i12mr33314855pjj.28.1575253232515; Sun, 01 Dec 2019 18:20:32 -0800 (PST) Received: from [192.168.1.11] (97-113-7-119.tukw.qwest.net. [97.113.7.119]) by smtp.gmail.com with ESMTPSA id u7sm31314045pfh.84.2019.12.01.18.20.31 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Sun, 01 Dec 2019 18:20:31 -0800 (PST) Subject: Re: [PATCH v2 06/14] target/arm: use gdb_get_reg helpers To: =?UTF-8?Q?Alex_Benn=c3=a9e?= , qemu-devel@nongnu.org Cc: alan.hayward@arm.com, luis.machado@linaro.org, damien.hedde@greensocs.com, Peter Maydell , "open list:ARM TCG CPUs" References: <20191130084602.10818-1-alex.bennee@linaro.org> <20191130084602.10818-7-alex.bennee@linaro.org> From: Richard Henderson Message-ID: Date: Sun, 1 Dec 2019 18:20:29 -0800 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.2.1 MIME-Version: 1.0 In-Reply-To: <20191130084602.10818-7-alex.bennee@linaro.org> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 8bit X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::644 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 02 Dec 2019 02:20:36 -0000 On 11/30/19 8:45 AM, Alex Bennée wrote: > This is cleaner than poking memory directly and will make later > clean-ups easier. > > Signed-off-by: Alex Bennée > > --- > v2 > - make sure we pass hi/lo correctly as quads are stored in LE order > --- > target/arm/helper.c | 18 +++++++----------- > 1 file changed, 7 insertions(+), 11 deletions(-) Reviewed-by: Richard Henderson r~ From MAILER-DAEMON Sun Dec 01 21:24:55 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1ibbOQ-0005N8-Sr for mharc-qemu-arm@gnu.org; Sun, 01 Dec 2019 21:24:54 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:59285) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ibbOP-0005Kz-0e for qemu-arm@nongnu.org; Sun, 01 Dec 2019 21:24:54 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ibbON-0007Om-QA for qemu-arm@nongnu.org; Sun, 01 Dec 2019 21:24:52 -0500 Received: from mail-pj1-x1042.google.com ([2607:f8b0:4864:20::1042]:44064) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ibbON-0007O4-JW for qemu-arm@nongnu.org; Sun, 01 Dec 2019 21:24:51 -0500 Received: by mail-pj1-x1042.google.com with SMTP id w5so1433058pjh.11 for ; Sun, 01 Dec 2019 18:24:51 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=subject:to:cc:references:from:message-id:date:user-agent :mime-version:in-reply-to:content-language:content-transfer-encoding; bh=9uZMeOcjp69CcLk4kJoh51jLK8rzeIE59U8CnyNM9uw=; b=NdKXEZFPqImyiun752tSnpnNEyZG0dTjM0NwfMw7m/reaycfYDF5JhWaLkXPkOm+hW YtJqnFRYK+0i68KbHUGbwDX7xf2L5eRwOn0Z4XexdP5slDmA5M9LquKLrv4macGSEYB+ s5lvW11sgcZfqb3Fz8f+XJD2vb21K0F+tofwnUu1/gRNzCoMkcxH2ttbHaiiykR0sR80 zKnYQhYym+rUBSKupGJLIAaTPKdO44FmyaKa+ejylbqwcUx+cNLcEDR3D+he+esdPIw/ sVYX/yIT9nXJNPQnA151wsnHZN1GMcCzCZX7udc5Evd2SyE0OrSvQbR5JwmWTD5ld3sc sV7A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:subject:to:cc:references:from:message-id:date :user-agent:mime-version:in-reply-to:content-language :content-transfer-encoding; bh=9uZMeOcjp69CcLk4kJoh51jLK8rzeIE59U8CnyNM9uw=; b=ZwxEs7anutKfrptbCIzHjzWJu/wwMVhn+bFyNLuVi5bvPTCnuS7x/K/Rz0W6SRInyc dIRqC6w9JC2q76dBpXjM0VKZ/mysEVGgOyhvqWpgdzA4koRRrsVn//xei94CQLNYyTMY UngzaBVBb588jgJPXi0tqnI4BEHuIETz6mtv+jtUHX2kwkJ9htKr4T8zkljgl7hfxLqv 81jyTzAw0TIYhrbUtiSdpjpa0kYMlVJHogKtO/D6gQA3363q9QLXqzz7qDIANFj04SLe 2zqnuAELLHSSFMRxsQg3GziW4e3QGytD+zVkbktQ7Dk45UJEftPCED5N1mvl+/IVrDLn ahnQ== X-Gm-Message-State: APjAAAWwFBHmtWn2Hq7SvyfG6SzIiSTCz6e+NCPuCHKRWPB3rYkoYULl DAsIJ2r8NkNHkwqeQtaDLezXXg== X-Google-Smtp-Source: APXvYqwNCsLHCmgtq4yEB82YTo8Go2tM/yn6Jyk+zdoQ0lb8zpr6smFP27PzPme3sWBdki3UBROaiw== X-Received: by 2002:a17:90a:30a4:: with SMTP id h33mr32078066pjb.50.1575253490309; Sun, 01 Dec 2019 18:24:50 -0800 (PST) Received: from [192.168.1.11] (97-113-7-119.tukw.qwest.net. [97.113.7.119]) by smtp.gmail.com with ESMTPSA id h3sm20818336pji.16.2019.12.01.18.24.48 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Sun, 01 Dec 2019 18:24:49 -0800 (PST) Subject: Re: [PATCH v2 08/14] gdbstub: extend GByteArray to read register helpers To: =?UTF-8?Q?Alex_Benn=c3=a9e?= , qemu-devel@nongnu.org Cc: alan.hayward@arm.com, luis.machado@linaro.org, damien.hedde@greensocs.com, =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= , Eduardo Habkost , Marcel Apfelbaum , Richard Henderson , Peter Maydell , "Edgar E. Iglesias" , Paolo Bonzini , Michael Walle , Laurent Vivier , Aurelien Jarno , Aleksandar Markovic , Aleksandar Rikalo , Chris Wulff , Marek Vasut , Stafford Horne , David Gibson , Palmer Dabbelt , Alistair Francis , Sagar Karandikar , Bastian Koppelmann , David Hildenbrand , Cornelia Huck , Mark Cave-Ayland , Artyom Tarasenko , Max Filippov , "open list:ARM TCG CPUs" , "open list:PowerPC TCG CPUs" , "open list:RISC-V TCG CPUs" , "open list:S390 TCG CPUs" References: <20191130084602.10818-1-alex.bennee@linaro.org> <20191130084602.10818-9-alex.bennee@linaro.org> From: Richard Henderson Message-ID: Date: Sun, 1 Dec 2019 18:24:47 -0800 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.2.1 MIME-Version: 1.0 In-Reply-To: <20191130084602.10818-9-alex.bennee@linaro.org> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 8bit X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::1042 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 02 Dec 2019 02:24:54 -0000 On 11/30/19 8:45 AM, Alex Bennée wrote: > -static int cpu_read_virt_reg(CPUS390XState *env, uint8_t *mem_buf, int n) > +static int cpu_read_virt_reg(CPUS390XState *env, GByteArray *mem_buf, int n) > { > switch (n) { > case S390_VIRT_CKC_REGNUM: > @@ -296,9 +296,9 @@ static int cpu_write_virt_reg(CPUS390XState *env, uint8_t *mem_buf, int n) > /* total number of registers in s390-gs.xml */ > #define S390_NUM_GS_REGS 4 > > -static int cpu_read_gs_reg(CPUS390XState *env, uint8_t *mem_buf, int n) > +static int cpu_read_gs_reg(CPUS390XState *env, GByteArray *buf, int n) Sometimes you're changing the name from mem_buf and sometimes not. Perhaps better not to change it anywhere, or change it everywhere first, without changing the type. r~ From MAILER-DAEMON Sun Dec 01 21:41:42 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1ibbeg-0002ro-Nv for mharc-qemu-arm@gnu.org; Sun, 01 Dec 2019 21:41:42 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:33400) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ibbed-0002pG-Op for qemu-arm@nongnu.org; Sun, 01 Dec 2019 21:41:40 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ibbec-0008RK-JQ for qemu-arm@nongnu.org; Sun, 01 Dec 2019 21:41:39 -0500 Received: from mail-pl1-x642.google.com ([2607:f8b0:4864:20::642]:43688) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ibbec-0008Qd-BT for qemu-arm@nongnu.org; Sun, 01 Dec 2019 21:41:38 -0500 Received: by mail-pl1-x642.google.com with SMTP id q16so11384397plr.10 for ; Sun, 01 Dec 2019 18:41:38 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=subject:to:cc:references:from:message-id:date:user-agent :mime-version:in-reply-to:content-language:content-transfer-encoding; bh=c13Wjzos1EtGKKvew52DvMGXElPNobtTinpSlmyukJA=; b=NKlNgjFQi6sOk7HkO8p4H2g/ovKzfs0J94FjBbxdCd36Y4m9tvWePzC7/XYhvTgFi8 qmPC+NHbeOAXw9kVJubX6e5o6GjZ0HmTFmhPFgO7Pk4alsSBHA1HbOlIEzwrjxkxZ9OB PCVcEq4WuFMTaE+2FFTLuOb1GIETNMrcvAeQdV6Sx/5MfDbQYcNUBvCP2RmbC2rK79/h bywxmJON8h3vF3aSfXsf3MmyqUDg/bPeETBaUpRRdRpJhtGsWwqdC9QPrZnfPapPwHwv dSwMlmHgbBDhUp/XflIn99HfTwF4tZjTqoc3oKQFd8HYQlBLKl1kb+8xHKzJXPWnRe7n PZZg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:subject:to:cc:references:from:message-id:date :user-agent:mime-version:in-reply-to:content-language :content-transfer-encoding; bh=c13Wjzos1EtGKKvew52DvMGXElPNobtTinpSlmyukJA=; b=l0eDVH3gUcWd0rUXfiUaUj5h4wgpLCeEnWq8lsWuAqGhtnkbKSvM7L63OKh/nCrqUH dTF4S1BReiGdcNX7m67ufzVtN05DKglkOxcEO0kjWYx5s9NtfbInDh6iO/QAsOAYUb1G mP7JG8gGPsHHLwizh3EV6+qaT1I4yvvBAm1+ebkBgP8nPzyi+gIQ7IMZ7eQ4srwIQh39 ei1KC9cphM+XeGYA7MsT/XD8Omim9N3R83msZnBAoo19tz3i6kX4xUTPb6wTTGG2lT5o Arpu6RSj0DOj6rwv35SP73erSg/mPO0aIWHYHO1EP2pZJgIf1JEBjOIGNd3kkhZ3otVe D8LA== X-Gm-Message-State: APjAAAXEc6oVHLwzNbXGKwXfki1wIK+ZtdUEDZVcHTqBKlJpznbckywE QR5zfAGaEp5juyQW+Uv8xSZzzDhTKjA= X-Google-Smtp-Source: APXvYqwwdN0t6YJZkt+82dxh4n2UojMRsqoLnEp3XQMKtVLZEuJURDc98DpQCtzq6wkNWU0nnDswHg== X-Received: by 2002:a17:90b:d85:: with SMTP id bg5mr6202738pjb.99.1575254496974; Sun, 01 Dec 2019 18:41:36 -0800 (PST) Received: from [192.168.1.11] (97-113-7-119.tukw.qwest.net. [97.113.7.119]) by smtp.gmail.com with ESMTPSA id u18sm16530275pgi.44.2019.12.01.18.41.35 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Sun, 01 Dec 2019 18:41:36 -0800 (PST) Subject: Re: [PATCH v2 11/14] target/arm: default SVE length to 64 bytes for linux-user To: =?UTF-8?Q?Alex_Benn=c3=a9e?= , qemu-devel@nongnu.org Cc: alan.hayward@arm.com, luis.machado@linaro.org, damien.hedde@greensocs.com, Peter Maydell , "open list:ARM TCG CPUs" References: <20191130084602.10818-1-alex.bennee@linaro.org> <20191130084602.10818-12-alex.bennee@linaro.org> From: Richard Henderson Message-ID: <9362663d-6452-39aa-2a8d-1cfd853d7faa@linaro.org> Date: Sun, 1 Dec 2019 18:41:34 -0800 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.2.1 MIME-Version: 1.0 In-Reply-To: <20191130084602.10818-12-alex.bennee@linaro.org> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 8bit X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::642 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 02 Dec 2019 02:41:41 -0000 On 11/30/19 8:45 AM, Alex Bennée wrote: > The Linux kernel chooses the default of 64 bytes for SVE registers on > the basis that it is the largest size that won't grow the signal > frame. When debugging larger sizes are also unwieldy in gdb as each > zreg will take over a page of terminal to display. > > The user can of course always specify a larger size with the > sve-max-vq property on the command line: > > -cpu max,sve-max-vq=16 > > This should not make any difference to SVE enabled software as the SVE > is of course vector length agnostic. > > Signed-off-by: Alex Bennée > --- > target/arm/cpu64.c | 3 +++ > 1 file changed, 3 insertions(+) 6 is the largest size that doesn't grow the signal frame. I imagine 4 was chosen because that's the only real hw atm. > + /* Default sve-max-vq to a reasonable numer */ > + cpu->sve_max_vq = 4; I also agree that we should match the kernel, but this is not the right way. Changing max vq is not the same as changing the default vq. You should change the value of env->vfp.zcr_el[1] in arm_cpu_reset(), and the user can increase the length with prctl(2) as they would be able to on real hardware that would have support for longer vector lengths. Also, I don't think you should mix this up with gdb stuff. r~ From MAILER-DAEMON Mon Dec 02 01:08:21 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1ibesf-0004Vw-HA for mharc-qemu-arm@gnu.org; Mon, 02 Dec 2019 01:08:21 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:58136) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ibesb-0004Vo-RQ for qemu-arm@nongnu.org; Mon, 02 Dec 2019 01:08:19 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ibesa-00016R-9l for qemu-arm@nongnu.org; Mon, 02 Dec 2019 01:08:17 -0500 Received: from ozlabs.org ([203.11.71.1]:53979) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1ibesZ-00016B-8u; Mon, 02 Dec 2019 01:08:16 -0500 Received: by ozlabs.org (Postfix, from userid 1007) id 47RF621gLzz9sPL; Mon, 2 Dec 2019 17:08:10 +1100 (AEDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gibson.dropbear.id.au; s=201602; t=1575266890; bh=USu8JlsY/OzHA2YhXxTPxDDMZBunzRsn+270mXy38Zo=; h=From:To:Cc:Subject:Date:From; b=bi3XDkPwIZaOws/HGq/oT54ob58swfTjE0sP4YauSYuvixDLssPVIE1tKsGEYBcMJ TcWo7VfXn6a1tbmIzSpeW44GVJQYIZBwLMVJhCGTzM4LoTpcrnMQExbq2XR7JCzJCt mcZ+GuU/2FAVchKJPlHlrdjXqvsBtUQzN/lAns/Q= From: David Gibson To: peter.maydell@linaro.org Cc: qemu-arm@nongnu.org, qemu-devel@nongnu.org, i.mitsyanko@gmail.com, richard.henderson@linaro.org, David Gibson , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCHv3] exynos4210_gic: Suppress gcc9 format-truncation warnings Date: Mon, 2 Dec 2019 17:08:06 +1100 Message-Id: <20191202060806.77968-1-david@gibson.dropbear.id.au> X-Mailer: git-send-email 2.23.0 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 203.11.71.1 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 02 Dec 2019 06:08:20 -0000 exynos4210_gic_realize() prints the number of cpus into some temporary buffers, but it only allows 3 bytes space for it. That's plenty: existing machines will only ever set this value to EXYNOS4210_NCPUS (2). But the compiler can't always figure that out, so some[*] gcc9 versions emit -Wformat-truncation warnings. We can fix that by hinting the constraint to the compiler with a suitably placed assert(). [*] The bizarre thing here, is that I've long gotten these warnings compiling in a 32-bit x86 container as host - Fedora 30 with gcc-9.2.1-1.fc30.i686 - but it compiles just fine on my normal x86_64 host - Fedora 30 with and gcc-9.2.1-1.fc30.x86_64. Signed-off-by: David Gibson Reviewed-by: Philippe Mathieu-Daud=C3=A9 Peter, up to you if you squeeze this in for qemu-4.2 or leave it until 5.= 0 Changes since v2: * Moved the assert outside the for loop using a trick suggested by Richard Henderson Changes since v1: * Used an assert to hint the compiler, instead of increasing the buffer size. --- hw/intc/exynos4210_gic.c | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/hw/intc/exynos4210_gic.c b/hw/intc/exynos4210_gic.c index a1b699b6ba..ddd006aca6 100644 --- a/hw/intc/exynos4210_gic.c +++ b/hw/intc/exynos4210_gic.c @@ -293,6 +293,7 @@ static void exynos4210_gic_realize(DeviceState *dev, = Error **errp) char cpu_alias_name[sizeof(cpu_prefix) + 3]; char dist_alias_name[sizeof(cpu_prefix) + 3]; SysBusDevice *gicbusdev; + uint32_t n =3D s->num_cpu; uint32_t i; =20 s->gic =3D qdev_create(NULL, "arm_gic"); @@ -313,7 +314,14 @@ static void exynos4210_gic_realize(DeviceState *dev,= Error **errp) memory_region_init(&s->dist_container, obj, "exynos4210-dist-contain= er", EXYNOS4210_EXT_GIC_DIST_REGION_SIZE); =20 - for (i =3D 0; i < s->num_cpu; i++) { + /* + * This clues in gcc that our on-stack buffers do, in fact have + * enough room for the cpu numbers. gcc 9.2.1 on 32-bit x86 + * doesn't figure this out, otherwise and gives spurious warnings. + */ + assert(n <=3D EXYNOS4210_NCPUS); + for (i =3D 0; i < n; i++) { + /* Map CPU interface per SMP Core */ sprintf(cpu_alias_name, "%s%x", cpu_prefix, i); memory_region_init_alias(&s->cpu_alias[i], obj, --=20 2.23.0 From MAILER-DAEMON Mon Dec 02 06:07:56 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1ibjYa-0006CT-Me for mharc-qemu-arm@gnu.org; Mon, 02 Dec 2019 06:07:56 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:39746) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ibjYY-00069q-AK for qemu-arm@nongnu.org; Mon, 02 Dec 2019 06:07:56 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ibjYW-00054A-Jb for qemu-arm@nongnu.org; Mon, 02 Dec 2019 06:07:53 -0500 Received: from beetle.greensocs.com ([5.135.226.135]:50072) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1ibjYW-00053H-0V; Mon, 02 Dec 2019 06:07:52 -0500 Received: from [172.16.11.102] (crumble.bar.greensocs.com [172.16.11.102]) by beetle.greensocs.com (Postfix) with ESMTPSA id 286D096EF0; Mon, 2 Dec 2019 11:07:44 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=greensocs.com; s=mail; t=1575284864; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=VgBiRzmN073Vt3AzJ9rm6Cx1Gcb36ZBoNwgbMrTiU+8=; b=IwMknjXkDLtrvdHaZyxhRACIvQFjk55icM9LvYUSHcazLx66RDyaVeAcjF4v3xGEsB3wgH LSdk0tdDVohQXzT4OKI8bLxxHtYVwnPv8o9oQUvp4ij5A9B0DTvAkzBmdXMcc6GcSadSNE H9EwwcdXqGAJKksmiE6+1sbogmSnL9c= Subject: Re: [PATCH v5 03/13] hw/core: create Resettable QOM interface To: Peter Maydell Cc: QEMU Developers , Edgar Iglesias , Mark Burton , Paolo Bonzini , "Daniel P. Berrange" , Eduardo Habkost , David Gibson , Cornelia Huck , =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= , qemu-arm , qemu-s390x References: <20191018150630.31099-1-damien.hedde@greensocs.com> <20191018150630.31099-4-damien.hedde@greensocs.com> From: Damien Hedde Message-ID: <20402bef-d615-3258-bde9-12d42c9b1029@greensocs.com> Date: Mon, 2 Dec 2019 12:07:43 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.2.0 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=utf-8 Content-Language: en-US-large Content-Transfer-Encoding: 7bit ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=greensocs.com; s=mail; t=1575284865; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=VgBiRzmN073Vt3AzJ9rm6Cx1Gcb36ZBoNwgbMrTiU+8=; b=EduGSw3JMDJG1Sn0lWOS4xD/qCTqnAe1EDmixxcw/wDW2HokGjApZ+oY50/E1hA+ovnJSp F6vxS/giWXu4cyDxhS9TSpxpUmGFhFzXBKnNGa1hRSzQ7YXSROnUQ6m/ev6OlHwIH4S7Lk N5IgVUYXwAhAmXoN8xql2dv0Hrty7BU= ARC-Seal: i=1; s=mail; d=greensocs.com; t=1575284865; a=rsa-sha256; cv=none; b=DK378j0q4oF3AN+WuCUGrN6wsxVONTwWkMYG0ySpG4lnjDJAp/jj/eTOSwaCKmPJSYqoYQ /tANyc0d2QZkQ4kpgZcOAvhFchWCuQS3D516Hg6bnt84htG6abXi5B2eJy3tyG2fZlxKoF OjDGnAVD5ZCezPXjZLjuldVhMsWb2Lg= ARC-Authentication-Results: i=1; ORIGINATING; auth=pass smtp.auth=damien smtp.mailfrom=damien.hedde@greensocs.com X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 5.135.226.135 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 02 Dec 2019 11:07:56 -0000 On 11/29/19 7:32 PM, Peter Maydell wrote: > On Fri, 18 Oct 2019 at 16:07, Damien Hedde wrote: >> >> This commit defines an interface allowing multi-phase reset. This aims >> to solve a problem of the actual single-phase reset (built in >> DeviceClass and BusClass): reset behavior is dependent on the order >> in which reset handlers are called. In particular doing external >> side-effect (like setting an qemu_irq) is problematic because receiving >> object may not be reset yet. >> >> The Resettable interface divides the reset in 3 well defined phases. >> To reset an object tree, all 1st phases are executed then all 2nd then >> all 3rd. See the comments in include/hw/resettable.h for a more complete >> description. The interface defines 3 phases to let the future >> possibility of holding an object into reset for some time. >> >> The qdev/qbus reset in DeviceClass and BusClass will be modified in >> following commits to use this interface. A mechanism is provided >> to allow executing a transitional reset handler in place of the 2nd >> phase which is executed in children-then-parent order inside a tree. >> This will allow to transition devices and buses smoothly while >> keeping the exact current qdev/qbus reset behavior for now. >> >> Documentation will be added in a following commit. >> >> Signed-off-by: Damien Hedde >> --- >> >> In this patch only a single reset type is supported, but the interface >> allows for more to be defined. >> >> I had some thought about problems which may arise when having multiple >> reset types: > > [snip] > > Yeah, these all seem right. We clearly need to think a bit > more before we add multiple reset types. Let's get this basic > just-cold-reset in for now and come back to the rest later. > > > Almost all of my comments below are just grammar/typo fixes > for comments. The only substantives are: > * globals > * copyright/licensing comment needed in the .h file > and they're pretty minor items. > >> +/** >> + * enter_phase_in_progress: >> + * Flag telling whether we are currently in an enter phase where side >> + * effects are forbidden. This flag allows us to catch if reset is called >> + * again during during this phase. >> + */ >> +static bool enter_phase_in_progress; > > This looks weird -- I don't think a global for this works, > because you might have several distinct subtrees of > devices, and be doing reset on them both at once. > I think that we only use this for an assert, though -- is > that right? If so, we could just drop this. We say that we need to own the iothread mutex for any reset, so global should be ok. Thought, I just checked, it's only mentioned in the documentation not in the header file. I should probably add a comment there too along with the link to the documentation file. If we want to drop the iothread mutex constraint. I think we need to carefully check there is no hidden problem. In particular in hold and exit phases we allow to have external effects like setting gpios and we have no way to control what it provokes. You're right it is just for assert: to avoid any miss-use of the api which could lead to being in bad reset state. So we can indeed drop it. > >> +void resettable_assert_reset(Object *obj, ResetType type) >> +{ >> + assert(!enter_phase_in_progress); >> + /* TODO: change that assert when adding support for other reset types */ > > I'm not sure which assert this is referring to -- the one above > the comment, or the one below ? It refers to the assert(type == RESET_TYPE_COLD). I added theses because we cannot just add items in the enum to have working multiple reset types. A comment like this will be more clear: /* * TODO: Additional reset types need support in phases handling * functions (resettable_phase_enter/hold/exit()) before allowing more * enum entries. Remove the following assert when it is done. */ > >> + assert(type == RESET_TYPE_COLD); >> + trace_resettable_reset_assert_begin(obj, type); >> + enter_phase_in_progress = true; >> + resettable_phase_enter(obj, NULL, type); >> + enter_phase_in_progress = false; >> + resettable_phase_hold(obj, NULL, type); >> + trace_resettable_reset_assert_end(obj); >> +} >> + >> +void resettable_release_reset(Object *obj, ResetType type) >> +{ >> + assert(!enter_phase_in_progress); >> + /* TODO: change that assert when adding support for other reset types */ > > Ditto. > > > >> --- /dev/null >> +++ b/include/hw/resettable.h >> @@ -0,0 +1,199 @@ >> +#ifndef HW_RESETTABLE_H >> +#define HW_RESETTABLE_H >> + > > All new files, including even small header files, should have > the usual copyright-and-license comment at the top. (Can you > check also whether this needs adding for any other new files the > patchset creates, please?) I'll do that and fix all the typos Thanks for the review, -- Damien From MAILER-DAEMON Mon Dec 02 06:15:10 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1ibjfY-0002Tt-1U for mharc-qemu-arm@gnu.org; Mon, 02 Dec 2019 06:15:08 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:40921) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ibjfP-0002NM-MA for qemu-arm@nongnu.org; Mon, 02 Dec 2019 06:15:04 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ibjfO-0008CI-G3 for qemu-arm@nongnu.org; Mon, 02 Dec 2019 06:14:59 -0500 Received: from mail-oi1-x241.google.com ([2607:f8b0:4864:20::241]:34561) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ibjfO-0008Bw-AM for qemu-arm@nongnu.org; Mon, 02 Dec 2019 06:14:58 -0500 Received: by mail-oi1-x241.google.com with SMTP id l136so16436297oig.1 for ; Mon, 02 Dec 2019 03:14:58 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=xN2DMI7ujIHJDmHjQcTmxMXXC1w59NzaLVTz8uCIN04=; b=xiV7tWWoibjcZDYkMIDqkXiXMYwQCKblJ/ZFe6EVovM5woD8kjN1WRON36vxeVnn8d BDRsPARpuFvIKD0QrSwyu/2/ARUmUpy69V10/vOn/5JXjwEclFeeUcTluSAPi+4mEaOB 1yLMMLFxp3Myfrwugb4PitEGGsqhEF/8cJpPaRLUp/PXNf8VUd0EAxSRf3qmHQuzJX2K /nH747q/4IPdw1rM/wWkSOVf23Ns60t+eKFxpkuBgS1BYDe4c8t6+wqr7/JkHDItXvTh /FDGseOA/NIAKOu64pMW+KHT9ygco/xPZT680GyAQBS7OjdllB5bFVy1urMAM7j6Doxz LHpQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=xN2DMI7ujIHJDmHjQcTmxMXXC1w59NzaLVTz8uCIN04=; b=UtCR1Xuqzw75dCbPgSmD/WwgMfu+Ny/uo0MrXhUTC8hqXZ9CZ7+0mcQLewR9PHVqxD KFPOAhTi2lQiLfohlDMeQwOdSPKCJJ5xWiljftr0w4pnPzJpDAGd4FnV3Y2kUgLMLnrc jMqXUElTHszqpM441xLir01Tu0iRAFApgnn5Zocl2IZFRst8zj9mQz7qHqwaOsD8EZDx 4PY1mHDbjlZQMxggjzG6BrvFNMFp0C6BMZPYnnd2J/GojzOe+G+Ch6klvAy6v+XDuaOI f2bdCU9EVTHwWPovf3XBEFSi66vbBNeZe2OKq5RLJBcKsMVj7jAkRsMu4BHZwk5q4PNC ZtEA== X-Gm-Message-State: APjAAAVks2UDGoewINtIGSDfWU2vDC1B8Vun9m6WrCc0e6voLg9A2e8+ d8juz6AVqoEw/hSAZyaVl7fEtVFIX1zDH8tANnIe2Q== X-Google-Smtp-Source: APXvYqwhdMvCsN7xbqAwL+fzv9rQtKSYdpsOk3oogHIaCpRpKhke0OVzeyJvgCyLrVkm/Dp4Reh7DAhro61e5TjTNPo= X-Received: by 2002:aca:f5cc:: with SMTP id t195mr20322028oih.163.1575285297444; Mon, 02 Dec 2019 03:14:57 -0800 (PST) MIME-Version: 1.0 References: <20191018150630.31099-1-damien.hedde@greensocs.com> <20191018150630.31099-4-damien.hedde@greensocs.com> <20402bef-d615-3258-bde9-12d42c9b1029@greensocs.com> In-Reply-To: <20402bef-d615-3258-bde9-12d42c9b1029@greensocs.com> From: Peter Maydell Date: Mon, 2 Dec 2019 11:14:46 +0000 Message-ID: Subject: Re: [PATCH v5 03/13] hw/core: create Resettable QOM interface To: Damien Hedde Cc: QEMU Developers , Edgar Iglesias , Mark Burton , Paolo Bonzini , "Daniel P. Berrange" , Eduardo Habkost , David Gibson , Cornelia Huck , =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= , qemu-arm , qemu-s390x Content-Type: text/plain; charset="UTF-8" X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::241 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 02 Dec 2019 11:15:04 -0000 On Mon, 2 Dec 2019 at 11:07, Damien Hedde wrote: > > > On 11/29/19 7:32 PM, Peter Maydell wrote: > > On Fri, 18 Oct 2019 at 16:07, Damien Hedde wrote: > >> +/** > >> + * enter_phase_in_progress: > >> + * Flag telling whether we are currently in an enter phase where side > >> + * effects are forbidden. This flag allows us to catch if reset is called > >> + * again during during this phase. > >> + */ > >> +static bool enter_phase_in_progress; > > > > This looks weird -- I don't think a global for this works, > > because you might have several distinct subtrees of > > devices, and be doing reset on them both at once. > > I think that we only use this for an assert, though -- is > > that right? If so, we could just drop this. > > We say that we need to own the iothread mutex for any reset, so global > should be ok. Thought, I just checked, it's only mentioned in the > documentation not in the header file. I should probably add a comment > there too along with the link to the documentation file. Ah, right, I hadn't considered that the mutex is effectively restricting to only a single reset happening at once. If you want to keep the asserts you can, if you add a comment noting that these globals are (a) only for asserts and (b) OK because we rely on the iothread mutex to ensure that only one reset operation can be in progress at once. thanks -- PMM From MAILER-DAEMON Mon Dec 02 06:38:32 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1ibk2C-0006Ka-N8 for mharc-qemu-arm@gnu.org; Mon, 02 Dec 2019 06:38:32 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:44577) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ibk29-0006KR-Dr for qemu-arm@nongnu.org; Mon, 02 Dec 2019 06:38:30 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ibk28-0004Ps-1l for qemu-arm@nongnu.org; Mon, 02 Dec 2019 06:38:29 -0500 Received: from beetle.greensocs.com ([5.135.226.135]:51086) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1ibk27-0004PE-FE; Mon, 02 Dec 2019 06:38:28 -0500 Received: from [172.16.11.102] (crumble.bar.greensocs.com [172.16.11.102]) by beetle.greensocs.com (Postfix) with ESMTPSA id 82F8696EF0; Mon, 2 Dec 2019 11:38:20 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=greensocs.com; s=mail; t=1575286701; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=kc4rOJaJAYsNyCWNjPbW9WW8Alz48HOG756F5zrMF0A=; b=3qnXKbgngrLys298wuE/JEhUm0wVSEaZ89fMLWV4Cb34aYF/4myeg4+4+XSagbqI3LafXk IhRQHAqQYfQfC3GP97klTyipM93omHoIP2Mq6fqQefl7XCghoBMbNGmrXnO7AmXlh6WwY8 qYu2RljaoW3ebaC1K2uAmgcxphur5uQ= Subject: Re: [PATCH v5 04/13] hw/core: add Resettable support to BusClass and DeviceClass To: Peter Maydell Cc: QEMU Developers , Edgar Iglesias , Mark Burton , Paolo Bonzini , "Daniel P. Berrange" , Eduardo Habkost , David Gibson , Cornelia Huck , =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= , qemu-arm , qemu-s390x References: <20191018150630.31099-1-damien.hedde@greensocs.com> <20191018150630.31099-5-damien.hedde@greensocs.com> From: Damien Hedde Message-ID: <0befd5d7-dde3-9a41-6c60-1bc372f7fd28@greensocs.com> Date: Mon, 2 Dec 2019 12:38:20 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.2.0 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=utf-8 Content-Language: en-US-large Content-Transfer-Encoding: 7bit ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=greensocs.com; s=mail; t=1575286701; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=kc4rOJaJAYsNyCWNjPbW9WW8Alz48HOG756F5zrMF0A=; b=Wi4oqgutqhzNbKcEtiG4+L4eiPJCFAsdD4tm4s9izLCm1Ju2q41Lv7sAOnTuh8Pm6Rfo2F JCNDiq6dDsKhlrgZteDGN3NWCfjUzRJPhTfJZ05H77uYoC4VoUpW1E7Zi+R4j3PmtkR36A UIpLYX8uNZvuektGCsFrIPCoPyUoYls= ARC-Seal: i=1; s=mail; d=greensocs.com; t=1575286701; a=rsa-sha256; cv=none; b=a5+O9S4I9dxfA+Rnf7LutTBtMjnLdCtsP1Uiv3LCOVrc80pTRx1i+NPR4ofgLPefyvngrv H65jPJ2pdBO/uL5Rqr6K2HqSzL/j0eA0rFbJzkGgtOgHQG+pxcqx0ji9M47acfIZPTPrTv Gs7YpitOBwpWbXPIM6JRKXWl/gpu2Uo= ARC-Authentication-Results: i=1; ORIGINATING; auth=pass smtp.auth=damien smtp.mailfrom=damien.hedde@greensocs.com X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 5.135.226.135 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 02 Dec 2019 11:38:30 -0000 On 11/29/19 7:36 PM, Peter Maydell wrote: > On Fri, 18 Oct 2019 at 16:07, Damien Hedde wrote: >> >> This commit adds support of Resettable interface to buses and devices: >> + ResettableState structure is added in the Bus/Device state >> + Resettable methods are implemented. >> + device/bus_is_in_reset function defined >> >> This commit allows to transition the objects to the new >> multi-phase interface without changing the reset behavior at all. >> Object single reset method can be split into the 3 different phases >> but the 3 phases are still executed in a row for a given object. >> From the qdev/qbus reset api point of view, nothing is changed. >> qdev_reset_all() and qbus_reset_all() are not modified as well as >> device_legacy_reset(). >> >> Transition of an object must be done from mother class to daughter >> classes. > > The standard terminology here is "parent class" and "child class". > > I notice you've used mother/daughter in a bunch of other comments > in various patches -- could you change that to the more usual > terms, please? Yes. Sorry for that. > >> Care has been taken to allow the transition of a mother class >> without requiring the daughter classes to be transitioned at the same >> time. Note that SysBus and SysBusDevice class do not need any transition >> because they do not override the legacy reset method. >> >> Signed-off-by: Damien Hedde > > Otherwise > Reviewed-by: Peter Maydell > > thanks > -- PMM > -- Damien From MAILER-DAEMON Mon Dec 02 06:43:52 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1ibk7M-0002Is-GF for mharc-qemu-arm@gnu.org; Mon, 02 Dec 2019 06:43:52 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:45255) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ibk7J-0002GE-Qm for qemu-arm@nongnu.org; Mon, 02 Dec 2019 06:43:50 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ibk7I-0008OL-ID for qemu-arm@nongnu.org; Mon, 02 Dec 2019 06:43:49 -0500 Received: from beetle.greensocs.com ([5.135.226.135]:51292) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1ibk7I-0008NT-6Z; Mon, 02 Dec 2019 06:43:48 -0500 Received: from [172.16.11.102] (crumble.bar.greensocs.com [172.16.11.102]) by beetle.greensocs.com (Postfix) with ESMTPSA id D5CAE96EF0; Mon, 2 Dec 2019 11:43:41 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=greensocs.com; s=mail; t=1575287022; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=hU90s+NFHEXRn3VjyWITYrFg1NmjzzO7O71eODyuVMw=; b=AORW9fsFHNcLSiYHSAhDg3ykTt5o54RrTE6pWtKyaypd3oq4V5oT5DIEl4vYjc2RuyZbZY XIgQbyII3NsrhXsE0qf8WqoXzatgs+vLjGJKRlXkAi37RzLoeuqNdW9KcI0tJF25CckRVT t8vO/x57xHA7nnpS/oVmcc3lk9cooyo= Subject: Re: [PATCH v5 05/13] hw/core/resettable: add support for changing parent To: Peter Maydell Cc: QEMU Developers , Edgar Iglesias , Mark Burton , Paolo Bonzini , "Daniel P. Berrange" , Eduardo Habkost , David Gibson , Cornelia Huck , =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= , qemu-arm , qemu-s390x References: <20191018150630.31099-1-damien.hedde@greensocs.com> <20191018150630.31099-6-damien.hedde@greensocs.com> From: Damien Hedde Message-ID: <02003f2e-38f5-2ff3-8160-e0bf6063839a@greensocs.com> Date: Mon, 2 Dec 2019 12:43:41 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.2.0 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=utf-8 Content-Language: en-US-large Content-Transfer-Encoding: 7bit ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=greensocs.com; s=mail; t=1575287022; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=hU90s+NFHEXRn3VjyWITYrFg1NmjzzO7O71eODyuVMw=; b=Did3pQhHLza7i5pYC+rI0Gx3bb7g9TeE+DDv4mBgTLcnCNsmEn5+f4uBWFml/P9HGpNiCT 12yMnL64LF0KDsVTOJX8loR3CrRjDwgERvarrnY97se+o+qsLf7OIJRjiI/xda8cjnlaUP VTWrQt1+zOJ7+WngsrqRI/f2Vs+5rMQ= ARC-Seal: i=1; s=mail; d=greensocs.com; t=1575287022; a=rsa-sha256; cv=none; b=P1O+eFriWFeGMbriDgzgaJYoTf0hrJebLLcJjOhGZZTXZOpMX7kE/qMCaMlilA5RXj4gXW Qq2hHaWUcIHFF4rskJ6U8Fywa5ISsYUgtxsrhLc/rFUK9RuIM/wJ3xWK61/rcseXlAXXLQ Cov7dmMkGJfdBcuw3pGWkja6jZgWEOA= ARC-Authentication-Results: i=1; ORIGINATING; auth=pass smtp.auth=damien smtp.mailfrom=damien.hedde@greensocs.com X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 5.135.226.135 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 02 Dec 2019 11:43:51 -0000 On 11/29/19 7:38 PM, Peter Maydell wrote: > On Fri, 18 Oct 2019 at 16:07, Damien Hedde wrote: >> >> Add a function resettable_change_parent() to do the required >> plumbing when changing the parent a of Resettable object. >> >> We need to make sure that the reset state of the object remains >> coherent with the reset state of the new parent. >> >> We make the 2 following hypothesis: >> + when an object is put in a parent under reset, the object goes in >> reset. >> + when an object is removed from a parent under reset, the object >> leaves reset. >> >> The added function avoid any glitch if both old and new parent are >> already in reset. >> >> Signed-off-by: Damien Hedde >> --- >> hw/core/resettable.c | 54 +++++++++++++++++++++++++++++++++++++++++ >> hw/core/trace-events | 1 + >> include/hw/resettable.h | 16 ++++++++++++ >> 3 files changed, 71 insertions(+) >> >> diff --git a/hw/core/resettable.c b/hw/core/resettable.c >> index c5e11cff4f..60d4285fcc 100644 >> --- a/hw/core/resettable.c >> +++ b/hw/core/resettable.c >> @@ -32,6 +32,14 @@ static void resettable_phase_exit(Object *obj, void *opaque, ResetType type); >> */ >> static bool enter_phase_in_progress; >> >> +/** >> + * exit_phase_in_progress: >> + * Flag telling whether we are currently in an enter phase where side >> + * effects are forbidden. This flag allows us to catch if >> + * resettable_change_parent() is called during exit phase. >> + */ >> +static unsigned exit_phase_in_progress; > > This is another global that I don't think we should have. > Is it also just for asserts ? Yes. It's only to ensure we don't miss-use the api. -- Damien From MAILER-DAEMON Mon Dec 02 07:27:56 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1ibko0-0007ux-KW for mharc-qemu-arm@gnu.org; Mon, 02 Dec 2019 07:27:56 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:50869) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ibknx-0007sJ-8s for qemu-arm@nongnu.org; Mon, 02 Dec 2019 07:27:54 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ibknv-0001d6-SI for qemu-arm@nongnu.org; Mon, 02 Dec 2019 07:27:53 -0500 Received: from beetle.greensocs.com ([5.135.226.135]:52694) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1ibknv-0001cY-3a; Mon, 02 Dec 2019 07:27:51 -0500 Received: from [172.16.11.102] (crumble.bar.greensocs.com [172.16.11.102]) by beetle.greensocs.com (Postfix) with ESMTPSA id 3FFF196EF0; Mon, 2 Dec 2019 12:27:48 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=greensocs.com; s=mail; t=1575289668; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=dDDYoSOz3CzxlxX4Sp0U/vxXCaY5fCXwnI4hQzM9KYU=; b=FSTxIeKUvVeZxjJ5/ygx6cl5i87zqK6gLpzTN8wlvDxos/zxlBxD6ULV5LGq+6AKVEtJn7 4Wuo/an7DmuPCY4HOh5fCPiWOXU+KZkn3nUVRmgLlTHlN7U20u9Prbr/B08tzLR0Cq053h Z5qCwooQyRkatyZmv3iyKJMWyDMkXBo= Subject: Re: [PATCH v5 12/13] hw/gpio/bcm2835_gpio: Isolate sdbus reparenting To: Peter Maydell Cc: QEMU Developers , Edgar Iglesias , Mark Burton , Paolo Bonzini , "Daniel P. Berrange" , Eduardo Habkost , David Gibson , Cornelia Huck , =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= , qemu-arm , qemu-s390x , Andrew Baumann References: <20191018150630.31099-1-damien.hedde@greensocs.com> <20191018150630.31099-13-damien.hedde@greensocs.com> From: Damien Hedde Message-ID: <1ae3a4d3-26e6-fe6d-87a3-d5dcce1fd64c@greensocs.com> Date: Mon, 2 Dec 2019 13:27:47 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.2.0 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=utf-8 Content-Language: en-US-large ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=greensocs.com; s=mail; t=1575289668; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=dDDYoSOz3CzxlxX4Sp0U/vxXCaY5fCXwnI4hQzM9KYU=; b=bv8wiRv35OOvul7zX10ifi6pX54HzRP2/qeZEwxXv5+qqf02NBr1akxUelVxRYmOnuOBV5 NkypAirKXHlXpcS6uEDVwPMPeN12vt3VQF2aWWuWvOdGsey+DSFRw8vI0pUPXBclQr/ToK hOkR9mrjEK+WXWtM/uQy+Flf62AsAK8= ARC-Seal: i=1; s=mail; d=greensocs.com; t=1575289668; a=rsa-sha256; cv=none; b=sO5qK3FYrp+SYEw5JfqKVyIKVxBHRwScXkfCv5zExvOB9ziTg0dI0og7Si8t5OB8U9scB1 6XR5gxc45NpNenr94O/YO6/emqblS8mN7ZrBcNWJ/gXAxR1hEzC6MFDeUrH53EaMLAZ2i0 bA1K9M3L66i0YKzFYRVZ7+mX7gYtY2I= ARC-Authentication-Results: i=1; ORIGINATING; auth=pass smtp.auth=damien smtp.mailfrom=damien.hedde@greensocs.com Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 5.135.226.135 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 02 Dec 2019 12:27:55 -0000 On 11/29/19 8:05 PM, Peter Maydell wrote: > On Fri, 18 Oct 2019 at 16:07, Damien Hedde = wrote: >> >> Split gpfsel_set() in 2 so that the sdbus reparenting is done >> in a dedicated function. >> >> Signed-off-by: Damien Hedde >> --- >> Cc: Peter Maydell >> Cc: Andrew Baumann >> Cc: Philippe Mathieu-Daud=C3=A9 >> Cc: qemu-arm@nongnu.org >> --- >> hw/gpio/bcm2835_gpio.c | 16 ++++++++++++---- >> 1 file changed, 12 insertions(+), 4 deletions(-) >> >> diff --git a/hw/gpio/bcm2835_gpio.c b/hw/gpio/bcm2835_gpio.c >> index 91ce3d10cc..81fe07132f 100644 >> --- a/hw/gpio/bcm2835_gpio.c >> +++ b/hw/gpio/bcm2835_gpio.c >> @@ -75,7 +75,10 @@ static void gpfsel_set(BCM2835GpioState *s, uint8_t= reg, uint32_t value) >> s->fsel[index] =3D fsel; >> } >> } >> +} >> >> +static void gpfsel_update_sdbus(BCM2835GpioState *s) >> +{ >> /* SD controller selection (48-53) */ >> if (s->sd_fsel !=3D 0 >> && (s->fsel[48] =3D=3D 0) /* SD_CLK_R */ >> @@ -86,6 +89,7 @@ static void gpfsel_set(BCM2835GpioState *s, uint8_t = reg, uint32_t value) >> && (s->fsel[53] =3D=3D 0) /* SD_DATA3_R */ >> ) { >> /* SDHCI controller selected */ >> + sdbus_reparent_card(&s->sdbus, s->sdbus_sdhci); >> sdbus_reparent_card(s->sdbus_sdhost, s->sdbus_sdhci); >> s->sd_fsel =3D 0;> } else if (s->sd_fsel !=3D 4 >> @@ -97,6 +101,7 @@ static void gpfsel_set(BCM2835GpioState *s, uint8_t= reg, uint32_t value) >> && (s->fsel[53] =3D=3D 4) /* SD_DATA3_R */ >> ) { >> /* SDHost controller selected */ >> + sdbus_reparent_card(&s->sdbus, s->sdbus_sdhost); >> sdbus_reparent_card(s->sdbus_sdhci, s->sdbus_sdhost); >=20 > The commit message says it's just splitting the function in two, > but these two hunks are adding extra calls to sdbus_reparent_card(). > Why do we need to call it twice ? You're right. I forgot to update the commit message. The patch also refactor a little the reset procedure and move the call to sdbus_reparent_card(&s->sdbus, s->sdbus_sdhci) which was in there to this part of the code. raspi machines create the sd in &s->sdbus. So there is need for a first reparenting from this bus. With this addition "gpfsel_update_sdbus" always do the expected effect of putting the sd card onto the right bus. sdbus_reparent_card(src,dst) only do something if the _src_ bus has a card. So only one of the 2 sdbus_reparent_card will have an effect. If the card is already onto the _dst_, both calls will be nop-op. What about rewording the commit message like this ? | hw/gpio/bcm2835_gpio: Refactor sdbus reparenting | | Split gpfsel_set() in 2 so that the sdbus reparenting is done in a | dedicated function gpfsel_update_sdbus() and update call sites. | Also make gpfsel_update_sdbus() handle the case where the sdcard is in | BCM2835GpioState.sdbus (initial sd card holding bus at machine | creation). | Refactor the reset procedure in consequence. | | This patch is a preparation step for the migration to multi-phases | reset which will be done in a following commit Thanks, -- Damien From MAILER-DAEMON Mon Dec 02 07:33:29 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1ibktN-0002Ex-HP for mharc-qemu-arm@gnu.org; Mon, 02 Dec 2019 07:33:29 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:51733) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ibktG-00025l-TR for qemu-arm@nongnu.org; Mon, 02 Dec 2019 07:33:27 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ibktF-0003bq-Hb for qemu-arm@nongnu.org; Mon, 02 Dec 2019 07:33:22 -0500 Received: from mail-ot1-x343.google.com ([2607:f8b0:4864:20::343]:45354) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ibktF-0003bL-B7 for qemu-arm@nongnu.org; Mon, 02 Dec 2019 07:33:21 -0500 Received: by mail-ot1-x343.google.com with SMTP id 59so92644otp.12 for ; Mon, 02 Dec 2019 04:33:21 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=w3QJs8joDrXvkLAs2T6oYNfyRbXCuGP1b67uc8VXb3g=; b=bmUTo7y+WXT3jeoZnZzhuDLmZGLKL5qvE7VeN9OUKBdZzN5t16bkgVgCtPaP0pmnBJ SoOEWn1YKZkRvpRydhy8N/zJGwII3CzOoN8cw2zL5efw2bSfpRi0BuaMqmdi9tK5MIK/ sfH8CIVTePqAUKgr0npKbPgVPh+qx34xHd7yIvoVm899+7L8wgzgl9Ok4sY4a2dtKFBs ILrD5mT30mCzLGGhaXDZjL00Fo8NBkwNnFveWyLua1ZIsHRSDK/bOj+uSz83qLSSaDT+ HVNdj4BvE2Kv6DajnaZ/11yqbADmpY1+ItJABt2SIN8EmTgp4HsgV2/lflwobaQjhJ0j x6yA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=w3QJs8joDrXvkLAs2T6oYNfyRbXCuGP1b67uc8VXb3g=; b=CbITEfgDHGmq1sXz3k6g7ZfZe91Nys0lPt8k8GCYcRpf7h296AAT/0lhuf2ZGrjsTE m/Fa1vLaGBejvawBW2sK9PtntFFiYgnkVSxMjv6IYlBTBJb6dqZzQjZos00u8uoPP0sN /wJJY9QXhfZ3lILEJKcDRzED4g2nrY3W3VMDJTouecIemDTcAd5ks88xpWElrrf4PD32 ryp9NSpkBsruNgzhz+JjDocFtccLpZu3FvNICx3jPhlC9M8X4c1kn2G5j32Q2I01yxRP kV5UIQB7T98/XlxRJYU2HiU3LIiruI7qWSzHbCZJSE6YyK6AI2M9isfV0azg9HbK4gSt 6Kjg== X-Gm-Message-State: APjAAAXxkJQfM6C2+ei060u4WXdZsxPAvLixGR2ztwKkeKHnYLwo5v20 JjulhcCU76qc+aZRt+pixUkREfIbP/RVZTFlFv4EZA== X-Google-Smtp-Source: APXvYqxy0bMHLvZ1VrTEwtwKIyzCUsG2Pbx1oTlFbb93vFIB5dNEW4NDiuWD64dctB4s/w7gTB9CftR48JMoJksodKE= X-Received: by 2002:a05:6830:2001:: with SMTP id e1mr2540872otp.97.1575290000501; Mon, 02 Dec 2019 04:33:20 -0800 (PST) MIME-Version: 1.0 References: <20191018150630.31099-1-damien.hedde@greensocs.com> <20191018150630.31099-13-damien.hedde@greensocs.com> <1ae3a4d3-26e6-fe6d-87a3-d5dcce1fd64c@greensocs.com> In-Reply-To: <1ae3a4d3-26e6-fe6d-87a3-d5dcce1fd64c@greensocs.com> From: Peter Maydell Date: Mon, 2 Dec 2019 12:33:09 +0000 Message-ID: Subject: Re: [PATCH v5 12/13] hw/gpio/bcm2835_gpio: Isolate sdbus reparenting To: Damien Hedde Cc: QEMU Developers , Edgar Iglesias , Mark Burton , Paolo Bonzini , "Daniel P. Berrange" , Eduardo Habkost , David Gibson , Cornelia Huck , =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= , qemu-arm , qemu-s390x , Andrew Baumann Content-Type: text/plain; charset="UTF-8" X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::343 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 02 Dec 2019 12:33:28 -0000 On Mon, 2 Dec 2019 at 12:27, Damien Hedde wrote: > > > > On 11/29/19 8:05 PM, Peter Maydell wrote: > > On Fri, 18 Oct 2019 at 16:07, Damien Hedde wrote: > >> @@ -97,6 +101,7 @@ static void gpfsel_set(BCM2835GpioState *s, uint8_t reg, uint32_t value) > >> && (s->fsel[53] == 4) /* SD_DATA3_R */ > >> ) { > >> /* SDHost controller selected */ > >> + sdbus_reparent_card(&s->sdbus, s->sdbus_sdhost); > >> sdbus_reparent_card(s->sdbus_sdhci, s->sdbus_sdhost); > > > > The commit message says it's just splitting the function in two, > > but these two hunks are adding extra calls to sdbus_reparent_card(). > > Why do we need to call it twice ? > > You're right. I forgot to update the commit message. The patch also > refactor a little the reset procedure and move the call to > sdbus_reparent_card(&s->sdbus, s->sdbus_sdhci) > which was in there to this part of the code. > > raspi machines create the sd in &s->sdbus. So there is need for a first > reparenting from this bus. > > With this addition "gpfsel_update_sdbus" always do the expected effect > of putting the sd card onto the right bus. > > sdbus_reparent_card(src,dst) only do something if the _src_ bus has a > card. So only one of the 2 sdbus_reparent_card will have an effect. If > the card is already onto the _dst_, both calls will be nop-op The intention of sdbus_reparent_card() is that it moves something from the 'src' bus to the 'dst' bus. So one call is supposed to do the whole job of the move. If it doesn't, then that's a bug. I thought the raspi machines had an sd card that could either be connected to one of the controllers, or the other. Why would the sd card ever be somewhere else than on one of those two buses? If the machine creation puts the sdcard somewhere wrong then we should probably just fix that. thanks -- PMM From MAILER-DAEMON Mon Dec 02 08:05:09 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1iblO0-00088R-Uc for mharc-qemu-arm@gnu.org; Mon, 02 Dec 2019 08:05:08 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:55607) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iblNy-00088J-Dr for qemu-arm@nongnu.org; Mon, 02 Dec 2019 08:05:07 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1iblNw-0002BX-Vp for qemu-arm@nongnu.org; Mon, 02 Dec 2019 08:05:06 -0500 Received: from beetle.greensocs.com ([5.135.226.135]:53804) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1iblNw-0002B4-DE; Mon, 02 Dec 2019 08:05:04 -0500 Received: from [172.16.11.102] (crumble.bar.greensocs.com [172.16.11.102]) by beetle.greensocs.com (Postfix) with ESMTPSA id 9D34D96EF2; Mon, 2 Dec 2019 13:05:01 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=greensocs.com; s=mail; t=1575291902; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=59jHss8An0NYZMESND1tXJ7A23ua1uMaUfpnpEIm3Lc=; b=2U/sAm8R++nNlTJEguc4NZCONBgfkiDK6JAsfwSupYjapVY1h/tEPVFCFkOrVe8ZTS5srj ohXsJoG1MDz/AHUzwebMb6sp7LRU4HMEIce4ZOy+ef5b8Pf0qaNSiQ69aCJcgsbP+1Mc5u E4V7BjXdxzj31vV2k+sUKjMcLJ/ttXk= Subject: Re: [PATCH v5 12/13] hw/gpio/bcm2835_gpio: Isolate sdbus reparenting To: Peter Maydell Cc: QEMU Developers , Edgar Iglesias , Mark Burton , Paolo Bonzini , "Daniel P. Berrange" , Eduardo Habkost , David Gibson , Cornelia Huck , =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= , qemu-arm , qemu-s390x , Andrew Baumann References: <20191018150630.31099-1-damien.hedde@greensocs.com> <20191018150630.31099-13-damien.hedde@greensocs.com> <1ae3a4d3-26e6-fe6d-87a3-d5dcce1fd64c@greensocs.com> From: Damien Hedde Message-ID: <8bd421d9-d0a9-853d-1ab2-09467df64e05@greensocs.com> Date: Mon, 2 Dec 2019 14:05:01 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.2.0 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=utf-8 Content-Language: en-US-large Content-Transfer-Encoding: 7bit ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=greensocs.com; s=mail; t=1575291902; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=59jHss8An0NYZMESND1tXJ7A23ua1uMaUfpnpEIm3Lc=; b=yg/C5QnGwUNCtTZ+3miMKD56lDWZdT4Sa+ZbMfcvm/Bwcci0xDSa5c0OsRY2X+4eFyZ0Dy HD/rY473Bl0Dpqs1KacjHuS6qCbtVcSiudXP7LwuAYFqDNR65ETyTGoPxM0+a0j5wjxSzL sNW1G12qUsaJbgqlbK1XGitwoQ6LmpQ= ARC-Seal: i=1; s=mail; d=greensocs.com; t=1575291902; a=rsa-sha256; cv=none; b=kbN66ivQO5obHOCsPHk/7oA9GN/c85XcrufnEaunsnOzC9dwiGvlV7bWMRYxoSvBZ8baLO ZiezTVC2ywOCnKXSF7lWvbzMD2jPSrX+IjVU9DkFn9mPe7J2vm29WwojHTZ1J/O82mHnQN 6rURIxNVnK03oioRFjmDTN1lqXu9MtU= ARC-Authentication-Results: i=1; ORIGINATING; auth=pass smtp.auth=damien smtp.mailfrom=damien.hedde@greensocs.com X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 5.135.226.135 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 02 Dec 2019 13:05:08 -0000 On 12/2/19 1:33 PM, Peter Maydell wrote: > On Mon, 2 Dec 2019 at 12:27, Damien Hedde wrote: >> >> >> >> On 11/29/19 8:05 PM, Peter Maydell wrote: >>> On Fri, 18 Oct 2019 at 16:07, Damien Hedde wrote: >>>> @@ -97,6 +101,7 @@ static void gpfsel_set(BCM2835GpioState *s, uint8_t reg, uint32_t value) >>>> && (s->fsel[53] == 4) /* SD_DATA3_R */ >>>> ) { >>>> /* SDHost controller selected */ >>>> + sdbus_reparent_card(&s->sdbus, s->sdbus_sdhost); >>>> sdbus_reparent_card(s->sdbus_sdhci, s->sdbus_sdhost); >>> >>> The commit message says it's just splitting the function in two, >>> but these two hunks are adding extra calls to sdbus_reparent_card(). >>> Why do we need to call it twice ? >> >> You're right. I forgot to update the commit message. The patch also >> refactor a little the reset procedure and move the call to >> sdbus_reparent_card(&s->sdbus, s->sdbus_sdhci) >> which was in there to this part of the code. >> >> raspi machines create the sd in &s->sdbus. So there is need for a first >> reparenting from this bus. >> >> With this addition "gpfsel_update_sdbus" always do the expected effect >> of putting the sd card onto the right bus. >> >> sdbus_reparent_card(src,dst) only do something if the _src_ bus has a >> card. So only one of the 2 sdbus_reparent_card will have an effect. If >> the card is already onto the _dst_, both calls will be nop-op > > The intention of sdbus_reparent_card() is that it moves > something from the 'src' bus to the 'dst' bus. So one > call is supposed to do the whole job of the move. If > it doesn't, then that's a bug. > > I thought the raspi machines had an sd card that could > either be connected to one of the controllers, or the > other. Why would the sd card ever be somewhere else > than on one of those two buses? If the machine creation > puts the sdcard somewhere wrong then we should probably > just fix that. > I don't know why it has been implemented like this but right now the raspi_init() does the following during machine creation: | bus = qdev_get_child_bus(DEVICE(&s->soc), "sd-bus"); | [...] | carddev = qdev_create(bus, TYPE_SD_CARD); which put the sd in the BCM2835GpioState.sdbus . Then the reset procedure of the BCM2835Gpio move the sd card to one of the two usable controllers and the sd card can never go back to the initial BCM2835GpioState.sdbus. As far as I understand, it is theorically possible to have the sd card on no controller at all (it's maybe the reason for the .sdbus "useless" bus) (for example if the BCM2835Gpio is badly configured) but this is not implemented in qemu. Anyway I can add some plumbing to only call sdbus_reparent_card() when really needed by: + not duplicating the sdbus_reparent_card() in gpfsel_update_sdbus() + adding needed test in reset() method to only do the initial sdbus_reparent_card() if needed (first time we call reset). -- Damien From MAILER-DAEMON Mon Dec 02 08:10:54 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1iblTa-0003JL-9p for mharc-qemu-arm@gnu.org; Mon, 02 Dec 2019 08:10:54 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:56431) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iblTU-0003EX-9P for qemu-arm@nongnu.org; Mon, 02 Dec 2019 08:10:53 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1iblTS-0004P7-UL for qemu-arm@nongnu.org; Mon, 02 Dec 2019 08:10:48 -0500 Received: from mail-ot1-x343.google.com ([2607:f8b0:4864:20::343]:44439) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1iblTS-0004Og-NS for qemu-arm@nongnu.org; Mon, 02 Dec 2019 08:10:46 -0500 Received: by mail-ot1-x343.google.com with SMTP id x3so6439425oto.11 for ; Mon, 02 Dec 2019 05:10:46 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=dtmk+AViR5zUt+ZAvHOkNZ2Mi79saamn3iW5l1Vzgto=; b=SUClcpAMdEJS8EdmXJRr1EU6yjG7j/JR/pHHYbaOAhpsKtV4LLuLUpeWGc1F4hucaO GcAdMWZ9MPMH/gZZltSS/fLABCEzeHJxsZAsR8pLsVVoyNG8N9az09Q7IGlSdW22TWTv yc7BJQcIUsKUyTnUipzAV4X8g6+wMN7ARf3b1wkC+JBD8DEwEEjwuPWbWLxiQDJhF3Ip lQzkBPcksBnZfoZtlIHh9RlJJ1AIRssOfcSiKDxc2nFXPoVt8VI40iQasqhpJgnUutpt TSPHTyVWOLTpKtHEzTxhI6lhzwpMnvzzJOFNL/EynHqkBQMvrWxWjT878Beb5rmCgM8x J8wg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=dtmk+AViR5zUt+ZAvHOkNZ2Mi79saamn3iW5l1Vzgto=; b=BqvYqNA1Kn2mOfMpVr1PtlRZ3CC8ie58d0BBjagPNhhz4grFPfLS8ANS4bJ7Wk4hZ/ T+hVOJ5DBy3EFCT3XAi+gG1Y1ByQrxwWsvn8h7G9hIZ6vtb2tyUYgPIuOOPqliJjssYr /l9UitbVfxMBq2EuiThSxi6ToxXBK2XrFcDhxzm8tIIe2YWihRY4sBmhg/WJCJkwH4BM mJclOeK9hgAGMT43dlaID5jDLZ7heOrlU8cCLNxHLlIv736c1j5V+nVkzubuC8VFuRRg qtVcXEaw+MoefYxhU1r9xFuB7H0f/fx/Q8sEtNG5wknMGWsmIMWrrttDkvXTCxt4B0v9 obzA== X-Gm-Message-State: APjAAAXH075i3gL41lVSiXXdtiIZOfJ7OlTW/j9QLwU1vfURL9TSvmwx 2JMU6irXcakk5M4cqs2KyoTUgdHEO4z/ewMslvapWg== X-Google-Smtp-Source: APXvYqzmcoOLw0QYt3zqBJ/c7wxqjCCiZeY/bv2r/fQGQeZJ1cLoFaqCenZ6zo7uszy04pOfnKT5lHLO5s440zg45to= X-Received: by 2002:a05:6830:13d3:: with SMTP id e19mr2063572otq.135.1575292245725; Mon, 02 Dec 2019 05:10:45 -0800 (PST) MIME-Version: 1.0 References: <20191018150630.31099-1-damien.hedde@greensocs.com> <20191018150630.31099-13-damien.hedde@greensocs.com> <1ae3a4d3-26e6-fe6d-87a3-d5dcce1fd64c@greensocs.com> <8bd421d9-d0a9-853d-1ab2-09467df64e05@greensocs.com> In-Reply-To: <8bd421d9-d0a9-853d-1ab2-09467df64e05@greensocs.com> From: Peter Maydell Date: Mon, 2 Dec 2019 13:10:34 +0000 Message-ID: Subject: Re: [PATCH v5 12/13] hw/gpio/bcm2835_gpio: Isolate sdbus reparenting To: Damien Hedde Cc: QEMU Developers , Edgar Iglesias , Mark Burton , Paolo Bonzini , "Daniel P. Berrange" , Eduardo Habkost , David Gibson , Cornelia Huck , =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= , qemu-arm , qemu-s390x , Andrew Baumann Content-Type: text/plain; charset="UTF-8" X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::343 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 02 Dec 2019 13:10:53 -0000 On Mon, 2 Dec 2019 at 13:05, Damien Hedde wrote: > > I don't know why it has been implemented like this but right now the > raspi_init() does the following during machine creation: > | bus = qdev_get_child_bus(DEVICE(&s->soc), "sd-bus"); > | [...] > | carddev = qdev_create(bus, TYPE_SD_CARD); > which put the sd in the BCM2835GpioState.sdbus . > > Then the reset procedure of the BCM2835Gpio move the sd card > to one of the two usable controllers and the sd card can never go back > to the initial BCM2835GpioState.sdbus. This seems like it's just an oversight. The code in raspi_init() which creates the SD card was added in 2016, a year before the gpio device was added, so when it was written there was only ever one place the SD card could be, I think. We should fix it so it puts the card in the right place to start with. > As far as I understand, it is theorically possible to have the sd card > on no controller at all (it's maybe the reason for the .sdbus "useless" > bus) (for example if the BCM2835Gpio is badly configured) but this is > not implemented in qemu. > > Anyway I can add some plumbing to only call sdbus_reparent_card() when > really needed by: > + not duplicating the sdbus_reparent_card() in gpfsel_update_sdbus() > + adding needed test in reset() method to only do the initial > sdbus_reparent_card() if needed (first time we call reset). I don't think you need the latter if we make the machine model put the card in the right place to start with. thanks -- PMM From MAILER-DAEMON Mon Dec 02 08:36:29 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1iblsK-0003oD-VD for mharc-qemu-arm@gnu.org; Mon, 02 Dec 2019 08:36:28 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:59278) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ibiai-0007Ch-Bi for qemu-arm@nongnu.org; Mon, 02 Dec 2019 05:06:09 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ibiag-0003EX-Va for qemu-arm@nongnu.org; Mon, 02 Dec 2019 05:06:04 -0500 Received: from mail-eopbgr60083.outbound.protection.outlook.com ([40.107.6.83]:16118 helo=EUR04-DB3-obe.outbound.protection.outlook.com) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1ibiac-0003CP-JF; Mon, 02 Dec 2019 05:05:58 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; 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Mon, 2 Dec 2019 10:05:44 +0000 From: Alan Hayward To: =?utf-8?B?QWxleCBCZW5uw6ll?= CC: "qemu-devel@nongnu.org" , "damien.hedde@greensocs.com" , Peter Maydell , Luis Machado , "richard.henderson@linaro.org" , "open list:ARM TCG CPUs" , =?utf-8?B?UGhpbGlwcGUgTWF0aGlldS1EYXVkw6k=?= , nd Subject: Re: [PATCH v2 06/14] target/arm: use gdb_get_reg helpers Thread-Topic: [PATCH v2 06/14] target/arm: use gdb_get_reg helpers Thread-Index: AQHVqIKv65Q7cbxEuk+QAo74emkk/6emnxkA Date: Mon, 2 Dec 2019 10:05:44 +0000 Message-ID: <42017B4E-E961-494C-A505-FCDA74EFB265@arm.com> References: <20191130084602.10818-1-alex.bennee@linaro.org> <20191130084602.10818-7-alex.bennee@linaro.org> <987465d3-3b13-e675-9622-c13e2d5205c2@redhat.com> In-Reply-To: <987465d3-3b13-e675-9622-c13e2d5205c2@redhat.com> Accept-Language: en-GB, en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-mailer: Apple Mail (2.3601.0.10) Authentication-Results-Original: spf=none (sender IP is ) smtp.mailfrom=Alan.Hayward@arm.com; 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Mon, 02 Dec 2019 08:42:58 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:59996) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iblyZ-0005xV-V1 for qemu-arm@nongnu.org; Mon, 02 Dec 2019 08:42:57 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1iblyY-0001D4-8Q for qemu-arm@nongnu.org; Mon, 02 Dec 2019 08:42:55 -0500 Received: from mail-oi1-x244.google.com ([2607:f8b0:4864:20::244]:33640) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1iblyY-0001CT-17 for qemu-arm@nongnu.org; Mon, 02 Dec 2019 08:42:54 -0500 Received: by mail-oi1-x244.google.com with SMTP id x21so25336019oic.0 for ; Mon, 02 Dec 2019 05:42:53 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc:content-transfer-encoding; bh=VZX6lBHSz0FQNHjiAsYon2lwI6dwOqr/6nqKVc9ThqE=; b=Yba2toiYPk6rL0kRll0oHDiISouSWrtXErfJ7yVUciQ6NEArLMRlsKfRm1zgbZHycC dMlT+aUrvs68rXktUUmysGFUyRBKp/BNB3Vv7UOnwwc0L9IqTglNY82e1Ib9TuBEdP7J +7I5pEHNdxIL/fAlBsn0KSIPFLPSy8cs4vGv4DaFMbvFtvpRStB9ff9wwBe3pQLE23S1 qdV6yRbbMqN3wM9gv5fLa4K7nXpfUA60Mn6vA3NJg37qpZHO5q/BFsrLWKfDmOc2SGPQ 5bEHvHVm5td898ZQxxJQ41QYR9TdudC0Fr/D45lGrTdjSLBlBqpJB4DRyOXnnCp2n3Wq GB2A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc:content-transfer-encoding; bh=VZX6lBHSz0FQNHjiAsYon2lwI6dwOqr/6nqKVc9ThqE=; b=YNV8l/p9kdcFRIUp4608Ehn9UrEyfXLTHp+Nkfqb/4I24iM3qT5BjOE4QRaFgVxBdz AImje5mWsA0kDrooaHVOxHr6CrzuYc0t9hW00Aj7IXkpqYDlHep+UOTCnY1unCAFj2C7 8d1plt1+knhRYwGJN3G7HUFZ6ttWYAvPoEYqMywVcB1dn3qPOyOM/6diaA70hwIAfacP bXegekyrbXZ8VoFJAy6sRdOHkllbjDcyE6srT8EcNb0h5gdry4ZnbTj6YiQsTu6JyM5p y9puKYAg/JrZrvGvTpDb5rMCq7Pi1Cr+Y9fUl9A3WgUfzOlq73ePICuKLanI78H3XSnU DPzQ== X-Gm-Message-State: APjAAAVErveNmWdb44yWIvb9b3a6lbTVkBbX/YBKuyrT3vs0vc1DiE/v zNKh9ofYjoINYSSy5eA5DdF9shAXtjJYI6GsZ5yoVA== X-Google-Smtp-Source: APXvYqxgi7SIi4bUEgJdtAl4rpjWd+RBE3NW34UdDA6aCgrvYTyGLo7iA7lKp1GJC1KWQMxUb5mg6+UoGFG8E+doumo= X-Received: by 2002:aca:3182:: with SMTP id x124mr13381262oix.170.1575294172927; Mon, 02 Dec 2019 05:42:52 -0800 (PST) MIME-Version: 1.0 References: <20190904125531.27545-1-damien.hedde@greensocs.com> <20190904125531.27545-2-damien.hedde@greensocs.com> In-Reply-To: <20190904125531.27545-2-damien.hedde@greensocs.com> From: Peter Maydell Date: Mon, 2 Dec 2019 13:42:41 +0000 Message-ID: Subject: Re: [PATCH v6 1/9] hw/core/clock: introduce clock objects To: Damien Hedde Cc: QEMU Developers , Mark Burton , "Edgar E. Iglesias" , Alistair Francis , =?UTF-8?B?TWFyYy1BbmRyw6kgTHVyZWF1?= , Paolo Bonzini , "Daniel P. Berrange" , Eduardo Habkost , qemu-arm , =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::244 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 02 Dec 2019 13:42:57 -0000 On Wed, 4 Sep 2019 at 13:56, Damien Hedde wrot= e: > > Introduce clock objects: ClockIn and ClockOut. > > These objects may be used to distribute clocks from an object to several > other objects. Each ClockIn object contains the current state of the > clock: the frequency; it allows an object to migrate its input clock stat= e > independently of other objects. > > A ClockIn may be connected to a ClockOut so that it receives update, "updates" (or "an update") > through a callback, whenever the Clockout is updated using the > ClockOut's set function. > > This is based on the original work of Frederic Konrad. > > Signed-off-by: Damien Hedde > Reviewed-by: Philippe Mathieu-Daud=C3=A9 > Tested-by: Philippe Mathieu-Daud=C3=A9 > --- > Makefile.objs | 1 + > hw/core/Makefile.objs | 1 + > hw/core/clock.c | 144 ++++++++++++++++++++++++++++++++++++++++++ > hw/core/trace-events | 6 ++ > include/hw/clock.h | 124 ++++++++++++++++++++++++++++++++++++ > 5 files changed, 276 insertions(+) > create mode 100644 hw/core/clock.c > create mode 100644 include/hw/clock.h > > diff --git a/Makefile.objs b/Makefile.objs > index a723a47e14..4da623c759 100644 > --- a/Makefile.objs > +++ b/Makefile.objs > @@ -153,6 +153,7 @@ trace-events-subdirs +=3D hw/audio > trace-events-subdirs +=3D hw/block > trace-events-subdirs +=3D hw/block/dataplane > trace-events-subdirs +=3D hw/char > +trace-events-subdirs +=3D hw/core > trace-events-subdirs +=3D hw/dma > trace-events-subdirs +=3D hw/hppa > trace-events-subdirs +=3D hw/i2c > diff --git a/hw/core/Makefile.objs b/hw/core/Makefile.objs > index 69b408ad1c..c66a5b2c6b 100644 > --- a/hw/core/Makefile.objs > +++ b/hw/core/Makefile.objs > @@ -7,6 +7,7 @@ common-obj-$(CONFIG_SOFTMMU) +=3D fw-path-provider.o > # irq.o needed for qdev GPIO handling: > common-obj-y +=3D irq.o > common-obj-y +=3D hotplug.o > +common-obj-y +=3D clock.o > common-obj-$(CONFIG_SOFTMMU) +=3D nmi.o > common-obj-$(CONFIG_SOFTMMU) +=3D vm-change-state-handler.o > > diff --git a/hw/core/clock.c b/hw/core/clock.c > new file mode 100644 > index 0000000000..888f247f2a > --- /dev/null > +++ b/hw/core/clock.c > @@ -0,0 +1,144 @@ > +/* > + * Clock inputs and outputs > + * > + * Copyright GreenSocs 2016-2018 > + * > + * Authors: > + * Frederic Konrad > + * Damien Hedde > + * > + * This work is licensed under the terms of the GNU GPL, version 2 or la= ter. > + * See the COPYING file in the top-level directory. > + */ > + > +#include "qemu/osdep.h" > +#include "hw/clock.h" > +#include "trace.h" > + > +#define CLOCK_PATH(_clk) (_clk->canonical_path) Don't use leading underscores in identifiers, please. > + > +void clock_out_setup_canonical_path(ClockOut *clk) > +{ > + g_free(clk->canonical_path); > + clk->canonical_path =3D object_get_canonical_path(OBJECT(clk)); > +} > + > +void clock_in_setup_canonical_path(ClockIn *clk) > +{ > + g_free(clk->canonical_path); > + clk->canonical_path =3D object_get_canonical_path(OBJECT(clk)); > +} > + > +void clock_set_callback(ClockIn *clk, ClockCallback *cb, void *opaque) > +{ > + assert(clk); > + > + clk->callback =3D cb; > + clk->callback_opaque =3D opaque; > +} > + > +void clock_init_frequency(ClockIn *clk, uint64_t freq) > +{ > + assert(clk); This sort of assert isn't necessary. Asserts are good when they help to make a bug visible sooner and more obviously -- when they avoid "something goes wrong much later on and further from the site of the actual error". In this case, if the assert was not present then the code would just segfault on the next line: > + > + clk->frequency =3D freq; which is already a very easy bug to diagnose and where the offending caller will be in the backtrace. If the parameter isn't supposed to be NULL, and the method doesn't actually do anything that would dereference it, that might be a good candidate to assert on. The same kind of unnecessary assert is also in some of the other functions here (and probably in other patches). > diff --git a/hw/core/trace-events b/hw/core/trace-events > index ecf966c314..aa940e268b 100644 > --- a/hw/core/trace-events > +++ b/hw/core/trace-events > @@ -34,3 +34,9 @@ resettable_phase_hold_end(void *obj, int needed) "obj= =3D%p needed=3D%d" > resettable_phase_exit(void *obj, const char *type) "obj=3D%p(%s)" > resettable_phase_exit_end(void *obj, uint32_t count) "obj=3D%p count=3D%= " PRIu32 > resettable_count_underflow(void *obj) "obj=3D%p" > + > +# hw/core/clock-port.c > +clock_connect(const char *clk, const char *driver) "'%s' drived-by '%s'" "driven-by" > +clock_disconnect(const char *clk) "'%s'" > +clock_set_frequency(const char *clk, uint64_t freq) "'%s' freq_hz=3D%" P= RIu64 > +clock_propagate(const char *clko, const char *clki) "'%s' =3D> '%s'" > diff --git a/include/hw/clock.h b/include/hw/clock.h > new file mode 100644 > index 0000000000..fd11202ba4 > --- /dev/null > +++ b/include/hw/clock.h > @@ -0,0 +1,124 @@ > +#ifndef QEMU_HW_CLOCK_H > +#define QEMU_HW_CLOCK_H All new files need a copyright-and-license comment header (could you check the rest of the patchset for this, please?). > + > +/** > + * clock_get_frequency: > + * @clk: the clk to fetch the clock > + * > + * @return: the current frequency of @clk in Hz. If @clk is NULL, return= 0. > + */ > +static inline uint64_t clock_get_frequency(const ClockIn *clk) > +{ > + return clk ? clk->frequency : 0; > +} Is there a use case where we want to support "pass in NULL" rather than just making it a programming error for the caller to try that ? > + > +/** > + * clock_is_enabled: > + * @clk: a clock state > + * > + * @return: true if the clock is running. If @clk is NULL return false. > + */ > +static inline bool clock_is_enabled(const ClockIn *clk) > +{ > + return clock_get_frequency(clk) !=3D 0; > +} Ditto here. thanks -- PMM From MAILER-DAEMON Mon Dec 02 08:45:05 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1ibm0e-0008K5-HS for mharc-qemu-arm@gnu.org; Mon, 02 Dec 2019 08:45:05 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:60396) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ibm0c-0008HA-Hh for qemu-arm@nongnu.org; Mon, 02 Dec 2019 08:45:03 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ibm0b-00021f-FN for qemu-arm@nongnu.org; Mon, 02 Dec 2019 08:45:02 -0500 Received: from mail-ot1-x342.google.com ([2607:f8b0:4864:20::342]:33539) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ibm0b-00021A-9v for qemu-arm@nongnu.org; Mon, 02 Dec 2019 08:45:01 -0500 Received: by mail-ot1-x342.google.com with SMTP id d17so7547099otc.0 for ; Mon, 02 Dec 2019 05:45:01 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=UNCsfXRsfWtMe/ccNNxw+9lM/I8D9p1NJg7vYX4iwto=; b=GszemOh2qwGzBLjApmjYSNZ2JTIrzG+/uWRRrnG15sjyz/gqhzW050LjQ7RzIVOFMh d/34ZiuyCFqlDmSgEREJEF9kFaXCVd6dksSzcYTV73OdGkab5RntwQzuAzZ8sLicqe2O 9phzehzJGyEQL4sWDYRWol0qaRDk587Z1bjdU/cBRWIpjMP10hBnn5VWrCk9e2mHU09S mwaRUsjRJQHQ86/QPFGndOlwnv7iQNpJ0LwFVe2GjkCx9ae6tB4NYcxdku9YNIZaO1kK +Zodi3RNp3RhI6vRedjt9/vgUtceKpadfK5LfZ6j2D9u/9BgxqfIJ6l8lGJAkPwxiNjw j61A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=UNCsfXRsfWtMe/ccNNxw+9lM/I8D9p1NJg7vYX4iwto=; b=M1zDsgb56H2aF0QUNq81dLv8E43sYprIInzqz1toHgFQEAAnzJDbA0C5H5mrDD8cC/ rWbqpHpFT8coUcxmwNc5KFGz7N9p00CnpX/QRxf1uB6Jd+rgpp2hFLA2iPAy2mDCYyFN wqcs5kKeNhvjM/WfFyjp9bzz7pSt6eJbt9BYaa2YNBFUklKP5k4spkXdcG8rTUvz/9pB gVghDZA4LiBuYnQhJ+WLUDWKuTDTrjyGs1ZRaG2ab3OeOSG5u3zSFqCh7s6h1BLDLtQc 0GVXByBfXjvBi4qdLn6d+CVYoTVqjDcNJYlv2dg+80AijnyJ/yD7SjB+my6xUOhjbp7v HIrw== X-Gm-Message-State: APjAAAVXzrSpxt84+ixbDYfcRTSH04gFDEkeIfklJQy1dUqUZ3JXbhCy VERZo2WOxQdiDi+055XgSTV3TJMUbLzNp2E4hXnCkg== X-Google-Smtp-Source: APXvYqwMNW5R89L7qSQaUOBmrKmhK1tiHhCOovvXGkXCQgCihROMR0Q5gW4mZsY+lwlAt1iLqkCLUlfYytHIK08qI4w= X-Received: by 2002:a9d:12d2:: with SMTP id g76mr22150584otg.232.1575294300474; Mon, 02 Dec 2019 05:45:00 -0800 (PST) MIME-Version: 1.0 References: <20190904125531.27545-1-damien.hedde@greensocs.com> <20190904125531.27545-3-damien.hedde@greensocs.com> In-Reply-To: <20190904125531.27545-3-damien.hedde@greensocs.com> From: Peter Maydell Date: Mon, 2 Dec 2019 13:44:49 +0000 Message-ID: Subject: Re: [PATCH v6 2/9] hw/core/clock-vmstate: define a vmstate entry for clock state To: Damien Hedde Cc: QEMU Developers , Mark Burton , "Edgar E. Iglesias" , Alistair Francis , =?UTF-8?B?TWFyYy1BbmRyw6kgTHVyZWF1?= , Paolo Bonzini , "Daniel P. Berrange" , Eduardo Habkost , qemu-arm , =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= Content-Type: text/plain; charset="UTF-8" X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::342 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 02 Dec 2019 13:45:03 -0000 On Wed, 4 Sep 2019 at 13:56, Damien Hedde wrote: > > Signed-off-by: Damien Hedde > --- > This was in the previous reviewed commit. But it can't be in the > clock.c file in order to allow linux-user builds. Reviewed-by: Peter Maydell thanks -- PMM From MAILER-DAEMON Mon Dec 02 09:34:54 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1ibmms-00081K-Jq for mharc-qemu-arm@gnu.org; Mon, 02 Dec 2019 09:34:54 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:39044) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ibmmq-000817-Bb for qemu-arm@nongnu.org; Mon, 02 Dec 2019 09:34:54 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ibmmo-00086P-Fx for qemu-arm@nongnu.org; Mon, 02 Dec 2019 09:34:52 -0500 Received: from mail-ot1-x344.google.com ([2607:f8b0:4864:20::344]:37937) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ibmmo-000868-9S for qemu-arm@nongnu.org; Mon, 02 Dec 2019 09:34:50 -0500 Received: by mail-ot1-x344.google.com with SMTP id z25so31305241oti.5 for ; Mon, 02 Dec 2019 06:34:50 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=OOx/U42IwCgVTBRpxJArTPlYznxoXFOGHOWbSCNf3W0=; b=AixxexQ6NC6ix+9Y/G6mMoBv8oToordZIDm9iTjHK/NuaqLFlE+SJF0xWbD9Jp+jHD lRZDytoHgV2TRX6Lz1YUFn1w0n+jt7Nw/b5tTXd01Hgxzx+FVnr4dN6veJEH5FOibRdF vp7UUGZcWeMrswboob5fEMMDUzjSiJsgcp8Or63Y2B5jxxr+alTpR6Xv78MJaC2hCFhK pj7mzRPSjFvekMQftUSefI1hl+ySCjf2XJhktOeQXbZTh+LZaLJqfTEphmrvvTpcUUyh TNzWzSD2y5Olli2o/br/1H680YdLirHieiWrfED5+jYiUEHOweJIt4ueLzTnQMuTBM6X r0wg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=OOx/U42IwCgVTBRpxJArTPlYznxoXFOGHOWbSCNf3W0=; b=ZNGfU5MVAxVC/Y88xypAkZKjNGmb6bB9QX3BAHQN+yFpS7ZIGnfxyxRV250M+LajDE TjTgTKXJx0YPxJ3cy4Y3bSsDp9AKINfv9heK51/yRyP+kxLiSRNYk5LUU7XSxilxTs6J hd5WZxhk52mw73Fif9BJjGuqroBC3+c0VCjDzKGvXLfbKjAeizrbehXHySiCOxG9dckq aaHTZLUsUZo8t7JRlqP/72PKLyA2wAkMGjX4T8h04qOOA1v24noB22aHfWFr9sFYDBDa eJlK8PQvVDdmxk2GXD2zGJ+fkEBhnTbihdZlhDqKcxzARuMVEq80p+nVgAYOLXWjTHEi Oz3Q== X-Gm-Message-State: APjAAAVR4S/+JsoNUhbJ0hN0YzSG6V+xRd3grU0CjU7VUWwR7tP9DeAY 5cBMX1ZYfaewu0cbOAF6QlbkEoW/wOzagjadVB7UTw== X-Google-Smtp-Source: APXvYqxbEvify2wKC5QA+Sk8C6vxS+H1KevVgESZEHs+P0D4n8PkjtHbW1p4L+9iM5azzAMgb0nsowM1CCED19svHuY= X-Received: by 2002:a9d:6357:: with SMTP id y23mr21860696otk.91.1575297288933; Mon, 02 Dec 2019 06:34:48 -0800 (PST) MIME-Version: 1.0 References: <20190904125531.27545-1-damien.hedde@greensocs.com> <20190904125531.27545-4-damien.hedde@greensocs.com> In-Reply-To: <20190904125531.27545-4-damien.hedde@greensocs.com> From: Peter Maydell Date: Mon, 2 Dec 2019 14:34:37 +0000 Message-ID: Subject: Re: [PATCH v6 3/9] qdev: add clock input&output support to devices. To: Damien Hedde Cc: QEMU Developers , Mark Burton , "Edgar E. Iglesias" , Alistair Francis , =?UTF-8?B?TWFyYy1BbmRyw6kgTHVyZWF1?= , Paolo Bonzini , "Daniel P. Berrange" , Eduardo Habkost , qemu-arm , =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= Content-Type: text/plain; charset="UTF-8" X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::344 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 02 Dec 2019 14:34:54 -0000 On Wed, 4 Sep 2019 at 13:56, Damien Hedde wrote: > > Add functions to easily add input or output clocks to a device. > A clock objects is added as a child of the device. "object" > The api is very similar the gpio's one. "API"; "to the GPIO API". > > This is based on the original work of Frederic Konrad. > > Signed-off-by: Damien Hedde > > +static NamedClockList *qdev_init_clocklist(DeviceState *dev, const char *name, > + bool forward) > +{ > + NamedClockList *ncl; > + > + /* > + * The clock path will be computed by the device's realize function call. > + * This is required to ensure the clock's canonical path is right and log > + * messages are meaningfull. "meaningful" > + */ > + assert(name); > + assert(!dev->realized); > + > + /* The ncl structure will be freed in device's finalize function call */ Do you mean "in device_finalize()", or "in the finalize method of the device" ? If you mean a specific function, then it's good to name it, so the reader can go and check that code if they need to confirm that there's a matching free()/deref/etc. > + ncl = g_malloc0(sizeof(*ncl)); Prefer g_new0(NamedClockList, 1). > + ncl->name = g_strdup(name); > + ncl->forward = forward; > + > + QLIST_INSERT_HEAD(&dev->clocks, ncl, node); > + return ncl; > +} > + > +ClockOut *qdev_init_clock_out(DeviceState *dev, const char *name) > +{ > + NamedClockList *ncl; > + Object *clk; > + > + ncl = qdev_init_clocklist(dev, name, false); > + > + clk = object_new(TYPE_CLOCK_OUT); > + > + /* will fail if name already exists */ This is true but it would be more helpful to say /* * Trying to create a clock whose name clashes with some other * clock or property is a bug in the caller and we will abort(). */ (assuming that's what's going on here). > + object_property_add_child(OBJECT(dev), name, clk, &error_abort); > + object_unref(clk); /* remove the initial ref made by object_new */ > + > + ncl->out = CLOCK_OUT(clk); > + return ncl->out; > +} > + > +ClockIn *qdev_init_clock_in(DeviceState *dev, const char *name, > + ClockCallback *callback, void *opaque) > +{ > + NamedClockList *ncl; > + Object *clk; > + > + ncl = qdev_init_clocklist(dev, name, false); > + > + clk = object_new(TYPE_CLOCK_IN); > + /* > + * the ref initialized by object_new will be cleared during dev finalize. This means "in device_finalize()", I think from reading later patches ? > + * It allows us to safely remove the callback. > + */ > + > + /* will fail if name already exists */ Similar remark as for earlier comment. > + object_property_add_child(OBJECT(dev), name, clk, &error_abort); > + > + ncl->in = CLOCK_IN(clk); > + if (callback) { > + clock_set_callback(ncl->in, callback, opaque); > + } > + return ncl->in; > +} > +ClockIn *qdev_get_clock_in(DeviceState *dev, const char *name) > +{ > + NamedClockList *ncl; > + > + assert(dev && name); > + > + ncl = qdev_get_clocklist(dev, name); > + return ncl ? ncl->in : NULL; > +} Do we expect to want to be able to pass in the name of a clock that doesn't exist ? Should that be an error rather than returning NULL ? > + > +static ClockOut *qdev_get_clock_out(DeviceState *dev, const char *name) > +{ > + NamedClockList *ncl; > + > + assert(dev && name); > + > + ncl = qdev_get_clocklist(dev, name); > + return ncl ? ncl->out : NULL; Ditto. > +} > + > +void qdev_connect_clock_out(DeviceState *dev, const char *name, ClockIn *clk, > + Error **errp) > +{ > + ClockOut *clkout = qdev_get_clock_out(dev, name); > + > + if (!clk) { > + error_setg(errp, "NULL input clock"); > + return; > + } > + > + if (!clkout) { > + error_setg(errp, "no output clock '%s' in device", name); > + return; > + } > + > + clock_connect(clk, clkout); Do we need to support returning an error here, or would it always be a programming bug to try to connect a non-existent clock? > --- /dev/null > +++ b/include/hw/qdev-clock.h > @@ -0,0 +1,67 @@ > +#ifndef QDEV_CLOCK_H > +#define QDEV_CLOCK_H Another missing copyright/license comment. > + > +#include "hw/clock.h" > + > +/** > + * qdev_init_clock_in: > + * @dev: the device in which to add a clock "the device to add a clock input to" > + * @name: the name of the clock (can't be NULL). > + * @callback: optional callback to be called on update or NULL. > + * @opaque: argument for the callback > + * @returns: a pointer to the newly added clock > + * > + * Add a input clock to device @dev as a clock named @name. > + * This adds a child<> property. > + * The callback will be called with @dev as opaque parameter. Isn't it called with @opaque, not @dev ? > + */ > +ClockIn *qdev_init_clock_in(DeviceState *dev, const char *name, > + ClockCallback *callback, void *opaque); > + > +/** > + * qdev_init_clock_out: > + * @dev: the device to add a clock to "the device to add a clock output to" > + * @name: the name of the clock (can't be NULL). > + * @callback: optional callback to be called on update or NULL. > + * @returns: a pointer to the newly added clock > + * > + * Add a output clock to device @dev as a clock named @name. > + * This adds a child<> property. > + */ > +ClockOut *qdev_init_clock_out(DeviceState *dev, const char *name); > + > +/** > + * qdev_get_clock_in: > + * @dev: the device which has the clock > + * @name: the name of the clock (can't be NULL). > + * @returns: a pointer to the clock > + * > + * Get the clock @name from @dev or NULL if does not exists. "if it does not exist" > + */ > +ClockIn *qdev_get_clock_in(DeviceState *dev, const char *name); > + > +/** > + * qdev_connect_clock_out: > + * @dev: the device which has the clock > + * @name: the name of the clock (can't be NULL). > + * @errp: error report > + * > + * Connect @clk to the output clock @name of @dev. > + * Reports an error if clk is NULL or @name does not exists in @dev. "or if @name does not exist in @dev" > + */ > +void qdev_connect_clock_out(DeviceState *dev, const char *name, ClockIn *clk, > + Error **errp); > + > +/** > + * qdev_pass_clock: > + * @dev: the device to forward the clock to > + * @name: the name of the clock to be added (can't be NULL) > + * @container: the device which already has the clock > + * @cont_name: the name of the clock in the container device > + * > + * Add a clock @name to @dev which forward to the clock @cont_name in @container > + */ 'container' seems odd terminology here, because I would expect the usual use of this function to be when a 'container' object like an SoC wants to forward a clock to one of its components; in that case the 'container' SoC would be @dev, wouldn't it? We should get this to be the same way round as qdev_pass_gpios(), which takes "DeviceState *dev, DeviceState *container", and passes the gpios that exist on 'dev' over to 'container' so that 'container' now has gpios which it did not before. Also, your use of 'forward to' is inconsistent: in the 'dev' documentation you say we're forwarding the clock to 'dev', but in the body of the documentation you say we're forwarding the clock to the clock in 'container'. I think the way to resolve this is to stick to the terminology in the function name itself: @dev: the device which has the clock @name: the name of the clock on @dev @container: the name of the device which the clock should be passed to @cont_name: the name to use for the clock on @container Q: if you pass a clock to another device with this function, does it still exist to be used directly on the original device? For qdev_pass_gpios it does not (I think), but this is more accident of implementation than anything else. > +void qdev_pass_clock(DeviceState *dev, const char *name, > + DeviceState *container, const char *cont_name); > + > +#endif /* QDEV_CLOCK_H */ > diff --git a/include/hw/qdev-core.h b/include/hw/qdev-core.h > index eb11f0f801..60a65f6142 100644 > --- a/include/hw/qdev-core.h > +++ b/include/hw/qdev-core.h > @@ -131,6 +131,19 @@ struct NamedGPIOList { > QLIST_ENTRY(NamedGPIOList) node; > }; > > +typedef struct NamedClockList NamedClockList; > + > +typedef struct ClockIn ClockIn; > +typedef struct ClockOut ClockOut; > + > +struct NamedClockList { > + char *name; Could this be 'const char*' ? > + bool forward; > + ClockIn *in; > + ClockOut *out; > + QLIST_ENTRY(NamedClockList) node; > +}; thanks -- PMM From MAILER-DAEMON Mon Dec 02 09:35:39 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1ibmnb-0000Rd-FV for mharc-qemu-arm@gnu.org; Mon, 02 Dec 2019 09:35:39 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:39186) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ibmnY-0000Ok-TW for qemu-arm@nongnu.org; Mon, 02 Dec 2019 09:35:37 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ibmnX-0008Lw-Tl for qemu-arm@nongnu.org; Mon, 02 Dec 2019 09:35:36 -0500 Received: from mail-oi1-x244.google.com ([2607:f8b0:4864:20::244]:33177) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ibmnX-0008Lk-Og for qemu-arm@nongnu.org; Mon, 02 Dec 2019 09:35:35 -0500 Received: by mail-oi1-x244.google.com with SMTP id x21so25504199oic.0 for ; Mon, 02 Dec 2019 06:35:35 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc:content-transfer-encoding; bh=yagIx/TuVFmkuXmSVKfUN+M4CJhpe9vr7IPQM2u2PIs=; b=AwGkMoSycbGw+xMuRIVpVKTB4t1Pe25RTYWodNhkHef09BzzaVYULPAxoby2NHo60Y 0kUFKfsW5n1rNRgJe1Ky5bVZ++ecoqgjG6O1Y7ZVDDyd6/KW6XRso/R131oWdhNtHxmC fUFm2RBfYsyyZCqa5b37RQukOqLZhRGaTffVzxgykiWi+i6HwXRHIdfvIvbZtep40U6f nVHijfv+h4+uRjJZK8g02fs472lJR7NYZiPUtmhKKXJ5aCEzkOS4pcS8brJlEXszCjrg XwDnPxABfBUgRMyKZCSquTlOXGyRMCc1VEnrjf+p/mf0wQ8E1RSE+Sye2zz8r7/xcYXE mNPQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc:content-transfer-encoding; bh=yagIx/TuVFmkuXmSVKfUN+M4CJhpe9vr7IPQM2u2PIs=; b=WaueSD09KqtN5oPmd3sRuzYmaoTrZ3GQpsJp217+d3+5K8+yvAWTVSNUs8puRaH3cG aQ8fYyoZbLmfV1Koz/Ea5p5aLDKsv0DGVSC5ap+cj3LhMoYtqizv7Q4jWrCo69posymO UZp+ob4U4mYU8b+MCZzZCMlFV1wfhS4JaqIoRV+Im1r1qAN710qSh7zFhoYxjps/8mrD tddGNGvix6cw5YSjKGpXLPh4PpxC3StEG7bpKQEeUSFoODd7XywpvbBKlhg3RVeFfqBW Wj4PacZSr99e+1GiioD2ppndZj8Y/bAGaUvjZ+GG9RNQrA/P0ubdTJ9zkz4PCKgHArax 3Dug== X-Gm-Message-State: APjAAAWSGPP6qGLKaynseEh7H8d5fa6jLluS8D+NdFZhzeK86j9AE72S gzQ+hxaG7BtBZPzjmETjciHPCXesGBdJ92qTsggrsg== X-Google-Smtp-Source: APXvYqywHKp1TBf9VKYWSBuWrzhmeDV2kVzbCZabCrlAqogNg9gpaYPc8AdHipFheybSWhecqf0UxQPdy5G6zg/WjDg= X-Received: by 2002:aca:edd5:: with SMTP id l204mr12580766oih.98.1575297334268; Mon, 02 Dec 2019 06:35:34 -0800 (PST) MIME-Version: 1.0 References: <20190904125531.27545-1-damien.hedde@greensocs.com> <20190904125531.27545-5-damien.hedde@greensocs.com> In-Reply-To: <20190904125531.27545-5-damien.hedde@greensocs.com> From: Peter Maydell Date: Mon, 2 Dec 2019 14:35:23 +0000 Message-ID: Subject: Re: [PATCH v6 4/9] qdev-monitor: print the device's clock with info qtree To: Damien Hedde Cc: QEMU Developers , Mark Burton , "Edgar E. Iglesias" , Alistair Francis , =?UTF-8?B?TWFyYy1BbmRyw6kgTHVyZWF1?= , Paolo Bonzini , "Daniel P. Berrange" , Eduardo Habkost , qemu-arm , =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::244 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 02 Dec 2019 14:35:38 -0000 On Wed, 4 Sep 2019 at 13:56, Damien Hedde wrot= e: > > This prints the clocks attached to a DeviceState when using "info qtree" = monitor > command. For every clock, it displays the direction, the name and if the > clock is forwarded. For input clock, it displays also the frequency. > > This is based on the original work of Frederic Konrad. Providing a sample of the 'info qtree' output in the commit message would be nice. > > Signed-off-by: Damien Hedde > Reviewed-by: Philippe Mathieu-Daud=C3=A9 > Tested-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Peter Maydell thanks -- PMM From MAILER-DAEMON Mon Dec 02 10:13:26 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1ibnOA-0006kY-NE for mharc-qemu-arm@gnu.org; Mon, 02 Dec 2019 10:13:26 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:44501) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ibnO7-0006kB-8j for qemu-arm@nongnu.org; Mon, 02 Dec 2019 10:13:24 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ibnO5-0003Ju-V1 for qemu-arm@nongnu.org; Mon, 02 Dec 2019 10:13:23 -0500 Received: from mail-oi1-x242.google.com ([2607:f8b0:4864:20::242]:38805) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ibnO5-0003JY-Qo for qemu-arm@nongnu.org; Mon, 02 Dec 2019 10:13:21 -0500 Received: by mail-oi1-x242.google.com with SMTP id b8so3497304oiy.5 for ; Mon, 02 Dec 2019 07:13:21 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc:content-transfer-encoding; bh=q51OprDEZ8c6nQUVqt2JoEFN8OvtbrXdTiVDSXhbGb8=; b=cJEW0aP8PES+gRwEKtGz9dMqSNPngYb7wJxUvc6U3MX0R3MK6oaIBXrjt5NpnBLS2V QRVYjRKIcD/C4n8b8eVh0k82J6h8bKWejbXYN2HqiKXUVK5zhqtgJQ98SvFRJHRuLhay z2g0Eee5QMcxbm0OmTKeU0QChgVZ/fdibiLQOlN9mtzmrHJ+owL1MA5nibYpslPpFMc1 Xdrhex1QRTb7wZvM8Zhm2BbIVUyB9vujBN6cvutUuMG1/2lThoPCDm7uRqQq79TEPn46 t56iO9NO+3fR7ZSipFxwXI3r++Og7Vz3MeFeyQmD0q+rbqxKSNAq9J1AlLeXMpxx0ASu 8+gA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc:content-transfer-encoding; bh=q51OprDEZ8c6nQUVqt2JoEFN8OvtbrXdTiVDSXhbGb8=; b=mNGY3ibmHjZ3Q1F8DFi1jYdI7t4i2b/pyMopaIQ6tBguNr5ZExzL+3MSl7j83JK0v8 gbSF3BMz9W5HrWEaR/Zlx3X+SAxcRUqDjiTkWyNWrjQT19HA4ehSHH2hD1I3AX1e9rg7 gLXsEXh0xhCfvpcPQHP3Ub+0Mjtv18SREmBo+i9imXNEgcjl7bn+uPTU8PClaC0wfqac CfWXygdvqhlwDNoKfpcBUPPu5Stmv2HLCxTuMXRA9vjpjwC9yLxYrR6M2/asNDlEh2BM iRg9HGPqFQQBMFEeUBhUqDSOynYffJD+8DrvQJ1CFjvEMIl56ONFwFbXso5bxBt3dRO2 Jh5w== X-Gm-Message-State: APjAAAUTErACI5TYrQjjXhfSijrXS39d4kZL9r8G72/8kPHglSeltJ3d ZtEZbG9bqKilJ6q9QSHK2NQQhyCZ9Wh1Po5zwu/foQ== X-Google-Smtp-Source: APXvYqz4OvS0zGSt6PTg0wSfxwNZcQHBi17DbYKQl2JSJckiTAcrFokpe7L1TyLVsKDftW8RaoEtoW9K8jVeRq2vZ2Q= X-Received: by 2002:aca:f484:: with SMTP id s126mr9353276oih.48.1575299600734; Mon, 02 Dec 2019 07:13:20 -0800 (PST) MIME-Version: 1.0 References: <20190904125531.27545-1-damien.hedde@greensocs.com> <20190904125531.27545-6-damien.hedde@greensocs.com> In-Reply-To: <20190904125531.27545-6-damien.hedde@greensocs.com> From: Peter Maydell Date: Mon, 2 Dec 2019 15:13:09 +0000 Message-ID: Subject: Re: [PATCH v6 5/9] qdev-clock: introduce an init array to ease the device construction To: Damien Hedde Cc: QEMU Developers , Mark Burton , "Edgar E. Iglesias" , Alistair Francis , =?UTF-8?B?TWFyYy1BbmRyw6kgTHVyZWF1?= , Paolo Bonzini , "Daniel P. Berrange" , Eduardo Habkost , qemu-arm , =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::242 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 02 Dec 2019 15:13:24 -0000 On Wed, 4 Sep 2019 at 13:56, Damien Hedde wrot= e: > > Introduce a function and macro helpers to setup several clocks > in a device from a static array description. > > An element of the array describes the clock (name and direction) as > well as the related callback and an optional offset to store the > created object pointer in the device state structure. > > The array must be terminated by a special element QDEV_CLOCK_END. > > This is based on the original work of Frederic Konrad. > > Signed-off-by: Damien Hedde > Reviewed-by: Philippe Mathieu-Daud=C3=A9 > --- > hw/core/qdev-clock.c | 26 ++++++++++++++++ > include/hw/qdev-clock.h | 67 +++++++++++++++++++++++++++++++++++++++++ > 2 files changed, 93 insertions(+) > > diff --git a/hw/core/qdev-clock.c b/hw/core/qdev-clock.c > index bebdd8fa15..32ad45c061 100644 > --- a/hw/core/qdev-clock.c > +++ b/hw/core/qdev-clock.c > @@ -153,3 +153,29 @@ void qdev_connect_clock_out(DeviceState *dev, const = char *name, ClockIn *clk, > > clock_connect(clk, clkout); > } > + > +void qdev_init_clocks(DeviceState *dev, const ClockPortInitArray clocks) > +{ > + const struct ClockPortInitElem *elem; > + > + assert(dev); > + assert(clocks); More unnecessary asserts, I think. > +/** > + * ClockInitElem: > + * @name: name of the clock (can't be NULL) > + * @is_output: indicates whether the clock is input or output > + * @callback: for inputs, optional callback to be called on clock's upda= te > + * with device as opaque > + * @offset: optional offset to store the ClockIn or ClockOut pointer in = device > + * state structure (0 means unused) > + */ > +struct ClockPortInitElem { > + const char *name; > + bool is_output; > + ClockCallback *callback; > + size_t offset; > +}; > + > +#define clock_offset_value(_type, _devstate, _field) \ > + (offsetof(_devstate, _field) + \ > + type_check(_type *, typeof_field(_devstate, _field))) Avoid leading underscores, please. > + > +#define QDEV_CLOCK(_is_output, _type, _devstate, _field, _callback) { \ > + .name =3D (stringify(_field)), \ > + .is_output =3D _is_output, \ > + .callback =3D _callback, \ > + .offset =3D clock_offset_value(_type, _devstate, _field), \ > +} > + > +/** > + * QDEV_CLOCK_(IN|OUT): > + * @_devstate: structure type. @dev argument of qdev_init_clocks below m= ust be > + * a pointer to that same type. It's a bit unclear what "below" here is referring to. Maybe just have this be "@devstate: name of a C struct type" and then explain below... > + * @_field: a field in @_devstate (must be ClockIn* or ClockOut*) > + * @_callback: (for input only) callback (or NULL) to be called with the= device > + * state as argument > + * ...here, where we can have a paragraph giving the purpose of the macro: "Define an entry in a ClockPortInitArray which is intended to be passed to qdev_init_clocks(), which should be called with an @dev argument which is a pointer to the @devstate struct type." > + * The name of the clock will be derived from @_field Derived how? Guessing from the stringify(_field) above that it will be the same as the field name ? It makes sense to hardcode the opaque pointer for the callback to be the device pointer. > + */ > +#define QDEV_CLOCK_IN(_devstate, _field, _callback) \ > + QDEV_CLOCK(false, ClockIn, _devstate, _field, _callback) > + > +#define QDEV_CLOCK_OUT(_devstate, _field) \ > + QDEV_CLOCK(true, ClockOut, _devstate, _field, NULL) > + > +/** > + * QDEV_CLOCK_IN_NOFIELD: > + * @_name: name of the clock > + * @_callback: callback (or NULL) to be called with the device state as = argument > + */ > +#define QDEV_CLOCK_IN_NOFIELD(_name, _callback) { \ > + .name =3D _name, \ > + .is_output =3D false, \ > + .callback =3D _callback, \ > + .offset =3D 0, \ > +} When would we want to use this one ? > + > +#define QDEV_CLOCK_END { .name =3D NULL } > + > +typedef struct ClockPortInitElem ClockPortInitArray[]; > + > +/** > + * qdev_init_clocks: > + * @dev: the device to add clocks "to add clocks to" > + * @clocks: a QDEV_CLOCK_END-terminated array which contains the > + * clocks information. > + */ > +void qdev_init_clocks(DeviceState *dev, const ClockPortInitArray clocks)= ; > + > #endif /* QDEV_CLOCK_H */ > -- > 2.22.0 > thanks -- PMM From MAILER-DAEMON Mon Dec 02 10:18:00 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1ibnSa-0000co-H1 for mharc-qemu-arm@gnu.org; Mon, 02 Dec 2019 10:18:00 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:45019) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ibnSY-0000cc-3G for qemu-arm@nongnu.org; Mon, 02 Dec 2019 10:17:59 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ibnSW-0005uH-NC for qemu-arm@nongnu.org; Mon, 02 Dec 2019 10:17:57 -0500 Received: from mail-io1-xd43.google.com ([2607:f8b0:4864:20::d43]:38006) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ibnSW-0005tO-Gh for qemu-arm@nongnu.org; Mon, 02 Dec 2019 10:17:56 -0500 Received: by mail-io1-xd43.google.com with SMTP id u24so39199959iob.5 for ; Mon, 02 Dec 2019 07:17:56 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=AyEE6rm28fohnOjDpM5iW4SydDnsLq70FLgX6leZw3U=; b=ASCeWhO/c0PXzxb1EKZ9JwisA4d7avcb5i9V5AUNEiX3VKJ4JWHl4cFir95re3yO8+ j7GHk0haozWM7Z0K5TnQ1mjIEcyHnEzpP6gK2b5aeKXKwuUPs+h6Ij9qSzBoo3qFRTAW fr6HzKEULDWo6RH/jeRDPITxHpxQKfDuuVAFGvEIzQ96PHw8b1r43vaG/gQQvrnyauTY 3Jwrgp9XTy5K5w5Npr+cZiLcavABnToS1RXPuLg8A5Q796xBK3Sr/heS6oVbGSSPTM2M 1sjI59r3B+8hFF+WxS6GyviP1ogc3FlA8UpOWr4fK35JulrW62c/4Z4mTK5542KjiZYi Olhw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=AyEE6rm28fohnOjDpM5iW4SydDnsLq70FLgX6leZw3U=; b=T2wO4yNqKwsSlm1vGeD0te0wASM+yo3fzso0cIzVufuZ6FtEjKVfjKvWZqnQ4ojii7 gfqn7yPH8oEh9N4ceqKJ5dpxqfuQ3H+1RsGoyO/cEg5JjmBoJnL8ntmeH0IC8UPiWwuM yUohS2NsxWUpMlkerP/QHZmTEhCzPdKa1xzYnae5hbLH01acD3kdswU6bfAdFCnCVVsu bFDOl0SdUDHDsw6OaAX6Njkt/1IvkltUFxUG4ik0sbWaTn9OLxAVcd5VIMWJP6abutAp lFW5x9sLvmR2eQ506ErO2DYB3fIBJLGw1FApIWcRPeNCeeyooURTPUd2HLtSHAKMce0q kNMA== X-Gm-Message-State: APjAAAUpQiyfFyV26Og8/PumSzkYGvgRNfwUvrz3toMpeqnC4+Ux9PB4 JfhfjDrakHXZk3AHr36kv2enUYchFLGhWQRx9rcd+A== X-Google-Smtp-Source: APXvYqzsY0Nf/Exi6eu3LA3kM1tDshhmSOrUYHmKFtN9/sNVwW6JZFc/0LcOO6LH0jzPmYTVKev1Je9g8eXFVwmI4d8= X-Received: by 2002:a02:a148:: with SMTP id m8mr26271758jah.69.1575299875215; Mon, 02 Dec 2019 07:17:55 -0800 (PST) MIME-Version: 1.0 References: <20190904125531.27545-1-damien.hedde@greensocs.com> <20190904125531.27545-7-damien.hedde@greensocs.com> In-Reply-To: <20190904125531.27545-7-damien.hedde@greensocs.com> From: Peter Maydell Date: Mon, 2 Dec 2019 15:17:43 +0000 Message-ID: Subject: Re: [PATCH v6 6/9] docs/clocks: add device's clock documentation To: Damien Hedde Cc: QEMU Developers , Mark Burton , "Edgar E. Iglesias" , Alistair Francis , =?UTF-8?B?TWFyYy1BbmRyw6kgTHVyZWF1?= , Paolo Bonzini , "Daniel P. Berrange" , Eduardo Habkost , qemu-arm , =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= Content-Type: text/plain; charset="UTF-8" X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::d43 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 02 Dec 2019 15:17:59 -0000 On Wed, 4 Sep 2019 at 13:56, Damien Hedde wrote: > > Add the documentation about the clock inputs and outputs in devices. > > This is based on the original work of Frederic Konrad. > > Signed-off-by: Damien Hedde > --- > docs/devel/clock.txt | 246 +++++++++++++++++++++++++++++++++++++++++++ > 1 file changed, 246 insertions(+) > create mode 100644 docs/devel/clock.txt Could you convert this to rst format, please? > +Changing a clock output > +======================= > + > +A device can change its outputs using the clock_set_frequency function. It > +will trigger updates on every connected inputs. "input" > + > +For example, let's say that we have an output clock "clkout" and we have a > +pointer to it in the device state because we did the following in init phase: > +dev->clkout = qdev_init_clock_out(DEVICE(dev), "clkout"); > + > +Then at any time (apart from the cases listed below), it is possible to > +change the clock value by doing: > +clock_set_frequency(dev->clkout, 1000 * 1000 * 1000); /* 1Ghz */ > +This operation must be done while holding the qemu io lock. > + > +One can change clocks only when it is allowed to have side effects on other > +objects. In consequence, it is forbidden: > ++ during migration, > ++ and in the init phase of reset. > + > +Forwarding clocks > +================= > + > +Sometimes, one needs to forward, or inherit, a clock from another device. > +Typically, when doing device composition, a device might expose a sub-device's > +clock without interfering with it. > +The function qdev_pass_clock() can be used to achieve this behaviour. Note, that "Note that" > +it is possible to expose the clock under a different name. This works for both > +inputs or outputs. "inputs and outputs" > +Migration > +========= > + > +Only the ClockIn object has a state. ClockOut is not concerned by migration. "has any state". "ClockOut has no state and does not need special handling for migration." > + > +In case the frequency of in input clock is needed for a device's migration, > +this state must be migrated. Are you trying to say that if an input clock is known to be a fixed frequency we don't need to migrate anything? I wonder if we need to worry about that or if we could/should just say that input clocks should always be migrated. > The VMSTATE_CLOCKIN macro defines an entry to > +be added in a vmstate description. > + > +For example, if a device has a clock input and the device state looks like: > +MyDeviceState { > + DeviceState parent_obj; > + ClockIn *clk; > +}; > + > +Then, to add the clock frequency to the device's migrated state, the vmstate > +description is: > +VMStateDescription my_device_vmstate = { > + .name = "my_device", > + .fields = (VMStateField[]) { > + VMSTATE_CLOCKIN(clk, MyDeviceState), > + VMSTATE_END_OF_LIST() > + } > +}; > + > +When adding a input clock support to an existing device, you must care about > +migration compatibility. To this end, you can use the clock_init_frequency in > +a pre_load function to setup a default value in case the source vm does not > +migrate the frequency. thanks -- PMM From MAILER-DAEMON Mon Dec 02 10:20:30 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1ibnUy-0001kJ-Sk for mharc-qemu-arm@gnu.org; Mon, 02 Dec 2019 10:20:29 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:45264) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ibnUw-0001k5-76 for qemu-arm@nongnu.org; Mon, 02 Dec 2019 10:20:27 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ibnUv-0007F9-19 for qemu-arm@nongnu.org; Mon, 02 Dec 2019 10:20:26 -0500 Received: from mail-io1-xd44.google.com ([2607:f8b0:4864:20::d44]:46012) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ibnUu-0007Eh-90 for qemu-arm@nongnu.org; Mon, 02 Dec 2019 10:20:24 -0500 Received: by mail-io1-xd44.google.com with SMTP id i11so30044720ioi.12 for ; Mon, 02 Dec 2019 07:20:24 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=D5j5sc6m+3Do9c2vsFcfFanl3eE/9mKLyTDuX+zpAuo=; b=RyAIufo82LnEb0ct0nMaUs7kc8wpVYDWbPPW3mKWWlNAsm8EuRwYjJtmjUNhTlP+81 3zau4PFNO7L8psABWAT60N5D/v3rt1I1WLVcPAfptoodzwRToEvmEETHyjDbq5V6deWK hAgB5F66pjxx9bqQtuY7yXkckAS8JCk3+8NvNaH46zxrbd0ZVVHRQF3zm/XRws6huGZj zbu2kaCVMCeu5o6r6S2/TiVNk82c5iJc0bGDMe4ORSk7EfcfOduP9bJPs2Iujl7EgA1S TTYeZ05x/EW2Kld72q4NBfpiE4ILQ3o7o3oh4bvWWPUiBYU+E6Gsq9Wg2yS8vo4SY2AC l3ZQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=D5j5sc6m+3Do9c2vsFcfFanl3eE/9mKLyTDuX+zpAuo=; b=et4GDHrM9BRPRkF90MgX/K+hehwlDNEHkok5tYkrKY9+73O/e4yseLPouy3/ve8D1m qTrRQL3+8EOwgFuWixiyrBtEDQgeG69iY6erch4Snss+cOVMiYI7rSkmfqEhAwXM7Ppe aKxkVfl97wAZg24G0jd0AhmtKwp9DrtQDuYJvieWHijO0tjISVIOnyscmUY7ihAE6Ngo OmCA9lA0s/5uwRYJfvLVPE8gkHV3Sym4UwgzJaNPbZSyS59A3AlSAx25KOsJe+/9t8Ut kQjU035cqWLJ0wy3n/ZY1vKdXvGx4EsCf/ZIY/sE7wY1ttZReylv4nlYTxq9YaO5ZYpG uHpw== X-Gm-Message-State: APjAAAVPv78vJMgvtmrt3mF0Xz1UwLYhoSsj8pXrBEqOw/r7jz6pKO+G G8Lqqx4VtfikJaOOtJ8QbcAQSbGCMA859Kkcc4yuxw== X-Google-Smtp-Source: APXvYqz9jURPCuTYUUYdTxs7l8hqdgsTr6KuVZR32Hf4iSyJ4sCMw+51Q2VptBfXqOBr9X0qkNVbRuFpgSkJALBzkAY= X-Received: by 2002:a02:55c3:: with SMTP id e186mr28436075jab.143.1575300023375; Mon, 02 Dec 2019 07:20:23 -0800 (PST) MIME-Version: 1.0 References: <20190904125531.27545-1-damien.hedde@greensocs.com> <20190904125531.27545-8-damien.hedde@greensocs.com> In-Reply-To: <20190904125531.27545-8-damien.hedde@greensocs.com> From: Peter Maydell Date: Mon, 2 Dec 2019 15:20:12 +0000 Message-ID: Subject: Re: [PATCH v6 7/9] hw/misc/zynq_slcr: add clock generation for uarts To: Damien Hedde Cc: QEMU Developers , Mark Burton , "Edgar E. Iglesias" , Alistair Francis , =?UTF-8?B?TWFyYy1BbmRyw6kgTHVyZWF1?= , Paolo Bonzini , "Daniel P. Berrange" , Eduardo Habkost , qemu-arm , =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= Content-Type: text/plain; charset="UTF-8" X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::d44 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 02 Dec 2019 15:20:27 -0000 On Wed, 4 Sep 2019 at 13:56, Damien Hedde wrote: > > Switch the slcr to multi-phase reset and add some clocks: > + the main input clock (ps_clk) > + the reference clock outputs for each uart (uart0 & 1) > > The clock frequencies are computed using the internal pll & uart configuration > registers and the ps_clk frequency. > > Signed-off-by: Damien Hedde Review of this and the following two patches by some Xilinx person would be nice. I've just looked them over for general issues, and haven't checked against the hardware specs. > --- > +/* > + * return the output frequency of a clock given: > + * + the frequencies in an array corresponding to mux's indexes > + * + the register xxx_CLK_CTRL value > + * + enable bit index in ctrl register > + * > + * This function make the assumption that ctrl_reg value is organized as follow: "makes"; "that the"; "follows" > + * + bits[13:8] clock divisor > + * + bits[5:4] clock mux selector (index in array) > + * + bits[index] clock enable > + */ > +static uint64_t zynq_slcr_compute_clock(const uint64_t mux[], > + uint32_t ctrl_reg, > + unsigned index) > +{ > + uint32_t srcsel = extract32(ctrl_reg, 4, 2); /* bits [5:4] */ > + uint32_t divisor = extract32(ctrl_reg, 8, 6); /* bits [13:8] */ > + > + /* first, check if clock is enabled */ > + if (((ctrl_reg >> index) & 1u) == 0) { > + return 0; > + } > + > + /* > + * according to the Zynq technical ref. manual UG585 v1.12.2 in > + * "Clocks" chapter, section 25.10.1 page 705" the range of the divisor > + * is [1;63]. Is this the range notation the spec doc uses? > + * So divide the source while avoiding division-by-zero. > + */ > + return mux[srcsel] / (divisor ? divisor : 1u); > +} > + > +static const ClockPortInitArray zynq_slcr_clocks = { > + QDEV_CLOCK_IN(ZynqSLCRState, ps_clk, zynq_slcr_ps_clk_callback), > + QDEV_CLOCK_OUT(ZynqSLCRState, uart0_ref_clk), > + QDEV_CLOCK_OUT(ZynqSLCRState, uart1_ref_clk), > + QDEV_CLOCK_END > +}; > + > static void zynq_slcr_init(Object *obj) > { > ZynqSLCRState *s = ZYNQ_SLCR(obj); > @@ -425,6 +559,8 @@ static void zynq_slcr_init(Object *obj) > memory_region_init_io(&s->iomem, obj, &slcr_ops, s, "slcr", > ZYNQ_SLCR_MMIO_SIZE); > sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->iomem); > + > + qdev_init_clocks(DEVICE(obj), zynq_slcr_clocks); > } > > static const VMStateDescription vmstate_zynq_slcr = { > @@ -440,9 +576,12 @@ static const VMStateDescription vmstate_zynq_slcr = { > static void zynq_slcr_class_init(ObjectClass *klass, void *data) > { > DeviceClass *dc = DEVICE_CLASS(klass); > + ResettableClass *rc = RESETTABLE_CLASS(klass); > > dc->vmsd = &vmstate_zynq_slcr; > - dc->reset = zynq_slcr_reset; > + rc->phases.init = zynq_slcr_reset_init; > + rc->phases.hold = zynq_slcr_reset_hold; > + rc->phases.exit = zynq_slcr_reset_exit; > } We're adding an input clock, so doesn't the migration state struct need to be updated to migrate it ? thanks -- PMM From MAILER-DAEMON Mon Dec 02 10:24:51 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1ibnZC-0004Rh-UK for mharc-qemu-arm@gnu.org; Mon, 02 Dec 2019 10:24:50 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:45850) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ibnZA-0004RV-Pj for qemu-arm@nongnu.org; Mon, 02 Dec 2019 10:24:49 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ibnZ8-0000w3-MZ for qemu-arm@nongnu.org; Mon, 02 Dec 2019 10:24:47 -0500 Received: from mail-io1-xd41.google.com ([2607:f8b0:4864:20::d41]:41965) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ibnZ8-0000vJ-H2 for qemu-arm@nongnu.org; Mon, 02 Dec 2019 10:24:46 -0500 Received: by mail-io1-xd41.google.com with SMTP id z26so37454586iot.8 for ; Mon, 02 Dec 2019 07:24:46 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=QJOBjADfA+ccFaGnSH39XSvCu6Wstd7Jkr8Gx+Uryd8=; b=r9S8ttlOFu9FrNkNhafD22Ym2jqdHI7GqFoRxy0httgyf4nbuWCsksV0WtiKhZIjYx lB0mvqEv45ErC5LUI8zxMIEoyUtlQVXsnHmM4ZzkvnWjxefcvBshyWgNeK/B0z6FLbac fwtuAFo0TzHl81W54r+NjN/0G/2eLYMRxNZUDwqPGwnIBuP+TNxJXHEcA06kmXPBuvqJ P72NT+mFSDwBRctmy0+ZxYWSf76qdaNyOEGvFNXxMyiWz69iNpBXcnmqjbT2jp8AiplM 8fLaaWCqpbsl5u8ELyCVzGOfTdbPopLw/SnVnezQ5CVd1gqMzqbs7VxcXqD1RwFbvI/U nvyg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=QJOBjADfA+ccFaGnSH39XSvCu6Wstd7Jkr8Gx+Uryd8=; b=VX+YDKwRdf7h/eH80xbWAfLLPdqpkhY1LV+1WzvVZk+s525aZpuIwy5Ijo05gETHuc ugJhmXHnOeELtMJoMU/ydfkVTtG/7NcBv30gBxU2QZrdrZot9qkfZgZR1WrWFdzoI3PR cEutWhPCMiI5u1bqQU9OBFeKcS7gbZKRFBQ6hRwLpyBw6W/3g3vVXwZppOekHtJg7ipK zgirDkoe2ak3e2XCE4r2RcPOHcII0On/wm+x+ecfZgZZo4TVFCoomtDesQryc1bghBEw pLnfyJPyM06BK2aRLZYmJPxI4bKi9HXdqmiJKfP5B2sbuqlXOAYOQY+FGIV10KcEjSwV YEmg== X-Gm-Message-State: APjAAAUmM10OidqD0hOL0B3PHMAb+k/on4vovAo88n0fo8tdk2hT+5bY It2w6A9FBSjdGeMSgjZeIneLXmvk4jkx1n8aN2LzXw== X-Google-Smtp-Source: APXvYqzkuUkVr8fRB9we+E4pd5c/vS8aPDdLSHH0NksGaOdrLAMCkQ+geUqDgwt4zpyCP7oQdybke/iulnioqciO3wA= X-Received: by 2002:a5e:920a:: with SMTP id y10mr12339198iop.292.1575300285908; Mon, 02 Dec 2019 07:24:45 -0800 (PST) MIME-Version: 1.0 References: <20190904125531.27545-1-damien.hedde@greensocs.com> <20190904125531.27545-9-damien.hedde@greensocs.com> In-Reply-To: <20190904125531.27545-9-damien.hedde@greensocs.com> From: Peter Maydell Date: Mon, 2 Dec 2019 15:24:34 +0000 Message-ID: Subject: Re: [PATCH v6 8/9] hw/char/cadence_uart: add clock support To: Damien Hedde Cc: QEMU Developers , Mark Burton , "Edgar E. Iglesias" , Alistair Francis , =?UTF-8?B?TWFyYy1BbmRyw6kgTHVyZWF1?= , Paolo Bonzini , "Daniel P. Berrange" , Eduardo Habkost , qemu-arm , =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= Content-Type: text/plain; charset="UTF-8" X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::d41 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 02 Dec 2019 15:24:49 -0000 On Wed, 4 Sep 2019 at 13:56, Damien Hedde wrote: > > Switch the cadence uart to multi-phase reset and add the > reference clock input. > > The input clock frequency is added to the migration structure. > > The reference clock controls the baudrate generation. If it disabled, > any input characters and events are ignored. > > If this clock remains unconnected, the uart behaves as before > (it default to a 50MHz ref clock). > > Signed-off-by: Damien Hedde > static void uart_parameters_setup(CadenceUARTState *s) > { > QEMUSerialSetParams ssp; > - unsigned int baud_rate, packet_size; > + unsigned int baud_rate, packet_size, input_clk; > + input_clk = clock_get_frequency(s->refclk); > > - baud_rate = (s->r[R_MR] & UART_MR_CLKS) ? > - UART_INPUT_CLK / 8 : UART_INPUT_CLK; > + baud_rate = (s->r[R_MR] & UART_MR_CLKS) ? input_clk / 8 : input_clk; > + baud_rate /= (s->r[R_BRGR] * (s->r[R_BDIV] + 1)); > + trace_cadence_uart_baudrate(baud_rate); > + > + ssp.speed = baud_rate; > > - ssp.speed = baud_rate / (s->r[R_BRGR] * (s->r[R_BDIV] + 1)); > packet_size = 1; > > switch (s->r[R_MR] & UART_MR_PAR) { > @@ -215,6 +220,13 @@ static void uart_parameters_setup(CadenceUARTState *s) > } > > packet_size += ssp.data_bits + ssp.stop_bits; > + if (ssp.speed == 0) { > + /* > + * Avoid division-by-zero below. > + * TODO: find something better > + */ Any ideas what might be better? :-) > + ssp.speed = 1; > + } > s->char_tx_time = (NANOSECONDS_PER_SECOND / ssp.speed) * packet_size; > qemu_chr_fe_ioctl(&s->chr, CHR_IOCTL_SERIAL_SET_PARAMS, &ssp); > } thanks -- PMM From MAILER-DAEMON Mon Dec 02 10:34:25 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1ibniT-0004wy-Cj for mharc-qemu-arm@gnu.org; Mon, 02 Dec 2019 10:34:25 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:47050) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ibniQ-0004sK-Ko for qemu-arm@nongnu.org; Mon, 02 Dec 2019 10:34:23 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ibniP-0005bx-Eu for qemu-arm@nongnu.org; Mon, 02 Dec 2019 10:34:22 -0500 Received: from mail-il1-x141.google.com ([2607:f8b0:4864:20::141]:38450) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ibniP-0005b6-63 for qemu-arm@nongnu.org; Mon, 02 Dec 2019 10:34:21 -0500 Received: by mail-il1-x141.google.com with SMTP id u17so28001ilq.5 for ; Mon, 02 Dec 2019 07:34:20 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=yWx/sBpLVO3XZKtiD0Otn7MVG0ze2/ppcE5uUV2W2Ns=; b=u1qvsYpyp4OZju2Gl0iBTjdd38gaBQNK971DlKXb0RifqrI5Mxeycmn9xvIZECeF0E KVRSlnCe66vW7su6GM6qAR0XURQqecrxBMhab8RH9accCeGcngdWcskXvAQ6URUPPK25 bnBoHkZXlXoGi5fLZlptTeDYCk880OxIL1+t1udfWKILGOZiyClzN3ChiQxvhkXGXMIG 0+TzhH8lEnK+qsqmyGKhP3rUY15tCU7pGrsu05V6D3ikQMLbWlu+1jf/j24UdLShsclR cjQgacQtX9A3z+BBOLwJmwpuMM5jKSaHXbm6MuHW/GuaPRUykQ0Qmb1o98TKq38BIsuM Aayg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=yWx/sBpLVO3XZKtiD0Otn7MVG0ze2/ppcE5uUV2W2Ns=; b=hDqBVok3OHa7q2i7/bKwMjRLFddbbLMKjykPLKK6i2D8wOOT5VhWKSuswurplHEXPb Rf2uohaOuKdSoLm4QLwA49oJMEXjEa/KMj0HAfhPpNi92SP64C3w7DWd9qoVyU9532tl PW+XaZRuFrfCnQ6NRa9mFl6WoACGsTJWhYB/Pp1tQOhLT4fEfjUF5nmFRKts1G8f3yR1 9axnmI2EnEEQsHSFC2Ss+b0UtAS1LpAEK+fo0//5/shiTOCljWGMh7fYkgzlxFoLp5oB 7VPRUSeHEXF4cIwFvbMIuFHTnCTsSDjSTYU4ARrDVLk6fGjL74TotFNOf6PGAvgVAod6 +Z9Q== X-Gm-Message-State: APjAAAWKrRwnE8ZuZk4jos4fYMKYVk+Aml6DOc7bc55xoSxqPne8F7iE SqpCRDanF8fBB+NFFSEct9xZxovZd+KTRQwsHDbl9g== X-Google-Smtp-Source: APXvYqwNg5yYZGrgVw+hKzqyGiThnJXCrskDZLq+NX1JMfu1seuV6QgmDe/nYzTtN4IMXDa7IftCzAcbx/qmslpqLaA= X-Received: by 2002:a92:3d49:: with SMTP id k70mr15076543ila.246.1575300858807; Mon, 02 Dec 2019 07:34:18 -0800 (PST) MIME-Version: 1.0 References: <20190904125531.27545-1-damien.hedde@greensocs.com> <20190904125531.27545-10-damien.hedde@greensocs.com> In-Reply-To: <20190904125531.27545-10-damien.hedde@greensocs.com> From: Peter Maydell Date: Mon, 2 Dec 2019 15:34:07 +0000 Message-ID: Subject: Re: [PATCH v6 9/9] hw/arm/xilinx_zynq: connect uart clocks to slcr To: Damien Hedde Cc: QEMU Developers , Mark Burton , "Edgar E. Iglesias" , Alistair Francis , =?UTF-8?B?TWFyYy1BbmRyw6kgTHVyZWF1?= , Paolo Bonzini , "Daniel P. Berrange" , Eduardo Habkost , qemu-arm , =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= Content-Type: text/plain; charset="UTF-8" X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::141 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 02 Dec 2019 15:34:24 -0000 On Wed, 4 Sep 2019 at 13:56, Damien Hedde wrote: > > Add the connection between the slcr's output clocks and the uarts inputs. > > Also add the main board clock 'ps_clk', which is hard-coded to 33.33MHz > (the default frequency). This clock is used to feed the slcr's input > clock. > > Signed-off-by: Damien Hedde Nothing obviously wrong in the body of the patch, but as with 7 and 8, review from a Xilinx person would be helpful. /* board base frequency: 33.333333 MHz */ #define PS_CLK_FREQUENCY (100 * 1000 * 1000 / 3) This is interesting, because it's not an integer... I'll come back to this topic in a reply to the cover letter in a moment. thanks -- PMM From MAILER-DAEMON Mon Dec 02 11:08:09 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1iboF7-0001T3-A5 for mharc-qemu-arm@gnu.org; Mon, 02 Dec 2019 11:08:09 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:53127) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iboF4-0001Qt-GT for qemu-arm@nongnu.org; Mon, 02 Dec 2019 11:08:07 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1iboF3-0003I1-D3 for qemu-arm@nongnu.org; Mon, 02 Dec 2019 11:08:06 -0500 Received: from mail-pl1-x62d.google.com ([2607:f8b0:4864:20::62d]:44202) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1iboF3-0003HZ-7R for qemu-arm@nongnu.org; Mon, 02 Dec 2019 11:08:05 -0500 Received: by mail-pl1-x62d.google.com with SMTP id az9so99689plb.11 for ; Mon, 02 Dec 2019 08:08:04 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=subject:to:cc:references:from:message-id:date:user-agent :mime-version:in-reply-to:content-language:content-transfer-encoding; bh=N4iwl6gO27U0OW+8kRHtJsgDrHGzcB40YvGn9zm5cj8=; b=ZJYVyao3d2/IFEUV2y092K+jQvxIBdGEYQqmgDq9LDI2L/zGr5n8xcHAyMWkkaYjaP Uzkv2qhmTqcGJw238JRGnLT6R3ZWORi5RGqzsTn8M1tNnCV5tVPCzg88W/nxFRtfcmU6 YhM79gLe7RaT/LaJ9bvX4j8r/wMTSF4emub1cPmr2darKltN52m3+/0nhQvT+O0XDTPr CBXlAHiAJKJjCKQF0PytvsUgT0cAQBS4CCO5CSaZ4r2o1I/1vzLhGWKPKqSlakC93xo/ x4qKlrdTAKuxYq1reiX20UW8VpyXJYB+wRjkWNm7y6Yf4MqciXyNNAzm0AVtF9CkU53P a04w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:subject:to:cc:references:from:message-id:date :user-agent:mime-version:in-reply-to:content-language :content-transfer-encoding; bh=N4iwl6gO27U0OW+8kRHtJsgDrHGzcB40YvGn9zm5cj8=; b=prKihWgghTyPG+NibHEzycMNKYNxxFfsXspfzhWIj9M91nUhEGOUEamHriWszX0DQF qD7wji7hbyoy73ruY1cDAXmfE8PaX1tf4cIOVhYBD+z22/eLmYiFuth1iJv7oOilxYXs 3RMlqOUK5rzJZSbrNttutczCQKRB/cSu7sWUTGJF9IsBGUb3csN93ALg1bYLHuhuSS0o HqzAYUptgTwEoY/FHEfVWpdJEIMIxBNabBghg9QkSG7Zc+fO1VYO1k9PrWX5zvR4nZmu aA7/o8SBIMxK3WfhHrQ2Yd7HeNpDZizljOJMITrkXXAv2XKHcXs9oEmgdmW/PbIiT2bu Hu6g== X-Gm-Message-State: APjAAAX6daNyThco7e7KppONL79MZa08tfHMfmvvGQXcRDCY2VSk/S4G yt9GNQZNDCbrnK6VEVNh4xHNhA== X-Google-Smtp-Source: APXvYqwflwYRyJ+Z9qOLHBXUR9Jt31rtAB3K03oseTE7CEaieUOC46bo8mSdmXQxgCe8UAIWzvHaIA== X-Received: by 2002:a17:902:b70b:: with SMTP id d11mr27549776pls.48.1575302883800; Mon, 02 Dec 2019 08:08:03 -0800 (PST) Received: from [192.168.1.11] (97-113-7-119.tukw.qwest.net. [97.113.7.119]) by smtp.gmail.com with ESMTPSA id o124sm36352821pfb.56.2019.12.02.08.08.02 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 02 Dec 2019 08:08:03 -0800 (PST) Subject: Re: [PATCHv3] exynos4210_gic: Suppress gcc9 format-truncation warnings To: David Gibson , peter.maydell@linaro.org Cc: qemu-arm@nongnu.org, qemu-devel@nongnu.org, i.mitsyanko@gmail.com, =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= References: <20191202060806.77968-1-david@gibson.dropbear.id.au> From: Richard Henderson Message-ID: <8b490fbe-2b09-2a2c-16a8-6739ce6a847d@linaro.org> Date: Mon, 2 Dec 2019 08:08:00 -0800 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.2.1 MIME-Version: 1.0 In-Reply-To: <20191202060806.77968-1-david@gibson.dropbear.id.au> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 7bit X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::62d X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 02 Dec 2019 16:08:07 -0000 On 12/1/19 6:08 AM, David Gibson wrote: > > - for (i = 0; i < s->num_cpu; i++) { > + /* > + * This clues in gcc that our on-stack buffers do, in fact have > + * enough room for the cpu numbers. gcc 9.2.1 on 32-bit x86 > + * doesn't figure this out, otherwise and gives spurious warnings. > + */ > + assert(n <= EXYNOS4210_NCPUS); > + for (i = 0; i < n; i++) { > + > /* Map CPU interface per SMP Core */ Watch out for the extra line added at the start of the block. Otherwise, Reviewed-by: Richard Henderson r~ From MAILER-DAEMON Mon Dec 02 11:15:49 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1iboMX-0005OV-Op for mharc-qemu-arm@gnu.org; Mon, 02 Dec 2019 11:15:49 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:54081) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iboMT-0005NB-QT for qemu-arm@nongnu.org; Mon, 02 Dec 2019 11:15:47 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1iboMR-000751-LZ for qemu-arm@nongnu.org; Mon, 02 Dec 2019 11:15:45 -0500 Received: from mail-ot1-x344.google.com ([2607:f8b0:4864:20::344]:40766) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1iboMR-00074e-Fj for qemu-arm@nongnu.org; Mon, 02 Dec 2019 11:15:43 -0500 Received: by mail-ot1-x344.google.com with SMTP id i15so2164599oto.7 for ; Mon, 02 Dec 2019 08:15:42 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=2AOcNssktF6gqXIaJlj3n809rn2H9KnsBb75pdyNby8=; b=ocOh/xxRNzw6zKBgd02/XoLOKsbxhHZ5tT8Ut+vEoZPVBs+ZEXOVhITid5vNQCTnRP xNtYagt0E3VAlYf+ZMZ3rSUtBZpq74xQK9qZYMDC7uP5f8/zklCeSnIqmr1966DtQK2E o38GKC+euhBuz7F7Pb1qKmhaAz5F9FQN5CPyGUADiGGTNStNhNSfYGMrUWAs/sU7xadj SulcHUHvyRVGlhbhcIN0v3/VQGFQ1Rv/poXe4y8TgwJP5ACyGBaukoaRJr+WOgIKVGDK GK5BL4Du5S9/QuwhbOptqXCLnuR9vMS4zwr3yFBgm3dV87Ok9/sYBRha5zW4vtg2Hgcy GIRA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=2AOcNssktF6gqXIaJlj3n809rn2H9KnsBb75pdyNby8=; b=WUw7q7EMu1UOj4iArLTGBj9EAmYzjlYeuHTca6Vjy1eFuDkdtXcVZ5CTq6yCYEQbEm BT6bH+jF8sLtXtdIRlUH3bQcj1UWtHtFuZulVkHCuqO98g8ggufHXSGQhRXqay2+agLP tbVqan6F2aOEH0mO8aCeTYqPllDnVBEEmjCE/hYv6eogp/cSHwBCiV7zRv4ngARsRQ/a g4tvPacWSpBXZVObWrvyHW09yGnDWXnwR1OYTock9da1+neM6gz6KaxEsWNwYevJoqKe ZFluh8T2uQuEHGiao9iXiip/TIkmEpc4jZ0ybJnj/f27NW7vkAh1ffIdYL6ycfSm88V4 F72Q== X-Gm-Message-State: APjAAAVAWMjRMrU63CIvmMvwmVokA3+JvNlgn0lvZIypQEITUbAgo0n5 y45fuyvJtusG/pIl4NLeojtxje1Wsx+IM8W0FKvA3A== X-Google-Smtp-Source: APXvYqyvXIJYH8yj1inwPmL1uryBhuLkH68iQRRUo/FEj8QNkmJcNorE1yzSQcoNSxQZw3mhynxyAyro7tZpADOJxzo= X-Received: by 2002:a9d:6357:: with SMTP id y23mr22242219otk.91.1575303342083; Mon, 02 Dec 2019 08:15:42 -0800 (PST) MIME-Version: 1.0 References: <20190904125531.27545-1-damien.hedde@greensocs.com> In-Reply-To: <20190904125531.27545-1-damien.hedde@greensocs.com> From: Peter Maydell Date: Mon, 2 Dec 2019 16:15:30 +0000 Message-ID: Subject: Re: [PATCH v6 0/9] Clock framework API To: Damien Hedde Cc: QEMU Developers , Mark Burton , "Edgar E. Iglesias" , Alistair Francis , =?UTF-8?B?TWFyYy1BbmRyw6kgTHVyZWF1?= , Paolo Bonzini , "Daniel P. Berrange" , Eduardo Habkost , qemu-arm , =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= Content-Type: text/plain; charset="UTF-8" X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::344 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 02 Dec 2019 16:15:47 -0000 On Wed, 4 Sep 2019 at 13:56, Damien Hedde wrote: > > This series aims to add a way to model clock distribution in qemu. This allows > to model the clock tree of a platform allowing us to inspect clock > configuration and detect problems such as disabled clock or bad configured > pll. > > The added clock api is very similar the the gpio api for devices. We can add > input and output and connect them together. > > Very few changes since v5 in the core patches: we were waiting for multi phase > ability to allow proper initialization of the clock tree. So this is almost a > simple rebase on top of the current "Multi-phase reset mechanism" series. > Based-on: <20190821163341.16309-1-damien.hedde@greensocs.com> I've now gone through and given review comments on the patchset. I don't think there was anything particularly major -- overall I like the structure and API (and also the documentation!). The one topic I think we could do with discussing is whether a simple uint64_t giving the frequency of the clock in Hz is the right representation. In particular in your patch 9 the board has a clock frequency that's not a nice integer number of Hz. I think Philippe also mentioned on irc some board where the UART clock ends up at a weird frequency. Since the representation of the frequency is baked into the migration format it's going to be easier to get it right first rather than trying to change it later. So what should the representation be? Some random thoughts: 1) ptimer internally uses a 'period plus fraction' representation: int64_t period is the integer part of the period in nanoseconds, uint32_t period_frac is the fractional part of the period (if you like you can think of this as "96-bit integer period measured in units of one-2^32nd of a nanosecond"). However its only public interfaces for setting the frequency are (a) set the frequency in Hz (uint32_t) or (b) set the period in nanoseconds (int64_t); the period_frac part is used to handle frequencies which don't work out to a nice whole number of nanoseconds per cycle. 2) I hear that SystemC uses "value plus a time unit", with the smallest unit being a picosecond. (I think SystemC also lets you specify the duty cycle, but we definitely don't want to get into that!) 3) QEMUTimers are basically just nanosecond timers 4) The MAME emulator seems to work with periods of 96-bit attoseconds (represented internally by a 32-bit count of seconds plus a 64-bit count of attoseconds). One attosecond is 1e-18 seconds. Does anybody else have experience with other modelling or emulator technology and how it represents clocks ? I feel we should at least be able to represent clocks with the same accuracy that ptimer has. thanks -- PMM From MAILER-DAEMON Mon Dec 02 12:44:28 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1ibpkK-0003gC-Pi for mharc-qemu-arm@gnu.org; Mon, 02 Dec 2019 12:44:28 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:53745) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ibpkI-0003dX-K1 for qemu-arm@nongnu.org; Mon, 02 Dec 2019 12:44:27 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ibpkH-0002j2-9v for qemu-arm@nongnu.org; Mon, 02 Dec 2019 12:44:26 -0500 Received: from mail-oi1-x233.google.com ([2607:f8b0:4864:20::233]:36174) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ibpkH-0002iX-46 for qemu-arm@nongnu.org; Mon, 02 Dec 2019 12:44:25 -0500 Received: by mail-oi1-x233.google.com with SMTP id c16so455829oic.3 for ; Mon, 02 Dec 2019 09:44:23 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=L/OQceRW1bkzHkgGcsWhik4ob1xjBqqDcVG046qg/6Y=; b=Z8ItNsW7bscMSGPQWc0JXU04nSp7yhKKk1vE9CVN5X13FXakoGlaj2ELC9AlD2L6mI m5UF1I8rOvw+bIzBQ1ZXBOpM54OdCR2OdNhG3w9nMv2XDC4YKCO+/z1aruQQ1nwam5q8 Yp7nkttYvC6O1A891u5Tnf8StXHq+MiJ5Gtq490seNTbJvmJvIUkdZ/LbSKZts3L15EF jGGnj7Ei32iZnQe9q/y3t5V1OQGUOAiU46TUNQcOuYiJoDEJX+Yrv3cHF59LSeJu8O4b Z3p9BvYwYlUCs6PPM6Wmq4bsknUJwdiHyPG9hFKBLJ2fdnp7aNPBnygnjcVw6s4+AfnY /qvQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=L/OQceRW1bkzHkgGcsWhik4ob1xjBqqDcVG046qg/6Y=; b=jD2qklaHWJO7m5ynwkhWWiUTkvwqCbwBRWgCpSkdCRir9t1FBzj88Gbc6ARqlB6hEm uqSJGXGLCRYiBmS0JsooUX1HzEndRB/Jg8IHje2t6jgYPS7Av/fe725q+6BCh8YGkttN 9jwHnTsFwolpgo8R0gymC5mThCTjFl0fwhfxYl3va0tlnKo7nMWU139eIptc4VkyigMQ 796Fur2BNujyJVExYs4QMwpk1C9KYCoYddmR3ZaRA9dj6fqR8NLms9Q7knpQc1xTFJNX eJNcGnlc+ost1pO10okG6DSdRkmF31xjJLaDv/Zd1zZdla50m94dWXhRdRZCt1IXc/Ee VU3Q== X-Gm-Message-State: APjAAAXhOliTfTeO0rBOJyJhEykCzju0amrOdcCfMEX53snurN7fWamM PuHLCMg7Vh/QtgYRTgoCeCkcOA9YzygdCorVRO3Wgw== X-Google-Smtp-Source: APXvYqxQ/dnujMFsiApz3wCLmMfLWddpoFyB5tuTNsBb1qsDBycKeOaHMUec4fk3yJrm3+pXM6kaeovgTdmjjFWwZRY= X-Received: by 2002:aca:edd5:: with SMTP id l204mr198823oih.98.1575308662864; Mon, 02 Dec 2019 09:44:22 -0800 (PST) MIME-Version: 1.0 References: <20191202060806.77968-1-david@gibson.dropbear.id.au> <8b490fbe-2b09-2a2c-16a8-6739ce6a847d@linaro.org> In-Reply-To: <8b490fbe-2b09-2a2c-16a8-6739ce6a847d@linaro.org> From: Peter Maydell Date: Mon, 2 Dec 2019 17:44:11 +0000 Message-ID: Subject: Re: [PATCHv3] exynos4210_gic: Suppress gcc9 format-truncation warnings To: Richard Henderson Cc: David Gibson , qemu-arm , QEMU Developers , Igor Mitsyanko , =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= Content-Type: text/plain; charset="UTF-8" X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::233 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 02 Dec 2019 17:44:27 -0000 On Mon, 2 Dec 2019 at 16:08, Richard Henderson wrote: > > On 12/1/19 6:08 AM, David Gibson wrote: > > > > - for (i = 0; i < s->num_cpu; i++) { > > + /* > > + * This clues in gcc that our on-stack buffers do, in fact have > > + * enough room for the cpu numbers. gcc 9.2.1 on 32-bit x86 > > + * doesn't figure this out, otherwise and gives spurious warnings. > > + */ > > + assert(n <= EXYNOS4210_NCPUS); > > + for (i = 0; i < n; i++) { > > + > > /* Map CPU interface per SMP Core */ > > Watch out for the extra line added at the start of the block. Otherwise, > > Reviewed-by: Richard Henderson I thought about putting this in rc4 but eventually decided against it. Queued for 5.0 (with the stray extra blank line removed). thanks -- PMM From MAILER-DAEMON Mon Dec 02 13:09:23 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1ibq8R-0007I4-By for mharc-qemu-arm@gnu.org; Mon, 02 Dec 2019 13:09:23 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:58523) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ibq8I-0007Ff-PO for qemu-arm@nongnu.org; Mon, 02 Dec 2019 13:09:15 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ibq8H-0002J5-N2 for qemu-arm@nongnu.org; Mon, 02 Dec 2019 13:09:14 -0500 Received: from mail-pg1-x541.google.com ([2607:f8b0:4864:20::541]:35586) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ibq8H-0002Ik-FZ for qemu-arm@nongnu.org; Mon, 02 Dec 2019 13:09:13 -0500 Received: by mail-pg1-x541.google.com with SMTP id l24so47980pgk.2 for ; Mon, 02 Dec 2019 10:09:13 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=subject:to:cc:references:from:message-id:date:user-agent :mime-version:in-reply-to:content-language:content-transfer-encoding; bh=3i0gqRIZR7MOB9y3SV/8qk3Dk62rM1kFev6OWDH78cM=; b=QkJA3Wi3kkcLfdbzcYxgjfXrzEFTN9ytWm/VKpj/4nKOPvT7yFXiWYn+PhQSMW+zvC ouUAAtOkF5+DlHQETtgagHTp/uTFdCZcxbbzZiwqoT8zB9vErcWz8lzc0PBGDCl1fMU7 wIeh3jAcl7M972vWyDalsRso8qCMMZCvvksTGaKKRRg427I6Eg5h/pwkmdmso/xF9tbs JCRiYQyaqmv24HaLIpMgZAiVAaj5M5Ij7WX1j+hdPWPJj0cwQUTiyjPuSUwIJqucSWhG bcVijfTahx0x57HZkaTq1rB4Ykq7IC1io/dJBvpThUrkzHJWp2qW5CLiw1Z0TFFXGLfc CrdQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:subject:to:cc:references:from:message-id:date :user-agent:mime-version:in-reply-to:content-language :content-transfer-encoding; bh=3i0gqRIZR7MOB9y3SV/8qk3Dk62rM1kFev6OWDH78cM=; b=g0Dwyf1g5+gZVHSms7kBl2thiFJNPMUbU29ThLaKA+WRQTB4IcVMjIR0YgdfTwV7sP csq73tYJ1z3tbMQL791sNsmR0eaQZ0MPIWG5r9AyVFr2WNY6goOOY2GDRQ7U/BMeXEF8 GMlr13LhfejvCk7QU7zAsPUhp+Y7UF/KSgPAG6RuPezSLvrFYXdC1rmKQJkHg2UpMgkx tGXStqMVJ9rzuKw++B28kqaaH/MFDSgfZ8NjrOpVT8rBc81lE+RxNa3eOwoorfWtpsOS 04mzuFpZVIgiT2UpHYyAFlhbC0rQClitCFEV8bXfnnBgqwLjv2rLN/KgWLX36et9fnpS PQJw== X-Gm-Message-State: APjAAAUbp3Aa6S/XvvLsDdxYZol7bZCRMyZH8MR2+oNJFGUQDcTNnd6u 9lAiHpyIBBSvDVh03AmLebMeng== X-Google-Smtp-Source: APXvYqy8Lj5cOKGdaj4sYpeGH16BvGUTd8c6FTDR25i5Y6KRcAcCMeLfdDPvQQ91Fn3PS2ey1rMzbQ== X-Received: by 2002:a63:4946:: with SMTP id y6mr278236pgk.377.1575310152321; Mon, 02 Dec 2019 10:09:12 -0800 (PST) Received: from [192.168.1.11] (97-113-7-119.tukw.qwest.net. [97.113.7.119]) by smtp.gmail.com with ESMTPSA id d85sm128126pfd.146.2019.12.02.10.09.10 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 02 Dec 2019 10:09:11 -0800 (PST) Subject: Re: [PATCH 0/4] Expose GT CNTFRQ as a CPU property to support AST2600 To: Andrew Jeffery , qemu-arm@nongnu.org Cc: qemu-devel@nongnu.org, peter.maydell@linaro.org, clg@kaod.org, joel@jms.id.au References: <20191128054527.25450-1-andrew@aj.id.au> From: Richard Henderson Message-ID: <7aed21dd-a0f9-baf3-70e8-023dcd16ce6f@linaro.org> Date: Mon, 2 Dec 2019 10:09:09 -0800 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.2.1 MIME-Version: 1.0 In-Reply-To: <20191128054527.25450-1-andrew@aj.id.au> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 7bit X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::541 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 02 Dec 2019 18:09:16 -0000 On 11/27/19 5:45 AM, Andrew Jeffery wrote: > Andrew Jeffery (4): > target/arm: Remove redundant scaling of nexttick > target/arm: Abstract the generic timer frequency > target/arm: Prepare generic timer for per-platform CNTFRQ > ast2600: Configure CNTFRQ at 1125MHz Reviewed-by: Richard Henderson r~ From MAILER-DAEMON Mon Dec 02 13:13:06 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1ibqC1-0001Om-T0 for mharc-qemu-arm@gnu.org; Mon, 02 Dec 2019 13:13:05 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:59172) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ibqBz-0001OP-2u for qemu-arm@nongnu.org; Mon, 02 Dec 2019 13:13:04 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ibqBx-0003SS-To for qemu-arm@nongnu.org; Mon, 02 Dec 2019 13:13:02 -0500 Received: from mail-ot1-x342.google.com ([2607:f8b0:4864:20::342]:41713) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ibqBx-0003SE-No for qemu-arm@nongnu.org; Mon, 02 Dec 2019 13:13:01 -0500 Received: by mail-ot1-x342.google.com with SMTP id r27so309247otc.8 for ; Mon, 02 Dec 2019 10:13:01 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=q0xCx7uBW7RnFZp2fYdgddjrgqtvR0xZKFC397jatao=; b=mqdCKRBL4LeS089VRgIdzhvO8AS712WeVkOisGm/UNkw0z+351UWgrWnRBRQpJAJzX dEBkCX8KymTGbb+TT+1FEv4/ZYjZKaAxqDHXG6ZqVi2VQAeXCviBCg1tPN5Fp4svicFZ LfHcdvE+DXSjItGRbn/vvGTo509GiToS99vXO8968Y4ygox9yFSFvddJdi1xyuP6bXoh GbqiC0RznxtVGgQamy14za6+zyQTpXZn6pqf+/b/LcyE7GQZ6Qfr8K0iJ/HrwbNznH7Z jKpOfbSjLMkGZm43cRbdalaSmanxAuUxdPK2DzAsPkEYXWhZ+mlfTUyuRrZKCd2ylXKr HsJA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=q0xCx7uBW7RnFZp2fYdgddjrgqtvR0xZKFC397jatao=; b=Rr0JOp5nhTFFaAVH1gJ0aukC2Mlvq9/hK6r0miMQpMtaCeLBPKQwd+MA2i8UjWYYki j5piy69Uv36ZfkDFpqPH8vdxhqE4BHaj46Ynf1lxt8wl10To/3E5IOYWXqKsl3EqEh6g 7UmWoFII+/kVXMeg+gwC7A8sa7R4ZHpPx0npf6zL2U/UAv2aPXoHFzodwA/2HdhAmmKr R0OUtq7DrAyWznkmtgP4eu3M1FSlUorVsSQhc97HMpnJEjaE08GKzSsctTwGrIQUSj8a LFMy6vq/hTGbupYQlQ5BAYr6A6CqiK8jayAIE28pSWccAFov3WokGtuJX3dc4vyXV/++ hGsg== X-Gm-Message-State: APjAAAU6zk0Ad+cd3v3L5Ytvv169x9U1sPMTSYKNczo4kZp6QAdjBt9y fXJcBu9NNoS41V1gJiSf2QU2MKtBt3SyY+FViueN96UIPpA= X-Google-Smtp-Source: APXvYqwzU4Bmum6RYOKftwT6nG3fCLyxJDE0kESwp8ZWz2HydjQoRDT0uFGHYsCVI17Zj2vBckX9wy8113DS2wcy2Ao= X-Received: by 2002:a9d:6357:: with SMTP id y23mr272507otk.91.1575310380586; Mon, 02 Dec 2019 10:13:00 -0800 (PST) MIME-Version: 1.0 References: <20191128054527.25450-1-andrew@aj.id.au> <20191128054527.25450-3-andrew@aj.id.au> In-Reply-To: <20191128054527.25450-3-andrew@aj.id.au> From: Peter Maydell Date: Mon, 2 Dec 2019 18:12:49 +0000 Message-ID: Subject: Re: [PATCH 2/4] target/arm: Abstract the generic timer frequency To: Andrew Jeffery Cc: qemu-arm , =?UTF-8?Q?C=C3=A9dric_Le_Goater?= , Joel Stanley , QEMU Developers Content-Type: text/plain; charset="UTF-8" X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::342 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 02 Dec 2019 18:13:04 -0000 On Thu, 28 Nov 2019 at 05:44, Andrew Jeffery wrote: > > Prepare for SoCs such as the ASPEED AST2600 whose firmware configures > CNTFRQ to values significantly larger than the static 62.5MHz value > currently derived from GTIMER_SCALE. As the OS potentially derives its > timer periods from the CNTFRQ value the lack of support for running > QEMUTimers at the appropriate rate leads to sticky behaviour in the > guest. > > Substitute the GTIMER_SCALE constant with use of a helper to derive the > period from gt_cntfrq stored in struct ARMCPU. Initially set gt_cntfrq > to the frequency associated with GTIMER_SCALE so current behaviour is > maintained. > > Signed-off-by: Andrew Jeffery > +static inline unsigned int gt_cntfrq_period_ns(ARMCPU *cpu) > +{ > + /* XXX: Could include qemu/timer.h to get NANOSECONDS_PER_SECOND? */ > + const unsigned int ns_per_s = 1000 * 1000 * 1000; > + return ns_per_s > cpu->gt_cntfrq ? ns_per_s / cpu->gt_cntfrq : 1; > +} This function is named gt_cntfrq_period_ns()... > static uint64_t gt_virt_cnt_read(CPUARMState *env, const ARMCPRegInfo *ri) > { > + ARMCPU *cpu = env_archcpu(env); > + > /* Currently we have no support for QEMUTimer in linux-user so we > * can't call gt_get_countervalue(env), instead we directly > * call the lower level functions. > */ > - return cpu_get_clock() / GTIMER_SCALE; > + return cpu_get_clock() / gt_cntfrq_period(cpu); > } ...but here we call gt_cntfrq_period(), which doesn't exist, and indeed at least one of the patchew build systems reported it as a compile failure. thanks -- PMM From MAILER-DAEMON Mon Dec 02 13:22:22 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1ibqL0-0001L9-Rk for mharc-qemu-arm@gnu.org; Mon, 02 Dec 2019 13:22:22 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:60074) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ibqKy-0001JO-Uv for qemu-arm@nongnu.org; Mon, 02 Dec 2019 13:22:22 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ibqKx-0006aC-Ox for qemu-arm@nongnu.org; Mon, 02 Dec 2019 13:22:20 -0500 Received: from mail-oi1-x242.google.com ([2607:f8b0:4864:20::242]:36027) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ibqKx-0006ZE-BL for qemu-arm@nongnu.org; Mon, 02 Dec 2019 13:22:19 -0500 Received: by mail-oi1-x242.google.com with SMTP id c16so581330oic.3 for ; Mon, 02 Dec 2019 10:22:19 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=Mt0ebUCDlDgmkudTT+9hpvbvHuHkrX1tE7sw2iHLAt8=; b=gX4AoLyXiyO1zwgoVhMLAVZUSrYejSWLpTUCSkiBTM8KIGfGghefVqaLWftqvuy6Pj 4cuuh7ZuMbET9+Psx6/a854XuTdb/FIimeOv+hyIlMgKru2Z+gmys48h3M6bpd7qoo9S ofXdaDOv6K9Q7aqJGX5dIVqwOB1BkpeOLnfajgNaAq1lWHNwWHsbeX+qxUNwQrkaw7IV l0OBLF0KkTk+meKSgsBIoP0zg7mpiUegHM17p6gMhQsXdFTLCF/wxtN3J6eKS2ec8jk2 4TBtpVV9N/go9/UjgELqSmmQAQ9rNqyRMUgByISLZIzK99yXgFdKnM4GqV1aZa/UWhH4 j7Sw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=Mt0ebUCDlDgmkudTT+9hpvbvHuHkrX1tE7sw2iHLAt8=; b=g0T9MOzJziG9Aw8UpKJa0LlhVkXz2A8Yp31jadcmcD1UvlByEl44PhZKIVETLxwIAF 2qzkFGhpPYVp+809MCFjLoyec+of1JMkreH+js9H6UYVqQsahdhd//yNacuokRnc0J2x gzQOWPobzAaZ1pIWb6cpYwwhAcMCVU4MMMcoCWlF/nv/h8n4AxaB2kt1GLnG6U8L606D 45/sotpKrO1HypsypTp+duhbkICTtASdPflGwfKUlMPUZJSGTDhAAPrwnRPmQ4T8R9zo ZT2Ii8ojA/HzhsdJdA21uS4BVT12xzji+FQ2oIuQb2sxjKWhjsC68Sw1r4Ar8c6x7QKL 5pBw== X-Gm-Message-State: APjAAAX9dGeRpsk9IQNoa1pOQfNAhS7nRy8BuixC2M5FhdlKPkyFCu2k kAuyvu8UwrdiItopS40nVmNFieA++mk0EveMFzgGeg== X-Google-Smtp-Source: APXvYqyf9UhXEkFzj9oRHoU3UbqvOfk+HCMVWPzXh2Pv1uoa+7cfVmqFdqUILIrrmurrCqbtkC4dtlXxj6WLaa0+9Hc= X-Received: by 2002:aca:1a0a:: with SMTP id a10mr315133oia.146.1575310938470; Mon, 02 Dec 2019 10:22:18 -0800 (PST) MIME-Version: 1.0 References: <20191111014048.21296-1-zhengxiang9@huawei.com> <20191111014048.21296-2-zhengxiang9@huawei.com> In-Reply-To: <20191111014048.21296-2-zhengxiang9@huawei.com> From: Peter Maydell Date: Mon, 2 Dec 2019 18:22:07 +0000 Message-ID: Subject: Re: [RESEND PATCH v21 1/6] hw/arm/virt: Introduce a RAS machine option To: Xiang Zheng Cc: Paolo Bonzini , "Michael S. Tsirkin" , Igor Mammedov , Shannon Zhao , Laszlo Ersek , James Morse , gengdongjiu , Marcelo Tosatti , Richard Henderson , Eduardo Habkost , Jonathan Cameron , "xuwei (O)" , kvm-devel , QEMU Developers , qemu-arm , Linuxarm , wanghaibin.wang@huawei.com Content-Type: text/plain; charset="UTF-8" X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::242 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 02 Dec 2019 18:22:22 -0000 On Mon, 11 Nov 2019 at 01:44, Xiang Zheng wrote: > > From: Dongjiu Geng > > RAS Virtualization feature is not supported now, so add a RAS machine > option and disable it by default. > > Signed-off-by: Dongjiu Geng > Signed-off-by: Xiang Zheng > --- > hw/arm/virt.c | 23 +++++++++++++++++++++++ > include/hw/arm/virt.h | 1 + > 2 files changed, 24 insertions(+) > > diff --git a/hw/arm/virt.c b/hw/arm/virt.c > index d4bedc2607..ea0fbf82be 100644 > --- a/hw/arm/virt.c > +++ b/hw/arm/virt.c > @@ -1819,6 +1819,20 @@ static void virt_set_its(Object *obj, bool value, Error **errp) > vms->its = value; > } > > +static bool virt_get_ras(Object *obj, Error **errp) > +{ > + VirtMachineState *vms = VIRT_MACHINE(obj); > + > + return vms->ras; > +} > + > +static void virt_set_ras(Object *obj, bool value, Error **errp) > +{ > + VirtMachineState *vms = VIRT_MACHINE(obj); > + > + vms->ras = value; > +} > + > static char *virt_get_gic_version(Object *obj, Error **errp) > { > VirtMachineState *vms = VIRT_MACHINE(obj); > @@ -2122,6 +2136,15 @@ static void virt_instance_init(Object *obj) > "Valid values are none and smmuv3", > NULL); > > + /* Default disallows RAS instantiation */ > + vms->ras = false; > + object_property_add_bool(obj, "ras", virt_get_ras, > + virt_set_ras, NULL); > + object_property_set_description(obj, "ras", > + "Set on/off to enable/disable " > + "RAS instantiation", > + NULL); I think we could make the user-facing description of the option a little clearer: something like "Set on/off to enable/disable reporting host memory errors to a KVM guest using ACPI and guest external abort exceptions" ? Otherwise Reviewed-by: Peter Maydell thanks -- PMM From MAILER-DAEMON Mon Dec 02 13:24:11 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1ibqMl-0003ba-E1 for mharc-qemu-arm@gnu.org; Mon, 02 Dec 2019 13:24:11 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:60275) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ibqMi-0003Yu-Rl for qemu-arm@nongnu.org; Mon, 02 Dec 2019 13:24:09 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ibqMh-0008QK-V4 for qemu-arm@nongnu.org; Mon, 02 Dec 2019 13:24:08 -0500 Received: from mail-oi1-x243.google.com ([2607:f8b0:4864:20::243]:33438) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ibqMh-0008PX-RC for qemu-arm@nongnu.org; Mon, 02 Dec 2019 13:24:07 -0500 Received: by mail-oi1-x243.google.com with SMTP id v140so450138oie.0 for ; Mon, 02 Dec 2019 10:24:07 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=N6tE3Gl+YL/gnN9cI/JoRh0/ptDCZUGoGmUrLUqtfPA=; b=KIoVwB+g2xZRTRyivQl3lHKbHqDW7+fKT8JSbn9ycCIo5oC/NPXK98bIBiUDDtDmza CoLmCMwYaDlZMdg9wSmfCPNXy7UgAG4OUuggUlpiFbj3DZ689stO+gTD5I4pj4xea15t AB0ilFOUVV9UKBw/o5jiyrMKzPHp2W8Y4OHxM6j1dm3uFVJd14rpbrTsVetvVhOb7RVJ qN3E8lvvNc6DTa1LaUWkIpjx5iafhUyPevmaZIC8pTOg5dhlEMB0WHXW6WrQwDwlr6eE yD6/71+fz9AjiqA1MIVaqWd06m2BPuScvbh5hggXw+ia9dQCg/4q84kAX4Ov+hHkvmKp GR3A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=N6tE3Gl+YL/gnN9cI/JoRh0/ptDCZUGoGmUrLUqtfPA=; b=qd51gFeVDn3dgVKSnHXeWYmZEUrZ19UAGTy7upHTlFIpTt57u+yRLNseIidn6qKGCs M6pqZGH5pdIUUSA6mdcXj8R+cj69zsHcMws609HWpDRRFwWLQK91eBKiS+pimCdCe54X 1sx5lYXjxbH+BQXD4gHClWZHakxtP9JuyTHGgTf03afmPwfvIcIfYOp32XZ7W4xvtvyV ZE0GFa26+rA5cNcXeiRCjL75/q4ejEfTSu4rYquTJPErf1MIwLjq0y4sACMfv2pPmOa+ phaazQ85sCpwULjMj0aj67uv21o+oNtC45jxUaaro4p56FKrDy8BIyHN2JsvdOKH2yhI jGfg== X-Gm-Message-State: APjAAAW6VpUmq1ovPlQe9R2zfe6zIbOi8JXGwcrtQf3ILv5kmWFSXOrS nkFgY7+Je/FqFlkmeygTVW7HaWvAqnlCb4xtjK3v9A== X-Google-Smtp-Source: APXvYqw0vqAYx40bDkI5iYCYuymZq09hHslD8P+AVC8IjBFIdxz6qxqVUAusAje5nsc//jcgd/17CJBqsVxWqeUeD6o= X-Received: by 2002:aca:f484:: with SMTP id s126mr349470oih.48.1575311046960; Mon, 02 Dec 2019 10:24:06 -0800 (PST) MIME-Version: 1.0 References: <20191111014048.21296-1-zhengxiang9@huawei.com> <20191111014048.21296-5-zhengxiang9@huawei.com> In-Reply-To: <20191111014048.21296-5-zhengxiang9@huawei.com> From: Peter Maydell Date: Mon, 2 Dec 2019 18:23:56 +0000 Message-ID: Subject: Re: [RESEND PATCH v21 4/6] KVM: Move hwpoison page related functions into kvm-all.c To: Xiang Zheng Cc: Paolo Bonzini , "Michael S. Tsirkin" , Igor Mammedov , Shannon Zhao , Laszlo Ersek , James Morse , gengdongjiu , Marcelo Tosatti , Richard Henderson , Eduardo Habkost , Jonathan Cameron , "xuwei (O)" , kvm-devel , QEMU Developers , qemu-arm , Linuxarm , wanghaibin.wang@huawei.com Content-Type: text/plain; charset="UTF-8" X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::243 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 02 Dec 2019 18:24:09 -0000 On Mon, 11 Nov 2019 at 01:44, Xiang Zheng wrote: > > From: Dongjiu Geng > > kvm_hwpoison_page_add() and kvm_unpoison_all() will both be used by X86 > and ARM platforms, so moving them into "accel/kvm/kvm-all.c" to avoid > duplicate code. > > For architectures that don't use the poison-list functionality the > reset handler will harmlessly do nothing, so let's register the > kvm_unpoison_all() function in the generic kvm_init() function. > > Signed-off-by: Dongjiu Geng > Signed-off-by: Xiang Zheng Reviewed-by: Peter Maydell thanks -- PMM From MAILER-DAEMON Mon Dec 02 13:26:40 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1ibqPA-0004t0-3v for mharc-qemu-arm@gnu.org; Mon, 02 Dec 2019 13:26:40 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:60558) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ibqP6-0004rW-Sj for qemu-arm@nongnu.org; Mon, 02 Dec 2019 13:26:37 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ibqP5-0002Wz-T3 for qemu-arm@nongnu.org; Mon, 02 Dec 2019 13:26:36 -0500 Received: from mail-pj1-x1044.google.com ([2607:f8b0:4864:20::1044]:36231) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ibqP5-0002Vw-Ms for qemu-arm@nongnu.org; Mon, 02 Dec 2019 13:26:35 -0500 Received: by mail-pj1-x1044.google.com with SMTP id n96so93131pjc.3 for ; Mon, 02 Dec 2019 10:26:35 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=subject:to:cc:references:from:message-id:date:user-agent :mime-version:in-reply-to:content-language:content-transfer-encoding; bh=aGJgiHH9sd1ke5gnSsQDTZuuqeW60GiMKpvcK0Se2Rk=; b=wbFA0cfg9jMunP65qtn8Bc1FH2baEVFtUo6E4C01kcsKJxC0elBMKufSbMAB2XkjXz wud0TC3SiSK7UBncKEc33NmvO7psra0r0YiGk0oUrPJ1Svvj3bIVrkbtO8Opobh4L2Tk nAwUr1ON/flvPyhJhvwSX7WsXh7qb2Q/gOR0sniMxHauhp7eHiYnnjTdGsuRW79Q3x7X ISSHGE3HO58U0/DVAc19HhGAThNdvu71ze1SRoOGNgz34ojWyTl9adv6+06RmKtQ7MKM grmHzglvqWpG+BYbbDLAFzgoXHgh4FXqaYpRo72O2KuC8WPtaXOGwYCA52G8+cg3inNJ tJ1w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:subject:to:cc:references:from:message-id:date :user-agent:mime-version:in-reply-to:content-language :content-transfer-encoding; bh=aGJgiHH9sd1ke5gnSsQDTZuuqeW60GiMKpvcK0Se2Rk=; b=lZPA8FIQS/crLRSXQkXvT0hVhE694jM0kuk3iU/hZYIua8KDUHgzlngYKu92nUySpA gfevmwQesrtzVkQ+3oelbSs309nuy8+aVrWplzqKt+JebVhSd377IV9MAtc/yoNgNGob NZ3jqBHd3od+upwbbFq1cHKOYg4+yM8amf9MViLNN1+k8jXnYMNFdsBPQigLvWg3LJUk x7pl4HA3ZIsyrkZYJzC2O8QWFWu+3WlZTnnbTuFLMw6j3F6oEgj8hHks4uz61eLffnZz D6TytoSLPzPwMGHMLtrNCNt11ufX0lkH5LdtcjH7tTQ4du59xDYkm0oCEyc4DHE4Rha2 MJXQ== X-Gm-Message-State: APjAAAW1PuIJQqiSSnB/mOpX6Nq7p+vlrV62yLTdJTJo7Cmj+5Al1sPR rz+Kuxv/HI8W/rGfSzOkZoh+GzGESWA= X-Google-Smtp-Source: APXvYqw4rG2Z2KWwfgK5P1Z7QpqglitI/r7ECdLCnnd78swk7kYEyuyLpkH1LL9bL7967OKvVTsSxA== X-Received: by 2002:a17:902:104:: with SMTP id 4mr636294plb.130.1575311194391; Mon, 02 Dec 2019 10:26:34 -0800 (PST) Received: from [192.168.1.11] (97-113-7-119.tukw.qwest.net. [97.113.7.119]) by smtp.gmail.com with ESMTPSA id y3sm145344pfe.183.2019.12.02.10.26.33 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 02 Dec 2019 10:26:33 -0800 (PST) Subject: Re: [PATCH v2 09/14] target/arm: prepare for multiple dynamic XMLs To: =?UTF-8?Q?Alex_Benn=c3=a9e?= , qemu-devel@nongnu.org Cc: alan.hayward@arm.com, luis.machado@linaro.org, damien.hedde@greensocs.com, Peter Maydell , "open list:ARM TCG CPUs" References: <20191130084602.10818-1-alex.bennee@linaro.org> <20191130084602.10818-10-alex.bennee@linaro.org> From: Richard Henderson Message-ID: <7d088175-4b98-bd03-75db-f19b8a31bf8d@linaro.org> Date: Mon, 2 Dec 2019 10:26:31 -0800 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.2.1 MIME-Version: 1.0 In-Reply-To: <20191130084602.10818-10-alex.bennee@linaro.org> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 8bit X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::1044 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 02 Dec 2019 18:26:37 -0000 On 11/30/19 8:45 AM, Alex Bennée wrote: > We will want to generate similar dynamic XML for gdbstub support of > SVE registers (the upstream doesn't use XML). To that end lightly > rename a few things to make the distinction. > > Signed-off-by: Alex Bennée > --- > target/arm/cpu.h | 20 +++++++++++++------- > target/arm/gdbstub.c | 30 +++++++++++++++--------------- > target/arm/helper.c | 4 ++-- > 3 files changed, 30 insertions(+), 24 deletions(-) Reviewed-by: Richard Henderson r~ From MAILER-DAEMON Mon Dec 02 13:27:56 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1ibqQO-0005vy-Av for mharc-qemu-arm@gnu.org; Mon, 02 Dec 2019 13:27:56 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:60764) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ibqQL-0005qb-Sr for qemu-arm@nongnu.org; Mon, 02 Dec 2019 13:27:54 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ibqQK-0004Ye-OW for qemu-arm@nongnu.org; Mon, 02 Dec 2019 13:27:53 -0500 Received: from mail-oi1-x241.google.com ([2607:f8b0:4864:20::241]:43010) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ibqQK-0004Xp-KL for qemu-arm@nongnu.org; Mon, 02 Dec 2019 13:27:52 -0500 Received: by mail-oi1-x241.google.com with SMTP id l20so552691oie.10 for ; Mon, 02 Dec 2019 10:27:52 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=dP2JCQbWzYq+j6H+K0zSpsgH9pH8Yu2DiLKkze34i5c=; b=zXaEndRpo940BmNkNAkaG6vBp7FBhL5TWuQQlK2FC9TCYW/TZ0ynoQO+5wlTMTzXn6 bG4GbRuqtTqouOX40iBFMVnXfO7I/1g48C+2ag5kOYw4IG0s7mmbfrrWVZ5CJsfa+zqc Mdey985FaDxiu07xmI2G1Gz+8whe2ARv9+Qv7mdRxmcxEZiL6EbJ5QDPt/Pytv3f6bnD B2pJibyJzHzPvCnBY2/X9aKraz+F6iixJVPkEihesTLkgOydvd6ISSTReRoaPcfd22Vb CU1XSDlQefGLowhufDortNYAg872s+1ka5doOtHs4UVwWOu1s8f1EXdIgUK+/LOoKDHd Qsmg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=dP2JCQbWzYq+j6H+K0zSpsgH9pH8Yu2DiLKkze34i5c=; b=rC51FuFRV1MddQMFL8xTj0a8uS8wuKYi4aR702uf2otBbAY3yP8kSa3PkE2fKqkfUM FPE4y6o/mBCParWBbgt4miOG12otahN7Kqn3fBKc+VDziLh0cAvX/jy5KzEENpJ4w1Jt mVQGZZLqGaVO6kUZIV4ZA59M/zvtXUHvBDViKcypbF9G7zLjGIJSWh1wux9WdirMNUuj mcccKrRediAF6lQhEB8w4WLjRm35nA9CpJ0gfeRAAo8ov9Vql7d1U7CNyJAYCrUtrEli vM03Wc5ebSGO5AXBKzl4LQOrcvlVhOhElo0uG35HUnrezOMROQmlWCcNXc4Gdw/tB3lN D+Ew== X-Gm-Message-State: APjAAAWsWa+VUsLzcmlWZfAHHcYpfGzVs2J/2Pel5q/kVj2opmOn2nzZ vZmjE7506NX75o8Ov1eHss2Qldf+j+UDII4eDTiqNQ== X-Google-Smtp-Source: APXvYqzYkcr1K/kbJ9V5EeCHx+PRqgxp8GQzi/6Rw2Jb5q31RVmSbaRKDgbS1Q2W2/t69lWVMT1IcbklCE2EXW5NnY0= X-Received: by 2002:aca:edd5:: with SMTP id l204mr369787oih.98.1575311271706; Mon, 02 Dec 2019 10:27:51 -0800 (PST) MIME-Version: 1.0 References: <20191111014048.21296-1-zhengxiang9@huawei.com> In-Reply-To: <20191111014048.21296-1-zhengxiang9@huawei.com> From: Peter Maydell Date: Mon, 2 Dec 2019 18:27:40 +0000 Message-ID: Subject: Re: [RESEND PATCH v21 0/6] Add ARMv8 RAS virtualization support in QEMU To: Xiang Zheng Cc: Paolo Bonzini , "Michael S. Tsirkin" , Igor Mammedov , Shannon Zhao , Laszlo Ersek , James Morse , gengdongjiu , Marcelo Tosatti , Richard Henderson , Eduardo Habkost , Jonathan Cameron , "xuwei (O)" , kvm-devel , QEMU Developers , qemu-arm , Linuxarm , wanghaibin.wang@huawei.com Content-Type: text/plain; charset="UTF-8" X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::241 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 02 Dec 2019 18:27:55 -0000 On Mon, 11 Nov 2019 at 01:44, Xiang Zheng wrote: > > In the ARMv8 platform, the CPU error types are synchronous external abort(SEA) > and SError Interrupt (SEI). If exception happens in guest, sometimes it's better > for guest to perform the recovery, because host does not know the detailed > information of guest. For example, if an exception happens in a user-space > application within guest, host does not know which application encounters > errors. > > For the ARMv8 SEA/SEI, KVM or host kernel delivers SIGBUS to notify userspace. > After user space gets the notification, it will record the CPER into guest GHES > buffer and inject an exception or IRQ into guest. > > In the current implementation, if the type of SIGBUS is BUS_MCEERR_AR, we will > treat it as a synchronous exception, and notify guest with ARMv8 SEA > notification type after recording CPER into guest. Hi; I've given you reviewed-by tags on a couple of patches; other people have given review comments on some of the other patches, so I think you have enough to do a v22 addressing those. thanks -- PMM From MAILER-DAEMON Mon Dec 02 13:44:58 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1ibqgs-0006HE-D5 for mharc-qemu-arm@gnu.org; Mon, 02 Dec 2019 13:44:58 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:34661) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ibqgq-0006G1-14 for qemu-arm@nongnu.org; Mon, 02 Dec 2019 13:44:57 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ibqgo-0003Oj-Vx for qemu-arm@nongnu.org; Mon, 02 Dec 2019 13:44:55 -0500 Received: from mail-pl1-x641.google.com ([2607:f8b0:4864:20::641]:34787) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ibqgo-0003Nz-QR for qemu-arm@nongnu.org; Mon, 02 Dec 2019 13:44:54 -0500 Received: by mail-pl1-x641.google.com with SMTP id h13so315055plr.1 for ; Mon, 02 Dec 2019 10:44:53 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=subject:to:cc:references:from:message-id:date:user-agent :mime-version:in-reply-to:content-language:content-transfer-encoding; bh=HWDGnAwwg81AxYaByamp6Musnv8ydCk1iaAOmLWCwrE=; b=rSLWJGXb+1EonvOcABrla7OAsCYaMeVKhgbWx2DrzHkhqMhrA5ThHU3rjD1jCRemnL L8lDdlhmIJVoHMJzqk7zyWO8Ws6OuCV3Kgj/1nXz4QKckwPGdwVy/F5YkjeVacP6FXm3 IM8ZV60Sce4kYfUMdpeLahuiC1C26cAOsZgtRCR793Y7jnFzQidKZ8lcTWMknmo1GqpS FsZLTexy2ANHeb1Sh4Eurna5nf8wPblC8W1imp3KBsxJeUVFdEsFtz+D7fu+3+cj0ssh 7CjHWw4cG7zWfR3D1FuvmIrYjftYZDGeKp9hv1F0Un6qaBkuYlNm3sn5TJIn059svLS5 lHvA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:subject:to:cc:references:from:message-id:date :user-agent:mime-version:in-reply-to:content-language :content-transfer-encoding; bh=HWDGnAwwg81AxYaByamp6Musnv8ydCk1iaAOmLWCwrE=; b=Oj8kKuCqck6pHFia5iMFxnzaMp3zHiBqRwJA3z9R1ETr3LZWV5x8Qn38kEb8sNT+uv tzUQA/tBfMX+f5+iesfp/prNpSc102TGejyfzgPlQJhSkLS0qmYW7NvFRguCEG5rlp6u 9dRxuyrH39saOpoGZCVPd1yIXfEqSVfWHJvyg0sVJ4UWaAdoIaDs2fJyYYp6kRHSypMX S4JHx4GbFMp1QXHJW/T3oq13ju+J51zBI8pLIvcoQaBRktvTHtWo56FrEmJ/fOHjOIMD rq3Op1p52kUtLEaiZfxuOl8IwRLgJaS5JbNgO3ndmWXKZBLmI7yvzwmQmrhfHMlSLztO IsBA== X-Gm-Message-State: APjAAAWiCwx7Dayn74eHnwekSDzg6t6rlet0MHZGzYNWKSXCabptH5gz hzKgUPFJxFtf7WlkH/OAYjCguqvAwJM= X-Google-Smtp-Source: APXvYqwfGoV4Eei6umuPI1vB+vYJebvtTioHWlPD277zk+ea6P4XzzXOIzRXazT9wXW9z6tQ2ETiPQ== X-Received: by 2002:a17:902:7784:: with SMTP id o4mr672107pll.176.1575312292289; Mon, 02 Dec 2019 10:44:52 -0800 (PST) Received: from [192.168.1.11] (97-113-7-119.tukw.qwest.net. [97.113.7.119]) by smtp.gmail.com with ESMTPSA id d1sm213069pfo.31.2019.12.02.10.44.51 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 02 Dec 2019 10:44:51 -0800 (PST) Subject: Re: [PATCH v2 12/14] target/arm: generate xml description of our SVE registers To: =?UTF-8?Q?Alex_Benn=c3=a9e?= , qemu-devel@nongnu.org Cc: alan.hayward@arm.com, luis.machado@linaro.org, damien.hedde@greensocs.com, Peter Maydell , "open list:ARM TCG CPUs" References: <20191130084602.10818-1-alex.bennee@linaro.org> <20191130084602.10818-13-alex.bennee@linaro.org> From: Richard Henderson Message-ID: Date: Mon, 2 Dec 2019 10:44:49 -0800 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.2.1 MIME-Version: 1.0 In-Reply-To: <20191130084602.10818-13-alex.bennee@linaro.org> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 8bit X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::641 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 02 Dec 2019 18:44:57 -0000 On 11/30/19 8:46 AM, Alex Bennée wrote: > +struct TypeSize { > + const char *gdb_type; > + int size; > + const char sz, suffix; > +}; > + > +static struct TypeSize vec_lanes[] = { static const. > + for (bits = 128; bits >= 8; bits = bits/2) { Mind the spacing in the binary /, or bits /= 2. > +#ifdef TARGET_AARCH64 > +static int arm_gdb_get_svereg(CPUARMState *env, GByteArray *buf, int reg) > +{ > + ARMCPU *cpu = env_archcpu(env); > + DynamicGDBXMLInfo *info = &cpu->dyn_svereg_xml; > + > + /* The first 32 registers are the zregs */ > + if (reg < 32) { > + int vq, len = 0; > + for (vq = 0; vq < cpu->sve_max_vq; vq++) { > + len += gdb_get_reg128(buf, > + env->vfp.zregs[reg].d[vq * 2 + 1], > + env->vfp.zregs[reg].d[vq * 2]); > + } > + return len; This is tricky. The "standard" ordering of sve vectors is a stream of bytes, in little-endian ordering. This is how the hardware handles things, even in big-endian mode. I'm not sure how gdb is set up to handle this. Probably it doesn't matter for now, since almost no one uses BE, and can fixed later if needs be. > + case 2 ... 19: > + { > + int preg = reg - info->data.sve.fpsr_pos - 2; > + int vq, len = 0; > + for (vq = 0; vq < cpu->sve_max_vq; vq = vq + 4) { > + len += gdb_get_reg64(buf, env->vfp.pregs[preg].p[vq / 4]); > + } > + return len; > + } The byte ordering of the predicate registers is similar. This output does not appear to work for vq % 4 != 0. The vqp type is defined as a vector of uint16, so you'd need to output in units of reg16, extracted from the uint64_t as extract64(env->vfp.pregs[preg].p[vq / 4], vq % 4 * 16, 16); r~ From MAILER-DAEMON Mon Dec 02 16:38:02 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1ibtOM-0003w5-Bq for mharc-qemu-arm@gnu.org; Mon, 02 Dec 2019 16:38:02 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:38270) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ibsxg-0002hC-O7 for qemu-arm@nongnu.org; Mon, 02 Dec 2019 16:10:31 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ibsxa-0000kR-Ic for qemu-arm@nongnu.org; Mon, 02 Dec 2019 16:10:26 -0500 Received: from mail-wm1-x344.google.com ([2a00:1450:4864:20::344]:51722) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ibsxK-0000Yq-Fi; Mon, 02 Dec 2019 16:10:06 -0500 Received: by mail-wm1-x344.google.com with SMTP id g206so842287wme.1; Mon, 02 Dec 2019 13:10:01 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=h+Tla/hLm55CHAFtteEGlDuBFiTlLj9DvIB7CMAPe0U=; b=nrfGIqVqRbt7KSSVeD1gS+X4WPnrIyzuiRlPn3nEaqGL417jGLEWJZDYs9/6XbSpLF 5qB+iykwbGI4Y1wFOrjxWC1ELQWSXBhnYI33igURPxPI7CpybY/jV/L7nFbIJzNF3nlv 9BqNCEZ4vlhMwgRzwtABSDJ/5IoRGlEO54niMC0t634UvtrcMG7G1K1KC32otlIBveja 7VoB2smZ7SBVqXBP+uPM4Ay86xvq56uljkKe53yK6QI+NPaPYn33QTqlSO1uI3/ZG3b3 n7DmYkieRYnhx4Qa9cVA+foV+KYWDh4tGPEVxow6q3BfLQl2VIVpR2WtfALaPnUq8QWO sasA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=h+Tla/hLm55CHAFtteEGlDuBFiTlLj9DvIB7CMAPe0U=; b=JMQ0ubyAIoLl/whuu8u0hMt9H9W/ez544SRhTXw/JGxjBleTQEvYUAIX19BK66gKZ+ 1vegkSQDMpOiZViNoGX3No0iNI7VwpLbfWHCQ0wVo2TlczIgd+ynPAVk484SZ7SJIniF 1UF8OtlkmAuzEuFXYiD6pLn0Q57Dsdy/jluTRJkIqvcc/emW45kSj3fqNFVuW1w+gfJH xEqUe80aP44kROrijwTXI8MOlUnS+gAgPsPqc9SuJ1kcWQaLSj8RUuumeJ7bC4r6f4cE w1JQsnZTNpBAZiPCfBR0/jFWNKbNxkW6iXTFsJqwGhCJnFM07d7hdf/88IUiHGZgvMUY f8sQ== X-Gm-Message-State: APjAAAUXJt5r5f4Wf5KrnDLGnK2Oq1DSgjHWTPCC8VcCcLvS4ZgYtECN QAZcxQXZ5DBlXvp75mpbv/v08znf X-Google-Smtp-Source: APXvYqw19bYDiNd1ZTbVxqeeSMuDEmV5T0DCFA0fHOto5GoVwwhCpN0VpgyUmURETx8spDwc4DBYJg== X-Received: by 2002:a7b:cb87:: with SMTP id m7mr9521215wmi.148.1575320999594; Mon, 02 Dec 2019 13:09:59 -0800 (PST) Received: from pavilion.home ([2a02:a456:6be8:1:8edc:d4ff:fe8b:18b7]) by smtp.gmail.com with ESMTPSA id f1sm770859wrp.93.2019.12.02.13.09.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 02 Dec 2019 13:09:58 -0800 (PST) From: Niek Linnenbank To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, peter.maydell@linaro.org, b.galvani@gmail.com, Niek Linnenbank Subject: [PATCH 03/10] arm: allwinner-h3: add Clock Control Unit Date: Mon, 2 Dec 2019 22:09:40 +0100 Message-Id: <20191202210947.3603-4-nieklinnenbank@gmail.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20191202210947.3603-1-nieklinnenbank@gmail.com> References: <20191202210947.3603-1-nieklinnenbank@gmail.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::344 X-Mailman-Approved-At: Mon, 02 Dec 2019 16:38:01 -0500 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 02 Dec 2019 21:10:32 -0000 The Clock Control Unit is responsible for clock signal generation, configuration and distribution in the Allwinner H3 System on Chip. This commit adds support for the Clock Control Unit which emulates a simple read/write register interface. Signed-off-by: Niek Linnenbank --- hw/arm/allwinner-h3.c | 11 ++ hw/misc/Makefile.objs | 1 + hw/misc/allwinner-h3-clk.c | 227 +++++++++++++++++++++++++++++ include/hw/arm/allwinner-h3.h | 2 + include/hw/misc/allwinner-h3-clk.h | 41 ++++++ 5 files changed, 282 insertions(+) create mode 100644 hw/misc/allwinner-h3-clk.c create mode 100644 include/hw/misc/allwinner-h3-clk.h diff --git a/hw/arm/allwinner-h3.c b/hw/arm/allwinner-h3.c index 470fdfebef..5566e979ec 100644 --- a/hw/arm/allwinner-h3.c +++ b/hw/arm/allwinner-h3.c @@ -37,6 +37,9 @@ static void aw_h3_init(Object *obj) sysbus_init_child_obj(obj, "timer", &s->timer, sizeof(s->timer), TYPE_AW_A10_PIT); + + sysbus_init_child_obj(obj, "ccu", &s->ccu, sizeof(s->ccu), + TYPE_AW_H3_CLK); } static void aw_h3_realize(DeviceState *dev, Error **errp) @@ -172,6 +175,14 @@ static void aw_h3_realize(DeviceState *dev, Error **errp) memory_region_add_subregion(get_system_memory(), AW_H3_SRAM_C_BASE, &s->sram_c); + /* Clock Control Unit */ + object_property_set_bool(OBJECT(&s->ccu), true, "realized", &err); + if (err) { + error_propagate(errp, err); + return; + } + sysbus_mmio_map(SYS_BUS_DEVICE(&s->ccu), 0, AW_H3_CCU_BASE); + /* UART */ if (serial_hd(0)) { serial_mm_init(get_system_memory(), AW_H3_UART0_REG_BASE, 2, diff --git a/hw/misc/Makefile.objs b/hw/misc/Makefile.objs index ba898a5781..200ed44ce1 100644 --- a/hw/misc/Makefile.objs +++ b/hw/misc/Makefile.objs @@ -28,6 +28,7 @@ common-obj-$(CONFIG_MACIO) += macio/ common-obj-$(CONFIG_IVSHMEM_DEVICE) += ivshmem.o +common-obj-$(CONFIG_ALLWINNER_H3) += allwinner-h3-clk.o common-obj-$(CONFIG_REALVIEW) += arm_sysctl.o common-obj-$(CONFIG_NSERIES) += cbus.o common-obj-$(CONFIG_ECCMEMCTL) += eccmemctl.o diff --git a/hw/misc/allwinner-h3-clk.c b/hw/misc/allwinner-h3-clk.c new file mode 100644 index 0000000000..77c55b4f92 --- /dev/null +++ b/hw/misc/allwinner-h3-clk.c @@ -0,0 +1,227 @@ +/* + * Allwinner H3 Clock Control Unit emulation + * + * Copyright (C) 2019 Niek Linnenbank + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#include "qemu/osdep.h" +#include "hw/sysbus.h" +#include "migration/vmstate.h" +#include "qemu/log.h" +#include "qemu/module.h" +#include "hw/misc/allwinner-h3-clk.h" + +/* CCU register offsets */ +#define REG_PLL_CPUX (0x0000) /* PLL CPUX Control */ +#define REG_PLL_AUDIO (0x0008) /* PLL Audio Control */ +#define REG_PLL_VIDEO (0x0010) /* PLL Video Control */ +#define REG_PLL_VE (0x0018) /* PLL VE Control */ +#define REG_PLL_DDR (0x0020) /* PLL DDR Control */ +#define REG_PLL_PERIPH0 (0x0028) /* PLL Peripherals 0 Control */ +#define REG_PLL_GPU (0x0038) /* PLL GPU Control */ +#define REG_PLL_PERIPH1 (0x0044) /* PLL Peripherals 1 Control */ +#define REG_PLL_DE (0x0048) /* PLL Display Engine Control */ +#define REG_CPUX_AXI (0x0050) /* CPUX/AXI Configuration */ +#define REG_APB1 (0x0054) /* ARM Peripheral Bus 1 Config */ +#define REG_APB2 (0x0058) /* ARM Peripheral Bus 2 Config */ +#define REG_MBUS (0x00FC) /* MBUS Reset */ +#define REG_PLL_TIME0 (0x0200) /* PLL Stable Time 0 */ +#define REG_PLL_TIME1 (0x0204) /* PLL Stable Time 1 */ +#define REG_PLL_CPUX_BIAS (0x0220) /* PLL CPUX Bias */ +#define REG_PLL_AUDIO_BIAS (0x0224) /* PLL Audio Bias */ +#define REG_PLL_VIDEO_BIAS (0x0228) /* PLL Video Bias */ +#define REG_PLL_VE_BIAS (0x022C) /* PLL VE Bias */ +#define REG_PLL_DDR_BIAS (0x0230) /* PLL DDR Bias */ +#define REG_PLL_PERIPH0_BIAS (0x0234) /* PLL Peripherals 0 Bias */ +#define REG_PLL_GPU_BIAS (0x023C) /* PLL GPU Bias */ +#define REG_PLL_PERIPH1_BIAS (0x0244) /* PLL Peripherals 1 Bias */ +#define REG_PLL_DE_BIAS (0x0248) /* PLL Display Engine Bias */ +#define REG_PLL_CPUX_TUNING (0x0250) /* PLL CPUX Tuning */ +#define REG_PLL_DDR_TUNING (0x0260) /* PLL DDR Tuning */ +#define REG_INDEX(offset) (offset / sizeof(uint32_t)) + +/* CCU register flags */ +#define REG_PLL_ENABLE (1 << 31) +#define REG_PLL_LOCK (1 << 28) + +/* CCU register reset values */ +#define REG_PLL_CPUX_RST (0x00001000) +#define REG_PLL_AUDIO_RST (0x00035514) +#define REG_PLL_VIDEO_RST (0x03006207) +#define REG_PLL_VE_RST (0x03006207) +#define REG_PLL_DDR_RST (0x00001000) +#define REG_PLL_PERIPH0_RST (0x00041811) +#define REG_PLL_GPU_RST (0x03006207) +#define REG_PLL_PERIPH1_RST (0x00041811) +#define REG_PLL_DE_RST (0x03006207) +#define REG_CPUX_AXI_RST (0x00010000) +#define REG_APB1_RST (0x00001010) +#define REG_APB2_RST (0x01000000) +#define REG_MBUS_RST (0x80000000) +#define REG_PLL_TIME0_RST (0x000000FF) +#define REG_PLL_TIME1_RST (0x000000FF) +#define REG_PLL_CPUX_BIAS_RST (0x08100200) +#define REG_PLL_AUDIO_BIAS_RST (0x10100000) +#define REG_PLL_VIDEO_BIAS_RST (0x10100000) +#define REG_PLL_VE_BIAS_RST (0x10100000) +#define REG_PLL_DDR_BIAS_RST (0x81104000) +#define REG_PLL_PERIPH0_BIAS_RST (0x10100010) +#define REG_PLL_GPU_BIAS_RST (0x10100000) +#define REG_PLL_PERIPH1_BIAS_RST (0x10100010) +#define REG_PLL_DE_BIAS_RST (0x10100000) +#define REG_PLL_CPUX_TUNING_RST (0x0A101000) +#define REG_PLL_DDR_TUNING_RST (0x14880000) + +static uint64_t allwinner_h3_clk_read(void *opaque, hwaddr offset, + unsigned size) +{ + const AwH3ClockState *s = (AwH3ClockState *)opaque; + const uint32_t idx = REG_INDEX(offset); + + if (idx >= AW_H3_CLK_REGS_NUM) { + qemu_log_mask(LOG_GUEST_ERROR, "%s: bad read offset 0x%04x\n", + __func__, (uint32_t)offset); + return 0; + } + + return s->regs[idx]; +} + +static void allwinner_h3_clk_write(void *opaque, hwaddr offset, + uint64_t val, unsigned size) +{ + AwH3ClockState *s = (AwH3ClockState *)opaque; + const uint32_t idx = REG_INDEX(offset); + + if (idx >= AW_H3_CLK_REGS_NUM) { + qemu_log_mask(LOG_GUEST_ERROR, "%s: bad write offset 0x%04x\n", + __func__, (uint32_t)offset); + return; + } + + switch (offset) { + case REG_PLL_CPUX: /* PLL CPUX Control */ + case REG_PLL_AUDIO: /* PLL Audio Control */ + case REG_PLL_VIDEO: /* PLL Video Control */ + case REG_PLL_VE: /* PLL VE Control */ + case REG_PLL_DDR: /* PLL DDR Control */ + case REG_PLL_PERIPH0: /* PLL Peripherals 0 Control */ + case REG_PLL_GPU: /* PLL GPU Control */ + case REG_PLL_PERIPH1: /* PLL Peripherals 1 Control */ + case REG_PLL_DE: /* PLL Display Engine Control */ + if (val & REG_PLL_ENABLE) { + val |= REG_PLL_LOCK; + } + break; + default: + break; + } + + s->regs[idx] = (uint32_t) val; +} + +static const MemoryRegionOps allwinner_h3_clk_ops = { + .read = allwinner_h3_clk_read, + .write = allwinner_h3_clk_write, + .endianness = DEVICE_NATIVE_ENDIAN, + .valid = { + .min_access_size = 4, + .max_access_size = 4, + .unaligned = false + } +}; + +static void allwinner_h3_clk_reset(DeviceState *dev) +{ + AwH3ClockState *s = AW_H3_CLK(dev); + + /* Set default values for registers */ + s->regs[REG_INDEX(REG_PLL_CPUX)] = REG_PLL_CPUX_RST; + s->regs[REG_INDEX(REG_PLL_AUDIO)] = REG_PLL_AUDIO_RST; + s->regs[REG_INDEX(REG_PLL_VIDEO)] = REG_PLL_VIDEO_RST; + s->regs[REG_INDEX(REG_PLL_VE)] = REG_PLL_VE_RST; + s->regs[REG_INDEX(REG_PLL_DDR)] = REG_PLL_DDR_RST; + s->regs[REG_INDEX(REG_PLL_PERIPH0)] = REG_PLL_PERIPH0_RST; + s->regs[REG_INDEX(REG_PLL_GPU)] = REG_PLL_GPU_RST; + s->regs[REG_INDEX(REG_PLL_PERIPH1)] = REG_PLL_PERIPH1_RST; + s->regs[REG_INDEX(REG_PLL_DE)] = REG_PLL_DE_RST; + s->regs[REG_INDEX(REG_CPUX_AXI)] = REG_CPUX_AXI_RST; + s->regs[REG_INDEX(REG_APB1)] = REG_APB1_RST; + s->regs[REG_INDEX(REG_APB2)] = REG_APB2_RST; + s->regs[REG_INDEX(REG_MBUS)] = REG_MBUS_RST; + s->regs[REG_INDEX(REG_PLL_TIME0)] = REG_PLL_TIME0_RST; + s->regs[REG_INDEX(REG_PLL_TIME1)] = REG_PLL_TIME1_RST; + s->regs[REG_INDEX(REG_PLL_CPUX_BIAS)] = REG_PLL_CPUX_BIAS_RST; + s->regs[REG_INDEX(REG_PLL_AUDIO_BIAS)] = REG_PLL_AUDIO_BIAS_RST; + s->regs[REG_INDEX(REG_PLL_VIDEO_BIAS)] = REG_PLL_VIDEO_BIAS_RST; + s->regs[REG_INDEX(REG_PLL_VE_BIAS)] = REG_PLL_VE_BIAS_RST; + s->regs[REG_INDEX(REG_PLL_DDR_BIAS)] = REG_PLL_DDR_BIAS_RST; + s->regs[REG_INDEX(REG_PLL_PERIPH0_BIAS)] = REG_PLL_PERIPH0_BIAS_RST; + s->regs[REG_INDEX(REG_PLL_GPU_BIAS)] = REG_PLL_GPU_BIAS_RST; + s->regs[REG_INDEX(REG_PLL_PERIPH1_BIAS)] = REG_PLL_PERIPH1_BIAS_RST; + s->regs[REG_INDEX(REG_PLL_DE_BIAS)] = REG_PLL_DE_BIAS_RST; + s->regs[REG_INDEX(REG_PLL_CPUX_TUNING)] = REG_PLL_CPUX_TUNING_RST; + s->regs[REG_INDEX(REG_PLL_DDR_TUNING)] = REG_PLL_DDR_TUNING_RST; +} + +static void allwinner_h3_clk_realize(DeviceState *dev, Error **errp) +{ +} + +static void allwinner_h3_clk_init(Object *obj) +{ + SysBusDevice *sbd = SYS_BUS_DEVICE(obj); + AwH3ClockState *s = AW_H3_CLK(obj); + + /* Memory mapping */ + memory_region_init_io(&s->iomem, OBJECT(s), &allwinner_h3_clk_ops, s, + TYPE_AW_H3_CLK, AW_H3_CLK_REGS_MEM_SIZE); + sysbus_init_mmio(sbd, &s->iomem); +} + +static const VMStateDescription allwinner_h3_clk_vmstate = { + .name = TYPE_AW_H3_CLK, + .version_id = 1, + .minimum_version_id = 1, + .fields = (VMStateField[]) { + VMSTATE_UINT32_ARRAY(regs, AwH3ClockState, AW_H3_CLK_REGS_NUM), + VMSTATE_END_OF_LIST() + } +}; + +static void allwinner_h3_clk_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + + dc->reset = allwinner_h3_clk_reset; + dc->realize = allwinner_h3_clk_realize; + dc->vmsd = &allwinner_h3_clk_vmstate; +} + +static const TypeInfo allwinner_h3_clk_info = { + .name = TYPE_AW_H3_CLK, + .parent = TYPE_SYS_BUS_DEVICE, + .instance_init = allwinner_h3_clk_init, + .instance_size = sizeof(AwH3ClockState), + .class_init = allwinner_h3_clk_class_init, +}; + +static void allwinner_h3_clk_register(void) +{ + type_register_static(&allwinner_h3_clk_info); +} + +type_init(allwinner_h3_clk_register) diff --git a/include/hw/arm/allwinner-h3.h b/include/hw/arm/allwinner-h3.h index af368c2254..e596516c5c 100644 --- a/include/hw/arm/allwinner-h3.h +++ b/include/hw/arm/allwinner-h3.h @@ -26,6 +26,7 @@ #include "hw/arm/boot.h" #include "hw/timer/allwinner-a10-pit.h" #include "hw/intc/arm_gic.h" +#include "hw/misc/allwinner-h3-clk.h" #include "target/arm/cpu.h" #define AW_H3_SRAM_A1_BASE (0x00000000) @@ -109,6 +110,7 @@ typedef struct AwH3State { qemu_irq irq[AW_H3_GIC_NUM_SPI]; AwA10PITState timer; + AwH3ClockState ccu; GICState gic; MemoryRegion sram_a1; MemoryRegion sram_a2; diff --git a/include/hw/misc/allwinner-h3-clk.h b/include/hw/misc/allwinner-h3-clk.h new file mode 100644 index 0000000000..69ea559db1 --- /dev/null +++ b/include/hw/misc/allwinner-h3-clk.h @@ -0,0 +1,41 @@ +/* + * Allwinner H3 Clock Control Unit emulation + * + * Copyright (C) 2019 Niek Linnenbank + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#ifndef HW_MISC_ALLWINNER_H3_CLK_H +#define HW_MISC_ALLWINNER_H3_CLK_H + +#include "hw/sysbus.h" + +#define AW_H3_CLK_REGS_MAX_ADDR (0x304) +#define AW_H3_CLK_REGS_NUM (AW_H3_CLK_REGS_MAX_ADDR / sizeof(uint32_t)) +#define AW_H3_CLK_REGS_MEM_SIZE (1024) + +#define TYPE_AW_H3_CLK "allwinner-h3-clk" +#define AW_H3_CLK(obj) OBJECT_CHECK(AwH3ClockState, (obj), TYPE_AW_H3_CLK) + +typedef struct AwH3ClockState { + /*< private >*/ + SysBusDevice parent_obj; + /*< public >*/ + + MemoryRegion iomem; + uint32_t regs[AW_H3_CLK_REGS_NUM]; +} AwH3ClockState; + +#endif -- 2.17.1 From MAILER-DAEMON Mon Dec 02 16:38:03 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1ibtOM-0003w9-HV for mharc-qemu-arm@gnu.org; Mon, 02 Dec 2019 16:38:03 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:38608) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ibsxv-0002va-OS for qemu-arm@nongnu.org; Mon, 02 Dec 2019 16:10:46 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ibsxp-0000vH-Py for qemu-arm@nongnu.org; Mon, 02 Dec 2019 16:10:39 -0500 Received: from mail-wm1-x342.google.com ([2a00:1450:4864:20::342]:38631) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ibsxj-0000Zk-PN; Mon, 02 Dec 2019 16:10:32 -0500 Received: by mail-wm1-x342.google.com with SMTP id p17so1104582wmi.3; Mon, 02 Dec 2019 13:10:04 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=8lluLcXPi3hnYH6Ygv8lu4PnBF+2/P64LGe20+1b09Y=; b=IaaNGa/xTJJsau+FEd6bH3Orvmr7M2hmoP8N4NJOvvEdG5FBhAw7r5qoEF3O2E4oq4 T29F62P3aY/FBVASqu1vlTt6Y23w3xBZoaHA+6bPbx0NEssAcq1dNOqNcTLFVQWHHB53 rgX7XNIAV5m/TEsEpTVQyX//tVS0wpbPouzxhCtKtIbwFF1Bmu81qdlZQ9qDwGz8YL9q RGKFx2LyN3zHBWWRHuyq7Qj3rb6+TgNkcki6bcp97TNv6knjtjkVug0E7cG6lvsebw3n cVFtCATFktltFwI2eBDF7asFVTEr4jcRCp+Du+9fCYYx1s5wBTGF9hSKR0uIO9WhcLr/ adQw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=8lluLcXPi3hnYH6Ygv8lu4PnBF+2/P64LGe20+1b09Y=; b=Wq1okkFiPenTfcVusacAWlGnGr3n8T/DT2z2XgqO/56y2FUFX25TnkYy1f/N0Y2xTT rbV8tYwe0gsbx+HG79+fXASonCknMD8aBB7RNEI5ffQ8sGOdXA9JttQpLndXYvIqeUI9 aDOAWPEHKjC75vlxtle3+UIsPyHpkrMyXBnmrqi69ATKnYU5RkT9Il6aS5GwBwU2djfl ksnVGg5BKv0gmoZkz4D7BpM/5bv5QVE2WKNuWkhX4Jndq8IQ+YW0kZfChHkwaTIZhh7v krSfRGUYpE4TdV1ue6ihU2mco4aPQ/HKd8RhEUBrLtGju+jfQEzBpRGszRwqFDnBleWL oA/g== X-Gm-Message-State: APjAAAV2Dp9H9CXqhoRwzWM6XpJK85vgwliPAmd29ErrEIuwHeTOdzh6 6AOymjpBZvfR1w4aJUtZjLpgngQH X-Google-Smtp-Source: APXvYqytFB54mKI6R0m+7yMnJirBfUWuIzriMBd0azSgoDQMki+WNs15DxWXwzfcUHM7rH3SfeXAdw== X-Received: by 2002:a1c:a548:: with SMTP id o69mr30725863wme.31.1575321003600; Mon, 02 Dec 2019 13:10:03 -0800 (PST) Received: from pavilion.home ([2a02:a456:6be8:1:8edc:d4ff:fe8b:18b7]) by smtp.gmail.com with ESMTPSA id f1sm770859wrp.93.2019.12.02.13.10.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 02 Dec 2019 13:10:03 -0800 (PST) From: Niek Linnenbank To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, peter.maydell@linaro.org, b.galvani@gmail.com, Niek Linnenbank Subject: [PATCH 08/10] arm: allwinner-h3: add Security Identifier device Date: Mon, 2 Dec 2019 22:09:45 +0100 Message-Id: <20191202210947.3603-9-nieklinnenbank@gmail.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20191202210947.3603-1-nieklinnenbank@gmail.com> References: <20191202210947.3603-1-nieklinnenbank@gmail.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::342 X-Mailman-Approved-At: Mon, 02 Dec 2019 16:38:01 -0500 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 02 Dec 2019 21:10:46 -0000 The Security Identifier device in Allwinner H3 System on Chip gives applications a per-board unique identifier. This commit adds support for the Allwinner H3 Security Identifier using randomized data as input. Signed-off-by: Niek Linnenbank --- hw/arm/allwinner-h3.c | 11 ++ hw/misc/Makefile.objs | 1 + hw/misc/allwinner-h3-sid.c | 162 +++++++++++++++++++++++++++++ hw/misc/trace-events | 5 + include/hw/arm/allwinner-h3.h | 2 + include/hw/misc/allwinner-h3-sid.h | 42 ++++++++ 6 files changed, 223 insertions(+) create mode 100644 hw/misc/allwinner-h3-sid.c create mode 100644 include/hw/misc/allwinner-h3-sid.h diff --git a/hw/arm/allwinner-h3.c b/hw/arm/allwinner-h3.c index 44aba1de6a..4fc4c8c725 100644 --- a/hw/arm/allwinner-h3.c +++ b/hw/arm/allwinner-h3.c @@ -47,6 +47,9 @@ static void aw_h3_init(Object *obj) sysbus_init_child_obj(obj, "cpucfg", &s->cpucfg, sizeof(s->cpucfg), TYPE_AW_H3_CPUCFG); + + sysbus_init_child_obj(obj, "sid", &s->sid, sizeof(s->sid), + TYPE_AW_H3_SID); } static void aw_h3_realize(DeviceState *dev, Error **errp) @@ -206,6 +209,14 @@ static void aw_h3_realize(DeviceState *dev, Error **errp) } sysbus_mmio_map(SYS_BUS_DEVICE(&s->cpucfg), 0, AW_H3_CPUCFG_BASE); + /* Security Identifier */ + object_property_set_bool(OBJECT(&s->sid), true, "realized", &err); + if (err) { + error_propagate(errp, err); + return; + } + sysbus_mmio_map(SYS_BUS_DEVICE(&s->sid), 0, AW_H3_SID_BASE); + /* Universal Serial Bus */ sysbus_create_simple(TYPE_AW_H3_EHCI, AW_H3_EHCI0_BASE, s->irq[AW_H3_GIC_SPI_EHCI0]); diff --git a/hw/misc/Makefile.objs b/hw/misc/Makefile.objs index c4ca2ed689..f3620eee4e 100644 --- a/hw/misc/Makefile.objs +++ b/hw/misc/Makefile.objs @@ -31,6 +31,7 @@ common-obj-$(CONFIG_IVSHMEM_DEVICE) += ivshmem.o common-obj-$(CONFIG_ALLWINNER_H3) += allwinner-h3-clk.o obj-$(CONFIG_ALLWINNER_H3) += allwinner-h3-cpucfg.o common-obj-$(CONFIG_ALLWINNER_H3) += allwinner-h3-syscon.o +common-obj-$(CONFIG_ALLWINNER_H3) += allwinner-h3-sid.o common-obj-$(CONFIG_REALVIEW) += arm_sysctl.o common-obj-$(CONFIG_NSERIES) += cbus.o common-obj-$(CONFIG_ECCMEMCTL) += eccmemctl.o diff --git a/hw/misc/allwinner-h3-sid.c b/hw/misc/allwinner-h3-sid.c new file mode 100644 index 0000000000..e13e0d9887 --- /dev/null +++ b/hw/misc/allwinner-h3-sid.c @@ -0,0 +1,162 @@ +/* + * Allwinner H3 Security ID emulation + * + * Copyright (C) 2019 Niek Linnenbank + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#include "qemu/osdep.h" +#include "hw/sysbus.h" +#include "migration/vmstate.h" +#include "qemu/log.h" +#include "qemu/module.h" +#include "qemu/guest-random.h" +#include "qapi/error.h" +#include "hw/misc/allwinner-h3-sid.h" + +/* SID register offsets */ +#define REG_PRCTL (0x40) /* Control */ +#define REG_RDKEY (0x60) /* Read Key */ + +/* SID register flags */ +#define REG_PRCTL_WRITE (0x2) /* Unknown write flag */ +#define REG_PRCTL_OP_LOCK (0xAC) /* Lock operation */ + +static uint64_t allwinner_h3_sid_read(void *opaque, hwaddr offset, + unsigned size) +{ + const AwH3SidState *s = (AwH3SidState *)opaque; + uint64_t val = 0; + + switch (offset) { + case REG_PRCTL: /* Control */ + val = s->control; + break; + case REG_RDKEY: /* Read Key */ + val = s->rdkey; + break; + default: + qemu_log_mask(LOG_GUEST_ERROR, "%s: bad read offset 0x%04x\n", + __func__, (uint32_t)offset); + return 0; + } + + return val; +} + +static void allwinner_h3_sid_write(void *opaque, hwaddr offset, + uint64_t val, unsigned size) +{ + AwH3SidState *s = (AwH3SidState *)opaque; + + switch (offset) { + case REG_PRCTL: /* Control */ + s->control = val & ~(REG_PRCTL_WRITE); + if (!(s->control & REG_PRCTL_OP_LOCK)) { + uint32_t id = (s->control >> 16) / sizeof(uint32_t); + if (id < AW_H3_SID_NUM_IDS) { + s->rdkey = s->identifier[id]; + } + } + break; + case REG_RDKEY: /* Read Key */ + break; + default: + qemu_log_mask(LOG_GUEST_ERROR, "%s: bad write offset 0x%04x\n", + __func__, (uint32_t)offset); + break; + } +} + +static const MemoryRegionOps allwinner_h3_sid_ops = { + .read = allwinner_h3_sid_read, + .write = allwinner_h3_sid_write, + .endianness = DEVICE_NATIVE_ENDIAN, + .valid = { + .min_access_size = 4, + .max_access_size = 4, + .unaligned = false + } +}; + +static void allwinner_h3_sid_reset(DeviceState *dev) +{ + AwH3SidState *s = AW_H3_SID(dev); + Error *err = NULL; + + /* Set default values for registers */ + s->control = 0; + s->rdkey = 0; + + /* Initialize identifier data */ + for (int i = 0; i < AW_H3_SID_NUM_IDS; i++) { + s->identifier[i] = 0; + } + + if (qemu_guest_getrandom(s->identifier, sizeof(s->identifier), &err)) { + error_report_err(err); + } +} + +static void allwinner_h3_sid_realize(DeviceState *dev, Error **errp) +{ +} + +static void allwinner_h3_sid_init(Object *obj) +{ + SysBusDevice *sbd = SYS_BUS_DEVICE(obj); + AwH3SidState *s = AW_H3_SID(obj); + + /* Memory mapping */ + memory_region_init_io(&s->iomem, OBJECT(s), &allwinner_h3_sid_ops, s, + TYPE_AW_H3_SID, AW_H3_SID_REGS_MEM_SIZE); + sysbus_init_mmio(sbd, &s->iomem); +} + +static const VMStateDescription allwinner_h3_sid_vmstate = { + .name = TYPE_AW_H3_SID, + .version_id = 1, + .minimum_version_id = 1, + .fields = (VMStateField[]) { + VMSTATE_UINT32(control, AwH3SidState), + VMSTATE_UINT32(rdkey, AwH3SidState), + VMSTATE_UINT32_ARRAY(identifier, AwH3SidState, AW_H3_SID_NUM_IDS), + VMSTATE_END_OF_LIST() + } +}; + +static void allwinner_h3_sid_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + + dc->reset = allwinner_h3_sid_reset; + dc->realize = allwinner_h3_sid_realize; + dc->vmsd = &allwinner_h3_sid_vmstate; +} + +static const TypeInfo allwinner_h3_sid_info = { + .name = TYPE_AW_H3_SID, + .parent = TYPE_SYS_BUS_DEVICE, + .instance_init = allwinner_h3_sid_init, + .instance_size = sizeof(AwH3SidState), + .class_init = allwinner_h3_sid_class_init, +}; + +static void allwinner_h3_sid_register(void) +{ + type_register_static(&allwinner_h3_sid_info); +} + +type_init(allwinner_h3_sid_register) diff --git a/hw/misc/trace-events b/hw/misc/trace-events index 1deb1d08c1..5d8a95816a 100644 --- a/hw/misc/trace-events +++ b/hw/misc/trace-events @@ -1,5 +1,10 @@ # See docs/devel/tracing.txt for syntax documentation. +# allwinner-h3-cpucfg.c +allwinner_h3_cpucfg_cpu_reset(uint8_t cpu_id, uint32_t reset_addr) "H3-CPUCFG: cpu_reset: id %u, reset_addr 0x%08x" +allwinner_h3_cpucfg_read(uint64_t offset, uint64_t data, unsigned size) "H3-CPUCFG: read: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u" +allwinner_h3_cpucfg_write(uint64_t offset, uint64_t data, unsigned size) "H3-CPUCFG: write: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u" + # eccmemctl.c ecc_mem_writel_mer(uint32_t val) "Write memory enable 0x%08x" ecc_mem_writel_mdr(uint32_t val) "Write memory delay 0x%08x" diff --git a/include/hw/arm/allwinner-h3.h b/include/hw/arm/allwinner-h3.h index 374061b550..33602599eb 100644 --- a/include/hw/arm/allwinner-h3.h +++ b/include/hw/arm/allwinner-h3.h @@ -29,6 +29,7 @@ #include "hw/misc/allwinner-h3-clk.h" #include "hw/misc/allwinner-h3-cpucfg.h" #include "hw/misc/allwinner-h3-syscon.h" +#include "hw/misc/allwinner-h3-sid.h" #include "target/arm/cpu.h" #define AW_H3_SRAM_A1_BASE (0x00000000) @@ -115,6 +116,7 @@ typedef struct AwH3State { AwH3ClockState ccu; AwH3CpuCfgState cpucfg; AwH3SysconState syscon; + AwH3SidState sid; GICState gic; MemoryRegion sram_a1; MemoryRegion sram_a2; diff --git a/include/hw/misc/allwinner-h3-sid.h b/include/hw/misc/allwinner-h3-sid.h new file mode 100644 index 0000000000..359cc86dfc --- /dev/null +++ b/include/hw/misc/allwinner-h3-sid.h @@ -0,0 +1,42 @@ +/* + * Allwinner H3 Security ID emulation + * + * Copyright (C) 2019 Niek Linnenbank + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#ifndef HW_MISC_ALLWINNER_H3_SID_H +#define HW_MISC_ALLWINNER_H3_SID_H + +#include "hw/sysbus.h" + +#define AW_H3_SID_NUM_IDS (4) +#define AW_H3_SID_REGS_MEM_SIZE (1024) + +#define TYPE_AW_H3_SID "allwinner-h3-sid" +#define AW_H3_SID(obj) OBJECT_CHECK(AwH3SidState, (obj), TYPE_AW_H3_SID) + +typedef struct AwH3SidState { + /*< private >*/ + SysBusDevice parent_obj; + /*< public >*/ + + MemoryRegion iomem; + uint32_t control; + uint32_t rdkey; + uint32_t identifier[AW_H3_SID_NUM_IDS]; +} AwH3SidState; + +#endif -- 2.17.1 From MAILER-DAEMON Mon Dec 02 16:38:04 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1ibtOO-0003wu-0m for mharc-qemu-arm@gnu.org; Mon, 02 Dec 2019 16:38:04 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:38618) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ibsxv-0002vp-QR for qemu-arm@nongnu.org; Mon, 02 Dec 2019 16:10:48 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ibsxp-0000vO-Qn for qemu-arm@nongnu.org; Mon, 02 Dec 2019 16:10:41 -0500 Received: from mail-wm1-x342.google.com ([2a00:1450:4864:20::342]:33855) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ibsxc-0000aw-OK; Mon, 02 Dec 2019 16:10:27 -0500 Received: by mail-wm1-x342.google.com with SMTP id f4so776132wmj.1; Mon, 02 Dec 2019 13:10:06 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=FG2UWWMlSaxSuJKFPn2Bzn2BvM9nYHlOC0LTH9A/EEA=; b=mmEM1tcuBs1pApAkRW/Cs+IyRYZJHNvhCYySGcrz/cjA6wfqCZRnxI9gk6F0vWiMLB kLIIdvPM3vKLrUM6OeB8oAHcIJAksbVqFYU/gwHwNQu+g1fumxWAwck3B5Al2LVA2+ZC mseMqbt5UWRf8/Z1fLF3TuD5ebL0npanJ2SID5v4a+DQ5mhvH+wMpEGMN0+dhgOYlvRK VQzkVTiYjSbf32W+tWBnJ/dDfQ3hfc3B0i1NOhmfedoXTwQ+8V4RyPnBLx3EUJ7wsHgv 0DhyJP/yqIEULFpwfYlDMlnlfkeaUvhaa8E450dfzKIP12b8VQqWXACw5sVwt+1g2KVd 1W7w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=FG2UWWMlSaxSuJKFPn2Bzn2BvM9nYHlOC0LTH9A/EEA=; b=mThSlxNsltOENPvCGIiuQQRX2lCh/efSf6/51Jr/HOy0bwowr1dp68TqiQ5CbHBjmH H/zMcYozxmIChwlYhvb1E6BaJsNte4CApxYiNi5Fi9YOB6jhUA5yRqWiuIvhZIjn1EM1 /OuI1J00cghilD9KKcl9rsWcIHrgN3rXo2W57uvV57CHX7l861j5NyB7yRuzkDaSBBjk f1gnguUYedmEHeUfb2PanxU6/vEj+eLloJsNprsSZUO7acWk16Aob0zUjf0btGfXHY1G lvAPaVzLhEoIO0quMav96EwEYRvI6cKilOCKn74ftj6dQgoN1NFjPTLfdrHLhQWTxI0J fe2Q== X-Gm-Message-State: APjAAAXig0mFDnu4MMHRPItgEgV3Vq/QTAfJ+sK3yijMoScMafHMJcqI S2oJTV57XkLRYZZRxicvJ5e7EoOE X-Google-Smtp-Source: APXvYqxkUVQbysCp0r9yWIfoUfymPGWiSpWIKEPr2FcyhlKmKCgodGSk+l5hQBH8JNXYTGwfSuApsQ== X-Received: by 2002:a1c:f416:: with SMTP id z22mr29848831wma.72.1575321005043; Mon, 02 Dec 2019 13:10:05 -0800 (PST) Received: from pavilion.home ([2a02:a456:6be8:1:8edc:d4ff:fe8b:18b7]) by smtp.gmail.com with ESMTPSA id f1sm770859wrp.93.2019.12.02.13.10.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 02 Dec 2019 13:10:03 -0800 (PST) From: Niek Linnenbank To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, peter.maydell@linaro.org, b.galvani@gmail.com, Niek Linnenbank Subject: [PATCH 09/10] arm: allwinner-h3: add SD/MMC host controller Date: Mon, 2 Dec 2019 22:09:46 +0100 Message-Id: <20191202210947.3603-10-nieklinnenbank@gmail.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20191202210947.3603-1-nieklinnenbank@gmail.com> References: <20191202210947.3603-1-nieklinnenbank@gmail.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::342 X-Mailman-Approved-At: Mon, 02 Dec 2019 16:38:01 -0500 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 02 Dec 2019 21:10:48 -0000 The Allwinner H3 System on Chip contains an integrated storage controller for Secure Digital (SD) and Multi Media Card (MMC) interfaces. This commit adds support for the Allwinner H3 SD/MMC storage controller with the following emulated features: * DMA transfers * Direct FIFO I/O * Short/Long format command responses * Auto-Stop command (CMD12) * Insert & remove card detection Signed-off-by: Niek Linnenbank --- hw/arm/allwinner-h3.c | 20 + hw/arm/orangepi.c | 17 + hw/sd/Makefile.objs | 1 + hw/sd/allwinner-h3-sdhost.c | 791 ++++++++++++++++++++++++++++ hw/sd/trace-events | 7 + include/hw/arm/allwinner-h3.h | 2 + include/hw/sd/allwinner-h3-sdhost.h | 73 +++ 7 files changed, 911 insertions(+) create mode 100644 hw/sd/allwinner-h3-sdhost.c create mode 100644 include/hw/sd/allwinner-h3-sdhost.h diff --git a/hw/arm/allwinner-h3.c b/hw/arm/allwinner-h3.c index 4fc4c8c725..c2972caf88 100644 --- a/hw/arm/allwinner-h3.c +++ b/hw/arm/allwinner-h3.c @@ -50,6 +50,9 @@ static void aw_h3_init(Object *obj) sysbus_init_child_obj(obj, "sid", &s->sid, sizeof(s->sid), TYPE_AW_H3_SID); + + sysbus_init_child_obj(obj, "mmc0", &s->mmc0, sizeof(s->mmc0), + TYPE_AW_H3_SDHOST); } static void aw_h3_realize(DeviceState *dev, Error **errp) @@ -217,6 +220,23 @@ static void aw_h3_realize(DeviceState *dev, Error **errp) } sysbus_mmio_map(SYS_BUS_DEVICE(&s->sid), 0, AW_H3_SID_BASE); + /* SD/MMC */ + object_property_set_bool(OBJECT(&s->mmc0), true, "realized", &err); + if (err != NULL) { + error_propagate(errp, err); + return; + } + sysbusdev = SYS_BUS_DEVICE(&s->mmc0); + sysbus_mmio_map(sysbusdev, 0, AW_H3_MMC0_BASE); + sysbus_connect_irq(sysbusdev, 0, s->irq[AW_H3_GIC_SPI_MMC0]); + + object_property_add_alias(OBJECT(s), "sd-bus", OBJECT(&s->mmc0), + "sd-bus", &err); + if (err) { + error_propagate(errp, err); + return; + } + /* Universal Serial Bus */ sysbus_create_simple(TYPE_AW_H3_EHCI, AW_H3_EHCI0_BASE, s->irq[AW_H3_GIC_SPI_EHCI0]); diff --git a/hw/arm/orangepi.c b/hw/arm/orangepi.c index 5ef2735f81..dee3efaf08 100644 --- a/hw/arm/orangepi.c +++ b/hw/arm/orangepi.c @@ -39,6 +39,10 @@ typedef struct OrangePiState { static void orangepi_init(MachineState *machine) { OrangePiState *s = g_new(OrangePiState, 1); + DriveInfo *di; + BlockBackend *blk; + BusState *bus; + DeviceState *carddev; Error *err = NULL; s->h3 = AW_H3(object_new(TYPE_AW_H3)); @@ -64,6 +68,18 @@ static void orangepi_init(MachineState *machine) exit(1); } + /* Create and plug in the SD card */ + di = drive_get_next(IF_SD); + blk = di ? blk_by_legacy_dinfo(di) : NULL; + bus = qdev_get_child_bus(DEVICE(s->h3), "sd-bus"); + if (bus == NULL) { + error_report("No SD/MMC found in H3 object"); + exit(1); + } + carddev = qdev_create(bus, TYPE_SD_CARD); + qdev_prop_set_drive(carddev, "drive", blk, &error_fatal); + object_property_set_bool(OBJECT(carddev), true, "realized", &error_fatal); + /* RAM */ memory_region_allocate_system_memory(&s->sdram, NULL, "orangepi.ram", machine->ram_size); @@ -80,6 +96,7 @@ static void orangepi_machine_init(MachineClass *mc) { mc->desc = "Orange Pi PC"; mc->init = orangepi_init; + mc->block_default_type = IF_SD; mc->units_per_default_bus = 1; mc->min_cpus = AW_H3_NUM_CPUS; mc->max_cpus = AW_H3_NUM_CPUS; diff --git a/hw/sd/Makefile.objs b/hw/sd/Makefile.objs index a884c238df..e7cc5ab739 100644 --- a/hw/sd/Makefile.objs +++ b/hw/sd/Makefile.objs @@ -4,6 +4,7 @@ common-obj-$(CONFIG_SD) += sd.o core.o sdmmc-internal.o common-obj-$(CONFIG_SDHCI) += sdhci.o common-obj-$(CONFIG_SDHCI_PCI) += sdhci-pci.o +obj-$(CONFIG_ALLWINNER_H3) += allwinner-h3-sdhost.o obj-$(CONFIG_MILKYMIST) += milkymist-memcard.o obj-$(CONFIG_OMAP) += omap_mmc.o obj-$(CONFIG_PXA2XX) += pxa2xx_mmci.o diff --git a/hw/sd/allwinner-h3-sdhost.c b/hw/sd/allwinner-h3-sdhost.c new file mode 100644 index 0000000000..26e113a144 --- /dev/null +++ b/hw/sd/allwinner-h3-sdhost.c @@ -0,0 +1,791 @@ +/* + * Allwinner H3 SD Host Controller emulation + * + * Copyright (C) 2019 Niek Linnenbank + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#include "qemu/osdep.h" +#include "qemu/log.h" +#include "qemu/module.h" +#include "sysemu/blockdev.h" +#include "hw/irq.h" +#include "hw/sd/allwinner-h3-sdhost.h" +#include "migration/vmstate.h" +#include "trace.h" + +#define TYPE_AW_H3_SDHOST_BUS "allwinner-h3-sdhost-bus" +#define AW_H3_SDHOST_BUS(obj) \ + OBJECT_CHECK(SDBus, (obj), TYPE_AW_H3_SDHOST_BUS) + +/* SD Host register offsets */ +#define REG_SD_GCTL (0x00) /* Global Control */ +#define REG_SD_CKCR (0x04) /* Clock Control */ +#define REG_SD_TMOR (0x08) /* Timeout */ +#define REG_SD_BWDR (0x0C) /* Bus Width */ +#define REG_SD_BKSR (0x10) /* Block Size */ +#define REG_SD_BYCR (0x14) /* Byte Count */ +#define REG_SD_CMDR (0x18) /* Command */ +#define REG_SD_CAGR (0x1C) /* Command Argument */ +#define REG_SD_RESP0 (0x20) /* Response Zero */ +#define REG_SD_RESP1 (0x24) /* Response One */ +#define REG_SD_RESP2 (0x28) /* Response Two */ +#define REG_SD_RESP3 (0x2C) /* Response Three */ +#define REG_SD_IMKR (0x30) /* Interrupt Mask */ +#define REG_SD_MISR (0x34) /* Masked Interrupt Status */ +#define REG_SD_RISR (0x38) /* Raw Interrupt Status */ +#define REG_SD_STAR (0x3C) /* Status */ +#define REG_SD_FWLR (0x40) /* FIFO Water Level */ +#define REG_SD_FUNS (0x44) /* FIFO Function Select */ +#define REG_SD_DBGC (0x50) /* Debug Enable */ +#define REG_SD_A12A (0x58) /* Auto command 12 argument */ +#define REG_SD_NTSR (0x5C) /* SD NewTiming Set */ +#define REG_SD_SDBG (0x60) /* SD newTiming Set Debug */ +#define REG_SD_HWRST (0x78) /* Hardware Reset Register */ +#define REG_SD_DMAC (0x80) /* Internal DMA Controller Control */ +#define REG_SD_DLBA (0x84) /* Descriptor List Base Address */ +#define REG_SD_IDST (0x88) /* Internal DMA Controller Status */ +#define REG_SD_IDIE (0x8C) /* Internal DMA Controller IRQ Enable */ +#define REG_SD_THLDC (0x100) /* Card Threshold Control */ +#define REG_SD_DSBD (0x10C) /* eMMC DDR Start Bit Detection Control */ +#define REG_SD_RES_CRC (0x110) /* Response CRC from card/eMMC */ +#define REG_SD_DATA7_CRC (0x114) /* CRC Data 7 from card/eMMC */ +#define REG_SD_DATA6_CRC (0x118) /* CRC Data 6 from card/eMMC */ +#define REG_SD_DATA5_CRC (0x11C) /* CRC Data 5 from card/eMMC */ +#define REG_SD_DATA4_CRC (0x120) /* CRC Data 4 from card/eMMC */ +#define REG_SD_DATA3_CRC (0x124) /* CRC Data 3 from card/eMMC */ +#define REG_SD_DATA2_CRC (0x128) /* CRC Data 2 from card/eMMC */ +#define REG_SD_DATA1_CRC (0x12C) /* CRC Data 1 from card/eMMC */ +#define REG_SD_DATA0_CRC (0x130) /* CRC Data 0 from card/eMMC */ +#define REG_SD_CRC_STA (0x134) /* CRC status from card/eMMC during write */ +#define REG_SD_FIFO (0x200) /* Read/Write FIFO */ + +/* SD Host register flags */ +#define SD_GCTL_FIFO_AC_MOD (1 << 31) +#define SD_GCTL_DDR_MOD_SEL (1 << 10) +#define SD_GCTL_CD_DBC_ENB (1 << 8) +#define SD_GCTL_DMA_ENB (1 << 5) +#define SD_GCTL_INT_ENB (1 << 4) +#define SD_GCTL_DMA_RST (1 << 2) +#define SD_GCTL_FIFO_RST (1 << 1) +#define SD_GCTL_SOFT_RST (1 << 0) + +#define SD_CMDR_LOAD (1 << 31) +#define SD_CMDR_CLKCHANGE (1 << 21) +#define SD_CMDR_WRITE (1 << 10) +#define SD_CMDR_AUTOSTOP (1 << 12) +#define SD_CMDR_DATA (1 << 9) +#define SD_CMDR_RESPONSE_LONG (1 << 7) +#define SD_CMDR_RESPONSE (1 << 6) +#define SD_CMDR_CMDID_MASK (0x3f) + +#define SD_RISR_CARD_REMOVE (1 << 31) +#define SD_RISR_CARD_INSERT (1 << 30) +#define SD_RISR_AUTOCMD_DONE (1 << 14) +#define SD_RISR_DATA_COMPLETE (1 << 3) +#define SD_RISR_CMD_COMPLETE (1 << 2) +#define SD_RISR_NO_RESPONSE (1 << 1) + +#define SD_STAR_CARD_PRESENT (1 << 8) + +#define SD_IDST_SUM_RECEIVE_IRQ (1 << 8) +#define SD_IDST_RECEIVE_IRQ (1 << 1) +#define SD_IDST_TRANSMIT_IRQ (1 << 0) +#define SD_IDST_IRQ_MASK (SD_IDST_RECEIVE_IRQ | SD_IDST_TRANSMIT_IRQ | \ + SD_IDST_SUM_RECEIVE_IRQ) +#define SD_IDST_WR_MASK (0x3ff) + +/* SD Host register reset values */ +#define REG_SD_GCTL_RST (0x00000300) +#define REG_SD_CKCR_RST (0x0) +#define REG_SD_TMOR_RST (0xFFFFFF40) +#define REG_SD_BWDR_RST (0x0) +#define REG_SD_BKSR_RST (0x00000200) +#define REG_SD_BYCR_RST (0x00000200) +#define REG_SD_CMDR_RST (0x0) +#define REG_SD_CAGR_RST (0x0) +#define REG_SD_RESP_RST (0x0) +#define REG_SD_IMKR_RST (0x0) +#define REG_SD_MISR_RST (0x0) +#define REG_SD_RISR_RST (0x0) +#define REG_SD_STAR_RST (0x00000100) +#define REG_SD_FWLR_RST (0x000F0000) +#define REG_SD_FUNS_RST (0x0) +#define REG_SD_DBGC_RST (0x0) +#define REG_SD_A12A_RST (0x0000FFFF) +#define REG_SD_NTSR_RST (0x00000001) +#define REG_SD_SDBG_RST (0x0) +#define REG_SD_HWRST_RST (0x00000001) +#define REG_SD_DMAC_RST (0x0) +#define REG_SD_DLBA_RST (0x0) +#define REG_SD_IDST_RST (0x0) +#define REG_SD_IDIE_RST (0x0) +#define REG_SD_THLDC_RST (0x0) +#define REG_SD_DSBD_RST (0x0) +#define REG_SD_RES_CRC_RST (0x0) +#define REG_SD_DATA_CRC_RST (0x0) +#define REG_SD_CRC_STA_RST (0x0) +#define REG_SD_FIFO_RST (0x0) + +/* Data transfer descriptor for DMA */ +typedef struct TransferDescriptor { + uint32_t status; /* Status flags */ + uint32_t size; /* Data buffer size */ + uint32_t addr; /* Data buffer address */ + uint32_t next; /* Physical address of next descriptor */ +} TransferDescriptor; + +/* Data transfer descriptor flags */ +#define DESC_STATUS_HOLD (1 << 31) /* Set when descriptor is in use by DMA */ +#define DESC_STATUS_ERROR (1 << 30) /* Set when DMA transfer error occurred */ +#define DESC_STATUS_CHAIN (1 << 4) /* Indicates chained descriptor. */ +#define DESC_STATUS_FIRST (1 << 3) /* Set on the first descriptor */ +#define DESC_STATUS_LAST (1 << 2) /* Set on the last descriptor */ +#define DESC_STATUS_NOIRQ (1 << 1) /* Skip raising interrupt after transfer */ + +#define DESC_SIZE_MASK (0xfffffffc) + +static void aw_h3_sdhost_update_irq(AwH3SDHostState *s) +{ + uint32_t irq_en = s->global_ctl & SD_GCTL_INT_ENB; + uint32_t irq = irq_en ? s->irq_status & s->irq_mask : 0; + + trace_aw_h3_sdhost_update_irq(irq); + qemu_set_irq(s->irq, irq); +} + +static void aw_h3_sdhost_update_transfer_cnt(AwH3SDHostState *s, uint32_t bytes) +{ + if (s->transfer_cnt > bytes) { + s->transfer_cnt -= bytes; + } else { + s->transfer_cnt = 0; + } + + if (!s->transfer_cnt) { + s->irq_status |= SD_RISR_DATA_COMPLETE | SD_RISR_AUTOCMD_DONE; + } +} + +static void aw_h3_sdhost_set_inserted(DeviceState *dev, bool inserted) +{ + AwH3SDHostState *s = AW_H3_SDHOST(dev); + + trace_aw_h3_sdhost_set_inserted(inserted); + + if (inserted) { + s->irq_status |= SD_RISR_CARD_INSERT; + s->irq_status &= ~SD_RISR_CARD_REMOVE; + s->status |= SD_STAR_CARD_PRESENT; + } else { + s->irq_status &= ~SD_RISR_CARD_INSERT; + s->irq_status |= SD_RISR_CARD_REMOVE; + s->status &= ~SD_STAR_CARD_PRESENT; + } + + aw_h3_sdhost_update_irq(s); +} + +static void aw_h3_sdhost_send_command(AwH3SDHostState *s) +{ + SDRequest request; + uint8_t resp[16]; + int rlen; + + /* Auto clear load flag */ + s->command &= ~SD_CMDR_LOAD; + + /* Clock change does not actually interact with the SD bus */ + if (!(s->command & SD_CMDR_CLKCHANGE)) { + + /* Prepare request */ + request.cmd = s->command & SD_CMDR_CMDID_MASK; + request.arg = s->command_arg; + + /* Send request to SD bus */ + rlen = sdbus_do_command(&s->sdbus, &request, resp); + if (rlen < 0) { + goto error; + } + + /* If the command has a response, store it in the response registers */ + if ((s->command & SD_CMDR_RESPONSE)) { + if (rlen == 0 || + (rlen == 4 && (s->command & SD_CMDR_RESPONSE_LONG))) { + goto error; + } + if (rlen != 4 && rlen != 16) { + goto error; + } + if (rlen == 4) { + s->response[0] = ldl_be_p(&resp[0]); + s->response[1] = s->response[2] = s->response[3] = 0; + } else { + s->response[0] = ldl_be_p(&resp[12]); + s->response[1] = ldl_be_p(&resp[8]); + s->response[2] = ldl_be_p(&resp[4]); + s->response[3] = ldl_be_p(&resp[0]); + } + } + } + + /* Set interrupt status bits */ + s->irq_status |= SD_RISR_CMD_COMPLETE; + return; + +error: + s->irq_status |= SD_RISR_NO_RESPONSE; +} + +static void aw_h3_sdhost_auto_stop(AwH3SDHostState *s) +{ + /* + * The stop command (CMD12) ensures the SD bus + * returns to the transfer state. + */ + if ((s->command & SD_CMDR_AUTOSTOP) && (s->transfer_cnt == 0)) { + /* First save current command registers */ + uint32_t saved_cmd = s->command; + uint32_t saved_arg = s->command_arg; + + /* Prepare stop command (CMD12) */ + s->command &= ~SD_CMDR_CMDID_MASK; + s->command |= 12; /* CMD12 */ + s->command_arg = 0; + + /* Put the command on SD bus */ + aw_h3_sdhost_send_command(s); + + /* Restore command values */ + s->command = saved_cmd; + s->command_arg = saved_arg; + } +} + +static uint32_t aw_h3_sdhost_process_desc(AwH3SDHostState *s, + hwaddr desc_addr, + TransferDescriptor *desc, + bool is_write, uint32_t max_bytes) +{ + uint32_t num_done = 0; + uint32_t num_bytes = max_bytes; + uint8_t buf[1024]; + + /* Read descriptor */ + cpu_physical_memory_read(desc_addr, desc, sizeof(*desc)); + if (desc->size == 0) { + desc->size = 0xffff + 1; + } + if (desc->size < num_bytes) { + num_bytes = desc->size; + } + + trace_aw_h3_sdhost_process_desc(desc_addr, desc->size, is_write, max_bytes); + + while (num_done < num_bytes) { + /* Try to completely fill the local buffer */ + uint32_t buf_bytes = num_bytes - num_done; + if (buf_bytes > sizeof(buf)) { + buf_bytes = sizeof(buf); + } + + /* Write to SD bus */ + if (is_write) { + cpu_physical_memory_read((desc->addr & DESC_SIZE_MASK) + num_done, + buf, buf_bytes); + + for (uint32_t i = 0; i < buf_bytes; i++) { + sdbus_write_data(&s->sdbus, buf[i]); + } + + /* Read from SD bus */ + } else { + for (uint32_t i = 0; i < buf_bytes; i++) { + buf[i] = sdbus_read_data(&s->sdbus); + } + cpu_physical_memory_write((desc->addr & DESC_SIZE_MASK) + num_done, + buf, buf_bytes); + } + num_done += buf_bytes; + } + + /* Clear hold flag and flush descriptor */ + desc->status &= ~DESC_STATUS_HOLD; + cpu_physical_memory_write(desc_addr, desc, sizeof(*desc)); + + return num_done; +} + +static void aw_h3_sdhost_dma(AwH3SDHostState *s) +{ + TransferDescriptor desc; + hwaddr desc_addr = s->desc_base; + bool is_write = (s->command & SD_CMDR_WRITE); + uint32_t bytes_done = 0; + + /* Check if DMA can be performed */ + if (s->byte_count == 0 || s->block_size == 0 || + !(s->global_ctl & SD_GCTL_DMA_ENB)) { + return; + } + + /* + * For read operations, data must be available on the SD bus + * If not, it is an error and we should not act at all + */ + if (!is_write && !sdbus_data_ready(&s->sdbus)) { + return; + } + + /* Process the DMA descriptors until all data is copied */ + while (s->byte_count > 0) { + bytes_done = aw_h3_sdhost_process_desc(s, desc_addr, &desc, + is_write, s->byte_count); + aw_h3_sdhost_update_transfer_cnt(s, bytes_done); + + if (bytes_done <= s->byte_count) { + s->byte_count -= bytes_done; + } else { + s->byte_count = 0; + } + + if (desc.status & DESC_STATUS_LAST) { + break; + } else { + desc_addr = desc.next; + } + } + + /* Raise IRQ to signal DMA is completed */ + s->irq_status |= SD_RISR_DATA_COMPLETE | SD_RISR_AUTOCMD_DONE; + + /* Update DMAC bits */ + if (is_write) { + s->dmac_status |= SD_IDST_TRANSMIT_IRQ; + } else { + s->dmac_status |= (SD_IDST_SUM_RECEIVE_IRQ | SD_IDST_RECEIVE_IRQ); + } +} + +static uint64_t aw_h3_sdhost_read(void *opaque, hwaddr offset, + unsigned size) +{ + AwH3SDHostState *s = (AwH3SDHostState *)opaque; + uint32_t res = 0; + + switch (offset) { + case REG_SD_GCTL: /* Global Control */ + res = s->global_ctl; + break; + case REG_SD_CKCR: /* Clock Control */ + res = s->clock_ctl; + break; + case REG_SD_TMOR: /* Timeout */ + res = s->timeout; + break; + case REG_SD_BWDR: /* Bus Width */ + res = s->bus_width; + break; + case REG_SD_BKSR: /* Block Size */ + res = s->block_size; + break; + case REG_SD_BYCR: /* Byte Count */ + res = s->byte_count; + break; + case REG_SD_CMDR: /* Command */ + res = s->command; + break; + case REG_SD_CAGR: /* Command Argument */ + res = s->command_arg; + break; + case REG_SD_RESP0: /* Response Zero */ + res = s->response[0]; + break; + case REG_SD_RESP1: /* Response One */ + res = s->response[1]; + break; + case REG_SD_RESP2: /* Response Two */ + res = s->response[2]; + break; + case REG_SD_RESP3: /* Response Three */ + res = s->response[3]; + break; + case REG_SD_IMKR: /* Interrupt Mask */ + res = s->irq_mask; + break; + case REG_SD_MISR: /* Masked Interrupt Status */ + res = s->irq_status & s->irq_mask; + break; + case REG_SD_RISR: /* Raw Interrupt Status */ + res = s->irq_status; + break; + case REG_SD_STAR: /* Status */ + res = s->status; + break; + case REG_SD_FWLR: /* FIFO Water Level */ + res = s->fifo_wlevel; + break; + case REG_SD_FUNS: /* FIFO Function Select */ + res = s->fifo_func_sel; + break; + case REG_SD_DBGC: /* Debug Enable */ + res = s->debug_enable; + break; + case REG_SD_A12A: /* Auto command 12 argument */ + res = s->auto12_arg; + break; + case REG_SD_NTSR: /* SD NewTiming Set */ + res = s->newtiming_set; + break; + case REG_SD_SDBG: /* SD newTiming Set Debug */ + res = s->newtiming_debug; + break; + case REG_SD_HWRST: /* Hardware Reset Register */ + res = s->hardware_rst; + break; + case REG_SD_DMAC: /* Internal DMA Controller Control */ + res = s->dmac; + break; + case REG_SD_DLBA: /* Descriptor List Base Address */ + res = s->desc_base; + break; + case REG_SD_IDST: /* Internal DMA Controller Status */ + res = s->dmac_status; + break; + case REG_SD_IDIE: /* Internal DMA Controller Interrupt Enable */ + res = s->dmac_irq; + break; + case REG_SD_THLDC: /* Card Threshold Control */ + res = s->card_threshold; + break; + case REG_SD_DSBD: /* eMMC DDR Start Bit Detection Control */ + res = s->startbit_detect; + break; + case REG_SD_RES_CRC: /* Response CRC from card/eMMC */ + res = s->response_crc; + break; + case REG_SD_DATA7_CRC: /* CRC Data 7 from card/eMMC */ + case REG_SD_DATA6_CRC: /* CRC Data 6 from card/eMMC */ + case REG_SD_DATA5_CRC: /* CRC Data 5 from card/eMMC */ + case REG_SD_DATA4_CRC: /* CRC Data 4 from card/eMMC */ + case REG_SD_DATA3_CRC: /* CRC Data 3 from card/eMMC */ + case REG_SD_DATA2_CRC: /* CRC Data 2 from card/eMMC */ + case REG_SD_DATA1_CRC: /* CRC Data 1 from card/eMMC */ + case REG_SD_DATA0_CRC: /* CRC Data 0 from card/eMMC */ + res = s->data_crc[((offset - REG_SD_DATA7_CRC) / sizeof(uint32_t))]; + break; + case REG_SD_CRC_STA: /* CRC status from card/eMMC in write operation */ + res = s->status_crc; + break; + case REG_SD_FIFO: /* Read/Write FIFO */ + if (sdbus_data_ready(&s->sdbus)) { + res = sdbus_read_data(&s->sdbus); + res |= sdbus_read_data(&s->sdbus) << 8; + res |= sdbus_read_data(&s->sdbus) << 16; + res |= sdbus_read_data(&s->sdbus) << 24; + aw_h3_sdhost_update_transfer_cnt(s, sizeof(uint32_t)); + aw_h3_sdhost_auto_stop(s); + aw_h3_sdhost_update_irq(s); + } else { + qemu_log_mask(LOG_GUEST_ERROR, "%s: no data ready on SD bus\n", + __func__); + } + break; + default: + qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset %"HWADDR_PRIx"\n", + __func__, offset); + res = 0; + break; + } + + trace_aw_h3_sdhost_read(offset, res, size); + return res; +} + +static void aw_h3_sdhost_write(void *opaque, hwaddr offset, + uint64_t value, unsigned size) +{ + AwH3SDHostState *s = (AwH3SDHostState *)opaque; + + trace_aw_h3_sdhost_write(offset, value, size); + + switch (offset) { + case REG_SD_GCTL: /* Global Control */ + s->global_ctl = value; + s->global_ctl &= ~(SD_GCTL_DMA_RST | SD_GCTL_FIFO_RST | + SD_GCTL_SOFT_RST); + aw_h3_sdhost_update_irq(s); + break; + case REG_SD_CKCR: /* Clock Control */ + s->clock_ctl = value; + break; + case REG_SD_TMOR: /* Timeout */ + s->timeout = value; + break; + case REG_SD_BWDR: /* Bus Width */ + s->bus_width = value; + break; + case REG_SD_BKSR: /* Block Size */ + s->block_size = value; + break; + case REG_SD_BYCR: /* Byte Count */ + s->byte_count = value; + s->transfer_cnt = value; + break; + case REG_SD_CMDR: /* Command */ + s->command = value; + if (value & SD_CMDR_LOAD) { + aw_h3_sdhost_send_command(s); + aw_h3_sdhost_dma(s); + aw_h3_sdhost_auto_stop(s); + } + aw_h3_sdhost_update_irq(s); + break; + case REG_SD_CAGR: /* Command Argument */ + s->command_arg = value; + break; + case REG_SD_RESP0: /* Response Zero */ + s->response[0] = value; + break; + case REG_SD_RESP1: /* Response One */ + s->response[1] = value; + break; + case REG_SD_RESP2: /* Response Two */ + s->response[2] = value; + break; + case REG_SD_RESP3: /* Response Three */ + s->response[3] = value; + break; + case REG_SD_IMKR: /* Interrupt Mask */ + s->irq_mask = value; + aw_h3_sdhost_update_irq(s); + break; + case REG_SD_MISR: /* Masked Interrupt Status */ + case REG_SD_RISR: /* Raw Interrupt Status */ + s->irq_status &= ~value; + aw_h3_sdhost_update_irq(s); + break; + case REG_SD_STAR: /* Status */ + s->status &= ~value; + aw_h3_sdhost_update_irq(s); + break; + case REG_SD_FWLR: /* FIFO Water Level */ + s->fifo_wlevel = value; + break; + case REG_SD_FUNS: /* FIFO Function Select */ + s->fifo_func_sel = value; + break; + case REG_SD_DBGC: /* Debug Enable */ + s->debug_enable = value; + break; + case REG_SD_A12A: /* Auto command 12 argument */ + s->auto12_arg = value; + break; + case REG_SD_NTSR: /* SD NewTiming Set */ + s->newtiming_set = value; + break; + case REG_SD_SDBG: /* SD newTiming Set Debug */ + s->newtiming_debug = value; + break; + case REG_SD_HWRST: /* Hardware Reset Register */ + s->hardware_rst = value; + break; + case REG_SD_DMAC: /* Internal DMA Controller Control */ + s->dmac = value; + aw_h3_sdhost_update_irq(s); + break; + case REG_SD_DLBA: /* Descriptor List Base Address */ + s->desc_base = value; + break; + case REG_SD_IDST: /* Internal DMA Controller Status */ + s->dmac_status &= (~SD_IDST_WR_MASK) | (~value & SD_IDST_WR_MASK); + aw_h3_sdhost_update_irq(s); + break; + case REG_SD_IDIE: /* Internal DMA Controller Interrupt Enable */ + s->dmac_irq = value; + aw_h3_sdhost_update_irq(s); + break; + case REG_SD_THLDC: /* Card Threshold Control */ + s->card_threshold = value; + break; + case REG_SD_DSBD: /* eMMC DDR Start Bit Detection Control */ + s->startbit_detect = value; + break; + case REG_SD_FIFO: /* Read/Write FIFO */ + sdbus_write_data(&s->sdbus, value & 0xff); + sdbus_write_data(&s->sdbus, (value >> 8) & 0xff); + sdbus_write_data(&s->sdbus, (value >> 16) & 0xff); + sdbus_write_data(&s->sdbus, (value >> 24) & 0xff); + aw_h3_sdhost_update_transfer_cnt(s, sizeof(uint32_t)); + aw_h3_sdhost_auto_stop(s); + aw_h3_sdhost_update_irq(s); + break; + case REG_SD_RES_CRC: /* Response CRC from card/eMMC */ + case REG_SD_DATA7_CRC: /* CRC Data 7 from card/eMMC */ + case REG_SD_DATA6_CRC: /* CRC Data 6 from card/eMMC */ + case REG_SD_DATA5_CRC: /* CRC Data 5 from card/eMMC */ + case REG_SD_DATA4_CRC: /* CRC Data 4 from card/eMMC */ + case REG_SD_DATA3_CRC: /* CRC Data 3 from card/eMMC */ + case REG_SD_DATA2_CRC: /* CRC Data 2 from card/eMMC */ + case REG_SD_DATA1_CRC: /* CRC Data 1 from card/eMMC */ + case REG_SD_DATA0_CRC: /* CRC Data 0 from card/eMMC */ + case REG_SD_CRC_STA: /* CRC status from card/eMMC in write operation */ + break; + default: + qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset %"HWADDR_PRIx"\n", + __func__, offset); + break; + } +} + +static const MemoryRegionOps aw_h3_sdhost_ops = { + .read = aw_h3_sdhost_read, + .write = aw_h3_sdhost_write, + .endianness = DEVICE_NATIVE_ENDIAN, +}; + +static const VMStateDescription vmstate_aw_h3_sdhost = { + .name = TYPE_AW_H3_SDHOST, + .version_id = 1, + .minimum_version_id = 1, + .fields = (VMStateField[]) { + VMSTATE_UINT32(global_ctl, AwH3SDHostState), + VMSTATE_UINT32(clock_ctl, AwH3SDHostState), + VMSTATE_UINT32(timeout, AwH3SDHostState), + VMSTATE_UINT32(bus_width, AwH3SDHostState), + VMSTATE_UINT32(block_size, AwH3SDHostState), + VMSTATE_UINT32(byte_count, AwH3SDHostState), + VMSTATE_UINT32(transfer_cnt, AwH3SDHostState), + VMSTATE_UINT32(command, AwH3SDHostState), + VMSTATE_UINT32(command_arg, AwH3SDHostState), + VMSTATE_UINT32_ARRAY(response, AwH3SDHostState, 4), + VMSTATE_UINT32(irq_mask, AwH3SDHostState), + VMSTATE_UINT32(irq_status, AwH3SDHostState), + VMSTATE_UINT32(status, AwH3SDHostState), + VMSTATE_UINT32(fifo_wlevel, AwH3SDHostState), + VMSTATE_UINT32(fifo_func_sel, AwH3SDHostState), + VMSTATE_UINT32(debug_enable, AwH3SDHostState), + VMSTATE_UINT32(auto12_arg, AwH3SDHostState), + VMSTATE_UINT32(newtiming_set, AwH3SDHostState), + VMSTATE_UINT32(newtiming_debug, AwH3SDHostState), + VMSTATE_UINT32(hardware_rst, AwH3SDHostState), + VMSTATE_UINT32(dmac, AwH3SDHostState), + VMSTATE_UINT32(desc_base, AwH3SDHostState), + VMSTATE_UINT32(dmac_status, AwH3SDHostState), + VMSTATE_UINT32(dmac_irq, AwH3SDHostState), + VMSTATE_UINT32(card_threshold, AwH3SDHostState), + VMSTATE_UINT32(startbit_detect, AwH3SDHostState), + VMSTATE_UINT32(response_crc, AwH3SDHostState), + VMSTATE_UINT32_ARRAY(data_crc, AwH3SDHostState, 8), + VMSTATE_UINT32(status_crc, AwH3SDHostState), + VMSTATE_END_OF_LIST() + } +}; + +static void aw_h3_sdhost_init(Object *obj) +{ + AwH3SDHostState *s = AW_H3_SDHOST(obj); + + qbus_create_inplace(&s->sdbus, sizeof(s->sdbus), + TYPE_AW_H3_SDHOST_BUS, DEVICE(s), "sd-bus"); + + memory_region_init_io(&s->iomem, obj, &aw_h3_sdhost_ops, s, + TYPE_AW_H3_SDHOST, AW_H3_SDHOST_REGS_MEM_SIZE); + sysbus_init_mmio(SYS_BUS_DEVICE(s), &s->iomem); + sysbus_init_irq(SYS_BUS_DEVICE(s), &s->irq); +} + +static void aw_h3_sdhost_reset(DeviceState *dev) +{ + AwH3SDHostState *s = AW_H3_SDHOST(dev); + + s->global_ctl = REG_SD_GCTL_RST; + s->clock_ctl = REG_SD_CKCR_RST; + s->timeout = REG_SD_TMOR_RST; + s->bus_width = REG_SD_BWDR_RST; + s->block_size = REG_SD_BKSR_RST; + s->byte_count = REG_SD_BYCR_RST; + s->transfer_cnt = 0; + + s->command = REG_SD_CMDR_RST; + s->command_arg = REG_SD_CAGR_RST; + + for (int i = 0; i < sizeof(s->response) / sizeof(s->response[0]); i++) { + s->response[i] = REG_SD_RESP_RST; + } + + s->irq_mask = REG_SD_IMKR_RST; + s->irq_status = REG_SD_RISR_RST; + s->status = REG_SD_STAR_RST; + + s->fifo_wlevel = REG_SD_FWLR_RST; + s->fifo_func_sel = REG_SD_FUNS_RST; + s->debug_enable = REG_SD_DBGC_RST; + s->auto12_arg = REG_SD_A12A_RST; + s->newtiming_set = REG_SD_NTSR_RST; + s->newtiming_debug = REG_SD_SDBG_RST; + s->hardware_rst = REG_SD_HWRST_RST; + s->dmac = REG_SD_DMAC_RST; + s->desc_base = REG_SD_DLBA_RST; + s->dmac_status = REG_SD_IDST_RST; + s->dmac_irq = REG_SD_IDIE_RST; + s->card_threshold = REG_SD_THLDC_RST; + s->startbit_detect = REG_SD_DSBD_RST; + s->response_crc = REG_SD_RES_CRC_RST; + + for (int i = 0; i < sizeof(s->data_crc) / sizeof(s->data_crc[0]); i++) { + s->data_crc[i] = REG_SD_DATA_CRC_RST; + } + + s->status_crc = REG_SD_CRC_STA_RST; +} + +static void aw_h3_sdhost_bus_class_init(ObjectClass *klass, void *data) +{ + SDBusClass *sbc = SD_BUS_CLASS(klass); + + sbc->set_inserted = aw_h3_sdhost_set_inserted; +} + +static void aw_h3_sdhost_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + + dc->reset = aw_h3_sdhost_reset; + dc->vmsd = &vmstate_aw_h3_sdhost; +} + +static TypeInfo aw_h3_sdhost_info = { + .name = TYPE_AW_H3_SDHOST, + .parent = TYPE_SYS_BUS_DEVICE, + .instance_size = sizeof(AwH3SDHostState), + .class_init = aw_h3_sdhost_class_init, + .instance_init = aw_h3_sdhost_init, +}; + +static const TypeInfo aw_h3_sdhost_bus_info = { + .name = TYPE_AW_H3_SDHOST_BUS, + .parent = TYPE_SD_BUS, + .instance_size = sizeof(SDBus), + .class_init = aw_h3_sdhost_bus_class_init, +}; + +static void aw_h3_sdhost_register_types(void) +{ + type_register_static(&aw_h3_sdhost_info); + type_register_static(&aw_h3_sdhost_bus_info); +} + +type_init(aw_h3_sdhost_register_types) diff --git a/hw/sd/trace-events b/hw/sd/trace-events index efcff666a2..c672a201b5 100644 --- a/hw/sd/trace-events +++ b/hw/sd/trace-events @@ -1,5 +1,12 @@ # See docs/devel/tracing.txt for syntax documentation. +# allwinner-h3-sdhost.c +aw_h3_sdhost_set_inserted(bool inserted) "inserted %u" +aw_h3_sdhost_process_desc(uint64_t desc_addr, uint32_t desc_size, bool is_write, uint32_t max_bytes) "desc_addr 0x%" PRIx64 " desc_size %u is_write %u max_bytes %u" +aw_h3_sdhost_read(uint64_t offset, uint64_t data, unsigned size) "offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u" +aw_h3_sdhost_write(uint64_t offset, uint64_t data, unsigned size) "offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u" +aw_h3_sdhost_update_irq(uint32_t irq) "IRQ bits 0x%x" + # bcm2835_sdhost.c bcm2835_sdhost_read(uint64_t offset, uint64_t data, unsigned size) "offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u" bcm2835_sdhost_write(uint64_t offset, uint64_t data, unsigned size) "offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u" diff --git a/include/hw/arm/allwinner-h3.h b/include/hw/arm/allwinner-h3.h index 33602599eb..7aff4ebbd2 100644 --- a/include/hw/arm/allwinner-h3.h +++ b/include/hw/arm/allwinner-h3.h @@ -30,6 +30,7 @@ #include "hw/misc/allwinner-h3-cpucfg.h" #include "hw/misc/allwinner-h3-syscon.h" #include "hw/misc/allwinner-h3-sid.h" +#include "hw/sd/allwinner-h3-sdhost.h" #include "target/arm/cpu.h" #define AW_H3_SRAM_A1_BASE (0x00000000) @@ -117,6 +118,7 @@ typedef struct AwH3State { AwH3CpuCfgState cpucfg; AwH3SysconState syscon; AwH3SidState sid; + AwH3SDHostState mmc0; GICState gic; MemoryRegion sram_a1; MemoryRegion sram_a2; diff --git a/include/hw/sd/allwinner-h3-sdhost.h b/include/hw/sd/allwinner-h3-sdhost.h new file mode 100644 index 0000000000..6c898a3c84 --- /dev/null +++ b/include/hw/sd/allwinner-h3-sdhost.h @@ -0,0 +1,73 @@ +/* + * Allwinner H3 SD Host Controller emulation + * + * Copyright (C) 2019 Niek Linnenbank + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#ifndef ALLWINNER_H3_SDHOST_H +#define ALLWINNER_H3_SDHOST_H + +#include "hw/sysbus.h" +#include "hw/sd/sd.h" + +#define AW_H3_SDHOST_REGS_MEM_SIZE (1024) + +#define TYPE_AW_H3_SDHOST "allwinner-h3-sdhost" +#define AW_H3_SDHOST(obj) \ + OBJECT_CHECK(AwH3SDHostState, (obj), TYPE_AW_H3_SDHOST) + +typedef struct { + SysBusDevice busdev; + SDBus sdbus; + MemoryRegion iomem; + + uint32_t global_ctl; + uint32_t clock_ctl; + uint32_t timeout; + uint32_t bus_width; + uint32_t block_size; + uint32_t byte_count; + uint32_t transfer_cnt; + + uint32_t command; + uint32_t command_arg; + uint32_t response[4]; + + uint32_t irq_mask; + uint32_t irq_status; + uint32_t status; + + uint32_t fifo_wlevel; + uint32_t fifo_func_sel; + uint32_t debug_enable; + uint32_t auto12_arg; + uint32_t newtiming_set; + uint32_t newtiming_debug; + uint32_t hardware_rst; + uint32_t dmac; + uint32_t desc_base; + uint32_t dmac_status; + uint32_t dmac_irq; + uint32_t card_threshold; + uint32_t startbit_detect; + uint32_t response_crc; + uint32_t data_crc[8]; + uint32_t status_crc; + + qemu_irq irq; +} AwH3SDHostState; + +#endif -- 2.17.1 From MAILER-DAEMON Mon Dec 02 16:38:04 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1ibtOO-0003xq-Fz for mharc-qemu-arm@gnu.org; Mon, 02 Dec 2019 16:38:04 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:38334) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ibsxj-0002kD-T5 for qemu-arm@nongnu.org; Mon, 02 Dec 2019 16:10:34 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ibsxg-0000mI-7w for qemu-arm@nongnu.org; Mon, 02 Dec 2019 16:10:31 -0500 Received: from mail-wm1-x341.google.com ([2a00:1450:4864:20::341]:38630) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ibsxK-0000Z6-MT; Mon, 02 Dec 2019 16:10:06 -0500 Received: by mail-wm1-x341.google.com with SMTP id p17so1104421wmi.3; Mon, 02 Dec 2019 13:10:02 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=83StbJO9vc/PtHWWasIgmXL+LHo+Q8gv4+RVzsR74VQ=; b=gCiXGfOnKPgloIuyHuMaCPhD8S9iAMudxA9AQQt/u5v4kMTdj4vptn1OEHUBcKCCHQ csbBJqPb02EJBK4Uy433GrSxvySd0Cf1d7YqWPz7DzewkEQeBxkAIr+z27hFmPwcRfWn hg7doU9HUzUPHWUdhb4wwijTF7xp/1ugQuZ8rjz6A26yu8Cok860KBsd52bKoTu6w3oQ LdDdSzS7zCPpNQLHD0icoAlVEaTukdiiRW1VDkdxvgXoUBbctfM8cIpMfmlAtTKGTcQY DUa+yeH2V1y0Tw4azB0rArbR9zuafu+0xotqNxk15Z4iyV+l1CeYI34OfpSneJlsOYSS FrYA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=83StbJO9vc/PtHWWasIgmXL+LHo+Q8gv4+RVzsR74VQ=; b=ORpjx6ZpvxQDj+HHO/ryPpvFud+WyK71h/7+gSzpna6lc+YI46US2Q3lfByDC1dKzz +mtUYkjYBNykboGNTcfwaFKV9weW5dWvajvzOPAAUbdsOWyEBnyoOgjHJaso3TP1GpjX 0Eo8lHJTSSPJgPa8ve4iLFRRrZgG5oGwAhDWCD7GfazIZxZgA6XvFB2MvB347knX8jwQ jfdKv9pqaVohX9kF3yCwVAUDdT53ssCKsgAr+uKNtkUbKjugrjboVlaRJ9c9kYyGnTop idaLNZIPc8N6bC2gSKCct1CCcsFpz1aHuhugV4PZG5monH3vatuPFryyBRLP+E+Ut35w Wtaw== X-Gm-Message-State: APjAAAU8Uf6fdP1bcxF0G34GPFlRKZhEphT/Z5XjJ/EjiJeU46lqqUtQ i4ewYxxWpC+6KGG4PT1G2/tFdr6c X-Google-Smtp-Source: APXvYqwJLHQwAWW5duRMG7fSzTt431DYaSB/pQPPvt6Lguh49y+ClNL3iN8VJAoRaFQNaJz3T6V52Q== X-Received: by 2002:a1c:c906:: with SMTP id f6mr32010469wmb.14.1575321001109; Mon, 02 Dec 2019 13:10:01 -0800 (PST) Received: from pavilion.home ([2a02:a456:6be8:1:8edc:d4ff:fe8b:18b7]) by smtp.gmail.com with ESMTPSA id f1sm770859wrp.93.2019.12.02.13.10.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 02 Dec 2019 13:10:00 -0800 (PST) From: Niek Linnenbank To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, peter.maydell@linaro.org, b.galvani@gmail.com, Niek Linnenbank Subject: [PATCH 05/10] arm: allwinner-h3: add System Control module Date: Mon, 2 Dec 2019 22:09:42 +0100 Message-Id: <20191202210947.3603-6-nieklinnenbank@gmail.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20191202210947.3603-1-nieklinnenbank@gmail.com> References: <20191202210947.3603-1-nieklinnenbank@gmail.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::341 X-Mailman-Approved-At: Mon, 02 Dec 2019 16:38:01 -0500 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 02 Dec 2019 21:10:34 -0000 The Allwinner H3 System on Chip has an System Control module that provides system wide generic controls and device information. This commit adds support for the Allwinner H3 System Control module. Signed-off-by: Niek Linnenbank --- hw/arm/allwinner-h3.c | 11 ++ hw/misc/Makefile.objs | 1 + hw/misc/allwinner-h3-syscon.c | 139 ++++++++++++++++++++++++++ include/hw/arm/allwinner-h3.h | 2 + include/hw/misc/allwinner-h3-syscon.h | 43 ++++++++ 5 files changed, 196 insertions(+) create mode 100644 hw/misc/allwinner-h3-syscon.c create mode 100644 include/hw/misc/allwinner-h3-syscon.h diff --git a/hw/arm/allwinner-h3.c b/hw/arm/allwinner-h3.c index afeb49c0ac..ebd8fde412 100644 --- a/hw/arm/allwinner-h3.c +++ b/hw/arm/allwinner-h3.c @@ -41,6 +41,9 @@ static void aw_h3_init(Object *obj) sysbus_init_child_obj(obj, "ccu", &s->ccu, sizeof(s->ccu), TYPE_AW_H3_CLK); + + sysbus_init_child_obj(obj, "syscon", &s->syscon, sizeof(s->syscon), + TYPE_AW_H3_SYSCON); } static void aw_h3_realize(DeviceState *dev, Error **errp) @@ -184,6 +187,14 @@ static void aw_h3_realize(DeviceState *dev, Error **errp) } sysbus_mmio_map(SYS_BUS_DEVICE(&s->ccu), 0, AW_H3_CCU_BASE); + /* System Control */ + object_property_set_bool(OBJECT(&s->syscon), true, "realized", &err); + if (err) { + error_propagate(errp, err); + return; + } + sysbus_mmio_map(SYS_BUS_DEVICE(&s->syscon), 0, AW_H3_SYSCON_BASE); + /* Universal Serial Bus */ sysbus_create_simple(TYPE_AW_H3_EHCI, AW_H3_EHCI0_BASE, s->irq[AW_H3_GIC_SPI_EHCI0]); diff --git a/hw/misc/Makefile.objs b/hw/misc/Makefile.objs index 200ed44ce1..b234aefba5 100644 --- a/hw/misc/Makefile.objs +++ b/hw/misc/Makefile.objs @@ -29,6 +29,7 @@ common-obj-$(CONFIG_MACIO) += macio/ common-obj-$(CONFIG_IVSHMEM_DEVICE) += ivshmem.o common-obj-$(CONFIG_ALLWINNER_H3) += allwinner-h3-clk.o +common-obj-$(CONFIG_ALLWINNER_H3) += allwinner-h3-syscon.o common-obj-$(CONFIG_REALVIEW) += arm_sysctl.o common-obj-$(CONFIG_NSERIES) += cbus.o common-obj-$(CONFIG_ECCMEMCTL) += eccmemctl.o diff --git a/hw/misc/allwinner-h3-syscon.c b/hw/misc/allwinner-h3-syscon.c new file mode 100644 index 0000000000..66bd518a05 --- /dev/null +++ b/hw/misc/allwinner-h3-syscon.c @@ -0,0 +1,139 @@ +/* + * Allwinner H3 System Control emulation + * + * Copyright (C) 2019 Niek Linnenbank + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#include "qemu/osdep.h" +#include "hw/sysbus.h" +#include "migration/vmstate.h" +#include "qemu/log.h" +#include "qemu/module.h" +#include "hw/misc/allwinner-h3-syscon.h" + +/* SYSCON register offsets */ +#define REG_VER (0x24) /* Version */ +#define REG_EMAC_PHY_CLK (0x30) /* EMAC PHY Clock */ +#define REG_INDEX(offset) (offset / sizeof(uint32_t)) + +/* SYSCON register reset values */ +#define REG_VER_RST (0x0) +#define REG_EMAC_PHY_CLK_RST (0x58000) + +static uint64_t allwinner_h3_syscon_read(void *opaque, hwaddr offset, + unsigned size) +{ + const AwH3SysconState *s = (AwH3SysconState *)opaque; + const uint32_t idx = REG_INDEX(offset); + + if (idx >= AW_H3_SYSCON_REGS_NUM) { + qemu_log_mask(LOG_GUEST_ERROR, "%s: bad read offset 0x%04x\n", + __func__, (uint32_t)offset); + return 0; + } + + return s->regs[idx]; +} + +static void allwinner_h3_syscon_write(void *opaque, hwaddr offset, + uint64_t val, unsigned size) +{ + AwH3SysconState *s = (AwH3SysconState *)opaque; + const uint32_t idx = REG_INDEX(offset); + + if (idx >= AW_H3_SYSCON_REGS_NUM) { + qemu_log_mask(LOG_GUEST_ERROR, "%s: bad write offset 0x%04x\n", + __func__, (uint32_t)offset); + return; + } + + switch (offset) { + case REG_VER: /* Version */ + break; + default: + s->regs[idx] = (uint32_t) val; + break; + } +} + +static const MemoryRegionOps allwinner_h3_syscon_ops = { + .read = allwinner_h3_syscon_read, + .write = allwinner_h3_syscon_write, + .endianness = DEVICE_NATIVE_ENDIAN, + .valid = { + .min_access_size = 4, + .max_access_size = 4, + .unaligned = false + } +}; + +static void allwinner_h3_syscon_reset(DeviceState *dev) +{ + AwH3SysconState *s = AW_H3_SYSCON(dev); + + /* Set default values for registers */ + s->regs[REG_INDEX(REG_VER)] = REG_VER_RST; + s->regs[REG_INDEX(REG_EMAC_PHY_CLK)] = REG_EMAC_PHY_CLK_RST; +} + +static void allwinner_h3_syscon_realize(DeviceState *dev, Error **errp) +{ +} + +static void allwinner_h3_syscon_init(Object *obj) +{ + SysBusDevice *sbd = SYS_BUS_DEVICE(obj); + AwH3SysconState *s = AW_H3_SYSCON(obj); + + /* Memory mapping */ + memory_region_init_io(&s->iomem, OBJECT(s), &allwinner_h3_syscon_ops, s, + TYPE_AW_H3_SYSCON, AW_H3_SYSCON_REGS_MEM_SIZE); + sysbus_init_mmio(sbd, &s->iomem); +} + +static const VMStateDescription allwinner_h3_syscon_vmstate = { + .name = TYPE_AW_H3_SYSCON, + .version_id = 1, + .minimum_version_id = 1, + .fields = (VMStateField[]) { + VMSTATE_UINT32_ARRAY(regs, AwH3SysconState, AW_H3_SYSCON_REGS_NUM), + VMSTATE_END_OF_LIST() + } +}; + +static void allwinner_h3_syscon_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + + dc->reset = allwinner_h3_syscon_reset; + dc->realize = allwinner_h3_syscon_realize; + dc->vmsd = &allwinner_h3_syscon_vmstate; +} + +static const TypeInfo allwinner_h3_syscon_info = { + .name = TYPE_AW_H3_SYSCON, + .parent = TYPE_SYS_BUS_DEVICE, + .instance_init = allwinner_h3_syscon_init, + .instance_size = sizeof(AwH3SysconState), + .class_init = allwinner_h3_syscon_class_init, +}; + +static void allwinner_h3_syscon_register(void) +{ + type_register_static(&allwinner_h3_syscon_info); +} + +type_init(allwinner_h3_syscon_register) diff --git a/include/hw/arm/allwinner-h3.h b/include/hw/arm/allwinner-h3.h index e596516c5c..2bc526b77b 100644 --- a/include/hw/arm/allwinner-h3.h +++ b/include/hw/arm/allwinner-h3.h @@ -27,6 +27,7 @@ #include "hw/timer/allwinner-a10-pit.h" #include "hw/intc/arm_gic.h" #include "hw/misc/allwinner-h3-clk.h" +#include "hw/misc/allwinner-h3-syscon.h" #include "target/arm/cpu.h" #define AW_H3_SRAM_A1_BASE (0x00000000) @@ -111,6 +112,7 @@ typedef struct AwH3State { qemu_irq irq[AW_H3_GIC_NUM_SPI]; AwA10PITState timer; AwH3ClockState ccu; + AwH3SysconState syscon; GICState gic; MemoryRegion sram_a1; MemoryRegion sram_a2; diff --git a/include/hw/misc/allwinner-h3-syscon.h b/include/hw/misc/allwinner-h3-syscon.h new file mode 100644 index 0000000000..22a2f2a11b --- /dev/null +++ b/include/hw/misc/allwinner-h3-syscon.h @@ -0,0 +1,43 @@ +/* + * Allwinner H3 System Control emulation + * + * Copyright (C) 2019 Niek Linnenbank + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#ifndef HW_MISC_ALLWINNER_H3_SYSCON_H +#define HW_MISC_ALLWINNER_H3_SYSCON_H + +#include "hw/sysbus.h" + +#define AW_H3_SYSCON_REGS_MAX_ADDR (0x30) +#define AW_H3_SYSCON_REGS_NUM ((AW_H3_SYSCON_REGS_MAX_ADDR / \ + sizeof(uint32_t)) + 1) +#define AW_H3_SYSCON_REGS_MEM_SIZE (1024) + +#define TYPE_AW_H3_SYSCON "allwinner-h3-syscon" +#define AW_H3_SYSCON(obj) OBJECT_CHECK(AwH3SysconState, (obj), \ + TYPE_AW_H3_SYSCON) + +typedef struct AwH3SysconState { + /*< private >*/ + SysBusDevice parent_obj; + /*< public >*/ + + MemoryRegion iomem; + uint32_t regs[AW_H3_SYSCON_REGS_NUM]; +} AwH3SysconState; + +#endif -- 2.17.1 From MAILER-DAEMON Mon Dec 02 16:38:05 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1ibtOP-000401-G8 for mharc-qemu-arm@gnu.org; Mon, 02 Dec 2019 16:38:05 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:38272) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ibsxg-0002hE-OR for qemu-arm@nongnu.org; Mon, 02 Dec 2019 16:10:30 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ibsxa-0000kJ-IS for qemu-arm@nongnu.org; Mon, 02 Dec 2019 16:10:26 -0500 Received: from mail-wm1-x342.google.com ([2a00:1450:4864:20::342]:33854) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ibsxK-0000Y6-El; Mon, 02 Dec 2019 16:10:06 -0500 Received: by mail-wm1-x342.google.com with SMTP id f4so775853wmj.1; Mon, 02 Dec 2019 13:09:58 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id; bh=LEn9j1X544VOGdDqcFyPUsPjhPLUxtiH/o0b4RFTF1E=; b=hEMvku+HxXFrtCH1xtIajvdSr/C+PUBdv2Fet/yl+OwJEbRXojjQzZY014UAZoucjp VFhhRPLXdj62/117gVf8gOMHUB6iPUHYBZWi84cMlPXKoS1XITnKtaGVcCg4zjSLJ7O+ 8cd58bxvixqVo9NDEEfukoldTpx1HVpo5+qeR7CZOTKcputw/BEw3XYmQtbt96Bh0Vzw sHQR7jI4/5wyvBksLF96tCXh8wc3IihTX64o/GMI0hbAjhynh28rleB7zL8J5R6qvWDU BDy5r0GwV5r9aQ+KwiKBCVYHFffS5BL0kk3bJYuJWcs3oh6bXXOW4kQpkoE3qs4BaYuG sAow== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=LEn9j1X544VOGdDqcFyPUsPjhPLUxtiH/o0b4RFTF1E=; b=bizGrgq9RaVWRGbNwpOYeWHkoCNJ3bAV30vNFCQlhKlcVN7rDllv/O/H7APBtjupxh aBKhW0hzOY210SzpABn48CIYFY2PfyOxG+D+aTYq6dKUlst3kVCkNjdRxkTqY5IbItEC 2y5Ferqwj6O47ZEI0XP8POhxu98OUpSAQm/elwy4G8jN/MI3R+Ioo6qlJfzINpcB3C9y UsvnKjzpc6biFami8e7e69OFk52VVI5owvr2jPl44Oi/f+H17mv+2py86LQrbF565UiU lxUB+cn4Z+bC3QQzjtd+yUAW8lJu/yPp8a+3xGKjqvD9b2CrB7/Q3ObHDJiP/G/M9XWW 94vw== X-Gm-Message-State: APjAAAXNj86efFF7iZEJdV/z8VnRSmsz1IYC314i2xwQC8HaCTYpKA9g b2D8YjQw/6FzOHSHv99l3tZGB2ha X-Google-Smtp-Source: APXvYqzrlNrtMOZkbwP829x1e9OHf1FO0oYhLeXbnXLcsXAAtMVaxR49D9Apa/xD9Tpgnsb2DsRAgg== X-Received: by 2002:a7b:ce19:: with SMTP id m25mr11697248wmc.6.1575320996724; Mon, 02 Dec 2019 13:09:56 -0800 (PST) Received: from pavilion.home ([2a02:a456:6be8:1:8edc:d4ff:fe8b:18b7]) by smtp.gmail.com with ESMTPSA id f1sm770859wrp.93.2019.12.02.13.09.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 02 Dec 2019 13:09:56 -0800 (PST) From: Niek Linnenbank To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, peter.maydell@linaro.org, b.galvani@gmail.com, Niek Linnenbank Subject: [PATCH 00/10] Add Allwinner H3 SoC and Orange Pi PC Machine Date: Mon, 2 Dec 2019 22:09:37 +0100 Message-Id: <20191202210947.3603-1-nieklinnenbank@gmail.com> X-Mailer: git-send-email 2.17.1 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::342 X-Mailman-Approved-At: Mon, 02 Dec 2019 16:38:01 -0500 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 02 Dec 2019 21:10:30 -0000 Dear QEMU developers, Hereby I would like to contribute the following set of patches to QEMU which add support for the Allwinner H3 System on Chip and the Orange Pi PC machine. The following features and devices are supported: * SMP (Quad Core Cortex A7) * Generic Interrupt Controller configuration * SRAM mappings * Timer device (re-used from Allwinner A10) * UART * SD/MMC storage controller * EMAC ethernet connectivity * USB 2.0 interfaces * Clock Control Unit * System Control module * Security Identifier device Functionality related to graphical output such as HDMI, GPU, Display Engine and audio are not included. Recently released mainline Linux kernels (4.19 up to latest master) and mainline U-Boot are known to work. The SD/MMC code is tested using bonnie++ and various tools such as fsck, dd and fdisk. The EMAC is verified with iperf3 using -netdev socket. To build a Linux mainline kernel that can be booted by the Orange Pi PC machine, simply configure the kernel using the sunxi_defconfig configuration: $ ARCH=arm CROSS_COMPILE=arm-linux-gnueabi- make mrproper $ ARCH=arm CROSS_COMPILE=arm-linux-gnueabi- make sunxi_defconfig To be able to use USB storage, you need to manually enable the corresponding configuration item. Start the kconfig configuration tool: $ ARCH=arm CROSS_COMPILE=arm-linux-gnueabi- make menuconfig Navigate to the following item, enable it and save your configuration: Device Drivers > USB support > USB Mass Storage support Build the Linux kernel with: $ ARCH=arm CROSS_COMPILE=arm-linux-gnueabi- make -j5 To boot the newly build linux kernel in QEMU with the Orange Pi PC machine, use: $ qemu-system-arm -M orangepi -m 512 -nic user -nographic \ -kernel /path/to/linux/arch/arm/boot/zImage \ -append 'console=ttyS0,115200' \ -dtb /path/to/linux/arch/arm/boot/dts/sun8i-h3-orangepi-pc.dtb Note that this kernel does not have a root filesystem. You may provide it with an official Orange Pi PC image [1] either as an SD card or as USB mass storage. To boot using the Orange Pi PC Debian image on SD card, simply add the -sd argument and provide the proper root= kernel parameter: $ qemu-system-arm -M orangepi -m 512 -nic user -nographic \ -kernel /path/to/linux/arch/arm/boot/zImage \ -append 'console=ttyS0,115200 root=/dev/mmcblk0p2' \ -dtb /path/to/linux/arch/arm/boot/dts/sun8i-h3-orangepi-pc.dtb \ -sd OrangePi_pc_debian_stretch_server_linux5.3.5_v1.0.img Alternatively, you can also choose to build and boot a recent buildroot [2] using the orangepi_pc_defconfig or Armbian image [3] for Orange Pi PC. To attach an USB mass storage device to the machine, simply append to the command: -drive if=none,id=stick,file=myimage.img \ -device usb-storage,bus=usb-bus.0,drive=stick U-Boot mainline can be build and configured using the orangepi_pc_defconfig using similar commands as describe above for Linux. To start U-Boot using the Orange Pi PC machine, provide the u-boot binary to the -kernel argument: $ qemu-system-arm -M orangepi -m 512 -nic user -nographic \ -kernel /path/to/uboot/u-boot -sd disk.img Use the following U-boot commands to load and boot a Linux kernel from SD card: -> setenv bootargs console=ttyS0,115200 -> ext2load mmc 0 0x42000000 zImage -> ext2load mmc 0 0x43000000 sun8i-h2-plus-orangepi-zero.dtb -> bootz 0x42000000 - 0x43000000 Looking forward to your review comments. I will do my best to update the patches where needed. With kind regards, Niek Linnenbank [1] http://www.orangepi.org/downloadresources/ [2] https://buildroot.org/download.html [3] https://www.armbian.com/orange-pi-pc/ Niek Linnenbank (10): hw: arm: add Allwinner H3 System-on-Chip hw: arm: add Xunlong Orange Pi PC machine arm: allwinner-h3: add Clock Control Unit arm: allwinner-h3: add USB host controller arm: allwinner-h3: add System Control module arm/arm-powerctl: set NSACR.{CP11,CP10} bits in arm_set_cpu_on() arm: allwinner-h3: add CPU Configuration module arm: allwinner-h3: add Security Identifier device arm: allwinner-h3: add SD/MMC host controller arm: allwinner-h3: add EMAC ethernet device MAINTAINERS | 8 + default-configs/arm-softmmu.mak | 1 + hw/arm/Kconfig | 9 + hw/arm/Makefile.objs | 1 + hw/arm/allwinner-h3.c | 316 ++++++++++ hw/arm/orangepi.c | 114 ++++ hw/misc/Makefile.objs | 4 + hw/misc/allwinner-h3-clk.c | 227 ++++++++ hw/misc/allwinner-h3-cpucfg.c | 280 +++++++++ hw/misc/allwinner-h3-sid.c | 162 ++++++ hw/misc/allwinner-h3-syscon.c | 139 +++++ hw/misc/trace-events | 5 + hw/net/Kconfig | 3 + hw/net/Makefile.objs | 1 + hw/net/allwinner-h3-emac.c | 786 +++++++++++++++++++++++++ hw/net/trace-events | 10 + hw/sd/Makefile.objs | 1 + hw/sd/allwinner-h3-sdhost.c | 791 ++++++++++++++++++++++++++ hw/sd/trace-events | 7 + hw/usb/hcd-ehci-sysbus.c | 17 + hw/usb/hcd-ehci.h | 1 + include/hw/arm/allwinner-h3.h | 130 +++++ include/hw/misc/allwinner-h3-clk.h | 41 ++ include/hw/misc/allwinner-h3-cpucfg.h | 44 ++ include/hw/misc/allwinner-h3-sid.h | 42 ++ include/hw/misc/allwinner-h3-syscon.h | 43 ++ include/hw/net/allwinner-h3-emac.h | 69 +++ include/hw/sd/allwinner-h3-sdhost.h | 73 +++ target/arm/arm-powerctl.c | 3 + 29 files changed, 3328 insertions(+) create mode 100644 hw/arm/allwinner-h3.c create mode 100644 hw/arm/orangepi.c create mode 100644 hw/misc/allwinner-h3-clk.c create mode 100644 hw/misc/allwinner-h3-cpucfg.c create mode 100644 hw/misc/allwinner-h3-sid.c create mode 100644 hw/misc/allwinner-h3-syscon.c create mode 100644 hw/net/allwinner-h3-emac.c create mode 100644 hw/sd/allwinner-h3-sdhost.c create mode 100644 include/hw/arm/allwinner-h3.h create mode 100644 include/hw/misc/allwinner-h3-clk.h create mode 100644 include/hw/misc/allwinner-h3-cpucfg.h create mode 100644 include/hw/misc/allwinner-h3-sid.h create mode 100644 include/hw/misc/allwinner-h3-syscon.h create mode 100644 include/hw/net/allwinner-h3-emac.h create mode 100644 include/hw/sd/allwinner-h3-sdhost.h -- 2.17.1 From MAILER-DAEMON Mon Dec 02 16:38:05 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1ibtOP-00040T-NA for mharc-qemu-arm@gnu.org; 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Mon, 02 Dec 2019 13:09:58 -0800 (PST) From: Niek Linnenbank To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, peter.maydell@linaro.org, b.galvani@gmail.com, Niek Linnenbank Subject: [PATCH 02/10] hw: arm: add Xunlong Orange Pi PC machine Date: Mon, 2 Dec 2019 22:09:39 +0100 Message-Id: <20191202210947.3603-3-nieklinnenbank@gmail.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20191202210947.3603-1-nieklinnenbank@gmail.com> References: <20191202210947.3603-1-nieklinnenbank@gmail.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::343 X-Mailman-Approved-At: Mon, 02 Dec 2019 16:38:01 -0500 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 02 Dec 2019 21:10:33 -0000 The Xunlong Orange Pi PC is an Allwinner H3 System on Chip based embedded computer with mainline support in both U-Boot and Linux. The board comes with a Quad Core Cortex A7 @ 1.3GHz, 512MB RAM, 100Mbit ethernet, USB, SD/MMC, USB, HDMI and various other I/O. This commit add support for the Xunlong Orange Pi PC machine. Signed-off-by: Niek Linnenbank --- MAINTAINERS | 1 + hw/arm/Makefile.objs | 2 +- hw/arm/orangepi.c | 90 ++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 92 insertions(+), 1 deletion(-) create mode 100644 hw/arm/orangepi.c diff --git a/MAINTAINERS b/MAINTAINERS index 29c9936037..42c913d6cb 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -485,6 +485,7 @@ L: qemu-arm@nongnu.org S: Maintained F: hw/*/allwinner-h3* F: include/hw/*/allwinner-h3* +F: hw/arm/orangepi.c ARM PrimeCell and CMSDK devices M: Peter Maydell diff --git a/hw/arm/Makefile.objs b/hw/arm/Makefile.objs index 956e496052..8d5ea453d5 100644 --- a/hw/arm/Makefile.objs +++ b/hw/arm/Makefile.objs @@ -34,7 +34,7 @@ obj-$(CONFIG_DIGIC) += digic.o obj-$(CONFIG_OMAP) += omap1.o omap2.o obj-$(CONFIG_STRONGARM) += strongarm.o obj-$(CONFIG_ALLWINNER_A10) += allwinner-a10.o cubieboard.o -obj-$(CONFIG_ALLWINNER_H3) += allwinner-h3.o +obj-$(CONFIG_ALLWINNER_H3) += allwinner-h3.o orangepi.o obj-$(CONFIG_RASPI) += bcm2835_peripherals.o bcm2836.o raspi.o obj-$(CONFIG_STM32F205_SOC) += stm32f205_soc.o obj-$(CONFIG_XLNX_ZYNQMP_ARM) += xlnx-zynqmp.o xlnx-zcu102.o diff --git a/hw/arm/orangepi.c b/hw/arm/orangepi.c new file mode 100644 index 0000000000..5ef2735f81 --- /dev/null +++ b/hw/arm/orangepi.c @@ -0,0 +1,90 @@ +/* + * Orange Pi emulation + * + * Copyright (C) 2019 Niek Linnenbank + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#include "qemu/osdep.h" +#include "exec/address-spaces.h" +#include "qapi/error.h" +#include "cpu.h" +#include "hw/sysbus.h" +#include "hw/boards.h" +#include "hw/qdev-properties.h" +#include "hw/arm/allwinner-h3.h" + +static struct arm_boot_info orangepi_binfo = { + .loader_start = AW_H3_SDRAM_BASE, + .board_id = -1, +}; + +typedef struct OrangePiState { + AwH3State *h3; + MemoryRegion sdram; +} OrangePiState; + +static void orangepi_init(MachineState *machine) +{ + OrangePiState *s = g_new(OrangePiState, 1); + Error *err = NULL; + + s->h3 = AW_H3(object_new(TYPE_AW_H3)); + + /* Setup timer properties */ + object_property_set_int(OBJECT(&s->h3->timer), 32768, "clk0-freq", &err); + if (err != NULL) { + error_reportf_err(err, "Couldn't set clk0 frequency: "); + exit(1); + } + + object_property_set_int(OBJECT(&s->h3->timer), 24000000, "clk1-freq", + &err); + if (err != NULL) { + error_reportf_err(err, "Couldn't set clk1 frequency: "); + exit(1); + } + + /* Mark H3 object realized */ + object_property_set_bool(OBJECT(s->h3), true, "realized", &err); + if (err != NULL) { + error_reportf_err(err, "Couldn't realize Allwinner H3: "); + exit(1); + } + + /* RAM */ + memory_region_allocate_system_memory(&s->sdram, NULL, "orangepi.ram", + machine->ram_size); + memory_region_add_subregion(get_system_memory(), AW_H3_SDRAM_BASE, + &s->sdram); + + /* Load target kernel */ + orangepi_binfo.ram_size = machine->ram_size; + orangepi_binfo.nb_cpus = AW_H3_NUM_CPUS; + arm_load_kernel(ARM_CPU(first_cpu), machine, &orangepi_binfo); +} + +static void orangepi_machine_init(MachineClass *mc) +{ + mc->desc = "Orange Pi PC"; + mc->init = orangepi_init; + mc->units_per_default_bus = 1; + mc->min_cpus = AW_H3_NUM_CPUS; + mc->max_cpus = AW_H3_NUM_CPUS; + mc->default_cpus = AW_H3_NUM_CPUS; + mc->ignore_memory_transaction_failures = true; +} + +DEFINE_MACHINE("orangepi", orangepi_machine_init) -- 2.17.1 From MAILER-DAEMON Mon Dec 02 16:38:06 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1ibtOP-000410-V0 for mharc-qemu-arm@gnu.org; Mon, 02 Dec 2019 16:38:05 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:38530) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ibsxp-0002rj-Q9 for qemu-arm@nongnu.org; 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Mon, 02 Dec 2019 13:10:01 -0800 (PST) From: Niek Linnenbank To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, peter.maydell@linaro.org, b.galvani@gmail.com, Niek Linnenbank Subject: [PATCH 06/10] arm/arm-powerctl: set NSACR.{CP11, CP10} bits in arm_set_cpu_on() Date: Mon, 2 Dec 2019 22:09:43 +0100 Message-Id: <20191202210947.3603-7-nieklinnenbank@gmail.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20191202210947.3603-1-nieklinnenbank@gmail.com> References: <20191202210947.3603-1-nieklinnenbank@gmail.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::341 X-Mailman-Approved-At: Mon, 02 Dec 2019 16:38:01 -0500 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 02 Dec 2019 21:10:39 -0000 This change ensures that the FPU can be accessed in Non-Secure mode when the CPU core is reset using the arm_set_cpu_on() function call. The NSACR.{CP11,CP10} bits define the exception level required to access the FPU in Non-Secure mode. Without these bits set, the CPU will give an undefined exception trap on the first FPU access for the secondary cores under Linux. Fixes: fc1120a7f5 Signed-off-by: Niek Linnenbank --- target/arm/arm-powerctl.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/target/arm/arm-powerctl.c b/target/arm/arm-powerctl.c index f77a950db6..b064513d44 100644 --- a/target/arm/arm-powerctl.c +++ b/target/arm/arm-powerctl.c @@ -104,6 +104,9 @@ static void arm_set_cpu_on_async_work(CPUState *target_cpu_state, /* Processor is not in secure mode */ target_cpu->env.cp15.scr_el3 |= SCR_NS; + /* Set NSACR.{CP11,CP10} so NS can access the FPU */ + target_cpu->env.cp15.nsacr |= 3 << 10; + /* * If QEMU is providing the equivalent of EL3 firmware, then we need * to make sure a CPU targeting EL2 comes out of reset with a -- 2.17.1 From MAILER-DAEMON Mon Dec 02 16:38:06 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1ibtOQ-00041V-4l for mharc-qemu-arm@gnu.org; Mon, 02 Dec 2019 16:38:06 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:38539) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ibsxp-0002ru-TD for qemu-arm@nongnu.org; Mon, 02 Dec 2019 16:10:41 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ibsxk-0000qd-PH for qemu-arm@nongnu.org; Mon, 02 Dec 2019 16:10:37 -0500 Received: from mail-wr1-x441.google.com ([2a00:1450:4864:20::441]:41607) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ibsxQ-0000b8-Pf; Mon, 02 Dec 2019 16:10:13 -0500 Received: by mail-wr1-x441.google.com with SMTP id b18so983379wrj.8; Mon, 02 Dec 2019 13:10:07 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=YSSdKKG1i6JVSlPytRsAwGL4WTE2dxtGdKjtspalJFE=; b=L7ZszqUzkHcluseCQLaWzNFJkI+6teYGz8kuF4ZzyMxGNDrQjkB1q3yD4lB0aSz1t2 4WgoAtsG1TqhLzlPY6scu4WFW5vve946/3lHfjOcecVoDicSS53/rs7DIXcFQbEW+smO HoGj+UsxG+J/smctlkiTJnmBHksNt9KsnixK4M34VWwG9hrCbW/UO8LoCofv+6iB2pGs fmUecTmhJf5HdwFMGVdat0iCixJRq6nlFChReialxQJmlf8prJJxVlJiqzqivWEKkBI8 VWTkyLJb+olapWmqYemz1GpeTCJdfVrAN8Z9LT8BzMO6dfw7GDhUgJLLZCH47Cv7KOfw 5XNg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=YSSdKKG1i6JVSlPytRsAwGL4WTE2dxtGdKjtspalJFE=; b=FUYpHTd04WBfPD0Tzcr5h10VBlV+I6VcmDPSgmnGvV2rmw7DEhA8Q8do2R98IE5K4c vdzhLsbKmOSlsNuTocWq96VCD6oojdDlZ5fIDm2NJITE8NcJIQmBmKc3uGu85T22yXjr y5mCmkk7SVc2jL4DALsN/a051GEVPlQzLnF/excNYXE+XjZxCelPq1nN3RfY+Dtkcccs 8Zek+8Qmge7IvmAskSXT9Xkgrj0qWLJcLaPE5xmK5cmD1Dle+/QHrLaA+8Iiv2WjqPBQ +2Busx4fmHKuFx7fUVHHdGWcy2obLDmRlqODaG3LhMCarB5F/PgRUt19+C07TptPiAO2 Oitg== X-Gm-Message-State: APjAAAUIYTTcBSU9aMyCibpqxqdXHItBbH25brEIH2csRGgSHICmW9DL F0ml87b7K6lud4+9pj0zXIp15fQ4 X-Google-Smtp-Source: APXvYqwQkNFAKM4YhPm2hslVoloXVTCFDw47qe/cJqMSf2UxnufyFhxJppZZ3oE4wZQwnsa3gqhQ8g== X-Received: by 2002:adf:edd0:: with SMTP id v16mr1112264wro.310.1575321005843; Mon, 02 Dec 2019 13:10:05 -0800 (PST) Received: from pavilion.home ([2a02:a456:6be8:1:8edc:d4ff:fe8b:18b7]) by smtp.gmail.com with ESMTPSA id f1sm770859wrp.93.2019.12.02.13.10.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 02 Dec 2019 13:10:05 -0800 (PST) From: Niek Linnenbank To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, peter.maydell@linaro.org, b.galvani@gmail.com, Niek Linnenbank Subject: [PATCH 10/10] arm: allwinner-h3: add EMAC ethernet device Date: Mon, 2 Dec 2019 22:09:47 +0100 Message-Id: <20191202210947.3603-11-nieklinnenbank@gmail.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20191202210947.3603-1-nieklinnenbank@gmail.com> References: <20191202210947.3603-1-nieklinnenbank@gmail.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::441 X-Mailman-Approved-At: Mon, 02 Dec 2019 16:38:01 -0500 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 02 Dec 2019 21:10:42 -0000 The Allwinner H3 System on Chip includes an Ethernet MAC (EMAC) which provides 10M/100M/1000M Ethernet connectivity. This commit adds support for the Allwinner H3 EMAC, including emulation for the following functionality: * DMA transfers * MII interface * Transmit CRC calculation Signed-off-by: Niek Linnenbank --- hw/arm/Kconfig | 1 + hw/arm/allwinner-h3.c | 17 + hw/arm/orangepi.c | 7 + hw/net/Kconfig | 3 + hw/net/Makefile.objs | 1 + hw/net/allwinner-h3-emac.c | 786 +++++++++++++++++++++++++++++ hw/net/trace-events | 10 + include/hw/arm/allwinner-h3.h | 2 + include/hw/net/allwinner-h3-emac.h | 69 +++ 9 files changed, 896 insertions(+) create mode 100644 hw/net/allwinner-h3-emac.c create mode 100644 include/hw/net/allwinner-h3-emac.h diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig index ebf8d2325f..551cff3442 100644 --- a/hw/arm/Kconfig +++ b/hw/arm/Kconfig @@ -294,6 +294,7 @@ config ALLWINNER_A10 config ALLWINNER_H3 bool select ALLWINNER_A10_PIT + select ALLWINNER_H3_EMAC select SERIAL select ARM_TIMER select ARM_GIC diff --git a/hw/arm/allwinner-h3.c b/hw/arm/allwinner-h3.c index c2972caf88..274b8548c0 100644 --- a/hw/arm/allwinner-h3.c +++ b/hw/arm/allwinner-h3.c @@ -53,6 +53,9 @@ static void aw_h3_init(Object *obj) sysbus_init_child_obj(obj, "mmc0", &s->mmc0, sizeof(s->mmc0), TYPE_AW_H3_SDHOST); + + sysbus_init_child_obj(obj, "emac", &s->emac, sizeof(s->emac), + TYPE_AW_H3_EMAC); } static void aw_h3_realize(DeviceState *dev, Error **errp) @@ -237,6 +240,20 @@ static void aw_h3_realize(DeviceState *dev, Error **errp) return; } + /* EMAC */ + if (nd_table[0].used) { + qemu_check_nic_model(&nd_table[0], TYPE_AW_H3_EMAC); + qdev_set_nic_properties(DEVICE(&s->emac), &nd_table[0]); + } + object_property_set_bool(OBJECT(&s->emac), true, "realized", &err); + if (err != NULL) { + error_propagate(errp, err); + return; + } + sysbusdev = SYS_BUS_DEVICE(&s->emac); + sysbus_mmio_map(sysbusdev, 0, AW_H3_EMAC_BASE); + sysbus_connect_irq(sysbusdev, 0, s->irq[AW_H3_GIC_SPI_EMAC]); + /* Universal Serial Bus */ sysbus_create_simple(TYPE_AW_H3_EHCI, AW_H3_EHCI0_BASE, s->irq[AW_H3_GIC_SPI_EHCI0]); diff --git a/hw/arm/orangepi.c b/hw/arm/orangepi.c index dee3efaf08..8a61eb0e69 100644 --- a/hw/arm/orangepi.c +++ b/hw/arm/orangepi.c @@ -61,6 +61,13 @@ static void orangepi_init(MachineState *machine) exit(1); } + /* Setup EMAC properties */ + object_property_set_int(OBJECT(&s->h3->emac), 1, "phy-addr", &err); + if (err != NULL) { + error_reportf_err(err, "Couldn't set phy address: "); + exit(1); + } + /* Mark H3 object realized */ object_property_set_bool(OBJECT(s->h3), true, "realized", &err); if (err != NULL) { diff --git a/hw/net/Kconfig b/hw/net/Kconfig index 3856417d42..36d3923992 100644 --- a/hw/net/Kconfig +++ b/hw/net/Kconfig @@ -74,6 +74,9 @@ config MIPSNET config ALLWINNER_EMAC bool +config ALLWINNER_H3_EMAC + bool + config IMX_FEC bool diff --git a/hw/net/Makefile.objs b/hw/net/Makefile.objs index 7907d2c199..5548deb07a 100644 --- a/hw/net/Makefile.objs +++ b/hw/net/Makefile.objs @@ -23,6 +23,7 @@ common-obj-$(CONFIG_XGMAC) += xgmac.o common-obj-$(CONFIG_MIPSNET) += mipsnet.o common-obj-$(CONFIG_XILINX_AXI) += xilinx_axienet.o common-obj-$(CONFIG_ALLWINNER_EMAC) += allwinner_emac.o +common-obj-$(CONFIG_ALLWINNER_H3_EMAC) += allwinner-h3-emac.o common-obj-$(CONFIG_IMX_FEC) += imx_fec.o common-obj-$(CONFIG_CADENCE) += cadence_gem.o diff --git a/hw/net/allwinner-h3-emac.c b/hw/net/allwinner-h3-emac.c new file mode 100644 index 0000000000..37f6f44406 --- /dev/null +++ b/hw/net/allwinner-h3-emac.c @@ -0,0 +1,786 @@ +/* + * Allwinner H3 EMAC emulation + * + * Copyright (C) 2019 Niek Linnenbank + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#include "qemu/osdep.h" +#include "hw/sysbus.h" +#include "migration/vmstate.h" +#include "net/net.h" +#include "hw/irq.h" +#include "hw/qdev-properties.h" +#include "qemu/log.h" +#include "trace.h" +#include "net/checksum.h" +#include "qemu/module.h" +#include "exec/cpu-common.h" +#include "hw/net/allwinner-h3-emac.h" + +/* EMAC register offsets */ +#define REG_BASIC_CTL_0 (0x0000) /* Basic Control 0 */ +#define REG_BASIC_CTL_1 (0x0004) /* Basic Control 1 */ +#define REG_INT_STA (0x0008) /* Interrupt Status */ +#define REG_INT_EN (0x000C) /* Interrupt Enable */ +#define REG_TX_CTL_0 (0x0010) /* Transmit Control 0 */ +#define REG_TX_CTL_1 (0x0014) /* Transmit Control 1 */ +#define REG_TX_FLOW_CTL (0x001C) /* Transmit Flow Control */ +#define REG_TX_DMA_DESC_LIST (0x0020) /* Transmit Descriptor List Address */ +#define REG_RX_CTL_0 (0x0024) /* Receive Control 0 */ +#define REG_RX_CTL_1 (0x0028) /* Receive Control 1 */ +#define REG_RX_DMA_DESC_LIST (0x0034) /* Receive Descriptor List Address */ +#define REG_FRM_FLT (0x0038) /* Receive Frame Filter */ +#define REG_RX_HASH_0 (0x0040) /* Receive Hash Table 0 */ +#define REG_RX_HASH_1 (0x0044) /* Receive Hash Table 1 */ +#define REG_MII_CMD (0x0048) /* Management Interface Command */ +#define REG_MII_DATA (0x004C) /* Management Interface Data */ +#define REG_ADDR_HIGH (0x0050) /* MAC Address High */ +#define REG_ADDR_LOW (0x0054) /* MAC Address Low */ +#define REG_TX_DMA_STA (0x00B0) /* Transmit DMA Status */ +#define REG_TX_CUR_DESC (0x00B4) /* Transmit Current Descriptor */ +#define REG_TX_CUR_BUF (0x00B8) /* Transmit Current Buffer */ +#define REG_RX_DMA_STA (0x00C0) /* Receive DMA Status */ +#define REG_RX_CUR_DESC (0x00C4) /* Receive Current Descriptor */ +#define REG_RX_CUR_BUF (0x00C8) /* Receive Current Buffer */ +#define REG_RGMII_STA (0x00D0) /* RGMII Status */ + +/* EMAC register flags */ +#define BASIC_CTL0_100Mbps (0b11 << 2) +#define BASIC_CTL0_FD (1 << 0) +#define BASIC_CTL1_SOFTRST (1 << 0) + +#define INT_STA_RGMII_LINK (1 << 16) +#define INT_STA_RX_EARLY (1 << 13) +#define INT_STA_RX_OVERFLOW (1 << 12) +#define INT_STA_RX_TIMEOUT (1 << 11) +#define INT_STA_RX_DMA_STOP (1 << 10) +#define INT_STA_RX_BUF_UA (1 << 9) +#define INT_STA_RX (1 << 8) +#define INT_STA_TX_EARLY (1 << 5) +#define INT_STA_TX_UNDERFLOW (1 << 4) +#define INT_STA_TX_TIMEOUT (1 << 3) +#define INT_STA_TX_BUF_UA (1 << 2) +#define INT_STA_TX_DMA_STOP (1 << 1) +#define INT_STA_TX (1 << 0) + +#define INT_EN_RX_EARLY (1 << 13) +#define INT_EN_RX_OVERFLOW (1 << 12) +#define INT_EN_RX_TIMEOUT (1 << 11) +#define INT_EN_RX_DMA_STOP (1 << 10) +#define INT_EN_RX_BUF_UA (1 << 9) +#define INT_EN_RX (1 << 8) +#define INT_EN_TX_EARLY (1 << 5) +#define INT_EN_TX_UNDERFLOW (1 << 4) +#define INT_EN_TX_TIMEOUT (1 << 3) +#define INT_EN_TX_BUF_UA (1 << 2) +#define INT_EN_TX_DMA_STOP (1 << 1) +#define INT_EN_TX (1 << 0) + +#define TX_CTL0_TX_EN (1 << 31) +#define TX_CTL1_TX_DMA_START (1 << 31) +#define TX_CTL1_TX_DMA_EN (1 << 30) +#define TX_CTL1_TX_FLUSH (1 << 0) + +#define RX_CTL0_RX_EN (1 << 31) +#define RX_CTL0_STRIP_FCS (1 << 28) +#define RX_CTL0_CRC_IPV4 (1 << 27) + +#define RX_CTL1_RX_DMA_START (1 << 31) +#define RX_CTL1_RX_DMA_EN (1 << 30) +#define RX_CTL1_RX_MD (1 << 1) + +#define RX_FRM_FLT_DIS_ADDR (1 << 31) + +#define MII_CMD_PHY_ADDR_SHIFT (12) +#define MII_CMD_PHY_ADDR_MASK (0xf000) +#define MII_CMD_PHY_REG_SHIFT (4) +#define MII_CMD_PHY_REG_MASK (0xf0) +#define MII_CMD_PHY_RW (1 << 1) +#define MII_CMD_PHY_BUSY (1 << 0) + +#define TX_DMA_STA_STOP (0b000) +#define TX_DMA_STA_RUN_FETCH (0b001) +#define TX_DMA_STA_WAIT_STA (0b010) + +#define RX_DMA_STA_STOP (0b000) +#define RX_DMA_STA_RUN_FETCH (0b001) +#define RX_DMA_STA_WAIT_FRM (0b011) + +#define RGMII_LINK_UP (1 << 3) +#define RGMII_FD (1 << 0) + +/* EMAC register reset values */ +#define REG_BASIC_CTL_1_RST (0x08000000) + +/* EMAC constants */ +#define AW_H3_EMAC_MIN_PKT_SZ (64) + +/* Transmit/receive frame descriptor */ +typedef struct FrameDescriptor { + uint32_t status; + uint32_t status2; + uint32_t addr; + uint32_t next; +} FrameDescriptor; + +/* Frame descriptor flags */ +#define DESC_STATUS_CTL (1 << 31) +#define DESC_STATUS2_BUF_SIZE_MASK (0x7ff) + +/* Transmit frame descriptor flags */ +#define TX_DESC_STATUS_LENGTH_ERR (1 << 14) +#define TX_DESC_STATUS2_FIRST_DESC (1 << 29) +#define TX_DESC_STATUS2_LAST_DESC (1 << 30) +#define TX_DESC_STATUS2_CHECKSUM_MASK (0x3 << 27) + +/* Receive frame descriptor flags */ +#define RX_DESC_STATUS_FIRST_DESC (1 << 9) +#define RX_DESC_STATUS_LAST_DESC (1 << 8) +#define RX_DESC_STATUS_FRM_LEN_MASK (0x3fff0000) +#define RX_DESC_STATUS_FRM_LEN_SHIFT (16) +#define RX_DESC_STATUS_NO_BUF (1 << 14) +#define RX_DESC_STATUS_HEADER_ERR (1 << 7) +#define RX_DESC_STATUS_LENGTH_ERR (1 << 4) +#define RX_DESC_STATUS_CRC_ERR (1 << 1) +#define RX_DESC_STATUS_PAYLOAD_ERR (1 << 0) +#define RX_DESC_STATUS2_RX_INT_CTL (1 << 31) + +/* MII register offsets */ +#define MII_REG_CR (0x0) +#define MII_REG_ST (0x1) +#define MII_REG_ID_HIGH (0x2) +#define MII_REG_ID_LOW (0x3) + +/* MII register flags */ +#define MII_REG_CR_RESET (1 << 15) +#define MII_REG_CR_POWERDOWN (1 << 11) +#define MII_REG_CR_10Mbit (0) +#define MII_REG_CR_100Mbit (1 << 13) +#define MII_REG_CR_1000Mbit (1 << 6) +#define MII_REG_CR_AUTO_NEG (1 << 12) +#define MII_REG_CR_AUTO_NEG_RESTART (1 << 9) +#define MII_REG_CR_FULLDUPLEX (1 << 8) + +#define MII_REG_ST_100BASE_T4 (1 << 15) +#define MII_REG_ST_100BASE_X_FD (1 << 14) +#define MII_REG_ST_100BASE_X_HD (1 << 13) +#define MII_REG_ST_10_FD (1 << 12) +#define MII_REG_ST_10_HD (1 << 11) +#define MII_REG_ST_100BASE_T2_FD (1 << 10) +#define MII_REG_ST_100BASE_T2_HD (1 << 9) +#define MII_REG_ST_AUTONEG_COMPLETE (1 << 5) +#define MII_REG_ST_AUTONEG_AVAIL (1 << 3) +#define MII_REG_ST_LINK_UP (1 << 2) + +/* MII constants */ +#define MII_PHY_ID_HIGH (0x0044) +#define MII_PHY_ID_LOW (0x1400) + +static void aw_h3_emac_mii_set_link(AwH3EmacState *s, bool link_active) +{ + if (link_active) { + s->mii_st |= MII_REG_ST_LINK_UP; + } else { + s->mii_st &= ~MII_REG_ST_LINK_UP; + } +} + +static void aw_h3_emac_mii_reset(AwH3EmacState *s, bool link_active) +{ + s->mii_cr = MII_REG_CR_100Mbit | MII_REG_CR_AUTO_NEG | + MII_REG_CR_FULLDUPLEX; + s->mii_st = MII_REG_ST_100BASE_T4 | MII_REG_ST_100BASE_X_FD | + MII_REG_ST_100BASE_X_HD | MII_REG_ST_10_FD | MII_REG_ST_10_HD | + MII_REG_ST_100BASE_T2_FD | MII_REG_ST_100BASE_T2_HD | + MII_REG_ST_AUTONEG_COMPLETE | MII_REG_ST_AUTONEG_AVAIL; + + aw_h3_emac_mii_set_link(s, link_active); +} + +static void aw_h3_emac_mii_cmd(AwH3EmacState *s) +{ + uint8_t addr, reg; + + addr = (s->mii_cmd & MII_CMD_PHY_ADDR_MASK) >> MII_CMD_PHY_ADDR_SHIFT; + reg = (s->mii_cmd & MII_CMD_PHY_REG_MASK) >> MII_CMD_PHY_REG_SHIFT; + + if (addr != s->mii_phy_addr) { + return; + } + + /* Read or write a PHY register? */ + if (s->mii_cmd & MII_CMD_PHY_RW) { + trace_aw_h3_emac_mii_write_reg(reg, s->mii_data); + + switch (reg) { + case MII_REG_CR: + if (s->mii_data & MII_REG_CR_RESET) { + aw_h3_emac_mii_reset(s, s->mii_st & MII_REG_ST_LINK_UP); + } else { + s->mii_cr = s->mii_data & ~(MII_REG_CR_RESET | + MII_REG_CR_AUTO_NEG_RESTART); + } + break; + default: + qemu_log_mask(LOG_UNIMP, "allwinner-h3-emac: write access to " + "unknown MII register 0x%x\n", reg); + break; + } + } else { + switch (reg) { + case MII_REG_CR: + s->mii_data = s->mii_cr; + break; + case MII_REG_ST: + s->mii_data = s->mii_st; + break; + case MII_REG_ID_HIGH: + s->mii_data = MII_PHY_ID_HIGH; + break; + case MII_REG_ID_LOW: + s->mii_data = MII_PHY_ID_LOW; + break; + default: + qemu_log_mask(LOG_UNIMP, "allwinner-h3-emac: read access to " + "unknown MII register 0x%x\n", reg); + s->mii_data = 0; + break; + } + + trace_aw_h3_emac_mii_read_reg(reg, s->mii_data); + } +} + +static void aw_h3_emac_update_irq(AwH3EmacState *s) +{ + qemu_set_irq(s->irq, (s->int_sta & s->int_en) != 0); +} + +static uint32_t aw_h3_emac_next_desc(FrameDescriptor *desc, size_t min_size) +{ + uint32_t paddr = desc->next; + + cpu_physical_memory_read(paddr, desc, sizeof(*desc)); + + if ((desc->status & DESC_STATUS_CTL) && + (desc->status2 & DESC_STATUS2_BUF_SIZE_MASK) >= min_size) { + return paddr; + } else { + return 0; + } +} + +static uint32_t aw_h3_emac_get_desc(FrameDescriptor *desc, uint32_t start_addr, + size_t min_size) +{ + uint32_t desc_addr = start_addr; + + /* Note that the list is a cycle. Last entry points back to the head. */ + while (desc_addr != 0) { + cpu_physical_memory_read(desc_addr, desc, sizeof(*desc)); + + if ((desc->status & DESC_STATUS_CTL) && + (desc->status2 & DESC_STATUS2_BUF_SIZE_MASK) >= min_size) { + return desc_addr; + } else if (desc->next == start_addr) { + break; + } else { + desc_addr = desc->next; + } + } + + return 0; +} + +static uint32_t aw_h3_emac_get_rx_desc(AwH3EmacState *s, FrameDescriptor *desc, + size_t min_size) +{ + return aw_h3_emac_get_desc(desc, s->rx_desc_curr, min_size); +} + +static uint32_t aw_h3_emac_get_tx_desc(AwH3EmacState *s, FrameDescriptor *desc, + size_t min_size) +{ + return aw_h3_emac_get_desc(desc, s->tx_desc_head, min_size); +} + +static void aw_h3_emac_flush_desc(FrameDescriptor *desc, uint32_t phys_addr) +{ + cpu_physical_memory_write(phys_addr, desc, sizeof(*desc)); +} + +static int aw_h3_emac_can_receive(NetClientState *nc) +{ + AwH3EmacState *s = qemu_get_nic_opaque(nc); + FrameDescriptor desc; + + return (s->rx_ctl0 & RX_CTL0_RX_EN) && + (aw_h3_emac_get_rx_desc(s, &desc, 0) != 0); +} + +static ssize_t aw_h3_emac_receive(NetClientState *nc, const uint8_t *buf, + size_t size) +{ + AwH3EmacState *s = qemu_get_nic_opaque(nc); + FrameDescriptor desc; + size_t bytes_left = size; + size_t desc_bytes = 0; + size_t pad_fcs_size = 4; + size_t padding = 0; + + if (!(s->rx_ctl0 & RX_CTL0_RX_EN)) { + return -1; + } + + s->rx_desc_curr = aw_h3_emac_get_rx_desc(s, &desc, AW_H3_EMAC_MIN_PKT_SZ); + if (!s->rx_desc_curr) { + s->int_sta |= INT_STA_RX_BUF_UA; + } + + /* Keep filling RX descriptors until the whole frame is written */ + while (s->rx_desc_curr && bytes_left > 0) { + desc.status &= ~DESC_STATUS_CTL; + desc.status &= ~RX_DESC_STATUS_FRM_LEN_MASK; + + if (bytes_left == size) { + desc.status |= RX_DESC_STATUS_FIRST_DESC; + } + + if ((desc.status2 & DESC_STATUS2_BUF_SIZE_MASK) < + (bytes_left + pad_fcs_size)) { + desc_bytes = desc.status2 & DESC_STATUS2_BUF_SIZE_MASK; + desc.status |= desc_bytes << RX_DESC_STATUS_FRM_LEN_SHIFT; + } else { + padding = pad_fcs_size; + if (bytes_left < AW_H3_EMAC_MIN_PKT_SZ) { + padding += (AW_H3_EMAC_MIN_PKT_SZ - bytes_left); + } + + desc_bytes = (bytes_left); + desc.status |= RX_DESC_STATUS_LAST_DESC; + desc.status |= (bytes_left + padding) + << RX_DESC_STATUS_FRM_LEN_SHIFT; + } + + cpu_physical_memory_write(desc.addr, buf, desc_bytes); + aw_h3_emac_flush_desc(&desc, s->rx_desc_curr); + trace_aw_h3_emac_receive(s->rx_desc_curr, desc.addr, desc_bytes); + + /* Check if frame needs to raise the receive interrupt */ + if (!(desc.status2 & RX_DESC_STATUS2_RX_INT_CTL)) { + s->int_sta |= INT_STA_RX; + } + + /* Increment variables */ + buf += desc_bytes; + bytes_left -= desc_bytes; + + /* Move to the next descriptor */ + s->rx_desc_curr = aw_h3_emac_next_desc(&desc, 64); + if (!s->rx_desc_curr) { + /* Not enough buffer space available */ + s->int_sta |= INT_STA_RX_BUF_UA; + s->rx_desc_curr = s->rx_desc_head; + break; + } + } + + /* Report receive DMA is finished */ + s->rx_ctl1 &= ~RX_CTL1_RX_DMA_START; + aw_h3_emac_update_irq(s); + + return size; +} + +static void aw_h3_emac_transmit(AwH3EmacState *s) +{ + NetClientState *nc = qemu_get_queue(s->nic); + FrameDescriptor desc; + size_t bytes = 0; + size_t packet_bytes = 0; + size_t transmitted = 0; + static uint8_t packet_buf[2048]; + + s->tx_desc_curr = aw_h3_emac_get_tx_desc(s, &desc, 0); + + /* Read all transmit descriptors */ + while (s->tx_desc_curr != 0) { + + /* Read from physical memory into packet buffer */ + bytes = desc.status2 & DESC_STATUS2_BUF_SIZE_MASK; + if (bytes + packet_bytes > sizeof(packet_buf)) { + desc.status |= TX_DESC_STATUS_LENGTH_ERR; + break; + } + cpu_physical_memory_read(desc.addr, packet_buf + packet_bytes, bytes); + packet_bytes += bytes; + desc.status &= ~DESC_STATUS_CTL; + aw_h3_emac_flush_desc(&desc, s->tx_desc_curr); + + /* After the last descriptor, send the packet */ + if (desc.status2 & TX_DESC_STATUS2_LAST_DESC) { + if (desc.status2 & TX_DESC_STATUS2_CHECKSUM_MASK) { + net_checksum_calculate(packet_buf, packet_bytes); + } + + qemu_send_packet(nc, packet_buf, packet_bytes); + trace_aw_h3_emac_transmit(s->tx_desc_curr, desc.addr, bytes); + + packet_bytes = 0; + transmitted++; + } + s->tx_desc_curr = aw_h3_emac_next_desc(&desc, 0); + } + + /* Raise transmit completed interrupt */ + if (transmitted > 0) { + s->int_sta |= INT_STA_TX; + s->tx_ctl1 &= ~TX_CTL1_TX_DMA_START; + aw_h3_emac_update_irq(s); + } +} + +static void aw_h3_emac_reset(DeviceState *dev) +{ + AwH3EmacState *s = AW_H3_EMAC(dev); + NetClientState *nc = qemu_get_queue(s->nic); + + trace_aw_h3_emac_reset(); + + s->mii_cmd = 0; + s->mii_data = 0; + s->basic_ctl0 = 0; + s->basic_ctl1 = 0; + s->int_en = 0; + s->int_sta = 0; + s->frm_flt = 0; + s->rx_ctl0 = 0; + s->rx_ctl1 = RX_CTL1_RX_MD; + s->rx_desc_head = 0; + s->rx_desc_curr = 0; + s->tx_ctl0 = 0; + s->tx_ctl1 = 0; + s->tx_desc_head = 0; + s->tx_desc_curr = 0; + s->tx_flowctl = 0; + + aw_h3_emac_mii_reset(s, !nc->link_down); +} + +static uint64_t aw_h3_emac_read(void *opaque, hwaddr offset, unsigned size) +{ + AwH3EmacState *s = opaque; + uint64_t value = 0; + FrameDescriptor desc; + + switch (offset) { + case REG_BASIC_CTL_0: /* Basic Control 0 */ + value = s->basic_ctl0; + break; + case REG_BASIC_CTL_1: /* Basic Control 1 */ + value = s->basic_ctl1; + break; + case REG_INT_STA: /* Interrupt Status */ + value = s->int_sta; + break; + case REG_INT_EN: /* Interupt Enable */ + value = s->int_en; + break; + case REG_TX_CTL_0: /* Transmit Control 0 */ + value = s->tx_ctl0; + break; + case REG_TX_CTL_1: /* Transmit Control 1 */ + value = s->tx_ctl1; + break; + case REG_TX_FLOW_CTL: /* Transmit Flow Control */ + value = s->tx_flowctl; + break; + case REG_TX_DMA_DESC_LIST: /* Transmit Descriptor List Address */ + value = s->tx_desc_head; + break; + case REG_RX_CTL_0: /* Receive Control 0 */ + value = s->rx_ctl0; + break; + case REG_RX_CTL_1: /* Receive Control 1 */ + value = s->rx_ctl1; + break; + case REG_RX_DMA_DESC_LIST: /* Receive Descriptor List Address */ + value = s->rx_desc_head; + break; + case REG_FRM_FLT: /* Receive Frame Filter */ + value = s->frm_flt; + break; + case REG_RX_HASH_0: /* Receive Hash Table 0 */ + case REG_RX_HASH_1: /* Receive Hash Table 1 */ + break; + case REG_MII_CMD: /* Management Interface Command */ + value = s->mii_cmd; + break; + case REG_MII_DATA: /* Management Interface Data */ + value = s->mii_data; + break; + case REG_ADDR_HIGH: /* MAC Address High */ + value = *(((uint32_t *) (s->conf.macaddr.a)) + 1); + break; + case REG_ADDR_LOW: /* MAC Address Low */ + value = *(uint32_t *) (s->conf.macaddr.a); + break; + case REG_TX_DMA_STA: /* Transmit DMA Status */ + break; + case REG_TX_CUR_DESC: /* Transmit Current Descriptor */ + value = s->tx_desc_curr; + break; + case REG_TX_CUR_BUF: /* Transmit Current Buffer */ + if (s->tx_desc_curr != 0) { + cpu_physical_memory_read(s->tx_desc_curr, &desc, sizeof(desc)); + value = desc.addr; + } else { + value = 0; + } + break; + case REG_RX_DMA_STA: /* Receive DMA Status */ + break; + case REG_RX_CUR_DESC: /* Receive Current Descriptor */ + value = s->rx_desc_curr; + break; + case REG_RX_CUR_BUF: /* Receive Current Buffer */ + if (s->rx_desc_curr != 0) { + cpu_physical_memory_read(s->rx_desc_curr, &desc, sizeof(desc)); + value = desc.addr; + } else { + value = 0; + } + break; + default: + qemu_log_mask(LOG_UNIMP, "allwinner-h3-emac: read access to unknown " + "EMAC register 0x" TARGET_FMT_plx "\n", + offset); + } + + trace_aw_h3_emac_read(offset, value); + return value; +} + +static void aw_h3_emac_write(void *opaque, hwaddr offset, uint64_t value, + unsigned size) +{ + AwH3EmacState *s = opaque; + NetClientState *nc = qemu_get_queue(s->nic); + + trace_aw_h3_emac_write(offset, value); + + switch (offset) { + case REG_BASIC_CTL_0: /* Basic Control 0 */ + s->basic_ctl0 = value; + break; + case REG_BASIC_CTL_1: /* Basic Control 1 */ + if (value & BASIC_CTL1_SOFTRST) { + aw_h3_emac_reset(DEVICE(s)); + value &= ~BASIC_CTL1_SOFTRST; + } + s->basic_ctl1 = value; + if (aw_h3_emac_can_receive(nc)) { + qemu_flush_queued_packets(nc); + } + break; + case REG_INT_STA: /* Interrupt Status */ + s->int_sta &= ~value; + aw_h3_emac_update_irq(s); + break; + case REG_INT_EN: /* Interrupt Enable */ + s->int_en = value; + aw_h3_emac_update_irq(s); + break; + case REG_TX_CTL_0: /* Transmit Control 0 */ + s->tx_ctl0 = value; + break; + case REG_TX_CTL_1: /* Transmit Control 1 */ + s->tx_ctl1 = value; + if (value & TX_CTL1_TX_DMA_EN) { + aw_h3_emac_transmit(s); + } + break; + case REG_TX_FLOW_CTL: /* Transmit Flow Control */ + s->tx_flowctl = value; + break; + case REG_TX_DMA_DESC_LIST: /* Transmit Descriptor List Address */ + s->tx_desc_head = value; + s->tx_desc_curr = value; + break; + case REG_RX_CTL_0: /* Receive Control 0 */ + s->rx_ctl0 = value; + break; + case REG_RX_CTL_1: /* Receive Control 1 */ + s->rx_ctl1 = value | RX_CTL1_RX_MD; + if ((value & RX_CTL1_RX_DMA_EN) && aw_h3_emac_can_receive(nc)) { + qemu_flush_queued_packets(nc); + } + break; + case REG_RX_DMA_DESC_LIST: /* Receive Descriptor List Address */ + s->rx_desc_head = value; + s->rx_desc_curr = value; + break; + case REG_FRM_FLT: /* Receive Frame Filter */ + s->frm_flt = value; + break; + case REG_RX_HASH_0: /* Receive Hash Table 0 */ + case REG_RX_HASH_1: /* Receive Hash Table 1 */ + break; + case REG_MII_CMD: /* Management Interface Command */ + s->mii_cmd = value & ~MII_CMD_PHY_BUSY; + aw_h3_emac_mii_cmd(s); + break; + case REG_MII_DATA: /* Management Interface Data */ + s->mii_data = value; + break; + case REG_ADDR_HIGH: /* MAC Address High */ + s->conf.macaddr.a[4] = (value & 0xff); + s->conf.macaddr.a[5] = (value & 0xff00) >> 8; + break; + case REG_ADDR_LOW: /* MAC Address Low */ + s->conf.macaddr.a[0] = (value & 0xff); + s->conf.macaddr.a[1] = (value & 0xff00) >> 8; + s->conf.macaddr.a[2] = (value & 0xff0000) >> 16; + s->conf.macaddr.a[3] = (value & 0xff000000) >> 24; + break; + case REG_TX_DMA_STA: /* Transmit DMA Status */ + case REG_TX_CUR_DESC: /* Transmit Current Descriptor */ + case REG_TX_CUR_BUF: /* Transmit Current Buffer */ + case REG_RX_DMA_STA: /* Receive DMA Status */ + case REG_RX_CUR_DESC: /* Receive Current Descriptor */ + case REG_RX_CUR_BUF: /* Receive Current Buffer */ + case REG_RGMII_STA: /* RGMII Status */ + break; + default: + qemu_log_mask(LOG_UNIMP, "allwinner-h3-emac: write access to unknown " + "EMAC register 0x" TARGET_FMT_plx "\n", + offset); + } +} + +static void aw_h3_emac_set_link(NetClientState *nc) +{ + AwH3EmacState *s = qemu_get_nic_opaque(nc); + + trace_aw_h3_emac_set_link(!nc->link_down); + aw_h3_emac_mii_set_link(s, !nc->link_down); +} + +static const MemoryRegionOps aw_h3_emac_mem_ops = { + .read = aw_h3_emac_read, + .write = aw_h3_emac_write, + .endianness = DEVICE_NATIVE_ENDIAN, + .valid = { + .min_access_size = 4, + .max_access_size = 4, + }, +}; + +static NetClientInfo net_aw_h3_emac_info = { + .type = NET_CLIENT_DRIVER_NIC, + .size = sizeof(NICState), + .can_receive = aw_h3_emac_can_receive, + .receive = aw_h3_emac_receive, + .link_status_changed = aw_h3_emac_set_link, +}; + +static void aw_h3_emac_init(Object *obj) +{ + SysBusDevice *sbd = SYS_BUS_DEVICE(obj); + AwH3EmacState *s = AW_H3_EMAC(obj); + + memory_region_init_io(&s->iomem, OBJECT(s), &aw_h3_emac_mem_ops, s, + TYPE_AW_H3_EMAC, AW_H3_EMAC_REGS_MEM_SIZE); + sysbus_init_mmio(sbd, &s->iomem); + sysbus_init_irq(sbd, &s->irq); +} + +static void aw_h3_emac_realize(DeviceState *dev, Error **errp) +{ + AwH3EmacState *s = AW_H3_EMAC(dev); + + qemu_macaddr_default_if_unset(&s->conf.macaddr); + s->nic = qemu_new_nic(&net_aw_h3_emac_info, &s->conf, + object_get_typename(OBJECT(dev)), dev->id, s); + qemu_format_nic_info_str(qemu_get_queue(s->nic), s->conf.macaddr.a); +} + +static Property aw_h3_emac_properties[] = { + DEFINE_NIC_PROPERTIES(AwH3EmacState, conf), + DEFINE_PROP_UINT8("phy-addr", AwH3EmacState, mii_phy_addr, 0), + DEFINE_PROP_END_OF_LIST(), +}; + +static int aw_h3_emac_post_load(void *opaque, int version_id) +{ + AwH3EmacState *s = opaque; + + aw_h3_emac_set_link(qemu_get_queue(s->nic)); + + return 0; +} + +static const VMStateDescription vmstate_aw_emac = { + .name = TYPE_AW_H3_EMAC, + .version_id = 1, + .minimum_version_id = 1, + .post_load = aw_h3_emac_post_load, + .fields = (VMStateField[]) { + VMSTATE_UINT8(mii_phy_addr, AwH3EmacState), + VMSTATE_UINT32(mii_cmd, AwH3EmacState), + VMSTATE_UINT32(mii_data, AwH3EmacState), + VMSTATE_UINT32(basic_ctl0, AwH3EmacState), + VMSTATE_UINT32(basic_ctl1, AwH3EmacState), + VMSTATE_UINT32(int_en, AwH3EmacState), + VMSTATE_UINT32(int_sta, AwH3EmacState), + VMSTATE_UINT32(frm_flt, AwH3EmacState), + VMSTATE_UINT32(rx_ctl0, AwH3EmacState), + VMSTATE_UINT32(rx_ctl1, AwH3EmacState), + VMSTATE_UINT32(rx_desc_head, AwH3EmacState), + VMSTATE_UINT32(rx_desc_curr, AwH3EmacState), + VMSTATE_UINT32(tx_ctl0, AwH3EmacState), + VMSTATE_UINT32(tx_ctl1, AwH3EmacState), + VMSTATE_UINT32(tx_desc_head, AwH3EmacState), + VMSTATE_UINT32(tx_desc_curr, AwH3EmacState), + VMSTATE_UINT32(tx_flowctl, AwH3EmacState), + VMSTATE_END_OF_LIST() + } +}; + +static void aw_h3_emac_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + + dc->realize = aw_h3_emac_realize; + dc->props = aw_h3_emac_properties; + dc->reset = aw_h3_emac_reset; + dc->vmsd = &vmstate_aw_emac; +} + +static const TypeInfo aw_h3_emac_info = { + .name = TYPE_AW_H3_EMAC, + .parent = TYPE_SYS_BUS_DEVICE, + .instance_size = sizeof(AwH3EmacState), + .instance_init = aw_h3_emac_init, + .class_init = aw_h3_emac_class_init, +}; + +static void aw_h3_emac_register_types(void) +{ + type_register_static(&aw_h3_emac_info); +} + +type_init(aw_h3_emac_register_types) diff --git a/hw/net/trace-events b/hw/net/trace-events index e70f12bee1..e9e2f26f68 100644 --- a/hw/net/trace-events +++ b/hw/net/trace-events @@ -1,5 +1,15 @@ # See docs/devel/tracing.txt for syntax documentation. +# allwinner-h3-emac.c +aw_h3_emac_mii_write_reg(uint32_t reg, uint32_t value) "MII write: reg=0x%x value=0x%x" +aw_h3_emac_mii_read_reg(uint32_t reg, uint32_t value) "MII read: reg=0x%x value=0x%x" +aw_h3_emac_receive(uint32_t desc, uint32_t paddr, uint32_t bytes) "RX packet: desc=0x%08x paddr=0x%08x bytes=%u" +aw_h3_emac_transmit(uint32_t desc, uint32_t paddr, uint32_t bytes) "TX packet: desc=0x%08x paddr=0x%08x bytes=%u" +aw_h3_emac_reset(void) "HW reset" +aw_h3_emac_set_link(bool active) "Set link: active=%u" +aw_h3_emac_read(uint64_t offset, uint64_t val) "MMIO read: offset=0x%" PRIx64 " value=0x%" PRIx64 +aw_h3_emac_write(uint64_t offset, uint64_t val) "MMIO write: offset=0x%" PRIx64 " value=0x%" PRIx64 + # etraxfs_eth.c mdio_phy_read(int regnum, uint16_t value) "read phy_reg:%d value:0x%04x" mdio_phy_write(int regnum, uint16_t value) "write phy_reg:%d value:0x%04x" diff --git a/include/hw/arm/allwinner-h3.h b/include/hw/arm/allwinner-h3.h index 7aff4ebbd2..b964a60f41 100644 --- a/include/hw/arm/allwinner-h3.h +++ b/include/hw/arm/allwinner-h3.h @@ -31,6 +31,7 @@ #include "hw/misc/allwinner-h3-syscon.h" #include "hw/misc/allwinner-h3-sid.h" #include "hw/sd/allwinner-h3-sdhost.h" +#include "hw/net/allwinner-h3-emac.h" #include "target/arm/cpu.h" #define AW_H3_SRAM_A1_BASE (0x00000000) @@ -119,6 +120,7 @@ typedef struct AwH3State { AwH3SysconState syscon; AwH3SidState sid; AwH3SDHostState mmc0; + AwH3EmacState emac; GICState gic; MemoryRegion sram_a1; MemoryRegion sram_a2; diff --git a/include/hw/net/allwinner-h3-emac.h b/include/hw/net/allwinner-h3-emac.h new file mode 100644 index 0000000000..a007d54472 --- /dev/null +++ b/include/hw/net/allwinner-h3-emac.h @@ -0,0 +1,69 @@ +/* + * Allwinner H3 EMAC emulation + * + * Copyright (C) 2019 Niek Linnenbank + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#ifndef ALLWINNER_H3_EMAC_H +#define ALLWINNER_H3_EMAC_H + +#include "qemu/units.h" +#include "net/net.h" +#include "qemu/fifo8.h" +#include "hw/net/mii.h" +#include "hw/sysbus.h" + +#define AW_H3_EMAC_REGS_MEM_SIZE (1024) + +#define TYPE_AW_H3_EMAC "allwinner-h3-emac" +#define AW_H3_EMAC(obj) OBJECT_CHECK(AwH3EmacState, (obj), TYPE_AW_H3_EMAC) + +typedef struct AwH3EmacState { + /*< private >*/ + SysBusDevice parent_obj; + /*< public >*/ + + MemoryRegion iomem; + qemu_irq irq; + NICState *nic; + NICConf conf; + + uint8_t mii_phy_addr; + uint32_t mii_cmd; + uint32_t mii_data; + uint32_t mii_cr; + uint32_t mii_st; + + uint32_t basic_ctl0; + uint32_t basic_ctl1; + uint32_t int_en; + uint32_t int_sta; + uint32_t frm_flt; + + uint32_t rx_ctl0; + uint32_t rx_ctl1; + uint32_t rx_desc_head; + uint32_t rx_desc_curr; + + uint32_t tx_ctl0; + uint32_t tx_ctl1; + uint32_t tx_desc_head; + uint32_t tx_desc_curr; + uint32_t tx_flowctl; + +} AwH3EmacState; + +#endif -- 2.17.1 From MAILER-DAEMON Mon Dec 02 16:38:06 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1ibtOQ-00041u-B9 for mharc-qemu-arm@gnu.org; Mon, 02 Dec 2019 16:38:06 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:38538) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ibsxp-0002rt-Sm for qemu-arm@nongnu.org; Mon, 02 Dec 2019 16:10:41 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ibsxn-0000sW-3a for qemu-arm@nongnu.org; Mon, 02 Dec 2019 16:10:37 -0500 Received: from mail-wm1-x342.google.com ([2a00:1450:4864:20::342]:33689) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ibsxY-0000YO-Ji; Mon, 02 Dec 2019 16:10:22 -0500 Received: by mail-wm1-x342.google.com with SMTP id y23so780786wma.0; Mon, 02 Dec 2019 13:09:59 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=vNPnXm90420wfmia3L0ifKw7OOjXJ8KY6gwGS45HUo8=; b=jUE3wTae+CEXqBH+qobldNTykiKtKaI5y024fUALUm85+MBqeKaWT8wYx7isud0qlO ZG7n7o7ce3Kv+YtVH46HXLo1lIPR42HlGeihxjRQfzQ/S5ISAPpwtYO/dYFLPpaFfCKg 4xLjVJ4DAxaVYI+QxqBc71XJkTACs57pawYNnayTBycco/8R3uB6c32URRV+0mxh1BY5 Ljtmc6yy4aAzF07ZXBIaSo4XcFOWtgyuu4ndOunZ0etsfpio+yS6lrSuznf5dUIL1uRi OIWfxLmbV1i/DKljVEhqlqA2lH6nDqaGZCJoSHb/XixqSI7KPtsGJvl5ZdnmyZlFYE6O cawg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=vNPnXm90420wfmia3L0ifKw7OOjXJ8KY6gwGS45HUo8=; b=bU5Ghv34ozKgj1FBhdt7ZK1rr04uu9CUlqmu7ORhoBMA9LdXR7cxO3TW1A7V8MqKi7 kDn9MLGWwiTmvd+Wk8G+IfmI40wQwB+177Gfd+v0wADkIyIX1ODx+zmRFz7GMuN12Gx8 xEN6rwupgsFQVvMVfelbqfWBVuRhW28wFeNFayNQ6LU8OJwItZ0+vGsJbB1HYEG1Ib0r iOEqhbB7ViUYKFGxEgKSkYAYl1N3JcD05c5s+JjukWfoCzabqx/1zIslUQcgTz9zkcAc 9jTlHJv/m8JMoBkZfNFzjBe9ynzdthijBTUvYrRnU4jePEoBimEHwcFcmVIa45LrRopS gxpQ== X-Gm-Message-State: APjAAAVDvVxUWWBioggDQSbmQ+IqccJeR2HjxBeOPoBefZ7eaNcRtHV9 c1o63W2BYsPwm0t4yq2J81freb38 X-Google-Smtp-Source: APXvYqxeBoOb/sPHDEPYgUAT813SkyzEU6elzQvDLZAJpyE+HN96qGj+sGLy4QLAEmUNclTPbBDOCw== X-Received: by 2002:a1c:f416:: with SMTP id z22mr29848373wma.72.1575320997882; Mon, 02 Dec 2019 13:09:57 -0800 (PST) Received: from pavilion.home ([2a02:a456:6be8:1:8edc:d4ff:fe8b:18b7]) by smtp.gmail.com with ESMTPSA id f1sm770859wrp.93.2019.12.02.13.09.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 02 Dec 2019 13:09:56 -0800 (PST) From: Niek Linnenbank To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, peter.maydell@linaro.org, b.galvani@gmail.com, Niek Linnenbank Subject: [PATCH 01/10] hw: arm: add Allwinner H3 System-on-Chip Date: Mon, 2 Dec 2019 22:09:38 +0100 Message-Id: <20191202210947.3603-2-nieklinnenbank@gmail.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20191202210947.3603-1-nieklinnenbank@gmail.com> References: <20191202210947.3603-1-nieklinnenbank@gmail.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::342 X-Mailman-Approved-At: Mon, 02 Dec 2019 16:38:01 -0500 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 02 Dec 2019 21:10:42 -0000 The Allwinner H3 is a System on Chip containing four ARM Cortex A7 processor cores. Features and specifications include DDR2/DDR3 memory, SD/MMC storage cards, 10/100/1000Mbit ethernet, USB 2.0, HDMI and various I/O modules. This commit adds support for the Allwinner H3 System on Chip. Signed-off-by: Niek Linnenbank --- MAINTAINERS | 7 ++ default-configs/arm-softmmu.mak | 1 + hw/arm/Kconfig | 8 ++ hw/arm/Makefile.objs | 1 + hw/arm/allwinner-h3.c | 215 ++++++++++++++++++++++++++++++++ include/hw/arm/allwinner-h3.h | 118 ++++++++++++++++++ 6 files changed, 350 insertions(+) create mode 100644 hw/arm/allwinner-h3.c create mode 100644 include/hw/arm/allwinner-h3.h diff --git a/MAINTAINERS b/MAINTAINERS index 5e5e3e52d6..29c9936037 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -479,6 +479,13 @@ F: hw/*/allwinner* F: include/hw/*/allwinner* F: hw/arm/cubieboard.c +Allwinner-h3 +M: Niek Linnenbank +L: qemu-arm@nongnu.org +S: Maintained +F: hw/*/allwinner-h3* +F: include/hw/*/allwinner-h3* + ARM PrimeCell and CMSDK devices M: Peter Maydell L: qemu-arm@nongnu.org diff --git a/default-configs/arm-softmmu.mak b/default-configs/arm-softmmu.mak index 1f2e0e7fde..d75a239c2c 100644 --- a/default-configs/arm-softmmu.mak +++ b/default-configs/arm-softmmu.mak @@ -40,3 +40,4 @@ CONFIG_FSL_IMX25=y CONFIG_FSL_IMX7=y CONFIG_FSL_IMX6UL=y CONFIG_SEMIHOSTING=y +CONFIG_ALLWINNER_H3=y diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig index c6e7782580..ebf8d2325f 100644 --- a/hw/arm/Kconfig +++ b/hw/arm/Kconfig @@ -291,6 +291,14 @@ config ALLWINNER_A10 select SERIAL select UNIMP +config ALLWINNER_H3 + bool + select ALLWINNER_A10_PIT + select SERIAL + select ARM_TIMER + select ARM_GIC + select UNIMP + config RASPI bool select FRAMEBUFFER diff --git a/hw/arm/Makefile.objs b/hw/arm/Makefile.objs index fe749f65fd..956e496052 100644 --- a/hw/arm/Makefile.objs +++ b/hw/arm/Makefile.objs @@ -34,6 +34,7 @@ obj-$(CONFIG_DIGIC) += digic.o obj-$(CONFIG_OMAP) += omap1.o omap2.o obj-$(CONFIG_STRONGARM) += strongarm.o obj-$(CONFIG_ALLWINNER_A10) += allwinner-a10.o cubieboard.o +obj-$(CONFIG_ALLWINNER_H3) += allwinner-h3.o obj-$(CONFIG_RASPI) += bcm2835_peripherals.o bcm2836.o raspi.o obj-$(CONFIG_STM32F205_SOC) += stm32f205_soc.o obj-$(CONFIG_XLNX_ZYNQMP_ARM) += xlnx-zynqmp.o xlnx-zcu102.o diff --git a/hw/arm/allwinner-h3.c b/hw/arm/allwinner-h3.c new file mode 100644 index 0000000000..470fdfebef --- /dev/null +++ b/hw/arm/allwinner-h3.c @@ -0,0 +1,215 @@ +/* + * Allwinner H3 System on Chip emulation + * + * Copyright (C) 2019 Niek Linnenbank + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#include "qemu/osdep.h" +#include "exec/address-spaces.h" +#include "qapi/error.h" +#include "qemu/module.h" +#include "qemu/units.h" +#include "cpu.h" +#include "hw/sysbus.h" +#include "hw/arm/allwinner-h3.h" +#include "hw/misc/unimp.h" +#include "sysemu/sysemu.h" + +static void aw_h3_init(Object *obj) +{ + AwH3State *s = AW_H3(obj); + + sysbus_init_child_obj(obj, "gic", &s->gic, sizeof(s->gic), + TYPE_ARM_GIC); + + sysbus_init_child_obj(obj, "timer", &s->timer, sizeof(s->timer), + TYPE_AW_A10_PIT); +} + +static void aw_h3_realize(DeviceState *dev, Error **errp) +{ + AwH3State *s = AW_H3(dev); + SysBusDevice *sysbusdev = NULL; + Error *err = NULL; + unsigned i = 0; + + /* CPUs */ + for (i = 0; i < AW_H3_NUM_CPUS; i++) { + Object *cpuobj = object_new(ARM_CPU_TYPE_NAME("cortex-a7")); + CPUState *cpustate = CPU(cpuobj); + + /* Set the proper CPU index */ + cpustate->cpu_index = i; + + /* Provide Power State Coordination Interface */ + object_property_set_int(cpuobj, QEMU_PSCI_CONDUIT_HVC, + "psci-conduit", &error_abort); + + /* Disable secondary CPUs */ + object_property_set_bool(cpuobj, i > 0, "start-powered-off", &err); + if (err != NULL) { + error_propagate(errp, err); + return; + } + + /* All exception levels required */ + object_property_set_bool(cpuobj, + true, "has_el3", NULL); + object_property_set_bool(cpuobj, + true, "has_el2", NULL); + + /* Mark realized */ + object_property_set_bool(cpuobj, true, "realized", &err); + if (err != NULL) { + error_propagate(errp, err); + return; + } + object_unref(cpuobj); + } + + /* Generic Interrupt Controller */ + qdev_prop_set_uint32(DEVICE(&s->gic), "num-irq", AW_H3_GIC_NUM_SPI + + GIC_INTERNAL); + qdev_prop_set_uint32(DEVICE(&s->gic), "revision", 2); + qdev_prop_set_uint32(DEVICE(&s->gic), "num-cpu", AW_H3_NUM_CPUS); + qdev_prop_set_bit(DEVICE(&s->gic), "has-security-extensions", false); + qdev_prop_set_bit(DEVICE(&s->gic), "has-virtualization-extensions", true); + + object_property_set_bool(OBJECT(&s->gic), true, "realized", &err); + if (err) { + error_propagate(errp, err); + return; + } + + sysbusdev = SYS_BUS_DEVICE(&s->gic); + sysbus_mmio_map(sysbusdev, 0, AW_H3_GIC_DIST_BASE); + sysbus_mmio_map(sysbusdev, 1, AW_H3_GIC_CPU_BASE); + sysbus_mmio_map(sysbusdev, 2, AW_H3_GIC_HYP_BASE); + sysbus_mmio_map(sysbusdev, 3, AW_H3_GIC_VCPU_BASE); + + /* + * Wire the outputs from each CPU's generic timer and the GICv3 + * maintenance interrupt signal to the appropriate GIC PPI inputs, + * and the GIC's IRQ/FIQ/VIRQ/VFIQ interrupt outputs to the CPU's inputs. + */ + for (i = 0; i < AW_H3_NUM_CPUS; i++) { + DeviceState *cpudev = DEVICE(qemu_get_cpu(i)); + int ppibase = AW_H3_GIC_NUM_SPI + i * GIC_INTERNAL + GIC_NR_SGIS; + int irq; + /* + * Mapping from the output timer irq lines from the CPU to the + * GIC PPI inputs used for this board. + */ + const int timer_irq[] = { + [GTIMER_PHYS] = AW_H3_GIC_PPI_ARM_PHYSTIMER, + [GTIMER_VIRT] = AW_H3_GIC_PPI_ARM_VIRTTIMER, + [GTIMER_HYP] = AW_H3_GIC_PPI_ARM_HYPTIMER, + [GTIMER_SEC] = AW_H3_GIC_PPI_ARM_SECTIMER, + }; + + /* Connect CPU timer outputs to GIC PPI inputs */ + for (irq = 0; irq < ARRAY_SIZE(timer_irq); irq++) { + qdev_connect_gpio_out(cpudev, irq, + qdev_get_gpio_in(DEVICE(&s->gic), + ppibase + timer_irq[irq])); + } + + /* Connect GIC outputs to CPU interrupt inputs */ + sysbus_connect_irq(sysbusdev, i, + qdev_get_gpio_in(cpudev, ARM_CPU_IRQ)); + sysbus_connect_irq(sysbusdev, i + AW_H3_NUM_CPUS, + qdev_get_gpio_in(cpudev, ARM_CPU_FIQ)); + sysbus_connect_irq(sysbusdev, i + (2 * AW_H3_NUM_CPUS), + qdev_get_gpio_in(cpudev, ARM_CPU_VIRQ)); + sysbus_connect_irq(sysbusdev, i + (3 * AW_H3_NUM_CPUS), + qdev_get_gpio_in(cpudev, ARM_CPU_VFIQ)); + + /* GIC maintenance signal */ + sysbus_connect_irq(sysbusdev, i + (4 * AW_H3_NUM_CPUS), + qdev_get_gpio_in(DEVICE(&s->gic), + ppibase + AW_H3_GIC_PPI_MAINT)); + } + + for (i = 0; i < AW_H3_GIC_NUM_SPI; i++) { + s->irq[i] = qdev_get_gpio_in(DEVICE(&s->gic), i); + } + + /* Timer */ + object_property_set_bool(OBJECT(&s->timer), true, "realized", &err); + if (err != NULL) { + error_propagate(errp, err); + return; + } + sysbusdev = SYS_BUS_DEVICE(&s->timer); + sysbus_mmio_map(sysbusdev, 0, AW_H3_PIT_REG_BASE); + sysbus_connect_irq(sysbusdev, 0, s->irq[AW_H3_GIC_SPI_TIMER0]); + sysbus_connect_irq(sysbusdev, 1, s->irq[AW_H3_GIC_SPI_TIMER1]); + + /* SRAM */ + memory_region_init_ram(&s->sram_a1, OBJECT(dev), "sram A1", + AW_H3_SRAM_A1_SIZE, &error_fatal); + memory_region_init_ram(&s->sram_a2, OBJECT(dev), "sram A2", + AW_H3_SRAM_A2_SIZE, &error_fatal); + memory_region_init_ram(&s->sram_c, OBJECT(dev), "sram C", + AW_H3_SRAM_C_SIZE, &error_fatal); + memory_region_add_subregion(get_system_memory(), AW_H3_SRAM_A1_BASE, + &s->sram_a1); + memory_region_add_subregion(get_system_memory(), AW_H3_SRAM_A2_BASE, + &s->sram_a2); + memory_region_add_subregion(get_system_memory(), AW_H3_SRAM_C_BASE, + &s->sram_c); + + /* UART */ + if (serial_hd(0)) { + serial_mm_init(get_system_memory(), AW_H3_UART0_REG_BASE, 2, + s->irq[AW_H3_GIC_SPI_UART0], 115200, serial_hd(0), + DEVICE_NATIVE_ENDIAN); + } + + /* Unimplemented devices */ + create_unimplemented_device("display-engine", AW_H3_DE_BASE, AW_H3_DE_SIZE); + create_unimplemented_device("dma", AW_H3_DMA_BASE, AW_H3_DMA_SIZE); + create_unimplemented_device("lcd0", AW_H3_LCD0_BASE, AW_H3_LCD0_SIZE); + create_unimplemented_device("lcd1", AW_H3_LCD1_BASE, AW_H3_LCD1_SIZE); + create_unimplemented_device("gpu", AW_H3_GPU_BASE, AW_H3_GPU_SIZE); + create_unimplemented_device("hdmi", AW_H3_HDMI_BASE, AW_H3_HDMI_SIZE); + create_unimplemented_device("rtc", AW_H3_RTC_BASE, AW_H3_RTC_SIZE); + create_unimplemented_device("audio-codec", AW_H3_AC_BASE, AW_H3_AC_SIZE); +} + +static void aw_h3_class_init(ObjectClass *oc, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(oc); + + dc->realize = aw_h3_realize; + /* Reason: uses serial_hds and nd_table */ + dc->user_creatable = false; +} + +static const TypeInfo aw_h3_type_info = { + .name = TYPE_AW_H3, + .parent = TYPE_DEVICE, + .instance_size = sizeof(AwH3State), + .instance_init = aw_h3_init, + .class_init = aw_h3_class_init, +}; + +static void aw_h3_register_types(void) +{ + type_register_static(&aw_h3_type_info); +} + +type_init(aw_h3_register_types) diff --git a/include/hw/arm/allwinner-h3.h b/include/hw/arm/allwinner-h3.h new file mode 100644 index 0000000000..af368c2254 --- /dev/null +++ b/include/hw/arm/allwinner-h3.h @@ -0,0 +1,118 @@ +/* + * Allwinner H3 System on Chip emulation + * + * Copyright (C) 2019 Niek Linnenbank + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#ifndef HW_ARM_ALLWINNER_H3_H +#define HW_ARM_ALLWINNER_H3_H + +#include "qemu/error-report.h" +#include "qemu/units.h" +#include "hw/char/serial.h" +#include "hw/arm/boot.h" +#include "hw/timer/allwinner-a10-pit.h" +#include "hw/intc/arm_gic.h" +#include "target/arm/cpu.h" + +#define AW_H3_SRAM_A1_BASE (0x00000000) +#define AW_H3_SRAM_A2_BASE (0x00044000) +#define AW_H3_SRAM_C_BASE (0x00010000) +#define AW_H3_DE_BASE (0x01000000) +#define AW_H3_SYSCON_BASE (0x01c00000) +#define AW_H3_DMA_BASE (0x01c02000) +#define AW_H3_LCD0_BASE (0x01c0c000) +#define AW_H3_LCD1_BASE (0x01c0d000) +#define AW_H3_SID_BASE (0x01c14000) +#define AW_H3_CCU_BASE (0x01c20000) +#define AW_H3_PIC_REG_BASE (0x01c20400) +#define AW_H3_PIT_REG_BASE (0x01c20c00) +#define AW_H3_AC_BASE (0x01c22c00) +#define AW_H3_UART0_REG_BASE (0x01c28000) +#define AW_H3_EMAC_BASE (0x01c30000) +#define AW_H3_MMC0_BASE (0x01c0f000) +#define AW_H3_EHCI0_BASE (0x01c1a000) +#define AW_H3_OHCI0_BASE (0x01c1a400) +#define AW_H3_EHCI1_BASE (0x01c1b000) +#define AW_H3_OHCI1_BASE (0x01c1b400) +#define AW_H3_EHCI2_BASE (0x01c1c000) +#define AW_H3_OHCI2_BASE (0x01c1c400) +#define AW_H3_EHCI3_BASE (0x01c1d000) +#define AW_H3_OHCI3_BASE (0x01c1d400) +#define AW_H3_GPU_BASE (0x01c40000) +#define AW_H3_GIC_DIST_BASE (0x01c81000) +#define AW_H3_GIC_CPU_BASE (0x01c82000) +#define AW_H3_GIC_HYP_BASE (0x01c84000) +#define AW_H3_GIC_VCPU_BASE (0x01c86000) +#define AW_H3_HDMI_BASE (0x01ee0000) +#define AW_H3_RTC_BASE (0x01f00000) +#define AW_H3_CPUCFG_BASE (0x01f01c00) +#define AW_H3_SDRAM_BASE (0x40000000) + +#define AW_H3_SRAM_A1_SIZE (64 * KiB) +#define AW_H3_SRAM_A2_SIZE (32 * KiB) +#define AW_H3_SRAM_C_SIZE (44 * KiB) +#define AW_H3_DE_SIZE (4 * MiB) +#define AW_H3_DMA_SIZE (4 * KiB) +#define AW_H3_LCD0_SIZE (4 * KiB) +#define AW_H3_LCD1_SIZE (4 * KiB) +#define AW_H3_GPU_SIZE (64 * KiB) +#define AW_H3_HDMI_SIZE (128 * KiB) +#define AW_H3_RTC_SIZE (1 * KiB) +#define AW_H3_AC_SIZE (2 * KiB) + +#define AW_H3_GIC_PPI_MAINT (9) +#define AW_H3_GIC_PPI_ARM_HYPTIMER (10) +#define AW_H3_GIC_PPI_ARM_VIRTTIMER (11) +#define AW_H3_GIC_PPI_ARM_SECTIMER (13) +#define AW_H3_GIC_PPI_ARM_PHYSTIMER (14) + +#define AW_H3_GIC_SPI_UART0 (0) +#define AW_H3_GIC_SPI_TIMER0 (18) +#define AW_H3_GIC_SPI_TIMER1 (19) +#define AW_H3_GIC_SPI_MMC0 (60) +#define AW_H3_GIC_SPI_MMC1 (61) +#define AW_H3_GIC_SPI_MMC2 (62) +#define AW_H3_GIC_SPI_EHCI0 (72) +#define AW_H3_GIC_SPI_OHCI0 (73) +#define AW_H3_GIC_SPI_EHCI1 (74) +#define AW_H3_GIC_SPI_OHCI1 (75) +#define AW_H3_GIC_SPI_EHCI2 (76) +#define AW_H3_GIC_SPI_OHCI2 (77) +#define AW_H3_GIC_SPI_EHCI3 (78) +#define AW_H3_GIC_SPI_OHCI3 (79) +#define AW_H3_GIC_SPI_EMAC (82) + +#define AW_H3_GIC_NUM_SPI (128) +#define AW_H3_NUM_CPUS (4) + +#define TYPE_AW_H3 "allwinner-h3" +#define AW_H3(obj) OBJECT_CHECK(AwH3State, (obj), TYPE_AW_H3) + +typedef struct AwH3State { + /*< private >*/ + DeviceState parent_obj; + /*< public >*/ + + qemu_irq irq[AW_H3_GIC_NUM_SPI]; + AwA10PITState timer; + GICState gic; + MemoryRegion sram_a1; + MemoryRegion sram_a2; + MemoryRegion sram_c; +} AwH3State; + +#endif -- 2.17.1 From MAILER-DAEMON Mon Dec 02 16:38:07 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1ibtOR-00044c-O4 for mharc-qemu-arm@gnu.org; Mon, 02 Dec 2019 16:38:07 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:38271) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ibsxg-0002hD-ON for qemu-arm@nongnu.org; Mon, 02 Dec 2019 16:10:31 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ibsxa-0000kK-IU for qemu-arm@nongnu.org; Mon, 02 Dec 2019 16:10:26 -0500 Received: from mail-wm1-x341.google.com ([2a00:1450:4864:20::341]:53089) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ibsxK-0000Ze-T0; Mon, 02 Dec 2019 16:10:08 -0500 Received: by mail-wm1-x341.google.com with SMTP id p9so832211wmc.2; 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Mon, 02 Dec 2019 13:10:02 -0800 (PST) Received: from pavilion.home ([2a02:a456:6be8:1:8edc:d4ff:fe8b:18b7]) by smtp.gmail.com with ESMTPSA id f1sm770859wrp.93.2019.12.02.13.10.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 02 Dec 2019 13:10:02 -0800 (PST) From: Niek Linnenbank To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, peter.maydell@linaro.org, b.galvani@gmail.com, Niek Linnenbank Subject: [PATCH 07/10] arm: allwinner-h3: add CPU Configuration module Date: Mon, 2 Dec 2019 22:09:44 +0100 Message-Id: <20191202210947.3603-8-nieklinnenbank@gmail.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20191202210947.3603-1-nieklinnenbank@gmail.com> References: <20191202210947.3603-1-nieklinnenbank@gmail.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::341 X-Mailman-Approved-At: Mon, 02 Dec 2019 16:38:01 -0500 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 02 Dec 2019 21:10:32 -0000 The Allwinner H3 System on Chip design contains four ARM Cortex A7 processors that can be configured and reset using the CPU Configuration module interface. This commit adds support for the CPU configuration interface which emulates the following features: * CPU reset * Shared 64-bit timer Signed-off-by: Niek Linnenbank --- hw/arm/allwinner-h3.c | 11 + hw/misc/Makefile.objs | 1 + hw/misc/allwinner-h3-cpucfg.c | 280 ++++++++++++++++++++++++++ include/hw/arm/allwinner-h3.h | 2 + include/hw/misc/allwinner-h3-cpucfg.h | 44 ++++ 5 files changed, 338 insertions(+) create mode 100644 hw/misc/allwinner-h3-cpucfg.c create mode 100644 include/hw/misc/allwinner-h3-cpucfg.h diff --git a/hw/arm/allwinner-h3.c b/hw/arm/allwinner-h3.c index ebd8fde412..44aba1de6a 100644 --- a/hw/arm/allwinner-h3.c +++ b/hw/arm/allwinner-h3.c @@ -44,6 +44,9 @@ static void aw_h3_init(Object *obj) sysbus_init_child_obj(obj, "syscon", &s->syscon, sizeof(s->syscon), TYPE_AW_H3_SYSCON); + + sysbus_init_child_obj(obj, "cpucfg", &s->cpucfg, sizeof(s->cpucfg), + TYPE_AW_H3_CPUCFG); } static void aw_h3_realize(DeviceState *dev, Error **errp) @@ -195,6 +198,14 @@ static void aw_h3_realize(DeviceState *dev, Error **errp) } sysbus_mmio_map(SYS_BUS_DEVICE(&s->syscon), 0, AW_H3_SYSCON_BASE); + /* CPU Configuration */ + object_property_set_bool(OBJECT(&s->cpucfg), true, "realized", &err); + if (err) { + error_propagate(errp, err); + return; + } + sysbus_mmio_map(SYS_BUS_DEVICE(&s->cpucfg), 0, AW_H3_CPUCFG_BASE); + /* Universal Serial Bus */ sysbus_create_simple(TYPE_AW_H3_EHCI, AW_H3_EHCI0_BASE, s->irq[AW_H3_GIC_SPI_EHCI0]); diff --git a/hw/misc/Makefile.objs b/hw/misc/Makefile.objs index b234aefba5..c4ca2ed689 100644 --- a/hw/misc/Makefile.objs +++ b/hw/misc/Makefile.objs @@ -29,6 +29,7 @@ common-obj-$(CONFIG_MACIO) += macio/ common-obj-$(CONFIG_IVSHMEM_DEVICE) += ivshmem.o common-obj-$(CONFIG_ALLWINNER_H3) += allwinner-h3-clk.o +obj-$(CONFIG_ALLWINNER_H3) += allwinner-h3-cpucfg.o common-obj-$(CONFIG_ALLWINNER_H3) += allwinner-h3-syscon.o common-obj-$(CONFIG_REALVIEW) += arm_sysctl.o common-obj-$(CONFIG_NSERIES) += cbus.o diff --git a/hw/misc/allwinner-h3-cpucfg.c b/hw/misc/allwinner-h3-cpucfg.c new file mode 100644 index 0000000000..b47feebd73 --- /dev/null +++ b/hw/misc/allwinner-h3-cpucfg.c @@ -0,0 +1,280 @@ +/* + * Allwinner H3 CPU Configuration Module emulation + * + * Copyright (C) 2019 Niek Linnenbank + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#include "qemu/osdep.h" +#include "hw/sysbus.h" +#include "migration/vmstate.h" +#include "qemu/log.h" +#include "qemu/module.h" +#include "qemu/error-report.h" +#include "qemu/timer.h" +#include "hw/core/cpu.h" +#include "arm-powerctl.h" +#include "hw/misc/allwinner-h3-cpucfg.h" +#include "trace.h" + +/* CPUCFG register offsets */ +#define REG_CPUS_RST_CTRL (0x0000) /* CPUs Reset Control */ +#define REG_CPU0_RST_CTRL (0x0040) /* CPU#0 Reset Control */ +#define REG_CPU0_CTRL (0x0044) /* CPU#0 Control */ +#define REG_CPU0_STATUS (0x0048) /* CPU#0 Status */ +#define REG_CPU1_RST_CTRL (0x0080) /* CPU#1 Reset Control */ +#define REG_CPU1_CTRL (0x0084) /* CPU#1 Control */ +#define REG_CPU1_STATUS (0x0088) /* CPU#1 Status */ +#define REG_CPU2_RST_CTRL (0x00C0) /* CPU#2 Reset Control */ +#define REG_CPU2_CTRL (0x00C4) /* CPU#2 Control */ +#define REG_CPU2_STATUS (0x00C8) /* CPU#2 Status */ +#define REG_CPU3_RST_CTRL (0x0100) /* CPU#3 Reset Control */ +#define REG_CPU3_CTRL (0x0104) /* CPU#3 Control */ +#define REG_CPU3_STATUS (0x0108) /* CPU#3 Status */ +#define REG_CPU_SYS_RST (0x0140) /* CPU System Reset */ +#define REG_CLK_GATING (0x0144) /* CPU Clock Gating */ +#define REG_GEN_CTRL (0x0184) /* General Control */ +#define REG_SUPER_STANDBY (0x01A0) /* Super Standby Flag */ +#define REG_ENTRY_ADDR (0x01A4) /* Reset Entry Address */ +#define REG_DBG_EXTERN (0x01E4) /* Debug External */ +#define REG_CNT64_CTRL (0x0280) /* 64-bit Counter Control */ +#define REG_CNT64_LOW (0x0284) /* 64-bit Counter Low */ +#define REG_CNT64_HIGH (0x0288) /* 64-bit Counter High */ + +/* CPUCFG register flags */ +#define CPUX_RESET_RELEASED ((1 << 1) | (1 << 0)) +#define CPUX_STATUS_SMP (1 << 0) +#define CPU_SYS_RESET_RELEASED (1 << 0) +#define CLK_GATING_ENABLE ((1 << 8) | 0xF) + +/* CPUCFG register reset values */ +#define REG_CLK_GATING_RST (0x0000010F) +#define REG_GEN_CTRL_RST (0x00000020) +#define REG_SUPER_STANDBY_RST (0x0) +#define REG_CNT64_CTRL_RST (0x0) + +static void allwinner_h3_cpucfg_cpu_reset(AwH3CpuCfgState *s, uint8_t cpu_id) +{ + int ret; + + trace_allwinner_h3_cpucfg_cpu_reset(cpu_id, s->entry_addr); + + ret = arm_set_cpu_on(cpu_id, s->entry_addr, 0, 3, false); + if (ret != QEMU_ARM_POWERCTL_RET_SUCCESS) { + error_report("%s: failed to bring up CPU %d: err %d", + __func__, cpu_id, ret); + return; + } +} + +static uint64_t allwinner_h3_cpucfg_read(void *opaque, hwaddr offset, + unsigned size) +{ + const AwH3CpuCfgState *s = (AwH3CpuCfgState *)opaque; + uint64_t val = 0; + + switch (offset) { + case REG_CPUS_RST_CTRL: /* CPUs Reset Control */ + case REG_CPU_SYS_RST: /* CPU System Reset */ + val = CPU_SYS_RESET_RELEASED; + break; + case REG_CPU0_RST_CTRL: /* CPU#0 Reset Control */ + case REG_CPU1_RST_CTRL: /* CPU#1 Reset Control */ + case REG_CPU2_RST_CTRL: /* CPU#2 Reset Control */ + case REG_CPU3_RST_CTRL: /* CPU#3 Reset Control */ + val = CPUX_RESET_RELEASED; + break; + case REG_CPU0_CTRL: /* CPU#0 Control */ + case REG_CPU1_CTRL: /* CPU#1 Control */ + case REG_CPU2_CTRL: /* CPU#2 Control */ + case REG_CPU3_CTRL: /* CPU#3 Control */ + val = 0; + break; + case REG_CPU0_STATUS: /* CPU#0 Status */ + case REG_CPU1_STATUS: /* CPU#1 Status */ + case REG_CPU2_STATUS: /* CPU#2 Status */ + case REG_CPU3_STATUS: /* CPU#3 Status */ + val = CPUX_STATUS_SMP; + break; + case REG_CLK_GATING: /* CPU Clock Gating */ + val = CLK_GATING_ENABLE; + break; + case REG_GEN_CTRL: /* General Control */ + val = s->gen_ctrl; + break; + case REG_SUPER_STANDBY: /* Super Standby Flag */ + val = s->super_standby; + break; + case REG_ENTRY_ADDR: /* Reset Entry Address */ + val = s->entry_addr; + break; + case REG_DBG_EXTERN: /* Debug External */ + break; + case REG_CNT64_CTRL: /* 64-bit Counter Control */ + val = s->counter_ctrl; + break; + case REG_CNT64_LOW: /* 64-bit Counter Low */ + val = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) & 0xffffffff; + break; + case REG_CNT64_HIGH: /* 64-bit Counter High */ + val = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) >> 32; + break; + default: + qemu_log_mask(LOG_GUEST_ERROR, "%s: bad read offset 0x%04x\n", + __func__, (uint32_t)offset); + return 0; + } + + trace_allwinner_h3_cpucfg_read(offset, val, size); + + return val; +} + +static void allwinner_h3_cpucfg_write(void *opaque, hwaddr offset, + uint64_t val, unsigned size) +{ + AwH3CpuCfgState *s = (AwH3CpuCfgState *)opaque; + + trace_allwinner_h3_cpucfg_write(offset, val, size); + + switch (offset) { + case REG_CPUS_RST_CTRL: /* CPUs Reset Control */ + case REG_CPU_SYS_RST: /* CPU System Reset */ + break; + case REG_CPU0_RST_CTRL: /* CPU#0 Reset Control */ + if (val) { + allwinner_h3_cpucfg_cpu_reset(s, 0); + } + break; + case REG_CPU1_RST_CTRL: /* CPU#1 Reset Control */ + if (val) { + allwinner_h3_cpucfg_cpu_reset(s, 1); + } + break; + case REG_CPU2_RST_CTRL: /* CPU#2 Reset Control */ + if (val) { + allwinner_h3_cpucfg_cpu_reset(s, 2); + } + break; + case REG_CPU3_RST_CTRL: /* CPU#3 Reset Control */ + if (val) { + allwinner_h3_cpucfg_cpu_reset(s, 3); + } + break; + case REG_CPU0_CTRL: /* CPU#0 Control */ + case REG_CPU1_CTRL: /* CPU#1 Control */ + case REG_CPU2_CTRL: /* CPU#2 Control */ + case REG_CPU3_CTRL: /* CPU#3 Control */ + case REG_CPU0_STATUS: /* CPU#0 Status */ + case REG_CPU1_STATUS: /* CPU#1 Status */ + case REG_CPU2_STATUS: /* CPU#2 Status */ + case REG_CPU3_STATUS: /* CPU#3 Status */ + case REG_CLK_GATING: /* CPU Clock Gating */ + case REG_GEN_CTRL: /* General Control */ + s->gen_ctrl = val; + break; + case REG_SUPER_STANDBY: /* Super Standby Flag */ + s->super_standby = val; + break; + case REG_ENTRY_ADDR: /* Reset Entry Address */ + s->entry_addr = val; + break; + case REG_DBG_EXTERN: /* Debug External */ + break; + case REG_CNT64_CTRL: /* 64-bit Counter Control */ + s->counter_ctrl = val; + break; + case REG_CNT64_LOW: /* 64-bit Counter Low */ + case REG_CNT64_HIGH: /* 64-bit Counter High */ + break; + default: + qemu_log_mask(LOG_GUEST_ERROR, "%s: bad write offset 0x%04x\n", + __func__, (uint32_t)offset); + return; + } +} + +static const MemoryRegionOps allwinner_h3_cpucfg_ops = { + .read = allwinner_h3_cpucfg_read, + .write = allwinner_h3_cpucfg_write, + .endianness = DEVICE_NATIVE_ENDIAN, + .valid = { + .min_access_size = 4, + .max_access_size = 4, + .unaligned = false + } +}; + +static void allwinner_h3_cpucfg_reset(DeviceState *dev) +{ + AwH3CpuCfgState *s = AW_H3_CPUCFG(dev); + + /* Set default values for registers */ + s->gen_ctrl = REG_GEN_CTRL_RST; + s->super_standby = REG_SUPER_STANDBY_RST; + s->entry_addr = 0; + s->counter_ctrl = REG_CNT64_CTRL_RST; +} + +static void allwinner_h3_cpucfg_realize(DeviceState *dev, Error **errp) +{ +} + +static void allwinner_h3_cpucfg_init(Object *obj) +{ + SysBusDevice *sbd = SYS_BUS_DEVICE(obj); + AwH3CpuCfgState *s = AW_H3_CPUCFG(obj); + + /* Memory mapping */ + memory_region_init_io(&s->iomem, OBJECT(s), &allwinner_h3_cpucfg_ops, s, + TYPE_AW_H3_CPUCFG, AW_H3_CPUCFG_REGS_MEM_SIZE); + sysbus_init_mmio(sbd, &s->iomem); +} + +static const VMStateDescription allwinner_h3_cpucfg_vmstate = { + .name = TYPE_AW_H3_CPUCFG, + .version_id = 1, + .minimum_version_id = 1, + .fields = (VMStateField[]) { + VMSTATE_UINT32(gen_ctrl, AwH3CpuCfgState), + VMSTATE_UINT32(super_standby, AwH3CpuCfgState), + VMSTATE_UINT32(counter_ctrl, AwH3CpuCfgState), + VMSTATE_END_OF_LIST() + } +}; + +static void allwinner_h3_cpucfg_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + + dc->reset = allwinner_h3_cpucfg_reset; + dc->realize = allwinner_h3_cpucfg_realize; + dc->vmsd = &allwinner_h3_cpucfg_vmstate; +} + +static const TypeInfo allwinner_h3_cpucfg_info = { + .name = TYPE_AW_H3_CPUCFG, + .parent = TYPE_SYS_BUS_DEVICE, + .instance_init = allwinner_h3_cpucfg_init, + .instance_size = sizeof(AwH3CpuCfgState), + .class_init = allwinner_h3_cpucfg_class_init, +}; + +static void allwinner_h3_cpucfg_register(void) +{ + type_register_static(&allwinner_h3_cpucfg_info); +} + +type_init(allwinner_h3_cpucfg_register) diff --git a/include/hw/arm/allwinner-h3.h b/include/hw/arm/allwinner-h3.h index 2bc526b77b..374061b550 100644 --- a/include/hw/arm/allwinner-h3.h +++ b/include/hw/arm/allwinner-h3.h @@ -27,6 +27,7 @@ #include "hw/timer/allwinner-a10-pit.h" #include "hw/intc/arm_gic.h" #include "hw/misc/allwinner-h3-clk.h" +#include "hw/misc/allwinner-h3-cpucfg.h" #include "hw/misc/allwinner-h3-syscon.h" #include "target/arm/cpu.h" @@ -112,6 +113,7 @@ typedef struct AwH3State { qemu_irq irq[AW_H3_GIC_NUM_SPI]; AwA10PITState timer; AwH3ClockState ccu; + AwH3CpuCfgState cpucfg; AwH3SysconState syscon; GICState gic; MemoryRegion sram_a1; diff --git a/include/hw/misc/allwinner-h3-cpucfg.h b/include/hw/misc/allwinner-h3-cpucfg.h new file mode 100644 index 0000000000..808aaa90f6 --- /dev/null +++ b/include/hw/misc/allwinner-h3-cpucfg.h @@ -0,0 +1,44 @@ +/* + * Allwinner H3 CPU Configuration Module emulation + * + * Copyright (C) 2019 Niek Linnenbank + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#ifndef HW_MISC_ALLWINNER_H3_CPUCFG_H +#define HW_MISC_ALLWINNER_H3_CPUCFG_H + +#include "hw/sysbus.h" + +#define AW_H3_CPUCFG_REGS_MEM_SIZE (1024) + +#define TYPE_AW_H3_CPUCFG "allwinner-h3-cpucfg" +#define AW_H3_CPUCFG(obj) OBJECT_CHECK(AwH3CpuCfgState, (obj), \ + TYPE_AW_H3_CPUCFG) + +typedef struct AwH3CpuCfgState { + /*< private >*/ + SysBusDevice parent_obj; + /*< public >*/ + + MemoryRegion iomem; + uint32_t gen_ctrl; + uint32_t super_standby; + uint32_t entry_addr; + uint32_t counter_ctrl; + +} AwH3CpuCfgState; + +#endif -- 2.17.1 From MAILER-DAEMON Mon Dec 02 16:38:08 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1ibtOR-000452-Uu for mharc-qemu-arm@gnu.org; Mon, 02 Dec 2019 16:38:07 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:38332) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ibsxj-0002kC-Rf for qemu-arm@nongnu.org; Mon, 02 Dec 2019 16:10:33 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ibsxh-0000nB-3E for qemu-arm@nongnu.org; Mon, 02 Dec 2019 16:10:31 -0500 Received: from mail-wm1-x343.google.com ([2a00:1450:4864:20::343]:38631) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ibsxM-0000Yv-M5; Mon, 02 Dec 2019 16:10:09 -0500 Received: by mail-wm1-x343.google.com with SMTP id p17so1104368wmi.3; Mon, 02 Dec 2019 13:10:01 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=KLiQATngYVxKEhubgojMgx0rCFF3IHtRu91h6RNCkKo=; b=Zzf9OofcZJUPgAFukp7W3plQeSrCvtZlB3w08FQWUlrvc1cOJJKd/V9lfWDnvp/uvB DU4nmVsjqPdvbdW30q4RQwg386IMMyvgbSpZqqCaeouPfeRmaZWQQHEaOxa2frHitFE5 may7cKBTmnAu38A6Xp2ckW/dpHBWoRxtfEKwoNpIuBn+4duzdvgeiIRjjiMvhMHnCCl1 5Uaf53f6a9iyXnzff8IwqUanYIcGePlR8FHTm8rtBlNdWcRyMJhDIHBea1PGTmw4NxKK JH6ANxMWIS9yltWaRz/v4lal6C2zIktWISXu9fTbmdBxnIjwWdNK0R66Du5IG0M6DgrR aKhw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=KLiQATngYVxKEhubgojMgx0rCFF3IHtRu91h6RNCkKo=; b=j093eMlVXD5wl+sgDiYn6qaf9VWAMIacJdNtuqHaqYflM/XRVlQkkgV3v4/zzhlOju nEnpZ/pVQalKea3X4vHixlmo5io5gO2hn1tWhwVtgat05RUAOWw1xzoCy1kvlN3CkkTp Oc7nPnmo+hoOI6ywtzZBy5PtAhssuzuNUyECzqZLSo+Pfi8OzCre9ccBt1T297dLcQpy P20fSJ3C1nXpxO3ewDEOyU1yIaCaWWQnuK3+sIZH41O81Qzdwo538XWD6FDg0uKcPO9r 7UUBD4E8dlnwwScjx5dEkiKMPrWs8UToglzr1jsguGf3f/oLTcmmB6RnhtbUOrmzvJm4 Vxbg== X-Gm-Message-State: APjAAAUgnkGsGTodg9eIAVkjx6UolJT6P00MlVxFwD95X5Sd+Mrq5qvR 0xzHzugb39cHppMYIGhuKB4Ke0Rs X-Google-Smtp-Source: APXvYqzsCs/54zu5WwvX5AIRGqqFYZ/xh6JgPfmACi7UrEIyvtFQ2f81q5C4DBUfolCRWIjdzP6UGg== X-Received: by 2002:a1c:f610:: with SMTP id w16mr12606830wmc.34.1575321000343; Mon, 02 Dec 2019 13:10:00 -0800 (PST) Received: from pavilion.home ([2a02:a456:6be8:1:8edc:d4ff:fe8b:18b7]) by smtp.gmail.com with ESMTPSA id f1sm770859wrp.93.2019.12.02.13.09.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 02 Dec 2019 13:09:59 -0800 (PST) From: Niek Linnenbank To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, peter.maydell@linaro.org, b.galvani@gmail.com, Niek Linnenbank Subject: [PATCH 04/10] arm: allwinner-h3: add USB host controller Date: Mon, 2 Dec 2019 22:09:41 +0100 Message-Id: <20191202210947.3603-5-nieklinnenbank@gmail.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20191202210947.3603-1-nieklinnenbank@gmail.com> References: <20191202210947.3603-1-nieklinnenbank@gmail.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::343 X-Mailman-Approved-At: Mon, 02 Dec 2019 16:38:01 -0500 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 02 Dec 2019 21:10:33 -0000 The Allwinner H3 System on Chip contains multiple USB 2.0 bus connections which provide software access using the Enhanced Host Controller Interface (EHCI) and Open Host Controller Interface (OHCI) interfaces. This commit adds support for both interfaces in the Allwinner H3 System on Chip. Signed-off-by: Niek Linnenbank --- hw/arm/allwinner-h3.c | 20 ++++++++++++++++++++ hw/usb/hcd-ehci-sysbus.c | 17 +++++++++++++++++ hw/usb/hcd-ehci.h | 1 + 3 files changed, 38 insertions(+) diff --git a/hw/arm/allwinner-h3.c b/hw/arm/allwinner-h3.c index 5566e979ec..afeb49c0ac 100644 --- a/hw/arm/allwinner-h3.c +++ b/hw/arm/allwinner-h3.c @@ -26,6 +26,7 @@ #include "hw/sysbus.h" #include "hw/arm/allwinner-h3.h" #include "hw/misc/unimp.h" +#include "hw/usb/hcd-ehci.h" #include "sysemu/sysemu.h" static void aw_h3_init(Object *obj) @@ -183,6 +184,25 @@ static void aw_h3_realize(DeviceState *dev, Error **errp) } sysbus_mmio_map(SYS_BUS_DEVICE(&s->ccu), 0, AW_H3_CCU_BASE); + /* Universal Serial Bus */ + sysbus_create_simple(TYPE_AW_H3_EHCI, AW_H3_EHCI0_BASE, + s->irq[AW_H3_GIC_SPI_EHCI0]); + sysbus_create_simple(TYPE_AW_H3_EHCI, AW_H3_EHCI1_BASE, + s->irq[AW_H3_GIC_SPI_EHCI1]); + sysbus_create_simple(TYPE_AW_H3_EHCI, AW_H3_EHCI2_BASE, + s->irq[AW_H3_GIC_SPI_EHCI2]); + sysbus_create_simple(TYPE_AW_H3_EHCI, AW_H3_EHCI3_BASE, + s->irq[AW_H3_GIC_SPI_EHCI3]); + + sysbus_create_simple("sysbus-ohci", AW_H3_OHCI0_BASE, + s->irq[AW_H3_GIC_SPI_OHCI0]); + sysbus_create_simple("sysbus-ohci", AW_H3_OHCI1_BASE, + s->irq[AW_H3_GIC_SPI_OHCI1]); + sysbus_create_simple("sysbus-ohci", AW_H3_OHCI2_BASE, + s->irq[AW_H3_GIC_SPI_OHCI2]); + sysbus_create_simple("sysbus-ohci", AW_H3_OHCI3_BASE, + s->irq[AW_H3_GIC_SPI_OHCI3]); + /* UART */ if (serial_hd(0)) { serial_mm_init(get_system_memory(), AW_H3_UART0_REG_BASE, 2, diff --git a/hw/usb/hcd-ehci-sysbus.c b/hw/usb/hcd-ehci-sysbus.c index 020211fd10..174c3446ef 100644 --- a/hw/usb/hcd-ehci-sysbus.c +++ b/hw/usb/hcd-ehci-sysbus.c @@ -145,6 +145,22 @@ static const TypeInfo ehci_exynos4210_type_info = { .class_init = ehci_exynos4210_class_init, }; +static void ehci_aw_h3_class_init(ObjectClass *oc, void *data) +{ + SysBusEHCIClass *sec = SYS_BUS_EHCI_CLASS(oc); + DeviceClass *dc = DEVICE_CLASS(oc); + + sec->capsbase = 0x0; + sec->opregbase = 0x10; + set_bit(DEVICE_CATEGORY_USB, dc->categories); +} + +static const TypeInfo ehci_aw_h3_type_info = { + .name = TYPE_AW_H3_EHCI, + .parent = TYPE_SYS_BUS_EHCI, + .class_init = ehci_aw_h3_class_init, +}; + static void ehci_tegra2_class_init(ObjectClass *oc, void *data) { SysBusEHCIClass *sec = SYS_BUS_EHCI_CLASS(oc); @@ -267,6 +283,7 @@ static void ehci_sysbus_register_types(void) type_register_static(&ehci_platform_type_info); type_register_static(&ehci_xlnx_type_info); type_register_static(&ehci_exynos4210_type_info); + type_register_static(&ehci_aw_h3_type_info); type_register_static(&ehci_tegra2_type_info); type_register_static(&ehci_ppc4xx_type_info); type_register_static(&ehci_fusbh200_type_info); diff --git a/hw/usb/hcd-ehci.h b/hw/usb/hcd-ehci.h index 0298238f0b..edb59311c4 100644 --- a/hw/usb/hcd-ehci.h +++ b/hw/usb/hcd-ehci.h @@ -342,6 +342,7 @@ typedef struct EHCIPCIState { #define TYPE_SYS_BUS_EHCI "sysbus-ehci-usb" #define TYPE_PLATFORM_EHCI "platform-ehci-usb" #define TYPE_EXYNOS4210_EHCI "exynos4210-ehci-usb" +#define TYPE_AW_H3_EHCI "aw-h3-ehci-usb" #define TYPE_TEGRA2_EHCI "tegra2-ehci-usb" #define TYPE_PPC4xx_EHCI "ppc4xx-ehci-usb" #define TYPE_FUSBH200_EHCI "fusbh200-ehci-usb" -- 2.17.1 From MAILER-DAEMON Mon Dec 02 18:47:11 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1ibvPL-0003SJ-JV for mharc-qemu-arm@gnu.org; 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Mon, 2 Dec 2019 18:46:57 -0500 (EST) X-Mailer: MessagingEngine.com Webmail Interface User-Agent: Cyrus-JMAP/3.1.7-578-g826f590-fmstable-20191119v1 Mime-Version: 1.0 Message-Id: In-Reply-To: References: <20191128054527.25450-1-andrew@aj.id.au> <20191128054527.25450-3-andrew@aj.id.au> Date: Tue, 03 Dec 2019 10:18:32 +1030 From: "Andrew Jeffery" To: "Peter Maydell" Cc: qemu-arm , =?UTF-8?Q?C=C3=A9dric_Le_Goater?= , "Joel Stanley" , "QEMU Developers" Subject: Re: [PATCH 2/4] target/arm: Abstract the generic timer frequency Content-Type: text/plain X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 64.147.123.21 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 02 Dec 2019 23:47:10 -0000 On Tue, 3 Dec 2019, at 04:42, Peter Maydell wrote: > On Thu, 28 Nov 2019 at 05:44, Andrew Jeffery wrote: > > > > Prepare for SoCs such as the ASPEED AST2600 whose firmware configures > > CNTFRQ to values significantly larger than the static 62.5MHz value > > currently derived from GTIMER_SCALE. As the OS potentially derives its > > timer periods from the CNTFRQ value the lack of support for running > > QEMUTimers at the appropriate rate leads to sticky behaviour in the > > guest. > > > > Substitute the GTIMER_SCALE constant with use of a helper to derive the > > period from gt_cntfrq stored in struct ARMCPU. Initially set gt_cntfrq > > to the frequency associated with GTIMER_SCALE so current behaviour is > > maintained. > > > > Signed-off-by: Andrew Jeffery > > > +static inline unsigned int gt_cntfrq_period_ns(ARMCPU *cpu) > > +{ > > + /* XXX: Could include qemu/timer.h to get NANOSECONDS_PER_SECOND? */ > > + const unsigned int ns_per_s = 1000 * 1000 * 1000; > > + return ns_per_s > cpu->gt_cntfrq ? ns_per_s / cpu->gt_cntfrq : 1; > > +} > > This function is named gt_cntfrq_period_ns()... > > > static uint64_t gt_virt_cnt_read(CPUARMState *env, const ARMCPRegInfo *ri) > > { > > + ARMCPU *cpu = env_archcpu(env); > > + > > /* Currently we have no support for QEMUTimer in linux-user so we > > * can't call gt_get_countervalue(env), instead we directly > > * call the lower level functions. > > */ > > - return cpu_get_clock() / GTIMER_SCALE; > > + return cpu_get_clock() / gt_cntfrq_period(cpu); > > } > > ...but here we call gt_cntfrq_period(), which doesn't exist, > and indeed at least one of the patchew build systems reported > it as a compile failure. > Ah yep, I failed to test user mode after renaming the function and missed this. I haven't seen an alert from patchew though, I wonder where that got to? Andrew From MAILER-DAEMON Mon Dec 02 19:22:18 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1ibvxJ-0002uI-UU for mharc-qemu-arm@gnu.org; Mon, 02 Dec 2019 19:22:17 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:51036) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ibvxE-0002rI-LA for qemu-arm@nongnu.org; Mon, 02 Dec 2019 19:22:15 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ibvxA-0001iz-LD for qemu-arm@nongnu.org; Mon, 02 Dec 2019 19:22:10 -0500 Received: from ozlabs.org ([2401:3900:2:1::2]:38763) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1ibvx4-0001b3-JL; Mon, 02 Dec 2019 19:22:05 -0500 Received: by ozlabs.org (Postfix, from userid 1007) id 47RjN22lNWz9sPL; Tue, 3 Dec 2019 11:21:54 +1100 (AEDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gibson.dropbear.id.au; s=201602; t=1575332514; bh=UtK4MZTFX5Ll0DXboYjXPnFFAe2D7Fp1y5zVX5+Q3ZY=; h=Date:From:To:Cc:Subject:References:In-Reply-To:From; b=YVqPCs+L2aR5OdrZPNE1791xeM+P8UTLF2nm6pneJP2rtg06ktc2HWlx6Sw+NS5Jh QxcZnlr9OcZj7PqR6TarySOK4U8byKmNkvs7ZfXtd6X23AbY5p8f9w8XsdAj/NztrK OcjB1Nxe+TmTvSxBM/XL3atLc+Tb9DQEJLMXsjTE= Date: Tue, 3 Dec 2019 11:21:43 +1100 From: David Gibson To: Peter Maydell Cc: Richard Henderson , qemu-arm , QEMU Developers , Igor Mitsyanko , Philippe =?iso-8859-1?Q?Mathieu-Daud=E9?= Subject: Re: [PATCHv3] exynos4210_gic: Suppress gcc9 format-truncation warnings Message-ID: <20191203002143.GD37909@umbus.fritz.box> References: <20191202060806.77968-1-david@gibson.dropbear.id.au> <8b490fbe-2b09-2a2c-16a8-6739ce6a847d@linaro.org> MIME-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha256; protocol="application/pgp-signature"; boundary="YToU2i3Vx8H2dn7O" Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.12.1 (2019-06-15) X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2401:3900:2:1::2 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 03 Dec 2019 00:22:15 -0000 --YToU2i3Vx8H2dn7O Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Content-Transfer-Encoding: quoted-printable On Mon, Dec 02, 2019 at 05:44:11PM +0000, Peter Maydell wrote: > On Mon, 2 Dec 2019 at 16:08, Richard Henderson > wrote: > > > > On 12/1/19 6:08 AM, David Gibson wrote: > > > > > > - for (i =3D 0; i < s->num_cpu; i++) { > > > + /* > > > + * This clues in gcc that our on-stack buffers do, in fact have > > > + * enough room for the cpu numbers. gcc 9.2.1 on 32-bit x86 > > > + * doesn't figure this out, otherwise and gives spurious warning= s. > > > + */ > > > + assert(n <=3D EXYNOS4210_NCPUS); > > > + for (i =3D 0; i < n; i++) { > > > + > > > /* Map CPU interface per SMP Core */ > > > > Watch out for the extra line added at the start of the block. Otherwis= e, > > > > Reviewed-by: Richard Henderson >=20 > I thought about putting this in rc4 but eventually decided > against it. Queued for 5.0 (with the stray extra blank line > removed). Great! --=20 David Gibson | I'll have my music baroque, and my code david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_ | _way_ _around_! http://www.ozlabs.org/~dgibson --YToU2i3Vx8H2dn7O Content-Type: application/pgp-signature; name="signature.asc" -----BEGIN PGP SIGNATURE----- iQIzBAEBCAAdFiEEdfRlhq5hpmzETofcbDjKyiDZs5IFAl3lqpUACgkQbDjKyiDZ s5KuEg//UFgKQhzaHfjvcBROlr7x4twHsRWOLWgBcDPDwdlpNTIjs1PBdgOtMs7/ VsBl2BmLDsOFqrZ5ZRdXCnEkqqTnwDiDJOSDBd/RDm+TE+HSFXOZ8sgi1N8BPeee Pwnu/bCDt4OkfkZc6iIE4QWE0zbz7GwLZG7B+9S43Ymoc0lnEukXHRab35sasw4W vUU9CFosmI8X8jS2eH39HLr8eBgjktmq8wnmK9kY8FobcUWuX/vWtk19ivpMjuER KcsOUywiDTCk64XcForkJwRym0s3R+8DivVYk2r17YDq1bA5Bk9mluRsJz/BEJ60 aPu7CfO7vBfKNgNyhfX0y8dps83ghK3sdKJKwDlPvg61l3/b5uxGHWBV5n3tXpLP oEmgSpMJUCO395ONvCD6l9gjZARUHiRodk4uoQD9R5y1ripqFqA3zp0F9fixfHgX 3dp8u80HnZz992SZOjBVTy5O4lL5Ne2enDNMBowAkEFS2hJs/qYO22wOag4C0lrI HR82DNuy38oRvbTsQ8O4VDPO3G1v24QB7Gcz1EqsJNSeJ4MrkoxfaPxwi+uvYsrW 72ULRh2h2yDfyt1Lea8V4Gd1oGVPrXUQ8KqgYl0NSMePgmKztqvuTgyCk5Kvnopy GpvzBpHrOGxas/+G8bnpjhnYvaBEVYMgeT2SUaAe63zBnOhkpHM= =jc2+ -----END PGP SIGNATURE----- --YToU2i3Vx8H2dn7O-- From MAILER-DAEMON Mon Dec 02 21:10:40 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1ibxeC-0007tI-N0 for mharc-qemu-arm@gnu.org; Mon, 02 Dec 2019 21:10:40 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:53197) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ibxe9-0007sr-Oh for qemu-arm@nongnu.org; Mon, 02 Dec 2019 21:10:38 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ibxe3-0003mk-2a for qemu-arm@nongnu.org; Mon, 02 Dec 2019 21:10:33 -0500 Received: from szxga04-in.huawei.com ([45.249.212.190]:2206 helo=huawei.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1ibxe2-0003Mi-FD; Mon, 02 Dec 2019 21:10:30 -0500 Received: from DGGEMS404-HUB.china.huawei.com (unknown [172.30.72.60]) by Forcepoint Email with ESMTP id AE02B229EEBA8B584857; Tue, 3 Dec 2019 10:10:09 +0800 (CST) Received: from [127.0.0.1] (10.142.68.147) by DGGEMS404-HUB.china.huawei.com (10.3.19.204) with Microsoft SMTP Server id 14.3.439.0; Tue, 3 Dec 2019 10:10:03 +0800 Subject: Re: [RESEND PATCH v21 0/6] Add ARMv8 RAS virtualization support in QEMU To: Peter Maydell , Xiang Zheng CC: Paolo Bonzini , "Michael S. Tsirkin" , Igor Mammedov , Shannon Zhao , Laszlo Ersek , James Morse , Marcelo Tosatti , "Richard Henderson" , Eduardo Habkost , "Jonathan Cameron" , "xuwei (O)" , kvm-devel , QEMU Developers , qemu-arm , Linuxarm , References: <20191111014048.21296-1-zhengxiang9@huawei.com> From: gengdongjiu Message-ID: <2fc18991-ecc7-a59f-c0ec-a39786e2dbf9@huawei.com> Date: Tue, 3 Dec 2019 10:09:47 +0800 User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:52.0) Gecko/20100101 Thunderbird/52.3.0 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset="utf-8" Content-Language: en-US Content-Transfer-Encoding: 7bit X-Originating-IP: [10.142.68.147] X-CFilter-Loop: Reflected X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 45.249.212.190 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 03 Dec 2019 02:10:38 -0000 On 2019/12/3 2:27, Peter Maydell wrote: >> application within guest, host does not know which application encounters >> errors. >> >> For the ARMv8 SEA/SEI, KVM or host kernel delivers SIGBUS to notify userspace. >> After user space gets the notification, it will record the CPER into guest GHES >> buffer and inject an exception or IRQ into guest. >> >> In the current implementation, if the type of SIGBUS is BUS_MCEERR_AR, we will >> treat it as a synchronous exception, and notify guest with ARMv8 SEA >> notification type after recording CPER into guest. > Hi; I've given you reviewed-by tags on a couple of patches; other > people have given review comments on some of the other patches, > so I think you have enough to do a v22 addressing those. Thanks very much for the reviewed-by tags, we will upload v22. > > thanks > -- PMM > . > From MAILER-DAEMON Mon Dec 02 22:35:34 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1ibyyM-0003YN-B6 for mharc-qemu-arm@gnu.org; Mon, 02 Dec 2019 22:35:34 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:47512) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ibyyJ-0003Wx-Of for qemu-arm@nongnu.org; Mon, 02 Dec 2019 22:35:33 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ibyyI-0007Ow-B7 for qemu-arm@nongnu.org; Mon, 02 Dec 2019 22:35:31 -0500 Received: from szxga05-in.huawei.com ([45.249.212.191]:2271 helo=huawei.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1ibyyH-0007Hy-Q9; Mon, 02 Dec 2019 22:35:30 -0500 Received: from DGGEMS413-HUB.china.huawei.com (unknown [172.30.72.58]) by Forcepoint Email with ESMTP id 1D09FC0E0806ED26CA59; Tue, 3 Dec 2019 11:35:24 +0800 (CST) Received: from [127.0.0.1] (10.133.224.57) by DGGEMS413-HUB.china.huawei.com (10.3.19.213) with Microsoft SMTP Server id 14.3.439.0; Tue, 3 Dec 2019 11:35:14 +0800 Subject: Re: [RESEND PATCH v21 5/6] target-arm: kvm64: handle SIGBUS signal from kernel or KVM To: Beata Michalska , Igor Mammedov CC: , , , "Peter Maydell" , Laszlo Ersek , , gengdongjiu , , , , , , , , , , References: <20191111014048.21296-1-zhengxiang9@huawei.com> <20191111014048.21296-6-zhengxiang9@huawei.com> <22a3935a-a672-f8f1-e5be-6c0725f738c4@huawei.com> <20191127140223.58d1a35b@redhat.com> From: Xiang Zheng Message-ID: <4282defe-80e6-fdd9-ece0-3349c94f2611@huawei.com> Date: Tue, 3 Dec 2019 11:35:13 +0800 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:68.0) Gecko/20100101 Thunderbird/68.1.0 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset="utf-8" Content-Language: en-US Content-Transfer-Encoding: 7bit X-Originating-IP: [10.133.224.57] X-CFilter-Loop: Reflected X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 45.249.212.191 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 03 Dec 2019 03:35:33 -0000 On 2019/11/27 22:17, Beata Michalska wrote: > On Wed, 27 Nov 2019 at 13:03, Igor Mammedov wrote: >> >> On Wed, 27 Nov 2019 20:47:15 +0800 >> Xiang Zheng wrote: >> >>> Hi Beata, >>> >>> Thanks for you review! >>> >>> On 2019/11/22 23:47, Beata Michalska wrote: >>>> Hi, >>>> >>>> On Mon, 11 Nov 2019 at 01:48, Xiang Zheng wrote: >>>>> >>>>> From: Dongjiu Geng >>>>> >>>>> Add a SIGBUS signal handler. In this handler, it checks the SIGBUS type, >>>>> translates the host VA delivered by host to guest PA, then fills this PA >>>>> to guest APEI GHES memory, then notifies guest according to the SIGBUS >>>>> type. >>>>> >>>>> When guest accesses the poisoned memory, it will generate a Synchronous >>>>> External Abort(SEA). Then host kernel gets an APEI notification and calls >>>>> memory_failure() to unmapped the affected page in stage 2, finally >>>>> returns to guest. >>>>> >>>>> Guest continues to access the PG_hwpoison page, it will trap to KVM as >>>>> stage2 fault, then a SIGBUS_MCEERR_AR synchronous signal is delivered to >>>>> Qemu, Qemu records this error address into guest APEI GHES memory and >>>>> notifes guest using Synchronous-External-Abort(SEA). >>>>> >>>>> In order to inject a vSEA, we introduce the kvm_inject_arm_sea() function >>>>> in which we can setup the type of exception and the syndrome information. >>>>> When switching to guest, the target vcpu will jump to the synchronous >>>>> external abort vector table entry. >>>>> >>>>> The ESR_ELx.DFSC is set to synchronous external abort(0x10), and the >>>>> ESR_ELx.FnV is set to not valid(0x1), which will tell guest that FAR is >>>>> not valid and hold an UNKNOWN value. These values will be set to KVM >>>>> register structures through KVM_SET_ONE_REG IOCTL. >>>>> >>>>> Signed-off-by: Dongjiu Geng >>>>> Signed-off-by: Xiang Zheng >>>>> Reviewed-by: Michael S. Tsirkin >>>>> --- >> [...] >>>>> diff --git a/include/hw/acpi/acpi_ghes.h b/include/hw/acpi/acpi_ghes.h >>>>> index cb62ec9c7b..8e3c5b879e 100644 >>>>> --- a/include/hw/acpi/acpi_ghes.h >>>>> +++ b/include/hw/acpi/acpi_ghes.h >>>>> @@ -24,6 +24,9 @@ >>>>> >>>>> #include "hw/acpi/bios-linker-loader.h" >>>>> >>>>> +#define ACPI_GHES_CPER_OK 1 >>>>> +#define ACPI_GHES_CPER_FAIL 0 >>>>> + >>>> >>>> Is there really a need to introduce those ? >>>> >>> >>> Don't you think it's more clear than using "1" or "0"? :) >> >> or maybe just reuse default libc return convention: 0 - ok, -1 - fail >> and drop custom macros >> > > Totally agree. > OK, let's reuse default libc return convention. -- Thanks, Xiang From MAILER-DAEMON Mon Dec 02 22:35:34 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1ibyyM-0003Ys-L8 for mharc-qemu-arm@gnu.org; Mon, 02 Dec 2019 22:35:34 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:47460) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ibyyJ-0003Wk-Jh for qemu-arm@nongnu.org; Mon, 02 Dec 2019 22:35:33 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ibyyH-0007Nf-OL for qemu-arm@nongnu.org; Mon, 02 Dec 2019 22:35:31 -0500 Received: from szxga04-in.huawei.com ([45.249.212.190]:2207 helo=huawei.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1ibyyG-0007Fm-Ve; Mon, 02 Dec 2019 22:35:29 -0500 Received: from DGGEMS401-HUB.china.huawei.com (unknown [172.30.72.58]) by Forcepoint Email with ESMTP id 95E033A9891C360ACA0D; Tue, 3 Dec 2019 11:35:19 +0800 (CST) Received: from [127.0.0.1] (10.133.224.57) by DGGEMS401-HUB.china.huawei.com (10.3.19.201) with Microsoft SMTP Server id 14.3.439.0; Tue, 3 Dec 2019 11:35:09 +0800 Subject: Re: [RESEND PATCH v21 5/6] target-arm: kvm64: handle SIGBUS signal from kernel or KVM To: Beata Michalska CC: , , Igor Mammedov , , Peter Maydell , Laszlo Ersek , , gengdongjiu , , , , , , , , , , References: <20191111014048.21296-1-zhengxiang9@huawei.com> <20191111014048.21296-6-zhengxiang9@huawei.com> <22a3935a-a672-f8f1-e5be-6c0725f738c4@huawei.com> From: Xiang Zheng Message-ID: <9e22a655-5333-ba65-a00d-712b5b144ff4@huawei.com> Date: Tue, 3 Dec 2019 11:35:07 +0800 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:68.0) Gecko/20100101 Thunderbird/68.1.0 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset="utf-8" Content-Language: en-US Content-Transfer-Encoding: 7bit X-Originating-IP: [10.133.224.57] X-CFilter-Loop: Reflected X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 45.249.212.190 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 03 Dec 2019 03:35:33 -0000 On 2019/11/27 22:17, Beata Michalska wrote: > Hi > > On Wed, 27 Nov 2019 at 12:47, Xiang Zheng wrote: >> >> Hi Beata, >> >> Thanks for you review! >> > YAW > >> On 2019/11/22 23:47, Beata Michalska wrote: >>> Hi, >>> >>> On Mon, 11 Nov 2019 at 01:48, Xiang Zheng wrote: >>>> >>>> From: Dongjiu Geng >>>> >>>> Add a SIGBUS signal handler. In this handler, it checks the SIGBUS type, >>>> translates the host VA delivered by host to guest PA, then fills this PA >>>> to guest APEI GHES memory, then notifies guest according to the SIGBUS >>>> type. >>>> >>>> When guest accesses the poisoned memory, it will generate a Synchronous >>>> External Abort(SEA). Then host kernel gets an APEI notification and calls >>>> memory_failure() to unmapped the affected page in stage 2, finally >>>> returns to guest. >>>> >>>> Guest continues to access the PG_hwpoison page, it will trap to KVM as >>>> stage2 fault, then a SIGBUS_MCEERR_AR synchronous signal is delivered to >>>> Qemu, Qemu records this error address into guest APEI GHES memory and >>>> notifes guest using Synchronous-External-Abort(SEA). >>>> >>>> In order to inject a vSEA, we introduce the kvm_inject_arm_sea() function >>>> in which we can setup the type of exception and the syndrome information. >>>> When switching to guest, the target vcpu will jump to the synchronous >>>> external abort vector table entry. >>>> >>>> The ESR_ELx.DFSC is set to synchronous external abort(0x10), and the >>>> ESR_ELx.FnV is set to not valid(0x1), which will tell guest that FAR is >>>> not valid and hold an UNKNOWN value. These values will be set to KVM >>>> register structures through KVM_SET_ONE_REG IOCTL. >>>> >>>> Signed-off-by: Dongjiu Geng >>>> Signed-off-by: Xiang Zheng >>>> Reviewed-by: Michael S. Tsirkin >>>> --- >>>> hw/acpi/acpi_ghes.c | 297 ++++++++++++++++++++++++++++++++++++ >>>> include/hw/acpi/acpi_ghes.h | 4 + >>>> include/sysemu/kvm.h | 3 +- >>>> target/arm/cpu.h | 4 + >>>> target/arm/helper.c | 2 +- >>>> target/arm/internals.h | 5 +- >>>> target/arm/kvm64.c | 64 ++++++++ >>>> target/arm/tlb_helper.c | 2 +- >>>> target/i386/cpu.h | 2 + >>>> 9 files changed, 377 insertions(+), 6 deletions(-) >>>> >>>> diff --git a/hw/acpi/acpi_ghes.c b/hw/acpi/acpi_ghes.c >>>> index 42c00ff3d3..f5b54990c0 100644 >>>> --- a/hw/acpi/acpi_ghes.c >>>> +++ b/hw/acpi/acpi_ghes.c >>>> @@ -39,6 +39,34 @@ >>>> /* The max size in bytes for one error block */ >>>> #define ACPI_GHES_MAX_RAW_DATA_LENGTH 0x1000 >>>> >>>> +/* >>>> + * The total size of Generic Error Data Entry >>>> + * ACPI 6.1/6.2: 18.3.2.7.1 Generic Error Data, >>>> + * Table 18-343 Generic Error Data Entry >>>> + */ >>>> +#define ACPI_GHES_DATA_LENGTH 72 >>>> + >>>> +/* >>>> + * The memory section CPER size, >>>> + * UEFI 2.6: N.2.5 Memory Error Section >>>> + */ >>>> +#define ACPI_GHES_MEM_CPER_LENGTH 80 >>>> + >>>> +/* >>>> + * Masks for block_status flags >>>> + */ >>>> +#define ACPI_GEBS_UNCORRECTABLE 1 >>> >>> Why not listing all supported statuses ? Similar to error severity below ? >>> >> >> We now only use the first bit for uncorrectable error. The correctable errors >> are handled in host and would not be delivered to QEMU. >> >> I think it's unnecessary to list all the bit masks. > > I'm not sure we are using all the error severity types either, but fair enough. >> >>>> + >>>> +/* >>>> + * Values for error_severity field >>>> + */ >>>> +enum AcpiGenericErrorSeverity { >>>> + ACPI_CPER_SEV_RECOVERABLE, >>>> + ACPI_CPER_SEV_FATAL, >>>> + ACPI_CPER_SEV_CORRECTED, >>>> + ACPI_CPER_SEV_NONE, >>>> +}; >>>> + >>>> /* >>>> * Now only support ARMv8 SEA notification type error source >>>> */ >>>> @@ -49,6 +77,16 @@ >>>> */ >>>> #define ACPI_GHES_SOURCE_GENERIC_ERROR_V2 10 >>>> >>>> +#define UUID_BE(a, b, c, d0, d1, d2, d3, d4, d5, d6, d7) \ >>>> + {{{ ((a) >> 24) & 0xff, ((a) >> 16) & 0xff, ((a) >> 8) & 0xff, (a) & 0xff, \ >>>> + ((b) >> 8) & 0xff, (b) & 0xff, \ >>>> + ((c) >> 8) & 0xff, (c) & 0xff, \ >>>> + (d0), (d1), (d2), (d3), (d4), (d5), (d6), (d7) } } } >>>> + >>>> +#define UEFI_CPER_SEC_PLATFORM_MEM \ >>>> + UUID_BE(0xA5BC1114, 0x6F64, 0x4EDE, 0xB8, 0x63, 0x3E, 0x83, \ >>>> + 0xED, 0x7C, 0x83, 0xB1) >>>> + >>>> /* > > As suggested in different thread - could this be also made common with > NVMe code ? Sure, I will make it common in a separate patch. >>>> @@ -1036,6 +1062,44 @@ int kvm_arch_get_registers(CPUState *cs) >>>> return ret; >>>> } >>>> >>>> +void kvm_arch_on_sigbus_vcpu(CPUState *c, int code, void *addr) >>>> +{ >>>> + ram_addr_t ram_addr; >>>> + hwaddr paddr; >>>> + >>>> + assert(code == BUS_MCEERR_AR || code == BUS_MCEERR_AO); >>>> + >>>> + if (acpi_enabled && addr && >>>> + object_property_get_bool(qdev_get_machine(), "ras", NULL)) { >>>> + ram_addr = qemu_ram_addr_from_host(addr); >>>> + if (ram_addr != RAM_ADDR_INVALID && >>>> + kvm_physical_memory_addr_from_host(c->kvm_state, addr, &paddr)) { >>>> + kvm_hwpoison_page_add(ram_addr); >>>> + /* >>>> + * Asynchronous signal will be masked by main thread, so >>>> + * only handle synchronous signal. >>>> + */ >>> >>> I'm not entirely sure that the comment above is correct (it has been >>> pointed out before). I would expect the AO signal to be handled here as >>> well. Not having proper support to do that just yet is another story but >>> the comment might be bit misleading. >>> >> >> We also expect the AO signal can be handled here. Maybe we could add the comment like: >> >> "Asynchronous signal is masked by main thread now. Once it can be asserted, we could >> handle it." :) >> > Still not entirely there - if I'm not mistaken. Both BUS_MCEERR_AR and > BUS_MVEERR_AO can end up here. > I'm not entirely sure what you mean by "masked by main thread" ? Both will be > handled by sigbus_handler and as such both will end up here either > directly through kvm_on_sigbus > or through kvm_cpu_exec with pending sigbus. Or am I misguided ? > In fact BUS_MCEERR_AO cannot go to here, because QEMU main thread masks the SIGBUS signal[1] and vcpu threads can only handle the BUS_MCEERR_AR. Qemu Main Thread VCPU Threads Kernel: Mask SIGBUS AO SIGBUS would be send to Qemu main thread in kernel(kill_proc()) KVM: Mask SIGBUS Only send AR SIGBUS to VCPU threads in KVM(kvm_send_hwpoison_signal()) However, maybe we shouldn't consider the behaviors of kernel or KVM and just keep the logic of handling the AO signal in kvm_arch_on_sigbus_vcpu() like what x86 version does. [1] https://lists.gnu.org/archive/html/qemu-devel/2017-11/msg03575.html -- Thanks, Xiang From MAILER-DAEMON Mon Dec 02 23:13:25 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1ibzYz-0005ch-16 for mharc-qemu-arm@gnu.org; Mon, 02 Dec 2019 23:13:25 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:32869) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ibzYu-0005Zz-Je for qemu-arm@nongnu.org; Mon, 02 Dec 2019 23:13:22 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ibzYt-00013g-FD for qemu-arm@nongnu.org; Mon, 02 Dec 2019 23:13:20 -0500 Received: from wout1-smtp.messagingengine.com ([64.147.123.24]:40661) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1ibzYs-00011e-TO; Mon, 02 Dec 2019 23:13:19 -0500 Received: from compute4.internal (compute4.nyi.internal [10.202.2.44]) by mailout.west.internal (Postfix) with ESMTP id 61CB25C3; Mon, 2 Dec 2019 23:13:17 -0500 (EST) Received: from mailfrontend1 ([10.202.2.162]) by compute4.internal (MEProxy); Mon, 02 Dec 2019 23:13:17 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=aj.id.au; h=from :to:cc:subject:date:message-id:mime-version:content-type :content-transfer-encoding; s=fm1; bh=QNsQgXYGYrk1YAopBqhxivrkfW 0hwxhGi//jQO/OV+Y=; b=W9Ga0kapNxAUI7CfChi/1lwKgYjYSBTH0ke+a0x9mt W8EV/L/YRFjKWsHATsaL0VAO+9By4PIq+bfInCeLgxNjIYdtEb38mof0d08MhnNi VioBEZvDe4BPvbagcCJ40wK1H4p2ONK1TPkQds7HQbQMmnlKSUn7d7ZGblzabqas 3/vHWDoBGpuB/r9Ltva0ZhOkZuf/jLXqFm7zj/QQIaIlI2IHgGcdzsVOg1D1ip+6 EopWiRgdaNfmmOaamvoIxyljgn/DDTZGW0Yotb8QXbVrD+HrE0WAjcENPzE9XAXN AhN6g0IfHoMNkJc0o53WFZqiTc/lShloI88lTYNPRdhQ== DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d= messagingengine.com; h=cc:content-transfer-encoding:content-type :date:from:message-id:mime-version:subject:to:x-me-proxy :x-me-proxy:x-me-sender:x-me-sender:x-sasl-enc; s=fm1; bh=QNsQgX YGYrk1YAopBqhxivrkfW0hwxhGi//jQO/OV+Y=; b=DOQ9gAUdeYVmcEArki+n0s ZJ1PpLNZ3CohTIiRNfNuJsk3SFbHoIpY+RsGoWdHbpEMRJp05XQot6Hhn9x96PaL lA2uYVD9zHD6g0FsEr1BomSNp7QIbE0/rZN6b/cKY6vorEkgp9zXwRepNEu2pFZh VTxDy3WY+dJGnMXPn5zDd/eUDzA0NxTs8SLnagcLY+MlO9NztWB5VP6Pv11zmXSm 2LAJUENoxAAnhBQn7yMOQoHe71VJe1gZzoyC+SQAh10FH8JUwAtd7IwpWbmx17E9 m06DcCn6US75U6AYUrp30Ab79//3gM74yiJvxc6InYX876ORQJYqpqfMMlzY3ZKw == X-ME-Sender: X-ME-Proxy-Cause: gggruggvucftvghtrhhoucdtuddrgedufedrudejiedgieeiucetufdoteggodetrfdotf fvucfrrhhofhhilhgvmecuhfgrshhtofgrihhlpdfqfgfvpdfurfetoffkrfgpnffqhgen uceurghilhhouhhtmecufedttdenucenucfjughrpefhvffufffkofggtgfgsehtkeertd ertdejnecuhfhrohhmpeetnhgurhgvficulfgvfhhfvghrhicuoegrnhgurhgvfiesrghj rdhiugdrrghuqeenucffohhmrghinhepohiilhgrsghsrdhorhhgnecukfhppedvtddvrd ekuddrudekrdeftdenucfrrghrrghmpehmrghilhhfrhhomheprghnughrvgifsegrjhdr ihgurdgruhenucevlhhushhtvghrufhiiigvpedt X-ME-Proxy: Received: from mistburn.au.ibm.com (bh02i525f01.au.ibm.com [202.81.18.30]) by mail.messagingengine.com (Postfix) with ESMTPA id 1497B8005A; Mon, 2 Dec 2019 23:13:13 -0500 (EST) From: Andrew Jeffery To: qemu-arm@nongnu.org Cc: clg@kaod.org, peter.maydell@linaro.org, joel@jms.id.au, qemu-devel@nongnu.org Subject: [PATCH v2 0/4] Expose GT CNTFRQ as a CPU property to support AST2600 Date: Tue, 3 Dec 2019 14:44:36 +1030 Message-Id: <20191203041440.6275-1-andrew@aj.id.au> X-Mailer: git-send-email 2.20.1 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 64.147.123.24 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 03 Dec 2019 04:13:23 -0000 Hello, This is a v2 of the belated follow-up from a few of my earlier attempts to fix up the ARM generic timer for correct behaviour on the ASPEED AST2600 SoC. The AST2600 clocks the generic timer at the rate of HPLL, which is configured to 1125MHz. This is significantly quicker than the currently hard-coded generic timer rate of 62.5MHz and so we see "sticky" behaviour in the guest. v1 can be found here: https://patchwork.ozlabs.org/cover/1201887/ Changes since v1: * Fix a user mode build failure from partial renaming of gt_cntfrq_period_ns() * Add tags from Cedric and Richard Please review. Andrew Andrew Jeffery (4): target/arm: Remove redundant scaling of nexttick target/arm: Abstract the generic timer frequency target/arm: Prepare generic timer for per-platform CNTFRQ ast2600: Configure CNTFRQ at 1125MHz hw/arm/aspeed_ast2600.c | 3 +++ target/arm/cpu.c | 41 +++++++++++++++++++++++++++++++++-------- target/arm/cpu.h | 28 ++++++++++++++++++++++++++++ target/arm/helper.c | 24 ++++++++++++++++++------ 4 files changed, 82 insertions(+), 14 deletions(-) -- 2.20.1 From MAILER-DAEMON Mon Dec 02 23:13:27 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1ibzZ1-0005fV-6f for mharc-qemu-arm@gnu.org; Mon, 02 Dec 2019 23:13:27 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:33195) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ibzYx-0005b8-6S for qemu-arm@nongnu.org; Mon, 02 Dec 2019 23:13:24 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ibzYv-00016p-Il for qemu-arm@nongnu.org; Mon, 02 Dec 2019 23:13:22 -0500 Received: from wout1-smtp.messagingengine.com ([64.147.123.24]:34713) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1ibzYv-00015I-2A; Mon, 02 Dec 2019 23:13:21 -0500 Received: from compute4.internal (compute4.nyi.internal [10.202.2.44]) by mailout.west.internal (Postfix) with ESMTP id CE5C2EC1; Mon, 2 Dec 2019 23:13:19 -0500 (EST) Received: from mailfrontend1 ([10.202.2.162]) by compute4.internal (MEProxy); Mon, 02 Dec 2019 23:13:20 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=aj.id.au; h=from :to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-type:content-transfer-encoding; s=fm1; bh= xQZFQojovBLO7NXxKyIwYjcITEQBg1WTDSYEUPbUvsQ=; b=psiTW247RLk6Bn+b OHJ5bOJIY8TB3QfJNrWZKWoaqlJH8mcSWBn/vWjFZ/ZgPw8cjt3K8dLeJaJB7NRf zyNfEkpZP20Q2oU8zIUkJdy2Fc0mBxaeQAd5U9D5rDPKglmsKR+9PKA2zBPtArZY y1o6S0+Yt2Ff2YjEmnmKrYi2pvu7XzlFAgxHad9lHJilgDkNm1MnfuGXqhzo+JwN E/z290Nvo9At28xjYL3qS25dv1+booOAgTR+vR49KdyDpr3QNb4+DpsOAc0yivaa mpUkN+4yselQnRNTIztQeGzE57EN9P8N3e0wKQZ8dMXV6of2Eh0MhEVZ1H2IuDj1 jb9aHw== DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d= messagingengine.com; h=cc:content-transfer-encoding:content-type :date:from:in-reply-to:message-id:mime-version:references :subject:to:x-me-proxy:x-me-proxy:x-me-sender:x-me-sender :x-sasl-enc; s=fm1; bh=xQZFQojovBLO7NXxKyIwYjcITEQBg1WTDSYEUPbUv sQ=; b=DltCjfY/2s8M8DMpmvBsds5dpYyaozh1+KoFQaO1Momh73PY3egzFmyeo YWU1Stu/9b8ZR+9KTZmMtzlNmQrm2ZiYQIhzEMO5sXgtup1XeOx1nD5CCngIlnnB QQAX7udwxoL+2v2Iu7Gru2sdwma07/PmNhxOTVbrQw1IpISaEPGSn85Z9yDXImBV kYo0fcrLvKsQuG0l+DLR7Rd5rLqR37w7ulUxPorU5q/vCAAEwx9a1fOSJjR+sfzo 3tjTSjnsoUzXNfNtEbyNUU2j5x3X2YQvoVW2GAQcpRwoVjHUCiRW5gVEQg2tWnjT iMt/i5nHYr8zeL8zSKPO3idwjo5OQ== X-ME-Sender: X-ME-Proxy-Cause: gggruggvucftvghtrhhoucdtuddrgedufedrudejiedgieeiucetufdoteggodetrfdotf fvucfrrhhofhhilhgvmecuhfgrshhtofgrihhlpdfqfgfvpdfurfetoffkrfgpnffqhgen uceurghilhhouhhtmecufedttdenucesvcftvggtihhpihgvnhhtshculddquddttddmne cujfgurhephffvufffkffojghfgggtgfesthekredtredtjeenucfhrhhomheptehnughr vgifucflvghffhgvrhihuceorghnughrvgifsegrjhdrihgurdgruheqnecukfhppedvtd dvrdekuddrudekrdeftdenucfrrghrrghmpehmrghilhhfrhhomheprghnughrvgifsegr jhdrihgurdgruhenucevlhhushhtvghrufhiiigvpedt X-ME-Proxy: Received: from mistburn.au.ibm.com (bh02i525f01.au.ibm.com [202.81.18.30]) by mail.messagingengine.com (Postfix) with ESMTPA id D29B48005C; Mon, 2 Dec 2019 23:13:16 -0500 (EST) From: Andrew Jeffery To: qemu-arm@nongnu.org Cc: clg@kaod.org, peter.maydell@linaro.org, joel@jms.id.au, qemu-devel@nongnu.org, Richard Henderson Subject: [PATCH v2 1/4] target/arm: Remove redundant scaling of nexttick Date: Tue, 3 Dec 2019 14:44:37 +1030 Message-Id: <20191203041440.6275-2-andrew@aj.id.au> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20191203041440.6275-1-andrew@aj.id.au> References: <20191203041440.6275-1-andrew@aj.id.au> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 64.147.123.24 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 03 Dec 2019 04:13:24 -0000 The corner-case codepath was adjusting nexttick such that overflow wouldn't occur when timer_mod() scaled the value back up. Remove a use of GTIMER_SCALE and avoid unnecessary operations by calling timer_mod_ns() directly. Signed-off-by: Andrew Jeffery Reviewed-by: Richard Henderson Reviewed-by: Cédric Le Goater --- target/arm/helper.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index a089fb5a6909..65c4441a3896 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -2446,9 +2446,10 @@ static void gt_recalc_timer(ARMCPU *cpu, int timeridx) * timer expires we will reset the timer for any remaining period. */ if (nexttick > INT64_MAX / GTIMER_SCALE) { - nexttick = INT64_MAX / GTIMER_SCALE; + timer_mod_ns(cpu->gt_timer[timeridx], INT64_MAX); + } else { + timer_mod(cpu->gt_timer[timeridx], nexttick); } - timer_mod(cpu->gt_timer[timeridx], nexttick); trace_arm_gt_recalc(timeridx, irqstate, nexttick); } else { /* Timer disabled: ISTATUS and timer output always clear */ -- 2.20.1 From MAILER-DAEMON Mon Dec 02 23:13:30 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1ibzZ3-0005i5-SS for mharc-qemu-arm@gnu.org; Mon, 02 Dec 2019 23:13:29 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:33623) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ibzYz-0005dw-PM for qemu-arm@nongnu.org; Mon, 02 Dec 2019 23:13:26 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ibzYy-0001BM-IX for qemu-arm@nongnu.org; Mon, 02 Dec 2019 23:13:25 -0500 Received: from wout1-smtp.messagingengine.com ([64.147.123.24]:56831) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1ibzYy-00019R-9q; Mon, 02 Dec 2019 23:13:24 -0500 Received: from compute4.internal (compute4.nyi.internal [10.202.2.44]) by mailout.west.internal (Postfix) with ESMTP id F2E39C28; Mon, 2 Dec 2019 23:13:22 -0500 (EST) Received: from mailfrontend1 ([10.202.2.162]) by compute4.internal (MEProxy); Mon, 02 Dec 2019 23:13:23 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=aj.id.au; h=from :to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; s=fm1; bh=rb9NcXkJ9zfKj 9uToigm9zdKRmguNiX84tLrvX+4KtM=; b=rxWOCAb4QrTYOHw+AOy9CHaP5yQDu ds+pxsIFfO9BFgBI7FoLLK0qXoKMCesOvXF1pj3ogu+akepRTdud9P5IyiDf6E9I HYoKDLKa7qRu9+aNbSBmCBnxV82dR7xbjwjrMz4zUlOtqT6jdqM2BiKRvrGhBKs0 2AlmCWFeiZIbsHqfjDDrq4HDm7AaIyl8KX2m9mu195yT6/CdI/MO0M3j2u1FYkVY blZ9DmDe7az8dkBE5TNDLMGY+Yr2au8jFekLESI4N+3uBlOPl8wJF2IkT28TA7J3 bQn+/y3rcladJtUYeXMGy+BstGRWwxLFVFa4Q9lCkwcya3sGsTm5eYB+A== DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d= messagingengine.com; h=cc:content-transfer-encoding:date:from :in-reply-to:message-id:mime-version:references:subject:to :x-me-proxy:x-me-proxy:x-me-sender:x-me-sender:x-sasl-enc; s= fm1; bh=rb9NcXkJ9zfKj9uToigm9zdKRmguNiX84tLrvX+4KtM=; b=WkWYouxI 5CUu77WyTFyO2M6zDePAr/jScj+GR/8I3O1OKS/wMkCJcoao/7xt+pkb5ceAQRw0 Cs74PJMWZ8/x4LXr5vZh5UGHxKxSTKsOJC/LrjYC+f+OAIJgvDTN4kbJSyBQysnD u81Cv8VAA+18JaHK085JNmtcLYPRk9755gp2tjWOc3FweK5GROnQXSfNVD3K0pP6 BYw8nLFQnIuDGG+tvH/6tVVh9ZmQ+n06c4UcvATaD9gCfGZ2irydJv9OELuxfsO/ KrDa+9GKXmi+FoalFwcjtIwHahZ6a/vbgJR90NOdcKFXPxrs2tdFm2aCCagTNpED L3Akb93Vzv5wKA== X-ME-Sender: X-ME-Proxy-Cause: gggruggvucftvghtrhhoucdtuddrgedufedrudejiedgieeiucetufdoteggodetrfdotf fvucfrrhhofhhilhgvmecuhfgrshhtofgrihhlpdfqfgfvpdfurfetoffkrfgpnffqhgen uceurghilhhouhhtmecufedttdenucesvcftvggtihhpihgvnhhtshculddquddttddmne cujfgurhephffvufffkffojghfggfgsedtkeertdertddtnecuhfhrohhmpeetnhgurhgv ficulfgvfhhfvghrhicuoegrnhgurhgvfiesrghjrdhiugdrrghuqeenucfkphepvddtvd drkedurddukedrfedtnecurfgrrhgrmhepmhgrihhlfhhrohhmpegrnhgurhgvfiesrghj rdhiugdrrghunecuvehluhhsthgvrhfuihiivgeptd X-ME-Proxy: Received: from mistburn.au.ibm.com (bh02i525f01.au.ibm.com [202.81.18.30]) by mail.messagingengine.com (Postfix) with ESMTPA id E375C80060; Mon, 2 Dec 2019 23:13:19 -0500 (EST) From: Andrew Jeffery To: qemu-arm@nongnu.org Cc: clg@kaod.org, peter.maydell@linaro.org, joel@jms.id.au, qemu-devel@nongnu.org, Richard Henderson Subject: [PATCH v2 2/4] target/arm: Abstract the generic timer frequency Date: Tue, 3 Dec 2019 14:44:38 +1030 Message-Id: <20191203041440.6275-3-andrew@aj.id.au> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20191203041440.6275-1-andrew@aj.id.au> References: <20191203041440.6275-1-andrew@aj.id.au> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 64.147.123.24 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 03 Dec 2019 04:13:27 -0000 Prepare for SoCs such as the ASPEED AST2600 whose firmware configures CNTFRQ to values significantly larger than the static 62.5MHz value currently derived from GTIMER_SCALE. As the OS potentially derives its timer periods from the CNTFRQ value the lack of support for running QEMUTimers at the appropriate rate leads to sticky behaviour in the guest. Substitute the GTIMER_SCALE constant with use of a helper to derive the period from gt_cntfrq stored in struct ARMCPU. Initially set gt_cntfrq to the frequency associated with GTIMER_SCALE so current behaviour is maintained. Signed-off-by: Andrew Jeffery Reviewed-by: Richard Henderson --- target/arm/cpu.c | 2 ++ target/arm/cpu.h | 10 ++++++++++ target/arm/helper.c | 10 +++++++--- 3 files changed, 19 insertions(+), 3 deletions(-) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 7a4ac9339bf9..5698a74061bb 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -974,6 +974,8 @@ static void arm_cpu_initfn(Object *obj) if (tcg_enabled()) { cpu->psci_version = 2; /* TCG implements PSCI 0.2 */ } + + cpu->gt_cntfrq = NANOSECONDS_PER_SECOND / GTIMER_SCALE; } static Property arm_cpu_reset_cbar_property = diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 83a809d4bac4..666c03871fdf 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -932,8 +932,18 @@ struct ARMCPU { */ DECLARE_BITMAP(sve_vq_map, ARM_MAX_VQ); DECLARE_BITMAP(sve_vq_init, ARM_MAX_VQ); + + /* Generic timer counter frequency, in Hz */ + uint64_t gt_cntfrq; }; +static inline unsigned int gt_cntfrq_period_ns(ARMCPU *cpu) +{ + /* XXX: Could include qemu/timer.h to get NANOSECONDS_PER_SECOND? */ + const unsigned int ns_per_s = 1000 * 1000 * 1000; + return ns_per_s > cpu->gt_cntfrq ? ns_per_s / cpu->gt_cntfrq : 1; +} + void arm_cpu_post_init(Object *obj); uint64_t arm_cpu_mp_affinity(int idx, uint8_t clustersz); diff --git a/target/arm/helper.c b/target/arm/helper.c index 65c4441a3896..2622a9a8d02f 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -2409,7 +2409,9 @@ static CPAccessResult gt_stimer_access(CPUARMState *env, static uint64_t gt_get_countervalue(CPUARMState *env) { - return qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) / GTIMER_SCALE; + ARMCPU *cpu = env_archcpu(env); + + return qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) / gt_cntfrq_period_ns(cpu); } static void gt_recalc_timer(ARMCPU *cpu, int timeridx) @@ -2445,7 +2447,7 @@ static void gt_recalc_timer(ARMCPU *cpu, int timeridx) * set the timer for as far in the future as possible. When the * timer expires we will reset the timer for any remaining period. */ - if (nexttick > INT64_MAX / GTIMER_SCALE) { + if (nexttick > INT64_MAX / gt_cntfrq_period_ns(cpu)) { timer_mod_ns(cpu->gt_timer[timeridx], INT64_MAX); } else { timer_mod(cpu->gt_timer[timeridx], nexttick); @@ -2874,11 +2876,13 @@ static const ARMCPRegInfo generic_timer_cp_reginfo[] = { static uint64_t gt_virt_cnt_read(CPUARMState *env, const ARMCPRegInfo *ri) { + ARMCPU *cpu = env_archcpu(env); + /* Currently we have no support for QEMUTimer in linux-user so we * can't call gt_get_countervalue(env), instead we directly * call the lower level functions. */ - return cpu_get_clock() / GTIMER_SCALE; + return cpu_get_clock() / gt_cntfrq_period_ns(cpu); } static const ARMCPRegInfo generic_timer_cp_reginfo[] = { -- 2.20.1 From MAILER-DAEMON Mon Dec 02 23:13:35 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1ibzZ8-0005mI-1r for mharc-qemu-arm@gnu.org; Mon, 02 Dec 2019 23:13:35 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:34016) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ibzZ3-0005hV-FJ for qemu-arm@nongnu.org; Mon, 02 Dec 2019 23:13:31 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ibzZ1-0001Fs-G5 for qemu-arm@nongnu.org; Mon, 02 Dec 2019 23:13:29 -0500 Received: from wout1-smtp.messagingengine.com ([64.147.123.24]:56489) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1ibzZ1-0001El-7c; Mon, 02 Dec 2019 23:13:27 -0500 Received: from compute4.internal (compute4.nyi.internal [10.202.2.44]) by mailout.west.internal (Postfix) with ESMTP id 08B10ED2; Mon, 2 Dec 2019 23:13:25 -0500 (EST) Received: from mailfrontend1 ([10.202.2.162]) by compute4.internal (MEProxy); Mon, 02 Dec 2019 23:13:26 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=aj.id.au; h=from :to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; s=fm1; bh=UnMHwPPfQ4KRN 61OUf/u4EXG5kQhV6gU2lUxKArzxDo=; b=jv6kpy63xqnWAhau27nV+ZCposTPf kiQ61fjwkzCXyx/Nk8bWtxMAnkHfKVViOVY6PuS4AA0EoEMDAdlaNL4FsmyLGDtJ rt/WrlC9YEZy+fSFRIOMgQOImGseiVyLrxYGTc3JUtFUzf1vNQTYHVHK9sltf/i8 6nxyFr72oG1+huUPdAydtc5eV/JL5uvxTze4u3sRc13hrUlTAYXewTBO+SiZmRLY txueFKm1YRVYmq44VXzQnLBq3qeSAAQ/c8ELJNsLyLLmKOqgWtbzNfuVvZ0Pxzsk a/EA/R3XwU+weeGsAnc9R7JDTQyZ9GiuV7VNtwQUybiR8qVBQeTE6mJTg== DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d= messagingengine.com; h=cc:content-transfer-encoding:date:from :in-reply-to:message-id:mime-version:references:subject:to :x-me-proxy:x-me-proxy:x-me-sender:x-me-sender:x-sasl-enc; s= fm1; bh=UnMHwPPfQ4KRN61OUf/u4EXG5kQhV6gU2lUxKArzxDo=; b=uT9tE2oL Y9GYFM8myJifEkSq33gIoLUwOb63A9AWdaSmY1Qmn8x/WnFmmIv8d2cOsTRTb3DR vxqo3/C/xn4ssizCYw1XEJDyprvPyirB7GT2NcgRk7wOIvSwNI83cwTRH/Nxe7or BYo3kIMWkXQPrk+fmrUIBm4nsy4zWRCwnBJ+L1X+WaWQXCtDWpLFywlYDwXPQzBv X1NYDo/mjfaQcKzapjqDZLWYfiY1LPY4MWO275HE2o09CKkHC55M9oGxdPBbxMGH oHxRkK4sbptx0G5IrmZVJJVK1IFmoIfU3R5uZDSdq1iOelYt/coWxTVov1vzyMd3 ta+nnviQ9FhXFg== X-ME-Sender: X-ME-Proxy-Cause: gggruggvucftvghtrhhoucdtuddrgedufedrudejiedgieeiucetufdoteggodetrfdotf fvucfrrhhofhhilhgvmecuhfgrshhtofgrihhlpdfqfgfvpdfurfetoffkrfgpnffqhgen uceurghilhhouhhtmecufedttdenucesvcftvggtihhpihgvnhhtshculddquddttddmne cujfgurhephffvufffkffojghfggfgsedtkeertdertddtnecuhfhrohhmpeetnhgurhgv ficulfgvfhhfvghrhicuoegrnhgurhgvfiesrghjrdhiugdrrghuqeenucfkphepvddtvd drkedurddukedrfedtnecurfgrrhgrmhepmhgrihhlfhhrohhmpegrnhgurhgvfiesrghj rdhiugdrrghunecuvehluhhsthgvrhfuihiivgepud X-ME-Proxy: Received: from mistburn.au.ibm.com (bh02i525f01.au.ibm.com [202.81.18.30]) by mail.messagingengine.com (Postfix) with ESMTPA id EE4028005A; Mon, 2 Dec 2019 23:13:22 -0500 (EST) From: Andrew Jeffery To: qemu-arm@nongnu.org Cc: clg@kaod.org, peter.maydell@linaro.org, joel@jms.id.au, qemu-devel@nongnu.org, Richard Henderson Subject: [PATCH v2 3/4] target/arm: Prepare generic timer for per-platform CNTFRQ Date: Tue, 3 Dec 2019 14:44:39 +1030 Message-Id: <20191203041440.6275-4-andrew@aj.id.au> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20191203041440.6275-1-andrew@aj.id.au> References: <20191203041440.6275-1-andrew@aj.id.au> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 64.147.123.24 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 03 Dec 2019 04:13:32 -0000 The ASPEED AST2600 clocks the generic timer at the rate of HPLL. On recent firmwares this is at 1125MHz, which is considerably quicker than the assumed 62.5MHz of the current generic timer implementation. The delta between the value as read from CNTFRQ and the true rate of the underlying QEMUTimer leads to sticky behaviour in AST2600 guests. Add a feature-gated property exposing CNTFRQ for ARM CPUs providing the generic timer. This allows platforms to configure CNTFRQ (and the associated QEMUTimer) to the appropriate frequency prior to starting the guest. As the platform can now determine the rate of CNTFRQ we're exposed to limitations of QEMUTimer that didn't previously materialise: In the course of emulation we need to arbitrarily and accurately convert between guest ticks and time, but we're constrained by QEMUTimer's use of an integer scaling factor. The effect is QEMUTimer cannot exactly capture the period of frequencies that do not cleanly divide NANOSECONDS_PER_SECOND for scaling ticks to time. As such, provide an equally inaccurate scaling factor for scaling time to ticks so at least a self-consistent inverse relationship holds. Signed-off-by: Andrew Jeffery Reviewed-by: Richard Henderson --- target/arm/cpu.c | 43 +++++++++++++++++++++++++++++++++---------- target/arm/cpu.h | 18 ++++++++++++++++++ target/arm/helper.c | 9 ++++++++- 3 files changed, 59 insertions(+), 11 deletions(-) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 5698a74061bb..f186019a77fd 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -974,10 +974,12 @@ static void arm_cpu_initfn(Object *obj) if (tcg_enabled()) { cpu->psci_version = 2; /* TCG implements PSCI 0.2 */ } - - cpu->gt_cntfrq = NANOSECONDS_PER_SECOND / GTIMER_SCALE; } +static Property arm_cpu_gt_cntfrq_property = + DEFINE_PROP_UINT64("cntfrq", ARMCPU, gt_cntfrq, + NANOSECONDS_PER_SECOND / GTIMER_SCALE); + static Property arm_cpu_reset_cbar_property = DEFINE_PROP_UINT64("reset-cbar", ARMCPU, reset_cbar, 0); @@ -1174,6 +1176,11 @@ void arm_cpu_post_init(Object *obj) qdev_property_add_static(DEVICE(obj), &arm_cpu_cfgend_property, &error_abort); + + if (arm_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER)) { + qdev_property_add_static(DEVICE(cpu), &arm_cpu_gt_cntfrq_property, + &error_abort); + } } static void arm_cpu_finalizefn(Object *obj) @@ -1253,14 +1260,30 @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp) } } - cpu->gt_timer[GTIMER_PHYS] = timer_new(QEMU_CLOCK_VIRTUAL, GTIMER_SCALE, - arm_gt_ptimer_cb, cpu); - cpu->gt_timer[GTIMER_VIRT] = timer_new(QEMU_CLOCK_VIRTUAL, GTIMER_SCALE, - arm_gt_vtimer_cb, cpu); - cpu->gt_timer[GTIMER_HYP] = timer_new(QEMU_CLOCK_VIRTUAL, GTIMER_SCALE, - arm_gt_htimer_cb, cpu); - cpu->gt_timer[GTIMER_SEC] = timer_new(QEMU_CLOCK_VIRTUAL, GTIMER_SCALE, - arm_gt_stimer_cb, cpu); + + { + uint64_t scale; + + if (arm_feature(env, ARM_FEATURE_GENERIC_TIMER)) { + if (!cpu->gt_cntfrq) { + error_setg(errp, "Invalid CNTFRQ: %"PRId64"Hz", + cpu->gt_cntfrq); + return; + } + scale = gt_cntfrq_period_ns(cpu); + } else { + scale = GTIMER_SCALE; + } + + cpu->gt_timer[GTIMER_PHYS] = timer_new(QEMU_CLOCK_VIRTUAL, scale, + arm_gt_ptimer_cb, cpu); + cpu->gt_timer[GTIMER_VIRT] = timer_new(QEMU_CLOCK_VIRTUAL, scale, + arm_gt_vtimer_cb, cpu); + cpu->gt_timer[GTIMER_HYP] = timer_new(QEMU_CLOCK_VIRTUAL, scale, + arm_gt_htimer_cb, cpu); + cpu->gt_timer[GTIMER_SEC] = timer_new(QEMU_CLOCK_VIRTUAL, scale, + arm_gt_stimer_cb, cpu); + } #endif cpu_exec_realizefn(cs, &local_err); diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 666c03871fdf..0bcd13dcac81 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -939,6 +939,24 @@ struct ARMCPU { static inline unsigned int gt_cntfrq_period_ns(ARMCPU *cpu) { + /* + * The exact approach to calculating guest ticks is: + * + * muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), cpu->gt_cntfrq, + * NANOSECONDS_PER_SECOND); + * + * We don't do that. Rather we intentionally use integer division + * truncation below and in the caller for the conversion of host monotonic + * time to guest ticks to provide the exact inverse for the semantics of + * the QEMUTimer scale factor. QEMUTimer's scale facter is an integer, so + * it loses precision when representing frequencies where + * `(NANOSECONDS_PER_SECOND % cpu->gt_cntfrq) > 0` holds. Failing to + * provide an exact inverse leads to scheduling timers with negative + * periods, which in turn leads to sticky behaviour in the guest. + * + * Finally, CNTFRQ is effectively capped at 1GHz to ensure our scale factor + * cannot become zero. + */ /* XXX: Could include qemu/timer.h to get NANOSECONDS_PER_SECOND? */ const unsigned int ns_per_s = 1000 * 1000 * 1000; return ns_per_s > cpu->gt_cntfrq ? ns_per_s / cpu->gt_cntfrq : 1; diff --git a/target/arm/helper.c b/target/arm/helper.c index 2622a9a8d02f..da960d17040b 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -2683,6 +2683,13 @@ void arm_gt_stimer_cb(void *opaque) gt_recalc_timer(cpu, GTIMER_SEC); } +static void arm_gt_cntfrq_reset(CPUARMState *env, const ARMCPRegInfo *opaque) +{ + ARMCPU *cpu = env_archcpu(env); + + cpu->env.cp15.c14_cntfrq = cpu->gt_cntfrq; +} + static const ARMCPRegInfo generic_timer_cp_reginfo[] = { /* Note that CNTFRQ is purely reads-as-written for the benefit * of software; writing it doesn't actually change the timer frequency. @@ -2697,7 +2704,7 @@ static const ARMCPRegInfo generic_timer_cp_reginfo[] = { .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 0, .opc2 = 0, .access = PL1_RW | PL0_R, .accessfn = gt_cntfrq_access, .fieldoffset = offsetof(CPUARMState, cp15.c14_cntfrq), - .resetvalue = (1000 * 1000 * 1000) / GTIMER_SCALE, + .resetfn = arm_gt_cntfrq_reset, }, /* overall control: mostly access permissions */ { .name = "CNTKCTL", .state = ARM_CP_STATE_BOTH, -- 2.20.1 From MAILER-DAEMON Mon Dec 02 23:13:41 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1ibzZF-0005rh-KQ for mharc-qemu-arm@gnu.org; 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Mon, 2 Dec 2019 23:13:25 -0500 (EST) From: Andrew Jeffery To: qemu-arm@nongnu.org Cc: clg@kaod.org, peter.maydell@linaro.org, joel@jms.id.au, qemu-devel@nongnu.org, Richard Henderson Subject: [PATCH v2 4/4] ast2600: Configure CNTFRQ at 1125MHz Date: Tue, 3 Dec 2019 14:44:40 +1030 Message-Id: <20191203041440.6275-5-andrew@aj.id.au> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20191203041440.6275-1-andrew@aj.id.au> References: <20191203041440.6275-1-andrew@aj.id.au> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 64.147.123.24 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 03 Dec 2019 04:13:38 -0000 This matches the configuration set by u-boot on the AST2600. Signed-off-by: Andrew Jeffery Reviewed-by: Richard Henderson Reviewed-by: Cédric Le Goater --- hw/arm/aspeed_ast2600.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/hw/arm/aspeed_ast2600.c b/hw/arm/aspeed_ast2600.c index 931887ac681f..5aecc3b3caec 100644 --- a/hw/arm/aspeed_ast2600.c +++ b/hw/arm/aspeed_ast2600.c @@ -259,6 +259,9 @@ static void aspeed_soc_ast2600_realize(DeviceState *dev, Error **errp) object_property_set_int(OBJECT(&s->cpu[i]), aspeed_calc_affinity(i), "mp-affinity", &error_abort); + object_property_set_int(OBJECT(&s->cpu[i]), 1125000000, "cntfrq", + &error_abort); + /* * TODO: the secondary CPUs are started and a boot helper * is needed when using -kernel -- 2.20.1 From MAILER-DAEMON Tue Dec 03 01:05:50 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1ic1Jm-0002Tm-1z for mharc-qemu-arm@gnu.org; Tue, 03 Dec 2019 01:05:50 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:38488) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ic1Jj-0002TI-6v for qemu-arm@nongnu.org; Tue, 03 Dec 2019 01:05:48 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ic1Jg-0005Hl-LN for qemu-arm@nongnu.org; Tue, 03 Dec 2019 01:05:45 -0500 Received: from us-smtp-2.mimecast.com ([207.211.31.81]:47499 helo=us-smtp-delivery-1.mimecast.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1ic1Jg-0005Fc-FO for qemu-arm@nongnu.org; Tue, 03 Dec 2019 01:05:44 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1575353143; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=Uvedzpt4OkIgx2yiLQUlMfryhKEnzzdOmhEosWuDBL0=; b=c43+a1nNFnnvJu73mRFRnh0tKF/Brq9vvjIA4fnJAYzd9OUEqQMCgXG1iKybWQji2Cx79V bTCbtA6ry7hFJ7jZqkPn1OtpTx729q9BXfpvPBAIZsb1BRGJe1Oaxv8mlYD28fNh/v9zlB rxDE6emjpv2619RXSd7+pAEHAnicdeY= Received: from mail-wm1-f69.google.com (mail-wm1-f69.google.com [209.85.128.69]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-375-XR4lizlWNgS93tHlJsWgRA-1; Tue, 03 Dec 2019 01:05:42 -0500 Received: by mail-wm1-f69.google.com with SMTP id n4so548015wmd.7 for ; Mon, 02 Dec 2019 22:05:42 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:subject:to:cc:references:from:message-id:date :user-agent:mime-version:in-reply-to:content-language :content-transfer-encoding; bh=Uvedzpt4OkIgx2yiLQUlMfryhKEnzzdOmhEosWuDBL0=; b=NUsG4h6lj5n9fZLhDoClUrA4KPLBnqARWuZW7Cq1BIR5NyGaJ9qmBD1ZZ5rbsHmQzk c6UYlP1AZeIv9kU6QfAiP0i8imXLBHv2MpLFVmi/bci/13HCS7FjTNeiWrB/fRKtErmr 1JIL1h31Dnd2gceUCCgkg2VNl5OQ7YskkqRZ7FlqGFLhM539i8H9KJirHNjDvQziRm9h jSMeZ/IqYRPBhZnDoy0WpBUmDLsHRDX7kLMf3fx68yfkh01f8CVwiA/in6DQkCq4m5DA InDBqvoHh1JKp0aqp9tmRJrroCQt8yjJdCxnFQpewo/GWoTpeOIM0dMG0C22VkzO+cYY NJ4A== X-Gm-Message-State: APjAAAUcARjcFRNBP17g6GVZSUMWNl7+Vq2skd/XbHPP1susqkVXincb ZOdPHZiJdcENC7W+8lu5//tb4mlB0Gjoze9ubq0j8trt5jd57Q+DG92pwOAbsWSsuuOv+uVyOgg M3e5T8xPhTMqk X-Received: by 2002:a1c:6707:: with SMTP id b7mr28806157wmc.54.1575353141380; Mon, 02 Dec 2019 22:05:41 -0800 (PST) X-Google-Smtp-Source: APXvYqynBA4BKlHbizkr07q/TJ9zRcFl9uM4rbB1rmsHfs6GRcs9s8m3GQRpyZYLhRDClmm64FjAhQ== X-Received: by 2002:a1c:6707:: with SMTP id b7mr28806135wmc.54.1575353141122; Mon, 02 Dec 2019 22:05:41 -0800 (PST) Received: from [192.168.1.35] (182.red-88-21-103.staticip.rima-tde.net. [88.21.103.182]) by smtp.gmail.com with ESMTPSA id n188sm1991006wme.14.2019.12.02.22.05.39 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 02 Dec 2019 22:05:40 -0800 (PST) Subject: Re: [PATCH v2 0/4] Expose GT CNTFRQ as a CPU property to support AST2600 To: Andrew Jeffery , qemu-arm@nongnu.org Cc: qemu-devel@nongnu.org, peter.maydell@linaro.org, clg@kaod.org, joel@jms.id.au References: <20191203041440.6275-1-andrew@aj.id.au> From: =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= Message-ID: <6540201e-b8dc-753b-cdaf-5d7da8716714@redhat.com> Date: Tue, 3 Dec 2019 07:05:38 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.2.2 MIME-Version: 1.0 In-Reply-To: <20191203041440.6275-1-andrew@aj.id.au> Content-Language: en-US X-MC-Unique: XR4lizlWNgS93tHlJsWgRA-1 X-Mimecast-Spam-Score: 0 Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 7bit X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 207.211.31.81 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 03 Dec 2019 06:05:48 -0000 On 12/3/19 5:14 AM, Andrew Jeffery wrote: > Hello, > > This is a v2 of the belated follow-up from a few of my earlier attempts to fix > up the ARM generic timer for correct behaviour on the ASPEED AST2600 SoC. The > AST2600 clocks the generic timer at the rate of HPLL, which is configured to > 1125MHz. This is significantly quicker than the currently hard-coded generic > timer rate of 62.5MHz and so we see "sticky" behaviour in the guest. Glad you fixed this! I hit the same problem with the Raspi4. From MAILER-DAEMON Tue Dec 03 01:09:58 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1ic1Nm-0004qo-PI for mharc-qemu-arm@gnu.org; Tue, 03 Dec 2019 01:09:58 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:54586) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ic1Nk-0004mI-Lk for qemu-arm@nongnu.org; Tue, 03 Dec 2019 01:09:57 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ic1Nh-00054k-Rh for qemu-arm@nongnu.org; Tue, 03 Dec 2019 01:09:55 -0500 Received: from us-smtp-2.mimecast.com ([205.139.110.61]:30331 helo=us-smtp-delivery-1.mimecast.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1ic1Nh-000520-N5 for qemu-arm@nongnu.org; Tue, 03 Dec 2019 01:09:53 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1575353392; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=3CgCdBNIjws7notuP2bcv87jEX3tF15nyKZxcylDcoM=; b=JpAOYG4W4LPY/KeiWgnKeuLCghGOAdGnsfZhUD3jWQPkFtMBRlUqr5Sl8t1XmWGcyQAQBQ yUjbI2GhIdd3YTEdSoj342hZkvEm2qBx2E2hxanuk6Afj1hkv2KKFzxquyiWCr/snnxZyY pUGOGyvb2M/Gv9YxuMVn4F4KjOklhMA= Received: from mail-wr1-f71.google.com (mail-wr1-f71.google.com [209.85.221.71]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-342-BiY9U2P8PEOaUcnY3K_kCQ-1; Tue, 03 Dec 2019 01:09:51 -0500 Received: by mail-wr1-f71.google.com with SMTP id c6so1192099wrm.18 for ; Mon, 02 Dec 2019 22:09:51 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:subject:to:cc:references:from:message-id:date :user-agent:mime-version:in-reply-to:content-language :content-transfer-encoding; bh=3CgCdBNIjws7notuP2bcv87jEX3tF15nyKZxcylDcoM=; b=jniWgVLSEGY/3F4Sbp8m2oUjCrBR0lpPoa5hiqTQp7uqJLge0At0X/R60lIIfN0DA7 rn0vr2auu+aJSPU5DulVcQWEfhX1jqYzqg91hOJsZDkYZk+GR1vjZLd4jVwy2MLVQpAg SIqY1An2rlKdadm729U7nYlj1GLpybKVlrXj7g54t3e5l2wX//fJ6Io4V1EEpzaNrqe1 7ZiqR7XRMv/KZviNRki6jlDnOGAsLI5eNVSrKH43saR54baWO6+Z+Qop4EUW9l9P5Gh9 dWxm4ktxXeMYvBGpNXlfp3pw38tkHRemwZ8SLvsyJMzZ3ghzodOL+oDnoZGE2GCHnKQD Vlmg== X-Gm-Message-State: APjAAAWZVzBZjpv71CsiXJt08+wllea1x+omZNfxjbwDVeKDmNUZxClO 7ffu71tRLGcyBQNl2gJmO0SLatlJPWwOcDek/43tjLvnsvJo3soJkik7kvH129WiU+dBK0EVLtn TKYvPcL6i35+q X-Received: by 2002:adf:ebc6:: with SMTP id v6mr3046712wrn.75.1575353390138; Mon, 02 Dec 2019 22:09:50 -0800 (PST) X-Google-Smtp-Source: APXvYqwLg6SHSqjCa/n2eklIcf/6sM1Q3pGXYQ4XZht81Be9rgGuJMndJMA3R7AxQ00EtgFXSQ4Eiw== X-Received: by 2002:adf:ebc6:: with SMTP id v6mr3046648wrn.75.1575353389275; Mon, 02 Dec 2019 22:09:49 -0800 (PST) Received: from [192.168.1.35] (182.red-88-21-103.staticip.rima-tde.net. [88.21.103.182]) by smtp.gmail.com with ESMTPSA id o7sm1796086wmc.41.2019.12.02.22.09.47 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 02 Dec 2019 22:09:48 -0800 (PST) Subject: Re: [PATCH v2 2/4] target/arm: Abstract the generic timer frequency To: Andrew Jeffery , qemu-arm@nongnu.org Cc: qemu-devel@nongnu.org, peter.maydell@linaro.org, Richard Henderson , clg@kaod.org, joel@jms.id.au References: <20191203041440.6275-1-andrew@aj.id.au> <20191203041440.6275-3-andrew@aj.id.au> From: =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= Message-ID: <283c152b-b1c7-551e-bec0-c087b14de996@redhat.com> Date: Tue, 3 Dec 2019 07:09:47 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.2.2 MIME-Version: 1.0 In-Reply-To: <20191203041440.6275-3-andrew@aj.id.au> Content-Language: en-US X-MC-Unique: BiY9U2P8PEOaUcnY3K_kCQ-1 X-Mimecast-Spam-Score: 0 Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 7bit X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 205.139.110.61 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 03 Dec 2019 06:09:58 -0000 On 12/3/19 5:14 AM, Andrew Jeffery wrote: > Prepare for SoCs such as the ASPEED AST2600 whose firmware configures > CNTFRQ to values significantly larger than the static 62.5MHz value > currently derived from GTIMER_SCALE. As the OS potentially derives its > timer periods from the CNTFRQ value the lack of support for running > QEMUTimers at the appropriate rate leads to sticky behaviour in the > guest. > > Substitute the GTIMER_SCALE constant with use of a helper to derive the > period from gt_cntfrq stored in struct ARMCPU. Initially set gt_cntfrq > to the frequency associated with GTIMER_SCALE so current behaviour is > maintained. > > Signed-off-by: Andrew Jeffery > Reviewed-by: Richard Henderson > --- > target/arm/cpu.c | 2 ++ > target/arm/cpu.h | 10 ++++++++++ > target/arm/helper.c | 10 +++++++--- > 3 files changed, 19 insertions(+), 3 deletions(-) > > diff --git a/target/arm/cpu.c b/target/arm/cpu.c > index 7a4ac9339bf9..5698a74061bb 100644 > --- a/target/arm/cpu.c > +++ b/target/arm/cpu.c > @@ -974,6 +974,8 @@ static void arm_cpu_initfn(Object *obj) > if (tcg_enabled()) { > cpu->psci_version = 2; /* TCG implements PSCI 0.2 */ > } > + > + cpu->gt_cntfrq = NANOSECONDS_PER_SECOND / GTIMER_SCALE; > } > > static Property arm_cpu_reset_cbar_property = > diff --git a/target/arm/cpu.h b/target/arm/cpu.h > index 83a809d4bac4..666c03871fdf 100644 > --- a/target/arm/cpu.h > +++ b/target/arm/cpu.h > @@ -932,8 +932,18 @@ struct ARMCPU { > */ > DECLARE_BITMAP(sve_vq_map, ARM_MAX_VQ); > DECLARE_BITMAP(sve_vq_init, ARM_MAX_VQ); > + > + /* Generic timer counter frequency, in Hz */ > + uint64_t gt_cntfrq; You can also explicit the unit by calling it 'gt_cntfrq_hz'. > }; > > +static inline unsigned int gt_cntfrq_period_ns(ARMCPU *cpu) > +{ > + /* XXX: Could include qemu/timer.h to get NANOSECONDS_PER_SECOND? */ Why inline this call? I doubt there is a significant performance gain. > + const unsigned int ns_per_s = 1000 * 1000 * 1000; > + return ns_per_s > cpu->gt_cntfrq ? ns_per_s / cpu->gt_cntfrq : 1; > +} > + > void arm_cpu_post_init(Object *obj); > > uint64_t arm_cpu_mp_affinity(int idx, uint8_t clustersz); > diff --git a/target/arm/helper.c b/target/arm/helper.c > index 65c4441a3896..2622a9a8d02f 100644 > --- a/target/arm/helper.c > +++ b/target/arm/helper.c > @@ -2409,7 +2409,9 @@ static CPAccessResult gt_stimer_access(CPUARMState *env, > > static uint64_t gt_get_countervalue(CPUARMState *env) > { > - return qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) / GTIMER_SCALE; > + ARMCPU *cpu = env_archcpu(env); > + > + return qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) / gt_cntfrq_period_ns(cpu); > } > > static void gt_recalc_timer(ARMCPU *cpu, int timeridx) > @@ -2445,7 +2447,7 @@ static void gt_recalc_timer(ARMCPU *cpu, int timeridx) > * set the timer for as far in the future as possible. When the > * timer expires we will reset the timer for any remaining period. > */ > - if (nexttick > INT64_MAX / GTIMER_SCALE) { > + if (nexttick > INT64_MAX / gt_cntfrq_period_ns(cpu)) { > timer_mod_ns(cpu->gt_timer[timeridx], INT64_MAX); > } else { > timer_mod(cpu->gt_timer[timeridx], nexttick); > @@ -2874,11 +2876,13 @@ static const ARMCPRegInfo generic_timer_cp_reginfo[] = { > > static uint64_t gt_virt_cnt_read(CPUARMState *env, const ARMCPRegInfo *ri) > { > + ARMCPU *cpu = env_archcpu(env); > + > /* Currently we have no support for QEMUTimer in linux-user so we > * can't call gt_get_countervalue(env), instead we directly > * call the lower level functions. > */ > - return cpu_get_clock() / GTIMER_SCALE; > + return cpu_get_clock() / gt_cntfrq_period_ns(cpu); > } > > static const ARMCPRegInfo generic_timer_cp_reginfo[] = { > From MAILER-DAEMON Tue Dec 03 01:20:00 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1ic1XT-0000pZ-Ud for mharc-qemu-arm@gnu.org; Tue, 03 Dec 2019 01:19:59 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:38810) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ic1XR-0000kI-Mo for qemu-arm@nongnu.org; Tue, 03 Dec 2019 01:19:59 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ic1XN-0006fV-23 for qemu-arm@nongnu.org; Tue, 03 Dec 2019 01:19:54 -0500 Received: from us-smtp-1.mimecast.com ([207.211.31.81]:41525 helo=us-smtp-delivery-1.mimecast.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1ic1XL-0006eP-8Q for qemu-arm@nongnu.org; Tue, 03 Dec 2019 01:19:51 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1575353990; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=NIggsHV7RwzfRpHde3nsZOyP42nBpUZTWDoAvsx3sFU=; b=ebColzZeyGHO6Ovs/VD3bQpQFLE4OlUQpseY7AD4QmqlFbfWFIhZe8Te7skJLoDGT69bRO xPJJzz2UwDwUeFAzGB9rXvx5yRlVTQIWpL5KV9rpRLo8A3sr1nt1O0L9Elw//KNiJtZKhc k+2W4Er1JCmNy5vBG5zn0DUkbN5Ul7g= Received: from mail-wr1-f70.google.com (mail-wr1-f70.google.com [209.85.221.70]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-65-2TlDFHPVPlG5Ch19TB-7Pw-1; Tue, 03 Dec 2019 01:19:49 -0500 Received: by mail-wr1-f70.google.com with SMTP id h30so1231292wrh.5 for ; Mon, 02 Dec 2019 22:19:48 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:subject:to:cc:references:from:message-id:date :user-agent:mime-version:in-reply-to:content-language :content-transfer-encoding; bh=cQ6SeHgzlGCjdsiT8Qv10jhbeiLaVPvQtaufLIrxZ5A=; b=UAIWk1VMOuOY9UBbg7qWx31KzaHdbkxtFgio3/cY5U1aX0hzxU5FXfCTryaShzBJZd GObnWcUl9yxhyBBMwbNC6i5jbC6tzcZmBKRUiqbxb64H5pVLvyf9b7mlAnRAOGsX1Cuj UWzoiFvJ8ORubNGF6s5kMOomPTge1gt8Z62FfXuEm9fZWjJiDrUOODUtsyRJEKbcrjMN I3l1Jnsyd9wSPjEoH2gBd4JFHCP0OljV5yexfPJcoRB3RBmTymaJH3sfYRLwXAZuRCzl +dytuYlp8zFAjAM6ZlTbEdOh+ctFwS9cRLM9kywkQ3IMmL8k6158NCFAX1XyZgYLRymp dnRQ== X-Gm-Message-State: APjAAAXBMPes1qS4VqkzmWXwwJekTIeVicDYVxDl/Ec6a5rR/5yVcz9m CGjE7Wzej4rMhjivMywvqxb4ve4WaK3C7mR6v9hrA8pt+yqaxRhtS0ArEVU7QzVu2dTj9SV33rC nZKGkCXwFHlbE X-Received: by 2002:a1c:6207:: with SMTP id w7mr25888569wmb.16.1575353987770; Mon, 02 Dec 2019 22:19:47 -0800 (PST) X-Google-Smtp-Source: APXvYqxunwusEg1LgtmAipcMpNQ2d1XNghTg9Z5lGsj2d+FHSaTSCAzrVy7SiHD3HzU6AQYSMnuK2w== X-Received: by 2002:a1c:6207:: with SMTP id w7mr25888551wmb.16.1575353987459; Mon, 02 Dec 2019 22:19:47 -0800 (PST) Received: from [192.168.1.35] (182.red-88-21-103.staticip.rima-tde.net. [88.21.103.182]) by smtp.gmail.com with ESMTPSA id e18sm2114137wrr.95.2019.12.02.22.19.46 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 02 Dec 2019 22:19:46 -0800 (PST) Subject: Re: [PATCH v2 3/4] target/arm: Prepare generic timer for per-platform CNTFRQ To: Andrew Jeffery , qemu-arm@nongnu.org Cc: qemu-devel@nongnu.org, peter.maydell@linaro.org, Richard Henderson , clg@kaod.org, joel@jms.id.au References: <20191203041440.6275-1-andrew@aj.id.au> <20191203041440.6275-4-andrew@aj.id.au> From: =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= Message-ID: Date: Tue, 3 Dec 2019 07:19:45 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.2.2 MIME-Version: 1.0 In-Reply-To: <20191203041440.6275-4-andrew@aj.id.au> Content-Language: en-US X-MC-Unique: 2TlDFHPVPlG5Ch19TB-7Pw-1 X-Mimecast-Spam-Score: 0 Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 207.211.31.81 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 03 Dec 2019 06:19:59 -0000 On 12/3/19 5:14 AM, Andrew Jeffery wrote: > The ASPEED AST2600 clocks the generic timer at the rate of HPLL. On > recent firmwares this is at 1125MHz, which is considerably quicker than > the assumed 62.5MHz of the current generic timer implementation. The > delta between the value as read from CNTFRQ and the true rate of the > underlying QEMUTimer leads to sticky behaviour in AST2600 guests. >=20 > Add a feature-gated property exposing CNTFRQ for ARM CPUs providing the > generic timer. This allows platforms to configure CNTFRQ (and the > associated QEMUTimer) to the appropriate frequency prior to starting the > guest. >=20 > As the platform can now determine the rate of CNTFRQ we're exposed to > limitations of QEMUTimer that didn't previously materialise: In the > course of emulation we need to arbitrarily and accurately convert > between guest ticks and time, but we're constrained by QEMUTimer's use > of an integer scaling factor. The effect is QEMUTimer cannot exactly > capture the period of frequencies that do not cleanly divide > NANOSECONDS_PER_SECOND for scaling ticks to time. As such, provide an > equally inaccurate scaling factor for scaling time to ticks so at least > a self-consistent inverse relationship holds. >=20 > Signed-off-by: Andrew Jeffery > Reviewed-by: Richard Henderson > --- > target/arm/cpu.c | 43 +++++++++++++++++++++++++++++++++---------- > target/arm/cpu.h | 18 ++++++++++++++++++ > target/arm/helper.c | 9 ++++++++- > 3 files changed, 59 insertions(+), 11 deletions(-) >=20 > diff --git a/target/arm/cpu.c b/target/arm/cpu.c > index 5698a74061bb..f186019a77fd 100644 > --- a/target/arm/cpu.c > +++ b/target/arm/cpu.c > @@ -974,10 +974,12 @@ static void arm_cpu_initfn(Object *obj) > if (tcg_enabled()) { > cpu->psci_version =3D 2; /* TCG implements PSCI 0.2 */ > } > - > - cpu->gt_cntfrq =3D NANOSECONDS_PER_SECOND / GTIMER_SCALE; > } > =20 > +static Property arm_cpu_gt_cntfrq_property =3D > + DEFINE_PROP_UINT64("cntfrq", ARMCPU, gt_cntfrq, > + NANOSECONDS_PER_SECOND / GTIMER_SCALE); > + > static Property arm_cpu_reset_cbar_property =3D > DEFINE_PROP_UINT64("reset-cbar", ARMCPU, reset_cbar, 0); > =20 > @@ -1174,6 +1176,11 @@ void arm_cpu_post_init(Object *obj) > =20 > qdev_property_add_static(DEVICE(obj), &arm_cpu_cfgend_property, > &error_abort); > + > + if (arm_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER)) { > + qdev_property_add_static(DEVICE(cpu), &arm_cpu_gt_cntfrq_propert= y, > + &error_abort); > + } > } > =20 > static void arm_cpu_finalizefn(Object *obj) > @@ -1253,14 +1260,30 @@ static void arm_cpu_realizefn(DeviceState *dev, E= rror **errp) > } > } > =20 > - cpu->gt_timer[GTIMER_PHYS] =3D timer_new(QEMU_CLOCK_VIRTUAL, GTIMER_= SCALE, > - arm_gt_ptimer_cb, cpu); > - cpu->gt_timer[GTIMER_VIRT] =3D timer_new(QEMU_CLOCK_VIRTUAL, GTIMER_= SCALE, > - arm_gt_vtimer_cb, cpu); > - cpu->gt_timer[GTIMER_HYP] =3D timer_new(QEMU_CLOCK_VIRTUAL, GTIMER_S= CALE, > - arm_gt_htimer_cb, cpu); > - cpu->gt_timer[GTIMER_SEC] =3D timer_new(QEMU_CLOCK_VIRTUAL, GTIMER_S= CALE, > - arm_gt_stimer_cb, cpu); > + > + { > + uint64_t scale; Apparently you have to use this odd indent due to the '#ifndef=20 CONFIG_USER_ONLY'. Well, acceptable. > + > + if (arm_feature(env, ARM_FEATURE_GENERIC_TIMER)) { > + if (!cpu->gt_cntfrq) { > + error_setg(errp, "Invalid CNTFRQ: %"PRId64"Hz", > + cpu->gt_cntfrq); > + return; > + } > + scale =3D gt_cntfrq_period_ns(cpu); > + } else { > + scale =3D GTIMER_SCALE; > + } > + > + cpu->gt_timer[GTIMER_PHYS] =3D timer_new(QEMU_CLOCK_VIRTUAL, sca= le, > + arm_gt_ptimer_cb, cpu); > + cpu->gt_timer[GTIMER_VIRT] =3D timer_new(QEMU_CLOCK_VIRTUAL, sca= le, > + arm_gt_vtimer_cb, cpu); > + cpu->gt_timer[GTIMER_HYP] =3D timer_new(QEMU_CLOCK_VIRTUAL, scal= e, > + arm_gt_htimer_cb, cpu); > + cpu->gt_timer[GTIMER_SEC] =3D timer_new(QEMU_CLOCK_VIRTUAL, scal= e, > + arm_gt_stimer_cb, cpu); > + } > #endif > =20 > cpu_exec_realizefn(cs, &local_err); > diff --git a/target/arm/cpu.h b/target/arm/cpu.h > index 666c03871fdf..0bcd13dcac81 100644 > --- a/target/arm/cpu.h > +++ b/target/arm/cpu.h > @@ -939,6 +939,24 @@ struct ARMCPU { > =20 > static inline unsigned int gt_cntfrq_period_ns(ARMCPU *cpu) > { > + /* > + * The exact approach to calculating guest ticks is: > + * > + * muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), cpu->gt_cntfr= q, > + * NANOSECONDS_PER_SECOND); > + * > + * We don't do that. Rather we intentionally use integer division > + * truncation below and in the caller for the conversion of host mon= otonic > + * time to guest ticks to provide the exact inverse for the semantic= s of > + * the QEMUTimer scale factor. QEMUTimer's scale facter is an intege= r, so > + * it loses precision when representing frequencies where > + * `(NANOSECONDS_PER_SECOND % cpu->gt_cntfrq) > 0` holds. Failing to > + * provide an exact inverse leads to scheduling timers with negative > + * periods, which in turn leads to sticky behaviour in the guest. > + * > + * Finally, CNTFRQ is effectively capped at 1GHz to ensure our scale= factor > + * cannot become zero. > + */ This comment belong to the previous patch. I'd rather see this function=20 + big comment in target/arm/cpu.c. With comment moved (and if possible function uninlined): Reviewed-by: Philippe Mathieu-Daud=C3=A9 > /* XXX: Could include qemu/timer.h to get NANOSECONDS_PER_SECOND? *= / > const unsigned int ns_per_s =3D 1000 * 1000 * 1000; > return ns_per_s > cpu->gt_cntfrq ? ns_per_s / cpu->gt_cntfrq : 1; > diff --git a/target/arm/helper.c b/target/arm/helper.c > index 2622a9a8d02f..da960d17040b 100644 > --- a/target/arm/helper.c > +++ b/target/arm/helper.c > @@ -2683,6 +2683,13 @@ void arm_gt_stimer_cb(void *opaque) > gt_recalc_timer(cpu, GTIMER_SEC); > } > =20 > +static void arm_gt_cntfrq_reset(CPUARMState *env, const ARMCPRegInfo *op= aque) > +{ > + ARMCPU *cpu =3D env_archcpu(env); > + > + cpu->env.cp15.c14_cntfrq =3D cpu->gt_cntfrq; > +} > + > static const ARMCPRegInfo generic_timer_cp_reginfo[] =3D { > /* Note that CNTFRQ is purely reads-as-written for the benefit > * of software; writing it doesn't actually change the timer freque= ncy. > @@ -2697,7 +2704,7 @@ static const ARMCPRegInfo generic_timer_cp_reginfo[= ] =3D { > .opc0 =3D 3, .opc1 =3D 3, .crn =3D 14, .crm =3D 0, .opc2 =3D 0, > .access =3D PL1_RW | PL0_R, .accessfn =3D gt_cntfrq_access, > .fieldoffset =3D offsetof(CPUARMState, cp15.c14_cntfrq), > - .resetvalue =3D (1000 * 1000 * 1000) / GTIMER_SCALE, > + .resetfn =3D arm_gt_cntfrq_reset, > }, > /* overall control: mostly access permissions */ > { .name =3D "CNTKCTL", .state =3D ARM_CP_STATE_BOTH, >=20 From MAILER-DAEMON Tue Dec 03 01:20:29 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1ic1Xx-0001Dv-CD for mharc-qemu-arm@gnu.org; Tue, 03 Dec 2019 01:20:29 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:44984) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ic1Xv-0001AT-1N for qemu-arm@nongnu.org; Tue, 03 Dec 2019 01:20:28 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ic1Xq-0007r6-TG for qemu-arm@nongnu.org; Tue, 03 Dec 2019 01:20:23 -0500 Received: from us-smtp-delivery-1.mimecast.com ([207.211.31.120]:28567 helo=us-smtp-1.mimecast.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1ic1Xq-0007pX-Oc for qemu-arm@nongnu.org; Tue, 03 Dec 2019 01:20:22 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1575354022; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=IowVLIFpCNfUQQivs6ggVTO0eknpK2SZq4cU1OclQ1k=; b=bJhIdK7bJutgMe4hB5ZPefgcvc/h4p3SxdIC3g/3LfgcsWhHqORLfIvaZ8q0k+oVwycs79 S8659XHSpA7LhAK4gtSFLzGvjge2FxNczAhVyBhegZBzHpfzqIwPOTxu0XB1OuK23FHjn/ fdoM73+v4x74yMbOqBBQNhrfx9o1MGk= Received: from mail-wr1-f71.google.com (mail-wr1-f71.google.com [209.85.221.71]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-357-H_EgDfNpOBOuuu40N5RzJg-1; Tue, 03 Dec 2019 01:20:20 -0500 Received: by mail-wr1-f71.google.com with SMTP id z15so1245418wrw.0 for ; Mon, 02 Dec 2019 22:20:20 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:subject:to:cc:references:from:message-id:date :user-agent:mime-version:in-reply-to:content-language :content-transfer-encoding; bh=jWwm6mWogocAZy961+vligZwjtpQocl6XWYfy+GpYlc=; b=TEUDcyfLfWJZbRAueEIpZX23j9E8ujZ8qheazO1uU83tqKGmwLjUsalVBVeihmaBKE 5zT+OwbbLEeDizhfKzGVF0d3evJ6PCiKK+EMygt0iLFXRpqHH0Do7OpxeLrnFKpFgBkV HXJKnPqc0RfJ2OtM2EQFuIebhUZjMCSYiQiGtsd+7Wbt2RAedl+HdLMVrA/u/WUGsdvn 8ZId9kDVzlid0spTgDgi1iC1+74IvqOTW8GlTn7fw6N8aIA9NNLoJX+rW0p/02GaCw5r XjqFmY6MNmuLqv44P/uZ5WoydHx+iRhj8ICTuxuD/4zqAHpoNojGd2JfmfJ1v0eWA5NT yeRQ== X-Gm-Message-State: APjAAAVhbx4FLmvSCLWBJaQ82qO3BejcEYJr1qlvnQlHQg00uL9aw3CA KztlkjvI1Pfc4eQw+/ZhBG6RPgELHrW80H1lAbZQAr65Qm3McYpy1lrDniE+FluumAqMrKWG5b4 HBJ1Q/x97yOiE X-Received: by 2002:a1c:ed0e:: with SMTP id l14mr30580687wmh.74.1575354017939; Mon, 02 Dec 2019 22:20:17 -0800 (PST) X-Google-Smtp-Source: APXvYqwN1jz6yqI+WQVL3MT0+k3G6FtfSDcpVXQfPQzBPl0jYYLp6j276JLlUVaz7J+rocY9z3GN1A== X-Received: by 2002:a1c:ed0e:: with SMTP id l14mr30580675wmh.74.1575354017742; Mon, 02 Dec 2019 22:20:17 -0800 (PST) Received: from [192.168.1.35] (182.red-88-21-103.staticip.rima-tde.net. [88.21.103.182]) by smtp.gmail.com with ESMTPSA id x7sm2157117wrq.41.2019.12.02.22.20.16 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 02 Dec 2019 22:20:17 -0800 (PST) Subject: Re: [PATCH v2 4/4] ast2600: Configure CNTFRQ at 1125MHz To: Andrew Jeffery , qemu-arm@nongnu.org Cc: qemu-devel@nongnu.org, peter.maydell@linaro.org, Richard Henderson , clg@kaod.org, joel@jms.id.au References: <20191203041440.6275-1-andrew@aj.id.au> <20191203041440.6275-5-andrew@aj.id.au> From: =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= Message-ID: Date: Tue, 3 Dec 2019 07:20:16 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.2.2 MIME-Version: 1.0 In-Reply-To: <20191203041440.6275-5-andrew@aj.id.au> Content-Language: en-US X-MC-Unique: H_EgDfNpOBOuuu40N5RzJg-1 X-Mimecast-Spam-Score: 0 Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 207.211.31.120 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 03 Dec 2019 06:20:28 -0000 On 12/3/19 5:14 AM, Andrew Jeffery wrote: > This matches the configuration set by u-boot on the AST2600. >=20 > Signed-off-by: Andrew Jeffery > Reviewed-by: Richard Henderson > Reviewed-by: C=C3=A9dric Le Goater > --- > hw/arm/aspeed_ast2600.c | 3 +++ > 1 file changed, 3 insertions(+) >=20 > diff --git a/hw/arm/aspeed_ast2600.c b/hw/arm/aspeed_ast2600.c > index 931887ac681f..5aecc3b3caec 100644 > --- a/hw/arm/aspeed_ast2600.c > +++ b/hw/arm/aspeed_ast2600.c > @@ -259,6 +259,9 @@ static void aspeed_soc_ast2600_realize(DeviceState *d= ev, Error **errp) > object_property_set_int(OBJECT(&s->cpu[i]), aspeed_calc_affinit= y(i), > "mp-affinity", &error_abort); > =20 > + object_property_set_int(OBJECT(&s->cpu[i]), 1125000000, "cntfrq"= , > + &error_abort); > + > /* > * TODO: the secondary CPUs are started and a boot helper > * is needed when using -kernel >=20 Reviewed-by: Philippe Mathieu-Daud=C3=A9 From MAILER-DAEMON Tue Dec 03 03:47:58 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1ic3qg-0000X8-7j for mharc-qemu-arm@gnu.org; Tue, 03 Dec 2019 03:47:58 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:43189) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ic3qc-0000U0-QV for qemu-arm@nongnu.org; Tue, 03 Dec 2019 03:47:56 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ic3qW-000697-6Q for qemu-arm@nongnu.org; Tue, 03 Dec 2019 03:47:50 -0500 Received: from us-smtp-delivery-1.mimecast.com ([207.211.31.120]:50896 helo=us-smtp-1.mimecast.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1ic3qV-00064D-VH for qemu-arm@nongnu.org; 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[88.21.103.182]) by smtp.gmail.com with ESMTPSA id c72sm2285383wmd.11.2019.12.03.00.47.40 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 03 Dec 2019 00:47:40 -0800 (PST) Subject: Re: [PATCH 00/10] Add Allwinner H3 SoC and Orange Pi PC Machine To: Niek Linnenbank , qemu-devel@nongnu.org Cc: b.galvani@gmail.com, peter.maydell@linaro.org, qemu-arm@nongnu.org, Richard Henderson References: <20191202210947.3603-1-nieklinnenbank@gmail.com> From: =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= Message-ID: Date: Tue, 3 Dec 2019 09:47:39 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.2.2 MIME-Version: 1.0 In-Reply-To: <20191202210947.3603-1-nieklinnenbank@gmail.com> Content-Language: en-US X-MC-Unique: 4M8lHoPjOwuaK4xvt1R9jQ-1 X-Mimecast-Spam-Score: 0 Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 207.211.31.120 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 03 Dec 2019 08:47:57 -0000 On 12/2/19 10:09 PM, Niek Linnenbank wrote: > Dear QEMU developers, > > Hereby I would like to contribute the following set of patches to QEMU > which add support for the Allwinner H3 System on Chip and the > Orange Pi PC machine. The following features and devices are supported: > > * SMP (Quad Core Cortex A7) > * Generic Interrupt Controller configuration > * SRAM mappings > * Timer device (re-used from Allwinner A10) > * UART > * SD/MMC storage controller > * EMAC ethernet connectivity > * USB 2.0 interfaces > * Clock Control Unit > * System Control module > * Security Identifier device Awesome! > Functionality related to graphical output such as HDMI, GPU, > Display Engine and audio are not included. Recently released > mainline Linux kernels (4.19 up to latest master) and mainline U-Boot > are known to work. The SD/MMC code is tested using bonnie++ and > various tools such as fsck, dd and fdisk. The EMAC is verified with iperf3 > using -netdev socket. > > To build a Linux mainline kernel that can be booted by the Orange Pi PC > machine, simply configure the kernel using the sunxi_defconfig configuration: > $ ARCH=arm CROSS_COMPILE=arm-linux-gnueabi- make mrproper > $ ARCH=arm CROSS_COMPILE=arm-linux-gnueabi- make sunxi_defconfig > > To be able to use USB storage, you need to manually enable the corresponding > configuration item. Start the kconfig configuration tool: > $ ARCH=arm CROSS_COMPILE=arm-linux-gnueabi- make menuconfig > > Navigate to the following item, enable it and save your configuration: > Device Drivers > USB support > USB Mass Storage support > > Build the Linux kernel with: > $ ARCH=arm CROSS_COMPILE=arm-linux-gnueabi- make -j5 > > To boot the newly build linux kernel in QEMU with the Orange Pi PC machine, use: > $ qemu-system-arm -M orangepi -m 512 -nic user -nographic \ > -kernel /path/to/linux/arch/arm/boot/zImage \ > -append 'console=ttyS0,115200' \ > -dtb /path/to/linux/arch/arm/boot/dts/sun8i-h3-orangepi-pc.dtb > > Note that this kernel does not have a root filesystem. You may provide it > with an official Orange Pi PC image [1] either as an SD card or as > USB mass storage. To boot using the Orange Pi PC Debian image on SD card, > simply add the -sd argument and provide the proper root= kernel parameter: > $ qemu-system-arm -M orangepi -m 512 -nic user -nographic \ > -kernel /path/to/linux/arch/arm/boot/zImage \ > -append 'console=ttyS0,115200 root=/dev/mmcblk0p2' \ > -dtb /path/to/linux/arch/arm/boot/dts/sun8i-h3-orangepi-pc.dtb \ > -sd OrangePi_pc_debian_stretch_server_linux5.3.5_v1.0.img > > Alternatively, you can also choose to build and boot a recent buildroot [2] > using the orangepi_pc_defconfig or Armbian image [3] for Orange Pi PC. Richard, trying the Armbian image from https://apt.armbian.com/pool/main/l/linux-4.20.7-sunxi/ I get: $ arm-softmmu/qemu-system-arm -M orangepi -m 512 -nic user \ -append 'console=ttyS0,115200' \ -kernel boot/vmlinuz-4.20.7-sunxi \ -dtb usr/lib/linux-image-dev-sunxi/sun8i-h3-orangepi-pc.dtb \ -serial stdio -d unimp Uncompressing Linux... done, booting the kernel. rtc: unimplemented device write (size 4, value 0x16aa0001, offset 0x0) rtc: unimplemented device read (size 4, offset 0x0) rtc: unimplemented device read (size 4, offset 0x0) rtc: unimplemented device read (size 4, offset 0x8) qemu-system-arm: target/arm/helper.c:11359: cpu_get_tb_cpu_state: Assertion `flags == rebuild_hflags_internal(env)' failed. Aborted (core dumped) (gdb) bt #0 0x00007f6c1fa2ce35 in raise () at /lib64/libc.so.6 #1 0x00007f6c1fa17895 in abort () at /lib64/libc.so.6 #2 0x00007f6c1fa17769 in _nl_load_domain.cold () at /lib64/libc.so.6 #3 0x00007f6c1fa25566 in annobin_assert.c_end () at /lib64/libc.so.6 #4 0x00005590657e2685 in cpu_get_tb_cpu_state (env=0x5590686899b0, pc=0x7f6c07ffa718, cs_base=0x7f6c07ffa714, pflags=0x7f6c07ffa71c) at target/arm/helper.c:11359 #5 0x000055906569f962 in tb_lookup__cpu_state (cpu=0x5590686808b0, pc=0x7f6c07ffa718, cs_base=0x7f6c07ffa714, flags=0x7f6c07ffa71c, cf_mask=524288) at include/exec/tb-lookup.h:28 #6 0x00005590656a084c in tb_find (cpu=0x5590686808b0, last_tb=0x0, tb_exit=0, cf_mask=524288) at accel/tcg/cpu-exec.c:403 #7 0x00005590656a114a in cpu_exec (cpu=0x5590686808b0) at accel/tcg/cpu-exec.c:730 #8 0x000055906565f6af in tcg_cpu_exec (cpu=0x5590686808b0) at cpus.c:1473 #9 0x000055906565ff05 in qemu_tcg_cpu_thread_fn (arg=0x5590686808b0) at cpus.c:1781 #10 0x0000559065d54aa6 in qemu_thread_start (args=0x5590687d8c20) at util/qemu-thread-posix.c:519 #11 0x00007f6c1fbc54c0 in start_thread () at /lib64/libpthread.so.0 #12 0x00007f6c1faf1553 in clone () at /lib64/libc.so.6 (gdb) p/x flags $1 = 0x33600000 (gdb) p/x *env $2 = {regs = {0x0 , 0x40102448}, xregs = {0x0 }, pc = 0x0, pstate = 0x0, aarch64 = 0x0, hflags = 0x33600000, uncached_cpsr = 0x1a, spsr = 0x0, banked_spsr = {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, banked_r13 = {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, banked_r14 = {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, usr_regs = {0x0, 0x0, 0x0, 0x0, 0x0}, fiq_regs = {0x0, 0x0, 0x0, 0x0, 0x0}, CF = 0x0, VF = 0x0, NF = 0x0, ZF = 0x0, QF = 0x0, GE = 0x0, thumb = 0x1, condexec_bits = 0x0, btype = 0x0, daif = 0x3c0, elr_el = {0x0, 0x0, 0x0, 0x0}, sp_el = {0x0, 0x0, 0x0, 0x0}, cp15 = {c0_cpuid = 0x410fc075, {{_unused_csselr0 = 0x0, csselr_ns = 0x0, _unused_csselr1 = 0x0, csselr_s = 0x0}, csselr_el = {0x0, 0x0, 0x0, 0x0}}, {{_unused_sctlr = 0x0, sctlr_ns = 0xc50078, hsctlr = 0x0, sctlr_s = 0xc50078}, sctlr_el = {0x0, 0xc50078, 0x0, 0xc50078}}, cpacr_el1 = 0x0, cptr_el = { 0x0, 0x0, 0x0, 0x0}, c1_xscaleauxcr = 0x0, sder = 0x0, nsacr = 0xc00, {{_unused_ttbr0_0 = 0x0, ttbr0_ns = 0x0, _unused_ttbr0_1 = 0x0, ttbr0_s = 0x0}, ttbr0_el = {0x0, 0x0, 0x0, 0x0}}, {{_unused_ttbr1_0 = 0x0, ttbr1_ns = 0x0, _unused_ttbr1_1 = 0x0, ttbr1_s = 0x0}, ttbr1_el = {0x0, 0x0, 0x0, 0x0}}, vttbr_el2 = 0x0, tcr_el = {{raw_tcr = 0x0, mask = 0x0, base_mask = 0x0}, {raw_tcr = 0x0, mask = 0x0, base_mask = 0xffffc000}, {raw_tcr = 0x0, mask = 0x0, base_mask = 0x0}, {raw_tcr = 0x0, mask = 0x0, base_mask = 0xffffc000}}, vtcr_el2 = {raw_tcr = 0x0, mask = 0x0, base_mask = 0x0}, c2_data = 0x0, c2_insn = 0x0, {{dacr_ns = 0x0, dacr_s = 0x0}, {dacr32_el2 = 0x0}}, pmsav5_data_ap = 0x0, pmsav5_insn_ap = 0x0, hcr_el2 = 0x0, scr_el3 = 0x101, {{ifsr_ns = 0x0, ifsr_s = 0x0}, {ifsr32_el2 = 0x0}}, {{_unused_dfsr = 0x0, dfsr_ns = 0x0, hsr = 0x0, dfsr_s = 0x0}, esr_el = {0x0, 0x0, 0x0, 0x0}}, c6_region = {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, {{_unused_far0 = 0x0, dfar_ns = 0x0, ifar_ns = 0x0, dfar_s = 0x0, ifar_s = 0x0, _unused_far3 = 0x0}, far_el = {0x0, 0x0, 0x0, 0x0}}, hpfar_el2 = 0x0, hstr_el2 = 0x0, {{ _unused_par_0 = 0x0, par_ns = 0x0, _unused_par_1 = 0x0, par_s = 0x0}, par_el = {0x0, 0x0, 0x0, 0x0}}, c9_insn = 0x0, c9_data = 0x0, c9_pmcr = 0x41002000, c9_pmcnten = 0x0, c9_pmovsr = 0x0, c9_pmuserenr = 0x0, c9_pmselr = 0x0, c9_pminten = 0x0, {{_unused_mair_0 = 0x0, mair0_ns = 0x0, mair1_ns = 0x0, _unused_mair_1 = 0x0, mair0_s = 0x0, mair1_s = 0x0}, mair_el = {0x0, 0x0, 0x0, 0x0}}, {{_unused_vbar = 0x0, vbar_ns = 0x0, hvbar = 0x0, vbar_s = 0x0}, vbar_el = {0x0, 0x0, 0x0, 0x0}}, mvbar = 0x0, {fcseidr_ns = 0x0, fcseidr_s = 0x0}, {{_unused_contextidr_0 = 0x0, contextidr_ns = 0x0, _unused_contextidr_1 = 0x0, contextidr_s = 0x0}, contextidr_el = {0x0, 0x0, 0x0, 0x0}}, {{ tpidrurw_ns = 0x0, tpidrprw_ns = 0x0, htpidr = 0x0, _tpidr_el3 = 0x0}, tpidr_el = {0x0, 0x0, 0x0, 0x0}}, tpidrurw_s = 0x0, tpidrprw_s = 0x0, tpidruro_s = 0x0, {tpidruro_ns = 0x0, tpidrro_el = {0x0}}, c14_cntfrq = 0x3b9aca0, c14_cntkctl = 0x0, cnthctl_el2 = 0x3, cntvoff_el2 = 0x0, c14_timer = {{cval = 0x0, ctl = 0x0}, {cval = 0x0, ctl = 0x0}, {cval = 0x0, ctl = 0x0}, {cval = 0x0, ctl = 0x0}}, c15_cpar = 0x0, c15_ticonfig = 0x0, c15_i_max = 0x0, c15_i_min = 0x0, c15_threadid = 0x0, c15_config_base_address = 0x0, c15_diagnostic = 0x0, c15_power_diagnostic = 0x0, c15_power_control = 0x0, dbgbvr = {0x0 }, dbgbcr = {0x0 }, dbgwvr = { 0x0 }, dbgwcr = {0x0 }, mdscr_el1 = 0x0, oslsr_el1 = 0xa, mdcr_el2 = 0x0, mdcr_el3 = 0x0, c15_ccnt = 0x0, c15_ccnt_delta = 0x0, c14_pmevcntr = {0x0 }, c14_pmevcntr_delta = { 0x0 }, c14_pmevtyper = {0x0 }, pmccfiltr_el0 = 0x0, vpidr_el2 = 0x410fc075, vmpidr_el2 = 0x80000001}, v7m = {other_sp = 0x0, other_ss_msp = 0x0, other_ss_psp = 0x0, vecbase = {0x0, 0x0}, basepri = {0x0, 0x0}, control = {0x0, 0x0}, ccr = {0x0, 0x0}, cfsr = {0x0, 0x0}, hfsr = 0x0, dfsr = 0x0, sfsr = 0x0, mmfar = {0x0, 0x0}, bfar = 0x0, sfar = 0x0, mpu_ctrl = {0x0, 0x0}, exception = 0x0, primask = {0x0, 0x0}, faultmask = {0x0, 0x0}, aircr = 0x0, secure = 0x0, csselr = {0x0, 0x0}, scr = {0x0, 0x0}, msplim = {0x0, 0x0}, psplim = {0x0, 0x0}, fpcar = {0x0, 0x0}, fpccr = {0x0, 0x0}, fpdscr = {0x0, 0x0}, cpacr = {0x0, 0x0}, nsacr = 0x0}, exception = {syndrome = 0x0, fsr = 0x0, vaddress = 0x0, target_el = 0x0}, serror = {pending = 0x0, has_esr = 0x0, esr = 0x0}, irq_line_state = 0x0, teecr = 0x0, teehbr = 0x0, vfp = {zregs = {{d = {0x0, 0x0}} }, qc = {0x0, 0x0, 0x0, 0x0}, vec_len = 0x0, vec_stride = 0x0, xregs = {0x41023075, 0x0, 0x0, 0x0, 0x0, 0x0, 0x11111111, 0x10110222, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, scratch = {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, fp_status = {float_detect_tininess = 0x1, float_rounding_mode = 0x0, float_exception_flags = 0x0, floatx80_rounding_precision = 0x0, flush_to_zero = 0x0, flush_inputs_to_zero = 0x0, default_nan_mode = 0x0, snan_bit_is_one = 0x0}, fp_status_f16 = {float_detect_tininess = 0x1, float_rounding_mode = 0x0, float_exception_flags = 0x0, floatx80_rounding_precision = 0x0, flush_to_zero = 0x0, flush_inputs_to_zero = 0x0, default_nan_mode = 0x0, snan_bit_is_one = 0x0}, standard_fp_status = {float_detect_tininess = 0x1, float_rounding_mode = 0x0, float_exception_flags = 0x0, floatx80_rounding_precision = 0x0, flush_to_zero = 0x1, flush_inputs_to_zero = 0x1, default_nan_mode = 0x1, snan_bit_is_one = 0x0}, zcr_el = {0x0, 0x0, 0x0, 0x0}}, exclusive_addr = 0xffffffffffffffff, exclusive_val = 0x0, exclusive_high = 0x0, iwmmxt = {regs = {0x0 }, val = 0x0, cregs = { 0x0 }}, cpu_breakpoint = {0x0 }, cpu_watchpoint = {0x0 }, end_reset_fields = {}, features = 0xfd38fbe6f3, pmsav7 = {drbar = 0x0, drsr = 0x0, dracr = 0x0, rnr = {0x0, 0x0}}, pmsav8 = {rbar = {0x0, 0x0}, rlar = {0x0, 0x0}, mair0 = {0x0, 0x0}, mair1 = {0x0, 0x0}}, sau = {rbar = 0x0, rlar = 0x0, rnr = 0x0, ctrl = 0x0}, nvic = 0x0, boot_info = 0x5622af3a17a0, gicv3state = 0x0} > [1] http://www.orangepi.org/downloadresources/ > [2] https://buildroot.org/download.html > [3] https://www.armbian.com/orange-pi-pc/ From MAILER-DAEMON Tue Dec 03 04:02:47 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1ic44z-0007VQ-TL for mharc-qemu-arm@gnu.org; Tue, 03 Dec 2019 04:02:47 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:43599) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ic44x-0007Te-2d for qemu-arm@nongnu.org; Tue, 03 Dec 2019 04:02:44 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ic44u-0007yb-N8 for qemu-arm@nongnu.org; Tue, 03 Dec 2019 04:02:41 -0500 Received: from us-smtp-1.mimecast.com ([205.139.110.61]:46292 helo=us-smtp-delivery-1.mimecast.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1ic44u-0007tO-F5 for qemu-arm@nongnu.org; Tue, 03 Dec 2019 04:02:40 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[88.21.103.182]) by smtp.gmail.com with ESMTPSA id i16sm2193619wmb.36.2019.12.03.01.02.34 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 03 Dec 2019 01:02:35 -0800 (PST) Subject: Re: [PATCH 00/10] Add Allwinner H3 SoC and Orange Pi PC Machine To: Niek Linnenbank , qemu-devel@nongnu.org Cc: b.galvani@gmail.com, peter.maydell@linaro.org, qemu-arm@nongnu.org, Richard Henderson , KONRAD Frederic , Alistair Francis , =?UTF-8?Q?Niccol=c3=b2_Izzo?= References: <20191202210947.3603-1-nieklinnenbank@gmail.com> From: =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= Message-ID: <1de57227-8124-4d11-d996-9faf67b3e4f3@redhat.com> Date: Tue, 3 Dec 2019 10:02:34 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.2.2 MIME-Version: 1.0 In-Reply-To: <20191202210947.3603-1-nieklinnenbank@gmail.com> Content-Language: en-US X-MC-Unique: MwXGp6JZPy2NHjyS4PBOPw-1 X-Mimecast-Spam-Score: 0 Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 205.139.110.61 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 03 Dec 2019 09:02:44 -0000 On 12/2/19 10:09 PM, Niek Linnenbank wrote: > Dear QEMU developers, > > Hereby I would like to contribute the following set of patches to QEMU > which add support for the Allwinner H3 System on Chip and the > Orange Pi PC machine. The following features and devices are supported: > > * SMP (Quad Core Cortex A7) > * Generic Interrupt Controller configuration > * SRAM mappings > * Timer device (re-used from Allwinner A10) > * UART > * SD/MMC storage controller > * EMAC ethernet connectivity > * USB 2.0 interfaces > * Clock Control Unit > * System Control module > * Security Identifier device > > Functionality related to graphical output such as HDMI, GPU, > Display Engine and audio are not included. I'd love to see the OpenRISC AR100 core instantiated in this SoC. Your contribution makes another good example of multi-arch/single-binary QEMU (here 4x ARM + 1x OpenRISC). From MAILER-DAEMON Tue Dec 03 04:18:21 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1ic4K3-00062X-Cj for mharc-qemu-arm@gnu.org; Tue, 03 Dec 2019 04:18:21 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:40210) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ic4Jw-00060S-D0 for qemu-arm@nongnu.org; Tue, 03 Dec 2019 04:18:14 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ic4Js-0002fS-F9 for qemu-arm@nongnu.org; Tue, 03 Dec 2019 04:18:10 -0500 Received: from us-smtp-delivery-1.mimecast.com ([205.139.110.120]:40782 helo=us-smtp-1.mimecast.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1ic4Js-0002dy-3H for qemu-arm@nongnu.org; Tue, 03 Dec 2019 04:18:08 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1575364685; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=6+wFDPvF/zPv5j2vgY/iKVd0+CqIFpL1Y/L/YNDsulc=; b=R5EgvIqrmwwoB8QxvXHNmpxPDkzNFLr0ZD5GO8kTxnf9oHGmbBsS45CxBqtPq/s5Ka8uor bamq8TCv4f8XZlmyeLQy0ruCJAkjKkpP4/7h7IjUn3wXFLtXeBN9dKZ3W0tOr9/SLF5Cfy o/g1L73+4H6GfTxO8W4q/oOksE7yVQU= Received: from mail-wr1-f72.google.com (mail-wr1-f72.google.com [209.85.221.72]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-234-MQdTmJutMVaV3U3XG64GVg-1; Tue, 03 Dec 2019 04:18:03 -0500 Received: by mail-wr1-f72.google.com with SMTP id u18so1444628wrn.11 for ; Tue, 03 Dec 2019 01:18:02 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:subject:to:cc:references:from:message-id:date :user-agent:mime-version:in-reply-to:content-language :content-transfer-encoding; bh=6+wFDPvF/zPv5j2vgY/iKVd0+CqIFpL1Y/L/YNDsulc=; b=ijIAcll69ndh+ggy4rl2V36KwO+0k0RS8oa3F+PbYQj4HaVUJrzPM1j5FpKfuHG9BU jrq3QL36CA70E2vhHq9bCOjW0xn0JoCdgRaV4e/SUuXq0z8Aaj2+GU0Ppv+QVo1yaNyR vyMgzBqsCJ2oCxTbCRN3VjqIQV+QKevgMDY98s9ktmMhZ3zt1TCr/Dpo1lamqoftYQzb tNFzZTQySM9K6VLcQ5/xWpO68mlmGR6mdCWV2+Rw5SonPwcAYpHR3dv7f4QMtnAqwMBl BW0f+ukYNbq/FHhBLelRMpjEJ9pr26J2+6/xqQ6gYhtYOhUQIir9VBT2J9CN307rJTmp 5JrA== X-Gm-Message-State: APjAAAUs9CpTdpSmnt1AVhTsphUuvSms594OTxkuX3GB8wtfPtYfA0dz 1agBowC4dz7a434NBrJfcZ2sIoSDym1H8GUtC4Uy5M/7XNHV7IJRVMB7zNa8lFyd7rrGMolqAXF JzcRsYrge67OG X-Received: by 2002:a1c:7d93:: with SMTP id y141mr23811192wmc.111.1575364681202; Tue, 03 Dec 2019 01:18:01 -0800 (PST) X-Google-Smtp-Source: APXvYqw1kY36edrrvAl6WCw2WZn8/1ez9u2EvRYGsaxgdH++oxKgAUAC17ujahiaODE0gTG5Bbx8KA== X-Received: by 2002:a1c:7d93:: with SMTP id y141mr23811171wmc.111.1575364680943; Tue, 03 Dec 2019 01:18:00 -0800 (PST) Received: from [192.168.1.35] (182.red-88-21-103.staticip.rima-tde.net. [88.21.103.182]) by smtp.gmail.com with ESMTPSA id w188sm2354874wmg.32.2019.12.03.01.17.59 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 03 Dec 2019 01:18:00 -0800 (PST) Subject: Re: [PATCH 02/10] hw: arm: add Xunlong Orange Pi PC machine To: Niek Linnenbank , qemu-devel@nongnu.org Cc: b.galvani@gmail.com, peter.maydell@linaro.org, qemu-arm@nongnu.org References: <20191202210947.3603-1-nieklinnenbank@gmail.com> <20191202210947.3603-3-nieklinnenbank@gmail.com> From: =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= Message-ID: Date: Tue, 3 Dec 2019 10:17:59 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.2.2 MIME-Version: 1.0 In-Reply-To: <20191202210947.3603-3-nieklinnenbank@gmail.com> Content-Language: en-US X-MC-Unique: MQdTmJutMVaV3U3XG64GVg-1 X-Mimecast-Spam-Score: 0 Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 205.139.110.120 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 03 Dec 2019 09:18:14 -0000 On 12/2/19 10:09 PM, Niek Linnenbank wrote: > The Xunlong Orange Pi PC is an Allwinner H3 System on Chip > based embedded computer with mainline support in both U-Boot > and Linux. The board comes with a Quad Core Cortex A7 @ 1.3GHz, > 512MB RAM, 100Mbit ethernet, USB, SD/MMC, USB, HDMI and > various other I/O. This commit add support for the Xunlong > Orange Pi PC machine. > > Signed-off-by: Niek Linnenbank > --- > MAINTAINERS | 1 + > hw/arm/Makefile.objs | 2 +- > hw/arm/orangepi.c | 90 ++++++++++++++++++++++++++++++++++++++++++++ > 3 files changed, 92 insertions(+), 1 deletion(-) > create mode 100644 hw/arm/orangepi.c > > diff --git a/MAINTAINERS b/MAINTAINERS > index 29c9936037..42c913d6cb 100644 > --- a/MAINTAINERS > +++ b/MAINTAINERS > @@ -485,6 +485,7 @@ L: qemu-arm@nongnu.org > S: Maintained > F: hw/*/allwinner-h3* > F: include/hw/*/allwinner-h3* > +F: hw/arm/orangepi.c > > ARM PrimeCell and CMSDK devices > M: Peter Maydell > diff --git a/hw/arm/Makefile.objs b/hw/arm/Makefile.objs > index 956e496052..8d5ea453d5 100644 > --- a/hw/arm/Makefile.objs > +++ b/hw/arm/Makefile.objs > @@ -34,7 +34,7 @@ obj-$(CONFIG_DIGIC) += digic.o > obj-$(CONFIG_OMAP) += omap1.o omap2.o > obj-$(CONFIG_STRONGARM) += strongarm.o > obj-$(CONFIG_ALLWINNER_A10) += allwinner-a10.o cubieboard.o > -obj-$(CONFIG_ALLWINNER_H3) += allwinner-h3.o > +obj-$(CONFIG_ALLWINNER_H3) += allwinner-h3.o orangepi.o > obj-$(CONFIG_RASPI) += bcm2835_peripherals.o bcm2836.o raspi.o > obj-$(CONFIG_STM32F205_SOC) += stm32f205_soc.o > obj-$(CONFIG_XLNX_ZYNQMP_ARM) += xlnx-zynqmp.o xlnx-zcu102.o > diff --git a/hw/arm/orangepi.c b/hw/arm/orangepi.c > new file mode 100644 > index 0000000000..5ef2735f81 > --- /dev/null > +++ b/hw/arm/orangepi.c > @@ -0,0 +1,90 @@ > +/* > + * Orange Pi emulation > + * > + * Copyright (C) 2019 Niek Linnenbank > + * > + * This program is free software: you can redistribute it and/or modify > + * it under the terms of the GNU General Public License as published by > + * the Free Software Foundation, either version 2 of the License, or > + * (at your option) any later version. > + * > + * This program is distributed in the hope that it will be useful, > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > + * GNU General Public License for more details. > + * > + * You should have received a copy of the GNU General Public License > + * along with this program. If not, see . > + */ > + > +#include "qemu/osdep.h" > +#include "exec/address-spaces.h" > +#include "qapi/error.h" > +#include "cpu.h" > +#include "hw/sysbus.h" > +#include "hw/boards.h" > +#include "hw/qdev-properties.h" > +#include "hw/arm/allwinner-h3.h" > + > +static struct arm_boot_info orangepi_binfo = { > + .loader_start = AW_H3_SDRAM_BASE, > + .board_id = -1, > +}; > + > +typedef struct OrangePiState { > + AwH3State *h3; > + MemoryRegion sdram; > +} OrangePiState; > + > +static void orangepi_init(MachineState *machine) > +{ > + OrangePiState *s = g_new(OrangePiState, 1); > + Error *err = NULL; > + Here I'd add: if (strcmp(machine->cpu_type, ARM_CPU_TYPE_NAME("cortex-a7")) != 0) { error_report("This board can only be used with cortex-a7 CPU"); exit(1); } > + s->h3 = AW_H3(object_new(TYPE_AW_H3)); > + > + /* Setup timer properties */ > + object_property_set_int(OBJECT(&s->h3->timer), 32768, "clk0-freq", &err); > + if (err != NULL) { > + error_reportf_err(err, "Couldn't set clk0 frequency: "); > + exit(1); > + } > + > + object_property_set_int(OBJECT(&s->h3->timer), 24000000, "clk1-freq", > + &err); > + if (err != NULL) { > + error_reportf_err(err, "Couldn't set clk1 frequency: "); > + exit(1); > + } > + > + /* Mark H3 object realized */ > + object_property_set_bool(OBJECT(s->h3), true, "realized", &err); I'm not sure if that's correct but I'd simply use &error_abort here. > + if (err != NULL) { > + error_reportf_err(err, "Couldn't realize Allwinner H3: "); > + exit(1); > + } > + > + /* RAM */ > + memory_region_allocate_system_memory(&s->sdram, NULL, "orangepi.ram", > + machine->ram_size); I'd only allow machine->ram_size == 1 * GiB here, since the onboard DRAM is not upgradable. > + memory_region_add_subregion(get_system_memory(), AW_H3_SDRAM_BASE, > + &s->sdram); > + > + /* Load target kernel */ > + orangepi_binfo.ram_size = machine->ram_size; > + orangepi_binfo.nb_cpus = AW_H3_NUM_CPUS; > + arm_load_kernel(ARM_CPU(first_cpu), machine, &orangepi_binfo); > +} > + > +static void orangepi_machine_init(MachineClass *mc) > +{ > + mc->desc = "Orange Pi PC"; > + mc->init = orangepi_init; > + mc->units_per_default_bus = 1; > + mc->min_cpus = AW_H3_NUM_CPUS; > + mc->max_cpus = AW_H3_NUM_CPUS; > + mc->default_cpus = AW_H3_NUM_CPUS; mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-a7"); > + mc->ignore_memory_transaction_failures = true; You should not use this flag in new design. See the documentation in include/hw/boards.h: * @ignore_memory_transaction_failures: * [...] New board models * should instead use "unimplemented-device" for all memory ranges where * the guest will attempt to probe for a device that QEMU doesn't * implement and a stub device is required. You already use the "unimplemented-device". > +} > + > +DEFINE_MACHINE("orangepi", orangepi_machine_init) Can you name it 'orangepi-pc'? So we can add other orangepi models. Thanks, Phil. From MAILER-DAEMON Tue Dec 03 04:33:47 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1ic4Yz-0006PD-SD for mharc-qemu-arm@gnu.org; Tue, 03 Dec 2019 04:33:47 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:56840) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ic4Yp-0006Na-KO for qemu-arm@nongnu.org; Tue, 03 Dec 2019 04:33:39 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ic4Yj-00017F-Vq for qemu-arm@nongnu.org; Tue, 03 Dec 2019 04:33:35 -0500 Received: from mel.act-europe.fr ([194.98.77.210]:33220 helo=smtp.eu.adacore.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1ic4Yi-0000yA-PN; Tue, 03 Dec 2019 04:33:29 -0500 Received: from localhost (localhost [127.0.0.1]) by filtered-smtp.eu.adacore.com (Postfix) with ESMTP id C39C78137E; Tue, 3 Dec 2019 10:33:20 +0100 (CET) X-Virus-Scanned: Debian amavisd-new at eu.adacore.com Received: from smtp.eu.adacore.com ([127.0.0.1]) by localhost (smtp.eu.adacore.com [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id 7HBRh53_tzvf; Tue, 3 Dec 2019 10:33:20 +0100 (CET) Received: from localhost.localdomain (lfbn-tou-1-352-33.w86-206.abo.wanadoo.fr [86.206.184.33]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.eu.adacore.com (Postfix) with ESMTPSA id 6D92D8137C; Tue, 3 Dec 2019 10:33:20 +0100 (CET) Subject: Re: [PATCH 10/10] arm: allwinner-h3: add EMAC ethernet device To: Niek Linnenbank , qemu-devel@nongnu.org Cc: b.galvani@gmail.com, peter.maydell@linaro.org, qemu-arm@nongnu.org References: <20191202210947.3603-1-nieklinnenbank@gmail.com> <20191202210947.3603-11-nieklinnenbank@gmail.com> From: KONRAD Frederic Message-ID: Date: Tue, 3 Dec 2019 10:33:18 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101 Thunderbird/60.9.1 MIME-Version: 1.0 In-Reply-To: <20191202210947.3603-11-nieklinnenbank@gmail.com> Content-Type: text/plain; charset=utf-8; format=flowed Content-Language: fr Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [fuzzy] X-Received-From: 194.98.77.210 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 03 Dec 2019 09:33:39 -0000 Le 12/2/19 =C3=A0 10:09 PM, Niek Linnenbank a =C3=A9crit=C2=A0: > The Allwinner H3 System on Chip includes an Ethernet MAC (EMAC) > which provides 10M/100M/1000M Ethernet connectivity. This commit > adds support for the Allwinner H3 EMAC, including emulation for > the following functionality: >=20 > * DMA transfers > * MII interface > * Transmit CRC calculation >=20 > Signed-off-by: Niek Linnenbank > --- > hw/arm/Kconfig | 1 + > hw/arm/allwinner-h3.c | 17 + > hw/arm/orangepi.c | 7 + > hw/net/Kconfig | 3 + > hw/net/Makefile.objs | 1 + > hw/net/allwinner-h3-emac.c | 786 ++++++++++++++++++++++++++++= + > hw/net/trace-events | 10 + > include/hw/arm/allwinner-h3.h | 2 + > include/hw/net/allwinner-h3-emac.h | 69 +++ > 9 files changed, 896 insertions(+) > create mode 100644 hw/net/allwinner-h3-emac.c > create mode 100644 include/hw/net/allwinner-h3-emac.h >=20 > diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig > index ebf8d2325f..551cff3442 100644 > --- a/hw/arm/Kconfig > +++ b/hw/arm/Kconfig > @@ -294,6 +294,7 @@ config ALLWINNER_A10 > config ALLWINNER_H3 > bool > select ALLWINNER_A10_PIT > + select ALLWINNER_H3_EMAC > select SERIAL > select ARM_TIMER > select ARM_GIC > diff --git a/hw/arm/allwinner-h3.c b/hw/arm/allwinner-h3.c > index c2972caf88..274b8548c0 100644 > --- a/hw/arm/allwinner-h3.c > +++ b/hw/arm/allwinner-h3.c > @@ -53,6 +53,9 @@ static void aw_h3_init(Object *obj) > =20 > sysbus_init_child_obj(obj, "mmc0", &s->mmc0, sizeof(s->mmc0), > TYPE_AW_H3_SDHOST); > + > + sysbus_init_child_obj(obj, "emac", &s->emac, sizeof(s->emac), > + TYPE_AW_H3_EMAC); > } > =20 > static void aw_h3_realize(DeviceState *dev, Error **errp) > @@ -237,6 +240,20 @@ static void aw_h3_realize(DeviceState *dev, Error = **errp) > return; > } > =20 > + /* EMAC */ > + if (nd_table[0].used) { > + qemu_check_nic_model(&nd_table[0], TYPE_AW_H3_EMAC); > + qdev_set_nic_properties(DEVICE(&s->emac), &nd_table[0]); > + } > + object_property_set_bool(OBJECT(&s->emac), true, "realized", &err)= ; > + if (err !=3D NULL) { > + error_propagate(errp, err); > + return; > + } > + sysbusdev =3D SYS_BUS_DEVICE(&s->emac); > + sysbus_mmio_map(sysbusdev, 0, AW_H3_EMAC_BASE); > + sysbus_connect_irq(sysbusdev, 0, s->irq[AW_H3_GIC_SPI_EMAC]); > + > /* Universal Serial Bus */ > sysbus_create_simple(TYPE_AW_H3_EHCI, AW_H3_EHCI0_BASE, > s->irq[AW_H3_GIC_SPI_EHCI0]); > diff --git a/hw/arm/orangepi.c b/hw/arm/orangepi.c > index dee3efaf08..8a61eb0e69 100644 > --- a/hw/arm/orangepi.c > +++ b/hw/arm/orangepi.c > @@ -61,6 +61,13 @@ static void orangepi_init(MachineState *machine) > exit(1); > } > =20 > + /* Setup EMAC properties */ > + object_property_set_int(OBJECT(&s->h3->emac), 1, "phy-addr", &err)= ; > + if (err !=3D NULL) { > + error_reportf_err(err, "Couldn't set phy address: "); > + exit(1); > + } > + > /* Mark H3 object realized */ > object_property_set_bool(OBJECT(s->h3), true, "realized", &err); > if (err !=3D NULL) { > diff --git a/hw/net/Kconfig b/hw/net/Kconfig > index 3856417d42..36d3923992 100644 > --- a/hw/net/Kconfig > +++ b/hw/net/Kconfig > @@ -74,6 +74,9 @@ config MIPSNET > config ALLWINNER_EMAC > bool > =20 > +config ALLWINNER_H3_EMAC > + bool > + > config IMX_FEC > bool > =20 > diff --git a/hw/net/Makefile.objs b/hw/net/Makefile.objs > index 7907d2c199..5548deb07a 100644 > --- a/hw/net/Makefile.objs > +++ b/hw/net/Makefile.objs > @@ -23,6 +23,7 @@ common-obj-$(CONFIG_XGMAC) +=3D xgmac.o > common-obj-$(CONFIG_MIPSNET) +=3D mipsnet.o > common-obj-$(CONFIG_XILINX_AXI) +=3D xilinx_axienet.o > common-obj-$(CONFIG_ALLWINNER_EMAC) +=3D allwinner_emac.o > +common-obj-$(CONFIG_ALLWINNER_H3_EMAC) +=3D allwinner-h3-emac.o > common-obj-$(CONFIG_IMX_FEC) +=3D imx_fec.o > =20 > common-obj-$(CONFIG_CADENCE) +=3D cadence_gem.o > diff --git a/hw/net/allwinner-h3-emac.c b/hw/net/allwinner-h3-emac.c > new file mode 100644 > index 0000000000..37f6f44406 > --- /dev/null > +++ b/hw/net/allwinner-h3-emac.c > @@ -0,0 +1,786 @@ > +/* > + * Allwinner H3 EMAC emulation > + * > + * Copyright (C) 2019 Niek Linnenbank > + * > + * This program is free software: you can redistribute it and/or modif= y > + * it under the terms of the GNU General Public License as published b= y > + * the Free Software Foundation, either version 2 of the License, or > + * (at your option) any later version. > + * > + * This program is distributed in the hope that it will be useful, > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > + * GNU General Public License for more details. > + * > + * You should have received a copy of the GNU General Public License > + * along with this program. If not, see . > + */ > + > +#include "qemu/osdep.h" > +#include "hw/sysbus.h" > +#include "migration/vmstate.h" > +#include "net/net.h" > +#include "hw/irq.h" > +#include "hw/qdev-properties.h" > +#include "qemu/log.h" > +#include "trace.h" > +#include "net/checksum.h" > +#include "qemu/module.h" > +#include "exec/cpu-common.h" > +#include "hw/net/allwinner-h3-emac.h" > + > +/* EMAC register offsets */ > +#define REG_BASIC_CTL_0 (0x0000) /* Basic Control 0 */ > +#define REG_BASIC_CTL_1 (0x0004) /* Basic Control 1 */ > +#define REG_INT_STA (0x0008) /* Interrupt Status */ > +#define REG_INT_EN (0x000C) /* Interrupt Enable */ > +#define REG_TX_CTL_0 (0x0010) /* Transmit Control 0 */ > +#define REG_TX_CTL_1 (0x0014) /* Transmit Control 1 */ > +#define REG_TX_FLOW_CTL (0x001C) /* Transmit Flow Control */ > +#define REG_TX_DMA_DESC_LIST (0x0020) /* Transmit Descriptor List Ad= dress */ > +#define REG_RX_CTL_0 (0x0024) /* Receive Control 0 */ > +#define REG_RX_CTL_1 (0x0028) /* Receive Control 1 */ > +#define REG_RX_DMA_DESC_LIST (0x0034) /* Receive Descriptor List Add= ress */ > +#define REG_FRM_FLT (0x0038) /* Receive Frame Filter */ > +#define REG_RX_HASH_0 (0x0040) /* Receive Hash Table 0 */ > +#define REG_RX_HASH_1 (0x0044) /* Receive Hash Table 1 */ > +#define REG_MII_CMD (0x0048) /* Management Interface Comman= d */ > +#define REG_MII_DATA (0x004C) /* Management Interface Data *= / > +#define REG_ADDR_HIGH (0x0050) /* MAC Address High */ > +#define REG_ADDR_LOW (0x0054) /* MAC Address Low */ > +#define REG_TX_DMA_STA (0x00B0) /* Transmit DMA Status */ > +#define REG_TX_CUR_DESC (0x00B4) /* Transmit Current Descriptor= */ > +#define REG_TX_CUR_BUF (0x00B8) /* Transmit Current Buffer */ > +#define REG_RX_DMA_STA (0x00C0) /* Receive DMA Status */ > +#define REG_RX_CUR_DESC (0x00C4) /* Receive Current Descriptor = */ > +#define REG_RX_CUR_BUF (0x00C8) /* Receive Current Buffer */ > +#define REG_RGMII_STA (0x00D0) /* RGMII Status */ > + > +/* EMAC register flags */ > +#define BASIC_CTL0_100Mbps (0b11 << 2) > +#define BASIC_CTL0_FD (1 << 0) > +#define BASIC_CTL1_SOFTRST (1 << 0) > + > +#define INT_STA_RGMII_LINK (1 << 16) > +#define INT_STA_RX_EARLY (1 << 13) > +#define INT_STA_RX_OVERFLOW (1 << 12) > +#define INT_STA_RX_TIMEOUT (1 << 11) > +#define INT_STA_RX_DMA_STOP (1 << 10) > +#define INT_STA_RX_BUF_UA (1 << 9) > +#define INT_STA_RX (1 << 8) > +#define INT_STA_TX_EARLY (1 << 5) > +#define INT_STA_TX_UNDERFLOW (1 << 4) > +#define INT_STA_TX_TIMEOUT (1 << 3) > +#define INT_STA_TX_BUF_UA (1 << 2) > +#define INT_STA_TX_DMA_STOP (1 << 1) > +#define INT_STA_TX (1 << 0) > + > +#define INT_EN_RX_EARLY (1 << 13) > +#define INT_EN_RX_OVERFLOW (1 << 12) > +#define INT_EN_RX_TIMEOUT (1 << 11) > +#define INT_EN_RX_DMA_STOP (1 << 10) > +#define INT_EN_RX_BUF_UA (1 << 9) > +#define INT_EN_RX (1 << 8) > +#define INT_EN_TX_EARLY (1 << 5) > +#define INT_EN_TX_UNDERFLOW (1 << 4) > +#define INT_EN_TX_TIMEOUT (1 << 3) > +#define INT_EN_TX_BUF_UA (1 << 2) > +#define INT_EN_TX_DMA_STOP (1 << 1) > +#define INT_EN_TX (1 << 0) > + > +#define TX_CTL0_TX_EN (1 << 31) > +#define TX_CTL1_TX_DMA_START (1 << 31) > +#define TX_CTL1_TX_DMA_EN (1 << 30) > +#define TX_CTL1_TX_FLUSH (1 << 0) > + > +#define RX_CTL0_RX_EN (1 << 31) > +#define RX_CTL0_STRIP_FCS (1 << 28) > +#define RX_CTL0_CRC_IPV4 (1 << 27) > + > +#define RX_CTL1_RX_DMA_START (1 << 31) > +#define RX_CTL1_RX_DMA_EN (1 << 30) > +#define RX_CTL1_RX_MD (1 << 1) > + > +#define RX_FRM_FLT_DIS_ADDR (1 << 31) > + > +#define MII_CMD_PHY_ADDR_SHIFT (12) > +#define MII_CMD_PHY_ADDR_MASK (0xf000) > +#define MII_CMD_PHY_REG_SHIFT (4) > +#define MII_CMD_PHY_REG_MASK (0xf0) > +#define MII_CMD_PHY_RW (1 << 1) > +#define MII_CMD_PHY_BUSY (1 << 0) > + > +#define TX_DMA_STA_STOP (0b000) > +#define TX_DMA_STA_RUN_FETCH (0b001) > +#define TX_DMA_STA_WAIT_STA (0b010) > + > +#define RX_DMA_STA_STOP (0b000) > +#define RX_DMA_STA_RUN_FETCH (0b001) > +#define RX_DMA_STA_WAIT_FRM (0b011) > + > +#define RGMII_LINK_UP (1 << 3) > +#define RGMII_FD (1 << 0) > + > +/* EMAC register reset values */ > +#define REG_BASIC_CTL_1_RST (0x08000000) > + > +/* EMAC constants */ > +#define AW_H3_EMAC_MIN_PKT_SZ (64) > + > +/* Transmit/receive frame descriptor */ > +typedef struct FrameDescriptor { > + uint32_t status; > + uint32_t status2; > + uint32_t addr; > + uint32_t next; > +} FrameDescriptor; > + > +/* Frame descriptor flags */ > +#define DESC_STATUS_CTL (1 << 31) > +#define DESC_STATUS2_BUF_SIZE_MASK (0x7ff) > + > +/* Transmit frame descriptor flags */ > +#define TX_DESC_STATUS_LENGTH_ERR (1 << 14) > +#define TX_DESC_STATUS2_FIRST_DESC (1 << 29) > +#define TX_DESC_STATUS2_LAST_DESC (1 << 30) > +#define TX_DESC_STATUS2_CHECKSUM_MASK (0x3 << 27) > + > +/* Receive frame descriptor flags */ > +#define RX_DESC_STATUS_FIRST_DESC (1 << 9) > +#define RX_DESC_STATUS_LAST_DESC (1 << 8) > +#define RX_DESC_STATUS_FRM_LEN_MASK (0x3fff0000) > +#define RX_DESC_STATUS_FRM_LEN_SHIFT (16) > +#define RX_DESC_STATUS_NO_BUF (1 << 14) > +#define RX_DESC_STATUS_HEADER_ERR (1 << 7) > +#define RX_DESC_STATUS_LENGTH_ERR (1 << 4) > +#define RX_DESC_STATUS_CRC_ERR (1 << 1) > +#define RX_DESC_STATUS_PAYLOAD_ERR (1 << 0) > +#define RX_DESC_STATUS2_RX_INT_CTL (1 << 31) > + > +/* MII register offsets */ > +#define MII_REG_CR (0x0) > +#define MII_REG_ST (0x1) > +#define MII_REG_ID_HIGH (0x2) > +#define MII_REG_ID_LOW (0x3) > + > +/* MII register flags */ > +#define MII_REG_CR_RESET (1 << 15) > +#define MII_REG_CR_POWERDOWN (1 << 11) > +#define MII_REG_CR_10Mbit (0) > +#define MII_REG_CR_100Mbit (1 << 13) > +#define MII_REG_CR_1000Mbit (1 << 6) > +#define MII_REG_CR_AUTO_NEG (1 << 12) > +#define MII_REG_CR_AUTO_NEG_RESTART (1 << 9) > +#define MII_REG_CR_FULLDUPLEX (1 << 8) > + > +#define MII_REG_ST_100BASE_T4 (1 << 15) > +#define MII_REG_ST_100BASE_X_FD (1 << 14) > +#define MII_REG_ST_100BASE_X_HD (1 << 13) > +#define MII_REG_ST_10_FD (1 << 12) > +#define MII_REG_ST_10_HD (1 << 11) > +#define MII_REG_ST_100BASE_T2_FD (1 << 10) > +#define MII_REG_ST_100BASE_T2_HD (1 << 9) > +#define MII_REG_ST_AUTONEG_COMPLETE (1 << 5) > +#define MII_REG_ST_AUTONEG_AVAIL (1 << 3) > +#define MII_REG_ST_LINK_UP (1 << 2) > + > +/* MII constants */ > +#define MII_PHY_ID_HIGH (0x0044) > +#define MII_PHY_ID_LOW (0x1400) I wonder if we can't share all those mii stuff accross the network adapte= rs instead of redoing the work everytime. I've some patches about it I may p= ost them sometimes. > + > +static void aw_h3_emac_mii_set_link(AwH3EmacState *s, bool link_active= ) > +{ > + if (link_active) { > + s->mii_st |=3D MII_REG_ST_LINK_UP; > + } else { > + s->mii_st &=3D ~MII_REG_ST_LINK_UP; > + } > +} > + > +static void aw_h3_emac_mii_reset(AwH3EmacState *s, bool link_active) > +{ > + s->mii_cr =3D MII_REG_CR_100Mbit | MII_REG_CR_AUTO_NEG | > + MII_REG_CR_FULLDUPLEX; > + s->mii_st =3D MII_REG_ST_100BASE_T4 | MII_REG_ST_100BASE_X_FD | > + MII_REG_ST_100BASE_X_HD | MII_REG_ST_10_FD | MII_REG_S= T_10_HD | > + MII_REG_ST_100BASE_T2_FD | MII_REG_ST_100BASE_T2_HD | > + MII_REG_ST_AUTONEG_COMPLETE | MII_REG_ST_AUTONEG_AVAIL= ; > + > + aw_h3_emac_mii_set_link(s, link_active); > +} > + > +static void aw_h3_emac_mii_cmd(AwH3EmacState *s) > +{ > + uint8_t addr, reg; > + > + addr =3D (s->mii_cmd & MII_CMD_PHY_ADDR_MASK) >> MII_CMD_PHY_ADDR_= SHIFT; > + reg =3D (s->mii_cmd & MII_CMD_PHY_REG_MASK) >> MII_CMD_PHY_REG_SHI= FT; > + > + if (addr !=3D s->mii_phy_addr) { > + return; > + } > + > + /* Read or write a PHY register? */ > + if (s->mii_cmd & MII_CMD_PHY_RW) { > + trace_aw_h3_emac_mii_write_reg(reg, s->mii_data); > + > + switch (reg) { > + case MII_REG_CR: > + if (s->mii_data & MII_REG_CR_RESET) { > + aw_h3_emac_mii_reset(s, s->mii_st & MII_REG_ST_LINK_UP= ); > + } else { > + s->mii_cr =3D s->mii_data & ~(MII_REG_CR_RESET | > + MII_REG_CR_AUTO_NEG_RESTAR= T); > + } > + break; > + default: > + qemu_log_mask(LOG_UNIMP, "allwinner-h3-emac: write access = to " > + "unknown MII register 0x%x\n", re= g); > + break; > + } > + } else { > + switch (reg) { > + case MII_REG_CR: > + s->mii_data =3D s->mii_cr; > + break; > + case MII_REG_ST: > + s->mii_data =3D s->mii_st; > + break; > + case MII_REG_ID_HIGH: > + s->mii_data =3D MII_PHY_ID_HIGH; > + break; > + case MII_REG_ID_LOW: > + s->mii_data =3D MII_PHY_ID_LOW; > + break; > + default: > + qemu_log_mask(LOG_UNIMP, "allwinner-h3-emac: read access t= o " > + "unknown MII register 0x%x\n", re= g); > + s->mii_data =3D 0; > + break; > + } > + > + trace_aw_h3_emac_mii_read_reg(reg, s->mii_data); > + } > +} > + > +static void aw_h3_emac_update_irq(AwH3EmacState *s) > +{ > + qemu_set_irq(s->irq, (s->int_sta & s->int_en) !=3D 0); > +} > + > +static uint32_t aw_h3_emac_next_desc(FrameDescriptor *desc, size_t min= _size) > +{ > + uint32_t paddr =3D desc->next; > + > + cpu_physical_memory_read(paddr, desc, sizeof(*desc)); > + > + if ((desc->status & DESC_STATUS_CTL) && > + (desc->status2 & DESC_STATUS2_BUF_SIZE_MASK) >=3D min_size) { > + return paddr; > + } else { > + return 0; > + } > +} > + > +static uint32_t aw_h3_emac_get_desc(FrameDescriptor *desc, uint32_t st= art_addr, > + size_t min_size) > +{ > + uint32_t desc_addr =3D start_addr; > + > + /* Note that the list is a cycle. Last entry points back to the he= ad. */ > + while (desc_addr !=3D 0) { > + cpu_physical_memory_read(desc_addr, desc, sizeof(*desc)); > + > + if ((desc->status & DESC_STATUS_CTL) && > + (desc->status2 & DESC_STATUS2_BUF_SIZE_MASK) >=3D min_size= ) { > + return desc_addr; > + } else if (desc->next =3D=3D start_addr) { > + break; > + } else { > + desc_addr =3D desc->next; > + } > + } > + > + return 0; > +} > + > +static uint32_t aw_h3_emac_get_rx_desc(AwH3EmacState *s, FrameDescript= or *desc, > + size_t min_size) > +{ > + return aw_h3_emac_get_desc(desc, s->rx_desc_curr, min_size); > +} > + > +static uint32_t aw_h3_emac_get_tx_desc(AwH3EmacState *s, FrameDescript= or *desc, > + size_t min_size) > +{ > + return aw_h3_emac_get_desc(desc, s->tx_desc_head, min_size); > +} > + > +static void aw_h3_emac_flush_desc(FrameDescriptor *desc, uint32_t phys= _addr) > +{ > + cpu_physical_memory_write(phys_addr, desc, sizeof(*desc)); > +} > + > +static int aw_h3_emac_can_receive(NetClientState *nc) > +{ > + AwH3EmacState *s =3D qemu_get_nic_opaque(nc); > + FrameDescriptor desc; > + > + return (s->rx_ctl0 & RX_CTL0_RX_EN) && > + (aw_h3_emac_get_rx_desc(s, &desc, 0) !=3D 0); > +} > + > +static ssize_t aw_h3_emac_receive(NetClientState *nc, const uint8_t *b= uf, > + size_t size) > +{ > + AwH3EmacState *s =3D qemu_get_nic_opaque(nc); > + FrameDescriptor desc; > + size_t bytes_left =3D size; > + size_t desc_bytes =3D 0; > + size_t pad_fcs_size =3D 4; > + size_t padding =3D 0; > + > + if (!(s->rx_ctl0 & RX_CTL0_RX_EN)) { > + return -1; > + } > + > + s->rx_desc_curr =3D aw_h3_emac_get_rx_desc(s, &desc, AW_H3_EMAC_MI= N_PKT_SZ); > + if (!s->rx_desc_curr) { > + s->int_sta |=3D INT_STA_RX_BUF_UA; > + } > + > + /* Keep filling RX descriptors until the whole frame is written */ > + while (s->rx_desc_curr && bytes_left > 0) { > + desc.status &=3D ~DESC_STATUS_CTL; > + desc.status &=3D ~RX_DESC_STATUS_FRM_LEN_MASK; > + > + if (bytes_left =3D=3D size) { > + desc.status |=3D RX_DESC_STATUS_FIRST_DESC; > + } > + > + if ((desc.status2 & DESC_STATUS2_BUF_SIZE_MASK) < > + (bytes_left + pad_fcs_size)) { > + desc_bytes =3D desc.status2 & DESC_STATUS2_BUF_SIZE_MASK; > + desc.status |=3D desc_bytes << RX_DESC_STATUS_FRM_LEN_SHIF= T; > + } else { > + padding =3D pad_fcs_size; > + if (bytes_left < AW_H3_EMAC_MIN_PKT_SZ) { > + padding +=3D (AW_H3_EMAC_MIN_PKT_SZ - bytes_left); > + } > + > + desc_bytes =3D (bytes_left); > + desc.status |=3D RX_DESC_STATUS_LAST_DESC; > + desc.status |=3D (bytes_left + padding) > + << RX_DESC_STATUS_FRM_LEN_SHIFT; > + } > + > + cpu_physical_memory_write(desc.addr, buf, desc_bytes); > + aw_h3_emac_flush_desc(&desc, s->rx_desc_curr); > + trace_aw_h3_emac_receive(s->rx_desc_curr, desc.addr, desc_byte= s); > + > + /* Check if frame needs to raise the receive interrupt */ > + if (!(desc.status2 & RX_DESC_STATUS2_RX_INT_CTL)) { > + s->int_sta |=3D INT_STA_RX; > + } > + > + /* Increment variables */ > + buf +=3D desc_bytes; > + bytes_left -=3D desc_bytes; > + > + /* Move to the next descriptor */ > + s->rx_desc_curr =3D aw_h3_emac_next_desc(&desc, 64); > + if (!s->rx_desc_curr) { > + /* Not enough buffer space available */ > + s->int_sta |=3D INT_STA_RX_BUF_UA; > + s->rx_desc_curr =3D s->rx_desc_head; > + break; > + } > + } > + > + /* Report receive DMA is finished */ > + s->rx_ctl1 &=3D ~RX_CTL1_RX_DMA_START; > + aw_h3_emac_update_irq(s); > + > + return size; > +} > + > +static void aw_h3_emac_transmit(AwH3EmacState *s) > +{ > + NetClientState *nc =3D qemu_get_queue(s->nic); > + FrameDescriptor desc; > + size_t bytes =3D 0; > + size_t packet_bytes =3D 0; > + size_t transmitted =3D 0; > + static uint8_t packet_buf[2048]; > + > + s->tx_desc_curr =3D aw_h3_emac_get_tx_desc(s, &desc, 0); > + > + /* Read all transmit descriptors */ > + while (s->tx_desc_curr !=3D 0) { > + > + /* Read from physical memory into packet buffer */ > + bytes =3D desc.status2 & DESC_STATUS2_BUF_SIZE_MASK; > + if (bytes + packet_bytes > sizeof(packet_buf)) { > + desc.status |=3D TX_DESC_STATUS_LENGTH_ERR; > + break; > + } > + cpu_physical_memory_read(desc.addr, packet_buf + packet_bytes,= bytes); > + packet_bytes +=3D bytes; > + desc.status &=3D ~DESC_STATUS_CTL; > + aw_h3_emac_flush_desc(&desc, s->tx_desc_curr); > + > + /* After the last descriptor, send the packet */ > + if (desc.status2 & TX_DESC_STATUS2_LAST_DESC) { > + if (desc.status2 & TX_DESC_STATUS2_CHECKSUM_MASK) { > + net_checksum_calculate(packet_buf, packet_bytes); > + } > + > + qemu_send_packet(nc, packet_buf, packet_bytes); > + trace_aw_h3_emac_transmit(s->tx_desc_curr, desc.addr, byte= s); > + > + packet_bytes =3D 0; > + transmitted++; > + } > + s->tx_desc_curr =3D aw_h3_emac_next_desc(&desc, 0); > + } > + > + /* Raise transmit completed interrupt */ > + if (transmitted > 0) { > + s->int_sta |=3D INT_STA_TX; > + s->tx_ctl1 &=3D ~TX_CTL1_TX_DMA_START; > + aw_h3_emac_update_irq(s); > + } > +} > + > +static void aw_h3_emac_reset(DeviceState *dev) > +{ > + AwH3EmacState *s =3D AW_H3_EMAC(dev); > + NetClientState *nc =3D qemu_get_queue(s->nic); > + > + trace_aw_h3_emac_reset(); > + > + s->mii_cmd =3D 0; > + s->mii_data =3D 0; > + s->basic_ctl0 =3D 0; > + s->basic_ctl1 =3D 0; > + s->int_en =3D 0; > + s->int_sta =3D 0; > + s->frm_flt =3D 0; > + s->rx_ctl0 =3D 0; > + s->rx_ctl1 =3D RX_CTL1_RX_MD; > + s->rx_desc_head =3D 0; > + s->rx_desc_curr =3D 0; > + s->tx_ctl0 =3D 0; > + s->tx_ctl1 =3D 0; > + s->tx_desc_head =3D 0; > + s->tx_desc_curr =3D 0; > + s->tx_flowctl =3D 0; > + > + aw_h3_emac_mii_reset(s, !nc->link_down); > +} > + > +static uint64_t aw_h3_emac_read(void *opaque, hwaddr offset, unsigned = size) > +{ > + AwH3EmacState *s =3D opaque; I'd put AW_H3_EMAC(opaque) here. > + uint64_t value =3D 0; > + FrameDescriptor desc; > + > + switch (offset) { > + case REG_BASIC_CTL_0: /* Basic Control 0 */ > + value =3D s->basic_ctl0; > + break; > + case REG_BASIC_CTL_1: /* Basic Control 1 */ > + value =3D s->basic_ctl1; > + break; > + case REG_INT_STA: /* Interrupt Status */ > + value =3D s->int_sta; > + break; > + case REG_INT_EN: /* Interupt Enable */ > + value =3D s->int_en; > + break; > + case REG_TX_CTL_0: /* Transmit Control 0 */ > + value =3D s->tx_ctl0; > + break; > + case REG_TX_CTL_1: /* Transmit Control 1 */ > + value =3D s->tx_ctl1; > + break; > + case REG_TX_FLOW_CTL: /* Transmit Flow Control */ > + value =3D s->tx_flowctl; > + break; > + case REG_TX_DMA_DESC_LIST: /* Transmit Descriptor List Address */ > + value =3D s->tx_desc_head; > + break; > + case REG_RX_CTL_0: /* Receive Control 0 */ > + value =3D s->rx_ctl0; > + break; > + case REG_RX_CTL_1: /* Receive Control 1 */ > + value =3D s->rx_ctl1; > + break; > + case REG_RX_DMA_DESC_LIST: /* Receive Descriptor List Address */ > + value =3D s->rx_desc_head; > + break; > + case REG_FRM_FLT: /* Receive Frame Filter */ > + value =3D s->frm_flt; > + break; > + case REG_RX_HASH_0: /* Receive Hash Table 0 */ > + case REG_RX_HASH_1: /* Receive Hash Table 1 */ > + break; > + case REG_MII_CMD: /* Management Interface Command */ > + value =3D s->mii_cmd; > + break; > + case REG_MII_DATA: /* Management Interface Data */ > + value =3D s->mii_data; > + break; > + case REG_ADDR_HIGH: /* MAC Address High */ > + value =3D *(((uint32_t *) (s->conf.macaddr.a)) + 1); > + break; > + case REG_ADDR_LOW: /* MAC Address Low */ > + value =3D *(uint32_t *) (s->conf.macaddr.a); > + break; > + case REG_TX_DMA_STA: /* Transmit DMA Status */ > + break; > + case REG_TX_CUR_DESC: /* Transmit Current Descriptor */ > + value =3D s->tx_desc_curr; > + break; > + case REG_TX_CUR_BUF: /* Transmit Current Buffer */ > + if (s->tx_desc_curr !=3D 0) { > + cpu_physical_memory_read(s->tx_desc_curr, &desc, sizeof(de= sc)); > + value =3D desc.addr; > + } else { > + value =3D 0; > + } > + break; > + case REG_RX_DMA_STA: /* Receive DMA Status */ > + break; > + case REG_RX_CUR_DESC: /* Receive Current Descriptor */ > + value =3D s->rx_desc_curr; > + break; > + case REG_RX_CUR_BUF: /* Receive Current Buffer */ > + if (s->rx_desc_curr !=3D 0) { > + cpu_physical_memory_read(s->rx_desc_curr, &desc, sizeof(de= sc)); > + value =3D desc.addr; > + } else { > + value =3D 0; > + } > + break; > + default: > + qemu_log_mask(LOG_UNIMP, "allwinner-h3-emac: read access to un= known " > + "EMAC register 0x" TARGET_FMT_plx "\n= ", > + offset); > + } > + > + trace_aw_h3_emac_read(offset, value); > + return value; > +} > + > +static void aw_h3_emac_write(void *opaque, hwaddr offset, uint64_t val= ue, > + unsigned size) > +{ > + AwH3EmacState *s =3D opaque; The same. > + NetClientState *nc =3D qemu_get_queue(s->nic); > + > + trace_aw_h3_emac_write(offset, value); > + > + switch (offset) { > + case REG_BASIC_CTL_0: /* Basic Control 0 */ > + s->basic_ctl0 =3D value; > + break; > + case REG_BASIC_CTL_1: /* Basic Control 1 */ > + if (value & BASIC_CTL1_SOFTRST) { > + aw_h3_emac_reset(DEVICE(s)); > + value &=3D ~BASIC_CTL1_SOFTRST; > + } > + s->basic_ctl1 =3D value; > + if (aw_h3_emac_can_receive(nc)) { > + qemu_flush_queued_packets(nc); > + } > + break; > + case REG_INT_STA: /* Interrupt Status */ > + s->int_sta &=3D ~value; > + aw_h3_emac_update_irq(s); > + break; > + case REG_INT_EN: /* Interrupt Enable */ > + s->int_en =3D value; > + aw_h3_emac_update_irq(s); > + break; > + case REG_TX_CTL_0: /* Transmit Control 0 */ > + s->tx_ctl0 =3D value; > + break; > + case REG_TX_CTL_1: /* Transmit Control 1 */ > + s->tx_ctl1 =3D value; > + if (value & TX_CTL1_TX_DMA_EN) { > + aw_h3_emac_transmit(s); > + } > + break; > + case REG_TX_FLOW_CTL: /* Transmit Flow Control */ > + s->tx_flowctl =3D value; > + break; > + case REG_TX_DMA_DESC_LIST: /* Transmit Descriptor List Address */ > + s->tx_desc_head =3D value; > + s->tx_desc_curr =3D value; > + break; > + case REG_RX_CTL_0: /* Receive Control 0 */ > + s->rx_ctl0 =3D value; > + break; > + case REG_RX_CTL_1: /* Receive Control 1 */ > + s->rx_ctl1 =3D value | RX_CTL1_RX_MD; > + if ((value & RX_CTL1_RX_DMA_EN) && aw_h3_emac_can_receive(nc))= { > + qemu_flush_queued_packets(nc); > + } > + break; > + case REG_RX_DMA_DESC_LIST: /* Receive Descriptor List Address */ > + s->rx_desc_head =3D value; > + s->rx_desc_curr =3D value; > + break; > + case REG_FRM_FLT: /* Receive Frame Filter */ > + s->frm_flt =3D value; > + break; > + case REG_RX_HASH_0: /* Receive Hash Table 0 */ > + case REG_RX_HASH_1: /* Receive Hash Table 1 */ > + break; > + case REG_MII_CMD: /* Management Interface Command */ > + s->mii_cmd =3D value & ~MII_CMD_PHY_BUSY; > + aw_h3_emac_mii_cmd(s); > + break; > + case REG_MII_DATA: /* Management Interface Data */ > + s->mii_data =3D value; > + break; > + case REG_ADDR_HIGH: /* MAC Address High */ > + s->conf.macaddr.a[4] =3D (value & 0xff); > + s->conf.macaddr.a[5] =3D (value & 0xff00) >> 8; > + break; > + case REG_ADDR_LOW: /* MAC Address Low */ > + s->conf.macaddr.a[0] =3D (value & 0xff); > + s->conf.macaddr.a[1] =3D (value & 0xff00) >> 8; > + s->conf.macaddr.a[2] =3D (value & 0xff0000) >> 16; > + s->conf.macaddr.a[3] =3D (value & 0xff000000) >> 24; > + break; > + case REG_TX_DMA_STA: /* Transmit DMA Status */ > + case REG_TX_CUR_DESC: /* Transmit Current Descriptor */ > + case REG_TX_CUR_BUF: /* Transmit Current Buffer */ > + case REG_RX_DMA_STA: /* Receive DMA Status */ > + case REG_RX_CUR_DESC: /* Receive Current Descriptor */ > + case REG_RX_CUR_BUF: /* Receive Current Buffer */ > + case REG_RGMII_STA: /* RGMII Status */ > + break; > + default: > + qemu_log_mask(LOG_UNIMP, "allwinner-h3-emac: write access to u= nknown " > + "EMAC register 0x" TARGET_FMT_plx "\n= ", > + offset); > + } > +} > + > +static void aw_h3_emac_set_link(NetClientState *nc) > +{ > + AwH3EmacState *s =3D qemu_get_nic_opaque(nc); > + > + trace_aw_h3_emac_set_link(!nc->link_down); > + aw_h3_emac_mii_set_link(s, !nc->link_down); > +} > + > +static const MemoryRegionOps aw_h3_emac_mem_ops =3D { > + .read =3D aw_h3_emac_read, > + .write =3D aw_h3_emac_write, > + .endianness =3D DEVICE_NATIVE_ENDIAN, > + .valid =3D { > + .min_access_size =3D 4, > + .max_access_size =3D 4, > + }, > +}; > + > +static NetClientInfo net_aw_h3_emac_info =3D { > + .type =3D NET_CLIENT_DRIVER_NIC, > + .size =3D sizeof(NICState), > + .can_receive =3D aw_h3_emac_can_receive, > + .receive =3D aw_h3_emac_receive, > + .link_status_changed =3D aw_h3_emac_set_link, > +}; > + > +static void aw_h3_emac_init(Object *obj) > +{ > + SysBusDevice *sbd =3D SYS_BUS_DEVICE(obj); > + AwH3EmacState *s =3D AW_H3_EMAC(obj); > + > + memory_region_init_io(&s->iomem, OBJECT(s), &aw_h3_emac_mem_ops, s= , > + TYPE_AW_H3_EMAC, AW_H3_EMAC_REGS_MEM_SIZE); > + sysbus_init_mmio(sbd, &s->iomem); > + sysbus_init_irq(sbd, &s->irq); > +} > + > +static void aw_h3_emac_realize(DeviceState *dev, Error **errp) > +{ > + AwH3EmacState *s =3D AW_H3_EMAC(dev); > + > + qemu_macaddr_default_if_unset(&s->conf.macaddr); > + s->nic =3D qemu_new_nic(&net_aw_h3_emac_info, &s->conf, > + object_get_typename(OBJECT(dev)), dev->id, s= ); > + qemu_format_nic_info_str(qemu_get_queue(s->nic), s->conf.macaddr.a= ); > +} > + > +static Property aw_h3_emac_properties[] =3D { > + DEFINE_NIC_PROPERTIES(AwH3EmacState, conf), > + DEFINE_PROP_UINT8("phy-addr", AwH3EmacState, mii_phy_addr, 0), > + DEFINE_PROP_END_OF_LIST(), > +}; > + > +static int aw_h3_emac_post_load(void *opaque, int version_id) > +{ > + AwH3EmacState *s =3D opaque; > + > + aw_h3_emac_set_link(qemu_get_queue(s->nic)); > + > + return 0; > +} > + > +static const VMStateDescription vmstate_aw_emac =3D { > + .name =3D TYPE_AW_H3_EMAC, > + .version_id =3D 1, > + .minimum_version_id =3D 1, > + .post_load =3D aw_h3_emac_post_load, > + .fields =3D (VMStateField[]) { > + VMSTATE_UINT8(mii_phy_addr, AwH3EmacState), > + VMSTATE_UINT32(mii_cmd, AwH3EmacState), > + VMSTATE_UINT32(mii_data, AwH3EmacState), > + VMSTATE_UINT32(basic_ctl0, AwH3EmacState), > + VMSTATE_UINT32(basic_ctl1, AwH3EmacState), > + VMSTATE_UINT32(int_en, AwH3EmacState), > + VMSTATE_UINT32(int_sta, AwH3EmacState), > + VMSTATE_UINT32(frm_flt, AwH3EmacState), > + VMSTATE_UINT32(rx_ctl0, AwH3EmacState), > + VMSTATE_UINT32(rx_ctl1, AwH3EmacState), > + VMSTATE_UINT32(rx_desc_head, AwH3EmacState), > + VMSTATE_UINT32(rx_desc_curr, AwH3EmacState), > + VMSTATE_UINT32(tx_ctl0, AwH3EmacState), > + VMSTATE_UINT32(tx_ctl1, AwH3EmacState), > + VMSTATE_UINT32(tx_desc_head, AwH3EmacState), > + VMSTATE_UINT32(tx_desc_curr, AwH3EmacState), > + VMSTATE_UINT32(tx_flowctl, AwH3EmacState), > + VMSTATE_END_OF_LIST() > + } > +}; > + > +static void aw_h3_emac_class_init(ObjectClass *klass, void *data) > +{ > + DeviceClass *dc =3D DEVICE_CLASS(klass); > + > + dc->realize =3D aw_h3_emac_realize; > + dc->props =3D aw_h3_emac_properties; > + dc->reset =3D aw_h3_emac_reset; > + dc->vmsd =3D &vmstate_aw_emac; > +} > + > +static const TypeInfo aw_h3_emac_info =3D { > + .name =3D TYPE_AW_H3_EMAC, > + .parent =3D TYPE_SYS_BUS_DEVICE, > + .instance_size =3D sizeof(AwH3EmacState), > + .instance_init =3D aw_h3_emac_init, > + .class_init =3D aw_h3_emac_class_init, > +}; > + > +static void aw_h3_emac_register_types(void) > +{ > + type_register_static(&aw_h3_emac_info); > +} > + > +type_init(aw_h3_emac_register_types) > diff --git a/hw/net/trace-events b/hw/net/trace-events > index e70f12bee1..e9e2f26f68 100644 > --- a/hw/net/trace-events > +++ b/hw/net/trace-events > @@ -1,5 +1,15 @@ > # See docs/devel/tracing.txt for syntax documentation. > =20 > +# allwinner-h3-emac.c > +aw_h3_emac_mii_write_reg(uint32_t reg, uint32_t value) "MII write: reg= =3D0x%x value=3D0x%x" > +aw_h3_emac_mii_read_reg(uint32_t reg, uint32_t value) "MII read: reg=3D= 0x%x value=3D0x%x" > +aw_h3_emac_receive(uint32_t desc, uint32_t paddr, uint32_t bytes) "RX = packet: desc=3D0x%08x paddr=3D0x%08x bytes=3D%u" > +aw_h3_emac_transmit(uint32_t desc, uint32_t paddr, uint32_t bytes) "TX= packet: desc=3D0x%08x paddr=3D0x%08x bytes=3D%u" > +aw_h3_emac_reset(void) "HW reset" > +aw_h3_emac_set_link(bool active) "Set link: active=3D%u" > +aw_h3_emac_read(uint64_t offset, uint64_t val) "MMIO read: offset=3D0x= %" PRIx64 " value=3D0x%" PRIx64 > +aw_h3_emac_write(uint64_t offset, uint64_t val) "MMIO write: offset=3D= 0x%" PRIx64 " value=3D0x%" PRIx64 > + > # etraxfs_eth.c > mdio_phy_read(int regnum, uint16_t value) "read phy_reg:%d value:0x%0= 4x" > mdio_phy_write(int regnum, uint16_t value) "write phy_reg:%d value:0x= %04x" > diff --git a/include/hw/arm/allwinner-h3.h b/include/hw/arm/allwinner-h= 3.h > index 7aff4ebbd2..b964a60f41 100644 > --- a/include/hw/arm/allwinner-h3.h > +++ b/include/hw/arm/allwinner-h3.h > @@ -31,6 +31,7 @@ > #include "hw/misc/allwinner-h3-syscon.h" > #include "hw/misc/allwinner-h3-sid.h" > #include "hw/sd/allwinner-h3-sdhost.h" > +#include "hw/net/allwinner-h3-emac.h" > #include "target/arm/cpu.h" > =20 > #define AW_H3_SRAM_A1_BASE (0x00000000) > @@ -119,6 +120,7 @@ typedef struct AwH3State { > AwH3SysconState syscon; > AwH3SidState sid; > AwH3SDHostState mmc0; > + AwH3EmacState emac; > GICState gic; > MemoryRegion sram_a1; > MemoryRegion sram_a2; > diff --git a/include/hw/net/allwinner-h3-emac.h b/include/hw/net/allwin= ner-h3-emac.h > new file mode 100644 > index 0000000000..a007d54472 > --- /dev/null > +++ b/include/hw/net/allwinner-h3-emac.h > @@ -0,0 +1,69 @@ > +/* > + * Allwinner H3 EMAC emulation > + * > + * Copyright (C) 2019 Niek Linnenbank > + * > + * This program is free software: you can redistribute it and/or modif= y > + * it under the terms of the GNU General Public License as published b= y > + * the Free Software Foundation, either version 2 of the License, or > + * (at your option) any later version. > + * > + * This program is distributed in the hope that it will be useful, > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > + * GNU General Public License for more details. > + * > + * You should have received a copy of the GNU General Public License > + * along with this program. If not, see . > + */ > + > +#ifndef ALLWINNER_H3_EMAC_H > +#define ALLWINNER_H3_EMAC_H > + > +#include "qemu/units.h" > +#include "net/net.h" > +#include "qemu/fifo8.h" > +#include "hw/net/mii.h" > +#include "hw/sysbus.h" > + > +#define AW_H3_EMAC_REGS_MEM_SIZE (1024) > + > +#define TYPE_AW_H3_EMAC "allwinner-h3-emac" > +#define AW_H3_EMAC(obj) OBJECT_CHECK(AwH3EmacState, (obj), TYPE_AW_H3_= EMAC) > + > +typedef struct AwH3EmacState { > + /*< private >*/ > + SysBusDevice parent_obj; > + /*< public >*/ > + > + MemoryRegion iomem; > + qemu_irq irq; > + NICState *nic; > + NICConf conf; > + > + uint8_t mii_phy_addr; > + uint32_t mii_cmd; > + uint32_t mii_data; > + uint32_t mii_cr; > + uint32_t mii_st; > + > + uint32_t basic_ctl0; > + uint32_t basic_ctl1; > + uint32_t int_en; > + uint32_t int_sta; > + uint32_t frm_flt; > + > + uint32_t rx_ctl0; > + uint32_t rx_ctl1; > + uint32_t rx_desc_head; > + uint32_t rx_desc_curr; > + > + uint32_t tx_ctl0; > + uint32_t tx_ctl1; > + uint32_t tx_desc_head; > + uint32_t tx_desc_curr; > + uint32_t tx_flowctl; > + > +} AwH3EmacState; > + > +#endif >=20 The rest seems ok to me. Thanks for the contribution :)! Cheers, Fred From MAILER-DAEMON Tue Dec 03 05:55:57 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1ic5qX-0003Pm-BG for mharc-qemu-arm@gnu.org; Tue, 03 Dec 2019 05:55:57 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:53415) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ic5qM-0003LW-IN for qemu-arm@nongnu.org; Tue, 03 Dec 2019 05:55:53 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ic5qH-0006sW-Dm for qemu-arm@nongnu.org; Tue, 03 Dec 2019 05:55:45 -0500 Received: from us-smtp-1.mimecast.com ([205.139.110.61]:36425 helo=us-smtp-delivery-1.mimecast.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1ic5qH-0006od-8A for qemu-arm@nongnu.org; Tue, 03 Dec 2019 05:55:41 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1575370536; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=Sz1GpD+3T1QWTgobHdtGvt1jXECG9RFlmUdUGH0uwVA=; b=LmqRVpEvt4adYYmUedXsYAi0ZitjTyL8lPSeUbqs1lLbTjnJ2aEWHU0spcZSphvrGdO3O8 kyp77x+/TLYNFe+pPZxNULc9hQSUNyrMiTzfe1xTfg4fn5L7r3t9dS2Sfh2tij9AT3TE+r 4HbO5QGCLIcz7SWvbiasLxmFXJG0abs= Received: from mimecast-mx01.redhat.com (mimecast-mx01.redhat.com [209.132.183.4]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-138-OVaDAPWzNkKWeEFJbPRAwg-1; Tue, 03 Dec 2019 05:55:35 -0500 Received: from smtp.corp.redhat.com (int-mx07.intmail.prod.int.phx2.redhat.com [10.5.11.22]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx01.redhat.com (Postfix) with ESMTPS id ADB97107ACC5; Tue, 3 Dec 2019 10:55:32 +0000 (UTC) Received: from gondolin (ovpn-116-214.ams2.redhat.com [10.36.116.214]) by smtp.corp.redhat.com (Postfix) with ESMTP id 62E0A10016DA; Tue, 3 Dec 2019 10:55:12 +0000 (UTC) Date: Tue, 3 Dec 2019 11:55:08 +0100 From: Cornelia Huck To: Damien Hedde Cc: qemu-devel@nongnu.org, edgari@xilinx.com, mark.burton@greensocs.com, pbonzini@redhat.com, berrange@redhat.com, ehabkost@redhat.com, peter.maydell@linaro.org, david@gibson.dropbear.id.au, philmd@redhat.com, qemu-arm@nongnu.org, qemu-s390x@nongnu.org, Gerd Hoffmann , Richard Henderson , "Michael S. Tsirkin" , Marcel Apfelbaum , John Snow , =?UTF-8?B?Q8OpZHJpYw==?= Le Goater , Collin Walling , David Hildenbrand , Halil Pasic , Christian Borntraeger , Dmitry Fleytman , Fam Zheng Subject: Re: [PATCH v5 01/13] add device_legacy_reset function to prepare for reset api change Message-ID: <20191203115508.6c2a6ef4.cohuck@redhat.com> In-Reply-To: <20191018150630.31099-2-damien.hedde@greensocs.com> References: <20191018150630.31099-1-damien.hedde@greensocs.com> <20191018150630.31099-2-damien.hedde@greensocs.com> Organization: Red Hat GmbH MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.84 on 10.5.11.22 X-MC-Unique: OVaDAPWzNkKWeEFJbPRAwg-1 X-Mimecast-Spam-Score: 0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 205.139.110.61 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 03 Dec 2019 10:55:53 -0000 On Fri, 18 Oct 2019 17:06:18 +0200 Damien Hedde wrote: > Provide a temporary device_legacy_reset function doing what > device_reset does to prepare for the transition with Resettable > API. >=20 > All occurrence of device_reset in the code tree are also replaced > by device_legacy_reset. >=20 > The new resettable API has different prototype and semantics > (resetting child buses as well as the specified device). Subsequent > commits will make the changeover for each call site individually; once > that is complete device_legacy_reset() will be removed. >=20 > Signed-off-by: Damien Hedde > Reviewed-by: Peter Maydell > Acked-by: David Gibson > --- > Cc: Gerd Hoffmann > Cc: Paolo Bonzini > Cc: "Daniel P. Berrang=C3=A9" > Cc: Eduardo Habkost > Cc: Richard Henderson > Cc: "Michael S. Tsirkin" > Cc: Marcel Apfelbaum > Cc: John Snow > Cc: "C=C3=A9dric Le Goater" > Cc: Collin Walling > Cc: Cornelia Huck > Cc: David Hildenbrand > Cc: Halil Pasic > Cc: Christian Borntraeger > Cc: Dmitry Fleytman > Cc: Fam Zheng > --- > hw/audio/intel-hda.c | 2 +- > hw/core/qdev.c | 6 +++--- > hw/hyperv/hyperv.c | 2 +- > hw/i386/pc.c | 2 +- > hw/ide/microdrive.c | 8 ++++---- > hw/intc/spapr_xive.c | 2 +- > hw/ppc/pnv_psi.c | 2 +- > hw/ppc/spapr_pci.c | 2 +- > hw/ppc/spapr_vio.c | 2 +- > hw/s390x/s390-pci-inst.c | 2 +- > hw/scsi/vmw_pvscsi.c | 2 +- > hw/sd/omap_mmc.c | 2 +- > hw/sd/pl181.c | 2 +- > include/hw/qdev-core.h | 4 ++-- > 14 files changed, 20 insertions(+), 20 deletions(-) Acked-by: Cornelia Huck From MAILER-DAEMON Tue Dec 03 05:57:57 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1ic5sT-0004SB-LJ for mharc-qemu-arm@gnu.org; Tue, 03 Dec 2019 05:57:57 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:40813) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ic5sP-0004Mn-VR for qemu-arm@nongnu.org; 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Tue, 03 Dec 2019 05:57:41 -0500 Received: from smtp.corp.redhat.com (int-mx01.intmail.prod.int.phx2.redhat.com [10.5.11.11]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx01.redhat.com (Postfix) with ESMTPS id 8CBB9801E76; Tue, 3 Dec 2019 10:57:39 +0000 (UTC) Received: from gondolin (ovpn-116-214.ams2.redhat.com [10.36.116.214]) by smtp.corp.redhat.com (Postfix) with ESMTP id 6FAE8600C8; Tue, 3 Dec 2019 10:57:34 +0000 (UTC) Date: Tue, 3 Dec 2019 11:57:31 +0100 From: Cornelia Huck To: Damien Hedde Cc: qemu-devel@nongnu.org, edgari@xilinx.com, mark.burton@greensocs.com, pbonzini@redhat.com, berrange@redhat.com, ehabkost@redhat.com, peter.maydell@linaro.org, david@gibson.dropbear.id.au, philmd@redhat.com, qemu-arm@nongnu.org, qemu-s390x@nongnu.org Subject: Re: [PATCH v5 02/13] hw/core/qdev: add trace events to help with resettable transition Message-ID: <20191203115731.5c5f55f1.cohuck@redhat.com> In-Reply-To: <20191018150630.31099-3-damien.hedde@greensocs.com> References: <20191018150630.31099-1-damien.hedde@greensocs.com> <20191018150630.31099-3-damien.hedde@greensocs.com> Organization: Red Hat GmbH MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.79 on 10.5.11.11 X-MC-Unique: 3WbV_gq6OYiqkqvsa42EWw-1 X-Mimecast-Spam-Score: 0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 205.139.110.120 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 03 Dec 2019 10:57:57 -0000 On Fri, 18 Oct 2019 17:06:19 +0200 Damien Hedde wrote: > Adds trace events to reset procedure and when updating the parent > bus of a device. > > Signed-off-by: Damien Hedde > --- > hw/core/qdev.c | 27 ++++++++++++++++++++++++--- > hw/core/trace-events | 9 +++++++++ > 2 files changed, 33 insertions(+), 3 deletions(-) Reviewed-by: Cornelia Huck From MAILER-DAEMON Tue Dec 03 06:01:35 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1ic5vz-0005jK-4G for mharc-qemu-arm@gnu.org; Tue, 03 Dec 2019 06:01:35 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:60924) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ic5vr-0005gF-C4 for qemu-arm@nongnu.org; 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X-Received-From: 2607:f8b0:4864:20::242 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 03 Dec 2019 11:01:32 -0000 On Fri, 11 Oct 2019 at 14:48, Richard Henderson wrote: > > A translation with 2 ranges has both positive and negative addresses. > This is true for the EL1&0 and the as-yet unimplemented EL2&0 regimes. > > Signed-off-by: Richard Henderson > --- > target/arm/internals.h | 14 ++++++++++++++ > target/arm/helper.c | 22 +++++----------------- > target/arm/translate-a64.c | 3 +-- > 3 files changed, 20 insertions(+), 19 deletions(-) > > diff --git a/target/arm/internals.h b/target/arm/internals.h > index dcc5d6cca3..9486680b87 100644 > --- a/target/arm/internals.h > +++ b/target/arm/internals.h > @@ -804,6 +804,20 @@ static inline void arm_call_el_change_hook(ARMCPU *cpu) > } > } > > +/* Return true if this address translation regime has two ranges. */ > +static inline bool regime_has_2_ranges(ARMMMUIdx mmu_idx) > +{ > + switch (mmu_idx) { > + case ARMMMUIdx_S12NSE0: > + case ARMMMUIdx_S12NSE1: > + case ARMMMUIdx_S1NSE0: > + case ARMMMUIdx_S1NSE1: > + return true; Don't S1SE0 and S1SE1 also need to be here? > + default: > + return false; > + } > +} > + > /* Return true if this address translation regime is secure */ > static inline bool regime_is_secure(CPUARMState *env, ARMMMUIdx mmu_idx) > { > diff --git a/target/arm/helper.c b/target/arm/helper.c > index b690eda136..f9dee51ede 100644 > --- a/target/arm/helper.c > +++ b/target/arm/helper.c > @@ -8774,15 +8774,8 @@ static int get_S1prot(CPUARMState *env, ARMMMUIdx mmu_idx, bool is_aa64, > } > > if (is_aa64) { > - switch (regime_el(env, mmu_idx)) { > - case 1: > - if (!is_user) { > - xn = pxn || (user_rw & PAGE_WRITE); > - } > - break; > - case 2: > - case 3: > - break; > + if (regime_has_2_ranges(mmu_idx) && !is_user) { > + xn = pxn || (user_rw & PAGE_WRITE); > } (I was sceptical that 'regime_has_2_ranges()' was the right condition here, but the Arm ARM really does define it as "valid only when stage 1 of the translation regime can support two VA ranges".) > } else if (arm_feature(env, ARM_FEATURE_V7)) { > switch (regime_el(env, mmu_idx)) { > @@ -9316,7 +9309,6 @@ ARMVAParameters aa64_va_parameters_both(CPUARMState *env, uint64_t va, > ARMMMUIdx mmu_idx) > { > uint64_t tcr = regime_tcr(env, mmu_idx)->raw_tcr; > - uint32_t el = regime_el(env, mmu_idx); > bool tbi, tbid, epd, hpd, tcma, using16k, using64k; > int select, tsz; > > @@ -9326,7 +9318,7 @@ ARMVAParameters aa64_va_parameters_both(CPUARMState *env, uint64_t va, > */ > select = extract64(va, 55, 1); > > - if (el > 1) { > + if (!regime_has_2_ranges(mmu_idx)) { > tsz = extract32(tcr, 0, 6); > using64k = extract32(tcr, 14, 1); > using16k = extract32(tcr, 15, 1); > @@ -9486,10 +9478,7 @@ static bool get_phys_addr_lpae(CPUARMState *env, target_ulong address, > param = aa64_va_parameters(env, address, mmu_idx, > access_type != MMU_INST_FETCH); > level = 0; > - /* If we are in 64-bit EL2 or EL3 then there is no TTBR1, so mark it > - * invalid. > - */ > - ttbr1_valid = (el < 2); > + ttbr1_valid = regime_has_2_ranges(mmu_idx); > addrsize = 64 - 8 * param.tbi; > inputsize = 64 - param.tsz; > } else { > @@ -11095,8 +11084,7 @@ void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc, > ARMVAParameters p0 = aa64_va_parameters_both(env, 0, stage1); > int tbii; > > - /* FIXME: ARMv8.1-VHE S2 translation regime. */ > - if (regime_el(env, stage1) < 2) { > + if (regime_has_2_ranges(mmu_idx)) { Now that the rebuild_hflags patchset has landed this is in rebuild_hflags_a64(). > ARMVAParameters p1 = aa64_va_parameters_both(env, -1, stage1); > tbid = (p1.tbi << 1) | p0.tbi; > tbii = tbid & ~((p1.tbid << 1) | p0.tbid); > diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c > index 51f3af9cd9..c85db69db4 100644 > --- a/target/arm/translate-a64.c > +++ b/target/arm/translate-a64.c > @@ -175,8 +175,7 @@ static void gen_top_byte_ignore(DisasContext *s, TCGv_i64 dst, > if (tbi == 0) { > /* Load unmodified address */ > tcg_gen_mov_i64(dst, src); > - } else if (s->current_el >= 2) { > - /* FIXME: ARMv8.1-VHE S2 translation regime. */ > + } else if (!regime_has_2_ranges(s->mmu_idx)) { > /* Force tag byte to all zero */ > tcg_gen_extract_i64(dst, src, 0, 56); > } else { The comment above this function also needs updating to no longer refer to "EL2 and EL3" vs "EL0 and EL1". (You might also remove the use of the imperial 'We' in the last sentence in it ;-)) Otherwise Reviewed-by: Peter Maydell thanks -- PMM From MAILER-DAEMON Tue Dec 03 06:16:56 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1ic6Aq-0004ij-Pg for mharc-qemu-arm@gnu.org; Tue, 03 Dec 2019 06:16:56 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:51919) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ic6Ao-0004g1-4S for qemu-arm@nongnu.org; Tue, 03 Dec 2019 06:16:55 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ic6Ae-0007pj-0p for qemu-arm@nongnu.org; Tue, 03 Dec 2019 06:16:45 -0500 Received: from us-smtp-2.mimecast.com ([205.139.110.61]:39651 helo=us-smtp-delivery-1.mimecast.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1ic6Ad-0007lQ-IZ for qemu-arm@nongnu.org; Tue, 03 Dec 2019 06:16:43 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1575371802; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=46GkAHZ0kT4yudLpq/A3X3Stoo/DLwoWQbUp1hxmoeM=; b=DmPOKkMgJvCJmn1EX9bhw0x+PFj/CwFg1Tu7W7X/mftgOeE1tJdH3Z3RGNAtJCf9gXywi/ le/0zSpUFuuMr0cKhfBn9nQArvihg5s06E0wXigiB9cpDWHXRXsfKd0o6dZbHSvApKXwPv bdt5AN6cwdMxiblTWGVSyQM1C+s6tfs= Received: from mimecast-mx01.redhat.com (mimecast-mx01.redhat.com [209.132.183.4]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-318-EszTurjQMXW19SBBsTCvXg-1; Tue, 03 Dec 2019 06:16:40 -0500 Received: from smtp.corp.redhat.com (int-mx04.intmail.prod.int.phx2.redhat.com [10.5.11.14]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx01.redhat.com (Postfix) with ESMTPS id 4E8DD107ACC4; Tue, 3 Dec 2019 11:16:39 +0000 (UTC) Received: from gondolin (ovpn-116-214.ams2.redhat.com [10.36.116.214]) by smtp.corp.redhat.com (Postfix) with ESMTP id A05E85DA70; Tue, 3 Dec 2019 11:16:33 +0000 (UTC) Date: Tue, 3 Dec 2019 12:16:30 +0100 From: Cornelia Huck To: Damien Hedde Cc: qemu-devel@nongnu.org, edgari@xilinx.com, mark.burton@greensocs.com, pbonzini@redhat.com, berrange@redhat.com, ehabkost@redhat.com, peter.maydell@linaro.org, david@gibson.dropbear.id.au, philmd@redhat.com, qemu-arm@nongnu.org, qemu-s390x@nongnu.org Subject: Re: [PATCH v5 03/13] hw/core: create Resettable QOM interface Message-ID: <20191203121630.279e68e3.cohuck@redhat.com> In-Reply-To: <20191018150630.31099-4-damien.hedde@greensocs.com> References: <20191018150630.31099-1-damien.hedde@greensocs.com> <20191018150630.31099-4-damien.hedde@greensocs.com> Organization: Red Hat GmbH MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.79 on 10.5.11.14 X-MC-Unique: EszTurjQMXW19SBBsTCvXg-1 X-Mimecast-Spam-Score: 0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 205.139.110.61 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 03 Dec 2019 11:16:55 -0000 On Fri, 18 Oct 2019 17:06:20 +0200 Damien Hedde wrote: > This commit defines an interface allowing multi-phase reset. This aims > to solve a problem of the actual single-phase reset (built in > DeviceClass and BusClass): reset behavior is dependent on the order > in which reset handlers are called. In particular doing external > side-effect (like setting an qemu_irq) is problematic because receiving > object may not be reset yet. > > The Resettable interface divides the reset in 3 well defined phases. > To reset an object tree, all 1st phases are executed then all 2nd then > all 3rd. See the comments in include/hw/resettable.h for a more complete > description. The interface defines 3 phases to let the future > possibility of holding an object into reset for some time. > > The qdev/qbus reset in DeviceClass and BusClass will be modified in > following commits to use this interface. A mechanism is provided > to allow executing a transitional reset handler in place of the 2nd > phase which is executed in children-then-parent order inside a tree. > This will allow to transition devices and buses smoothly while > keeping the exact current qdev/qbus reset behavior for now. > > Documentation will be added in a following commit. > > Signed-off-by: Damien Hedde > --- > > In this patch only a single reset type is supported, but the interface > allows for more to be defined. > > I had some thought about problems which may arise when having multiple > reset types: > > - reset type propagation. Right now we propagate the same reset type > to the children. I don't think it will work that with multiple > types. > For example, if we add pci_bus_reset type: a pci device will > implement the reset type but not its children (they may have > nothing to do with pci). > This can be solved by changing the child_foreach method rules. > We should say that child_foreach may change the type it > propagates to its children (on a children by children basis). > For example, the pci device may just propagate cold reset type > to its children. > For this we need to pass the type as parameter to child_foreach() > method. > > - are all children concerned ? For a given reset type, some child > may not need to be reset. As above we can handle that with > child_foreach: an resettable object can propagate the reset only > to a partial set of its child. > For this we need to know the type when we release the reset, > that's why I added it to resettable_release_reset() even if it > is unused right now. > I've also added an opaque parameter to child_foreach. I think > we will need that to handle the change of parent because we > will need to test if a child is concerned by a reset type: the > opaque will allow to use a test callback and get some result. What about an optional ->filter() callback? That would be invoked if existing prior to calling the child_foreach callback and could be used to exclude children from the reset for this round for all callbacks. Or have it modify the reset type (like in your pci reset -> cold reset example above), and completely skip it if the reset type has been modified to a 'no reset' type? > > - several reset types at the same time. I don't another solution > than saying we execute *enter* and *hold* phase for every reset > type. *exit* will still be executed once for all at the end. > It will be up for each object to cope with it if it handle > multiple reset types. For *enter* is trivial, calling it twice > in a row is no problem given that it should only reset internal > state. For *hold* there may be some complication. > > - Obviously we will need to at least an interface class field to hold > the supported reset types by the class. Also the reset state will > need some modification. > --- > Makefile.objs | 1 + > hw/core/Makefile.objs | 1 + > hw/core/resettable.c | 230 ++++++++++++++++++++++++++++++++++++++++ > hw/core/trace-events | 17 +++ > include/hw/resettable.h | 199 ++++++++++++++++++++++++++++++++++ > 5 files changed, 448 insertions(+) > create mode 100644 hw/core/resettable.c > create mode 100644 include/hw/resettable.h From MAILER-DAEMON Tue Dec 03 06:37:39 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1ic6Ut-0007VA-In for mharc-qemu-arm@gnu.org; Tue, 03 Dec 2019 06:37:39 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:58991) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ic6Ur-0007SH-2T for qemu-arm@nongnu.org; Tue, 03 Dec 2019 06:37:38 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ic6Up-0004bt-Eg for qemu-arm@nongnu.org; Tue, 03 Dec 2019 06:37:36 -0500 Received: from us-smtp-delivery-1.mimecast.com ([205.139.110.120]:33897 helo=us-smtp-1.mimecast.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1ic6Uk-0004Xu-2c for qemu-arm@nongnu.org; Tue, 03 Dec 2019 06:37:31 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1575373046; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=5k+TVu0cIfGxnOX/ynMd2OfHm/k4ejo/NeyD3pZO+z8=; b=QISeKQppfG51B+XruD9HCl0bu7Fmj/ApcHXs+UdNG4NtcFGF65eoqcYVkZeGpSFkltIoV9 VFxuDGpWrd7Sixiyn6ZXh9rnDt5AwA2FeKLEgJ1pPcEyBw3jtFSS2QqN5Jo7u4xnCWTM70 rno2MFf6zNHhm9rS1Jp86NeErw1x6Hs= Received: from mimecast-mx01.redhat.com (mimecast-mx01.redhat.com [209.132.183.4]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-18-bM7UFjCbPN2XtgtErmpyxA-1; Tue, 03 Dec 2019 06:37:25 -0500 Received: from smtp.corp.redhat.com (int-mx05.intmail.prod.int.phx2.redhat.com [10.5.11.15]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx01.redhat.com (Postfix) with ESMTPS id A42E51005502; Tue, 3 Dec 2019 11:37:23 +0000 (UTC) Received: from gondolin (ovpn-116-214.ams2.redhat.com [10.36.116.214]) by smtp.corp.redhat.com (Postfix) with ESMTP id 66D955D6A7; Tue, 3 Dec 2019 11:37:17 +0000 (UTC) Date: Tue, 3 Dec 2019 12:37:14 +0100 From: Cornelia Huck To: Peter Maydell Cc: Damien Hedde , QEMU Developers , Edgar Iglesias , Mark Burton , Paolo Bonzini , "Daniel P. Berrange" , Eduardo Habkost , David Gibson , Philippe =?UTF-8?B?TWF0aGll?= =?UTF-8?B?dS1EYXVkw6k=?= , qemu-arm , qemu-s390x Subject: Re: [PATCH v5 06/13] hw/core/qdev: handle parent bus change regarding resettable Message-ID: <20191203123714.0886e34f.cohuck@redhat.com> In-Reply-To: References: <20191018150630.31099-1-damien.hedde@greensocs.com> <20191018150630.31099-7-damien.hedde@greensocs.com> Organization: Red Hat GmbH MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.79 on 10.5.11.15 X-MC-Unique: bM7UFjCbPN2XtgtErmpyxA-1 X-Mimecast-Spam-Score: 0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 205.139.110.120 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 03 Dec 2019 11:37:38 -0000 On Fri, 29 Nov 2019 18:41:26 +0000 Peter Maydell wrote: > On Fri, 18 Oct 2019 at 16:07, Damien Hedde wrote: > > > > In qdev_set_parent_bus(), when changing the parent bus of a > > realized device, if the source and destination buses are not in the > > same reset state, some adaptation are required. This patch adds > > "adaptations" > > > needed call to resettable_change_parent() to make sure a device reset > > state stays coherent with its parent bus. > > > > The addition is a no-op if: > > 1. the device being parented is not realized. > > 2. the device is realized, but both buses are not under reset. > > > > Case 2 means that as long as qdev_set_parent_bus() is called > > during the machine realization procedure (which is before the > > machine reset so nothing is in reset), it is a no op. > > > > There are 49 call sites of qdev_set_parent_bus(). All but one fall > > into the no-op case: > > + 28 calls related to virtio (in hw/{s390x,display,virtio}/ > > {vhost,virtio}-xxx.c) to set a _vdev_/_vgpu_ composing device > > parent bus just before realizing the _vdev_/_vgpu_. > > + hw/qdev.c: when creating a device in qdev_try_create() > > + hw/sysbus.c: when initializing a device in the sysbus > > + hw/display/virtio-gpu-pci.c: before realizing VirtIOGPUPCIBase/vgpu > > + hw/display/virtio-vga.c: before realizing VirtIOVGABase/vgpu > > + hw/i386/amd_iommu.c: before realizing AMDVIState/pci > > + hw/misc/auxbus.c: when creating an AUXBus > > + hw/misc/auxbus.c: when creating an AUXBus child > > + hw/misc/macio/macio.c: when initializing a MACIOState child > > + hw/misc/macio/macio.c: before realizing NewWorldMacIOState/pmu > > + hw/misc/macio/macio.c: before realizing NewWorldMacIOState/cuda > > + hw/pci-host/designware.c: before realizing DesignwarePCIEHost/root > > + hw/pci-host/gpex.c: before realizing GPEXHost/root > > + hw/pci-host/prep.c: when initializaing PREPPCIState/pci_dev > > + hw/pci-host/q35.c: before realizing Q35PCIHost/mch > > + hw/pci-host/versatile.c: when initializing PCIVPBState/pci_dev > > + hw/pci-host/xilinx-pcie.c: before realizing XilinxPCIEHost/root > > + hw/s390x/event-facility.c: when creating SCLPEventFacility/ > > TYPE_SCLP_QUIESCE > > + hw/s390x/event-facility.c: ditto with SCLPEventFacility/ > > TYPE_SCLP_CPU_HOTPLUG > > + hw/s390x/sclp.c: Not trivial because it is called on a SLCPDevice > > just after realizing it. Ok because at this point the destination > > bus (sysbus) is not in reset; the realize step is before the > > machine reset. > > + hw/sd/core.c: Not OK. Used in sdbus_reparent_card(). See below. > > + hw/ssi/ssi.c: Used to put spi slave on spi bus and connect the cs > > line in ssi_auto_connect_slave(). Ok because this function is only > > used in realize step in hw/ssi/aspeed_smc.ci, hw/ssi/imx_spi.c, > > hw/ssi/mss-spi.c, hw/ssi/xilinx_spi.c and hw/ssi/xilinx_spips.c. > > + hw/xen/xen-legacy-backend.c: when creating a XenLegacyDevice device > > + qdev-monitor.c: in device hotplug creation procedure before realize > > This is a really useful analysis to have in the commit message; > thanks! > > (Side note: I wonder if the sclp.c case could be reordered so > it realizes the device after parenting it? Anyway, not something > to worry about now.) As far as I can see, that should work. This code is a bit weird anyway; the problem is that we need the sysbus somewhere in there... I'm wondering if that can be handled in a different way. But agreed, that is something we can revisit later. > > > Note that this commit alone will have no effect, right now there is no > > use of resettable API to reset anything. So a bus will never be tagged > > as in-reset by this same API. > > > > The one place where side-effect will occurs is in hw/sd/core.c in > > sdbus_reparent_card(). This function is only used in the raspi machines, > > including during the sysbus reset procedure. This case will be fixed by > > a following commit before globally enabling resettable API for sysbus > > reset. > > > > Signed-off-by: Damien Hedde > > Reviewed-by: Peter Maydell > > thanks > -- PMM > From MAILER-DAEMON Tue Dec 03 06:41:44 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1ic6Yo-0001ZA-RM for mharc-qemu-arm@gnu.org; Tue, 03 Dec 2019 06:41:44 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:50253) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ic6Yl-0001Y4-S8 for qemu-arm@nongnu.org; Tue, 03 Dec 2019 06:41:41 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ic6Yj-0004AO-U2 for qemu-arm@nongnu.org; Tue, 03 Dec 2019 06:41:39 -0500 Received: from us-smtp-2.mimecast.com ([207.211.31.81]:50476 helo=us-smtp-1.mimecast.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1ic6Yi-00042o-0G for qemu-arm@nongnu.org; Tue, 03 Dec 2019 06:41:36 -0500 DKIM-Signature: v=1; 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Tue, 3 Dec 2019 11:41:19 +0000 (UTC) Date: Tue, 3 Dec 2019 12:41:16 +0100 From: Cornelia Huck To: Damien Hedde Cc: qemu-devel@nongnu.org, edgari@xilinx.com, mark.burton@greensocs.com, pbonzini@redhat.com, berrange@redhat.com, ehabkost@redhat.com, peter.maydell@linaro.org, david@gibson.dropbear.id.au, philmd@redhat.com, qemu-arm@nongnu.org, qemu-s390x@nongnu.org, Christian Borntraeger , Thomas Huth Subject: Re: [PATCH v5 11/13] hw/s390x/ipl: replace deprecated qdev_reset_all registration Message-ID: <20191203124116.1a1ca685.cohuck@redhat.com> In-Reply-To: <20191018150630.31099-12-damien.hedde@greensocs.com> References: <20191018150630.31099-1-damien.hedde@greensocs.com> <20191018150630.31099-12-damien.hedde@greensocs.com> Organization: Red Hat GmbH MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.79 on 10.5.11.14 X-MC-Unique: UQkry_sTMOyU-FXzNTpUYw-1 X-Mimecast-Spam-Score: 0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 207.211.31.81 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 03 Dec 2019 11:41:41 -0000 On Fri, 18 Oct 2019 17:06:28 +0200 Damien Hedde wrote: > Replace deprecated qdev_reset_all by resettable_cold_reset_fn for > the ipl registration in the main reset handlers. > > This does not impact the behavior for the following reasons: > + at this point resettable just call the old reset methods of devices > and buses in the same order than qdev/qbus. > + resettable handlers registered with qemu_register_reset are > serialized; there is no interleaving. > + eventual explicit calls to legacy reset API (device_reset or > qdev/qbus_reset) inside this reset handler will not be masked out > by resettable mechanism; they do not go through resettable api. > > Signed-off-by: Damien Hedde > --- > Cc: Cornelia Huck > Cc: qemu-s390x@nongnu.org > Cc: Christian Borntraeger > Cc: Thomas Huth > --- > hw/s390x/ipl.c | 10 +++++++++- > 1 file changed, 9 insertions(+), 1 deletion(-) Reviewed-by: Cornelia Huck From MAILER-DAEMON Tue Dec 03 06:45:29 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1ic6cJ-0003Um-O5 for mharc-qemu-arm@gnu.org; Tue, 03 Dec 2019 06:45:21 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:37222) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ic6c5-0003Sw-DQ for qemu-arm@nongnu.org; Tue, 03 Dec 2019 06:45:11 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ic6c2-0001b4-5r for qemu-arm@nongnu.org; Tue, 03 Dec 2019 06:45:03 -0500 Received: from us-smtp-delivery-1.mimecast.com ([207.211.31.120]:52212 helo=us-smtp-1.mimecast.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1ic6c1-0001Yv-Fa for qemu-arm@nongnu.org; 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Tue, 3 Dec 2019 11:44:57 +0000 (UTC) Received: from gondolin (ovpn-116-214.ams2.redhat.com [10.36.116.214]) by smtp.corp.redhat.com (Postfix) with ESMTP id 20892608E2; Tue, 3 Dec 2019 11:44:51 +0000 (UTC) Date: Tue, 3 Dec 2019 12:44:49 +0100 From: Cornelia Huck To: Damien Hedde Cc: qemu-devel@nongnu.org, edgari@xilinx.com, mark.burton@greensocs.com, pbonzini@redhat.com, berrange@redhat.com, ehabkost@redhat.com, peter.maydell@linaro.org, david@gibson.dropbear.id.au, philmd@redhat.com, qemu-arm@nongnu.org, qemu-s390x@nongnu.org Subject: Re: [PATCH v5 00/13] Multi-phase reset mechanism Message-ID: <20191203124449.72158cb9.cohuck@redhat.com> In-Reply-To: <20191018150630.31099-1-damien.hedde@greensocs.com> References: <20191018150630.31099-1-damien.hedde@greensocs.com> Organization: Red Hat GmbH MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.79 on 10.5.11.13 X-MC-Unique: 0FEI4IavMOCpV58pIn4DAQ-1 X-Mimecast-Spam-Score: 0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 207.211.31.120 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 03 Dec 2019 11:45:12 -0000 On Fri, 18 Oct 2019 17:06:17 +0200 Damien Hedde wrote: > Hi all, > > The purpose of this series is to split the current reset procedure > into multiple phases. This will help to solve some ordering > difficulties we have during reset. Previous version can be found here: > https://lists.gnu.org/archive/html/qemu-devel/2019-08/msg04359.html > > This series adds resettable interface and transitions base Device and > Bus classes (sysbus subclasses are ok too). It provides new reset > functions but does not switch anymore the old functions > (device_reset() and qdev/qbus_reset_all()) to resettable interface. > These functions keep the exact same behavior as before. > > The series also transition the main reset handlers registration which > has no impact until devices and buses are transitioned. > > I think this version is way better regarding the transition from the > legacy to the resettable interface than the previous one. > After this series, the plan is then to transition devices, buses and > legacy reset call sites. Devices and buses have to be transitioned > from mother class to daughter classes order but until the final > (daughter) class is transitioned, old monolitic reset behavior will > be kept for this class. I have looked over this patchset a bit (with an eye to the s390 stuff). Seems sane, although I currently don't have the resources to review more in detail. From MAILER-DAEMON Tue Dec 03 06:49:09 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1ic6g1-00063Y-Hm for mharc-qemu-arm@gnu.org; Tue, 03 Dec 2019 06:49:09 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:53270) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ic6fy-0005zj-TB for qemu-arm@nongnu.org; Tue, 03 Dec 2019 06:49:08 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ic6fw-0000UE-An for qemu-arm@nongnu.org; Tue, 03 Dec 2019 06:49:06 -0500 Received: from mail-oi1-x242.google.com ([2607:f8b0:4864:20::242]:43690) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ic6fv-0000QT-T6 for qemu-arm@nongnu.org; Tue, 03 Dec 2019 06:49:04 -0500 Received: by mail-oi1-x242.google.com with SMTP id t25so713816oij.10 for ; Tue, 03 Dec 2019 03:49:03 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=J9a9Q25g3Pw3d8B2XWQ6fSo3JvscZVrNGGE/LmkOG4U=; b=e78gdWVplLjIhNu/AMecMmugJ37cfElNi4nZQ+auDgqzXWKfTKcP1e/vdTAzmge50y P2EW9SgCi43AXrcRvIuM+L45DLOzK83HOKlaCSNRmUoGn00+5S8kPjUBzIWC8Jm02mKt Wl7ejaJTVqkQvK3JK/ZEaXXCugrO77bUSRyveZxKPzgodz+3ypCD9uY/QD5qyGgQaUu1 NOmW7u9R4AB/GWPdZvPsz8/pGK4o0ccofLbG1K7CQBq0RZhxKFqhrAVPph5IufrqTyCo nIPfvmX3M33lM0G/85H3q2Wdi31Vm1LyXoG94w6qwkP/BHWHJ2RKTnwUbmSSBejchftA +SFQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=J9a9Q25g3Pw3d8B2XWQ6fSo3JvscZVrNGGE/LmkOG4U=; b=WsEuVXLctLHAWYDpvK83bALwZzITD8VV2NJw2/+ur2Qb+rpHyJLucEJe7rLR6v2cr7 v54eVRMhqi5AY38GHAxWJwwfZZ2xyQ/Slz/AS+Zgtfx+Q9n5tpXPozhnNzFRZhNf0hbk JdeYrSY8UjJApKsrztvATeHbiSPCb1ezmv5hpomZ72dOzE0MGrbORC270g1Tdzy1/vYv +z3kn4H5jUkoSE5UX1MKG11Y7hs56BFANKWn718ViE7sQLu1aAJTrpS4coguw8Uljoii 0EvH+PwodMtZwMnXCifuvW4IZuw0z5EYXVEElXWksnV4/r+RaWLT6FEcUG4BjCSpNv6l Z2gA== X-Gm-Message-State: APjAAAWuMuiz2pEiFJiCkg3qI25hfgZPOhtnFtXwi4TxKyLqRCOiidqz 4fxJn6fi7yaGGCk90jcCXWPltOzomqykGx8Z1r6zbQ== X-Google-Smtp-Source: APXvYqzjjemuY92HI8Gpo8GGUfhYG7/mB8dIIvujLoGZ28kexWC4M67NLNov85A5LxXWTT/IRsM4VgGNYQseumhrG0k= X-Received: by 2002:aca:3182:: with SMTP id x124mr3275663oix.170.1575373742707; Tue, 03 Dec 2019 03:49:02 -0800 (PST) MIME-Version: 1.0 References: <20191011134744.2477-1-richard.henderson@linaro.org> <20191011134744.2477-4-richard.henderson@linaro.org> In-Reply-To: <20191011134744.2477-4-richard.henderson@linaro.org> From: Peter Maydell Date: Tue, 3 Dec 2019 11:48:51 +0000 Message-ID: Subject: Re: [PATCH v5 03/22] target/arm: Add MTE system registers To: Richard Henderson Cc: QEMU Developers , qemu-arm Content-Type: text/plain; charset="UTF-8" X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::242 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 03 Dec 2019 11:49:08 -0000 On Fri, 11 Oct 2019 at 14:48, Richard Henderson wrote: > > This is TFSRE0_EL1, TFSR_EL1, TFSR_EL2, TFSR_EL3, > RGSR_EL1, GCR_EL1, GMID_EL1, and PSTATE.TCO. > > Signed-off-by: Richard Henderson > --- > v3: Add GMID; add access_mte. > v4: Define only TCO at mte_insn_reg. > --- > target/arm/cpu.h | 3 ++ > target/arm/internals.h | 6 ++++ > target/arm/helper.c | 73 ++++++++++++++++++++++++++++++++++++++ > target/arm/translate-a64.c | 11 ++++++ > 4 files changed, 93 insertions(+) > + { .name = "GMID_EL1", .state = ARM_CP_STATE_AA64, > + .opc0 = 3, .opc1 = 1, .crn = 0, .crm = 0, .opc2 = 4, > + .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = GMID_EL1_BS }, This should trap if HCR_EL2.TID5 is 1 (since we're adding support for the TID* ID reg trap bits now). > + REGINFO_SENTINEL > +}; > + > +static const ARMCPRegInfo mte_tco_reginfo[] = { > + { .name = "TCO", .state = ARM_CP_STATE_AA64, > + .opc0 = 3, .opc1 = 3, .crn = 4, .crm = 2, .opc2 = 7, > + .type = ARM_CP_NO_RAW, > + .access = PL0_RW, .readfn = tco_read, .writefn = tco_write }, > + REGINFO_SENTINEL > +}; > #endif > > static CPAccessResult access_predinv(CPUARMState *env, const ARMCPRegInfo *ri, > @@ -6881,6 +6948,12 @@ void register_cp_regs_for_features(ARMCPU *cpu) > if (cpu_isar_feature(aa64_rndr, cpu)) { > define_arm_cp_regs(cpu, rndr_reginfo); > } So, aa64_mte_insn_reg here is checking for ID_AA64PFR1_EL1 != 0 ("instructions accessible at EL0 are implemented") and aa64_mte is checking for >= 2 ("full implementation"). I think a couple of brief comments would clarify: > + if (cpu_isar_feature(aa64_mte_insn_reg, cpu)) { /* EL0-visible MTE registers, present even for dummy implementation */ > + define_arm_cp_regs(cpu, mte_tco_reginfo); > + } > + if (cpu_isar_feature(aa64_mte, cpu)) { /* MTE registers present for a full implementation */ > + define_arm_cp_regs(cpu, mte_reginfo); > + } (The other way to arrange this would be to have the 'real' TCO regdef in mte_reginfo, and separately have "reginfo if we only have the dummy visible-from-EL0-parts-only which defines a constant 0 TCO" (and also make the MSR_i code implement a RAZ/WI for this case, for consistency). An implementation that allows the guest to toggle the PSTATE.TCO bit to no visible effect is architecturally valid, though.) > #endif > > /* > diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c > index c85db69db4..62bdf50796 100644 > --- a/target/arm/translate-a64.c > +++ b/target/arm/translate-a64.c > @@ -1611,6 +1611,17 @@ static void handle_msr_i(DisasContext *s, uint32_t insn, > s->base.is_jmp = DISAS_UPDATE; > break; > > + case 0x1c: /* TCO */ > + if (!dc_isar_feature(aa64_mte_insn_reg, s)) { > + goto do_unallocated; > + } > + if (crm & 1) { > + set_pstate_bits(PSTATE_TCO); > + } else { > + clear_pstate_bits(PSTATE_TCO); > + } > + break; > + > default: > do_unallocated: > unallocated_encoding(s); > -- > 2.17.1 Otherwise Reviewed-by: Peter Maydell thanks -- PMM From MAILER-DAEMON Tue Dec 03 07:29:49 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1ic7JL-00083B-Tw for mharc-qemu-arm@gnu.org; Tue, 03 Dec 2019 07:29:49 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:48647) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ic7JG-00082r-KG for qemu-arm@nongnu.org; Tue, 03 Dec 2019 07:29:44 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ic7JE-0003Yf-80 for qemu-arm@nongnu.org; Tue, 03 Dec 2019 07:29:41 -0500 Received: from szxga07-in.huawei.com ([45.249.212.35]:40888 helo=huawei.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1ic7JC-0003Q6-Fn; Tue, 03 Dec 2019 07:29:39 -0500 Received: from DGGEMS412-HUB.china.huawei.com (unknown [172.30.72.58]) by Forcepoint Email with ESMTP id 493BF2DA8E0A56A3B62F; Tue, 3 Dec 2019 20:29:31 +0800 (CST) Received: from HGHY4Z004218071.china.huawei.com (10.133.224.57) by DGGEMS412-HUB.china.huawei.com (10.3.19.212) with Microsoft SMTP Server id 14.3.439.0; Tue, 3 Dec 2019 20:29:21 +0800 From: Xiang Zheng To: , , CC: , , , , , , Subject: [PATCH 0/5] tests: Enable fw_cfg tests on AArch64 Date: Tue, 3 Dec 2019 20:27:48 +0800 Message-ID: <20191203122753.19792-1-zhengxiang9@huawei.com> X-Mailer: git-send-email 2.15.1.windows.2 MIME-Version: 1.0 Content-Type: text/plain X-Originating-IP: [10.133.224.57] X-CFilter-Loop: Reflected X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 45.249.212.35 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 03 Dec 2019 12:29:45 -0000 There are quite a few tests disabled on AArch64 such as fw_cfg-tests. This patch series fix some problems in test code and adapt it to virt machine. Xiang Zheng (5): tests: fw_cfg: Rename pc_fw_cfg_* to fw_cfg_* tests: fw_cfg: Support read/write of fw_cfg registers on aarch64 tests: fw_cfg: Use virt as default machine in fw_cfg-test.c hw/arm/virt: Add FW_CFG_RAM_SIZE and FW_CFG_MAX_CPUS into fw_cfg tests: Enable fw_cfg test on aarch64 hw/arm/virt.c | 3 ++ tests/Makefile.include | 1 + tests/fw_cfg-test.c | 113 ++++++++++++++++++++++++++------------- tests/hd-geo-test.c | 6 +-- tests/libqos/fw_cfg.c | 17 +++++- tests/libqos/fw_cfg.h | 20 +++++-- tests/libqos/malloc-pc.c | 4 +- 7 files changed, 115 insertions(+), 49 deletions(-) -- 2.19.1 From MAILER-DAEMON Tue Dec 03 07:30:00 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1ic7JW-00086z-A7 for mharc-qemu-arm@gnu.org; Tue, 03 Dec 2019 07:29:58 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:48764) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ic7JJ-00082z-MK for qemu-arm@nongnu.org; Tue, 03 Dec 2019 07:29:47 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ic7JI-0003d5-4o for qemu-arm@nongnu.org; Tue, 03 Dec 2019 07:29:45 -0500 Received: from szxga07-in.huawei.com ([45.249.212.35]:40892 helo=huawei.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1ic7JG-0003QA-E4; Tue, 03 Dec 2019 07:29:43 -0500 Received: from DGGEMS412-HUB.china.huawei.com (unknown [172.30.72.58]) by Forcepoint Email with ESMTP id 55886495215DB76C2F91; Tue, 3 Dec 2019 20:29:31 +0800 (CST) Received: from HGHY4Z004218071.china.huawei.com (10.133.224.57) by DGGEMS412-HUB.china.huawei.com (10.3.19.212) with Microsoft SMTP Server id 14.3.439.0; Tue, 3 Dec 2019 20:29:24 +0800 From: Xiang Zheng To: , , CC: , , , , , , Subject: [PATCH 4/5] hw/arm/virt: Add FW_CFG_RAM_SIZE and FW_CFG_MAX_CPUS into fw_cfg Date: Tue, 3 Dec 2019 20:27:52 +0800 Message-ID: <20191203122753.19792-5-zhengxiang9@huawei.com> X-Mailer: git-send-email 2.15.1.windows.2 In-Reply-To: <20191203122753.19792-1-zhengxiang9@huawei.com> References: <20191203122753.19792-1-zhengxiang9@huawei.com> MIME-Version: 1.0 Content-Type: text/plain X-Originating-IP: [10.133.224.57] X-CFilter-Loop: Reflected X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 45.249.212.35 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 03 Dec 2019 12:29:49 -0000 I'm not sure whether it's neccesary to add FW_CFG_RAM_SIZE and FW_CFG_MAX_CPUS into fw_cfg on virt machine. This patch just makes the fw_cfg-test happy. Signed-off-by: Xiang Zheng --- hw/arm/virt.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/hw/arm/virt.c b/hw/arm/virt.c index d4bedc2607..26a4183775 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -1084,6 +1084,9 @@ static FWCfgState *create_fw_cfg(const VirtMachineState *vms, AddressSpace *as) fw_cfg = fw_cfg_init_mem_wide(base + 8, base, 8, base + 16, as); fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, (uint16_t)ms->smp.cpus); + fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size); + fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, (uint16_t)ms->smp.max_cpus); + nodename = g_strdup_printf("/fw-cfg@%" PRIx64, base); qemu_fdt_add_subnode(vms->fdt, nodename); qemu_fdt_setprop_string(vms->fdt, nodename, -- 2.19.1 From MAILER-DAEMON Tue Dec 03 07:30:04 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1ic7JY-00087N-LS for mharc-qemu-arm@gnu.org; Tue, 03 Dec 2019 07:30:01 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:48783) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ic7JK-000832-Of for qemu-arm@nongnu.org; Tue, 03 Dec 2019 07:29:49 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ic7JI-0003dh-78 for qemu-arm@nongnu.org; Tue, 03 Dec 2019 07:29:45 -0500 Received: from szxga07-in.huawei.com ([45.249.212.35]:40894 helo=huawei.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1ic7JG-0003Q7-F6; Tue, 03 Dec 2019 07:29:44 -0500 Received: from DGGEMS412-HUB.china.huawei.com (unknown [172.30.72.58]) by Forcepoint Email with ESMTP id 631662E73581EE20096E; Tue, 3 Dec 2019 20:29:31 +0800 (CST) Received: from HGHY4Z004218071.china.huawei.com (10.133.224.57) by DGGEMS412-HUB.china.huawei.com (10.3.19.212) with Microsoft SMTP Server id 14.3.439.0; Tue, 3 Dec 2019 20:29:23 +0800 From: Xiang Zheng To: , , CC: , , , , , , Subject: [PATCH 2/5] tests: fw_cfg: Support read/write of fw_cfg registers on aarch64 Date: Tue, 3 Dec 2019 20:27:50 +0800 Message-ID: <20191203122753.19792-3-zhengxiang9@huawei.com> X-Mailer: git-send-email 2.15.1.windows.2 In-Reply-To: <20191203122753.19792-1-zhengxiang9@huawei.com> References: <20191203122753.19792-1-zhengxiang9@huawei.com> MIME-Version: 1.0 Content-Type: text/plain X-Originating-IP: [10.133.224.57] X-CFilter-Loop: Reflected X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 45.249.212.35 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 03 Dec 2019 12:29:49 -0000 Refer to the fw_cfg registers locations of x86 and arm in docs/specs/fw_cfg.txt, the test codes need to differ on the addresses for read/write. Besides, fix the endian problems in mm_fw_cfg_select(). Signed-off-by: Xiang Zheng --- tests/libqos/fw_cfg.c | 17 +++++++++++++++-- 1 file changed, 15 insertions(+), 2 deletions(-) diff --git a/tests/libqos/fw_cfg.c b/tests/libqos/fw_cfg.c index 1f46258f96..c1518c5e81 100644 --- a/tests/libqos/fw_cfg.c +++ b/tests/libqos/fw_cfg.c @@ -57,7 +57,14 @@ uint64_t qfw_cfg_get_u64(QFWCFG *fw_cfg, uint16_t key) static void mm_fw_cfg_select(QFWCFG *fw_cfg, uint16_t key) { - qtest_writew(fw_cfg->qts, fw_cfg->base, key); + const char *arch = qtest_get_arch(); + uint64_t offset = 0; + + if (!strcmp(arch, "aarch64")) { + offset = 8; + } + + qtest_writew(fw_cfg->qts, fw_cfg->base + offset, cpu_to_be16(key)); } /* @@ -108,9 +115,15 @@ static void mm_fw_cfg_read(QFWCFG *fw_cfg, void *data, size_t len) { uint8_t *ptr = data; int i; + uint64_t offset = 2; + const char *arch = qtest_get_arch(); + + if (!strcmp(arch, "aarch64")) { + offset = 0; + } for (i = 0; i < len; i++) { - ptr[i] = qtest_readb(fw_cfg->qts, fw_cfg->base + 2); + ptr[i] = qtest_readb(fw_cfg->qts, fw_cfg->base + offset); } } -- 2.19.1 From MAILER-DAEMON Tue Dec 03 07:30:05 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1ic7Jd-00089z-54 for mharc-qemu-arm@gnu.org; Tue, 03 Dec 2019 07:30:05 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:48793) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ic7JK-000833-QX for qemu-arm@nongnu.org; Tue, 03 Dec 2019 07:29:49 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ic7JI-0003eS-RG for qemu-arm@nongnu.org; Tue, 03 Dec 2019 07:29:45 -0500 Received: from szxga07-in.huawei.com ([45.249.212.35]:41160 helo=huawei.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1ic7JI-0003Zf-5o; Tue, 03 Dec 2019 07:29:44 -0500 Received: from DGGEMS412-HUB.china.huawei.com (unknown [172.30.72.59]) by Forcepoint Email with ESMTP id 4CC09DFCF0713DAA2A47; Tue, 3 Dec 2019 20:29:36 +0800 (CST) Received: from HGHY4Z004218071.china.huawei.com (10.133.224.57) by DGGEMS412-HUB.china.huawei.com (10.3.19.212) with Microsoft SMTP Server id 14.3.439.0; Tue, 3 Dec 2019 20:29:25 +0800 From: Xiang Zheng To: , , CC: , , , , , , Subject: [PATCH 5/5] tests: Enable fw_cfg test on aarch64 Date: Tue, 3 Dec 2019 20:27:53 +0800 Message-ID: <20191203122753.19792-6-zhengxiang9@huawei.com> X-Mailer: git-send-email 2.15.1.windows.2 In-Reply-To: <20191203122753.19792-1-zhengxiang9@huawei.com> References: <20191203122753.19792-1-zhengxiang9@huawei.com> MIME-Version: 1.0 Content-Type: text/plain X-Originating-IP: [10.133.224.57] X-CFilter-Loop: Reflected X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 45.249.212.35 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 03 Dec 2019 12:29:49 -0000 Now turn on the fw_cfg test for aarch64. Signed-off-by: Xiang Zheng --- tests/Makefile.include | 1 + 1 file changed, 1 insertion(+) diff --git a/tests/Makefile.include b/tests/Makefile.include index 8566f5f119..180e0ed2b7 100644 --- a/tests/Makefile.include +++ b/tests/Makefile.include @@ -276,6 +276,7 @@ check-qtest-aarch64-y += tests/arm-cpu-features$(EXESUF) check-qtest-aarch64-y += tests/numa-test$(EXESUF) check-qtest-aarch64-y += tests/boot-serial-test$(EXESUF) check-qtest-aarch64-y += tests/migration-test$(EXESUF) +check-qtest-aarch64-y += tests/fw_cfg-test$(EXESUF) # TODO: once aarch64 TCG is fixed on ARM 32 bit host, make test unconditional ifneq ($(ARCH),arm) check-qtest-aarch64-y += tests/bios-tables-test$(EXESUF) -- 2.19.1 From MAILER-DAEMON Tue Dec 03 07:30:10 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1ic7Ji-0008Dk-Ke for mharc-qemu-arm@gnu.org; Tue, 03 Dec 2019 07:30:10 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:48656) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ic7JH-00082s-Ni for qemu-arm@nongnu.org; Tue, 03 Dec 2019 07:29:46 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ic7JE-0003Yy-A2 for qemu-arm@nongnu.org; Tue, 03 Dec 2019 07:29:42 -0500 Received: from szxga07-in.huawei.com ([45.249.212.35]:40896 helo=huawei.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1ic7JD-0003QC-Rb; Tue, 03 Dec 2019 07:29:40 -0500 Received: from DGGEMS412-HUB.china.huawei.com (unknown [172.30.72.58]) by Forcepoint Email with ESMTP id 6F224D2CDBA246A38D2B; Tue, 3 Dec 2019 20:29:31 +0800 (CST) Received: from HGHY4Z004218071.china.huawei.com (10.133.224.57) by DGGEMS412-HUB.china.huawei.com (10.3.19.212) with Microsoft SMTP Server id 14.3.439.0; Tue, 3 Dec 2019 20:29:24 +0800 From: Xiang Zheng To: , , CC: , , , , , , Subject: [PATCH 3/5] tests: fw_cfg: Use virt as default machine in fw_cfg-test.c Date: Tue, 3 Dec 2019 20:27:51 +0800 Message-ID: <20191203122753.19792-4-zhengxiang9@huawei.com> X-Mailer: git-send-email 2.15.1.windows.2 In-Reply-To: <20191203122753.19792-1-zhengxiang9@huawei.com> References: <20191203122753.19792-1-zhengxiang9@huawei.com> MIME-Version: 1.0 Content-Type: text/plain X-Originating-IP: [10.133.224.57] X-CFilter-Loop: Reflected X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 45.249.212.35 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 03 Dec 2019 12:29:47 -0000 The default machine type on aarch64 is not set which causes error in qtest_init(). Here we use the "virt" machine as the default machine type on aarch64. Signed-off-by: Xiang Zheng --- tests/fw_cfg-test.c | 65 +++++++++++++++++++++++++++++++++++---------- 1 file changed, 51 insertions(+), 14 deletions(-) diff --git a/tests/fw_cfg-test.c b/tests/fw_cfg-test.c index 5a5342fa9d..a3a67d1099 100644 --- a/tests/fw_cfg-test.c +++ b/tests/fw_cfg-test.c @@ -23,13 +23,28 @@ static uint16_t max_cpus = 1; static uint64_t nb_nodes = 0; static uint16_t boot_menu = 0; +static char *make_extra_args(const char *args) +{ + const char *arch = qtest_get_arch(); + const char *machine_arg = NULL; + + if (strcmp(arch, "aarch64") == 0) { + machine_arg = "-machine virt"; + } else { + machine_arg = ""; + } + + return g_strdup_printf("%s %s", machine_arg, args); +} + static void test_fw_cfg_signature(void) { QFWCFG *fw_cfg; QTestState *s; char buf[5]; + char *cli = make_extra_args(""); - s = qtest_init(""); + s = qtest_init(cli); fw_cfg = fw_cfg_init(s); qfw_cfg_get(fw_cfg, FW_CFG_SIGNATURE, buf, 4); @@ -38,6 +53,7 @@ static void test_fw_cfg_signature(void) g_assert_cmpstr(buf, ==, "QEMU"); fw_cfg_uninit(fw_cfg); qtest_quit(s); + g_free(cli); } static void test_fw_cfg_id(void) @@ -45,8 +61,9 @@ static void test_fw_cfg_id(void) QFWCFG *fw_cfg; QTestState *s; uint32_t id; + char *cli = make_extra_args(""); - s = qtest_init(""); + s = qtest_init(cli); fw_cfg = fw_cfg_init(s); id = qfw_cfg_get_u32(fw_cfg, FW_CFG_ID); @@ -54,6 +71,7 @@ static void test_fw_cfg_id(void) (id == 3)); fw_cfg_uninit(fw_cfg); qtest_quit(s); + g_free(cli); } static void test_fw_cfg_uuid(void) @@ -66,8 +84,9 @@ static void test_fw_cfg_uuid(void) 0x46, 0x00, 0xcb, 0x32, 0x38, 0xec, 0x4b, 0x2f, 0x8a, 0xcb, 0x81, 0xc6, 0xea, 0x54, 0xf2, 0xd8, }; + char *cli = make_extra_args("-uuid 4600cb32-38ec-4b2f-8acb-81c6ea54f2d8"); - s = qtest_init("-uuid 4600cb32-38ec-4b2f-8acb-81c6ea54f2d8"); + s = qtest_init(cli); fw_cfg = fw_cfg_init(s); qfw_cfg_get(fw_cfg, FW_CFG_UUID, buf, 16); @@ -75,62 +94,70 @@ static void test_fw_cfg_uuid(void) fw_cfg_uninit(fw_cfg); qtest_quit(s); - + g_free(cli); } static void test_fw_cfg_ram_size(void) { QFWCFG *fw_cfg; QTestState *s; + char *cli = make_extra_args(""); - s = qtest_init(""); + s = qtest_init(cli); fw_cfg = fw_cfg_init(s); g_assert_cmpint(qfw_cfg_get_u64(fw_cfg, FW_CFG_RAM_SIZE), ==, ram_size); fw_cfg_uninit(fw_cfg); qtest_quit(s); + g_free(cli); } static void test_fw_cfg_nographic(void) { QFWCFG *fw_cfg; QTestState *s; + char *cli = make_extra_args(""); - s = qtest_init(""); + s = qtest_init(cli); fw_cfg = fw_cfg_init(s); g_assert_cmpint(qfw_cfg_get_u16(fw_cfg, FW_CFG_NOGRAPHIC), ==, 0); fw_cfg_uninit(fw_cfg); qtest_quit(s); + g_free(cli); } static void test_fw_cfg_nb_cpus(void) { QFWCFG *fw_cfg; QTestState *s; + char *cli = make_extra_args(""); - s = qtest_init(""); + s = qtest_init(cli); fw_cfg = fw_cfg_init(s); g_assert_cmpint(qfw_cfg_get_u16(fw_cfg, FW_CFG_NB_CPUS), ==, nb_cpus); fw_cfg_uninit(fw_cfg); qtest_quit(s); + g_free(cli); } static void test_fw_cfg_max_cpus(void) { QFWCFG *fw_cfg; QTestState *s; + char *cli = make_extra_args(""); - s = qtest_init(""); + s = qtest_init(cli); fw_cfg = fw_cfg_init(s); g_assert_cmpint(qfw_cfg_get_u16(fw_cfg, FW_CFG_MAX_CPUS), ==, max_cpus); fw_cfg_uninit(fw_cfg); qtest_quit(s); + g_free(cli); } static void test_fw_cfg_numa(void) @@ -139,8 +166,9 @@ static void test_fw_cfg_numa(void) QTestState *s; uint64_t *cpu_mask; uint64_t *node_mask; + char *cli = make_extra_args(""); - s = qtest_init(""); + s = qtest_init(cli); fw_cfg = fw_cfg_init(s); g_assert_cmpint(qfw_cfg_get_u64(fw_cfg, FW_CFG_NUMA), ==, nb_nodes); @@ -160,19 +188,22 @@ static void test_fw_cfg_numa(void) g_free(cpu_mask); fw_cfg_uninit(fw_cfg); qtest_quit(s); + g_free(cli); } static void test_fw_cfg_boot_menu(void) { QFWCFG *fw_cfg; QTestState *s; + char *cli = make_extra_args(""); - s = qtest_init(""); + s = qtest_init(cli); fw_cfg = fw_cfg_init(s); g_assert_cmpint(qfw_cfg_get_u16(fw_cfg, FW_CFG_BOOT_MENU), ==, boot_menu); fw_cfg_uninit(fw_cfg); qtest_quit(s); + g_free(cli); } static void test_fw_cfg_reboot_timeout(void) @@ -181,8 +212,9 @@ static void test_fw_cfg_reboot_timeout(void) QTestState *s; uint32_t reboot_timeout = 0; size_t filesize; + char *cli = make_extra_args("-boot reboot-timeout=15"); - s = qtest_init("-boot reboot-timeout=15"); + s = qtest_init(cli); fw_cfg = fw_cfg_init(s); filesize = qfw_cfg_get_file(fw_cfg, "etc/boot-fail-wait", @@ -192,6 +224,7 @@ static void test_fw_cfg_reboot_timeout(void) g_assert_cmpint(reboot_timeout, ==, 15); fw_cfg_uninit(fw_cfg); qtest_quit(s); + g_free(cli); } static void test_fw_cfg_no_reboot_timeout(void) @@ -200,9 +233,10 @@ static void test_fw_cfg_no_reboot_timeout(void) QTestState *s; uint32_t reboot_timeout = 0; size_t filesize; - /* Special value -1 means "don't reboot" */ - s = qtest_init("-boot reboot-timeout=-1"); + char *cli = make_extra_args("-boot reboot-timeout=-1"); + + s = qtest_init(cli); fw_cfg = fw_cfg_init(s); filesize = qfw_cfg_get_file(fw_cfg, "etc/boot-fail-wait", @@ -212,6 +246,7 @@ static void test_fw_cfg_no_reboot_timeout(void) g_assert_cmpint(reboot_timeout, ==, UINT32_MAX); fw_cfg_uninit(fw_cfg); qtest_quit(s); + g_free(cli); } static void test_fw_cfg_splash_time(void) @@ -220,8 +255,9 @@ static void test_fw_cfg_splash_time(void) QTestState *s; uint16_t splash_time = 0; size_t filesize; + char *cli = make_extra_args("-boot splash-time=12"); - s = qtest_init("-boot splash-time=12"); + s = qtest_init(cli); fw_cfg = fw_cfg_init(s); filesize = qfw_cfg_get_file(fw_cfg, "etc/boot-menu-wait", @@ -231,6 +267,7 @@ static void test_fw_cfg_splash_time(void) g_assert_cmpint(splash_time, ==, 12); fw_cfg_uninit(fw_cfg); qtest_quit(s); + g_free(cli); } int main(int argc, char **argv) -- 2.19.1 From MAILER-DAEMON Tue Dec 03 07:30:18 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1ic7Jk-0008F6-H0 for mharc-qemu-arm@gnu.org; Tue, 03 Dec 2019 07:30:14 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:48713) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ic7JJ-00082t-8f for qemu-arm@nongnu.org; Tue, 03 Dec 2019 07:29:47 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ic7JG-0003be-JU for qemu-arm@nongnu.org; Tue, 03 Dec 2019 07:29:44 -0500 Received: from szxga07-in.huawei.com ([45.249.212.35]:40890 helo=huawei.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1ic7JD-0003QB-PK; Tue, 03 Dec 2019 07:29:41 -0500 Received: from DGGEMS412-HUB.china.huawei.com (unknown [172.30.72.58]) by Forcepoint Email with ESMTP id 7C2628850E3415A8B2D3; Tue, 3 Dec 2019 20:29:31 +0800 (CST) Received: from HGHY4Z004218071.china.huawei.com (10.133.224.57) by DGGEMS412-HUB.china.huawei.com (10.3.19.212) with Microsoft SMTP Server id 14.3.439.0; Tue, 3 Dec 2019 20:29:22 +0800 From: Xiang Zheng To: , , CC: , , , , , , Subject: [PATCH 1/5] tests: fw_cfg: Rename pc_fw_cfg_* to fw_cfg_* Date: Tue, 3 Dec 2019 20:27:49 +0800 Message-ID: <20191203122753.19792-2-zhengxiang9@huawei.com> X-Mailer: git-send-email 2.15.1.windows.2 In-Reply-To: <20191203122753.19792-1-zhengxiang9@huawei.com> References: <20191203122753.19792-1-zhengxiang9@huawei.com> MIME-Version: 1.0 Content-Type: text/plain X-Originating-IP: [10.133.224.57] X-CFilter-Loop: Reflected X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 45.249.212.35 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 03 Dec 2019 12:29:49 -0000 Rename pc_fw_cfg_* to fw_cfg_* to make them common for other architectures so that we can run fw_cfg tests on aarch64. Signed-off-by: Xiang Zheng --- tests/fw_cfg-test.c | 48 ++++++++++++++++++++-------------------- tests/hd-geo-test.c | 6 ++--- tests/libqos/fw_cfg.h | 20 +++++++++++++---- tests/libqos/malloc-pc.c | 4 ++-- 4 files changed, 45 insertions(+), 33 deletions(-) diff --git a/tests/fw_cfg-test.c b/tests/fw_cfg-test.c index 5dc807ba23..5a5342fa9d 100644 --- a/tests/fw_cfg-test.c +++ b/tests/fw_cfg-test.c @@ -30,13 +30,13 @@ static void test_fw_cfg_signature(void) char buf[5]; s = qtest_init(""); - fw_cfg = pc_fw_cfg_init(s); + fw_cfg = fw_cfg_init(s); qfw_cfg_get(fw_cfg, FW_CFG_SIGNATURE, buf, 4); buf[4] = 0; g_assert_cmpstr(buf, ==, "QEMU"); - pc_fw_cfg_uninit(fw_cfg); + fw_cfg_uninit(fw_cfg); qtest_quit(s); } @@ -47,12 +47,12 @@ static void test_fw_cfg_id(void) uint32_t id; s = qtest_init(""); - fw_cfg = pc_fw_cfg_init(s); + fw_cfg = fw_cfg_init(s); id = qfw_cfg_get_u32(fw_cfg, FW_CFG_ID); g_assert((id == 1) || (id == 3)); - pc_fw_cfg_uninit(fw_cfg); + fw_cfg_uninit(fw_cfg); qtest_quit(s); } @@ -68,12 +68,12 @@ static void test_fw_cfg_uuid(void) }; s = qtest_init("-uuid 4600cb32-38ec-4b2f-8acb-81c6ea54f2d8"); - fw_cfg = pc_fw_cfg_init(s); + fw_cfg = fw_cfg_init(s); qfw_cfg_get(fw_cfg, FW_CFG_UUID, buf, 16); g_assert(memcmp(buf, uuid, sizeof(buf)) == 0); - pc_fw_cfg_uninit(fw_cfg); + fw_cfg_uninit(fw_cfg); qtest_quit(s); } @@ -84,11 +84,11 @@ static void test_fw_cfg_ram_size(void) QTestState *s; s = qtest_init(""); - fw_cfg = pc_fw_cfg_init(s); + fw_cfg = fw_cfg_init(s); g_assert_cmpint(qfw_cfg_get_u64(fw_cfg, FW_CFG_RAM_SIZE), ==, ram_size); - pc_fw_cfg_uninit(fw_cfg); + fw_cfg_uninit(fw_cfg); qtest_quit(s); } @@ -98,11 +98,11 @@ static void test_fw_cfg_nographic(void) QTestState *s; s = qtest_init(""); - fw_cfg = pc_fw_cfg_init(s); + fw_cfg = fw_cfg_init(s); g_assert_cmpint(qfw_cfg_get_u16(fw_cfg, FW_CFG_NOGRAPHIC), ==, 0); - pc_fw_cfg_uninit(fw_cfg); + fw_cfg_uninit(fw_cfg); qtest_quit(s); } @@ -112,11 +112,11 @@ static void test_fw_cfg_nb_cpus(void) QTestState *s; s = qtest_init(""); - fw_cfg = pc_fw_cfg_init(s); + fw_cfg = fw_cfg_init(s); g_assert_cmpint(qfw_cfg_get_u16(fw_cfg, FW_CFG_NB_CPUS), ==, nb_cpus); - pc_fw_cfg_uninit(fw_cfg); + fw_cfg_uninit(fw_cfg); qtest_quit(s); } @@ -126,10 +126,10 @@ static void test_fw_cfg_max_cpus(void) QTestState *s; s = qtest_init(""); - fw_cfg = pc_fw_cfg_init(s); + fw_cfg = fw_cfg_init(s); g_assert_cmpint(qfw_cfg_get_u16(fw_cfg, FW_CFG_MAX_CPUS), ==, max_cpus); - pc_fw_cfg_uninit(fw_cfg); + fw_cfg_uninit(fw_cfg); qtest_quit(s); } @@ -141,7 +141,7 @@ static void test_fw_cfg_numa(void) uint64_t *node_mask; s = qtest_init(""); - fw_cfg = pc_fw_cfg_init(s); + fw_cfg = fw_cfg_init(s); g_assert_cmpint(qfw_cfg_get_u64(fw_cfg, FW_CFG_NUMA), ==, nb_nodes); @@ -158,7 +158,7 @@ static void test_fw_cfg_numa(void) g_free(node_mask); g_free(cpu_mask); - pc_fw_cfg_uninit(fw_cfg); + fw_cfg_uninit(fw_cfg); qtest_quit(s); } @@ -168,10 +168,10 @@ static void test_fw_cfg_boot_menu(void) QTestState *s; s = qtest_init(""); - fw_cfg = pc_fw_cfg_init(s); + fw_cfg = fw_cfg_init(s); g_assert_cmpint(qfw_cfg_get_u16(fw_cfg, FW_CFG_BOOT_MENU), ==, boot_menu); - pc_fw_cfg_uninit(fw_cfg); + fw_cfg_uninit(fw_cfg); qtest_quit(s); } @@ -183,14 +183,14 @@ static void test_fw_cfg_reboot_timeout(void) size_t filesize; s = qtest_init("-boot reboot-timeout=15"); - fw_cfg = pc_fw_cfg_init(s); + fw_cfg = fw_cfg_init(s); filesize = qfw_cfg_get_file(fw_cfg, "etc/boot-fail-wait", &reboot_timeout, sizeof(reboot_timeout)); g_assert_cmpint(filesize, ==, sizeof(reboot_timeout)); reboot_timeout = le32_to_cpu(reboot_timeout); g_assert_cmpint(reboot_timeout, ==, 15); - pc_fw_cfg_uninit(fw_cfg); + fw_cfg_uninit(fw_cfg); qtest_quit(s); } @@ -203,14 +203,14 @@ static void test_fw_cfg_no_reboot_timeout(void) /* Special value -1 means "don't reboot" */ s = qtest_init("-boot reboot-timeout=-1"); - fw_cfg = pc_fw_cfg_init(s); + fw_cfg = fw_cfg_init(s); filesize = qfw_cfg_get_file(fw_cfg, "etc/boot-fail-wait", &reboot_timeout, sizeof(reboot_timeout)); g_assert_cmpint(filesize, ==, sizeof(reboot_timeout)); reboot_timeout = le32_to_cpu(reboot_timeout); g_assert_cmpint(reboot_timeout, ==, UINT32_MAX); - pc_fw_cfg_uninit(fw_cfg); + fw_cfg_uninit(fw_cfg); qtest_quit(s); } @@ -222,14 +222,14 @@ static void test_fw_cfg_splash_time(void) size_t filesize; s = qtest_init("-boot splash-time=12"); - fw_cfg = pc_fw_cfg_init(s); + fw_cfg = fw_cfg_init(s); filesize = qfw_cfg_get_file(fw_cfg, "etc/boot-menu-wait", &splash_time, sizeof(splash_time)); g_assert_cmpint(filesize, ==, sizeof(splash_time)); splash_time = le16_to_cpu(splash_time); g_assert_cmpint(splash_time, ==, 12); - pc_fw_cfg_uninit(fw_cfg); + fw_cfg_uninit(fw_cfg); qtest_quit(s); } diff --git a/tests/hd-geo-test.c b/tests/hd-geo-test.c index 7e86c5416c..a9b8a07403 100644 --- a/tests/hd-geo-test.c +++ b/tests/hd-geo-test.c @@ -693,7 +693,7 @@ static void test_override(TestArgs *args, CHSResult expected[]) joined_args = g_strjoinv(" ", args->argv); qts = qtest_init(joined_args); - fw_cfg = pc_fw_cfg_init(qts); + fw_cfg = fw_cfg_init(qts); read_bootdevices(fw_cfg, expected); @@ -829,7 +829,7 @@ static void test_override_scsi_hot_unplug(void) joined_args = g_strjoinv(" ", args->argv); qts = qtest_init(joined_args); - fw_cfg = pc_fw_cfg_init(qts); + fw_cfg = fw_cfg_init(qts); read_bootdevices(fw_cfg, expected); @@ -889,7 +889,7 @@ static void test_override_virtio_hot_unplug(void) joined_args = g_strjoinv(" ", args->argv); qts = qtest_init(joined_args); - fw_cfg = pc_fw_cfg_init(qts); + fw_cfg = fw_cfg_init(qts); read_bootdevices(fw_cfg, expected); diff --git a/tests/libqos/fw_cfg.h b/tests/libqos/fw_cfg.h index 13325cc4ff..708aa922ed 100644 --- a/tests/libqos/fw_cfg.h +++ b/tests/libqos/fw_cfg.h @@ -39,14 +39,26 @@ void mm_fw_cfg_uninit(QFWCFG *fw_cfg); QFWCFG *io_fw_cfg_init(QTestState *qts, uint16_t base); void io_fw_cfg_uninit(QFWCFG *fw_cfg); -static inline QFWCFG *pc_fw_cfg_init(QTestState *qts) +static inline QFWCFG *fw_cfg_init(QTestState *qts) { - return io_fw_cfg_init(qts, 0x510); + const char *arch = qtest_get_arch(); + + if (!strcmp(arch, "aarch64")) { + return mm_fw_cfg_init(qts, 0x09020000); + } else { + return io_fw_cfg_init(qts, 0x510); + } } -static inline void pc_fw_cfg_uninit(QFWCFG *fw_cfg) +static inline void fw_cfg_uninit(QFWCFG *fw_cfg) { - io_fw_cfg_uninit(fw_cfg); + const char *arch = qtest_get_arch(); + + if (!strcmp(arch, "aarch64")) { + mm_fw_cfg_uninit(fw_cfg); + } else { + io_fw_cfg_uninit(fw_cfg); + } } #endif diff --git a/tests/libqos/malloc-pc.c b/tests/libqos/malloc-pc.c index 6f92ce4135..5c58bf6e88 100644 --- a/tests/libqos/malloc-pc.c +++ b/tests/libqos/malloc-pc.c @@ -23,11 +23,11 @@ void pc_alloc_init(QGuestAllocator *s, QTestState *qts, QAllocOpts flags) { uint64_t ram_size; - QFWCFG *fw_cfg = pc_fw_cfg_init(qts); + QFWCFG *fw_cfg = fw_cfg_init(qts); ram_size = qfw_cfg_get_u64(fw_cfg, FW_CFG_RAM_SIZE); alloc_init(s, flags, 1 << 20, MIN(ram_size, 0xE0000000), PAGE_SIZE); /* clean-up */ - pc_fw_cfg_uninit(fw_cfg); + fw_cfg_uninit(fw_cfg); } -- 2.19.1 From MAILER-DAEMON Tue Dec 03 07:32:57 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1ic7MP-0001lr-8X for mharc-qemu-arm@gnu.org; Tue, 03 Dec 2019 07:32:57 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:58366) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ic7MM-0001h3-Gz for qemu-arm@nongnu.org; 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charset="UTF-8" X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::341 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 03 Dec 2019 12:32:56 -0000 On Tue, 3 Dec 2019 at 12:29, Xiang Zheng wrote: > > I'm not sure whether it's neccesary to add FW_CFG_RAM_SIZE and > FW_CFG_MAX_CPUS into fw_cfg on virt machine. This patch just makes > the fw_cfg-test happy. > > Signed-off-by: Xiang Zheng > --- > hw/arm/virt.c | 3 +++ > 1 file changed, 3 insertions(+) > > diff --git a/hw/arm/virt.c b/hw/arm/virt.c > index d4bedc2607..26a4183775 100644 > --- a/hw/arm/virt.c > +++ b/hw/arm/virt.c > @@ -1084,6 +1084,9 @@ static FWCfgState *create_fw_cfg(const VirtMachineState *vms, AddressSpace *as) > fw_cfg = fw_cfg_init_mem_wide(base + 8, base, 8, base + 16, as); > fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, (uint16_t)ms->smp.cpus); > > + fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size); > + fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, (uint16_t)ms->smp.max_cpus); > + > nodename = g_strdup_printf("/fw-cfg@%" PRIx64, base); > qemu_fdt_add_subnode(vms->fdt, nodename); > qemu_fdt_setprop_string(vms->fdt, nodename, > -- Is there a spec anywhere that defines the meaning of these FW_CFG entries ? docs/specs/fw_cfg.txt defines the device interface but not what the 'standard' keys mean. I'd prefer not to add them to the virt board without knowing what they mean and why we have them. thanks -- PMM From MAILER-DAEMON Tue Dec 03 07:34:49 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1ic7OD-0003TQ-9Z for mharc-qemu-arm@gnu.org; Tue, 03 Dec 2019 07:34:49 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:38090) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ic7OA-0003QW-Of for qemu-arm@nongnu.org; Tue, 03 Dec 2019 07:34:47 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ic7O9-0005e4-HR for qemu-arm@nongnu.org; Tue, 03 Dec 2019 07:34:46 -0500 Received: from mail-ot1-x344.google.com ([2607:f8b0:4864:20::344]:39374) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ic7O8-0005OA-9T for qemu-arm@nongnu.org; Tue, 03 Dec 2019 07:34:45 -0500 Received: by mail-ot1-x344.google.com with SMTP id 77so2720476oty.6 for ; Tue, 03 Dec 2019 04:34:42 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=Y4Ers7w9eC9tFu3//E3iYq14QUmK3g6bRYSZTOSxXBQ=; b=chSW3jeQ3yDjE9qOy+ox4lKN+4lJ9OBSxncisgX8xoaJ4nitsHCBY4f/llanEK2GOu eCHPJqeSvqXBE7oPaimtA+3V1CjIP5nL/1931W6gb34Hkw80zDE8TAyqQDGlvvFtszNj rVU3CLlVmK0XZRbccA/UmQElzTZk57ADj3urQ5g98oOE9uL08XymdWNW4Zzz8BK/kfJn 2ETC9R7Wo+Obb+GQMBOjQnzsux8a/gq33BDL8aY2HJ8XiSdmYKEdts/3djXTOTTTVHUF Fqt3Xqw9jLZZDIMjf9+T2GCvYTv809ySPvJDNx1rq91CzuoeeeqBiE0SXojf2j8aHPGL Lf2g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=Y4Ers7w9eC9tFu3//E3iYq14QUmK3g6bRYSZTOSxXBQ=; b=BAxV5qAWzCjuJftSMJaxrPjS7rvvVfwDKBo8SC0bXLQ93K1W+nbUFHbKNhARXjEJ3s ameluUqTy7p0G2f9NkfXznvJcyIzLfA9ZTMnPl62z3aC/lcMrbR4pbz6NDbfm+bgAMBY rTEXAWEHSnC+lXO+o2vHe0viB84pxOlHhYNldIfUpBEHVaDrD7uPVLe+V3ih49Hf4w7m 2vg07iM5SLRx864uuWz47erWpd7PHLnTNs3+aPOYiChogIEpI6pH6jSmgk0boogM+jnS GSwSPhXr7iqxGvV/F3VFOvLz2Xic/k85ylkngSh/VQ+URgv1Eu2F8NLbhGzFKsP/QXT7 8AiA== X-Gm-Message-State: APjAAAXWU79UddQf6FNzza4K78sIUVaUBXpaBNzBsZnV4Fn8diaEJHXs UlV9UjIfSItgXjLyU3MFbz7r4uBDL2/QloMsSXv+iw== X-Google-Smtp-Source: APXvYqzd9j7AC2GdibUE89z/Zur7rg78vf97ol/Mb09pve+U6TZHT/0su65mecqSP48q/8PkdxOuUqNOh30zMYAKKBs= X-Received: by 2002:a9d:6357:: with SMTP id y23mr2932410otk.91.1575376481627; Tue, 03 Dec 2019 04:34:41 -0800 (PST) MIME-Version: 1.0 References: <20191203122753.19792-1-zhengxiang9@huawei.com> <20191203122753.19792-2-zhengxiang9@huawei.com> In-Reply-To: <20191203122753.19792-2-zhengxiang9@huawei.com> From: Peter Maydell Date: Tue, 3 Dec 2019 12:34:30 +0000 Message-ID: Subject: Re: [PATCH 1/5] tests: fw_cfg: Rename pc_fw_cfg_* to fw_cfg_* To: Xiang Zheng Cc: Thomas Huth , Laurent Vivier , Paolo Bonzini , =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= , Laszlo Ersek , Gerd Hoffmann , qemu-arm , QEMU Developers , wanghaibin.wang@huawei.com Content-Type: text/plain; charset="UTF-8" X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::344 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 03 Dec 2019 12:34:47 -0000 On Tue, 3 Dec 2019 at 12:29, Xiang Zheng wrote: > > Rename pc_fw_cfg_* to fw_cfg_* to make them common for other > architectures so that we can run fw_cfg tests on aarch64. > > Signed-off-by: Xiang Zheng > -static inline QFWCFG *pc_fw_cfg_init(QTestState *qts) > +static inline QFWCFG *fw_cfg_init(QTestState *qts) > { > - return io_fw_cfg_init(qts, 0x510); > + const char *arch = qtest_get_arch(); > + > + if (!strcmp(arch, "aarch64")) { > + return mm_fw_cfg_init(qts, 0x09020000); > + } else { > + return io_fw_cfg_init(qts, 0x510); > + } Presence and address of the fw_cfg device depends on the machine type, not the architecture, so is it possible to write this so that it varies by machine type, rather than by guest arch ? There should also presumably be a fallback path for "fw_cfg not present here", I suppose. thanks -- PMM From MAILER-DAEMON Tue Dec 03 07:47:57 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1ic7av-0002JA-Ik for mharc-qemu-arm@gnu.org; Tue, 03 Dec 2019 07:47:57 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:45207) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ic7ab-0002El-9z for qemu-arm@nongnu.org; Tue, 03 Dec 2019 07:47:54 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ic7aW-0005Ld-Vb for qemu-arm@nongnu.org; Tue, 03 Dec 2019 07:47:34 -0500 Received: from out2-smtp.messagingengine.com ([66.111.4.26]:45533) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1ic7aW-0004x5-4l; Tue, 03 Dec 2019 07:47:32 -0500 Received: from compute4.internal (compute4.nyi.internal [10.202.2.44]) by mailout.nyi.internal (Postfix) with ESMTP id 77D5A223CC; Tue, 3 Dec 2019 07:47:26 -0500 (EST) Received: from imap2 ([10.202.2.52]) by compute4.internal (MEProxy); Tue, 03 Dec 2019 07:47:26 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=aj.id.au; h= mime-version:message-id:in-reply-to:references:date:from:to:cc :subject:content-type:content-transfer-encoding; s=fm1; bh=ACyzv u8ZpyXA+VrmBvFkqbpxOAuy1IEd+giaDT4RTUU=; b=mtJL4cwMAKcQfuAhUeg0G I48vGdUdfrMLeBwdL0xpQLX0rpC8xdgfRF3DiePAiDJN/HerMWiIlJ8E3tA1uFeY D5N/2N+vu9G2fepnub8Vo/esgIoEr9vZuEQREgOdCYDr77nyhEx7wte6YeYtlcGU U5IW5EYGK9TcdjOwq6det43kh2e2wf+aK90B3B5vLBRgJyJ6zV4CfIFgDi8YMc/t kcuTf16G38dX7rp2BhlXkOT3PMZCsIa8Yhj+qMlWdYhGt6Tqriou24nYVQVdZqTW n8YOo7WQ+Gbp92/vy7YD8sDFMMTpLWPeB5Dzwu5Gt1eJv/46IRP/vlQFvfel9/ma Q== DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d= messagingengine.com; h=cc:content-transfer-encoding:content-type :date:from:in-reply-to:message-id:mime-version:references :subject:to:x-me-proxy:x-me-proxy:x-me-sender:x-me-sender :x-sasl-enc; s=fm1; bh=ACyzvu8ZpyXA+VrmBvFkqbpxOAuy1IEd+giaDT4RT UU=; b=Xq592oAbWL8is3ySXBuzMXG7fILlblARzoO3uDhxow79/26coJ/+gMZX8 AFmJYGpMkGFhS+V6KHKYkzfvi+hVE472hddL2TOfpwC4LEackCuxJ7pnhy4QHl7o nNo5TAh/+NFFY2+Fo2k8P7Y8G8W6394xatiolsNPqFQiSS5rxKUNYruegs4IyeH3 Fhr1mzby1oAqKmxSacpUBz48TbK5lqVh01Krsm3Kg1a3mhsYxfu4gNREAjJLuO4A nKQigtSF0mt4xogw/nRWZinmeTT5ZNgBPwfcB5ADkjD0siK26//jeOdp0L+JD5RP W6tcOU1hutzTw2Bpb4Q3TuibYtysw== X-ME-Sender: X-ME-Proxy-Cause: gggruggvucftvghtrhhoucdtuddrgedufedrudejjedggeehucetufdoteggodetrfdotf fvucfrrhhofhhilhgvmecuhfgrshhtofgrihhlpdfqfgfvpdfurfetoffkrfgpnffqhgen uceurghilhhouhhtmecufedttdenucesvcftvggtihhpihgvnhhtshculddquddttddmne cujfgurhepofgfggfkjghffffhvffutgfgsehtqhertderreejnecuhfhrohhmpedftehn ughrvgifucflvghffhgvrhihfdcuoegrnhgurhgvfiesrghjrdhiugdrrghuqeenucfrrg hrrghmpehmrghilhhfrhhomheprghnughrvgifsegrjhdrihgurdgruhenucevlhhushht vghrufhiiigvpedt X-ME-Proxy: Received: by mailuser.nyi.internal (Postfix, from userid 501) id 7DA3DE00A2; Tue, 3 Dec 2019 07:47:25 -0500 (EST) X-Mailer: MessagingEngine.com Webmail Interface User-Agent: Cyrus-JMAP/3.1.7-612-g13027cc-fmstable-20191203v1 Mime-Version: 1.0 Message-Id: <4e90d36d-aa13-441f-9298-56f83a5bff6a@www.fastmail.com> In-Reply-To: <283c152b-b1c7-551e-bec0-c087b14de996@redhat.com> References: <20191203041440.6275-1-andrew@aj.id.au> <20191203041440.6275-3-andrew@aj.id.au> <283c152b-b1c7-551e-bec0-c087b14de996@redhat.com> Date: Tue, 03 Dec 2019 23:18:59 +1030 From: "Andrew Jeffery" To: =?UTF-8?Q?Philippe_Mathieu-Daud=C3=A9?= , qemu-arm@nongnu.org Cc: qemu-devel@nongnu.org, "Peter Maydell" , "Richard Henderson" , =?UTF-8?Q?C=C3=A9dric_Le_Goater?= , "Joel Stanley" Subject: Re: [PATCH v2 2/4] target/arm: Abstract the generic timer frequency Content-Type: text/plain;charset=utf-8 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 66.111.4.26 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 03 Dec 2019 12:47:55 -0000 On Tue, 3 Dec 2019, at 16:39, Philippe Mathieu-Daud=C3=A9 wrote: > On 12/3/19 5:14 AM, Andrew Jeffery wrote: > > Prepare for SoCs such as the ASPEED AST2600 whose firmware configure= s > > CNTFRQ to values significantly larger than the static 62.5MHz value > > currently derived from GTIMER_SCALE. As the OS potentially derives i= ts > > timer periods from the CNTFRQ value the lack of support for running > > QEMUTimers at the appropriate rate leads to sticky behaviour in the > > guest. > >=20 > > Substitute the GTIMER_SCALE constant with use of a helper to derive = the > > period from gt_cntfrq stored in struct ARMCPU. Initially set gt_cntf= rq > > to the frequency associated with GTIMER_SCALE so current behaviour i= s > > maintained. > >=20 > > Signed-off-by: Andrew Jeffery > > Reviewed-by: Richard Henderson > > --- > > target/arm/cpu.c | 2 ++ > > target/arm/cpu.h | 10 ++++++++++ > > target/arm/helper.c | 10 +++++++--- > > 3 files changed, 19 insertions(+), 3 deletions(-) > >=20 > > diff --git a/target/arm/cpu.c b/target/arm/cpu.c > > index 7a4ac9339bf9..5698a74061bb 100644 > > --- a/target/arm/cpu.c > > +++ b/target/arm/cpu.c > > @@ -974,6 +974,8 @@ static void arm_cpu_initfn(Object *obj) > > if (tcg_enabled()) { > > cpu->psci_version =3D 2; /* TCG implements PSCI 0.2 */ > > } > > + > > + cpu->gt_cntfrq =3D NANOSECONDS_PER_SECOND / GTIMER_SCALE; > > } > > =20 > > static Property arm_cpu_reset_cbar_property =3D > > diff --git a/target/arm/cpu.h b/target/arm/cpu.h > > index 83a809d4bac4..666c03871fdf 100644 > > --- a/target/arm/cpu.h > > +++ b/target/arm/cpu.h > > @@ -932,8 +932,18 @@ struct ARMCPU { > > */ > > DECLARE_BITMAP(sve_vq_map, ARM_MAX_VQ); > > DECLARE_BITMAP(sve_vq_init, ARM_MAX_VQ); > > + > > + /* Generic timer counter frequency, in Hz */ > > + uint64_t gt_cntfrq; >=20 > You can also explicit the unit by calling it 'gt_cntfrq_hz'. Fair call, I'll fix that. >=20 > > }; > > =20 > > +static inline unsigned int gt_cntfrq_period_ns(ARMCPU *cpu) > > +{ > > + /* XXX: Could include qemu/timer.h to get NANOSECONDS_PER_SECON= D? */ >=20 > Why inline this call? I doubt there is a significant performance gain.= It wasn't so much performance. It started out as a macro for a simple ca= lculation because I didn't want to duplicate it across a number of places, then I = wanted type safety for the pointer so I switched the macro in the header to an inli= ne function. So it is an evolution of the patch rather than something that came from an = explicit goal of e.g. performance. Andrew From MAILER-DAEMON Tue Dec 03 07:58:48 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1ic7lQ-0005bg-OS for mharc-qemu-arm@gnu.org; Tue, 03 Dec 2019 07:58:48 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:43843) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ic7lI-0005a1-Sl for qemu-arm@nongnu.org; Tue, 03 Dec 2019 07:58:46 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ic7lE-00042Z-8q for qemu-arm@nongnu.org; Tue, 03 Dec 2019 07:58:37 -0500 Received: from out3-smtp.messagingengine.com ([66.111.4.27]:33831) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1ic7lC-0003mP-Sp; Tue, 03 Dec 2019 07:58:36 -0500 Received: from compute4.internal (compute4.nyi.internal [10.202.2.44]) by mailout.nyi.internal (Postfix) with ESMTP id 2675C22434; Tue, 3 Dec 2019 07:58:32 -0500 (EST) Received: from imap2 ([10.202.2.52]) by compute4.internal (MEProxy); Tue, 03 Dec 2019 07:58:32 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=aj.id.au; h= mime-version:message-id:in-reply-to:references:date:from:to:cc :subject:content-type:content-transfer-encoding; s=fm1; bh=gmcRl dLVl4I/fOLntbCUdmtMLEf8OQ0bpPWIabSstiY=; b=J0XOrd6BnoTOajNzODzlY 0VbixE3gQsvO8DIaJYbS3YS0WTVOBu/csGCOE/uEeNXop7J4L7VAW9g5LLPqGybz kxMq16dH4oGnySU/x6GQyU3kb6xK+s4zNpDCCgnVgSa6KEgMY4DAZDLmlX0RsltL SjXHqWGs7FvUpSo5/H8Ij61luMez9vd2D4Lfdwd/cGHtjc8EicrAiS5Xu/lZHSfN Rq0Kdn6yZDAdEY0UmeWQtk0QydebKRmwi8P9HXQZuFwkDjQwEJHyBv4SLrsry+o1 xbuhlVY+zL3QP0uRJorGBMUekBO0z3DS1n7Rd7c8ztSjldT9mvnYUGnNin7mRdld g== DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d= messagingengine.com; h=cc:content-transfer-encoding:content-type :date:from:in-reply-to:message-id:mime-version:references :subject:to:x-me-proxy:x-me-proxy:x-me-sender:x-me-sender :x-sasl-enc; s=fm1; bh=gmcRldLVl4I/fOLntbCUdmtMLEf8OQ0bpPWIabSst iY=; b=aPSc1UxfLKBksK7HlqQmFXmkdTbA5GJcRUq9GhvBeiM9CUM0zOmdeTR3W COGoraFXemiTRIG08FVxqKHKEUpFsITcDKBo3Yb9ERF6SLIE5ckaJR/vz7cy4Z29 jbaCH3GanIxqsKt4vJ6JzDOExkcbJQkDu+lse8v4yXH8xkZF4lWJuHPMTE5VVQ5o gS+RUnicy5N+bXUhb6rm1Wfm2cBCkMuaPZudSk+bh/srbHru+pudvKlxRC13ifCm 9yivNJBAGe/S+9Pg/x8wmiNY9h/rA6yTTPDnn+o7KuOZrqF9+CtSYRTUxKHSQBIs OxPiy4mbCWMl8kFiVa8X1DvUy5avg== X-ME-Sender: X-ME-Proxy-Cause: gggruggvucftvghtrhhoucdtuddrgedufedrudejjedggeekucetufdoteggodetrfdotf fvucfrrhhofhhilhgvmecuhfgrshhtofgrihhlpdfqfgfvpdfurfetoffkrfgpnffqhgen uceurghilhhouhhtmecufedttdenucesvcftvggtihhpihgvnhhtshculddquddttddmne cujfgurhepofgfggfkjghffffhvffutgfgsehtqhertderreejnecuhfhrohhmpedftehn ughrvgifucflvghffhgvrhihfdcuoegrnhgurhgvfiesrghjrdhiugdrrghuqeenucfrrg hrrghmpehmrghilhhfrhhomheprghnughrvgifsegrjhdrihgurdgruhenucevlhhushht vghrufhiiigvpedt X-ME-Proxy: Received: by mailuser.nyi.internal (Postfix, from userid 501) id 52010E00A3; Tue, 3 Dec 2019 07:58:31 -0500 (EST) X-Mailer: MessagingEngine.com Webmail Interface User-Agent: Cyrus-JMAP/3.1.7-612-g13027cc-fmstable-20191203v1 Mime-Version: 1.0 Message-Id: <915ab8c8-5cd9-43fa-8abf-e1ea8c91c807@www.fastmail.com> In-Reply-To: References: <20191203041440.6275-1-andrew@aj.id.au> <20191203041440.6275-4-andrew@aj.id.au> Date: Tue, 03 Dec 2019 23:29:54 +1030 From: "Andrew Jeffery" To: =?UTF-8?Q?Philippe_Mathieu-Daud=C3=A9?= , qemu-arm@nongnu.org Cc: qemu-devel@nongnu.org, "Peter Maydell" , "Richard Henderson" , =?UTF-8?Q?C=C3=A9dric_Le_Goater?= , "Joel Stanley" Subject: =?UTF-8?Q?Re:_[PATCH_v2_3/4]_target/arm:_Prepare_generic_timer_for_per-p?= =?UTF-8?Q?latform_CNTFRQ?= Content-Type: text/plain;charset=utf-8 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 66.111.4.27 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 03 Dec 2019 12:58:46 -0000 On Tue, 3 Dec 2019, at 16:49, Philippe Mathieu-Daud=C3=A9 wrote: > On 12/3/19 5:14 AM, Andrew Jeffery wrote: > > The ASPEED AST2600 clocks the generic timer at the rate of HPLL. On > > recent firmwares this is at 1125MHz, which is considerably quicker t= han > > the assumed 62.5MHz of the current generic timer implementation. The= > > delta between the value as read from CNTFRQ and the true rate of the= > > underlying QEMUTimer leads to sticky behaviour in AST2600 guests. > >=20 > > Add a feature-gated property exposing CNTFRQ for ARM CPUs providing = the > > generic timer. This allows platforms to configure CNTFRQ (and the > > associated QEMUTimer) to the appropriate frequency prior to starting= the > > guest. > >=20 > > As the platform can now determine the rate of CNTFRQ we're exposed t= o > > limitations of QEMUTimer that didn't previously materialise: In the > > course of emulation we need to arbitrarily and accurately convert > > between guest ticks and time, but we're constrained by QEMUTimer's u= se > > of an integer scaling factor. The effect is QEMUTimer cannot exactly= > > capture the period of frequencies that do not cleanly divide > > NANOSECONDS_PER_SECOND for scaling ticks to time. As such, provide a= n > > equally inaccurate scaling factor for scaling time to ticks so at le= ast > > a self-consistent inverse relationship holds. > >=20 > > Signed-off-by: Andrew Jeffery > > Reviewed-by: Richard Henderson > > --- > > target/arm/cpu.c | 43 +++++++++++++++++++++++++++++++++--------= -- > > target/arm/cpu.h | 18 ++++++++++++++++++ > > target/arm/helper.c | 9 ++++++++- > > 3 files changed, 59 insertions(+), 11 deletions(-) > >=20 > > diff --git a/target/arm/cpu.c b/target/arm/cpu.c > > index 5698a74061bb..f186019a77fd 100644 > > --- a/target/arm/cpu.c > > +++ b/target/arm/cpu.c > > @@ -974,10 +974,12 @@ static void arm_cpu_initfn(Object *obj) > > if (tcg_enabled()) { > > cpu->psci_version =3D 2; /* TCG implements PSCI 0.2 */ > > } > > - > > - cpu->gt_cntfrq =3D NANOSECONDS_PER_SECOND / GTIMER_SCALE; > > } > > =20 > > +static Property arm_cpu_gt_cntfrq_property =3D > > + DEFINE_PROP_UINT64("cntfrq", ARMCPU, gt_cntfrq, > > + NANOSECONDS_PER_SECOND / GTIMER_SCAL= E); > > + > > static Property arm_cpu_reset_cbar_property =3D > > DEFINE_PROP_UINT64("reset-cbar", ARMCPU, reset_cbar, 0= ); > > =20 > > @@ -1174,6 +1176,11 @@ void arm_cpu_post_init(Object *obj) > > =20 > > qdev_property_add_static(DEVICE(obj), &arm_cpu_cfgend_property= , > > &error_abort); > > + > > + if (arm_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER)) { > > + qdev_property_add_static(DEVICE(cpu), &arm_cpu_gt_cntfrq_pr= operty, > > + &error_abort); > > + } > > } > > =20 > > static void arm_cpu_finalizefn(Object *obj) > > @@ -1253,14 +1260,30 @@ static void arm_cpu_realizefn(DeviceState *d= ev, Error **errp) > > } > > } > > =20 > > - cpu->gt_timer[GTIMER_PHYS] =3D timer_new(QEMU_CLOCK_VIRTUAL, GT= IMER_SCALE, > > - arm_gt_ptimer_cb, cpu); > > - cpu->gt_timer[GTIMER_VIRT] =3D timer_new(QEMU_CLOCK_VIRTUAL, GT= IMER_SCALE, > > - arm_gt_vtimer_cb, cpu); > > - cpu->gt_timer[GTIMER_HYP] =3D timer_new(QEMU_CLOCK_VIRTUAL, GTI= MER_SCALE, > > - arm_gt_htimer_cb, cpu); > > - cpu->gt_timer[GTIMER_SEC] =3D timer_new(QEMU_CLOCK_VIRTUAL, GTI= MER_SCALE, > > - arm_gt_stimer_cb, cpu); > > + > > + { > > + uint64_t scale; >=20 > Apparently you have to use this odd indent due to the '#ifndef=20 > CONFIG_USER_ONLY'. Well, acceptable. It's the indent associated with the block scope for the scale variable t= o limit its lifetime to where I needed it. >=20 > > + > > + if (arm_feature(env, ARM_FEATURE_GENERIC_TIMER)) { > > + if (!cpu->gt_cntfrq) { > > + error_setg(errp, "Invalid CNTFRQ: %"PRId64"Hz", > > + cpu->gt_cntfrq); > > + return; > > + } > > + scale =3D gt_cntfrq_period_ns(cpu); > > + } else { > > + scale =3D GTIMER_SCALE; > > + } > > + > > + cpu->gt_timer[GTIMER_PHYS] =3D timer_new(QEMU_CLOCK_VIRTUAL= , scale, > > + arm_gt_ptimer_cb, cp= u); > > + cpu->gt_timer[GTIMER_VIRT] =3D timer_new(QEMU_CLOCK_VIRTUAL= , scale, > > + arm_gt_vtimer_cb, cp= u); > > + cpu->gt_timer[GTIMER_HYP] =3D timer_new(QEMU_CLOCK_VIRTUAL,= scale, > > + arm_gt_htimer_cb, cpu= ); > > + cpu->gt_timer[GTIMER_SEC] =3D timer_new(QEMU_CLOCK_VIRTUAL,= scale, > > + arm_gt_stimer_cb, cpu= ); > > + } > > #endif > > =20 > > cpu_exec_realizefn(cs, &local_err); > > diff --git a/target/arm/cpu.h b/target/arm/cpu.h > > index 666c03871fdf..0bcd13dcac81 100644 > > --- a/target/arm/cpu.h > > +++ b/target/arm/cpu.h > > @@ -939,6 +939,24 @@ struct ARMCPU { > > =20 > > static inline unsigned int gt_cntfrq_period_ns(ARMCPU *cpu) > > { > > + /* > > + * The exact approach to calculating guest ticks is: > > + * > > + * muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), cpu->gt_= cntfrq, > > + * NANOSECONDS_PER_SECOND); > > + * > > + * We don't do that. Rather we intentionally use integer divisi= on > > + * truncation below and in the caller for the conversion of hos= t monotonic > > + * time to guest ticks to provide the exact inverse for the sem= antics of > > + * the QEMUTimer scale factor. QEMUTimer's scale facter is an i= nteger, so > > + * it loses precision when representing frequencies where > > + * `(NANOSECONDS_PER_SECOND % cpu->gt_cntfrq) > 0` holds. Faili= ng to > > + * provide an exact inverse leads to scheduling timers with neg= ative > > + * periods, which in turn leads to sticky behaviour in the gues= t. > > + * > > + * Finally, CNTFRQ is effectively capped at 1GHz to ensure our = scale factor > > + * cannot become zero. > > + */ >=20 > This comment belong to the previous patch. Sort of, but also sort of not. We don't expose the limitation until this= patch as NANOSECONDS_PER_SECOND is an integer multiple of GTIMER_SCALE, which is what gt_cntfrq is set to until we add the property to configure it to= arbitrary values in this patch. So I added the comment in this patch rather than t= he previous one which adds the code. Andrew From MAILER-DAEMON Tue Dec 03 08:01:46 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1ic7oI-0006JC-BG for mharc-qemu-arm@gnu.org; Tue, 03 Dec 2019 08:01:46 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:57241) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ic7oF-0006HU-BH for qemu-arm@nongnu.org; Tue, 03 Dec 2019 08:01:45 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ic7o5-00043b-5z for qemu-arm@nongnu.org; Tue, 03 Dec 2019 08:01:37 -0500 Received: from us-smtp-2.mimecast.com ([205.139.110.61]:46618 helo=us-smtp-delivery-1.mimecast.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1ic7o1-0003uz-HP for qemu-arm@nongnu.org; Tue, 03 Dec 2019 08:01:30 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1575378086; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references:openpgp:openpgp; bh=2fFnz/Aj1Pp+kEJTzCgNJw48MFTE8Uwes9027KPoL0E=; b=Gge1iNbo8exZzMlKDCpWL8Ffe/8h9RZes+gLGBk2+qLj19liXd5l96ApU98A7BmrK6Dnlh fA5LwOca5hiXTnrWCamyBAn/sVR0Gi90aZ85acbm8RuhSiaDh1iRtlCK7OgIyoPFXNmdRS 20tixW5RENOwr1qVhSQVi5kIqhhUs7s= Received: from mimecast-mx01.redhat.com (mimecast-mx01.redhat.com [209.132.183.4]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-100-nbF3ed9yMV-7zY4bN5cvjg-1; Tue, 03 Dec 2019 08:01:23 -0500 Received: from smtp.corp.redhat.com (int-mx03.intmail.prod.int.phx2.redhat.com [10.5.11.13]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx01.redhat.com (Postfix) with ESMTPS id AAAF08024CC; Tue, 3 Dec 2019 13:01:22 +0000 (UTC) Received: from thuth.remote.csb (ovpn-116-176.ams2.redhat.com [10.36.116.176]) by smtp.corp.redhat.com (Postfix) with ESMTPS id 3267667E5D; Tue, 3 Dec 2019 13:01:20 +0000 (UTC) Subject: Re: [PATCH 0/5] tests: Enable fw_cfg tests on AArch64 To: Xiang Zheng , peter.maydell@linaro.org, lvivier@redhat.com Cc: pbonzini@redhat.com, philmd@redhat.com, lersek@redhat.com, kraxel@redhat.com, qemu-arm@nongnu.org, qemu-devel@nongnu.org, wanghaibin.wang@huawei.com References: <20191203122753.19792-1-zhengxiang9@huawei.com> From: Thomas Huth Openpgp: preference=signencrypt Message-ID: Date: Tue, 3 Dec 2019 14:01:18 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101 Thunderbird/60.9.0 MIME-Version: 1.0 In-Reply-To: <20191203122753.19792-1-zhengxiang9@huawei.com> Content-Language: en-US X-Scanned-By: MIMEDefang 2.79 on 10.5.11.13 X-MC-Unique: nbF3ed9yMV-7zY4bN5cvjg-1 X-Mimecast-Spam-Score: 0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: 7bit X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 205.139.110.61 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 03 Dec 2019 13:01:45 -0000 On 03/12/2019 13.27, Xiang Zheng wrote: > There are quite a few tests disabled on AArch64 such as fw_cfg-tests. > This patch series fix some problems in test code and adapt it to > virt machine. > > Xiang Zheng (5): > tests: fw_cfg: Rename pc_fw_cfg_* to fw_cfg_* > tests: fw_cfg: Support read/write of fw_cfg registers on aarch64 > tests: fw_cfg: Use virt as default machine in fw_cfg-test.c > hw/arm/virt: Add FW_CFG_RAM_SIZE and FW_CFG_MAX_CPUS into fw_cfg > tests: Enable fw_cfg test on aarch64 Hi, this breaks "make check-qtest-ppc64": TEST check-qtest-ppc64: tests/boot-order-test ** ERROR:tests/boot-order-test.c:40:test_a_boot_order: assertion failed (actual == expected_boot): (0x00000000 == 0x00000063) Please make sure that "make check" continuous to work with all other targets, too. Thanks, Thomas From MAILER-DAEMON Tue Dec 03 08:42:37 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1ic8Rp-0005Sk-Ex for mharc-qemu-arm@gnu.org; Tue, 03 Dec 2019 08:42:37 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:53643) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ic8Rl-0005MR-UY for qemu-arm@nongnu.org; Tue, 03 Dec 2019 08:42:35 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ic8RX-0003ke-MH for qemu-arm@nongnu.org; Tue, 03 Dec 2019 08:42:23 -0500 Received: from mail-oi1-x244.google.com ([2607:f8b0:4864:20::244]:36996) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ic8RX-0003Ym-FO for qemu-arm@nongnu.org; Tue, 03 Dec 2019 08:42:19 -0500 Received: by mail-oi1-x244.google.com with SMTP id x195so3287543oix.4 for ; Tue, 03 Dec 2019 05:42:17 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=soWhI6No3tGQBHEkzHvxFefPjyrYmqm4pcmKH6TBqBM=; b=ppgXXhsXDNWhUOFl0X91JCfyO9UwZrGH1VEYHpZE7vzkNRqS+w29S9V2E3OwCl+kB4 nL/csPgdpy9XzSpFsLO6ZqH32x6hFZBxKXxXpgDtPXoRwZLV0SD/RRlBzqa4305T7RYQ 53RPa9ZpkEQcwBQlZr+y4YMjN8YIxetAYSJ1Nd2f5JoLhdpLuELu5+f107GUpddyg9fN EsIvUiRAaiTNvPAwNbXswlwqCGiJY46irap2tVAQwH04+h+5c5VerKUVFF21515ZGkZu eSvqBRiIhb0CU/+X5Lm0aw5fQwYlZi7a7gHTT22DVH9R9B/mQ6SyWH9FiF9MiqT7zfJQ a6lg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=soWhI6No3tGQBHEkzHvxFefPjyrYmqm4pcmKH6TBqBM=; b=cf36AhBdWRp6xFalT96ArBrRRoO6AwXh1hgK/5l4lkyC4rpgxakj/BHcxNKv88+ujB Fzq5nsPYYBbmE05RTeRjx66YoMea0GxYO2a/woItprK5vKX//vVQAsTf+NT/QvJ9sjpX /GVmVwE8ddOfFlaWT2mHHjLB13RLjQuWUw3dCNbVykRwwdSSu8nmLnAag5pkENhdyZDp i0rFlB25ZIonmtdTw6C88nYiP6xTeCqu4eRQydvn92cwKlH6dLRKxwdAZp7UQFluXxpV DT2ZydjQnS+Z72lOq/dBp7acMk1jLZipBzkVEBwGvH1xpvkwgzIA3/Glaj72f7ku2aec buIw== X-Gm-Message-State: APjAAAU25dladSHeckXW/V4BvXA7yzSqoDaGOf5mLkdRZ2T/ahZUwvWB Gcw+vOF1nxW4M5M1Yi8vN8EVvrWXdj+oUDQkbNVZoQ== X-Google-Smtp-Source: APXvYqyJvaDmXr0B1uzI4qD5kFYFQUwpFfPbLewWTRqreszcj/OlGI5KT3Nb360adnYHoKaD25Q4ZfA89BleKhZMGrU= X-Received: by 2002:aca:edd5:: with SMTP id l204mr3664271oih.98.1575380536122; Tue, 03 Dec 2019 05:42:16 -0800 (PST) MIME-Version: 1.0 References: <20191011134744.2477-1-richard.henderson@linaro.org> <20191011134744.2477-5-richard.henderson@linaro.org> In-Reply-To: <20191011134744.2477-5-richard.henderson@linaro.org> From: Peter Maydell Date: Tue, 3 Dec 2019 13:42:05 +0000 Message-ID: Subject: Re: [PATCH v5 04/22] target/arm: Add helper_mte_check{1,2,3} To: Richard Henderson Cc: QEMU Developers , qemu-arm Content-Type: text/plain; charset="UTF-8" X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::244 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 03 Dec 2019 13:42:36 -0000 On Fri, 11 Oct 2019 at 14:49, Richard Henderson wrote: > > Implements the rules of "PE generation of Checked and Unchecked > accesses" which aren't already implied by TB_FLAGS_MTE_ACTIVE. > Implements the rules of "PE handling of Tag Check Failure". > > Does not implement tag physical address space, so all operations > reduce to unchecked so far. > > Signed-off-by: Richard Henderson > --- > v2: Fix TFSR update. > v3: Split helper_mte_check per {1,2} IAs; take tbi data from translate. > v5: Split helper_mte_check3, the only one that needs a runtime check for tbi. > --- > target/arm/helper-a64.h | 4 + > target/arm/mte_helper.c | 167 +++++++++++++++++++++++++++++++++++++ > target/arm/translate-a64.c | 15 +++- > target/arm/Makefile.objs | 1 + > 4 files changed, 186 insertions(+), 1 deletion(-) > create mode 100644 target/arm/mte_helper.c > > diff --git a/target/arm/helper-a64.h b/target/arm/helper-a64.h > index a915c1247f..a82e21f15a 100644 > --- a/target/arm/helper-a64.h > +++ b/target/arm/helper-a64.h > @@ -102,3 +102,7 @@ DEF_HELPER_FLAGS_3(autda, TCG_CALL_NO_WG, i64, env, i64, i64) > DEF_HELPER_FLAGS_3(autdb, TCG_CALL_NO_WG, i64, env, i64, i64) > DEF_HELPER_FLAGS_2(xpaci, TCG_CALL_NO_RWG_SE, i64, env, i64) > DEF_HELPER_FLAGS_2(xpacd, TCG_CALL_NO_RWG_SE, i64, env, i64) > + > +DEF_HELPER_FLAGS_2(mte_check1, TCG_CALL_NO_WG, i64, env, i64) > +DEF_HELPER_FLAGS_2(mte_check2, TCG_CALL_NO_WG, i64, env, i64) > +DEF_HELPER_FLAGS_3(mte_check3, TCG_CALL_NO_WG, i64, env, i64, i32) > diff --git a/target/arm/mte_helper.c b/target/arm/mte_helper.c > new file mode 100644 > index 0000000000..bbb90cbe86 > --- /dev/null > +++ b/target/arm/mte_helper.c > @@ -0,0 +1,167 @@ > +/* > + * ARM v8.5-MemTag Operations > + * > + * Copyright (c) 2019 Linaro, Ltd. > + * > + * This library is free software; you can redistribute it and/or > + * modify it under the terms of the GNU Lesser General Public > + * License as published by the Free Software Foundation; either > + * version 2.1 of the License, or (at your option) any later version. > + * > + * This library is distributed in the hope that it will be useful, > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU > + * Lesser General Public License for more details. > + * > + * You should have received a copy of the GNU Lesser General Public > + * License along with this library; if not, see . > + */ > + > +#include "qemu/osdep.h" > +#include "cpu.h" > +#include "internals.h" > +#include "exec/exec-all.h" > +#include "exec/cpu_ldst.h" > +#include "exec/helper-proto.h" > + > + > +static int get_allocation_tag(CPUARMState *env, uint64_t ptr, uintptr_t ra) > +{ > + /* Tag storage not implemented. */ > + return -1; > +} > + > +static int allocation_tag_from_addr(uint64_t ptr) > +{ > + ptr += 1ULL << 55; /* carry ptr[55] into ptr[59:56]. */ > + return extract64(ptr, 56, 4); What's the carry-bit-55 logic for? The pseudocode AArch64.AllocationTagFromAddress just returns bits [59:56]. > +} > + > +/* > + * Perform a checked access for MTE. > + * On arrival, TBI is known to enabled, as is allocation_tag_access_enabled. "to be" > + */ > +static uint64_t do_mte_check(CPUARMState *env, uint64_t dirty_ptr, > + uint64_t clean_ptr, uint32_t select, > + uintptr_t ra) > +{ > + ARMMMUIdx stage1 = arm_stage1_mmu_idx(env); > + int ptr_tag, mem_tag; > + > + /* > + * If TCMA is enabled, then physical tag 0 is unchecked. > + * Note the rules in D6.8.1 are written with logical tags, where > + * the corresponding physical tag rule is simpler: equal to 0. > + * We will need the physical tag below anyway. > + */ This reads a bit oddly, because (in the final version of the spec) physical and logical tags are identical (AArch64.PhysicalTag() just returns bits [59:56] of the vaddr). > + ptr_tag = allocation_tag_from_addr(dirty_ptr); > + if (ptr_tag == 0) { > + ARMVAParameters p = aa64_va_parameters(env, dirty_ptr, stage1, true); > + if (p.tcma) { > + return clean_ptr; > + } > + } I don't think this logic gets the "regime has two address ranges" case correct. For a two-address-range translation regime (where TCR_ELx has TCMA0 and TCMA1 bits, rather than just a single TCMA bit), then the 'select' argument to this function needs to be involved, because we should do a tag-unchecked access if: * addr[59:55]==0b00000 (ie select == 0 and ptr_tag == 0) and TCR_ELx.TCMA0 is set * addr[59:55]==0b11111 (ie select == 1 and ptr_tag == 0xf) and TCR_ELx.TCMA1 is set (the pseudocode for this is in AArch64.AccessTagIsChecked(), and the TCR_EL1.TCMA[01] bit definitions agree; the text in D6.8.1 appears to be confused.) > + > + /* > + * If an access is made to an address that does not provide tag > + * storage, the result is IMPLEMENTATION DEFINED. We choose to > + * treat the access as unchecked. > + * This is similar to MemAttr != Tagged, which are also unchecked. > + */ > + mem_tag = get_allocation_tag(env, clean_ptr, ra); > + if (mem_tag < 0) { > + return clean_ptr; > + } > + > + /* If the tags do not match, the tag check operation fails. */ > + if (unlikely(ptr_tag != mem_tag)) { > + int el, regime_el, tcf; > + uint64_t sctlr; > + > + el = arm_current_el(env); > + regime_el = (el ? el : 1); /* TODO: ARMv8.1-VHE EL2&0 regime */ We could write this as "regime_el(env, stage1)" if that function wasn't local to helper.c, right ? > + sctlr = env->cp15.sctlr_el[regime_el]; > + if (el == 0) { > + tcf = extract64(sctlr, 38, 2); > + } else { > + tcf = extract64(sctlr, 40, 2); > + } > + > + switch (tcf) { > + case 1: > + /* > + * Tag check fail causes a synchronous exception. > + * > + * In restore_state_to_opc, we set the exception syndrome > + * for the load or store operation. Do that first so we > + * may overwrite that with the syndrome for the tag check. > + */ > + cpu_restore_state(env_cpu(env), ra, true); > + env->exception.vaddress = dirty_ptr; > + raise_exception(env, EXCP_DATA_ABORT, > + syn_data_abort_no_iss(el != 0, 0, 0, 0, 0, 0x11), > + exception_target_el(env)); > + /* noreturn; fall through to assert anyway */ hopefully this fallthrough comment syntax doesn't confuse any of our compilers/static analyzers... > + > + case 0: > + /* > + * Tag check fail does not affect the PE. > + * We eliminate this case by not setting MTE_ACTIVE > + * in tb_flags, so that we never make this runtime call. > + */ > + g_assert_not_reached(); > + > + case 2: > + /* Tag check fail causes asynchronous flag set. */ > + env->cp15.tfsr_el[regime_el] |= 1 << select; Won't this incorrectly accumulate tagfails for EL0 into TFSR_EL1 rather than TFSRE0_EL1 ? I think you want "[el]". > + break; > + > + default: > + /* Case 3: Reserved. */ > + qemu_log_mask(LOG_GUEST_ERROR, > + "Tag check failure with SCTLR_EL%d.TCF " > + "set to reserved value %d\n", regime_el, tcf); Technically this message is going to be wrong for the case of el==0 (where it's SCTLR_EL1.TCF0, not .TCF, that's been mis-set). > + break; > + } > + } > + > + return clean_ptr; > +} > + > +/* > + * Perform check in translation regime w/single IA range. > + * It is known that TBI is enabled on entry. > + */ > +uint64_t HELPER(mte_check1)(CPUARMState *env, uint64_t dirty_ptr) > +{ > + uint64_t clean_ptr = extract64(dirty_ptr, 0, 56); > + return do_mte_check(env, dirty_ptr, clean_ptr, 0, GETPC()); > +} > + > +/* > + * Perform check in translation regime w/two IA ranges. > + * It is known that TBI is enabled on entry. > + */ > +uint64_t HELPER(mte_check2)(CPUARMState *env, uint64_t dirty_ptr) > +{ > + uint32_t select = extract64(dirty_ptr, 55, 1); > + uint64_t clean_ptr = sextract64(dirty_ptr, 0, 56); > + return do_mte_check(env, dirty_ptr, clean_ptr, select, GETPC()); > +} > + > +/* > + * Perform check in translation regime w/two IA ranges. > + * The TBI argument is the concatenation of TBI1:TBI0. > + */ > +uint64_t HELPER(mte_check3)(CPUARMState *env, uint64_t dirty_ptr, uint32_t tbi) > +{ > + uint32_t select = extract64(dirty_ptr, 55, 1); > + uint64_t clean_ptr = sextract64(dirty_ptr, 0, 56); > + > + if ((tbi >> select) & 1) { > + return do_mte_check(env, dirty_ptr, clean_ptr, select, GETPC()); > + } else { > + /* TBI is disabled; the access is unchecked. */ > + return dirty_ptr; > + } > +} > diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c > index 62bdf50796..8e4fea6b4c 100644 > --- a/target/arm/translate-a64.c > +++ b/target/arm/translate-a64.c > @@ -214,7 +214,20 @@ static void gen_a64_set_pc(DisasContext *s, TCGv_i64 src) > static TCGv_i64 clean_data_tbi(DisasContext *s, TCGv_i64 addr) > { > TCGv_i64 clean = new_tmp_a64(s); > - gen_top_byte_ignore(s, clean, addr, s->tbid); > + > + /* Note that s->mte_active already includes a check for s->tbid != 0. */ > + if (!s->mte_active) { > + gen_top_byte_ignore(s, clean, addr, s->tbid); > + } else if (!regime_has_2_ranges(s->mmu_idx)) { > + gen_helper_mte_check1(clean, cpu_env, addr); > + } else if (s->tbid == 3) { > + /* Both TBI1:TBI0 are set; no need to check at runtime. */ > + gen_helper_mte_check2(clean, cpu_env, addr); > + } else { > + TCGv_i32 tbi = tcg_const_i32(s->tbid); > + gen_helper_mte_check3(clean, cpu_env, addr, tbi); > + tcg_temp_free_i32(tbi); > + } > return clean; > } > > diff --git a/target/arm/Makefile.objs b/target/arm/Makefile.objs > index cf26c16f5f..8fd7d086c8 100644 > --- a/target/arm/Makefile.objs > +++ b/target/arm/Makefile.objs > @@ -67,3 +67,4 @@ obj-$(CONFIG_SOFTMMU) += psci.o > obj-$(TARGET_AARCH64) += translate-a64.o helper-a64.o > obj-$(TARGET_AARCH64) += translate-sve.o sve_helper.o > obj-$(TARGET_AARCH64) += pauth_helper.o > +obj-$(TARGET_AARCH64) += mte_helper.o > -- > 2.17.1 thanks -- PMM From MAILER-DAEMON Tue Dec 03 09:08:11 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1ic8qZ-0002JP-E6 for mharc-qemu-arm@gnu.org; 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a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=/CnwmbUFWRsqWL2N14UyvLbg9Cdi2y+1OqJISDKJtjw=; b=oiySnEqevOKv/33Tn/pmVlPIGr58j8kVyuttaKUd0DmDr89PqbiskvTk42fy+t5x46 Q46E2+nOevBJNOTr/4zpXiZbk48+18cqa5FhsLDoD+Gt7wOyRBFt+I3R+x9k9jVOTCXv 0Fsk8g5cL0V0doKkEDW/6J41Nr4Mp4JgUl6BDBz6SWGNu/OApB4udbY/HIP8r9Z1id0F VuWFhPpSl1HoPOFQOp6IbWRT+OMqE6N/TTOKGo89ApmsGBTyGGq1eUuBTYlXyk3MQTPd 9creg9ObyADUy7pU5uDgtCL2htEdFcrcRPj2O30kpP6sjdjUJPZtu5Pg8L2VXTCLFoRr 4AKA== X-Gm-Message-State: APjAAAVRhsdjRQOCjzxvc7AusJ4qZF0+a2/sOJOC6Fmpk69qNW4ShX6n km5UNRCd2ODLoUwBRR2aUvtmV721dUwJft7ghUdwjA== X-Google-Smtp-Source: APXvYqwFJQnHO1LQABxtrSdrdrgcEOZsuOrGVnYMXS9ocaRVq8MJK+19WwpfY3vXFPZhRRveWvtJx/kYnnR54TXyX1c= X-Received: by 2002:aca:edd5:: with SMTP id l204mr3760486oih.98.1575382075765; Tue, 03 Dec 2019 06:07:55 -0800 (PST) MIME-Version: 1.0 References: <20191011134744.2477-1-richard.henderson@linaro.org> <20191011134744.2477-6-richard.henderson@linaro.org> In-Reply-To: <20191011134744.2477-6-richard.henderson@linaro.org> From: Peter Maydell Date: Tue, 3 Dec 2019 14:07:44 +0000 Message-ID: Subject: Re: [PATCH v5 05/22] target/arm: Suppress tag check for sp+offset To: Richard Henderson Cc: QEMU Developers , qemu-arm Content-Type: text/plain; charset="UTF-8" X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::241 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 03 Dec 2019 14:08:10 -0000 On Fri, 11 Oct 2019 at 14:49, Richard Henderson wrote: > > R0078 specifies that base register, or base register plus immediate > offset, is unchecked when the base register is SP. It looks like rule-numbers didn't make it into the final Arm ARM, so I guess the reference here would just be to section D6.8.1 ? Also, this phrasing is slightly ambiguous about whether the "when base is SP" condition applies to both "base register" and "base register + immediate", or just to the last of the two; the correct reading is the latter of these (and the D6.8.1 Arm ARM text is in error; trust the pseudocode here). We could perhaps say something like: D6.8.1 specifies that accesses are tag-unchecked for loads and stores (including exclusives, compare-and-swap, etc) whose addresses are: * base-register only, where the base register is SP * base-register plus immediate, where the base register is SP (not including reg+imm with writeback addressing forms) and also that literal (pc-relative) loads are tag-unchecked. > Signed-off-by: Richard Henderson > --- > v2: Include writeback addresses as checked. The load-literal case is implicitly tag-unchecked because the address calculation doesn't go via clean_data_tbi(), right? Reviewed-by: Peter Maydell thanks -- PMM From MAILER-DAEMON Tue Dec 03 09:26:40 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1ic98S-0002Xo-R4 for mharc-qemu-arm@gnu.org; Tue, 03 Dec 2019 09:26:40 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:36147) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ic98N-0002V9-DA for qemu-arm@nongnu.org; Tue, 03 Dec 2019 09:26:39 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ic98H-0001Ur-P7 for qemu-arm@nongnu.org; Tue, 03 Dec 2019 09:26:32 -0500 Received: from mail-ot1-x341.google.com ([2607:f8b0:4864:20::341]:41598) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ic98H-0001GG-Fq for qemu-arm@nongnu.org; Tue, 03 Dec 2019 09:26:29 -0500 Received: by mail-ot1-x341.google.com with SMTP id r27so3020998otc.8 for ; Tue, 03 Dec 2019 06:26:25 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=InB6KgY6GCiRdq/2s1tuH0uEgrcaw+iAWR/7DGnezY8=; b=M+LU6PAP0IoEiZ/YA2PoMVzZk9dRZYO/gX6co+4B0LdPxoPBw8vPeZGZqg5cRYUNrK CbKSMgiRNJP/uiuq67s49JexLbrrXsibIbVX7rtBRNG7MlXm3c0cIfEO7Rpj+RXO9//f QMUGNii5kQXU38xL04o1cpKl0TM5oIzzwNFyPdzbWTNGspKogrC9OCDWZFI+8d6tlSJF tkq04PyJ+PrBCdJVmvpHVkKbAarTbqf+ygSDk7WcRRb72eu8/0euBXbwqkA3cU0xbPsc tQcslOxwIrL6ke2fCV9Ca69OqfVrfo5pn9TP+V0mk6TNqQ3X55ODTauwEEAxbYiyd2Gb m9Mg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=InB6KgY6GCiRdq/2s1tuH0uEgrcaw+iAWR/7DGnezY8=; b=kD+2VyMag/F82ujXxtwmlIGOwmpI8totzZa9HOcN6WrT+zHOgQzW0i1kPaHWWEsqWi u6otElOWSVsy4nxLHmivZN3ZQkoXtb7VROwrZYwNcJUJdR+ha4GlaBAdx7HznsILeZwu jkFkIGPjmr1UhSOp8qxRxY7M1vKC8vjmXfbwd9uNMV0dQ/LwwSbqkkOhpgG5Pr01ZnL6 giVC2JGW/VvEBpflAn8N+MHV4YM0Zva9ZpbUnqXnYMbG/8sLi7uC2RopSf1n2lnX+0tC gfivnTeMgN/r8gnMbc+BJ8+nq/FlQUFO19wXY/Z1aStA/SW5dtad9r83sQ+hiamte6SN RcSw== X-Gm-Message-State: APjAAAWehJ9/saZ87Z3SoXGS1qMNJyBDpm2QHGjSVc9lNoXb8ymPQEJU 6mhNmVmyRWflz8PveFYYxtVbBznefBHl2msnQGBfrQ== X-Google-Smtp-Source: APXvYqyPYP54cld6SnY+4wB0EuojskSrW6EpK8sp44ZcmhXDIwYQTrb4mZlx70Dit3uW9tPKqkjbmx8HsGh9JlGGv9Q= X-Received: by 2002:a9d:12d2:: with SMTP id g76mr3400676otg.232.1575383183807; Tue, 03 Dec 2019 06:26:23 -0800 (PST) MIME-Version: 1.0 References: <20191011134744.2477-1-richard.henderson@linaro.org> <20191011134744.2477-7-richard.henderson@linaro.org> In-Reply-To: <20191011134744.2477-7-richard.henderson@linaro.org> From: Peter Maydell Date: Tue, 3 Dec 2019 14:26:13 +0000 Message-ID: Subject: Re: [PATCH v5 06/22] target/arm: Implement the IRG instruction To: Richard Henderson Cc: QEMU Developers , qemu-arm Content-Type: text/plain; charset="UTF-8" X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::341 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 03 Dec 2019 14:26:39 -0000 On Fri, 11 Oct 2019 at 14:49, Richard Henderson wrote: > > Signed-off-by: Richard Henderson > --- > v2: Update to 00eac5. > Merge choose_random_nonexcluded_tag into helper_irg since > that pseudo function no longer exists separately. > --- > target/arm/helper-a64.h | 1 + > target/arm/mte_helper.c | 57 ++++++++++++++++++++++++++++++++++++++ > target/arm/translate-a64.c | 7 +++++ > 3 files changed, 65 insertions(+) > > diff --git a/target/arm/helper-a64.h b/target/arm/helper-a64.h > index a82e21f15a..6ff7f5b756 100644 > --- a/target/arm/helper-a64.h > +++ b/target/arm/helper-a64.h > @@ -106,3 +106,4 @@ DEF_HELPER_FLAGS_2(xpacd, TCG_CALL_NO_RWG_SE, i64, env, i64) > DEF_HELPER_FLAGS_2(mte_check1, TCG_CALL_NO_WG, i64, env, i64) > DEF_HELPER_FLAGS_2(mte_check2, TCG_CALL_NO_WG, i64, env, i64) > DEF_HELPER_FLAGS_3(mte_check3, TCG_CALL_NO_WG, i64, env, i64, i32) > +DEF_HELPER_FLAGS_3(irg, TCG_CALL_NO_RWG, i64, env, i64, i64) > diff --git a/target/arm/mte_helper.c b/target/arm/mte_helper.c > index bbb90cbe86..9848849a91 100644 > --- a/target/arm/mte_helper.c > +++ b/target/arm/mte_helper.c > @@ -37,6 +37,31 @@ static int allocation_tag_from_addr(uint64_t ptr) > return extract64(ptr, 56, 4); > } > > +static int choose_nonexcluded_tag(int tag, int offset, uint16_t exclude) > +{ > + if (exclude == 0xffff) { > + return 0; > + } > + if (offset == 0) { > + while (exclude & (1 << tag)) { > + tag = (tag + 1) & 15; > + } > + } else { > + do { > + do { > + tag = (tag + 1) & 15; > + } while (exclude & (1 << tag)); > + } while (--offset > 0); > + } I feel like this would be easier to review if it matched the logic the pseudocode uses, though I think the end result comes out the same. > + return tag; > +} > + > +static uint64_t address_with_allocation_tag(uint64_t ptr, int rtag) > +{ > + rtag -= extract64(ptr, 55, 1); > + return deposit64(ptr, 56, 4, rtag); This doesn't match AArch64.AddressWithAllocationTag -- the fiddling with bit 55 is unwanted. > +} > + > /* > * Perform a checked access for MTE. > * On arrival, TBI is known to enabled, as is allocation_tag_access_enabled. > @@ -165,3 +190,35 @@ uint64_t HELPER(mte_check3)(CPUARMState *env, uint64_t dirty_ptr, uint32_t tbi) > return dirty_ptr; > } > } > + > +uint64_t HELPER(irg)(CPUARMState *env, uint64_t rn, uint64_t rm) > +{ > + int el = arm_current_el(env); > + uint64_t sctlr = arm_sctlr(env, el); > + int rtag = 0; > + > + if (allocation_tag_access_enabled(env, el, sctlr)) { > + /* > + * Our IMPDEF choice for GCR_EL1.RRND==1 is to behave as if > + * GCR_EL1.RRND==0, always producing deterministic results. > + */ > + uint16_t exclude = extract32(rm | env->cp15.gcr_el1, 0, 16); > + int start = extract32(env->cp15.rgsr_el1, 0, 4); > + int seed = extract32(env->cp15.rgsr_el1, 8, 16); > + int offset, i; > + > + /* RandomTag */ > + for (i = offset = 0; i < 4; ++i) { > + /* NextRandomTagBit */ > + int top = (extract32(seed, 5, 1) ^ extract32(seed, 3, 1) ^ > + extract32(seed, 2, 1) ^ extract32(seed, 0, 1)); > + seed = (top << 15) | (seed >> 1); > + offset |= top << i; > + } > + rtag = choose_nonexcluded_tag(start, offset, exclude); > + > + env->cp15.rgsr_el1 = rtag | (seed << 8); > + } > + > + return address_with_allocation_tag(rn, rtag); > +} > diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c > index 18d45fba87..83d253d67f 100644 > --- a/target/arm/translate-a64.c > +++ b/target/arm/translate-a64.c > @@ -5156,6 +5156,13 @@ static void disas_data_proc_2src(DisasContext *s, uint32_t insn) > case 3: /* SDIV */ > handle_div(s, true, sf, rm, rn, rd); > break; > + case 4: /* IRG */ > + if (sf == 0 || !dc_isar_feature(aa64_mte_insn_reg, s)) { > + goto do_unallocated; > + } > + gen_helper_irg(cpu_reg_sp(s, rd), cpu_env, > + cpu_reg_sp(s, rn), cpu_reg(s, rm)); In the case of "we only have mte_insn_reg, not full MTE", the allocation tag we insert into the address must always be zero, so you could just special case this and emit code inline to clear bits [59:56]. The code as it stands works because we ensure that the guest can't set the SCTLR.*ATA* bits. (That's a bit inconsistent with our approach to the PSTATE.TCO bit, which we do allow a guest to toggle, but the inconsistency is permitted by the architecture.) I'm not sure whether "we only have the EL0 visible bits" is going to be a common enough config to care about to special-case. thanks -- PMM From MAILER-DAEMON Tue Dec 03 10:00:02 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1ic9ek-00088e-RA for mharc-qemu-arm@gnu.org; Tue, 03 Dec 2019 10:00:02 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:40716) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ic9ee-000822-I7 for qemu-arm@nongnu.org; Tue, 03 Dec 2019 09:59:58 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ic9eX-0002G3-W6 for qemu-arm@nongnu.org; Tue, 03 Dec 2019 09:59:51 -0500 Received: from beetle.greensocs.com ([5.135.226.135]:41166) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1ic9eV-0001ld-EQ; Tue, 03 Dec 2019 09:59:48 -0500 Received: from [172.16.11.102] (crumble.bar.greensocs.com [172.16.11.102]) by beetle.greensocs.com (Postfix) with ESMTPSA id 50ED396EF0; Tue, 3 Dec 2019 14:59:39 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=greensocs.com; s=mail; t=1575385179; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=tidNTzqhuJlf4WZkJ82WQRFfpo9g/npgDroo0yBSuJw=; b=XxXuOF/NU+Scg1M65uaSkqLtMoi+Ib7t4WFW9yj79G1R52BvKeeD1C+WlsXhT0+Q39EwEz Bm+NzLz/3DOLZczhtoLlBq3Dezg6FGSFKpHxLdaiOTErdc4w+YI3Cnb41DBHIDp+0iPXiU Ur+MBnfX2gWm6ZxxujmcuVxXCQZL7tU= Subject: Re: [PATCH v6 9/9] hw/arm/xilinx_zynq: connect uart clocks to slcr To: Peter Maydell Cc: QEMU Developers , Mark Burton , "Edgar E. Iglesias" , Alistair Francis , =?UTF-8?Q?Marc-Andr=c3=a9_Lureau?= , Paolo Bonzini , "Daniel P. Berrange" , Eduardo Habkost , qemu-arm , =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= References: <20190904125531.27545-1-damien.hedde@greensocs.com> <20190904125531.27545-10-damien.hedde@greensocs.com> From: Damien Hedde Message-ID: Date: Tue, 3 Dec 2019 15:59:38 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.2.0 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=utf-8 Content-Language: en-US-large Content-Transfer-Encoding: 7bit ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=greensocs.com; s=mail; t=1575385180; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=tidNTzqhuJlf4WZkJ82WQRFfpo9g/npgDroo0yBSuJw=; b=XhJ2pFL27cJQ5kp/MAGV3fXwOROkxugqBglKMQNyS3/WDafmCCzXBcnt/rX68TpAGBXO6R Iy2j20qwfW04d/OXd35EAHEkLG9/KGJBL7EmgMGw/wxRU+9EsWEn+vJsdX3/DGDjAgmT9y uVxnJ8VygfmiMUbwQUcpxyhSoOuSZHo= ARC-Seal: i=1; s=mail; d=greensocs.com; t=1575385180; a=rsa-sha256; cv=none; b=F0f1SvObNKyMvucWXfP+8kSnxjVaUqdaH3BRtZR+s44mJxCQKcWD2CeiTJ8yE7jfQuoMNb RUVW4COGCe69/hZjkZl+2HMmJj9sBd5DCPVrh6nh2cX3V8FkURi9Td5B67GLe1qGAC4uVq NXqShNHPBXntZ8vbFeWFttBBrlLcBTA= ARC-Authentication-Results: i=1; ORIGINATING; auth=pass smtp.auth=damien smtp.mailfrom=damien.hedde@greensocs.com X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 5.135.226.135 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 03 Dec 2019 14:59:59 -0000 On 12/2/19 4:34 PM, Peter Maydell wrote: > On Wed, 4 Sep 2019 at 13:56, Damien Hedde wrote: >> >> Add the connection between the slcr's output clocks and the uarts inputs. >> >> Also add the main board clock 'ps_clk', which is hard-coded to 33.33MHz >> (the default frequency). This clock is used to feed the slcr's input >> clock. >> >> Signed-off-by: Damien Hedde > > Nothing obviously wrong in the body of the patch, but as with > 7 and 8, review from a Xilinx person would be helpful. > > /* board base frequency: 33.333333 MHz */ > #define PS_CLK_FREQUENCY (100 * 1000 * 1000 / 3) > > This is interesting, because it's not an integer... I'll come back > to this topic in a reply to the cover letter in a moment. For this precise case, what I wanted is the resulting integer which I got from the device trees in linux (btw I should probably add this point in comment). Just thought it was more readable this way than "33333333". -- Damien From MAILER-DAEMON Tue Dec 03 10:10:01 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1ic9oP-0002Cd-Kn for mharc-qemu-arm@gnu.org; Tue, 03 Dec 2019 10:10:01 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:45413) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ic9oL-00028C-O7 for qemu-arm@nongnu.org; Tue, 03 Dec 2019 10:09:58 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ic9oD-0007sw-El for qemu-arm@nongnu.org; Tue, 03 Dec 2019 10:09:50 -0500 Received: from mail-pl1-x644.google.com ([2607:f8b0:4864:20::644]:39180) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ic9oD-0007dp-7K for qemu-arm@nongnu.org; Tue, 03 Dec 2019 10:09:49 -0500 Received: by mail-pl1-x644.google.com with SMTP id o9so1810914plk.6 for ; Tue, 03 Dec 2019 07:09:47 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=subject:to:cc:references:from:message-id:date:user-agent :mime-version:in-reply-to:content-language:content-transfer-encoding; bh=dwqjuWSNcNr2c2ServoaUGYVWGdUe1z+kLXm78sBdfk=; b=c5BgjaTasi0oSrcjSWP7J9FOVQ0GIuVXSDMcnNXLXMCTXGBk7oqgN1fiZ+LKDvepsR xG42xzqD4fdhMxLS9tGabMJ8+t48+0hhao7GVhH22ocU1YiKDZJTmlrak+LiL2JplFmF hyAEsJMq5XvCzBn0OfmA3+e7cu2y7Llcu9Ojffb4ktxFedt5KlFVsAjbeZTLSZnNKXJv 6unAuE/PYgSnaqm20q0hj1ap+PwpiCnw93laBN8Zr0gGQINs5/h0YnZioP+NvZdqSUoD YwznEaXQLGL7lDMkJH+m9OVIdDWavWkyx4AbHVFg1+9wYSu4ZMkKHqFIjVC8jqVfVBv8 TV5Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:subject:to:cc:references:from:message-id:date :user-agent:mime-version:in-reply-to:content-language :content-transfer-encoding; bh=dwqjuWSNcNr2c2ServoaUGYVWGdUe1z+kLXm78sBdfk=; b=nf1i/iiZkg8M8MgaJNQm5VVA7xy5AOt1eqOwOHiAMZksZNydicx89CAlMHSuFFFPhx GifP48SvYM+hMkQyyCXnv0DcFkyr5CBGaSxYHjHIOrqLA18HUEPlfFf9sfY5QQcGTYEG M7GrwIKT4IHNHNkAO8OBPbkUVS4sEFzoGwZ1wLIBN1R0xhRa6g/7KSjGVWRzVGtXvRrK oLV1s0gyb7iO0vAFPczSkg/YNaj30iikKhDSUWrPQRMoSgI88BODoG8uA05+HqoxvAqF nlwHoCSN6CncJ3EGdXfvuLT+k4p+wGwys11TbPVtUluMH3AnyH0IJ+fwNbJKkHzCEXE2 PRDA== X-Gm-Message-State: APjAAAU/mBel+iuBNDmThMMN4nrNM3JyreRzdGgcPXWBvlc/I3v7FiSs L4l512Wu2mPArDNwfQIVnjHReY6QjNU= X-Google-Smtp-Source: APXvYqwE9al6I//QLmdV7vIDw7dWoZmsH8w8QgfFs5T4V3Gdr0Jp/5VTsRmdOX+jg+XVNBH4tzL+Cw== X-Received: by 2002:a17:90a:5d17:: with SMTP id s23mr5683766pji.55.1575385784330; Tue, 03 Dec 2019 07:09:44 -0800 (PST) Received: from [192.168.1.11] (97-113-7-119.tukw.qwest.net. [97.113.7.119]) by smtp.gmail.com with ESMTPSA id ce22sm3291383pjb.17.2019.12.03.07.09.43 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 03 Dec 2019 07:09:43 -0800 (PST) Subject: Re: [PATCH v5 02/22] target/arm: Add regime_has_2_ranges To: Peter Maydell Cc: QEMU Developers , qemu-arm References: <20191011134744.2477-1-richard.henderson@linaro.org> <20191011134744.2477-3-richard.henderson@linaro.org> From: Richard Henderson Message-ID: <2687022d-9165-1059-233d-7b42f4f733ef@linaro.org> Date: Tue, 3 Dec 2019 07:09:41 -0800 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.2.1 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 7bit X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::644 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 03 Dec 2019 15:09:58 -0000 On 12/3/19 11:01 AM, Peter Maydell wrote: >> +/* Return true if this address translation regime has two ranges. */ >> +static inline bool regime_has_2_ranges(ARMMMUIdx mmu_idx) >> +{ >> + switch (mmu_idx) { >> + case ARMMMUIdx_S12NSE0: >> + case ARMMMUIdx_S12NSE1: >> + case ARMMMUIdx_S1NSE0: >> + case ARMMMUIdx_S1NSE1: >> + return true; > > Don't S1SE0 and S1SE1 also need to be here? Whoops, yes. I'll need to fix that in the VHE patch set too. r~ From MAILER-DAEMON Tue Dec 03 10:15:32 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1ic9tg-0003ZN-Fu for mharc-qemu-arm@gnu.org; Tue, 03 Dec 2019 10:15:30 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:34559) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ic9tX-0003YC-5m for qemu-arm@nongnu.org; Tue, 03 Dec 2019 10:15:20 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ic9tG-0007Fr-SG for qemu-arm@nongnu.org; Tue, 03 Dec 2019 10:15:12 -0500 Received: from beetle.greensocs.com ([5.135.226.135]:41568) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1ic9tG-00076M-8d; Tue, 03 Dec 2019 10:15:02 -0500 Received: from [172.16.11.102] (crumble.bar.greensocs.com [172.16.11.102]) by beetle.greensocs.com (Postfix) with ESMTPSA id 2B6DE96EF0; Tue, 3 Dec 2019 15:14:59 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=greensocs.com; s=mail; t=1575386099; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=Y+Ssg94fEKiJOG8sgIrMssOBBvuXoDqgaPDRIWUBlzk=; b=eDROYK43rWl8jk4R4vno8u1RqnoVuY9h2qOyw3PqWireUB04dSjBZiT+DaDtc2cyHxqSNf 4BeFYaWuqg3C0hGuKup49ShbK1YaE5lCQFL+iYJMKPGVgoI0xZNMhbzDegPRJYenVILBCp BwhqwiFutPm17QcUaj72z2stW8bUM4I= Subject: Re: [PATCH v6 1/9] hw/core/clock: introduce clock objects To: =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= , qemu-devel@nongnu.org Cc: mark.burton@greensocs.com, edgar.iglesias@gmail.com, alistair@alistair23.me, peter.maydell@linaro.org, marcandre.lureau@redhat.com, pbonzini@redhat.com, berrange@redhat.com, ehabkost@redhat.com, qemu-arm@nongnu.org References: <20190904125531.27545-1-damien.hedde@greensocs.com> <20190904125531.27545-2-damien.hedde@greensocs.com> <50c7d986-1630-e75c-acbd-24330e961dbb@redhat.com> From: Damien Hedde Message-ID: <9f79bf28-ad1a-4df1-76b4-8ecef780bb0f@greensocs.com> Date: Tue, 3 Dec 2019 16:14:58 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.2.0 MIME-Version: 1.0 In-Reply-To: <50c7d986-1630-e75c-acbd-24330e961dbb@redhat.com> Content-Type: text/plain; charset=utf-8 Content-Language: en-US-large ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=greensocs.com; s=mail; t=1575386099; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=Y+Ssg94fEKiJOG8sgIrMssOBBvuXoDqgaPDRIWUBlzk=; b=NIg02mQeNDQW68KKyYyAz3CPscELn+/OUI5jluHGV9nrSQj1p2Ir6XJD0+Hq4E1SPpDDlp V1QsB8y6ZBJygQzQUdCn7cSSNZDzfTSuDccbtoptPQsnRvIWI6iMI9UAGqdEbgzCYwJP6r bPWKMCgr/YJfrbZ+357iYjeCmE8eIAI= ARC-Seal: i=1; s=mail; d=greensocs.com; t=1575386099; a=rsa-sha256; cv=none; b=A9WmEAcAWj3t2Oezb7mTK+faJC8ICDg415eeG5p6iCwKz/+cjXxR7iaXPbULPpmt5DIiO2 GMwAE6pB5huK0YqIACddwpE0Cuqw8ZPkC1hEQJ8iZpyR/IvNDm2dvH7tU9YbfOm+hQBIYE hQhM82X2ltYejI+0mNWj1V+NjoDKBGo= ARC-Authentication-Results: i=1; ORIGINATING; auth=pass smtp.auth=damien smtp.mailfrom=damien.hedde@greensocs.com Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 5.135.226.135 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 03 Dec 2019 15:15:24 -0000 On 11/25/19 2:37 PM, Philippe Mathieu-Daud=C3=A9 wrote: > On 9/4/19 2:55 PM, Damien Hedde wrote: >> Introduce clock objects: ClockIn and ClockOut. >> >> These objects may be used to distribute clocks from an object to sever= al >> other objects. Each ClockIn object contains the current state of the >> clock: the frequency; it allows an object to migrate its input clock >> state >> independently of other objects. >> >> A ClockIn may be connected to a ClockOut so that it receives update, >> through a callback, whenever the Clockout is updated using the >> ClockOut's set function. >> >> This is based on the original work of Frederic Konrad. >> >> Signed-off-by: Damien Hedde >> Reviewed-by: Philippe Mathieu-Daud=C3=A9 >> Tested-by: Philippe Mathieu-Daud=C3=A9 >> --- >> =C2=A0 Makefile.objs=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 |= =C2=A0=C2=A0 1 + >> =C2=A0 hw/core/Makefile.objs |=C2=A0=C2=A0 1 + >> =C2=A0 hw/core/clock.c=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 | 144 +++++= +++++++++++++++++++++++++++++++++++++ >> =C2=A0 hw/core/trace-events=C2=A0 |=C2=A0=C2=A0 6 ++ >> =C2=A0 include/hw/clock.h=C2=A0=C2=A0=C2=A0 | 124 ++++++++++++++++++++= ++++++++++++++++ >> =C2=A0 5 files changed, 276 insertions(+) >> =C2=A0 create mode 100644 hw/core/clock.c >> =C2=A0 create mode 100644 include/hw/clock.h >> >> diff --git a/hw/core/trace-events b/hw/core/trace-events >> index ecf966c314..aa940e268b 100644 >> --- a/hw/core/trace-events >> +++ b/hw/core/trace-events >> @@ -34,3 +34,9 @@ resettable_phase_hold_end(void *obj, int needed) >> "obj=3D%p needed=3D%d" >> =C2=A0 resettable_phase_exit(void *obj, const char *type) "obj=3D%p(%s= )" >> =C2=A0 resettable_phase_exit_end(void *obj, uint32_t count) "obj=3D%p >> count=3D%" PRIu32 >> =C2=A0 resettable_count_underflow(void *obj) "obj=3D%p" >> + >> +# hw/core/clock-port.c >=20 > "# clock.c" >=20 Oups, I missed this one in the renaming. >> + >> +struct ClockIn { >> +=C2=A0=C2=A0=C2=A0 /*< private >*/ >> +=C2=A0=C2=A0=C2=A0 Object parent_obj; >> +=C2=A0=C2=A0=C2=A0 /*< private >*/ >> +=C2=A0=C2=A0=C2=A0 uint64_t frequency; >> +=C2=A0=C2=A0=C2=A0 char *canonical_path; /* clock path cache */ >> +=C2=A0=C2=A0=C2=A0 ClockOut *driver; /* clock output controlling this= clock */ >> +=C2=A0=C2=A0=C2=A0 ClockCallback *callback; /* local callback */ >> +=C2=A0=C2=A0=C2=A0 void *callback_opaque; /* opaque argument for the = callback */ >> +=C2=A0=C2=A0=C2=A0 QLIST_ENTRY(ClockIn) sibling;=C2=A0 /* entry in a = followers list */ >> +}; >> + >> +struct ClockOut { >> +=C2=A0=C2=A0=C2=A0 /*< private >*/ >> +=C2=A0=C2=A0=C2=A0 Object parent_obj; >> +=C2=A0=C2=A0=C2=A0 /*< private >*/ >> +=C2=A0=C2=A0=C2=A0 char *canonical_path; /* clock path cache */ >> +=C2=A0=C2=A0=C2=A0 QLIST_HEAD(, ClockIn) followers; /* list of regist= ered clocks */ >> +}; >=20 > Can we keep the structure definitions opaque in hw/core/clock.c? > If so, clock_get_frequency() can't be inlined anymore. >=20 I think so. Apart from the monitor command (and the inline), nothing requires the structure fields. I suppose we can add a function to access or print the fields to be used by the monitor. I don't have a opinion on this. Damien From MAILER-DAEMON Tue Dec 03 10:28:37 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1icA6P-0000Hb-BP for mharc-qemu-arm@gnu.org; Tue, 03 Dec 2019 10:28:37 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:43608) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1icA6K-0000DI-9L for qemu-arm@nongnu.org; Tue, 03 Dec 2019 10:28:35 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1icA6G-0000P5-Nu for qemu-arm@nongnu.org; Tue, 03 Dec 2019 10:28:30 -0500 Received: from beetle.greensocs.com ([5.135.226.135]:41968) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1icA6D-0000G9-NK; Tue, 03 Dec 2019 10:28:26 -0500 Received: from [172.16.11.102] (crumble.bar.greensocs.com [172.16.11.102]) by beetle.greensocs.com (Postfix) with ESMTPSA id 1E7B096EF0; Tue, 3 Dec 2019 15:28:16 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=greensocs.com; s=mail; t=1575386897; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=yERPzRJQrw1BP5h162NpfWzRvwpbb+McaU1URc4BXlc=; b=ZFbZY0ZzmVolddP5etGi1xVETJbXnQGewqpWk4Ieb/mwEyQGp1kMlyuU7jS1S/Pc7xzE8A zMiRgBsBm3y+Ialwpile/0xPnn/r6VHUNmUwDkobqz92SFNczV+6XTKvM474QcZDpiHPHQ lHUFcQhGi9o4tWwnpiu1x95awyZcRjs= Subject: Re: [PATCH v6 1/9] hw/core/clock: introduce clock objects To: Peter Maydell Cc: QEMU Developers , Mark Burton , "Edgar E. Iglesias" , Alistair Francis , =?UTF-8?Q?Marc-Andr=c3=a9_Lureau?= , Paolo Bonzini , "Daniel P. Berrange" , Eduardo Habkost , qemu-arm , =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= References: <20190904125531.27545-1-damien.hedde@greensocs.com> <20190904125531.27545-2-damien.hedde@greensocs.com> From: Damien Hedde Message-ID: Date: Tue, 3 Dec 2019 16:28:16 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.2.0 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=utf-8 Content-Language: en-US-large Content-Transfer-Encoding: 7bit ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=greensocs.com; s=mail; t=1575386897; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=yERPzRJQrw1BP5h162NpfWzRvwpbb+McaU1URc4BXlc=; b=PPLZUPuNfrmcELa2SaBimi7sz6SO28AzOGtjJ6+lQrJt5Okqx5I3p9FABqL0zGPJ5W6cut 5MV3huYpUTNx4Gkj4/iTcm9DseWuP6sDOiDd7KcK6YQv6fmipGUqE3DMYv6R3yGt3AQOrj BIIwdPTbOLQ0rc1i8cpcS5c/7y5hkmI= ARC-Seal: i=1; s=mail; d=greensocs.com; t=1575386897; a=rsa-sha256; cv=none; b=5XK1zhFzLtTDBCrD31s1z2O09n2QbD4oI9JEQ5/0miQ7+E8xFDIZBDYokdqLuCBJov8vFv QeOaHv5Xu4y/tVLLUYXTVX5gv2y9MVBlyU/hiWb+aNzyqL+re7qYmRA1jSCYOrPhcRZLyM 0+gAG4ZWQro3kLN750LIPJbSOfzi61Y= ARC-Authentication-Results: i=1; ORIGINATING; auth=pass smtp.auth=damien smtp.mailfrom=damien.hedde@greensocs.com X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 5.135.226.135 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 03 Dec 2019 15:28:35 -0000 On 12/2/19 2:42 PM, Peter Maydell wrote: > On Wed, 4 Sep 2019 at 13:56, Damien Hedde wrote: >> >> Introduce clock objects: ClockIn and ClockOut. >> >> These objects may be used to distribute clocks from an object to several >> other objects. Each ClockIn object contains the current state of the >> clock: the frequency; it allows an object to migrate its input clock state >> independently of other objects. >> >> A ClockIn may be connected to a ClockOut so that it receives update, > > "updates" (or "an update") > >> through a callback, whenever the Clockout is updated using the >> ClockOut's set function. >> >> This is based on the original work of Frederic Konrad. >> >> + >> +#define CLOCK_PATH(_clk) (_clk->canonical_path) > > Don't use leading underscores in identifiers, please. ok > >> + >> +void clock_init_frequency(ClockIn *clk, uint64_t freq) >> +{ >> + assert(clk); > > This sort of assert isn't necessary. Asserts are good > when they help to make a bug visible sooner and more > obviously -- when they avoid "something goes wrong > much later on and further from the site of the actual > error". In this case, if the assert was not present > then the code would just segfault on the next line: > >> + >> + clk->frequency = freq; > > which is already a very easy bug to diagnose and > where the offending caller will be in the backtrace. > > If the parameter isn't supposed to be NULL, and the > method doesn't actually do anything that would > dereference it, that might be a good candidate to > assert on. > > The same kind of unnecessary assert is also in some of > the other functions here (and probably in other patches). I'll take a look. > >> diff --git a/include/hw/clock.h b/include/hw/clock.h >> new file mode 100644 >> index 0000000000..fd11202ba4 >> --- /dev/null >> +++ b/include/hw/clock.h >> @@ -0,0 +1,124 @@ >> +#ifndef QEMU_HW_CLOCK_H >> +#define QEMU_HW_CLOCK_H > > All new files need a copyright-and-license comment header (could > you check the rest of the patchset for this, please?). Sure. > >> + > >> +/** >> + * clock_get_frequency: >> + * @clk: the clk to fetch the clock >> + * >> + * @return: the current frequency of @clk in Hz. If @clk is NULL, return 0. >> + */ >> +static inline uint64_t clock_get_frequency(const ClockIn *clk) >> +{ >> + return clk ? clk->frequency : 0; >> +} > > Is there a use case where we want to support "pass in NULL" > rather than just making it a programming error for the caller > to try that ? No, it's probably a remnant of previous version where input and output shared some code. I'll remove it. -- Damien From MAILER-DAEMON Tue Dec 03 10:29:42 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1icA7S-0000bb-R1 for mharc-qemu-arm@gnu.org; Tue, 03 Dec 2019 10:29:42 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:47392) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1icA7L-0000YE-Bc for qemu-arm@nongnu.org; Tue, 03 Dec 2019 10:29:37 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1icA7E-0003iZ-IX for qemu-arm@nongnu.org; Tue, 03 Dec 2019 10:29:30 -0500 Received: from us-smtp-1.mimecast.com ([205.139.110.61]:56163 helo=us-smtp-delivery-1.mimecast.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1icA78-0003bZ-On for qemu-arm@nongnu.org; Tue, 03 Dec 2019 10:29:23 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1575386958; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=WeerkaiTznFWZe+uFrLFBE25ivmPwQ5NX0TUY7VdjnU=; b=Q1+cA51vv7EbACpYpkWsjpbfYqQeGIIjSJEVxmWMiAasIrbzp2KZrg/q/FbVO614Ejg/lp RJjyucd1TdzQRUDbNwkZ7j+jnl7BQb9bOcklPMNKTpf9is5IrS+xk4pzCgQQDiH8r7D7zZ EJKuH7J9shSsSSXNlkTU1XeekvuEeyg= Received: from mail-wm1-f71.google.com (mail-wm1-f71.google.com [209.85.128.71]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-430-NkLAkHsWMk67nQG7SyUGbw-1; Tue, 03 Dec 2019 10:29:17 -0500 Received: by mail-wm1-f71.google.com with SMTP id y133so1055335wmd.8 for ; Tue, 03 Dec 2019 07:29:16 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:subject:to:cc:references:from:message-id:date :user-agent:mime-version:in-reply-to:content-language :content-transfer-encoding; bh=WeerkaiTznFWZe+uFrLFBE25ivmPwQ5NX0TUY7VdjnU=; b=Lcn2sdMEKhZc87W/T0144HN+Q3kwsyEEY8H1I8aP6RaDnbSbxKfOEERSwcpTWsRvkB yjNuHHoYOszDLDjxXt7IH5StCzNVzMBIgoD2qghBZ65nD0TyeYN4kklBc5ciQN/6F+aj dYtGrRDzdyk0e9FEj9DG8Zs534a4kWGjsZ/6jEaxBeh3H8IY60ZtHIftW8yyDazdrGmU 4JrzIN4WUxDPf9yOzI1gJNQoiW7lALJZ4ZjNOnb+ocWLiTaDDdh5ZkLE0k6DkcTHmTGY gGq/6ZhDTukEbJiJ90euRMzs45kWh4m6rg+gN8LZE9k6k+pz+xI55oWx1Md5tCbM6Kn2 68sQ== X-Gm-Message-State: APjAAAUsAAzfDjHxOMny83KnEK2SASmrGSYz3kJJIjJ99cpBjrbQ41A8 YS6GnaXSFaSFK1MWffS/vR9kr0DHHtRPKLBsqPDdO1TEDXqjbx3bc8j65O94teEiHPmmDmsLZFz FcSoAb4WhnmYC X-Received: by 2002:a5d:4acb:: with SMTP id y11mr6035643wrs.106.1575386955687; Tue, 03 Dec 2019 07:29:15 -0800 (PST) X-Google-Smtp-Source: APXvYqz/vvJxh8a4QR3uEQLBa4OwtJoTVRBtcinj837XMBskPpwh+4Pji2CUM5XqlJ+5llaRfTGXzA== X-Received: by 2002:a5d:4acb:: with SMTP id y11mr6035607wrs.106.1575386955402; Tue, 03 Dec 2019 07:29:15 -0800 (PST) Received: from [192.168.1.35] (182.red-88-21-103.staticip.rima-tde.net. [88.21.103.182]) by smtp.gmail.com with ESMTPSA id c1sm3105575wmk.22.2019.12.03.07.29.13 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 03 Dec 2019 07:29:14 -0800 (PST) Subject: Re: [PATCH v6 9/9] hw/arm/xilinx_zynq: connect uart clocks to slcr To: Damien Hedde , Peter Maydell Cc: QEMU Developers , Mark Burton , "Edgar E. Iglesias" , Alistair Francis , =?UTF-8?Q?Marc-Andr=c3=a9_Lureau?= , Paolo Bonzini , "Daniel P. Berrange" , Eduardo Habkost , qemu-arm References: <20190904125531.27545-1-damien.hedde@greensocs.com> <20190904125531.27545-10-damien.hedde@greensocs.com> From: =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= Message-ID: Date: Tue, 3 Dec 2019 16:29:13 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.2.2 MIME-Version: 1.0 In-Reply-To: Content-Language: en-US X-MC-Unique: NkLAkHsWMk67nQG7SyUGbw-1 X-Mimecast-Spam-Score: 0 Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 7bit X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 205.139.110.61 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 03 Dec 2019 15:29:37 -0000 On 12/3/19 3:59 PM, Damien Hedde wrote: > On 12/2/19 4:34 PM, Peter Maydell wrote: >> On Wed, 4 Sep 2019 at 13:56, Damien Hedde wrote: >>> >>> Add the connection between the slcr's output clocks and the uarts inputs. >>> >>> Also add the main board clock 'ps_clk', which is hard-coded to 33.33MHz >>> (the default frequency). This clock is used to feed the slcr's input >>> clock. >>> >>> Signed-off-by: Damien Hedde >> >> Nothing obviously wrong in the body of the patch, but as with >> 7 and 8, review from a Xilinx person would be helpful. >> >> /* board base frequency: 33.333333 MHz */ >> #define PS_CLK_FREQUENCY (100 * 1000 * 1000 / 3) >> >> This is interesting, because it's not an integer... I'll come back >> to this topic in a reply to the cover letter in a moment. > > For this precise case, what I wanted is the resulting integer which I > got from the device trees in linux (btw I should probably add this point > in comment). Just thought it was more readable this way than "33333333". FWIW I'm auditing if it is possible to use the float type for frequencies (before to ask on the list if this makes sense), because in hw/core/ptimer we use timers with periods, and loose some precision using 1/freq again. Also we have MiB/KiB in "qemu/units.h" and I'd like to introduce MHz/KHz. From MAILER-DAEMON Tue Dec 03 10:35:54 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1icADS-0002mB-P0 for mharc-qemu-arm@gnu.org; Tue, 03 Dec 2019 10:35:54 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:35673) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1icADJ-0002hv-Pj for qemu-arm@nongnu.org; Tue, 03 Dec 2019 10:35:48 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1icADG-0001Xe-IM for qemu-arm@nongnu.org; Tue, 03 Dec 2019 10:35:44 -0500 Received: from beetle.greensocs.com ([5.135.226.135]:42236) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1icAD8-0001TX-5I; Tue, 03 Dec 2019 10:35:35 -0500 Received: from [172.16.11.102] (crumble.bar.greensocs.com [172.16.11.102]) by beetle.greensocs.com (Postfix) with ESMTPSA id DCD3096EF0; Tue, 3 Dec 2019 15:35:29 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=greensocs.com; s=mail; t=1575387330; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=3rtcgx24BVdxIE+n3CGbbouJnJV5jKm2LoYK00DXaEs=; b=OEJ3qSVVm5k8two2BmGqm8TXAADshyO7sFGozbodU4XCA3r+Un0ewHCkkL7ZpL31aqenJQ 9rOoU0oL1aipTwBujtVobAn0hSD9xRF7NbL8B4ECbE9zDcwO8XhsMEfifAAofn6bKEKiNu Xe3VEztr3kecFoEY6AUIC0p84FGc2+8= Subject: Re: [PATCH v6 3/9] qdev: add clock input&output support to devices. To: =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= , qemu-devel@nongnu.org Cc: mark.burton@greensocs.com, edgar.iglesias@gmail.com, alistair@alistair23.me, peter.maydell@linaro.org, marcandre.lureau@redhat.com, pbonzini@redhat.com, berrange@redhat.com, ehabkost@redhat.com, qemu-arm@nongnu.org References: <20190904125531.27545-1-damien.hedde@greensocs.com> <20190904125531.27545-4-damien.hedde@greensocs.com> From: Damien Hedde Message-ID: Date: Tue, 3 Dec 2019 16:35:29 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.2.0 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=utf-8 Content-Language: en-US-large ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=greensocs.com; s=mail; t=1575387330; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=3rtcgx24BVdxIE+n3CGbbouJnJV5jKm2LoYK00DXaEs=; b=iNQjZ75iPSc3miDBaPymDurBw9qHFoIuohGqgdrP2jmS1vh9d5d5g3oUDhscGY+LPV1adZ pwthFQbMM/ZVsxSkmaUOpDf2NQEsmUlY5MgoJqZj8lOBWkL+jQ5Ju6Vwc0n5xjxOEWn6Kr 90M/OmUOHo9JopDYsCzxy2odhHhP19g= ARC-Seal: i=1; s=mail; d=greensocs.com; t=1575387330; a=rsa-sha256; cv=none; b=7k8HL8dK8tnvMqkFIiTRbMlA6Tb3/MudCDaFaG3shDmBB9qPtv2kRX3jicl6WIeZLGvJ2d KPJU45zNQFtVM5fdUU5G36bl0ykxstOAt+WkgU04kjj8VgpD6BX3i7E2WUdZOuDRL6TRRm jeGQJ3m9S+tmHpvGZcWKCVs8BmNWwZ0= ARC-Authentication-Results: i=1; ORIGINATING; auth=pass smtp.auth=damien smtp.mailfrom=damien.hedde@greensocs.com Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 5.135.226.135 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 03 Dec 2019 15:35:48 -0000 On 11/25/19 2:30 PM, Philippe Mathieu-Daud=C3=A9 wrote: > Nitpick: remove trailing dot in patch subject >=20 > On 9/4/19 2:55 PM, Damien Hedde wrote: >> Add functions to easily add input or output clocks to a device. >> A clock objects is added as a child of the device. >=20 > ? >=20 >> The api is very similar the gpio's one. >=20 > Maybe "This API is very similar to the QDEV GPIO API." >=20 >> >> This is based on the original work of Frederic Konrad. >> >> Signed-off-by: Damien Hedde >> >> --- >> I've removed the reviewed-by/tested-by of Philippe because I did a sma= ll >> modification. >> >> qdev_connect_clock() which allowed to connect an input to an output is >> now split in 2: >> + qdev_get_clock_in() which gets a given input from a device >> + qdev_connect_clock_out() which connect a given output to a clock >> (previously fetched by qdev_get_clock_in()) >> This part is located in (qdev-clock.[c|h]). >> It better matches gpios api and also add the possibility to connect a >> device's input clock to a random output clock (used in patch 9). >> >> Also add missing qdev-clock in the test-qdev-global-props so that test= s >> pass. >> --- >> =C2=A0 hw/core/Makefile.objs=C2=A0=C2=A0 |=C2=A0=C2=A0 2 +- >> =C2=A0 hw/core/qdev-clock.c=C2=A0=C2=A0=C2=A0 | 155 ++++++++++++++++++= ++++++++++++++++++++++ >> =C2=A0 hw/core/qdev.c=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0 |=C2=A0 32 +++++++++ >> =C2=A0 include/hw/qdev-clock.h |=C2=A0 67 +++++++++++++++++ >> =C2=A0 include/hw/qdev-core.h=C2=A0 |=C2=A0 14 ++++ >> =C2=A0 tests/Makefile.include=C2=A0 |=C2=A0=C2=A0 1 + >=20 > Please setup the scripts/git.orderfile to ease reviews. >=20 >> =C2=A0 6 files changed, 270 insertions(+), 1 deletion(-) >> =C2=A0 create mode 100644 hw/core/qdev-clock.c >> =C2=A0 create mode 100644 include/hw/qdev-clock.h >> >> diff --git a/hw/core/Makefile.objs b/hw/core/Makefile.objs >> index 8fcebf2e67..4523d3b5c7 100644 >> --- a/hw/core/Makefile.objs >> +++ b/hw/core/Makefile.objs >> @@ -1,5 +1,5 @@ >> =C2=A0 # core qdev-related obj files, also used by *-user: >> -common-obj-y +=3D qdev.o qdev-properties.o >> +common-obj-y +=3D qdev.o qdev-properties.o qdev-clock.o >> =C2=A0 common-obj-y +=3D bus.o reset.o >> =C2=A0 common-obj-y +=3D resettable.o >> =C2=A0 common-obj-$(CONFIG_SOFTMMU) +=3D qdev-fw.o >> diff --git a/hw/core/qdev-clock.c b/hw/core/qdev-clock.c >> new file mode 100644 >> index 0000000000..bebdd8fa15 >> --- /dev/null >> +++ b/hw/core/qdev-clock.c >> @@ -0,0 +1,155 @@ >> +/* >> + * Device's clock >> + * >> + * Copyright GreenSocs 2016-2018 >=20 > 2019 >=20 >> + * >> + * Authors: >> + *=C2=A0 Frederic Konrad >> + *=C2=A0 Damien Hedde >> + * >> + * This work is licensed under the terms of the GNU GPL, version 2 or >> later. >> + * See the COPYING file in the top-level directory. >> + */ >> + >> +#include "qemu/osdep.h" >> +#include "hw/qdev-clock.h" >> +#include "hw/qdev-core.h" >> +#include "qapi/error.h" >> + >> +static NamedClockList *qdev_init_clocklist(DeviceState *dev, const >> char *name, >> +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 bool forward) >=20 > Indentation off. >=20 >> +{ >> +=C2=A0=C2=A0=C2=A0 NamedClockList *ncl; >> + >> +=C2=A0=C2=A0=C2=A0 /* >> +=C2=A0=C2=A0=C2=A0=C2=A0 * The clock path will be computed by the dev= ice's realize >> function call. >> +=C2=A0=C2=A0=C2=A0=C2=A0 * This is required to ensure the clock's can= onical path is right >> and log >> +=C2=A0=C2=A0=C2=A0=C2=A0 * messages are meaningfull. >> +=C2=A0=C2=A0=C2=A0=C2=A0 */ >> +=C2=A0=C2=A0=C2=A0 assert(name); >> +=C2=A0=C2=A0=C2=A0 assert(!dev->realized); >> + >> +=C2=A0=C2=A0=C2=A0 /* The ncl structure will be freed in device's fin= alize function >> call */ >> +=C2=A0=C2=A0=C2=A0 ncl =3D g_malloc0(sizeof(*ncl)); >=20 > Similar but easier to review: >=20 > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 ncl =3D g_new0(NamedClockList, 1) >=20 >> +=C2=A0=C2=A0=C2=A0 ncl->name =3D g_strdup(name); >> +=C2=A0=C2=A0=C2=A0 ncl->forward =3D forward; >> + >> +=C2=A0=C2=A0=C2=A0 QLIST_INSERT_HEAD(&dev->clocks, ncl, node); >> +=C2=A0=C2=A0=C2=A0 return ncl; >> +} >> + >> +ClockOut *qdev_init_clock_out(DeviceState *dev, const char *name) >> +{ >> +=C2=A0=C2=A0=C2=A0 NamedClockList *ncl; >> +=C2=A0=C2=A0=C2=A0 Object *clk; >> + >> +=C2=A0=C2=A0=C2=A0 ncl =3D qdev_init_clocklist(dev, name, false); >> + >> +=C2=A0=C2=A0=C2=A0 clk =3D object_new(TYPE_CLOCK_OUT); >> + >> +=C2=A0=C2=A0=C2=A0 /* will fail if name already exists */ >> +=C2=A0=C2=A0=C2=A0 object_property_add_child(OBJECT(dev), name, clk, = &error_abort); >> +=C2=A0=C2=A0=C2=A0 object_unref(clk); /* remove the initial ref made = by object_new */ >> + >> +=C2=A0=C2=A0=C2=A0 ncl->out =3D CLOCK_OUT(clk); >> +=C2=A0=C2=A0=C2=A0 return ncl->out; >> +} >> + >> +ClockIn *qdev_init_clock_in(DeviceState *dev, const char *name, >> +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 Clo= ckCallback *callback, void *opaque) >=20 > Indentation off. >=20 >> +{ >> +=C2=A0=C2=A0=C2=A0 NamedClockList *ncl; >> +=C2=A0=C2=A0=C2=A0 Object *clk; >> + >> +=C2=A0=C2=A0=C2=A0 ncl =3D qdev_init_clocklist(dev, name, false); >> + >> +=C2=A0=C2=A0=C2=A0 clk =3D object_new(TYPE_CLOCK_IN); >> +=C2=A0=C2=A0=C2=A0 /* >> +=C2=A0=C2=A0=C2=A0=C2=A0 * the ref initialized by object_new will be = cleared during dev >> finalize. >> +=C2=A0=C2=A0=C2=A0=C2=A0 * It allows us to safely remove the callback= . >> +=C2=A0=C2=A0=C2=A0=C2=A0 */ >> + >> +=C2=A0=C2=A0=C2=A0 /* will fail if name already exists */ >> +=C2=A0=C2=A0=C2=A0 object_property_add_child(OBJECT(dev), name, clk, = &error_abort); >> + >> +=C2=A0=C2=A0=C2=A0 ncl->in =3D CLOCK_IN(clk); >> +=C2=A0=C2=A0=C2=A0 if (callback) { >> +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 clock_set_callback(ncl->in= , callback, opaque); >> +=C2=A0=C2=A0=C2=A0 } >> +=C2=A0=C2=A0=C2=A0 return ncl->in; >> +} >> + >> +static NamedClockList *qdev_get_clocklist(DeviceState *dev, const >> char *name) >> +{ >> +=C2=A0=C2=A0=C2=A0 NamedClockList *ncl; >> + >> +=C2=A0=C2=A0=C2=A0 QLIST_FOREACH(ncl, &dev->clocks, node) { >> +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 if (strcmp(name, ncl->name= ) =3D=3D 0) { >> +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 re= turn ncl; >> +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 } >> +=C2=A0=C2=A0=C2=A0 } >> + >> +=C2=A0=C2=A0=C2=A0 return NULL; >> +} >> + >> +void qdev_pass_clock(DeviceState *dev, const char *name, >> +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 DeviceState *containe= r, const char *cont_name) >> +{ >> +=C2=A0=C2=A0=C2=A0 NamedClockList *original_ncl, *ncl; >> +=C2=A0=C2=A0=C2=A0 Object **clk; >=20 > Is it really a Object** or a Object*? An Object** because it tells where the Object* is stored for the link property below. >=20 >> + >> +=C2=A0=C2=A0=C2=A0 assert(container && cont_name); >> + >> +=C2=A0=C2=A0=C2=A0 original_ncl =3D qdev_get_clocklist(container, con= t_name); >> +=C2=A0=C2=A0=C2=A0 assert(original_ncl); /* clock must exist in origi= n */ >> + >> +=C2=A0=C2=A0=C2=A0 ncl =3D qdev_init_clocklist(dev, name, true); >> + >> +=C2=A0=C2=A0=C2=A0 if (ncl->out) { >> +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 clk =3D (Object **)&ncl->o= ut; >> +=C2=A0=C2=A0=C2=A0 } else { >> +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 clk =3D (Object **)&ncl->i= n; >> +=C2=A0=C2=A0=C2=A0 } >> + >> +=C2=A0=C2=A0=C2=A0 /* will fail if name already exists */ >> +=C2=A0=C2=A0=C2=A0 object_property_add_link(OBJECT(dev), name, >> object_get_typename(*clk), >> +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0=C2=A0=C2=A0 clk, NULL, OBJ_PROP_LINK_STRONG, >> &error_abort); >> +} >> + -- Damien From MAILER-DAEMON Tue Dec 03 11:05:06 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1icAfh-0007fK-Rm for mharc-qemu-arm@gnu.org; Tue, 03 Dec 2019 11:05:05 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:45713) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1icAff-0007d0-1K for qemu-arm@nongnu.org; Tue, 03 Dec 2019 11:05:04 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1icAfc-0003fo-TN for qemu-arm@nongnu.org; Tue, 03 Dec 2019 11:05:02 -0500 Received: from mail-qv1-xf42.google.com ([2607:f8b0:4864:20::f42]:33282) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1icAfX-0003Vs-Gk; Tue, 03 Dec 2019 11:04:55 -0500 Received: by mail-qv1-xf42.google.com with SMTP id z3so1746657qvn.0; Tue, 03 Dec 2019 08:04:50 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=kK01j+jtcyJhmrX4/7BKHM8cxyWwgPUG6WT1zXZuUmY=; b=kxU82a8ScrfqhiA70X7n4MfyE6AWrHQ/9lcfQ/19RC4Y0aNTqQCJNVFbqePLERicNN jhSFFHCBxNHDoLuvXdrSN640pKNY4sr3fXbKF/NBtIPQHcVUPWJrs/Ti+eiHBtx2zgwR QkWyu+qkUeaKD3NuDglJXBPXSBmEUxSQs44s8kETv7Mg3XROl7bk4OT2odDJfDoSiGLE PIzg4qkaiMS2fsBez4kWMLTB9AwRjx+tr+GVWNAAQwjNkSMeZFIXdTXwZJfXeHl3mFzk rjE0JKMWIb+iaFYOZZqW0LSlbsFPK4qMiE1+V1608Qs9jkL2XvUTZ9vcQe1n00EXQv9V m5tA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=kK01j+jtcyJhmrX4/7BKHM8cxyWwgPUG6WT1zXZuUmY=; b=ZdRRaT2BZZg+sVxvt4sxb2tUyTxhizh1p4/4J4fduPpTAsMed3Wtr8Hq2FxVKJC09y Wk/an09wftZvQ3QlSfcPzi1rXyAHNpV3HqPAc0BfipchcIfGtV7YLpvHeIysE9JHp+Zx zIv1cqJvUyUN0faI8LPCKg0I6l9L/311Oe0RcsSGj2K7gCqoB9jGbrvt4in5NP//ED+3 KeLafX7p80XTVTVGxCnzliqI5tWT1BSfQg/3BQtJuwDdp8y6Oeq8qweRTmH+cNRoXpNo kq4FQOgNEhZWGBY9///gYsZjT4uCliZSzeoK7GAo71041OVi8kzqaoQi6nM0SiwnRV+E e0Sg== X-Gm-Message-State: APjAAAU6jNf5I7XGvS3s6zSaDuS0XzukctmWUhYlK8Oyykl3z+5y4MHb dneXteYPS4XW4yI3qgw7O4f2rUWo6EcFpyXcuBk= X-Google-Smtp-Source: APXvYqxJpqM7Yry1X7/U3Zu9GwMWbQh4QA6QslrwpbGLhSb80Gm1vOet2Y4FU/Lx8slJOoligX6wTV6uzhzDpFzELVA= X-Received: by 2002:a05:6214:4f0:: with SMTP id cl16mr5858994qvb.213.1575389089889; Tue, 03 Dec 2019 08:04:49 -0800 (PST) MIME-Version: 1.0 References: <20191129150508.24404-1-bilalwasim676@gmail.com> <8c956ae31e8f44a2b831a5030b2448b4@SVR-IES-MBX-03.mgc.mentorg.com> In-Reply-To: From: Bilal Wasim Date: Tue, 3 Dec 2019 21:04:38 +0500 Message-ID: Subject: Re: [PATCH] net/imx_fec: Updating the IMX_FEC IP to support loopback mode. To: jasowang@redhat.com Cc: "Wasim, Bilal" , "qemu-devel@nongnu.org" , "peter.maydell@linaro.org" , "aa1ronham@gmail.com" , "jcd@tribudubois.net" , "qemu-arm@nongnu.org" , "linux@roeck-us.net" , philmd@redhat.com Content-Type: multipart/alternative; boundary="0000000000001602820598cedb09" X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::f42 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 03 Dec 2019 16:05:04 -0000 --0000000000001602820598cedb09 Content-Type: text/plain; charset="UTF-8" ping... --0000000000001602820598cedb09 Content-Type: text/html; charset="UTF-8"
ping...
--0000000000001602820598cedb09-- From MAILER-DAEMON Tue Dec 03 11:09:14 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1icAji-0001T2-L7 for mharc-qemu-arm@gnu.org; Tue, 03 Dec 2019 11:09:14 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:50707) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1icAja-0008WH-1e for qemu-arm@nongnu.org; Tue, 03 Dec 2019 11:09:12 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1icAgx-0008Ir-54 for qemu-arm@nongnu.org; Tue, 03 Dec 2019 11:06:24 -0500 Received: from mail-pg1-x544.google.com ([2607:f8b0:4864:20::544]:44110) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1icAgv-0007yu-Uq for qemu-arm@nongnu.org; Tue, 03 Dec 2019 11:06:23 -0500 Received: by mail-pg1-x544.google.com with SMTP id x7so1849528pgl.11 for ; Tue, 03 Dec 2019 08:06:19 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=subject:to:cc:references:from:message-id:date:user-agent :mime-version:in-reply-to:content-language:content-transfer-encoding; bh=qPlxmpsww/pu/bjvZI3jSfIkTgDjwuMlI8DdBaeblcE=; b=zrUDicuC5vJp8eOS+zae9b4mnkSMy6Eba9YkZ39rXCjz6TgntJbdTRj56xT35AKPZ6 b66D7T59e6zVwF/1PJD4oZHQnSf+89CRACCZ8Kjft/0pKzE7Le7obKXKUEryll5919di lPdYYkbNiCIhX1U43SH6SAK3zkx67o2qVSPTxJiX/nSTYOa6G31wYDsUbtYtGBHV6wlP Fegv5dbO/bRdwdAdp6tzU+dAu8cPjnr353betzNe8UoxtzGmxxtTziqCvAIxwXfQOwp4 6ofVOMVf1pGlKO3/hRPSZ4r71kqMmaroc9husZjrwJFsw9QK9uIFwD5HveY0nNci0tXi QboQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:subject:to:cc:references:from:message-id:date :user-agent:mime-version:in-reply-to:content-language :content-transfer-encoding; bh=qPlxmpsww/pu/bjvZI3jSfIkTgDjwuMlI8DdBaeblcE=; b=IjSG+Rhwm2TVVcY71TV3YrTH+Ztx4tMumrAMtrB5DY0dyhbuD0eIlTAGxyXzRG84jf dSqI7xAlKWcYx1cjMVrGZinYgZmz/On3NglNN8lPxoRlxfCWW7iYwX12yALa9+MqVE8M /jK9bJMKcOPGx75ZOTaxnBL5QcIwDXNy+0SJvm3ls863o4JCNIwkF5Z3WwZyQRTELAcu zAzYU/IkazoKcuG9gper2cRALS6T8U8ysHHWOwFMX9JEImOPM1Si2aPsjc+RTYF/wkko XZjhaBbKh6B8EbPbfn9arIUXIJ2+k+t/hBrfDvCfr0DBXBQ5+fMz4w2Pc+sVzuIhK6Kr +krA== X-Gm-Message-State: APjAAAUNNbB2DONDKNnqYKGWEif6rBTrcwXRxKa+KP3koc954IEMofbD 68Y25tlcTswNIZKaC4aPhwRl8S3rlAc= X-Google-Smtp-Source: APXvYqzSdzBwyum6Yk0RuvnTROce3CUdvtALlK+A/5V5UOLp0Vya8gSGvtMlsnzHzfTX5ELuka+sVw== X-Received: by 2002:a62:5e04:: with SMTP id s4mr5700726pfb.63.1575389177445; Tue, 03 Dec 2019 08:06:17 -0800 (PST) Received: from [192.168.1.11] (97-113-7-119.tukw.qwest.net. [97.113.7.119]) by smtp.gmail.com with ESMTPSA id i5sm220648pgj.58.2019.12.03.08.06.15 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 03 Dec 2019 08:06:16 -0800 (PST) Subject: Re: [PATCH v5 04/22] target/arm: Add helper_mte_check{1,2,3} To: Peter Maydell Cc: QEMU Developers , qemu-arm References: <20191011134744.2477-1-richard.henderson@linaro.org> <20191011134744.2477-5-richard.henderson@linaro.org> From: Richard Henderson Message-ID: <5fb06e8a-3cc6-072e-a906-0c83fd2d107c@linaro.org> Date: Tue, 3 Dec 2019 08:06:14 -0800 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.2.1 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 7bit X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::544 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 03 Dec 2019 16:09:13 -0000 On 12/3/19 1:42 PM, Peter Maydell wrote: >> +static int allocation_tag_from_addr(uint64_t ptr) >> +{ >> + ptr += 1ULL << 55; /* carry ptr[55] into ptr[59:56]. */ >> + return extract64(ptr, 56, 4); > > What's the carry-bit-55 logic for? The pseudocode > AArch64.AllocationTagFromAddress just returns bits [59:56]. This was the old physical tag extraction. >> +static uint64_t do_mte_check(CPUARMState *env, uint64_t dirty_ptr, >> + uint64_t clean_ptr, uint32_t select, >> + uintptr_t ra) >> +{ >> + ARMMMUIdx stage1 = arm_stage1_mmu_idx(env); >> + int ptr_tag, mem_tag; >> + >> + /* >> + * If TCMA is enabled, then physical tag 0 is unchecked. >> + * Note the rules in D6.8.1 are written with logical tags, where >> + * the corresponding physical tag rule is simpler: equal to 0. >> + * We will need the physical tag below anyway. >> + */ > > This reads a bit oddly, because (in the final version of the spec) > physical and logical tags are identical (AArch64.PhysicalTag() > just returns bits [59:56] of the vaddr). I missed that change between draft and final. Wow, that's really annoying. If they were going to drop physical vs logical tags, why did they keep the language? Frankly, it made a *lot* of sense as a way to handle addresses in TTBR1, which now have asymmetric special cases. In particular, ADDG will, as I read it now, with allocation tag access disabled, munge a TTBR1 address to <59:56> = 0. Which is fine so long as access is disabled, but when re-enabled (e.g. via PSTATE.TCO) the address will no longer pass the TCMA test. Is this really intentional? r~ From MAILER-DAEMON Tue Dec 03 11:14:42 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1icAp0-0003cS-NZ for mharc-qemu-arm@gnu.org; Tue, 03 Dec 2019 11:14:42 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:44492) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1icAoy-0003aA-Lw for qemu-arm@nongnu.org; Tue, 03 Dec 2019 11:14:41 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1icAox-0003Sz-A9 for qemu-arm@nongnu.org; Tue, 03 Dec 2019 11:14:40 -0500 Received: from mail-pl1-x642.google.com ([2607:f8b0:4864:20::642]:38479) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1icAov-0003OE-5P for qemu-arm@nongnu.org; Tue, 03 Dec 2019 11:14:38 -0500 Received: by mail-pl1-x642.google.com with SMTP id o8so1881955pls.5 for ; Tue, 03 Dec 2019 08:14:30 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=subject:to:cc:references:from:message-id:date:user-agent :mime-version:in-reply-to:content-language:content-transfer-encoding; bh=m/GrtFDIpUGCPR2VKiymWN5ig4th9UzpETIPcVzQZwM=; b=Gxj93EMQEDNXx+9uH+yAaDemwYyjMep+z7TB242BIKQK09nNj945DFcwdZNZ+uaBnJ sfjS80AHP7xe72AMXJnKmjco6bERdJdkfMnaGP94wrh7m7W459Kmz/9gFeB8UXsveF6Q QJ+3dt1eRzjHpz6Pxb/9LNGkYNghSMpM19kPNIfhTdYelrvOth7cZoZ02fd0+uEKrHF7 pAm5+Mpd4gnomkBq9Gl4JahycOG5I3Y9u1erWYy7uevU78vrTWnyrnodr+OkjGIomOCm YeaA4ZGa7EfOxKh28RtfgzM+f18OTVxZIOz1FQ3tKDq33Hosdx5NCEwDhRmFpyhYsRLh 5rxw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:subject:to:cc:references:from:message-id:date :user-agent:mime-version:in-reply-to:content-language :content-transfer-encoding; bh=m/GrtFDIpUGCPR2VKiymWN5ig4th9UzpETIPcVzQZwM=; b=ar30X2pM+AJe+Q89nDn21MNhIyFmT5G8N1aMGmkJh3yyhnyM+8yMfJ15I+ZxjZCpiJ WR+GyZQ7fHD7Z/WDTjEYVqlbNEgsfFlSCsSjS2ZYClycCq8WrLZaPEgRdFvs5aiZtEkE Ea6QFkiaX7Pv1J3RBhT7Sx4aqa69vFEFirTk6r592xoMT7CG+kB9Xb3Y5xU8RDqpf3Wc 3XPQIWPuPCByrQEvypgP6+xC5sX0IEYVAYamzomsAgqkLHAI+XlNsy+aO2cE+xAY1+aC 5SYKcXhXqAtjMYnpb1SRmmW0UQIX7g8iwViQYfhZfLqTOJVxEaHcid/UKeAM45Qmn/Op lRNw== X-Gm-Message-State: APjAAAWBttpZToW23ScFVZhRlKUH8ynwEj/hpQa4l31k/xvDHQFlTvYG RT0N8wysM+thoFIjP69Ipzo5o6A8kDQ= X-Google-Smtp-Source: APXvYqxoFEnmSaSoM4THYyoGsi0v6ZcdCmQhKgJKRlyvsIyjkE8b31oZhUcuenAr2dtNCloyR4U6GQ== X-Received: by 2002:a17:902:6b01:: with SMTP id o1mr5582660plk.24.1575389669582; Tue, 03 Dec 2019 08:14:29 -0800 (PST) Received: from [192.168.1.11] (97-113-7-119.tukw.qwest.net. [97.113.7.119]) by smtp.gmail.com with ESMTPSA id s60sm708994pjb.3.2019.12.03.08.14.28 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 03 Dec 2019 08:14:28 -0800 (PST) Subject: Re: [PATCH v5 04/22] target/arm: Add helper_mte_check{1,2,3} To: Peter Maydell Cc: QEMU Developers , qemu-arm References: <20191011134744.2477-1-richard.henderson@linaro.org> <20191011134744.2477-5-richard.henderson@linaro.org> From: Richard Henderson Message-ID: <120a00d4-a33d-6263-c6d4-4671449d7dab@linaro.org> Date: Tue, 3 Dec 2019 08:14:26 -0800 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.2.1 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 7bit X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::642 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 03 Dec 2019 16:14:42 -0000 Oh, to finish up on the replies... On 12/3/19 1:42 PM, Peter Maydell wrote: >> + ptr_tag = allocation_tag_from_addr(dirty_ptr); >> + if (ptr_tag == 0) { >> + ARMVAParameters p = aa64_va_parameters(env, dirty_ptr, stage1, true); >> + if (p.tcma) { >> + return clean_ptr; >> + } >> + } > > I don't think this logic gets the "regime has two address ranges" > case correct. For a two-address-range translation regime (where > TCR_ELx has TCMA0 and TCMA1 bits, rather than just a single TCMA bit), > then the 'select' argument to this function needs to be involved, > because we should do a tag-unchecked access if: > * addr[59:55]==0b00000 (ie select == 0 and ptr_tag == 0) > and TCR_ELx.TCMA0 is set > * addr[59:55]==0b11111 (ie select == 1 and ptr_tag == 0xf) > and TCR_ELx.TCMA1 is set > (the pseudocode for this is in AArch64.AccessTagIsChecked(), > and the TCR_EL1.TCMA[01] bit definitions agree; the text in > D6.8.1 appears to be confused.) It used to be correct. That was the lovely bit about physical vs logical tags. Add 1 bit bit 55, let the carry ripple up, so that the physical tag check for TCMA was always against 0. That seems to be broken now in the final spec. >> + el = arm_current_el(env); >> + regime_el = (el ? el : 1); /* TODO: ARMv8.1-VHE EL2&0 regime */ > > We could write this as "regime_el(env, stage1)" if that function > wasn't local to helper.c, right ? Yes. >> + /* noreturn; fall through to assert anyway */ > > hopefully this fallthrough comment syntax doesn't confuse any > of our compilers/static analyzers... It shouldn't... >> + /* Tag check fail causes asynchronous flag set. */ >> + env->cp15.tfsr_el[regime_el] |= 1 << select; > > Won't this incorrectly accumulate tagfails for EL0 into > TFSR_EL1 rather than TFSRE0_EL1 ? I think you want "[el]". Yep. >> + /* Case 3: Reserved. */ >> + qemu_log_mask(LOG_GUEST_ERROR, >> + "Tag check failure with SCTLR_EL%d.TCF " >> + "set to reserved value %d\n", regime_el, tcf); > > Technically this message is going to be wrong for the > case of el==0 (where it's SCTLR_EL1.TCF0, not .TCF, that's > been mis-set). Yep. r~ From MAILER-DAEMON Tue Dec 03 11:27:02 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1icB0w-000443-NH for mharc-qemu-arm@gnu.org; Tue, 03 Dec 2019 11:27:02 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:44392) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1icB0r-0003z4-6u for qemu-arm@nongnu.org; Tue, 03 Dec 2019 11:26:59 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1icB0n-0003gZ-Pd for qemu-arm@nongnu.org; Tue, 03 Dec 2019 11:26:55 -0500 Received: from mail-ot1-x344.google.com ([2607:f8b0:4864:20::344]:47006) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1icB0k-0003cm-R6 for qemu-arm@nongnu.org; Tue, 03 Dec 2019 11:26:51 -0500 Received: by mail-ot1-x344.google.com with SMTP id g18so3390914otj.13 for ; Tue, 03 Dec 2019 08:26:47 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=+OMYhskkZ9V6o9Mq+CP1YBBMIFI1DP97rUoerzwObPY=; b=oRH4s+ibQPvdpaRHlFJeMZYoAtAD0r6gPcKQdPyWGcjl39aOLnq4VL6lXEPxMZZ+ak OmdygDpmwCBQQZyBLiWAj7x5oTpzQtnl99eqfLcI3lHrcZZGesv6UG7jPCAsDn1hN2OC FQiLMDQUyNEgJoy6ACwYVHzeHdfMXhlkJb1Nm0T13Dwua3K5u7v3zovHO4fwPXiwmjal ZQdu8Hy4gmgQ8+wZw4nzFzeJSNq4I2HsD0wAcmfgh70xZOInRvhdEYS6qs0viwsIxssq Y6gSlo9YGP2VbN3vCin0gber5UTU4PaeYaJCv5JghGalTkkJ6PMlK9PfguarybQF9XSd 8LQg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=+OMYhskkZ9V6o9Mq+CP1YBBMIFI1DP97rUoerzwObPY=; b=LsPim/uO+2EP+KgKw3DMs+3o0qKO1fB/1vs9KOMVBBY/4evyRPb6vEhbRJ34Qnhpqv O5UEYzJApEap/pW7aLzbJNkExM57roaIZxbkvMjDh1rFnT5kjFpH/t8V2V7IgT1sr3X9 rb7R+snsMgPLX+w0taILOglBDkLnoLhCk2nNK2TQIj+opx70Zx82VJHBpDfPVo48SMOl sDvlZ4r6wRaJk2y+x3hwDvVEcvTF/ZEzSDXL+f6mQyKNKp7y/NTkos/Ro5h+Tsw1oWuO d0+H3YuGm9CRuo5tHDzXNBwc+TsUNDCS0VUZScGT53zvSwUtx4mxHzIvlwzpCv8hCMXY HF1g== X-Gm-Message-State: APjAAAXBKmHAqVhC8qKVu3LRdXzB7T+yrxlk9n5HV1wyMUfQR3AAWHuy NCAcpaWsU0hrTbhzMt7U44rlk+2IsjSNGXSEUp/LSA== X-Google-Smtp-Source: APXvYqxz2p1lkisl1LFUAweCaYeEKf8mFQn1kGAbVda2Wb/m0OW7i53QHATyyj0MlE4ohcDVxcKIr5yoHq8+evJXuy0= X-Received: by 2002:a05:6830:2001:: with SMTP id e1mr3484930otp.97.1575390406703; Tue, 03 Dec 2019 08:26:46 -0800 (PST) MIME-Version: 1.0 References: <20191011134744.2477-1-richard.henderson@linaro.org> <20191011134744.2477-5-richard.henderson@linaro.org> <5fb06e8a-3cc6-072e-a906-0c83fd2d107c@linaro.org> In-Reply-To: <5fb06e8a-3cc6-072e-a906-0c83fd2d107c@linaro.org> From: Peter Maydell Date: Tue, 3 Dec 2019 16:26:35 +0000 Message-ID: Subject: Re: [PATCH v5 04/22] target/arm: Add helper_mte_check{1,2,3} To: Richard Henderson Cc: QEMU Developers , qemu-arm Content-Type: text/plain; charset="UTF-8" X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::344 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 03 Dec 2019 16:26:59 -0000 On Tue, 3 Dec 2019 at 16:06, Richard Henderson wrote: > On 12/3/19 1:42 PM, Peter Maydell wrote: > > This reads a bit oddly, because (in the final version of the spec) > > physical and logical tags are identical (AArch64.PhysicalTag() > > just returns bits [59:56] of the vaddr). > > I missed that change between draft and final. > > Wow, that's really annoying. If they were going to drop physical vs logical > tags, why did they keep the language? It leaves space for a potential future architecture making the mapping something other than 1:1. > Is this really intentional? Yes. thanks -- PMM From MAILER-DAEMON Tue Dec 03 12:30:10 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1icC02-0006GN-4W for mharc-qemu-arm@gnu.org; Tue, 03 Dec 2019 12:30:10 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:33114) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1icBzy-0005C4-VW for qemu-arm@nongnu.org; Tue, 03 Dec 2019 12:30:08 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1icBxq-0007F4-0m for qemu-arm@nongnu.org; Tue, 03 Dec 2019 12:27:57 -0500 Received: from us-smtp-1.mimecast.com ([205.139.110.61]:47783 helo=us-smtp-delivery-1.mimecast.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1icBxp-00079Y-RY for qemu-arm@nongnu.org; Tue, 03 Dec 2019 12:27:53 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1575394066; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=SDFRBhregaWR6UCPYA48ea7W+JzhzpaIQSt2Oza1ncI=; b=U5+2OUvmfqWfIzPapZ2dnPdcOc4NLM4SqaVfz6GvoL4qS66ym7AIXfUnJ9cpiIO3BLg4Hz +kwvQjzUGG7tNeZ/0WlWL00P0YOxKoBLhUGdMDLxMKid6nl6JKd4sdxxLPf/8Z9FW3PTN2 ++qWQgnCDoXmpmvntcNhmwEHMLum3nY= Received: from mail-wm1-f72.google.com (mail-wm1-f72.google.com [209.85.128.72]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-296-zyCjA1XyPfOCvZMz2juYkw-1; Tue, 03 Dec 2019 12:27:44 -0500 Received: by mail-wm1-f72.google.com with SMTP id s12so1142946wmc.6 for ; Tue, 03 Dec 2019 09:27:44 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:subject:to:cc:references:from:message-id:date :user-agent:mime-version:in-reply-to:content-language :content-transfer-encoding; bh=0D6PkLGHTZYjnPVu9XAb8Uu49tCjXJV4smH8ssuZw2s=; b=FnooN2aSZdlYXnK8zKbIVXzsIbnLOllIwY3fwAsveoCHcsDVgVvosoFadL6lTNOxwD 2Qy57IMVvDOga+58uB1Onq0mU2Wb03cL/u6XFpjio+UmwLJO8Fmujwniel5pAuM2OXUd HLYd4dE/0gEFYMx3JiLb0MjJFNkdfijIR+AY8iuMRWtPM9rGVu+71kCxV+yILvBa9IZQ frsZcKjCC9SlFZzG0eRRgtUh04LjdBYUW/i9xpns/KJy1yyT5c3au9QL8DBDaCF8TPNc rVaXkmSM6lX40I1ejQKWEPThcy6YNuoUPcXiyAqtyBO0+Ijdb2QRKilgBGL5YzpuX3qD 3f3Q== X-Gm-Message-State: APjAAAXNSbDvxWSG63qVobOeQlYdxL5GUPFQP+NA62I1vVXtayGvjWn0 9sKLor4DtAsQit2nPhw6Rc8z/5aExj8ZWEqBLtzDkygqI28hrNjm/59uDHWzo7uFkCtZLzWUlNL uWjjGNRN6c0oX X-Received: by 2002:a5d:49c7:: with SMTP id t7mr6345200wrs.369.1575394063026; Tue, 03 Dec 2019 09:27:43 -0800 (PST) X-Google-Smtp-Source: APXvYqwl5x7IJPTK960yATmh8P588D+vnq9K07QphsjWR6m2ZM+sDyg4iQ/ZdfLRMiWr172FftpTYA== X-Received: by 2002:a5d:49c7:: with SMTP id t7mr6345170wrs.369.1575394062698; Tue, 03 Dec 2019 09:27:42 -0800 (PST) Received: from [192.168.1.35] (182.red-88-21-103.staticip.rima-tde.net. [88.21.103.182]) by smtp.gmail.com with ESMTPSA id l3sm4465275wrt.29.2019.12.03.09.27.41 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 03 Dec 2019 09:27:42 -0800 (PST) Subject: Re: [PATCH v2 2/4] target/arm: Abstract the generic timer frequency To: Andrew Jeffery , qemu-arm@nongnu.org Cc: qemu-devel@nongnu.org, Peter Maydell , Richard Henderson , =?UTF-8?Q?C=c3=a9dric_Le_Goater?= , Joel Stanley References: <20191203041440.6275-1-andrew@aj.id.au> <20191203041440.6275-3-andrew@aj.id.au> <283c152b-b1c7-551e-bec0-c087b14de996@redhat.com> <4e90d36d-aa13-441f-9298-56f83a5bff6a@www.fastmail.com> From: =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= Message-ID: <87bf3c1d-9e77-f4a1-1163-548a3cfee3bc@redhat.com> Date: Tue, 3 Dec 2019 18:27:41 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.2.2 MIME-Version: 1.0 In-Reply-To: <4e90d36d-aa13-441f-9298-56f83a5bff6a@www.fastmail.com> Content-Language: en-US X-MC-Unique: zyCjA1XyPfOCvZMz2juYkw-1 X-Mimecast-Spam-Score: 0 Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 205.139.110.61 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 03 Dec 2019 17:30:08 -0000 On 12/3/19 1:48 PM, Andrew Jeffery wrote: > On Tue, 3 Dec 2019, at 16:39, Philippe Mathieu-Daud=C3=A9 wrote: >> On 12/3/19 5:14 AM, Andrew Jeffery wrote: >>> Prepare for SoCs such as the ASPEED AST2600 whose firmware configures >>> CNTFRQ to values significantly larger than the static 62.5MHz value >>> currently derived from GTIMER_SCALE. As the OS potentially derives its >>> timer periods from the CNTFRQ value the lack of support for running >>> QEMUTimers at the appropriate rate leads to sticky behaviour in the >>> guest. >>> >>> Substitute the GTIMER_SCALE constant with use of a helper to derive the >>> period from gt_cntfrq stored in struct ARMCPU. Initially set gt_cntfrq >>> to the frequency associated with GTIMER_SCALE so current behaviour is >>> maintained. >>> >>> Signed-off-by: Andrew Jeffery >>> Reviewed-by: Richard Henderson >>> --- >>> target/arm/cpu.c | 2 ++ >>> target/arm/cpu.h | 10 ++++++++++ >>> target/arm/helper.c | 10 +++++++--- >>> 3 files changed, 19 insertions(+), 3 deletions(-) >>> >>> diff --git a/target/arm/cpu.c b/target/arm/cpu.c >>> index 7a4ac9339bf9..5698a74061bb 100644 >>> --- a/target/arm/cpu.c >>> +++ b/target/arm/cpu.c >>> @@ -974,6 +974,8 @@ static void arm_cpu_initfn(Object *obj) >>> if (tcg_enabled()) { >>> cpu->psci_version =3D 2; /* TCG implements PSCI 0.2 */ >>> } >>> + >>> + cpu->gt_cntfrq =3D NANOSECONDS_PER_SECOND / GTIMER_SCALE; >>> } >>> =20 >>> static Property arm_cpu_reset_cbar_property =3D >>> diff --git a/target/arm/cpu.h b/target/arm/cpu.h >>> index 83a809d4bac4..666c03871fdf 100644 >>> --- a/target/arm/cpu.h >>> +++ b/target/arm/cpu.h >>> @@ -932,8 +932,18 @@ struct ARMCPU { >>> */ >>> DECLARE_BITMAP(sve_vq_map, ARM_MAX_VQ); >>> DECLARE_BITMAP(sve_vq_init, ARM_MAX_VQ); >>> + >>> + /* Generic timer counter frequency, in Hz */ >>> + uint64_t gt_cntfrq; >> >> You can also explicit the unit by calling it 'gt_cntfrq_hz'. >=20 > Fair call, I'll fix that. >=20 >> >>> }; >>> =20 >>> +static inline unsigned int gt_cntfrq_period_ns(ARMCPU *cpu) >>> +{ >>> + /* XXX: Could include qemu/timer.h to get NANOSECONDS_PER_SECOND? = */ >> >> Why inline this call? I doubt there is a significant performance gain. >=20 > It wasn't so much performance. It started out as a macro for a simple cal= culation > because I didn't want to duplicate it across a number of places, then I w= anted type > safety for the pointer so I switched the macro in the header to an inlin= e function. So > it is an evolution of the patch rather than something that came from an e= xplicit goal > of e.g. performance. OK. Eventually NANOSECONDS_PER_SECOND will move to "qemu/units.h". Should the XXX comment stay? I'm not sure, it is confusing. Reviewed-by: Philippe Mathieu-Daud=C3=A9 From MAILER-DAEMON Tue Dec 03 14:26:26 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1icDoY-0002G6-C9 for mharc-qemu-arm@gnu.org; Tue, 03 Dec 2019 14:26:26 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:33031) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1icDoR-0002B1-TM for qemu-arm@nongnu.org; Tue, 03 Dec 2019 14:26:24 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1icDoK-0002bj-Ba for qemu-arm@nongnu.org; Tue, 03 Dec 2019 14:26:16 -0500 Received: from mail-io1-xd30.google.com ([2607:f8b0:4864:20::d30]:33643) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1icDo9-0001as-Ox; Tue, 03 Dec 2019 14:26:02 -0500 Received: by mail-io1-xd30.google.com with SMTP id j13so5143160ioe.0; Tue, 03 Dec 2019 11:25:59 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=q59LGKPX00OXXu/bzLVuRQ5ldPP5Jh7dhrE/xNgoVOQ=; b=HSHxRvIdrU8MTCYmztBzFS5Inr8CRYQVV+UFeUzv6GgrZ1Ou3MIBSFNEDe1zS/SIjO E3xKb9yQ6cWp0HKrqJmWvSl0qzqzo0kibM0cLuQtbpIEmJWcbaTvJ1kbIeKlBRcBXY4p qvf8Y0N6AxVu36ayIVfHl8d+nZT1JQ4sIB3idx7QuqEm5Mt2LG4b+Z63JJCWAsP7uD/3 vFnJt6Jj4GNlcD9u+mIzNMuvnRS6FT58j6TpNqtwsLmT9ggfJu78sIZ/gmQXI9SlfGw0 PMjDS1XR1VQ4Cfi7twNeJr7Ool2MEbQFt7rQ+vb6rE4IVoEjT7mfdvdt65gdRyobH9IX 0Rrg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=q59LGKPX00OXXu/bzLVuRQ5ldPP5Jh7dhrE/xNgoVOQ=; b=r00UCbopj3sJiHvjeYWoyF5l3DYARHbIEj14yGanfvzcRRueI88DpDSOhSZliUV+Gc tC/PfDXmnji77K8Og4wAkQBQ6VU68XI153EVp8GP/AvEBwHykLbef+PnS2N6xiyJZMGi qz0sMdnlBfKfuSFsXhIGC4mS1E1FEfCPiqhWV635Qa6oCDoyOgTgtTEF/9u1blLA8RW4 VwGPvPfMoA/5baOMhTyhT5fvsaEHzY6R7uqJAo0UVwcBM6Cm0lmzGZp9feBqNohhQPP5 Fo3XWiXbs/u0jMO0ikPBfhBaJ17LZEOb096sblb4jrU99Sw0kyYUYcgBvrJnQkps1/iZ D4ig== X-Gm-Message-State: APjAAAUHHb8+cg8AxP/9m7xXeX0Aq698h9Je9dBNhh4JqVliyIVOvSbY 8grKXMY3afk4By0S479hhI6mM+Lushk4wAg+97Q= X-Google-Smtp-Source: APXvYqwN/Pow0alPHzFAknqyq5/o1P441HsVU6oa5OBU7hyQbN14HMStEYWx7mH3hNGoEY4ZTOF+bbtFITELU+kapMc= X-Received: by 2002:a6b:d912:: with SMTP id r18mr3435327ioc.306.1575401157295; Tue, 03 Dec 2019 11:25:57 -0800 (PST) MIME-Version: 1.0 References: <20191202210947.3603-1-nieklinnenbank@gmail.com> In-Reply-To: From: Niek Linnenbank Date: Tue, 3 Dec 2019 20:25:46 +0100 Message-ID: Subject: Re: [PATCH 00/10] Add Allwinner H3 SoC and Orange Pi PC Machine To: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= Cc: qemu-devel@nongnu.org, b.galvani@gmail.com, Peter Maydell , qemu-arm@nongnu.org, Richard Henderson Content-Type: multipart/alternative; boundary="0000000000005c0a4a0598d1aa1b" X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::d30 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 03 Dec 2019 19:26:24 -0000 --0000000000005c0a4a0598d1aa1b Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Hi Philippe, Thanks for your very quick response! I remember I have seen this error before while working on the patches, in particular on the SMP part. I'll try to reproduce this error with the 4.20 sunxi kernel you used and debug it. Could it be related to the change I made in patch 0006 for the CP10/CP11 bits? Basically I needed to add that to get the CPUCFG module working. It is an interface that U-Boot uses to reset the secondary cores for PSCI functionality. I use= d the arm_set_cpu_on() function there to reset the cores at the desired start address, but Im not sure if that function is the right choice. At some point while rebasing the patches, I got undefined exceptions which turned out to be because of the CP10/CP11 bits missing. If I made an obvious mistake there, please let me know and I'll correct it. Regards, Niek On Tue, Dec 3, 2019 at 9:47 AM Philippe Mathieu-Daud=C3=A9 wrote: > On 12/2/19 10:09 PM, Niek Linnenbank wrote: > > Dear QEMU developers, > > > > Hereby I would like to contribute the following set of patches to QEMU > > which add support for the Allwinner H3 System on Chip and the > > Orange Pi PC machine. The following features and devices are supported: > > > > * SMP (Quad Core Cortex A7) > > * Generic Interrupt Controller configuration > > * SRAM mappings > > * Timer device (re-used from Allwinner A10) > > * UART > > * SD/MMC storage controller > > * EMAC ethernet connectivity > > * USB 2.0 interfaces > > * Clock Control Unit > > * System Control module > > * Security Identifier device > > Awesome! > > > Functionality related to graphical output such as HDMI, GPU, > > Display Engine and audio are not included. Recently released > > mainline Linux kernels (4.19 up to latest master) and mainline U-Boot > > are known to work. The SD/MMC code is tested using bonnie++ and > > various tools such as fsck, dd and fdisk. The EMAC is verified with > iperf3 > > using -netdev socket. > > > > To build a Linux mainline kernel that can be booted by the Orange Pi PC > > machine, simply configure the kernel using the sunxi_defconfig > configuration: > > $ ARCH=3Darm CROSS_COMPILE=3Darm-linux-gnueabi- make mrproper > > $ ARCH=3Darm CROSS_COMPILE=3Darm-linux-gnueabi- make sunxi_defconfig > > > > To be able to use USB storage, you need to manually enable the > corresponding > > configuration item. Start the kconfig configuration tool: > > $ ARCH=3Darm CROSS_COMPILE=3Darm-linux-gnueabi- make menuconfig > > > > Navigate to the following item, enable it and save your configuration: > > Device Drivers > USB support > USB Mass Storage support > > > > Build the Linux kernel with: > > $ ARCH=3Darm CROSS_COMPILE=3Darm-linux-gnueabi- make -j5 > > > > To boot the newly build linux kernel in QEMU with the Orange Pi PC > machine, use: > > $ qemu-system-arm -M orangepi -m 512 -nic user -nographic \ > > -kernel /path/to/linux/arch/arm/boot/zImage \ > > -append 'console=3DttyS0,115200' \ > > -dtb /path/to/linux/arch/arm/boot/dts/sun8i-h3-orangepi-pc.dtb > > > > Note that this kernel does not have a root filesystem. You may provide = it > > with an official Orange Pi PC image [1] either as an SD card or as > > USB mass storage. To boot using the Orange Pi PC Debian image on SD car= d, > > simply add the -sd argument and provide the proper root=3D kernel > parameter: > > $ qemu-system-arm -M orangepi -m 512 -nic user -nographic \ > > -kernel /path/to/linux/arch/arm/boot/zImage \ > > -append 'console=3DttyS0,115200 root=3D/dev/mmcblk0p2' \ > > -dtb /path/to/linux/arch/arm/boot/dts/sun8i-h3-orangepi-pc.dtb \ > > -sd OrangePi_pc_debian_stretch_server_linux5.3.5_v1.0.img > > > > Alternatively, you can also choose to build and boot a recent buildroot > [2] > > using the orangepi_pc_defconfig or Armbian image [3] for Orange Pi PC. > > Richard, trying the Armbian image from > https://apt.armbian.com/pool/main/l/linux-4.20.7-sunxi/ I get: > > $ arm-softmmu/qemu-system-arm -M orangepi -m 512 -nic user \ > -append 'console=3DttyS0,115200' \ > -kernel boot/vmlinuz-4.20.7-sunxi \ > -dtb usr/lib/linux-image-dev-sunxi/sun8i-h3-orangepi-pc.dtb \ > -serial stdio -d unimp > Uncompressing Linux... done, booting the kernel. > rtc: unimplemented device write (size 4, value 0x16aa0001, offset 0x0) > rtc: unimplemented device read (size 4, offset 0x0) > rtc: unimplemented device read (size 4, offset 0x0) > rtc: unimplemented device read (size 4, offset 0x8) > qemu-system-arm: target/arm/helper.c:11359: cpu_get_tb_cpu_state: > Assertion `flags =3D=3D rebuild_hflags_internal(env)' failed. > Aborted (core dumped) > > (gdb) bt > #0 0x00007f6c1fa2ce35 in raise () at /lib64/libc.so.6 > #1 0x00007f6c1fa17895 in abort () at /lib64/libc.so.6 > #2 0x00007f6c1fa17769 in _nl_load_domain.cold () at /lib64/libc.so.6 > #3 0x00007f6c1fa25566 in annobin_assert.c_end () at /lib64/libc.so.6 > #4 0x00005590657e2685 in cpu_get_tb_cpu_state (env=3D0x5590686899b0, > pc=3D0x7f6c07ffa718, cs_base=3D0x7f6c07ffa714, pflags=3D0x7f6c07ffa71c) a= t > target/arm/helper.c:11359 > #5 0x000055906569f962 in tb_lookup__cpu_state (cpu=3D0x5590686808b0, > pc=3D0x7f6c07ffa718, cs_base=3D0x7f6c07ffa714, flags=3D0x7f6c07ffa71c, > cf_mask=3D524288) at include/exec/tb-lookup.h:28 > #6 0x00005590656a084c in tb_find (cpu=3D0x5590686808b0, last_tb=3D0x0, > tb_exit=3D0, cf_mask=3D524288) at accel/tcg/cpu-exec.c:403 > #7 0x00005590656a114a in cpu_exec (cpu=3D0x5590686808b0) at > accel/tcg/cpu-exec.c:730 > #8 0x000055906565f6af in tcg_cpu_exec (cpu=3D0x5590686808b0) at cpus.c:1= 473 > #9 0x000055906565ff05 in qemu_tcg_cpu_thread_fn (arg=3D0x5590686808b0) a= t > cpus.c:1781 > #10 0x0000559065d54aa6 in qemu_thread_start (args=3D0x5590687d8c20) at > util/qemu-thread-posix.c:519 > #11 0x00007f6c1fbc54c0 in start_thread () at /lib64/libpthread.so.0 > #12 0x00007f6c1faf1553 in clone () at /lib64/libc.so.6 > > (gdb) p/x flags > $1 =3D 0x33600000 > > (gdb) p/x *env > $2 =3D {regs =3D {0x0 , 0x40102448}, xregs =3D {0x0 32 times>}, pc =3D 0x0, pstate =3D 0x0, aarch64 =3D 0x0, hflags =3D 0x336= 00000, > uncached_cpsr =3D 0x1a, spsr =3D 0x0, banked_spsr =3D {0x0, 0x0, 0x0, 0x0= , > 0x0, 0x0, 0x0, 0x0}, > banked_r13 =3D {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, banked_r14 = =3D > {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, usr_regs =3D {0x0, 0x0, 0x0, > 0x0, 0x0}, fiq_regs =3D {0x0, 0x0, 0x0, 0x0, 0x0}, CF =3D 0x0, VF =3D 0x0= , NF > =3D 0x0, ZF =3D 0x0, > QF =3D 0x0, GE =3D 0x0, thumb =3D 0x1, condexec_bits =3D 0x0, btype = =3D 0x0, > daif =3D 0x3c0, elr_el =3D {0x0, 0x0, 0x0, 0x0}, sp_el =3D {0x0, 0x0, 0x0= , > 0x0}, cp15 =3D {c0_cpuid =3D 0x410fc075, {{_unused_csselr0 =3D 0x0, cssel= r_ns > =3D 0x0, > _unused_csselr1 =3D 0x0, csselr_s =3D 0x0}, csselr_el =3D {0x0, = 0x0, > 0x0, 0x0}}, {{_unused_sctlr =3D 0x0, sctlr_ns =3D 0xc50078, hsctlr =3D 0x= 0, > sctlr_s =3D 0xc50078}, sctlr_el =3D {0x0, 0xc50078, 0x0, 0xc50078}}, > cpacr_el1 =3D 0x0, cptr_el =3D { > 0x0, 0x0, 0x0, 0x0}, c1_xscaleauxcr =3D 0x0, sder =3D 0x0, nsacr = =3D > 0xc00, {{_unused_ttbr0_0 =3D 0x0, ttbr0_ns =3D 0x0, _unused_ttbr0_1 =3D 0= x0, > ttbr0_s =3D 0x0}, ttbr0_el =3D {0x0, 0x0, 0x0, 0x0}}, {{_unused_ttbr1_0 = =3D > 0x0, ttbr1_ns =3D 0x0, > _unused_ttbr1_1 =3D 0x0, ttbr1_s =3D 0x0}, ttbr1_el =3D {0x0, 0x= 0, > 0x0, 0x0}}, vttbr_el2 =3D 0x0, tcr_el =3D {{raw_tcr =3D 0x0, mask =3D 0x0= , > base_mask =3D 0x0}, {raw_tcr =3D 0x0, mask =3D 0x0, base_mask =3D 0xffffc= 000}, > {raw_tcr =3D 0x0, mask =3D 0x0, > base_mask =3D 0x0}, {raw_tcr =3D 0x0, mask =3D 0x0, base_mask = =3D > 0xffffc000}}, vtcr_el2 =3D {raw_tcr =3D 0x0, mask =3D 0x0, base_mask =3D = 0x0}, > c2_data =3D 0x0, c2_insn =3D 0x0, {{dacr_ns =3D 0x0, dacr_s =3D 0x0}, > {dacr32_el2 =3D 0x0}}, > pmsav5_data_ap =3D 0x0, pmsav5_insn_ap =3D 0x0, hcr_el2 =3D 0x0, scr= _el3 > =3D 0x101, {{ifsr_ns =3D 0x0, ifsr_s =3D 0x0}, {ifsr32_el2 =3D 0x0}}, > {{_unused_dfsr =3D 0x0, dfsr_ns =3D 0x0, hsr =3D 0x0, dfsr_s =3D 0x0}, es= r_el =3D > {0x0, 0x0, 0x0, 0x0}}, > c6_region =3D {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, > {{_unused_far0 =3D 0x0, dfar_ns =3D 0x0, ifar_ns =3D 0x0, dfar_s =3D 0x0,= ifar_s > =3D 0x0, _unused_far3 =3D 0x0}, far_el =3D {0x0, 0x0, 0x0, 0x0}}, hpfar_e= l2 =3D > 0x0, hstr_el2 =3D 0x0, {{ > _unused_par_0 =3D 0x0, par_ns =3D 0x0, _unused_par_1 =3D 0x0, pa= r_s =3D > 0x0}, par_el =3D {0x0, 0x0, 0x0, 0x0}}, c9_insn =3D 0x0, c9_data =3D 0x0, > c9_pmcr =3D 0x41002000, c9_pmcnten =3D 0x0, c9_pmovsr =3D 0x0, c9_pmusere= nr =3D > 0x0, c9_pmselr =3D 0x0, > c9_pminten =3D 0x0, {{_unused_mair_0 =3D 0x0, mair0_ns =3D 0x0, mair= 1_ns > =3D 0x0, _unused_mair_1 =3D 0x0, mair0_s =3D 0x0, mair1_s =3D 0x0}, mair_= el =3D > {0x0, 0x0, 0x0, 0x0}}, {{_unused_vbar =3D 0x0, vbar_ns =3D 0x0, hvbar =3D= 0x0, > vbar_s =3D 0x0}, > vbar_el =3D {0x0, 0x0, 0x0, 0x0}}, mvbar =3D 0x0, {fcseidr_ns =3D = 0x0, > fcseidr_s =3D 0x0}, {{_unused_contextidr_0 =3D 0x0, contextidr_ns =3D 0x0= , > _unused_contextidr_1 =3D 0x0, contextidr_s =3D 0x0}, contextidr_el =3D {0= x0, > 0x0, 0x0, 0x0}}, {{ > tpidrurw_ns =3D 0x0, tpidrprw_ns =3D 0x0, htpidr =3D 0x0, _tpidr= _el3 > =3D 0x0}, tpidr_el =3D {0x0, 0x0, 0x0, 0x0}}, tpidrurw_s =3D 0x0, tpidrpr= w_s =3D > 0x0, tpidruro_s =3D 0x0, {tpidruro_ns =3D 0x0, tpidrro_el =3D {0x0}}, > c14_cntfrq =3D 0x3b9aca0, > c14_cntkctl =3D 0x0, cnthctl_el2 =3D 0x3, cntvoff_el2 =3D 0x0, c14_t= imer > =3D {{cval =3D 0x0, ctl =3D 0x0}, {cval =3D 0x0, ctl =3D 0x0}, {cval =3D = 0x0, ctl =3D > 0x0}, {cval =3D 0x0, ctl =3D 0x0}}, c15_cpar =3D 0x0, c15_ticonfig =3D 0x= 0, > c15_i_max =3D 0x0, > c15_i_min =3D 0x0, c15_threadid =3D 0x0, c15_config_base_address =3D= 0x0, > c15_diagnostic =3D 0x0, c15_power_diagnostic =3D 0x0, c15_power_control = =3D > 0x0, dbgbvr =3D {0x0 }, dbgbcr =3D {0x0 times>}, dbgwvr =3D { > 0x0 }, dbgwcr =3D {0x0 }, > mdscr_el1 =3D 0x0, oslsr_el1 =3D 0xa, mdcr_el2 =3D 0x0, mdcr_el3 =3D 0x0, > c15_ccnt =3D 0x0, c15_ccnt_delta =3D 0x0, c14_pmevcntr =3D {0x0 times>}, c14_pmevcntr_delta =3D { > 0x0 }, c14_pmevtyper =3D {0x0 times>}, pmccfiltr_el0 =3D 0x0, vpidr_el2 =3D 0x410fc075, vmpidr_el2 =3D > 0x80000001}, v7m =3D {other_sp =3D 0x0, other_ss_msp =3D 0x0, other_ss_ps= p =3D > 0x0, vecbase =3D {0x0, 0x0}, > basepri =3D {0x0, 0x0}, control =3D {0x0, 0x0}, ccr =3D {0x0, 0x0}, = cfsr > =3D {0x0, 0x0}, hfsr =3D 0x0, dfsr =3D 0x0, sfsr =3D 0x0, mmfar =3D {0x0,= 0x0}, > bfar =3D 0x0, sfar =3D 0x0, mpu_ctrl =3D {0x0, 0x0}, exception =3D 0x0, p= rimask > =3D {0x0, 0x0}, > faultmask =3D {0x0, 0x0}, aircr =3D 0x0, secure =3D 0x0, csselr =3D = {0x0, > 0x0}, scr =3D {0x0, 0x0}, msplim =3D {0x0, 0x0}, psplim =3D {0x0, 0x0}, f= pcar > =3D {0x0, 0x0}, fpccr =3D {0x0, 0x0}, fpdscr =3D {0x0, 0x0}, cpacr =3D {0= x0, > 0x0}, nsacr =3D 0x0}, > exception =3D {syndrome =3D 0x0, fsr =3D 0x0, vaddress =3D 0x0, target= _el =3D > 0x0}, serror =3D {pending =3D 0x0, has_esr =3D 0x0, esr =3D 0x0}, irq_lin= e_state > =3D 0x0, teecr =3D 0x0, teehbr =3D 0x0, vfp =3D {zregs =3D {{d =3D {0x0, = 0x0}} > }, > qc =3D {0x0, 0x0, 0x0, 0x0}, vec_len =3D 0x0, vec_stride =3D 0x0, xr= egs =3D > {0x41023075, 0x0, 0x0, 0x0, 0x0, 0x0, 0x11111111, 0x10110222, 0x0, 0x0, > 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, scratch =3D {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, > 0x0, 0x0}, > fp_status =3D {float_detect_tininess =3D 0x1, float_rounding_mode = =3D > 0x0, float_exception_flags =3D 0x0, floatx80_rounding_precision =3D 0x0, > flush_to_zero =3D 0x0, flush_inputs_to_zero =3D 0x0, default_nan_mode =3D= 0x0, > snan_bit_is_one =3D 0x0}, > fp_status_f16 =3D {float_detect_tininess =3D 0x1, float_rounding_mod= e =3D > 0x0, float_exception_flags =3D 0x0, floatx80_rounding_precision =3D 0x0, > flush_to_zero =3D 0x0, flush_inputs_to_zero =3D 0x0, default_nan_mode =3D= 0x0, > snan_bit_is_one =3D 0x0}, standard_fp_status =3D > {float_detect_tininess =3D 0x1, float_rounding_mode =3D 0x0, > float_exception_flags =3D 0x0, floatx80_rounding_precision =3D 0x0, > flush_to_zero =3D 0x1, flush_inputs_to_zero =3D 0x1, > default_nan_mode =3D 0x1, snan_bit_is_one =3D 0x0}, zcr_el =3D {0x= 0, > 0x0, 0x0, 0x0}}, exclusive_addr =3D 0xffffffffffffffff, exclusive_val =3D > 0x0, exclusive_high =3D 0x0, iwmmxt =3D {regs =3D {0x0 = }, > val =3D 0x0, cregs =3D { > 0x0 }}, cpu_breakpoint =3D {0x0 times>}, cpu_watchpoint =3D {0x0 }, end_reset_fields = =3D > {}, features =3D 0xfd38fbe6f3, pmsav7 =3D {drbar =3D 0x0,= drsr > =3D 0x0, dracr =3D 0x0, > rnr =3D {0x0, 0x0}}, pmsav8 =3D {rbar =3D {0x0, 0x0}, rlar =3D {0x0,= 0x0}, > mair0 =3D {0x0, 0x0}, mair1 =3D {0x0, 0x0}}, sau =3D {rbar =3D 0x0, rlar = =3D 0x0, > rnr =3D 0x0, ctrl =3D 0x0}, nvic =3D 0x0, boot_info =3D 0x5622af3a17a0, > gicv3state =3D 0x0} > > > [1] http://www.orangepi.org/downloadresources/ > > [2] https://buildroot.org/download.html > > [3] https://www.armbian.com/orange-pi-pc/ > > --=20 Niek Linnenbank WWW: http://www.nieklinnenbank.nl/ BLOG: http://nieklinnenbank.wordpress.com/ FUN: http://www.FreeNOS.org/ --0000000000005c0a4a0598d1aa1b Content-Type: text/html; charset="UTF-8" Content-Transfer-Encoding: quoted-printable
Hi Philippe,

Thanks for your= very quick response!
I remember I have seen this error before wh= ile working on the patches, in particular
on the SMP part. I'= ll try to reproduce this error with the 4.20 sunxi kernel you used and debu= g it.

Could it be related to the change I made in= patch 0006 for the CP10/CP11 bits?
Basically I needed to ad= d that to get the CPUCFG module working. It is an interface
that = U-Boot uses to reset the secondary cores for PSCI functionality. I used
the arm_set_cpu_on() function there to reset the cores at the desire= d start address,
but Im not sure if that function is the right ch= oice. At some point while rebasing the patches,
I got undefined e= xceptions which turned out to be because of the CP10/CP11 bits missing.
If I made an obvious mistake there, please let me know and I'll = correct it.

Regards,
Niek
<= div>

On Tue, Dec 3, 2019 at 9:47 AM Philippe Mathieu-Daud=C3=A9 = <philmd@redhat.com> wrote:
On 12/2/19 10:09 = PM, Niek Linnenbank wrote:
> Dear QEMU developers,
>
> Hereby I would like to contribute the following set of patches to QEMU=
> which add support for the Allwinner H3 System on Chip and the
> Orange Pi PC machine. The following features and devices are supported= :
>
>=C2=A0 =C2=A0* SMP (Quad Core Cortex A7)
>=C2=A0 =C2=A0* Generic Interrupt Controller configuration
>=C2=A0 =C2=A0* SRAM mappings
>=C2=A0 =C2=A0* Timer device (re-used from Allwinner A10)
>=C2=A0 =C2=A0* UART
>=C2=A0 =C2=A0* SD/MMC storage controller
>=C2=A0 =C2=A0* EMAC ethernet connectivity
>=C2=A0 =C2=A0* USB 2.0 interfaces
>=C2=A0 =C2=A0* Clock Control Unit
>=C2=A0 =C2=A0* System Control module
>=C2=A0 =C2=A0* Security Identifier device

Awesome!

> Functionality related to graphical output such as HDMI, GPU,
> Display Engine and audio are not included. Recently released
> mainline Linux kernels (4.19 up to latest master) and mainline U-Boot<= br> > are known to work. The SD/MMC code is tested using bonnie++ and
> various tools such as fsck, dd and fdisk. The EMAC is verified with ip= erf3
> using -netdev socket.
>
> To build a Linux mainline kernel that can be booted by the Orange Pi P= C
> machine, simply configure the kernel using the sunxi_defconfig configu= ration:
>=C2=A0 =C2=A0$ ARCH=3Darm CROSS_COMPILE=3Darm-linux-gnueabi- make mrpro= per
>=C2=A0 =C2=A0$ ARCH=3Darm CROSS_COMPILE=3Darm-linux-gnueabi- make sunxi= _defconfig
>
> To be able to use USB storage, you need to manually enable the corresp= onding
> configuration item. Start the kconfig configuration tool:
>=C2=A0 =C2=A0$ ARCH=3Darm CROSS_COMPILE=3Darm-linux-gnueabi- make menuc= onfig
>
> Navigate to the following item, enable it and save your configuration:=
>=C2=A0 =C2=A0Device Drivers > USB support > USB Mass Storage supp= ort
>
> Build the Linux kernel with:
>=C2=A0 =C2=A0$ ARCH=3Darm CROSS_COMPILE=3Darm-linux-gnueabi- make -j5 >
> To boot the newly build linux kernel in QEMU with the Orange Pi PC mac= hine, use:
>=C2=A0 =C2=A0$ qemu-system-arm -M orangepi -m 512 -nic user -nographic = \
>=C2=A0 =C2=A0 =C2=A0 =C2=A0-kernel /path/to/linux/arch/arm/boot/zImage = \
>=C2=A0 =C2=A0 =C2=A0 =C2=A0-append 'console=3DttyS0,115200' \ >=C2=A0 =C2=A0 =C2=A0 =C2=A0-dtb /path/to/linux/arch/arm/boot/dts/sun8i-= h3-orangepi-pc.dtb
>
> Note that this kernel does not have a root filesystem. You may provide= it
> with an official Orange Pi PC image [1] either as an SD card or as
> USB mass storage. To boot using the Orange Pi PC Debian image on SD ca= rd,
> simply add the -sd argument and provide the proper root=3D kernel para= meter:
>=C2=A0 =C2=A0$ qemu-system-arm -M orangepi -m 512 -nic user -nographic = \
>=C2=A0 =C2=A0 =C2=A0 =C2=A0-kernel /path/to/linux/arch/arm/boot/zImage = \
>=C2=A0 =C2=A0 =C2=A0 =C2=A0-append 'console=3DttyS0,115200 root=3D/= dev/mmcblk0p2' \
>=C2=A0 =C2=A0 =C2=A0 =C2=A0-dtb /path/to/linux/arch/arm/boot/dts/sun8i-= h3-orangepi-pc.dtb \
>=C2=A0 =C2=A0 =C2=A0 =C2=A0-sd OrangePi_pc_debian_stretch_server_linux5= .3.5_v1.0.img
>
> Alternatively, you can also choose to build and boot a recent buildroo= t [2]
> using the orangepi_pc_defconfig or Armbian image [3] for Orange Pi PC.=

Richard, trying the Armbian image from
https://apt.armbian.com/pool/main/l/linux-4.2= 0.7-sunxi/ I get:

$ arm-softmmu/qemu-system-arm -M orangepi -m 512 -nic user \
=C2=A0 =C2=A0-append 'console=3DttyS0,115200' \
=C2=A0 =C2=A0-kernel boot/vmlinuz-4.20.7-sunxi \
=C2=A0 =C2=A0-dtb usr/lib/linux-image-dev-sunxi/sun8i-h3-orangepi-pc.dtb \<= br> =C2=A0 =C2=A0-serial stdio -d unimp
Uncompressing Linux... done, booting the kernel.
rtc: unimplemented device write (size 4, value 0x16aa0001, offset 0x0)
rtc: unimplemented device read (size 4, offset 0x0)
rtc: unimplemented device read (size 4, offset 0x0)
rtc: unimplemented device read (size 4, offset 0x8)
qemu-system-arm: target/arm/helper.c:11359: cpu_get_tb_cpu_state:
Assertion `flags =3D=3D rebuild_hflags_internal(env)' failed.
Aborted (core dumped)

(gdb) bt
#0=C2=A0 0x00007f6c1fa2ce35 in raise () at /lib64/libc.so.6
#1=C2=A0 0x00007f6c1fa17895 in abort () at /lib64/libc.so.6
#2=C2=A0 0x00007f6c1fa17769 in _nl_load_domain.cold () at /lib64/libc.so.6<= br> #3=C2=A0 0x00007f6c1fa25566 in annobin_assert.c_end () at /lib64/libc.so.6<= br> #4=C2=A0 0x00005590657e2685 in cpu_get_tb_cpu_state (env=3D0x5590686899b0, =
pc=3D0x7f6c07ffa718, cs_base=3D0x7f6c07ffa714, pflags=3D0x7f6c07ffa71c) at =
target/arm/helper.c:11359
#5=C2=A0 0x000055906569f962 in tb_lookup__cpu_state (cpu=3D0x5590686808b0, =
pc=3D0x7f6c07ffa718, cs_base=3D0x7f6c07ffa714, flags=3D0x7f6c07ffa71c,
cf_mask=3D524288) at include/exec/tb-lookup.h:28
#6=C2=A0 0x00005590656a084c in tb_find (cpu=3D0x5590686808b0, last_tb=3D0x0= ,
tb_exit=3D0, cf_mask=3D524288) at accel/tcg/cpu-exec.c:403
#7=C2=A0 0x00005590656a114a in cpu_exec (cpu=3D0x5590686808b0) at
accel/tcg/cpu-exec.c:730
#8=C2=A0 0x000055906565f6af in tcg_cpu_exec (cpu=3D0x5590686808b0) at cpus.= c:1473
#9=C2=A0 0x000055906565ff05 in qemu_tcg_cpu_thread_fn (arg=3D0x5590686808b0= ) at
cpus.c:1781
#10 0x0000559065d54aa6 in qemu_thread_start (args=3D0x5590687d8c20) at
util/qemu-thread-posix.c:519
#11 0x00007f6c1fbc54c0 in start_thread () at /lib64/libpthread.so.0
#12 0x00007f6c1faf1553 in clone () at /lib64/libc.so.6

(gdb) p/x flags
$1 =3D 0x33600000

(gdb) p/x *env
$2 =3D {regs =3D {0x0 <repeats 15 times>, 0x40102448}, xregs =3D {0x0= <repeats
32 times>}, pc =3D 0x0, pstate =3D 0x0, aarch64 =3D 0x0, hflags =3D 0x33= 600000,
uncached_cpsr =3D 0x1a, spsr =3D 0x0, banked_spsr =3D {0x0, 0x0, 0x0, 0x0, =
0x0, 0x0, 0x0, 0x0},
=C2=A0 =C2=A0banked_r13 =3D {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, banke= d_r14 =3D
{0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, usr_regs =3D {0x0, 0x0, 0x0,
0x0, 0x0}, fiq_regs =3D {0x0, 0x0, 0x0, 0x0, 0x0}, CF =3D 0x0, VF =3D 0x0, = NF
=3D 0x0, ZF =3D 0x0,
=C2=A0 =C2=A0QF =3D 0x0, GE =3D 0x0, thumb =3D 0x1, condexec_bits =3D 0x0, = btype =3D 0x0,
daif =3D 0x3c0, elr_el =3D {0x0, 0x0, 0x0, 0x0}, sp_el =3D {0x0, 0x0, 0x0, =
0x0}, cp15 =3D {c0_cpuid =3D 0x410fc075, {{_unused_csselr0 =3D 0x0, csselr_= ns
=3D 0x0,
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0_unused_csselr1 =3D 0x0, csselr_s =3D 0x0= }, csselr_el =3D {0x0, 0x0,
0x0, 0x0}}, {{_unused_sctlr =3D 0x0, sctlr_ns =3D 0xc50078, hsctlr =3D 0x0,=
sctlr_s =3D 0xc50078}, sctlr_el =3D {0x0, 0xc50078, 0x0, 0xc50078}},
cpacr_el1 =3D 0x0, cptr_el =3D {
=C2=A0 =C2=A0 =C2=A0 =C2=A00x0, 0x0, 0x0, 0x0}, c1_xscaleauxcr =3D 0x0, sde= r =3D 0x0, nsacr =3D
0xc00, {{_unused_ttbr0_0 =3D 0x0, ttbr0_ns =3D 0x0, _unused_ttbr0_1 =3D 0x0= ,
ttbr0_s =3D 0x0}, ttbr0_el =3D {0x0, 0x0, 0x0, 0x0}}, {{_unused_ttbr1_0 =3D=
0x0, ttbr1_ns =3D 0x0,
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0_unused_ttbr1_1 =3D 0x0, ttbr1_s =3D 0x0}= , ttbr1_el =3D {0x0, 0x0,
0x0, 0x0}}, vttbr_el2 =3D 0x0, tcr_el =3D {{raw_tcr =3D 0x0, mask =3D 0x0, =
base_mask =3D 0x0}, {raw_tcr =3D 0x0, mask =3D 0x0, base_mask =3D 0xffffc00= 0},
{raw_tcr =3D 0x0, mask =3D 0x0,
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0base_mask =3D 0x0}, {raw_tcr =3D 0x0, mas= k =3D 0x0, base_mask =3D
0xffffc000}}, vtcr_el2 =3D {raw_tcr =3D 0x0, mask =3D 0x0, base_mask =3D 0x= 0},
c2_data =3D 0x0, c2_insn =3D 0x0, {{dacr_ns =3D 0x0, dacr_s =3D 0x0},
{dacr32_el2 =3D 0x0}},
=C2=A0 =C2=A0 =C2=A0pmsav5_data_ap =3D 0x0, pmsav5_insn_ap =3D 0x0, hcr_el2= =3D 0x0, scr_el3
=3D 0x101, {{ifsr_ns =3D 0x0, ifsr_s =3D 0x0}, {ifsr32_el2 =3D 0x0}},
{{_unused_dfsr =3D 0x0, dfsr_ns =3D 0x0, hsr =3D 0x0, dfsr_s =3D 0x0}, esr_= el =3D
{0x0, 0x0, 0x0, 0x0}},
=C2=A0 =C2=A0 =C2=A0c6_region =3D {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},=
{{_unused_far0 =3D 0x0, dfar_ns =3D 0x0, ifar_ns =3D 0x0, dfar_s =3D 0x0, i= far_s
=3D 0x0, _unused_far3 =3D 0x0}, far_el =3D {0x0, 0x0, 0x0, 0x0}}, hpfar_el2= =3D
0x0, hstr_el2 =3D 0x0, {{
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0_unused_par_0 =3D 0x0, par_ns =3D 0x0, _u= nused_par_1 =3D 0x0, par_s =3D
0x0}, par_el =3D {0x0, 0x0, 0x0, 0x0}}, c9_insn =3D 0x0, c9_data =3D 0x0, <= br> c9_pmcr =3D 0x41002000, c9_pmcnten =3D 0x0, c9_pmovsr =3D 0x0, c9_pmuserenr= =3D
0x0, c9_pmselr =3D 0x0,
=C2=A0 =C2=A0 =C2=A0c9_pminten =3D 0x0, {{_unused_mair_0 =3D 0x0, mair0_ns = =3D 0x0, mair1_ns
=3D 0x0, _unused_mair_1 =3D 0x0, mair0_s =3D 0x0, mair1_s =3D 0x0}, mair_el= =3D
{0x0, 0x0, 0x0, 0x0}}, {{_unused_vbar =3D 0x0, vbar_ns =3D 0x0, hvbar =3D 0= x0,
vbar_s =3D 0x0},
=C2=A0 =C2=A0 =C2=A0 =C2=A0vbar_el =3D {0x0, 0x0, 0x0, 0x0}}, mvbar =3D 0x0= , {fcseidr_ns =3D 0x0,
fcseidr_s =3D 0x0}, {{_unused_contextidr_0 =3D 0x0, contextidr_ns =3D 0x0, =
_unused_contextidr_1 =3D 0x0, contextidr_s =3D 0x0}, contextidr_el =3D {0x0= ,
0x0, 0x0, 0x0}}, {{
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0tpidrurw_ns =3D 0x0, tpidrprw_ns =3D 0x0,= htpidr =3D 0x0, _tpidr_el3
=3D 0x0}, tpidr_el =3D {0x0, 0x0, 0x0, 0x0}}, tpidrurw_s =3D 0x0, tpidrprw_= s =3D
0x0, tpidruro_s =3D 0x0, {tpidruro_ns =3D 0x0, tpidrro_el =3D {0x0}},
c14_cntfrq =3D 0x3b9aca0,
=C2=A0 =C2=A0 =C2=A0c14_cntkctl =3D 0x0, cnthctl_el2 =3D 0x3, cntvoff_el2 = =3D 0x0, c14_timer
=3D {{cval =3D 0x0, ctl =3D 0x0}, {cval =3D 0x0, ctl =3D 0x0}, {cval =3D 0x= 0, ctl =3D
0x0}, {cval =3D 0x0, ctl =3D 0x0}}, c15_cpar =3D 0x0, c15_ticonfig =3D 0x0,=
c15_i_max =3D 0x0,
=C2=A0 =C2=A0 =C2=A0c15_i_min =3D 0x0, c15_threadid =3D 0x0, c15_config_bas= e_address =3D 0x0,
c15_diagnostic =3D 0x0, c15_power_diagnostic =3D 0x0, c15_power_control =3D=
0x0, dbgbvr =3D {0x0 <repeats 16 times>}, dbgbcr =3D {0x0 <repeats= 16
times>}, dbgwvr =3D {
=C2=A0 =C2=A0 =C2=A0 =C2=A00x0 <repeats 16 times>}, dbgwcr =3D {0x0 &= lt;repeats 16 times>},
mdscr_el1 =3D 0x0, oslsr_el1 =3D 0xa, mdcr_el2 =3D 0x0, mdcr_el3 =3D 0x0, <= br> c15_ccnt =3D 0x0, c15_ccnt_delta =3D 0x0, c14_pmevcntr =3D {0x0 <repeats= 31
times>}, c14_pmevcntr_delta =3D {
=C2=A0 =C2=A0 =C2=A0 =C2=A00x0 <repeats 31 times>}, c14_pmevtyper =3D= {0x0 <repeats 31
times>}, pmccfiltr_el0 =3D 0x0, vpidr_el2 =3D 0x410fc075, vmpidr_el2 =3D=
0x80000001}, v7m =3D {other_sp =3D 0x0, other_ss_msp =3D 0x0, other_ss_psp = =3D
0x0, vecbase =3D {0x0, 0x0},
=C2=A0 =C2=A0 =C2=A0basepri =3D {0x0, 0x0}, control =3D {0x0, 0x0}, ccr =3D= {0x0, 0x0}, cfsr
=3D {0x0, 0x0}, hfsr =3D 0x0, dfsr =3D 0x0, sfsr =3D 0x0, mmfar =3D {0x0, 0= x0},
bfar =3D 0x0, sfar =3D 0x0, mpu_ctrl =3D {0x0, 0x0}, exception =3D 0x0, pri= mask
=3D {0x0, 0x0},
=C2=A0 =C2=A0 =C2=A0faultmask =3D {0x0, 0x0}, aircr =3D 0x0, secure =3D 0x0= , csselr =3D {0x0,
0x0}, scr =3D {0x0, 0x0}, msplim =3D {0x0, 0x0}, psplim =3D {0x0, 0x0}, fpc= ar
=3D {0x0, 0x0}, fpccr =3D {0x0, 0x0}, fpdscr =3D {0x0, 0x0}, cpacr =3D {0x0= ,
0x0}, nsacr =3D 0x0},
=C2=A0 =C2=A0exception =3D {syndrome =3D 0x0, fsr =3D 0x0, vaddress =3D 0x0= , target_el =3D
0x0}, serror =3D {pending =3D 0x0, has_esr =3D 0x0, esr =3D 0x0}, irq_line_= state
=3D 0x0, teecr =3D 0x0, teehbr =3D 0x0, vfp =3D {zregs =3D {{d =3D {0x0, 0x= 0}}
<repeats 32 times>},
=C2=A0 =C2=A0 =C2=A0qc =3D {0x0, 0x0, 0x0, 0x0}, vec_len =3D 0x0, vec_strid= e =3D 0x0, xregs =3D
{0x41023075, 0x0, 0x0, 0x0, 0x0, 0x0, 0x11111111, 0x10110222, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, scratch =3D {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, <= br> 0x0, 0x0},
=C2=A0 =C2=A0 =C2=A0fp_status =3D {float_detect_tininess =3D 0x1, float_rou= nding_mode =3D
0x0, float_exception_flags =3D 0x0, floatx80_rounding_precision =3D 0x0, flush_to_zero =3D 0x0, flush_inputs_to_zero =3D 0x0, default_nan_mode =3D 0= x0,
snan_bit_is_one =3D 0x0},
=C2=A0 =C2=A0 =C2=A0fp_status_f16 =3D {float_detect_tininess =3D 0x1, float= _rounding_mode =3D
0x0, float_exception_flags =3D 0x0, floatx80_rounding_precision =3D 0x0, flush_to_zero =3D 0x0, flush_inputs_to_zero =3D 0x0, default_nan_mode =3D 0= x0,
=C2=A0 =C2=A0 =C2=A0 =C2=A0snan_bit_is_one =3D 0x0}, standard_fp_status =3D=
{float_detect_tininess =3D 0x1, float_rounding_mode =3D 0x0,
float_exception_flags =3D 0x0, floatx80_rounding_precision =3D 0x0,
flush_to_zero =3D 0x1, flush_inputs_to_zero =3D 0x1,
=C2=A0 =C2=A0 =C2=A0 =C2=A0default_nan_mode =3D 0x1, snan_bit_is_one =3D 0x= 0}, zcr_el =3D {0x0,
0x0, 0x0, 0x0}}, exclusive_addr =3D 0xffffffffffffffff, exclusive_val =3D <= br> 0x0, exclusive_high =3D 0x0, iwmmxt =3D {regs =3D {0x0 <repeats 16 times= >},
val =3D 0x0, cregs =3D {
=C2=A0 =C2=A0 =C2=A0 =C2=A00x0 <repeats 16 times>}}, cpu_breakpoint = =3D {0x0 <repeats 16
times>}, cpu_watchpoint =3D {0x0 <repeats 16 times>}, end_reset_fi= elds =3D
{<No data fields>}, features =3D 0xfd38fbe6f3, pmsav7 =3D {drbar =3D = 0x0, drsr
=3D 0x0, dracr =3D 0x0,
=C2=A0 =C2=A0 =C2=A0rnr =3D {0x0, 0x0}}, pmsav8 =3D {rbar =3D {0x0, 0x0}, r= lar =3D {0x0, 0x0},
mair0 =3D {0x0, 0x0}, mair1 =3D {0x0, 0x0}}, sau =3D {rbar =3D 0x0, rlar = =3D 0x0,
rnr =3D 0x0, ctrl =3D 0x0}, nvic =3D 0x0, boot_info =3D 0x5622af3a17a0, gicv3state =3D 0x0}

> [1] http://www.orangepi.org/downloadresources/ > [2] https://buildroot.org/download.html
> [3] https://www.armbian.com/orange-pi-pc/



--
--0000000000005c0a4a0598d1aa1b-- From MAILER-DAEMON Tue Dec 03 14:33:09 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1icDv3-00061R-E1 for mharc-qemu-arm@gnu.org; Tue, 03 Dec 2019 14:33:09 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:51235) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1icDux-0005v1-KU for qemu-arm@nongnu.org; Tue, 03 Dec 2019 14:33:04 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1icDus-00078T-5f for qemu-arm@nongnu.org; Tue, 03 Dec 2019 14:33:00 -0500 Received: from mail-io1-xd41.google.com ([2607:f8b0:4864:20::d41]:35818) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1icDuk-0005gv-OG; Tue, 03 Dec 2019 14:32:50 -0500 Received: by mail-io1-xd41.google.com with SMTP id v18so5132952iol.2; Tue, 03 Dec 2019 11:32:40 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=t5NL6mvqL5yVtcAOIAakNXXJi3byViXFQ5xzYZoL4+I=; b=ojQQysNDES/TTydF1eJA4NfyZk9a5YxTrlS79/TE6LG88x+Pj+gHEqZx3vGw4hBOk6 aq4w2M3c1H7TFh6CpwIoBWqm39hRW5coOzjigf0eS1cRvdCsrMAYKIeK8JYl96mqQcWa H92eI04IQL4rF56pAUnOqfcVJsjNVHyua7whr0K3edERJVNjMuV1pFzQIKCQDxv2A48d y5TkVA9QNY7T/gF74Cd8CP+wJ3pqtTkqz8e1CTRfKxbV3bnmNFBIk/vgUnAfsf9TnEwl EssJ+wZEDLOcY5RJUkaUIWJ8JWYKkhjEIerASifQUQIi1bgxCewp28UKJuzEWS43NAKk ziMQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=t5NL6mvqL5yVtcAOIAakNXXJi3byViXFQ5xzYZoL4+I=; b=Xmupn/OhoBfdFbpceVSCw7OUVBZGRtfaz0/EdgnnRLeI24uvKft5XIRjYLQhty8h26 2F86gN51UJ1iNTvXfZWvzM3Dp9cPyO9xyEaHMGArNpJQCbAqKqLRrNqEA+0hybEJeEv8 fPstmrfayyprE6saWXsaAeQyHl2L/NTecWViTdGRNxsIHva/8RlbYgXvKovRJIWUvN7E KCKJa5zIqpeXXKRJcogTliNbEqk+nM1o55K6inytGCJ+7HaRfeWq+hVfzghcv+o4eA+6 HhrM/aIJEXhupoz7D8DuUQUUnbyPYbjVK8edgTLcqLE/KViBkKthIx4nPjVcDdNj6G1K dzfw== X-Gm-Message-State: APjAAAUsSBXrNJey5CKWGiSCJqeszcAg1fPcIkSGx8tFXk8hOBC6JOG3 8tFdwTupDQkYsb1DmuRod9CrHiTtta8Qt3+1oNo= X-Google-Smtp-Source: APXvYqx30guA7t3cMMjPaIYO+QxahhhX7rqGqPpnkPh6g6mptrkQWojaM2awR2uSw7uJpfN/s/6bCz6oIhk6y+TK/0g= X-Received: by 2002:a5d:8f17:: with SMTP id f23mr3577178iof.265.1575401558814; Tue, 03 Dec 2019 11:32:38 -0800 (PST) MIME-Version: 1.0 References: <20191202210947.3603-1-nieklinnenbank@gmail.com> <1de57227-8124-4d11-d996-9faf67b3e4f3@redhat.com> In-Reply-To: <1de57227-8124-4d11-d996-9faf67b3e4f3@redhat.com> From: Niek Linnenbank Date: Tue, 3 Dec 2019 20:32:27 +0100 Message-ID: Subject: Re: [PATCH 00/10] Add Allwinner H3 SoC and Orange Pi PC Machine To: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= Cc: qemu-devel@nongnu.org, b.galvani@gmail.com, Peter Maydell , qemu-arm@nongnu.org, Richard Henderson , KONRAD Frederic , Alistair Francis , =?UTF-8?Q?Niccol=C3=B2_Izzo?= Content-Type: multipart/alternative; boundary="0000000000004ab92a0598d1c28d" X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::d41 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 03 Dec 2019 19:33:05 -0000 --0000000000004ab92a0598d1c28d Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Hello Philippe, On Tue, Dec 3, 2019 at 10:02 AM Philippe Mathieu-Daud=C3=A9 wrote: > On 12/2/19 10:09 PM, Niek Linnenbank wrote: > > Dear QEMU developers, > > > > Hereby I would like to contribute the following set of patches to QEMU > > which add support for the Allwinner H3 System on Chip and the > > Orange Pi PC machine. The following features and devices are supported: > > > > * SMP (Quad Core Cortex A7) > > * Generic Interrupt Controller configuration > > * SRAM mappings > > * Timer device (re-used from Allwinner A10) > > * UART > > * SD/MMC storage controller > > * EMAC ethernet connectivity > > * USB 2.0 interfaces > > * Clock Control Unit > > * System Control module > > * Security Identifier device > > > > Functionality related to graphical output such as HDMI, GPU, > > Display Engine and audio are not included. > > I'd love to see the OpenRISC AR100 core instantiated in this SoC. > > Your contribution makes another good example of multi-arch/single-binary > QEMU (here 4x ARM + 1x OpenRISC). > > Indeed that sounds like an interesting combination. Are there plans to build a multi-arch/single-binary QEMU? I have not looked yet at that part of the H3, but there is some documention available here on this wiki: https://linux-sunxi.org/AR100 Regards, Niek --=20 Niek Linnenbank WWW: http://www.nieklinnenbank.nl/ BLOG: http://nieklinnenbank.wordpress.com/ FUN: http://www.FreeNOS.org/ --0000000000004ab92a0598d1c28d Content-Type: text/html; charset="UTF-8" Content-Transfer-Encoding: quoted-printable
Hello Philippe,

On Tue, Dec 3, 2019 at 10:02 AM Ph= ilippe Mathieu-Daud=C3=A9 <philmd@r= edhat.com> wrote:
On 12/2/19 10:09 PM, Niek Linnenbank wrote:
> Dear QEMU developers,
>
> Hereby I would like to contribute the following set of patches to QEMU=
> which add support for the Allwinner H3 System on Chip and the
> Orange Pi PC machine. The following features and devices are supported= :
>
>=C2=A0 =C2=A0* SMP (Quad Core Cortex A7)
>=C2=A0 =C2=A0* Generic Interrupt Controller configuration
>=C2=A0 =C2=A0* SRAM mappings
>=C2=A0 =C2=A0* Timer device (re-used from Allwinner A10)
>=C2=A0 =C2=A0* UART
>=C2=A0 =C2=A0* SD/MMC storage controller
>=C2=A0 =C2=A0* EMAC ethernet connectivity
>=C2=A0 =C2=A0* USB 2.0 interfaces
>=C2=A0 =C2=A0* Clock Control Unit
>=C2=A0 =C2=A0* System Control module
>=C2=A0 =C2=A0* Security Identifier device
>
> Functionality related to graphical output such as HDMI, GPU,
> Display Engine and audio are not included.

I'd love to see the OpenRISC AR100 core instantiated in this SoC.

Your contribution makes another good example of multi-arch/single-binary QEMU (here 4x ARM + 1x OpenRISC).


Indeed that sounds like an interesti= ng combination. Are there plans to build a multi-arch/single-binary QEMU?
I have not looked yet at that part of the H3, but there is som= e documention available here on this wiki:

=
Regards,
Niek

--
<= /div> --0000000000004ab92a0598d1c28d-- From MAILER-DAEMON Tue Dec 03 14:34:36 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1icDwS-0006z7-IW for mharc-qemu-arm@gnu.org; Tue, 03 Dec 2019 14:34:36 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:53986) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1icDwK-0006pW-Ik for qemu-arm@nongnu.org; Tue, 03 Dec 2019 14:34:34 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1icDwB-0002Po-Cr for qemu-arm@nongnu.org; Tue, 03 Dec 2019 14:34:22 -0500 Received: from mail-il1-x141.google.com ([2607:f8b0:4864:20::141]:35647) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1icDvz-00010X-E3; Tue, 03 Dec 2019 14:34:07 -0500 Received: by mail-il1-x141.google.com with SMTP id g12so4288069ild.2; Tue, 03 Dec 2019 11:33:59 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=RElXdVy5CUpWdVkjnm5HwIkcJk5yE+QhvD9DsgucomA=; b=GoV6+QIpGPUw5BGq+W7IAyXX30FxUInuY58VMoYCI7L0edp2vq9/TnpC1VHzX1h3pP j9B23ARkva6gmh7DaAAyLSB68tX1WkF1Km+004UPh79Ehi5S0icVyMtpfLvND/NGhrWb hLn9sC39xF5emB5zVR++FbxrgMHJp3aF2WNegWs7St7/iUYR8MbjhdT+fU5hHid5Ef76 dD/I59zRhi8UnYBqpntMwSRH/lEJ2l6MSsZqlWMlrhy7pzBIUjSpopQqPBZBxUVmozth 49FRvQqwLC/rHwmlqv389Hx/jmldMwugIpE4HzlqkW1bApGD9NBxe9UENpLETNzwtyu0 AWgw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=RElXdVy5CUpWdVkjnm5HwIkcJk5yE+QhvD9DsgucomA=; b=M7q8+BI/zSIczdiO5qRdZeZxxd7Xmov5kGdYxX7l74yyEVjGil/VEBD0EL2hAhewq0 cUMLaTONcBeOiC3bwdi1ZheawmOIr0/gl8AW29ADK42ucmNAuqXMNV+9QW4uLO5IliQy 1mz8SWvuDf+Mo4i8JUHBmUBhZdQn3iIn1fbquFQJ7XskNEmAvqxDHD7st5ty2MTcabIp zFTcgevAulOzd4WYME8Qb3Wb+YiUIy+IrfztaHnmY64cS4gPjnOYVPtqi7uScms79Y9U DW1d7f+zl9oqps3CEnq4o4/BWZgwGjA86DTue1UbSXz9vfjI/w3OHEfjpa6fIcwCS8f/ P0xg== X-Gm-Message-State: APjAAAXE3THeOwqgm+BIEtn00tyD+9IBTDQv3gZrha9CaSjdUJzL1o9H I8eu2DzM9tyiLmtxnbalhJd0zWd8cMp9T3TySEE= X-Google-Smtp-Source: APXvYqyGHOaDPZMyNU7wsswKZ3vQ0E2RyTsfoc31r5e3/lSZxNrMrieOCfdPuwQ1pVpKRGOtoKzOFRTiY/EPdbLktXM= X-Received: by 2002:a92:d5cf:: with SMTP id d15mr6009545ilq.306.1575401638468; Tue, 03 Dec 2019 11:33:58 -0800 (PST) MIME-Version: 1.0 References: <20191202210947.3603-1-nieklinnenbank@gmail.com> <20191202210947.3603-3-nieklinnenbank@gmail.com> In-Reply-To: From: Niek Linnenbank Date: Tue, 3 Dec 2019 20:33:47 +0100 Message-ID: Subject: Re: [PATCH 02/10] hw: arm: add Xunlong Orange Pi PC machine To: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= Cc: qemu-devel@nongnu.org, b.galvani@gmail.com, Peter Maydell , qemu-arm@nongnu.org Content-Type: multipart/alternative; boundary="0000000000000a20df0598d1c71e" X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::141 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 03 Dec 2019 19:34:34 -0000 --0000000000000a20df0598d1c71e Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Hello Philippe, Thanks for your quick review comments! I'll start working on a v2 of the patches and include the changes you suggested. Regards, Niek On Tue, Dec 3, 2019 at 10:18 AM Philippe Mathieu-Daud=C3=A9 wrote: > On 12/2/19 10:09 PM, Niek Linnenbank wrote: > > The Xunlong Orange Pi PC is an Allwinner H3 System on Chip > > based embedded computer with mainline support in both U-Boot > > and Linux. The board comes with a Quad Core Cortex A7 @ 1.3GHz, > > 512MB RAM, 100Mbit ethernet, USB, SD/MMC, USB, HDMI and > > various other I/O. This commit add support for the Xunlong > > Orange Pi PC machine. > > > > Signed-off-by: Niek Linnenbank > > --- > > MAINTAINERS | 1 + > > hw/arm/Makefile.objs | 2 +- > > hw/arm/orangepi.c | 90 +++++++++++++++++++++++++++++++++++++++++++= + > > 3 files changed, 92 insertions(+), 1 deletion(-) > > create mode 100644 hw/arm/orangepi.c > > > > diff --git a/MAINTAINERS b/MAINTAINERS > > index 29c9936037..42c913d6cb 100644 > > --- a/MAINTAINERS > > +++ b/MAINTAINERS > > @@ -485,6 +485,7 @@ L: qemu-arm@nongnu.org > > S: Maintained > > F: hw/*/allwinner-h3* > > F: include/hw/*/allwinner-h3* > > +F: hw/arm/orangepi.c > > > > ARM PrimeCell and CMSDK devices > > M: Peter Maydell > > diff --git a/hw/arm/Makefile.objs b/hw/arm/Makefile.objs > > index 956e496052..8d5ea453d5 100644 > > --- a/hw/arm/Makefile.objs > > +++ b/hw/arm/Makefile.objs > > @@ -34,7 +34,7 @@ obj-$(CONFIG_DIGIC) +=3D digic.o > > obj-$(CONFIG_OMAP) +=3D omap1.o omap2.o > > obj-$(CONFIG_STRONGARM) +=3D strongarm.o > > obj-$(CONFIG_ALLWINNER_A10) +=3D allwinner-a10.o cubieboard.o > > -obj-$(CONFIG_ALLWINNER_H3) +=3D allwinner-h3.o > > +obj-$(CONFIG_ALLWINNER_H3) +=3D allwinner-h3.o orangepi.o > > obj-$(CONFIG_RASPI) +=3D bcm2835_peripherals.o bcm2836.o raspi.o > > obj-$(CONFIG_STM32F205_SOC) +=3D stm32f205_soc.o > > obj-$(CONFIG_XLNX_ZYNQMP_ARM) +=3D xlnx-zynqmp.o xlnx-zcu102.o > > diff --git a/hw/arm/orangepi.c b/hw/arm/orangepi.c > > new file mode 100644 > > index 0000000000..5ef2735f81 > > --- /dev/null > > +++ b/hw/arm/orangepi.c > > @@ -0,0 +1,90 @@ > > +/* > > + * Orange Pi emulation > > + * > > + * Copyright (C) 2019 Niek Linnenbank > > + * > > + * This program is free software: you can redistribute it and/or modif= y > > + * it under the terms of the GNU General Public License as published b= y > > + * the Free Software Foundation, either version 2 of the License, or > > + * (at your option) any later version. > > + * > > + * This program is distributed in the hope that it will be useful, > > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > > + * GNU General Public License for more details. > > + * > > + * You should have received a copy of the GNU General Public License > > + * along with this program. If not, see >. > > + */ > > + > > +#include "qemu/osdep.h" > > +#include "exec/address-spaces.h" > > +#include "qapi/error.h" > > +#include "cpu.h" > > +#include "hw/sysbus.h" > > +#include "hw/boards.h" > > +#include "hw/qdev-properties.h" > > +#include "hw/arm/allwinner-h3.h" > > + > > +static struct arm_boot_info orangepi_binfo =3D { > > + .loader_start =3D AW_H3_SDRAM_BASE, > > + .board_id =3D -1, > > +}; > > + > > +typedef struct OrangePiState { > > + AwH3State *h3; > > + MemoryRegion sdram; > > +} OrangePiState; > > + > > +static void orangepi_init(MachineState *machine) > > +{ > > + OrangePiState *s =3D g_new(OrangePiState, 1); > > + Error *err =3D NULL; > > + > > Here I'd add: > > if (strcmp(machine->cpu_type, ARM_CPU_TYPE_NAME("cortex-a7")) !=3D= 0) > { > error_report("This board can only be used with cortex-a7 CPU")= ; > exit(1); > } > > > + s->h3 =3D AW_H3(object_new(TYPE_AW_H3)); > > + > > + /* Setup timer properties */ > > + object_property_set_int(OBJECT(&s->h3->timer), 32768, "clk0-freq", > &err); > > + if (err !=3D NULL) { > > + error_reportf_err(err, "Couldn't set clk0 frequency: "); > > + exit(1); > > + } > > + > > + object_property_set_int(OBJECT(&s->h3->timer), 24000000, > "clk1-freq", > > + &err); > > + if (err !=3D NULL) { > > + error_reportf_err(err, "Couldn't set clk1 frequency: "); > > + exit(1); > > + } > > + > > + /* Mark H3 object realized */ > > + object_property_set_bool(OBJECT(s->h3), true, "realized", &err); > > I'm not sure if that's correct but I'd simply use &error_abort here. > > > + if (err !=3D NULL) { > > + error_reportf_err(err, "Couldn't realize Allwinner H3: "); > > + exit(1); > > + } > > + > > + /* RAM */ > > + memory_region_allocate_system_memory(&s->sdram, NULL, > "orangepi.ram", > > + machine->ram_size); > > I'd only allow machine->ram_size =3D=3D 1 * GiB here, since the onboard D= RAM > is not upgradable. > > > + memory_region_add_subregion(get_system_memory(), AW_H3_SDRAM_BASE, > > + &s->sdram); > > + > > + /* Load target kernel */ > > + orangepi_binfo.ram_size =3D machine->ram_size; > > + orangepi_binfo.nb_cpus =3D AW_H3_NUM_CPUS; > > + arm_load_kernel(ARM_CPU(first_cpu), machine, &orangepi_binfo); > > +} > > + > > +static void orangepi_machine_init(MachineClass *mc) > > +{ > > + mc->desc =3D "Orange Pi PC"; > > + mc->init =3D orangepi_init; > > + mc->units_per_default_bus =3D 1; > > + mc->min_cpus =3D AW_H3_NUM_CPUS; > > + mc->max_cpus =3D AW_H3_NUM_CPUS; > > + mc->default_cpus =3D AW_H3_NUM_CPUS; > > mc->default_cpu_type =3D ARM_CPU_TYPE_NAME("cortex-a7"); > > > + mc->ignore_memory_transaction_failures =3D true; > > You should not use this flag in new design. See the documentation in > include/hw/boards.h: > > * @ignore_memory_transaction_failures: > * [...] New board models > * should instead use "unimplemented-device" for all memory ranges > where > * the guest will attempt to probe for a device that QEMU doesn't > * implement and a stub device is required. > > You already use the "unimplemented-device". > > > +} > > + > > +DEFINE_MACHINE("orangepi", orangepi_machine_init) > > Can you name it 'orangepi-pc'? So we can add other orangepi models. > > Thanks, > > Phil. > > --=20 Niek Linnenbank WWW: http://www.nieklinnenbank.nl/ BLOG: http://nieklinnenbank.wordpress.com/ FUN: http://www.FreeNOS.org/ --0000000000000a20df0598d1c71e Content-Type: text/html; charset="UTF-8" Content-Transfer-Encoding: quoted-printable
Hello Philippe,

Thanks for y= our quick review comments!
I'll start working on a v2 of the = patches and include the changes you suggested.

Reg= ards,
Niek

On Tue, Dec 3, 2019 at 10:18 AM Philippe Mathieu-Da= ud=C3=A9 <philmd@redhat.com>= wrote:
On 12/2/= 19 10:09 PM, Niek Linnenbank wrote:
> The Xunlong Orange Pi PC is an Allwinner H3 System on Chip
> based embedded computer with mainline support in both U-Boot
> and Linux. The board comes with a Quad Core Cortex A7 @ 1.3GHz,
> 512MB RAM, 100Mbit ethernet, USB, SD/MMC, USB, HDMI and
> various other I/O. This commit add support for the Xunlong
> Orange Pi PC machine.
>
> Signed-off-by: Niek Linnenbank <nieklinnenbank@gmail.com>
> ---
>=C2=A0 =C2=A0MAINTAINERS=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 |=C2=A0 1 +<= br> >=C2=A0 =C2=A0hw/arm/Makefile.objs |=C2=A0 2 +-
>=C2=A0 =C2=A0hw/arm/orangepi.c=C2=A0 =C2=A0 | 90 ++++++++++++++++++++++= ++++++++++++++++++++++
>=C2=A0 =C2=A03 files changed, 92 insertions(+), 1 deletion(-)
>=C2=A0 =C2=A0create mode 100644 hw/arm/orangepi.c
>
> diff --git a/MAINTAINERS b/MAINTAINERS
> index 29c9936037..42c913d6cb 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -485,6 +485,7 @@ L: qemu-arm@nongnu.org
>=C2=A0 =C2=A0S: Maintained
>=C2=A0 =C2=A0F: hw/*/allwinner-h3*
>=C2=A0 =C2=A0F: include/hw/*/allwinner-h3*
> +F: hw/arm/orangepi.c
>=C2=A0 =C2=A0
>=C2=A0 =C2=A0ARM PrimeCell and CMSDK devices
>=C2=A0 =C2=A0M: Peter Maydell <peter.maydell@linaro.org>
> diff --git a/hw/arm/Makefile.objs b/hw/arm/Makefile.objs
> index 956e496052..8d5ea453d5 100644
> --- a/hw/arm/Makefile.objs
> +++ b/hw/arm/Makefile.objs
> @@ -34,7 +34,7 @@ obj-$(CONFIG_DIGIC) +=3D digic.o
>=C2=A0 =C2=A0obj-$(CONFIG_OMAP) +=3D omap1.o omap2.o
>=C2=A0 =C2=A0obj-$(CONFIG_STRONGARM) +=3D strongarm.o
>=C2=A0 =C2=A0obj-$(CONFIG_ALLWINNER_A10) +=3D allwinner-a10.o cubieboar= d.o
> -obj-$(CONFIG_ALLWINNER_H3) +=3D allwinner-h3.o
> +obj-$(CONFIG_ALLWINNER_H3) +=3D allwinner-h3.o orangepi.o
>=C2=A0 =C2=A0obj-$(CONFIG_RASPI) +=3D bcm2835_peripherals.o bcm2836.o r= aspi.o
>=C2=A0 =C2=A0obj-$(CONFIG_STM32F205_SOC) +=3D stm32f205_soc.o
>=C2=A0 =C2=A0obj-$(CONFIG_XLNX_ZYNQMP_ARM) +=3D xlnx-zynqmp.o xlnx-zcu1= 02.o
> diff --git a/hw/arm/orangepi.c b/hw/arm/orangepi.c
> new file mode 100644
> index 0000000000..5ef2735f81
> --- /dev/null
> +++ b/hw/arm/orangepi.c
> @@ -0,0 +1,90 @@
> +/*
> + * Orange Pi emulation
> + *
> + * Copyright (C) 2019 Niek Linnenbank <nieklinnenbank@gmail.com>
> + *
> + * This program is free software: you can redistribute it and/or modi= fy
> + * it under the terms of the GNU General Public License as published = by
> + * the Free Software Foundation, either version 2 of the License, or<= br> > + * (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful, > + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.=C2=A0 See the=
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License<= br> > + * along with this program.=C2=A0 If not, see <http://www.gnu.o= rg/licenses/>.
> + */
> +
> +#include "qemu/osdep.h"
> +#include "exec/address-spaces.h"
> +#include "qapi/error.h"
> +#include "cpu.h"
> +#include "hw/sysbus.h"
> +#include "hw/boards.h"
> +#include "hw/qdev-properties.h"
> +#include "hw/arm/allwinner-h3.h"
> +
> +static struct arm_boot_info orangepi_binfo =3D {
> +=C2=A0 =C2=A0 .loader_start =3D AW_H3_SDRAM_BASE,
> +=C2=A0 =C2=A0 .board_id =3D -1,
> +};
> +
> +typedef struct OrangePiState {
> +=C2=A0 =C2=A0 AwH3State *h3;
> +=C2=A0 =C2=A0 MemoryRegion sdram;
> +} OrangePiState;
> +
> +static void orangepi_init(MachineState *machine)
> +{
> +=C2=A0 =C2=A0 OrangePiState *s =3D g_new(OrangePiState, 1);
> +=C2=A0 =C2=A0 Error *err =3D NULL;
> +

Here I'd add:

=C2=A0 =C2=A0 =C2=A0 =C2=A0if (strcmp(machine->cpu_type, ARM_CPU_TYPE_NA= ME("cortex-a7")) !=3D 0) {
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0error_report("This board can = only be used with cortex-a7 CPU");
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0exit(1);
=C2=A0 =C2=A0 =C2=A0 =C2=A0}

> +=C2=A0 =C2=A0 s->h3 =3D AW_H3(object_new(TYPE_AW_H3));
> +
> +=C2=A0 =C2=A0 /* Setup timer properties */
> +=C2=A0 =C2=A0 object_property_set_int(OBJECT(&s->h3->timer)= , 32768, "clk0-freq", &err);
> +=C2=A0 =C2=A0 if (err !=3D NULL) {
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 error_reportf_err(err, "Couldn't= set clk0 frequency: ");
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 exit(1);
> +=C2=A0 =C2=A0 }
> +
> +=C2=A0 =C2=A0 object_property_set_int(OBJECT(&s->h3->timer)= , 24000000, "clk1-freq",
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0 =C2=A0 =C2=A0 &err);
> +=C2=A0 =C2=A0 if (err !=3D NULL) {
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 error_reportf_err(err, "Couldn't= set clk1 frequency: ");
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 exit(1);
> +=C2=A0 =C2=A0 }
> +
> +=C2=A0 =C2=A0 /* Mark H3 object realized */
> +=C2=A0 =C2=A0 object_property_set_bool(OBJECT(s->h3), true, "= realized", &err);

I'm not sure if that's correct but I'd simply use &error_ab= ort here.

> +=C2=A0 =C2=A0 if (err !=3D NULL) {
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 error_reportf_err(err, "Couldn't= realize Allwinner H3: ");
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 exit(1);
> +=C2=A0 =C2=A0 }
> +
> +=C2=A0 =C2=A0 /* RAM */
> +=C2=A0 =C2=A0 memory_region_allocate_system_memory(&s->sdram, = NULL, "orangepi.ram",
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0machine->ram_size);

I'd only allow machine->ram_size =3D=3D 1 * GiB here, since the onbo= ard DRAM
is not upgradable.

> +=C2=A0 =C2=A0 memory_region_add_subregion(get_system_memory(), AW_H3_= SDRAM_BASE,
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 &s->sdram);
> +
> +=C2=A0 =C2=A0 /* Load target kernel */
> +=C2=A0 =C2=A0 orangepi_binfo.ram_size =3D machine->ram_size;
> +=C2=A0 =C2=A0 orangepi_binfo.nb_cpus=C2=A0 =3D AW_H3_NUM_CPUS;
> +=C2=A0 =C2=A0 arm_load_kernel(ARM_CPU(first_cpu), machine, &orang= epi_binfo);
> +}
> +
> +static void orangepi_machine_init(MachineClass *mc)
> +{
> +=C2=A0 =C2=A0 mc->desc =3D "Orange Pi PC";
> +=C2=A0 =C2=A0 mc->init =3D orangepi_init;
> +=C2=A0 =C2=A0 mc->units_per_default_bus =3D 1;
> +=C2=A0 =C2=A0 mc->min_cpus =3D AW_H3_NUM_CPUS;
> +=C2=A0 =C2=A0 mc->max_cpus =3D AW_H3_NUM_CPUS;
> +=C2=A0 =C2=A0 mc->default_cpus =3D AW_H3_NUM_CPUS;

=C2=A0 =C2=A0 =C2=A0 =C2=A0 mc->default_cpu_type =3D ARM_CPU_TYPE_NAME(&= quot;cortex-a7");

> +=C2=A0 =C2=A0 mc->ignore_memory_transaction_failures =3D true;

You should not use this flag in new design. See the documentation in
include/hw/boards.h:

=C2=A0 * @ignore_memory_transaction_failures:
=C2=A0 *=C2=A0 =C2=A0 [...] New board models
=C2=A0 *=C2=A0 =C2=A0 should instead use "unimplemented-device" f= or all memory ranges where
=C2=A0 *=C2=A0 =C2=A0 the guest will attempt to probe for a device that QEM= U doesn't
=C2=A0 *=C2=A0 =C2=A0 implement and a stub device is required.

You already use the "unimplemented-device".

> +}
> +
> +DEFINE_MACHINE("orangepi", orangepi_machine_init)

Can you name it 'orangepi-pc'? So we can add other orangepi models.=

Thanks,

Phil.



--
--0000000000000a20df0598d1c71e-- From MAILER-DAEMON Tue Dec 03 14:51:35 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1icECt-0005vp-Pr for mharc-qemu-arm@gnu.org; Tue, 03 Dec 2019 14:51:35 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:38212) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1icECj-0005hv-P4 for qemu-arm@nongnu.org; Tue, 03 Dec 2019 14:51:34 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1icE4C-0005s3-9k for qemu-arm@nongnu.org; Tue, 03 Dec 2019 14:42:44 -0500 Received: from mail-il1-x132.google.com ([2607:f8b0:4864:20::132]:45118) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1icE41-0004ti-45; Tue, 03 Dec 2019 14:42:25 -0500 Received: by mail-il1-x132.google.com with SMTP id p8so283979iln.12; Tue, 03 Dec 2019 11:42:09 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=b+beXecnhfj+JkB7YzqTh8c1TSx+LJCxVTLV6WMXZik=; b=GcNyh1b2pDdakLjTXDoomoSRjTQ2xIzvyjO6jzZfBoRyIvNfb7iYgPx9fJnLSpXdYS fBU08mBgh6xRhREAYWBL0PhyLWFJ4Hp6bi/pgc5CpvmBSAfkBvjm8FoIL8DiUTKAyheu +fgfrKhBwHqeO1PX7wNvvzle7CPfB0nYWgv2Nkptlhb8iWDouJGKG5ERW3Zys8ymC5R1 wdgo7ZHWqmTgDi+cqSX0NI3ADkj4J2SYTLYlZFKmptB47KrHALyT5UJWvjy2CWZSSa7k Ji3D/arYiTl47F8xsqGxRNBidOgEMB4zhEo7ILBBkZLXYnckTz9lPseifkiNsD2hpepx mIXA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=b+beXecnhfj+JkB7YzqTh8c1TSx+LJCxVTLV6WMXZik=; b=KGInJQSdtFQ9Wcko49BRgnbikD32Mm7XG1UmfOZBLRG2pdu3mc0se60BfKz05wuHN5 Fe/FHeKFWUYLnbGNqutM4VwVypEKS2C1If01cwqKQ27AtXU66J/rcdTe/q3DMRgk9kiM FAWbexhdnhHVrZzokAshwV+TBHJAleHxKY8z9X8ROGK4sHmpbyOGJG6NZINu7A0k62DB Rd+8lmvW7ghZDI30DtNeWwYgkFoDE8fKaekFPZRtqmoKBRolki3QoYVsZp4iw+BqJzNM b9g9ERduZI6yf2dcCdF0WR0Ezd/GIpmymyaPyFi8cyevwBsQkPLXDRqAA8wiprRUoX2R sUWw== X-Gm-Message-State: APjAAAVa/aDYlv8O0KpHG4GOV6pLZVrb/h6G50Q8SyQklLkjovpfhzhQ jxdw7v+tqAElV0G+SRzKsuQTQ4jfPLEjxb62rKw= X-Google-Smtp-Source: APXvYqwaP0ti2B+IOjSzWQXDmwNzeiQJ1UUGKHU8oP6ggtM3ZQb2FGP7SAttjyTvgGvss8g/1uPUy+ymv3pfrTqOH4g= X-Received: by 2002:a92:af08:: with SMTP id n8mr6132015ili.217.1575402127837; Tue, 03 Dec 2019 11:42:07 -0800 (PST) MIME-Version: 1.0 References: <20191202210947.3603-1-nieklinnenbank@gmail.com> <20191202210947.3603-11-nieklinnenbank@gmail.com> In-Reply-To: From: Niek Linnenbank Date: Tue, 3 Dec 2019 20:41:56 +0100 Message-ID: Subject: Re: [PATCH 10/10] arm: allwinner-h3: add EMAC ethernet device To: KONRAD Frederic Cc: qemu-devel@nongnu.org, b.galvani@gmail.com, Peter Maydell , qemu-arm@nongnu.org Content-Type: multipart/alternative; boundary="000000000000354d600598d1e4fc" X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::132 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 03 Dec 2019 19:51:34 -0000 --000000000000354d600598d1e4fc Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Hello Frederic, Thank you for your quick review comments! I'll start working on v2 of the patches and include the changes you suggested. On Tue, Dec 3, 2019 at 10:33 AM KONRAD Frederic wrote: > > > Le 12/2/19 =C3=A0 10:09 PM, Niek Linnenbank a =C3=A9crit : > > The Allwinner H3 System on Chip includes an Ethernet MAC (EMAC) > > which provides 10M/100M/1000M Ethernet connectivity. This commit > > adds support for the Allwinner H3 EMAC, including emulation for > > the following functionality: > > > > * DMA transfers > > * MII interface > > * Transmit CRC calculation > > > > Signed-off-by: Niek Linnenbank > > --- > > hw/arm/Kconfig | 1 + > > hw/arm/allwinner-h3.c | 17 + > > hw/arm/orangepi.c | 7 + > > hw/net/Kconfig | 3 + > > hw/net/Makefile.objs | 1 + > > hw/net/allwinner-h3-emac.c | 786 ++++++++++++++++++++++++++++= + > > hw/net/trace-events | 10 + > > include/hw/arm/allwinner-h3.h | 2 + > > include/hw/net/allwinner-h3-emac.h | 69 +++ > > 9 files changed, 896 insertions(+) > > create mode 100644 hw/net/allwinner-h3-emac.c > > create mode 100644 include/hw/net/allwinner-h3-emac.h > > > > diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig > > index ebf8d2325f..551cff3442 100644 > > --- a/hw/arm/Kconfig > > +++ b/hw/arm/Kconfig > > @@ -294,6 +294,7 @@ config ALLWINNER_A10 > > config ALLWINNER_H3 > > bool > > select ALLWINNER_A10_PIT > > + select ALLWINNER_H3_EMAC > > select SERIAL > > select ARM_TIMER > > select ARM_GIC > > diff --git a/hw/arm/allwinner-h3.c b/hw/arm/allwinner-h3.c > > index c2972caf88..274b8548c0 100644 > > --- a/hw/arm/allwinner-h3.c > > +++ b/hw/arm/allwinner-h3.c > > @@ -53,6 +53,9 @@ static void aw_h3_init(Object *obj) > > > > sysbus_init_child_obj(obj, "mmc0", &s->mmc0, sizeof(s->mmc0), > > TYPE_AW_H3_SDHOST); > > + > > + sysbus_init_child_obj(obj, "emac", &s->emac, sizeof(s->emac), > > + TYPE_AW_H3_EMAC); > > } > > > > static void aw_h3_realize(DeviceState *dev, Error **errp) > > @@ -237,6 +240,20 @@ static void aw_h3_realize(DeviceState *dev, Error > **errp) > > return; > > } > > > > + /* EMAC */ > > + if (nd_table[0].used) { > > + qemu_check_nic_model(&nd_table[0], TYPE_AW_H3_EMAC); > > + qdev_set_nic_properties(DEVICE(&s->emac), &nd_table[0]); > > + } > > + object_property_set_bool(OBJECT(&s->emac), true, "realized", &err)= ; > > + if (err !=3D NULL) { > > + error_propagate(errp, err); > > + return; > > + } > > + sysbusdev =3D SYS_BUS_DEVICE(&s->emac); > > + sysbus_mmio_map(sysbusdev, 0, AW_H3_EMAC_BASE); > > + sysbus_connect_irq(sysbusdev, 0, s->irq[AW_H3_GIC_SPI_EMAC]); > > + > > /* Universal Serial Bus */ > > sysbus_create_simple(TYPE_AW_H3_EHCI, AW_H3_EHCI0_BASE, > > s->irq[AW_H3_GIC_SPI_EHCI0]); > > diff --git a/hw/arm/orangepi.c b/hw/arm/orangepi.c > > index dee3efaf08..8a61eb0e69 100644 > > --- a/hw/arm/orangepi.c > > +++ b/hw/arm/orangepi.c > > @@ -61,6 +61,13 @@ static void orangepi_init(MachineState *machine) > > exit(1); > > } > > > > + /* Setup EMAC properties */ > > + object_property_set_int(OBJECT(&s->h3->emac), 1, "phy-addr", &err)= ; > > + if (err !=3D NULL) { > > + error_reportf_err(err, "Couldn't set phy address: "); > > + exit(1); > > + } > > + > > /* Mark H3 object realized */ > > object_property_set_bool(OBJECT(s->h3), true, "realized", &err); > > if (err !=3D NULL) { > > diff --git a/hw/net/Kconfig b/hw/net/Kconfig > > index 3856417d42..36d3923992 100644 > > --- a/hw/net/Kconfig > > +++ b/hw/net/Kconfig > > @@ -74,6 +74,9 @@ config MIPSNET > > config ALLWINNER_EMAC > > bool > > > > +config ALLWINNER_H3_EMAC > > + bool > > + > > config IMX_FEC > > bool > > > > diff --git a/hw/net/Makefile.objs b/hw/net/Makefile.objs > > index 7907d2c199..5548deb07a 100644 > > --- a/hw/net/Makefile.objs > > +++ b/hw/net/Makefile.objs > > @@ -23,6 +23,7 @@ common-obj-$(CONFIG_XGMAC) +=3D xgmac.o > > common-obj-$(CONFIG_MIPSNET) +=3D mipsnet.o > > common-obj-$(CONFIG_XILINX_AXI) +=3D xilinx_axienet.o > > common-obj-$(CONFIG_ALLWINNER_EMAC) +=3D allwinner_emac.o > > +common-obj-$(CONFIG_ALLWINNER_H3_EMAC) +=3D allwinner-h3-emac.o > > common-obj-$(CONFIG_IMX_FEC) +=3D imx_fec.o > > > > common-obj-$(CONFIG_CADENCE) +=3D cadence_gem.o > > diff --git a/hw/net/allwinner-h3-emac.c b/hw/net/allwinner-h3-emac.c > > new file mode 100644 > > index 0000000000..37f6f44406 > > --- /dev/null > > +++ b/hw/net/allwinner-h3-emac.c > > @@ -0,0 +1,786 @@ > > +/* > > + * Allwinner H3 EMAC emulation > > + * > > + * Copyright (C) 2019 Niek Linnenbank > > + * > > + * This program is free software: you can redistribute it and/or modif= y > > + * it under the terms of the GNU General Public License as published b= y > > + * the Free Software Foundation, either version 2 of the License, or > > + * (at your option) any later version. > > + * > > + * This program is distributed in the hope that it will be useful, > > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > > + * GNU General Public License for more details. > > + * > > + * You should have received a copy of the GNU General Public License > > + * along with this program. If not, see >. > > + */ > > + > > +#include "qemu/osdep.h" > > +#include "hw/sysbus.h" > > +#include "migration/vmstate.h" > > +#include "net/net.h" > > +#include "hw/irq.h" > > +#include "hw/qdev-properties.h" > > +#include "qemu/log.h" > > +#include "trace.h" > > +#include "net/checksum.h" > > +#include "qemu/module.h" > > +#include "exec/cpu-common.h" > > +#include "hw/net/allwinner-h3-emac.h" > > + > > +/* EMAC register offsets */ > > +#define REG_BASIC_CTL_0 (0x0000) /* Basic Control 0 */ > > +#define REG_BASIC_CTL_1 (0x0004) /* Basic Control 1 */ > > +#define REG_INT_STA (0x0008) /* Interrupt Status */ > > +#define REG_INT_EN (0x000C) /* Interrupt Enable */ > > +#define REG_TX_CTL_0 (0x0010) /* Transmit Control 0 */ > > +#define REG_TX_CTL_1 (0x0014) /* Transmit Control 1 */ > > +#define REG_TX_FLOW_CTL (0x001C) /* Transmit Flow Control */ > > +#define REG_TX_DMA_DESC_LIST (0x0020) /* Transmit Descriptor List > Address */ > > +#define REG_RX_CTL_0 (0x0024) /* Receive Control 0 */ > > +#define REG_RX_CTL_1 (0x0028) /* Receive Control 1 */ > > +#define REG_RX_DMA_DESC_LIST (0x0034) /* Receive Descriptor List > Address */ > > +#define REG_FRM_FLT (0x0038) /* Receive Frame Filter */ > > +#define REG_RX_HASH_0 (0x0040) /* Receive Hash Table 0 */ > > +#define REG_RX_HASH_1 (0x0044) /* Receive Hash Table 1 */ > > +#define REG_MII_CMD (0x0048) /* Management Interface Comman= d > */ > > +#define REG_MII_DATA (0x004C) /* Management Interface Data *= / > > +#define REG_ADDR_HIGH (0x0050) /* MAC Address High */ > > +#define REG_ADDR_LOW (0x0054) /* MAC Address Low */ > > +#define REG_TX_DMA_STA (0x00B0) /* Transmit DMA Status */ > > +#define REG_TX_CUR_DESC (0x00B4) /* Transmit Current Descriptor > */ > > +#define REG_TX_CUR_BUF (0x00B8) /* Transmit Current Buffer */ > > +#define REG_RX_DMA_STA (0x00C0) /* Receive DMA Status */ > > +#define REG_RX_CUR_DESC (0x00C4) /* Receive Current Descriptor = */ > > +#define REG_RX_CUR_BUF (0x00C8) /* Receive Current Buffer */ > > +#define REG_RGMII_STA (0x00D0) /* RGMII Status */ > > + > > +/* EMAC register flags */ > > +#define BASIC_CTL0_100Mbps (0b11 << 2) > > +#define BASIC_CTL0_FD (1 << 0) > > +#define BASIC_CTL1_SOFTRST (1 << 0) > > + > > +#define INT_STA_RGMII_LINK (1 << 16) > > +#define INT_STA_RX_EARLY (1 << 13) > > +#define INT_STA_RX_OVERFLOW (1 << 12) > > +#define INT_STA_RX_TIMEOUT (1 << 11) > > +#define INT_STA_RX_DMA_STOP (1 << 10) > > +#define INT_STA_RX_BUF_UA (1 << 9) > > +#define INT_STA_RX (1 << 8) > > +#define INT_STA_TX_EARLY (1 << 5) > > +#define INT_STA_TX_UNDERFLOW (1 << 4) > > +#define INT_STA_TX_TIMEOUT (1 << 3) > > +#define INT_STA_TX_BUF_UA (1 << 2) > > +#define INT_STA_TX_DMA_STOP (1 << 1) > > +#define INT_STA_TX (1 << 0) > > + > > +#define INT_EN_RX_EARLY (1 << 13) > > +#define INT_EN_RX_OVERFLOW (1 << 12) > > +#define INT_EN_RX_TIMEOUT (1 << 11) > > +#define INT_EN_RX_DMA_STOP (1 << 10) > > +#define INT_EN_RX_BUF_UA (1 << 9) > > +#define INT_EN_RX (1 << 8) > > +#define INT_EN_TX_EARLY (1 << 5) > > +#define INT_EN_TX_UNDERFLOW (1 << 4) > > +#define INT_EN_TX_TIMEOUT (1 << 3) > > +#define INT_EN_TX_BUF_UA (1 << 2) > > +#define INT_EN_TX_DMA_STOP (1 << 1) > > +#define INT_EN_TX (1 << 0) > > + > > +#define TX_CTL0_TX_EN (1 << 31) > > +#define TX_CTL1_TX_DMA_START (1 << 31) > > +#define TX_CTL1_TX_DMA_EN (1 << 30) > > +#define TX_CTL1_TX_FLUSH (1 << 0) > > + > > +#define RX_CTL0_RX_EN (1 << 31) > > +#define RX_CTL0_STRIP_FCS (1 << 28) > > +#define RX_CTL0_CRC_IPV4 (1 << 27) > > + > > +#define RX_CTL1_RX_DMA_START (1 << 31) > > +#define RX_CTL1_RX_DMA_EN (1 << 30) > > +#define RX_CTL1_RX_MD (1 << 1) > > + > > +#define RX_FRM_FLT_DIS_ADDR (1 << 31) > > + > > +#define MII_CMD_PHY_ADDR_SHIFT (12) > > +#define MII_CMD_PHY_ADDR_MASK (0xf000) > > +#define MII_CMD_PHY_REG_SHIFT (4) > > +#define MII_CMD_PHY_REG_MASK (0xf0) > > +#define MII_CMD_PHY_RW (1 << 1) > > +#define MII_CMD_PHY_BUSY (1 << 0) > > + > > +#define TX_DMA_STA_STOP (0b000) > > +#define TX_DMA_STA_RUN_FETCH (0b001) > > +#define TX_DMA_STA_WAIT_STA (0b010) > > + > > +#define RX_DMA_STA_STOP (0b000) > > +#define RX_DMA_STA_RUN_FETCH (0b001) > > +#define RX_DMA_STA_WAIT_FRM (0b011) > > + > > +#define RGMII_LINK_UP (1 << 3) > > +#define RGMII_FD (1 << 0) > > + > > +/* EMAC register reset values */ > > +#define REG_BASIC_CTL_1_RST (0x08000000) > > + > > +/* EMAC constants */ > > +#define AW_H3_EMAC_MIN_PKT_SZ (64) > > + > > +/* Transmit/receive frame descriptor */ > > +typedef struct FrameDescriptor { > > + uint32_t status; > > + uint32_t status2; > > + uint32_t addr; > > + uint32_t next; > > +} FrameDescriptor; > > + > > +/* Frame descriptor flags */ > > +#define DESC_STATUS_CTL (1 << 31) > > +#define DESC_STATUS2_BUF_SIZE_MASK (0x7ff) > > + > > +/* Transmit frame descriptor flags */ > > +#define TX_DESC_STATUS_LENGTH_ERR (1 << 14) > > +#define TX_DESC_STATUS2_FIRST_DESC (1 << 29) > > +#define TX_DESC_STATUS2_LAST_DESC (1 << 30) > > +#define TX_DESC_STATUS2_CHECKSUM_MASK (0x3 << 27) > > + > > +/* Receive frame descriptor flags */ > > +#define RX_DESC_STATUS_FIRST_DESC (1 << 9) > > +#define RX_DESC_STATUS_LAST_DESC (1 << 8) > > +#define RX_DESC_STATUS_FRM_LEN_MASK (0x3fff0000) > > +#define RX_DESC_STATUS_FRM_LEN_SHIFT (16) > > +#define RX_DESC_STATUS_NO_BUF (1 << 14) > > +#define RX_DESC_STATUS_HEADER_ERR (1 << 7) > > +#define RX_DESC_STATUS_LENGTH_ERR (1 << 4) > > +#define RX_DESC_STATUS_CRC_ERR (1 << 1) > > +#define RX_DESC_STATUS_PAYLOAD_ERR (1 << 0) > > +#define RX_DESC_STATUS2_RX_INT_CTL (1 << 31) > > + > > +/* MII register offsets */ > > +#define MII_REG_CR (0x0) > > +#define MII_REG_ST (0x1) > > +#define MII_REG_ID_HIGH (0x2) > > +#define MII_REG_ID_LOW (0x3) > > + > > +/* MII register flags */ > > +#define MII_REG_CR_RESET (1 << 15) > > +#define MII_REG_CR_POWERDOWN (1 << 11) > > +#define MII_REG_CR_10Mbit (0) > > +#define MII_REG_CR_100Mbit (1 << 13) > > +#define MII_REG_CR_1000Mbit (1 << 6) > > +#define MII_REG_CR_AUTO_NEG (1 << 12) > > +#define MII_REG_CR_AUTO_NEG_RESTART (1 << 9) > > +#define MII_REG_CR_FULLDUPLEX (1 << 8) > > + > > +#define MII_REG_ST_100BASE_T4 (1 << 15) > > +#define MII_REG_ST_100BASE_X_FD (1 << 14) > > +#define MII_REG_ST_100BASE_X_HD (1 << 13) > > +#define MII_REG_ST_10_FD (1 << 12) > > +#define MII_REG_ST_10_HD (1 << 11) > > +#define MII_REG_ST_100BASE_T2_FD (1 << 10) > > +#define MII_REG_ST_100BASE_T2_HD (1 << 9) > > +#define MII_REG_ST_AUTONEG_COMPLETE (1 << 5) > > +#define MII_REG_ST_AUTONEG_AVAIL (1 << 3) > > +#define MII_REG_ST_LINK_UP (1 << 2) > > + > > +/* MII constants */ > > +#define MII_PHY_ID_HIGH (0x0044) > > +#define MII_PHY_ID_LOW (0x1400) > > I wonder if we can't share all those mii stuff accross the network adapte= rs > instead of redoing the work everytime. I've some patches about it I may > post > them sometimes. > > Indeed, that would be a nice improvement. In fact, I was looking for somekind of MII library inside QEMU and could not find it. Then I saw that the other emulated ethernet cards all have that code inside each file, so that is why I did the same here. > > + > > +static void aw_h3_emac_mii_set_link(AwH3EmacState *s, bool link_active= ) > > +{ > > + if (link_active) { > > + s->mii_st |=3D MII_REG_ST_LINK_UP; > > + } else { > > + s->mii_st &=3D ~MII_REG_ST_LINK_UP; > > + } > > +} > > + > > +static void aw_h3_emac_mii_reset(AwH3EmacState *s, bool link_active) > > +{ > > + s->mii_cr =3D MII_REG_CR_100Mbit | MII_REG_CR_AUTO_NEG | > > + MII_REG_CR_FULLDUPLEX; > > + s->mii_st =3D MII_REG_ST_100BASE_T4 | MII_REG_ST_100BASE_X_FD | > > + MII_REG_ST_100BASE_X_HD | MII_REG_ST_10_FD | > MII_REG_ST_10_HD | > > + MII_REG_ST_100BASE_T2_FD | MII_REG_ST_100BASE_T2_HD | > > + MII_REG_ST_AUTONEG_COMPLETE | MII_REG_ST_AUTONEG_AVAIL= ; > > + > > + aw_h3_emac_mii_set_link(s, link_active); > > +} > > + > > +static void aw_h3_emac_mii_cmd(AwH3EmacState *s) > > +{ > > + uint8_t addr, reg; > > + > > + addr =3D (s->mii_cmd & MII_CMD_PHY_ADDR_MASK) >> > MII_CMD_PHY_ADDR_SHIFT; > > + reg =3D (s->mii_cmd & MII_CMD_PHY_REG_MASK) >> MII_CMD_PHY_REG_SHI= FT; > > + > > + if (addr !=3D s->mii_phy_addr) { > > + return; > > + } > > + > > + /* Read or write a PHY register? */ > > + if (s->mii_cmd & MII_CMD_PHY_RW) { > > + trace_aw_h3_emac_mii_write_reg(reg, s->mii_data); > > + > > + switch (reg) { > > + case MII_REG_CR: > > + if (s->mii_data & MII_REG_CR_RESET) { > > + aw_h3_emac_mii_reset(s, s->mii_st & MII_REG_ST_LINK_UP= ); > > + } else { > > + s->mii_cr =3D s->mii_data & ~(MII_REG_CR_RESET | > > + > MII_REG_CR_AUTO_NEG_RESTART); > > + } > > + break; > > + default: > > + qemu_log_mask(LOG_UNIMP, "allwinner-h3-emac: write access > to " > > + "unknown MII register 0x%x\n", > reg); > > + break; > > + } > > + } else { > > + switch (reg) { > > + case MII_REG_CR: > > + s->mii_data =3D s->mii_cr; > > + break; > > + case MII_REG_ST: > > + s->mii_data =3D s->mii_st; > > + break; > > + case MII_REG_ID_HIGH: > > + s->mii_data =3D MII_PHY_ID_HIGH; > > + break; > > + case MII_REG_ID_LOW: > > + s->mii_data =3D MII_PHY_ID_LOW; > > + break; > > + default: > > + qemu_log_mask(LOG_UNIMP, "allwinner-h3-emac: read access t= o > " > > + "unknown MII register 0x%x\n", > reg); > > + s->mii_data =3D 0; > > + break; > > + } > > + > > + trace_aw_h3_emac_mii_read_reg(reg, s->mii_data); > > + } > > +} > > + > > +static void aw_h3_emac_update_irq(AwH3EmacState *s) > > +{ > > + qemu_set_irq(s->irq, (s->int_sta & s->int_en) !=3D 0); > > +} > > + > > +static uint32_t aw_h3_emac_next_desc(FrameDescriptor *desc, size_t > min_size) > > +{ > > + uint32_t paddr =3D desc->next; > > + > > + cpu_physical_memory_read(paddr, desc, sizeof(*desc)); > > + > > + if ((desc->status & DESC_STATUS_CTL) && > > + (desc->status2 & DESC_STATUS2_BUF_SIZE_MASK) >=3D min_size) { > > + return paddr; > > + } else { > > + return 0; > > + } > > +} > > + > > +static uint32_t aw_h3_emac_get_desc(FrameDescriptor *desc, uint32_t > start_addr, > > + size_t min_size) > > +{ > > + uint32_t desc_addr =3D start_addr; > > + > > + /* Note that the list is a cycle. Last entry points back to the > head. */ > > + while (desc_addr !=3D 0) { > > + cpu_physical_memory_read(desc_addr, desc, sizeof(*desc)); > > + > > + if ((desc->status & DESC_STATUS_CTL) && > > + (desc->status2 & DESC_STATUS2_BUF_SIZE_MASK) >=3D min_size= ) { > > + return desc_addr; > > + } else if (desc->next =3D=3D start_addr) { > > + break; > > + } else { > > + desc_addr =3D desc->next; > > + } > > + } > > + > > + return 0; > > +} > > + > > +static uint32_t aw_h3_emac_get_rx_desc(AwH3EmacState *s, > FrameDescriptor *desc, > > + size_t min_size) > > +{ > > + return aw_h3_emac_get_desc(desc, s->rx_desc_curr, min_size); > > +} > > + > > +static uint32_t aw_h3_emac_get_tx_desc(AwH3EmacState *s, > FrameDescriptor *desc, > > + size_t min_size) > > +{ > > + return aw_h3_emac_get_desc(desc, s->tx_desc_head, min_size); > > +} > > + > > +static void aw_h3_emac_flush_desc(FrameDescriptor *desc, uint32_t > phys_addr) > > +{ > > + cpu_physical_memory_write(phys_addr, desc, sizeof(*desc)); > > +} > > + > > +static int aw_h3_emac_can_receive(NetClientState *nc) > > +{ > > + AwH3EmacState *s =3D qemu_get_nic_opaque(nc); > > + FrameDescriptor desc; > > + > > + return (s->rx_ctl0 & RX_CTL0_RX_EN) && > > + (aw_h3_emac_get_rx_desc(s, &desc, 0) !=3D 0); > > +} > > + > > +static ssize_t aw_h3_emac_receive(NetClientState *nc, const uint8_t > *buf, > > + size_t size) > > +{ > > + AwH3EmacState *s =3D qemu_get_nic_opaque(nc); > > + FrameDescriptor desc; > > + size_t bytes_left =3D size; > > + size_t desc_bytes =3D 0; > > + size_t pad_fcs_size =3D 4; > > + size_t padding =3D 0; > > + > > + if (!(s->rx_ctl0 & RX_CTL0_RX_EN)) { > > + return -1; > > + } > > + > > + s->rx_desc_curr =3D aw_h3_emac_get_rx_desc(s, &desc, > AW_H3_EMAC_MIN_PKT_SZ); > > + if (!s->rx_desc_curr) { > > + s->int_sta |=3D INT_STA_RX_BUF_UA; > > + } > > + > > + /* Keep filling RX descriptors until the whole frame is written */ > > + while (s->rx_desc_curr && bytes_left > 0) { > > + desc.status &=3D ~DESC_STATUS_CTL; > > + desc.status &=3D ~RX_DESC_STATUS_FRM_LEN_MASK; > > + > > + if (bytes_left =3D=3D size) { > > + desc.status |=3D RX_DESC_STATUS_FIRST_DESC; > > + } > > + > > + if ((desc.status2 & DESC_STATUS2_BUF_SIZE_MASK) < > > + (bytes_left + pad_fcs_size)) { > > + desc_bytes =3D desc.status2 & DESC_STATUS2_BUF_SIZE_MASK; > > + desc.status |=3D desc_bytes << RX_DESC_STATUS_FRM_LEN_SHIF= T; > > + } else { > > + padding =3D pad_fcs_size; > > + if (bytes_left < AW_H3_EMAC_MIN_PKT_SZ) { > > + padding +=3D (AW_H3_EMAC_MIN_PKT_SZ - bytes_left); > > + } > > + > > + desc_bytes =3D (bytes_left); > > + desc.status |=3D RX_DESC_STATUS_LAST_DESC; > > + desc.status |=3D (bytes_left + padding) > > + << RX_DESC_STATUS_FRM_LEN_SHIFT; > > + } > > + > > + cpu_physical_memory_write(desc.addr, buf, desc_bytes); > > + aw_h3_emac_flush_desc(&desc, s->rx_desc_curr); > > + trace_aw_h3_emac_receive(s->rx_desc_curr, desc.addr, > desc_bytes); > > + > > + /* Check if frame needs to raise the receive interrupt */ > > + if (!(desc.status2 & RX_DESC_STATUS2_RX_INT_CTL)) { > > + s->int_sta |=3D INT_STA_RX; > > + } > > + > > + /* Increment variables */ > > + buf +=3D desc_bytes; > > + bytes_left -=3D desc_bytes; > > + > > + /* Move to the next descriptor */ > > + s->rx_desc_curr =3D aw_h3_emac_next_desc(&desc, 64); > > + if (!s->rx_desc_curr) { > > + /* Not enough buffer space available */ > > + s->int_sta |=3D INT_STA_RX_BUF_UA; > > + s->rx_desc_curr =3D s->rx_desc_head; > > + break; > > + } > > + } > > + > > + /* Report receive DMA is finished */ > > + s->rx_ctl1 &=3D ~RX_CTL1_RX_DMA_START; > > + aw_h3_emac_update_irq(s); > > + > > + return size; > > +} > > + > > +static void aw_h3_emac_transmit(AwH3EmacState *s) > > +{ > > + NetClientState *nc =3D qemu_get_queue(s->nic); > > + FrameDescriptor desc; > > + size_t bytes =3D 0; > > + size_t packet_bytes =3D 0; > > + size_t transmitted =3D 0; > > + static uint8_t packet_buf[2048]; > > + > > + s->tx_desc_curr =3D aw_h3_emac_get_tx_desc(s, &desc, 0); > > + > > + /* Read all transmit descriptors */ > > + while (s->tx_desc_curr !=3D 0) { > > + > > + /* Read from physical memory into packet buffer */ > > + bytes =3D desc.status2 & DESC_STATUS2_BUF_SIZE_MASK; > > + if (bytes + packet_bytes > sizeof(packet_buf)) { > > + desc.status |=3D TX_DESC_STATUS_LENGTH_ERR; > > + break; > > + } > > + cpu_physical_memory_read(desc.addr, packet_buf + packet_bytes, > bytes); > > + packet_bytes +=3D bytes; > > + desc.status &=3D ~DESC_STATUS_CTL; > > + aw_h3_emac_flush_desc(&desc, s->tx_desc_curr); > > + > > + /* After the last descriptor, send the packet */ > > + if (desc.status2 & TX_DESC_STATUS2_LAST_DESC) { > > + if (desc.status2 & TX_DESC_STATUS2_CHECKSUM_MASK) { > > + net_checksum_calculate(packet_buf, packet_bytes); > > + } > > + > > + qemu_send_packet(nc, packet_buf, packet_bytes); > > + trace_aw_h3_emac_transmit(s->tx_desc_curr, desc.addr, > bytes); > > + > > + packet_bytes =3D 0; > > + transmitted++; > > + } > > + s->tx_desc_curr =3D aw_h3_emac_next_desc(&desc, 0); > > + } > > + > > + /* Raise transmit completed interrupt */ > > + if (transmitted > 0) { > > + s->int_sta |=3D INT_STA_TX; > > + s->tx_ctl1 &=3D ~TX_CTL1_TX_DMA_START; > > + aw_h3_emac_update_irq(s); > > + } > > +} > > + > > +static void aw_h3_emac_reset(DeviceState *dev) > > +{ > > + AwH3EmacState *s =3D AW_H3_EMAC(dev); > > + NetClientState *nc =3D qemu_get_queue(s->nic); > > + > > + trace_aw_h3_emac_reset(); > > + > > + s->mii_cmd =3D 0; > > + s->mii_data =3D 0; > > + s->basic_ctl0 =3D 0; > > + s->basic_ctl1 =3D 0; > > + s->int_en =3D 0; > > + s->int_sta =3D 0; > > + s->frm_flt =3D 0; > > + s->rx_ctl0 =3D 0; > > + s->rx_ctl1 =3D RX_CTL1_RX_MD; > > + s->rx_desc_head =3D 0; > > + s->rx_desc_curr =3D 0; > > + s->tx_ctl0 =3D 0; > > + s->tx_ctl1 =3D 0; > > + s->tx_desc_head =3D 0; > > + s->tx_desc_curr =3D 0; > > + s->tx_flowctl =3D 0; > > + > > + aw_h3_emac_mii_reset(s, !nc->link_down); > > +} > > + > > +static uint64_t aw_h3_emac_read(void *opaque, hwaddr offset, unsigned > size) > > +{ > > + AwH3EmacState *s =3D opaque; > > I'd put AW_H3_EMAC(opaque) here. > > > + uint64_t value =3D 0; > > + FrameDescriptor desc; > > + > > + switch (offset) { > > + case REG_BASIC_CTL_0: /* Basic Control 0 */ > > + value =3D s->basic_ctl0; > > + break; > > + case REG_BASIC_CTL_1: /* Basic Control 1 */ > > + value =3D s->basic_ctl1; > > + break; > > + case REG_INT_STA: /* Interrupt Status */ > > + value =3D s->int_sta; > > + break; > > + case REG_INT_EN: /* Interupt Enable */ > > + value =3D s->int_en; > > + break; > > + case REG_TX_CTL_0: /* Transmit Control 0 */ > > + value =3D s->tx_ctl0; > > + break; > > + case REG_TX_CTL_1: /* Transmit Control 1 */ > > + value =3D s->tx_ctl1; > > + break; > > + case REG_TX_FLOW_CTL: /* Transmit Flow Control */ > > + value =3D s->tx_flowctl; > > + break; > > + case REG_TX_DMA_DESC_LIST: /* Transmit Descriptor List Address */ > > + value =3D s->tx_desc_head; > > + break; > > + case REG_RX_CTL_0: /* Receive Control 0 */ > > + value =3D s->rx_ctl0; > > + break; > > + case REG_RX_CTL_1: /* Receive Control 1 */ > > + value =3D s->rx_ctl1; > > + break; > > + case REG_RX_DMA_DESC_LIST: /* Receive Descriptor List Address */ > > + value =3D s->rx_desc_head; > > + break; > > + case REG_FRM_FLT: /* Receive Frame Filter */ > > + value =3D s->frm_flt; > > + break; > > + case REG_RX_HASH_0: /* Receive Hash Table 0 */ > > + case REG_RX_HASH_1: /* Receive Hash Table 1 */ > > + break; > > + case REG_MII_CMD: /* Management Interface Command */ > > + value =3D s->mii_cmd; > > + break; > > + case REG_MII_DATA: /* Management Interface Data */ > > + value =3D s->mii_data; > > + break; > > + case REG_ADDR_HIGH: /* MAC Address High */ > > + value =3D *(((uint32_t *) (s->conf.macaddr.a)) + 1); > > + break; > > + case REG_ADDR_LOW: /* MAC Address Low */ > > + value =3D *(uint32_t *) (s->conf.macaddr.a); > > + break; > > + case REG_TX_DMA_STA: /* Transmit DMA Status */ > > + break; > > + case REG_TX_CUR_DESC: /* Transmit Current Descriptor */ > > + value =3D s->tx_desc_curr; > > + break; > > + case REG_TX_CUR_BUF: /* Transmit Current Buffer */ > > + if (s->tx_desc_curr !=3D 0) { > > + cpu_physical_memory_read(s->tx_desc_curr, &desc, > sizeof(desc)); > > + value =3D desc.addr; > > + } else { > > + value =3D 0; > > + } > > + break; > > + case REG_RX_DMA_STA: /* Receive DMA Status */ > > + break; > > + case REG_RX_CUR_DESC: /* Receive Current Descriptor */ > > + value =3D s->rx_desc_curr; > > + break; > > + case REG_RX_CUR_BUF: /* Receive Current Buffer */ > > + if (s->rx_desc_curr !=3D 0) { > > + cpu_physical_memory_read(s->rx_desc_curr, &desc, > sizeof(desc)); > > + value =3D desc.addr; > > + } else { > > + value =3D 0; > > + } > > + break; > > + default: > > + qemu_log_mask(LOG_UNIMP, "allwinner-h3-emac: read access to > unknown " > > + "EMAC register 0x" TARGET_FMT_plx "\n= ", > > + offset); > > + } > > + > > + trace_aw_h3_emac_read(offset, value); > > + return value; > > +} > > + > > +static void aw_h3_emac_write(void *opaque, hwaddr offset, uint64_t > value, > > + unsigned size) > > +{ > > + AwH3EmacState *s =3D opaque; > > The same. > > > + NetClientState *nc =3D qemu_get_queue(s->nic); > > + > > + trace_aw_h3_emac_write(offset, value); > > + > > + switch (offset) { > > + case REG_BASIC_CTL_0: /* Basic Control 0 */ > > + s->basic_ctl0 =3D value; > > + break; > > + case REG_BASIC_CTL_1: /* Basic Control 1 */ > > + if (value & BASIC_CTL1_SOFTRST) { > > + aw_h3_emac_reset(DEVICE(s)); > > + value &=3D ~BASIC_CTL1_SOFTRST; > > + } > > + s->basic_ctl1 =3D value; > > + if (aw_h3_emac_can_receive(nc)) { > > + qemu_flush_queued_packets(nc); > > + } > > + break; > > + case REG_INT_STA: /* Interrupt Status */ > > + s->int_sta &=3D ~value; > > + aw_h3_emac_update_irq(s); > > + break; > > + case REG_INT_EN: /* Interrupt Enable */ > > + s->int_en =3D value; > > + aw_h3_emac_update_irq(s); > > + break; > > + case REG_TX_CTL_0: /* Transmit Control 0 */ > > + s->tx_ctl0 =3D value; > > + break; > > + case REG_TX_CTL_1: /* Transmit Control 1 */ > > + s->tx_ctl1 =3D value; > > + if (value & TX_CTL1_TX_DMA_EN) { > > + aw_h3_emac_transmit(s); > > + } > > + break; > > + case REG_TX_FLOW_CTL: /* Transmit Flow Control */ > > + s->tx_flowctl =3D value; > > + break; > > + case REG_TX_DMA_DESC_LIST: /* Transmit Descriptor List Address */ > > + s->tx_desc_head =3D value; > > + s->tx_desc_curr =3D value; > > + break; > > + case REG_RX_CTL_0: /* Receive Control 0 */ > > + s->rx_ctl0 =3D value; > > + break; > > + case REG_RX_CTL_1: /* Receive Control 1 */ > > + s->rx_ctl1 =3D value | RX_CTL1_RX_MD; > > + if ((value & RX_CTL1_RX_DMA_EN) && aw_h3_emac_can_receive(nc))= { > > + qemu_flush_queued_packets(nc); > > + } > > + break; > > + case REG_RX_DMA_DESC_LIST: /* Receive Descriptor List Address */ > > + s->rx_desc_head =3D value; > > + s->rx_desc_curr =3D value; > > + break; > > + case REG_FRM_FLT: /* Receive Frame Filter */ > > + s->frm_flt =3D value; > > + break; > > + case REG_RX_HASH_0: /* Receive Hash Table 0 */ > > + case REG_RX_HASH_1: /* Receive Hash Table 1 */ > > + break; > > + case REG_MII_CMD: /* Management Interface Command */ > > + s->mii_cmd =3D value & ~MII_CMD_PHY_BUSY; > > + aw_h3_emac_mii_cmd(s); > > + break; > > + case REG_MII_DATA: /* Management Interface Data */ > > + s->mii_data =3D value; > > + break; > > + case REG_ADDR_HIGH: /* MAC Address High */ > > + s->conf.macaddr.a[4] =3D (value & 0xff); > > + s->conf.macaddr.a[5] =3D (value & 0xff00) >> 8; > > + break; > > + case REG_ADDR_LOW: /* MAC Address Low */ > > + s->conf.macaddr.a[0] =3D (value & 0xff); > > + s->conf.macaddr.a[1] =3D (value & 0xff00) >> 8; > > + s->conf.macaddr.a[2] =3D (value & 0xff0000) >> 16; > > + s->conf.macaddr.a[3] =3D (value & 0xff000000) >> 24; > > + break; > > + case REG_TX_DMA_STA: /* Transmit DMA Status */ > > + case REG_TX_CUR_DESC: /* Transmit Current Descriptor */ > > + case REG_TX_CUR_BUF: /* Transmit Current Buffer */ > > + case REG_RX_DMA_STA: /* Receive DMA Status */ > > + case REG_RX_CUR_DESC: /* Receive Current Descriptor */ > > + case REG_RX_CUR_BUF: /* Receive Current Buffer */ > > + case REG_RGMII_STA: /* RGMII Status */ > > + break; > > + default: > > + qemu_log_mask(LOG_UNIMP, "allwinner-h3-emac: write access to > unknown " > > + "EMAC register 0x" TARGET_FMT_plx "\n= ", > > + offset); > > + } > > +} > > + > > +static void aw_h3_emac_set_link(NetClientState *nc) > > +{ > > + AwH3EmacState *s =3D qemu_get_nic_opaque(nc); > > + > > + trace_aw_h3_emac_set_link(!nc->link_down); > > + aw_h3_emac_mii_set_link(s, !nc->link_down); > > +} > > + > > +static const MemoryRegionOps aw_h3_emac_mem_ops =3D { > > + .read =3D aw_h3_emac_read, > > + .write =3D aw_h3_emac_write, > > + .endianness =3D DEVICE_NATIVE_ENDIAN, > > + .valid =3D { > > + .min_access_size =3D 4, > > + .max_access_size =3D 4, > > + }, > > +}; > > + > > +static NetClientInfo net_aw_h3_emac_info =3D { > > + .type =3D NET_CLIENT_DRIVER_NIC, > > + .size =3D sizeof(NICState), > > + .can_receive =3D aw_h3_emac_can_receive, > > + .receive =3D aw_h3_emac_receive, > > + .link_status_changed =3D aw_h3_emac_set_link, > > +}; > > + > > +static void aw_h3_emac_init(Object *obj) > > +{ > > + SysBusDevice *sbd =3D SYS_BUS_DEVICE(obj); > > + AwH3EmacState *s =3D AW_H3_EMAC(obj); > > + > > + memory_region_init_io(&s->iomem, OBJECT(s), &aw_h3_emac_mem_ops, s= , > > + TYPE_AW_H3_EMAC, AW_H3_EMAC_REGS_MEM_SIZE); > > + sysbus_init_mmio(sbd, &s->iomem); > > + sysbus_init_irq(sbd, &s->irq); > > +} > > + > > +static void aw_h3_emac_realize(DeviceState *dev, Error **errp) > > +{ > > + AwH3EmacState *s =3D AW_H3_EMAC(dev); > > + > > + qemu_macaddr_default_if_unset(&s->conf.macaddr); > > + s->nic =3D qemu_new_nic(&net_aw_h3_emac_info, &s->conf, > > + object_get_typename(OBJECT(dev)), dev->id, s= ); > > + qemu_format_nic_info_str(qemu_get_queue(s->nic), s->conf.macaddr.a= ); > > +} > > + > > +static Property aw_h3_emac_properties[] =3D { > > + DEFINE_NIC_PROPERTIES(AwH3EmacState, conf), > > + DEFINE_PROP_UINT8("phy-addr", AwH3EmacState, mii_phy_addr, 0), > > + DEFINE_PROP_END_OF_LIST(), > > +}; > > + > > +static int aw_h3_emac_post_load(void *opaque, int version_id) > > +{ > > + AwH3EmacState *s =3D opaque; > > + > > + aw_h3_emac_set_link(qemu_get_queue(s->nic)); > > + > > + return 0; > > +} > > + > > +static const VMStateDescription vmstate_aw_emac =3D { > > + .name =3D TYPE_AW_H3_EMAC, > > + .version_id =3D 1, > > + .minimum_version_id =3D 1, > > + .post_load =3D aw_h3_emac_post_load, > > + .fields =3D (VMStateField[]) { > > + VMSTATE_UINT8(mii_phy_addr, AwH3EmacState), > > + VMSTATE_UINT32(mii_cmd, AwH3EmacState), > > + VMSTATE_UINT32(mii_data, AwH3EmacState), > > + VMSTATE_UINT32(basic_ctl0, AwH3EmacState), > > + VMSTATE_UINT32(basic_ctl1, AwH3EmacState), > > + VMSTATE_UINT32(int_en, AwH3EmacState), > > + VMSTATE_UINT32(int_sta, AwH3EmacState), > > + VMSTATE_UINT32(frm_flt, AwH3EmacState), > > + VMSTATE_UINT32(rx_ctl0, AwH3EmacState), > > + VMSTATE_UINT32(rx_ctl1, AwH3EmacState), > > + VMSTATE_UINT32(rx_desc_head, AwH3EmacState), > > + VMSTATE_UINT32(rx_desc_curr, AwH3EmacState), > > + VMSTATE_UINT32(tx_ctl0, AwH3EmacState), > > + VMSTATE_UINT32(tx_ctl1, AwH3EmacState), > > + VMSTATE_UINT32(tx_desc_head, AwH3EmacState), > > + VMSTATE_UINT32(tx_desc_curr, AwH3EmacState), > > + VMSTATE_UINT32(tx_flowctl, AwH3EmacState), > > + VMSTATE_END_OF_LIST() > > + } > > +}; > > + > > +static void aw_h3_emac_class_init(ObjectClass *klass, void *data) > > +{ > > + DeviceClass *dc =3D DEVICE_CLASS(klass); > > + > > + dc->realize =3D aw_h3_emac_realize; > > + dc->props =3D aw_h3_emac_properties; > > + dc->reset =3D aw_h3_emac_reset; > > + dc->vmsd =3D &vmstate_aw_emac; > > +} > > + > > +static const TypeInfo aw_h3_emac_info =3D { > > + .name =3D TYPE_AW_H3_EMAC, > > + .parent =3D TYPE_SYS_BUS_DEVICE, > > + .instance_size =3D sizeof(AwH3EmacState), > > + .instance_init =3D aw_h3_emac_init, > > + .class_init =3D aw_h3_emac_class_init, > > +}; > > + > > +static void aw_h3_emac_register_types(void) > > +{ > > + type_register_static(&aw_h3_emac_info); > > +} > > + > > +type_init(aw_h3_emac_register_types) > > diff --git a/hw/net/trace-events b/hw/net/trace-events > > index e70f12bee1..e9e2f26f68 100644 > > --- a/hw/net/trace-events > > +++ b/hw/net/trace-events > > @@ -1,5 +1,15 @@ > > # See docs/devel/tracing.txt for syntax documentation. > > > > +# allwinner-h3-emac.c > > +aw_h3_emac_mii_write_reg(uint32_t reg, uint32_t value) "MII write: > reg=3D0x%x value=3D0x%x" > > +aw_h3_emac_mii_read_reg(uint32_t reg, uint32_t value) "MII read: > reg=3D0x%x value=3D0x%x" > > +aw_h3_emac_receive(uint32_t desc, uint32_t paddr, uint32_t bytes) "RX > packet: desc=3D0x%08x paddr=3D0x%08x bytes=3D%u" > > +aw_h3_emac_transmit(uint32_t desc, uint32_t paddr, uint32_t bytes) "TX > packet: desc=3D0x%08x paddr=3D0x%08x bytes=3D%u" > > +aw_h3_emac_reset(void) "HW reset" > > +aw_h3_emac_set_link(bool active) "Set link: active=3D%u" > > +aw_h3_emac_read(uint64_t offset, uint64_t val) "MMIO read: offset=3D0x= %" > PRIx64 " value=3D0x%" PRIx64 > > +aw_h3_emac_write(uint64_t offset, uint64_t val) "MMIO write: > offset=3D0x%" PRIx64 " value=3D0x%" PRIx64 > > + > > # etraxfs_eth.c > > mdio_phy_read(int regnum, uint16_t value) "read phy_reg:%d > value:0x%04x" > > mdio_phy_write(int regnum, uint16_t value) "write phy_reg:%d > value:0x%04x" > > diff --git a/include/hw/arm/allwinner-h3.h > b/include/hw/arm/allwinner-h3.h > > index 7aff4ebbd2..b964a60f41 100644 > > --- a/include/hw/arm/allwinner-h3.h > > +++ b/include/hw/arm/allwinner-h3.h > > @@ -31,6 +31,7 @@ > > #include "hw/misc/allwinner-h3-syscon.h" > > #include "hw/misc/allwinner-h3-sid.h" > > #include "hw/sd/allwinner-h3-sdhost.h" > > +#include "hw/net/allwinner-h3-emac.h" > > #include "target/arm/cpu.h" > > > > #define AW_H3_SRAM_A1_BASE (0x00000000) > > @@ -119,6 +120,7 @@ typedef struct AwH3State { > > AwH3SysconState syscon; > > AwH3SidState sid; > > AwH3SDHostState mmc0; > > + AwH3EmacState emac; > > GICState gic; > > MemoryRegion sram_a1; > > MemoryRegion sram_a2; > > diff --git a/include/hw/net/allwinner-h3-emac.h > b/include/hw/net/allwinner-h3-emac.h > > new file mode 100644 > > index 0000000000..a007d54472 > > --- /dev/null > > +++ b/include/hw/net/allwinner-h3-emac.h > > @@ -0,0 +1,69 @@ > > +/* > > + * Allwinner H3 EMAC emulation > > + * > > + * Copyright (C) 2019 Niek Linnenbank > > + * > > + * This program is free software: you can redistribute it and/or modif= y > > + * it under the terms of the GNU General Public License as published b= y > > + * the Free Software Foundation, either version 2 of the License, or > > + * (at your option) any later version. > > + * > > + * This program is distributed in the hope that it will be useful, > > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > > + * GNU General Public License for more details. > > + * > > + * You should have received a copy of the GNU General Public License > > + * along with this program. If not, see >. > > + */ > > + > > +#ifndef ALLWINNER_H3_EMAC_H > > +#define ALLWINNER_H3_EMAC_H > > + > > +#include "qemu/units.h" > > +#include "net/net.h" > > +#include "qemu/fifo8.h" > > +#include "hw/net/mii.h" > > +#include "hw/sysbus.h" > > + > > +#define AW_H3_EMAC_REGS_MEM_SIZE (1024) > > + > > +#define TYPE_AW_H3_EMAC "allwinner-h3-emac" > > +#define AW_H3_EMAC(obj) OBJECT_CHECK(AwH3EmacState, (obj), > TYPE_AW_H3_EMAC) > > + > > +typedef struct AwH3EmacState { > > + /*< private >*/ > > + SysBusDevice parent_obj; > > + /*< public >*/ > > + > > + MemoryRegion iomem; > > + qemu_irq irq; > > + NICState *nic; > > + NICConf conf; > > + > > + uint8_t mii_phy_addr; > > + uint32_t mii_cmd; > > + uint32_t mii_data; > > + uint32_t mii_cr; > > + uint32_t mii_st; > > + > > + uint32_t basic_ctl0; > > + uint32_t basic_ctl1; > > + uint32_t int_en; > > + uint32_t int_sta; > > + uint32_t frm_flt; > > + > > + uint32_t rx_ctl0; > > + uint32_t rx_ctl1; > > + uint32_t rx_desc_head; > > + uint32_t rx_desc_curr; > > + > > + uint32_t tx_ctl0; > > + uint32_t tx_ctl1; > > + uint32_t tx_desc_head; > > + uint32_t tx_desc_curr; > > + uint32_t tx_flowctl; > > + > > +} AwH3EmacState; > > + > > +#endif > > > > The rest seems ok to me. Thanks for the contribution :)! > Thanks! :-) Regards, Niek > Cheers, > Fred > > --=20 Niek Linnenbank WWW: http://www.nieklinnenbank.nl/ BLOG: http://nieklinnenbank.wordpress.com/ FUN: http://www.FreeNOS.org/ --000000000000354d600598d1e4fc Content-Type: text/html; charset="UTF-8" Content-Transfer-Encoding: quoted-printable
Hello Frederic,

=
Thank you for your quick review comments!
I'll start wor= king on v2 of the patches and include the changes you suggested.
<= /div>
O= n Tue, Dec 3, 2019 at 10:33 AM KONRAD Frederic <frederic.konrad@adacore.com> wrote:
=


Le 12/2/19 =C3=A0 10:09 PM, Niek Linnenbank a =C3=A9crit=C2=A0:
> The Allwinner H3 System on Chip includes an Ethernet MAC (EMAC)
> which provides 10M/100M/1000M Ethernet connectivity. This commit
> adds support for the Allwinner H3 EMAC, including emulation for
> the following functionality:
>
>=C2=A0 =C2=A0* DMA transfers
>=C2=A0 =C2=A0* MII interface
>=C2=A0 =C2=A0* Transmit CRC calculation
>
> Signed-off-by: Niek Linnenbank <nieklinnenbank@gmail.com>
> ---
>=C2=A0 =C2=A0hw/arm/Kconfig=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0|=C2=A0 =C2=A01 +
>=C2=A0 =C2=A0hw/arm/allwinner-h3.c=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 |=C2=A0 17 +
>=C2=A0 =C2=A0hw/arm/orangepi.c=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0 =C2=A0 |=C2=A0 =C2=A07 +
>=C2=A0 =C2=A0hw/net/Kconfig=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0|=C2=A0 =C2=A03 +
>=C2=A0 =C2=A0hw/net/Makefile.objs=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0|=C2=A0 =C2=A01 +
>=C2=A0 =C2=A0hw/net/allwinner-h3-emac.c=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0| 786 +++++++++++++++++++++++++++++
>=C2=A0 =C2=A0hw/net/trace-events=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 |=C2=A0 10 +
>=C2=A0 =C2=A0include/hw/arm/allwinner-h3.h=C2=A0 =C2=A0 =C2=A0 |=C2=A0 = =C2=A02 +
>=C2=A0 =C2=A0include/hw/net/allwinner-h3-emac.h |=C2=A0 69 +++
>=C2=A0 =C2=A09 files changed, 896 insertions(+)
>=C2=A0 =C2=A0create mode 100644 hw/net/allwinner-h3-emac.c
>=C2=A0 =C2=A0create mode 100644 include/hw/net/allwinner-h3-emac.h
>
> diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig
> index ebf8d2325f..551cff3442 100644
> --- a/hw/arm/Kconfig
> +++ b/hw/arm/Kconfig
> @@ -294,6 +294,7 @@ config ALLWINNER_A10
>=C2=A0 =C2=A0config ALLWINNER_H3
>=C2=A0 =C2=A0 =C2=A0 =C2=A0bool
>=C2=A0 =C2=A0 =C2=A0 =C2=A0select ALLWINNER_A10_PIT
> +=C2=A0 =C2=A0 select ALLWINNER_H3_EMAC
>=C2=A0 =C2=A0 =C2=A0 =C2=A0select SERIAL
>=C2=A0 =C2=A0 =C2=A0 =C2=A0select ARM_TIMER
>=C2=A0 =C2=A0 =C2=A0 =C2=A0select ARM_GIC
> diff --git a/hw/arm/allwinner-h3.c b/hw/arm/allwinner-h3.c
> index c2972caf88..274b8548c0 100644
> --- a/hw/arm/allwinner-h3.c
> +++ b/hw/arm/allwinner-h3.c
> @@ -53,6 +53,9 @@ static void aw_h3_init(Object *obj)
>=C2=A0 =C2=A0
>=C2=A0 =C2=A0 =C2=A0 =C2=A0sysbus_init_child_obj(obj, "mmc0",= &s->mmc0, sizeof(s->mmc0),
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0TYPE_AW_H3_SDHOST);
> +
> +=C2=A0 =C2=A0 sysbus_init_child_obj(obj, "emac", &s->= ;emac, sizeof(s->emac),
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0 =C2=A0 TYPE_AW_H3_EMAC);
>=C2=A0 =C2=A0}
>=C2=A0 =C2=A0
>=C2=A0 =C2=A0static void aw_h3_realize(DeviceState *dev, Error **errp)<= br> > @@ -237,6 +240,20 @@ static void aw_h3_realize(DeviceState *dev, Error= **errp)
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0return;
>=C2=A0 =C2=A0 =C2=A0 =C2=A0}
>=C2=A0 =C2=A0
> +=C2=A0 =C2=A0 /* EMAC */
> +=C2=A0 =C2=A0 if (nd_table[0].used) {
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 qemu_check_nic_model(&nd_table[0], TY= PE_AW_H3_EMAC);
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 qdev_set_nic_properties(DEVICE(&s->= ;emac), &nd_table[0]);
> +=C2=A0 =C2=A0 }
> +=C2=A0 =C2=A0 object_property_set_bool(OBJECT(&s->emac), true,= "realized", &err);
> +=C2=A0 =C2=A0 if (err !=3D NULL) {
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 error_propagate(errp, err);
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 return;
> +=C2=A0 =C2=A0 }
> +=C2=A0 =C2=A0 sysbusdev =3D SYS_BUS_DEVICE(&s->emac);
> +=C2=A0 =C2=A0 sysbus_mmio_map(sysbusdev, 0, AW_H3_EMAC_BASE);
> +=C2=A0 =C2=A0 sysbus_connect_irq(sysbusdev, 0, s->irq[AW_H3_GIC_SP= I_EMAC]);
> +
>=C2=A0 =C2=A0 =C2=A0 =C2=A0/* Universal Serial Bus */
>=C2=A0 =C2=A0 =C2=A0 =C2=A0sysbus_create_simple(TYPE_AW_H3_EHCI, AW_H3_= EHCI0_BASE,
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 s->irq[AW_H3_GIC_SPI_EHCI0]);
> diff --git a/hw/arm/orangepi.c b/hw/arm/orangepi.c
> index dee3efaf08..8a61eb0e69 100644
> --- a/hw/arm/orangepi.c
> +++ b/hw/arm/orangepi.c
> @@ -61,6 +61,13 @@ static void orangepi_init(MachineState *machine) >=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0exit(1);
>=C2=A0 =C2=A0 =C2=A0 =C2=A0}
>=C2=A0 =C2=A0
> +=C2=A0 =C2=A0 /* Setup EMAC properties */
> +=C2=A0 =C2=A0 object_property_set_int(OBJECT(&s->h3->emac),= 1, "phy-addr", &err);
> +=C2=A0 =C2=A0 if (err !=3D NULL) {
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 error_reportf_err(err, "Couldn't= set phy address: ");
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 exit(1);
> +=C2=A0 =C2=A0 }
> +
>=C2=A0 =C2=A0 =C2=A0 =C2=A0/* Mark H3 object realized */
>=C2=A0 =C2=A0 =C2=A0 =C2=A0object_property_set_bool(OBJECT(s->h3), t= rue, "realized", &err);
>=C2=A0 =C2=A0 =C2=A0 =C2=A0if (err !=3D NULL) {
> diff --git a/hw/net/Kconfig b/hw/net/Kconfig
> index 3856417d42..36d3923992 100644
> --- a/hw/net/Kconfig
> +++ b/hw/net/Kconfig
> @@ -74,6 +74,9 @@ config MIPSNET
>=C2=A0 =C2=A0config ALLWINNER_EMAC
>=C2=A0 =C2=A0 =C2=A0 =C2=A0bool
>=C2=A0 =C2=A0
> +config ALLWINNER_H3_EMAC
> +=C2=A0 =C2=A0 bool
> +
>=C2=A0 =C2=A0config IMX_FEC
>=C2=A0 =C2=A0 =C2=A0 =C2=A0bool
>=C2=A0 =C2=A0
> diff --git a/hw/net/Makefile.objs b/hw/net/Makefile.objs
> index 7907d2c199..5548deb07a 100644
> --- a/hw/net/Makefile.objs
> +++ b/hw/net/Makefile.objs
> @@ -23,6 +23,7 @@ common-obj-$(CONFIG_XGMAC) +=3D xgmac.o
>=C2=A0 =C2=A0common-obj-$(CONFIG_MIPSNET) +=3D mipsnet.o
>=C2=A0 =C2=A0common-obj-$(CONFIG_XILINX_AXI) +=3D xilinx_axienet.o
>=C2=A0 =C2=A0common-obj-$(CONFIG_ALLWINNER_EMAC) +=3D allwinner_emac.o<= br> > +common-obj-$(CONFIG_ALLWINNER_H3_EMAC) +=3D allwinner-h3-emac.o
>=C2=A0 =C2=A0common-obj-$(CONFIG_IMX_FEC) +=3D imx_fec.o
>=C2=A0 =C2=A0
>=C2=A0 =C2=A0common-obj-$(CONFIG_CADENCE) +=3D cadence_gem.o
> diff --git a/hw/net/allwinner-h3-emac.c b/hw/net/allwinner-h3-emac.c > new file mode 100644
> index 0000000000..37f6f44406
> --- /dev/null
> +++ b/hw/net/allwinner-h3-emac.c
> @@ -0,0 +1,786 @@
> +/*
> + * Allwinner H3 EMAC emulation
> + *
> + * Copyright (C) 2019 Niek Linnenbank <nieklinnenbank@gmail.com>
> + *
> + * This program is free software: you can redistribute it and/or modi= fy
> + * it under the terms of the GNU General Public License as published = by
> + * the Free Software Foundation, either version 2 of the License, or<= br> > + * (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful, > + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.=C2=A0 See the=
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License<= br> > + * along with this program.=C2=A0 If not, see <http://www.gnu.o= rg/licenses/>.
> + */
> +
> +#include "qemu/osdep.h"
> +#include "hw/sysbus.h"
> +#include "migration/vmstate.h"
> +#include "net/net.h"
> +#include "hw/irq.h"
> +#include "hw/qdev-properties.h"
> +#include "qemu/log.h"
> +#include "trace.h"
> +#include "net/checksum.h"
> +#include "qemu/module.h"
> +#include "exec/cpu-common.h"
> +#include "hw/net/allwinner-h3-emac.h"
> +
> +/* EMAC register offsets */
> +#define REG_BASIC_CTL_0=C2=A0 =C2=A0 =C2=A0 =C2=A0 (0x0000) /* Basic = Control 0 */
> +#define REG_BASIC_CTL_1=C2=A0 =C2=A0 =C2=A0 =C2=A0 (0x0004) /* Basic = Control 1 */
> +#define REG_INT_STA=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 (0x0008)= /* Interrupt Status */
> +#define REG_INT_EN=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0(0x= 000C) /* Interrupt Enable */
> +#define REG_TX_CTL_0=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0(0x0010)= /* Transmit Control 0 */
> +#define REG_TX_CTL_1=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0(0x0014)= /* Transmit Control 1 */
> +#define REG_TX_FLOW_CTL=C2=A0 =C2=A0 =C2=A0 =C2=A0 (0x001C) /* Transm= it Flow Control */
> +#define REG_TX_DMA_DESC_LIST=C2=A0 =C2=A0(0x0020) /* Transmit Descrip= tor List Address */
> +#define REG_RX_CTL_0=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0(0x0024)= /* Receive Control 0 */
> +#define REG_RX_CTL_1=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0(0x0028)= /* Receive Control 1 */
> +#define REG_RX_DMA_DESC_LIST=C2=A0 =C2=A0(0x0034) /* Receive Descript= or List Address */
> +#define REG_FRM_FLT=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 (0x0038)= /* Receive Frame Filter */
> +#define REG_RX_HASH_0=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 (0x0040) /* R= eceive Hash Table 0 */
> +#define REG_RX_HASH_1=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 (0x0044) /* R= eceive Hash Table 1 */
> +#define REG_MII_CMD=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 (0x0048)= /* Management Interface Command */
> +#define REG_MII_DATA=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0(0x004C)= /* Management Interface Data */
> +#define REG_ADDR_HIGH=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 (0x0050) /* M= AC Address High */
> +#define REG_ADDR_LOW=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0(0x0054)= /* MAC Address Low */
> +#define REG_TX_DMA_STA=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0(0x00B0) /* T= ransmit DMA Status */
> +#define REG_TX_CUR_DESC=C2=A0 =C2=A0 =C2=A0 =C2=A0 (0x00B4) /* Transm= it Current Descriptor */
> +#define REG_TX_CUR_BUF=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0(0x00B8) /* T= ransmit Current Buffer */
> +#define REG_RX_DMA_STA=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0(0x00C0) /* R= eceive DMA Status */
> +#define REG_RX_CUR_DESC=C2=A0 =C2=A0 =C2=A0 =C2=A0 (0x00C4) /* Receiv= e Current Descriptor */
> +#define REG_RX_CUR_BUF=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0(0x00C8) /* R= eceive Current Buffer */
> +#define REG_RGMII_STA=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 (0x00D0) /* R= GMII Status */
> +
> +/* EMAC register flags */
> +#define BASIC_CTL0_100Mbps=C2=A0 =C2=A0 =C2=A0(0b11 << 2)
> +#define BASIC_CTL0_FD=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 (1 << 0= )
> +#define BASIC_CTL1_SOFTRST=C2=A0 =C2=A0 =C2=A0(1 << 0)
> +
> +#define INT_STA_RGMII_LINK=C2=A0 =C2=A0 =C2=A0(1 << 16)
> +#define INT_STA_RX_EARLY=C2=A0 =C2=A0 =C2=A0 =C2=A0(1 << 13) > +#define INT_STA_RX_OVERFLOW=C2=A0 =C2=A0 (1 << 12)
> +#define INT_STA_RX_TIMEOUT=C2=A0 =C2=A0 =C2=A0(1 << 11)
> +#define INT_STA_RX_DMA_STOP=C2=A0 =C2=A0 (1 << 10)
> +#define INT_STA_RX_BUF_UA=C2=A0 =C2=A0 =C2=A0 (1 << 9)
> +#define INT_STA_RX=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0(1 = << 8)
> +#define INT_STA_TX_EARLY=C2=A0 =C2=A0 =C2=A0 =C2=A0(1 << 5)
> +#define INT_STA_TX_UNDERFLOW=C2=A0 =C2=A0(1 << 4)
> +#define INT_STA_TX_TIMEOUT=C2=A0 =C2=A0 =C2=A0(1 << 3)
> +#define INT_STA_TX_BUF_UA=C2=A0 =C2=A0 =C2=A0 (1 << 2)
> +#define INT_STA_TX_DMA_STOP=C2=A0 =C2=A0 (1 << 1)
> +#define INT_STA_TX=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0(1 = << 0)
> +
> +#define INT_EN_RX_EARLY=C2=A0 =C2=A0 =C2=A0 =C2=A0 (1 << 13) > +#define INT_EN_RX_OVERFLOW=C2=A0 =C2=A0 =C2=A0(1 << 12)
> +#define INT_EN_RX_TIMEOUT=C2=A0 =C2=A0 =C2=A0 (1 << 11)
> +#define INT_EN_RX_DMA_STOP=C2=A0 =C2=A0 =C2=A0(1 << 10)
> +#define INT_EN_RX_BUF_UA=C2=A0 =C2=A0 =C2=A0 =C2=A0(1 << 9)
> +#define INT_EN_RX=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 (1 = << 8)
> +#define INT_EN_TX_EARLY=C2=A0 =C2=A0 =C2=A0 =C2=A0 (1 << 5)
> +#define INT_EN_TX_UNDERFLOW=C2=A0 =C2=A0 (1 << 4)
> +#define INT_EN_TX_TIMEOUT=C2=A0 =C2=A0 =C2=A0 (1 << 3)
> +#define INT_EN_TX_BUF_UA=C2=A0 =C2=A0 =C2=A0 =C2=A0(1 << 2)
> +#define INT_EN_TX_DMA_STOP=C2=A0 =C2=A0 =C2=A0(1 << 1)
> +#define INT_EN_TX=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 (1 = << 0)
> +
> +#define TX_CTL0_TX_EN=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 (1 << 3= 1)
> +#define TX_CTL1_TX_DMA_START=C2=A0 =C2=A0(1 << 31)
> +#define TX_CTL1_TX_DMA_EN=C2=A0 =C2=A0 =C2=A0 (1 << 30)
> +#define TX_CTL1_TX_FLUSH=C2=A0 =C2=A0 =C2=A0 =C2=A0(1 << 0)
> +
> +#define RX_CTL0_RX_EN=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 (1 << 3= 1)
> +#define RX_CTL0_STRIP_FCS=C2=A0 =C2=A0 =C2=A0 (1 << 28)
> +#define RX_CTL0_CRC_IPV4=C2=A0 =C2=A0 =C2=A0 =C2=A0(1 << 27) > +
> +#define RX_CTL1_RX_DMA_START=C2=A0 =C2=A0(1 << 31)
> +#define RX_CTL1_RX_DMA_EN=C2=A0 =C2=A0 =C2=A0 (1 << 30)
> +#define RX_CTL1_RX_MD=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 (1 << 1= )
> +
> +#define RX_FRM_FLT_DIS_ADDR=C2=A0 =C2=A0 (1 << 31)
> +
> +#define MII_CMD_PHY_ADDR_SHIFT (12)
> +#define MII_CMD_PHY_ADDR_MASK=C2=A0 (0xf000)
> +#define MII_CMD_PHY_REG_SHIFT=C2=A0 (4)
> +#define MII_CMD_PHY_REG_MASK=C2=A0 =C2=A0(0xf0)
> +#define MII_CMD_PHY_RW=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0(1 << 1= )
> +#define MII_CMD_PHY_BUSY=C2=A0 =C2=A0 =C2=A0 =C2=A0(1 << 0)
> +
> +#define TX_DMA_STA_STOP=C2=A0 =C2=A0 =C2=A0 =C2=A0 (0b000)
> +#define TX_DMA_STA_RUN_FETCH=C2=A0 =C2=A0(0b001)
> +#define TX_DMA_STA_WAIT_STA=C2=A0 =C2=A0 (0b010)
> +
> +#define RX_DMA_STA_STOP=C2=A0 =C2=A0 =C2=A0 =C2=A0 (0b000)
> +#define RX_DMA_STA_RUN_FETCH=C2=A0 =C2=A0(0b001)
> +#define RX_DMA_STA_WAIT_FRM=C2=A0 =C2=A0 (0b011)
> +
> +#define RGMII_LINK_UP=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 (1 << 3= )
> +#define RGMII_FD=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0(1 << 0)
> +
> +/* EMAC register reset values */
> +#define REG_BASIC_CTL_1_RST=C2=A0 =C2=A0 (0x08000000)
> +
> +/* EMAC constants */
> +#define AW_H3_EMAC_MIN_PKT_SZ=C2=A0 (64)
> +
> +/* Transmit/receive frame descriptor */
> +typedef struct FrameDescriptor {
> +=C2=A0 =C2=A0 uint32_t status;
> +=C2=A0 =C2=A0 uint32_t status2;
> +=C2=A0 =C2=A0 uint32_t addr;
> +=C2=A0 =C2=A0 uint32_t next;
> +} FrameDescriptor;
> +
> +/* Frame descriptor flags */
> +#define DESC_STATUS_CTL=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0(1 << 31)
> +#define DESC_STATUS2_BUF_SIZE_MASK=C2=A0 =C2=A0 =C2=A0 (0x7ff)
> +
> +/* Transmit frame descriptor flags */
> +#define TX_DESC_STATUS_LENGTH_ERR=C2=A0 =C2=A0 =C2=A0 =C2=A0(1 <&l= t; 14)
> +#define TX_DESC_STATUS2_FIRST_DESC=C2=A0 =C2=A0 =C2=A0 (1 << 29= )
> +#define TX_DESC_STATUS2_LAST_DESC=C2=A0 =C2=A0 =C2=A0 =C2=A0(1 <&l= t; 30)
> +#define TX_DESC_STATUS2_CHECKSUM_MASK=C2=A0 =C2=A0(0x3 << 27) > +
> +/* Receive frame descriptor flags */
> +#define RX_DESC_STATUS_FIRST_DESC=C2=A0 =C2=A0 =C2=A0 =C2=A0(1 <&l= t; 9)
> +#define RX_DESC_STATUS_LAST_DESC=C2=A0 =C2=A0 =C2=A0 =C2=A0 (1 <&l= t; 8)
> +#define RX_DESC_STATUS_FRM_LEN_MASK=C2=A0 =C2=A0 =C2=A0(0x3fff0000) > +#define RX_DESC_STATUS_FRM_LEN_SHIFT=C2=A0 =C2=A0 (16)
> +#define RX_DESC_STATUS_NO_BUF=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0(1 << 14)
> +#define RX_DESC_STATUS_HEADER_ERR=C2=A0 =C2=A0 =C2=A0 =C2=A0(1 <&l= t; 7)
> +#define RX_DESC_STATUS_LENGTH_ERR=C2=A0 =C2=A0 =C2=A0 =C2=A0(1 <&l= t; 4)
> +#define RX_DESC_STATUS_CRC_ERR=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 (1 &= lt;< 1)
> +#define RX_DESC_STATUS_PAYLOAD_ERR=C2=A0 =C2=A0 =C2=A0 (1 << 0)=
> +#define RX_DESC_STATUS2_RX_INT_CTL=C2=A0 =C2=A0 =C2=A0 (1 << 31= )
> +
> +/* MII register offsets */
> +#define MII_REG_CR=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 (0x0)
> +#define MII_REG_ST=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 (0x1)
> +#define MII_REG_ID_HIGH=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0(0x2)
> +#define MII_REG_ID_LOW=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 (0x3)
> +
> +/* MII register flags */
> +#define MII_REG_CR_RESET=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 (1 << 15)
> +#define MII_REG_CR_POWERDOWN=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= (1 << 11)
> +#define MII_REG_CR_10Mbit=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0(0)
> +#define MII_REG_CR_100Mbit=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 (1 << 13)
> +#define MII_REG_CR_1000Mbit=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0(1 << 6)
> +#define MII_REG_CR_AUTO_NEG=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0(1 << 12)
> +#define MII_REG_CR_AUTO_NEG_RESTART=C2=A0 =C2=A0 =C2=A0(1 << 9)=
> +#define MII_REG_CR_FULLDUPLEX=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0(1 << 8)
> +
> +#define MII_REG_ST_100BASE_T4=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0(1 << 15)
> +#define MII_REG_ST_100BASE_X_FD=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0(1 &= lt;< 14)
> +#define MII_REG_ST_100BASE_X_HD=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0(1 &= lt;< 13)
> +#define MII_REG_ST_10_FD=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 (1 << 12)
> +#define MII_REG_ST_10_HD=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 (1 << 11)
> +#define MII_REG_ST_100BASE_T2_FD=C2=A0 =C2=A0 =C2=A0 =C2=A0 (1 <&l= t; 10)
> +#define MII_REG_ST_100BASE_T2_HD=C2=A0 =C2=A0 =C2=A0 =C2=A0 (1 <&l= t; 9)
> +#define MII_REG_ST_AUTONEG_COMPLETE=C2=A0 =C2=A0 =C2=A0(1 << 5)=
> +#define MII_REG_ST_AUTONEG_AVAIL=C2=A0 =C2=A0 =C2=A0 =C2=A0 (1 <&l= t; 3)
> +#define MII_REG_ST_LINK_UP=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 (1 << 2)
> +
> +/* MII constants */
> +#define MII_PHY_ID_HIGH=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0(0x0044)
> +#define MII_PHY_ID_LOW=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 (0x1400)

I wonder if we can't share all those mii stuff accross the network adap= ters
instead of redoing the work everytime. I've some patches about it I may= post
them sometimes.


Indeed, that would be a nice improveme= nt. In fact, I was looking for somekind of
MII library inside QEM= U and could not find it. Then I saw that the other emulated ethernet cards<= /div>
all have that code inside each file, so that is why I did the sam= e here.
=C2=A0
> +
> +static void aw_h3_emac_mii_set_link(AwH3EmacState *s, bool link_activ= e)
> +{
> +=C2=A0 =C2=A0 if (link_active) {
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 s->mii_st |=3D MII_REG_ST_LINK_UP;
> +=C2=A0 =C2=A0 } else {
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 s->mii_st &=3D ~MII_REG_ST_LINK_UP= ;
> +=C2=A0 =C2=A0 }
> +}
> +
> +static void aw_h3_emac_mii_reset(AwH3EmacState *s, bool link_active)<= br> > +{
> +=C2=A0 =C2=A0 s->mii_cr =3D MII_REG_CR_100Mbit | MII_REG_CR_AUTO_N= EG |
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 MII_REG_CR_FU= LLDUPLEX;
> +=C2=A0 =C2=A0 s->mii_st =3D MII_REG_ST_100BASE_T4 | MII_REG_ST_100= BASE_X_FD |
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 MII_REG_ST_10= 0BASE_X_HD | MII_REG_ST_10_FD | MII_REG_ST_10_HD |
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 MII_REG_ST_10= 0BASE_T2_FD | MII_REG_ST_100BASE_T2_HD |
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 MII_REG_ST_AU= TONEG_COMPLETE | MII_REG_ST_AUTONEG_AVAIL;
> +
> +=C2=A0 =C2=A0 aw_h3_emac_mii_set_link(s, link_active);
> +}
> +
> +static void aw_h3_emac_mii_cmd(AwH3EmacState *s)
> +{
> +=C2=A0 =C2=A0 uint8_t addr, reg;
> +
> +=C2=A0 =C2=A0 addr =3D (s->mii_cmd & MII_CMD_PHY_ADDR_MASK) &g= t;> MII_CMD_PHY_ADDR_SHIFT;
> +=C2=A0 =C2=A0 reg =3D (s->mii_cmd & MII_CMD_PHY_REG_MASK) >= > MII_CMD_PHY_REG_SHIFT;
> +
> +=C2=A0 =C2=A0 if (addr !=3D s->mii_phy_addr) {
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 return;
> +=C2=A0 =C2=A0 }
> +
> +=C2=A0 =C2=A0 /* Read or write a PHY register? */
> +=C2=A0 =C2=A0 if (s->mii_cmd & MII_CMD_PHY_RW) {
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 trace_aw_h3_emac_mii_write_reg(reg, s->= ;mii_data);
> +
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 switch (reg) {
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 case MII_REG_CR:
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 if (s->mii_data & MI= I_REG_CR_RESET) {
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 aw_h3_emac_mi= i_reset(s, s->mii_st & MII_REG_ST_LINK_UP);
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 } else {
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 s->mii_cr = =3D s->mii_data & ~(MII_REG_CR_RESET |
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 MII_REG_CR_AUTO_NEG_RESTART);
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 }
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 break;
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 default:
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 qemu_log_mask(LOG_UNIMP, &q= uot;allwinner-h3-emac: write access to "
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0"unknow= n MII register 0x%x\n", reg);
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 break;
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 }
> +=C2=A0 =C2=A0 } else {
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 switch (reg) {
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 case MII_REG_CR:
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 s->mii_data =3D s->mi= i_cr;
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 break;
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 case MII_REG_ST:
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 s->mii_data =3D s->mi= i_st;
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 break;
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 case MII_REG_ID_HIGH:
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 s->mii_data =3D MII_PHY_= ID_HIGH;
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 break;
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 case MII_REG_ID_LOW:
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 s->mii_data =3D MII_PHY_= ID_LOW;
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 break;
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 default:
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 qemu_log_mask(LOG_UNIMP, &q= uot;allwinner-h3-emac: read access to "
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0"unknow= n MII register 0x%x\n", reg);
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 s->mii_data =3D 0;
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 break;
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 }
> +
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 trace_aw_h3_emac_mii_read_reg(reg, s->= mii_data);
> +=C2=A0 =C2=A0 }
> +}
> +
> +static void aw_h3_emac_update_irq(AwH3EmacState *s)
> +{
> +=C2=A0 =C2=A0 qemu_set_irq(s->irq, (s->int_sta & s->int_= en) !=3D 0);
> +}
> +
> +static uint32_t aw_h3_emac_next_desc(FrameDescriptor *desc, size_t mi= n_size)
> +{
> +=C2=A0 =C2=A0 uint32_t paddr =3D desc->next;
> +
> +=C2=A0 =C2=A0 cpu_physical_memory_read(paddr, desc, sizeof(*desc)); > +
> +=C2=A0 =C2=A0 if ((desc->status & DESC_STATUS_CTL) &&<= br> > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 (desc->status2 & DESC_STATUS2_BUF_= SIZE_MASK) >=3D min_size) {
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 return paddr;
> +=C2=A0 =C2=A0 } else {
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 return 0;
> +=C2=A0 =C2=A0 }
> +}
> +
> +static uint32_t aw_h3_emac_get_desc(FrameDescriptor *desc, uint32_t s= tart_addr,
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 size_t min_size) > +{
> +=C2=A0 =C2=A0 uint32_t desc_addr =3D start_addr;
> +
> +=C2=A0 =C2=A0 /* Note that the list is a cycle. Last entry points bac= k to the head. */
> +=C2=A0 =C2=A0 while (desc_addr !=3D 0) {
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 cpu_physical_memory_read(desc_addr, desc,= sizeof(*desc));
> +
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 if ((desc->status & DESC_STATUS_CT= L) &&
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 (desc->status2 & DES= C_STATUS2_BUF_SIZE_MASK) >=3D min_size) {
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 return desc_addr;
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 } else if (desc->next =3D=3D start_add= r) {
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 break;
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 } else {
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 desc_addr =3D desc->next= ;
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 }
> +=C2=A0 =C2=A0 }
> +
> +=C2=A0 =C2=A0 return 0;
> +}
> +
> +static uint32_t aw_h3_emac_get_rx_desc(AwH3EmacState *s, FrameDescrip= tor *desc,
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0size_= t min_size)
> +{
> +=C2=A0 =C2=A0 return aw_h3_emac_get_desc(desc, s->rx_desc_curr, mi= n_size);
> +}
> +
> +static uint32_t aw_h3_emac_get_tx_desc(AwH3EmacState *s, FrameDescrip= tor *desc,
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0size_= t min_size)
> +{
> +=C2=A0 =C2=A0 return aw_h3_emac_get_desc(desc, s->tx_desc_head, mi= n_size);
> +}
> +
> +static void aw_h3_emac_flush_desc(FrameDescriptor *desc, uint32_t phy= s_addr)
> +{
> +=C2=A0 =C2=A0 cpu_physical_memory_write(phys_addr, desc, sizeof(*desc= ));
> +}
> +
> +static int aw_h3_emac_can_receive(NetClientState *nc)
> +{
> +=C2=A0 =C2=A0 AwH3EmacState *s =3D qemu_get_nic_opaque(nc);
> +=C2=A0 =C2=A0 FrameDescriptor desc;
> +
> +=C2=A0 =C2=A0 return (s->rx_ctl0 & RX_CTL0_RX_EN) && > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0(aw_h3_emac_get_rx_desc(s, &= amp;desc, 0) !=3D 0);
> +}
> +
> +static ssize_t aw_h3_emac_receive(NetClientState *nc, const uint8_t *= buf,
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 size_t size)
> +{
> +=C2=A0 =C2=A0 AwH3EmacState *s =3D qemu_get_nic_opaque(nc);
> +=C2=A0 =C2=A0 FrameDescriptor desc;
> +=C2=A0 =C2=A0 size_t bytes_left =3D size;
> +=C2=A0 =C2=A0 size_t desc_bytes =3D 0;
> +=C2=A0 =C2=A0 size_t pad_fcs_size =3D 4;
> +=C2=A0 =C2=A0 size_t padding =3D 0;
> +
> +=C2=A0 =C2=A0 if (!(s->rx_ctl0 & RX_CTL0_RX_EN)) {
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 return -1;
> +=C2=A0 =C2=A0 }
> +
> +=C2=A0 =C2=A0 s->rx_desc_curr =3D aw_h3_emac_get_rx_desc(s, &d= esc, AW_H3_EMAC_MIN_PKT_SZ);
> +=C2=A0 =C2=A0 if (!s->rx_desc_curr) {
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 s->int_sta |=3D INT_STA_RX_BUF_UA;
> +=C2=A0 =C2=A0 }
> +
> +=C2=A0 =C2=A0 /* Keep filling RX descriptors until the whole frame is= written */
> +=C2=A0 =C2=A0 while (s->rx_desc_curr && bytes_left > 0)= {
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 desc.status &=3D ~DESC_STATUS_CTL; > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 desc.status &=3D ~RX_DESC_STATUS_FRM_= LEN_MASK;
> +
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 if (bytes_left =3D=3D size) {
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 desc.status |=3D RX_DESC_ST= ATUS_FIRST_DESC;
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 }
> +
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 if ((desc.status2 & DESC_STATUS2_BUF_= SIZE_MASK) <
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 (bytes_left + pad_fcs_size)= ) {
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 desc_bytes =3D desc.status2= & DESC_STATUS2_BUF_SIZE_MASK;
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 desc.status |=3D desc_bytes= << RX_DESC_STATUS_FRM_LEN_SHIFT;
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 } else {
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 padding =3D pad_fcs_size; > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 if (bytes_left < AW_H3_E= MAC_MIN_PKT_SZ) {
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 padding +=3D = (AW_H3_EMAC_MIN_PKT_SZ - bytes_left);
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 }
> +
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 desc_bytes =3D (bytes_left)= ;
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 desc.status |=3D RX_DESC_ST= ATUS_LAST_DESC;
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 desc.status |=3D (bytes_lef= t + padding)
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0 =C2=A0 =C2=A0 << RX_DESC_STATUS_FRM_LEN_SHIFT;
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 }
> +
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 cpu_physical_memory_write(desc.addr, buf,= desc_bytes);
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 aw_h3_emac_flush_desc(&desc, s->rx= _desc_curr);
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 trace_aw_h3_emac_receive(s->rx_desc_cu= rr, desc.addr, desc_bytes);
> +
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 /* Check if frame needs to raise the rece= ive interrupt */
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 if (!(desc.status2 & RX_DESC_STATUS2_= RX_INT_CTL)) {
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 s->int_sta |=3D INT_STA_= RX;
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 }
> +
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 /* Increment variables */
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 buf +=3D desc_bytes;
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 bytes_left -=3D desc_bytes;
> +
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 /* Move to the next descriptor */
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 s->rx_desc_curr =3D aw_h3_emac_next_de= sc(&desc, 64);
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 if (!s->rx_desc_curr) {
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 /* Not enough buffer space = available */
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 s->int_sta |=3D INT_STA_= RX_BUF_UA;
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 s->rx_desc_curr =3D s-&g= t;rx_desc_head;
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 break;
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 }
> +=C2=A0 =C2=A0 }
> +
> +=C2=A0 =C2=A0 /* Report receive DMA is finished */
> +=C2=A0 =C2=A0 s->rx_ctl1 &=3D ~RX_CTL1_RX_DMA_START;
> +=C2=A0 =C2=A0 aw_h3_emac_update_irq(s);
> +
> +=C2=A0 =C2=A0 return size;
> +}
> +
> +static void aw_h3_emac_transmit(AwH3EmacState *s)
> +{
> +=C2=A0 =C2=A0 NetClientState *nc =3D qemu_get_queue(s->nic);
> +=C2=A0 =C2=A0 FrameDescriptor desc;
> +=C2=A0 =C2=A0 size_t bytes =3D 0;
> +=C2=A0 =C2=A0 size_t packet_bytes =3D 0;
> +=C2=A0 =C2=A0 size_t transmitted =3D 0;
> +=C2=A0 =C2=A0 static uint8_t packet_buf[2048];
> +
> +=C2=A0 =C2=A0 s->tx_desc_curr =3D aw_h3_emac_get_tx_desc(s, &d= esc, 0);
> +
> +=C2=A0 =C2=A0 /* Read all transmit descriptors */
> +=C2=A0 =C2=A0 while (s->tx_desc_curr !=3D 0) {
> +
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 /* Read from physical memory into packet = buffer */
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 bytes =3D desc.status2 & DESC_STATUS2= _BUF_SIZE_MASK;
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 if (bytes + packet_bytes > sizeof(pack= et_buf)) {
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 desc.status |=3D TX_DESC_ST= ATUS_LENGTH_ERR;
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 break;
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 }
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 cpu_physical_memory_read(desc.addr, packe= t_buf + packet_bytes, bytes);
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 packet_bytes +=3D bytes;
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 desc.status &=3D ~DESC_STATUS_CTL; > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 aw_h3_emac_flush_desc(&desc, s->tx= _desc_curr);
> +
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 /* After the last descriptor, send the pa= cket */
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 if (desc.status2 & TX_DESC_STATUS2_LA= ST_DESC) {
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 if (desc.status2 & TX_D= ESC_STATUS2_CHECKSUM_MASK) {
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 net_checksum_= calculate(packet_buf, packet_bytes);
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 }
> +
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 qemu_send_packet(nc, packet= _buf, packet_bytes);
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 trace_aw_h3_emac_transmit(s= ->tx_desc_curr, desc.addr, bytes);
> +
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 packet_bytes =3D 0;
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 transmitted++;
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 }
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 s->tx_desc_curr =3D aw_h3_emac_next_de= sc(&desc, 0);
> +=C2=A0 =C2=A0 }
> +
> +=C2=A0 =C2=A0 /* Raise transmit completed interrupt */
> +=C2=A0 =C2=A0 if (transmitted > 0) {
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 s->int_sta |=3D INT_STA_TX;
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 s->tx_ctl1 &=3D ~TX_CTL1_TX_DMA_ST= ART;
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 aw_h3_emac_update_irq(s);
> +=C2=A0 =C2=A0 }
> +}
> +
> +static void aw_h3_emac_reset(DeviceState *dev)
> +{
> +=C2=A0 =C2=A0 AwH3EmacState *s =3D AW_H3_EMAC(dev);
> +=C2=A0 =C2=A0 NetClientState *nc =3D qemu_get_queue(s->nic);
> +
> +=C2=A0 =C2=A0 trace_aw_h3_emac_reset();
> +
> +=C2=A0 =C2=A0 s->mii_cmd =3D 0;
> +=C2=A0 =C2=A0 s->mii_data =3D 0;
> +=C2=A0 =C2=A0 s->basic_ctl0 =3D 0;
> +=C2=A0 =C2=A0 s->basic_ctl1 =3D 0;
> +=C2=A0 =C2=A0 s->int_en =3D 0;
> +=C2=A0 =C2=A0 s->int_sta =3D 0;
> +=C2=A0 =C2=A0 s->frm_flt =3D 0;
> +=C2=A0 =C2=A0 s->rx_ctl0 =3D 0;
> +=C2=A0 =C2=A0 s->rx_ctl1 =3D RX_CTL1_RX_MD;
> +=C2=A0 =C2=A0 s->rx_desc_head =3D 0;
> +=C2=A0 =C2=A0 s->rx_desc_curr =3D 0;
> +=C2=A0 =C2=A0 s->tx_ctl0 =3D 0;
> +=C2=A0 =C2=A0 s->tx_ctl1 =3D 0;
> +=C2=A0 =C2=A0 s->tx_desc_head =3D 0;
> +=C2=A0 =C2=A0 s->tx_desc_curr =3D 0;
> +=C2=A0 =C2=A0 s->tx_flowctl =3D 0;
> +
> +=C2=A0 =C2=A0 aw_h3_emac_mii_reset(s, !nc->link_down);
> +}
> +
> +static uint64_t aw_h3_emac_read(void *opaque, hwaddr offset, unsigned= size)
> +{
> +=C2=A0 =C2=A0 AwH3EmacState *s =3D opaque;

I'd put AW_H3_EMAC(opaque) here.

> +=C2=A0 =C2=A0 uint64_t value =3D 0;
> +=C2=A0 =C2=A0 FrameDescriptor desc;
> +
> +=C2=A0 =C2=A0 switch (offset) {
> +=C2=A0 =C2=A0 case REG_BASIC_CTL_0:=C2=A0 =C2=A0 =C2=A0 =C2=A0/* Basi= c Control 0 */
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 value =3D s->basic_ctl0;
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 break;
> +=C2=A0 =C2=A0 case REG_BASIC_CTL_1:=C2=A0 =C2=A0 =C2=A0 =C2=A0/* Basi= c Control 1 */
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 value =3D s->basic_ctl1;
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 break;
> +=C2=A0 =C2=A0 case REG_INT_STA:=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0/* Interrupt Status */
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 value =3D s->int_sta;
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 break;
> +=C2=A0 =C2=A0 case REG_INT_EN:=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 /* Interupt Enable */
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 value =3D s->int_en;
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 break;
> +=C2=A0 =C2=A0 case REG_TX_CTL_0:=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 /*= Transmit Control 0 */
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 value =3D s->tx_ctl0;
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 break;
> +=C2=A0 =C2=A0 case REG_TX_CTL_1:=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 /*= Transmit Control 1 */
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 value =3D s->tx_ctl1;
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 break;
> +=C2=A0 =C2=A0 case REG_TX_FLOW_CTL:=C2=A0 =C2=A0 =C2=A0 =C2=A0/* Tran= smit Flow Control */
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 value =3D s->tx_flowctl;
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 break;
> +=C2=A0 =C2=A0 case REG_TX_DMA_DESC_LIST:=C2=A0 /* Transmit Descriptor= List Address */
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 value =3D s->tx_desc_head;
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 break;
> +=C2=A0 =C2=A0 case REG_RX_CTL_0:=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 /*= Receive Control 0 */
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 value =3D s->rx_ctl0;
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 break;
> +=C2=A0 =C2=A0 case REG_RX_CTL_1:=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 /*= Receive Control 1 */
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 value =3D s->rx_ctl1;
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 break;
> +=C2=A0 =C2=A0 case REG_RX_DMA_DESC_LIST:=C2=A0 /* Receive Descriptor = List Address */
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 value =3D s->rx_desc_head;
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 break;
> +=C2=A0 =C2=A0 case REG_FRM_FLT:=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0/* Receive Frame Filter */
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 value =3D s->frm_flt;
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 break;
> +=C2=A0 =C2=A0 case REG_RX_HASH_0:=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0/*= Receive Hash Table 0 */
> +=C2=A0 =C2=A0 case REG_RX_HASH_1:=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0/*= Receive Hash Table 1 */
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 break;
> +=C2=A0 =C2=A0 case REG_MII_CMD:=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0/* Management Interface Command */
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 value =3D s->mii_cmd;
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 break;
> +=C2=A0 =C2=A0 case REG_MII_DATA:=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 /*= Management Interface Data */
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 value =3D s->mii_data;
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 break;
> +=C2=A0 =C2=A0 case REG_ADDR_HIGH:=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0/*= MAC Address High */
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 value =3D *(((uint32_t *) (s->conf.mac= addr.a)) + 1);
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 break;
> +=C2=A0 =C2=A0 case REG_ADDR_LOW:=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 /*= MAC Address Low */
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 value =3D *(uint32_t *) (s->conf.macad= dr.a);
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 break;
> +=C2=A0 =C2=A0 case REG_TX_DMA_STA:=C2=A0 =C2=A0 =C2=A0 =C2=A0 /* Tran= smit DMA Status */
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 break;
> +=C2=A0 =C2=A0 case REG_TX_CUR_DESC:=C2=A0 =C2=A0 =C2=A0 =C2=A0/* Tran= smit Current Descriptor */
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 value =3D s->tx_desc_curr;
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 break;
> +=C2=A0 =C2=A0 case REG_TX_CUR_BUF:=C2=A0 =C2=A0 =C2=A0 =C2=A0 /* Tran= smit Current Buffer */
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 if (s->tx_desc_curr !=3D 0) {
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 cpu_physical_memory_read(s-= >tx_desc_curr, &desc, sizeof(desc));
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 value =3D desc.addr;
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 } else {
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 value =3D 0;
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 }
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 break;
> +=C2=A0 =C2=A0 case REG_RX_DMA_STA:=C2=A0 =C2=A0 =C2=A0 =C2=A0 /* Rece= ive DMA Status */
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 break;
> +=C2=A0 =C2=A0 case REG_RX_CUR_DESC:=C2=A0 =C2=A0 =C2=A0 =C2=A0/* Rece= ive Current Descriptor */
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 value =3D s->rx_desc_curr;
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 break;
> +=C2=A0 =C2=A0 case REG_RX_CUR_BUF:=C2=A0 =C2=A0 =C2=A0 =C2=A0 /* Rece= ive Current Buffer */
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 if (s->rx_desc_curr !=3D 0) {
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 cpu_physical_memory_read(s-= >rx_desc_curr, &desc, sizeof(desc));
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 value =3D desc.addr;
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 } else {
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 value =3D 0;
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 }
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 break;
> +=C2=A0 =C2=A0 default:
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 qemu_log_mask(LOG_UNIMP, "allwinner-= h3-emac: read access to unknown "
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0"EMAC register 0x&quo= t; TARGET_FMT_plx "\n",
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 offset);
> +=C2=A0 =C2=A0 }
> +
> +=C2=A0 =C2=A0 trace_aw_h3_emac_read(offset, value);
> +=C2=A0 =C2=A0 return value;
> +}
> +
> +static void aw_h3_emac_write(void *opaque, hwaddr offset, uint64_t va= lue,
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0unsigned size)
> +{
> +=C2=A0 =C2=A0 AwH3EmacState *s =3D opaque;

The same.

> +=C2=A0 =C2=A0 NetClientState *nc =3D qemu_get_queue(s->nic);
> +
> +=C2=A0 =C2=A0 trace_aw_h3_emac_write(offset, value);
> +
> +=C2=A0 =C2=A0 switch (offset) {
> +=C2=A0 =C2=A0 case REG_BASIC_CTL_0:=C2=A0 =C2=A0 =C2=A0 =C2=A0/* Basi= c Control 0 */
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 s->basic_ctl0 =3D value;
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 break;
> +=C2=A0 =C2=A0 case REG_BASIC_CTL_1:=C2=A0 =C2=A0 =C2=A0 =C2=A0/* Basi= c Control 1 */
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 if (value & BASIC_CTL1_SOFTRST) {
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 aw_h3_emac_reset(DEVICE(s))= ;
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 value &=3D ~BASIC_CTL1_= SOFTRST;
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 }
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 s->basic_ctl1 =3D value;
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 if (aw_h3_emac_can_receive(nc)) {
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 qemu_flush_queued_packets(n= c);
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 }
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 break;
> +=C2=A0 =C2=A0 case REG_INT_STA:=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0/* Interrupt Status */
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 s->int_sta &=3D ~value;
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 aw_h3_emac_update_irq(s);
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 break;
> +=C2=A0 =C2=A0 case REG_INT_EN:=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 /* Interrupt Enable */
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 s->int_en =3D value;
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 aw_h3_emac_update_irq(s);
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 break;
> +=C2=A0 =C2=A0 case REG_TX_CTL_0:=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 /*= Transmit Control 0 */
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 s->tx_ctl0 =3D value;
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 break;
> +=C2=A0 =C2=A0 case REG_TX_CTL_1:=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 /*= Transmit Control 1 */
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 s->tx_ctl1 =3D value;
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 if (value & TX_CTL1_TX_DMA_EN) {
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 aw_h3_emac_transmit(s);
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 }
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 break;
> +=C2=A0 =C2=A0 case REG_TX_FLOW_CTL:=C2=A0 =C2=A0 =C2=A0 =C2=A0/* Tran= smit Flow Control */
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 s->tx_flowctl =3D value;
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 break;
> +=C2=A0 =C2=A0 case REG_TX_DMA_DESC_LIST:=C2=A0 /* Transmit Descriptor= List Address */
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 s->tx_desc_head =3D value;
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 s->tx_desc_curr =3D value;
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 break;
> +=C2=A0 =C2=A0 case REG_RX_CTL_0:=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 /*= Receive Control 0 */
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 s->rx_ctl0 =3D value;
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 break;
> +=C2=A0 =C2=A0 case REG_RX_CTL_1:=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 /*= Receive Control 1 */
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 s->rx_ctl1 =3D value | RX_CTL1_RX_MD;<= br> > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 if ((value & RX_CTL1_RX_DMA_EN) &= & aw_h3_emac_can_receive(nc)) {
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 qemu_flush_queued_packets(n= c);
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 }
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 break;
> +=C2=A0 =C2=A0 case REG_RX_DMA_DESC_LIST:=C2=A0 /* Receive Descriptor = List Address */
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 s->rx_desc_head =3D value;
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 s->rx_desc_curr =3D value;
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 break;
> +=C2=A0 =C2=A0 case REG_FRM_FLT:=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0/* Receive Frame Filter */
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 s->frm_flt =3D value;
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 break;
> +=C2=A0 =C2=A0 case REG_RX_HASH_0:=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0/*= Receive Hash Table 0 */
> +=C2=A0 =C2=A0 case REG_RX_HASH_1:=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0/*= Receive Hash Table 1 */
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 break;
> +=C2=A0 =C2=A0 case REG_MII_CMD:=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0/* Management Interface Command */
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 s->mii_cmd =3D value & ~MII_CMD_PH= Y_BUSY;
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 aw_h3_emac_mii_cmd(s);
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 break;
> +=C2=A0 =C2=A0 case REG_MII_DATA:=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 /*= Management Interface Data */
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 s->mii_data =3D value;
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 break;
> +=C2=A0 =C2=A0 case REG_ADDR_HIGH:=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0/*= MAC Address High */
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 s->conf.macaddr.a[4] =3D (value & = 0xff);
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 s->conf.macaddr.a[5] =3D (value & = 0xff00) >> 8;
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 break;
> +=C2=A0 =C2=A0 case REG_ADDR_LOW:=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 /*= MAC Address Low */
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 s->conf.macaddr.a[0] =3D (value & = 0xff);
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 s->conf.macaddr.a[1] =3D (value & = 0xff00) >> 8;
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 s->conf.macaddr.a[2] =3D (value & = 0xff0000) >> 16;
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 s->conf.macaddr.a[3] =3D (value & = 0xff000000) >> 24;
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 break;
> +=C2=A0 =C2=A0 case REG_TX_DMA_STA:=C2=A0 =C2=A0 =C2=A0 =C2=A0 /* Tran= smit DMA Status */
> +=C2=A0 =C2=A0 case REG_TX_CUR_DESC:=C2=A0 =C2=A0 =C2=A0 =C2=A0/* Tran= smit Current Descriptor */
> +=C2=A0 =C2=A0 case REG_TX_CUR_BUF:=C2=A0 =C2=A0 =C2=A0 =C2=A0 /* Tran= smit Current Buffer */
> +=C2=A0 =C2=A0 case REG_RX_DMA_STA:=C2=A0 =C2=A0 =C2=A0 =C2=A0 /* Rece= ive DMA Status */
> +=C2=A0 =C2=A0 case REG_RX_CUR_DESC:=C2=A0 =C2=A0 =C2=A0 =C2=A0/* Rece= ive Current Descriptor */
> +=C2=A0 =C2=A0 case REG_RX_CUR_BUF:=C2=A0 =C2=A0 =C2=A0 =C2=A0 /* Rece= ive Current Buffer */
> +=C2=A0 =C2=A0 case REG_RGMII_STA:=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0/*= RGMII Status */
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 break;
> +=C2=A0 =C2=A0 default:
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 qemu_log_mask(LOG_UNIMP, "allwinner-= h3-emac: write access to unknown "
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0"EMAC register 0x&quo= t; TARGET_FMT_plx "\n",
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 offset);
> +=C2=A0 =C2=A0 }
> +}
> +
> +static void aw_h3_emac_set_link(NetClientState *nc)
> +{
> +=C2=A0 =C2=A0 AwH3EmacState *s =3D qemu_get_nic_opaque(nc);
> +
> +=C2=A0 =C2=A0 trace_aw_h3_emac_set_link(!nc->link_down);
> +=C2=A0 =C2=A0 aw_h3_emac_mii_set_link(s, !nc->link_down);
> +}
> +
> +static const MemoryRegionOps aw_h3_emac_mem_ops =3D {
> +=C2=A0 =C2=A0 .read =3D aw_h3_emac_read,
> +=C2=A0 =C2=A0 .write =3D aw_h3_emac_write,
> +=C2=A0 =C2=A0 .endianness =3D DEVICE_NATIVE_ENDIAN,
> +=C2=A0 =C2=A0 .valid =3D {
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 .min_access_size =3D 4,
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 .max_access_size =3D 4,
> +=C2=A0 =C2=A0 },
> +};
> +
> +static NetClientInfo net_aw_h3_emac_info =3D {
> +=C2=A0 =C2=A0 .type =3D NET_CLIENT_DRIVER_NIC,
> +=C2=A0 =C2=A0 .size =3D sizeof(NICState),
> +=C2=A0 =C2=A0 .can_receive =3D aw_h3_emac_can_receive,
> +=C2=A0 =C2=A0 .receive =3D aw_h3_emac_receive,
> +=C2=A0 =C2=A0 .link_status_changed =3D aw_h3_emac_set_link,
> +};
> +
> +static void aw_h3_emac_init(Object *obj)
> +{
> +=C2=A0 =C2=A0 SysBusDevice *sbd =3D SYS_BUS_DEVICE(obj);
> +=C2=A0 =C2=A0 AwH3EmacState *s =3D AW_H3_EMAC(obj);
> +
> +=C2=A0 =C2=A0 memory_region_init_io(&s->iomem, OBJECT(s), &= ;aw_h3_emac_mem_ops, s,
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0 =C2=A0 TYPE_AW_H3_EMAC, AW_H3_EMAC_REGS_MEM_SIZE);
> +=C2=A0 =C2=A0 sysbus_init_mmio(sbd, &s->iomem);
> +=C2=A0 =C2=A0 sysbus_init_irq(sbd, &s->irq);
> +}
> +
> +static void aw_h3_emac_realize(DeviceState *dev, Error **errp)
> +{
> +=C2=A0 =C2=A0 AwH3EmacState *s =3D AW_H3_EMAC(dev);
> +
> +=C2=A0 =C2=A0 qemu_macaddr_default_if_unset(&s->conf.macaddr);=
> +=C2=A0 =C2=A0 s->nic =3D qemu_new_nic(&net_aw_h3_emac_info, &a= mp;s->conf,
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0 =C2=A0 object_get_typename(OBJECT(dev)), dev->id, s);
> +=C2=A0 =C2=A0 qemu_format_nic_info_str(qemu_get_queue(s->nic), s-&= gt;conf.macaddr.a);
> +}
> +
> +static Property aw_h3_emac_properties[] =3D {
> +=C2=A0 =C2=A0 DEFINE_NIC_PROPERTIES(AwH3EmacState, conf),
> +=C2=A0 =C2=A0 DEFINE_PROP_UINT8("phy-addr", AwH3EmacState, = mii_phy_addr, 0),
> +=C2=A0 =C2=A0 DEFINE_PROP_END_OF_LIST(),
> +};
> +
> +static int aw_h3_emac_post_load(void *opaque, int version_id)
> +{
> +=C2=A0 =C2=A0 AwH3EmacState *s =3D opaque;
> +
> +=C2=A0 =C2=A0 aw_h3_emac_set_link(qemu_get_queue(s->nic));
> +
> +=C2=A0 =C2=A0 return 0;
> +}
> +
> +static const VMStateDescription vmstate_aw_emac =3D {
> +=C2=A0 =C2=A0 .name =3D TYPE_AW_H3_EMAC,
> +=C2=A0 =C2=A0 .version_id =3D 1,
> +=C2=A0 =C2=A0 .minimum_version_id =3D 1,
> +=C2=A0 =C2=A0 .post_load =3D aw_h3_emac_post_load,
> +=C2=A0 =C2=A0 .fields =3D (VMStateField[]) {
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 VMSTATE_UINT8(mii_phy_addr, AwH3EmacState= ),
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 VMSTATE_UINT32(mii_cmd, AwH3EmacState), > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 VMSTATE_UINT32(mii_data, AwH3EmacState),<= br> > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 VMSTATE_UINT32(basic_ctl0, AwH3EmacState)= ,
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 VMSTATE_UINT32(basic_ctl1, AwH3EmacState)= ,
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 VMSTATE_UINT32(int_en, AwH3EmacState), > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 VMSTATE_UINT32(int_sta, AwH3EmacState), > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 VMSTATE_UINT32(frm_flt, AwH3EmacState), > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 VMSTATE_UINT32(rx_ctl0, AwH3EmacState), > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 VMSTATE_UINT32(rx_ctl1, AwH3EmacState), > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 VMSTATE_UINT32(rx_desc_head, AwH3EmacStat= e),
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 VMSTATE_UINT32(rx_desc_curr, AwH3EmacStat= e),
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 VMSTATE_UINT32(tx_ctl0, AwH3EmacState), > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 VMSTATE_UINT32(tx_ctl1, AwH3EmacState), > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 VMSTATE_UINT32(tx_desc_head, AwH3EmacStat= e),
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 VMSTATE_UINT32(tx_desc_curr, AwH3EmacStat= e),
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 VMSTATE_UINT32(tx_flowctl, AwH3EmacState)= ,
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 VMSTATE_END_OF_LIST()
> +=C2=A0 =C2=A0 }
> +};
> +
> +static void aw_h3_emac_class_init(ObjectClass *klass, void *data)
> +{
> +=C2=A0 =C2=A0 DeviceClass *dc =3D DEVICE_CLASS(klass);
> +
> +=C2=A0 =C2=A0 dc->realize =3D aw_h3_emac_realize;
> +=C2=A0 =C2=A0 dc->props =3D aw_h3_emac_properties;
> +=C2=A0 =C2=A0 dc->reset =3D aw_h3_emac_reset;
> +=C2=A0 =C2=A0 dc->vmsd =3D &vmstate_aw_emac;
> +}
> +
> +static const TypeInfo aw_h3_emac_info =3D {
> +=C2=A0 =C2=A0 .name=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0=3D TYPE_= AW_H3_EMAC,
> +=C2=A0 =C2=A0 .parent=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0=3D TYPE_SYS_B= US_DEVICE,
> +=C2=A0 =C2=A0 .instance_size=C2=A0 =3D sizeof(AwH3EmacState),
> +=C2=A0 =C2=A0 .instance_init=C2=A0 =3D aw_h3_emac_init,
> +=C2=A0 =C2=A0 .class_init=C2=A0 =C2=A0 =C2=A0=3D aw_h3_emac_class_ini= t,
> +};
> +
> +static void aw_h3_emac_register_types(void)
> +{
> +=C2=A0 =C2=A0 type_register_static(&aw_h3_emac_info);
> +}
> +
> +type_init(aw_h3_emac_register_types)
> diff --git a/hw/net/trace-events b/hw/net/trace-events
> index e70f12bee1..e9e2f26f68 100644
> --- a/hw/net/trace-events
> +++ b/hw/net/trace-events
> @@ -1,5 +1,15 @@
>=C2=A0 =C2=A0# See docs/devel/tracing.txt for syntax documentation.
>=C2=A0 =C2=A0
> +# allwinner-h3-emac.c
> +aw_h3_emac_mii_write_reg(uint32_t reg, uint32_t value) "MII writ= e: reg=3D0x%x value=3D0x%x"
> +aw_h3_emac_mii_read_reg(uint32_t reg, uint32_t value) "MII read:= reg=3D0x%x value=3D0x%x"
> +aw_h3_emac_receive(uint32_t desc, uint32_t paddr, uint32_t bytes) &qu= ot;RX packet: desc=3D0x%08x paddr=3D0x%08x bytes=3D%u"
> +aw_h3_emac_transmit(uint32_t desc, uint32_t paddr, uint32_t bytes) &q= uot;TX packet: desc=3D0x%08x paddr=3D0x%08x bytes=3D%u"
> +aw_h3_emac_reset(void) "HW reset"
> +aw_h3_emac_set_link(bool active) "Set link: active=3D%u" > +aw_h3_emac_read(uint64_t offset, uint64_t val) "MMIO read: offse= t=3D0x%" PRIx64 " value=3D0x%" PRIx64
> +aw_h3_emac_write(uint64_t offset, uint64_t val) "MMIO write: off= set=3D0x%" PRIx64 " value=3D0x%" PRIx64
> +
>=C2=A0 =C2=A0# etraxfs_eth.c
>=C2=A0 =C2=A0mdio_phy_read(int regnum, uint16_t value) "read phy_r= eg:%d value:0x%04x"
>=C2=A0 =C2=A0mdio_phy_write(int regnum, uint16_t value) "write phy= _reg:%d value:0x%04x"
> diff --git a/include/hw/arm/allwinner-h3.h b/include/hw/arm/allwinner-= h3.h
> index 7aff4ebbd2..b964a60f41 100644
> --- a/include/hw/arm/allwinner-h3.h
> +++ b/include/hw/arm/allwinner-h3.h
> @@ -31,6 +31,7 @@
>=C2=A0 =C2=A0#include "hw/misc/allwinner-h3-syscon.h"
>=C2=A0 =C2=A0#include "hw/misc/allwinner-h3-sid.h"
>=C2=A0 =C2=A0#include "hw/sd/allwinner-h3-sdhost.h"
> +#include "hw/net/allwinner-h3-emac.h"
>=C2=A0 =C2=A0#include "target/arm/cpu.h"
>=C2=A0 =C2=A0
>=C2=A0 =C2=A0#define AW_H3_SRAM_A1_BASE=C2=A0 =C2=A0 =C2=A0(0x00000000)=
> @@ -119,6 +120,7 @@ typedef struct AwH3State {
>=C2=A0 =C2=A0 =C2=A0 =C2=A0AwH3SysconState syscon;
>=C2=A0 =C2=A0 =C2=A0 =C2=A0AwH3SidState sid;
>=C2=A0 =C2=A0 =C2=A0 =C2=A0AwH3SDHostState mmc0;
> +=C2=A0 =C2=A0 AwH3EmacState emac;
>=C2=A0 =C2=A0 =C2=A0 =C2=A0GICState gic;
>=C2=A0 =C2=A0 =C2=A0 =C2=A0MemoryRegion sram_a1;
>=C2=A0 =C2=A0 =C2=A0 =C2=A0MemoryRegion sram_a2;
> diff --git a/include/hw/net/allwinner-h3-emac.h b/include/hw/net/allwi= nner-h3-emac.h
> new file mode 100644
> index 0000000000..a007d54472
> --- /dev/null
> +++ b/include/hw/net/allwinner-h3-emac.h
> @@ -0,0 +1,69 @@
> +/*
> + * Allwinner H3 EMAC emulation
> + *
> + * Copyright (C) 2019 Niek Linnenbank <nieklinnenbank@gmail.com>
> + *
> + * This program is free software: you can redistribute it and/or modi= fy
> + * it under the terms of the GNU General Public License as published = by
> + * the Free Software Foundation, either version 2 of the License, or<= br> > + * (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful, > + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.=C2=A0 See the=
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License<= br> > + * along with this program.=C2=A0 If not, see <http://www.gnu.o= rg/licenses/>.
> + */
> +
> +#ifndef ALLWINNER_H3_EMAC_H
> +#define ALLWINNER_H3_EMAC_H
> +
> +#include "qemu/units.h"
> +#include "net/net.h"
> +#include "qemu/fifo8.h"
> +#include "hw/net/mii.h"
> +#include "hw/sysbus.h"
> +
> +#define AW_H3_EMAC_REGS_MEM_SIZE=C2=A0 (1024)
> +
> +#define TYPE_AW_H3_EMAC "allwinner-h3-emac"
> +#define AW_H3_EMAC(obj) OBJECT_CHECK(AwH3EmacState, (obj), TYPE_AW_H3= _EMAC)
> +
> +typedef struct AwH3EmacState {
> +=C2=A0 =C2=A0 /*< private >*/
> +=C2=A0 =C2=A0 SysBusDevice=C2=A0 parent_obj;
> +=C2=A0 =C2=A0 /*< public >*/
> +
> +=C2=A0 =C2=A0 MemoryRegion iomem;
> +=C2=A0 =C2=A0 qemu_irq=C2=A0 =C2=A0 =C2=A0irq;
> +=C2=A0 =C2=A0 NICState=C2=A0 =C2=A0 =C2=A0*nic;
> +=C2=A0 =C2=A0 NICConf=C2=A0 =C2=A0 =C2=A0 conf;
> +
> +=C2=A0 =C2=A0 uint8_t=C2=A0 =C2=A0 =C2=A0 mii_phy_addr;
> +=C2=A0 =C2=A0 uint32_t=C2=A0 =C2=A0 =C2=A0mii_cmd;
> +=C2=A0 =C2=A0 uint32_t=C2=A0 =C2=A0 =C2=A0mii_data;
> +=C2=A0 =C2=A0 uint32_t=C2=A0 =C2=A0 =C2=A0mii_cr;
> +=C2=A0 =C2=A0 uint32_t=C2=A0 =C2=A0 =C2=A0mii_st;
> +
> +=C2=A0 =C2=A0 uint32_t=C2=A0 =C2=A0 =C2=A0basic_ctl0;
> +=C2=A0 =C2=A0 uint32_t=C2=A0 =C2=A0 =C2=A0basic_ctl1;
> +=C2=A0 =C2=A0 uint32_t=C2=A0 =C2=A0 =C2=A0int_en;
> +=C2=A0 =C2=A0 uint32_t=C2=A0 =C2=A0 =C2=A0int_sta;
> +=C2=A0 =C2=A0 uint32_t=C2=A0 =C2=A0 =C2=A0frm_flt;
> +
> +=C2=A0 =C2=A0 uint32_t=C2=A0 =C2=A0 =C2=A0rx_ctl0;
> +=C2=A0 =C2=A0 uint32_t=C2=A0 =C2=A0 =C2=A0rx_ctl1;
> +=C2=A0 =C2=A0 uint32_t=C2=A0 =C2=A0 =C2=A0rx_desc_head;
> +=C2=A0 =C2=A0 uint32_t=C2=A0 =C2=A0 =C2=A0rx_desc_curr;
> +
> +=C2=A0 =C2=A0 uint32_t=C2=A0 =C2=A0 =C2=A0tx_ctl0;
> +=C2=A0 =C2=A0 uint32_t=C2=A0 =C2=A0 =C2=A0tx_ctl1;
> +=C2=A0 =C2=A0 uint32_t=C2=A0 =C2=A0 =C2=A0tx_desc_head;
> +=C2=A0 =C2=A0 uint32_t=C2=A0 =C2=A0 =C2=A0tx_desc_curr;
> +=C2=A0 =C2=A0 uint32_t=C2=A0 =C2=A0 =C2=A0tx_flowctl;
> +
> +} AwH3EmacState;
> +
> +#endif
>

The rest seems ok to me. Thanks for the contribution :)!

Thanks! :-)
=C2=A0
Regards,
Niek


Cheers,
Fred



--
--000000000000354d600598d1e4fc-- From MAILER-DAEMON Tue Dec 03 21:15:28 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1icKCO-0004oE-41 for mharc-qemu-arm@gnu.org; Tue, 03 Dec 2019 21:15:28 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:34845) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1icKCF-0004gA-PX for qemu-arm@nongnu.org; Tue, 03 Dec 2019 21:15:22 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1icKC4-0004OP-WB for qemu-arm@nongnu.org; Tue, 03 Dec 2019 21:15:13 -0500 Received: from us-smtp-2.mimecast.com ([207.211.31.81]:42600 helo=us-smtp-delivery-1.mimecast.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1icKC4-00047o-On for qemu-arm@nongnu.org; Tue, 03 Dec 2019 21:15:08 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1575425702; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=wXEE1wJyPj6gtPCkc/kKuPTioY0kF5NKRS4t1wJ7Jmc=; b=C4xRQfObzwW5631IpFrJGDcK85FOkNpIirXrsx/oYcuul3+J7NqKm10i0Ah5AMD5eOPwuk erneeYbyEzC4HwDfT9Dao9iG8o920PT+IIYiLzHOYxAG13bGcu79dYoilvTCp16kDIF1WJ kAijK0m0dHKz7dR8QoLiO2/yeTIrnC4= Received: from mimecast-mx01.redhat.com (mimecast-mx01.redhat.com [209.132.183.4]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-251-CeDC4bRnON-60DPUodyBfg-1; Tue, 03 Dec 2019 21:15:00 -0500 Received: from smtp.corp.redhat.com (int-mx02.intmail.prod.int.phx2.redhat.com [10.5.11.12]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx01.redhat.com (Postfix) with ESMTPS id 75363107ACC4; Wed, 4 Dec 2019 02:14:58 +0000 (UTC) Received: from [10.72.12.78] (ovpn-12-78.pek2.redhat.com [10.72.12.78]) by smtp.corp.redhat.com (Postfix) with ESMTP id 7EE2060C80; Wed, 4 Dec 2019 02:14:51 +0000 (UTC) Subject: Re: [PATCH] net/imx_fec: Updating the IMX_FEC IP to support loopback mode. To: =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= , "Wasim, Bilal" Cc: "bilalwasim676@gmail.com" , "qemu-devel@nongnu.org" , "peter.maydell@linaro.org" , "aa1ronham@gmail.com" , "jcd@tribudubois.net" , "qemu-arm@nongnu.org" , "linux@roeck-us.net" References: <20191129150508.24404-1-bilalwasim676@gmail.com> <8c956ae31e8f44a2b831a5030b2448b4@SVR-IES-MBX-03.mgc.mentorg.com> From: Jason Wang Message-ID: Date: Wed, 4 Dec 2019 10:14:49 +0800 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101 Thunderbird/60.8.0 MIME-Version: 1.0 In-Reply-To: Content-Language: en-US X-Scanned-By: MIMEDefang 2.79 on 10.5.11.12 X-MC-Unique: CeDC4bRnON-60DPUodyBfg-1 X-Mimecast-Spam-Score: 0 Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 207.211.31.81 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 04 Dec 2019 02:15:23 -0000 On 2019/11/30 =E4=B8=8A=E5=8D=8812:04, Philippe Mathieu-Daud=C3=A9 wrote: > On Fri, Nov 29, 2019 at 4:59 PM Wasim, Bilal wro= te: >> Thanks for the pointers philippe.. Is the patch okay to be merged withou= t it or do I need to do a re-submission with the updated username ? > If there are no review comments on your patch, I think the maintainer > taking your patch can fix this details directly, no need to resend. > >> -----Original Message----- >> From: Philippe Mathieu-Daud=C3=A9 [mailto:philmd@redhat.com] >> Sent: Friday, November 29, 2019 8:38 PM >> To: bilalwasim676@gmail.com; qemu-devel@nongnu.org >> Cc: peter.maydell@linaro.org; aa1ronham@gmail.com; jcd@tribudubois.net; = qemu-arm@nongnu.org; Wasim, Bilal ; linux@roeck-us.= net; Jason Wang >> Subject: Re: [PATCH] net/imx_fec: Updating the IMX_FEC IP to support loo= pback mode. >> >> Hi Bilal, >> >> Cc'ing Jason, the maintainer of network devices. >> >> On 11/29/19 4:05 PM, bilalwasim676@gmail.com wrote: >>> From: bwasim >> Your git setup misses your 'user.name', you could fix it running: >> >> git config user.name "Bilal Wasim" >> >> (eventually with the --global option). >> >> The patch looks good otherwise. >> >> Thanks! Applied with the fix for user.name. Thanks >> >>> Loopback mode only works when specific conditions (as dictated by the >>> IP guide) are met, i.e. the MII_MODE is set and the RMII_MODE is >>> cleared. If not, we simply send the packet on the output queue (for TX >>> to the host network). Tested by running a custom RTOS and TXing a ton >>> of packets. The same packets were received on the RX side.. >>> >>> Signed-off-by: Bilal Wasim >>> --- >>> hw/net/imx_fec.c | 27 +++++++++++++++++++++++++-- >>> 1 file changed, 25 insertions(+), 2 deletions(-) >>> >>> diff --git a/hw/net/imx_fec.c b/hw/net/imx_fec.c index >>> bd99236864..c51e7f7363 100644 >>> --- a/hw/net/imx_fec.c >>> +++ b/hw/net/imx_fec.c >>> @@ -256,6 +256,29 @@ static const VMStateDescription vmstate_imx_eth = =3D >>> { >>> >>> static void imx_eth_update(IMXFECState *s); >>> >>> +/* >>> + * Function to check if the MAC is configured to run in loopback mode. >>> + * If so, invoke the "receive" routine. >>> + * Else write to the output. >>> + * */ >>> +static void send_pkt(IMXFECState *s, uint8_t *frame, int frame_size) >>> +{ >>> + NetClientState *nc =3D qemu_get_queue(s->nic); >>> + >>> + /* >>> + * Loopback or Normal mode ? >>> + * Per the FEC Manual: If loopback is enabled, the MII_MODE >>> + * should be SET and the RMII_MODE should be cleared. Loopback >>> + * will only work if this criterion is met. If not met, >>> + * we will send the frame on the output queue. */ >>> + if ((s->regs[ENET_RCR] & ENET_RCR_LOOP) && (s->regs[ENET_RCR] & EN= ET_RCR_MII_MODE) >>> + && !(s->regs[ENET_RCR] & ENET_RCR_RMII_MODE)) { >>> + nc->info->receive(nc, frame, frame_size); >>> + } else { >>> + qemu_send_packet(nc, frame, frame_size); >>> + } >>> +} >>> + >>> /* >>> * The MII phy could raise a GPIO to the processor which in turn >>> * could be handled as an interrpt by the OS. >>> @@ -488,7 +511,7 @@ static void imx_fec_do_tx(IMXFECState *s) >>> frame_size +=3D len; >>> if (bd.flags & ENET_BD_L) { >>> /* Last buffer in frame. */ >>> - qemu_send_packet(qemu_get_queue(s->nic), s->frame, frame_s= ize); >>> + send_pkt(s, (uint8_t *)&s->frame, frame_size); >>> ptr =3D s->frame; >>> frame_size =3D 0; >>> s->regs[ENET_EIR] |=3D ENET_INT_TXF; @@ -586,7 +609,7 @@ >>> static void imx_enet_do_tx(IMXFECState *s, uint32_t index) >>> } >>> /* Last buffer in frame. */ >>> >>> - qemu_send_packet(qemu_get_queue(s->nic), s->frame, frame_s= ize); >>> + send_pkt(s, (uint8_t *)&s->frame, frame_size); >>> ptr =3D s->frame; >>> >>> frame_size =3D 0; >>> From MAILER-DAEMON Wed Dec 04 01:14:29 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1icNvh-0002S1-1h for mharc-qemu-arm@gnu.org; Wed, 04 Dec 2019 01:14:29 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:49113) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1icNva-0002Qp-Px for qemu-arm@nongnu.org; Wed, 04 Dec 2019 01:14:24 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1icNvU-0005Pl-BP for qemu-arm@nongnu.org; Wed, 04 Dec 2019 01:14:19 -0500 Received: from szxga04-in.huawei.com ([45.249.212.190]:2210 helo=huawei.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1icNvT-0004YT-Te; Wed, 04 Dec 2019 01:14:16 -0500 Received: from DGGEMS402-HUB.china.huawei.com (unknown [172.30.72.58]) by Forcepoint Email with ESMTP id 6A12D230597084F36CD4; Wed, 4 Dec 2019 14:14:00 +0800 (CST) Received: from [127.0.0.1] (10.133.224.57) by DGGEMS402-HUB.china.huawei.com (10.3.19.202) with Microsoft SMTP Server id 14.3.439.0; Wed, 4 Dec 2019 14:13:54 +0800 From: Xiang Zheng Subject: Re: [PATCH 1/5] tests: fw_cfg: Rename pc_fw_cfg_* to fw_cfg_* To: Peter Maydell CC: Thomas Huth , Laurent Vivier , "Paolo Bonzini" , =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= , Laszlo Ersek , Gerd Hoffmann , qemu-arm , QEMU Developers , References: <20191203122753.19792-1-zhengxiang9@huawei.com> <20191203122753.19792-2-zhengxiang9@huawei.com> Message-ID: <76a92f2e-bf55-77e1-7691-30d76298aeca@huawei.com> Date: Wed, 4 Dec 2019 14:13:53 +0800 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:68.0) Gecko/20100101 Thunderbird/68.1.0 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset="utf-8" Content-Language: en-US Content-Transfer-Encoding: 7bit X-Originating-IP: [10.133.224.57] X-CFilter-Loop: Reflected X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 45.249.212.190 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 04 Dec 2019 06:14:24 -0000 On 2019/12/3 20:34, Peter Maydell wrote: > On Tue, 3 Dec 2019 at 12:29, Xiang Zheng wrote: >> >> Rename pc_fw_cfg_* to fw_cfg_* to make them common for other >> architectures so that we can run fw_cfg tests on aarch64. >> >> Signed-off-by: Xiang Zheng > >> -static inline QFWCFG *pc_fw_cfg_init(QTestState *qts) >> +static inline QFWCFG *fw_cfg_init(QTestState *qts) >> { >> - return io_fw_cfg_init(qts, 0x510); >> + const char *arch = qtest_get_arch(); >> + >> + if (!strcmp(arch, "aarch64")) { >> + return mm_fw_cfg_init(qts, 0x09020000); >> + } else { >> + return io_fw_cfg_init(qts, 0x510); >> + } > > Presence and address of the fw_cfg device depends > on the machine type, not the architecture, so is > it possible to write this so that it varies by > machine type, rather than by guest arch ? > There should also presumably be a fallback path > for "fw_cfg not present here", I suppose. > Yes, "0x09020000" is the address of the fw_cfg device on virt machine, I should have noticed it. I will have a try for varying the addresses by machine type. -- Thanks, Xiang From MAILER-DAEMON Wed Dec 04 01:14:35 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1icNvn-0002TC-8J for mharc-qemu-arm@gnu.org; Wed, 04 Dec 2019 01:14:35 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:49369) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1icNvg-0002R8-Dd for qemu-arm@nongnu.org; Wed, 04 Dec 2019 01:14:30 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1icNvZ-0005fw-BH for qemu-arm@nongnu.org; Wed, 04 Dec 2019 01:14:24 -0500 Received: from szxga07-in.huawei.com ([45.249.212.35]:46900 helo=huawei.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1icNvY-000551-Ut; Wed, 04 Dec 2019 01:14:21 -0500 Received: from DGGEMS412-HUB.china.huawei.com (unknown [172.30.72.60]) by Forcepoint Email with ESMTP id 8B58E170EB14C16A5A99; Wed, 4 Dec 2019 14:14:09 +0800 (CST) Received: from [127.0.0.1] (10.133.224.57) by DGGEMS412-HUB.china.huawei.com (10.3.19.212) with Microsoft SMTP Server id 14.3.439.0; Wed, 4 Dec 2019 14:14:02 +0800 From: Xiang Zheng Subject: Re: [PATCH 4/5] hw/arm/virt: Add FW_CFG_RAM_SIZE and FW_CFG_MAX_CPUS into fw_cfg To: Peter Maydell CC: Thomas Huth , Laurent Vivier , "Paolo Bonzini" , =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= , Laszlo Ersek , Gerd Hoffmann , qemu-arm , QEMU Developers , References: <20191203122753.19792-1-zhengxiang9@huawei.com> <20191203122753.19792-5-zhengxiang9@huawei.com> Message-ID: <3f4d33e2-df25-42f3-0896-31d4df32ea64@huawei.com> Date: Wed, 4 Dec 2019 14:14:00 +0800 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:68.0) Gecko/20100101 Thunderbird/68.1.0 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset="utf-8" Content-Language: en-US Content-Transfer-Encoding: 7bit X-Originating-IP: [10.133.224.57] X-CFilter-Loop: Reflected X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 45.249.212.35 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 04 Dec 2019 06:14:30 -0000 On 2019/12/3 20:32, Peter Maydell wrote: > On Tue, 3 Dec 2019 at 12:29, Xiang Zheng wrote: >> >> I'm not sure whether it's neccesary to add FW_CFG_RAM_SIZE and >> FW_CFG_MAX_CPUS into fw_cfg on virt machine. This patch just makes >> the fw_cfg-test happy. >> >> Signed-off-by: Xiang Zheng >> --- >> hw/arm/virt.c | 3 +++ >> 1 file changed, 3 insertions(+) >> >> diff --git a/hw/arm/virt.c b/hw/arm/virt.c >> index d4bedc2607..26a4183775 100644 >> --- a/hw/arm/virt.c >> +++ b/hw/arm/virt.c >> @@ -1084,6 +1084,9 @@ static FWCfgState *create_fw_cfg(const VirtMachineState *vms, AddressSpace *as) >> fw_cfg = fw_cfg_init_mem_wide(base + 8, base, 8, base + 16, as); >> fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, (uint16_t)ms->smp.cpus); >> >> + fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size); >> + fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, (uint16_t)ms->smp.max_cpus); >> + >> nodename = g_strdup_printf("/fw-cfg@%" PRIx64, base); >> qemu_fdt_add_subnode(vms->fdt, nodename); >> qemu_fdt_setprop_string(vms->fdt, nodename, >> -- > > Is there a spec anywhere that defines the meaning of these > FW_CFG entries ? docs/specs/fw_cfg.txt defines the > device interface but not what the 'standard' keys mean. > I'd prefer not to add them to the virt board without knowing > what they mean and why we have them. > I cannot find a spec or doc defines these FW_CFG entries. It seems that they are used on x86 machines to limit APIC ID values but useless on virt machine. I will drop this patch. -- Thanks, Xiang From MAILER-DAEMON Wed Dec 04 01:18:38 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1icNzh-0003jZ-TW for mharc-qemu-arm@gnu.org; Wed, 04 Dec 2019 01:18:37 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:59005) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1icNzb-0003hV-RK for qemu-arm@nongnu.org; Wed, 04 Dec 2019 01:18:33 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1icNzU-0008Us-Pr for qemu-arm@nongnu.org; Wed, 04 Dec 2019 01:18:26 -0500 Received: from szxga06-in.huawei.com ([45.249.212.32]:45878 helo=huawei.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1icNzU-0007np-BZ; Wed, 04 Dec 2019 01:18:24 -0500 Received: from DGGEMS405-HUB.china.huawei.com (unknown [172.30.72.58]) by Forcepoint Email with ESMTP id 9EB029CEB8646D368816; Wed, 4 Dec 2019 14:18:14 +0800 (CST) Received: from [127.0.0.1] (10.133.224.57) by DGGEMS405-HUB.china.huawei.com (10.3.19.205) with Microsoft SMTP Server id 14.3.439.0; Wed, 4 Dec 2019 14:18:06 +0800 Subject: Re: [PATCH 0/5] tests: Enable fw_cfg tests on AArch64 To: Thomas Huth , , CC: , , , , , , References: <20191203122753.19792-1-zhengxiang9@huawei.com> From: Xiang Zheng Message-ID: Date: Wed, 4 Dec 2019 14:18:04 +0800 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:68.0) Gecko/20100101 Thunderbird/68.1.0 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset="utf-8" Content-Language: en-US Content-Transfer-Encoding: 7bit X-Originating-IP: [10.133.224.57] X-CFilter-Loop: Reflected X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 45.249.212.32 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 04 Dec 2019 06:18:33 -0000 On 2019/12/3 21:01, Thomas Huth wrote: > On 03/12/2019 13.27, Xiang Zheng wrote: >> There are quite a few tests disabled on AArch64 such as fw_cfg-tests. >> This patch series fix some problems in test code and adapt it to >> virt machine. >> >> Xiang Zheng (5): >> tests: fw_cfg: Rename pc_fw_cfg_* to fw_cfg_* >> tests: fw_cfg: Support read/write of fw_cfg registers on aarch64 >> tests: fw_cfg: Use virt as default machine in fw_cfg-test.c >> hw/arm/virt: Add FW_CFG_RAM_SIZE and FW_CFG_MAX_CPUS into fw_cfg >> tests: Enable fw_cfg test on aarch64 > > Hi, > > this breaks "make check-qtest-ppc64": > > TEST check-qtest-ppc64: tests/boot-order-test > ** > ERROR:tests/boot-order-test.c:40:test_a_boot_order: assertion failed > (actual == expected_boot): (0x00000000 == 0x00000063) > > Please make sure that "make check" continuous to work with all other > targets, too. > Hi Thomas, Thanks for your suggestion, I will make sure for that. :) -- Thanks, Xiang From MAILER-DAEMON Wed Dec 04 04:04:04 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1icQZo-0005Lc-CL for mharc-qemu-arm@gnu.org; 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[88.21.103.182]) by smtp.gmail.com with ESMTPSA id c2sm7263359wrp.46.2019.12.04.01.03.08 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 04 Dec 2019 01:03:08 -0800 (PST) Subject: Re: [PATCH 02/10] hw: arm: add Xunlong Orange Pi PC machine To: Niek Linnenbank Cc: qemu-devel@nongnu.org, b.galvani@gmail.com, Peter Maydell , qemu-arm@nongnu.org References: <20191202210947.3603-1-nieklinnenbank@gmail.com> <20191202210947.3603-3-nieklinnenbank@gmail.com> From: =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= Message-ID: <239606dc-3545-c3f7-1e11-429f53994147@redhat.com> Date: Wed, 4 Dec 2019 10:03:07 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.2.2 MIME-Version: 1.0 In-Reply-To: Content-Language: en-US X-MC-Unique: 4h6D6CPFMNGGCRpIfnCnGQ-1 X-Mimecast-Spam-Score: 0 Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 7bit X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 205.139.110.120 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 04 Dec 2019 09:04:00 -0000 On 12/3/19 8:33 PM, Niek Linnenbank wrote: > Hello Philippe, > > Thanks for your quick review comments! > I'll start working on a v2 of the patches and include the changes you > suggested. Thanks, but I'd suggest to wait few more days to give time to others reviewers. Else having multiple versions of a big series reviewed at the same time is very confusing. I have other minor comments on others patches, but need to find the time to continue reviewing. From MAILER-DAEMON Wed Dec 04 04:05:39 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1icQbK-0005up-Rp for mharc-qemu-arm@gnu.org; Wed, 04 Dec 2019 04:05:38 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:60872) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1icQbB-0005nj-Qr for qemu-arm@nongnu.org; Wed, 04 Dec 2019 04:05:34 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1icQb3-0002Np-Fh for qemu-arm@nongnu.org; Wed, 04 Dec 2019 04:05:25 -0500 Received: from beetle.greensocs.com ([5.135.226.135]:40680) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1icQb2-0002BS-RS; Wed, 04 Dec 2019 04:05:21 -0500 Received: from [172.16.11.102] (crumble.bar.greensocs.com [172.16.11.102]) by beetle.greensocs.com (Postfix) with ESMTPSA id 1319896EF0; Wed, 4 Dec 2019 09:05:16 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=greensocs.com; s=mail; t=1575450317; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=+M0eJbitAjFgLnmEEkFN14ss5YnhHtCP/lJks2m5PoU=; b=BrVGheMS1SijpDbh9BB2yAZ8aAshUHGK1gCtkry5pxKboXiJ5IRsYYlXDoiLMekrs9zFav Xn2Gkdib40qBV4GTpMMqEn3TukPSVNajft1IOc+bR+a35Q+qIPzBWDQVNUlUpTxSGrIj/8 avZco9iGpTozTiltZkCHk9gQTbY9wY4= From: Damien Hedde Subject: Re: [PATCH v6 3/9] qdev: add clock input&output support to devices. To: Peter Maydell Cc: QEMU Developers , Mark Burton , "Edgar E. Iglesias" , Alistair Francis , =?UTF-8?Q?Marc-Andr=c3=a9_Lureau?= , Paolo Bonzini , "Daniel P. Berrange" , Eduardo Habkost , qemu-arm , =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= References: <20190904125531.27545-1-damien.hedde@greensocs.com> <20190904125531.27545-4-damien.hedde@greensocs.com> Message-ID: <8ac54ca8-4acf-5145-9ead-6791a5181617@greensocs.com> Date: Wed, 4 Dec 2019 10:05:16 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.2.0 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=utf-8 Content-Language: en-US-large Content-Transfer-Encoding: 7bit ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=greensocs.com; s=mail; t=1575450317; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=+M0eJbitAjFgLnmEEkFN14ss5YnhHtCP/lJks2m5PoU=; b=dFYrHkVAuxmer0WsqunZnmIjRuYHu/0p60LPyJZFH4/vSxIxtmfhwAmSfs591kPnaw+plm YxnimAV6jdI4tz1ryX8DSCZu294lSf32PcG4pcMMw0v/mqPKpxpVX7IwquHhn6C9GXbsQ8 sOGEWVo8SQgbTES6DcTCGiR/sGcxt2w= ARC-Seal: i=1; s=mail; d=greensocs.com; t=1575450317; a=rsa-sha256; cv=none; b=TPA45jSn4WBMtWnkHnc0xyII4cym2ConvK1Eeut6Z2QKd+2WIVa0drSzWmrK+3GyXl42lp MDsetdRArx2YCUwaOw6jOxPyWNd5+5QgsA0Ez4TK5Lc8aGA3oXstw+LDObY2zXfOXHhIoT qgHKP+XwQWCbalWqP6x0yuomkz1lAZ0= ARC-Authentication-Results: i=1; ORIGINATING; auth=pass smtp.auth=damien smtp.mailfrom=damien.hedde@greensocs.com X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 5.135.226.135 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 04 Dec 2019 09:05:34 -0000 On 12/2/19 3:34 PM, Peter Maydell wrote: > On Wed, 4 Sep 2019 at 13:56, Damien Hedde wrote: >> >> Add functions to easily add input or output clocks to a device. >> A clock objects is added as a child of the device. > > "object" > >> The api is very similar the gpio's one. > > "API"; "to the GPIO API". > >> >> This is based on the original work of Frederic Konrad. >> >> Signed-off-by: Damien Hedde >> > >> +static NamedClockList *qdev_init_clocklist(DeviceState *dev, const char *name, >> + bool forward) >> +{ >> + NamedClockList *ncl; >> + >> + /* >> + * The clock path will be computed by the device's realize function call. >> + * This is required to ensure the clock's canonical path is right and log >> + * messages are meaningfull. > > "meaningful" > >> + */ >> + assert(name); >> + assert(!dev->realized); >> + >> + /* The ncl structure will be freed in device's finalize function call */ > > Do you mean "in device_finalize()", or "in the finalize method > of the device" ? If you mean a specific function, then it's > good to name it, so the reader can go and check that code if > they need to confirm that there's a matching free()/deref/etc. Yes, it is device_finalize(). I'll update the comment. > >> + ncl = g_malloc0(sizeof(*ncl)); > > Prefer g_new0(NamedClockList, 1). > >> + ncl->name = g_strdup(name); >> + ncl->forward = forward; >> + >> + QLIST_INSERT_HEAD(&dev->clocks, ncl, node); >> + return ncl; >> +} >> + >> +ClockOut *qdev_init_clock_out(DeviceState *dev, const char *name) >> +{ >> + NamedClockList *ncl; >> + Object *clk; >> + >> + ncl = qdev_init_clocklist(dev, name, false); >> + >> + clk = object_new(TYPE_CLOCK_OUT); >> + >> + /* will fail if name already exists */ > > This is true but it would be more helpful to say > /* > * Trying to create a clock whose name clashes with some other > * clock or property is a bug in the caller and we will abort(). > */ > > (assuming that's what's going on here). You're right. > >> + object_property_add_child(OBJECT(dev), name, clk, &error_abort); >> + object_unref(clk); /* remove the initial ref made by object_new */ >> + >> + ncl->out = CLOCK_OUT(clk); >> + return ncl->out; >> +} >> + >> +ClockIn *qdev_init_clock_in(DeviceState *dev, const char *name, >> + ClockCallback *callback, void *opaque) >> +{ >> + NamedClockList *ncl; >> + Object *clk; >> + >> + ncl = qdev_init_clocklist(dev, name, false); >> + >> + clk = object_new(TYPE_CLOCK_IN); >> + /* >> + * the ref initialized by object_new will be cleared during dev finalize. > > This means "in device_finalize()", I think from reading later patches ? Yes. I'll update the comment too. > >> + * It allows us to safely remove the callback. >> + */ >> + >> + /* will fail if name already exists */ > > Similar remark as for earlier comment. > >> + object_property_add_child(OBJECT(dev), name, clk, &error_abort); >> + >> + ncl->in = CLOCK_IN(clk); >> + if (callback) { >> + clock_set_callback(ncl->in, callback, opaque); >> + } >> + return ncl->in; >> +} > >> +ClockIn *qdev_get_clock_in(DeviceState *dev, const char *name) >> +{ >> + NamedClockList *ncl; >> + >> + assert(dev && name); >> + >> + ncl = qdev_get_clocklist(dev, name); >> + return ncl ? ncl->in : NULL; >> +} > > Do we expect to want to be able to pass in the name of > a clock that doesn't exist ? Should that be an error > rather than returning NULL ? I think it can be an error and we may assert the clock exists. > >> + >> +static ClockOut *qdev_get_clock_out(DeviceState *dev, const char *name) >> +{ >> + NamedClockList *ncl; >> + >> + assert(dev && name); >> + >> + ncl = qdev_get_clocklist(dev, name); >> + return ncl ? ncl->out : NULL; > > Ditto. > >> +} >> + >> +void qdev_connect_clock_out(DeviceState *dev, const char *name, ClockIn *clk, >> + Error **errp) >> +{ >> + ClockOut *clkout = qdev_get_clock_out(dev, name); >> + >> + if (!clk) { >> + error_setg(errp, "NULL input clock"); >> + return; >> + } >> + >> + if (!clkout) { >> + error_setg(errp, "no output clock '%s' in device", name); >> + return; >> + } >> + >> + clock_connect(clk, clkout); > > Do we need to support returning an error here, or would it > always be a programming bug to try to connect a non-existent clock? As for above, I think it can be considered an error. Should I remove the errp and do an assert instead ? > >> --- /dev/null >> +++ b/include/hw/qdev-clock.h >> @@ -0,0 +1,67 @@ >> +#ifndef QDEV_CLOCK_H >> +#define QDEV_CLOCK_H > > Another missing copyright/license comment. > >> + >> +#include "hw/clock.h" >> + >> +/** >> + * qdev_init_clock_in: >> + * @dev: the device in which to add a clock > > "the device to add a clock input to" > >> + * @name: the name of the clock (can't be NULL). >> + * @callback: optional callback to be called on update or NULL. >> + * @opaque: argument for the callback >> + * @returns: a pointer to the newly added clock >> + * >> + * Add a input clock to device @dev as a clock named @name. >> + * This adds a child<> property. >> + * The callback will be called with @dev as opaque parameter. > > Isn't it called with @opaque, not @dev ? > >> + */ >> +ClockIn *qdev_init_clock_in(DeviceState *dev, const char *name, >> + ClockCallback *callback, void *opaque); >> + >> +/** >> + * qdev_init_clock_out: >> + * @dev: the device to add a clock to > > "the device to add a clock output to" > >> + * @name: the name of the clock (can't be NULL). >> + * @callback: optional callback to be called on update or NULL. >> + * @returns: a pointer to the newly added clock >> + * >> + * Add a output clock to device @dev as a clock named @name. >> + * This adds a child<> property. >> + */ >> +ClockOut *qdev_init_clock_out(DeviceState *dev, const char *name); >> + >> +/** >> + * qdev_get_clock_in: >> + * @dev: the device which has the clock >> + * @name: the name of the clock (can't be NULL). >> + * @returns: a pointer to the clock >> + * >> + * Get the clock @name from @dev or NULL if does not exists. > > "if it does not exist" > >> + */ >> +ClockIn *qdev_get_clock_in(DeviceState *dev, const char *name); >> + >> +/** >> + * qdev_connect_clock_out: >> + * @dev: the device which has the clock >> + * @name: the name of the clock (can't be NULL). >> + * @errp: error report >> + * >> + * Connect @clk to the output clock @name of @dev. >> + * Reports an error if clk is NULL or @name does not exists in @dev. > > "or if @name does not exist in @dev" > >> + */ >> +void qdev_connect_clock_out(DeviceState *dev, const char *name, ClockIn *clk, >> + Error **errp); >> + >> +/** >> + * qdev_pass_clock: >> + * @dev: the device to forward the clock to >> + * @name: the name of the clock to be added (can't be NULL) >> + * @container: the device which already has the clock >> + * @cont_name: the name of the clock in the container device >> + * >> + * Add a clock @name to @dev which forward to the clock @cont_name in @container >> + */ > > 'container' seems odd terminology here, because I would expect > the usual use of this function to be when a 'container' object > like an SoC wants to forward a clock to one of its components; > in that case the 'container' SoC would be @dev, wouldn't it? Yes. I agree it is confusing. This function just allow a a device 'A' to exhibit a clock from another device 'B' (typically a composing sub-device, inside a soc like you said). The device A is not supposed to interact with the clock itself. The original sub-device is the true owner/controller of the clock and is the only one which should use the clock API: setting a callback on it (input clock); or updating the clock frequency (output clock). Basically, it just add the clock into the device clock namespace without interfering with it. > We should get this to be the same way round as qdev_pass_gpios(), > which takes "DeviceState *dev, DeviceState *container", and > passes the gpios that exist on 'dev' over to 'container' so that > 'container' now has gpios which it did not before. Ok, I'll invert the arguments. > > Also, your use of 'forward to' is inconsistent: in the 'dev' > documentation you say we're forwarding the clock to 'dev', > but in the body of the documentation you say we're forwarding > the clock to the clock in 'container'. I'll try to clarify this and make the documentation more consistent with the comments here. > > I think the way to resolve this is to stick to the terminology > in the function name itself: > @dev: the device which has the clock > @name: the name of the clock on @dev > @container: the name of the device which the clock should > be passed to > @cont_name: the name to use for the clock on @container I think container is confusing because depending on how we reason (clock in a device; device in another device), we end up thinking the opposite. Maybe we can use "exhibit" instead of "container" in the 2nd pair of parameters, or prefix use "origin" or "owner" as a prefix for the first pair of parameters. > > Q: if you pass a clock to another device with this function, > does it still exist to be used directly on the original > device? For qdev_pass_gpios it does not (I think), but > this is more accident of implementation than anything else. It depends what we mean by "used by". Original device can: + set the callback in case it is an input + update the frequency in case it is an output But since an input clock can only be connected once, I think the logic here is that any connection should now go through the new device. But this is not checked and using one or the other is exactly the same. Maybe I misunderstood the meaning of qdev_pass_gpios(). > >> +void qdev_pass_clock(DeviceState *dev, const char *name, >> + DeviceState *container, const char *cont_name); >> + >> +#endif /* QDEV_CLOCK_H */ >> diff --git a/include/hw/qdev-core.h b/include/hw/qdev-core.h >> index eb11f0f801..60a65f6142 100644 >> --- a/include/hw/qdev-core.h >> +++ b/include/hw/qdev-core.h >> @@ -131,6 +131,19 @@ struct NamedGPIOList { >> QLIST_ENTRY(NamedGPIOList) node; >> }; >> >> +typedef struct NamedClockList NamedClockList; >> + >> +typedef struct ClockIn ClockIn; >> +typedef struct ClockOut ClockOut; >> + >> +struct NamedClockList { >> + char *name; > > Could this be 'const char*' ? Yes. -- Damien From MAILER-DAEMON Wed Dec 04 04:54:03 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1icRMB-0005JU-At for mharc-qemu-arm@gnu.org; Wed, 04 Dec 2019 04:54:03 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:46065) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1icRM8-0005FA-NW for qemu-arm@nongnu.org; Wed, 04 Dec 2019 04:54:01 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1icRLz-0003qA-G6 for qemu-arm@nongnu.org; Wed, 04 Dec 2019 04:53:53 -0500 Received: from us-smtp-2.mimecast.com ([205.139.110.61]:33504 helo=us-smtp-delivery-1.mimecast.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1icRLy-0003Zq-Ay for qemu-arm@nongnu.org; Wed, 04 Dec 2019 04:53:51 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1575453226; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=0dwGLHg0baVBbBxWdrAAkf8RroB3yMWuAT5RxiT1E98=; b=dDkqwAiEZoEOmSghJwrZnW4Bk/GBYHG2FVLl8UMs2Dyco1lo5LwJRSWqLePObTEmrKxdGd 1j0kOYUKMrlNpYkySPbO5gQiI8zZ39GnmSip2ySepwsW5HzBElLbNVTqQfj+pR/P655qRv cH/SChfUXH0yc0pwCx6vYdm0qvFggoc= Received: from mail-wr1-f69.google.com (mail-wr1-f69.google.com [209.85.221.69]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-142-Uf6a6dCNO2SLpTP5hn71Pw-1; Wed, 04 Dec 2019 04:53:45 -0500 Received: by mail-wr1-f69.google.com with SMTP id u12so3375107wrt.15 for ; Wed, 04 Dec 2019 01:53:45 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:subject:to:cc:references:from:message-id:date :user-agent:mime-version:in-reply-to:content-language :content-transfer-encoding; bh=0dwGLHg0baVBbBxWdrAAkf8RroB3yMWuAT5RxiT1E98=; b=QiU5ndYCbeJShSBZ8nyhioQcd+NFFjhPFa7GXsEff858m0SLFr0TiD3QvXgQxfPzKn zYJiAQCI34p0hXMcpd+t9AYRvAgVvbTDJ8BpsQ3ICdiyxgvvKp8fMMdpIPEWYERYPyuO Rl0BAAzQIeVsPl10KZgqFy3pPl6hE62SiKHF2EQQkPybq54J15lNtXpYioNHhMPu4q5p DwdGKEsyqRnrLfDDQU8SLH0twKF+xt1psfDX36YVfYHOw/S7YeViEgKMc2ZCXgTiFFlk GmWRtY6NPTo8dhyOMZSWSU7Z045aIvNkQbmNHdlajj4M34WbIIUyheMxqacMz5BnXgu5 ydQw== X-Gm-Message-State: APjAAAWSTeFdQNw0WTLQq3EORbJaQxF0FjsgFMoeO4AUa0D9RVVnEz9P wFU/pVuczqcgw/1MOqOsgGUpMHae1s8GBrJTSxmt1b1Qa7xkF/2pL9xMZrrFUjdQrHb2OC/bSej 7HizVyIm0AD7Q X-Received: by 2002:adf:ea8a:: with SMTP id s10mr2942141wrm.278.1575453223867; Wed, 04 Dec 2019 01:53:43 -0800 (PST) X-Google-Smtp-Source: APXvYqzKjVeX6p5sK6geDepDnzyjqoq2fWYNHA/bDrKnnUO07emB2SMpMqnixhvjcNd6UuT4xECv4w== X-Received: by 2002:adf:ea8a:: with SMTP id s10mr2942113wrm.278.1575453223568; Wed, 04 Dec 2019 01:53:43 -0800 (PST) Received: from [10.201.33.36] ([195.166.127.210]) by smtp.gmail.com with ESMTPSA id k19sm6024344wmi.42.2019.12.04.01.53.42 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 04 Dec 2019 01:53:43 -0800 (PST) Subject: Re: [PATCH v6 3/9] qdev: add clock input&output support to devices. To: Damien Hedde , Peter Maydell Cc: QEMU Developers , Mark Burton , "Edgar E. Iglesias" , Alistair Francis , =?UTF-8?Q?Marc-Andr=c3=a9_Lureau?= , Paolo Bonzini , "Daniel P. Berrange" , Eduardo Habkost , qemu-arm References: <20190904125531.27545-1-damien.hedde@greensocs.com> <20190904125531.27545-4-damien.hedde@greensocs.com> <8ac54ca8-4acf-5145-9ead-6791a5181617@greensocs.com> From: =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= Message-ID: Date: Wed, 4 Dec 2019 10:53:41 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.2.2 MIME-Version: 1.0 In-Reply-To: <8ac54ca8-4acf-5145-9ead-6791a5181617@greensocs.com> Content-Language: en-US X-MC-Unique: Uf6a6dCNO2SLpTP5hn71Pw-1 X-Mimecast-Spam-Score: 0 Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 7bit X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 205.139.110.61 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 04 Dec 2019 09:54:02 -0000 On 12/4/19 10:05 AM, Damien Hedde wrote: > On 12/2/19 3:34 PM, Peter Maydell wrote: >> On Wed, 4 Sep 2019 at 13:56, Damien Hedde wrote: >>> [...] >>> +/** >>> + * qdev_pass_clock: >>> + * @dev: the device to forward the clock to >>> + * @name: the name of the clock to be added (can't be NULL) >>> + * @container: the device which already has the clock >>> + * @cont_name: the name of the clock in the container device >>> + * >>> + * Add a clock @name to @dev which forward to the clock @cont_name in @container >>> + */ >> >> 'container' seems odd terminology here, because I would expect >> the usual use of this function to be when a 'container' object >> like an SoC wants to forward a clock to one of its components; >> in that case the 'container' SoC would be @dev, wouldn't it? > > Yes. I agree it is confusing. > This function just allow a a device 'A' to exhibit a clock from another > device 'B' (typically a composing sub-device, inside a soc like you > said). The device A is not supposed to interact with the clock itself. > The original sub-device is the true > owner/controller of the clock and is the only one which should use the > clock API: setting a callback on it (input clock); or updating the clock > frequency (output clock). > Basically, it just add the clock into the device clock namespace without > interfering with it. > >> We should get this to be the same way round as qdev_pass_gpios(), >> which takes "DeviceState *dev, DeviceState *container", and >> passes the gpios that exist on 'dev' over to 'container' so that >> 'container' now has gpios which it did not before. > > Ok, I'll invert the arguments. > >> >> Also, your use of 'forward to' is inconsistent: in the 'dev' >> documentation you say we're forwarding the clock to 'dev', >> but in the body of the documentation you say we're forwarding >> the clock to the clock in 'container'. > > I'll try to clarify this and make the documentation more consistent with > the comments here. > >> >> I think the way to resolve this is to stick to the terminology >> in the function name itself: >> @dev: the device which has the clock >> @name: the name of the clock on @dev >> @container: the name of the device which the clock should >> be passed to >> @cont_name: the name to use for the clock on @container > > I think container is confusing because depending on how we reason (clock > in a device; device in another device), we end up thinking the opposite. > > Maybe we can use "exhibit" instead of "container" in the 2nd pair of > parameters, or prefix use "origin" or "owner" as a prefix for the first > pair of parameters. @sink vs @source? >> Q: if you pass a clock to another device with this function, >> does it still exist to be used directly on the original >> device? For qdev_pass_gpios it does not (I think), but >> this is more accident of implementation than anything else. > > It depends what we mean by "used by". > Original device can: > + set the callback in case it is an input > + update the frequency in case it is an output Hmm here you use @input vs @output... > But since an input clock can only be connected once, > I think the logic here is that any connection should now go through the > new device. But this is not checked and using one or the other is > exactly the same. > > Maybe I misunderstood the meaning of qdev_pass_gpios(). [...] From MAILER-DAEMON Wed Dec 04 06:05:10 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1icST0-0002IA-38 for mharc-qemu-arm@gnu.org; Wed, 04 Dec 2019 06:05:10 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:47776) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1icSSr-0002CJ-6M for qemu-arm@nongnu.org; Wed, 04 Dec 2019 06:05:04 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1icSSk-00084g-Il for qemu-arm@nongnu.org; Wed, 04 Dec 2019 06:04:56 -0500 Received: from beetle.greensocs.com ([5.135.226.135]:44230) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1icSSi-0007Mo-8r; Wed, 04 Dec 2019 06:04:53 -0500 Received: from [172.16.11.102] (crumble.bar.greensocs.com [172.16.11.102]) by beetle.greensocs.com (Postfix) with ESMTPSA id A476D96EF0; Wed, 4 Dec 2019 11:04:42 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=greensocs.com; s=mail; t=1575457483; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=hcjwxM4UObU02Iu0FnUFEfgmhSEGsz5B6l28uOEWu2U=; b=1uvJNFWEMFotdydoqOGFrDvv/196PrbDBQalc4K9pVlXsGCmQtjKOK2xOFpH8fagwYtzBf nz4qX9BQtv92JW+ViG8XeQkY/JQ72MaJwxEMHuLkFzLBZBwNoEoWXHnUgxsCwWiqrVxWPK sL/M3+QFGiZwHcJ09A2/VDI6la7QFyQ= Subject: Re: [PATCH v6 5/9] qdev-clock: introduce an init array to ease the device construction To: Peter Maydell Cc: QEMU Developers , Mark Burton , "Edgar E. Iglesias" , Alistair Francis , =?UTF-8?Q?Marc-Andr=c3=a9_Lureau?= , Paolo Bonzini , "Daniel P. Berrange" , Eduardo Habkost , qemu-arm , =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= References: <20190904125531.27545-1-damien.hedde@greensocs.com> <20190904125531.27545-6-damien.hedde@greensocs.com> From: Damien Hedde Message-ID: <102dda6f-ca2d-7d16-0a65-8f6d5a6d1d46@greensocs.com> Date: Wed, 4 Dec 2019 12:04:42 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.2.0 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=utf-8 Content-Language: en-US-large ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=greensocs.com; s=mail; t=1575457483; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=hcjwxM4UObU02Iu0FnUFEfgmhSEGsz5B6l28uOEWu2U=; b=rVwR/jUlT7f/nrP/jeiZzwLoeaVKbTGAbtVgjWOOSJkz+T3XKLsYSe1v9hCdRaGGF4I/Ob sulxMi3qF/yBiUCqOsgSHRXTf3WgtgvPWR/h5turZ2ncYRn+Sx9cPSa5XmN60qpCdJIGEN xNQtVwmZy5B1eN4ctPh8NofjwEYLGBA= ARC-Seal: i=1; s=mail; d=greensocs.com; t=1575457483; a=rsa-sha256; cv=none; b=Oqs2WeakP7YcTe0+dleEMc/eRA3F9RRrNMMczPRsT5NuYJCdCVJPSv0gIIu6NEC1ElX3XY Rg1HC6j38PTiO1aarrSKB508ta64OFjrj4OM4LxLog/slhLbit0jRQleMVkTWZ0gq5OfYP OFOjdB4XZLwWBRmTRU7mnmBS2PuxXAI= ARC-Authentication-Results: i=1; ORIGINATING; auth=pass smtp.auth=damien smtp.mailfrom=damien.hedde@greensocs.com Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 5.135.226.135 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 04 Dec 2019 11:05:05 -0000 On 12/2/19 4:13 PM, Peter Maydell wrote: > On Wed, 4 Sep 2019 at 13:56, Damien Hedde = wrote: >> >> Introduce a function and macro helpers to setup several clocks >> in a device from a static array description. >> >> An element of the array describes the clock (name and direction) as >> well as the related callback and an optional offset to store the >> created object pointer in the device state structure. >> >> The array must be terminated by a special element QDEV_CLOCK_END. >> >> This is based on the original work of Frederic Konrad. >> >> Signed-off-by: Damien Hedde >> Reviewed-by: Philippe Mathieu-Daud=C3=A9 >> --- >> hw/core/qdev-clock.c | 26 ++++++++++++++++ >> include/hw/qdev-clock.h | 67 ++++++++++++++++++++++++++++++++++++++++= + >> 2 files changed, 93 insertions(+) >> >> diff --git a/hw/core/qdev-clock.c b/hw/core/qdev-clock.c >> index bebdd8fa15..32ad45c061 100644 >> --- a/hw/core/qdev-clock.c >> +++ b/hw/core/qdev-clock.c >> @@ -153,3 +153,29 @@ void qdev_connect_clock_out(DeviceState *dev, con= st char *name, ClockIn *clk, >> >> clock_connect(clk, clkout); >> } >> + >> +void qdev_init_clocks(DeviceState *dev, const ClockPortInitArray cloc= ks) >> +{ >> + const struct ClockPortInitElem *elem; >> + >> + assert(dev); >> + assert(clocks); >=20 > More unnecessary asserts, I think. >=20 >=20 >=20 >> +/** >> + * ClockInitElem: >> + * @name: name of the clock (can't be NULL) >> + * @is_output: indicates whether the clock is input or output >> + * @callback: for inputs, optional callback to be called on clock's u= pdate >> + * with device as opaque >> + * @offset: optional offset to store the ClockIn or ClockOut pointer = in device >> + * state structure (0 means unused) >> + */ >> +struct ClockPortInitElem { >> + const char *name; >> + bool is_output; >> + ClockCallback *callback; >> + size_t offset; >> +}; >> + >> +#define clock_offset_value(_type, _devstate, _field) \ >> + (offsetof(_devstate, _field) + \ >> + type_check(_type *, typeof_field(_devstate, _field))) >=20 > Avoid leading underscores, please. >=20 >> + >> +#define QDEV_CLOCK(_is_output, _type, _devstate, _field, _callback) {= \ >> + .name =3D (stringify(_field)), \ >> + .is_output =3D _is_output, \ >> + .callback =3D _callback, \ >> + .offset =3D clock_offset_value(_type, _devstate, _field), \ >> +} >> + >> +/** >> + * QDEV_CLOCK_(IN|OUT): >> + * @_devstate: structure type. @dev argument of qdev_init_clocks belo= w must be >> + * a pointer to that same type. >=20 > It's a bit unclear what "below" here is referring to. Maybe > just have this be "@devstate: name of a C struct type" > and then explain below... >=20 >> + * @_field: a field in @_devstate (must be ClockIn* or ClockOut*) >> + * @_callback: (for input only) callback (or NULL) to be called with = the device >> + * state as argument >> + * >=20 > ...here, where we can have a paragraph giving the purpose > of the macro: >=20 > "Define an entry in a ClockPortInitArray which is intended > to be passed to qdev_init_clocks(), which should be called > with an @dev argument which is a pointer to the @devstate > struct type." Sounds good. >=20 >> + * The name of the clock will be derived from @_field >=20 > Derived how? Guessing from the stringify(_field) above that it > will be the same as the field name ? yes. >=20 > It makes sense to hardcode the opaque pointer for the callback to be > the device pointer. >=20 >=20 >> + */ >> +#define QDEV_CLOCK_IN(_devstate, _field, _callback) \ >> + QDEV_CLOCK(false, ClockIn, _devstate, _field, _callback) >> + >> +#define QDEV_CLOCK_OUT(_devstate, _field) \ >> + QDEV_CLOCK(true, ClockOut, _devstate, _field, NULL) >> + >> +/** >> + * QDEV_CLOCK_IN_NOFIELD: >> + * @_name: name of the clock >> + * @_callback: callback (or NULL) to be called with the device state = as argument >> + */ >> +#define QDEV_CLOCK_IN_NOFIELD(_name, _callback) { \ >> + .name =3D _name, \ >> + .is_output =3D false, \ >> + .callback =3D _callback, \ >> + .offset =3D 0, \ >> +} >=20 > When would we want to use this one ? If the callback interaction is enough, we don't need to access the clock object directly. So we don't need the field in the device state structure. I can remove this macro for sake of simplicity. -- Damien From MAILER-DAEMON Wed Dec 04 06:58:57 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1icTJ3-0006qW-Po for mharc-qemu-arm@gnu.org; Wed, 04 Dec 2019 06:58:57 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:47415) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1icTIx-0006n5-Tb for qemu-arm@nongnu.org; Wed, 04 Dec 2019 06:58:54 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1icTIr-00034k-WE for qemu-arm@nongnu.org; Wed, 04 Dec 2019 06:58:48 -0500 Received: from beetle.greensocs.com ([5.135.226.135]:45762) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1icTIr-0002iI-Cu; Wed, 04 Dec 2019 06:58:45 -0500 Received: from [172.16.11.102] (crumble.bar.greensocs.com [172.16.11.102]) by beetle.greensocs.com (Postfix) with ESMTPSA id A95F296EF0; Wed, 4 Dec 2019 11:58:41 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=greensocs.com; s=mail; t=1575460722; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=8ljSCwCD3O4e7pPsXT+MroUcr3135nqWethx1Gpbjuk=; b=ME8n+R4fLmX9fusvWwUBqlaHbU3t6uMxB4GWpYle5KmMmGxA3gWLNDe80yNw25b5GePgrm SCWxuwA6suJbg5CMUpzBDG3TxTtVuj/V2iRpMKlXHdY24V0TTlItUW/90NOJ993Zw5Pdfg hAYBtQuwtisRqbayMzldysn7j8WXl18= Subject: Re: [PATCH v6 3/9] qdev: add clock input&output support to devices. To: =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= , Peter Maydell Cc: QEMU Developers , Mark Burton , "Edgar E. Iglesias" , Alistair Francis , =?UTF-8?Q?Marc-Andr=c3=a9_Lureau?= , Paolo Bonzini , "Daniel P. Berrange" , Eduardo Habkost , qemu-arm References: <20190904125531.27545-1-damien.hedde@greensocs.com> <20190904125531.27545-4-damien.hedde@greensocs.com> <8ac54ca8-4acf-5145-9ead-6791a5181617@greensocs.com> From: Damien Hedde Message-ID: Date: Wed, 4 Dec 2019 12:58:41 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.2.0 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=utf-8 Content-Language: en-US-large ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=greensocs.com; s=mail; t=1575460722; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=8ljSCwCD3O4e7pPsXT+MroUcr3135nqWethx1Gpbjuk=; b=kMohnrxOSGi/bc2DJWVZPeVkXKu0dPgbRlmc2HIz42+9hLjxiPb2sKVuLevJQVVyDeTbSq XMrUZxavi+77oRokysQqiSD/egPitKW2O9/Uw2+/S7y56jV88TacJQ+EIuWZ4tK+BnCv/I xyDANj8WMWukbFxLN16t7LSjXI7LeTY= ARC-Seal: i=1; s=mail; d=greensocs.com; t=1575460722; a=rsa-sha256; cv=none; b=4jjL4V+OVqzIQM1lGRM833Vyrn2OZM1Expn5PvC3c1PT+VafVskD/PbWfHgNspsHeBi/+j 2iOHgwS4U60Mp/2o1SSot5u+I182q5r76STPd2V202inWZx4Rn3ZQC7BtWCnmD4m2oq/oF yvU4RLtGEwvBv3F4PQW+ZPhDozP78wE= ARC-Authentication-Results: i=1; ORIGINATING; auth=pass smtp.auth=damien smtp.mailfrom=damien.hedde@greensocs.com Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 5.135.226.135 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 04 Dec 2019 11:58:55 -0000 On 12/4/19 10:53 AM, Philippe Mathieu-Daud=C3=A9 wrote: > On 12/4/19 10:05 AM, Damien Hedde wrote: >> On 12/2/19 3:34 PM, Peter Maydell wrote: >>> On Wed, 4 Sep 2019 at 13:56, Damien Hedde >>> wrote: >>>> > [...] >>>> +/** >>>> + * qdev_pass_clock: >>>> + * @dev: the device to forward the clock to >>>> + * @name: the name of the clock to be added (can't be NULL) >>>> + * @container: the device which already has the clock >>>> + * @cont_name: the name of the clock in the container device >>>> + * >>>> + * Add a clock @name to @dev which forward to the clock @cont_name >>>> in @container >>>> + */ >>> >>> 'container' seems odd terminology here, because I would expect >>> the usual use of this function to be when a 'container' object >>> like an SoC wants to forward a clock to one of its components; >>> in that case the 'container' SoC would be @dev, wouldn't it? >> >> Yes. I agree it is confusing. >> This function just allow a a device 'A' to exhibit a clock from anothe= r >> device 'B' (typically a composing sub-device, inside a soc like you >> said). The device A is not supposed to interact with the clock itself. >> The original sub-device is the true >> owner/controller of the clock and is the only one which should use the >> clock API: setting a callback on it (input clock); or updating the clo= ck >> frequency (output clock). >> Basically, it just add the clock into the device clock namespace witho= ut >> interfering with it. >> >>> We should get this to be the same way round as qdev_pass_gpios(), >>> which takes "DeviceState *dev, DeviceState *container", and >>> passes the gpios that exist on 'dev' over to 'container' so that >>> 'container' now has gpios which it did not before. >> >> Ok, I'll invert the arguments. >> >>> >>> Also, your use of 'forward to' is inconsistent: in the 'dev' >>> documentation you say we're forwarding the clock to 'dev', >>> but in the body of the documentation you say we're forwarding >>> the clock to the clock in 'container'. >> >> I'll try to clarify this and make the documentation more consistent wi= th >> the comments here. >> >>> >>> I think the way to resolve this is to stick to the terminology >>> in the function name itself: >>> =C2=A0 @dev: the device which has the clock >>> =C2=A0 @name: the name of the clock on @dev >>> =C2=A0 @container: the name of the device which the clock should >>> =C2=A0=C2=A0 be passed to >>> =C2=A0 @cont_name: the name to use for the clock on @container >> >> I think container is confusing because depending on how we reason (clo= ck >> in a device; device in another device), we end up thinking the opposit= e. >> >> Maybe we can use "exhibit" instead of "container" in the 2nd pair of >> parameters, or prefix use "origin" or "owner" as a prefix for the firs= t >> pair of parameters. >=20 > @sink vs @source? >=20 >>> Q: if you pass a clock to another device with this function, >>> does it still exist to be used directly on the original >>> device? For qdev_pass_gpios it does not (I think), but >>> this is more accident of implementation than anything else. >> >> It depends what we mean by "used by". >> Original device can: >> + set the callback in case it is an input >> + update the frequency in case it is an output >=20 > Hmm here you use @input vs @output... Not really. What I meant here is that the device which originally creates the clock is the only device which can interact with the clock. And it will never gives this right to another device even if qdev_pass_clock() is used. There are 2 interactions, depending on the clock direction (input or output). If it is an input clock, it can register a callback on frequency changes; and if it is an output clock, it can updates the frequency of the clock. >=20 >> But since an input clock can only be connected once, >> I think the logic here is that any connection should now go through th= e >> new device. But this is not checked and using one or the other is >> exactly the same. >> >> Maybe I misunderstood the meaning of qdev_pass_gpios(). > [...] >=20 From MAILER-DAEMON Wed Dec 04 07:11:55 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1icTVb-0004WL-5j for mharc-qemu-arm@gnu.org; Wed, 04 Dec 2019 07:11:55 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:49916) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1icTVX-0004TK-Lw for qemu-arm@nongnu.org; Wed, 04 Dec 2019 07:11:52 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1icTVV-0002AQ-70 for qemu-arm@nongnu.org; Wed, 04 Dec 2019 07:11:50 -0500 Received: from beetle.greensocs.com ([5.135.226.135]:46166) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1icTVU-0001kY-LP; Wed, 04 Dec 2019 07:11:49 -0500 Received: from [172.16.11.102] (crumble.bar.greensocs.com [172.16.11.102]) by beetle.greensocs.com (Postfix) with ESMTPSA id 05BAF96EF0; Wed, 4 Dec 2019 12:11:43 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=greensocs.com; s=mail; t=1575461504; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=TaurbfOKuOcfUaP1AMMQnTq3LAvy/GF5omcI4wFBMHA=; b=RRh5qfR9TkykdbQBNF5BrwkB5Zn6pbAjlGt0vQEkdZJSt1YX7YFxUHAn+xSTY4tvzqwwS+ aPVyaeiXCvE4/55lhA6J8RBb4wnqnuhNsU7fFnWvOafuhrGCWtXmmFSRBuYeZf7VZ762ot ysbL7+sVv6wjHSN4j1UJK2tDVZsTOs0= Subject: Re: [PATCH v6 6/9] docs/clocks: add device's clock documentation To: Peter Maydell Cc: QEMU Developers , Mark Burton , "Edgar E. Iglesias" , Alistair Francis , =?UTF-8?Q?Marc-Andr=c3=a9_Lureau?= , Paolo Bonzini , "Daniel P. Berrange" , Eduardo Habkost , qemu-arm , =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= References: <20190904125531.27545-1-damien.hedde@greensocs.com> <20190904125531.27545-7-damien.hedde@greensocs.com> From: Damien Hedde Message-ID: <9a460a48-250f-eb70-f2cd-bbc9624963b1@greensocs.com> Date: Wed, 4 Dec 2019 13:11:42 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.2.0 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=utf-8 Content-Language: en-US-large Content-Transfer-Encoding: 7bit ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=greensocs.com; s=mail; t=1575461504; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=TaurbfOKuOcfUaP1AMMQnTq3LAvy/GF5omcI4wFBMHA=; b=yOiKSflFcV8ysr1i64O5apL2lQ7AfpgP6u6IJehGC+wbvPMnuPdXr8i5k8wFJChxb7yZwv 9Da4UxHDpU58v73F2rhW4uAR0EPcGo/DzdcsUG4oSoxMI4Z5MH0OLbFNmQGqHt7Jy3x4+/ JmGV34Z42jrRLtyFk1kn/7bV/cdOtrY= ARC-Seal: i=1; s=mail; d=greensocs.com; t=1575461504; a=rsa-sha256; cv=none; b=jxaYQJd2zVG4nWG7KgI5GAO9a3ly5rTRUjxj/naUxXX87iPkXYAwnH1zxrFyW3tfjR84ll NOXHImHWT6h80cyco6ePcTjfa3j1c57snuSolbdJoywxmhK57jlPfbQHOvYZwkSplX4Dj4 5FUH4zgvSDCcbbSvPCG1JmBA8eemLyk= ARC-Authentication-Results: i=1; ORIGINATING; auth=pass smtp.auth=damien smtp.mailfrom=damien.hedde@greensocs.com X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 5.135.226.135 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 04 Dec 2019 12:11:53 -0000 On 12/2/19 4:17 PM, Peter Maydell wrote: > On Wed, 4 Sep 2019 at 13:56, Damien Hedde wrote: >> >> Add the documentation about the clock inputs and outputs in devices. >> >> This is based on the original work of Frederic Konrad. >> >> Signed-off-by: Damien Hedde >> --- >> docs/devel/clock.txt | 246 +++++++++++++++++++++++++++++++++++++++++++ >> 1 file changed, 246 insertions(+) >> create mode 100644 docs/devel/clock.txt > > Could you convert this to rst format, please?Yes. > > > >> +Changing a clock output >> +======================= >> + >> +A device can change its outputs using the clock_set_frequency function. It >> +will trigger updates on every connected inputs. > > "input" > >> + >> +For example, let's say that we have an output clock "clkout" and we have a >> +pointer to it in the device state because we did the following in init phase: >> +dev->clkout = qdev_init_clock_out(DEVICE(dev), "clkout"); >> + >> +Then at any time (apart from the cases listed below), it is possible to >> +change the clock value by doing: >> +clock_set_frequency(dev->clkout, 1000 * 1000 * 1000); /* 1Ghz */ >> +This operation must be done while holding the qemu io lock. >> + >> +One can change clocks only when it is allowed to have side effects on other >> +objects. In consequence, it is forbidden: >> ++ during migration, >> ++ and in the init phase of reset. >> + >> +Forwarding clocks >> +================= >> + >> +Sometimes, one needs to forward, or inherit, a clock from another device. >> +Typically, when doing device composition, a device might expose a sub-device's >> +clock without interfering with it. >> +The function qdev_pass_clock() can be used to achieve this behaviour. Note, that > > "Note that" > >> +it is possible to expose the clock under a different name. This works for both >> +inputs or outputs. > > "inputs and outputs" > > >> +Migration >> +========= >> + >> +Only the ClockIn object has a state. ClockOut is not concerned by migration. > > "has any state". > > "ClockOut has no state and does not need special handling for migration." > >> + >> +In case the frequency of in input clock is needed for a device's migration, >> +this state must be migrated. > > Are you trying to say that if an input clock is known to be a > fixed frequency we don't need to migrate anything? I wonder > if we need to worry about that or if we could/should just say that > input clocks should always be migrated. What I wanted to say is that there are indeed probably cases where migrating the frequency is unnecessary. For example if we only use the callback and never fetch the frequency outside it: if the frequency is only used to compute something which is already saved/loaded during migration. But yes we could just do as you say. It's probably less confusing. > >> The VMSTATE_CLOCKIN macro defines an entry to >> +be added in a vmstate description. >> + >> +For example, if a device has a clock input and the device state looks like: >> +MyDeviceState { >> + DeviceState parent_obj; >> + ClockIn *clk; >> +}; >> + >> +Then, to add the clock frequency to the device's migrated state, the vmstate >> +description is: >> +VMStateDescription my_device_vmstate = { >> + .name = "my_device", >> + .fields = (VMStateField[]) { >> + VMSTATE_CLOCKIN(clk, MyDeviceState), >> + VMSTATE_END_OF_LIST() >> + } >> +}; >> + >> +When adding a input clock support to an existing device, you must care about >> +migration compatibility. To this end, you can use the clock_init_frequency in >> +a pre_load function to setup a default value in case the source vm does not >> +migrate the frequency. > > thanks > -- PMM > From MAILER-DAEMON Wed Dec 04 07:51:52 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1icU8G-0003BT-N6 for mharc-qemu-arm@gnu.org; Wed, 04 Dec 2019 07:51:52 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:55678) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1icU8E-0003B9-1g for qemu-arm@nongnu.org; Wed, 04 Dec 2019 07:51:51 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1icU8C-0006jD-E7 for qemu-arm@nongnu.org; Wed, 04 Dec 2019 07:51:49 -0500 Received: from beetle.greensocs.com ([5.135.226.135]:47514) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1icU8B-0006ih-Rz; Wed, 04 Dec 2019 07:51:48 -0500 Received: from [172.16.11.102] (crumble.bar.greensocs.com [172.16.11.102]) by beetle.greensocs.com (Postfix) with ESMTPSA id 0800496EF0; Wed, 4 Dec 2019 12:51:44 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=greensocs.com; s=mail; t=1575463905; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=OBFgRgY4wIEhLoMAYwc94hmZaFaQBM/mMjjINIFJ5ZI=; b=fIcbZZK/GP3axF2KOd6gSzFzLkmwVdlQPTY13wtdOQUQ1tdvRqstqQGdCW7x5On5l2PPwb ZJu1Onc9esznT+CnUPhLaalnkUlwcCW7QxHhRq1CLBihRfz0zRaIeoSrUapbI5SalatM+H v3aAJoi4nGSIwKR38ilekoGMg7KjqU8= Subject: Re: [PATCH v6 7/9] hw/misc/zynq_slcr: add clock generation for uarts To: Peter Maydell Cc: QEMU Developers , Mark Burton , "Edgar E. Iglesias" , Alistair Francis , =?UTF-8?Q?Marc-Andr=c3=a9_Lureau?= , Paolo Bonzini , "Daniel P. Berrange" , Eduardo Habkost , qemu-arm , =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= References: <20190904125531.27545-1-damien.hedde@greensocs.com> <20190904125531.27545-8-damien.hedde@greensocs.com> From: Damien Hedde Message-ID: <7e255f65-bbfa-897a-4dd0-cb366886f32c@greensocs.com> Date: Wed, 4 Dec 2019 13:51:44 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.2.0 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=utf-8 Content-Language: en-US-large Content-Transfer-Encoding: 7bit ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=greensocs.com; s=mail; t=1575463905; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=OBFgRgY4wIEhLoMAYwc94hmZaFaQBM/mMjjINIFJ5ZI=; b=3N5xzz1AsIzwskbc4d4tQ8te3WGoJ42BR7F2ZfcXncEENAfIok9ANzMCuKZUHDh/6nx8GN UwWO9QL7kBr16K48vzIjPWmFAdDExAO2MXWiy6G+xAYdCEFsTVho5X3zT2EIC4rYhnS2f3 HQrkGZs2VSsIXDrPE6YVJL7Iteg14SQ= ARC-Seal: i=1; s=mail; d=greensocs.com; t=1575463905; a=rsa-sha256; cv=none; b=7jh+YjDZfbgf5tQMfwe6bqIXCKyuv8k1OZdQL8g8W6rFUvmQZNSeTJxSyGIKhE03Xgn3wt M0McP9y3PXyBF66cv9Ac9a2KrrmSYFDwCMeIYucA5YqB6N7Ktm2A5Jcsl83MSo1rKMLYJm Jwk30WQ2Aj8FXnOg6oAxazaXZNjifaY= ARC-Authentication-Results: i=1; ORIGINATING; auth=pass smtp.auth=damien smtp.mailfrom=damien.hedde@greensocs.com X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 5.135.226.135 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 04 Dec 2019 12:51:51 -0000 On 12/2/19 4:20 PM, Peter Maydell wrote: > On Wed, 4 Sep 2019 at 13:56, Damien Hedde wrote: >> >> Switch the slcr to multi-phase reset and add some clocks: >> + the main input clock (ps_clk) >> + the reference clock outputs for each uart (uart0 & 1) >> >> The clock frequencies are computed using the internal pll & uart configuration >> registers and the ps_clk frequency. >> >> Signed-off-by: Damien Hedde > > Review of this and the following two patches by some Xilinx > person would be nice. I've just looked them over for general > issues, and haven't checked against the hardware specs. > >> --- > > >> +/* >> + * return the output frequency of a clock given: >> + * + the frequencies in an array corresponding to mux's indexes >> + * + the register xxx_CLK_CTRL value >> + * + enable bit index in ctrl register >> + * >> + * This function make the assumption that ctrl_reg value is organized as follow: > > "makes"; "that the"; "follows" > >> + * + bits[13:8] clock divisor >> + * + bits[5:4] clock mux selector (index in array) >> + * + bits[index] clock enable >> + */ >> +static uint64_t zynq_slcr_compute_clock(const uint64_t mux[], >> + uint32_t ctrl_reg, >> + unsigned index) >> +{ >> + uint32_t srcsel = extract32(ctrl_reg, 4, 2); /* bits [5:4] */ >> + uint32_t divisor = extract32(ctrl_reg, 8, 6); /* bits [13:8] */ >> + >> + /* first, check if clock is enabled */ >> + if (((ctrl_reg >> index) & 1u) == 0) { >> + return 0; >> + } >> + >> + /* >> + * according to the Zynq technical ref. manual UG585 v1.12.2 in >> + * "Clocks" chapter, section 25.10.1 page 705" the range of the divisor >> + * is [1;63]. > > Is this the range notation the spec doc uses? The exact terms is: "The 6-bit divider provides a divide range of 1 to 63" At the time, I checked also the kernel sources, and this is the behavior implemented in the driver as well (1 based timer and allowing 0 special value for bypass). The bypass is undocumented as far as I can tell. > >> + * So divide the source while avoiding division-by-zero. >> + */ >> + return mux[srcsel] / (divisor ? divisor : 1u); >> +} >> + > >> +static const ClockPortInitArray zynq_slcr_clocks = { >> + QDEV_CLOCK_IN(ZynqSLCRState, ps_clk, zynq_slcr_ps_clk_callback), >> + QDEV_CLOCK_OUT(ZynqSLCRState, uart0_ref_clk), >> + QDEV_CLOCK_OUT(ZynqSLCRState, uart1_ref_clk), >> + QDEV_CLOCK_END >> +}; >> + >> static void zynq_slcr_init(Object *obj) >> { >> ZynqSLCRState *s = ZYNQ_SLCR(obj); >> @@ -425,6 +559,8 @@ static void zynq_slcr_init(Object *obj) >> memory_region_init_io(&s->iomem, obj, &slcr_ops, s, "slcr", >> ZYNQ_SLCR_MMIO_SIZE); >> sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->iomem); >> + >> + qdev_init_clocks(DEVICE(obj), zynq_slcr_clocks); >> } >> >> static const VMStateDescription vmstate_zynq_slcr = { >> @@ -440,9 +576,12 @@ static const VMStateDescription vmstate_zynq_slcr = { >> static void zynq_slcr_class_init(ObjectClass *klass, void *data) >> { >> DeviceClass *dc = DEVICE_CLASS(klass); >> + ResettableClass *rc = RESETTABLE_CLASS(klass); >> >> dc->vmsd = &vmstate_zynq_slcr; >> - dc->reset = zynq_slcr_reset; >> + rc->phases.init = zynq_slcr_reset_init; >> + rc->phases.hold = zynq_slcr_reset_hold; >> + rc->phases.exit = zynq_slcr_reset_exit; >> } > > We're adding an input clock, so doesn't the migration > state struct need to be updated to migrate it ? Yes, we can. Although this input clock is really not expected to change. > > thanks > -- PMM > From MAILER-DAEMON Wed Dec 04 08:35:48 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1icUom-0002so-Dc for mharc-qemu-arm@gnu.org; Wed, 04 Dec 2019 08:35:48 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:33365) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1icUoi-0002sf-7G for qemu-arm@nongnu.org; Wed, 04 Dec 2019 08:35:47 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1icUog-0005mI-Uv for qemu-arm@nongnu.org; Wed, 04 Dec 2019 08:35:43 -0500 Received: from beetle.greensocs.com ([5.135.226.135]:48770) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1icUog-0005lx-Be; Wed, 04 Dec 2019 08:35:42 -0500 Received: from [172.16.11.102] (crumble.bar.greensocs.com [172.16.11.102]) by beetle.greensocs.com (Postfix) with ESMTPSA id A2AEA96EF0; Wed, 4 Dec 2019 13:35:39 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=greensocs.com; s=mail; t=1575466540; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=lfOQ/XuakjnWsNeoSdUr3UbRkZAPKweMNeEUHV4Xnuw=; b=FsPwH7tUIlPN+HEcjUAFkh6QI5D5MxlR5GSZf71wEkbnloI2SWr1EcTtiGDazvuvDHSv1e kZkzJtDEolHMEDmv/7f7WiNmiRy9LKFAHXO14fuQ/+9l0J/lPuHgvfFK8QAU0968EQfxzA 8FYZMLgPqklsa1uwF08ooTC3t63VdG4= Subject: Re: [PATCH v6 8/9] hw/char/cadence_uart: add clock support To: Peter Maydell Cc: QEMU Developers , Mark Burton , "Edgar E. Iglesias" , Alistair Francis , =?UTF-8?Q?Marc-Andr=c3=a9_Lureau?= , Paolo Bonzini , "Daniel P. Berrange" , Eduardo Habkost , qemu-arm , =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= References: <20190904125531.27545-1-damien.hedde@greensocs.com> <20190904125531.27545-9-damien.hedde@greensocs.com> From: Damien Hedde Message-ID: <75c38376-bbe9-1c52-d7a5-cc3aa73cbac2@greensocs.com> Date: Wed, 4 Dec 2019 14:35:39 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.2.0 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=utf-8 Content-Language: en-US-large Content-Transfer-Encoding: 7bit ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=greensocs.com; s=mail; t=1575466540; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=lfOQ/XuakjnWsNeoSdUr3UbRkZAPKweMNeEUHV4Xnuw=; b=ZscCWZk7LlsX8kd02cRVKUwB1nMABjLhOmUc1PXXfZbZnq2OypHT4t49Wh2r3GkhDeJRgY Z9qV0aUv76SUzD51IgtrM6Wdr18gD74B0d0/8wUWiVNTwVFZ4zOBhVaTou6VI3ndT8W4Do 1Wr4V7PgTq5x/uPcfOlchRN/7HFpxIs= ARC-Seal: i=1; s=mail; d=greensocs.com; t=1575466540; a=rsa-sha256; cv=none; b=7hg/tmCb64KH5gTd7e1YfQlpOb0Kta8faJfKWjxmQq96wCOQ6V8Qme84h/PY0hjkgS74wz NKc4vsbiipK9Ic/5rhp42A6MQZK4/KhznzfS1GaMlCLz2lrqSbVJcr1li1Q/kSQCGg5R8S zmddbVnXlKnDB1jJSn8AGOzdsAg+C+k= ARC-Authentication-Results: i=1; ORIGINATING; auth=pass smtp.auth=damien smtp.mailfrom=damien.hedde@greensocs.com X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 5.135.226.135 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 04 Dec 2019 13:35:47 -0000 On 12/2/19 4:24 PM, Peter Maydell wrote: > On Wed, 4 Sep 2019 at 13:56, Damien Hedde wrote: >> >> Switch the cadence uart to multi-phase reset and add the >> reference clock input. >> >> The input clock frequency is added to the migration structure. >> >> The reference clock controls the baudrate generation. If it disabled, >> any input characters and events are ignored. >> >> If this clock remains unconnected, the uart behaves as before >> (it default to a 50MHz ref clock). >> >> Signed-off-by: Damien Hedde > >> static void uart_parameters_setup(CadenceUARTState *s) >> { >> QEMUSerialSetParams ssp; >> - unsigned int baud_rate, packet_size; >> + unsigned int baud_rate, packet_size, input_clk; >> + input_clk = clock_get_frequency(s->refclk); >> >> - baud_rate = (s->r[R_MR] & UART_MR_CLKS) ? >> - UART_INPUT_CLK / 8 : UART_INPUT_CLK; >> + baud_rate = (s->r[R_MR] & UART_MR_CLKS) ? input_clk / 8 : input_clk; >> + baud_rate /= (s->r[R_BRGR] * (s->r[R_BDIV] + 1)); >> + trace_cadence_uart_baudrate(baud_rate); >> + >> + ssp.speed = baud_rate; >> >> - ssp.speed = baud_rate / (s->r[R_BRGR] * (s->r[R_BDIV] + 1)); >> packet_size = 1; >> >> switch (s->r[R_MR] & UART_MR_PAR) { >> @@ -215,6 +220,13 @@ static void uart_parameters_setup(CadenceUARTState *s) >> } >> >> packet_size += ssp.data_bits + ssp.stop_bits; >> + if (ssp.speed == 0) { >> + /* >> + * Avoid division-by-zero below. >> + * TODO: find something better >> + */ > > Any ideas what might be better? :-) Well maybe the comment is misplaced. Because it is probably a good thing to round up the ssp.speed in case it becomes 0 (which is very unlikely apart from the case where the input clock is 0/disabled). The problem is what should we do when the clock is disabled ? Right now we: + set a minimal baudrate + ignore input characters/events + still forward output characters... (I just checked) I suppose we could at least fix the last point: we can drop any output characters. But if this happen, there is definitely a problem somewhere (a firmware should not try to send characters to an unclocked uart). Is there a qemu way of reporting this kind of situation ? It would be best to somehow tell the backend we're not handling anything anymore. So I could put that in the comment instead. I really don't know if/how we can do that. When I looked I did not see any way to do the opposite of qemu_chr_fe_accept_input() which is done to start receiving stuff. -- Damien From MAILER-DAEMON Wed Dec 04 08:56:25 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1icV8j-000577-GA for mharc-qemu-arm@gnu.org; Wed, 04 Dec 2019 08:56:25 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:38363) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1icV8g-00056w-VI for qemu-arm@nongnu.org; Wed, 04 Dec 2019 08:56:24 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1icV8f-00059n-Ss for qemu-arm@nongnu.org; Wed, 04 Dec 2019 08:56:22 -0500 Received: from smtp-fw-6001.amazon.com ([52.95.48.154]:42197) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1icV8f-00058h-N0; Wed, 04 Dec 2019 08:56:21 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amazon.de; i=@amazon.de; q=dns/txt; s=amazon201209; t=1575467782; x=1607003782; h=from:to:cc:subject:date:message-id:in-reply-to: references; bh=qj63OZvgUd2blMa1aPgiv5NYnxSXE+CuB5YhjLWxvAQ=; b=TJAKTEAf9mBVF6OR39gakACdYNs24NTz0lAPMf6D0rVo0oIG+hd++2qf KuITrx/F/AVCuQH8WFv35c1ISiTFr7Hgo8ywZliCWOEvbSYcSmK9oUiwi BTWOPXwG2gn3wXiaAIBayUjjmdyfPc437IIgLihMQtgkyA8R1u20y0NGd w=; IronPort-SDR: 9XWlbc6AWrPk3Sj3AkLAH72XL5hyTn7zSX2aKM1OSxlEtUk5upywo/vxwyze+8OM3TAF/7Xmah 3NCeQZ6lGfYQ== X-IronPort-AV: E=Sophos;i="5.69,277,1571702400"; d="scan'208";a="7621879" Received: from iad6-co-svc-p1-lb1-vlan3.amazon.com (HELO email-inbound-relay-2a-1c1b5cdd.us-west-2.amazon.com) ([10.124.125.6]) by smtp-border-fw-out-6001.iad6.amazon.com with ESMTP; 04 Dec 2019 13:56:19 +0000 Received: from sveith-desktop.aka.corp.amazon.com (pdx2-ws-svc-lb17-vlan3.amazon.com [10.247.140.70]) by email-inbound-relay-2a-1c1b5cdd.us-west-2.amazon.com (Postfix) with ESMTPS id 09EB5A1DCA; Wed, 4 Dec 2019 13:56:17 +0000 (UTC) Received: from sveith-desktop.aka.corp.amazon.com (localhost [127.0.0.1]) by sveith-desktop.aka.corp.amazon.com (8.15.2/8.15.2/Debian-3) with ESMTP id xB4DuG4i029360; Wed, 4 Dec 2019 14:56:16 +0100 Received: (from sveith@localhost) by sveith-desktop.aka.corp.amazon.com (8.15.2/8.15.2/Submit) id xB4DuG1e029358; Wed, 4 Dec 2019 14:56:16 +0100 From: Simon Veith To: qemu-devel@nongnu.org, qemu-arm@nongnu.org Cc: Simon Veith , Eric Auger Subject: [PATCH 1/5] hw/arm/smmuv3: Apply address mask to linear strtab base address Date: Wed, 4 Dec 2019 14:55:44 +0100 Message-Id: <1575467748-28898-2-git-send-email-sveith@amazon.de> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1575467748-28898-1-git-send-email-sveith@amazon.de> References: <1575467748-28898-1-git-send-email-sveith@amazon.de> Precedence: Bulk X-detected-operating-system: by eggs.gnu.org: FreeBSD 9.x [fuzzy] X-Received-From: 52.95.48.154 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 04 Dec 2019 13:56:24 -0000 In the SMMU_STRTAB_BASE register, the stream table base address only occupies bits [51:6]. Other bits, such as RA (bit [62]), must be masked out to obtain the base address. The branch for 2-level stream tables correctly applies this mask by way of SMMU_BASE_ADDR_MASK, but the one for linear stream tables does not. Apply the missing mask in that case as well so that the correct stream base address is used by guests which configure a linear stream table. Linux guests are unaffected by this change because they choose a 2-level stream table layout for the QEMU SMMUv3, based on the size of its stream ID space. ref. ARM IHI 0070C, section 6.3.23. Signed-off-by: Simon Veith Cc: Eric Auger Cc: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org --- hw/arm/smmuv3.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c index e2fbb83..eef9a18 100644 --- a/hw/arm/smmuv3.c +++ b/hw/arm/smmuv3.c @@ -429,7 +429,7 @@ static int smmu_find_ste(SMMUv3State *s, uint32_t sid, STE *ste, } addr = l2ptr + l2_ste_offset * sizeof(*ste); } else { - addr = s->strtab_base + sid * sizeof(*ste); + addr = (s->strtab_base & SMMU_BASE_ADDR_MASK) + sid * sizeof(*ste); } if (smmu_get_ste(s, addr, ste, event)) { -- 2.7.4 From MAILER-DAEMON Wed Dec 04 08:56:28 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1icV8l-0005Ag-TA for mharc-qemu-arm@gnu.org; Wed, 04 Dec 2019 08:56:27 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:38398) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1icV8j-000578-Dp for qemu-arm@nongnu.org; Wed, 04 Dec 2019 08:56:26 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1icV8i-0005DD-92 for qemu-arm@nongnu.org; Wed, 04 Dec 2019 08:56:25 -0500 Received: from smtp-fw-9101.amazon.com ([207.171.184.25]:9490) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1icV8i-0005BH-2F; Wed, 04 Dec 2019 08:56:24 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amazon.de; i=@amazon.de; q=dns/txt; s=amazon201209; t=1575467784; x=1607003784; h=from:to:cc:subject:date:message-id; bh=amRmOZ81ssXzZqOVsDMBobbUW7BTTADIGSXfhNanSq8=; b=AgcBFSXrH15UHCFncEIWqeTYwSd8VKm73tGjm4FFarhcFIXaAojjEaKP QCH97zxXsXvrnrnPEyePD7a0W7Qx+qDsXPWGlpEhDJEOVsFH/ARVpmN76 e/A18NNhTTQ3k46nQ7PcolqFz/ZgjpQOJYSnMf3SPKA/3p2fQCN1xBAhy Q=; IronPort-SDR: yUaUEAX32SYqXk8ZjOlm+6F+BYcvUIP+QNVXs80cyWQWILsbhPkduqaBOJQeL+KN/s7WL/0Wpb +CHvJ2bEC2Ag== X-IronPort-AV: E=Sophos;i="5.69,277,1571702400"; d="scan'208";a="3177649" Received: from sea32-co-svc-lb4-vlan3.sea.corp.amazon.com (HELO email-inbound-relay-2a-e7be2041.us-west-2.amazon.com) ([10.47.23.38]) by smtp-border-fw-out-9101.sea19.amazon.com with ESMTP; 04 Dec 2019 13:56:12 +0000 Received: from sveith-desktop.aka.corp.amazon.com (pdx2-ws-svc-lb17-vlan3.amazon.com [10.247.140.70]) by email-inbound-relay-2a-e7be2041.us-west-2.amazon.com (Postfix) with ESMTPS id E7A91A21B0; Wed, 4 Dec 2019 13:56:11 +0000 (UTC) Received: from sveith-desktop.aka.corp.amazon.com (localhost [127.0.0.1]) by sveith-desktop.aka.corp.amazon.com (8.15.2/8.15.2/Debian-3) with ESMTP id xB4DuAqV029090; Wed, 4 Dec 2019 14:56:10 +0100 Received: (from sveith@localhost) by sveith-desktop.aka.corp.amazon.com (8.15.2/8.15.2/Submit) id xB4DuAC3029089; Wed, 4 Dec 2019 14:56:10 +0100 From: Simon Veith To: qemu-devel@nongnu.org, qemu-arm@nongnu.org Cc: Simon Veith Subject: [PATCH 0/5] hw/arm/smmuv3: Correct stream ID and event address handling Date: Wed, 4 Dec 2019 14:55:43 +0100 Message-Id: <1575467748-28898-1-git-send-email-sveith@amazon.de> X-Mailer: git-send-email 2.7.4 Precedence: Bulk X-detected-operating-system: by eggs.gnu.org: FreeBSD 9.x [fuzzy] X-Received-From: 207.171.184.25 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 04 Dec 2019 13:56:26 -0000 While working on the Linux SMMUv3 driver, I noticed a few cases where the QEMU SMMUv3 behavior relating to stream tables was inconsistent with our hardware. Also, when debugging those differences, I found that the errors reported through the QEMU SMMUv3 event queue contained the address fields in an incorrect position. These patches correct the QEMU SMMUv3 behavior to match the specification (and the behavior that I observed in our hardware). Linux guests normally will not notice these issues, but other SMMUv3 driver implementations might. Simon Veith (5): hw/arm/smmuv3: Apply address mask to linear strtab base address hw/arm/smmuv3: Check stream IDs against actual table LOG2SIZE hw/arm/smmuv3: Align stream table base address to table size hw/arm/smmuv3: Use correct bit positions in EVT_SET_ADDR2 macro hw/arm/smmuv3: Report F_STE_FETCH fault address in correct word position hw/arm/smmuv3-internal.h | 4 ++-- hw/arm/smmuv3.c | 39 ++++++++++++++++++++++++++++++++------- 2 files changed, 34 insertions(+), 9 deletions(-) -- 2.7.4 From MAILER-DAEMON Wed Dec 04 08:56:30 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1icV8o-0005EZ-2V for mharc-qemu-arm@gnu.org; Wed, 04 Dec 2019 08:56:30 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:38439) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1icV8l-00059X-5Y for qemu-arm@nongnu.org; Wed, 04 Dec 2019 08:56:28 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1icV8j-0005Hh-Th for qemu-arm@nongnu.org; Wed, 04 Dec 2019 08:56:27 -0500 Received: from smtp-fw-6001.amazon.com ([52.95.48.154]:42197) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1icV8j-00058h-Pi; Wed, 04 Dec 2019 08:56:25 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amazon.de; i=@amazon.de; q=dns/txt; s=amazon201209; t=1575467786; x=1607003786; h=from:to:cc:subject:date:message-id:in-reply-to: references; bh=903Oin9iiuc+khCz3xboU318uHpQzskDGrltjVjcCSM=; b=FfLvHL4rlHS3OTiics/U3hMmZjFuBmt6+Mx/jDoVpOWeE04uCSpgsZvU 4TqaJ0Uu0kt19Z0o2DVqQqvFn8tYIiEDySqUi/HUckopc0cInm3/OF9ds 4dvnk4WFnk2nyJ0Y2lkf3I3b8OyHhdnwWAaUAysi1P+ryZK936629hjUt Q=; IronPort-SDR: 14zrM5qDK+M1wIRKinaJl1On6utbiyQqfM9hpWiDqLLMvFtDYSLempEbZ898yszACoWOIFSjRH onZAOInhjG7w== X-IronPort-AV: E=Sophos;i="5.69,277,1571702400"; d="scan'208";a="7621894" Received: from iad6-co-svc-p1-lb1-vlan3.amazon.com (HELO email-inbound-relay-2c-6f38efd9.us-west-2.amazon.com) ([10.124.125.6]) by smtp-border-fw-out-6001.iad6.amazon.com with ESMTP; 04 Dec 2019 13:56:25 +0000 Received: from sveith-desktop.aka.corp.amazon.com (pdx2-ws-svc-lb17-vlan2.amazon.com [10.247.140.66]) by email-inbound-relay-2c-6f38efd9.us-west-2.amazon.com (Postfix) with ESMTPS id 292F1A1FA7; Wed, 4 Dec 2019 13:56:23 +0000 (UTC) Received: from sveith-desktop.aka.corp.amazon.com (localhost [127.0.0.1]) by sveith-desktop.aka.corp.amazon.com (8.15.2/8.15.2/Debian-3) with ESMTP id xB4DuMZO029396; Wed, 4 Dec 2019 14:56:22 +0100 Received: (from sveith@localhost) by sveith-desktop.aka.corp.amazon.com (8.15.2/8.15.2/Submit) id xB4DuMcV029395; Wed, 4 Dec 2019 14:56:22 +0100 From: Simon Veith To: qemu-devel@nongnu.org, qemu-arm@nongnu.org Cc: Simon Veith , Eric Auger Subject: [PATCH 3/5] hw/arm/smmuv3: Align stream table base address to table size Date: Wed, 4 Dec 2019 14:55:46 +0100 Message-Id: <1575467748-28898-4-git-send-email-sveith@amazon.de> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1575467748-28898-1-git-send-email-sveith@amazon.de> References: <1575467748-28898-1-git-send-email-sveith@amazon.de> Precedence: Bulk X-detected-operating-system: by eggs.gnu.org: FreeBSD 9.x [fuzzy] X-Received-From: 52.95.48.154 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 04 Dec 2019 13:56:29 -0000 Per the specification, and as observed in hardware, the SMMUv3 aligns the SMMU_STRTAB_BASE address to the size of the table by masking out the respective least significant bits in the ADDR field. Apply this masking logic to our smmu_find_ste() lookup function per the specification. ref. ARM IHI 0070C, section 6.3.23. Signed-off-by: Simon Veith Cc: Eric Auger Cc: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org --- hw/arm/smmuv3.c | 29 +++++++++++++++++++++++++---- 1 file changed, 25 insertions(+), 4 deletions(-) diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c index aad4639..2d6c275 100644 --- a/hw/arm/smmuv3.c +++ b/hw/arm/smmuv3.c @@ -376,8 +376,9 @@ bad_ste: static int smmu_find_ste(SMMUv3State *s, uint32_t sid, STE *ste, SMMUEventInfo *event) { - dma_addr_t addr; + dma_addr_t addr, strtab_base; uint32_t log2size; + int strtab_size_shift; int ret; trace_smmuv3_find_ste(sid, s->features, s->sid_split); @@ -391,10 +392,23 @@ static int smmu_find_ste(SMMUv3State *s, uint32_t sid, STE *ste, } if (s->features & SMMU_FEATURE_2LVL_STE) { int l1_ste_offset, l2_ste_offset, max_l2_ste, span; - dma_addr_t strtab_base, l1ptr, l2ptr; + dma_addr_t l1ptr, l2ptr; STEDesc l1std; - strtab_base = s->strtab_base & SMMU_BASE_ADDR_MASK; + /* + * Align strtab base address to table size. For this purpose, assume it + * is not bounded by SMMU_IDR1_SIDSIZE. + */ + strtab_size_shift = log2size - s->sid_split - 1 + 3; + if (strtab_size_shift < DMA_ADDR_BITS) { + if (strtab_size_shift < 5) { + strtab_size_shift = 5; + } + strtab_base = s->strtab_base & SMMU_BASE_ADDR_MASK & + ~((1ULL << strtab_size_shift) - 1); + } else { + strtab_base = 0; + } l1_ste_offset = sid >> s->sid_split; l2_ste_offset = sid & ((1 << s->sid_split) - 1); l1ptr = (dma_addr_t)(strtab_base + l1_ste_offset * sizeof(l1std)); @@ -433,7 +447,14 @@ static int smmu_find_ste(SMMUv3State *s, uint32_t sid, STE *ste, } addr = l2ptr + l2_ste_offset * sizeof(*ste); } else { - addr = (s->strtab_base & SMMU_BASE_ADDR_MASK) + sid * sizeof(*ste); + strtab_size_shift = log2size + 5; + if (strtab_size_shift < DMA_ADDR_BITS) { + strtab_base = s->strtab_base & SMMU_BASE_ADDR_MASK & + ~((1ULL << strtab_size_shift) - 1); + } else { + strtab_base = 0; + } + addr = strtab_base + sid * sizeof(*ste); } if (smmu_get_ste(s, addr, ste, event)) { -- 2.7.4 From MAILER-DAEMON Wed Dec 04 08:56:30 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1icV8o-0005F5-DY for mharc-qemu-arm@gnu.org; Wed, 04 Dec 2019 08:56:30 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:38411) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1icV8j-00057e-Tq for qemu-arm@nongnu.org; Wed, 04 Dec 2019 08:56:27 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1icV8i-0005EG-OP for qemu-arm@nongnu.org; Wed, 04 Dec 2019 08:56:25 -0500 Received: from smtp-fw-9101.amazon.com ([207.171.184.25]:9490) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1icV8i-0005BH-HB; Wed, 04 Dec 2019 08:56:24 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amazon.de; i=@amazon.de; q=dns/txt; s=amazon201209; t=1575467784; x=1607003784; h=from:to:cc:subject:date:message-id:in-reply-to: references; bh=mGz2Hs159Z/4+8pT881Ub7PtsnSyXxiUtbVakc2yFWM=; b=F01Fw8CDIdq4GZyQntiadzGH2NBKnZufGKnyhlu0SaepjkVzIj2ywRhF LKkillroCAZhyWJ936gRjDDt6Z0uclr8LHaB8a8EJB1qJ9JQhPQz5aW9W oNpYkA8djhq8YcDRt0rAZOjqmMFoRQ008YA+nwZs0p8slBUziq1UPUA3z g=; IronPort-SDR: 6smuSj9Iia7aCLpemJErFU3iL5nFjvhmsp19zr4FoSQ1qTYGbMstT+LPjGnZTaJLRGtz6d5vZL L9Kv8Oo6K72Q== X-IronPort-AV: E=Sophos;i="5.69,277,1571702400"; d="scan'208";a="3177677" Received: from sea32-co-svc-lb4-vlan3.sea.corp.amazon.com (HELO email-inbound-relay-2b-8cc5d68b.us-west-2.amazon.com) ([10.47.23.38]) by smtp-border-fw-out-9101.sea19.amazon.com with ESMTP; 04 Dec 2019 13:56:22 +0000 Received: from sveith-desktop.aka.corp.amazon.com (pdx2-ws-svc-lb17-vlan2.amazon.com [10.247.140.66]) by email-inbound-relay-2b-8cc5d68b.us-west-2.amazon.com (Postfix) with ESMTPS id 19EF7A2330; Wed, 4 Dec 2019 13:56:20 +0000 (UTC) Received: from sveith-desktop.aka.corp.amazon.com (localhost [127.0.0.1]) by sveith-desktop.aka.corp.amazon.com (8.15.2/8.15.2/Debian-3) with ESMTP id xB4DuJbQ029389; Wed, 4 Dec 2019 14:56:19 +0100 Received: (from sveith@localhost) by sveith-desktop.aka.corp.amazon.com (8.15.2/8.15.2/Submit) id xB4DuJ65029388; Wed, 4 Dec 2019 14:56:19 +0100 From: Simon Veith To: qemu-devel@nongnu.org, qemu-arm@nongnu.org Cc: Simon Veith , Eric Auger Subject: [PATCH 2/5] hw/arm/smmuv3: Check stream IDs against actual table LOG2SIZE Date: Wed, 4 Dec 2019 14:55:45 +0100 Message-Id: <1575467748-28898-3-git-send-email-sveith@amazon.de> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1575467748-28898-1-git-send-email-sveith@amazon.de> References: <1575467748-28898-1-git-send-email-sveith@amazon.de> Precedence: Bulk X-detected-operating-system: by eggs.gnu.org: FreeBSD 9.x [fuzzy] X-Received-From: 207.171.184.25 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 04 Dec 2019 13:56:28 -0000 When checking whether a stream ID is in range of the stream table, we have so far been only checking it against our implementation limit (SMMU_IDR1_SIDSIZE). However, the guest can program the STRTAB_BASE_CFG.LOG2SIZE field to a size that is smaller than this limit. Check the stream ID against this limit as well to match the hardware behavior of raising C_BAD_STREAMID events in case the limit is exceeded. ref. ARM IHI 0070C, section 6.3.24. Signed-off-by: Simon Veith Cc: Eric Auger Cc: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org --- hw/arm/smmuv3.c | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c index eef9a18..aad4639 100644 --- a/hw/arm/smmuv3.c +++ b/hw/arm/smmuv3.c @@ -377,11 +377,15 @@ static int smmu_find_ste(SMMUv3State *s, uint32_t sid, STE *ste, SMMUEventInfo *event) { dma_addr_t addr; + uint32_t log2size; int ret; trace_smmuv3_find_ste(sid, s->features, s->sid_split); - /* Check SID range */ - if (sid > (1 << SMMU_IDR1_SIDSIZE)) { + log2size = FIELD_EX32(s->strtab_base_cfg, STRTAB_BASE_CFG, LOG2SIZE); + /* + * Check SID range against both guest-configured and implementation limits + */ + if (sid > (1 << MIN(log2size, SMMU_IDR1_SIDSIZE))) { event->type = SMMU_EVT_C_BAD_STREAMID; return -EINVAL; } -- 2.7.4 From MAILER-DAEMON Wed Dec 04 08:56:35 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1icV8t-0005NC-6t for mharc-qemu-arm@gnu.org; Wed, 04 Dec 2019 08:56:35 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:38498) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1icV8q-0005IE-6S for qemu-arm@nongnu.org; Wed, 04 Dec 2019 08:56:33 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1icV8p-0005Po-3O for qemu-arm@nongnu.org; Wed, 04 Dec 2019 08:56:32 -0500 Received: from smtp-fw-2101.amazon.com ([72.21.196.25]:62079) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1icV8o-0005PN-UN; Wed, 04 Dec 2019 08:56:31 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amazon.de; i=@amazon.de; q=dns/txt; s=amazon201209; t=1575467791; x=1607003791; h=from:to:cc:subject:date:message-id:in-reply-to: references; bh=ZJTN+ohaJEyJa5Mz38YWX2orkNnDr5ayiRkSEay2Bdo=; b=Jb+yjW7WmxhOiBvSEB8HwP8Zi/Wdac+eksxvj7s/Wv5AQO12vILGGXg2 6cSq1q7qci2B/F0pamc4TDE9FNipZcajTaNOkfIQtvii+XZFNDExseP5h FvtmEb5lIs5zy03zaLHW0yw0B3aHJtdR05mqPdqaG4NRe/B4s5WVCm0yM 4=; IronPort-SDR: xAghjvXNYNirL+e0jZsjnDzVKkEodVBF1T9JaUN3H8Slhdwps/MZLMCnBH+oh0CIHOOs/1woY2 yi3yNajWEnlg== X-IronPort-AV: E=Sophos;i="5.69,277,1571702400"; d="scan'208";a="7106992" Received: from iad6-co-svc-p1-lb1-vlan2.amazon.com (HELO email-inbound-relay-2c-6f38efd9.us-west-2.amazon.com) ([10.124.125.2]) by smtp-border-fw-out-2101.iad2.amazon.com with ESMTP; 04 Dec 2019 13:56:29 +0000 Received: from sveith-desktop.aka.corp.amazon.com (pdx2-ws-svc-lb17-vlan2.amazon.com [10.247.140.66]) by email-inbound-relay-2c-6f38efd9.us-west-2.amazon.com (Postfix) with ESMTPS id DF7E8A1FAE; Wed, 4 Dec 2019 13:56:27 +0000 (UTC) Received: from sveith-desktop.aka.corp.amazon.com (localhost [127.0.0.1]) by sveith-desktop.aka.corp.amazon.com (8.15.2/8.15.2/Debian-3) with ESMTP id xB4DuQXE029431; Wed, 4 Dec 2019 14:56:26 +0100 Received: (from sveith@localhost) by sveith-desktop.aka.corp.amazon.com (8.15.2/8.15.2/Submit) id xB4DuQPZ029429; Wed, 4 Dec 2019 14:56:26 +0100 From: Simon Veith To: qemu-devel@nongnu.org, qemu-arm@nongnu.org Cc: Simon Veith , Eric Auger Subject: [PATCH 4/5] hw/arm/smmuv3: Use correct bit positions in EVT_SET_ADDR2 macro Date: Wed, 4 Dec 2019 14:55:47 +0100 Message-Id: <1575467748-28898-5-git-send-email-sveith@amazon.de> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1575467748-28898-1-git-send-email-sveith@amazon.de> References: <1575467748-28898-1-git-send-email-sveith@amazon.de> Precedence: Bulk X-detected-operating-system: by eggs.gnu.org: FreeBSD 9.x [fuzzy] X-Received-From: 72.21.196.25 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 04 Dec 2019 13:56:34 -0000 The bit offsets in the EVT_SET_ADDR2 macro do not match those specified in the ARM SMMUv3 Architecture Specification. In all events that use this macro, e.g. F_WALK_EABT, the faulting fetch address or IPA actually occupies the 32-bit words 6 and 7 in the event record contiguously, with the upper and lower unused bits clear due to alignment or maximum supported address bits. How many bits are clear depends on the individual event type. Update the macro to write to the correct words in the event record so that guest drivers can obtain accurate address information on events. ref. ARM IHI 0070C, sections 7.3.12 through 7.3.16. Signed-off-by: Simon Veith Cc: Eric Auger Cc: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org --- hw/arm/smmuv3-internal.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/hw/arm/smmuv3-internal.h b/hw/arm/smmuv3-internal.h index d190181..eb275e2 100644 --- a/hw/arm/smmuv3-internal.h +++ b/hw/arm/smmuv3-internal.h @@ -461,8 +461,8 @@ typedef struct SMMUEventInfo { } while (0) #define EVT_SET_ADDR2(x, addr) \ do { \ - (x)->word[7] = deposit32((x)->word[7], 3, 29, addr >> 16); \ - (x)->word[7] = deposit32((x)->word[7], 0, 16, addr & 0xffff);\ + (x)->word[7] = (uint32_t)(addr >> 32); \ + (x)->word[6] = (uint32_t)(addr & 0xffffffff); \ } while (0) void smmuv3_record_event(SMMUv3State *s, SMMUEventInfo *event); -- 2.7.4 From MAILER-DAEMON Wed Dec 04 08:56:38 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1icV8w-0005Sj-IC for mharc-qemu-arm@gnu.org; Wed, 04 Dec 2019 08:56:38 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:38531) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1icV8s-0005M9-Gh for qemu-arm@nongnu.org; Wed, 04 Dec 2019 08:56:35 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1icV8r-0005RZ-Dz for qemu-arm@nongnu.org; Wed, 04 Dec 2019 08:56:34 -0500 Received: from smtp-fw-9101.amazon.com ([207.171.184.25]:9536) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1icV8r-0005QG-6e; Wed, 04 Dec 2019 08:56:33 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amazon.de; i=@amazon.de; q=dns/txt; s=amazon201209; t=1575467793; x=1607003793; h=from:to:cc:subject:date:message-id:in-reply-to: references; bh=uThbvtPQAz4aUcOeaWmIN//ZqDzYZn0zQCbaxFwdtm0=; b=FEZpZAsTEgUabUqIqUochmBbsfGJ9UvVqT7JWHO3eLSokf10badQzn5y gZUGy8gNbWzLFChaB+Zfyrz3+jgyfWgGTv19UidtKkZEUOFv3KoRxGkpO tWDTHk/mBYDC488mbJqqiaJ3Bqg7fVJfEKDl4x2lXJJCJjU9E2bWV+iPx c=; IronPort-SDR: 99aAc83sA2OgyShNxfulzAYj5fH+VfXXffUGMHdweV+0Iuyx7LbWzGx1DrSMd9TbQzfj+YgX+/ 8qH33e89q97w== X-IronPort-AV: E=Sophos;i="5.69,277,1571702400"; d="scan'208";a="3177723" Received: from sea32-co-svc-lb4-vlan3.sea.corp.amazon.com (HELO email-inbound-relay-2a-119b4f96.us-west-2.amazon.com) ([10.47.23.38]) by smtp-border-fw-out-9101.sea19.amazon.com with ESMTP; 04 Dec 2019 13:56:32 +0000 Received: from sveith-desktop.aka.corp.amazon.com (pdx2-ws-svc-lb17-vlan3.amazon.com [10.247.140.70]) by email-inbound-relay-2a-119b4f96.us-west-2.amazon.com (Postfix) with ESMTPS id BA66F1A11D5; Wed, 4 Dec 2019 13:56:31 +0000 (UTC) Received: from sveith-desktop.aka.corp.amazon.com (localhost [127.0.0.1]) by sveith-desktop.aka.corp.amazon.com (8.15.2/8.15.2/Debian-3) with ESMTP id xB4DuUkY029462; Wed, 4 Dec 2019 14:56:30 +0100 Received: (from sveith@localhost) by sveith-desktop.aka.corp.amazon.com (8.15.2/8.15.2/Submit) id xB4DuUrM029461; Wed, 4 Dec 2019 14:56:30 +0100 From: Simon Veith To: qemu-devel@nongnu.org, qemu-arm@nongnu.org Cc: Simon Veith , Eric Auger Subject: [PATCH 5/5] hw/arm/smmuv3: Report F_STE_FETCH fault address in correct word position Date: Wed, 4 Dec 2019 14:55:48 +0100 Message-Id: <1575467748-28898-6-git-send-email-sveith@amazon.de> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1575467748-28898-1-git-send-email-sveith@amazon.de> References: <1575467748-28898-1-git-send-email-sveith@amazon.de> Precedence: Bulk X-detected-operating-system: by eggs.gnu.org: FreeBSD 9.x [fuzzy] X-Received-From: 207.171.184.25 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 04 Dec 2019 13:56:37 -0000 The smmuv3_record_event() function that generates the F_STE_FETCH error uses the EVT_SET_ADDR macro to record the fetch address, placing it in 32-bit words 4 and 5. The correct position for this address is in words 6 and 7, per the SMMUv3 Architecture Specification. Update the function to use the EVT_SET_ADDR2 macro instead, which is the macro intended for writing to these words. ref. ARM IHI 0070C, section 7.3.4. Signed-off-by: Simon Veith Cc: Eric Auger Cc: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org --- hw/arm/smmuv3.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c index 2d6c275..125e47d 100644 --- a/hw/arm/smmuv3.c +++ b/hw/arm/smmuv3.c @@ -172,7 +172,7 @@ void smmuv3_record_event(SMMUv3State *s, SMMUEventInfo *info) case SMMU_EVT_F_STE_FETCH: EVT_SET_SSID(&evt, info->u.f_ste_fetch.ssid); EVT_SET_SSV(&evt, info->u.f_ste_fetch.ssv); - EVT_SET_ADDR(&evt, info->u.f_ste_fetch.addr); + EVT_SET_ADDR2(&evt, info->u.f_ste_fetch.addr); break; case SMMU_EVT_C_BAD_STE: EVT_SET_SSID(&evt, info->u.c_bad_ste.ssid); -- 2.7.4 From MAILER-DAEMON Wed Dec 04 10:01:08 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1icW9K-00081y-8h for mharc-qemu-arm@gnu.org; Wed, 04 Dec 2019 10:01:07 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:48422) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1icW95-0007yG-5v for qemu-arm@nongnu.org; Wed, 04 Dec 2019 10:00:55 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1icW8x-0000MA-PY for qemu-arm@nongnu.org; Wed, 04 Dec 2019 10:00:50 -0500 Received: from us-smtp-2.mimecast.com ([207.211.31.81]:33688 helo=us-smtp-delivery-1.mimecast.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1icW8x-0000Ll-JS for qemu-arm@nongnu.org; Wed, 04 Dec 2019 10:00:43 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1575471643; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=ajRfpg8Ys2mundddq1XB+ae7HTn9RvM1JIztRsA+x88=; b=A+ywdV5WHf3FBI4ktUXu7ICSEbE2SacHxC4AkvV9WKIb3dyCmtID2cVDscbs0Fn9sWUDTD fxe0NTe1r9dfbgsz9680THTB8UqzJaYENPIqd5zPevHmvkcBuEmhTVqmgu0XZW7+ehi12h kOBG0WhgeB5AJspWzLTjoBwbbVH88Fk= Received: from mimecast-mx01.redhat.com (mimecast-mx01.redhat.com [209.132.183.4]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-121-mtHk5eY3O-2_dbJ5ZdlsaQ-1; Wed, 04 Dec 2019 10:00:40 -0500 Received: from smtp.corp.redhat.com (int-mx08.intmail.prod.int.phx2.redhat.com [10.5.11.23]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx01.redhat.com (Postfix) with ESMTPS id D568618557FF; Wed, 4 Dec 2019 15:00:36 +0000 (UTC) Received: from blackfin.pond.sub.org (ovpn-116-134.ams2.redhat.com [10.36.116.134]) by smtp.corp.redhat.com (Postfix) with ESMTPS id 4E41E19C68; Wed, 4 Dec 2019 15:00:01 +0000 (UTC) Received: by blackfin.pond.sub.org (Postfix, from userid 1000) id C11E51138606; Wed, 4 Dec 2019 15:59:59 +0100 (CET) From: Markus Armbruster To: Vladimir Sementsov-Ogievskiy Cc: qemu-devel@nongnu.org, Ronnie Sahlberg , Jeff Cody , Jan Kiszka , Alberto Garcia , Hailiang Zhang , qemu-block@nongnu.org, Aleksandar Rikalo , Halil Pasic , =?utf-8?Q?Herv=C3=A9?= Poussineau , Anthony Perard , Samuel Thibault , Philippe =?utf-8?Q?Mathieu-Daud=C3=A9?= , Anthony Green , Laurent Vivier , Eduardo Habkost , Xie Changlong , Peter Lieven , "Dr. David Alan Gilbert" , Beniamino Galvani , Eric Auger , Alex Williamson , Stefan Hajnoczi , John Snow , Richard Henderson , Kevin Wolf , Andrew Jeffery , Chris Wulff , Subbaraya Sundeep , Michael Walle , qemu-ppc@nongnu.org, Bastian Koppelmann , Igor Mammedov , Fam Zheng , Peter Maydell , sheepdog@lists.wpkg.org, Matthew Rosato , David Hildenbrand , Palmer Dabbelt , Thomas Huth , Max Filippov , "Denis V. Lunev" , Hannes Reinecke , Stefano Stabellini , "Gonglei \(Arei\)" , Liu Yuan , Artyom Tarasenko , Eric Farman , Amit Shah , Stefan Weil , Greg Kurz , Yuval Shaia , qemu-s390x@nongnu.org, qemu-arm@nongnu.org, Peter Chubb , =?utf-8?Q?C=C3=A9dric?= Le Goater , Stafford Horne , qemu-riscv@nongnu.org, Cornelia Huck , Aleksandar Markovic , Aurelien Jarno , Paul Burton , Sagar Karandikar , Paul Durrant , Jason Wang , Gerd Hoffmann , "Edgar E. Iglesias" , Guan Xuetao , Ari Sundholm , Juan Quintela , Michael Roth , Christian Borntraeger , Joel Stanley , Jason Dillaman , Antony Pavlov , xen-devel@lists.xenproject.org, integration@gluster.org, Laszlo Ersek , "Richard W.M. Jones" , Andrew Baumann , Max Reitz , "Michael S. Tsirkin" , Mark Cave-Ayland , Vincenzo Maffione , Marek Vasut , armbru@redhat.com, =?utf-8?Q?Marc-Andr=C3=A9?= Lureau , Alistair Francis , Pavel Dovgalyuk , Giuseppe Lettieri , Luigi Rizzo , David Gibson , Tony Krowiak , Daniel P. =?utf-8?Q?Berrang=C3=A9?= , Xiao Guangrong , Pierre Morel , Wen Congyang , Jean-Christophe Dubois , Paolo Bonzini , Stefan Berger Subject: Re: [RFC v5 024/126] error: auto propagated local_err References: <20191011160552.22907-1-vsementsov@virtuozzo.com> <20191011160552.22907-25-vsementsov@virtuozzo.com> Date: Wed, 04 Dec 2019 15:59:59 +0100 In-Reply-To: <20191011160552.22907-25-vsementsov@virtuozzo.com> (Vladimir Sementsov-Ogievskiy's message of "Fri, 11 Oct 2019 19:04:10 +0300") Message-ID: <87muc8p24w.fsf@dusky.pond.sub.org> User-Agent: Gnus/5.13 (Gnus v5.13) Emacs/26.2 (gnu/linux) MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.84 on 10.5.11.23 X-MC-Unique: mtHk5eY3O-2_dbJ5ZdlsaQ-1 X-Mimecast-Spam-Score: 0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 207.211.31.81 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 04 Dec 2019 15:00:56 -0000 Vladimir Sementsov-Ogievskiy writes: > Here is introduced ERRP_AUTO_PROPAGATE macro, to be used at start of > functions with errp OUT parameter. > > It has three goals: > > 1. Fix issue with error_fatal & error_prepend/error_append_hint: user > can't see this additional information, because exit() happens in > error_setg earlier than information is added. [Reported by Greg Kurz] > > 2. Fix issue with error_abort & error_propagate: when we wrap > error_abort by local_err+error_propagate, resulting coredump will > refer to error_propagate and not to the place where error happened. I get what you mean, but I have plenty of context. > (the macro itself doesn't fix the issue, but it allows to [3.] drop all > local_err+error_propagate pattern, which will definitely fix the issue) The parenthesis is not part of the goal. > [Reported by Kevin Wolf] > > 3. Drop local_err+error_propagate pattern, which is used to workaround > void functions with errp parameter, when caller wants to know resulting > status. (Note: actually these functions could be merely updated to > return int error code). > > To achieve these goals, we need to add invocation of the macro at start > of functions, which needs error_prepend/error_append_hint (1.); add > invocation of the macro at start of functions which do > local_err+error_propagate scenario the check errors, drop local errors > from them and just use *errp instead (2., 3.). The paragraph talks about two cases: 1. and 2.+3. Makes me think we want two paragraphs, each illustrated with an example. What about you provide the examples, and then I try to polish the prose? > Signed-off-by: Vladimir Sementsov-Ogievskiy > Reviewed-by: Eric Blake > --- > > CC: Gerd Hoffmann > CC: "Gonglei (Arei)" > CC: Eduardo Habkost > CC: Igor Mammedov > CC: Laurent Vivier > CC: Amit Shah > CC: Kevin Wolf > CC: Max Reitz > CC: John Snow > CC: Ari Sundholm > CC: Pavel Dovgalyuk > CC: Paolo Bonzini > CC: Stefan Hajnoczi > CC: Fam Zheng > CC: Stefan Weil > CC: Ronnie Sahlberg > CC: Peter Lieven > CC: Eric Blake > CC: "Denis V. Lunev" > CC: Markus Armbruster > CC: Alberto Garcia > CC: Jason Dillaman > CC: Wen Congyang > CC: Xie Changlong > CC: Liu Yuan > CC: "Richard W.M. Jones" > CC: Jeff Cody > CC: "Marc-Andr=C3=A9 Lureau" > CC: "Daniel P. Berrang=C3=A9" > CC: Richard Henderson > CC: Greg Kurz > CC: "Michael S. Tsirkin" > CC: Marcel Apfelbaum > CC: Beniamino Galvani > CC: Peter Maydell > CC: "C=C3=A9dric Le Goater" > CC: Andrew Jeffery > CC: Joel Stanley > CC: Andrew Baumann > CC: "Philippe Mathieu-Daud=C3=A9" > CC: Antony Pavlov > CC: Jean-Christophe Dubois > CC: Peter Chubb > CC: Subbaraya Sundeep > CC: Eric Auger > CC: Alistair Francis > CC: "Edgar E. Iglesias" > CC: Stefano Stabellini > CC: Anthony Perard > CC: Paul Durrant > CC: Paul Burton > CC: Aleksandar Rikalo > CC: Chris Wulff > CC: Marek Vasut > CC: David Gibson > CC: Cornelia Huck > CC: Halil Pasic > CC: Christian Borntraeger > CC: "Herv=C3=A9 Poussineau" > CC: Xiao Guangrong > CC: Aurelien Jarno > CC: Aleksandar Markovic > CC: Mark Cave-Ayland > CC: Jason Wang > CC: Laszlo Ersek > CC: Yuval Shaia > CC: Palmer Dabbelt > CC: Sagar Karandikar > CC: Bastian Koppelmann > CC: David Hildenbrand > CC: Thomas Huth > CC: Eric Farman > CC: Matthew Rosato > CC: Hannes Reinecke > CC: Michael Walle > CC: Artyom Tarasenko > CC: Stefan Berger > CC: Samuel Thibault > CC: Alex Williamson > CC: Tony Krowiak > CC: Pierre Morel > CC: Michael Roth > CC: Hailiang Zhang > CC: Juan Quintela > CC: "Dr. David Alan Gilbert" > CC: Luigi Rizzo > CC: Giuseppe Lettieri > CC: Vincenzo Maffione > CC: Jan Kiszka > CC: Anthony Green > CC: Stafford Horne > CC: Guan Xuetao > CC: Max Filippov > CC: qemu-block@nongnu.org > CC: integration@gluster.org > CC: sheepdog@lists.wpkg.org > CC: qemu-arm@nongnu.org > CC: xen-devel@lists.xenproject.org > CC: qemu-ppc@nongnu.org > CC: qemu-s390x@nongnu.org > CC: qemu-riscv@nongnu.org > > include/qapi/error.h | 38 ++++++++++++++++++++++++++++++++++++++ > 1 file changed, 38 insertions(+) > > diff --git a/include/qapi/error.h b/include/qapi/error.h > index d6898d833b..47238d9065 100644 > --- a/include/qapi/error.h > +++ b/include/qapi/error.h > @@ -345,6 +345,44 @@ void error_set_internal(Error **errp, > ErrorClass err_class, const char *fmt, ...) > GCC_FMT_ATTR(6, 7); > =20 > +typedef struct ErrorPropagator { > + Error *local_err; > + Error **errp; > +} ErrorPropagator; > + > +static inline void error_propagator_cleanup(ErrorPropagator *prop) > +{ > + error_propagate(prop->errp, prop->local_err); > +} > + > +G_DEFINE_AUTO_CLEANUP_CLEAR_FUNC(ErrorPropagator, error_propagator_clean= up); > + > +/* > + * ERRP_AUTO_PROPAGATE > + * > + * This macro is created to be the first line of a function with Error *= *errp > + * OUT parameter. It's needed only in cases where we want to use error_p= repend, > + * error_append_hint or dereference *errp. It's still safe (but useless)= in > + * other cases. > + * > + * If errp is NULL or points to error_fatal, it is rewritten to point to= a > + * local Error object, which will be automatically propagated to the ori= ginal > + * errp on function exit (see error_propagator_cleanup). > + * > + * After invocation of this macro it is always safe to dereference errp > + * (as it's not NULL anymore) and to add information (by error_prepend o= r > + * error_append_hint) > + * (as, if it was error_fatal, we swapped it with a local_error to be > + * propagated on cleanup). > + * > + * Note: we don't wrap the error_abort case, as we want resulting coredu= mp > + * to point to the place where the error happened, not to error_propagat= e. > + */ > +#define ERRP_AUTO_PROPAGATE() \ > + g_auto(ErrorPropagator) _auto_errp_prop =3D {.errp =3D errp}; \ > + errp =3D ((errp =3D=3D NULL || *errp =3D=3D error_fatal) = \ > + ? &_auto_errp_prop.local_err : errp) > + > /* > * Special error destination to abort on error. > * See error_setg() and error_propagate() for details. Missing: update of the big comment starting with "Error reporting system loosely patterned after Glib's GError." From MAILER-DAEMON Wed Dec 04 10:11:49 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1icWJh-0008HJ-7t for mharc-qemu-arm@gnu.org; Wed, 04 Dec 2019 10:11:49 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:50138) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1icWJe-0008Gz-Jh for qemu-arm@nongnu.org; Wed, 04 Dec 2019 10:11:47 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1icWJd-0003Ay-CQ for qemu-arm@nongnu.org; Wed, 04 Dec 2019 10:11:46 -0500 Received: from mail-ot1-x341.google.com ([2607:f8b0:4864:20::341]:45952) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1icWJd-0003AN-3Q for qemu-arm@nongnu.org; Wed, 04 Dec 2019 10:11:45 -0500 Received: by mail-ot1-x341.google.com with SMTP id 59so6565645otp.12 for ; Wed, 04 Dec 2019 07:11:44 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc:content-transfer-encoding; bh=4/Qwt0GouNX9aM/smKfTqvCUQpZ3KJlj3iVgRiG22vk=; b=txot3LlfUrdPFV8xcn0ktczbFaWdRP1NcTfchRBQkBGqH90l52P+tEJFZXMzQ+rolk TbQuZu0N6AHmidT+gG5Hh4cIc6xy2uumCVA1ZSUryVZNcRYTjBtGrfyO795gtClyltA9 LNlLVIRMtFRGx4nIxvtXa6Re2lcf0yplU2TAmlLlfnWNpdg8BpxFpumnHqo6aQE40oEy 7H1gWQ3u08m+kGhL6YTImwX9jcmtWkEF7iOiDACu5hVbRbDALgiv+hF7u6a6uG6NgcQ4 b830G/n6nL7SqOeaqbgBDQtUwKAGG2HkrdVthEpQ+UWPquAFmPE2mTNArofaqyL+6yqZ SWAQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc:content-transfer-encoding; bh=4/Qwt0GouNX9aM/smKfTqvCUQpZ3KJlj3iVgRiG22vk=; b=b1m/TnqkjC1uTeYI7IxOpdnwCAEMob1339CKYeI3zIK3YudZ+wPrh8v7XoYHX3M0Xt pdE/fn5rCEWZDUTc4I9O9Mi7qGTvEhwwMRwnzSdT+B142fQDQqwqusaUGM+BYXhzNh+w DquTgQkX5kWs6JBHVwfyZ2R5sYjJRGJ+iaDRp9qNvEv9XftH7F8eMBRWqnKwopxYKBoi 7zars7bZwp06KrxYGwVO6kbSE4xqSjlefFQ6Nqi2jbGp52hsSHxZAW0HeF9cz9WMFyGW /65FqFOP/v5a/a6r6blTxEHBhZMXB1Mb7/mI3te5i+wJWv/5IQi2k3rT9PSnmhYkt+19 8agA== X-Gm-Message-State: APjAAAXdrBJ6H5NoYwgVC/d3UlDiudR9yVm78t0tXAJ5Dtz7eO6gFhg0 /KgwHzlOEc7wrN9w7As0A0Dr4emjkko76TO+ke0pMw== X-Google-Smtp-Source: APXvYqwrdxglaHM3KUKhMSJK609w99Cskdit0Oyeklq+626ssgw7G53HY6EhmHBLglmIr8Un0Hh3R8/BWBW5gJtUC3k= X-Received: by 2002:a9d:6745:: with SMTP id w5mr2733664otm.221.1575472303955; Wed, 04 Dec 2019 07:11:43 -0800 (PST) MIME-Version: 1.0 References: <20191129150508.24404-1-bilalwasim676@gmail.com> <8c956ae31e8f44a2b831a5030b2448b4@SVR-IES-MBX-03.mgc.mentorg.com> In-Reply-To: From: Peter Maydell Date: Wed, 4 Dec 2019 15:11:32 +0000 Message-ID: Subject: Re: [PATCH] net/imx_fec: Updating the IMX_FEC IP to support loopback mode. To: Jason Wang Cc: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= , "Wasim, Bilal" , "bilalwasim676@gmail.com" , "qemu-devel@nongnu.org" , "aa1ronham@gmail.com" , "jcd@tribudubois.net" , "qemu-arm@nongnu.org" , "linux@roeck-us.net" Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::341 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 04 Dec 2019 15:11:47 -0000 On Wed, 4 Dec 2019 at 02:15, Jason Wang wrote: > > > On 2019/11/30 =E4=B8=8A=E5=8D=8812:04, Philippe Mathieu-Daud=C3=A9 wrote: > > On Fri, Nov 29, 2019 at 4:59 PM Wasim, Bilal w= rote: > >> Thanks for the pointers philippe.. Is the patch okay to be merged with= out it or do I need to do a re-submission with the updated username ? > > If there are no review comments on your patch, I think the maintainer > > taking your patch can fix this details directly, no need to resend. > > > >> -----Original Message----- > >> From: Philippe Mathieu-Daud=C3=A9 [mailto:philmd@redhat.com] > >> Sent: Friday, November 29, 2019 8:38 PM > >> To: bilalwasim676@gmail.com; qemu-devel@nongnu.org > >> Cc: peter.maydell@linaro.org; aa1ronham@gmail.com; jcd@tribudubois.net= ; qemu-arm@nongnu.org; Wasim, Bilal ; linux@roeck-u= s.net; Jason Wang > >> Subject: Re: [PATCH] net/imx_fec: Updating the IMX_FEC IP to support l= oopback mode. > >> > >> Hi Bilal, > >> > >> Cc'ing Jason, the maintainer of network devices. > >> > >> On 11/29/19 4:05 PM, bilalwasim676@gmail.com wrote: > >>> From: bwasim > >> Your git setup misses your 'user.name', you could fix it running: > >> > >> git config user.name "Bilal Wasim" > >> > >> (eventually with the --global option). > >> > >> The patch looks good otherwise. > >> > >> Thanks! > > > Applied with the fix for user.name. Could you fix up the non-standard block comment formatting too? thanks -- PMM From MAILER-DAEMON Wed Dec 04 10:14:40 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1icWMS-0001HS-Jp for mharc-qemu-arm@gnu.org; Wed, 04 Dec 2019 10:14:40 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:50355) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1icWMN-0001BM-03 for qemu-arm@nongnu.org; Wed, 04 Dec 2019 10:14:38 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1icWMK-0004kv-M7 for qemu-arm@nongnu.org; Wed, 04 Dec 2019 10:14:34 -0500 Received: from us-smtp-1.mimecast.com ([207.211.31.81]:38667 helo=us-smtp-delivery-1.mimecast.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1icWMK-0004kE-ID for qemu-arm@nongnu.org; Wed, 04 Dec 2019 10:14:32 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1575472471; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=DmIL8lWWj1hyNzh2lSYRiHrckJIy94t5tsFXYkLsG5U=; b=PQbvidKUo3wh6Bemg0Udt4uyv+gsbl8ym+p6if56MjzDVyE2g7/7nusisJ1DDhCb5zergD SipG36Q2xcl9ispABOyHgg/A+Mdfm7kc/aQ31QQZOzItWU3EvFrxfzlns9QzEoDxlIGlvL WGt0HozN7PWYXT6Lzg0P3sHI9/3Dt4k= Received: from mail-wr1-f70.google.com (mail-wr1-f70.google.com [209.85.221.70]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-413-fRvjFrQqOHeGtvRiscBiPg-1; Wed, 04 Dec 2019 10:14:28 -0500 Received: by mail-wr1-f70.google.com with SMTP id c17so3759029wrp.10 for ; Wed, 04 Dec 2019 07:14:28 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:subject:to:cc:references:from:message-id:date :user-agent:mime-version:in-reply-to:content-language :content-transfer-encoding; bh=W18PxyJxSWB9j8jjViZ8sbO8hMAPaqPBEkNc0R4KLPM=; b=lacnf4fLOMFHK0f2kYvzxR2I6t4IIAiwfQBO+IPkyW69nN2cqos1oWbjoVQyIFemwR WKo8v0bA4Q+r6GRG2c6d//zsvyzBu8f7d2rqZonpB0l5QuJhhMCISj5wNHgCw5Iyrcjx eSInvHWLhM892+/fo7sZEQADbwI1v3BdTm+Olukfk8Um2FOeNh4vEPifAUv52Xzwluz4 B+lScmO0p3Hgsnu9ikZ9OZ1fIsBakJOHyZLzu/jwTWC06p+SGZy+XD90H3fImoNK/XOs L1ZHXFueTCCKT3SLsy6Tj8Rzcl47GkZd7zSmHMicOkhMBBc5orpbtdD5P6ni0r6SGeUX JjnQ== X-Gm-Message-State: APjAAAUzIF8+SK8siHIaXHGujUiKVpMdpHJC8ijFwYpELfXPx+pY1Ug0 XbzRl3X7OKxeywnTLoxJc7QE0xoYUo6ze4NdgL6FtALRt4gpQiDLE/2/xamEa4+oOO7j+mIzmZs PCar8wSdaG6pu X-Received: by 2002:a5d:6305:: with SMTP id i5mr4683932wru.119.1575472467125; Wed, 04 Dec 2019 07:14:27 -0800 (PST) X-Google-Smtp-Source: APXvYqxM1dInIw8DQr/izmUcxozvnmIY0Zfs3JqycwXdjMouUAL76BSyVhrYLpwI+rZWSIgxQRVnZg== X-Received: by 2002:a5d:6305:: with SMTP id i5mr4683894wru.119.1575472466759; Wed, 04 Dec 2019 07:14:26 -0800 (PST) Received: from [192.168.1.35] (182.red-88-21-103.staticip.rima-tde.net. [88.21.103.182]) by smtp.gmail.com with ESMTPSA id q6sm9075835wrx.72.2019.12.04.07.14.25 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 04 Dec 2019 07:14:26 -0800 (PST) Subject: Re: [PATCH 10/10] arm: allwinner-h3: add EMAC ethernet device To: KONRAD Frederic , Niek Linnenbank , qemu-devel@nongnu.org Cc: b.galvani@gmail.com, peter.maydell@linaro.org, qemu-arm@nongnu.org, Sai Pavan Boddu , Sven Schnelle , Grant Likely , Paolo Bonzini , Jason Wang References: <20191202210947.3603-1-nieklinnenbank@gmail.com> <20191202210947.3603-11-nieklinnenbank@gmail.com> From: =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= Message-ID: <0b549e25-cf45-e491-9342-58592514870f@redhat.com> Date: Wed, 4 Dec 2019 16:14:24 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.2.2 MIME-Version: 1.0 In-Reply-To: Content-Language: en-US X-MC-Unique: fRvjFrQqOHeGtvRiscBiPg-1 X-Mimecast-Spam-Score: 0 Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 207.211.31.81 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 04 Dec 2019 15:14:38 -0000 On 12/3/19 10:33 AM, KONRAD Frederic wrote: > Le 12/2/19 =C3=A0 10:09 PM, Niek Linnenbank a =C3=A9crit=C2=A0: >> The Allwinner H3 System on Chip includes an Ethernet MAC (EMAC) >> which provides 10M/100M/1000M Ethernet connectivity. This commit >> adds support for the Allwinner H3 EMAC, including emulation for >> the following functionality: >> >> =C2=A0 * DMA transfers >> =C2=A0 * MII interface >> =C2=A0 * Transmit CRC calculation >> >> Signed-off-by: Niek Linnenbank >> --- >> =C2=A0 hw/arm/Kconfig=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 |=C2= =A0=C2=A0 1 + >> =C2=A0 hw/arm/allwinner-h3.c=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 |=C2=A0 17 + >> =C2=A0 hw/arm/orangepi.c=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 |=C2=A0=C2=A0 7 + >> =C2=A0 hw/net/Kconfig=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 |=C2= =A0=C2=A0 3 + >> =C2=A0 hw/net/Makefile.objs=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 |=C2=A0=C2=A0 1 + >> =C2=A0 hw/net/allwinner-h3-emac.c=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0 | 786 +++++++++++++++++++++++++++++ >> =C2=A0 hw/net/trace-events=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 |=C2=A0 10 + >> =C2=A0 include/hw/arm/allwinner-h3.h=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 |=C2= =A0=C2=A0 2 + >> =C2=A0 include/hw/net/allwinner-h3-emac.h |=C2=A0 69 +++ >> =C2=A0 9 files changed, 896 insertions(+) >> =C2=A0 create mode 100644 hw/net/allwinner-h3-emac.c >> =C2=A0 create mode 100644 include/hw/net/allwinner-h3-emac.h >> >> diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig >> index ebf8d2325f..551cff3442 100644 >> --- a/hw/arm/Kconfig >> +++ b/hw/arm/Kconfig >> @@ -294,6 +294,7 @@ config ALLWINNER_A10 >> =C2=A0 config ALLWINNER_H3 >> =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 bool >> =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 select ALLWINNER_A10_PIT >> +=C2=A0=C2=A0=C2=A0 select ALLWINNER_H3_EMAC >> =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 select SERIAL >> =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 select ARM_TIMER >> =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 select ARM_GIC >> diff --git a/hw/arm/allwinner-h3.c b/hw/arm/allwinner-h3.c >> index c2972caf88..274b8548c0 100644 >> --- a/hw/arm/allwinner-h3.c >> +++ b/hw/arm/allwinner-h3.c >> @@ -53,6 +53,9 @@ static void aw_h3_init(Object *obj) >> =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 sysbus_init_child_obj(obj, "mmc0", &s->mm= c0, sizeof(s->mmc0), >> =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0 TYPE_AW_H3_SDHOST); >> + >> +=C2=A0=C2=A0=C2=A0 sysbus_init_child_obj(obj, "emac", &s->emac, sizeof(= s->emac), >> +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0 TYPE_AW_H3_EMAC); >> =C2=A0 } >> =C2=A0 static void aw_h3_realize(DeviceState *dev, Error **errp) >> @@ -237,6 +240,20 @@ static void aw_h3_realize(DeviceState *dev, Error= =20 >> **errp) >> =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 return; >> =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 } >> +=C2=A0=C2=A0=C2=A0 /* EMAC */ >> +=C2=A0=C2=A0=C2=A0 if (nd_table[0].used) { >> +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 qemu_check_nic_model(&nd_tab= le[0], TYPE_AW_H3_EMAC); >> +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 qdev_set_nic_properties(DEVI= CE(&s->emac), &nd_table[0]); >> +=C2=A0=C2=A0=C2=A0 } >> +=C2=A0=C2=A0=C2=A0 object_property_set_bool(OBJECT(&s->emac), true, "re= alized", &err); >> +=C2=A0=C2=A0=C2=A0 if (err !=3D NULL) { >> +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 error_propagate(errp, err); >> +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 return; >> +=C2=A0=C2=A0=C2=A0 } >> +=C2=A0=C2=A0=C2=A0 sysbusdev =3D SYS_BUS_DEVICE(&s->emac); >> +=C2=A0=C2=A0=C2=A0 sysbus_mmio_map(sysbusdev, 0, AW_H3_EMAC_BASE); >> +=C2=A0=C2=A0=C2=A0 sysbus_connect_irq(sysbusdev, 0, s->irq[AW_H3_GIC_SP= I_EMAC]); >> + >> =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 /* Universal Serial Bus */ >> =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 sysbus_create_simple(TYPE_AW_H3_EHCI, AW_= H3_EHCI0_BASE, >> =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0 s->irq[AW_H3_GIC_SPI_EHCI0]); >> diff --git a/hw/arm/orangepi.c b/hw/arm/orangepi.c >> index dee3efaf08..8a61eb0e69 100644 >> --- a/hw/arm/orangepi.c >> +++ b/hw/arm/orangepi.c >> @@ -61,6 +61,13 @@ static void orangepi_init(MachineState *machine) >> =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 exit(1); >> =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 } >> +=C2=A0=C2=A0=C2=A0 /* Setup EMAC properties */ >> +=C2=A0=C2=A0=C2=A0 object_property_set_int(OBJECT(&s->h3->emac), 1, "ph= y-addr", &err); >> +=C2=A0=C2=A0=C2=A0 if (err !=3D NULL) { >> +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 error_reportf_err(err, "Coul= dn't set phy address: "); >> +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 exit(1); >> +=C2=A0=C2=A0=C2=A0 } >> + >> =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 /* Mark H3 object realized */ >> =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 object_property_set_bool(OBJECT(s->h3), t= rue, "realized", &err); >> =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 if (err !=3D NULL) { >> diff --git a/hw/net/Kconfig b/hw/net/Kconfig >> index 3856417d42..36d3923992 100644 >> --- a/hw/net/Kconfig >> +++ b/hw/net/Kconfig >> @@ -74,6 +74,9 @@ config MIPSNET >> =C2=A0 config ALLWINNER_EMAC >> =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 bool >> +config ALLWINNER_H3_EMAC >> +=C2=A0=C2=A0=C2=A0 bool >> + >> =C2=A0 config IMX_FEC >> =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 bool >> diff --git a/hw/net/Makefile.objs b/hw/net/Makefile.objs >> index 7907d2c199..5548deb07a 100644 >> --- a/hw/net/Makefile.objs >> +++ b/hw/net/Makefile.objs >> @@ -23,6 +23,7 @@ common-obj-$(CONFIG_XGMAC) +=3D xgmac.o >> =C2=A0 common-obj-$(CONFIG_MIPSNET) +=3D mipsnet.o >> =C2=A0 common-obj-$(CONFIG_XILINX_AXI) +=3D xilinx_axienet.o >> =C2=A0 common-obj-$(CONFIG_ALLWINNER_EMAC) +=3D allwinner_emac.o >> +common-obj-$(CONFIG_ALLWINNER_H3_EMAC) +=3D allwinner-h3-emac.o >> =C2=A0 common-obj-$(CONFIG_IMX_FEC) +=3D imx_fec.o >> =C2=A0 common-obj-$(CONFIG_CADENCE) +=3D cadence_gem.o >> diff --git a/hw/net/allwinner-h3-emac.c b/hw/net/allwinner-h3-emac.c >> new file mode 100644 >> index 0000000000..37f6f44406 >> --- /dev/null >> +++ b/hw/net/allwinner-h3-emac.c >> @@ -0,0 +1,786 @@ >> +/* >> + * Allwinner H3 EMAC emulation >> + * >> + * Copyright (C) 2019 Niek Linnenbank >> + * >> + * This program is free software: you can redistribute it and/or modify >> + * it under the terms of the GNU General Public License as published by >> + * the Free Software Foundation, either version 2 of the License, or >> + * (at your option) any later version. >> + * >> + * This program is distributed in the hope that it will be useful, >> + * but WITHOUT ANY WARRANTY; without even the implied warranty of >> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.=C2=A0 See the >> + * GNU General Public License for more details. >> + * >> + * You should have received a copy of the GNU General Public License >> + * along with this program.=C2=A0 If not, see . >> + */ >> + >> +#include "qemu/osdep.h" >> +#include "hw/sysbus.h" >> +#include "migration/vmstate.h" >> +#include "net/net.h" >> +#include "hw/irq.h" >> +#include "hw/qdev-properties.h" >> +#include "qemu/log.h" >> +#include "trace.h" >> +#include "net/checksum.h" >> +#include "qemu/module.h" >> +#include "exec/cpu-common.h" >> +#include "hw/net/allwinner-h3-emac.h" >> + >> +/* EMAC register offsets */ >> +#define REG_BASIC_CTL_0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 (0x00= 00) /* Basic Control 0 */ >> +#define REG_BASIC_CTL_1=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 (0x00= 04) /* Basic Control 1 */ >> +#define REG_INT_STA=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0 (0x0008) /* Interrupt Status */ >> +#define REG_INT_EN=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0=C2=A0 (0x000C) /* Interrupt Enable */ >> +#define REG_TX_CTL_0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0 (0x0010) /* Transmit Control 0 */ >> +#define REG_TX_CTL_1=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0 (0x0014) /* Transmit Control 1 */ >> +#define REG_TX_FLOW_CTL=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 (0x00= 1C) /* Transmit Flow Control */ >> +#define REG_TX_DMA_DESC_LIST=C2=A0=C2=A0 (0x0020) /* Transmit Descripto= r List=20 >> Address */ >> +#define REG_RX_CTL_0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0 (0x0024) /* Receive Control 0 */ >> +#define REG_RX_CTL_1=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0 (0x0028) /* Receive Control 1 */ >> +#define REG_RX_DMA_DESC_LIST=C2=A0=C2=A0 (0x0034) /* Receive Descriptor= List=20 >> Address */ >> +#define REG_FRM_FLT=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0 (0x0038) /* Receive Frame Filter */ >> +#define REG_RX_HASH_0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0 (0x0040) /* Receive Hash Table 0 */ >> +#define REG_RX_HASH_1=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0 (0x0044) /* Receive Hash Table 1 */ >> +#define REG_MII_CMD=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0 (0x0048) /* Management Interface=20 >> Command */ >> +#define REG_MII_DATA=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0 (0x004C) /* Management Interface Data */ >> +#define REG_ADDR_HIGH=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0 (0x0050) /* MAC Address High */ >> +#define REG_ADDR_LOW=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0 (0x0054) /* MAC Address Low */ >> +#define REG_TX_DMA_STA=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 = (0x00B0) /* Transmit DMA Status */ >> +#define REG_TX_CUR_DESC=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 (0x00= B4) /* Transmit Current=20 >> Descriptor */ >> +#define REG_TX_CUR_BUF=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 = (0x00B8) /* Transmit Current Buffer */ >> +#define REG_RX_DMA_STA=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 = (0x00C0) /* Receive DMA Status */ >> +#define REG_RX_CUR_DESC=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 (0x00= C4) /* Receive Current Descriptor */ >> +#define REG_RX_CUR_BUF=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 = (0x00C8) /* Receive Current Buffer */ >> +#define REG_RGMII_STA=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0 (0x00D0) /* RGMII Status */ >> + >> +/* EMAC register flags */ >> +#define BASIC_CTL0_100Mbps=C2=A0=C2=A0=C2=A0=C2=A0 (0b11 << 2) >> +#define BASIC_CTL0_FD=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0 (1 << 0) >> +#define BASIC_CTL1_SOFTRST=C2=A0=C2=A0=C2=A0=C2=A0 (1 << 0) >> + >> +#define INT_STA_RGMII_LINK=C2=A0=C2=A0=C2=A0=C2=A0 (1 << 16) >> +#define INT_STA_RX_EARLY=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 (1 << 13) >> +#define INT_STA_RX_OVERFLOW=C2=A0=C2=A0=C2=A0 (1 << 12) >> +#define INT_STA_RX_TIMEOUT=C2=A0=C2=A0=C2=A0=C2=A0 (1 << 11) >> +#define INT_STA_RX_DMA_STOP=C2=A0=C2=A0=C2=A0 (1 << 10) >> +#define INT_STA_RX_BUF_UA=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 (1 << 9) >> +#define INT_STA_RX=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0=C2=A0 (1 << 8) >> +#define INT_STA_TX_EARLY=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 (1 << 5) >> +#define INT_STA_TX_UNDERFLOW=C2=A0=C2=A0 (1 << 4) >> +#define INT_STA_TX_TIMEOUT=C2=A0=C2=A0=C2=A0=C2=A0 (1 << 3) >> +#define INT_STA_TX_BUF_UA=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 (1 << 2) >> +#define INT_STA_TX_DMA_STOP=C2=A0=C2=A0=C2=A0 (1 << 1) >> +#define INT_STA_TX=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0=C2=A0 (1 << 0) >> + >> +#define INT_EN_RX_EARLY=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 (1 <<= 13) >> +#define INT_EN_RX_OVERFLOW=C2=A0=C2=A0=C2=A0=C2=A0 (1 << 12) >> +#define INT_EN_RX_TIMEOUT=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 (1 << 11) >> +#define INT_EN_RX_DMA_STOP=C2=A0=C2=A0=C2=A0=C2=A0 (1 << 10) >> +#define INT_EN_RX_BUF_UA=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 (1 << 9) >> +#define INT_EN_RX=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0=C2=A0=C2=A0 (1 << 8) >> +#define INT_EN_TX_EARLY=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 (1 <<= 5) >> +#define INT_EN_TX_UNDERFLOW=C2=A0=C2=A0=C2=A0 (1 << 4) >> +#define INT_EN_TX_TIMEOUT=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 (1 << 3) >> +#define INT_EN_TX_BUF_UA=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 (1 << 2) >> +#define INT_EN_TX_DMA_STOP=C2=A0=C2=A0=C2=A0=C2=A0 (1 << 1) >> +#define INT_EN_TX=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0=C2=A0=C2=A0 (1 << 0) >> + >> +#define TX_CTL0_TX_EN=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0 (1 << 31) >> +#define TX_CTL1_TX_DMA_START=C2=A0=C2=A0 (1 << 31) >> +#define TX_CTL1_TX_DMA_EN=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 (1 << 30) >> +#define TX_CTL1_TX_FLUSH=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 (1 << 0) >> + >> +#define RX_CTL0_RX_EN=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0 (1 << 31) >> +#define RX_CTL0_STRIP_FCS=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 (1 << 28) >> +#define RX_CTL0_CRC_IPV4=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 (1 << 27) >> + >> +#define RX_CTL1_RX_DMA_START=C2=A0=C2=A0 (1 << 31) >> +#define RX_CTL1_RX_DMA_EN=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 (1 << 30) >> +#define RX_CTL1_RX_MD=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0 (1 << 1) >> + >> +#define RX_FRM_FLT_DIS_ADDR=C2=A0=C2=A0=C2=A0 (1 << 31) >> + >> +#define MII_CMD_PHY_ADDR_SHIFT (12) >> +#define MII_CMD_PHY_ADDR_MASK=C2=A0 (0xf000) >> +#define MII_CMD_PHY_REG_SHIFT=C2=A0 (4) >> +#define MII_CMD_PHY_REG_MASK=C2=A0=C2=A0 (0xf0) >> +#define MII_CMD_PHY_RW=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 = (1 << 1) >> +#define MII_CMD_PHY_BUSY=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 (1 << 0) >> + >> +#define TX_DMA_STA_STOP=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 (0b00= 0) >> +#define TX_DMA_STA_RUN_FETCH=C2=A0=C2=A0 (0b001) >> +#define TX_DMA_STA_WAIT_STA=C2=A0=C2=A0=C2=A0 (0b010) >> + >> +#define RX_DMA_STA_STOP=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 (0b00= 0) >> +#define RX_DMA_STA_RUN_FETCH=C2=A0=C2=A0 (0b001) >> +#define RX_DMA_STA_WAIT_FRM=C2=A0=C2=A0=C2=A0 (0b011) >> + >> +#define RGMII_LINK_UP=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0 (1 << 3) >> +#define RGMII_FD=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 (1 << 0) >> + >> +/* EMAC register reset values */ >> +#define REG_BASIC_CTL_1_RST=C2=A0=C2=A0=C2=A0 (0x08000000) >> + >> +/* EMAC constants */ >> +#define AW_H3_EMAC_MIN_PKT_SZ=C2=A0 (64) >> + >> +/* Transmit/receive frame descriptor */ >> +typedef struct FrameDescriptor { >> +=C2=A0=C2=A0=C2=A0 uint32_t status; >> +=C2=A0=C2=A0=C2=A0 uint32_t status2; >> +=C2=A0=C2=A0=C2=A0 uint32_t addr; >> +=C2=A0=C2=A0=C2=A0 uint32_t next; >> +} FrameDescriptor; >> + >> +/* Frame descriptor flags */ >> +#define DESC_STATUS_CTL=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 (1 << 31) >> +#define DESC_STATUS2_BUF_SIZE_MASK=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 (0x7ff= ) >> + >> +/* Transmit frame descriptor flags */ >> +#define TX_DESC_STATUS_LENGTH_ERR=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 (= 1 << 14) >> +#define TX_DESC_STATUS2_FIRST_DESC=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 (1 << = 29) >> +#define TX_DESC_STATUS2_LAST_DESC=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 (= 1 << 30) >> +#define TX_DESC_STATUS2_CHECKSUM_MASK=C2=A0=C2=A0 (0x3 << 27) >> + >> +/* Receive frame descriptor flags */ >> +#define RX_DESC_STATUS_FIRST_DESC=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 (= 1 << 9) >> +#define RX_DESC_STATUS_LAST_DESC=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0 (1 << 8) >> +#define RX_DESC_STATUS_FRM_LEN_MASK=C2=A0=C2=A0=C2=A0=C2=A0 (0x3fff0000= ) >> +#define RX_DESC_STATUS_FRM_LEN_SHIFT=C2=A0=C2=A0=C2=A0 (16) >> +#define RX_DESC_STATUS_NO_BUF=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0=C2=A0 (1 << 14) >> +#define RX_DESC_STATUS_HEADER_ERR=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 (= 1 << 7) >> +#define RX_DESC_STATUS_LENGTH_ERR=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 (= 1 << 4) >> +#define RX_DESC_STATUS_CRC_ERR=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0 (1 << 1) >> +#define RX_DESC_STATUS_PAYLOAD_ERR=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 (1 << = 0) >> +#define RX_DESC_STATUS2_RX_INT_CTL=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 (1 << = 31) >> + >> +/* MII register offsets */ >> +#define MII_REG_CR=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= (0x0) >> +#define MII_REG_ST=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= (0x1) >> +#define MII_REG_ID_HIGH=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 (0x2) >> +#define MII_REG_ID_LOW=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 (0x3) >> + >> +/* MII register flags */ >> +#define MII_REG_CR_RESET=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 (1 << 15) >> +#define MII_REG_CR_POWERDOWN=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0=C2=A0=C2=A0 (1 << 11) >> +#define MII_REG_CR_10Mbit=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 (0) >> +#define MII_REG_CR_100Mbit=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 (1 << 13) >> +#define MII_REG_CR_1000Mbit=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 (1 << 6) >> +#define MII_REG_CR_AUTO_NEG=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 (1 << 12) >> +#define MII_REG_CR_AUTO_NEG_RESTART=C2=A0=C2=A0=C2=A0=C2=A0 (1 << 9) >> +#define MII_REG_CR_FULLDUPLEX=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0=C2=A0 (1 << 8) >> + >> +#define MII_REG_ST_100BASE_T4=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0=C2=A0 (1 << 15) >> +#define MII_REG_ST_100BASE_X_FD=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0 (1 << 14) >> +#define MII_REG_ST_100BASE_X_HD=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0 (1 << 13) >> +#define MII_REG_ST_10_FD=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 (1 << 12) >> +#define MII_REG_ST_10_HD=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 (1 << 11) >> +#define MII_REG_ST_100BASE_T2_FD=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0 (1 << 10) >> +#define MII_REG_ST_100BASE_T2_HD=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0 (1 << 9) >> +#define MII_REG_ST_AUTONEG_COMPLETE=C2=A0=C2=A0=C2=A0=C2=A0 (1 << 5) >> +#define MII_REG_ST_AUTONEG_AVAIL=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0 (1 << 3) >> +#define MII_REG_ST_LINK_UP=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 (1 << 2) >> + >> +/* MII constants */ >> +#define MII_PHY_ID_HIGH=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 (0x0044) >> +#define MII_PHY_ID_LOW=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 (0x1400) >=20 > I wonder if we can't share all those mii stuff accross the network adapte= rs > instead of redoing the work everytime. I've some patches about it I may= =20 > post > them sometimes. I started that too, salvaging patches from Grant Likely and Sai Pavan=20 Boddu, but I'm doing this in my hobbyist time so progress is slow. I=20 estimate I'v 80% of the work done. Basically it adds a MDIO QBUS (as SD/I2C) and we can plug multiple QDEV=20 slaves. Benefits are easily tracing of the MDIO activity, and ability to=20 interchange the master/slaves for testing (think libqos qgraph). From MAILER-DAEMON Wed Dec 04 10:22:52 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1icWUO-0003jm-0k for mharc-qemu-arm@gnu.org; Wed, 04 Dec 2019 10:22:52 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:51093) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1icWUK-0003ja-Cn for qemu-arm@nongnu.org; Wed, 04 Dec 2019 10:22:50 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1icWUI-0008Cu-5n for qemu-arm@nongnu.org; Wed, 04 Dec 2019 10:22:48 -0500 Received: from mel.act-europe.fr ([194.98.77.210]:47418 helo=smtp.eu.adacore.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1icWUH-0008CA-SE; Wed, 04 Dec 2019 10:22:46 -0500 Received: from localhost (localhost [127.0.0.1]) by filtered-smtp.eu.adacore.com (Postfix) with ESMTP id 09BD181387; Wed, 4 Dec 2019 16:22:43 +0100 (CET) X-Virus-Scanned: Debian amavisd-new at eu.adacore.com Received: from smtp.eu.adacore.com ([127.0.0.1]) by localhost (smtp.eu.adacore.com [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id cYHIzmlfooSm; Wed, 4 Dec 2019 16:22:42 +0100 (CET) Received: from localhost.localdomain (lfbn-tou-1-352-33.w86-206.abo.wanadoo.fr [86.206.184.33]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.eu.adacore.com (Postfix) with ESMTPSA id 93DA281382; Wed, 4 Dec 2019 16:22:40 +0100 (CET) Subject: Re: [PATCH 10/10] arm: allwinner-h3: add EMAC ethernet device To: =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= , Niek Linnenbank , qemu-devel@nongnu.org Cc: b.galvani@gmail.com, peter.maydell@linaro.org, qemu-arm@nongnu.org, Sai Pavan Boddu , Sven Schnelle , Grant Likely , Paolo Bonzini , Jason Wang References: <20191202210947.3603-1-nieklinnenbank@gmail.com> <20191202210947.3603-11-nieklinnenbank@gmail.com> <0b549e25-cf45-e491-9342-58592514870f@redhat.com> From: KONRAD Frederic Message-ID: Date: Wed, 4 Dec 2019 16:22:38 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101 Thunderbird/60.9.1 MIME-Version: 1.0 In-Reply-To: <0b549e25-cf45-e491-9342-58592514870f@redhat.com> Content-Type: text/plain; charset=utf-8; format=flowed Content-Language: fr Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [fuzzy] X-Received-From: 194.98.77.210 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 04 Dec 2019 15:22:50 -0000 Le 12/4/19 =C3=A0 4:14 PM, Philippe Mathieu-Daud=C3=A9 a =C3=A9crit=C2=A0= : > On 12/3/19 10:33 AM, KONRAD Frederic wrote: >> Le 12/2/19 =C3=A0 10:09 PM, Niek Linnenbank a =C3=A9crit=C2=A0: >>> The Allwinner H3 System on Chip includes an Ethernet MAC (EMAC) >>> which provides 10M/100M/1000M Ethernet connectivity. This commit >>> adds support for the Allwinner H3 EMAC, including emulation for >>> the following functionality: >>> >>> =C2=A0 * DMA transfers >>> =C2=A0 * MII interface >>> =C2=A0 * Transmit CRC calculation >>> >>> Signed-off-by: Niek Linnenbank >>> --- >>> =C2=A0 hw/arm/Kconfig=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 = |=C2=A0=C2=A0 1 + >>> =C2=A0 hw/arm/allwinner-h3.c=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 |=C2=A0 17 + >>> =C2=A0 hw/arm/orangepi.c=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 |=C2=A0=C2=A0 7= + >>> =C2=A0 hw/net/Kconfig=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 = |=C2=A0=C2=A0 3 + >>> =C2=A0 hw/net/Makefile.objs=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 |=C2=A0=C2=A0 1 + >>> =C2=A0 hw/net/allwinner-h3-emac.c=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0 | 786 +++++++++++++++++++++++++++++ >>> =C2=A0 hw/net/trace-events=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 |=C2=A0 10 + >>> =C2=A0 include/hw/arm/allwinner-h3.h=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 |=C2= =A0=C2=A0 2 + >>> =C2=A0 include/hw/net/allwinner-h3-emac.h |=C2=A0 69 +++ >>> =C2=A0 9 files changed, 896 insertions(+) >>> =C2=A0 create mode 100644 hw/net/allwinner-h3-emac.c >>> =C2=A0 create mode 100644 include/hw/net/allwinner-h3-emac.h >>> >>> diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig >>> index ebf8d2325f..551cff3442 100644 >>> --- a/hw/arm/Kconfig >>> +++ b/hw/arm/Kconfig >>> @@ -294,6 +294,7 @@ config ALLWINNER_A10 >>> =C2=A0 config ALLWINNER_H3 >>> =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 bool >>> =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 select ALLWINNER_A10_PIT >>> +=C2=A0=C2=A0=C2=A0 select ALLWINNER_H3_EMAC >>> =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 select SERIAL >>> =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 select ARM_TIMER >>> =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 select ARM_GIC >>> diff --git a/hw/arm/allwinner-h3.c b/hw/arm/allwinner-h3.c >>> index c2972caf88..274b8548c0 100644 >>> --- a/hw/arm/allwinner-h3.c >>> +++ b/hw/arm/allwinner-h3.c >>> @@ -53,6 +53,9 @@ static void aw_h3_init(Object *obj) >>> =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 sysbus_init_child_obj(obj, "mmc0", &s-= >mmc0, sizeof(s->mmc0), >>> =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0=C2=A0 TYPE_AW_H3_SDHOST); >>> + >>> +=C2=A0=C2=A0=C2=A0 sysbus_init_child_obj(obj, "emac", &s->emac, size= of(s->emac), >>> +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0 TYPE_AW_H3_EMAC); >>> =C2=A0 } >>> =C2=A0 static void aw_h3_realize(DeviceState *dev, Error **errp) >>> @@ -237,6 +240,20 @@ static void aw_h3_realize(DeviceState *dev, Erro= r **errp) >>> =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 return; >>> =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 } >>> +=C2=A0=C2=A0=C2=A0 /* EMAC */ >>> +=C2=A0=C2=A0=C2=A0 if (nd_table[0].used) { >>> +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 qemu_check_nic_model(&nd_= table[0], TYPE_AW_H3_EMAC); >>> +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 qdev_set_nic_properties(D= EVICE(&s->emac), &nd_table[0]); >>> +=C2=A0=C2=A0=C2=A0 } >>> +=C2=A0=C2=A0=C2=A0 object_property_set_bool(OBJECT(&s->emac), true, = "realized", &err); >>> +=C2=A0=C2=A0=C2=A0 if (err !=3D NULL) { >>> +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 error_propagate(errp, err= ); >>> +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 return; >>> +=C2=A0=C2=A0=C2=A0 } >>> +=C2=A0=C2=A0=C2=A0 sysbusdev =3D SYS_BUS_DEVICE(&s->emac); >>> +=C2=A0=C2=A0=C2=A0 sysbus_mmio_map(sysbusdev, 0, AW_H3_EMAC_BASE); >>> +=C2=A0=C2=A0=C2=A0 sysbus_connect_irq(sysbusdev, 0, s->irq[AW_H3_GIC= _SPI_EMAC]); >>> + >>> =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 /* Universal Serial Bus */ >>> =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 sysbus_create_simple(TYPE_AW_H3_EHCI, = AW_H3_EHCI0_BASE, >>> =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0 s->irq[AW_H3_GIC_SPI_EHCI0]); >>> diff --git a/hw/arm/orangepi.c b/hw/arm/orangepi.c >>> index dee3efaf08..8a61eb0e69 100644 >>> --- a/hw/arm/orangepi.c >>> +++ b/hw/arm/orangepi.c >>> @@ -61,6 +61,13 @@ static void orangepi_init(MachineState *machine) >>> =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 exit(1); >>> =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 } >>> +=C2=A0=C2=A0=C2=A0 /* Setup EMAC properties */ >>> +=C2=A0=C2=A0=C2=A0 object_property_set_int(OBJECT(&s->h3->emac), 1, = "phy-addr", &err); >>> +=C2=A0=C2=A0=C2=A0 if (err !=3D NULL) { >>> +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 error_reportf_err(err, "C= ouldn't set phy address: "); >>> +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 exit(1); >>> +=C2=A0=C2=A0=C2=A0 } >>> + >>> =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 /* Mark H3 object realized */ >>> =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 object_property_set_bool(OBJECT(s->h3)= , true, "realized", &err); >>> =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 if (err !=3D NULL) { >>> diff --git a/hw/net/Kconfig b/hw/net/Kconfig >>> index 3856417d42..36d3923992 100644 >>> --- a/hw/net/Kconfig >>> +++ b/hw/net/Kconfig >>> @@ -74,6 +74,9 @@ config MIPSNET >>> =C2=A0 config ALLWINNER_EMAC >>> =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 bool >>> +config ALLWINNER_H3_EMAC >>> +=C2=A0=C2=A0=C2=A0 bool >>> + >>> =C2=A0 config IMX_FEC >>> =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 bool >>> diff --git a/hw/net/Makefile.objs b/hw/net/Makefile.objs >>> index 7907d2c199..5548deb07a 100644 >>> --- a/hw/net/Makefile.objs >>> +++ b/hw/net/Makefile.objs >>> @@ -23,6 +23,7 @@ common-obj-$(CONFIG_XGMAC) +=3D xgmac.o >>> =C2=A0 common-obj-$(CONFIG_MIPSNET) +=3D mipsnet.o >>> =C2=A0 common-obj-$(CONFIG_XILINX_AXI) +=3D xilinx_axienet.o >>> =C2=A0 common-obj-$(CONFIG_ALLWINNER_EMAC) +=3D allwinner_emac.o >>> +common-obj-$(CONFIG_ALLWINNER_H3_EMAC) +=3D allwinner-h3-emac.o >>> =C2=A0 common-obj-$(CONFIG_IMX_FEC) +=3D imx_fec.o >>> =C2=A0 common-obj-$(CONFIG_CADENCE) +=3D cadence_gem.o >>> diff --git a/hw/net/allwinner-h3-emac.c b/hw/net/allwinner-h3-emac.c >>> new file mode 100644 >>> index 0000000000..37f6f44406 >>> --- /dev/null >>> +++ b/hw/net/allwinner-h3-emac.c >>> @@ -0,0 +1,786 @@ >>> +/* >>> + * Allwinner H3 EMAC emulation >>> + * >>> + * Copyright (C) 2019 Niek Linnenbank >>> + * >>> + * This program is free software: you can redistribute it and/or mod= ify >>> + * it under the terms of the GNU General Public License as published= by >>> + * the Free Software Foundation, either version 2 of the License, or >>> + * (at your option) any later version. >>> + * >>> + * This program is distributed in the hope that it will be useful, >>> + * but WITHOUT ANY WARRANTY; without even the implied warranty of >>> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.=C2=A0 See th= e >>> + * GNU General Public License for more details. >>> + * >>> + * You should have received a copy of the GNU General Public License >>> + * along with this program.=C2=A0 If not, see . >>> + */ >>> + >>> +#include "qemu/osdep.h" >>> +#include "hw/sysbus.h" >>> +#include "migration/vmstate.h" >>> +#include "net/net.h" >>> +#include "hw/irq.h" >>> +#include "hw/qdev-properties.h" >>> +#include "qemu/log.h" >>> +#include "trace.h" >>> +#include "net/checksum.h" >>> +#include "qemu/module.h" >>> +#include "exec/cpu-common.h" >>> +#include "hw/net/allwinner-h3-emac.h" >>> + >>> +/* EMAC register offsets */ >>> +#define REG_BASIC_CTL_0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 (0= x0000) /* Basic Control 0 */ >>> +#define REG_BASIC_CTL_1=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 (0= x0004) /* Basic Control 1 */ >>> +#define REG_INT_STA=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0 (0x0008) /* Interrupt Status */ >>> +#define REG_INT_EN=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0=C2=A0 (0x000C) /* Interrupt Enable */ >>> +#define REG_TX_CTL_0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0 (0x0010) /* Transmit Control 0 */ >>> +#define REG_TX_CTL_1=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0 (0x0014) /* Transmit Control 1 */ >>> +#define REG_TX_FLOW_CTL=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 (0= x001C) /* Transmit Flow Control */ >>> +#define REG_TX_DMA_DESC_LIST=C2=A0=C2=A0 (0x0020) /* Transmit Descri= ptor List Address */ >>> +#define REG_RX_CTL_0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0 (0x0024) /* Receive Control 0 */ >>> +#define REG_RX_CTL_1=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0 (0x0028) /* Receive Control 1 */ >>> +#define REG_RX_DMA_DESC_LIST=C2=A0=C2=A0 (0x0034) /* Receive Descrip= tor List Address */ >>> +#define REG_FRM_FLT=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0 (0x0038) /* Receive Frame Filter */ >>> +#define REG_RX_HASH_0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0 (0x0040) /* Receive Hash Table 0 */ >>> +#define REG_RX_HASH_1=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0 (0x0044) /* Receive Hash Table 1 */ >>> +#define REG_MII_CMD=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0 (0x0048) /* Management Interface Command */ >>> +#define REG_MII_DATA=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0 (0x004C) /* Management Interface Data */ >>> +#define REG_ADDR_HIGH=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0 (0x0050) /* MAC Address High */ >>> +#define REG_ADDR_LOW=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0 (0x0054) /* MAC Address Low */ >>> +#define REG_TX_DMA_STA=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= (0x00B0) /* Transmit DMA Status */ >>> +#define REG_TX_CUR_DESC=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 (0= x00B4) /* Transmit Current Descriptor */ >>> +#define REG_TX_CUR_BUF=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= (0x00B8) /* Transmit Current Buffer */ >>> +#define REG_RX_DMA_STA=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= (0x00C0) /* Receive DMA Status */ >>> +#define REG_RX_CUR_DESC=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 (0= x00C4) /* Receive Current Descriptor */ >>> +#define REG_RX_CUR_BUF=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= (0x00C8) /* Receive Current Buffer */ >>> +#define REG_RGMII_STA=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0 (0x00D0) /* RGMII Status */ >>> + >>> +/* EMAC register flags */ >>> +#define BASIC_CTL0_100Mbps=C2=A0=C2=A0=C2=A0=C2=A0 (0b11 << 2) >>> +#define BASIC_CTL0_FD=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0 (1 << 0) >>> +#define BASIC_CTL1_SOFTRST=C2=A0=C2=A0=C2=A0=C2=A0 (1 << 0) >>> + >>> +#define INT_STA_RGMII_LINK=C2=A0=C2=A0=C2=A0=C2=A0 (1 << 16) >>> +#define INT_STA_RX_EARLY=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 (1 << 1= 3) >>> +#define INT_STA_RX_OVERFLOW=C2=A0=C2=A0=C2=A0 (1 << 12) >>> +#define INT_STA_RX_TIMEOUT=C2=A0=C2=A0=C2=A0=C2=A0 (1 << 11) >>> +#define INT_STA_RX_DMA_STOP=C2=A0=C2=A0=C2=A0 (1 << 10) >>> +#define INT_STA_RX_BUF_UA=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 (1 << 9) >>> +#define INT_STA_RX=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0=C2=A0 (1 << 8) >>> +#define INT_STA_TX_EARLY=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 (1 << 5= ) >>> +#define INT_STA_TX_UNDERFLOW=C2=A0=C2=A0 (1 << 4) >>> +#define INT_STA_TX_TIMEOUT=C2=A0=C2=A0=C2=A0=C2=A0 (1 << 3) >>> +#define INT_STA_TX_BUF_UA=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 (1 << 2) >>> +#define INT_STA_TX_DMA_STOP=C2=A0=C2=A0=C2=A0 (1 << 1) >>> +#define INT_STA_TX=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0=C2=A0 (1 << 0) >>> + >>> +#define INT_EN_RX_EARLY=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 (1= << 13) >>> +#define INT_EN_RX_OVERFLOW=C2=A0=C2=A0=C2=A0=C2=A0 (1 << 12) >>> +#define INT_EN_RX_TIMEOUT=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 (1 << 11) >>> +#define INT_EN_RX_DMA_STOP=C2=A0=C2=A0=C2=A0=C2=A0 (1 << 10) >>> +#define INT_EN_RX_BUF_UA=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 (1 << 9= ) >>> +#define INT_EN_RX=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0=C2=A0=C2=A0 (1 << 8) >>> +#define INT_EN_TX_EARLY=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 (1= << 5) >>> +#define INT_EN_TX_UNDERFLOW=C2=A0=C2=A0=C2=A0 (1 << 4) >>> +#define INT_EN_TX_TIMEOUT=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 (1 << 3) >>> +#define INT_EN_TX_BUF_UA=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 (1 << 2= ) >>> +#define INT_EN_TX_DMA_STOP=C2=A0=C2=A0=C2=A0=C2=A0 (1 << 1) >>> +#define INT_EN_TX=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0=C2=A0=C2=A0 (1 << 0) >>> + >>> +#define TX_CTL0_TX_EN=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0 (1 << 31) >>> +#define TX_CTL1_TX_DMA_START=C2=A0=C2=A0 (1 << 31) >>> +#define TX_CTL1_TX_DMA_EN=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 (1 << 30) >>> +#define TX_CTL1_TX_FLUSH=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 (1 << 0= ) >>> + >>> +#define RX_CTL0_RX_EN=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0 (1 << 31) >>> +#define RX_CTL0_STRIP_FCS=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 (1 << 28) >>> +#define RX_CTL0_CRC_IPV4=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 (1 << 2= 7) >>> + >>> +#define RX_CTL1_RX_DMA_START=C2=A0=C2=A0 (1 << 31) >>> +#define RX_CTL1_RX_DMA_EN=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 (1 << 30) >>> +#define RX_CTL1_RX_MD=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0 (1 << 1) >>> + >>> +#define RX_FRM_FLT_DIS_ADDR=C2=A0=C2=A0=C2=A0 (1 << 31) >>> + >>> +#define MII_CMD_PHY_ADDR_SHIFT (12) >>> +#define MII_CMD_PHY_ADDR_MASK=C2=A0 (0xf000) >>> +#define MII_CMD_PHY_REG_SHIFT=C2=A0 (4) >>> +#define MII_CMD_PHY_REG_MASK=C2=A0=C2=A0 (0xf0) >>> +#define MII_CMD_PHY_RW=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= (1 << 1) >>> +#define MII_CMD_PHY_BUSY=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 (1 << 0= ) >>> + >>> +#define TX_DMA_STA_STOP=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 (0= b000) >>> +#define TX_DMA_STA_RUN_FETCH=C2=A0=C2=A0 (0b001) >>> +#define TX_DMA_STA_WAIT_STA=C2=A0=C2=A0=C2=A0 (0b010) >>> + >>> +#define RX_DMA_STA_STOP=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 (0= b000) >>> +#define RX_DMA_STA_RUN_FETCH=C2=A0=C2=A0 (0b001) >>> +#define RX_DMA_STA_WAIT_FRM=C2=A0=C2=A0=C2=A0 (0b011) >>> + >>> +#define RGMII_LINK_UP=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0 (1 << 3) >>> +#define RGMII_FD=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 (1 << 0) >>> + >>> +/* EMAC register reset values */ >>> +#define REG_BASIC_CTL_1_RST=C2=A0=C2=A0=C2=A0 (0x08000000) >>> + >>> +/* EMAC constants */ >>> +#define AW_H3_EMAC_MIN_PKT_SZ=C2=A0 (64) >>> + >>> +/* Transmit/receive frame descriptor */ >>> +typedef struct FrameDescriptor { >>> +=C2=A0=C2=A0=C2=A0 uint32_t status; >>> +=C2=A0=C2=A0=C2=A0 uint32_t status2; >>> +=C2=A0=C2=A0=C2=A0 uint32_t addr; >>> +=C2=A0=C2=A0=C2=A0 uint32_t next; >>> +} FrameDescriptor; >>> + >>> +/* Frame descriptor flags */ >>> +#define DESC_STATUS_CTL=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 (1 << 31) >>> +#define DESC_STATUS2_BUF_SIZE_MASK=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 (0x= 7ff) >>> + >>> +/* Transmit frame descriptor flags */ >>> +#define TX_DESC_STATUS_LENGTH_ERR=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= (1 << 14) >>> +#define TX_DESC_STATUS2_FIRST_DESC=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 (1 = << 29) >>> +#define TX_DESC_STATUS2_LAST_DESC=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= (1 << 30) >>> +#define TX_DESC_STATUS2_CHECKSUM_MASK=C2=A0=C2=A0 (0x3 << 27) >>> + >>> +/* Receive frame descriptor flags */ >>> +#define RX_DESC_STATUS_FIRST_DESC=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= (1 << 9) >>> +#define RX_DESC_STATUS_LAST_DESC=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0 (1 << 8) >>> +#define RX_DESC_STATUS_FRM_LEN_MASK=C2=A0=C2=A0=C2=A0=C2=A0 (0x3fff0= 000) >>> +#define RX_DESC_STATUS_FRM_LEN_SHIFT=C2=A0=C2=A0=C2=A0 (16) >>> +#define RX_DESC_STATUS_NO_BUF=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0=C2=A0 (1 << 14) >>> +#define RX_DESC_STATUS_HEADER_ERR=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= (1 << 7) >>> +#define RX_DESC_STATUS_LENGTH_ERR=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= (1 << 4) >>> +#define RX_DESC_STATUS_CRC_ERR=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0 (1 << 1) >>> +#define RX_DESC_STATUS_PAYLOAD_ERR=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 (1 = << 0) >>> +#define RX_DESC_STATUS2_RX_INT_CTL=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 (1 = << 31) >>> + >>> +/* MII register offsets */ >>> +#define MII_REG_CR=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= (0x0) >>> +#define MII_REG_ST=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= (0x1) >>> +#define MII_REG_ID_HIGH=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 (0x2) >>> +#define MII_REG_ID_LOW=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 (0x3) >>> + >>> +/* MII register flags */ >>> +#define MII_REG_CR_RESET=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 (1 << 15) >>> +#define MII_REG_CR_POWERDOWN=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0=C2=A0=C2=A0 (1 << 11) >>> +#define MII_REG_CR_10Mbit=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 (0) >>> +#define MII_REG_CR_100Mbit=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 (1 << 13) >>> +#define MII_REG_CR_1000Mbit=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 (1 << 6) >>> +#define MII_REG_CR_AUTO_NEG=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 (1 << 12) >>> +#define MII_REG_CR_AUTO_NEG_RESTART=C2=A0=C2=A0=C2=A0=C2=A0 (1 << 9) >>> +#define MII_REG_CR_FULLDUPLEX=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0=C2=A0 (1 << 8) >>> + >>> +#define MII_REG_ST_100BASE_T4=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0=C2=A0 (1 << 15) >>> +#define MII_REG_ST_100BASE_X_FD=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0 (1 << 14) >>> +#define MII_REG_ST_100BASE_X_HD=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0 (1 << 13) >>> +#define MII_REG_ST_10_FD=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 (1 << 12) >>> +#define MII_REG_ST_10_HD=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 (1 << 11) >>> +#define MII_REG_ST_100BASE_T2_FD=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0 (1 << 10) >>> +#define MII_REG_ST_100BASE_T2_HD=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0 (1 << 9) >>> +#define MII_REG_ST_AUTONEG_COMPLETE=C2=A0=C2=A0=C2=A0=C2=A0 (1 << 5) >>> +#define MII_REG_ST_AUTONEG_AVAIL=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0 (1 << 3) >>> +#define MII_REG_ST_LINK_UP=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 (1 << 2) >>> + >>> +/* MII constants */ >>> +#define MII_PHY_ID_HIGH=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 (0x0044) >>> +#define MII_PHY_ID_LOW=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 (0x1400) >> >> I wonder if we can't share all those mii stuff accross the network ada= pters >> instead of redoing the work everytime. I've some patches about it I ma= y post >> them sometimes. >=20 > I started that too, salvaging patches from Grant Likely and Sai Pavan B= oddu, but=20 > I'm doing this in my hobbyist time so progress is slow. I estimate I'v = 80% of=20 > the work done. > Basically it adds a MDIO QBUS (as SD/I2C) and we can plug multiple QDEV= slaves.=20 > Benefits are easily tracing of the MDIO activity, and ability to interc= hange the=20 > master/slaves for testing (think libqos qgraph). >=20 Interesting! I didn't go that far though. The ability to change the devic= e ID and not rewriting those registers for every network adapters is suffic= ient for me :). From MAILER-DAEMON Wed Dec 04 11:12:07 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1icXFw-0005Ap-2L for mharc-qemu-arm@gnu.org; Wed, 04 Dec 2019 11:12:04 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:60531) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1icXFh-00056j-H8 for qemu-arm@nongnu.org; Wed, 04 Dec 2019 11:11:51 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1icXFd-0004EK-Aa for qemu-arm@nongnu.org; Wed, 04 Dec 2019 11:11:44 -0500 Received: from mail-oi1-x242.google.com ([2607:f8b0:4864:20::242]:41919) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1icXFU-00046f-A2; Wed, 04 Dec 2019 11:11:32 -0500 Received: by mail-oi1-x242.google.com with SMTP id i1so3261594oie.8; Wed, 04 Dec 2019 08:11:30 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=mime-version:in-reply-to:references:from:date:message-id:subject:to :cc; bh=5t/1v78hE6NyJ3o2GpUTU1gSeku0E4UCR1wVphzXSp8=; b=f5sesb5YnQ/z44M/W65klN3FzjaV2vupsX7HXvjF42WsFP2WRlxPtBurWsKdCXz5gQ VUZXTfBX4GTKlJT2h7zDnng7XrbfCXp1euLhsD02j4nMongOw4oGOEp8hG+Jed4iszW9 6wkclceNxBackjQq4kw/0FQ5UUox7MpnPWWevcRan+xdrRXA49FzHqXTDOQzD294aZa3 +62A1m3HX32X3M11aU9G0WMal4nD06/lDh2+V5MFCcOx+PBm2thi3Gq8+6pqOF7yu13+ V0HN704Muph5q2grlhjLvJhCg6pWC9M6yd6l4aza11FhVZm4pxbWjkNLX4mLRTi7fdF6 jcyw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:in-reply-to:references:from:date :message-id:subject:to:cc; bh=5t/1v78hE6NyJ3o2GpUTU1gSeku0E4UCR1wVphzXSp8=; b=N7bVXmk6+WJw9okT6sz+vNfQaBZbAbO/8/BKTEtXjpeTxhFmtOGUQzD4rF+cxwL2eA Vku7c/y4agwCejTwWR4YJLcKUZmnujZU2n7HKIviE9UZ8HnV7VGYq+t+3b7KVm7avXAj p9vTMIrg3NCQTonHUaCzWL5j1q3LCKLdf2z38YviXH0eKCGpXXzvJgN0CcbwWRWuw4fM fMXo8xDrv1VpN3ziVVE8PH+htLGDKv81dJjRGNK+LiBaxahajJ361LkdgUqBwcREgaJg 6kROSC8UCPaMrGQ1F6H2muOBiyQx7LWbG5rd8nwvrgeGkA7ORx9FgAZXqDz6vrtgGB1Q rsPw== X-Gm-Message-State: APjAAAUuv+ThB9HlzpYP/joMM/xVapnP/fl3/sOOBREItgveXYeuy3g2 teSnN2lKL2tA7OPiUm/HJ9+FHVSh1cM3aoss1GI= X-Google-Smtp-Source: APXvYqxUZ+jAdcGPjbecPw/g/WVBwmdylJiyeCZdznfJTk6fYWitEvneN5+muUyYDSY3GCoYDgamylautUTMMnrXFVw= X-Received: by 2002:aca:bd85:: with SMTP id n127mr3267748oif.136.1575475889777; Wed, 04 Dec 2019 08:11:29 -0800 (PST) MIME-Version: 1.0 Received: by 2002:a9d:d21:0:0:0:0:0 with HTTP; Wed, 4 Dec 2019 08:11:29 -0800 (PST) In-Reply-To: <20191202210947.3603-5-nieklinnenbank@gmail.com> References: <20191202210947.3603-1-nieklinnenbank@gmail.com> <20191202210947.3603-5-nieklinnenbank@gmail.com> From: Aleksandar Markovic Date: Wed, 4 Dec 2019 17:11:29 +0100 Message-ID: Subject: Re: [PATCH 04/10] arm: allwinner-h3: add USB host controller To: Niek Linnenbank Cc: "qemu-devel@nongnu.org" , "b.galvani@gmail.com" , "peter.maydell@linaro.org" , "qemu-arm@nongnu.org" Content-Type: multipart/alternative; boundary="000000000000c332150598e3106d" X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::242 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 04 Dec 2019 16:11:51 -0000 --000000000000c332150598e3106d Content-Type: text/plain; charset="UTF-8" On Monday, December 2, 2019, Niek Linnenbank wrote: > The Allwinner H3 System on Chip contains multiple USB 2.0 bus > connections which provide software access using the Enhanced > Host Controller Interface (EHCI) and Open Host Controller > Interface (OHCI) interfaces. This commit adds support for > both interfaces in the Allwinner H3 System on Chip. > > Signed-off-by: Niek Linnenbank > --- Niek, hi! I would like to clarify a detail here: The spec of the SoC enumerates (in 8.5.2.4. USB Host Register List) a number of registers for reading various USB-related states, but also for setting some of USB features. Does this series cover these registers, and interaction with them? If yes, how and where? If not, do you think it is not necessary at all? Or perhaps that it is a non-crucial limitation of this series? Thanks in advance, and congrats for your, it seems, first submission! Aleksandar hw/arm/allwinner-h3.c | 20 ++++++++++++++++++++ > hw/usb/hcd-ehci-sysbus.c | 17 +++++++++++++++++ > hw/usb/hcd-ehci.h | 1 + > 3 files changed, 38 insertions(+) > > diff --git a/hw/arm/allwinner-h3.c b/hw/arm/allwinner-h3.c > index 5566e979ec..afeb49c0ac 100644 > --- a/hw/arm/allwinner-h3.c > +++ b/hw/arm/allwinner-h3.c > @@ -26,6 +26,7 @@ > #include "hw/sysbus.h" > #include "hw/arm/allwinner-h3.h" > #include "hw/misc/unimp.h" > +#include "hw/usb/hcd-ehci.h" > #include "sysemu/sysemu.h" > > static void aw_h3_init(Object *obj) > @@ -183,6 +184,25 @@ static void aw_h3_realize(DeviceState *dev, Error > **errp) > } > sysbus_mmio_map(SYS_BUS_DEVICE(&s->ccu), 0, AW_H3_CCU_BASE); > > + /* Universal Serial Bus */ > + sysbus_create_simple(TYPE_AW_H3_EHCI, AW_H3_EHCI0_BASE, > + s->irq[AW_H3_GIC_SPI_EHCI0]); > + sysbus_create_simple(TYPE_AW_H3_EHCI, AW_H3_EHCI1_BASE, > + s->irq[AW_H3_GIC_SPI_EHCI1]); > + sysbus_create_simple(TYPE_AW_H3_EHCI, AW_H3_EHCI2_BASE, > + s->irq[AW_H3_GIC_SPI_EHCI2]); > + sysbus_create_simple(TYPE_AW_H3_EHCI, AW_H3_EHCI3_BASE, > + s->irq[AW_H3_GIC_SPI_EHCI3]); > + > + sysbus_create_simple("sysbus-ohci", AW_H3_OHCI0_BASE, > + s->irq[AW_H3_GIC_SPI_OHCI0]); > + sysbus_create_simple("sysbus-ohci", AW_H3_OHCI1_BASE, > + s->irq[AW_H3_GIC_SPI_OHCI1]); > + sysbus_create_simple("sysbus-ohci", AW_H3_OHCI2_BASE, > + s->irq[AW_H3_GIC_SPI_OHCI2]); > + sysbus_create_simple("sysbus-ohci", AW_H3_OHCI3_BASE, > + s->irq[AW_H3_GIC_SPI_OHCI3]); > + > /* UART */ > if (serial_hd(0)) { > serial_mm_init(get_system_memory(), AW_H3_UART0_REG_BASE, 2, > diff --git a/hw/usb/hcd-ehci-sysbus.c b/hw/usb/hcd-ehci-sysbus.c > index 020211fd10..174c3446ef 100644 > --- a/hw/usb/hcd-ehci-sysbus.c > +++ b/hw/usb/hcd-ehci-sysbus.c > @@ -145,6 +145,22 @@ static const TypeInfo ehci_exynos4210_type_info = { > .class_init = ehci_exynos4210_class_init, > }; > > +static void ehci_aw_h3_class_init(ObjectClass *oc, void *data) > +{ > + SysBusEHCIClass *sec = SYS_BUS_EHCI_CLASS(oc); > + DeviceClass *dc = DEVICE_CLASS(oc); > + > + sec->capsbase = 0x0; > + sec->opregbase = 0x10; > + set_bit(DEVICE_CATEGORY_USB, dc->categories); > +} > + > +static const TypeInfo ehci_aw_h3_type_info = { > + .name = TYPE_AW_H3_EHCI, > + .parent = TYPE_SYS_BUS_EHCI, > + .class_init = ehci_aw_h3_class_init, > +}; > + > static void ehci_tegra2_class_init(ObjectClass *oc, void *data) > { > SysBusEHCIClass *sec = SYS_BUS_EHCI_CLASS(oc); > @@ -267,6 +283,7 @@ static void ehci_sysbus_register_types(void) > type_register_static(&ehci_platform_type_info); > type_register_static(&ehci_xlnx_type_info); > type_register_static(&ehci_exynos4210_type_info); > + type_register_static(&ehci_aw_h3_type_info); > type_register_static(&ehci_tegra2_type_info); > type_register_static(&ehci_ppc4xx_type_info); > type_register_static(&ehci_fusbh200_type_info); > diff --git a/hw/usb/hcd-ehci.h b/hw/usb/hcd-ehci.h > index 0298238f0b..edb59311c4 100644 > --- a/hw/usb/hcd-ehci.h > +++ b/hw/usb/hcd-ehci.h > @@ -342,6 +342,7 @@ typedef struct EHCIPCIState { > #define TYPE_SYS_BUS_EHCI "sysbus-ehci-usb" > #define TYPE_PLATFORM_EHCI "platform-ehci-usb" > #define TYPE_EXYNOS4210_EHCI "exynos4210-ehci-usb" > +#define TYPE_AW_H3_EHCI "aw-h3-ehci-usb" > #define TYPE_TEGRA2_EHCI "tegra2-ehci-usb" > #define TYPE_PPC4xx_EHCI "ppc4xx-ehci-usb" > #define TYPE_FUSBH200_EHCI "fusbh200-ehci-usb" > -- > 2.17.1 > > > --000000000000c332150598e3106d Content-Type: text/html; charset="UTF-8" Content-Transfer-Encoding: quoted-printable

On Monday, December 2, 2019, Niek Linnenbank <nieklinnenbank@gmail.com> wrote:
The Allwinner H3 System on Chip contains multiple = USB 2.0 bus
connections which provide software access using the Enhanced
Host Controller Interface (EHCI) and Open Host Controller
Interface (OHCI) interfaces. This commit adds support for
both interfaces in the Allwinner H3 System on Chip.

Signed-off-by: Niek Linnenbank <nieklinnenbank@gmail.com>
---

Niek, hi!

I wo= uld like to clarify a detail here:

The spec of the= SoC enumerates (in 8.5.2.4. USB Host Register List) a number of registers = for reading various USB-related states, but also for setting some of USB fe= atures.
=C2=A0
Does this series cover these registers, = and interaction with them? If yes, how and where? If not, do you think it i= s not necessary at all? Or perhaps that it is a non-crucial limitation of t= his series?

Thanks in advance, and congrats for yo= ur, it seems, first submission!

Aleksandar


=C2=A0hw/arm/allwinner-h3.c=C2=A0 =C2=A0 | 20 ++++++++++++++++++++
=C2=A0hw/usb/hcd-ehci-sysbus.c | 17 +++++++++++++++++
=C2=A0hw/usb/hcd-ehci.h=C2=A0 =C2=A0 =C2=A0 =C2=A0 |=C2=A0 1 +
=C2=A03 files changed, 38 insertions(+)

diff --git a/hw/arm/allwinner-h3.c b/hw/arm/allwinner-h3.c
index 5566e979ec..afeb49c0ac 100644
--- a/hw/arm/allwinner-h3.c
+++ b/hw/arm/allwinner-h3.c
@@ -26,6 +26,7 @@
=C2=A0#include "hw/sysbus.h"
=C2=A0#include "hw/arm/allwinner-h3.h"
=C2=A0#include "hw/misc/unimp.h"
+#include "hw/usb/hcd-ehci.h"
=C2=A0#include "sysemu/sysemu.h"

=C2=A0static void aw_h3_init(Object *obj)
@@ -183,6 +184,25 @@ static void aw_h3_realize(DeviceState *dev, Error **er= rp)
=C2=A0 =C2=A0 =C2=A0}
=C2=A0 =C2=A0 =C2=A0sysbus_mmio_map(SYS_BUS_DEVICE(&s->ccu), 0,= AW_H3_CCU_BASE);

+=C2=A0 =C2=A0 /* Universal Serial Bus */
+=C2=A0 =C2=A0 sysbus_create_simple(TYPE_AW_H3_EHCI, AW_H3_EHCI0_BASE,=
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0s->irq[AW_H3_GIC_SPI_EHCI0]);
+=C2=A0 =C2=A0 sysbus_create_simple(TYPE_AW_H3_EHCI, AW_H3_EHCI1_BASE,=
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0s->irq[AW_H3_GIC_SPI_EHCI1]);
+=C2=A0 =C2=A0 sysbus_create_simple(TYPE_AW_H3_EHCI, AW_H3_EHCI2_BASE,=
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0s->irq[AW_H3_GIC_SPI_EHCI2]);
+=C2=A0 =C2=A0 sysbus_create_simple(TYPE_AW_H3_EHCI, AW_H3_EHCI3_BASE,=
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0s->irq[AW_H3_GIC_SPI_EHCI3]);
+
+=C2=A0 =C2=A0 sysbus_create_simple("sysbus-ohci", AW_H3_OHC= I0_BASE,
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0s->irq[AW_H3_GIC_SPI_OHCI0]);
+=C2=A0 =C2=A0 sysbus_create_simple("sysbus-ohci", AW_H3_OHC= I1_BASE,
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0s->irq[AW_H3_GIC_SPI_OHCI1]);
+=C2=A0 =C2=A0 sysbus_create_simple("sysbus-ohci", AW_H3_OHC= I2_BASE,
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0s->irq[AW_H3_GIC_SPI_OHCI2]);
+=C2=A0 =C2=A0 sysbus_create_simple("sysbus-ohci", AW_H3_OHC= I3_BASE,
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0s->irq[AW_H3_GIC_SPI_OHCI3]);
+
=C2=A0 =C2=A0 =C2=A0/* UART */
=C2=A0 =C2=A0 =C2=A0if (serial_hd(0)) {
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0serial_mm_init(get_system_memory(), = AW_H3_UART0_REG_BASE, 2,
diff --git a/hw/usb/hcd-ehci-sysbus.c b/hw/usb/hcd-ehci-sysbus.c
index 020211fd10..174c3446ef 100644
--- a/hw/usb/hcd-ehci-sysbus.c
+++ b/hw/usb/hcd-ehci-sysbus.c
@@ -145,6 +145,22 @@ static const TypeInfo ehci_exynos4210_type_info =3D {<= br> =C2=A0 =C2=A0 =C2=A0.class_init=C2=A0 =C2=A0 =3D ehci_exynos4210_class_init= ,
=C2=A0};

+static void ehci_aw_h3_class_init(ObjectClass *oc, void *data)
+{
+=C2=A0 =C2=A0 SysBusEHCIClass *sec =3D SYS_BUS_EHCI_CLASS(oc);
+=C2=A0 =C2=A0 DeviceClass *dc =3D DEVICE_CLASS(oc);
+
+=C2=A0 =C2=A0 sec->capsbase =3D 0x0;
+=C2=A0 =C2=A0 sec->opregbase =3D 0x10;
+=C2=A0 =C2=A0 set_bit(DEVICE_CATEGORY_USB, dc->categories);
+}
+
+static const TypeInfo ehci_aw_h3_type_info =3D {
+=C2=A0 =C2=A0 .name=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =3D TYPE_AW_H3_EHCI,=
+=C2=A0 =C2=A0 .parent=C2=A0 =C2=A0 =C2=A0 =C2=A0 =3D TYPE_SYS_BUS_EHCI, +=C2=A0 =C2=A0 .class_init=C2=A0 =C2=A0 =3D ehci_aw_h3_class_init,
+};
+
=C2=A0static void ehci_tegra2_class_init(ObjectClass *oc, void *data)<= br> =C2=A0{
=C2=A0 =C2=A0 =C2=A0SysBusEHCIClass *sec =3D SYS_BUS_EHCI_CLASS(oc);
@@ -267,6 +283,7 @@ static void ehci_sysbus_register_types(void)
=C2=A0 =C2=A0 =C2=A0type_register_static(&ehci_platform_type_info)= ;
=C2=A0 =C2=A0 =C2=A0type_register_static(&ehci_xlnx_type_info); =C2=A0 =C2=A0 =C2=A0type_register_static(&ehci_exynos4210_type_inf= o);
+=C2=A0 =C2=A0 type_register_static(&ehci_aw_h3_type_info);
=C2=A0 =C2=A0 =C2=A0type_register_static(&ehci_tegra2_type_info);<= br> =C2=A0 =C2=A0 =C2=A0type_register_static(&ehci_ppc4xx_type_info);<= br> =C2=A0 =C2=A0 =C2=A0type_register_static(&ehci_fusbh200_type_info)= ;
diff --git a/hw/usb/hcd-ehci.h b/hw/usb/hcd-ehci.h
index 0298238f0b..edb59311c4 100644
--- a/hw/usb/hcd-ehci.h
+++ b/hw/usb/hcd-ehci.h
@@ -342,6 +342,7 @@ typedef struct EHCIPCIState {
=C2=A0#define TYPE_SYS_BUS_EHCI "sysbus-ehci-usb"
=C2=A0#define TYPE_PLATFORM_EHCI "platform-ehci-usb"
=C2=A0#define TYPE_EXYNOS4210_EHCI "exynos4210-ehci-usb"
+#define TYPE_AW_H3_EHCI "aw-h3-ehci-usb"
=C2=A0#define TYPE_TEGRA2_EHCI "tegra2-ehci-usb"
=C2=A0#define TYPE_PPC4xx_EHCI "ppc4xx-ehci-usb"
=C2=A0#define TYPE_FUSBH200_EHCI "fusbh200-ehci-usb"
--
2.17.1


--000000000000c332150598e3106d-- From MAILER-DAEMON Wed Dec 04 11:40:55 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1icXhv-0007Uw-EW for mharc-qemu-arm@gnu.org; Wed, 04 Dec 2019 11:40:55 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:37599) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1icXhm-0007R6-Fu for qemu-arm@nongnu.org; Wed, 04 Dec 2019 11:40:50 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1icXhf-0007bG-2I for qemu-arm@nongnu.org; Wed, 04 Dec 2019 11:40:40 -0500 Received: from beetle.greensocs.com ([5.135.226.135]:54638) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1icXhe-0006zr-A7; Wed, 04 Dec 2019 11:40:39 -0500 Received: from [172.16.11.102] (crumble.bar.greensocs.com [172.16.11.102]) by beetle.greensocs.com (Postfix) with ESMTPSA id 8907096EF0; Wed, 4 Dec 2019 16:40:31 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=greensocs.com; s=mail; t=1575477632; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=DjGKPB5c4P8bd8a+QNrfUgzYWNg71wjN6eLs9KmHosA=; b=tnh7BobCcUBp+eIoC+Yfy9v91Q7AWWdA7AjwLJ6+QFRosm74E1i+ny0zlQro1llKDSDPEG E4opTNCd77Et0TWfXjt+L5z1r5/w2ZKJ4Jcy1kWUEZj0BwXZ9eT/VR8YFglupA8cATtPnB IL2V3unVulskwovAVJQyo3TLI3SjiDI= Subject: Re: [PATCH v6 0/9] Clock framework API To: Peter Maydell Cc: QEMU Developers , Mark Burton , "Edgar E. Iglesias" , Alistair Francis , =?UTF-8?Q?Marc-Andr=c3=a9_Lureau?= , Paolo Bonzini , "Daniel P. Berrange" , Eduardo Habkost , qemu-arm , =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= References: <20190904125531.27545-1-damien.hedde@greensocs.com> From: Damien Hedde Message-ID: Date: Wed, 4 Dec 2019 17:40:30 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.2.0 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=utf-8 Content-Language: en-US-large Content-Transfer-Encoding: 7bit ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=greensocs.com; s=mail; t=1575477632; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=DjGKPB5c4P8bd8a+QNrfUgzYWNg71wjN6eLs9KmHosA=; b=31u+hFb35XIKDa1zPuVQ0clcg3xiPu4NiiRlCFmzEoaTMeZIlUAjP3BPdvy+D+SRLbcGNP E4KVIJnlSGQFOK69lfi8gKbAGuuLI50zbCmkY+T+Gg7c1udlnaLQNcMwj6PhGnWGOITGvM V7nkn9+3+Zvl+DzoLkYU2q7bGMfU65A= ARC-Seal: i=1; s=mail; d=greensocs.com; t=1575477632; a=rsa-sha256; cv=none; b=TRASPnEhWHWxFEkSUF/96I1NtUBXdQQaIT/hRwFBCIAVi8JltKJ72k9cDo+RVLqy0TwkdS +Lgp8RyONz60AWHMPlNzUyoa3Ldt1uBI3bszI0LavHW1b0fFbO/VR9UqDOxBmuX29KB02m kn5VpMDZ376B8+uebQQbfzPJZd0OP3M= ARC-Authentication-Results: i=1; ORIGINATING; auth=pass smtp.auth=damien smtp.mailfrom=damien.hedde@greensocs.com X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 5.135.226.135 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 04 Dec 2019 16:40:51 -0000 On 12/2/19 5:15 PM, Peter Maydell wrote: > > The one topic I think we could do with discussing is whether > a simple uint64_t giving the frequency of the clock in Hz is > the right representation. In particular in your patch 9 the > board has a clock frequency that's not a nice integer number > of Hz. I think Philippe also mentioned on irc some board where > the UART clock ends up at a weird frequency. Since the > representation of the frequency is baked into the migration > format it's going to be easier to get it right first rather > than trying to change it later. > > So what should the representation be? Some random thoughts: > > 1) ptimer internally uses a 'period plus fraction' representation: > int64_t period is the integer part of the period in nanoseconds, > uint32_t period_frac is the fractional part of the period > (if you like you can think of this as "96-bit integer > period measured in units of one-2^32nd of a nanosecond"). > However its only public interfaces for setting the frequency > are (a) set the frequency in Hz (uint32_t) or (b) set > the period in nanoseconds (int64_t); the period_frac part > is used to handle frequencies which don't work out to > a nice whole number of nanoseconds per cycle. > > 2) I hear that SystemC uses "value plus a time unit", with > the smallest unit being a picosecond. (I think SystemC > also lets you specify the duty cycle, but we definitely > don't want to get into that!) The "value" is internally stored in a 64bits unsigned integer. > > 3) QEMUTimers are basically just nanosecond timers > > 4) The MAME emulator seems to work with periods of > 96-bit attoseconds (represented internally by a > 32-bit count of seconds plus a 64-bit count of > attoseconds). One attosecond is 1e-18 seconds. > > Does anybody else have experience with other modelling > or emulator technology and how it represents clocks ? 5) In linux, a clock rate is an "unsigned long" representing Hz. > > I feel we should at least be able to represent clocks > with the same accuracy that ptimer has. Then is a maybe a good idea to store the period and not the frequency in clocks so that we don't loose anything when we switch from a clock to a ptimer ? Regarding the clock, I don't see any strong obstacle to switch internally to a period based value. The only things we have to choose is how to represent a disabled clock. Since putting a "0" period to a ptimer will disable the timer in ptimer_reload(). We can choose that (and it's a good value because we can multiply or divide it, it stays the same). We could use the same representation as a ptimer. But if we don't keep a C number representation, then computation of frequencies/periods will be complicated at best and error prone. >From that point of view, if we could stick to a 64bits integer (or floating point number) it would be great. Can we use a sub nanosecond unit that fit our needs ? I did some test with a unit of 2^-32 of nanoseconds on 64bits (is that the unit of the ptimer fractional part ?) and if I'm not mistaken + we have a frequency range from ~0.2Hz up to 10^18Hz + the resolution is decreasing with the frequency (but at 100Mhz we have a ~2.3mHz resolution, at 1GHz it's ~0.23Hz and at 10GHz ~23Hz resolution). We hit 1Hz resolution around 2GHz. So it sounds to me we have largely enough resolution to model clocks in the range of frequencies we will have to handle. What do you think ? -- Damien From MAILER-DAEMON Wed Dec 04 11:54:08 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1icXui-00049q-NE for mharc-qemu-arm@gnu.org; Wed, 04 Dec 2019 11:54:08 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:40557) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1icXud-00042J-SU for qemu-arm@nongnu.org; Wed, 04 Dec 2019 11:54:06 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1icXuX-00048y-23 for qemu-arm@nongnu.org; Wed, 04 Dec 2019 11:54:00 -0500 Received: from us-smtp-delivery-1.mimecast.com ([207.211.31.120]:21714 helo=us-smtp-1.mimecast.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1icXuV-0002qr-02 for qemu-arm@nongnu.org; Wed, 04 Dec 2019 11:53:56 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1575478433; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=Sn7syersY781ySQM/IKHN+gNGr7N27AdeWJ99eb3Pjw=; b=eyciIFFPcNKeuSUjuXTUItLgRFRsEC/6dsAmZmPHxOUqYmtM9x5qq+1ORFLHl9QCyWirOW ivOTTBrx+wf6u4ZWGt5f6g5U2S1VRaamc1k27ZWa1yNdW2Y35QF9vD06xqStomA4mU5HH0 SQLREx9bnvDQ3+GTyWCIHVNc3BwEjik= Received: from mail-wr1-f69.google.com (mail-wr1-f69.google.com [209.85.221.69]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-399-djKCA98WMhyANFNuIUAX5w-1; Wed, 04 Dec 2019 11:53:51 -0500 Received: by mail-wr1-f69.google.com with SMTP id 90so125746wrq.6 for ; Wed, 04 Dec 2019 08:53:51 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:subject:to:cc:references:from:message-id:date :user-agent:mime-version:in-reply-to:content-language :content-transfer-encoding; bh=Sn7syersY781ySQM/IKHN+gNGr7N27AdeWJ99eb3Pjw=; b=PysjcqkklW9ECsid4jqyhYrPu0IjyLsKBHBKljh6njUj1BKGPO7ONwNbLgIdhrcJwq 7xtIufz2QTocjcud6t+iuNTm75jRlp6ENHcECTlSJIQfelAFotc1TtqrUJn1YgOCCrdC FqkHo5cIXqFsb4VkD93ckumWMJ5wmHahbhuZkLn8sbKWpEJ2gwlPYUzXISB+Pnz767Za i6U7bgQws8NE0JtCGHhm+mgYGLiWy553e2YDSAUDthuidJUb1LVcYFMWRzAoYVnSD053 Po+o8aSjq36DZU6XImNEb/AExv6MJZ42PvfO/muO5f34YYflvrq8Gcc/xoW7REfl9ylU F27Q== X-Gm-Message-State: APjAAAXeradJodHSzrK/XZ+MuYrgz9au25pFSkqMDMuW+6HvDJwyS4fh BoW21zmP9mdQiyziAemWQW6i921gICgyIOX3sTqTrq1rtjt76KaheNKmWgoDuI5IQHTn337uFbZ 5vcR/RyeZWfzu X-Received: by 2002:adf:e3d0:: with SMTP id k16mr5202999wrm.241.1575478430064; Wed, 04 Dec 2019 08:53:50 -0800 (PST) X-Google-Smtp-Source: APXvYqywXpKbxeh6tUAR88Jjn0N5UOWwT8JaopP6+eo+opwKYsH46xXT711/X/F6pxwdZ4qoR0ikeA== X-Received: by 2002:adf:e3d0:: with SMTP id k16mr5202967wrm.241.1575478429632; Wed, 04 Dec 2019 08:53:49 -0800 (PST) Received: from [192.168.1.35] (182.red-88-21-103.staticip.rima-tde.net. [88.21.103.182]) by smtp.gmail.com with ESMTPSA id l4sm7045743wml.33.2019.12.04.08.53.48 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 04 Dec 2019 08:53:49 -0800 (PST) Subject: Re: [PATCH 01/10] hw: arm: add Allwinner H3 System-on-Chip To: Niek Linnenbank , qemu-devel@nongnu.org Cc: b.galvani@gmail.com, peter.maydell@linaro.org, qemu-arm@nongnu.org, Markus Armbruster References: <20191202210947.3603-1-nieklinnenbank@gmail.com> <20191202210947.3603-2-nieklinnenbank@gmail.com> From: =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= Message-ID: <5d3961ca-8586-6d93-2525-fd2e29b233e1@redhat.com> Date: Wed, 4 Dec 2019 17:53:48 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.2.2 MIME-Version: 1.0 In-Reply-To: <20191202210947.3603-2-nieklinnenbank@gmail.com> Content-Language: en-US X-MC-Unique: djKCA98WMhyANFNuIUAX5w-1 X-Mimecast-Spam-Score: 0 Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 207.211.31.120 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 04 Dec 2019 16:54:07 -0000 Hi Niek, On 12/2/19 10:09 PM, Niek Linnenbank wrote: > The Allwinner H3 is a System on Chip containing four ARM Cortex A7 > processor cores. Features and specifications include DDR2/DDR3 memory, > SD/MMC storage cards, 10/100/1000Mbit ethernet, USB 2.0, HDMI and > various I/O modules. This commit adds support for the Allwinner H3 > System on Chip. > > Signed-off-by: Niek Linnenbank > --- > MAINTAINERS | 7 ++ > default-configs/arm-softmmu.mak | 1 + > hw/arm/Kconfig | 8 ++ > hw/arm/Makefile.objs | 1 + > hw/arm/allwinner-h3.c | 215 ++++++++++++++++++++++++++++++++ > include/hw/arm/allwinner-h3.h | 118 ++++++++++++++++++ > 6 files changed, 350 insertions(+) > create mode 100644 hw/arm/allwinner-h3.c > create mode 100644 include/hw/arm/allwinner-h3.h Since your series changes various files, can you have a look at the scripts/git.orderfile file and setup it for your QEMU contributions? > > diff --git a/MAINTAINERS b/MAINTAINERS > index 5e5e3e52d6..29c9936037 100644 > --- a/MAINTAINERS > +++ b/MAINTAINERS > @@ -479,6 +479,13 @@ F: hw/*/allwinner* > F: include/hw/*/allwinner* > F: hw/arm/cubieboard.c > > +Allwinner-h3 > +M: Niek Linnenbank > +L: qemu-arm@nongnu.org > +S: Maintained > +F: hw/*/allwinner-h3* > +F: include/hw/*/allwinner-h3* > + > ARM PrimeCell and CMSDK devices > M: Peter Maydell > L: qemu-arm@nongnu.org > diff --git a/default-configs/arm-softmmu.mak b/default-configs/arm-softmmu.mak > index 1f2e0e7fde..d75a239c2c 100644 > --- a/default-configs/arm-softmmu.mak > +++ b/default-configs/arm-softmmu.mak > @@ -40,3 +40,4 @@ CONFIG_FSL_IMX25=y > CONFIG_FSL_IMX7=y > CONFIG_FSL_IMX6UL=y > CONFIG_SEMIHOSTING=y > +CONFIG_ALLWINNER_H3=y > diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig > index c6e7782580..ebf8d2325f 100644 > --- a/hw/arm/Kconfig > +++ b/hw/arm/Kconfig > @@ -291,6 +291,14 @@ config ALLWINNER_A10 > select SERIAL > select UNIMP > > +config ALLWINNER_H3 > + bool > + select ALLWINNER_A10_PIT > + select SERIAL > + select ARM_TIMER > + select ARM_GIC > + select UNIMP > + > config RASPI > bool > select FRAMEBUFFER > diff --git a/hw/arm/Makefile.objs b/hw/arm/Makefile.objs > index fe749f65fd..956e496052 100644 > --- a/hw/arm/Makefile.objs > +++ b/hw/arm/Makefile.objs > @@ -34,6 +34,7 @@ obj-$(CONFIG_DIGIC) += digic.o > obj-$(CONFIG_OMAP) += omap1.o omap2.o > obj-$(CONFIG_STRONGARM) += strongarm.o > obj-$(CONFIG_ALLWINNER_A10) += allwinner-a10.o cubieboard.o > +obj-$(CONFIG_ALLWINNER_H3) += allwinner-h3.o > obj-$(CONFIG_RASPI) += bcm2835_peripherals.o bcm2836.o raspi.o > obj-$(CONFIG_STM32F205_SOC) += stm32f205_soc.o > obj-$(CONFIG_XLNX_ZYNQMP_ARM) += xlnx-zynqmp.o xlnx-zcu102.o > diff --git a/hw/arm/allwinner-h3.c b/hw/arm/allwinner-h3.c > new file mode 100644 > index 0000000000..470fdfebef > --- /dev/null > +++ b/hw/arm/allwinner-h3.c > @@ -0,0 +1,215 @@ > +/* > + * Allwinner H3 System on Chip emulation > + * > + * Copyright (C) 2019 Niek Linnenbank > + * > + * This program is free software: you can redistribute it and/or modify > + * it under the terms of the GNU General Public License as published by > + * the Free Software Foundation, either version 2 of the License, or > + * (at your option) any later version. > + * > + * This program is distributed in the hope that it will be useful, > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > + * GNU General Public License for more details. > + * > + * You should have received a copy of the GNU General Public License > + * along with this program. If not, see . > + */ > + > +#include "qemu/osdep.h" > +#include "exec/address-spaces.h" > +#include "qapi/error.h" > +#include "qemu/module.h" > +#include "qemu/units.h" > +#include "cpu.h" > +#include "hw/sysbus.h" > +#include "hw/arm/allwinner-h3.h" > +#include "hw/misc/unimp.h" > +#include "sysemu/sysemu.h" > + > +static void aw_h3_init(Object *obj) > +{ > + AwH3State *s = AW_H3(obj); > + > + sysbus_init_child_obj(obj, "gic", &s->gic, sizeof(s->gic), > + TYPE_ARM_GIC); > + > + sysbus_init_child_obj(obj, "timer", &s->timer, sizeof(s->timer), > + TYPE_AW_A10_PIT); > +} > + > +static void aw_h3_realize(DeviceState *dev, Error **errp) > +{ > + AwH3State *s = AW_H3(dev); > + SysBusDevice *sysbusdev = NULL; > + Error *err = NULL; > + unsigned i = 0; > + > + /* CPUs */ > + for (i = 0; i < AW_H3_NUM_CPUS; i++) { In https://www.mail-archive.com/qemu-devel@nongnu.org/msg662942.html Markus noted some incorrect pattern, and apparently you inherited it. You should initialize 'err' in the loop. > + Object *cpuobj = object_new(ARM_CPU_TYPE_NAME("cortex-a7")); > + CPUState *cpustate = CPU(cpuobj); We loose access to the CPUs. Can you use an array of AW_H3_NUM_CPUS cpus in AwH3State? > + > + /* Set the proper CPU index */ > + cpustate->cpu_index = i; > + > + /* Provide Power State Coordination Interface */ > + object_property_set_int(cpuobj, QEMU_PSCI_CONDUIT_HVC, > + "psci-conduit", &error_abort); Here you use the error_abort shortcut. > + > + /* Disable secondary CPUs */ > + object_property_set_bool(cpuobj, i > 0, "start-powered-off", &err); > + if (err != NULL) { > + error_propagate(errp, err); > + return; Here you return. > + } > + > + /* All exception levels required */ > + object_property_set_bool(cpuobj, > + true, "has_el3", NULL); > + object_property_set_bool(cpuobj, > + true, "has_el2", NULL); Here you don't use error. Cc'ing Markus who is the expert, since he might have better suggestions. This function is called before the machine starts, and we are not handling with user-provided configurations, so I'd say using &error_abort in all places is OK. > + > + /* Mark realized */ > + object_property_set_bool(cpuobj, true, "realized", &err); > + if (err != NULL) { > + error_propagate(errp, err); > + return; > + } > + object_unref(cpuobj); > + } > + > + /* Generic Interrupt Controller */ > + qdev_prop_set_uint32(DEVICE(&s->gic), "num-irq", AW_H3_GIC_NUM_SPI + > + GIC_INTERNAL); > + qdev_prop_set_uint32(DEVICE(&s->gic), "revision", 2); > + qdev_prop_set_uint32(DEVICE(&s->gic), "num-cpu", AW_H3_NUM_CPUS); > + qdev_prop_set_bit(DEVICE(&s->gic), "has-security-extensions", false); > + qdev_prop_set_bit(DEVICE(&s->gic), "has-virtualization-extensions", true); > + > + object_property_set_bool(OBJECT(&s->gic), true, "realized", &err); Why change API? Can we use qdev_init_nofail() instead? > + if (err) { > + error_propagate(errp, err); > + return; > + } > + > + sysbusdev = SYS_BUS_DEVICE(&s->gic); > + sysbus_mmio_map(sysbusdev, 0, AW_H3_GIC_DIST_BASE); > + sysbus_mmio_map(sysbusdev, 1, AW_H3_GIC_CPU_BASE); > + sysbus_mmio_map(sysbusdev, 2, AW_H3_GIC_HYP_BASE); > + sysbus_mmio_map(sysbusdev, 3, AW_H3_GIC_VCPU_BASE); > + > + /* > + * Wire the outputs from each CPU's generic timer and the GICv3 > + * maintenance interrupt signal to the appropriate GIC PPI inputs, > + * and the GIC's IRQ/FIQ/VIRQ/VFIQ interrupt outputs to the CPU's inputs. > + */ > + for (i = 0; i < AW_H3_NUM_CPUS; i++) { > + DeviceState *cpudev = DEVICE(qemu_get_cpu(i)); > + int ppibase = AW_H3_GIC_NUM_SPI + i * GIC_INTERNAL + GIC_NR_SGIS; > + int irq; > + /* > + * Mapping from the output timer irq lines from the CPU to the > + * GIC PPI inputs used for this board. > + */ > + const int timer_irq[] = { > + [GTIMER_PHYS] = AW_H3_GIC_PPI_ARM_PHYSTIMER, > + [GTIMER_VIRT] = AW_H3_GIC_PPI_ARM_VIRTTIMER, > + [GTIMER_HYP] = AW_H3_GIC_PPI_ARM_HYPTIMER, > + [GTIMER_SEC] = AW_H3_GIC_PPI_ARM_SECTIMER, > + }; > + > + /* Connect CPU timer outputs to GIC PPI inputs */ > + for (irq = 0; irq < ARRAY_SIZE(timer_irq); irq++) { > + qdev_connect_gpio_out(cpudev, irq, > + qdev_get_gpio_in(DEVICE(&s->gic), > + ppibase + timer_irq[irq])); > + } > + > + /* Connect GIC outputs to CPU interrupt inputs */ > + sysbus_connect_irq(sysbusdev, i, > + qdev_get_gpio_in(cpudev, ARM_CPU_IRQ)); > + sysbus_connect_irq(sysbusdev, i + AW_H3_NUM_CPUS, > + qdev_get_gpio_in(cpudev, ARM_CPU_FIQ)); > + sysbus_connect_irq(sysbusdev, i + (2 * AW_H3_NUM_CPUS), > + qdev_get_gpio_in(cpudev, ARM_CPU_VIRQ)); > + sysbus_connect_irq(sysbusdev, i + (3 * AW_H3_NUM_CPUS), > + qdev_get_gpio_in(cpudev, ARM_CPU_VFIQ)); > + > + /* GIC maintenance signal */ > + sysbus_connect_irq(sysbusdev, i + (4 * AW_H3_NUM_CPUS), > + qdev_get_gpio_in(DEVICE(&s->gic), > + ppibase + AW_H3_GIC_PPI_MAINT)); > + } > + > + for (i = 0; i < AW_H3_GIC_NUM_SPI; i++) { > + s->irq[i] = qdev_get_gpio_in(DEVICE(&s->gic), i); Apparently we don't need the irq array in AwH3State, because ... > + } > + > + /* Timer */ > + object_property_set_bool(OBJECT(&s->timer), true, "realized", &err); > + if (err != NULL) { > + error_propagate(errp, err); > + return; > + } > + sysbusdev = SYS_BUS_DEVICE(&s->timer); > + sysbus_mmio_map(sysbusdev, 0, AW_H3_PIT_REG_BASE); > + sysbus_connect_irq(sysbusdev, 0, s->irq[AW_H3_GIC_SPI_TIMER0]); > + sysbus_connect_irq(sysbusdev, 1, s->irq[AW_H3_GIC_SPI_TIMER1]); ... we can call qdev_get_gpio_in() here directly. > + > + /* SRAM */ > + memory_region_init_ram(&s->sram_a1, OBJECT(dev), "sram A1", > + AW_H3_SRAM_A1_SIZE, &error_fatal); > + memory_region_init_ram(&s->sram_a2, OBJECT(dev), "sram A2", > + AW_H3_SRAM_A2_SIZE, &error_fatal); > + memory_region_init_ram(&s->sram_c, OBJECT(dev), "sram C", > + AW_H3_SRAM_C_SIZE, &error_fatal); > + memory_region_add_subregion(get_system_memory(), AW_H3_SRAM_A1_BASE, > + &s->sram_a1); > + memory_region_add_subregion(get_system_memory(), AW_H3_SRAM_A2_BASE, > + &s->sram_a2); > + memory_region_add_subregion(get_system_memory(), AW_H3_SRAM_C_BASE, > + &s->sram_c); > + > + /* UART */ > + if (serial_hd(0)) { > + serial_mm_init(get_system_memory(), AW_H3_UART0_REG_BASE, 2, > + s->irq[AW_H3_GIC_SPI_UART0], 115200, serial_hd(0), qdev_get_gpio_in() here too. > + DEVICE_NATIVE_ENDIAN); > + } > + > + /* Unimplemented devices */ > + create_unimplemented_device("display-engine", AW_H3_DE_BASE, AW_H3_DE_SIZE); > + create_unimplemented_device("dma", AW_H3_DMA_BASE, AW_H3_DMA_SIZE); > + create_unimplemented_device("lcd0", AW_H3_LCD0_BASE, AW_H3_LCD0_SIZE); > + create_unimplemented_device("lcd1", AW_H3_LCD1_BASE, AW_H3_LCD1_SIZE); > + create_unimplemented_device("gpu", AW_H3_GPU_BASE, AW_H3_GPU_SIZE); > + create_unimplemented_device("hdmi", AW_H3_HDMI_BASE, AW_H3_HDMI_SIZE); > + create_unimplemented_device("rtc", AW_H3_RTC_BASE, AW_H3_RTC_SIZE); > + create_unimplemented_device("audio-codec", AW_H3_AC_BASE, AW_H3_AC_SIZE); > +} > + > +static void aw_h3_class_init(ObjectClass *oc, void *data) > +{ > + DeviceClass *dc = DEVICE_CLASS(oc); > + > + dc->realize = aw_h3_realize; > + /* Reason: uses serial_hds and nd_table */ > + dc->user_creatable = false; > +} > + > +static const TypeInfo aw_h3_type_info = { > + .name = TYPE_AW_H3, > + .parent = TYPE_DEVICE, > + .instance_size = sizeof(AwH3State), > + .instance_init = aw_h3_init, > + .class_init = aw_h3_class_init, > +}; > + > +static void aw_h3_register_types(void) > +{ > + type_register_static(&aw_h3_type_info); > +} > + > +type_init(aw_h3_register_types) > diff --git a/include/hw/arm/allwinner-h3.h b/include/hw/arm/allwinner-h3.h > new file mode 100644 > index 0000000000..af368c2254 > --- /dev/null > +++ b/include/hw/arm/allwinner-h3.h > @@ -0,0 +1,118 @@ > +/* > + * Allwinner H3 System on Chip emulation > + * > + * Copyright (C) 2019 Niek Linnenbank > + * > + * This program is free software: you can redistribute it and/or modify > + * it under the terms of the GNU General Public License as published by > + * the Free Software Foundation, either version 2 of the License, or > + * (at your option) any later version. > + * > + * This program is distributed in the hope that it will be useful, > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > + * GNU General Public License for more details. > + * > + * You should have received a copy of the GNU General Public License > + * along with this program. If not, see . > + */ > + > +#ifndef HW_ARM_ALLWINNER_H3_H > +#define HW_ARM_ALLWINNER_H3_H > + > +#include "qemu/error-report.h" > +#include "qemu/units.h" > +#include "hw/char/serial.h" > +#include "hw/arm/boot.h" > +#include "hw/timer/allwinner-a10-pit.h" > +#include "hw/intc/arm_gic.h" > +#include "target/arm/cpu.h" > + > +#define AW_H3_SRAM_A1_BASE (0x00000000) > +#define AW_H3_SRAM_A2_BASE (0x00044000) > +#define AW_H3_SRAM_C_BASE (0x00010000) > +#define AW_H3_DE_BASE (0x01000000) > +#define AW_H3_SYSCON_BASE (0x01c00000) > +#define AW_H3_DMA_BASE (0x01c02000) > +#define AW_H3_LCD0_BASE (0x01c0c000) > +#define AW_H3_LCD1_BASE (0x01c0d000) > +#define AW_H3_SID_BASE (0x01c14000) > +#define AW_H3_CCU_BASE (0x01c20000) > +#define AW_H3_PIC_REG_BASE (0x01c20400) > +#define AW_H3_PIT_REG_BASE (0x01c20c00) > +#define AW_H3_AC_BASE (0x01c22c00) > +#define AW_H3_UART0_REG_BASE (0x01c28000) > +#define AW_H3_EMAC_BASE (0x01c30000) > +#define AW_H3_MMC0_BASE (0x01c0f000) > +#define AW_H3_EHCI0_BASE (0x01c1a000) > +#define AW_H3_OHCI0_BASE (0x01c1a400) > +#define AW_H3_EHCI1_BASE (0x01c1b000) > +#define AW_H3_OHCI1_BASE (0x01c1b400) > +#define AW_H3_EHCI2_BASE (0x01c1c000) > +#define AW_H3_OHCI2_BASE (0x01c1c400) > +#define AW_H3_EHCI3_BASE (0x01c1d000) > +#define AW_H3_OHCI3_BASE (0x01c1d400) > +#define AW_H3_GPU_BASE (0x01c40000) > +#define AW_H3_GIC_DIST_BASE (0x01c81000) > +#define AW_H3_GIC_CPU_BASE (0x01c82000) > +#define AW_H3_GIC_HYP_BASE (0x01c84000) > +#define AW_H3_GIC_VCPU_BASE (0x01c86000) > +#define AW_H3_HDMI_BASE (0x01ee0000) > +#define AW_H3_RTC_BASE (0x01f00000) > +#define AW_H3_CPUCFG_BASE (0x01f01c00) > +#define AW_H3_SDRAM_BASE (0x40000000) > + > +#define AW_H3_SRAM_A1_SIZE (64 * KiB) > +#define AW_H3_SRAM_A2_SIZE (32 * KiB) > +#define AW_H3_SRAM_C_SIZE (44 * KiB) > +#define AW_H3_DE_SIZE (4 * MiB) > +#define AW_H3_DMA_SIZE (4 * KiB) > +#define AW_H3_LCD0_SIZE (4 * KiB) > +#define AW_H3_LCD1_SIZE (4 * KiB) > +#define AW_H3_GPU_SIZE (64 * KiB) > +#define AW_H3_HDMI_SIZE (128 * KiB) > +#define AW_H3_RTC_SIZE (1 * KiB) > +#define AW_H3_AC_SIZE (2 * KiB) > + > +#define AW_H3_GIC_PPI_MAINT (9) > +#define AW_H3_GIC_PPI_ARM_HYPTIMER (10) > +#define AW_H3_GIC_PPI_ARM_VIRTTIMER (11) > +#define AW_H3_GIC_PPI_ARM_SECTIMER (13) > +#define AW_H3_GIC_PPI_ARM_PHYSTIMER (14) > + > +#define AW_H3_GIC_SPI_UART0 (0) > +#define AW_H3_GIC_SPI_TIMER0 (18) > +#define AW_H3_GIC_SPI_TIMER1 (19) > +#define AW_H3_GIC_SPI_MMC0 (60) > +#define AW_H3_GIC_SPI_MMC1 (61) > +#define AW_H3_GIC_SPI_MMC2 (62) > +#define AW_H3_GIC_SPI_EHCI0 (72) > +#define AW_H3_GIC_SPI_OHCI0 (73) > +#define AW_H3_GIC_SPI_EHCI1 (74) > +#define AW_H3_GIC_SPI_OHCI1 (75) > +#define AW_H3_GIC_SPI_EHCI2 (76) > +#define AW_H3_GIC_SPI_OHCI2 (77) > +#define AW_H3_GIC_SPI_EHCI3 (78) > +#define AW_H3_GIC_SPI_OHCI3 (79) > +#define AW_H3_GIC_SPI_EMAC (82) I'd move half of the previous definitions into allwinner-h3.c, since they are only used there. Also, I'd use an enum for the PPI/SPI. > + > +#define AW_H3_GIC_NUM_SPI (128) > +#define AW_H3_NUM_CPUS (4) > + > +#define TYPE_AW_H3 "allwinner-h3" > +#define AW_H3(obj) OBJECT_CHECK(AwH3State, (obj), TYPE_AW_H3) > + > +typedef struct AwH3State { > + /*< private >*/ > + DeviceState parent_obj; > + /*< public >*/ > + > + qemu_irq irq[AW_H3_GIC_NUM_SPI]; > + AwA10PITState timer; > + GICState gic; > + MemoryRegion sram_a1; > + MemoryRegion sram_a2; > + MemoryRegion sram_c; > +} AwH3State; > + > +#endif > Nice clean patch, for a first contribution :) From MAILER-DAEMON Wed Dec 04 14:50:35 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1icafS-0004AU-VA for mharc-qemu-arm@gnu.org; Wed, 04 Dec 2019 14:50:34 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:59337) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1icafH-00041K-3k for qemu-arm@nongnu.org; Wed, 04 Dec 2019 14:50:25 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1icafF-00038E-VM for qemu-arm@nongnu.org; Wed, 04 Dec 2019 14:50:23 -0500 Received: from mail-il1-x142.google.com ([2607:f8b0:4864:20::142]:39711) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1icafC-0002ys-PY; Wed, 04 Dec 2019 14:50:18 -0500 Received: by mail-il1-x142.google.com with SMTP id a7so668142ild.6; Wed, 04 Dec 2019 11:50:17 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=I5pUPHYbr0BueGJe7F25s/VFQXDl8+ZiGmqPzGqYpgY=; b=jlnALiCZ9Pzedb7XVTPCJGOgZDTsT2BpiWWDkywevUOm0ns/61Cq7WElbVpLPQeBZD IbszXua3FwaREiCZc/dsXkyxOhRi6mxozA1ODc4NK9RFpYX9hHn4Z/0JUgu6DJ17UE8S 7iLRPNrXfA861gA9oTEEKd46HQc1Dqdbn0jVHYqrJBsPXIDJQdG+H6j/effvSkxTmCyt Mmx7Fk9iRHxL4Q8YZL8lFvGSvsWxd/H/bmHdYb3eZAreKri0TRiZfc5fA2EUurbIkm7F SwztkkL6Cf1qdL1v7AA5JL5ZdEVdAKViuux9o0h+nCiOqhdfUp5y06FqtfzHqLZEqPTH PxyQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=I5pUPHYbr0BueGJe7F25s/VFQXDl8+ZiGmqPzGqYpgY=; b=CwxY4Z19/IzguWYRpqPGK+jECwm93Di3R+aPnv1gq5QLVDFrw+rs7AEUExcM0f/gqj 8r/NlSYc57LyrtTOi4XS/vUabxe8MXjghl8BkjTe/O8zckjvgJ9KkJVNGxAl1Y36/ave 1xlAUNpOb1s7PkmAZDH1qR4I3yxyoKVZ1Ln9gE5ecPMFhNpeMWTvToobF7aTja/1xXTV Ov6xZqvKLLVRNeyoNuU9p9HF7WI5FJ8whtE133CjVQ1nSnEU7B4lhBwNhyCmHWn7Efxe aRLc+2vaTdx/2pcgsjEzd5NGwj7Hl2WMvLw7uoSSrHm3qId+M35LyzxJvnxcp8WI5qmI i2zQ== X-Gm-Message-State: APjAAAWrX31ArnkW9QUuASJKrRSHU5xpP5pPDSSxSC1PY0uWTv14k8d+ mNbUr+fpwrWk98fT4Qz1lIifTKxKo4NWK91JgLU= X-Google-Smtp-Source: APXvYqygCgdlSpjPHk7b/9w2aYIoxaLOeIq2rzsSj+EihENrU1Utr8ED/QHXVqK0gs2vQY4esecXTUQOVytCgvW8xaE= X-Received: by 2002:a92:5a45:: with SMTP id o66mr4970679ilb.67.1575489017236; Wed, 04 Dec 2019 11:50:17 -0800 (PST) MIME-Version: 1.0 References: <20191202210947.3603-1-nieklinnenbank@gmail.com> <20191202210947.3603-3-nieklinnenbank@gmail.com> <239606dc-3545-c3f7-1e11-429f53994147@redhat.com> In-Reply-To: <239606dc-3545-c3f7-1e11-429f53994147@redhat.com> From: Niek Linnenbank Date: Wed, 4 Dec 2019 20:50:05 +0100 Message-ID: Subject: Re: [PATCH 02/10] hw: arm: add Xunlong Orange Pi PC machine To: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= Cc: qemu-devel@nongnu.org, b.galvani@gmail.com, Peter Maydell , qemu-arm@nongnu.org Content-Type: multipart/alternative; boundary="0000000000003852570598e61f67" X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::142 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 04 Dec 2019 19:50:31 -0000 --0000000000003852570598e61f67 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable On Wed, Dec 4, 2019 at 10:03 AM Philippe Mathieu-Daud=C3=A9 wrote: > On 12/3/19 8:33 PM, Niek Linnenbank wrote: > > Hello Philippe, > > > > Thanks for your quick review comments! > > I'll start working on a v2 of the patches and include the changes you > > suggested. > > Thanks, but I'd suggest to wait few more days to give time to others > reviewers. Else having multiple versions of a big series reviewed at the > same time is very confusing. > I have other minor comments on others patches, but need to find the time > to continue reviewing. > > OK Philippe, I will follow your advise and wait a few more days before submitting a new version. I'll wait at least until you had a chance to review all the patches. I'm new to the QEMU community, so I will need to learn the process along the way. Regards, Niek --=20 Niek Linnenbank --0000000000003852570598e61f67 Content-Type: text/html; charset="UTF-8" Content-Transfer-Encoding: quoted-printable


=
On Wed, Dec 4, 2019 at 10:03 AM Phili= ppe Mathieu-Daud=C3=A9 <philmd@redh= at.com> wrote:
On 12/3/19 8:33 PM, Niek Linnenbank wrote:
> Hello Philippe,
>
> Thanks for your quick review comments!
> I'll start working on a v2 of the patches and include the changes = you
> suggested.

Thanks, but I'd suggest to wait few more days to give time to others reviewers. Else having multiple versions of a big series reviewed at the same time is very confusing.
I have other minor comments on others patches, but need to find the time to continue reviewing.


OK Philippe, I will follow your advi= se and wait a few more days before submitting a new version.
I= 9;ll wait at least until you had a chance to review all the patches. I'= m new to the QEMU
community, so I will need to learn the process = along the way.

Regards,
Niek





--
Niek Linnenbank<= br>
--0000000000003852570598e61f67-- From MAILER-DAEMON Wed Dec 04 15:20:57 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1icb8r-0002SO-Ky for mharc-qemu-arm@gnu.org; Wed, 04 Dec 2019 15:20:57 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:42602) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1icb8o-0002PC-I6 for qemu-arm@nongnu.org; Wed, 04 Dec 2019 15:20:56 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1icb8m-00019u-Ic for qemu-arm@nongnu.org; Wed, 04 Dec 2019 15:20:54 -0500 Received: from mail-io1-xd42.google.com ([2607:f8b0:4864:20::d42]:34966) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1icb8h-0000w7-9R; Wed, 04 Dec 2019 15:20:48 -0500 Received: by mail-io1-xd42.google.com with SMTP id v18so1071048iol.2; Wed, 04 Dec 2019 12:20:45 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=xPJxrSztFlFEdpfOr2gCi5I691E4UF6NIoWtO3B06sE=; b=io8FyGOa9L3xA0HRd4ZaE4YaBwIJ/vM/D89sBIJJxkgrCtnTkduo8a4TeVbS+cgPdL zEgt70djGtINfu+ZsJkss6kkLsEuUQb/AlxrZGDn4EdFuyZML9MvjTuerCi5IYw/MDD/ LpjHovZdWYRZpE4nY3H8CeLnCGdTjgnIW6SwBiuetgL/pl9jM5hngw2UQER2w/5AmHqf GZ7v05q6FY2rliv41iPygtopHfkcF9Y5TZLrgDwk76NO0v0fCf7Qb3q0TlD8G5feYA2W zxS8tmZVrKVRgehQunE4SUpcVGHzcQ0f8qKmTZQtqv+JjdwNsPPHnxY5vXkP986a4Erk ombg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=xPJxrSztFlFEdpfOr2gCi5I691E4UF6NIoWtO3B06sE=; b=gJBxp7f/aPLlIJdpdp8yhYsjFOboX3MwOYi8s7CVDWK99PrEqGGC5zI4O48/FiPkW7 8bsBPzjSYjH2F34yidnoOMnmOYL87hakmqE04nL8CKvjX3UPk/52vSqJkWfHRzYOjQUT 0yV7n035oL36aBfft1qTKO3Zenl/8I9KtddtokRGV08YMpAhSy+idAv6XnJYvrDDU4Ia 2erZ6uFFye4e1EcocVSIchpm/61ZGPfnfjoOGLuAuQdfaSdvmCSFCBUPFML1OjMCIyzm QO7q966h6a70qbJjbLKbBAK1+DuAJg1VGORDsgInoP6wOuWyr7cQJNHwKHkNnqq9MyQZ 7dNQ== X-Gm-Message-State: APjAAAWZfCFFwui86vJULIbOqPMFCPdaok1h5jlENXi5MXN6iYxwMBtq FLVeF9SYmxnDnNgcjqJOZk3mu4TBxG+T1b+JNsY= X-Google-Smtp-Source: APXvYqyzz5Arr3qpyZfmpyw21ENq55Y10LZVduz0yt136YhFMZAInQa7zIdxi/RQswbrpenaeK4Ty++d4DIQWwKL6F8= X-Received: by 2002:a02:7fd0:: with SMTP id r199mr4824173jac.126.1575490844837; Wed, 04 Dec 2019 12:20:44 -0800 (PST) MIME-Version: 1.0 References: <20191202210947.3603-1-nieklinnenbank@gmail.com> <20191202210947.3603-5-nieklinnenbank@gmail.com> In-Reply-To: From: Niek Linnenbank Date: Wed, 4 Dec 2019 21:20:33 +0100 Message-ID: Subject: Re: [PATCH 04/10] arm: allwinner-h3: add USB host controller To: Aleksandar Markovic Cc: "qemu-devel@nongnu.org" , "b.galvani@gmail.com" , "peter.maydell@linaro.org" , "qemu-arm@nongnu.org" Content-Type: multipart/alternative; boundary="0000000000002753aa0598e68c8a" X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::d42 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 04 Dec 2019 20:20:56 -0000 --0000000000002753aa0598e68c8a Content-Type: text/plain; charset="UTF-8" On Wed, Dec 4, 2019 at 5:11 PM Aleksandar Markovic < aleksandar.m.mail@gmail.com> wrote: > > > On Monday, December 2, 2019, Niek Linnenbank > wrote: > >> The Allwinner H3 System on Chip contains multiple USB 2.0 bus >> connections which provide software access using the Enhanced >> Host Controller Interface (EHCI) and Open Host Controller >> Interface (OHCI) interfaces. This commit adds support for >> both interfaces in the Allwinner H3 System on Chip. >> >> Signed-off-by: Niek Linnenbank >> --- > > > Niek, hi! > > I would like to clarify a detail here: > > The spec of the SoC enumerates (in 8.5.2.4. USB Host Register List) a > number of registers for reading various USB-related states, but also for > setting some of USB features. > > Does this series cover these registers, and interaction with them? If yes, > how and where? If not, do you think it is not necessary at all? Or perhaps > that it is a non-crucial limitation of this series? > Hello Aleksandar! Very good question, I will try to explain what I did to support USB for the Allwinner H3 emulation. EHCI and OHCI are both standardized interfaces to the USB bus and both provide their own standardized software interface. Because they are standards, operatings system drivers can implement a generic driver which uses the defined interface and re-use it in multiple boards/platforms. Things that can be different between boards are, for example the base address in memory where the registers are provided. In QEMU I found that both the OHCI and EHCI host controllers are already emulated and used by other boards as well. For example, you can find the OHCI registers from 8.5.2.4 implemented in the file hw/usb/hcd-ohci.c:1515 in ohci_mem_read(). So for the Allwinner H3 I simply had to define the base address for both controllers and create the objects. At that point, the Linux kernel can access the USB bus with the generic EHCI/OHCI platform drivers. In the Linux code, you can see in the file ./arch/arm/boot/dts/sunxi-h3-h5.dtsi:281 the definitions named ehci0-ehci3 and ohci0-ohci3 where it specifies in the device tree configuration to load the generic drivers. > > Thanks in advance, and congrats for your, it seems, first submission! > > Thank you Aleksandar! Indeed, it is my first submission. I will do my best to update the patches to comply with the QEMU coding style and best practises. Regards, Niek > Aleksandar > > > hw/arm/allwinner-h3.c | 20 ++++++++++++++++++++ >> hw/usb/hcd-ehci-sysbus.c | 17 +++++++++++++++++ >> hw/usb/hcd-ehci.h | 1 + >> 3 files changed, 38 insertions(+) >> >> diff --git a/hw/arm/allwinner-h3.c b/hw/arm/allwinner-h3.c >> index 5566e979ec..afeb49c0ac 100644 >> --- a/hw/arm/allwinner-h3.c >> +++ b/hw/arm/allwinner-h3.c >> @@ -26,6 +26,7 @@ >> #include "hw/sysbus.h" >> #include "hw/arm/allwinner-h3.h" >> #include "hw/misc/unimp.h" >> +#include "hw/usb/hcd-ehci.h" >> #include "sysemu/sysemu.h" >> >> static void aw_h3_init(Object *obj) >> @@ -183,6 +184,25 @@ static void aw_h3_realize(DeviceState *dev, Error >> **errp) >> } >> sysbus_mmio_map(SYS_BUS_DEVICE(&s->ccu), 0, AW_H3_CCU_BASE); >> >> + /* Universal Serial Bus */ >> + sysbus_create_simple(TYPE_AW_H3_EHCI, AW_H3_EHCI0_BASE, >> + s->irq[AW_H3_GIC_SPI_EHCI0]); >> + sysbus_create_simple(TYPE_AW_H3_EHCI, AW_H3_EHCI1_BASE, >> + s->irq[AW_H3_GIC_SPI_EHCI1]); >> + sysbus_create_simple(TYPE_AW_H3_EHCI, AW_H3_EHCI2_BASE, >> + s->irq[AW_H3_GIC_SPI_EHCI2]); >> + sysbus_create_simple(TYPE_AW_H3_EHCI, AW_H3_EHCI3_BASE, >> + s->irq[AW_H3_GIC_SPI_EHCI3]); >> + >> + sysbus_create_simple("sysbus-ohci", AW_H3_OHCI0_BASE, >> + s->irq[AW_H3_GIC_SPI_OHCI0]); >> + sysbus_create_simple("sysbus-ohci", AW_H3_OHCI1_BASE, >> + s->irq[AW_H3_GIC_SPI_OHCI1]); >> + sysbus_create_simple("sysbus-ohci", AW_H3_OHCI2_BASE, >> + s->irq[AW_H3_GIC_SPI_OHCI2]); >> + sysbus_create_simple("sysbus-ohci", AW_H3_OHCI3_BASE, >> + s->irq[AW_H3_GIC_SPI_OHCI3]); >> + >> /* UART */ >> if (serial_hd(0)) { >> serial_mm_init(get_system_memory(), AW_H3_UART0_REG_BASE, 2, >> diff --git a/hw/usb/hcd-ehci-sysbus.c b/hw/usb/hcd-ehci-sysbus.c >> index 020211fd10..174c3446ef 100644 >> --- a/hw/usb/hcd-ehci-sysbus.c >> +++ b/hw/usb/hcd-ehci-sysbus.c >> @@ -145,6 +145,22 @@ static const TypeInfo ehci_exynos4210_type_info = { >> .class_init = ehci_exynos4210_class_init, >> }; >> >> +static void ehci_aw_h3_class_init(ObjectClass *oc, void *data) >> +{ >> + SysBusEHCIClass *sec = SYS_BUS_EHCI_CLASS(oc); >> + DeviceClass *dc = DEVICE_CLASS(oc); >> + >> + sec->capsbase = 0x0; >> + sec->opregbase = 0x10; >> + set_bit(DEVICE_CATEGORY_USB, dc->categories); >> +} >> + >> +static const TypeInfo ehci_aw_h3_type_info = { >> + .name = TYPE_AW_H3_EHCI, >> + .parent = TYPE_SYS_BUS_EHCI, >> + .class_init = ehci_aw_h3_class_init, >> +}; >> + >> static void ehci_tegra2_class_init(ObjectClass *oc, void *data) >> { >> SysBusEHCIClass *sec = SYS_BUS_EHCI_CLASS(oc); >> @@ -267,6 +283,7 @@ static void ehci_sysbus_register_types(void) >> type_register_static(&ehci_platform_type_info); >> type_register_static(&ehci_xlnx_type_info); >> type_register_static(&ehci_exynos4210_type_info); >> + type_register_static(&ehci_aw_h3_type_info); >> type_register_static(&ehci_tegra2_type_info); >> type_register_static(&ehci_ppc4xx_type_info); >> type_register_static(&ehci_fusbh200_type_info); >> diff --git a/hw/usb/hcd-ehci.h b/hw/usb/hcd-ehci.h >> index 0298238f0b..edb59311c4 100644 >> --- a/hw/usb/hcd-ehci.h >> +++ b/hw/usb/hcd-ehci.h >> @@ -342,6 +342,7 @@ typedef struct EHCIPCIState { >> #define TYPE_SYS_BUS_EHCI "sysbus-ehci-usb" >> #define TYPE_PLATFORM_EHCI "platform-ehci-usb" >> #define TYPE_EXYNOS4210_EHCI "exynos4210-ehci-usb" >> +#define TYPE_AW_H3_EHCI "aw-h3-ehci-usb" >> #define TYPE_TEGRA2_EHCI "tegra2-ehci-usb" >> #define TYPE_PPC4xx_EHCI "ppc4xx-ehci-usb" >> #define TYPE_FUSBH200_EHCI "fusbh200-ehci-usb" >> -- >> 2.17.1 >> >> >> -- Niek Linnenbank --0000000000002753aa0598e68c8a Content-Type: text/html; charset="UTF-8" Content-Transfer-Encoding: quoted-printable


=
On Wed, Dec 4, 2019 at 5:11 PM Aleksa= ndar Markovic <aleksandar= .m.mail@gmail.com> wrote:


On Monday, December 2, 2019, Niek Linnenbank <<= a href=3D"mailto:nieklinnenbank@gmail.com" target=3D"_blank">nieklinnenbank= @gmail.com> wrote:
The Allwinner H3 System on Chip contains multiple USB 2.0 bus
connections which provide software access using the Enhanced
Host Controller Interface (EHCI) and Open Host Controller
Interface (OHCI) interfaces. This commit adds support for
both interfaces in the Allwinner H3 System on Chip.

Signed-off-by: Niek Linnenbank <nieklinnenbank@gmail.com>
---

Niek, hi!

I wo= uld like to clarify a detail here:

The spec of the= SoC enumerates (in 8.5.2.4. USB Host Register List) a number of registers = for reading various USB-related states, but also for setting some of USB fe= atures.
=C2=A0
Does this series cover these registers, = and interaction with them? If yes, how and where? If not, do you think it i= s not necessary at all? Or perhaps that it is a non-crucial limitation of t= his series?

Hello Aleksandar!

Very good question, I will try to explain what I did to s= upport USB for the Allwinner H3 emulation.
EHCI and OHCI are both= standardized interfaces to the USB bus and both provide their own standard= ized software interface.
Because they are standards, operatings s= ystem drivers can implement a generic driver which uses the defined interfa= ce and
re-use it in multiple boards/platforms. Things that can be= different between boards are, for example the base address in
me= mory where the registers are provided.

In QEMU I f= ound that both the OHCI and EHCI host controllers are already emulated and = used by other boards as well. For example,
you can find the OHCI = registers from 8.5.2.4 implemented in the file hw/usb/hcd-ohci.c:1515 in oh= ci_mem_read(). So for the Allwinner
H3 I simply had to define the= base address for both controllers and create the objects. At that point, t= he Linux kernel can access
the USB bus with the generic EHCI/OHCI= platform drivers. In the Linux code, you can see in the file ./arch/arm/bo= ot/dts/sunxi-h3-h5.dtsi:281
the definitions named ehci0-ehci3 and= ohci0-ohci3 where it specifies in the device tree configuration to load th= e generic drivers.
=C2=A0

Thanks in advance, and congrats for you= r, it seems, first submission!


Thank you Aleksandar! Indeed, it is my first submission. I will do= my best to
update the patches to comply with the QEMU coding sty= le and best practises.

Regards,
Niek
=
=C2=A0
Aleksandar


=C2=A0hw/arm/allwinner-h3.c=C2=A0 =C2=A0 | 20 ++++++++++++++++++++
=C2=A0hw/usb/hcd-ehci-sysbus.c | 17 +++++++++++++++++
=C2=A0hw/usb/hcd-ehci.h=C2=A0 =C2=A0 =C2=A0 =C2=A0 |=C2=A0 1 +
=C2=A03 files changed, 38 insertions(+)

diff --git a/hw/arm/allwinner-h3.c b/hw/arm/allwinner-h3.c
index 5566e979ec..afeb49c0ac 100644
--- a/hw/arm/allwinner-h3.c
+++ b/hw/arm/allwinner-h3.c
@@ -26,6 +26,7 @@
=C2=A0#include "hw/sysbus.h"
=C2=A0#include "hw/arm/allwinner-h3.h"
=C2=A0#include "hw/misc/unimp.h"
+#include "hw/usb/hcd-ehci.h"
=C2=A0#include "sysemu/sysemu.h"

=C2=A0static void aw_h3_init(Object *obj)
@@ -183,6 +184,25 @@ static void aw_h3_realize(DeviceState *dev, Error **er= rp)
=C2=A0 =C2=A0 =C2=A0}
=C2=A0 =C2=A0 =C2=A0sysbus_mmio_map(SYS_BUS_DEVICE(&s->ccu), 0, AW_H= 3_CCU_BASE);

+=C2=A0 =C2=A0 /* Universal Serial Bus */
+=C2=A0 =C2=A0 sysbus_create_simple(TYPE_AW_H3_EHCI, AW_H3_EHCI0_BASE,
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0s->irq[AW_H3_GIC_SPI_EHCI0]);
+=C2=A0 =C2=A0 sysbus_create_simple(TYPE_AW_H3_EHCI, AW_H3_EHCI1_BASE,
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0s->irq[AW_H3_GIC_SPI_EHCI1]);
+=C2=A0 =C2=A0 sysbus_create_simple(TYPE_AW_H3_EHCI, AW_H3_EHCI2_BASE,
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0s->irq[AW_H3_GIC_SPI_EHCI2]);
+=C2=A0 =C2=A0 sysbus_create_simple(TYPE_AW_H3_EHCI, AW_H3_EHCI3_BASE,
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0s->irq[AW_H3_GIC_SPI_EHCI3]);
+
+=C2=A0 =C2=A0 sysbus_create_simple("sysbus-ohci", AW_H3_OHCI0_BA= SE,
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0s->irq[AW_H3_GIC_SPI_OHCI0]);
+=C2=A0 =C2=A0 sysbus_create_simple("sysbus-ohci", AW_H3_OHCI1_BA= SE,
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0s->irq[AW_H3_GIC_SPI_OHCI1]);
+=C2=A0 =C2=A0 sysbus_create_simple("sysbus-ohci", AW_H3_OHCI2_BA= SE,
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0s->irq[AW_H3_GIC_SPI_OHCI2]);
+=C2=A0 =C2=A0 sysbus_create_simple("sysbus-ohci", AW_H3_OHCI3_BA= SE,
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0s->irq[AW_H3_GIC_SPI_OHCI3]);
+
=C2=A0 =C2=A0 =C2=A0/* UART */
=C2=A0 =C2=A0 =C2=A0if (serial_hd(0)) {
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0serial_mm_init(get_system_memory(), AW_H3= _UART0_REG_BASE, 2,
diff --git a/hw/usb/hcd-ehci-sysbus.c b/hw/usb/hcd-ehci-sysbus.c
index 020211fd10..174c3446ef 100644
--- a/hw/usb/hcd-ehci-sysbus.c
+++ b/hw/usb/hcd-ehci-sysbus.c
@@ -145,6 +145,22 @@ static const TypeInfo ehci_exynos4210_type_info =3D {<= br> =C2=A0 =C2=A0 =C2=A0.class_init=C2=A0 =C2=A0 =3D ehci_exynos4210_class_init= ,
=C2=A0};

+static void ehci_aw_h3_class_init(ObjectClass *oc, void *data)
+{
+=C2=A0 =C2=A0 SysBusEHCIClass *sec =3D SYS_BUS_EHCI_CLASS(oc);
+=C2=A0 =C2=A0 DeviceClass *dc =3D DEVICE_CLASS(oc);
+
+=C2=A0 =C2=A0 sec->capsbase =3D 0x0;
+=C2=A0 =C2=A0 sec->opregbase =3D 0x10;
+=C2=A0 =C2=A0 set_bit(DEVICE_CATEGORY_USB, dc->categories);
+}
+
+static const TypeInfo ehci_aw_h3_type_info =3D {
+=C2=A0 =C2=A0 .name=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =3D TYPE_AW_H3_EHCI,=
+=C2=A0 =C2=A0 .parent=C2=A0 =C2=A0 =C2=A0 =C2=A0 =3D TYPE_SYS_BUS_EHCI, +=C2=A0 =C2=A0 .class_init=C2=A0 =C2=A0 =3D ehci_aw_h3_class_init,
+};
+
=C2=A0static void ehci_tegra2_class_init(ObjectClass *oc, void *data)
=C2=A0{
=C2=A0 =C2=A0 =C2=A0SysBusEHCIClass *sec =3D SYS_BUS_EHCI_CLASS(oc);
@@ -267,6 +283,7 @@ static void ehci_sysbus_register_types(void)
=C2=A0 =C2=A0 =C2=A0type_register_static(&ehci_platform_type_info);
=C2=A0 =C2=A0 =C2=A0type_register_static(&ehci_xlnx_type_info);
=C2=A0 =C2=A0 =C2=A0type_register_static(&ehci_exynos4210_type_info); +=C2=A0 =C2=A0 type_register_static(&ehci_aw_h3_type_info);
=C2=A0 =C2=A0 =C2=A0type_register_static(&ehci_tegra2_type_info);
=C2=A0 =C2=A0 =C2=A0type_register_static(&ehci_ppc4xx_type_info);
=C2=A0 =C2=A0 =C2=A0type_register_static(&ehci_fusbh200_type_info);
diff --git a/hw/usb/hcd-ehci.h b/hw/usb/hcd-ehci.h
index 0298238f0b..edb59311c4 100644
--- a/hw/usb/hcd-ehci.h
+++ b/hw/usb/hcd-ehci.h
@@ -342,6 +342,7 @@ typedef struct EHCIPCIState {
=C2=A0#define TYPE_SYS_BUS_EHCI "sysbus-ehci-usb"
=C2=A0#define TYPE_PLATFORM_EHCI "platform-ehci-usb"
=C2=A0#define TYPE_EXYNOS4210_EHCI "exynos4210-ehci-usb"
+#define TYPE_AW_H3_EHCI "aw-h3-ehci-usb"
=C2=A0#define TYPE_TEGRA2_EHCI "tegra2-ehci-usb"
=C2=A0#define TYPE_PPC4xx_EHCI "ppc4xx-ehci-usb"
=C2=A0#define TYPE_FUSBH200_EHCI "fusbh200-ehci-usb"
--
2.17.1




--
Niek Linnenbank

--0000000000002753aa0598e68c8a-- From MAILER-DAEMON Wed Dec 04 15:34:46 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1icbME-0007S9-1f for mharc-qemu-arm@gnu.org; Wed, 04 Dec 2019 15:34:46 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:53650) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1icbMA-0007OK-Nm for qemu-arm@nongnu.org; Wed, 04 Dec 2019 15:34:44 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1icbM7-0003ZT-MH for qemu-arm@nongnu.org; Wed, 04 Dec 2019 15:34:41 -0500 Received: from us-smtp-delivery-1.mimecast.com ([207.211.31.120]:20170 helo=us-smtp-1.mimecast.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1icbM7-0003QS-5h for qemu-arm@nongnu.org; Wed, 04 Dec 2019 15:34:39 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1575491678; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=0WjFZOrzUSD4D64AXF+5lbkr3hRrlCI5J+kJa4yL5eU=; b=aLrwVkyPHOH7atg9qmuGrzRdfFCKboj/GBPFKtwBeqmxNl1x6FkC/eQXgCFzecOMEsVI1z Ux0aCf+fLZuiVNUdFFdQVl962135cuRpDLQXwUKoLJN3t5yvq7hBDP93YbJ/JVms0JoimU 4iP3Lv2lWAoUMUpcQOT4g2xvgeOiFtw= Received: from mail-wr1-f72.google.com (mail-wr1-f72.google.com [209.85.221.72]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-139-6HY856azOtu6ZGTrbogyXg-1; Wed, 04 Dec 2019 15:34:36 -0500 Received: by mail-wr1-f72.google.com with SMTP id 92so371155wro.14 for ; Wed, 04 Dec 2019 12:34:36 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:subject:to:cc:references:from:message-id:date :user-agent:mime-version:in-reply-to:content-language :content-transfer-encoding; bh=0WjFZOrzUSD4D64AXF+5lbkr3hRrlCI5J+kJa4yL5eU=; b=jp1qP7Hxe7NFH7go5RnkIEyMowSzho+0Rbmwzv+Ibg6hbm7PwuytJb8F4g1yXVA/6f EHQZJ4gDxbJZZwkm6OlEoatbdfnF/jfhiFTvefOB4M64t+hWLMNF6J3X1jO4izOwUVYb YVlMsknlXee8O2nlz/rTU+6KbXLTVHFG9mcyJHV61FJesHO/kf1/172d2T2SpGfYNKjw TaxK2Mya0ofYueK1KsVVGwmI0X9SnjkSNESyFagMwCzk8i9pTk7t5spc6ZaJPkwH4H6w 3D/UU4RzVla+SrYglZF092tarlHcZaS8Cl92VMWVsLAcytDtuCb2q2/II4V3QMx+6332 xQTw== X-Gm-Message-State: APjAAAUmtoKYN1lVcq0E2fvcew+pNcU1HFdj6856SwTWc6MmCxOB/Vkv ukx28eaPuHqekVg9myGASeFvjCpblfFwHSYFGqxmuFFfAM120GbCE44XIfCeMDExjo2W3Ql/Wv7 7IaByBqEp6z+L X-Received: by 2002:a7b:c357:: with SMTP id l23mr1560928wmj.152.1575491675175; Wed, 04 Dec 2019 12:34:35 -0800 (PST) X-Google-Smtp-Source: APXvYqybCVP4Urmi/mc3YP51QEjMnuUFUZnwy44YcMyL3d+XUzWbbR7Y7Rj7UjJwtr53R3oKo9ViWA== X-Received: by 2002:a7b:c357:: with SMTP id l23mr1560903wmj.152.1575491674896; Wed, 04 Dec 2019 12:34:34 -0800 (PST) Received: from [192.168.1.35] (182.red-88-21-103.staticip.rima-tde.net. [88.21.103.182]) by smtp.gmail.com with ESMTPSA id a20sm8173836wmd.19.2019.12.04.12.34.33 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 04 Dec 2019 12:34:34 -0800 (PST) Subject: Re: [PATCH v6 0/9] Clock framework API To: Damien Hedde , Peter Maydell Cc: QEMU Developers , Mark Burton , "Edgar E. Iglesias" , Alistair Francis , =?UTF-8?Q?Marc-Andr=c3=a9_Lureau?= , Paolo Bonzini , "Daniel P. Berrange" , Eduardo Habkost , qemu-arm References: <20190904125531.27545-1-damien.hedde@greensocs.com> From: =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= Message-ID: Date: Wed, 4 Dec 2019 21:34:33 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.2.2 MIME-Version: 1.0 In-Reply-To: Content-Language: en-US X-MC-Unique: 6HY856azOtu6ZGTrbogyXg-1 X-Mimecast-Spam-Score: 0 Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 7bit X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 207.211.31.120 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 04 Dec 2019 20:34:44 -0000 On 12/4/19 5:40 PM, Damien Hedde wrote: > On 12/2/19 5:15 PM, Peter Maydell wrote: >> >> The one topic I think we could do with discussing is whether >> a simple uint64_t giving the frequency of the clock in Hz is >> the right representation. In particular in your patch 9 the >> board has a clock frequency that's not a nice integer number >> of Hz. I think Philippe also mentioned on irc some board where >> the UART clock ends up at a weird frequency. Since the >> representation of the frequency is baked into the migration >> format it's going to be easier to get it right first rather >> than trying to change it later. Important precision for Damien, IIUC we can not migrate float/double types. >> So what should the representation be? Some random thoughts: >> >> 1) ptimer internally uses a 'period plus fraction' representation: >> int64_t period is the integer part of the period in nanoseconds, >> uint32_t period_frac is the fractional part of the period >> (if you like you can think of this as "96-bit integer >> period measured in units of one-2^32nd of a nanosecond"). >> However its only public interfaces for setting the frequency >> are (a) set the frequency in Hz (uint32_t) or (b) set >> the period in nanoseconds (int64_t); the period_frac part >> is used to handle frequencies which don't work out to >> a nice whole number of nanoseconds per cycle. This is very clear, thanks Peter! The period+period_frac split allow us to migrate the 96 bits: VMSTATE_UINT32(period_frac, ptimer_state), VMSTATE_INT64(period, ptimer_state), >> 2) I hear that SystemC uses "value plus a time unit", with >> the smallest unit being a picosecond. (I think SystemC >> also lets you specify the duty cycle, but we definitely >> don't want to get into that!) > > The "value" is internally stored in a 64bits unsigned integer. > >> >> 3) QEMUTimers are basically just nanosecond timers Similarly to SystemC, the QEMUTimers macro use a 'scale' unit, of: #define SCALE_MS 1000000 #define SCALE_US 1000 #define SCALE_NS 1 >> >> 4) The MAME emulator seems to work with periods of >> 96-bit attoseconds (represented internally by a >> 32-bit count of seconds plus a 64-bit count of >> attoseconds). One attosecond is 1e-18 seconds. >> >> Does anybody else have experience with other modelling >> or emulator technology and how it represents clocks ? > > 5) In linux, a clock rate is an "unsigned long" representing Hz. > >> >> I feel we should at least be able to represent clocks >> with the same accuracy that ptimer has. > > Then is a maybe a good idea to store the period and not the frequency in > clocks so that we don't loose anything when we switch from a clock to a > ptimer ? I think storing the period as an integer type is a good idea. However if we store the period in nanoseconds, we get at most 1GHz frequency. The attosecond granularity feels overkill. If we use a 96-bit integer to store picoseconds and use similar SCALE macros we get to 1THz. Regardless the unit chosen, as long it is integer, we can migrate it. If can migrate the period, we don't need to migrate the frequency. We can then use the float type in with the timer API to pass frequencies (which in the modeled hardware are ratios, likely not integers). So we could use set_freq(100e6 / 3), set_freq(40e6 / 5.5) directly. > Regarding the clock, I don't see any strong obstacle to switch > internally to a period based value. > The only things we have to choose is how to represent a disabled clock. > Since putting a "0" period to a ptimer will disable the timer in > ptimer_reload(). We can choose that (and it's a good value because we > can multiply or divide it, it stays the same). > > We could use the same representation as a ptimer. But if we don't keep a > C number representation, then computation of frequencies/periods will be > complicated at best and error prone. > > From that point of view, if we could stick to a 64bits integer (or > floating point number) it would be great. Can we use a sub nanosecond > unit that fit our needs ? > > I did some test with a unit of 2^-32 of nanoseconds on 64bits (is that > the unit of the ptimer fractional part ?) and if I'm not mistaken > + we have a frequency range from ~0.2Hz up to 10^18Hz > + the resolution is decreasing with the frequency (but at 100Mhz we have > a ~2.3mHz resolution, at 1GHz it's ~0.23Hz and at 10GHz ~23Hz > resolution). We hit 1Hz resolution around 2GHz. > > So it sounds to me we have largely enough resolution to model clocks in > the range of frequencies we will have to handle. What do you think ? Back to your series, I wonder why you want to store the frequency in ClockIn. ClockIn shouldn't be aware at what frequency it is clocked. What matters is ClockOut, and each device exposing ClockOuts has a (migrated) state of the output frequencies (rather in fields, or encoded in registers). Once migrated, after the state is loaded back into the device, we call post_load(). Isn't it a good place to call clock_set_frequency(ClockOut[]) which will correctly set each ClockIn frequency. IOW I don't think ClockIn/ClockOut require to migrate a frequency field. From MAILER-DAEMON Wed Dec 04 15:44:45 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1icbVt-0002kM-AN for mharc-qemu-arm@gnu.org; Wed, 04 Dec 2019 15:44:45 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:35174) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1icbVl-0002hE-1k for qemu-arm@nongnu.org; Wed, 04 Dec 2019 15:44:41 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1icbVd-0002Zp-Sq for qemu-arm@nongnu.org; Wed, 04 Dec 2019 15:44:34 -0500 Received: from mail-io1-xd33.google.com ([2607:f8b0:4864:20::d33]:39469) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1icbVO-00088q-Su; Wed, 04 Dec 2019 15:44:16 -0500 Received: by mail-io1-xd33.google.com with SMTP id c16so1107944ioh.6; Wed, 04 Dec 2019 12:44:12 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=R1VDfwEqKI50zMmWhp4rcTzePsgmgtT8/VwZES8y3oU=; b=UdCL+IIK8UVOOWZ4kWZ0mPwcp0oklIYMl9OrenLSdFhwLSMkq0X8VSMoJQ2JSPE5+H 0wJX9ici5qrEHmx8iaXF+2usczxLEMJiYTC2eKNzb3GjmCFLGiRnglXy/Yilu4JV5dpj LqlYCNaPVeN9/dosKpEN/neadPLBg5jekTl3SAf+b2SFcqXEfJNVDA6pjnKHrbOTWcWL 0nhHHG41gk0r+ArtIcFWDQNM2IyZwUe6Ht92xO2jikK+MS+ymhpTgK0Aqyb++3i8y/cV 8301A4lVLlCyYyBY0vKLv15ZEP2a0PT0I7jEbnPXQKIt1A4fszocF2yM6sD9I8R69rNM cBow== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=R1VDfwEqKI50zMmWhp4rcTzePsgmgtT8/VwZES8y3oU=; b=N2ZEud446UuXAXzE6dHBkL+yA/u/UxG1XqlyCKu1XZSt48A2DQU0YvKn94/KwbZh7n 606Ft0lwIfy7+29TTZj2RL3G/+EI+TEUeeIb7eBWiIYp3tTnEdck2ohIuWLWtUuhP+sE 3UQh2xMrTCMV3VtwXiVYBauAkE8mGqN6bywTCv4D1MdBax2SNdd1BWPuINIgieolOm1O IYOv5NC8RW4eH7aEdlbHtWqKts35vISPCHlFI1tAXLvgltFyjt0r/MtCncqQ8jkVyk0S 0hswhGt2cP0kCFmqnWxqf311T3dWyFzaAExzLxBfCEeoiUAiXbRRRwrovB8TtLDrOCe9 RyQQ== X-Gm-Message-State: APjAAAV2E5OzVwtLVMhoIGQ8XvlOSNjBdzWZa/sGUdtNpAlHy/5g/SrQ BCRQzY1TLtKMHExPcYsnxMdp9gNlVg88cWmSUwY= X-Google-Smtp-Source: APXvYqwqrVhGnAZc/YzlN5rBiK6KEnwQ/Fc5ng9nzWgxBms5YzuO1WvjQ94PQGG/TJVEcHtAQ5TMOzaPxPZBLnDqi2w= X-Received: by 2002:a6b:6f01:: with SMTP id k1mr3755274ioc.28.1575492251645; Wed, 04 Dec 2019 12:44:11 -0800 (PST) MIME-Version: 1.0 References: <20191202210947.3603-1-nieklinnenbank@gmail.com> <20191202210947.3603-2-nieklinnenbank@gmail.com> <5d3961ca-8586-6d93-2525-fd2e29b233e1@redhat.com> In-Reply-To: <5d3961ca-8586-6d93-2525-fd2e29b233e1@redhat.com> From: Niek Linnenbank Date: Wed, 4 Dec 2019 21:44:00 +0100 Message-ID: Subject: Re: [PATCH 01/10] hw: arm: add Allwinner H3 System-on-Chip To: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= Cc: qemu-devel@nongnu.org, b.galvani@gmail.com, Peter Maydell , qemu-arm@nongnu.org, Markus Armbruster Content-Type: multipart/alternative; boundary="000000000000017eb20598e6e057" X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::d33 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 04 Dec 2019 20:44:42 -0000 --000000000000017eb20598e6e057 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Hello Philippe, On Wed, Dec 4, 2019 at 5:53 PM Philippe Mathieu-Daud=C3=A9 wrote: > Hi Niek, > > On 12/2/19 10:09 PM, Niek Linnenbank wrote: > > The Allwinner H3 is a System on Chip containing four ARM Cortex A7 > > processor cores. Features and specifications include DDR2/DDR3 memory, > > SD/MMC storage cards, 10/100/1000Mbit ethernet, USB 2.0, HDMI and > > various I/O modules. This commit adds support for the Allwinner H3 > > System on Chip. > > > > Signed-off-by: Niek Linnenbank > > --- > > MAINTAINERS | 7 ++ > > default-configs/arm-softmmu.mak | 1 + > > hw/arm/Kconfig | 8 ++ > > hw/arm/Makefile.objs | 1 + > > hw/arm/allwinner-h3.c | 215 +++++++++++++++++++++++++++++++= + > > include/hw/arm/allwinner-h3.h | 118 ++++++++++++++++++ > > 6 files changed, 350 insertions(+) > > create mode 100644 hw/arm/allwinner-h3.c > > create mode 100644 include/hw/arm/allwinner-h3.h > > Since your series changes various files, can you have a look at the > scripts/git.orderfile file and setup it for your QEMU contributions? > OK, done! I didn't know such a script existed, thanks. I ran this command in my local repository: $ git config diff.orderFile scripts/git.orderfile It seems to work, when I re-generate the patches, the order of the diff is different. > > > > diff --git a/MAINTAINERS b/MAINTAINERS > > index 5e5e3e52d6..29c9936037 100644 > > --- a/MAINTAINERS > > +++ b/MAINTAINERS > > @@ -479,6 +479,13 @@ F: hw/*/allwinner* > > F: include/hw/*/allwinner* > > F: hw/arm/cubieboard.c > > > > +Allwinner-h3 > > +M: Niek Linnenbank > > +L: qemu-arm@nongnu.org > > +S: Maintained > > +F: hw/*/allwinner-h3* > > +F: include/hw/*/allwinner-h3* > > + > > ARM PrimeCell and CMSDK devices > > M: Peter Maydell > > L: qemu-arm@nongnu.org > > diff --git a/default-configs/arm-softmmu.mak > b/default-configs/arm-softmmu.mak > > index 1f2e0e7fde..d75a239c2c 100644 > > --- a/default-configs/arm-softmmu.mak > > +++ b/default-configs/arm-softmmu.mak > > @@ -40,3 +40,4 @@ CONFIG_FSL_IMX25=3Dy > > CONFIG_FSL_IMX7=3Dy > > CONFIG_FSL_IMX6UL=3Dy > > CONFIG_SEMIHOSTING=3Dy > > +CONFIG_ALLWINNER_H3=3Dy > > diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig > > index c6e7782580..ebf8d2325f 100644 > > --- a/hw/arm/Kconfig > > +++ b/hw/arm/Kconfig > > @@ -291,6 +291,14 @@ config ALLWINNER_A10 > > select SERIAL > > select UNIMP > > > > +config ALLWINNER_H3 > > + bool > > + select ALLWINNER_A10_PIT > > + select SERIAL > > + select ARM_TIMER > > + select ARM_GIC > > + select UNIMP > > + > > config RASPI > > bool > > select FRAMEBUFFER > > diff --git a/hw/arm/Makefile.objs b/hw/arm/Makefile.objs > > index fe749f65fd..956e496052 100644 > > --- a/hw/arm/Makefile.objs > > +++ b/hw/arm/Makefile.objs > > @@ -34,6 +34,7 @@ obj-$(CONFIG_DIGIC) +=3D digic.o > > obj-$(CONFIG_OMAP) +=3D omap1.o omap2.o > > obj-$(CONFIG_STRONGARM) +=3D strongarm.o > > obj-$(CONFIG_ALLWINNER_A10) +=3D allwinner-a10.o cubieboard.o > > +obj-$(CONFIG_ALLWINNER_H3) +=3D allwinner-h3.o > > obj-$(CONFIG_RASPI) +=3D bcm2835_peripherals.o bcm2836.o raspi.o > > obj-$(CONFIG_STM32F205_SOC) +=3D stm32f205_soc.o > > obj-$(CONFIG_XLNX_ZYNQMP_ARM) +=3D xlnx-zynqmp.o xlnx-zcu102.o > > diff --git a/hw/arm/allwinner-h3.c b/hw/arm/allwinner-h3.c > > new file mode 100644 > > index 0000000000..470fdfebef > > --- /dev/null > > +++ b/hw/arm/allwinner-h3.c > > @@ -0,0 +1,215 @@ > > +/* > > + * Allwinner H3 System on Chip emulation > > + * > > + * Copyright (C) 2019 Niek Linnenbank > > + * > > + * This program is free software: you can redistribute it and/or modif= y > > + * it under the terms of the GNU General Public License as published b= y > > + * the Free Software Foundation, either version 2 of the License, or > > + * (at your option) any later version. > > + * > > + * This program is distributed in the hope that it will be useful, > > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > > + * GNU General Public License for more details. > > + * > > + * You should have received a copy of the GNU General Public License > > + * along with this program. If not, see >. > > + */ > > + > > +#include "qemu/osdep.h" > > +#include "exec/address-spaces.h" > > +#include "qapi/error.h" > > +#include "qemu/module.h" > > +#include "qemu/units.h" > > +#include "cpu.h" > > +#include "hw/sysbus.h" > > +#include "hw/arm/allwinner-h3.h" > > +#include "hw/misc/unimp.h" > > +#include "sysemu/sysemu.h" > > + > > +static void aw_h3_init(Object *obj) > > +{ > > + AwH3State *s =3D AW_H3(obj); > > + > > + sysbus_init_child_obj(obj, "gic", &s->gic, sizeof(s->gic), > > + TYPE_ARM_GIC); > > + > > + sysbus_init_child_obj(obj, "timer", &s->timer, sizeof(s->timer), > > + TYPE_AW_A10_PIT); > > +} > > + > > +static void aw_h3_realize(DeviceState *dev, Error **errp) > > +{ > > + AwH3State *s =3D AW_H3(dev); > > + SysBusDevice *sysbusdev =3D NULL; > > + Error *err =3D NULL; > > + unsigned i =3D 0; > > + > > + /* CPUs */ > > + for (i =3D 0; i < AW_H3_NUM_CPUS; i++) { > > In https://www.mail-archive.com/qemu-devel@nongnu.org/msg662942.html > Markus noted some incorrect pattern, and apparently you inherited it. > You should initialize 'err' in the loop. > > > + Object *cpuobj =3D object_new(ARM_CPU_TYPE_NAME("cortex-a7")); > > + CPUState *cpustate =3D CPU(cpuobj); > > We loose access to the CPUs. Can you use an array of AW_H3_NUM_CPUS cpus > in AwH3State? > > > + > > + /* Set the proper CPU index */ > > + cpustate->cpu_index =3D i; > > + > > + /* Provide Power State Coordination Interface */ > > + object_property_set_int(cpuobj, QEMU_PSCI_CONDUIT_HVC, > > + "psci-conduit", &error_abort); > > Here you use the error_abort shortcut. > > > + > > + /* Disable secondary CPUs */ > > + object_property_set_bool(cpuobj, i > 0, "start-powered-off", > &err); > > + if (err !=3D NULL) { > > + error_propagate(errp, err); > > + return; > > Here you return. > > > + } > > + > > + /* All exception levels required */ > > + object_property_set_bool(cpuobj, > > + true, "has_el3", NULL); > > + object_property_set_bool(cpuobj, > > + true, "has_el2", NULL); > > Here you don't use error. > > Cc'ing Markus who is the expert, since he might have better suggestions. > > This function is called before the machine starts, and we are not > handling with user-provided configurations, so I'd say using > &error_abort in all places is OK. > > > + > > + /* Mark realized */ > > + object_property_set_bool(cpuobj, true, "realized", &err); > > + if (err !=3D NULL) { > > + error_propagate(errp, err); > > + return; > > + } > > + object_unref(cpuobj); > > + } > > + > > + /* Generic Interrupt Controller */ > > + qdev_prop_set_uint32(DEVICE(&s->gic), "num-irq", AW_H3_GIC_NUM_SPI= + > > + GIC_INTERNAL); > > + qdev_prop_set_uint32(DEVICE(&s->gic), "revision", 2); > > + qdev_prop_set_uint32(DEVICE(&s->gic), "num-cpu", AW_H3_NUM_CPUS); > > + qdev_prop_set_bit(DEVICE(&s->gic), "has-security-extensions", > false); > > + qdev_prop_set_bit(DEVICE(&s->gic), "has-virtualization-extensions"= , > true); > > + > > + object_property_set_bool(OBJECT(&s->gic), true, "realized", &err); > > Why change API? Can we use qdev_init_nofail() instead? > > > + if (err) { > > + error_propagate(errp, err); > > + return; > > + } > > + > > + sysbusdev =3D SYS_BUS_DEVICE(&s->gic); > > + sysbus_mmio_map(sysbusdev, 0, AW_H3_GIC_DIST_BASE); > > + sysbus_mmio_map(sysbusdev, 1, AW_H3_GIC_CPU_BASE); > > + sysbus_mmio_map(sysbusdev, 2, AW_H3_GIC_HYP_BASE); > > + sysbus_mmio_map(sysbusdev, 3, AW_H3_GIC_VCPU_BASE); > > + > > + /* > > + * Wire the outputs from each CPU's generic timer and the GICv3 > > + * maintenance interrupt signal to the appropriate GIC PPI inputs, > > + * and the GIC's IRQ/FIQ/VIRQ/VFIQ interrupt outputs to the CPU's > inputs. > > + */ > > + for (i =3D 0; i < AW_H3_NUM_CPUS; i++) { > > + DeviceState *cpudev =3D DEVICE(qemu_get_cpu(i)); > > + int ppibase =3D AW_H3_GIC_NUM_SPI + i * GIC_INTERNAL + > GIC_NR_SGIS; > > + int irq; > > + /* > > + * Mapping from the output timer irq lines from the CPU to the > > + * GIC PPI inputs used for this board. > > + */ > > + const int timer_irq[] =3D { > > + [GTIMER_PHYS] =3D AW_H3_GIC_PPI_ARM_PHYSTIMER, > > + [GTIMER_VIRT] =3D AW_H3_GIC_PPI_ARM_VIRTTIMER, > > + [GTIMER_HYP] =3D AW_H3_GIC_PPI_ARM_HYPTIMER, > > + [GTIMER_SEC] =3D AW_H3_GIC_PPI_ARM_SECTIMER, > > + }; > > + > > + /* Connect CPU timer outputs to GIC PPI inputs */ > > + for (irq =3D 0; irq < ARRAY_SIZE(timer_irq); irq++) { > > + qdev_connect_gpio_out(cpudev, irq, > > + qdev_get_gpio_in(DEVICE(&s->gic), > > + ppibase + > timer_irq[irq])); > > + } > > + > > + /* Connect GIC outputs to CPU interrupt inputs */ > > + sysbus_connect_irq(sysbusdev, i, > > + qdev_get_gpio_in(cpudev, ARM_CPU_IRQ)); > > + sysbus_connect_irq(sysbusdev, i + AW_H3_NUM_CPUS, > > + qdev_get_gpio_in(cpudev, ARM_CPU_FIQ)); > > + sysbus_connect_irq(sysbusdev, i + (2 * AW_H3_NUM_CPUS), > > + qdev_get_gpio_in(cpudev, ARM_CPU_VIRQ)); > > + sysbus_connect_irq(sysbusdev, i + (3 * AW_H3_NUM_CPUS), > > + qdev_get_gpio_in(cpudev, ARM_CPU_VFIQ)); > > + > > + /* GIC maintenance signal */ > > + sysbus_connect_irq(sysbusdev, i + (4 * AW_H3_NUM_CPUS), > > + qdev_get_gpio_in(DEVICE(&s->gic), > > + ppibase + > AW_H3_GIC_PPI_MAINT)); > > + } > > + > > + for (i =3D 0; i < AW_H3_GIC_NUM_SPI; i++) { > > + s->irq[i] =3D qdev_get_gpio_in(DEVICE(&s->gic), i); > > Apparently we don't need the irq array in AwH3State, because ... > > > + } > > + > > + /* Timer */ > > + object_property_set_bool(OBJECT(&s->timer), true, "realized", &err= ); > > + if (err !=3D NULL) { > > + error_propagate(errp, err); > > + return; > > + } > > + sysbusdev =3D SYS_BUS_DEVICE(&s->timer); > > + sysbus_mmio_map(sysbusdev, 0, AW_H3_PIT_REG_BASE); > > + sysbus_connect_irq(sysbusdev, 0, s->irq[AW_H3_GIC_SPI_TIMER0]); > > + sysbus_connect_irq(sysbusdev, 1, s->irq[AW_H3_GIC_SPI_TIMER1]); > > ... we can call qdev_get_gpio_in() here directly. > > > + > > + /* SRAM */ > > + memory_region_init_ram(&s->sram_a1, OBJECT(dev), "sram A1", > > + AW_H3_SRAM_A1_SIZE, &error_fatal); > > + memory_region_init_ram(&s->sram_a2, OBJECT(dev), "sram A2", > > + AW_H3_SRAM_A2_SIZE, &error_fatal); > > + memory_region_init_ram(&s->sram_c, OBJECT(dev), "sram C", > > + AW_H3_SRAM_C_SIZE, &error_fatal); > > + memory_region_add_subregion(get_system_memory(), AW_H3_SRAM_A1_BAS= E, > > + &s->sram_a1); > > + memory_region_add_subregion(get_system_memory(), AW_H3_SRAM_A2_BAS= E, > > + &s->sram_a2); > > + memory_region_add_subregion(get_system_memory(), AW_H3_SRAM_C_BASE= , > > + &s->sram_c); > > + > > + /* UART */ > > + if (serial_hd(0)) { > > + serial_mm_init(get_system_memory(), AW_H3_UART0_REG_BASE, 2, > > + s->irq[AW_H3_GIC_SPI_UART0], 115200, > serial_hd(0), > > qdev_get_gpio_in() here too. > > > + DEVICE_NATIVE_ENDIAN); > > + } > > + > > + /* Unimplemented devices */ > > + create_unimplemented_device("display-engine", AW_H3_DE_BASE, > AW_H3_DE_SIZE); > > + create_unimplemented_device("dma", AW_H3_DMA_BASE, AW_H3_DMA_SIZE)= ; > > + create_unimplemented_device("lcd0", AW_H3_LCD0_BASE, > AW_H3_LCD0_SIZE); > > + create_unimplemented_device("lcd1", AW_H3_LCD1_BASE, > AW_H3_LCD1_SIZE); > > + create_unimplemented_device("gpu", AW_H3_GPU_BASE, AW_H3_GPU_SIZE)= ; > > + create_unimplemented_device("hdmi", AW_H3_HDMI_BASE, > AW_H3_HDMI_SIZE); > > + create_unimplemented_device("rtc", AW_H3_RTC_BASE, AW_H3_RTC_SIZE)= ; > > + create_unimplemented_device("audio-codec", AW_H3_AC_BASE, > AW_H3_AC_SIZE); > > +} > > + > > +static void aw_h3_class_init(ObjectClass *oc, void *data) > > +{ > > + DeviceClass *dc =3D DEVICE_CLASS(oc); > > + > > + dc->realize =3D aw_h3_realize; > > + /* Reason: uses serial_hds and nd_table */ > > + dc->user_creatable =3D false; > > +} > > + > > +static const TypeInfo aw_h3_type_info =3D { > > + .name =3D TYPE_AW_H3, > > + .parent =3D TYPE_DEVICE, > > + .instance_size =3D sizeof(AwH3State), > > + .instance_init =3D aw_h3_init, > > + .class_init =3D aw_h3_class_init, > > +}; > > + > > +static void aw_h3_register_types(void) > > +{ > > + type_register_static(&aw_h3_type_info); > > +} > > + > > +type_init(aw_h3_register_types) > > diff --git a/include/hw/arm/allwinner-h3.h > b/include/hw/arm/allwinner-h3.h > > new file mode 100644 > > index 0000000000..af368c2254 > > --- /dev/null > > +++ b/include/hw/arm/allwinner-h3.h > > @@ -0,0 +1,118 @@ > > +/* > > + * Allwinner H3 System on Chip emulation > > + * > > + * Copyright (C) 2019 Niek Linnenbank > > + * > > + * This program is free software: you can redistribute it and/or modif= y > > + * it under the terms of the GNU General Public License as published b= y > > + * the Free Software Foundation, either version 2 of the License, or > > + * (at your option) any later version. > > + * > > + * This program is distributed in the hope that it will be useful, > > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > > + * GNU General Public License for more details. > > + * > > + * You should have received a copy of the GNU General Public License > > + * along with this program. If not, see >. > > + */ > > + > > +#ifndef HW_ARM_ALLWINNER_H3_H > > +#define HW_ARM_ALLWINNER_H3_H > > + > > +#include "qemu/error-report.h" > > +#include "qemu/units.h" > > +#include "hw/char/serial.h" > > +#include "hw/arm/boot.h" > > +#include "hw/timer/allwinner-a10-pit.h" > > +#include "hw/intc/arm_gic.h" > > +#include "target/arm/cpu.h" > > + > > +#define AW_H3_SRAM_A1_BASE (0x00000000) > > +#define AW_H3_SRAM_A2_BASE (0x00044000) > > +#define AW_H3_SRAM_C_BASE (0x00010000) > > +#define AW_H3_DE_BASE (0x01000000) > > +#define AW_H3_SYSCON_BASE (0x01c00000) > > +#define AW_H3_DMA_BASE (0x01c02000) > > +#define AW_H3_LCD0_BASE (0x01c0c000) > > +#define AW_H3_LCD1_BASE (0x01c0d000) > > +#define AW_H3_SID_BASE (0x01c14000) > > +#define AW_H3_CCU_BASE (0x01c20000) > > +#define AW_H3_PIC_REG_BASE (0x01c20400) > > +#define AW_H3_PIT_REG_BASE (0x01c20c00) > > +#define AW_H3_AC_BASE (0x01c22c00) > > +#define AW_H3_UART0_REG_BASE (0x01c28000) > > +#define AW_H3_EMAC_BASE (0x01c30000) > > +#define AW_H3_MMC0_BASE (0x01c0f000) > > +#define AW_H3_EHCI0_BASE (0x01c1a000) > > +#define AW_H3_OHCI0_BASE (0x01c1a400) > > +#define AW_H3_EHCI1_BASE (0x01c1b000) > > +#define AW_H3_OHCI1_BASE (0x01c1b400) > > +#define AW_H3_EHCI2_BASE (0x01c1c000) > > +#define AW_H3_OHCI2_BASE (0x01c1c400) > > +#define AW_H3_EHCI3_BASE (0x01c1d000) > > +#define AW_H3_OHCI3_BASE (0x01c1d400) > > +#define AW_H3_GPU_BASE (0x01c40000) > > +#define AW_H3_GIC_DIST_BASE (0x01c81000) > > +#define AW_H3_GIC_CPU_BASE (0x01c82000) > > +#define AW_H3_GIC_HYP_BASE (0x01c84000) > > +#define AW_H3_GIC_VCPU_BASE (0x01c86000) > > +#define AW_H3_HDMI_BASE (0x01ee0000) > > +#define AW_H3_RTC_BASE (0x01f00000) > > +#define AW_H3_CPUCFG_BASE (0x01f01c00) > > +#define AW_H3_SDRAM_BASE (0x40000000) > > + > > +#define AW_H3_SRAM_A1_SIZE (64 * KiB) > > +#define AW_H3_SRAM_A2_SIZE (32 * KiB) > > +#define AW_H3_SRAM_C_SIZE (44 * KiB) > > +#define AW_H3_DE_SIZE (4 * MiB) > > +#define AW_H3_DMA_SIZE (4 * KiB) > > +#define AW_H3_LCD0_SIZE (4 * KiB) > > +#define AW_H3_LCD1_SIZE (4 * KiB) > > +#define AW_H3_GPU_SIZE (64 * KiB) > > +#define AW_H3_HDMI_SIZE (128 * KiB) > > +#define AW_H3_RTC_SIZE (1 * KiB) > > +#define AW_H3_AC_SIZE (2 * KiB) > > + > > +#define AW_H3_GIC_PPI_MAINT (9) > > +#define AW_H3_GIC_PPI_ARM_HYPTIMER (10) > > +#define AW_H3_GIC_PPI_ARM_VIRTTIMER (11) > > +#define AW_H3_GIC_PPI_ARM_SECTIMER (13) > > +#define AW_H3_GIC_PPI_ARM_PHYSTIMER (14) > > + > > +#define AW_H3_GIC_SPI_UART0 (0) > > +#define AW_H3_GIC_SPI_TIMER0 (18) > > +#define AW_H3_GIC_SPI_TIMER1 (19) > > +#define AW_H3_GIC_SPI_MMC0 (60) > > +#define AW_H3_GIC_SPI_MMC1 (61) > > +#define AW_H3_GIC_SPI_MMC2 (62) > > +#define AW_H3_GIC_SPI_EHCI0 (72) > > +#define AW_H3_GIC_SPI_OHCI0 (73) > > +#define AW_H3_GIC_SPI_EHCI1 (74) > > +#define AW_H3_GIC_SPI_OHCI1 (75) > > +#define AW_H3_GIC_SPI_EHCI2 (76) > > +#define AW_H3_GIC_SPI_OHCI2 (77) > > +#define AW_H3_GIC_SPI_EHCI3 (78) > > +#define AW_H3_GIC_SPI_OHCI3 (79) > > +#define AW_H3_GIC_SPI_EMAC (82) > > I'd move half of the previous definitions into allwinner-h3.c, since > they are only used there. > > Indeed, you are right, I'll move them. Also, I'd use an enum for the PPI/SPI. > Thanks, I will process all of your comments above for the next patch version. > > > + > > +#define AW_H3_GIC_NUM_SPI (128) > > +#define AW_H3_NUM_CPUS (4) > > + > > +#define TYPE_AW_H3 "allwinner-h3" > > +#define AW_H3(obj) OBJECT_CHECK(AwH3State, (obj), TYPE_AW_H3) > > + > > +typedef struct AwH3State { > > + /*< private >*/ > > + DeviceState parent_obj; > > + /*< public >*/ > > + > > + qemu_irq irq[AW_H3_GIC_NUM_SPI]; > > + AwA10PITState timer; > > + GICState gic; > > + MemoryRegion sram_a1; > > + MemoryRegion sram_a2; > > + MemoryRegion sram_c; > > +} AwH3State; > > + > > +#endif > > > > Nice clean patch, for a first contribution :) > Thank you Philippe! Regards, Niek --=20 Niek Linnenbank --000000000000017eb20598e6e057 Content-Type: text/html; charset="UTF-8" Content-Transfer-Encoding: quoted-printable
Hello Philippe,

On Wed, Dec 4, 2019 at 5:53 PM Phi= lippe Mathieu-Daud=C3=A9 <philmd@re= dhat.com> wrote:
Hi Niek,

On 12/2/19 10:09 PM, Niek Linnenbank wrote:
> The Allwinner H3 is a System on Chip containing four ARM Cortex A7
> processor cores. Features and specifications include DDR2/DDR3 memory,=
> SD/MMC storage cards, 10/100/1000Mbit ethernet, USB 2.0, HDMI and
> various I/O modules. This commit adds support for the Allwinner H3
> System on Chip.
>
> Signed-off-by: Niek Linnenbank <nieklinnenbank@gmail.com>
> ---
>=C2=A0 =C2=A0MAINTAINERS=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0|=C2=A0 =C2=A07 ++
>=C2=A0 =C2=A0default-configs/arm-softmmu.mak |=C2=A0 =C2=A01 +
>=C2=A0 =C2=A0hw/arm/Kconfig=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 |=C2=A0 =C2=A08 ++
>=C2=A0 =C2=A0hw/arm/Makefile.objs=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 |=C2=A0 =C2=A01 +
>=C2=A0 =C2=A0hw/arm/allwinner-h3.c=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0| 215 ++++++++++++++++++++++++++++++++
>=C2=A0 =C2=A0include/hw/arm/allwinner-h3.h=C2=A0 =C2=A0| 118 ++++++++++= ++++++++
>=C2=A0 =C2=A06 files changed, 350 insertions(+)
>=C2=A0 =C2=A0create mode 100644 hw/arm/allwinner-h3.c
>=C2=A0 =C2=A0create mode 100644 include/hw/arm/allwinner-h3.h

Since your series changes various files, can you have a look at the
scripts/git.orderfile file and setup it for your QEMU contributions?

OK, done! I didn't know such a script exi= sted, thanks.
I ran this command in my local repository:
=C2=A0$ git config diff.orderFile scripts/git.orderfile
It = seems to work, when I re-generate the patches, the order of the diff is dif= ferent.
=C2=A0


>
> diff --git a/MAINTAINERS b/MAINTAINERS
> index 5e5e3e52d6..29c9936037 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -479,6 +479,13 @@ F: hw/*/allwinner*
>=C2=A0 =C2=A0F: include/hw/*/allwinner*
>=C2=A0 =C2=A0F: hw/arm/cubieboard.c
>=C2=A0 =C2=A0
> +Allwinner-h3
> +M: Niek Linnenbank <nieklinnenbank@gmail.com>
> +L: qemu-arm@= nongnu.org
> +S: Maintained
> +F: hw/*/allwinner-h3*
> +F: include/hw/*/allwinner-h3*
> +
>=C2=A0 =C2=A0ARM PrimeCell and CMSDK devices
>=C2=A0 =C2=A0M: Peter Maydell <peter.maydell@linaro.org>
>=C2=A0 =C2=A0L: qemu-arm@nongnu.org
> diff --git a/default-configs/arm-softmmu.mak b/default-configs/arm-sof= tmmu.mak
> index 1f2e0e7fde..d75a239c2c 100644
> --- a/default-configs/arm-softmmu.mak
> +++ b/default-configs/arm-softmmu.mak
> @@ -40,3 +40,4 @@ CONFIG_FSL_IMX25=3Dy
>=C2=A0 =C2=A0CONFIG_FSL_IMX7=3Dy
>=C2=A0 =C2=A0CONFIG_FSL_IMX6UL=3Dy
>=C2=A0 =C2=A0CONFIG_SEMIHOSTING=3Dy
> +CONFIG_ALLWINNER_H3=3Dy
> diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig
> index c6e7782580..ebf8d2325f 100644
> --- a/hw/arm/Kconfig
> +++ b/hw/arm/Kconfig
> @@ -291,6 +291,14 @@ config ALLWINNER_A10
>=C2=A0 =C2=A0 =C2=A0 =C2=A0select SERIAL
>=C2=A0 =C2=A0 =C2=A0 =C2=A0select UNIMP
>=C2=A0 =C2=A0
> +config ALLWINNER_H3
> +=C2=A0 =C2=A0 bool
> +=C2=A0 =C2=A0 select ALLWINNER_A10_PIT
> +=C2=A0 =C2=A0 select SERIAL
> +=C2=A0 =C2=A0 select ARM_TIMER
> +=C2=A0 =C2=A0 select ARM_GIC
> +=C2=A0 =C2=A0 select UNIMP
> +
>=C2=A0 =C2=A0config RASPI
>=C2=A0 =C2=A0 =C2=A0 =C2=A0bool
>=C2=A0 =C2=A0 =C2=A0 =C2=A0select FRAMEBUFFER
> diff --git a/hw/arm/Makefile.objs b/hw/arm/Makefile.objs
> index fe749f65fd..956e496052 100644
> --- a/hw/arm/Makefile.objs
> +++ b/hw/arm/Makefile.objs
> @@ -34,6 +34,7 @@ obj-$(CONFIG_DIGIC) +=3D digic.o
>=C2=A0 =C2=A0obj-$(CONFIG_OMAP) +=3D omap1.o omap2.o
>=C2=A0 =C2=A0obj-$(CONFIG_STRONGARM) +=3D strongarm.o
>=C2=A0 =C2=A0obj-$(CONFIG_ALLWINNER_A10) +=3D allwinner-a10.o cubieboar= d.o
> +obj-$(CONFIG_ALLWINNER_H3) +=3D allwinner-h3.o
>=C2=A0 =C2=A0obj-$(CONFIG_RASPI) +=3D bcm2835_peripherals.o bcm2836.o r= aspi.o
>=C2=A0 =C2=A0obj-$(CONFIG_STM32F205_SOC) +=3D stm32f205_soc.o
>=C2=A0 =C2=A0obj-$(CONFIG_XLNX_ZYNQMP_ARM) +=3D xlnx-zynqmp.o xlnx-zcu1= 02.o
> diff --git a/hw/arm/allwinner-h3.c b/hw/arm/allwinner-h3.c
> new file mode 100644
> index 0000000000..470fdfebef
> --- /dev/null
> +++ b/hw/arm/allwinner-h3.c
> @@ -0,0 +1,215 @@
> +/*
> + * Allwinner H3 System on Chip emulation
> + *
> + * Copyright (C) 2019 Niek Linnenbank <nieklinnenbank@gmail.com>
> + *
> + * This program is free software: you can redistribute it and/or modi= fy
> + * it under the terms of the GNU General Public License as published = by
> + * the Free Software Foundation, either version 2 of the License, or<= br> > + * (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful, > + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.=C2=A0 See the=
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License<= br> > + * along with this program.=C2=A0 If not, see <http://www.gnu.o= rg/licenses/>.
> + */
> +
> +#include "qemu/osdep.h"
> +#include "exec/address-spaces.h"
> +#include "qapi/error.h"
> +#include "qemu/module.h"
> +#include "qemu/units.h"
> +#include "cpu.h"
> +#include "hw/sysbus.h"
> +#include "hw/arm/allwinner-h3.h"
> +#include "hw/misc/unimp.h"
> +#include "sysemu/sysemu.h"
> +
> +static void aw_h3_init(Object *obj)
> +{
> +=C2=A0 =C2=A0 AwH3State *s =3D AW_H3(obj);
> +
> +=C2=A0 =C2=A0 sysbus_init_child_obj(obj, "gic", &s->= gic, sizeof(s->gic),
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0 =C2=A0 TYPE_ARM_GIC);
> +
> +=C2=A0 =C2=A0 sysbus_init_child_obj(obj, "timer", &s-&g= t;timer, sizeof(s->timer),
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0 =C2=A0 TYPE_AW_A10_PIT);
> +}
> +
> +static void aw_h3_realize(DeviceState *dev, Error **errp)
> +{
> +=C2=A0 =C2=A0 AwH3State *s =3D AW_H3(dev);
> +=C2=A0 =C2=A0 SysBusDevice *sysbusdev =3D NULL;
> +=C2=A0 =C2=A0 Error *err =3D NULL;
> +=C2=A0 =C2=A0 unsigned i =3D 0;
> +
> +=C2=A0 =C2=A0 /* CPUs */
> +=C2=A0 =C2=A0 for (i =3D 0; i < AW_H3_NUM_CPUS; i++) {

In https://www.mail-archive.com/qem= u-devel@nongnu.org/msg662942.html
Markus noted some incorrect pattern, and apparently you inherited it.
You should initialize 'err' in the loop.

> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 Object *cpuobj =3D object_new(ARM_CPU_TYP= E_NAME("cortex-a7"));
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 CPUState *cpustate =3D CPU(cpuobj);

We loose access to the CPUs. Can you use an array of AW_H3_NUM_CPUS cpus in AwH3State?

> +
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 /* Set the proper CPU index */
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 cpustate->cpu_index =3D i;
> +
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 /* Provide Power State Coordination Inter= face */
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 object_property_set_int(cpuobj, QEMU_PSCI= _CONDUIT_HVC,
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 "psci-conduit", &e= rror_abort);

Here you use the error_abort shortcut.

> +
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 /* Disable secondary CPUs */
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 object_property_set_bool(cpuobj, i > 0= , "start-powered-off", &err);
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 if (err !=3D NULL) {
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 error_propagate(errp, err);=
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 return;

Here you return.

> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 }
> +
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 /* All exception levels required */
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 object_property_set_bool(cpuobj,
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0true, "has_el3",= NULL);
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 object_property_set_bool(cpuobj,
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0true, "has_el2",= NULL);

Here you don't use error.

Cc'ing Markus who is the expert, since he might have better suggestions= .

This function is called before the machine starts, and we are not
handling with user-provided configurations, so I'd say using
&error_abort in all places is OK.

> +
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 /* Mark realized */
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 object_property_set_bool(cpuobj, true, &q= uot;realized", &err);
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 if (err !=3D NULL) {
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 error_propagate(errp, err);=
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 return;
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 }
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 object_unref(cpuobj);
> +=C2=A0 =C2=A0 }
> +
> +=C2=A0 =C2=A0 /* Generic Interrupt Controller */
> +=C2=A0 =C2=A0 qdev_prop_set_uint32(DEVICE(&s->gic), "num-= irq", AW_H3_GIC_NUM_SPI +
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0GIC_INTERNAL);
> +=C2=A0 =C2=A0 qdev_prop_set_uint32(DEVICE(&s->gic), "revi= sion", 2);
> +=C2=A0 =C2=A0 qdev_prop_set_uint32(DEVICE(&s->gic), "num-= cpu", AW_H3_NUM_CPUS);
> +=C2=A0 =C2=A0 qdev_prop_set_bit(DEVICE(&s->gic), "has-sec= urity-extensions", false);
> +=C2=A0 =C2=A0 qdev_prop_set_bit(DEVICE(&s->gic), "has-vir= tualization-extensions", true);
> +
> +=C2=A0 =C2=A0 object_property_set_bool(OBJECT(&s->gic), true, = "realized", &err);

Why change API? Can we use qdev_init_nofail() instead?

> +=C2=A0 =C2=A0 if (err) {
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 error_propagate(errp, err);
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 return;
> +=C2=A0 =C2=A0 }
> +
> +=C2=A0 =C2=A0 sysbusdev =3D SYS_BUS_DEVICE(&s->gic);
> +=C2=A0 =C2=A0 sysbus_mmio_map(sysbusdev, 0, AW_H3_GIC_DIST_BASE);
> +=C2=A0 =C2=A0 sysbus_mmio_map(sysbusdev, 1, AW_H3_GIC_CPU_BASE);
> +=C2=A0 =C2=A0 sysbus_mmio_map(sysbusdev, 2, AW_H3_GIC_HYP_BASE);
> +=C2=A0 =C2=A0 sysbus_mmio_map(sysbusdev, 3, AW_H3_GIC_VCPU_BASE);
> +
> +=C2=A0 =C2=A0 /*
> +=C2=A0 =C2=A0 =C2=A0* Wire the outputs from each CPU's generic ti= mer and the GICv3
> +=C2=A0 =C2=A0 =C2=A0* maintenance interrupt signal to the appropriate= GIC PPI inputs,
> +=C2=A0 =C2=A0 =C2=A0* and the GIC's IRQ/FIQ/VIRQ/VFIQ interrupt o= utputs to the CPU's inputs.
> +=C2=A0 =C2=A0 =C2=A0*/
> +=C2=A0 =C2=A0 for (i =3D 0; i < AW_H3_NUM_CPUS; i++) {
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 DeviceState *cpudev =3D DEVICE(qemu_get_c= pu(i));
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 int ppibase =3D AW_H3_GIC_NUM_SPI + i * G= IC_INTERNAL + GIC_NR_SGIS;
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 int irq;
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 /*
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0* Mapping from the output timer irq= lines from the CPU to the
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0* GIC PPI inputs used for this boar= d.
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0*/
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 const int timer_irq[] =3D {
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 [GTIMER_PHYS] =3D AW_H3_GIC= _PPI_ARM_PHYSTIMER,
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 [GTIMER_VIRT] =3D AW_H3_GIC= _PPI_ARM_VIRTTIMER,
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 [GTIMER_HYP]=C2=A0 =3D AW_H= 3_GIC_PPI_ARM_HYPTIMER,
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 [GTIMER_SEC]=C2=A0 =3D AW_H= 3_GIC_PPI_ARM_SECTIMER,
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 };
> +
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 /* Connect CPU timer outputs to GIC PPI i= nputs */
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 for (irq =3D 0; irq < ARRAY_SIZE(timer= _irq); irq++) {
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 qdev_connect_gpio_out(cpude= v, irq,
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 qdev_get_gpio_in(DEVICE(&= amp;s->gic),
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0ppibase + timer_irq[irq]));
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 }
> +
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 /* Connect GIC outputs to CPU interrupt i= nputs */
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 sysbus_connect_irq(sysbusdev, i,
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0 =C2=A0 =C2=A0qdev_get_gpio_in(cpudev, ARM_CPU_IRQ));
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 sysbus_connect_irq(sysbusdev, i + AW_H3_N= UM_CPUS,
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0 =C2=A0 =C2=A0qdev_get_gpio_in(cpudev, ARM_CPU_FIQ));
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 sysbus_connect_irq(sysbusdev, i + (2 * AW= _H3_NUM_CPUS),
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0 =C2=A0 =C2=A0qdev_get_gpio_in(cpudev, ARM_CPU_VIRQ));
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 sysbus_connect_irq(sysbusdev, i + (3 * AW= _H3_NUM_CPUS),
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0 =C2=A0 =C2=A0qdev_get_gpio_in(cpudev, ARM_CPU_VFIQ));
> +
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 /* GIC maintenance signal */
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 sysbus_connect_irq(sysbusdev, i + (4 * AW= _H3_NUM_CPUS),
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0 =C2=A0 =C2=A0qdev_get_gpio_in(DEVICE(&s->gic),
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 ppibase + AW_H3_GIC_PPI_MAINT));
> +=C2=A0 =C2=A0 }
> +
> +=C2=A0 =C2=A0 for (i =3D 0; i < AW_H3_GIC_NUM_SPI; i++) {
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 s->irq[i] =3D qdev_get_gpio_in(DEVICE(= &s->gic), i);

Apparently we don't need the irq array in AwH3State, because ...

> +=C2=A0 =C2=A0 }
> +
> +=C2=A0 =C2=A0 /* Timer */
> +=C2=A0 =C2=A0 object_property_set_bool(OBJECT(&s->timer), true= , "realized", &err);
> +=C2=A0 =C2=A0 if (err !=3D NULL) {
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 error_propagate(errp, err);
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 return;
> +=C2=A0 =C2=A0 }
> +=C2=A0 =C2=A0 sysbusdev =3D SYS_BUS_DEVICE(&s->timer);
> +=C2=A0 =C2=A0 sysbus_mmio_map(sysbusdev, 0, AW_H3_PIT_REG_BASE);
> +=C2=A0 =C2=A0 sysbus_connect_irq(sysbusdev, 0, s->irq[AW_H3_GIC_SP= I_TIMER0]);
> +=C2=A0 =C2=A0 sysbus_connect_irq(sysbusdev, 1, s->irq[AW_H3_GIC_SP= I_TIMER1]);

... we can call qdev_get_gpio_in() here directly.

> +
> +=C2=A0 =C2=A0 /* SRAM */
> +=C2=A0 =C2=A0 memory_region_init_ram(&s->sram_a1, OBJECT(dev),= "sram A1",
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0 =C2=A0 =C2=A0 AW_H3_SRAM_A1_SIZE, &error_fatal);
> +=C2=A0 =C2=A0 memory_region_init_ram(&s->sram_a2, OBJECT(dev),= "sram A2",
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0 =C2=A0 =C2=A0 AW_H3_SRAM_A2_SIZE, &error_fatal);
> +=C2=A0 =C2=A0 memory_region_init_ram(&s->sram_c, OBJECT(dev), = "sram C",
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0 =C2=A0 =C2=A0 AW_H3_SRAM_C_SIZE, &error_fatal);
> +=C2=A0 =C2=A0 memory_region_add_subregion(get_system_memory(), AW_H3_= SRAM_A1_BASE,
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 &s->sram_a1);
> +=C2=A0 =C2=A0 memory_region_add_subregion(get_system_memory(), AW_H3_= SRAM_A2_BASE,
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 &s->sram_a2);
> +=C2=A0 =C2=A0 memory_region_add_subregion(get_system_memory(), AW_H3_= SRAM_C_BASE,
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 &s->sram_c);
> +
> +=C2=A0 =C2=A0 /* UART */
> +=C2=A0 =C2=A0 if (serial_hd(0)) {
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 serial_mm_init(get_system_memory(), AW_H3= _UART0_REG_BASE, 2,
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0s->irq[AW_H3_GIC_SPI_UART0], 115200, serial_hd(0),

qdev_get_gpio_in() here too.

> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0DEVICE_NATIVE_ENDIAN);
> +=C2=A0 =C2=A0 }
> +
> +=C2=A0 =C2=A0 /* Unimplemented devices */
> +=C2=A0 =C2=A0 create_unimplemented_device("display-engine",= AW_H3_DE_BASE, AW_H3_DE_SIZE);
> +=C2=A0 =C2=A0 create_unimplemented_device("dma", AW_H3_DMA_= BASE, AW_H3_DMA_SIZE);
> +=C2=A0 =C2=A0 create_unimplemented_device("lcd0", AW_H3_LCD= 0_BASE, AW_H3_LCD0_SIZE);
> +=C2=A0 =C2=A0 create_unimplemented_device("lcd1", AW_H3_LCD= 1_BASE, AW_H3_LCD1_SIZE);
> +=C2=A0 =C2=A0 create_unimplemented_device("gpu", AW_H3_GPU_= BASE, AW_H3_GPU_SIZE);
> +=C2=A0 =C2=A0 create_unimplemented_device("hdmi", AW_H3_HDM= I_BASE, AW_H3_HDMI_SIZE);
> +=C2=A0 =C2=A0 create_unimplemented_device("rtc", AW_H3_RTC_= BASE, AW_H3_RTC_SIZE);
> +=C2=A0 =C2=A0 create_unimplemented_device("audio-codec", AW= _H3_AC_BASE, AW_H3_AC_SIZE);
> +}
> +
> +static void aw_h3_class_init(ObjectClass *oc, void *data)
> +{
> +=C2=A0 =C2=A0 DeviceClass *dc =3D DEVICE_CLASS(oc);
> +
> +=C2=A0 =C2=A0 dc->realize =3D aw_h3_realize;
> +=C2=A0 =C2=A0 /* Reason: uses serial_hds and nd_table */
> +=C2=A0 =C2=A0 dc->user_creatable =3D false;
> +}
> +
> +static const TypeInfo aw_h3_type_info =3D {
> +=C2=A0 =C2=A0 .name =3D TYPE_AW_H3,
> +=C2=A0 =C2=A0 .parent =3D TYPE_DEVICE,
> +=C2=A0 =C2=A0 .instance_size =3D sizeof(AwH3State),
> +=C2=A0 =C2=A0 .instance_init =3D aw_h3_init,
> +=C2=A0 =C2=A0 .class_init =3D aw_h3_class_init,
> +};
> +
> +static void aw_h3_register_types(void)
> +{
> +=C2=A0 =C2=A0 type_register_static(&aw_h3_type_info);
> +}
> +
> +type_init(aw_h3_register_types)
> diff --git a/include/hw/arm/allwinner-h3.h b/include/hw/arm/allwinner-= h3.h
> new file mode 100644
> index 0000000000..af368c2254
> --- /dev/null
> +++ b/include/hw/arm/allwinner-h3.h
> @@ -0,0 +1,118 @@
> +/*
> + * Allwinner H3 System on Chip emulation
> + *
> + * Copyright (C) 2019 Niek Linnenbank <nieklinnenbank@gmail.com>
> + *
> + * This program is free software: you can redistribute it and/or modi= fy
> + * it under the terms of the GNU General Public License as published = by
> + * the Free Software Foundation, either version 2 of the License, or<= br> > + * (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful, > + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.=C2=A0 See the=
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License<= br> > + * along with this program.=C2=A0 If not, see <http://www.gnu.o= rg/licenses/>.
> + */
> +
> +#ifndef HW_ARM_ALLWINNER_H3_H
> +#define HW_ARM_ALLWINNER_H3_H
> +
> +#include "qemu/error-report.h"
> +#include "qemu/units.h"
> +#include "hw/char/serial.h"
> +#include "hw/arm/boot.h"
> +#include "hw/timer/allwinner-a10-pit.h"
> +#include "hw/intc/arm_gic.h"
> +#include "target/arm/cpu.h"
> +
> +#define AW_H3_SRAM_A1_BASE=C2=A0 =C2=A0 =C2=A0(0x00000000)
> +#define AW_H3_SRAM_A2_BASE=C2=A0 =C2=A0 =C2=A0(0x00044000)
> +#define AW_H3_SRAM_C_BASE=C2=A0 =C2=A0 =C2=A0 (0x00010000)
> +#define AW_H3_DE_BASE=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 (0x01000000)<= br> > +#define AW_H3_SYSCON_BASE=C2=A0 =C2=A0 =C2=A0 (0x01c00000)
> +#define AW_H3_DMA_BASE=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0(0x01c02000)<= br> > +#define AW_H3_LCD0_BASE=C2=A0 =C2=A0 =C2=A0 =C2=A0 (0x01c0c000)
> +#define AW_H3_LCD1_BASE=C2=A0 =C2=A0 =C2=A0 =C2=A0 (0x01c0d000)
> +#define AW_H3_SID_BASE=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0(0x01c14000)<= br> > +#define AW_H3_CCU_BASE=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0(0x01c20000)<= br> > +#define AW_H3_PIC_REG_BASE=C2=A0 =C2=A0 =C2=A0(0x01c20400)
> +#define AW_H3_PIT_REG_BASE=C2=A0 =C2=A0 =C2=A0(0x01c20c00)
> +#define AW_H3_AC_BASE=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 (0x01c22c00)<= br> > +#define AW_H3_UART0_REG_BASE=C2=A0 =C2=A0(0x01c28000)
> +#define AW_H3_EMAC_BASE=C2=A0 =C2=A0 =C2=A0 =C2=A0 (0x01c30000)
> +#define AW_H3_MMC0_BASE=C2=A0 =C2=A0 =C2=A0 =C2=A0 (0x01c0f000)
> +#define AW_H3_EHCI0_BASE=C2=A0 =C2=A0 =C2=A0 =C2=A0(0x01c1a000)
> +#define AW_H3_OHCI0_BASE=C2=A0 =C2=A0 =C2=A0 =C2=A0(0x01c1a400)
> +#define AW_H3_EHCI1_BASE=C2=A0 =C2=A0 =C2=A0 =C2=A0(0x01c1b000)
> +#define AW_H3_OHCI1_BASE=C2=A0 =C2=A0 =C2=A0 =C2=A0(0x01c1b400)
> +#define AW_H3_EHCI2_BASE=C2=A0 =C2=A0 =C2=A0 =C2=A0(0x01c1c000)
> +#define AW_H3_OHCI2_BASE=C2=A0 =C2=A0 =C2=A0 =C2=A0(0x01c1c400)
> +#define AW_H3_EHCI3_BASE=C2=A0 =C2=A0 =C2=A0 =C2=A0(0x01c1d000)
> +#define AW_H3_OHCI3_BASE=C2=A0 =C2=A0 =C2=A0 =C2=A0(0x01c1d400)
> +#define AW_H3_GPU_BASE=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0(0x01c40000)<= br> > +#define AW_H3_GIC_DIST_BASE=C2=A0 =C2=A0 (0x01c81000)
> +#define AW_H3_GIC_CPU_BASE=C2=A0 =C2=A0 =C2=A0(0x01c82000)
> +#define AW_H3_GIC_HYP_BASE=C2=A0 =C2=A0 =C2=A0(0x01c84000)
> +#define AW_H3_GIC_VCPU_BASE=C2=A0 =C2=A0 (0x01c86000)
> +#define AW_H3_HDMI_BASE=C2=A0 =C2=A0 =C2=A0 =C2=A0 (0x01ee0000)
> +#define AW_H3_RTC_BASE=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0(0x01f00000)<= br> > +#define AW_H3_CPUCFG_BASE=C2=A0 =C2=A0 =C2=A0 (0x01f01c00)
> +#define AW_H3_SDRAM_BASE=C2=A0 =C2=A0 =C2=A0 =C2=A0(0x40000000)
> +
> +#define AW_H3_SRAM_A1_SIZE=C2=A0 =C2=A0 =C2=A0(64 * KiB)
> +#define AW_H3_SRAM_A2_SIZE=C2=A0 =C2=A0 =C2=A0(32 * KiB)
> +#define AW_H3_SRAM_C_SIZE=C2=A0 =C2=A0 =C2=A0 (44 * KiB)
> +#define AW_H3_DE_SIZE=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 (4 * MiB)
> +#define AW_H3_DMA_SIZE=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0(4 * KiB)
> +#define AW_H3_LCD0_SIZE=C2=A0 =C2=A0 =C2=A0 =C2=A0 (4 * KiB)
> +#define AW_H3_LCD1_SIZE=C2=A0 =C2=A0 =C2=A0 =C2=A0 (4 * KiB)
> +#define AW_H3_GPU_SIZE=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0(64 * KiB) > +#define AW_H3_HDMI_SIZE=C2=A0 =C2=A0 =C2=A0 =C2=A0 (128 * KiB)
> +#define AW_H3_RTC_SIZE=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0(1 * KiB)
> +#define AW_H3_AC_SIZE=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 (2 * KiB)
> +
> +#define AW_H3_GIC_PPI_MAINT=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 (9)
> +#define AW_H3_GIC_PPI_ARM_HYPTIMER=C2=A0 (10)
> +#define AW_H3_GIC_PPI_ARM_VIRTTIMER (11)
> +#define AW_H3_GIC_PPI_ARM_SECTIMER=C2=A0 (13)
> +#define AW_H3_GIC_PPI_ARM_PHYSTIMER (14)
> +
> +#define AW_H3_GIC_SPI_UART0=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0(0)
> +#define AW_H3_GIC_SPI_TIMER0=C2=A0 =C2=A0 =C2=A0 =C2=A0 (18)
> +#define AW_H3_GIC_SPI_TIMER1=C2=A0 =C2=A0 =C2=A0 =C2=A0 (19)
> +#define AW_H3_GIC_SPI_MMC0=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 (60)
> +#define AW_H3_GIC_SPI_MMC1=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 (61)
> +#define AW_H3_GIC_SPI_MMC2=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 (62)
> +#define AW_H3_GIC_SPI_EHCI0=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0(72)
> +#define AW_H3_GIC_SPI_OHCI0=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0(73)
> +#define AW_H3_GIC_SPI_EHCI1=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0(74)
> +#define AW_H3_GIC_SPI_OHCI1=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0(75)
> +#define AW_H3_GIC_SPI_EHCI2=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0(76)
> +#define AW_H3_GIC_SPI_OHCI2=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0(77)
> +#define AW_H3_GIC_SPI_EHCI3=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0(78)
> +#define AW_H3_GIC_SPI_OHCI3=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0(79)
> +#define AW_H3_GIC_SPI_EMAC=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 (82)

I'd move half of the previous definitions into allwinner-h3.c, since they are only used there.

Indeed, you are right, I'll move them.
<= div>
Also, I'd use an enum for the PPI/SPI.

=
Thanks, I will process all of your comments above for the = next patch version.
=C2=A0
=C2=A0
> +
> +#define AW_H3_GIC_NUM_SPI=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0(12= 8)
> +#define AW_H3_NUM_CPUS=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 (4)
> +
> +#define TYPE_AW_H3 "allwinner-h3"
> +#define AW_H3(obj) OBJECT_CHECK(AwH3State, (obj), TYPE_AW_H3)
> +
> +typedef struct AwH3State {
> +=C2=A0 =C2=A0 /*< private >*/
> +=C2=A0 =C2=A0 DeviceState parent_obj;
> +=C2=A0 =C2=A0 /*< public >*/
> +
> +=C2=A0 =C2=A0 qemu_irq irq[AW_H3_GIC_NUM_SPI];
> +=C2=A0 =C2=A0 AwA10PITState timer;
> +=C2=A0 =C2=A0 GICState gic;
> +=C2=A0 =C2=A0 MemoryRegion sram_a1;
> +=C2=A0 =C2=A0 MemoryRegion sram_a2;
> +=C2=A0 =C2=A0 MemoryRegion sram_c;
> +} AwH3State;
> +
> +#endif
>

Nice clean patch, for a first contribution :)

Thank you Philippe!=C2=A0

Regard= s,
Niek

--
Niek Linnenbank

--000000000000017eb20598e6e057-- From MAILER-DAEMON Thu Dec 05 00:02:53 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1icjHx-00078Q-7H for mharc-qemu-arm@gnu.org; Thu, 05 Dec 2019 00:02:53 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:51228) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1icjHt-00076M-H6 for qemu-arm@nongnu.org; Thu, 05 Dec 2019 00:02:50 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1icjHs-0004DV-5a for qemu-arm@nongnu.org; Thu, 05 Dec 2019 00:02:49 -0500 Received: from out4-smtp.messagingengine.com ([66.111.4.28]:57249) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1icjHo-0004AQ-FD; Thu, 05 Dec 2019 00:02:46 -0500 Received: from compute4.internal (compute4.nyi.internal [10.202.2.44]) by mailout.nyi.internal (Postfix) with ESMTP id 1402A227B8; Thu, 5 Dec 2019 00:02:41 -0500 (EST) Received: from imap2 ([10.202.2.52]) by compute4.internal (MEProxy); Thu, 05 Dec 2019 00:02:41 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=aj.id.au; h= mime-version:message-id:in-reply-to:references:date:from:to:cc :subject:content-type:content-transfer-encoding; s=fm1; bh=Gm0Bu 76qnev5eR0jj9tPedHTPd0qyliUowe7Q0H39aI=; b=OX+hWXUVlXljYh73YbpVX uk67rYXN4fsOD5l+nVQ1fdHNEAop0/CPM39xmLBfZCWpPndnxWbIpnF2hydvMVXu iDLt86pWkUR4+XTb5sGDbDi3q40LVMZ/Lf/CHuFFdVXi42UNTN/m8f1U8SxSIt9/ 9PPlsF37mTXaayfyTjrp0sDf8DyrzAGUpMfYYIJL+f1D3ALYZMPMAMSltN4w5Rnx pDeFqhq0IZo+1lRh6zxP7npx5a39XOZvvpw8FnFYjTelyrZks9p3L3HIMSMb8veJ bVRJJHuyYYPSjq7xlgxE7mxtkFcAWXCvYzeGyMJRncJnE+6usaFxpopFsfYYZuya A== DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d= messagingengine.com; h=cc:content-transfer-encoding:content-type :date:from:in-reply-to:message-id:mime-version:references :subject:to:x-me-proxy:x-me-proxy:x-me-sender:x-me-sender :x-sasl-enc; s=fm1; bh=Gm0Bu76qnev5eR0jj9tPedHTPd0qyliUowe7Q0H39 aI=; b=EOZvZyXLmz0TaFvn8tufEc/zPRTBUr6dclFE1VBO73z426qsNWf01DoCe dXCgMPH3kEujC61WF/4DZ4S7ZZ0LCOG2r6zUenehQ5ne+JyWmBv9Lqv6tz3FvpLg If5wj/K9SO0MOcK4+L95nuQGpzAZvEXmUCu95qh3TdvjI/MJInfG+WjbYQUCfuM4 qWib4AfeEzJuy7UC0cUz8Q/t7UELUMqe/i0TUa3bGhI+NooEfqxQeBrwQjVfaItU FM+TQkHDu8hhbm5CxBqwaj8pq5RPbr1fjKRQRbuKCcMt+9T6klV3Omfu/YFTdOEZ SauWSGyR9RAkp2KjHup2K0CPhUkMQ== X-ME-Sender: X-ME-Proxy-Cause: gggruggvucftvghtrhhoucdtuddrgedufedrudektddgjeelucetufdoteggodetrfdotf fvucfrrhhofhhilhgvmecuhfgrshhtofgrihhlpdfqfgfvpdfurfetoffkrfgpnffqhgen uceurghilhhouhhtmecufedttdenucesvcftvggtihhpihgvnhhtshculddquddttddmne cujfgurhepofgfggfkjghffffhvffutgfgsehtqhertderreejnecuhfhrohhmpedftehn ughrvgifucflvghffhgvrhihfdcuoegrnhgurhgvfiesrghjrdhiugdrrghuqeenucfrrg hrrghmpehmrghilhhfrhhomheprghnughrvgifsegrjhdrihgurdgruhenucevlhhushht vghrufhiiigvpedt X-ME-Proxy: Received: by mailuser.nyi.internal (Postfix, from userid 501) id 63050E00A2; Thu, 5 Dec 2019 00:02:40 -0500 (EST) X-Mailer: MessagingEngine.com Webmail Interface User-Agent: Cyrus-JMAP/3.1.7-612-g13027cc-fmstable-20191203v1 Mime-Version: 1.0 Message-Id: In-Reply-To: <87bf3c1d-9e77-f4a1-1163-548a3cfee3bc@redhat.com> References: <20191203041440.6275-1-andrew@aj.id.au> <20191203041440.6275-3-andrew@aj.id.au> <283c152b-b1c7-551e-bec0-c087b14de996@redhat.com> <4e90d36d-aa13-441f-9298-56f83a5bff6a@www.fastmail.com> <87bf3c1d-9e77-f4a1-1163-548a3cfee3bc@redhat.com> Date: Thu, 05 Dec 2019 15:34:15 +1030 From: "Andrew Jeffery" To: =?UTF-8?Q?Philippe_Mathieu-Daud=C3=A9?= , qemu-arm@nongnu.org Cc: qemu-devel@nongnu.org, "Peter Maydell" , "Richard Henderson" , =?UTF-8?Q?C=C3=A9dric_Le_Goater?= , "Joel Stanley" Subject: Re: [PATCH v2 2/4] target/arm: Abstract the generic timer frequency Content-Type: text/plain;charset=utf-8 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 66.111.4.28 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 05 Dec 2019 05:02:51 -0000 On Wed, 4 Dec 2019, at 03:57, Philippe Mathieu-Daud=C3=A9 wrote: > On 12/3/19 1:48 PM, Andrew Jeffery wrote: > > On Tue, 3 Dec 2019, at 16:39, Philippe Mathieu-Daud=C3=A9 wrote: > >> On 12/3/19 5:14 AM, Andrew Jeffery wrote: > >>> Prepare for SoCs such as the ASPEED AST2600 whose firmware configu= res > >>> CNTFRQ to values significantly larger than the static 62.5MHz valu= e > >>> currently derived from GTIMER_SCALE. As the OS potentially derives= its > >>> timer periods from the CNTFRQ value the lack of support for runnin= g > >>> QEMUTimers at the appropriate rate leads to sticky behaviour in th= e > >>> guest. > >>> > >>> Substitute the GTIMER_SCALE constant with use of a helper to deriv= e the > >>> period from gt_cntfrq stored in struct ARMCPU. Initially set gt_cn= tfrq > >>> to the frequency associated with GTIMER_SCALE so current behaviour= is > >>> maintained. > >>> > >>> Signed-off-by: Andrew Jeffery > >>> Reviewed-by: Richard Henderson > >>> --- > >>> target/arm/cpu.c | 2 ++ > >>> target/arm/cpu.h | 10 ++++++++++ > >>> target/arm/helper.c | 10 +++++++--- > >>> 3 files changed, 19 insertions(+), 3 deletions(-) > >>> > >>> diff --git a/target/arm/cpu.c b/target/arm/cpu.c > >>> index 7a4ac9339bf9..5698a74061bb 100644 > >>> --- a/target/arm/cpu.c > >>> +++ b/target/arm/cpu.c > >>> @@ -974,6 +974,8 @@ static void arm_cpu_initfn(Object *obj) > >>> if (tcg_enabled()) { > >>> cpu->psci_version =3D 2; /* TCG implements PSCI 0.2 */ > >>> } > >>> + > >>> + cpu->gt_cntfrq =3D NANOSECONDS_PER_SECOND / GTIMER_SCALE; > >>> } > >>> =20 > >>> static Property arm_cpu_reset_cbar_property =3D > >>> diff --git a/target/arm/cpu.h b/target/arm/cpu.h > >>> index 83a809d4bac4..666c03871fdf 100644 > >>> --- a/target/arm/cpu.h > >>> +++ b/target/arm/cpu.h > >>> @@ -932,8 +932,18 @@ struct ARMCPU { > >>> */ > >>> DECLARE_BITMAP(sve_vq_map, ARM_MAX_VQ); > >>> DECLARE_BITMAP(sve_vq_init, ARM_MAX_VQ); > >>> + > >>> + /* Generic timer counter frequency, in Hz */ > >>> + uint64_t gt_cntfrq; > >> > >> You can also explicit the unit by calling it 'gt_cntfrq_hz'. > >=20 > > Fair call, I'll fix that. > >=20 > >> > >>> }; > >>> =20 > >>> +static inline unsigned int gt_cntfrq_period_ns(ARMCPU *cpu) > >>> +{ > >>> + /* XXX: Could include qemu/timer.h to get NANOSECONDS_PER_SEC= OND? */ > >> > >> Why inline this call? I doubt there is a significant performance ga= in. > >=20 > > It wasn't so much performance. It started out as a macro for a simpl= e calculation > > because I didn't want to duplicate it across a number of places, the= n I wanted type > > safety for the pointer so I switched the macro in the header to an = inline function. So > > it is an evolution of the patch rather than something that came from= an explicit goal > > of e.g. performance. >=20 > OK. Eventually NANOSECONDS_PER_SECOND will move to "qemu/units.h". >=20 > Should the XXX comment stay? I'm not sure, it is confusing. I'll remove that.=20 >=20 > Reviewed-by: Philippe Mathieu-Daud=C3=A9 Thanks. However, did you still want your comment on 4/4 addressed (move the comment to this patch)? Andrew From MAILER-DAEMON Thu Dec 05 03:37:39 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1icmdm-0005ms-Ro for mharc-qemu-arm@gnu.org; Thu, 05 Dec 2019 03:37:38 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:58591) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1icmdk-0005hr-Ic for qemu-arm@nongnu.org; Thu, 05 Dec 2019 03:37:37 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1icmdj-0007Ys-Dz for qemu-arm@nongnu.org; Thu, 05 Dec 2019 03:37:36 -0500 Received: from us-smtp-1.mimecast.com ([207.211.31.81]:54164 helo=us-smtp-delivery-1.mimecast.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1icmdi-0007Q9-6b for qemu-arm@nongnu.org; Thu, 05 Dec 2019 03:37:35 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1575535053; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=gjAx9qo7unBhZw8XOGVCMog1QrLyKDuC1ZKnNfrR6Ic=; b=DVqcGIHJWtKbaTpkjVYQzoiUk5xIKKErUcsmSlZ4E5uGlE13o2RouHBUGPQTgxDrulo4jc Iv2Y2QvKsisyhfkMf0TgVRc++Vffztp8Ea1ECtUJZMZkJpRa18KrAHY60ma2nMY28QDVh+ rXwGPOPK1fFtFf9txKc/Fr93D8Afdfg= Received: from mimecast-mx01.redhat.com (mimecast-mx01.redhat.com [209.132.183.4]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-165-KrgiRwe-O-WdUIogmUeZOw-1; Thu, 05 Dec 2019 03:37:30 -0500 Received: from smtp.corp.redhat.com (int-mx03.intmail.prod.int.phx2.redhat.com [10.5.11.13]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx01.redhat.com (Postfix) with ESMTPS id D46541005502; Thu, 5 Dec 2019 08:37:28 +0000 (UTC) Received: from [10.36.116.117] (ovpn-116-117.ams2.redhat.com [10.36.116.117]) by smtp.corp.redhat.com (Postfix) with ESMTPS id C13B517AA3; Thu, 5 Dec 2019 08:37:27 +0000 (UTC) Subject: Re: [PATCH 4/5] hw/arm/smmuv3: Use correct bit positions in EVT_SET_ADDR2 macro To: Simon Veith , qemu-devel@nongnu.org, qemu-arm@nongnu.org References: <1575467748-28898-1-git-send-email-sveith@amazon.de> <1575467748-28898-5-git-send-email-sveith@amazon.de> From: Auger Eric Message-ID: <56987d35-a6cc-e9dc-b216-efae755a9fe0@redhat.com> Date: Thu, 5 Dec 2019 09:37:26 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101 Thunderbird/60.4.0 MIME-Version: 1.0 In-Reply-To: <1575467748-28898-5-git-send-email-sveith@amazon.de> Content-Language: en-US X-Scanned-By: MIMEDefang 2.79 on 10.5.11.13 X-MC-Unique: KrgiRwe-O-WdUIogmUeZOw-1 X-Mimecast-Spam-Score: 0 Content-Type: text/plain; charset=windows-1252 Content-Transfer-Encoding: 7bit X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 207.211.31.81 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 05 Dec 2019 08:37:37 -0000 Hi Simon, On 12/4/19 2:55 PM, Simon Veith wrote: > The bit offsets in the EVT_SET_ADDR2 macro do not match those specified > in the ARM SMMUv3 Architecture Specification. In all events that use > this macro, e.g. F_WALK_EABT, the faulting fetch address or IPA actually > occupies the 32-bit words 6 and 7 in the event record contiguously, with > the upper and lower unused bits clear due to alignment or maximum > supported address bits. How many bits are clear depends on the > individual event type. > > Update the macro to write to the correct words in the event record so > that guest drivers can obtain accurate address information on events. > > ref. ARM IHI 0070C, sections 7.3.12 through 7.3.16. > > Signed-off-by: Simon Veith Acked-by: Eric Auger Thanks Eric > Cc: Eric Auger > Cc: qemu-devel@nongnu.org > Cc: qemu-arm@nongnu.org > --- > hw/arm/smmuv3-internal.h | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git a/hw/arm/smmuv3-internal.h b/hw/arm/smmuv3-internal.h > index d190181..eb275e2 100644 > --- a/hw/arm/smmuv3-internal.h > +++ b/hw/arm/smmuv3-internal.h > @@ -461,8 +461,8 @@ typedef struct SMMUEventInfo { > } while (0) > #define EVT_SET_ADDR2(x, addr) \ > do { \ > - (x)->word[7] = deposit32((x)->word[7], 3, 29, addr >> 16); \ > - (x)->word[7] = deposit32((x)->word[7], 0, 16, addr & 0xffff);\ > + (x)->word[7] = (uint32_t)(addr >> 32); \ > + (x)->word[6] = (uint32_t)(addr & 0xffffffff); \ > } while (0) > > void smmuv3_record_event(SMMUv3State *s, SMMUEventInfo *event); > From MAILER-DAEMON Thu Dec 05 03:39:26 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1icmfW-0007ah-DE for mharc-qemu-arm@gnu.org; Thu, 05 Dec 2019 03:39:26 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:43976) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1icmfQ-0007XP-OO for qemu-arm@nongnu.org; Thu, 05 Dec 2019 03:39:24 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1icmfP-0003if-J3 for qemu-arm@nongnu.org; Thu, 05 Dec 2019 03:39:20 -0500 Received: from us-smtp-1.mimecast.com ([205.139.110.61]:39159) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1icmfP-0003gr-8t for qemu-arm@nongnu.org; Thu, 05 Dec 2019 03:39:19 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1575535158; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=WEw3d+DqTbpKJERAhcdHK2F5dU6bzzDjmvLgz+gaJQ0=; b=H98HaKzOVl5eusB1sMuBL4lkYdHwVop0tXN5HQ72TmgFL9FnXmjXOWhcRQQLIGHtLDzcCC 7GL0/bOXhipHAN5g7h/BQuvXOwhK3V2ceK6gkhl9d9YPjnw674LGbb9IhWkZlZOrDF9qnK o9MV2mUAau+cB5HPNPLeEiZUKgs+aH8= Received: from mimecast-mx01.redhat.com (mimecast-mx01.redhat.com [209.132.183.4]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-22-Vv2LqZlkOUWmOhPLzVbL5w-1; Thu, 05 Dec 2019 03:39:15 -0500 Received: from smtp.corp.redhat.com (int-mx01.intmail.prod.int.phx2.redhat.com [10.5.11.11]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx01.redhat.com (Postfix) with ESMTPS id 292518017DF; Thu, 5 Dec 2019 08:39:14 +0000 (UTC) Received: from [10.36.116.117] (ovpn-116-117.ams2.redhat.com [10.36.116.117]) by smtp.corp.redhat.com (Postfix) with ESMTPS id 555526012C; Thu, 5 Dec 2019 08:39:13 +0000 (UTC) Subject: Re: [PATCH 5/5] hw/arm/smmuv3: Report F_STE_FETCH fault address in correct word position To: Simon Veith , qemu-devel@nongnu.org, qemu-arm@nongnu.org References: <1575467748-28898-1-git-send-email-sveith@amazon.de> <1575467748-28898-6-git-send-email-sveith@amazon.de> From: Auger Eric Message-ID: <39341988-f302-c750-9801-4710ff50c2fe@redhat.com> Date: Thu, 5 Dec 2019 09:39:11 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101 Thunderbird/60.4.0 MIME-Version: 1.0 In-Reply-To: <1575467748-28898-6-git-send-email-sveith@amazon.de> Content-Language: en-US X-Scanned-By: MIMEDefang 2.79 on 10.5.11.11 X-MC-Unique: Vv2LqZlkOUWmOhPLzVbL5w-1 X-Mimecast-Spam-Score: 0 Content-Type: text/plain; charset=windows-1252 Content-Transfer-Encoding: 7bit X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 205.139.110.61 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 05 Dec 2019 08:39:25 -0000 Hi Simon, On 12/4/19 2:55 PM, Simon Veith wrote: > The smmuv3_record_event() function that generates the F_STE_FETCH error > uses the EVT_SET_ADDR macro to record the fetch address, placing it in > 32-bit words 4 and 5. > > The correct position for this address is in words 6 and 7, per the > SMMUv3 Architecture Specification. > > Update the function to use the EVT_SET_ADDR2 macro instead, which is the > macro intended for writing to these words. > > ref. ARM IHI 0070C, section 7.3.4. > > Signed-off-by: Simon Veith > Cc: Eric Auger > Cc: qemu-devel@nongnu.org > Cc: qemu-arm@nongnu.org > --- > hw/arm/smmuv3.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c > index 2d6c275..125e47d 100644 > --- a/hw/arm/smmuv3.c > +++ b/hw/arm/smmuv3.c > @@ -172,7 +172,7 @@ void smmuv3_record_event(SMMUv3State *s, SMMUEventInfo *info) > case SMMU_EVT_F_STE_FETCH: > EVT_SET_SSID(&evt, info->u.f_ste_fetch.ssid); > EVT_SET_SSV(&evt, info->u.f_ste_fetch.ssv); > - EVT_SET_ADDR(&evt, info->u.f_ste_fetch.addr); > + EVT_SET_ADDR2(&evt, info->u.f_ste_fetch.addr); > break; > case SMMU_EVT_C_BAD_STE: > EVT_SET_SSID(&evt, info->u.c_bad_ste.ssid); > Acked-by: Eric Auger Thanks Eric From MAILER-DAEMON Thu Dec 05 03:42:04 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1icmi4-0000iU-0O for mharc-qemu-arm@gnu.org; Thu, 05 Dec 2019 03:42:04 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:38225) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1icmi1-0000hH-7I for qemu-arm@nongnu.org; Thu, 05 Dec 2019 03:42:02 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1icmhz-0002ti-WF for qemu-arm@nongnu.org; Thu, 05 Dec 2019 03:42:01 -0500 Received: from us-smtp-1.mimecast.com ([205.139.110.61]:50358 helo=us-smtp-delivery-1.mimecast.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1icmhl-0002WI-8P for qemu-arm@nongnu.org; Thu, 05 Dec 2019 03:41:59 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1575535304; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=oWzU1D6brfrqeWW9oo+vPzM9VdKyFyvRG4TgMO+1RUw=; b=cqj0gmhxSR7iftuFooTxDWPxylJ3zTsZyLjMEv/Hlivj81FwovJownIJiV424NQkYQuQnc XkXO3HWuMJOBixu+cWPBsDz+FZ2Na/KDmFgouSMb5ls6MIms2ZTPXDTeIGKd3y1JiQrbSe MI8xRsmg3VBYhDqnB/rvQ/kMY6OggEs= Received: from mimecast-mx01.redhat.com (mimecast-mx01.redhat.com [209.132.183.4]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-274-6JD909Y4MhyCz5GoWs41Sg-1; Thu, 05 Dec 2019 03:41:41 -0500 Received: from smtp.corp.redhat.com (int-mx06.intmail.prod.int.phx2.redhat.com [10.5.11.16]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx01.redhat.com (Postfix) with ESMTPS id 6422964A7D; Thu, 5 Dec 2019 08:41:40 +0000 (UTC) Received: from [10.36.116.117] (ovpn-116-117.ams2.redhat.com [10.36.116.117]) by smtp.corp.redhat.com (Postfix) with ESMTPS id 82FE85C1B5; Thu, 5 Dec 2019 08:41:39 +0000 (UTC) Subject: Re: [PATCH 2/5] hw/arm/smmuv3: Check stream IDs against actual table LOG2SIZE To: Simon Veith , qemu-devel@nongnu.org, qemu-arm@nongnu.org References: <1575467748-28898-1-git-send-email-sveith@amazon.de> <1575467748-28898-3-git-send-email-sveith@amazon.de> From: Auger Eric Message-ID: <1a0656ce-5da0-2251-1304-1ee0e683b887@redhat.com> Date: Thu, 5 Dec 2019 09:41:37 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101 Thunderbird/60.4.0 MIME-Version: 1.0 In-Reply-To: <1575467748-28898-3-git-send-email-sveith@amazon.de> Content-Language: en-US X-Scanned-By: MIMEDefang 2.79 on 10.5.11.16 X-MC-Unique: 6JD909Y4MhyCz5GoWs41Sg-1 X-Mimecast-Spam-Score: 0 Content-Type: text/plain; charset=windows-1252 Content-Transfer-Encoding: 7bit X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 205.139.110.61 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 05 Dec 2019 08:42:02 -0000 Hi Simon, On 12/4/19 2:55 PM, Simon Veith wrote: > When checking whether a stream ID is in range of the stream table, we > have so far been only checking it against our implementation limit > (SMMU_IDR1_SIDSIZE). However, the guest can program the > STRTAB_BASE_CFG.LOG2SIZE field to a size that is smaller than this > limit. > > Check the stream ID against this limit as well to match the hardware > behavior of raising C_BAD_STREAMID events in case the limit is exceeded. > > ref. ARM IHI 0070C, section 6.3.24. > > Signed-off-by: Simon Veith > Cc: Eric Auger > Cc: qemu-devel@nongnu.org > Cc: qemu-arm@nongnu.org > --- > hw/arm/smmuv3.c | 8 ++++++-- > 1 file changed, 6 insertions(+), 2 deletions(-) > > diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c > index eef9a18..aad4639 100644 > --- a/hw/arm/smmuv3.c > +++ b/hw/arm/smmuv3.c > @@ -377,11 +377,15 @@ static int smmu_find_ste(SMMUv3State *s, uint32_t sid, STE *ste, > SMMUEventInfo *event) > { > dma_addr_t addr; > + uint32_t log2size; > int ret; > > trace_smmuv3_find_ste(sid, s->features, s->sid_split); > - /* Check SID range */ > - if (sid > (1 << SMMU_IDR1_SIDSIZE)) { > + log2size = FIELD_EX32(s->strtab_base_cfg, STRTAB_BASE_CFG, LOG2SIZE); > + /* > + * Check SID range against both guest-configured and implementation limits > + */ > + if (sid > (1 << MIN(log2size, SMMU_IDR1_SIDSIZE))) {I think this should be sid >= (1 << MIN(log2size, SMMU_IDR1_SIDSIZE)) If you agree can you fix it at the same time? > event->type = SMMU_EVT_C_BAD_STREAMID; > return -EINVAL; > } > Thanks Eric From MAILER-DAEMON Thu Dec 05 03:42:55 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1icmit-0001YD-5D for mharc-qemu-arm@gnu.org; Thu, 05 Dec 2019 03:42:55 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:48398) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1icmiq-0001VM-Ev for qemu-arm@nongnu.org; Thu, 05 Dec 2019 03:42:53 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1icmip-0006Kt-Ai for qemu-arm@nongnu.org; Thu, 05 Dec 2019 03:42:52 -0500 Received: from us-smtp-1.mimecast.com ([205.139.110.61]:23101 helo=us-smtp-delivery-1.mimecast.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1icmip-0006Ia-3c for qemu-arm@nongnu.org; Thu, 05 Dec 2019 03:42:51 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1575535370; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=jgdqmmKVdMbSsk9weGSCSEzICTE6qo/wwWVP4u9Ohaw=; b=XLQBmsZ8yFMhrUmDywAz4VHgvp6ruGzMq1lebBhohnPYmxiIm3AU8QbXufE+4dx2ovCUR6 tbkestuaZT2eSfWGVs/lv5bvFaq7ao5yNA4QTJRpmN2xmtSly4xhB20hoEDVG3jGA+e9U6 87A/LaoNgS9Iuh5TMBAQqpwVRvXQsvU= Received: from mimecast-mx01.redhat.com (mimecast-mx01.redhat.com [209.132.183.4]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-124-sWwO2_LGMDWnLSVuuO7Q0A-1; Thu, 05 Dec 2019 03:42:49 -0500 Received: from smtp.corp.redhat.com (int-mx05.intmail.prod.int.phx2.redhat.com [10.5.11.15]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx01.redhat.com (Postfix) with ESMTPS id 31C4C800C7D; Thu, 5 Dec 2019 08:42:48 +0000 (UTC) Received: from [10.36.116.117] (ovpn-116-117.ams2.redhat.com [10.36.116.117]) by smtp.corp.redhat.com (Postfix) with ESMTPS id 407275D6A5; Thu, 5 Dec 2019 08:42:46 +0000 (UTC) Subject: Re: [PATCH 1/5] hw/arm/smmuv3: Apply address mask to linear strtab base address To: Simon Veith , qemu-devel@nongnu.org, qemu-arm@nongnu.org References: <1575467748-28898-1-git-send-email-sveith@amazon.de> <1575467748-28898-2-git-send-email-sveith@amazon.de> From: Auger Eric Message-ID: <0f01a30e-5b27-f97c-903a-a8a2a74a1cdd@redhat.com> Date: Thu, 5 Dec 2019 09:42:45 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101 Thunderbird/60.4.0 MIME-Version: 1.0 In-Reply-To: <1575467748-28898-2-git-send-email-sveith@amazon.de> Content-Language: en-US X-Scanned-By: MIMEDefang 2.79 on 10.5.11.15 X-MC-Unique: sWwO2_LGMDWnLSVuuO7Q0A-1 X-Mimecast-Spam-Score: 0 Content-Type: text/plain; charset=windows-1252 Content-Transfer-Encoding: 7bit X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 205.139.110.61 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 05 Dec 2019 08:42:53 -0000 Hi Simon, On 12/4/19 2:55 PM, Simon Veith wrote: > In the SMMU_STRTAB_BASE register, the stream table base address only > occupies bits [51:6]. Other bits, such as RA (bit [62]), must be masked > out to obtain the base address. > > The branch for 2-level stream tables correctly applies this mask by way > of SMMU_BASE_ADDR_MASK, but the one for linear stream tables does not. > > Apply the missing mask in that case as well so that the correct stream > base address is used by guests which configure a linear stream table. > > Linux guests are unaffected by this change because they choose a 2-level > stream table layout for the QEMU SMMUv3, based on the size of its stream > ID space. > > ref. ARM IHI 0070C, section 6.3.23. > > Signed-off-by: Simon Veith > Cc: Eric Auger > Cc: qemu-devel@nongnu.org > Cc: qemu-arm@nongnu.org > --- > hw/arm/smmuv3.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c > index e2fbb83..eef9a18 100644 > --- a/hw/arm/smmuv3.c > +++ b/hw/arm/smmuv3.c > @@ -429,7 +429,7 @@ static int smmu_find_ste(SMMUv3State *s, uint32_t sid, STE *ste, > } > addr = l2ptr + l2_ste_offset * sizeof(*ste); > } else { > - addr = s->strtab_base + sid * sizeof(*ste); > + addr = (s->strtab_base & SMMU_BASE_ADDR_MASK) + sid * sizeof(*ste); Not related to this patch but I noticed SMMU_BASE_ADDR_MASK should be 0xffffffffffc0 and not 0xffffffffffe0. I can fix it separately or if you respin, you may fix it as well? > } > > if (smmu_get_ste(s, addr, ste, event)) { > Besides Acked-by: Eric Auger Thanks Eric From MAILER-DAEMON Thu Dec 05 04:36:17 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1icnYX-0003JQ-8Z for mharc-qemu-arm@gnu.org; Thu, 05 Dec 2019 04:36:17 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:35845) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1icnYT-0003Il-NS for qemu-arm@nongnu.org; Thu, 05 Dec 2019 04:36:15 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1icnYR-0004tx-OE for qemu-arm@nongnu.org; Thu, 05 Dec 2019 04:36:13 -0500 Received: from beetle.greensocs.com ([5.135.226.135]:50852) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1icnYP-0004rr-Pm; Thu, 05 Dec 2019 04:36:10 -0500 Received: from [172.16.11.102] (crumble.bar.greensocs.com [172.16.11.102]) by beetle.greensocs.com (Postfix) with ESMTPSA id 9B55496EF0; Thu, 5 Dec 2019 09:36:05 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=greensocs.com; s=mail; t=1575538566; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=MTH39LOLBKhiZZY+Qr5iT9+p1EQRnbjX+gTe1G3pmYM=; b=YrxcVxmHp8QhLbXYxdfz2N4frh0iddI1UwW0xQe2dwuEAPgmiUCI9P1r/gGPxGEM2O2g+b KDp8JyFebrNvpjs7+5c5dERWFC5/P8BcHtKxp6s4B6tDgjPWn0Zj8vZ4RB5dd0eHB48DMY BvPPM71ZOuQ1cHGUhVpADBfilFF2X6A= Subject: Re: [PATCH v6 0/9] Clock framework API To: =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= , Peter Maydell Cc: QEMU Developers , Mark Burton , "Edgar E. Iglesias" , Alistair Francis , =?UTF-8?Q?Marc-Andr=c3=a9_Lureau?= , Paolo Bonzini , "Daniel P. Berrange" , Eduardo Habkost , qemu-arm References: <20190904125531.27545-1-damien.hedde@greensocs.com> From: Damien Hedde Message-ID: Date: Thu, 5 Dec 2019 10:36:05 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.2.0 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=utf-8 Content-Language: en-US-large ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=greensocs.com; s=mail; t=1575538566; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=MTH39LOLBKhiZZY+Qr5iT9+p1EQRnbjX+gTe1G3pmYM=; b=es8ChEyrvdC4tSl6gUs/giAF8uN7sKwqDNLfsrLLFNsSizSyA4iYxLtxoE0wFlPdV+np4K U+V+rq9/OvUaIV89rOnm79cK287ARxWZnfO9o92Wxo9ax5yqeNwUV6U5QQ0uoNeIJiDTBX Y41/T7jL4Uvh4GDnoi0RX3A1m/k+NKU= ARC-Seal: i=1; s=mail; d=greensocs.com; t=1575538566; a=rsa-sha256; cv=none; b=5F5R19wCqtnFg07bNesjkS3mIX19UseJ7rRbMP6PhLryUjTsVxdLte4yK3jm+u39qp5wql bYmPEe2G8l2F85Lvi+KNyWY1f0gSk9SBAxlgWJc3ASIi4nzPaVx4M7EL5eTSRVO1slMCa4 Er1b6oUTx4UQwm381k2xMRZaWEhWDsI= ARC-Authentication-Results: i=1; ORIGINATING; auth=pass smtp.auth=damien smtp.mailfrom=damien.hedde@greensocs.com Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 5.135.226.135 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 05 Dec 2019 09:36:15 -0000 On 12/4/19 9:34 PM, Philippe Mathieu-Daud=C3=A9 wrote: > On 12/4/19 5:40 PM, Damien Hedde wrote: >> On 12/2/19 5:15 PM, Peter Maydell wrote: >>> >>> The one topic I think we could do with discussing is whether >>> a simple uint64_t giving the frequency of the clock in Hz is >>> the right representation. In particular in your patch 9 the >>> board has a clock frequency that's not a nice integer number >>> of Hz. I think Philippe also mentioned on irc some board where >>> the UART clock ends up at a weird frequency. Since the >>> representation of the frequency is baked into the migration >>> format it's going to be easier to get it right first rather >>> than trying to change it later. >=20 > Important precision for Damien, IIUC we can not migrate float/double ty= pes. >=20 >>> So what should the representation be? Some random thoughts: >>> >>> 1) ptimer internally uses a 'period plus fraction' representation: >>> =C2=A0 int64_t period is the integer part of the period in nanosecond= s, >>> =C2=A0 uint32_t period_frac is the fractional part of the period >>> (if you like you can think of this as "96-bit integer >>> period measured in units of one-2^32nd of a nanosecond"). >>> However its only public interfaces for setting the frequency >>> are (a) set the frequency in Hz (uint32_t) or (b) set >>> the period in nanoseconds (int64_t); the period_frac part >>> is used to handle frequencies which don't work out to >>> a nice whole number of nanoseconds per cycle. >=20 > This is very clear, thanks Peter! >=20 > The period+period_frac split allow us to migrate the 96 bits: >=20 > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 VMSTATE_UINT32(period_frac, = ptimer_state), > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 VMSTATE_INT64(period, ptimer= _state), >=20 >>> 2) I hear that SystemC uses "value plus a time unit", with >>> the smallest unit being a picosecond. (I think SystemC >>> also lets you specify the duty cycle, but we definitely >>> don't want to get into that!) >> >> The "value" is internally stored in a 64bits unsigned integer. >> >>> >>> 3) QEMUTimers are basically just nanosecond timers >=20 > Similarly to SystemC, the QEMUTimers macro use a 'scale' unit, of: >=20 > #define SCALE_MS 1000000 > #define SCALE_US 1000 > #define SCALE_NS 1 >=20 >>> >>> 4) The MAME emulator seems to work with periods of >>> 96-bit attoseconds (represented internally by a >>> 32-bit count of seconds plus a 64-bit count of >>> attoseconds). One attosecond is 1e-18 seconds. >>> >>> Does anybody else have experience with other modelling >>> or emulator technology and how it represents clocks ? >> >> 5) In linux, a clock rate is an "unsigned long" representing Hz. >> >>> >>> I feel we should at least be able to represent clocks >>> with the same accuracy that ptimer has. >> >> Then is a maybe a good idea to store the period and not the frequency = in >> clocks so that we don't loose anything when we switch from a clock to = a >> ptimer ? >=20 > I think storing the period as an integer type is a good idea. >=20 > However if we store the period in nanoseconds, we get at most 1GHz > frequency. >=20 > The attosecond granularity feels overkill. >=20 > If we use a 96-bit integer to store picoseconds and use similar SCALE > macros we get to 1THz. >=20 > Regardless the unit chosen, as long it is integer, we can migrate it. > If can migrate the period, we don't need to migrate the frequency. > We can then use the float type in with the timer API to pass frequencie= s > (which in the modeled hardware are ratios, likely not integers). >=20 > So we could use set_freq(100e6 / 3), set_freq(40e6 / 5.5) directly. >=20 >> Regarding the clock, I don't see any strong obstacle to switch >> internally to a period based value. >> The only things we have to choose is how to represent a disabled clock= . >> Since putting a "0" period to a ptimer will disable the timer in >> ptimer_reload(). We can choose that (and it's a good value because we >> can multiply or divide it, it stays the same). >> >> We could use the same representation as a ptimer. But if we don't keep= a >> C number representation, then computation of frequencies/periods will = be >> complicated at best and error prone. >> >> =C2=A0From that point of view, if we could stick to a 64bits integer (= or >> floating point number) it would be great. Can we use a sub nanosecond >> unit that fit our needs ? >> >> I did some test with a unit of 2^-32 of nanoseconds on 64bits (is that >> the unit of the ptimer fractional part ?) and if I'm not mistaken >> + we have a frequency range from ~0.2Hz up to 10^18Hz >> + the resolution is decreasing with the frequency (but at 100Mhz we ha= ve >> a ~2.3mHz resolution, at 1GHz it's ~0.23Hz and at 10GHz ~23Hz >> resolution). We hit 1Hz resolution around 2GHz. >> >> So it sounds to me we have largely enough resolution to model clocks i= n >> the range of frequencies we will have to handle. What do you think ? >=20 > Back to your series, I wonder why you want to store the frequency in > ClockIn. ClockIn shouldn't be aware at what frequency it is clocked. > What matters is ClockOut, and each device exposing ClockOuts has a > (migrated) state of the output frequencies (rather in fields, or encode= d > in registers). Once migrated, after the state is loaded back into the > device, we call post_load(). Isn't it a good place to call > clock_set_frequency(ClockOut[]) which will correctly set each ClockIn > frequency. >=20 > IOW I don't think ClockIn/ClockOut require to migrate a frequency field= . >=20 I agree it is more logical to store the frequency in clock out. But, regarding migration constraints, we have no choice I think because a device cannot rely on values that are migrated by another device for restoring its state. (when I checked, I add the impression that post_load()s are called on a per device migration basis not all at the end of migration). So we could store the frequency in clock out and migrate things there. But since we have no way to ensure all clock out states are migrated before some device fetch a ClockIn: we'll have to say "don't fetch one of your ClockIn frequency during migration and migrate the value yourself if you need it", pretty much like gpios. So we will probably migrate all ClockOut and almost all ClockIn. It would nice if we had a way to ensure clocks are migrated before devices try to use them. But I don't think this is possible. -- Damien From MAILER-DAEMON Thu Dec 05 04:39:20 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1icnbT-0004NS-Sh for mharc-qemu-arm@gnu.org; Thu, 05 Dec 2019 04:39:19 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:57579) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1icnbP-0004Lb-Ie for qemu-arm@nongnu.org; Thu, 05 Dec 2019 04:39:17 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1icnbB-00041A-Fv for qemu-arm@nongnu.org; Thu, 05 Dec 2019 04:39:07 -0500 Received: from mail-eopbgr20093.outbound.protection.outlook.com ([40.107.2.93]:30222 helo=EUR02-VE1-obe.outbound.protection.outlook.com) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1icnb3-0003eC-1u; Thu, 05 Dec 2019 04:38:53 -0500 ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=lgbmmPUW15cSoetFA3ZWreoJdiz/el29JWIPI5TnrdMeYgIX+sd9bf/Z0pacAEOnB1Tv73bj/P97RyVIVJpfnCvXqXqzUzjFaJTvEUTw7ZrYka38MboYkwoTH+GmIGwqKUPNSna/tjXkEYcztZDGbr2P2JiXuWeKzcqXsz6HnQWwZB9ipAROkn1LX28j2a5P84z2ZNC7eIqsBd9HGKBN/E0tNmll6rNEn7KiqwdICyuZ3lidcgj+moP4HcsJ2S6TDyRPzVZ92IbocUS53ugSiMGCOgJxURTLNYH0hINNl9lcTAwI5i2/o23N1embqUJj6QbPoZ/GRlE/h09Si+PYNg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=ia1p69Vw40bANxIuoeSQaYjHJYbA1cGLl9V08AlorT0=; b=WloxzEqTOA/f84qsLhHHAWfUySOH3TbQFjj9G+L3uI1g/YScEiCurtcd0qSiw40nTE5gINNaJOF44xbQPY7tmpn0DDSUAlPLDb21I0yMG4A5DaChi+iFnMjmNK2dI50ihv6m8aA37nQjVqvQ4FrO5pViRsnt9QzQi/eIIkpdseIJjRJ3XwSGASTngdmiULfV84Y0oG4FSfXkTRN430N9xsIEdwX5N+SKgAShYu/7uTzcuuEEd8DF6vTE6S5jibEHCaVxn3TcBza9cb7TE8D0jWpWj6Idva/b9fUoSV7vOnmrCOL9lW31L1wHneXTzG1l9pI2oirOyMhuEsc+T1Y73Q== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=virtuozzo.com; dmarc=pass action=none header.from=virtuozzo.com; dkim=pass header.d=virtuozzo.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=virtuozzo.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=ia1p69Vw40bANxIuoeSQaYjHJYbA1cGLl9V08AlorT0=; b=QkLJr1FNVx7QQXGiFeXr2rmDS+fqIScBFoDPV9YYNcF1JAVQp8PojDKXhry5FVGRDXxPRnTAbK9NcvuoqpkivztsKd4z0hRluXFSdpwcg3YM09jmG7I7q1S6aB1zU4zd+fcWWp1u0DGJj70k7p08wRVcj6h/CWweHP1c+P4vYJQ= Received: from AM6PR08MB4423.eurprd08.prod.outlook.com (20.179.7.140) by AM6PR08MB5157.eurprd08.prod.outlook.com (10.255.121.222) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.2495.18; Thu, 5 Dec 2019 09:38:49 +0000 Received: from AM6PR08MB4423.eurprd08.prod.outlook.com ([fe80::11a9:a944:c946:3030]) by AM6PR08MB4423.eurprd08.prod.outlook.com ([fe80::11a9:a944:c946:3030%7]) with mapi id 15.20.2516.014; Thu, 5 Dec 2019 09:38:49 +0000 From: Vladimir Sementsov-Ogievskiy To: Markus Armbruster CC: "qemu-devel@nongnu.org" , Ronnie Sahlberg , Jeff Cody , Jan Kiszka , Alberto Garcia , Hailiang Zhang , "qemu-block@nongnu.org" , Aleksandar Rikalo , Halil Pasic , =?utf-8?B?SGVydsOpIFBvdXNzaW5lYXU=?= , Anthony Perard , Samuel Thibault , =?utf-8?B?UGhpbGlwcGUgTWF0aGlldS1EYXVkw6k=?= , Anthony Green , Laurent Vivier , Eduardo Habkost , Xie Changlong , Peter Lieven , "Dr. David Alan Gilbert" , Beniamino Galvani , Eric Auger , Alex Williamson , Stefan Hajnoczi , John Snow , Richard Henderson , Kevin Wolf , Andrew Jeffery , Chris Wulff , Subbaraya Sundeep , Michael Walle , "qemu-ppc@nongnu.org" , Bastian Koppelmann , Igor Mammedov , Fam Zheng , Peter Maydell , "sheepdog@lists.wpkg.org" , Matthew Rosato , David Hildenbrand , Palmer Dabbelt , Thomas Huth , Max Filippov , Denis Lunev , Hannes Reinecke , Stefano Stabellini , "Gonglei (Arei)" , Liu Yuan , Artyom Tarasenko , Eric Farman , Amit Shah , Stefan Weil , Greg Kurz , Yuval Shaia , "qemu-s390x@nongnu.org" , "qemu-arm@nongnu.org" , Peter Chubb , =?utf-8?B?Q8OpZHJpYyBMZSBHb2F0ZXI=?= , Stafford Horne , "qemu-riscv@nongnu.org" , Cornelia Huck , Aleksandar Markovic , Aurelien Jarno , Paul Burton , Sagar Karandikar , Paul Durrant , Jason Wang , Gerd Hoffmann , "Edgar E. Iglesias" , Guan Xuetao , Ari Sundholm , Juan Quintela , Michael Roth , Christian Borntraeger , Joel Stanley , Jason Dillaman , Antony Pavlov , "xen-devel@lists.xenproject.org" , "integration@gluster.org" , Laszlo Ersek , "Richard W.M. Jones" , Andrew Baumann , Max Reitz , "Michael S. Tsirkin" , Mark Cave-Ayland , Vincenzo Maffione , Marek Vasut , =?utf-8?B?TWFyYy1BbmRyw6kgTHVyZWF1?= , Alistair Francis , Pavel Dovgalyuk , Giuseppe Lettieri , Luigi Rizzo , David Gibson , Tony Krowiak , =?utf-8?B?RGFuaWVsIFAuIEJlcnJhbmfDqQ==?= , Xiao Guangrong , Pierre Morel , Wen Congyang , Jean-Christophe Dubois , Paolo Bonzini , Stefan Berger Subject: Re: [RFC v5 024/126] error: auto propagated local_err Thread-Topic: [RFC v5 024/126] error: auto propagated local_err Thread-Index: AQHVgE3c5dwPNEl0z0OyUhbNfTU1EqeqZpzagAE4WYA= Date: Thu, 5 Dec 2019 09:38:49 +0000 Message-ID: <55393c08-5bda-8042-1a95-f350b3781d99@virtuozzo.com> References: <20191011160552.22907-1-vsementsov@virtuozzo.com> <20191011160552.22907-25-vsementsov@virtuozzo.com> <87muc8p24w.fsf@dusky.pond.sub.org> In-Reply-To: <87muc8p24w.fsf@dusky.pond.sub.org> Accept-Language: ru-RU, en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-clientproxiedby: HE1PR0902CA0025.eurprd09.prod.outlook.com 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[88.21.103.182]) by smtp.gmail.com with ESMTPSA id f1sm11787323wrp.93.2019.12.05.01.59.57 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 05 Dec 2019 01:59:58 -0800 (PST) Subject: Re: [PATCH v6 0/9] Clock framework API To: Damien Hedde , Peter Maydell , "Dr. David Alan Gilbert" Cc: QEMU Developers , Mark Burton , "Edgar E. Iglesias" , Alistair Francis , =?UTF-8?Q?Marc-Andr=c3=a9_Lureau?= , Paolo Bonzini , "Daniel P. Berrange" , Eduardo Habkost , qemu-arm References: <20190904125531.27545-1-damien.hedde@greensocs.com> From: =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= Message-ID: <279a0fd5-1ea5-b3c7-27bb-b1d22db5e359@redhat.com> Date: Thu, 5 Dec 2019 10:59:57 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.2.2 MIME-Version: 1.0 In-Reply-To: Content-Language: en-US X-MC-Unique: K1ZeRrODOAKTIqRtyQyApQ-1 X-Mimecast-Spam-Score: 0 Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 205.139.110.61 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 05 Dec 2019 10:00:09 -0000 On 12/5/19 10:36 AM, Damien Hedde wrote: > On 12/4/19 9:34 PM, Philippe Mathieu-Daud=C3=A9 wrote: >> On 12/4/19 5:40 PM, Damien Hedde wrote: >>> On 12/2/19 5:15 PM, Peter Maydell wrote: >>>> >>>> The one topic I think we could do with discussing is whether >>>> a simple uint64_t giving the frequency of the clock in Hz is >>>> the right representation. In particular in your patch 9 the >>>> board has a clock frequency that's not a nice integer number >>>> of Hz. I think Philippe also mentioned on irc some board where >>>> the UART clock ends up at a weird frequency. Since the >>>> representation of the frequency is baked into the migration >>>> format it's going to be easier to get it right first rather >>>> than trying to change it later. >> >> Important precision for Damien, IIUC we can not migrate float/double typ= es. >> >>>> So what should the representation be? Some random thoughts: >>>> >>>> 1) ptimer internally uses a 'period plus fraction' representation: >>>> =C2=A0 int64_t period is the integer part of the period in nanosecond= s, >>>> =C2=A0 uint32_t period_frac is the fractional part of the period >>>> (if you like you can think of this as "96-bit integer >>>> period measured in units of one-2^32nd of a nanosecond"). >>>> However its only public interfaces for setting the frequency >>>> are (a) set the frequency in Hz (uint32_t) or (b) set >>>> the period in nanoseconds (int64_t); the period_frac part >>>> is used to handle frequencies which don't work out to >>>> a nice whole number of nanoseconds per cycle. >> >> This is very clear, thanks Peter! >> >> The period+period_frac split allow us to migrate the 96 bits: >> >> =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 VMSTATE_UINT32(period_frac, = ptimer_state), >> =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 VMSTATE_INT64(period, ptimer= _state), >> >>>> 2) I hear that SystemC uses "value plus a time unit", with >>>> the smallest unit being a picosecond. (I think SystemC >>>> also lets you specify the duty cycle, but we definitely >>>> don't want to get into that!) >>> >>> The "value" is internally stored in a 64bits unsigned integer. >>> >>>> >>>> 3) QEMUTimers are basically just nanosecond timers >> >> Similarly to SystemC, the QEMUTimers macro use a 'scale' unit, of: >> >> #define SCALE_MS 1000000 >> #define SCALE_US 1000 >> #define SCALE_NS 1 >> >>>> >>>> 4) The MAME emulator seems to work with periods of >>>> 96-bit attoseconds (represented internally by a >>>> 32-bit count of seconds plus a 64-bit count of >>>> attoseconds). One attosecond is 1e-18 seconds. >>>> >>>> Does anybody else have experience with other modelling >>>> or emulator technology and how it represents clocks ? >>> >>> 5) In linux, a clock rate is an "unsigned long" representing Hz. >>> >>>> >>>> I feel we should at least be able to represent clocks >>>> with the same accuracy that ptimer has. >>> >>> Then is a maybe a good idea to store the period and not the frequency i= n >>> clocks so that we don't loose anything when we switch from a clock to a >>> ptimer ? >> >> I think storing the period as an integer type is a good idea. >> >> However if we store the period in nanoseconds, we get at most 1GHz >> frequency. >> >> The attosecond granularity feels overkill. >> >> If we use a 96-bit integer to store picoseconds and use similar SCALE >> macros we get to 1THz. >> >> Regardless the unit chosen, as long it is integer, we can migrate it. >> If can migrate the period, we don't need to migrate the frequency. >> We can then use the float type in with the timer API to pass frequencies >> (which in the modeled hardware are ratios, likely not integers). >> >> So we could use set_freq(100e6 / 3), set_freq(40e6 / 5.5) directly. >> >>> Regarding the clock, I don't see any strong obstacle to switch >>> internally to a period based value. >>> The only things we have to choose is how to represent a disabled clock. >>> Since putting a "0" period to a ptimer will disable the timer in >>> ptimer_reload(). We can choose that (and it's a good value because we >>> can multiply or divide it, it stays the same). >>> >>> We could use the same representation as a ptimer. But if we don't keep = a >>> C number representation, then computation of frequencies/periods will b= e >>> complicated at best and error prone. >>> >>> =C2=A0From that point of view, if we could stick to a 64bits integer (= or >>> floating point number) it would be great. Can we use a sub nanosecond >>> unit that fit our needs ? >>> >>> I did some test with a unit of 2^-32 of nanoseconds on 64bits (is that >>> the unit of the ptimer fractional part ?) and if I'm not mistaken >>> + we have a frequency range from ~0.2Hz up to 10^18Hz >>> + the resolution is decreasing with the frequency (but at 100Mhz we hav= e >>> a ~2.3mHz resolution, at 1GHz it's ~0.23Hz and at 10GHz ~23Hz >>> resolution). We hit 1Hz resolution around 2GHz. >>> >>> So it sounds to me we have largely enough resolution to model clocks in >>> the range of frequencies we will have to handle. What do you think ? >> >> Back to your series, I wonder why you want to store the frequency in >> ClockIn. ClockIn shouldn't be aware at what frequency it is clocked. >> What matters is ClockOut, and each device exposing ClockOuts has a >> (migrated) state of the output frequencies (rather in fields, or encoded >> in registers). Once migrated, after the state is loaded back into the >> device, we call post_load(). Isn't it a good place to call >> clock_set_frequency(ClockOut[]) which will correctly set each ClockIn >> frequency. >> >> IOW I don't think ClockIn/ClockOut require to migrate a frequency field. >> >=20 > I agree it is more logical to store the frequency in clock out. But, > regarding migration constraints, we have no choice I think because a > device cannot rely on values that are migrated by another device for > restoring its state. (when I checked, I add the impression that > post_load()s are called on a per device migration basis not all at the > end of migration). Cc'ing David to clear that out. > So we could store the frequency in clock out and migrate things there. > But since we have no way to ensure all clock out states are migrated > before some device fetch a ClockIn: we'll have to say "don't fetch one > of your ClockIn frequency during migration and migrate the value > yourself if you need it", pretty much like gpios. >=20 > So we will probably migrate all ClockOut and almost all ClockIn. >=20 > It would nice if we had a way to ensure clocks are migrated before > devices try to use them. But I don't think this is possible. >=20 > -- > Damien >=20 From MAILER-DAEMON Thu Dec 05 05:22:11 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1icoGx-0002kR-6x for mharc-qemu-arm@gnu.org; Thu, 05 Dec 2019 05:22:11 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:47047) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1icoGu-0002jv-1b for qemu-arm@nongnu.org; Thu, 05 Dec 2019 05:22:09 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1icoGr-0007Sn-Ds for qemu-arm@nongnu.org; Thu, 05 Dec 2019 05:22:07 -0500 Received: from us-smtp-delivery-1.mimecast.com ([207.211.31.120]:58754 helo=us-smtp-1.mimecast.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1icoGr-0007Mq-8u for qemu-arm@nongnu.org; Thu, 05 Dec 2019 05:22:05 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1575541323; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=MVg8tTPmIRSU+yVAO5p+EuU9NukICxQMvEzmz9savAQ=; b=fLY/vKPsZaTuqzkcKsFtPxNVOxzeNBANtmF11TpWKcv4G9npwcaO6UGDHPWzaORVcpE6wS B4EUGcqIOB0QWPSlBe5+edEisfAnkDoccFA7RWi0nQHePPgbPSnJQqq1DyYTwo+bPgXSJN Am9T3PNFD0blo7XWdhBru3N1SdrXQ6c= Received: from mimecast-mx01.redhat.com (mimecast-mx01.redhat.com [209.132.183.4]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-101-4qFRWYmUPuqycGei6rpleg-1; Thu, 05 Dec 2019 05:22:02 -0500 Received: from smtp.corp.redhat.com (int-mx05.intmail.prod.int.phx2.redhat.com [10.5.11.15]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx01.redhat.com (Postfix) with ESMTPS id 12A37183B700; Thu, 5 Dec 2019 10:22:01 +0000 (UTC) Received: from work-vm (unknown [10.36.118.4]) by smtp.corp.redhat.com (Postfix) with ESMTPS id 137405D6A5; Thu, 5 Dec 2019 10:21:53 +0000 (UTC) Date: Thu, 5 Dec 2019 10:21:51 +0000 From: "Dr. David Alan Gilbert" To: Philippe =?iso-8859-1?Q?Mathieu-Daud=E9?= Cc: Damien Hedde , Peter Maydell , QEMU Developers , Mark Burton , "Edgar E. Iglesias" , Alistair Francis , =?iso-8859-1?Q?Marc-Andr=E9?= Lureau , Paolo Bonzini , "Daniel P. Berrange" , Eduardo Habkost , qemu-arm Subject: Re: [PATCH v6 0/9] Clock framework API Message-ID: <20191205102151.GB2824@work-vm> References: <20190904125531.27545-1-damien.hedde@greensocs.com> <279a0fd5-1ea5-b3c7-27bb-b1d22db5e359@redhat.com> MIME-Version: 1.0 In-Reply-To: <279a0fd5-1ea5-b3c7-27bb-b1d22db5e359@redhat.com> User-Agent: Mutt/1.12.1 (2019-06-15) X-Scanned-By: MIMEDefang 2.79 on 10.5.11.15 X-MC-Unique: 4qFRWYmUPuqycGei6rpleg-1 X-Mimecast-Spam-Score: 0 Content-Type: text/plain; charset=iso-8859-1 Content-Transfer-Encoding: quoted-printable Content-Disposition: inline X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 207.211.31.120 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 05 Dec 2019 10:22:10 -0000 * Philippe Mathieu-Daud=E9 (philmd@redhat.com) wrote: > On 12/5/19 10:36 AM, Damien Hedde wrote: > > On 12/4/19 9:34 PM, Philippe Mathieu-Daud=E9 wrote: > > > On 12/4/19 5:40 PM, Damien Hedde wrote: > > > > On 12/2/19 5:15 PM, Peter Maydell wrote: > > > > >=20 > > > > > The one topic I think we could do with discussing is whether > > > > > a simple uint64_t giving the frequency of the clock in Hz is > > > > > the right representation. In particular in your patch 9 the > > > > > board has a clock frequency that's not a nice integer number > > > > > of Hz. I think Philippe also mentioned on irc some board where > > > > > the UART clock ends up at a weird frequency. Since the > > > > > representation of the frequency is baked into the migration > > > > > format it's going to be easier to get it right first rather > > > > > than trying to change it later. > > >=20 > > > Important precision for Damien, IIUC we can not migrate float/double = types. > > >=20 > > > > > So what should the representation be? Some random thoughts: > > > > >=20 > > > > > 1) ptimer internally uses a 'period plus fraction' representation= : > > > > > =A0 int64_t period is the integer part of the period in nanoseco= nds, > > > > > =A0 uint32_t period_frac is the fractional part of the period > > > > > (if you like you can think of this as "96-bit integer > > > > > period measured in units of one-2^32nd of a nanosecond"). > > > > > However its only public interfaces for setting the frequency > > > > > are (a) set the frequency in Hz (uint32_t) or (b) set > > > > > the period in nanoseconds (int64_t); the period_frac part > > > > > is used to handle frequencies which don't work out to > > > > > a nice whole number of nanoseconds per cycle. > > >=20 > > > This is very clear, thanks Peter! > > >=20 > > > The period+period_frac split allow us to migrate the 96 bits: > > >=20 > > > =A0=A0=A0=A0=A0=A0=A0 VMSTATE_UINT32(period_frac, ptimer_state), > > > =A0=A0=A0=A0=A0=A0=A0 VMSTATE_INT64(period, ptimer_state), > > >=20 > > > > > 2) I hear that SystemC uses "value plus a time unit", with > > > > > the smallest unit being a picosecond. (I think SystemC > > > > > also lets you specify the duty cycle, but we definitely > > > > > don't want to get into that!) > > > >=20 > > > > The "value" is internally stored in a 64bits unsigned integer. > > > >=20 > > > > >=20 > > > > > 3) QEMUTimers are basically just nanosecond timers > > >=20 > > > Similarly to SystemC, the QEMUTimers macro use a 'scale' unit, of: > > >=20 > > > #define SCALE_MS 1000000 > > > #define SCALE_US 1000 > > > #define SCALE_NS 1 > > >=20 > > > > >=20 > > > > > 4) The MAME emulator seems to work with periods of > > > > > 96-bit attoseconds (represented internally by a > > > > > 32-bit count of seconds plus a 64-bit count of > > > > > attoseconds). One attosecond is 1e-18 seconds. > > > > >=20 > > > > > Does anybody else have experience with other modelling > > > > > or emulator technology and how it represents clocks ? > > > >=20 > > > > 5) In linux, a clock rate is an "unsigned long" representing Hz. > > > >=20 > > > > >=20 > > > > > I feel we should at least be able to represent clocks > > > > > with the same accuracy that ptimer has. > > > >=20 > > > > Then is a maybe a good idea to store the period and not the frequen= cy in > > > > clocks so that we don't loose anything when we switch from a clock = to a > > > > ptimer ? > > >=20 > > > I think storing the period as an integer type is a good idea. > > >=20 > > > However if we store the period in nanoseconds, we get at most 1GHz > > > frequency. > > >=20 > > > The attosecond granularity feels overkill. > > >=20 > > > If we use a 96-bit integer to store picoseconds and use similar SCALE > > > macros we get to 1THz. > > >=20 > > > Regardless the unit chosen, as long it is integer, we can migrate it. > > > If can migrate the period, we don't need to migrate the frequency. > > > We can then use the float type in with the timer API to pass frequenc= ies > > > (which in the modeled hardware are ratios, likely not integers). > > >=20 > > > So we could use set_freq(100e6 / 3), set_freq(40e6 / 5.5) directly. > > >=20 > > > > Regarding the clock, I don't see any strong obstacle to switch > > > > internally to a period based value. > > > > The only things we have to choose is how to represent a disabled cl= ock. > > > > Since putting a "0" period to a ptimer will disable the timer in > > > > ptimer_reload(). We can choose that (and it's a good value because = we > > > > can multiply or divide it, it stays the same). > > > >=20 > > > > We could use the same representation as a ptimer. But if we don't k= eep a > > > > C number representation, then computation of frequencies/periods wi= ll be > > > > complicated at best and error prone. > > > >=20 > > > > =A0From that point of view, if we could stick to a 64bits integer = (or > > > > floating point number) it would be great. Can we use a sub nanoseco= nd > > > > unit that fit our needs ? > > > >=20 > > > > I did some test with a unit of 2^-32 of nanoseconds on 64bits (is t= hat > > > > the unit of the ptimer fractional part ?) and if I'm not mistaken > > > > + we have a frequency range from ~0.2Hz up to 10^18Hz > > > > + the resolution is decreasing with the frequency (but at 100Mhz we= have > > > > a ~2.3mHz resolution, at 1GHz it's ~0.23Hz and at 10GHz ~23Hz > > > > resolution). We hit 1Hz resolution around 2GHz. > > > >=20 > > > > So it sounds to me we have largely enough resolution to model clock= s in > > > > the range of frequencies we will have to handle. What do you think = ? > > >=20 > > > Back to your series, I wonder why you want to store the frequency in > > > ClockIn. ClockIn shouldn't be aware at what frequency it is clocked. > > > What matters is ClockOut, and each device exposing ClockOuts has a > > > (migrated) state of the output frequencies (rather in fields, or enco= ded > > > in registers). Once migrated, after the state is loaded back into the > > > device, we call post_load(). Isn't it a good place to call > > > clock_set_frequency(ClockOut[]) which will correctly set each ClockIn > > > frequency. > > >=20 > > > IOW I don't think ClockIn/ClockOut require to migrate a frequency fie= ld. > > >=20 > >=20 > > I agree it is more logical to store the frequency in clock out. But, > > regarding migration constraints, we have no choice I think because a > > device cannot rely on values that are migrated by another device for > > restoring its state. (when I checked, I add the impression that > > post_load()s are called on a per device migration basis not all at the > > end of migration). >=20 > Cc'ing David to clear that out. That's pretty much right; the 'post_load' is called on a structure at the e= nd of loading the data for that structure. You can do things at the end of migration; one way is to register a vm change state handler (search for qemu_add_vm_change_state_handler) and that means you get a kick when the VM starts running or a timer set in virtual time (not wall clock time because that becomes sensitive to the speed of the host). Somewhere ^^^ it says we can't migrate fp values; I'm not sure that's true; we've got a VMSTATE_FLOAT64 macro but I don't see it's used anywhere. Dave > > So we could store the frequency in clock out and migrate things there. > > But since we have no way to ensure all clock out states are migrated > > before some device fetch a ClockIn: we'll have to say "don't fetch one > > of your ClockIn frequency during migration and migrate the value > > yourself if you need it", pretty much like gpios. > >=20 > > So we will probably migrate all ClockOut and almost all ClockIn. > >=20 > > It would nice if we had a way to ensure clocks are migrated before > > devices try to use them. But I don't think this is possible. > >=20 > > -- > > Damien > >=20 >=20 -- Dr. David Alan Gilbert / dgilbert@redhat.com / Manchester, UK From MAILER-DAEMON Thu Dec 05 05:40:11 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1icoYN-0003i6-9Q for mharc-qemu-arm@gnu.org; Thu, 05 Dec 2019 05:40:11 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:57066) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1icoYH-0003f9-2H for qemu-arm@nongnu.org; Thu, 05 Dec 2019 05:40:10 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1icoYF-0000ms-BQ for qemu-arm@nongnu.org; Thu, 05 Dec 2019 05:40:04 -0500 Received: from us-smtp-1.mimecast.com ([205.139.110.61]:28292 helo=us-smtp-delivery-1.mimecast.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1icoYF-0000kj-1W for qemu-arm@nongnu.org; Thu, 05 Dec 2019 05:40:03 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1575542402; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=FWPcJ3ALPwUSQ0HyCh09oGg4lLyEV91wWtHkL2sGBRc=; b=iQfoSjwOjMYgJF6+D0xMfLem7jpfemZhzGZOkf5DyajCDfBgrFBtw4ER01aDQdU83j9EJc cbyw7ALQo8UFSQ8lsZDxSXlAIJo+2lSGlNOlW7a5/LSTKGjYJ0t4KS+ZQ39y2IR5/gt2Kx LCnm3YG+XP/4KyqRuSgnwfOMHn48SCA= Received: from mimecast-mx01.redhat.com (mimecast-mx01.redhat.com [209.132.183.4]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-322-ZNbHaoY1OZuFyVuHb8N5Mw-1; Thu, 05 Dec 2019 05:39:59 -0500 Received: from smtp.corp.redhat.com (int-mx01.intmail.prod.int.phx2.redhat.com [10.5.11.11]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx01.redhat.com (Postfix) with ESMTPS id 1D76018543A3; Thu, 5 Dec 2019 10:39:58 +0000 (UTC) Received: from [10.36.116.117] (ovpn-116-117.ams2.redhat.com [10.36.116.117]) by smtp.corp.redhat.com (Postfix) with ESMTPS id 04814600F0; Thu, 5 Dec 2019 10:39:56 +0000 (UTC) Subject: Re: [PATCH 3/5] hw/arm/smmuv3: Align stream table base address to table size To: Simon Veith , qemu-devel@nongnu.org, qemu-arm@nongnu.org References: <1575467748-28898-1-git-send-email-sveith@amazon.de> <1575467748-28898-4-git-send-email-sveith@amazon.de> From: Auger Eric Message-ID: Date: Thu, 5 Dec 2019 11:39:55 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101 Thunderbird/60.4.0 MIME-Version: 1.0 In-Reply-To: <1575467748-28898-4-git-send-email-sveith@amazon.de> Content-Language: en-US X-Scanned-By: MIMEDefang 2.79 on 10.5.11.11 X-MC-Unique: ZNbHaoY1OZuFyVuHb8N5Mw-1 X-Mimecast-Spam-Score: 0 Content-Type: text/plain; charset=windows-1252 Content-Transfer-Encoding: 7bit X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 205.139.110.61 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 05 Dec 2019 10:40:10 -0000 Hi Simon, On 12/4/19 2:55 PM, Simon Veith wrote: > Per the specification, and as observed in hardware, the SMMUv3 aligns > the SMMU_STRTAB_BASE address to the size of the table by masking out the > respective least significant bits in the ADDR field. > > Apply this masking logic to our smmu_find_ste() lookup function per the > specification. > > ref. ARM IHI 0070C, section 6.3.23. > > Signed-off-by: Simon Veith > Cc: Eric Auger > Cc: qemu-devel@nongnu.org > Cc: qemu-arm@nongnu.org > --- > hw/arm/smmuv3.c | 29 +++++++++++++++++++++++++---- > 1 file changed, 25 insertions(+), 4 deletions(-) > > diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c > index aad4639..2d6c275 100644 > --- a/hw/arm/smmuv3.c > +++ b/hw/arm/smmuv3.c > @@ -376,8 +376,9 @@ bad_ste: > static int smmu_find_ste(SMMUv3State *s, uint32_t sid, STE *ste, > SMMUEventInfo *event) > { > - dma_addr_t addr; > + dma_addr_t addr, strtab_base; > uint32_t log2size; > + int strtab_size_shift; > int ret; > > trace_smmuv3_find_ste(sid, s->features, s->sid_split); > @@ -391,10 +392,23 @@ static int smmu_find_ste(SMMUv3State *s, uint32_t sid, STE *ste, > } > if (s->features & SMMU_FEATURE_2LVL_STE) { > int l1_ste_offset, l2_ste_offset, max_l2_ste, span; > - dma_addr_t strtab_base, l1ptr, l2ptr; > + dma_addr_t l1ptr, l2ptr; > STEDesc l1std; > > - strtab_base = s->strtab_base & SMMU_BASE_ADDR_MASK; > + /* > + * Align strtab base address to table size. For this purpose, assume it > + * is not bounded by SMMU_IDR1_SIDSIZE. > + */ > + strtab_size_shift = log2size - s->sid_split - 1 + 3; Maybe just as the spec use MAX(5, (LOG2SIZE-SPLIT-1+3))? > + if (strtab_size_shift < DMA_ADDR_BITS) { > + if (strtab_size_shift < 5) { > + strtab_size_shift = 5; > + } > + strtab_base = s->strtab_base & SMMU_BASE_ADDR_MASK & > + ~((1ULL << strtab_size_shift) - 1); nit: you may use ~MAKE_64BIT_MASK(0, strtab_size_shift) > + } else { see below > + strtab_base = 0; > + } > l1_ste_offset = sid >> s->sid_split; > l2_ste_offset = sid & ((1 << s->sid_split) - 1); > l1ptr = (dma_addr_t)(strtab_base + l1_ste_offset * sizeof(l1std)); > @@ -433,7 +447,14 @@ static int smmu_find_ste(SMMUv3State *s, uint32_t sid, STE *ste, > } > addr = l2ptr + l2_ste_offset * sizeof(*ste); > } else { > - addr = (s->strtab_base & SMMU_BASE_ADDR_MASK) + sid * sizeof(*ste); > + strtab_size_shift = log2size + 5; > + if (strtab_size_shift < DMA_ADDR_BITS) { > + strtab_base = s->strtab_base & SMMU_BASE_ADDR_MASK & > + ~((1ULL << strtab_size_shift) - 1); > + } else { Can it happen? I understand LOG2SIZE <= SMMU_S_IDR_5.SIDSIZE and SIDSIZE is max 32. Same above? > + strtab_base = 0; > + } > + addr = strtab_base + sid * sizeof(*ste); > } > > if (smmu_get_ste(s, addr, ste, event)) { > Thank you for those series fixes. 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[88.21.103.182]) by smtp.gmail.com with ESMTPSA id w13sm12376880wru.38.2019.12.05.02.44.32 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 05 Dec 2019 02:44:32 -0800 (PST) Subject: Re: [PATCH v6 0/9] Clock framework API To: "Dr. David Alan Gilbert" , Peter Maydell , =?UTF-8?Q?Alex_Benn=c3=a9e?= , Richard Henderson Cc: Damien Hedde , QEMU Developers , Mark Burton , "Edgar E. Iglesias" , Alistair Francis , =?UTF-8?Q?Marc-Andr=c3=a9_Lureau?= , Paolo Bonzini , "Daniel P. Berrange" , Eduardo Habkost , qemu-arm References: <20190904125531.27545-1-damien.hedde@greensocs.com> <279a0fd5-1ea5-b3c7-27bb-b1d22db5e359@redhat.com> <20191205102151.GB2824@work-vm> From: =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= Message-ID: Date: Thu, 5 Dec 2019 11:44:31 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.2.2 MIME-Version: 1.0 In-Reply-To: <20191205102151.GB2824@work-vm> Content-Language: en-US X-MC-Unique: w1iAgqUANdKWHeARTAdzlg-1 X-Mimecast-Spam-Score: 0 Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 207.211.31.120 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 05 Dec 2019 10:44:41 -0000 On 12/5/19 11:21 AM, Dr. David Alan Gilbert wrote: > * Philippe Mathieu-Daud=C3=A9 (philmd@redhat.com) wrote: >> On 12/5/19 10:36 AM, Damien Hedde wrote: >>> On 12/4/19 9:34 PM, Philippe Mathieu-Daud=C3=A9 wrote: >>>> On 12/4/19 5:40 PM, Damien Hedde wrote: >>>>> On 12/2/19 5:15 PM, Peter Maydell wrote: >>>>>> >>>>>> The one topic I think we could do with discussing is whether >>>>>> a simple uint64_t giving the frequency of the clock in Hz is >>>>>> the right representation. In particular in your patch 9 the >>>>>> board has a clock frequency that's not a nice integer number >>>>>> of Hz. I think Philippe also mentioned on irc some board where >>>>>> the UART clock ends up at a weird frequency. Since the >>>>>> representation of the frequency is baked into the migration >>>>>> format it's going to be easier to get it right first rather >>>>>> than trying to change it later. >>>> >>>> Important precision for Damien, IIUC we can not migrate float/double t= ypes. >>>> >>>>>> So what should the representation be? Some random thoughts: >>>>>> >>>>>> 1) ptimer internally uses a 'period plus fraction' representation: >>>>>> =C2=A0 int64_t period is the integer part of the period in nanosec= onds, >>>>>> =C2=A0 uint32_t period_frac is the fractional part of the period >>>>>> (if you like you can think of this as "96-bit integer >>>>>> period measured in units of one-2^32nd of a nanosecond"). >>>>>> However its only public interfaces for setting the frequency >>>>>> are (a) set the frequency in Hz (uint32_t) or (b) set >>>>>> the period in nanoseconds (int64_t); the period_frac part >>>>>> is used to handle frequencies which don't work out to >>>>>> a nice whole number of nanoseconds per cycle. >>>> >>>> This is very clear, thanks Peter! >>>> >>>> The period+period_frac split allow us to migrate the 96 bits: >>>> >>>> =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 VMSTATE_UINT32(period_fra= c, ptimer_state), >>>> =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 VMSTATE_INT64(period, pti= mer_state), >>>> >>>>>> 2) I hear that SystemC uses "value plus a time unit", with >>>>>> the smallest unit being a picosecond. (I think SystemC >>>>>> also lets you specify the duty cycle, but we definitely >>>>>> don't want to get into that!) >>>>> >>>>> The "value" is internally stored in a 64bits unsigned integer. >>>>> >>>>>> >>>>>> 3) QEMUTimers are basically just nanosecond timers >>>> >>>> Similarly to SystemC, the QEMUTimers macro use a 'scale' unit, of: >>>> >>>> #define SCALE_MS 1000000 >>>> #define SCALE_US 1000 >>>> #define SCALE_NS 1 >>>> >>>>>> >>>>>> 4) The MAME emulator seems to work with periods of >>>>>> 96-bit attoseconds (represented internally by a >>>>>> 32-bit count of seconds plus a 64-bit count of >>>>>> attoseconds). One attosecond is 1e-18 seconds. >>>>>> >>>>>> Does anybody else have experience with other modelling >>>>>> or emulator technology and how it represents clocks ? >>>>> >>>>> 5) In linux, a clock rate is an "unsigned long" representing Hz. >>>>> >>>>>> >>>>>> I feel we should at least be able to represent clocks >>>>>> with the same accuracy that ptimer has. >>>>> >>>>> Then is a maybe a good idea to store the period and not the frequency= in >>>>> clocks so that we don't loose anything when we switch from a clock to= a >>>>> ptimer ? >>>> >>>> I think storing the period as an integer type is a good idea. >>>> >>>> However if we store the period in nanoseconds, we get at most 1GHz >>>> frequency. >>>> >>>> The attosecond granularity feels overkill. >>>> >>>> If we use a 96-bit integer to store picoseconds and use similar SCALE >>>> macros we get to 1THz. >>>> >>>> Regardless the unit chosen, as long it is integer, we can migrate it. >>>> If can migrate the period, we don't need to migrate the frequency. >>>> We can then use the float type in with the timer API to pass frequenci= es >>>> (which in the modeled hardware are ratios, likely not integers). >>>> >>>> So we could use set_freq(100e6 / 3), set_freq(40e6 / 5.5) directly. >>>> >>>>> Regarding the clock, I don't see any strong obstacle to switch >>>>> internally to a period based value. >>>>> The only things we have to choose is how to represent a disabled cloc= k. >>>>> Since putting a "0" period to a ptimer will disable the timer in >>>>> ptimer_reload(). We can choose that (and it's a good value because we >>>>> can multiply or divide it, it stays the same). >>>>> >>>>> We could use the same representation as a ptimer. But if we don't kee= p a >>>>> C number representation, then computation of frequencies/periods will= be >>>>> complicated at best and error prone. >>>>> >>>>> =C2=A0From that point of view, if we could stick to a 64bits intege= r (or >>>>> floating point number) it would be great. Can we use a sub nanosecond >>>>> unit that fit our needs ? >>>>> >>>>> I did some test with a unit of 2^-32 of nanoseconds on 64bits (is tha= t >>>>> the unit of the ptimer fractional part ?) and if I'm not mistaken >>>>> + we have a frequency range from ~0.2Hz up to 10^18Hz >>>>> + the resolution is decreasing with the frequency (but at 100Mhz we h= ave >>>>> a ~2.3mHz resolution, at 1GHz it's ~0.23Hz and at 10GHz ~23Hz >>>>> resolution). We hit 1Hz resolution around 2GHz. >>>>> >>>>> So it sounds to me we have largely enough resolution to model clocks = in >>>>> the range of frequencies we will have to handle. What do you think ? >>>> >>>> Back to your series, I wonder why you want to store the frequency in >>>> ClockIn. ClockIn shouldn't be aware at what frequency it is clocked. >>>> What matters is ClockOut, and each device exposing ClockOuts has a >>>> (migrated) state of the output frequencies (rather in fields, or encod= ed >>>> in registers). Once migrated, after the state is loaded back into the >>>> device, we call post_load(). Isn't it a good place to call >>>> clock_set_frequency(ClockOut[]) which will correctly set each ClockIn >>>> frequency. >>>> >>>> IOW I don't think ClockIn/ClockOut require to migrate a frequency fiel= d. >>>> >>> >>> I agree it is more logical to store the frequency in clock out. But, >>> regarding migration constraints, we have no choice I think because a >>> device cannot rely on values that are migrated by another device for >>> restoring its state. (when I checked, I add the impression that >>> post_load()s are called on a per device migration basis not all at the >>> end of migration). >> >> Cc'ing David to clear that out. >=20 >=20 > That's pretty much right; the 'post_load' is called on a structure at the= end > of loading the data for that structure. >=20 > You can do things at the end of migration; one way is to register a > vm change state handler (search for qemu_add_vm_change_state_handler) > and that means you get a kick when the VM starts running or a timer set > in virtual time (not wall clock time because that becomes sensitive > to the speed of the host). >=20 > Somewhere ^^^ it says we can't migrate fp values; I'm not sure that's > true; we've got a VMSTATE_FLOAT64 macro but I don't see it's used > anywhere. OK, Cc'ing Alex & Richard now, because I guess remember a discussion=20 about "we can not migrate floats because this is a architectural=20 implementation, so cross-architecture migration is likely to fail". But=20 I can't find trace of a such discussion on the list or IRC logs. Maybe this was instead about whether we can use the host FPU registers. I hope I'm wrong and confuse, this is a great news for me to know we can migrate floats! > Dave >=20 >>> So we could store the frequency in clock out and migrate things there. >>> But since we have no way to ensure all clock out states are migrated >>> before some device fetch a ClockIn: we'll have to say "don't fetch one >>> of your ClockIn frequency during migration and migrate the value >>> yourself if you need it", pretty much like gpios. >>> >>> So we will probably migrate all ClockOut and almost all ClockIn. >>> >>> It would nice if we had a way to ensure clocks are migrated before >>> devices try to use them. But I don't think this is possible. >>> >>> -- >>> Damien >>> >> > -- > Dr. David Alan Gilbert / dgilbert@redhat.com / Manchester, UK >=20 From MAILER-DAEMON Thu Dec 05 05:56:33 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1icooD-0001iu-Pq for mharc-qemu-arm@gnu.org; Thu, 05 Dec 2019 05:56:33 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:55976) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1icooA-0001iX-Sj for qemu-arm@nongnu.org; Thu, 05 Dec 2019 05:56:32 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1icoo8-0001vt-4w for qemu-arm@nongnu.org; Thu, 05 Dec 2019 05:56:30 -0500 Received: from us-smtp-1.mimecast.com ([207.211.31.81]:58269 helo=us-smtp-delivery-1.mimecast.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1icoo7-0001rn-Uz for qemu-arm@nongnu.org; Thu, 05 Dec 2019 05:56:28 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1575543387; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=6dV5kiwKR7VmLdsxeym7avGhPpFE89PHlLOVSxNXm6Y=; b=XpsWDL6GMcF1FAttQYzQ1kJaQ5m8ZaHLO5TcLVywkqK/joHaYy8NVvU/djZVM6WxmMaoXC UEQCWWzHgJacYdMQwIxlLduwlhknLxmPA+lZ9fGDiAUc1KjV6lJ9OrowJM7TCBO0S54Mgy bvXnSxiMSrMS6xzsgYEDxrDfbp04BEo= Received: from mimecast-mx01.redhat.com (mimecast-mx01.redhat.com [209.132.183.4]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-37-YR65CIVhMFKlz3AU4-YRYQ-1; Thu, 05 Dec 2019 05:56:25 -0500 Received: from smtp.corp.redhat.com (int-mx08.intmail.prod.int.phx2.redhat.com [10.5.11.23]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx01.redhat.com (Postfix) with ESMTPS id 0EE47800D54; Thu, 5 Dec 2019 10:56:24 +0000 (UTC) Received: from work-vm (unknown [10.36.118.4]) by smtp.corp.redhat.com (Postfix) with ESMTPS id 5778619488; Thu, 5 Dec 2019 10:56:15 +0000 (UTC) Date: Thu, 5 Dec 2019 10:56:13 +0000 From: "Dr. David Alan Gilbert" To: Philippe =?iso-8859-1?Q?Mathieu-Daud=E9?= Cc: Peter Maydell , Alex =?iso-8859-1?Q?Benn=E9e?= , Richard Henderson , Damien Hedde , QEMU Developers , Mark Burton , "Edgar E. Iglesias" , Alistair Francis , =?iso-8859-1?Q?Marc-Andr=E9?= Lureau , Paolo Bonzini , "Daniel P. Berrange" , Eduardo Habkost , qemu-arm Subject: Re: [PATCH v6 0/9] Clock framework API Message-ID: <20191205105613.GE2824@work-vm> References: <20190904125531.27545-1-damien.hedde@greensocs.com> <279a0fd5-1ea5-b3c7-27bb-b1d22db5e359@redhat.com> <20191205102151.GB2824@work-vm> MIME-Version: 1.0 In-Reply-To: User-Agent: Mutt/1.12.1 (2019-06-15) X-Scanned-By: MIMEDefang 2.84 on 10.5.11.23 X-MC-Unique: YR65CIVhMFKlz3AU4-YRYQ-1 X-Mimecast-Spam-Score: 0 Content-Type: text/plain; charset=iso-8859-1 Content-Transfer-Encoding: quoted-printable Content-Disposition: inline X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 207.211.31.81 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 05 Dec 2019 10:56:33 -0000 * Philippe Mathieu-Daud=E9 (philmd@redhat.com) wrote: > On 12/5/19 11:21 AM, Dr. David Alan Gilbert wrote: > > * Philippe Mathieu-Daud=E9 (philmd@redhat.com) wrote: > > > On 12/5/19 10:36 AM, Damien Hedde wrote: > > > > On 12/4/19 9:34 PM, Philippe Mathieu-Daud=E9 wrote: > > > > > On 12/4/19 5:40 PM, Damien Hedde wrote: > > > > > > On 12/2/19 5:15 PM, Peter Maydell wrote: > > > > > > >=20 > > > > > > > The one topic I think we could do with discussing is whether > > > > > > > a simple uint64_t giving the frequency of the clock in Hz is > > > > > > > the right representation. In particular in your patch 9 the > > > > > > > board has a clock frequency that's not a nice integer number > > > > > > > of Hz. I think Philippe also mentioned on irc some board wher= e > > > > > > > the UART clock ends up at a weird frequency. Since the > > > > > > > representation of the frequency is baked into the migration > > > > > > > format it's going to be easier to get it right first rather > > > > > > > than trying to change it later. > > > > >=20 > > > > > Important precision for Damien, IIUC we can not migrate float/dou= ble types. > > > > >=20 > > > > > > > So what should the representation be? Some random thoughts: > > > > > > >=20 > > > > > > > 1) ptimer internally uses a 'period plus fraction' representa= tion: > > > > > > > =A0 int64_t period is the integer part of the period in nan= oseconds, > > > > > > > =A0 uint32_t period_frac is the fractional part of the peri= od > > > > > > > (if you like you can think of this as "96-bit integer > > > > > > > period measured in units of one-2^32nd of a nanosecond"). > > > > > > > However its only public interfaces for setting the frequency > > > > > > > are (a) set the frequency in Hz (uint32_t) or (b) set > > > > > > > the period in nanoseconds (int64_t); the period_frac part > > > > > > > is used to handle frequencies which don't work out to > > > > > > > a nice whole number of nanoseconds per cycle. > > > > >=20 > > > > > This is very clear, thanks Peter! > > > > >=20 > > > > > The period+period_frac split allow us to migrate the 96 bits: > > > > >=20 > > > > > =A0=A0=A0=A0=A0=A0=A0 VMSTATE_UINT32(period_frac, ptimer_state)= , > > > > > =A0=A0=A0=A0=A0=A0=A0 VMSTATE_INT64(period, ptimer_state), > > > > >=20 > > > > > > > 2) I hear that SystemC uses "value plus a time unit", with > > > > > > > the smallest unit being a picosecond. (I think SystemC > > > > > > > also lets you specify the duty cycle, but we definitely > > > > > > > don't want to get into that!) > > > > > >=20 > > > > > > The "value" is internally stored in a 64bits unsigned integer. > > > > > >=20 > > > > > > >=20 > > > > > > > 3) QEMUTimers are basically just nanosecond timers > > > > >=20 > > > > > Similarly to SystemC, the QEMUTimers macro use a 'scale' unit, of= : > > > > >=20 > > > > > #define SCALE_MS 1000000 > > > > > #define SCALE_US 1000 > > > > > #define SCALE_NS 1 > > > > >=20 > > > > > > >=20 > > > > > > > 4) The MAME emulator seems to work with periods of > > > > > > > 96-bit attoseconds (represented internally by a > > > > > > > 32-bit count of seconds plus a 64-bit count of > > > > > > > attoseconds). One attosecond is 1e-18 seconds. > > > > > > >=20 > > > > > > > Does anybody else have experience with other modelling > > > > > > > or emulator technology and how it represents clocks ? > > > > > >=20 > > > > > > 5) In linux, a clock rate is an "unsigned long" representing Hz= . > > > > > >=20 > > > > > > >=20 > > > > > > > I feel we should at least be able to represent clocks > > > > > > > with the same accuracy that ptimer has. > > > > > >=20 > > > > > > Then is a maybe a good idea to store the period and not the fre= quency in > > > > > > clocks so that we don't loose anything when we switch from a cl= ock to a > > > > > > ptimer ? > > > > >=20 > > > > > I think storing the period as an integer type is a good idea. > > > > >=20 > > > > > However if we store the period in nanoseconds, we get at most 1GH= z > > > > > frequency. > > > > >=20 > > > > > The attosecond granularity feels overkill. > > > > >=20 > > > > > If we use a 96-bit integer to store picoseconds and use similar S= CALE > > > > > macros we get to 1THz. > > > > >=20 > > > > > Regardless the unit chosen, as long it is integer, we can migrate= it. > > > > > If can migrate the period, we don't need to migrate the frequency= . > > > > > We can then use the float type in with the timer API to pass freq= uencies > > > > > (which in the modeled hardware are ratios, likely not integers). > > > > >=20 > > > > > So we could use set_freq(100e6 / 3), set_freq(40e6 / 5.5) directl= y. > > > > >=20 > > > > > > Regarding the clock, I don't see any strong obstacle to switch > > > > > > internally to a period based value. > > > > > > The only things we have to choose is how to represent a disable= d clock. > > > > > > Since putting a "0" period to a ptimer will disable the timer i= n > > > > > > ptimer_reload(). We can choose that (and it's a good value beca= use we > > > > > > can multiply or divide it, it stays the same). > > > > > >=20 > > > > > > We could use the same representation as a ptimer. But if we don= 't keep a > > > > > > C number representation, then computation of frequencies/period= s will be > > > > > > complicated at best and error prone. > > > > > >=20 > > > > > > =A0From that point of view, if we could stick to a 64bits int= eger (or > > > > > > floating point number) it would be great. Can we use a sub nano= second > > > > > > unit that fit our needs ? > > > > > >=20 > > > > > > I did some test with a unit of 2^-32 of nanoseconds on 64bits (= is that > > > > > > the unit of the ptimer fractional part ?) and if I'm not mistak= en > > > > > > + we have a frequency range from ~0.2Hz up to 10^18Hz > > > > > > + the resolution is decreasing with the frequency (but at 100Mh= z we have > > > > > > a ~2.3mHz resolution, at 1GHz it's ~0.23Hz and at 10GHz ~23Hz > > > > > > resolution). We hit 1Hz resolution around 2GHz. > > > > > >=20 > > > > > > So it sounds to me we have largely enough resolution to model c= locks in > > > > > > the range of frequencies we will have to handle. What do you th= ink ? > > > > >=20 > > > > > Back to your series, I wonder why you want to store the frequency= in > > > > > ClockIn. ClockIn shouldn't be aware at what frequency it is clock= ed. > > > > > What matters is ClockOut, and each device exposing ClockOuts has = a > > > > > (migrated) state of the output frequencies (rather in fields, or = encoded > > > > > in registers). Once migrated, after the state is loaded back into= the > > > > > device, we call post_load(). Isn't it a good place to call > > > > > clock_set_frequency(ClockOut[]) which will correctly set each Clo= ckIn > > > > > frequency. > > > > >=20 > > > > > IOW I don't think ClockIn/ClockOut require to migrate a frequency= field. > > > > >=20 > > > >=20 > > > > I agree it is more logical to store the frequency in clock out. But= , > > > > regarding migration constraints, we have no choice I think because = a > > > > device cannot rely on values that are migrated by another device fo= r > > > > restoring its state. (when I checked, I add the impression that > > > > post_load()s are called on a per device migration basis not all at = the > > > > end of migration). > > >=20 > > > Cc'ing David to clear that out. > >=20 > >=20 > > That's pretty much right; the 'post_load' is called on a structure at t= he end > > of loading the data for that structure. > >=20 > > You can do things at the end of migration; one way is to register a > > vm change state handler (search for qemu_add_vm_change_state_handler) > > and that means you get a kick when the VM starts running or a timer set > > in virtual time (not wall clock time because that becomes sensitive > > to the speed of the host). > >=20 > > Somewhere ^^^ it says we can't migrate fp values; I'm not sure that's > > true; we've got a VMSTATE_FLOAT64 macro but I don't see it's used > > anywhere. >=20 > OK, Cc'ing Alex & Richard now, because I guess remember a discussion abou= t > "we can not migrate floats because this is a architectural implementation= , > so cross-architecture migration is likely to fail". But I can't find trac= e > of a such discussion on the list or IRC logs. > Maybe this was instead about whether we can use the host FPU registers. We have to be careful when migrating the FP registers within a CPU, since they can have crazy values that are not valid/weird corners of standard FP encodings (e.g. if the guest just uses the FP registers as a spare 64bit register - which is perfectly valid on some architectures). However, migrating an actual floating point real world measurement should be fine. I'm assuming we can rely on 64 bit IEEE FP format on the wire being portable. Dave > I hope I'm wrong and confuse, this is a great news for me to know we > can migrate floats! >=20 > > Dave > >=20 > > > > So we could store the frequency in clock out and migrate things the= re. > > > > But since we have no way to ensure all clock out states are migrate= d > > > > before some device fetch a ClockIn: we'll have to say "don't fetch = one > > > > of your ClockIn frequency during migration and migrate the value > > > > yourself if you need it", pretty much like gpios. > > > >=20 > > > > So we will probably migrate all ClockOut and almost all ClockIn. > > > >=20 > > > > It would nice if we had a way to ensure clocks are migrated before > > > > devices try to use them. But I don't think this is possible. > > > >=20 > > > > -- > > > > Damien > > > >=20 > > >=20 > > -- > > Dr. David Alan Gilbert / dgilbert@redhat.com / Manchester, UK > >=20 >=20 -- Dr. David Alan Gilbert / dgilbert@redhat.com / Manchester, UK From MAILER-DAEMON Thu Dec 05 06:02:13 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1icoth-00053d-Nw for mharc-qemu-arm@gnu.org; Thu, 05 Dec 2019 06:02:13 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:55510) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1icotZ-0004zi-Sy for qemu-arm@nongnu.org; Thu, 05 Dec 2019 06:02:11 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1icotX-0007Gf-HJ for qemu-arm@nongnu.org; Thu, 05 Dec 2019 06:02:05 -0500 Received: from us-smtp-2.mimecast.com ([207.211.31.81]:42980 helo=us-smtp-delivery-1.mimecast.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1icotX-0007DS-Aa for qemu-arm@nongnu.org; Thu, 05 Dec 2019 06:02:03 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1575543722; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=nXUqmRSry+2VkpQAsGw0698CR5HOjXyePDV6ReLRvGg=; b=ezbMdMnbIp3EVdu+0GzAcd9/Z2yEVaLWDO0b3a6cDVWojniKKWirNje7SKtxwX6QaZug/p 1e+UE8tl7SoZ9zQ7up3Oasr9F0x3T3spf/Q6mMdQfbO4U3V5SfWcMHuA0lchqeBG4oRjbK lyA990tzD/GKtmZumDB4tieRiD6aE1w= Received: from mail-wm1-f71.google.com (mail-wm1-f71.google.com [209.85.128.71]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-233-EeIWzMj6MjG-068_uuXNxg-1; Thu, 05 Dec 2019 06:02:01 -0500 Received: by mail-wm1-f71.google.com with SMTP id s12so843336wmc.6 for ; Thu, 05 Dec 2019 03:02:00 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:subject:to:cc:references:from:message-id:date :user-agent:mime-version:in-reply-to:content-language :content-transfer-encoding; bh=DN+oinf0xZ0J1+dC2H6zxxOHcMlos5bPEPinjCdAlNw=; b=EL27avlGvOb7Vayw92zuC0GCfPP0Bow9GjeWjlWh5eRxhGG85ROV5ezufpq9zNCmNC Fxh39lyWKv+u1PSDyn9HpXzfnC5I/XhEbct2lFAo/biGAFLg4x+uKY5cKiRgBp1ZLSuS JcMv8FalI+BHHANg7pzUnwrIUgpb+x/WognFdVO2mQ9PN/Uh7Gi1d8ufxg9temZa9Mm3 mFszqjljO+WCWVZ9p993xu9QnFQeFjCNUF77cNlsel+Apo2N7Kq98rEibgM5aOMXkSkG 30CqDh0WoYYW6RpLhLyEN37dt2T23sr/MTzTfdEoEV+Nv2qagBW/fdc5I1Dd/juZLvdv gXBA== X-Gm-Message-State: APjAAAVS14EUtzjbduXyfnMlOUfHhj8xPHdVZCc4UNw+gn2m2VFO8sH1 9v1uFnHQ3RjewEBQT+tK3SCEJJVt/RZvTqFl7S3E62Hy0ExVGsCOc2i6x0GJh5Y6jlFWR2N7Kgb iCImdDnxYU6bA X-Received: by 2002:adf:fe90:: with SMTP id l16mr10000828wrr.265.1575543719579; Thu, 05 Dec 2019 03:01:59 -0800 (PST) X-Google-Smtp-Source: APXvYqzXZ0Rww2qEp9kVeRaZXZF++mKTIh7PhNbPyiY2aZ0NvI5vs8Pl7o1hBbNlH7EYC6E3bxR3dA== X-Received: by 2002:adf:fe90:: with SMTP id l16mr10000755wrr.265.1575543719122; Thu, 05 Dec 2019 03:01:59 -0800 (PST) Received: from [192.168.1.35] (182.red-88-21-103.staticip.rima-tde.net. [88.21.103.182]) by smtp.gmail.com with ESMTPSA id w8sm10742098wmm.0.2019.12.05.03.01.57 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 05 Dec 2019 03:01:58 -0800 (PST) Subject: Re: [PATCH v6 0/9] Clock framework API To: "Dr. David Alan Gilbert" , Cleber Rosa Cc: Peter Maydell , =?UTF-8?Q?Alex_Benn=c3=a9e?= , Richard Henderson , Damien Hedde , QEMU Developers , Mark Burton , "Edgar E. Iglesias" , Alistair Francis , =?UTF-8?Q?Marc-Andr=c3=a9_Lureau?= , Paolo Bonzini , "Daniel P. Berrange" , Eduardo Habkost , qemu-arm References: <20190904125531.27545-1-damien.hedde@greensocs.com> <279a0fd5-1ea5-b3c7-27bb-b1d22db5e359@redhat.com> <20191205102151.GB2824@work-vm> <20191205105613.GE2824@work-vm> From: =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= Message-ID: <138ef325-dc9a-2ca5-9044-c67ffdabb968@redhat.com> Date: Thu, 5 Dec 2019 12:01:56 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.2.2 MIME-Version: 1.0 In-Reply-To: <20191205105613.GE2824@work-vm> Content-Language: en-US X-MC-Unique: EeIWzMj6MjG-068_uuXNxg-1 X-Mimecast-Spam-Score: 0 Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 207.211.31.81 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 05 Dec 2019 11:02:11 -0000 On 12/5/19 11:56 AM, Dr. David Alan Gilbert wrote: > * Philippe Mathieu-Daud=C3=A9 (philmd@redhat.com) wrote: >> On 12/5/19 11:21 AM, Dr. David Alan Gilbert wrote: >>> * Philippe Mathieu-Daud=C3=A9 (philmd@redhat.com) wrote: >>>> On 12/5/19 10:36 AM, Damien Hedde wrote: >>>>> On 12/4/19 9:34 PM, Philippe Mathieu-Daud=C3=A9 wrote: >>>>>> On 12/4/19 5:40 PM, Damien Hedde wrote: >>>>>>> On 12/2/19 5:15 PM, Peter Maydell wrote: >>>>>>>> >>>>>>>> The one topic I think we could do with discussing is whether >>>>>>>> a simple uint64_t giving the frequency of the clock in Hz is >>>>>>>> the right representation. In particular in your patch 9 the >>>>>>>> board has a clock frequency that's not a nice integer number >>>>>>>> of Hz. I think Philippe also mentioned on irc some board where >>>>>>>> the UART clock ends up at a weird frequency. Since the >>>>>>>> representation of the frequency is baked into the migration >>>>>>>> format it's going to be easier to get it right first rather >>>>>>>> than trying to change it later. >>>>>> >>>>>> Important precision for Damien, IIUC we can not migrate float/double= types. >>>>>> >>>>>>>> So what should the representation be? Some random thoughts: >>>>>>>> >>>>>>>> 1) ptimer internally uses a 'period plus fraction' representation: >>>>>>>> =C2=A0 int64_t period is the integer part of the period in nano= seconds, >>>>>>>> =C2=A0 uint32_t period_frac is the fractional part of the perio= d >>>>>>>> (if you like you can think of this as "96-bit integer >>>>>>>> period measured in units of one-2^32nd of a nanosecond"). >>>>>>>> However its only public interfaces for setting the frequency >>>>>>>> are (a) set the frequency in Hz (uint32_t) or (b) set >>>>>>>> the period in nanoseconds (int64_t); the period_frac part >>>>>>>> is used to handle frequencies which don't work out to >>>>>>>> a nice whole number of nanoseconds per cycle. >>>>>> >>>>>> This is very clear, thanks Peter! >>>>>> >>>>>> The period+period_frac split allow us to migrate the 96 bits: >>>>>> >>>>>> =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 VMSTATE_UINT32(period_= frac, ptimer_state), >>>>>> =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 VMSTATE_INT64(period, = ptimer_state), >>>>>> >>>>>>>> 2) I hear that SystemC uses "value plus a time unit", with >>>>>>>> the smallest unit being a picosecond. (I think SystemC >>>>>>>> also lets you specify the duty cycle, but we definitely >>>>>>>> don't want to get into that!) >>>>>>> >>>>>>> The "value" is internally stored in a 64bits unsigned integer. >>>>>>> >>>>>>>> >>>>>>>> 3) QEMUTimers are basically just nanosecond timers >>>>>> >>>>>> Similarly to SystemC, the QEMUTimers macro use a 'scale' unit, of: >>>>>> >>>>>> #define SCALE_MS 1000000 >>>>>> #define SCALE_US 1000 >>>>>> #define SCALE_NS 1 >>>>>> >>>>>>>> >>>>>>>> 4) The MAME emulator seems to work with periods of >>>>>>>> 96-bit attoseconds (represented internally by a >>>>>>>> 32-bit count of seconds plus a 64-bit count of >>>>>>>> attoseconds). One attosecond is 1e-18 seconds. >>>>>>>> >>>>>>>> Does anybody else have experience with other modelling >>>>>>>> or emulator technology and how it represents clocks ? >>>>>>> >>>>>>> 5) In linux, a clock rate is an "unsigned long" representing Hz. >>>>>>> >>>>>>>> >>>>>>>> I feel we should at least be able to represent clocks >>>>>>>> with the same accuracy that ptimer has. >>>>>>> >>>>>>> Then is a maybe a good idea to store the period and not the frequen= cy in >>>>>>> clocks so that we don't loose anything when we switch from a clock = to a >>>>>>> ptimer ? >>>>>> >>>>>> I think storing the period as an integer type is a good idea. >>>>>> >>>>>> However if we store the period in nanoseconds, we get at most 1GHz >>>>>> frequency. >>>>>> >>>>>> The attosecond granularity feels overkill. >>>>>> >>>>>> If we use a 96-bit integer to store picoseconds and use similar SCAL= E >>>>>> macros we get to 1THz. >>>>>> >>>>>> Regardless the unit chosen, as long it is integer, we can migrate it= . >>>>>> If can migrate the period, we don't need to migrate the frequency. >>>>>> We can then use the float type in with the timer API to pass frequen= cies >>>>>> (which in the modeled hardware are ratios, likely not integers). >>>>>> >>>>>> So we could use set_freq(100e6 / 3), set_freq(40e6 / 5.5) directly. >>>>>> >>>>>>> Regarding the clock, I don't see any strong obstacle to switch >>>>>>> internally to a period based value. >>>>>>> The only things we have to choose is how to represent a disabled cl= ock. >>>>>>> Since putting a "0" period to a ptimer will disable the timer in >>>>>>> ptimer_reload(). We can choose that (and it's a good value because = we >>>>>>> can multiply or divide it, it stays the same). >>>>>>> >>>>>>> We could use the same representation as a ptimer. But if we don't k= eep a >>>>>>> C number representation, then computation of frequencies/periods wi= ll be >>>>>>> complicated at best and error prone. >>>>>>> >>>>>>> =C2=A0From that point of view, if we could stick to a 64bits int= eger (or >>>>>>> floating point number) it would be great. Can we use a sub nanoseco= nd >>>>>>> unit that fit our needs ? >>>>>>> >>>>>>> I did some test with a unit of 2^-32 of nanoseconds on 64bits (is t= hat >>>>>>> the unit of the ptimer fractional part ?) and if I'm not mistaken >>>>>>> + we have a frequency range from ~0.2Hz up to 10^18Hz >>>>>>> + the resolution is decreasing with the frequency (but at 100Mhz we= have >>>>>>> a ~2.3mHz resolution, at 1GHz it's ~0.23Hz and at 10GHz ~23Hz >>>>>>> resolution). We hit 1Hz resolution around 2GHz. >>>>>>> >>>>>>> So it sounds to me we have largely enough resolution to model clock= s in >>>>>>> the range of frequencies we will have to handle. What do you think = ? >>>>>> >>>>>> Back to your series, I wonder why you want to store the frequency in >>>>>> ClockIn. ClockIn shouldn't be aware at what frequency it is clocked. >>>>>> What matters is ClockOut, and each device exposing ClockOuts has a >>>>>> (migrated) state of the output frequencies (rather in fields, or enc= oded >>>>>> in registers). Once migrated, after the state is loaded back into th= e >>>>>> device, we call post_load(). Isn't it a good place to call >>>>>> clock_set_frequency(ClockOut[]) which will correctly set each ClockI= n >>>>>> frequency. >>>>>> >>>>>> IOW I don't think ClockIn/ClockOut require to migrate a frequency fi= eld. >>>>>> >>>>> >>>>> I agree it is more logical to store the frequency in clock out. But, >>>>> regarding migration constraints, we have no choice I think because a >>>>> device cannot rely on values that are migrated by another device for >>>>> restoring its state. (when I checked, I add the impression that >>>>> post_load()s are called on a per device migration basis not all at th= e >>>>> end of migration). >>>> >>>> Cc'ing David to clear that out. >>> >>> >>> That's pretty much right; the 'post_load' is called on a structure at t= he end >>> of loading the data for that structure. >>> >>> You can do things at the end of migration; one way is to register a >>> vm change state handler (search for qemu_add_vm_change_state_handler) >>> and that means you get a kick when the VM starts running or a timer set >>> in virtual time (not wall clock time because that becomes sensitive >>> to the speed of the host). >>> >>> Somewhere ^^^ it says we can't migrate fp values; I'm not sure that's >>> true; we've got a VMSTATE_FLOAT64 macro but I don't see it's used >>> anywhere. >> >> OK, Cc'ing Alex & Richard now, because I guess remember a discussion abo= ut >> "we can not migrate floats because this is a architectural implementatio= n, >> so cross-architecture migration is likely to fail". But I can't find tra= ce >> of a such discussion on the list or IRC logs. >> Maybe this was instead about whether we can use the host FPU registers. >=20 > We have to be careful when migrating the FP registers within a CPU, > since they can have crazy values that are not valid/weird corners of > standard FP encodings (e.g. if the guest just uses the FP registers as > a spare 64bit register - which is perfectly valid on some > architectures). However, migrating an actual floating point > real world measurement should be fine. I'm assuming we can rely on > 64 bit IEEE FP format on the wire being portable. Understood, thanks for clearing this out! Side note, we don't do cross-arch migration testing, but we talked about=20 having a 'different QEMU version' migration test. When we get a such=20 test setup, it shouldn't be too difficult to evolve to some cross-arch=20 migration test. >> I hope I'm wrong and confuse, this is a great news for me to know we >> can migrate floats! >> >>> Dave >>> >>>>> So we could store the frequency in clock out and migrate things there= . >>>>> But since we have no way to ensure all clock out states are migrated >>>>> before some device fetch a ClockIn: we'll have to say "don't fetch on= e >>>>> of your ClockIn frequency during migration and migrate the value >>>>> yourself if you need it", pretty much like gpios. >>>>> >>>>> So we will probably migrate all ClockOut and almost all ClockIn. >>>>> >>>>> It would nice if we had a way to ensure clocks are migrated before >>>>> devices try to use them. But I don't think this is possible. >>>>> >>>>> -- >>>>> Damien >>>>> >>>> >>> -- >>> Dr. David Alan Gilbert / dgilbert@redhat.com / Manchester, UK >>> >> > -- > Dr. David Alan Gilbert / dgilbert@redhat.com / Manchester, UK >=20 From MAILER-DAEMON Thu Dec 05 08:39:34 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1icrLw-0007ka-VM for mharc-qemu-arm@gnu.org; Thu, 05 Dec 2019 08:39:34 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:48793) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1icrLh-0007i4-Ui for qemu-arm@nongnu.org; Thu, 05 Dec 2019 08:39:20 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1icrLg-0004TD-Eh for qemu-arm@nongnu.org; Thu, 05 Dec 2019 08:39:17 -0500 Received: from us-smtp-delivery-1.mimecast.com ([205.139.110.120]:31976 helo=us-smtp-1.mimecast.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1icrLd-0004Pu-4J for qemu-arm@nongnu.org; Thu, 05 Dec 2019 08:39:13 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1575553150; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=hnhb/x6YaZwfbYwlyRlda7171y0HPcU5qK2g5bnRUHs=; b=HV66kXuStetuAOJKDAWC5J25aq+52xIA7o9LJKwmjZYRVw6H80MmvmIgnBqPueQZ/u6qFZ z/0cXKIZFJBuTmnvKCAqULunXONc6vmcpbVxpy5mGnh/8G0NsAeL2klQXKcSe8cC3rJyA8 mY/KRgMIkamjdIu4Qgj/o3A/P22H8H0= Received: from mimecast-mx01.redhat.com (mimecast-mx01.redhat.com [209.132.183.4]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-103-In8rOFh3PGWTvk4no7Xklw-1; Thu, 05 Dec 2019 07:37:20 -0500 Received: from smtp.corp.redhat.com (int-mx06.intmail.prod.int.phx2.redhat.com [10.5.11.16]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx01.redhat.com (Postfix) with ESMTPS id 247F5100; Thu, 5 Dec 2019 12:37:14 +0000 (UTC) Received: from blackfin.pond.sub.org (ovpn-116-134.ams2.redhat.com [10.36.116.134]) by smtp.corp.redhat.com (Postfix) with ESMTPS id 59B435C1B5; Thu, 5 Dec 2019 12:36:42 +0000 (UTC) Received: by blackfin.pond.sub.org (Postfix, from userid 1000) id BB0531138606; Thu, 5 Dec 2019 13:36:40 +0100 (CET) From: Markus Armbruster To: Vladimir Sementsov-Ogievskiy Cc: Markus Armbruster , Ronnie Sahlberg , Jeff Cody , Jan Kiszka , Alberto Garcia , Hailiang Zhang , "qemu-block\@nongnu.org" , Aleksandar Rikalo , Halil Pasic , =?utf-8?Q?Herv=C3=A9?= Poussineau , Anthony Perard , Samuel Thibault , Laszlo Ersek , Jason Wang , Laurent Vivier , Eduardo Habkost , Xie Changlong , Peter Lieven , "Dr. David Alan Gilbert" , Beniamino Galvani , Eric Auger , Alex Williamson , Stefan Hajnoczi , John Snow , Richard Henderson , Kevin Wolf , Andrew Jeffery , Chris Wulff , Subbaraya Sundeep , Michael Walle , "qemu-ppc\@nongnu.org" , Bastian Koppelmann , Igor Mammedov , Fam Zheng , Peter Maydell , "sheepdog\@lists.wpkg.org" , Matthew Rosato , David Hildenbrand , Palmer Dabbelt , Eric Farman , Max Filippov , Hannes Reinecke , Stefano Stabellini , "Gonglei \(Arei\)" , Liu Yuan , Artyom Tarasenko , Thomas Huth , Amit Shah , Stefan Weil , Greg Kurz , Yuval Shaia , "qemu-s390x\@nongnu.org" , "qemu-arm\@nongnu.org" , Peter Chubb , =?utf-8?Q?C=C3=A9dric?= Le Goater , Stafford Horne , "qemu-riscv\@nongnu.org" , Cornelia Huck , Aleksandar Markovic , Aurelien Jarno , Paul Burton , Sagar Karandikar , Paul Durrant , Anthony Green , Gerd Hoffmann , "Edgar E. Iglesias" , Guan Xuetao , Ari Sundholm , Juan Quintela , Michael Roth , Christian Borntraeger , Joel Stanley , Jason Dillaman , Antony Pavlov , "xen-devel\@lists.xenproject.org" , "integration\@gluster.org" , Philippe =?utf-8?Q?Mathieu-Daud=C3=A9?= , "Richard W.M. Jones" , Andrew Baumann , Max Reitz , Denis Lunev , "Michael S. Tsirkin" , Mark Cave-Ayland , "qemu-devel\@nongnu.org" , Vincenzo Maffione , Marek Vasut , =?utf-8?Q?Marc-Andr=C3=A9?= Lureau , Alistair Francis , Pavel Dovgalyuk , Giuseppe Lettieri , Luigi Rizzo , David Gibson , Tony Krowiak , Daniel P. =?utf-8?Q?Berrang=C3=A9?= , Xiao Guangrong , Pierre Morel , Wen Congyang , Jean-Christophe Dubois , Paolo Bonzini , Stefan Berger Subject: Re: [RFC v5 024/126] error: auto propagated local_err References: <20191011160552.22907-1-vsementsov@virtuozzo.com> <20191011160552.22907-25-vsementsov@virtuozzo.com> <87muc8p24w.fsf@dusky.pond.sub.org> <55393c08-5bda-8042-1a95-f350b3781d99@virtuozzo.com> Date: Thu, 05 Dec 2019 13:36:40 +0100 In-Reply-To: <55393c08-5bda-8042-1a95-f350b3781d99@virtuozzo.com> (Vladimir Sementsov-Ogievskiy's message of "Thu, 5 Dec 2019 09:38:49 +0000") Message-ID: <87d0d3c5k7.fsf@dusky.pond.sub.org> User-Agent: Gnus/5.13 (Gnus v5.13) Emacs/26.2 (gnu/linux) MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.79 on 10.5.11.16 X-MC-Unique: In8rOFh3PGWTvk4no7Xklw-1 X-Mimecast-Spam-Score: 0 Content-Type: text/plain Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 205.139.110.120 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 05 Dec 2019 13:39:23 -0000 Vladimir Sementsov-Ogievskiy writes: > 04.12.2019 17:59, Markus Armbruster wrote: >> Vladimir Sementsov-Ogievskiy writes: >>=20 >>> Here is introduced ERRP_AUTO_PROPAGATE macro, to be used at start of >>> functions with errp OUT parameter. >>> >>> It has three goals: >>> >>> 1. Fix issue with error_fatal & error_prepend/error_append_hint: user >>> can't see this additional information, because exit() happens in >>> error_setg earlier than information is added. [Reported by Greg Kurz] >>> >>> 2. Fix issue with error_abort & error_propagate: when we wrap >>> error_abort by local_err+error_propagate, resulting coredump will >>> refer to error_propagate and not to the place where error happened. >>=20 >> I get what you mean, but I have plenty of context. >>=20 >>> (the macro itself doesn't fix the issue, but it allows to [3.] drop all >>> local_err+error_propagate pattern, which will definitely fix the issue) >>=20 >> The parenthesis is not part of the goal. >>=20 >>> [Reported by Kevin Wolf] >>> >>> 3. Drop local_err+error_propagate pattern, which is used to workaround >>> void functions with errp parameter, when caller wants to know resulting >>> status. (Note: actually these functions could be merely updated to >>> return int error code). >>> >>> To achieve these goals, we need to add invocation of the macro at start >>> of functions, which needs error_prepend/error_append_hint (1.); add >>> invocation of the macro at start of functions which do >>> local_err+error_propagate scenario the check errors, drop local errors >>> from them and just use *errp instead (2., 3.). >>=20 >> The paragraph talks about two cases: 1. and 2.+3.=20 > > Hmm, I don't think so.. 1. and 2. are issues. 3. is a refactoring.. We ju= st > fix achieve 2 and 3 by one action. > >> Makes me think we >> want two paragraphs, each illustrated with an example. >>=20 >> What about you provide the examples, and then I try to polish the prose? > > 1: error_fatal problem > > Assume the following code flow: > > int f1(errp) { > ... > ret =3D f2(errp); > if (ret < 0) { > error_append_hint(errp, "very useful hint"); > return ret; > } > ... > } > > Now, if we call f1 with &error_fatal argument and f2 fails, the program > will exit immediately inside f2, when setting the errp. User will not > see the hint. > > So, in this case we should use local_err. How does this example look after the transformation? > 2: error_abort problem > > Now, consider functions without return value. We normally use local_err > variable to catch failures: > > void f1(errp) { > Error *local_err =3D NULL; > ... > f2(&local_err); > if (local_err) { > error_propagate(errp, local_err); > return; > } > ... > } > > Now, if we call f2 with &error_abort and f2 fails, the stack in resulting > crash dump will point to error_propagate, not to the failure point in f2, > which complicates debugging. > > So, we should never wrap error_abort by local_err. Likewise. > > =3D=3D=3D > > Our solution: > > - Fixes [1.], adding invocation of new macro into functions with error_ap= pen_hint/error_prepend, > New macro will wrap error_fatal. > - Fixes [2.], by switching from hand-written local_err to smart macro, wh= ich never > wraps error_abort. > - Handles [3.], by switching to macro, which is less code > - Additionally, macro doesn't wrap normal non-zero errp, to avoid extra p= ropagations > (in fact, error_propagate is called, but returns immediately on first = if (!local_err)) From MAILER-DAEMON Thu Dec 05 09:06:29 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1icrm1-0008Qh-Hg for mharc-qemu-arm@gnu.org; Thu, 05 Dec 2019 09:06:29 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:55547) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1icrlw-0008Ko-HY for qemu-arm@nongnu.org; Thu, 05 Dec 2019 09:06:25 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1icrlv-0000WR-8D for qemu-arm@nongnu.org; Thu, 05 Dec 2019 09:06:24 -0500 Received: from us-smtp-delivery-1.mimecast.com ([207.211.31.120]:59926 helo=us-smtp-1.mimecast.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1icrlv-0000T8-30 for qemu-arm@nongnu.org; Thu, 05 Dec 2019 09:06:23 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1575554782; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=NLRko2/oQTzK9BJwSE/ikxWjurLXgr2kyfOXgtePXp0=; b=Yy4eDk86vfviu2XvuEQpRqAU5CN8lyc2NQJj5BnBPAM0B1TGsmCji30JO1A6tIA6haHRX2 H2xY+61U0lPQtvC8KaRkclmuLy7ueCiNgJxRuE+t/XEdu5GHQIIxRrA+SOqv2qqVSgcfHS gCnUZ/L6AzE2z4BY5r64UuFMv9EDB+c= Received: from mimecast-mx01.redhat.com (mimecast-mx01.redhat.com [209.132.183.4]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-315-Rvc7Il-UOk2M4BUmu0_qfQ-1; Thu, 05 Dec 2019 09:06:19 -0500 Received: from smtp.corp.redhat.com (int-mx05.intmail.prod.int.phx2.redhat.com [10.5.11.15]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx01.redhat.com (Postfix) with ESMTPS id 5EBC6186E658; Thu, 5 Dec 2019 14:06:17 +0000 (UTC) Received: from [10.72.12.127] (ovpn-12-127.pek2.redhat.com [10.72.12.127]) by smtp.corp.redhat.com (Postfix) with ESMTP id 737C55D6A5; Thu, 5 Dec 2019 14:06:11 +0000 (UTC) Subject: Re: [PATCH] net/imx_fec: Updating the IMX_FEC IP to support loopback mode. To: Peter Maydell Cc: =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= , "qemu-devel@nongnu.org" , "aa1ronham@gmail.com" , "jcd@tribudubois.net" , "qemu-arm@nongnu.org" , "Wasim, Bilal" , "bilalwasim676@gmail.com" , "linux@roeck-us.net" References: <20191129150508.24404-1-bilalwasim676@gmail.com> <8c956ae31e8f44a2b831a5030b2448b4@SVR-IES-MBX-03.mgc.mentorg.com> From: Jason Wang Message-ID: <4d9b3cb3-db73-5a58-c32c-594984508a68@redhat.com> Date: Thu, 5 Dec 2019 22:06:09 +0800 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101 Thunderbird/60.8.0 MIME-Version: 1.0 In-Reply-To: Content-Language: en-US X-Scanned-By: MIMEDefang 2.79 on 10.5.11.15 X-MC-Unique: Rvc7Il-UOk2M4BUmu0_qfQ-1 X-Mimecast-Spam-Score: 0 Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 207.211.31.120 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 05 Dec 2019 14:06:27 -0000 On 2019/12/4 =E4=B8=8B=E5=8D=8811:11, Peter Maydell wrote: > On Wed, 4 Dec 2019 at 02:15, Jason Wang wrote: >> On 2019/11/30 =E4=B8=8A=E5=8D=8812:04, Philippe Mathieu-Daud=C3=A9 wrote= : >>> On Fri, Nov 29, 2019 at 4:59 PM Wasim, Bilal w= rote: >>>> Thanks for the pointers philippe.. Is the patch okay to be merged with= out it or do I need to do a re-submission with the updated username ? >>> If there are no review comments on your patch, I think the maintainer >>> taking your patch can fix this details directly, no need to resend. >>> >>>> -----Original Message----- >>>> From: Philippe Mathieu-Daud=C3=A9 [mailto:philmd@redhat.com] >>>> Sent: Friday, November 29, 2019 8:38 PM >>>> To:bilalwasim676@gmail.com;qemu-devel@nongnu.org >>>> Cc:peter.maydell@linaro.org;aa1ronham@gmail.com;jcd@tribudubois.net;qe= mu-arm@nongnu.org; Wasim, Bilal;linux@roeck-us.net;= Jason Wang >>>> Subject: Re: [PATCH] net/imx_fec: Updating the IMX_FEC IP to support l= oopback mode. >>>> >>>> Hi Bilal, >>>> >>>> Cc'ing Jason, the maintainer of network devices. >>>> >>>> On 11/29/19 4:05 PM,bilalwasim676@gmail.com wrote: >>>>> From: bwasim >>>> Your git setup misses your 'user.name', you could fix it running: >>>> >>>> git config user.name "Bilal Wasim" >>>> >>>> (eventually with the --global option). >>>> >>>> The patch looks good otherwise. >>>> >>>> Thanks! >> Applied with the fix for user.name. > Could you fix up the non-standard block comment formatting too? > > thanks > -- PMM > Yes, fixed. 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Tsirkin" , Mark Cave-Ayland , "qemu-devel@nongnu.org" , Vincenzo Maffione , Marek Vasut , =?utf-8?B?TWFyYy1BbmRyw6kgTHVyZWF1?= , Alistair Francis , Pavel Dovgalyuk , Giuseppe Lettieri , Luigi Rizzo , David Gibson , Tony Krowiak , =?utf-8?B?RGFuaWVsIFAuIEJlcnJhbmfDqQ==?= , Xiao Guangrong , Pierre Morel , Wen Congyang , Jean-Christophe Dubois , Paolo Bonzini , Stefan Berger Subject: Re: [RFC v5 024/126] error: auto propagated local_err Thread-Topic: [RFC v5 024/126] error: auto propagated local_err Thread-Index: AQHVgE3c5dwPNEl0z0OyUhbNfTU1EqeqZpzagAFqo4D///+mMYAAJ34A Date: Thu, 5 Dec 2019 14:58:53 +0000 Message-ID: References: <20191011160552.22907-1-vsementsov@virtuozzo.com> <20191011160552.22907-25-vsementsov@virtuozzo.com> <87muc8p24w.fsf@dusky.pond.sub.org> <55393c08-5bda-8042-1a95-f350b3781d99@virtuozzo.com> <87d0d3c5k7.fsf@dusky.pond.sub.org> In-Reply-To: <87d0d3c5k7.fsf@dusky.pond.sub.org> Accept-Language: ru-RU, en-US Content-Language: en-US X-MS-Has-Attach: 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SMTP id s126mr7442804oih.48.1575562340754; Thu, 05 Dec 2019 08:12:20 -0800 (PST) MIME-Version: 1.0 References: <20191011134744.2477-1-richard.henderson@linaro.org> <20191011134744.2477-11-richard.henderson@linaro.org> In-Reply-To: <20191011134744.2477-11-richard.henderson@linaro.org> From: Peter Maydell Date: Thu, 5 Dec 2019 16:12:09 +0000 Message-ID: Subject: Re: [PATCH v5 10/22] target/arm: Define arm_cpu_do_unaligned_access for CONFIG_USER_ONLY To: Richard Henderson Cc: QEMU Developers , qemu-arm Content-Type: text/plain; charset="UTF-8" X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::241 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 05 Dec 2019 16:12:27 -0000 On Fri, 11 Oct 2019 at 14:50, Richard Henderson wrote: > > We will need this to raise unaligned exceptions from user mode. > > Signed-off-by: Richard Henderson > --- > target/arm/tlb_helper.c | 3 +-- > 1 file changed, 1 insertion(+), 2 deletions(-) > > diff --git a/target/arm/tlb_helper.c b/target/arm/tlb_helper.c > index 5feb312941..29b92a1149 100644 > --- a/target/arm/tlb_helper.c > +++ b/target/arm/tlb_helper.c > @@ -10,8 +10,6 @@ > #include "internals.h" > #include "exec/exec-all.h" > > -#if !defined(CONFIG_USER_ONLY) > - > static inline uint32_t merge_syn_data_abort(uint32_t template_syn, > unsigned int target_el, > bool same_el, bool ea, > @@ -122,6 +120,7 @@ void arm_cpu_do_unaligned_access(CPUState *cs, vaddr vaddr, > arm_deliver_fault(cpu, vaddr, access_type, mmu_idx, &fi); > } > > +#ifndef CONFIG_USER_ONLY > /* > * arm_cpu_do_transaction_failed: handle a memory system error response > * (eg "no device/memory present at address") by raising an external abort > -- > 2.17.1 Isn't this just enabling compilation of the softmmu arm_cpu_do_unaligned_access() on linux-user? That codepath does a lot of softmmu stuff including calling arm_deliver_fault() (which implicitly does somewhat more looking at EL1 system register state than we necessarily have set up correctly for the user-mode code). For arm_cpu_tlb_fill() which handles prefetch/data aborts we just have a separate much simpler codepath for CONFIG_USER_ONLY which doesn't call arm_deliver_fault(). I think being consistent here about how we handle the CONFIG_USER_ONLY case would help avoid having a codepath that isn't very well tested because it's only used in the odd special case of unaligned-address exceptions. thanks -- PMM From MAILER-DAEMON Thu Dec 05 11:37:01 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1icu7h-0004Rs-7c for mharc-qemu-arm@gnu.org; Thu, 05 Dec 2019 11:37:01 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:46783) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1icu7e-0004Me-BK for qemu-arm@nongnu.org; Thu, 05 Dec 2019 11:36:59 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1icu7c-0002Rh-Lg for qemu-arm@nongnu.org; Thu, 05 Dec 2019 11:36:58 -0500 Received: from mail-eopbgr80125.outbound.protection.outlook.com ([40.107.8.125]:62784 helo=EUR04-VI1-obe.outbound.protection.outlook.com) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1icu7R-0001QU-9S; Thu, 05 Dec 2019 11:36:46 -0500 ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=fr4ykQT3Ewm21lon3aUQPxSwSL/JLevYNelkzsFKTG4Y9mHz3lenYYAstffgZ0XvEWLG8C68hdl1OUTFIOOn1wEeRZGj6byBiLIX4AhW+TV+EmbD0OUtf5mWkdrNrJsDyflV7vPgxORQtKUirTtqZ1HdzbrPhYfA8jAhPF2w//ArWuq3UwS2xrc8BIiNLL1TZwwZg6vSZt3k09LHK4kMo4773HHqTOaWaNKx8+Hlug+xOs+MzmTF0qqK4iS5PNdpMoD+29Mr9vXclRUfysQhQl6B/TuoMy841W/Hhtndvy85xC4AonEqbpgL/xsv0+VtXrNQ7qy1E0dYoIUCFD2f7w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=BYFcZEZvWhTiSAbFQyG3vTsddaFK3yn9mr+VXoBleB4=; b=mys6kURJ5U/S8z9ERRIk8VTzLrAyDpPnsZJVJlNyrbku93kha415V3wrsvxGrNkB+RA2m1cXSqQsRgd1MwuBVSjyuzE6wxJGV5CoUPq6Ot3B6x1UsepDw+PZSQUb0FuUdwxN5QoTt0v7yGuMYcpDnT7FrDDx4YnFYH17AhjxpvCExhJIEelUZwlHvkD3BF3bwoJxqc6wUDQ2RQQjKLsNCGHHx+O0cynyAlbG+kgAaAgohx6wqJNN0O3Ug61bjp1O26ouOTlhdmBd9fceEwaxPXIw8J4WL2s6HxHndSP44mVcAaDEJZeUXqOwoZMNNt+n1IVihMiKJ1EPoxBoi/+2AQ== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=virtuozzo.com; dmarc=pass action=none header.from=virtuozzo.com; dkim=pass header.d=virtuozzo.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=virtuozzo.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=BYFcZEZvWhTiSAbFQyG3vTsddaFK3yn9mr+VXoBleB4=; b=kd7JrIfMeOe9HUIUk1hOGaDSrtkaQUQaXAQ7ZSqZXMf6bPvtl6pXsGEDKPtbm0zRI9y4IuJOCqyw1rpRl+afy6GOTGPdl8RAqnJHFeSB4TLZqXCVzluGz1HdDCwzPuWGC2kJds+ptfcTVJfONYEj0N78n2VjTKzrCLJDV8BT2GE= Received: from AM6PR08MB4423.eurprd08.prod.outlook.com (20.179.7.140) by AM6PR08MB3413.eurprd08.prod.outlook.com (20.177.113.10) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.2495.20; Thu, 5 Dec 2019 16:36:42 +0000 Received: from AM6PR08MB4423.eurprd08.prod.outlook.com ([fe80::11a9:a944:c946:3030]) by AM6PR08MB4423.eurprd08.prod.outlook.com ([fe80::11a9:a944:c946:3030%7]) with mapi id 15.20.2516.014; Thu, 5 Dec 2019 16:36:42 +0000 From: Vladimir Sementsov-Ogievskiy To: Markus Armbruster CC: Stefan Hajnoczi , Jeff Cody , Jan Kiszka , Alberto Garcia , Hailiang Zhang , "qemu-block@nongnu.org" , Aleksandar Rikalo , Halil Pasic , =?utf-8?B?SGVydsOpIFBvdXNzaW5lYXU=?= , Anthony Perard , Samuel Thibault , =?utf-8?B?UGhpbGlwcGUgTWF0aGlldS1EYXVkw6k=?= , Anthony Green , Laurent Vivier , Eduardo Habkost , Xie Changlong , Peter Lieven , "Dr. David Alan Gilbert" , Beniamino Galvani , Eric Auger , Alex Williamson , Ronnie Sahlberg , John Snow , Richard Henderson , Kevin Wolf , Andrew Jeffery , Chris Wulff , Subbaraya Sundeep , Michael Walle , "qemu-ppc@nongnu.org" , Bastian Koppelmann , Igor Mammedov , Fam Zheng , Peter Maydell , "sheepdog@lists.wpkg.org" , Matthew Rosato , David Hildenbrand , Palmer Dabbelt , Eric Farman , Max Filippov , Hannes Reinecke , Stefano Stabellini , "Gonglei (Arei)" , Liu Yuan , Artyom Tarasenko , Thomas Huth , Amit Shah , Stefan Weil , Greg Kurz , Yuval Shaia , "qemu-s390x@nongnu.org" , "qemu-arm@nongnu.org" , Peter Chubb , =?utf-8?B?Q8OpZHJpYyBMZSBHb2F0ZXI=?= , Stafford Horne , "qemu-riscv@nongnu.org" , Cornelia Huck , Aleksandar Markovic , Aurelien Jarno , Paul Burton , Sagar Karandikar , Paul Durrant , Jason Wang , Gerd Hoffmann , "Edgar E. Iglesias" , Guan Xuetao , Ari Sundholm , Juan Quintela , Michael Roth , Christian Borntraeger , Joel Stanley , Jason Dillaman , Antony Pavlov , "xen-devel@lists.xenproject.org" , "integration@gluster.org" , Laszlo Ersek , "Richard W.M. Jones" , Andrew Baumann , Max Reitz , Denis Lunev , "Michael S. Tsirkin" , Mark Cave-Ayland , "qemu-devel@nongnu.org" , Vincenzo Maffione , Marek Vasut , =?utf-8?B?TWFyYy1BbmRyw6kgTHVyZWF1?= , Alistair Francis , Pavel Dovgalyuk , Giuseppe Lettieri , Luigi Rizzo , David Gibson , Tony Krowiak , =?utf-8?B?RGFuaWVsIFAuIEJlcnJhbmfDqQ==?= , Xiao Guangrong , Pierre Morel , Wen Congyang , Jean-Christophe Dubois , Paolo Bonzini , Stefan Berger Subject: Re: [RFC v5 024/126] error: auto propagated local_err Thread-Topic: [RFC v5 024/126] error: auto propagated local_err Thread-Index: AQHVgE3c5dwPNEl0z0OyUhbNfTU1EqeqZpzagAFqo4D///+mMYAAWcgA///pCIA= Date: Thu, 5 Dec 2019 16:36:42 +0000 Message-ID: References: <20191011160552.22907-1-vsementsov@virtuozzo.com> <20191011160552.22907-25-vsementsov@virtuozzo.com> <87muc8p24w.fsf@dusky.pond.sub.org> <55393c08-5bda-8042-1a95-f350b3781d99@virtuozzo.com> <87d0d3c5k7.fsf@dusky.pond.sub.org> In-Reply-To: Accept-Language: ru-RU, en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-clientproxiedby: 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X-Received-From: 2607:f8b0:4864:20::344 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 05 Dec 2019 17:07:33 -0000 On Fri, 11 Oct 2019 at 14:50, Richard Henderson wrote: > > Signed-off-by: Richard Henderson > --- > v2: Split out allocation_tag_mem. Handle atomicity of stores. > v3: Add X[t] input to these insns; require pre-cleaned addresses. > v5: Fix !32-byte aligned operation of st2g. > --- > target/arm/helper-a64.h | 5 ++ > target/arm/mte_helper.c | 154 +++++++++++++++++++++++++++++++++++++ > target/arm/translate-a64.c | 115 +++++++++++++++++++++++++++ > 3 files changed, 274 insertions(+) > > --- a/target/arm/mte_helper.c > +++ b/target/arm/mte_helper.c > @@ -25,8 +25,21 @@ > #include "exec/helper-proto.h" > > > +static uint8_t *allocation_tag_mem(CPUARMState *env, uint64_t ptr, > + bool write, uintptr_t ra) > +{ > + /* Tag storage not implemented. */ > + return NULL; > +} > + > static int get_allocation_tag(CPUARMState *env, uint64_t ptr, uintptr_t ra) > { > + uint8_t *mem = allocation_tag_mem(env, ptr, false, ra); > + > + if (mem) { > + int ofs = extract32(ptr, LOG2_TAG_GRANULE, 1) * 4; > + return extract32(atomic_read(mem), ofs, 4); Can we have a comment somewhere describing what our tag storage looks like? I guess from the code that we're doing it as a byte array where each byte stores 2 4-bit tags (in which order?), but documenting it would be nice. > + } > /* Tag storage not implemented. */ > return -1; > } > +static void do_st2g(CPUARMState *env, uint64_t ptr1, uint64_t xt, > + uintptr_t ra, stg_store1 store1) > +{ > + int el, tag; > + uint64_t ptr2, sctlr; > + uint8_t *mem1, *mem2; > + > + check_tag_aligned(env, ptr1, ra); > + > + el = arm_current_el(env); > + sctlr = arm_sctlr(env, el); > + tag = allocation_tag_from_addr(xt); > + > + /* > + * Trap if accessing an invalid page(s). > + * This takes priority over !allocation_tag_access_enabled. > + */ > + mem1 = allocation_tag_mem(env, ptr1, true, ra); > + > + if (ptr1 & TAG_GRANULE) { > + /* The two stores are unaligned and modify two bytes. */ > + ptr2 = ptr1 + TAG_GRANULE; > + mem2 = allocation_tag_mem(env, ptr2, true, ra); > + > + /* Store if page supports tags and access is enabled. */ > + if ((mem1 || mem2) && allocation_tag_access_enabled(env, el, sctlr)) { > + if (mem1) { > + store1(ptr1, mem1, tag); > + } > + if (mem2) { > + store1(ptr2, mem2, tag); > + } > + } > + } else { > + /* The two stores are aligned 32, and modify one byte. */ Not sure what the '32' means here? > + if (mem1 && allocation_tag_access_enabled(env, el, sctlr)) { > + tag |= tag << 4; > + atomic_set(mem1, tag); > + } > + } > +} > diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c > index cf341c98d3..c17b36ebb2 100644 > --- a/target/arm/translate-a64.c > +++ b/target/arm/translate-a64.c > @@ -3559,6 +3559,118 @@ static void disas_ldst_single_struct(DisasContext *s, uint32_t insn) > } > } > > +/* > + * Load/Store memory tags > + * > + * 31 30 29 24 22 21 12 10 5 0 > + * +-----+-------------+-----+---+------+-----+------+------+ > + * | 1 1 | 0 1 1 0 0 1 | op1 | 1 | imm9 | op2 | Rn | Rt | > + * +-----+-------------+-----+---+------+-----+------+------+ > + */ > +static void disas_ldst_tag(DisasContext *s, uint32_t insn) > +{ > + int rt = extract32(insn, 0, 5); > + int rn = extract32(insn, 5, 5); > + uint64_t offset = sextract64(insn, 12, 9) << LOG2_TAG_GRANULE; > + int op2 = extract32(insn, 10, 3); Typo ? op2 is only 2 bits, not 3. > + int op1 = extract32(insn, 22, 2); The Arm ARM calls this field 'opc', fwiw. > + bool is_load = false, is_pair = false, is_zero = false; > + int index = 0; > + TCGv_i64 dirty_addr, clean_addr, tcg_rt; > + > + if ((insn & 0xff200000) != 0xd9200000 > + || !dc_isar_feature(aa64_mte_insn_reg, s)) { > + goto do_unallocated; > + } Bits 28:24 are already checked by the decode that got us here. I did wonder about maybe doing the decode of [31:30] and [21] in the caller (which would match the structure of the decode tables in the manual), but we do the same sort of thing for bit [31] in disas_ldst_multiple_struct() and disas_ldst_single_struct(), so this is fine. Not all the insns in this encoding group are present for the mte_insn_reg cut-down implementation: LDGM, STGM and STZGM should UNDEF unless we have full-fat MTE. We haven't added any of those in this patch, but it might affect how you want to structure the conditional for doing the feature bit test. (Looking ahead, patch 13 which adds those insns doesn't update the feature bit test.) > + > + switch (op1) { > + case 0: /* STG */ > + if (op2 != 0) { > + /* STG */ > + index = op2 - 2; What does 'index' represent? It looks from the rest of the code like it's some sort of tristate between 'preindex', 'postindex' and 'not indexed'; if so a comment explaining what the valid values and meanings are would be helpful. Alternatively, follow the approach of disas_ldst_reg_imm9() and just have separate 'post_index' and 'writeback' bools. > + break; > + } > + goto do_unallocated; > + case 1: > + if (op2 != 0) { > + /* STZG */ > + is_zero = true; > + index = op2 - 2; > + } else { > + /* LDG */ > + is_load = true; > + } > + break; > + case 2: > + if (op2 != 0) { > + /* ST2G */ > + is_pair = true; > + index = op2 - 2; > + break; > + } > + goto do_unallocated; > + case 3: > + if (op2 != 0) { > + /* STZ2G */ > + is_pair = is_zero = true; > + index = op2 - 2; > + break; > + } > + goto do_unallocated; > + > + default: > + do_unallocated: > + unallocated_encoding(s); > + return; > + } Should there be a if (rn == 31) { gen_check_sp_alignment(s); } here? > + > + dirty_addr = read_cpu_reg_sp(s, rn, true); > + if (index <= 0) { > + /* pre-index or signed offset */ > + tcg_gen_addi_i64(dirty_addr, dirty_addr, offset); > + } > + > + clean_addr = clean_data_tbi(s, dirty_addr, false); > + tcg_rt = cpu_reg(s, rt); I think this is only correct for LDG, where the Rt field is 'specifies the Xt register to use'; for STG and ST2G it's an '' form where 31 means "use SP" and you want cpu_reg_sp() for those. > + > + if (is_load) { > + gen_helper_ldg(tcg_rt, cpu_env, clean_addr, tcg_rt); > + } else if (tb_cflags(s->base.tb) & CF_PARALLEL) { > + if (is_pair) { > + gen_helper_st2g_parallel(cpu_env, clean_addr, tcg_rt); > + } else { > + gen_helper_stg_parallel(cpu_env, clean_addr, tcg_rt); > + } > + } else { > + if (is_pair) { > + gen_helper_st2g(cpu_env, clean_addr, tcg_rt); > + } else { > + gen_helper_stg(cpu_env, clean_addr, tcg_rt); > + } > + } > + > + if (is_zero) { > + TCGv_i64 tcg_zero = tcg_const_i64(0); > + int mem_index = get_mem_index(s); > + int i, n = (1 + is_pair) << LOG2_TAG_GRANULE; > + > + for (i = 0; i < n; i += 8) { > + tcg_gen_qemu_st_i64(tcg_zero, clean_addr, mem_index, MO_Q); > + tcg_gen_addi_i64(clean_addr, clean_addr, 8); > + } > + tcg_temp_free_i64(tcg_zero); > + } > + > + if (index != 0) { > + /* pre-index or post-index */ > + if (index > 0) { > + /* post-index */ > + tcg_gen_addi_i64(dirty_addr, dirty_addr, offset); > + } > + tcg_gen_mov_i64(cpu_reg_sp(s, rn), dirty_addr); > + } > +} thanks -- PMM From MAILER-DAEMON Thu Dec 05 12:16:25 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1icujp-0006pN-Au for mharc-qemu-arm@gnu.org; Thu, 05 Dec 2019 12:16:25 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:58279) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1icujZ-0006gK-6d for qemu-arm@nongnu.org; Thu, 05 Dec 2019 12:16:10 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1icujX-0002DD-PK for qemu-arm@nongnu.org; Thu, 05 Dec 2019 12:16:08 -0500 Received: from mail-oi1-x242.google.com ([2607:f8b0:4864:20::242]:32924) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1icujX-00028f-Db for qemu-arm@nongnu.org; Thu, 05 Dec 2019 12:16:07 -0500 Received: by mail-oi1-x242.google.com with SMTP id v140so3476850oie.0 for ; Thu, 05 Dec 2019 09:16:07 -0800 (PST) DKIM-Signature: v=1; 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Thu, 05 Dec 2019 09:16:06 -0800 (PST) MIME-Version: 1.0 References: <20191011134744.2477-1-richard.henderson@linaro.org> <20191011134744.2477-13-richard.henderson@linaro.org> In-Reply-To: <20191011134744.2477-13-richard.henderson@linaro.org> From: Peter Maydell Date: Thu, 5 Dec 2019 17:15:55 +0000 Message-ID: Subject: Re: [PATCH v5 12/22] target/arm: Implement the STGP instruction To: Richard Henderson Cc: QEMU Developers , qemu-arm Content-Type: text/plain; charset="UTF-8" X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::242 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 05 Dec 2019 17:16:11 -0000 On Fri, 11 Oct 2019 at 14:50, Richard Henderson wrote: > > Signed-off-by: Richard Henderson > --- > v3: Handle atomicity, require pre-cleaned address. > --- > target/arm/translate-a64.c | 20 +++++++++++++++++++- > 1 file changed, 19 insertions(+), 1 deletion(-) > > diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c > index c17b36ebb2..4ecb0a2fb7 100644 > --- a/target/arm/translate-a64.c > +++ b/target/arm/translate-a64.c > @@ -2657,7 +2657,7 @@ static void disas_ld_lit(DisasContext *s, uint32_t insn) > * +-----+-------+---+---+-------+---+-------+-------+------+------+ > * > * opc: LDP/STP/LDNP/STNP 00 -> 32 bit, 10 -> 64 bit > - * LDPSW 01 > + * LDPSW/STGP 01 > * LDP/STP/LDNP/STNP (SIMD) 00 -> 32 bit, 01 -> 64 bit, 10 -> 128 bit > * V: 0 -> GPR, 1 -> Vector > * idx: 00 -> signed offset with non-temporal hint, 01 -> post-index, > @@ -2682,6 +2682,7 @@ static void disas_ldst_pair(DisasContext *s, uint32_t insn) > bool is_signed = false; > bool postindex = false; > bool wback = false; > + bool set_tag = false; > > TCGv_i64 clean_addr, dirty_addr; > > @@ -2694,6 +2695,14 @@ static void disas_ldst_pair(DisasContext *s, uint32_t insn) > > if (is_vector) { > size = 2 + opc; > + } else if (opc == 1 && !is_load) { > + /* STGP */ > + if (!dc_isar_feature(aa64_mte_insn_reg, s) || index == 0) { > + unallocated_encoding(s); > + return; > + } > + size = 3; > + set_tag = true; > } else { > size = 2 + extract32(opc, 1, 1); > is_signed = extract32(opc, 0, 1); > @@ -2746,6 +2755,15 @@ static void disas_ldst_pair(DisasContext *s, uint32_t insn) > } > clean_addr = clean_data_tbi(s, dirty_addr, wback || rn != 31); Don't we need to adjust the 'check' argument to clean_data_tbi() here? The pseudocode says STGP doesn't do tag-checking. > > + if (set_tag) { > + TCGv_i64 tcg_rn = cpu_reg_sp(s, rn); > + if (tb_cflags(s->base.tb) & CF_PARALLEL) { > + gen_helper_stg_parallel(cpu_env, clean_addr, tcg_rn); > + } else { > + gen_helper_stg(cpu_env, clean_addr, tcg_rn); > + } > + } > + > if (is_vector) { > if (is_load) { > do_fp_ld(s, rt, clean_addr, size); > -- > 2.17.1 Otherwise Reviewed-by: Peter Maydell thanks -- PMM From MAILER-DAEMON Thu Dec 05 12:32:00 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1icuyu-0008Rz-HZ for mharc-qemu-arm@gnu.org; Thu, 05 Dec 2019 12:32:00 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:54540) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1icuyr-0008RT-Qr for qemu-arm@nongnu.org; Thu, 05 Dec 2019 12:31:59 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1icuyq-0000el-7T for qemu-arm@nongnu.org; Thu, 05 Dec 2019 12:31:57 -0500 Received: from mail-wr1-x442.google.com ([2a00:1450:4864:20::442]:32972) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1icuyp-0000a1-Rq for qemu-arm@nongnu.org; Thu, 05 Dec 2019 12:31:56 -0500 Received: by mail-wr1-x442.google.com with SMTP id b6so4670343wrq.0 for ; Thu, 05 Dec 2019 09:31:55 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=references:user-agent:from:to:cc:subject:in-reply-to:date :message-id:mime-version:content-transfer-encoding; bh=mPR+RnI5ndaYekc/cM5S/YEFXT8srJA+hLrqRZ+HoYE=; b=UiAC6+UU0tvF06T6R+TJWNwzBwI1dT+NTdJvlNtacAeXOMXf1X+Ke3oEfnw/E+BBtl fRgYzEhNcZ4IIF7RKAhMWHIavbnWfi9uaj+MgRAjItHl9Sk2pWb7KGnfthtXBj4pzvgQ p+4ZDcmxI24/g723GlucsIKsU1l/h/dcScKsVJGxNgD7uN5dBMpmr1NguvHHvmPN8u+s q4gYho4fTR6pQyflHOZXcQ2bRKQava6AMNDZBpVTESnu9EshFtNDeGiz6m9A+U2DfSsg hOuKy+sdPSOle03MsMrUVvCQe72RpyCunXP2G6FDbOnw+9fhNBzg5MR+LrSI1/4DS/Hz 1Q6Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:references:user-agent:from:to:cc:subject :in-reply-to:date:message-id:mime-version:content-transfer-encoding; bh=mPR+RnI5ndaYekc/cM5S/YEFXT8srJA+hLrqRZ+HoYE=; b=lVnyFaCqSOaXenQZRVhgNVOyBH+6M17f8r7sAoMdMBFIJQhp+qhsuE4vvsJu66siQT MJ5E4vh4+38uKNbximq/BynDD+26v4PNaPFqilYb37KF/bBKy/8RKGOSImyTxoaNjhsF ek37aPuM9VAIDwso8GJ9Zkyp3uJQD6Rpckmotcf49ewiFPiTjDgKATADkwyGjZsqmUxx cQf7sHl2PEwg5xQGn2VvFLvTdDJACAAfWDdzZOgSfh/lF7qokgvZ6F3tJ4WC4lRSGNTs CkLG+LZZwSCdZz61eRSvLvNQ43kMh/MmbALnYjBZP7G26nmNpE8/t3Mw/QpGRjq1/+9o dYLQ== X-Gm-Message-State: APjAAAUDJj7tu8/7y4m5hqgAIw2uXvzNap3Yejp4cH3dSxNhoZniMlvF j1vD74IuAEHln+dPh7wdmx3h6Q== X-Google-Smtp-Source: APXvYqz3IVXeR/QTDnfjchFAFmxWU7P0m4RwRTQ9x0iiI2pZCIQMZN1kXq8Jmrel9N1V7Mmm+VpGyw== X-Received: by 2002:a05:6000:1044:: with SMTP id c4mr11767622wrx.204.1575567114457; Thu, 05 Dec 2019 09:31:54 -0800 (PST) Received: from zen.linaroharston ([51.148.130.216]) by smtp.gmail.com with ESMTPSA id y10sm515562wmm.3.2019.12.05.09.31.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 05 Dec 2019 09:31:53 -0800 (PST) Received: from zen (localhost [127.0.0.1]) by zen.linaroharston (Postfix) with ESMTP id 5EE511FF87; Thu, 5 Dec 2019 17:31:52 +0000 (GMT) References: <20191130084602.10818-1-alex.bennee@linaro.org> <20191130084602.10818-12-alex.bennee@linaro.org> <9362663d-6452-39aa-2a8d-1cfd853d7faa@linaro.org> User-agent: mu4e 1.3.5; emacs 27.0.50 From: Alex =?utf-8?Q?Benn=C3=A9e?= To: Richard Henderson Cc: qemu-devel@nongnu.org, alan.hayward@arm.com, luis.machado@linaro.org, damien.hedde@greensocs.com, Peter Maydell , "open list:ARM TCG CPUs" Subject: Re: [PATCH v2 11/14] target/arm: default SVE length to 64 bytes for linux-user In-reply-to: <9362663d-6452-39aa-2a8d-1cfd853d7faa@linaro.org> Date: Thu, 05 Dec 2019 17:31:52 +0000 Message-ID: <87o8wm7k6v.fsf@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::442 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 05 Dec 2019 17:31:59 -0000 Richard Henderson writes: > On 11/30/19 8:45 AM, Alex Benn=C3=A9e wrote: >> The Linux kernel chooses the default of 64 bytes for SVE registers on >> the basis that it is the largest size that won't grow the signal >> frame. When debugging larger sizes are also unwieldy in gdb as each >> zreg will take over a page of terminal to display. >>=20 >> The user can of course always specify a larger size with the >> sve-max-vq property on the command line: >>=20 >> -cpu max,sve-max-vq=3D16 >>=20 >> This should not make any difference to SVE enabled software as the SVE >> is of course vector length agnostic. >>=20 >> Signed-off-by: Alex Benn=C3=A9e >> --- >> target/arm/cpu64.c | 3 +++ >> 1 file changed, 3 insertions(+) > > 6 is the largest size that doesn't grow the signal frame. > I imagine 4 was chosen because that's the only real hw atm. > >> + /* Default sve-max-vq to a reasonable numer */ >> + cpu->sve_max_vq =3D 4; > > I also agree that we should match the kernel, but this is not the right w= ay. > Changing max vq is not the same as changing the default vq. > > You should change the value of env->vfp.zcr_el[1] in arm_cpu_reset(), and= the > user can increase the length with prctl(2) as they would be able to on re= al > hardware that would have support for longer vector lengths. No the intention is to default to a lower max VQ because... > Also, I don't think you should mix this up with gdb stuff. it is what we use for sizing the registers for the gdbstub. The other option would be to use the effective zcr_el1 value at the time of the gdbstub connecting but then things will go horribly wrong if the user execute a prctl and widens their size. > > > r~ --=20 Alex Benn=C3=A9e From MAILER-DAEMON Thu Dec 05 12:33:40 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1icv0W-00016c-92 for mharc-qemu-arm@gnu.org; Thu, 05 Dec 2019 12:33:40 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:60993) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1icv0O-00013E-IS for qemu-arm@nongnu.org; Thu, 05 Dec 2019 12:33:34 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1icv0H-0006UB-Vj for qemu-arm@nongnu.org; Thu, 05 Dec 2019 12:33:29 -0500 Received: from us-smtp-1.mimecast.com ([207.211.31.81]:58945) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1icv0G-0006Rb-3Z for qemu-arm@nongnu.org; Thu, 05 Dec 2019 12:33:25 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1575567201; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=SXeZyo48H3SZ9vKNo89jpscEKcAmkJ65SmGcOay8P6g=; b=RM5kEcsHTyKGqFH/bUVeQ/6BF21N4sYuxtXzS+eTI3lGX4lGttc7l0Dfb8jq1BNyj1arxD ueUym+D+NjRmW057UswGMBxm0eSloq2SGlaZrSSJcW2F7hzl14akl+LzBXP1y90QfAQgDB 4lf3whKZYtpLj8TMUoUdh3Xh3g0/J8k= Received: from mimecast-mx01.redhat.com (mimecast-mx01.redhat.com [209.132.183.4]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-1-gkHur7j6PiOysEy_2vMLcg-1; Thu, 05 Dec 2019 12:33:20 -0500 Received: from smtp.corp.redhat.com (int-mx01.intmail.prod.int.phx2.redhat.com [10.5.11.11]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx01.redhat.com (Postfix) with ESMTPS id 7409E800D41; Thu, 5 Dec 2019 17:33:16 +0000 (UTC) Received: from [10.3.116.171] (ovpn-116-171.phx2.redhat.com [10.3.116.171]) by smtp.corp.redhat.com (Postfix) with ESMTPS id 885356012D; Thu, 5 Dec 2019 17:32:42 +0000 (UTC) Subject: Re: [RFC v5 024/126] error: auto propagated local_err To: Vladimir Sementsov-Ogievskiy , Markus Armbruster Cc: Stefan Hajnoczi , Jan Kiszka , Hailiang Zhang , "qemu-block@nongnu.org" , Aleksandar Rikalo , Halil Pasic , =?UTF-8?Q?Herv=c3=a9_Poussineau?= , Anthony Perard , Samuel Thibault , =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= , Anthony Green , Laurent Vivier , Eduardo Habkost , Xie Changlong , Peter Lieven , "Dr. David Alan Gilbert" , Beniamino Galvani , Eric Auger , Alex Williamson , Ronnie Sahlberg , Richard Henderson , Kevin Wolf , Andrew Jeffery , Chris Wulff , Subbaraya Sundeep , Michael Walle , "qemu-ppc@nongnu.org" , Bastian Koppelmann , Igor Mammedov , Fam Zheng , Peter Maydell , "sheepdog@lists.wpkg.org" , Matthew Rosato , David Hildenbrand , Palmer Dabbelt , Max Filippov , Hannes Reinecke , Stefano Stabellini , "Gonglei (Arei)" , Liu Yuan , Artyom Tarasenko , Thomas Huth , Amit Shah , Stefan Weil , Greg Kurz , Yuval Shaia , "qemu-s390x@nongnu.org" , "qemu-arm@nongnu.org" , Peter Chubb , =?UTF-8?Q?C=c3=a9dric_Le_Goater?= , Stafford Horne , "qemu-riscv@nongnu.org" , Cornelia Huck , Aleksandar Markovic , Aurelien Jarno , Paul Burton , Sagar Karandikar , Paul Durrant , Jason Wang , Gerd Hoffmann , "Edgar E. Iglesias" , Guan Xuetao , Juan Quintela , Michael Roth , Christian Borntraeger , Joel Stanley , Antony Pavlov , "xen-devel@lists.xenproject.org" , "integration@gluster.org" , Laszlo Ersek , Andrew Baumann , Max Reitz , Denis Lunev , "Michael S. Tsirkin" , Mark Cave-Ayland , "qemu-devel@nongnu.org" , Vincenzo Maffione , Marek Vasut , =?UTF-8?Q?Marc-Andr=c3=a9_Lureau?= , Alistair Francis , Pavel Dovgalyuk , Giuseppe Lettieri , Luigi Rizzo , David Gibson , Tony Krowiak , =?UTF-8?Q?Daniel_P=2e_Berrang=c3=a9?= , Xiao Guangrong , Pierre Morel , Wen Congyang , Jean-Christophe Dubois , Paolo Bonzini , Stefan Berger References: <20191011160552.22907-1-vsementsov@virtuozzo.com> <20191011160552.22907-25-vsementsov@virtuozzo.com> <87muc8p24w.fsf@dusky.pond.sub.org> <55393c08-5bda-8042-1a95-f350b3781d99@virtuozzo.com> <87d0d3c5k7.fsf@dusky.pond.sub.org> From: Eric Blake Organization: Red Hat, Inc. Message-ID: <54c19813-8a10-1607-6fdc-cd7d930ecac7@redhat.com> Date: Thu, 5 Dec 2019 11:32:41 -0600 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.2.2 MIME-Version: 1.0 In-Reply-To: Content-Language: en-US X-Scanned-By: MIMEDefang 2.79 on 10.5.11.11 X-MC-Unique: gkHur7j6PiOysEy_2vMLcg-1 X-Mimecast-Spam-Score: 0 Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 7bit X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 207.211.31.81 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 05 Dec 2019 17:33:34 -0000 On 12/5/19 8:58 AM, Vladimir Sementsov-Ogievskiy wrote: >>>> What about you provide the examples, and then I try to polish the prose? >>> >>> 1: error_fatal problem >>> >>> Assume the following code flow: >>> >>> int f1(errp) { >>> ... >>> ret = f2(errp); >>> if (ret < 0) { >>> error_append_hint(errp, "very useful hint"); >>> return ret; >>> } >>> ... >>> } >>> >>> Now, if we call f1 with &error_fatal argument and f2 fails, the program >>> will exit immediately inside f2, when setting the errp. User will not >>> see the hint. >>> >>> So, in this case we should use local_err. >> >> How does this example look after the transformation? Without ERRP_AUTO_PROPAGATE(), the transformation is a lot of boilerplate: int f1(errp) { Error *err = NULL; ret = f2(&err); if (ret < 0) { error_append_hint(&err, "very useful hint"); error_propagate(errp, err); return ret; } } what's worse, that boilerplate to solve problem 1 turns out to be... > > Good point. > > int f1(errp) { > ERRP_AUTO_PROPAGATE(); > ... > ret = f2(errp); > if (ret < 0) { > error_append_hint(errp, "very useful hint"); > return ret; > } > ... > } > > - nothing changed, only add macro at start. But now errp is safe, if it was > error_fatal it is wrapped by local error, and will only call exit on automatic > propagation on f1 finish. > >> >>> 2: error_abort problem >>> >>> Now, consider functions without return value. We normally use local_err >>> variable to catch failures: >>> >>> void f1(errp) { >>> Error *local_err = NULL; >>> ... >>> f2(&local_err); >>> if (local_err) { >>> error_propagate(errp, local_err); >>> return; >>> } >>> ... >>> } the very same code as the cause of problem 2. >>> >>> Now, if we call f2 with &error_abort and f2 fails, the stack in resulting >>> crash dump will point to error_propagate, not to the failure point in f2, >>> which complicates debugging. >>> >>> So, we should never wrap error_abort by local_err. >> >> Likewise. > > And here: > > void f1(errp) { > ERRP_AUTO_PROPAGATE(); > ... > f2(errp); > if (*errp) { > return; > } > ... > > - if errp was NULL, it is wrapped, so dereferencing errp is safe. On return, > local error is automatically propagated to original one. So, the use of ERRP_AUTO_PROPAGATE() solves BOTH problems 1 and 2 - we avoid the boilerplate that trades one problem for another, by consolidating ALL of the boilerplate into a single-line macro, such that error_propagate() no longer needs to be called anywhere except inside the ERRP_AUTO_PROPAGATE macro. > >> >>> >>> === >>> >>> Our solution: >>> >>> - Fixes [1.], adding invocation of new macro into functions with error_appen_hint/error_prepend, >>> New macro will wrap error_fatal. >>> - Fixes [2.], by switching from hand-written local_err to smart macro, which never >>> wraps error_abort. >>> - Handles [3.], by switching to macro, which is less code >>> - Additionally, macro doesn't wrap normal non-zero errp, to avoid extra propagations >>> (in fact, error_propagate is called, but returns immediately on first if (!local_err)) >> > > -- Eric Blake, Principal Software Engineer Red Hat, Inc. +1-919-301-3226 Virtualization: qemu.org | libvirt.org From MAILER-DAEMON Thu Dec 05 12:42:50 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1icv9O-0005YA-4w for mharc-qemu-arm@gnu.org; Thu, 05 Dec 2019 12:42:50 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:34592) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1icv9K-0005VK-EE for qemu-arm@nongnu.org; Thu, 05 Dec 2019 12:42:47 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1icv9J-0001hm-2c for qemu-arm@nongnu.org; Thu, 05 Dec 2019 12:42:46 -0500 Received: from mail-ot1-x342.google.com ([2607:f8b0:4864:20::342]:33829) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1icv9I-0001d7-RL for qemu-arm@nongnu.org; Thu, 05 Dec 2019 12:42:44 -0500 Received: by mail-ot1-x342.google.com with SMTP id a15so3374326otf.1 for ; Thu, 05 Dec 2019 09:42:44 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=iNUL6o24JTKX4/e7ryKKlUun/EEBdrrjt6MWlFZHtt0=; b=dh0rYjcgJ3RUdG6Gi37DLPiYYqEgTj835qJegCy0kyY+lDtuZ6AKZ/RlvoBGc6KWUW eBHRoQ8REevtPRuvV8kANU8dLniuLz7/IAw1gpX/vBEGKoEf+kXVzpe5pbXy6MABH43U 74s1C5XjKl0rVVXtaDYOiHeLHPmbLFZ9BU9BTlgTzgGs/0ZeLZF9VdA3JuHWdMayVLnw X3oDG5Ipcffb9bsqxmEZ0MYyd5k+p+LKRFEXcImh9Y5yAtGfjym8CCqLMrM4RlS1YC+G YRn0RanjRCXuwSKKdUS4UgHXTqF8Zmhe9ydXg7pAe9rhXXQZ4DDYvxrFsh9RmYtm8L1j /39w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=iNUL6o24JTKX4/e7ryKKlUun/EEBdrrjt6MWlFZHtt0=; b=dXXQOl3Lvt3PNkXyYEVNpD405+Xi91XOUD6qG3pCzPtSFtzVknBEmYFKrtXaMgzCY6 RFKnKDMxzqjMM5KRcikCEqQwdlEt3+e9iVnQHsV6fU3icF2pMWqEvufkKz393La2alAh pA8ePxQKUhVOpcsvdfMmaK+AI/b/88dSlgNO6OhpYpxUCqKrqxhhE/uG//OBAMTI+eFN +eVtUXGXvQLHKd4tFwkh0ds1d+tfaoPgk00IsrMhWiO1JlL1nE0uF/LR+MWJ0BmP8dR7 yhwfkWey7iCIuH2XPxv/V8/FRn4NkGx9boFG756oMZbJ8XrDuaKoU8379RBAfYbiCAKb 8qOg== X-Gm-Message-State: APjAAAVCfDjQa8Wl3SRmGteSo3sfARANn3MyVdDjqCwrmhOInPjKze5V 8JsfCkk+MC56Whl1ZgzWgehTx+htMc3GMyXWwbXdhsBnz8c= X-Google-Smtp-Source: APXvYqx6SnlrN6LSAkuJjUGwQ8ZF+dX5PfYkn6xK3jgnd3etiGbxAubZMq5Ngau/EAcncoEzkJRnNCZf3483Jj6BemU= X-Received: by 2002:a05:6830:2001:: with SMTP id e1mr7043345otp.97.1575567763730; Thu, 05 Dec 2019 09:42:43 -0800 (PST) MIME-Version: 1.0 References: <20191011134744.2477-1-richard.henderson@linaro.org> <20191011134744.2477-14-richard.henderson@linaro.org> In-Reply-To: <20191011134744.2477-14-richard.henderson@linaro.org> From: Peter Maydell Date: Thu, 5 Dec 2019 17:42:32 +0000 Message-ID: Subject: Re: [PATCH v5 13/22] target/arm: Implement the LDGM and STGM instructions To: Richard Henderson Cc: QEMU Developers , qemu-arm Content-Type: text/plain; charset="UTF-8" X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::342 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 05 Dec 2019 17:42:48 -0000 On Fri, 11 Oct 2019 at 14:50, Richard Henderson wrote: > > Signed-off-by: Richard Henderson > --- > v3: Require pre-cleaned addresses. > --- > target/arm/helper-a64.h | 3 ++ > target/arm/mte_helper.c | 96 ++++++++++++++++++++++++++++++++++++++ > target/arm/translate-a64.c | 42 +++++++++++++---- > 3 files changed, 132 insertions(+), 9 deletions(-) > > diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c > index 4ecb0a2fb7..4e049bb4aa 100644 > --- a/target/arm/translate-a64.c > +++ b/target/arm/translate-a64.c > @@ -3592,7 +3592,7 @@ static void disas_ldst_tag(DisasContext *s, uint32_t insn) > uint64_t offset = sextract64(insn, 12, 9) << LOG2_TAG_GRANULE; > int op2 = extract32(insn, 10, 3); > int op1 = extract32(insn, 22, 2); > - bool is_load = false, is_pair = false, is_zero = false; > + bool is_load = false, is_pair = false, is_zero = false, is_mult = false; > int index = 0; > TCGv_i64 dirty_addr, clean_addr, tcg_rt; > > @@ -3602,13 +3602,18 @@ static void disas_ldst_tag(DisasContext *s, uint32_t insn) > } > These are the insns that should UNDEF if we have only the insn_reg dummy flavour of MTE. (Also, unlike STG and ST2G, none of the M insns want Xt to be .) Otherwise Reviewed-by: Peter Maydell thanks -- PMM From MAILER-DAEMON Thu Dec 05 12:49:43 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1icvG3-0001aw-Oz for mharc-qemu-arm@gnu.org; Thu, 05 Dec 2019 12:49:43 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:53135) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1icvG0-0001XD-NA for qemu-arm@nongnu.org; Thu, 05 Dec 2019 12:49:41 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1icvFz-0001x2-2n for qemu-arm@nongnu.org; Thu, 05 Dec 2019 12:49:40 -0500 Received: from mail-oi1-x241.google.com ([2607:f8b0:4864:20::241]:39239) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1icvFy-0001rb-Oh for qemu-arm@nongnu.org; Thu, 05 Dec 2019 12:49:38 -0500 Received: by mail-oi1-x241.google.com with SMTP id a67so3542023oib.6 for ; Thu, 05 Dec 2019 09:49:38 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=7TZrodYeXioGpPRAE8ETahiLdBZLUfn2Bk6fVVqCSEE=; b=HUNJNG/dr1YTRjWt3dX54M87sHzpPiOvZQre8eN8yoJpamPABH+Kh6Isj8UR3GJh0f mBL30w3DXmU2D7ge6BEDL0rCIl6R6EeVAx0MfF16CjbcCqjVfxGA/RJT9JY8JYqtl5+i LUO7SuZMqr5QA2DrFxo6G5zEV+ASvZdQecLM69Wrs/LmTeHdEw+PLa3KgIN0v5kLTrKW 4XSw+n7YPYB/2OYM91K/WI3ULiMp4Np35xvQXUFBY/hK9VEKyNEqhhJxbsG+WJIQl5Se ZlYflHgu3NyCyGD8az9dwFBOKBXpG/Cj/7IKqPXdfmm6xj18SWN2YORi4PmpuNSmhQQS iyOg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=7TZrodYeXioGpPRAE8ETahiLdBZLUfn2Bk6fVVqCSEE=; b=RO5bNEDXc6IRUxTuFXnoRlMmCjdS9jNuCfQfZMRw0nntApIaRlRC1k1/no26m3nv0J k5YMC4XSBxBgytSWa4xXpDtCF6qCIA7IhxrbF8i0ERKY/2mmEUUbiHvikQoBVTUuN5ZV vxMP98MBkDT4L6h8MTuIzQ8SYYq0rOxPiSIrrkKqIyoTnnj6z741nVodAdFcsHnRwUPS PCvPvbc7EtqqU6PubBJNW0DCHyuLblfbGVJPFAahCRZtpMgmaPo1iEAuMx6tzUIu+Yq3 r1E/f7Z7urA3liR7nlKTnv4T/VfaMvavH+P4EBaMsa/R3p6WCp+y9ypeBVl77Xtk1l4n 84iw== X-Gm-Message-State: APjAAAWF0m4t/bDp1qsQaM+Pb1k/MCGm5CV6GSvEzO2Fy3ZC+x0yC7de VjCgy1C15Em/RXZM4JrSv8slMWl5jj/hG0SIQoXz0Q== X-Google-Smtp-Source: APXvYqxz4uaWdLhYj/w4g6/vR65niMndWEAx9/kARVQUdtjT6Y7737Yk4n5sFptfNJhhLagz90O2RyazktSQVyCUEQM= X-Received: by 2002:aca:3182:: with SMTP id x124mr8488329oix.170.1575568177597; Thu, 05 Dec 2019 09:49:37 -0800 (PST) MIME-Version: 1.0 References: <20191011134744.2477-1-richard.henderson@linaro.org> <20191011134744.2477-15-richard.henderson@linaro.org> In-Reply-To: <20191011134744.2477-15-richard.henderson@linaro.org> From: Peter Maydell Date: Thu, 5 Dec 2019 17:49:26 +0000 Message-ID: Subject: Re: [PATCH v5 14/22] target/arm: Implement the access tag cache flushes To: Richard Henderson Cc: QEMU Developers , qemu-arm Content-Type: text/plain; charset="UTF-8" X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::241 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 05 Dec 2019 17:49:42 -0000 On Fri, 11 Oct 2019 at 14:50, Richard Henderson wrote: > > Like the regular data cache flushes, these are nops within qemu. > > Signed-off-by: Richard Henderson > --- > target/arm/helper.c | 48 +++++++++++++++++++++++++++++++++++++++++++++ > 1 file changed, 48 insertions(+) > > diff --git a/target/arm/helper.c b/target/arm/helper.c > index f435a8d8bd..33bc176e1c 100644 > --- a/target/arm/helper.c > +++ b/target/arm/helper.c > @@ -5978,6 +5978,54 @@ static const ARMCPRegInfo mte_reginfo[] = { > { .name = "GMID_EL1", .state = ARM_CP_STATE_AA64, > .opc0 = 3, .opc1 = 1, .crn = 0, .crm = 0, .opc2 = 4, > .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = GMID_EL1_BS }, > + { .name = "IGVAC", .state = ARM_CP_STATE_AA64, > + .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 6, .opc2 = 3, > + .type = ARM_CP_NOP, .access = PL1_W }, > + { .name = "IGSW", .state = ARM_CP_STATE_AA64, > + .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 6, .opc2 = 4, > + .type = ARM_CP_NOP, .access = PL1_W }, > + { .name = "IGDVAC", .state = ARM_CP_STATE_AA64, > + .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 6, .opc2 = 5, > + .type = ARM_CP_NOP, .access = PL1_W }, > + { .name = "IGDSW", .state = ARM_CP_STATE_AA64, > + .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 6, .opc2 = 6, > + .type = ARM_CP_NOP, .access = PL1_W }, > + { .name = "CGSW", .state = ARM_CP_STATE_AA64, > + .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 10, .opc2 = 4, > + .type = ARM_CP_NOP, .access = PL1_W }, > + { .name = "CGDSW", .state = ARM_CP_STATE_AA64, > + .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 10, .opc2 = 6, > + .type = ARM_CP_NOP, .access = PL1_W }, > + { .name = "CIGSW", .state = ARM_CP_STATE_AA64, > + .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 14, .opc2 = 4, > + .type = ARM_CP_NOP, .access = PL1_W }, > + { .name = "CIGDSW", .state = ARM_CP_STATE_AA64, > + .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 14, .opc2 = 6, > + .type = ARM_CP_NOP, .access = PL1_W }, > + { .name = "CGVAC", .state = ARM_CP_STATE_AA64, > + .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 10, .opc2 = 3, > + .type = ARM_CP_NOP, .access = PL1_W }, > + { .name = "CGDVAC", .state = ARM_CP_STATE_AA64, > + .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 10, .opc2 = 5, > + .type = ARM_CP_NOP, .access = PL1_W }, > + { .name = "CGVAP", .state = ARM_CP_STATE_AA64, > + .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 12, .opc2 = 3, > + .type = ARM_CP_NOP, .access = PL1_W }, > + { .name = "CGDVAP", .state = ARM_CP_STATE_AA64, > + .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 12, .opc2 = 5, > + .type = ARM_CP_NOP, .access = PL1_W }, > + { .name = "CGVADP", .state = ARM_CP_STATE_AA64, > + .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 13, .opc2 = 3, > + .type = ARM_CP_NOP, .access = PL1_W }, > + { .name = "CGDVADP", .state = ARM_CP_STATE_AA64, > + .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 13, .opc2 = 5, > + .type = ARM_CP_NOP, .access = PL1_W }, > + { .name = "CIGVAC", .state = ARM_CP_STATE_AA64, > + .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 14, .opc2 = 3, > + .type = ARM_CP_NOP, .access = PL1_W }, > + { .name = "CIGDVAC", .state = ARM_CP_STATE_AA64, > + .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 14, .opc2 = 5, > + .type = ARM_CP_NOP, .access = PL1_W }, > REGINFO_SENTINEL > }; Some of these, but not all, are conditionally available at EL0, which means that for those that are: * .access should be PL0_W * .accessfn should be aa64_cacheop_access() (which checks SCTLR_EL1.UCI) * they need to be in a reginfo that makes them available for the insns-and-regs-only flavour of MTE thanks -- PMM From MAILER-DAEMON Thu Dec 05 12:55:00 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1icvLA-0008S2-4s for mharc-qemu-arm@gnu.org; Thu, 05 Dec 2019 12:55:00 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:42853) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1icvL5-0008L6-US for qemu-arm@nongnu.org; Thu, 05 Dec 2019 12:54:56 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1icvL4-0003ga-SU for qemu-arm@nongnu.org; Thu, 05 Dec 2019 12:54:55 -0500 Received: from mail-ot1-x343.google.com ([2607:f8b0:4864:20::343]:38396) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1icvL4-0003gQ-M3 for qemu-arm@nongnu.org; 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Thu, 05 Dec 2019 09:54:53 -0800 (PST) MIME-Version: 1.0 References: <20191011134744.2477-1-richard.henderson@linaro.org> <20191011134744.2477-16-richard.henderson@linaro.org> In-Reply-To: <20191011134744.2477-16-richard.henderson@linaro.org> From: Peter Maydell Date: Thu, 5 Dec 2019 17:54:43 +0000 Message-ID: Subject: Re: [PATCH v5 15/22] target/arm: Clean address for DC ZVA To: Richard Henderson Cc: QEMU Developers , qemu-arm Content-Type: text/plain; charset="UTF-8" X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::343 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 05 Dec 2019 17:54:58 -0000 On Fri, 11 Oct 2019 at 14:50, Richard Henderson wrote: > > This data access was forgotten in the previous patch. Do you mean "in the patch where we added support for cleaning addresses of TBI information"? As written it sounds like you're referring to the previous patch in this patchseries. > Fixes: 3a471103ac1823ba > Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell thanks -- PMM From MAILER-DAEMON Thu Dec 05 12:58:48 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1icvOq-0003sm-Lg for mharc-qemu-arm@gnu.org; Thu, 05 Dec 2019 12:58:48 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:54318) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1icvOm-0003jB-Dp for qemu-arm@nongnu.org; Thu, 05 Dec 2019 12:58:45 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1icvOl-0005WA-0T for qemu-arm@nongnu.org; Thu, 05 Dec 2019 12:58:44 -0500 Received: from mail-wm1-x343.google.com ([2a00:1450:4864:20::343]:55352) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1icvOk-0005R0-Lc for qemu-arm@nongnu.org; Thu, 05 Dec 2019 12:58:42 -0500 Received: by mail-wm1-x343.google.com with SMTP id q9so4900567wmj.5 for ; Thu, 05 Dec 2019 09:58:42 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=references:user-agent:from:to:cc:subject:in-reply-to:date :message-id:mime-version:content-transfer-encoding; bh=zMecNqqSJ4VYfE/rNTGUDOH12wNz/+QCGWYMWDkatnw=; b=IoWIJMAifHTwtkmnO6vgnTrUBLDmvpqfdgd3vANXlY6EOX2nIMI7et2D9rrSR7Z3uF MGE7TZCLiyhBhevScAUidT+i0b6bftMNaCMmm49DFyGzUdUMv7Yu835B6CN/N05LnT+a jXKKjKAOLi7716w7VNPdYIAWyjtfdfFstFFjaOeAsB3Z7k3GzxETo+c8Qr9+c07A88Ni e+ZIy2OdK1zKG8RD1dsMDHIE2k0SH24Qhi2qaHSY4WSxDAXTddB6PXjw7zX6O/J8/RI8 DNoIOSBjIsJ2NTDlxMu645yMtyP9e54O0MK6EppBSZruRRc17T2rZbv853M0Q8+A4AUe dmLA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:references:user-agent:from:to:cc:subject :in-reply-to:date:message-id:mime-version:content-transfer-encoding; bh=zMecNqqSJ4VYfE/rNTGUDOH12wNz/+QCGWYMWDkatnw=; b=SknURwtaoBNIvb1+pXgjjLD4t494Vd2+BlgrdjPC4TB6cBwuwvAAYKfYT0mgrzU9mI 84fEdtxsLKpXb2ecWkboOWzIQQIAbHRzZ5Qcalw5WI3TjFh/dCNIUxN/6RHw0tlROrJ6 R54Dfl6QuDaht48UCwAvcWbIkEPjoV+xNinhruBeV8k5P86DoXJawGaDpRdWkG3IK8dk G+Zwj5gihbkWqB+c1EWFUfnZlxkYPoHHX4xZAUclJ5+pfjHCpky4jxLW8pzaZs/5BzD1 cg30uKe6fAHY5yPNfQLLK64cioBl/i8B1F3B1N2mR4/IvMh55l7k587CbqXh8Mzll7xZ uI+Q== X-Gm-Message-State: APjAAAXQf3/7U7GFgAMes5hX+rqRAK/rdRy9o62sNI7GRu49O2X08eR/ pzmOR8pHhP51M8tOWQvwlCINWA== X-Google-Smtp-Source: APXvYqxV8LbcaCOV6vBjSzDSswM/k2nv1dJvpI8Xxj3yxlJsl6ZqXbbW2HF1okJelzOr+87AlL1gyw== X-Received: by 2002:a05:600c:249:: with SMTP id 9mr6329166wmj.2.1575568721311; Thu, 05 Dec 2019 09:58:41 -0800 (PST) Received: from zen.linaroharston ([51.148.130.216]) by smtp.gmail.com with ESMTPSA id t5sm13215195wrr.35.2019.12.05.09.58.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 05 Dec 2019 09:58:39 -0800 (PST) Received: from zen (localhost [127.0.0.1]) by zen.linaroharston (Postfix) with ESMTP id 3E09E1FF87; Thu, 5 Dec 2019 17:58:39 +0000 (GMT) References: <20191130084602.10818-1-alex.bennee@linaro.org> <20191130084602.10818-7-alex.bennee@linaro.org> <987465d3-3b13-e675-9622-c13e2d5205c2@redhat.com> <42017B4E-E961-494C-A505-FCDA74EFB265@arm.com> User-agent: mu4e 1.3.5; emacs 27.0.50 From: Alex =?utf-8?Q?Benn=C3=A9e?= To: Alan Hayward Cc: "qemu-devel@nongnu.org" , "damien.hedde@greensocs.com" , Peter Maydell , Luis Machado , "richard.henderson@linaro.org" , "open list:ARM TCG CPUs" , Philippe =?utf-8?Q?Mathieu-Daud=C3=A9?= , nd Subject: Re: [PATCH v2 06/14] target/arm: use gdb_get_reg helpers In-reply-to: <42017B4E-E961-494C-A505-FCDA74EFB265@arm.com> Date: Thu, 05 Dec 2019 17:58:39 +0000 Message-ID: <87lfrq7iy8.fsf@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::343 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 05 Dec 2019 17:58:47 -0000 Alan Hayward writes: >> On 1 Dec 2019, at 20:05, Philippe Mathieu-Daud=C3=A9 = wrote: >>=20 >> On 11/30/19 9:45 AM, Alex Benn=C3=A9e wrote: >>> This is cleaner than poking memory directly and will make later >>> clean-ups easier. >>> Signed-off-by: Alex Benn=C3=A9e >>> --- >>> v2 >>> - make sure we pass hi/lo correctly as quads are stored in LE order >>> --- >>> target/arm/helper.c | 18 +++++++----------- >>> 1 file changed, 7 insertions(+), 11 deletions(-) >>> diff --git a/target/arm/helper.c b/target/arm/helper.c >>> index 0bf8f53d4b8..0ac950d6c71 100644 >>> --- a/target/arm/helper.c >>> +++ b/target/arm/helper.c >>> @@ -105,21 +105,17 @@ static int aarch64_fpu_gdb_get_reg(CPUARMState *e= nv, uint8_t *buf, int reg) >>> { >>> switch (reg) { >>> case 0 ... 31: >>> - /* 128 bit FP register */ >>> - { >>> - uint64_t *q =3D aa64_vfp_qreg(env, reg); >>> - stq_le_p(buf, q[0]); >>> - stq_le_p(buf + 8, q[1]); >>> - return 16; >>> - } >>> + { >>> + /* 128 bit FP register - quads are in LE order */ >>=20 >> Oh, this was always wrong on BE :( > > Am I right in thinking this patch correctly matches the SVE BE changes fr= om June? > > Specifically, this patch: > http://lists.infradead.org/pipermail/linux-arm-kernel/2019-June/657826.ht= ml Not quite. This is just taking into account the way we store the data internally in cpu.h. The gdb_get_reg128 helper will then ensure stuff is in target endian format which is what gdbstub defines. There aren't any actual kernel to userspace transfers going on here. > > > Alan. > >>=20 >> Reviewed-by: Philippe Mathieu-Daud=C3=A9 >>=20 >>> + uint64_t *q =3D aa64_vfp_qreg(env, reg); >>> + return gdb_get_reg128(buf, q[1], q[0]); >>> + } >>> case 32: >>> /* FPSR */ >>> - stl_p(buf, vfp_get_fpsr(env)); >>> - return 4; >>> + return gdb_get_reg32(buf, vfp_get_fpsr(env)); >>> case 33: >>> /* FPCR */ >>> - stl_p(buf, vfp_get_fpcr(env)); >>> - return 4; >>> + return gdb_get_reg32(buf,vfp_get_fpcr(env)); >>> default: >>> return 0; >>> } --=20 Alex Benn=C3=A9e From MAILER-DAEMON Thu Dec 05 13:17:49 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1icvhF-0005tF-6H for mharc-qemu-arm@gnu.org; Thu, 05 Dec 2019 13:17:49 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:54148) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1icvh7-0005oq-Kz for qemu-arm@nongnu.org; Thu, 05 Dec 2019 13:17:42 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1icvh5-0001De-RE for qemu-arm@nongnu.org; Thu, 05 Dec 2019 13:17:41 -0500 Received: from mail-ot1-x341.google.com ([2607:f8b0:4864:20::341]:45708) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1icvh5-00019f-LV for qemu-arm@nongnu.org; Thu, 05 Dec 2019 13:17:39 -0500 Received: by mail-ot1-x341.google.com with SMTP id 59so3406925otp.12 for ; Thu, 05 Dec 2019 10:17:39 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=YZ4Mv11SbDP5AhWiY1/9jeSZG9dC8AF0VxMGlBUfvlo=; b=Ipl2EU0Nj4ZgDIEFzKSAjPGLxvdDU6FB7z0H+28C46+NaH88JCG/94tMI2O2DIT1eG f4JN8+xm2HKsjFudmLkE/0rzk2E3ZaW5p8JcIey0JDKhbluASgJNJxTpDe3xe79DKTwO FWrMHErCqvaBecO+jZe1ROvWw0N0Tv4KfNbxS2JJGJpZN6+rU1fi1UQGy7rOggyTcNJ/ UDcU4fv/KCZd09zWix0UmGIzDxCBOtOf3CnpGvU+QbOXg1sZwPr0QpWPynqAFpjiEmbV UO8ybBBRzgrYWsDk3h5z/DyQGDHAwH94mn57pVT/pijUw5nccb1hcgwb6moJe9ugRb+5 cScQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=YZ4Mv11SbDP5AhWiY1/9jeSZG9dC8AF0VxMGlBUfvlo=; b=oiC6q+XYQSV3kI02m1iYsdHCJ3heJDb8SJcDUHmelHMSA+nlRXvLUuVdTt6XR57aUC FG374dY0NcjuqFhvNZgTwhlemkqSfBkVoAKI7R3CpQL7riElOBW/M2aqSwgdAylDCikQ 4XCDwH/DJl+e/ksnAmHRuwC7GiP4l/KQyqbqMBw0ADjHl6Wy/8SD2fe3fyC9a2tJu/Q8 4DSiHLxqxwwQyoQ2al20VS4X6QY6WZoljB/1Rgb+wcyu0O0Z6wgqRea8Miasi8cu3SC0 1MACspxe5NMqou6h8FlhDDyXAN6VWfRWha1ADlxjbR3fKt4lXhHwMT71QWG6Ci2VHU7Q xK8Q== X-Gm-Message-State: APjAAAUdbBf7nda3nxNwBXY4cVtTLG3CAWtIUmiLHHmsx/+/15V/hu3f egBDwnknpxol6PWkSs7pGCbpuRcL/KdN49jGxyWpNg== X-Google-Smtp-Source: APXvYqzkxcU2015HGUspQwgwNwRnTrMjHDlzJSVP5pjq2g6nclp0TxuEvWiZjawykVA39s0nDPTqlf4yzM0juF86HkY= X-Received: by 2002:a05:6830:4a4:: with SMTP id l4mr1878403otd.91.1575569858679; Thu, 05 Dec 2019 10:17:38 -0800 (PST) MIME-Version: 1.0 References: <20191011134744.2477-1-richard.henderson@linaro.org> <20191011134744.2477-17-richard.henderson@linaro.org> In-Reply-To: <20191011134744.2477-17-richard.henderson@linaro.org> From: Peter Maydell Date: Thu, 5 Dec 2019 18:17:27 +0000 Message-ID: Subject: Re: [PATCH v5 16/22] target/arm: Implement data cache set allocation tags To: Richard Henderson Cc: QEMU Developers , qemu-arm Content-Type: text/plain; charset="UTF-8" X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::341 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 05 Dec 2019 18:17:43 -0000 On Fri, 11 Oct 2019 at 14:50, Richard Henderson wrote: > > This is DC GVA and DC GZVA. > > Signed-off-by: Richard Henderson > --- > v2: Use allocation_tag_mem + memset. > v3: Require pre-cleaned addresses. > --- > diff --git a/target/arm/mte_helper.c b/target/arm/mte_helper.c > index f1315bae37..e8d8a6bedb 100644 > --- a/target/arm/mte_helper.c > +++ b/target/arm/mte_helper.c > @@ -510,3 +510,31 @@ void HELPER(stzgm)(CPUARMState *env, uint64_t ptr, uint64_t val) > } > } > } > + > +void HELPER(dc_gva)(CPUARMState *env, uint64_t ptr) > +{ > + ARMCPU *cpu = env_archcpu(env); > + size_t blocklen = 4 << cpu->dcz_blocksize; > + int el; > + uint64_t sctlr; > + uint8_t *mem; > + int rtag; > + > + ptr = QEMU_ALIGN_DOWN(ptr, blocklen); > + > + /* Trap if accessing an invalid page. */ > + mem = allocation_tag_mem(env, ptr, true, GETPC()); > + > + /* No action if page does not support tags, or if access is disabled. */ > + el = arm_current_el(env); > + sctlr = arm_sctlr(env, el); > + if (!mem || !allocation_tag_access_enabled(env, el, sctlr)) { > + return; > + } > + > + rtag = allocation_tag_from_addr(ptr); > + rtag |= rtag << 4; > + > + assert(QEMU_IS_ALIGNED(blocklen, 2 * TAG_GRANULE)); Could we assert this on CPU init rather than in this helper? That way if anybody tries to create a CPU whose dcz_blocksize doesn't work with the TAG_GRANULE they'll realize immediately rather than only if they happen to run a guest workload that use DC GVA or DC GZVA. I also had to think a bit to work out which way round this assert is checking: it's testing that the ZVA block length (usually 64 bytes) is a multiple of (twice the TAG_GRANULE), which is to say a multiple of 32. Given that the blocksize is stored as a log2 value, this can only fail for blocksizes 16, 8, 4, 2 or 1, which are all fairly unlikely. > + memset(mem, rtag, blocklen / (2 * TAG_GRANULE)); > +} > diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c > index 49817b96ae..31260f97f9 100644 > --- a/target/arm/translate-a64.c > +++ b/target/arm/translate-a64.c > @@ -1769,6 +1769,15 @@ static void handle_sys(DisasContext *s, uint32_t insn, bool isread, > tcg_rt = clean_data_tbi(s, cpu_reg(s, rt), false); > gen_helper_dc_zva(cpu_env, tcg_rt); > return; > + case ARM_CP_DC_GVA: > + tcg_rt = clean_data_tbi(s, cpu_reg(s, rt), false); > + gen_helper_dc_gva(cpu_env, tcg_rt); > + return; > + case ARM_CP_DC_GZVA: > + tcg_rt = clean_data_tbi(s, cpu_reg(s, rt), false); > + gen_helper_dc_zva(cpu_env, tcg_rt); > + gen_helper_dc_gva(cpu_env, tcg_rt); I think this means that if there's a watchpoint set on the memory partway through the block we're zeroing then we'll take the watchpoint with some of the memory zeroed but without the corresponding tags having been updated. But that's probably OK (at any rate I wouldn't worry about it for now...) > + return; > default: > break; > } > -- Otherwise Reviewed-by: Peter Maydell thanks -- PMM From MAILER-DAEMON Thu Dec 05 13:23:18 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1icvmY-0002tm-Bn for mharc-qemu-arm@gnu.org; Thu, 05 Dec 2019 13:23:18 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:42534) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1icvmU-0002pm-W3 for qemu-arm@nongnu.org; Thu, 05 Dec 2019 13:23:16 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1icvmT-0003Jy-JG for qemu-arm@nongnu.org; Thu, 05 Dec 2019 13:23:14 -0500 Received: from mail-oi1-x241.google.com ([2607:f8b0:4864:20::241]:43323) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1icvmT-0003EM-Cb for qemu-arm@nongnu.org; Thu, 05 Dec 2019 13:23:13 -0500 Received: by mail-oi1-x241.google.com with SMTP id x14so89751oic.10 for ; Thu, 05 Dec 2019 10:23:13 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=ywEp5s2xOWuK7D7RAlraYeWBuhfECY/Yhnh+tMIgVBs=; b=AxD8RNjGmJa+dEMPmKEOO/bjIN97EHefoZbrvr7v+i5ltyu9sYvLYCpXljaSdU/tck /GDPHBB3OH+Gyq32SoZGQaudU29cb3pokh9Z/L0czQIcRFpQ1YfQmTotbfV0iHWJ9/yj ydVWfCZ2tbT91VEPxsrSEpJ13Wq/PGGiDgaTRa0gS2dftTJePqx1q675giQ37ZFemvfj W8C+TPZZgv7T1gs8oiikMTZPiLFenM3QmKd25Dho+ygVNlzdj0nBmOMSzdsHERBshHGR dvCO2Irssit8DtR+4mxugpj45lWt9ulpz9ILM38O6diXuDLa6uCje+f30UV86w/+C71P VReg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=ywEp5s2xOWuK7D7RAlraYeWBuhfECY/Yhnh+tMIgVBs=; b=jOATgwKQIRxWmwshIr1jdVz8+/uVUcAaoPlhmj5vvt2Lvvj45nEA2wztdhR4Zlx0qT 6XVpXTLBmoJhPKt+SgC4c5pc7nkH/NxQgxma2nV8xDDK5IMjRpQe0oxTU+90nMch6BGc N5UH2+brfUGgqPaXg65zy83kFkruGYBsVJ12/pjlO/g6Fv1c3N8QS/0LvBdRBePTWTsA YzW2CQHiED8low6WYtRSldEHaWs1joNloo7nVQNXhQzlPeMxI652dwtgCD6bg3RJd7iI Q4qoF+WnIReK3tkgaGz5UY1bFwXC8gLlgyxIwIgRZr+Eyb7p+x4CqH1pq0cytiyqMSM7 ECEw== X-Gm-Message-State: APjAAAU5fKIr2uhlh8CqXOUrJN6uvxzU16J/ijl44uN1iVC+B8tQoKDM fwbDG6Lpl0PM/Hezi1BzbWisGkWbJ+qIr7nEh2XPmg== X-Google-Smtp-Source: APXvYqynT2e8OWp2aD6Gz2f39kybeFFAOBdo/R8aF7Gru9sOIkSyLgsI5RAIT/v21tPyBMD/44lWoDngEd1qezP9AsI= X-Received: by 2002:aca:f5cc:: with SMTP id t195mr8633767oih.163.1575570192219; Thu, 05 Dec 2019 10:23:12 -0800 (PST) MIME-Version: 1.0 References: <20191011134744.2477-1-richard.henderson@linaro.org> <20191011134744.2477-19-richard.henderson@linaro.org> In-Reply-To: <20191011134744.2477-19-richard.henderson@linaro.org> From: Peter Maydell Date: Thu, 5 Dec 2019 18:23:01 +0000 Message-ID: Subject: Re: [PATCH v5 18/22] target/arm: Enable MTE To: Richard Henderson Cc: QEMU Developers , qemu-arm Content-Type: text/plain; charset="UTF-8" X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::241 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 05 Dec 2019 18:23:17 -0000 On Fri, 11 Oct 2019 at 14:50, Richard Henderson wrote: > > We now implement all of the components of MTE, without actually > supporting any tagged memory. All MTE instructions will work, > trivially, so we can enable support. > > Signed-off-by: Richard Henderson > --- > target/arm/cpu.c | 10 ++++++++++ > target/arm/cpu64.c | 1 + > 2 files changed, 11 insertions(+) > > diff --git a/target/arm/cpu.c b/target/arm/cpu.c > index 2399c14471..12fffa3ee4 100644 > --- a/target/arm/cpu.c > +++ b/target/arm/cpu.c > @@ -209,6 +209,16 @@ static void arm_cpu_reset(CPUState *s) > * make no difference to the user-level emulation. > */ > env->cp15.tcr_el[1].raw_tcr = (3ULL << 37); > + /* Enable MTE allocation tags. */ > + env->cp15.hcr_el2 |= HCR_ATA; > + env->cp15.scr_el3 |= SCR_ATA; > + env->cp15.sctlr_el[1] |= SCTLR_ATA0; > + /* Enable synchronous tag check failures. */ > + env->cp15.sctlr_el[1] |= 1ull << 38; Isn't this making assumptions about the Linux ABI for memtag (ie that it actually will expose it to userspace and that it will make tag check failures synchronous)? > +#ifdef TARGET_AARCH64 > + /* Set MTE seed to non-zero value, otherwise RandomTag fails. */ > + env->cp15.rgsr_el1 = 0x123400; > +#endif Does anything go wrong if we don't bother with the #ifdef? > #else > /* Reset into the highest available EL */ > if (arm_feature(env, ARM_FEATURE_EL3)) { > diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c > index d7f5bf610a..ac1e2dc2c4 100644 > --- a/target/arm/cpu64.c > +++ b/target/arm/cpu64.c > @@ -350,6 +350,7 @@ static void aarch64_max_initfn(Object *obj) > > t = cpu->isar.id_aa64pfr1; > t = FIELD_DP64(t, ID_AA64PFR1, BT, 1); > + t = FIELD_DP64(t, ID_AA64PFR1, MTE, 2); > cpu->isar.id_aa64pfr1 = t; > > t = cpu->isar.id_aa64mmfr1; > -- thanks -- PMM From MAILER-DAEMON Thu Dec 05 13:32:54 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1icvvo-0001TN-Q3 for mharc-qemu-arm@gnu.org; Thu, 05 Dec 2019 13:32:53 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:39413) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1icvvk-0001T5-Am for qemu-arm@nongnu.org; Thu, 05 Dec 2019 13:32:49 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1icvvi-00082W-DN for qemu-arm@nongnu.org; Thu, 05 Dec 2019 13:32:47 -0500 Received: from mail-oi1-x241.google.com ([2607:f8b0:4864:20::241]:41122) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1icvvh-00080w-Dd for qemu-arm@nongnu.org; Thu, 05 Dec 2019 13:32:45 -0500 Received: by mail-oi1-x241.google.com with SMTP id i1so3666022oie.8 for ; Thu, 05 Dec 2019 10:32:43 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=fo78LySk+IDjHJmOYFaESpk0uW4l7d7VSVykxo1MFYI=; b=zok+uz4GuyolOqem9+ituSa4mJxRpP4Baj0B9R9dNwdGTomF5SOyvNSTGkpy7bIX3k 3eDPSksWNCgnyJTwh48YE3tnW48xZ67H2xg/O0tXRP33L4NDNQ4mio75LW6mbkYbtpYM UOdUuNhyeczdFJ6u/Ndxsojau2KpWHsGIbgb7aGFwU0N+nDROs1BiueQSypHpnxN+fHF pN09mUJ+7p2XnhXWBll22+UcfNm4D7gpUTEvDmez+OL1RYFBqnnIYEBjNpeJoXgxxemP t8GnY9Uk1CImxIwhr2PQnZ5sjf1weiOLvB8u9n6hM9eUleorbAZl2ZeiMDVpj+JDMmlP GChg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=fo78LySk+IDjHJmOYFaESpk0uW4l7d7VSVykxo1MFYI=; b=TdUhnRFLkYlCrwkSzjQg1eVaRWIoyvHJeGqrCLBKWt2HmDaucWZO1BI9CY+YmXDaW/ QOtUgnDfV4fdlXW7KizEUkVXtzG0k+JN2Yikz3aftBMTKFM59NbDUvc1NlyZmfhl1E5F F5FhesxUCUZ3nB8IRineys/Qs3Dd7Y+xGr1+4eiatvkFNKdnlJ6CioRMruvv5Gv3X83T H4nY2nca0LWtbycSgE/1wSDasZ4IOMdG1Eru5ZUmLElXX+EdVPUjphqbqJPoFSAfyYvf JJpnUYIMT0SAub4NJlYWbuLD96mtJDLAqcMrbYSewN73K4fVdzJDbos1SOL2WiXilQqp QSpQ== X-Gm-Message-State: APjAAAWlIdSBeebm8NXJtkF4PrNVkyhu0Z3VHqDf7t4tt6uqg/tA5NUs rOW39MKCgw9uFVtZyea0tBG1wB4DII+GMHjtoxelRyuJKss= X-Google-Smtp-Source: APXvYqx4W0hD3SZOGmrfMuHkD1IEodWRg+9Hf/ZCYhSrdcYHyrMWDp5hWm+p2ctXmqJTRG2mgiDPp2FlVdxtGRWCJts= X-Received: by 2002:aca:f5cc:: with SMTP id t195mr8680471oih.163.1575570762676; Thu, 05 Dec 2019 10:32:42 -0800 (PST) MIME-Version: 1.0 References: <20191011134744.2477-1-richard.henderson@linaro.org> <20191011134744.2477-20-richard.henderson@linaro.org> In-Reply-To: <20191011134744.2477-20-richard.henderson@linaro.org> From: Peter Maydell Date: Thu, 5 Dec 2019 18:32:31 +0000 Message-ID: Subject: Re: [PATCH v5 19/22] target/arm: Cache the Tagged bit for a page in MemTxAttrs To: Richard Henderson Cc: QEMU Developers , qemu-arm Content-Type: text/plain; charset="UTF-8" X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::241 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 05 Dec 2019 18:32:50 -0000 On Fri, 11 Oct 2019 at 14:50, Richard Henderson wrote: > > This "bit" is a particular value of the page's MemAttr. > > Signed-off-by: Richard Henderson > --- > target/arm/helper.c | 25 +++++++++++++++---------- > 1 file changed, 15 insertions(+), 10 deletions(-) > > diff --git a/target/arm/helper.c b/target/arm/helper.c > index e988398fce..17981d7c48 100644 > --- a/target/arm/helper.c > +++ b/target/arm/helper.c > @@ -9609,6 +9609,7 @@ static bool get_phys_addr_lpae(CPUARMState *env, target_ulong address, > uint64_t descaddrmask; > bool aarch64 = arm_el_is_aa64(env, el); > bool guarded = false; > + uint8_t memattr; > > /* TODO: > * This code does not handle the different format TCR for VTCR_EL2. > @@ -9836,17 +9837,21 @@ static bool get_phys_addr_lpae(CPUARMState *env, target_ulong address, > txattrs->target_tlb_bit0 = true; > } > > + if (mmu_idx == ARMMMUIdx_S2NS) { > + memattr = convert_stage2_attrs(env, extract32(attrs, 0, 4)); > + } else { > + /* Index into MAIR registers for cache attributes */ > + uint64_t mair = env->cp15.mair_el[el]; > + memattr = extract64(mair, extract32(attrs, 0, 3) * 8, 8); > + } > + > + /* When in aarch64 mode, and MTE is enabled, remember Tagged in IOTLB. */ > + if (aarch64 && memattr == 0xf0 && cpu_isar_feature(aa64_mte, cpu)) { > + txattrs->target_tlb_bit1 = true; > + } A comment somewhere saying that 0xf0 is the "Tagged Normal Memory" attribute would probably be helpful. > + > if (cacheattrs != NULL) { > - if (mmu_idx == ARMMMUIdx_S2NS) { > - cacheattrs->attrs = convert_stage2_attrs(env, > - extract32(attrs, 0, 4)); > - } else { > - /* Index into MAIR registers for cache attributes */ > - uint8_t attrindx = extract32(attrs, 0, 3); > - uint64_t mair = env->cp15.mair_el[regime_el(env, mmu_idx)]; > - assert(attrindx <= 7); > - cacheattrs->attrs = extract64(mair, attrindx * 8, 8); > - } > + cacheattrs->attrs = memattr; > cacheattrs->shareability = extract32(attrs, 6, 2); > } Don't we also need to care about the stage 2 attributes somewhere ? If the combo of stage 1 + stage 2 doesn't say it's Normal Inner&OuterShareable WB NT RA WA then it shouldn't be Tagged even if the stage 1 attributes ask for that. There's also the special case for "stage 1 translation disabled" -- depends on HCR_EL2.DC and HCR_EL2.DCT. thanks -- PMM From MAILER-DAEMON Thu Dec 05 13:40:17 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1icw2z-0003IN-OQ for mharc-qemu-arm@gnu.org; Thu, 05 Dec 2019 13:40:17 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:58859) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1icw2x-0003IA-O9 for qemu-arm@nongnu.org; Thu, 05 Dec 2019 13:40:17 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1icw2w-0004YC-2L for qemu-arm@nongnu.org; Thu, 05 Dec 2019 13:40:15 -0500 Received: from mail-oi1-x242.google.com ([2607:f8b0:4864:20::242]:41190) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1icw2v-0004U7-Lr for qemu-arm@nongnu.org; Thu, 05 Dec 2019 13:40:13 -0500 Received: by mail-oi1-x242.google.com with SMTP id i1so3687957oie.8 for ; Thu, 05 Dec 2019 10:40:11 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=wpET3lzcKB22iPNVtFlsEzKa/4+3mu1B+c0PsjFBF2Y=; b=PkcPrGAhkb+DaTfiZwjROMKVihOXHHwj2emaoP151g9t7Wbca8W9qESxPnIT06fNuz 0adVpiSY/67REJmRnpeC/Aq0q01tc3rnJTJGy7Ehj2EyCqMYR5y3PRWxUEXoYniJvTOy Z9cyE//zazj9I7urZ0hRZ6EGn17+jaV9EZwCPrrEAu6F2mmDvYvVfSwHWw0eX/5cIJl9 YSTJGvBvLc9tTgszfGuvfdfE2Lx7lRE6LlTuTXev4GXDuH8tijs/LNvko8dATrJpBGVD 2Zig4WdzNVEyiaV0/hxhJmx0wNrqLqhySjay7P9wyxBkL8gUKSkM4dd9VJqJoNFcmUKL WNbw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=wpET3lzcKB22iPNVtFlsEzKa/4+3mu1B+c0PsjFBF2Y=; b=KB9Gd1dZ505Mhf5c7AE9fUDOLu4Q2fVyO+3X//toUvZB6PTwzcryvM2kHLOuC+OIrH OlE0G6jAKYn5Ukv4eOrjRvXP/eqA4//4UXco4m2vCr9HibOxTzTrj3kJj/WorH2cqZy7 IZDvsNJFCSqBm1dz9b8qFbEbkmgrbgrikRDhS5s0/YLYJm/Ywkxd+s8k17d9vZRGGr8Z L3SaXGgsAvgCBp/AQiNnE7gqeXAOIN4ooKMZ7QXUkau9CHjK70NEPXrA2VDz4voUUbgV Vb+6rdin2/BTRRLeStw/kDWNqXDRQ5MJm1sC/hWegxpH6AsajtCODnLeG9MZiyqYyZhr IeMg== X-Gm-Message-State: APjAAAUA4dGwMRUWWM1C9+lb8Q1Z0O7t2jm6cVTB/GfS7fvXTm38uCvW DkEQVRJY5uEvZ8L3JO6f3FwNis3fQCl29t6O9ScpdA== X-Google-Smtp-Source: APXvYqz3MJp/sBrmbbRiZjO/ftHK7vNqXHLQbOsRURa/k0qxR5qT0IrWHea8c6wS0/ELwPU31n87vbWy4rBMSYT717o= X-Received: by 2002:aca:f5cc:: with SMTP id t195mr8715903oih.163.1575571210836; Thu, 05 Dec 2019 10:40:10 -0800 (PST) MIME-Version: 1.0 References: <20191011134744.2477-1-richard.henderson@linaro.org> <20191011134744.2477-21-richard.henderson@linaro.org> In-Reply-To: <20191011134744.2477-21-richard.henderson@linaro.org> From: Peter Maydell Date: Thu, 5 Dec 2019 18:40:00 +0000 Message-ID: Subject: Re: [PATCH v5 20/22] target/arm: Create tagged ram when MTE is enabled To: Richard Henderson Cc: QEMU Developers , qemu-arm Content-Type: text/plain; charset="UTF-8" X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::242 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 05 Dec 2019 18:40:17 -0000 On Fri, 11 Oct 2019 at 14:50, Richard Henderson wrote: > > Signed-off-by: Richard Henderson > --- > v5: Assign cs->num_ases to the final value first. > Downgrade to ID_AA64PFR1.MTE=1 if tag memory is not available. > v6: Add secure tag memory for EL3. > --- > target/arm/cpu.h | 6 ++++++ > hw/arm/virt.c | 54 ++++++++++++++++++++++++++++++++++++++++++++++++ > target/arm/cpu.c | 53 ++++++++++++++++++++++++++++++++++++++++++++--- > 3 files changed, 110 insertions(+), 3 deletions(-) > > diff --git a/target/arm/cpu.h b/target/arm/cpu.h > index 93a362708b..faca43ea78 100644 > --- a/target/arm/cpu.h > +++ b/target/arm/cpu.h > @@ -765,6 +765,10 @@ struct ARMCPU { > /* MemoryRegion to use for secure physical accesses */ > MemoryRegion *secure_memory; > > + /* MemoryRegion to use for allocation tag accesses */ > + MemoryRegion *tag_memory; > + MemoryRegion *secure_tag_memory; > + > /* For v8M, pointer to the IDAU interface provided by board/SoC */ > Object *idau; > > @@ -2956,6 +2960,8 @@ int cpu_mmu_index(CPUARMState *env, bool ifetch); > typedef enum ARMASIdx { > ARMASIdx_NS = 0, > ARMASIdx_S = 1, > + ARMASIdx_TagNS = 2, > + ARMASIdx_TagS = 3, > } ARMASIdx; > > /* Return the Exception Level targeted by debug exceptions. */ > diff --git a/hw/arm/virt.c b/hw/arm/virt.c > index d74538b021..573988ba4d 100644 > --- a/hw/arm/virt.c > +++ b/hw/arm/virt.c > @@ -1330,6 +1330,18 @@ static void create_secure_ram(VirtMachineState *vms, > g_free(nodename); > } > > +static void create_tag_ram(MemoryRegion *tag_sysmem, > + hwaddr base, hwaddr size, > + const char *name) > +{ > + MemoryRegion *tagram = g_new(MemoryRegion, 1); > + > + memory_region_init_ram(tagram, NULL, name, size / 32, &error_fatal); > + memory_region_add_subregion(tag_sysmem, base / 32, tagram); > + > + /* ??? Do we really need an fdt entry, or is MemTag enabled sufficient. */ What's this '???' asking about? I would be surprised if the kernel expected to have any kind of FDT for tag RAM (with the exception that an implementation that puts tags in a special part of normal-ram will want that not to be described in the fdt as ram usable by the kernel), but we should ask the kernel folks. > +} > + > static void *machvirt_dtb(const struct arm_boot_info *binfo, int *fdt_size) > { > const VirtMachineState *board = container_of(binfo, VirtMachineState, > @@ -1485,6 +1497,8 @@ static void machvirt_init(MachineState *machine) > qemu_irq pic[NUM_IRQS]; > MemoryRegion *sysmem = get_system_memory(); > MemoryRegion *secure_sysmem = NULL; > + MemoryRegion *tag_sysmem = NULL; > + MemoryRegion *secure_tag_sysmem = NULL; > int n, virt_max_cpus; > MemoryRegion *ram = g_new(MemoryRegion, 1); > bool firmware_loaded; > @@ -1652,6 +1666,35 @@ static void machvirt_init(MachineState *machine) > "secure-memory", &error_abort); > } > > + /* > + * The cpu adds the property iff MemTag is supported. We've had confusion before from non-native-speakers and non-maths-geeks about 'iff' in comments; better to expand to 'if and only if'. > + * If it is, we must allocate the ram to back that up. > + */ > + if (object_property_find(cpuobj, "tag-memory", NULL)) { > + if (!tag_sysmem) { > + tag_sysmem = g_new(MemoryRegion, 1); > + memory_region_init(tag_sysmem, OBJECT(machine), > + "tag-memory", UINT64_MAX / 32); > + > + if (vms->secure) { > + secure_tag_sysmem = g_new(MemoryRegion, 1); > + memory_region_init(secure_tag_sysmem, OBJECT(machine), > + "secure-tag-memory", UINT64_MAX / 32); > + > + /* As with ram, secure-tag takes precedence over tag. */ > + memory_region_add_subregion_overlap(secure_tag_sysmem, 0, > + tag_sysmem, -1); > + } > + } Are there really separate S and NS tag RAMs? thanks -- PMM From MAILER-DAEMON Thu Dec 05 13:58:41 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1icwKn-0006zq-H2 for mharc-qemu-arm@gnu.org; Thu, 05 Dec 2019 13:58:41 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:44585) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1icwKl-0006zN-Uq for qemu-arm@nongnu.org; Thu, 05 Dec 2019 13:58:40 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1icwKi-0003xo-GU for qemu-arm@nongnu.org; Thu, 05 Dec 2019 13:58:38 -0500 Received: from mail-oi1-x241.google.com ([2607:f8b0:4864:20::241]:35063) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1icwKg-0003uf-CK for qemu-arm@nongnu.org; Thu, 05 Dec 2019 13:58:36 -0500 Received: by mail-oi1-x241.google.com with SMTP id k196so3771930oib.2 for ; Thu, 05 Dec 2019 10:58:32 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=AEQI4xHNIqMIIegnskaMD5l3+ExBopVS61N6I2vC0DI=; b=N32gbZ2VEtN1AHvzpjEXiZx4Ufd7FLblT6aZPLL0RX9jZhF+HfkH7WHvz20n5EUjl5 hcyYU30R+uZIPoq68oSlvUl7U8xqwB1R8WtdWlFybSSvIp+CrIOws8yuPJRAHiucfOKU 5hYFYJTQw1dmhC8vwi0n6L/gLPua22W5v/ca8cj1FBatZjwitlygXg6RJkOz9QlCyIUk lYWHEQATshFkx2oGQFukvjfrxKqobGsm/N8nTOo5d1dRX2nqt4CWW+KwTTz2vxuGov6w t2HjmPRFtMjoP9IhTIcdlSFOWNFlFLEdpWJpFBBljkA83BnwSFZ6Offx4MNa5Blz4x48 wSwA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=AEQI4xHNIqMIIegnskaMD5l3+ExBopVS61N6I2vC0DI=; b=gmkWftreNAzpwSifpYJV/+iaNUIY+kdqDhw4BGT469WB6EYsJrgYBk0LUuFzl2vg3f wEiJNN2orzqg6dYPyWK0DGUzuhTuoafMcdCvDFRlaX7J8L1fqFkyATfWWRBm+S1K9xnr 0y1yiuSDJ98rDlIJVk9wpzbbaNtbAj38/TZE1BTNqOkyqJtAE5DlPcr/vTH7UVjHz2xf 091vf2Q9LdY8IiLWvfaJogAMK4OqsKXP94vli/T6BOR+JJi2RWlmP2Omx3jVtU2wX6eX N3F8FNMwMAf0c9R1eqvtxAPeYVsGiNmfXljCLMpmkiZiH54JXDrTUpUw0EoObN53LMgR k79A== X-Gm-Message-State: APjAAAUvcWofG6iySJD/Gwp+NVAB1fEZLsnhPqx8X5+cxSEiIAB1bCJn yBw/3kpszs59gyNxEyx4BX1eyNA3/d6lPmirAFsihg== X-Google-Smtp-Source: APXvYqw/AISrj/43VSH6spRMT8kKxwzOMJTGiR6VxBuZ2Y0SNwLSjenNeiDz9BmnsUe6Pe2diizbucxV8pbkwu54Msk= X-Received: by 2002:aca:f484:: with SMTP id s126mr8226827oih.48.1575572312105; Thu, 05 Dec 2019 10:58:32 -0800 (PST) MIME-Version: 1.0 References: <20191011134744.2477-1-richard.henderson@linaro.org> <20191011134744.2477-16-richard.henderson@linaro.org> In-Reply-To: <20191011134744.2477-16-richard.henderson@linaro.org> From: Peter Maydell Date: Thu, 5 Dec 2019 18:58:21 +0000 Message-ID: Subject: Re: [PATCH v5 15/22] target/arm: Clean address for DC ZVA To: Richard Henderson Cc: QEMU Developers , qemu-arm Content-Type: text/plain; charset="UTF-8" X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::241 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 05 Dec 2019 18:58:41 -0000 On Fri, 11 Oct 2019 at 14:50, Richard Henderson wrote: > > This data access was forgotten in the previous patch. > > Fixes: 3a471103ac1823ba > Signed-off-by: Richard Henderson > --- > target/arm/translate-a64.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c > index 4e049bb4aa..49817b96ae 100644 > --- a/target/arm/translate-a64.c > +++ b/target/arm/translate-a64.c > @@ -1766,7 +1766,7 @@ static void handle_sys(DisasContext *s, uint32_t insn, bool isread, > return; > case ARM_CP_DC_ZVA: > /* Writes clear the aligned block of memory which rt points into. */ > - tcg_rt = cpu_reg(s, rt); > + tcg_rt = clean_data_tbi(s, cpu_reg(s, rt), false); > gen_helper_dc_zva(cpu_env, tcg_rt); > return; ...doesn't this mean we don't do a tag check for DC ZVA? Or is that handled in the helper ? (I guess it has to be, the DC ZVA will span multiple tag granules). thanks -- PMM From MAILER-DAEMON Thu Dec 05 14:25:00 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1icwkG-0003Hw-4f for mharc-qemu-arm@gnu.org; Thu, 05 Dec 2019 14:25:00 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:34896) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1icwkE-0003Hg-3X for qemu-arm@nongnu.org; Thu, 05 Dec 2019 14:24:58 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1icwkC-00050w-7s for qemu-arm@nongnu.org; Thu, 05 Dec 2019 14:24:57 -0500 Received: from mail-pg1-x541.google.com ([2607:f8b0:4864:20::541]:35161) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1icwkB-0004vr-I4 for qemu-arm@nongnu.org; Thu, 05 Dec 2019 14:24:55 -0500 Received: by mail-pg1-x541.google.com with SMTP id l24so2054854pgk.2 for ; Thu, 05 Dec 2019 11:24:55 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=subject:to:cc:references:from:message-id:date:user-agent :mime-version:in-reply-to:content-language:content-transfer-encoding; bh=hGPCjxihMUhKShcKlyxjNO+KotcaAPS/t36MNL94j40=; b=sCuRL7FNZbTsQZUuct5ez9ifzZWjyGajs5TFVPs/77bFu1207pMfPoGnNZoMpv8Jux F03/9NTrZ3ZT5R46NN9y76rTJKRuMTnU0Qu3YAD5JF8c/c4WuN1etVYR76lz2fJmBoS0 mqZnM4n8EJP2pY4Wh/Kyz42XxEj4T0SEFMfBNbS6rSZNuU07SIRa8E5PRdHLp5HcEGKw jBgyc4kjWxzVvqdlIqrQvI97pvee1aezsSgF/SvOcmnarzItthIvAPFrFZNq14SDs1nP HQHoQSZ+MFZ0ZA3isDdOgVQS8Vs9v737DAj6JIzA7C/34sXNGO/gf9Sq9pinmFtpcOx/ ewgg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:subject:to:cc:references:from:message-id:date :user-agent:mime-version:in-reply-to:content-language :content-transfer-encoding; bh=hGPCjxihMUhKShcKlyxjNO+KotcaAPS/t36MNL94j40=; b=k9FbJSnzxnWG1Hp3mJiGRhUzOmrMLS5/To/QV7Xwl547bCCH68ZOgSFYcLPE4NqZyx YRP/3Cj+LBV6Glg/qZmGPdD9XVG4Lac/tuKsFGvjjt6cjSMEXQ3fYiQJlsfjbW6ZZPDM th93GKEfuDeD6oEbqPUqZcMMgwHPKOyb9D67GYuE2DhVkZH4LeXu8KCtjLoO3BtRznYS 5vittkT8cYnIT87/CAW79UpKj0FUo4bG1+8+oo/QEU3xCsiCPYtBRehtoUd9QO1cw+Ki IoC+s+7EyzUJ1/bagyhjw0clhVXHchh6DKpFz6WROz+qvJAs6n6vatTJFI86tG8kEUcc F7Zg== X-Gm-Message-State: APjAAAUS5w9GBIF9GlmwmdfrBRT4n/kKH76MsDxAKmW5e78fz3RcVkTU K6O+msnQTU6fTpGenGobDlK6Q9PcOgU= X-Google-Smtp-Source: APXvYqwa2JsImEpiPb1m2YgHmy9qu9dIPjnjWlmq7Bg7buy+yDAv99C8WudrjKFlTgvckeGfA8sNvA== X-Received: by 2002:a65:5307:: with SMTP id m7mr11219160pgq.113.1575573893805; Thu, 05 Dec 2019 11:24:53 -0800 (PST) Received: from [192.168.1.11] (97-113-7-119.tukw.qwest.net. [97.113.7.119]) by smtp.gmail.com with ESMTPSA id k16sm14110816pfh.97.2019.12.05.11.24.51 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 05 Dec 2019 11:24:52 -0800 (PST) Subject: Re: [PATCH v5 20/22] target/arm: Create tagged ram when MTE is enabled To: Peter Maydell Cc: QEMU Developers , qemu-arm References: <20191011134744.2477-1-richard.henderson@linaro.org> <20191011134744.2477-21-richard.henderson@linaro.org> From: Richard Henderson Message-ID: Date: Thu, 5 Dec 2019 11:24:50 -0800 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.2.1 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 7bit X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::541 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 05 Dec 2019 19:24:59 -0000 On 12/5/19 10:40 AM, Peter Maydell wrote: >> + * If it is, we must allocate the ram to back that up. >> + */ >> + if (object_property_find(cpuobj, "tag-memory", NULL)) { >> + if (!tag_sysmem) { >> + tag_sysmem = g_new(MemoryRegion, 1); >> + memory_region_init(tag_sysmem, OBJECT(machine), >> + "tag-memory", UINT64_MAX / 32); >> + >> + if (vms->secure) { >> + secure_tag_sysmem = g_new(MemoryRegion, 1); >> + memory_region_init(secure_tag_sysmem, OBJECT(machine), >> + "secure-tag-memory", UINT64_MAX / 32); >> + >> + /* As with ram, secure-tag takes precedence over tag. */ >> + memory_region_add_subregion_overlap(secure_tag_sysmem, 0, >> + tag_sysmem, -1); >> + } >> + } > > Are there really separate S and NS tag RAMs? Implementation defined, I believe. As with everything about tag storage, it would seem. But since there are separate S and NS normal RAMS, I create separate tag spaces to match. r~ From MAILER-DAEMON Thu Dec 05 14:36:37 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1icwvV-0008Sm-P7 for mharc-qemu-arm@gnu.org; Thu, 05 Dec 2019 14:36:37 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:50840) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1icwvS-0008QI-PE for qemu-arm@nongnu.org; Thu, 05 Dec 2019 14:36:35 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1icwvR-0005lQ-9v for qemu-arm@nongnu.org; Thu, 05 Dec 2019 14:36:34 -0500 Received: from mail-pf1-x443.google.com ([2607:f8b0:4864:20::443]:45067) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1icwvQ-0005ev-Tq for qemu-arm@nongnu.org; Thu, 05 Dec 2019 14:36:33 -0500 Received: by mail-pf1-x443.google.com with SMTP id 2so2063888pfg.12 for ; Thu, 05 Dec 2019 11:36:30 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=subject:to:cc:references:from:message-id:date:user-agent :mime-version:in-reply-to:content-language:content-transfer-encoding; bh=+wif4h4CRxcxxjYAPak4RRxF1JnlVEgWYO5ih4Y0pfY=; b=SqUaMfXFSihNvxOnqqn7pBDj/km17ZmaTt2ghEyxmNKVReuGMXYwRwFbm7AF+Tfm2S OQX2YmzuBWoZoOgGvqlZXaaUyv4IWDvSX8GhvCTLbxqGUE+O7i+MRABgkBLJadN/xzNB VIui/zF5+z5N9+yG+x9usNyvNCTwdLX26TTyf2KixlqQa8Zjy6CTnr3fphZ6vF+3N+zs SrTbzJsdqyc8sczMRWBsh5fFRKQFqwxW1jRROEeR/vNFnc6Sd0k8kQlqoWfP/a18Hqrf upqqdOzQ0i7XcTsYmrWjIQ8cfXoMl5NE3yniNLYfECx2C6EOM1PCTTOCfDTVH5G6r0Hj yUOw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:subject:to:cc:references:from:message-id:date :user-agent:mime-version:in-reply-to:content-language :content-transfer-encoding; bh=+wif4h4CRxcxxjYAPak4RRxF1JnlVEgWYO5ih4Y0pfY=; b=NnQhGUOrYz0uJZEZqd9UzbZSZK4yH5Cwgo0Dk2mwItpy41GuiyyHlaksVFGQEvgPmT uPgi4epSjmv0xm+NydI+5P6uww9S1HwKb2Svo3ORlmOV2XvNzS7/fFpvIPUFH6iG6JVo zHoeZ3USGb7AoGl/saxBCD40MTcSaXpf+hTzl9LLuSI7KfwkhxB0DxNDKKLXPLhpdO7C 4c0NEFMKQAMcPCXl474EnKRXu9J4m8kKLofXcC8Lk1PErTBjFj5mokSXYfWbbxNVA7fo YBW/lFO78ar7RKLEELvuhR8Ii2W25tU7rqvN6XI2/I1KsbDbDBR4imnH5qrLg3Vm7n98 j+dw== X-Gm-Message-State: APjAAAXdPJr09ghB0UfOALHE85Mei/rxBWU0J4ptgs6XlQ04RfDSGDC1 Q46GXP0m0GdXd/5yjRnn4f/agBJ8FoI= X-Google-Smtp-Source: APXvYqyEQ8RZvjSBrBG4nwRogjPgebId2z/n0JyheG+9wEeMCqNdh8TPoFdVtVUThjYW4+VDiqITSQ== X-Received: by 2002:a63:2acc:: with SMTP id q195mr10878365pgq.26.1575574589524; Thu, 05 Dec 2019 11:36:29 -0800 (PST) Received: from [192.168.1.11] (97-113-7-119.tukw.qwest.net. [97.113.7.119]) by smtp.gmail.com with ESMTPSA id h3sm12499284pgr.81.2019.12.05.11.36.28 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 05 Dec 2019 11:36:28 -0800 (PST) Subject: Re: [PATCH v2 11/14] target/arm: default SVE length to 64 bytes for linux-user To: =?UTF-8?Q?Alex_Benn=c3=a9e?= Cc: qemu-devel@nongnu.org, alan.hayward@arm.com, luis.machado@linaro.org, damien.hedde@greensocs.com, Peter Maydell , "open list:ARM TCG CPUs" References: <20191130084602.10818-1-alex.bennee@linaro.org> <20191130084602.10818-12-alex.bennee@linaro.org> <9362663d-6452-39aa-2a8d-1cfd853d7faa@linaro.org> <87o8wm7k6v.fsf@linaro.org> From: Richard Henderson Message-ID: Date: Thu, 5 Dec 2019 11:36:26 -0800 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.2.1 MIME-Version: 1.0 In-Reply-To: <87o8wm7k6v.fsf@linaro.org> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 8bit X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::443 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 05 Dec 2019 19:36:36 -0000 On 12/5/19 9:31 AM, Alex Bennée wrote: > > Richard Henderson writes: > >> On 11/30/19 8:45 AM, Alex Bennée wrote: >>> The Linux kernel chooses the default of 64 bytes for SVE registers on >>> the basis that it is the largest size that won't grow the signal >>> frame. When debugging larger sizes are also unwieldy in gdb as each >>> zreg will take over a page of terminal to display. >>> >>> The user can of course always specify a larger size with the >>> sve-max-vq property on the command line: >>> >>> -cpu max,sve-max-vq=16 >>> >>> This should not make any difference to SVE enabled software as the SVE >>> is of course vector length agnostic. >>> >>> Signed-off-by: Alex Bennée >>> --- >>> target/arm/cpu64.c | 3 +++ >>> 1 file changed, 3 insertions(+) >> >> 6 is the largest size that doesn't grow the signal frame. >> I imagine 4 was chosen because that's the only real hw atm. >> >>> + /* Default sve-max-vq to a reasonable numer */ >>> + cpu->sve_max_vq = 4; >> >> I also agree that we should match the kernel, but this is not the right way. >> Changing max vq is not the same as changing the default vq. >> >> You should change the value of env->vfp.zcr_el[1] in arm_cpu_reset(), and the >> user can increase the length with prctl(2) as they would be able to on real >> hardware that would have support for longer vector lengths. > > No the intention is to default to a lower max VQ because... > >> Also, I don't think you should mix this up with gdb stuff. > > it is what we use for sizing the registers for the gdbstub. The other > option would be to use the effective zcr_el1 value at the time of the > gdbstub connecting but then things will go horribly wrong if the user > execute a prctl and widens their size. Why would you care about the size of the registers as passed by default? You shouldn't need or want to change that default to make gdbstub work. The gdbstub should be passing along the vq value (via the "vg" pseudo-register, iirc), and gdb should be working out what to display based on that. If that isn't happening, and you are only changing the default so that gdb quits displaying massive registers when they aren't in use, then you're doing something wrong with gdb and gdbstub. r~ From MAILER-DAEMON Thu Dec 05 17:05:21 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1iczFR-0006FR-3X for mharc-qemu-arm@gnu.org; Thu, 05 Dec 2019 17:05:21 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:46655) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iczFL-0006DM-5q for qemu-arm@nongnu.org; Thu, 05 Dec 2019 17:05:16 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1iczFI-0007nw-Lr for qemu-arm@nongnu.org; Thu, 05 Dec 2019 17:05:14 -0500 Received: from smtp-fw-2101.amazon.com ([72.21.196.25]:16889) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1iczFA-0007ib-6y; Thu, 05 Dec 2019 17:05:07 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; 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Thu, 05 Dec 2019 17:16:14 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:39383) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iczPq-0001rh-OE for qemu-arm@nongnu.org; Thu, 05 Dec 2019 17:16:10 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1iczPk-0001LN-LV for qemu-arm@nongnu.org; Thu, 05 Dec 2019 17:16:04 -0500 Received: from mail-il1-x141.google.com ([2607:f8b0:4864:20::141]:37838) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1iczPe-0000wC-Gd; Thu, 05 Dec 2019 17:15:54 -0500 Received: by mail-il1-x141.google.com with SMTP id t9so4463602iln.4; Thu, 05 Dec 2019 14:15:54 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=2s8WccqH0C1+PGklupS+pdXblcVhyHCjpleiPomaBK0=; b=n65rF2x2f0IRclgKMAadltc2vIdQIqaUhpWp9K+W+RU82IFFPcT93GGXdht9smRjxc h2dTz37GS0RvQXwx96Zhysq9wGLVUQEYPt6zC1/FM1BC2/45f8r0tzi/sJ+p5MnY6zMk F2cLUqOgzWA4/YqGB04fO+6iYnIrjnvRB6qamBuAL1uB6+eYyD8pwgyH4aIGZt9eKUmD rGjuh8Wr1NZb2S+wYrDioipk3Og5/jj5wl5atL1zwNR5lxvv4TMchAW9ZOSR3fDeoE+M Tztq8fy23u45QxvxdlXNaPqhyBm3YJdkHZNgtof67xaoJb3W5MjN6w1A0M7DraaWq9AQ m4KQ== X-Google-DKIM-Signature: v=1; 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boundary="000000000000c2c3f00598fc450d" X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::141 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 05 Dec 2019 22:16:10 -0000 --000000000000c2c3f00598fc450d Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Hello Philippe, On Tue, Dec 3, 2019 at 10:18 AM Philippe Mathieu-Daud=C3=A9 wrote: > On 12/2/19 10:09 PM, Niek Linnenbank wrote: > > The Xunlong Orange Pi PC is an Allwinner H3 System on Chip > > based embedded computer with mainline support in both U-Boot > > and Linux. The board comes with a Quad Core Cortex A7 @ 1.3GHz, > > 512MB RAM, 100Mbit ethernet, USB, SD/MMC, USB, HDMI and > > various other I/O. This commit add support for the Xunlong > > Orange Pi PC machine. > > > > Signed-off-by: Niek Linnenbank > > --- > > MAINTAINERS | 1 + > > hw/arm/Makefile.objs | 2 +- > > hw/arm/orangepi.c | 90 +++++++++++++++++++++++++++++++++++++++++++= + > > 3 files changed, 92 insertions(+), 1 deletion(-) > > create mode 100644 hw/arm/orangepi.c > > > > diff --git a/MAINTAINERS b/MAINTAINERS > > index 29c9936037..42c913d6cb 100644 > > --- a/MAINTAINERS > > +++ b/MAINTAINERS > > @@ -485,6 +485,7 @@ L: qemu-arm@nongnu.org > > S: Maintained > > F: hw/*/allwinner-h3* > > F: include/hw/*/allwinner-h3* > > +F: hw/arm/orangepi.c > > > > ARM PrimeCell and CMSDK devices > > M: Peter Maydell > > diff --git a/hw/arm/Makefile.objs b/hw/arm/Makefile.objs > > index 956e496052..8d5ea453d5 100644 > > --- a/hw/arm/Makefile.objs > > +++ b/hw/arm/Makefile.objs > > @@ -34,7 +34,7 @@ obj-$(CONFIG_DIGIC) +=3D digic.o > > obj-$(CONFIG_OMAP) +=3D omap1.o omap2.o > > obj-$(CONFIG_STRONGARM) +=3D strongarm.o > > obj-$(CONFIG_ALLWINNER_A10) +=3D allwinner-a10.o cubieboard.o > > -obj-$(CONFIG_ALLWINNER_H3) +=3D allwinner-h3.o > > +obj-$(CONFIG_ALLWINNER_H3) +=3D allwinner-h3.o orangepi.o > > obj-$(CONFIG_RASPI) +=3D bcm2835_peripherals.o bcm2836.o raspi.o > > obj-$(CONFIG_STM32F205_SOC) +=3D stm32f205_soc.o > > obj-$(CONFIG_XLNX_ZYNQMP_ARM) +=3D xlnx-zynqmp.o xlnx-zcu102.o > > diff --git a/hw/arm/orangepi.c b/hw/arm/orangepi.c > > new file mode 100644 > > index 0000000000..5ef2735f81 > > --- /dev/null > > +++ b/hw/arm/orangepi.c > > @@ -0,0 +1,90 @@ > > +/* > > + * Orange Pi emulation > > + * > > + * Copyright (C) 2019 Niek Linnenbank > > + * > > + * This program is free software: you can redistribute it and/or modif= y > > + * it under the terms of the GNU General Public License as published b= y > > + * the Free Software Foundation, either version 2 of the License, or > > + * (at your option) any later version. > > + * > > + * This program is distributed in the hope that it will be useful, > > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > > + * GNU General Public License for more details. > > + * > > + * You should have received a copy of the GNU General Public License > > + * along with this program. If not, see >. > > + */ > > + > > +#include "qemu/osdep.h" > > +#include "exec/address-spaces.h" > > +#include "qapi/error.h" > > +#include "cpu.h" > > +#include "hw/sysbus.h" > > +#include "hw/boards.h" > > +#include "hw/qdev-properties.h" > > +#include "hw/arm/allwinner-h3.h" > > + > > +static struct arm_boot_info orangepi_binfo =3D { > > + .loader_start =3D AW_H3_SDRAM_BASE, > > + .board_id =3D -1, > > +}; > > + > > +typedef struct OrangePiState { > > + AwH3State *h3; > > + MemoryRegion sdram; > > +} OrangePiState; > > + > > +static void orangepi_init(MachineState *machine) > > +{ > > + OrangePiState *s =3D g_new(OrangePiState, 1); > > + Error *err =3D NULL; > > + > > Here I'd add: > > if (strcmp(machine->cpu_type, ARM_CPU_TYPE_NAME("cortex-a7")) !=3D= 0) > { > error_report("This board can only be used with cortex-a7 CPU")= ; > exit(1); > } > > Done! > + s->h3 =3D AW_H3(object_new(TYPE_AW_H3)); > > + > > + /* Setup timer properties */ > > + object_property_set_int(OBJECT(&s->h3->timer), 32768, "clk0-freq", > &err); > > + if (err !=3D NULL) { > > + error_reportf_err(err, "Couldn't set clk0 frequency: "); > > + exit(1); > > + } > > + > > + object_property_set_int(OBJECT(&s->h3->timer), 24000000, > "clk1-freq", > > + &err); > > + if (err !=3D NULL) { > > + error_reportf_err(err, "Couldn't set clk1 frequency: "); > > + exit(1); > > + } > > + > > + /* Mark H3 object realized */ > > + object_property_set_bool(OBJECT(s->h3), true, "realized", &err); > > I'm not sure if that's correct but I'd simply use &error_abort here. > > Done, I applied it to all the functions and removed the err variable. > + if (err !=3D NULL) { > > + error_reportf_err(err, "Couldn't realize Allwinner H3: "); > > + exit(1); > > + } > > + > > + /* RAM */ > > + memory_region_allocate_system_memory(&s->sdram, NULL, > "orangepi.ram", > > + machine->ram_size); > > I'd only allow machine->ram_size =3D=3D 1 * GiB here, since the onboard D= RAM > is not upgradable. > Agree, we should add something for that. Would it be acceptable if we make the 1GB an upper limit? I see that the Raspberry Pi is doing that too in hw/arm/raspi.c, like so: if (machine->ram_size > 1 * GiB) { error_report("Requested ram size is too large for this machine: " "maximum is 1GB"); exit(1); } I think it would be helpful to allow the flexibility to the user of reducing the RAM to less than 1GB, in case resources of the host OS are limited. What do you think? > > + memory_region_add_subregion(get_system_memory(), AW_H3_SDRAM_BASE, > > + &s->sdram); > > + > > + /* Load target kernel */ > > + orangepi_binfo.ram_size =3D machine->ram_size; > > + orangepi_binfo.nb_cpus =3D AW_H3_NUM_CPUS; > > + arm_load_kernel(ARM_CPU(first_cpu), machine, &orangepi_binfo); > > +} > > + > > +static void orangepi_machine_init(MachineClass *mc) > > +{ > > + mc->desc =3D "Orange Pi PC"; > > + mc->init =3D orangepi_init; > > + mc->units_per_default_bus =3D 1; > > + mc->min_cpus =3D AW_H3_NUM_CPUS; > > + mc->max_cpus =3D AW_H3_NUM_CPUS; > > + mc->default_cpus =3D AW_H3_NUM_CPUS; > > mc->default_cpu_type =3D ARM_CPU_TYPE_NAME("cortex-a7"); > > > + mc->ignore_memory_transaction_failures =3D true; > > You should not use this flag in new design. See the documentation in > include/hw/boards.h: > > * @ignore_memory_transaction_failures: > * [...] New board models > * should instead use "unimplemented-device" for all memory ranges > where > * the guest will attempt to probe for a device that QEMU doesn't > * implement and a stub device is required. > > You already use the "unimplemented-device". > > Thanks, I'm working on this now. I think that at least I'll need to add all of the devices mentioned in the 4.1 Memory Mapping chapter of the datasheet as an unimplemented device. Previously I only added some that I thought were relevant. I added all the missing devices as unimplemented and removed the ignore_memory_transaction_failures flag from the machine. Now it seems Linux gets a data abort while probing the uart1 serial device at 0x01c28400, so I'll need to debug it further. I'll post back when I have more results. Regards, Niek > > +} > > + > > +DEFINE_MACHINE("orangepi", orangepi_machine_init) > > Can you name it 'orangepi-pc'? So we can add other orangepi models. > > Thanks, > > Phil. > > --=20 Niek Linnenbank --000000000000c2c3f00598fc450d Content-Type: text/html; charset="UTF-8" Content-Transfer-Encoding: quoted-printable
Hello Philippe,

On Tue, Dec 3, 2019 at 10:18 AM Ph= ilippe Mathieu-Daud=C3=A9 <philmd@r= edhat.com> wrote:
On 12/2/19 10:09 PM, Niek Linnenbank wrote:
> The Xunlong Orange Pi PC is an Allwinner H3 System on Chip
> based embedded computer with mainline support in both U-Boot
> and Linux. The board comes with a Quad Core Cortex A7 @ 1.3GHz,
> 512MB RAM, 100Mbit ethernet, USB, SD/MMC, USB, HDMI and
> various other I/O. This commit add support for the Xunlong
> Orange Pi PC machine.
>
> Signed-off-by: Niek Linnenbank <nieklinnenbank@gmail.com>
> ---
>=C2=A0 =C2=A0MAINTAINERS=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 |=C2=A0 1 +<= br> >=C2=A0 =C2=A0hw/arm/Makefile.objs |=C2=A0 2 +-
>=C2=A0 =C2=A0hw/arm/orangepi.c=C2=A0 =C2=A0 | 90 ++++++++++++++++++++++= ++++++++++++++++++++++
>=C2=A0 =C2=A03 files changed, 92 insertions(+), 1 deletion(-)
>=C2=A0 =C2=A0create mode 100644 hw/arm/orangepi.c
>
> diff --git a/MAINTAINERS b/MAINTAINERS
> index 29c9936037..42c913d6cb 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -485,6 +485,7 @@ L: qemu-arm@nongnu.org
>=C2=A0 =C2=A0S: Maintained
>=C2=A0 =C2=A0F: hw/*/allwinner-h3*
>=C2=A0 =C2=A0F: include/hw/*/allwinner-h3*
> +F: hw/arm/orangepi.c
>=C2=A0 =C2=A0
>=C2=A0 =C2=A0ARM PrimeCell and CMSDK devices
>=C2=A0 =C2=A0M: Peter Maydell <peter.maydell@linaro.org>
> diff --git a/hw/arm/Makefile.objs b/hw/arm/Makefile.objs
> index 956e496052..8d5ea453d5 100644
> --- a/hw/arm/Makefile.objs
> +++ b/hw/arm/Makefile.objs
> @@ -34,7 +34,7 @@ obj-$(CONFIG_DIGIC) +=3D digic.o
>=C2=A0 =C2=A0obj-$(CONFIG_OMAP) +=3D omap1.o omap2.o
>=C2=A0 =C2=A0obj-$(CONFIG_STRONGARM) +=3D strongarm.o
>=C2=A0 =C2=A0obj-$(CONFIG_ALLWINNER_A10) +=3D allwinner-a10.o cubieboar= d.o
> -obj-$(CONFIG_ALLWINNER_H3) +=3D allwinner-h3.o
> +obj-$(CONFIG_ALLWINNER_H3) +=3D allwinner-h3.o orangepi.o
>=C2=A0 =C2=A0obj-$(CONFIG_RASPI) +=3D bcm2835_peripherals.o bcm2836.o r= aspi.o
>=C2=A0 =C2=A0obj-$(CONFIG_STM32F205_SOC) +=3D stm32f205_soc.o
>=C2=A0 =C2=A0obj-$(CONFIG_XLNX_ZYNQMP_ARM) +=3D xlnx-zynqmp.o xlnx-zcu1= 02.o
> diff --git a/hw/arm/orangepi.c b/hw/arm/orangepi.c
> new file mode 100644
> index 0000000000..5ef2735f81
> --- /dev/null
> +++ b/hw/arm/orangepi.c
> @@ -0,0 +1,90 @@
> +/*
> + * Orange Pi emulation
> + *
> + * Copyright (C) 2019 Niek Linnenbank <nieklinnenbank@gmail.com>
> + *
> + * This program is free software: you can redistribute it and/or modi= fy
> + * it under the terms of the GNU General Public License as published = by
> + * the Free Software Foundation, either version 2 of the License, or<= br> > + * (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful, > + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.=C2=A0 See the=
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License<= br> > + * along with this program.=C2=A0 If not, see <http://www.gnu.o= rg/licenses/>.
> + */
> +
> +#include "qemu/osdep.h"
> +#include "exec/address-spaces.h"
> +#include "qapi/error.h"
> +#include "cpu.h"
> +#include "hw/sysbus.h"
> +#include "hw/boards.h"
> +#include "hw/qdev-properties.h"
> +#include "hw/arm/allwinner-h3.h"
> +
> +static struct arm_boot_info orangepi_binfo =3D {
> +=C2=A0 =C2=A0 .loader_start =3D AW_H3_SDRAM_BASE,
> +=C2=A0 =C2=A0 .board_id =3D -1,
> +};
> +
> +typedef struct OrangePiState {
> +=C2=A0 =C2=A0 AwH3State *h3;
> +=C2=A0 =C2=A0 MemoryRegion sdram;
> +} OrangePiState;
> +
> +static void orangepi_init(MachineState *machine)
> +{
> +=C2=A0 =C2=A0 OrangePiState *s =3D g_new(OrangePiState, 1);
> +=C2=A0 =C2=A0 Error *err =3D NULL;
> +

Here I'd add:

=C2=A0 =C2=A0 =C2=A0 =C2=A0if (strcmp(machine->cpu_type, ARM_CPU_TYPE_NA= ME("cortex-a7")) !=3D 0) {
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0error_report("This board can = only be used with cortex-a7 CPU");
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0exit(1);
=C2=A0 =C2=A0 =C2=A0 =C2=A0}

Done!

> +=C2=A0 =C2=A0 s->h3 =3D AW_H3(object_new(TYPE_AW_H3));
> +
> +=C2=A0 =C2=A0 /* Setup timer properties */
> +=C2=A0 =C2=A0 object_property_set_int(OBJECT(&s->h3->timer)= , 32768, "clk0-freq", &err);
> +=C2=A0 =C2=A0 if (err !=3D NULL) {
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 error_reportf_err(err, "Couldn't= set clk0 frequency: ");
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 exit(1);
> +=C2=A0 =C2=A0 }
> +
> +=C2=A0 =C2=A0 object_property_set_int(OBJECT(&s->h3->timer)= , 24000000, "clk1-freq",
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0 =C2=A0 =C2=A0 &err);
> +=C2=A0 =C2=A0 if (err !=3D NULL) {
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 error_reportf_err(err, "Couldn't= set clk1 frequency: ");
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 exit(1);
> +=C2=A0 =C2=A0 }
> +
> +=C2=A0 =C2=A0 /* Mark H3 object realized */
> +=C2=A0 =C2=A0 object_property_set_bool(OBJECT(s->h3), true, "= realized", &err);

I'm not sure if that's correct but I'd simply use &error_ab= ort here.

Done, I applied it to all the functions and removed t= he err variable.

> +=C2=A0 =C2=A0 if (err !=3D NULL) {
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 error_reportf_err(err, "Couldn't= realize Allwinner H3: ");
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 exit(1);
> +=C2=A0 =C2=A0 }
> +
> +=C2=A0 =C2=A0 /* RAM */
> +=C2=A0 =C2=A0 memory_region_allocate_system_memory(&s->sdram, = NULL, "orangepi.ram",
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0machine->ram_size);

I'd only allow machine->ram_size =3D=3D 1 * GiB here, since the onbo= ard DRAM
is not upgradable.

Agree, we should add= something for that. Would it be acceptable if we make the 1GB an upper lim= it?
I see that the Raspberry Pi is doing that too in hw/arm/raspi= .c, like so:

=C2=A0 =C2=A0 if (machine->ram_siz= e > 1 * GiB) {
=C2=A0 =C2=A0 =C2=A0 =C2=A0 error_report("Request= ed ram size is too large for this machine: "
=C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0"maximum is 1GB= ");
=C2=A0 =C2=A0 =C2=A0 =C2=A0 exit(1);
=C2=A0 =C2=A0 }

I think it would be helpful to allow the flexibility to t= he user of reducing the RAM to less than 1GB,
in case resources o= f the host OS are limited. What do you think?
=C2=A0


> +=C2=A0 =C2=A0 memory_region_add_subregion(get_system_memory(), AW_H3_= SDRAM_BASE,
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 &s->sdram);
> +
> +=C2=A0 =C2=A0 /* Load target kernel */
> +=C2=A0 =C2=A0 orangepi_binfo.ram_size =3D machine->ram_size;
> +=C2=A0 =C2=A0 orangepi_binfo.nb_cpus=C2=A0 =3D AW_H3_NUM_CPUS;
> +=C2=A0 =C2=A0 arm_load_kernel(ARM_CPU(first_cpu), machine, &orang= epi_binfo);
> +}
> +
> +static void orangepi_machine_init(MachineClass *mc)
> +{
> +=C2=A0 =C2=A0 mc->desc =3D "Orange Pi PC";
> +=C2=A0 =C2=A0 mc->init =3D orangepi_init;
> +=C2=A0 =C2=A0 mc->units_per_default_bus =3D 1;
> +=C2=A0 =C2=A0 mc->min_cpus =3D AW_H3_NUM_CPUS;
> +=C2=A0 =C2=A0 mc->max_cpus =3D AW_H3_NUM_CPUS;
> +=C2=A0 =C2=A0 mc->default_cpus =3D AW_H3_NUM_CPUS;

=C2=A0 =C2=A0 =C2=A0 =C2=A0 mc->default_cpu_type =3D ARM_CPU_TYPE_NAME(&= quot;cortex-a7");

> +=C2=A0 =C2=A0 mc->ignore_memory_transaction_failures =3D true;

You should not use this flag in new design. See the documentation in
include/hw/boards.h:

=C2=A0 * @ignore_memory_transaction_failures:
=C2=A0 *=C2=A0 =C2=A0 [...] New board models
=C2=A0 *=C2=A0 =C2=A0 should instead use "unimplemented-device" f= or all memory ranges where
=C2=A0 *=C2=A0 =C2=A0 the guest will attempt to probe for a device that QEM= U doesn't
=C2=A0 *=C2=A0 =C2=A0 implement and a stub device is required.

You already use the "unimplemented-device".

Thanks, I'm working on this now. I think that at = least I'll need to add
all of the devices mentioned in the 4.= 1 Memory Mapping chapter of the datasheet
as an unimplemented dev= ice. Previously I only added some that I thought were relevant.
<= br>
I added all the missing devices as unimplemented and removed = the ignore_memory_transaction_failures flag
from the machine. Now= it seems Linux gets a data abort while probing the uart1 serial device at = 0x01c28400,
so I'll need to debug it further. I'll post b= ack when I have more results.

Regards,
N= iek

=C2=A0
> +}
> +
> +DEFINE_MACHINE("orangepi", orangepi_machine_init)

Can you name it 'orangepi-pc'? So we can add other orangepi models.=

Thanks,

Phil.



--
Niek Linnenbank

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Tsirkin" , Mark Cave-Ayland , "qemu-devel@nongnu.org" , Vincenzo Maffione , Marek Vasut , =?utf-8?B?TWFyYy1BbmRyw6kgTHVyZWF1?= , Alistair Francis , Pavel Dovgalyuk , Giuseppe Lettieri , Luigi Rizzo , David Gibson , Tony Krowiak , =?utf-8?B?RGFuaWVsIFAuIEJlcnJhbmfDqQ==?= , Xiao Guangrong , Pierre Morel , Wen Congyang , Jean-Christophe Dubois , Paolo Bonzini , Stefan Berger Subject: Re: [RFC v5 024/126] error: auto propagated local_err Thread-Topic: [RFC v5 024/126] error: auto propagated local_err Thread-Index: AQHVgE3c5dwPNEl0z0OyUhbNfTU1EqeqZpzagAFqo4D///+mMYAAWcgA///pCIA= Date: Thu, 5 Dec 2019 16:36:42 +0000 Message-ID: References: <20191011160552.22907-1-vsementsov@virtuozzo.com> <20191011160552.22907-25-vsementsov@virtuozzo.com> <87muc8p24w.fsf@dusky.pond.sub.org> <55393c08-5bda-8042-1a95-f350b3781d99@virtuozzo.com> <87d0d3c5k7.fsf@dusky.pond.sub.org> In-Reply-To: Accept-Language: ru-RU, en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-clientproxiedby: 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[88.21.103.182]) by smtp.gmail.com with ESMTPSA id e16sm2149845wme.35.2019.12.05.21.41.02 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 05 Dec 2019 21:41:03 -0800 (PST) Subject: Re: [PATCH 02/10] hw: arm: add Xunlong Orange Pi PC machine To: Niek Linnenbank Cc: qemu-devel@nongnu.org, b.galvani@gmail.com, Peter Maydell , qemu-arm@nongnu.org References: <20191202210947.3603-1-nieklinnenbank@gmail.com> <20191202210947.3603-3-nieklinnenbank@gmail.com> From: =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= Message-ID: Date: Fri, 6 Dec 2019 06:41:02 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.2.2 MIME-Version: 1.0 In-Reply-To: Content-Language: en-US X-MC-Unique: 0_yhLOiOMuGpnoMsnKf3Ng-1 X-Mimecast-Spam-Score: 0 Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 207.211.31.81 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 06 Dec 2019 05:41:14 -0000 On 12/5/19 11:15 PM, Niek Linnenbank wrote: > Hello Philippe, >=20 > On Tue, Dec 3, 2019 at 10:18 AM Philippe Mathieu-Daud=C3=A9=20 > > wrote: >=20 > On 12/2/19 10:09 PM, Niek Linnenbank wrote: > > The Xunlong Orange Pi PC is an Allwinner H3 System on Chip > > based embedded computer with mainline support in both U-Boot > > and Linux. The board comes with a Quad Core Cortex A7 @ 1.3GHz, > > 512MB RAM, 100Mbit ethernet, USB, SD/MMC, USB, HDMI and > > various other I/O. This commit add support for the Xunlong > > Orange Pi PC machine. > > > > Signed-off-by: Niek Linnenbank > > > --- > >=C2=A0 =C2=A0MAINTAINERS=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 |=C2=A0 = 1 + > >=C2=A0 =C2=A0hw/arm/Makefile.objs |=C2=A0 2 +- > >=C2=A0 =C2=A0hw/arm/orangepi.c=C2=A0 =C2=A0 | 90 > ++++++++++++++++++++++++++++++++++++++++++++ > >=C2=A0 =C2=A03 files changed, 92 insertions(+), 1 deletion(-) > >=C2=A0 =C2=A0create mode 100644 hw/arm/orangepi.c > > > > diff --git a/MAINTAINERS b/MAINTAINERS > > index 29c9936037..42c913d6cb 100644 > > --- a/MAINTAINERS > > +++ b/MAINTAINERS > > @@ -485,6 +485,7 @@ L: qemu-arm@nongnu.org > > >=C2=A0 =C2=A0S: Maintained > >=C2=A0 =C2=A0F: hw/*/allwinner-h3* > >=C2=A0 =C2=A0F: include/hw/*/allwinner-h3* > > +F: hw/arm/orangepi.c > > > >=C2=A0 =C2=A0ARM PrimeCell and CMSDK devices > >=C2=A0 =C2=A0M: Peter Maydell > > > diff --git a/hw/arm/Makefile.objs b/hw/arm/Makefile.objs > > index 956e496052..8d5ea453d5 100644 > > --- a/hw/arm/Makefile.objs > > +++ b/hw/arm/Makefile.objs > > @@ -34,7 +34,7 @@ obj-$(CONFIG_DIGIC) +=3D digic.o > >=C2=A0 =C2=A0obj-$(CONFIG_OMAP) +=3D omap1.o omap2.o > >=C2=A0 =C2=A0obj-$(CONFIG_STRONGARM) +=3D strongarm.o > >=C2=A0 =C2=A0obj-$(CONFIG_ALLWINNER_A10) +=3D allwinner-a10.o cubie= board.o > > -obj-$(CONFIG_ALLWINNER_H3) +=3D allwinner-h3.o > > +obj-$(CONFIG_ALLWINNER_H3) +=3D allwinner-h3.o orangepi.o > >=C2=A0 =C2=A0obj-$(CONFIG_RASPI) +=3D bcm2835_peripherals.o bcm2836= .o raspi.o > >=C2=A0 =C2=A0obj-$(CONFIG_STM32F205_SOC) +=3D stm32f205_soc.o > >=C2=A0 =C2=A0obj-$(CONFIG_XLNX_ZYNQMP_ARM) +=3D xlnx-zynqmp.o xlnx-= zcu102.o > > diff --git a/hw/arm/orangepi.c b/hw/arm/orangepi.c > > new file mode 100644 > > index 0000000000..5ef2735f81 > > --- /dev/null > > +++ b/hw/arm/orangepi.c > > @@ -0,0 +1,90 @@ > > +/* > > + * Orange Pi emulation > > + * > > + * Copyright (C) 2019 Niek Linnenbank > > > + * > > + * This program is free software: you can redistribute it and/or > modify > > + * it under the terms of the GNU General Public License as > published by > > + * the Free Software Foundation, either version 2 of the License,= or > > + * (at your option) any later version. > > + * > > + * This program is distributed in the hope that it will be useful= , > > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.=C2=A0 See= the > > + * GNU General Public License for more details. > > + * > > + * You should have received a copy of the GNU General Public Lice= nse > > + * along with this program.=C2=A0 If not, see > . > > + */ > > + > > +#include "qemu/osdep.h" > > +#include "exec/address-spaces.h" > > +#include "qapi/error.h" > > +#include "cpu.h" > > +#include "hw/sysbus.h" > > +#include "hw/boards.h" > > +#include "hw/qdev-properties.h" > > +#include "hw/arm/allwinner-h3.h" > > + > > +static struct arm_boot_info orangepi_binfo =3D { > > +=C2=A0 =C2=A0 .loader_start =3D AW_H3_SDRAM_BASE, > > +=C2=A0 =C2=A0 .board_id =3D -1, > > +}; > > + > > +typedef struct OrangePiState { > > +=C2=A0 =C2=A0 AwH3State *h3; > > +=C2=A0 =C2=A0 MemoryRegion sdram; > > +} OrangePiState; > > + > > +static void orangepi_init(MachineState *machine) > > +{ > > +=C2=A0 =C2=A0 OrangePiState *s =3D g_new(OrangePiState, 1); > > +=C2=A0 =C2=A0 Error *err =3D NULL; > > + >=20 > Here I'd add: >=20 > =C2=A0 =C2=A0 =C2=A0 =C2=A0if (strcmp(machine->cpu_type, > ARM_CPU_TYPE_NAME("cortex-a7")) !=3D 0) { > =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0error_report("This board ca= n only be used with cortex-a7 > CPU"); > =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0exit(1); > =C2=A0 =C2=A0 =C2=A0 =C2=A0} >=20 > Done! >=20 > > +=C2=A0 =C2=A0 s->h3 =3D AW_H3(object_new(TYPE_AW_H3)); > > + > > +=C2=A0 =C2=A0 /* Setup timer properties */ > > +=C2=A0 =C2=A0 object_property_set_int(OBJECT(&s->h3->timer), 3276= 8, > "clk0-freq", &err); > > +=C2=A0 =C2=A0 if (err !=3D NULL) { > > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 error_reportf_err(err, "Couldn't set = clk0 frequency: "); > > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 exit(1); > > +=C2=A0 =C2=A0 } > > + > > +=C2=A0 =C2=A0 object_property_set_int(OBJECT(&s->h3->timer), 2400= 0000, > "clk1-freq", > > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 &err); > > +=C2=A0 =C2=A0 if (err !=3D NULL) { > > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 error_reportf_err(err, "Couldn't set = clk1 frequency: "); > > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 exit(1); > > +=C2=A0 =C2=A0 } > > + > > +=C2=A0 =C2=A0 /* Mark H3 object realized */ > > +=C2=A0 =C2=A0 object_property_set_bool(OBJECT(s->h3), true, "real= ized", &err); >=20 > I'm not sure if that's correct but I'd simply use &error_abort here. >=20 > Done, I applied it to all the functions and removed the err variable. >=20 > > +=C2=A0 =C2=A0 if (err !=3D NULL) { > > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 error_reportf_err(err, "Couldn't real= ize Allwinner H3: "); > > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 exit(1); > > +=C2=A0 =C2=A0 } > > + > > +=C2=A0 =C2=A0 /* RAM */ > > +=C2=A0 =C2=A0 memory_region_allocate_system_memory(&s->sdram, NUL= L, > "orangepi.ram", > > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0machine->ram_size); >=20 > I'd only allow machine->ram_size =3D=3D 1 * GiB here, since the onboa= rd > DRAM > is not upgradable. >=20 >=20 > Agree, we should add something for that. Would it be acceptable if we=20 > make the 1GB an upper limit? > I see that the Raspberry Pi is doing that too in hw/arm/raspi.c, like so: >=20 > =C2=A0 =C2=A0 if (machine->ram_size > 1 * GiB) { > =C2=A0 =C2=A0 =C2=A0 =C2=A0 error_report("Requested ram size is too larg= e for this machine: " > =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0"maximum is 1GB"); > =C2=A0 =C2=A0 =C2=A0 =C2=A0 exit(1); > =C2=A0 =C2=A0 } >=20 > I think it would be helpful to allow the flexibility to the user of=20 > reducing the RAM to less than 1GB, > in case resources of the host OS are limited. What do you think? Sure, good idea. FIY (in case you add more models) we recently noticed there is a problem=20 when using 2GiB default on 32-bit hosts, so the workaround is to use <=3D= =20 1GiB default. > > +=C2=A0 =C2=A0 memory_region_add_subregion(get_system_memory(), > AW_H3_SDRAM_BASE, > > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 &s->sdram); > > + > > +=C2=A0 =C2=A0 /* Load target kernel */ > > +=C2=A0 =C2=A0 orangepi_binfo.ram_size =3D machine->ram_size; > > +=C2=A0 =C2=A0 orangepi_binfo.nb_cpus=C2=A0 =3D AW_H3_NUM_CPUS; > > +=C2=A0 =C2=A0 arm_load_kernel(ARM_CPU(first_cpu), machine, &orang= epi_binfo); > > +} > > + > > +static void orangepi_machine_init(MachineClass *mc) > > +{ > > +=C2=A0 =C2=A0 mc->desc =3D "Orange Pi PC"; > > +=C2=A0 =C2=A0 mc->init =3D orangepi_init; > > +=C2=A0 =C2=A0 mc->units_per_default_bus =3D 1; > > +=C2=A0 =C2=A0 mc->min_cpus =3D AW_H3_NUM_CPUS; > > +=C2=A0 =C2=A0 mc->max_cpus =3D AW_H3_NUM_CPUS; > > +=C2=A0 =C2=A0 mc->default_cpus =3D AW_H3_NUM_CPUS; >=20 > =C2=A0 =C2=A0 =C2=A0 =C2=A0 mc->default_cpu_type =3D ARM_CPU_TYPE_NA= ME("cortex-a7"); >=20 > > +=C2=A0 =C2=A0 mc->ignore_memory_transaction_failures =3D true; >=20 > You should not use this flag in new design. See the documentation in > include/hw/boards.h: >=20 > =C2=A0 * @ignore_memory_transaction_failures: > =C2=A0 *=C2=A0 =C2=A0 [...] New board models > =C2=A0 *=C2=A0 =C2=A0 should instead use "unimplemented-device" for = all memory > ranges where > =C2=A0 *=C2=A0 =C2=A0 the guest will attempt to probe for a device t= hat QEMU doesn't > =C2=A0 *=C2=A0 =C2=A0 implement and a stub device is required. >=20 > You already use the "unimplemented-device". >=20 > Thanks, I'm working on this now. I think that at least I'll need to add > all of the devices mentioned in the 4.1 Memory Mapping chapter of the=20 > datasheet > as an unimplemented device. Previously I only added some that I thought= =20 > were relevant. >=20 > I added all the missing devices as unimplemented and removed the=20 > ignore_memory_transaction_failures flag I was going to say, "instead of adding *all* the devices regions you can=20 add the likely bus decoding regions", probably: 0x01c0.0000 128KiB AMBA AXI 0x01c2.0000 64KiB AMBA APB But too late. > from the machine. Now it seems Linux gets a data abort while probing the= =20 > uart1 serial device at 0x01c28400, Did you add the UART1 as UNIMP or 16550? > so I'll need to debug it further. I'll post back when I have more results= . >=20 > Regards, > Niek >=20 > > +} > > + > > +DEFINE_MACHINE("orangepi", orangepi_machine_init) >=20 > Can you name it 'orangepi-pc'? So we can add other orangepi models. >=20 > Thanks, >=20 > Phil. >=20 >=20 >=20 > --=20 > Niek Linnenbank >=20 From MAILER-DAEMON Fri Dec 06 09:07:03 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1idEG7-0000k1-H2 for mharc-qemu-arm@gnu.org; Fri, 06 Dec 2019 09:07:03 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:47745) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1idEG4-0000js-ST for qemu-arm@nongnu.org; Fri, 06 Dec 2019 09:07:01 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1idEG3-0006Yc-Fe for qemu-arm@nongnu.org; Fri, 06 Dec 2019 09:07:00 -0500 Received: from mail-oi1-f196.google.com ([209.85.167.196]:38756) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1idEG3-0006Ws-9G for qemu-arm@nongnu.org; Fri, 06 Dec 2019 09:06:59 -0500 Received: by mail-oi1-f196.google.com with SMTP id b8so6256768oiy.5 for ; Fri, 06 Dec 2019 06:06:58 -0800 (PST) DKIM-Signature: v=1; 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Fri, 06 Dec 2019 05:12:48 -0800 (PST) MIME-Version: 1.0 References: <20191119141211.25716-1-clg@kaod.org> In-Reply-To: <20191119141211.25716-1-clg@kaod.org> From: Peter Maydell Date: Fri, 6 Dec 2019 13:12:37 +0000 Message-ID: Subject: Re: [PATCH 00/17] aspeed: extensions and fixes To: =?UTF-8?Q?C=C3=A9dric_Le_Goater?= Cc: Andrew Jeffery , Joel Stanley , qemu-arm , QEMU Developers Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.85.167.196 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 06 Dec 2019 14:07:01 -0000 On Tue, 19 Nov 2019 at 14:12, C=C3=A9dric Le Goater wrote: > > Hi, > > Here is a series adding : > > - support for pool buffer transfers in the I2C controller > - fixes for the AST2600 and for the SMC controller > - a new Tacoma BMC board using the AST2600 SoC. > - misc small cleanups Applied to target-arm.next for 5.0; thanks. -- PMM From MAILER-DAEMON Fri Dec 06 09:11:51 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1idEKl-0005i6-7R for mharc-qemu-arm@gnu.org; Fri, 06 Dec 2019 09:11:51 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:41407) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1idEKh-0005cM-Ii for qemu-arm@nongnu.org; Fri, 06 Dec 2019 09:11:48 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1idEKg-0004WT-2s for qemu-arm@nongnu.org; Fri, 06 Dec 2019 09:11:47 -0500 Received: from mail-pl1-x641.google.com ([2607:f8b0:4864:20::641]:33896) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1idEKf-0004Sv-Rm for qemu-arm@nongnu.org; Fri, 06 Dec 2019 09:11:45 -0500 Received: by mail-pl1-x641.google.com with SMTP id h13so2794057plr.1 for ; Fri, 06 Dec 2019 06:11:45 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=subject:to:cc:references:from:message-id:date:user-agent :mime-version:in-reply-to:content-language:content-transfer-encoding; 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[97.113.7.119]) by smtp.gmail.com with ESMTPSA id q3sm17495356pfc.114.2019.12.06.06.03.48 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 06 Dec 2019 06:03:48 -0800 (PST) Subject: Re: [PATCH v5 21/22] target/arm: Add mmu indexes for tag memory To: Peter Maydell Cc: QEMU Developers , qemu-arm References: <20191011134744.2477-1-richard.henderson@linaro.org> <20191011134744.2477-22-richard.henderson@linaro.org> From: Richard Henderson Message-ID: <454d686b-e453-256e-7008-a2c00ea64148@linaro.org> Date: Fri, 6 Dec 2019 06:03:46 -0800 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.2.1 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 7bit X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::641 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 06 Dec 2019 14:11:49 -0000 On 12/6/19 3:46 AM, Peter Maydell wrote: >> + case ARMMMUIdx_TagS: >> + case ARMMMUIdx_TagNS: >> + /* Indicate tag memory to arm_asidx_from_attrs. */ >> + attrs->target_tlb_bit2 = true; >> + break; > > So here we fall through to the "handle a stage 1 lookup" code, which: > * sets attrs->secure > * sets attrs->user (always false, so we could have left it alone) > * skips the FCSE handling (as we're v8) > * skips the PMSA handling > * hits the regime_translation_disabled() check, which fills in > *phys_ptr, *prot and *page_size and returns Exactly. > Maybe it would be clearer if this case here just did all of that: > > case ARMMMUIdx_TagS: > attrs->secure = true; > /* fall through */ > case ARMMMUIdx_TagNS: > /* Indicate tag memory to arm_asidx_from_attrs. */ > attrs->target_tlb_bit2 = true; > *phys_ptr = address; > *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC; > *page_size = TARGET_PAGE_SIZE; > return 0; > > Did I miss anything out? I think that's about it. I thought about doing exactly this. Also, this is a better location if I ever do something about the TODO in tne next patch, wherein I talk about mapping not from physical address but from the normal ram's ramaddr_t, so as to cache that mapping step as well. r~ From MAILER-DAEMON Fri Dec 06 09:14:12 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1idEN1-000824-9M for mharc-qemu-arm@gnu.org; Fri, 06 Dec 2019 09:14:12 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:51331) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1idEMs-0007wU-BE for qemu-arm@nongnu.org; Fri, 06 Dec 2019 09:14:04 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1idEMm-0007Sm-BE for qemu-arm@nongnu.org; Fri, 06 Dec 2019 09:14:01 -0500 Received: from mail-ot1-x342.google.com ([2607:f8b0:4864:20::342]:39286) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1idEMk-0007Kj-Tz for qemu-arm@nongnu.org; Fri, 06 Dec 2019 09:13:56 -0500 Received: by mail-ot1-x342.google.com with SMTP id 77so5888352oty.6 for ; Fri, 06 Dec 2019 06:13:51 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=KhS4gG43qgtC91LEgSVI97VHTZLo7KkC/ba4BqbDDQA=; b=VOSYcnF3rR0AwaPLcHqOYQhhO3CElLvh+Rawv3pFS0HhebTxFVXscRXeGD+3CxeQ5O huEE8S4lWuSZHvXiHhhZQMqE6E5Bqf+8RXUxPz0ORzaKk/u0V8sw8RVbQMMIyNAj0Mkt 27U+/ugbKPZWsjq8RLxImQnin6CsFP3AD+pJA+pCaDXWpJyyRUBCQ8mvI349NvA3WyfF f6T++ZZlU4krHslZ20AJcYJ/gkpkakzn4oGd6EnQwnWSyteLe+Y9p+mtwenExiyzDU2+ bYXGfGq6hoKBfgOpDfUWogzlItmfD+Etro2yOGn5nnc4Ub71Rvo4SY8X82mAfxIna/Uf 6Ktg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=KhS4gG43qgtC91LEgSVI97VHTZLo7KkC/ba4BqbDDQA=; b=Mf8sP1VRJW6LKWV7WUuLiHfPz1Y8LjPYRIdYmWKQQKPvbT8Bdjm0wvWOtFmuzWi9pg MnPuaDYmilkj3zMRfN9+MRsFJOxWzVmhsXHACT5WZjQlg1/UUr9sqZFkUQB11TqsdwKp v8dhxmGvycC7/colPS1JnJGEWK/XABeN1EAkytCAGGmwCd4bgtpdPI6mTlalYwMD97DY 4+OIYiO97fg7E7BitupiLThty+xBivU5jKklpMLkWDS0oCEjFyV6Fki2ZD23e+TZbdoR Qk4PCpS+tWqsNttNqk512rGfZl0R41C/JCwwHlQLnGNOlLkd/VQKy5TCPRSjEqZEi84m 1fuQ== X-Gm-Message-State: APjAAAXwu9vwP423hHnj31XTwWabYPSZnZNHYdps/rGpsQHPKCdes+1W dOkjsamcyhBMn4MfNDCmg2dBNqkbjYh8n4fyHTz2eawP X-Google-Smtp-Source: APXvYqzon2R7riMvCbIfmw0eUySY3t+l0thH4e4kjiebly2OpJH162ICKgk240/4T+npqt9OnzSAi+lnq1kejn41kC0= X-Received: by 2002:a9d:6745:: with SMTP id w5mr10496157otm.221.1575640246856; Fri, 06 Dec 2019 05:50:46 -0800 (PST) MIME-Version: 1.0 References: <1552098649-28341-1-git-send-email-guoheyi@huawei.com> <20190312170859.73f0de9d@redhat.com> In-Reply-To: From: Peter Maydell Date: Fri, 6 Dec 2019 13:50:35 +0000 Message-ID: Subject: Re: [Qemu-devel] [PATCH v5 0/2] arm/acpi: simplify aml code and enable SHPC To: Guoheyi Cc: Igor Mammedov , qemu-arm , QEMU Developers , "Michael S. Tsirkin" , Shannon Zhao , wanghaibin.wang@huawei.com Content-Type: text/plain; charset="UTF-8" X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::342 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 06 Dec 2019 14:14:10 -0000 On Sat, 30 Nov 2019 at 03:47, Guoheyi wrote: > > Hi Peter, Igor, > > I couldn't find these 2 patches in the latest tree. Could you help to > merge them? In future I recommend pinging unapplied patches with a shorter delay than nine months :-) In QEMU's process, unless somebody has specifically said they've picked up the patch, it still "belongs" to the submitter to chase if it hasn't been applied. In this case I simply didn't see Igor's request that I take it -- the chances of me actually reading any particular list email even if it's cc'd to me are not good. I tried applying them to target-arm.next but unfortunately they break 'make check': TEST check-qtest-aarch64: tests/bios-tables-test acpi-test: Warning! DSDT binary file mismatch. Actual [aml:/tmp/aml-4IELC0], Expected [aml:tests/data/acpi/virt/DSDT]. acpi-test: Warning! DSDT mismatch. Actual [asl:/tmp/asl-AOELC0.dsl, aml:/tmp/aml-4IELC0], Expected [asl:/tmp/asl-XL7KC0.dsl, aml:tests/data/acpi/virt/DSDT]. ** ERROR:/home/petmay01/linaro/qemu-from-laptop/qemu/tests/bios-tables-test.c:477:test_acpi_asl: assertion failed: (all_tables_match) ERROR - Bail out! ERROR:/home/petmay01/linaro/qemu-from-laptop/qemu/tests/bios-tables-test.c:477:test_acpi_asl: assertion failed: (all_tables_match) Aborted (core dumped) /home/petmay01/linaro/qemu-from-laptop/qemu/tests/Makefile.include:918: recipe for target 'check-qtest-aarch64' failed Could you fix and resubmit, please? thanks -- PMM From MAILER-DAEMON Fri Dec 06 09:14:48 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1idENc-0000OU-54 for mharc-qemu-arm@gnu.org; Fri, 06 Dec 2019 09:14:48 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:54434) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1idENZ-0000Jk-2i for qemu-arm@nongnu.org; Fri, 06 Dec 2019 09:14:46 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1idENY-00005H-0L for qemu-arm@nongnu.org; Fri, 06 Dec 2019 09:14:44 -0500 Received: from mail-pf1-x442.google.com ([2607:f8b0:4864:20::442]:38031) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1idENX-0008Vu-Qy for qemu-arm@nongnu.org; Fri, 06 Dec 2019 09:14:43 -0500 Received: by mail-pf1-x442.google.com with SMTP id x185so3416156pfc.5 for ; Fri, 06 Dec 2019 06:14:43 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=subject:to:cc:references:from:message-id:date:user-agent :mime-version:in-reply-to:content-language:content-transfer-encoding; bh=nJ3Ty/hziDCgTO/SCbkDbEcjoRLOPPW5sJ3nnbViC+Q=; b=J0JW6vvSXD/EiBndUYVjjeDnd6O/kiE19EKi/U4mByJ+0DjF3TXyLxl7ggZr0Y2Pli HIHUe8W8BrWNJGHta8aqatQsQStJV2xYUC50ZA3Lcdm0CJaSSzWoJvg06OsuxcADvuNV L2NAR1krBb3CUvdAGHTz6pflbjvS2CZbwci6eazXIIxQAHrcJj084iO1IRM5dPuPfJs2 Xm6RfAKnQZNxUJ4IKwwh4vYUP/0+prjnHAoAogIZJ745ryxrckzm0i2eleJfNjESCRpL Td66N/F2o5BdBADf3cHkkgI/2OAjQWjTfT1O3hAv6+VNkYEp+RkAdm9Kl/7hlia7ESEX 7iFw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:subject:to:cc:references:from:message-id:date :user-agent:mime-version:in-reply-to:content-language :content-transfer-encoding; bh=nJ3Ty/hziDCgTO/SCbkDbEcjoRLOPPW5sJ3nnbViC+Q=; b=VZS/RyE3KX8KQvoCHq372q1Mn80F38YKT/VvIwieLNll+GgKvtXTsbXulbSFuldy8i YB/vgP84cRUWsVF30y45OKbA7AlvSIhvjZFbxwHA5RdRPDg5QO/6C65++/PYC6QR03bR KD+hkkNSRLSDLElIGY0sqrQUPyKIAoQ/0kquzo7lzbiV7q+2bq5vvMPNEJh0HtkyMWFm iV2J9BVHPlCUNkeU7bt9CqG3jUbmD7E5ZPxWShmRgDkeHQlLvRXw+MCwTePItF0wctMO uxrzisiOkSJxBN29O/u2e5vBFtnPUo7n6ZSs0HUuwsRxO9lX+2ZovbovlYfHLQLChUVn O0jg== X-Gm-Message-State: APjAAAUnKI2e172EQ9fF6QV3TggIWv7ygi4xuQmyhj9PlJygZkSnVYX2 bd5pNkEJp/+KGMqaGkJZSebusRsJ9Q8= X-Google-Smtp-Source: APXvYqw2VUCUqiDrh0YcV3Nfd4Ek4u6fuowiGYaF6ikD90eoixb9AIIrgUW4b6V2htGh5FutXd0VCQ== X-Received: by 2002:a62:bd08:: with SMTP id a8mr14542107pff.84.1575641682271; Fri, 06 Dec 2019 06:14:42 -0800 (PST) Received: from [192.168.1.11] (97-113-7-119.tukw.qwest.net. [97.113.7.119]) by smtp.gmail.com with ESMTPSA id q12sm10864147pfh.158.2019.12.06.06.14.41 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 06 Dec 2019 06:14:41 -0800 (PST) Subject: Re: [PATCH v5 22/22] target/arm: Add allocation tag storage for system mode To: Peter Maydell Cc: QEMU Developers , qemu-arm References: <20191011134744.2477-1-richard.henderson@linaro.org> <20191011134744.2477-23-richard.henderson@linaro.org> From: Richard Henderson Message-ID: Date: Fri, 6 Dec 2019 06:14:39 -0800 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.2.1 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 7bit X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::442 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 06 Dec 2019 14:14:46 -0000 On 12/6/19 5:02 AM, Peter Maydell wrote: >> + /* >> + * Find the physical address for the virtual access. >> + * >> + * TODO: It should be possible to have the tag mmu_idx map >> + * from main memory ram_addr to tag memory host address. >> + * that would allow this lookup step to be cached as well. >> + */ >> + section = iotlb_to_section(cs, iotlbentry->addr, iotlbentry->attrs); >> + physaddr = ((iotlbentry->addr & TARGET_PAGE_MASK) + ptr >> + + section->offset_within_address_space >> + - section->offset_within_region); > > I'm surprised that going from vaddr to (physaddr, attrs) requires > this much effort, it seems like the kind of thing we would > already have a function to do. There are very few places that need to talk about the actual physical address. Mostly because that doesn't mean much within qemu -- physical address within which address space? Usually we want the ramaddr_t (which is a sort of combination of pa + as), or the host address, or the device the exists at the pa + as. >> + /* >> + * FIXME: Get access length and type so that we can use >> + * probe_access, so that pages are marked dirty for migration. >> + */ >> + return tlb_vaddr_to_host(env, tag_physaddr, MMU_DATA_LOAD, mmu_idx); > > Hmm, does that mean that a setup with MemTag is not migratable? > If so, we should at least install a migration-blocker for CPUs > in that configuration. It probably does as written. I intend to fix this properly before final. r~ From MAILER-DAEMON Fri Dec 06 09:16:30 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1idEPF-0002OC-3N for mharc-qemu-arm@gnu.org; Fri, 06 Dec 2019 09:16:30 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:35532) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1idEP9-0002Hp-Pc for qemu-arm@nongnu.org; Fri, 06 Dec 2019 09:16:25 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1idEP7-0002m6-LI for qemu-arm@nongnu.org; Fri, 06 Dec 2019 09:16:23 -0500 Received: from us-smtp-delivery-1.mimecast.com ([205.139.110.120]:50403 helo=us-smtp-1.mimecast.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1idEP7-0002hF-Ew for qemu-arm@nongnu.org; Fri, 06 Dec 2019 09:16:21 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1575641773; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=QydCtaGu0VxNLL1vkJgck5UBv6FIuo7+xYoT62obZJU=; b=WNuPiCVFqtykdArdtsfKsuIY130OeRw9Q16csGfmLPUU3DG0XYUTGs5Clgb4OLG88Anakw bz3xRoryi2HKw0K2w7UVZuZ+9moEcAfKm47Q7xWfxW6P9pJ21Q1u+u9GxWMKtqugRQadKe yMD1Yxu6e2iC4TjlKkzgwfBK1f3P1eI= Received: from mimecast-mx01.redhat.com (mimecast-mx01.redhat.com [209.132.183.4]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-348-Ywo88t0dNVOFL__UeWWsrg-1; Fri, 06 Dec 2019 03:14:29 -0500 Received: from smtp.corp.redhat.com (int-mx08.intmail.prod.int.phx2.redhat.com [10.5.11.23]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx01.redhat.com (Postfix) with ESMTPS id 34BFA102CE28; Fri, 6 Dec 2019 08:14:25 +0000 (UTC) Received: from blackfin.pond.sub.org (ovpn-116-134.ams2.redhat.com [10.36.116.134]) by smtp.corp.redhat.com (Postfix) with ESMTPS id A2D8819C7F; Fri, 6 Dec 2019 08:13:58 +0000 (UTC) Received: by blackfin.pond.sub.org (Postfix, from userid 1000) id 22B421138606; Fri, 6 Dec 2019 09:13:57 +0100 (CET) From: Markus Armbruster To: Vladimir Sementsov-Ogievskiy Cc: Stefan Hajnoczi , Jeff Cody , Jan Kiszka , Alberto Garcia , Hailiang Zhang , "qemu-block\@nongnu.org" , Aleksandar Rikalo , Halil Pasic , =?utf-8?Q?Herv=C3=A9?= Poussineau , Anthony Perard , Samuel Thibault , Laszlo Ersek , Jason Wang , Laurent Vivier , Eduardo Habkost , Xie Changlong , Peter Lieven , "Dr. David Alan Gilbert" , Beniamino Galvani , Eric Auger , Alex Williamson , Ronnie Sahlberg , John Snow , Richard Henderson , Kevin Wolf , Andrew Jeffery , Chris Wulff , Subbaraya Sundeep , Michael Walle , "qemu-ppc\@nongnu.org" , Bastian Koppelmann , Igor Mammedov , Fam Zheng , Peter Maydell , "sheepdog\@lists.wpkg.org" , Matthew Rosato , David Hildenbrand , Palmer Dabbelt , Eric Farman , Max Filippov , Hannes Reinecke , Stefano Stabellini , "Gonglei \(Arei\)" , Liu Yuan , Artyom Tarasenko , Thomas Huth , Amit Shah , Stefan Weil , Greg Kurz , Yuval Shaia , "qemu-s390x\@nongnu.org" , "qemu-arm\@nongnu.org" , Peter Chubb , =?utf-8?Q?C=C3=A9dric?= Le Goater , Stafford Horne , "qemu-riscv\@nongnu.org" , Cornelia Huck , Aleksandar Markovic , Aurelien Jarno , Paul Burton , Sagar Karandikar , Paul Durrant , Anthony Green , Gerd Hoffmann , "Edgar E. Iglesias" , Guan Xuetao , Ari Sundholm , Juan Quintela , Michael Roth , Christian Borntraeger , Joel Stanley , Jason Dillaman , Antony Pavlov , "xen-devel\@lists.xenproject.org" , "integration\@gluster.org" , Philippe =?utf-8?Q?Mathieu-Daud=C3=A9?= , "Richard W.M. Jones" , Andrew Baumann , Max Reitz , Denis Lunev , "Michael S. Tsirkin" , Mark Cave-Ayland , "qemu-devel\@nongnu.org" , Vincenzo Maffione , Marek Vasut , =?utf-8?Q?Marc-Andr=C3=A9?= Lureau , Alistair Francis , Pavel Dovgalyuk , Giuseppe Lettieri , Luigi Rizzo , David Gibson , Tony Krowiak , Daniel P. =?utf-8?Q?Berrang=C3=A9?= , Xiao Guangrong , Pierre Morel , Wen Congyang , Jean-Christophe Dubois , Paolo Bonzini , Stefan Berger Subject: Re: [RFC v5 024/126] error: auto propagated local_err References: <20191011160552.22907-1-vsementsov@virtuozzo.com> <20191011160552.22907-25-vsementsov@virtuozzo.com> <87muc8p24w.fsf@dusky.pond.sub.org> <55393c08-5bda-8042-1a95-f350b3781d99@virtuozzo.com> <87d0d3c5k7.fsf@dusky.pond.sub.org> Date: Fri, 06 Dec 2019 09:13:57 +0100 In-Reply-To: (Vladimir Sementsov-Ogievskiy's message of "Thu, 5 Dec 2019 16:36:42 +0000") Message-ID: <87h82dna62.fsf@dusky.pond.sub.org> User-Agent: Gnus/5.13 (Gnus v5.13) Emacs/26.2 (gnu/linux) MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.84 on 10.5.11.23 X-MC-Unique: Ywo88t0dNVOFL__UeWWsrg-1 X-Mimecast-Spam-Score: 0 Content-Type: text/plain Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 205.139.110.120 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 06 Dec 2019 14:16:27 -0000 Vladimir Sementsov-Ogievskiy writes: > 05.12.2019 17:58, Vladimir Sementsov-Ogievskiy wrote: >> 05.12.2019 15:36, Markus Armbruster wrote: >>> Vladimir Sementsov-Ogievskiy writes: >>> >>>> 04.12.2019 17:59, Markus Armbruster wrote: >>>>> Vladimir Sementsov-Ogievskiy writes: >>>>> >>>>>> Here is introduced ERRP_AUTO_PROPAGATE macro, to be used at start of >>>>>> functions with errp OUT parameter. >>>>>> >>>>>> It has three goals: >>>>>> >>>>>> 1. Fix issue with error_fatal & error_prepend/error_append_hint: use= r >>>>>> can't see this additional information, because exit() happens in >>>>>> error_setg earlier than information is added. [Reported by Greg Kurz= ] >>>>>> >>>>>> 2. Fix issue with error_abort & error_propagate: when we wrap >>>>>> error_abort by local_err+error_propagate, resulting coredump will >>>>>> refer to error_propagate and not to the place where error happened. >>>>> >>>>> I get what you mean, but I have plenty of context. >>>>> >>>>>> (the macro itself doesn't fix the issue, but it allows to [3.] drop = all >>>>>> local_err+error_propagate pattern, which will definitely fix the iss= ue) >>>>> >>>>> The parenthesis is not part of the goal. >>>>> >>>>>> [Reported by Kevin Wolf] >>>>>> >>>>>> 3. Drop local_err+error_propagate pattern, which is used to workarou= nd >>>>>> void functions with errp parameter, when caller wants to know result= ing >>>>>> status. (Note: actually these functions could be merely updated to >>>>>> return int error code). >>>>>> >>>>>> To achieve these goals, we need to add invocation of the macro at st= art >>>>>> of functions, which needs error_prepend/error_append_hint (1.); add >>>>>> invocation of the macro at start of functions which do >>>>>> local_err+error_propagate scenario the check errors, drop local erro= rs >>>>>> from them and just use *errp instead (2., 3.). >>>>> >>>>> The paragraph talks about two cases: 1. and 2.+3. >>>> >>>> Hmm, I don't think so.. 1. and 2. are issues. 3. is a refactoring.. We= just >>>> fix achieve 2 and 3 by one action. >>>> >>>>> Makes me think we >>>>> want two paragraphs, each illustrated with an example. >>>>> >>>>> What about you provide the examples, and then I try to polish the pro= se? >>>> >>>> 1: error_fatal problem >>>> >>>> Assume the following code flow: >>>> >>>> int f1(errp) { >>>> ... >>>> ret =3D f2(errp); >>>> if (ret < 0) { >>>> error_append_hint(errp, "very useful hint"); >>>> return ret; >>>> } >>>> ... >>>> } >>>> >>>> Now, if we call f1 with &error_fatal argument and f2 fails, the progra= m >>>> will exit immediately inside f2, when setting the errp. User will not >>>> see the hint. >>>> >>>> So, in this case we should use local_err. >>> >>> How does this example look after the transformation? >>=20 >> Good point. >>=20 >> int f1(errp) { >> ERRP_AUTO_PROPAGATE(); >> ... >> ret =3D f2(errp); >> if (ret < 0) { >> error_append_hint(errp, "very useful hint"); >> return ret; >> } >> ... >> } >>=20 >> - nothing changed, only add macro at start. But now errp is safe, if it = was >> error_fatal it is wrapped by local error, and will only call exit on aut= omatic >> propagation on f1 finish. >>=20 >>> >>>> 2: error_abort problem >>>> >>>> Now, consider functions without return value. We normally use local_er= r >>>> variable to catch failures: >>>> >>>> void f1(errp) { >>>> Error *local_err =3D NULL; >>>> ... >>>> f2(&local_err); >>>> if (local_err) { >>>> error_propagate(errp, local_err); >>>> return; >>>> } >>>> ... >>>> } >>>> >>>> Now, if we call f2 with &error_abort and f2 fails, the stack in result= ing >>>> crash dump will point to error_propagate, not to the failure point in = f2, >>>> which complicates debugging. >>>> >>>> So, we should never wrap error_abort by local_err. >>> >>> Likewise. >>=20 >> And here: >>=20 >> void f1(errp) { >> ERRP_AUTO_PROPAGATE(); >> ... >> f2(errp); >> if (*errp) { >> return; >> } >> ... >>=20 >> - if errp was NULL, it is wrapped, so dereferencing errp is safe. On ret= urn, >> local error is automatically propagated to original one. > > and if it was error_abort, it is not wrapped, so will crash where failed. We still need to avoid passing on unwrapped @errp when we want to ignore some errors, as in fit_load_fdt(), but that should be quite rare. Doesn't invalidate your approach. [...] From MAILER-DAEMON Fri Dec 06 09:16:53 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1idEPd-0002jo-E4 for mharc-qemu-arm@gnu.org; Fri, 06 Dec 2019 09:16:53 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:36584) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1idEPY-0002fa-UF for qemu-arm@nongnu.org; Fri, 06 Dec 2019 09:16:50 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1idEPV-00036F-4r for qemu-arm@nongnu.org; Fri, 06 Dec 2019 09:16:46 -0500 Received: from mail-oi1-x241.google.com ([2607:f8b0:4864:20::241]:45745) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1idEPT-00033w-Ou for qemu-arm@nongnu.org; Fri, 06 Dec 2019 09:16:44 -0500 Received: by mail-oi1-x241.google.com with SMTP id v10so6225190oiv.12 for ; Fri, 06 Dec 2019 06:16:41 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=cqLL5RtdyUdC5IL64sizJ5FYAyB9GVg7mF4uLUkd2ck=; b=Xy26temOiPfQ2BXiKHRPxzyqkQpjxppqbn3sjJYv16iKFhjEPsYYt8zRI2h05x6YML bVZndVDyazYL++HHCbYEEZj0Qg9TTZCoyW0R9W5oZYIeEdYGFjmzlyxd0Wpa+OGRxEIJ QVDQxRcptCPijJWly9olMZ5/RYUxEUbalUvJQHuJNIkfZhFWAIhaPcr3W0SzZwpRq15n uIso3oXeDHzkQykQvo3+RO9mp2S8gFacNrboVx6yt8PAosz9Ixd9fsRMEkmQt/wFiOi2 0Q0dHSHzUxRJpmtASypxD/e0RJRoapA45E1zoS9XU0TB/S+v6TjI7lcttiF/vqeq7LB4 0n+A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=cqLL5RtdyUdC5IL64sizJ5FYAyB9GVg7mF4uLUkd2ck=; b=L7GGAE83cx8PupBTbxLDxVzoInjzGer3UcT/jQp5fI92OWsD5/AitRuMLQsaqS/sR3 chv0j7NXwk5wlr8OMBRveFbct7BNFRC+VS6+PV2l/jv28UM1YoGWzv24chJyx1OIs9/9 ABQRyOvepAky0E6ll1KK4qPv5CcLYSL+2g3Iv3NOulgcR6fKbkp8+/T3VxtIXwFsShuV OPrHFBlR0BYgPkAE2P6Mq34tGKPnlo6eeLv0bPpZZCpGa7k2Qr7xNgC2SsG+dzOw63hx 8cr9X+IgBoMGN64GA/xyH2tuofqqwG1hD42/MLMFxmBvvevrUOuZpidjKkW6sd67DNjS Gjsw== X-Gm-Message-State: APjAAAXj9MDUxy60Oy8AitpERHqZq9z5GYRIcRku1IjwZ6s5M0UqlS54 Ly4HQBoAlE7XU0EDXtRM9jbukI8qKxBS4DOBROOPUg== X-Google-Smtp-Source: APXvYqyotJT4TYt3XVxqaLIrZXCcD+9qllLQmnQyva14c9LScCikQTngN9hVk25112Zv7iYftV+AwPk/gnmJhQfTp4o= X-Received: by 2002:a05:6808:996:: with SMTP id a22mr11804663oic.146.1575641800450; Fri, 06 Dec 2019 06:16:40 -0800 (PST) MIME-Version: 1.0 References: <20191202210947.3603-1-nieklinnenbank@gmail.com> <1de57227-8124-4d11-d996-9faf67b3e4f3@redhat.com> In-Reply-To: From: Peter Maydell Date: Fri, 6 Dec 2019 14:16:29 +0000 Message-ID: Subject: Re: [PATCH 00/10] Add Allwinner H3 SoC and Orange Pi PC Machine To: Niek Linnenbank Cc: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= , QEMU Developers , Beniamino Galvani , qemu-arm , Richard Henderson , KONRAD Frederic , Alistair Francis , =?UTF-8?Q?Niccol=C3=B2_Izzo?= Content-Type: text/plain; charset="UTF-8" X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::241 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 06 Dec 2019 14:16:51 -0000 On Tue, 3 Dec 2019 at 19:32, Niek Linnenbank wrote: > Indeed that sounds like an interesting combination. Are there plans to build a multi-arch/single-binary QEMU? This is in the category of "it would be nice in theory to support multi-arch guest machines, and we've made some small steps in that direction and/or tried to keep the door open for it when designing things, but it would still be a huge amount of work to actually implement, so don't hold your breath for it or make anything else depend on having it happen first"... thanks -- PMM From MAILER-DAEMON Fri Dec 06 09:18:47 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1idERT-000521-9d for mharc-qemu-arm@gnu.org; Fri, 06 Dec 2019 09:18:47 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:47192) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1idERP-0004vd-Gw for qemu-arm@nongnu.org; Fri, 06 Dec 2019 09:18:44 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1idERO-0005yg-8N for qemu-arm@nongnu.org; Fri, 06 Dec 2019 09:18:43 -0500 Received: from mail-wr1-x441.google.com ([2a00:1450:4864:20::441]:42431) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1idERO-0005ve-1I for qemu-arm@nongnu.org; Fri, 06 Dec 2019 09:18:42 -0500 Received: by mail-wr1-x441.google.com with SMTP id a15so7902092wrf.9 for ; Fri, 06 Dec 2019 06:18:41 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=FD/Gkl8WcCvCcRAxkg2Vj/Km0ssoYdQNd69civUvsNY=; b=rWobYaBzJqmLkIkFrA5eMyiDv5QGLzEibM6XsJ01npKypFTPnNbcMitaPvGtmiQogt ogK6OwYXXuqsY8NJpqjGpNxGXIPPBiz+iFNNzxYC9EMYuVlLYpBgiLBRU/mLQN+frdBd H8Lkkqm8jyNTVbiLcnqLrKaaxx7T0xwr60IcchvJjngjxJ5MjlRGmEvyJBUC8BytOJ3w 6Hl2sIe3WID49sW4CIKiLeagLJ8K5oo2lap3BMMIv57PqR7CcgJGq0NrcFyauy4Jm8tu huQbHIx7VQN8GM73AY9pVjWEHJ6g8tCnTNm8wQPieX1CZUcjId1i7SwEghYFJ7tJ4/7F wDHA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=FD/Gkl8WcCvCcRAxkg2Vj/Km0ssoYdQNd69civUvsNY=; b=Cnba3ToylxNhCdvA3szrQ5CMMrKxctOXfBF031LvzCpk+Qf3dzXk/I6piDGVFtmboU 17PAQw7rPvlHmpmBGcRZjF3AVILasBSCvxcd5FAIjhvzGCfV6qoGhIKKleqNj1Ct9YIF 5kNOkec4U+rPy1MGdILTiwpKWBYrvQ4/w+gG9Q0/2au2Y6EqX8Y1QhDK8M2Sdn+yJb+Q 71zC4aplbrZHTRTn1raC2nUVYBET3XC0d4G7SqqyfvQD7BeQ6xEMXbDggUSYcQ/2Jx1O OPI50RlWyIFuYWPmIqZk/vSO2JatQertswfBe5KgSUQan/IK+6f+PPBB38b3VF0pFwCB cfiA== X-Gm-Message-State: APjAAAXBQPiMBbmcmTSd0nlnxMtRGqa+kNazi/bm29/oIKmn310K24kW 46AlpaLBzry+BHcMiDCpIZt4PAGvS2Y= X-Google-Smtp-Source: APXvYqxkx0SwWhQUZQbI5bGBGLowxnE0tSC2lFGY8s6O7J/AuvXKgVTBunS8dXesZwKJCtCxqMcLgQ== X-Received: by 2002:a5d:6ca1:: with SMTP id a1mr15105563wra.36.1575634975459; Fri, 06 Dec 2019 04:22:55 -0800 (PST) Received: from zen.linaroharston ([51.148.130.216]) by smtp.gmail.com with ESMTPSA id q3sm16242114wrn.33.2019.12.06.04.22.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 06 Dec 2019 04:22:54 -0800 (PST) Received: from zen.lan (localhost [127.0.0.1]) by zen.linaroharston (Postfix) with ESMTP id 991831FF87; Fri, 6 Dec 2019 12:22:53 +0000 (GMT) From: =?UTF-8?q?Alex=20Benn=C3=A9e?= To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, =?UTF-8?q?Alex=20Benn=C3=A9e?= , Peter Maydell Subject: [PATCH] target/arm: don't bother with id_aa64pfr0_read for USER_ONLY Date: Fri, 6 Dec 2019 12:22:47 +0000 Message-Id: <20191206122247.7507-1-alex.bennee@linaro.org> X-Mailer: git-send-email 2.20.1 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::441 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 06 Dec 2019 14:18:46 -0000 For system emulation we need to check the state of the GIC before we report the value. However this isn't relevant to exporting of the value to linux-user and indeed breaks the exported value as set by modify_arm_cp_regs. [AJB: the other option would be just to set reset value anyway and not ifdef out the readfn as the register will become const anyway] Signed-off-by: Alex Bennée --- target/arm/helper.c | 16 ++++++++++++---- 1 file changed, 12 insertions(+), 4 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index f78dd3b5fe3..489c31504a6 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -5867,6 +5867,7 @@ static uint64_t id_pfr1_read(CPUARMState *env, const ARMCPRegInfo *ri) return pfr1; } +#ifndef CONFIG_USER_ONLY static uint64_t id_aa64pfr0_read(CPUARMState *env, const ARMCPRegInfo *ri) { ARMCPU *cpu = env_archcpu(env); @@ -5877,6 +5878,7 @@ static uint64_t id_aa64pfr0_read(CPUARMState *env, const ARMCPRegInfo *ri) } return pfr0; } +#endif /* Shared logic between LORID and the rest of the LOR* registers. * Secure state has already been delt with. @@ -6297,16 +6299,22 @@ void register_cp_regs_for_features(ARMCPU *cpu) * define new registers here. */ ARMCPRegInfo v8_idregs[] = { - /* ID_AA64PFR0_EL1 is not a plain ARM_CP_CONST because we don't - * know the right value for the GIC field until after we - * define these regs. + /* + * ID_AA64PFR0_EL1 is not a plain ARM_CP_CONST in system + * emulation because we don't know the right value for the + * GIC field until after we define these regs. */ { .name = "ID_AA64PFR0_EL1", .state = ARM_CP_STATE_AA64, .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 0, .access = PL1_R, .type = ARM_CP_NO_RAW, .accessfn = access_aa64_tid3, +#ifdef CONFIG_USER_ONLY + .resetvalue = cpu->isar.id_aa64pfr0 +#else .readfn = id_aa64pfr0_read, - .writefn = arm_cp_write_ignore }, + .writefn = arm_cp_write_ignore +#endif + }, { .name = "ID_AA64PFR1_EL1", .state = ARM_CP_STATE_AA64, .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 1, .access = PL1_R, .type = ARM_CP_CONST, -- 2.20.1 From MAILER-DAEMON Fri Dec 06 09:20:13 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1idESr-0005s1-Gd for mharc-qemu-arm@gnu.org; Fri, 06 Dec 2019 09:20:13 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:51279) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1idESn-0005nG-FO for qemu-arm@nongnu.org; Fri, 06 Dec 2019 09:20:10 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1idESl-0007nV-U2 for qemu-arm@nongnu.org; Fri, 06 Dec 2019 09:20:09 -0500 Received: from us-smtp-1.mimecast.com ([207.211.31.81]:25118 helo=us-smtp-delivery-1.mimecast.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1idESl-0007hy-MC for qemu-arm@nongnu.org; Fri, 06 Dec 2019 09:20:07 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1575642004; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=qeEpOHiVicsdQEuTeVw1xPx0IpulfUWaY/EsL1Z8z1Q=; b=f1nhVLyM5DhijZ8xG4duIOOm4J/0OeMvwg/dPZ7yADw1H94Rj2ieItDTRE4HyFQBATTOTi 9qV4mV/F/McrKP39vvjZtdbAJ2e4Jyat4M04934lOMaDdDFHoy3oBlSuHtDngOB9NDVRZd yy80B2cqaiAydHJVlQfie1hnd8vcK7Y= Received: from mimecast-mx01.redhat.com (mimecast-mx01.redhat.com [209.132.183.4]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-343-4R-FKP8ONSOLEjbz2If8fQ-1; Fri, 06 Dec 2019 08:49:12 -0500 Received: from smtp.corp.redhat.com (int-mx03.intmail.prod.int.phx2.redhat.com [10.5.11.13]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx01.redhat.com (Postfix) with ESMTPS id AFEA7107ACC4; Fri, 6 Dec 2019 13:49:10 +0000 (UTC) Received: from work-vm (ovpn-117-232.ams2.redhat.com [10.36.117.232]) by smtp.corp.redhat.com (Postfix) with ESMTPS id 3ADC9608A5; Fri, 6 Dec 2019 13:49:02 +0000 (UTC) Date: Fri, 6 Dec 2019 13:48:59 +0000 From: "Dr. David Alan Gilbert" To: Cleber Rosa Cc: Philippe =?iso-8859-1?Q?Mathieu-Daud=E9?= , Peter Maydell , Alex =?iso-8859-1?Q?Benn=E9e?= , Richard Henderson , Damien Hedde , QEMU Developers , Mark Burton , "Edgar E. Iglesias" , Alistair Francis , =?iso-8859-1?Q?Marc-Andr=E9?= Lureau , Paolo Bonzini , "Daniel P. Berrange" , Eduardo Habkost , qemu-arm , Oksana Voshchana Subject: Re: [PATCH v6 0/9] Clock framework API Message-ID: <20191206134859.GC2878@work-vm> References: <279a0fd5-1ea5-b3c7-27bb-b1d22db5e359@redhat.com> <20191205102151.GB2824@work-vm> <20191205105613.GE2824@work-vm> <138ef325-dc9a-2ca5-9044-c67ffdabb968@redhat.com> <20191206124613.GA3902@dhcp-17-72.bos.redhat.com> MIME-Version: 1.0 In-Reply-To: <20191206124613.GA3902@dhcp-17-72.bos.redhat.com> User-Agent: Mutt/1.12.1 (2019-06-15) X-Scanned-By: MIMEDefang 2.79 on 10.5.11.13 X-MC-Unique: 4R-FKP8ONSOLEjbz2If8fQ-1 X-Mimecast-Spam-Score: 0 Content-Type: text/plain; charset=iso-8859-1 Content-Transfer-Encoding: quoted-printable Content-Disposition: inline X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 207.211.31.81 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 06 Dec 2019 14:20:11 -0000 * Cleber Rosa (crosa@redhat.com) wrote: > On Thu, Dec 05, 2019 at 12:01:56PM +0100, Philippe Mathieu-Daud=E9 wrote: > >=20 > > Understood, thanks for clearing this out! > >=20 > > Side note, we don't do cross-arch migration testing, but we talked abou= t > > having a 'different QEMU version' migration test. When we get a such te= st > > setup, it shouldn't be too difficult to evolve to some cross-arch migra= tion > > test. > > >=20 > +Oksana, >=20 > Avocado-VT has had this as a core concept as far as I can remember, and > it's exposed even as a command line argument: >=20 > avocado run --help > ... > [--vt-qemu-dst-bin VT_DST_QEMU_BIN] > ... >=20 Yeh, I've run that in the past - it works OK. Dave > Oksana is currently working on new migration test cases, and may consider > looking into adding "different QEMU version" support too. >=20 > PS: I have to say, though, that I'm trying to get my mind around > cross-arch migration being real. >=20 > - Cleber. >=20 > > > > I hope I'm wrong and confuse, this is a great news for me to know w= e > > > > can migrate floats! > > > >=20 > > > > > Dave > > > > >=20 > > > > > > > So we could store the frequency in clock out and migrate thin= gs there. > > > > > > > But since we have no way to ensure all clock out states are m= igrated > > > > > > > before some device fetch a ClockIn: we'll have to say "don't = fetch one > > > > > > > of your ClockIn frequency during migration and migrate the va= lue > > > > > > > yourself if you need it", pretty much like gpios. > > > > > > >=20 > > > > > > > So we will probably migrate all ClockOut and almost all Clock= In. > > > > > > >=20 > > > > > > > It would nice if we had a way to ensure clocks are migrated b= efore > > > > > > > devices try to use them. But I don't think this is possible. > > > > > > >=20 > > > > > > > -- > > > > > > > Damien > > > > > > >=20 > > > > > >=20 > > > > > -- > > > > > Dr. David Alan Gilbert / dgilbert@redhat.com / Manchester, UK > > > > >=20 > > > >=20 > > > -- > > > Dr. David Alan Gilbert / dgilbert@redhat.com / Manchester, UK > > >=20 > >=20 -- Dr. David Alan Gilbert / dgilbert@redhat.com / Manchester, UK From MAILER-DAEMON Fri Dec 06 09:21:39 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1idEUF-0007IP-60 for mharc-qemu-arm@gnu.org; Fri, 06 Dec 2019 09:21:39 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:57728) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1idEUB-0007DG-EB for qemu-arm@nongnu.org; Fri, 06 Dec 2019 09:21:36 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1idEUA-0001t4-Co for qemu-arm@nongnu.org; Fri, 06 Dec 2019 09:21:35 -0500 Received: from mail-ua1-x942.google.com ([2607:f8b0:4864:20::942]:37464) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1idEUA-0001s2-8a for qemu-arm@nongnu.org; Fri, 06 Dec 2019 09:21:34 -0500 Received: by mail-ua1-x942.google.com with SMTP id f9so2544449ual.4 for ; Fri, 06 Dec 2019 06:21:34 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=dmq/2j6nGIVBQGtDL6jBJ9TApdnLutBPJ157fatWu+4=; b=zLbDDOl1dLgyWsvAFLYNoGci9uF9Va2gzT3W/EoGykUNumLA2qDUDlRxfhLo37nbu5 70eROptPAgLUvinZlMMwTqlAsRjvhiZkSg3cCj6FJ546zml5Lqikjcg98SaYOL4qTPLD pFBciYWkmfExoPToBX10HlCV/ds2vqXeklnl551MiwCRCtSIUL3sNqGwqZxCuwexGSVN i63YxB5aC0n0XUUytuMO6IqABiyx//NcXOsvtoN23JkVym1QygAmsmY4XqUH7wRumwbZ 1zWQwQVCZnMndoRW8ylkqFV+g+zmngXtWr02YbycILpIWz7FYZYySEcWhBR3f6ruwJrN 6eJQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=dmq/2j6nGIVBQGtDL6jBJ9TApdnLutBPJ157fatWu+4=; b=RoVYqj6fcmKAp4hbsbJ2PZRlZeCjERBHsCm5GPa/f1VRMEeVNLzi7j/Zm6pwc5wx9M UywQXhOPJZLtHAhRdph5mgEbu4dN3TgEECsvzva55cRMM090TX0nTM14Ha71oTbeO3xB JBdHcHzzgNXl/0uChu1BHwsCuR+fomrLvwAyFaUtLSk/OGcRy0axsd1PlI9b1I8m8UIq gtAiVmXr9HpEjFcS6qhfbOpHslOWxm43SUnFtmp6Hn+cNP396inK562ZQhbcpxa8R/HS fO744l1WedJHoR/ObMAZ7KoXz/aB8taL8fonj4cjaFLYA/RLrOmD/vtXhEDpFNVIfZje pgTw== X-Gm-Message-State: APjAAAVJmcMbCWfsTTF/mTGDqCyookfMeJICcqnFURO9YN6CJaaNsg5q 1Ovudu4MhTfT2PXdUEmGXuk/V4/gpijsumb/BBSiEOF0 X-Google-Smtp-Source: APXvYqxROLhRMAql+98WYp7dAbT5NVrgWi3zooCajKGV57yz+Ps8KZm3tVPYaQ2mI/1IkSgdmlYWZh8towZUC/cwhIw= X-Received: by 2002:a05:6830:13d3:: with SMTP id e19mr11025372otq.135.1575638646107; Fri, 06 Dec 2019 05:24:06 -0800 (PST) MIME-Version: 1.0 References: <20191015163507.12153-1-richard.henderson@linaro.org> In-Reply-To: <20191015163507.12153-1-richard.henderson@linaro.org> From: Peter Maydell Date: Fri, 6 Dec 2019 13:23:55 +0000 Message-ID: Subject: Re: [PATCH 0/3] target/arm: Implement ARMv8.5-MemTag, user mode To: Richard Henderson Cc: QEMU Developers , elver@google.com, icb@rice.edu, qemu-arm Content-Type: text/plain; charset="UTF-8" X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::942 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 06 Dec 2019 14:21:37 -0000 On Tue, 15 Oct 2019 at 17:47, Richard Henderson wrote: > > This is a refresh of the user-only patch set from March. > > I do not attempt to implement any part of a kernel abi wrt mmap > and/or mprotect. Instead, it uses a x-tagged-pages property to > assume that all anonymous pages have tags. > > The tests added are disabled by default, but do pass if you have > binutils 2.32 installed. I'm going to skip reviewing this until we have a defined kernel ABI to compare against. thanks -- PMM From MAILER-DAEMON Fri Dec 06 09:25:10 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1idEXe-0002wr-Bw for mharc-qemu-arm@gnu.org; Fri, 06 Dec 2019 09:25:10 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:43240) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1idEXa-0002qv-E0 for qemu-arm@nongnu.org; Fri, 06 Dec 2019 09:25:08 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1idEXY-0007CL-9q for qemu-arm@nongnu.org; Fri, 06 Dec 2019 09:25:06 -0500 Received: from mail-ot1-x342.google.com ([2607:f8b0:4864:20::342]:33617) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1idEXW-000793-A0 for qemu-arm@nongnu.org; Fri, 06 Dec 2019 09:25:02 -0500 Received: by mail-ot1-x342.google.com with SMTP id d17so5963554otc.0 for ; Fri, 06 Dec 2019 06:25:01 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=8W6n0kR1bFwEF85pvn2wG6pk2VseIJva/P+1Sid05Ck=; b=C5BwTg0N0cLIemU9LmFGcOSdiqFyMuYJQZ5ZHKz0Cjn4bXHy3oNoY0TRgNcxkfLmlc abWDdeqGigWC4/qqEL+gGScnLmmbrdHbewdt3fn5+RnpIRQ0MYAdSnlNPEIixTQgQGYz n/QoZHFXTYWSGOW56fJJzOqVfCX2PALnpdaZ7ZteUrdaJwcrINbttNQ9weXd+lbEuTNJ WB98kIC6Wbyl2QplcvyLO2VcE9bhSaSIY08aC9YNo12pErbruZWIP7d6hVigkgEaZHF0 MoKe4cYRwJ9uQGmlhU1GDEV6+pwIIBEaYhg0y7Z31uaG9WkTgqh50O3S3ROKh6Sjcn8U rAUg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=8W6n0kR1bFwEF85pvn2wG6pk2VseIJva/P+1Sid05Ck=; b=e+WSJJmEfxxaUHCzNS8W9RKircD+zW8alym3QGebVfdM4Oq11C1nWxnC3HgCt4MmcL p739igOIE+whkT3+XUTR4qmHLrkd7IUSAr2JTwcts9C8sgnVBwAs5GWXexGTgIin3M8P C7XnS1eJAYezfrzgva4krcS+uHh4P+6eROs0rB7wETBeaURzSS8B4H/+yqas0BF1utJe zg9jkFepz6mP6XISr4R/JcbQ0PrkplbyyZ2+KlO1uXV7QpG7wzQWIUnBJj9mwZBL1hKt rcxVqQAX3pw8LYPyzqvo+9fozhxVpBLw/NBfgyQu3ztVNmmMIBs7Cd733KQVtthhBLJ6 GTnA== X-Gm-Message-State: APjAAAUqSjah6ImdyEmq4uXV5XwklSMOUKpeejKT0l6GaklJQFP21ANn 46iXYL+2pynso5IUZFTaT2OlVmwtpPSvzzRwyiEl0i+W X-Google-Smtp-Source: APXvYqzzTBy2ONOQ/mNa4QskKxAUjTeT3fk2vxqCng1mGL3g5x1Gp1TinrINyvb69lcPZ3/LKmU/9n2rg2Y7OlSrWrU= X-Received: by 2002:a05:6830:4a4:: with SMTP id l4mr5197606otd.91.1575642300952; Fri, 06 Dec 2019 06:25:00 -0800 (PST) MIME-Version: 1.0 References: <20191202210947.3603-1-nieklinnenbank@gmail.com> <20191202210947.3603-7-nieklinnenbank@gmail.com> In-Reply-To: <20191202210947.3603-7-nieklinnenbank@gmail.com> From: Peter Maydell Date: Fri, 6 Dec 2019 14:24:50 +0000 Message-ID: Subject: Re: [PATCH 06/10] arm/arm-powerctl: set NSACR.{CP11, CP10} bits in arm_set_cpu_on() To: Niek Linnenbank Cc: QEMU Developers , qemu-arm , Beniamino Galvani Content-Type: text/plain; charset="UTF-8" X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::342 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 06 Dec 2019 14:25:08 -0000 On Mon, 2 Dec 2019 at 21:10, Niek Linnenbank wrote: > > This change ensures that the FPU can be accessed in Non-Secure mode > when the CPU core is reset using the arm_set_cpu_on() function call. > The NSACR.{CP11,CP10} bits define the exception level required to > access the FPU in Non-Secure mode. Without these bits set, the CPU > will give an undefined exception trap on the first FPU access for the > secondary cores under Linux. > > Fixes: fc1120a7f5 > Signed-off-by: Niek Linnenbank > --- Oops, another place where we failed to realise the ramifications of making NSACR actually do something. Since this is a bugfix I'm going to fish it out of this patchset and apply it to target-arm.next with a cc: stable. Thanks for the catch! -- PMM From MAILER-DAEMON Fri Dec 06 09:26:11 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1idEYd-00041f-Lk for mharc-qemu-arm@gnu.org; Fri, 06 Dec 2019 09:26:11 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:46390) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1idEYb-0003xW-2Q for qemu-arm@nongnu.org; Fri, 06 Dec 2019 09:26:10 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1idEYY-0000mh-GI for qemu-arm@nongnu.org; Fri, 06 Dec 2019 09:26:08 -0500 Received: from us-smtp-1.mimecast.com ([207.211.31.81]:51258 helo=us-smtp-delivery-1.mimecast.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1idEYY-0000ip-Ao for qemu-arm@nongnu.org; Fri, 06 Dec 2019 09:26:06 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1575642364; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding; bh=RVrvv9IFtOxf7TVu5YfYeIqWyis1fMQehJN3vG2vBTg=; b=hZsdfzpougtu8kcBQiAxuTeOuqmDtlQSbTRL4Ct4qqKBeSBprFK1F5yT0ru7vC/yG3D9K6 1iUPmoEjPEVJlPW6iQNth2R3PwJS/CDYG7qLfPrL7FOt9LPnaIjLXlUZ38V4RCffbgql3h Bx26SkqIqa2z2WEzNEGZWwf6qyQj7QM= Received: from mimecast-mx01.redhat.com (mimecast-mx01.redhat.com [209.132.183.4]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-431-u2CuVsTvOYaalhZ8yW_cuA-1; Fri, 06 Dec 2019 02:23:06 -0500 Received: from smtp.corp.redhat.com (int-mx08.intmail.prod.int.phx2.redhat.com [10.5.11.23]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx01.redhat.com (Postfix) with ESMTPS id 3B900DB20; Fri, 6 Dec 2019 07:23:05 +0000 (UTC) Received: from x1w.redhat.com (ovpn-204-212.brq.redhat.com [10.40.204.212]) by smtp.corp.redhat.com (Postfix) with ESMTPS id 8F49B19C4F; Fri, 6 Dec 2019 07:23:00 +0000 (UTC) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Leif Lindholm , Radoslaw Biernacki , qemu-arm@nongnu.org, Peter Maydell , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH-for-5.0] hw/arm/sbsa-ref: Call qdev_get_gpio_in in place Date: Fri, 6 Dec 2019 08:22:57 +0100 Message-Id: <20191206072257.7221-1-philmd@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.84 on 10.5.11.23 X-MC-Unique: u2CuVsTvOYaalhZ8yW_cuA-1 X-Mimecast-Spam-Score: 0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 207.211.31.81 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 06 Dec 2019 14:26:11 -0000 Instead of filling an array of qemu_irq and passing it around, directly call qdev_get_gpio_in() on the GIC. Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- I accept better patch subject suggestions :) --- hw/arm/sbsa-ref.c | 58 +++++++++++++++++++++++------------------------ 1 file changed, 29 insertions(+), 29 deletions(-) diff --git a/hw/arm/sbsa-ref.c b/hw/arm/sbsa-ref.c index 27046cc284..30cb647551 100644 --- a/hw/arm/sbsa-ref.c +++ b/hw/arm/sbsa-ref.c @@ -328,7 +328,7 @@ static void create_secure_ram(SBSAMachineState *sms, memory_region_add_subregion(secure_sysmem, base, secram); } =20 -static void create_gic(SBSAMachineState *sms, qemu_irq *pic) +static DeviceState *create_gic(SBSAMachineState *sms) { unsigned int smp_cpus =3D MACHINE(sms)->smp.cpus; DeviceState *gicdev; @@ -403,12 +403,10 @@ static void create_gic(SBSAMachineState *sms, qemu_ir= q *pic) qdev_get_gpio_in(cpudev, ARM_CPU_VFIQ)); } =20 - for (i =3D 0; i < NUM_IRQS; i++) { - pic[i] =3D qdev_get_gpio_in(gicdev, i); - } + return gicdev; } =20 -static void create_uart(const SBSAMachineState *sms, qemu_irq *pic, int ua= rt, +static void create_uart(const SBSAMachineState *sms, DeviceState *gic, int= uart, MemoryRegion *mem, Chardev *chr) { hwaddr base =3D sbsa_ref_memmap[uart].base; @@ -420,15 +418,15 @@ static void create_uart(const SBSAMachineState *sms, = qemu_irq *pic, int uart, qdev_init_nofail(dev); memory_region_add_subregion(mem, base, sysbus_mmio_get_region(s, 0)); - sysbus_connect_irq(s, 0, pic[irq]); + sysbus_connect_irq(s, 0, qdev_get_gpio_in(gic, irq)); } =20 -static void create_rtc(const SBSAMachineState *sms, qemu_irq *pic) +static void create_rtc(const SBSAMachineState *sms, DeviceState *gic) { hwaddr base =3D sbsa_ref_memmap[SBSA_RTC].base; int irq =3D sbsa_ref_irqmap[SBSA_RTC]; =20 - sysbus_create_simple("pl031", base, pic[irq]); + sysbus_create_simple("pl031", base, qdev_get_gpio_in(gic, irq)); } =20 static DeviceState *gpio_key_dev; @@ -442,13 +440,13 @@ static Notifier sbsa_ref_powerdown_notifier =3D { .notify =3D sbsa_ref_powerdown_req }; =20 -static void create_gpio(const SBSAMachineState *sms, qemu_irq *pic) +static void create_gpio(const SBSAMachineState *sms, DeviceState *gic) { DeviceState *pl061_dev; hwaddr base =3D sbsa_ref_memmap[SBSA_GPIO].base; int irq =3D sbsa_ref_irqmap[SBSA_GPIO]; =20 - pl061_dev =3D sysbus_create_simple("pl061", base, pic[irq]); + pl061_dev =3D sysbus_create_simple("pl061", base, qdev_get_gpio_in(gic= , irq)); =20 gpio_key_dev =3D sysbus_create_simple("gpio-key", -1, qdev_get_gpio_in(pl061_dev, 3)); @@ -457,7 +455,7 @@ static void create_gpio(const SBSAMachineState *sms, qe= mu_irq *pic) qemu_register_powerdown_notifier(&sbsa_ref_powerdown_notifier); } =20 -static void create_ahci(const SBSAMachineState *sms, qemu_irq *pic) +static void create_ahci(const SBSAMachineState *sms, DeviceState *gic) { hwaddr base =3D sbsa_ref_memmap[SBSA_AHCI].base; int irq =3D sbsa_ref_irqmap[SBSA_AHCI]; @@ -471,7 +469,7 @@ static void create_ahci(const SBSAMachineState *sms, qe= mu_irq *pic) qdev_prop_set_uint32(dev, "num-ports", NUM_SATA_PORTS); qdev_init_nofail(dev); sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base); - sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, pic[irq]); + sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, qdev_get_gpio_in(gic, irq))= ; =20 sysahci =3D SYSBUS_AHCI(dev); ahci =3D &sysahci->ahci; @@ -484,15 +482,15 @@ static void create_ahci(const SBSAMachineState *sms, = qemu_irq *pic) } } =20 -static void create_ehci(const SBSAMachineState *sms, qemu_irq *pic) +static void create_ehci(const SBSAMachineState *sms, DeviceState *gic) { hwaddr base =3D sbsa_ref_memmap[SBSA_EHCI].base; int irq =3D sbsa_ref_irqmap[SBSA_EHCI]; =20 - sysbus_create_simple("platform-ehci-usb", base, pic[irq]); + sysbus_create_simple("platform-ehci-usb", base, qdev_get_gpio_in(gic, = irq)); } =20 -static void create_smmu(const SBSAMachineState *sms, qemu_irq *pic, +static void create_smmu(const SBSAMachineState *sms, DeviceState *gic, PCIBus *bus) { hwaddr base =3D sbsa_ref_memmap[SBSA_SMMU].base; @@ -507,11 +505,12 @@ static void create_smmu(const SBSAMachineState *sms, = qemu_irq *pic, qdev_init_nofail(dev); sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base); for (i =3D 0; i < NUM_SMMU_IRQS; i++) { - sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, pic[irq + i]); + sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, + qdev_get_gpio_in(gic, irq + 1)); } } =20 -static void create_pcie(SBSAMachineState *sms, qemu_irq *pic) +static void create_pcie(SBSAMachineState *sms, DeviceState *gic) { hwaddr base_ecam =3D sbsa_ref_memmap[SBSA_PCIE_ECAM].base; hwaddr size_ecam =3D sbsa_ref_memmap[SBSA_PCIE_ECAM].size; @@ -555,7 +554,8 @@ static void create_pcie(SBSAMachineState *sms, qemu_irq= *pic) sysbus_mmio_map(SYS_BUS_DEVICE(dev), 2, base_pio); =20 for (i =3D 0; i < GPEX_NUM_IRQS; i++) { - sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, pic[irq + i]); + sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, + qdev_get_gpio_in(gic, irq + 1)); gpex_set_irq_num(GPEX_HOST(dev), i, irq + i); } =20 @@ -574,7 +574,7 @@ static void create_pcie(SBSAMachineState *sms, qemu_irq= *pic) =20 pci_create_simple(pci->bus, -1, "VGA"); =20 - create_smmu(sms, pic, pci->bus); + create_smmu(sms, gic, pci->bus); } =20 static void *sbsa_ref_dtb(const struct arm_boot_info *binfo, int *fdt_size= ) @@ -598,7 +598,7 @@ static void sbsa_ref_init(MachineState *machine) bool firmware_loaded; const CPUArchIdList *possible_cpus; int n, sbsa_max_cpus; - qemu_irq pic[NUM_IRQS]; + DeviceState *gic; =20 if (strcmp(machine->cpu_type, ARM_CPU_TYPE_NAME("cortex-a57"))) { error_report("sbsa-ref: CPU type other than the built-in " @@ -695,22 +695,22 @@ static void sbsa_ref_init(MachineState *machine) =20 create_secure_ram(sms, secure_sysmem); =20 - create_gic(sms, pic); + gic =3D create_gic(sms); =20 - create_uart(sms, pic, SBSA_UART, sysmem, serial_hd(0)); - create_uart(sms, pic, SBSA_SECURE_UART, secure_sysmem, serial_hd(1)); + create_uart(sms, gic, SBSA_UART, sysmem, serial_hd(0)); + create_uart(sms, gic, SBSA_SECURE_UART, secure_sysmem, serial_hd(1)); /* Second secure UART for RAS and MM from EL0 */ - create_uart(sms, pic, SBSA_SECURE_UART_MM, secure_sysmem, serial_hd(2)= ); + create_uart(sms, gic, SBSA_SECURE_UART_MM, secure_sysmem, serial_hd(2)= ); =20 - create_rtc(sms, pic); + create_rtc(sms, gic); =20 - create_gpio(sms, pic); + create_gpio(sms, gic); =20 - create_ahci(sms, pic); + create_ahci(sms, gic); =20 - create_ehci(sms, pic); + create_ehci(sms, gic); =20 - create_pcie(sms, pic); + create_pcie(sms, gic); =20 sms->bootinfo.ram_size =3D machine->ram_size; sms->bootinfo.nb_cpus =3D smp_cpus; --=20 2.21.0 From MAILER-DAEMON Fri Dec 06 09:28:12 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1idEaa-0005qv-C6 for mharc-qemu-arm@gnu.org; Fri, 06 Dec 2019 09:28:12 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:52628) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1idEaT-0005dl-RG for qemu-arm@nongnu.org; Fri, 06 Dec 2019 09:28:10 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1idEaS-0006O9-LP for qemu-arm@nongnu.org; Fri, 06 Dec 2019 09:28:05 -0500 Received: from mail-ot1-x341.google.com ([2607:f8b0:4864:20::341]:44935) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1idEaS-0006Hl-Eg for qemu-arm@nongnu.org; Fri, 06 Dec 2019 09:28:04 -0500 Received: by mail-ot1-x341.google.com with SMTP id x3so5886331oto.11 for ; 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Fri, 06 Dec 2019 06:28:02 -0800 (PST) MIME-Version: 1.0 References: <20191202210947.3603-1-nieklinnenbank@gmail.com> <20191202210947.3603-9-nieklinnenbank@gmail.com> In-Reply-To: <20191202210947.3603-9-nieklinnenbank@gmail.com> From: Peter Maydell Date: Fri, 6 Dec 2019 14:27:51 +0000 Message-ID: Subject: Re: [PATCH 08/10] arm: allwinner-h3: add Security Identifier device To: Niek Linnenbank Cc: QEMU Developers , qemu-arm , Beniamino Galvani Content-Type: text/plain; charset="UTF-8" X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::341 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 06 Dec 2019 14:28:11 -0000 On Mon, 2 Dec 2019 at 21:10, Niek Linnenbank wrote: > > The Security Identifier device in Allwinner H3 System on Chip > gives applications a per-board unique identifier. This commit > adds support for the Allwinner H3 Security Identifier using > randomized data as input. If this is a fixed value in hardware, I'm not sure that having the QEMU model pick a random value is the best choice. If we just set it to a fixed value in QEMU, is that going to cause problems? (Generally it's nice for QEMU to be deterministic, so it behaves the same way every time you run it. Also if it's always the same we don't need to bother migrating the ID value.) thanks -- PMM From MAILER-DAEMON Fri Dec 06 09:47:22 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1idEt7-0000Mc-U4 for mharc-qemu-arm@gnu.org; Fri, 06 Dec 2019 09:47:21 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:54483) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1idEsx-0000Id-9t for qemu-arm@nongnu.org; Fri, 06 Dec 2019 09:47:13 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1idEss-0003aa-0x for qemu-arm@nongnu.org; Fri, 06 Dec 2019 09:47:07 -0500 Received: from mail-oi1-x243.google.com ([2607:f8b0:4864:20::243]:42992) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1idEsr-0003Zm-Qv for qemu-arm@nongnu.org; Fri, 06 Dec 2019 09:47:05 -0500 Received: by mail-oi1-x243.google.com with SMTP id j22so6340899oij.9 for ; Fri, 06 Dec 2019 06:47:05 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=uhSPlg+i9CiAubF7ClC0ww2vNy2qAmWgFnaNVgQgOxE=; b=zzsj35yd960LbiaSBcl/usD7GRpWOsvW98l1RP+jhOWQfLebIUn2wV2+T9mfupbxch e93nHD4TZJlfhk5O0kSjTqVQ9kAmqFigsdzw6vbxNcKNbYHGBBJR4WtLJnOtCYmfeiWN Oc+Mal+rpJUHvmiVerGR7FkUHafsoCh0ZCI/9hWqOsB9KukvjFnW74gfHF3KczHaYLWp 90mLdshDyOYx7g1tE/o7HSHRWfK5XlNlhEZz7D2BrQGNv608xXmdvKJr0jGdZnhSOT91 Ecuk55bLRIX9g6M3EnNxsdA5sxTN0qkNTXzWj7muhFqvRD2MpCWlWU466cSZdN2ZMZ9+ 5LRg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=uhSPlg+i9CiAubF7ClC0ww2vNy2qAmWgFnaNVgQgOxE=; b=CfliYpiaVJNjIyishRCbF0rV6H/jbCRXOCFiFecAlKKKKEP07jxsPJIbUXIqK39+Ji z6aWtY7QPDh4ef5CWBNjsl1kmRZxiTORhVty3NhVL/3VGXS2Og6YbeQLqAuCU+/04pAc Ku0ZvTzUh7l4M37duvfUkzm9iQdqhaiEqNqYIvyJh7Z6ulCBo6F8eaMxWrSTbFI5QBgV ECLwTIf3CYfBhDwXwuQrSE/Z2zmcHkyoSZ0nYfzpbuvc4c+6o5gKxV7ZTwEMI9TR4nGy HGlTMr6Qux/Qs5g7vv8FSqC5HBIcQkPzW7NWZ7y+PCF7PybjVQp1iTZs8K2bHd0dPR7V DwGw== X-Gm-Message-State: APjAAAWGvroVySCYaDyMXX3F+uGFsOpLu8f8NqEJDf4DSG5RP7z0OI+U vuGhMdEiQK62fHzKmYnb7eXjGLGEN5poCRueFpJ//s9P X-Google-Smtp-Source: APXvYqw2gpZf9eGRHwCYCA4+iyO+tNdoHE1d4WU9umvAw5Ya5N+sNHgm4KB59ivtXp+w1i5oD9gVxA0jXOWo5q4I3vU= X-Received: by 2002:aca:edd5:: with SMTP id l204mr12121697oih.98.1575632772773; Fri, 06 Dec 2019 03:46:12 -0800 (PST) MIME-Version: 1.0 References: <20191011134744.2477-1-richard.henderson@linaro.org> <20191011134744.2477-22-richard.henderson@linaro.org> In-Reply-To: <20191011134744.2477-22-richard.henderson@linaro.org> From: Peter Maydell Date: Fri, 6 Dec 2019 11:46:02 +0000 Message-ID: Subject: Re: [PATCH v5 21/22] target/arm: Add mmu indexes for tag memory To: Richard Henderson Cc: QEMU Developers , qemu-arm Content-Type: text/plain; charset="UTF-8" X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::243 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 06 Dec 2019 14:47:13 -0000 On Fri, 11 Oct 2019 at 14:50, Richard Henderson wrote: > > The process by which one goes from an address space plus physical > address to a host pointer is complex. It is easiest to reuse the > mechanism already present within cputlb, and letting that cache > the results. > > Signed-off-by: Richard Henderson > --- > target/arm/cpu-param.h | 2 +- > target/arm/cpu.h | 12 +++++++++--- > target/arm/internals.h | 2 ++ > target/arm/helper.c | 25 +++++++++++++++++++++++-- > 4 files changed, 35 insertions(+), 6 deletions(-) > > diff --git a/target/arm/cpu-param.h b/target/arm/cpu-param.h > index 6e6948e960..18ac562346 100644 > --- a/target/arm/cpu-param.h > +++ b/target/arm/cpu-param.h > @@ -29,6 +29,6 @@ > # define TARGET_PAGE_BITS_MIN 10 > #endif > > -#define NB_MMU_MODES 8 > +#define NB_MMU_MODES 9 > > #endif > diff --git a/target/arm/cpu.h b/target/arm/cpu.h > index faca43ea78..c3609ef9d5 100644 > --- a/target/arm/cpu.h > +++ b/target/arm/cpu.h > @@ -2854,8 +2854,8 @@ static inline bool arm_excp_unmasked(CPUState *cs, unsigned int excp_idx, > #define ARM_MMU_IDX_M_NEGPRI 0x2 > #define ARM_MMU_IDX_M_S 0x4 > > -#define ARM_MMU_IDX_TYPE_MASK (~0x7) > -#define ARM_MMU_IDX_COREIDX_MASK 0x7 > +#define ARM_MMU_IDX_TYPE_MASK (~0xf) > +#define ARM_MMU_IDX_COREIDX_MASK 0xf > > typedef enum ARMMMUIdx { > ARMMMUIdx_S12NSE0 = 0 | ARM_MMU_IDX_A, > @@ -2865,6 +2865,9 @@ typedef enum ARMMMUIdx { > ARMMMUIdx_S1SE0 = 4 | ARM_MMU_IDX_A, > ARMMMUIdx_S1SE1 = 5 | ARM_MMU_IDX_A, > ARMMMUIdx_S2NS = 6 | ARM_MMU_IDX_A, > + ARMMMUIdx_TagNS = 7 | ARM_MMU_IDX_A, > + ARMMMUIdx_TagS = 8 | ARM_MMU_IDX_A, > + > ARMMMUIdx_MUser = 0 | ARM_MMU_IDX_M, > ARMMMUIdx_MPriv = 1 | ARM_MMU_IDX_M, > ARMMMUIdx_MUserNegPri = 2 | ARM_MMU_IDX_M, > @@ -2891,6 +2894,8 @@ typedef enum ARMMMUIdxBit { > ARMMMUIdxBit_S1SE0 = 1 << 4, > ARMMMUIdxBit_S1SE1 = 1 << 5, > ARMMMUIdxBit_S2NS = 1 << 6, > + ARMMMUIdxBit_TagNS = 1 << 7, > + ARMMMUIdxBit_TagS = 1 << 8, > ARMMMUIdxBit_MUser = 1 << 0, > ARMMMUIdxBit_MPriv = 1 << 1, > ARMMMUIdxBit_MUserNegPri = 1 << 2, > @@ -3254,7 +3259,8 @@ enum { > /* Return the address space index to use for a memory access */ > static inline int arm_asidx_from_attrs(CPUState *cs, MemTxAttrs attrs) > { > - return attrs.secure ? ARMASIdx_S : ARMASIdx_NS; > + return ((attrs.target_tlb_bit2 ? ARMASIdx_TagNS : ARMASIdx_NS) > + + attrs.secure); If you want to do the "just add attrs.secure" can we have a build-time assert that ARMASIdx_S is ARMASIdx_NS + 1, and ditto for TagNS/TagS, please? It seems like the kind of thing that will catch us out later on. > } > if (env->cp15.hcr_el2 & HCR_TGE) { > @@ -10662,7 +10671,9 @@ bool get_phys_addr(CPUARMState *env, target_ulong address, > target_ulong *page_size, > ARMMMUFaultInfo *fi, ARMCacheAttrs *cacheattrs) > { > - if (mmu_idx == ARMMMUIdx_S12NSE0 || mmu_idx == ARMMMUIdx_S12NSE1) { > + switch (mmu_idx) { > + case ARMMMUIdx_S12NSE0: > + case ARMMMUIdx_S12NSE1: > /* Call ourselves recursively to do the stage 1 and then stage 2 > * translations. > */ > @@ -10713,6 +10724,16 @@ bool get_phys_addr(CPUARMState *env, target_ulong address, > */ > mmu_idx = stage_1_mmu_idx(mmu_idx); > } > + break; > + > + case ARMMMUIdx_TagS: > + case ARMMMUIdx_TagNS: > + /* Indicate tag memory to arm_asidx_from_attrs. */ > + attrs->target_tlb_bit2 = true; > + break; So here we fall through to the "handle a stage 1 lookup" code, which: * sets attrs->secure * sets attrs->user (always false, so we could have left it alone) * skips the FCSE handling (as we're v8) * skips the PMSA handling * hits the regime_translation_disabled() check, which fills in *phys_ptr, *prot and *page_size and returns Maybe it would be clearer if this case here just did all of that: case ARMMMUIdx_TagS: attrs->secure = true; /* fall through */ case ARMMMUIdx_TagNS: /* Indicate tag memory to arm_asidx_from_attrs. */ attrs->target_tlb_bit2 = true; *phys_ptr = address; *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC; *page_size = TARGET_PAGE_SIZE; return 0; Did I miss anything out? Or are we going to want more things which are common between the stage 1 codepath and the "just a tag ram access" case in future? thanks -- PMM From MAILER-DAEMON Fri Dec 06 09:47:29 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1idEtE-0000S3-Bp for mharc-qemu-arm@gnu.org; Fri, 06 Dec 2019 09:47:28 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:54674) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1idEt9-0000Nz-F8 for qemu-arm@nongnu.org; Fri, 06 Dec 2019 09:47:25 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1idEt6-0003l5-Td for qemu-arm@nongnu.org; Fri, 06 Dec 2019 09:47:22 -0500 Received: from mail-pj1-x1041.google.com ([2607:f8b0:4864:20::1041]:45522) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1idEt6-0003dq-C7 for qemu-arm@nongnu.org; Fri, 06 Dec 2019 09:47:20 -0500 Received: by mail-pj1-x1041.google.com with SMTP id r11so2826313pjp.12 for ; Fri, 06 Dec 2019 06:47:09 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=subject:to:cc:references:from:message-id:date:user-agent :mime-version:in-reply-to:content-language:content-transfer-encoding; bh=Ou2NIgpCqpSNreFVd54xN+SCEb16nwgso+pX/SawtfY=; b=Fd8OvthmQkw/GsY6S905ylcQrpZ884BcwuhMOHSNo3zAU6sVr6aJsKGQ6sTxDKHTvM pTMYt8b9JFDOSQq26xLJGTitsjohWxFB2O27kHIUvIvxtR/WXWcCTR4dasGUkm6BdFa7 zfwh2dx0/R4YnOQNj59d3zlRuMs6G04Wz1jDAMSaja33x4jxctSgQrykxGQcz2+nACgp sgnPomnHoj0w0624Q67w8RnJdMejqRWI8ymO+s+BLS9Y78pV7ru8KIImDlY6l+AGD9nn XF4+wSFsllcXoge+1N7BtZ0gFeSF05PdEcCLO/pFKg1N5slAFOaFvUOpIsa5PWeGDHgR lRZQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:subject:to:cc:references:from:message-id:date :user-agent:mime-version:in-reply-to:content-language :content-transfer-encoding; bh=Ou2NIgpCqpSNreFVd54xN+SCEb16nwgso+pX/SawtfY=; b=Bhwe2GHBHOsEPoAsXZG8/+kidtRYOKKsAfY0TWebYmCi8JVfDa9DwDMQ3VKH9gFP1F vmvOHZ5iTM+Y1ofvPU+KQNQO5n3gawP6bl20y84fMz3zPWI7SrOwoG80hXZ0marbAQp6 wUuoh3syCfH58cZVOimczwjUZhqkd3Ap6GFXDyxPPQ3kBYZabQVXZswjLL+BHbkk37FH sxrvqDp3+NLz8AtCRqY+XRNUt/rJ/v5EOYFvpCEAqmqTAojyWwruXAQA/VfBgLW8m29B ncEi8A3N7TfKEj2iDtDGBFGSOOUSA5KT+TIELKR56MJj9tfrXjF/Xl1UrxmiN1q4vFeo rMow== X-Gm-Message-State: APjAAAXbdSThwCK1gfSmG9Qk/dnTRaYh2mJBE2UXYWH09xH1B861uSkN U6qHvibeZEzWONDEf93AjdfQRh26HLg= X-Google-Smtp-Source: APXvYqxLD0LwUBKhDzrDEj45ePVTacM/K10xf/6cqmiMz3a6bF5fvPqlELND7WgSc9RRnQLi/CLk6Q== X-Received: by 2002:a17:90b:f06:: with SMTP id br6mr2226536pjb.125.1575643628749; Fri, 06 Dec 2019 06:47:08 -0800 (PST) Received: from [192.168.1.11] (97-113-7-119.tukw.qwest.net. [97.113.7.119]) by smtp.gmail.com with ESMTPSA id a22sm17794578pfk.108.2019.12.06.06.47.07 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 06 Dec 2019 06:47:07 -0800 (PST) Subject: Re: [PATCH v5 03/22] target/arm: Add MTE system registers To: Peter Maydell Cc: QEMU Developers , qemu-arm References: <20191011134744.2477-1-richard.henderson@linaro.org> <20191011134744.2477-4-richard.henderson@linaro.org> From: Richard Henderson Message-ID: <597e1b27-24df-164e-d289-f8d8bb69f0c3@linaro.org> Date: Fri, 6 Dec 2019 06:47:05 -0800 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.2.1 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 7bit X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::1041 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 06 Dec 2019 14:47:25 -0000 On 12/3/19 3:48 AM, Peter Maydell wrote: >> + { .name = "GMID_EL1", .state = ARM_CP_STATE_AA64, >> + .opc0 = 3, .opc1 = 1, .crn = 0, .crm = 0, .opc2 = 4, >> + .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = GMID_EL1_BS }, > > This should trap if HCR_EL2.TID5 is 1 (since we're adding > support for the TID* ID reg trap bits now). Done. > So, aa64_mte_insn_reg here is checking for ID_AA64PFR1_EL1 != 0 > ("instructions accessible at EL0 are implemented") > and aa64_mte is checking for >= 2 ("full implementation"). > I think a couple of brief comments would clarify: Done. > (The other way to arrange this would be to have the 'real' > TCO regdef in mte_reginfo, and separately have "reginfo > if we only have the dummy visible-from-EL0-parts-only > which defines a constant 0 TCO" (and also make the MSR_i > code implement a RAZ/WI for this case, for consistency). Done. I agree this is a better way to treat the EL0-only case... > An implementation that allows the guest to toggle the PSTATE.TCO > bit to no visible effect is architecturally valid, though. ... because this could turn out to be slightly confusing. r~ From MAILER-DAEMON Fri Dec 06 09:47:32 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1idEtH-0000UY-5j for mharc-qemu-arm@gnu.org; Fri, 06 Dec 2019 09:47:31 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:54762) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1idEtC-0000QK-F6 for qemu-arm@nongnu.org; Fri, 06 Dec 2019 09:47:27 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1idEt8-0003mu-V3 for qemu-arm@nongnu.org; Fri, 06 Dec 2019 09:47:24 -0500 Received: from us-smtp-delivery-1.mimecast.com ([205.139.110.120]:29450 helo=us-smtp-1.mimecast.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1idEt6-0003g4-T5 for qemu-arm@nongnu.org; Fri, 06 Dec 2019 09:47:21 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1575643633; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=S7puR9cKXQmceadF8aHitsChjwoUelc3PuZxZ7OsHwg=; b=LkESELtyd20bLdAWIKyWAaczTpoPFYQmqPoGon0XwwvxBgcldRsbXAi3Q45OiApygVk0cI yyJgzKPdMz6D7Yn4hXoHv+t71yzczPDPSwQnL6D1yU1mVJkfncIbNV7g3Mv6lj56+VCjbp yZa7yBNg28Coo71XV2pcD/mX4zRXwFU= Received: from mimecast-mx01.redhat.com (mimecast-mx01.redhat.com [209.132.183.4]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-394-MMCP8qYbNLKcimh9pfhsYw-1; Fri, 06 Dec 2019 07:46:24 -0500 Received: from smtp.corp.redhat.com (int-mx03.intmail.prod.int.phx2.redhat.com [10.5.11.13]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx01.redhat.com (Postfix) with ESMTPS id 7D68F800EB9; Fri, 6 Dec 2019 12:46:22 +0000 (UTC) Received: from dhcp-17-72.bos.redhat.com (dhcp-17-72.bos.redhat.com [10.18.17.72]) by smtp.corp.redhat.com (Postfix) with ESMTPS id 8A38567E52; Fri, 6 Dec 2019 12:46:14 +0000 (UTC) Date: Fri, 6 Dec 2019 07:46:13 -0500 From: Cleber Rosa To: Philippe =?iso-8859-1?Q?Mathieu-Daud=E9?= Cc: "Dr. David Alan Gilbert" , Peter Maydell , Alex =?iso-8859-1?Q?Benn=E9e?= , Richard Henderson , Damien Hedde , QEMU Developers , Mark Burton , "Edgar E. Iglesias" , Alistair Francis , =?iso-8859-1?Q?Marc-Andr=E9?= Lureau , Paolo Bonzini , "Daniel P. Berrange" , Eduardo Habkost , qemu-arm , Oksana Voshchana Subject: Re: [PATCH v6 0/9] Clock framework API Message-ID: <20191206124613.GA3902@dhcp-17-72.bos.redhat.com> References: <20190904125531.27545-1-damien.hedde@greensocs.com> <279a0fd5-1ea5-b3c7-27bb-b1d22db5e359@redhat.com> <20191205102151.GB2824@work-vm> <20191205105613.GE2824@work-vm> <138ef325-dc9a-2ca5-9044-c67ffdabb968@redhat.com> MIME-Version: 1.0 In-Reply-To: <138ef325-dc9a-2ca5-9044-c67ffdabb968@redhat.com> User-Agent: Mutt/1.12.1 (2019-06-15) X-Scanned-By: MIMEDefang 2.79 on 10.5.11.13 X-MC-Unique: MMCP8qYbNLKcimh9pfhsYw-1 X-Mimecast-Spam-Score: 0 Content-Type: text/plain; charset=iso-8859-1 Content-Transfer-Encoding: quoted-printable Content-Disposition: inline X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 205.139.110.120 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 06 Dec 2019 14:47:29 -0000 On Thu, Dec 05, 2019 at 12:01:56PM +0100, Philippe Mathieu-Daud=E9 wrote: >=20 > Understood, thanks for clearing this out! >=20 > Side note, we don't do cross-arch migration testing, but we talked about > having a 'different QEMU version' migration test. When we get a such test > setup, it shouldn't be too difficult to evolve to some cross-arch migrati= on > test. > +Oksana, Avocado-VT has had this as a core concept as far as I can remember, and it's exposed even as a command line argument: avocado run --help ... [--vt-qemu-dst-bin VT_DST_QEMU_BIN] ... Oksana is currently working on new migration test cases, and may consider looking into adding "different QEMU version" support too. PS: I have to say, though, that I'm trying to get my mind around cross-arch migration being real. - Cleber. > > > I hope I'm wrong and confuse, this is a great news for me to know we > > > can migrate floats! > > >=20 > > > > Dave > > > >=20 > > > > > > So we could store the frequency in clock out and migrate things= there. > > > > > > But since we have no way to ensure all clock out states are mig= rated > > > > > > before some device fetch a ClockIn: we'll have to say "don't fe= tch one > > > > > > of your ClockIn frequency during migration and migrate the valu= e > > > > > > yourself if you need it", pretty much like gpios. > > > > > >=20 > > > > > > So we will probably migrate all ClockOut and almost all ClockIn= . > > > > > >=20 > > > > > > It would nice if we had a way to ensure clocks are migrated bef= ore > > > > > > devices try to use them. But I don't think this is possible. > > > > > >=20 > > > > > > -- > > > > > > Damien > > > > > >=20 > > > > >=20 > > > > -- > > > > Dr. David Alan Gilbert / dgilbert@redhat.com / Manchester, UK > > > >=20 > > >=20 > > -- > > Dr. David Alan Gilbert / dgilbert@redhat.com / Manchester, UK > >=20 >=20 From MAILER-DAEMON Fri Dec 06 09:52:51 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1idEyR-0007t5-2R for mharc-qemu-arm@gnu.org; Fri, 06 Dec 2019 09:52:51 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:56660) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1idEyN-0007nz-Q1 for qemu-arm@nongnu.org; Fri, 06 Dec 2019 09:52:48 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1idEyM-0004bt-DS for qemu-arm@nongnu.org; Fri, 06 Dec 2019 09:52:47 -0500 Received: from mail-wm1-x342.google.com ([2a00:1450:4864:20::342]:38191) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1idEyM-0004a2-5i for qemu-arm@nongnu.org; Fri, 06 Dec 2019 09:52:46 -0500 Received: by mail-wm1-x342.google.com with SMTP id p17so7620658wmi.3 for ; Fri, 06 Dec 2019 06:52:45 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=references:user-agent:from:to:cc:subject:in-reply-to:date :message-id:mime-version:content-transfer-encoding; bh=v6DcG/q6LskpbU7+BFpd5NgSOoqBfxqnbb2+YKX0aUU=; b=RixRN66mTzjNLzw9/wdPdDaNncVowkyByDe/xaqpM/KmZNGasB7wRnpNmfW/4srtur fiqyX5Y7ydd9imOTRThsz9GEvgGWBMOHcV9mBhEe70hAysgwD92CmOXtPqJtUael66LR Rq3YHSgAokb+H//hg+22sXSsDCpOfLLlIvKEFeI3GufhOWcIps03v+pmNxaIQ1wY04m6 Cb5duFEAuDk60tFczQ+NZtiImGKLYa1DdjyxOHQ7MuxV8S98T9q3wN4F0DCUbADLbgiE QJ9E4i0O281UfgsFLtS+97xeMq9wS0nkpkoTXgBUwoZxF5N8UF5GP4xZ5U9h0UkO5x9p KCMw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:references:user-agent:from:to:cc:subject :in-reply-to:date:message-id:mime-version:content-transfer-encoding; bh=v6DcG/q6LskpbU7+BFpd5NgSOoqBfxqnbb2+YKX0aUU=; b=SbLjbVFp1aFX0k+aSPz9VmTQ+s9h53OhSi+SXhCMet1uQBgnWh/Vh2Qrtvp0A8nLPt MqbyZiqqGAUZJb0jzzPkDJDDzCphD7nuK9O9M8e/WuuE+ezUfHv9nq20ZIUkXlnz4Y4l Clxwr9qLamq70BQZXUYOAVR4scY4B2CRBJLR9F0D7CIgTrQg8nYMCHL7vfeu5VPSQDqp g6adCF/EwyuwlKj2Oew5d15OnOadzLD4/9iowpG+yslALvQQzuqbDsrg+7FYBhLlzZ6y Bl/bDDUQnc9JXeh3UtDG7rqqsbhFOny4JIS7CDbCHQyceEZTKia0jNUXg1cQ4wcj6Dp7 ihkg== X-Gm-Message-State: APjAAAWoTQHCE8b38njvk8/4byaeUGL4T3w5nUgZRpqc0tH4Zxewv/7C Y3PI1nk/NHccU3Wke2RXse4Rfw== X-Google-Smtp-Source: APXvYqxg7JhQmObIGzYli6D55JfJngNCGYSXmxKga1NucZL6ha6xidbWhOpKpPcEQG3uFzTnfVZUWw== X-Received: by 2002:a1c:7419:: with SMTP id p25mr10546332wmc.129.1575643964831; Fri, 06 Dec 2019 06:52:44 -0800 (PST) Received: from zen.linaroharston ([51.148.130.216]) by smtp.gmail.com with ESMTPSA id n16sm16506771wro.88.2019.12.06.06.52.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 06 Dec 2019 06:52:43 -0800 (PST) Received: from zen (localhost [127.0.0.1]) by zen.linaroharston (Postfix) with ESMTP id DF7701FF87; Fri, 6 Dec 2019 14:52:42 +0000 (GMT) References: <20191130084602.10818-1-alex.bennee@linaro.org> <20191130084602.10818-12-alex.bennee@linaro.org> <9362663d-6452-39aa-2a8d-1cfd853d7faa@linaro.org> <87o8wm7k6v.fsf@linaro.org> User-agent: mu4e 1.3.5; emacs 27.0.50 From: Alex =?utf-8?Q?Benn=C3=A9e?= To: Richard Henderson Cc: qemu-devel@nongnu.org, alan.hayward@arm.com, luis.machado@linaro.org, damien.hedde@greensocs.com, Peter Maydell , "open list:ARM TCG CPUs" Subject: Re: [PATCH v2 11/14] target/arm: default SVE length to 64 bytes for linux-user In-reply-to: Date: Fri, 06 Dec 2019 14:52:42 +0000 Message-ID: <87fthx7bgl.fsf@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::342 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 06 Dec 2019 14:52:49 -0000 Richard Henderson writes: > On 12/5/19 9:31 AM, Alex Benn=C3=A9e wrote: >>=20 >> Richard Henderson writes: >>=20 >>> On 11/30/19 8:45 AM, Alex Benn=C3=A9e wrote: >>>> The Linux kernel chooses the default of 64 bytes for SVE registers on >>>> the basis that it is the largest size that won't grow the signal >>>> frame. When debugging larger sizes are also unwieldy in gdb as each >>>> zreg will take over a page of terminal to display. >>>> >>>> The user can of course always specify a larger size with the >>>> sve-max-vq property on the command line: >>>> >>>> -cpu max,sve-max-vq=3D16 >>>> >>>> This should not make any difference to SVE enabled software as the SVE >>>> is of course vector length agnostic. >>>> >>>> Signed-off-by: Alex Benn=C3=A9e >>>> --- >>>> target/arm/cpu64.c | 3 +++ >>>> 1 file changed, 3 insertions(+) >>> >>> 6 is the largest size that doesn't grow the signal frame. >>> I imagine 4 was chosen because that's the only real hw atm. >>> >>>> + /* Default sve-max-vq to a reasonable numer */ >>>> + cpu->sve_max_vq =3D 4; >>> >>> I also agree that we should match the kernel, but this is not the right= way. >>> Changing max vq is not the same as changing the default vq. >>> >>> You should change the value of env->vfp.zcr_el[1] in arm_cpu_reset(), a= nd the >>> user can increase the length with prctl(2) as they would be able to on = real >>> hardware that would have support for longer vector lengths. >>=20 >> No the intention is to default to a lower max VQ because... >>=20 >>> Also, I don't think you should mix this up with gdb stuff. >>=20 >> it is what we use for sizing the registers for the gdbstub. The other >> option would be to use the effective zcr_el1 value at the time of the >> gdbstub connecting but then things will go horribly wrong if the user >> execute a prctl and widens their size. > > Why would you care about the size of the registers as passed by default? = You > shouldn't need or want to change that default to make gdbstub work. > > The gdbstub should be passing along the vq value (via the "vg" pseudo-reg= ister, > iirc), and gdb should be working out what to display based on that. > > If that isn't happening, and you are only changing the default so that gdb > quits displaying massive registers when they aren't in use, then you're d= oing > something wrong with gdb and gdbstub. Currently the upstream gdbserver sends the XML based on the VL at start-up.= It doesn't handle changes in the vector size. --=20 Alex Benn=C3=A9e From MAILER-DAEMON Fri Dec 06 09:58:32 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1idF3w-00064x-I7 for mharc-qemu-arm@gnu.org; Fri, 06 Dec 2019 09:58:32 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:54238) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1idF3t-00060A-Jp for qemu-arm@nongnu.org; Fri, 06 Dec 2019 09:58:30 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1idF3r-0003WP-HF for qemu-arm@nongnu.org; Fri, 06 Dec 2019 09:58:29 -0500 Received: from mail-oi1-x241.google.com ([2607:f8b0:4864:20::241]:45187) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1idF3q-0003Ts-R3 for qemu-arm@nongnu.org; Fri, 06 Dec 2019 09:58:27 -0500 Received: by mail-oi1-x241.google.com with SMTP id v10so6348621oiv.12 for ; Fri, 06 Dec 2019 06:58:23 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=6SeJWuW7smgEfzxeMhKUR3tViJ1MMS3OliKE3zzGKtU=; b=s7UKlPpBZD1y3gEUPUtZSvKlf+9xf3fyBPXTbvolyaLSa3/gXKLvv18JDrNBynJ29X M9VnbeztwyV6mhNSQpvM/AWI35JqfDTE0H2q/kRP6xmZnO78giE7niRuGBrH0uIBoT56 yeYghhciwt9trXxFMxfhCO3dkzyZTqTbpoOXDcL3uak5Jwps5TzlgFiVEwLkxBH95Vh2 rKq/0soWsRqx3UIntqXNG88V+vHoxG1iYRcoQjh1hAN+To0TxOKTxdjfwtsim2WcMb+r 5i0+LS3K+ZQN2UaYLrAhTPNcuxBt6fpWsP2fmreNyqiWIbSmN6yM05wmF8RXtSLqFTrf 1Cvw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=6SeJWuW7smgEfzxeMhKUR3tViJ1MMS3OliKE3zzGKtU=; b=qcp41ZtEgQ7NYKNM5Wv85I6IaMjbisPYLdnxcwQAdeLfg2lprNOGNU3YvSo7VhpV3t jt2oyjUkOQeoWFAGXDBYW6ZXcnZGQ0A+5eRKaKYXR026rZgl6MSta9hSyXLM5mNWqbxT 8V5FYP0xKQjQ5lYsPHyoqPHqzscB0pnKoI8WfXh00mO+sAV1YrG/7JzDtA1chgX5n/oI n9Y+NeC3oGcbVQR65yAgQHPxUO0Z25xaSrIbdiZgq5T6utvkcKQGsIzoKcFoL75Rg760 V9dGe4i6V8fBYz5rfipn+fdZwdFVobAuBCNvU4tmfY+yaJ6XFd9+dNxEYKSFQyFS2fWW 1qsA== X-Gm-Message-State: APjAAAVi05U+cZPP5f7NGo88KsnIvLFVVtnQh9o2Ud3YVgRSV2gz8vrE sA2v+Jr2Krw3FDynl0J3RMxHpLDda87LDeVSx4JXQExW X-Google-Smtp-Source: APXvYqy1yYb6XgF1yeK+H7REH5tkoChDUJ1cNFgFWZI+AySwvrFoOEBeLnw54auwS7gj63wLVpOlCfYehquYJy4l0S0= X-Received: by 2002:aca:edd5:: with SMTP id l204mr12369452oih.98.1575637362903; Fri, 06 Dec 2019 05:02:42 -0800 (PST) MIME-Version: 1.0 References: <20191011134744.2477-1-richard.henderson@linaro.org> <20191011134744.2477-23-richard.henderson@linaro.org> In-Reply-To: <20191011134744.2477-23-richard.henderson@linaro.org> From: Peter Maydell Date: Fri, 6 Dec 2019 13:02:32 +0000 Message-ID: Subject: Re: [PATCH v5 22/22] target/arm: Add allocation tag storage for system mode To: Richard Henderson Cc: QEMU Developers , qemu-arm Content-Type: text/plain; charset="UTF-8" X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::241 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 06 Dec 2019 14:58:31 -0000 On Fri, 11 Oct 2019 at 14:50, Richard Henderson wrote: > > Signed-off-by: Richard Henderson > --- > target/arm/mte_helper.c | 61 +++++++++++++++++++++++++++++++++++++++++ > 1 file changed, 61 insertions(+) > > diff --git a/target/arm/mte_helper.c b/target/arm/mte_helper.c > index e8d8a6bedb..657383ba0e 100644 > --- a/target/arm/mte_helper.c > +++ b/target/arm/mte_helper.c > @@ -28,8 +28,69 @@ > static uint8_t *allocation_tag_mem(CPUARMState *env, uint64_t ptr, > bool write, uintptr_t ra) > { > +#ifdef CONFIG_USER_ONLY > /* Tag storage not implemented. */ > return NULL; > +#else > + CPUState *cs = env_cpu(env); > + uintptr_t index; > + int mmu_idx; > + CPUTLBEntry *entry; > + CPUIOTLBEntry *iotlbentry; > + MemoryRegionSection *section; > + hwaddr physaddr, tag_physaddr; > + > + /* > + * Find the TLB entry for this access. > + * As a side effect, this also raises an exception for invalid access. > + * > + * TODO: Perhaps there should be a cputlb helper that returns a > + * matching tlb entry + iotlb entry. That would also be able to > + * make use of the victim tlb cache, which is currently private. > + */ > + mmu_idx = cpu_mmu_index(env, false); > + index = tlb_index(env, mmu_idx, ptr); > + entry = tlb_entry(env, mmu_idx, ptr); > + if (!tlb_hit(write ? tlb_addr_write(entry) : entry->addr_read, ptr)) { > + bool ok = arm_cpu_tlb_fill(cs, ptr, 16, > + write ? MMU_DATA_STORE : MMU_DATA_LOAD, > + mmu_idx, false, ra); > + assert(ok); > + index = tlb_index(env, mmu_idx, ptr); > + entry = tlb_entry(env, mmu_idx, ptr); > + } > + > + /* If the virtual page MemAttr != Tagged, nothing to do. */ > + iotlbentry = &env_tlb(env)->d[mmu_idx].iotlb[index]; > + if (!iotlbentry->attrs.target_tlb_bit1) { > + return NULL; > + } > + > + /* > + * Find the physical address for the virtual access. > + * > + * TODO: It should be possible to have the tag mmu_idx map > + * from main memory ram_addr to tag memory host address. > + * that would allow this lookup step to be cached as well. > + */ > + section = iotlb_to_section(cs, iotlbentry->addr, iotlbentry->attrs); > + physaddr = ((iotlbentry->addr & TARGET_PAGE_MASK) + ptr > + + section->offset_within_address_space > + - section->offset_within_region); I'm surprised that going from vaddr to (physaddr, attrs) requires this much effort, it seems like the kind of thing we would already have a function to do. > + > + /* Convert to the physical address in tag space. */ > + tag_physaddr = physaddr >> (LOG2_TAG_GRANULE + 1); > + > + /* Choose the tlb index to use for the tag physical access. */ > + mmu_idx = iotlbentry->attrs.secure ? ARMMMUIdx_TagS : ARMMMUIdx_TagNS; > + mmu_idx = arm_to_core_mmu_idx(mmu_idx); > + > + /* > + * FIXME: Get access length and type so that we can use > + * probe_access, so that pages are marked dirty for migration. > + */ > + return tlb_vaddr_to_host(env, tag_physaddr, MMU_DATA_LOAD, mmu_idx); Hmm, does that mean that a setup with MemTag is not migratable? If so, we should at least install a migration-blocker for CPUs in that configuration. > +#endif > } > > static int get_allocation_tag(CPUARMState *env, uint64_t ptr, uintptr_t ra) > -- > 2.17.1 > thanks -- PMM From MAILER-DAEMON Fri Dec 06 10:00:09 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1idF5V-00080B-D2 for mharc-qemu-arm@gnu.org; Fri, 06 Dec 2019 10:00:09 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:35725) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1idF5R-0007sZ-1a for qemu-arm@nongnu.org; Fri, 06 Dec 2019 10:00:06 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1idF5P-0005nu-21 for qemu-arm@nongnu.org; Fri, 06 Dec 2019 10:00:04 -0500 Received: from mail-oi1-x241.google.com ([2607:f8b0:4864:20::241]:45207) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1idF5O-0005lQ-OO for qemu-arm@nongnu.org; Fri, 06 Dec 2019 10:00:02 -0500 Received: by mail-oi1-x241.google.com with SMTP id v10so6353540oiv.12 for ; Fri, 06 Dec 2019 07:00:02 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=eOLM4an9fc0aqxUJp71/rlPAB5BObyJXmI160pSiPVY=; b=zxIK7zx79X/dzDCJPrU8k6TPGxbecc6UbR4y6TTpTz3DjhmKeLDYXeZiP9fAVd2Y3A PYo0Uy4IG9YJNo2tXj11Dny0gOc0ZrxXCwTfYBOMy21rbjFknJNnJGpMeWALjYt/J9KF hABouP+p+xi7D9v3ne1hk9EGDRuAsTm6x8g0/n8r1g5lLAUCui4OV5IPqV2KvIdXbV/h fYmBN7Xnn85UyLkXcXx5ZTG0HP487OrdOz5b6lu8eZb2ZY0GweAvUgNnQhyCqrbDSKcg d81tT0aNtFZ61rzrLNaYqeZVPixYEMVZm425HU3H+Ka6EQIhQeuptbt9e06mpQdJnAzz xbOw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=eOLM4an9fc0aqxUJp71/rlPAB5BObyJXmI160pSiPVY=; b=AlUR6RnOkM/I2LJnnt7m58XKnEw6BVQjlfMnxeeqJ3SaRwFltHDJRfBIcCG+tp7JN5 MXx1+XciOo6+hHaiKDqdwuvANwJZBRvjXJiErWNd8FEfu45RPdBNacRZ7+MIPnpSiBp0 noezcs2TP0Pbh28pbzCsVHo53kVlhdAXPszsx1rImqvRskEqrFemsNBXv3qBihjXOZO5 3TnvBZKP1laBGG7evvrbE0tR6IwTs9vGFw6lBfdoedBQencKb7L8MXh7addmZWLET29G WzA0q906yxrwUteyfWN94jaZUpzH35lCaLFMGacC3DVptHb+1sRO38kxYBfZHmmYVVCS tUSQ== X-Gm-Message-State: APjAAAXcPkOjBeKqgm6mlrj/mhxBlZUk5HYfKObvQWR5wWmTZKSmE9vQ hSVWuYu8t5ic7QXtqHoq3Jeq/TYU4pI6fAZTY19kXg== X-Google-Smtp-Source: APXvYqyW8BtYV2mrUNt67h9M6TKKFEoFrbE5dXdkMxeaeMaRe8xgyZT0Xqc3AaoWPU0qkfYGiYMREuLsB5IboOOlODg= X-Received: by 2002:aca:edd5:: with SMTP id l204mr12877351oih.98.1575644402117; Fri, 06 Dec 2019 07:00:02 -0800 (PST) MIME-Version: 1.0 References: <20191121000843.24844-1-beata.michalska@linaro.org> In-Reply-To: <20191121000843.24844-1-beata.michalska@linaro.org> From: Peter Maydell Date: Fri, 6 Dec 2019 14:59:51 +0000 Message-ID: Subject: Re: [PATCH v3 0/4] target/arm: Support for Data Cache Clean up to PoP To: Beata Michalska Cc: QEMU Developers , qemu-arm , Richard Henderson , =?UTF-8?B?QWxleCBCZW5uw6ll?= , Paolo Bonzini , Juan Quintela , "Dr. David Alan Gilbert" , Eric Auger , Shameerali Kolothum Thodi Content-Type: text/plain; charset="UTF-8" X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::241 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 06 Dec 2019 15:00:08 -0000 On Thu, 21 Nov 2019 at 00:09, Beata Michalska wrote: > > ARMv8.2 introduced support for Data Cache Clean instructions to PoP > (point-of-persistence) and PoDP (point-of-deep-persistence): > ARMv8.2-DCCVAP & ARMv8.2-DCCVADP respectively. > This patch set adds support for emulating both, though there is no > distinction between the two points: the PoDP is assumed to represent > the same point of persistence as PoP. Case there is no such point specified > for the considered memory system both will fall back to the DV CVAC inst > (clean up to the point of coherency). > The changes introduced include adding probe_read for validating read memory > access to allow verification for mandatory read access for both cache > clean instructions, along with support for writeback for requested memory > regions through msync, if one is available, based otherwise on fsyncdata. Applied to target-arm.next for 5.0, thanks. -- PMM From MAILER-DAEMON Fri Dec 06 10:23:16 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1idFRr-0008KH-Tc for mharc-qemu-arm@gnu.org; Fri, 06 Dec 2019 10:23:15 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:60275) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1idFRo-0008DN-0Z for qemu-arm@nongnu.org; Fri, 06 Dec 2019 10:23:13 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1idFRm-00078D-JN for qemu-arm@nongnu.org; Fri, 06 Dec 2019 10:23:11 -0500 Received: from mail-ot1-x344.google.com ([2607:f8b0:4864:20::344]:35920) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1idFRm-00075U-8p for qemu-arm@nongnu.org; Fri, 06 Dec 2019 10:23:10 -0500 Received: by mail-ot1-x344.google.com with SMTP id i4so6115077otr.3 for ; Fri, 06 Dec 2019 07:23:10 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=lLL/PA8yye6H36YmDTDJ1uLtOzjPFZ9wMfmCB3T9Qaw=; b=fFIDUgKOI1eK6U6SOWpzPMY5IN6xLt9g7ESb8lserQJo4MEbirU+ui8SF1e4sw60+S E1Xf+J43b/F8q3V8NvBwVLwOIL+W1EsXSxY3Dc2H9NlwF6aeE470tJBYmDgrRTfeLvkF HFrAomGXZqDzHmZM+HrnhTUJ5UC5Z9v1YgiMUWq5mBdT9vUPGwE9emNaiP4EtNUwNi45 FwliZR36D0M1XhKbSPx3HbHNsiLnn40s84Yd8RL2ISNZhZW4RqPVCnakx+J9v3PeY33F mxlimG9lU9M5Jw4qT+gnRtXyt5g6zGUS2kYQaFu5E1f2aDM0Kv0AaSW8BLUBbh3XK6yb IpwQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=lLL/PA8yye6H36YmDTDJ1uLtOzjPFZ9wMfmCB3T9Qaw=; b=j5hlvkilotiYAHqQ5ylVigDbGrIaDudNeT9AIam9l+IKD9XhTbM1B0R1P+3W0kV38a 4MkCO+0pUFQC5XBRbYN4ROovVPYFO6amLqlNT7fGccP+/2nocC3oPyqh62z6eq6kGZBl mQdHCIIuWwUgEjHkCUBbUilM31TeSH4zAwJW1tMxfgJNnjjF5/qSZZKaxgGPcOQcKgBl HOxmeORPlj+V5hYe2VqtB4oWWhpzj3FboNe4XGcBNfsSHdy416K6eLlQ0h4r6XiykHk6 HpAXKulH7QcqDTZ4ZpC/ssthjhxtRVbY4t9La0xqWllt8z4iV6ckNL2meLEh1M00u7gC 3ZTQ== X-Gm-Message-State: APjAAAUtkOYFMHjZoYPQLVfgORZDX/24VZNdSUlLv5kMHwD49WBDeSAd h6yt9FsRzr9msfMvxlsnKPYaN0MlexL+ynvd1UQRjQ== X-Google-Smtp-Source: APXvYqw03zSH9ugAJHHK2drjDnpsWCs3dJY/2x/6anKkZgiejvRbtuCIpGjAyWmr6rs8oUwX7MlxyngqTAlyD4EoXlY= X-Received: by 2002:a9d:12d2:: with SMTP id g76mr11769992otg.232.1575645789270; Fri, 06 Dec 2019 07:23:09 -0800 (PST) MIME-Version: 1.0 References: <20191016143410.5023-1-drjones@redhat.com> In-Reply-To: <20191016143410.5023-1-drjones@redhat.com> From: Peter Maydell Date: Fri, 6 Dec 2019 15:22:58 +0000 Message-ID: Subject: Re: [PATCH v1 0/5] target/arm/kvm: Provide an option to adjust virtual time To: Andrew Jones Cc: QEMU Developers , qemu-arm , Richard Henderson , bijan.mottahedeh@oracle.com, Marc Zyngier Content-Type: text/plain; charset="UTF-8" X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::344 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 06 Dec 2019 15:23:14 -0000 On Wed, 16 Oct 2019 at 15:34, Andrew Jones wrote: > > v2: > - move from RFC status to v1 > - put kvm_arm_vm_state_change() in kvm.c to share among kvm32.c and kvm64.c > - add r-b's from Richard > > > This series is inspired by a series[1] posted by Bijan Mottahedeh about > a year ago. The problem described in the cover letter of [1] is easily > reproducible and some users would like to have the option to avoid it. > However the solution, which is to adjust the virtual counter offset each > time the VM transitions to the running state, introduces a different > problem, which is that the virtual and physical counters diverge. As > described in the cover letter of [1] this divergence is easily observed > when comparing the output of `date` and `hwclock` after suspending the > guest, waiting a while, and then resuming it. Because this different > problem may actually be worse for some users, unlike [1], the series > posted here makes the virtual counter offset adjustment optional and not > even enabled by default. Besides the adjustment being optional, this > series approaches the needed changes differently to apply them in more > appropriate locations. Finally, unlike [1], this series doesn't attempt > to measure "pause time" itself. Simply using QEMU_CLOCK_VIRTUAL, which > only ticks when the VM is not stopped, is sufficient. So I guess my overall question is "what is the x86 solution to this problem, and why is this all arm-specific?" It would also be helpful to know how it fits into all the other proposals regarding time in VMs. thanks -- PMM From MAILER-DAEMON Fri Dec 06 10:29:42 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1idFY4-000801-PV for mharc-qemu-arm@gnu.org; Fri, 06 Dec 2019 10:29:41 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:40796) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1idFXz-0007xR-O4 for qemu-arm@nongnu.org; Fri, 06 Dec 2019 10:29:37 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1idFXy-0008JI-NW for qemu-arm@nongnu.org; Fri, 06 Dec 2019 10:29:35 -0500 Received: from mail-ot1-x342.google.com ([2607:f8b0:4864:20::342]:33290) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1idFXx-0008Hu-Mj for qemu-arm@nongnu.org; Fri, 06 Dec 2019 10:29:33 -0500 Received: by mail-ot1-x342.google.com with SMTP id d17so6152164otc.0 for ; Fri, 06 Dec 2019 07:29:32 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc:content-transfer-encoding; bh=2Yzv5Xveobx+eBUxsnVw67hztizIW+3C2SXpKxGaDxU=; b=ozGlnR8bZqcf4D26sD/TAzQBXj2oK0ZCFIJGSuFogeAaLHPq8maW6DUvYPnjxfN4Rf EvMIWUO6sI6Tv4tDgjOFjfJP8T2FelTTep1/D3pdwHk57D7mRj5m8nLomvSyA+LOYVr6 JtcLBaxcW4U4OyyshjGFKMh5CCZhzqKPkgLsM4YsqNfp46e9KiNkYCuGS4OO1bp0F0ug +AU8Y212F9DmF8Us1AeC6l0L6LU6q9v9JLGImOJWCUx4X5ZTrDyyOssxS3nNE57MPC3+ xJcS4E3IG7ZOZ/yqTqElfuNgxw0UdELz8ZjKERi6+lhnClcdfhHfRrHoQ+E5ZLidBlDw IxOA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc:content-transfer-encoding; bh=2Yzv5Xveobx+eBUxsnVw67hztizIW+3C2SXpKxGaDxU=; b=DyCHHNE1JdpSUXqaltqkuVCXyqcOcjnSlqMKFCrTleGr7YVJ7PS7yeaeW8MOdUkks3 88CQS6U2QMEJZtnM6vhmeCgHfFtsxRp/Yq1ajuZAUQKgFo/lC2V9GG2RbVyvImiFvidM rOl9ZRRNKMVvyOqef0VtFc5Hd0aj8YBlHJMZJNF816lFgJAWCiu2hQp1V7CN90RIPeRi yf3gN7P6luBAmIC4mnizxi7MVzfRSEy8e37bifLFld2SDE6ovaaf3ClJRM9b3UCV85ta UdxA6kOLnIad/tY5ii3WZtSt5nahH5KlhJXGdsj9uLfMk/g+qirRi+qFwmY7oaW0NfK3 k8UQ== X-Gm-Message-State: APjAAAVsl+jXUzdtfQMbLra63QAm0iZVDD1MdnM+IzR5ZrtSPW4PHt97 umQ6CjX3b7eQR9u4m8E5P44kuKG2YhiER9T2+s88BA== X-Google-Smtp-Source: APXvYqx7ADnxQQd2CUTKfZRlgeADallzuH7gsnzL/2RWBJif6Y+L4dcK5VnOh/+pYwlvxXY7o9ruYzUI7U7UbPbY4jU= X-Received: by 2002:a9d:12d2:: with SMTP id g76mr11796431otg.232.1575646171756; Fri, 06 Dec 2019 07:29:31 -0800 (PST) MIME-Version: 1.0 References: <20191206122247.7507-1-alex.bennee@linaro.org> In-Reply-To: <20191206122247.7507-1-alex.bennee@linaro.org> From: Peter Maydell Date: Fri, 6 Dec 2019 15:29:21 +0000 Message-ID: Subject: Re: [PATCH] target/arm: don't bother with id_aa64pfr0_read for USER_ONLY To: =?UTF-8?B?QWxleCBCZW5uw6ll?= Cc: QEMU Developers , qemu-arm Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::342 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 06 Dec 2019 15:29:38 -0000 On Fri, 6 Dec 2019 at 12:22, Alex Benn=C3=A9e wrot= e: > > For system emulation we need to check the state of the GIC before we > report the value. However this isn't relevant to exporting of the > value to linux-user and indeed breaks the exported value as set by > modify_arm_cp_regs. > > [AJB: the other option would be just to set reset value anyway and not > ifdef out the readfn as the register will become const anyway] If you want it to be const it would be clearer to define it with ARM_CP_CONST... I'm not sure what an ARM_CP_NO_RAW without a readfn or a fieldoffset will do on reads. thanks -- PMM From MAILER-DAEMON Fri Dec 06 10:33:48 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1idFc4-000344-Nk for mharc-qemu-arm@gnu.org; Fri, 06 Dec 2019 10:33:48 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:54392) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1idFby-000312-MW for qemu-arm@nongnu.org; Fri, 06 Dec 2019 10:33:45 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1idFbx-0003Q7-5a for qemu-arm@nongnu.org; Fri, 06 Dec 2019 10:33:42 -0500 Received: from mail-ot1-x344.google.com ([2607:f8b0:4864:20::344]:41027) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1idFbu-0003O3-BJ for qemu-arm@nongnu.org; Fri, 06 Dec 2019 10:33:38 -0500 Received: by mail-ot1-x344.google.com with SMTP id r27so6099920otc.8 for ; Fri, 06 Dec 2019 07:33:27 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=O5nsFOtjimTarn9GS+btDv87kUC1vCLmzpNDta2HK4s=; b=L5jOzS155bNCJ4UXbeMy8WfpGFnhylLmy6JTayxrFtoocFrgo2Aw2oRJ0YZKjnn0VJ xeiluYE6eu0Mv5RqFmD/QLeJll5t92+PRB6GFtg3BkX5T8lEjjabwqm4c/ndwt/6kvdt ZmKCfFPgkxQga/F5ExQsqnaobyvDIOUsKBnLYyIHrw2nAfZsaIU0/mqQNaEtKJJ+SE/J pgDUhrpbYxMWfqMx4V4mVn/Su15wtVPPM6S47Gb7VBZJBU0TiCXT5RCB+57+jYoz/Ttp 7j9PmUFQrKXEa1ncKT59cbS5ETBu1HGkIjurDbwzdpb1BdKB9FzKBW00a1zzL7ur9gGE Vghg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=O5nsFOtjimTarn9GS+btDv87kUC1vCLmzpNDta2HK4s=; b=oTSh/jaoqsI1/NvyAZuel7nVLPYLNn3TYK+fYKnpsZ8a5NcD9wmf6tsnN5KrdMNJcI e1q1pt6IFIqlMPA+zLIoeabET480n3XCtxjBQQz72FsvYc2q6IW+TtYodziC3sV77vfi 1Noz/lp1aCY13eIusvQ8trSz8TUZlj5ammn5CucQFrwx7rB9cbrg5BvoTzDlPNw0PWKM RHtCfW9C9RcoGnki9GKnyclacBtHuXe2dXIKx1z7b38122Pl47sYOjMZweTflzWuxE7J ol+g5j6/UiEYFOHDHCuFRJpPlp8PG9EwY7OGE00dxkS9QFfVrCnzVL4/otOrgzswwlHE wMwg== X-Gm-Message-State: APjAAAXC9wVS+3riRjWJBNKPJZLgWuZwoXnjkvgegdh6xcP4pvCZNuoN gJ8aDIhkqiyvwNo0qAZy3qluiDB9uPT8gEiRMtkACmQR X-Google-Smtp-Source: APXvYqx0mgH1eZdXMJbTSz8/uk5lM8qaVRisD8J7Oy2Nvm8QuC/mlP7MyfC9Gfh/qiuuQgPFvQ56xF0sGkG+97F67Cs= X-Received: by 2002:a9d:12d2:: with SMTP id g76mr10680515otg.232.1575625923512; Fri, 06 Dec 2019 01:52:03 -0800 (PST) MIME-Version: 1.0 References: <20191011134744.2477-1-richard.henderson@linaro.org> <20191011134744.2477-21-richard.henderson@linaro.org> In-Reply-To: From: Peter Maydell Date: Fri, 6 Dec 2019 09:51:52 +0000 Message-ID: Subject: Re: [PATCH v5 20/22] target/arm: Create tagged ram when MTE is enabled To: Richard Henderson Cc: QEMU Developers , qemu-arm Content-Type: text/plain; charset="UTF-8" X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::344 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 06 Dec 2019 15:33:46 -0000 On Thu, 5 Dec 2019 at 19:24, Richard Henderson wrote: > > On 12/5/19 10:40 AM, Peter Maydell wrote: > > Are there really separate S and NS tag RAMs? > > Implementation defined, I believe. As with everything about tag storage, it > would seem. But since there are separate S and NS normal RAMS, I create > separate tag spaces to match. Yeah, it seems like the obvious design. I just couldn't find anything in the spec that said it was possible. I'm probably missing the relevant paragraph. -- PMM From MAILER-DAEMON Fri Dec 06 10:34:59 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1idFdD-0004XM-BO for mharc-qemu-arm@gnu.org; Fri, 06 Dec 2019 10:34:59 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:32878) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1idFd9-0004RW-Hi for qemu-arm@nongnu.org; Fri, 06 Dec 2019 10:34:56 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1idFd8-00053q-9P for qemu-arm@nongnu.org; Fri, 06 Dec 2019 10:34:55 -0500 Received: from mail-ot1-x344.google.com ([2607:f8b0:4864:20::344]:39206) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1idFd8-00052N-2d for qemu-arm@nongnu.org; Fri, 06 Dec 2019 10:34:54 -0500 Received: by mail-ot1-x344.google.com with SMTP id 77so6123875oty.6 for ; Fri, 06 Dec 2019 07:34:53 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc:content-transfer-encoding; bh=RPcSIYISFBGo154XUSTQYSxMjNsNm7pj3byN7uYuvPg=; b=eOKamfZlDixU8QGd/iqSOaHV9oe5RhQvoLa/8FzX30/1VJkuC4apnoGlH37gw+SGQF brGOKNS1YYtxM5vIx72h/OLYOQVHwYypPHyq5eLetOoA80+MGcevGo0qCh/RpHyUayfW Je3OgdtMjvrtsh7fxbl4MgQIgnHvAkP9Hu8G3xPp7A0Pm4Jrlw1r/Gya+tnCOtSxSnIp WmRRLvjCrtu8fvfYCrNuR59xORsKxHEtGYE7PxtUFcThIxodq+Q9shEcLGmOZTGQvAzx K733qXbsjSjX++qb5Qm4BdZCZBweDl8vtk7B8DUrXF5LhAwG7jDyVaSWirIpe/KRC/L3 WVpw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc:content-transfer-encoding; bh=RPcSIYISFBGo154XUSTQYSxMjNsNm7pj3byN7uYuvPg=; b=F2QzNLHuGTYSbggDVp9MtHw86eDYrCmgGuQssIgjPJuGfIjrzgSsFoLN999nQqsZBE 9ROEbGT/Z6X6NmTl+7th/otmfbG1uA5tkA17DVZ99reH3f/cy80hdlo1GUgigwTpnWhu DHGMbjm9dzvAFMDJtYitE1pwgpayrmEY9uPQ2dC6nJYPrC/PFcW4kd/hhxRyoH0/o33F oFlGTj3Ku7JekQgO/4UvPHfV+j1urPKsn4V3IOqtdcvPATQ4DqXYmnWAqHmBEr5agaO8 PR2B3T7ndMdrPRcvE8ite9nFCxyIxij/TbyCIMn6rRsi0b+NGooTaR053iislLC6Q53V V7kw== X-Gm-Message-State: APjAAAU6L02PnWoqnZUqWeeWWaMV1rpUJLpr9BB6L4xeU+rpA8P/pslf NUMDDgsszV4DvtevQqMbFqydNtF4eZmxugsOZpJ62w== X-Google-Smtp-Source: APXvYqyVrekgGkxjL1TN6VssP2gTgQswzzmUxmbtGP6t+Wr62x9E8SVQ1mvqOeAra1HWBumsmlrbCTD6yIzlsW/q/q0= X-Received: by 2002:a05:6830:4a4:: with SMTP id l4mr5490552otd.91.1575646493249; Fri, 06 Dec 2019 07:34:53 -0800 (PST) MIME-Version: 1.0 References: <20191206072257.7221-1-philmd@redhat.com> In-Reply-To: <20191206072257.7221-1-philmd@redhat.com> From: Peter Maydell Date: Fri, 6 Dec 2019 15:34:42 +0000 Message-ID: Subject: Re: [PATCH-for-5.0] hw/arm/sbsa-ref: Call qdev_get_gpio_in in place To: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= Cc: QEMU Developers , Leif Lindholm , Radoslaw Biernacki , qemu-arm Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::344 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 06 Dec 2019 15:34:57 -0000 On Fri, 6 Dec 2019 at 07:23, Philippe Mathieu-Daud=C3=A9 wrote: > > Instead of filling an array of qemu_irq and passing it around, > directly call qdev_get_gpio_in() on the GIC. > > Signed-off-by: Philippe Mathieu-Daud=C3=A9 > --- > I accept better patch subject suggestions :) > --- > hw/arm/sbsa-ref.c | 58 +++++++++++++++++++++++------------------------ > 1 file changed, 29 insertions(+), 29 deletions(-) > > diff --git a/hw/arm/sbsa-ref.c b/hw/arm/sbsa-ref.c > index 27046cc284..30cb647551 100644 > --- a/hw/arm/sbsa-ref.c > +++ b/hw/arm/sbsa-ref.c > @@ -328,7 +328,7 @@ static void create_secure_ram(SBSAMachineState *sms, > memory_region_add_subregion(secure_sysmem, base, secram); > } > > -static void create_gic(SBSAMachineState *sms, qemu_irq *pic) > +static DeviceState *create_gic(SBSAMachineState *sms) > { > unsigned int smp_cpus =3D MACHINE(sms)->smp.cpus; > DeviceState *gicdev; > @@ -403,12 +403,10 @@ static void create_gic(SBSAMachineState *sms, qemu_= irq *pic) > qdev_get_gpio_in(cpudev, ARM_CPU_VFIQ)); > } > > - for (i =3D 0; i < NUM_IRQS; i++) { > - pic[i] =3D qdev_get_gpio_in(gicdev, i); > - } > + return gicdev; If you make DeviceState *gic a field in SBSAMachineState then you don't need to pass it in as a parameter to all these functions. I think this code is mostly borrowed from the virt board, which is written the way it is because at the time we didn't have machine state structs which could own all the device structs etc for the devices on the board. thanks -- PMM From MAILER-DAEMON Fri Dec 06 10:40:23 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1idFiR-0002s6-7f for mharc-qemu-arm@gnu.org; Fri, 06 Dec 2019 10:40:23 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:34798) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1idFiM-0002kK-H5 for qemu-arm@nongnu.org; Fri, 06 Dec 2019 10:40:19 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1idFiK-0004LY-Gl for qemu-arm@nongnu.org; Fri, 06 Dec 2019 10:40:17 -0500 Received: from beetle.greensocs.com ([5.135.226.135]:42634) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1idFiJ-0004H1-W7; Fri, 06 Dec 2019 10:40:16 -0500 Received: from [172.16.11.102] (crumble.bar.greensocs.com [172.16.11.102]) by beetle.greensocs.com (Postfix) with ESMTPSA id 36ED296EF0; Fri, 6 Dec 2019 15:40:13 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=greensocs.com; s=mail; t=1575646813; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=LkE7SYCCqhtLN+sQUgbdWaSzdNEbRl8KD/D5Bb/y4UQ=; b=i9R7WRPkIyEU6u+LR6jGj5PMR/0Smq/CyvfXWd2gh0cKhGtb1Q2GV43MkwwWT5ikGGmH3I X9HzAqOVHSUJoHJzB+HhbKcrqONYqeTqgyToaPwse0OHADY/atH7a3TcEsR+qc742jPUSM CW6JeydkMowtoyAQ4aDd++UYM4FVQDE= Subject: Re: [PATCH v5 09/13] docs/devel/reset.txt: add doc about Resettable interface To: Peter Maydell Cc: QEMU Developers , Edgar Iglesias , Mark Burton , Paolo Bonzini , "Daniel P. Berrange" , Eduardo Habkost , David Gibson , Cornelia Huck , =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= , qemu-arm , qemu-s390x References: <20191018150630.31099-1-damien.hedde@greensocs.com> <20191018150630.31099-10-damien.hedde@greensocs.com> From: Damien Hedde Message-ID: <6e730df5-878e-369f-dd79-08dfb6e09082@greensocs.com> Date: Fri, 6 Dec 2019 16:40:12 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.2.0 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=utf-8 Content-Language: en-US-large Content-Transfer-Encoding: 7bit ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=greensocs.com; s=mail; t=1575646814; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=LkE7SYCCqhtLN+sQUgbdWaSzdNEbRl8KD/D5Bb/y4UQ=; b=VOH82BzNEyHsWBACjsBw+dpMN3NvW9nA7R5ucbUFKXUE1QES5J3T9yQSGa4aFGCy7L9hYF RIvF41tOocEJyddELByNhiyASgikgpbZOn1q9CP690QFbKM1iSgzKUi0VX55MDekzBjWCi LKgdSSc00pnEU1Y4qDiD1+5eT8mDxPc= ARC-Seal: i=1; s=mail; d=greensocs.com; t=1575646814; a=rsa-sha256; cv=none; b=oaG3ZgcD+ITNRtGCz+O9+FA6/pa581OSI35YXe5p1yu60HxT+jkzWWG0ZjsoG7XxqY7k9B hQjBO6J2YiCp4dHIPogwafP9OWLPuEZRC+XCWyp/Rs/R0MdcwMl2zgh/YkeQ7W/2mGxjPT ftV99nD4gwsiMPKf1lP+saI3aP8o2t8= ARC-Authentication-Results: i=1; ORIGINATING; auth=pass smtp.auth=damien smtp.mailfrom=damien.hedde@greensocs.com X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 5.135.226.135 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 06 Dec 2019 15:40:20 -0000 On 11/29/19 8:00 PM, Peter Maydell wrote: > On Fri, 18 Oct 2019 at 16:07, Damien Hedde wrote: >> >> Signed-off-by: Damien Hedde > > Subject line still says ".txt". > >> --- >> >> Should I add an entry into index.rst ? > > Yes, please. > > I have one substantive comment on this patch: in the > MyDev example of implementing reset, you make the enter/hold/exit > functions do the reset of the subclass and then call the > myclass->parent_phases method. This feels to me like it's the > wrong way round and the parent class should reset first. Does > it make any difference to do it this way round? > Not really, I'll update them to what you say. -- Damien From MAILER-DAEMON Fri Dec 06 10:53:40 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1idFvI-0001Th-KQ for mharc-qemu-arm@gnu.org; Fri, 06 Dec 2019 10:53:40 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:58873) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1idFvE-0001OW-Q9 for qemu-arm@nongnu.org; Fri, 06 Dec 2019 10:53:37 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1idFvD-0001T2-KU for qemu-arm@nongnu.org; Fri, 06 Dec 2019 10:53:36 -0500 Received: from us-smtp-delivery-1.mimecast.com ([207.211.31.120]:24282 helo=us-smtp-1.mimecast.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1idFvD-0001Rg-G2 for qemu-arm@nongnu.org; Fri, 06 Dec 2019 10:53:35 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1575647614; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=xx+gBQINEfsdCHgzHWk9u1vbTF0umg2qaZIaBUYeVFs=; b=I3fr0R0v4FYy9x4JfAx8fDj3syXyx9AVruAC8wMYYhG5svmRSuArVbHajeJ09WOrTslS9S Oc0s3uyVf2AIVlvd0IIl+OmekIxP3DQuC06tOwqaWIHt6w/sz9g7h/m0GNQoMyp5J8rK1K p+y2Wa+/tFIHHp4DrXhGATT6Edsop+U= Received: from mimecast-mx01.redhat.com (mimecast-mx01.redhat.com [209.132.183.4]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-219-ZKWUJp0YOXu4ZFKdzCgesQ-1; Fri, 06 Dec 2019 10:53:31 -0500 Received: from smtp.corp.redhat.com (int-mx04.intmail.prod.int.phx2.redhat.com [10.5.11.14]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx01.redhat.com (Postfix) with ESMTPS id 28DD0DB22; Fri, 6 Dec 2019 15:53:30 +0000 (UTC) Received: from kamzik.brq.redhat.com (unknown [10.43.2.160]) by smtp.corp.redhat.com (Postfix) with ESMTPS id CFB325D9E1; Fri, 6 Dec 2019 15:53:28 +0000 (UTC) Date: Fri, 6 Dec 2019 16:53:27 +0100 From: Andrew Jones To: Peter Maydell Cc: QEMU Developers , qemu-arm , Richard Henderson , bijan.mottahedeh@oracle.com, Marc Zyngier Subject: Re: [PATCH v1 0/5] target/arm/kvm: Provide an option to adjust virtual time Message-ID: <20191206155327.7adiyjjkjh56mg2t@kamzik.brq.redhat.com> References: <20191016143410.5023-1-drjones@redhat.com> MIME-Version: 1.0 In-Reply-To: X-Scanned-By: MIMEDefang 2.79 on 10.5.11.14 X-MC-Unique: ZKWUJp0YOXu4ZFKdzCgesQ-1 X-Mimecast-Spam-Score: 0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: quoted-printable Content-Disposition: inline X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 207.211.31.120 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 06 Dec 2019 15:53:38 -0000 On Fri, Dec 06, 2019 at 03:22:58PM +0000, Peter Maydell wrote: > On Wed, 16 Oct 2019 at 15:34, Andrew Jones wrote: > > > > v2: > > - move from RFC status to v1 > > - put kvm_arm_vm_state_change() in kvm.c to share among kvm32.c and kv= m64.c > > - add r-b's from Richard > > > > > > This series is inspired by a series[1] posted by Bijan Mottahedeh about > > a year ago. The problem described in the cover letter of [1] is easily > > reproducible and some users would like to have the option to avoid it. > > However the solution, which is to adjust the virtual counter offset eac= h > > time the VM transitions to the running state, introduces a different > > problem, which is that the virtual and physical counters diverge. As > > described in the cover letter of [1] this divergence is easily observed > > when comparing the output of `date` and `hwclock` after suspending the > > guest, waiting a while, and then resuming it. Because this different > > problem may actually be worse for some users, unlike [1], the series > > posted here makes the virtual counter offset adjustment optional and no= t > > even enabled by default. Besides the adjustment being optional, this > > series approaches the needed changes differently to apply them in more > > appropriate locations. Finally, unlike [1], this series doesn't attemp= t > > to measure "pause time" itself. Simply using QEMU_CLOCK_VIRTUAL, which > > only ticks when the VM is not stopped, is sufficient. >=20 > So I guess my overall question is "what is the x86 solution to > this problem, and why is this all arm-specific?" It would also x86 adjusts the counter offset by default, and I don't think there's any way to turn that behavior off. I think it's too late to follow that default for arm, but this series provides a way to opt into the same behavior. > be helpful to know how it fits into all the other proposals regarding > time in VMs. I've been lightly following the other stuff, but haven't yet seen any overlap. BTW, this series needs to be rebased and reposted. I've been waiting for 4.2 though. Thanks, drew From MAILER-DAEMON Fri Dec 06 11:19:38 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1idGKP-0006L9-0R for mharc-qemu-arm@gnu.org; Fri, 06 Dec 2019 11:19:37 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:51015) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1idGK1-0005rm-Vm for qemu-arm@nongnu.org; Fri, 06 Dec 2019 11:19:18 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1idGJw-00038F-Tt for qemu-arm@nongnu.org; Fri, 06 Dec 2019 11:19:10 -0500 Received: from us-smtp-delivery-1.mimecast.com ([207.211.31.120]:41367 helo=us-smtp-1.mimecast.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1idGJv-00032w-0w for qemu-arm@nongnu.org; Fri, 06 Dec 2019 11:19:08 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1575649137; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=/8FkBmT49LXKNBsclsnSXXFcBOEc1Utu4LKmwsbCXCs=; b=TdOSerH03XvlLMqP6eJBrM+z2qbWrz0fCLMJE/CfghgcNrT87BCAiBdZsPOPbetArT8hwT CsLUVY/Ns5WjZkI+Xo0/VQ8hU0PBX3p3zVP6fXX7QLgXAFHcdnEyYJS76jLcCW/zJHtVjT qBDzPKP/WLGzO+rxp655s8WDXZ8n42o= Received: from mail-wr1-f72.google.com (mail-wr1-f72.google.com [209.85.221.72]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-279-JuL1hZnvNcSaclH-aiqvWw-1; Fri, 06 Dec 2019 11:18:56 -0500 Received: by mail-wr1-f72.google.com with SMTP id d8so3336850wrq.12 for ; Fri, 06 Dec 2019 08:18:55 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:subject:to:cc:references:from:message-id:date :user-agent:mime-version:in-reply-to:content-language :content-transfer-encoding; bh=XDTWNNsDHsp0CCh47OiHb+CMYdzkyMNSlMUYmHnXQpw=; b=KE6qaEdBkJE2ASq4MsGhL+jdX+rKNI75aQudzdVs2OM9/nCrTByvWgxGk/nWVKcSgO KoRZIkC7Royago2MBEhEKXfYGVadfLk5N2UUHKHbA2UNQPz72TZsnFITgRcmErD1lv7K bgNs7VvzL/ShgaJ5MPVpc3FSSGOVzj69Iy1t1CuUStOrCh9e+YSPtpSMhlA3BJ1yxrtw L7l+if5F5opWes5uNOgeadGsIuHBKqXSPAqnQFzDh0HXdV4t0J+fZAcsjg0HiVHnt/Tm fI7nBY5kSL76MB3SUy9jiX3Rpd49K9XYUdKobbZTj5mSN64dsgcdXNwaacZByKgB/t7A XZjQ== X-Gm-Message-State: APjAAAXVBQNXO/fAuj4zH1GbIcwIofIsQZMJUwvt/an3YOJWuGu4K092 4JYI4O1WdMc3SXpx6iNg5VFXr/m4Sa3+nn+E/W0Cy0rPlE9H6qPlnu1aLxffJXoxHk46CKmtraD 0EfDEd+RzFbqb X-Received: by 2002:a1c:6485:: with SMTP id y127mr12068561wmb.19.1575649134620; Fri, 06 Dec 2019 08:18:54 -0800 (PST) X-Google-Smtp-Source: APXvYqzVNJDRwMuaZGnChuAMtK61dM/NLc1UylbLzzFao/vm+w8iiiFe/5tmqj0GwNA+fUIb1y7Hkg== X-Received: by 2002:a1c:6485:: with SMTP id y127mr12068550wmb.19.1575649134426; Fri, 06 Dec 2019 08:18:54 -0800 (PST) Received: from [192.168.1.35] (182.red-88-21-103.staticip.rima-tde.net. [88.21.103.182]) by smtp.gmail.com with ESMTPSA id m7sm11782414wrr.40.2019.12.06.08.18.53 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 06 Dec 2019 08:18:53 -0800 (PST) Subject: Re: [PATCH-for-5.0] hw/arm/sbsa-ref: Call qdev_get_gpio_in in place To: Peter Maydell Cc: QEMU Developers , Leif Lindholm , Radoslaw Biernacki , qemu-arm References: <20191206072257.7221-1-philmd@redhat.com> From: =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= Message-ID: <75d0cce3-de3e-08ac-0ecf-c97d93e30c8d@redhat.com> Date: Fri, 6 Dec 2019 17:18:52 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.2.2 MIME-Version: 1.0 In-Reply-To: Content-Language: en-US X-MC-Unique: JuL1hZnvNcSaclH-aiqvWw-1 X-Mimecast-Spam-Score: 0 Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 207.211.31.120 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 06 Dec 2019 16:19:18 -0000 On 12/6/19 4:34 PM, Peter Maydell wrote: > On Fri, 6 Dec 2019 at 07:23, Philippe Mathieu-Daud=C3=A9 wrote: >> >> Instead of filling an array of qemu_irq and passing it around, >> directly call qdev_get_gpio_in() on the GIC. >> >> Signed-off-by: Philippe Mathieu-Daud=C3=A9 >> --- >> I accept better patch subject suggestions :) >> --- >> hw/arm/sbsa-ref.c | 58 +++++++++++++++++++++++------------------------ >> 1 file changed, 29 insertions(+), 29 deletions(-) >> >> diff --git a/hw/arm/sbsa-ref.c b/hw/arm/sbsa-ref.c >> index 27046cc284..30cb647551 100644 >> --- a/hw/arm/sbsa-ref.c >> +++ b/hw/arm/sbsa-ref.c >> @@ -328,7 +328,7 @@ static void create_secure_ram(SBSAMachineState *sms, >> memory_region_add_subregion(secure_sysmem, base, secram); >> } >> >> -static void create_gic(SBSAMachineState *sms, qemu_irq *pic) >> +static DeviceState *create_gic(SBSAMachineState *sms) >> { >> unsigned int smp_cpus =3D MACHINE(sms)->smp.cpus; >> DeviceState *gicdev; >> @@ -403,12 +403,10 @@ static void create_gic(SBSAMachineState *sms, qemu= _irq *pic) >> qdev_get_gpio_in(cpudev, ARM_CPU_VFIQ)); >> } >> >> - for (i =3D 0; i < NUM_IRQS; i++) { >> - pic[i] =3D qdev_get_gpio_in(gicdev, i); >> - } >> + return gicdev; >=20 > If you make DeviceState *gic a field in SBSAMachineState then > you don't need to pass it in as a parameter to all these > functions. I think this code is mostly borrowed from the > virt board, which is written the way it is because at the > time we didn't have machine state structs which could > own all the device structs etc for the devices on the board. Great idea, thanks! From MAILER-DAEMON Fri Dec 06 11:21:18 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1idGM2-0007xB-2z for mharc-qemu-arm@gnu.org; Fri, 06 Dec 2019 11:21:18 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:32789) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1idGLx-0007pM-Ci for qemu-arm@nongnu.org; Fri, 06 Dec 2019 11:21:14 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1idGLw-0006Qn-1t for qemu-arm@nongnu.org; Fri, 06 Dec 2019 11:21:13 -0500 Received: from beetle.greensocs.com ([5.135.226.135]:44274) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1idGLv-0006LC-EQ; Fri, 06 Dec 2019 11:21:11 -0500 Received: from [172.16.11.102] (crumble.bar.greensocs.com [172.16.11.102]) by beetle.greensocs.com (Postfix) with ESMTPSA id B401C96EF0; Fri, 6 Dec 2019 16:21:08 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=greensocs.com; s=mail; t=1575649269; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=n8c+iJWFGPAiZo9jyfQbNY0kXYYSglGYK/9W4fXx3aw=; b=r/rjT14+vBaGM9Jyt10ruvVkwDTpFJZmmNZYEMVR79pBFBFipB47pHs9bIKJFUD6jy0/vP y89v4rJ0ghvzbUjOrf9L0/REKpfARpEYm5isva6Hethq8Dx1tnl2tcz3qsFl+/I9uSjGnN Srfk9Vaq4n5iWWlZqPOq/9hHnkRv8+k= Subject: Re: [PATCH v5 09/13] docs/devel/reset.txt: add doc about Resettable interface To: Peter Maydell Cc: QEMU Developers , Edgar Iglesias , Mark Burton , Paolo Bonzini , "Daniel P. Berrange" , Eduardo Habkost , David Gibson , Cornelia Huck , =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= , qemu-arm , qemu-s390x References: <20191018150630.31099-1-damien.hedde@greensocs.com> <20191018150630.31099-10-damien.hedde@greensocs.com> From: Damien Hedde Message-ID: <82ff568e-2828-f055-af3e-43e748127fd2@greensocs.com> Date: Fri, 6 Dec 2019 17:21:08 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.2.0 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=utf-8 Content-Language: en-US-large Content-Transfer-Encoding: 7bit ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=greensocs.com; s=mail; t=1575649269; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=n8c+iJWFGPAiZo9jyfQbNY0kXYYSglGYK/9W4fXx3aw=; b=DtV9BBUDi5HAWhHGhslm/XNInRy71liL5TTsKD9NRCmqb2CB0w3fd5GptvXqAywhJJjR2M Q/vgQyI4QxSYo0cgbvrD2RjE+U4EXZK2HgviS1NAiawUUCT9FmmOj0D5ENIC78b/+OcsA7 hE5BA0hpu3Sza77WxwCvoK8fCWK4oHY= ARC-Seal: i=1; s=mail; d=greensocs.com; t=1575649269; a=rsa-sha256; cv=none; b=ZDIdtvKGXiPY69R/9y4+7NXRhIzaRs0nQ698DAPBxrVWWasaav/o77lITX/YGJIMmz3zH0 VZ0ZyZosJYjU7wDNnFii1p6Bo5pg4o8eBRKrYPnxUh8N66Sc449vmL5H3J2uvBY7/OboGx WRvPb2cAwLbFUhvJ5PzMDW9p1LNLjKI= ARC-Authentication-Results: i=1; ORIGINATING; auth=pass smtp.auth=damien smtp.mailfrom=damien.hedde@greensocs.com X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 5.135.226.135 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 06 Dec 2019 16:21:15 -0000 On 11/29/19 8:00 PM, Peter Maydell wrote: > On Fri, 18 Oct 2019 at 16:07, Damien Hedde wrote: >> >> Signed-off-by: Damien Hedde > > Subject line still says ".txt". > >> --- >> >> +Polling the reset state >> +....................... >> + >> +Resettable interface provides the ``resettable_is_in_reset()`` function. >> +This function returns true if the object parameter is currently under reset. >> + >> +An object is under reset from the beginning of the *init* phase to the end of >> +the *exit* phase. During all three phases, the function will return that the >> +object is in reset. >> + >> +This function may be used if behavior has to be adapted when receiving external >> +interaction while in reset state. Note that until migration of the reset state >> +is supported, an object should not be left in reset. So apart from being >> +currently executing one of a reset phase, the only cases when this >> +function should return true is if an external interaction is made during *hold* >> +or *exit* phase of another object in the same reset group. > > This paragraph feels a bit unclear to me but I'm not sure how to improve it. > If I add an example like this is it better ? This function may be used if the object behavior has to be adapted while in reset state. For example if a device has an irq input, it will probably need to ignore it while in reset; then it can for example check the reset state at the beginning of the irq callback. Note that until migration of the reset state is supported, an object should not be left in reset. So apart from being currently executing one of the reset phases, the only cases when this function will return true is if an external interaction (like changing an io) is made during *hold* or *exit* phase of another object in the same reset group. -- Damien From MAILER-DAEMON Fri Dec 06 11:23:21 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1idGO1-0001uB-4R for mharc-qemu-arm@gnu.org; Fri, 06 Dec 2019 11:23:21 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:45940) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1idGNw-0001nW-V2 for qemu-arm@nongnu.org; Fri, 06 Dec 2019 11:23:18 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1idGNv-0001lV-3c for qemu-arm@nongnu.org; Fri, 06 Dec 2019 11:23:16 -0500 Received: from us-smtp-delivery-1.mimecast.com ([207.211.31.120]:28344 helo=us-smtp-1.mimecast.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1idGNu-0001kK-Rx for qemu-arm@nongnu.org; Fri, 06 Dec 2019 11:23:14 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1575649394; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding; bh=LOn4/rsQbtWBKdgDyXeGLcG/9R2mNlOXmomdSUKqcV0=; b=HmH5oSYuqssmhvT6m4wOzqeplpvzw8X3I7Ctdrbtem45b0iexQec+WzUpvbFoK3gfiqB8l WflbeEnlQnCrx9wdndgQ12GtsQCuqy2MoINlo1CWWVQDG3JQq13Oo2YRPBJVIc43uBnqij wcArj0pDKclXyJlr71qFUkW7O9et1n8= Received: from mimecast-mx01.redhat.com (mimecast-mx01.redhat.com [209.132.183.4]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-363-3_OFbeCnPamw2S0sF3uzJg-1; Fri, 06 Dec 2019 11:23:13 -0500 Received: from smtp.corp.redhat.com (int-mx02.intmail.prod.int.phx2.redhat.com [10.5.11.12]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx01.redhat.com (Postfix) with ESMTPS id 1C7761005512; Fri, 6 Dec 2019 16:23:12 +0000 (UTC) Received: from x1w.redhat.com (ovpn-204-212.brq.redhat.com [10.40.204.212]) by smtp.corp.redhat.com (Postfix) with ESMTPS id B8FFE6EE3B; Fri, 6 Dec 2019 16:23:06 +0000 (UTC) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Leif Lindholm , Radoslaw Biernacki , Peter Maydell , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH v2] hw/arm/sbsa-ref: Simplify by moving the gic in the machine state Date: Fri, 6 Dec 2019 17:23:03 +0100 Message-Id: <20191206162303.30338-1-philmd@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.79 on 10.5.11.12 X-MC-Unique: 3_OFbeCnPamw2S0sF3uzJg-1 X-Mimecast-Spam-Score: 0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 207.211.31.120 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 06 Dec 2019 16:23:20 -0000 Make the gic a field in the machine state, and instead of filling an array of qemu_irq and passing it around, directly call qdev_get_gpio_in() on the gic field. Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- v2: make DeviceState *gic a field in SBSAMachineState (Peter) --- hw/arm/sbsa-ref.c | 86 +++++++++++++++++++++++------------------------ 1 file changed, 42 insertions(+), 44 deletions(-) diff --git a/hw/arm/sbsa-ref.c b/hw/arm/sbsa-ref.c index 27046cc284..5853bdee5c 100644 --- a/hw/arm/sbsa-ref.c +++ b/hw/arm/sbsa-ref.c @@ -89,6 +89,7 @@ typedef struct { void *fdt; int fdt_size; int psci_conduit; + DeviceState *gic; PFlashCFI01 *flash[2]; } SBSAMachineState; =20 @@ -328,10 +329,9 @@ static void create_secure_ram(SBSAMachineState *sms, memory_region_add_subregion(secure_sysmem, base, secram); } =20 -static void create_gic(SBSAMachineState *sms, qemu_irq *pic) +static void create_gic(SBSAMachineState *sms) { unsigned int smp_cpus =3D MACHINE(sms)->smp.cpus; - DeviceState *gicdev; SysBusDevice *gicbusdev; const char *gictype; uint32_t redist0_capacity, redist0_count; @@ -339,25 +339,25 @@ static void create_gic(SBSAMachineState *sms, qemu_ir= q *pic) =20 gictype =3D gicv3_class_name(); =20 - gicdev =3D qdev_create(NULL, gictype); - qdev_prop_set_uint32(gicdev, "revision", 3); - qdev_prop_set_uint32(gicdev, "num-cpu", smp_cpus); + sms->gic =3D qdev_create(NULL, gictype); + qdev_prop_set_uint32(sms->gic, "revision", 3); + qdev_prop_set_uint32(sms->gic, "num-cpu", smp_cpus); /* * Note that the num-irq property counts both internal and external * interrupts; there are always 32 of the former (mandated by GIC spec= ). */ - qdev_prop_set_uint32(gicdev, "num-irq", NUM_IRQS + 32); - qdev_prop_set_bit(gicdev, "has-security-extensions", true); + qdev_prop_set_uint32(sms->gic, "num-irq", NUM_IRQS + 32); + qdev_prop_set_bit(sms->gic, "has-security-extensions", true); =20 redist0_capacity =3D sbsa_ref_memmap[SBSA_GIC_REDIST].size / GICV3_REDIST_SIZE; redist0_count =3D MIN(smp_cpus, redist0_capacity); =20 - qdev_prop_set_uint32(gicdev, "len-redist-region-count", 1); - qdev_prop_set_uint32(gicdev, "redist-region-count[0]", redist0_count); + qdev_prop_set_uint32(sms->gic, "len-redist-region-count", 1); + qdev_prop_set_uint32(sms->gic, "redist-region-count[0]", redist0_count= ); =20 - qdev_init_nofail(gicdev); - gicbusdev =3D SYS_BUS_DEVICE(gicdev); + qdev_init_nofail(sms->gic); + gicbusdev =3D SYS_BUS_DEVICE(sms->gic); sysbus_mmio_map(gicbusdev, 0, sbsa_ref_memmap[SBSA_GIC_DIST].base); sysbus_mmio_map(gicbusdev, 1, sbsa_ref_memmap[SBSA_GIC_REDIST].base); =20 @@ -383,15 +383,15 @@ static void create_gic(SBSAMachineState *sms, qemu_ir= q *pic) =20 for (irq =3D 0; irq < ARRAY_SIZE(timer_irq); irq++) { qdev_connect_gpio_out(cpudev, irq, - qdev_get_gpio_in(gicdev, + qdev_get_gpio_in(sms->gic, ppibase + timer_irq[irq= ])); } =20 qdev_connect_gpio_out_named(cpudev, "gicv3-maintenance-interrupt",= 0, - qdev_get_gpio_in(gicdev, ppibase + qdev_get_gpio_in(sms->gic, ppibase + ARCH_GIC_MAINT_IRQ)= ); qdev_connect_gpio_out_named(cpudev, "pmu-interrupt", 0, - qdev_get_gpio_in(gicdev, ppibase + qdev_get_gpio_in(sms->gic, ppibase + VIRTUAL_PMU_IRQ)); =20 sysbus_connect_irq(gicbusdev, i, qdev_get_gpio_in(cpudev, ARM_CPU_= IRQ)); @@ -402,13 +402,9 @@ static void create_gic(SBSAMachineState *sms, qemu_irq= *pic) sysbus_connect_irq(gicbusdev, i + 3 * smp_cpus, qdev_get_gpio_in(cpudev, ARM_CPU_VFIQ)); } - - for (i =3D 0; i < NUM_IRQS; i++) { - pic[i] =3D qdev_get_gpio_in(gicdev, i); - } } =20 -static void create_uart(const SBSAMachineState *sms, qemu_irq *pic, int ua= rt, +static void create_uart(const SBSAMachineState *sms, int uart, MemoryRegion *mem, Chardev *chr) { hwaddr base =3D sbsa_ref_memmap[uart].base; @@ -420,15 +416,15 @@ static void create_uart(const SBSAMachineState *sms, = qemu_irq *pic, int uart, qdev_init_nofail(dev); memory_region_add_subregion(mem, base, sysbus_mmio_get_region(s, 0)); - sysbus_connect_irq(s, 0, pic[irq]); + sysbus_connect_irq(s, 0, qdev_get_gpio_in(sms->gic, irq)); } =20 -static void create_rtc(const SBSAMachineState *sms, qemu_irq *pic) +static void create_rtc(const SBSAMachineState *sms) { hwaddr base =3D sbsa_ref_memmap[SBSA_RTC].base; int irq =3D sbsa_ref_irqmap[SBSA_RTC]; =20 - sysbus_create_simple("pl031", base, pic[irq]); + sysbus_create_simple("pl031", base, qdev_get_gpio_in(sms->gic, irq)); } =20 static DeviceState *gpio_key_dev; @@ -442,13 +438,14 @@ static Notifier sbsa_ref_powerdown_notifier =3D { .notify =3D sbsa_ref_powerdown_req }; =20 -static void create_gpio(const SBSAMachineState *sms, qemu_irq *pic) +static void create_gpio(const SBSAMachineState *sms) { DeviceState *pl061_dev; hwaddr base =3D sbsa_ref_memmap[SBSA_GPIO].base; int irq =3D sbsa_ref_irqmap[SBSA_GPIO]; =20 - pl061_dev =3D sysbus_create_simple("pl061", base, pic[irq]); + pl061_dev =3D sysbus_create_simple("pl061", base, + qdev_get_gpio_in(sms->gic, irq)); =20 gpio_key_dev =3D sysbus_create_simple("gpio-key", -1, qdev_get_gpio_in(pl061_dev, 3)); @@ -457,7 +454,7 @@ static void create_gpio(const SBSAMachineState *sms, qe= mu_irq *pic) qemu_register_powerdown_notifier(&sbsa_ref_powerdown_notifier); } =20 -static void create_ahci(const SBSAMachineState *sms, qemu_irq *pic) +static void create_ahci(const SBSAMachineState *sms) { hwaddr base =3D sbsa_ref_memmap[SBSA_AHCI].base; int irq =3D sbsa_ref_irqmap[SBSA_AHCI]; @@ -471,7 +468,7 @@ static void create_ahci(const SBSAMachineState *sms, qe= mu_irq *pic) qdev_prop_set_uint32(dev, "num-ports", NUM_SATA_PORTS); qdev_init_nofail(dev); sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base); - sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, pic[irq]); + sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, qdev_get_gpio_in(sms->gic, = irq)); =20 sysahci =3D SYSBUS_AHCI(dev); ahci =3D &sysahci->ahci; @@ -484,16 +481,16 @@ static void create_ahci(const SBSAMachineState *sms, = qemu_irq *pic) } } =20 -static void create_ehci(const SBSAMachineState *sms, qemu_irq *pic) +static void create_ehci(const SBSAMachineState *sms) { hwaddr base =3D sbsa_ref_memmap[SBSA_EHCI].base; int irq =3D sbsa_ref_irqmap[SBSA_EHCI]; =20 - sysbus_create_simple("platform-ehci-usb", base, pic[irq]); + sysbus_create_simple("platform-ehci-usb", base, + qdev_get_gpio_in(sms->gic, irq)); } =20 -static void create_smmu(const SBSAMachineState *sms, qemu_irq *pic, - PCIBus *bus) +static void create_smmu(const SBSAMachineState *sms, PCIBus *bus) { hwaddr base =3D sbsa_ref_memmap[SBSA_SMMU].base; int irq =3D sbsa_ref_irqmap[SBSA_SMMU]; @@ -507,11 +504,12 @@ static void create_smmu(const SBSAMachineState *sms, = qemu_irq *pic, qdev_init_nofail(dev); sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base); for (i =3D 0; i < NUM_SMMU_IRQS; i++) { - sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, pic[irq + i]); + sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, + qdev_get_gpio_in(sms->gic, irq + 1)); } } =20 -static void create_pcie(SBSAMachineState *sms, qemu_irq *pic) +static void create_pcie(SBSAMachineState *sms) { hwaddr base_ecam =3D sbsa_ref_memmap[SBSA_PCIE_ECAM].base; hwaddr size_ecam =3D sbsa_ref_memmap[SBSA_PCIE_ECAM].size; @@ -555,7 +553,8 @@ static void create_pcie(SBSAMachineState *sms, qemu_irq= *pic) sysbus_mmio_map(SYS_BUS_DEVICE(dev), 2, base_pio); =20 for (i =3D 0; i < GPEX_NUM_IRQS; i++) { - sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, pic[irq + i]); + sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, + qdev_get_gpio_in(sms->gic, irq + 1)); gpex_set_irq_num(GPEX_HOST(dev), i, irq + i); } =20 @@ -574,7 +573,7 @@ static void create_pcie(SBSAMachineState *sms, qemu_irq= *pic) =20 pci_create_simple(pci->bus, -1, "VGA"); =20 - create_smmu(sms, pic, pci->bus); + create_smmu(sms, pci->bus); } =20 static void *sbsa_ref_dtb(const struct arm_boot_info *binfo, int *fdt_size= ) @@ -598,7 +597,6 @@ static void sbsa_ref_init(MachineState *machine) bool firmware_loaded; const CPUArchIdList *possible_cpus; int n, sbsa_max_cpus; - qemu_irq pic[NUM_IRQS]; =20 if (strcmp(machine->cpu_type, ARM_CPU_TYPE_NAME("cortex-a57"))) { error_report("sbsa-ref: CPU type other than the built-in " @@ -695,22 +693,22 @@ static void sbsa_ref_init(MachineState *machine) =20 create_secure_ram(sms, secure_sysmem); =20 - create_gic(sms, pic); + create_gic(sms); =20 - create_uart(sms, pic, SBSA_UART, sysmem, serial_hd(0)); - create_uart(sms, pic, SBSA_SECURE_UART, secure_sysmem, serial_hd(1)); + create_uart(sms, SBSA_UART, sysmem, serial_hd(0)); + create_uart(sms, SBSA_SECURE_UART, secure_sysmem, serial_hd(1)); /* Second secure UART for RAS and MM from EL0 */ - create_uart(sms, pic, SBSA_SECURE_UART_MM, secure_sysmem, serial_hd(2)= ); + create_uart(sms, SBSA_SECURE_UART_MM, secure_sysmem, serial_hd(2)); =20 - create_rtc(sms, pic); + create_rtc(sms); =20 - create_gpio(sms, pic); + create_gpio(sms); =20 - create_ahci(sms, pic); + create_ahci(sms); =20 - create_ehci(sms, pic); + create_ehci(sms); =20 - create_pcie(sms, pic); + create_pcie(sms); =20 sms->bootinfo.ram_size =3D machine->ram_size; sms->bootinfo.nb_cpus =3D smp_cpus; --=20 2.21.0 From MAILER-DAEMON Fri Dec 06 11:36:00 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1idGaG-0006bP-Lb for mharc-qemu-arm@gnu.org; Fri, 06 Dec 2019 11:36:00 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:56421) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1idGaD-0006VN-0l for qemu-arm@nongnu.org; Fri, 06 Dec 2019 11:35:57 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1idGaB-0004sF-5H for qemu-arm@nongnu.org; Fri, 06 Dec 2019 11:35:56 -0500 Received: from us-smtp-delivery-1.mimecast.com ([205.139.110.120]:22907 helo=us-smtp-1.mimecast.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1idGa5-0004oy-Uj for qemu-arm@nongnu.org; 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[88.21.103.182]) by smtp.gmail.com with ESMTPSA id f1sm16986312wrp.93.2019.12.06.08.35.31 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 06 Dec 2019 08:35:31 -0800 (PST) Subject: Re: [PATCH 08/10] arm: allwinner-h3: add Security Identifier device To: Peter Maydell , Niek Linnenbank Cc: Beniamino Galvani , qemu-arm , QEMU Developers References: <20191202210947.3603-1-nieklinnenbank@gmail.com> <20191202210947.3603-9-nieklinnenbank@gmail.com> From: =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= Message-ID: <41ab9f5a-3318-b412-44e8-f8571a64da64@redhat.com> Date: Fri, 6 Dec 2019 17:35:30 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.2.2 MIME-Version: 1.0 In-Reply-To: Content-Language: en-US X-MC-Unique: pisVkofmNZOU_Q1Wh3SPsw-1 X-Mimecast-Spam-Score: 0 Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 7bit X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 205.139.110.120 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 06 Dec 2019 16:35:59 -0000 On 12/6/19 3:27 PM, Peter Maydell wrote: > On Mon, 2 Dec 2019 at 21:10, Niek Linnenbank wrote: >> >> The Security Identifier device in Allwinner H3 System on Chip >> gives applications a per-board unique identifier. This commit >> adds support for the Allwinner H3 Security Identifier using >> randomized data as input. > > If this is a fixed value in hardware, I'm not sure that > having the QEMU model pick a random value is the best > choice. If we just set it to a fixed value in QEMU, is > that going to cause problems? > > (Generally it's nice for QEMU to be deterministic, so it > behaves the same way every time you run it. Also if it's > always the same we don't need to bother migrating the > ID value.) Agreed. Since the identifier is 128-bit, I'd use DEFINE_PROP_UUID() or, to be even safer, DEFINE_PROP_UUID_NODEFAULT(). See how the ipmi-bmc-sim device checks its guid field and fails if unset. From MAILER-DAEMON Fri Dec 06 12:27:49 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1idHOO-0001c5-UA for mharc-qemu-arm@gnu.org; Fri, 06 Dec 2019 12:27:48 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:43593) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1idHOI-0001am-2G for qemu-arm@nongnu.org; Fri, 06 Dec 2019 12:27:44 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1idHOG-0002vx-9A for qemu-arm@nongnu.org; Fri, 06 Dec 2019 12:27:41 -0500 Received: from us-smtp-1.mimecast.com ([205.139.110.61]:26950 helo=us-smtp-delivery-1.mimecast.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1idHOF-0002to-PP for qemu-arm@nongnu.org; Fri, 06 Dec 2019 12:27:39 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1575653258; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding; bh=aakNe6ZpWKcgBnsHkUK2g0Vs/5LZCUeTONSVZshyz7w=; b=g/cX5IFRjINdqnxG1fMspMs+PpzWmjtELZ8nBFyg8kMZz/Sx+bvoPJIL7qMEXGtJrhgidB WKjACNnmknIXE3GAgSzNtTaRRGJOolLxvo91HSFowz6udq3s1af2r3ohGdoCtYsz+xz9ZV SRPQLMoEc9wPeoFRvYEvhG/riBV5XOg= Received: from mimecast-mx01.redhat.com (mimecast-mx01.redhat.com [209.132.183.4]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-268-mx1TiMz0PQSCxMj6L9ao7A-1; Fri, 06 Dec 2019 12:27:35 -0500 Received: from smtp.corp.redhat.com (int-mx02.intmail.prod.int.phx2.redhat.com [10.5.11.12]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx01.redhat.com (Postfix) with ESMTPS id DBC14800597; Fri, 6 Dec 2019 17:27:33 +0000 (UTC) Received: from laptop.redhat.com (ovpn-116-117.ams2.redhat.com [10.36.116.117]) by smtp.corp.redhat.com (Postfix) with ESMTP id 8C6426CE40; Fri, 6 Dec 2019 17:27:28 +0000 (UTC) From: Eric Auger To: eric.auger.pro@gmail.com, eric.auger@redhat.com, maz@kernel.org, kvmarm@lists.cs.columbia.edu, kvm@vger.kernel.org, qemu-devel@nongnu.org, qemu-arm@nongnu.org Cc: drjones@redhat.com, andrew.murray@arm.com, andre.przywara@arm.com, peter.maydell@linaro.org Subject: [kvm-unit-tests RFC 00/10] KVM: arm64: PMUv3 Event Counter Tests Date: Fri, 6 Dec 2019 18:27:14 +0100 Message-Id: <20191206172724.947-1-eric.auger@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.79 on 10.5.11.12 X-MC-Unique: mx1TiMz0PQSCxMj6L9ao7A-1 X-Mimecast-Spam-Score: 0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 205.139.110.61 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 06 Dec 2019 17:27:44 -0000 This series implements tests exercising the PMUv3 event counters. It tests both the 32-bit and 64-bit versions. Overflow interrupts also are checked. Those tests only are written for arm64. It allowed to reveal some issues related to SW_INCR implementation (esp. related to 64-bit implementation), some problems related to 32-bit <-> 64-bit transitions and consistency of enabled states of odd and event counters. Overflow interrupt testing relies of one patch from Andre ("arm: gic: Provide per-IRQ helper functions") to enable the PPI 23, coming from "arm: gic: Test SPIs and interrupt groups" (https://patchwork.kernel.org/cover/11234975/). Drew kindly provided "arm64: Provide read/write_sysreg_s". All PMU tests can be launched with: ./run_tests.sh -g pmu Tests also can be launched individually. For example: ./arm-run arm/pmu.flat -append 'chained-sw-incr' With KVM: - chain-promotion and chained-sw-incr are known to be failing. - Problems were reported upstream. With TCG: - pmu-event-introspection is failing due to missing required events (we may remove this from TCG actually) - chained-sw-incr also fails. I haven't investigated yet. Andre Przywara (1): arm: gic: Provide per-IRQ helper functions Andrew Jones (1): arm64: Provide read/write_sysreg_s Eric Auger (8): pmu: Let pmu tests take a sub-test parameter pmu: Add a pmu struct pmu: Check Required Event Support pmu: Basic event counter Tests pmu: Test chained counter arm: pmu: test 32-bit <-> 64-bit transitions arm/arm64: gic: Introduce setup_irq() helper pmu: Test overflow interrupts arm/gic.c | 24 +- arm/pmu.c | 754 ++++++++++++++++++++++++++++++++++++++++- arm/unittests.cfg | 55 ++- lib/arm/asm/gic-v3.h | 2 + lib/arm/asm/gic.h | 12 + lib/arm/gic.c | 101 ++++++ lib/arm64/asm/sysreg.h | 11 + 7 files changed, 922 insertions(+), 37 deletions(-) --=20 2.20.1 From MAILER-DAEMON Fri Dec 06 12:27:53 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1idHOR-0001fu-FD for mharc-qemu-arm@gnu.org; Fri, 06 Dec 2019 12:27:53 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:43801) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1idHOO-0001bz-Pd for qemu-arm@nongnu.org; Fri, 06 Dec 2019 12:27:50 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1idHOM-00034k-Md for qemu-arm@nongnu.org; Fri, 06 Dec 2019 12:27:48 -0500 Received: from us-smtp-1.mimecast.com ([207.211.31.81]:25449 helo=us-smtp-delivery-1.mimecast.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1idHOK-000302-Kt for qemu-arm@nongnu.org; Fri, 06 Dec 2019 12:27:46 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1575653262; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=82q1ODmkZ7c1oPzZoGIi16jb3fC0s7ZgyAm8HyUNG/k=; b=GqWKDFaN1Wm9fSEJbCykqP9EPZCrn/NTMaKlhErAReFctSzaePjnd1kyiNftswvAukaybB kX0s8W6I391/vTmlXTeMx6Bb06EyfGP5X7c5b6PMNru1hGfiEoXWwEVnk50+nC/SATJx82 iJLGUYnxO2W0RFEoaDbi2dQZdX92jGI= Received: from mimecast-mx01.redhat.com (mimecast-mx01.redhat.com [209.132.183.4]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-139-am3fbLFtNLK_jb0VJtV8MA-1; Fri, 06 Dec 2019 12:27:40 -0500 Received: from smtp.corp.redhat.com (int-mx02.intmail.prod.int.phx2.redhat.com [10.5.11.12]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx01.redhat.com (Postfix) with ESMTPS id 1CBB3800580; Fri, 6 Dec 2019 17:27:39 +0000 (UTC) Received: from laptop.redhat.com (ovpn-116-117.ams2.redhat.com [10.36.116.117]) by smtp.corp.redhat.com (Postfix) with ESMTP id 3E9436CE40; Fri, 6 Dec 2019 17:27:34 +0000 (UTC) From: Eric Auger To: eric.auger.pro@gmail.com, eric.auger@redhat.com, maz@kernel.org, kvmarm@lists.cs.columbia.edu, kvm@vger.kernel.org, qemu-devel@nongnu.org, qemu-arm@nongnu.org Cc: drjones@redhat.com, andrew.murray@arm.com, andre.przywara@arm.com, peter.maydell@linaro.org Subject: [kvm-unit-tests RFC 01/10] arm64: Provide read/write_sysreg_s Date: Fri, 6 Dec 2019 18:27:15 +0100 Message-Id: <20191206172724.947-2-eric.auger@redhat.com> In-Reply-To: <20191206172724.947-1-eric.auger@redhat.com> References: <20191206172724.947-1-eric.auger@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.79 on 10.5.11.12 X-MC-Unique: am3fbLFtNLK_jb0VJtV8MA-1 X-Mimecast-Spam-Score: 0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 207.211.31.81 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 06 Dec 2019 17:27:50 -0000 From: Andrew Jones Sometimes we need to test access to system registers which are missing assembler mnemonics. Signed-off-by: Andrew Jones --- lib/arm64/asm/sysreg.h | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/lib/arm64/asm/sysreg.h b/lib/arm64/asm/sysreg.h index a03830b..a45eebd 100644 --- a/lib/arm64/asm/sysreg.h +++ b/lib/arm64/asm/sysreg.h @@ -38,6 +38,17 @@ =09asm volatile("msr " xstr(r) ", %x0" : : "rZ" (__val));=09\ } while (0) =20 +#define read_sysreg_s(r) ({=09=09=09=09=09\ +=09u64 __val;=09=09=09=09=09=09\ +=09asm volatile("mrs_s %0, " xstr(r) : "=3Dr" (__val));=09\ +=09__val;=09=09=09=09=09=09=09\ +}) + +#define write_sysreg_s(v, r) do {=09=09=09=09\ +=09u64 __val =3D (u64)v;=09=09=09=09=09\ +=09asm volatile("msr_s " xstr(r) ", %x0" : : "rZ" (__val));\ +} while (0) + asm( "=09.irp=09num,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,= 23,24,25,26,27,28,29,30\n" "=09.equ=09.L__reg_num_x\\num, \\num\n" --=20 2.20.1 From MAILER-DAEMON Fri Dec 06 12:27:54 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1idHOU-0001iF-Dh for mharc-qemu-arm@gnu.org; Fri, 06 Dec 2019 12:27:54 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:43958) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1idHOP-0001dr-Th for qemu-arm@nongnu.org; Fri, 06 Dec 2019 12:27:51 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1idHOO-00036k-LF for qemu-arm@nongnu.org; Fri, 06 Dec 2019 12:27:49 -0500 Received: from us-smtp-1.mimecast.com ([207.211.31.81]:48277 helo=us-smtp-delivery-1.mimecast.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1idHOM-00033U-Kl for qemu-arm@nongnu.org; Fri, 06 Dec 2019 12:27:46 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1575653265; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=lZIWyVz0mXJm3WKdFFZ/MDv4wbAF4ZdIGNT+t+b1NIM=; b=gDxL6DE/1IjAi8VzFP4328+FXyLjs1PkxQMtPLyTulAm4D5a+n6lJMX0vtji190ALhfULQ oSZuMVyfE1Yf56EiNOvH4hG2m65WGl9LnY6qshrPDnErh+jr4VSkd1CEWjNBzfUyob0cTh FNxtOcIx8HD2ULoU7GSAyPDr7MJAa7c= Received: from mimecast-mx01.redhat.com (mimecast-mx01.redhat.com [209.132.183.4]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-393-D71sZqEuNFWfvlreylC4FA-1; Fri, 06 Dec 2019 12:27:43 -0500 Received: from smtp.corp.redhat.com (int-mx02.intmail.prod.int.phx2.redhat.com [10.5.11.12]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx01.redhat.com (Postfix) with ESMTPS id F0DC9107ACC9; Fri, 6 Dec 2019 17:27:41 +0000 (UTC) Received: from laptop.redhat.com (ovpn-116-117.ams2.redhat.com [10.36.116.117]) by smtp.corp.redhat.com (Postfix) with ESMTP id 73DC86CE40; Fri, 6 Dec 2019 17:27:39 +0000 (UTC) From: Eric Auger To: eric.auger.pro@gmail.com, eric.auger@redhat.com, maz@kernel.org, kvmarm@lists.cs.columbia.edu, kvm@vger.kernel.org, qemu-devel@nongnu.org, qemu-arm@nongnu.org Cc: drjones@redhat.com, andrew.murray@arm.com, andre.przywara@arm.com, peter.maydell@linaro.org Subject: [kvm-unit-tests RFC 02/10] pmu: Let pmu tests take a sub-test parameter Date: Fri, 6 Dec 2019 18:27:16 +0100 Message-Id: <20191206172724.947-3-eric.auger@redhat.com> In-Reply-To: <20191206172724.947-1-eric.auger@redhat.com> References: <20191206172724.947-1-eric.auger@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.79 on 10.5.11.12 X-MC-Unique: D71sZqEuNFWfvlreylC4FA-1 X-Mimecast-Spam-Score: 0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 207.211.31.81 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 06 Dec 2019 17:27:51 -0000 As we intend to introduce more PMU tests, let's add a sub-test parameter that will allow to categorize them. Existing tests are in the cycle-counter category. Signed-off-by: Eric Auger --- arm/pmu.c | 22 ++++++++++++++-------- arm/unittests.cfg | 7 ++++--- 2 files changed, 18 insertions(+), 11 deletions(-) diff --git a/arm/pmu.c b/arm/pmu.c index 1de7d77..2ad6469 100644 --- a/arm/pmu.c +++ b/arm/pmu.c @@ -287,21 +287,27 @@ int main(int argc, char *argv[]) { =09int cpi =3D 0; =20 -=09if (argc > 1) -=09=09cpi =3D atol(argv[1]); - =09if (!pmu_probe()) { =09=09printf("No PMU found, test skipped...\n"); =09=09return report_summary(); =09} =20 +=09if (argc < 2) +=09=09report_abort("no test specified"); + =09report_prefix_push("pmu"); =20 -=09report("Control register", check_pmcr()); -=09report("Monotonically increasing cycle count", check_cycles_increase())= ; -=09report("Cycle/instruction ratio", check_cpi(cpi)); - -=09pmccntr64_test(); +=09if (strcmp(argv[1], "cycle-counter") =3D=3D 0) { +=09=09report_prefix_push(argv[1]); +=09=09if (argc > 2) +=09=09=09cpi =3D atol(argv[2]); +=09=09report("Control register", check_pmcr()); +=09=09report("Monotonically increasing cycle count", check_cycles_increase= ()); +=09=09report("Cycle/instruction ratio", check_cpi(cpi)); +=09=09pmccntr64_test(); +=09} else { +=09=09report_abort("Unknown subtest '%s'", argv[1]); +=09} =20 =09return report_summary(); } diff --git a/arm/unittests.cfg b/arm/unittests.cfg index daeb5a0..79f0d7a 100644 --- a/arm/unittests.cfg +++ b/arm/unittests.cfg @@ -61,21 +61,22 @@ file =3D pci-test.flat groups =3D pci =20 # Test PMU support -[pmu] +[pmu-cycle-counter] file =3D pmu.flat groups =3D pmu +extra_params =3D -append 'cycle-counter 0' =20 # Test PMU support (TCG) with -icount IPC=3D1 #[pmu-tcg-icount-1] #file =3D pmu.flat -#extra_params =3D -icount 0 -append '1' +#extra_params =3D -icount 0 -append 'cycle-counter 1' #groups =3D pmu #accel =3D tcg =20 # Test PMU support (TCG) with -icount IPC=3D256 #[pmu-tcg-icount-256] #file =3D pmu.flat -#extra_params =3D -icount 8 -append '256' +#extra_params =3D -icount 8 -append 'cycle-counter 256' #groups =3D pmu #accel =3D tcg =20 --=20 2.20.1 From MAILER-DAEMON Fri Dec 06 12:27:58 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1idHOY-0001p3-DM for mharc-qemu-arm@gnu.org; Fri, 06 Dec 2019 12:27:58 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:44430) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1idHOU-0001io-N6 for qemu-arm@nongnu.org; Fri, 06 Dec 2019 12:27:55 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1idHOT-0003J6-Iw for qemu-arm@nongnu.org; Fri, 06 Dec 2019 12:27:54 -0500 Received: from us-smtp-delivery-1.mimecast.com ([205.139.110.120]:59886 helo=us-smtp-1.mimecast.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1idHOT-0003H2-Bz for qemu-arm@nongnu.org; Fri, 06 Dec 2019 12:27:53 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1575653272; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=yqTunPkxwrcyQFOxDUNzfOp1hv1TJYsH7F1IJZPhTJo=; b=GUPCMfIKF/NWK5pNJR+nw4t8tI35nE0kVEHbQBwq3GIctmI2xGM1ydTOAYXVFGOXu7Lkan 4F6NA3RqJTvSWP41bQqzaW5Jw2O2Ym/jyBsUmDCFPNaeJ4T4jiY9YQeFz5DzzjmgQLNsGY WHzQc/CIyfBYdiU/9dXuX33hG0tAtMw= Received: from mimecast-mx01.redhat.com (mimecast-mx01.redhat.com [209.132.183.4]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-64-RwGInhliOwmo9mMSBC3FqA-1; Fri, 06 Dec 2019 12:27:48 -0500 Received: from smtp.corp.redhat.com (int-mx02.intmail.prod.int.phx2.redhat.com [10.5.11.12]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx01.redhat.com (Postfix) with ESMTPS id 35E9A1005502; Fri, 6 Dec 2019 17:27:47 +0000 (UTC) Received: from laptop.redhat.com (ovpn-116-117.ams2.redhat.com [10.36.116.117]) by smtp.corp.redhat.com (Postfix) with ESMTP id 540D86CE40; Fri, 6 Dec 2019 17:27:42 +0000 (UTC) From: Eric Auger To: eric.auger.pro@gmail.com, eric.auger@redhat.com, maz@kernel.org, kvmarm@lists.cs.columbia.edu, kvm@vger.kernel.org, qemu-devel@nongnu.org, qemu-arm@nongnu.org Cc: drjones@redhat.com, andrew.murray@arm.com, andre.przywara@arm.com, peter.maydell@linaro.org Subject: [kvm-unit-tests RFC 03/10] pmu: Add a pmu struct Date: Fri, 6 Dec 2019 18:27:17 +0100 Message-Id: <20191206172724.947-4-eric.auger@redhat.com> In-Reply-To: <20191206172724.947-1-eric.auger@redhat.com> References: <20191206172724.947-1-eric.auger@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.79 on 10.5.11.12 X-MC-Unique: RwGInhliOwmo9mMSBC3FqA-1 X-Mimecast-Spam-Score: 0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 205.139.110.120 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 06 Dec 2019 17:27:56 -0000 This struct aims at storing information potentially used by all tests such as the pmu version, the read-only part of the PMCR, the number of implemented event counters, ... Signed-off-by: Eric Auger --- arm/pmu.c | 29 ++++++++++++++++++++++++----- 1 file changed, 24 insertions(+), 5 deletions(-) diff --git a/arm/pmu.c b/arm/pmu.c index 2ad6469..8e95251 100644 --- a/arm/pmu.c +++ b/arm/pmu.c @@ -33,7 +33,15 @@ =20 #define NR_SAMPLES 10 =20 -static unsigned int pmu_version; +struct pmu { +=09unsigned int version; +=09unsigned int nb_implemented_counters; +=09uint32_t pmcr_ro; +}; + +static struct pmu pmu; + + #if defined(__arm__) #define ID_DFR0_PERFMON_SHIFT 24 #define ID_DFR0_PERFMON_MASK 0xf @@ -265,7 +273,7 @@ static bool check_cpi(int cpi) static void pmccntr64_test(void) { #ifdef __arm__ -=09if (pmu_version =3D=3D 0x3) { +=09if (pmu.version =3D=3D 0x3) { =09=09if (ERRATA(9e3f7a296940)) { =09=09=09write_sysreg(0xdead, PMCCNTR64); =09=09=09report("pmccntr64", read_sysreg(PMCCNTR64) =3D=3D 0xdead); @@ -278,9 +286,20 @@ static void pmccntr64_test(void) /* Return FALSE if no PMU found, otherwise return TRUE */ static bool pmu_probe(void) { -=09pmu_version =3D get_pmu_version(); -=09report_info("PMU version: %d", pmu_version); -=09return pmu_version !=3D 0 && pmu_version !=3D 0xf; +=09uint32_t pmcr; + +=09pmu.version =3D get_pmu_version(); +=09report_info("PMU version: %d", pmu.version); + +=09if (pmu.version =3D=3D 0 || pmu.version =3D=3D 0xF) +=09=09return false; + +=09pmcr =3D get_pmcr(); +=09pmu.pmcr_ro =3D pmcr & 0xFFFFFF80; +=09pmu.nb_implemented_counters =3D (pmcr >> PMU_PMCR_N_SHIFT) & PMU_PMCR_N= _MASK; +=09report_info("Implements %d event counters", pmu.nb_implemented_counters= ); + +=09return true; } =20 int main(int argc, char *argv[]) --=20 2.20.1 From MAILER-DAEMON Fri Dec 06 12:28:04 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1idHOe-0001wu-3x for mharc-qemu-arm@gnu.org; Fri, 06 Dec 2019 12:28:04 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:45384) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1idHOa-0001rU-KR for qemu-arm@nongnu.org; Fri, 06 Dec 2019 12:28:01 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1idHOY-0003Yz-8E for qemu-arm@nongnu.org; Fri, 06 Dec 2019 12:28:00 -0500 Received: from us-smtp-1.mimecast.com ([205.139.110.61]:47003 helo=us-smtp-delivery-1.mimecast.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1idHOY-0003XZ-2p for qemu-arm@nongnu.org; Fri, 06 Dec 2019 12:27:58 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1575653277; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=WMQUa3khr5jsekFu/skIEP0pnlonAM+9sITcAnn0lGM=; b=hwmvMYDlKP+dCIybQFNTsOzW/N6tFV5lvnPlml7BU0mdo4Dy6N6sx8qpernl4xT0EF8mpv iGlpGBNNO/P3tRUsaQKW9/TH314jRwqZEsb6PwyowxMPITKBSdGWnBoS3KpOmU1Xl+hoOm H2o9EKDEorbwv+34UtSRgkoTcPY4uYY= Received: from mimecast-mx01.redhat.com (mimecast-mx01.redhat.com [209.132.183.4]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-188-bNevScXFNg-cmD5S24rlpg-1; Fri, 06 Dec 2019 12:27:56 -0500 Received: from smtp.corp.redhat.com (int-mx02.intmail.prod.int.phx2.redhat.com [10.5.11.12]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx01.redhat.com (Postfix) with ESMTPS id CE4C31005502; Fri, 6 Dec 2019 17:27:54 +0000 (UTC) Received: from laptop.redhat.com (ovpn-116-117.ams2.redhat.com [10.36.116.117]) by smtp.corp.redhat.com (Postfix) with ESMTP id 8CC286CE40; Fri, 6 Dec 2019 17:27:47 +0000 (UTC) From: Eric Auger To: eric.auger.pro@gmail.com, eric.auger@redhat.com, maz@kernel.org, kvmarm@lists.cs.columbia.edu, kvm@vger.kernel.org, qemu-devel@nongnu.org, qemu-arm@nongnu.org Cc: drjones@redhat.com, andrew.murray@arm.com, andre.przywara@arm.com, peter.maydell@linaro.org Subject: [kvm-unit-tests RFC 04/10] pmu: Check Required Event Support Date: Fri, 6 Dec 2019 18:27:18 +0100 Message-Id: <20191206172724.947-5-eric.auger@redhat.com> In-Reply-To: <20191206172724.947-1-eric.auger@redhat.com> References: <20191206172724.947-1-eric.auger@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.79 on 10.5.11.12 X-MC-Unique: bNevScXFNg-cmD5S24rlpg-1 X-Mimecast-Spam-Score: 0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 205.139.110.61 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 06 Dec 2019 17:28:02 -0000 If event counters are implemented check the common events required by the PMUv3 are implemented. Some are unconditionally required (SW_INCR, CPU_CYCLES, either INST_RETIRED or INST_SPEC). Some others only are required if the implementation implements some other features. Check those wich are unconditionally required. This test currently fails on TCG as neither INST_RETIRED or INST_SPEC are supported. Signed-off-by: Eric Auger --- arm/pmu.c | 70 +++++++++++++++++++++++++++++++++++++++++++++++ arm/unittests.cfg | 6 ++++ 2 files changed, 76 insertions(+) diff --git a/arm/pmu.c b/arm/pmu.c index 8e95251..f78c43f 100644 --- a/arm/pmu.c +++ b/arm/pmu.c @@ -102,6 +102,10 @@ static inline void precise_instrs_loop(int loop, uint3= 2_t pmcr) =09: [pmcr] "r" (pmcr), [z] "r" (0) =09: "cc"); } + +/* event counter tests only implemented for aarch64 */ +static void test_event_introspection(void) {} + #elif defined(__aarch64__) #define ID_AA64DFR0_PERFMON_SHIFT 8 #define ID_AA64DFR0_PERFMON_MASK 0xf @@ -140,6 +144,69 @@ static inline void precise_instrs_loop(int loop, uint3= 2_t pmcr) =09: [pmcr] "r" (pmcr) =09: "cc"); } + +#define PMCEID1_EL0 sys_reg(11, 3, 9, 12, 7) + +static bool is_event_supported(uint32_t n, bool warn) +{ +=09uint64_t pmceid0 =3D read_sysreg(pmceid0_el0); +=09uint64_t pmceid1 =3D read_sysreg_s(PMCEID1_EL0); +=09bool supported; +=09uint32_t reg; + +=09if (n >=3D 0x0 && n <=3D 0x1F) { +=09=09reg =3D pmceid0 & 0xFFFFFFFF; +=09} else if (n >=3D 0x4000 && n <=3D 0x401F) { +=09=09reg =3D pmceid0 >> 32; +=09} else if (n >=3D 0x20 && n <=3D 0x3F) { +=09=09reg =3D pmceid1 & 0xFFFFFFFF; +=09} else if (n >=3D 0x4020 && n <=3D 0x403F) { +=09=09reg =3D pmceid1 >> 32; +=09} else { +=09=09abort(); +=09} +=09supported =3D reg & (1 << n); +=09if (!supported && warn) +=09=09report_info("event %d is not supported", n); +=09return supported; +} + +static void test_event_introspection(void) +{ +=09bool required_events; + +=09if (!pmu.nb_implemented_counters) { +=09=09report_skip("No event counter, skip ..."); +=09=09return; +=09} +=09if (pmu.nb_implemented_counters < 2) +=09=09report_info("%d event counters are implemented. " + "ARM recommends to implement at least 2", + pmu.nb_implemented_counters); + +=09/* PMUv3 requires an implementation includes some common events */ +=09required_events =3D is_event_supported(0x0, true) /* SW_INCR */ && +=09=09=09 is_event_supported(0x11, true) /* CPU_CYCLES */ && +=09=09=09 (is_event_supported(0x8, true) /* INST_RETIRED */ || +=09=09=09 is_event_supported(0x1B, true) /* INST_PREC */); +=09if (!is_event_supported(0x8, false)) +=09=09report_info("ARM strongly recomments INST_RETIRED (0x8) event " +=09=09=09 "to be implemented"); + +=09if (pmu.version =3D=3D 0x4) { +=09=09/* ARMv8.1 PMU: STALL_FRONTEND and STALL_BACKEND are required */ +=09=09required_events =3D required_events || +=09=09=09=09 is_event_supported(0x23, true) || +=09=09=09=09 is_event_supported(0x24, true); +=09} + +=09/* L1D_CACHE_REFILL(0x3) and L1D_CACHE(0x4) are only required if +=09 L1 data / unified cache. BR_MIS_PRED(0x10), BR_PRED(0x12) are only +=09 required if program-flow prediction is implemented. */ + +=09report("Check required events are implemented", required_events); +} + #endif =20 /* @@ -324,6 +391,9 @@ int main(int argc, char *argv[]) =09=09report("Monotonically increasing cycle count", check_cycles_increase= ()); =09=09report("Cycle/instruction ratio", check_cpi(cpi)); =09=09pmccntr64_test(); +=09} else if (strcmp(argv[1], "event-introspection") =3D=3D 0) { +=09=09report_prefix_push(argv[1]); +=09=09test_event_introspection(); =09} else { =09=09report_abort("Unknown subtest '%s'", argv[1]); =09} diff --git a/arm/unittests.cfg b/arm/unittests.cfg index 79f0d7a..4433ef3 100644 --- a/arm/unittests.cfg +++ b/arm/unittests.cfg @@ -66,6 +66,12 @@ file =3D pmu.flat groups =3D pmu extra_params =3D -append 'cycle-counter 0' =20 +[pmu-event-introspection] +file =3D pmu.flat +groups =3D pmu +arch =3D arm64 +extra_params =3D -append 'event-introspection' + # Test PMU support (TCG) with -icount IPC=3D1 #[pmu-tcg-icount-1] #file =3D pmu.flat --=20 2.20.1 From MAILER-DAEMON Fri Dec 06 12:28:07 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1idHOh-00023j-Q8 for mharc-qemu-arm@gnu.org; Fri, 06 Dec 2019 12:28:07 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:45950) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1idHOd-0001wY-R1 for qemu-arm@nongnu.org; Fri, 06 Dec 2019 12:28:05 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1idHOb-0003jY-G3 for qemu-arm@nongnu.org; Fri, 06 Dec 2019 12:28:03 -0500 Received: from us-smtp-1.mimecast.com ([207.211.31.81]:22444 helo=us-smtp-delivery-1.mimecast.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1idHOb-0003hK-9k for qemu-arm@nongnu.org; Fri, 06 Dec 2019 12:28:01 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1575653280; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=05gJo/iDZRpCh33ff7JxVNxihlf01laZ3I+XStrtiS8=; b=AGFs9sLEQ6dh04N8M8SW1i7C/5Q7rFwChxycMqc+QRKS126HPEDnOt8d3UTZL1nB0Eo9Ds ThjD/VlU8fU4w7C/A1hiIS/U9t45CRiU0E1RQtlwhyyN7WQV568kEltyLxtVrivCkCbg+l ZTjt2G+WlWE2t8AUgTQLX+8KVixRlrM= Received: from mimecast-mx01.redhat.com (mimecast-mx01.redhat.com [209.132.183.4]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-431-cZUedAMGMjSY8CBp_wrjmw-1; Fri, 06 Dec 2019 12:27:59 -0500 Received: from smtp.corp.redhat.com (int-mx02.intmail.prod.int.phx2.redhat.com [10.5.11.12]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx01.redhat.com (Postfix) with ESMTPS id B0943800C7B; Fri, 6 Dec 2019 17:27:57 +0000 (UTC) Received: from laptop.redhat.com (ovpn-116-117.ams2.redhat.com [10.36.116.117]) by smtp.corp.redhat.com (Postfix) with ESMTP id 31D1060BF4; Fri, 6 Dec 2019 17:27:55 +0000 (UTC) From: Eric Auger To: eric.auger.pro@gmail.com, eric.auger@redhat.com, maz@kernel.org, kvmarm@lists.cs.columbia.edu, kvm@vger.kernel.org, qemu-devel@nongnu.org, qemu-arm@nongnu.org Cc: drjones@redhat.com, andrew.murray@arm.com, andre.przywara@arm.com, peter.maydell@linaro.org Subject: [kvm-unit-tests RFC 05/10] pmu: Basic event counter Tests Date: Fri, 6 Dec 2019 18:27:19 +0100 Message-Id: <20191206172724.947-6-eric.auger@redhat.com> In-Reply-To: <20191206172724.947-1-eric.auger@redhat.com> References: <20191206172724.947-1-eric.auger@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.79 on 10.5.11.12 X-MC-Unique: cZUedAMGMjSY8CBp_wrjmw-1 X-Mimecast-Spam-Score: 0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 207.211.31.81 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 06 Dec 2019 17:28:06 -0000 Adds the following tests: - event-counter-config: test event counter configuration - basic-event-count: - programs counters #0 and #1 to count 2 required events (resp. CPU_CYCLES and INST_RETIRED). Counter #0 is preset to a value close enough to the 32b overflow limit so that we check the overflow bit is set after the execution of the asm loop. - mem-access: counts MEM_ACCESS event on counters #0 and #1 with and without 32-bit overflow. Signed-off-by: Eric Auger --- arm/pmu.c | 254 ++++++++++++++++++++++++++++++++++++++++++++++ arm/unittests.cfg | 18 ++++ 2 files changed, 272 insertions(+) diff --git a/arm/pmu.c b/arm/pmu.c index f78c43f..8ffeb93 100644 --- a/arm/pmu.c +++ b/arm/pmu.c @@ -18,9 +18,15 @@ #include "asm/barrier.h" #include "asm/sysreg.h" #include "asm/processor.h" +#include +#include =20 #define PMU_PMCR_E (1 << 0) +#define PMU_PMCR_P (1 << 1) #define PMU_PMCR_C (1 << 2) +#define PMU_PMCR_D (1 << 3) +#define PMU_PMCR_X (1 << 4) +#define PMU_PMCR_DP (1 << 5) #define PMU_PMCR_LC (1 << 6) #define PMU_PMCR_N_SHIFT 11 #define PMU_PMCR_N_MASK 0x1f @@ -105,6 +111,9 @@ static inline void precise_instrs_loop(int loop, uint32= _t pmcr) =20 /* event counter tests only implemented for aarch64 */ static void test_event_introspection(void) {} +static void test_event_counter_config(void) {} +static void test_basic_event_count(void) {} +static void test_mem_access(void) {} =20 #elif defined(__aarch64__) #define ID_AA64DFR0_PERFMON_SHIFT 8 @@ -146,6 +155,32 @@ static inline void precise_instrs_loop(int loop, uint3= 2_t pmcr) } =20 #define PMCEID1_EL0 sys_reg(11, 3, 9, 12, 7) +#define PMCNTENSET_EL0 sys_reg(11, 3, 9, 12, 1) +#define PMCNTENCLR_EL0 sys_reg(11, 3, 9, 12, 2) + +#define PMEVTYPER_EXCLUDE_EL1 (1 << 31) +#define PMEVTYPER_EXCLUDE_EL0 (1 << 30) + +#define regn_el0(__reg, __n) __reg ## __n ## _el0 +#define write_regn(__reg, __n, __val) \ +=09write_sysreg((__val), __reg ## __n ## _el0) + +#define read_regn(__reg, __n) \ +=09read_sysreg(__reg ## __n ## _el0) + +#define print_pmevtyper(__s , __n) do { \ +=09uint32_t val; \ +=09val =3D read_regn(pmevtyper, __n);\ +=09report_info("%s pmevtyper%d=3D0x%x, eventcount=3D0x%x (p=3D%ld, u=3D%ld= nsk=3D%ld, nsu=3D%ld, nsh=3D%ld m=3D%ld, mt=3D%ld)", \ +=09=09=09(__s), (__n), val, val & 0xFFFF, \ +=09=09=09(BIT_MASK(31) & val) >> 31, \ +=09=09=09(BIT_MASK(30) & val) >> 30, \ +=09=09=09(BIT_MASK(29) & val) >> 29, \ +=09=09=09(BIT_MASK(28) & val) >> 28, \ +=09=09=09(BIT_MASK(27) & val) >> 27, \ +=09=09=09(BIT_MASK(26) & val) >> 26, \ +=09=09=09(BIT_MASK(25) & val) >> 25); \ +=09} while (0) =20 static bool is_event_supported(uint32_t n, bool warn) { @@ -207,6 +242,216 @@ static void test_event_introspection(void) =09report("Check required events are implemented", required_events); } =20 +static inline void mem_access_loop(void *addr, int loop, uint32_t pmcr) +{ +asm volatile( +=09" msr pmcr_el0, %[pmcr]\n" +=09" isb\n" +=09" mov x10, %[loop]\n" +=09"1: sub x10, x10, #1\n" +=09" mov x8, %[addr]\n" +=09" ldr x9, [x8]\n" +=09" cmp x10, #0x0\n" +=09" b.gt 1b\n" +=09" msr pmcr_el0, xzr\n" +=09" isb\n" +=09: +=09: [addr] "r" (addr), [pmcr] "r" (pmcr), [loop] "r" (loop) +=09: ); +} + + +static void pmu_reset(void) +{ +=09/* reset all counters, counting disabled at PMCR level*/ +=09set_pmcr(pmu.pmcr_ro | PMU_PMCR_LC | PMU_PMCR_C | PMU_PMCR_P); +=09/* Disable all counters */ +=09write_sysreg_s(0xFFFFFFFF, PMCNTENCLR_EL0); +=09/* clear overflow reg */ +=09write_sysreg(0xFFFFFFFF, pmovsclr_el0); +=09/* disable overflow interrupts on all counters */ +=09write_sysreg(0xFFFFFFFF, pmintenclr_el1); +=09isb(); +} + +static void test_event_counter_config(void) { +=09int i; + +=09if (!pmu.nb_implemented_counters) { +=09=09report_skip("No event counter, skip ..."); +=09=09return; +=09} + +=09pmu_reset(); + +=09/* Test setting through PMESELR/PMXEVTYPER and PMEVTYPERn read */ + /* select counter 0 */ + write_sysreg(1, PMSELR_EL0); + /* program this counter to count unsupported event */ + write_sysreg(0xEA, PMXEVTYPER_EL0); + write_sysreg(0xdeadbeef, PMXEVCNTR_EL0); +=09report("PMESELR/PMXEVTYPER/PMEVTYPERn", +=09=09(read_regn(pmevtyper, 1) & 0xFFF) =3D=3D 0xEA); +=09report("PMESELR/PMXEVCNTR/PMEVCNTRn", +=09=09(read_regn(pmevcntr, 1) =3D=3D 0xdeadbeef)); + +=09/* try configure an unsupported event within the range [0x0, 0x3F] */ +=09for (i =3D 0; i <=3D 0x3F; i++) { +=09=09if (!is_event_supported(i, false)) +=09=09=09goto test_unsupported; +=09} +=09report_skip("pmevtyper: all events within [0x0, 0x3F] are supported"); + +test_unsupported: +=09/* select counter 0 */ +=09write_sysreg(0, PMSELR_EL0); +=09/* program this counter to count unsupported event */ +=09write_sysreg(i, PMXEVCNTR_EL0); +=09/* read the counter value */ +=09read_sysreg(PMXEVCNTR_EL0); +=09report("read of a counter programmed with unsupported event", read_sysr= eg(PMXEVCNTR_EL0) =3D=3D i); + +} + +static bool satisfy_prerequisites(uint32_t *events, unsigned int nb_events= ) +{ +=09int i; + +=09if (pmu.nb_implemented_counters < nb_events) { +=09=09report_skip("Skip test as number of counters is too small (%d)", +=09=09=09 pmu.nb_implemented_counters); +=09=09return false; +=09} + +=09for (i =3D 0; i < nb_events; i++) { +=09=09if (!is_event_supported(events[i], false)) { +=09=09=09report_skip("Skip test as event %d is not supported", +=09=09=09=09 events[i]); +=09=09=09return false; +=09=09} +=09}=09=09 +=09return true; +} + +static void test_basic_event_count(void) +{ +=09uint32_t implemented_counter_mask, non_implemented_counter_mask; +=09uint32_t counter_mask; +=09uint32_t events[] =3D { +=09=090x11,=09/* CPU_CYCLES */ +=09=090x8,=09/* INST_RETIRED */ +=09}; + +=09if (!satisfy_prerequisites(events, ARRAY_SIZE(events))) +=09=09return; + +=09implemented_counter_mask =3D (1 << pmu.nb_implemented_counters) - 1; +=09non_implemented_counter_mask =3D ~((1 << 31) | implemented_counter_mask= ); +=09counter_mask =3D implemented_counter_mask | non_implemented_counter_mas= k; + + write_regn(pmevtyper, 0, events[0] | PMEVTYPER_EXCLUDE_EL0); + write_regn(pmevtyper, 1, events[1] | PMEVTYPER_EXCLUDE_EL0); + +=09/* disable all counters */ +=09write_sysreg_s(0xFFFFFFFF, PMCNTENCLR_EL0); +=09report("pmcntenclr: disable all counters", +=09 !read_sysreg_s(PMCNTENCLR_EL0) && !read_sysreg_s(PMCNTENSET_EL0)= ); + +=09/* +=09 * clear cycle and all event counters and allow counter enablement +=09 * through PMCNTENSET. LC is RES1. +=09 */ +=09set_pmcr(pmu.pmcr_ro | PMU_PMCR_LC | PMU_PMCR_C | PMU_PMCR_P); +=09isb();=09 +=09report("pmcr: reset counters", get_pmcr() =3D=3D (pmu.pmcr_ro | PMU_PMC= R_LC)); + +=09/* Preset counter #0 to 0xFFFFFFF0 to trigger an overflow interrupt */ +=09write_regn(pmevcntr, 0, 0xFFFFFFF0); +=09report("counter #0 preset to 0xFFFFFFF0", +=09=09read_regn(pmevcntr, 0) =3D=3D 0xFFFFFFF0); +=09report("counter #1 is 0", !read_regn(pmevcntr, 1)); + +=09/* +=09 * Enable all implemented counters and also attempt to enable +=09 * not supported counters. Counting still is disabled by !PMCR.E +=09 */ +=09write_sysreg_s(counter_mask, PMCNTENSET_EL0); + +=09/* check only those implemented are enabled */ +=09report("pmcntenset: enabled implemented_counters", +=09 (read_sysreg_s(PMCNTENSET_EL0) =3D=3D read_sysreg_s(PMCNTENCLR_E= L0)) && +=09=09(read_sysreg_s(PMCNTENSET_EL0) =3D=3D implemented_counter_mask)); + +=09/* Disable all counters but counters #0 and #1 */ +=09write_sysreg_s(~0x3, PMCNTENCLR_EL0); +=09report("pmcntenset: just enabled #0 and #1", +=09 (read_sysreg_s(PMCNTENSET_EL0) =3D=3D read_sysreg_s(PMCNTENCLR_E= L0)) && +=09=09(read_sysreg_s(PMCNTENSET_EL0) =3D=3D 0x3)); + +=09/* clear overflow register */ +=09write_sysreg(0xFFFFFFFF, pmovsclr_el0); +=09report("check overflow reg is 0", !read_sysreg(pmovsclr_el0)); + +=09/* disable overflow interrupts on all counters*/ +=09write_sysreg(0xFFFFFFFF, pmintenclr_el1); +=09report("pmintenclr_el1=3D0, all interrupts disabled", +=09=09!read_sysreg(pmintenclr_el1)); + +=09/* enable overflow interrupts on all event counters */ +=09write_sysreg(implemented_counter_mask | non_implemented_counter_mask, +=09=09 pmintenset_el1); +=09report("overflow interrupts enabled on all implemented counters", +=09=09read_sysreg(pmintenset_el1) =3D=3D implemented_counter_mask); + +=09/* Set PMCR.E, execute asm code and unset PMCR.E */ +=09precise_instrs_loop(20, pmu.pmcr_ro | PMU_PMCR_E); + +=09report_info("counter #0 is 0x%lx (CPU_CYCLES)", read_regn(pmevcntr, 0))= ; +=09report_info("counter #1 is 0x%lx (INST_RETIRED)", read_regn(pmevcntr, 1= )); + +=09report_info("overflow reg =3D 0x%lx", read_sysreg(pmovsclr_el0) ); +=09report("check overflow happened on #0 only", read_sysreg(pmovsclr_el0) = & 0x1); +} + +static void test_mem_access(void) +{ +=09void *addr =3D malloc(PAGE_SIZE); +=09uint32_t events[] =3D { + 0x13, /* MEM_ACCESS */ + 0x13, /* MEM_ACCESS */ + }; + +=09if (!satisfy_prerequisites(events, ARRAY_SIZE(events))) +=09=09return; + +=09pmu_reset(); + + write_regn(pmevtyper, 0, events[0] | PMEVTYPER_EXCLUDE_EL0); + write_regn(pmevtyper, 1, events[1] | PMEVTYPER_EXCLUDE_EL0); +=09write_sysreg_s(0x3, PMCNTENSET_EL0); +=09isb(); +=09mem_access_loop(addr, 20, pmu.pmcr_ro | PMU_PMCR_E); +=09report_info("counter #0 is %ld (MEM_ACCESS)", read_regn(pmevcntr, 0)); +=09report_info("counter #1 is %ld (MEM_ACCESS)", read_regn(pmevcntr, 1)); +=09/* We may not measure exactly 20 mem access, this depends on the platfo= rm */ +=09report("Ran 20 mem accesses", +=09 (read_regn(pmevcntr, 0) =3D=3D read_regn(pmevcntr, 1)) && +=09 (read_regn(pmevcntr, 0) >=3D 20) && !read_sysreg(pmovsclr_el0)); + +=09pmu_reset(); + +=09write_regn(pmevcntr, 0, 0xFFFFFFFA); +=09write_regn(pmevcntr, 1, 0xFFFFFFF0); +=09write_sysreg_s(0x3, PMCNTENSET_EL0); +=09isb(); +=09mem_access_loop(addr, 20, pmu.pmcr_ro | PMU_PMCR_E); +=09report("Ran 20 mem accesses with expected overflows on both counters", +=09 read_sysreg(pmovsclr_el0) =3D=3D 0x3); +=09report_info("cnt#0 =3D %ld cnt#1=3D%ld overflow=3D0x%lx", +=09=09=09read_regn(pmevcntr, 0), read_regn(pmevcntr, 1), +=09=09=09read_sysreg(pmovsclr_el0)); +} + #endif =20 /* @@ -394,6 +639,15 @@ int main(int argc, char *argv[]) =09} else if (strcmp(argv[1], "event-introspection") =3D=3D 0) { =09=09report_prefix_push(argv[1]); =09=09test_event_introspection(); + } else if (strcmp(argv[1], "event-counter-config") =3D=3D 0) { + report_prefix_push(argv[1]); +=09=09test_event_counter_config(); +=09} else if (strcmp(argv[1], "basic-event-count") =3D=3D 0) { +=09=09report_prefix_push(argv[1]); +=09=09test_basic_event_count(); +=09} else if (strcmp(argv[1], "mem-access") =3D=3D 0) { +=09=09report_prefix_push(argv[1]); +=09=09test_mem_access(); =09} else { =09=09report_abort("Unknown subtest '%s'", argv[1]); =09} diff --git a/arm/unittests.cfg b/arm/unittests.cfg index 4433ef3..7a59403 100644 --- a/arm/unittests.cfg +++ b/arm/unittests.cfg @@ -72,6 +72,24 @@ groups =3D pmu arch =3D arm64 extra_params =3D -append 'event-introspection' =20 +[pmu-event-counter-config] +file =3D pmu.flat +groups =3D pmu +arch =3D arm64 +extra_params =3D -append 'event-counter-config' + +[pmu-basic-event-count] +file =3D pmu.flat +groups =3D pmu +arch =3D arm64 +extra_params =3D -append 'basic-event-count' + +[pmu-mem-access] +file =3D pmu.flat +groups =3D pmu +arch =3D arm64 +extra_params =3D -append 'mem-access' + # Test PMU support (TCG) with -icount IPC=3D1 #[pmu-tcg-icount-1] #file =3D pmu.flat --=20 2.20.1 From MAILER-DAEMON Fri Dec 06 12:28:09 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1idHOj-00025o-03 for mharc-qemu-arm@gnu.org; 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bh=cSQq/C7pHCzkPl8tiWZuEBhfZM9PZ9tXND49zKMJFso=; b=auC4eH5FY42YDKcpTP9ic8ih/NWuoeIT4++bCj/B7CsjltpeCjbK272R3QRCFRD0CC4qBP DAcYPRhoJmJnbvto7InlVI/gGQxZicOArVnXnMwNI2eTiSS11BV+gDfegQEsaAMVnGykLq Uvow8soO1ZMexvJVaqi4kgi6eysEMn0= Received: from mimecast-mx01.redhat.com (mimecast-mx01.redhat.com [209.132.183.4]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-308-8c5GEJRsMwWaBaD1nzgbAw-1; Fri, 06 Dec 2019 12:28:02 -0500 Received: from smtp.corp.redhat.com (int-mx02.intmail.prod.int.phx2.redhat.com [10.5.11.12]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx01.redhat.com (Postfix) with ESMTPS id 8EB4F107ACC7; Fri, 6 Dec 2019 17:28:00 +0000 (UTC) Received: from laptop.redhat.com (ovpn-116-117.ams2.redhat.com [10.36.116.117]) by smtp.corp.redhat.com (Postfix) with ESMTP id 1101760BF4; Fri, 6 Dec 2019 17:27:57 +0000 (UTC) From: Eric Auger To: eric.auger.pro@gmail.com, eric.auger@redhat.com, maz@kernel.org, kvmarm@lists.cs.columbia.edu, kvm@vger.kernel.org, qemu-devel@nongnu.org, qemu-arm@nongnu.org Cc: drjones@redhat.com, andrew.murray@arm.com, andre.przywara@arm.com, peter.maydell@linaro.org Subject: [kvm-unit-tests RFC 06/10] pmu: Test chained counter Date: Fri, 6 Dec 2019 18:27:20 +0100 Message-Id: <20191206172724.947-7-eric.auger@redhat.com> In-Reply-To: <20191206172724.947-1-eric.auger@redhat.com> References: <20191206172724.947-1-eric.auger@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.79 on 10.5.11.12 X-MC-Unique: 8c5GEJRsMwWaBaD1nzgbAw-1 X-Mimecast-Spam-Score: 0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 205.139.110.120 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 06 Dec 2019 17:28:07 -0000 Add 2 tests exercising chained counters. The first one uses CPU_CYCLES and the second one uses SW_INCR. Signed-off-by: Eric Auger --- arm/pmu.c | 125 ++++++++++++++++++++++++++++++++++++++++++++++ arm/unittests.cfg | 12 +++++ 2 files changed, 137 insertions(+) diff --git a/arm/pmu.c b/arm/pmu.c index 8ffeb93..e185809 100644 --- a/arm/pmu.c +++ b/arm/pmu.c @@ -114,6 +114,8 @@ static void test_event_introspection(void) {} static void test_event_counter_config(void) {} static void test_basic_event_count(void) {} static void test_mem_access(void) {} +static void test_chained_counters(void) {} +static void test_chained_sw_incr(void) {} =20 #elif defined(__aarch64__) #define ID_AA64DFR0_PERFMON_SHIFT 8 @@ -452,6 +454,123 @@ static void test_mem_access(void) =09=09=09read_sysreg(pmovsclr_el0)); } =20 +static void test_chained_counters(void) +{ +=09uint32_t events[] =3D { 0x11 /* CPU_CYCLES */, 0x1E /* CHAIN */}; + +=09if (!satisfy_prerequisites(events, ARRAY_SIZE(events))) +=09=09return; + +=09pmu_reset(); + + write_regn(pmevtyper, 0, events[0] | PMEVTYPER_EXCLUDE_EL0); + write_regn(pmevtyper, 1, events[1] | PMEVTYPER_EXCLUDE_EL0); +=09/* enable counters #0 and #1 */ +=09write_sysreg_s(0x3, PMCNTENSET_EL0); +=09/* preset counter #0 at 0xFFFFFFF0 */ +=09write_regn(pmevcntr, 0, 0xFFFFFFF0); + +=09precise_instrs_loop(22, pmu.pmcr_ro | PMU_PMCR_E); + +=09report("CHAIN counter #1 incremented", read_regn(pmevcntr, 1) =3D=3D 1)= ;=20 +=09report("check no overflow is recorded", !read_sysreg(pmovsclr_el0)); + +=09/* test 64b overflow */ + +=09pmu_reset(); +=09write_sysreg_s(0x3, PMCNTENSET_EL0); + +=09write_regn(pmevcntr, 0, 0xFFFFFFF0); +=09write_regn(pmevcntr, 1, 0x1); +=09precise_instrs_loop(22, pmu.pmcr_ro | PMU_PMCR_E); +=09report_info("overflow reg =3D 0x%lx", read_sysreg(pmovsclr_el0)); +=09report("CHAIN counter #1 incremented", read_regn(pmevcntr, 1) =3D=3D 2)= ;=20 +=09report("check no overflow is recorded", !read_sysreg(pmovsclr_el0)); + +=09write_regn(pmevcntr, 0, 0xFFFFFFF0); +=09write_regn(pmevcntr, 1, 0xFFFFFFFF); + +=09precise_instrs_loop(22, pmu.pmcr_ro | PMU_PMCR_E); +=09report_info("overflow reg =3D 0x%lx", read_sysreg(pmovsclr_el0)); +=09report("CHAIN counter #1 wrapped", !read_regn(pmevcntr, 1));=20 +=09report("check no overflow is recorded", read_sysreg(pmovsclr_el0) =3D= =3D 0x2); +} + +static void test_chained_sw_incr(void) +{ +=09uint32_t events[] =3D { 0x0 /* SW_INCR */, 0x0 /* SW_INCR */}; +=09int i; + +=09if (!satisfy_prerequisites(events, ARRAY_SIZE(events))) +=09=09return; + +=09pmu_reset(); + + write_regn(pmevtyper, 0, events[0] | PMEVTYPER_EXCLUDE_EL0); + write_regn(pmevtyper, 1, events[1] | PMEVTYPER_EXCLUDE_EL0); +=09/* enable counters #0 and #1 */ +=09write_sysreg_s(0x3, PMCNTENSET_EL0); + +=09/* preset counter #0 at 0xFFFFFFF0 */ +=09write_regn(pmevcntr, 0, 0xFFFFFFF0); + +=09for (i =3D 0; i < 100; i++) { +=09=09write_sysreg(0x1, pmswinc_el0); +=09} +=09report_info("SW_INCR counter #0 has value %ld", read_regn(pmevcntr, 0))= ;=20 +=09report("PWSYNC does not increment if PMCR.E is unset", +=09=09read_regn(pmevcntr, 0) =3D=3D 0xFFFFFFF0); + +=09pmu_reset(); + +=09write_regn(pmevcntr, 0, 0xFFFFFFF0); +=09write_sysreg_s(0x3, PMCNTENSET_EL0); +=09set_pmcr(pmu.pmcr_ro | PMU_PMCR_E); + +=09for (i =3D 0; i < 100; i++) { +=09=09write_sysreg(0x3, pmswinc_el0); +=09} +=09report("counter #1 after + 100 SW_INCR", read_regn(pmevcntr, 0) =3D=3D= 84); +=09report("counter #0 after + 100 SW_INCR", read_regn(pmevcntr, 1) =3D=3D= 100); +=09report_info(" counter values after 100 SW_INCR #0=3D%ld #1=3D%ld", +=09=09=09read_regn(pmevcntr, 0), read_regn(pmevcntr, 1)); +=09report("overflow reg after 100 SW_INCR", read_sysreg(pmovsclr_el0) =3D= =3D 0x1); + +=09/* 64b SW_INCR */ +=09pmu_reset(); + +=09events[1] =3D 0x1E /* CHAIN */; + write_regn(pmevtyper, 1, events[1] | PMEVTYPER_EXCLUDE_EL0); +=09write_regn(pmevcntr, 0, 0xFFFFFFF0); +=09write_sysreg_s(0x3, PMCNTENSET_EL0); +=09set_pmcr(pmu.pmcr_ro | PMU_PMCR_E); +=09for (i =3D 0; i < 100; i++) { +=09=09write_sysreg(0x3, pmswinc_el0); +=09} +=09report("overflow reg after 100 SW_INCR/CHAIN", +=09=09!read_sysreg(pmovsclr_el0) && (read_regn(pmevcntr, 1) =3D=3D 1)); +=09report_info("overflow=3D0x%lx, #0=3D%ld #1=3D%ld", read_sysreg(pmovsclr= _el0), +=09=09 read_regn(pmevcntr, 0), read_regn(pmevcntr, 1)); + +=09/* 64b SW_INCR and overflow on CHAIN counter*/ +=09pmu_reset(); + + write_regn(pmevtyper, 1, events[1] | PMEVTYPER_EXCLUDE_EL0); +=09write_regn(pmevcntr, 0, 0xFFFFFFF0); +=09write_regn(pmevcntr, 1, 0xFFFFFFFF); +=09write_sysreg_s(0x3, PMCNTENSET_EL0); +=09set_pmcr(pmu.pmcr_ro | PMU_PMCR_E); +=09for (i =3D 0; i < 100; i++) { +=09=09write_sysreg(0x3, pmswinc_el0); +=09} +=09report("overflow reg after 100 SW_INCR/CHAIN", +=09=09(read_sysreg(pmovsclr_el0) =3D=3D 0x2) && +=09=09(read_regn(pmevcntr, 1) =3D=3D 0) && +=09=09(read_regn(pmevcntr, 0) =3D=3D 84)); +=09report_info("overflow=3D0x%lx, #0=3D%ld #1=3D%ld", read_sysreg(pmovsclr= _el0), +=09=09 read_regn(pmevcntr, 0), read_regn(pmevcntr, 1)); +} + #endif =20 /* @@ -648,6 +767,12 @@ int main(int argc, char *argv[]) =09} else if (strcmp(argv[1], "mem-access") =3D=3D 0) { =09=09report_prefix_push(argv[1]); =09=09test_mem_access(); +=09} else if (strcmp(argv[1], "chained-counters") =3D=3D 0) { +=09=09report_prefix_push(argv[1]); +=09=09test_chained_counters(); +=09} else if (strcmp(argv[1], "chained-sw-incr") =3D=3D 0) { +=09=09report_prefix_push(argv[1]); +=09=09test_chained_sw_incr(); =09} else { =09=09report_abort("Unknown subtest '%s'", argv[1]); =09} diff --git a/arm/unittests.cfg b/arm/unittests.cfg index 7a59403..1bd4319 100644 --- a/arm/unittests.cfg +++ b/arm/unittests.cfg @@ -90,6 +90,18 @@ groups =3D pmu arch =3D arm64 extra_params =3D -append 'mem-access' =20 +[pmu-chained-counters] +file =3D pmu.flat +groups =3D pmu +arch =3D arm64 +extra_params =3D -append 'chained-counters' + +[pmu-chained-sw-incr] +file =3D pmu.flat +groups =3D pmu +arch =3D arm64 +extra_params =3D -append 'chained-sw-incr' + # Test PMU support (TCG) with -icount IPC=3D1 #[pmu-tcg-icount-1] #file =3D pmu.flat --=20 2.20.1 From MAILER-DAEMON Fri Dec 06 12:28:15 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1idHOn-00029X-Te for mharc-qemu-arm@gnu.org; Fri, 06 Dec 2019 12:28:15 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:46783) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1idHOi-00025d-N0 for qemu-arm@nongnu.org; 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Fri, 06 Dec 2019 12:28:05 -0500 Received: from smtp.corp.redhat.com (int-mx02.intmail.prod.int.phx2.redhat.com [10.5.11.12]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx01.redhat.com (Postfix) with ESMTPS id 697F7107ACC4; Fri, 6 Dec 2019 17:28:03 +0000 (UTC) Received: from laptop.redhat.com (ovpn-116-117.ams2.redhat.com [10.36.116.117]) by smtp.corp.redhat.com (Postfix) with ESMTP id E3D7160BF4; Fri, 6 Dec 2019 17:28:00 +0000 (UTC) From: Eric Auger To: eric.auger.pro@gmail.com, eric.auger@redhat.com, maz@kernel.org, kvmarm@lists.cs.columbia.edu, kvm@vger.kernel.org, qemu-devel@nongnu.org, qemu-arm@nongnu.org Cc: drjones@redhat.com, andrew.murray@arm.com, andre.przywara@arm.com, peter.maydell@linaro.org Subject: [kvm-unit-tests RFC 07/10] arm: pmu: test 32-bit <-> 64-bit transitions Date: Fri, 6 Dec 2019 18:27:21 +0100 Message-Id: <20191206172724.947-8-eric.auger@redhat.com> In-Reply-To: <20191206172724.947-1-eric.auger@redhat.com> References: <20191206172724.947-1-eric.auger@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.79 on 10.5.11.12 X-MC-Unique: F-9tv1RVOcePy6CWYZVclw-1 X-Mimecast-Spam-Score: 0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 207.211.31.120 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 06 Dec 2019 17:28:11 -0000 --- arm/pmu.c | 125 +++++++++++++++++++++++++++++++++++++++++++++- arm/unittests.cfg | 6 +++ 2 files changed, 130 insertions(+), 1 deletion(-) diff --git a/arm/pmu.c b/arm/pmu.c index e185809..47d46a2 100644 --- a/arm/pmu.c +++ b/arm/pmu.c @@ -116,6 +116,7 @@ static void test_basic_event_count(void) {} static void test_mem_access(void) {} static void test_chained_counters(void) {} static void test_chained_sw_incr(void) {} +static void test_chain_promotion(void) {} =20 #elif defined(__aarch64__) #define ID_AA64DFR0_PERFMON_SHIFT 8 @@ -262,7 +263,6 @@ asm volatile( =09: ); } =20 - static void pmu_reset(void) { =09/* reset all counters, counting disabled at PMCR level*/ @@ -571,6 +571,126 @@ static void test_chained_sw_incr(void) =09=09 read_regn(pmevcntr, 0), read_regn(pmevcntr, 1)); } =20 +static void test_chain_promotion(void) +{ +=09uint32_t events[] =3D { 0x13 /* MEM_ACCESS */, 0x1E /* CHAIN */}; +=09void *addr =3D malloc(PAGE_SIZE); + +=09if (!satisfy_prerequisites(events, ARRAY_SIZE(events))) +=09=09return; + +=09/* Only enable CHAIN counter */ +=09pmu_reset(); + write_regn(pmevtyper, 0, events[0] | PMEVTYPER_EXCLUDE_EL0); + write_regn(pmevtyper, 1, events[1] | PMEVTYPER_EXCLUDE_EL0); +=09write_sysreg_s(0x2, PMCNTENSET_EL0); +=09isb(); + +=09mem_access_loop(addr, 20, pmu.pmcr_ro | PMU_PMCR_E); +=09report("chain counter not counting if even counter is disabled", +=09=09!read_regn(pmevcntr, 0)); + +=09/* Only enable even counter */ +=09pmu_reset(); +=09write_regn(pmevcntr, 0, 0xFFFFFFF0); +=09write_sysreg_s(0x1, PMCNTENSET_EL0); +=09isb(); + +=09mem_access_loop(addr, 20, pmu.pmcr_ro | PMU_PMCR_E); +=09report("odd counter did not increment on overflow if disabled", +=09=09!read_regn(pmevcntr, 1) && (read_sysreg(pmovsclr_el0) =3D=3D 0x1)); +=09report_info("MEM_ACCESS counter #0 has value %ld", read_regn(pmevcntr, = 0));=20 +=09report_info("CHAIN counter #1 has value %ld", read_regn(pmevcntr, 1));= =20 +=09report_info("overflow counter %ld", read_sysreg(pmovsclr_el0)); + +=09/* start at 0xFFFFFFDC, +20 with CHAIN enabled, +20 with CHAIN disabled= */ +=09pmu_reset(); +=09write_sysreg_s(0x3, PMCNTENSET_EL0); +=09write_regn(pmevcntr, 0, 0xFFFFFFDC); +=09isb(); + +=09mem_access_loop(addr, 20, pmu.pmcr_ro | PMU_PMCR_E); +=09report_info("MEM_ACCESS counter #0 has value 0x%lx", read_regn(pmevcntr= , 0));=20 + +=09/* disable the CHAIN event */ +=09write_sysreg_s(0x2, PMCNTENCLR_EL0); +=09mem_access_loop(addr, 20, pmu.pmcr_ro | PMU_PMCR_E); +=09report_info("MEM_ACCESS counter #0 has value 0x%lx", read_regn(pmevcntr= , 0));=20 +=09report("should have triggered an overflow on #0", read_sysreg(pmovsclr_= el0) =3D=3D 0x1); +=09report("CHAIN counter #1 shouldn't have incremented", !read_regn(pmevcn= tr, 1)); + +=09/* start at 0xFFFFFFDC, +20 with CHAIN disabled, +20 with CHAIN enabled= */ + +=09pmu_reset(); +=09write_sysreg_s(0x1, PMCNTENSET_EL0); +=09write_regn(pmevcntr, 0, 0xFFFFFFDC); +=09isb(); +=09report_info("counter #0 =3D 0x%lx, counter #1 =3D 0x%lx overflow=3D0x%l= x", +=09=09 read_regn(pmevcntr, 0), read_regn(pmevcntr, 1), +=09=09 read_sysreg(pmovsclr_el0)); + +=09mem_access_loop(addr, 20, pmu.pmcr_ro | PMU_PMCR_E); +=09report_info("MEM_ACCESS counter #0 has value 0x%lx", read_regn(pmevcntr= , 0));=20 + +=09/* enable the CHAIN event */ +=09write_sysreg_s(0x3, PMCNTENSET_EL0); +=09isb(); +=09mem_access_loop(addr, 20, pmu.pmcr_ro | PMU_PMCR_E); +=09report_info("MEM_ACCESS counter #0 has value 0x%lx", read_regn(pmevcntr= , 0));=20 + +=09report("CHAIN counter #1 should have incremented and no overflow expect= ed", +=09=09(read_regn(pmevcntr, 1) =3D=3D 1) && !read_sysreg(pmovsclr_el0)); + +=09report_info("CHAIN counter #1 =3D 0x%lx, overflow=3D0x%lx", +=09=09read_regn(pmevcntr, 1), read_sysreg(pmovsclr_el0)); + +=09/* start as MEM_ACCESS/CPU_CYCLES and move to CHAIN/MEM_ACCESS */ +=09pmu_reset(); + write_regn(pmevtyper, 0, 0x13 /* MEM_ACCESS */ | PMEVTYPER_EXCLUDE= _EL0); + write_regn(pmevtyper, 1, 0x11 /* CPU_CYCLES */ | PMEVTYPER_EXCLUDE= _EL0); +=09write_sysreg_s(0x3, PMCNTENSET_EL0); +=09write_regn(pmevcntr, 0, 0xFFFFFFDC); +=09isb(); + +=09mem_access_loop(addr, 20, pmu.pmcr_ro | PMU_PMCR_E); +=09report_info("MEM_ACCESS counter #0 has value 0x%lx", read_regn(pmevcntr= , 0));=20 + +=09/* 0 becomes CHAINED */ +=09write_sysreg_s(0x0, PMCNTENSET_EL0); + write_regn(pmevtyper, 1, 0x1E /* CHAIN */ | PMEVTYPER_EXCLUDE_EL0)= ; +=09write_sysreg_s(0x3, PMCNTENSET_EL0); + +=09mem_access_loop(addr, 20, pmu.pmcr_ro | PMU_PMCR_E); +=09report_info("MEM_ACCESS counter #0 has value 0x%lx", read_regn(pmevcntr= , 0));=20 + +=09report("CHAIN counter #1 should have incremented and no overflow expect= ed", +=09=09(read_regn(pmevcntr, 1) =3D=3D 1) && !read_sysreg(pmovsclr_el0)); + +=09report_info("CHAIN counter #1 =3D 0x%lx, overflow=3D0x%lx", +=09=09read_regn(pmevcntr, 1), read_sysreg(pmovsclr_el0)); + +=09/* start as CHAIN/MEM_ACCESS and move to MEM_ACCESS/CPU_CYCLES */ +=09pmu_reset(); + write_regn(pmevtyper, 0, 0x13 /* MEM_ACCESS */ | PMEVTYPER_EXCLUDE= _EL0); + write_regn(pmevtyper, 1, 0x1E /* CHAIN */ | PMEVTYPER_EXCLUDE_EL0)= ; +=09write_regn(pmevcntr, 0, 0xFFFFFFDC); +=09write_sysreg_s(0x3, PMCNTENSET_EL0); + +=09mem_access_loop(addr, 20, pmu.pmcr_ro | PMU_PMCR_E); +=09report_info("counter #0=3D0x%lx, counter #1=3D0x%lx", +=09=09=09read_regn(pmevcntr, 0), read_regn(pmevcntr, 1)); + +=09write_sysreg_s(0x0, PMCNTENSET_EL0); + write_regn(pmevtyper, 1, 0x11 /* CPU_CYCLES */ | PMEVTYPER_EXCLUDE= _EL0); +=09write_sysreg_s(0x3, PMCNTENSET_EL0); + +=09mem_access_loop(addr, 20, pmu.pmcr_ro | PMU_PMCR_E); +=09report("overflow is expected on counter 0", read_sysreg(pmovsclr_el0) = =3D=3D 1); +=09report_info("counter #0=3D0x%lx, counter #1=3D0x%lx overflow=3D0x%lx", +=09=09=09read_regn(pmevcntr, 0), read_regn(pmevcntr, 1), +=09=09=09read_sysreg(pmovsclr_el0)); +} + #endif =20 /* @@ -773,6 +893,9 @@ int main(int argc, char *argv[]) =09} else if (strcmp(argv[1], "chained-sw-incr") =3D=3D 0) { =09=09report_prefix_push(argv[1]); =09=09test_chained_sw_incr(); +=09} else if (strcmp(argv[1], "chain-promotion") =3D=3D 0) { +=09=09report_prefix_push(argv[1]); +=09=09test_chain_promotion(); =09} else { =09=09report_abort("Unknown subtest '%s'", argv[1]); =09} diff --git a/arm/unittests.cfg b/arm/unittests.cfg index 1bd4319..eb6e87e 100644 --- a/arm/unittests.cfg +++ b/arm/unittests.cfg @@ -102,6 +102,12 @@ groups =3D pmu arch =3D arm64 extra_params =3D -append 'chained-sw-incr' =20 +[pmu-chain-promotion] +file =3D pmu.flat +groups =3D pmu +arch =3D arm64 +extra_params =3D -append 'chain-promotion' + # Test PMU support (TCG) with -icount IPC=3D1 #[pmu-tcg-icount-1] #file =3D pmu.flat --=20 2.20.1 From MAILER-DAEMON Fri Dec 06 12:28:16 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1idHOq-0002C0-LK for mharc-qemu-arm@gnu.org; Fri, 06 Dec 2019 12:28:16 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:47132) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1idHOm-00028O-Jt for qemu-arm@nongnu.org; Fri, 06 Dec 2019 12:28:15 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1idHOk-0004D4-En for qemu-arm@nongnu.org; Fri, 06 Dec 2019 12:28:11 -0500 Received: from us-smtp-delivery-1.mimecast.com ([207.211.31.120]:27320 helo=us-smtp-1.mimecast.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1idHOk-0004B1-1S for qemu-arm@nongnu.org; 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Fri, 6 Dec 2019 17:28:06 +0000 (UTC) Received: from laptop.redhat.com (ovpn-116-117.ams2.redhat.com [10.36.116.117]) by smtp.corp.redhat.com (Postfix) with ESMTP id C04AC60BF4; Fri, 6 Dec 2019 17:28:03 +0000 (UTC) From: Eric Auger To: eric.auger.pro@gmail.com, eric.auger@redhat.com, maz@kernel.org, kvmarm@lists.cs.columbia.edu, kvm@vger.kernel.org, qemu-devel@nongnu.org, qemu-arm@nongnu.org Cc: drjones@redhat.com, andrew.murray@arm.com, andre.przywara@arm.com, peter.maydell@linaro.org Subject: [kvm-unit-tests RFC 08/10] arm: gic: Provide per-IRQ helper functions Date: Fri, 6 Dec 2019 18:27:22 +0100 Message-Id: <20191206172724.947-9-eric.auger@redhat.com> In-Reply-To: <20191206172724.947-1-eric.auger@redhat.com> References: <20191206172724.947-1-eric.auger@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.79 on 10.5.11.12 X-MC-Unique: ZjMCxGmWPFqGGTt0nhH_nA-1 X-Mimecast-Spam-Score: 0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 207.211.31.120 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 06 Dec 2019 17:28:15 -0000 From: Andre Przywara A common theme when accessing per-IRQ parameters in the GIC distributor is to set fields of a certain bit width in a range of MMIO registers. Examples are the enabled status (one bit per IRQ), the level/edge configuration (2 bits per IRQ) or the priority (8 bits per IRQ). Add a generic helper function which is able to mask and set the respective number of bits, given the IRQ number and the MMIO offset. Provide wrappers using this function to easily allow configuring an IRQ. For now assume that private IRQ numbers always refer to the current CPU. In a GICv2 accessing the "other" private IRQs is not easily doable (the registers are banked per CPU on the same MMIO address), so we impose the same limitation on GICv3, even though those registers are not banked there anymore. Signed-off-by: Andre Przywara --- initialize reg --- lib/arm/asm/gic-v3.h | 2 + lib/arm/asm/gic.h | 9 +++++ lib/arm/gic.c | 90 ++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 101 insertions(+) diff --git a/lib/arm/asm/gic-v3.h b/lib/arm/asm/gic-v3.h index 347be2f..4a445a5 100644 --- a/lib/arm/asm/gic-v3.h +++ b/lib/arm/asm/gic-v3.h @@ -23,6 +23,8 @@ #define GICD_CTLR_ENABLE_G1A=09=09(1U << 1) #define GICD_CTLR_ENABLE_G1=09=09(1U << 0) =20 +#define GICD_IROUTER=09=09=090x6000 + /* Re-Distributor registers, offsets from RD_base */ #define GICR_TYPER=09=09=090x0008 =20 diff --git a/lib/arm/asm/gic.h b/lib/arm/asm/gic.h index 1fc10a0..21cdb58 100644 --- a/lib/arm/asm/gic.h +++ b/lib/arm/asm/gic.h @@ -15,6 +15,7 @@ #define GICD_IIDR=09=09=090x0008 #define GICD_IGROUPR=09=09=090x0080 #define GICD_ISENABLER=09=09=090x0100 +#define GICD_ICENABLER=09=09=090x0180 #define GICD_ISPENDR=09=09=090x0200 #define GICD_ICPENDR=09=09=090x0280 #define GICD_ISACTIVER=09=09=090x0300 @@ -73,5 +74,13 @@ extern void gic_write_eoir(u32 irqstat); extern void gic_ipi_send_single(int irq, int cpu); extern void gic_ipi_send_mask(int irq, const cpumask_t *dest); =20 +void gic_set_irq_bit(int irq, int offset); +void gic_enable_irq(int irq); +void gic_disable_irq(int irq); +void gic_set_irq_priority(int irq, u8 prio); +void gic_set_irq_target(int irq, int cpu); +void gic_set_irq_group(int irq, int group); +int gic_get_irq_group(int irq); + #endif /* !__ASSEMBLY__ */ #endif /* _ASMARM_GIC_H_ */ diff --git a/lib/arm/gic.c b/lib/arm/gic.c index 9430116..aa9cb86 100644 --- a/lib/arm/gic.c +++ b/lib/arm/gic.c @@ -146,3 +146,93 @@ void gic_ipi_send_mask(int irq, const cpumask_t *dest) =09assert(gic_common_ops && gic_common_ops->ipi_send_mask); =09gic_common_ops->ipi_send_mask(irq, dest); } + +enum gic_bit_access { +=09ACCESS_READ, +=09ACCESS_SET, +=09ACCESS_RMW +}; + +static u8 gic_masked_irq_bits(int irq, int offset, int bits, u8 value, +=09=09=09 enum gic_bit_access access) +{ +=09void *base; +=09int split =3D 32 / bits; +=09int shift =3D (irq % split) * bits; +=09u32 reg =3D 0, mask =3D ((1U << bits) - 1) << shift; + +=09switch (gic_version()) { +=09case 2: +=09=09base =3D gicv2_dist_base(); +=09=09break; +=09case 3: +=09=09if (irq < 32) +=09=09=09base =3D gicv3_sgi_base(); +=09=09else +=09=09=09base =3D gicv3_dist_base(); +=09=09break; +=09default: +=09=09return 0; +=09} +=09base +=3D offset + (irq / split) * 4; + +=09switch (access) { +=09case ACCESS_READ: +=09=09return (readl(base) & mask) >> shift; +=09case ACCESS_SET: +=09=09reg =3D 0; +=09=09break; +=09case ACCESS_RMW: +=09=09reg =3D readl(base) & ~mask; +=09=09break; +=09} + +=09writel(reg | ((u32)value << shift), base); + +=09return 0; +} + +void gic_set_irq_bit(int irq, int offset) +{ +=09gic_masked_irq_bits(irq, offset, 1, 1, ACCESS_SET); +} + +void gic_enable_irq(int irq) +{ +=09gic_set_irq_bit(irq, GICD_ISENABLER); +} + +void gic_disable_irq(int irq) +{ +=09gic_set_irq_bit(irq, GICD_ICENABLER); +} + +void gic_set_irq_priority(int irq, u8 prio) +{ +=09gic_masked_irq_bits(irq, GICD_IPRIORITYR, 8, prio, ACCESS_RMW); +} + +void gic_set_irq_target(int irq, int cpu) +{ +=09if (irq < 32) +=09=09return; + +=09if (gic_version() =3D=3D 2) { +=09=09gic_masked_irq_bits(irq, GICD_ITARGETSR, 8, 1U << cpu, +=09=09=09=09 ACCESS_RMW); + +=09=09return; +=09} + +=09writeq(cpus[cpu], gicv3_dist_base() + GICD_IROUTER + irq * 8); +} + +void gic_set_irq_group(int irq, int group) +{ +=09gic_masked_irq_bits(irq, GICD_IGROUPR, 1, group, ACCESS_RMW); +} + +int gic_get_irq_group(int irq) +{ +=09return gic_masked_irq_bits(irq, GICD_IGROUPR, 1, 0, ACCESS_READ); +} --=20 2.20.1 From MAILER-DAEMON Fri Dec 06 12:28:20 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1idHOu-0002IB-DY for mharc-qemu-arm@gnu.org; Fri, 06 Dec 2019 12:28:20 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:47530) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1idHOq-0002CJ-Pr for qemu-arm@nongnu.org; Fri, 06 Dec 2019 12:28:17 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1idHOp-0004Mq-LH for qemu-arm@nongnu.org; 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Fri, 06 Dec 2019 12:28:14 -0500 Received: from smtp.corp.redhat.com (int-mx02.intmail.prod.int.phx2.redhat.com [10.5.11.12]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx01.redhat.com (Postfix) with ESMTPS id B301B1005502; Fri, 6 Dec 2019 17:28:11 +0000 (UTC) Received: from laptop.redhat.com (ovpn-116-117.ams2.redhat.com [10.36.116.117]) by smtp.corp.redhat.com (Postfix) with ESMTP id A0C1E60BF4; Fri, 6 Dec 2019 17:28:06 +0000 (UTC) From: Eric Auger To: eric.auger.pro@gmail.com, eric.auger@redhat.com, maz@kernel.org, kvmarm@lists.cs.columbia.edu, kvm@vger.kernel.org, qemu-devel@nongnu.org, qemu-arm@nongnu.org Cc: drjones@redhat.com, andrew.murray@arm.com, andre.przywara@arm.com, peter.maydell@linaro.org Subject: [kvm-unit-tests RFC 09/10] arm/arm64: gic: Introduce setup_irq() helper Date: Fri, 6 Dec 2019 18:27:23 +0100 Message-Id: <20191206172724.947-10-eric.auger@redhat.com> In-Reply-To: <20191206172724.947-1-eric.auger@redhat.com> References: <20191206172724.947-1-eric.auger@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.79 on 10.5.11.12 X-MC-Unique: K79uiRAXONuXvi2zOw0w7Q-1 X-Mimecast-Spam-Score: 0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 207.211.31.120 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 06 Dec 2019 17:28:18 -0000 ipi_enable() code would be reusable for other interrupts than IPI. Let's rename it setup_irq() and pass an interrupt handler pointer. We also export it to use it in other tests such as the PMU's one. Signed-off-by: Eric Auger --- arm/gic.c | 24 +++--------------------- lib/arm/asm/gic.h | 3 +++ lib/arm/gic.c | 11 +++++++++++ 3 files changed, 17 insertions(+), 21 deletions(-) diff --git a/arm/gic.c b/arm/gic.c index adb6aa4..04919ae 100644 --- a/arm/gic.c +++ b/arm/gic.c @@ -215,20 +215,9 @@ static void ipi_test_smp(void) =09report_prefix_pop(); } =20 -static void ipi_enable(void) -{ -=09gic_enable_defaults(); -#ifdef __arm__ -=09install_exception_handler(EXCPTN_IRQ, ipi_handler); -#else -=09install_irq_handler(EL1H_IRQ, ipi_handler); -#endif -=09local_irq_enable(); -} - static void ipi_send(void) { -=09ipi_enable(); +=09setup_irq(ipi_handler); =09wait_on_ready(); =09ipi_test_self(); =09ipi_test_smp(); @@ -238,7 +227,7 @@ static void ipi_send(void) =20 static void ipi_recv(void) { -=09ipi_enable(); +=09setup_irq(ipi_handler); =09cpumask_set_cpu(smp_processor_id(), &ready); =09while (1) =09=09wfi(); @@ -295,14 +284,7 @@ static void ipi_clear_active_handler(struct pt_regs *r= egs __unused) static void run_active_clear_test(void) { =09report_prefix_push("active"); -=09gic_enable_defaults(); -#ifdef __arm__ -=09install_exception_handler(EXCPTN_IRQ, ipi_clear_active_handler); -#else -=09install_irq_handler(EL1H_IRQ, ipi_clear_active_handler); -#endif -=09local_irq_enable(); - +=09setup_irq(ipi_clear_active_handler); =09ipi_test_self(); =09report_prefix_pop(); } diff --git a/lib/arm/asm/gic.h b/lib/arm/asm/gic.h index 21cdb58..55dd84b 100644 --- a/lib/arm/asm/gic.h +++ b/lib/arm/asm/gic.h @@ -82,5 +82,8 @@ void gic_set_irq_target(int irq, int cpu); void gic_set_irq_group(int irq, int group); int gic_get_irq_group(int irq); =20 +typedef void (*handler_t)(struct pt_regs *regs __unused); +extern void setup_irq(handler_t handler); + #endif /* !__ASSEMBLY__ */ #endif /* _ASMARM_GIC_H_ */ diff --git a/lib/arm/gic.c b/lib/arm/gic.c index aa9cb86..0c5511f 100644 --- a/lib/arm/gic.c +++ b/lib/arm/gic.c @@ -236,3 +236,14 @@ int gic_get_irq_group(int irq) { =09return gic_masked_irq_bits(irq, GICD_IGROUPR, 1, 0, ACCESS_READ); } + +void setup_irq(handler_t handler) +{ + gic_enable_defaults(); +#ifdef __arm__ + install_exception_handler(EXCPTN_IRQ, handler); +#else + install_irq_handler(EL1H_IRQ, handler); +#endif + local_irq_enable(); +} --=20 2.20.1 From MAILER-DAEMON Fri Dec 06 12:28:21 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1idHOv-0002Kp-QZ for mharc-qemu-arm@gnu.org; Fri, 06 Dec 2019 12:28:21 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:48000) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1idHOt-0002Gb-B9 for qemu-arm@nongnu.org; Fri, 06 Dec 2019 12:28:20 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1idHOr-0004Vd-RB for qemu-arm@nongnu.org; Fri, 06 Dec 2019 12:28:19 -0500 Received: from us-smtp-1.mimecast.com ([207.211.31.81]:45436 helo=us-smtp-delivery-1.mimecast.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1idHOr-0004TR-MA for qemu-arm@nongnu.org; Fri, 06 Dec 2019 12:28:17 -0500 DKIM-Signature: v=1; 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Fri, 6 Dec 2019 17:28:11 +0000 (UTC) From: Eric Auger To: eric.auger.pro@gmail.com, eric.auger@redhat.com, maz@kernel.org, kvmarm@lists.cs.columbia.edu, kvm@vger.kernel.org, qemu-devel@nongnu.org, qemu-arm@nongnu.org Cc: drjones@redhat.com, andrew.murray@arm.com, andre.przywara@arm.com, peter.maydell@linaro.org Subject: [kvm-unit-tests RFC 10/10] pmu: Test overflow interrupts Date: Fri, 6 Dec 2019 18:27:24 +0100 Message-Id: <20191206172724.947-11-eric.auger@redhat.com> In-Reply-To: <20191206172724.947-1-eric.auger@redhat.com> References: <20191206172724.947-1-eric.auger@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.79 on 10.5.11.12 X-MC-Unique: BOXZZEcbPF-QJRXfsfQH8w-1 X-Mimecast-Spam-Score: 0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 207.211.31.81 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 06 Dec 2019 17:28:21 -0000 Test overflows for MEM_ACESS and SW_INCR events. Also tests overflows with 64-bit events. Signed-off-by: Eric Auger --- arm/pmu.c | 133 +++++++++++++++++++++++++++++++++++++++++++++- arm/unittests.cfg | 6 +++ 2 files changed, 138 insertions(+), 1 deletion(-) diff --git a/arm/pmu.c b/arm/pmu.c index 47d46a2..a63b93e 100644 --- a/arm/pmu.c +++ b/arm/pmu.c @@ -45,8 +45,12 @@ struct pmu { =09uint32_t pmcr_ro; }; =20 -static struct pmu pmu; +struct pmu_stats { +=09unsigned long bitmap; +=09uint32_t interrupts[32]; +}; =20 +static struct pmu pmu; =20 #if defined(__arm__) #define ID_DFR0_PERFMON_SHIFT 24 @@ -117,6 +121,7 @@ static void test_mem_access(void) {} static void test_chained_counters(void) {} static void test_chained_sw_incr(void) {} static void test_chain_promotion(void) {} +static void test_overflow_interrupt(void) {} =20 #elif defined(__aarch64__) #define ID_AA64DFR0_PERFMON_SHIFT 8 @@ -263,6 +268,43 @@ asm volatile( =09: ); } =20 +static struct pmu_stats pmu_stats; + +static void irq_handler(struct pt_regs *regs) +{ + uint32_t irqstat, irqnr; + + irqstat =3D gic_read_iar(); + irqnr =3D gic_iar_irqnr(irqstat); + gic_write_eoir(irqstat); + + if (irqnr =3D=3D 23) { + unsigned long overflows =3D read_sysreg(pmovsclr_el0); +=09=09int i; + + report_info("--> PMU overflow interrupt %d (counter bitmas= k 0x%lx)", irqnr, overflows); +=09=09for (i =3D 0; i < 32; i++) { +=09=09=09if (test_and_clear_bit(i, &overflows)) { +=09=09=09=09pmu_stats.interrupts[i]++; +=09=09=09=09pmu_stats.bitmap |=3D 1 << i; +=09=09=09} +=09=09} + write_sysreg(0xFFFFFFFF, pmovsclr_el0); + } else { + report_info("Unexpected interrupt: %d\n", irqnr); + } +} + +static void pmu_reset_stats(void) +{ +=09int i; + +=09for (i =3D 0; i < 32; i++) { +=09=09pmu_stats.interrupts[i] =3D 0; +=09} +=09pmu_stats.bitmap =3D 0; +} + static void pmu_reset(void) { =09/* reset all counters, counting disabled at PMCR level*/ @@ -273,6 +315,7 @@ static void pmu_reset(void) =09write_sysreg(0xFFFFFFFF, pmovsclr_el0); =09/* disable overflow interrupts on all counters */ =09write_sysreg(0xFFFFFFFF, pmintenclr_el1); +=09pmu_reset_stats(); =09isb(); } =20 @@ -691,8 +734,93 @@ static void test_chain_promotion(void) =09=09=09read_sysreg(pmovsclr_el0)); } =20 +static bool expect_interrupts(uint32_t bitmap) +{ +=09int i; + +=09if (pmu_stats.bitmap ^ bitmap) +=09=09return false; + +=09for (i =3D 0; i < 32; i++) { +=09=09if (test_and_clear_bit(i, &pmu_stats.bitmap)) +=09=09=09if (pmu_stats.interrupts[i] !=3D 1) +=09=09=09=09return false; +=09} +=09return true; +} + +static void test_overflow_interrupt(void) +{ +=09uint32_t events[] =3D { 0x13 /* MEM_ACCESS */, 0x00 /* SW_INCR */}; +=09void *addr =3D malloc(PAGE_SIZE); +=09int i; + +=09if (!satisfy_prerequisites(events, ARRAY_SIZE(events))) +=09=09return; + +=09setup_irq(irq_handler); +=09gic_enable_irq(23); + +=09pmu_reset(); + + write_regn(pmevtyper, 0, events[0] | PMEVTYPER_EXCLUDE_EL0); + write_regn(pmevtyper, 1, events[1] | PMEVTYPER_EXCLUDE_EL0); +=09write_sysreg_s(0x3, PMCNTENSET_EL0); +=09write_regn(pmevcntr, 0, 0xFFFFFFF0); +=09write_regn(pmevcntr, 1, 0xFFFFFFF0); +=09isb(); + +=09/* interrupts are disabled */ + +=09mem_access_loop(addr, 200, pmu.pmcr_ro | PMU_PMCR_E); +=09report("no overflow interrupt received", expect_interrupts(0)); + +=09set_pmcr(pmu.pmcr_ro | PMU_PMCR_E); +=09for (i =3D 0; i < 100; i++) { +=09=09write_sysreg(0x2, pmswinc_el0); +=09} +=09set_pmcr(pmu.pmcr_ro); +=09report("no overflow interrupt received", expect_interrupts(0)); + +=09/* enable interrupts */ + +=09pmu_reset_stats(); + +=09write_regn(pmevcntr, 0, 0xFFFFFFF0); +=09write_regn(pmevcntr, 1, 0xFFFFFFF0); +=09write_sysreg(0xFFFFFFFF, pmintenset_el1); +=09isb(); + +=09mem_access_loop(addr, 200, pmu.pmcr_ro | PMU_PMCR_E); +=09for (i =3D 0; i < 100; i++) { +=09=09write_sysreg(0x3, pmswinc_el0); +=09} +=09mem_access_loop(addr, 200, pmu.pmcr_ro); +=09report_info("overflow=3D0x%lx", read_sysreg(pmovsclr_el0)); +=09report("overflow interrupts expected on #0 and #1", expect_interrupts(0= x3)); + +=09/* promote to 64-b */ + +=09pmu_reset_stats(); + +=09events[1] =3D 0x1E /* CHAIN */; + write_regn(pmevtyper, 1, events[1] | PMEVTYPER_EXCLUDE_EL0); +=09write_regn(pmevcntr, 0, 0xFFFFFFF0); +=09isb(); +=09mem_access_loop(addr, 200, pmu.pmcr_ro | PMU_PMCR_E); +=09report("no overflow interrupt expected on 32b boundary", expect_interru= pts(0)); + +=09/* overflow on odd counter */ +=09pmu_reset_stats(); +=09write_regn(pmevcntr, 0, 0xFFFFFFF0); +=09write_regn(pmevcntr, 1, 0xFFFFFFFF); +=09isb(); +=09mem_access_loop(addr, 200, pmu.pmcr_ro | PMU_PMCR_E); +=09report("expect overflow interrupt on odd counter", expect_interrupts(0x= 2)); +} #endif =20 + /* * As a simple sanity check on the PMCR_EL0, ensure the implementer field = isn't * null. Also print out a couple other interesting fields for diagnostic @@ -896,6 +1024,9 @@ int main(int argc, char *argv[]) =09} else if (strcmp(argv[1], "chain-promotion") =3D=3D 0) { =09=09report_prefix_push(argv[1]); =09=09test_chain_promotion(); +=09} else if (strcmp(argv[1], "overflow-interrupt") =3D=3D 0) { +=09=09report_prefix_push(argv[1]); +=09=09test_overflow_interrupt(); =09} else { =09=09report_abort("Unknown subtest '%s'", argv[1]); =09} diff --git a/arm/unittests.cfg b/arm/unittests.cfg index eb6e87e..31b4c7a 100644 --- a/arm/unittests.cfg +++ b/arm/unittests.cfg @@ -108,6 +108,12 @@ groups =3D pmu arch =3D arm64 extra_params =3D -append 'chain-promotion' =20 +[pmu-chain-promotion] +file =3D pmu.flat +groups =3D pmu +arch =3D arm64 +extra_params =3D -append 'overflow-interrupt' + # Test PMU support (TCG) with -icount IPC=3D1 #[pmu-tcg-icount-1] #file =3D pmu.flat --=20 2.20.1 From MAILER-DAEMON Fri Dec 06 12:45:55 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1idHfv-0005dt-GU for mharc-qemu-arm@gnu.org; Fri, 06 Dec 2019 12:45:55 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:58424) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1idHXM-0003rR-Bg for qemu-arm@nongnu.org; Fri, 06 Dec 2019 12:37:05 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1idHXK-0001IV-AT for qemu-arm@nongnu.org; Fri, 06 Dec 2019 12:37:03 -0500 Received: from foss.arm.com ([217.140.110.172]:59740) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1idHXK-0001D7-30; Fri, 06 Dec 2019 12:37:02 -0500 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 4A52431B; Fri, 6 Dec 2019 09:37:00 -0800 (PST) Received: from [10.1.196.63] (e123195-lin.cambridge.arm.com [10.1.196.63]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id E51A03F52E; Fri, 6 Dec 2019 09:36:58 -0800 (PST) Subject: Re: [kvm-unit-tests RFC 01/10] arm64: Provide read/write_sysreg_s To: Eric Auger , eric.auger.pro@gmail.com, maz@kernel.org, kvmarm@lists.cs.columbia.edu, kvm@vger.kernel.org, qemu-devel@nongnu.org, qemu-arm@nongnu.org Cc: drjones@redhat.com, andrew.murray@arm.com, andre.przywara@arm.com, peter.maydell@linaro.org References: <20191206172724.947-1-eric.auger@redhat.com> <20191206172724.947-2-eric.auger@redhat.com> From: Alexandru Elisei Message-ID: Date: Fri, 6 Dec 2019 17:36:57 +0000 User-Agent: Mozilla/5.0 (X11; Linux aarch64; rv:60.0) Gecko/20100101 Thunderbird/60.9.0 MIME-Version: 1.0 In-Reply-To: <20191206172724.947-2-eric.auger@redhat.com> Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: 7bit Content-Language: en-US X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 217.140.110.172 X-Mailman-Approved-At: Fri, 06 Dec 2019 12:45:54 -0500 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 06 Dec 2019 17:37:05 -0000 Hi, On 12/6/19 5:27 PM, Eric Auger wrote: > From: Andrew Jones > > Sometimes we need to test access to system registers which are > missing assembler mnemonics. > > Signed-off-by: Andrew Jones > --- > lib/arm64/asm/sysreg.h | 11 +++++++++++ > 1 file changed, 11 insertions(+) > > diff --git a/lib/arm64/asm/sysreg.h b/lib/arm64/asm/sysreg.h > index a03830b..a45eebd 100644 > --- a/lib/arm64/asm/sysreg.h > +++ b/lib/arm64/asm/sysreg.h > @@ -38,6 +38,17 @@ > asm volatile("msr " xstr(r) ", %x0" : : "rZ" (__val)); \ > } while (0) > > +#define read_sysreg_s(r) ({ \ > + u64 __val; \ > + asm volatile("mrs_s %0, " xstr(r) : "=r" (__val)); \ > + __val; \ > +}) > + > +#define write_sysreg_s(v, r) do { \ > + u64 __val = (u64)v; \ > + asm volatile("msr_s " xstr(r) ", %x0" : : "rZ" (__val));\ > +} while (0) > + > asm( > " .irp num,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30\n" > " .equ .L__reg_num_x\\num, \\num\n" That's exactly the code that I wrote for my EL2 series :) Reviewed-by: Alexandru Elisei Thanks, Alex From MAILER-DAEMON Fri Dec 06 12:52:20 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1idHm7-0004px-TQ for mharc-qemu-arm@gnu.org; Fri, 06 Dec 2019 12:52:20 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:45598) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1idHm5-0004o6-AS for qemu-arm@nongnu.org; Fri, 06 Dec 2019 12:52:18 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1idHm4-0003Vs-14 for qemu-arm@nongnu.org; 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[97.113.7.119]) by smtp.gmail.com with ESMTPSA id w11sm15823707pgs.60.2019.12.06.09.52.13 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 06 Dec 2019 09:52:13 -0800 (PST) Subject: Re: [PATCH] target/arm: don't bother with id_aa64pfr0_read for USER_ONLY To: Peter Maydell , =?UTF-8?Q?Alex_Benn=c3=a9e?= Cc: qemu-arm , QEMU Developers References: <20191206122247.7507-1-alex.bennee@linaro.org> From: Richard Henderson Message-ID: <0bbc14b3-ad57-5580-8707-b6c614fbcdc2@linaro.org> Date: Fri, 6 Dec 2019 09:52:11 -0800 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.2.1 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 8bit X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::443 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 06 Dec 2019 17:52:19 -0000 On 12/6/19 7:29 AM, Peter Maydell wrote: > On Fri, 6 Dec 2019 at 12:22, Alex Bennée wrote: >> >> For system emulation we need to check the state of the GIC before we >> report the value. However this isn't relevant to exporting of the >> value to linux-user and indeed breaks the exported value as set by >> modify_arm_cp_regs. >> >> [AJB: the other option would be just to set reset value anyway and not >> ifdef out the readfn as the register will become const anyway] > > If you want it to be const it would be clearer to define it > with ARM_CP_CONST... I'm not sure what an ARM_CP_NO_RAW without > a readfn or a fieldoffset will do on reads. Yep, and the accessfn should be ifdefed away as well. r~ From MAILER-DAEMON Fri Dec 06 13:25:41 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1idIIP-0000PH-B2 for mharc-qemu-arm@gnu.org; Fri, 06 Dec 2019 13:25:41 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:43924) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1idIIM-0000Kt-KP for qemu-arm@nongnu.org; Fri, 06 Dec 2019 13:25:39 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1idIIL-0005sH-9G for qemu-arm@nongnu.org; Fri, 06 Dec 2019 13:25:38 -0500 Received: from mail-wm1-x343.google.com ([2a00:1450:4864:20::343]:38320) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1idIIK-0005nk-UC for qemu-arm@nongnu.org; Fri, 06 Dec 2019 13:25:37 -0500 Received: by mail-wm1-x343.google.com with SMTP id p17so8286832wmi.3 for ; Fri, 06 Dec 2019 10:25:36 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=references:user-agent:from:to:cc:subject:in-reply-to:date :message-id:mime-version:content-transfer-encoding; bh=APhVKom77qZGDibg0Juh23y4l2Jl1d2AiYktXpeIw6Y=; b=vRoMSD6R0Kc5lAanIW38Evq8wrkrM7ARkTTtI3DeM9DG69IleJg+miO+Lx46gHJN0z bZwCKbjsx7aDVKhqWkchUGI+0N1Ml9fznc7FaKmr+gyE0sdRuVqwC/3oIAXIrb8NlVNn 8hHy/fSrM+4F78wfMtVnDSyiHroIQ00O3gZrtqidv7mNNKWLSkSVqd1F59eovZ4p3g22 bVTsQNFnRVIqG2IEulVogKZonogY94sshaqzPaszleODRAAjxMuXiUk9SdPrOnd7uUxr pDwqZbxs4OthxpO4pPMvQg0uxdx90W4kDGGz96O7Ul8LYTHPAuT/EkWwmwwKa/lNOXml TpJw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:references:user-agent:from:to:cc:subject :in-reply-to:date:message-id:mime-version:content-transfer-encoding; bh=APhVKom77qZGDibg0Juh23y4l2Jl1d2AiYktXpeIw6Y=; b=Pz/tEaFIV1dgqVbCL3trdtdolU30EzfqvGhaQRtvJblpHMd3/dPeIKLfoD+KclPFqQ 7vwTMcJ90l83RSqqfqKLe05ndp4D8nibz5MsfGGkoYXtNNuuQ5Ejdpr8top6NncDx8/a 9XjO0ZXyC2Of5VzjUW3xJTrER6o2W0ajDwWole7Vpx4BgQ+V8558Uu14WLqglMRhiMG/ Vx5xdTkSCd4RvfGiJqb8/+UDDmR2bqZJDo7+2NOublWsEQjGnhlj2hLv+5C/GKvYdwEF N7QljhrzIC+r3AvqnHtRaUcBzIdYIUU9lzmvGk6rGrB0LG5hqfSn2PAZa4iKw1B7C5qs hrZA== X-Gm-Message-State: APjAAAXDq/EXDm6LomaHmzS5ve49IpqRrnQot9ebhX8xgYn7f2E36fbu KTnCJIc/yuSUQFRUo3PZ5iOucA== X-Google-Smtp-Source: APXvYqydT2m3OORgjPTrHjMhPqPtP9A9V+teolod7UMttktevBJuUVnyaFe6lUNp+CAr7jdScaU6Bg== X-Received: by 2002:a05:600c:30a:: with SMTP id q10mr11449304wmd.84.1575656735535; Fri, 06 Dec 2019 10:25:35 -0800 (PST) Received: from zen.linaroharston ([51.148.130.216]) by smtp.gmail.com with ESMTPSA id j12sm6285903wrt.55.2019.12.06.10.25.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 06 Dec 2019 10:25:34 -0800 (PST) Received: from zen (localhost [127.0.0.1]) by zen.linaroharston (Postfix) with ESMTP id 978951FF87; Fri, 6 Dec 2019 18:25:33 +0000 (GMT) References: <20191206122247.7507-1-alex.bennee@linaro.org> User-agent: mu4e 1.3.5; emacs 27.0.50 From: Alex =?utf-8?Q?Benn=C3=A9e?= To: Peter Maydell Cc: QEMU Developers , qemu-arm Subject: Re: [PATCH] target/arm: don't bother with id_aa64pfr0_read for USER_ONLY In-reply-to: Date: Fri, 06 Dec 2019 18:25:33 +0000 Message-ID: <87d0d171lu.fsf@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::343 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 06 Dec 2019 18:25:40 -0000 Peter Maydell writes: > On Fri, 6 Dec 2019 at 12:22, Alex Benn=C3=A9e wr= ote: >> >> For system emulation we need to check the state of the GIC before we >> report the value. However this isn't relevant to exporting of the >> value to linux-user and indeed breaks the exported value as set by >> modify_arm_cp_regs. >> >> [AJB: the other option would be just to set reset value anyway and not >> ifdef out the readfn as the register will become const anyway] > > If you want it to be const it would be clearer to define it > with ARM_CP_CONST... I'm not sure what an ARM_CP_NO_RAW without > a readfn or a fieldoffset will do on reads. Well the modify_arm_cp_regs ensures it is ARM_CP_CONST when it changes the definition. It's just ensuring the reset value is set so it can be masked/fixed. However the ifdef approach does reduce the amount of unused stuff in the linux-user build. > > thanks > -- PMM --=20 Alex Benn=C3=A9e From MAILER-DAEMON Fri Dec 06 13:39:21 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1idIVd-0006CL-3t for mharc-qemu-arm@gnu.org; Fri, 06 Dec 2019 13:39:21 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:57259) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1idIVX-0006An-JX for qemu-arm@nongnu.org; Fri, 06 Dec 2019 13:39:16 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1idIVT-0008Vg-4J for qemu-arm@nongnu.org; Fri, 06 Dec 2019 13:39:13 -0500 Received: from mail-ot1-x341.google.com ([2607:f8b0:4864:20::341]:33852) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1idIVP-0008Sz-9V for qemu-arm@nongnu.org; Fri, 06 Dec 2019 13:39:09 -0500 Received: by mail-ot1-x341.google.com with SMTP id a15so6673939otf.1 for ; Fri, 06 Dec 2019 10:39:04 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc:content-transfer-encoding; bh=eh9xvqGv160fKMlLUwlPlM7qfEP0isz5KYXYGxgyu8c=; b=wACfxTUlczOZsG7CCDJ5ZRZYorQx6HmmA6N/te+cyrzutNJJ4HsJmfbIIB4BL1vyNd iLK5kQ80Gm7RqGznez8vHvqZgraxshgcUHXJug7YhOAGeKXFw8SNnZdchqrPs0MhCqnD ihIiy2Up0ULk9ZRK5L6nnec60KSVt5Hi2nmzCl2yNIhA2uVg7nM8LJc7HH9HMc4SyXx3 LPDARTMnGfjmSrVIriqZV/RwYk0XPcKxPLm15jAAQ7734HLgbIeroaqpv/XS0odRLhUD mf7u4RWQuWsGBn4WH7I4hJLhHHtGn0AalxhM3Lq1YQAoi9lJHxWvbqyHpt4EEHlNMTCl irFQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc:content-transfer-encoding; bh=eh9xvqGv160fKMlLUwlPlM7qfEP0isz5KYXYGxgyu8c=; b=oeVT7x0My+0UZ2vrum8lTApa/UBhxH6o6HHCrhCSQMrLLO4s1xt7mJ7GsHIcOkrMxy 2IjOBSQnp70+VKCZyaFfD5nbgdy+43Gu6UCO7/ZXYKa7oF3QMgc3o5dLWhrRKeN5nUhW +OagvKwFkGDahPjM5kWh4hnr/rEpbJaFejd+pPO9uME7NAIH/cZ2LlGxPV4A6we6/85b 8TEWnhzYWYL0djAI3IlVmOLtjWQz7DoalDIx6M5Q2SuIl0kUYUlLRCfl8Wt3XaygbeVp UaROkjvlUk6z2NtypgjfeKt3TONhyOx9syeMLdQsPAfD+yXTX5qClcSXXBIVyS/YL/lC VI5w== X-Gm-Message-State: APjAAAWqksObmOp+xRVCTFXx5Gu4KFL6jOT0a09pATuaCRcsPnBFQLlH iM4ucEvkw4rGYbjdr325WRhURzXY1xgq22jpOcTMTg== X-Google-Smtp-Source: APXvYqyLyH4WzoktiVZ8ekTSUBK5nOb267oJQ6YQGWI6LORU5SMake6vRYUt6QE5llPM+YQQzs+xKVAufpDOlOiVvrQ= X-Received: by 2002:a05:6830:13d3:: with SMTP id e19mr12398993otq.135.1575657544333; Fri, 06 Dec 2019 10:39:04 -0800 (PST) MIME-Version: 1.0 References: <20191206162303.30338-1-philmd@redhat.com> In-Reply-To: <20191206162303.30338-1-philmd@redhat.com> From: Peter Maydell Date: Fri, 6 Dec 2019 18:38:53 +0000 Message-ID: Subject: Re: [PATCH v2] hw/arm/sbsa-ref: Simplify by moving the gic in the machine state To: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= Cc: QEMU Developers , qemu-arm , Leif Lindholm , Radoslaw Biernacki Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::341 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 06 Dec 2019 18:39:16 -0000 On Fri, 6 Dec 2019 at 16:23, Philippe Mathieu-Daud=C3=A9 wrote: > > Make the gic a field in the machine state, and instead of filling > an array of qemu_irq and passing it around, directly call > qdev_get_gpio_in() on the gic field. > > Signed-off-by: Philippe Mathieu-Daud=C3=A9 Applied to target-arm.next, thanks. -- PMM From MAILER-DAEMON Fri Dec 06 15:02:21 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1idJnw-0005sk-Te for mharc-qemu-arm@gnu.org; Fri, 06 Dec 2019 15:02:20 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:49410) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1idJnr-0005mc-8h for qemu-arm@nongnu.org; Fri, 06 Dec 2019 15:02:16 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1idJnp-0003o9-Vp for qemu-arm@nongnu.org; Fri, 06 Dec 2019 15:02:15 -0500 Received: from mail-il1-x144.google.com ([2607:f8b0:4864:20::144]:44508) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1idJnk-0003fO-1T; Fri, 06 Dec 2019 15:02:08 -0500 Received: by mail-il1-x144.google.com with SMTP id z12so7259646iln.11; Fri, 06 Dec 2019 12:02:01 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=ciqFUU5MY4QIDiBl5osr7K35WjCbFJa6f4x6hN3vQ3g=; b=PjLKwI+xL3+9lLuoQfj6Q4CB+J4ufMl4/gyXeyNsGYIn0H9lH4cjIuqupR5J8Bt/r4 j3CUjzZYd3hY/DnEIkLGtxcPvWAL0fh6cLOgaoN+OY0gfeRGM6mZ7XDyAaiTJw9o7AUR Y0tMUgZBK3bDEWpEXH4/HZon30FnRDaSWal33AtuUgaMFrMOEsZz3NGYOFZDwQ+Ro9IJ HRQTOHJMIsml3qtIOG3m2nX2XofyvSlu0L1jQrrqoVyrmnf7eD0qm1LE/r0KqxZwFiKO yQpxlOGF6f9YGmSMv626QFAPCyKHxhhirNHq2eMWXdtPYyk9FBw/Qlm6NaU8x6cx08ry MQOA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=ciqFUU5MY4QIDiBl5osr7K35WjCbFJa6f4x6hN3vQ3g=; b=WI9VQKggClc128DZaGOP81ZXPkZEaDHlVswC/NYVoDNP3zOzCXr/BFN9Mxzbch77wI ptQHRCyFmjn1MfxRowN7DRV6YFLD/T6ckMJPJetQcvaBX2HkViQxpeyz2LBRjoSeKkJb cLD3s40wiX/TlQvjaMxli2i1DRCGIGZg+gbmsUZnn6CmhuSU5DDCvDZpz/SVXpLQpGGl fZHtRO7oYSJwPlbB5/V3hmynvrN+aKLEor1weETnF89AKKArX5eZ2y51vAERVGunhC2n 2+S1qi/o9GdxMQEd8/UH4XjgGG90T7sx3gQ+Rg3Icrc/b47Ek1j3G/WWuHeh8zzYpFFN RJLQ== X-Gm-Message-State: APjAAAVSXA40Q0naWTTiY/m4DKi1ig1YaQuD94lqfa12eY7Nqi5W/T6X i5jkA6OdWOVlXWDGSBSwYw2mWu55CiZ7Hmp/v8k= X-Google-Smtp-Source: APXvYqw/CxDSfKyY9oDRb9ZAOgaHYcB/cD2x69cRMa5LU2i7r0PDfXfvngoCytiKqgoTqV1QMkTTd+VJ6RETgUXVIco= X-Received: by 2002:a92:af08:: with SMTP id n8mr15431530ili.217.1575662520840; Fri, 06 Dec 2019 12:02:00 -0800 (PST) MIME-Version: 1.0 References: <20191202210947.3603-1-nieklinnenbank@gmail.com> <20191202210947.3603-7-nieklinnenbank@gmail.com> In-Reply-To: From: Niek Linnenbank Date: Fri, 6 Dec 2019 21:01:49 +0100 Message-ID: Subject: Re: [PATCH 06/10] arm/arm-powerctl: set NSACR.{CP11, CP10} bits in arm_set_cpu_on() To: Peter Maydell Cc: QEMU Developers , qemu-arm , Beniamino Galvani Content-Type: multipart/alternative; boundary="000000000000d736f805990e8492" X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::144 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 06 Dec 2019 20:02:17 -0000 --000000000000d736f805990e8492 Content-Type: text/plain; charset="UTF-8" Hey Peter, On Fri, Dec 6, 2019 at 3:25 PM Peter Maydell wrote: > On Mon, 2 Dec 2019 at 21:10, Niek Linnenbank > wrote: > > > > This change ensures that the FPU can be accessed in Non-Secure mode > > when the CPU core is reset using the arm_set_cpu_on() function call. > > The NSACR.{CP11,CP10} bits define the exception level required to > > access the FPU in Non-Secure mode. Without these bits set, the CPU > > will give an undefined exception trap on the first FPU access for the > > secondary cores under Linux. > > > > Fixes: fc1120a7f5 > > Signed-off-by: Niek Linnenbank > > --- > > Oops, another place where we failed to realise the ramifications > of making NSACR actually do something. > > Since this is a bugfix I'm going to fish it out of this patchset > and apply it to target-arm.next with a cc: stable. > > Thanks for the catch! > Sure, I'm happy to help. Note that I only tested this fix with the Allwinner H3 SoC patches that I'm working on. OK, I'll keep an eye out for it. Once it is solved in master, I'll remove this patch from the patch series. Regards, Niek > > -- PMM > -- Niek Linnenbank --000000000000d736f805990e8492 Content-Type: text/html; charset="UTF-8" Content-Transfer-Encoding: quoted-printable
Hey Peter,

On Fri, Dec 6, 2019 at 3:25 PM Peter Ma= ydell <peter.maydell@linaro.= org> wrote:
On Mon, 2 Dec 2019 at 21:10, Niek Linnenbank <nieklinnenbank@gmail.com> wro= te:
>
> This change ensures that the FPU can be accessed in Non-Secure mode > when the CPU core is reset using the arm_set_cpu_on() function call. > The NSACR.{CP11,CP10} bits define the exception level required to
> access the FPU in Non-Secure mode. Without these bits set, the CPU
> will give an undefined exception trap on the first FPU access for the<= br> > secondary cores under Linux.
>
> Fixes: fc1120a7f5
> Signed-off-by: Niek Linnenbank <nieklinnenbank@gmail.com>
> ---

Oops, another place where we failed to realise the ramifications
of making NSACR actually do something.

Since this is a bugfix I'm going to fish it out of this patchset
and apply it to target-arm.next with a cc: stable.

Thanks for the catch!
=C2=A0
Sure, I= 9;m happy to help. Note that I only tested this fix with
the Allw= inner H3 SoC patches that I'm working on.

OK, I'll keep an eye out for it. Once it is solved in master, I'= ll remove this patch from the patch series.
=C2=A0
= Regards,
Niek

-- PMM


--
Niek Linnenbank

--000000000000d736f805990e8492-- From MAILER-DAEMON Fri Dec 06 15:20:51 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1idK5r-0005W2-0i for mharc-qemu-arm@gnu.org; Fri, 06 Dec 2019 15:20:51 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:42970) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1idK5n-0005Vs-Ko for qemu-arm@nongnu.org; Fri, 06 Dec 2019 15:20:48 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1idK5l-0002V4-Bn for qemu-arm@nongnu.org; Fri, 06 Dec 2019 15:20:47 -0500 Received: from mail-io1-xd43.google.com ([2607:f8b0:4864:20::d43]:33990) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1idK5l-0002T4-4w; Fri, 06 Dec 2019 15:20:45 -0500 Received: by mail-io1-xd43.google.com with SMTP id z193so8632636iof.1; Fri, 06 Dec 2019 12:20:45 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=VPrqLSDF6cbyZzlOcEit277juDu8n1Mg9FZXYf0DkF8=; b=biYg6He5J7jIk7sNgqpqyTA6deV7GDILYQE8zyKyRPVkR9r+Cq0+bIz2ji3lcUPATg wXmNwlEgPjVJY1sOU4Mu5g3gt/0nlAAqYQZbp63N0GWTnG3PkegYYPRlslUjW08etW43 gZk736CpE1P2nmwp7H4tb43tU3ExA4ZYKK8xfgU1hrc8wNFrvXiuZtuEOsvswMR7Dv8Z PQABx4Q7r9Ro8JElzczbgvCU3x0OKwNePjG8UPjGGLp8LXGpqLFWcojGQ/raK2WXffAu 0GMGxFW3dqJvKGRrjP/kQdGDDypcOsBewFIqZN5dedBREXKa2MqsekjmfAdh6adS896Z F30g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=VPrqLSDF6cbyZzlOcEit277juDu8n1Mg9FZXYf0DkF8=; b=uoIFLYLAFsQ1fUC6L2JGFO4bKTLR7r5B+Szmw9geq7EOJbbN5pZeRi3891vuS98sy8 B0IFa/i3TkcCOuCOMNfDUg6bGUApGtZJpXv7Jwz3h94X3Oh217mOd+xExFLByTOIm8lr hAB8gIs+1S3i0Q7Zo6kiRIB86lrRWa4TK5sGRpxbqsXmKbQgf0kl/r39UvxRzo8CrCZR bY1iQgPnub2ldbVK+J9td3VChv4COjZMG+uxplllSGXzZWhtg4YG9/9PG86yn5+2lkoX YOMH/2E+HI1LaBxUjaJLKOQ4Zl8nPnuTxNyR313O1Mqm+Ld0MGZWAmNMEsPriGBwAfTm Erbg== X-Gm-Message-State: APjAAAWRKZqY0C7x7J07kzSgfsUm7Bpwj6D664q0aMS+oTCNOol64QG4 tD71Nokwqxa+8A6WY0GjGoYZmdcKXifQ8j1IKHg= X-Google-Smtp-Source: APXvYqzy1wc5GhvRQa4kq+0rg0yFrpFJiSpnEgtxgHU7niY8F/hmb17DweDzkPhQKp234OIyx2IMHC6je4jahUQki6U= X-Received: by 2002:a5d:8f17:: with SMTP id f23mr12298036iof.265.1575663644369; Fri, 06 Dec 2019 12:20:44 -0800 (PST) MIME-Version: 1.0 References: <20191202210947.3603-1-nieklinnenbank@gmail.com> <20191202210947.3603-9-nieklinnenbank@gmail.com> <41ab9f5a-3318-b412-44e8-f8571a64da64@redhat.com> In-Reply-To: <41ab9f5a-3318-b412-44e8-f8571a64da64@redhat.com> From: Niek Linnenbank Date: Fri, 6 Dec 2019 21:20:33 +0100 Message-ID: Subject: Re: [PATCH 08/10] arm: allwinner-h3: add Security Identifier device To: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= Cc: Peter Maydell , Beniamino Galvani , qemu-arm , QEMU Developers Content-Type: multipart/alternative; boundary="000000000000ceea9005990ec7cb" X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::d43 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 06 Dec 2019 20:20:49 -0000 --000000000000ceea9005990ec7cb Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Hey Peter, Philippe, On Fri, Dec 6, 2019 at 5:35 PM Philippe Mathieu-Daud=C3=A9 wrote: > On 12/6/19 3:27 PM, Peter Maydell wrote: > > On Mon, 2 Dec 2019 at 21:10, Niek Linnenbank > wrote: > >> > >> The Security Identifier device in Allwinner H3 System on Chip > >> gives applications a per-board unique identifier. This commit > >> adds support for the Allwinner H3 Security Identifier using > >> randomized data as input. > > > > If this is a fixed value in hardware, I'm not sure that > > having the QEMU model pick a random value is the best > > choice. If we just set it to a fixed value in QEMU, is > > that going to cause problems? > > > > (Generally it's nice for QEMU to be deterministic, so it > > behaves the same way every time you run it. Also if it's > > always the same we don't need to bother migrating the > > ID value.) > > Agreed. Since the identifier is 128-bit, I'd use DEFINE_PROP_UUID() or, > to be even safer, DEFINE_PROP_UUID_NODEFAULT(). > See how the ipmi-bmc-sim device checks its guid field and fails if unset. > Thank you both for clarifying this. OK, I'll update this patch such that the identifier is fixed, using the functions Philippe suggested. The reason I originally chose to make it randomized is that U-Boot mainline reads out the SID data in order to create a MAC address for the ethernet device. So when a user runs multiple QEMU machines inside a virtualized network, they will get the same MACs if the SID isnt unique. However this problem can also be solved very easy with U-Boot itself by just overriding the ethaddr environment variable. For your interest, in the U-Boot source you can see this behaviour in the file arch/arm/mach-sunxi/cpu_info.c:139 in sunxi_get_sid(), sun8i_efuse_read() where it reads the SID and in board/sunxi/board.c:782 in setup_environment() where it uses the SID to create the MAC address. Regards, Niek --=20 Niek Linnenbank --000000000000ceea9005990ec7cb Content-Type: text/html; charset="UTF-8" Content-Transfer-Encoding: quoted-printable
Hey Peter, Philippe,

On Fri, Dec 6, 2019 at 5:35 P= M Philippe Mathieu-Daud=C3=A9 <phil= md@redhat.com> wrote:
On 12/6/19 3:27 PM, Peter Maydell wrote:
> On Mon, 2 Dec 2019 at 21:10, Niek Linnenbank <nieklinnenbank@gmail.com> w= rote:
>>
>> The Security Identifier device in Allwinner H3 System on Chip
>> gives applications a per-board unique identifier. This commit
>> adds support for the Allwinner H3 Security Identifier using
>> randomized data as input.
>
> If this is a fixed value in hardware, I'm not sure that
> having the QEMU model pick a random value is the best
> choice. If we just set it to a fixed value in QEMU, is
> that going to cause problems?
>
> (Generally it's nice for QEMU to be deterministic, so it
> behaves the same way every time you run it. Also if it's
> always the same we don't need to bother migrating the
> ID value.)

Agreed. Since the identifier is 128-bit, I'd use DEFINE_PROP_UUID() or,=
to be even safer, DEFINE_PROP_UUID_NODEFAULT().
See how the ipmi-bmc-sim device checks its guid field and fails if unset.

Thank you both for clarifying this. OK, = I'll update this patch such that the identifier is fixed,
usi= ng the functions Philippe suggested.

The reason I = originally chose to make it randomized is that U-Boot mainline reads out th= e
SID data in order to create a MAC address for the ethernet devi= ce. So when a user runs multiple
QEMU machines inside a virtualiz= ed network, they will get the same MACs if the SID isnt unique.
H= owever this problem can also be solved very easy with U-Boot itself by just= overriding the ethaddr environment variable.

= For your interest, in the U-Boot source you can see this behaviour in the f= ile
arch/arm/mach-sunxi/cpu_info.c:139 in sunxi_get_sid(), sun8i_= efuse_read() where it reads the SID
and in board/sunxi/board.c:78= 2 in setup_environment() where it uses the SID to create the MAC address.

Regards,
Niek

-- <= br>
Niek Li= nnenbank

--000000000000ceea9005990ec7cb-- From MAILER-DAEMON Fri Dec 06 17:16:17 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1idLtZ-0002n1-CA for mharc-qemu-arm@gnu.org; Fri, 06 Dec 2019 17:16:17 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:60078) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1idLtU-0002k3-EO for qemu-arm@nongnu.org; Fri, 06 Dec 2019 17:16:15 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1idLtR-0007x2-22 for qemu-arm@nongnu.org; Fri, 06 Dec 2019 17:16:12 -0500 Received: from mail-io1-xd43.google.com ([2607:f8b0:4864:20::d43]:47042) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1idLtJ-0007aw-Ur; Fri, 06 Dec 2019 17:16:02 -0500 Received: by mail-io1-xd43.google.com with SMTP id i11so8843635iol.13; Fri, 06 Dec 2019 14:16:00 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=s/7OdeqmZUFG/ihDfSirzk0p9NzkShThT+s7z8P7mpE=; b=MlCjZLTacz8jXTW90H/+4HvcVgZkXw04W9zw9uUByxgOGK+3exgno7jzijCKP3NK56 7UpxMdDJ09Ur55szOv10QoGIUi6dD8xhzV1xbl38IXxxGsvnJvisHklgeAcs7HhdJpLW 3OGT2S53/CbXSlaBXuhQ0No+imlQDkufb56PLvD9IFPbhsyfmQyUAOH7BHPIAqViZyMS QBvxhZu3f8N6PTw7q559BMthz3XxYhqYs6yYScEb1wfnpvxv+T5gvpMQJciTiOQG2EnE hK3RNr8mvBZHtgDFCnIQu+2eaNhfeZKHbpQTd4HxULruYlu9xPcpyPKA/ji1ZzVg/Ieq URzw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=s/7OdeqmZUFG/ihDfSirzk0p9NzkShThT+s7z8P7mpE=; b=e/4NQKV0KkIMWVI0tQHKSxtZJlaeET3rMm4IWfl5mSWkJ2AVkb7m21EX2/Xu+XZQlK v4PDs6sOCK6ezC42DaFWZLsIVxGpBrC7tALJo2F9ZMMS8RYy1ZDV4/8dKdrAvdzlG6ZN 1OmK+wR/ouAVRhUMjsrD83BO9ILKvF4QklJ+hAznAhxCB560kDG+yPwsNhn5iv4XmPtk ZKGqNKyo0n3NMltoUzBvkqjJKG571fBo6g2a2YpiBlBcOTMHCc/bEwFAzOU5c61uB1nM CoKNc3ufT7anzDkkEn85GXbG+mwkYbKc6B0wlo9a+hzYhZ+1yyeOSyvhlPBUkaPAh5Ck bStA== X-Gm-Message-State: APjAAAUNm125rX0wg9Uf7WjUKKKPrQ6VNdcGehGMP4o/FkNDozZftTeM 8yAdF7DzkgfNaSI6MW1yKD2XRkrPEv4TqfukAuM= X-Google-Smtp-Source: APXvYqzbBWp8fDiQEJTOkzCVQ0jkS3tRT7AUMRPZAKXZFTEn/ShATKtmPzDo/s4/0VXh31m3J5KCTyCB9iawfw/votQ= X-Received: by 2002:a6b:d912:: with SMTP id r18mr12132192ioc.306.1575670559704; Fri, 06 Dec 2019 14:15:59 -0800 (PST) MIME-Version: 1.0 References: <20191202210947.3603-1-nieklinnenbank@gmail.com> <20191202210947.3603-3-nieklinnenbank@gmail.com> In-Reply-To: From: Niek Linnenbank Date: Fri, 6 Dec 2019 23:15:48 +0100 Message-ID: Subject: Re: [PATCH 02/10] hw: arm: add Xunlong Orange Pi PC machine To: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= Cc: QEMU Developers , Beniamino Galvani , Peter Maydell , qemu-arm Content-Type: multipart/alternative; boundary="000000000000fe8a3705991063e9" X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::d43 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 06 Dec 2019 22:16:16 -0000 --000000000000fe8a3705991063e9 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Hi Philippe, On Fri, Dec 6, 2019 at 6:41 AM Philippe Mathieu-Daud=C3=A9 wrote: > On 12/5/19 11:15 PM, Niek Linnenbank wrote: > > Hello Philippe, > > > > On Tue, Dec 3, 2019 at 10:18 AM Philippe Mathieu-Daud=C3=A9 > > > wrote: > > > > On 12/2/19 10:09 PM, Niek Linnenbank wrote: > > > The Xunlong Orange Pi PC is an Allwinner H3 System on Chip > > > based embedded computer with mainline support in both U-Boot > > > and Linux. The board comes with a Quad Core Cortex A7 @ 1.3GHz, > > > 512MB RAM, 100Mbit ethernet, USB, SD/MMC, USB, HDMI and > > > various other I/O. This commit add support for the Xunlong > > > Orange Pi PC machine. > > > > > > Signed-off-by: Niek Linnenbank > > > > > --- > > > MAINTAINERS | 1 + > > > hw/arm/Makefile.objs | 2 +- > > > hw/arm/orangepi.c | 90 > > ++++++++++++++++++++++++++++++++++++++++++++ > > > 3 files changed, 92 insertions(+), 1 deletion(-) > > > create mode 100644 hw/arm/orangepi.c > > > > > > diff --git a/MAINTAINERS b/MAINTAINERS > > > index 29c9936037..42c913d6cb 100644 > > > --- a/MAINTAINERS > > > +++ b/MAINTAINERS > > > @@ -485,6 +485,7 @@ L: qemu-arm@nongnu.org > > > > > S: Maintained > > > F: hw/*/allwinner-h3* > > > F: include/hw/*/allwinner-h3* > > > +F: hw/arm/orangepi.c > > > > > > ARM PrimeCell and CMSDK devices > > > M: Peter Maydell > > > > > diff --git a/hw/arm/Makefile.objs b/hw/arm/Makefile.objs > > > index 956e496052..8d5ea453d5 100644 > > > --- a/hw/arm/Makefile.objs > > > +++ b/hw/arm/Makefile.objs > > > @@ -34,7 +34,7 @@ obj-$(CONFIG_DIGIC) +=3D digic.o > > > obj-$(CONFIG_OMAP) +=3D omap1.o omap2.o > > > obj-$(CONFIG_STRONGARM) +=3D strongarm.o > > > obj-$(CONFIG_ALLWINNER_A10) +=3D allwinner-a10.o cubieboard.o > > > -obj-$(CONFIG_ALLWINNER_H3) +=3D allwinner-h3.o > > > +obj-$(CONFIG_ALLWINNER_H3) +=3D allwinner-h3.o orangepi.o > > > obj-$(CONFIG_RASPI) +=3D bcm2835_peripherals.o bcm2836.o raspi= .o > > > obj-$(CONFIG_STM32F205_SOC) +=3D stm32f205_soc.o > > > obj-$(CONFIG_XLNX_ZYNQMP_ARM) +=3D xlnx-zynqmp.o xlnx-zcu102.o > > > diff --git a/hw/arm/orangepi.c b/hw/arm/orangepi.c > > > new file mode 100644 > > > index 0000000000..5ef2735f81 > > > --- /dev/null > > > +++ b/hw/arm/orangepi.c > > > @@ -0,0 +1,90 @@ > > > +/* > > > + * Orange Pi emulation > > > + * > > > + * Copyright (C) 2019 Niek Linnenbank > > > > > + * > > > + * This program is free software: you can redistribute it and/o= r > > modify > > > + * it under the terms of the GNU General Public License as > > published by > > > + * the Free Software Foundation, either version 2 of the > License, or > > > + * (at your option) any later version. > > > + * > > > + * This program is distributed in the hope that it will be > useful, > > > + * but WITHOUT ANY WARRANTY; without even the implied warranty = of > > > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See th= e > > > + * GNU General Public License for more details. > > > + * > > > + * You should have received a copy of the GNU General Public > License > > > + * along with this program. If not, see > > . > > > + */ > > > + > > > +#include "qemu/osdep.h" > > > +#include "exec/address-spaces.h" > > > +#include "qapi/error.h" > > > +#include "cpu.h" > > > +#include "hw/sysbus.h" > > > +#include "hw/boards.h" > > > +#include "hw/qdev-properties.h" > > > +#include "hw/arm/allwinner-h3.h" > > > + > > > +static struct arm_boot_info orangepi_binfo =3D { > > > + .loader_start =3D AW_H3_SDRAM_BASE, > > > + .board_id =3D -1, > > > +}; > > > + > > > +typedef struct OrangePiState { > > > + AwH3State *h3; > > > + MemoryRegion sdram; > > > +} OrangePiState; > > > + > > > +static void orangepi_init(MachineState *machine) > > > +{ > > > + OrangePiState *s =3D g_new(OrangePiState, 1); > > > + Error *err =3D NULL; > > > + > > > > Here I'd add: > > > > if (strcmp(machine->cpu_type, > > ARM_CPU_TYPE_NAME("cortex-a7")) !=3D 0) { > > error_report("This board can only be used with cortex-a= 7 > > CPU"); > > exit(1); > > } > > > > Done! > > > > > + s->h3 =3D AW_H3(object_new(TYPE_AW_H3)); > > > + > > > + /* Setup timer properties */ > > > + object_property_set_int(OBJECT(&s->h3->timer), 32768, > > "clk0-freq", &err); > > > + if (err !=3D NULL) { > > > + error_reportf_err(err, "Couldn't set clk0 frequency: ")= ; > > > + exit(1); > > > + } > > > + > > > + object_property_set_int(OBJECT(&s->h3->timer), 24000000, > > "clk1-freq", > > > + &err); > > > + if (err !=3D NULL) { > > > + error_reportf_err(err, "Couldn't set clk1 frequency: ")= ; > > > + exit(1); > > > + } > > > + > > > + /* Mark H3 object realized */ > > > + object_property_set_bool(OBJECT(s->h3), true, "realized", > &err); > > > > I'm not sure if that's correct but I'd simply use &error_abort here= . > > > > Done, I applied it to all the functions and removed the err variable. > > > > > + if (err !=3D NULL) { > > > + error_reportf_err(err, "Couldn't realize Allwinner H3: > "); > > > + exit(1); > > > + } > > > + > > > + /* RAM */ > > > + memory_region_allocate_system_memory(&s->sdram, NULL, > > "orangepi.ram", > > > + machine->ram_size); > > > > I'd only allow machine->ram_size =3D=3D 1 * GiB here, since the onb= oard > > DRAM > > is not upgradable. > > > > > > Agree, we should add something for that. Would it be acceptable if we > > make the 1GB an upper limit? > > I see that the Raspberry Pi is doing that too in hw/arm/raspi.c, like s= o: > > > > if (machine->ram_size > 1 * GiB) { > > error_report("Requested ram size is too large for this machine= : > " > > "maximum is 1GB"); > > exit(1); > > } > > > > I think it would be helpful to allow the flexibility to the user of > > reducing the RAM to less than 1GB, > > in case resources of the host OS are limited. What do you think? > > Sure, good idea. > > FIY (in case you add more models) we recently noticed there is a problem > when using 2GiB default on 32-bit hosts, so the workaround is to use <=3D > 1GiB default. > > > > + memory_region_add_subregion(get_system_memory(), > > AW_H3_SDRAM_BASE, > > > + &s->sdram); > > > + > > > + /* Load target kernel */ > > > + orangepi_binfo.ram_size =3D machine->ram_size; > > > + orangepi_binfo.nb_cpus =3D AW_H3_NUM_CPUS; > > > + arm_load_kernel(ARM_CPU(first_cpu), machine, > &orangepi_binfo); > > > +} > > > + > > > +static void orangepi_machine_init(MachineClass *mc) > > > +{ > > > + mc->desc =3D "Orange Pi PC"; > > > + mc->init =3D orangepi_init; > > > + mc->units_per_default_bus =3D 1; > > > + mc->min_cpus =3D AW_H3_NUM_CPUS; > > > + mc->max_cpus =3D AW_H3_NUM_CPUS; > > > + mc->default_cpus =3D AW_H3_NUM_CPUS; > > > > mc->default_cpu_type =3D ARM_CPU_TYPE_NAME("cortex-a7"); > > > > > + mc->ignore_memory_transaction_failures =3D true; > > > > You should not use this flag in new design. See the documentation i= n > > include/hw/boards.h: > > > > * @ignore_memory_transaction_failures: > > * [...] New board models > > * should instead use "unimplemented-device" for all memory > > ranges where > > * the guest will attempt to probe for a device that QEMU > doesn't > > * implement and a stub device is required. > > > > You already use the "unimplemented-device". > > > > Thanks, I'm working on this now. I think that at least I'll need to add > > all of the devices mentioned in the 4.1 Memory Mapping chapter of the > > datasheet > > as an unimplemented device. Previously I only added some that I thought > > were relevant. > > > > I added all the missing devices as unimplemented and removed the > > ignore_memory_transaction_failures flag > > I was going to say, "instead of adding *all* the devices regions you can > add the likely bus decoding regions", probably: > > 0x01c0.0000 128KiB AMBA AXI > 0x01c2.0000 64KiB AMBA APB > > But too late. > Hehe its okey, I can change it to whichever is preferable: the minimum set with unimplemented device entries to get a working linux kernel / u-boot or just cover the full memory space from the datasheet. My initial thought was that if we only provide the minimum set, and the linux kernel later adds a new driver for a device which is not marked unimplemented, it will trigger the data abort and potentially resulting in a non-booting kernel. But I'm not sure what is normally done here. I do see other board files using the create_unimplemented_device() function, but I dont know if they are covering the whole memory space or not. Any thoughts? :-) > > > from the machine. Now it seems Linux gets a data abort while probing th= e > > uart1 serial device at 0x01c28400, > > Did you add the UART1 as UNIMP or 16550? > > I discovered what goes wrong here. See this kernel oops message: [ 1.084985] [f08600f8] *pgd=3D6f00a811, *pte=3D01c28653, *ppte=3D01c2845= 3 [ 1.085564] Internal error: : 8 [#1] SMP ARM [ 1.085698] Modules linked in: [ 1.085940] CPU: 0 PID: 1 Comm: swapper/0 Not tainted 5.4.0-11747-g2f13437b8917 #4 [ 1.085968] Hardware name: Allwinner sun8i Family [ 1.086447] PC is at dw8250_setup_port+0x10/0x10c [ 1.086478] LR is at dw8250_probe+0x500/0x56c It tries to access the UART0 at base address 0x01c28400, which I did provide. The strange thing is that is accesses offset 0xf8, thus address 0x01c284f8. The datasheet does not mention this register but if we provide the 1KiB (0x400) I/O space it should at least read as zero and writes ignored. Unfortunately the emulated serial driver only maps a small portion until 0x1f: (qemu) info mtree ... 0000000001c28000-0000000001c2801f (prio 0, i/o): serial 0000000001c28400-0000000001c2841f (prio 0, i/o): serial 0000000001c28800-0000000001c2881f (prio 0, i/o): serial Apparently, the register that the mainline linux kernel is using is DesignWare specific: drivers/tty/serial/8250/8250_dwlib.c:13: /* Offsets for the DesignWare specific registers */ #define DW_UART_DLF<--->0xc0 /* Divisor Latch Fraction Register */ #define DW_UART_CPR<--->0xf4 /* Component Parameter Register */ #define DW_UART_UCV<--->0xf8 /* UART Component Version */ I tried to find a way to increase the memory mapped size of the serial device I created with serial_mm_init(), but I don't think its possible with that interface. I did manage to get it working by overlaying the UART0 with another unimplemented device that does have an I/O size of 0x400, but I guess that is probably not the solution we are looking for? I wonder, did any of the other SoC / boards have this problem when removing mc->ignore_memory_transaction_failures? Regards, Niek > so I'll need to debug it further. I'll post back when I have more results= . > > > > Regards, > > Niek > > > > > +} > > > + > > > +DEFINE_MACHINE("orangepi", orangepi_machine_init) > > > > Can you name it 'orangepi-pc'? So we can add other orangepi models. > > > > Thanks, > > > > Phil. > > > > > > > > -- > > Niek Linnenbank > > > > --=20 Niek Linnenbank --000000000000fe8a3705991063e9 Content-Type: text/html; charset="UTF-8" Content-Transfer-Encoding: quoted-printable
Hi Philippe,

On Fri, Dec 6, 2019 = at 6:41 AM Philippe Mathieu-Daud=C3=A9 <philmd@redhat.com> wrote:
On 12/5/19 11:15 PM, Niek Linnenbank wrote:
> Hello Philippe,
>
> On Tue, Dec 3, 2019 at 10:18 AM Philippe Mathieu-Daud=C3=A9
> <philmd@redh= at.com <mailto:philmd@redhat.com>> wrote:
>
>=C2=A0 =C2=A0 =C2=A0On 12/2/19 10:09 PM, Niek Linnenbank wrote:
>=C2=A0 =C2=A0 =C2=A0 > The Xunlong Orange Pi PC is an Allwinner H3 S= ystem on Chip
>=C2=A0 =C2=A0 =C2=A0 > based embedded computer with mainline support= in both U-Boot
>=C2=A0 =C2=A0 =C2=A0 > and Linux. The board comes with a Quad Core C= ortex A7 @ 1.3GHz,
>=C2=A0 =C2=A0 =C2=A0 > 512MB RAM, 100Mbit ethernet, USB, SD/MMC, USB= , HDMI and
>=C2=A0 =C2=A0 =C2=A0 > various other I/O. This commit add support fo= r the Xunlong
>=C2=A0 =C2=A0 =C2=A0 > Orange Pi PC machine.
>=C2=A0 =C2=A0 =C2=A0 >
>=C2=A0 =C2=A0 =C2=A0 > Signed-off-by: Niek Linnenbank <nieklinnenbank@gmail.co= m
>=C2=A0 =C2=A0 =C2=A0<mailto:nieklinnenbank@gmail.com>>
>=C2=A0 =C2=A0 =C2=A0 > ---
>=C2=A0 =C2=A0 =C2=A0 >=C2=A0 =C2=A0MAINTAINERS=C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 |=C2=A0 1 +
>=C2=A0 =C2=A0 =C2=A0 >=C2=A0 =C2=A0hw/arm/Makefile.objs |=C2=A0 2 +-=
>=C2=A0 =C2=A0 =C2=A0 >=C2=A0 =C2=A0hw/arm/orangepi.c=C2=A0 =C2=A0 | = 90
>=C2=A0 =C2=A0 =C2=A0++++++++++++++++++++++++++++++++++++++++++++
>=C2=A0 =C2=A0 =C2=A0 >=C2=A0 =C2=A03 files changed, 92 insertions(+)= , 1 deletion(-)
>=C2=A0 =C2=A0 =C2=A0 >=C2=A0 =C2=A0create mode 100644 hw/arm/orangep= i.c
>=C2=A0 =C2=A0 =C2=A0 >
>=C2=A0 =C2=A0 =C2=A0 > diff --git a/MAINTAINERS b/MAINTAINERS
>=C2=A0 =C2=A0 =C2=A0 > index 29c9936037..42c913d6cb 100644
>=C2=A0 =C2=A0 =C2=A0 > --- a/MAINTAINERS
>=C2=A0 =C2=A0 =C2=A0 > +++ b/MAINTAINERS
>=C2=A0 =C2=A0 =C2=A0 > @@ -485,6 +485,7 @@ L: qemu-arm@nongnu.org
>=C2=A0 =C2=A0 =C2=A0<mailto:qemu-arm@nongnu.org>
>=C2=A0 =C2=A0 =C2=A0 >=C2=A0 =C2=A0S: Maintained
>=C2=A0 =C2=A0 =C2=A0 >=C2=A0 =C2=A0F: hw/*/allwinner-h3*
>=C2=A0 =C2=A0 =C2=A0 >=C2=A0 =C2=A0F: include/hw/*/allwinner-h3*
>=C2=A0 =C2=A0 =C2=A0 > +F: hw/arm/orangepi.c
>=C2=A0 =C2=A0 =C2=A0 >
>=C2=A0 =C2=A0 =C2=A0 >=C2=A0 =C2=A0ARM PrimeCell and CMSDK devices >=C2=A0 =C2=A0 =C2=A0 >=C2=A0 =C2=A0M: Peter Maydell <peter.maydell@linaro.org<= /a>
>=C2=A0 =C2=A0 =C2=A0<mailto:
peter.maydell@linaro.org>>
>=C2=A0 =C2=A0 =C2=A0 > diff --git a/hw/arm/Makefile.objs b/hw/arm/Ma= kefile.objs
>=C2=A0 =C2=A0 =C2=A0 > index 956e496052..8d5ea453d5 100644
>=C2=A0 =C2=A0 =C2=A0 > --- a/hw/arm/Makefile.objs
>=C2=A0 =C2=A0 =C2=A0 > +++ b/hw/arm/Makefile.objs
>=C2=A0 =C2=A0 =C2=A0 > @@ -34,7 +34,7 @@ obj-$(CONFIG_DIGIC) +=3D di= gic.o
>=C2=A0 =C2=A0 =C2=A0 >=C2=A0 =C2=A0obj-$(CONFIG_OMAP) +=3D omap1.o o= map2.o
>=C2=A0 =C2=A0 =C2=A0 >=C2=A0 =C2=A0obj-$(CONFIG_STRONGARM) +=3D stro= ngarm.o
>=C2=A0 =C2=A0 =C2=A0 >=C2=A0 =C2=A0obj-$(CONFIG_ALLWINNER_A10) +=3D = allwinner-a10.o cubieboard.o
>=C2=A0 =C2=A0 =C2=A0 > -obj-$(CONFIG_ALLWINNER_H3) +=3D allwinner-h3= .o
>=C2=A0 =C2=A0 =C2=A0 > +obj-$(CONFIG_ALLWINNER_H3) +=3D allwinner-h3= .o orangepi.o
>=C2=A0 =C2=A0 =C2=A0 >=C2=A0 =C2=A0obj-$(CONFIG_RASPI) +=3D bcm2835_= peripherals.o bcm2836.o raspi.o
>=C2=A0 =C2=A0 =C2=A0 >=C2=A0 =C2=A0obj-$(CONFIG_STM32F205_SOC) +=3D = stm32f205_soc.o
>=C2=A0 =C2=A0 =C2=A0 >=C2=A0 =C2=A0obj-$(CONFIG_XLNX_ZYNQMP_ARM) += =3D xlnx-zynqmp.o xlnx-zcu102.o
>=C2=A0 =C2=A0 =C2=A0 > diff --git a/hw/arm/orangepi.c b/hw/arm/orang= epi.c
>=C2=A0 =C2=A0 =C2=A0 > new file mode 100644
>=C2=A0 =C2=A0 =C2=A0 > index 0000000000..5ef2735f81
>=C2=A0 =C2=A0 =C2=A0 > --- /dev/null
>=C2=A0 =C2=A0 =C2=A0 > +++ b/hw/arm/orangepi.c
>=C2=A0 =C2=A0 =C2=A0 > @@ -0,0 +1,90 @@
>=C2=A0 =C2=A0 =C2=A0 > +/*
>=C2=A0 =C2=A0 =C2=A0 > + * Orange Pi emulation
>=C2=A0 =C2=A0 =C2=A0 > + *
>=C2=A0 =C2=A0 =C2=A0 > + * Copyright (C) 2019 Niek Linnenbank <nieklinnenbank@= gmail.com
>=C2=A0 =C2=A0 =C2=A0<mailto:nieklinnenbank@gmail.com>>
>=C2=A0 =C2=A0 =C2=A0 > + *
>=C2=A0 =C2=A0 =C2=A0 > + * This program is free software: you can re= distribute it and/or
>=C2=A0 =C2=A0 =C2=A0modify
>=C2=A0 =C2=A0 =C2=A0 > + * it under the terms of the GNU General Pub= lic License as
>=C2=A0 =C2=A0 =C2=A0published by
>=C2=A0 =C2=A0 =C2=A0 > + * the Free Software Foundation, either vers= ion 2 of the License, or
>=C2=A0 =C2=A0 =C2=A0 > + * (at your option) any later version.
>=C2=A0 =C2=A0 =C2=A0 > + *
>=C2=A0 =C2=A0 =C2=A0 > + * This program is distributed in the hope t= hat it will be useful,
>=C2=A0 =C2=A0 =C2=A0 > + * but WITHOUT ANY WARRANTY; without even th= e implied warranty of
>=C2=A0 =C2=A0 =C2=A0 > + * MERCHANTABILITY or FITNESS FOR A PARTICUL= AR PURPOSE.=C2=A0 See the
>=C2=A0 =C2=A0 =C2=A0 > + * GNU General Public License for more detai= ls.
>=C2=A0 =C2=A0 =C2=A0 > + *
>=C2=A0 =C2=A0 =C2=A0 > + * You should have received a copy of the GN= U General Public License
>=C2=A0 =C2=A0 =C2=A0 > + * along with this program.=C2=A0 If not, se= e
>=C2=A0 =C2=A0 =C2=A0<http://www.gnu.org/licenses/>.
>=C2=A0 =C2=A0 =C2=A0 > + */
>=C2=A0 =C2=A0 =C2=A0 > +
>=C2=A0 =C2=A0 =C2=A0 > +#include "qemu/osdep.h"
>=C2=A0 =C2=A0 =C2=A0 > +#include "exec/address-spaces.h" >=C2=A0 =C2=A0 =C2=A0 > +#include "qapi/error.h"
>=C2=A0 =C2=A0 =C2=A0 > +#include "cpu.h"
>=C2=A0 =C2=A0 =C2=A0 > +#include "hw/sysbus.h"
>=C2=A0 =C2=A0 =C2=A0 > +#include "hw/boards.h"
>=C2=A0 =C2=A0 =C2=A0 > +#include "hw/qdev-properties.h" >=C2=A0 =C2=A0 =C2=A0 > +#include "hw/arm/allwinner-h3.h" >=C2=A0 =C2=A0 =C2=A0 > +
>=C2=A0 =C2=A0 =C2=A0 > +static struct arm_boot_info orangepi_binfo = =3D {
>=C2=A0 =C2=A0 =C2=A0 > +=C2=A0 =C2=A0 .loader_start =3D AW_H3_SDRAM_= BASE,
>=C2=A0 =C2=A0 =C2=A0 > +=C2=A0 =C2=A0 .board_id =3D -1,
>=C2=A0 =C2=A0 =C2=A0 > +};
>=C2=A0 =C2=A0 =C2=A0 > +
>=C2=A0 =C2=A0 =C2=A0 > +typedef struct OrangePiState {
>=C2=A0 =C2=A0 =C2=A0 > +=C2=A0 =C2=A0 AwH3State *h3;
>=C2=A0 =C2=A0 =C2=A0 > +=C2=A0 =C2=A0 MemoryRegion sdram;
>=C2=A0 =C2=A0 =C2=A0 > +} OrangePiState;
>=C2=A0 =C2=A0 =C2=A0 > +
>=C2=A0 =C2=A0 =C2=A0 > +static void orangepi_init(MachineState *mach= ine)
>=C2=A0 =C2=A0 =C2=A0 > +{
>=C2=A0 =C2=A0 =C2=A0 > +=C2=A0 =C2=A0 OrangePiState *s =3D g_new(Ora= ngePiState, 1);
>=C2=A0 =C2=A0 =C2=A0 > +=C2=A0 =C2=A0 Error *err =3D NULL;
>=C2=A0 =C2=A0 =C2=A0 > +
>
>=C2=A0 =C2=A0 =C2=A0Here I'd add:
>
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0if (strcmp(machine->= cpu_type,
>=C2=A0 =C2=A0 =C2=A0ARM_CPU_TYPE_NAME("cortex-a7")) !=3D 0) {=
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0error_rep= ort("This board can only be used with cortex-a7
>=C2=A0 =C2=A0 =C2=A0CPU");
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0exit(1);<= br> >=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0}
>
> Done!
>
>=C2=A0 =C2=A0 =C2=A0 > +=C2=A0 =C2=A0 s->h3 =3D AW_H3(object_new(= TYPE_AW_H3));
>=C2=A0 =C2=A0 =C2=A0 > +
>=C2=A0 =C2=A0 =C2=A0 > +=C2=A0 =C2=A0 /* Setup timer properties */ >=C2=A0 =C2=A0 =C2=A0 > +=C2=A0 =C2=A0 object_property_set_int(OBJECT= (&s->h3->timer), 32768,
>=C2=A0 =C2=A0 =C2=A0"clk0-freq", &err);
>=C2=A0 =C2=A0 =C2=A0 > +=C2=A0 =C2=A0 if (err !=3D NULL) {
>=C2=A0 =C2=A0 =C2=A0 > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 error_reportf_er= r(err, "Couldn't set clk0 frequency: ");
>=C2=A0 =C2=A0 =C2=A0 > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 exit(1);
>=C2=A0 =C2=A0 =C2=A0 > +=C2=A0 =C2=A0 }
>=C2=A0 =C2=A0 =C2=A0 > +
>=C2=A0 =C2=A0 =C2=A0 > +=C2=A0 =C2=A0 object_property_set_int(OBJECT= (&s->h3->timer), 24000000,
>=C2=A0 =C2=A0 =C2=A0"clk1-freq",
>=C2=A0 =C2=A0 =C2=A0 > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 &err);
>=C2=A0 =C2=A0 =C2=A0 > +=C2=A0 =C2=A0 if (err !=3D NULL) {
>=C2=A0 =C2=A0 =C2=A0 > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 error_reportf_er= r(err, "Couldn't set clk1 frequency: ");
>=C2=A0 =C2=A0 =C2=A0 > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 exit(1);
>=C2=A0 =C2=A0 =C2=A0 > +=C2=A0 =C2=A0 }
>=C2=A0 =C2=A0 =C2=A0 > +
>=C2=A0 =C2=A0 =C2=A0 > +=C2=A0 =C2=A0 /* Mark H3 object realized */<= br> >=C2=A0 =C2=A0 =C2=A0 > +=C2=A0 =C2=A0 object_property_set_bool(OBJEC= T(s->h3), true, "realized", &err);
>
>=C2=A0 =C2=A0 =C2=A0I'm not sure if that's correct but I'd = simply use &error_abort here.
>
> Done, I applied it to all the functions and removed the err variable.<= br> >
>=C2=A0 =C2=A0 =C2=A0 > +=C2=A0 =C2=A0 if (err !=3D NULL) {
>=C2=A0 =C2=A0 =C2=A0 > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 error_reportf_er= r(err, "Couldn't realize Allwinner H3: ");
>=C2=A0 =C2=A0 =C2=A0 > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 exit(1);
>=C2=A0 =C2=A0 =C2=A0 > +=C2=A0 =C2=A0 }
>=C2=A0 =C2=A0 =C2=A0 > +
>=C2=A0 =C2=A0 =C2=A0 > +=C2=A0 =C2=A0 /* RAM */
>=C2=A0 =C2=A0 =C2=A0 > +=C2=A0 =C2=A0 memory_region_allocate_system_= memory(&s->sdram, NULL,
>=C2=A0 =C2=A0 =C2=A0"orangepi.ram",
>=C2=A0 =C2=A0 =C2=A0 > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0machine->ram_size);
>
>=C2=A0 =C2=A0 =C2=A0I'd only allow machine->ram_size =3D=3D 1 * = GiB here, since the onboard
>=C2=A0 =C2=A0 =C2=A0DRAM
>=C2=A0 =C2=A0 =C2=A0is not upgradable.
>
>
> Agree, we should add something for that. Would it be acceptable if we =
> make the 1GB an upper limit?
> I see that the Raspberry Pi is doing that too in hw/arm/raspi.c, like = so:
>
>=C2=A0 =C2=A0 =C2=A0 if (machine->ram_size > 1 * GiB) {
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 error_report("Requested ram siz= e is too large for this machine: "
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0"maximum is 1GB");
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 exit(1);
>=C2=A0 =C2=A0 =C2=A0 }
>
> I think it would be helpful to allow the flexibility to the user of > reducing the RAM to less than 1GB,
> in case resources of the host OS are limited. What do you think?

Sure, good idea.

FIY (in case you add more models) we recently noticed there is a problem when using 2GiB default on 32-bit hosts, so the workaround is to use <= =3D
1GiB default.

>=C2=A0 =C2=A0 =C2=A0 > +=C2=A0 =C2=A0 memory_region_add_subregion(ge= t_system_memory(),
>=C2=A0 =C2=A0 =C2=A0AW_H3_SDRAM_BASE,
>=C2=A0 =C2=A0 =C2=A0 > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 &= s->sdram);
>=C2=A0 =C2=A0 =C2=A0 > +
>=C2=A0 =C2=A0 =C2=A0 > +=C2=A0 =C2=A0 /* Load target kernel */
>=C2=A0 =C2=A0 =C2=A0 > +=C2=A0 =C2=A0 orangepi_binfo.ram_size =3D ma= chine->ram_size;
>=C2=A0 =C2=A0 =C2=A0 > +=C2=A0 =C2=A0 orangepi_binfo.nb_cpus=C2=A0 = =3D AW_H3_NUM_CPUS;
>=C2=A0 =C2=A0 =C2=A0 > +=C2=A0 =C2=A0 arm_load_kernel(ARM_CPU(first_= cpu), machine, &orangepi_binfo);
>=C2=A0 =C2=A0 =C2=A0 > +}
>=C2=A0 =C2=A0 =C2=A0 > +
>=C2=A0 =C2=A0 =C2=A0 > +static void orangepi_machine_init(MachineCla= ss *mc)
>=C2=A0 =C2=A0 =C2=A0 > +{
>=C2=A0 =C2=A0 =C2=A0 > +=C2=A0 =C2=A0 mc->desc =3D "Orange P= i PC";
>=C2=A0 =C2=A0 =C2=A0 > +=C2=A0 =C2=A0 mc->init =3D orangepi_init;=
>=C2=A0 =C2=A0 =C2=A0 > +=C2=A0 =C2=A0 mc->units_per_default_bus = =3D 1;
>=C2=A0 =C2=A0 =C2=A0 > +=C2=A0 =C2=A0 mc->min_cpus =3D AW_H3_NUM_= CPUS;
>=C2=A0 =C2=A0 =C2=A0 > +=C2=A0 =C2=A0 mc->max_cpus =3D AW_H3_NUM_= CPUS;
>=C2=A0 =C2=A0 =C2=A0 > +=C2=A0 =C2=A0 mc->default_cpus =3D AW_H3_= NUM_CPUS;
>
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 mc->default_cpu_typ= e =3D ARM_CPU_TYPE_NAME("cortex-a7");
>
>=C2=A0 =C2=A0 =C2=A0 > +=C2=A0 =C2=A0 mc->ignore_memory_transacti= on_failures =3D true;
>
>=C2=A0 =C2=A0 =C2=A0You should not use this flag in new design. See the= documentation in
>=C2=A0 =C2=A0 =C2=A0include/hw/boards.h:
>
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 * @ignore_memory_transaction_failures:
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 *=C2=A0 =C2=A0 [...] New board models
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 *=C2=A0 =C2=A0 should instead use "uni= mplemented-device" for all memory
>=C2=A0 =C2=A0 =C2=A0ranges where
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 *=C2=A0 =C2=A0 the guest will attempt to pr= obe for a device that QEMU doesn't
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 *=C2=A0 =C2=A0 implement and a stub device = is required.
>
>=C2=A0 =C2=A0 =C2=A0You already use the "unimplemented-device"= ;.
>
> Thanks, I'm working on this now. I think that at least I'll ne= ed to add
> all of the devices mentioned in the 4.1 Memory Mapping chapter of the =
> datasheet
> as an unimplemented device. Previously I only added some that I though= t
> were relevant.
>
> I added all the missing devices as unimplemented and removed the
> ignore_memory_transaction_failures flag

I was going to say, "instead of adding *all* the devices regions you c= an
add the likely bus decoding regions", probably:

0x01c0.0000=C2=A0 =C2=A0128KiB=C2=A0 =C2=A0AMBA AXI
0x01c2.0000=C2=A0 =C2=A064KiB=C2=A0 =C2=A0 AMBA APB

But too late.

Hehe its okey, I can chan= ge it to whichever is preferable: the minimum set
with unimplemen= ted device entries to get a working linux kernel / u-boot or
just cover the full memory space from the datasheet. My initial thought wa= s that if
we only provide the minimum set, and the linux kernel l= ater adds a new driver for a device
which is not marked unimpleme= nted, it will trigger the data abort and potentially resulting in a non-boo= ting kernel.

But I'm not sure what is norm= ally done here. I do see other board files using the create_unimplemented_d= evice() function,
but I dont know if they are covering the whole = memory space or not.

Any thoughts? :-)
=C2=A0

> from the machine. Now it seems Linux gets a data abort while probing t= he
> uart1 serial device at 0x01c28400,

Did you add the UART1 as UNIMP or 16550?


I discovered what goes wrong here. See= this kernel oops message:

[    1.084985] [f0=
8600f8] *pgd=3D6f00a811, *pte=3D01c28653, *ppte=3D01c28453
[    1.085564] Internal error: : 8 [#1] SMP ARM
[    1.085698] Modules linked in:
[    1.085940] CPU: 0 PID: 1 Comm: swapper/0 Not tainted 5.4.0-11747-g2f134=
37b8917 #4
[    1.085968] Hardware name: Allwinner sun8i Family
[    1.086447] PC is at dw8250_setup_port+0x10/0x10c
[    1.086478] LR is at dw8250_probe+0x500/0x56c
It tries to access the UART0 at base address 0x01c28400, w= hich I did provide. The strange
thing is that is accesses offset = 0xf8, thus address 0x01c284f8. The datasheet does not mention this register=
but if we provide the 1KiB (0x400) I/O space it should at least = read as zero and writes ignored. Unfortunately the emulated
seria= l driver only maps a small portion until 0x1f:
(qemu) info m=
tree
...=20
    0000000001c28000-0000000001c2801f (prio 0, i/o): serial
    0000000001c28400-0000000001c2841f (prio 0, i/o): serial
    0000000001c28800-0000000001c2881f (prio 0, i/o): serial

Apparently, the register that the mainline linux kernel is = using is DesignWare specific:
drivers/tty/serial/8250/82=
50_dwlib.c:13:

/* Offsets for the DesignWare specific registers */
#define DW_UART_DLF<--->0xc0 /* Divisor Latch Fraction Register */
#define DW_UART_CPR<--->0xf4 /* Component Parameter Register */
#define DW_UART_UCV<--->0xf8 /* UART Component Version */
=
I tried to find a way to increase the memory mapped size of the serial= device I created with serial_mm_init(),
but I don't think it= s possible with that interface.

I did manage = to get it working by overlaying the UART0 with another unimplemented device=
that does have an I/O size of 0x400, but I guess that is probabl= y not the solution we are looking for?

I wonde= r, did any of the other SoC / boards have this problem when removing mc->= ;ignore_memory_transaction_failures?
=C2=A0
Regards= ,
Niek

> so I'll need to debug it further. I'll post back when I have m= ore results.
>
> Regards,
> Niek
>
>=C2=A0 =C2=A0 =C2=A0 > +}
>=C2=A0 =C2=A0 =C2=A0 > +
>=C2=A0 =C2=A0 =C2=A0 > +DEFINE_MACHINE("orangepi", orangep= i_machine_init)
>
>=C2=A0 =C2=A0 =C2=A0Can you name it 'orangepi-pc'? So we can ad= d other orangepi models.
>
>=C2=A0 =C2=A0 =C2=A0Thanks,
>
>=C2=A0 =C2=A0 =C2=A0Phil.
>
>
>
> --
> Niek Linnenbank
>



--
Niek Linnenbank

--000000000000fe8a3705991063e9-- From MAILER-DAEMON Sat Dec 07 04:33:26 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1idWSr-0001OF-SJ for mharc-qemu-arm@gnu.org; Sat, 07 Dec 2019 04:33:25 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:50443) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1idWSo-0001O8-1N for qemu-arm@nongnu.org; Sat, 07 Dec 2019 04:33:24 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1idWSl-0003zD-Cl for qemu-arm@nongnu.org; Sat, 07 Dec 2019 04:33:21 -0500 Received: from szxga04-in.huawei.com ([45.249.212.190]:2215 helo=huawei.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1idWSk-0003P1-M9; Sat, 07 Dec 2019 04:33:19 -0500 Received: from DGGEMS408-HUB.china.huawei.com (unknown [172.30.72.59]) by Forcepoint Email with ESMTP id BAF9296E8E8CC2C8FB65; Sat, 7 Dec 2019 17:33:09 +0800 (CST) Received: from [127.0.0.1] (10.142.68.147) by DGGEMS408-HUB.china.huawei.com (10.3.19.208) with Microsoft SMTP Server id 14.3.439.0; Sat, 7 Dec 2019 17:33:03 +0800 Subject: Re: [RESEND PATCH v21 5/6] target-arm: kvm64: handle SIGBUS signal from kernel or KVM To: Beata Michalska , Xiang Zheng CC: , , , , Peter Maydell , "Laszlo Ersek" , , , , , , , , , , , References: <20191111014048.21296-1-zhengxiang9@huawei.com> <20191111014048.21296-6-zhengxiang9@huawei.com> From: gengdongjiu Message-ID: <238ea7b3-9d6d-e3f7-40c9-e3e62b5fb477@huawei.com> Date: Sat, 7 Dec 2019 17:33:01 +0800 User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:52.0) Gecko/20100101 Thunderbird/52.3.0 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset="utf-8" Content-Language: en-US Content-Transfer-Encoding: 7bit X-Originating-IP: [10.142.68.147] X-CFilter-Loop: Reflected X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 45.249.212.190 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sat, 07 Dec 2019 09:33:24 -0000 On 2019/11/22 23:47, Beata Michalska wrote: > Hi, > > On Mon, 11 Nov 2019 at 01:48, Xiang Zheng wrote: >> >> From: Dongjiu Geng >> >> Add a SIGBUS signal handler. In this handler, it checks the SIGBUS type, >> translates the host VA delivered by host to guest PA, then fills this PA >> to guest APEI GHES memory, then notifies guest according to the SIGBUS >> type. >> >> When guest accesses the poisoned memory, it will generate a Synchronous >> External Abort(SEA). Then host kernel gets an APEI notification and calls >> memory_failure() to unmapped the affected page in stage 2, finally >> returns to guest. >> >> Guest continues to access the PG_hwpoison page, it will trap to KVM as >> stage2 fault, then a SIGBUS_MCEERR_AR synchronous signal is delivered to >> Qemu, Qemu records this error address into guest APEI GHES memory and >> notifes guest using Synchronous-External-Abort(SEA). >> >> In order to inject a vSEA, we introduce the kvm_inject_arm_sea() function >> in which we can setup the type of exception and the syndrome information. >> When switching to guest, the target vcpu will jump to the synchronous >> external abort vector table entry. >> >> The ESR_ELx.DFSC is set to synchronous external abort(0x10), and the >> ESR_ELx.FnV is set to not valid(0x1), which will tell guest that FAR is >> not valid and hold an UNKNOWN value. These values will be set to KVM >> register structures through KVM_SET_ONE_REG IOCTL. >> >> Signed-off-by: Dongjiu Geng >> Signed-off-by: Xiang Zheng >> Reviewed-by: Michael S. Tsirkin >> --- >> hw/acpi/acpi_ghes.c | 297 ++++++++++++++++++++++++++++++++++++ >> include/hw/acpi/acpi_ghes.h | 4 + >> include/sysemu/kvm.h | 3 +- >> target/arm/cpu.h | 4 + >> target/arm/helper.c | 2 +- >> target/arm/internals.h | 5 +- >> target/arm/kvm64.c | 64 ++++++++ >> target/arm/tlb_helper.c | 2 +- >> target/i386/cpu.h | 2 + >> 9 files changed, 377 insertions(+), 6 deletions(-) >> >> diff --git a/hw/acpi/acpi_ghes.c b/hw/acpi/acpi_ghes.c >> index 42c00ff3d3..f5b54990c0 100644 >> --- a/hw/acpi/acpi_ghes.c >> +++ b/hw/acpi/acpi_ghes.c >> @@ -39,6 +39,34 @@ >> /* The max size in bytes for one error block */ >> #define ACPI_GHES_MAX_RAW_DATA_LENGTH 0x1000 >> >> +/* >> + * The total size of Generic Error Data Entry >> + * ACPI 6.1/6.2: 18.3.2.7.1 Generic Error Data, >> + * Table 18-343 Generic Error Data Entry >> + */ >> +#define ACPI_GHES_DATA_LENGTH 72 >> + >> +/* >> + * The memory section CPER size, >> + * UEFI 2.6: N.2.5 Memory Error Section >> + */ >> +#define ACPI_GHES_MEM_CPER_LENGTH 80 >> + >> +/* >> + * Masks for block_status flags >> + */ >> +#define ACPI_GEBS_UNCORRECTABLE 1 > > Why not listing all supported statuses ? Similar to error severity below ? > >> + >> +/* >> + * Values for error_severity field >> + */ >> +enum AcpiGenericErrorSeverity { >> + ACPI_CPER_SEV_RECOVERABLE, >> + ACPI_CPER_SEV_FATAL, >> + ACPI_CPER_SEV_CORRECTED, >> + ACPI_CPER_SEV_NONE, >> +}; >> + >> /* >> * Now only support ARMv8 SEA notification type error source >> */ >> @@ -49,6 +77,16 @@ >> */ >> #define ACPI_GHES_SOURCE_GENERIC_ERROR_V2 10 >> >> +#define UUID_BE(a, b, c, d0, d1, d2, d3, d4, d5, d6, d7) \ >> + {{{ ((a) >> 24) & 0xff, ((a) >> 16) & 0xff, ((a) >> 8) & 0xff, (a) & 0xff, \ >> + ((b) >> 8) & 0xff, (b) & 0xff, \ >> + ((c) >> 8) & 0xff, (c) & 0xff, \ >> + (d0), (d1), (d2), (d3), (d4), (d5), (d6), (d7) } } } >> + >> +#define UEFI_CPER_SEC_PLATFORM_MEM \ >> + UUID_BE(0xA5BC1114, 0x6F64, 0x4EDE, 0xB8, 0x63, 0x3E, 0x83, \ >> + 0xED, 0x7C, 0x83, 0xB1) >> + >> /* >> * | +--------------------------+ 0 >> * | | Header | >> @@ -77,6 +115,174 @@ typedef struct AcpiGhesState { >> uint64_t ghes_addr_le; >> } AcpiGhesState; >> >> +/* >> + * Total size for Generic Error Status Block >> + * ACPI 6.2: 18.3.2.7.1 Generic Error Data, >> + * Table 18-380 Generic Error Status Block >> + */ >> +#define ACPI_GHES_GESB_SIZE 20 > > Minor: This is not entirely correct: GEDE is part of GESB so the total length > would be ACPI_GHES_GESB_SIZE + n* sizeof(GEDE) yes, the comments needs to correct. > >> +/* The offset of Data Length in Generic Error Status Block */ >> +#define ACPI_GHES_GESB_DATA_LENGTH_OFFSET 12 >> + > > If those were nicely represented as structures you get the offsets easily > without having number of defines. That could simplify the code and make it > more readable - see comments below > >> +/* >> + * Record the value of data length for each error status block to avoid getting >> + * this value from guest. >> + */ >> +static uint32_t acpi_ghes_data_length[ACPI_GHES_ERROR_SOURCE_COUNT]; >> + >> +/* >> + * Generic Error Data Entry >> + * ACPI 6.1: 18.3.2.7.1 Generic Error Data >> + */ >> +static void acpi_ghes_generic_error_data(GArray *table, QemuUUID section_type, >> + uint32_t error_severity, uint16_t revision, >> + uint8_t validation_bits, uint8_t flags, >> + uint32_t error_data_length, QemuUUID fru_id, >> + uint8_t *fru_text, uint64_t time_stamp) > > Why not just defining a struct that represents the GED entry? This is due to address Igor's comments. there are two reasons: 1. avoid define many structures about APEI/GHES/CPER, so you can see it has very little structures definition in acpi_ghes.h 2. using build_append_int_noprefix() to compose the table can avoid considering endian > >> +{ >> + QemuUUID uuid_le; >> + >> + /* Section Type */ >> + uuid_le = qemu_uuid_bswap(section_type); >> + g_array_append_vals(table, uuid_le.data, ARRAY_SIZE(uuid_le.data)); >> + >> + /* Error Severity */ >> + build_append_int_noprefix(table, error_severity, 4); >> + /* Revision */ >> + build_append_int_noprefix(table, revision, 2); > > Minor: According to the spec it seems that the revision number is > a fixed value so you could drop that from the parameters.... > or ... use a struct to represent the data > >> + /* Validation Bits */ >> + build_append_int_noprefix(table, validation_bits, 1); >> + /* Flags */ >> + build_append_int_noprefix(table, flags, 1); >> + /* Error Data Length */ >> + build_append_int_noprefix(table, error_data_length, 4); >> + >> + /* FRU Id */ >> + uuid_le = qemu_uuid_bswap(fru_id); >> + g_array_append_vals(table, uuid_le.data, ARRAY_SIZE(uuid_le.data)); >> + >> + /* FRU Text */ >> + g_array_append_vals(table, fru_text, 20); >> + /* Timestamp */ >> + build_append_int_noprefix(table, time_stamp, 8); >> +} >> + >> +/* >> + * Generic Error Status Block >> + * ACPI 6.1: 18.3.2.7.1 Generic Error Data >> + */ >> +static void acpi_ghes_generic_error_status(GArray *table, uint32_t block_status, >> + uint32_t raw_data_offset, uint32_t raw_data_length, >> + uint32_t data_length, uint32_t error_severity) > > Same as the above > >> +{ >> + /* Block Status */ >> + build_append_int_noprefix(table, block_status, 4); >> + /* Raw Data Offset */ >> + build_append_int_noprefix(table, raw_data_offset, 4); >> + /* Raw Data Length */ >> + build_append_int_noprefix(table, raw_data_length, 4); >> + /* Data Length */ >> + build_append_int_noprefix(table, data_length, 4); >> + /* Error Severity */ >> + build_append_int_noprefix(table, error_severity, 4); >> +} >> + >> +/* UEFI 2.6: N.2.5 Memory Error Section */ >> +static void acpi_ghes_build_append_mem_cper(GArray *table, >> + uint64_t error_physical_addr) >> +{ >> + /* >> + * Memory Error Record >> + */ >> + >> + /* Validation Bits */ >> + build_append_int_noprefix(table, >> + (1UL << 14) | /* Type Valid */ >> + (1UL << 1) /* Physical Address Valid */, >> + 8); >> + /* Error Status */ >> + build_append_int_noprefix(table, 0, 8); > > Just wondering whether it would be worth to specify the Error Type > through the Error Status ? > >> + /* Physical Address */ >> + build_append_int_noprefix(table, error_physical_addr, 8); >> + /* Skip all the detailed information normally found in such a record */ >> + build_append_int_noprefix(table, 0, 48); >> + /* Memory Error Type */ >> + build_append_int_noprefix(table, 0 /* Unknown error */, 1); >> + /* Skip all the detailed information normally found in such a record */ >> + build_append_int_noprefix(table, 0, 7); >> +} >> + >> +static int acpi_ghes_record_mem_error(uint64_t error_block_address, >> + uint64_t error_physical_addr, >> + uint32_t data_length) >> +{ >> + GArray *block; >> + uint64_t current_block_length; >> + /* Memory Error Section Type */ >> + QemuUUID mem_section_id_le = UEFI_CPER_SEC_PLATFORM_MEM; > > As already mentioned - mixing LE /w BE > >> + QemuUUID fru_id = {}; >> + uint8_t fru_text[20] = {}; >> + >> + /* >> + * Generic Error Status Block >> + * | +---------------------+ >> + * | | block_status | >> + * | +---------------------+ >> + * | | raw_data_offset | >> + * | +---------------------+ >> + * | | raw_data_length | >> + * | +---------------------+ >> + * | | data_length | >> + * | +---------------------+ >> + * | | error_severity | >> + * | +---------------------+ >> + */ >> + block = g_array_new(false, true /* clear */, 1); >> + >> + /* The current whole length of the generic error status block */ >> + current_block_length = ACPI_GHES_GESB_SIZE + data_length; >> + >> + /* This is the length if adding a new generic error data entry*/ >> + data_length += ACPI_GHES_DATA_LENGTH; >> + data_length += ACPI_GHES_MEM_CPER_LENGTH; >> + >> + /* >> + * Check whether it will run out of the preallocated memory if adding a new >> + * generic error data entry >> + */ >> + if ((data_length + ACPI_GHES_GESB_SIZE) > ACPI_GHES_MAX_RAW_DATA_LENGTH) { >> + error_report("Record CPER out of boundary!!!"); > > Minor: The error message could be made more accurate, like: > "Not enough memory to record new CPER" > >> + return ACPI_GHES_CPER_FAIL; >> + } >> + >> + /* Build the new generic error status block header */ >> + acpi_ghes_generic_error_status(block, cpu_to_le32(ACPI_GEBS_UNCORRECTABLE), >> + 0, 0, cpu_to_le32(data_length), cpu_to_le32(ACPI_CPER_SEV_RECOVERABLE)); >> + >> + /* Write back above generic error status block header to guest memory */ >> + cpu_physical_memory_write(error_block_address, block->data, >> + block->len); >> + >> + /* Add a new generic error data entry */ >> + >> + data_length = block->len; >> + /* Build this new generic error data entry header */ >> + acpi_ghes_generic_error_data(block, mem_section_id_le, >> + cpu_to_le32(ACPI_CPER_SEV_RECOVERABLE), cpu_to_le32(0x300), 0, 0, >> + cpu_to_le32(ACPI_GHES_MEM_CPER_LENGTH), fru_id, fru_text, 0); >> + >> + /* Build the memory section CPER for above new generic error data entry */ >> + acpi_ghes_build_append_mem_cper(block, error_physical_addr); >> + >> + /* Write back above this new generic error data entry to guest memory */ >> + cpu_physical_memory_write(error_block_address + current_block_length, >> + block->data + data_length, block->len - data_length); >> + > > As already mentioned and unless I have missed smth (which is highly possible) > this will append new records while the GESB is kept 'in-place'. So the > used space is > only growing. > >> + g_array_free(block, true); >> + >> + return ACPI_GHES_CPER_OK; >> +} >> + >> /* >> * Hardware Error Notification >> * ACPI 4.0: 17.3.2.7 Hardware Error Notification >> @@ -265,3 +471,94 @@ void acpi_ghes_add_fw_cfg(FWCfgState *s, GArray *hardware_error) >> fw_cfg_add_file_callback(s, ACPI_GHES_DATA_ADDR_FW_CFG_FILE, NULL, NULL, >> NULL, &ges.ghes_addr_le, sizeof(ges.ghes_addr_le), false); >> } >> + >> +bool acpi_ghes_record_errors(uint32_t notify, uint64_t physical_address) >> +{ >> + uint64_t error_block_addr, read_ack_register_addr, read_ack_register = 0; >> + int loop = 0; >> + uint64_t start_addr = le64_to_cpu(ges.ghes_addr_le); >> + bool ret = ACPI_GHES_CPER_FAIL; >> + uint8_t source_id; >> + const uint8_t error_source_id[] = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, >> + 0xff, 0xff, 0, 0xff, 0xff, 0xff}; >> + > > I'm not entirely sure why this is needed - se below > >> + /* >> + * | +---------------------+ ges.ghes_addr_le >> + * | |error_block_address0 | >> + * | +---------------------+ --+-- >> + * | | ............. | ACPI_GHES_ADDRESS_SIZE >> + * | +---------------------+ --+-- >> + * | |error_block_addressN | >> + * | +---------------------+ >> + * | | read_ack_register0 | >> + * | +---------------------+ --+-- >> + * | | ............. | ACPI_GHES_ADDRESS_SIZE >> + * | +---------------------+ --+-- >> + * | | read_ack_registerN | >> + * | +---------------------+ --+-- >> + * | | CPER | | >> + * | | .... | ACPI_GHES_MAX_RAW_DATA_LENGT >> + * | | CPER | | >> + * | +---------------------+ --+-- >> + * | | .......... | >> + * | +---------------------+ >> + * | | CPER | >> + * | | .... | >> + * | | CPER | >> + * | +---------------------+ >> + */ >> + if (physical_address && notify < ACPI_GHES_NOTIFY_RESERVED) { >> + /* Find and check the source id for this new CPER */ >> + source_id = error_source_id[notify]; > > Why not using switch case for supported source types ? > For the time being only one is being supported. And you only use that to > verify that support - seems a bit unnecessary. Afterwards May be we will many source types to support, so Igor's suggestion is better as shown below. static const uint8_t ghes_notify2source_id_map[] = { ACPI_HEST_SRC_ID_SEA, ACPI_HEST_SRC_ID_RESERVED } > >> + if (source_id != 0xff) { >> + start_addr += source_id * ACPI_GHES_ADDRESS_SIZE; >> + } else { >> + goto out; >> + } >> + [...] >> >> +/* Callers must hold the iothread mutex lock */ >> +static void kvm_inject_arm_sea(CPUState *c) > > We could enclose this function along with the kvm_arch_on_sigbus_vcpu > within ifdef switch for KVM_HAVE_MCE_INJECTION > >> +{ >> + ARMCPU *cpu = ARM_CPU(c); >> + CPUARMState *env = &cpu->env; >> + CPUClass *cc = CPU_GET_CLASS(c); >> + uint32_t esr; >> + bool same_el; >> + >> + c->exception_index = EXCP_DATA_ABORT; >> + env->exception.target_el = 1; >> + >> + /* >> + * Set the DFSC to synchronous external abort and set FnV to not valid, >> + * this will tell guest the FAR_ELx is UNKNOWN for this abort. >> + */ >> + same_el = arm_current_el(env) == env->exception.target_el; >> + esr = syn_data_abort_no_iss(same_el, 1, 0, 0, 0, 0, 0x10); > > IINM this is the only use case when FnV is considered to be valid > so I'm not convinced it is worth to modify the syn_data_abort_no_iss > just for this. Here we set the FnV to not valid, not to set it to valid. because Guest will use the physical address that recorded in APEI table. > >> + >> + env->exception.syndrome = esr; >> + >> + cc->do_interrupt(c); >> +} >> + >> #define AARCH64_CORE_REG(x) (KVM_REG_ARM64 | KVM_REG_SIZE_U64 | \ >> KVM_REG_ARM_CORE | KVM_REG_ARM_CORE_REG(x)) >> >> @@ -1036,6 +1062,44 @@ int kvm_arch_get_registers(CPUState *cs) >> return ret; >> } >> >> +void kvm_arch_on_sigbus_vcpu(CPUState *c, int code, void *addr) >> +{ >> + ram_addr_t ram_addr; >> + hwaddr paddr; >> + >> + assert(code == BUS_MCEERR_AR || code == BUS_MCEERR_AO); >> + >> + if (acpi_enabled && addr && >> + object_property_get_bool(qdev_get_machine(), "ras", NULL)) { >> + ram_addr = qemu_ram_addr_from_host(addr); >> + if (ram_addr != RAM_ADDR_INVALID && >> + kvm_physical_memory_addr_from_host(c->kvm_state, addr, &paddr)) { >> + kvm_hwpoison_page_add(ram_addr); >> + /* >> + * Asynchronous signal will be masked by main thread, so >> + * only handle synchronous signal. >> + */ > > I'm not entirely sure that the comment above is correct (it has been > pointed out before). I would expect the AO signal to be handled here as > well. Not having proper support to do that just yet is another story but > the comment might be bit misleading. > > >> + if (code == BUS_MCEERR_AR) { >> + kvm_cpu_synchronize_state(c); >> + if (ACPI_GHES_CPER_FAIL != >> + acpi_ghes_record_errors(ACPI_GHES_NOTIFY_SEA, paddr)) { >> + kvm_inject_arm_sea(c); >> + } else { >> + fprintf(stderr, "failed to record the error\n"); >> + } >> + } >> + return; >> + } >> + fprintf(stderr, "Hardware memory error for memory used by " >> + "QEMU itself instead of guest system!\n"); >> + } >> + >> + if (code == BUS_MCEERR_AR) { >> + fprintf(stderr, "Hardware memory error!\n"); >> + exit(1); >> + } >> +} >> + >> /* C6.6.29 BRK instruction */ >> static const uint32_t brk_insn = 0xd4200000; >> >> diff --git a/target/arm/tlb_helper.c b/target/arm/tlb_helper.c >> index 5feb312941..499672ebbc 100644 >> --- a/target/arm/tlb_helper.c >> +++ b/target/arm/tlb_helper.c >> @@ -33,7 +33,7 @@ static inline uint32_t merge_syn_data_abort(uint32_t template_syn, >> * ISV field. >> */ >> if (!(template_syn & ARM_EL_ISV) || target_el != 2 || s1ptw) { >> - syn = syn_data_abort_no_iss(same_el, >> + syn = syn_data_abort_no_iss(same_el, 0, >> ea, 0, s1ptw, is_write, fsc); >> } else { >> /* >> diff --git a/target/i386/cpu.h b/target/i386/cpu.h >> index 5352c9ff55..f75a210f96 100644 >> --- a/target/i386/cpu.h >> +++ b/target/i386/cpu.h >> @@ -29,6 +29,8 @@ >> /* The x86 has a strong memory model with some store-after-load re-ordering */ >> #define TCG_GUEST_DEFAULT_MO (TCG_MO_ALL & ~TCG_MO_ST_LD) >> >> +#define KVM_HAVE_MCE_INJECTION 1 >> + >> /* Maximum instruction code size */ >> #define TARGET_MAX_INSN_SIZE 16 >> >> -- >> 2.19.1 >> >> >> > . > From MAILER-DAEMON Sat Dec 07 14:57:55 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1idgDD-0003U1-4G for mharc-qemu-arm@gnu.org; Sat, 07 Dec 2019 14:57:55 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:45624) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1idgD9-0003Tm-Sk for qemu-arm@nongnu.org; Sat, 07 Dec 2019 14:57:52 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1idgD8-0006Y5-Le for qemu-arm@nongnu.org; Sat, 07 Dec 2019 14:57:51 -0500 Received: from szxga07-in.huawei.com ([45.249.212.35]:46610 helo=huawei.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1idgD8-0006An-9K; Sat, 07 Dec 2019 14:57:50 -0500 Received: from DGGEMS408-HUB.china.huawei.com (unknown [172.30.72.59]) by Forcepoint Email with ESMTP id BC182A40469D3AC3E506; Sat, 7 Dec 2019 20:10:41 +0800 (CST) Received: from [127.0.0.1] (10.142.68.147) by DGGEMS408-HUB.china.huawei.com (10.3.19.208) with Microsoft SMTP Server id 14.3.439.0; Sat, 7 Dec 2019 20:10:31 +0800 Subject: Re: [RESEND PATCH v21 1/6] hw/arm/virt: Introduce a RAS machine option To: Peter Maydell , Xiang Zheng CC: Paolo Bonzini , "Michael S. Tsirkin" , Igor Mammedov , Shannon Zhao , Laszlo Ersek , James Morse , Marcelo Tosatti , "Richard Henderson" , Eduardo Habkost , "Jonathan Cameron" , "xuwei (O)" , kvm-devel , QEMU Developers , qemu-arm , Linuxarm , References: <20191111014048.21296-1-zhengxiang9@huawei.com> <20191111014048.21296-2-zhengxiang9@huawei.com> From: gengdongjiu Message-ID: <8219fac5-107c-32de-e9d2-2178bd8639a8@huawei.com> Date: Sat, 7 Dec 2019 20:10:28 +0800 User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:52.0) Gecko/20100101 Thunderbird/52.3.0 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset="utf-8" Content-Language: en-US Content-Transfer-Encoding: 7bit X-Originating-IP: [10.142.68.147] X-CFilter-Loop: Reflected X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 45.249.212.35 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sat, 07 Dec 2019 19:57:53 -0000 > > I think we could make the user-facing description of > the option a little clearer: something like > "Set on/off to enable/disable reporting host memory errors > to a KVM guest using ACPI and guest external abort exceptions" > > ? Peter, sorry for the late response. sure, we have already updated it, and will send PATCH V22. > > Otherwise > Reviewed-by: Peter Maydell > > thanks > -- PMM > . > From MAILER-DAEMON Sat Dec 07 15:35:10 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1idgnG-0003qu-4p for mharc-qemu-arm@gnu.org; Sat, 07 Dec 2019 15:35:10 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:43456) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1idgnC-0003mc-Vi for qemu-arm@nongnu.org; Sat, 07 Dec 2019 15:35:08 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1idgnA-0001Yw-H4 for qemu-arm@nongnu.org; Sat, 07 Dec 2019 15:35:06 -0500 Received: from mail-lf1-x143.google.com ([2a00:1450:4864:20::143]:37481) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1idgn6-0001Rv-U8; Sat, 07 Dec 2019 15:35:01 -0500 Received: by mail-lf1-x143.google.com with SMTP id b15so7810226lfc.4; Sat, 07 Dec 2019 12:35:00 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=hNUjK1+kYweHU8biayWEpHSVMZrIN26jACvApJZkpdE=; b=VPBbK9IyFG5K/UJfCwODJChg8RrMQG25q9eJMV+phx8QbZvWZlXp1cP4pTLoWJP5vS i/SAJ+suo4rP5hAFgKsl9f6Wac2QYL2ix4s6PjitslZEG78WCcI/ix8Whs63PO2o3gCm 8hhLlreJdfYQxdCT9fVCeRLyHnkeGYSEVXBXIDy8AOe5X5Jtdyw7naQjT+KGQnVPNj6R DIIwg18zR6N1uWtdbqqTd2CE02uPlXV/yYSJAJshZHh+KT2pZo/eodCg7CVsOQF0Xien om3mgQhBX+eRc5+lmFqLZ8cx0gmASO8YgJnTJYxJQ/PTNyvH6CA0IeO/POoV04AUn19v hTcQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=hNUjK1+kYweHU8biayWEpHSVMZrIN26jACvApJZkpdE=; b=n2595SvkgzERxwnkoLT6RD/3fmj4YytfDWWBLA9PimNQoldoJ1ND2jXvTBO8q2WnZt F7empJbKtV7aks6UKJTe+IWSyd8C5n0T89sxDKBnqEaGrz6nUckZ1B45DW0/mGQh+hLR Safeb6b0FyPpTA8c0tjWGUrBCCV5VMR4SefBxxFPaVlCOb1bsiEOv522OqPpFIrSj4XT 3ZtIFgZrRo6Em+wFcg2kpgXN8rXC2Za/bi14bOn6WA3Nbln8yZ4Zb0lyCjFk4oMDEWex 6sWxvYnJzuQjq/8jNAZy/fBQfB4a9dDQSBWt76SuN1S0O3ZN72uTxCGIM8jXqXx+Age7 dzuw== X-Gm-Message-State: APjAAAURKtlHQj/rQVxG7QI2ICWCnitES08LN/CSZzg2sd4ZwYXzRe1B DrdmdQDA5aUmTlpn1XOVl33A36ZKG10= X-Google-Smtp-Source: APXvYqxO64tgaFZCigNrkJ0Mi2hObj9KNiF2/azEUf0U/wAtBCj4yqtpTRw9N+PGEPHMNcTl98wuuA== X-Received: by 2002:ac2:5a48:: with SMTP id r8mr11090826lfn.179.1575750898705; Sat, 07 Dec 2019 12:34:58 -0800 (PST) Received: from PKL-BWASIM-LT.mgc.mentorg.com (static-host202-147-173-53.link.net.pk. [202.147.173.53]) by smtp.gmail.com with ESMTPSA id c9sm7579815ljd.28.2019.12.07.12.34.54 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sat, 07 Dec 2019 12:34:57 -0800 (PST) From: bilalwasim676@gmail.com To: qemu-devel@nongnu.org Cc: jasowang@redhat.com, qemu-arm@nongnu.org, peter.maydell@linaro.org, philmd@redhat.com, Bilal Wasim , Bilal Wasim Subject: [PATCH] Adding support for MAC filtering in the FEC IP implementation. Date: Sun, 8 Dec 2019 01:34:50 +0500 Message-Id: <20191207203450.6304-1-bilalwasim676@gmail.com> X-Mailer: git-send-email 2.19.1.windows.1 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::143 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sat, 07 Dec 2019 20:35:08 -0000 From: Bilal Wasim This addition ensures that the IP does NOT boot up in promiscuous mode by default, and so the software only receives the desired packets(Unicast, Broadcast, Unicast / Multicast hashed) by default. The software running on-top of QEMU can also modify these settings and disable reception of broadcast frames or make the IP receive all packets (PROM mode). This patch greatly reduces the number of packets received by the software running on-top of the QEMU model. Tested with the armv7-a SABRE_LITE machine. Testing included running a custom OS with IPv4 / IPv6 support. Hashing and filtering of packets is tested to work well. Skeleton taken from the CADENCE_GEM IP and hash generation algorithm from the Linux Kernel. Signed-off-by: Bilal Wasim --- hw/net/imx_fec.c | 108 ++++++++++++++++++++++++++++++++++++++- include/hw/net/imx_fec.h | 12 +++++ 2 files changed, 119 insertions(+), 1 deletion(-) diff --git a/hw/net/imx_fec.c b/hw/net/imx_fec.c index bd99236864..dc39f1f597 100644 --- a/hw/net/imx_fec.c +++ b/hw/net/imx_fec.c @@ -419,6 +419,80 @@ static void imx_enet_write_bd(IMXENETBufDesc *bd, dma_addr_t addr) dma_memory_write(&address_space_memory, addr, bd, sizeof(*bd)); } +/* + * Calculate a FEC MAC Address hash index + */ +static unsigned calc_mac_hash(const uint8_t *mac, uint8_t mac_length) +{ + uint32_t crc = -1; + int i; + + while (mac_length --) { + crc ^= *mac++; + for (i = 0; i < 8; i++) { + crc = (crc >> 1) ^ ((crc & 1) ? CRCPOLY_LE : 0); + } + } + + /* only upper 6 bits (FEC_HASH_BITS) are used + * which point to specific bit in the hash registers + */ + return ((crc >> (32 - FEC_HASH_BITS)) & 0x3f); +} + +/* + * fec_mac_address_filter: + * Accept or reject this destination address? + */ +static int fec_mac_address_filter(IMXFECState *s, const uint8_t *packet) +{ + const uint8_t broadcast_addr[] = { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }; + uint32_t addr1, addr2; + uint8_t hash; + + /* Promiscuous mode? */ + if (s->regs[ENET_RCR] & ENET_RCR_PROM) { + return (FEC_RX_PROMISCUOUS_ACCEPT); /* Accept all packets in promiscuous mode (even if bc_rej is set). */ + } + + /* Broadcast packet? */ + if (!memcmp(packet, broadcast_addr, 6)) { + /* Reject broadcast packets? */ + if (s->regs[ENET_RCR] & ENET_RCR_BC_REJ) { + return (FEC_RX_REJECT); + } + return (FEC_RX_BROADCAST_ACCEPT); /* Accept packets from broadcast address. */ + } + + /* Accept packets -w- hash match? */ + hash = calc_mac_hash(packet, 6); + + /* Accept packets -w- multicast hash match? */ + if ((packet[0] & 0x01) == 0x01) { + /* See if the computed hash matches a set bit in either GAUR / GALR register. */ + if (((hash < 32) && (s->regs[ENET_GALR] & (1 << hash))) + || ((hash > 31) && (s->regs[ENET_GAUR] & (1 << (hash-32))))) { + return (FEC_RX_MULTICAST_HASH_ACCEPT); /* Accept multicast hash enabled address. */ + } + } else { + /* See if the computed hash matches a set bit in either IAUR / IALR register. */ + if (((hash < 32) && (s->regs[ENET_IALR] & (1 << hash))) + || ((hash > 31) && (s->regs[ENET_IAUR] & (1 << (hash-32))))) { + return (FEC_RX_UNICAST_HASH_ACCEPT); /* Accept multicast hash enabled address. */ + } + } + + /* Match Unicast address. */ + addr1 = g_htonl(s->regs[ENET_PALR]); + addr2 = g_htonl(s->regs[ENET_PAUR]); + if (!(memcmp(packet, (uint8_t *) &addr1, 4) || memcmp(packet+4, (uint8_t *) &addr2, 2))) { + return (FEC_RX_UNICAST_ACCEPT); /* Accept packet because it matches my unicast address. */ + } + + /* Return -1 because we do NOT support MAC address filtering.. */ + return (FEC_RX_REJECT); +} + static void imx_eth_update(IMXFECState *s) { /* @@ -984,7 +1058,7 @@ static void imx_eth_write(void *opaque, hwaddr offset, uint64_t value, case ENET_IALR: case ENET_GAUR: case ENET_GALR: - /* TODO: implement MAC hash filtering. */ + s->regs[index] |= value; break; case ENET_TFWR: if (s->is_fec) { @@ -1066,8 +1140,16 @@ static ssize_t imx_fec_receive(NetClientState *nc, const uint8_t *buf, uint32_t buf_addr; uint8_t *crc_ptr; unsigned int buf_len; + int maf; size_t size = len; + /* Is this destination MAC address "for us" ? */ + maf = fec_mac_address_filter(s, buf); + if (maf == FEC_RX_REJECT) + { + return (FEC_RX_REJECT); + } + FEC_PRINTF("len %d\n", (int)size); if (!s->regs[ENET_RDAR]) { @@ -1133,6 +1215,14 @@ static ssize_t imx_fec_receive(NetClientState *nc, const uint8_t *buf, } else { s->regs[ENET_EIR] |= ENET_INT_RXB; } + + /* Update descriptor based on the "maf" flag. */ + if (maf == FEC_RX_BROADCAST_ACCEPT) { + bd.flags |= ENET_BD_BC; /* The packet is destined for the "broadcast" address. */ + } else if (maf == FEC_RX_MULTICAST_HASH_ACCEPT) { + bd.flags |= ENET_BD_MC; /* The packet is destined for a "multicast" address. */ + } + imx_fec_write_bd(&bd, addr); /* Advance to the next descriptor. */ if ((bd.flags & ENET_BD_W) != 0) { @@ -1159,8 +1249,16 @@ static ssize_t imx_enet_receive(NetClientState *nc, const uint8_t *buf, uint8_t *crc_ptr; unsigned int buf_len; size_t size = len; + int maf; bool shift16 = s->regs[ENET_RACC] & ENET_RACC_SHIFT16; + /* Is this destination MAC address "for us" ? */ + maf = fec_mac_address_filter(s, buf); + if (maf == FEC_RX_REJECT) + { + return (FEC_RX_REJECT); + } + FEC_PRINTF("len %d\n", (int)size); if (!s->regs[ENET_RDAR]) { @@ -1254,6 +1352,14 @@ static ssize_t imx_enet_receive(NetClientState *nc, const uint8_t *buf, s->regs[ENET_EIR] |= ENET_INT_RXB; } } + + /* Update descriptor based on the "maf" flag. */ + if (maf == FEC_RX_BROADCAST_ACCEPT) { + bd.flags |= ENET_BD_BC; /* The packet is destined for the "broadcast" address. */ + } else if (maf == FEC_RX_MULTICAST_HASH_ACCEPT) { + bd.flags |= ENET_BD_MC; /* The packet is destined for a "multicast" address. */ + } + imx_enet_write_bd(&bd, addr); /* Advance to the next descriptor. */ if ((bd.flags & ENET_BD_W) != 0) { diff --git a/include/hw/net/imx_fec.h b/include/hw/net/imx_fec.h index 7b3faa4019..d38c8fe0e8 100644 --- a/include/hw/net/imx_fec.h +++ b/include/hw/net/imx_fec.h @@ -275,4 +275,16 @@ typedef struct IMXFECState { uint8_t frame[ENET_MAX_FRAME_SIZE]; } IMXFECState; +/* FEC address filtering defines. */ +#define FEC_RX_REJECT (-1) +#define FEC_RX_PROMISCUOUS_ACCEPT (-2) +#define FEC_RX_BROADCAST_ACCEPT (-3) +#define FEC_RX_MULTICAST_HASH_ACCEPT (-4) +#define FEC_RX_UNICAST_HASH_ACCEPT (-5) +#define FEC_RX_UNICAST_ACCEPT (-6) + +/* FEC hash filtering defines.*/ +#define CRCPOLY_LE 0xedb88320 +#define FEC_HASH_BITS 6 /* #bits in hash */ + #endif -- 2.19.1.windows.1 From MAILER-DAEMON Sat Dec 07 16:08:29 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1idhJV-0003wC-5l for mharc-qemu-arm@gnu.org; Sat, 07 Dec 2019 16:08:29 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:46145) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1idhJS-0003sZ-0f for qemu-arm@nongnu.org; Sat, 07 Dec 2019 16:08:27 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1idhJQ-00035u-Ed for qemu-arm@nongnu.org; Sat, 07 Dec 2019 16:08:25 -0500 Resent-Date: Sat, 07 Dec 2019 16:08:25 -0500 Resent-Message-Id: Received: from sender4-of-o50.zoho.com ([136.143.188.50]:21021) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1idhJM-0002Xc-3t; Sat, 07 Dec 2019 16:08:20 -0500 ARC-Seal: i=1; a=rsa-sha256; t=1575752883; cv=none; d=zohomail.com; s=zohoarc; b=nWjCJt72UjZpS8WVlkRPFw7lUusK4c9QYxgPVzmhkUwtY0Bd2G0s30r8EeYcPFgF73dEnC31JB7zGOfKjtUMke3bvqQ8C6cUFDGWTKgbEgFM32vTrUhEjlozAkODqKR3OYkBOoWj0g8WhR0uw9miFC/JoBbjUQ4HkH1k2qT394Q= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1575752883; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:MIME-Version:Message-ID:Reply-To:Subject:To; bh=QnUPEnrmrRos4pht7sHAediUfj0ILaD9yNFS+AoHBNg=; b=VmDBbXu86Aj5EHz/mkoRxJ/8Lzt9UWlUHqVFa3i9yPqcnIiFf0ajDIJHda/UZqCU09784MQTM1scWNr+cD1gAwnqcVHgAMbThYFmFhMWpYw3r17gfObeaaluRujQAvFtJCf1ob82xOaQrw11Qcndredncaj7zazVfcWOiQLNthA= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass header.i=patchew.org; spf=pass smtp.mailfrom=no-reply@patchew.org; dmarc=pass header.from= header.from= Received: from [172.17.0.3] (23.253.156.214 [23.253.156.214]) by mx.zohomail.com with SMTPS id 1575752882996808.4241966592465; Sat, 7 Dec 2019 13:08:02 -0800 (PST) In-Reply-To: <20191207203450.6304-1-bilalwasim676@gmail.com> Reply-To: Subject: Re: [PATCH] Adding support for MAC filtering in the FEC IP implementation. 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[202.147.173.53]) by smtp.gmail.com with ESMTPSA id s22sm8759229ljm.41.2019.12.07.13.56.27 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sat, 07 Dec 2019 13:56:29 -0800 (PST) From: bilalwasim676@gmail.com To: qemu-devel@nongnu.org Cc: jasowang@redhat.com, qemu-arm@nongnu.org, peter.maydell@linaro.org, philmd@redhat.com, bilal_wasim@mentor.com, Bilal Wasim Subject: [PATCH v2] Adding support for MAC filtering in the FEC IP implementation. Date: Sun, 8 Dec 2019 02:56:23 +0500 Message-Id: <20191207215623.16532-1-bilalwasim676@gmail.com> X-Mailer: git-send-email 2.19.1.windows.1 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::243 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sat, 07 Dec 2019 21:56:47 -0000 From: Bilal Wasim This addition ensures that the IP does NOT boot up in promiscuous mode by default, and so the software only receives the desired packets(Unicast, Broadcast, Unicast / Multicast hashed) by default. The software running on-top of QEMU can also modify these settings and disable reception of broadcast frames or make the IP receive all packets (PROM mode). This patch greatly reduces the number of packets received by the software running on-top of the QEMU model. Tested with the armv7-a SABRE_LITE machine. Testing included running a custom OS with IPv4 / IPv6 support. Hashing and filtering of packets is tested to work well. Skeleton taken from the CADENCE_GEM IP and hash generation algorithm from the Linux Kernel. Signed-off-by: Bilal Wasim --- hw/net/imx_fec.c | 117 ++++++++++++++++++++++++++++++++++++++- include/hw/net/imx_fec.h | 12 ++++ 2 files changed, 128 insertions(+), 1 deletion(-) diff --git a/hw/net/imx_fec.c b/hw/net/imx_fec.c index bd99236864..cc1572b5fe 100644 --- a/hw/net/imx_fec.c +++ b/hw/net/imx_fec.c @@ -419,6 +419,87 @@ static void imx_enet_write_bd(IMXENETBufDesc *bd, dma_addr_t addr) dma_memory_write(&address_space_memory, addr, bd, sizeof(*bd)); } +/* + * Calculate a FEC MAC Address hash index + */ +static unsigned calc_mac_hash(const uint8_t *mac, uint8_t mac_length) +{ + uint32_t crc = -1; + int i; + + while (mac_length--) { + crc ^= *mac++; + for (i = 0; i < 8; i++) { + crc = (crc >> 1) ^ ((crc & 1) ? CRCPOLY_LE : 0); + } + } + + /* + * only upper 6 bits (FEC_HASH_BITS) are used + * which point to specific bit in the hash registers + */ + return (crc >> (32 - FEC_HASH_BITS)) & 0x3f; +} + +/* + * fec_mac_address_filter: + * Accept or reject this destination address? + */ +static int fec_mac_address_filter(IMXFECState *s, const uint8_t *packet) +{ + const uint8_t broadcast_addr[] = { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }; + uint32_t addr1, addr2; + uint8_t hash; + + /* Promiscuous mode? */ + if (s->regs[ENET_RCR] & ENET_RCR_PROM) { + /* Accept all packets in promiscuous mode (even if bc_rej is set). */ + return FEC_RX_PROMISCUOUS_ACCEPT; + } + + /* Broadcast packet? */ + if (!memcmp(packet, broadcast_addr, 6)) { + /* Reject broadcast packets? */ + if (s->regs[ENET_RCR] & ENET_RCR_BC_REJ) { + return FEC_RX_REJECT; + } + /* Accept packets from broadcast address. */ + return FEC_RX_BROADCAST_ACCEPT; + } + + /* Accept packets -w- hash match? */ + hash = calc_mac_hash(packet, 6); + + /* Accept packets -w- multicast hash match? */ + if ((packet[0] & 0x01) == 0x01) { + /* Computed hash matches GAUR / GALR register ? */ + if (((hash < 32) && (s->regs[ENET_GALR] & (1 << hash))) + || ((hash > 31) && (s->regs[ENET_GAUR] & (1 << (hash - 32))))) { + /* Accept multicast hash enabled address. */ + return FEC_RX_MULTICAST_HASH_ACCEPT; + } + } else { + /* Computed hash matches IAUR / IALR register ? */ + if (((hash < 32) && (s->regs[ENET_IALR] & (1 << hash))) + || ((hash > 31) && (s->regs[ENET_IAUR] & (1 << (hash - 32))))) { + /* Accept multicast hash enabled address. */ + return FEC_RX_UNICAST_HASH_ACCEPT; + } + } + + /* Match Unicast address. */ + addr1 = g_htonl(s->regs[ENET_PALR]); + addr2 = g_htonl(s->regs[ENET_PAUR]); + if (!(memcmp(packet, (uint8_t *) &addr1, 4) || + memcmp(packet + 4, (uint8_t *) &addr2, 2))) { + /* Accept packet because it matches my unicast address. */ + return FEC_RX_UNICAST_ACCEPT; + } + + /* Return -1 because we do NOT support MAC address filtering.. */ + return FEC_RX_REJECT; +} + static void imx_eth_update(IMXFECState *s) { /* @@ -984,7 +1065,7 @@ static void imx_eth_write(void *opaque, hwaddr offset, uint64_t value, case ENET_IALR: case ENET_GAUR: case ENET_GALR: - /* TODO: implement MAC hash filtering. */ + s->regs[index] |= value; break; case ENET_TFWR: if (s->is_fec) { @@ -1066,8 +1147,15 @@ static ssize_t imx_fec_receive(NetClientState *nc, const uint8_t *buf, uint32_t buf_addr; uint8_t *crc_ptr; unsigned int buf_len; + int maf; size_t size = len; + /* Is this destination MAC address "for us" ? */ + maf = fec_mac_address_filter(s, buf); + if (maf == FEC_RX_REJECT) { + return FEC_RX_REJECT; + } + FEC_PRINTF("len %d\n", (int)size); if (!s->regs[ENET_RDAR]) { @@ -1133,6 +1221,16 @@ static ssize_t imx_fec_receive(NetClientState *nc, const uint8_t *buf, } else { s->regs[ENET_EIR] |= ENET_INT_RXB; } + + /* Update descriptor based on the "maf" flag. */ + if (maf == FEC_RX_BROADCAST_ACCEPT) { + /* The packet is destined for the "broadcast" address. */ + bd.flags |= ENET_BD_BC; + } else if (maf == FEC_RX_MULTICAST_HASH_ACCEPT) { + /* The packet is destined for a "multicast" address. */ + bd.flags |= ENET_BD_MC; + } + imx_fec_write_bd(&bd, addr); /* Advance to the next descriptor. */ if ((bd.flags & ENET_BD_W) != 0) { @@ -1159,8 +1257,15 @@ static ssize_t imx_enet_receive(NetClientState *nc, const uint8_t *buf, uint8_t *crc_ptr; unsigned int buf_len; size_t size = len; + int maf; bool shift16 = s->regs[ENET_RACC] & ENET_RACC_SHIFT16; + /* Is this destination MAC address "for us" ? */ + maf = fec_mac_address_filter(s, buf); + if (maf == FEC_RX_REJECT) { + return FEC_RX_REJECT; + } + FEC_PRINTF("len %d\n", (int)size); if (!s->regs[ENET_RDAR]) { @@ -1254,6 +1359,16 @@ static ssize_t imx_enet_receive(NetClientState *nc, const uint8_t *buf, s->regs[ENET_EIR] |= ENET_INT_RXB; } } + + /* Update descriptor based on the "maf" flag. */ + if (maf == FEC_RX_BROADCAST_ACCEPT) { + /* The packet is destined for the "broadcast" address. */ + bd.flags |= ENET_BD_BC; + } else if (maf == FEC_RX_MULTICAST_HASH_ACCEPT) { + /* The packet is destined for a "multicast" address. */ + bd.flags |= ENET_BD_MC; + } + imx_enet_write_bd(&bd, addr); /* Advance to the next descriptor. */ if ((bd.flags & ENET_BD_W) != 0) { diff --git a/include/hw/net/imx_fec.h b/include/hw/net/imx_fec.h index 7b3faa4019..d38c8fe0e8 100644 --- a/include/hw/net/imx_fec.h +++ b/include/hw/net/imx_fec.h @@ -275,4 +275,16 @@ typedef struct IMXFECState { uint8_t frame[ENET_MAX_FRAME_SIZE]; } IMXFECState; +/* FEC address filtering defines. */ +#define FEC_RX_REJECT (-1) +#define FEC_RX_PROMISCUOUS_ACCEPT (-2) +#define FEC_RX_BROADCAST_ACCEPT (-3) +#define FEC_RX_MULTICAST_HASH_ACCEPT (-4) +#define FEC_RX_UNICAST_HASH_ACCEPT (-5) +#define FEC_RX_UNICAST_ACCEPT (-6) + +/* FEC hash filtering defines.*/ +#define CRCPOLY_LE 0xedb88320 +#define FEC_HASH_BITS 6 /* #bits in hash */ + #endif -- 2.19.1.windows.1 From MAILER-DAEMON Sun Dec 08 21:07:11 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1ie8S7-0000G0-EC for mharc-qemu-arm@gnu.org; Sun, 08 Dec 2019 21:07:11 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:35297) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ie8S4-0000Fs-QH for qemu-arm@nongnu.org; Sun, 08 Dec 2019 21:07:09 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ie8S3-0007ce-Mk for qemu-arm@nongnu.org; Sun, 08 Dec 2019 21:07:08 -0500 Received: from szxga07-in.huawei.com ([45.249.212.35]:55542 helo=huawei.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1ie8S3-0007NS-9r; Sun, 08 Dec 2019 21:07:07 -0500 Received: from DGGEMS413-HUB.china.huawei.com (unknown [172.30.72.58]) by Forcepoint Email with ESMTP id EF74DCD4B669C687F342; Mon, 9 Dec 2019 10:06:59 +0800 (CST) Received: from [127.0.0.1] (10.133.216.73) by DGGEMS413-HUB.china.huawei.com (10.3.19.213) with Microsoft SMTP Server id 14.3.439.0; Mon, 9 Dec 2019 10:06:51 +0800 Subject: Re: [Qemu-devel] [PATCH v5 0/2] arm/acpi: simplify aml code and enable SHPC To: Peter Maydell CC: Igor Mammedov , qemu-arm , "QEMU Developers" , "Michael S. Tsirkin" , Shannon Zhao , References: <1552098649-28341-1-git-send-email-guoheyi@huawei.com> <20190312170859.73f0de9d@redhat.com> From: Guoheyi Message-ID: <9761915a-3ed1-7d91-60c3-bfdf703d22d5@huawei.com> Date: Mon, 9 Dec 2019 10:06:50 +0800 User-Agent: Mozilla/5.0 (Windows NT 10.0; WOW64; rv:68.0) Gecko/20100101 Thunderbird/68.2.2 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset="utf-8"; format=flowed X-Originating-IP: [10.133.216.73] X-CFilter-Loop: Reflected Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 45.249.212.35 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 09 Dec 2019 02:07:10 -0000 =E5=9C=A8 2019/12/6 21:50, Peter Maydell =E5=86=99=E9=81=93: > On Sat, 30 Nov 2019 at 03:47, Guoheyi wrote: >> Hi Peter, Igor, >> >> I couldn't find these 2 patches in the latest tree. Could you help to >> merge them? > In future I recommend pinging unapplied patches with a shorter > delay than nine months :-) Tha's really a long time... > In QEMU's process, unless somebody > has specifically said they've picked up the patch, it still > "belongs" to the submitter to chase if it hasn't been > applied. In this case I simply didn't see Igor's request > that I take it -- the chances of me actually reading any > particular list email even if it's cc'd to me are not good. One of the reasons that I didn't check it earlier is that we don't=20 really use PCI SHPC in our production version, for Linux ITS driver can=20 only allocate a fixed range of MSI interrupts for a PCI-bridge during=20 initialization, so a later plugged-in PCI device may not be able to get=20 enough MSI interrupts and then fall back to legacy INTx. However, I=20 think it is still better to let guest OS make the decision. > > I tried applying them to target-arm.next but unfortunately > they break 'make check': > > TEST check-qtest-aarch64: tests/bios-tables-test > acpi-test: Warning! DSDT binary file mismatch. Actual > [aml:/tmp/aml-4IELC0], Expected [aml:tests/data/acpi/virt/DSDT]. > acpi-test: Warning! DSDT mismatch. Actual [asl:/tmp/asl-AOELC0.dsl, > aml:/tmp/aml-4IELC0], Expected [asl:/tmp/asl-XL7KC0.dsl, > aml:tests/data/acpi/virt/DSDT]. > ** > ERROR:/home/petmay01/linaro/qemu-from-laptop/qemu/tests/bios-tables-tes= t.c:477:test_acpi_asl: > assertion failed: (all_tables_match) > ERROR - Bail out! > ERROR:/home/petmay01/linaro/qemu-from-laptop/qemu/tests/bios-tables-tes= t.c:477:test_acpi_asl: > assertion failed: (all_tables_match) > Aborted (core dumped) > /home/petmay01/linaro/qemu-from-laptop/qemu/tests/Makefile.include:918: > recipe for target 'check-qtest-aarch64' failed > > Could you fix and resubmit, please? Sure. Thanks, Heyi > > thanks > -- PMM > > . From MAILER-DAEMON Sun Dec 08 23:45:24 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1ieAvD-00010V-U0 for mharc-qemu-arm@gnu.org; Sun, 08 Dec 2019 23:45:23 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:44970) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ie8ZA-0001v1-8z for qemu-arm@nongnu.org; Sun, 08 Dec 2019 21:14:30 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ie8Z8-0006ob-Qm for qemu-arm@nongnu.org; Sun, 08 Dec 2019 21:14:28 -0500 Received: from szxga03-in.huawei.com ([45.249.212.189]:2049 helo=huawei.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1ie8Z8-0006dy-FO; Sun, 08 Dec 2019 21:14:26 -0500 Received: from DGGEMM402-HUB.china.huawei.com (unknown [172.30.72.57]) by Forcepoint Email with ESMTP id 3AF42E8A1B330D45BAC3; Mon, 9 Dec 2019 10:14:15 +0800 (CST) Received: from DGGEMM526-MBX.china.huawei.com ([169.254.8.101]) by DGGEMM402-HUB.china.huawei.com ([10.3.20.210]) with mapi id 14.03.0439.000; Mon, 9 Dec 2019 10:14:09 +0800 From: "Zengtao (B)" To: Andrew Jones , "qemu-devel@nongnu.org" , "qemu-arm@nongnu.org" CC: "wei@redhat.com" , "peter.maydell@linaro.org" , "eric.auger@redhat.com" , "imammedo@redhat.com" , "xuwei (O)" , huangdaode Subject: RE: [Qemu-devel] [RFC PATCH 0/6] hw/arm/virt: Introduce cpu topology support Thread-Topic: [Qemu-devel] [RFC PATCH 0/6] hw/arm/virt: Introduce cpu topology support Thread-Index: AdQTlaRpUFkm+EncK0mrDnlTRz6dtGan2sPQ Date: Mon, 9 Dec 2019 02:14:09 +0000 Message-ID: <678F3D1BB717D949B966B68EAEB446ED3405A26F@dggemm526-mbx.china.huawei.com> References: <20180704124923.32483-1-drjones@redhat.com> In-Reply-To: <20180704124923.32483-1-drjones@redhat.com> Accept-Language: zh-CN, en-US Content-Language: zh-CN X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [10.74.221.187] Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 MIME-Version: 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by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ieCgy-0004bJ-AZ for qemu-arm@nongnu.org; Mon, 09 Dec 2019 01:38:49 -0500 Received: from szxga07-in.huawei.com ([45.249.212.35]:60986 helo=huawei.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1ieCgx-0004aK-V8; Mon, 09 Dec 2019 01:38:48 -0500 Received: from DGGEMS413-HUB.china.huawei.com (unknown [172.30.72.60]) by Forcepoint Email with ESMTP id A3CBF6D634ECE13C9D14; Mon, 9 Dec 2019 14:38:42 +0800 (CST) Received: from linux-XCyijm.huawei.com (10.175.104.212) by DGGEMS413-HUB.china.huawei.com (10.3.19.213) with Microsoft SMTP Server id 14.3.439.0; Mon, 9 Dec 2019 14:38:33 +0800 From: Heyi Guo To: , CC: , Heyi Guo , Shannon Zhao , Peter Maydell , "Michael S. Tsirkin" , Igor Mammedov Subject: [PATCH v6 0/2] arm/acpi: simplify aml code and enable SHPC Date: Mon, 9 Dec 2019 14:37:17 +0800 Message-ID: <20191209063719.23086-1-guoheyi@huawei.com> X-Mailer: git-send-email 2.19.1 MIME-Version: 1.0 Content-Type: text/plain X-Originating-IP: [10.175.104.212] X-CFilter-Loop: Reflected Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 45.249.212.35 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 09 Dec 2019 06:38:50 -0000 After the introduction of generic PCIe root port and PCIe-PCI bridge, we = will also have SHPC controller on ARM, and we don't support ACPI hot plug, so = just enable SHPC native hot plug. Igor also spotted the store operation outside of bit and/or is not necess= ary, so simply the code at first. v6: - Fix "make check" errors by updating tests/data/acpi/virt/DSDT*. v5: - Refine commit message of patch 1/2 v4: - Improve the code indention. Cc: Shannon Zhao Cc: Peter Maydell Cc: "Michael S. Tsirkin" Cc: Igor Mammedov Heyi Guo (2): hw/arm/acpi: simplify AML bit and/or statement hw/arm/acpi: enable SHPC native hot plug hw/arm/virt-acpi-build.c | 21 +++++++++++++-------- tests/data/acpi/virt/DSDT | Bin 18470 -> 18462 bytes tests/data/acpi/virt/DSDT.memhp | Bin 19807 -> 19799 bytes tests/data/acpi/virt/DSDT.numamem | Bin 18470 -> 18462 bytes 4 files changed, 13 insertions(+), 8 deletions(-) --=20 2.19.1 From MAILER-DAEMON Mon Dec 09 01:38:52 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1ieCh2-0005LU-DR for mharc-qemu-arm@gnu.org; Mon, 09 Dec 2019 01:38:52 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:36116) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ieCgz-0005KV-Ky for qemu-arm@nongnu.org; Mon, 09 Dec 2019 01:38:50 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ieCgy-0004bS-B2 for qemu-arm@nongnu.org; Mon, 09 Dec 2019 01:38:49 -0500 Received: from szxga07-in.huawei.com ([45.249.212.35]:60988 helo=huawei.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1ieCgx-0004aM-Vu; Mon, 09 Dec 2019 01:38:48 -0500 Received: from DGGEMS413-HUB.china.huawei.com (unknown [172.30.72.60]) by Forcepoint Email with ESMTP id A8D9E3A6E32C72004617; Mon, 9 Dec 2019 14:38:42 +0800 (CST) Received: from linux-XCyijm.huawei.com (10.175.104.212) by DGGEMS413-HUB.china.huawei.com (10.3.19.213) with Microsoft SMTP Server id 14.3.439.0; Mon, 9 Dec 2019 14:38:34 +0800 From: Heyi Guo To: , CC: , Heyi Guo , Shannon Zhao , Peter Maydell , "Michael S. Tsirkin" , Igor Mammedov Subject: [PATCH v6 2/2] hw/arm/acpi: enable SHPC native hot plug Date: Mon, 9 Dec 2019 14:37:19 +0800 Message-ID: <20191209063719.23086-3-guoheyi@huawei.com> X-Mailer: git-send-email 2.19.1 In-Reply-To: <20191209063719.23086-1-guoheyi@huawei.com> References: <20191209063719.23086-1-guoheyi@huawei.com> MIME-Version: 1.0 Content-Type: text/plain X-Originating-IP: [10.175.104.212] X-CFilter-Loop: Reflected Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 45.249.212.35 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 09 Dec 2019 06:38:50 -0000 After the introduction of generic PCIe root port and PCIe-PCI bridge, we will also have SHPC controller on ARM, so just enable SHPC native hot plug. Also update tests/data/acpi/virt/DSDT* to pass "make check". Cc: Shannon Zhao Cc: Peter Maydell Cc: "Michael S. Tsirkin" Cc: Igor Mammedov Reviewed-by: Michael S. Tsirkin Reviewed-by: Igor Mammedov Signed-off-by: Heyi Guo --- hw/arm/virt-acpi-build.c | 7 ++++++- tests/data/acpi/virt/DSDT | Bin 18462 -> 18462 bytes tests/data/acpi/virt/DSDT.memhp | Bin 19799 -> 19799 bytes tests/data/acpi/virt/DSDT.numamem | Bin 18462 -> 18462 bytes 4 files changed, 6 insertions(+), 1 deletion(-) diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c index 51b293e0a1..bd5f771e9b 100644 --- a/hw/arm/virt-acpi-build.c +++ b/hw/arm/virt-acpi-build.c @@ -267,7 +267,12 @@ static void acpi_dsdt_add_pci(Aml *scope, const MemM= apEntry *memmap, aml_create_dword_field(aml_arg(3), aml_int(8), "CDW3")); aml_append(ifctx, aml_store(aml_name("CDW2"), aml_name("SUPP"))); aml_append(ifctx, aml_store(aml_name("CDW3"), aml_name("CTRL"))); - aml_append(ifctx, aml_and(aml_name("CTRL"), aml_int(0x1D), + + /* + * Allow OS control for all 5 features: + * PCIeHotplug SHPCHotplug PME AER PCIeCapability. + */ + aml_append(ifctx, aml_and(aml_name("CTRL"), aml_int(0x1F), aml_name("CTRL"))); =20 ifctx1 =3D aml_if(aml_lnot(aml_equal(aml_arg(1), aml_int(0x1)))); diff --git a/tests/data/acpi/virt/DSDT b/tests/data/acpi/virt/DSDT index 05bcfc8a912f58f266aa906563ea01c24906717e..d0f3afeb134fdf1c11f64cd06= dbcdd30be603b80 100644 GIT binary patch delta 28 kcmbO?fpOjhMlP3Nmk>D*1_q{tja=3D*8809zbbW3Ff0C~9xM*si- delta 28 kcmbO?fpOjhMlP3Nmk>D*1_q|2ja=3D*87-cu_bW3Ff0C~j-M*si- diff --git a/tests/data/acpi/virt/DSDT.memhp b/tests/data/acpi/virt/DSDT.= memhp index c041a910fdf272cb89263bb636239ae3a5e1708d..41ccc6431b917252bcbaac86c= 33b340c796be5ce 100644 GIT binary patch delta 28 kcmcaUi}Cs_MlP3NmymE@1_mbija=3D*8809zbbeqQp0Eq|*2mk;8 delta 28 kcmcaUi}Cs_MlP3NmymE@1_ma@ja=3D*87-cu_beqQp0ErX{2mk;8 diff --git a/tests/data/acpi/virt/DSDT.numamem b/tests/data/acpi/virt/DSD= T.numamem index 05bcfc8a912f58f266aa906563ea01c24906717e..d0f3afeb134fdf1c11f64cd06= dbcdd30be603b80 100644 GIT binary patch delta 28 kcmbO?fpOjhMlP3Nmk>D*1_q{tja=3D*8809zbbW3Ff0C~9xM*si- delta 28 kcmbO?fpOjhMlP3Nmk>D*1_q|2ja=3D*87-cu_bW3Ff0C~j-M*si- --=20 2.19.1 From MAILER-DAEMON Mon Dec 09 01:38:54 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1ieCh4-0005OR-Id for mharc-qemu-arm@gnu.org; Mon, 09 Dec 2019 01:38:54 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:36114) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ieCgz-0005KU-Ib for qemu-arm@nongnu.org; Mon, 09 Dec 2019 01:38:50 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ieCgy-0004bC-5K for qemu-arm@nongnu.org; Mon, 09 Dec 2019 01:38:49 -0500 Received: from szxga07-in.huawei.com ([45.249.212.35]:60990 helo=huawei.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1ieCgx-0004aL-Pe; Mon, 09 Dec 2019 01:38:48 -0500 Received: from DGGEMS413-HUB.china.huawei.com (unknown [172.30.72.60]) by Forcepoint Email with ESMTP id AE692E26B1E13D5F2F62; Mon, 9 Dec 2019 14:38:42 +0800 (CST) Received: from linux-XCyijm.huawei.com (10.175.104.212) by DGGEMS413-HUB.china.huawei.com (10.3.19.213) with Microsoft SMTP Server id 14.3.439.0; Mon, 9 Dec 2019 14:38:34 +0800 From: Heyi Guo To: , CC: , Heyi Guo , Shannon Zhao , Peter Maydell , "Michael S. Tsirkin" , Igor Mammedov Subject: [PATCH v6 1/2] hw/arm/acpi: simplify AML bit and/or statement Date: Mon, 9 Dec 2019 14:37:18 +0800 Message-ID: <20191209063719.23086-2-guoheyi@huawei.com> X-Mailer: git-send-email 2.19.1 In-Reply-To: <20191209063719.23086-1-guoheyi@huawei.com> References: <20191209063719.23086-1-guoheyi@huawei.com> MIME-Version: 1.0 Content-Type: text/plain X-Originating-IP: [10.175.104.212] X-CFilter-Loop: Reflected Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 45.249.212.35 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 09 Dec 2019 06:38:50 -0000 The last argument of AML bit and/or statement is the target variable, so we don't need to use a NULL target and then an additional store operation; using just aml_and() or aml_or() statement is enough. Also update tests/data/acpi/virt/DSDT* to pass "make check". Cc: Shannon Zhao Cc: Peter Maydell Cc: "Michael S. Tsirkin" Cc: Igor Mammedov Suggested-by: Igor Mammedov Reviewed-by: Igor Mammedov Signed-off-by: Heyi Guo --- hw/arm/virt-acpi-build.c | 16 ++++++++-------- tests/data/acpi/virt/DSDT | Bin 18470 -> 18462 bytes tests/data/acpi/virt/DSDT.memhp | Bin 19807 -> 19799 bytes tests/data/acpi/virt/DSDT.numamem | Bin 18470 -> 18462 bytes 4 files changed, 8 insertions(+), 8 deletions(-) diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c index 4cd50175e0..51b293e0a1 100644 --- a/hw/arm/virt-acpi-build.c +++ b/hw/arm/virt-acpi-build.c @@ -267,17 +267,17 @@ static void acpi_dsdt_add_pci(Aml *scope, const Mem= MapEntry *memmap, aml_create_dword_field(aml_arg(3), aml_int(8), "CDW3")); aml_append(ifctx, aml_store(aml_name("CDW2"), aml_name("SUPP"))); aml_append(ifctx, aml_store(aml_name("CDW3"), aml_name("CTRL"))); - aml_append(ifctx, aml_store(aml_and(aml_name("CTRL"), aml_int(0x1D),= NULL), - aml_name("CTRL"))); + aml_append(ifctx, aml_and(aml_name("CTRL"), aml_int(0x1D), + aml_name("CTRL"))); =20 ifctx1 =3D aml_if(aml_lnot(aml_equal(aml_arg(1), aml_int(0x1)))); - aml_append(ifctx1, aml_store(aml_or(aml_name("CDW1"), aml_int(0x08),= NULL), - aml_name("CDW1"))); + aml_append(ifctx1, aml_or(aml_name("CDW1"), aml_int(0x08), + aml_name("CDW1"))); aml_append(ifctx, ifctx1); =20 ifctx1 =3D aml_if(aml_lnot(aml_equal(aml_name("CDW3"), aml_name("CTR= L")))); - aml_append(ifctx1, aml_store(aml_or(aml_name("CDW1"), aml_int(0x10),= NULL), - aml_name("CDW1"))); + aml_append(ifctx1, aml_or(aml_name("CDW1"), aml_int(0x10), + aml_name("CDW1"))); aml_append(ifctx, ifctx1); =20 aml_append(ifctx, aml_store(aml_name("CTRL"), aml_name("CDW3"))); @@ -285,8 +285,8 @@ static void acpi_dsdt_add_pci(Aml *scope, const MemMa= pEntry *memmap, aml_append(method, ifctx); =20 elsectx =3D aml_else(); - aml_append(elsectx, aml_store(aml_or(aml_name("CDW1"), aml_int(4), N= ULL), - aml_name("CDW1"))); + aml_append(elsectx, aml_or(aml_name("CDW1"), aml_int(4), + aml_name("CDW1"))); aml_append(elsectx, aml_return(aml_arg(3))); aml_append(method, elsectx); aml_append(dev, method); diff --git a/tests/data/acpi/virt/DSDT b/tests/data/acpi/virt/DSDT index bce76e3d23e99e6c5ef64c94c770282dd30ecdd0..05bcfc8a912f58f266aa90656= 3ea01c24906717e 100644 GIT binary patch delta 133 zcmZ2BfpOjhMlP3Nmk>D*1_q|2iCof5o%I{lJ2{y;?{412x!p#mARjJS5V=3D5L(&S9WT970c2Uv;Nq{%?q7$gZ1761tsfcPNsCD{x4 MAmS{W8QoPG0j8@bzW@LL delta 141 zcmbO?fpOUcMlP3Nmk>1%1_q`n6S<_B8XGpMcXBc{-rKy1bGwazA7{LOuro_nHiNTE zxZwi7$(3%F{sq;}AwfP|vJ4<! diff --git a/tests/data/acpi/virt/DSDT.memhp b/tests/data/acpi/virt/DSDT.= memhp index b4b153fcdc30d211237fced6be1e99d3500bd276..c041a910fdf272cb89263bb63= 6239ae3a5e1708d 100644 GIT binary patch delta 132 zcmcaVi}Cs_MlP3NmymE@1_ma@iCof*O&is^IGH-{Zr;SX-A2HTGu}VgnWZb6!PzC; zaDm6_#p8m*$ep~ L;w+mP-Q(B*s{AMU delta 140 zcmcaUi}C&}MlP3Nmymd01_maViCof*T^rT9IGGynZQjJW-A2HVGu}VgnWZb6!PzC; zaDm_CN;gaYf@D*1_q|2iCof5o%I{lJ2{y;?{412x!p#mARjJS5V=3D5L(&S9WT970c2Uv;Nq{%?q7$gZ1761tsfcPNsCD{x4 MAmS{W8QoPG0j8@bzW@LL delta 141 zcmbO?fpOUcMlP3Nmk>1%1_q`n6S<_B8XGpMcXBc{-rKy1bGwazA7{LOuro_nHiNTE zxZwi7$(3%F{sq;}AwfP|vJ4<! --=20 2.19.1 From MAILER-DAEMON Mon Dec 09 04:03:23 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1ieEwt-000675-Mi for mharc-qemu-arm@gnu.org; Mon, 09 Dec 2019 04:03:23 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:42718) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ieEwq-00063a-B3 for qemu-arm@nongnu.org; Mon, 09 Dec 2019 04:03:22 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ieEwn-0001Ie-Qu for qemu-arm@nongnu.org; Mon, 09 Dec 2019 04:03:20 -0500 Received: from us-smtp-delivery-1.mimecast.com ([205.139.110.120]:58220 helo=us-smtp-1.mimecast.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1ieEwn-0001Hr-Kz for qemu-arm@nongnu.org; Mon, 09 Dec 2019 04:03:17 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1575882197; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding; bh=z3pUryutP47DJBp6MpKLuTkGvVAsdwEI/VzhLyro1Js=; b=NAN2KEtdeQzMbD2QsQafykZP2tARuF/cPyEYZ9kNqyfVCL6nObHVLPpxl7uB19Q3c/Je0h i5l/6D4Tm4a/XDM/CEh3qnydatOEjb7TmNj0s81PKLHMIpnmgkiyy7ftaVK4F9SgYpYCAE bNf2QnZE4BKrOA4I529V1TtlFu5Lqog= Received: from mimecast-mx01.redhat.com (mimecast-mx01.redhat.com [209.132.183.4]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-376-o89xQ_UbMGaL8URnCxKhCA-1; Mon, 09 Dec 2019 04:03:15 -0500 Received: from smtp.corp.redhat.com (int-mx02.intmail.prod.int.phx2.redhat.com [10.5.11.12]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx01.redhat.com (Postfix) with ESMTPS id B07E8DB65; Mon, 9 Dec 2019 09:03:14 +0000 (UTC) Received: from x1w.redhat.com (ovpn-205-142.brq.redhat.com [10.40.205.142]) by smtp.corp.redhat.com (Postfix) with ESMTPS id 655B960BEC; Mon, 9 Dec 2019 09:03:09 +0000 (UTC) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Luc Michel , Peter Maydell , qemu-arm@nongnu.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH] hw/arm/virt: Simplify by moving the gic in the machine state Date: Mon, 9 Dec 2019 10:03:06 +0100 Message-Id: <20191209090306.20433-1-philmd@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.79 on 10.5.11.12 X-MC-Unique: o89xQ_UbMGaL8URnCxKhCA-1 X-Mimecast-Spam-Score: 0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 205.139.110.120 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 09 Dec 2019 09:03:22 -0000 Make the gic a field in the machine state, and instead of filling an array of qemu_irq and passing it around, directly call qdev_get_gpio_in() on the gic field. Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- include/hw/arm/virt.h | 1 + hw/arm/virt.c | 109 +++++++++++++++++++++--------------------- 2 files changed, 55 insertions(+), 55 deletions(-) diff --git a/include/hw/arm/virt.h b/include/hw/arm/virt.h index 0b41083e9d..38f0c33c77 100644 --- a/include/hw/arm/virt.h +++ b/include/hw/arm/virt.h @@ -136,6 +136,7 @@ typedef struct { uint32_t iommu_phandle; int psci_conduit; hwaddr highest_gpa; + DeviceState *gic; DeviceState *acpi_dev; Notifier powerdown_notifier; } VirtMachineState; diff --git a/hw/arm/virt.c b/hw/arm/virt.c index d4bedc2607..67d031c051 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -531,7 +531,7 @@ static void fdt_add_pmu_nodes(const VirtMachineState *v= ms) } } =20 -static inline DeviceState *create_acpi_ged(VirtMachineState *vms, qemu_irq= *pic) +static inline DeviceState *create_acpi_ged(VirtMachineState *vms) { DeviceState *dev; MachineState *ms =3D MACHINE(vms); @@ -547,14 +547,14 @@ static inline DeviceState *create_acpi_ged(VirtMachin= eState *vms, qemu_irq *pic) =20 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, vms->memmap[VIRT_ACPI_GED].bas= e); sysbus_mmio_map(SYS_BUS_DEVICE(dev), 1, vms->memmap[VIRT_PCDIMM_ACPI].= base); - sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, pic[irq]); + sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, qdev_get_gpio_in(vms->gic, = irq)); =20 qdev_init_nofail(dev); =20 return dev; } =20 -static void create_its(VirtMachineState *vms, DeviceState *gicdev) +static void create_its(VirtMachineState *vms) { const char *itsclass =3D its_class_name(); DeviceState *dev; @@ -566,7 +566,7 @@ static void create_its(VirtMachineState *vms, DeviceSta= te *gicdev) =20 dev =3D qdev_create(NULL, itsclass); =20 - object_property_set_link(OBJECT(dev), OBJECT(gicdev), "parent-gicv3", + object_property_set_link(OBJECT(dev), OBJECT(vms->gic), "parent-gicv3"= , &error_abort); qdev_init_nofail(dev); sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, vms->memmap[VIRT_GIC_ITS].base= ); @@ -574,7 +574,7 @@ static void create_its(VirtMachineState *vms, DeviceSta= te *gicdev) fdt_add_its_gic_node(vms); } =20 -static void create_v2m(VirtMachineState *vms, qemu_irq *pic) +static void create_v2m(VirtMachineState *vms) { int i; int irq =3D vms->irqmap[VIRT_GIC_V2M]; @@ -587,17 +587,17 @@ static void create_v2m(VirtMachineState *vms, qemu_ir= q *pic) qdev_init_nofail(dev); =20 for (i =3D 0; i < NUM_GICV2M_SPIS; i++) { - sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, pic[irq + i]); + sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, + qdev_get_gpio_in(vms->gic, irq + i)); } =20 fdt_add_v2m_gic_node(vms); } =20 -static void create_gic(VirtMachineState *vms, qemu_irq *pic) +static void create_gic(VirtMachineState *vms) { MachineState *ms =3D MACHINE(vms); /* We create a standalone GIC */ - DeviceState *gicdev; SysBusDevice *gicbusdev; const char *gictype; int type =3D vms->gic_version, i; @@ -606,15 +606,15 @@ static void create_gic(VirtMachineState *vms, qemu_ir= q *pic) =20 gictype =3D (type =3D=3D 3) ? gicv3_class_name() : gic_class_name(); =20 - gicdev =3D qdev_create(NULL, gictype); - qdev_prop_set_uint32(gicdev, "revision", type); - qdev_prop_set_uint32(gicdev, "num-cpu", smp_cpus); + vms->gic =3D qdev_create(NULL, gictype); + qdev_prop_set_uint32(vms->gic, "revision", type); + qdev_prop_set_uint32(vms->gic, "num-cpu", smp_cpus); /* Note that the num-irq property counts both internal and external * interrupts; there are always 32 of the former (mandated by GIC spec= ). */ - qdev_prop_set_uint32(gicdev, "num-irq", NUM_IRQS + 32); + qdev_prop_set_uint32(vms->gic, "num-irq", NUM_IRQS + 32); if (!kvm_irqchip_in_kernel()) { - qdev_prop_set_bit(gicdev, "has-security-extensions", vms->secure); + qdev_prop_set_bit(vms->gic, "has-security-extensions", vms->secure= ); } =20 if (type =3D=3D 3) { @@ -624,25 +624,25 @@ static void create_gic(VirtMachineState *vms, qemu_ir= q *pic) =20 nb_redist_regions =3D virt_gicv3_redist_region_count(vms); =20 - qdev_prop_set_uint32(gicdev, "len-redist-region-count", + qdev_prop_set_uint32(vms->gic, "len-redist-region-count", nb_redist_regions); - qdev_prop_set_uint32(gicdev, "redist-region-count[0]", redist0_cou= nt); + qdev_prop_set_uint32(vms->gic, "redist-region-count[0]", redist0_c= ount); =20 if (nb_redist_regions =3D=3D 2) { uint32_t redist1_capacity =3D vms->memmap[VIRT_HIGH_GIC_REDIST2].size / GICV3_REDIST= _SIZE; =20 - qdev_prop_set_uint32(gicdev, "redist-region-count[1]", + qdev_prop_set_uint32(vms->gic, "redist-region-count[1]", MIN(smp_cpus - redist0_count, redist1_capacity)); } } else { if (!kvm_irqchip_in_kernel()) { - qdev_prop_set_bit(gicdev, "has-virtualization-extensions", + qdev_prop_set_bit(vms->gic, "has-virtualization-extensions", vms->virt); } } - qdev_init_nofail(gicdev); - gicbusdev =3D SYS_BUS_DEVICE(gicdev); + qdev_init_nofail(vms->gic); + gicbusdev =3D SYS_BUS_DEVICE(vms->gic); sysbus_mmio_map(gicbusdev, 0, vms->memmap[VIRT_GIC_DIST].base); if (type =3D=3D 3) { sysbus_mmio_map(gicbusdev, 1, vms->memmap[VIRT_GIC_REDIST].base); @@ -678,23 +678,23 @@ static void create_gic(VirtMachineState *vms, qemu_ir= q *pic) =20 for (irq =3D 0; irq < ARRAY_SIZE(timer_irq); irq++) { qdev_connect_gpio_out(cpudev, irq, - qdev_get_gpio_in(gicdev, + qdev_get_gpio_in(vms->gic, ppibase + timer_irq[irq= ])); } =20 if (type =3D=3D 3) { - qemu_irq irq =3D qdev_get_gpio_in(gicdev, + qemu_irq irq =3D qdev_get_gpio_in(vms->gic, ppibase + ARCH_GIC_MAINT_IRQ); qdev_connect_gpio_out_named(cpudev, "gicv3-maintenance-interru= pt", 0, irq); } else if (vms->virt) { - qemu_irq irq =3D qdev_get_gpio_in(gicdev, + qemu_irq irq =3D qdev_get_gpio_in(vms->gic, ppibase + ARCH_GIC_MAINT_IRQ); sysbus_connect_irq(gicbusdev, i + 4 * smp_cpus, irq); } =20 qdev_connect_gpio_out_named(cpudev, "pmu-interrupt", 0, - qdev_get_gpio_in(gicdev, ppibase + qdev_get_gpio_in(vms->gic, ppibase + VIRTUAL_PMU_IRQ)); =20 sysbus_connect_irq(gicbusdev, i, qdev_get_gpio_in(cpudev, ARM_CPU_= IRQ)); @@ -706,20 +706,16 @@ static void create_gic(VirtMachineState *vms, qemu_ir= q *pic) qdev_get_gpio_in(cpudev, ARM_CPU_VFIQ)); } =20 - for (i =3D 0; i < NUM_IRQS; i++) { - pic[i] =3D qdev_get_gpio_in(gicdev, i); - } - fdt_add_gic_node(vms); =20 if (type =3D=3D 3 && vms->its) { - create_its(vms, gicdev); + create_its(vms); } else if (type =3D=3D 2) { - create_v2m(vms, pic); + create_v2m(vms); } } =20 -static void create_uart(const VirtMachineState *vms, qemu_irq *pic, int ua= rt, +static void create_uart(const VirtMachineState *vms, int uart, MemoryRegion *mem, Chardev *chr) { char *nodename; @@ -735,7 +731,7 @@ static void create_uart(const VirtMachineState *vms, qe= mu_irq *pic, int uart, qdev_init_nofail(dev); memory_region_add_subregion(mem, base, sysbus_mmio_get_region(s, 0)); - sysbus_connect_irq(s, 0, pic[irq]); + sysbus_connect_irq(s, 0, qdev_get_gpio_in(vms->gic, irq)); =20 nodename =3D g_strdup_printf("/pl011@%" PRIx64, base); qemu_fdt_add_subnode(vms->fdt, nodename); @@ -767,7 +763,7 @@ static void create_uart(const VirtMachineState *vms, qe= mu_irq *pic, int uart, g_free(nodename); } =20 -static void create_rtc(const VirtMachineState *vms, qemu_irq *pic) +static void create_rtc(const VirtMachineState *vms) { char *nodename; hwaddr base =3D vms->memmap[VIRT_RTC].base; @@ -775,7 +771,7 @@ static void create_rtc(const VirtMachineState *vms, qem= u_irq *pic) int irq =3D vms->irqmap[VIRT_RTC]; const char compat[] =3D "arm,pl031\0arm,primecell"; =20 - sysbus_create_simple("pl031", base, pic[irq]); + sysbus_create_simple("pl031", base, qdev_get_gpio_in(vms->gic, irq)); =20 nodename =3D g_strdup_printf("/pl031@%" PRIx64, base); qemu_fdt_add_subnode(vms->fdt, nodename); @@ -803,7 +799,7 @@ static void virt_powerdown_req(Notifier *n, void *opaqu= e) } } =20 -static void create_gpio(const VirtMachineState *vms, qemu_irq *pic) +static void create_gpio(const VirtMachineState *vms) { char *nodename; DeviceState *pl061_dev; @@ -812,7 +808,8 @@ static void create_gpio(const VirtMachineState *vms, qe= mu_irq *pic) int irq =3D vms->irqmap[VIRT_GPIO]; const char compat[] =3D "arm,pl061\0arm,primecell"; =20 - pl061_dev =3D sysbus_create_simple("pl061", base, pic[irq]); + pl061_dev =3D sysbus_create_simple("pl061", base, + qdev_get_gpio_in(vms->gic, irq)); =20 uint32_t phandle =3D qemu_fdt_alloc_phandle(vms->fdt); nodename =3D g_strdup_printf("/pl061@%" PRIx64, base); @@ -846,7 +843,7 @@ static void create_gpio(const VirtMachineState *vms, qe= mu_irq *pic) g_free(nodename); } =20 -static void create_virtio_devices(const VirtMachineState *vms, qemu_irq *p= ic) +static void create_virtio_devices(const VirtMachineState *vms) { int i; hwaddr size =3D vms->memmap[VIRT_MMIO].size; @@ -882,7 +879,8 @@ static void create_virtio_devices(const VirtMachineStat= e *vms, qemu_irq *pic) int irq =3D vms->irqmap[VIRT_MMIO] + i; hwaddr base =3D vms->memmap[VIRT_MMIO].base + i * size; =20 - sysbus_create_simple("virtio-mmio", base, pic[irq]); + sysbus_create_simple("virtio-mmio", base, + qdev_get_gpio_in(vms->gic, irq)); } =20 /* We add dtb nodes in reverse order so that they appear in the finish= ed @@ -1131,7 +1129,7 @@ static void create_pcie_irq_map(const VirtMachineStat= e *vms, 0x7 /* PCI irq */); } =20 -static void create_smmu(const VirtMachineState *vms, qemu_irq *pic, +static void create_smmu(const VirtMachineState *vms, PCIBus *bus) { char *node; @@ -1154,7 +1152,8 @@ static void create_smmu(const VirtMachineState *vms, = qemu_irq *pic, qdev_init_nofail(dev); sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base); for (i =3D 0; i < NUM_SMMU_IRQS; i++) { - sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, pic[irq + i]); + sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, + qdev_get_gpio_in(vms->gic, irq + i)); } =20 node =3D g_strdup_printf("/smmuv3@%" PRIx64, base); @@ -1181,7 +1180,7 @@ static void create_smmu(const VirtMachineState *vms, = qemu_irq *pic, g_free(node); } =20 -static void create_pcie(VirtMachineState *vms, qemu_irq *pic) +static void create_pcie(VirtMachineState *vms) { hwaddr base_mmio =3D vms->memmap[VIRT_PCIE_MMIO].base; hwaddr size_mmio =3D vms->memmap[VIRT_PCIE_MMIO].size; @@ -1241,7 +1240,8 @@ static void create_pcie(VirtMachineState *vms, qemu_i= rq *pic) sysbus_mmio_map(SYS_BUS_DEVICE(dev), 2, base_pio); =20 for (i =3D 0; i < GPEX_NUM_IRQS; i++) { - sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, pic[irq + i]); + sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, + qdev_get_gpio_in(vms->gic, irq + i)); gpex_set_irq_num(GPEX_HOST(dev), i, irq + i); } =20 @@ -1301,7 +1301,7 @@ static void create_pcie(VirtMachineState *vms, qemu_i= rq *pic) if (vms->iommu) { vms->iommu_phandle =3D qemu_fdt_alloc_phandle(vms->fdt); =20 - create_smmu(vms, pic, pci->bus); + create_smmu(vms, pci->bus); =20 qemu_fdt_setprop_cells(vms->fdt, nodename, "iommu-map", 0x0, vms->iommu_phandle, 0x0, 0x10000); @@ -1310,7 +1310,7 @@ static void create_pcie(VirtMachineState *vms, qemu_i= rq *pic) g_free(nodename); } =20 -static void create_platform_bus(VirtMachineState *vms, qemu_irq *pic) +static void create_platform_bus(VirtMachineState *vms) { DeviceState *dev; SysBusDevice *s; @@ -1326,8 +1326,8 @@ static void create_platform_bus(VirtMachineState *vms= , qemu_irq *pic) =20 s =3D SYS_BUS_DEVICE(dev); for (i =3D 0; i < PLATFORM_BUS_NUM_IRQS; i++) { - int irqn =3D vms->irqmap[VIRT_PLATFORM_BUS] + i; - sysbus_connect_irq(s, i, pic[irqn]); + int irq =3D vms->irqmap[VIRT_PLATFORM_BUS] + i; + sysbus_connect_irq(s, i, qdev_get_gpio_in(vms->gic, irq)); } =20 memory_region_add_subregion(sysmem, @@ -1509,7 +1509,6 @@ static void machvirt_init(MachineState *machine) VirtMachineClass *vmc =3D VIRT_MACHINE_GET_CLASS(machine); MachineClass *mc =3D MACHINE_GET_CLASS(machine); const CPUArchIdList *possible_cpus; - qemu_irq pic[NUM_IRQS]; MemoryRegion *sysmem =3D get_system_memory(); MemoryRegion *secure_sysmem =3D NULL; int n, virt_max_cpus; @@ -1712,27 +1711,27 @@ static void machvirt_init(MachineState *machine) =20 virt_flash_fdt(vms, sysmem, secure_sysmem ?: sysmem); =20 - create_gic(vms, pic); + create_gic(vms); =20 fdt_add_pmu_nodes(vms); =20 - create_uart(vms, pic, VIRT_UART, sysmem, serial_hd(0)); + create_uart(vms, VIRT_UART, sysmem, serial_hd(0)); =20 if (vms->secure) { create_secure_ram(vms, secure_sysmem); - create_uart(vms, pic, VIRT_SECURE_UART, secure_sysmem, serial_hd(1= )); + create_uart(vms, VIRT_SECURE_UART, secure_sysmem, serial_hd(1)); } =20 vms->highmem_ecam &=3D vms->highmem && (!firmware_loaded || aarch64); =20 - create_rtc(vms, pic); + create_rtc(vms); =20 - create_pcie(vms, pic); + create_pcie(vms); =20 if (has_ged && aarch64 && firmware_loaded && acpi_enabled) { - vms->acpi_dev =3D create_acpi_ged(vms, pic); + vms->acpi_dev =3D create_acpi_ged(vms); } else { - create_gpio(vms, pic); + create_gpio(vms); } =20 /* connect powerdown request */ @@ -1743,12 +1742,12 @@ static void machvirt_init(MachineState *machine) * (which will be automatically plugged in to the transports). If * no backend is created the transport will just sit harmlessly idle. */ - create_virtio_devices(vms, pic); + create_virtio_devices(vms); =20 vms->fw_cfg =3D create_fw_cfg(vms, &address_space_memory); rom_set_fw(vms->fw_cfg); =20 - create_platform_bus(vms, pic); + create_platform_bus(vms); =20 vms->bootinfo.ram_size =3D machine->ram_size; vms->bootinfo.nb_cpus =3D smp_cpus; --=20 2.21.0 From MAILER-DAEMON Mon Dec 09 04:14:16 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1ieF7Q-0005Wa-8h for mharc-qemu-arm@gnu.org; Mon, 09 Dec 2019 04:14:16 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:44522) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ieF7N-0005Qh-GW for qemu-arm@nongnu.org; Mon, 09 Dec 2019 04:14:14 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ieF7M-00006T-6C for qemu-arm@nongnu.org; Mon, 09 Dec 2019 04:14:13 -0500 Received: from us-smtp-2.mimecast.com ([205.139.110.61]:43582 helo=us-smtp-delivery-1.mimecast.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1ieF7M-00005x-1v for qemu-arm@nongnu.org; Mon, 09 Dec 2019 04:14:12 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1575882851; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=kg914zhVRWU/PXU4bqk0dhOqJTfDhMBjbVHa5VDvUIE=; b=BECOQpQtTqeYbiV/xvyi+fhz6yKDQ0y5ALkj+oNNuJRVYzUwZLMDyYSTSALPKp/qTdThtS DoCE6JSVy6C9bJ3RX/4zaOE3eCeRFgIN0jRgcCWoNE4+hTjNyrr/8/KIqlm+XxSOayHaI3 oXRo1+1yvA8aAmS/4Nq/KrnFkdxBu4w= Received: from mimecast-mx01.redhat.com (mimecast-mx01.redhat.com [209.132.183.4]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-314-X4inzE7gOh2EdYLqIXGvZQ-1; Mon, 09 Dec 2019 04:14:10 -0500 Received: from smtp.corp.redhat.com (int-mx07.intmail.prod.int.phx2.redhat.com [10.5.11.22]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx01.redhat.com (Postfix) with ESMTPS id 0DD22801E70; Mon, 9 Dec 2019 09:14:09 +0000 (UTC) Received: from [10.36.116.117] (ovpn-116-117.ams2.redhat.com [10.36.116.117]) by smtp.corp.redhat.com (Postfix) with ESMTPS id 2DE2610016E8; Mon, 9 Dec 2019 09:14:07 +0000 (UTC) Subject: Re: [PATCH 1/5] hw/arm/smmuv3: Apply address mask to linear strtab base address To: Simon Veith , qemu-devel@nongnu.org, qemu-arm@nongnu.org References: <1575467748-28898-1-git-send-email-sveith@amazon.de> <1575467748-28898-2-git-send-email-sveith@amazon.de> <0f01a30e-5b27-f97c-903a-a8a2a74a1cdd@redhat.com> <13be5c71-128a-0ae7-1af0-72b58b5958ab@amazon.de> From: Auger Eric Message-ID: Date: Mon, 9 Dec 2019 10:14:06 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101 Thunderbird/60.4.0 MIME-Version: 1.0 In-Reply-To: <13be5c71-128a-0ae7-1af0-72b58b5958ab@amazon.de> Content-Language: en-US X-Scanned-By: MIMEDefang 2.84 on 10.5.11.22 X-MC-Unique: X4inzE7gOh2EdYLqIXGvZQ-1 X-Mimecast-Spam-Score: 0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: 7bit X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 205.139.110.61 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 09 Dec 2019 09:14:15 -0000 Hi Simon, On 12/5/19 11:04 PM, Simon Veith wrote: > Hello Eric, > > On 05/12/2019 09:42, Auger Eric wrote: >> Not related to this patch but I noticed SMMU_BASE_ADDR_MASK should be >> 0xffffffffffc0 and not 0xffffffffffe0. I can fix it separately or if you >> respin, you may fix it as well? > > Good catch, thank you. I'll fix it in the next version. > > Looking at the upper end of that mask, it seems that we are currently masking out bits 48 through 63, rather than just 51 through 63. > The reference manual says that this should be done to match the system physical address size as given by SMMU_IDR5.OAS. Yes you're right. This should go up to 51 as per the field range definition. Spec says address bits and above this field range are treated as zero. > > We define SMMU_IDR5_OAS to be 4, which selects a physical address size of 44 bits (ref. section 6.3.6). I think the mask should therefore be 0xfffffffffc0 to clear bits 44 and above. Do you agree? bits beyond the OAS are RES0. The spec does not says those fields are treated as zero, as explicitly mentioned for bits > 51. Normally the guest should not set them to something != 0, this would be a programming error right? Guest is supposed to read the IDR5 and program accordingly? > > Ideally, we would derive this mask from our definition of SMMU_IDR5_OAS, but I'm not sure it's okay to stuff a call to oas2bits() into the SMMU_BASE_ADDR_MASK macro. Well I am not sure this is worth the candle. I am not sure we are obliged to enforce this. Thanks Eric > > Regards > Simon > > > > Amazon Development Center Germany GmbH > Krausenstr. 38 > 10117 Berlin > Geschaeftsfuehrung: Christian Schlaeger, Ralf Herbrich > Eingetragen am Amtsgericht Charlottenburg unter HRB 149173 B > Sitz: Berlin > Ust-ID: DE 289 237 879 > > From MAILER-DAEMON Mon Dec 09 04:23:35 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1ieFGQ-0001Pb-VV for mharc-qemu-arm@gnu.org; Mon, 09 Dec 2019 04:23:34 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:45838) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ieFGN-0001Om-3W for qemu-arm@nongnu.org; Mon, 09 Dec 2019 04:23:33 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ieFGK-0007Pr-Mc for qemu-arm@nongnu.org; Mon, 09 Dec 2019 04:23:30 -0500 Received: from beetle.greensocs.com ([5.135.226.135]:48406) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1ieFGK-0007P3-49; Mon, 09 Dec 2019 04:23:28 -0500 Received: from [172.16.11.100] (tiramisu.bar.greensocs.com [172.16.11.100]) by beetle.greensocs.com (Postfix) with ESMTPSA id A7BA996EF0; Mon, 9 Dec 2019 09:23:24 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=greensocs.com; s=mail; t=1575883404; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=D4MCkhDmZVnbeV6Br6p29eQegN9pT3eqhuL4ZzCQkJE=; b=OkakVgGacl9TlN9zMgXQrknuj36SGrvmPqvU3gsN0ZjPbhIJFVq/dGmFTTxptIW2yaisai oWTZHANBLwsaShdfX5AOgAhhT8w4IBh0E4kbQ6YetpBfH41XsWJ2Acq0Bmf/JQsNB9eqnr eW/j8J7LOxGEsxNRqQ24O8fGTpukv0U= Subject: Re: [PATCH] hw/arm/virt: Simplify by moving the gic in the machine state To: =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= , qemu-devel@nongnu.org Cc: Peter Maydell , qemu-arm@nongnu.org References: <20191209090306.20433-1-philmd@redhat.com> From: Luc Michel Message-ID: Date: Mon, 9 Dec 2019 10:23:23 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.2.2 MIME-Version: 1.0 In-Reply-To: <20191209090306.20433-1-philmd@redhat.com> Content-Type: text/plain; charset=utf-8 Content-Language: en-PH ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=greensocs.com; s=mail; t=1575883405; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=D4MCkhDmZVnbeV6Br6p29eQegN9pT3eqhuL4ZzCQkJE=; b=GbdlQg1f+6eOYO/d3wF+31JzcteQKuTlUgeQqBFLF/C++uh2N7XftsoUXZ47ndzvO8Jk5n Z6Ehpka2aYoN8iDX+Bxk2C4ONnsKxtsAXCLCrfhaeJL01Lin8XNvWCuzca6KRAFa5919U9 vka3B0sQuDHgX5sZOarQPeJPMYjknps= ARC-Seal: i=1; s=mail; d=greensocs.com; t=1575883405; a=rsa-sha256; cv=none; b=dML/jeFP271XmMpPMkXjeAfDrolBzz5vhIQ8/3+w/c02gDuO6+Texy+ObH6DKyVmsHJDbS 2+ukNsX2sxRs3xmNBtDgeH8/gOUfvccLTw9LNTgGESb3UE8cv57hru16gKCYnk11h1SbpB ldxwNyIqnp9PjnzBPEE2EqGn7v2nmY8= ARC-Authentication-Results: i=1; ORIGINATING; auth=pass smtp.auth=luc smtp.mailfrom=luc.michel@greensocs.com Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 5.135.226.135 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 09 Dec 2019 09:23:33 -0000 On 12/9/19 10:03 AM, Philippe Mathieu-Daud=C3=A9 wrote: > Make the gic a field in the machine state, and instead of filling > an array of qemu_irq and passing it around, directly call > qdev_get_gpio_in() on the gic field. >=20 > Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Luc Michel > --- > include/hw/arm/virt.h | 1 + > hw/arm/virt.c | 109 +++++++++++++++++++++--------------------- > 2 files changed, 55 insertions(+), 55 deletions(-) >=20 > diff --git a/include/hw/arm/virt.h b/include/hw/arm/virt.h > index 0b41083e9d..38f0c33c77 100644 > --- a/include/hw/arm/virt.h > +++ b/include/hw/arm/virt.h > @@ -136,6 +136,7 @@ typedef struct { > uint32_t iommu_phandle; > int psci_conduit; > hwaddr highest_gpa; > + DeviceState *gic; > DeviceState *acpi_dev; > Notifier powerdown_notifier; > } VirtMachineState; > diff --git a/hw/arm/virt.c b/hw/arm/virt.c > index d4bedc2607..67d031c051 100644 > --- a/hw/arm/virt.c > +++ b/hw/arm/virt.c > @@ -531,7 +531,7 @@ static void fdt_add_pmu_nodes(const VirtMachineStat= e *vms) > } > } > =20 > -static inline DeviceState *create_acpi_ged(VirtMachineState *vms, qemu= _irq *pic) > +static inline DeviceState *create_acpi_ged(VirtMachineState *vms) > { > DeviceState *dev; > MachineState *ms =3D MACHINE(vms); > @@ -547,14 +547,14 @@ static inline DeviceState *create_acpi_ged(VirtMa= chineState *vms, qemu_irq *pic) > =20 > sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, vms->memmap[VIRT_ACPI_GED]= .base); > sysbus_mmio_map(SYS_BUS_DEVICE(dev), 1, vms->memmap[VIRT_PCDIMM_AC= PI].base); > - sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, pic[irq]); > + sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, qdev_get_gpio_in(vms->g= ic, irq)); > =20 > qdev_init_nofail(dev); > =20 > return dev; > } > =20 > -static void create_its(VirtMachineState *vms, DeviceState *gicdev) > +static void create_its(VirtMachineState *vms) > { > const char *itsclass =3D its_class_name(); > DeviceState *dev; > @@ -566,7 +566,7 @@ static void create_its(VirtMachineState *vms, Devic= eState *gicdev) > =20 > dev =3D qdev_create(NULL, itsclass); > =20 > - object_property_set_link(OBJECT(dev), OBJECT(gicdev), "parent-gicv= 3", > + object_property_set_link(OBJECT(dev), OBJECT(vms->gic), "parent-gi= cv3", > &error_abort); > qdev_init_nofail(dev); > sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, vms->memmap[VIRT_GIC_ITS].= base); > @@ -574,7 +574,7 @@ static void create_its(VirtMachineState *vms, Devic= eState *gicdev) > fdt_add_its_gic_node(vms); > } > =20 > -static void create_v2m(VirtMachineState *vms, qemu_irq *pic) > +static void create_v2m(VirtMachineState *vms) > { > int i; > int irq =3D vms->irqmap[VIRT_GIC_V2M]; > @@ -587,17 +587,17 @@ static void create_v2m(VirtMachineState *vms, qem= u_irq *pic) > qdev_init_nofail(dev); > =20 > for (i =3D 0; i < NUM_GICV2M_SPIS; i++) { > - sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, pic[irq + i]); > + sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, > + qdev_get_gpio_in(vms->gic, irq + i)); > } > =20 > fdt_add_v2m_gic_node(vms); > } > =20 > -static void create_gic(VirtMachineState *vms, qemu_irq *pic) > +static void create_gic(VirtMachineState *vms) > { > MachineState *ms =3D MACHINE(vms); > /* We create a standalone GIC */ > - DeviceState *gicdev; > SysBusDevice *gicbusdev; > const char *gictype; > int type =3D vms->gic_version, i; > @@ -606,15 +606,15 @@ static void create_gic(VirtMachineState *vms, qem= u_irq *pic) > =20 > gictype =3D (type =3D=3D 3) ? gicv3_class_name() : gic_class_name(= ); > =20 > - gicdev =3D qdev_create(NULL, gictype); > - qdev_prop_set_uint32(gicdev, "revision", type); > - qdev_prop_set_uint32(gicdev, "num-cpu", smp_cpus); > + vms->gic =3D qdev_create(NULL, gictype); > + qdev_prop_set_uint32(vms->gic, "revision", type); > + qdev_prop_set_uint32(vms->gic, "num-cpu", smp_cpus); > /* Note that the num-irq property counts both internal and externa= l > * interrupts; there are always 32 of the former (mandated by GIC = spec). > */ > - qdev_prop_set_uint32(gicdev, "num-irq", NUM_IRQS + 32); > + qdev_prop_set_uint32(vms->gic, "num-irq", NUM_IRQS + 32); > if (!kvm_irqchip_in_kernel()) { > - qdev_prop_set_bit(gicdev, "has-security-extensions", vms->secu= re); > + qdev_prop_set_bit(vms->gic, "has-security-extensions", vms->se= cure); > } > =20 > if (type =3D=3D 3) { > @@ -624,25 +624,25 @@ static void create_gic(VirtMachineState *vms, qem= u_irq *pic) > =20 > nb_redist_regions =3D virt_gicv3_redist_region_count(vms); > =20 > - qdev_prop_set_uint32(gicdev, "len-redist-region-count", > + qdev_prop_set_uint32(vms->gic, "len-redist-region-count", > nb_redist_regions); > - qdev_prop_set_uint32(gicdev, "redist-region-count[0]", redist0= _count); > + qdev_prop_set_uint32(vms->gic, "redist-region-count[0]", redis= t0_count); > =20 > if (nb_redist_regions =3D=3D 2) { > uint32_t redist1_capacity =3D > vms->memmap[VIRT_HIGH_GIC_REDIST2].size / GICV3_RE= DIST_SIZE; > =20 > - qdev_prop_set_uint32(gicdev, "redist-region-count[1]", > + qdev_prop_set_uint32(vms->gic, "redist-region-count[1]", > MIN(smp_cpus - redist0_count, redist1_capacity)); > } > } else { > if (!kvm_irqchip_in_kernel()) { > - qdev_prop_set_bit(gicdev, "has-virtualization-extensions", > + qdev_prop_set_bit(vms->gic, "has-virtualization-extensions= ", > vms->virt); > } > } > - qdev_init_nofail(gicdev); > - gicbusdev =3D SYS_BUS_DEVICE(gicdev); > + qdev_init_nofail(vms->gic); > + gicbusdev =3D SYS_BUS_DEVICE(vms->gic); > sysbus_mmio_map(gicbusdev, 0, vms->memmap[VIRT_GIC_DIST].base); > if (type =3D=3D 3) { > sysbus_mmio_map(gicbusdev, 1, vms->memmap[VIRT_GIC_REDIST].bas= e); > @@ -678,23 +678,23 @@ static void create_gic(VirtMachineState *vms, qem= u_irq *pic) > =20 > for (irq =3D 0; irq < ARRAY_SIZE(timer_irq); irq++) { > qdev_connect_gpio_out(cpudev, irq, > - qdev_get_gpio_in(gicdev, > + qdev_get_gpio_in(vms->gic, > ppibase + timer_irq= [irq])); > } > =20 > if (type =3D=3D 3) { > - qemu_irq irq =3D qdev_get_gpio_in(gicdev, > + qemu_irq irq =3D qdev_get_gpio_in(vms->gic, > ppibase + ARCH_GIC_MAINT_I= RQ); > qdev_connect_gpio_out_named(cpudev, "gicv3-maintenance-int= errupt", > 0, irq); > } else if (vms->virt) { > - qemu_irq irq =3D qdev_get_gpio_in(gicdev, > + qemu_irq irq =3D qdev_get_gpio_in(vms->gic, > ppibase + ARCH_GIC_MAINT_I= RQ); > sysbus_connect_irq(gicbusdev, i + 4 * smp_cpus, irq); > } > =20 > qdev_connect_gpio_out_named(cpudev, "pmu-interrupt", 0, > - qdev_get_gpio_in(gicdev, ppibase > + qdev_get_gpio_in(vms->gic, ppibase > + VIRTUAL_PMU_IRQ= )); > =20 > sysbus_connect_irq(gicbusdev, i, qdev_get_gpio_in(cpudev, ARM_= CPU_IRQ)); > @@ -706,20 +706,16 @@ static void create_gic(VirtMachineState *vms, qem= u_irq *pic) > qdev_get_gpio_in(cpudev, ARM_CPU_VFIQ)); > } > =20 > - for (i =3D 0; i < NUM_IRQS; i++) { > - pic[i] =3D qdev_get_gpio_in(gicdev, i); > - } > - > fdt_add_gic_node(vms); > =20 > if (type =3D=3D 3 && vms->its) { > - create_its(vms, gicdev); > + create_its(vms); > } else if (type =3D=3D 2) { > - create_v2m(vms, pic); > + create_v2m(vms); > } > } > =20 > -static void create_uart(const VirtMachineState *vms, qemu_irq *pic, in= t uart, > +static void create_uart(const VirtMachineState *vms, int uart, > MemoryRegion *mem, Chardev *chr) > { > char *nodename; > @@ -735,7 +731,7 @@ static void create_uart(const VirtMachineState *vms= , qemu_irq *pic, int uart, > qdev_init_nofail(dev); > memory_region_add_subregion(mem, base, > sysbus_mmio_get_region(s, 0)); > - sysbus_connect_irq(s, 0, pic[irq]); > + sysbus_connect_irq(s, 0, qdev_get_gpio_in(vms->gic, irq)); > =20 > nodename =3D g_strdup_printf("/pl011@%" PRIx64, base); > qemu_fdt_add_subnode(vms->fdt, nodename); > @@ -767,7 +763,7 @@ static void create_uart(const VirtMachineState *vms= , qemu_irq *pic, int uart, > g_free(nodename); > } > =20 > -static void create_rtc(const VirtMachineState *vms, qemu_irq *pic) > +static void create_rtc(const VirtMachineState *vms) > { > char *nodename; > hwaddr base =3D vms->memmap[VIRT_RTC].base; > @@ -775,7 +771,7 @@ static void create_rtc(const VirtMachineState *vms,= qemu_irq *pic) > int irq =3D vms->irqmap[VIRT_RTC]; > const char compat[] =3D "arm,pl031\0arm,primecell"; > =20 > - sysbus_create_simple("pl031", base, pic[irq]); > + sysbus_create_simple("pl031", base, qdev_get_gpio_in(vms->gic, irq= )); > =20 > nodename =3D g_strdup_printf("/pl031@%" PRIx64, base); > qemu_fdt_add_subnode(vms->fdt, nodename); > @@ -803,7 +799,7 @@ static void virt_powerdown_req(Notifier *n, void *o= paque) > } > } > =20 > -static void create_gpio(const VirtMachineState *vms, qemu_irq *pic) > +static void create_gpio(const VirtMachineState *vms) > { > char *nodename; > DeviceState *pl061_dev; > @@ -812,7 +808,8 @@ static void create_gpio(const VirtMachineState *vms= , qemu_irq *pic) > int irq =3D vms->irqmap[VIRT_GPIO]; > const char compat[] =3D "arm,pl061\0arm,primecell"; > =20 > - pl061_dev =3D sysbus_create_simple("pl061", base, pic[irq]); > + pl061_dev =3D sysbus_create_simple("pl061", base, > + qdev_get_gpio_in(vms->gic, irq)); > =20 > uint32_t phandle =3D qemu_fdt_alloc_phandle(vms->fdt); > nodename =3D g_strdup_printf("/pl061@%" PRIx64, base); > @@ -846,7 +843,7 @@ static void create_gpio(const VirtMachineState *vms= , qemu_irq *pic) > g_free(nodename); > } > =20 > -static void create_virtio_devices(const VirtMachineState *vms, qemu_ir= q *pic) > +static void create_virtio_devices(const VirtMachineState *vms) > { > int i; > hwaddr size =3D vms->memmap[VIRT_MMIO].size; > @@ -882,7 +879,8 @@ static void create_virtio_devices(const VirtMachine= State *vms, qemu_irq *pic) > int irq =3D vms->irqmap[VIRT_MMIO] + i; > hwaddr base =3D vms->memmap[VIRT_MMIO].base + i * size; > =20 > - sysbus_create_simple("virtio-mmio", base, pic[irq]); > + sysbus_create_simple("virtio-mmio", base, > + qdev_get_gpio_in(vms->gic, irq)); > } > =20 > /* We add dtb nodes in reverse order so that they appear in the fi= nished > @@ -1131,7 +1129,7 @@ static void create_pcie_irq_map(const VirtMachine= State *vms, > 0x7 /* PCI irq */); > } > =20 > -static void create_smmu(const VirtMachineState *vms, qemu_irq *pic, > +static void create_smmu(const VirtMachineState *vms, > PCIBus *bus) > { > char *node; > @@ -1154,7 +1152,8 @@ static void create_smmu(const VirtMachineState *v= ms, qemu_irq *pic, > qdev_init_nofail(dev); > sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base); > for (i =3D 0; i < NUM_SMMU_IRQS; i++) { > - sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, pic[irq + i]); > + sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, > + qdev_get_gpio_in(vms->gic, irq + i)); > } > =20 > node =3D g_strdup_printf("/smmuv3@%" PRIx64, base); > @@ -1181,7 +1180,7 @@ static void create_smmu(const VirtMachineState *v= ms, qemu_irq *pic, > g_free(node); > } > =20 > -static void create_pcie(VirtMachineState *vms, qemu_irq *pic) > +static void create_pcie(VirtMachineState *vms) > { > hwaddr base_mmio =3D vms->memmap[VIRT_PCIE_MMIO].base; > hwaddr size_mmio =3D vms->memmap[VIRT_PCIE_MMIO].size; > @@ -1241,7 +1240,8 @@ static void create_pcie(VirtMachineState *vms, qe= mu_irq *pic) > sysbus_mmio_map(SYS_BUS_DEVICE(dev), 2, base_pio); > =20 > for (i =3D 0; i < GPEX_NUM_IRQS; i++) { > - sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, pic[irq + i]); > + sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, > + qdev_get_gpio_in(vms->gic, irq + i)); > gpex_set_irq_num(GPEX_HOST(dev), i, irq + i); > } > =20 > @@ -1301,7 +1301,7 @@ static void create_pcie(VirtMachineState *vms, qe= mu_irq *pic) > if (vms->iommu) { > vms->iommu_phandle =3D qemu_fdt_alloc_phandle(vms->fdt); > =20 > - create_smmu(vms, pic, pci->bus); > + create_smmu(vms, pci->bus); > =20 > qemu_fdt_setprop_cells(vms->fdt, nodename, "iommu-map", > 0x0, vms->iommu_phandle, 0x0, 0x10000); > @@ -1310,7 +1310,7 @@ static void create_pcie(VirtMachineState *vms, qe= mu_irq *pic) > g_free(nodename); > } > =20 > -static void create_platform_bus(VirtMachineState *vms, qemu_irq *pic) > +static void create_platform_bus(VirtMachineState *vms) > { > DeviceState *dev; > SysBusDevice *s; > @@ -1326,8 +1326,8 @@ static void create_platform_bus(VirtMachineState = *vms, qemu_irq *pic) > =20 > s =3D SYS_BUS_DEVICE(dev); > for (i =3D 0; i < PLATFORM_BUS_NUM_IRQS; i++) { > - int irqn =3D vms->irqmap[VIRT_PLATFORM_BUS] + i; > - sysbus_connect_irq(s, i, pic[irqn]); > + int irq =3D vms->irqmap[VIRT_PLATFORM_BUS] + i; > + sysbus_connect_irq(s, i, qdev_get_gpio_in(vms->gic, irq)); > } > =20 > memory_region_add_subregion(sysmem, > @@ -1509,7 +1509,6 @@ static void machvirt_init(MachineState *machine) > VirtMachineClass *vmc =3D VIRT_MACHINE_GET_CLASS(machine); > MachineClass *mc =3D MACHINE_GET_CLASS(machine); > const CPUArchIdList *possible_cpus; > - qemu_irq pic[NUM_IRQS]; > MemoryRegion *sysmem =3D get_system_memory(); > MemoryRegion *secure_sysmem =3D NULL; > int n, virt_max_cpus; > @@ -1712,27 +1711,27 @@ static void machvirt_init(MachineState *machine= ) > =20 > virt_flash_fdt(vms, sysmem, secure_sysmem ?: sysmem); > =20 > - create_gic(vms, pic); > + create_gic(vms); > =20 > fdt_add_pmu_nodes(vms); > =20 > - create_uart(vms, pic, VIRT_UART, sysmem, serial_hd(0)); > + create_uart(vms, VIRT_UART, sysmem, serial_hd(0)); > =20 > if (vms->secure) { > create_secure_ram(vms, secure_sysmem); > - create_uart(vms, pic, VIRT_SECURE_UART, secure_sysmem, serial_= hd(1)); > + create_uart(vms, VIRT_SECURE_UART, secure_sysmem, serial_hd(1)= ); > } > =20 > vms->highmem_ecam &=3D vms->highmem && (!firmware_loaded || aarch6= 4); > =20 > - create_rtc(vms, pic); > + create_rtc(vms); > =20 > - create_pcie(vms, pic); > + create_pcie(vms); > =20 > if (has_ged && aarch64 && firmware_loaded && acpi_enabled) { > - vms->acpi_dev =3D create_acpi_ged(vms, pic); > + vms->acpi_dev =3D create_acpi_ged(vms); > } else { > - create_gpio(vms, pic); > + create_gpio(vms); > } > =20 > /* connect powerdown request */ > @@ -1743,12 +1742,12 @@ static void machvirt_init(MachineState *machine= ) > * (which will be automatically plugged in to the transports). If > * no backend is created the transport will just sit harmlessly id= le. > */ > - create_virtio_devices(vms, pic); > + create_virtio_devices(vms); > =20 > vms->fw_cfg =3D create_fw_cfg(vms, &address_space_memory); > rom_set_fw(vms->fw_cfg); > =20 > - create_platform_bus(vms, pic); > + create_platform_bus(vms); > =20 > vms->bootinfo.ram_size =3D machine->ram_size; > vms->bootinfo.nb_cpus =3D smp_cpus; >=20 From MAILER-DAEMON Mon Dec 09 08:05:12 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1ieIiu-0002EA-2y for mharc-qemu-arm@gnu.org; Mon, 09 Dec 2019 08:05:12 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:42808) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ieIiq-0002Dx-F3 for qemu-arm@nongnu.org; Mon, 09 Dec 2019 08:05:10 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ieIio-0001Uq-FV for qemu-arm@nongnu.org; Mon, 09 Dec 2019 08:05:08 -0500 Received: from lhrrgout.huawei.com ([185.176.76.210]:2055 helo=huawei.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1ieIio-0001T4-5I; Mon, 09 Dec 2019 08:05:06 -0500 Received: from lhreml701-cah.china.huawei.com (unknown [172.18.7.108]) by Forcepoint Email with ESMTP id EF84DEC8CF68C3FF54C9; Mon, 9 Dec 2019 13:04:51 +0000 (GMT) Received: from lhreml709-chm.china.huawei.com (10.201.108.58) by lhreml701-cah.china.huawei.com (10.201.108.42) with Microsoft SMTP Server (TLS) id 14.3.408.0; Mon, 9 Dec 2019 13:04:51 +0000 Received: from lhreml710-chm.china.huawei.com (10.201.108.61) by lhreml709-chm.china.huawei.com (10.201.108.58) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5; Mon, 9 Dec 2019 13:04:51 +0000 Received: from lhreml710-chm.china.huawei.com ([169.254.81.184]) by lhreml710-chm.china.huawei.com ([169.254.81.184]) with mapi id 15.01.1713.004; Mon, 9 Dec 2019 13:04:51 +0000 From: Shameerali Kolothum Thodi To: Igor Mammedov , "Michael S. Tsirkin" CC: "peter.maydell@linaro.org" , "shannon.zhaosl@gmail.com" , "qemu-devel@nongnu.org" , Linuxarm , "eric.auger@redhat.com" , "qemu-arm@nongnu.org" , "xuwei (O)" , "lersek@redhat.com" Subject: RE: [PATCH 1/5] hw/arm: Align ACPI blob len to PAGE size Thread-Topic: [PATCH 1/5] hw/arm: Align ACPI blob len to PAGE size Thread-Index: AQHVeswOt9Cm/mHIvkOjMvan5ZmmMqeBqoOAgAR2W8CALAlAoA== Date: Mon, 9 Dec 2019 13:04:51 +0000 Message-ID: <323aa74a92934b6a989e6e4dbe0dfe21@huawei.com> References: <20191004155302.4632-1-shameerali.kolothum.thodi@huawei.com> <20191004155302.4632-2-shameerali.kolothum.thodi@huawei.com> <20191108171745.1465295b@redhat.com> <3ae89f87a5d64f57bea7246772c41301@huawei.com> In-Reply-To: <3ae89f87a5d64f57bea7246772c41301@huawei.com> Accept-Language: en-GB, en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [10.202.227.237] Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-CFilter-Loop: Reflected X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 185.176.76.210 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 09 Dec 2019 13:05:10 -0000 Hi Igor/ Michael, > -----Original Message----- > From: Linuxarm [mailto:linuxarm-bounces@huawei.com] On Behalf Of > Shameerali Kolothum Thodi > Sent: 11 November 2019 12:47 > To: Igor Mammedov > Cc: peter.maydell@linaro.org; shannon.zhaosl@gmail.com; Michael S. Tsirki= n > ; qemu-devel@nongnu.org; Linuxarm > ; eric.auger@redhat.com; qemu-arm@nongnu.org; > xuwei (O) ; lersek@redhat.com > Subject: RE: [PATCH 1/5] hw/arm: Align ACPI blob len to PAGE size >=20 > Hi Igor, >=20 > > -----Original Message----- > > From: Igor Mammedov [mailto:imammedo@redhat.com] > > Sent: 08 November 2019 16:18 > > To: Shameerali Kolothum Thodi > > Cc: qemu-devel@nongnu.org; qemu-arm@nongnu.org; > > eric.auger@redhat.com; peter.maydell@linaro.org; > > shannon.zhaosl@gmail.com; xuwei (O) ; > > lersek@redhat.com; Linuxarm ; Michael S. Tsirkin > > > > Subject: Re: [PATCH 1/5] hw/arm: Align ACPI blob len to PAGE size > > > > On Fri, 4 Oct 2019 16:52:58 +0100 > > Shameer Kolothum wrote: > > > > > If ACPI blob length modifications happens after the initial > > > virt_acpi_build() call, and the changed blob length is within > > > the PAGE size boundary, then the revised size is not seen by > > > the firmware on Guest reboot. The is because in the > > > virt_acpi_build_update() -> acpi_ram_update() -> qemu_ram_resize() > > > path, qemu_ram_resize() uses ram_block size which is aligned > > > to PAGE size and the "resize callback" to update the size seen > > > by firmware is not getting invoked. Hence align ACPI blob sizes > > > to PAGE boundary. > > > > > > Signed-off-by: Shameer Kolothum > > > > --- > > > More details on this issue can be found here, > > > https://patchwork.kernel.org/patch/11154757/ > > re-read it again and it seems to me that this patch is workaround > > rather than a solution to the problem. >=20 > Thanks for taking a look at this. Yes, I was also not very sure about thi= s > approach > as the root cause of the issue is in qemu_ram_resize(). >=20 > > CCing Michael as an author this code. > > on x86 we have crazy history of manually aligning acpi blobs, see code = under > > comment > > > > /* We'll expose it all to Guest so we want to reduce > > > > so used_length endups with over-sized value which includes table and > padding > > and it happens that ACPI_BUILD_TABLE_SIZE is much bigger than host page > > size > > so if on reboot we happen to exceed ACPI_BUILD_TABLE_SIZE, the next > padded > > table > > size (used_length) would be 2 x ACPI_BUILD_TABLE_SIZE which doesn't > > trigger > > block->used_length =3D=3D HOST_PAGE_ALIGN(newsize) > > condition so fwcfg gets updated value. >=20 > Yes, this is the reason why the issue is not visible on x86. >=20 > > > > > --- > > > hw/arm/virt-acpi-build.c | 14 ++++++++++++++ > > > 1 file changed, 14 insertions(+) > > > > > > diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c > > > index 4cd50175e0..074e0c858e 100644 > > > --- a/hw/arm/virt-acpi-build.c > > > +++ b/hw/arm/virt-acpi-build.c > > > @@ -790,6 +790,7 @@ void virt_acpi_build(VirtMachineState *vms, > > AcpiBuildTables *tables) > > > GArray *table_offsets; > > > unsigned dsdt, xsdt; > > > GArray *tables_blob =3D tables->table_data; > > > + GArray *cmd_blob =3D tables->linker->cmd_blob; > > > MachineState *ms =3D MACHINE(vms); > > > > > > table_offsets =3D g_array_new(false, true /* clear */, > > > @@ -854,6 +855,19 @@ void virt_acpi_build(VirtMachineState *vms, > > AcpiBuildTables *tables) > > > build_rsdp(tables->rsdp, tables->linker, &rsdp_data); > > > } > > > > > > + /* > > > + * Align the ACPI blob lengths to PAGE size so that on ACPI tabl= e > > > + * regeneration, the length that firmware sees really gets updat= ed > > > + * through 'resize' callback in qemu_ram_resize() in the > > > + * virt_acpi_build_update() -> acpi_ram_update() -> > > qemu_ram_resize() > > > + * path. > > > + */ > > > + g_array_set_size(tables_blob, > > > + > > TARGET_PAGE_ALIGN(acpi_data_len(tables_blob))); > > here it would depend on TARGET_PAGE_ALIGN vs HOST_PAGE_ALIGN > relation > > so depending on host it could flip it's behavior to opposite. >=20 > Ok. >=20 > > > > one thing we could do is dropping (block->used_length =3D=3D newsize) c= ondition >=20 > I tried this before and strangely for some reason on reboot path, >=20 > virt_acpi_build_update() is called with build_state being NULL and no > acpi_ram_update() > happens. Not sure what causes this behavior when we drop the above > condition. >=20 > > another is to use value of block->used_length for s->files->f[index].si= ze. >=20 > I just tried this by passing block->used_length to fw_cfg_add_file_callba= ck() . > This could work for this case. But not sure there will be any corner case= s > and also there isn't any easy way to access the mr->ram_balck->used_lengt= h > from > hw/core/loader.c. >=20 > > > > Michael, > > what's your take in this? >=20 This is how(below) I tried to use the RAMBlock used_length for s->files->f[= index].size. As used_length is abstracted here, I had to introduce a new api to retrieve= the same. Please take a look and let me know if there is a better way of achiev= ing this. Thanks. Shameer ---8--- diff --git a/hw/core/loader.c b/hw/core/loader.c index 5099f27dc8..e862c8c0e1 100644 --- a/hw/core/loader.c +++ b/hw/core/loader.c @@ -1055,6 +1055,7 @@ MemoryRegion *rom_add_blob(const char *name, const vo= id *blob, size_t len, if (fw_file_name && fw_cfg) { char devpath[100]; void *data; + size_t size; =20 if (read_only) { snprintf(devpath, sizeof(devpath), "/rom@%s", fw_file_name); @@ -1065,13 +1066,15 @@ MemoryRegion *rom_add_blob(const char *name, const = void *blob, size_t len, if (mc->rom_file_has_mr) { data =3D rom_set_mr(rom, OBJECT(fw_cfg), devpath, read_only); mr =3D rom->mr; + size =3D memory_region_get_used_length(mr); } else { data =3D rom->data; + size =3D rom->datasize; } =20 fw_cfg_add_file_callback(fw_cfg, fw_file_name, fw_callback, NULL, callback_opaque, - data, rom->datasize, read_only); + data, size, read_only); } return mr; } diff --git a/include/exec/memory.h b/include/exec/memory.h index e499dc215b..c51e6cdb9a 100644 --- a/include/exec/memory.h +++ b/include/exec/memory.h @@ -1584,6 +1584,12 @@ void memory_region_add_subregion_overlap(MemoryRegio= n *mr, */ ram_addr_t memory_region_get_ram_addr(MemoryRegion *mr); =20 +/** + * memory_region_get_used_length: Get the used length associated with a me= mory + * region + */ +ram_addr_t memory_region_get_used_length(MemoryRegion *mr); + uint64_t memory_region_get_alignment(const MemoryRegion *mr); /** * memory_region_del_subregion: Remove a subregion. diff --git a/memory.c b/memory.c index 06484c2bff..d1f60c0c9a 100644 --- a/memory.c +++ b/memory.c @@ -2200,6 +2200,11 @@ ram_addr_t memory_region_get_ram_addr(MemoryRegion *= mr) return mr->ram_block ? mr->ram_block->offset : RAM_ADDR_INVALID; } =20 +ram_addr_t memory_region_get_used_length(MemoryRegion *mr) +{ + return mr->ram_block ? mr->ram_block->used_length : RAM_ADDR_INVALID; +} + void memory_region_ram_resize(MemoryRegion *mr, ram_addr_t newsize, Error = **errp) { assert(mr->ram_block); ---8-- From MAILER-DAEMON Mon Dec 09 08:05:42 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1ieIjO-0002kq-NW for mharc-qemu-arm@gnu.org; Mon, 09 Dec 2019 08:05:42 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:42896) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ieIjG-0002bm-VM for qemu-arm@nongnu.org; Mon, 09 Dec 2019 08:05:41 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ieIjE-0001db-2A for qemu-arm@nongnu.org; Mon, 09 Dec 2019 08:05:34 -0500 Received: from mail-il1-x142.google.com ([2607:f8b0:4864:20::142]:38568) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ieIjD-0001dC-Or for qemu-arm@nongnu.org; Mon, 09 Dec 2019 08:05:32 -0500 Received: by mail-il1-x142.google.com with SMTP id u17so12661319ilq.5 for ; Mon, 09 Dec 2019 05:05:31 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=Pq1VnlfgzcHCQJUO32Frg0EdLNprnm9eqLtuA42zu7k=; b=feb5SHfGA+O42Pfi3xXO9Rqt5xYzZjznx9mrRC+eUdR2sFjzJRgk6UQfC4n8tb1G7W zO+OYzrw7xC4wXhLbgCq9V4ZJ5XfC92+xl95paRQbBBsbz43qudQl9+BVOKkzW6aQdXI FZbaKxe4igjH0EOSDjaXODalaVs949GmPhs7c53qjjkbPOra0wvHs4ROlevvToLzbxzb e49MJb3Yp7vLNcCNmwfG0Pwdd5Mpfou4XfAYvlw1vgS2s1ok0shCE4PI7p/mZS7hbadp bR2jzT5sjyPssQttlC7kt+g3tb+/DjQouBAjEhALtKNAhrPRlpyAOo+bS19M43MeF+hy hVMg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=Pq1VnlfgzcHCQJUO32Frg0EdLNprnm9eqLtuA42zu7k=; b=Es72yBmX4jNSE/+wCUoXsiOKilbL5O0LG2IaQCGnqhkMq37VvTk4mQX+tXO7/5dlO3 UZ9MMpvUng0+y2yNL1foX4sVKf5mjYRWpz9fNY9TKl0BTwbhS0AfpOHHn9smk1J25yr9 sOIub3nAmK+cM718NRbWLAssRU02UBeHIBlAa1Wm9d5lMXyasV4RUefr0ZcY4VYsCzUm NiAK/dWiuiih4BsgkdY9yOWUp7ba32321D0giip400+yWOChnxEC2G61xM3jpUEW7hjD JMu3Zcldq1wCxBLcoLpISHDoXYylcduKoHxwbJWbx2/DburdPfyGV+xv/WWBGexCZHU5 R7kg== X-Gm-Message-State: APjAAAVKNHPMnJdNJFcFLvv/ceeLe7krxiTt5BgyO+FtCxw/8iCmwRp2 0QWZH+Opjy9u6eDGFdg+NRA7/VfGN4ju5x7/sKsEDw== X-Google-Smtp-Source: APXvYqzRysTxu6BAnyOdhlOugs6B0yiBfWcE+8peBNltmDcf3EYuCxWSNBXWuukvL1Afr5eHIQI8kAb6QfwN/XraZg0= X-Received: by 2002:a92:5b5b:: with SMTP id p88mr9272188ilb.307.1575896730283; Mon, 09 Dec 2019 05:05:30 -0800 (PST) MIME-Version: 1.0 References: <20191111014048.21296-1-zhengxiang9@huawei.com> <20191111014048.21296-6-zhengxiang9@huawei.com> <238ea7b3-9d6d-e3f7-40c9-e3e62b5fb477@huawei.com> In-Reply-To: <238ea7b3-9d6d-e3f7-40c9-e3e62b5fb477@huawei.com> From: Beata Michalska Date: Mon, 9 Dec 2019 13:05:19 +0000 Message-ID: Subject: Re: [RESEND PATCH v21 5/6] target-arm: kvm64: handle SIGBUS signal from kernel or KVM To: gengdongjiu Cc: Xiang Zheng , pbonzini@redhat.com, mst@redhat.com, Igor Mammedov , shannon.zhaosl@gmail.com, Peter Maydell , Laszlo Ersek , james.morse@arm.com, mtosatti@redhat.com, rth@twiddle.net, ehabkost@redhat.com, jonathan.cameron@huawei.com, xuwei5@huawei.com, kvm@vger.kernel.org, qemu-devel@nongnu.org, qemu-arm@nongnu.org, linuxarm@huawei.com, wanghaibin.wang@huawei.com Content-Type: text/plain; charset="UTF-8" X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::142 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 09 Dec 2019 13:05:41 -0000 On Sat, 7 Dec 2019 at 09:33, gengdongjiu wrote: > > > > On 2019/11/22 23:47, Beata Michalska wrote: > > Hi, > > > > On Mon, 11 Nov 2019 at 01:48, Xiang Zheng wrote: > >> > >> From: Dongjiu Geng > >> > >> Add a SIGBUS signal handler. In this handler, it checks the SIGBUS type, > >> translates the host VA delivered by host to guest PA, then fills this PA > >> to guest APEI GHES memory, then notifies guest according to the SIGBUS > >> type. > >> > >> When guest accesses the poisoned memory, it will generate a Synchronous > >> External Abort(SEA). Then host kernel gets an APEI notification and calls > >> memory_failure() to unmapped the affected page in stage 2, finally > >> returns to guest. > >> > >> Guest continues to access the PG_hwpoison page, it will trap to KVM as > >> stage2 fault, then a SIGBUS_MCEERR_AR synchronous signal is delivered to > >> Qemu, Qemu records this error address into guest APEI GHES memory and > >> notifes guest using Synchronous-External-Abort(SEA). > >> > >> In order to inject a vSEA, we introduce the kvm_inject_arm_sea() function > >> in which we can setup the type of exception and the syndrome information. > >> When switching to guest, the target vcpu will jump to the synchronous > >> external abort vector table entry. > >> > >> The ESR_ELx.DFSC is set to synchronous external abort(0x10), and the > >> ESR_ELx.FnV is set to not valid(0x1), which will tell guest that FAR is > >> not valid and hold an UNKNOWN value. These values will be set to KVM > >> register structures through KVM_SET_ONE_REG IOCTL. > >> > >> Signed-off-by: Dongjiu Geng > >> Signed-off-by: Xiang Zheng > >> Reviewed-by: Michael S. Tsirkin > >> --- > >> hw/acpi/acpi_ghes.c | 297 ++++++++++++++++++++++++++++++++++++ > >> include/hw/acpi/acpi_ghes.h | 4 + > >> include/sysemu/kvm.h | 3 +- > >> target/arm/cpu.h | 4 + > >> target/arm/helper.c | 2 +- > >> target/arm/internals.h | 5 +- > >> target/arm/kvm64.c | 64 ++++++++ > >> target/arm/tlb_helper.c | 2 +- > >> target/i386/cpu.h | 2 + > >> 9 files changed, 377 insertions(+), 6 deletions(-) > >> > >> diff --git a/hw/acpi/acpi_ghes.c b/hw/acpi/acpi_ghes.c > >> index 42c00ff3d3..f5b54990c0 100644 > >> --- a/hw/acpi/acpi_ghes.c > >> +++ b/hw/acpi/acpi_ghes.c > >> @@ -39,6 +39,34 @@ > >> /* The max size in bytes for one error block */ > >> #define ACPI_GHES_MAX_RAW_DATA_LENGTH 0x1000 > >> > >> +/* > >> + * The total size of Generic Error Data Entry > >> + * ACPI 6.1/6.2: 18.3.2.7.1 Generic Error Data, > >> + * Table 18-343 Generic Error Data Entry > >> + */ > >> +#define ACPI_GHES_DATA_LENGTH 72 > >> + > >> +/* > >> + * The memory section CPER size, > >> + * UEFI 2.6: N.2.5 Memory Error Section > >> + */ > >> +#define ACPI_GHES_MEM_CPER_LENGTH 80 > >> + > >> +/* > >> + * Masks for block_status flags > >> + */ > >> +#define ACPI_GEBS_UNCORRECTABLE 1 > > > > Why not listing all supported statuses ? Similar to error severity below ? > > > >> + > >> +/* > >> + * Values for error_severity field > >> + */ > >> +enum AcpiGenericErrorSeverity { > >> + ACPI_CPER_SEV_RECOVERABLE, > >> + ACPI_CPER_SEV_FATAL, > >> + ACPI_CPER_SEV_CORRECTED, > >> + ACPI_CPER_SEV_NONE, > >> +}; > >> + > >> /* > >> * Now only support ARMv8 SEA notification type error source > >> */ > >> @@ -49,6 +77,16 @@ > >> */ > >> #define ACPI_GHES_SOURCE_GENERIC_ERROR_V2 10 > >> > >> +#define UUID_BE(a, b, c, d0, d1, d2, d3, d4, d5, d6, d7) \ > >> + {{{ ((a) >> 24) & 0xff, ((a) >> 16) & 0xff, ((a) >> 8) & 0xff, (a) & 0xff, \ > >> + ((b) >> 8) & 0xff, (b) & 0xff, \ > >> + ((c) >> 8) & 0xff, (c) & 0xff, \ > >> + (d0), (d1), (d2), (d3), (d4), (d5), (d6), (d7) } } } > >> + > >> +#define UEFI_CPER_SEC_PLATFORM_MEM \ > >> + UUID_BE(0xA5BC1114, 0x6F64, 0x4EDE, 0xB8, 0x63, 0x3E, 0x83, \ > >> + 0xED, 0x7C, 0x83, 0xB1) > >> + > >> /* > >> * | +--------------------------+ 0 > >> * | | Header | > >> @@ -77,6 +115,174 @@ typedef struct AcpiGhesState { > >> uint64_t ghes_addr_le; > >> } AcpiGhesState; > >> > >> +/* > >> + * Total size for Generic Error Status Block > >> + * ACPI 6.2: 18.3.2.7.1 Generic Error Data, > >> + * Table 18-380 Generic Error Status Block > >> + */ > >> +#define ACPI_GHES_GESB_SIZE 20 > > > > Minor: This is not entirely correct: GEDE is part of GESB so the total length > > would be ACPI_GHES_GESB_SIZE + n* sizeof(GEDE) > yes, the comments needs to correct. > > > > >> +/* The offset of Data Length in Generic Error Status Block */ > >> +#define ACPI_GHES_GESB_DATA_LENGTH_OFFSET 12 > >> + > > > > If those were nicely represented as structures you get the offsets easily > > without having number of defines. That could simplify the code and make it > > more readable - see comments below > > > >> +/* > >> + * Record the value of data length for each error status block to avoid getting > >> + * this value from guest. > >> + */ > >> +static uint32_t acpi_ghes_data_length[ACPI_GHES_ERROR_SOURCE_COUNT]; > >> + > >> +/* > >> + * Generic Error Data Entry > >> + * ACPI 6.1: 18.3.2.7.1 Generic Error Data > >> + */ > >> +static void acpi_ghes_generic_error_data(GArray *table, QemuUUID section_type, > >> + uint32_t error_severity, uint16_t revision, > >> + uint8_t validation_bits, uint8_t flags, > >> + uint32_t error_data_length, QemuUUID fru_id, > >> + uint8_t *fru_text, uint64_t time_stamp) > > > > Why not just defining a struct that represents the GED entry? > > This is due to address Igor's comments. there are two reasons: > 1. avoid define many structures about APEI/GHES/CPER, so you can see it has very little structures definition in acpi_ghes.h > 2. using build_append_int_noprefix() to compose the table can avoid considering endian > > > > >> +{ > >> + QemuUUID uuid_le; > >> + > >> + /* Section Type */ > >> + uuid_le = qemu_uuid_bswap(section_type); > >> + g_array_append_vals(table, uuid_le.data, ARRAY_SIZE(uuid_le.data)); > >> + > >> + /* Error Severity */ > >> + build_append_int_noprefix(table, error_severity, 4); > >> + /* Revision */ > >> + build_append_int_noprefix(table, revision, 2); > > > > Minor: According to the spec it seems that the revision number is > > a fixed value so you could drop that from the parameters.... > > or ... use a struct to represent the data > > > >> + /* Validation Bits */ > >> + build_append_int_noprefix(table, validation_bits, 1); > >> + /* Flags */ > >> + build_append_int_noprefix(table, flags, 1); > >> + /* Error Data Length */ > >> + build_append_int_noprefix(table, error_data_length, 4); > >> + > >> + /* FRU Id */ > >> + uuid_le = qemu_uuid_bswap(fru_id); > >> + g_array_append_vals(table, uuid_le.data, ARRAY_SIZE(uuid_le.data)); > >> + > >> + /* FRU Text */ > >> + g_array_append_vals(table, fru_text, 20); > >> + /* Timestamp */ > >> + build_append_int_noprefix(table, time_stamp, 8); > >> +} > >> + > >> +/* > >> + * Generic Error Status Block > >> + * ACPI 6.1: 18.3.2.7.1 Generic Error Data > >> + */ > >> +static void acpi_ghes_generic_error_status(GArray *table, uint32_t block_status, > >> + uint32_t raw_data_offset, uint32_t raw_data_length, > >> + uint32_t data_length, uint32_t error_severity) > > > > Same as the above > > > >> +{ > >> + /* Block Status */ > >> + build_append_int_noprefix(table, block_status, 4); > >> + /* Raw Data Offset */ > >> + build_append_int_noprefix(table, raw_data_offset, 4); > >> + /* Raw Data Length */ > >> + build_append_int_noprefix(table, raw_data_length, 4); > >> + /* Data Length */ > >> + build_append_int_noprefix(table, data_length, 4); > >> + /* Error Severity */ > >> + build_append_int_noprefix(table, error_severity, 4); > >> +} > >> + > >> +/* UEFI 2.6: N.2.5 Memory Error Section */ > >> +static void acpi_ghes_build_append_mem_cper(GArray *table, > >> + uint64_t error_physical_addr) > >> +{ > >> + /* > >> + * Memory Error Record > >> + */ > >> + > >> + /* Validation Bits */ > >> + build_append_int_noprefix(table, > >> + (1UL << 14) | /* Type Valid */ > >> + (1UL << 1) /* Physical Address Valid */, > >> + 8); > >> + /* Error Status */ > >> + build_append_int_noprefix(table, 0, 8); > > > > Just wondering whether it would be worth to specify the Error Type > > through the Error Status ? > > > >> + /* Physical Address */ > >> + build_append_int_noprefix(table, error_physical_addr, 8); > >> + /* Skip all the detailed information normally found in such a record */ > >> + build_append_int_noprefix(table, 0, 48); > >> + /* Memory Error Type */ > >> + build_append_int_noprefix(table, 0 /* Unknown error */, 1); > >> + /* Skip all the detailed information normally found in such a record */ > >> + build_append_int_noprefix(table, 0, 7); > >> +} > >> + > >> +static int acpi_ghes_record_mem_error(uint64_t error_block_address, > >> + uint64_t error_physical_addr, > >> + uint32_t data_length) > >> +{ > >> + GArray *block; > >> + uint64_t current_block_length; > >> + /* Memory Error Section Type */ > >> + QemuUUID mem_section_id_le = UEFI_CPER_SEC_PLATFORM_MEM; > > > > As already mentioned - mixing LE /w BE > > > >> + QemuUUID fru_id = {}; > >> + uint8_t fru_text[20] = {}; > >> + > >> + /* > >> + * Generic Error Status Block > >> + * | +---------------------+ > >> + * | | block_status | > >> + * | +---------------------+ > >> + * | | raw_data_offset | > >> + * | +---------------------+ > >> + * | | raw_data_length | > >> + * | +---------------------+ > >> + * | | data_length | > >> + * | +---------------------+ > >> + * | | error_severity | > >> + * | +---------------------+ > >> + */ > >> + block = g_array_new(false, true /* clear */, 1); > >> + > >> + /* The current whole length of the generic error status block */ > >> + current_block_length = ACPI_GHES_GESB_SIZE + data_length; > >> + > >> + /* This is the length if adding a new generic error data entry*/ > >> + data_length += ACPI_GHES_DATA_LENGTH; > >> + data_length += ACPI_GHES_MEM_CPER_LENGTH; > >> + > >> + /* > >> + * Check whether it will run out of the preallocated memory if adding a new > >> + * generic error data entry > >> + */ > >> + if ((data_length + ACPI_GHES_GESB_SIZE) > ACPI_GHES_MAX_RAW_DATA_LENGTH) { > >> + error_report("Record CPER out of boundary!!!"); > > > > Minor: The error message could be made more accurate, like: > > "Not enough memory to record new CPER" > > > >> + return ACPI_GHES_CPER_FAIL; > >> + } > >> + > >> + /* Build the new generic error status block header */ > >> + acpi_ghes_generic_error_status(block, cpu_to_le32(ACPI_GEBS_UNCORRECTABLE), > >> + 0, 0, cpu_to_le32(data_length), cpu_to_le32(ACPI_CPER_SEV_RECOVERABLE)); > >> + > >> + /* Write back above generic error status block header to guest memory */ > >> + cpu_physical_memory_write(error_block_address, block->data, > >> + block->len); > >> + > >> + /* Add a new generic error data entry */ > >> + > >> + data_length = block->len; > >> + /* Build this new generic error data entry header */ > >> + acpi_ghes_generic_error_data(block, mem_section_id_le, > >> + cpu_to_le32(ACPI_CPER_SEV_RECOVERABLE), cpu_to_le32(0x300), 0, 0, > >> + cpu_to_le32(ACPI_GHES_MEM_CPER_LENGTH), fru_id, fru_text, 0); > >> + > >> + /* Build the memory section CPER for above new generic error data entry */ > >> + acpi_ghes_build_append_mem_cper(block, error_physical_addr); > >> + > >> + /* Write back above this new generic error data entry to guest memory */ > >> + cpu_physical_memory_write(error_block_address + current_block_length, > >> + block->data + data_length, block->len - data_length); > >> + > > > > As already mentioned and unless I have missed smth (which is highly possible) > > this will append new records while the GESB is kept 'in-place'. So the > > used space is > > only growing. > > > >> + g_array_free(block, true); > >> + > >> + return ACPI_GHES_CPER_OK; > >> +} > >> + > >> /* > >> * Hardware Error Notification > >> * ACPI 4.0: 17.3.2.7 Hardware Error Notification > >> @@ -265,3 +471,94 @@ void acpi_ghes_add_fw_cfg(FWCfgState *s, GArray *hardware_error) > >> fw_cfg_add_file_callback(s, ACPI_GHES_DATA_ADDR_FW_CFG_FILE, NULL, NULL, > >> NULL, &ges.ghes_addr_le, sizeof(ges.ghes_addr_le), false); > >> } > >> + > >> +bool acpi_ghes_record_errors(uint32_t notify, uint64_t physical_address) > >> +{ > >> + uint64_t error_block_addr, read_ack_register_addr, read_ack_register = 0; > >> + int loop = 0; > >> + uint64_t start_addr = le64_to_cpu(ges.ghes_addr_le); > >> + bool ret = ACPI_GHES_CPER_FAIL; > >> + uint8_t source_id; > >> + const uint8_t error_source_id[] = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, > >> + 0xff, 0xff, 0, 0xff, 0xff, 0xff}; > >> + > > > > I'm not entirely sure why this is needed - se below > > > >> + /* > >> + * | +---------------------+ ges.ghes_addr_le > >> + * | |error_block_address0 | > >> + * | +---------------------+ --+-- > >> + * | | ............. | ACPI_GHES_ADDRESS_SIZE > >> + * | +---------------------+ --+-- > >> + * | |error_block_addressN | > >> + * | +---------------------+ > >> + * | | read_ack_register0 | > >> + * | +---------------------+ --+-- > >> + * | | ............. | ACPI_GHES_ADDRESS_SIZE > >> + * | +---------------------+ --+-- > >> + * | | read_ack_registerN | > >> + * | +---------------------+ --+-- > >> + * | | CPER | | > >> + * | | .... | ACPI_GHES_MAX_RAW_DATA_LENGT > >> + * | | CPER | | > >> + * | +---------------------+ --+-- > >> + * | | .......... | > >> + * | +---------------------+ > >> + * | | CPER | > >> + * | | .... | > >> + * | | CPER | > >> + * | +---------------------+ > >> + */ > >> + if (physical_address && notify < ACPI_GHES_NOTIFY_RESERVED) { > >> + /* Find and check the source id for this new CPER */ > >> + source_id = error_source_id[notify]; > > > > Why not using switch case for supported source types ? > > For the time being only one is being supported. And you only use that to > > verify that support - seems a bit unnecessary. > > Afterwards May be we will many source types to support, so Igor's suggestion is better as shown below. > > static const uint8_t ghes_notify2source_id_map[] = { > ACPI_HEST_SRC_ID_SEA, > ACPI_HEST_SRC_ID_RESERVED > } > > > > > >> + if (source_id != 0xff) { > >> + start_addr += source_id * ACPI_GHES_ADDRESS_SIZE; > >> + } else { > >> + goto out; > >> + } > >> + > [...] > >> > >> +/* Callers must hold the iothread mutex lock */ > >> +static void kvm_inject_arm_sea(CPUState *c) > > > > We could enclose this function along with the kvm_arch_on_sigbus_vcpu > > within ifdef switch for KVM_HAVE_MCE_INJECTION > > > >> +{ > >> + ARMCPU *cpu = ARM_CPU(c); > >> + CPUARMState *env = &cpu->env; > >> + CPUClass *cc = CPU_GET_CLASS(c); > >> + uint32_t esr; > >> + bool same_el; > >> + > >> + c->exception_index = EXCP_DATA_ABORT; > >> + env->exception.target_el = 1; > >> + > >> + /* > >> + * Set the DFSC to synchronous external abort and set FnV to not valid, > >> + * this will tell guest the FAR_ELx is UNKNOWN for this abort. > >> + */ > >> + same_el = arm_current_el(env) == env->exception.target_el; > >> + esr = syn_data_abort_no_iss(same_el, 1, 0, 0, 0, 0, 0x10); > > > > IINM this is the only use case when FnV is considered to be valid > > so I'm not convinced it is worth to modify the syn_data_abort_no_iss > > just for this. > > Here we set the FnV to not valid, not to set it to valid. > because Guest will use the physical address that recorded in APEI table. > To be precise : the FnV is giving the status of FAR - so what you are setting here is status of 0b0 which means FAR is valid, not FnV on it's own. And my point was that you are changing the prototype for syn_data_abort_no_iss just for this case only so I was just thinking that it might not be worth that, instead you could just set it here ... or to be more flexible , provide a way to set specific bits on demand. BR Beata > > > >> + > >> + env->exception.syndrome = esr; > >> + > >> + cc->do_interrupt(c); > >> +} > >> + > >> #define AARCH64_CORE_REG(x) (KVM_REG_ARM64 | KVM_REG_SIZE_U64 | \ > >> KVM_REG_ARM_CORE | KVM_REG_ARM_CORE_REG(x)) > >> > >> @@ -1036,6 +1062,44 @@ int kvm_arch_get_registers(CPUState *cs) > >> return ret; > >> } > >> > >> +void kvm_arch_on_sigbus_vcpu(CPUState *c, int code, void *addr) > >> +{ > >> + ram_addr_t ram_addr; > >> + hwaddr paddr; > >> + > >> + assert(code == BUS_MCEERR_AR || code == BUS_MCEERR_AO); > >> + > >> + if (acpi_enabled && addr && > >> + object_property_get_bool(qdev_get_machine(), "ras", NULL)) { > >> + ram_addr = qemu_ram_addr_from_host(addr); > >> + if (ram_addr != RAM_ADDR_INVALID && > >> + kvm_physical_memory_addr_from_host(c->kvm_state, addr, &paddr)) { > >> + kvm_hwpoison_page_add(ram_addr); > >> + /* > >> + * Asynchronous signal will be masked by main thread, so > >> + * only handle synchronous signal. > >> + */ > > > > I'm not entirely sure that the comment above is correct (it has been > > pointed out before). I would expect the AO signal to be handled here as > > well. Not having proper support to do that just yet is another story but > > the comment might be bit misleading. > > > > > >> + if (code == BUS_MCEERR_AR) { > >> + kvm_cpu_synchronize_state(c); > >> + if (ACPI_GHES_CPER_FAIL != > >> + acpi_ghes_record_errors(ACPI_GHES_NOTIFY_SEA, paddr)) { > >> + kvm_inject_arm_sea(c); > >> + } else { > >> + fprintf(stderr, "failed to record the error\n"); > >> + } > >> + } > >> + return; > >> + } > >> + fprintf(stderr, "Hardware memory error for memory used by " > >> + "QEMU itself instead of guest system!\n"); > >> + } > >> + > >> + if (code == BUS_MCEERR_AR) { > >> + fprintf(stderr, "Hardware memory error!\n"); > >> + exit(1); > >> + } > >> +} > >> + > >> /* C6.6.29 BRK instruction */ > >> static const uint32_t brk_insn = 0xd4200000; > >> > >> diff --git a/target/arm/tlb_helper.c b/target/arm/tlb_helper.c > >> index 5feb312941..499672ebbc 100644 > >> --- a/target/arm/tlb_helper.c > >> +++ b/target/arm/tlb_helper.c > >> @@ -33,7 +33,7 @@ static inline uint32_t merge_syn_data_abort(uint32_t template_syn, > >> * ISV field. > >> */ > >> if (!(template_syn & ARM_EL_ISV) || target_el != 2 || s1ptw) { > >> - syn = syn_data_abort_no_iss(same_el, > >> + syn = syn_data_abort_no_iss(same_el, 0, > >> ea, 0, s1ptw, is_write, fsc); > >> } else { > >> /* > >> diff --git a/target/i386/cpu.h b/target/i386/cpu.h > >> index 5352c9ff55..f75a210f96 100644 > >> --- a/target/i386/cpu.h > >> +++ b/target/i386/cpu.h > >> @@ -29,6 +29,8 @@ > >> /* The x86 has a strong memory model with some store-after-load re-ordering */ > >> #define TCG_GUEST_DEFAULT_MO (TCG_MO_ALL & ~TCG_MO_ST_LD) > >> > >> +#define KVM_HAVE_MCE_INJECTION 1 > >> + > >> /* Maximum instruction code size */ > >> #define TARGET_MAX_INSN_SIZE 16 > >> > >> -- > >> 2.19.1 > >> > >> > >> > > . > > > From MAILER-DAEMON Mon Dec 09 08:46:10 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1ieJMY-0000db-6n for mharc-qemu-arm@gnu.org; Mon, 09 Dec 2019 08:46:10 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:55960) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ieJMV-0000VW-3j for qemu-arm@nongnu.org; Mon, 09 Dec 2019 08:46:08 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ieJMR-0004CV-Ne for qemu-arm@nongnu.org; Mon, 09 Dec 2019 08:46:04 -0500 Received: from us-smtp-delivery-1.mimecast.com ([205.139.110.120]:54009 helo=us-smtp-1.mimecast.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1ieJMR-0004AO-JR for qemu-arm@nongnu.org; Mon, 09 Dec 2019 08:46:03 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1575899162; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding; bh=gxSwZyfeXxijSS52FpvVEEVrVieTj0X+VbLn4u/MPlA=; b=cPvCuArRulQSABAb1qbQ2T/tlyjogvfP9ESsqav4Ayx0L8gJejSqNGLoXNfzzToXCd/f1y jPjeY3FMDdNDaSFDXIq93Whq4I3xLEgcbIXQAJHNqQapGjVwWfs+5TtJbi3D/D474Bznyf 1bcHOtwy4HORrRMnY8clbSnxA1wOou0= Received: from mimecast-mx01.redhat.com (mimecast-mx01.redhat.com [209.132.183.4]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-14-2wA0zExYMlaUMLVu6bu2QQ-1; Mon, 09 Dec 2019 08:46:01 -0500 Received: from smtp.corp.redhat.com (int-mx07.intmail.prod.int.phx2.redhat.com [10.5.11.22]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx01.redhat.com (Postfix) with ESMTPS id D11B5801E74; Mon, 9 Dec 2019 13:45:59 +0000 (UTC) Received: from x1w.redhat.com (ovpn-205-146.brq.redhat.com [10.40.205.146]) by smtp.corp.redhat.com (Postfix) with ESMTPS id 345A81001938; Mon, 9 Dec 2019 13:45:54 +0000 (UTC) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Peter Maydell , qemu-arm@nongnu.org, =?UTF-8?q?Alex=20Benn=C3=A9e?= , Richard Henderson , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH] target/arm: Display helpful message when hflags mismatch Date: Mon, 9 Dec 2019 14:45:52 +0100 Message-Id: <20191209134552.27733-1-philmd@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.84 on 10.5.11.22 X-MC-Unique: 2wA0zExYMlaUMLVu6bu2QQ-1 X-Mimecast-Spam-Score: 0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 205.139.110.120 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 09 Dec 2019 13:46:08 -0000 Instead of crashing in a confuse way, give some hint to the user about why we aborted. He might report the issue without having to use a debugger. Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- target/arm/helper.c | 18 +++++++++++++++--- 1 file changed, 15 insertions(+), 3 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 0bf8f53d4b..6bfb62672b 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -11348,6 +11348,20 @@ void HELPER(rebuild_hflags_a64)(CPUARMState *env, = int el) env->hflags =3D rebuild_hflags_a64(env, el, fp_el, mmu_idx); } =20 +static inline void assert_hflags_rebuild_correctly(CPUARMState *env) +{ +#ifdef CONFIG_DEBUG_TCG + uint32_t env_flags_current =3D env->hflags; + uint32_t env_flags_rebuilt =3D rebuild_hflags_internal(env); + + if (unlikely(env_flags_current !=3D env_flags_rebuilt)) { + fprintf(stderr, "TCG hflags mismatch (current:0x%08x rebuilt:0x%08= x)\n", + env_flags_current, env_flags_rebuilt); + abort(); + } +#endif +} + void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc, target_ulong *cs_base, uint32_t *pflags) { @@ -11355,9 +11369,7 @@ void cpu_get_tb_cpu_state(CPUARMState *env, target_= ulong *pc, uint32_t pstate_for_ss; =20 *cs_base =3D 0; -#ifdef CONFIG_DEBUG_TCG - assert(flags =3D=3D rebuild_hflags_internal(env)); -#endif + assert_hflags_rebuild_correctly(env); =20 if (FIELD_EX32(flags, TBFLAG_ANY, AARCH64_STATE)) { *pc =3D env->pc; --=20 2.21.0 From MAILER-DAEMON Mon Dec 09 09:13:08 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1ieJme-0002TD-7o for mharc-qemu-arm@gnu.org; Mon, 09 Dec 2019 09:13:08 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:34581) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ieJmb-0002So-IL for qemu-arm@nongnu.org; Mon, 09 Dec 2019 09:13:06 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ieJma-0007Vt-9q for qemu-arm@nongnu.org; Mon, 09 Dec 2019 09:13:05 -0500 Received: from szxga07-in.huawei.com ([45.249.212.35]:53060 helo=huawei.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1ieJmZ-0007E9-Fr; Mon, 09 Dec 2019 09:13:04 -0500 Received: from DGGEMS407-HUB.china.huawei.com (unknown [172.30.72.60]) by Forcepoint Email with ESMTP id D162478339045A5766C6; Mon, 9 Dec 2019 22:12:42 +0800 (CST) Received: from [127.0.0.1] (10.142.68.147) by DGGEMS407-HUB.china.huawei.com (10.3.19.207) with Microsoft SMTP Server id 14.3.439.0; Mon, 9 Dec 2019 22:12:37 +0800 Subject: Re: [RESEND PATCH v21 5/6] target-arm: kvm64: handle SIGBUS signal from kernel or KVM To: Beata Michalska CC: Xiang Zheng , , , Igor Mammedov , , Peter Maydell , "Laszlo Ersek" , , , , , , , , , , , References: <20191111014048.21296-1-zhengxiang9@huawei.com> <20191111014048.21296-6-zhengxiang9@huawei.com> <238ea7b3-9d6d-e3f7-40c9-e3e62b5fb477@huawei.com> From: gengdongjiu Message-ID: <650e26cf-e007-1e31-cd0a-4042bb9fa6a8@huawei.com> Date: Mon, 9 Dec 2019 22:12:33 +0800 User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:52.0) Gecko/20100101 Thunderbird/52.3.0 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset="utf-8" Content-Language: en-US Content-Transfer-Encoding: 7bit X-Originating-IP: [10.142.68.147] X-CFilter-Loop: Reflected X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 45.249.212.35 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 09 Dec 2019 14:13:06 -0000 On 2019/12/9 21:05, Beata Michalska wrote: >> Here we set the FnV to not valid, not to set it to valid. >> because Guest will use the physical address that recorded in APEI table. >> > To be precise : the FnV is giving the status of FAR - so what you are setting > here is status of 0b0 which means FAR is valid, not FnV on it's own. > And my point was that you are changing the prototype for syn_data_abort_no_iss > just for this case only so I was just thinking that it might not be > worth that, instead > you could just set it here ... or to be more flexible , provide a way > to set specific bits > on demand. No, I set the FnV to 0b1, not 0b0, the whole esr_el1's value is 0x96000410, as shown below log: I remember changing the prototype for syn_data_abort_no_iss is suggested by Peter Maydell. [1]: [ 62.851830] Internal error: synchronous external abort: 96000410 [#1] PREEMPT SMP [ 62.854465] Modules linked in: > From MAILER-DAEMON Mon Dec 09 09:37:39 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1ieKAN-0001XV-21 for mharc-qemu-arm@gnu.org; Mon, 09 Dec 2019 09:37:39 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:40270) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ieKAK-0001XG-QX for qemu-arm@nongnu.org; Mon, 09 Dec 2019 09:37:38 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ieKAJ-0008PM-BN for qemu-arm@nongnu.org; Mon, 09 Dec 2019 09:37:36 -0500 Received: from mail-wm1-x341.google.com ([2a00:1450:4864:20::341]:54780) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ieKAJ-0008OP-4D for qemu-arm@nongnu.org; Mon, 09 Dec 2019 09:37:35 -0500 Received: by mail-wm1-x341.google.com with SMTP id b11so15739897wmj.4 for ; Mon, 09 Dec 2019 06:37:34 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=ze9o5C9rN/nrAOSr5U48vX+lIHw5KxUruwz9gl3yE10=; b=LF6nP2+uGmuaxVelXb/OGN12zEzzIdZK39FKk24OcEO/mhK08yAPwD2ahBvWuUdRxz bp3IO66FA371MaHZbCGPsspeMqHv12/EIjDlr5OWQAHXfB0g4LgHifO8O3bZR38WP6JQ krxE6xm7J4+cncZnquqOLKi9qPvPdLq7vd8rPb6KI400IPbqY/fD9qeBHJRerzWIjRJT vJAQO3XlCdqolj1uOgdbU8FJFnIt0MTQ1Bc3JddCwYq+KtiIzboVrATQzGxIe+9Rydoq t3DDzrIC2f3p7NtNNhUNdmPCBJDjOJoPF1wPhb7Xk5liWdNwalZtH49OI/HgnOgCIwkV hwcQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=ze9o5C9rN/nrAOSr5U48vX+lIHw5KxUruwz9gl3yE10=; b=Ujp82tWzsR5AKzAjo/I4RU8GEPuKRV2rh3Vn0631ynD4TGimQhkUeEbpTyfcVMEFPY Mpt3hXU3HHrgtbHVEfsx1zSMH36kgKGtxu3Kev/bzuir/dJ9jNM355NIs2xjinvKV47s Us40K2bGcWPn/1nSYWveINR03yPanQmjcDI45J10lSQjrvME/m/qCwhB864VxyhcKQq2 vcNITxGOlB7930qqKzBuQgvaBZrYPMMtRHaDGY6zh7JMvLD2e/vRhfQQpUL8wx6Wqk72 garUBmpGxzNo+rA7iLtxSa1c88q3vRRb7TUerrfkB8DXeciOxPOPBfU1fkkgFnfRT/Sv l5nQ== X-Gm-Message-State: APjAAAW49gmWKNZmlUpbdYu4Z9zIUzQnMILq7Q9iifPI7wh/OdBiY4hQ lcYs49zSbOgJule/UFoPbdOGtQ== X-Google-Smtp-Source: APXvYqwx8UGqeazJKzzsU1g3jr2kkVASx4I0MHroZKBodM+ezU8dJFNi3DEUJXoxEInbdZlQVpmyJg== X-Received: by 2002:a05:600c:1109:: with SMTP id b9mr25227010wma.162.1575902253251; Mon, 09 Dec 2019 06:37:33 -0800 (PST) Received: from zen.linaroharston ([51.148.130.216]) by smtp.gmail.com with ESMTPSA id d16sm29784405wrg.27.2019.12.09.06.37.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 09 Dec 2019 06:37:32 -0800 (PST) Received: from zen.lan (localhost [127.0.0.1]) by zen.linaroharston (Postfix) with ESMTP id 7D4701FF87; Mon, 9 Dec 2019 14:37:31 +0000 (GMT) From: =?UTF-8?q?Alex=20Benn=C3=A9e?= To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, =?UTF-8?q?Alex=20Benn=C3=A9e?= , Richard Henderson , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Peter Maydell Subject: [PATCH] target/arm: ensure we use current exception state after SCR update Date: Mon, 9 Dec 2019 14:37:23 +0000 Message-Id: <20191209143723.6368-1-alex.bennee@linaro.org> X-Mailer: git-send-email 2.20.1 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::341 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 09 Dec 2019 14:37:38 -0000 A write to the SCR can change the effective EL by droppping the system from secure to non-secure mode. However if we use a cached current_el from before the change we'll rebuild the flags incorrectly. To fix this we overload the ARM_CP_CURRENTEL flag for the register and ensure the new EL is used when recomputing the flags. Signed-off-by: Alex Bennée Cc: Richard Henderson Cc: Philippe Mathieu-Daudé --- target/arm/cpu.h | 1 + target/arm/helper.h | 1 + target/arm/helper.c | 14 +++++++++++++- target/arm/translate.c | 6 +++++- 4 files changed, 20 insertions(+), 2 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index bd4d5b4445b..d2ef4644d8f 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -2262,6 +2262,7 @@ static inline uint64_t cpreg_to_kvm_id(uint32_t cpregid) #define ARM_CP_NOP (ARM_CP_SPECIAL | 0x0100) #define ARM_CP_WFI (ARM_CP_SPECIAL | 0x0200) #define ARM_CP_NZCV (ARM_CP_SPECIAL | 0x0300) +/* Re-read the current EL, don't use cached values */ #define ARM_CP_CURRENTEL (ARM_CP_SPECIAL | 0x0400) #define ARM_CP_DC_ZVA (ARM_CP_SPECIAL | 0x0500) #define ARM_LAST_SPECIAL ARM_CP_DC_ZVA diff --git a/target/arm/helper.h b/target/arm/helper.h index 3d4ec267a2c..e345bdb726a 100644 --- a/target/arm/helper.h +++ b/target/arm/helper.h @@ -91,6 +91,7 @@ DEF_HELPER_2(get_user_reg, i32, env, i32) DEF_HELPER_3(set_user_reg, void, env, i32, i32) DEF_HELPER_FLAGS_2(rebuild_hflags_m32, TCG_CALL_NO_RWG, void, env, int) +DEF_HELPER_FLAGS_1(rebuild_hflags_a32_newel, TCG_CALL_NO_RWG, void, env) DEF_HELPER_FLAGS_2(rebuild_hflags_a32, TCG_CALL_NO_RWG, void, env, int) DEF_HELPER_FLAGS_2(rebuild_hflags_a64, TCG_CALL_NO_RWG, void, env, int) diff --git a/target/arm/helper.c b/target/arm/helper.c index 489c31504a6..db2e33224d6 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -5179,7 +5179,7 @@ static const ARMCPRegInfo el3_cp_reginfo[] = { .opc0 = 3, .opc1 = 6, .crn = 1, .crm = 1, .opc2 = 0, .access = PL3_RW, .fieldoffset = offsetof(CPUARMState, cp15.scr_el3), .resetvalue = 0, .writefn = scr_write }, - { .name = "SCR", .type = ARM_CP_ALIAS, + { .name = "SCR", .type = ARM_CP_ALIAS | ARM_CP_CURRENTEL, .cp = 15, .opc1 = 0, .crn = 1, .crm = 1, .opc2 = 0, .access = PL1_RW, .accessfn = access_trap_aa32s_el1, .fieldoffset = offsetoflow32(CPUARMState, cp15.scr_el3), @@ -11437,6 +11437,18 @@ void HELPER(rebuild_hflags_m32)(CPUARMState *env, int el) env->hflags = rebuild_hflags_m32(env, fp_el, mmu_idx); } +/* + * If we have triggered a EL state change we can't rely on the + * translator having passed it too us, we need to recompute. + */ +void HELPER(rebuild_hflags_a32_newel)(CPUARMState *env) +{ + int el = arm_current_el(env); + int fp_el = fp_exception_el(env, el); + ARMMMUIdx mmu_idx = arm_mmu_idx_el(env, el); + env->hflags = rebuild_hflags_a32(env, fp_el, mmu_idx); +} + void HELPER(rebuild_hflags_a32)(CPUARMState *env, int el) { int fp_el = fp_exception_el(env, el); diff --git a/target/arm/translate.c b/target/arm/translate.c index 4d5d4bd8886..59213310065 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -7083,7 +7083,11 @@ static int disas_coproc_insn(DisasContext *s, uint32_t insn) if (arm_dc_feature(s, ARM_FEATURE_M)) { gen_helper_rebuild_hflags_m32(cpu_env, tcg_el); } else { - gen_helper_rebuild_hflags_a32(cpu_env, tcg_el); + if (ri->type & ARM_CP_CURRENTEL) { + gen_helper_rebuild_hflags_a32_newel(cpu_env); + } else { + gen_helper_rebuild_hflags_a32(cpu_env, tcg_el); + } } tcg_temp_free_i32(tcg_el); /* -- 2.20.1 From MAILER-DAEMON Mon Dec 09 09:44:13 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1ieKGj-0005fV-MO for mharc-qemu-arm@gnu.org; Mon, 09 Dec 2019 09:44:13 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:42097) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ieKGg-0005ah-KJ for qemu-arm@nongnu.org; Mon, 09 Dec 2019 09:44:11 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ieKGf-00078R-Ff for qemu-arm@nongnu.org; Mon, 09 Dec 2019 09:44:10 -0500 Received: from us-smtp-delivery-1.mimecast.com ([207.211.31.120]:39188 helo=us-smtp-1.mimecast.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1ieKGf-00078K-Ck for qemu-arm@nongnu.org; Mon, 09 Dec 2019 09:44:09 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1575902649; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; 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[88.21.103.182]) by smtp.gmail.com with ESMTPSA id n10sm27352635wrt.14.2019.12.09.06.44.02 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 09 Dec 2019 06:44:03 -0800 (PST) Subject: Re: [PATCH] target/arm: ensure we use current exception state after SCR update To: =?UTF-8?Q?Alex_Benn=c3=a9e?= , qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Richard Henderson , Peter Maydell References: <20191209143723.6368-1-alex.bennee@linaro.org> From: =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= Message-ID: <1042c399-0bf4-ef61-dec3-0c35822cf530@redhat.com> Date: Mon, 9 Dec 2019 15:44:02 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.2.2 MIME-Version: 1.0 In-Reply-To: <20191209143723.6368-1-alex.bennee@linaro.org> Content-Language: en-US X-MC-Unique: XOT4XOykMbmmzGBfpm68IA-1 X-Mimecast-Spam-Score: 0 Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 207.211.31.120 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 09 Dec 2019 14:44:12 -0000 On 12/9/19 3:37 PM, Alex Benn=C3=A9e wrote: > A write to the SCR can change the effective EL by droppping the system > from secure to non-secure mode. However if we use a cached current_el > from before the change we'll rebuild the flags incorrectly. To fix > this we overload the ARM_CP_CURRENTEL flag for the register and ensure > the new EL is used when recomputing the flags. >=20 > Signed-off-by: Alex Benn=C3=A9e > Cc: Richard Henderson > Cc: Philippe Mathieu-Daud=C3=A9 Thanks! This patch indeed fixes my problem :) Tested-by: Philippe Mathieu-Daud=C3=A9 > --- > target/arm/cpu.h | 1 + > target/arm/helper.h | 1 + > target/arm/helper.c | 14 +++++++++++++- > target/arm/translate.c | 6 +++++- > 4 files changed, 20 insertions(+), 2 deletions(-) >=20 > diff --git a/target/arm/cpu.h b/target/arm/cpu.h > index bd4d5b4445b..d2ef4644d8f 100644 > --- a/target/arm/cpu.h > +++ b/target/arm/cpu.h > @@ -2262,6 +2262,7 @@ static inline uint64_t cpreg_to_kvm_id(uint32_t cpr= egid) > #define ARM_CP_NOP (ARM_CP_SPECIAL | 0x0100) > #define ARM_CP_WFI (ARM_CP_SPECIAL | 0x0200) > #define ARM_CP_NZCV (ARM_CP_SPECIAL | 0x0300) > +/* Re-read the current EL, don't use cached values */ > #define ARM_CP_CURRENTEL (ARM_CP_SPECIAL | 0x0400) > #define ARM_CP_DC_ZVA (ARM_CP_SPECIAL | 0x0500) > #define ARM_LAST_SPECIAL ARM_CP_DC_ZVA > diff --git a/target/arm/helper.h b/target/arm/helper.h > index 3d4ec267a2c..e345bdb726a 100644 > --- a/target/arm/helper.h > +++ b/target/arm/helper.h > @@ -91,6 +91,7 @@ DEF_HELPER_2(get_user_reg, i32, env, i32) > DEF_HELPER_3(set_user_reg, void, env, i32, i32) > =20 > DEF_HELPER_FLAGS_2(rebuild_hflags_m32, TCG_CALL_NO_RWG, void, env, int) > +DEF_HELPER_FLAGS_1(rebuild_hflags_a32_newel, TCG_CALL_NO_RWG, void, env) > DEF_HELPER_FLAGS_2(rebuild_hflags_a32, TCG_CALL_NO_RWG, void, env, int) > DEF_HELPER_FLAGS_2(rebuild_hflags_a64, TCG_CALL_NO_RWG, void, env, int) > =20 > diff --git a/target/arm/helper.c b/target/arm/helper.c > index 489c31504a6..db2e33224d6 100644 > --- a/target/arm/helper.c > +++ b/target/arm/helper.c > @@ -5179,7 +5179,7 @@ static const ARMCPRegInfo el3_cp_reginfo[] =3D { > .opc0 =3D 3, .opc1 =3D 6, .crn =3D 1, .crm =3D 1, .opc2 =3D 0, > .access =3D PL3_RW, .fieldoffset =3D offsetof(CPUARMState, cp15.s= cr_el3), > .resetvalue =3D 0, .writefn =3D scr_write }, > - { .name =3D "SCR", .type =3D ARM_CP_ALIAS, > + { .name =3D "SCR", .type =3D ARM_CP_ALIAS | ARM_CP_CURRENTEL, > .cp =3D 15, .opc1 =3D 0, .crn =3D 1, .crm =3D 1, .opc2 =3D 0, > .access =3D PL1_RW, .accessfn =3D access_trap_aa32s_el1, > .fieldoffset =3D offsetoflow32(CPUARMState, cp15.scr_el3), > @@ -11437,6 +11437,18 @@ void HELPER(rebuild_hflags_m32)(CPUARMState *env= , int el) > env->hflags =3D rebuild_hflags_m32(env, fp_el, mmu_idx); > } > =20 > +/* > + * If we have triggered a EL state change we can't rely on the > + * translator having passed it too us, we need to recompute. > + */ > +void HELPER(rebuild_hflags_a32_newel)(CPUARMState *env) > +{ > + int el =3D arm_current_el(env); > + int fp_el =3D fp_exception_el(env, el); > + ARMMMUIdx mmu_idx =3D arm_mmu_idx_el(env, el); > + env->hflags =3D rebuild_hflags_a32(env, fp_el, mmu_idx); > +} > + > void HELPER(rebuild_hflags_a32)(CPUARMState *env, int el) > { > int fp_el =3D fp_exception_el(env, el); > diff --git a/target/arm/translate.c b/target/arm/translate.c > index 4d5d4bd8886..59213310065 100644 > --- a/target/arm/translate.c > +++ b/target/arm/translate.c > @@ -7083,7 +7083,11 @@ static int disas_coproc_insn(DisasContext *s, uint= 32_t insn) > if (arm_dc_feature(s, ARM_FEATURE_M)) { > gen_helper_rebuild_hflags_m32(cpu_env, tcg_el); > } else { > - gen_helper_rebuild_hflags_a32(cpu_env, tcg_el); > + if (ri->type & ARM_CP_CURRENTEL) { > + gen_helper_rebuild_hflags_a32_newel(cpu_env); > + } else { > + gen_helper_rebuild_hflags_a32(cpu_env, tcg_el); > + } > } > tcg_temp_free_i32(tcg_el); > /* >=20 From MAILER-DAEMON Mon Dec 09 10:36:33 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1ieL5N-0001Da-EL for mharc-qemu-arm@gnu.org; Mon, 09 Dec 2019 10:36:33 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:54770) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ieL5L-0001DG-Aw for qemu-arm@nongnu.org; Mon, 09 Dec 2019 10:36:32 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ieL5J-0003Eb-St for qemu-arm@nongnu.org; Mon, 09 Dec 2019 10:36:31 -0500 Received: from mail-ot1-x344.google.com ([2607:f8b0:4864:20::344]:35524) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ieL5J-0003EJ-Me for qemu-arm@nongnu.org; Mon, 09 Dec 2019 10:36:29 -0500 Received: by mail-ot1-x344.google.com with SMTP id o9so12540673ote.2 for ; Mon, 09 Dec 2019 07:36:29 -0800 (PST) DKIM-Signature: v=1; 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Mon, 09 Dec 2019 07:36:28 -0800 (PST) MIME-Version: 1.0 References: <20191209152456.977399-1-daniel.thompson@linaro.org> In-Reply-To: <20191209152456.977399-1-daniel.thompson@linaro.org> From: Peter Maydell Date: Mon, 9 Dec 2019 15:36:17 +0000 Message-ID: Subject: Re: [PATCH] hw/arm/virt: Second uart for normal-world To: Daniel Thompson Cc: qemu-arm , QEMU Developers , "patches@linaro.org" Content-Type: text/plain; charset="UTF-8" X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::344 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 09 Dec 2019 15:36:33 -0000 On Mon, 9 Dec 2019 at 15:25, Daniel Thompson wrote: > > The virt machine can have two UARTs but the second UART is only > registered when secure-mode support is enabled. Change the machine so > this UART is always registered bringing the behaviour of the virt > machine closer to x86 land, where VMs can be expected to support two > UARTs. This approach is also similar to how a TZPC would typically > make a UART inaccessible to normal world on physical hardware. > > Signed-off-by: Daniel Thompson > --- > > Notes: > It is difficult to add a UART without some kind of odd difference of > behaviour somewhere. As far as I could tell the choices are: > > 1. Move the secure UART from UART1 to UART2. This is a > not-backward-compatible difference of behaviour (will likely break > the command lines for existing users of the secure UART). > > 2. We tack the new UART on at the end, meaning UART1 will re-enumerates > as UART2 when secure mode is enabled/disabled. This is rather > surprising for users. > > 3. UART1 is registered and inaccessible when secure mode is not enabled > (e.g. user must provide a dummy -serial argument to skip the missing > UART) > > 4. Normal world can only use the second UART if there is no secure mode > support. > > 5. Don't support an extra UART ;-) > > Of these I concluded that #4 was least worst! Ultimately it is should be > unsurprising for users because it is how most physical hardware works > (e.g. a trustzone controller is used to make an existing UART > inaccessible to normal world). This change looks simple but it will break booting of UEFI in the guest. Unfortunately UEFI enumerates UARTs in the guest in the opposite order to the Linux kernel, so whichever way round you put the extra UART something will get it wrong and stop producing output where the user expects. I think the conclusion I came to was that the only way to avoid breaking existing command lines would be to only create the second UART if the user explicitly asked for it somehow. (Possibly just looking at "if there really is a 2nd serial on the command line" with "if (serial_hd(1)" would suffice, or perhaps not.) You also need to do something to add the 2nd UART to the ACPI tables. (Very out of date and broken patchset from last time I looked at this: https://lists.gnu.org/archive/html/qemu-arm/2017-12/msg00063.html ) thanks -- PMM From MAILER-DAEMON Mon Dec 09 11:00:49 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1ieLSr-0004F8-EO for mharc-qemu-arm@gnu.org; Mon, 09 Dec 2019 11:00:49 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:57981) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ieLSj-00047Q-QV for qemu-arm@nongnu.org; Mon, 09 Dec 2019 11:00:46 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ieLSi-0002M0-Dx for qemu-arm@nongnu.org; Mon, 09 Dec 2019 11:00:41 -0500 Received: from mail-wr1-x444.google.com ([2a00:1450:4864:20::444]:38237) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ieLSi-0002Jo-6W for qemu-arm@nongnu.org; Mon, 09 Dec 2019 11:00:40 -0500 Received: by mail-wr1-x444.google.com with SMTP id y17so16802867wrh.5 for ; Mon, 09 Dec 2019 08:00:39 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=references:user-agent:from:to:cc:subject:in-reply-to:date :message-id:mime-version:content-transfer-encoding; bh=cJ5tC38qdbylHz6Ukz5CSrO7+ZUQTXXN8j03HEEov2s=; b=MeGRWJOj200Uu7rHuzwpplBuRH7Q9GvxIWKTOfljP1sayybMS7xowlhEGv1E6wQR56 avcwuJPNe/nOIS81trv4ake8nDeXYXsi/xeYkAfp+Gy3Uq85PmRaaeDUx/jIBde37bV4 CWECw69ZSYk8H5S4jHFHlYQMtvqFbLuM+oUCNkgKE0jGNzvDrtBo7BOB8U0OpaqEBwN0 YzJyxCwks+WT72XBvYxK5OH/PRWIekLROUPOl2m7D8hvAM3VgaIAP6+sdlXviLZUYOQN u3HNkgJM9njUcDU+qpOVxxH1DthYsHKtdtMOZyYpNUllXa3vqS0vZkaEkM9/nUHPCzep 0R8Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:references:user-agent:from:to:cc:subject :in-reply-to:date:message-id:mime-version:content-transfer-encoding; bh=cJ5tC38qdbylHz6Ukz5CSrO7+ZUQTXXN8j03HEEov2s=; b=X4YGqh3T0+y1/0dk/b071WbM8gzyRSrh1mmF7KBDQt5y/pPmqVQ7r5jPmgTo4i+ykJ bU/VS+T1vE7mQJRcXF87C/OfyT54O/XTL9WbRI/jB4lzsOwHsHyroZfrZsjty9d7Q3k0 +UwY+wFOhowNU66zE56yjRxoXNHrY0vajEKIQaiw7WfW46waW34xtwpPIeUCYq821s6w a73oX+rnLEekUSkD+xH+GNmibh/ryRmmmyGr+qmv7n5ffgT8pTT8l/Gj4xa7z395tKk5 G1TIud8KgegMEb7fXo0FRnW8Hwvr/b9gG0IWk6Mk6pRidWK/QqBoL6YUdUJwECCBu3M4 RyZg== X-Gm-Message-State: APjAAAUweBjVscD0Pe0I2LPUD6FqVuv/8/YDpgB6p2DGtRakJZSAU6VG UTWbhtfvCkb9HU76XAZtgiY4gw== X-Google-Smtp-Source: APXvYqwxwVDnpCx4in1YK2Qeeh7X/ju/e/aZVEZPADcS/++kleEZ3Hc2tZ/JEw2cJwQ5w6ShvXU/aQ== X-Received: by 2002:a05:6000:1248:: with SMTP id j8mr2921073wrx.44.1575907238651; Mon, 09 Dec 2019 08:00:38 -0800 (PST) Received: from zen.linaroharston ([51.148.130.216]) by smtp.gmail.com with ESMTPSA id v22sm63170wml.11.2019.12.09.08.00.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 09 Dec 2019 08:00:37 -0800 (PST) Received: from zen (localhost [127.0.0.1]) by zen.linaroharston (Postfix) with ESMTP id 86D401FF87; Mon, 9 Dec 2019 16:00:36 +0000 (GMT) References: <20191209134552.27733-1-philmd@redhat.com> User-agent: mu4e 1.3.5; emacs 27.0.50 From: Alex =?utf-8?Q?Benn=C3=A9e?= To: Philippe =?utf-8?Q?Mathieu-Daud=C3=A9?= Cc: qemu-devel@nongnu.org, Peter Maydell , qemu-arm@nongnu.org, Richard Henderson Subject: Re: [PATCH] target/arm: Display helpful message when hflags mismatch In-reply-to: <20191209134552.27733-1-philmd@redhat.com> Date: Mon, 09 Dec 2019 16:00:36 +0000 Message-ID: <87d0cx32vv.fsf@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::444 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 09 Dec 2019 16:00:48 -0000 Philippe Mathieu-Daud=C3=A9 writes: > Instead of crashing in a confuse way, give some hint to the user > about why we aborted. He might report the issue without having > to use a debugger. > > Signed-off-by: Philippe Mathieu-Daud=C3=A9 > --- > target/arm/helper.c | 18 +++++++++++++++--- > 1 file changed, 15 insertions(+), 3 deletions(-) > > diff --git a/target/arm/helper.c b/target/arm/helper.c > index 0bf8f53d4b..6bfb62672b 100644 > --- a/target/arm/helper.c > +++ b/target/arm/helper.c > @@ -11348,6 +11348,20 @@ void HELPER(rebuild_hflags_a64)(CPUARMState *env= , int el) > env->hflags =3D rebuild_hflags_a64(env, el, fp_el, mmu_idx); > } >=20=20 > +static inline void assert_hflags_rebuild_correctly(CPUARMState *env) > +{ > +#ifdef CONFIG_DEBUG_TCG > + uint32_t env_flags_current =3D env->hflags; > + uint32_t env_flags_rebuilt =3D rebuild_hflags_internal(env); > + > + if (unlikely(env_flags_current !=3D env_flags_rebuilt)) { > + fprintf(stderr, "TCG hflags mismatch (current:0x%08x rebuilt:0x%= 08x)\n", > + env_flags_current, env_flags_rebuilt); > + abort(); > + } > +#endif > +} > + > void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc, > target_ulong *cs_base, uint32_t *pflags) > { > @@ -11355,9 +11369,7 @@ void cpu_get_tb_cpu_state(CPUARMState *env, targe= t_ulong *pc, > uint32_t pstate_for_ss; >=20=20 > *cs_base =3D 0; > -#ifdef CONFIG_DEBUG_TCG > - assert(flags =3D=3D rebuild_hflags_internal(env)); > -#endif > + assert_hflags_rebuild_correctly(env); I'm trying to recall why we don't just use: g_assert_cmphex(flags, =3D, rebuild_hflags_internal(env)) I think it came up in one of the reviews. >=20=20 > if (FIELD_EX32(flags, TBFLAG_ANY, AARCH64_STATE)) { > *pc =3D env->pc; --=20 Alex Benn=C3=A9e From MAILER-DAEMON Mon Dec 09 11:42:22 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1ieM74-0002vv-82 for mharc-qemu-arm@gnu.org; Mon, 09 Dec 2019 11:42:22 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:53627) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ieKuO-0002hC-Gz for qemu-arm@nongnu.org; Mon, 09 Dec 2019 10:25:13 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ieKuN-0006VQ-2v for qemu-arm@nongnu.org; Mon, 09 Dec 2019 10:25:12 -0500 Received: from mail-wr1-x444.google.com ([2a00:1450:4864:20::444]:37930) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ieKuM-0006U8-PK for qemu-arm@nongnu.org; Mon, 09 Dec 2019 10:25:11 -0500 Received: by mail-wr1-x444.google.com with SMTP id y17so16667232wrh.5 for ; Mon, 09 Dec 2019 07:25:10 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=aGde4CZaZE2g83epTJ24+hkZLk06bQgpmJ+TMTkjII4=; b=LnvACBIHHIl30sTRb/r3Cefu+ncKuO1uJiadFQydWCKRSfsIH42wpHy5X3aaSWou6R INMnkPlJxvep/tztrMzqi/mL/I36D+JWuXHJOruImZZ7u+80R37hujLCZFTLlMQnMyCN wuM0W9J1mLZBTlobHENItkSuzeXQoslito/jYxvr5JQn1YTAo936/AVoDWFIqxe8r9BF 6eCmeZw2F9j5pa6S4A308zbIaZ4aE+shSWcpNG5aa1+6l+jgZq0qvtgvI5vEdGgD6RU6 y367pRB00srhm6/onSWkHugDp4q9eeJhrT6zPPmPTz/VEuz0ZyxpjCHx7oP04WlmdZIc qvrA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=aGde4CZaZE2g83epTJ24+hkZLk06bQgpmJ+TMTkjII4=; b=MJG4zsFEAu/PaJeo4ckZznMkqARVAU62xh4N6jf+ExBasgYyln7FyaK11b3m6PwVwi gTW9WuitGHcKPDfYWCoHW+QwnPVj/BPNtQFc+b9Eui3YFb0Pq9+9ylG60wkxuaxeOZgM +37IgU91hIBRtbEkTbiPqauGmhKzCFYQwK2Sy4oA3CMmT1Xm9OSn8fK5bNVeSu/41AZc TSuD1RzNVDoCwkFtkmXxYdM2PksN727hRL10QpmRxI4dfGAU4q1ldcMsGmqRiG6S2kJH G036N+CDFR1Ua81cAMCciTRD5RvYUhm+Kf+Z2iONauIeD5oQ0hZnGqUzOhGP6PsVZOxC fOPA== X-Gm-Message-State: APjAAAUsAse2Wllcbk1N2IoPcpK4fxmC3S6M4SGFsjhbNa8LqBpTlI9Y T49mqE1bYCx56rF9BII2G4LeHw== X-Google-Smtp-Source: APXvYqzuy/laWjexzdEipuxFiA5531SrDLRRfqUM2bZmR0ybwssZlMTDLKI1lDHCYXOpnQ6ujdse9A== X-Received: by 2002:adf:ca07:: with SMTP id o7mr2831505wrh.49.1575905108758; Mon, 09 Dec 2019 07:25:08 -0800 (PST) Received: from wychelm.lan (cpc141214-aztw34-2-0-cust773.18-1.cable.virginm.net. [86.9.19.6]) by smtp.gmail.com with ESMTPSA id u18sm27606386wrt.26.2019.12.09.07.25.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 09 Dec 2019 07:25:08 -0800 (PST) From: Daniel Thompson To: Peter Maydell Cc: Daniel Thompson , qemu-arm@nongnu.org, qemu-devel@nongnu.org, patches@linaro.org Subject: [PATCH] hw/arm/virt: Second uart for normal-world Date: Mon, 9 Dec 2019 15:24:55 +0000 Message-Id: <20191209152456.977399-1-daniel.thompson@linaro.org> X-Mailer: git-send-email 2.23.0 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::444 X-Mailman-Approved-At: Mon, 09 Dec 2019 11:42:20 -0500 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 09 Dec 2019 15:25:14 -0000 The virt machine can have two UARTs but the second UART is only registered when secure-mode support is enabled. Change the machine so this UART is always registered bringing the behaviour of the virt machine closer to x86 land, where VMs can be expected to support two UARTs. This approach is also similar to how a TZPC would typically make a UART inaccessible to normal world on physical hardware. Signed-off-by: Daniel Thompson --- Notes: It is difficult to add a UART without some kind of odd difference of behaviour somewhere. As far as I could tell the choices are: 1. Move the secure UART from UART1 to UART2. This is a not-backward-compatible difference of behaviour (will likely break the command lines for existing users of the secure UART). 2. We tack the new UART on at the end, meaning UART1 will re-enumerates as UART2 when secure mode is enabled/disabled. This is rather surprising for users. 3. UART1 is registered and inaccessible when secure mode is not enabled (e.g. user must provide a dummy -serial argument to skip the missing UART) 4. Normal world can only use the second UART if there is no secure mode support. 5. Don't support an extra UART ;-) Of these I concluded that #4 was least worst! Ultimately it is should be unsurprising for users because it is how most physical hardware works (e.g. a trustzone controller is used to make an existing UART inaccessible to normal world). hw/arm/virt.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/hw/arm/virt.c b/hw/arm/virt.c index d4bedc260712..a5cca04dba7f 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -1721,6 +1721,12 @@ static void machvirt_init(MachineState *machine) if (vms->secure) { create_secure_ram(vms, secure_sysmem); create_uart(vms, pic, VIRT_SECURE_UART, secure_sysmem, serial_hd(1)); + } else { + /* + * If secure mode is disabled then let's setup the "secure" + * UART so that normal world can use it. + */ + create_uart(vms, pic, VIRT_SECURE_UART, sysmem, serial_hd(1)); } vms->highmem_ecam &= vms->highmem && (!firmware_loaded || aarch64); base-commit: 8350b17be015bb872f28268bdeba1bac6c380efc -- 2.23.0 From MAILER-DAEMON Mon Dec 09 12:08:38 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1ieMWU-0000Gs-1x for mharc-qemu-arm@gnu.org; Mon, 09 Dec 2019 12:08:38 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:43852) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ieMWR-0000Fd-Jb for qemu-arm@nongnu.org; Mon, 09 Dec 2019 12:08:37 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ieMWQ-0002On-7H for qemu-arm@nongnu.org; Mon, 09 Dec 2019 12:08:35 -0500 Received: from mail-wr1-x444.google.com ([2a00:1450:4864:20::444]:44470) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ieMWQ-0002LZ-0u for qemu-arm@nongnu.org; Mon, 09 Dec 2019 12:08:34 -0500 Received: by mail-wr1-x444.google.com with SMTP id q10so17055345wrm.11 for ; Mon, 09 Dec 2019 09:08:32 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=date:from:to:cc:subject:message-id:references:mime-version :content-disposition:in-reply-to; bh=ioF9gOYZwQRQay1Cw3ZQd95BcX21otjmgrUHOTzhRPc=; b=mTTDgD2+Iw1cBbT3UDV1VWZMAnWhJm0s734NqNT55Za2NLBygIFdPeBj7n0URp2OpP AjpZ+eMJCJFTbPR9d6xxUjExAlK34HbmYOih6iAYV06l9OlPvdI5hm2PP0ggKvZ2XOox HtzH7p4LgLUu6b9azxElwjaYnkASTWoW+7nK7P8zUCqTVgzbV6GMKCekKZq8u1eA01Cl CMNtLHfO/Y7EP/2iP+QPUbPONHZjBCp5vNUlTAFvUpoUcyyw1bluxGZ76AeMFtrpgTcI I9kR7WkMK0xsMLKomSfQYYGBMvWT9m+wdFdLsvBsgJ/a2ZLz+To2n8WbGSVGPuVGRtEd FFFA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:in-reply-to; bh=ioF9gOYZwQRQay1Cw3ZQd95BcX21otjmgrUHOTzhRPc=; b=kF8rqRzmOArn0+BSNaCDVSogj1Ut0R+wIduPiSQ8YmFbPhF+YEjLhJBuPfJ5bTvGjS OUz4vCtYzlm9LVmP7I8mydivec2FOMTvyhj+YL2dJF0uXc/fvMWg/E2Sq8flX3BATBgC HPFtAmABs+P3RzJCObS/S7uy46aELISFN09nwz1y7nsJowfDCKACWL2gQEcXzAz1zCi9 g+1qVuWuBDzx9w0ZVG93Nr374M5DvxwMBKVLWHwsT1/Fl1ZIK45ejfQalEIjUNbhlX9w qPzriW0N4AMUrIiZYVx/bHa7zt5I5PulirHAFyd86UPGo/J+v95C+r6EaWLfk6JwIxK+ 95Pw== X-Gm-Message-State: APjAAAV6QKFE3Yoz8pNZvYLGz9Mz1MWZdpHCOBqzIHzkQyxOfGLkLg5v Uqyytznr4x+dtU3XVzIIq9FX8g== X-Google-Smtp-Source: APXvYqyBab0ty4M+7hsxV+0ALRG1YL6lMBRIkB4UmNU5BJRlAwYcYvmcpES7LAMjhsG11JO4iafvGQ== X-Received: by 2002:adf:ee82:: with SMTP id b2mr3465705wro.194.1575911309788; Mon, 09 Dec 2019 09:08:29 -0800 (PST) Received: from holly.lan (cpc141214-aztw34-2-0-cust773.18-1.cable.virginm.net. [86.9.19.6]) by smtp.gmail.com with ESMTPSA id b185sm428329wme.36.2019.12.09.09.08.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 09 Dec 2019 09:08:29 -0800 (PST) Date: Mon, 9 Dec 2019 17:08:27 +0000 From: Daniel Thompson To: Peter Maydell Cc: qemu-arm , QEMU Developers , "patches@linaro.org" Subject: Re: [PATCH] hw/arm/virt: Second uart for normal-world Message-ID: <20191209170827.yojyts6qdvpxbkp4@holly.lan> References: <20191209152456.977399-1-daniel.thompson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::444 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 09 Dec 2019 17:08:37 -0000 On Mon, Dec 09, 2019 at 03:36:17PM +0000, Peter Maydell wrote: > On Mon, 9 Dec 2019 at 15:25, Daniel Thompson wrote: > > > > The virt machine can have two UARTs but the second UART is only > > registered when secure-mode support is enabled. Change the machine so > > this UART is always registered bringing the behaviour of the virt > > machine closer to x86 land, where VMs can be expected to support two > > UARTs. This approach is also similar to how a TZPC would typically > > make a UART inaccessible to normal world on physical hardware. > > > > Signed-off-by: Daniel Thompson > > --- > > > > Notes: > > It is difficult to add a UART without some kind of odd difference of > > behaviour somewhere. As far as I could tell the choices are: > > > > 1. Move the secure UART from UART1 to UART2. This is a > > not-backward-compatible difference of behaviour (will likely break > > the command lines for existing users of the secure UART). > > > > 2. We tack the new UART on at the end, meaning UART1 will re-enumerates > > as UART2 when secure mode is enabled/disabled. This is rather > > surprising for users. > > > > 3. UART1 is registered and inaccessible when secure mode is not enabled > > (e.g. user must provide a dummy -serial argument to skip the missing > > UART) > > > > 4. Normal world can only use the second UART if there is no secure mode > > support. > > > > 5. Don't support an extra UART ;-) > > > > Of these I concluded that #4 was least worst! Ultimately it is should be > > unsurprising for users because it is how most physical hardware works > > (e.g. a trustzone controller is used to make an existing UART > > inaccessible to normal world). > > This change looks simple but it will break booting of UEFI > in the guest. Unfortunately UEFI enumerates UARTs in the guest > in the opposite order to the Linux kernel, so whichever way > round you put the extra UART something will get it wrong and > stop producing output where the user expects. > > I think the conclusion I came to was that the only way to > avoid breaking existing command lines would be to only > create the second UART if the user explicitly asked for > it somehow. (Possibly just looking at "if there really is > a 2nd serial on the command line" with "if (serial_hd(1)" > would suffice, or perhaps not.) I don't object to making it command line dependant (it is certainly lower risk) but, out of interest, has using /aliases to force the kernel to enumerate the serial nodes in the existing order been ruled out for any reason. With something like the patch below we can give /dev/ttyAMA0 with a stable device number regardless of the order of the UARTs within the DT: diff --git a/hw/arm/virt.c b/hw/arm/virt.c index a5cca04dba7f..7078cfc0c106 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -225,8 +225,12 @@ static void create_fdt(VirtMachineState *vms) qemu_fdt_setprop_cell(fdt, "/", "#address-cells", 0x2); qemu_fdt_setprop_cell(fdt, "/", "#size-cells", 0x2); - /* /chosen must exist for load_dtb to fill in necessary properties later */ + /* + * /chosen and /aliases must exist for load_dtb to fill in + * necessary properties later + */ qemu_fdt_add_subnode(fdt, "/chosen"); + qemu_fdt_add_subnode(fdt, "/aliases"); /* Clock node, for the benefit of the UART. The kernel device tree * binding documentation claims the PL011 node clock properties are @@ -754,6 +758,9 @@ static void create_uart(const VirtMachineState *vms, qemu_irq *pic, int uart, if (uart == VIRT_UART) { qemu_fdt_setprop_string(vms->fdt, "/chosen", "stdout-path", nodename); + qemu_fdt_setprop_string(vms->fdt, "/aliases", "serial0", nodename); + } else if (!vms->secure) { + qemu_fdt_setprop_string(vms->fdt, "/aliases", "serial1", nodename); } else { /* Mark as not usable by the normal world */ qemu_fdt_setprop_string(vms->fdt, nodename, "status", "disabled"); > You also need to do something to add the 2nd UART to the ACPI tables. > > (Very out of date and broken patchset from last time I looked at this: > https://lists.gnu.org/archive/html/qemu-arm/2017-12/msg00063.html > ) Thanks for the heads up. I'll have to do a bit of reading/testing before I get back to you on that! Daniel. From MAILER-DAEMON Mon Dec 09 12:10:45 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1ieMYX-0001nI-Ki for mharc-qemu-arm@gnu.org; Mon, 09 Dec 2019 12:10:45 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:45080) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ieMYV-0001n2-Jd for qemu-arm@nongnu.org; Mon, 09 Dec 2019 12:10:44 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ieMYU-0005wx-Kb for qemu-arm@nongnu.org; Mon, 09 Dec 2019 12:10:43 -0500 Received: from mail-oi1-x242.google.com ([2607:f8b0:4864:20::242]:43383) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ieMYU-0005wT-Fc for qemu-arm@nongnu.org; Mon, 09 Dec 2019 12:10:42 -0500 Received: by mail-oi1-x242.google.com with SMTP id x14so6959687oic.10 for ; Mon, 09 Dec 2019 09:10:42 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=uG0p7uaocyTdM0lZUqiJyB5zKa4/nuiB6lCeMmbQvYg=; b=Vxj318R459k3r1HH7WKzuOobiHupJZ/+ErR13u9Ln0EV651ESx44qpEzkD1N4+S8nC 2geP1OSFmIXo8BqBFHMvjrUt9bK/bVpZeozDuaTzBgLsiFVd6Se+3a1bPG+SgCyqrmXv HEFkOP5ytYA/AtXNsqsxqGUeKjA/+334Nhlyd4QgcZq/bxxCtrXpZV6sbKJaKogpSLnv funYKCiOy6KFZgu1lzZ/HfZwzcL08vI6Dk9+WlP9ggE8AS81M8y5nZUcybNBZ7cj3oXa NURnBXJ7F5DOYDzTs898khBJ8NHxaJzr4IpvKGKxrdsha7x8B0JJ7SGzgU1yCKFnNuLZ adTA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=uG0p7uaocyTdM0lZUqiJyB5zKa4/nuiB6lCeMmbQvYg=; b=VihmClLbLnWOL+65o+2QUzkGRX0H+9goWRe0GoFtUk6TA4LDrJ3b4Kx+Krqf/CrXWI ONHf5Phn98RN94u1InzdLtbNd42oAPzIEE9vIzcnVPss9Ze7LV6tDfhwF5iun+9M0CAE nQFS3+2/5ip0qwuuMBf2Y6CZJN5Iweu9UkTQYojklDTajLeKORBBWZx1yXspFmF7mg6M j8iGmxTqe3h3oaRwUvBqQ2z8nQuPkbfhJpgMs7mR5I8oxJbwZm6ESF0Dgz6He0Vvz8BD uRFUEN+5sZqKdvnwNbk7b6Ah2JKzuoUOnHi/AbJxArnH5kn92l7td+RxgomWWqKNgDyw XZpA== X-Gm-Message-State: APjAAAV25oP45HgPGc04YAAii/uBDsiQ5SGyYhRfJQ0tWOiDC4hMvCaX v3ZkcyE0frO93mxGsFPsWz8ohWLSDPTKd9txihTWaw== X-Google-Smtp-Source: APXvYqxPRr61NIU1WbsewIXezDv84gBakid6F7j379zjtwU9RlCnyRG0iMXGXNEQetueHA1FRmb8lzl6MklJxKOR+Uw= X-Received: by 2002:aca:edd5:: with SMTP id l204mr78252oih.98.1575911441621; Mon, 09 Dec 2019 09:10:41 -0800 (PST) MIME-Version: 1.0 References: <20191209152456.977399-1-daniel.thompson@linaro.org> <20191209170827.yojyts6qdvpxbkp4@holly.lan> In-Reply-To: <20191209170827.yojyts6qdvpxbkp4@holly.lan> From: Peter Maydell Date: Mon, 9 Dec 2019 17:10:30 +0000 Message-ID: Subject: Re: [PATCH] hw/arm/virt: Second uart for normal-world To: Daniel Thompson Cc: qemu-arm , QEMU Developers , "patches@linaro.org" Content-Type: text/plain; charset="UTF-8" X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::242 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 09 Dec 2019 17:10:44 -0000 On Mon, 9 Dec 2019 at 17:08, Daniel Thompson wrote: > I don't object to making it command line dependant (it is certainly > lower risk) but, out of interest, has using /aliases to force the > kernel to enumerate the serial nodes in the existing order been ruled > out for any reason. No, I don't think anybody's investigated that (I wasn't aware that you could do something like that). Bear in mind that the kernel is not the only consumer of the DT, though -- you need to use a mechanism that all DT consumers will handle correctly. thanks -- PMM From MAILER-DAEMON Mon Dec 09 12:39:24 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1ieN0G-0005l7-LS for mharc-qemu-arm@gnu.org; Mon, 09 Dec 2019 12:39:24 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:52233) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ieN0C-0005jR-UH for qemu-arm@nongnu.org; Mon, 09 Dec 2019 12:39:22 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ieN0B-0006Ks-JA for qemu-arm@nongnu.org; Mon, 09 Dec 2019 12:39:20 -0500 Received: from lhrrgout.huawei.com ([185.176.76.210]:2056 helo=huawei.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1ieN0B-0006Je-DP; Mon, 09 Dec 2019 12:39:19 -0500 Received: from lhreml703-cah.china.huawei.com (unknown [172.18.7.107]) by Forcepoint Email with ESMTP id 6CD5060A903E0C8C1D2D; Mon, 9 Dec 2019 17:39:16 +0000 (GMT) Received: from lhreml704-chm.china.huawei.com (10.201.108.53) by lhreml703-cah.china.huawei.com (10.201.108.44) with Microsoft SMTP Server (TLS) id 14.3.408.0; Mon, 9 Dec 2019 17:39:16 +0000 Received: from lhreml710-chm.china.huawei.com (10.201.108.61) by lhreml704-chm.china.huawei.com (10.201.108.53) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5; Mon, 9 Dec 2019 17:39:15 +0000 Received: from lhreml710-chm.china.huawei.com ([169.254.81.184]) by lhreml710-chm.china.huawei.com ([169.254.81.184]) with mapi id 15.01.1713.004; Mon, 9 Dec 2019 17:39:16 +0000 From: Shameerali Kolothum Thodi To: Igor Mammedov , "xiaoguangrong.eric@gmail.com" CC: "peter.maydell@linaro.org" , "drjones@redhat.com" , "shannon.zhaosl@gmail.com" , "qemu-devel@nongnu.org" , Linuxarm , Auger Eric , "qemu-arm@nongnu.org" , "xuwei (O)" , "lersek@redhat.com" Subject: RE: [PATCH 0/5] ARM virt: Add NVDIMM support Thread-Topic: [PATCH 0/5] ARM virt: Add NVDIMM support Thread-Index: AQHVeswdQv2zL2ZjnU2+5S1CywnCCKdgnucAgAYn2ECANV3CUIAANK6AgAADjLCAARyUgIADW0wAgBGftAA= Date: Mon, 9 Dec 2019 17:39:15 +0000 Message-ID: References: <20191004155302.4632-1-shameerali.kolothum.thodi@huawei.com> <441c818f24084b4191315cf2a6267cef@huawei.com> <20191125164541.3f0a593f@redhat.com> <444efcb441fe42e5aff58b3af3ab14b4@huawei.com> <20191126095655.27227f59@redhat.com> Accept-Language: en-GB, en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [10.202.227.237] Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-CFilter-Loop: Reflected X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 185.176.76.210 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 09 Dec 2019 17:39:22 -0000 Hi Igor/ xiaoguangrong, > -----Original Message----- > From: Shameerali Kolothum Thodi > Sent: 28 November 2019 12:36 > To: 'Igor Mammedov' ; > xiaoguangrong.eric@gmail.com > Cc: peter.maydell@linaro.org; drjones@redhat.com; > shannon.zhaosl@gmail.com; qemu-devel@nongnu.org; Linuxarm > ; Auger Eric ; > qemu-arm@nongnu.org; xuwei (O) ; > lersek@redhat.com > Subject: RE: [PATCH 0/5] ARM virt: Add NVDIMM support >=20 >=20 >=20 > > -----Original Message----- > > From: Qemu-devel > > > [mailto:qemu-devel-bounces+shameerali.kolothum.thodi=3Dhuawei.com@nongn > > u.org] On Behalf Of Igor Mammedov > > Sent: 26 November 2019 08:57 > > To: Shameerali Kolothum Thodi > > Cc: peter.maydell@linaro.org; drjones@redhat.com; > > xiaoguangrong.eric@gmail.com; shannon.zhaosl@gmail.com; > > qemu-devel@nongnu.org; Linuxarm ; Auger Eric > > ; qemu-arm@nongnu.org; xuwei (O) > > ; lersek@redhat.com > > Subject: Re: [PATCH 0/5] ARM virt: Add NVDIMM support >=20 > [..] >=20 > > > > 0xb8 Dirty No. -->Another read is attempted > > > > > [Qemu]NVDIMM:nvdimm_dsm_func_read_fit: read_fit_out buf size 0x8 > > > > func_ret_status 3 --> Error status returned > > > > > > > > status 3 means that QEMU didn't like content of NRAM, and there is = only > > > > 1 place like this in nvdimm_dsm_func_read_fit() > > > > if (read_fit->offset > fit->len) { > > > > func_ret_status =3D NVDIMM_DSM_RET_STATUS_INVALID; > > > > goto exit; > > > > } > > > > > > > > so I'd start looking from here and check that QEMU gets expected da= ta > > > > in nvdimm_dsm_write(). In other words I'd try to trace/compare > > > > content of DSM buffer (from qemu side). > > > > > > I had printed the DSM buffer previously and it looked same, I will do= uble > check > > > that. >=20 > Tried printing the buffer in both Qemu/AML code. >=20 > On Amr64, [...] =20 > Attached the SSDT.dsl used for debugging. I am still not clear why on ARM= 64, > 2nd iteration case, the created buffer size in NCAL and RFIT methods have > additional 4 bytes!. >=20 > CreateField (ODAT, Zero, Local1, OBUF) > Concatenate (Buffer (Zero){}, OBUF, Local7) >=20 > Please let me know if you have any clue. >=20 I couldn't figure out yet, why this extra 4 bytes are added by aml code on = ARM64 when the nvdimm_dsm_func_read_fit() returns NvdimmFuncReadFITOut without any FIT data. ie, when the FIT buffer len (read_len) is zero. But the below will fix this issue, diff --git a/hw/acpi/nvdimm.c b/hw/acpi/nvdimm.c index f91eea3802..cddf95f4c1 100644 --- a/hw/acpi/nvdimm.c +++ b/hw/acpi/nvdimm.c @@ -588,7 +588,7 @@ static void nvdimm_dsm_func_read_fit(NVDIMMState *state= , NvdimmDsmIn *in, nvdimm_debug("Read FIT: offset %#x FIT size %#x Dirty %s.\n", read_fit->offset, fit->len, fit_buf->dirty ? "Yes" : "No"= ); - if (read_fit->offset > fit->len) { + if (read_fit->offset >=3D fit->len) { func_ret_status =3D NVDIMM_DSM_RET_STATUS_INVALID; goto exit; } This will return error code to aml in the second iteration when there is no= further FIT data to report. But, I am not sure why this check was omitted in the fi= rst place. Please let me know if this is acceptable and then probably I can look into = a v2 of this series. Thanks, Shameer From MAILER-DAEMON Mon Dec 09 12:51:27 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1ieNBv-0001CX-85 for mharc-qemu-arm@gnu.org; Mon, 09 Dec 2019 12:51:27 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:55897) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ieNBs-00019U-6e for qemu-arm@nongnu.org; Mon, 09 Dec 2019 12:51:25 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ieNBr-0002vr-4X for qemu-arm@nongnu.org; Mon, 09 Dec 2019 12:51:24 -0500 Received: from mail-ot1-x342.google.com ([2607:f8b0:4864:20::342]:41761) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ieNBq-0002vS-TZ for qemu-arm@nongnu.org; Mon, 09 Dec 2019 12:51:23 -0500 Received: by mail-ot1-x342.google.com with SMTP id r27so12936963otc.8 for ; Mon, 09 Dec 2019 09:51:22 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=OypWHPqB8CZ/V92Fqh1GsT7znQ/C5e/e4lOcHCGijus=; b=YDX4QcWfylmrzS7SMTCTNhfGGptDYdF8ojmqUi+p7bf13wwkG+6SrCnjeIRZDWtSN0 OZ62dFYEg7wy4qHyvw9F4GHEDGhfh1pZURMWby4OTYCpJ9QhN+/OB2w71eI/I+v4a9A/ shMNl3Hn8HQDsrqNHlIcKWzBIf9sqvE7ipXGv/lhsNiGEsftc/1hEMgu4SiTnSY1STXd 2ENGgPdzefSR2Vw2tzxOA9jtdCCtKUCymfLLDPUIFtdtk8cPx+2UZ47AdiNhFtfejTg+ pZF3WXMyjF0fIkuQSNvABQD3zpZfrVQLR1EPL/XxR0ODRd6/EKc1geP5oH2ke+eyMr3R Jrrw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=OypWHPqB8CZ/V92Fqh1GsT7znQ/C5e/e4lOcHCGijus=; b=k8zulqZjHe/d7x2mmO5uDKy7rjU3TkUNQoCUMzp+qAV9e3IcYqqZ965rXK7TCCONTf q8c25vZPepHokDsPbWZ7KfUgVHSNqRXcIwn+Qe+0bBPK6VBRtt+I/YpaBHcjA68NOqQB 3vbZN0OAdqK6uD+CwmnIPd7h+Fq/5O041S4mVdklNbpmJqnt71z7b6Lnb4YjWxXnkJqL YRPtJckQ2wZiy63K41Cc9YWvwAmzMOeQScHaRZXRJFsjTXzgTq5FgakdfX+f1Spx5gcs wj09ecY0jB+4oOm/eedm8lUwtFNd9I6dr51JpRXB9yP07wflq//s9ipltI7cFObMTNUA nCTw== X-Gm-Message-State: APjAAAUghapC3Z33MvGMk7s4wvRB25XTtzbrMrDGNwrPhyLHFS3TQHu6 TrU53GV2IMTxPa6ZXiyBToCNujWujNST5jdXTYZUhA== X-Google-Smtp-Source: APXvYqwHOSUtLk0t5QXyOY0CWdRL/tm6o6FSxBCfMjLZOnUP50hdQQe6EBUwVPLEE2pHP5XayjJPX8XuZSxTw6ttgh8= X-Received: by 2002:a05:6830:13d3:: with SMTP id e19mr22868775otq.135.1575913881931; Mon, 09 Dec 2019 09:51:21 -0800 (PST) MIME-Version: 1.0 References: <20191209063719.23086-1-guoheyi@huawei.com> In-Reply-To: <20191209063719.23086-1-guoheyi@huawei.com> From: Peter Maydell Date: Mon, 9 Dec 2019 17:51:10 +0000 Message-ID: Subject: Re: [PATCH v6 0/2] arm/acpi: simplify aml code and enable SHPC To: Heyi Guo Cc: qemu-arm , QEMU Developers , wanghaibin.wang@huawei.com, Shannon Zhao , "Michael S. Tsirkin" , Igor Mammedov Content-Type: text/plain; charset="UTF-8" X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::342 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 09 Dec 2019 17:51:25 -0000 On Mon, 9 Dec 2019 at 06:38, Heyi Guo wrote: > > After the introduction of generic PCIe root port and PCIe-PCI bridge, we will > also have SHPC controller on ARM, and we don't support ACPI hot plug, so just > enable SHPC native hot plug. > > Igor also spotted the store operation outside of bit and/or is not necessary, so > simply the code at first. > > v6: > - Fix "make check" errors by updating tests/data/acpi/virt/DSDT*. > > v5: > - Refine commit message of patch 1/2 > > v4: > - Improve the code indention. > > Cc: Shannon Zhao > Cc: Peter Maydell > Cc: "Michael S. Tsirkin" > Cc: Igor Mammedov Thanks, applied to target-arm.next. (it's a bit awkward that acpi table updates require also updating a bunch of binary test files, but I suppose trying to make the golden-reference be some textual format would be not very feasible.) thanks -- PMM From MAILER-DAEMON Mon Dec 09 12:57:15 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1ieNHX-00054r-1o for mharc-qemu-arm@gnu.org; Mon, 09 Dec 2019 12:57:15 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:56859) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ieNHT-0004zt-OV for qemu-arm@nongnu.org; Mon, 09 Dec 2019 12:57:12 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ieNHS-0004mu-O7 for qemu-arm@nongnu.org; Mon, 09 Dec 2019 12:57:11 -0500 Received: from mail-oi1-x241.google.com ([2607:f8b0:4864:20::241]:38740) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ieNHS-0004md-JJ for qemu-arm@nongnu.org; Mon, 09 Dec 2019 12:57:10 -0500 Received: by mail-oi1-x241.google.com with SMTP id b8so7148175oiy.5 for ; Mon, 09 Dec 2019 09:57:10 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc:content-transfer-encoding; bh=lKXlVuxkWEUUPeb9LOuGSqHW5akNYDaoRPQweqBFnWY=; b=gMxvqQ7/qVHRP74un03Z7LiyW5Qm537Q8uHZXNdLncuU0rKXpbwkrP9eTXnjM1OoXZ xOBFyoKib8Livc4EeHHWk0wjCIColNqllox4jXgJKyitvw0N3RCssBpN60DWDb0litpY vg/sLkctapRcIzyjA5wB8TdDbQZS+kNgIdRK3q1VQrjdmfk0eeWLjgPo2n9Q7wqIdMxf xuYm0EG+iazbz6Oa37qiu3VFye7F7EEDw6bfnISEOK+X3iH9/mVbYdWyxomz8Q/i1iOB p5Dq61PphPABufgdqKWa1GLvhZZCRiumG2q424BLBmToimw2VhboogsaHy8ZJXdkNe4Q ObVA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc:content-transfer-encoding; bh=lKXlVuxkWEUUPeb9LOuGSqHW5akNYDaoRPQweqBFnWY=; b=P9VmI1MA6iwVzQFtRLWay19kUDATp0v6cHvQwal7IQKBHXlXR1NbUR4TJ5hV1GmIwl GWVIZRD45PAXb6LgxsMKD07yD354gexXOnmNCQN3Y3T82Rri5DPmB8Q5m4ZjeDDTU9W+ xq5GMZr6cGfwaJSWPtwPp1vwAfoXpx8/B3dT/ldTKSl6Cf0W+bajtHFytlp9bvE1bm3R lThbMrNHgwoYOJeqdfz6/8Ti2etSChlVBUxFuMghORVeo8S4fvAsdh8bDopq3vxsQtRV BRHfzSMuwQMqnQkIgwMd7kDKL2Q6fLneaF08csjIzk5Naopuq9JB760zePesCyGVCQmY jQ0w== X-Gm-Message-State: APjAAAV6/kJo7cKcD+VcQHKrFimkBOj02Tk5IIVPjCHnipwvhmfkLTZu e7+Frd2IkkB2EZFsVf5Djd00ps17ZXLXewZjX/Xl2Q== X-Google-Smtp-Source: APXvYqx7Exkmbj6LfNvuCBymecwolihDrSf70G2OZntF+krMomgpiFKdfJDix5UcOvaToisC605JRUhBYc1y8FUubvA= X-Received: by 2002:aca:f484:: with SMTP id s126mr255085oih.48.1575914229769; Mon, 09 Dec 2019 09:57:09 -0800 (PST) MIME-Version: 1.0 References: <20191209090306.20433-1-philmd@redhat.com> In-Reply-To: <20191209090306.20433-1-philmd@redhat.com> From: Peter Maydell Date: Mon, 9 Dec 2019 17:56:58 +0000 Message-ID: Subject: Re: [PATCH] hw/arm/virt: Simplify by moving the gic in the machine state To: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= Cc: QEMU Developers , Luc Michel , qemu-arm Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::241 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 09 Dec 2019 17:57:13 -0000 On Mon, 9 Dec 2019 at 09:03, Philippe Mathieu-Daud=C3=A9 wrote: > > Make the gic a field in the machine state, and instead of filling > an array of qemu_irq and passing it around, directly call > qdev_get_gpio_in() on the gic field. > > Signed-off-by: Philippe Mathieu-Daud=C3=A9 > --- > include/hw/arm/virt.h | 1 + > hw/arm/virt.c | 109 +++++++++++++++++++++--------------------- > 2 files changed, 55 insertions(+), 55 deletions(-) > Applied to target-arm.next, thanks. -- PMM From MAILER-DAEMON Mon Dec 09 14:05:20 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1ieOLQ-00036l-8Y for mharc-qemu-arm@gnu.org; Mon, 09 Dec 2019 14:05:20 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:49848) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ieOLN-00033I-IU for qemu-arm@nongnu.org; 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Mon, 09 Dec 2019 16:22:12 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:48096) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ieQTq-0005LK-0u for qemu-arm@nongnu.org; Mon, 09 Dec 2019 16:22:11 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ieQTo-0007GG-Cn for qemu-arm@nongnu.org; Mon, 09 Dec 2019 16:22:09 -0500 Received: from mail.ilande.co.uk ([46.43.2.167]:41154 helo=mail.default.ilande.uk0.bigv.io) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1ieQTo-0005UC-66; Mon, 09 Dec 2019 16:22:08 -0500 Received: from host86-185-91-45.range86-185.btcentralplus.com ([86.185.91.45] helo=[192.168.1.65]) by mail.default.ilande.uk0.bigv.io with esmtpsa (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.89) (envelope-from ) id 1ieQRT-0006et-Ii; Mon, 09 Dec 2019 21:19:44 +0000 To: bilalwasim676@gmail.com, qemu-devel@nongnu.org Cc: peter.maydell@linaro.org, philmd@redhat.com, jasowang@redhat.com, qemu-arm@nongnu.org, bilal_wasim@mentor.com References: <20191207215623.16532-1-bilalwasim676@gmail.com> From: Mark Cave-Ayland Autocrypt: addr=mark.cave-ayland@ilande.co.uk; keydata= mQENBFQJuzwBCADAYvxrwUh1p/PvUlNFwKosVtVHHplgWi5p29t58QlOUkceZG0DBYSNqk93 3JzBTbtd4JfFcSupo6MNNOrCzdCbCjZ64ik8ycaUOSzK2tKbeQLEXzXoaDL1Y7vuVO7nL9bG E5Ru3wkhCFc7SkoypIoAUqz8EtiB6T89/D9TDEyjdXUacc53R5gu8wEWiMg5MQQuGwzbQy9n PFI+mXC7AaEUqBVc2lBQVpAYXkN0EyqNNT12UfDLdxaxaFpUAE2pCa2LTyo5vn5hEW+i3VdN PkmjyPvL6DdY03fvC01PyY8zaw+UI94QqjlrDisHpUH40IUPpC/NB0LwzL2aQOMkzT2NABEB AAG0ME1hcmsgQ2F2ZS1BeWxhbmQgPG1hcmsuY2F2ZS1heWxhbmRAaWxhbmRlLmNvLnVrPokB OAQTAQIAIgUCVAm7PAIbAwYLCQgHAwIGFQgCCQoLBBYCAwECHgECF4AACgkQW8LFb64PMh9f NAgAuc3ObOEY8NbZko72AGrg2tWKdybcMVITxmcor4hb9155o/OWcA4IDbeATR6cfiDL/oxU mcmtXVgPqOwtW3NYAKr5g/FrZZ3uluQ2mtNYAyTFeALy8YF7N3yhs7LOcpbFP7tEbkSzoXNG z8iYMiYtKwttt40WaheWuRs0ZOLbs6yoczZBDhna3Nj0LA3GpeJKlaV03O4umjKJgACP1c/q T2Pkg+FCBHHFP454+waqojHp4OCBo6HyK+8I4wJRa9Z0EFqXIu8lTDYoggeX0Xd6bWeCFHK3 DhD0/Xi/kegSW33unsp8oVcM4kcFxTkpBgj39dB4KwAUznhTJR0zUHf63LkBDQRUCbs8AQgA y7kyevA4bpetM/EjtuqQX4U05MBhEz/2SFkX6IaGtTG2NNw5wbcAfhOIuNNBYbw6ExuaJ3um 2uLseHnudmvN4VSJ5Hfbd8rhqoMmmO71szgT/ZD9MEe2KHzBdmhmhxJdp+zQNivy215j6H27 14mbC2dia7ktwP1rxPIX1OOfQwPuqlkmYPuVwZP19S4EYnCELOrnJ0m56tZLn5Zj+1jZX9Co YbNLMa28qsktYJ4oU4jtn6V79H+/zpERZAHmH40IRXdR3hA+Ye7iC/ZpWzT2VSDlPbGY9Yja Sp7w2347L5G+LLbAfaVoejHlfy/msPeehUcuKjAdBLoEhSPYzzdvEQARAQABiQEfBBgBAgAJ BQJUCbs8AhsMAAoJEFvCxW+uDzIfabYIAJXmBepHJpvCPiMNEQJNJ2ZSzSjhic84LTMWMbJ+ opQgr5cb8SPQyyb508fc8b4uD8ejlF/cdbbBNktp3BXsHlO5BrmcABgxSP8HYYNsX0n9kERv NMToU0oiBuAaX7O/0K9+BW+3+PGMwiu5ml0cwDqljxfVN0dUBZnQ8kZpLsY+WDrIHmQWjtH+ Ir6VauZs5Gp25XLrL6bh/SL8aK0BX6y79m5nhfKI1/6qtzHAjtMAjqy8ChPvOqVVVqmGUzFg KPsrrIoklWcYHXPyMLj9afispPVR8e0tMKvxzFBWzrWX1mzljbBlnV2n8BIwVXWNbgwpHSsj imgcU9TTGC5qd9g= Message-ID: Date: Mon, 9 Dec 2019 21:18:48 +0000 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.2.2 MIME-Version: 1.0 In-Reply-To: <20191207215623.16532-1-bilalwasim676@gmail.com> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 7bit X-SA-Exim-Connect-IP: 86.185.91.45 X-SA-Exim-Mail-From: mark.cave-ayland@ilande.co.uk Subject: Re: [PATCH v2] Adding support for MAC filtering in the FEC IP implementation. X-SA-Exim-Version: 4.2.1 (built Tue, 02 Aug 2016 21:08:31 +0000) X-SA-Exim-Scanned: Yes (on mail.default.ilande.uk0.bigv.io) X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 46.43.2.167 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 09 Dec 2019 21:22:11 -0000 On 07/12/2019 21:56, bilalwasim676@gmail.com wrote: > From: Bilal Wasim > > This addition ensures that the IP does NOT boot up in > promiscuous mode by default, and so the software only receives the desired > packets(Unicast, Broadcast, Unicast / Multicast hashed) by default. The > software running on-top of QEMU can also modify these settings and disable > reception of broadcast frames or make the IP receive all packets (PROM mode). > This patch greatly reduces the number of packets received by the software > running on-top of the QEMU model. Tested with the armv7-a SABRE_LITE machine. > Testing included running a custom OS with IPv4 / IPv6 support. Hashing and > filtering of packets is tested to work well. Skeleton taken from the > CADENCE_GEM IP and hash generation algorithm from the Linux Kernel. > > Signed-off-by: Bilal Wasim > --- > hw/net/imx_fec.c | 117 ++++++++++++++++++++++++++++++++++++++- > include/hw/net/imx_fec.h | 12 ++++ > 2 files changed, 128 insertions(+), 1 deletion(-) > > diff --git a/hw/net/imx_fec.c b/hw/net/imx_fec.c > index bd99236864..cc1572b5fe 100644 > --- a/hw/net/imx_fec.c > +++ b/hw/net/imx_fec.c > @@ -419,6 +419,87 @@ static void imx_enet_write_bd(IMXENETBufDesc *bd, dma_addr_t addr) > dma_memory_write(&address_space_memory, addr, bd, sizeof(*bd)); > } > > +/* > + * Calculate a FEC MAC Address hash index > + */ > +static unsigned calc_mac_hash(const uint8_t *mac, uint8_t mac_length) > +{ > + uint32_t crc = -1; > + int i; > + > + while (mac_length--) { > + crc ^= *mac++; > + for (i = 0; i < 8; i++) { > + crc = (crc >> 1) ^ ((crc & 1) ? CRCPOLY_LE : 0); > + } > + } Can you not use the existing net_crc32_le() function here? > + /* > + * only upper 6 bits (FEC_HASH_BITS) are used > + * which point to specific bit in the hash registers > + */ > + return (crc >> (32 - FEC_HASH_BITS)) & 0x3f; > +} > + > +/* > + * fec_mac_address_filter: > + * Accept or reject this destination address? > + */ > +static int fec_mac_address_filter(IMXFECState *s, const uint8_t *packet) > +{ > + const uint8_t broadcast_addr[] = { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }; > + uint32_t addr1, addr2; > + uint8_t hash; > + > + /* Promiscuous mode? */ > + if (s->regs[ENET_RCR] & ENET_RCR_PROM) { > + /* Accept all packets in promiscuous mode (even if bc_rej is set). */ > + return FEC_RX_PROMISCUOUS_ACCEPT; > + } > + > + /* Broadcast packet? */ > + if (!memcmp(packet, broadcast_addr, 6)) { > + /* Reject broadcast packets? */ > + if (s->regs[ENET_RCR] & ENET_RCR_BC_REJ) { > + return FEC_RX_REJECT; > + } > + /* Accept packets from broadcast address. */ > + return FEC_RX_BROADCAST_ACCEPT; > + } > + > + /* Accept packets -w- hash match? */ > + hash = calc_mac_hash(packet, 6); > + > + /* Accept packets -w- multicast hash match? */ > + if ((packet[0] & 0x01) == 0x01) { > + /* Computed hash matches GAUR / GALR register ? */ > + if (((hash < 32) && (s->regs[ENET_GALR] & (1 << hash))) > + || ((hash > 31) && (s->regs[ENET_GAUR] & (1 << (hash - 32))))) { > + /* Accept multicast hash enabled address. */ > + return FEC_RX_MULTICAST_HASH_ACCEPT; > + } > + } else { > + /* Computed hash matches IAUR / IALR register ? */ > + if (((hash < 32) && (s->regs[ENET_IALR] & (1 << hash))) > + || ((hash > 31) && (s->regs[ENET_IAUR] & (1 << (hash - 32))))) { > + /* Accept multicast hash enabled address. */ > + return FEC_RX_UNICAST_HASH_ACCEPT; > + } > + } > + > + /* Match Unicast address. */ > + addr1 = g_htonl(s->regs[ENET_PALR]); > + addr2 = g_htonl(s->regs[ENET_PAUR]); > + if (!(memcmp(packet, (uint8_t *) &addr1, 4) || > + memcmp(packet + 4, (uint8_t *) &addr2, 2))) { > + /* Accept packet because it matches my unicast address. */ > + return FEC_RX_UNICAST_ACCEPT; > + } > + > + /* Return -1 because we do NOT support MAC address filtering.. */ > + return FEC_RX_REJECT; > +} > + > static void imx_eth_update(IMXFECState *s) > { > /* > @@ -984,7 +1065,7 @@ static void imx_eth_write(void *opaque, hwaddr offset, uint64_t value, > case ENET_IALR: > case ENET_GAUR: > case ENET_GALR: > - /* TODO: implement MAC hash filtering. */ > + s->regs[index] |= value; > break; > case ENET_TFWR: > if (s->is_fec) { > @@ -1066,8 +1147,15 @@ static ssize_t imx_fec_receive(NetClientState *nc, const uint8_t *buf, > uint32_t buf_addr; > uint8_t *crc_ptr; > unsigned int buf_len; > + int maf; > size_t size = len; > > + /* Is this destination MAC address "for us" ? */ > + maf = fec_mac_address_filter(s, buf); > + if (maf == FEC_RX_REJECT) { > + return FEC_RX_REJECT; > + } > + > FEC_PRINTF("len %d\n", (int)size); > > if (!s->regs[ENET_RDAR]) { > @@ -1133,6 +1221,16 @@ static ssize_t imx_fec_receive(NetClientState *nc, const uint8_t *buf, > } else { > s->regs[ENET_EIR] |= ENET_INT_RXB; > } > + > + /* Update descriptor based on the "maf" flag. */ > + if (maf == FEC_RX_BROADCAST_ACCEPT) { > + /* The packet is destined for the "broadcast" address. */ > + bd.flags |= ENET_BD_BC; > + } else if (maf == FEC_RX_MULTICAST_HASH_ACCEPT) { > + /* The packet is destined for a "multicast" address. */ > + bd.flags |= ENET_BD_MC; > + } > + > imx_fec_write_bd(&bd, addr); > /* Advance to the next descriptor. */ > if ((bd.flags & ENET_BD_W) != 0) { > @@ -1159,8 +1257,15 @@ static ssize_t imx_enet_receive(NetClientState *nc, const uint8_t *buf, > uint8_t *crc_ptr; > unsigned int buf_len; > size_t size = len; > + int maf; > bool shift16 = s->regs[ENET_RACC] & ENET_RACC_SHIFT16; > > + /* Is this destination MAC address "for us" ? */ > + maf = fec_mac_address_filter(s, buf); > + if (maf == FEC_RX_REJECT) { > + return FEC_RX_REJECT; > + } > + > FEC_PRINTF("len %d\n", (int)size); > > if (!s->regs[ENET_RDAR]) { > @@ -1254,6 +1359,16 @@ static ssize_t imx_enet_receive(NetClientState *nc, const uint8_t *buf, > s->regs[ENET_EIR] |= ENET_INT_RXB; > } > } > + > + /* Update descriptor based on the "maf" flag. */ > + if (maf == FEC_RX_BROADCAST_ACCEPT) { > + /* The packet is destined for the "broadcast" address. */ > + bd.flags |= ENET_BD_BC; > + } else if (maf == FEC_RX_MULTICAST_HASH_ACCEPT) { > + /* The packet is destined for a "multicast" address. */ > + bd.flags |= ENET_BD_MC; > + } > + > imx_enet_write_bd(&bd, addr); > /* Advance to the next descriptor. */ > if ((bd.flags & ENET_BD_W) != 0) { > diff --git a/include/hw/net/imx_fec.h b/include/hw/net/imx_fec.h > index 7b3faa4019..d38c8fe0e8 100644 > --- a/include/hw/net/imx_fec.h > +++ b/include/hw/net/imx_fec.h > @@ -275,4 +275,16 @@ typedef struct IMXFECState { > uint8_t frame[ENET_MAX_FRAME_SIZE]; > } IMXFECState; > > +/* FEC address filtering defines. */ > +#define FEC_RX_REJECT (-1) > +#define FEC_RX_PROMISCUOUS_ACCEPT (-2) > +#define FEC_RX_BROADCAST_ACCEPT (-3) > +#define FEC_RX_MULTICAST_HASH_ACCEPT (-4) > +#define FEC_RX_UNICAST_HASH_ACCEPT (-5) > +#define FEC_RX_UNICAST_ACCEPT (-6) > + > +/* FEC hash filtering defines.*/ > +#define CRCPOLY_LE 0xedb88320 > +#define FEC_HASH_BITS 6 /* #bits in hash */ > + > #endif ATB, Mark. From MAILER-DAEMON Mon Dec 09 16:38:24 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1ieQjX-0000YH-UG for mharc-qemu-arm@gnu.org; Mon, 09 Dec 2019 16:38:23 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:52201) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ieQjT-0000Tn-Mg for qemu-arm@nongnu.org; Mon, 09 Dec 2019 16:38:22 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ieQjQ-0000PH-BH for qemu-arm@nongnu.org; Mon, 09 Dec 2019 16:38:19 -0500 Received: from mail-io1-xd43.google.com ([2607:f8b0:4864:20::d43]:40225) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ieQjJ-0000Jd-Hj; Mon, 09 Dec 2019 16:38:09 -0500 Received: by mail-io1-xd43.google.com with SMTP id x1so16461744iop.7; Mon, 09 Dec 2019 13:38:09 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=+3gENAQHq1UU/H8cZE00XySCflDEESuT84KXr3tGvfU=; b=KJ+56I8PwFNuZ+qvE/C7tg+UwTqdIzvAVhw9gI/KqlaEqkhqcwj8Kpmt/2WeAO+2cP UbI3+kMh1MCPewqzrLtMZNLMzUUWtCyc2/UckPmatXog9BYKPfQaGPj/LVupsI3mt6BX roErji0Jr6c9GbdVrRSLPyTaiZMbNo3Wej3mbVRkusMkBFU3Zr6EOrsMJaBsnVUeu0Y2 9PpRsDRlz+Rgejn1yJXbI3epy6yz4P3FRlC62wr06NCxGJABHuQJhhtJW0s1gfchSyNA o7x5SRyqbhL4PFMn++s7X8VN4wHZxvfYjc/q2N+WWRkZuY9ivJJWR2QiDbEUznRzkixC VQQw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=+3gENAQHq1UU/H8cZE00XySCflDEESuT84KXr3tGvfU=; b=ouZgYDkHJt/CY/DWyowop/voP4CLPcB5djZyEvOFzxqCN4fcSW8fOxMu407ueOOsHI ltSXZvcdX82hmrsYGJ2+OOig4S7FpeGTaKbgXl1D1ZgWPIRtFMZ4y7Fu0bnDMJ/J8OnT 0QqpvieWo7OKR6mQRUuScgdWsBZ39s1J/zdeadlhTyMPmCR5ngSizGLUNnpdyhYTysHv ZXW69bni0Fo44mfOUDHgZ2xuIH8029nPZZv/KDkZt+4vz5fqjSHnhEEThApRJJLDss0+ qqZqaoYgj46v3x3Lz/jkOvCjGOUVBgDxakPWTUxF4mvAwFe0it5nkydBaSxKwW47GYhp OfVA== X-Gm-Message-State: APjAAAVCSq5XrS4mNRN3+UrmdYapaSd7khHDJ0br02b3mqYNvdG1inDW dLA86lnPIr+CurKcfA0sS+eNNZUS/G3QCp51tlA= X-Google-Smtp-Source: APXvYqzQjQUXANuzG0GV3wJi6fBujd3iBiaG4oQ8pQesxX1ybESAA13RkeNEwALtGqoO1TobYbc8auxplrQ3icHpLiU= X-Received: by 2002:a6b:6f01:: with SMTP id k1mr23023234ioc.28.1575927488222; Mon, 09 Dec 2019 13:38:08 -0800 (PST) MIME-Version: 1.0 References: <20191202210947.3603-1-nieklinnenbank@gmail.com> In-Reply-To: From: Niek Linnenbank Date: Mon, 9 Dec 2019 22:37:57 +0100 Message-ID: Subject: Re: [PATCH 00/10] Add Allwinner H3 SoC and Orange Pi PC Machine To: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= Cc: QEMU Developers , Beniamino Galvani , Peter Maydell , qemu-arm , Richard Henderson Content-Type: multipart/alternative; boundary="000000000000209d5b05994c3674" X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::d43 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 09 Dec 2019 21:38:23 -0000 --000000000000209d5b05994c3674 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Hi Philippe, On Tue, Dec 3, 2019 at 9:47 AM Philippe Mathieu-Daud=C3=A9 wrote: > On 12/2/19 10:09 PM, Niek Linnenbank wrote: > > Dear QEMU developers, > > > > Hereby I would like to contribute the following set of patches to QEMU > > which add support for the Allwinner H3 System on Chip and the > > Orange Pi PC machine. The following features and devices are supported: > > > > * SMP (Quad Core Cortex A7) > > * Generic Interrupt Controller configuration > > * SRAM mappings > > * Timer device (re-used from Allwinner A10) > > * UART > > * SD/MMC storage controller > > * EMAC ethernet connectivity > > * USB 2.0 interfaces > > * Clock Control Unit > > * System Control module > > * Security Identifier device > > Awesome! > > > Functionality related to graphical output such as HDMI, GPU, > > Display Engine and audio are not included. Recently released > > mainline Linux kernels (4.19 up to latest master) and mainline U-Boot > > are known to work. The SD/MMC code is tested using bonnie++ and > > various tools such as fsck, dd and fdisk. The EMAC is verified with > iperf3 > > using -netdev socket. > > > > To build a Linux mainline kernel that can be booted by the Orange Pi PC > > machine, simply configure the kernel using the sunxi_defconfig > configuration: > > $ ARCH=3Darm CROSS_COMPILE=3Darm-linux-gnueabi- make mrproper > > $ ARCH=3Darm CROSS_COMPILE=3Darm-linux-gnueabi- make sunxi_defconfig > > > > To be able to use USB storage, you need to manually enable the > corresponding > > configuration item. Start the kconfig configuration tool: > > $ ARCH=3Darm CROSS_COMPILE=3Darm-linux-gnueabi- make menuconfig > > > > Navigate to the following item, enable it and save your configuration: > > Device Drivers > USB support > USB Mass Storage support > > > > Build the Linux kernel with: > > $ ARCH=3Darm CROSS_COMPILE=3Darm-linux-gnueabi- make -j5 > > > > To boot the newly build linux kernel in QEMU with the Orange Pi PC > machine, use: > > $ qemu-system-arm -M orangepi -m 512 -nic user -nographic \ > > -kernel /path/to/linux/arch/arm/boot/zImage \ > > -append 'console=3DttyS0,115200' \ > > -dtb /path/to/linux/arch/arm/boot/dts/sun8i-h3-orangepi-pc.dtb > > > > Note that this kernel does not have a root filesystem. You may provide = it > > with an official Orange Pi PC image [1] either as an SD card or as > > USB mass storage. To boot using the Orange Pi PC Debian image on SD car= d, > > simply add the -sd argument and provide the proper root=3D kernel > parameter: > > $ qemu-system-arm -M orangepi -m 512 -nic user -nographic \ > > -kernel /path/to/linux/arch/arm/boot/zImage \ > > -append 'console=3DttyS0,115200 root=3D/dev/mmcblk0p2' \ > > -dtb /path/to/linux/arch/arm/boot/dts/sun8i-h3-orangepi-pc.dtb \ > > -sd OrangePi_pc_debian_stretch_server_linux5.3.5_v1.0.img > > > > Alternatively, you can also choose to build and boot a recent buildroot > [2] > > using the orangepi_pc_defconfig or Armbian image [3] for Orange Pi PC. > > Richard, trying the Armbian image from > https://apt.armbian.com/pool/main/l/linux-4.20.7-sunxi/ I get: > > $ arm-softmmu/qemu-system-arm -M orangepi -m 512 -nic user \ > -append 'console=3DttyS0,115200' \ > -kernel boot/vmlinuz-4.20.7-sunxi \ > -dtb usr/lib/linux-image-dev-sunxi/sun8i-h3-orangepi-pc.dtb \ > -serial stdio -d unimp > Uncompressing Linux... done, booting the kernel. > rtc: unimplemented device write (size 4, value 0x16aa0001, offset 0x0) > rtc: unimplemented device read (size 4, offset 0x0) > rtc: unimplemented device read (size 4, offset 0x0) > rtc: unimplemented device read (size 4, offset 0x8) > qemu-system-arm: target/arm/helper.c:11359: cpu_get_tb_cpu_state: > Assertion `flags =3D=3D rebuild_hflags_internal(env)' failed. > Aborted (core dumped) > I'm trying to reproduce the error you reported here with my patch set on latest master, but so far without any result. The host OS I'm using is Ubuntu 18.04.3 LTS on x86_64. I ran several times using the same 4.20.7-sunxi kernel and same command line. Some questions that might help: 1) Are there any specific steps you did in order to produce this error? 2) Could this be a known / existing issue? 3) How many times did you see this error? 4) Are you also using Ubuntu 18.04.3 LTS on x86_64, or a different host OS? Regards, Niek > > (gdb) bt > #0 0x00007f6c1fa2ce35 in raise () at /lib64/libc.so.6 > #1 0x00007f6c1fa17895 in abort () at /lib64/libc.so.6 > #2 0x00007f6c1fa17769 in _nl_load_domain.cold () at /lib64/libc.so.6 > #3 0x00007f6c1fa25566 in annobin_assert.c_end () at /lib64/libc.so.6 > #4 0x00005590657e2685 in cpu_get_tb_cpu_state (env=3D0x5590686899b0, > pc=3D0x7f6c07ffa718, cs_base=3D0x7f6c07ffa714, pflags=3D0x7f6c07ffa71c) a= t > target/arm/helper.c:11359 > #5 0x000055906569f962 in tb_lookup__cpu_state (cpu=3D0x5590686808b0, > pc=3D0x7f6c07ffa718, cs_base=3D0x7f6c07ffa714, flags=3D0x7f6c07ffa71c, > cf_mask=3D524288) at include/exec/tb-lookup.h:28 > #6 0x00005590656a084c in tb_find (cpu=3D0x5590686808b0, last_tb=3D0x0, > tb_exit=3D0, cf_mask=3D524288) at accel/tcg/cpu-exec.c:403 > #7 0x00005590656a114a in cpu_exec (cpu=3D0x5590686808b0) at > accel/tcg/cpu-exec.c:730 > #8 0x000055906565f6af in tcg_cpu_exec (cpu=3D0x5590686808b0) at cpus.c:1= 473 > #9 0x000055906565ff05 in qemu_tcg_cpu_thread_fn (arg=3D0x5590686808b0) a= t > cpus.c:1781 > #10 0x0000559065d54aa6 in qemu_thread_start (args=3D0x5590687d8c20) at > util/qemu-thread-posix.c:519 > #11 0x00007f6c1fbc54c0 in start_thread () at /lib64/libpthread.so.0 > #12 0x00007f6c1faf1553 in clone () at /lib64/libc.so.6 > > (gdb) p/x flags > $1 =3D 0x33600000 > > (gdb) p/x *env > $2 =3D {regs =3D {0x0 , 0x40102448}, xregs =3D {0x0 32 times>}, pc =3D 0x0, pstate =3D 0x0, aarch64 =3D 0x0, hflags =3D 0x336= 00000, > uncached_cpsr =3D 0x1a, spsr =3D 0x0, banked_spsr =3D {0x0, 0x0, 0x0, 0x0= , > 0x0, 0x0, 0x0, 0x0}, > banked_r13 =3D {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, banked_r14 = =3D > {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, usr_regs =3D {0x0, 0x0, 0x0, > 0x0, 0x0}, fiq_regs =3D {0x0, 0x0, 0x0, 0x0, 0x0}, CF =3D 0x0, VF =3D 0x0= , NF > =3D 0x0, ZF =3D 0x0, > QF =3D 0x0, GE =3D 0x0, thumb =3D 0x1, condexec_bits =3D 0x0, btype = =3D 0x0, > daif =3D 0x3c0, elr_el =3D {0x0, 0x0, 0x0, 0x0}, sp_el =3D {0x0, 0x0, 0x0= , > 0x0}, cp15 =3D {c0_cpuid =3D 0x410fc075, {{_unused_csselr0 =3D 0x0, cssel= r_ns > =3D 0x0, > _unused_csselr1 =3D 0x0, csselr_s =3D 0x0}, csselr_el =3D {0x0, = 0x0, > 0x0, 0x0}}, {{_unused_sctlr =3D 0x0, sctlr_ns =3D 0xc50078, hsctlr =3D 0x= 0, > sctlr_s =3D 0xc50078}, sctlr_el =3D {0x0, 0xc50078, 0x0, 0xc50078}}, > cpacr_el1 =3D 0x0, cptr_el =3D { > 0x0, 0x0, 0x0, 0x0}, c1_xscaleauxcr =3D 0x0, sder =3D 0x0, nsacr = =3D > 0xc00, {{_unused_ttbr0_0 =3D 0x0, ttbr0_ns =3D 0x0, _unused_ttbr0_1 =3D 0= x0, > ttbr0_s =3D 0x0}, ttbr0_el =3D {0x0, 0x0, 0x0, 0x0}}, {{_unused_ttbr1_0 = =3D > 0x0, ttbr1_ns =3D 0x0, > _unused_ttbr1_1 =3D 0x0, ttbr1_s =3D 0x0}, ttbr1_el =3D {0x0, 0x= 0, > 0x0, 0x0}}, vttbr_el2 =3D 0x0, tcr_el =3D {{raw_tcr =3D 0x0, mask =3D 0x0= , > base_mask =3D 0x0}, {raw_tcr =3D 0x0, mask =3D 0x0, base_mask =3D 0xffffc= 000}, > {raw_tcr =3D 0x0, mask =3D 0x0, > base_mask =3D 0x0}, {raw_tcr =3D 0x0, mask =3D 0x0, base_mask = =3D > 0xffffc000}}, vtcr_el2 =3D {raw_tcr =3D 0x0, mask =3D 0x0, base_mask =3D = 0x0}, > c2_data =3D 0x0, c2_insn =3D 0x0, {{dacr_ns =3D 0x0, dacr_s =3D 0x0}, > {dacr32_el2 =3D 0x0}}, > pmsav5_data_ap =3D 0x0, pmsav5_insn_ap =3D 0x0, hcr_el2 =3D 0x0, scr= _el3 > =3D 0x101, {{ifsr_ns =3D 0x0, ifsr_s =3D 0x0}, {ifsr32_el2 =3D 0x0}}, > {{_unused_dfsr =3D 0x0, dfsr_ns =3D 0x0, hsr =3D 0x0, dfsr_s =3D 0x0}, es= r_el =3D > {0x0, 0x0, 0x0, 0x0}}, > c6_region =3D {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, > {{_unused_far0 =3D 0x0, dfar_ns =3D 0x0, ifar_ns =3D 0x0, dfar_s =3D 0x0,= ifar_s > =3D 0x0, _unused_far3 =3D 0x0}, far_el =3D {0x0, 0x0, 0x0, 0x0}}, hpfar_e= l2 =3D > 0x0, hstr_el2 =3D 0x0, {{ > _unused_par_0 =3D 0x0, par_ns =3D 0x0, _unused_par_1 =3D 0x0, pa= r_s =3D > 0x0}, par_el =3D {0x0, 0x0, 0x0, 0x0}}, c9_insn =3D 0x0, c9_data =3D 0x0, > c9_pmcr =3D 0x41002000, c9_pmcnten =3D 0x0, c9_pmovsr =3D 0x0, c9_pmusere= nr =3D > 0x0, c9_pmselr =3D 0x0, > c9_pminten =3D 0x0, {{_unused_mair_0 =3D 0x0, mair0_ns =3D 0x0, mair= 1_ns > =3D 0x0, _unused_mair_1 =3D 0x0, mair0_s =3D 0x0, mair1_s =3D 0x0}, mair_= el =3D > {0x0, 0x0, 0x0, 0x0}}, {{_unused_vbar =3D 0x0, vbar_ns =3D 0x0, hvbar =3D= 0x0, > vbar_s =3D 0x0}, > vbar_el =3D {0x0, 0x0, 0x0, 0x0}}, mvbar =3D 0x0, {fcseidr_ns =3D = 0x0, > fcseidr_s =3D 0x0}, {{_unused_contextidr_0 =3D 0x0, contextidr_ns =3D 0x0= , > _unused_contextidr_1 =3D 0x0, contextidr_s =3D 0x0}, contextidr_el =3D {0= x0, > 0x0, 0x0, 0x0}}, {{ > tpidrurw_ns =3D 0x0, tpidrprw_ns =3D 0x0, htpidr =3D 0x0, _tpidr= _el3 > =3D 0x0}, tpidr_el =3D {0x0, 0x0, 0x0, 0x0}}, tpidrurw_s =3D 0x0, tpidrpr= w_s =3D > 0x0, tpidruro_s =3D 0x0, {tpidruro_ns =3D 0x0, tpidrro_el =3D {0x0}}, > c14_cntfrq =3D 0x3b9aca0, > c14_cntkctl =3D 0x0, cnthctl_el2 =3D 0x3, cntvoff_el2 =3D 0x0, c14_t= imer > =3D {{cval =3D 0x0, ctl =3D 0x0}, {cval =3D 0x0, ctl =3D 0x0}, {cval =3D = 0x0, ctl =3D > 0x0}, {cval =3D 0x0, ctl =3D 0x0}}, c15_cpar =3D 0x0, c15_ticonfig =3D 0x= 0, > c15_i_max =3D 0x0, > c15_i_min =3D 0x0, c15_threadid =3D 0x0, c15_config_base_address =3D= 0x0, > c15_diagnostic =3D 0x0, c15_power_diagnostic =3D 0x0, c15_power_control = =3D > 0x0, dbgbvr =3D {0x0 }, dbgbcr =3D {0x0 times>}, dbgwvr =3D { > 0x0 }, dbgwcr =3D {0x0 }, > mdscr_el1 =3D 0x0, oslsr_el1 =3D 0xa, mdcr_el2 =3D 0x0, mdcr_el3 =3D 0x0, > c15_ccnt =3D 0x0, c15_ccnt_delta =3D 0x0, c14_pmevcntr =3D {0x0 times>}, c14_pmevcntr_delta =3D { > 0x0 }, c14_pmevtyper =3D {0x0 times>}, pmccfiltr_el0 =3D 0x0, vpidr_el2 =3D 0x410fc075, vmpidr_el2 =3D > 0x80000001}, v7m =3D {other_sp =3D 0x0, other_ss_msp =3D 0x0, other_ss_ps= p =3D > 0x0, vecbase =3D {0x0, 0x0}, > basepri =3D {0x0, 0x0}, control =3D {0x0, 0x0}, ccr =3D {0x0, 0x0}, = cfsr > =3D {0x0, 0x0}, hfsr =3D 0x0, dfsr =3D 0x0, sfsr =3D 0x0, mmfar =3D {0x0,= 0x0}, > bfar =3D 0x0, sfar =3D 0x0, mpu_ctrl =3D {0x0, 0x0}, exception =3D 0x0, p= rimask > =3D {0x0, 0x0}, > faultmask =3D {0x0, 0x0}, aircr =3D 0x0, secure =3D 0x0, csselr =3D = {0x0, > 0x0}, scr =3D {0x0, 0x0}, msplim =3D {0x0, 0x0}, psplim =3D {0x0, 0x0}, f= pcar > =3D {0x0, 0x0}, fpccr =3D {0x0, 0x0}, fpdscr =3D {0x0, 0x0}, cpacr =3D {0= x0, > 0x0}, nsacr =3D 0x0}, > exception =3D {syndrome =3D 0x0, fsr =3D 0x0, vaddress =3D 0x0, target= _el =3D > 0x0}, serror =3D {pending =3D 0x0, has_esr =3D 0x0, esr =3D 0x0}, irq_lin= e_state > =3D 0x0, teecr =3D 0x0, teehbr =3D 0x0, vfp =3D {zregs =3D {{d =3D {0x0, = 0x0}} > }, > qc =3D {0x0, 0x0, 0x0, 0x0}, vec_len =3D 0x0, vec_stride =3D 0x0, xr= egs =3D > {0x41023075, 0x0, 0x0, 0x0, 0x0, 0x0, 0x11111111, 0x10110222, 0x0, 0x0, > 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, scratch =3D {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, > 0x0, 0x0}, > fp_status =3D {float_detect_tininess =3D 0x1, float_rounding_mode = =3D > 0x0, float_exception_flags =3D 0x0, floatx80_rounding_precision =3D 0x0, > flush_to_zero =3D 0x0, flush_inputs_to_zero =3D 0x0, default_nan_mode =3D= 0x0, > snan_bit_is_one =3D 0x0}, > fp_status_f16 =3D {float_detect_tininess =3D 0x1, float_rounding_mod= e =3D > 0x0, float_exception_flags =3D 0x0, floatx80_rounding_precision =3D 0x0, > flush_to_zero =3D 0x0, flush_inputs_to_zero =3D 0x0, default_nan_mode =3D= 0x0, > snan_bit_is_one =3D 0x0}, standard_fp_status =3D > {float_detect_tininess =3D 0x1, float_rounding_mode =3D 0x0, > float_exception_flags =3D 0x0, floatx80_rounding_precision =3D 0x0, > flush_to_zero =3D 0x1, flush_inputs_to_zero =3D 0x1, > default_nan_mode =3D 0x1, snan_bit_is_one =3D 0x0}, zcr_el =3D {0x= 0, > 0x0, 0x0, 0x0}}, exclusive_addr =3D 0xffffffffffffffff, exclusive_val =3D > 0x0, exclusive_high =3D 0x0, iwmmxt =3D {regs =3D {0x0 = }, > val =3D 0x0, cregs =3D { > 0x0 }}, cpu_breakpoint =3D {0x0 times>}, cpu_watchpoint =3D {0x0 }, end_reset_fields = =3D > {}, features =3D 0xfd38fbe6f3, pmsav7 =3D {drbar =3D 0x0,= drsr > =3D 0x0, dracr =3D 0x0, > rnr =3D {0x0, 0x0}}, pmsav8 =3D {rbar =3D {0x0, 0x0}, rlar =3D {0x0,= 0x0}, > mair0 =3D {0x0, 0x0}, mair1 =3D {0x0, 0x0}}, sau =3D {rbar =3D 0x0, rlar = =3D 0x0, > rnr =3D 0x0, ctrl =3D 0x0}, nvic =3D 0x0, boot_info =3D 0x5622af3a17a0, > gicv3state =3D 0x0} > > > [1] http://www.orangepi.org/downloadresources/ > > [2] https://buildroot.org/download.html > > [3] https://www.armbian.com/orange-pi-pc/ > > --=20 Niek Linnenbank --000000000000209d5b05994c3674 Content-Type: text/html; charset="UTF-8" Content-Transfer-Encoding: quoted-printable
Hi Philippe,

=
On Tue, Dec 3, 2019 at 9:47 AM Philip= pe Mathieu-Daud=C3=A9 <philmd@redha= t.com> wrote:
On 12/2/19 10:09 PM, Niek Linnenbank wrote:
> Dear QEMU developers,
>
> Hereby I would like to contribute the following set of patches to QEMU=
> which add support for the Allwinner H3 System on Chip and the
> Orange Pi PC machine. The following features and devices are supported= :
>
>=C2=A0 =C2=A0* SMP (Quad Core Cortex A7)
>=C2=A0 =C2=A0* Generic Interrupt Controller configuration
>=C2=A0 =C2=A0* SRAM mappings
>=C2=A0 =C2=A0* Timer device (re-used from Allwinner A10)
>=C2=A0 =C2=A0* UART
>=C2=A0 =C2=A0* SD/MMC storage controller
>=C2=A0 =C2=A0* EMAC ethernet connectivity
>=C2=A0 =C2=A0* USB 2.0 interfaces
>=C2=A0 =C2=A0* Clock Control Unit
>=C2=A0 =C2=A0* System Control module
>=C2=A0 =C2=A0* Security Identifier device

Awesome!

> Functionality related to graphical output such as HDMI, GPU,
> Display Engine and audio are not included. Recently released
> mainline Linux kernels (4.19 up to latest master) and mainline U-Boot<= br> > are known to work. The SD/MMC code is tested using bonnie++ and
> various tools such as fsck, dd and fdisk. The EMAC is verified with ip= erf3
> using -netdev socket.
>
> To build a Linux mainline kernel that can be booted by the Orange Pi P= C
> machine, simply configure the kernel using the sunxi_defconfig configu= ration:
>=C2=A0 =C2=A0$ ARCH=3Darm CROSS_COMPILE=3Darm-linux-gnueabi- make mrpro= per
>=C2=A0 =C2=A0$ ARCH=3Darm CROSS_COMPILE=3Darm-linux-gnueabi- make sunxi= _defconfig
>
> To be able to use USB storage, you need to manually enable the corresp= onding
> configuration item. Start the kconfig configuration tool:
>=C2=A0 =C2=A0$ ARCH=3Darm CROSS_COMPILE=3Darm-linux-gnueabi- make menuc= onfig
>
> Navigate to the following item, enable it and save your configuration:=
>=C2=A0 =C2=A0Device Drivers > USB support > USB Mass Storage supp= ort
>
> Build the Linux kernel with:
>=C2=A0 =C2=A0$ ARCH=3Darm CROSS_COMPILE=3Darm-linux-gnueabi- make -j5 >
> To boot the newly build linux kernel in QEMU with the Orange Pi PC mac= hine, use:
>=C2=A0 =C2=A0$ qemu-system-arm -M orangepi -m 512 -nic user -nographic = \
>=C2=A0 =C2=A0 =C2=A0 =C2=A0-kernel /path/to/linux/arch/arm/boot/zImage = \
>=C2=A0 =C2=A0 =C2=A0 =C2=A0-append 'console=3DttyS0,115200' \ >=C2=A0 =C2=A0 =C2=A0 =C2=A0-dtb /path/to/linux/arch/arm/boot/dts/sun8i-= h3-orangepi-pc.dtb
>
> Note that this kernel does not have a root filesystem. You may provide= it
> with an official Orange Pi PC image [1] either as an SD card or as
> USB mass storage. To boot using the Orange Pi PC Debian image on SD ca= rd,
> simply add the -sd argument and provide the proper root=3D kernel para= meter:
>=C2=A0 =C2=A0$ qemu-system-arm -M orangepi -m 512 -nic user -nographic = \
>=C2=A0 =C2=A0 =C2=A0 =C2=A0-kernel /path/to/linux/arch/arm/boot/zImage = \
>=C2=A0 =C2=A0 =C2=A0 =C2=A0-append 'console=3DttyS0,115200 root=3D/= dev/mmcblk0p2' \
>=C2=A0 =C2=A0 =C2=A0 =C2=A0-dtb /path/to/linux/arch/arm/boot/dts/sun8i-= h3-orangepi-pc.dtb \
>=C2=A0 =C2=A0 =C2=A0 =C2=A0-sd OrangePi_pc_debian_stretch_server_linux5= .3.5_v1.0.img
>
> Alternatively, you can also choose to build and boot a recent buildroo= t [2]
> using the orangepi_pc_defconfig or Armbian image [3] for Orange Pi PC.=

Richard, trying the Armbian image from
https://apt.armbian.com/pool/main/l/linux-4.2= 0.7-sunxi/ I get:

$ arm-softmmu/qemu-system-arm -M orangepi -m 512 -nic user \
=C2=A0 =C2=A0-append 'console=3DttyS0,115200' \
=C2=A0 =C2=A0-kernel boot/vmlinuz-4.20.7-sunxi \
=C2=A0 =C2=A0-dtb usr/lib/linux-image-dev-sunxi/sun8i-h3-orangepi-pc.dtb \<= br> =C2=A0 =C2=A0-serial stdio -d unimp
Uncompressing Linux... done, booting the kernel.
rtc: unimplemented device write (size 4, value 0x16aa0001, offset 0x0)
rtc: unimplemented device read (size 4, offset 0x0)
rtc: unimplemented device read (size 4, offset 0x0)
rtc: unimplemented device read (size 4, offset 0x8)
qemu-system-arm: target/arm/helper.c:11359: cpu_get_tb_cpu_state:
Assertion `flags =3D=3D rebuild_hflags_internal(env)' failed.
Aborted (core dumped)

I'm trying to= reproduce the error you reported here with my patch set on latest master,<= /div>
but so far without any result. The host OS I'm using is Ubunt= u 18.04.3 LTS on x86_64.
I ran several times using the same 4.20.= 7-sunxi kernel and same command line.

Some questio= ns that might help:
1) Are there any specific steps you did i= n order to produce this error?
2) Could this be a known / existin= g issue?
3) How many times did you see this error?
= 4) Are you also using Ubuntu 18.04.3 LTS on x86_64, or a different host OS?=

Regards,
Niek
=C2=A0

(gdb) bt
#0=C2=A0 0x00007f6c1fa2ce35 in raise () at /lib64/libc.so.6
#1=C2=A0 0x00007f6c1fa17895 in abort () at /lib64/libc.so.6
#2=C2=A0 0x00007f6c1fa17769 in _nl_load_domain.cold () at /lib64/libc.so.6<= br> #3=C2=A0 0x00007f6c1fa25566 in annobin_assert.c_end () at /lib64/libc.so.6<= br> #4=C2=A0 0x00005590657e2685 in cpu_get_tb_cpu_state (env=3D0x5590686899b0, =
pc=3D0x7f6c07ffa718, cs_base=3D0x7f6c07ffa714, pflags=3D0x7f6c07ffa71c) at =
target/arm/helper.c:11359
#5=C2=A0 0x000055906569f962 in tb_lookup__cpu_state (cpu=3D0x5590686808b0, =
pc=3D0x7f6c07ffa718, cs_base=3D0x7f6c07ffa714, flags=3D0x7f6c07ffa71c,
cf_mask=3D524288) at include/exec/tb-lookup.h:28
#6=C2=A0 0x00005590656a084c in tb_find (cpu=3D0x5590686808b0, last_tb=3D0x0= ,
tb_exit=3D0, cf_mask=3D524288) at accel/tcg/cpu-exec.c:403
#7=C2=A0 0x00005590656a114a in cpu_exec (cpu=3D0x5590686808b0) at
accel/tcg/cpu-exec.c:730
#8=C2=A0 0x000055906565f6af in tcg_cpu_exec (cpu=3D0x5590686808b0) at cpus.= c:1473
#9=C2=A0 0x000055906565ff05 in qemu_tcg_cpu_thread_fn (arg=3D0x5590686808b0= ) at
cpus.c:1781
#10 0x0000559065d54aa6 in qemu_thread_start (args=3D0x5590687d8c20) at
util/qemu-thread-posix.c:519
#11 0x00007f6c1fbc54c0 in start_thread () at /lib64/libpthread.so.0
#12 0x00007f6c1faf1553 in clone () at /lib64/libc.so.6

(gdb) p/x flags
$1 =3D 0x33600000

(gdb) p/x *env
$2 =3D {regs =3D {0x0 <repeats 15 times>, 0x40102448}, xregs =3D {0x0= <repeats
32 times>}, pc =3D 0x0, pstate =3D 0x0, aarch64 =3D 0x0, hflags =3D 0x33= 600000,
uncached_cpsr =3D 0x1a, spsr =3D 0x0, banked_spsr =3D {0x0, 0x0, 0x0, 0x0, =
0x0, 0x0, 0x0, 0x0},
=C2=A0 =C2=A0banked_r13 =3D {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, banke= d_r14 =3D
{0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, usr_regs =3D {0x0, 0x0, 0x0,
0x0, 0x0}, fiq_regs =3D {0x0, 0x0, 0x0, 0x0, 0x0}, CF =3D 0x0, VF =3D 0x0, = NF
=3D 0x0, ZF =3D 0x0,
=C2=A0 =C2=A0QF =3D 0x0, GE =3D 0x0, thumb =3D 0x1, condexec_bits =3D 0x0, = btype =3D 0x0,
daif =3D 0x3c0, elr_el =3D {0x0, 0x0, 0x0, 0x0}, sp_el =3D {0x0, 0x0, 0x0, =
0x0}, cp15 =3D {c0_cpuid =3D 0x410fc075, {{_unused_csselr0 =3D 0x0, csselr_= ns
=3D 0x0,
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0_unused_csselr1 =3D 0x0, csselr_s =3D 0x0= }, csselr_el =3D {0x0, 0x0,
0x0, 0x0}}, {{_unused_sctlr =3D 0x0, sctlr_ns =3D 0xc50078, hsctlr =3D 0x0,=
sctlr_s =3D 0xc50078}, sctlr_el =3D {0x0, 0xc50078, 0x0, 0xc50078}},
cpacr_el1 =3D 0x0, cptr_el =3D {
=C2=A0 =C2=A0 =C2=A0 =C2=A00x0, 0x0, 0x0, 0x0}, c1_xscaleauxcr =3D 0x0, sde= r =3D 0x0, nsacr =3D
0xc00, {{_unused_ttbr0_0 =3D 0x0, ttbr0_ns =3D 0x0, _unused_ttbr0_1 =3D 0x0= ,
ttbr0_s =3D 0x0}, ttbr0_el =3D {0x0, 0x0, 0x0, 0x0}}, {{_unused_ttbr1_0 =3D=
0x0, ttbr1_ns =3D 0x0,
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0_unused_ttbr1_1 =3D 0x0, ttbr1_s =3D 0x0}= , ttbr1_el =3D {0x0, 0x0,
0x0, 0x0}}, vttbr_el2 =3D 0x0, tcr_el =3D {{raw_tcr =3D 0x0, mask =3D 0x0, =
base_mask =3D 0x0}, {raw_tcr =3D 0x0, mask =3D 0x0, base_mask =3D 0xffffc00= 0},
{raw_tcr =3D 0x0, mask =3D 0x0,
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0base_mask =3D 0x0}, {raw_tcr =3D 0x0, mas= k =3D 0x0, base_mask =3D
0xffffc000}}, vtcr_el2 =3D {raw_tcr =3D 0x0, mask =3D 0x0, base_mask =3D 0x= 0},
c2_data =3D 0x0, c2_insn =3D 0x0, {{dacr_ns =3D 0x0, dacr_s =3D 0x0},
{dacr32_el2 =3D 0x0}},
=C2=A0 =C2=A0 =C2=A0pmsav5_data_ap =3D 0x0, pmsav5_insn_ap =3D 0x0, hcr_el2= =3D 0x0, scr_el3
=3D 0x101, {{ifsr_ns =3D 0x0, ifsr_s =3D 0x0}, {ifsr32_el2 =3D 0x0}},
{{_unused_dfsr =3D 0x0, dfsr_ns =3D 0x0, hsr =3D 0x0, dfsr_s =3D 0x0}, esr_= el =3D
{0x0, 0x0, 0x0, 0x0}},
=C2=A0 =C2=A0 =C2=A0c6_region =3D {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},=
{{_unused_far0 =3D 0x0, dfar_ns =3D 0x0, ifar_ns =3D 0x0, dfar_s =3D 0x0, i= far_s
=3D 0x0, _unused_far3 =3D 0x0}, far_el =3D {0x0, 0x0, 0x0, 0x0}}, hpfar_el2= =3D
0x0, hstr_el2 =3D 0x0, {{
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0_unused_par_0 =3D 0x0, par_ns =3D 0x0, _u= nused_par_1 =3D 0x0, par_s =3D
0x0}, par_el =3D {0x0, 0x0, 0x0, 0x0}}, c9_insn =3D 0x0, c9_data =3D 0x0, <= br> c9_pmcr =3D 0x41002000, c9_pmcnten =3D 0x0, c9_pmovsr =3D 0x0, c9_pmuserenr= =3D
0x0, c9_pmselr =3D 0x0,
=C2=A0 =C2=A0 =C2=A0c9_pminten =3D 0x0, {{_unused_mair_0 =3D 0x0, mair0_ns = =3D 0x0, mair1_ns
=3D 0x0, _unused_mair_1 =3D 0x0, mair0_s =3D 0x0, mair1_s =3D 0x0}, mair_el= =3D
{0x0, 0x0, 0x0, 0x0}}, {{_unused_vbar =3D 0x0, vbar_ns =3D 0x0, hvbar =3D 0= x0,
vbar_s =3D 0x0},
=C2=A0 =C2=A0 =C2=A0 =C2=A0vbar_el =3D {0x0, 0x0, 0x0, 0x0}}, mvbar =3D 0x0= , {fcseidr_ns =3D 0x0,
fcseidr_s =3D 0x0}, {{_unused_contextidr_0 =3D 0x0, contextidr_ns =3D 0x0, =
_unused_contextidr_1 =3D 0x0, contextidr_s =3D 0x0}, contextidr_el =3D {0x0= ,
0x0, 0x0, 0x0}}, {{
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0tpidrurw_ns =3D 0x0, tpidrprw_ns =3D 0x0,= htpidr =3D 0x0, _tpidr_el3
=3D 0x0}, tpidr_el =3D {0x0, 0x0, 0x0, 0x0}}, tpidrurw_s =3D 0x0, tpidrprw_= s =3D
0x0, tpidruro_s =3D 0x0, {tpidruro_ns =3D 0x0, tpidrro_el =3D {0x0}},
c14_cntfrq =3D 0x3b9aca0,
=C2=A0 =C2=A0 =C2=A0c14_cntkctl =3D 0x0, cnthctl_el2 =3D 0x3, cntvoff_el2 = =3D 0x0, c14_timer
=3D {{cval =3D 0x0, ctl =3D 0x0}, {cval =3D 0x0, ctl =3D 0x0}, {cval =3D 0x= 0, ctl =3D
0x0}, {cval =3D 0x0, ctl =3D 0x0}}, c15_cpar =3D 0x0, c15_ticonfig =3D 0x0,=
c15_i_max =3D 0x0,
=C2=A0 =C2=A0 =C2=A0c15_i_min =3D 0x0, c15_threadid =3D 0x0, c15_config_bas= e_address =3D 0x0,
c15_diagnostic =3D 0x0, c15_power_diagnostic =3D 0x0, c15_power_control =3D=
0x0, dbgbvr =3D {0x0 <repeats 16 times>}, dbgbcr =3D {0x0 <repeats= 16
times>}, dbgwvr =3D {
=C2=A0 =C2=A0 =C2=A0 =C2=A00x0 <repeats 16 times>}, dbgwcr =3D {0x0 &= lt;repeats 16 times>},
mdscr_el1 =3D 0x0, oslsr_el1 =3D 0xa, mdcr_el2 =3D 0x0, mdcr_el3 =3D 0x0, <= br> c15_ccnt =3D 0x0, c15_ccnt_delta =3D 0x0, c14_pmevcntr =3D {0x0 <repeats= 31
times>}, c14_pmevcntr_delta =3D {
=C2=A0 =C2=A0 =C2=A0 =C2=A00x0 <repeats 31 times>}, c14_pmevtyper =3D= {0x0 <repeats 31
times>}, pmccfiltr_el0 =3D 0x0, vpidr_el2 =3D 0x410fc075, vmpidr_el2 =3D=
0x80000001}, v7m =3D {other_sp =3D 0x0, other_ss_msp =3D 0x0, other_ss_psp = =3D
0x0, vecbase =3D {0x0, 0x0},
=C2=A0 =C2=A0 =C2=A0basepri =3D {0x0, 0x0}, control =3D {0x0, 0x0}, ccr =3D= {0x0, 0x0}, cfsr
=3D {0x0, 0x0}, hfsr =3D 0x0, dfsr =3D 0x0, sfsr =3D 0x0, mmfar =3D {0x0, 0= x0},
bfar =3D 0x0, sfar =3D 0x0, mpu_ctrl =3D {0x0, 0x0}, exception =3D 0x0, pri= mask
=3D {0x0, 0x0},
=C2=A0 =C2=A0 =C2=A0faultmask =3D {0x0, 0x0}, aircr =3D 0x0, secure =3D 0x0= , csselr =3D {0x0,
0x0}, scr =3D {0x0, 0x0}, msplim =3D {0x0, 0x0}, psplim =3D {0x0, 0x0}, fpc= ar
=3D {0x0, 0x0}, fpccr =3D {0x0, 0x0}, fpdscr =3D {0x0, 0x0}, cpacr =3D {0x0= ,
0x0}, nsacr =3D 0x0},
=C2=A0 =C2=A0exception =3D {syndrome =3D 0x0, fsr =3D 0x0, vaddress =3D 0x0= , target_el =3D
0x0}, serror =3D {pending =3D 0x0, has_esr =3D 0x0, esr =3D 0x0}, irq_line_= state
=3D 0x0, teecr =3D 0x0, teehbr =3D 0x0, vfp =3D {zregs =3D {{d =3D {0x0, 0x= 0}}
<repeats 32 times>},
=C2=A0 =C2=A0 =C2=A0qc =3D {0x0, 0x0, 0x0, 0x0}, vec_len =3D 0x0, vec_strid= e =3D 0x0, xregs =3D
{0x41023075, 0x0, 0x0, 0x0, 0x0, 0x0, 0x11111111, 0x10110222, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, scratch =3D {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, <= br> 0x0, 0x0},
=C2=A0 =C2=A0 =C2=A0fp_status =3D {float_detect_tininess =3D 0x1, float_rou= nding_mode =3D
0x0, float_exception_flags =3D 0x0, floatx80_rounding_precision =3D 0x0, flush_to_zero =3D 0x0, flush_inputs_to_zero =3D 0x0, default_nan_mode =3D 0= x0,
snan_bit_is_one =3D 0x0},
=C2=A0 =C2=A0 =C2=A0fp_status_f16 =3D {float_detect_tininess =3D 0x1, float= _rounding_mode =3D
0x0, float_exception_flags =3D 0x0, floatx80_rounding_precision =3D 0x0, flush_to_zero =3D 0x0, flush_inputs_to_zero =3D 0x0, default_nan_mode =3D 0= x0,
=C2=A0 =C2=A0 =C2=A0 =C2=A0snan_bit_is_one =3D 0x0}, standard_fp_status =3D=
{float_detect_tininess =3D 0x1, float_rounding_mode =3D 0x0,
float_exception_flags =3D 0x0, floatx80_rounding_precision =3D 0x0,
flush_to_zero =3D 0x1, flush_inputs_to_zero =3D 0x1,
=C2=A0 =C2=A0 =C2=A0 =C2=A0default_nan_mode =3D 0x1, snan_bit_is_one =3D 0x= 0}, zcr_el =3D {0x0,
0x0, 0x0, 0x0}}, exclusive_addr =3D 0xffffffffffffffff, exclusive_val =3D <= br> 0x0, exclusive_high =3D 0x0, iwmmxt =3D {regs =3D {0x0 <repeats 16 times= >},
val =3D 0x0, cregs =3D {
=C2=A0 =C2=A0 =C2=A0 =C2=A00x0 <repeats 16 times>}}, cpu_breakpoint = =3D {0x0 <repeats 16
times>}, cpu_watchpoint =3D {0x0 <repeats 16 times>}, end_reset_fi= elds =3D
{<No data fields>}, features =3D 0xfd38fbe6f3, pmsav7 =3D {drbar =3D = 0x0, drsr
=3D 0x0, dracr =3D 0x0,
=C2=A0 =C2=A0 =C2=A0rnr =3D {0x0, 0x0}}, pmsav8 =3D {rbar =3D {0x0, 0x0}, r= lar =3D {0x0, 0x0},
mair0 =3D {0x0, 0x0}, mair1 =3D {0x0, 0x0}}, sau =3D {rbar =3D 0x0, rlar = =3D 0x0,
rnr =3D 0x0, ctrl =3D 0x0}, nvic =3D 0x0, boot_info =3D 0x5622af3a17a0, gicv3state =3D 0x0}

> [1] http://www.orangepi.org/downloadresources/ > [2] https://buildroot.org/download.html
> [3] https://www.armbian.com/orange-pi-pc/



--
Niek Linnenbank

--000000000000209d5b05994c3674-- From MAILER-DAEMON Mon Dec 09 17:25:00 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1ieRSe-0003ic-2V for mharc-qemu-arm@gnu.org; Mon, 09 Dec 2019 17:25:00 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:60096) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ieRSb-0003g4-3W for qemu-arm@nongnu.org; Mon, 09 Dec 2019 17:24:58 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ieRSa-0006Ic-4Z for qemu-arm@nongnu.org; Mon, 09 Dec 2019 17:24:57 -0500 Received: from mail-ot1-x342.google.com ([2607:f8b0:4864:20::342]:34126) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ieRSX-0006Ha-U8; Mon, 09 Dec 2019 17:24:54 -0500 Received: by mail-ot1-x342.google.com with SMTP id a15so13756462otf.1; Mon, 09 Dec 2019 14:24:53 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=mime-version:in-reply-to:references:from:date:message-id:subject:to :cc; bh=ianzxofX1UwQRBrnwc+mhuW0kKW3XYkkz8u7Q0wzBzY=; b=EQs7w4OPWhLV5oTpLg596hXWDUS/z5qT/BqE7P1MhgUfjJ08Y8PWyMBZauXQHnbrUT QcPhiaJOh04PLb2IROYHgtwGosXH2tSTrNaiXosme++7JcjZ8HjGke5RGcnq6siSXX0S hNCLSOaVvruvohR29lGrW6z6ZKLu6Vq3JnfPH6PhVustU+ps2/Md3BX6JInsJ6VGEgX3 hoLe7/Xphcd5sRSXgVEHpzqp8caaWBnGGMFshspMhQ6dKhpm4VQZduYYe6PXQsg+LMi6 ASU0Ch3u7WQ5Du84ST9k7E8omV0leeU0T4qLlC1hdGaOAv4Ttmvpx9cyVuoo0CyY2qXT Q9pQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:in-reply-to:references:from:date :message-id:subject:to:cc; bh=ianzxofX1UwQRBrnwc+mhuW0kKW3XYkkz8u7Q0wzBzY=; b=Nwxt2TAJ5X/3UfdxEPFlLgKTofjk77GWkMFnK0nUPzNk7bCZQDVhO0OFma9PfPMs/m V3nrprBfXrpFUqBY6JB3fp2vwE/+4Zs3jyjXywv8m4afse7X0yuYB6a9ALsXAZ+gfWAi zalsaKgR6IPSjkHTR6jIzZmt6UOvQfPjg5lIzyVXIIcx6088mS8gb2Nai1vY1yzFRtBr VV46IXEvYdnDI7S/1b2SEiLBh6u4DkVN/SnljdxrqLxwoXUFlL9nkWPOtmpX3sxCz3Y8 Ciz9c+yuVitJDT2RzVO8VcszIo3MnS5efFUER0KYmlHeeXZMztnLvfuWNsEj0gKpgVyB sOzA== X-Gm-Message-State: APjAAAWxM5KsuDt7jbTFyZXO4yJOD9TTo1GaLQ+iTG3RaG2xh1vEkHex 5dxPHeE5QEm54tH8LgYYuuceeBF4R2MAuZ9+RaM= X-Google-Smtp-Source: APXvYqx3cQnMjK89Xoq/DG/BCDyPDjlyMD8G0xyKRoZBT5Zc9/ON4JlxERr2rgwzkaJtBrFV9osXwFH8QtW/+k9z6Yc= X-Received: by 2002:a9d:58c9:: with SMTP id s9mr22204180oth.121.1575930293084; Mon, 09 Dec 2019 14:24:53 -0800 (PST) MIME-Version: 1.0 Received: by 2002:a9d:d21:0:0:0:0:0 with HTTP; Mon, 9 Dec 2019 14:24:52 -0800 (PST) In-Reply-To: References: <20191202210947.3603-1-nieklinnenbank@gmail.com> <1de57227-8124-4d11-d996-9faf67b3e4f3@redhat.com> From: Aleksandar Markovic Date: Mon, 9 Dec 2019 23:24:52 +0100 Message-ID: Subject: Re: [PATCH 00/10] Add Allwinner H3 SoC and Orange Pi PC Machine To: Peter Maydell Cc: Niek Linnenbank , Alistair Francis , Richard Henderson , QEMU Developers , =?UTF-8?Q?Niccol=C3=B2_Izzo?= , Beniamino Galvani , KONRAD Frederic , qemu-arm , =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= Content-Type: multipart/alternative; boundary="0000000000004f686805994cdd01" X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::342 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 09 Dec 2019 22:24:58 -0000 --0000000000004f686805994cdd01 Content-Type: text/plain; charset="UTF-8" On Friday, December 6, 2019, Peter Maydell wrote: > On Tue, 3 Dec 2019 at 19:32, Niek Linnenbank > wrote: > > Indeed that sounds like an interesting combination. Are there plans to > build a multi-arch/single-binary QEMU? > > This is in the category of "it would be nice in theory to > support multi-arch guest machines, and we've made some > small steps in that direction and/or tried to keep the > door open for it when designing things, but it would > still be a huge amount of work to actually implement, > so don't hold your breath for it or make anything else > depend on having it happen first"... > > Peter, This is one of the longest definitions of a category (in fact, most likely, the longest) that I have heard in my life. ;)) Aleksandar > thanks > -- PMM > > --0000000000004f686805994cdd01 Content-Type: text/html; charset="UTF-8" Content-Transfer-Encoding: quoted-printable

On Friday, December 6, 2019, Peter Maydell <peter.maydell@linaro.org> wrote:
On Tue, 3 Dec 2019 at 19:32, Niek Linnenbank <nieklinnenbank@gmail.com> w= rote:
> Indeed that sounds like an interesting combination. Are there plans to= build a multi-arch/single-binary QEMU?

This is in the category of "it would be nice in theory to
support multi-arch guest machines, and we've made some
small steps in that direction and/or tried to keep the
door open for it when designing things, but it would
still be a huge amount of work to actually implement,
so don't hold your breath for it or make anything else
depend on having it happen first"...


Peter,

This i= s one of the longest definitions of a category (in fact, most likely, the l= ongest) that I have heard in my life. ;))

Aleksand= ar

=C2=A0
thanks
-- PMM

--0000000000004f686805994cdd01-- From MAILER-DAEMON Mon Dec 09 19:51:32 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1ieTkS-0001W4-8x for mharc-qemu-arm@gnu.org; Mon, 09 Dec 2019 19:51:32 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:59203) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ieTkQ-0001Vj-DE for qemu-arm@nongnu.org; Mon, 09 Dec 2019 19:51:31 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ieTkP-0000M1-60 for qemu-arm@nongnu.org; Mon, 09 Dec 2019 19:51:30 -0500 Received: from out3-smtp.messagingengine.com ([66.111.4.27]:57901) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1ieTkO-0000LK-Nt; Mon, 09 Dec 2019 19:51:29 -0500 Received: from compute4.internal (compute4.nyi.internal [10.202.2.44]) by mailout.nyi.internal (Postfix) with ESMTP id 609A522721; Mon, 9 Dec 2019 19:51:26 -0500 (EST) Received: from mailfrontend2 ([10.202.2.163]) by compute4.internal (MEProxy); Mon, 09 Dec 2019 19:51:26 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=aj.id.au; h=from :to:cc:subject:date:message-id:mime-version :content-transfer-encoding; s=fm1; bh=d1dmNORHMlpfYt+AMVjS4Tn/Y9 CmVlh1D4pT80hKJvA=; b=EGANWB7Okcu9K8aWsEYz4CRdtDGQsxLuLligsRB6ti JFImEmY7kDlEp+Aea0styf6bZIaEQIUIfsfOBTnpcnKgy766YU35QCrtAzGFmh01 d8Yd0wrGpQYPl6/QvidlH51VzQmLxQekMrvuStk3Ar7J9QkzZbQYmvSqLjiGu8kU JaDnSrvWwGuVMq4JLNPylWzL64wm2xLkvicumQPal0rYjMO8pbbYNcNtK8bgBXvo Sp8yqctwnpO0up5Z5dwWk0Roa3mwziCMRQm+6dQD5MKsZDfgn7LUZf4RwSHXqpp5 F3e5sTmDtKAAqHa4qDevny6NDncOtOr1lSu5T/Cgk/9A== DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d= messagingengine.com; h=cc:content-transfer-encoding:date:from :message-id:mime-version:subject:to:x-me-proxy:x-me-proxy :x-me-sender:x-me-sender:x-sasl-enc; s=fm1; bh=d1dmNORHMlpfYt+AM VjS4Tn/Y9CmVlh1D4pT80hKJvA=; b=dUBePxy4jB+2eJ8N6BIpIwWSdW60BtDH5 f8GLISfI0IrWei4Zm7/FDjRCuLV7vVnCHkQnE2dRQ9kj+ppmyEK2M9oyhUsvNhmD hIKL8oi/Kd9RxgcxKOcj8tYl8Io6VPlPqsyjZzTK709I8fwGziQrzEeUZvFcsY/M RNNyAsgJvUS5uHnJka6ta02UT5LCJl0s0qxQSzBY86iqViXIL2ogdlnyqYnpLI49 jb6XquB8VHtD1+VyfD5G2EDLO+PKHNHdx+tvl2ty3RcOg1zTkLn58mB9D2Yxobwx mo9y/QJp/uVkwtsScTlqz77jn2Q2REgEQR54d3Oiy7sxHgjuhkUgw== X-ME-Sender: X-ME-Proxy-Cause: gggruggvucftvghtrhhoucdtuddrgedufedrudelvddgvddvucetufdoteggodetrfdotf fvucfrrhhofhhilhgvmecuhfgrshhtofgrihhlpdfqfgfvpdfurfetoffkrfgpnffqhgen uceurghilhhouhhtmecufedttdenucenucfjughrpefhvffufffkofgggfestdekredtre dttdenucfhrhhomheptehnughrvgifucflvghffhgvrhihuceorghnughrvgifsegrjhdr ihgurdgruheqnecukfhppedvtddvrdekuddrudekrdeftdenucfrrghrrghmpehmrghilh hfrhhomheprghnughrvgifsegrjhdrihgurdgruhenucevlhhushhtvghrufhiiigvpedt X-ME-Proxy: Received: from mistburn.au.ibm.com (bh02i525f01.au.ibm.com [202.81.18.30]) by mail.messagingengine.com (Postfix) with ESMTPA id 145E830600BD; Mon, 9 Dec 2019 19:51:22 -0500 (EST) From: Andrew Jeffery To: qemu-arm@nongnu.org Cc: clg@kaod.org, peter.maydell@linaro.org, joel@jms.id.au, qemu-devel@nongnu.org Subject: [PATCH 0/2] hw/arm: ast2600: Wire up eMMC controller Date: Tue, 10 Dec 2019 11:22:49 +1030 Message-Id: X-Mailer: git-send-email 2.20.1 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 66.111.4.27 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 10 Dec 2019 00:51:31 -0000 Hello, The AST2600 has an additional SDHCI intended for use as an eMMC boot source. These two patches rework the existing ASPEED SDHCI model to accommodate the single-slot nature of the eMMC controller and wire it into the AST2600 SoC. Please review! Andrew Andrew Jeffery (2): hw/sd: Configure number of slots exposed by the ASPEED SDHCI model hw/arm: ast2600: Wire up the eMMC controller hw/arm/aspeed.c | 15 ++++++++++++++- hw/arm/aspeed_ast2600.c | 23 +++++++++++++++++++++++ hw/arm/aspeed_soc.c | 3 +++ hw/sd/aspeed_sdhci.c | 11 +++++++++-- include/hw/arm/aspeed_soc.h | 2 ++ include/hw/sd/aspeed_sdhci.h | 1 + 6 files changed, 52 insertions(+), 3 deletions(-) base-commit: 6a4ef4e5d1084ce41fafa7d470a644b0fd3d9317 -- git-series 0.9.1 From MAILER-DAEMON Mon Dec 09 19:51:33 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1ieTkT-0001Y2-Eq for mharc-qemu-arm@gnu.org; Mon, 09 Dec 2019 19:51:33 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:59211) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ieTkR-0001Vk-0V for qemu-arm@nongnu.org; Mon, 09 Dec 2019 19:51:32 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ieTkP-0000MC-PE for qemu-arm@nongnu.org; Mon, 09 Dec 2019 19:51:30 -0500 Received: from out3-smtp.messagingengine.com ([66.111.4.27]:41529) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1ieTkP-0000Ll-Lf; Mon, 09 Dec 2019 19:51:29 -0500 Received: from compute4.internal (compute4.nyi.internal [10.202.2.44]) by mailout.nyi.internal (Postfix) with ESMTP id 0AB3B2274C; Mon, 9 Dec 2019 19:51:28 -0500 (EST) Received: from mailfrontend2 ([10.202.2.163]) by compute4.internal (MEProxy); Mon, 09 Dec 2019 19:51:28 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=aj.id.au; h=from :to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; s=fm1; bh=rUFlEnpp1Xzck M6kcV2NqxDXgI9i9LAVjGAQGY512Q8=; b=kzpsk9a+FMdyP9JOh+u46xMxCCOWX /WJVA7FRXvTxX4shCMAb208r7cjsPxtelke/dA/6NurHBF6c3BEN3UIBtqKxrBLC x6MybfmPjyVazd3q3UjY2GPPkZoxD7V7+cFrY5jTpmllfP2/J6hqtw0HWUHxdkXo OMkrWBCy137S4mqTwMIbO18jL/Ud1cgh33BXJ6bWAazquZ8asPSPoBgIqw6J7ike 9BeBnIwcDRIPTgEAN9Zfugs0LBdugix4QPfj/+QQQ0Hh1Z6ljwU/StBTOQmCns// VH6hlN1sD+aBVz0GPaZbvSZPUbOaihM/XVZ7aEWjYvJqyWdLq3itIbimw== DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d= messagingengine.com; h=cc:content-transfer-encoding:date:from :in-reply-to:message-id:mime-version:references:subject:to :x-me-proxy:x-me-proxy:x-me-sender:x-me-sender:x-sasl-enc; s= fm1; bh=rUFlEnpp1XzckM6kcV2NqxDXgI9i9LAVjGAQGY512Q8=; b=kuB49+zX TByF//kQfk8ML5iLwfoo2LgALJGu0CGBDN5gGRxO1l9z/JRHo6EdImNLORc/CYhy HKiWxi3IIT5P1XR7vTaiI2G/VUpwkyf5wLxgyfH5w2khXYU2hbcVybsC8fmHMrCS pksc3WhGOXBwybnBPxRWGzu7bXYj7g3i7V5D1eMbzee1PIBKw/Jk6+V6jLhCnqDk sa5GX7TlOIuo4SJeLBQL9tBofrAQulV50gHwFuTZ4mqTQHt544YqRYAbYHqI1MhP GxRQaoMI9gYiSQBhEnbxwfhnSGJQZ9of8WenFUQsLBy03trzYnvEl7JGi/PrvbeG 0WxkQ2aA865CQw== X-ME-Sender: X-ME-Proxy-Cause: gggruggvucftvghtrhhoucdtuddrgedufedrudelvddgvddvucetufdoteggodetrfdotf fvucfrrhhofhhilhgvmecuhfgrshhtofgrihhlpdfqfgfvpdfurfetoffkrfgpnffqhgen uceurghilhhouhhtmecufedttdenucenucfjughrpefhvffufffkofgjfhgggfestdekre dtredttdenucfhrhhomheptehnughrvgifucflvghffhgvrhihuceorghnughrvgifsegr jhdrihgurdgruheqnecukfhppedvtddvrdekuddrudekrdeftdenucfrrghrrghmpehmrg hilhhfrhhomheprghnughrvgifsegrjhdrihgurdgruhenucevlhhushhtvghrufhiiigv pedt X-ME-Proxy: Received: from mistburn.au.ibm.com (bh02i525f01.au.ibm.com [202.81.18.30]) by mail.messagingengine.com (Postfix) with ESMTPA id BE98B30600D4; Mon, 9 Dec 2019 19:51:25 -0500 (EST) From: Andrew Jeffery To: qemu-arm@nongnu.org Cc: clg@kaod.org, peter.maydell@linaro.org, joel@jms.id.au, qemu-devel@nongnu.org Subject: [PATCH 1/2] hw/sd: Configure number of slots exposed by the ASPEED SDHCI model Date: Tue, 10 Dec 2019 11:22:50 +1030 Message-Id: <11e1d38d2374a48996a3496c906db215de246583.1575938234.git-series.andrew@aj.id.au> X-Mailer: git-send-email 2.20.1 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 66.111.4.27 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 10 Dec 2019 00:51:32 -0000 The AST2600 includes a second cut-down version of the SD/MMC controller found in the AST2500, named the eMMC controller. It's cut down in the sense that it only supports one slot rather than two, but it brings the total number of slots supported by the AST2600 to three. The existing code assumed that the SD controller always provided two slots. Rework the SDHCI object to expose the number of slots as a property to be set by the SoC configuration. Signed-off-by: Andrew Jeffery --- hw/arm/aspeed.c | 2 +- hw/arm/aspeed_ast2600.c | 2 ++ hw/arm/aspeed_soc.c | 3 +++ hw/sd/aspeed_sdhci.c | 11 +++++++++-- include/hw/sd/aspeed_sdhci.h | 1 + 5 files changed, 16 insertions(+), 3 deletions(-) diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c index 028191ff36fc..862549b1f3a9 100644 --- a/hw/arm/aspeed.c +++ b/hw/arm/aspeed.c @@ -259,7 +259,7 @@ static void aspeed_board_init(MachineState *machine, cfg->i2c_init(bmc); } - for (i = 0; i < ARRAY_SIZE(bmc->soc.sdhci.slots); i++) { + for (i = 0; i < bmc->soc.sdhci.num_slots; i++) { SDHCIState *sdhci = &bmc->soc.sdhci.slots[i]; DriveInfo *dinfo = drive_get_next(IF_SD); BlockBackend *blk; diff --git a/hw/arm/aspeed_ast2600.c b/hw/arm/aspeed_ast2600.c index 931887ac681f..931ee5aae183 100644 --- a/hw/arm/aspeed_ast2600.c +++ b/hw/arm/aspeed_ast2600.c @@ -208,6 +208,8 @@ static void aspeed_soc_ast2600_init(Object *obj) sysbus_init_child_obj(obj, "sdc", OBJECT(&s->sdhci), sizeof(s->sdhci), TYPE_ASPEED_SDHCI); + object_property_set_int(OBJECT(&s->sdhci), 2, "num-slots", &error_abort); + /* Init sd card slot class here so that they're under the correct parent */ for (i = 0; i < ASPEED_SDHCI_NUM_SLOTS; ++i) { sysbus_init_child_obj(obj, "sdhci[*]", OBJECT(&s->sdhci.slots[i]), diff --git a/hw/arm/aspeed_soc.c b/hw/arm/aspeed_soc.c index f4fe243458fd..3498f55603f2 100644 --- a/hw/arm/aspeed_soc.c +++ b/hw/arm/aspeed_soc.c @@ -215,6 +215,9 @@ static void aspeed_soc_init(Object *obj) sysbus_init_child_obj(obj, "sdc", OBJECT(&s->sdhci), sizeof(s->sdhci), TYPE_ASPEED_SDHCI); + object_property_set_int(OBJECT(&s->sdhci), ASPEED_SDHCI_NUM_SLOTS, + "num-slots", &error_abort); + /* Init sd card slot class here so that they're under the correct parent */ for (i = 0; i < ASPEED_SDHCI_NUM_SLOTS; ++i) { sysbus_init_child_obj(obj, "sdhci[*]", OBJECT(&s->sdhci.slots[i]), diff --git a/hw/sd/aspeed_sdhci.c b/hw/sd/aspeed_sdhci.c index cff3eb7dd21e..939d1510dedb 100644 --- a/hw/sd/aspeed_sdhci.c +++ b/hw/sd/aspeed_sdhci.c @@ -13,6 +13,7 @@ #include "qapi/error.h" #include "hw/irq.h" #include "migration/vmstate.h" +#include "hw/qdev-properties.h" #define ASPEED_SDHCI_INFO 0x00 #define ASPEED_SDHCI_INFO_RESET 0x00030000 @@ -120,14 +121,14 @@ static void aspeed_sdhci_realize(DeviceState *dev, Error **errp) /* Create input irqs for the slots */ qdev_init_gpio_in_named_with_opaque(DEVICE(sbd), aspeed_sdhci_set_irq, - sdhci, NULL, ASPEED_SDHCI_NUM_SLOTS); + sdhci, NULL, sdhci->num_slots); sysbus_init_irq(sbd, &sdhci->irq); memory_region_init_io(&sdhci->iomem, OBJECT(sdhci), &aspeed_sdhci_ops, sdhci, TYPE_ASPEED_SDHCI, 0x1000); sysbus_init_mmio(sbd, &sdhci->iomem); - for (int i = 0; i < ASPEED_SDHCI_NUM_SLOTS; ++i) { + for (int i = 0; i < sdhci->num_slots; ++i) { Object *sdhci_slot = OBJECT(&sdhci->slots[i]); SysBusDevice *sbd_slot = SYS_BUS_DEVICE(&sdhci->slots[i]); @@ -174,6 +175,11 @@ static const VMStateDescription vmstate_aspeed_sdhci = { }, }; +static Property aspeed_sdhci_properties[] = { + DEFINE_PROP_UINT8("num-slots", AspeedSDHCIState, num_slots, 0), + DEFINE_PROP_END_OF_LIST(), +}; + static void aspeed_sdhci_class_init(ObjectClass *classp, void *data) { DeviceClass *dc = DEVICE_CLASS(classp); @@ -181,6 +187,7 @@ static void aspeed_sdhci_class_init(ObjectClass *classp, void *data) dc->realize = aspeed_sdhci_realize; dc->reset = aspeed_sdhci_reset; dc->vmsd = &vmstate_aspeed_sdhci; + dc->props = aspeed_sdhci_properties; } static TypeInfo aspeed_sdhci_info = { diff --git a/include/hw/sd/aspeed_sdhci.h b/include/hw/sd/aspeed_sdhci.h index dfdab4379021..dffbb46946b9 100644 --- a/include/hw/sd/aspeed_sdhci.h +++ b/include/hw/sd/aspeed_sdhci.h @@ -24,6 +24,7 @@ typedef struct AspeedSDHCIState { SysBusDevice parent; SDHCIState slots[ASPEED_SDHCI_NUM_SLOTS]; + uint8_t num_slots; MemoryRegion iomem; qemu_irq irq; -- git-series 0.9.1 From MAILER-DAEMON Mon Dec 09 19:51:36 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1ieTkV-0001cC-SG for mharc-qemu-arm@gnu.org; Mon, 09 Dec 2019 19:51:35 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:59232) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ieTkS-0001WO-CN for qemu-arm@nongnu.org; Mon, 09 Dec 2019 19:51:33 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ieTkR-0000Mh-4p for qemu-arm@nongnu.org; Mon, 09 Dec 2019 19:51:32 -0500 Received: from out3-smtp.messagingengine.com ([66.111.4.27]:54371) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1ieTkR-0000MU-1G; Mon, 09 Dec 2019 19:51:31 -0500 Received: from compute4.internal (compute4.nyi.internal [10.202.2.44]) by mailout.nyi.internal (Postfix) with ESMTP id AF6FA22721; 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Signed-off-by: Andrew Jeffery --- hw/arm/aspeed.c | 13 +++++++++++++ hw/arm/aspeed_ast2600.c | 21 +++++++++++++++++++++ include/hw/arm/aspeed_soc.h | 2 ++ 3 files changed, 36 insertions(+) diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c index 862549b1f3a9..0e08d62e9ff3 100644 --- a/hw/arm/aspeed.c +++ b/hw/arm/aspeed.c @@ -272,6 +272,19 @@ static void aspeed_board_init(MachineState *machine, object_property_set_bool(OBJECT(card), true, "realized", &error_fatal); } + if (bmc->soc.emmc.num_slots) { + SDHCIState *emmc = &bmc->soc.emmc.slots[0]; + DriveInfo *dinfo = drive_get_next(IF_SD); + BlockBackend *blk; + DeviceState *card; + + blk = dinfo ? blk_by_legacy_dinfo(dinfo) : NULL; + card = qdev_create(qdev_get_child_bus(DEVICE(emmc), "sd-bus"), + TYPE_SD_CARD); + qdev_prop_set_drive(card, "drive", blk, &error_fatal); + object_property_set_bool(OBJECT(card), true, "realized", &error_fatal); + } + arm_load_kernel(ARM_CPU(first_cpu), machine, &aspeed_board_binfo); } diff --git a/hw/arm/aspeed_ast2600.c b/hw/arm/aspeed_ast2600.c index 931ee5aae183..723c8196c8a5 100644 --- a/hw/arm/aspeed_ast2600.c +++ b/hw/arm/aspeed_ast2600.c @@ -46,6 +46,7 @@ static const hwaddr aspeed_soc_ast2600_memmap[] = { [ASPEED_ADC] = 0x1E6E9000, [ASPEED_VIDEO] = 0x1E700000, [ASPEED_SDHCI] = 0x1E740000, + [ASPEED_EMMC] = 0x1E750000, [ASPEED_GPIO] = 0x1E780000, [ASPEED_GPIO_1_8V] = 0x1E780800, [ASPEED_RTC] = 0x1E781000, @@ -64,6 +65,7 @@ static const hwaddr aspeed_soc_ast2600_memmap[] = { #define ASPEED_SOC_AST2600_MAX_IRQ 128 +/* Shared Peripheral Interrupt values below are offset by -32 from datasheet */ static const int aspeed_soc_ast2600_irqmap[] = { [ASPEED_UART1] = 47, [ASPEED_UART2] = 48, @@ -77,6 +79,7 @@ static const int aspeed_soc_ast2600_irqmap[] = { [ASPEED_ADC] = 78, [ASPEED_XDMA] = 6, [ASPEED_SDHCI] = 43, + [ASPEED_EMMC] = 15, [ASPEED_GPIO] = 40, [ASPEED_GPIO_1_8V] = 11, [ASPEED_RTC] = 13, @@ -215,6 +218,14 @@ static void aspeed_soc_ast2600_init(Object *obj) sysbus_init_child_obj(obj, "sdhci[*]", OBJECT(&s->sdhci.slots[i]), sizeof(s->sdhci.slots[i]), TYPE_SYSBUS_SDHCI); } + + sysbus_init_child_obj(obj, "emmc", OBJECT(&s->emmc), sizeof(s->emmc), + TYPE_ASPEED_SDHCI); + + object_property_set_int(OBJECT(&s->emmc), 1, "num-slots", &error_abort); + + sysbus_init_child_obj(obj, "emmc[*]", OBJECT(&s->emmc.slots[0]), + sizeof(s->emmc.slots[0]), TYPE_SYSBUS_SDHCI); } /* @@ -487,6 +498,16 @@ static void aspeed_soc_ast2600_realize(DeviceState *dev, Error **errp) sc->memmap[ASPEED_SDHCI]); sysbus_connect_irq(SYS_BUS_DEVICE(&s->sdhci), 0, aspeed_soc_get_irq(s, ASPEED_SDHCI)); + + /* eMMC */ + object_property_set_bool(OBJECT(&s->emmc), true, "realized", &err); + if (err) { + error_propagate(errp, err); + return; + } + sysbus_mmio_map(SYS_BUS_DEVICE(&s->emmc), 0, sc->memmap[ASPEED_EMMC]); + sysbus_connect_irq(SYS_BUS_DEVICE(&s->emmc), 0, + aspeed_soc_get_irq(s, ASPEED_EMMC)); } static void aspeed_soc_ast2600_class_init(ObjectClass *oc, void *data) diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h index 495c08be1b84..911443f4c071 100644 --- a/include/hw/arm/aspeed_soc.h +++ b/include/hw/arm/aspeed_soc.h @@ -56,6 +56,7 @@ typedef struct AspeedSoCState { AspeedGPIOState gpio; AspeedGPIOState gpio_1_8v; AspeedSDHCIState sdhci; + AspeedSDHCIState emmc; } AspeedSoCState; #define TYPE_ASPEED_SOC "aspeed-soc" @@ -125,6 +126,7 @@ enum { ASPEED_MII4, ASPEED_SDRAM, ASPEED_XDMA, + ASPEED_EMMC, }; #endif /* ASPEED_SOC_H */ -- git-series 0.9.1 From MAILER-DAEMON Tue Dec 10 02:49:20 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1ieaGm-00029u-3i for mharc-qemu-arm@gnu.org; Tue, 10 Dec 2019 02:49:20 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:50905) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ieaGi-00027a-PL for qemu-arm@nongnu.org; Tue, 10 Dec 2019 02:49:18 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ieaGh-0005GD-H8 for qemu-arm@nongnu.org; Tue, 10 Dec 2019 02:49:16 -0500 Received: from us-smtp-2.mimecast.com ([207.211.31.81]:26580 helo=us-smtp-delivery-1.mimecast.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1ieaGh-0005Fu-EC for qemu-arm@nongnu.org; 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[88.21.103.182]) by smtp.gmail.com with ESMTPSA id w13sm2364554wru.38.2019.12.09.23.49.09 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 09 Dec 2019 23:49:09 -0800 (PST) Subject: Re: [PATCH 1/2] hw/sd: Configure number of slots exposed by the ASPEED SDHCI model To: Andrew Jeffery , qemu-arm@nongnu.org Cc: qemu-devel@nongnu.org, peter.maydell@linaro.org, clg@kaod.org, joel@jms.id.au References: <11e1d38d2374a48996a3496c906db215de246583.1575938234.git-series.andrew@aj.id.au> From: =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= Message-ID: Date: Tue, 10 Dec 2019 08:49:08 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.2.2 MIME-Version: 1.0 In-Reply-To: <11e1d38d2374a48996a3496c906db215de246583.1575938234.git-series.andrew@aj.id.au> Content-Language: en-US X-MC-Unique: tXJyuiIYNnSFtCoSftyE3g-1 X-Mimecast-Spam-Score: 0 Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 207.211.31.81 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 10 Dec 2019 07:49:18 -0000 On 12/10/19 1:52 AM, Andrew Jeffery wrote: > The AST2600 includes a second cut-down version of the SD/MMC controller > found in the AST2500, named the eMMC controller. It's cut down in the > sense that it only supports one slot rather than two, but it brings the > total number of slots supported by the AST2600 to three. >=20 > The existing code assumed that the SD controller always provided two > slots. Rework the SDHCI object to expose the number of slots as a > property to be set by the SoC configuration. >=20 > Signed-off-by: Andrew Jeffery Reviewed-by: Philippe Mathieu-Daud=C3=A9 > --- > hw/arm/aspeed.c | 2 +- > hw/arm/aspeed_ast2600.c | 2 ++ > hw/arm/aspeed_soc.c | 3 +++ > hw/sd/aspeed_sdhci.c | 11 +++++++++-- > include/hw/sd/aspeed_sdhci.h | 1 + > 5 files changed, 16 insertions(+), 3 deletions(-) >=20 > diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c > index 028191ff36fc..862549b1f3a9 100644 > --- a/hw/arm/aspeed.c > +++ b/hw/arm/aspeed.c > @@ -259,7 +259,7 @@ static void aspeed_board_init(MachineState *machine, > cfg->i2c_init(bmc); > } > =20 > - for (i =3D 0; i < ARRAY_SIZE(bmc->soc.sdhci.slots); i++) { > + for (i =3D 0; i < bmc->soc.sdhci.num_slots; i++) { > SDHCIState *sdhci =3D &bmc->soc.sdhci.slots[i]; > DriveInfo *dinfo =3D drive_get_next(IF_SD); > BlockBackend *blk; > diff --git a/hw/arm/aspeed_ast2600.c b/hw/arm/aspeed_ast2600.c > index 931887ac681f..931ee5aae183 100644 > --- a/hw/arm/aspeed_ast2600.c > +++ b/hw/arm/aspeed_ast2600.c > @@ -208,6 +208,8 @@ static void aspeed_soc_ast2600_init(Object *obj) > sysbus_init_child_obj(obj, "sdc", OBJECT(&s->sdhci), sizeof(s->sdhc= i), > TYPE_ASPEED_SDHCI); > =20 > + object_property_set_int(OBJECT(&s->sdhci), 2, "num-slots", &error_ab= ort); > + > /* Init sd card slot class here so that they're under the correct p= arent */ > for (i =3D 0; i < ASPEED_SDHCI_NUM_SLOTS; ++i) { > sysbus_init_child_obj(obj, "sdhci[*]", OBJECT(&s->sdhci.slots[i= ]), > diff --git a/hw/arm/aspeed_soc.c b/hw/arm/aspeed_soc.c > index f4fe243458fd..3498f55603f2 100644 > --- a/hw/arm/aspeed_soc.c > +++ b/hw/arm/aspeed_soc.c > @@ -215,6 +215,9 @@ static void aspeed_soc_init(Object *obj) > sysbus_init_child_obj(obj, "sdc", OBJECT(&s->sdhci), sizeof(s->sdhc= i), > TYPE_ASPEED_SDHCI); > =20 > + object_property_set_int(OBJECT(&s->sdhci), ASPEED_SDHCI_NUM_SLOTS, > + "num-slots", &error_abort); > + > /* Init sd card slot class here so that they're under the correct p= arent */ > for (i =3D 0; i < ASPEED_SDHCI_NUM_SLOTS; ++i) { > sysbus_init_child_obj(obj, "sdhci[*]", OBJECT(&s->sdhci.slots[i= ]), > diff --git a/hw/sd/aspeed_sdhci.c b/hw/sd/aspeed_sdhci.c > index cff3eb7dd21e..939d1510dedb 100644 > --- a/hw/sd/aspeed_sdhci.c > +++ b/hw/sd/aspeed_sdhci.c > @@ -13,6 +13,7 @@ > #include "qapi/error.h" > #include "hw/irq.h" > #include "migration/vmstate.h" > +#include "hw/qdev-properties.h" > =20 > #define ASPEED_SDHCI_INFO 0x00 > #define ASPEED_SDHCI_INFO_RESET 0x00030000 > @@ -120,14 +121,14 @@ static void aspeed_sdhci_realize(DeviceState *dev, = Error **errp) > =20 > /* Create input irqs for the slots */ > qdev_init_gpio_in_named_with_opaque(DEVICE(sbd), aspeed_sdhci_set_i= rq, > - sdhci, NULL, ASPEED_SDHCI_NUM_SL= OTS); > + sdhci, NULL, sdhci->num_slots); > =20 > sysbus_init_irq(sbd, &sdhci->irq); > memory_region_init_io(&sdhci->iomem, OBJECT(sdhci), &aspeed_sdhci_o= ps, > sdhci, TYPE_ASPEED_SDHCI, 0x1000); > sysbus_init_mmio(sbd, &sdhci->iomem); > =20 > - for (int i =3D 0; i < ASPEED_SDHCI_NUM_SLOTS; ++i) { > + for (int i =3D 0; i < sdhci->num_slots; ++i) { > Object *sdhci_slot =3D OBJECT(&sdhci->slots[i]); > SysBusDevice *sbd_slot =3D SYS_BUS_DEVICE(&sdhci->slots[i]); > =20 > @@ -174,6 +175,11 @@ static const VMStateDescription vmstate_aspeed_sdhci= =3D { > }, > }; > =20 > +static Property aspeed_sdhci_properties[] =3D { > + DEFINE_PROP_UINT8("num-slots", AspeedSDHCIState, num_slots, 0), > + DEFINE_PROP_END_OF_LIST(), > +}; > + > static void aspeed_sdhci_class_init(ObjectClass *classp, void *data) > { > DeviceClass *dc =3D DEVICE_CLASS(classp); > @@ -181,6 +187,7 @@ static void aspeed_sdhci_class_init(ObjectClass *clas= sp, void *data) > dc->realize =3D aspeed_sdhci_realize; > dc->reset =3D aspeed_sdhci_reset; > dc->vmsd =3D &vmstate_aspeed_sdhci; > + dc->props =3D aspeed_sdhci_properties; > } > =20 > static TypeInfo aspeed_sdhci_info =3D { > diff --git a/include/hw/sd/aspeed_sdhci.h b/include/hw/sd/aspeed_sdhci.h > index dfdab4379021..dffbb46946b9 100644 > --- a/include/hw/sd/aspeed_sdhci.h > +++ b/include/hw/sd/aspeed_sdhci.h > @@ -24,6 +24,7 @@ typedef struct AspeedSDHCIState { > SysBusDevice parent; > =20 > SDHCIState slots[ASPEED_SDHCI_NUM_SLOTS]; > + uint8_t num_slots; > =20 > MemoryRegion iomem; > qemu_irq irq; >=20 From MAILER-DAEMON Tue Dec 10 02:56:11 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1ieaNP-0004wZ-Lw for mharc-qemu-arm@gnu.org; Tue, 10 Dec 2019 02:56:11 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:51495) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ieaNM-0004vy-Iy for qemu-arm@nongnu.org; Tue, 10 Dec 2019 02:56:09 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ieaNL-0008GF-9n for qemu-arm@nongnu.org; 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[88.21.103.182]) by smtp.gmail.com with ESMTPSA id g69sm2283097wmg.13.2019.12.09.23.56.02 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 09 Dec 2019 23:56:03 -0800 (PST) Subject: Re: [PATCH 04/10] arm: allwinner-h3: add USB host controller To: Niek Linnenbank , qemu-devel@nongnu.org, Gerd Hoffmann Cc: b.galvani@gmail.com, peter.maydell@linaro.org, qemu-arm@nongnu.org References: <20191202210947.3603-1-nieklinnenbank@gmail.com> <20191202210947.3603-5-nieklinnenbank@gmail.com> From: =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= Message-ID: <4a900e8d-d803-5c58-5a4b-879cce5970b4@redhat.com> Date: Tue, 10 Dec 2019 08:56:02 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.2.2 MIME-Version: 1.0 In-Reply-To: <20191202210947.3603-5-nieklinnenbank@gmail.com> Content-Language: en-US X-MC-Unique: r_KqU9QCOUWzvEbfc7w_VA-1 X-Mimecast-Spam-Score: 0 Content-Type: text/plain; charset=WINDOWS-1252; format=flowed Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 205.139.110.61 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 10 Dec 2019 07:56:09 -0000 On 12/2/19 10:09 PM, Niek Linnenbank wrote: > The Allwinner H3 System on Chip contains multiple USB 2.0 bus > connections which provide software access using the Enhanced > Host Controller Interface (EHCI) and Open Host Controller > Interface (OHCI) interfaces. This commit adds support for > both interfaces in the Allwinner H3 System on Chip. >=20 > Signed-off-by: Niek Linnenbank > --- > hw/arm/allwinner-h3.c | 20 ++++++++++++++++++++ > hw/usb/hcd-ehci-sysbus.c | 17 +++++++++++++++++ > hw/usb/hcd-ehci.h | 1 + Cc'ing Gerd, the maintainer of these files. Reviewed-by: Philippe Mathieu-Daud=E9 > 3 files changed, 38 insertions(+) >=20 > diff --git a/hw/arm/allwinner-h3.c b/hw/arm/allwinner-h3.c > index 5566e979ec..afeb49c0ac 100644 > --- a/hw/arm/allwinner-h3.c > +++ b/hw/arm/allwinner-h3.c > @@ -26,6 +26,7 @@ > #include "hw/sysbus.h" > #include "hw/arm/allwinner-h3.h" > #include "hw/misc/unimp.h" > +#include "hw/usb/hcd-ehci.h" > #include "sysemu/sysemu.h" > =20 > static void aw_h3_init(Object *obj) > @@ -183,6 +184,25 @@ static void aw_h3_realize(DeviceState *dev, Error **= errp) > } > sysbus_mmio_map(SYS_BUS_DEVICE(&s->ccu), 0, AW_H3_CCU_BASE); > =20 > + /* Universal Serial Bus */ > + sysbus_create_simple(TYPE_AW_H3_EHCI, AW_H3_EHCI0_BASE, > + s->irq[AW_H3_GIC_SPI_EHCI0]); > + sysbus_create_simple(TYPE_AW_H3_EHCI, AW_H3_EHCI1_BASE, > + s->irq[AW_H3_GIC_SPI_EHCI1]); > + sysbus_create_simple(TYPE_AW_H3_EHCI, AW_H3_EHCI2_BASE, > + s->irq[AW_H3_GIC_SPI_EHCI2]); > + sysbus_create_simple(TYPE_AW_H3_EHCI, AW_H3_EHCI3_BASE, > + s->irq[AW_H3_GIC_SPI_EHCI3]); > + > + sysbus_create_simple("sysbus-ohci", AW_H3_OHCI0_BASE, > + s->irq[AW_H3_GIC_SPI_OHCI0]); > + sysbus_create_simple("sysbus-ohci", AW_H3_OHCI1_BASE, > + s->irq[AW_H3_GIC_SPI_OHCI1]); > + sysbus_create_simple("sysbus-ohci", AW_H3_OHCI2_BASE, > + s->irq[AW_H3_GIC_SPI_OHCI2]); > + sysbus_create_simple("sysbus-ohci", AW_H3_OHCI3_BASE, > + s->irq[AW_H3_GIC_SPI_OHCI3]); > + > /* UART */ > if (serial_hd(0)) { > serial_mm_init(get_system_memory(), AW_H3_UART0_REG_BASE, 2, > diff --git a/hw/usb/hcd-ehci-sysbus.c b/hw/usb/hcd-ehci-sysbus.c > index 020211fd10..174c3446ef 100644 > --- a/hw/usb/hcd-ehci-sysbus.c > +++ b/hw/usb/hcd-ehci-sysbus.c > @@ -145,6 +145,22 @@ static const TypeInfo ehci_exynos4210_type_info =3D = { > .class_init =3D ehci_exynos4210_class_init, > }; > =20 > +static void ehci_aw_h3_class_init(ObjectClass *oc, void *data) > +{ > + SysBusEHCIClass *sec =3D SYS_BUS_EHCI_CLASS(oc); > + DeviceClass *dc =3D DEVICE_CLASS(oc); > + > + sec->capsbase =3D 0x0; > + sec->opregbase =3D 0x10; > + set_bit(DEVICE_CATEGORY_USB, dc->categories); > +} > + > +static const TypeInfo ehci_aw_h3_type_info =3D { > + .name =3D TYPE_AW_H3_EHCI, > + .parent =3D TYPE_SYS_BUS_EHCI, > + .class_init =3D ehci_aw_h3_class_init, > +}; > + > static void ehci_tegra2_class_init(ObjectClass *oc, void *data) > { > SysBusEHCIClass *sec =3D SYS_BUS_EHCI_CLASS(oc); > @@ -267,6 +283,7 @@ static void ehci_sysbus_register_types(void) > type_register_static(&ehci_platform_type_info); > type_register_static(&ehci_xlnx_type_info); > type_register_static(&ehci_exynos4210_type_info); > + type_register_static(&ehci_aw_h3_type_info); > type_register_static(&ehci_tegra2_type_info); > type_register_static(&ehci_ppc4xx_type_info); > type_register_static(&ehci_fusbh200_type_info); > diff --git a/hw/usb/hcd-ehci.h b/hw/usb/hcd-ehci.h > index 0298238f0b..edb59311c4 100644 > --- a/hw/usb/hcd-ehci.h > +++ b/hw/usb/hcd-ehci.h > @@ -342,6 +342,7 @@ typedef struct EHCIPCIState { > #define TYPE_SYS_BUS_EHCI "sysbus-ehci-usb" > #define TYPE_PLATFORM_EHCI "platform-ehci-usb" > #define TYPE_EXYNOS4210_EHCI "exynos4210-ehci-usb" > +#define TYPE_AW_H3_EHCI "aw-h3-ehci-usb" > #define TYPE_TEGRA2_EHCI "tegra2-ehci-usb" > #define TYPE_PPC4xx_EHCI "ppc4xx-ehci-usb" > #define TYPE_FUSBH200_EHCI "fusbh200-ehci-usb" >=20 From MAILER-DAEMON Tue Dec 10 03:08:53 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1ieaZh-0007jX-HT for mharc-qemu-arm@gnu.org; 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[88.21.103.182]) by smtp.gmail.com with ESMTPSA id w188sm2343378wmg.32.2019.12.10.00.26.26 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 10 Dec 2019 00:26:27 -0800 (PST) Subject: Re: [PATCH 00/10] Add Allwinner H3 SoC and Orange Pi PC Machine To: Niek Linnenbank Cc: QEMU Developers , Beniamino Galvani , Peter Maydell , qemu-arm , Richard Henderson References: <20191202210947.3603-1-nieklinnenbank@gmail.com> From: =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= Message-ID: <74df65db-1f84-62ba-6d01-edf765fd1dc2@redhat.com> Date: Tue, 10 Dec 2019 09:26:26 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.2.2 MIME-Version: 1.0 In-Reply-To: Content-Language: en-US X-MC-Unique: 5oKwWILCMUq1lG4TCTEZpA-1 X-Mimecast-Spam-Score: 0 Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 207.211.31.81 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 10 Dec 2019 08:26:37 -0000 On 12/9/19 10:37 PM, Niek Linnenbank wrote: > Hi Philippe, >=20 > On Tue, Dec 3, 2019 at 9:47 AM Philippe Mathieu-Daud=C3=A9 > wrote: >=20 > On 12/2/19 10:09 PM, Niek Linnenbank wrote: > > Dear QEMU developers, > > > > Hereby I would like to contribute the following set of patches to > QEMU > > which add support for the Allwinner H3 System on Chip and the > > Orange Pi PC machine. The following features and devices are > supported: > > > >=C2=A0 =C2=A0* SMP (Quad Core Cortex A7) > >=C2=A0 =C2=A0* Generic Interrupt Controller configuration > >=C2=A0 =C2=A0* SRAM mappings > >=C2=A0 =C2=A0* Timer device (re-used from Allwinner A10) > >=C2=A0 =C2=A0* UART > >=C2=A0 =C2=A0* SD/MMC storage controller > >=C2=A0 =C2=A0* EMAC ethernet connectivity > >=C2=A0 =C2=A0* USB 2.0 interfaces > >=C2=A0 =C2=A0* Clock Control Unit > >=C2=A0 =C2=A0* System Control module > >=C2=A0 =C2=A0* Security Identifier device >=20 > Awesome! >=20 > > Functionality related to graphical output such as HDMI, GPU, > > Display Engine and audio are not included. Recently released > > mainline Linux kernels (4.19 up to latest master) and mainline U-B= oot > > are known to work. The SD/MMC code is tested using bonnie++ and > > various tools such as fsck, dd and fdisk. The EMAC is verified > with iperf3 > > using -netdev socket. > > > > To build a Linux mainline kernel that can be booted by the Orange > Pi PC > > machine, simply configure the kernel using the sunxi_defconfig > configuration: > >=C2=A0 =C2=A0$ ARCH=3Darm CROSS_COMPILE=3Darm-linux-gnueabi- make m= rproper > >=C2=A0 =C2=A0$ ARCH=3Darm CROSS_COMPILE=3Darm-linux-gnueabi- make s= unxi_defconfig > > > > To be able to use USB storage, you need to manually enable the > corresponding > > configuration item. Start the kconfig configuration tool: > >=C2=A0 =C2=A0$ ARCH=3Darm CROSS_COMPILE=3Darm-linux-gnueabi- make m= enuconfig > > > > Navigate to the following item, enable it and save your > configuration: > >=C2=A0 =C2=A0Device Drivers > USB support > USB Mass Storage suppor= t > > > > Build the Linux kernel with: > >=C2=A0 =C2=A0$ ARCH=3Darm CROSS_COMPILE=3Darm-linux-gnueabi- make -= j5 > > > > To boot the newly build linux kernel in QEMU with the Orange Pi > PC machine, use: > >=C2=A0 =C2=A0$ qemu-system-arm -M orangepi -m 512 -nic user -nograp= hic \ > >=C2=A0 =C2=A0 =C2=A0 =C2=A0-kernel /path/to/linux/arch/arm/boot/zIm= age \ > >=C2=A0 =C2=A0 =C2=A0 =C2=A0-append 'console=3DttyS0,115200' \ > >=C2=A0 =C2=A0 =C2=A0 =C2=A0-dtb /path/to/linux/arch/arm/boot/dts/su= n8i-h3-orangepi-pc.dtb > > > > Note that this kernel does not have a root filesystem. You may > provide it > > with an official Orange Pi PC image [1] either as an SD card or as > > USB mass storage. To boot using the Orange Pi PC Debian image on > SD card, > > simply add the -sd argument and provide the proper root=3D kernel > parameter: > >=C2=A0 =C2=A0$ qemu-system-arm -M orangepi -m 512 -nic user -nograp= hic \ > >=C2=A0 =C2=A0 =C2=A0 =C2=A0-kernel /path/to/linux/arch/arm/boot/zIm= age \ > >=C2=A0 =C2=A0 =C2=A0 =C2=A0-append 'console=3DttyS0,115200 root=3D/= dev/mmcblk0p2' \ > >=C2=A0 =C2=A0 =C2=A0 =C2=A0-dtb > /path/to/linux/arch/arm/boot/dts/sun8i-h3-orangepi-pc.dtb \ > >=C2=A0 =C2=A0 =C2=A0 =C2=A0-sd OrangePi_pc_debian_stretch_server_li= nux5.3.5_v1.0.img > > > > Alternatively, you can also choose to build and boot a recent > buildroot [2] > > using the orangepi_pc_defconfig or Armbian image [3] for Orange > Pi PC. >=20 > Richard, trying the Armbian image from > https://apt.armbian.com/pool/main/l/linux-4.20.7-sunxi/ I get: >=20 > $ arm-softmmu/qemu-system-arm -M orangepi -m 512 -nic user \ > =C2=A0 =C2=A0-append 'console=3DttyS0,115200' \ > =C2=A0 =C2=A0-kernel boot/vmlinuz-4.20.7-sunxi \ > =C2=A0 =C2=A0-dtb usr/lib/linux-image-dev-sunxi/sun8i-h3-orangepi-pc= .dtb \ > =C2=A0 =C2=A0-serial stdio -d unimp > Uncompressing Linux... done, booting the kernel. > rtc: unimplemented device write (size 4, value 0x16aa0001, offset 0x0= ) > rtc: unimplemented device read (size 4, offset 0x0) > rtc: unimplemented device read (size 4, offset 0x0) > rtc: unimplemented device read (size 4, offset 0x8) > qemu-system-arm: target/arm/helper.c:11359: cpu_get_tb_cpu_state: > Assertion `flags =3D=3D rebuild_hflags_internal(env)' failed. > Aborted (core dumped) >=20 >=20 > I'm trying to reproduce the error you reported here with my patch set on= =20 > latest master, > but so far without any result. The host OS I'm using is Ubuntu 18.04.3=20 > LTS on x86_64. > I ran several times using the same 4.20.7-sunxi kernel and same command= =20 > line. >=20 > Some questions that might help: > 1) Are there any specific steps you did in order to produce this error? I build QEMU with: ./configure --enable-trace-backends=3Dlog --extra-cflags=3D-ggdb --enable-d= ebug > 2) Could this be a known / existing issue? > 3) How many times did you see this error? Always > 4) Are you also using Ubuntu 18.04.3 LTS on x86_64, or a different host O= S? Host is Fedora 30. >=20 > Regards, > Niek From MAILER-DAEMON Tue Dec 10 03:29:42 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1ieatq-00078s-LW for mharc-qemu-arm@gnu.org; Tue, 10 Dec 2019 03:29:42 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:55067) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ieato-00078d-7Y for qemu-arm@nongnu.org; Tue, 10 Dec 2019 03:29:41 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ieatm-0006Fz-VG for qemu-arm@nongnu.org; Tue, 10 Dec 2019 03:29:40 -0500 Received: from us-smtp-delivery-1.mimecast.com ([207.211.31.120]:28964 helo=us-smtp-1.mimecast.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1ieatm-0006Fl-Rj for qemu-arm@nongnu.org; Tue, 10 Dec 2019 03:29:38 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1575966578; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=VcMyK4IOa6/41nvg81B4lCm1hECzWTQ/P/XjN715egk=; b=bYXIJxcYHAZzmLfmaWmmchAdICNVY4htrr/R6SDQRqKFpOjjU2nUp84nmfPvD/DBTu6+gK D6SGa03V7mE4K1OadTaYIB4JkatKmGleOoR4QbYLmRyZl3EEj/M83xyKlloisK0WoWkfG0 ro2Sj2+KiBIQFDR2yJTAwD3Y80Jdlr8= Received: from mimecast-mx01.redhat.com (mimecast-mx01.redhat.com [209.132.183.4]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-123-JAdTh2XYPdOpiMG0q2BfTw-1; Tue, 10 Dec 2019 03:29:37 -0500 Received: from smtp.corp.redhat.com (int-mx03.intmail.prod.int.phx2.redhat.com [10.5.11.13]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx01.redhat.com (Postfix) with ESMTPS id 4F319800EC0; Tue, 10 Dec 2019 08:29:36 +0000 (UTC) Received: from sirius.home.kraxel.org (ovpn-116-67.ams2.redhat.com [10.36.116.67]) by smtp.corp.redhat.com (Postfix) with ESMTP id 1888D6E504; Tue, 10 Dec 2019 08:29:33 +0000 (UTC) Received: by sirius.home.kraxel.org (Postfix, from userid 1000) id 4EBD616E19; Tue, 10 Dec 2019 09:29:32 +0100 (CET) Date: Tue, 10 Dec 2019 09:29:32 +0100 From: Gerd Hoffmann To: Philippe =?utf-8?Q?Mathieu-Daud=C3=A9?= Cc: Niek Linnenbank , qemu-devel@nongnu.org, b.galvani@gmail.com, peter.maydell@linaro.org, qemu-arm@nongnu.org Subject: Re: [PATCH 04/10] arm: allwinner-h3: add USB host controller Message-ID: <20191210082932.teizmu3nco3ndjel@sirius.home.kraxel.org> References: <20191202210947.3603-1-nieklinnenbank@gmail.com> <20191202210947.3603-5-nieklinnenbank@gmail.com> <4a900e8d-d803-5c58-5a4b-879cce5970b4@redhat.com> MIME-Version: 1.0 In-Reply-To: <4a900e8d-d803-5c58-5a4b-879cce5970b4@redhat.com> X-Scanned-By: MIMEDefang 2.79 on 10.5.11.13 X-MC-Unique: JAdTh2XYPdOpiMG0q2BfTw-1 X-Mimecast-Spam-Score: 0 Content-Type: text/plain; charset=iso-8859-1 Content-Transfer-Encoding: quoted-printable Content-Disposition: inline X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 207.211.31.120 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 10 Dec 2019 08:29:41 -0000 On Tue, Dec 10, 2019 at 08:56:02AM +0100, Philippe Mathieu-Daud=E9 wrote: > On 12/2/19 10:09 PM, Niek Linnenbank wrote: > > The Allwinner H3 System on Chip contains multiple USB 2.0 bus > > connections which provide software access using the Enhanced > > Host Controller Interface (EHCI) and Open Host Controller > > Interface (OHCI) interfaces. This commit adds support for > > both interfaces in the Allwinner H3 System on Chip. > >=20 > > Signed-off-by: Niek Linnenbank > > --- > > hw/arm/allwinner-h3.c | 20 ++++++++++++++++++++ > > hw/usb/hcd-ehci-sysbus.c | 17 +++++++++++++++++ > > hw/usb/hcd-ehci.h | 1 + >=20 > Cc'ing Gerd, the maintainer of these files. Looks all reasonable. Reviewed-by: Gerd Hoffmann (assuming this will be merged through arm tree not usb). >=20 > Reviewed-by: Philippe Mathieu-Daud=E9 >=20 > > 3 files changed, 38 insertions(+) > >=20 > > diff --git a/hw/arm/allwinner-h3.c b/hw/arm/allwinner-h3.c > > index 5566e979ec..afeb49c0ac 100644 > > --- a/hw/arm/allwinner-h3.c > > +++ b/hw/arm/allwinner-h3.c > > @@ -26,6 +26,7 @@ > > #include "hw/sysbus.h" > > #include "hw/arm/allwinner-h3.h" > > #include "hw/misc/unimp.h" > > +#include "hw/usb/hcd-ehci.h" > > #include "sysemu/sysemu.h" > > static void aw_h3_init(Object *obj) > > @@ -183,6 +184,25 @@ static void aw_h3_realize(DeviceState *dev, Error = **errp) > > } > > sysbus_mmio_map(SYS_BUS_DEVICE(&s->ccu), 0, AW_H3_CCU_BASE); > > + /* Universal Serial Bus */ > > + sysbus_create_simple(TYPE_AW_H3_EHCI, AW_H3_EHCI0_BASE, > > + s->irq[AW_H3_GIC_SPI_EHCI0]); > > + sysbus_create_simple(TYPE_AW_H3_EHCI, AW_H3_EHCI1_BASE, > > + s->irq[AW_H3_GIC_SPI_EHCI1]); > > + sysbus_create_simple(TYPE_AW_H3_EHCI, AW_H3_EHCI2_BASE, > > + s->irq[AW_H3_GIC_SPI_EHCI2]); > > + sysbus_create_simple(TYPE_AW_H3_EHCI, AW_H3_EHCI3_BASE, > > + s->irq[AW_H3_GIC_SPI_EHCI3]); > > + > > + sysbus_create_simple("sysbus-ohci", AW_H3_OHCI0_BASE, > > + s->irq[AW_H3_GIC_SPI_OHCI0]); > > + sysbus_create_simple("sysbus-ohci", AW_H3_OHCI1_BASE, > > + s->irq[AW_H3_GIC_SPI_OHCI1]); > > + sysbus_create_simple("sysbus-ohci", AW_H3_OHCI2_BASE, > > + s->irq[AW_H3_GIC_SPI_OHCI2]); > > + sysbus_create_simple("sysbus-ohci", AW_H3_OHCI3_BASE, > > + s->irq[AW_H3_GIC_SPI_OHCI3]); > > + > > /* UART */ > > if (serial_hd(0)) { > > serial_mm_init(get_system_memory(), AW_H3_UART0_REG_BASE, 2, > > diff --git a/hw/usb/hcd-ehci-sysbus.c b/hw/usb/hcd-ehci-sysbus.c > > index 020211fd10..174c3446ef 100644 > > --- a/hw/usb/hcd-ehci-sysbus.c > > +++ b/hw/usb/hcd-ehci-sysbus.c > > @@ -145,6 +145,22 @@ static const TypeInfo ehci_exynos4210_type_info = =3D { > > .class_init =3D ehci_exynos4210_class_init, > > }; > > +static void ehci_aw_h3_class_init(ObjectClass *oc, void *data) > > +{ > > + SysBusEHCIClass *sec =3D SYS_BUS_EHCI_CLASS(oc); > > + DeviceClass *dc =3D DEVICE_CLASS(oc); > > + > > + sec->capsbase =3D 0x0; > > + sec->opregbase =3D 0x10; > > + set_bit(DEVICE_CATEGORY_USB, dc->categories); > > +} > > + > > +static const TypeInfo ehci_aw_h3_type_info =3D { > > + .name =3D TYPE_AW_H3_EHCI, > > + .parent =3D TYPE_SYS_BUS_EHCI, > > + .class_init =3D ehci_aw_h3_class_init, > > +}; > > + > > static void ehci_tegra2_class_init(ObjectClass *oc, void *data) > > { > > SysBusEHCIClass *sec =3D SYS_BUS_EHCI_CLASS(oc); > > @@ -267,6 +283,7 @@ static void ehci_sysbus_register_types(void) > > type_register_static(&ehci_platform_type_info); > > type_register_static(&ehci_xlnx_type_info); > > type_register_static(&ehci_exynos4210_type_info); > > + type_register_static(&ehci_aw_h3_type_info); > > type_register_static(&ehci_tegra2_type_info); > > type_register_static(&ehci_ppc4xx_type_info); > > type_register_static(&ehci_fusbh200_type_info); > > diff --git a/hw/usb/hcd-ehci.h b/hw/usb/hcd-ehci.h > > index 0298238f0b..edb59311c4 100644 > > --- a/hw/usb/hcd-ehci.h > > +++ b/hw/usb/hcd-ehci.h > > @@ -342,6 +342,7 @@ typedef struct EHCIPCIState { > > #define TYPE_SYS_BUS_EHCI "sysbus-ehci-usb" > > #define TYPE_PLATFORM_EHCI "platform-ehci-usb" > > #define TYPE_EXYNOS4210_EHCI "exynos4210-ehci-usb" > > +#define TYPE_AW_H3_EHCI "aw-h3-ehci-usb" > > #define TYPE_TEGRA2_EHCI "tegra2-ehci-usb" > > #define TYPE_PPC4xx_EHCI "ppc4xx-ehci-usb" > > #define TYPE_FUSBH200_EHCI "fusbh200-ehci-usb" > >=20 >=20 From MAILER-DAEMON Tue Dec 10 03:40:26 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1ieb4E-0000sw-NF for mharc-qemu-arm@gnu.org; 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[88.21.103.182]) by smtp.gmail.com with ESMTPSA id f9sm2203201wmb.4.2019.12.10.00.40.09 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 10 Dec 2019 00:40:09 -0800 (PST) Subject: Re: [PATCH 00/10] Add Allwinner H3 SoC and Orange Pi PC Machine To: Niek Linnenbank , =?UTF-8?Q?Alex_Benn=c3=a9e?= Cc: qemu-devel@nongnu.org, b.galvani@gmail.com, Peter Maydell , qemu-arm@nongnu.org, Richard Henderson References: <20191202210947.3603-1-nieklinnenbank@gmail.com> From: =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= Message-ID: <14e0a506-19c0-ab9d-70b3-700995b2bfa7@redhat.com> Date: Tue, 10 Dec 2019 09:40:08 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.2.2 MIME-Version: 1.0 In-Reply-To: Content-Language: en-US X-MC-Unique: dqHVkALvNLefy9Ul_7Sd3g-1 X-Mimecast-Spam-Score: 0 Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 207.211.31.120 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 10 Dec 2019 08:40:23 -0000 Cc'ing Alex. On 12/3/19 8:25 PM, Niek Linnenbank wrote: > Hi Philippe, >=20 > Thanks for your very quick response! > I remember I have seen this error before while working on the patches,=20 > in particular > on the SMP part. I'll try to reproduce this error with the 4.20 sunxi=20 > kernel you used and debug it. >=20 > Could it be related to the change I made in patch 0006 for the CP10/CP11= =20 > bits? > Basically I needed to add that to get the CPUCFG module working. It is=20 > an interface > that U-Boot uses to reset the secondary cores for PSCI functionality. I u= sed > the arm_set_cpu_on() function there to reset the cores at the desired=20 > start address, > but Im not sure if that function is the right choice. At some point=20 > while rebasing the patches, > I got undefined exceptions which turned out to be because of the=20 > CP10/CP11 bits missing. > If I made an obvious mistake there, please let me know and I'll correct i= t. >=20 > Regards, > Niek >=20 >=20 > On Tue, Dec 3, 2019 at 9:47 AM Philippe Mathieu-Daud=C3=A9 > wrote: >=20 > On 12/2/19 10:09 PM, Niek Linnenbank wrote: > > Dear QEMU developers, > > > > Hereby I would like to contribute the following set of patches to > QEMU > > which add support for the Allwinner H3 System on Chip and the > > Orange Pi PC machine. The following features and devices are > supported: > > > >=C2=A0 =C2=A0* SMP (Quad Core Cortex A7) > >=C2=A0 =C2=A0* Generic Interrupt Controller configuration > >=C2=A0 =C2=A0* SRAM mappings > >=C2=A0 =C2=A0* Timer device (re-used from Allwinner A10) > >=C2=A0 =C2=A0* UART > >=C2=A0 =C2=A0* SD/MMC storage controller > >=C2=A0 =C2=A0* EMAC ethernet connectivity > >=C2=A0 =C2=A0* USB 2.0 interfaces > >=C2=A0 =C2=A0* Clock Control Unit > >=C2=A0 =C2=A0* System Control module > >=C2=A0 =C2=A0* Security Identifier device >=20 > Awesome! >=20 > > Functionality related to graphical output such as HDMI, GPU, > > Display Engine and audio are not included. Recently released > > mainline Linux kernels (4.19 up to latest master) and mainline U-B= oot > > are known to work. The SD/MMC code is tested using bonnie++ and > > various tools such as fsck, dd and fdisk. The EMAC is verified > with iperf3 > > using -netdev socket. > > > > To build a Linux mainline kernel that can be booted by the Orange > Pi PC > > machine, simply configure the kernel using the sunxi_defconfig > configuration: > >=C2=A0 =C2=A0$ ARCH=3Darm CROSS_COMPILE=3Darm-linux-gnueabi- make m= rproper > >=C2=A0 =C2=A0$ ARCH=3Darm CROSS_COMPILE=3Darm-linux-gnueabi- make s= unxi_defconfig > > > > To be able to use USB storage, you need to manually enable the > corresponding > > configuration item. Start the kconfig configuration tool: > >=C2=A0 =C2=A0$ ARCH=3Darm CROSS_COMPILE=3Darm-linux-gnueabi- make m= enuconfig > > > > Navigate to the following item, enable it and save your > configuration: > >=C2=A0 =C2=A0Device Drivers > USB support > USB Mass Storage suppor= t > > > > Build the Linux kernel with: > >=C2=A0 =C2=A0$ ARCH=3Darm CROSS_COMPILE=3Darm-linux-gnueabi- make -= j5 > > > > To boot the newly build linux kernel in QEMU with the Orange Pi > PC machine, use: > >=C2=A0 =C2=A0$ qemu-system-arm -M orangepi -m 512 -nic user -nograp= hic \ > >=C2=A0 =C2=A0 =C2=A0 =C2=A0-kernel /path/to/linux/arch/arm/boot/zIm= age \ > >=C2=A0 =C2=A0 =C2=A0 =C2=A0-append 'console=3DttyS0,115200' \ > >=C2=A0 =C2=A0 =C2=A0 =C2=A0-dtb /path/to/linux/arch/arm/boot/dts/su= n8i-h3-orangepi-pc.dtb > > > > Note that this kernel does not have a root filesystem. You may > provide it > > with an official Orange Pi PC image [1] either as an SD card or as > > USB mass storage. To boot using the Orange Pi PC Debian image on > SD card, > > simply add the -sd argument and provide the proper root=3D kernel > parameter: > >=C2=A0 =C2=A0$ qemu-system-arm -M orangepi -m 512 -nic user -nograp= hic \ > >=C2=A0 =C2=A0 =C2=A0 =C2=A0-kernel /path/to/linux/arch/arm/boot/zIm= age \ > >=C2=A0 =C2=A0 =C2=A0 =C2=A0-append 'console=3DttyS0,115200 root=3D/= dev/mmcblk0p2' \ > >=C2=A0 =C2=A0 =C2=A0 =C2=A0-dtb > /path/to/linux/arch/arm/boot/dts/sun8i-h3-orangepi-pc.dtb \ > >=C2=A0 =C2=A0 =C2=A0 =C2=A0-sd OrangePi_pc_debian_stretch_server_li= nux5.3.5_v1.0.img > > > > Alternatively, you can also choose to build and boot a recent > buildroot [2] > > using the orangepi_pc_defconfig or Armbian image [3] for Orange > Pi PC. >=20 > Richard, trying the Armbian image from > https://apt.armbian.com/pool/main/l/linux-4.20.7-sunxi/ I get: >=20 > $ arm-softmmu/qemu-system-arm -M orangepi -m 512 -nic user \ > =C2=A0 =C2=A0-append 'console=3DttyS0,115200' \ > =C2=A0 =C2=A0-kernel boot/vmlinuz-4.20.7-sunxi \ > =C2=A0 =C2=A0-dtb usr/lib/linux-image-dev-sunxi/sun8i-h3-orangepi-pc= .dtb \ > =C2=A0 =C2=A0-serial stdio -d unimp > Uncompressing Linux... done, booting the kernel. > rtc: unimplemented device write (size 4, value 0x16aa0001, offset 0x0= ) > rtc: unimplemented device read (size 4, offset 0x0) > rtc: unimplemented device read (size 4, offset 0x0) > rtc: unimplemented device read (size 4, offset 0x8) > qemu-system-arm: target/arm/helper.c:11359: cpu_get_tb_cpu_state: > Assertion `flags =3D=3D rebuild_hflags_internal(env)' failed. > Aborted (core dumped) To have ELF debug info I built a Linux kernel around v5.5-rc1 (commit=20 2f13437b8) with: $ make ARCH=3Darm CROSS_COMPILE=3Darm-linux-gnu- sunxi_defconfig zImage Then I applied Alex patch and mine on top of your series: https://www.mail-archive.com/qemu-devel@nongnu.org/msg663850.html https://www.mail-archive.com/qemu-devel@nongnu.org/msg663843.html Running with -d in_asm,cpu: ---------------- IN: 0xc0102128: e281c018 add ip, r1, #0x18 0xc010212c: e8ac6ff0 stm ip!, {r4, r5, r6, r7, r8, sb, sl, fp,=20 sp, lr} 0xc0102130: e592405c ldr r4, [r2, #0x5c] 0xc0102134: e5925060 ldr r5, [r2, #0x60] 0xc0102138: ee1d7f50 mrc p15, #0, r7, c13, c0, #2 0xc010213c: ee0d4f70 mcr p15, #0, r4, c13, c0, #3 R00=3Dc0a07c40 R01=3Dc0a00000 R02=3Dc685a000 R03=3D00000000 R04=3Dc6ea7cc0 R05=3Dc0a07c40 R06=3Dc68405c0 R07=3Dc0958cc0 R08=3D00000000 R09=3D0654f000 R10=3Dc0701e8c R11=3Dc0a01f94 R12=3D00000000 R13=3Dc0a01f50 R14=3Dc06df2fc R15=3Dc0102128 PSR=3D600000d3 -ZC- A NS svc32 ---------------- IN: 0xc0102140: ee0d5f50 mcr p15, #0, r5, c13, c0, #2 R00=3Dc0a07c40 R01=3Dc0a00000 R02=3Dc685a000 R03=3D00000000 R04=3D00000000 R05=3D00000000 R06=3Dc68405c0 R07=3D00000000 R08=3D00000000 R09=3D0654f000 R10=3Dc0701e8c R11=3Dc0a01f94 R12=3Dc0a00040 R13=3Dc0a01f50 R14=3Dc06df2fc R15=3Dc0102140 PSR=3D600000d3 -ZC- A NS svc32 ---------------- TCG hflags mismatch (current:0x33600000 rebuilt:0x20200040) Aborted (core dumped) (gdb) disas __switch_to Dump of assembler code for function __switch_to: 0xc0102128 <+0>: add r12, r1, #24 0xc010212c <+4>: stmia r12!, {r4, r5, r6, r7, r8, r9, r10,=20 r11, sp, lr} 0xc0102130 <+8>: ldr r4, [r2, #92] ; 0x5c 0xc0102134 <+12>: ldr r5, [r2, #96] ; 0x60 0xc0102138 <+16>: mrc 15, 0, r7, cr13, cr0, {2} 0xc010213c <+20>: mcr 15, 0, r4, cr13, cr0, {3} 0xc0102140 <+24>: mcr 15, 0, r5, cr13, cr0, {2} 0xc0102144 <+28>: str r7, [r1, #96] ; 0x60 0xc0102148 <+32>: mov r5, r0 0xc010214c <+36>: add r4, r2, #24 0xc0102150 <+40>: ldr r0, [pc, #12] ; 0xc0102164 0xc0102154 <+44>: mov r1, #2 0xc0102158 <+48>: bl 0xc013e348 0xc010215c <+52>: mov r0, r5 0xc0102160 <+56>: ldm r4, {r4, r5, r6, r7, r8, r9, r10, r11,=20 sp, pc} (gdb) x/10i 0xc06df2f0 - 12 0xc06df2e4 <__schedule+532>: mov r0, r5 0xc06df2e8 <__schedule+536>: bic r3, r3, #3 0xc06df2ec <__schedule+540>: str r3, [r4, #1376] ; 0x560 0xc06df2f0 <__schedule+544>: ldr r2, [r6, #4] 0xc06df2f4 <__schedule+548>: ldr r1, [r5, #4] 0xc06df2f8 <__schedule+552>: bl 0xc0102128 <__switch_to> 0xc06df2fc <__schedule+556>: bl 0xc0141f00 0xc06df300 <__schedule+560>: mov r4, r0 0xc06df304 <__schedule+564>: ldr r3, [r4, #1452] ; 0x5ac 0xc06df308 <__schedule+568>: cmp r3, #0 Note from patch #1: CPU is cortex-a7 with: object_property_set_bool(cpuobj, true, "has_el3", NULL); object_property_set_bool(cpuobj, true, "has_el2", NULL); >=20 > (gdb) bt > #0=C2=A0 0x00007f6c1fa2ce35 in raise () at /lib64/libc.so.6 > #1=C2=A0 0x00007f6c1fa17895 in abort () at /lib64/libc.so.6 > #2=C2=A0 0x00007f6c1fa17769 in _nl_load_domain.cold () at /lib64/libc= .so.6 > #3=C2=A0 0x00007f6c1fa25566 in annobin_assert.c_end () at /lib64/libc= .so.6 > #4=C2=A0 0x00005590657e2685 in cpu_get_tb_cpu_state (env=3D0x55906868= 99b0, > pc=3D0x7f6c07ffa718, cs_base=3D0x7f6c07ffa714, pflags=3D0x7f6c07ffa71= c) at > target/arm/helper.c:11359 > #5=C2=A0 0x000055906569f962 in tb_lookup__cpu_state (cpu=3D0x55906868= 08b0, > pc=3D0x7f6c07ffa718, cs_base=3D0x7f6c07ffa714, flags=3D0x7f6c07ffa71c= , > cf_mask=3D524288) at include/exec/tb-lookup.h:28 > #6=C2=A0 0x00005590656a084c in tb_find (cpu=3D0x5590686808b0, last_tb= =3D0x0, > tb_exit=3D0, cf_mask=3D524288) at accel/tcg/cpu-exec.c:403 > #7=C2=A0 0x00005590656a114a in cpu_exec (cpu=3D0x5590686808b0) at > accel/tcg/cpu-exec.c:730 > #8=C2=A0 0x000055906565f6af in tcg_cpu_exec (cpu=3D0x5590686808b0) at > cpus.c:1473 > #9=C2=A0 0x000055906565ff05 in qemu_tcg_cpu_thread_fn > (arg=3D0x5590686808b0) at > cpus.c:1781 > #10 0x0000559065d54aa6 in qemu_thread_start (args=3D0x5590687d8c20) a= t > util/qemu-thread-posix.c:519 > #11 0x00007f6c1fbc54c0 in start_thread () at /lib64/libpthread.so.0 > #12 0x00007f6c1faf1553 in clone () at /lib64/libc.so.6 >=20 > (gdb) p/x flags > $1 =3D 0x33600000 >=20 > (gdb) p/x *env > $2 =3D {regs =3D {0x0 , 0x40102448}, xregs =3D {0x0 > 32 times>}, pc =3D 0x0, pstate =3D 0x0, aarch64 =3D 0x0, hflags =3D 0= x33600000, > uncached_cpsr =3D 0x1a, spsr =3D 0x0, banked_spsr =3D {0x0, 0x0, 0x0,= 0x0, > 0x0, 0x0, 0x0, 0x0}, > =C2=A0 =C2=A0banked_r13 =3D {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}= , banked_r14 =3D > {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, usr_regs =3D {0x0, 0x0, 0x0= , > 0x0, 0x0}, fiq_regs =3D {0x0, 0x0, 0x0, 0x0, 0x0}, CF =3D 0x0, VF =3D= 0x0, NF > =3D 0x0, ZF =3D 0x0, > =C2=A0 =C2=A0QF =3D 0x0, GE =3D 0x0, thumb =3D 0x1, condexec_bits = =3D 0x0, btype =3D 0x0, > daif =3D 0x3c0, elr_el =3D {0x0, 0x0, 0x0, 0x0}, sp_el =3D {0x0, 0x0,= 0x0, > 0x0}, cp15 =3D {c0_cpuid =3D 0x410fc075, {{_unused_csselr0 =3D 0x0, c= sselr_ns > =3D 0x0, > =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0_unused_csselr1 =3D 0x0, csselr_s = =3D 0x0}, csselr_el =3D {0x0, > 0x0, > 0x0, 0x0}}, {{_unused_sctlr =3D 0x0, sctlr_ns =3D 0xc50078, hsctlr = =3D 0x0, > sctlr_s =3D 0xc50078}, sctlr_el =3D {0x0, 0xc50078, 0x0, 0xc50078}}, > cpacr_el1 =3D 0x0, cptr_el =3D { > =C2=A0 =C2=A0 =C2=A0 =C2=A00x0, 0x0, 0x0, 0x0}, c1_xscaleauxcr =3D 0= x0, sder =3D 0x0, nsacr =3D > 0xc00, {{_unused_ttbr0_0 =3D 0x0, ttbr0_ns =3D 0x0, _unused_ttbr0_1 = =3D 0x0, > ttbr0_s =3D 0x0}, ttbr0_el =3D {0x0, 0x0, 0x0, 0x0}}, {{_unused_ttbr1= _0 =3D > 0x0, ttbr1_ns =3D 0x0, > =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0_unused_ttbr1_1 =3D 0x0, ttbr1_s = =3D 0x0}, ttbr1_el =3D {0x0, 0x0, > 0x0, 0x0}}, vttbr_el2 =3D 0x0, tcr_el =3D {{raw_tcr =3D 0x0, mask =3D= 0x0, > base_mask =3D 0x0}, {raw_tcr =3D 0x0, mask =3D 0x0, base_mask =3D 0xf= fffc000}, > {raw_tcr =3D 0x0, mask =3D 0x0, > =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0base_mask =3D 0x0}, {raw_tcr =3D 0= x0, mask =3D 0x0, base_mask =3D > 0xffffc000}}, vtcr_el2 =3D {raw_tcr =3D 0x0, mask =3D 0x0, base_mask = =3D 0x0}, > c2_data =3D 0x0, c2_insn =3D 0x0, {{dacr_ns =3D 0x0, dacr_s =3D 0x0}, > {dacr32_el2 =3D 0x0}}, > =C2=A0 =C2=A0 =C2=A0pmsav5_data_ap =3D 0x0, pmsav5_insn_ap =3D 0x0, = hcr_el2 =3D 0x0, > scr_el3 > =3D 0x101, {{ifsr_ns =3D 0x0, ifsr_s =3D 0x0}, {ifsr32_el2 =3D 0x0}}, > {{_unused_dfsr =3D 0x0, dfsr_ns =3D 0x0, hsr =3D 0x0, dfsr_s =3D 0x0}= , esr_el =3D > {0x0, 0x0, 0x0, 0x0}}, > =C2=A0 =C2=A0 =C2=A0c6_region =3D {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0= , 0x0}, > {{_unused_far0 =3D 0x0, dfar_ns =3D 0x0, ifar_ns =3D 0x0, dfar_s =3D = 0x0, > ifar_s > =3D 0x0, _unused_far3 =3D 0x0}, far_el =3D {0x0, 0x0, 0x0, 0x0}}, hpf= ar_el2 =3D > 0x0, hstr_el2 =3D 0x0, {{ > =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0_unused_par_0 =3D 0x0, par_ns =3D = 0x0, _unused_par_1 =3D 0x0, > par_s =3D > 0x0}, par_el =3D {0x0, 0x0, 0x0, 0x0}}, c9_insn =3D 0x0, c9_data =3D = 0x0, > c9_pmcr =3D 0x41002000, c9_pmcnten =3D 0x0, c9_pmovsr =3D 0x0, c9_pmu= serenr =3D > 0x0, c9_pmselr =3D 0x0, > =C2=A0 =C2=A0 =C2=A0c9_pminten =3D 0x0, {{_unused_mair_0 =3D 0x0, ma= ir0_ns =3D 0x0, > mair1_ns > =3D 0x0, _unused_mair_1 =3D 0x0, mair0_s =3D 0x0, mair1_s =3D 0x0}, m= air_el =3D > {0x0, 0x0, 0x0, 0x0}}, {{_unused_vbar =3D 0x0, vbar_ns =3D 0x0, hvbar= =3D > 0x0, > vbar_s =3D 0x0}, > =C2=A0 =C2=A0 =C2=A0 =C2=A0vbar_el =3D {0x0, 0x0, 0x0, 0x0}}, mvbar = =3D 0x0, {fcseidr_ns =3D > 0x0, > fcseidr_s =3D 0x0}, {{_unused_contextidr_0 =3D 0x0, contextidr_ns =3D= 0x0, > _unused_contextidr_1 =3D 0x0, contextidr_s =3D 0x0}, contextidr_el = =3D {0x0, > 0x0, 0x0, 0x0}}, {{ > =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0tpidrurw_ns =3D 0x0, tpidrprw_ns = =3D 0x0, htpidr =3D 0x0, > _tpidr_el3 > =3D 0x0}, tpidr_el =3D {0x0, 0x0, 0x0, 0x0}}, tpidrurw_s =3D 0x0, > tpidrprw_s =3D > 0x0, tpidruro_s =3D 0x0, {tpidruro_ns =3D 0x0, tpidrro_el =3D {0x0}}, > c14_cntfrq =3D 0x3b9aca0, > =C2=A0 =C2=A0 =C2=A0c14_cntkctl =3D 0x0, cnthctl_el2 =3D 0x3, cntvof= f_el2 =3D 0x0, > c14_timer > =3D {{cval =3D 0x0, ctl =3D 0x0}, {cval =3D 0x0, ctl =3D 0x0}, {cval = =3D 0x0, ctl =3D > 0x0}, {cval =3D 0x0, ctl =3D 0x0}}, c15_cpar =3D 0x0, c15_ticonfig = =3D 0x0, > c15_i_max =3D 0x0, > =C2=A0 =C2=A0 =C2=A0c15_i_min =3D 0x0, c15_threadid =3D 0x0, c15_con= fig_base_address =3D > 0x0, > c15_diagnostic =3D 0x0, c15_power_diagnostic =3D 0x0, c15_power_contr= ol =3D > 0x0, dbgbvr =3D {0x0 }, dbgbcr =3D {0x0 times>}, dbgwvr =3D { > =C2=A0 =C2=A0 =C2=A0 =C2=A00x0 }, dbgwcr =3D {0x0 = }, > mdscr_el1 =3D 0x0, oslsr_el1 =3D 0xa, mdcr_el2 =3D 0x0, mdcr_el3 =3D = 0x0, > c15_ccnt =3D 0x0, c15_ccnt_delta =3D 0x0, c14_pmevcntr =3D {0x0 times>}, c14_pmevcntr_delta =3D { > =C2=A0 =C2=A0 =C2=A0 =C2=A00x0 }, c14_pmevtyper = =3D {0x0 times>}, pmccfiltr_el0 =3D 0x0, vpidr_el2 =3D 0x410fc075, vmpidr_el2 = =3D > 0x80000001}, v7m =3D {other_sp =3D 0x0, other_ss_msp =3D 0x0, other_s= s_psp =3D > 0x0, vecbase =3D {0x0, 0x0}, > =C2=A0 =C2=A0 =C2=A0basepri =3D {0x0, 0x0}, control =3D {0x0, 0x0}, = ccr =3D {0x0, 0x0}, > cfsr > =3D {0x0, 0x0}, hfsr =3D 0x0, dfsr =3D 0x0, sfsr =3D 0x0, mmfar =3D {= 0x0, 0x0}, > bfar =3D 0x0, sfar =3D 0x0, mpu_ctrl =3D {0x0, 0x0}, exception =3D 0x= 0, primask > =3D {0x0, 0x0}, > =C2=A0 =C2=A0 =C2=A0faultmask =3D {0x0, 0x0}, aircr =3D 0x0, secure = =3D 0x0, csselr =3D {0x0, > 0x0}, scr =3D {0x0, 0x0}, msplim =3D {0x0, 0x0}, psplim =3D {0x0, 0x0= }, fpcar > =3D {0x0, 0x0}, fpccr =3D {0x0, 0x0}, fpdscr =3D {0x0, 0x0}, cpacr = =3D {0x0, > 0x0}, nsacr =3D 0x0}, > =C2=A0 =C2=A0exception =3D {syndrome =3D 0x0, fsr =3D 0x0, vaddress = =3D 0x0, target_el =3D > 0x0}, serror =3D {pending =3D 0x0, has_esr =3D 0x0, esr =3D 0x0}, > irq_line_state > =3D 0x0, teecr =3D 0x0, teehbr =3D 0x0, vfp =3D {zregs =3D {{d =3D {0= x0, 0x0}} > }, > =C2=A0 =C2=A0 =C2=A0qc =3D {0x0, 0x0, 0x0, 0x0}, vec_len =3D 0x0, ve= c_stride =3D 0x0, > xregs =3D > {0x41023075, 0x0, 0x0, 0x0, 0x0, 0x0, 0x11111111, 0x10110222, 0x0, 0x= 0, > 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, scratch =3D {0x0, 0x0, 0x0, 0x0, 0x0, = 0x0, > 0x0, 0x0}, > =C2=A0 =C2=A0 =C2=A0fp_status =3D {float_detect_tininess =3D 0x1, fl= oat_rounding_mode =3D > 0x0, float_exception_flags =3D 0x0, floatx80_rounding_precision =3D 0= x0, > flush_to_zero =3D 0x0, flush_inputs_to_zero =3D 0x0, default_nan_mode= =3D > 0x0, > snan_bit_is_one =3D 0x0}, > =C2=A0 =C2=A0 =C2=A0fp_status_f16 =3D {float_detect_tininess =3D 0x1= , > float_rounding_mode =3D > 0x0, float_exception_flags =3D 0x0, floatx80_rounding_precision =3D 0= x0, > flush_to_zero =3D 0x0, flush_inputs_to_zero =3D 0x0, default_nan_mode= =3D 0x0, > =C2=A0 =C2=A0 =C2=A0 =C2=A0snan_bit_is_one =3D 0x0}, standard_fp_sta= tus =3D > {float_detect_tininess =3D 0x1, float_rounding_mode =3D 0x0, > float_exception_flags =3D 0x0, floatx80_rounding_precision =3D 0x0, > flush_to_zero =3D 0x1, flush_inputs_to_zero =3D 0x1, > =C2=A0 =C2=A0 =C2=A0 =C2=A0default_nan_mode =3D 0x1, snan_bit_is_one= =3D 0x0}, zcr_el =3D {0x0, > 0x0, 0x0, 0x0}}, exclusive_addr =3D 0xffffffffffffffff, exclusive_val= =3D > 0x0, exclusive_high =3D 0x0, iwmmxt =3D {regs =3D {0x0 }, > val =3D 0x0, cregs =3D { > =C2=A0 =C2=A0 =C2=A0 =C2=A00x0 }}, cpu_breakpoint = =3D {0x0 times>}, cpu_watchpoint =3D {0x0 }, end_reset_field= s =3D > {}, features =3D 0xfd38fbe6f3, pmsav7 =3D {drbar =3D = 0x0, > drsr > =3D 0x0, dracr =3D 0x0, > =C2=A0 =C2=A0 =C2=A0rnr =3D {0x0, 0x0}}, pmsav8 =3D {rbar =3D {0x0, = 0x0}, rlar =3D {0x0, > 0x0}, > mair0 =3D {0x0, 0x0}, mair1 =3D {0x0, 0x0}}, sau =3D {rbar =3D 0x0, r= lar =3D 0x0, > rnr =3D 0x0, ctrl =3D 0x0}, nvic =3D 0x0, boot_info =3D 0x5622af3a17a= 0, > gicv3state =3D 0x0} >=20 > > [1] http://www.orangepi.org/downloadresources/ > > [2] https://buildroot.org/download.html > > [3] https://www.armbian.com/orange-pi-pc/ >=20 >=20 >=20 > --=20 > Niek Linnenbank >=20 > WWW: http://www.nieklinnenbank.nl/ > BLOG: http://nieklinnenbank.wordpress.com/ > FUN: http://www.FreeNOS.org/ From MAILER-DAEMON Tue Dec 10 03:53:40 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1iebH1-0004PI-UW for mharc-qemu-arm@gnu.org; Tue, 10 Dec 2019 03:53:39 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:57430) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iebH0-0004P4-Bc for qemu-arm@nongnu.org; Tue, 10 Dec 2019 03:53:39 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1iebGz-0005r7-EE for qemu-arm@nongnu.org; Tue, 10 Dec 2019 03:53:38 -0500 Received: from 1.mo68.mail-out.ovh.net ([46.105.41.146]:57768) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1iebGz-0005qb-7k for qemu-arm@nongnu.org; Tue, 10 Dec 2019 03:53:37 -0500 Received: from player711.ha.ovh.net (unknown [10.109.146.86]) by mo68.mail-out.ovh.net (Postfix) with ESMTP id 4C5E8147515 for ; Tue, 10 Dec 2019 09:53:35 +0100 (CET) Received: from kaod.org (lfbn-1-2229-223.w90-76.abo.wanadoo.fr [90.76.50.223]) (Authenticated sender: clg@kaod.org) by player711.ha.ovh.net (Postfix) with ESMTPSA id 35262CFBD502; Tue, 10 Dec 2019 08:53:30 +0000 (UTC) Subject: Re: [PATCH 0/2] hw/arm: ast2600: Wire up eMMC controller To: Andrew Jeffery , qemu-arm@nongnu.org Cc: peter.maydell@linaro.org, joel@jms.id.au, qemu-devel@nongnu.org References: From: =?UTF-8?Q?C=c3=a9dric_Le_Goater?= Message-ID: <378a875a-17c8-3b35-9753-2158e86c5412@kaod.org> Date: Tue, 10 Dec 2019 09:53:28 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.1.1 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 7bit X-Ovh-Tracer-Id: 6705296898481425216 X-VR-SPAMSTATE: OK X-VR-SPAMSCORE: -100 X-VR-SPAMCAUSE: gggruggvucftvghtrhhoucdtuddrgedufedrudelvddguddvfecutefuodetggdotefrodftvfcurfhrohhfihhlvgemucfqggfjpdevjffgvefmvefgnecuuegrihhlohhuthemucehtddtnecusecvtfgvtghiphhivghnthhsucdlqddutddtmdenucfjughrpefuvfhfhffkffgfgggjtgfgsehtjeertddtfeejnecuhfhrohhmpeevrogurhhitggpnfgvpgfiohgrthgvrhcuoegtlhhgsehkrghougdrohhrgheqnecukfhppedtrddtrddtrddtpdeltddrjeeirdehtddrvddvfeenucfrrghrrghmpehmohguvgepshhmthhpqdhouhhtpdhhvghlohepphhlrgihvghrjeduuddrhhgrrdhovhhhrdhnvghtpdhinhgvtheptddrtddrtddrtddpmhgrihhlfhhrohhmpegtlhhgsehkrghougdrohhrghdprhgtphhtthhopehqvghmuhdqrghrmhesnhhonhhgnhhurdhorhhgnecuvehluhhsthgvrhfuihiivgeptd X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 46.105.41.146 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 10 Dec 2019 08:53:39 -0000 On 10/12/2019 01:52, Andrew Jeffery wrote: > Hello, > > The AST2600 has an additional SDHCI intended for use as an eMMC boot source. Have you also considered booting the QEMU Aspeed AST2600 machine from the eMMC device ? C. > These two patches rework the existing ASPEED SDHCI model to accommodate the > single-slot nature of the eMMC controller and wire it into the AST2600 SoC. > > Please review! > > Andrew > > Andrew Jeffery (2): > hw/sd: Configure number of slots exposed by the ASPEED SDHCI model > hw/arm: ast2600: Wire up the eMMC controller > > hw/arm/aspeed.c | 15 ++++++++++++++- > hw/arm/aspeed_ast2600.c | 23 +++++++++++++++++++++++ > hw/arm/aspeed_soc.c | 3 +++ > hw/sd/aspeed_sdhci.c | 11 +++++++++-- > include/hw/arm/aspeed_soc.h | 2 ++ > include/hw/sd/aspeed_sdhci.h | 1 + > 6 files changed, 52 insertions(+), 3 deletions(-) > > base-commit: 6a4ef4e5d1084ce41fafa7d470a644b0fd3d9317 > From MAILER-DAEMON Tue Dec 10 03:56:42 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1iebJy-0005np-2V for mharc-qemu-arm@gnu.org; Tue, 10 Dec 2019 03:56:42 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:57649) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iebJu-0005mG-Lr for qemu-arm@nongnu.org; Tue, 10 Dec 2019 03:56:40 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1iebJt-0006fM-DA for qemu-arm@nongnu.org; Tue, 10 Dec 2019 03:56:38 -0500 Received: from 2.mo2.mail-out.ovh.net ([188.165.53.149]:38053) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1iebJt-0006ex-6R for qemu-arm@nongnu.org; Tue, 10 Dec 2019 03:56:37 -0500 Received: from player789.ha.ovh.net (unknown [10.109.143.183]) by mo2.mail-out.ovh.net (Postfix) with ESMTP id 314D21BC121 for ; Tue, 10 Dec 2019 09:56:35 +0100 (CET) Received: from kaod.org (lfbn-1-2229-223.w90-76.abo.wanadoo.fr [90.76.50.223]) (Authenticated sender: clg@kaod.org) by player789.ha.ovh.net (Postfix) with ESMTPSA id E8861D0DE6FD; Tue, 10 Dec 2019 08:56:28 +0000 (UTC) Subject: Re: [PATCH 1/2] hw/sd: Configure number of slots exposed by the ASPEED SDHCI model To: Andrew Jeffery , qemu-arm@nongnu.org Cc: peter.maydell@linaro.org, joel@jms.id.au, qemu-devel@nongnu.org References: <11e1d38d2374a48996a3496c906db215de246583.1575938234.git-series.andrew@aj.id.au> From: =?UTF-8?Q?C=c3=a9dric_Le_Goater?= Message-ID: Date: Tue, 10 Dec 2019 09:56:28 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.1.1 MIME-Version: 1.0 In-Reply-To: <11e1d38d2374a48996a3496c906db215de246583.1575938234.git-series.andrew@aj.id.au> Content-Type: text/plain; charset=utf-8 Content-Language: en-US X-Ovh-Tracer-Id: 6755962394227936064 X-VR-SPAMSTATE: OK X-VR-SPAMSCORE: -100 X-VR-SPAMCAUSE: gggruggvucftvghtrhhoucdtuddrgedufedrudelvddguddvgecutefuodetggdotefrodftvfcurfhrohhfihhlvgemucfqggfjpdevjffgvefmvefgnecuuegrihhlohhuthemucehtddtnecusecvtfgvtghiphhivghnthhsucdlqddutddtmdenucfjughrpefuvfhfhffkffgfgggjtgfgsehtkeertddtfeejnecuhfhrohhmpeevrogurhhitggpnfgvpgfiohgrthgvrhcuoegtlhhgsehkrghougdrohhrgheqnecukfhppedtrddtrddtrddtpdeltddrjeeirdehtddrvddvfeenucfrrghrrghmpehmohguvgepshhmthhpqdhouhhtpdhhvghlohepphhlrgihvghrjeekledrhhgrrdhovhhhrdhnvghtpdhinhgvtheptddrtddrtddrtddpmhgrihhlfhhrohhmpegtlhhgsehkrghougdrohhrghdprhgtphhtthhopehqvghmuhdqrghrmhesnhhonhhgnhhurdhorhhgnecuvehluhhsthgvrhfuihiivgeptd Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 188.165.53.149 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 10 Dec 2019 08:56:40 -0000 On 10/12/2019 01:52, Andrew Jeffery wrote: > The AST2600 includes a second cut-down version of the SD/MMC controller > found in the AST2500, named the eMMC controller. It's cut down in the > sense that it only supports one slot rather than two, but it brings the > total number of slots supported by the AST2600 to three. >=20 > The existing code assumed that the SD controller always provided two > slots. Rework the SDHCI object to expose the number of slots as a > property to be set by the SoC configuration. >=20 > Signed-off-by: Andrew Jeffery Reviewed-by: C=C3=A9dric Le Goater One minor question below. > --- > hw/arm/aspeed.c | 2 +- > hw/arm/aspeed_ast2600.c | 2 ++ > hw/arm/aspeed_soc.c | 3 +++ > hw/sd/aspeed_sdhci.c | 11 +++++++++-- > include/hw/sd/aspeed_sdhci.h | 1 + > 5 files changed, 16 insertions(+), 3 deletions(-) >=20 > diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c > index 028191ff36fc..862549b1f3a9 100644 > --- a/hw/arm/aspeed.c > +++ b/hw/arm/aspeed.c > @@ -259,7 +259,7 @@ static void aspeed_board_init(MachineState *machine= , > cfg->i2c_init(bmc); > } > =20 > - for (i =3D 0; i < ARRAY_SIZE(bmc->soc.sdhci.slots); i++) { > + for (i =3D 0; i < bmc->soc.sdhci.num_slots; i++) { > SDHCIState *sdhci =3D &bmc->soc.sdhci.slots[i]; > DriveInfo *dinfo =3D drive_get_next(IF_SD); > BlockBackend *blk; > diff --git a/hw/arm/aspeed_ast2600.c b/hw/arm/aspeed_ast2600.c > index 931887ac681f..931ee5aae183 100644 > --- a/hw/arm/aspeed_ast2600.c > +++ b/hw/arm/aspeed_ast2600.c > @@ -208,6 +208,8 @@ static void aspeed_soc_ast2600_init(Object *obj) > sysbus_init_child_obj(obj, "sdc", OBJECT(&s->sdhci), sizeof(s->sdh= ci), > TYPE_ASPEED_SDHCI); > =20 > + object_property_set_int(OBJECT(&s->sdhci), 2, "num-slots", &error_= abort); OK. This defines 2 SDHCI slots for the ast2600 SoC, but > + > /* Init sd card slot class here so that they're under the correct = parent */ > for (i =3D 0; i < ASPEED_SDHCI_NUM_SLOTS; ++i) { > sysbus_init_child_obj(obj, "sdhci[*]", OBJECT(&s->sdhci.slots[= i]), > diff --git a/hw/arm/aspeed_soc.c b/hw/arm/aspeed_soc.c > index f4fe243458fd..3498f55603f2 100644 > --- a/hw/arm/aspeed_soc.c > +++ b/hw/arm/aspeed_soc.c > @@ -215,6 +215,9 @@ static void aspeed_soc_init(Object *obj) > sysbus_init_child_obj(obj, "sdc", OBJECT(&s->sdhci), sizeof(s->sdh= ci), > TYPE_ASPEED_SDHCI); > =20 > + object_property_set_int(OBJECT(&s->sdhci), ASPEED_SDHCI_NUM_SLOTS, > + "num-slots", &error_abort); why use ASPEED_SDHCI_NUM_SLOTS here ? C. > /* Init sd card slot class here so that they're under the correct = parent */ > for (i =3D 0; i < ASPEED_SDHCI_NUM_SLOTS; ++i) { > sysbus_init_child_obj(obj, "sdhci[*]", OBJECT(&s->sdhci.slots[= i]), > diff --git a/hw/sd/aspeed_sdhci.c b/hw/sd/aspeed_sdhci.c > index cff3eb7dd21e..939d1510dedb 100644 > --- a/hw/sd/aspeed_sdhci.c > +++ b/hw/sd/aspeed_sdhci.c > @@ -13,6 +13,7 @@ > #include "qapi/error.h" > #include "hw/irq.h" > #include "migration/vmstate.h" > +#include "hw/qdev-properties.h" > =20 > #define ASPEED_SDHCI_INFO 0x00 > #define ASPEED_SDHCI_INFO_RESET 0x00030000 > @@ -120,14 +121,14 @@ static void aspeed_sdhci_realize(DeviceState *dev= , Error **errp) > =20 > /* Create input irqs for the slots */ > qdev_init_gpio_in_named_with_opaque(DEVICE(sbd), aspeed_sdhci_set_= irq, > - sdhci, NULL, ASPEED_SDHCI_NUM_= SLOTS); > + sdhci, NULL, sdhci->num_slots)= ; > =20 > sysbus_init_irq(sbd, &sdhci->irq); > memory_region_init_io(&sdhci->iomem, OBJECT(sdhci), &aspeed_sdhci_= ops, > sdhci, TYPE_ASPEED_SDHCI, 0x1000); > sysbus_init_mmio(sbd, &sdhci->iomem); > =20 > - for (int i =3D 0; i < ASPEED_SDHCI_NUM_SLOTS; ++i) { > + for (int i =3D 0; i < sdhci->num_slots; ++i) { > Object *sdhci_slot =3D OBJECT(&sdhci->slots[i]); > SysBusDevice *sbd_slot =3D SYS_BUS_DEVICE(&sdhci->slots[i]); > =20 > @@ -174,6 +175,11 @@ static const VMStateDescription vmstate_aspeed_sdh= ci =3D { > }, > }; > =20 > +static Property aspeed_sdhci_properties[] =3D { > + DEFINE_PROP_UINT8("num-slots", AspeedSDHCIState, num_slots, 0), > + DEFINE_PROP_END_OF_LIST(), > +}; > + > static void aspeed_sdhci_class_init(ObjectClass *classp, void *data) > { > DeviceClass *dc =3D DEVICE_CLASS(classp); > @@ -181,6 +187,7 @@ static void aspeed_sdhci_class_init(ObjectClass *cl= assp, void *data) > dc->realize =3D aspeed_sdhci_realize; > dc->reset =3D aspeed_sdhci_reset; > dc->vmsd =3D &vmstate_aspeed_sdhci; > + dc->props =3D aspeed_sdhci_properties; > } > =20 > static TypeInfo aspeed_sdhci_info =3D { > diff --git a/include/hw/sd/aspeed_sdhci.h b/include/hw/sd/aspeed_sdhci.= h > index dfdab4379021..dffbb46946b9 100644 > --- a/include/hw/sd/aspeed_sdhci.h > +++ b/include/hw/sd/aspeed_sdhci.h > @@ -24,6 +24,7 @@ typedef struct AspeedSDHCIState { > SysBusDevice parent; > =20 > SDHCIState slots[ASPEED_SDHCI_NUM_SLOTS]; > + uint8_t num_slots; > =20 > MemoryRegion iomem; > qemu_irq irq; >=20 From MAILER-DAEMON Tue Dec 10 03:59:42 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1iebMs-0007FK-FC for mharc-qemu-arm@gnu.org; Tue, 10 Dec 2019 03:59:42 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:58004) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iebMp-0007EX-2i for qemu-arm@nongnu.org; Tue, 10 Dec 2019 03:59:40 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1iebMl-0007W3-Sh for qemu-arm@nongnu.org; Tue, 10 Dec 2019 03:59:37 -0500 Received: from us-smtp-delivery-1.mimecast.com ([207.211.31.120]:45469 helo=us-smtp-1.mimecast.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1iebMl-0007Vi-Dm for qemu-arm@nongnu.org; Tue, 10 Dec 2019 03:59:35 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; 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[88.21.103.182]) by smtp.gmail.com with ESMTPSA id x132sm2493956wmg.0.2019.12.10.00.59.30 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 10 Dec 2019 00:59:30 -0800 (PST) Subject: Re: [PATCH 02/10] hw: arm: add Xunlong Orange Pi PC machine To: Niek Linnenbank Cc: QEMU Developers , Beniamino Galvani , Peter Maydell , qemu-arm References: <20191202210947.3603-1-nieklinnenbank@gmail.com> <20191202210947.3603-3-nieklinnenbank@gmail.com> From: =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= Message-ID: Date: Tue, 10 Dec 2019 09:59:29 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.2.2 MIME-Version: 1.0 In-Reply-To: Content-Language: en-US X-MC-Unique: iz0lhgmJMv69QeN91uZEdQ-1 X-Mimecast-Spam-Score: 0 Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 207.211.31.120 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 10 Dec 2019 08:59:40 -0000 On 12/6/19 11:15 PM, Niek Linnenbank wrote: [...] > >=C2=A0 =C2=A0 =C2=A0 > +static void orangepi_machine_init(MachineCl= ass *mc) > >=C2=A0 =C2=A0 =C2=A0 > +{ > >=C2=A0 =C2=A0 =C2=A0 > +=C2=A0 =C2=A0 mc->desc =3D "Orange Pi PC"; > >=C2=A0 =C2=A0 =C2=A0 > +=C2=A0 =C2=A0 mc->init =3D orangepi_init; > >=C2=A0 =C2=A0 =C2=A0 > +=C2=A0 =C2=A0 mc->units_per_default_bus =3D= 1; > >=C2=A0 =C2=A0 =C2=A0 > +=C2=A0 =C2=A0 mc->min_cpus =3D AW_H3_NUM_CP= US; > >=C2=A0 =C2=A0 =C2=A0 > +=C2=A0 =C2=A0 mc->max_cpus =3D AW_H3_NUM_CP= US; > >=C2=A0 =C2=A0 =C2=A0 > +=C2=A0 =C2=A0 mc->default_cpus =3D AW_H3_NU= M_CPUS; > > > >=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 mc->default_cpu_ty= pe =3D ARM_CPU_TYPE_NAME("cortex-a7"); > > > >=C2=A0 =C2=A0 =C2=A0 > +=C2=A0 =C2=A0 mc->ignore_memory_transaction= _failures =3D true; > > > >=C2=A0 =C2=A0 =C2=A0You should not use this flag in new design. See= the > documentation in > >=C2=A0 =C2=A0 =C2=A0include/hw/boards.h: > > > >=C2=A0 =C2=A0 =C2=A0 =C2=A0 * @ignore_memory_transaction_failures: > >=C2=A0 =C2=A0 =C2=A0 =C2=A0 *=C2=A0 =C2=A0 [...] New board models > >=C2=A0 =C2=A0 =C2=A0 =C2=A0 *=C2=A0 =C2=A0 should instead use "unim= plemented-device" for all memory > >=C2=A0 =C2=A0 =C2=A0ranges where > >=C2=A0 =C2=A0 =C2=A0 =C2=A0 *=C2=A0 =C2=A0 the guest will attempt t= o probe for a device that > QEMU doesn't > >=C2=A0 =C2=A0 =C2=A0 =C2=A0 *=C2=A0 =C2=A0 implement and a stub dev= ice is required. > > > >=C2=A0 =C2=A0 =C2=A0You already use the "unimplemented-device". > > > > Thanks, I'm working on this now. I think that at least I'll need > to add > > all of the devices mentioned in the 4.1 Memory Mapping chapter of > the > > datasheet > > as an unimplemented device. Previously I only added some that I > thought > > were relevant. > > > > I added all the missing devices as unimplemented and removed the > > ignore_memory_transaction_failures flag >=20 > I was going to say, "instead of adding *all* the devices regions you > can > add the likely bus decoding regions", probably: >=20 > 0x01c0.0000=C2=A0 =C2=A0128KiB=C2=A0 =C2=A0AMBA AXI > 0x01c2.0000=C2=A0 =C2=A064KiB=C2=A0 =C2=A0 AMBA APB >=20 > But too late. >=20 >=20 > Hehe its okey, I can change it to whichever is preferable: the minimum se= t > with unimplemented device entries to get a working linux kernel / u-boot = or > just cover the full memory space from the datasheet. My initial thought= =20 > was that if > we only provide the minimum set, and the linux kernel later adds a new=20 > driver for a device > which is not marked unimplemented, it will trigger the data abort and=20 > potentially resulting in a non-booting kernel. >=20 > But I'm not sure what is normally done here. I do see other board files= =20 > using the create_unimplemented_device() function, > but I dont know if they are covering the whole memory space or not. If they don't cover all memory regions, the guest code can trigger a=20 data abort indeed. Since we don't know the memory layout of old board,=20 they are still supported with ignore_memory_transaction_failures=3Dtrue,=20 so guest still run unaffected. We expect new boards to implement the minimum layout. As long as your guest is happy and usable, UNIMP devices are fine,=20 either as big region or individual device (this requires someone with=20 access to the datasheet to verify). If you can add a UNIMP for each=20 device - which is what you did - it is even better because the the unimp=20 access log will be more useful, having finer granularity. > I added all the missing devices as unimplemented and removed the > ignore_memory_transaction_failures flag IOW, you already did the best you could do :) > > from the machine. Now it seems Linux gets a data abort while > probing the > > uart1 serial device at 0x01c28400, >=20 > Did you add the UART1 as UNIMP or 16550? >=20 >=20 > I discovered what goes wrong here. See this kernel oops message: >=20 > [ 1.084985] [f08600f8] *pgd=3D6f00a811, *pte=3D01c28653, *ppte=3D01c28= 453 > [ 1.085564] Internal error: : 8 [#1] SMP ARM > [ 1.085698] Modules linked in: > [ 1.085940] CPU: 0 PID: 1 Comm: swapper/0 Not tainted 5.4.0-11747-g2f1= 3437b8917 #4 > [ 1.085968] Hardware name: Allwinner sun8i Family > [ 1.086447] PC is at dw8250_setup_port+0x10/0x10c > [ 1.086478] LR is at dw8250_probe+0x500/0x56c >=20 > It tries to access the UART0 at base address 0x01c28400, which I did=20 > provide. The strange > thing is that is accesses offset 0xf8, thus address 0x01c284f8. The=20 > datasheet does not mention this register > but if we provide the 1KiB (0x400) I/O space it should at least read as= =20 > zero and writes ignored. Unfortunately the emulated > serial driver only maps a small portion until 0x1f: >=20 > (qemu) info mtree > ... > 0000000001c28000-0000000001c2801f (prio 0, i/o): serial > 0000000001c28400-0000000001c2841f (prio 0, i/o): serial > 0000000001c28800-0000000001c2881f (prio 0, i/o): serial >=20 >=20 > Apparently, the register that the mainline linux kernel is using is=20 > DesignWare specific: >=20 > drivers/tty/serial/8250/8250_dwlib.c:13: >=20 > /* Offsets for the DesignWare specific registers */ > #define DW_UART_DLF<--->0xc0 /* Divisor Latch Fraction Register */ > #define DW_UART_CPR<--->0xf4 /* Component Parameter Register */ > #define DW_UART_UCV<--->0xf8 /* UART Component Version */ >=20 > I tried to find a way to increase the memory mapped size of the serial=20 > device I created with serial_mm_init(), > but I don't think its possible with that interface. >=20 > I did manage to get it working by overlaying the UART0 with another=20 > unimplemented device > that does have an I/O size of 0x400, but I guess that is probably not=20 > the solution we are looking for? IMHO this is the correct solution :) Memory regions have priority. By default a device has priority 0, and=20 UNIMP device has priority -1000. So you can use: serial_mm_init(get_system_memory(), AW_H3_UART0_REG_BASE, 2, s->irq[AW_H3_GIC_SPI_UART0], 115200, serial_hd(0), DEVICE_NATIVE_ENDIAN); create_unimplemented_device("DesignWare-uart",\ AW_H3_UART0_REG_BASE, 0x400); (Or cleaner, add a create_designware_uart(...) function that does both). (qemu) info mtree ... 0000000001c28000-0000000001c2801f (prio 0, i/o): serial 0000000001c28000-0000000001c283ff (prio -1000, i/o): DesignWare-uart You could create an UNIMP region of 0x400 - 0x20 =3D 0x3e0, but that would= =20 appear this is a different device, so I don't recommend that. > I wonder, did any of the other SoC / boards have this problem when > removing mc->ignore_memory_transaction_failures? From MAILER-DAEMON Tue Dec 10 04:02:52 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1iebPw-00008i-4X for mharc-qemu-arm@gnu.org; Tue, 10 Dec 2019 04:02:52 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:58366) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iebPt-00008Z-Kz for qemu-arm@nongnu.org; Tue, 10 Dec 2019 04:02:50 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1iebPs-0000Db-JJ for qemu-arm@nongnu.org; Tue, 10 Dec 2019 04:02:49 -0500 Received: from us-smtp-1.mimecast.com ([205.139.110.61]:56995 helo=us-smtp-delivery-1.mimecast.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1iebPs-0000DS-Fu for qemu-arm@nongnu.org; Tue, 10 Dec 2019 04:02:48 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1575968568; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=vSMkijIZic98gZLxBN70ZWl3l2+XsDo4BdCYlb0skis=; b=XP2uL84AqS9+RocFyIY6qSrbz8o27/nnb8ry/xrnRWqaKutANnBw3gxJa0Zs9zCM5rpvP2 0uqRfRTfGeWzxfIWEN7XcY3Gik5xbEbfa6cpPBnGku1l3kbLFKQ+eygoLgU5eIECCNuCh0 J43V8sM3D7TlC1SyqRZUxjQYKwyHhb4= Received: from mail-lj1-f200.google.com (mail-lj1-f200.google.com [209.85.208.200]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-422-GimWqIpyNw6YrSskq3edFA-1; Tue, 10 Dec 2019 04:02:46 -0500 Received: by mail-lj1-f200.google.com with SMTP id t11so1707771ljo.13 for ; Tue, 10 Dec 2019 01:02:46 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:subject:to:cc:references:from:message-id:date :user-agent:mime-version:in-reply-to:content-language :content-transfer-encoding; bh=vSMkijIZic98gZLxBN70ZWl3l2+XsDo4BdCYlb0skis=; b=KE++Jq+ChKc+mltXmhNy6YsFClryowJtz/4CS92jyFqVlCS5VGzPc7f/It/W4dARtV avZXLMHeBx5EFhuG2FiRzNC3qnPEMBoozkq7OdpcrRkZLH4NtqzpMshe33znpMXt1/ir 4tclWfhiKmUBXN3VJCQppa0SMa2dZXIO8UjPl40ElsDdf4HR3YzJj8/tr3VPNGKA6mGx qPK3wcihjE/KEgYsXMYvJizY3RWC31aLTIC9PUnWA5BuTG7MIb7JvsY1mZoqSev1g4Ry v81ozfus+yjs1HkdrWaKOSNH19yGU1nlY1T+zAybMqnawyp7tDXVI3JDGVvQnam3Qb3y uH+g== X-Gm-Message-State: APjAAAXq/DXqjtTxOWGnCBKPEftbh4IYcH6lv2S3oyauAvxD5GUuZesL 1fE4VD3T4ikAjm0HWrEAGwoQ7ER1ZW5EUYpyF9OrwbLqgEml30UCVvF6DWDWMl6G2KtSIeNC2Ey IiLKIhPq/Gixb X-Received: by 2002:adf:fa0b:: with SMTP id m11mr1888468wrr.98.1575968563720; Tue, 10 Dec 2019 01:02:43 -0800 (PST) X-Google-Smtp-Source: APXvYqzE2I8PzvNqy9PeTYyk0iy6OBtzfR1eCTN6H6e5NpMzsvYKJOQxBRaTWMsK8p5t4henQt7EGQ== X-Received: by 2002:adf:fa0b:: with SMTP id m11mr1888444wrr.98.1575968563501; Tue, 10 Dec 2019 01:02:43 -0800 (PST) Received: from [192.168.1.35] (182.red-88-21-103.staticip.rima-tde.net. [88.21.103.182]) by smtp.gmail.com with ESMTPSA id g2sm2477083wrw.76.2019.12.10.01.02.42 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 10 Dec 2019 01:02:43 -0800 (PST) Subject: Re: [PATCH 01/10] hw: arm: add Allwinner H3 System-on-Chip To: Niek Linnenbank , qemu-devel@nongnu.org Cc: b.galvani@gmail.com, peter.maydell@linaro.org, qemu-arm@nongnu.org References: <20191202210947.3603-1-nieklinnenbank@gmail.com> <20191202210947.3603-2-nieklinnenbank@gmail.com> From: =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= Message-ID: <70e9d4e8-49fb-02f9-23b4-d7cbf6e55eac@redhat.com> Date: Tue, 10 Dec 2019 10:02:41 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.2.2 MIME-Version: 1.0 In-Reply-To: <20191202210947.3603-2-nieklinnenbank@gmail.com> Content-Language: en-US X-MC-Unique: GimWqIpyNw6YrSskq3edFA-1 X-Mimecast-Spam-Score: 0 Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 205.139.110.61 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 10 Dec 2019 09:02:50 -0000 On 12/2/19 10:09 PM, Niek Linnenbank wrote: > The Allwinner H3 is a System on Chip containing four ARM Cortex A7 > processor cores. Features and specifications include DDR2/DDR3 memory, > SD/MMC storage cards, 10/100/1000Mbit ethernet, USB 2.0, HDMI and > various I/O modules. This commit adds support for the Allwinner H3 > System on Chip. > > Signed-off-by: Niek Linnenbank > --- [...] > + > + /* UART */ > + if (serial_hd(0)) { As the uart0 is always mapped in the SoC, don't use 'if serial_hd()', instead map it regardless a console is connected. > + serial_mm_init(get_system_memory(), AW_H3_UART0_REG_BASE, 2, > + s->irq[AW_H3_GIC_SPI_UART0], 115200, serial_hd(0), > + DEVICE_NATIVE_ENDIAN); > + } > + > + /* Unimplemented devices */ > + create_unimplemented_device("display-engine", AW_H3_DE_BASE, AW_H3_DE_SIZE); > + create_unimplemented_device("dma", AW_H3_DMA_BASE, AW_H3_DMA_SIZE); > + create_unimplemented_device("lcd0", AW_H3_LCD0_BASE, AW_H3_LCD0_SIZE); > + create_unimplemented_device("lcd1", AW_H3_LCD1_BASE, AW_H3_LCD1_SIZE); > + create_unimplemented_device("gpu", AW_H3_GPU_BASE, AW_H3_GPU_SIZE); > + create_unimplemented_device("hdmi", AW_H3_HDMI_BASE, AW_H3_HDMI_SIZE); > + create_unimplemented_device("rtc", AW_H3_RTC_BASE, AW_H3_RTC_SIZE); > + create_unimplemented_device("audio-codec", AW_H3_AC_BASE, AW_H3_AC_SIZE); From MAILER-DAEMON Tue Dec 10 04:51:54 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1iecBO-0006vK-OS for mharc-qemu-arm@gnu.org; Tue, 10 Dec 2019 04:51:54 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:35946) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iecBM-0006v6-Ai for qemu-arm@nongnu.org; Tue, 10 Dec 2019 04:51:53 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1iecBK-0007Oo-0p for qemu-arm@nongnu.org; Tue, 10 Dec 2019 04:51:51 -0500 Received: from us-smtp-2.mimecast.com ([207.211.31.81]:25919 helo=us-smtp-delivery-1.mimecast.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1iecBJ-0007Oi-U3 for qemu-arm@nongnu.org; Tue, 10 Dec 2019 04:51:49 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1575971509; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=1J4KRTPTQfJmDBAoGFDnI8xY6ixnsml6F3fxdBMK8HA=; b=Ed7snXiDn6BE9f9myQXw8w0lubOwyoRepPZNIWOWF+S/f/AQLwyyXb49AQVIC7gjIpcSut OFGuNFgwWE8Tob09btt/KeU800jwHczaJc3TxkbiHWIyPaxAJTdfFiRuklQyvt9iRoX5p0 +Mo2RIBygrqTzwxqoAclbMN+zrfJxEo= Received: from mimecast-mx01.redhat.com (mimecast-mx01.redhat.com [209.132.183.4]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-129-PIEVm6txMBOzTznv_OPOCA-1; Tue, 10 Dec 2019 04:51:45 -0500 Received: from smtp.corp.redhat.com (int-mx05.intmail.prod.int.phx2.redhat.com [10.5.11.15]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx01.redhat.com (Postfix) with ESMTPS id 6175F107ACC7; Tue, 10 Dec 2019 09:51:44 +0000 (UTC) Received: from ovpn-205-69.brq.redhat.com (ovpn-205-69.brq.redhat.com [10.40.205.69]) by smtp.corp.redhat.com (Postfix) with ESMTPS id 934715D72C; Tue, 10 Dec 2019 09:51:41 +0000 (UTC) Message-ID: <596d07e933cb4da48dbba5b492e81a2438e78a2f.camel@redhat.com> Subject: Re: [PATCH v1 0/5] target/arm/kvm: Provide an option to adjust virtual time From: Andrea Bolognani To: Andrew Jones , Peter Maydell Cc: Marc Zyngier , qemu-arm , Richard Henderson , QEMU Developers , bijan.mottahedeh@oracle.com Date: Tue, 10 Dec 2019 10:51:38 +0100 In-Reply-To: <20191206155327.7adiyjjkjh56mg2t@kamzik.brq.redhat.com> References: <20191016143410.5023-1-drjones@redhat.com> <20191206155327.7adiyjjkjh56mg2t@kamzik.brq.redhat.com> User-Agent: Evolution 3.34.2 (3.34.2-1.fc31) MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.79 on 10.5.11.15 X-MC-Unique: PIEVm6txMBOzTznv_OPOCA-1 X-Mimecast-Spam-Score: 0 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: 7bit X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 207.211.31.81 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 10 Dec 2019 09:51:53 -0000 On Fri, 2019-12-06 at 16:53 +0100, Andrew Jones wrote: > On Fri, Dec 06, 2019 at 03:22:58PM +0000, Peter Maydell wrote: > > On Wed, 16 Oct 2019 at 15:34, Andrew Jones wrote: > > > This series is inspired by a series[1] posted by Bijan Mottahedeh about > > > a year ago. The problem described in the cover letter of [1] is easily > > > reproducible and some users would like to have the option to avoid it. > > > However the solution, which is to adjust the virtual counter offset each > > > time the VM transitions to the running state, introduces a different > > > problem, which is that the virtual and physical counters diverge. As > > > described in the cover letter of [1] this divergence is easily observed > > > when comparing the output of `date` and `hwclock` after suspending the > > > guest, waiting a while, and then resuming it. Because this different > > > problem may actually be worse for some users, unlike [1], the series > > > posted here makes the virtual counter offset adjustment optional and not > > > even enabled by default. Besides the adjustment being optional, this > > > series approaches the needed changes differently to apply them in more > > > appropriate locations. Finally, unlike [1], this series doesn't attempt > > > to measure "pause time" itself. Simply using QEMU_CLOCK_VIRTUAL, which > > > only ticks when the VM is not stopped, is sufficient. > > > > So I guess my overall question is "what is the x86 solution to > > this problem, and why is this all arm-specific?" It would also > > x86 adjusts the counter offset by default, and I don't think there's any > way to turn that behavior off. I think it's too late to follow that > default for arm, but this series provides a way to opt into the same > behavior. My understanding is that turning kvm-adjvtime either on or off results in a different set of advantages and drawbacks, with neither begin a one-size-fits-all solution. So it's good that we offer a way for the user to pick one or the other based on their specific needs. The main difference is that kvm-adjvtime=on matches x86's behavior, which is fairly well understood and thoroughly documented, along with the corresponding workarounds, dos and don'ts. With that in mind, in my opinion it would make sense to make kvm-adjvtime=on the behavior for newer machine types so that people coming from an x86 background and/or having to manage both at the same time will get a consistent experience and will be able to draw, even for aarch64, on the considerable amount of existing x86-centric literature on the subject. -- Andrea Bolognani / Red Hat / Virtualization From MAILER-DAEMON Tue Dec 10 05:13:42 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1iecWU-0004sY-LP for mharc-qemu-arm@gnu.org; Tue, 10 Dec 2019 05:13:42 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:38293) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iecWR-0004rW-NW for qemu-arm@nongnu.org; Tue, 10 Dec 2019 05:13:40 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1iecWQ-0007gD-JH for qemu-arm@nongnu.org; Tue, 10 Dec 2019 05:13:39 -0500 Received: from us-smtp-1.mimecast.com ([205.139.110.61]:46729 helo=us-smtp-delivery-1.mimecast.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1iecWQ-0007ft-FH for qemu-arm@nongnu.org; Tue, 10 Dec 2019 05:13:38 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1575972818; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=3wCO3GuM2moFcAks0xXtIp9Oxy/EmVQGKpZZV5ENJBE=; b=YTwJLSAdcbADMtYbi5ZrlRnn2VvuDELoP7YoYUwkfF1LZ288LTOSIHNuEDZmyQpaNNBOpq CB4W1nEB3rwaARCwMMudJ8bpOPLzegikTyEk7SA1/MtsdYMbYarc2rQ7zD8hmaWm3enTea 3aZg3UeXxQWS+fw5A1qW+lBm2liR2nc= Received: from mimecast-mx01.redhat.com (mimecast-mx01.redhat.com [209.132.183.4]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-398-Sv9F--SmMlq1LqAvEJt_rA-1; Tue, 10 Dec 2019 05:13:34 -0500 Received: from smtp.corp.redhat.com (int-mx01.intmail.prod.int.phx2.redhat.com [10.5.11.11]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx01.redhat.com (Postfix) with ESMTPS id 62D31107ACC4; Tue, 10 Dec 2019 10:13:33 +0000 (UTC) Received: from kamzik.brq.redhat.com (unknown [10.43.2.160]) by smtp.corp.redhat.com (Postfix) with ESMTPS id 5004760561; Tue, 10 Dec 2019 10:13:26 +0000 (UTC) Date: Tue, 10 Dec 2019 11:13:23 +0100 From: Andrew Jones To: "Zengtao (B)" Cc: "qemu-devel@nongnu.org" , "qemu-arm@nongnu.org" , "wei@redhat.com" , "peter.maydell@linaro.org" , "eric.auger@redhat.com" , "imammedo@redhat.com" , "xuwei (O)" , huangdaode Subject: Re: [Qemu-devel] [RFC PATCH 0/6] hw/arm/virt: Introduce cpu topology support Message-ID: <20191210101323.q7dn2f3pkx3ya5s4@kamzik.brq.redhat.com> References: <20180704124923.32483-1-drjones@redhat.com> <678F3D1BB717D949B966B68EAEB446ED3405A26F@dggemm526-mbx.china.huawei.com> MIME-Version: 1.0 In-Reply-To: <678F3D1BB717D949B966B68EAEB446ED3405A26F@dggemm526-mbx.china.huawei.com> X-Scanned-By: MIMEDefang 2.79 on 10.5.11.11 X-MC-Unique: Sv9F--SmMlq1LqAvEJt_rA-1 X-Mimecast-Spam-Score: 0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: quoted-printable Content-Disposition: inline X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 205.139.110.61 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 10 Dec 2019 10:13:41 -0000 On Mon, Dec 09, 2019 at 02:14:09AM +0000, Zengtao (B) wrote: > Hi Andrew: >=20 > Any update for this patch series? I have met the same issue, and if the= =20 > topology guessed by linux MPIDR conflicts with qemu specified numa, it > will failed to boot (sched domain initialization will fall into deadloop)= . Hi Zeng, This has been on my TODO list a long time, but it keeps getting preempted. We need to start by giving userspace control over the MPIDRs, including when KVM is in use. The earliest I can return to this will be mid/late January. If you'd like to jump in on it now, then feel free. Thanks, drew >=20 > Thanks. >=20 > > -----Original Message----- > > From: Qemu-devel > > [mailto:qemu-devel-bounces+incoming=3Dpatchwork.ozlabs.org@nongnu.or > > g] On Behalf Of Andrew Jones > > Sent: Thursday, July 05, 2018 4:49 AM > > To: qemu-devel@nongnu.org; qemu-arm@nongnu.org > > Cc: wei@redhat.com; peter.maydell@linaro.org; eric.auger@redhat.com; > > imammedo@redhat.com > > Subject: [Qemu-devel] [RFC PATCH 0/6] hw/arm/virt: Introduce cpu > > topology support > >=20 > > This series provides support for booting mach-virt machines with > > non-flat cpu topology, i.e. enabling the extended options of the > > '-smp' command line parameter (sockets,cores,threads). Both DT and > > ACPI description generators are added. We only apply the new feature > > to 3.1 and later machine types, as the change is guest visible, even > > when no command line change is made. This is because the basic > > '-smp ' parameter makes the assumption that refers to the > > number of sockets, but when no topology description is provided, > > Linux will use the MPIDR to guess. Neither the MPIDR exposed to > > the guest when running with KVM nor TCG currently provides socket > > information, leaving Linux to assume all processing elements are > > cores in the same socket. For example, before this series '-smp 4' > > would show up in the guest as > >=20 > > CPU(s): 4 > > On-line CPU(s) list: 0-3 > > Thread(s) per core: 1 > > Core(s) per socket: 4 > > Socket(s): 1 > >=20 > > and after it shows up as > >=20 > > CPU(s): 4 > > On-line CPU(s) list: 0-3 > > Thread(s) per core: 1 > > Core(s) per socket: 1 > > Socket(s): 4 > >=20 > > It's not expected that this should be a problem, but it's worth > > considering. The only way to avoid the silent change is for QEMU to > > provide boards a way to override the default '-smp' parsing function. > > Otherwise, if a user wants to avoid a guest visible change, but still > > use a 3.1 or later mach-virt machine type, then they must ensure the > > command line specifies a single socket, e.g. '-smp sockets=3D1,cores=3D= 4' > >=20 > > Thanks, > > drew > >=20 > >=20 > > Andrew Jones (6): > > hw/arm/virt: Add virt-3.1 machine type > > device_tree: add qemu_fdt_add_path > > hw/arm/virt: DT: add cpu-map > > hw/arm/virt-acpi-build: distinguish possible and present cpus > > virt-acpi-build: add PPTT table > > hw/arm/virt: cpu topology: don't allow threads > >=20 > > device_tree.c | 24 +++++++++++++ > > hw/acpi/aml-build.c | 50 ++++++++++++++++++++++++++ > > hw/arm/virt-acpi-build.c | 25 ++++++++++--- > > hw/arm/virt.c | 69 > > +++++++++++++++++++++++++++++++++--- > > include/hw/acpi/aml-build.h | 2 ++ > > include/hw/arm/virt.h | 1 + > > include/sysemu/device_tree.h | 1 + > > 7 files changed, 162 insertions(+), 10 deletions(-) From MAILER-DAEMON Tue Dec 10 05:29:38 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1ieclu-0000hB-Gx for mharc-qemu-arm@gnu.org; Tue, 10 Dec 2019 05:29:38 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:40297) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iecls-0000go-5a for qemu-arm@nongnu.org; Tue, 10 Dec 2019 05:29:37 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ieclr-0005qS-1U for qemu-arm@nongnu.org; Tue, 10 Dec 2019 05:29:36 -0500 Received: from mail-oi1-x244.google.com ([2607:f8b0:4864:20::244]:37045) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ieclq-0005q9-Rv for qemu-arm@nongnu.org; Tue, 10 Dec 2019 05:29:34 -0500 Received: by mail-oi1-x244.google.com with SMTP id x195so9339170oix.4 for ; Tue, 10 Dec 2019 02:29:34 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=ti24g5Ml8cfyB8YPNcyhO9AecXFyWAWKkXXMl7FXl00=; b=wjwluSQ1qNM2r8wY1O0DiAsyN6DHzdrop036iklOQCL7dzWdo29Cj8x1Ol/AtaHO5/ +9kRzICtxLb+WThzB/a65Sk6undmRl5SSUI+DbnhdwVvhtzDmikD+DKi72BaXdgLF0ge D2D5j5bB1wHy9IeXZ9IGPYZh8A+BGQlE/9LMIATDsHXTA1wNiLevnalEOoW9LKbTGwF3 kEIHx/vH1mDTMaRaCK9ZF4yB49D2t/8J+39O9CrhgIaNgzcWe4RZqBvrugCBq3ADCzT1 ydCdq156Nql2O7q0wriHO2zpNXbZt7nPSUKJoihE5Hj33YLDgPypt+LlBWfx0ryokIXC dV2A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=ti24g5Ml8cfyB8YPNcyhO9AecXFyWAWKkXXMl7FXl00=; b=shv1QGG/tltRc7E4zG3e2jHHjzjNdAe/aJ4zkmZnOxfBwWP605zpMndM29Z8CSGTqS Rp+KkHZs+SZQLAneZTmfR5ZIg3efdEjZHRwPhgF/IA0SHcskeiJTPEWSXb3bHvl5aBy7 sZSUiQn6siqKCbkYaSHXKRrpAkX0FGioSyXHWtTnzYZxp7vGlAcT/mAfbRzwL68TPHUP gYsa+GC8z3S0IEsDXvtUJdBpW4v1tGOuRiRLbmy7xgHDoW8rmqkIeX6kPiN9DBle6yIj Bjxd50Q6rJyMejuCSZ8QqaMg72cBhxvoNCc8bPRcMzTU7cUH9R22Q9mIasiSCAA8EJzi GlSg== X-Gm-Message-State: APjAAAV5TCzIuaqDm/A/emg4d96Az+M45LmtoAMI93qrrABMd6dKxvfk odiUAHeuv2d3M06jf0qY6C0awZR4YtjYHgmN++KRdw== X-Google-Smtp-Source: APXvYqx4rTi+YVEJMvNpW3CY+zwgfAxZ7qsdv3+IMUaFdB7N0TsvxXWY3Pp0jrCrXoe0fmpiKY5zTgzFtaO3RH+TTk0= X-Received: by 2002:a05:6808:996:: with SMTP id a22mr3143457oic.146.1575973773941; Tue, 10 Dec 2019 02:29:33 -0800 (PST) MIME-Version: 1.0 References: <20191016143410.5023-1-drjones@redhat.com> <20191206155327.7adiyjjkjh56mg2t@kamzik.brq.redhat.com> <596d07e933cb4da48dbba5b492e81a2438e78a2f.camel@redhat.com> In-Reply-To: <596d07e933cb4da48dbba5b492e81a2438e78a2f.camel@redhat.com> From: Peter Maydell Date: Tue, 10 Dec 2019 10:29:22 +0000 Message-ID: Subject: Re: [PATCH v1 0/5] target/arm/kvm: Provide an option to adjust virtual time To: Andrea Bolognani Cc: Andrew Jones , Marc Zyngier , qemu-arm , Richard Henderson , QEMU Developers , bijan.mottahedeh@oracle.com Content-Type: text/plain; charset="UTF-8" X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::244 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 10 Dec 2019 10:29:37 -0000 On Tue, 10 Dec 2019 at 09:51, Andrea Bolognani wrote: > > On Fri, 2019-12-06 at 16:53 +0100, Andrew Jones wrote: > > On Fri, Dec 06, 2019 at 03:22:58PM +0000, Peter Maydell wrote: > > > On Wed, 16 Oct 2019 at 15:34, Andrew Jones wrote: > > > > This series is inspired by a series[1] posted by Bijan Mottahedeh about > > > > a year ago. The problem described in the cover letter of [1] is easily > > > > reproducible and some users would like to have the option to avoid it. > > > > However the solution, which is to adjust the virtual counter offset each > > > > time the VM transitions to the running state, introduces a different > > > > problem, which is that the virtual and physical counters diverge. As > > > > described in the cover letter of [1] this divergence is easily observed > > > > when comparing the output of `date` and `hwclock` after suspending the > > > > guest, waiting a while, and then resuming it. Because this different > > > > problem may actually be worse for some users, unlike [1], the series > > > > posted here makes the virtual counter offset adjustment optional and not > > > > even enabled by default. Besides the adjustment being optional, this > > > > series approaches the needed changes differently to apply them in more > > > > appropriate locations. Finally, unlike [1], this series doesn't attempt > > > > to measure "pause time" itself. Simply using QEMU_CLOCK_VIRTUAL, which > > > > only ticks when the VM is not stopped, is sufficient. > > > > > > So I guess my overall question is "what is the x86 solution to > > > this problem, and why is this all arm-specific?" It would also > > > > x86 adjusts the counter offset by default, and I don't think there's any > > way to turn that behavior off. I think it's too late to follow that > > default for arm, but this series provides a way to opt into the same > > behavior. > > My understanding is that turning kvm-adjvtime either on or off > results in a different set of advantages and drawbacks, with neither > begin a one-size-fits-all solution. So it's good that we offer a way > for the user to pick one or the other based on their specific needs. If this is the case, shouldn't we be looking at having the option exist for all architectures, not just arm? Obviously pre-existing behaviour would imply having the default have to differ for some archs/machines. thanks -- PMM From MAILER-DAEMON Tue Dec 10 05:35:12 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1iecrH-0002UD-SA for mharc-qemu-arm@gnu.org; Tue, 10 Dec 2019 05:35:11 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:41009) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iecrE-0002RD-Nl for qemu-arm@nongnu.org; Tue, 10 Dec 2019 05:35:10 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1iecr9-0007NQ-2D for qemu-arm@nongnu.org; Tue, 10 Dec 2019 05:35:08 -0500 Received: from mel.act-europe.fr ([2a02:2ab8:224:1::a0a:d2]:41065 helo=smtp.eu.adacore.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1iecr8-0007MP-P2; Tue, 10 Dec 2019 05:35:03 -0500 Received: from localhost (localhost [127.0.0.1]) by filtered-smtp.eu.adacore.com (Postfix) with ESMTP id 1D4798138C; Tue, 10 Dec 2019 11:34:59 +0100 (CET) X-Virus-Scanned: Debian amavisd-new at eu.adacore.com Received: from smtp.eu.adacore.com ([127.0.0.1]) by localhost (smtp.eu.adacore.com [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id aBl5xW3mX5DS; Tue, 10 Dec 2019 11:34:59 +0100 (CET) Received: from localhost.localdomain (lfbn-tou-1-352-33.w86-206.abo.wanadoo.fr [86.206.184.33]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.eu.adacore.com (Postfix) with ESMTPSA id C928881388; Tue, 10 Dec 2019 11:34:58 +0100 (CET) Subject: Re: [PATCH 00/10] Add Allwinner H3 SoC and Orange Pi PC Machine To: Niek Linnenbank , qemu-devel@nongnu.org Cc: b.galvani@gmail.com, peter.maydell@linaro.org, qemu-arm@nongnu.org References: <20191202210947.3603-1-nieklinnenbank@gmail.com> From: KONRAD Frederic Message-ID: <6d774864-2bea-ecd6-0b14-a28d0756bfbc@adacore.com> Date: Tue, 10 Dec 2019 11:34:54 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101 Thunderbird/60.9.1 MIME-Version: 1.0 In-Reply-To: <20191202210947.3603-1-nieklinnenbank@gmail.com> Content-Type: text/plain; charset=utf-8; format=flowed Content-Language: fr Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x X-Received-From: 2a02:2ab8:224:1::a0a:d2 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 10 Dec 2019 10:35:10 -0000 Le 12/2/19 =C3=A0 10:09 PM, Niek Linnenbank a =C3=A9crit=C2=A0: > Dear QEMU developers, >=20 > Hereby I would like to contribute the following set of patches to QEMU > which add support for the Allwinner H3 System on Chip and the > Orange Pi PC machine. The following features and devices are supported: >=20 > * SMP (Quad Core Cortex A7) > * Generic Interrupt Controller configuration > * SRAM mappings > * Timer device (re-used from Allwinner A10) > * UART > * SD/MMC storage controller > * EMAC ethernet connectivity > * USB 2.0 interfaces > * Clock Control Unit > * System Control module > * Security Identifier device >=20 > Functionality related to graphical output such as HDMI, GPU, > Display Engine and audio are not included. Recently released > mainline Linux kernels (4.19 up to latest master) and mainline U-Boot > are known to work. The SD/MMC code is tested using bonnie++ and > various tools such as fsck, dd and fdisk. The EMAC is verified with ipe= rf3 > using -netdev socket. >=20 > To build a Linux mainline kernel that can be booted by the Orange Pi PC > machine, simply configure the kernel using the sunxi_defconfig configur= ation: > $ ARCH=3Darm CROSS_COMPILE=3Darm-linux-gnueabi- make mrproper > $ ARCH=3Darm CROSS_COMPILE=3Darm-linux-gnueabi- make sunxi_defconfig >=20 > To be able to use USB storage, you need to manually enable the correspo= nding > configuration item. Start the kconfig configuration tool: > $ ARCH=3Darm CROSS_COMPILE=3Darm-linux-gnueabi- make menuconfig >=20 > Navigate to the following item, enable it and save your configuration: > Device Drivers > USB support > USB Mass Storage support >=20 > Build the Linux kernel with: > $ ARCH=3Darm CROSS_COMPILE=3Darm-linux-gnueabi- make -j5 >=20 > To boot the newly build linux kernel in QEMU with the Orange Pi PC mach= ine, use: > $ qemu-system-arm -M orangepi -m 512 -nic user -nographic \ > -kernel /path/to/linux/arch/arm/boot/zImage \ > -append 'console=3DttyS0,115200' \ > -dtb /path/to/linux/arch/arm/boot/dts/sun8i-h3-orangepi-pc.dtb >=20 > Note that this kernel does not have a root filesystem. You may provide = it > with an official Orange Pi PC image [1] either as an SD card or as > USB mass storage. To boot using the Orange Pi PC Debian image on SD car= d, > simply add the -sd argument and provide the proper root=3D kernel param= eter: > $ qemu-system-arm -M orangepi -m 512 -nic user -nographic \ > -kernel /path/to/linux/arch/arm/boot/zImage \ > -append 'console=3DttyS0,115200 root=3D/dev/mmcblk0p2' \ > -dtb /path/to/linux/arch/arm/boot/dts/sun8i-h3-orangepi-pc.dtb \ > -sd OrangePi_pc_debian_stretch_server_linux5.3.5_v1.0.img >=20 > Alternatively, you can also choose to build and boot a recent buildroot= [2] > using the orangepi_pc_defconfig or Armbian image [3] for Orange Pi PC. > To attach an USB mass storage device to the machine, simply append to t= he command: > -drive if=3Dnone,id=3Dstick,file=3Dmyimage.img \ > -device usb-storage,bus=3Dusb-bus.0,drive=3Dstick >=20 > U-Boot mainline can be build and configured using the orangepi_pc_defco= nfig > using similar commands as describe above for Linux. To start U-Boot usi= ng > the Orange Pi PC machine, provide the u-boot binary to the -kernel argu= ment: > $ qemu-system-arm -M orangepi -m 512 -nic user -nographic \ > -kernel /path/to/uboot/u-boot -sd disk.img >=20 > Use the following U-boot commands to load and boot a Linux kernel from = SD card: > -> setenv bootargs console=3DttyS0,115200 > -> ext2load mmc 0 0x42000000 zImage > -> ext2load mmc 0 0x43000000 sun8i-h2-plus-orangepi-zero.dtb > -> bootz 0x42000000 - 0x43000000 >=20 > Looking forward to your review comments. I will do my best > to update the patches where needed. >=20 > With kind regards, >=20 > Niek Linnenbank >=20 > [1] http://www.orangepi.org/downloadresources/ > [2] https://buildroot.org/download.html > [3] https://www.armbian.com/orange-pi-pc/ Works well on my side with vanilla linux-4.9.13 built with gcc-8.3.0 + bu= sybox and sun8i-h3-orangepi-one.dtb. Tested-by: KONRAD Frederic >=20 > Niek Linnenbank (10): > hw: arm: add Allwinner H3 System-on-Chip > hw: arm: add Xunlong Orange Pi PC machine > arm: allwinner-h3: add Clock Control Unit > arm: allwinner-h3: add USB host controller > arm: allwinner-h3: add System Control module > arm/arm-powerctl: set NSACR.{CP11,CP10} bits in arm_set_cpu_on() > arm: allwinner-h3: add CPU Configuration module > arm: allwinner-h3: add Security Identifier device > arm: allwinner-h3: add SD/MMC host controller > arm: allwinner-h3: add EMAC ethernet device >=20 > MAINTAINERS | 8 + > default-configs/arm-softmmu.mak | 1 + > hw/arm/Kconfig | 9 + > hw/arm/Makefile.objs | 1 + > hw/arm/allwinner-h3.c | 316 ++++++++++ > hw/arm/orangepi.c | 114 ++++ > hw/misc/Makefile.objs | 4 + > hw/misc/allwinner-h3-clk.c | 227 ++++++++ > hw/misc/allwinner-h3-cpucfg.c | 280 +++++++++ > hw/misc/allwinner-h3-sid.c | 162 ++++++ > hw/misc/allwinner-h3-syscon.c | 139 +++++ > hw/misc/trace-events | 5 + > hw/net/Kconfig | 3 + > hw/net/Makefile.objs | 1 + > hw/net/allwinner-h3-emac.c | 786 +++++++++++++++++++++++++ > hw/net/trace-events | 10 + > hw/sd/Makefile.objs | 1 + > hw/sd/allwinner-h3-sdhost.c | 791 +++++++++++++++++++++++++= + > hw/sd/trace-events | 7 + > hw/usb/hcd-ehci-sysbus.c | 17 + > hw/usb/hcd-ehci.h | 1 + > include/hw/arm/allwinner-h3.h | 130 +++++ > include/hw/misc/allwinner-h3-clk.h | 41 ++ > include/hw/misc/allwinner-h3-cpucfg.h | 44 ++ > include/hw/misc/allwinner-h3-sid.h | 42 ++ > include/hw/misc/allwinner-h3-syscon.h | 43 ++ > include/hw/net/allwinner-h3-emac.h | 69 +++ > include/hw/sd/allwinner-h3-sdhost.h | 73 +++ > target/arm/arm-powerctl.c | 3 + > 29 files changed, 3328 insertions(+) > create mode 100644 hw/arm/allwinner-h3.c > create mode 100644 hw/arm/orangepi.c > create mode 100644 hw/misc/allwinner-h3-clk.c > create mode 100644 hw/misc/allwinner-h3-cpucfg.c > create mode 100644 hw/misc/allwinner-h3-sid.c > create mode 100644 hw/misc/allwinner-h3-syscon.c > create mode 100644 hw/net/allwinner-h3-emac.c > create mode 100644 hw/sd/allwinner-h3-sdhost.c > create mode 100644 include/hw/arm/allwinner-h3.h > create mode 100644 include/hw/misc/allwinner-h3-clk.h > create mode 100644 include/hw/misc/allwinner-h3-cpucfg.h > create mode 100644 include/hw/misc/allwinner-h3-sid.h > create mode 100644 include/hw/misc/allwinner-h3-syscon.h > create mode 100644 include/hw/net/allwinner-h3-emac.h > create mode 100644 include/hw/sd/allwinner-h3-sdhost.h >=20 From MAILER-DAEMON Tue Dec 10 06:05:47 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1iedKt-0001do-Nn for mharc-qemu-arm@gnu.org; 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bh=z5V5YY8ucihfErt16zYIpWs1KUH/OqX2XpnQG4ohYVk=; b=HQuZzC0nxs07fYH9XUT2bo/Wl4anCwgOw0X/6eblk1ZElZPA/Ql/trsJ8pxWCSeuIz3T32 pwdlbnNBOyBA91THJG5bnT66/6RlIFrHm2XVmyQbEd4TNW82vUROWZmTiGONz9jnM1r9yp 9MAs9PIFCYxvVZ9TbHM8HCYWO4r4uB8= Received: from mimecast-mx01.redhat.com (mimecast-mx01.redhat.com [209.132.183.4]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-201-SR1kMiVrPKmk2g8b02wheA-1; Tue, 10 Dec 2019 06:05:37 -0500 Received: from smtp.corp.redhat.com (int-mx03.intmail.prod.int.phx2.redhat.com [10.5.11.13]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx01.redhat.com (Postfix) with ESMTPS id 64049802C9B; Tue, 10 Dec 2019 11:05:36 +0000 (UTC) Received: from kamzik.brq.redhat.com (unknown [10.43.2.160]) by smtp.corp.redhat.com (Postfix) with ESMTPS id 8FD236FDCE; Tue, 10 Dec 2019 11:05:33 +0000 (UTC) Date: Tue, 10 Dec 2019 12:05:31 +0100 From: Andrew Jones To: Peter Maydell Cc: Andrea Bolognani , bijan.mottahedeh@oracle.com, Marc Zyngier , Richard Henderson , QEMU Developers , qemu-arm Subject: Re: [PATCH v1 0/5] target/arm/kvm: Provide an option to adjust virtual time Message-ID: <20191210110531.psjzlikir2ep2omo@kamzik.brq.redhat.com> References: <20191016143410.5023-1-drjones@redhat.com> <20191206155327.7adiyjjkjh56mg2t@kamzik.brq.redhat.com> <596d07e933cb4da48dbba5b492e81a2438e78a2f.camel@redhat.com> MIME-Version: 1.0 In-Reply-To: X-Scanned-By: MIMEDefang 2.79 on 10.5.11.13 X-MC-Unique: SR1kMiVrPKmk2g8b02wheA-1 X-Mimecast-Spam-Score: 0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: quoted-printable Content-Disposition: inline X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 207.211.31.120 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 10 Dec 2019 11:05:46 -0000 On Tue, Dec 10, 2019 at 10:29:22AM +0000, Peter Maydell wrote: > On Tue, 10 Dec 2019 at 09:51, Andrea Bolognani wrot= e: > > > > On Fri, 2019-12-06 at 16:53 +0100, Andrew Jones wrote: > > > On Fri, Dec 06, 2019 at 03:22:58PM +0000, Peter Maydell wrote: > > > > On Wed, 16 Oct 2019 at 15:34, Andrew Jones wro= te: > > > > > This series is inspired by a series[1] posted by Bijan Mottahedeh= about > > > > > a year ago. The problem described in the cover letter of [1] is = easily > > > > > reproducible and some users would like to have the option to avoi= d it. > > > > > However the solution, which is to adjust the virtual counter offs= et each > > > > > time the VM transitions to the running state, introduces a differ= ent > > > > > problem, which is that the virtual and physical counters diverge.= As > > > > > described in the cover letter of [1] this divergence is easily ob= served > > > > > when comparing the output of `date` and `hwclock` after suspendin= g the > > > > > guest, waiting a while, and then resuming it. Because this diffe= rent > > > > > problem may actually be worse for some users, unlike [1], the ser= ies > > > > > posted here makes the virtual counter offset adjustment optional = and not > > > > > even enabled by default. Besides the adjustment being optional, = this > > > > > series approaches the needed changes differently to apply them in= more > > > > > appropriate locations. Finally, unlike [1], this series doesn't = attempt > > > > > to measure "pause time" itself. Simply using QEMU_CLOCK_VIRTUAL,= which > > > > > only ticks when the VM is not stopped, is sufficient. > > > > > > > > So I guess my overall question is "what is the x86 solution to > > > > this problem, and why is this all arm-specific?" It would also > > > > > > x86 adjusts the counter offset by default, and I don't think there's = any > > > way to turn that behavior off. I think it's too late to follow that > > > default for arm, but this series provides a way to opt into the same > > > behavior. > > > > My understanding is that turning kvm-adjvtime either on or off > > results in a different set of advantages and drawbacks, with neither > > begin a one-size-fits-all solution. So it's good that we offer a way > > for the user to pick one or the other based on their specific needs. >=20 > If this is the case, shouldn't we be looking at having the > option exist for all architectures, not just arm? Obviously > pre-existing behaviour would imply having the default have > to differ for some archs/machines. > x86 developers could easily add this feature if/when they need a way to disable their current default behavior. But, since the kvm-adjvtime default would likely be 'on' for them, then they'd probably prefer the feature be named kvm-no-adjvtime, and default 'off'. Should we try to anticipate what x86 might want when naming this feature? IMO, we should not, especially because I'm doubtful that x86 will ever want to implement it. Also, what about the other KVM capable architectures? Which defaults do they have now? And do we expect them to want to expose a switch to the user to change it? OTOH, I agree with Andrea that it would be nice if arm had the same default as x86, allowing the documentation regarding this stuff to apply to both. If we did choose to turn this feature on by default for virt-5.0, then maybe we should introduce the feature with the name kvm-no-adjvtime instead. Thanks, drew From MAILER-DAEMON Tue Dec 10 06:48:54 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1iee0c-0003aB-Gh for mharc-qemu-arm@gnu.org; Tue, 10 Dec 2019 06:48:54 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:33524) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iee0Z-0003YT-L1 for qemu-arm@nongnu.org; Tue, 10 Dec 2019 06:48:52 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1iee0Y-0006qH-EE for qemu-arm@nongnu.org; Tue, 10 Dec 2019 06:48:51 -0500 Received: from mail-ot1-x342.google.com ([2607:f8b0:4864:20::342]:41887) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1iee0Y-0006pU-8K for qemu-arm@nongnu.org; Tue, 10 Dec 2019 06:48:50 -0500 Received: by mail-ot1-x342.google.com with SMTP id r27so15199874otc.8 for ; Tue, 10 Dec 2019 03:48:49 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=SfXh7eKZqdpO2LGEgz3P0HSgLknLGqn+asJn+CHcrPI=; b=tE2Bm7qH6GjY2mQXj1MWvgEieR2tcKUidD2+T4ja754WnhBE5poHvZhfvZk96rQ5S2 ot2BaTtcY3DY42tK0z50hv406f57UoY7CIRrVDAwSk7/+YmaqNynl8/s0807+AgmdMcN qeKd5mpmh42vcCbxaUjAGhnzH+Fyp2gcCkdi9bAIAHhg+LdQd1EwriUvZeRcmZ1YteRK tlb/ayBCDE1x3f4pJyCP/RXMcyH7YTwW2dU5RF5ec/8ws3xgfU72zeJqC41XuS6IuSI/ KwF0F7NrVQc+czEmGXwgkIIL9YLUS2x1tu6eu6kBkzMN9shDKY8aYc3+91OXMdGyoYFA MhhQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=SfXh7eKZqdpO2LGEgz3P0HSgLknLGqn+asJn+CHcrPI=; b=GOy1+dHOX2CTU8c2+J2HbwYgG6HUwEhMWej6Rp6qNfRbIPmAemIzak5b/wXZiLV2gY 6MOM6Y9Ww1zzQftsiDjQdWBj+QyR7KCUgVFmy9q/aTeM8ftu4l5UX+G6njHCOOG+4GOh N6ZiVQtSQ9BQZzZCcWfi+TLw4KEdr465PrRrBcY17pP6Z4XWHlQgRSZeBjCpBwq/hUFs m7WtRnfDN+FoQRneWiuwFKMBaz9Zq2hprzuctuqpBCUpdTHvYVsfN5vT7wwbRYSHYYgp YRIFbZuvV2x4HWUcStlge1lpjwEqr4gfFR1SfST5h/ym9G4kNk6kFzlUwjAWlMZ6ZQ/c uhsg== X-Gm-Message-State: APjAAAUSH+nU4PoyU9jT59AD/O18qK8WRX1H6LtURYOJld3aPG3tvGR+ Auvjq6pI7cbdVht0NSA5Yr1ml9eYOeDlxTrWUnTCfA== X-Google-Smtp-Source: APXvYqx16K1ZVv4gv8fQvB3f5jY1DQINqwMflWH7jrq9BnIDUnmN6ak6Qlo+A9+K9Zeo9StUIhpvspJu/yxV93Rchq8= X-Received: by 2002:a9d:4d8a:: with SMTP id u10mr10486979otk.232.1575978529096; Tue, 10 Dec 2019 03:48:49 -0800 (PST) MIME-Version: 1.0 References: <20191016143410.5023-1-drjones@redhat.com> <20191206155327.7adiyjjkjh56mg2t@kamzik.brq.redhat.com> <596d07e933cb4da48dbba5b492e81a2438e78a2f.camel@redhat.com> <20191210110531.psjzlikir2ep2omo@kamzik.brq.redhat.com> In-Reply-To: <20191210110531.psjzlikir2ep2omo@kamzik.brq.redhat.com> From: Peter Maydell Date: Tue, 10 Dec 2019 11:48:38 +0000 Message-ID: Subject: Re: [PATCH v1 0/5] target/arm/kvm: Provide an option to adjust virtual time To: Andrew Jones Cc: Andrea Bolognani , bijan.mottahedeh@oracle.com, Marc Zyngier , Richard Henderson , QEMU Developers , qemu-arm Content-Type: text/plain; charset="UTF-8" X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::342 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 10 Dec 2019 11:48:52 -0000 On Tue, 10 Dec 2019 at 11:05, Andrew Jones wrote: > x86 developers could easily add this feature if/when they need a way to > disable their current default behavior. But, since the kvm-adjvtime > default would likely be 'on' for them, then they'd probably prefer the > feature be named kvm-no-adjvtime, and default 'off'. Should we try to > anticipate what x86 might want when naming this feature? IMO, we should > not, especially because I'm doubtful that x86 will ever want to implement > it. Also, what about the other KVM capable architectures? Which defaults > do they have now? And do we expect them to want to expose a switch to the > user to change it? My perspective here is mostly that I don't really understand the ins and outs of KVM and in particular handling of time in VMs, beyond knowing that it's complicated. So I prefer approaches that push back to "do everything the same for all architectures rather than having something that's arm-specific", because then things get more review from the larger mass of non-arm KVM/QEMU developers. Arm-specific switches/interfaces/designs just make arm more of a special-snowflake. I don't really have a basis to be able to review the patchset beyond those general biases. thanks -- PMM From MAILER-DAEMON Tue Dec 10 07:52:53 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1ief0W-0008Qw-US for mharc-qemu-arm@gnu.org; Tue, 10 Dec 2019 07:52:52 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:51459) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ief0U-0008Oy-0h for qemu-arm@nongnu.org; Tue, 10 Dec 2019 07:52:51 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ief0S-0001HB-Jb for qemu-arm@nongnu.org; Tue, 10 Dec 2019 07:52:49 -0500 Received: from 7.mo5.mail-out.ovh.net ([178.32.124.100]:48809) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1ief0S-0001Gc-Cn for qemu-arm@nongnu.org; Tue, 10 Dec 2019 07:52:48 -0500 Received: from player759.ha.ovh.net (unknown [10.108.1.181]) by mo5.mail-out.ovh.net (Postfix) with ESMTP id 234BC25DC14 for ; Tue, 10 Dec 2019 13:52:45 +0100 (CET) Received: from kaod.org (lfbn-1-2229-223.w90-76.abo.wanadoo.fr [90.76.50.223]) (Authenticated sender: clg@kaod.org) by player759.ha.ovh.net (Postfix) with ESMTPSA id C375ED2502F3; Tue, 10 Dec 2019 12:52:40 +0000 (UTC) Subject: Re: [PATCH 2/2] hw/arm: ast2600: Wire up the eMMC controller To: Andrew Jeffery , qemu-arm@nongnu.org Cc: peter.maydell@linaro.org, joel@jms.id.au, qemu-devel@nongnu.org References: <5a93d2f9d375f92e9db6b1cf8687f86beaedcbb2.1575938234.git-series.andrew@aj.id.au> From: =?UTF-8?Q?C=c3=a9dric_Le_Goater?= Message-ID: Date: Tue, 10 Dec 2019 13:52:39 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.1.1 MIME-Version: 1.0 In-Reply-To: <5a93d2f9d375f92e9db6b1cf8687f86beaedcbb2.1575938234.git-series.andrew@aj.id.au> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 7bit X-Ovh-Tracer-Id: 10744744289061342016 X-VR-SPAMSTATE: OK X-VR-SPAMSCORE: -100 X-VR-SPAMCAUSE: gggruggvucftvghtrhhoucdtuddrgedufedrudelfedggeehucetufdoteggodetrfdotffvucfrrhhofhhilhgvmecuqfggjfdpvefjgfevmfevgfenuceurghilhhouhhtmecuhedttdenucesvcftvggtihhpihgvnhhtshculddquddttddmnecujfgurhepuffvfhfhkffffgggjggtgfesthejredttdefjeenucfhrhhomhepveorughrihgtpgfnvggpifhorghtvghruceotghlgheskhgrohgurdhorhhgqeenucfkpheptddrtddrtddrtddpledtrdejiedrhedtrddvvdefnecurfgrrhgrmhepmhhouggvpehsmhhtphdqohhuthdphhgvlhhopehplhgrhigvrhejheelrdhhrgdrohhvhhdrnhgvthdpihhnvghtpedtrddtrddtrddtpdhmrghilhhfrhhomheptghlgheskhgrohgurdhorhhgpdhrtghpthhtohepqhgvmhhuqdgrrhhmsehnohhnghhnuhdrohhrghenucevlhhushhtvghrufhiiigvpedt X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 178.32.124.100 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 10 Dec 2019 12:52:51 -0000 On 10/12/2019 01:52, Andrew Jeffery wrote: > Initialise another SDHCI model instance for the AST2600's eMMC > controller and use the SDHCI's num_slots value introduced previously to > determine whether we should create an SD card instance for the new slot. > > Signed-off-by: Andrew Jeffery LGTM. One comment. > --- > hw/arm/aspeed.c | 13 +++++++++++++ > hw/arm/aspeed_ast2600.c | 21 +++++++++++++++++++++ > include/hw/arm/aspeed_soc.h | 2 ++ > 3 files changed, 36 insertions(+) > > diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c > index 862549b1f3a9..0e08d62e9ff3 100644 > --- a/hw/arm/aspeed.c > +++ b/hw/arm/aspeed.c > @@ -272,6 +272,19 @@ static void aspeed_board_init(MachineState *machine, > object_property_set_bool(OBJECT(card), true, "realized", &error_fatal); > } > > + if (bmc->soc.emmc.num_slots) { > + SDHCIState *emmc = &bmc->soc.emmc.slots[0]; > + DriveInfo *dinfo = drive_get_next(IF_SD); > + BlockBackend *blk; > + DeviceState *card; > + > + blk = dinfo ? blk_by_legacy_dinfo(dinfo) : NULL; > + card = qdev_create(qdev_get_child_bus(DEVICE(emmc), "sd-bus"), > + TYPE_SD_CARD); > + qdev_prop_set_drive(card, "drive", blk, &error_fatal); > + object_property_set_bool(OBJECT(card), true, "realized", &error_fatal); > + } I think we could use a function for the above ^ C. > arm_load_kernel(ARM_CPU(first_cpu), machine, &aspeed_board_binfo); > } > > diff --git a/hw/arm/aspeed_ast2600.c b/hw/arm/aspeed_ast2600.c > index 931ee5aae183..723c8196c8a5 100644 > --- a/hw/arm/aspeed_ast2600.c > +++ b/hw/arm/aspeed_ast2600.c > @@ -46,6 +46,7 @@ static const hwaddr aspeed_soc_ast2600_memmap[] = { > [ASPEED_ADC] = 0x1E6E9000, > [ASPEED_VIDEO] = 0x1E700000, > [ASPEED_SDHCI] = 0x1E740000, > + [ASPEED_EMMC] = 0x1E750000, > [ASPEED_GPIO] = 0x1E780000, > [ASPEED_GPIO_1_8V] = 0x1E780800, > [ASPEED_RTC] = 0x1E781000, > @@ -64,6 +65,7 @@ static const hwaddr aspeed_soc_ast2600_memmap[] = { > > #define ASPEED_SOC_AST2600_MAX_IRQ 128 > > +/* Shared Peripheral Interrupt values below are offset by -32 from datasheet */ > static const int aspeed_soc_ast2600_irqmap[] = { > [ASPEED_UART1] = 47, > [ASPEED_UART2] = 48, > @@ -77,6 +79,7 @@ static const int aspeed_soc_ast2600_irqmap[] = { > [ASPEED_ADC] = 78, > [ASPEED_XDMA] = 6, > [ASPEED_SDHCI] = 43, > + [ASPEED_EMMC] = 15, > [ASPEED_GPIO] = 40, > [ASPEED_GPIO_1_8V] = 11, > [ASPEED_RTC] = 13, > @@ -215,6 +218,14 @@ static void aspeed_soc_ast2600_init(Object *obj) > sysbus_init_child_obj(obj, "sdhci[*]", OBJECT(&s->sdhci.slots[i]), > sizeof(s->sdhci.slots[i]), TYPE_SYSBUS_SDHCI); > } > + > + sysbus_init_child_obj(obj, "emmc", OBJECT(&s->emmc), sizeof(s->emmc), > + TYPE_ASPEED_SDHCI); > + > + object_property_set_int(OBJECT(&s->emmc), 1, "num-slots", &error_abort); > + > + sysbus_init_child_obj(obj, "emmc[*]", OBJECT(&s->emmc.slots[0]), > + sizeof(s->emmc.slots[0]), TYPE_SYSBUS_SDHCI); > } > > /* > @@ -487,6 +498,16 @@ static void aspeed_soc_ast2600_realize(DeviceState *dev, Error **errp) > sc->memmap[ASPEED_SDHCI]); > sysbus_connect_irq(SYS_BUS_DEVICE(&s->sdhci), 0, > aspeed_soc_get_irq(s, ASPEED_SDHCI)); > + > + /* eMMC */ > + object_property_set_bool(OBJECT(&s->emmc), true, "realized", &err); > + if (err) { > + error_propagate(errp, err); > + return; > + } > + sysbus_mmio_map(SYS_BUS_DEVICE(&s->emmc), 0, sc->memmap[ASPEED_EMMC]); > + sysbus_connect_irq(SYS_BUS_DEVICE(&s->emmc), 0, > + aspeed_soc_get_irq(s, ASPEED_EMMC)); > } > > static void aspeed_soc_ast2600_class_init(ObjectClass *oc, void *data) > diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h > index 495c08be1b84..911443f4c071 100644 > --- a/include/hw/arm/aspeed_soc.h > +++ b/include/hw/arm/aspeed_soc.h > @@ -56,6 +56,7 @@ typedef struct AspeedSoCState { > AspeedGPIOState gpio; > AspeedGPIOState gpio_1_8v; > AspeedSDHCIState sdhci; > + AspeedSDHCIState emmc; > } AspeedSoCState; > > #define TYPE_ASPEED_SOC "aspeed-soc" > @@ -125,6 +126,7 @@ enum { > ASPEED_MII4, > ASPEED_SDRAM, > ASPEED_XDMA, > + ASPEED_EMMC, > }; > > #endif /* ASPEED_SOC_H */ > From MAILER-DAEMON Tue Dec 10 08:33:11 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1iefdX-0002n4-Co for mharc-qemu-arm@gnu.org; Tue, 10 Dec 2019 08:33:11 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:39052) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iefdU-0002js-76 for qemu-arm@nongnu.org; Tue, 10 Dec 2019 08:33:09 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1iefdP-00029H-Oz for qemu-arm@nongnu.org; Tue, 10 Dec 2019 08:33:08 -0500 Received: from us-smtp-1.mimecast.com ([207.211.31.81]:24597 helo=us-smtp-delivery-1.mimecast.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1iefdP-00028g-KJ for qemu-arm@nongnu.org; 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Tue, 10 Dec 2019 13:32:58 +0000 (UTC) Received: from kamzik.brq.redhat.com (unknown [10.43.2.160]) by smtp.corp.redhat.com (Postfix) with ESMTPS id 998255DA70; Tue, 10 Dec 2019 13:32:56 +0000 (UTC) Date: Tue, 10 Dec 2019 14:32:54 +0100 From: Andrew Jones To: Peter Maydell Cc: bijan.mottahedeh@oracle.com, Marc Zyngier , Richard Henderson , QEMU Developers , Andrea Bolognani , qemu-arm Subject: Re: [PATCH v1 0/5] target/arm/kvm: Provide an option to adjust virtual time Message-ID: <20191210133254.22vcpvr3eabcnthe@kamzik.brq.redhat.com> References: <20191016143410.5023-1-drjones@redhat.com> <20191206155327.7adiyjjkjh56mg2t@kamzik.brq.redhat.com> <596d07e933cb4da48dbba5b492e81a2438e78a2f.camel@redhat.com> <20191210110531.psjzlikir2ep2omo@kamzik.brq.redhat.com> MIME-Version: 1.0 In-Reply-To: X-Scanned-By: MIMEDefang 2.79 on 10.5.11.14 X-MC-Unique: DpCF9hjAPVSXaf81I2sYTQ-1 X-Mimecast-Spam-Score: 0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: quoted-printable Content-Disposition: inline X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 207.211.31.81 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 10 Dec 2019 13:33:09 -0000 On Tue, Dec 10, 2019 at 11:48:38AM +0000, Peter Maydell wrote: > On Tue, 10 Dec 2019 at 11:05, Andrew Jones wrote: > > x86 developers could easily add this feature if/when they need a way to > > disable their current default behavior. But, since the kvm-adjvtime > > default would likely be 'on' for them, then they'd probably prefer the > > feature be named kvm-no-adjvtime, and default 'off'. Should we try to > > anticipate what x86 might want when naming this feature? IMO, we should > > not, especially because I'm doubtful that x86 will ever want to impleme= nt > > it. Also, what about the other KVM capable architectures? Which default= s > > do they have now? And do we expect them to want to expose a switch to t= he > > user to change it? >=20 > My perspective here is mostly that I don't really understand > the ins and outs of KVM and in particular handling of > time in VMs, beyond knowing that it's complicated. So I > prefer approaches that push back to "do everything the same > for all architectures rather than having something that's > arm-specific", because then things get more review from > the larger mass of non-arm KVM/QEMU developers. Arm-specific > switches/interfaces/designs just make arm more of a > special-snowflake. I don't really have a basis to be able > to review the patchset beyond those general biases. > So the ins and outs of this particular timekeeping issue (to the best of my knowledge) is that x86 has implemented this behavior since 00f4d64ee76e ("kvmclock: clock should count only if vm is running"), which was committed over six years ago. Possibly x86 VM time would behave more like arm VM time if kvmclock was disabled, but that's not a recommended configuration. PPC got an equivalent patch to the x86 one in 2017, 42043e4f1241 ("spapr: clock should count only if vm is running"), but when stopping time during pause on spapr they actually *keep* 'date' and 'hwclock' in synch. I guess whatever clocksource 'hwclock' uses on spapr was already stopping when paused? For x86 those values diverge, and for arm without this series they stay the same but experience jumps, and with this series they diverge like x86. I don't see any way to disable the behaviour 42043e4f1241 introduces. s390x got what appears to be its equivalent patch last year 9bc9d3d1ae3b ("s390x/tod: Properly stop the KVM TOD while the guest is not running"). The commit message doesn't state how hwclock and date values change / don't change, and I don't see any way to disable the behavior. MIPS has had this implemented since KVM support was introduced. No way to disable it that I know of. So why is this arm-specific? arm is just trying to catch up, but also offer a switch allowing the current behavior to be selected. If other architectures see value in the switch then they're free to adopt it too. After having done this git mining, it looks more and more like we should at least consider naming this feature 'kvm-no-adjvtime' and probably also change arm's default. Thanks, drew From MAILER-DAEMON Tue Dec 10 08:49:22 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1ieftC-00066M-Iw for mharc-qemu-arm@gnu.org; Tue, 10 Dec 2019 08:49:22 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:44483) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ieftA-00065W-8M for qemu-arm@nongnu.org; Tue, 10 Dec 2019 08:49:21 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ieft8-0007jW-G4 for qemu-arm@nongnu.org; Tue, 10 Dec 2019 08:49:19 -0500 Received: from us-smtp-1.mimecast.com ([205.139.110.61]:31733 helo=us-smtp-delivery-1.mimecast.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1ieft8-0007jA-Bu for qemu-arm@nongnu.org; Tue, 10 Dec 2019 08:49:18 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1575985757; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=I64k/0k0WqHLXmozMKl6bFkRveg8+eAnwsRxOZOuy1o=; b=L35dLW/wFoshKygftk0jLhW8iEVTurqKxOKFB9fU5RzxaglW/mhJcrJEnUz/qCnzBL16MX 2bzuniVjLXhcKsOhRMBRzLWwXc3vJuPqcrd4e5z2vnJz1ttjxQc56g95bC6KGpK2lTYr8K 1bcwc2WAWjC0mtmOTYB5NqyrE8LJXwo= Received: from mimecast-mx01.redhat.com (mimecast-mx01.redhat.com [209.132.183.4]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-108-mc-EPHbLP0i3DQouD872lQ-1; Tue, 10 Dec 2019 08:49:14 -0500 Received: from smtp.corp.redhat.com (int-mx07.intmail.prod.int.phx2.redhat.com [10.5.11.22]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx01.redhat.com (Postfix) with ESMTPS id 95FB112D658B; Tue, 10 Dec 2019 13:49:12 +0000 (UTC) Received: from localhost (unknown [10.43.2.114]) by smtp.corp.redhat.com (Postfix) with ESMTP id 3ADD710016E8; Tue, 10 Dec 2019 13:49:08 +0000 (UTC) Date: Tue, 10 Dec 2019 14:49:06 +0100 From: Igor Mammedov To: Peter Maydell Cc: Heyi Guo , qemu-arm , QEMU Developers , wanghaibin.wang@huawei.com, Shannon Zhao , "Michael S. Tsirkin" Subject: Re: [PATCH v6 0/2] arm/acpi: simplify aml code and enable SHPC Message-ID: <20191210144906.14e41c7a@redhat.com> In-Reply-To: References: <20191209063719.23086-1-guoheyi@huawei.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.84 on 10.5.11.22 X-MC-Unique: mc-EPHbLP0i3DQouD872lQ-1 X-Mimecast-Spam-Score: 0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 205.139.110.61 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 10 Dec 2019 13:49:21 -0000 On Mon, 9 Dec 2019 17:51:10 +0000 Peter Maydell wrote: > On Mon, 9 Dec 2019 at 06:38, Heyi Guo wrote: > > > > After the introduction of generic PCIe root port and PCIe-PCI bridge, we will > > also have SHPC controller on ARM, and we don't support ACPI hot plug, so just > > enable SHPC native hot plug. > > > > Igor also spotted the store operation outside of bit and/or is not necessary, so > > simply the code at first. > > > > v6: > > - Fix "make check" errors by updating tests/data/acpi/virt/DSDT*. > > > > v5: > > - Refine commit message of patch 1/2 > > > > v4: > > - Improve the code indention. > > > > Cc: Shannon Zhao > > Cc: Peter Maydell > > Cc: "Michael S. Tsirkin" > > Cc: Igor Mammedov > > Thanks, applied to target-arm.next. (it's a bit awkward that acpi > table updates require also updating a bunch of binary test files, > but I suppose trying to make the golden-reference be some textual > format would be not very feasible.) Michael tried document it (commit 30c63d4fbd69) so that binary blobs would not be required (trusted). Problem is usually in blobs being un-review-able and unresolvable merge conflicts, that's why Michael updates tables manually for all changes in pull req. But in this case it touches only ARM tables and it's the first change to go in, so it could just work out. > > thanks > -- PMM > From MAILER-DAEMON Tue Dec 10 09:01:55 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1ieg5K-0002d9-W5 for mharc-qemu-arm@gnu.org; Tue, 10 Dec 2019 09:01:55 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:47947) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ieg5H-0002cI-Bx for qemu-arm@nongnu.org; Tue, 10 Dec 2019 09:01:52 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ieg5C-0004e0-EL for qemu-arm@nongnu.org; Tue, 10 Dec 2019 09:01:51 -0500 Received: from mail-ot1-x343.google.com ([2607:f8b0:4864:20::343]:41156) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ieg5C-0004cf-7B for qemu-arm@nongnu.org; Tue, 10 Dec 2019 09:01:46 -0500 Received: by mail-ot1-x343.google.com with SMTP id r27so15536606otc.8 for ; Tue, 10 Dec 2019 06:01:46 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=30l090qRempxAQzWf4nBrff/DdGwPwgmUiqdyPb2KYc=; b=ONRmAizkqbJm3R6WGB70ZV/jttGViISia5PR8I9bebhYGd1Q/p8FaqOLWWYKoGrmWG 2v9RtUw2I1EufJwlC6S/T4Gv8ezsrTC79Som+z3I4SWmlSSAIfmcOAujeAWcU1kbS6IP kbYxDyQWKFQ5750gUU5VNRXNaoeYiRrj47e7FaSaFvstCQJ2I4S1JBP/wGmfL+FLCwDs 0AV8bo5TA7556zo9Etcx8tE97CtCxllWdy/At8vUxXdyXH8kiEQFNz8URdWfIs9AJtp/ sDCYYKh2rtEqvC3EOOcq1QS6+621kcDKhaDb+F08XW7fdmMrzA2cJ/Jh5wbfCdp13/b+ xB9g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=30l090qRempxAQzWf4nBrff/DdGwPwgmUiqdyPb2KYc=; b=pzlBywpEZ8DiUAhwzVqPhsjc8WXL3fTIOAThsTb48L7UQeN8nzGfEER39F7yO2wITz hEa2752JyC2N3o8DkJBVZ5Zt+xQqPR6etpeBLFDuDAJlcSlv13/fzLZHmXxcGW3ITt0C mmrcmDakGR3DCSQNiAuXXrv/LwwjQI+8LM4qZEHfjUclRROZuXK/WppX3vEC+GdGVA+w QNxkcsra50/2E0lp9fFTvsTMQ9ple0j2PUt4QO+ktodfBr4Fil9C2vYGSCEjrLETsLpA 3+avAy4iyIMPJYMkD5bvX6Czh9ZM2jZbFqtCVKstsZ79EDVMzAooPqz1bFu6DFzeSGEL GpTw== X-Gm-Message-State: APjAAAWFcZrnvCNqFMs5wPQ6gdJ2kG/CB/hJgRaH4Lq8l1DtsBiNeARF nwYDVRpqLONmlloK/3Gsch9nlI5eF49MdtauwghY+w== X-Google-Smtp-Source: APXvYqwbhAyU9JAibpwvBzzSxpsIiVjf+RAiPd4IG7VzhaqKPa5tnPjSVRFojYVHfLVpu04JbMCBEfqHTXVWtfZnpBM= X-Received: by 2002:a05:6830:4a4:: with SMTP id l4mr20181236otd.91.1575986503065; Tue, 10 Dec 2019 06:01:43 -0800 (PST) MIME-Version: 1.0 References: <20191209063719.23086-1-guoheyi@huawei.com> <20191210144906.14e41c7a@redhat.com> In-Reply-To: <20191210144906.14e41c7a@redhat.com> From: Peter Maydell Date: Tue, 10 Dec 2019 14:01:31 +0000 Message-ID: Subject: Re: [PATCH v6 0/2] arm/acpi: simplify aml code and enable SHPC To: Igor Mammedov Cc: Heyi Guo , qemu-arm , QEMU Developers , wanghaibin.wang@huawei.com, Shannon Zhao , "Michael S. Tsirkin" Content-Type: text/plain; charset="UTF-8" X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::343 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 10 Dec 2019 14:01:52 -0000 On Tue, 10 Dec 2019 at 13:49, Igor Mammedov wrote: > > On Mon, 9 Dec 2019 17:51:10 +0000 > Peter Maydell wrote: > > > On Mon, 9 Dec 2019 at 06:38, Heyi Guo wrote: > > > > > > After the introduction of generic PCIe root port and PCIe-PCI bridge, we will > > > also have SHPC controller on ARM, and we don't support ACPI hot plug, so just > > > enable SHPC native hot plug. > > > > > > Igor also spotted the store operation outside of bit and/or is not necessary, so > > > simply the code at first. > > > > > > v6: > > > - Fix "make check" errors by updating tests/data/acpi/virt/DSDT*. > > > > > > v5: > > > - Refine commit message of patch 1/2 > > > > > > v4: > > > - Improve the code indention. > > > > > > Cc: Shannon Zhao > > > Cc: Peter Maydell > > > Cc: "Michael S. Tsirkin" > > > Cc: Igor Mammedov > > > > Thanks, applied to target-arm.next. (it's a bit awkward that acpi > > table updates require also updating a bunch of binary test files, > > but I suppose trying to make the golden-reference be some textual > > format would be not very feasible.) > > Michael tried document it (commit 30c63d4fbd69) > so that binary blobs would not be required (trusted). > > Problem is usually in blobs being un-review-able and > unresolvable merge conflicts, that's why Michael > updates tables manually for all changes in pull req. A workflow that requires me to do a blob update when I apply patches to target-arm.next isn't going to work for me. If Michael wants the blobs to be handled like that, then all patches which need to touch them will have to go via his tree. thanks -- PMM From MAILER-DAEMON Tue Dec 10 09:06:38 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1ieg9u-0005f4-5c for mharc-qemu-arm@gnu.org; Tue, 10 Dec 2019 09:06:38 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:49088) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ieg9q-0005bn-SH for qemu-arm@nongnu.org; Tue, 10 Dec 2019 09:06:36 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ieg9p-0006Qd-Ck for qemu-arm@nongnu.org; Tue, 10 Dec 2019 09:06:34 -0500 Received: from mail-wm1-x341.google.com ([2a00:1450:4864:20::341]:36469) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ieg9i-0006Lw-6g; Tue, 10 Dec 2019 09:06:26 -0500 Received: by mail-wm1-x341.google.com with SMTP id p17so3352482wma.1; Tue, 10 Dec 2019 06:06:25 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=hFqtim+9HHduFLwD+2dEusU1yjl817nJKs7Wo98MEgE=; b=jMUOdv/4vkzCnEKeawJsCaVi+Lbjd2XAaHGdZ8MFuLCEzIggZVuTB0JOO6iu2Qa3m6 w7GF+iDZciJEIG650S+BFnThIV6mm62foubsEofJfklqn7OcfNn30Gmy8WqWiVH0nk6L AOWSx6JUP9rPubFybEFuKEbceJ3M1OrFcMjAwRMA1cYHFZerCujZDfLc+aCW9B8r9D32 4tXw4Gi+dJq2ntdoPNds7uHcPC/GMe0QH41R8TGnMIySVkrDVgYloQcCd0pye5ZNxfpe /llg3LC8pWA1YeIAJki2pc1p23WZi8qyQBrZZ3smx3Xfm5p6lbWJYjVxE3dfWUefNKpr oNkg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=hFqtim+9HHduFLwD+2dEusU1yjl817nJKs7Wo98MEgE=; b=fnj5WGVsP/+7+GAcjtJ0imbl/p4WwiEnT04QEUshEtLQcnOhwzZX/X33s9+POtk6TJ N000sXT4IelTiUNE0VibJruPWRsaQa5vn2XZ7BDJGvLRSlrIpH8VZo+vgx89Y53Tkb9z yAtS2suwB0AvrRfzz9h9VeVPRlsOz6ucP9QAQm69H40oLfQrVOJITLZK+rwx79btUEnO 8HQRM5UmCXrGmlw5NwjGRZHWmNjlzmMqUvOkWJvXmhKKyTvBP7wajwZO9jVmB8siXScp 6BLT5J5wzB7nwlERovt7zmxVIs8Wcut1HgRJcU2ozXcDLkmdWXHIRZGan5dN0U9IHVoX Qfsg== X-Gm-Message-State: APjAAAX7ceEPx7xkWN1+7IocKhUsMli427oU1UK3WRlcgemXabTBk/Db 3/9PGg2uKEgg8wjHHiF9wQE48DX71rk= X-Google-Smtp-Source: APXvYqwtA7VVHVotAEReY74Dbkn0vnsGgNqQ075JMMKF0EFSVWinb1Ye7UVp6qKoXgqlotsAQZ/YyQ== X-Received: by 2002:a7b:c19a:: with SMTP id y26mr5433570wmi.152.1575986784103; Tue, 10 Dec 2019 06:06:24 -0800 (PST) Received: from PKL-BWASIM-LT.mgc.mentorg.com ([110.93.212.98]) by smtp.gmail.com with ESMTPSA id n188sm3514002wme.14.2019.12.10.06.06.21 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 10 Dec 2019 06:06:23 -0800 (PST) From: bilalwasim676@gmail.com To: qemu-devel@nongnu.org Cc: jasowang@redhat.com, qemu-arm@nongnu.org, peter.maydell@linaro.org, philmd@redhat.com, mark.cave-ayland@ilande.co.uk, bwasim Subject: [PATCH v3] net/imx_fec: Adding support for MAC filtering in the FEC IP implementation. Date: Tue, 10 Dec 2019 19:06:17 +0500 Message-Id: <20191210140617.16656-1-bilalwasim676@gmail.com> X-Mailer: git-send-email 2.19.1.windows.1 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::341 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 10 Dec 2019 14:06:36 -0000 From: bwasim This addition ensures that the IP does NOT boot up in promiscuous mode by default, and so the software only receives the desired packets(Unicast, Broadcast, Unicast / Multicast hashed) by default. The software running on-top of QEMU can also modify these settings and disable reception of broadcast frames or make the IP receive all packets (PROM mode). This patch greatly reduces the number of packets received by the software running on-top of the QEMU model. Tested with the armv7-a SABRE_LITE machine. Testing included running a custom OS with IPv4 / IPv6 support. Hashing and filtering of packets is tested to work well. Skeleton taken from the CADENCE_GEM IP and hash generation algorithm from the Linux Kernel. Signed-off-by: Bilal Wasim --- hw/net/imx_fec.c | 109 ++++++++++++++++++++++++++++++++++++++- include/hw/net/imx_fec.h | 10 ++++ 2 files changed, 118 insertions(+), 1 deletion(-) diff --git a/hw/net/imx_fec.c b/hw/net/imx_fec.c index bd99236864..d248f39fb0 100644 --- a/hw/net/imx_fec.c +++ b/hw/net/imx_fec.c @@ -419,6 +419,79 @@ static void imx_enet_write_bd(IMXENETBufDesc *bd, dma_addr_t addr) dma_memory_write(&address_space_memory, addr, bd, sizeof(*bd)); } +/* + * Calculate a FEC MAC Address hash index + */ +static unsigned calc_mac_hash(const uint8_t *mac, uint8_t mac_length) +{ + uint32_t crc = net_crc32_le(mac, mac_length); + + /* + * only upper 6 bits (FEC_HASH_BITS) are used + * which point to specific bit in the hash registers + */ + return (crc >> (32 - FEC_HASH_BITS)) & 0x3f; +} + +/* + * fec_mac_address_filter: + * Accept or reject this destination address? + */ +static int fec_mac_address_filter(IMXFECState *s, const uint8_t *packet) +{ + const uint8_t broadcast_addr[] = { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }; + uint32_t addr1, addr2; + uint8_t hash; + + /* Promiscuous mode? */ + if (s->regs[ENET_RCR] & ENET_RCR_PROM) { + /* Accept all packets in promiscuous mode (even if bc_rej is set). */ + return FEC_RX_PROMISCUOUS_ACCEPT; + } + + /* Broadcast packet? */ + if (!memcmp(packet, broadcast_addr, 6)) { + /* Reject broadcast packets? */ + if (s->regs[ENET_RCR] & ENET_RCR_BC_REJ) { + return FEC_RX_REJECT; + } + /* Accept packets from broadcast address. */ + return FEC_RX_BROADCAST_ACCEPT; + } + + /* Accept packets -w- hash match? */ + hash = calc_mac_hash(packet, 6); + + /* Accept packets -w- multicast hash match? */ + if ((packet[0] & 0x01) == 0x01) { + /* Computed hash matches GAUR / GALR register ? */ + if (((hash < 32) && (s->regs[ENET_GALR] & (1 << hash))) + || ((hash > 31) && (s->regs[ENET_GAUR] & (1 << (hash - 32))))) { + /* Accept multicast hash enabled address. */ + return FEC_RX_MULTICAST_HASH_ACCEPT; + } + } else { + /* Computed hash matches IAUR / IALR register ? */ + if (((hash < 32) && (s->regs[ENET_IALR] & (1 << hash))) + || ((hash > 31) && (s->regs[ENET_IAUR] & (1 << (hash - 32))))) { + /* Accept multicast hash enabled address. */ + return FEC_RX_UNICAST_HASH_ACCEPT; + } + } + + /* Match Unicast address. */ + addr1 = g_htonl(s->regs[ENET_PALR]); + addr2 = g_htonl(s->regs[ENET_PAUR]); + if (!(memcmp(packet, (uint8_t *) &addr1, 4) || + memcmp(packet + 4, (uint8_t *) &addr2, 2))) { + /* Accept packet because it matches my unicast address. */ + return FEC_RX_UNICAST_ACCEPT; + } + + /* Return -1 because we do NOT support MAC address filtering.. */ + return FEC_RX_REJECT; +} + static void imx_eth_update(IMXFECState *s) { /* @@ -984,7 +1057,7 @@ static void imx_eth_write(void *opaque, hwaddr offset, uint64_t value, case ENET_IALR: case ENET_GAUR: case ENET_GALR: - /* TODO: implement MAC hash filtering. */ + s->regs[index] |= value; break; case ENET_TFWR: if (s->is_fec) { @@ -1066,8 +1139,15 @@ static ssize_t imx_fec_receive(NetClientState *nc, const uint8_t *buf, uint32_t buf_addr; uint8_t *crc_ptr; unsigned int buf_len; + int maf; size_t size = len; + /* Is this destination MAC address "for us" ? */ + maf = fec_mac_address_filter(s, buf); + if (maf == FEC_RX_REJECT) { + return FEC_RX_REJECT; + } + FEC_PRINTF("len %d\n", (int)size); if (!s->regs[ENET_RDAR]) { @@ -1133,6 +1213,16 @@ static ssize_t imx_fec_receive(NetClientState *nc, const uint8_t *buf, } else { s->regs[ENET_EIR] |= ENET_INT_RXB; } + + /* Update descriptor based on the "maf" flag. */ + if (maf == FEC_RX_BROADCAST_ACCEPT) { + /* The packet is destined for the "broadcast" address. */ + bd.flags |= ENET_BD_BC; + } else if (maf == FEC_RX_MULTICAST_HASH_ACCEPT) { + /* The packet is destined for a "multicast" address. */ + bd.flags |= ENET_BD_MC; + } + imx_fec_write_bd(&bd, addr); /* Advance to the next descriptor. */ if ((bd.flags & ENET_BD_W) != 0) { @@ -1159,8 +1249,15 @@ static ssize_t imx_enet_receive(NetClientState *nc, const uint8_t *buf, uint8_t *crc_ptr; unsigned int buf_len; size_t size = len; + int maf; bool shift16 = s->regs[ENET_RACC] & ENET_RACC_SHIFT16; + /* Is this destination MAC address "for us" ? */ + maf = fec_mac_address_filter(s, buf); + if (maf == FEC_RX_REJECT) { + return FEC_RX_REJECT; + } + FEC_PRINTF("len %d\n", (int)size); if (!s->regs[ENET_RDAR]) { @@ -1254,6 +1351,16 @@ static ssize_t imx_enet_receive(NetClientState *nc, const uint8_t *buf, s->regs[ENET_EIR] |= ENET_INT_RXB; } } + + /* Update descriptor based on the "maf" flag. */ + if (maf == FEC_RX_BROADCAST_ACCEPT) { + /* The packet is destined for the "broadcast" address. */ + bd.flags |= ENET_BD_BC; + } else if (maf == FEC_RX_MULTICAST_HASH_ACCEPT) { + /* The packet is destined for a "multicast" address. */ + bd.flags |= ENET_BD_MC; + } + imx_enet_write_bd(&bd, addr); /* Advance to the next descriptor. */ if ((bd.flags & ENET_BD_W) != 0) { diff --git a/include/hw/net/imx_fec.h b/include/hw/net/imx_fec.h index 7b3faa4019..f9cfcf6af5 100644 --- a/include/hw/net/imx_fec.h +++ b/include/hw/net/imx_fec.h @@ -275,4 +275,14 @@ typedef struct IMXFECState { uint8_t frame[ENET_MAX_FRAME_SIZE]; } IMXFECState; +/* FEC address filtering defines. */ +#define FEC_RX_REJECT (-1) +#define FEC_RX_PROMISCUOUS_ACCEPT (-2) +#define FEC_RX_BROADCAST_ACCEPT (-3) +#define FEC_RX_MULTICAST_HASH_ACCEPT (-4) +#define FEC_RX_UNICAST_HASH_ACCEPT (-5) +#define FEC_RX_UNICAST_ACCEPT (-6) + +#define FEC_HASH_BITS 6 /* #bits in hash */ + #endif -- 2.19.1.windows.1 From MAILER-DAEMON Tue Dec 10 09:21:23 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1iegOA-0002OF-0m for mharc-qemu-arm@gnu.org; Tue, 10 Dec 2019 09:21:22 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:52903) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iegO5-0002Nj-GJ for qemu-arm@nongnu.org; Tue, 10 Dec 2019 09:21:18 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1iegO3-0002zv-Du for qemu-arm@nongnu.org; Tue, 10 Dec 2019 09:21:16 -0500 Received: from us-smtp-2.mimecast.com ([205.139.110.61]:49652 helo=us-smtp-delivery-1.mimecast.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1iegO1-0002ym-V4 for qemu-arm@nongnu.org; Tue, 10 Dec 2019 09:21:14 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1575987672; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=moUHla2XqP5eoohiHGzDGD1SQJpqUmN21LiF4ELBiFE=; b=MalhjYhfGuV7gnWhRTWnitROGnc5cu9zZNFMyO+TpUdWW8oLZ2UOOcWDqedU/mNgJ21fRa js/WLtgZrqZAtNFdnWQIQaFQLqo/Qub901r2I2p7Xvesnxk3b59hG1Ih+2S5mVJ9QcobUi 4I1Pa4pmF/D2w8adjgQFyG/Xq6WNx5s= Received: from mimecast-mx01.redhat.com (mimecast-mx01.redhat.com [209.132.183.4]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-160-OwFQM3SrM72eeLypHmqsUQ-1; Tue, 10 Dec 2019 09:21:09 -0500 Received: from smtp.corp.redhat.com (int-mx02.intmail.prod.int.phx2.redhat.com [10.5.11.12]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx01.redhat.com (Postfix) with ESMTPS id 23C4F107AD24; Tue, 10 Dec 2019 14:21:08 +0000 (UTC) Received: from ovpn-205-189.brq.redhat.com (ovpn-205-189.brq.redhat.com [10.40.205.189]) by smtp.corp.redhat.com (Postfix) with ESMTPS id 7043B60BE2; Tue, 10 Dec 2019 14:21:05 +0000 (UTC) Message-ID: <29add42daba074ab5bdbd462b2d377115fec7c3c.camel@redhat.com> Subject: Re: [PATCH v1 0/5] target/arm/kvm: Provide an option to adjust virtual time From: Andrea Bolognani To: Andrew Jones , Peter Maydell Cc: bijan.mottahedeh@oracle.com, Marc Zyngier , Richard Henderson , QEMU Developers , qemu-arm Date: Tue, 10 Dec 2019 15:21:02 +0100 In-Reply-To: <20191210133254.22vcpvr3eabcnthe@kamzik.brq.redhat.com> References: <20191016143410.5023-1-drjones@redhat.com> <20191206155327.7adiyjjkjh56mg2t@kamzik.brq.redhat.com> <596d07e933cb4da48dbba5b492e81a2438e78a2f.camel@redhat.com> <20191210110531.psjzlikir2ep2omo@kamzik.brq.redhat.com> <20191210133254.22vcpvr3eabcnthe@kamzik.brq.redhat.com> User-Agent: Evolution 3.34.2 (3.34.2-1.fc31) MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.79 on 10.5.11.12 X-MC-Unique: OwFQM3SrM72eeLypHmqsUQ-1 X-Mimecast-Spam-Score: 0 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: 7bit X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 205.139.110.61 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 10 Dec 2019 14:21:19 -0000 On Tue, 2019-12-10 at 14:32 +0100, Andrew Jones wrote: > After having done this git mining, it looks more and more like we should > at least consider naming this feature 'kvm-no-adjvtime' and probably > also change arm's default. I agree with everything except the naming: why would kvm-no-adjvtime=off vtime is adjusted (default) kvm-no-adjvtime=on vtime is not adjusted be better than kvm-adjvtime=on vtime is adjusted (default) kvm-adjvtime=off vtime is not adjusted ? Both offer the exact same amount of flexibility, but the latter has the advantage of not introducing any unwieldy double negatives. -- Andrea Bolognani / Red Hat / Virtualization From MAILER-DAEMON Tue Dec 10 09:33:26 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1iegZq-0005Q5-KO for mharc-qemu-arm@gnu.org; Tue, 10 Dec 2019 09:33:26 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:56111) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iegZn-0005OI-GC for qemu-arm@nongnu.org; Tue, 10 Dec 2019 09:33:24 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1iegZl-0007uT-EO for qemu-arm@nongnu.org; Tue, 10 Dec 2019 09:33:22 -0500 Received: from us-smtp-1.mimecast.com ([205.139.110.61]:21693 helo=us-smtp-delivery-1.mimecast.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1iegZl-0007u3-2e for qemu-arm@nongnu.org; Tue, 10 Dec 2019 09:33:21 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1575988400; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=CF9FF+QH9Bg3CfnWnAhWc9idI2ShEituj8X2BRinmuo=; b=fcFPeZuZEKUDgFWpbRC5ZpUxGy9S/5fxRp5zUIpxYnciJiWONKzlvfPu4YDjn+8erBnY5H 3L+o3nszRd/gSzqH8SpJAY+3gDJ8fOv3ob8tTuFu9UGTyw2FR3fKs1wU1pRrjf6SkG9Epn 8Ref0JU+mG5jmgk8Ksu4RUAFxZrg3Fc= Received: from mimecast-mx01.redhat.com (mimecast-mx01.redhat.com [209.132.183.4]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-350-YCILETSNOjaWPB1QS-volA-1; Tue, 10 Dec 2019 09:33:16 -0500 Received: from smtp.corp.redhat.com (int-mx06.intmail.prod.int.phx2.redhat.com [10.5.11.16]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx01.redhat.com (Postfix) with ESMTPS id 2A9AE1800D45; Tue, 10 Dec 2019 14:33:15 +0000 (UTC) Received: from kamzik.brq.redhat.com (unknown [10.43.2.160]) by smtp.corp.redhat.com (Postfix) with ESMTPS id 911665C219; Tue, 10 Dec 2019 14:33:13 +0000 (UTC) Date: Tue, 10 Dec 2019 15:33:11 +0100 From: Andrew Jones To: Andrea Bolognani Cc: Peter Maydell , Marc Zyngier , qemu-arm , Richard Henderson , bijan.mottahedeh@oracle.com, QEMU Developers Subject: Re: [PATCH v1 0/5] target/arm/kvm: Provide an option to adjust virtual time Message-ID: <20191210143311.4sen6blhfhzop6zw@kamzik.brq.redhat.com> References: <20191016143410.5023-1-drjones@redhat.com> <20191206155327.7adiyjjkjh56mg2t@kamzik.brq.redhat.com> <596d07e933cb4da48dbba5b492e81a2438e78a2f.camel@redhat.com> <20191210110531.psjzlikir2ep2omo@kamzik.brq.redhat.com> <20191210133254.22vcpvr3eabcnthe@kamzik.brq.redhat.com> <29add42daba074ab5bdbd462b2d377115fec7c3c.camel@redhat.com> MIME-Version: 1.0 In-Reply-To: <29add42daba074ab5bdbd462b2d377115fec7c3c.camel@redhat.com> X-Scanned-By: MIMEDefang 2.79 on 10.5.11.16 X-MC-Unique: YCILETSNOjaWPB1QS-volA-1 X-Mimecast-Spam-Score: 0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: quoted-printable Content-Disposition: inline X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 205.139.110.61 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 10 Dec 2019 14:33:25 -0000 On Tue, Dec 10, 2019 at 03:21:02PM +0100, Andrea Bolognani wrote: > On Tue, 2019-12-10 at 14:32 +0100, Andrew Jones wrote: > > After having done this git mining, it looks more and more like we shoul= d > > at least consider naming this feature 'kvm-no-adjvtime' and probably > > also change arm's default. >=20 > I agree with everything except the naming: why would >=20 > kvm-no-adjvtime=3Doff vtime is adjusted (default) > kvm-no-adjvtime=3Don vtime is not adjusted >=20 > be better than >=20 > kvm-adjvtime=3Don vtime is adjusted (default) > kvm-adjvtime=3Doff vtime is not adjusted >=20 > ? Both offer the exact same amount of flexibility, but the latter has > the advantage of not introducing any unwieldy double negatives. > A default of 'off' =3D=3D 0 means not setting anything at all. There's already precedent for 'kvm-no*' prefixed cpu features, kvm-no-smi-migration kvm-nopiodelay (Unless there's something called a 'nopio' then I guess that one is missing a -, but whatever...) Thanks, drew From MAILER-DAEMON Tue Dec 10 10:45:29 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1iehhZ-0003lf-PH for mharc-qemu-arm@gnu.org; Tue, 10 Dec 2019 10:45:29 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:44909) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iehhT-0003dl-C5 for qemu-arm@nongnu.org; Tue, 10 Dec 2019 10:45:28 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1iehhR-0001GR-TN for qemu-arm@nongnu.org; Tue, 10 Dec 2019 10:45:22 -0500 Received: from mail-ot1-x343.google.com ([2607:f8b0:4864:20::343]:35476) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1iehhR-0001FC-NX for qemu-arm@nongnu.org; Tue, 10 Dec 2019 10:45:21 -0500 Received: by mail-ot1-x343.google.com with SMTP id o9so15893205ote.2 for ; Tue, 10 Dec 2019 07:45:21 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=BzYMi4o5tnM8+8TW8stcvngRLupsDB7APP25/5NOis8=; b=ZBCDTLuHsRqqPhpnw4ZnsfkALAysJLqfOnpMBc3TMKRYD6D1NyxSzRa5jCvEh7L+iF NTcF7Ca5X9bszyyN+jiD/YOS2ElDgIjzAWxZSLn6LLGnQjuHjPGJM8Z5z+7Y80WO+qc5 KJ86U98SQSBQm5fxuXJiElNJOjpvZpQKCXRURRAXPuLvYCwxJWQtzatrv4SbO3hQFB3d 3/qeOX2T0cjjO85pDILjRiIryKDVheA2ebR10xvGL+pq/z4Ud85QaYCQf62qJou/AOiH brk5EaJAKmJrm4vQHf1x+azvax3X1wegaq1YPieQDb19N9BLvkHmCFYNYGethOlLNCnP yapQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=BzYMi4o5tnM8+8TW8stcvngRLupsDB7APP25/5NOis8=; b=HpxIC64w2E9I4Z1yGiwbJu/CMpk49j2k76QnywEwi6Z2PoLqP70cIJ7cX7/qmI9vQi 7V5vss2YW+eN/wmS3W4yNUEOxxVvTnKiATGHf+IbmC7fa2hdK8sYJXuLLXPgPssOS0zW +1NfN1naTHQH8oHg1rbBoxRLpkfUXl0KXQREh2acrgTCNXB5kER8EQRdaYR4xYp7d4+K /sOR0le/RM3Z4dqKQ5910nYl3oQja+SQ3+nGrJTMvHuKUtrPlM8E54LkHksetE4Ze98v usSkWY0LmGrqHImAuc1vuqT4q7bmP29ZfsIFjESGmHSsjMHPeKJKNrBuKtkDIT5PZP6l sUiw== X-Gm-Message-State: APjAAAXGGHs9qlev+pmJGMYIIO0LUbs7yWuTtGxKqFcX9fJLDlncPSKJ 3ZaS9lwj1yYuXbO/LyKiTlAnhJ6PK0TIJX+/pobpnA== X-Google-Smtp-Source: APXvYqySfmyrxjXFPAv0TQJndI2bCGuPYwLb/lA4co49/ecx4y6IXbDUXIiyWa+65VdfYYCTM6v6c8pNaUGcNJlSOoo= X-Received: by 2002:a9d:6745:: with SMTP id w5mr25113617otm.221.1575992720459; Tue, 10 Dec 2019 07:45:20 -0800 (PST) MIME-Version: 1.0 References: <20191016143410.5023-1-drjones@redhat.com> <20191206155327.7adiyjjkjh56mg2t@kamzik.brq.redhat.com> <596d07e933cb4da48dbba5b492e81a2438e78a2f.camel@redhat.com> <20191210110531.psjzlikir2ep2omo@kamzik.brq.redhat.com> <20191210133254.22vcpvr3eabcnthe@kamzik.brq.redhat.com> In-Reply-To: <20191210133254.22vcpvr3eabcnthe@kamzik.brq.redhat.com> From: Peter Maydell Date: Tue, 10 Dec 2019 15:45:09 +0000 Message-ID: Subject: Re: [PATCH v1 0/5] target/arm/kvm: Provide an option to adjust virtual time To: Andrew Jones Cc: bijan.mottahedeh@oracle.com, Marc Zyngier , Richard Henderson , QEMU Developers , Andrea Bolognani , qemu-arm Content-Type: text/plain; charset="UTF-8" X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::343 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 10 Dec 2019 15:45:28 -0000 On Tue, 10 Dec 2019 at 13:33, Andrew Jones wrote: > So the ins and outs of this particular timekeeping issue (to the best of > my knowledge) is that x86 has implemented this behavior since > 00f4d64ee76e ("kvmclock: clock should count only if vm is running"), which > was committed over six years ago. Possibly x86 VM time would behave more > like arm VM time if kvmclock was disabled, but that's not a recommended > configuration. > > PPC got an equivalent patch to the x86 one in 2017, 42043e4f1241 ("spapr: > clock should count only if vm is running"), but when stopping time during > pause on spapr they actually *keep* 'date' and 'hwclock' in synch. I guess > whatever clocksource 'hwclock' uses on spapr was already stopping when > paused? For x86 those values diverge, and for arm without this series they > stay the same but experience jumps, and with this series they diverge like > x86. I don't see any way to disable the behaviour 42043e4f1241 introduces. > > s390x got what appears to be its equivalent patch last year 9bc9d3d1ae3b > ("s390x/tod: Properly stop the KVM TOD while the guest is not running"). > The commit message doesn't state how hwclock and date values change / > don't change, and I don't see any way to disable the behavior. > > MIPS has had this implemented since KVM support was introduced. No way > to disable it that I know of. > > So why is this arm-specific? arm is just trying to catch up, but also > offer a switch allowing the current behavior to be selected. If other > architectures see value in the switch then they're free to adopt it too. > After having done this git mining, it looks more and more like we should > at least consider naming this feature 'kvm-no-adjvtime' and probably > also change arm's default. Thanks for pulling up the handling by other architectures. I think I agree that we should change the arm default (ie we should just call this a bug fix, since the old behaviour seems unhelpful generally and is more random accident than a deliberate choice), with a switch provided just in case anybody had something depending on the old behaviour. -- PMM From MAILER-DAEMON Tue Dec 10 10:47:58 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1iehjx-000519-9w for mharc-qemu-arm@gnu.org; Tue, 10 Dec 2019 10:47:57 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:45506) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iehjs-00050n-Dz for qemu-arm@nongnu.org; Tue, 10 Dec 2019 10:47:53 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1iehjr-0003rZ-Fw for qemu-arm@nongnu.org; Tue, 10 Dec 2019 10:47:52 -0500 Received: from mail-oi1-x242.google.com ([2607:f8b0:4864:20::242]:38842) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1iehjr-0003qC-A0 for qemu-arm@nongnu.org; Tue, 10 Dec 2019 10:47:51 -0500 Received: by mail-oi1-x242.google.com with SMTP id b8so10206698oiy.5 for ; Tue, 10 Dec 2019 07:47:51 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=XPpi0vWeudD6eliQvYxFheqKFj6RhBHkYhtXnEujgKU=; b=ZMctcl6378t/GTgCTqQheHWa40RYt9BQRLQFkr3hs7KrhmWKUnIRwlRQ85I+g2sXKr 8KNkl/UEDjq1vBZf3lN7J/cpPcgsYZqdhfb5sxgeu3mpTtHgGbeVaTWctrtSqvU1hUFu GSL/h4jvj/Lk0dhgVWk936q0Ggly9hj8G0R1rWdcg3uliWT2P0OSG1sAPS4LlQZUZ6zP 9R2bLQXUkOVb1tAFtHP/6QcRHp+ynmfs+vxmSaG1elnh5EXKJ6lqXmS+Pai22xzoygWr shzMPwpfUYpiNCM1Ziy6FrIaEaTR5pjv0RWHNRqSNtSpinfumFMOL1UWGIpzI3e8d93h /HMg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=XPpi0vWeudD6eliQvYxFheqKFj6RhBHkYhtXnEujgKU=; b=JuOOj+FmRkJcHnBnKjeQTI85uxN1d5oVHyN5WlqdW0/XMOvkFhxJDzAzV9BegRQxrs ADrvPoumOHXa71detPE1QEhDTipkdbtbW/XBScyTBcYp08zRrsuM6DFKD1yIvz6VFwOb hFvYAD2twg66wEf3oVoRPr+i9kQqq6xeHJ50dTc5lcG26zU2V2z3N7DtGqIWkZOroCQt bBqmfjXkdBVbsMCqdYscCRtW9eIfHQDsAzat+ivD156b1vxd8iUY7Rn4wJquZ9xElp5s 4GBZUj5I/Ig70W+/FPBVTdQ1GQ48YOxoR/65bYzF/ZD1BXh6z/AWD+2qykDN1u5v9+B/ wzFw== X-Gm-Message-State: APjAAAXj6OsDfNEr7kMHH0Z8x38/yyuwq+yZmpxkxEobGa8ex7lk3Lb7 M0X2wMGrdl59zi0e7fmuC1hhKprdEF9ceylk7H497Q== X-Google-Smtp-Source: APXvYqzjzjCGxfqhWqUxs527OoEU8tYHKNRXvPQyjvdNKQD7l5ahY5zXiPjh20bYvn/5Y6BM31prx2/EUuht7mOo6aE= X-Received: by 2002:a05:6808:996:: with SMTP id a22mr4257367oic.146.1575992870184; Tue, 10 Dec 2019 07:47:50 -0800 (PST) MIME-Version: 1.0 References: <20191016143410.5023-1-drjones@redhat.com> <20191016143410.5023-3-drjones@redhat.com> In-Reply-To: <20191016143410.5023-3-drjones@redhat.com> From: Peter Maydell Date: Tue, 10 Dec 2019 15:47:39 +0000 Message-ID: Subject: Re: [PATCH v1 2/5] timer: arm: Introduce functions to get the host cntfrq To: Andrew Jones Cc: QEMU Developers , qemu-arm , Richard Henderson , bijan.mottahedeh@oracle.com, Marc Zyngier Content-Type: text/plain; charset="UTF-8" X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::242 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 10 Dec 2019 15:47:54 -0000 On Wed, 16 Oct 2019 at 15:34, Andrew Jones wrote: > > When acceleration like KVM is in use it's necessary to use the host's > counter frequency when converting ticks to or from time units. > > Signed-off-by: Andrew Jones > Reviewed-by: Richard Henderson > --- > include/qemu/timer.h | 16 ++++++++++++++++ > 1 file changed, 16 insertions(+) > > diff --git a/include/qemu/timer.h b/include/qemu/timer.h > index 85bc6eb00b21..8941ddea8242 100644 > --- a/include/qemu/timer.h > +++ b/include/qemu/timer.h > @@ -1006,6 +1006,22 @@ static inline int64_t cpu_get_host_ticks(void) > } > #endif > > +#if defined(__aarch64__) > +static inline uint32_t cpu_get_host_tick_frequency(void) > +{ > + uint64_t frq; > + asm volatile("mrs %0, cntfrq_el0" : "=r" (frq)); > + return frq; > +} > +#elif defined(__arm__) > +static inline uint32_t cpu_get_host_tick_frequency(void) > +{ > + uint32_t frq; > + asm volatile("mrc p15, 0, %0, c14, c0, 0" : "=r" (frq)); > + return frq; > +} > +#endif Don't we want to know what the guest counter frequency is, not the host counter frequency? That is, I would have expected that we get this value via doing a KVM ONE_REG ioctl to ask the kernel what the guest cntfrq is. Are we using the host value on the assumption that the guest might have misprogrammed their copy of the register? thanks -- PMM From MAILER-DAEMON Tue Dec 10 10:48:08 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1iehk8-00055Y-1p for mharc-qemu-arm@gnu.org; Tue, 10 Dec 2019 10:48:08 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:45556) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iehk4-00052O-PK for qemu-arm@nongnu.org; Tue, 10 Dec 2019 10:48:05 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1iehk3-00045g-22 for qemu-arm@nongnu.org; Tue, 10 Dec 2019 10:48:03 -0500 Received: from us-smtp-delivery-1.mimecast.com ([207.211.31.120]:35772 helo=us-smtp-1.mimecast.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1iehk2-00044t-VU for qemu-arm@nongnu.org; Tue, 10 Dec 2019 10:48:03 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1575992882; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=VhYuL2Sq9yxjpF+tZAOFmq1iyF/dfLOzaDkTF2Fc/GA=; b=N5y3xMU62O1O4QEfJvHH2bnozB3VU6fRh82LgNVymaqxNMLx8V/220GS1j9s74sXVQ+GR/ W2b4fea732LP37nLPxoEiX9KhHes8rDLpGi8sD6twE5AtgPQI65ahNs6uIEmRe8SQiK39k 7fa/LIYU/iQuJmkLQVGNgWWJp/w0Ybo= Received: from mimecast-mx01.redhat.com (mimecast-mx01.redhat.com [209.132.183.4]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-427-Vsc1rnNRMo-k8cxV4xnNCw-1; Tue, 10 Dec 2019 10:47:56 -0500 Received: from smtp.corp.redhat.com (int-mx02.intmail.prod.int.phx2.redhat.com [10.5.11.12]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx01.redhat.com (Postfix) with ESMTPS id 975FE100E0D9; Tue, 10 Dec 2019 15:47:54 +0000 (UTC) Received: from ovpn-205-189.brq.redhat.com (ovpn-205-189.brq.redhat.com [10.40.205.189]) by smtp.corp.redhat.com (Postfix) with ESMTPS id 56F1660BE0; Tue, 10 Dec 2019 15:47:52 +0000 (UTC) Message-ID: Subject: Re: [PATCH v1 0/5] target/arm/kvm: Provide an option to adjust virtual time From: Andrea Bolognani To: Andrew Jones Cc: Peter Maydell , Marc Zyngier , qemu-arm , Richard Henderson , bijan.mottahedeh@oracle.com, QEMU Developers Date: Tue, 10 Dec 2019 16:47:49 +0100 In-Reply-To: <20191210143311.4sen6blhfhzop6zw@kamzik.brq.redhat.com> References: <20191016143410.5023-1-drjones@redhat.com> <20191206155327.7adiyjjkjh56mg2t@kamzik.brq.redhat.com> <596d07e933cb4da48dbba5b492e81a2438e78a2f.camel@redhat.com> <20191210110531.psjzlikir2ep2omo@kamzik.brq.redhat.com> <20191210133254.22vcpvr3eabcnthe@kamzik.brq.redhat.com> <29add42daba074ab5bdbd462b2d377115fec7c3c.camel@redhat.com> <20191210143311.4sen6blhfhzop6zw@kamzik.brq.redhat.com> User-Agent: Evolution 3.34.2 (3.34.2-1.fc31) MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.79 on 10.5.11.12 X-MC-Unique: Vsc1rnNRMo-k8cxV4xnNCw-1 X-Mimecast-Spam-Score: 0 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: 7bit X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 207.211.31.120 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 10 Dec 2019 15:48:07 -0000 On Tue, 2019-12-10 at 15:33 +0100, Andrew Jones wrote: > On Tue, Dec 10, 2019 at 03:21:02PM +0100, Andrea Bolognani wrote: > > I agree with everything except the naming: why would > > > > kvm-no-adjvtime=off vtime is adjusted (default) > > kvm-no-adjvtime=on vtime is not adjusted > > > > be better than > > > > kvm-adjvtime=on vtime is adjusted (default) > > kvm-adjvtime=off vtime is not adjusted > > > > ? Both offer the exact same amount of flexibility, but the latter has > > the advantage of not introducing any unwieldy double negatives. > > A default of 'off' == 0 means not setting anything at all. There's > already precedent for 'kvm-no*' prefixed cpu features, > > kvm-no-smi-migration > kvm-nopiodelay Sorry, I'm not sure I understand. Do you mean that the array where you store CPU features is 0-inizialized, so it's more convenient to have off (0) as the default because it means you don't have to touch it beforehand? Or something different? -- Andrea Bolognani / Red Hat / Virtualization From MAILER-DAEMON Tue Dec 10 10:54:26 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1iehqE-0007ck-Mt for mharc-qemu-arm@gnu.org; Tue, 10 Dec 2019 10:54:26 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:46776) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iehqB-0007aw-V6 for qemu-arm@nongnu.org; Tue, 10 Dec 2019 10:54:24 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1iehqA-0008JK-RR for qemu-arm@nongnu.org; Tue, 10 Dec 2019 10:54:23 -0500 Received: from mail-oi1-x241.google.com ([2607:f8b0:4864:20::241]:41119) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1iehqA-0008Ix-Lo for qemu-arm@nongnu.org; Tue, 10 Dec 2019 10:54:22 -0500 Received: by mail-oi1-x241.google.com with SMTP id i1so10208770oie.8 for ; Tue, 10 Dec 2019 07:54:22 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=qkvXH55G+iv0yZ4areBM4JInh6uKCzUpqm+YCgqvJbg=; b=KuFGnYt/t268MsTXofoQshaYJr/nAShbCt+AOCnnzl96R8uRChzhjFXZN5CMtqb7Xr pxY21NtQsyPc8qWeSj36a/J7SC56DecORnLahkTeDyelNgVzR8wtuLGlvptJLsT1DWnY b+37dw4vio4cT+HWLqfeh+BTveDbM/SkVpXUtH+gdvfEuJcquhdK/8O9UF2iA/Jr5onx OsIhWk+j3bD7fxvViXxNgHWZN2+7n5hzdwHT1lDLjXeNrqTqd0MpYE6ADUTDAYATeM6Y GYx/j74CL0yipW+ERJ5B/GRI+HakWcD9/S+FgHXY5Ae4woqoc+itArFHecIwL3MtLEx2 15Ug== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=qkvXH55G+iv0yZ4areBM4JInh6uKCzUpqm+YCgqvJbg=; b=ZnEPYBOl6OPB1F7iFfqdAOQezpZsxlyZDug1sutfh4UN/8rY2mr+mzT4ongcfZ3xNo XG5No1XIdP9Y1gBUaT/aIgje9BJFA8TLPvqR4ztHItJxNkHBfBjSNRELd4PaLf4a3hBJ z4w8ZwBg73/mA/a/v2iEIUchKFJt55qvolIpUWU/vhYDb7/SFqk7qu6Bc19TkCT9HZ0O SgIAY6tmda/oNAuSxwxQRZ2kxQqar3QY+t8rsD9UsmcUdVpHS2YqVKAns2iUwJ2stxIx kiLTXftCpUXLqngvYHu2QD+DUxmfmWbdaC3m/ASoauXqxrYVM22u+k5Z44ljg4VTZOoK b7vA== X-Gm-Message-State: APjAAAXn4btt4LScg9712dt0kVN29GVJnbduKQ4g2LwaZU1DeDSGxzM/ K4tj4pMARajCMl9t3xGWEe/7hVxRfTYldUUZxgBWhQ== X-Google-Smtp-Source: APXvYqxlLGNk8aLVogO0zZkyoe+jfnwIR09cEFRD/p9gfWAP77vgqEJcSYX924cfMdQy/KubluT2raGTjGSR2xd8veI= X-Received: by 2002:aca:3182:: with SMTP id x124mr4651766oix.170.1575993261791; Tue, 10 Dec 2019 07:54:21 -0800 (PST) MIME-Version: 1.0 References: <20191016143410.5023-1-drjones@redhat.com> <20191016143410.5023-4-drjones@redhat.com> In-Reply-To: <20191016143410.5023-4-drjones@redhat.com> From: Peter Maydell Date: Tue, 10 Dec 2019 15:54:11 +0000 Message-ID: Subject: Re: [PATCH v1 3/5] target/arm/kvm: Implement cpu feature kvm-adjvtime To: Andrew Jones Cc: QEMU Developers , qemu-arm , Richard Henderson , bijan.mottahedeh@oracle.com, Marc Zyngier Content-Type: text/plain; charset="UTF-8" X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::241 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 10 Dec 2019 15:54:25 -0000 On Wed, 16 Oct 2019 at 15:34, Andrew Jones wrote: > > When kvm-adjvtime is enabled the guest's cntvct[_el0] won't count > the time when the VM is stopped. That time is skipped by updating > cntvoff[_el2] on each transition to vm_running using the current > QEMU_CLOCK_VIRTUAL time. QEMU_CLOCK_VIRTUAL only ticks when the VM > is running. > > This patch only provides the implementation. A subsequent patch > will provide the CPU property allowing the feature to be enabled. > +void kvm_arm_set_virtual_time(CPUState *cs) > +{ > + uint64_t cnt; > + struct kvm_one_reg reg = { > + .id = KVM_REG_ARM_TIMER_CNT, > + .addr = (uintptr_t)&cnt, > + }; > + int ret; > + > + cnt = muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), > + cpu_get_host_tick_frequency(), > + NANOSECONDS_PER_SECOND); > + > + ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, ®); > + if (ret) { > + error_report("Failed to set KVM_REG_ARM_TIMER_CNT"); > + abort(); > + } The commit message (and the doc comment for this function) say that we're updating the counter offset, but the kvm_one_reg operation here is updating the timer count (and relying on the kernel's handling of "if we update the timer count implement that by changing the offset"). That seems a bit confusing. Would it be possible to implement "cntvct should not change while the VM is stopped" with "read cntvct when the VM stops, and just write back that value when the VM is restarted", rather than "write back a new value calculated from QEMU_CLOCK_VIRTUAL"? If I understand commit 00f4d64ee76e873be8 correctly, that's basically how x86 is doing it. It would also let you sidestep the need to know the tick frequency of the counter. thanks -- PMM From MAILER-DAEMON Tue Dec 10 11:08:38 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1iei3y-00057c-Lx for mharc-qemu-arm@gnu.org; Tue, 10 Dec 2019 11:08:38 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:49794) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iei3v-00055j-QE for qemu-arm@nongnu.org; Tue, 10 Dec 2019 11:08:36 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1iei3t-00068W-90 for qemu-arm@nongnu.org; Tue, 10 Dec 2019 11:08:34 -0500 Received: from us-smtp-delivery-1.mimecast.com ([207.211.31.120]:25177 helo=us-smtp-1.mimecast.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1iei3t-00067z-5e for qemu-arm@nongnu.org; Tue, 10 Dec 2019 11:08:33 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1575994112; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=omvEPFgMa0ImghPBOD0QaB8/kVCMWZVlsLSkdCnszF4=; b=J9/xtnlVc6uYxfk9Q/xvovWVwqaj/zqkCRF2ukMAMws5eGbzi2jKVwSC4AdnMEYqn0AIm9 2IxKMMQ5m9Kg7BrqH7ikgP/8KHF1wn1RFtaVTQyko7UPCLpnq7ALZNZd+SeZzivvhD1e8e zx3/QgFKIdmlkC4jvqHfR4A4E4VOjWY= Received: from mimecast-mx01.redhat.com (mimecast-mx01.redhat.com [209.132.183.4]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-41-qYuj1O5nOgqp6Uz9pr90jA-1; Tue, 10 Dec 2019 11:08:30 -0500 Received: from smtp.corp.redhat.com (int-mx06.intmail.prod.int.phx2.redhat.com [10.5.11.16]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx01.redhat.com (Postfix) with ESMTPS id 3148610054E3; Tue, 10 Dec 2019 16:08:29 +0000 (UTC) Received: from kamzik.brq.redhat.com (unknown [10.43.2.160]) by smtp.corp.redhat.com (Postfix) with ESMTPS id 811FD5C1B0; Tue, 10 Dec 2019 16:08:27 +0000 (UTC) Date: Tue, 10 Dec 2019 17:08:25 +0100 From: Andrew Jones To: Andrea Bolognani Cc: Peter Maydell , Marc Zyngier , qemu-arm , Richard Henderson , bijan.mottahedeh@oracle.com, QEMU Developers Subject: Re: [PATCH v1 0/5] target/arm/kvm: Provide an option to adjust virtual time Message-ID: <20191210160825.ioah26u36eu2i3z2@kamzik.brq.redhat.com> References: <20191206155327.7adiyjjkjh56mg2t@kamzik.brq.redhat.com> <596d07e933cb4da48dbba5b492e81a2438e78a2f.camel@redhat.com> <20191210110531.psjzlikir2ep2omo@kamzik.brq.redhat.com> <20191210133254.22vcpvr3eabcnthe@kamzik.brq.redhat.com> <29add42daba074ab5bdbd462b2d377115fec7c3c.camel@redhat.com> <20191210143311.4sen6blhfhzop6zw@kamzik.brq.redhat.com> MIME-Version: 1.0 In-Reply-To: X-Scanned-By: MIMEDefang 2.79 on 10.5.11.16 X-MC-Unique: qYuj1O5nOgqp6Uz9pr90jA-1 X-Mimecast-Spam-Score: 0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: quoted-printable Content-Disposition: inline X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 207.211.31.120 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 10 Dec 2019 16:08:37 -0000 On Tue, Dec 10, 2019 at 04:47:49PM +0100, Andrea Bolognani wrote: > On Tue, 2019-12-10 at 15:33 +0100, Andrew Jones wrote: > > On Tue, Dec 10, 2019 at 03:21:02PM +0100, Andrea Bolognani wrote: > > > I agree with everything except the naming: why would > > >=20 > > > kvm-no-adjvtime=3Doff vtime is adjusted (default) > > > kvm-no-adjvtime=3Don vtime is not adjusted > > >=20 > > > be better than > > >=20 > > > kvm-adjvtime=3Don vtime is adjusted (default) > > > kvm-adjvtime=3Doff vtime is not adjusted > > >=20 > > > ? Both offer the exact same amount of flexibility, but the latter has > > > the advantage of not introducing any unwieldy double negatives. > >=20 > > A default of 'off' =3D=3D 0 means not setting anything at all. There's > > already precedent for 'kvm-no*' prefixed cpu features, > >=20 > > kvm-no-smi-migration > > kvm-nopiodelay >=20 > Sorry, I'm not sure I understand. Do you mean that the array where > you store CPU features is 0-inizialized, so it's more convenient to > have off (0) as the default because it means you don't have to touch > it beforehand? Or something different? > Right. The CPU feature flag (a boolean member of the CPU state) will be zero by default because C. It's not a big deal, though, because the property default can easily be set to true while it's added to a cpu type. I don't have a strong enough opinion about kvm-adjvtime vs. kvm-no-adjvtime to insist one way or another. I agree double inversions are easier to mess up, but I also like the way the '-no-' better communicates that the default is [probably] 'yes'. All interested parties, please vote. I'll be sending v2 soon and I can call this thing anything the majority (or the dominate minority) prefer. Thanks, drew From MAILER-DAEMON Tue Dec 10 11:11:12 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1iei6S-0006VQ-4s for mharc-qemu-arm@gnu.org; Tue, 10 Dec 2019 11:11:12 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:50342) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iei6P-0006UK-PE for qemu-arm@nongnu.org; Tue, 10 Dec 2019 11:11:10 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1iei6O-00070t-NO for qemu-arm@nongnu.org; Tue, 10 Dec 2019 11:11:09 -0500 Received: from us-smtp-1.mimecast.com ([205.139.110.61]:60379 helo=us-smtp-delivery-1.mimecast.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1iei6O-00070J-Jd for qemu-arm@nongnu.org; Tue, 10 Dec 2019 11:11:08 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1575994267; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=RL1wQzjB7ueQUertKiln5v+WwAvPFcgduWuDddphhwE=; b=FcVlzrbwu5/V1u1OmZm1IcNsjqEC0sgDLr8pcFpNKiotaRBlLNE87GLa0xGqjQXl0l76Nv d4fE9AdORDFjbtJPWUgLIqLqAfw3ujWjkR5TFS2O769LDGSMW7AI4oQr2SxWs/h2Avtbx3 o0gg8NVdR74XbAaxv8E+G04LAQNtoMg= Received: from mimecast-mx01.redhat.com (mimecast-mx01.redhat.com [209.132.183.4]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-102-TZK-Us21OFCP-9rmFixakg-1; Tue, 10 Dec 2019 11:11:04 -0500 Received: from smtp.corp.redhat.com (int-mx06.intmail.prod.int.phx2.redhat.com [10.5.11.16]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx01.redhat.com (Postfix) with ESMTPS id EF551803BC4; Tue, 10 Dec 2019 16:11:02 +0000 (UTC) Received: from kamzik.brq.redhat.com (unknown [10.43.2.160]) by smtp.corp.redhat.com (Postfix) with ESMTPS id A2E5A5C21B; Tue, 10 Dec 2019 16:11:01 +0000 (UTC) Date: Tue, 10 Dec 2019 17:10:58 +0100 From: Andrew Jones To: Peter Maydell Cc: Marc Zyngier , qemu-arm , Richard Henderson , QEMU Developers , bijan.mottahedeh@oracle.com Subject: Re: [PATCH v1 3/5] target/arm/kvm: Implement cpu feature kvm-adjvtime Message-ID: <20191210161058.f4ysoukuhf6k62xl@kamzik.brq.redhat.com> References: <20191016143410.5023-1-drjones@redhat.com> <20191016143410.5023-4-drjones@redhat.com> MIME-Version: 1.0 In-Reply-To: X-Scanned-By: MIMEDefang 2.79 on 10.5.11.16 X-MC-Unique: TZK-Us21OFCP-9rmFixakg-1 X-Mimecast-Spam-Score: 0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: quoted-printable Content-Disposition: inline X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 205.139.110.61 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 10 Dec 2019 16:11:10 -0000 On Tue, Dec 10, 2019 at 03:54:11PM +0000, Peter Maydell wrote: > On Wed, 16 Oct 2019 at 15:34, Andrew Jones wrote: > > > > When kvm-adjvtime is enabled the guest's cntvct[_el0] won't count > > the time when the VM is stopped. That time is skipped by updating > > cntvoff[_el2] on each transition to vm_running using the current > > QEMU_CLOCK_VIRTUAL time. QEMU_CLOCK_VIRTUAL only ticks when the VM > > is running. > > > > This patch only provides the implementation. A subsequent patch > > will provide the CPU property allowing the feature to be enabled. >=20 >=20 > > +void kvm_arm_set_virtual_time(CPUState *cs) > > +{ > > + uint64_t cnt; > > + struct kvm_one_reg reg =3D { > > + .id =3D KVM_REG_ARM_TIMER_CNT, > > + .addr =3D (uintptr_t)&cnt, > > + }; > > + int ret; > > + > > + cnt =3D muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), > > + cpu_get_host_tick_frequency(), > > + NANOSECONDS_PER_SECOND); > > + > > + ret =3D kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, ®); > > + if (ret) { > > + error_report("Failed to set KVM_REG_ARM_TIMER_CNT"); > > + abort(); > > + } >=20 > The commit message (and the doc comment for this function) > say that we're updating the counter offset, but the > kvm_one_reg operation here is updating the timer count > (and relying on the kernel's handling of "if we update > the timer count implement that by changing the offset"). > That seems a bit confusing. >=20 > Would it be possible to implement "cntvct should not change while the > VM is stopped" with "read cntvct when the VM stops, and just write > back that value when the VM is restarted", rather than > "write back a new value calculated from QEMU_CLOCK_VIRTUAL"? > If I understand commit 00f4d64ee76e873be8 correctly, that's > basically how x86 is doing it. It would also let you sidestep > the need to know the tick frequency of the counter. That's definitely worth some experimenting. Will do. Thanks, drew From MAILER-DAEMON Tue Dec 10 11:32:06 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1ieiQg-0007Bi-JI for mharc-qemu-arm@gnu.org; Tue, 10 Dec 2019 11:32:06 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:55992) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ieiQd-00079w-Or for qemu-arm@nongnu.org; Tue, 10 Dec 2019 11:32:04 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ieiQc-0007gd-Lr for qemu-arm@nongnu.org; Tue, 10 Dec 2019 11:32:03 -0500 Received: from mail-wr1-x442.google.com ([2a00:1450:4864:20::442]:42458) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ieiQc-0007fy-E8 for qemu-arm@nongnu.org; Tue, 10 Dec 2019 11:32:02 -0500 Received: by mail-wr1-x442.google.com with SMTP id a15so20801589wrf.9 for ; Tue, 10 Dec 2019 08:32:01 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=date:from:to:cc:subject:message-id:references:mime-version :content-disposition:in-reply-to; bh=yFJvEW6PL4Wk9dE8Q8kwfKDDjO3R418aBjP/+OttZ5A=; b=QL3B9wwzzN9AcFnvQWPzk69I2vS9i13JtB5K3ng8EPET4KlE2XDjpWJ2fNy2dAbjNQ dHflE7wG8NvhZUEAU+fT630hhR7x70Xr7zTrYIOrgfefmzOhrf7kPav7fqTy/RzNILrA 3bCH0f6ptEdJE+iPzvDm1Bb3BcwUo+Eg7lTaadOOOk6TQPeIVy5vIZ11epYqvV5pHM5w YpbBaDswRn29senin0FPUedkNbM794QSWPO2h4Pgr2eoAMVZrfrKrDrO3hjbpFU3rg+X Jr4MZkuLZ1y8fpfhdhg6JDdB8IFXgH5lFw7A+fGmuqMf7J/YfGIlr/oSJB2X2mT8iStN 0nBQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:in-reply-to; bh=yFJvEW6PL4Wk9dE8Q8kwfKDDjO3R418aBjP/+OttZ5A=; b=d/xFjwBBuEh4QjBav1ue5JVzr7puyQX9CF5v8L6Fu5HEwHRIWTNU10pxMtRvETm4e/ CWaPRQEg59bnSoayCNLZ/qIQx4OsXGwNRMdgWgTYknV4YxnCuB+PizTfJ7PT5JO/WGip RiuOCZTcf/H5TmCm1kLs7S8uqG+XLnv7sbIF5Ev4lfbsdy62e9cOqLdtuDjxIHWHWqGN MbXJYklaWBaPxevSANKMyBsh5i0kUN36g7sv5C2e65XfBvI/Kc4FmpEfcDIoMW7X5e3c EwBUgsU3b4E8I6D4EQxSsIQWeM3UofMWvdNg8/9sHwnO3mxIbMkLTB/A/jBgSnPI6Y3E QgGw== X-Gm-Message-State: APjAAAVOR4wna9V7sRQ1zZpwUfkGtnwRLtoLwdDmwOvavjX9DYFBQqAG l1btRE2CKM763lfaj/GGJpiNMQ== X-Google-Smtp-Source: APXvYqzjNyutGRXO8/G4WT7haieLoxlV0LaBYWCWz9kz1jBfJ5Fem0xDlkK1Isa0r6cI50zPINvIAA== X-Received: by 2002:adf:db41:: with SMTP id f1mr4380682wrj.392.1575995520619; Tue, 10 Dec 2019 08:32:00 -0800 (PST) Received: from myrica (adsl-84-227-176-239.adslplus.ch. [84.227.176.239]) by smtp.gmail.com with ESMTPSA id x17sm3807881wrt.74.2019.12.10.08.31.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 10 Dec 2019 08:31:59 -0800 (PST) Date: Tue, 10 Dec 2019 17:31:55 +0100 From: Jean-Philippe Brucker To: Eric Auger Cc: eric.auger.pro@gmail.com, qemu-devel@nongnu.org, qemu-arm@nongnu.org, peter.maydell@linaro.org, mst@redhat.com, armbru@redhat.com, jean-philippe.brucker@arm.com, bharatb.linux@gmail.com, yang.zhong@intel.com, dgilbert@redhat.com, quintela@redhat.com, kevin.tian@intel.com, peterx@redhat.com, tnowicki@marvell.com Subject: Re: [PATCH for-5.0 v11 02/20] virtio-iommu: Add skeleton Message-ID: <20191210163155.GA277340@myrica> References: <20191122182943.4656-1-eric.auger@redhat.com> <20191122182943.4656-3-eric.auger@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20191122182943.4656-3-eric.auger@redhat.com> X-TUID: HBRCdcJechMs X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::442 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 10 Dec 2019 16:32:05 -0000 Hi Eric, On Fri, Nov 22, 2019 at 07:29:25PM +0100, Eric Auger wrote: > +typedef struct VirtIOIOMMU { > + VirtIODevice parent_obj; > + VirtQueue *req_vq; > + VirtQueue *event_vq; > + struct virtio_iommu_config config; > + uint64_t features; > + uint64_t acked_features; We already have guest_features in the parent object. > + GHashTable *as_by_busptr; > + IOMMUPciBus *as_by_bus_num[IOMMU_PCI_BUS_MAX]; Doesn't seem used anymore. Thanks, Jean > + PCIBus *primary_bus; > + GTree *domains; > + QemuMutex mutex; > + GTree *endpoints; > +} VirtIOIOMMU; > + > +#endif > -- > 2.20.1 > > From MAILER-DAEMON Tue Dec 10 11:32:46 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1ieiRJ-0007qL-L2 for mharc-qemu-arm@gnu.org; Tue, 10 Dec 2019 11:32:45 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:56199) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ieiRF-0007nn-GH for qemu-arm@nongnu.org; Tue, 10 Dec 2019 11:32:43 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ieiRD-0007zv-G4 for qemu-arm@nongnu.org; Tue, 10 Dec 2019 11:32:41 -0500 Received: from mail-wm1-x344.google.com ([2a00:1450:4864:20::344]:38441) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ieiRD-0007zC-AB for qemu-arm@nongnu.org; Tue, 10 Dec 2019 11:32:39 -0500 Received: by mail-wm1-x344.google.com with SMTP id p17so3904870wmi.3 for ; Tue, 10 Dec 2019 08:32:38 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=date:from:to:cc:subject:message-id:references:mime-version :content-disposition:in-reply-to; bh=qgVznmekNB3MfWLf8bBgjLOIH1R7Lmqq4nQfM+upz3U=; b=k2qqHrXpr77w0dy+IsuoZDZBR/zO1WWMkmuM0lgyEBcYt9nGmQFMIP0tKz7vAakfPl mj6EEnUORMrkxg1qYTKoAazJMitEMrlle4erVE86cUl7DPGfuUAGqBiqdPNF1K/LfJF+ P4dmS1Bv1PLgJ7bdMv7iZOeUU1/Ex90kE6EkFf6eSgkovI0HowIC/TGoqP+Uj/0Y2m+Z USuRSdzIWqMKIIf5IwAWRTGPFnHtH233VgOwvj8mkK9nv2jJq3vx5z4UIC3j9TrzSaIY 9fWjHx8MXWKTQUc5DpkTy4jc81F1k8P+MHc+hHlOCT/bx4kgQkb0nvGN5vDPv1UnDiAL hstQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:in-reply-to; bh=qgVznmekNB3MfWLf8bBgjLOIH1R7Lmqq4nQfM+upz3U=; b=Qt13MywR3VQEecV64XkElqF3tWwirnsbsUhYwo8YL1viH9a6DKf6NJg4nNtMYtaLzA hIXFox9OtxAa+GRpQkR9olqoy20TMaU4FWPeAK3ohs1jjs98N1UFu9vAots/M2Ez4lHI tnk0NLjYU9qYHKkxQQ9h1eFtF9L0rNaV/VNH6Thmh+A6sMJ4LE5M/dQoXshhuF93Wsev 4dBmOeUNeHxXXfxHQPIfTiEzCh0wcFao3YPfnOihNf3eGbYpBI0zT0SsJ6sWDAttPKfS /dstnXRVDqzI+UMb422P0Z9afn5K+3iY4HdLDy7MabZOO1BlNe2vwRVa5zgbIBdPxF7F Yt9g== X-Gm-Message-State: APjAAAVvW77uZ/BWkDyOgzoo9DgEuhefl1+i7vI+5eZNKIgrvD8ksa8D ciomiEsrakcWxXMnYNqtE7/FGw== X-Google-Smtp-Source: APXvYqyltAwOreZoQ/omCzEQQ5FjH/XyA8RdQZXB56rgqB5k2s5ytj78cTlWZV+vkONaZtKV/jQjag== X-Received: by 2002:a05:600c:2301:: with SMTP id 1mr6485530wmo.147.1575995557913; Tue, 10 Dec 2019 08:32:37 -0800 (PST) Received: from myrica (adsl-84-227-176-239.adslplus.ch. [84.227.176.239]) by smtp.gmail.com with ESMTPSA id u10sm3615307wmd.1.2019.12.10.08.32.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 10 Dec 2019 08:32:37 -0800 (PST) Date: Tue, 10 Dec 2019 17:32:33 +0100 From: Jean-Philippe Brucker To: Eric Auger Cc: eric.auger.pro@gmail.com, qemu-devel@nongnu.org, qemu-arm@nongnu.org, peter.maydell@linaro.org, mst@redhat.com, armbru@redhat.com, jean-philippe.brucker@arm.com, bharatb.linux@gmail.com, yang.zhong@intel.com, dgilbert@redhat.com, quintela@redhat.com, kevin.tian@intel.com, peterx@redhat.com, tnowicki@marvell.com Subject: Re: [PATCH for-5.0 v11 03/20] virtio-iommu: Decode the command payload Message-ID: <20191210163233.GB277340@myrica> References: <20191122182943.4656-1-eric.auger@redhat.com> <20191122182943.4656-4-eric.auger@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20191122182943.4656-4-eric.auger@redhat.com> X-TUID: ajVuZQQERWm/ X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::344 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 10 Dec 2019 16:32:43 -0000 On Fri, Nov 22, 2019 at 07:29:26PM +0100, Eric Auger wrote: > This patch adds the command payload decoding and > introduces the functions that will do the actual > command handling. Those functions are not yet implemented. > > Signed-off-by: Eric Auger Reviewed-by: Jean-Philippe Brucker Which isn't worth much since I don't have prior QEMU experience but I did stare at this code for a while and work on future extensions. Thanks, Jean From MAILER-DAEMON Tue Dec 10 11:34:50 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1ieiTK-00023w-16 for mharc-qemu-arm@gnu.org; Tue, 10 Dec 2019 11:34:50 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:56694) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ieiTH-00021U-ES for qemu-arm@nongnu.org; Tue, 10 Dec 2019 11:34:48 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ieiTG-0001Rd-Fe for qemu-arm@nongnu.org; Tue, 10 Dec 2019 11:34:47 -0500 Received: from mail-wm1-x344.google.com ([2a00:1450:4864:20::344]:51178) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ieiTG-0001Na-8N for qemu-arm@nongnu.org; Tue, 10 Dec 2019 11:34:46 -0500 Received: by mail-wm1-x344.google.com with SMTP id p9so3984374wmg.0 for ; Tue, 10 Dec 2019 08:34:46 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=date:from:to:cc:subject:message-id:references:mime-version :content-disposition:in-reply-to; bh=nr9qD4DaDvJHHdIuwYMg0Ovc1bfT2/hPbW+c8+9Fprs=; b=WvMDtpxa2/IRtVWRf8WkOpm5ElUVivgCV1sDbwTLx2o70NhfnVP78ng9rbfwZgnmIG wOPE8CZyTf0d/FHReVJkddPj3ZcYKd2PdwPCZdiI1+dbl1UtGWzeoMN4prS/kXrDMhFd JaOMMTFNu3W4tAuUJFiuI+bRgnGEQ/PnFnNjGwIHRVimVYT6bUQAgb8plNFuGkSE56AQ wzkWZeGkDb4L1SBBqjrVgOE/16dBzUPb+YdnJhoCMAV0e9cQzcmWvyzeJZazjPeGWr1Y TTjrmUMSnr+vhazzFdgAaZ2l3nA966C6LituUenMUacLMHbP1Z4HNHyKB3DpxHxQEUvu ms6Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:in-reply-to; bh=nr9qD4DaDvJHHdIuwYMg0Ovc1bfT2/hPbW+c8+9Fprs=; b=eW0FTlX1Bpad/PYuThkmBD3tPjdwL28q58I/yu3qq1Js9fYUaAER3jSLT9ivu9Wlpj 5MDW2cHFCYC7UBooEXr1T6hruek7s0Fc4atzjkA+iwICTk+dgPcakALDYF+gByLtWNpZ Fh3yx/c40p2gWQ0b+O080s3fJnvlHNnbwhLNBCgJ/hkiFzGPyqaaZ+IUhzPCtWN5bRrk YYbCXyQ4inw80jRlICMMxHe+HrB0e5DWl+SmFsL3TTjyPOM9u6INk4pjZOnAPG7ivKbU z373rYx1khihym3Yyd1oTIurz3kzsZIT1J84pTmpCbC5jLV9ibruvHN6Xv4QDHUgVmnU 2tvQ== X-Gm-Message-State: APjAAAVxxhnKVzwct4XC7WiHg1NDky6JSXlo+q2hr0H6dM1U5+wBJ09H ZuEtyO520R8qCm8rgh4jLio6Nw== X-Google-Smtp-Source: APXvYqxPconFr5AK4By59wJ2vTLjsF91W7jn0hl9Ry8Q5p6TIY4Ut5t41QS5QyV6raIk1Z+sUtBfDQ== X-Received: by 2002:a1c:9602:: with SMTP id y2mr6185448wmd.23.1575995685380; Tue, 10 Dec 2019 08:34:45 -0800 (PST) Received: from myrica (adsl-84-227-176-239.adslplus.ch. [84.227.176.239]) by smtp.gmail.com with ESMTPSA id g17sm3504156wmc.37.2019.12.10.08.34.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 10 Dec 2019 08:34:44 -0800 (PST) Date: Tue, 10 Dec 2019 17:34:40 +0100 From: Jean-Philippe Brucker To: Eric Auger Cc: eric.auger.pro@gmail.com, qemu-devel@nongnu.org, qemu-arm@nongnu.org, peter.maydell@linaro.org, mst@redhat.com, armbru@redhat.com, jean-philippe.brucker@arm.com, bharatb.linux@gmail.com, yang.zhong@intel.com, dgilbert@redhat.com, quintela@redhat.com, kevin.tian@intel.com, peterx@redhat.com, tnowicki@marvell.com Subject: Re: [PATCH for-5.0 v11 04/20] virtio-iommu: Add the iommu regions Message-ID: <20191210163440.GC277340@myrica> References: <20191122182943.4656-1-eric.auger@redhat.com> <20191122182943.4656-5-eric.auger@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20191122182943.4656-5-eric.auger@redhat.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::344 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 10 Dec 2019 16:34:49 -0000 Two small things below, but looks good overall Reviewed-by: Jean-Philippe Brucker On Fri, Nov 22, 2019 at 07:29:27PM +0100, Eric Auger wrote: > +static AddressSpace *virtio_iommu_find_add_as(PCIBus *bus, void *opaque, > + int devfn) > +{ > + VirtIOIOMMU *s = opaque; > + IOMMUPciBus *sbus = g_hash_table_lookup(s->as_by_busptr, bus); > + static uint32_t mr_index; > + IOMMUDevice *sdev; > + > + if (!sbus) { > + sbus = g_malloc0(sizeof(IOMMUPciBus) + > + sizeof(IOMMUDevice *) * IOMMU_PCI_DEVFN_MAX); > + sbus->bus = bus; > + g_hash_table_insert(s->as_by_busptr, bus, sbus); > + } > + > + sdev = sbus->pbdev[devfn]; > + if (!sdev) { > + char *name = g_strdup_printf("%s-%d-%d", > + TYPE_VIRTIO_IOMMU_MEMORY_REGION, > + mr_index++, devfn); > + sdev = sbus->pbdev[devfn] = g_malloc0(sizeof(IOMMUDevice)); > + > + sdev->viommu = s; > + sdev->bus = bus; > + sdev->devfn = devfn; It might be better to store the endpoint ID in IOMMUDevice, then you could get rid of virtio_iommu_get_sid(), and remove a tiny bit of overhead in virtio_iommu_translate(). But I doubt it's significant. [...] > +static const TypeInfo virtio_iommu_memory_region_info = { > + .parent = TYPE_IOMMU_MEMORY_REGION, > + .name = TYPE_VIRTIO_IOMMU_MEMORY_REGION, > + .class_init = virtio_iommu_memory_region_class_init, > +}; > + > + nit: newline. Thanks, Jean From MAILER-DAEMON Tue Dec 10 11:37:26 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1ieiVq-0005JR-R8 for mharc-qemu-arm@gnu.org; Tue, 10 Dec 2019 11:37:26 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:57314) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ieiVo-0005HK-9Q for qemu-arm@nongnu.org; Tue, 10 Dec 2019 11:37:25 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ieiVm-00028n-RH for qemu-arm@nongnu.org; Tue, 10 Dec 2019 11:37:24 -0500 Received: from mail-wr1-x444.google.com ([2a00:1450:4864:20::444]:35025) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ieiVm-00028R-Kh for qemu-arm@nongnu.org; Tue, 10 Dec 2019 11:37:22 -0500 Received: by mail-wr1-x444.google.com with SMTP id g17so20869257wro.2 for ; Tue, 10 Dec 2019 08:37:22 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=date:from:to:cc:subject:message-id:references:mime-version :content-disposition:in-reply-to; bh=TS8bXKSl6jHU0cVwDFmZM85QEliVGmGHepmEnSkPSts=; b=W8rMi0AcwZDJ7di99vHnVlD8Z27RaZmDdQYYYvq7WANbmGIqPMGraHnrAGzOVCr2bo pvo4D0xqVMrF2JedG0nvR9BjT+1tX5FYi+89cCSYjfBBrmi1D//M/ymGN0cLCdIeuytW TpU0G/4Irrhzcirtznobbdf2mfhF9Ty6//ItnmrtUvFJMYYISK8z2WxuEH5Rz3OBEVQM JL7tjrr0ttDDYd+jC1mk8SuGsmxJk5LWXS9KO7yBTBsXQofUH8UAcx0wHcNYS5RAwiKt zO6xx46yPIV17dQAXw5jBajLZo9VnNy8l4hPTTdhHyWfsy34oR2vmbvEcWIsaaR+PqWl Zusg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:in-reply-to; bh=TS8bXKSl6jHU0cVwDFmZM85QEliVGmGHepmEnSkPSts=; b=tNqxHE26mBng3OVTJ5dl2cVQ8iynu1bquHtumELnQnjij27RLH1vP4y7KxFTZhLGep upscDvZ+ng3X/4l7TOWVmKQv5+KBnyFCCpn27wopcfS+0hE45+2nevNdBqOg8EluhIbg c/705EPb89xsh5JzMerQ5RQHyaYJkqHlSLynyV4TRtoQDn76GknL8LakaZfWcrih0Jdi kECNLmDQGGvHarZHWkXo0H8YSKI/Bf2ZgukTeB1p5bjJnlVrwfzwKk8mhAN5ogbSYp8/ dfdPbuhEQazxmUkwAEhLR9cJjtX4uBs70epBZrR5JVV6OuYFvcWpS8XrnXZxrEfN1HkH fEcw== X-Gm-Message-State: APjAAAUxzxwrWvMEzJ12vId9mOoCUhN01I170/R5pDCQIEdvoIqevAO/ A00VJ6Br9WQubQulTAs6y7Z/hQ== X-Google-Smtp-Source: APXvYqxT+id6lAe9dtPusHQxl3sXymIOGIAh/Cg61XvNMY7njU1Zwb8lVxwhgvwtGS04Nwx6EBQBeQ== X-Received: by 2002:adf:e3c7:: with SMTP id k7mr4554644wrm.80.1575995841218; Tue, 10 Dec 2019 08:37:21 -0800 (PST) Received: from myrica (adsl-84-227-176-239.adslplus.ch. [84.227.176.239]) by smtp.gmail.com with ESMTPSA id s1sm3687632wmc.23.2019.12.10.08.37.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 10 Dec 2019 08:37:20 -0800 (PST) Date: Tue, 10 Dec 2019 17:37:16 +0100 From: Jean-Philippe Brucker To: Eric Auger Cc: eric.auger.pro@gmail.com, qemu-devel@nongnu.org, qemu-arm@nongnu.org, peter.maydell@linaro.org, mst@redhat.com, armbru@redhat.com, jean-philippe.brucker@arm.com, bharatb.linux@gmail.com, yang.zhong@intel.com, dgilbert@redhat.com, quintela@redhat.com, kevin.tian@intel.com, peterx@redhat.com, tnowicki@marvell.com Subject: Re: [PATCH for-5.0 v11 05/20] virtio-iommu: Endpoint and domains structs and helpers Message-ID: <20191210163716.GD277340@myrica> References: <20191122182943.4656-1-eric.auger@redhat.com> <20191122182943.4656-6-eric.auger@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20191122182943.4656-6-eric.auger@redhat.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::444 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 10 Dec 2019 16:37:25 -0000 On Fri, Nov 22, 2019 at 07:29:28PM +0100, Eric Auger wrote: > +typedef struct viommu_domain { > + uint32_t id; > + GTree *mappings; > + QLIST_HEAD(, viommu_endpoint) endpoint_list; > +} viommu_domain; > + > +typedef struct viommu_endpoint { > + uint32_t id; > + viommu_domain *domain; > + QLIST_ENTRY(viommu_endpoint) next; > +} viommu_endpoint; There might be a way to merge viommu_endpoint and the IOMMUDevice structure introduced in patch 4, since they both represent one endpoint. Maybe virtio_iommu_find_add_pci_as() could add the IOMMUDevice to s->endpoints, and IOMMUDevice could store the endpoint ID rather than bus and devfn. > +typedef struct viommu_interval { > + uint64_t low; > + uint64_t high; > +} viommu_interval; I guess these should be named in CamelCase? Although if we're allowed to choose my vote goes to underscores :) Thanks, Jean From MAILER-DAEMON Tue Dec 10 11:41:21 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1ieiZd-0008VJ-9Y for mharc-qemu-arm@gnu.org; Tue, 10 Dec 2019 11:41:21 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:58133) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ieiZb-0008Td-FH for qemu-arm@nongnu.org; Tue, 10 Dec 2019 11:41:20 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ieiZa-0003Tn-Bi for qemu-arm@nongnu.org; Tue, 10 Dec 2019 11:41:19 -0500 Received: from us-smtp-delivery-1.mimecast.com ([205.139.110.120]:27881 helo=us-smtp-1.mimecast.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1ieiZa-0003TB-6w for qemu-arm@nongnu.org; Tue, 10 Dec 2019 11:41:18 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1575996077; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=oQ2rGxKgg83OZ9oqSgECS/5VH/LEYzs7CGZjuEUgRUI=; b=U2FuMeKaqgxy+iGDpBgo5bCgXw9zQJw2HHyuJ/4Q9+797q+iMJ08+JmFb18wQka96E4XHQ SWMxHo/Y/WbAmMZWDHH0kQBvnd5rZa5Plbp5bBT51gnmYx/X/P5V/8eufVyr6Vm0n1gedV 6acw9wrylReaa1fWfYTu7ZakekpSQwA= Received: from mimecast-mx01.redhat.com (mimecast-mx01.redhat.com [209.132.183.4]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-132-fCV5_Z9mP2qvGb4xpFHIBQ-1; Tue, 10 Dec 2019 11:41:13 -0500 Received: from smtp.corp.redhat.com (int-mx07.intmail.prod.int.phx2.redhat.com [10.5.11.22]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx01.redhat.com (Postfix) with ESMTPS id 71E711010C5D; Tue, 10 Dec 2019 16:41:12 +0000 (UTC) Received: from kamzik.brq.redhat.com (unknown [10.43.2.160]) by smtp.corp.redhat.com (Postfix) with ESMTPS id 227271001902; Tue, 10 Dec 2019 16:41:10 +0000 (UTC) Date: Tue, 10 Dec 2019 17:41:08 +0100 From: Andrew Jones To: Peter Maydell Cc: Marc Zyngier , qemu-arm , Richard Henderson , QEMU Developers , bijan.mottahedeh@oracle.com Subject: Re: [PATCH v1 2/5] timer: arm: Introduce functions to get the host cntfrq Message-ID: <20191210164108.waqpn3wbo75nwqpx@kamzik.brq.redhat.com> References: <20191016143410.5023-1-drjones@redhat.com> <20191016143410.5023-3-drjones@redhat.com> MIME-Version: 1.0 In-Reply-To: X-Scanned-By: MIMEDefang 2.84 on 10.5.11.22 X-MC-Unique: fCV5_Z9mP2qvGb4xpFHIBQ-1 X-Mimecast-Spam-Score: 0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: quoted-printable Content-Disposition: inline X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 205.139.110.120 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 10 Dec 2019 16:41:20 -0000 On Tue, Dec 10, 2019 at 03:47:39PM +0000, Peter Maydell wrote: > On Wed, 16 Oct 2019 at 15:34, Andrew Jones wrote: > > > > When acceleration like KVM is in use it's necessary to use the host's > > counter frequency when converting ticks to or from time units. > > > > Signed-off-by: Andrew Jones > > Reviewed-by: Richard Henderson > > --- > > include/qemu/timer.h | 16 ++++++++++++++++ > > 1 file changed, 16 insertions(+) > > > > diff --git a/include/qemu/timer.h b/include/qemu/timer.h > > index 85bc6eb00b21..8941ddea8242 100644 > > --- a/include/qemu/timer.h > > +++ b/include/qemu/timer.h > > @@ -1006,6 +1006,22 @@ static inline int64_t cpu_get_host_ticks(void) > > } > > #endif > > > > +#if defined(__aarch64__) > > +static inline uint32_t cpu_get_host_tick_frequency(void) > > +{ > > + uint64_t frq; > > + asm volatile("mrs %0, cntfrq_el0" : "=3Dr" (frq)); > > + return frq; > > +} > > +#elif defined(__arm__) > > +static inline uint32_t cpu_get_host_tick_frequency(void) > > +{ > > + uint32_t frq; > > + asm volatile("mrc p15, 0, %0, c14, c0, 0" : "=3Dr" (frq)); > > + return frq; > > +} > > +#endif >=20 > Don't we want to know what the guest counter frequency > is, not the host counter frequency? That is, I would have > expected that we get this value via doing a KVM ONE_REG ioctl > to ask the kernel what the guest cntfrq is. Are we using > the host value on the assumption that the guest might have > misprogrammed their copy of the register? > Indeed it would be best to get whatever KVM is using for the given VCPU's CNTFRQ through GET_ONE_REG, but KVM doesn't seem to allow it. I hadn't tested before, but to be sure, I did now with the following kselftests test #include "kvm_util.h" #include "processor.h" =20 static void guest_code(void) { } =20 int main(void) { struct kvm_vm *vm =3D vm_create_default(0, 0, guest_code); uint64_t reg; =20 get_reg(vm, 0, ARM64_SYS_REG(3, 3, 14, 0, 0), ®); printf("%lx\n", reg); return 0; } The vcpu ioctl fails with ENOENT. Currently KVM requires all guests to have the same frequency as the host, but I guess that will change eventually. It's definitely best to do the save/restore thing, as you suggest. Thanks, drew From MAILER-DAEMON Tue Dec 10 11:42:08 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1ieiaN-0000p1-SI for mharc-qemu-arm@gnu.org; Tue, 10 Dec 2019 11:42:07 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:58297) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ieiaL-0000md-GK for qemu-arm@nongnu.org; Tue, 10 Dec 2019 11:42:06 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ieiaK-0003hj-BO for qemu-arm@nongnu.org; Tue, 10 Dec 2019 11:42:05 -0500 Received: from mail-wr1-x441.google.com ([2a00:1450:4864:20::441]:44354) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ieiaK-0003hQ-3p for qemu-arm@nongnu.org; Tue, 10 Dec 2019 11:42:04 -0500 Received: by mail-wr1-x441.google.com with SMTP id q10so20864483wrm.11 for ; Tue, 10 Dec 2019 08:42:04 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=date:from:to:cc:subject:message-id:references:mime-version :content-disposition:in-reply-to; bh=gqtOT5wE759za0LpbvnxJtRB0nZSfy/DZcdzVo4pDRI=; b=lLCV/4KjY237HMPohF0mo2sSICkE5JBX794nSpAY+rZx6y/ynvDvsy48mtIzV4pzHS xbgVZ9JUDviRDv3KleVVmodHwqH1Bh5TDjOMb3MmhmE1J67RYHFtoDb4NH75EcJ90R4u q5wlb+wIMNeFVqYpnamEzMOO9IrIS78NeAUBrhFk0WxqlFuj8dipHRszGbzZU0wmfLLc s93pqsexqAAf1dNG0RrRmoeMnB4GVeb0459lyZE9Qqru4HBz709oEsuca58h++gMGB+O jwx30o5OzVspUdv36R5YLjTU9EYZts1t80PIRbShq5L3Ph7whBKvhj1BR8o/HAV/b0GS 3U+g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:in-reply-to; bh=gqtOT5wE759za0LpbvnxJtRB0nZSfy/DZcdzVo4pDRI=; b=ffpm/dwRpXoAUJX7d2blmOsc/jGJdMgwRpUnPztUbY6ihSTJWp6FhYTJRW8viy/Wdy QzfyKkzbC8fMvj8nm7QmNxgX5AD9p18QHin/lA8kyvTzfDunu6QMTZgOa9DzO7b05ax9 Ft5423jUWqI22uUzH5M575fvlkYNneZMtNBWGo15iyl97zP5vCrrIkD1kJ/k0bXoOtXg OfNs13sMfHIrHqWKs430NpgQyYv3hdF1VDr9R7umhb0C9G/p2IaNVqafXq8ZvD2gNfjM fz3dgaDo0JYwUUX7T8I9apjs3LRCBILP7VcMMRujx8D29Qspz1J+hmutFKXtmDFpCxyp xG9w== X-Gm-Message-State: APjAAAXzjw0ioBRMLunC8kHptMvgir7dWzsKZiR7H+82xQiis396ZSF0 4WEp7DVyWtrY4xqDr8ViOv893w== X-Google-Smtp-Source: APXvYqxT7TVZrWdQ7EPo9+cnmXvelYTJSYnHtDJVmDN5yg+cQRjFtKjdQagIL6g3hKz/i7pxIFhN+A== X-Received: by 2002:a5d:4cc9:: with SMTP id c9mr4213902wrt.70.1575996123027; Tue, 10 Dec 2019 08:42:03 -0800 (PST) Received: from myrica (adsl-84-227-176-239.adslplus.ch. [84.227.176.239]) by smtp.gmail.com with ESMTPSA id e8sm3824236wrt.7.2019.12.10.08.42.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 10 Dec 2019 08:42:02 -0800 (PST) Date: Tue, 10 Dec 2019 17:41:56 +0100 From: Jean-Philippe Brucker To: Eric Auger Cc: eric.auger.pro@gmail.com, qemu-devel@nongnu.org, qemu-arm@nongnu.org, peter.maydell@linaro.org, mst@redhat.com, armbru@redhat.com, jean-philippe.brucker@arm.com, bharatb.linux@gmail.com, yang.zhong@intel.com, dgilbert@redhat.com, quintela@redhat.com, kevin.tian@intel.com, peterx@redhat.com, tnowicki@marvell.com Subject: Re: [PATCH for-5.0 v11 06/20] virtio-iommu: Implement attach/detach command Message-ID: <20191210164156.GE277340@myrica> References: <20191122182943.4656-1-eric.auger@redhat.com> <20191122182943.4656-7-eric.auger@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20191122182943.4656-7-eric.auger@redhat.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::441 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 10 Dec 2019 16:42:06 -0000 On Fri, Nov 22, 2019 at 07:29:29PM +0100, Eric Auger wrote: > diff --git a/hw/virtio/virtio-iommu.c b/hw/virtio/virtio-iommu.c > index 235bde2203..138d5b2a9c 100644 > --- a/hw/virtio/virtio-iommu.c > +++ b/hw/virtio/virtio-iommu.c > @@ -77,11 +77,12 @@ static gint interval_cmp(gconstpointer a, gconstpointer b, gpointer user_data) > static void virtio_iommu_detach_endpoint_from_domain(viommu_endpoint *ep) > { > QLIST_REMOVE(ep, next); > + g_tree_unref(ep->domain->mappings); > ep->domain = NULL; > } > > -viommu_endpoint *virtio_iommu_get_endpoint(VirtIOIOMMU *s, uint32_t ep_id); > -viommu_endpoint *virtio_iommu_get_endpoint(VirtIOIOMMU *s, uint32_t ep_id) > +static viommu_endpoint *virtio_iommu_get_endpoint(VirtIOIOMMU *s, > + uint32_t ep_id) > { > viommu_endpoint *ep; > > @@ -102,15 +103,14 @@ static void virtio_iommu_put_endpoint(gpointer data) > > if (ep->domain) { > virtio_iommu_detach_endpoint_from_domain(ep); > - g_tree_unref(ep->domain->mappings); > } > > trace_virtio_iommu_put_endpoint(ep->id); > g_free(ep); > } > > -viommu_domain *virtio_iommu_get_domain(VirtIOIOMMU *s, uint32_t domain_id); > -viommu_domain *virtio_iommu_get_domain(VirtIOIOMMU *s, uint32_t domain_id) > +static viommu_domain *virtio_iommu_get_domain(VirtIOIOMMU *s, > + uint32_t domain_id) Looks like the above change belong to patch 5? > { > viommu_domain *domain; > > @@ -137,7 +137,6 @@ static void virtio_iommu_put_domain(gpointer data) > QLIST_FOREACH_SAFE(iter, &domain->endpoint_list, next, tmp) { > virtio_iommu_detach_endpoint_from_domain(iter); > } > - g_tree_destroy(domain->mappings); When created by virtio_iommu_get_domain(), mappings has one reference. Then for each attach (including the first one) an additional reference is taken, and freed by virtio_iommu_detach_endpoint_from_domain(). So I think there are two problems: * virtio_iommu_put_domain() drops one ref for each endpoint, but we still have one reference to mappings, so they're not freed. We do need this g_tree_destroy() * After detaching all the endpoints, the guest may reuse the domain ID for another domain, but the previous mappings haven't been erased. Not sure how to fix this using the g_tree refs, because dropping all the references will free the internal tree data and it won't be reusable. Thanks, Jean From MAILER-DAEMON Tue Dec 10 11:43:39 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1ieibr-0002G8-Cp for mharc-qemu-arm@gnu.org; Tue, 10 Dec 2019 11:43:39 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:58645) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ieibo-0002E2-C7 for qemu-arm@nongnu.org; Tue, 10 Dec 2019 11:43:38 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ieibn-00042R-3g for qemu-arm@nongnu.org; Tue, 10 Dec 2019 11:43:36 -0500 Received: from mail-wr1-x442.google.com ([2a00:1450:4864:20::442]:37623) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ieibm-000429-UH for qemu-arm@nongnu.org; Tue, 10 Dec 2019 11:43:35 -0500 Received: by mail-wr1-x442.google.com with SMTP id w15so20958125wru.4 for ; Tue, 10 Dec 2019 08:43:34 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=date:from:to:cc:subject:message-id:references:mime-version :content-disposition:in-reply-to; bh=WtaxfLDwEq+CPxRUbY/7JAvtoC2bGMlKZ7QdRWbKMnU=; b=Aonj25m5O3NG/3YcvFJ7MZMjqL8o4JwlSte53sfRkiPZx+v23ru9AtaLADs4js3iGV 4MX7HKiQdzzpyYebZIgbHCkIvBrbNiObRbVj6g4cpmsqKvcJCFozuI+bTaMM+M4ZnrfH josRRWe4AelRKAVFN5Clv420QFrxzvr5TiXC/Ab8FR/Pnx0URxdbC0cAKMKSnXmSWmcN zrrDeMQuXCsJpGxf0P9buODS3QUfo+E7YRMIaLzUNrTBs626ZMqcU8fmzfN+qO52JRHw 7htGYPYi+5gv3Tuw9edHiSG5EjX9lvBn+dhg6ZtHzZmB/TnA5P5g4cTFnH5R/lMyvjYY W7mw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:in-reply-to; bh=WtaxfLDwEq+CPxRUbY/7JAvtoC2bGMlKZ7QdRWbKMnU=; b=fH2z+UgEEpfLteY1cjhh7Xsg3kMCyQhDf0m/11vdaLJkday2VB50oOcqldylZJ7rRs aCVzMYhRvIbJv1+YH1ZVTPMifibq7UbEmgW5KN6EfPBswW3gFx2avW+4TdefsBn7LHbu kSAFjVGo33GFJv8kCowwq+wT4r8ISecfuwc402ch8atROUEUJyqG1PUp9+i5S2cmH0kb yjj/tah4pGGtzozzhLOLoc/LtxeWDDyakKlMv7Oru5frl+Z477sfLGGqmYcrdN0m2Apf v0aSaGb9bsYszphFdF1+DoobcLewBDZ0fwZlV5GCO/jZm9zeLZgk251QC9ZqyiJSYTUL r2jw== X-Gm-Message-State: APjAAAWhNwbQ332fhHQfNLeYb3C7KjExMtArBqz1wU8m3EGX6A7igh3E 95bQVx3e8HqkCTMDg4TBUOGIbA== X-Google-Smtp-Source: APXvYqyPt+8Jwb4gmCEufCkJ6i1T6iyNXkzmBu7FhNUtTYJ2P6ft4BOk8HS6kvcWauPXhDluGd9hOw== X-Received: by 2002:a5d:6ac5:: with SMTP id u5mr4284808wrw.271.1575996213730; Tue, 10 Dec 2019 08:43:33 -0800 (PST) Received: from myrica (adsl-84-227-176-239.adslplus.ch. [84.227.176.239]) by smtp.gmail.com with ESMTPSA id n14sm3689719wmi.26.2019.12.10.08.43.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 10 Dec 2019 08:43:33 -0800 (PST) Date: Tue, 10 Dec 2019 17:43:28 +0100 From: Jean-Philippe Brucker To: Eric Auger Cc: eric.auger.pro@gmail.com, qemu-devel@nongnu.org, qemu-arm@nongnu.org, peter.maydell@linaro.org, mst@redhat.com, armbru@redhat.com, jean-philippe.brucker@arm.com, bharatb.linux@gmail.com, yang.zhong@intel.com, dgilbert@redhat.com, quintela@redhat.com, kevin.tian@intel.com, peterx@redhat.com, tnowicki@marvell.com Subject: Re: [PATCH for-5.0 v11 07/20] virtio-iommu: Implement map/unmap Message-ID: <20191210164328.GF277340@myrica> References: <20191122182943.4656-1-eric.auger@redhat.com> <20191122182943.4656-8-eric.auger@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20191122182943.4656-8-eric.auger@redhat.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::442 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 10 Dec 2019 16:43:38 -0000 On Fri, Nov 22, 2019 at 07:29:30PM +0100, Eric Auger wrote: > @@ -238,10 +244,35 @@ static int virtio_iommu_map(VirtIOIOMMU *s, > uint64_t virt_start = le64_to_cpu(req->virt_start); > uint64_t virt_end = le64_to_cpu(req->virt_end); > uint32_t flags = le32_to_cpu(req->flags); > + viommu_domain *domain; > + viommu_interval *interval; > + viommu_mapping *mapping; Additional checks would be good. Most importantly we need to return S_INVAL if we don't recognize a bit in flags (a MUST in the spec). It might be good to check that addresses are aligned on the page granule as well, and return S_RANGE if they aren't (a SHOULD in the spec), but I don't care as much. > + > + interval = g_malloc0(sizeof(*interval)); > + > + interval->low = virt_start; > + interval->high = virt_end; > + > + domain = g_tree_lookup(s->domains, GUINT_TO_POINTER(domain_id)); > + if (!domain) { > + return VIRTIO_IOMMU_S_NOENT; Leaks interval, I guess you could allocate it after this block. Thanks, Jean > + } > + > + mapping = g_tree_lookup(domain->mappings, (gpointer)interval); > + if (mapping) { > + g_free(interval); > + return VIRTIO_IOMMU_S_INVAL; > + } > > trace_virtio_iommu_map(domain_id, virt_start, virt_end, phys_start, flags); > > - return VIRTIO_IOMMU_S_UNSUPP; > + mapping = g_malloc0(sizeof(*mapping)); > + mapping->phys_addr = phys_start; > + mapping->flags = flags; > + > + g_tree_insert(domain->mappings, interval, mapping); > + > + return VIRTIO_IOMMU_S_OK; From MAILER-DAEMON Tue Dec 10 11:44:03 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1ieicF-0002a5-Jn for mharc-qemu-arm@gnu.org; Tue, 10 Dec 2019 11:44:03 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:58794) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ieicC-0002Wx-OM for qemu-arm@nongnu.org; Tue, 10 Dec 2019 11:44:01 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ieicB-00049b-T9 for qemu-arm@nongnu.org; Tue, 10 Dec 2019 11:44:00 -0500 Received: from mail-wr1-x443.google.com ([2a00:1450:4864:20::443]:41043) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ieicB-000492-2l for qemu-arm@nongnu.org; Tue, 10 Dec 2019 11:43:59 -0500 Received: by mail-wr1-x443.google.com with SMTP id c9so20885383wrw.8 for ; Tue, 10 Dec 2019 08:43:58 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=date:from:to:cc:subject:message-id:references:mime-version :content-disposition:in-reply-to; bh=OlDxnhAEHtJOXMsOXwxoIBoY1rDQfYKSPVN/Ah8CeLg=; b=RkPzgErkwNvg/N/hYOb/+LM+QfNVPmUrh3IP8BwGL0zrTPfNkmO2EO0kyyaLyChNaa h3YLcgaSanQYYTZ95dWV8+ARp4BU9NAtPuSf+qAxEiRCY3hcoxUF5mK83MKBvKk6wiYW XkNowoTadaAtMTwl/QA+kfd6AZ7AzG+bkhKXosFHLAG1gB125LZULfLJnC3CAe1VPJ7U CBWNvOcLj+RW2G0OO81aM4oyUynYOtuxudtyF3gzzliBK46nn1nyrjBVON3s5u0wSXHL KQZwUJ+599bcYCxpxOzh7PCPdTm9ETE0D/HxTuEII1Q5bX6aEy+qmiO15dggtf0JCsca N4KQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:in-reply-to; bh=OlDxnhAEHtJOXMsOXwxoIBoY1rDQfYKSPVN/Ah8CeLg=; b=mxg49fNlS+B80QldK3v8MYrYcJmatsoFc8oRmA8PSSIUqtXwh5hQOpWUGUUNqMgbJQ EjtoEEELNnHja1UNTp0yWQKlDRtqVqs7X8/eKCv/nrJA7uFZ91EaGE96gUFDpkSiCuvi 8PxoMo5rdKODhCOcldRiSvk1cHFz2wpLI7/YGuDLPHBdaM2/FsQM8IAnlIQPTaaZEKbr YBVjxlWnfGfcLtwmN45eM+Fd78O6zqHxQ1DyOzFytUahr3BtjKnTIxV+cpksJx49miKj 1kuygrBjXJ5LoybnUnds+q8ZIJc7+dgaPrK8uQVmqRzS9bvtTk34TSGLUiM50bd4XwWm itQA== X-Gm-Message-State: APjAAAWGzg+Hcs4yEB0uWBlhvJVvtcXnbrGsmBGOQTLZfq1KF6VIfkps oeoy/5/25ZmcqlCxDpnQJIAdVQ== X-Google-Smtp-Source: APXvYqxAf3lYJEH+sbHwd2TTvcOdpvXAOoN2/dYBQV7PXO00goJ8X9YeG9ZTfAtJLwQw+cyjvXdKug== X-Received: by 2002:a5d:6349:: with SMTP id b9mr4484684wrw.346.1575996237774; Tue, 10 Dec 2019 08:43:57 -0800 (PST) Received: from myrica (adsl-84-227-176-239.adslplus.ch. [84.227.176.239]) by smtp.gmail.com with ESMTPSA id y10sm3660456wmm.3.2019.12.10.08.43.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 10 Dec 2019 08:43:57 -0800 (PST) Date: Tue, 10 Dec 2019 17:43:52 +0100 From: Jean-Philippe Brucker To: Eric Auger Cc: eric.auger.pro@gmail.com, qemu-devel@nongnu.org, qemu-arm@nongnu.org, peter.maydell@linaro.org, mst@redhat.com, armbru@redhat.com, jean-philippe.brucker@arm.com, bharatb.linux@gmail.com, yang.zhong@intel.com, dgilbert@redhat.com, quintela@redhat.com, kevin.tian@intel.com, peterx@redhat.com, tnowicki@marvell.com Subject: Re: [PATCH for-5.0 v11 08/20] virtio-iommu: Implement translate Message-ID: <20191210164352.GG277340@myrica> References: <20191122182943.4656-1-eric.auger@redhat.com> <20191122182943.4656-9-eric.auger@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20191122182943.4656-9-eric.auger@redhat.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::443 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 10 Dec 2019 16:44:01 -0000 On Fri, Nov 22, 2019 at 07:29:31PM +0100, Eric Auger wrote: > This patch implements the translate callback > > Signed-off-by: Eric Auger Reviewed-by: Jean-Philippe Brucker From MAILER-DAEMON Tue Dec 10 11:44:38 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1ieico-0003Ey-Dt for mharc-qemu-arm@gnu.org; Tue, 10 Dec 2019 11:44:38 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:58944) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ieicm-0003Cw-3I for qemu-arm@nongnu.org; Tue, 10 Dec 2019 11:44:37 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ieicl-0004MB-3d for qemu-arm@nongnu.org; Tue, 10 Dec 2019 11:44:36 -0500 Received: from mail-wr1-x443.google.com ([2a00:1450:4864:20::443]:41048) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ieick-0004Lk-Ts for qemu-arm@nongnu.org; Tue, 10 Dec 2019 11:44:35 -0500 Received: by mail-wr1-x443.google.com with SMTP id c9so20887576wrw.8 for ; Tue, 10 Dec 2019 08:44:34 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=date:from:to:cc:subject:message-id:references:mime-version :content-disposition:in-reply-to; bh=Pc/HUtwzczF7hl6cnINcFfG6ZqHbQFHNh940PLCprkw=; b=RnTss9rSbsavmfAYaoiMDwVIsdegSm3Pwy0/t5YimwPdG0Tv+LXOQAikrquQ1gH/L3 t/vDKRUi3Jpds48e+qclxshkUJMTwRB0d2Z1wWKfo37Bk0KI+5eSNqMcvp0pK4DKbHEh nyuqJYgoAfQg01JLLSalT+YN/J/pBKerH2xedN+0pQF6Kn0s7vvu2vaPZYHOA6ZeGcxS 4mzyygEJZSbZpsZ3NQXNV1PZdZRQ1QomUgc4zDAP3hRV4kTJauoI+7QJ79sjdIYSYzZA MMS3U5K+wmQTiC/pTOaPd3uE7PE0u9HFilKg6hdez/KP+HMU4KXkiZdd8WsF5MqPfT7s QWog== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:in-reply-to; bh=Pc/HUtwzczF7hl6cnINcFfG6ZqHbQFHNh940PLCprkw=; b=N9DHmie+2GifBVZ37d2hSlIJQePuavdgtLU0XzKLYHs5rD/M3YH6ZCCZHE2vXNuE8F 8l5QMefhr59MspNvFHY6XYGiWCr1lRVPF+dTpYzBX2ymVwbmPWXQlRgFgR7LZNgFwmpW 1Rk3QbjgWM/IbJkqUehqavKdUiL/U/6eztvgyBOjpTC0NeInsn2o/H7qkNr2Wh0XWNid 6T/mwTeHbZo+1F8QV9M9BsAP3DlDlmsNc6eATdnBmp3Zjg5LIFYTOQ3HVYM8t/P14IJz AW0VHfQpK09jiE0Bq+6ZZY3+K7BEe+T2PbULdIQYNIZT3XiusTN4ovKSOaXf37+Fz9TB IMEA== X-Gm-Message-State: APjAAAUXaqLeUEkLUKGZ44f/UIHBY4iXSabmKpkVT7GMtEa4/lNI25GU 7idAGZ3y2pIBnyIivfHSW3I+KQ== X-Google-Smtp-Source: APXvYqxbShFZ86wmwb83jArVx6pbttNvj/034bI8PUddYwI18r5tKa8vHPCYqAoiYCkfSCQCFbEwtw== X-Received: by 2002:adf:e3c1:: with SMTP id k1mr4138784wrm.151.1575996273900; Tue, 10 Dec 2019 08:44:33 -0800 (PST) Received: from myrica (adsl-84-227-176-239.adslplus.ch. [84.227.176.239]) by smtp.gmail.com with ESMTPSA id x18sm3823630wrr.75.2019.12.10.08.44.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 10 Dec 2019 08:44:33 -0800 (PST) Date: Tue, 10 Dec 2019 17:44:28 +0100 From: Jean-Philippe Brucker To: Eric Auger Cc: eric.auger.pro@gmail.com, qemu-devel@nongnu.org, qemu-arm@nongnu.org, peter.maydell@linaro.org, mst@redhat.com, armbru@redhat.com, jean-philippe.brucker@arm.com, bharatb.linux@gmail.com, yang.zhong@intel.com, dgilbert@redhat.com, quintela@redhat.com, kevin.tian@intel.com, peterx@redhat.com, tnowicki@marvell.com Subject: Re: [PATCH for-5.0 v11 09/20] virtio-iommu: Implement fault reporting Message-ID: <20191210164428.GH277340@myrica> References: <20191122182943.4656-1-eric.auger@redhat.com> <20191122182943.4656-10-eric.auger@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20191122182943.4656-10-eric.auger@redhat.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::443 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 10 Dec 2019 16:44:37 -0000 On Fri, Nov 22, 2019 at 07:29:32PM +0100, Eric Auger wrote: > @@ -443,6 +489,8 @@ static IOMMUTLBEntry virtio_iommu_translate(IOMMUMemoryRegion *mr, hwaddr addr, > if (!ep) { > if (!bypass_allowed) { > error_report_once("%s sid=%d is not known!!", __func__, sid); > + virtio_iommu_report_fault(s, VIRTIO_IOMMU_FAULT_R_UNKNOWN, > + 0, sid, 0); I guess we could report the faulting address as well, it can be useful for diagnostics. > } else { > entry.perm = flag; > } > @@ -455,6 +503,8 @@ static IOMMUTLBEntry virtio_iommu_translate(IOMMUMemoryRegion *mr, hwaddr addr, > "%s %02x:%02x.%01x not attached to any domain\n", > __func__, PCI_BUS_NUM(sid), > PCI_SLOT(sid), PCI_FUNC(sid)); > + virtio_iommu_report_fault(s, VIRTIO_IOMMU_FAULT_R_DOMAIN, > + 0, sid, 0); Here as well, especially since that error would get propagated by a linux guest to the device driver > } else { > entry.perm = flag; > } > @@ -468,16 +518,25 @@ static IOMMUTLBEntry virtio_iommu_translate(IOMMUMemoryRegion *mr, hwaddr addr, > qemu_log_mask(LOG_GUEST_ERROR, > "%s no mapping for 0x%"PRIx64" for sid=%d\n", > __func__, addr, sid); > + virtio_iommu_report_fault(s, VIRTIO_IOMMU_FAULT_R_MAPPING, > + 0, sid, addr); Flag VIRTIO_IOMMU_FAULT_F_ADDRESS denotes a valid address field Thanks, Jean From MAILER-DAEMON Tue Dec 10 11:45:05 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1ieidF-0003wZ-LL for mharc-qemu-arm@gnu.org; Tue, 10 Dec 2019 11:45:05 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:59065) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ieidC-0003t0-UM for qemu-arm@nongnu.org; Tue, 10 Dec 2019 11:45:03 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ieidB-0004XH-Ut for qemu-arm@nongnu.org; Tue, 10 Dec 2019 11:45:02 -0500 Received: from mail-wr1-x441.google.com ([2a00:1450:4864:20::441]:34709) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ieidB-0004Wq-OV for qemu-arm@nongnu.org; Tue, 10 Dec 2019 11:45:01 -0500 Received: by mail-wr1-x441.google.com with SMTP id t2so20914308wrr.1 for ; Tue, 10 Dec 2019 08:45:01 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=date:from:to:cc:subject:message-id:references:mime-version :content-disposition:in-reply-to; bh=g9cCMZtEkM7Y7AHaz9CHJEQ5Bqx3hepUjwcskldSK3k=; b=DwlGZP8+EpwQOTeJoLtucByNvZ9UpL03GK829rihVuEGOLULBNz27gCFJi/Y9asyhA /yagQyBTIKXfYCsif4YPCvJbeLoOViM5nGXhqxXYlgmTYkhnTJv5RJ/Tm+M7uQsAlBdz 3pZyBSiQXfNRschF5jx2eAS19+lA3YNorgni/IIgCVFtGxsy01bK+19MfpLQpDlKMcrC GUisdoMI78UK5NWmssIS0hibeg8OIweSne2qOi/aywIcas+FK1bE1xob0FsOeLAv1BsG /6nI6fMq/NzZQJUmr07aa0CPG5rrmuzUBnkk0tBxYOdW6vd5x4frEWqvWAlA2Li5cwGb Xqyw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:in-reply-to; bh=g9cCMZtEkM7Y7AHaz9CHJEQ5Bqx3hepUjwcskldSK3k=; b=KkWcCeF8+Ty/jSR6T4PyDOWxE1Q2EiqL7GzvRkhcuT+VfLbUZr/aooYOi3g8cZAibv LsHMLZ7Hma7/hu0dT637kf8hpmz2ABw8/xK5oMw5OmG4CggQnYY+oYpGwsBTo6ZmClyh Cr7XaPEbTAU86qbE4lqczcovDUuc9S79prWyibU0sIGKXjdGrpRWiIUr01r5EmD0OtE4 aV6YtdaJJW3EiTbPOdEeRyXlwYCk9BEdpjK39klBABckaAJXot2Saffzl4SqKEYtB//n p1F5H6IpbfpTDu8Ac1h/QEZYsPZ8DawqJLR5i9YJR1poeBt6VNtxqxMG+x1sNBLmfNDm PcwQ== X-Gm-Message-State: APjAAAULVdB+mKoCkgAoKK2IeKnaF8cHrFLafFq1F4U34rRLAL0GsK8o UIznZgo8NPFoX76s8sieW+X2bA== X-Google-Smtp-Source: APXvYqyg6IvNiPboGL1KqEAv5dXfOxRf4UKen/I72vMGY8AyDRICYfqHTvUK0rdLm54PegAZ4hgDLg== X-Received: by 2002:adf:ffc5:: with SMTP id x5mr4392337wrs.92.1575996300824; Tue, 10 Dec 2019 08:45:00 -0800 (PST) Received: from myrica (adsl-84-227-176-239.adslplus.ch. [84.227.176.239]) by smtp.gmail.com with ESMTPSA id p10sm3682392wmi.15.2019.12.10.08.44.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 10 Dec 2019 08:45:00 -0800 (PST) Date: Tue, 10 Dec 2019 17:44:55 +0100 From: Jean-Philippe Brucker To: Eric Auger Cc: eric.auger.pro@gmail.com, qemu-devel@nongnu.org, qemu-arm@nongnu.org, peter.maydell@linaro.org, mst@redhat.com, armbru@redhat.com, jean-philippe.brucker@arm.com, bharatb.linux@gmail.com, yang.zhong@intel.com, dgilbert@redhat.com, quintela@redhat.com, kevin.tian@intel.com, peterx@redhat.com, tnowicki@marvell.com Subject: Re: [PATCH for-5.0 v11 10/20] virtio-iommu-pci: Add virtio iommu pci support Message-ID: <20191210164455.GI277340@myrica> References: <20191122182943.4656-1-eric.auger@redhat.com> <20191122182943.4656-11-eric.auger@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20191122182943.4656-11-eric.auger@redhat.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::441 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 10 Dec 2019 16:45:04 -0000 On Fri, Nov 22, 2019 at 07:29:33PM +0100, Eric Auger wrote: > This patch adds virtio-iommu-pci, which is the pci proxy for > the virtio-iommu device. > > Signed-off-by: Eric Auger Reviewed-by: Jean-Philippe Brucker From MAILER-DAEMON Tue Dec 10 11:45:42 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1ieidq-0004Si-PD for mharc-qemu-arm@gnu.org; Tue, 10 Dec 2019 11:45:42 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:59174) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ieidn-0004O1-9n for qemu-arm@nongnu.org; Tue, 10 Dec 2019 11:45:40 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ieidm-0004qB-7H for qemu-arm@nongnu.org; Tue, 10 Dec 2019 11:45:39 -0500 Received: from mail-wr1-x442.google.com ([2a00:1450:4864:20::442]:38758) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ieidi-0004m1-M5 for qemu-arm@nongnu.org; Tue, 10 Dec 2019 11:45:35 -0500 Received: by mail-wr1-x442.google.com with SMTP id y17so20897873wrh.5 for ; Tue, 10 Dec 2019 08:45:34 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=date:from:to:cc:subject:message-id:references:mime-version :content-disposition:in-reply-to; bh=J9i3/MkcXXwFrp7MwGhstFhrn0JoZM+nuz8kFsu3TVs=; b=B4Mg2svv2Enjp6/cLsAW+6qr1toLBoUc624xx9f0y5aI9fYj4m3x66uYs7t2sJAPJa hsQq1YhwflwdTMQxuMAX5Jk6dMa5XbQ6UQfi6Gh8XSe09jhYhn8ZhAjnuzm6bkgU1hDR Emd8abkwuv12lv+fvHhfvw0mEmlb6yxgjqNnRzn813Y2i8jefUrggZEqacIFpBF+AwG4 PUUxWRWOgodys1WeeW99iGdXkpxfL++J8YexKTnZ1PusfUg7ya36D+gMTOw7d6EDJ0V0 DbyrguN/KPM6a+UZq/CPck78Ryz30C6yzzdw08IiAKTdbFCEJKNGlxALIL8SWzvQRPJg GGSw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:in-reply-to; bh=J9i3/MkcXXwFrp7MwGhstFhrn0JoZM+nuz8kFsu3TVs=; b=O2IpO32x8eshNl6vU/IKVlFqlhoS7RPEUMHMNFpTSt3ZRiBQ3c/+Rg21Jep4xvTrIS zb9Ig3GGXtx/qvnizsRbMXfL4+IXyLzd7RC4X6/SiZbbQmffdDrGt/E6/ZudwAXyw2Bb 5bfCAwu+XsBke2kP2yYPkhnjjYt6LbYEV+r3fvkfr2K/IKHFTMAJNCSaH0FzVz1rSZaR zv7OYP4WSZvngrW+MCiUIAsYA7hUZizJcKIj0ipLS97XasgRvuzoSap3Vn7+Os8NSlr7 tQeymExaokIkFtjDRt87OM5D9ClodrVd0zuvpCJwue1xU9POyCa/tkJUxM3az8RPTIo6 +3Iw== X-Gm-Message-State: APjAAAWHfLpAep0xLyp37R1tzqOi7r04f0uoUHM9qq5DNRw8rpvkaThn KYY1h4P7PKGnXX6WMKbIke5XmQ== X-Google-Smtp-Source: APXvYqyZ7Q/kWlwUTEDAmH6FUoWnHKchBRgXb1VlIGofFVKDPPpDPZlr1HpfGBaE3DvfAf+N0aXMbw== X-Received: by 2002:a05:6000:12ce:: with SMTP id l14mr4601426wrx.342.1575996333166; Tue, 10 Dec 2019 08:45:33 -0800 (PST) Received: from myrica (adsl-84-227-176-239.adslplus.ch. [84.227.176.239]) by smtp.gmail.com with ESMTPSA id v4sm3484387wml.2.2019.12.10.08.45.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 10 Dec 2019 08:45:32 -0800 (PST) Date: Tue, 10 Dec 2019 17:45:28 +0100 From: Jean-Philippe Brucker To: Eric Auger Cc: eric.auger.pro@gmail.com, qemu-devel@nongnu.org, qemu-arm@nongnu.org, peter.maydell@linaro.org, mst@redhat.com, armbru@redhat.com, jean-philippe.brucker@arm.com, bharatb.linux@gmail.com, yang.zhong@intel.com, dgilbert@redhat.com, quintela@redhat.com, kevin.tian@intel.com, peterx@redhat.com, tnowicki@marvell.com Subject: Re: [PATCH for-5.0 v11 11/20] hw/arm/virt: Add the virtio-iommu device tree mappings Message-ID: <20191210164528.GJ277340@myrica> References: <20191122182943.4656-1-eric.auger@redhat.com> <20191122182943.4656-12-eric.auger@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20191122182943.4656-12-eric.auger@redhat.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::442 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 10 Dec 2019 16:45:41 -0000 On Fri, Nov 22, 2019 at 07:29:34PM +0100, Eric Auger wrote: > diff --git a/hw/virtio/virtio-iommu-pci.c b/hw/virtio/virtio-iommu-pci.c > index 280230b31e..4cfae1f9df 100644 > --- a/hw/virtio/virtio-iommu-pci.c > +++ b/hw/virtio/virtio-iommu-pci.c > @@ -31,9 +31,6 @@ struct VirtIOIOMMUPCI { > > static Property virtio_iommu_pci_properties[] = { > DEFINE_PROP_UINT32("class", VirtIOPCIProxy, class_code, 0), > - DEFINE_PROP_ARRAY("reserved-regions", VirtIOIOMMUPCI, > - vdev.nb_reserved_regions, vdev.reserved_regions, > - qdev_prop_interval, Interval), Belongs in patch 10? Apart from that Reviewed-by: Jean-Philippe Brucker From MAILER-DAEMON Tue Dec 10 11:46:22 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1ieieU-0004n1-14 for mharc-qemu-arm@gnu.org; Tue, 10 Dec 2019 11:46:22 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:59291) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ieieR-0004k4-Pq for qemu-arm@nongnu.org; Tue, 10 Dec 2019 11:46:20 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ieieQ-000555-Ua for qemu-arm@nongnu.org; Tue, 10 Dec 2019 11:46:19 -0500 Received: from mail-wr1-x443.google.com ([2a00:1450:4864:20::443]:46261) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ieieQ-00054a-Os for qemu-arm@nongnu.org; Tue, 10 Dec 2019 11:46:18 -0500 Received: by mail-wr1-x443.google.com with SMTP id z7so20781808wrl.13 for ; Tue, 10 Dec 2019 08:46:18 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=date:from:to:cc:subject:message-id:references:mime-version :content-disposition:in-reply-to; bh=yBKxW4v01bphY2O9YP1yA6L9FAbeDZs2B/G4JBWdu/E=; b=j5+PyxjGFHC0Sr3oAnZYMUkLhH3Yjf/rZSjyCb+vUWnHg8tykTdUKDwS7HlIrmy6Sk nNXzqKGkeyQz4ujmtDZL+im0k2nQYSoivNp3P0P3qLl8ICw4iYxyKqI5MC4Sv7S5VSam Mg91e5Ycs2wgJyiuysUOIHSbewI/6UvG4AN5SvtKGzvyejo3uWy+FptbcGyNll+5XAX2 XHHAVRIUgfWyTRQZHXfPusugHkAu+UGIVgj4ISzTzgS13M/ZjdCaeHQIcseinzJGbHCS e1b18kluJ4WcKH6h0+vJye8COrWjl8ugB6+2WkHO2ehGnrHsFt1j/UIrzaMBdym6fj4B yM7w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:in-reply-to; bh=yBKxW4v01bphY2O9YP1yA6L9FAbeDZs2B/G4JBWdu/E=; b=ML+ktX6qjZBr4IYP+Dlhgnzo/WJMcW6kdNJ+PoKgDcD26KUKtQk5YUNepR5gYDbqPo aynKQQf4C9YVIWx/oe7fqNQstQNyqgSg+JzVKrqwyO48mhYjo+EuO1R+XsZ8Zxq4DfaA yu9T/Wq51Mp8JwxB6fhhUb9IekWtKuIvU6DiCrChK+zjDHGmHBeiUaBB+V2j8cp0YMu0 kSH9IP3olFH2+ezdINYPd1c99RMaGF6w6M4RHVnaJJx+elrNoJsYViL/oiNjqXNvImlr kRa5txUEY0lX6bnpE6FHqo/wbZe8RBoqe+Sz279hpHcbFy91qFxJFhZ/nDjCUvkeZDOq j7WA== X-Gm-Message-State: APjAAAVqHZEpKc2+xsx7ejBaXz2KYJSopWmSQO0I7XtX898Tz3M57o38 hgrw8U4sj2vyS6cNPPCtsot2UA== X-Google-Smtp-Source: APXvYqyV9Ji4GM/uba2zln5kgKPeRYOqyPr4NtfEVQdW7TPMXNfhY1QwgWxO9EfqTM1PDCs4P8LDOg== X-Received: by 2002:adf:fe4d:: with SMTP id m13mr3978876wrs.179.1575996377832; Tue, 10 Dec 2019 08:46:17 -0800 (PST) Received: from myrica (adsl-84-227-176-239.adslplus.ch. [84.227.176.239]) by smtp.gmail.com with ESMTPSA id w22sm3534503wmk.34.2019.12.10.08.46.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 10 Dec 2019 08:46:17 -0800 (PST) Date: Tue, 10 Dec 2019 17:46:12 +0100 From: Jean-Philippe Brucker To: Eric Auger Cc: eric.auger.pro@gmail.com, qemu-devel@nongnu.org, qemu-arm@nongnu.org, peter.maydell@linaro.org, mst@redhat.com, armbru@redhat.com, jean-philippe.brucker@arm.com, bharatb.linux@gmail.com, yang.zhong@intel.com, dgilbert@redhat.com, quintela@redhat.com, kevin.tian@intel.com, peterx@redhat.com, tnowicki@marvell.com Subject: Re: [PATCH for-5.0 v11 13/20] virtio-iommu: Implement probe request Message-ID: <20191210164612.GK277340@myrica> References: <20191122182943.4656-1-eric.auger@redhat.com> <20191122182943.4656-14-eric.auger@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20191122182943.4656-14-eric.auger@redhat.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::443 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 10 Dec 2019 16:46:21 -0000 On Fri, Nov 22, 2019 at 07:29:36PM +0100, Eric Auger wrote: > This patch implements the PROBE request. At the moment, > no reserved regions are returned as none are registered > per device. Only a NONE property is returned. > > Signed-off-by: Eric Auger Reviewed-by: Jean-Philippe Brucker From MAILER-DAEMON Tue Dec 10 11:47:02 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1ieif8-0005Py-Mi for mharc-qemu-arm@gnu.org; Tue, 10 Dec 2019 11:47:02 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:59419) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ieif4-0005M7-RH for qemu-arm@nongnu.org; Tue, 10 Dec 2019 11:46:59 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ieif3-0005FW-Qd for qemu-arm@nongnu.org; Tue, 10 Dec 2019 11:46:58 -0500 Received: from mail-wr1-x441.google.com ([2a00:1450:4864:20::441]:45887) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ieif3-0005Ew-Kg for qemu-arm@nongnu.org; Tue, 10 Dec 2019 11:46:57 -0500 Received: by mail-wr1-x441.google.com with SMTP id j42so20841244wrj.12 for ; Tue, 10 Dec 2019 08:46:57 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=date:from:to:cc:subject:message-id:references:mime-version :content-disposition:in-reply-to; bh=t6xiBm4AewZPGvWuP/C57U7CBdnlU6ctV7vonpSTcNY=; b=QfoZ5P48W8GsomtBZLloAwVJKXIiOVSv8BYnO1KEc4cVmUvX8ODXUpoKPaJ0DNLX5v hIoItecgjGlxfqsTlIhq89JGVyTjbsdMgfgfoXyYLtfzMlgZfEqbVCSxumBZU5daq7jF uxknZNGmVEn5uYE+yVkB8BHyqanWi7ObXl1EH+m0EBm9lHsGilGYnVCnxoY16hWRkaFh 9Ej/s0+ctL2JG8l5uuWj8u01+EyzvkH5MFI8hlOQJHaPn/zVlByD/96egQwVRkWRhCOP mTdMSWhlpkIUwP8O5H9Sav+mnYD3lANb0gMzx3pSUvxRLRTRR3o5dRW0ZtmAdZeyr7Gc +QYw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:in-reply-to; bh=t6xiBm4AewZPGvWuP/C57U7CBdnlU6ctV7vonpSTcNY=; b=OR5MhYxaKZz5F76lvNnpACfhnC+Z47mqtcmJ/4cfCc98jXVl0u4KgdGB2YlgUtALav 6+D5jX+Z4qv+YC64Ys8WsHQDFVcXr2ZerEtKxdMy86yx/MIBNavcbwCck+xIzBm0VoIg h6Qc2H3uoH7q4tNwWWpFLM393vtmlfaHp/KDsFMyPIYH3IwzfAyoxKNaHz6BfE1YMo+R SXLq+ieQCi/fF29mQJ6lem4aX7QpL3UAfjTGIwnnV3qNepd5U/kSv3/gpQmpTyBWXAyu bO5vMNH5rjrhCYqnMbDkoMBVnFS7sTAb4OIbtTaqIe6DBjLP9q73kUSRu/cC51OISbB9 Lcwg== X-Gm-Message-State: APjAAAVr6EVwVLxA/NKm7pTHIanGGKnIfe05tW5AF399Of1pPOjRngbZ YiHyVAnApAWEfd82cc1ZQUFFtA== X-Google-Smtp-Source: APXvYqx9XR6r84Xopmm1b212+fWkQzXvL9yJa3C/hKbkklYVUxSIArRDNTYIkSBmgTNPCdt+H2sL8A== X-Received: by 2002:adf:ea05:: with SMTP id q5mr4398038wrm.48.1575996416685; Tue, 10 Dec 2019 08:46:56 -0800 (PST) Received: from myrica (adsl-84-227-176-239.adslplus.ch. [84.227.176.239]) by smtp.gmail.com with ESMTPSA id q6sm3927503wrx.72.2019.12.10.08.46.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 10 Dec 2019 08:46:56 -0800 (PST) Date: Tue, 10 Dec 2019 17:46:51 +0100 From: Jean-Philippe Brucker To: Eric Auger Cc: eric.auger.pro@gmail.com, qemu-devel@nongnu.org, qemu-arm@nongnu.org, peter.maydell@linaro.org, mst@redhat.com, armbru@redhat.com, jean-philippe.brucker@arm.com, bharatb.linux@gmail.com, yang.zhong@intel.com, dgilbert@redhat.com, quintela@redhat.com, kevin.tian@intel.com, peterx@redhat.com, tnowicki@marvell.com Subject: Re: [PATCH for-5.0 v11 14/20] virtio-iommu: Handle reserved regions in the translation process Message-ID: <20191210164651.GL277340@myrica> References: <20191122182943.4656-1-eric.auger@redhat.com> <20191122182943.4656-15-eric.auger@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20191122182943.4656-15-eric.auger@redhat.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::441 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 10 Dec 2019 16:47:00 -0000 On Fri, Nov 22, 2019 at 07:29:37PM +0100, Eric Auger wrote: > + for (i = 0; i < s->nb_reserved_regions; i++) { > + if (interval.low >= s->reserved_regions[i].low && > + interval.low <= s->reserved_regions[i].high) { > + switch (s->reserved_regions[i].type) { > + case VIRTIO_IOMMU_RESV_MEM_T_MSI: > + entry.perm = flag; > + goto unlock; > + case VIRTIO_IOMMU_RESV_MEM_T_RESERVED: > + default: > + virtio_iommu_report_fault(s, VIRTIO_IOMMU_FAULT_R_MAPPING, > + 0, sid, addr); Needs the VIRTIO_IOMMU_FAULT_F_ADDRESS flag. Thanks, Jean From MAILER-DAEMON Tue Dec 10 11:47:14 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1ieifK-0005fA-53 for mharc-qemu-arm@gnu.org; Tue, 10 Dec 2019 11:47:14 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:59510) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ieifG-0005b8-WE for qemu-arm@nongnu.org; Tue, 10 Dec 2019 11:47:11 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ieifG-0005KC-0k for qemu-arm@nongnu.org; Tue, 10 Dec 2019 11:47:10 -0500 Received: from mail-wr1-x442.google.com ([2a00:1450:4864:20::442]:36224) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ieifF-0005Jn-R1 for qemu-arm@nongnu.org; Tue, 10 Dec 2019 11:47:09 -0500 Received: by mail-wr1-x442.google.com with SMTP id z3so20918893wru.3 for ; Tue, 10 Dec 2019 08:47:09 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=date:from:to:cc:subject:message-id:references:mime-version :content-disposition:in-reply-to; bh=MaG2yhQk2cqVE1psdudnea3pLB+w1y+rXcyshwhvQEQ=; b=C37tM1vu50Xd4/4ybdT4NjFOcRVsfZpTVIze9zGBYP41ep0mVm45g8YQEQLTDqxJBY JIhL7ZGtRi8k7sO7n4rFRD2061F9nPLQ0ZxyuD7K4OPOWkGXt9dkl/De+mfDT56CE9PH Vbw2dbsVLSGzcEBApcxllDjzVxOL2STEVmOkCWzl8Svbia3N9iiHPjojElzZHX/aFrXp caJPrw2+ReyMjwz8QFHMLre3WY7fhdW+UDe+x04Lv/n49pRrabnwnBPwFUzC8Ae/u0bb mBha/aiRRvxcvcSizi4occldr3egmOeszng7i71VqLWdvZPfnFxI53AgWlORyNNYvfkJ 9zSQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:in-reply-to; bh=MaG2yhQk2cqVE1psdudnea3pLB+w1y+rXcyshwhvQEQ=; b=pSN0EqiXUIXHd8OtAozQaOxWU4yUyIbyxKksPF4lRs0z0+x04amDPUovHkVrCqRiuP rXi4vtgE/D2dooqz81PLQiOQsYKjfEuSb5tcp3r8nfR4t4mAZ46xd92FnlVP970PZSZr VIinnR0H90dHLACOFNvcvso/GblCSLejmVQ8K3Xw3cPz8wjr0x9C1vTE+0nBDtCeJRbK okfMko61JJcK5nDFQWlijwg0kwepzMo6//JN1/zPH9GXQp/O/LvOpzTdgYcg7rRckN0g 0YZbASJ2lM+mC9uf0zPdc77woRmvxa2HlNEQNVXTzVKIu5XLaN8lTfFLYzD5j7BIxhOl OKCw== X-Gm-Message-State: APjAAAV2qpvoorQOUvJpEDp9SR46ubqbaTVaPOWklMAyaTIue/tMbBck wMX4GJWJoQqOJlP2kbv3LerGWg== X-Google-Smtp-Source: APXvYqwTE1gZERfzuQ9NC9J5s9ebQhgK3/hg4vjz/cnsqaJRMmw2DPRSXxntXYsq0iOk8/8JT4V4ag== X-Received: by 2002:a5d:43c7:: with SMTP id v7mr4121910wrr.32.1575996428921; Tue, 10 Dec 2019 08:47:08 -0800 (PST) Received: from myrica (adsl-84-227-176-239.adslplus.ch. [84.227.176.239]) by smtp.gmail.com with ESMTPSA id f17sm2032251wmc.8.2019.12.10.08.47.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 10 Dec 2019 08:47:08 -0800 (PST) Date: Tue, 10 Dec 2019 17:47:04 +0100 From: Jean-Philippe Brucker To: Eric Auger Cc: eric.auger.pro@gmail.com, qemu-devel@nongnu.org, qemu-arm@nongnu.org, peter.maydell@linaro.org, mst@redhat.com, armbru@redhat.com, jean-philippe.brucker@arm.com, bharatb.linux@gmail.com, yang.zhong@intel.com, dgilbert@redhat.com, quintela@redhat.com, kevin.tian@intel.com, peterx@redhat.com, tnowicki@marvell.com Subject: Re: [PATCH for-5.0 v11 15/20] virtio-iommu-pci: Add array of Interval properties Message-ID: <20191210164704.GM277340@myrica> References: <20191122182943.4656-1-eric.auger@redhat.com> <20191122182943.4656-16-eric.auger@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20191122182943.4656-16-eric.auger@redhat.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::442 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 10 Dec 2019 16:47:13 -0000 On Fri, Nov 22, 2019 at 07:29:38PM +0100, Eric Auger wrote: > The machine may need to pass reserved regions to the > virtio-iommu-pci device (such as the MSI window on x86). > So let's add an array of Interval properties. > > Signed-off-by: Eric Auger Reviewed-by: Jean-Philippe Brucker From MAILER-DAEMON Tue Dec 10 11:47:54 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1ieifs-0006HB-9E for mharc-qemu-arm@gnu.org; Tue, 10 Dec 2019 11:47:53 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:59677) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ieifm-0006D5-1y for qemu-arm@nongnu.org; Tue, 10 Dec 2019 11:47:43 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ieifj-0005VW-Ts for qemu-arm@nongnu.org; Tue, 10 Dec 2019 11:47:41 -0500 Received: from mail-wr1-x443.google.com ([2a00:1450:4864:20::443]:41084) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ieifj-0005VH-NM for qemu-arm@nongnu.org; Tue, 10 Dec 2019 11:47:39 -0500 Received: by mail-wr1-x443.google.com with SMTP id c9so20899216wrw.8 for ; Tue, 10 Dec 2019 08:47:39 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=date:from:to:cc:subject:message-id:references:mime-version :content-disposition:in-reply-to; bh=LtrQYfJdcTkOs3pftjkEUGXoyOJMbtVXOFWCdr+C1OY=; b=cP2GPmuVUE7UNfgpHtT+qtVlOHHLBBq2Wn4i+ghjaISiVk6S3tjqIKxoKxPLmkPUtf H/IVjd6DInMah9YbnLyHRTnJA/DH67iu952gCAgOO8294jdcLuN7fpsCYQZnOkLvKuNJ I8jTkqA0QeFh6E5nVECXnK60JrlTeUA9suaRTGiAkNLItgQol/FnQl1DkSoRgd89Yldo JfCh1q4Jb6h+s0YDQ9I932jkgYq2adIaX44hVUYOFqdS55IOlJXL+4TN7+rVs7nG14ER SVBMc7uWbAS50tQO2qPMg/cHrdWK10MCNa8ASNGESX3ocFmq3dxAtE2lqsemgUWBeYFP 0KGQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:in-reply-to; bh=LtrQYfJdcTkOs3pftjkEUGXoyOJMbtVXOFWCdr+C1OY=; b=Co7PJ5OotHS7PPTJ7BhAD/6ypQ0RuEAAZA71KmeY3JiEzd8DPmxkrGIhMpFEDCNt6h NPfqyRX7FBjVoVCCCTMmW8sW3RftiG+cPKhdlgAbTIdfdXXLTFEnNMSdbn89+oBmTs9G UUQicKMIOEkiSxxAkGs9zsGSuqOCDzEHa6gUxbnIUtL21vN16Awvnua2+yixCL9Mx10r Oey2ujMpXonBnj9ypPBZf6zVklyCuX60s1hlzxT33/n9CfSqdmXAf/CUoEwSyzltZBBA tVKDl1jddmi7W4ZiceAM2gQe+HaZhivSIFDWBxBWx4obbbtXAUUHLtXltHjwkNwjg5SY UcQQ== X-Gm-Message-State: APjAAAXk2BzLW36oUc6LBh/fipk+iBCCvr7YKzvz+ecw5dQTOnT8c0j2 pTyJ2+MWTunzua18Z6tcO4RtKw== X-Google-Smtp-Source: APXvYqzQ0vFombUSzUKCftQxtoWRZFhDtjVyKt3Qfkgpt/nAIWLb5hKleceMyatefZMevhl7+p1Ndg== X-Received: by 2002:adf:81c2:: with SMTP id 60mr4248392wra.8.1575996458872; Tue, 10 Dec 2019 08:47:38 -0800 (PST) Received: from myrica (adsl-84-227-176-239.adslplus.ch. [84.227.176.239]) by smtp.gmail.com with ESMTPSA id v3sm3759098wru.32.2019.12.10.08.47.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 10 Dec 2019 08:47:38 -0800 (PST) Date: Tue, 10 Dec 2019 17:47:33 +0100 From: Jean-Philippe Brucker To: Eric Auger Cc: eric.auger.pro@gmail.com, qemu-devel@nongnu.org, qemu-arm@nongnu.org, peter.maydell@linaro.org, mst@redhat.com, armbru@redhat.com, jean-philippe.brucker@arm.com, bharatb.linux@gmail.com, yang.zhong@intel.com, dgilbert@redhat.com, quintela@redhat.com, kevin.tian@intel.com, peterx@redhat.com, tnowicki@marvell.com Subject: Re: [PATCH for-5.0 v11 16/20] hw/arm/virt-acpi-build: Introduce fill_iort_idmap helper Message-ID: <20191210164733.GN277340@myrica> References: <20191122182943.4656-1-eric.auger@redhat.com> <20191122182943.4656-17-eric.auger@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20191122182943.4656-17-eric.auger@redhat.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::443 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 10 Dec 2019 16:47:44 -0000 On Fri, Nov 22, 2019 at 07:29:39PM +0100, Eric Auger wrote: > build_iort(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms) > { > @@ -426,13 +437,12 @@ build_iort(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms) > smmu->gerr_gsiv = cpu_to_le32(irq + 2); > smmu->sync_gsiv = cpu_to_le32(irq + 3); > > - /* Identity RID mapping covering the whole input RID range */ > - idmap = &smmu->id_mapping_array[0]; > - idmap->input_base = 0; > - idmap->id_count = cpu_to_le32(0xFFFF); > - idmap->output_base = 0; > - /* output IORT node is the ITS group node (the first node) */ > - idmap->output_reference = cpu_to_le32(iort_node_offset); > + /* > + * Identity RID mapping covering the whole input RID range. > + * The output IORT node is the ITS group node (the first node). > + */ > + fill_iort_idmap(smmu->id_mapping_array, 0, 0, 0xffff, 0, nit: the other calls use uppercase hex digits Reviewed-by: Jean-Philippe Brucker From MAILER-DAEMON Tue Dec 10 11:48:48 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1ieigp-0006y7-Sy for mharc-qemu-arm@gnu.org; Tue, 10 Dec 2019 11:48:47 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:59882) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ieigl-0006tg-Ls for qemu-arm@nongnu.org; Tue, 10 Dec 2019 11:48:44 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ieigk-0005qE-K8 for qemu-arm@nongnu.org; Tue, 10 Dec 2019 11:48:43 -0500 Received: from mail-wr1-x442.google.com ([2a00:1450:4864:20::442]:44428) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ieigk-0005pn-D7 for qemu-arm@nongnu.org; Tue, 10 Dec 2019 11:48:42 -0500 Received: by mail-wr1-x442.google.com with SMTP id q10so20889114wrm.11 for ; Tue, 10 Dec 2019 08:48:42 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=date:from:to:cc:subject:message-id:references:mime-version :content-disposition:in-reply-to; bh=B1cDfx8s5f/9QR+mlmSpW12qDckt3D/lvXSVtrdKzq4=; b=TjZh1j5u0sa58MCh/35yKK+h02dV1GjVfZe+pZwtrsCnoyLkP7xvCCCWrdv2R7YtBi r/nkuPds7iWxCZeOgtoT/asSpTkJr/raf6ErdGyZsDVrWA1CGpQoRNE4iiXjFlqQO71x jUof0258cALt89i/pRukTOHkweDwYQ0QaczoaCV8uxlRheK0+XBCo+gjda4JsH1oTywc tEBDwIhEPY8O8e9e8yiKtMHnTMh3P9QkiAQc3LryvfaPCLUKA/lVq5Zr4gJ6GxBaZOe2 /dq/yJwVcoWOBcrTYnAC6c5U+/mh2S8KE8neWL/lDVbwdIJ9RoTFusvURtADhl2Wge9k 90Tw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:in-reply-to; bh=B1cDfx8s5f/9QR+mlmSpW12qDckt3D/lvXSVtrdKzq4=; b=MmfCGv3X+7zS4AeSYXFJ53NbsZl/OhkbGjdTDCyzhudCnZfNcusICy+FUe9t+Lmtf6 1MfRghyLIRpwq2f1+CGFy209gXspPrP/WuLDGdA5RwqUf29tZFdykw5kuCTqly6l8POm E0Jb8AX6jSJy0biStoC3fApo89FLhWEzF5wbsIxUTQy37RsJCw6mwmKiAg70rGhJ3Rax 8M+aRYw9UJCXpK9fhRJwh/P0b4R2eVbgiEsvCA1UZbmRMqfyNGSxNNRBeD4PayXp76Hd ssGpEFtLWYwEEdwRKaoaCp5YqIwcrgN+Z6eip6Stu8Lz8CwZAsxyseeuShPqJNbnh5Rt Maaw== X-Gm-Message-State: APjAAAUwkQu1xjKFfQD6QeHWFEDU37/TluZIwaLV8O2xcxdIxZm04ZiC nDxZRNKtAoiFCqVHYx2QvFbaEw== X-Google-Smtp-Source: APXvYqxZ3nPGlovSWWgbV+/mrQ268XN14/6vPkqO/GWDigotiGR14SRQfC1U161GtPZldIB0vEwDdg== X-Received: by 2002:adf:dc4b:: with SMTP id m11mr4319211wrj.344.1575996521389; Tue, 10 Dec 2019 08:48:41 -0800 (PST) Received: from myrica (adsl-84-227-176-239.adslplus.ch. [84.227.176.239]) by smtp.gmail.com with ESMTPSA id o7sm3695579wmc.41.2019.12.10.08.48.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 10 Dec 2019 08:48:40 -0800 (PST) Date: Tue, 10 Dec 2019 17:48:36 +0100 From: Jean-Philippe Brucker To: Eric Auger Cc: eric.auger.pro@gmail.com, qemu-devel@nongnu.org, qemu-arm@nongnu.org, peter.maydell@linaro.org, mst@redhat.com, armbru@redhat.com, jean-philippe.brucker@arm.com, bharatb.linux@gmail.com, yang.zhong@intel.com, dgilbert@redhat.com, quintela@redhat.com, kevin.tian@intel.com, peterx@redhat.com, tnowicki@marvell.com Subject: Re: [PATCH for-5.0 v11 17/20] hw/arm/virt-acpi-build: Add virtio-iommu node in IORT table Message-ID: <20191210164836.GO277340@myrica> References: <20191122182943.4656-1-eric.auger@redhat.com> <20191122182943.4656-18-eric.auger@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20191122182943.4656-18-eric.auger@redhat.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::442 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 10 Dec 2019 16:48:46 -0000 On Fri, Nov 22, 2019 at 07:29:40PM +0100, Eric Auger wrote: > This patch builds the virtio-iommu node in the ACPI IORT table. > > The RID space of the root complex, which spans 0x0-0x10000 > maps to streamid space 0x0-0x10000 in the virtio-iommu which in > turn maps to deviceid space 0x0-0x10000 in the ITS group. > > The iommu RID is excluded as described in virtio-iommu > specification. > > Signed-off-by: Eric Auger Reviewed-by: Jean-Philippe Brucker Although VIOT changes the layout of the IORT node slightly, the implementation should stay pretty much the same. From MAILER-DAEMON Tue Dec 10 11:50:19 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1ieiiI-00087t-V0 for mharc-qemu-arm@gnu.org; Tue, 10 Dec 2019 11:50:18 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:60279) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ieiiE-00083j-79 for qemu-arm@nongnu.org; Tue, 10 Dec 2019 11:50:15 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ieiiD-0006QV-3O for qemu-arm@nongnu.org; Tue, 10 Dec 2019 11:50:13 -0500 Received: from mail-wm1-x344.google.com ([2a00:1450:4864:20::344]:34730) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ieiiC-0006Pz-Sh for qemu-arm@nongnu.org; Tue, 10 Dec 2019 11:50:13 -0500 Received: by mail-wm1-x344.google.com with SMTP id f4so2682084wmj.1 for ; Tue, 10 Dec 2019 08:50:12 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=date:from:to:cc:subject:message-id:references:mime-version :content-disposition:in-reply-to; bh=r8wiVmuohB+E6DxPcyxULVV8ixEmXNvbFga4Fjsd5gs=; b=ytkYdsWxjkbQ145QRW5KgM8/L9+9b3Gd8CuOQHfBcMvtHGvFazwETTkKBRABoi36lc RVYTNwCMvxCRtL/r7qYgFAcshjQ8TxfDIhKkMF5XJr63ZWEoxaoK40Sn3P9H2l/zgdF2 zNGbWEBV3hPAZdUZNEVG9vSkj2/x4jlEhhWs0mFexkEZPmfw9yTWoLr/XcHwR60Xy91+ 8KPlGw3hHb/8sMc4fIt7UCkVFItqinXe0+ZaE9VNCMjBVkZrR0CfUu6WyS/NpYCgBUSr UFALSDTEkSbgdeJNdOExQcEHgf3TojcI04AWP0061ZhSD6fig9EIibesm9fzAUFt8PID jF7Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:in-reply-to; bh=r8wiVmuohB+E6DxPcyxULVV8ixEmXNvbFga4Fjsd5gs=; b=ZyqcPzcdN401veTHbCkrMI44R9CZs77YQy4tHOkl/cH2rTPWLblS4IdRPRdU/iLEho N8u1qFPincP9dwdoNHg3FgR846ukpCqlrg6EqyFP4e3xhve46xAKEUvEuigtPNWeGz2t PURd/Yte2Lg+AvR1amhW6OSzJZNgu559jK34gmfXz9P4XMcOTmMgy62542TG6W5NRPnq iPf2odRTYwx4+1lhnSx+bnHbKW0FS/zB9KmgxkzgHgqkw+kD0iwL7rDv+tqi/yWnPuHZ Ot55HpBmfqUuVdgN9vnsmUyLEKKenQe9br7G0ZvfVs8syE2lwAQbCqshBuvrf/ZD06kY mpaQ== X-Gm-Message-State: APjAAAVwCpSlDxWlpvnkn8H3gKZ693pA/cJc50jKhge7F+Rl/PwPQir/ lrdtXx2Tutiqk6WQBrhJx6mkbA== X-Google-Smtp-Source: APXvYqwuFYFJNREQM+tpSI2EiAdhiApENKlYKeWCRwrSi5x0FlbhZVdJz1p6JphQdtYW1qgTyjWmiw== X-Received: by 2002:a05:600c:1105:: with SMTP id b5mr6634272wma.159.1575996611555; Tue, 10 Dec 2019 08:50:11 -0800 (PST) Received: from myrica (adsl-84-227-176-239.adslplus.ch. [84.227.176.239]) by smtp.gmail.com with ESMTPSA id e18sm3769701wrr.95.2019.12.10.08.50.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 10 Dec 2019 08:50:10 -0800 (PST) Date: Tue, 10 Dec 2019 17:50:06 +0100 From: Jean-Philippe Brucker To: Eric Auger Cc: eric.auger.pro@gmail.com, qemu-devel@nongnu.org, qemu-arm@nongnu.org, peter.maydell@linaro.org, mst@redhat.com, armbru@redhat.com, jean-philippe.brucker@arm.com, bharatb.linux@gmail.com, yang.zhong@intel.com, dgilbert@redhat.com, quintela@redhat.com, kevin.tian@intel.com, peterx@redhat.com, tnowicki@marvell.com Subject: Re: [PATCH for-5.0 v11 18/20] virtio-iommu: Support migration Message-ID: <20191210165006.GP277340@myrica> References: <20191122182943.4656-1-eric.auger@redhat.com> <20191122182943.4656-19-eric.auger@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20191122182943.4656-19-eric.auger@redhat.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::344 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 10 Dec 2019 16:50:17 -0000 On Fri, Nov 22, 2019 at 07:29:41PM +0100, Eric Auger wrote: > +static const VMStateDescription vmstate_virtio_iommu_device = { > + .name = "virtio-iommu-device", > + .minimum_version_id = 1, > + .version_id = 1, > + .post_load = iommu_post_load, > + .fields = (VMStateField[]) { > + VMSTATE_GTREE_DIRECT_KEY_V(domains, VirtIOIOMMU, 1, > + &vmstate_domain, viommu_domain), > + VMSTATE_GTREE_DIRECT_KEY_V(endpoints, VirtIOIOMMU, 1, > + &vmstate_endpoint, viommu_endpoint), So if I understand correctly these fields are state that is modified by the guest? We don't need to save/load fields that cannot be modified by the guest, static information that is created from the QEMU command-line. I think the above covers everything we need to migrate in VirtIOIOMMU then, except for acked_features, which (as I pointed out on another patch) seems redundant anyway since there is vdev->guest_features. Reviewed-by: Jean-Philippe Brucker > + VMSTATE_END_OF_LIST() > + }, > +}; > + > + > static const VMStateDescription vmstate_virtio_iommu = { > .name = "virtio-iommu", > .minimum_version_id = 1, > -- > 2.20.1 > > From MAILER-DAEMON Tue Dec 10 11:50:45 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1ieiij-0000Fr-6K for mharc-qemu-arm@gnu.org; Tue, 10 Dec 2019 11:50:45 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:60418) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ieiid-0000AH-Ri for qemu-arm@nongnu.org; Tue, 10 Dec 2019 11:50:40 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ieiic-0006dg-P7 for qemu-arm@nongnu.org; Tue, 10 Dec 2019 11:50:39 -0500 Received: from mail-wr1-x441.google.com ([2a00:1450:4864:20::441]:41109) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ieiic-0006dM-I3 for qemu-arm@nongnu.org; Tue, 10 Dec 2019 11:50:38 -0500 Received: by mail-wr1-x441.google.com with SMTP id c9so20910135wrw.8 for ; Tue, 10 Dec 2019 08:50:38 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=date:from:to:cc:subject:message-id:references:mime-version :content-disposition:in-reply-to; bh=OlfjqJ3/LjH+g5cdCQ/k0akt9iUKtH6iUQLY+fs5ZCM=; b=qGezvISlVmrWMXOA1mS735B4gad1o68cfJ+LwEuX+V7e9Ev0R/9siXzsfbfyApCFhK 1c5UXBmu/OT1IRn2lzF9Ao6FnzmgAbRfjFglthbVYHBmvDoEc6b+UDgwe24L9OX5uvi+ w+6galaekwHD0liVsafcK1mIZpzBnYsZrCbd3Lzp6rZlKxb3y0Av52pgMurWs2pkP684 1mWNs//a1A5jEyP/THJACCanF4h1ZtxhcvLKGzouyufnyIxavZCmcMOF9Z6NkwC14k3G GACHLLra0EDvtO9pdbVknKaKZtlTl/qcHXYtSsSSu8tYHpGO9xPShjLujukG2cBKsGqs tLdQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:in-reply-to; bh=OlfjqJ3/LjH+g5cdCQ/k0akt9iUKtH6iUQLY+fs5ZCM=; b=sdwxB5l5Ej46WdULqq8dHQ66ehMfyQUNRbe1P7wVXq1tMS92VPo0KLMQbkCIECaORl Oy4CTYFbDIre4QppS26dpgJrNz28bbn6f3UyO4Qi6A/mBkBzjZ9zDr8kECfuvKh3dm0a Z2VnKSSQiI+TqAhCqq6wtU7BuofFi+jKX/oBnoV9m9cYrYAIQehh+TkSdBQxMhg9ifxl sgJi5Jo/R/MY7r3CRukprZpaT1mJXBI4KlBEvqo4ShjFABJqBMn5nxo1Hjs6ohXDV1u7 LkzVET2FfPjoBhlf4emLsDs8L3oxSsSE3DdkQQGAMxG8kj0G1NoF1eNOsah+VOq2VzGq PpQQ== X-Gm-Message-State: APjAAAVgdBo5e/4Uu8jB6N7Gk8fnKJ8YSWS7nSxow4LMTeILBNYrbB4H p4ID7SHzx09Zyp49S48ZvMNXmA== X-Google-Smtp-Source: APXvYqxutjvagaAitDymFgNYzAxJjxXMx8MD/eBp205r+vchYhXoEY+d33R7oUoTyIsZmQ87JFx7jw== X-Received: by 2002:a5d:5308:: with SMTP id e8mr4359722wrv.77.1575996637592; Tue, 10 Dec 2019 08:50:37 -0800 (PST) Received: from myrica (adsl-84-227-176-239.adslplus.ch. [84.227.176.239]) by smtp.gmail.com with ESMTPSA id j12sm3978809wrw.54.2019.12.10.08.50.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 10 Dec 2019 08:50:37 -0800 (PST) Date: Tue, 10 Dec 2019 17:50:32 +0100 From: Jean-Philippe Brucker To: Eric Auger Cc: eric.auger.pro@gmail.com, qemu-devel@nongnu.org, qemu-arm@nongnu.org, peter.maydell@linaro.org, mst@redhat.com, armbru@redhat.com, jean-philippe.brucker@arm.com, bharatb.linux@gmail.com, yang.zhong@intel.com, dgilbert@redhat.com, quintela@redhat.com, kevin.tian@intel.com, peterx@redhat.com, tnowicki@marvell.com Subject: Re: [PATCH for-5.0 v11 19/20] pc: Add support for virtio-iommu-pci Message-ID: <20191210165032.GQ277340@myrica> References: <20191122182943.4656-1-eric.auger@redhat.com> <20191122182943.4656-20-eric.auger@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20191122182943.4656-20-eric.auger@redhat.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::441 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 10 Dec 2019 16:50:43 -0000 On Fri, Nov 22, 2019 at 07:29:42PM +0100, Eric Auger wrote: > The virtio-iommu-pci is instantiated through the -device QEMU > option. However if instantiated it also requires an IORT ACPI table > to describe the ID mappings between the root complex and the iommu. > > This patch adds the generation of the IORT table if the > virtio-iommu-pci device is instantiated. > > We also declare the [0xfee00000 - 0xfeefffff] MSI reserved region > so that it gets bypassed by the IOMMU. > > Signed-off-by: Eric Auger It would be nice to factor the IORT code with arm, but this looks OK. Reviewed-by: Jean-Philippe Brucker From MAILER-DAEMON Tue Dec 10 11:53:58 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1ieilq-000419-MZ for mharc-qemu-arm@gnu.org; Tue, 10 Dec 2019 11:53:58 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:33195) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ieilm-0003wN-VN for qemu-arm@nongnu.org; Tue, 10 Dec 2019 11:53:56 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ieill-0007dQ-RL for qemu-arm@nongnu.org; Tue, 10 Dec 2019 11:53:54 -0500 Received: from mail-wm1-x341.google.com ([2a00:1450:4864:20::341]:38950) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ieill-0007cQ-Lf for qemu-arm@nongnu.org; Tue, 10 Dec 2019 11:53:53 -0500 Received: by mail-wm1-x341.google.com with SMTP id d5so2458713wmb.4 for ; Tue, 10 Dec 2019 08:53:53 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=date:from:to:cc:subject:message-id:references:mime-version :content-disposition:in-reply-to; bh=UxvJ/YVTJuP+hzpz1BJMpuf68KLAsLUo57u2sksODLU=; b=BGiPRQuwSInGNHSJAJJyjw7IdSn2N/5ded78AZFJiUsXWL2FJn25Ro9Kdak/CS/Wlb RDw21qnr3CwaeOALl/A0is/GVeXyG2FwjftKiBjFdzylfZ3YkLhwt00ZN7h5XDBUkxVl 5ki1+DZNwPsqJTJMr6Yqr8rrpr1Ng3Nf8gYauYG9PUJWf2dgs4B3Fv+lipGlTHY12kTg E0pKtq/Kpr5Wu2SzOCbvCgGaZOYrYIrdKtwQpYuUrfqllnpKfzitGy/HXk+zOY8zaKdG 5W9mCF2aLisOKJnqwI3t7QFqLJtIzSHq/Vz57fQPwoSFVJHZLmgDGLv/Dr9zbyclJ0fj A0Iw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:in-reply-to; bh=UxvJ/YVTJuP+hzpz1BJMpuf68KLAsLUo57u2sksODLU=; b=e4g3ktbyQxMrLddT2YOlO0BTcxQgQOk4AmrmS2mBomD4B3GSUr0Uq9efPzvYhd/1/c 0tydbY+FlpWaG3IXlc3nnC08B4mjzR0gM8xp6COhvUrt0z1tEV+cxgjoyozHTPncO/KD XDBJoM1shUImoFMZFPHULVD+GdxEjtbOdtBQi7yJARsRXl4cILub0+YxbxNgPYqYVul9 OGlRxA1C2jdioyWBHGB19u3FUvDohAWfivC+NwjmzxdGUIATUHh7aueTjwJqSaLIeywr DE8O83F3/EB3PIp28f9vkuaqKIO3kLXWrpMYmInUBIPmknInLXq+Z+NEgX7j+ZH+Iq0B b6TA== X-Gm-Message-State: APjAAAVi57TXrQRJX3Cuk+OkcqT7+3rKk86Fdt2XMIytyTx9mzvyZfyV i8FF7evTj1iHEw6EfJpfXORi7g== X-Google-Smtp-Source: APXvYqwad2Wvw1plasNOQ27dhBz3MdQF4fdcqMICgUC5o9UQARbbU/XuWPAgnzI2IYafpsKxr9Fc5Q== X-Received: by 2002:a1c:731a:: with SMTP id d26mr5975246wmb.130.1575996832049; Tue, 10 Dec 2019 08:53:52 -0800 (PST) Received: from holly.lan (cpc141214-aztw34-2-0-cust773.18-1.cable.virginm.net. [86.9.19.6]) by smtp.gmail.com with ESMTPSA id z18sm3637640wmf.21.2019.12.10.08.53.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 10 Dec 2019 08:53:51 -0800 (PST) Date: Tue, 10 Dec 2019 16:53:49 +0000 From: Daniel Thompson To: Peter Maydell Cc: qemu-arm , QEMU Developers , "patches@linaro.org" Subject: Re: [PATCH] hw/arm/virt: Second uart for normal-world Message-ID: <20191210165349.5sfyqwkbpfl7nlk2@holly.lan> References: <20191209152456.977399-1-daniel.thompson@linaro.org> <20191209170827.yojyts6qdvpxbkp4@holly.lan> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::341 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 10 Dec 2019 16:53:57 -0000 On Mon, Dec 09, 2019 at 05:10:30PM +0000, Peter Maydell wrote: > On Mon, 9 Dec 2019 at 17:08, Daniel Thompson wrote: > > I don't object to making it command line dependant (it is certainly > > lower risk) but, out of interest, has using /aliases to force the > > kernel to enumerate the serial nodes in the existing order been ruled > > out for any reason. > > No, I don't think anybody's investigated that (I wasn't aware > that you could do something like that). Bear in mind that the > kernel is not the only consumer of the DT, though -- you need > to use a mechanism that all DT consumers will handle correctly. The syntax for /aliases is standardized (in the DT documentation) but AFAIK the exact semantic meaning of an alias relies somewhat on idiom. It is true that the DT binding documentation for some serial drivers does include details of /aliases but sadly PL011 is not amoung them. I took a fairly detailed look at FreeBSD. I don't think /aliases is used to control enumeration order but that appears to be because aliases are handled in a different way to Linux. For example FreeBSD allows a custom console to be selected using FDT syntax (hw.fdt.console=serial0 or hw.fdt.console=/path/to/fdt-uart ) which means the Linux-like approach (such as console=ttyAMA0) need not be used. In summary I think that support for /aliases can and should be added since it the best way to help DT systems figure out how to match qemu uart numbering to its own naming. However I agree we still need a way to create systems with only a single UART even if I have not yet been able to come up with a test case that proves /aliases is insufficient ;-) Daniel. From MAILER-DAEMON Tue Dec 10 12:16:49 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1iej7x-0005IW-0U for mharc-qemu-arm@gnu.org; Tue, 10 Dec 2019 12:16:49 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:38718) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iej7u-0005I9-Gu for qemu-arm@nongnu.org; Tue, 10 Dec 2019 12:16:47 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1iej7t-0000PQ-C5 for qemu-arm@nongnu.org; Tue, 10 Dec 2019 12:16:46 -0500 Received: from us-smtp-delivery-1.mimecast.com ([205.139.110.120]:60571 helo=us-smtp-1.mimecast.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1iej7t-0000P4-8m for qemu-arm@nongnu.org; Tue, 10 Dec 2019 12:16:45 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1575998204; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=vbeUY1tYvNFELFptAI6NyGsSXcrw+gBajlhVpD0Q4A8=; b=DGuGYqUmvuSuYSRG0g/eOlzKJIkFUQ3fvG1dG/LtRwycXGT8uUKueP+Z2l+j2dYUXwe3im maWC7MB1ITK4IiwPeuMwC8LQmuBhiSHaQ2u7QOqsfcWGY278Ut+SMeUry/ouypnWjKwdVZ csgVfyLLIxp2ppfzea85eDmbp8dWQBw= Received: from mimecast-mx01.redhat.com (mimecast-mx01.redhat.com [209.132.183.4]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-188-m-J_QNgtMqWr3h-gqil5nQ-1; Tue, 10 Dec 2019 12:16:40 -0500 Received: from smtp.corp.redhat.com (int-mx07.intmail.prod.int.phx2.redhat.com [10.5.11.22]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx01.redhat.com (Postfix) with ESMTPS id 623BC10054E3; Tue, 10 Dec 2019 17:16:39 +0000 (UTC) Received: from ovpn-205-189.brq.redhat.com (ovpn-205-189.brq.redhat.com [10.40.205.189]) by smtp.corp.redhat.com (Postfix) with ESMTPS id 907081001B03; Tue, 10 Dec 2019 17:16:36 +0000 (UTC) Message-ID: Subject: Re: [PATCH v1 0/5] target/arm/kvm: Provide an option to adjust virtual time From: Andrea Bolognani To: Andrew Jones Cc: Peter Maydell , Marc Zyngier , qemu-arm , Richard Henderson , bijan.mottahedeh@oracle.com, QEMU Developers Date: Tue, 10 Dec 2019 18:16:33 +0100 In-Reply-To: <20191210160825.ioah26u36eu2i3z2@kamzik.brq.redhat.com> References: <20191206155327.7adiyjjkjh56mg2t@kamzik.brq.redhat.com> <596d07e933cb4da48dbba5b492e81a2438e78a2f.camel@redhat.com> <20191210110531.psjzlikir2ep2omo@kamzik.brq.redhat.com> <20191210133254.22vcpvr3eabcnthe@kamzik.brq.redhat.com> <29add42daba074ab5bdbd462b2d377115fec7c3c.camel@redhat.com> <20191210143311.4sen6blhfhzop6zw@kamzik.brq.redhat.com> <20191210160825.ioah26u36eu2i3z2@kamzik.brq.redhat.com> User-Agent: Evolution 3.34.2 (3.34.2-1.fc31) MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.84 on 10.5.11.22 X-MC-Unique: m-J_QNgtMqWr3h-gqil5nQ-1 X-Mimecast-Spam-Score: 0 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: 7bit X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 205.139.110.120 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 10 Dec 2019 17:16:47 -0000 On Tue, 2019-12-10 at 17:08 +0100, Andrew Jones wrote: > I don't have a strong enough opinion about kvm-adjvtime vs. > kvm-no-adjvtime to insist one way or another. I agree double inversions > are easier to mess up, but I also like the way the '-no-' better > communicates that the default is [probably] 'yes'. > > All interested parties, please vote. I'll be sending v2 soon and I can > call this thing anything the majority (or the dominate minority) prefer. I like kvm-adjvtime better because it avoids the double negative, but on the other hand if the new default is be to adjust the time then I don't expect many people will actually need to use the parameter, so the name doesn't matter that much after all :) -- Andrea Bolognani / Red Hat / Virtualization From MAILER-DAEMON Tue Dec 10 14:12:02 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1iekvS-0002SG-9j for mharc-qemu-arm@gnu.org; Tue, 10 Dec 2019 14:12:02 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:50236) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iekvP-0002Pj-Qx for qemu-arm@nongnu.org; Tue, 10 Dec 2019 14:12:01 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1iekvO-0006Ju-5J for qemu-arm@nongnu.org; Tue, 10 Dec 2019 14:11:59 -0500 Received: from mail-il1-x141.google.com ([2607:f8b0:4864:20::141]:46005) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1iekvK-0006IX-7c; Tue, 10 Dec 2019 14:11:54 -0500 Received: by mail-il1-x141.google.com with SMTP id p8so17095545iln.12; Tue, 10 Dec 2019 11:11:54 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=Ir2OHURJgyd1utg6eQ0vao/9jZEovfcbKpNA4WxrXQE=; b=vS1r0KBqJBA0KkXC9R6Gj/Lk3TsRXyzJZNHTMZrQWNIes9KkdOTBjHurTY+NdnUUOc fCFDFTd9miTtWhLWWcis4/DA/SK/YoMWOhXlUvsBk5sqI2rjgo9KsW5PfQng5NVIKVD6 5Y/X1pvGGxf2O2g0QW32yhX0/np9lXeC8dwO2/KVTI1NYpR2spKI1vTSckTdtoOenatn jFbaFtQ5W0hgfLU2QMCQAdRkChosrMQaMKkmsDhSFcbMUehfHYC7IdUaMpD3uiJxRpIX xhtsG5+jtdmTSPf+CQNQDiGdeRKss/IOb6DEPAtrGhi6iOFtIUyAA0kvtk3Itf5jeImG Irjg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=Ir2OHURJgyd1utg6eQ0vao/9jZEovfcbKpNA4WxrXQE=; b=JbWYO0FDBx64Ln9J0LrymHn9a21RENGuj3U9pc/ZrDYU7zZoMJU42tPefPlca4rPMy 1XgeFClp0M8gbBjnW4QqNM+D6b5oRDu3xUwNDTsKM5wy9J0UoxgwQrm5pFJmy8NkPkto 0kZ6BUNmjH5g4iEfn7xuYT6L+IfVJAO3nY8wpm400OmNMse6JXwZdL3U7u1m9vZRSBYT g9B+SKy3tDhNBdE1l0BM2Dq8xKwUp0odgV1n3q1UJMs6aX5vbllr4AxckcQOyFe/FdlK 8/w3JF1i6UlkqbTav3T11V4eSisfDJW/PpnDUwbr5J9l1H2qN2tBy4G31xFLBc/OVBU3 q4vQ== X-Gm-Message-State: APjAAAUhRiBviqTYmS3Ypy9iRSePLuh8I8fo7eRITxTH65JlSqbYgTcS Y4YSGg/Lre5qH0+jEZTbO8u6fyv/Lh5A246D4Hg= X-Google-Smtp-Source: APXvYqzgtN8tv6RKkQK2hIcwTx/XrI10X2jTUbCvL2w+pD3tAGg13w3eLXs6jc8bT6ZOSghkwMDr8H8dvcM7KBB9P1c= X-Received: by 2002:a92:d203:: with SMTP id y3mr4220515ily.28.1576005113295; Tue, 10 Dec 2019 11:11:53 -0800 (PST) MIME-Version: 1.0 References: <20191202210947.3603-1-nieklinnenbank@gmail.com> <20191202210947.3603-5-nieklinnenbank@gmail.com> <4a900e8d-d803-5c58-5a4b-879cce5970b4@redhat.com> <20191210082932.teizmu3nco3ndjel@sirius.home.kraxel.org> In-Reply-To: <20191210082932.teizmu3nco3ndjel@sirius.home.kraxel.org> From: Niek Linnenbank Date: Tue, 10 Dec 2019 20:11:42 +0100 Message-ID: Subject: Re: [PATCH 04/10] arm: allwinner-h3: add USB host controller To: Gerd Hoffmann Cc: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= , QEMU Developers , Beniamino Galvani , Peter Maydell , qemu-arm Content-Type: multipart/alternative; boundary="000000000000f13ae605995e48fa" X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::141 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 10 Dec 2019 19:12:01 -0000 --000000000000f13ae605995e48fa Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Hi Gerd, On Tue, Dec 10, 2019 at 9:29 AM Gerd Hoffmann wrote: > On Tue, Dec 10, 2019 at 08:56:02AM +0100, Philippe Mathieu-Daud=C3=A9 wro= te: > > On 12/2/19 10:09 PM, Niek Linnenbank wrote: > > > The Allwinner H3 System on Chip contains multiple USB 2.0 bus > > > connections which provide software access using the Enhanced > > > Host Controller Interface (EHCI) and Open Host Controller > > > Interface (OHCI) interfaces. This commit adds support for > > > both interfaces in the Allwinner H3 System on Chip. > > > > > > Signed-off-by: Niek Linnenbank > > > --- > > > hw/arm/allwinner-h3.c | 20 ++++++++++++++++++++ > > > hw/usb/hcd-ehci-sysbus.c | 17 +++++++++++++++++ > > > hw/usb/hcd-ehci.h | 1 + > > > > Cc'ing Gerd, the maintainer of these files. > > Looks all reasonable. > Reviewed-by: Gerd Hoffmann > > (assuming this will be merged through arm tree not usb). > Thanks for reviewing! I'll add the tag to the commit message. Regards, Niek > > > > > Reviewed-by: Philippe Mathieu-Daud=C3=A9 > > > > > 3 files changed, 38 insertions(+) > > > > > > diff --git a/hw/arm/allwinner-h3.c b/hw/arm/allwinner-h3.c > > > index 5566e979ec..afeb49c0ac 100644 > > > --- a/hw/arm/allwinner-h3.c > > > +++ b/hw/arm/allwinner-h3.c > > > @@ -26,6 +26,7 @@ > > > #include "hw/sysbus.h" > > > #include "hw/arm/allwinner-h3.h" > > > #include "hw/misc/unimp.h" > > > +#include "hw/usb/hcd-ehci.h" > > > #include "sysemu/sysemu.h" > > > static void aw_h3_init(Object *obj) > > > @@ -183,6 +184,25 @@ static void aw_h3_realize(DeviceState *dev, Erro= r > **errp) > > > } > > > sysbus_mmio_map(SYS_BUS_DEVICE(&s->ccu), 0, AW_H3_CCU_BASE); > > > + /* Universal Serial Bus */ > > > + sysbus_create_simple(TYPE_AW_H3_EHCI, AW_H3_EHCI0_BASE, > > > + s->irq[AW_H3_GIC_SPI_EHCI0]); > > > + sysbus_create_simple(TYPE_AW_H3_EHCI, AW_H3_EHCI1_BASE, > > > + s->irq[AW_H3_GIC_SPI_EHCI1]); > > > + sysbus_create_simple(TYPE_AW_H3_EHCI, AW_H3_EHCI2_BASE, > > > + s->irq[AW_H3_GIC_SPI_EHCI2]); > > > + sysbus_create_simple(TYPE_AW_H3_EHCI, AW_H3_EHCI3_BASE, > > > + s->irq[AW_H3_GIC_SPI_EHCI3]); > > > + > > > + sysbus_create_simple("sysbus-ohci", AW_H3_OHCI0_BASE, > > > + s->irq[AW_H3_GIC_SPI_OHCI0]); > > > + sysbus_create_simple("sysbus-ohci", AW_H3_OHCI1_BASE, > > > + s->irq[AW_H3_GIC_SPI_OHCI1]); > > > + sysbus_create_simple("sysbus-ohci", AW_H3_OHCI2_BASE, > > > + s->irq[AW_H3_GIC_SPI_OHCI2]); > > > + sysbus_create_simple("sysbus-ohci", AW_H3_OHCI3_BASE, > > > + s->irq[AW_H3_GIC_SPI_OHCI3]); > > > + > > > /* UART */ > > > if (serial_hd(0)) { > > > serial_mm_init(get_system_memory(), AW_H3_UART0_REG_BASE, 2= , > > > diff --git a/hw/usb/hcd-ehci-sysbus.c b/hw/usb/hcd-ehci-sysbus.c > > > index 020211fd10..174c3446ef 100644 > > > --- a/hw/usb/hcd-ehci-sysbus.c > > > +++ b/hw/usb/hcd-ehci-sysbus.c > > > @@ -145,6 +145,22 @@ static const TypeInfo ehci_exynos4210_type_info = =3D > { > > > .class_init =3D ehci_exynos4210_class_init, > > > }; > > > +static void ehci_aw_h3_class_init(ObjectClass *oc, void *data) > > > +{ > > > + SysBusEHCIClass *sec =3D SYS_BUS_EHCI_CLASS(oc); > > > + DeviceClass *dc =3D DEVICE_CLASS(oc); > > > + > > > + sec->capsbase =3D 0x0; > > > + sec->opregbase =3D 0x10; > > > + set_bit(DEVICE_CATEGORY_USB, dc->categories); > > > +} > > > + > > > +static const TypeInfo ehci_aw_h3_type_info =3D { > > > + .name =3D TYPE_AW_H3_EHCI, > > > + .parent =3D TYPE_SYS_BUS_EHCI, > > > + .class_init =3D ehci_aw_h3_class_init, > > > +}; > > > + > > > static void ehci_tegra2_class_init(ObjectClass *oc, void *data) > > > { > > > SysBusEHCIClass *sec =3D SYS_BUS_EHCI_CLASS(oc); > > > @@ -267,6 +283,7 @@ static void ehci_sysbus_register_types(void) > > > type_register_static(&ehci_platform_type_info); > > > type_register_static(&ehci_xlnx_type_info); > > > type_register_static(&ehci_exynos4210_type_info); > > > + type_register_static(&ehci_aw_h3_type_info); > > > type_register_static(&ehci_tegra2_type_info); > > > type_register_static(&ehci_ppc4xx_type_info); > > > type_register_static(&ehci_fusbh200_type_info); > > > diff --git a/hw/usb/hcd-ehci.h b/hw/usb/hcd-ehci.h > > > index 0298238f0b..edb59311c4 100644 > > > --- a/hw/usb/hcd-ehci.h > > > +++ b/hw/usb/hcd-ehci.h > > > @@ -342,6 +342,7 @@ typedef struct EHCIPCIState { > > > #define TYPE_SYS_BUS_EHCI "sysbus-ehci-usb" > > > #define TYPE_PLATFORM_EHCI "platform-ehci-usb" > > > #define TYPE_EXYNOS4210_EHCI "exynos4210-ehci-usb" > > > +#define TYPE_AW_H3_EHCI "aw-h3-ehci-usb" > > > #define TYPE_TEGRA2_EHCI "tegra2-ehci-usb" > > > #define TYPE_PPC4xx_EHCI "ppc4xx-ehci-usb" > > > #define TYPE_FUSBH200_EHCI "fusbh200-ehci-usb" > > > > > > > --=20 Niek Linnenbank --000000000000f13ae605995e48fa Content-Type: text/html; charset="UTF-8" Content-Transfer-Encoding: quoted-printable
Hi Gerd,

<= div class=3D"gmail_quote">
On Tue, Dec= 10, 2019 at 9:29 AM Gerd Hoffmann <kraxel@redhat.com> wrote:
On Tue, Dec 10, 2019 at 08:56:02AM +0100, Philippe Mathie= u-Daud=C3=A9 wrote:
> On 12/2/19 10:09 PM, Niek Linnenbank wrote:
> > The Allwinner H3 System on Chip contains multiple USB 2.0 bus
> > connections which provide software access using the Enhanced
> > Host Controller Interface (EHCI) and Open Host Controller
> > Interface (OHCI) interfaces. This commit adds support for
> > both interfaces in the Allwinner H3 System on Chip.
> >
> > Signed-off-by: Niek Linnenbank <nieklinnenbank@gmail.com>
> > ---
> >=C2=A0 =C2=A0hw/arm/allwinner-h3.c=C2=A0 =C2=A0 | 20 +++++++++++++= +++++++
> >=C2=A0 =C2=A0hw/usb/hcd-ehci-sysbus.c | 17 +++++++++++++++++
> >=C2=A0 =C2=A0hw/usb/hcd-ehci.h=C2=A0 =C2=A0 =C2=A0 =C2=A0 |=C2=A0 = 1 +
>
> Cc'ing Gerd, the maintainer of these files.

Looks all reasonable.
Reviewed-by: Gerd Hoffmann <kraxel@redhat.com>

(assuming this will be merged through arm tree not usb).

Thanks for reviewing! I'll add the tag to the commit = message.

Regards,
Niek

>
> Reviewed-by: Philippe Mathieu-Daud=C3=A9 <philmd@redhat.com>
>
> >=C2=A0 =C2=A03 files changed, 38 insertions(+)
> >
> > diff --git a/hw/arm/allwinner-h3.c b/hw/arm/allwinner-h3.c
> > index 5566e979ec..afeb49c0ac 100644
> > --- a/hw/arm/allwinner-h3.c
> > +++ b/hw/arm/allwinner-h3.c
> > @@ -26,6 +26,7 @@
> >=C2=A0 =C2=A0#include "hw/sysbus.h"
> >=C2=A0 =C2=A0#include "hw/arm/allwinner-h3.h"
> >=C2=A0 =C2=A0#include "hw/misc/unimp.h"
> > +#include "hw/usb/hcd-ehci.h"
> >=C2=A0 =C2=A0#include "sysemu/sysemu.h"
> >=C2=A0 =C2=A0static void aw_h3_init(Object *obj)
> > @@ -183,6 +184,25 @@ static void aw_h3_realize(DeviceState *dev, = Error **errp)
> >=C2=A0 =C2=A0 =C2=A0 =C2=A0}
> >=C2=A0 =C2=A0 =C2=A0 =C2=A0sysbus_mmio_map(SYS_BUS_DEVICE(&s-&= gt;ccu), 0, AW_H3_CCU_BASE);
> > +=C2=A0 =C2=A0 /* Universal Serial Bus */
> > +=C2=A0 =C2=A0 sysbus_create_simple(TYPE_AW_H3_EHCI, AW_H3_EHCI0_= BASE,
> > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0s->irq[AW_H3_GIC_SPI_EHCI0]);
> > +=C2=A0 =C2=A0 sysbus_create_simple(TYPE_AW_H3_EHCI, AW_H3_EHCI1_= BASE,
> > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0s->irq[AW_H3_GIC_SPI_EHCI1]);
> > +=C2=A0 =C2=A0 sysbus_create_simple(TYPE_AW_H3_EHCI, AW_H3_EHCI2_= BASE,
> > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0s->irq[AW_H3_GIC_SPI_EHCI2]);
> > +=C2=A0 =C2=A0 sysbus_create_simple(TYPE_AW_H3_EHCI, AW_H3_EHCI3_= BASE,
> > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0s->irq[AW_H3_GIC_SPI_EHCI3]);
> > +
> > +=C2=A0 =C2=A0 sysbus_create_simple("sysbus-ohci", AW_H= 3_OHCI0_BASE,
> > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0s->irq[AW_H3_GIC_SPI_OHCI0]);
> > +=C2=A0 =C2=A0 sysbus_create_simple("sysbus-ohci", AW_H= 3_OHCI1_BASE,
> > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0s->irq[AW_H3_GIC_SPI_OHCI1]);
> > +=C2=A0 =C2=A0 sysbus_create_simple("sysbus-ohci", AW_H= 3_OHCI2_BASE,
> > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0s->irq[AW_H3_GIC_SPI_OHCI2]);
> > +=C2=A0 =C2=A0 sysbus_create_simple("sysbus-ohci", AW_H= 3_OHCI3_BASE,
> > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0s->irq[AW_H3_GIC_SPI_OHCI3]);
> > +
> >=C2=A0 =C2=A0 =C2=A0 =C2=A0/* UART */
> >=C2=A0 =C2=A0 =C2=A0 =C2=A0if (serial_hd(0)) {
> >=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0serial_mm_init(get_system= _memory(), AW_H3_UART0_REG_BASE, 2,
> > diff --git a/hw/usb/hcd-ehci-sysbus.c b/hw/usb/hcd-ehci-sysbus.c<= br> > > index 020211fd10..174c3446ef 100644
> > --- a/hw/usb/hcd-ehci-sysbus.c
> > +++ b/hw/usb/hcd-ehci-sysbus.c
> > @@ -145,6 +145,22 @@ static const TypeInfo ehci_exynos4210_type_i= nfo =3D {
> >=C2=A0 =C2=A0 =C2=A0 =C2=A0.class_init=C2=A0 =C2=A0 =3D ehci_exyno= s4210_class_init,
> >=C2=A0 =C2=A0};
> > +static void ehci_aw_h3_class_init(ObjectClass *oc, void *data) > > +{
> > +=C2=A0 =C2=A0 SysBusEHCIClass *sec =3D SYS_BUS_EHCI_CLASS(oc); > > +=C2=A0 =C2=A0 DeviceClass *dc =3D DEVICE_CLASS(oc);
> > +
> > +=C2=A0 =C2=A0 sec->capsbase =3D 0x0;
> > +=C2=A0 =C2=A0 sec->opregbase =3D 0x10;
> > +=C2=A0 =C2=A0 set_bit(DEVICE_CATEGORY_USB, dc->categories); > > +}
> > +
> > +static const TypeInfo ehci_aw_h3_type_info =3D {
> > +=C2=A0 =C2=A0 .name=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =3D TYPE_A= W_H3_EHCI,
> > +=C2=A0 =C2=A0 .parent=C2=A0 =C2=A0 =C2=A0 =C2=A0 =3D TYPE_SYS_BU= S_EHCI,
> > +=C2=A0 =C2=A0 .class_init=C2=A0 =C2=A0 =3D ehci_aw_h3_class_init= ,
> > +};
> > +
> >=C2=A0 =C2=A0static void ehci_tegra2_class_init(ObjectClass *oc, v= oid *data)
> >=C2=A0 =C2=A0{
> >=C2=A0 =C2=A0 =C2=A0 =C2=A0SysBusEHCIClass *sec =3D SYS_BUS_EHCI_C= LASS(oc);
> > @@ -267,6 +283,7 @@ static void ehci_sysbus_register_types(void)<= br> > >=C2=A0 =C2=A0 =C2=A0 =C2=A0type_register_static(&ehci_platform= _type_info);
> >=C2=A0 =C2=A0 =C2=A0 =C2=A0type_register_static(&ehci_xlnx_typ= e_info);
> >=C2=A0 =C2=A0 =C2=A0 =C2=A0type_register_static(&ehci_exynos42= 10_type_info);
> > +=C2=A0 =C2=A0 type_register_static(&ehci_aw_h3_type_info); > >=C2=A0 =C2=A0 =C2=A0 =C2=A0type_register_static(&ehci_tegra2_t= ype_info);
> >=C2=A0 =C2=A0 =C2=A0 =C2=A0type_register_static(&ehci_ppc4xx_t= ype_info);
> >=C2=A0 =C2=A0 =C2=A0 =C2=A0type_register_static(&ehci_fusbh200= _type_info);
> > diff --git a/hw/usb/hcd-ehci.h b/hw/usb/hcd-ehci.h
> > index 0298238f0b..edb59311c4 100644
> > --- a/hw/usb/hcd-ehci.h
> > +++ b/hw/usb/hcd-ehci.h
> > @@ -342,6 +342,7 @@ typedef struct EHCIPCIState {
> >=C2=A0 =C2=A0#define TYPE_SYS_BUS_EHCI "sysbus-ehci-usb"=
> >=C2=A0 =C2=A0#define TYPE_PLATFORM_EHCI "platform-ehci-usb&qu= ot;
> >=C2=A0 =C2=A0#define TYPE_EXYNOS4210_EHCI "exynos4210-ehci-us= b"
> > +#define TYPE_AW_H3_EHCI "aw-h3-ehci-usb"
> >=C2=A0 =C2=A0#define TYPE_TEGRA2_EHCI "tegra2-ehci-usb"<= br> > >=C2=A0 =C2=A0#define TYPE_PPC4xx_EHCI "ppc4xx-ehci-usb"<= br> > >=C2=A0 =C2=A0#define TYPE_FUSBH200_EHCI "fusbh200-ehci-usb&qu= ot;
> >
>



--
Niek Linnenbank

--000000000000f13ae605995e48fa-- From MAILER-DAEMON Tue Dec 10 14:14:38 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1iekxy-00045Q-Dl for mharc-qemu-arm@gnu.org; Tue, 10 Dec 2019 14:14:38 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:51293) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iekxs-000438-FE for qemu-arm@nongnu.org; Tue, 10 Dec 2019 14:14:33 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1iekxp-0007ip-SF for qemu-arm@nongnu.org; Tue, 10 Dec 2019 14:14:30 -0500 Received: from us-smtp-delivery-1.mimecast.com ([207.211.31.120]:34120 helo=us-smtp-1.mimecast.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1iekxp-0007go-Ox for qemu-arm@nongnu.org; Tue, 10 Dec 2019 14:14:29 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1576005267; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=QYz/6hrb7cqbBbeqZPE4uGuRtTwhiU/auYfMMLJF+NI=; b=HQGknXgxhsxyJKxdsTREfC44pus7vIDuoA6rwAWPCqSfI2OME0mxX45Zt+ADtd6EWffXHq MoY79k5E97/7E3EN7iFmLoZTTJ6a6qSsLB+misMuE3Da6vFqJpdXXo8kzBCfu1/2nK7tpm kc/HOdz1w/wpjhwf5xsUIv5/yhuEs58= Received: from mail-qv1-f69.google.com (mail-qv1-f69.google.com [209.85.219.69]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-381-TXh9UueoNSeYD6SePEVmHg-1; Tue, 10 Dec 2019 14:14:26 -0500 Received: by mail-qv1-f69.google.com with SMTP id g15so7466903qvk.11 for ; Tue, 10 Dec 2019 11:14:26 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:in-reply-to:user-agent; bh=t5NRopCXac/TaVRyYxckA1Ih+aNBJ6X1xXjY0vMyIYY=; b=arbFDJHe5TGOY3/G0hqNg+pZrHT6zdFy5BT2LxdN1s9QsZJTtyB6v8bk8yF2oT0NyS jbu0XHMTFlMQqKw/tDdww1OzRNR4UfvDqXhReK3a2rq/FRhBtIqfhx58Rnh7eQvg8MeM 1cZ8yx31z6DlSAhSdbpr1HKSzn4Y/NRBoF2WLRgzWj0jpjkq3SuJNE8VUS9y+/38JF58 JupzLWognZt9wmrpVLEUsDEROHx7EFQ2bb5kyEZjwFgkQ4b0Emn6jYWw4dnNL9/Jf9Jk BWBJAjKIrZl/EaBJd+HILBdSGaEvubhogwiTPNmY6sO0qlRipqfpXL6S2gSBf7LwJ86t cYYg== X-Gm-Message-State: APjAAAWFusneLP7aAHfpBM4jIM4byjl+pgxw+TYcXojVKWFzsYEg+ILQ A4jUy0ehz94dX9kYylMIeqGKCLjgumm/saFHrFsfPAQ+84R6xFS0faXZ7HgZzObWEYCbl+KKe9S r21AHD82K241a X-Received: by 2002:a05:620a:2010:: with SMTP id c16mr33446196qka.386.1576005265880; Tue, 10 Dec 2019 11:14:25 -0800 (PST) X-Google-Smtp-Source: APXvYqzLgHPu+HZpHBt7nfHOD0/Jgw6wPXTMskIpbGw97FKu4VzSaxBGLM63tD2FV7Gx0R0faTKS6w== X-Received: by 2002:a05:620a:2010:: with SMTP id c16mr33446170qka.386.1576005265597; Tue, 10 Dec 2019 11:14:25 -0800 (PST) Received: from xz-x1 ([104.156.64.74]) by smtp.gmail.com with ESMTPSA id e2sm1211935qkb.112.2019.12.10.11.14.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 10 Dec 2019 11:14:24 -0800 (PST) Date: Tue, 10 Dec 2019 14:14:23 -0500 From: Peter Xu To: Eric Auger Cc: eric.auger.pro@gmail.com, qemu-devel@nongnu.org, qemu-arm@nongnu.org, peter.maydell@linaro.org, mst@redhat.com, armbru@redhat.com, jean-philippe.brucker@arm.com, bharatb.linux@gmail.com, yang.zhong@intel.com, dgilbert@redhat.com, quintela@redhat.com, kevin.tian@intel.com, tnowicki@marvell.com Subject: Re: [PATCH for-5.0 v11 03/20] virtio-iommu: Decode the command payload Message-ID: <20191210191423.GH3352@xz-x1> References: <20191122182943.4656-1-eric.auger@redhat.com> <20191122182943.4656-4-eric.auger@redhat.com> MIME-Version: 1.0 In-Reply-To: <20191122182943.4656-4-eric.auger@redhat.com> User-Agent: Mutt/1.12.1 (2019-06-15) X-MC-Unique: TXh9UueoNSeYD6SePEVmHg-1 X-Mimecast-Spam-Score: 0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable Content-Disposition: inline X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 207.211.31.120 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 10 Dec 2019 19:14:33 -0000 On Fri, Nov 22, 2019 at 07:29:26PM +0100, Eric Auger wrote: > This patch adds the command payload decoding and > introduces the functions that will do the actual > command handling. Those functions are not yet implemented. >=20 > Signed-off-by: Eric Auger I would simply squash this into previous patch to avoid removing lines from newly introduced, but this is ok too so to keep Jean's r-b: Reviewed-by: Peter Xu --=20 Peter Xu From MAILER-DAEMON Tue Dec 10 14:15:10 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1iekyT-0004c2-S5 for mharc-qemu-arm@gnu.org; Tue, 10 Dec 2019 14:15:09 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:51494) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iekyP-0004YA-HK for qemu-arm@nongnu.org; Tue, 10 Dec 2019 14:15:07 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1iekyN-0007wP-9V for qemu-arm@nongnu.org; Tue, 10 Dec 2019 14:15:05 -0500 Received: from mail-il1-x143.google.com ([2607:f8b0:4864:20::143]:40512) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1iekyI-0007uE-I6; Tue, 10 Dec 2019 14:14:58 -0500 Received: by mail-il1-x143.google.com with SMTP id b15so17132461ila.7; Tue, 10 Dec 2019 11:14:58 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=alOcQcgvp6XCV+enV3qG3D/mHnMQSHhndppzu+ZmGrM=; b=THJR6EYuFy2c4ffOJwBwV2tVu7xDWwN+anvQQK9k3M2/FJEUncl50RXrUcdIdNqPez +HU/QO0vem93nw8qdJaPXnhU/VweuNwD+uk5WLq+r9IKBzxN2zBjPR6lSRhSSrqhGSmj LhBLPOIhkMhc9VX5Hdx078QKKYdAAhQfRKrLhDpyYCXDXdH7Jce7ECcmf0T/Junj7IfP mmOCXfjn+lYE4q8nKrnldPGoCOBW1mCkZPvnIkK/mnfaM1HZYrgIfIADCauHxo7iNPAT Chr5P3U9io3+7t1ZeCsEybz4mXcKB3vsR4Tk3fbAV7YKP7YLBT/+ZJ9cUMfxxKziU3k/ fmDw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=alOcQcgvp6XCV+enV3qG3D/mHnMQSHhndppzu+ZmGrM=; b=d8Jmfp6cODObyXtY9K1KQ/TuO9W62pI6mOEzGOe8Hfwr6/IoIZebTW3kWWod9OKG8y FdVnxVrSya3co0vYy2wOkmnC2JQA9rLSeUI/7j6OdQVZ3QvjSPpIaqN0JQvJ3imvzXe0 L5uYqRSqxgSZ6P/lII1Sha6m8tC06bqUYf8hB1LrvCyorHQK1pbKZmkYU4T82p0Yo8UE AC1OxNmVU1VTYvDwvQOvtvVX26RWQhhlbzT5n8h+SsEi/tvRTbB1MHnxcCNOF+lXxCN/ +2uuQMWZeQskBAnltVFhBv9DSLhzt22MY6yB37daILe6nIC1B1yQu1yYO3lpbFdWD3UE /LcQ== X-Gm-Message-State: APjAAAUzovezeHwCXfhWSBoeEj4M9X5dWoUqEk/CgOpVBYc/4CnbKBI4 ULcp10vGEkvZGjMrI+PEaTeu6VhWFvigDBdrHh0= X-Google-Smtp-Source: APXvYqzzy5UFNF3Yf3fNPlPr19aedwr9sNHhvCo1u1K6NZSCjdCr3w/j8e7uLYy2nzHwmQMpJvqGNEWfL/egz8IeIyY= X-Received: by 2002:a92:5a45:: with SMTP id o66mr33950807ilb.67.1576005297574; Tue, 10 Dec 2019 11:14:57 -0800 (PST) MIME-Version: 1.0 References: <20191202210947.3603-1-nieklinnenbank@gmail.com> <20191202210947.3603-3-nieklinnenbank@gmail.com> In-Reply-To: From: Niek Linnenbank Date: Tue, 10 Dec 2019 20:14:46 +0100 Message-ID: Subject: Re: [PATCH 02/10] hw: arm: add Xunlong Orange Pi PC machine To: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= Cc: QEMU Developers , Beniamino Galvani , Peter Maydell , qemu-arm Content-Type: multipart/alternative; boundary="000000000000ed1a5205995e531e" X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::143 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 10 Dec 2019 19:15:07 -0000 --000000000000ed1a5205995e531e Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Hi Philippe, On Tue, Dec 10, 2019 at 9:59 AM Philippe Mathieu-Daud=C3=A9 wrote: > On 12/6/19 11:15 PM, Niek Linnenbank wrote: > [...] > > > > +static void orangepi_machine_init(MachineClass *mc) > > > > +{ > > > > + mc->desc =3D "Orange Pi PC"; > > > > + mc->init =3D orangepi_init; > > > > + mc->units_per_default_bus =3D 1; > > > > + mc->min_cpus =3D AW_H3_NUM_CPUS; > > > > + mc->max_cpus =3D AW_H3_NUM_CPUS; > > > > + mc->default_cpus =3D AW_H3_NUM_CPUS; > > > > > > mc->default_cpu_type =3D > ARM_CPU_TYPE_NAME("cortex-a7"); > > > > > > > + mc->ignore_memory_transaction_failures =3D true; > > > > > > You should not use this flag in new design. See the > > documentation in > > > include/hw/boards.h: > > > > > > * @ignore_memory_transaction_failures: > > > * [...] New board models > > > * should instead use "unimplemented-device" for all > memory > > > ranges where > > > * the guest will attempt to probe for a device that > > QEMU doesn't > > > * implement and a stub device is required. > > > > > > You already use the "unimplemented-device". > > > > > > Thanks, I'm working on this now. I think that at least I'll need > > to add > > > all of the devices mentioned in the 4.1 Memory Mapping chapter o= f > > the > > > datasheet > > > as an unimplemented device. Previously I only added some that I > > thought > > > were relevant. > > > > > > I added all the missing devices as unimplemented and removed the > > > ignore_memory_transaction_failures flag > > > > I was going to say, "instead of adding *all* the devices regions yo= u > > can > > add the likely bus decoding regions", probably: > > > > 0x01c0.0000 128KiB AMBA AXI > > 0x01c2.0000 64KiB AMBA APB > > > > But too late. > > > > > > Hehe its okey, I can change it to whichever is preferable: the minimum > set > > with unimplemented device entries to get a working linux kernel / u-boo= t > or > > just cover the full memory space from the datasheet. My initial thought > > was that if > > we only provide the minimum set, and the linux kernel later adds a new > > driver for a device > > which is not marked unimplemented, it will trigger the data abort and > > potentially resulting in a non-booting kernel. > > > > But I'm not sure what is normally done here. I do see other board files > > using the create_unimplemented_device() function, > > but I dont know if they are covering the whole memory space or not. > > If they don't cover all memory regions, the guest code can trigger a > data abort indeed. Since we don't know the memory layout of old board, > they are still supported with ignore_memory_transaction_failures=3Dtrue, > so guest still run unaffected. > We expect new boards to implement the minimum layout. > As long as your guest is happy and usable, UNIMP devices are fine, > either as big region or individual device (this requires someone with > access to the datasheet to verify). If you can add a UNIMP for each > device - which is what you did - it is even better because the the unimp > access log will be more useful, having finer granularity. > > > I added all the missing devices as unimplemented and removed the > > ignore_memory_transaction_failures flag > > IOW, you already did the best you could do :) > > > > from the machine. Now it seems Linux gets a data abort while > > probing the > > > uart1 serial device at 0x01c28400, > > > > Did you add the UART1 as UNIMP or 16550? > > > > > > I discovered what goes wrong here. See this kernel oops message: > > > > [ 1.084985] [f08600f8] *pgd=3D6f00a811, *pte=3D01c28653, *ppte=3D01c= 28453 > > [ 1.085564] Internal error: : 8 [#1] SMP ARM > > [ 1.085698] Modules linked in: > > [ 1.085940] CPU: 0 PID: 1 Comm: swapper/0 Not tainted > 5.4.0-11747-g2f13437b8917 #4 > > [ 1.085968] Hardware name: Allwinner sun8i Family > > [ 1.086447] PC is at dw8250_setup_port+0x10/0x10c > > [ 1.086478] LR is at dw8250_probe+0x500/0x56c > > > > It tries to access the UART0 at base address 0x01c28400, which I did > > provide. The strange > > thing is that is accesses offset 0xf8, thus address 0x01c284f8. The > > datasheet does not mention this register > > but if we provide the 1KiB (0x400) I/O space it should at least read as > > zero and writes ignored. Unfortunately the emulated > > serial driver only maps a small portion until 0x1f: > > > > (qemu) info mtree > > ... > > 0000000001c28000-0000000001c2801f (prio 0, i/o): serial > > 0000000001c28400-0000000001c2841f (prio 0, i/o): serial > > 0000000001c28800-0000000001c2881f (prio 0, i/o): serial > > > > > > Apparently, the register that the mainline linux kernel is using is > > DesignWare specific: > > > > drivers/tty/serial/8250/8250_dwlib.c:13: > > > > /* Offsets for the DesignWare specific registers */ > > #define DW_UART_DLF<--->0xc0 /* Divisor Latch Fraction Register */ > > #define DW_UART_CPR<--->0xf4 /* Component Parameter Register */ > > #define DW_UART_UCV<--->0xf8 /* UART Component Version */ > > > > I tried to find a way to increase the memory mapped size of the serial > > device I created with serial_mm_init(), > > but I don't think its possible with that interface. > > > > I did manage to get it working by overlaying the UART0 with another > > unimplemented device > > that does have an I/O size of 0x400, but I guess that is probably not > > the solution we are looking for? > > IMHO this is the correct solution :) > > Memory regions have priority. By default a device has priority 0, and > UNIMP device has priority -1000. > > So you can use: > > serial_mm_init(get_system_memory(), AW_H3_UART0_REG_BASE, 2, > s->irq[AW_H3_GIC_SPI_UART0], 115200, > serial_hd(0), DEVICE_NATIVE_ENDIAN); > create_unimplemented_device("DesignWare-uart",\ > AW_H3_UART0_REG_BASE, > 0x400); > > Now it makes much more sense to me, thanks a lot for explaining this! Allright, I'll use this approach to finish the work for removing mc->ignore_memory_transaction_failures. Regards, Niek > (Or cleaner, add a create_designware_uart(...) function that does both). > > (qemu) info mtree > ... > 0000000001c28000-0000000001c2801f (prio 0, i/o): serial > 0000000001c28000-0000000001c283ff (prio -1000, i/o): DesignWare-uart > > You could create an UNIMP region of 0x400 - 0x20 =3D 0x3e0, but that woul= d > appear this is a different device, so I don't recommend that. > > > I wonder, did any of the other SoC / boards have this problem when > > removing mc->ignore_memory_transaction_failures? > > --=20 Niek Linnenbank --000000000000ed1a5205995e531e Content-Type: text/html; charset="UTF-8" Content-Transfer-Encoding: quoted-printable
Hi Philippe,

=
On Tue, Dec 10, 2019 at 9:59 AM Phili= ppe Mathieu-Daud=C3=A9 <philmd@redh= at.com> wrote:
On 12/6/19 11:15 PM, Niek Linnenbank wrote:
[...]
>=C2=A0 =C2=A0 =C2=A0 >=C2=A0 =C2=A0 =C2=A0 > +static void orangep= i_machine_init(MachineClass *mc)
>=C2=A0 =C2=A0 =C2=A0 >=C2=A0 =C2=A0 =C2=A0 > +{
>=C2=A0 =C2=A0 =C2=A0 >=C2=A0 =C2=A0 =C2=A0 > +=C2=A0 =C2=A0 mc-&g= t;desc =3D "Orange Pi PC";
>=C2=A0 =C2=A0 =C2=A0 >=C2=A0 =C2=A0 =C2=A0 > +=C2=A0 =C2=A0 mc-&g= t;init =3D orangepi_init;
>=C2=A0 =C2=A0 =C2=A0 >=C2=A0 =C2=A0 =C2=A0 > +=C2=A0 =C2=A0 mc-&g= t;units_per_default_bus =3D 1;
>=C2=A0 =C2=A0 =C2=A0 >=C2=A0 =C2=A0 =C2=A0 > +=C2=A0 =C2=A0 mc-&g= t;min_cpus =3D AW_H3_NUM_CPUS;
>=C2=A0 =C2=A0 =C2=A0 >=C2=A0 =C2=A0 =C2=A0 > +=C2=A0 =C2=A0 mc-&g= t;max_cpus =3D AW_H3_NUM_CPUS;
>=C2=A0 =C2=A0 =C2=A0 >=C2=A0 =C2=A0 =C2=A0 > +=C2=A0 =C2=A0 mc-&g= t;default_cpus =3D AW_H3_NUM_CPUS;
>=C2=A0 =C2=A0 =C2=A0 >
>=C2=A0 =C2=A0 =C2=A0 >=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 mc->default_cpu_type =3D ARM_CPU_TYPE_NAME("cortex-a7"); >=C2=A0 =C2=A0 =C2=A0 >
>=C2=A0 =C2=A0 =C2=A0 >=C2=A0 =C2=A0 =C2=A0 > +=C2=A0 =C2=A0 mc-&g= t;ignore_memory_transaction_failures =3D true;
>=C2=A0 =C2=A0 =C2=A0 >
>=C2=A0 =C2=A0 =C2=A0 >=C2=A0 =C2=A0 =C2=A0You should not use this fl= ag in new design. See the
>=C2=A0 =C2=A0 =C2=A0documentation in
>=C2=A0 =C2=A0 =C2=A0 >=C2=A0 =C2=A0 =C2=A0include/hw/boards.h:
>=C2=A0 =C2=A0 =C2=A0 >
>=C2=A0 =C2=A0 =C2=A0 >=C2=A0 =C2=A0 =C2=A0 =C2=A0 * @ignore_memory_t= ransaction_failures:
>=C2=A0 =C2=A0 =C2=A0 >=C2=A0 =C2=A0 =C2=A0 =C2=A0 *=C2=A0 =C2=A0 [..= .] New board models
>=C2=A0 =C2=A0 =C2=A0 >=C2=A0 =C2=A0 =C2=A0 =C2=A0 *=C2=A0 =C2=A0 sho= uld instead use "unimplemented-device" for all memory
>=C2=A0 =C2=A0 =C2=A0 >=C2=A0 =C2=A0 =C2=A0ranges where
>=C2=A0 =C2=A0 =C2=A0 >=C2=A0 =C2=A0 =C2=A0 =C2=A0 *=C2=A0 =C2=A0 the= guest will attempt to probe for a device that
>=C2=A0 =C2=A0 =C2=A0QEMU doesn't
>=C2=A0 =C2=A0 =C2=A0 >=C2=A0 =C2=A0 =C2=A0 =C2=A0 *=C2=A0 =C2=A0 imp= lement and a stub device is required.
>=C2=A0 =C2=A0 =C2=A0 >
>=C2=A0 =C2=A0 =C2=A0 >=C2=A0 =C2=A0 =C2=A0You already use the "= unimplemented-device".
>=C2=A0 =C2=A0 =C2=A0 >
>=C2=A0 =C2=A0 =C2=A0 > Thanks, I'm working on this now. I think = that at least I'll need
>=C2=A0 =C2=A0 =C2=A0to add
>=C2=A0 =C2=A0 =C2=A0 > all of the devices mentioned in the 4.1 Memor= y Mapping chapter of
>=C2=A0 =C2=A0 =C2=A0the
>=C2=A0 =C2=A0 =C2=A0 > datasheet
>=C2=A0 =C2=A0 =C2=A0 > as an unimplemented device. Previously I only= added some that I
>=C2=A0 =C2=A0 =C2=A0thought
>=C2=A0 =C2=A0 =C2=A0 > were relevant.
>=C2=A0 =C2=A0 =C2=A0 >
>=C2=A0 =C2=A0 =C2=A0 > I added all the missing devices as unimplemen= ted and removed the
>=C2=A0 =C2=A0 =C2=A0 > ignore_memory_transaction_failures flag
>
>=C2=A0 =C2=A0 =C2=A0I was going to say, "instead of adding *all* t= he devices regions you
>=C2=A0 =C2=A0 =C2=A0can
>=C2=A0 =C2=A0 =C2=A0add the likely bus decoding regions", probably= :
>
>=C2=A0 =C2=A0 =C2=A00x01c0.0000=C2=A0 =C2=A0128KiB=C2=A0 =C2=A0AMBA AXI=
>=C2=A0 =C2=A0 =C2=A00x01c2.0000=C2=A0 =C2=A064KiB=C2=A0 =C2=A0 AMBA APB=
>
>=C2=A0 =C2=A0 =C2=A0But too late.
>
>
> Hehe its okey, I can change it to whichever is preferable: the minimum= set
> with unimplemented device entries to get a working linux kernel / u-bo= ot or
> just cover the full memory space from the datasheet. My initial though= t
> was that if
> we only provide the minimum set, and the linux kernel later adds a new=
> driver for a device
> which is not marked unimplemented, it will trigger the data abort and =
> potentially resulting in a non-booting kernel.
>
> But I'm not sure what is normally done here. I do see other board = files
> using the create_unimplemented_device() function,
> but I dont know if they are covering the whole memory space or not.
If they don't cover all memory regions, the guest code can trigger a data abort indeed. Since we don't know the memory layout of old board, =
they are still supported with ignore_memory_transaction_failures=3Dtrue, so guest still run unaffected.
We expect new boards to implement the minimum layout.
As long as your guest is happy and usable, UNIMP devices are fine,
either as big region or individual device (this requires someone with
access to the datasheet to verify). If you can add a UNIMP for each
device - which is what you did - it is even better because the the unimp access log will be more useful, having finer granularity.

=C2=A0> I added all the missing devices as unimplemented and removed the=
=C2=A0> ignore_memory_transaction_failures flag

IOW, you already did the best you could do :)

>=C2=A0 =C2=A0 =C2=A0 > from the machine. Now it seems Linux gets a d= ata abort while
>=C2=A0 =C2=A0 =C2=A0probing the
>=C2=A0 =C2=A0 =C2=A0 > uart1 serial device at 0x01c28400,
>
>=C2=A0 =C2=A0 =C2=A0Did you add the UART1 as UNIMP or 16550?
>
>
> I discovered what goes wrong here. See this kernel oops message:
>
> [=C2=A0 =C2=A0 1.084985] [f08600f8] *pgd=3D6f00a811, *pte=3D01c28653, = *ppte=3D01c28453
> [=C2=A0 =C2=A0 1.085564] Internal error: : 8 [#1] SMP ARM
> [=C2=A0 =C2=A0 1.085698] Modules linked in:
> [=C2=A0 =C2=A0 1.085940] CPU: 0 PID: 1 Comm: swapper/0 Not tainted 5.4= .0-11747-g2f13437b8917 #4
> [=C2=A0 =C2=A0 1.085968] Hardware name: Allwinner sun8i Family
> [=C2=A0 =C2=A0 1.086447] PC is at dw8250_setup_port+0x10/0x10c
> [=C2=A0 =C2=A0 1.086478] LR is at dw8250_probe+0x500/0x56c
>
> It tries to access the UART0 at base address 0x01c28400, which I did <= br> > provide. The strange
> thing is that is accesses offset 0xf8, thus address 0x01c284f8. The > datasheet does not mention this register
> but if we provide the 1KiB (0x400) I/O space it should at least read a= s
> zero and writes ignored. Unfortunately the emulated
> serial driver only maps a small portion until 0x1f:
>
> (qemu) info mtree
> ...
>=C2=A0 =C2=A0 =C2=A0 0000000001c28000-0000000001c2801f (prio 0, i/o): s= erial
>=C2=A0 =C2=A0 =C2=A0 0000000001c28400-0000000001c2841f (prio 0, i/o): s= erial
>=C2=A0 =C2=A0 =C2=A0 0000000001c28800-0000000001c2881f (prio 0, i/o): s= erial
>
>
> Apparently, the register that the mainline linux kernel is using is > DesignWare specific:
>
> drivers/tty/serial/8250/8250_dwlib.c:13:
>
> /* Offsets for the DesignWare specific registers */
> #define DW_UART_DLF<--->0xc0 /* Divisor Latch Fraction Register = */
> #define DW_UART_CPR<--->0xf4 /* Component Parameter Register */<= br> > #define DW_UART_UCV<--->0xf8 /* UART Component Version */
>
> I tried to find a way to increase the memory mapped size of the serial=
> device I created with serial_mm_init(),
> but I don't think its possible with that interface.
>
> I did manage to get it working by overlaying the UART0 with another > unimplemented device
> that does have an I/O size of 0x400, but I guess that is probably not =
> the solution we are looking for?

IMHO this is the correct solution :)

Memory regions have priority. By default a device has priority 0, and
UNIMP device has priority -1000.

So you can use:

=C2=A0 =C2=A0 serial_mm_init(get_system_memory(), AW_H3_UART0_REG_BASE, 2,<= br> =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0s->= irq[AW_H3_GIC_SPI_UART0], 115200,
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0serial= _hd(0), DEVICE_NATIVE_ENDIAN);
=C2=A0 =C2=A0 create_unimplemented_device("DesignWare-uart",\
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 AW_H3_UART0_REG_BASE,
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 0x400);


Now it makes much more sense to me, th= anks a lot for explaining this!

Allright, I'll= use this approach to finish the work for removing mc->ignore_memory_tra= nsaction_failures.

Regards,
Niek
=
=C2=A0
(Or cleaner, add a create_designware_uart(...) function that does both).
(qemu) info mtree
...
=C2=A0 =C2=A0 0000000001c28000-0000000001c2801f (prio 0, i/o): serial
=C2=A0 =C2=A0 0000000001c28000-0000000001c283ff (prio -1000, i/o): DesignWa= re-uart

You could create an UNIMP region of 0x400 - 0x20 =3D 0x3e0, but that would =
appear this is a different device, so I don't recommend that.

=C2=A0> I wonder, did any of the other SoC / boards have this problem wh= en
=C2=A0> removing mc->ignore_memory_transaction_failures?



--
Niek Linnenbank

--000000000000ed1a5205995e531e-- From MAILER-DAEMON Tue Dec 10 14:17:34 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1iel0o-0006Gr-7G for mharc-qemu-arm@gnu.org; Tue, 10 Dec 2019 14:17:34 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:52507) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iel0e-0006A5-QI for qemu-arm@nongnu.org; Tue, 10 Dec 2019 14:17:29 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1iel0d-0000ka-7P for qemu-arm@nongnu.org; Tue, 10 Dec 2019 14:17:24 -0500 Received: from mail-io1-xd43.google.com ([2607:f8b0:4864:20::d43]:32906) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1iel0a-0000ia-0d; Tue, 10 Dec 2019 14:17:20 -0500 Received: by mail-io1-xd43.google.com with SMTP id s25so5323235iob.0; Tue, 10 Dec 2019 11:17:19 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=MD7YecZp3gunHf5drvkVKW7805f8VNuz6VEdbrGQghA=; b=i0KMhWl1rYgaUmevg5a5gU1Cn4e8YcTBFENVc5NjoDllpGlrbPb5bxa5jTSuZAtbZH E/4TKcs9qrvjkpKJotkVhnujB9qGGtAxiMWU7XK2wcgLgEO85cSxaLUQJedJwDcP0YYU /vKO8cgfqHffn6LsUcjQBX9m3oSfTXPcc4BY9iukK8qycCdRbNi4skmark/L4luKoSOP snA2udjJO1JrJiPjaHf2l5gzRFE+V3G+H0mcDAryS2f4SYJtXEaCUZjB2IiSKT5SGQbZ jCjXA0n2yIKy9S3Ey4PTgi8fSMVN9R5U9KNA5nWVORm8W8/5o3d9jKnysbieRElvJAtO 0GCA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=MD7YecZp3gunHf5drvkVKW7805f8VNuz6VEdbrGQghA=; b=V9VUdNFG2zhUY7XmL7ATPNVOJEXfFgqIli3ReCT/2WCxRTlzh09Tr4UpRKhWlAjnid 4dpkVSl7UhNKubbi1RD480VWfdgd5kysOCmOpM8QRhUVxEunc1m5RlII8uHQ56L+Jat2 cN4PNz/VuyTm6oPUi2LGCHjYaWL9Cny+BfKEuYFyNPFcQJZ93Rad7aSgWAb5w3DFvInz Nl0RcKj172qjOBWF2q/tlVsi/KPBB97KZvqJhHpDKtxPHslN8wquY54I42q3uZsqM169 Hpn1LJS0mtUxN/rPOfKlHfoOFcJ7WiGeUDXWz7c8gLmmJ9gnCMZFrpVomwS8682+HlgT wEAQ== X-Gm-Message-State: APjAAAV6/BkA1HoXy8RsvSi9ll63xrfcoRt8L4ThGP+/bNsDCF+nBVyD pPbnSiwMT7lJW5vheo/EwYFp6glsQ8S3WJ+x4HE= X-Google-Smtp-Source: APXvYqyAZFHeBclOR6NqX04d+iRlGkog2oYZa+dQvBupHcQJuZR4kCb00d8twHcJN+xFPmse6ExSfadm47FjwxXwCN8= X-Received: by 2002:a02:662a:: with SMTP id k42mr27760296jac.73.1576005439308; Tue, 10 Dec 2019 11:17:19 -0800 (PST) MIME-Version: 1.0 References: <20191202210947.3603-1-nieklinnenbank@gmail.com> <20191202210947.3603-2-nieklinnenbank@gmail.com> <70e9d4e8-49fb-02f9-23b4-d7cbf6e55eac@redhat.com> In-Reply-To: <70e9d4e8-49fb-02f9-23b4-d7cbf6e55eac@redhat.com> From: Niek Linnenbank Date: Tue, 10 Dec 2019 20:17:08 +0100 Message-ID: Subject: Re: [PATCH 01/10] hw: arm: add Allwinner H3 System-on-Chip To: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= Cc: QEMU Developers , Beniamino Galvani , Peter Maydell , qemu-arm Content-Type: multipart/alternative; boundary="0000000000005fc6b305995e5c00" X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::d43 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 10 Dec 2019 19:17:29 -0000 --0000000000005fc6b305995e5c00 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Hi Philippe, On Tue, Dec 10, 2019 at 10:02 AM Philippe Mathieu-Daud=C3=A9 wrote: > On 12/2/19 10:09 PM, Niek Linnenbank wrote: > > The Allwinner H3 is a System on Chip containing four ARM Cortex A7 > > processor cores. Features and specifications include DDR2/DDR3 memory, > > SD/MMC storage cards, 10/100/1000Mbit ethernet, USB 2.0, HDMI and > > various I/O modules. This commit adds support for the Allwinner H3 > > System on Chip. > > > > Signed-off-by: Niek Linnenbank > > --- > [...] > > + > > + /* UART */ > > + if (serial_hd(0)) { > > As the uart0 is always mapped in the SoC, don't use 'if serial_hd()', > instead map it regardless a console is connected. > Indeed, the UARTs should always be mapped for this SoC. Noted, I'll solve this too for in the v2 patch update. Regards, Niek > > > + serial_mm_init(get_system_memory(), AW_H3_UART0_REG_BASE, 2, > > + s->irq[AW_H3_GIC_SPI_UART0], 115200, > serial_hd(0), > > + DEVICE_NATIVE_ENDIAN); > > + } > > + > > + /* Unimplemented devices */ > > + create_unimplemented_device("display-engine", AW_H3_DE_BASE, > AW_H3_DE_SIZE); > > + create_unimplemented_device("dma", AW_H3_DMA_BASE, AW_H3_DMA_SIZE)= ; > > + create_unimplemented_device("lcd0", AW_H3_LCD0_BASE, > AW_H3_LCD0_SIZE); > > + create_unimplemented_device("lcd1", AW_H3_LCD1_BASE, > AW_H3_LCD1_SIZE); > > + create_unimplemented_device("gpu", AW_H3_GPU_BASE, AW_H3_GPU_SIZE)= ; > > + create_unimplemented_device("hdmi", AW_H3_HDMI_BASE, > AW_H3_HDMI_SIZE); > > + create_unimplemented_device("rtc", AW_H3_RTC_BASE, AW_H3_RTC_SIZE)= ; > > + create_unimplemented_device("audio-codec", AW_H3_AC_BASE, > AW_H3_AC_SIZE); > > --=20 Niek Linnenbank --0000000000005fc6b305995e5c00 Content-Type: text/html; charset="UTF-8" Content-Transfer-Encoding: quoted-printable
Hi Philippe,

=
On Tue, Dec 10, 2019 at 10:02 AM Phil= ippe Mathieu-Daud=C3=A9 <philmd@red= hat.com> wrote:
On 12/2/19 10:09 PM, Niek Linnenbank wrote:
> The Allwinner H3 is a System on Chip containing four ARM Cortex A7
> processor cores. Features and specifications include DDR2/DDR3 memory,=
> SD/MMC storage cards, 10/100/1000Mbit ethernet, USB 2.0, HDMI and
> various I/O modules. This commit adds support for the Allwinner H3
> System on Chip.
>
> Signed-off-by: Niek Linnenbank <nieklinnenbank@gmail.com>
> ---
[...]
> +
> +=C2=A0 =C2=A0 /* UART */
> +=C2=A0 =C2=A0 if (serial_hd(0)) {

As the uart0 is always mapped in the SoC, don't use 'if serial_hd()= ',
instead map it regardless a console is connected.

=
Indeed, the UARTs should always be mapped for this SoC.
Noted, I'll solve this too for in the v2 patch update.

=
Regards,
Niek
=C2=A0

> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 serial_mm_init(get_system_memory(), AW_H3= _UART0_REG_BASE, 2,
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0s->irq[AW_H3_GIC_SPI_UART0], 115200, serial_hd(0),
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0DEVICE_NATIVE_ENDIAN);
> +=C2=A0 =C2=A0 }
> +
> +=C2=A0 =C2=A0 /* Unimplemented devices */
> +=C2=A0 =C2=A0 create_unimplemented_device("display-engine",= AW_H3_DE_BASE, AW_H3_DE_SIZE);
> +=C2=A0 =C2=A0 create_unimplemented_device("dma", AW_H3_DMA_= BASE, AW_H3_DMA_SIZE);
> +=C2=A0 =C2=A0 create_unimplemented_device("lcd0", AW_H3_LCD= 0_BASE, AW_H3_LCD0_SIZE);
> +=C2=A0 =C2=A0 create_unimplemented_device("lcd1", AW_H3_LCD= 1_BASE, AW_H3_LCD1_SIZE);
> +=C2=A0 =C2=A0 create_unimplemented_device("gpu", AW_H3_GPU_= BASE, AW_H3_GPU_SIZE);
> +=C2=A0 =C2=A0 create_unimplemented_device("hdmi", AW_H3_HDM= I_BASE, AW_H3_HDMI_SIZE);
> +=C2=A0 =C2=A0 create_unimplemented_device("rtc", AW_H3_RTC_= BASE, AW_H3_RTC_SIZE);
> +=C2=A0 =C2=A0 create_unimplemented_device("audio-codec", AW= _H3_AC_BASE, AW_H3_AC_SIZE);



--
Niek Linnenbank

--0000000000005fc6b305995e5c00-- From MAILER-DAEMON Tue Dec 10 14:18:23 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1iel1b-0006qN-P4 for mharc-qemu-arm@gnu.org; Tue, 10 Dec 2019 14:18:23 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:52745) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iel1Y-0006on-Ma for qemu-arm@nongnu.org; Tue, 10 Dec 2019 14:18:21 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1iel1X-0001KF-Lj for qemu-arm@nongnu.org; Tue, 10 Dec 2019 14:18:20 -0500 Received: from us-smtp-delivery-1.mimecast.com ([205.139.110.120]:44667 helo=us-smtp-1.mimecast.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1iel1X-0001Jw-IU for qemu-arm@nongnu.org; Tue, 10 Dec 2019 14:18:19 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1576005499; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=c3++B6jGigoLFuo/3hQZOpMhqfas1y5qS8ZZuYwehX0=; b=aMMXiQv2M5zit0TLB6GOuOQgrxzGIJ/InfCvvcDt8Z21VuM8rYbU9rUX1AOau1/9FrXHFa uWcZJ4Hlk0Z1K3iYHUpLBVFEHqUKx1F6x/z7pX6q4D1+yVB9CKqAAl+6VP40PvU22qf/tE ad7uKvQVZ2IYf0vO5/Y+TA7zhVOEb1o= Received: from mail-qt1-f200.google.com (mail-qt1-f200.google.com [209.85.160.200]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-208-76wcU4EQMTuUUwec4qMP5w-1; Tue, 10 Dec 2019 14:18:17 -0500 Received: by mail-qt1-f200.google.com with SMTP id h14so2640281qtq.11 for ; Tue, 10 Dec 2019 11:18:17 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:in-reply-to:user-agent; bh=71U6KlP9jDk1ZWVrATst8QhUNwH9m6eIUrRigEc9LaE=; b=sCeAwQQnLGpVqirtTE23t+GoEKda+6Ntmb3x9hzbaismw1wpSmP5hhHw4X3vn4gyU7 N7Ut1tIDpvIyjNhTW2YKcRvoi8RJ+AOEYRtrfZ2v8GwfZa1CiCpW23U9f3gdFSxc7A5i hVrMJr/SVg1tZmsNijmere4kpIIdNhKVnlR+0gaxBrnkmLYJWB3PJd9g7qv6x7RYGAdt Q1lKjkm3oL0RCpLqKluqCuyQ+M2kCo888bBi6/a36O8x+ZKoE9pttXPAUvr63pic6Bt/ Pc0qLvy2e2C+yRtbel/72NICRYOQ9XYWEzxW6DL8SXeK1K04EdoJY7aOgJ5skVZ3Qjh/ Bieg== X-Gm-Message-State: APjAAAWHsg0VGb55UpSVjabTVRq3x+VfW1eHGo2rcWvEG/c+KBo7IKmw L08MWSwagC7rCMQdhkoHProJYRyqE7vDJ+6wPhFgYuE4WtynmPUdPdd6K/ylO5n5KiMHYyZYwdi RSW8zjlf/9qjv X-Received: by 2002:aed:3ac6:: with SMTP id o64mr32220049qte.219.1576005497138; Tue, 10 Dec 2019 11:18:17 -0800 (PST) X-Google-Smtp-Source: APXvYqzjGUdBcIM4JgpryqhUhkVAonqfsXZjPyRrrQIqrpRP0Gvo8pW6ggjTVBWB0P1+jWL3uKrGGQ== X-Received: by 2002:aed:3ac6:: with SMTP id o64mr32220030qte.219.1576005496972; Tue, 10 Dec 2019 11:18:16 -0800 (PST) Received: from xz-x1 ([104.156.64.74]) by smtp.gmail.com with ESMTPSA id q30sm1387181qtd.5.2019.12.10.11.18.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 10 Dec 2019 11:18:16 -0800 (PST) Date: Tue, 10 Dec 2019 14:18:14 -0500 From: Peter Xu To: Eric Auger Cc: eric.auger.pro@gmail.com, qemu-devel@nongnu.org, qemu-arm@nongnu.org, peter.maydell@linaro.org, mst@redhat.com, armbru@redhat.com, jean-philippe.brucker@arm.com, bharatb.linux@gmail.com, yang.zhong@intel.com, dgilbert@redhat.com, quintela@redhat.com, kevin.tian@intel.com, tnowicki@marvell.com Subject: Re: [PATCH for-5.0 v11 04/20] virtio-iommu: Add the iommu regions Message-ID: <20191210191814.GI3352@xz-x1> References: <20191122182943.4656-1-eric.auger@redhat.com> <20191122182943.4656-5-eric.auger@redhat.com> MIME-Version: 1.0 In-Reply-To: <20191122182943.4656-5-eric.auger@redhat.com> User-Agent: Mutt/1.12.1 (2019-06-15) X-MC-Unique: 76wcU4EQMTuUUwec4qMP5w-1 X-Mimecast-Spam-Score: 0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable Content-Disposition: inline X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 205.139.110.120 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 10 Dec 2019 19:18:21 -0000 On Fri, Nov 22, 2019 at 07:29:27PM +0100, Eric Auger wrote: > This patch initializes the iommu memory regions so that > PCIe end point transactions get translated. The translation > function is not yet implemented though. >=20 > Signed-off-by: Eric Auger Either with/without Jean's comment addressed: Reviewed-by: Peter Xu --=20 Peter Xu From MAILER-DAEMON Tue Dec 10 14:33:58 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1ielGg-0005Bq-4U for mharc-qemu-arm@gnu.org; Tue, 10 Dec 2019 14:33:58 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:58140) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ielGa-0005BD-64 for qemu-arm@nongnu.org; Tue, 10 Dec 2019 14:33:53 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ielGX-00083o-6w for qemu-arm@nongnu.org; Tue, 10 Dec 2019 14:33:50 -0500 Received: from us-smtp-delivery-1.mimecast.com ([207.211.31.120]:49798 helo=us-smtp-1.mimecast.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1ielGX-00082u-3L for qemu-arm@nongnu.org; Tue, 10 Dec 2019 14:33:49 -0500 DKIM-Signature: v=1; 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Tue, 10 Dec 2019 11:33:43 -0800 (PST) Date: Tue, 10 Dec 2019 14:33:42 -0500 From: Peter Xu To: Eric Auger Cc: eric.auger.pro@gmail.com, qemu-devel@nongnu.org, qemu-arm@nongnu.org, peter.maydell@linaro.org, mst@redhat.com, armbru@redhat.com, jean-philippe.brucker@arm.com, bharatb.linux@gmail.com, yang.zhong@intel.com, dgilbert@redhat.com, quintela@redhat.com, kevin.tian@intel.com, tnowicki@marvell.com Subject: Re: [PATCH for-5.0 v11 08/20] virtio-iommu: Implement translate Message-ID: <20191210193342.GJ3352@xz-x1> References: <20191122182943.4656-1-eric.auger@redhat.com> <20191122182943.4656-9-eric.auger@redhat.com> MIME-Version: 1.0 In-Reply-To: <20191122182943.4656-9-eric.auger@redhat.com> User-Agent: Mutt/1.12.1 (2019-06-15) X-MC-Unique: nc2qJw33M5CzqY3rLzczqw-1 X-Mimecast-Spam-Score: 0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable Content-Disposition: inline X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 207.211.31.120 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 10 Dec 2019 19:33:53 -0000 On Fri, Nov 22, 2019 at 07:29:31PM +0100, Eric Auger wrote: > This patch implements the translate callback >=20 > Signed-off-by: Eric Auger >=20 > --- >=20 > v10 -> v11: > - take into account the new value struct and use > g_tree_lookup_extended > - switched to error_report_once >=20 > v6 -> v7: > - implemented bypass-mode >=20 > v5 -> v6: > - replace error_report by qemu_log_mask >=20 > v4 -> v5: > - check the device domain is not NULL > - s/printf/error_report > - set flags to IOMMU_NONE in case of all translation faults > --- > hw/virtio/trace-events | 1 + > hw/virtio/virtio-iommu.c | 63 +++++++++++++++++++++++++++++++++++++++- > 2 files changed, 63 insertions(+), 1 deletion(-) >=20 > diff --git a/hw/virtio/trace-events b/hw/virtio/trace-events > index f25359cee2..de7cbb3c8f 100644 > --- a/hw/virtio/trace-events > +++ b/hw/virtio/trace-events > @@ -72,3 +72,4 @@ virtio_iommu_get_endpoint(uint32_t ep_id) "Alloc endpoi= nt=3D%d" > virtio_iommu_put_endpoint(uint32_t ep_id) "Free endpoint=3D%d" > virtio_iommu_get_domain(uint32_t domain_id) "Alloc domain=3D%d" > virtio_iommu_put_domain(uint32_t domain_id) "Free domain=3D%d" > +virtio_iommu_translate_out(uint64_t virt_addr, uint64_t phys_addr, uint3= 2_t sid) "0x%"PRIx64" -> 0x%"PRIx64 " for sid=3D%d" > diff --git a/hw/virtio/virtio-iommu.c b/hw/virtio/virtio-iommu.c > index f0a56833a2..a83666557b 100644 > --- a/hw/virtio/virtio-iommu.c > +++ b/hw/virtio/virtio-iommu.c > @@ -412,19 +412,80 @@ static IOMMUTLBEntry virtio_iommu_translate(IOMMUMe= moryRegion *mr, hwaddr addr, > int iommu_idx) > { > IOMMUDevice *sdev =3D container_of(mr, IOMMUDevice, iommu_mr); > + viommu_interval interval, *mapping_key; > + viommu_mapping *mapping_value; > + VirtIOIOMMU *s =3D sdev->viommu; > + viommu_endpoint *ep; > + bool bypass_allowed; > uint32_t sid; > + bool found; > + > + interval.low =3D addr; > + interval.high =3D addr + 1; > =20 > IOMMUTLBEntry entry =3D { > .target_as =3D &address_space_memory, > .iova =3D addr, > .translated_addr =3D addr, > - .addr_mask =3D ~(hwaddr)0, > + .addr_mask =3D (1 << ctz32(s->config.page_size_mask)) - 1, > .perm =3D IOMMU_NONE, > }; > =20 > + bypass_allowed =3D virtio_has_feature(s->acked_features, > + VIRTIO_IOMMU_F_BYPASS); > + Would it be easier to check bypass_allowed here once and then drop the latter [1] and [2] check? > sid =3D virtio_iommu_get_sid(sdev); > =20 > trace_virtio_iommu_translate(mr->parent_obj.name, sid, addr, flag); > + qemu_mutex_lock(&s->mutex); > + > + ep =3D g_tree_lookup(s->endpoints, GUINT_TO_POINTER(sid)); > + if (!ep) { > + if (!bypass_allowed) { [1] > + error_report_once("%s sid=3D%d is not known!!", __func__, si= d); > + } else { > + entry.perm =3D flag; > + } > + goto unlock; > + } > + > + if (!ep->domain) { > + if (!bypass_allowed) { [2] > + qemu_log_mask(LOG_GUEST_ERROR, > + "%s %02x:%02x.%01x not attached to any domain\= n", > + __func__, PCI_BUS_NUM(sid), > + PCI_SLOT(sid), PCI_FUNC(sid)); > + } else { > + entry.perm =3D flag; > + } > + goto unlock; > + } > + > + found =3D g_tree_lookup_extended(ep->domain->mappings, (gpointer)(&i= nterval), > + (void **)&mapping_key, > + (void **)&mapping_value); > + if (!found) { > + qemu_log_mask(LOG_GUEST_ERROR, > + "%s no mapping for 0x%"PRIx64" for sid=3D%d\n", > + __func__, addr, sid); I would still suggest that we use the same logging interface (either error_report_once() or qemu_log_mask(), not use them randomly). > + goto unlock; > + } > + > + if (((flag & IOMMU_RO) && > + !(mapping_value->flags & VIRTIO_IOMMU_MAP_F_READ)) || > + ((flag & IOMMU_WO) && > + !(mapping_value->flags & VIRTIO_IOMMU_MAP_F_WRITE))) { > + qemu_log_mask(LOG_GUEST_ERROR, > + "Permission error on 0x%"PRIx64"(%d): allowed=3D%d= \n", > + addr, flag, mapping_value->flags); (Btw, IIUC this may not be a guest error. Say, what if the device is simply broken?) > + goto unlock; > + } > + entry.translated_addr =3D addr - mapping_key->low + mapping_value->p= hys_addr; > + entry.perm =3D flag; > + trace_virtio_iommu_translate_out(addr, entry.translated_addr, sid); > + > +unlock: > + qemu_mutex_unlock(&s->mutex); > return entry; > } > =20 > --=20 > 2.20.1 >=20 --=20 Peter Xu From MAILER-DAEMON Tue Dec 10 14:36:22 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1ielJ0-0006QY-12 for mharc-qemu-arm@gnu.org; Tue, 10 Dec 2019 14:36:22 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:58825) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ielIx-0006Po-Av for qemu-arm@nongnu.org; Tue, 10 Dec 2019 14:36:20 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ielIw-0000x5-Dh for qemu-arm@nongnu.org; Tue, 10 Dec 2019 14:36:19 -0500 Received: from us-smtp-delivery-1.mimecast.com ([207.211.31.120]:58158 helo=us-smtp-1.mimecast.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1ielIw-0000wz-AQ for qemu-arm@nongnu.org; Tue, 10 Dec 2019 14:36:18 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1576006577; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=eb7AmweRNmrhfF8rgwPCRN+jvonKHTPSJaOP2AIRHTU=; b=V3uKNUDBF6UVyoziG+AfWFUQ5kyXhBU6p+U/BE58mvvhf14CskLqaUfRAImfLMoQfogpE6 h7Xx7lYEjeyE6RsfTDOkWCX8GMXrDJCfBguQuHK1IdAGR/EWhKmTKrTEdikA1blEP95K1d uvFTOVKGvZTutw4SwZAgD2WKfB+ssb4= Received: from mail-qk1-f200.google.com (mail-qk1-f200.google.com [209.85.222.200]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-281-P_4dVrFmMXWveGpR0-QHiw-1; Tue, 10 Dec 2019 14:36:16 -0500 Received: by mail-qk1-f200.google.com with SMTP id m13so12964420qka.9 for ; Tue, 10 Dec 2019 11:36:16 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:in-reply-to:user-agent; bh=VoST2cwgUReKtnPRy2fmQ6MgjrANU6LbhWvd8CWPERw=; b=h8oqqGD3IEa9qmIoI/ubEpjpoXHJBwkv5EhppjgwFlzZvUf99IZLZb/QqRjXEa1ei6 Q6X3DdKziAskME5RfDfg7BbZq1+cu5awyBoE89jZHqjuoalSNBGVjroNQkmvCmAPWVft DBTZ2bEQjSl/DsRxKPX2jikbKpYs64V+tAuSDxSK+rzcBauUDdrbwCJgPmU/z2T3wqSY Jii7tp3HyxBHZ+QvROmYKNDFsEV6TXPFv5//CnU9RMDzmYGDvQqY9ih/VAJUUmM/zO2l 4gVGobZrmMYZ67Xk1UFwiR/4Ix5wVCBQHYuXaBzXyTcsQd9g4wNHFlXL4UPiyAmTy5uA JWYg== X-Gm-Message-State: APjAAAWp4Z94ZARfhSd1IO5ODUu7evevfgY4OlDU41T0/ujILg3ploCj wvXpmXdw3Lugw3M4s3D/72veV8+bZeCfKHjVUk1iUXEXnDh00rBy2auieZM7/9p1G1NUT0uHB+r MaehaRERNjctE X-Received: by 2002:a37:a1c1:: with SMTP id k184mr17377454qke.66.1576006576115; Tue, 10 Dec 2019 11:36:16 -0800 (PST) X-Google-Smtp-Source: APXvYqy6Pmiy5TUMNv2yF1r9Mvi1s/hqqOLCZTm4OKvM+baGtNRR/oQKW9ZvzOM7z30W7+Kjf9p5tA== X-Received: by 2002:a37:a1c1:: with SMTP id k184mr17377436qke.66.1576006575903; Tue, 10 Dec 2019 11:36:15 -0800 (PST) Received: from xz-x1 ([104.156.64.74]) by smtp.gmail.com with ESMTPSA id d32sm1456168qtd.31.2019.12.10.11.36.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 10 Dec 2019 11:36:15 -0800 (PST) Date: Tue, 10 Dec 2019 14:36:13 -0500 From: Peter Xu To: Eric Auger Cc: eric.auger.pro@gmail.com, qemu-devel@nongnu.org, qemu-arm@nongnu.org, peter.maydell@linaro.org, mst@redhat.com, armbru@redhat.com, jean-philippe.brucker@arm.com, bharatb.linux@gmail.com, yang.zhong@intel.com, dgilbert@redhat.com, quintela@redhat.com, kevin.tian@intel.com, tnowicki@marvell.com Subject: Re: [PATCH for-5.0 v11 13/20] virtio-iommu: Implement probe request Message-ID: <20191210193613.GK3352@xz-x1> References: <20191122182943.4656-1-eric.auger@redhat.com> <20191122182943.4656-14-eric.auger@redhat.com> MIME-Version: 1.0 In-Reply-To: <20191122182943.4656-14-eric.auger@redhat.com> User-Agent: Mutt/1.12.1 (2019-06-15) X-MC-Unique: P_4dVrFmMXWveGpR0-QHiw-1 X-Mimecast-Spam-Score: 0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable Content-Disposition: inline X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 207.211.31.120 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 10 Dec 2019 19:36:20 -0000 On Fri, Nov 22, 2019 at 07:29:36PM +0100, Eric Auger wrote: > This patch implements the PROBE request. At the moment, > no reserved regions are returned as none are registered > per device. Only a NONE property is returned. >=20 > Signed-off-by: Eric Auger Reviewed-by: Peter Xu --=20 Peter Xu From MAILER-DAEMON Tue Dec 10 14:39:12 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1ielLk-0007tI-81 for mharc-qemu-arm@gnu.org; Tue, 10 Dec 2019 14:39:12 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:59768) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ielLh-0007sa-7P for qemu-arm@nongnu.org; Tue, 10 Dec 2019 14:39:10 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ielLg-0001hu-3s for qemu-arm@nongnu.org; Tue, 10 Dec 2019 14:39:09 -0500 Received: from us-smtp-delivery-1.mimecast.com ([205.139.110.120]:21697 helo=us-smtp-1.mimecast.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1ielLf-0001hf-Vh for qemu-arm@nongnu.org; Tue, 10 Dec 2019 14:39:08 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1576006747; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=FgAyacV+nZ8CBkg+wqkyy4NV8IkZ01Jpe3cd7x9PNsc=; b=A62Io/+s42Ok+rXV4l7NNHYNtY1/FXOmD5L/wHDKjN6fd/n2FKXMRVmlbYAopW2WzQhHXn ytBVhoLCmI2N2zxQC/AItHleWCh0KSjmKqSUC7xS3FHDKliFIL208zBmgWqKAENDqwS4DL o6LEoTneNTxc4t6T/g1P9SUy/fRReKQ= Received: from mail-qt1-f198.google.com (mail-qt1-f198.google.com [209.85.160.198]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-90-MRagr9PlMuqZ7MXx_R-2sw-1; Tue, 10 Dec 2019 14:39:05 -0500 Received: by mail-qt1-f198.google.com with SMTP id 42so2658521qtc.19 for ; Tue, 10 Dec 2019 11:39:05 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:in-reply-to:user-agent; bh=1mymb3Sv3zpDU5FJ6RFLPGZz5uXl0s3penVzv5qXOaM=; b=IcUILK/jdpjRRjKJ/o8fPqCU7iVaONDK8y+t8lCfIsmEVXbzZhLWTj91vx9UP+COPH Hkr3Y0WF9ZQwFMns94cn0Rhn6IN8M86a9WKia4fqHgHykH4909w5lF6FTCqh0Zflm4J3 kA62q338rNd0aQw0irtVnhRH3Bqer0Q+Lqi9q9WnUG9iDxhfdW7siqrCoqa/421VvQiz 15pizpEfWJm0WDZ/22Kq6kCynNWCwIgOZicRtch2EcSnZ8kHaRr86FJzCA8AG88pht+A JSqwI15/3dkc4pvUz2Dd+IupyVzJSo52RzQxRTVr5MgNuxpJLhTbqk+y9GJy8p+pQ8Tn fqcQ== X-Gm-Message-State: APjAAAVb93svo79NmSKRpEDm0Re6uAe6wwr9CKmGhTjkb9l85X2pjvTL +qcZUrNBjzWEgO2+eC747w3Uy7J/+qgDxuekVotbS6yz3nPQfsyjy9GmiMsscX4Qb+lKm/oPLYl TdPfuAhRI5KAD X-Received: by 2002:ad4:498d:: with SMTP id t13mr29235093qvx.58.1576006745419; Tue, 10 Dec 2019 11:39:05 -0800 (PST) X-Google-Smtp-Source: APXvYqxvXllWwZgZQ8+UpFxHdOU5dKoBDqTeaIxph01U8VD7I0FDDqMbw38c6MtFbOLuNnmNbHthdw== X-Received: by 2002:ad4:498d:: with SMTP id t13mr29235067qvx.58.1576006745175; Tue, 10 Dec 2019 11:39:05 -0800 (PST) Received: from xz-x1 ([104.156.64.74]) by smtp.gmail.com with ESMTPSA id o10sm1346480qtp.38.2019.12.10.11.39.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 10 Dec 2019 11:39:04 -0800 (PST) Date: Tue, 10 Dec 2019 14:39:03 -0500 From: Peter Xu To: Eric Auger Cc: eric.auger.pro@gmail.com, qemu-devel@nongnu.org, qemu-arm@nongnu.org, peter.maydell@linaro.org, mst@redhat.com, armbru@redhat.com, jean-philippe.brucker@arm.com, bharatb.linux@gmail.com, yang.zhong@intel.com, dgilbert@redhat.com, quintela@redhat.com, kevin.tian@intel.com, tnowicki@marvell.com Subject: Re: [PATCH for-5.0 v11 14/20] virtio-iommu: Handle reserved regions in the translation process Message-ID: <20191210193903.GL3352@xz-x1> References: <20191122182943.4656-1-eric.auger@redhat.com> <20191122182943.4656-15-eric.auger@redhat.com> MIME-Version: 1.0 In-Reply-To: <20191122182943.4656-15-eric.auger@redhat.com> User-Agent: Mutt/1.12.1 (2019-06-15) X-MC-Unique: MRagr9PlMuqZ7MXx_R-2sw-1 X-Mimecast-Spam-Score: 0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable Content-Disposition: inline X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 205.139.110.120 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 10 Dec 2019 19:39:10 -0000 On Fri, Nov 22, 2019 at 07:29:37PM +0100, Eric Auger wrote: > When translating an address we need to check if it belongs to > a reserved virtual address range. If it does, there are 2 cases: >=20 > - it belongs to a RESERVED region: the guest should neither use > this address in a MAP not instruct the end-point to DMA on > them. We report an error >=20 > - It belongs to an MSI region: we bypass the translation. >=20 > Signed-off-by: Eric Auger >=20 > --- >=20 > v10 -> v11: > - directly use the reserved_regions properties array >=20 > v9 -> v10: > - in case of MSI region, we immediatly return > --- > hw/virtio/virtio-iommu.c | 17 +++++++++++++++++ > 1 file changed, 17 insertions(+) >=20 > diff --git a/hw/virtio/virtio-iommu.c b/hw/virtio/virtio-iommu.c > index 1ce2218935..c5b202fab7 100644 > --- a/hw/virtio/virtio-iommu.c > +++ b/hw/virtio/virtio-iommu.c > @@ -548,6 +548,7 @@ static IOMMUTLBEntry virtio_iommu_translate(IOMMUMemo= ryRegion *mr, hwaddr addr, > uint32_t sid, flags; > bool bypass_allowed; > bool found; > + int i; > =20 > interval.low =3D addr; > interval.high =3D addr + 1; > @@ -580,6 +581,22 @@ static IOMMUTLBEntry virtio_iommu_translate(IOMMUMem= oryRegion *mr, hwaddr addr, > goto unlock; > } > =20 > + for (i =3D 0; i < s->nb_reserved_regions; i++) { > + if (interval.low >=3D s->reserved_regions[i].low && > + interval.low <=3D s->reserved_regions[i].high) { > + switch (s->reserved_regions[i].type) { > + case VIRTIO_IOMMU_RESV_MEM_T_MSI: > + entry.perm =3D flag; > + goto unlock; Might be a bit clearer to break here instead of goto, then.. > + case VIRTIO_IOMMU_RESV_MEM_T_RESERVED: /* Passthrough */ > + default: > + virtio_iommu_report_fault(s, VIRTIO_IOMMU_FAULT_R_MAPPIN= G, > + 0, sid, addr); > + goto unlock; .. do the same thing here, and... > + } .. goto unlock here.. > + } > + } > + > if (!ep->domain) { > if (!bypass_allowed) { > qemu_log_mask(LOG_GUEST_ERROR, > --=20 > 2.20.1 >=20 --=20 Peter Xu From MAILER-DAEMON Tue Dec 10 14:56:06 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1ielc6-0003a6-Ey for mharc-qemu-arm@gnu.org; Tue, 10 Dec 2019 14:56:06 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:37065) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ielc0-0003Y3-AP for qemu-arm@nongnu.org; Tue, 10 Dec 2019 14:56:03 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ielbx-0007Bm-8V for qemu-arm@nongnu.org; Tue, 10 Dec 2019 14:56:00 -0500 Received: from mail-il1-x142.google.com ([2607:f8b0:4864:20::142]:33410) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ielbs-00079L-2S; Tue, 10 Dec 2019 14:55:52 -0500 Received: by mail-il1-x142.google.com with SMTP id r81so17288070ilk.0; Tue, 10 Dec 2019 11:55:51 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=1dIZZM/9ov80ebOhF4v5HlOS5BwOWDRL3nqtdeKRMI4=; b=DiSWpiIooBSFWqTa8eHBGcond2A+qeITtzPcTmfiDp+Ux1wv6hN+sfDVVyCqyDLvAi nPlmRkwahNsh9D57sUHJ1miIgprEYMpUKNhcm5pJJh18TnJPzVPKEFCWn/PYoapkr+f+ U7e78xdwswsxmhtnBFQKLM4ye/JMwtPoXgNAD5nqRWxtH5oyIB6OpkHMW8GBifbbrQnE dnuMsZ+Dx2se09OVaEqli8PKc31ddZyMTIJ5Sphm/y3mWPFud7UgoSElCxixqfMbjgIp N9PCWOQuRX0vAw5PKubRCSj5Ab/KgDGiElcyOSLpGlNXO6jvX2IeQVNjehG7nLikfhiZ GKAA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=1dIZZM/9ov80ebOhF4v5HlOS5BwOWDRL3nqtdeKRMI4=; b=AaXfVdlhQfn+DCDr+lgKe7d3/v2OVGlN04cZmzd+vDxDozG6OGg4lQZVH7UNBgFfL5 fW5mjbIHBLNLh+Xwxex3VxkMxi1FPoULniVLKu5Sx5rout1eyWOuF9xG9tImIKWuX3EH aAbBW0nBEy8+A5hIWdpvUIP/+C87UEamcQY4JdBzjyOkLdcjiMuZqSR/tQ565sv1MR5W 6ri8sfX8H1ZiDXe1hF+GMn4mTT11nvkAPsZTYGu4RyteilPUTMdBopEtOrjAFC12W3bL hMibxrlSzd3aNcxHtAM/CzXC/OqZYZfSVYj0rbHo+FXFXk3gRlC+fpdRw+z/pw7wpZ4h Ma0Q== X-Gm-Message-State: APjAAAVVG/eHpUhoqZ3yQSVJtVtVDqNy5Oivyw6l77CuRtdUoPcOboAX jgum/SgZI3dAnhx11TzFSJwmUHyBFoA4D22CpTE= X-Google-Smtp-Source: APXvYqwkSAa+qCJICiNlJ3ueqeehm7sglbISd92hpmdB7F/CMx4P0nEmmZD9GCiCXQP6dlXK+TO2Id0Gydi2ZpVcUEc= X-Received: by 2002:a92:d084:: with SMTP id h4mr36000622ilh.265.1576007750959; Tue, 10 Dec 2019 11:55:50 -0800 (PST) MIME-Version: 1.0 References: <20191202210947.3603-1-nieklinnenbank@gmail.com> <6d774864-2bea-ecd6-0b14-a28d0756bfbc@adacore.com> In-Reply-To: <6d774864-2bea-ecd6-0b14-a28d0756bfbc@adacore.com> From: Niek Linnenbank Date: Tue, 10 Dec 2019 20:55:39 +0100 Message-ID: Subject: Re: [PATCH 00/10] Add Allwinner H3 SoC and Orange Pi PC Machine To: KONRAD Frederic Cc: QEMU Developers , Beniamino Galvani , Peter Maydell , qemu-arm Content-Type: multipart/alternative; boundary="00000000000028c75e05995ee654" X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::142 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 10 Dec 2019 19:56:03 -0000 --00000000000028c75e05995ee654 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Hi Frederic, On Tue, Dec 10, 2019 at 11:34 AM KONRAD Frederic < frederic.konrad@adacore.com> wrote: > > > Le 12/2/19 =C3=A0 10:09 PM, Niek Linnenbank a =C3=A9crit : > > Dear QEMU developers, > > > > Hereby I would like to contribute the following set of patches to QEMU > > which add support for the Allwinner H3 System on Chip and the > > Orange Pi PC machine. The following features and devices are supported: > > > > * SMP (Quad Core Cortex A7) > > * Generic Interrupt Controller configuration > > * SRAM mappings > > * Timer device (re-used from Allwinner A10) > > * UART > > * SD/MMC storage controller > > * EMAC ethernet connectivity > > * USB 2.0 interfaces > > * Clock Control Unit > > * System Control module > > * Security Identifier device > > > > Functionality related to graphical output such as HDMI, GPU, > > Display Engine and audio are not included. Recently released > > mainline Linux kernels (4.19 up to latest master) and mainline U-Boot > > are known to work. The SD/MMC code is tested using bonnie++ and > > various tools such as fsck, dd and fdisk. The EMAC is verified with > iperf3 > > using -netdev socket. > > > > To build a Linux mainline kernel that can be booted by the Orange Pi PC > > machine, simply configure the kernel using the sunxi_defconfig > configuration: > > $ ARCH=3Darm CROSS_COMPILE=3Darm-linux-gnueabi- make mrproper > > $ ARCH=3Darm CROSS_COMPILE=3Darm-linux-gnueabi- make sunxi_defconfig > > > > To be able to use USB storage, you need to manually enable the > corresponding > > configuration item. Start the kconfig configuration tool: > > $ ARCH=3Darm CROSS_COMPILE=3Darm-linux-gnueabi- make menuconfig > > > > Navigate to the following item, enable it and save your configuration: > > Device Drivers > USB support > USB Mass Storage support > > > > Build the Linux kernel with: > > $ ARCH=3Darm CROSS_COMPILE=3Darm-linux-gnueabi- make -j5 > > > > To boot the newly build linux kernel in QEMU with the Orange Pi PC > machine, use: > > $ qemu-system-arm -M orangepi -m 512 -nic user -nographic \ > > -kernel /path/to/linux/arch/arm/boot/zImage \ > > -append 'console=3DttyS0,115200' \ > > -dtb /path/to/linux/arch/arm/boot/dts/sun8i-h3-orangepi-pc.dtb > > > > Note that this kernel does not have a root filesystem. You may provide = it > > with an official Orange Pi PC image [1] either as an SD card or as > > USB mass storage. To boot using the Orange Pi PC Debian image on SD car= d, > > simply add the -sd argument and provide the proper root=3D kernel > parameter: > > $ qemu-system-arm -M orangepi -m 512 -nic user -nographic \ > > -kernel /path/to/linux/arch/arm/boot/zImage \ > > -append 'console=3DttyS0,115200 root=3D/dev/mmcblk0p2' \ > > -dtb /path/to/linux/arch/arm/boot/dts/sun8i-h3-orangepi-pc.dtb \ > > -sd OrangePi_pc_debian_stretch_server_linux5.3.5_v1.0.img > > > > Alternatively, you can also choose to build and boot a recent buildroot > [2] > > using the orangepi_pc_defconfig or Armbian image [3] for Orange Pi PC. > > To attach an USB mass storage device to the machine, simply append to > the command: > > -drive if=3Dnone,id=3Dstick,file=3Dmyimage.img \ > > -device usb-storage,bus=3Dusb-bus.0,drive=3Dstick > > > > U-Boot mainline can be build and configured using the > orangepi_pc_defconfig > > using similar commands as describe above for Linux. To start U-Boot usi= ng > > the Orange Pi PC machine, provide the u-boot binary to the -kernel > argument: > > $ qemu-system-arm -M orangepi -m 512 -nic user -nographic \ > > -kernel /path/to/uboot/u-boot -sd disk.img > > > > Use the following U-boot commands to load and boot a Linux kernel from > SD card: > > -> setenv bootargs console=3DttyS0,115200 > > -> ext2load mmc 0 0x42000000 zImage > > -> ext2load mmc 0 0x43000000 sun8i-h2-plus-orangepi-zero.dtb > > -> bootz 0x42000000 - 0x43000000 > > > > Looking forward to your review comments. I will do my best > > to update the patches where needed. > > > > With kind regards, > > > > Niek Linnenbank > > > > [1] http://www.orangepi.org/downloadresources/ > > [2] https://buildroot.org/download.html > > [3] https://www.armbian.com/orange-pi-pc/ > > Works well on my side with vanilla linux-4.9.13 built with gcc-8.3.0 + > busybox > and sun8i-h3-orangepi-one.dtb. > > Tested-by: KONRAD Frederic > > Thank you for testing! Great, I'll add the tag for the next v2 of the patches. Regards, Niek > > > > Niek Linnenbank (10): > > hw: arm: add Allwinner H3 System-on-Chip > > hw: arm: add Xunlong Orange Pi PC machine > > arm: allwinner-h3: add Clock Control Unit > > arm: allwinner-h3: add USB host controller > > arm: allwinner-h3: add System Control module > > arm/arm-powerctl: set NSACR.{CP11,CP10} bits in arm_set_cpu_on() > > arm: allwinner-h3: add CPU Configuration module > > arm: allwinner-h3: add Security Identifier device > > arm: allwinner-h3: add SD/MMC host controller > > arm: allwinner-h3: add EMAC ethernet device > > > > MAINTAINERS | 8 + > > default-configs/arm-softmmu.mak | 1 + > > hw/arm/Kconfig | 9 + > > hw/arm/Makefile.objs | 1 + > > hw/arm/allwinner-h3.c | 316 ++++++++++ > > hw/arm/orangepi.c | 114 ++++ > > hw/misc/Makefile.objs | 4 + > > hw/misc/allwinner-h3-clk.c | 227 ++++++++ > > hw/misc/allwinner-h3-cpucfg.c | 280 +++++++++ > > hw/misc/allwinner-h3-sid.c | 162 ++++++ > > hw/misc/allwinner-h3-syscon.c | 139 +++++ > > hw/misc/trace-events | 5 + > > hw/net/Kconfig | 3 + > > hw/net/Makefile.objs | 1 + > > hw/net/allwinner-h3-emac.c | 786 +++++++++++++++++++++++++ > > hw/net/trace-events | 10 + > > hw/sd/Makefile.objs | 1 + > > hw/sd/allwinner-h3-sdhost.c | 791 +++++++++++++++++++++++++= + > > hw/sd/trace-events | 7 + > > hw/usb/hcd-ehci-sysbus.c | 17 + > > hw/usb/hcd-ehci.h | 1 + > > include/hw/arm/allwinner-h3.h | 130 +++++ > > include/hw/misc/allwinner-h3-clk.h | 41 ++ > > include/hw/misc/allwinner-h3-cpucfg.h | 44 ++ > > include/hw/misc/allwinner-h3-sid.h | 42 ++ > > include/hw/misc/allwinner-h3-syscon.h | 43 ++ > > include/hw/net/allwinner-h3-emac.h | 69 +++ > > include/hw/sd/allwinner-h3-sdhost.h | 73 +++ > > target/arm/arm-powerctl.c | 3 + > > 29 files changed, 3328 insertions(+) > > create mode 100644 hw/arm/allwinner-h3.c > > create mode 100644 hw/arm/orangepi.c > > create mode 100644 hw/misc/allwinner-h3-clk.c > > create mode 100644 hw/misc/allwinner-h3-cpucfg.c > > create mode 100644 hw/misc/allwinner-h3-sid.c > > create mode 100644 hw/misc/allwinner-h3-syscon.c > > create mode 100644 hw/net/allwinner-h3-emac.c > > create mode 100644 hw/sd/allwinner-h3-sdhost.c > > create mode 100644 include/hw/arm/allwinner-h3.h > > create mode 100644 include/hw/misc/allwinner-h3-clk.h > > create mode 100644 include/hw/misc/allwinner-h3-cpucfg.h > > create mode 100644 include/hw/misc/allwinner-h3-sid.h > > create mode 100644 include/hw/misc/allwinner-h3-syscon.h > > create mode 100644 include/hw/net/allwinner-h3-emac.h > > create mode 100644 include/hw/sd/allwinner-h3-sdhost.h > > > --=20 Niek Linnenbank --00000000000028c75e05995ee654 Content-Type: text/html; charset="UTF-8" Content-Transfer-Encoding: quoted-printable
Hi Frederic,

=
On Tue, Dec 10, 2019 at 11:34 AM KONR= AD Frederic <frederic.kon= rad@adacore.com> wrote:


Le 12/2/19 =C3=A0 10:09 PM, Niek Linnenbank a =C3=A9crit=C2=A0:
> Dear QEMU developers,
>
> Hereby I would like to contribute the following set of patches to QEMU=
> which add support for the Allwinner H3 System on Chip and the
> Orange Pi PC machine. The following features and devices are supported= :
>
>=C2=A0 =C2=A0* SMP (Quad Core Cortex A7)
>=C2=A0 =C2=A0* Generic Interrupt Controller configuration
>=C2=A0 =C2=A0* SRAM mappings
>=C2=A0 =C2=A0* Timer device (re-used from Allwinner A10)
>=C2=A0 =C2=A0* UART
>=C2=A0 =C2=A0* SD/MMC storage controller
>=C2=A0 =C2=A0* EMAC ethernet connectivity
>=C2=A0 =C2=A0* USB 2.0 interfaces
>=C2=A0 =C2=A0* Clock Control Unit
>=C2=A0 =C2=A0* System Control module
>=C2=A0 =C2=A0* Security Identifier device
>
> Functionality related to graphical output such as HDMI, GPU,
> Display Engine and audio are not included. Recently released
> mainline Linux kernels (4.19 up to latest master) and mainline U-Boot<= br> > are known to work. The SD/MMC code is tested using bonnie++ and
> various tools such as fsck, dd and fdisk. The EMAC is verified with ip= erf3
> using -netdev socket.
>
> To build a Linux mainline kernel that can be booted by the Orange Pi P= C
> machine, simply configure the kernel using the sunxi_defconfig configu= ration:
>=C2=A0 =C2=A0$ ARCH=3Darm CROSS_COMPILE=3Darm-linux-gnueabi- make mrpro= per
>=C2=A0 =C2=A0$ ARCH=3Darm CROSS_COMPILE=3Darm-linux-gnueabi- make sunxi= _defconfig
>
> To be able to use USB storage, you need to manually enable the corresp= onding
> configuration item. Start the kconfig configuration tool:
>=C2=A0 =C2=A0$ ARCH=3Darm CROSS_COMPILE=3Darm-linux-gnueabi- make menuc= onfig
>
> Navigate to the following item, enable it and save your configuration:=
>=C2=A0 =C2=A0Device Drivers > USB support > USB Mass Storage supp= ort
>
> Build the Linux kernel with:
>=C2=A0 =C2=A0$ ARCH=3Darm CROSS_COMPILE=3Darm-linux-gnueabi- make -j5 >
> To boot the newly build linux kernel in QEMU with the Orange Pi PC mac= hine, use:
>=C2=A0 =C2=A0$ qemu-system-arm -M orangepi -m 512 -nic user -nographic = \
>=C2=A0 =C2=A0 =C2=A0 =C2=A0-kernel /path/to/linux/arch/arm/boot/zImage = \
>=C2=A0 =C2=A0 =C2=A0 =C2=A0-append 'console=3DttyS0,115200' \ >=C2=A0 =C2=A0 =C2=A0 =C2=A0-dtb /path/to/linux/arch/arm/boot/dts/sun8i-= h3-orangepi-pc.dtb
>
> Note that this kernel does not have a root filesystem. You may provide= it
> with an official Orange Pi PC image [1] either as an SD card or as
> USB mass storage. To boot using the Orange Pi PC Debian image on SD ca= rd,
> simply add the -sd argument and provide the proper root=3D kernel para= meter:
>=C2=A0 =C2=A0$ qemu-system-arm -M orangepi -m 512 -nic user -nographic = \
>=C2=A0 =C2=A0 =C2=A0 =C2=A0-kernel /path/to/linux/arch/arm/boot/zImage = \
>=C2=A0 =C2=A0 =C2=A0 =C2=A0-append 'console=3DttyS0,115200 root=3D/= dev/mmcblk0p2' \
>=C2=A0 =C2=A0 =C2=A0 =C2=A0-dtb /path/to/linux/arch/arm/boot/dts/sun8i-= h3-orangepi-pc.dtb \
>=C2=A0 =C2=A0 =C2=A0 =C2=A0-sd OrangePi_pc_debian_stretch_server_linux5= .3.5_v1.0.img
>
> Alternatively, you can also choose to build and boot a recent buildroo= t [2]
> using the orangepi_pc_defconfig or Armbian image [3] for Orange Pi PC.=
> To attach an USB mass storage device to the machine, simply append to = the command:
>=C2=A0 =C2=A0-drive if=3Dnone,id=3Dstick,file=3Dmyimage.img \
>=C2=A0 =C2=A0-device usb-storage,bus=3Dusb-bus.0,drive=3Dstick
>
> U-Boot mainline can be build and configured using the orangepi_pc_defc= onfig
> using similar commands as describe above for Linux. To start U-Boot us= ing
> the Orange Pi PC machine, provide the u-boot binary to the -kernel arg= ument:
>=C2=A0 =C2=A0$ qemu-system-arm -M orangepi -m 512 -nic user -nographic = \
>=C2=A0 =C2=A0 =C2=A0 =C2=A0-kernel /path/to/uboot/u-boot -sd disk.img >
> Use the following U-boot commands to load and boot a Linux kernel from= SD card:
>=C2=A0 =C2=A0-> setenv bootargs console=3DttyS0,115200
>=C2=A0 =C2=A0-> ext2load mmc 0 0x42000000 zImage
>=C2=A0 =C2=A0-> ext2load mmc 0 0x43000000 sun8i-h2-plus-orangepi-zer= o.dtb
>=C2=A0 =C2=A0-> bootz 0x42000000 - 0x43000000
>
> Looking forward to your review comments. I will do my best
> to update the patches where needed.
>
> With kind regards,
>
> Niek Linnenbank
>
> [1] http://www.orangepi.org/downloadresources/ > [2] https://buildroot.org/download.html
> [3] https://www.armbian.com/orange-pi-pc/

Works well on my side with vanilla linux-4.9.13 built with gcc-8.3.0 + busy= box
and sun8i-h3-orangepi-one.dtb.

Tested-by: KONRAD Frederic <frederic.konrad@adacore.com>

Thank you for testing! Great, I'll add the tag fo= r the next v2 of the patches.

Regards,
N= iek
=C2=A0
>
> Niek Linnenbank (10):
>=C2=A0 =C2=A0 hw: arm: add Allwinner H3 System-on-Chip
>=C2=A0 =C2=A0 hw: arm: add Xunlong Orange Pi PC machine
>=C2=A0 =C2=A0 arm: allwinner-h3: add Clock Control Unit
>=C2=A0 =C2=A0 arm: allwinner-h3: add USB host controller
>=C2=A0 =C2=A0 arm: allwinner-h3: add System Control module
>=C2=A0 =C2=A0 arm/arm-powerctl: set NSACR.{CP11,CP10} bits in arm_set_c= pu_on()
>=C2=A0 =C2=A0 arm: allwinner-h3: add CPU Configuration module
>=C2=A0 =C2=A0 arm: allwinner-h3: add Security Identifier device
>=C2=A0 =C2=A0 arm: allwinner-h3: add SD/MMC host controller
>=C2=A0 =C2=A0 arm: allwinner-h3: add EMAC ethernet device
>
>=C2=A0 =C2=A0MAINTAINERS=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0|=C2=A0 =C2=A08 +
>=C2=A0 =C2=A0default-configs/arm-softmmu.mak=C2=A0 =C2=A0 =C2=A0 =C2=A0= |=C2=A0 =C2=A01 +
>=C2=A0 =C2=A0hw/arm/Kconfig=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 |=C2=A0 =C2=A09 +
>=C2=A0 =C2=A0hw/arm/Makefile.objs=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 |=C2=A0 =C2=A01 +
>=C2=A0 =C2=A0hw/arm/allwinner-h3.c=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0| 316 ++++++++++
>=C2=A0 =C2=A0hw/arm/orangepi.c=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0| 114 ++++
>=C2=A0 =C2=A0hw/misc/Makefile.objs=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0|=C2=A0 =C2=A04 +
>=C2=A0 =C2=A0hw/misc/allwinner-h3-clk.c=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 | 227 ++++++++
>=C2=A0 =C2=A0hw/misc/allwinner-h3-cpucfg.c=C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0| 280 +++++++++
>=C2=A0 =C2=A0hw/misc/allwinner-h3-sid.c=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 | 162 ++++++
>=C2=A0 =C2=A0hw/misc/allwinner-h3-syscon.c=C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0| 139 +++++
>=C2=A0 =C2=A0hw/misc/trace-events=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 |=C2=A0 =C2=A05 +
>=C2=A0 =C2=A0hw/net/Kconfig=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 |=C2=A0 =C2=A03 +
>=C2=A0 =C2=A0hw/net/Makefile.objs=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 |=C2=A0 =C2=A01 +
>=C2=A0 =C2=A0hw/net/allwinner-h3-emac.c=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 | 786 +++++++++++++++++++++++++
>=C2=A0 =C2=A0hw/net/trace-events=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0|=C2=A0 10 +
>=C2=A0 =C2=A0hw/sd/Makefile.objs=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0|=C2=A0 =C2=A01 +
>=C2=A0 =C2=A0hw/sd/allwinner-h3-sdhost.c=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0| 791 ++++++++++++++++++++++++++
>=C2=A0 =C2=A0hw/sd/trace-events=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 |=C2=A0 =C2=A07 +
>=C2=A0 =C2=A0hw/usb/hcd-ehci-sysbus.c=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0 |=C2=A0 17 +
>=C2=A0 =C2=A0hw/usb/hcd-ehci.h=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0|=C2=A0 =C2=A01 +
>=C2=A0 =C2=A0include/hw/arm/allwinner-h3.h=C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0| 130 +++++
>=C2=A0 =C2=A0include/hw/misc/allwinner-h3-clk.h=C2=A0 =C2=A0 |=C2=A0 41= ++
>=C2=A0 =C2=A0include/hw/misc/allwinner-h3-cpucfg.h |=C2=A0 44 ++
>=C2=A0 =C2=A0include/hw/misc/allwinner-h3-sid.h=C2=A0 =C2=A0 |=C2=A0 42= ++
>=C2=A0 =C2=A0include/hw/misc/allwinner-h3-syscon.h |=C2=A0 43 ++
>=C2=A0 =C2=A0include/hw/net/allwinner-h3-emac.h=C2=A0 =C2=A0 |=C2=A0 69= +++
>=C2=A0 =C2=A0include/hw/sd/allwinner-h3-sdhost.h=C2=A0 =C2=A0|=C2=A0 73= +++
>=C2=A0 =C2=A0target/arm/arm-powerctl.c=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0|=C2=A0 =C2=A03 +
>=C2=A0 =C2=A029 files changed, 3328 insertions(+)
>=C2=A0 =C2=A0create mode 100644 hw/arm/allwinner-h3.c
>=C2=A0 =C2=A0create mode 100644 hw/arm/orangepi.c
>=C2=A0 =C2=A0create mode 100644 hw/misc/allwinner-h3-clk.c
>=C2=A0 =C2=A0create mode 100644 hw/misc/allwinner-h3-cpucfg.c
>=C2=A0 =C2=A0create mode 100644 hw/misc/allwinner-h3-sid.c
>=C2=A0 =C2=A0create mode 100644 hw/misc/allwinner-h3-syscon.c
>=C2=A0 =C2=A0create mode 100644 hw/net/allwinner-h3-emac.c
>=C2=A0 =C2=A0create mode 100644 hw/sd/allwinner-h3-sdhost.c
>=C2=A0 =C2=A0create mode 100644 include/hw/arm/allwinner-h3.h
>=C2=A0 =C2=A0create mode 100644 include/hw/misc/allwinner-h3-clk.h
>=C2=A0 =C2=A0create mode 100644 include/hw/misc/allwinner-h3-cpucfg.h >=C2=A0 =C2=A0create mode 100644 include/hw/misc/allwinner-h3-sid.h
>=C2=A0 =C2=A0create mode 100644 include/hw/misc/allwinner-h3-syscon.h >=C2=A0 =C2=A0create mode 100644 include/hw/net/allwinner-h3-emac.h
>=C2=A0 =C2=A0create mode 100644 include/hw/sd/allwinner-h3-sdhost.h
>


--
Niek Linnenbank

--00000000000028c75e05995ee654-- From MAILER-DAEMON Tue Dec 10 15:01:21 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1ielhB-0005BE-BU for mharc-qemu-arm@gnu.org; Tue, 10 Dec 2019 15:01:21 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:39244) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ielh8-00058Q-Ij for qemu-arm@nongnu.org; Tue, 10 Dec 2019 15:01:19 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ielh7-0001BW-KM for qemu-arm@nongnu.org; Tue, 10 Dec 2019 15:01:18 -0500 Received: from us-smtp-delivery-1.mimecast.com ([205.139.110.120]:46863 helo=us-smtp-1.mimecast.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1ielh7-0001BL-GU for qemu-arm@nongnu.org; Tue, 10 Dec 2019 15:01:17 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1576008076; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=bEAUEOB7LB+RypVO7eHlN1fn53tR2X/eYnhGrNV5zco=; b=bGwg0P4PUJQ5pnqRTRHrum4Jf/FgUUlpyqowoKCsEGDOFyilYpcMoOSGlTbfj8c59A19k3 LWEGh4zBnzpOgTztZpMpjwSNxn3FAfH5GB3dpK3vezWs0dLRx7o5BPkOCRnBx6HJm8QMj9 ztlogTT4LXN8kqBHWYvOZCh+V7lyTt8= Received: from mail-qt1-f199.google.com (mail-qt1-f199.google.com [209.85.160.199]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-132-OaCuYBUyNZmWoGONd4P7AQ-1; Tue, 10 Dec 2019 15:01:13 -0500 Received: by mail-qt1-f199.google.com with SMTP id p12so2731468qtu.6 for ; Tue, 10 Dec 2019 12:01:13 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:in-reply-to:user-agent; bh=qmighPdvFfuz6us6owSwdskxRzaylH0auzyFxMqRTtU=; b=nhH3oEYJGbWMPzFOFbckppSaN2V3Il8vFO2ojbRjprhieFh4xfHNRkl0yvIH2JrInO VOOMd3bPyjY0tQTZKVDkbA2n8U9soGHLWbWTG6xDdQCtU5HMvs1G4dK8b61Q1PKX6J8m 2WU7iC9IO36dXX0e2jLSgHP3vowOjFAuWm1Il3KIAm1ya7L/PMplf0kWO33Af0Ab1hAC 87UduvooORuOgUgFT9cPhS0K84+poksWr9A917KbFoMOYrD87+B1FAXw047xWSCX2J+k HBfY+yLdASEG0W+b9YA0L/7cpt6PO8j+7MktW43bMcWUBUP0tEhPGdaVpyokFzWi2spz HXPA== X-Gm-Message-State: APjAAAXe9EFdRAy/s9hy0/P3ApVImmEa/1/1rMdVvWMlSSVGLkGd1gtu rHQ1NyqAtW8Hxv+nMB5UGwGydHwnQ7jTE4he5qEzJBBlKw+qpf9j3RRxzWX5WLbt5XZ/8qYuPjr ayc0CQn9Y6MvD X-Received: by 2002:a37:b883:: with SMTP id i125mr35081957qkf.64.1576008073412; Tue, 10 Dec 2019 12:01:13 -0800 (PST) X-Google-Smtp-Source: APXvYqwpKHR7Ukvyt8IrO1Iy5+7e6MLiWMUJIH4b7HaDp6iANDVzOuauwL4uTfz72zlcCOaj76dxxA== X-Received: by 2002:a37:b883:: with SMTP id i125mr35081915qkf.64.1576008073111; Tue, 10 Dec 2019 12:01:13 -0800 (PST) Received: from xz-x1 ([104.156.64.74]) by smtp.gmail.com with ESMTPSA id t11sm1219316qkm.92.2019.12.10.12.01.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 10 Dec 2019 12:01:12 -0800 (PST) Date: Tue, 10 Dec 2019 15:01:10 -0500 From: Peter Xu To: Eric Auger Cc: eric.auger.pro@gmail.com, qemu-devel@nongnu.org, qemu-arm@nongnu.org, peter.maydell@linaro.org, mst@redhat.com, armbru@redhat.com, jean-philippe.brucker@arm.com, bharatb.linux@gmail.com, yang.zhong@intel.com, dgilbert@redhat.com, quintela@redhat.com, kevin.tian@intel.com, tnowicki@marvell.com Subject: Re: [PATCH for-5.0 v11 18/20] virtio-iommu: Support migration Message-ID: <20191210200110.GM3352@xz-x1> References: <20191122182943.4656-1-eric.auger@redhat.com> <20191122182943.4656-19-eric.auger@redhat.com> MIME-Version: 1.0 In-Reply-To: <20191122182943.4656-19-eric.auger@redhat.com> User-Agent: Mutt/1.12.1 (2019-06-15) X-MC-Unique: OaCuYBUyNZmWoGONd4P7AQ-1 X-Mimecast-Spam-Score: 0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable Content-Disposition: inline X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 205.139.110.120 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 10 Dec 2019 20:01:19 -0000 On Fri, Nov 22, 2019 at 07:29:41PM +0100, Eric Auger wrote: > +static const VMStateDescription vmstate_virtio_iommu_device =3D { > + .name =3D "virtio-iommu-device", > + .minimum_version_id =3D 1, > + .version_id =3D 1, > + .post_load =3D iommu_post_load, > + .fields =3D (VMStateField[]) { > + VMSTATE_GTREE_DIRECT_KEY_V(domains, VirtIOIOMMU, 1, > + &vmstate_domain, viommu_domain), > + VMSTATE_GTREE_DIRECT_KEY_V(endpoints, VirtIOIOMMU, 1, > + &vmstate_endpoint, viommu_endpoint), IIUC vmstate_domain already contains all the endpoint information (in endpoint_list of vmstate_domain), but here we migrate it twice. I suppose that's why now we need reconstruct_ep_domain_link() to fixup the duplicated migration? Then I'll instead ask whether we can skip migrating here? Then in post_load we simply: foreach(domain) foreach(endpoint in domain) g_tree_insert(s->endpoints); It might help to avoid the reconstruct_ep_domain_link ugliness? And besides, I also agree with Jean that the endpoint data structure could be reused with IOMMUDevice somehow. Thanks, --=20 Peter Xu From MAILER-DAEMON Tue Dec 10 15:12:52 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1ielsK-0007aZ-7F for mharc-qemu-arm@gnu.org; Tue, 10 Dec 2019 15:12:52 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:43539) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ielsE-0007WC-HS for qemu-arm@nongnu.org; Tue, 10 Dec 2019 15:12:49 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ielsC-0006fh-EQ for qemu-arm@nongnu.org; Tue, 10 Dec 2019 15:12:46 -0500 Received: from mail-io1-xd2c.google.com ([2607:f8b0:4864:20::d2c]:46523) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1iels8-0006dF-70; Tue, 10 Dec 2019 15:12:40 -0500 Received: by mail-io1-xd2c.google.com with SMTP id t26so8755596ioi.13; Tue, 10 Dec 2019 12:12:40 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=wXF79992wt0z9yLgV32jgth2ukQCBU2SjhmYPQSjvTA=; b=NnCHMKpLVX6bx21f3ihWVTIGF3XzCpyrcrxFN5M3f7Dn3LUubc6Up6sEVJ80xmQlsI Vk59bmNy+2QURfrh8ygYmnjAHC/HZ0CJzYaR2t+mgpS1v6+JK/LSgtB08fQrmsBJyh54 /XTnO5kjm1fS28z6OaSgkJ8RSDPgKUpx4CnyVOsbGJF2F3tzBiLAhrHH03E6FD/oIHEs o7+mcZm76WHOdPXGuv7zXx5GhaE7JiUA+v1+LDBVxZCticqxxRQyssxGrCAZocSy2fJ6 86ssm5P0uBeCcExxxXqJs+PwiZdjzZ17B82XzWo4oa0UyYBd76nHRW6gMZN2WQGD3SQN vuwg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=wXF79992wt0z9yLgV32jgth2ukQCBU2SjhmYPQSjvTA=; b=YhjC7oAt162LcaaUdHXuDlDpaOKxnzKMIHErZjc1hkPp5715ZwmJrUjgG2kcHjMAUs DiLorl+Pbu7Q4ZE26EtByJY1Yn4CiyXMiPsHUvSErM1pDh/v8INR6BcCIkzIrNQuzr+k PMgZS2Enr4jlcllYYro5HnaoZR85UA6eVW7cSkBG9H+hF/56sFou1kZeHHHCFBfAoZLd SdWJVXXy9E3QKcke0jDDzjG/OFfA3lg4lO9e2sQt2r6YD3dgUHW4GB75n/XadahSRGIr 7LPXZKdjZD0ZWltRUSIYyW55nZmJW/xb107vvWaO2++QPvPc7dks3G19yOeTpS0QTixs a1Jw== X-Gm-Message-State: APjAAAXOp/+4vfgq4h0JE+FTAV96iKTw25GhnrZawnJmOdFzLGCaDFJI qT7wRSltwh1a3tjebKqYprZcgm3PKzpvuCFW7J0= X-Google-Smtp-Source: APXvYqy1RzotywzvT2jY6UDbh+BLvRsZr1eI6AoRbe3IOkDUh8yrAP7jYrdFDy0iijsiiIKiMsuwX7W+n6e4AeqiheY= X-Received: by 2002:a02:662a:: with SMTP id k42mr27982977jac.73.1576008759530; Tue, 10 Dec 2019 12:12:39 -0800 (PST) MIME-Version: 1.0 References: <20191202210947.3603-1-nieklinnenbank@gmail.com> <74df65db-1f84-62ba-6d01-edf765fd1dc2@redhat.com> In-Reply-To: <74df65db-1f84-62ba-6d01-edf765fd1dc2@redhat.com> From: Niek Linnenbank Date: Tue, 10 Dec 2019 21:12:28 +0100 Message-ID: Subject: Re: [PATCH 00/10] Add Allwinner H3 SoC and Orange Pi PC Machine To: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= Cc: QEMU Developers , Beniamino Galvani , Peter Maydell , qemu-arm , Richard Henderson Content-Type: multipart/alternative; boundary="000000000000465c4f05995f2266" X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::d2c X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 10 Dec 2019 20:12:49 -0000 --000000000000465c4f05995f2266 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Hi Philippe, On Tue, Dec 10, 2019 at 9:26 AM Philippe Mathieu-Daud=C3=A9 wrote: > On 12/9/19 10:37 PM, Niek Linnenbank wrote: > > Hi Philippe, > > > > On Tue, Dec 3, 2019 at 9:47 AM Philippe Mathieu-Daud=C3=A9 > > wrote: > > > > On 12/2/19 10:09 PM, Niek Linnenbank wrote: > > > Dear QEMU developers, > > > > > > Hereby I would like to contribute the following set of patches t= o > > QEMU > > > which add support for the Allwinner H3 System on Chip and the > > > Orange Pi PC machine. The following features and devices are > > supported: > > > > > > * SMP (Quad Core Cortex A7) > > > * Generic Interrupt Controller configuration > > > * SRAM mappings > > > * Timer device (re-used from Allwinner A10) > > > * UART > > > * SD/MMC storage controller > > > * EMAC ethernet connectivity > > > * USB 2.0 interfaces > > > * Clock Control Unit > > > * System Control module > > > * Security Identifier device > > > > Awesome! > > > > > Functionality related to graphical output such as HDMI, GPU, > > > Display Engine and audio are not included. Recently released > > > mainline Linux kernels (4.19 up to latest master) and mainline > U-Boot > > > are known to work. The SD/MMC code is tested using bonnie++ and > > > various tools such as fsck, dd and fdisk. The EMAC is verified > > with iperf3 > > > using -netdev socket. > > > > > > To build a Linux mainline kernel that can be booted by the Orang= e > > Pi PC > > > machine, simply configure the kernel using the sunxi_defconfig > > configuration: > > > $ ARCH=3Darm CROSS_COMPILE=3Darm-linux-gnueabi- make mrproper > > > $ ARCH=3Darm CROSS_COMPILE=3Darm-linux-gnueabi- make sunxi_def= config > > > > > > To be able to use USB storage, you need to manually enable the > > corresponding > > > configuration item. Start the kconfig configuration tool: > > > $ ARCH=3Darm CROSS_COMPILE=3Darm-linux-gnueabi- make menuconfi= g > > > > > > Navigate to the following item, enable it and save your > > configuration: > > > Device Drivers > USB support > USB Mass Storage support > > > > > > Build the Linux kernel with: > > > $ ARCH=3Darm CROSS_COMPILE=3Darm-linux-gnueabi- make -j5 > > > > > > To boot the newly build linux kernel in QEMU with the Orange Pi > > PC machine, use: > > > $ qemu-system-arm -M orangepi -m 512 -nic user -nographic \ > > > -kernel /path/to/linux/arch/arm/boot/zImage \ > > > -append 'console=3DttyS0,115200' \ > > > -dtb > /path/to/linux/arch/arm/boot/dts/sun8i-h3-orangepi-pc.dtb > > > > > > Note that this kernel does not have a root filesystem. You may > > provide it > > > with an official Orange Pi PC image [1] either as an SD card or = as > > > USB mass storage. To boot using the Orange Pi PC Debian image on > > SD card, > > > simply add the -sd argument and provide the proper root=3D kerne= l > > parameter: > > > $ qemu-system-arm -M orangepi -m 512 -nic user -nographic \ > > > -kernel /path/to/linux/arch/arm/boot/zImage \ > > > -append 'console=3DttyS0,115200 root=3D/dev/mmcblk0p2' \ > > > -dtb > > /path/to/linux/arch/arm/boot/dts/sun8i-h3-orangepi-pc.dtb \ > > > -sd OrangePi_pc_debian_stretch_server_linux5.3.5_v1.0.img > > > > > > Alternatively, you can also choose to build and boot a recent > > buildroot [2] > > > using the orangepi_pc_defconfig or Armbian image [3] for Orange > > Pi PC. > > > > Richard, trying the Armbian image from > > https://apt.armbian.com/pool/main/l/linux-4.20.7-sunxi/ I get: > > > > $ arm-softmmu/qemu-system-arm -M orangepi -m 512 -nic user \ > > -append 'console=3DttyS0,115200' \ > > -kernel boot/vmlinuz-4.20.7-sunxi \ > > -dtb usr/lib/linux-image-dev-sunxi/sun8i-h3-orangepi-pc.dtb \ > > -serial stdio -d unimp > > Uncompressing Linux... done, booting the kernel. > > rtc: unimplemented device write (size 4, value 0x16aa0001, offset > 0x0) > > rtc: unimplemented device read (size 4, offset 0x0) > > rtc: unimplemented device read (size 4, offset 0x0) > > rtc: unimplemented device read (size 4, offset 0x8) > > qemu-system-arm: target/arm/helper.c:11359: cpu_get_tb_cpu_state: > > Assertion `flags =3D=3D rebuild_hflags_internal(env)' failed. > > Aborted (core dumped) > > > > > > I'm trying to reproduce the error you reported here with my patch set o= n > > latest master, > > but so far without any result. The host OS I'm using is Ubuntu 18.04.3 > > LTS on x86_64. > > I ran several times using the same 4.20.7-sunxi kernel and same command > > line. > > > > Some questions that might help: > > 1) Are there any specific steps you did in order to produce this error? > > I build QEMU with: > > ./configure --enable-trace-backends=3Dlog --extra-cflags=3D-ggdb --enable= -debug > > > 2) Could this be a known / existing issue? > > 3) How many times did you see this error? > > Always > > > 4) Are you also using Ubuntu 18.04.3 LTS on x86_64, or a different host > OS? > > Host is Fedora 30. > OK thanks, I will try again using the info above after I finished reworking the other patch comments. Niek > > > > > Regards, > > Niek > > --=20 Niek Linnenbank --000000000000465c4f05995f2266 Content-Type: text/html; charset="UTF-8" Content-Transfer-Encoding: quoted-printable
Hi Philippe,

=
On Tue, Dec 10, 2019 at 9:26 AM Phili= ppe Mathieu-Daud=C3=A9 <philmd@redh= at.com> wrote:
On 12/9/19 10:37 PM, Niek Linnenbank wrote:
> Hi Philippe,
>
> On Tue, Dec 3, 2019 at 9:47 AM Philippe Mathieu-Daud=C3=A9 <philmd@redhat.com
> <mailto:phil= md@redhat.com>> wrote:
>
>=C2=A0 =C2=A0 =C2=A0On 12/2/19 10:09 PM, Niek Linnenbank wrote:
>=C2=A0 =C2=A0 =C2=A0 > Dear QEMU developers,
>=C2=A0 =C2=A0 =C2=A0 >
>=C2=A0 =C2=A0 =C2=A0 > Hereby I would like to contribute the followi= ng set of patches to
>=C2=A0 =C2=A0 =C2=A0QEMU
>=C2=A0 =C2=A0 =C2=A0 > which add support for the Allwinner H3 System= on Chip and the
>=C2=A0 =C2=A0 =C2=A0 > Orange Pi PC machine. The following features = and devices are
>=C2=A0 =C2=A0 =C2=A0supported:
>=C2=A0 =C2=A0 =C2=A0 >
>=C2=A0 =C2=A0 =C2=A0 >=C2=A0 =C2=A0* SMP (Quad Core Cortex A7)
>=C2=A0 =C2=A0 =C2=A0 >=C2=A0 =C2=A0* Generic Interrupt Controller co= nfiguration
>=C2=A0 =C2=A0 =C2=A0 >=C2=A0 =C2=A0* SRAM mappings
>=C2=A0 =C2=A0 =C2=A0 >=C2=A0 =C2=A0* Timer device (re-used from Allw= inner A10)
>=C2=A0 =C2=A0 =C2=A0 >=C2=A0 =C2=A0* UART
>=C2=A0 =C2=A0 =C2=A0 >=C2=A0 =C2=A0* SD/MMC storage controller
>=C2=A0 =C2=A0 =C2=A0 >=C2=A0 =C2=A0* EMAC ethernet connectivity
>=C2=A0 =C2=A0 =C2=A0 >=C2=A0 =C2=A0* USB 2.0 interfaces
>=C2=A0 =C2=A0 =C2=A0 >=C2=A0 =C2=A0* Clock Control Unit
>=C2=A0 =C2=A0 =C2=A0 >=C2=A0 =C2=A0* System Control module
>=C2=A0 =C2=A0 =C2=A0 >=C2=A0 =C2=A0* Security Identifier device
>
>=C2=A0 =C2=A0 =C2=A0Awesome!
>
>=C2=A0 =C2=A0 =C2=A0 > Functionality related to graphical output suc= h as HDMI, GPU,
>=C2=A0 =C2=A0 =C2=A0 > Display Engine and audio are not included. Re= cently released
>=C2=A0 =C2=A0 =C2=A0 > mainline Linux kernels (4.19 up to latest mas= ter) and mainline U-Boot
>=C2=A0 =C2=A0 =C2=A0 > are known to work. The SD/MMC code is tested = using bonnie++ and
>=C2=A0 =C2=A0 =C2=A0 > various tools such as fsck, dd and fdisk. The= EMAC is verified
>=C2=A0 =C2=A0 =C2=A0with iperf3
>=C2=A0 =C2=A0 =C2=A0 > using -netdev socket.
>=C2=A0 =C2=A0 =C2=A0 >
>=C2=A0 =C2=A0 =C2=A0 > To build a Linux mainline kernel that can be = booted by the Orange
>=C2=A0 =C2=A0 =C2=A0Pi PC
>=C2=A0 =C2=A0 =C2=A0 > machine, simply configure the kernel using th= e sunxi_defconfig
>=C2=A0 =C2=A0 =C2=A0configuration:
>=C2=A0 =C2=A0 =C2=A0 >=C2=A0 =C2=A0$ ARCH=3Darm CROSS_COMPILE=3Darm-= linux-gnueabi- make mrproper
>=C2=A0 =C2=A0 =C2=A0 >=C2=A0 =C2=A0$ ARCH=3Darm CROSS_COMPILE=3Darm-= linux-gnueabi- make sunxi_defconfig
>=C2=A0 =C2=A0 =C2=A0 >
>=C2=A0 =C2=A0 =C2=A0 > To be able to use USB storage, you need to ma= nually enable the
>=C2=A0 =C2=A0 =C2=A0corresponding
>=C2=A0 =C2=A0 =C2=A0 > configuration item. Start the kconfig configu= ration tool:
>=C2=A0 =C2=A0 =C2=A0 >=C2=A0 =C2=A0$ ARCH=3Darm CROSS_COMPILE=3Darm-= linux-gnueabi- make menuconfig
>=C2=A0 =C2=A0 =C2=A0 >
>=C2=A0 =C2=A0 =C2=A0 > Navigate to the following item, enable it and= save your
>=C2=A0 =C2=A0 =C2=A0configuration:
>=C2=A0 =C2=A0 =C2=A0 >=C2=A0 =C2=A0Device Drivers > USB support &= gt; USB Mass Storage support
>=C2=A0 =C2=A0 =C2=A0 >
>=C2=A0 =C2=A0 =C2=A0 > Build the Linux kernel with:
>=C2=A0 =C2=A0 =C2=A0 >=C2=A0 =C2=A0$ ARCH=3Darm CROSS_COMPILE=3Darm-= linux-gnueabi- make -j5
>=C2=A0 =C2=A0 =C2=A0 >
>=C2=A0 =C2=A0 =C2=A0 > To boot the newly build linux kernel in QEMU = with the Orange Pi
>=C2=A0 =C2=A0 =C2=A0PC machine, use:
>=C2=A0 =C2=A0 =C2=A0 >=C2=A0 =C2=A0$ qemu-system-arm -M orangepi -m = 512 -nic user -nographic \
>=C2=A0 =C2=A0 =C2=A0 >=C2=A0 =C2=A0 =C2=A0 =C2=A0-kernel /path/to/li= nux/arch/arm/boot/zImage \
>=C2=A0 =C2=A0 =C2=A0 >=C2=A0 =C2=A0 =C2=A0 =C2=A0-append 'consol= e=3DttyS0,115200' \
>=C2=A0 =C2=A0 =C2=A0 >=C2=A0 =C2=A0 =C2=A0 =C2=A0-dtb /path/to/linux= /arch/arm/boot/dts/sun8i-h3-orangepi-pc.dtb
>=C2=A0 =C2=A0 =C2=A0 >
>=C2=A0 =C2=A0 =C2=A0 > Note that this kernel does not have a root fi= lesystem. You may
>=C2=A0 =C2=A0 =C2=A0provide it
>=C2=A0 =C2=A0 =C2=A0 > with an official Orange Pi PC image [1] eithe= r as an SD card or as
>=C2=A0 =C2=A0 =C2=A0 > USB mass storage. To boot using the Orange Pi= PC Debian image on
>=C2=A0 =C2=A0 =C2=A0SD card,
>=C2=A0 =C2=A0 =C2=A0 > simply add the -sd argument and provide the p= roper root=3D kernel
>=C2=A0 =C2=A0 =C2=A0parameter:
>=C2=A0 =C2=A0 =C2=A0 >=C2=A0 =C2=A0$ qemu-system-arm -M orangepi -m = 512 -nic user -nographic \
>=C2=A0 =C2=A0 =C2=A0 >=C2=A0 =C2=A0 =C2=A0 =C2=A0-kernel /path/to/li= nux/arch/arm/boot/zImage \
>=C2=A0 =C2=A0 =C2=A0 >=C2=A0 =C2=A0 =C2=A0 =C2=A0-append 'consol= e=3DttyS0,115200 root=3D/dev/mmcblk0p2' \
>=C2=A0 =C2=A0 =C2=A0 >=C2=A0 =C2=A0 =C2=A0 =C2=A0-dtb
>=C2=A0 =C2=A0 =C2=A0/path/to/linux/arch/arm/boot/dts/sun8i-h3-orangepi-= pc.dtb \
>=C2=A0 =C2=A0 =C2=A0 >=C2=A0 =C2=A0 =C2=A0 =C2=A0-sd OrangePi_pc_deb= ian_stretch_server_linux5.3.5_v1.0.img
>=C2=A0 =C2=A0 =C2=A0 >
>=C2=A0 =C2=A0 =C2=A0 > Alternatively, you can also choose to build a= nd boot a recent
>=C2=A0 =C2=A0 =C2=A0buildroot [2]
>=C2=A0 =C2=A0 =C2=A0 > using the orangepi_pc_defconfig or Armbian im= age [3] for Orange
>=C2=A0 =C2=A0 =C2=A0Pi PC.
>
>=C2=A0 =C2=A0 =C2=A0Richard, trying the Armbian image from
>=C2=A0 =C2=A0 =C2=A0https://apt.armbian.c= om/pool/main/l/linux-4.20.7-sunxi/ I get:
>
>=C2=A0 =C2=A0 =C2=A0$ arm-softmmu/qemu-system-arm -M orangepi -m 512 -n= ic user \
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0-append 'console=3DttyS0,115200&#= 39; \
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0-kernel boot/vmlinuz-4.20.7-sunxi \ >=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0-dtb usr/lib/linux-image-dev-sunxi/su= n8i-h3-orangepi-pc.dtb \
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0-serial stdio -d unimp
>=C2=A0 =C2=A0 =C2=A0Uncompressing Linux... done, booting the kernel. >=C2=A0 =C2=A0 =C2=A0rtc: unimplemented device write (size 4, value 0x16= aa0001, offset 0x0)
>=C2=A0 =C2=A0 =C2=A0rtc: unimplemented device read (size 4, offset 0x0)=
>=C2=A0 =C2=A0 =C2=A0rtc: unimplemented device read (size 4, offset 0x0)=
>=C2=A0 =C2=A0 =C2=A0rtc: unimplemented device read (size 4, offset 0x8)=
>=C2=A0 =C2=A0 =C2=A0qemu-system-arm: target/arm/helper.c:11359: cpu_get= _tb_cpu_state:
>=C2=A0 =C2=A0 =C2=A0Assertion `flags =3D=3D rebuild_hflags_internal(env= )' failed.
>=C2=A0 =C2=A0 =C2=A0Aborted (core dumped)
>
>
> I'm trying to reproduce the error you reported here with my patch = set on
> latest master,
> but so far without any result. The host OS I'm using is Ubuntu 18.= 04.3
> LTS on x86_64.
> I ran several times using the same 4.20.7-sunxi kernel and same comman= d
> line.
>
> Some questions that might help:
> 1) Are there any specific steps you did in order to produce this error= ?

I build QEMU with:

./configure --enable-trace-backends=3Dlog --extra-cflags=3D-ggdb --enable-d= ebug

> 2) Could this be a known / existing issue?
> 3) How many times did you see this error?

Always

> 4) Are you also using Ubuntu 18.04.3 LTS on x86_64, or a different hos= t OS?

Host is Fedora 30.

OK thanks, I will tr= y again using the info above after I finished reworking the other patch com= ments.

Niek
=C2=A0

>
> Regards,
> Niek



--
Niek Linnenbank

--000000000000465c4f05995f2266-- From MAILER-DAEMON Tue Dec 10 17:14:27 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1ienlz-0005pV-1A for mharc-qemu-arm@gnu.org; Tue, 10 Dec 2019 17:14:27 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:57985) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ienlw-0005pK-O1 for qemu-arm@nongnu.org; Tue, 10 Dec 2019 17:14:25 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ienlv-0003CN-Aw for qemu-arm@nongnu.org; Tue, 10 Dec 2019 17:14:24 -0500 Received: from wout1-smtp.messagingengine.com ([64.147.123.24]:46149) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1ienlu-0003Ag-Ql; Tue, 10 Dec 2019 17:14:23 -0500 Received: from compute4.internal (compute4.nyi.internal [10.202.2.44]) by mailout.west.internal (Postfix) with ESMTP id 14F78D72; Tue, 10 Dec 2019 17:14:21 -0500 (EST) Received: from imap2 ([10.202.2.52]) by compute4.internal (MEProxy); Tue, 10 Dec 2019 17:14:21 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=aj.id.au; h= mime-version:message-id:in-reply-to:references:date:from:to:cc :subject:content-type:content-transfer-encoding; s=fm1; bh=RidXc mMmXmc5rXabxPfPVHMgYhwokctJfhox3MmbJIk=; b=QmxoGEyJt3fWmxfpf9F83 pL9+ggMWdJ6X7BTs5sxBhYCPW5XjAEawTh3Gdqlm/oSZ/hlDV8pmR2k+9KCwaWlz nfFtdD1BcYq4gNf1xJqOjmQVTXnascxpD/KWo7yC3djEe2eBSHUpEyL8GaP7RHd9 lEfnXFfU0bRNV4eJu12ByKtRoxtEowUZnMNXuDLS4d8pZrHSJHLTIvL9CSKvdYfb kT+pSnhtga1ZHFDs/+3QSPtJAfZnpXaVODoyiFoWCTZ5/RZ43WOAt0nZe0D8i0BM eT3lf9NoSGldV+893czIOsOJBjTStZJiIxRKoL+KCCoBgiBbi+hyZMaakGYXOVeE Q== DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d= messagingengine.com; h=cc:content-transfer-encoding:content-type :date:from:in-reply-to:message-id:mime-version:references :subject:to:x-me-proxy:x-me-proxy:x-me-sender:x-me-sender :x-sasl-enc; s=fm1; bh=RidXcmMmXmc5rXabxPfPVHMgYhwokctJfhox3MmbJ Ik=; b=oPXzfeL+oXtQbZUNZyQmepiqFqajuPhVNCoY1FY7RWM7hFesE+S9qcre6 jlc41xU+rBXGOtPKS01BcdDtr7Tlt6Wwa4cG0AB10564evtHur+nI4SFVpjN6eC9 9BtyUui466tz/AErA5INcCRjGRtljnEAEuKb+MI3nUXSPBhpjPowzElODu9VVFNG Do1WkW3HuYK0rq2Jm/HqPNcHaNHQSXsrWttFQ8aFir0HKvjLc4uKFR/l2VxBAVHg KvFsa7QinRtW08BBF/VACP6fUi7hanfa4lLvQcbdNEiHyHoLp2EiOfeyZe+1YtZQ g9Y03TjqruOEtob2nlYYcIYd/VMWg== X-ME-Sender: X-ME-Proxy-Cause: gggruggvucftvghtrhhoucdtuddrgedufedrudelfedgudehkecutefuodetggdotefrod ftvfcurfhrohhfihhlvgemucfhrghsthforghilhdpqfgfvfdpuffrtefokffrpgfnqfgh necuuegrihhlohhuthemuceftddtnecusecvtfgvtghiphhivghnthhsucdlqddutddtmd enucfjughrpefofgggkfgjfhffhffvufgtgfesthhqredtreerjeenucfhrhhomhepfdet nhgurhgvficulfgvfhhfvghrhidfuceorghnughrvgifsegrjhdrihgurdgruheqnecurf grrhgrmhepmhgrihhlfhhrohhmpegrnhgurhgvfiesrghjrdhiugdrrghunecuvehluhhs thgvrhfuihiivgeptd X-ME-Proxy: Received: by mailuser.nyi.internal (Postfix, from userid 501) id 35CDBE00A2; Tue, 10 Dec 2019 17:14:20 -0500 (EST) X-Mailer: MessagingEngine.com Webmail Interface User-Agent: Cyrus-JMAP/3.1.7-679-g1f7ccac-fmstable-20191210v1 Mime-Version: 1.0 Message-Id: In-Reply-To: References: <5a93d2f9d375f92e9db6b1cf8687f86beaedcbb2.1575938234.git-series.andrew@aj.id.au> Date: Wed, 11 Dec 2019 08:45:59 +1030 From: "Andrew Jeffery" To: =?UTF-8?Q?C=C3=A9dric_Le_Goater?= , qemu-arm@nongnu.org Cc: "Peter Maydell" , "Joel Stanley" , qemu-devel@nongnu.org Subject: Re: [PATCH 2/2] hw/arm: ast2600: Wire up the eMMC controller Content-Type: text/plain;charset=utf-8 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 64.147.123.24 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 10 Dec 2019 22:14:26 -0000 On Tue, 10 Dec 2019, at 23:22, C=C3=A9dric Le Goater wrote: > On 10/12/2019 01:52, Andrew Jeffery wrote: > > Initialise another SDHCI model instance for the AST2600's eMMC > > controller and use the SDHCI's num_slots value introduced previously= to > > determine whether we should create an SD card instance for the new s= lot. > >=20 > > Signed-off-by: Andrew Jeffery >=20 > LGTM. One comment. >=20 > > --- > > hw/arm/aspeed.c | 13 +++++++++++++ > > hw/arm/aspeed_ast2600.c | 21 +++++++++++++++++++++ > > include/hw/arm/aspeed_soc.h | 2 ++ > > 3 files changed, 36 insertions(+) > >=20 > > diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c > > index 862549b1f3a9..0e08d62e9ff3 100644 > > --- a/hw/arm/aspeed.c > > +++ b/hw/arm/aspeed.c > > @@ -272,6 +272,19 @@ static void aspeed_board_init(MachineState *mac= hine, > > object_property_set_bool(OBJECT(card), true, "realized", &e= rror_fatal); > > } > > =20 > > + if (bmc->soc.emmc.num_slots) { > > + SDHCIState *emmc =3D &bmc->soc.emmc.slots[0]; > > + DriveInfo *dinfo =3D drive_get_next(IF_SD); > > + BlockBackend *blk; > > + DeviceState *card; > > + > > + blk =3D dinfo ? blk_by_legacy_dinfo(dinfo) : NULL; > > + card =3D qdev_create(qdev_get_child_bus(DEVICE(emmc), "sd-b= us"), > > + TYPE_SD_CARD); > > + qdev_prop_set_drive(card, "drive", blk, &error_fatal); > > + object_property_set_bool(OBJECT(card), true, "realized", &e= rror_fatal); > > + } >=20 > I think we could use a function for the above ^ Yep, I'll refactor that. Andrew From MAILER-DAEMON Tue Dec 10 17:16:18 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1iennm-0007O5-6g for mharc-qemu-arm@gnu.org; Tue, 10 Dec 2019 17:16:18 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:60796) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iennj-0007KJ-6c for qemu-arm@nongnu.org; Tue, 10 Dec 2019 17:16:16 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1iennh-00050y-UD for qemu-arm@nongnu.org; Tue, 10 Dec 2019 17:16:15 -0500 Received: from wout1-smtp.messagingengine.com ([64.147.123.24]:46433) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1iennh-0004yv-Hi; Tue, 10 Dec 2019 17:16:13 -0500 Received: from compute4.internal (compute4.nyi.internal [10.202.2.44]) by mailout.west.internal (Postfix) with ESMTP id B5E4AED3; Tue, 10 Dec 2019 17:16:11 -0500 (EST) Received: from imap2 ([10.202.2.52]) by compute4.internal (MEProxy); Tue, 10 Dec 2019 17:16:12 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=aj.id.au; h= mime-version:message-id:in-reply-to:references:date:from:to:cc :subject:content-type:content-transfer-encoding; s=fm1; bh=o3/w2 8DcUaCOTUMXgSPrVlQr0SfHyxTg5qkRp+tl6uc=; b=U7jBl7/RB/bZWlk+DKnMi Nk5UWkXR00ZoTNs5uJlKVH07CTT5lySk2m7PwScT7eFGyOtr8mBPE/zAMt3NvupV iMFL8sghteoEHp5rZjQiHcasP8JfZxKWSKvibS1Ixot0Zaqte4xqVq09SXZahKaI 11Em55qluxEw1z3NppUqtrbLgN6ITguKS2gpcIp3/OQUQ0+d7/dSNRbk/wgnylbe 8v5rk2+d6UUnJnvpBrOXXeqmWMS66f1gkHliJWYR/D+EHFS4FmPcyHkPid0Ilbxm bbHOUCgamQMqVVndAUy+nypSCY/VyYnaPC4Lgpcr/B1a6NXPJMqJcaSGrJg2ejri Q== DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d= messagingengine.com; h=cc:content-transfer-encoding:content-type :date:from:in-reply-to:message-id:mime-version:references :subject:to:x-me-proxy:x-me-proxy:x-me-sender:x-me-sender :x-sasl-enc; s=fm1; bh=o3/w28DcUaCOTUMXgSPrVlQr0SfHyxTg5qkRp+tl6 uc=; b=botsc4e4CfHucumguvrs5rYd/5kgA4EVTA2XlM4U9Mq2Ec+5hV/o0zc8W Vhm3lQ4EmWlUJy158Wvmy8GJuwz0CnGLxbqNiUz92yxtdQ0phmVRWOzFwvypn5a/ MqpuBhKf/gilCPQWL3Q8jjbEVpmTaPIHm3n0hzsq/1Y7U1D4ESczEddqKSCTFSMX KYMZOdbiD4ebuifYJ8R5LTHLztJbUf55r4539erekhG9KZQFTKk7sOonqg505iQP vzbB3cq/MEfExfhxtQlWpTL57Sb0zEHdm8ylG9gHhoxgQnyFcd0xc1adlUvI4hpC 42HVatkme13u42/3SNIHwxjE2khaA== X-ME-Sender: X-ME-Proxy-Cause: gggruggvucftvghtrhhoucdtuddrgedufedrudelfedgudehkecutefuodetggdotefrod ftvfcurfhrohhfihhlvgemucfhrghsthforghilhdpqfgfvfdpuffrtefokffrpgfnqfgh necuuegrihhlohhuthemuceftddtnecusecvtfgvtghiphhivghnthhsucdlqddutddtmd enucfjughrpefofgggkfgjfhffhffvufgtgfesthhqredtreerjeenucfhrhhomhepfdet nhgurhgvficulfgvfhhfvghrhidfuceorghnughrvgifsegrjhdrihgurdgruheqnecurf grrhgrmhepmhgrihhlfhhrohhmpegrnhgurhgvfiesrghjrdhiugdrrghunecuvehluhhs thgvrhfuihiivgepud X-ME-Proxy: Received: by mailuser.nyi.internal (Postfix, from userid 501) id A3F98E00A2; Tue, 10 Dec 2019 17:16:10 -0500 (EST) X-Mailer: MessagingEngine.com Webmail Interface User-Agent: Cyrus-JMAP/3.1.7-679-g1f7ccac-fmstable-20191210v1 Mime-Version: 1.0 Message-Id: <27aa4292-cc3b-4a9b-a13d-ab1eced3f952@www.fastmail.com> In-Reply-To: References: <11e1d38d2374a48996a3496c906db215de246583.1575938234.git-series.andrew@aj.id.au> Date: Wed, 11 Dec 2019 08:47:50 +1030 From: "Andrew Jeffery" To: =?UTF-8?Q?C=C3=A9dric_Le_Goater?= , qemu-arm@nongnu.org Cc: "Peter Maydell" , "Joel Stanley" , qemu-devel@nongnu.org Subject: =?UTF-8?Q?Re:_[PATCH_1/2]_hw/sd:_Configure_number_of_slots_exposed_by_th?= =?UTF-8?Q?e_ASPEED_SDHCI_model?= Content-Type: text/plain;charset=utf-8 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 64.147.123.24 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 10 Dec 2019 22:16:16 -0000 On Tue, 10 Dec 2019, at 19:26, C=C3=A9dric Le Goater wrote: > On 10/12/2019 01:52, Andrew Jeffery wrote: > > The AST2600 includes a second cut-down version of the SD/MMC control= ler > > found in the AST2500, named the eMMC controller. It's cut down in th= e > > sense that it only supports one slot rather than two, but it brings = the > > total number of slots supported by the AST2600 to three. > >=20 > > The existing code assumed that the SD controller always provided two= > > slots. Rework the SDHCI object to expose the number of slots as a > > property to be set by the SoC configuration. > >=20 > > Signed-off-by: Andrew Jeffery >=20 > Reviewed-by: C=C3=A9dric Le Goater >=20 > One minor question below. >=20 >=20 > > --- > > hw/arm/aspeed.c | 2 +- > > hw/arm/aspeed_ast2600.c | 2 ++ > > hw/arm/aspeed_soc.c | 3 +++ > > hw/sd/aspeed_sdhci.c | 11 +++++++++-- > > include/hw/sd/aspeed_sdhci.h | 1 + > > 5 files changed, 16 insertions(+), 3 deletions(-) > >=20 > > diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c > > index 028191ff36fc..862549b1f3a9 100644 > > --- a/hw/arm/aspeed.c > > +++ b/hw/arm/aspeed.c > > @@ -259,7 +259,7 @@ static void aspeed_board_init(MachineState *mach= ine, > > cfg->i2c_init(bmc); > > } > > =20 > > - for (i =3D 0; i < ARRAY_SIZE(bmc->soc.sdhci.slots); i++) { > > + for (i =3D 0; i < bmc->soc.sdhci.num_slots; i++) { > > SDHCIState *sdhci =3D &bmc->soc.sdhci.slots[i]; > > DriveInfo *dinfo =3D drive_get_next(IF_SD); > > BlockBackend *blk; > > diff --git a/hw/arm/aspeed_ast2600.c b/hw/arm/aspeed_ast2600.c > > index 931887ac681f..931ee5aae183 100644 > > --- a/hw/arm/aspeed_ast2600.c > > +++ b/hw/arm/aspeed_ast2600.c > > @@ -208,6 +208,8 @@ static void aspeed_soc_ast2600_init(Object *obj)= > > sysbus_init_child_obj(obj, "sdc", OBJECT(&s->sdhci), sizeof(s->= sdhci), > > TYPE_ASPEED_SDHCI); > > =20 > > + object_property_set_int(OBJECT(&s->sdhci), 2, "num-slots", &err= or_abort); >=20 > OK. This defines 2 SDHCI slots for the ast2600 SoC, but >=20 > > + > > /* Init sd card slot class here so that they're under the corre= ct parent */ > > for (i =3D 0; i < ASPEED_SDHCI_NUM_SLOTS; ++i) { > > sysbus_init_child_obj(obj, "sdhci[*]", OBJECT(&s->sdhci.slo= ts[i]), > > diff --git a/hw/arm/aspeed_soc.c b/hw/arm/aspeed_soc.c > > index f4fe243458fd..3498f55603f2 100644 > > --- a/hw/arm/aspeed_soc.c > > +++ b/hw/arm/aspeed_soc.c > > @@ -215,6 +215,9 @@ static void aspeed_soc_init(Object *obj) > > sysbus_init_child_obj(obj, "sdc", OBJECT(&s->sdhci), sizeof(s->= sdhci), > > TYPE_ASPEED_SDHCI); > > =20 > > + object_property_set_int(OBJECT(&s->sdhci), ASPEED_SDHCI_NUM_SLO= TS, > > + "num-slots", &error_abort); >=20 >=20 > why use ASPEED_SDHCI_NUM_SLOTS here ? No good reason. I'll just switch it to '2' like in the 2600. Andrew From MAILER-DAEMON Tue Dec 10 17:17:44 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1ienpA-0000Bv-1g for mharc-qemu-arm@gnu.org; Tue, 10 Dec 2019 17:17:44 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:34091) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ienp7-00009T-CV for qemu-arm@nongnu.org; Tue, 10 Dec 2019 17:17:42 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ienp6-00064a-G8 for qemu-arm@nongnu.org; Tue, 10 Dec 2019 17:17:41 -0500 Received: from wout1-smtp.messagingengine.com ([64.147.123.24]:46001) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1ienp6-00063i-Ap; Tue, 10 Dec 2019 17:17:40 -0500 Received: from compute4.internal (compute4.nyi.internal [10.202.2.44]) by mailout.west.internal (Postfix) with ESMTP id 07B15ED3; Tue, 10 Dec 2019 17:17:38 -0500 (EST) Received: from imap2 ([10.202.2.52]) by compute4.internal (MEProxy); Tue, 10 Dec 2019 17:17:39 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=aj.id.au; h= mime-version:message-id:in-reply-to:references:date:from:to:cc :subject:content-type:content-transfer-encoding; s=fm1; bh=3kGtz jp6D7Ka8D3pEkJj4zEeNC+L5CcFXQR/+ho4LW8=; b=gn61h7XjJ+L+CZjx1+Wtf khaU/OmeECCNZaZuWkHfmuhuW6SeZMF8CluM1xwV+29ttGJMEjXyn+yIS6U9NN0g m2rarxcxDZwx6P/aRq25+ieTGKrk4VsvaMwOMDq7C3bW2XYnH0J9okWMuL5oC3IV KHVlCoRIU+/KLwvJS0D1zQJMDlraP3q7rMGgfELjQuk6lb4vBUZLmPq049s0SOck OKYGYGMUvOJlmfJkkmerORjGWvGIwGAfF1hilcutXAtsZT8C0u5DhcX7j+bJlpyv YhbyjovObBd4l354iDu+0jom552crXsqVqpENBSo+b9DwuSUVWyLCKpL1lB+n0kX A== DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d= messagingengine.com; h=cc:content-transfer-encoding:content-type :date:from:in-reply-to:message-id:mime-version:references :subject:to:x-me-proxy:x-me-proxy:x-me-sender:x-me-sender :x-sasl-enc; s=fm1; bh=3kGtzjp6D7Ka8D3pEkJj4zEeNC+L5CcFXQR/+ho4L W8=; b=GBKwuY7ncsqFIc0lMp09ceJUEAC9nNLQl9QV4ic2xD3ADI/mu8P0jS+Cs A9rS8ByOdKKFTvT3FbcIfiIQ74NaQcSa6vuAPEM2/vlvJC7Kc8RL54WidcXsC+SH cyuhbriRAMTjAEMBpdJBX5PUJ/nflUzUUTy9a4A4E8fr9l/yTA0TR/nw1Nkm7f/4 JLkx+2STDwE3hPuZwvSg7rDI+Mfnrqg7ZNOap06mdu0Zeel4VStY+vezl5uyArRF x+4EA2/0Lkle6RdMeMXKbazPKWN174vrRTc+7kUZrUB+VgqsVI7IEWUoojnrWQ6g Qg1/8RfA4Az5tr0LsS6GkgdTKNSLg== X-ME-Sender: X-ME-Proxy-Cause: gggruggvucftvghtrhhoucdtuddrgedufedrudelfedgudehlecutefuodetggdotefrod ftvfcurfhrohhfihhlvgemucfhrghsthforghilhdpqfgfvfdpuffrtefokffrpgfnqfgh necuuegrihhlohhuthemuceftddtnecusecvtfgvtghiphhivghnthhsucdlqddutddtmd enucfjughrpefofgggkfgjfhffhffvufgtgfesthhqredtreerjeenucfhrhhomhepfdet nhgurhgvficulfgvfhhfvghrhidfuceorghnughrvgifsegrjhdrihgurdgruheqnecurf grrhgrmhepmhgrihhlfhhrohhmpegrnhgurhgvfiesrghjrdhiugdrrghunecuvehluhhs thgvrhfuihiivgeptd X-ME-Proxy: Received: by mailuser.nyi.internal (Postfix, from userid 501) id 2E52EE00A5; Tue, 10 Dec 2019 17:17:38 -0500 (EST) X-Mailer: MessagingEngine.com Webmail Interface User-Agent: Cyrus-JMAP/3.1.7-679-g1f7ccac-fmstable-20191210v1 Mime-Version: 1.0 Message-Id: <94dbdf58-399b-49ca-b644-87f54795a7a1@www.fastmail.com> In-Reply-To: <378a875a-17c8-3b35-9753-2158e86c5412@kaod.org> References: <378a875a-17c8-3b35-9753-2158e86c5412@kaod.org> Date: Wed, 11 Dec 2019 08:49:16 +1030 From: "Andrew Jeffery" To: =?UTF-8?Q?C=C3=A9dric_Le_Goater?= , qemu-arm@nongnu.org Cc: "Peter Maydell" , "Joel Stanley" , qemu-devel@nongnu.org Subject: Re: [PATCH 0/2] hw/arm: ast2600: Wire up eMMC controller Content-Type: text/plain;charset=utf-8 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 64.147.123.24 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 10 Dec 2019 22:17:42 -0000 On Tue, 10 Dec 2019, at 19:23, C=C3=A9dric Le Goater wrote: > On 10/12/2019 01:52, Andrew Jeffery wrote: > > Hello, > >=20 > > The AST2600 has an additional SDHCI intended for use as an eMMC boot= source. >=20 > Have you also considered booting the QEMU Aspeed AST2600 machine=20 > from the eMMC device ? >=20 I hadn't got that far. I was surprised we hadn't yet wired up the eMMC c= ontroller at all, so I solved that problem first :) Andrew From MAILER-DAEMON Wed Dec 11 02:57:45 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1iewsT-00011T-F8 for mharc-qemu-arm@gnu.org; Wed, 11 Dec 2019 02:57:45 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:58958) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iewsP-00010O-LE for qemu-arm@nongnu.org; Wed, 11 Dec 2019 02:57:43 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1iewsO-0000DA-2K for qemu-arm@nongnu.org; Wed, 11 Dec 2019 02:57:41 -0500 Received: from us-smtp-delivery-1.mimecast.com ([205.139.110.120]:39616 helo=us-smtp-1.mimecast.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1iewsN-0000Bz-SP for qemu-arm@nongnu.org; Wed, 11 Dec 2019 02:57:40 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; 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Wed, 11 Dec 2019 07:57:29 +0000 (UTC) Date: Wed, 11 Dec 2019 08:57:27 +0100 From: Igor Mammedov To: Shameerali Kolothum Thodi Cc: "xiaoguangrong.eric@gmail.com" , "peter.maydell@linaro.org" , "drjones@redhat.com" , "shannon.zhaosl@gmail.com" , "qemu-devel@nongnu.org" , Linuxarm , Auger Eric , "qemu-arm@nongnu.org" , "xuwei (O)" , "lersek@redhat.com" Subject: Re: [PATCH 0/5] ARM virt: Add NVDIMM support Message-ID: <20191211085727.1ab9564e@redhat.com> In-Reply-To: References: <20191004155302.4632-1-shameerali.kolothum.thodi@huawei.com> <441c818f24084b4191315cf2a6267cef@huawei.com> <20191125164541.3f0a593f@redhat.com> <444efcb441fe42e5aff58b3af3ab14b4@huawei.com> <20191126095655.27227f59@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.79 on 10.5.11.11 X-MC-Unique: HMXTjCAgMHOkVVSiRx10uQ-1 X-Mimecast-Spam-Score: 0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 205.139.110.120 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 11 Dec 2019 07:57:43 -0000 On Mon, 9 Dec 2019 17:39:15 +0000 Shameerali Kolothum Thodi wrote: > Hi Igor/ xiaoguangrong, > > > -----Original Message----- > > From: Shameerali Kolothum Thodi > > Sent: 28 November 2019 12:36 > > To: 'Igor Mammedov' ; > > xiaoguangrong.eric@gmail.com > > Cc: peter.maydell@linaro.org; drjones@redhat.com; > > shannon.zhaosl@gmail.com; qemu-devel@nongnu.org; Linuxarm > > ; Auger Eric ; > > qemu-arm@nongnu.org; xuwei (O) ; > > lersek@redhat.com > > Subject: RE: [PATCH 0/5] ARM virt: Add NVDIMM support > > > > > > > > > -----Original Message----- > > > From: Qemu-devel > > > > > [mailto:qemu-devel-bounces+shameerali.kolothum.thodi=huawei.com@nongn > > > u.org] On Behalf Of Igor Mammedov > > > Sent: 26 November 2019 08:57 > > > To: Shameerali Kolothum Thodi > > > Cc: peter.maydell@linaro.org; drjones@redhat.com; > > > xiaoguangrong.eric@gmail.com; shannon.zhaosl@gmail.com; > > > qemu-devel@nongnu.org; Linuxarm ; Auger Eric > > > ; qemu-arm@nongnu.org; xuwei (O) > > > ; lersek@redhat.com > > > Subject: Re: [PATCH 0/5] ARM virt: Add NVDIMM support > > > > [..] > > > > > > > 0xb8 Dirty No. -->Another read is attempted > > > > > > [Qemu]NVDIMM:nvdimm_dsm_func_read_fit: read_fit_out buf size 0x8 > > > > > func_ret_status 3 --> Error status returned > > > > > > > > > > status 3 means that QEMU didn't like content of NRAM, and there is only > > > > > 1 place like this in nvdimm_dsm_func_read_fit() > > > > > if (read_fit->offset > fit->len) { > > > > > func_ret_status = NVDIMM_DSM_RET_STATUS_INVALID; > > > > > goto exit; > > > > > } > > > > > > > > > > so I'd start looking from here and check that QEMU gets expected data > > > > > in nvdimm_dsm_write(). In other words I'd try to trace/compare > > > > > content of DSM buffer (from qemu side). > > > > > > > > I had printed the DSM buffer previously and it looked same, I will double > > check > > > > that. > > > > Tried printing the buffer in both Qemu/AML code. > > > > On Amr64, > > [...] > > > Attached the SSDT.dsl used for debugging. I am still not clear why on ARM64, > > 2nd iteration case, the created buffer size in NCAL and RFIT methods have > > additional 4 bytes!. > > > > CreateField (ODAT, Zero, Local1, OBUF) > > Concatenate (Buffer (Zero){}, OBUF, Local7) > > > > Please let me know if you have any clue. > > > > I couldn't figure out yet, why this extra 4 bytes are added by aml code on ARM64 > when the nvdimm_dsm_func_read_fit() returns NvdimmFuncReadFITOut without > any FIT data. ie, when the FIT buffer len (read_len) is zero. > > But the below will fix this issue, > > diff --git a/hw/acpi/nvdimm.c b/hw/acpi/nvdimm.c > index f91eea3802..cddf95f4c1 100644 > --- a/hw/acpi/nvdimm.c > +++ b/hw/acpi/nvdimm.c > @@ -588,7 +588,7 @@ static void nvdimm_dsm_func_read_fit(NVDIMMState *state, NvdimmDsmIn *in, > nvdimm_debug("Read FIT: offset %#x FIT size %#x Dirty %s.\n", > read_fit->offset, fit->len, fit_buf->dirty ? "Yes" : "No"); > > - if (read_fit->offset > fit->len) { > + if (read_fit->offset >= fit->len) { > func_ret_status = NVDIMM_DSM_RET_STATUS_INVALID; > goto exit; > } > > > This will return error code to aml in the second iteration when there is no further > FIT data to report. But, I am not sure why this check was omitted in the first place. > > Please let me know if this is acceptable and then probably I can look into a v2 of this > series. Sorry, I don't have capacity to debug this right now, but I'd prefer if 'why' question was answered first. Anyways, if something is unclear in how concrete AML code is build/works, feel free to ask and I'll try to explain and guide you. > Thanks, > Shameer > > > From MAILER-DAEMON Wed Dec 11 03:03:16 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1iewxo-0002qp-8g for mharc-qemu-arm@gnu.org; Wed, 11 Dec 2019 03:03:16 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:33058) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iewxl-0002qh-Cs for qemu-arm@nongnu.org; Wed, 11 Dec 2019 03:03:14 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1iewxi-0001je-62 for qemu-arm@nongnu.org; Wed, 11 Dec 2019 03:03:13 -0500 Received: from szxga04-in.huawei.com ([45.249.212.190]:2222 helo=huawei.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1iewxh-0001ND-OE; Wed, 11 Dec 2019 03:03:10 -0500 Received: from DGGEMS406-HUB.china.huawei.com (unknown [172.30.72.59]) by Forcepoint Email with ESMTP id 5F1A8C7F098378EFBC40; Wed, 11 Dec 2019 16:02:56 +0800 (CST) Received: from [127.0.0.1] (10.133.216.73) by DGGEMS406-HUB.china.huawei.com (10.3.19.206) with Microsoft SMTP Server id 14.3.439.0; Wed, 11 Dec 2019 16:02:53 +0800 Subject: Re: [PATCH v1 0/5] target/arm/kvm: Provide an option to adjust virtual time To: Peter Maydell , Andrew Jones CC: Marc Zyngier , qemu-arm , "Richard Henderson" , QEMU Developers , References: <20191016143410.5023-1-drjones@redhat.com> From: Guoheyi Message-ID: <5679d43f-3f29-6ee1-0894-19ef2f3e08a2@huawei.com> Date: Wed, 11 Dec 2019 16:02:52 +0800 User-Agent: Mozilla/5.0 (Windows NT 10.0; WOW64; rv:68.0) Gecko/20100101 Thunderbird/68.2.2 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset="utf-8"; format=flowed X-Originating-IP: [10.133.216.73] X-CFilter-Loop: Reflected Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 45.249.212.190 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 11 Dec 2019 08:03:15 -0000 =E5=9C=A8 2019/12/6 23:22, Peter Maydell =E5=86=99=E9=81=93: > On Wed, 16 Oct 2019 at 15:34, Andrew Jones wrote: >> v2: >> - move from RFC status to v1 >> - put kvm_arm_vm_state_change() in kvm.c to share among kvm32.c and = kvm64.c >> - add r-b's from Richard >> >> >> This series is inspired by a series[1] posted by Bijan Mottahedeh abou= t >> a year ago. The problem described in the cover letter of [1] is easil= y >> reproducible and some users would like to have the option to avoid it. >> However the solution, which is to adjust the virtual counter offset ea= ch >> time the VM transitions to the running state, introduces a different >> problem, which is that the virtual and physical counters diverge. As >> described in the cover letter of [1] this divergence is easily observe= d >> when comparing the output of `date` and `hwclock` after suspending the >> guest, waiting a while, and then resuming it. Because this different >> problem may actually be worse for some users, unlike [1], the series >> posted here makes the virtual counter offset adjustment optional and n= ot >> even enabled by default. Besides the adjustment being optional, this >> series approaches the needed changes differently to apply them in more >> appropriate locations. Finally, unlike [1], this series doesn't attem= pt >> to measure "pause time" itself. Simply using QEMU_CLOCK_VIRTUAL, whic= h >> only ticks when the VM is not stopped, is sufficient. > So I guess my overall question is "what is the x86 solution to > this problem, and why is this all arm-specific?" It would also > be helpful to know how it fits into all the other proposals regarding > time in VMs. I also sent a RFC in March and ARM KVM experts were also invoved in the=20 discussion: https://lists.cs.columbia.edu/pipermail/kvmarm/2019-March/035026.html According to the discussion, qemu on x86 is using KVM_KVMCLOCK_CTRL to=20 request KVM to set a flag "PVCLOCK_GUEST_STOPPED" in pvclock, informing=20 VM kernel about external force stop. Thanks, Heyi > > thanks > -- PMM > > From MAILER-DAEMON Wed Dec 11 04:00:15 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1iexqx-0002nd-Jq for mharc-qemu-arm@gnu.org; Wed, 11 Dec 2019 04:00:15 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:40461) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iexqu-0002nH-ML for qemu-arm@nongnu.org; Wed, 11 Dec 2019 04:00:14 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1iexqs-00081b-An for qemu-arm@nongnu.org; Wed, 11 Dec 2019 04:00:11 -0500 Received: from us-smtp-1.mimecast.com ([207.211.31.81]:20806 helo=us-smtp-delivery-1.mimecast.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1iexqs-00080L-5Y for qemu-arm@nongnu.org; Wed, 11 Dec 2019 04:00:10 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1576054809; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=dsHsAeCyGP+9vg/yV/H6LJG7OyvEe3wO3zM0wa/wLoI=; b=NFKsZsBYCAULlWXHWluTKHRkdKExbfpACdonMggVb0bVm9+AK7SvVX62CUwQgRm+ZMXe+6 +u5MROwjKnl8mmelFmOoox539oetgUnwqM5rlbBi2nDcLeLTpXcnntHGjYGtSeNT48/9gl WqBmoe6W+7t33fsrhWgcVtK8ZVHXK6o= Received: from mimecast-mx01.redhat.com (mimecast-mx01.redhat.com [209.132.183.4]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-315-RBmE-DGYPhCnVrDWe5RguQ-1; Wed, 11 Dec 2019 04:00:06 -0500 Received: from smtp.corp.redhat.com (int-mx08.intmail.prod.int.phx2.redhat.com [10.5.11.23]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx01.redhat.com (Postfix) with ESMTPS id C23C48E30B0; Wed, 11 Dec 2019 09:00:04 +0000 (UTC) Received: from kamzik.brq.redhat.com (unknown [10.43.2.160]) by smtp.corp.redhat.com (Postfix) with ESMTPS id 178DF19756; Wed, 11 Dec 2019 09:00:02 +0000 (UTC) Date: Wed, 11 Dec 2019 10:00:00 +0100 From: Andrew Jones To: Guoheyi Cc: Peter Maydell , Marc Zyngier , qemu-arm , Richard Henderson , QEMU Developers , bijan.mottahedeh@oracle.com Subject: Re: [PATCH v1 0/5] target/arm/kvm: Provide an option to adjust virtual time Message-ID: <20191211090000.kajcyk7oqlqr3chk@kamzik.brq.redhat.com> References: <20191016143410.5023-1-drjones@redhat.com> <5679d43f-3f29-6ee1-0894-19ef2f3e08a2@huawei.com> MIME-Version: 1.0 In-Reply-To: <5679d43f-3f29-6ee1-0894-19ef2f3e08a2@huawei.com> X-Scanned-By: MIMEDefang 2.84 on 10.5.11.23 X-MC-Unique: RBmE-DGYPhCnVrDWe5RguQ-1 X-Mimecast-Spam-Score: 0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable Content-Disposition: inline X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 207.211.31.81 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 11 Dec 2019 09:00:14 -0000 On Wed, Dec 11, 2019 at 04:02:52PM +0800, Guoheyi wrote: >=20 > =E5=9C=A8 2019/12/6 23:22, Peter Maydell =E5=86=99=E9=81=93: > > On Wed, 16 Oct 2019 at 15:34, Andrew Jones wrote: > > > v2: > > > - move from RFC status to v1 > > > - put kvm_arm_vm_state_change() in kvm.c to share among kvm32.c and= kvm64.c > > > - add r-b's from Richard > > >=20 > > >=20 > > > This series is inspired by a series[1] posted by Bijan Mottahedeh abo= ut > > > a year ago. The problem described in the cover letter of [1] is easi= ly > > > reproducible and some users would like to have the option to avoid it= . > > > However the solution, which is to adjust the virtual counter offset e= ach > > > time the VM transitions to the running state, introduces a different > > > problem, which is that the virtual and physical counters diverge. As > > > described in the cover letter of [1] this divergence is easily observ= ed > > > when comparing the output of `date` and `hwclock` after suspending th= e > > > guest, waiting a while, and then resuming it. Because this different > > > problem may actually be worse for some users, unlike [1], the series > > > posted here makes the virtual counter offset adjustment optional and = not > > > even enabled by default. Besides the adjustment being optional, this > > > series approaches the needed changes differently to apply them in mor= e > > > appropriate locations. Finally, unlike [1], this series doesn't atte= mpt > > > to measure "pause time" itself. Simply using QEMU_CLOCK_VIRTUAL, whi= ch > > > only ticks when the VM is not stopped, is sufficient. > > So I guess my overall question is "what is the x86 solution to > > this problem, and why is this all arm-specific?" It would also > > be helpful to know how it fits into all the other proposals regarding > > time in VMs. >=20 > I also sent a RFC in March and ARM KVM experts were also invoved in the > discussion: >=20 > https://lists.cs.columbia.edu/pipermail/kvmarm/2019-March/035026.html >=20 > According to the discussion, qemu on x86 is using KVM_KVMCLOCK_CTRL to > request KVM to set a flag "PVCLOCK_GUEST_STOPPED" in pvclock, informing V= M > kernel about external force stop. >=20 > Thanks, >=20 > Heyi Hi Heyi, Apologies for having forgotten about that thread. I recall now having followed it last March. Indeed it even addresses the issue in the way we're coming around to now (save/restore vs. update with virtual time). I just reread the whole thread, and my feeling is that, while there are still many issues left to work, until we get a pvclock for arm, a patch like this one, but with a way to opt-in/out in order to give users a chance to choose their poison, is the best we can do. Also a patch like this one is a step in the right direction, as it will be needed as part of the bigger pvclock solution eventually, just as it is for x86. One comment on the patch is that I would prefer to do the save/restore for all VCPUs, even though KVM does currently handle synchronization. Not only does it "feel" more correct to apply VCPU APIs to all VCPUs, but I assume it will be less problematic to implement CPU hotplug at some point. Thanks, drew From MAILER-DAEMON Wed Dec 11 08:51:09 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1if2OT-0006H8-HZ for mharc-qemu-arm@gnu.org; Wed, 11 Dec 2019 08:51:09 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:56650) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1if2OP-0006Ak-8w for qemu-arm@nongnu.org; Wed, 11 Dec 2019 08:51:06 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1if2ON-0000Pw-HO for qemu-arm@nongnu.org; Wed, 11 Dec 2019 08:51:04 -0500 Received: from szxga04-in.huawei.com ([45.249.212.190]:2223 helo=huawei.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1if2ON-0000JN-3n; Wed, 11 Dec 2019 08:51:03 -0500 Received: from DGGEMS401-HUB.china.huawei.com (unknown [172.30.72.58]) by Forcepoint Email with ESMTP id 48958B31F41B410CF4E1; Wed, 11 Dec 2019 21:50:54 +0800 (CST) Received: from [127.0.0.1] (10.133.216.73) by DGGEMS401-HUB.china.huawei.com (10.3.19.201) with Microsoft SMTP Server id 14.3.439.0; Wed, 11 Dec 2019 21:50:44 +0800 Subject: Re: [PATCH v1 0/5] target/arm/kvm: Provide an option to adjust virtual time To: Andrew Jones CC: Peter Maydell , Marc Zyngier , qemu-arm , Richard Henderson , QEMU Developers , , wanghaibin 00208455 References: <20191016143410.5023-1-drjones@redhat.com> <5679d43f-3f29-6ee1-0894-19ef2f3e08a2@huawei.com> <20191211090000.kajcyk7oqlqr3chk@kamzik.brq.redhat.com> From: Guoheyi Message-ID: Date: Wed, 11 Dec 2019 21:50:42 +0800 User-Agent: Mozilla/5.0 (Windows NT 10.0; WOW64; rv:68.0) Gecko/20100101 Thunderbird/68.2.2 MIME-Version: 1.0 In-Reply-To: <20191211090000.kajcyk7oqlqr3chk@kamzik.brq.redhat.com> Content-Type: text/plain; charset="utf-8"; format=flowed X-Originating-IP: [10.133.216.73] X-CFilter-Loop: Reflected Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 45.249.212.190 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 11 Dec 2019 13:51:07 -0000 =E5=9C=A8 2019/12/11 17:00, Andrew Jones =E5=86=99=E9=81=93: > On Wed, Dec 11, 2019 at 04:02:52PM +0800, Guoheyi wrote: >> =E5=9C=A8 2019/12/6 23:22, Peter Maydell =E5=86=99=E9=81=93: >>> On Wed, 16 Oct 2019 at 15:34, Andrew Jones wrote= : >>>> v2: >>>> - move from RFC status to v1 >>>> - put kvm_arm_vm_state_change() in kvm.c to share among kvm32.c a= nd kvm64.c >>>> - add r-b's from Richard >>>> >>>> >>>> This series is inspired by a series[1] posted by Bijan Mottahedeh ab= out >>>> a year ago. The problem described in the cover letter of [1] is eas= ily >>>> reproducible and some users would like to have the option to avoid i= t. >>>> However the solution, which is to adjust the virtual counter offset = each >>>> time the VM transitions to the running state, introduces a different >>>> problem, which is that the virtual and physical counters diverge. A= s >>>> described in the cover letter of [1] this divergence is easily obser= ved >>>> when comparing the output of `date` and `hwclock` after suspending t= he >>>> guest, waiting a while, and then resuming it. Because this differen= t >>>> problem may actually be worse for some users, unlike [1], the series >>>> posted here makes the virtual counter offset adjustment optional and= not >>>> even enabled by default. Besides the adjustment being optional, thi= s >>>> series approaches the needed changes differently to apply them in mo= re >>>> appropriate locations. Finally, unlike [1], this series doesn't att= empt >>>> to measure "pause time" itself. Simply using QEMU_CLOCK_VIRTUAL, wh= ich >>>> only ticks when the VM is not stopped, is sufficient. >>> So I guess my overall question is "what is the x86 solution to >>> this problem, and why is this all arm-specific?" It would also >>> be helpful to know how it fits into all the other proposals regarding >>> time in VMs. >> I also sent a RFC in March and ARM KVM experts were also invoved in th= e >> discussion: >> >> https://lists.cs.columbia.edu/pipermail/kvmarm/2019-March/035026.html >> >> According to the discussion, qemu on x86 is using KVM_KVMCLOCK_CTRL to >> request KVM to set a flag "PVCLOCK_GUEST_STOPPED" in pvclock, informin= g VM >> kernel about external force stop. >> >> Thanks, >> >> Heyi > Hi Heyi, > > Apologies for having forgotten about that thread. I recall now having > followed it last March. Indeed it even addresses the issue in the way > we're coming around to now (save/restore vs. update with virtual time). Never mind :) We were also blocked by this issue when trying to support=20 VM suspend/resume, save/restore, etc, so I'm happy to see your patches=20 that we have the chance to fix it. > > I just reread the whole thread, and my feeling is that, while there are > still many issues left to work, until we get a pvclock for arm, a patch > like this one, but with a way to opt-in/out in order to give users a > chance to choose their poison, is the best we can do. Also a patch like > this one is a step in the right direction, as it will be needed as part > of the bigger pvclock solution eventually, just as it is for x86. Yes, it is simple and it works with current version of ARM64 OS=20 distributions. Thanks, Heyi > > One comment on the patch is that I would prefer to do the save/restore > for all VCPUs, even though KVM does currently handle synchronization. > Not only does it "feel" more correct to apply VCPU APIs to all VCPUs, > but I assume it will be less problematic to implement CPU hotplug at > some point. > > Thanks, > drew > > > . From MAILER-DAEMON Wed Dec 11 09:57:07 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1if3QJ-0004Jr-9d for mharc-qemu-arm@gnu.org; Wed, 11 Dec 2019 09:57:07 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:40841) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1if3QG-0004Jg-2H for qemu-arm@nongnu.org; Wed, 11 Dec 2019 09:57:05 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1if3QE-0008SP-CO for qemu-arm@nongnu.org; Wed, 11 Dec 2019 09:57:03 -0500 Received: from szxga01-in.huawei.com ([45.249.212.187]:2425 helo=huawei.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1if3QD-0008H3-Vj; Wed, 11 Dec 2019 09:57:02 -0500 Received: from DGGEMM401-HUB.china.huawei.com (unknown [172.30.72.57]) by Forcepoint Email with ESMTP id 43DB7CF27CCA2C6CCBDD; Wed, 11 Dec 2019 19:10:54 +0800 (CST) Received: from DGGEMM421-HUB.china.huawei.com (10.1.198.38) by DGGEMM401-HUB.china.huawei.com (10.3.20.209) with Microsoft SMTP Server (TLS) id 14.3.439.0; Wed, 11 Dec 2019 19:10:53 +0800 Received: from DGGEMM526-MBX.china.huawei.com ([169.254.8.101]) by dggemm421-hub.china.huawei.com ([10.1.198.38]) with mapi id 14.03.0439.000; Wed, 11 Dec 2019 19:10:45 +0800 From: "Zengtao (B)" To: Andrew Jones CC: "qemu-devel@nongnu.org" , "qemu-arm@nongnu.org" , "wei@redhat.com" , "peter.maydell@linaro.org" , "eric.auger@redhat.com" , "imammedo@redhat.com" , "xuwei (O)" , huangdaode Subject: RE: [Qemu-devel] [RFC PATCH 0/6] hw/arm/virt: Introduce cpu topology support Thread-Topic: [Qemu-devel] [RFC PATCH 0/6] hw/arm/virt: Introduce cpu topology support Thread-Index: AdQTlaRpUFkm+EncK0mrDnlTRz6dtGan2sPQADKVqIAARGvRgA== Date: Wed, 11 Dec 2019 11:10:45 +0000 Message-ID: <678F3D1BB717D949B966B68EAEB446ED34066A4F@dggemm526-mbx.china.huawei.com> References: <20180704124923.32483-1-drjones@redhat.com> <678F3D1BB717D949B966B68EAEB446ED3405A26F@dggemm526-mbx.china.huawei.com> <20191210101323.q7dn2f3pkx3ya5s4@kamzik.brq.redhat.com> In-Reply-To: <20191210101323.q7dn2f3pkx3ya5s4@kamzik.brq.redhat.com> Accept-Language: zh-CN, en-US Content-Language: zh-CN X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [10.74.221.187] Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-CFilter-Loop: Reflected X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 45.249.212.187 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 11 Dec 2019 14:57:05 -0000 Hi Andrew: Thanks for your reply. It 's fine for me if you are still tracking the thread. And I can help to t= est if needed ^_^. > -----Original Message----- > From: Andrew Jones [mailto:drjones@redhat.com] > Sent: Tuesday, December 10, 2019 6:13 PM > To: Zengtao (B) > Cc: qemu-devel@nongnu.org; qemu-arm@nongnu.org; wei@redhat.com; > peter.maydell@linaro.org; eric.auger@redhat.com; > imammedo@redhat.com; xuwei (O); huangdaode > Subject: Re: [Qemu-devel] [RFC PATCH 0/6] hw/arm/virt: Introduce cpu > topology support >=20 > On Mon, Dec 09, 2019 at 02:14:09AM +0000, Zengtao (B) wrote: > > Hi Andrew: > > > > Any update for this patch series? I have met the same issue, and if the > > topology guessed by linux MPIDR conflicts with qemu specified numa, it > > will failed to boot (sched domain initialization will fall into deadloo= p). >=20 > Hi Zeng, >=20 > This has been on my TODO list a long time, but it keeps getting preempted= . > We need to start by giving userspace control over the MPIDRs, including > when KVM is in use. The earliest I can return to this will be mid/late > January. If you'd like to jump in on it now, then feel free. >=20 > Thanks, > drew >=20 > > > > Thanks. > > > > > -----Original Message----- > > > From: Qemu-devel > > > > [mailto:qemu-devel-bounces+incoming=3Dpatchwork.ozlabs.org@nongnu.or > > > g] On Behalf Of Andrew Jones > > > Sent: Thursday, July 05, 2018 4:49 AM > > > To: qemu-devel@nongnu.org; qemu-arm@nongnu.org > > > Cc: wei@redhat.com; peter.maydell@linaro.org; > eric.auger@redhat.com; > > > imammedo@redhat.com > > > Subject: [Qemu-devel] [RFC PATCH 0/6] hw/arm/virt: Introduce cpu > > > topology support > > > > > > This series provides support for booting mach-virt machines with > > > non-flat cpu topology, i.e. enabling the extended options of the > > > '-smp' command line parameter (sockets,cores,threads). Both DT and > > > ACPI description generators are added. We only apply the new feature > > > to 3.1 and later machine types, as the change is guest visible, even > > > when no command line change is made. This is because the basic > > > '-smp ' parameter makes the assumption that refers to the > > > number of sockets, but when no topology description is provided, > > > Linux will use the MPIDR to guess. Neither the MPIDR exposed to > > > the guest when running with KVM nor TCG currently provides socket > > > information, leaving Linux to assume all processing elements are > > > cores in the same socket. For example, before this series '-smp 4' > > > would show up in the guest as > > > > > > CPU(s): 4 > > > On-line CPU(s) list: 0-3 > > > Thread(s) per core: 1 > > > Core(s) per socket: 4 > > > Socket(s): 1 > > > > > > and after it shows up as > > > > > > CPU(s): 4 > > > On-line CPU(s) list: 0-3 > > > Thread(s) per core: 1 > > > Core(s) per socket: 1 > > > Socket(s): 4 > > > > > > It's not expected that this should be a problem, but it's worth > > > considering. The only way to avoid the silent change is for QEMU to > > > provide boards a way to override the default '-smp' parsing function. > > > Otherwise, if a user wants to avoid a guest visible change, but still > > > use a 3.1 or later mach-virt machine type, then they must ensure the > > > command line specifies a single socket, e.g. '-smp sockets=3D1,cores= =3D4' > > > > > > Thanks, > > > drew > > > > > > > > > Andrew Jones (6): > > > hw/arm/virt: Add virt-3.1 machine type > > > device_tree: add qemu_fdt_add_path > > > hw/arm/virt: DT: add cpu-map > > > hw/arm/virt-acpi-build: distinguish possible and present cpus > > > virt-acpi-build: add PPTT table > > > hw/arm/virt: cpu topology: don't allow threads > > > > > > device_tree.c | 24 +++++++++++++ > > > hw/acpi/aml-build.c | 50 ++++++++++++++++++++++++++ > > > hw/arm/virt-acpi-build.c | 25 ++++++++++--- > > > hw/arm/virt.c | 69 > > > +++++++++++++++++++++++++++++++++--- > > > include/hw/acpi/aml-build.h | 2 ++ > > > include/hw/arm/virt.h | 1 + > > > include/sysemu/device_tree.h | 1 + > > > 7 files changed, 162 insertions(+), 10 deletions(-) From MAILER-DAEMON Wed Dec 11 09:58:18 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1if3RS-0005Jb-Mt for mharc-qemu-arm@gnu.org; Wed, 11 Dec 2019 09:58:18 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:48557) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1if3RP-0005JE-92 for qemu-arm@nongnu.org; Wed, 11 Dec 2019 09:58:17 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1if3RO-0001NC-AA for qemu-arm@nongnu.org; Wed, 11 Dec 2019 09:58:15 -0500 Received: from smtp-fw-4101.amazon.com ([72.21.198.25]:4022) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1if3RO-0001L7-3G; Wed, 11 Dec 2019 09:58:14 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amazon.de; i=@amazon.de; q=dns/txt; s=amazon201209; t=1576076294; x=1607612294; h=from:to:cc:subject:date:message-id; bh=Asgepvkz4JWY1boo1mZHZcuk6CbY2wol3JthUOrMfrc=; b=CK45ggbVoS9RhvKxrj2TftDhpII3QTWdj6dq3DyYrCjYySVm5nqzGUPi 83crgAwk0dvVVyE8NIKR6YnS6/gN/Qy4ngi7c4BOrugM3RxOnbqEJvjKJ VqMHZsiuqgCYKEYepLi7eE6vqk9KAnW/m4QE8B1wKNYgjwhNA3Ze/cyZM 8=; IronPort-SDR: V1DlAf1kmpv5BVH9Sv5ABk2JDoz0+W1WvkC4TXJo1RTRRkil1GcCiqsh1UGUq622yrq55sd4mW 307Bmn/QaL+w== X-IronPort-AV: E=Sophos;i="5.69,301,1571702400"; d="scan'208";a="8041226" Received: from iad6-co-svc-p1-lb1-vlan3.amazon.com (HELO email-inbound-relay-1e-c7c08562.us-east-1.amazon.com) ([10.124.125.6]) by smtp-border-fw-out-4101.iad4.amazon.com with ESMTP; 11 Dec 2019 14:58:12 +0000 Received: from sveith-desktop.aka.corp.amazon.com (iad7-ws-svc-lb50-vlan2.amazon.com [10.0.93.210]) by email-inbound-relay-1e-c7c08562.us-east-1.amazon.com (Postfix) with ESMTPS id 8AFCE241D29; Wed, 11 Dec 2019 14:58:10 +0000 (UTC) Received: from sveith-desktop.aka.corp.amazon.com (localhost [127.0.0.1]) by sveith-desktop.aka.corp.amazon.com (8.15.2/8.15.2/Debian-3) with ESMTP id xBBEw52u018996; Wed, 11 Dec 2019 15:58:06 +0100 Received: (from sveith@localhost) by sveith-desktop.aka.corp.amazon.com (8.15.2/8.15.2/Submit) id xBBEw4fi018992; Wed, 11 Dec 2019 15:58:04 +0100 From: Simon Veith To: qemu-devel@nongnu.org, qemu-arm@nongnu.org Cc: Simon Veith , Eric Auger Subject: [PATCH v2 0/6] hw/arm/smmuv3: Correct stream ID and event address handling Date: Wed, 11 Dec 2019 15:57:34 +0100 Message-Id: <1576076260-18659-1-git-send-email-sveith@amazon.de> X-Mailer: git-send-email 2.7.4 Precedence: Bulk X-detected-operating-system: by eggs.gnu.org: FreeBSD 9.x [fuzzy] X-Received-From: 72.21.198.25 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 11 Dec 2019 14:58:17 -0000 While working on the Linux SMMUv3 driver, I noticed a few cases where the QEMU SMMUv3 behavior relating to stream tables was inconsistent with our hardware. Also, when debugging those differences, I found that the errors reported through the QEMU SMMUv3 event queue contained the address fields in an incorrect position. These patches correct the QEMU SMMUv3 behavior to match the specification (and the behavior that I observed in our hardware). Linux guests normally will not notice these issues, but other SMMUv3 driver implementations might. Simon Veith (6): hw/arm/smmuv3: Apply address mask to linear strtab base address hw/arm/smmuv3: Correct SMMU_BASE_ADDR_MASK value hw/arm/smmuv3: Check stream IDs against actual table LOG2SIZE hw/arm/smmuv3: Align stream table base address to table size hw/arm/smmuv3: Use correct bit positions in EVT_SET_ADDR2 macro hw/arm/smmuv3: Report F_STE_FETCH fault address in correct word position hw/arm/smmuv3-internal.h | 6 +++--- hw/arm/smmuv3.c | 28 +++++++++++++++++++++------- 2 files changed, 24 insertions(+), 10 deletions(-) Cc: Eric Auger Cc: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org -- 2.7.4 From MAILER-DAEMON Wed Dec 11 09:58:28 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1if3Rc-0005W0-7u for mharc-qemu-arm@gnu.org; Wed, 11 Dec 2019 09:58:28 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:49734) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1if3RZ-0005T6-FZ for qemu-arm@nongnu.org; Wed, 11 Dec 2019 09:58:26 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1if3RY-0001Z2-DB for qemu-arm@nongnu.org; Wed, 11 Dec 2019 09:58:25 -0500 Received: from smtp-fw-6001.amazon.com ([52.95.48.154]:60967) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1if3RY-0001YO-8Y; Wed, 11 Dec 2019 09:58:24 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amazon.de; i=@amazon.de; q=dns/txt; s=amazon201209; t=1576076304; x=1607612304; h=from:to:cc:subject:date:message-id:in-reply-to: references; bh=syWV6RethZ9zkiIkM27Et4g5OSvaauBfpbT1hVu+9aY=; b=Ud4yWMct5kmOFiH3Ispu0ZWbHdQG1c1y0CMUt0VhOEv6j4646r/6AGGd rhdIFPZXO+xFBlO7LFjg3BRbpSD3TemKKNPVjTWLSn6UrVw68FUqQOf69 brMwslAkXa8jnCf+WLAUovHM4CEZe97lzSUpkymdPY2em2hFLA6waIRmv U=; IronPort-SDR: 5U4PCsk5faTlsL3Cto8jsoKGs1PL+7+mTrFEHbg7o+uX5q2rZ64rYnPXCTiHqUCp9Udm/yoNQu fzb7kbt/0GiA== X-IronPort-AV: E=Sophos;i="5.69,301,1571702400"; d="scan'208";a="8624211" Received: from iad6-co-svc-p1-lb1-vlan3.amazon.com (HELO email-inbound-relay-2b-5bdc5131.us-west-2.amazon.com) ([10.124.125.6]) by smtp-border-fw-out-6001.iad6.amazon.com with ESMTP; 11 Dec 2019 14:58:23 +0000 Received: from sveith-desktop.aka.corp.amazon.com (pdx2-ws-svc-lb17-vlan2.amazon.com [10.247.140.66]) by email-inbound-relay-2b-5bdc5131.us-west-2.amazon.com (Postfix) with ESMTPS id AC093A1C74; Wed, 11 Dec 2019 14:58:21 +0000 (UTC) Received: from sveith-desktop.aka.corp.amazon.com (localhost [127.0.0.1]) by sveith-desktop.aka.corp.amazon.com (8.15.2/8.15.2/Debian-3) with ESMTP id xBBEwITa019099; Wed, 11 Dec 2019 15:58:18 +0100 Received: (from sveith@localhost) by sveith-desktop.aka.corp.amazon.com (8.15.2/8.15.2/Submit) id xBBEwIVR019077; Wed, 11 Dec 2019 15:58:18 +0100 From: Simon Veith To: qemu-devel@nongnu.org, qemu-arm@nongnu.org Cc: Simon Veith , Eric Auger Subject: [PATCH v2 1/6] hw/arm/smmuv3: Apply address mask to linear strtab base address Date: Wed, 11 Dec 2019 15:57:35 +0100 Message-Id: <1576076260-18659-2-git-send-email-sveith@amazon.de> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1576076260-18659-1-git-send-email-sveith@amazon.de> References: <1576076260-18659-1-git-send-email-sveith@amazon.de> Precedence: Bulk X-detected-operating-system: by eggs.gnu.org: FreeBSD 9.x [fuzzy] X-Received-From: 52.95.48.154 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 11 Dec 2019 14:58:26 -0000 In the SMMU_STRTAB_BASE register, the stream table base address only occupies bits [51:6]. Other bits, such as RA (bit [62]), must be masked out to obtain the base address. The branch for 2-level stream tables correctly applies this mask by way of SMMU_BASE_ADDR_MASK, but the one for linear stream tables does not. Apply the missing mask in that case as well so that the correct stream base address is used by guests which configure a linear stream table. Linux guests are unaffected by this change because they choose a 2-level stream table layout for the QEMU SMMUv3, based on the size of its stream ID space. ref. ARM IHI 0070C, section 6.3.23. Signed-off-by: Simon Veith Cc: Eric Auger Cc: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Acked-by: Eric Auger --- hw/arm/smmuv3.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c index e2fbb83..eef9a18 100644 --- a/hw/arm/smmuv3.c +++ b/hw/arm/smmuv3.c @@ -429,7 +429,7 @@ static int smmu_find_ste(SMMUv3State *s, uint32_t sid, STE *ste, } addr = l2ptr + l2_ste_offset * sizeof(*ste); } else { - addr = s->strtab_base + sid * sizeof(*ste); + addr = (s->strtab_base & SMMU_BASE_ADDR_MASK) + sid * sizeof(*ste); } if (smmu_get_ste(s, addr, ste, event)) { -- 2.7.4 From MAILER-DAEMON Wed Dec 11 10:06:23 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1if3ZH-0000hW-8O for mharc-qemu-arm@gnu.org; Wed, 11 Dec 2019 10:06:23 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:45551) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1if3ZF-0000fi-9e for qemu-arm@nongnu.org; Wed, 11 Dec 2019 10:06:22 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1if3ZE-0001yF-8A for qemu-arm@nongnu.org; Wed, 11 Dec 2019 10:06:21 -0500 Received: from smtp-fw-2101.amazon.com ([72.21.196.25]:44717) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1if3ZE-0001vm-3L; Wed, 11 Dec 2019 10:06:20 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amazon.de; i=@amazon.de; q=dns/txt; s=amazon201209; t=1576076780; x=1607612780; h=from:to:cc:subject:date:message-id:in-reply-to: references; bh=mVMZNzfGgCZy2rnEt7SIpbodq72YKWuf3Om7HpAHf2g=; b=gTi1E7VRURq/8F+m3ObZxnpdUDHC2/IfhGJ5AoFwdjT0IPcAMfN/Egxr qO9XG7oNgAEC+4qkurtVIE9nptg8FwY/R5mpJKyMl+BffRoaQ+x+lXTxh EwCxXcfgfITGMmyKXK0i6tXN9+RcNVm2U3wNK42U59XEqLiqEYQyVDetl M=; IronPort-SDR: p7UU1YkJwIQ3WP4vdsajOaU54IkE1Csl31l9DnNCzg2gx+MXCq9C6N9DoLk3l3ixomBy+QJ6c8 61zJL+IGrd6w== X-IronPort-AV: E=Sophos;i="5.69,301,1571702400"; d="scan'208";a="8108820" Received: from iad6-co-svc-p1-lb1-vlan2.amazon.com (HELO email-inbound-relay-1d-474bcd9f.us-east-1.amazon.com) ([10.124.125.2]) by smtp-border-fw-out-2101.iad2.amazon.com with ESMTP; 11 Dec 2019 15:06:18 +0000 Received: from sveith-desktop.aka.corp.amazon.com (iad7-ws-svc-lb50-vlan2.amazon.com [10.0.93.210]) by email-inbound-relay-1d-474bcd9f.us-east-1.amazon.com (Postfix) with ESMTPS id 1FFECA25EA; Wed, 11 Dec 2019 15:06:15 +0000 (UTC) Received: from sveith-desktop.aka.corp.amazon.com (localhost [127.0.0.1]) by sveith-desktop.aka.corp.amazon.com (8.15.2/8.15.2/Debian-3) with ESMTP id xBBF6Ce7024283; Wed, 11 Dec 2019 16:06:12 +0100 Received: (from sveith@localhost) by sveith-desktop.aka.corp.amazon.com (8.15.2/8.15.2/Submit) id xBBF6B5B024260; Wed, 11 Dec 2019 16:06:11 +0100 From: Simon Veith To: qemu-devel@nongnu.org, qemu-arm@nongnu.org Cc: Simon Veith , Eric Auger Subject: [PATCH v2 2/6] hw/arm/smmuv3: Correct SMMU_BASE_ADDR_MASK value Date: Wed, 11 Dec 2019 16:05:39 +0100 Message-Id: <1576076739-23708-1-git-send-email-sveith@amazon.de> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1576076260-18659-1-git-send-email-sveith@amazon.de> References: <1576076260-18659-1-git-send-email-sveith@amazon.de> Precedence: Bulk X-detected-operating-system: by eggs.gnu.org: FreeBSD 9.x [fuzzy] X-Received-From: 72.21.196.25 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 11 Dec 2019 15:06:22 -0000 There are two issues with the current value of SMMU_BASE_ADDR_MASK: - At the lower end, we are clearing bits [4:0]. Per the SMMUv3 spec, we should also be treating bit 5 as zero in the base address. - At the upper end, we are clearing bits [63:48]. Per the SMMUv3 spec, only bits [63:52] must be explicitly treated as zero. Update the SMMU_BASE_ADDR_MASK value to mask out bits [63:52] and [5:0]. ref. ARM IHI 0070C, section 6.3.23. Signed-off-by: Simon Veith Cc: Eric Auger Cc: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org --- hw/arm/smmuv3-internal.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/arm/smmuv3-internal.h b/hw/arm/smmuv3-internal.h index d190181..042b435 100644 --- a/hw/arm/smmuv3-internal.h +++ b/hw/arm/smmuv3-internal.h @@ -99,7 +99,7 @@ REG32(GERROR_IRQ_CFG2, 0x74) #define A_STRTAB_BASE 0x80 /* 64b */ -#define SMMU_BASE_ADDR_MASK 0xffffffffffe0 +#define SMMU_BASE_ADDR_MASK 0xfffffffffffc0 REG32(STRTAB_BASE_CFG, 0x88) FIELD(STRTAB_BASE_CFG, FMT, 16, 2) -- 2.7.4 From MAILER-DAEMON Wed Dec 11 10:08:01 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1if3ar-0002QW-Mb for mharc-qemu-arm@gnu.org; Wed, 11 Dec 2019 10:08:01 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:56421) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1if3ap-0002Me-7c for qemu-arm@nongnu.org; Wed, 11 Dec 2019 10:08:00 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1if3ao-0003jR-3J for qemu-arm@nongnu.org; Wed, 11 Dec 2019 10:07:59 -0500 Received: from smtp-fw-6002.amazon.com ([52.95.49.90]:24828) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1if3an-0003ib-U2; Wed, 11 Dec 2019 10:07:58 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amazon.de; i=@amazon.de; q=dns/txt; s=amazon201209; t=1576076878; x=1607612878; h=from:to:cc:subject:date:message-id:in-reply-to: references; bh=PCOnbhJypslF5hM47QeKN1c0yopkDWzpKcTM5nMU8Xo=; b=CDj6Mvi7P+4CADYQe8O5TkJhkIB8rXEMrpGN4WoS1K30AUdk6i2jNV/B MmomEoFKZaxDq1GGgoVc/Zkp+HgklLUy4tXXtWxmwCLzw4hg7CTwVz6tm xdD0sVt5WrHdahXmJKVFUxo9uJWz2+JmrjLB6RDEbkLeVdL98JZgDzwhF k=; IronPort-SDR: RWEUtVZsJacMYHqOeRxJKTi797ERWhrNiSGCdx/M2KVQwTbSZ9t73TaIVRHZabWOqmst+kEHDB 3nLBTIXiDaEw== X-IronPort-AV: E=Sophos;i="5.69,301,1571702400"; d="scan'208";a="7181881" Received: from iad6-co-svc-p1-lb1-vlan3.amazon.com (HELO email-inbound-relay-2b-baacba05.us-west-2.amazon.com) ([10.124.125.6]) by smtp-border-fw-out-6002.iad6.amazon.com with ESMTP; 11 Dec 2019 15:07:55 +0000 Received: from sveith-desktop.aka.corp.amazon.com (pdx2-ws-svc-lb17-vlan3.amazon.com [10.247.140.70]) by email-inbound-relay-2b-baacba05.us-west-2.amazon.com (Postfix) with ESMTPS id B6585A1BEC; Wed, 11 Dec 2019 15:07:54 +0000 (UTC) Received: from sveith-desktop.aka.corp.amazon.com (localhost [127.0.0.1]) by sveith-desktop.aka.corp.amazon.com (8.15.2/8.15.2/Debian-3) with ESMTP id xBBF7p0s024939; Wed, 11 Dec 2019 16:07:51 +0100 Received: (from sveith@localhost) by sveith-desktop.aka.corp.amazon.com (8.15.2/8.15.2/Submit) id xBBF7olP024913; Wed, 11 Dec 2019 16:07:50 +0100 From: Simon Veith To: qemu-devel@nongnu.org, qemu-arm@nongnu.org Cc: Simon Veith , Eric Auger Subject: [PATCH v2 3/6] hw/arm/smmuv3: Check stream IDs against actual table LOG2SIZE Date: Wed, 11 Dec 2019 16:07:37 +0100 Message-Id: <1576076860-24820-1-git-send-email-sveith@amazon.de> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1576076260-18659-1-git-send-email-sveith@amazon.de> References: <1576076260-18659-1-git-send-email-sveith@amazon.de> Precedence: Bulk X-detected-operating-system: by eggs.gnu.org: FreeBSD 9.x [fuzzy] X-Received-From: 52.95.49.90 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 11 Dec 2019 15:08:00 -0000 When checking whether a stream ID is in range of the stream table, we have so far been only checking it against our implementation limit (SMMU_IDR1_SIDSIZE). However, the guest can program the STRTAB_BASE_CFG.LOG2SIZE field to a size that is smaller than this limit. Check the stream ID against this limit as well to match the hardware behavior of raising C_BAD_STREAMID events in case the limit is exceeded. Also, ensure that we do not go one entry beyond the end of the table by checking that its index is strictly smaller than the table size. ref. ARM IHI 0070C, section 6.3.24. Signed-off-by: Simon Veith Cc: Eric Auger Cc: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org --- Changed in v2: * Also check that stream ID is strictly lower than the table size hw/arm/smmuv3.c | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c index eef9a18..727558b 100644 --- a/hw/arm/smmuv3.c +++ b/hw/arm/smmuv3.c @@ -377,11 +377,15 @@ static int smmu_find_ste(SMMUv3State *s, uint32_t sid, STE *ste, SMMUEventInfo *event) { dma_addr_t addr; + uint32_t log2size; int ret; trace_smmuv3_find_ste(sid, s->features, s->sid_split); - /* Check SID range */ - if (sid > (1 << SMMU_IDR1_SIDSIZE)) { + log2size = FIELD_EX32(s->strtab_base_cfg, STRTAB_BASE_CFG, LOG2SIZE); + /* + * Check SID range against both guest-configured and implementation limits + */ + if (sid >= (1 << MIN(log2size, SMMU_IDR1_SIDSIZE))) { event->type = SMMU_EVT_C_BAD_STREAMID; return -EINVAL; } -- 2.7.4 From MAILER-DAEMON Wed Dec 11 10:08:19 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1if3b9-0002pH-Cz for mharc-qemu-arm@gnu.org; Wed, 11 Dec 2019 10:08:19 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:58757) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1if3b6-0002mF-IL for qemu-arm@nongnu.org; Wed, 11 Dec 2019 10:08:17 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1if3b5-00045W-GI for qemu-arm@nongnu.org; Wed, 11 Dec 2019 10:08:16 -0500 Received: from smtp-fw-6002.amazon.com ([52.95.49.90]:24873) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1if3b5-00045H-Be; Wed, 11 Dec 2019 10:08:15 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amazon.de; i=@amazon.de; q=dns/txt; s=amazon201209; t=1576076895; x=1607612895; h=from:to:cc:subject:date:message-id:in-reply-to: references; bh=Z0g33k0fJJlh3np7I7IZdcyVyzV2EJT6J7A5HaBP1Jc=; b=GdHRVN08qKk7sweLlV/KaT4C5BvIdBKBQYeORpNQ4hdyp8xIr/0cYvN5 oKNVE8JVB3qHzMoFIztrVHRjjD1Rx+3c6JNtTYLDSH/tLNpHHaiiDufeN X2YN6D6wWZNAg+5QAaIdTlEYOzU1Hng+7grYHuRIiL01jKxAky3dD6zfB I=; IronPort-SDR: R/ypnAI5Yu/GywgLzK+GEv4XppaOVffQUDD1PP1XQyiQwFAWoJsxZkQXlC5weWe7zYDBizOnOq aDoz2tDNHIFQ== X-IronPort-AV: E=Sophos;i="5.69,301,1571702400"; d="scan'208";a="7181932" Received: from iad6-co-svc-p1-lb1-vlan3.amazon.com (HELO email-inbound-relay-2b-a7fdc47a.us-west-2.amazon.com) ([10.124.125.6]) by smtp-border-fw-out-6002.iad6.amazon.com with ESMTP; 11 Dec 2019 15:08:14 +0000 Received: from sveith-desktop.aka.corp.amazon.com (pdx2-ws-svc-lb17-vlan3.amazon.com [10.247.140.70]) by email-inbound-relay-2b-a7fdc47a.us-west-2.amazon.com (Postfix) with ESMTPS id C7E40C5D3E; Wed, 11 Dec 2019 15:08:13 +0000 (UTC) Received: from sveith-desktop.aka.corp.amazon.com (localhost [127.0.0.1]) by sveith-desktop.aka.corp.amazon.com (8.15.2/8.15.2/Debian-3) with ESMTP id xBBF8A04025082; Wed, 11 Dec 2019 16:08:11 +0100 Received: (from sveith@localhost) by sveith-desktop.aka.corp.amazon.com (8.15.2/8.15.2/Submit) id xBBF8AFM025081; Wed, 11 Dec 2019 16:08:10 +0100 From: Simon Veith To: qemu-devel@nongnu.org, qemu-arm@nongnu.org Cc: Simon Veith , Eric Auger Subject: [PATCH v2 6/6] hw/arm/smmuv3: Report F_STE_FETCH fault address in correct word position Date: Wed, 11 Dec 2019 16:07:40 +0100 Message-Id: <1576076860-24820-4-git-send-email-sveith@amazon.de> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1576076860-24820-1-git-send-email-sveith@amazon.de> References: <1576076260-18659-1-git-send-email-sveith@amazon.de> <1576076860-24820-1-git-send-email-sveith@amazon.de> Precedence: Bulk X-detected-operating-system: by eggs.gnu.org: FreeBSD 9.x [fuzzy] X-Received-From: 52.95.49.90 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 11 Dec 2019 15:08:18 -0000 The smmuv3_record_event() function that generates the F_STE_FETCH error uses the EVT_SET_ADDR macro to record the fetch address, placing it in 32-bit words 4 and 5. The correct position for this address is in words 6 and 7, per the SMMUv3 Architecture Specification. Update the function to use the EVT_SET_ADDR2 macro instead, which is the macro intended for writing to these words. ref. ARM IHI 0070C, section 7.3.4. Signed-off-by: Simon Veith Cc: Eric Auger Cc: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Acked-by: Eric Auger --- hw/arm/smmuv3.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c index 31ac3ca..8b5f157 100644 --- a/hw/arm/smmuv3.c +++ b/hw/arm/smmuv3.c @@ -172,7 +172,7 @@ void smmuv3_record_event(SMMUv3State *s, SMMUEventInfo *info) case SMMU_EVT_F_STE_FETCH: EVT_SET_SSID(&evt, info->u.f_ste_fetch.ssid); EVT_SET_SSV(&evt, info->u.f_ste_fetch.ssv); - EVT_SET_ADDR(&evt, info->u.f_ste_fetch.addr); + EVT_SET_ADDR2(&evt, info->u.f_ste_fetch.addr); break; case SMMU_EVT_C_BAD_STE: EVT_SET_SSID(&evt, info->u.c_bad_ste.ssid); -- 2.7.4 From MAILER-DAEMON Wed Dec 11 10:08:34 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1if3bO-0003Cx-7j for mharc-qemu-arm@gnu.org; Wed, 11 Dec 2019 10:08:34 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:60631) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1if3bL-00036j-1I for qemu-arm@nongnu.org; Wed, 11 Dec 2019 10:08:32 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1if3bJ-0004N6-Pz for qemu-arm@nongnu.org; Wed, 11 Dec 2019 10:08:30 -0500 Received: from smtp-fw-9102.amazon.com ([207.171.184.29]:35431) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1if3bJ-0004Ly-Ih; Wed, 11 Dec 2019 10:08:29 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amazon.de; i=@amazon.de; q=dns/txt; s=amazon201209; t=1576076909; x=1607612909; h=from:to:cc:subject:date:message-id:in-reply-to: references; bh=tRSad7WoTFOponF+G6UnpmzO4ecidPjoO2ZvHdSbdBA=; b=ADdjV5nRf7ueNSkJrwFRwPbKPH7Y0xGYLQV/7IY2m/kldTBhPtvWMTTg OckHftdehF7aFAueqeUzRUsFo1H6nYgq0LBylKf9F6VNOaYcFE/3y1xUM CukiPkYuE9yfzHW3T4j/cBcRaqKFq/0FwVUnUs5/4QltWW/MuY4YHCg8+ 0=; IronPort-SDR: JcPP2yMluJHY+DoWPRrIJwSu9G0JvoEXHllVdbQlyJy8CIHQQM9QB4XEHl0ggDQomO3RXbXyh1 is0wASgBoSag== X-IronPort-AV: E=Sophos;i="5.69,301,1571702400"; d="scan'208";a="12924716" Received: from sea32-co-svc-lb4-vlan3.sea.corp.amazon.com (HELO email-inbound-relay-1a-821c648d.us-east-1.amazon.com) ([10.47.23.38]) by smtp-border-fw-out-9102.sea19.amazon.com with ESMTP; 11 Dec 2019 15:08:05 +0000 Received: from sveith-desktop.aka.corp.amazon.com (iad7-ws-svc-lb50-vlan3.amazon.com [10.0.93.214]) by email-inbound-relay-1a-821c648d.us-east-1.amazon.com (Postfix) with ESMTPS id B51A7A2362; Wed, 11 Dec 2019 15:08:03 +0000 (UTC) Received: from sveith-desktop.aka.corp.amazon.com (localhost [127.0.0.1]) by sveith-desktop.aka.corp.amazon.com (8.15.2/8.15.2/Debian-3) with ESMTP id xBBF80aL024989; Wed, 11 Dec 2019 16:08:00 +0100 Received: (from sveith@localhost) by sveith-desktop.aka.corp.amazon.com (8.15.2/8.15.2/Submit) id xBBF7xqR024987; Wed, 11 Dec 2019 16:07:59 +0100 From: Simon Veith To: qemu-devel@nongnu.org, qemu-arm@nongnu.org Cc: Simon Veith , Eric Auger Subject: [PATCH v2 4/6] hw/arm/smmuv3: Align stream table base address to table size Date: Wed, 11 Dec 2019 16:07:38 +0100 Message-Id: <1576076860-24820-2-git-send-email-sveith@amazon.de> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1576076860-24820-1-git-send-email-sveith@amazon.de> References: <1576076260-18659-1-git-send-email-sveith@amazon.de> <1576076860-24820-1-git-send-email-sveith@amazon.de> Precedence: Bulk X-detected-operating-system: by eggs.gnu.org: FreeBSD 9.x [fuzzy] X-Received-From: 207.171.184.29 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 11 Dec 2019 15:08:32 -0000 Per the specification, and as observed in hardware, the SMMUv3 aligns the SMMU_STRTAB_BASE address to the size of the table by masking out the respective least significant bits in the ADDR field. Apply this masking logic to our smmu_find_ste() lookup function per the specification. ref. ARM IHI 0070C, section 6.3.23. Signed-off-by: Simon Veith Cc: Eric Auger Cc: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org --- Changed in v2: * Now using MAKE_64BIT_MASK() * Eliminated unnecessary branches by using MAX() * Removed unnecessary range check against DMA_ADDR_BITS hw/arm/smmuv3.c | 18 ++++++++++++++---- 1 file changed, 14 insertions(+), 4 deletions(-) diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c index 727558b..31ac3ca 100644 --- a/hw/arm/smmuv3.c +++ b/hw/arm/smmuv3.c @@ -376,8 +376,9 @@ bad_ste: static int smmu_find_ste(SMMUv3State *s, uint32_t sid, STE *ste, SMMUEventInfo *event) { - dma_addr_t addr; + dma_addr_t addr, strtab_base; uint32_t log2size; + int strtab_size_shift; int ret; trace_smmuv3_find_ste(sid, s->features, s->sid_split); @@ -391,10 +392,16 @@ static int smmu_find_ste(SMMUv3State *s, uint32_t sid, STE *ste, } if (s->features & SMMU_FEATURE_2LVL_STE) { int l1_ste_offset, l2_ste_offset, max_l2_ste, span; - dma_addr_t strtab_base, l1ptr, l2ptr; + dma_addr_t l1ptr, l2ptr; STEDesc l1std; - strtab_base = s->strtab_base & SMMU_BASE_ADDR_MASK; + /* + * Align strtab base address to table size. For this purpose, assume it + * is not bounded by SMMU_IDR1_SIDSIZE. + */ + strtab_size_shift = MAX(5, (int)log2size - s->sid_split - 1 + 3); + strtab_base = s->strtab_base & SMMU_BASE_ADDR_MASK & + ~MAKE_64BIT_MASK(0, strtab_size_shift); l1_ste_offset = sid >> s->sid_split; l2_ste_offset = sid & ((1 << s->sid_split) - 1); l1ptr = (dma_addr_t)(strtab_base + l1_ste_offset * sizeof(l1std)); @@ -433,7 +440,10 @@ static int smmu_find_ste(SMMUv3State *s, uint32_t sid, STE *ste, } addr = l2ptr + l2_ste_offset * sizeof(*ste); } else { - addr = (s->strtab_base & SMMU_BASE_ADDR_MASK) + sid * sizeof(*ste); + strtab_size_shift = log2size + 5; + strtab_base = s->strtab_base & SMMU_BASE_ADDR_MASK & + ~MAKE_64BIT_MASK(0, strtab_size_shift); + addr = strtab_base + sid * sizeof(*ste); } if (smmu_get_ste(s, addr, ste, event)) { -- 2.7.4 From MAILER-DAEMON Wed Dec 11 10:08:37 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1if3bR-0003HN-EC for mharc-qemu-arm@gnu.org; Wed, 11 Dec 2019 10:08:37 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:32862) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1if3bO-0003Di-MY for qemu-arm@nongnu.org; Wed, 11 Dec 2019 10:08:35 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1if3bN-0004TY-H9 for qemu-arm@nongnu.org; Wed, 11 Dec 2019 10:08:34 -0500 Received: from smtp-fw-9101.amazon.com ([207.171.184.25]:56946) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1if3bN-0004QZ-90; Wed, 11 Dec 2019 10:08:33 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amazon.de; i=@amazon.de; q=dns/txt; s=amazon201209; t=1576076913; x=1607612913; h=from:to:cc:subject:date:message-id:in-reply-to: references; bh=WqDn93kShKzHI1eWGSSDUcj9wy6ytrLQeVu/AxoQ7gg=; b=Crrzdt8ZbW1AJO1G2HcNdbaPOIj1Yzh3QaxTRXbzZUmQIB6+M3GQArVx XT44q4iYp16rWQI8miBs/cGSxaVEqciaTEhGXne6Qp3MjWP44xPddsyDj Z4Irmj0cm20Ums251MtrlfQOWkbQvxPFcGjqwtrgqcmSYq4JqKLZdLlyC U=; IronPort-SDR: mOCpLXf60icE7BSEfGXJJ697iu//uRSEzthC8HlKYNWaoBpS6qdcpJkYriiQ7sqYj5lt8PMg6U zPqzFN+4GLIA== X-IronPort-AV: E=Sophos;i="5.69,301,1571702400"; d="scan'208";a="4517821" Received: from sea32-co-svc-lb4-vlan3.sea.corp.amazon.com (HELO email-inbound-relay-2a-53356bf6.us-west-2.amazon.com) ([10.47.23.38]) by smtp-border-fw-out-9101.sea19.amazon.com with ESMTP; 11 Dec 2019 15:08:10 +0000 Received: from sveith-desktop.aka.corp.amazon.com (pdx2-ws-svc-lb17-vlan3.amazon.com [10.247.140.70]) by email-inbound-relay-2a-53356bf6.us-west-2.amazon.com (Postfix) with ESMTPS id 1922EA265D; Wed, 11 Dec 2019 15:08:08 +0000 (UTC) Received: from sveith-desktop.aka.corp.amazon.com (localhost [127.0.0.1]) by sveith-desktop.aka.corp.amazon.com (8.15.2/8.15.2/Debian-3) with ESMTP id xBBF86aj025050; Wed, 11 Dec 2019 16:08:06 +0100 Received: (from sveith@localhost) by sveith-desktop.aka.corp.amazon.com (8.15.2/8.15.2/Submit) id xBBF85m7025048; Wed, 11 Dec 2019 16:08:05 +0100 From: Simon Veith To: qemu-devel@nongnu.org, qemu-arm@nongnu.org Cc: Simon Veith , Eric Auger Subject: [PATCH v2 5/6] hw/arm/smmuv3: Use correct bit positions in EVT_SET_ADDR2 macro Date: Wed, 11 Dec 2019 16:07:39 +0100 Message-Id: <1576076860-24820-3-git-send-email-sveith@amazon.de> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1576076860-24820-1-git-send-email-sveith@amazon.de> References: <1576076260-18659-1-git-send-email-sveith@amazon.de> <1576076860-24820-1-git-send-email-sveith@amazon.de> Precedence: Bulk X-detected-operating-system: by eggs.gnu.org: FreeBSD 9.x [fuzzy] X-Received-From: 207.171.184.25 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 11 Dec 2019 15:08:36 -0000 The bit offsets in the EVT_SET_ADDR2 macro do not match those specified in the ARM SMMUv3 Architecture Specification. In all events that use this macro, e.g. F_WALK_EABT, the faulting fetch address or IPA actually occupies the 32-bit words 6 and 7 in the event record contiguously, with the upper and lower unused bits clear due to alignment or maximum supported address bits. How many bits are clear depends on the individual event type. Update the macro to write to the correct words in the event record so that guest drivers can obtain accurate address information on events. ref. ARM IHI 0070C, sections 7.3.12 through 7.3.16. Signed-off-by: Simon Veith Cc: Eric Auger Cc: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Acked-by: Eric Auger --- hw/arm/smmuv3-internal.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/hw/arm/smmuv3-internal.h b/hw/arm/smmuv3-internal.h index 0910e7c..994481d 100644 --- a/hw/arm/smmuv3-internal.h +++ b/hw/arm/smmuv3-internal.h @@ -461,8 +461,8 @@ typedef struct SMMUEventInfo { } while (0) #define EVT_SET_ADDR2(x, addr) \ do { \ - (x)->word[7] = deposit32((x)->word[7], 3, 29, addr >> 16); \ - (x)->word[7] = deposit32((x)->word[7], 0, 16, addr & 0xffff);\ + (x)->word[7] = (uint32_t)(addr >> 32); \ + (x)->word[6] = (uint32_t)(addr & 0xffffffff); \ } while (0) void smmuv3_record_event(SMMUv3State *s, SMMUEventInfo *event); -- 2.7.4 From MAILER-DAEMON Wed Dec 11 11:40:31 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1if52N-0001xh-Di for mharc-qemu-arm@gnu.org; Wed, 11 Dec 2019 11:40:31 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:56599) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1if52J-0001w6-Pb for qemu-arm@nongnu.org; Wed, 11 Dec 2019 11:40:29 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1if52H-0006Ki-Av for qemu-arm@nongnu.org; Wed, 11 Dec 2019 11:40:27 -0500 Received: from us-smtp-delivery-1.mimecast.com ([205.139.110.120]:42708 helo=us-smtp-1.mimecast.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1if52G-0006IO-Qz for qemu-arm@nongnu.org; Wed, 11 Dec 2019 11:40:25 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1576082423; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=cotwrvhrBLlOX+u6bkNYkuynFuQ2DSYOMG3pJLCJaeQ=; b=NrjXAVFdfkKBVtB8MOie4tKi2c6EHHg3caEtdQsI2X+DBg88TT9pNdOUYwIc1EOgR2i+l7 RHxZ02XmsGgYszKPwhc4/TkPZbBPr7Z+HMzkHHzlfGh0Ods6xO2JwaY5CRtul9u5zjKnb3 NYx1l6lns+18UxhR51gfhpqSMWwPrLg= Received: from mail-qv1-f69.google.com (mail-qv1-f69.google.com [209.85.219.69]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-224-xYgJpAHXMGOZ_ix0kq6W1Q-1; Wed, 11 Dec 2019 11:40:20 -0500 Received: by mail-qv1-f69.google.com with SMTP id r9so9258531qvs.19 for ; Wed, 11 Dec 2019 08:40:20 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:in-reply-to; bh=g0cOjXW4SkTBCf9OMHaW1IzT+97O5aKVzdaDN2Z44yk=; b=MRPXFpQ1fmGHQhMjFCMSUJF7VPW9ZqmuL+sL4EYDVSPmumXRjoWF8YAj3ctHG3l1Pt VyE7a/VKrR7iABqxvIDqH5p014eJdCr2oXU3MBq3TljKfG+rvqB/7gZkFGqcoVstJYA3 huPkYIKlroJj15PaQLLB5cD5s7ffru+fl+Omrhw+RybvKZZjUDYEr/NyXhBwQzxJN6yl EQUKeCYql8QGZp29RnhtMs4fskB4h8mKjCDknGSW2ZFl08n7WQLi7YIXGWIYs7VVhbIz hMbfvKtmxnszGUmSPMp8FMyN7kR3K3DU/lge9Fn+1ffCbSQkuwasfo4k86S1fKgv1xeh JR/g== X-Gm-Message-State: APjAAAVIjoASPeOeQ+pymCIq7GAAlWc4Z/TSPOl6UANPq6ceDxS39IOj AGwXw85/5kr2/ghZq/GrvGVRBz8D+jIjxuZYT6bzwEm36bhpq1PONp58iZDCC8FpVCm+HyG7As6 hflSsuhcO2eK0 X-Received: by 2002:ac8:27ae:: with SMTP id w43mr3545690qtw.273.1576082419733; Wed, 11 Dec 2019 08:40:19 -0800 (PST) X-Google-Smtp-Source: APXvYqy1vKJQyZfu2GHV0E+PAw8rPcBNi3e7u9c0nxV8ZjTZ7LVVo1qckCfqaaHBEEl2Qm520/4LIA== X-Received: by 2002:ac8:27ae:: with SMTP id w43mr3545663qtw.273.1576082419420; Wed, 11 Dec 2019 08:40:19 -0800 (PST) Received: from redhat.com (bzq-79-181-48-215.red.bezeqint.net. [79.181.48.215]) by smtp.gmail.com with ESMTPSA id d25sm1028760qtn.49.2019.12.11.08.40.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 11 Dec 2019 08:40:18 -0800 (PST) Date: Wed, 11 Dec 2019 11:40:12 -0500 From: "Michael S. Tsirkin" To: Eric Auger Cc: eric.auger.pro@gmail.com, qemu-devel@nongnu.org, qemu-arm@nongnu.org, peter.maydell@linaro.org, armbru@redhat.com, jean-philippe.brucker@arm.com, bharatb.linux@gmail.com, yang.zhong@intel.com, dgilbert@redhat.com, quintela@redhat.com, kevin.tian@intel.com, tnowicki@marvell.com, peterx@redhat.com Subject: Re: [PATCH for-5.0 v11 00/20] VIRTIO-IOMMU device Message-ID: <20191211113936-mutt-send-email-mst@kernel.org> References: <20191122182943.4656-1-eric.auger@redhat.com> MIME-Version: 1.0 In-Reply-To: <20191122182943.4656-1-eric.auger@redhat.com> X-MC-Unique: xYgJpAHXMGOZ_ix0kq6W1Q-1 X-Mimecast-Spam-Score: 0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: quoted-printable Content-Disposition: inline X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 205.139.110.120 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 11 Dec 2019 16:40:29 -0000 On Fri, Nov 22, 2019 at 07:29:23PM +0100, Eric Auger wrote: > This series implements the QEMU virtio-iommu device. >=20 > This matches the v0.12 spec and the corresponding virtio-iommu > driver upstreamed in 5.3. >=20 > The pci proxy for the virtio-iommu device is instantiated using > "-device virtio-iommu-pci". This series still relies on ACPI IORT/DT > integration. Note the ACPI IORT integration is not yet upstreamed > and testing needs to be based on Jean-Philippe's additional > kernel patches [1]. Or the config space approach? I really liked that one. >=20 > Work is ongoing to remove IORT adherence and allow the > bindings between the IOMMU and the root complex to be defined > and written into the PCI device configuration space. The outcome > of this work is uncertain at this stage though. See [2]. >=20 > So only patches 1-11 fully rely on upstreamed kernel code. Others > should be considered as RFC. >=20 > This respin allows people to test on ARM and x86. It also > brings migration support (tested on ARM) and various cleanups. > Reserved regions are now passed through an array of properties. > A libqos test also is introduced to test the virtio-iommu API. >=20 > Note integration with vhost devices and vfio devices is not part > of this series. Please follow Bharat's respins [3]. >=20 > The 1st Patch ("migration: Support QLIST migration") was sent > separately [4]. >=20 > Best Regards >=20 > Eric >=20 > This series can be found at: > https://github.com/eauger/qemu/tree/v4.2-rc2-virtio-iommu-v11 >=20 > [1] kernel branch to be used for guest > https://github.com/eauger/linux/tree/v5.4-rc8-virtio-iommu-iort > [2] [RFC 00/13] virtio-iommu on non-devicetree platforms > [3] VFIO/VHOST integration is not part of this series. Please follow > [PATCH RFC v5 0/5] virtio-iommu: VFIO integration respins > [4] [PATCH v6] migration: Support QLIST migration >=20 > Testing: > - tested with guest using virtio-net-pci > (,vhost=3Doff,iommu_platform,disable-modern=3Doff,disable-legacy=3Don) > and virtio-blk-pci > - migration on ARM > - on x86 PC machine I get some AHCI non translated transactions, > very early. This does not prevent the guest from boot and behaving > properly. Warnings look like: > qemu-system-x86_64: virtio_iommu_translate sid=3D250 is not known!! > qemu-system-x86_64: no buffer available in event queue to report event > qemu-system-x86_64: AHCI: Failed to start FIS receive engine: bad FIS > receive buffer address >=20 > History: >=20 > v10 -> v11: > - introduce virtio_iommu_handle_req macro > - migration support > - introduce DEFINE_PROP_INTERVAL and pass reserved regions > through an array of those > - domain gtree simplification >=20 > v9 -> v10: > - rebase on 4.1.0-rc2, compliance with 0.12 spec > - removed ACPI part > - cleanup (see individual change logs) > - moved to a PATCH series >=20 > v8 -> v9: > - virtio-iommu-pci device needs to be instantiated from the command > line (RID is not imposed anymore). > - tail structure properly initialized >=20 > v7 -> v8: > - virtio-iommu-pci added > - virt instantiation modified > - DT and ACPI modified to exclude the iommu RID from the mapping > - VIRTIO_IOMMU_F_BYPASS, VIRTIO_F_VERSION_1 features exposed >=20 > v6 -> v7: > - rebase on qemu 3.0.0-rc3 > - minor update against v0.7 > - fix issue with EP not on pci.0 and ACPI probing > - change the instantiation method >=20 > v5 -> v6: > - minor update against v0.6 spec > - fix g_hash_table_lookup in virtio_iommu_find_add_as > - replace some error_reports by qemu_log_mask(LOG_GUEST_ERROR, ...) >=20 > v4 -> v5: > - event queue and fault reporting > - we now return the IOAPIC MSI region if the virtio-iommu is instantiated > in a PC machine. > - we bypass transactions on MSI HW region and fault on reserved ones. > - We support ACPI boot with mach-virt (based on IORT proposal) > - We moved to the new driver naming conventions > - simplified mach-virt instantiation > - worked around the disappearing of pci_find_primary_bus > - in virtio_iommu_translate, check the dev->as is not NULL > - initialize as->device_list in virtio_iommu_get_as > - initialize bufstate.error to false in virtio_iommu_probe >=20 > v3 -> v4: > - probe request support although no reserved region is returned at > the moment > - unmap semantics less strict, as specified in v0.4 > - device registration, attach/detach revisited > - split into smaller patches to ease review > - propose a way to inform the IOMMU mr about the page_size_mask > of underlying HW IOMMU, if any > - remove warning associated with the translation of the MSI doorbell >=20 > v2 -> v3: > - rebase on top of 2.10-rc0 and especially > [PATCH qemu v9 0/2] memory/iommu: QOM'fy IOMMU MemoryRegion > - add mutex init > - fix as->mappings deletion using g_tree_ref/unref > - when a dev is attached whereas it is already attached to > another address space, first detach it > - fix some error values > - page_sizes =3D TARGET_PAGE_MASK; > - I haven't changed the unmap() semantics yet, waiting for the > next virtio-iommu spec revision. >=20 > v1 -> v2: > - fix redefinition of viommu_as typedef >=20 >=20 >=20 > Eric Auger (20): > migration: Support QLIST migration > virtio-iommu: Add skeleton > virtio-iommu: Decode the command payload > virtio-iommu: Add the iommu regions > virtio-iommu: Endpoint and domains structs and helpers > virtio-iommu: Implement attach/detach command > virtio-iommu: Implement map/unmap > virtio-iommu: Implement translate > virtio-iommu: Implement fault reporting > virtio-iommu-pci: Add virtio iommu pci support > hw/arm/virt: Add the virtio-iommu device tree mappings > qapi: Introduce DEFINE_PROP_INTERVAL > virtio-iommu: Implement probe request > virtio-iommu: Handle reserved regions in the translation process > virtio-iommu-pci: Add array of Interval properties > hw/arm/virt-acpi-build: Introduce fill_iort_idmap helper > hw/arm/virt-acpi-build: Add virtio-iommu node in IORT table > virtio-iommu: Support migration > pc: Add support for virtio-iommu-pci > tests: Add virtio-iommu test >=20 > hw/arm/virt-acpi-build.c | 91 ++- > hw/arm/virt.c | 53 +- > hw/core/qdev-properties.c | 90 +++ > hw/i386/acpi-build.c | 72 +++ > hw/i386/pc.c | 15 +- > hw/virtio/Kconfig | 5 + > hw/virtio/Makefile.objs | 2 + > hw/virtio/trace-events | 22 + > hw/virtio/virtio-iommu-pci.c | 91 +++ > hw/virtio/virtio-iommu.c | 952 +++++++++++++++++++++++++++++++ > include/exec/memory.h | 6 + > include/hw/acpi/acpi-defs.h | 21 +- > include/hw/arm/virt.h | 2 + > include/hw/i386/pc.h | 2 + > include/hw/pci/pci.h | 1 + > include/hw/qdev-properties.h | 3 + > include/hw/virtio/virtio-iommu.h | 67 +++ > include/migration/vmstate.h | 21 + > include/qemu/queue.h | 39 ++ > include/qemu/typedefs.h | 1 + > migration/trace-events | 5 + > migration/vmstate-types.c | 70 +++ > qdev-monitor.c | 1 + > tests/Makefile.include | 2 + > tests/libqos/virtio-iommu.c | 177 ++++++ > tests/libqos/virtio-iommu.h | 45 ++ > tests/test-vmstate.c | 170 ++++++ > tests/virtio-iommu-test.c | 261 +++++++++ > 28 files changed, 2253 insertions(+), 34 deletions(-) > create mode 100644 hw/virtio/virtio-iommu-pci.c > create mode 100644 hw/virtio/virtio-iommu.c > create mode 100644 include/hw/virtio/virtio-iommu.h > create mode 100644 tests/libqos/virtio-iommu.c > create mode 100644 tests/libqos/virtio-iommu.h > create mode 100644 tests/virtio-iommu-test.c >=20 > --=20 > 2.20.1 From MAILER-DAEMON Wed Dec 11 11:48:32 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1if5A8-0004Rb-FG for mharc-qemu-arm@gnu.org; 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bh=sG46IMvcj0yp0B5v1TxDs/8TYH5cRlwJHyrr9ml9234=; b=cueYOKsfbqZ9YHXbeWloBMGeDHel/iQeluFYl5isegXK9lP2PhjyAb+lIINwdcZ4EVLQ0x gXMxTGjxVkzHK40J17P5USFa/79Bu/Wm/tkGzi3EM5Z7golq+zz49FVdr4Jq5/PzAmBGah 7jc8oHEol3Uue0u+5dLrbUW3Hic1xv0= Received: from mimecast-mx01.redhat.com (mimecast-mx01.redhat.com [209.132.183.4]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-279-40gwlicCPmyLhWb8J6nfKA-1; Wed, 11 Dec 2019 11:48:18 -0500 Received: from smtp.corp.redhat.com (int-mx05.intmail.prod.int.phx2.redhat.com [10.5.11.15]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx01.redhat.com (Postfix) with ESMTPS id 3EDB38026A2; Wed, 11 Dec 2019 16:48:16 +0000 (UTC) Received: from [10.36.116.117] (ovpn-116-117.ams2.redhat.com [10.36.116.117]) by smtp.corp.redhat.com (Postfix) with ESMTPS id 182675D6A3; Wed, 11 Dec 2019 16:48:07 +0000 (UTC) Subject: Re: [PATCH for-5.0 v11 00/20] VIRTIO-IOMMU device To: "Michael S. Tsirkin" Cc: yang.zhong@intel.com, peter.maydell@linaro.org, kevin.tian@intel.com, tnowicki@marvell.com, quintela@redhat.com, jean-philippe.brucker@arm.com, qemu-devel@nongnu.org, peterx@redhat.com, armbru@redhat.com, bharatb.linux@gmail.com, qemu-arm@nongnu.org, dgilbert@redhat.com, eric.auger.pro@gmail.com References: <20191122182943.4656-1-eric.auger@redhat.com> <20191211113936-mutt-send-email-mst@kernel.org> From: Auger Eric Message-ID: <306e4e92-4e86-7a82-3777-fd85ffd0303c@redhat.com> Date: Wed, 11 Dec 2019 17:48:05 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101 Thunderbird/60.4.0 MIME-Version: 1.0 In-Reply-To: <20191211113936-mutt-send-email-mst@kernel.org> Content-Language: en-US X-Scanned-By: MIMEDefang 2.79 on 10.5.11.15 X-MC-Unique: 40gwlicCPmyLhWb8J6nfKA-1 X-Mimecast-Spam-Score: 0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: 7bit X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 207.211.31.120 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 11 Dec 2019 16:48:31 -0000 Hi Michael, On 12/11/19 5:40 PM, Michael S. Tsirkin wrote: > On Fri, Nov 22, 2019 at 07:29:23PM +0100, Eric Auger wrote: >> This series implements the QEMU virtio-iommu device. >> >> This matches the v0.12 spec and the corresponding virtio-iommu >> driver upstreamed in 5.3. >> >> The pci proxy for the virtio-iommu device is instantiated using >> "-device virtio-iommu-pci". This series still relies on ACPI IORT/DT >> integration. Note the ACPI IORT integration is not yet upstreamed >> and testing needs to be based on Jean-Philippe's additional >> kernel patches [1]. > > Or the config space approach? I really liked that one. Yes this corresponds to the paragraph below. > >> >> Work is ongoing to remove IORT adherence and allow the >> bindings between the IOMMU and the root complex to be defined >> and written into the PCI device configuration space. The outcome >> of this work is uncertain at this stage though. See [2]. Thanks Eric >> >> So only patches 1-11 fully rely on upstreamed kernel code. Others >> should be considered as RFC. >> >> This respin allows people to test on ARM and x86. It also >> brings migration support (tested on ARM) and various cleanups. >> Reserved regions are now passed through an array of properties. >> A libqos test also is introduced to test the virtio-iommu API. >> >> Note integration with vhost devices and vfio devices is not part >> of this series. Please follow Bharat's respins [3]. >> >> The 1st Patch ("migration: Support QLIST migration") was sent >> separately [4]. >> >> Best Regards >> >> Eric >> >> This series can be found at: >> https://github.com/eauger/qemu/tree/v4.2-rc2-virtio-iommu-v11 >> >> [1] kernel branch to be used for guest >> https://github.com/eauger/linux/tree/v5.4-rc8-virtio-iommu-iort >> [2] [RFC 00/13] virtio-iommu on non-devicetree platforms >> [3] VFIO/VHOST integration is not part of this series. Please follow >> [PATCH RFC v5 0/5] virtio-iommu: VFIO integration respins >> [4] [PATCH v6] migration: Support QLIST migration >> >> Testing: >> - tested with guest using virtio-net-pci >> (,vhost=off,iommu_platform,disable-modern=off,disable-legacy=on) >> and virtio-blk-pci >> - migration on ARM >> - on x86 PC machine I get some AHCI non translated transactions, >> very early. This does not prevent the guest from boot and behaving >> properly. Warnings look like: >> qemu-system-x86_64: virtio_iommu_translate sid=250 is not known!! >> qemu-system-x86_64: no buffer available in event queue to report event >> qemu-system-x86_64: AHCI: Failed to start FIS receive engine: bad FIS >> receive buffer address >> >> History: >> >> v10 -> v11: >> - introduce virtio_iommu_handle_req macro >> - migration support >> - introduce DEFINE_PROP_INTERVAL and pass reserved regions >> through an array of those >> - domain gtree simplification >> >> v9 -> v10: >> - rebase on 4.1.0-rc2, compliance with 0.12 spec >> - removed ACPI part >> - cleanup (see individual change logs) >> - moved to a PATCH series >> >> v8 -> v9: >> - virtio-iommu-pci device needs to be instantiated from the command >> line (RID is not imposed anymore). >> - tail structure properly initialized >> >> v7 -> v8: >> - virtio-iommu-pci added >> - virt instantiation modified >> - DT and ACPI modified to exclude the iommu RID from the mapping >> - VIRTIO_IOMMU_F_BYPASS, VIRTIO_F_VERSION_1 features exposed >> >> v6 -> v7: >> - rebase on qemu 3.0.0-rc3 >> - minor update against v0.7 >> - fix issue with EP not on pci.0 and ACPI probing >> - change the instantiation method >> >> v5 -> v6: >> - minor update against v0.6 spec >> - fix g_hash_table_lookup in virtio_iommu_find_add_as >> - replace some error_reports by qemu_log_mask(LOG_GUEST_ERROR, ...) >> >> v4 -> v5: >> - event queue and fault reporting >> - we now return the IOAPIC MSI region if the virtio-iommu is instantiated >> in a PC machine. >> - we bypass transactions on MSI HW region and fault on reserved ones. >> - We support ACPI boot with mach-virt (based on IORT proposal) >> - We moved to the new driver naming conventions >> - simplified mach-virt instantiation >> - worked around the disappearing of pci_find_primary_bus >> - in virtio_iommu_translate, check the dev->as is not NULL >> - initialize as->device_list in virtio_iommu_get_as >> - initialize bufstate.error to false in virtio_iommu_probe >> >> v3 -> v4: >> - probe request support although no reserved region is returned at >> the moment >> - unmap semantics less strict, as specified in v0.4 >> - device registration, attach/detach revisited >> - split into smaller patches to ease review >> - propose a way to inform the IOMMU mr about the page_size_mask >> of underlying HW IOMMU, if any >> - remove warning associated with the translation of the MSI doorbell >> >> v2 -> v3: >> - rebase on top of 2.10-rc0 and especially >> [PATCH qemu v9 0/2] memory/iommu: QOM'fy IOMMU MemoryRegion >> - add mutex init >> - fix as->mappings deletion using g_tree_ref/unref >> - when a dev is attached whereas it is already attached to >> another address space, first detach it >> - fix some error values >> - page_sizes = TARGET_PAGE_MASK; >> - I haven't changed the unmap() semantics yet, waiting for the >> next virtio-iommu spec revision. >> >> v1 -> v2: >> - fix redefinition of viommu_as typedef >> >> >> >> Eric Auger (20): >> migration: Support QLIST migration >> virtio-iommu: Add skeleton >> virtio-iommu: Decode the command payload >> virtio-iommu: Add the iommu regions >> virtio-iommu: Endpoint and domains structs and helpers >> virtio-iommu: Implement attach/detach command >> virtio-iommu: Implement map/unmap >> virtio-iommu: Implement translate >> virtio-iommu: Implement fault reporting >> virtio-iommu-pci: Add virtio iommu pci support >> hw/arm/virt: Add the virtio-iommu device tree mappings >> qapi: Introduce DEFINE_PROP_INTERVAL >> virtio-iommu: Implement probe request >> virtio-iommu: Handle reserved regions in the translation process >> virtio-iommu-pci: Add array of Interval properties >> hw/arm/virt-acpi-build: Introduce fill_iort_idmap helper >> hw/arm/virt-acpi-build: Add virtio-iommu node in IORT table >> virtio-iommu: Support migration >> pc: Add support for virtio-iommu-pci >> tests: Add virtio-iommu test >> >> hw/arm/virt-acpi-build.c | 91 ++- >> hw/arm/virt.c | 53 +- >> hw/core/qdev-properties.c | 90 +++ >> hw/i386/acpi-build.c | 72 +++ >> hw/i386/pc.c | 15 +- >> hw/virtio/Kconfig | 5 + >> hw/virtio/Makefile.objs | 2 + >> hw/virtio/trace-events | 22 + >> hw/virtio/virtio-iommu-pci.c | 91 +++ >> hw/virtio/virtio-iommu.c | 952 +++++++++++++++++++++++++++++++ >> include/exec/memory.h | 6 + >> include/hw/acpi/acpi-defs.h | 21 +- >> include/hw/arm/virt.h | 2 + >> include/hw/i386/pc.h | 2 + >> include/hw/pci/pci.h | 1 + >> include/hw/qdev-properties.h | 3 + >> include/hw/virtio/virtio-iommu.h | 67 +++ >> include/migration/vmstate.h | 21 + >> include/qemu/queue.h | 39 ++ >> include/qemu/typedefs.h | 1 + >> migration/trace-events | 5 + >> migration/vmstate-types.c | 70 +++ >> qdev-monitor.c | 1 + >> tests/Makefile.include | 2 + >> tests/libqos/virtio-iommu.c | 177 ++++++ >> tests/libqos/virtio-iommu.h | 45 ++ >> tests/test-vmstate.c | 170 ++++++ >> tests/virtio-iommu-test.c | 261 +++++++++ >> 28 files changed, 2253 insertions(+), 34 deletions(-) >> create mode 100644 hw/virtio/virtio-iommu-pci.c >> create mode 100644 hw/virtio/virtio-iommu.c >> create mode 100644 include/hw/virtio/virtio-iommu.h >> create mode 100644 tests/libqos/virtio-iommu.c >> create mode 100644 tests/libqos/virtio-iommu.h >> create mode 100644 tests/virtio-iommu-test.c >> >> -- >> 2.20.1 > > From MAILER-DAEMON Wed Dec 11 12:05:35 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1if5Qc-00056W-VX for mharc-qemu-arm@gnu.org; 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Wed, 11 Dec 2019 09:05:24 -0800 (PST) Received: from zen.lan (localhost [127.0.0.1]) by zen.linaroharston (Postfix) with ESMTP id F3F2C1FF93; Wed, 11 Dec 2019 17:05:21 +0000 (GMT) From: =?UTF-8?q?Alex=20Benn=C3=A9e?= To: qemu-devel@nongnu.org Cc: richard.henderson@linaro.org, alan.hayward@arm.com, luis.machado@linaro.org, damien.hedde@greensocs.com, =?UTF-8?q?Alex=20Benn=C3=A9e?= , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Peter Maydell , qemu-arm@nongnu.org (open list:ARM TCG CPUs) Subject: [PATCH v3 06/20] target/arm: use gdb_get_reg helpers Date: Wed, 11 Dec 2019 17:05:06 +0000 Message-Id: <20191211170520.7747-7-alex.bennee@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20191211170520.7747-1-alex.bennee@linaro.org> References: <20191211170520.7747-1-alex.bennee@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::444 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 11 Dec 2019 17:05:33 -0000 This is cleaner than poking memory directly and will make later clean-ups easier. Signed-off-by: Alex Bennée Reviewed-by: Philippe Mathieu-Daudé --- v2 - make sure we pass hi/lo correctly as quads are stored in LE order --- target/arm/helper.c | 18 +++++++----------- 1 file changed, 7 insertions(+), 11 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 0bf8f53d4b8..0ac950d6c71 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -105,21 +105,17 @@ static int aarch64_fpu_gdb_get_reg(CPUARMState *env, uint8_t *buf, int reg) { switch (reg) { case 0 ... 31: - /* 128 bit FP register */ - { - uint64_t *q = aa64_vfp_qreg(env, reg); - stq_le_p(buf, q[0]); - stq_le_p(buf + 8, q[1]); - return 16; - } + { + /* 128 bit FP register - quads are in LE order */ + uint64_t *q = aa64_vfp_qreg(env, reg); + return gdb_get_reg128(buf, q[1], q[0]); + } case 32: /* FPSR */ - stl_p(buf, vfp_get_fpsr(env)); - return 4; + return gdb_get_reg32(buf, vfp_get_fpsr(env)); case 33: /* FPCR */ - stl_p(buf, vfp_get_fpcr(env)); - return 4; + return gdb_get_reg32(buf,vfp_get_fpcr(env)); default: return 0; } -- 2.20.1 From MAILER-DAEMON Wed Dec 11 12:05:43 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1if5Ql-0005Ho-Gu for mharc-qemu-arm@gnu.org; Wed, 11 Dec 2019 12:05:43 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:39469) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1if5Qf-0005BR-Q1 for qemu-arm@nongnu.org; Wed, 11 Dec 2019 12:05:39 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1if5Qd-0003Lc-W8 for qemu-arm@nongnu.org; Wed, 11 Dec 2019 12:05:37 -0500 Received: from mail-wm1-x341.google.com ([2a00:1450:4864:20::341]:51550) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1if5Qd-0003Jt-Nm for qemu-arm@nongnu.org; Wed, 11 Dec 2019 12:05:35 -0500 Received: by mail-wm1-x341.google.com with SMTP id d73so4689311wmd.1 for ; Wed, 11 Dec 2019 09:05:35 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=cTqY+VVrIEiDrOiDCyCP2RljFepIcDuXrggPXm+fTw0=; b=TxkYuR1DnqCgq1mczx8KHXMthfHNfQwOnzRJpuBI21ocFBCIaOIemVSwNrGKFHbbeG eDx6u7mKy97mGMD/RKmdgJD5jt7/r3X1MTd/QP/VvBxeHp69lLjEI4vw15gJZiuxNv+l C7NUVClkDRq39+geDsE9SgP2y5E4M3I5zECl6A1x5sZfdo7rCke0EOUdGdtwRzEm9JlE s153TxX8WtuRa44gfeUjomU/D978pnEFQjW752qUIA35Pu6WBn0xYlXWymKv46C1jZvk 3fk/6S3UqG9zuRudWSaaRrCDGJ/5LRFQnnR9RWvJwToqMJjs8oWbm/XIXpjbw7YItxqb pqOA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=cTqY+VVrIEiDrOiDCyCP2RljFepIcDuXrggPXm+fTw0=; b=hUMHUFnaJo26ZEtyCdgI4X9jrQ2PjKt3dLUemGXgIsJvSaqAOM3PKQcMVwCssn8bOy ZKXO1EXhj1r/dzpBcoIx/lkZr88LHCQL2WfxOdw/mjYixSuViEv4j+E+m41qQL8jMt/x m7Y6e0Q6Q3/B8ZxmCp/RiU1x4Qqh8PeiQyvpxTMa0DXa0g3idCnOJDVFM+zZA1BRCZ9z kszHRD/3ImuvMq1a2FstBWFQrc9tGR+ZSF/sHqc6pLOAt+RAmNI8FilqojIfQzfsViL0 T4FWH5l4wMtl6sawIYbToa0L2GTYcnd7oCfuKpAFGXLaWWL1zBVGg4EoIRRu30m3WYDg JYQA== X-Gm-Message-State: APjAAAW8uL5X5Vocq2NLAheutTS3un2eDemBbmsvoh4lONLcZ0+c42a1 gR6pYla9eivgV1derePw8RmGLA== X-Google-Smtp-Source: APXvYqzo6ZqLKRpWLUE2tgwotBtu5xSypQNINEsDC23ot9/qcVNpKrmxc0kMiJG2bLygUqbZmJn0lw== X-Received: by 2002:a1c:638a:: with SMTP id x132mr955737wmb.43.1576083934578; Wed, 11 Dec 2019 09:05:34 -0800 (PST) Received: from zen.linaroharston ([51.148.130.216]) by smtp.gmail.com with ESMTPSA id a184sm3043182wmf.29.2019.12.11.09.05.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 11 Dec 2019 09:05:30 -0800 (PST) Received: from zen.lan (localhost [127.0.0.1]) by zen.linaroharston (Postfix) with ESMTP id 62E7D1FF99; Wed, 11 Dec 2019 17:05:23 +0000 (GMT) From: =?UTF-8?q?Alex=20Benn=C3=A9e?= To: qemu-devel@nongnu.org Cc: richard.henderson@linaro.org, alan.hayward@arm.com, luis.machado@linaro.org, damien.hedde@greensocs.com, =?UTF-8?q?Alex=20Benn=C3=A9e?= , Peter Maydell , qemu-arm@nongnu.org (open list:ARM TCG CPUs) Subject: [PATCH v3 10/20] target/arm: explicitly encode regnum in our XML Date: Wed, 11 Dec 2019 17:05:10 +0000 Message-Id: <20191211170520.7747-11-alex.bennee@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20191211170520.7747-1-alex.bennee@linaro.org> References: <20191211170520.7747-1-alex.bennee@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::341 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 11 Dec 2019 17:05:42 -0000 This is described as optional but I'm not convinced of the numbering when multiple target fragments are sent. Signed-off-by: Alex Bennée Reviewed-by: Richard Henderson --- v2 - post inc param->n in place so we don't get out count wrong --- target/arm/cpu.h | 2 +- target/arm/gdbstub.c | 17 +++++++++++------ target/arm/helper.c | 2 +- 3 files changed, 13 insertions(+), 8 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index a31c7a36d6b..cc7258d5f1d 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -961,7 +961,7 @@ int arm_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); /* Dynamically generates for gdb stub an XML description of the sysregs from * the cp_regs hashtable. Returns the registered sysregs number. */ -int arm_gen_dynamic_sysreg_xml(CPUState *cpu); +int arm_gen_dynamic_sysreg_xml(CPUState *cpu, int base_reg); /* Returns the dynamically generated XML for the gdb stub. * Returns a pointer to the XML contents for the specified XML file or NULL diff --git a/target/arm/gdbstub.c b/target/arm/gdbstub.c index 1f68ab98c3b..69c35462a63 100644 --- a/target/arm/gdbstub.c +++ b/target/arm/gdbstub.c @@ -24,6 +24,7 @@ typedef struct RegisterSysregXmlParam { CPUState *cs; GString *s; + int n; } RegisterSysregXmlParam; /* Old gdb always expect FPA registers. Newer (xml-aware) gdb only expect @@ -108,10 +109,11 @@ int arm_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n) static void arm_gen_one_xml_sysreg_tag(GString *s, DynamicGDBXMLInfo *dyn_xml, ARMCPRegInfo *ri, uint32_t ri_key, - int bitsize) + int bitsize, int regnum) { g_string_append_printf(s, "name); g_string_append_printf(s, " bitsize=\"%d\"", bitsize); + g_string_append_printf(s, " regnum=\"%d\"", regnum); g_string_append_printf(s, " group=\"cp_regs\"/>"); dyn_xml->data.cpregs.keys[dyn_xml->num] = ri_key; dyn_xml->num++; @@ -131,7 +133,8 @@ static void arm_register_sysreg_for_xml(gpointer key, gpointer value, if (!(ri->type & (ARM_CP_NO_RAW | ARM_CP_NO_GDB))) { if (arm_feature(env, ARM_FEATURE_AARCH64)) { if (ri->state == ARM_CP_STATE_AA64) { - arm_gen_one_xml_sysreg_tag(s , dyn_xml, ri, ri_key, 64); + arm_gen_one_xml_sysreg_tag(s , dyn_xml, ri, ri_key, 64, + param->n++); } } else { if (ri->state == ARM_CP_STATE_AA32) { @@ -140,20 +143,22 @@ static void arm_register_sysreg_for_xml(gpointer key, gpointer value, return; } if (ri->type & ARM_CP_64BIT) { - arm_gen_one_xml_sysreg_tag(s , dyn_xml, ri, ri_key, 64); + arm_gen_one_xml_sysreg_tag(s , dyn_xml, ri, ri_key, 64, + param->n++); } else { - arm_gen_one_xml_sysreg_tag(s , dyn_xml, ri, ri_key, 32); + arm_gen_one_xml_sysreg_tag(s , dyn_xml, ri, ri_key, 32, + param->n++); } } } } } -int arm_gen_dynamic_sysreg_xml(CPUState *cs) +int arm_gen_dynamic_sysreg_xml(CPUState *cs, int base_reg) { ARMCPU *cpu = ARM_CPU(cs); GString *s = g_string_new(NULL); - RegisterSysregXmlParam param = {cs, s}; + RegisterSysregXmlParam param = {cs, s, base_reg}; cpu->dyn_sysreg_xml.num = 0; cpu->dyn_sysreg_xml.data.cpregs.keys = g_new(uint32_t, g_hash_table_size(cpu->cp_regs)); diff --git a/target/arm/helper.c b/target/arm/helper.c index 4bf133e2f42..d00e4fcca86 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -6995,7 +6995,7 @@ void arm_cpu_register_gdb_regs_for_features(ARMCPU *cpu) 19, "arm-vfp.xml", 0); } gdb_register_coprocessor(cs, arm_gdb_get_sysreg, arm_gdb_set_sysreg, - arm_gen_dynamic_sysreg_xml(cs), + arm_gen_dynamic_sysreg_xml(cs, cs->gdb_num_regs), "system-registers.xml", 0); } -- 2.20.1 From MAILER-DAEMON Wed Dec 11 12:05:47 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1if5Qo-0005Kz-4Z for mharc-qemu-arm@gnu.org; Wed, 11 Dec 2019 12:05:46 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:39881) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1if5Qj-0005Ek-0F for qemu-arm@nongnu.org; Wed, 11 Dec 2019 12:05:42 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1if5Qg-0003R7-SS for qemu-arm@nongnu.org; Wed, 11 Dec 2019 12:05:40 -0500 Received: from mail-wm1-x343.google.com ([2a00:1450:4864:20::343]:50633) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1if5Qg-0003Ol-HI for qemu-arm@nongnu.org; Wed, 11 Dec 2019 12:05:38 -0500 Received: by mail-wm1-x343.google.com with SMTP id a5so2195925wmb.0 for ; Wed, 11 Dec 2019 09:05:38 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; 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Wed, 11 Dec 2019 09:05:37 -0800 (PST) Received: from zen.linaroharston ([51.148.130.216]) by smtp.gmail.com with ESMTPSA id i8sm2971855wro.47.2019.12.11.09.05.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 11 Dec 2019 09:05:30 -0800 (PST) Received: from zen.lan (localhost [127.0.0.1]) by zen.linaroharston (Postfix) with ESMTP id 92E6D1FF9A; Wed, 11 Dec 2019 17:05:23 +0000 (GMT) From: =?UTF-8?q?Alex=20Benn=C3=A9e?= To: qemu-devel@nongnu.org Cc: richard.henderson@linaro.org, alan.hayward@arm.com, luis.machado@linaro.org, damien.hedde@greensocs.com, =?UTF-8?q?Alex=20Benn=C3=A9e?= , Peter Maydell , qemu-arm@nongnu.org (open list:ARM TCG CPUs) Subject: [PATCH v3 11/20] target/arm: default SVE length to 64 bytes for linux-user Date: Wed, 11 Dec 2019 17:05:11 +0000 Message-Id: <20191211170520.7747-12-alex.bennee@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20191211170520.7747-1-alex.bennee@linaro.org> References: <20191211170520.7747-1-alex.bennee@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::343 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 11 Dec 2019 17:05:44 -0000 The Linux kernel chooses the default of 64 bytes for SVE registers on the basis that it is the largest size on known hardware that won't grow the signal frame. We still honour the sve-max-vq property and userspace can expand the number of lanes by calling PR_SVE_SET_VL. This should not make any difference to SVE enabled software as the SVE is of course vector length agnostic. Signed-off-by: Alex Bennée --- v2 - tweak zcr_el[1] instead --- target/arm/cpu.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 7a4ac9339bf..d42b88c9b73 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -199,9 +199,9 @@ static void arm_cpu_reset(CPUState *s) /* and to the SVE instructions */ env->cp15.cpacr_el1 = deposit64(env->cp15.cpacr_el1, 16, 2, 3); env->cp15.cptr_el[3] |= CPTR_EZ; - /* with maximum vector length */ + /* with reasonable vector length */ env->vfp.zcr_el[1] = cpu_isar_feature(aa64_sve, cpu) ? - cpu->sve_max_vq - 1 : 0; + MIN(cpu->sve_max_vq - 1, 3) : 0; env->vfp.zcr_el[2] = env->vfp.zcr_el[1]; env->vfp.zcr_el[3] = env->vfp.zcr_el[1]; /* -- 2.20.1 From MAILER-DAEMON Wed Dec 11 12:05:47 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1if5Qp-0005Ll-6m for mharc-qemu-arm@gnu.org; Wed, 11 Dec 2019 12:05:47 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:39768) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1if5Qi-0005Dt-6b for qemu-arm@nongnu.org; Wed, 11 Dec 2019 12:05:42 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1if5Qf-0003P3-TV for qemu-arm@nongnu.org; Wed, 11 Dec 2019 12:05:39 -0500 Received: from mail-wm1-x342.google.com ([2a00:1450:4864:20::342]:35529) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1if5Qf-0003NW-I0 for qemu-arm@nongnu.org; Wed, 11 Dec 2019 12:05:37 -0500 Received: by mail-wm1-x342.google.com with SMTP id p17so3440175wmb.0 for ; Wed, 11 Dec 2019 09:05:37 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=1HpaLHcELOKuPjtThJu7f56C+AUGyKN1UycOs1q17Gw=; b=HW6vD3KqiSy869G9W7mvhE0KqffByMyihNiUgP9BAYccIpS/a2HfGKhcQ8GabkbtZb 5s/JIlKbDmo2BmZoDlXCvSxi1L9+YNcubpqi927+Ui+atUHu/WoGI0pB4yeDCqHxrndQ mjAkrAbXcx+/qr2WgOKx/aV11jymftQde/Vxuny4qanOmHxe15Axiz0aFXucWN/Jlyn8 Cuote+yxOeFBhCNjwolWOXrx45glfa0XtquiPjy0FWXz8cfQ20PljoeF4oqy2aSFfqJV Il5hWJSe02aV/yMyfM0qn/IWAGCLYmh1L8JDCLcQ2QFJmZTxeAIU/mfynPnZuqzd9M78 reRg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=1HpaLHcELOKuPjtThJu7f56C+AUGyKN1UycOs1q17Gw=; b=ZzANX9g21CJSFavdQtQrwPTxJ2DXs+bRsB/vgkmz4jproT9HTofW1ISUwxT7jOWILa ODu9ayCCyWve4h2w4Gauqa2wSbiwYUnbrxgtr0wIPr/1j1RWpeD18DJfBHkGN1VLY8n7 vARqtWylUB3eapVGt/pi96tyi4hRVWP4fdWd4xai2SfQ6AC8Gw5eL3zUk7180tX7dwEY KY6VaRWbX3ByLOmXaHsSmZC3ByVIGgF5bIVZtsi2V4CNFXORrhbBYXGOo8TUd0rQ+KQF K8Nk1roRP/U0FrXWOfmI1LHNg8URDK2JcsTbpZ+wr+/lW8ecu67yeKEe9UMlaHvDXLLd 2AHw== X-Gm-Message-State: APjAAAVsRv88/Mc8OJWDF3bHjkiZM76bNMPhqgzp6IqSr0KzMPrO7Z0L uNL0nigyfxKZkfEHOQ5Vs8Tto5VREHg= X-Google-Smtp-Source: APXvYqzrM0iWBf9CGjPr7yOfq9DZLBHXGdJqC1bxuIjHIoISvWEc4ICMEiiJg5AoOGIgY8o85vEV2Q== X-Received: by 2002:a7b:cb02:: with SMTP id u2mr880479wmj.142.1576083936293; Wed, 11 Dec 2019 09:05:36 -0800 (PST) Received: from zen.linaroharston ([51.148.130.216]) by smtp.gmail.com with ESMTPSA id 25sm2237549wmi.32.2019.12.11.09.05.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 11 Dec 2019 09:05:30 -0800 (PST) Received: from zen.lan (localhost [127.0.0.1]) by zen.linaroharston (Postfix) with ESMTP id 3173F1FF98; Wed, 11 Dec 2019 17:05:23 +0000 (GMT) From: =?UTF-8?q?Alex=20Benn=C3=A9e?= To: qemu-devel@nongnu.org Cc: richard.henderson@linaro.org, alan.hayward@arm.com, luis.machado@linaro.org, damien.hedde@greensocs.com, =?UTF-8?q?Alex=20Benn=C3=A9e?= , Peter Maydell , qemu-arm@nongnu.org (open list:ARM TCG CPUs) Subject: [PATCH v3 09/20] target/arm: prepare for multiple dynamic XMLs Date: Wed, 11 Dec 2019 17:05:09 +0000 Message-Id: <20191211170520.7747-10-alex.bennee@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20191211170520.7747-1-alex.bennee@linaro.org> References: <20191211170520.7747-1-alex.bennee@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::342 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 11 Dec 2019 17:05:44 -0000 We will want to generate similar dynamic XML for gdbstub support of SVE registers (the upstream doesn't use XML). To that end lightly rename a few things to make the distinction. Signed-off-by: Alex Bennée --- target/arm/cpu.h | 20 +++++++++++++------- target/arm/gdbstub.c | 30 +++++++++++++++--------------- target/arm/helper.c | 4 ++-- 3 files changed, 30 insertions(+), 24 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index cf16f915c82..a31c7a36d6b 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -128,14 +128,20 @@ enum { /** * DynamicGDBXMLInfo: * @desc: Contains the XML descriptions. - * @num_cpregs: Number of the Coprocessor registers seen by GDB. - * @cpregs_keys: Array that contains the corresponding Key of - * a given cpreg with the same order of the cpreg in the XML description. + * @num: Number of the registers in this XML seen by GDB. + * @data: A union with data specific to the set of registers + * @cpregs_keys: Array that contains the corresponding Key of + * a given cpreg with the same order of the cpreg + * in the XML description. */ typedef struct DynamicGDBXMLInfo { char *desc; - int num_cpregs; - uint32_t *cpregs_keys; + int num; + union { + struct { + uint32_t *keys; + } cpregs; + } data; } DynamicGDBXMLInfo; /* CPU state for each instance of a generic timer (in cp15 c14) */ @@ -748,7 +754,7 @@ struct ARMCPU { uint64_t *cpreg_vmstate_values; int32_t cpreg_vmstate_array_len; - DynamicGDBXMLInfo dyn_xml; + DynamicGDBXMLInfo dyn_sysreg_xml; /* Timers used by the generic (architected) timer */ QEMUTimer *gt_timer[NUM_GTIMERS]; @@ -955,7 +961,7 @@ int arm_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); /* Dynamically generates for gdb stub an XML description of the sysregs from * the cp_regs hashtable. Returns the registered sysregs number. */ -int arm_gen_dynamic_xml(CPUState *cpu); +int arm_gen_dynamic_sysreg_xml(CPUState *cpu); /* Returns the dynamically generated XML for the gdb stub. * Returns a pointer to the XML contents for the specified XML file or NULL diff --git a/target/arm/gdbstub.c b/target/arm/gdbstub.c index 4557775d245..1f68ab98c3b 100644 --- a/target/arm/gdbstub.c +++ b/target/arm/gdbstub.c @@ -106,15 +106,15 @@ int arm_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n) return 0; } -static void arm_gen_one_xml_reg_tag(GString *s, DynamicGDBXMLInfo *dyn_xml, - ARMCPRegInfo *ri, uint32_t ri_key, - int bitsize) +static void arm_gen_one_xml_sysreg_tag(GString *s, DynamicGDBXMLInfo *dyn_xml, + ARMCPRegInfo *ri, uint32_t ri_key, + int bitsize) { g_string_append_printf(s, "name); g_string_append_printf(s, " bitsize=\"%d\"", bitsize); g_string_append_printf(s, " group=\"cp_regs\"/>"); - dyn_xml->num_cpregs++; - dyn_xml->cpregs_keys[dyn_xml->num_cpregs - 1] = ri_key; + dyn_xml->data.cpregs.keys[dyn_xml->num] = ri_key; + dyn_xml->num++; } static void arm_register_sysreg_for_xml(gpointer key, gpointer value, @@ -126,12 +126,12 @@ static void arm_register_sysreg_for_xml(gpointer key, gpointer value, GString *s = param->s; ARMCPU *cpu = ARM_CPU(param->cs); CPUARMState *env = &cpu->env; - DynamicGDBXMLInfo *dyn_xml = &cpu->dyn_xml; + DynamicGDBXMLInfo *dyn_xml = &cpu->dyn_sysreg_xml; if (!(ri->type & (ARM_CP_NO_RAW | ARM_CP_NO_GDB))) { if (arm_feature(env, ARM_FEATURE_AARCH64)) { if (ri->state == ARM_CP_STATE_AA64) { - arm_gen_one_xml_reg_tag(s , dyn_xml, ri, ri_key, 64); + arm_gen_one_xml_sysreg_tag(s , dyn_xml, ri, ri_key, 64); } } else { if (ri->state == ARM_CP_STATE_AA32) { @@ -140,30 +140,30 @@ static void arm_register_sysreg_for_xml(gpointer key, gpointer value, return; } if (ri->type & ARM_CP_64BIT) { - arm_gen_one_xml_reg_tag(s , dyn_xml, ri, ri_key, 64); + arm_gen_one_xml_sysreg_tag(s , dyn_xml, ri, ri_key, 64); } else { - arm_gen_one_xml_reg_tag(s , dyn_xml, ri, ri_key, 32); + arm_gen_one_xml_sysreg_tag(s , dyn_xml, ri, ri_key, 32); } } } } } -int arm_gen_dynamic_xml(CPUState *cs) +int arm_gen_dynamic_sysreg_xml(CPUState *cs) { ARMCPU *cpu = ARM_CPU(cs); GString *s = g_string_new(NULL); RegisterSysregXmlParam param = {cs, s}; - cpu->dyn_xml.num_cpregs = 0; - cpu->dyn_xml.cpregs_keys = g_new(uint32_t, g_hash_table_size(cpu->cp_regs)); + cpu->dyn_sysreg_xml.num = 0; + cpu->dyn_sysreg_xml.data.cpregs.keys = g_new(uint32_t, g_hash_table_size(cpu->cp_regs)); g_string_printf(s, ""); g_string_append_printf(s, ""); g_string_append_printf(s, ""); g_hash_table_foreach(cpu->cp_regs, arm_register_sysreg_for_xml, ¶m); g_string_append_printf(s, ""); - cpu->dyn_xml.desc = g_string_free(s, false); - return cpu->dyn_xml.num_cpregs; + cpu->dyn_sysreg_xml.desc = g_string_free(s, false); + return cpu->dyn_sysreg_xml.num; } const char *arm_gdb_get_dynamic_xml(CPUState *cs, const char *xmlname) @@ -171,7 +171,7 @@ const char *arm_gdb_get_dynamic_xml(CPUState *cs, const char *xmlname) ARMCPU *cpu = ARM_CPU(cs); if (strcmp(xmlname, "system-registers.xml") == 0) { - return cpu->dyn_xml.desc; + return cpu->dyn_sysreg_xml.desc; } return NULL; } diff --git a/target/arm/helper.c b/target/arm/helper.c index 6476245e789..4bf133e2f42 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -207,7 +207,7 @@ static int arm_gdb_get_sysreg(CPUARMState *env, GByteArray *buf, int reg) const ARMCPRegInfo *ri; uint32_t key; - key = cpu->dyn_xml.cpregs_keys[reg]; + key = cpu->dyn_sysreg_xml.data.cpregs.keys[reg]; ri = get_arm_cp_reginfo(cpu->cp_regs, key); if (ri) { if (cpreg_field_is_64bit(ri)) { @@ -6995,7 +6995,7 @@ void arm_cpu_register_gdb_regs_for_features(ARMCPU *cpu) 19, "arm-vfp.xml", 0); } gdb_register_coprocessor(cs, arm_gdb_get_sysreg, arm_gdb_set_sysreg, - arm_gen_dynamic_xml(cs), + arm_gen_dynamic_sysreg_xml(cs), "system-registers.xml", 0); } -- 2.20.1 From MAILER-DAEMON Wed Dec 11 12:05:50 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1if5Qs-0005P6-0Y for mharc-qemu-arm@gnu.org; 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Wed, 11 Dec 2019 09:05:30 -0800 (PST) Received: from zen.lan (localhost [127.0.0.1]) by zen.linaroharston (Postfix) with ESMTP id E85C71FFA5; Wed, 11 Dec 2019 17:05:24 +0000 (GMT) From: =?UTF-8?q?Alex=20Benn=C3=A9e?= To: qemu-devel@nongnu.org Cc: richard.henderson@linaro.org, alan.hayward@arm.com, luis.machado@linaro.org, damien.hedde@greensocs.com, =?UTF-8?q?Alex=20Benn=C3=A9e?= , Peter Maydell , qemu-arm@nongnu.org (open list:ARM TCG CPUs) Subject: [PATCH v3 19/20] tests/tcg/aarch64: add SVE iotcl test Date: Wed, 11 Dec 2019 17:05:19 +0000 Message-Id: <20191211170520.7747-20-alex.bennee@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20191211170520.7747-1-alex.bennee@linaro.org> References: <20191211170520.7747-1-alex.bennee@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::441 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 11 Dec 2019 17:05:46 -0000 This is a fairly bare-bones test of setting the various vector sizes for SVE which will only fail if the PR_SVE_SET_VL can't reduce the user-space vector length by powers of 2. However we will also be able to use it in a future test which exercises the GDB stub. Signed-off-by: Alex Bennée --- v3 - use index to fill zreg - CROSS_CC_HAS_SVE --- tests/tcg/aarch64/sve-ioctls.c | 77 +++++++++++++++++++++++++++++++ tests/tcg/aarch64/Makefile.target | 4 ++ 2 files changed, 81 insertions(+) create mode 100644 tests/tcg/aarch64/sve-ioctls.c diff --git a/tests/tcg/aarch64/sve-ioctls.c b/tests/tcg/aarch64/sve-ioctls.c new file mode 100644 index 00000000000..d7bb64d53f9 --- /dev/null +++ b/tests/tcg/aarch64/sve-ioctls.c @@ -0,0 +1,77 @@ +/* + * SVE ioctls tests + * + * Test the SVE width setting ioctls work and provide a base for + * testing the gdbstub. + * + * Copyright (c) 2019 Linaro Ltd + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ +#include +#include +#include +#include +#include +#include + +#ifndef HWCAP_CPUID +#define HWCAP_CPUID (1 << 11) +#endif + +#define SVE_MAX_QUADS (2048 / 128) +#define BYTES_PER_QUAD (128 / 8) + +#define get_cpu_reg(id) ({ \ + unsigned long __val; \ + asm("mrs %0, "#id : "=r" (__val)); \ + __val; \ + }) + +static int do_sve_ioctl_test(void) +{ + int i, res, init_vq; + + res = prctl(PR_SVE_GET_VL, 0, 0, 0, 0); + if (res < 0) { + printf("FAILED to PR_SVE_GET_VL (%d)", res); + return -1; + } + init_vq = res & PR_SVE_VL_LEN_MASK; + + for (i = init_vq; i > 15; i /= 2) { + printf("Checking PR_SVE_SET_VL=%d\n", i); + res = prctl(PR_SVE_SET_VL, i, 0, 0, 0, 0); + if (res < 0) { + printf("FAILED to PR_SVE_SET_VL (%d)", res); + return -1; + } + asm("index z0.b, #0, #1\n" + ".global __sve_ld_done\n" + "__sve_ld_done:\n" + "mov z0.b, #0\n" + : /* no outputs kept */ + : /* no inputs */ + : "memory", "z0"); + } + printf("PASS\n"); + return 0; +} + +int main(int argc, char **argv) +{ + unsigned int sve_feature = (get_cpu_reg(ID_AA64PFR0_EL1) >> 32) & 0xf; + /* Exit early if we don't support SVE at all */ + if (sve_feature == 0x1) { + /* we also need to probe for the ioctl support */ + if (getauxval(AT_HWCAP) & HWCAP_SVE) { + return do_sve_ioctl_test(); + } else { + printf("SKIP: no HWCAP_SVE on this system\n"); + return 0; + } + } else { + printf("SKIP: no SVE on this system\n"); + return 0; + } +} diff --git a/tests/tcg/aarch64/Makefile.target b/tests/tcg/aarch64/Makefile.target index 3f8783ada5c..209c79a1ddb 100644 --- a/tests/tcg/aarch64/Makefile.target +++ b/tests/tcg/aarch64/Makefile.target @@ -36,6 +36,10 @@ ifneq ($(DOCKER_IMAGE)$(CROSS_CC_HAS_SVE),) # System Registers Tests AARCH64_TESTS += sysregs sysregs: CFLAGS+=-march=armv8.1-a+sve + +# SVE ioctl test +AARCH64_TESTS += sve-ioctls +sve-ioctls: CFLAGS+=-march=armv8.1-a+sve endif TESTS += $(AARCH64_TESTS) -- 2.20.1 From MAILER-DAEMON Wed Dec 11 12:05:52 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1if5Qu-0005S8-C6 for mharc-qemu-arm@gnu.org; Wed, 11 Dec 2019 12:05:52 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:40212) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1if5Ql-0005HM-79 for qemu-arm@nongnu.org; Wed, 11 Dec 2019 12:05:49 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1if5Qd-0003Kt-O7 for qemu-arm@nongnu.org; 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Wed, 11 Dec 2019 09:05:30 -0800 (PST) Received: from zen.lan (localhost [127.0.0.1]) by zen.linaroharston (Postfix) with ESMTP id F2FE31FF87; Wed, 11 Dec 2019 17:05:22 +0000 (GMT) From: =?UTF-8?q?Alex=20Benn=C3=A9e?= To: qemu-devel@nongnu.org Cc: richard.henderson@linaro.org, alan.hayward@arm.com, luis.machado@linaro.org, damien.hedde@greensocs.com, =?UTF-8?q?Alex=20Benn=C3=A9e?= , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Eduardo Habkost , Marcel Apfelbaum , Richard Henderson , Peter Maydell , "Edgar E. Iglesias" , Paolo Bonzini , Michael Walle , Laurent Vivier , Aurelien Jarno , Aleksandar Markovic , Aleksandar Rikalo , Chris Wulff , Marek Vasut , Stafford Horne , David Gibson , Palmer Dabbelt , Alistair Francis , Sagar Karandikar , Bastian Koppelmann , David Hildenbrand , Cornelia Huck , Mark Cave-Ayland , Artyom Tarasenko , Max Filippov , qemu-arm@nongnu.org (open list:ARM TCG CPUs), qemu-ppc@nongnu.org (open list:PowerPC TCG CPUs), qemu-riscv@nongnu.org (open list:RISC-V TCG CPUs), qemu-s390x@nongnu.org (open list:S390 TCG CPUs) Subject: [PATCH v3 08/20] gdbstub: extend GByteArray to read register helpers Date: Wed, 11 Dec 2019 17:05:08 +0000 Message-Id: <20191211170520.7747-9-alex.bennee@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20191211170520.7747-1-alex.bennee@linaro.org> References: <20191211170520.7747-1-alex.bennee@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::444 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 11 Dec 2019 17:05:50 -0000 Instead of passing a pointer to memory now just extend the GByteArray to all the read register helpers. They can then safely append their data through the normal way. We don't bother with this abstraction for write registers as we have already ensured the buffer being copied from is the correct size. Signed-off-by: Alex Bennée --- include/exec/gdbstub.h | 46 +++++++++++++++++----------- include/hw/core/cpu.h | 2 +- target/alpha/cpu.h | 2 +- target/arm/cpu.h | 4 +-- target/cris/cpu.h | 4 +-- target/hppa/cpu.h | 2 +- target/i386/cpu.h | 2 +- target/lm32/cpu.h | 2 +- target/m68k/cpu.h | 2 +- target/microblaze/cpu.h | 2 +- target/mips/internal.h | 2 +- target/openrisc/cpu.h | 2 +- target/ppc/cpu.h | 4 +-- target/riscv/cpu.h | 2 +- target/s390x/internal.h | 2 +- target/sh4/cpu.h | 2 +- target/sparc/cpu.h | 2 +- target/xtensa/cpu.h | 2 +- gdbstub.c | 20 ++++++------ hw/core/cpu.c | 2 +- target/alpha/gdbstub.c | 2 +- target/arm/gdbstub.c | 2 +- target/arm/gdbstub64.c | 2 +- target/arm/helper.c | 19 +++++------- target/cris/gdbstub.c | 4 +-- target/hppa/gdbstub.c | 2 +- target/i386/gdbstub.c | 2 +- target/lm32/gdbstub.c | 2 +- target/m68k/gdbstub.c | 2 +- target/m68k/helper.c | 4 +-- target/microblaze/gdbstub.c | 2 +- target/mips/gdbstub.c | 2 +- target/nios2/cpu.c | 2 +- target/openrisc/gdbstub.c | 2 +- target/ppc/gdbstub.c | 48 +++++++++++++++-------------- target/ppc/translate_init.inc.c | 54 ++++++++++++++++++--------------- target/riscv/gdbstub.c | 18 +++++------ target/s390x/gdbstub.c | 30 +++++++++--------- target/sh4/gdbstub.c | 2 +- target/sparc/gdbstub.c | 2 +- target/xtensa/gdbstub.c | 2 +- 41 files changed, 165 insertions(+), 148 deletions(-) diff --git a/include/exec/gdbstub.h b/include/exec/gdbstub.h index 59e366ba3af..ef79e32708c 100644 --- a/include/exec/gdbstub.h +++ b/include/exec/gdbstub.h @@ -68,49 +68,59 @@ void gdb_signalled(CPUArchState *, int); void gdbserver_fork(CPUState *); #endif /* Get or set a register. Returns the size of the register. */ -typedef int (*gdb_reg_cb)(CPUArchState *env, uint8_t *buf, int reg); +typedef int (*gdb_get_reg_cb)(CPUArchState *env, GByteArray *buf, int reg); +typedef int (*gdb_set_reg_cb)(CPUArchState *env, uint8_t *buf, int reg); void gdb_register_coprocessor(CPUState *cpu, - gdb_reg_cb get_reg, gdb_reg_cb set_reg, + gdb_get_reg_cb get_reg, gdb_set_reg_cb set_reg, int num_regs, const char *xml, int g_pos); -/* The GDB remote protocol transfers values in target byte order. This means - * we can use the raw memory access routines to access the value buffer. - * Conveniently, these also handle the case where the buffer is mis-aligned. +/* + * The GDB remote protocol transfers values in target byte order. As + * the gdbstub may be batching up several register values we always + * append to the array. */ -static inline int gdb_get_reg8(uint8_t *mem_buf, uint8_t val) +static inline int gdb_get_reg8(GByteArray *buf, uint8_t val) { - stb_p(mem_buf, val); + g_byte_array_append(buf, &val, 1); return 1; } -static inline int gdb_get_reg16(uint8_t *mem_buf, uint16_t val) +static inline int gdb_get_reg16(GByteArray *buf, uint16_t val) { - stw_p(mem_buf, val); + uint16_t to_word = tswap16(val); + g_byte_array_append(buf, (uint8_t *) &to_word, 2); return 2; } -static inline int gdb_get_reg32(uint8_t *mem_buf, uint32_t val) +static inline int gdb_get_reg32(GByteArray *buf, uint32_t val) { - stl_p(mem_buf, val); + uint32_t to_long = tswap32(val); + g_byte_array_append(buf, (uint8_t *) &to_long, 4); return 4; } -static inline int gdb_get_reg64(uint8_t *mem_buf, uint64_t val) +static inline int gdb_get_reg64(GByteArray *buf, uint64_t val) { - stq_p(mem_buf, val); + uint64_t to_quad = tswap64(val); + g_byte_array_append(buf, (uint8_t *) &to_quad, 8); return 8; } -static inline int gdb_get_reg128(uint8_t *mem_buf, uint64_t val_hi, +static inline int gdb_get_reg128(GByteArray *buf, uint64_t val_hi, uint64_t val_lo) { + uint64_t to_quad; #ifdef TARGET_WORDS_BIGENDIAN - stq_p(mem_buf, val_hi); - stq_p(mem_buf + 8, val_lo); + to_quad = tswap64(val_hi); + g_byte_array_append(buf, (uint8_t *) &to_quad, 8); + to_quad = tswap64(val_lo); + g_byte_array_append(buf, (uint8_t *) &to_quad, 8); #else - stq_p(mem_buf, val_lo); - stq_p(mem_buf + 8, val_hi); + to_quad = tswap64(val_lo); + g_byte_array_append(buf, (uint8_t *) &to_quad, 8); + to_quad = tswap64(val_hi); + g_byte_array_append(buf, (uint8_t *) &to_quad, 8); #endif return 16; } diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h index 77c6f052990..e85ec519add 100644 --- a/include/hw/core/cpu.h +++ b/include/hw/core/cpu.h @@ -195,7 +195,7 @@ typedef struct CPUClass { hwaddr (*get_phys_page_attrs_debug)(CPUState *cpu, vaddr addr, MemTxAttrs *attrs); int (*asidx_from_attrs)(CPUState *cpu, MemTxAttrs attrs); - int (*gdb_read_register)(CPUState *cpu, uint8_t *buf, int reg); + int (*gdb_read_register)(CPUState *cpu, GByteArray *buf, int reg); int (*gdb_write_register)(CPUState *cpu, uint8_t *buf, int reg); bool (*debug_check_watchpoint)(CPUState *cpu, CPUWatchpoint *wp); void (*debug_excp_handler)(CPUState *cpu); diff --git a/target/alpha/cpu.h b/target/alpha/cpu.h index a530249a5bf..faa09768424 100644 --- a/target/alpha/cpu.h +++ b/target/alpha/cpu.h @@ -282,7 +282,7 @@ void alpha_cpu_do_interrupt(CPUState *cpu); bool alpha_cpu_exec_interrupt(CPUState *cpu, int int_req); void alpha_cpu_dump_state(CPUState *cs, FILE *f, int flags); hwaddr alpha_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); -int alpha_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg); +int alpha_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); int alpha_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); void alpha_cpu_do_unaligned_access(CPUState *cpu, vaddr addr, MMUAccessType access_type, diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 83a809d4bac..cf16f915c82 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -949,7 +949,7 @@ bool arm_cpu_exec_interrupt(CPUState *cpu, int int_req); hwaddr arm_cpu_get_phys_page_attrs_debug(CPUState *cpu, vaddr addr, MemTxAttrs *attrs); -int arm_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg); +int arm_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); int arm_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); /* Dynamically generates for gdb stub an XML description of the sysregs from @@ -969,7 +969,7 @@ int arm_cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cs, int cpuid, void *opaque); #ifdef TARGET_AARCH64 -int aarch64_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg); +int aarch64_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); int aarch64_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); void aarch64_sve_narrow_vq(CPUARMState *env, unsigned vq); void aarch64_sve_change_el(CPUARMState *env, int old_el, diff --git a/target/cris/cpu.h b/target/cris/cpu.h index aba0a664744..333ee5b171a 100644 --- a/target/cris/cpu.h +++ b/target/cris/cpu.h @@ -194,8 +194,8 @@ void cris_cpu_dump_state(CPUState *cs, FILE *f, int flags); hwaddr cris_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); -int crisv10_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg); -int cris_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg); +int crisv10_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); +int cris_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); int cris_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); /* you can call this signal handler from your SIGBUS and SIGSEGV diff --git a/target/hppa/cpu.h b/target/hppa/cpu.h index 6713d04f111..801a4fb1bae 100644 --- a/target/hppa/cpu.h +++ b/target/hppa/cpu.h @@ -321,7 +321,7 @@ void cpu_hppa_change_prot_id(CPUHPPAState *env); int cpu_hppa_signal_handler(int host_signum, void *pinfo, void *puc); hwaddr hppa_cpu_get_phys_page_debug(CPUState *cs, vaddr addr); -int hppa_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg); +int hppa_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); int hppa_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); void hppa_cpu_do_interrupt(CPUState *cpu); bool hppa_cpu_exec_interrupt(CPUState *cpu, int int_req); diff --git a/target/i386/cpu.h b/target/i386/cpu.h index cde2a16b941..11720130e66 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -1757,7 +1757,7 @@ void x86_cpu_dump_state(CPUState *cs, FILE *f, int flags); hwaddr x86_cpu_get_phys_page_attrs_debug(CPUState *cpu, vaddr addr, MemTxAttrs *attrs); -int x86_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg); +int x86_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); int x86_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); void x86_cpu_exec_enter(CPUState *cpu); diff --git a/target/lm32/cpu.h b/target/lm32/cpu.h index 064c6b1267e..01d408eb55d 100644 --- a/target/lm32/cpu.h +++ b/target/lm32/cpu.h @@ -202,7 +202,7 @@ void lm32_cpu_do_interrupt(CPUState *cpu); bool lm32_cpu_exec_interrupt(CPUState *cs, int int_req); void lm32_cpu_dump_state(CPUState *cpu, FILE *f, int flags); hwaddr lm32_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); -int lm32_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg); +int lm32_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); int lm32_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); typedef enum { diff --git a/target/m68k/cpu.h b/target/m68k/cpu.h index 20de3c379aa..cdb08c269f6 100644 --- a/target/m68k/cpu.h +++ b/target/m68k/cpu.h @@ -168,7 +168,7 @@ void m68k_cpu_do_interrupt(CPUState *cpu); bool m68k_cpu_exec_interrupt(CPUState *cpu, int int_req); void m68k_cpu_dump_state(CPUState *cpu, FILE *f, int flags); hwaddr m68k_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); -int m68k_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg); +int m68k_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); int m68k_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); void m68k_tcg_init(void); diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h index 95773089aa3..987e4629b0a 100644 --- a/target/microblaze/cpu.h +++ b/target/microblaze/cpu.h @@ -313,7 +313,7 @@ void mb_cpu_do_interrupt(CPUState *cs); bool mb_cpu_exec_interrupt(CPUState *cs, int int_req); void mb_cpu_dump_state(CPUState *cpu, FILE *f, int flags); hwaddr mb_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); -int mb_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg); +int mb_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); int mb_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); void mb_tcg_init(void); diff --git a/target/mips/internal.h b/target/mips/internal.h index 3f435b5e631..c5ae86360f5 100644 --- a/target/mips/internal.h +++ b/target/mips/internal.h @@ -82,7 +82,7 @@ void mips_cpu_do_interrupt(CPUState *cpu); bool mips_cpu_exec_interrupt(CPUState *cpu, int int_req); void mips_cpu_dump_state(CPUState *cpu, FILE *f, int flags); hwaddr mips_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); -int mips_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg); +int mips_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); int mips_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); void mips_cpu_do_unaligned_access(CPUState *cpu, vaddr addr, MMUAccessType access_type, diff --git a/target/openrisc/cpu.h b/target/openrisc/cpu.h index 0ad02eab794..d9484b802f3 100644 --- a/target/openrisc/cpu.h +++ b/target/openrisc/cpu.h @@ -320,7 +320,7 @@ void openrisc_cpu_do_interrupt(CPUState *cpu); bool openrisc_cpu_exec_interrupt(CPUState *cpu, int int_req); void openrisc_cpu_dump_state(CPUState *cpu, FILE *f, int flags); hwaddr openrisc_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); -int openrisc_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg); +int openrisc_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); int openrisc_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); void openrisc_translate_init(void); bool openrisc_cpu_tlb_fill(CPUState *cs, vaddr address, int size, diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index e3e82327b72..ed3f55ea4b4 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -1258,8 +1258,8 @@ bool ppc_cpu_exec_interrupt(CPUState *cpu, int int_req); void ppc_cpu_dump_state(CPUState *cpu, FILE *f, int flags); void ppc_cpu_dump_statistics(CPUState *cpu, int flags); hwaddr ppc_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); -int ppc_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg); -int ppc_cpu_gdb_read_register_apple(CPUState *cpu, uint8_t *buf, int reg); +int ppc_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); +int ppc_cpu_gdb_read_register_apple(CPUState *cpu, GByteArray *buf, int reg); int ppc_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); int ppc_cpu_gdb_write_register_apple(CPUState *cpu, uint8_t *buf, int reg); #ifndef CONFIG_USER_ONLY diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index e59343e13c0..fe0b8861021 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -243,7 +243,7 @@ extern const char * const riscv_excp_names[]; extern const char * const riscv_intr_names[]; void riscv_cpu_do_interrupt(CPUState *cpu); -int riscv_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg); +int riscv_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); int riscv_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); bool riscv_cpu_exec_interrupt(CPUState *cs, int interrupt_request); bool riscv_cpu_fp_enabled(CPURISCVState *env); diff --git a/target/s390x/internal.h b/target/s390x/internal.h index d37816104dd..8c95c734dbe 100644 --- a/target/s390x/internal.h +++ b/target/s390x/internal.h @@ -292,7 +292,7 @@ uint16_t float128_dcmask(CPUS390XState *env, float128 f1); /* gdbstub.c */ -int s390_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg); +int s390_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); int s390_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); void s390_cpu_gdb_init(CPUState *cs); diff --git a/target/sh4/cpu.h b/target/sh4/cpu.h index ecaa7a18a94..d7a1bffd600 100644 --- a/target/sh4/cpu.h +++ b/target/sh4/cpu.h @@ -208,7 +208,7 @@ void superh_cpu_do_interrupt(CPUState *cpu); bool superh_cpu_exec_interrupt(CPUState *cpu, int int_req); void superh_cpu_dump_state(CPUState *cpu, FILE *f, int flags); hwaddr superh_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); -int superh_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg); +int superh_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); int superh_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); void superh_cpu_do_unaligned_access(CPUState *cpu, vaddr addr, MMUAccessType access_type, diff --git a/target/sparc/cpu.h b/target/sparc/cpu.h index ae97c7d9f79..b9369398f24 100644 --- a/target/sparc/cpu.h +++ b/target/sparc/cpu.h @@ -571,7 +571,7 @@ extern const VMStateDescription vmstate_sparc_cpu; void sparc_cpu_do_interrupt(CPUState *cpu); void sparc_cpu_dump_state(CPUState *cpu, FILE *f, int flags); hwaddr sparc_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); -int sparc_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg); +int sparc_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); int sparc_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); void QEMU_NORETURN sparc_cpu_do_unaligned_access(CPUState *cpu, vaddr addr, MMUAccessType access_type, diff --git a/target/xtensa/cpu.h b/target/xtensa/cpu.h index b363ffcf106..b20be1f5814 100644 --- a/target/xtensa/cpu.h +++ b/target/xtensa/cpu.h @@ -569,7 +569,7 @@ void xtensa_cpu_dump_state(CPUState *cpu, FILE *f, int flags); hwaddr xtensa_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); void xtensa_count_regs(const XtensaConfig *config, unsigned *n_regs, unsigned *n_core_regs); -int xtensa_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg); +int xtensa_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); int xtensa_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); void xtensa_cpu_do_unaligned_access(CPUState *cpu, vaddr addr, MMUAccessType access_type, diff --git a/gdbstub.c b/gdbstub.c index ba63710cdcf..b51df542a70 100644 --- a/gdbstub.c +++ b/gdbstub.c @@ -319,8 +319,8 @@ static int gdb_signal_to_target (int sig) typedef struct GDBRegisterState { int base_reg; int num_regs; - gdb_reg_cb get_reg; - gdb_reg_cb set_reg; + gdb_get_reg_cb get_reg; + gdb_set_reg_cb set_reg; const char *xml; struct GDBRegisterState *next; } GDBRegisterState; @@ -905,19 +905,19 @@ static const char *get_feature_xml(const char *p, const char **newp, return name ? xml_builtin[i][1] : NULL; } -static int gdb_read_register(CPUState *cpu, uint8_t *mem_buf, int reg) +static int gdb_read_register(CPUState *cpu, GByteArray *buf, int reg) { CPUClass *cc = CPU_GET_CLASS(cpu); CPUArchState *env = cpu->env_ptr; GDBRegisterState *r; if (reg < cc->gdb_num_core_regs) { - return cc->gdb_read_register(cpu, mem_buf, reg); + return cc->gdb_read_register(cpu, buf, reg); } for (r = cpu->gdb_regs; r; r = r->next) { if (r->base_reg <= reg && reg < r->base_reg + r->num_regs) { - return r->get_reg(env, mem_buf, reg - r->base_reg); + return r->get_reg(env, buf, reg - r->base_reg); } } return 0; @@ -948,7 +948,7 @@ static int gdb_write_register(CPUState *cpu, uint8_t *mem_buf, int reg) */ void gdb_register_coprocessor(CPUState *cpu, - gdb_reg_cb get_reg, gdb_reg_cb set_reg, + gdb_get_reg_cb get_reg, gdb_set_reg_cb set_reg, int num_regs, const char *xml, int g_pos) { GDBRegisterState *s; @@ -1739,7 +1739,7 @@ static void handle_get_reg(GdbCmdContext *gdb_ctx, void *user_ctx) } reg_size = gdb_read_register(gdbserver_state.g_cpu, - gdbserver_state.mem_buf->data, + gdbserver_state.mem_buf, gdb_ctx->params[0].val_ull); if (!reg_size) { put_packet("E14"); @@ -1832,14 +1832,14 @@ static void handle_read_all_regs(GdbCmdContext *gdb_ctx, void *user_ctx) target_ulong addr, len; cpu_synchronize_state(gdbserver_state.g_cpu); + g_byte_array_set_size(gdbserver_state.mem_buf, 0); len = 0; for (addr = 0; addr < gdbserver_state.g_cpu->gdb_num_g_regs; addr++) { len += gdb_read_register(gdbserver_state.g_cpu, - gdbserver_state.mem_buf->data + len, + gdbserver_state.mem_buf, addr); } - /* FIXME: This is after the fact sizing */ - g_byte_array_set_size(gdbserver_state.mem_buf, len); + g_assert(len == gdbserver_state.mem_buf->len); memtohex(gdbserver_state.str_buf, gdbserver_state.mem_buf->data, len); put_strbuf(); diff --git a/hw/core/cpu.c b/hw/core/cpu.c index db1a03c6bbb..9cd1a2a54fb 100644 --- a/hw/core/cpu.c +++ b/hw/core/cpu.c @@ -177,7 +177,7 @@ static int cpu_common_write_elf64_note(WriteCoreDumpFunction f, } -static int cpu_common_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg) +static int cpu_common_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg) { return 0; } diff --git a/target/alpha/gdbstub.c b/target/alpha/gdbstub.c index 7f9cc092a9c..0cd76ddaa9e 100644 --- a/target/alpha/gdbstub.c +++ b/target/alpha/gdbstub.c @@ -21,7 +21,7 @@ #include "cpu.h" #include "exec/gdbstub.h" -int alpha_cpu_gdb_read_register(CPUState *cs, uint8_t *mem_buf, int n) +int alpha_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n) { AlphaCPU *cpu = ALPHA_CPU(cs); CPUAlphaState *env = &cpu->env; diff --git a/target/arm/gdbstub.c b/target/arm/gdbstub.c index 1239abd9842..4557775d245 100644 --- a/target/arm/gdbstub.c +++ b/target/arm/gdbstub.c @@ -32,7 +32,7 @@ typedef struct RegisterSysregXmlParam { We hack round this by giving the FPA regs zero size when talking to a newer gdb. */ -int arm_cpu_gdb_read_register(CPUState *cs, uint8_t *mem_buf, int n) +int arm_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n) { ARMCPU *cpu = ARM_CPU(cs); CPUARMState *env = &cpu->env; diff --git a/target/arm/gdbstub64.c b/target/arm/gdbstub64.c index 665ebb3ef64..35d0b80c2de 100644 --- a/target/arm/gdbstub64.c +++ b/target/arm/gdbstub64.c @@ -20,7 +20,7 @@ #include "cpu.h" #include "exec/gdbstub.h" -int aarch64_cpu_gdb_read_register(CPUState *cs, uint8_t *mem_buf, int n) +int aarch64_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n) { ARMCPU *cpu = ARM_CPU(cs); CPUARMState *env = &cpu->env; diff --git a/target/arm/helper.c b/target/arm/helper.c index 0ac950d6c71..6476245e789 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -47,30 +47,27 @@ static bool get_phys_addr_lpae(CPUARMState *env, target_ulong address, static void switch_mode(CPUARMState *env, int mode); -static int vfp_gdb_get_reg(CPUARMState *env, uint8_t *buf, int reg) +static int vfp_gdb_get_reg(CPUARMState *env, GByteArray *buf, int reg) { int nregs; /* VFP data registers are always little-endian. */ nregs = arm_feature(env, ARM_FEATURE_VFP3) ? 32 : 16; if (reg < nregs) { - stq_le_p(buf, *aa32_vfp_dreg(env, reg)); - return 8; + return gdb_get_reg64(buf, *aa32_vfp_dreg(env, reg)); } if (arm_feature(env, ARM_FEATURE_NEON)) { /* Aliases for Q regs. */ nregs += 16; if (reg < nregs) { uint64_t *q = aa32_vfp_qreg(env, reg - 32); - stq_le_p(buf, q[0]); - stq_le_p(buf + 8, q[1]); - return 16; + return gdb_get_reg128(buf, q[0], q[1]); } } switch (reg - nregs) { - case 0: stl_p(buf, env->vfp.xregs[ARM_VFP_FPSID]); return 4; - case 1: stl_p(buf, vfp_get_fpscr(env)); return 4; - case 2: stl_p(buf, env->vfp.xregs[ARM_VFP_FPEXC]); return 4; + case 0: return gdb_get_reg32(buf, env->vfp.xregs[ARM_VFP_FPSID]); break; + case 1: return gdb_get_reg32(buf, vfp_get_fpscr(env)); break; + case 2: return gdb_get_reg32(buf, env->vfp.xregs[ARM_VFP_FPEXC]); break; } return 0; } @@ -101,7 +98,7 @@ static int vfp_gdb_set_reg(CPUARMState *env, uint8_t *buf, int reg) return 0; } -static int aarch64_fpu_gdb_get_reg(CPUARMState *env, uint8_t *buf, int reg) +static int aarch64_fpu_gdb_get_reg(CPUARMState *env, GByteArray *buf, int reg) { switch (reg) { case 0 ... 31: @@ -204,7 +201,7 @@ static void write_raw_cp_reg(CPUARMState *env, const ARMCPRegInfo *ri, } } -static int arm_gdb_get_sysreg(CPUARMState *env, uint8_t *buf, int reg) +static int arm_gdb_get_sysreg(CPUARMState *env, GByteArray *buf, int reg) { ARMCPU *cpu = env_archcpu(env); const ARMCPRegInfo *ri; diff --git a/target/cris/gdbstub.c b/target/cris/gdbstub.c index a3d76d2e8c2..b01b2aa0811 100644 --- a/target/cris/gdbstub.c +++ b/target/cris/gdbstub.c @@ -21,7 +21,7 @@ #include "cpu.h" #include "exec/gdbstub.h" -int crisv10_cpu_gdb_read_register(CPUState *cs, uint8_t *mem_buf, int n) +int crisv10_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n) { CRISCPU *cpu = CRIS_CPU(cs); CPUCRISState *env = &cpu->env; @@ -53,7 +53,7 @@ int crisv10_cpu_gdb_read_register(CPUState *cs, uint8_t *mem_buf, int n) return 0; } -int cris_cpu_gdb_read_register(CPUState *cs, uint8_t *mem_buf, int n) +int cris_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n) { CRISCPU *cpu = CRIS_CPU(cs); CPUCRISState *env = &cpu->env; diff --git a/target/hppa/gdbstub.c b/target/hppa/gdbstub.c index 341888a9da0..a6428a2893f 100644 --- a/target/hppa/gdbstub.c +++ b/target/hppa/gdbstub.c @@ -21,7 +21,7 @@ #include "cpu.h" #include "exec/gdbstub.h" -int hppa_cpu_gdb_read_register(CPUState *cs, uint8_t *mem_buf, int n) +int hppa_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n) { HPPACPU *cpu = HPPA_CPU(cs); CPUHPPAState *env = &cpu->env; diff --git a/target/i386/gdbstub.c b/target/i386/gdbstub.c index aef25b70f10..38324498f33 100644 --- a/target/i386/gdbstub.c +++ b/target/i386/gdbstub.c @@ -79,7 +79,7 @@ static const int gpr_map32[8] = { 0, 1, 2, 3, 4, 5, 6, 7 }; #endif -int x86_cpu_gdb_read_register(CPUState *cs, uint8_t *mem_buf, int n) +int x86_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n) { X86CPU *cpu = X86_CPU(cs); CPUX86State *env = &cpu->env; diff --git a/target/lm32/gdbstub.c b/target/lm32/gdbstub.c index 82ede436e12..b6fe12e1d61 100644 --- a/target/lm32/gdbstub.c +++ b/target/lm32/gdbstub.c @@ -22,7 +22,7 @@ #include "exec/gdbstub.h" #include "hw/lm32/lm32_pic.h" -int lm32_cpu_gdb_read_register(CPUState *cs, uint8_t *mem_buf, int n) +int lm32_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n) { LM32CPU *cpu = LM32_CPU(cs); CPULM32State *env = &cpu->env; diff --git a/target/m68k/gdbstub.c b/target/m68k/gdbstub.c index fdc96f57fff..eb2d030e148 100644 --- a/target/m68k/gdbstub.c +++ b/target/m68k/gdbstub.c @@ -21,7 +21,7 @@ #include "cpu.h" #include "exec/gdbstub.h" -int m68k_cpu_gdb_read_register(CPUState *cs, uint8_t *mem_buf, int n) +int m68k_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n) { M68kCPU *cpu = M68K_CPU(cs); CPUM68KState *env = &cpu->env; diff --git a/target/m68k/helper.c b/target/m68k/helper.c index 2573ee7a535..6f9099cd937 100644 --- a/target/m68k/helper.c +++ b/target/m68k/helper.c @@ -68,7 +68,7 @@ void m68k_cpu_list(void) g_slist_free(list); } -static int cf_fpu_gdb_get_reg(CPUM68KState *env, uint8_t *mem_buf, int n) +static int cf_fpu_gdb_get_reg(CPUM68KState *env, GByteArray *mem_buf, int n) { if (n < 8) { float_status s; @@ -105,7 +105,7 @@ static int cf_fpu_gdb_set_reg(CPUM68KState *env, uint8_t *mem_buf, int n) return 0; } -static int m68k_fpu_gdb_get_reg(CPUM68KState *env, uint8_t *mem_buf, int n) +static int m68k_fpu_gdb_get_reg(CPUM68KState *env, GByteArray *mem_buf, int n) { if (n < 8) { int len = gdb_get_reg16(mem_buf, env->fregs[n].l.upper); diff --git a/target/microblaze/gdbstub.c b/target/microblaze/gdbstub.c index 30677b6d1f4..f41ebf1f33b 100644 --- a/target/microblaze/gdbstub.c +++ b/target/microblaze/gdbstub.c @@ -21,7 +21,7 @@ #include "cpu.h" #include "exec/gdbstub.h" -int mb_cpu_gdb_read_register(CPUState *cs, uint8_t *mem_buf, int n) +int mb_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n) { MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs); CPUMBState *env = &cpu->env; diff --git a/target/mips/gdbstub.c b/target/mips/gdbstub.c index bbb25449391..98f56e660d2 100644 --- a/target/mips/gdbstub.c +++ b/target/mips/gdbstub.c @@ -22,7 +22,7 @@ #include "internal.h" #include "exec/gdbstub.h" -int mips_cpu_gdb_read_register(CPUState *cs, uint8_t *mem_buf, int n) +int mips_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n) { MIPSCPU *cpu = MIPS_CPU(cs); CPUMIPSState *env = &cpu->env; diff --git a/target/nios2/cpu.c b/target/nios2/cpu.c index ca9c7a6df5d..17d868421ed 100644 --- a/target/nios2/cpu.c +++ b/target/nios2/cpu.c @@ -124,7 +124,7 @@ static void nios2_cpu_disas_set_info(CPUState *cpu, disassemble_info *info) #endif } -static int nios2_cpu_gdb_read_register(CPUState *cs, uint8_t *mem_buf, int n) +static int nios2_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n) { Nios2CPU *cpu = NIOS2_CPU(cs); CPUClass *cc = CPU_GET_CLASS(cs); diff --git a/target/openrisc/gdbstub.c b/target/openrisc/gdbstub.c index 0fcdb79668c..095bf76c12c 100644 --- a/target/openrisc/gdbstub.c +++ b/target/openrisc/gdbstub.c @@ -21,7 +21,7 @@ #include "cpu.h" #include "exec/gdbstub.h" -int openrisc_cpu_gdb_read_register(CPUState *cs, uint8_t *mem_buf, int n) +int openrisc_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n) { OpenRISCCPU *cpu = OPENRISC_CPU(cs); CPUOpenRISCState *env = &cpu->env; diff --git a/target/ppc/gdbstub.c b/target/ppc/gdbstub.c index 823759c92e7..6f08021cc22 100644 --- a/target/ppc/gdbstub.c +++ b/target/ppc/gdbstub.c @@ -114,10 +114,11 @@ void ppc_maybe_bswap_register(CPUPPCState *env, uint8_t *mem_buf, int len) * the FP regs zero size when talking to a newer gdb. */ -int ppc_cpu_gdb_read_register(CPUState *cs, uint8_t *mem_buf, int n) +int ppc_cpu_gdb_read_register(CPUState *cs, GByteArray *buf, int n) { PowerPCCPU *cpu = POWERPC_CPU(cs); CPUPPCState *env = &cpu->env; + uint8_t *mem_buf; int r = ppc_gdb_register_len(n); if (!r) { @@ -126,17 +127,17 @@ int ppc_cpu_gdb_read_register(CPUState *cs, uint8_t *mem_buf, int n) if (n < 32) { /* gprs */ - gdb_get_regl(mem_buf, env->gpr[n]); + gdb_get_regl(buf, env->gpr[n]); } else if (n < 64) { /* fprs */ - stfq_p(mem_buf, *cpu_fpr_ptr(env, n - 32)); + gdb_get_reg64(buf, *cpu_fpr_ptr(env, n - 32)); } else { switch (n) { case 64: - gdb_get_regl(mem_buf, env->nip); + gdb_get_regl(buf, env->nip); break; case 65: - gdb_get_regl(mem_buf, env->msr); + gdb_get_regl(buf, env->msr); break; case 66: { @@ -145,31 +146,33 @@ int ppc_cpu_gdb_read_register(CPUState *cs, uint8_t *mem_buf, int n) for (i = 0; i < 8; i++) { cr |= env->crf[i] << (32 - ((i + 1) * 4)); } - gdb_get_reg32(mem_buf, cr); + gdb_get_reg32(buf, cr); break; } case 67: - gdb_get_regl(mem_buf, env->lr); + gdb_get_regl(buf, env->lr); break; case 68: - gdb_get_regl(mem_buf, env->ctr); + gdb_get_regl(buf, env->ctr); break; case 69: - gdb_get_reg32(mem_buf, env->xer); + gdb_get_reg32(buf, env->xer); break; case 70: - gdb_get_reg32(mem_buf, env->fpscr); + gdb_get_reg32(buf, env->fpscr); break; } } + mem_buf = buf->data - r; ppc_maybe_bswap_register(env, mem_buf, r); return r; } -int ppc_cpu_gdb_read_register_apple(CPUState *cs, uint8_t *mem_buf, int n) +int ppc_cpu_gdb_read_register_apple(CPUState *cs, GByteArray *buf, int n) { PowerPCCPU *cpu = POWERPC_CPU(cs); CPUPPCState *env = &cpu->env; + uint8_t *mem_buf; int r = ppc_gdb_register_len_apple(n); if (!r) { @@ -178,21 +181,21 @@ int ppc_cpu_gdb_read_register_apple(CPUState *cs, uint8_t *mem_buf, int n) if (n < 32) { /* gprs */ - gdb_get_reg64(mem_buf, env->gpr[n]); + gdb_get_reg64(buf, env->gpr[n]); } else if (n < 64) { /* fprs */ - stfq_p(mem_buf, *cpu_fpr_ptr(env, n - 32)); + gdb_get_reg64(buf, *cpu_fpr_ptr(env, n - 32)); } else if (n < 96) { /* Altivec */ - stq_p(mem_buf, n - 64); - stq_p(mem_buf + 8, 0); + gdb_get_reg64(buf, n - 64); + gdb_get_reg64(buf, 0); } else { switch (n) { case 64 + 32: - gdb_get_reg64(mem_buf, env->nip); + gdb_get_reg64(buf, env->nip); break; case 65 + 32: - gdb_get_reg64(mem_buf, env->msr); + gdb_get_reg64(buf, env->msr); break; case 66 + 32: { @@ -201,23 +204,24 @@ int ppc_cpu_gdb_read_register_apple(CPUState *cs, uint8_t *mem_buf, int n) for (i = 0; i < 8; i++) { cr |= env->crf[i] << (32 - ((i + 1) * 4)); } - gdb_get_reg32(mem_buf, cr); + gdb_get_reg32(buf, cr); break; } case 67 + 32: - gdb_get_reg64(mem_buf, env->lr); + gdb_get_reg64(buf, env->lr); break; case 68 + 32: - gdb_get_reg64(mem_buf, env->ctr); + gdb_get_reg64(buf, env->ctr); break; case 69 + 32: - gdb_get_reg32(mem_buf, env->xer); + gdb_get_reg32(buf, env->xer); break; case 70 + 32: - gdb_get_reg64(mem_buf, env->fpscr); + gdb_get_reg64(buf, env->fpscr); break; } } + mem_buf = buf->data - r; ppc_maybe_bswap_register(env, mem_buf, r); return r; } diff --git a/target/ppc/translate_init.inc.c b/target/ppc/translate_init.inc.c index ba726dec4d0..154f876e44c 100644 --- a/target/ppc/translate_init.inc.c +++ b/target/ppc/translate_init.inc.c @@ -9587,7 +9587,7 @@ static int gdb_find_spr_idx(CPUPPCState *env, int n) return -1; } -static int gdb_get_spr_reg(CPUPPCState *env, uint8_t *mem_buf, int n) +static int gdb_get_spr_reg(CPUPPCState *env, GByteArray *buf, int n) { int reg; int len; @@ -9598,8 +9598,8 @@ static int gdb_get_spr_reg(CPUPPCState *env, uint8_t *mem_buf, int n) } len = TARGET_LONG_SIZE; - stn_p(mem_buf, len, env->spr[reg]); - ppc_maybe_bswap_register(env, mem_buf, len); + gdb_get_regl(buf, env->spr[reg]); + ppc_maybe_bswap_register(env, buf->data - len, len); return len; } @@ -9621,15 +9621,18 @@ static int gdb_set_spr_reg(CPUPPCState *env, uint8_t *mem_buf, int n) } #endif -static int gdb_get_float_reg(CPUPPCState *env, uint8_t *mem_buf, int n) +static int gdb_get_float_reg(CPUPPCState *env, GByteArray *buf, int n) { + uint8_t *mem_buf; if (n < 32) { - stfq_p(mem_buf, *cpu_fpr_ptr(env, n)); + gdb_get_reg64(buf, *cpu_fpr_ptr(env, n)); + mem_buf = buf->data - 8; ppc_maybe_bswap_register(env, mem_buf, 8); return 8; } if (n == 32) { - stl_p(mem_buf, env->fpscr); + gdb_get_reg32(buf, env->fpscr); + mem_buf = buf->data - 4; ppc_maybe_bswap_register(env, mem_buf, 4); return 4; } @@ -9651,28 +9654,31 @@ static int gdb_set_float_reg(CPUPPCState *env, uint8_t *mem_buf, int n) return 0; } -static int gdb_get_avr_reg(CPUPPCState *env, uint8_t *mem_buf, int n) +static int gdb_get_avr_reg(CPUPPCState *env, GByteArray *buf, int n) { + uint8_t *mem_buf; + if (n < 32) { ppc_avr_t *avr = cpu_avr_ptr(env, n); if (!avr_need_swap(env)) { - stq_p(mem_buf, avr->u64[0]); - stq_p(mem_buf + 8, avr->u64[1]); + gdb_get_reg128(buf, avr->u64[0] , avr->u64[1]); } else { - stq_p(mem_buf, avr->u64[1]); - stq_p(mem_buf + 8, avr->u64[0]); + gdb_get_reg128(buf, avr->u64[1] , avr->u64[0]); } + mem_buf = buf->data - 16; ppc_maybe_bswap_register(env, mem_buf, 8); ppc_maybe_bswap_register(env, mem_buf + 8, 8); return 16; } if (n == 32) { - stl_p(mem_buf, helper_mfvscr(env)); + gdb_get_reg32(buf, helper_mfvscr(env)); + mem_buf = buf->data - 4; ppc_maybe_bswap_register(env, mem_buf, 4); return 4; } if (n == 33) { - stl_p(mem_buf, (uint32_t)env->spr[SPR_VRSAVE]); + gdb_get_reg32(buf, (uint32_t)env->spr[SPR_VRSAVE]); + mem_buf = buf->data - 4; ppc_maybe_bswap_register(env, mem_buf, 4); return 4; } @@ -9707,25 +9713,25 @@ static int gdb_set_avr_reg(CPUPPCState *env, uint8_t *mem_buf, int n) return 0; } -static int gdb_get_spe_reg(CPUPPCState *env, uint8_t *mem_buf, int n) +static int gdb_get_spe_reg(CPUPPCState *env, GByteArray *buf, int n) { if (n < 32) { #if defined(TARGET_PPC64) - stl_p(mem_buf, env->gpr[n] >> 32); - ppc_maybe_bswap_register(env, mem_buf, 4); + gdb_get_reg32(buf, env->gpr[n] >> 32); + ppc_maybe_bswap_register(env, buf->data - 4, 4); #else - stl_p(mem_buf, env->gprh[n]); + gdb_get_reg32(buf, env->gprh[n]); #endif return 4; } if (n == 32) { - stq_p(mem_buf, env->spe_acc); - ppc_maybe_bswap_register(env, mem_buf, 8); + gdb_get_reg64(buf, env->spe_acc); + ppc_maybe_bswap_register(env, buf->data - 8, 8); return 8; } if (n == 33) { - stl_p(mem_buf, env->spe_fscr); - ppc_maybe_bswap_register(env, mem_buf, 4); + gdb_get_reg32(buf, env->spe_fscr); + ppc_maybe_bswap_register(env, buf->data - 4, 4); return 4; } return 0; @@ -9760,11 +9766,11 @@ static int gdb_set_spe_reg(CPUPPCState *env, uint8_t *mem_buf, int n) return 0; } -static int gdb_get_vsx_reg(CPUPPCState *env, uint8_t *mem_buf, int n) +static int gdb_get_vsx_reg(CPUPPCState *env, GByteArray *buf, int n) { if (n < 32) { - stq_p(mem_buf, *cpu_vsrl_ptr(env, n)); - ppc_maybe_bswap_register(env, mem_buf, 8); + gdb_get_reg64(buf, *cpu_vsrl_ptr(env, n)); + ppc_maybe_bswap_register(env, buf->data - 8, 8); return 8; } return 0; diff --git a/target/riscv/gdbstub.c b/target/riscv/gdbstub.c index 1a7947e0198..05442215a4b 100644 --- a/target/riscv/gdbstub.c +++ b/target/riscv/gdbstub.c @@ -269,7 +269,7 @@ static int csr_register_map[] = { CSR_MHCOUNTEREN, }; -int riscv_cpu_gdb_read_register(CPUState *cs, uint8_t *mem_buf, int n) +int riscv_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n) { RISCVCPU *cpu = RISCV_CPU(cs); CPURISCVState *env = &cpu->env; @@ -300,10 +300,10 @@ int riscv_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n) return 0; } -static int riscv_gdb_get_fpu(CPURISCVState *env, uint8_t *mem_buf, int n) +static int riscv_gdb_get_fpu(CPURISCVState *env, GByteArray *buf, int n) { if (n < 32) { - return gdb_get_reg64(mem_buf, env->fpr[n]); + return gdb_get_reg64(buf, env->fpr[n]); /* there is hole between ft11 and fflags in fpu.xml */ } else if (n < 36 && n > 32) { target_ulong val = 0; @@ -316,7 +316,7 @@ static int riscv_gdb_get_fpu(CPURISCVState *env, uint8_t *mem_buf, int n) result = riscv_csrrw_debug(env, n - 33 + csr_register_map[8], &val, 0, 0); if (result == 0) { - return gdb_get_regl(mem_buf, val); + return gdb_get_regl(buf, val); } } return 0; @@ -345,7 +345,7 @@ static int riscv_gdb_set_fpu(CPURISCVState *env, uint8_t *mem_buf, int n) return 0; } -static int riscv_gdb_get_csr(CPURISCVState *env, uint8_t *mem_buf, int n) +static int riscv_gdb_get_csr(CPURISCVState *env, GByteArray *buf, int n) { if (n < ARRAY_SIZE(csr_register_map)) { target_ulong val = 0; @@ -353,7 +353,7 @@ static int riscv_gdb_get_csr(CPURISCVState *env, uint8_t *mem_buf, int n) result = riscv_csrrw_debug(env, csr_register_map[n], &val, 0, 0); if (result == 0) { - return gdb_get_regl(mem_buf, val); + return gdb_get_regl(buf, val); } } return 0; @@ -373,13 +373,13 @@ static int riscv_gdb_set_csr(CPURISCVState *env, uint8_t *mem_buf, int n) return 0; } -static int riscv_gdb_get_virtual(CPURISCVState *cs, uint8_t *mem_buf, int n) +static int riscv_gdb_get_virtual(CPURISCVState *cs, GByteArray *buf, int n) { if (n == 0) { #ifdef CONFIG_USER_ONLY - return gdb_get_regl(mem_buf, 0); + return gdb_get_regl(buf, 0); #else - return gdb_get_regl(mem_buf, cs->priv); + return gdb_get_regl(buf, cs->priv); #endif } return 0; diff --git a/target/s390x/gdbstub.c b/target/s390x/gdbstub.c index e24a49f4a91..d6fce5ff1e1 100644 --- a/target/s390x/gdbstub.c +++ b/target/s390x/gdbstub.c @@ -27,7 +27,7 @@ #include "sysemu/hw_accel.h" #include "sysemu/tcg.h" -int s390_cpu_gdb_read_register(CPUState *cs, uint8_t *mem_buf, int n) +int s390_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n) { S390CPU *cpu = S390_CPU(cs); CPUS390XState *env = &cpu->env; @@ -82,11 +82,11 @@ int s390_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n) /* total number of registers in s390-acr.xml */ #define S390_NUM_AC_REGS 16 -static int cpu_read_ac_reg(CPUS390XState *env, uint8_t *mem_buf, int n) +static int cpu_read_ac_reg(CPUS390XState *env, GByteArray *buf, int n) { switch (n) { case S390_A0_REGNUM ... S390_A15_REGNUM: - return gdb_get_reg32(mem_buf, env->aregs[n]); + return gdb_get_reg32(buf, env->aregs[n]); default: return 0; } @@ -111,13 +111,13 @@ static int cpu_write_ac_reg(CPUS390XState *env, uint8_t *mem_buf, int n) /* total number of registers in s390-fpr.xml */ #define S390_NUM_FP_REGS 17 -static int cpu_read_fp_reg(CPUS390XState *env, uint8_t *mem_buf, int n) +static int cpu_read_fp_reg(CPUS390XState *env, GByteArray *buf, int n) { switch (n) { case S390_FPC_REGNUM: - return gdb_get_reg32(mem_buf, env->fpc); + return gdb_get_reg32(buf, env->fpc); case S390_F0_REGNUM ... S390_F15_REGNUM: - return gdb_get_reg64(mem_buf, *get_freg(env, n - S390_F0_REGNUM)); + return gdb_get_reg64(buf, *get_freg(env, n - S390_F0_REGNUM)); default: return 0; } @@ -145,17 +145,17 @@ static int cpu_write_fp_reg(CPUS390XState *env, uint8_t *mem_buf, int n) /* total number of registers in s390-vx.xml */ #define S390_NUM_VREGS 32 -static int cpu_read_vreg(CPUS390XState *env, uint8_t *mem_buf, int n) +static int cpu_read_vreg(CPUS390XState *env, GByteArray *buf, int n) { int ret; switch (n) { case S390_V0L_REGNUM ... S390_V15L_REGNUM: - ret = gdb_get_reg64(mem_buf, env->vregs[n][1]); + ret = gdb_get_reg64(buf, env->vregs[n][1]); break; case S390_V16_REGNUM ... S390_V31_REGNUM: - ret = gdb_get_reg64(mem_buf, env->vregs[n][0]); - ret += gdb_get_reg64(mem_buf + 8, env->vregs[n][1]); + ret = gdb_get_reg64(buf, env->vregs[n][0]); + ret += gdb_get_reg64(buf, env->vregs[n][1]); break; default: ret = 0; @@ -186,11 +186,11 @@ static int cpu_write_vreg(CPUS390XState *env, uint8_t *mem_buf, int n) #define S390_NUM_C_REGS 16 #ifndef CONFIG_USER_ONLY -static int cpu_read_c_reg(CPUS390XState *env, uint8_t *mem_buf, int n) +static int cpu_read_c_reg(CPUS390XState *env, GByteArray *buf, int n) { switch (n) { case S390_C0_REGNUM ... S390_C15_REGNUM: - return gdb_get_regl(mem_buf, env->cregs[n]); + return gdb_get_regl(buf, env->cregs[n]); default: return 0; } @@ -223,7 +223,7 @@ static int cpu_write_c_reg(CPUS390XState *env, uint8_t *mem_buf, int n) /* total number of registers in s390-virt.xml */ #define S390_NUM_VIRT_REGS 8 -static int cpu_read_virt_reg(CPUS390XState *env, uint8_t *mem_buf, int n) +static int cpu_read_virt_reg(CPUS390XState *env, GByteArray *mem_buf, int n) { switch (n) { case S390_VIRT_CKC_REGNUM: @@ -296,9 +296,9 @@ static int cpu_write_virt_reg(CPUS390XState *env, uint8_t *mem_buf, int n) /* total number of registers in s390-gs.xml */ #define S390_NUM_GS_REGS 4 -static int cpu_read_gs_reg(CPUS390XState *env, uint8_t *mem_buf, int n) +static int cpu_read_gs_reg(CPUS390XState *env, GByteArray *buf, int n) { - return gdb_get_regl(mem_buf, env->gscb[n]); + return gdb_get_regl(buf, env->gscb[n]); } static int cpu_write_gs_reg(CPUS390XState *env, uint8_t *mem_buf, int n) diff --git a/target/sh4/gdbstub.c b/target/sh4/gdbstub.c index 44c1679e9db..49fc4a0cc69 100644 --- a/target/sh4/gdbstub.c +++ b/target/sh4/gdbstub.c @@ -24,7 +24,7 @@ /* Hint: Use "set architecture sh4" in GDB to see fpu registers */ /* FIXME: We should use XML for this. */ -int superh_cpu_gdb_read_register(CPUState *cs, uint8_t *mem_buf, int n) +int superh_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n) { SuperHCPU *cpu = SUPERH_CPU(cs); CPUSH4State *env = &cpu->env; diff --git a/target/sparc/gdbstub.c b/target/sparc/gdbstub.c index 8be742b5a3d..78dc8dcc980 100644 --- a/target/sparc/gdbstub.c +++ b/target/sparc/gdbstub.c @@ -27,7 +27,7 @@ #define gdb_get_rega(buf, val) gdb_get_regl(buf, val) #endif -int sparc_cpu_gdb_read_register(CPUState *cs, uint8_t *mem_buf, int n) +int sparc_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n) { SPARCCPU *cpu = SPARC_CPU(cs); CPUSPARCState *env = &cpu->env; diff --git a/target/xtensa/gdbstub.c b/target/xtensa/gdbstub.c index 54727881f38..0ee3feabe54 100644 --- a/target/xtensa/gdbstub.c +++ b/target/xtensa/gdbstub.c @@ -63,7 +63,7 @@ void xtensa_count_regs(const XtensaConfig *config, } } -int xtensa_cpu_gdb_read_register(CPUState *cs, uint8_t *mem_buf, int n) +int xtensa_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n) { XtensaCPU *cpu = XTENSA_CPU(cs); CPUXtensaState *env = &cpu->env; -- 2.20.1 From MAILER-DAEMON Wed Dec 11 12:11:26 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1if5WI-0003Mi-7r for mharc-qemu-arm@gnu.org; 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Wed, 11 Dec 2019 09:11:13 -0800 (PST) Received: from zen.lan (localhost [127.0.0.1]) by zen.linaroharston (Postfix) with ESMTP id 1420E1FF9D; Wed, 11 Dec 2019 17:05:24 +0000 (GMT) From: =?UTF-8?q?Alex=20Benn=C3=A9e?= To: qemu-devel@nongnu.org Cc: richard.henderson@linaro.org, alan.hayward@arm.com, luis.machado@linaro.org, damien.hedde@greensocs.com, =?UTF-8?q?Alex=20Benn=C3=A9e?= , Peter Maydell , qemu-arm@nongnu.org (open list:ARM TCG CPUs) Subject: [PATCH v3 14/20] target/arm: don't bother with id_aa64pfr0_read for USER_ONLY Date: Wed, 11 Dec 2019 17:05:14 +0000 Message-Id: <20191211170520.7747-15-alex.bennee@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20191211170520.7747-1-alex.bennee@linaro.org> References: <20191211170520.7747-1-alex.bennee@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::444 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 11 Dec 2019 17:11:23 -0000 For system emulation we need to check the state of the GIC before we report the value. However this isn't relevant to exporting of the value to linux-user and indeed breaks the exported value as set by modify_arm_cp_regs. Signed-off-by: Alex Bennée --- v2 - extend the ifdef and make type CONST with no accessfn --- target/arm/helper.c | 20 +++++++++++++++----- 1 file changed, 15 insertions(+), 5 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index b6e1fe51d76..58592c86714 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -5878,6 +5878,7 @@ static uint64_t id_pfr1_read(CPUARMState *env, const ARMCPRegInfo *ri) return pfr1; } +#ifndef CONFIG_USER_ONLY static uint64_t id_aa64pfr0_read(CPUARMState *env, const ARMCPRegInfo *ri) { ARMCPU *cpu = env_archcpu(env); @@ -5888,6 +5889,7 @@ static uint64_t id_aa64pfr0_read(CPUARMState *env, const ARMCPRegInfo *ri) } return pfr0; } +#endif /* Shared logic between LORID and the rest of the LOR* registers. * Secure state has already been delt with. @@ -6308,16 +6310,24 @@ void register_cp_regs_for_features(ARMCPU *cpu) * define new registers here. */ ARMCPRegInfo v8_idregs[] = { - /* ID_AA64PFR0_EL1 is not a plain ARM_CP_CONST because we don't - * know the right value for the GIC field until after we - * define these regs. + /* + * ID_AA64PFR0_EL1 is not a plain ARM_CP_CONST in system + * emulation because we don't know the right value for the + * GIC field until after we define these regs. */ { .name = "ID_AA64PFR0_EL1", .state = ARM_CP_STATE_AA64, .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 0, - .access = PL1_R, .type = ARM_CP_NO_RAW, + .access = PL1_R, +#ifdef CONFIG_USER_ONLY + .type = ARM_CP_CONST, + .resetvalue = cpu->isar.id_aa64pfr0 +#else + .type = ARM_CP_NO_RAW, .accessfn = access_aa64_tid3, .readfn = id_aa64pfr0_read, - .writefn = arm_cp_write_ignore }, + .writefn = arm_cp_write_ignore +#endif + }, { .name = "ID_AA64PFR1_EL1", .state = ARM_CP_STATE_AA64, .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 1, .access = PL1_R, .type = ARM_CP_CONST, -- 2.20.1 From MAILER-DAEMON Wed Dec 11 12:11:28 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1if5WK-0003Q5-OJ for mharc-qemu-arm@gnu.org; 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Wed, 11 Dec 2019 09:11:13 -0800 (PST) Received: from zen.lan (localhost [127.0.0.1]) by zen.linaroharston (Postfix) with ESMTP id 1D0D21FFA6; Wed, 11 Dec 2019 17:05:25 +0000 (GMT) From: =?UTF-8?q?Alex=20Benn=C3=A9e?= To: qemu-devel@nongnu.org Cc: richard.henderson@linaro.org, alan.hayward@arm.com, luis.machado@linaro.org, damien.hedde@greensocs.com, =?UTF-8?q?Alex=20Benn=C3=A9e?= , Peter Maydell , qemu-arm@nongnu.org (open list:ARM TCG CPUs) Subject: [PATCH v3 20/20] tests/tcg/aarch64: add test-sve-ioctl guest-debug test Date: Wed, 11 Dec 2019 17:05:20 +0000 Message-Id: <20191211170520.7747-21-alex.bennee@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20191211170520.7747-1-alex.bennee@linaro.org> References: <20191211170520.7747-1-alex.bennee@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::443 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 11 Dec 2019 17:11:25 -0000 This test exercises the gdbstub while runing the sve-iotcl test. I haven't plubmed it into make system as we need a way of verifying if gdb has the right support for SVE. Signed-off-by: Alex Bennée --- tests/tcg/aarch64/gdbstub/test-sve-ioctl.py | 71 +++++++++++++++++++++ 1 file changed, 71 insertions(+) create mode 100644 tests/tcg/aarch64/gdbstub/test-sve-ioctl.py diff --git a/tests/tcg/aarch64/gdbstub/test-sve-ioctl.py b/tests/tcg/aarch64/gdbstub/test-sve-ioctl.py new file mode 100644 index 00000000000..2c8c21ca381 --- /dev/null +++ b/tests/tcg/aarch64/gdbstub/test-sve-ioctl.py @@ -0,0 +1,71 @@ +from __future__ import print_function +# +# Test the SVE ZReg reports the right amount of data. It uses the +# sve-ioctl test and examines the register data each time the +# __sve_ld_done breakpoint is hit. +# +# This is launched via tests/guest-debug/run-test.py +# + +import gdb + +initial_vlen = 0 +failcount = 0 + +def report(cond, msg): + "Report success/fail of test" + if cond: + print ("PASS: %s" % (msg)) + else: + print ("FAIL: %s" % (msg)) + global failcount + failcount += 1 + +class TestBreakpoint(gdb.Breakpoint): + def __init__(self, sym_name="__sve_ld_done"): + super(TestBreakpoint, self).__init__(sym_name) + # self.sym, ok = gdb.lookup_symbol(sym_name) + + def stop(self): + val_i = gdb.parse_and_eval('i') + global initial_vlen + for i in range(0, int(val_i)): + val_z = gdb.parse_and_eval("$z0.b.u[%d]" % i) + report(int(val_z) == i, "z0.b.u[%d] == %d" % (i, i)) + for i in range(i + 1, initial_vlen): + val_z = gdb.parse_and_eval("$z0.b.u[%d]" % i) + report(int(val_z) == 0, "z0.b.u[%d] == 0" % (i)) + + +def run_test(): + "Run through the tests one by one" + + print ("Setup breakpoint") + bp = TestBreakpoint() + + global initial_vlen + vg = gdb.parse_and_eval("$vg") + initial_vlen = int(vg) * 16 + + gdb.execute("c") + +# +# This runs as the script it sourced (via -x, via run-test.py) +# + +try: + # These are not very useful in scripts + gdb.execute("set pagination off") + gdb.execute("set confirm off") + + # Run the actual tests + run_test() +except: + print ("GDB Exception: %s" % (sys.exc_info()[0])) + failcount += 1 + import code + code.InteractiveConsole(locals=globals()).interact() + raise + +print("All tests complete: %d failures" % failcount) +exit(failcount) -- 2.20.1 From MAILER-DAEMON Wed Dec 11 12:11:29 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1if5WL-0003Qn-7A for mharc-qemu-arm@gnu.org; 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Wed, 11 Dec 2019 09:11:14 -0800 (PST) Received: from zen.lan (localhost [127.0.0.1]) by zen.linaroharston (Postfix) with ESMTP id BF5051FFA3; Wed, 11 Dec 2019 17:05:24 +0000 (GMT) From: =?UTF-8?q?Alex=20Benn=C3=A9e?= To: qemu-devel@nongnu.org Cc: richard.henderson@linaro.org, alan.hayward@arm.com, luis.machado@linaro.org, damien.hedde@greensocs.com, =?UTF-8?q?Alex=20Benn=C3=A9e?= , Peter Maydell , qemu-arm@nongnu.org (open list:ARM TCG CPUs) Subject: [PATCH v3 18/20] tests/tcg/aarch64: add a gdbstub testcase for SVE registers Date: Wed, 11 Dec 2019 17:05:18 +0000 Message-Id: <20191211170520.7747-19-alex.bennee@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20191211170520.7747-1-alex.bennee@linaro.org> References: <20191211170520.7747-1-alex.bennee@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::341 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 11 Dec 2019 17:11:26 -0000 We don't plumb this in yet as there are complications involved with binutils and cross-architectiure debugging but it is one step closer. Example: ./tests/guest-debug/run-test.py \ --qemu ./aarch64-linux-user/qemu-aarch64 \ --qargs "-cpu max" \ --bin ./tests/tcg/aarch64-linux-user/hello \ --test ~/lsrc/qemu.git/tests/tcg/aarch64/gdbstub/test-sve.py \ --gdb /home/alex/src/tools/binutils-gdb.git/install/bin/gdb Signed-off-by: Alex Bennée --- tests/.gitignore | 1 + tests/tcg/aarch64/gdbstub/test-sve.py | 75 +++++++++++++++++++++++++++ 2 files changed, 76 insertions(+) create mode 100644 tests/tcg/aarch64/gdbstub/test-sve.py diff --git a/tests/.gitignore b/tests/.gitignore index f9c01708812..8cc428b58bb 100644 --- a/tests/.gitignore +++ b/tests/.gitignore @@ -10,6 +10,7 @@ qht-bench rcutorture test-* !test-*.c +!test-*.py !docker/test-* test-qapi-commands.[ch] include/test-qapi-commands-sub-module.[ch] diff --git a/tests/tcg/aarch64/gdbstub/test-sve.py b/tests/tcg/aarch64/gdbstub/test-sve.py new file mode 100644 index 00000000000..11bc96fc06d --- /dev/null +++ b/tests/tcg/aarch64/gdbstub/test-sve.py @@ -0,0 +1,75 @@ +from __future__ import print_function +# +# Test the SVE registers are visable and changeable via gdbstub +# +# This is launched via tests/guest-debug/run-test.py +# + +import gdb + +MAGIC = 0xDEADBEEF + +failcount = 0 + +def report(cond, msg): + "Report success/fail of test" + if cond: + print ("PASS: %s" % (msg)) + else: + print ("FAIL: %s" % (msg)) + global failcount + failcount += 1 + +def run_test(): + "Run through the tests one by one" + + gdb.execute("info registers") + report(True, "info registers") + + gdb.execute("info registers vector") + report(True, "info registers vector") + + # Now all the zregs + frame = gdb.selected_frame() + for i in range(0, 32): + rname = "z%d" % (i) + zreg = frame.read_register(rname) + report(True, "Reading %s" % rname) + for j in range(0, 4): + cmd = "set $%s.q.u[%d] = 0x%x" % (rname, j, MAGIC) + gdb.execute(cmd) + report(True, "%s" % cmd) + for j in range(0, 4): + reg = "$%s.q.u[%d]" % (rname, j) + v = gdb.parse_and_eval(reg) + report(str(v.type) == "uint128_t", "size of %s" % (reg)) + for j in range(0, 8): + cmd = "set $%s.d.u[%d] = 0x%x" % (rname, j, MAGIC) + gdb.execute(cmd) + report(True, "%s" % cmd) + for j in range(0, 8): + reg = "$%s.d.u[%d]" % (rname, j) + v = gdb.parse_and_eval(reg) + report(str(v.type) == "uint64_t", "size of %s" % (reg)) + report(int(v) == MAGIC, "%s is 0x%x" % (reg, MAGIC)) + +# +# This runs as the script it sourced (via -x, via run-test.py) +# + +try: + # These are not very useful in scripts + gdb.execute("set pagination off") + gdb.execute("set confirm off") + + # Run the actual tests + run_test() +except: + print ("GDB Exception: %s" % (sys.exc_info()[0])) + failcount += 1 + +print("All tests complete: %d failures" % failcount) + +# Finally kill the inferior and exit gdb with a count of failures +gdb.execute("kill") +exit(failcount) -- 2.20.1 From MAILER-DAEMON Wed Dec 11 12:11:32 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1if5WO-0003Xf-Cf for mharc-qemu-arm@gnu.org; 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Wed, 11 Dec 2019 09:11:12 -0800 (PST) Received: from zen.lan (localhost [127.0.0.1]) by zen.linaroharston (Postfix) with ESMTP id 3F9741FF9E; Wed, 11 Dec 2019 17:05:24 +0000 (GMT) From: =?UTF-8?q?Alex=20Benn=C3=A9e?= To: qemu-devel@nongnu.org Cc: richard.henderson@linaro.org, alan.hayward@arm.com, luis.machado@linaro.org, damien.hedde@greensocs.com, =?UTF-8?q?Alex=20Benn=C3=A9e?= , Peter Maydell , qemu-arm@nongnu.org (open list:ARM TCG CPUs) Subject: [PATCH v3 15/20] tests/tcg/aarch64: userspace system register test Date: Wed, 11 Dec 2019 17:05:15 +0000 Message-Id: <20191211170520.7747-16-alex.bennee@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20191211170520.7747-1-alex.bennee@linaro.org> References: <20191211170520.7747-1-alex.bennee@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::443 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 11 Dec 2019 17:11:24 -0000 This tests a bunch of registers that the kernel allows userspace to read including the CPUID registers. We need a SVE aware compiler as we are testing the id_aa64zfr0_el1 register in the set. Signed-off-by: Alex Bennée Message-Id: <20190205190224.2198-7-alex.bennee@linaro.org> --- vgdbstub - don't build unless using docker or CROSS_CC_HAS_SVE --- tests/tcg/aarch64/sysregs.c | 172 ++++++++++++++++++++++++++++++ tests/tcg/aarch64/Makefile.target | 6 ++ 2 files changed, 178 insertions(+) create mode 100644 tests/tcg/aarch64/sysregs.c diff --git a/tests/tcg/aarch64/sysregs.c b/tests/tcg/aarch64/sysregs.c new file mode 100644 index 00000000000..40cf8d2877e --- /dev/null +++ b/tests/tcg/aarch64/sysregs.c @@ -0,0 +1,172 @@ +/* + * Check emulated system register access for linux-user mode. + * + * See: https://www.kernel.org/doc/Documentation/arm64/cpu-feature-registers.txt + * + * Copyright (c) 2019 Linaro + * + * This work is licensed under the terms of the GNU GPL, version 2 or later. + * See the COPYING file in the top-level directory. + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include +#include +#include +#include +#include +#include + +#ifndef HWCAP_CPUID +#define HWCAP_CPUID (1 << 11) +#endif + +int failed_bit_count; + +/* Read and print system register `id' value */ +#define get_cpu_reg(id) ({ \ + unsigned long __val = 0xdeadbeef; \ + asm("mrs %0, "#id : "=r" (__val)); \ + printf("%-20s: 0x%016lx\n", #id, __val); \ + __val; \ + }) + +/* As above but also check no bits outside of `mask' are set*/ +#define get_cpu_reg_check_mask(id, mask) ({ \ + unsigned long __cval = get_cpu_reg(id); \ + unsigned long __extra = __cval & ~mask; \ + if (__extra) { \ + printf("%-20s: 0x%016lx\n", " !!extra bits!!", __extra); \ + failed_bit_count++; \ + } \ +}) + +/* As above but check RAZ */ +#define get_cpu_reg_check_zero(id) ({ \ + unsigned long __val = 0xdeadbeef; \ + asm("mrs %0, "#id : "=r" (__val)); \ + if (__val) { \ + printf("%-20s: 0x%016lx (not RAZ!)\n", #id, __val); \ + failed_bit_count++; \ + } \ +}) + +/* Chunk up mask into 63:48, 47:32, 31:16, 15:0 to ease counting */ +#define _m(a, b, c, d) (0x ## a ## b ## c ## d ##ULL) + +bool should_fail; +int should_fail_count; +int should_not_fail_count; +uintptr_t failed_pc[10]; + +void sigill_handler(int signo, siginfo_t *si, void *data) +{ + ucontext_t *uc = (ucontext_t *)data; + + if (should_fail) { + should_fail_count++; + } else { + uintptr_t pc = (uintptr_t) uc->uc_mcontext.pc; + failed_pc[should_not_fail_count++] = pc; + } + uc->uc_mcontext.pc += 4; +} + +int main(void) +{ + struct sigaction sa; + + /* Hook in a SIGILL handler */ + memset(&sa, 0, sizeof(struct sigaction)); + sa.sa_flags = SA_SIGINFO; + sa.sa_sigaction = &sigill_handler; + sigemptyset(&sa.sa_mask); + + if (sigaction(SIGILL, &sa, 0) != 0) { + perror("sigaction"); + return 1; + } + + /* Counter values have been exposed since Linux 4.12 */ + printf("Checking Counter registers\n"); + + get_cpu_reg(ctr_el0); + get_cpu_reg(cntvct_el0); + get_cpu_reg(cntfrq_el0); + + /* HWCAP_CPUID indicates we can read feature registers, since Linux 4.11 */ + if (!(getauxval(AT_HWCAP) & HWCAP_CPUID)) { + printf("CPUID registers unavailable\n"); + return 1; + } else { + printf("Checking CPUID registers\n"); + } + + /* + * Some registers only expose some bits to user-space. Anything + * that is IMPDEF is exported as 0 to user-space. The _mask checks + * assert no extra bits are set. + * + * This check is *not* comprehensive as some fields are set to + * minimum valid fields - for the purposes of this check allowed + * to have non-zero values. + */ + get_cpu_reg_check_mask(id_aa64isar0_el1, _m(00ff,ffff,f0ff,fff0)); + get_cpu_reg_check_mask(id_aa64isar1_el1, _m(0000,00f0,ffff,ffff)); + /* TGran4 & TGran64 as pegged to -1 */ + get_cpu_reg_check_mask(id_aa64mmfr0_el1, _m(0000,0000,ff00,0000)); + get_cpu_reg_check_zero(id_aa64mmfr1_el1); + /* EL1/EL0 reported as AA64 only */ + get_cpu_reg_check_mask(id_aa64pfr0_el1, _m(000f,000f,00ff,0011)); + get_cpu_reg_check_mask(id_aa64pfr1_el1, _m(0000,0000,0000,00f0)); + /* all hidden, DebugVer fixed to 0x6 (ARMv8 debug architecture) */ + get_cpu_reg_check_mask(id_aa64dfr0_el1, _m(0000,0000,0000,0006)); + get_cpu_reg_check_zero(id_aa64dfr1_el1); + get_cpu_reg_check_zero(id_aa64zfr0_el1); + + get_cpu_reg_check_zero(id_aa64afr0_el1); + get_cpu_reg_check_zero(id_aa64afr1_el1); + + get_cpu_reg_check_mask(midr_el1, _m(0000,0000,ffff,ffff)); + /* mpidr sets bit 31, everything else hidden */ + get_cpu_reg_check_mask(mpidr_el1, _m(0000,0000,8000,0000)); + /* REVIDR is all IMPDEF so should be all zeros to user-space */ + get_cpu_reg_check_zero(revidr_el1); + + /* + * There are a block of more registers that are RAZ in the rest of + * the Op0=3, Op1=0, CRn=0, CRm=0,4,5,6,7 space. However for + * brevity we don't check stuff that is currently un-allocated + * here. Feel free to add them ;-) + */ + + printf("Remaining registers should fail\n"); + should_fail = true; + + /* Unexposed register access causes SIGILL */ + get_cpu_reg(id_mmfr0_el1); + get_cpu_reg(id_mmfr1_el1); + get_cpu_reg(id_mmfr2_el1); + get_cpu_reg(id_mmfr3_el1); + + get_cpu_reg(mvfr0_el1); + get_cpu_reg(mvfr1_el1); + + if (should_not_fail_count > 0) { + int i; + for (i = 0; i < should_not_fail_count; i++) { + uintptr_t pc = failed_pc[i]; + uint32_t insn = *(uint32_t *) pc; + printf("insn %#x @ %#lx unexpected FAIL\n", insn, pc); + } + return 1; + } + + if (failed_bit_count > 0) { + printf("Extra information leaked to user-space!\n"); + return 1; + } + + return should_fail_count == 6 ? 0 : 1; +} diff --git a/tests/tcg/aarch64/Makefile.target b/tests/tcg/aarch64/Makefile.target index 96d2321045a..3f8783ada5c 100644 --- a/tests/tcg/aarch64/Makefile.target +++ b/tests/tcg/aarch64/Makefile.target @@ -32,4 +32,10 @@ run-plugin-semihosting-with-%: $(call strip-plugin,$<) 2> $<.err, \ "$< on $(TARGET_NAME) with $*") +ifneq ($(DOCKER_IMAGE)$(CROSS_CC_HAS_SVE),) +# System Registers Tests +AARCH64_TESTS += sysregs +sysregs: CFLAGS+=-march=armv8.1-a+sve +endif + TESTS += $(AARCH64_TESTS) -- 2.20.1 From MAILER-DAEMON Wed Dec 11 12:11:32 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1if5WO-0003Y5-KG for mharc-qemu-arm@gnu.org; Wed, 11 Dec 2019 12:11:32 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:53903) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1if5WJ-0003OX-Ji for qemu-arm@nongnu.org; Wed, 11 Dec 2019 12:11:29 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1if5WH-0003OK-B2 for qemu-arm@nongnu.org; Wed, 11 Dec 2019 12:11:27 -0500 Received: from mail-wm1-x343.google.com ([2a00:1450:4864:20::343]:53924) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1if5WF-0003J9-Gt for qemu-arm@nongnu.org; Wed, 11 Dec 2019 12:11:24 -0500 Received: by mail-wm1-x343.google.com with SMTP id n9so7996977wmd.3 for ; Wed, 11 Dec 2019 09:11:23 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=3DbtusU2Ih08QJ6+xacVGyMR/0il0pzTPOprXECSOtU=; b=M0zqe6M9SM8Ozy1ID+t/7xsmeiyM2zAVzW9KcvKsnp4DpywwywM4GPf4WHfN1GR/RP ZR3ZOqPhb2BoBxoYPzuGsJQCIQqpn2O77hMy2FtYm+GofWY3cdxXZU9S6cCLYX3Sl+WW DWaIlYd7MK5lPL5mrYXEtY3arTyYvcHqTrcqoipmlQx+lg7cQ2FMsSthJnP8WJeTFm0X ByHf2uxU0FJSDoiIPvXKCLkrVN9qscYSq0JLXQ/etDea7/ZsSmr38EiFU8AFUsrFF64S rrKFj+Ib83e6dLaw++xGPOoKRqHHp1urOIXVbTXkVnUePPXZB76lCzsRTDnfgsSBavsL mTiA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=3DbtusU2Ih08QJ6+xacVGyMR/0il0pzTPOprXECSOtU=; b=lBVaBgl5uHofjTKBnT6JJg+9THNrYyjrd+6ilyGXCyvtexMfQUh1V3+wXSd0aCpGbj ZKmVDk1v3+tt3Url8D8c395bLXqFkZPzbL1KP5VxYelufxWvf+nN43YfcZNPZ/atieRB 0Ook/I/scVqeHwEdA0x2+IcWeGISHUcbySOYLlueoTOSR08JUl5NU/brBybt0bz4DrCo KXRs2p3h47r5WxBdvKuEaxijP+j7kz9V1uQgEn967TAkJC728wSq3derlabdZtap0ob8 8eLZaKm3KX4PAsQL/Wr4YRNTp56Q6qf7cdt9dzpSR6PBWils7bY9nvq3SE+Kp/CXrTM2 L/vg== X-Gm-Message-State: APjAAAWsES02PXbvrZNQjpXDvklbtaf9H97cgt7FHcw1+EP7AvXlbMAp ohruA6uEsKKibmofZ1I3B4FtAg== X-Google-Smtp-Source: APXvYqzT3duQdKSYZhFNYYyVExycQuv7AgS8iTuJ7bgcdTHnX7wf3K+FirtF0k01WKAue1LtO9J1RQ== X-Received: by 2002:a1c:f009:: with SMTP id a9mr887758wmb.73.1576084281972; Wed, 11 Dec 2019 09:11:21 -0800 (PST) Received: from zen.linaroharston ([51.148.130.216]) by smtp.gmail.com with ESMTPSA id p26sm2955834wmc.24.2019.12.11.09.11.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 11 Dec 2019 09:11:19 -0800 (PST) Received: from zen.lan (localhost [127.0.0.1]) by zen.linaroharston (Postfix) with ESMTP id C98281FF9B; Wed, 11 Dec 2019 17:05:23 +0000 (GMT) From: =?UTF-8?q?Alex=20Benn=C3=A9e?= To: qemu-devel@nongnu.org Cc: richard.henderson@linaro.org, alan.hayward@arm.com, luis.machado@linaro.org, damien.hedde@greensocs.com, =?UTF-8?q?Alex=20Benn=C3=A9e?= , Peter Maydell , qemu-arm@nongnu.org (open list:ARM TCG CPUs) Subject: [PATCH v3 12/20] target/arm: generate xml description of our SVE registers Date: Wed, 11 Dec 2019 17:05:12 +0000 Message-Id: <20191211170520.7747-13-alex.bennee@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20191211170520.7747-1-alex.bennee@linaro.org> References: <20191211170520.7747-1-alex.bennee@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::343 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 11 Dec 2019 17:11:29 -0000 We also expose a the helpers to read/write the the registers. Signed-off-by: Alex Bennée --- v2 - instead of zNpM expose zN at sve_max_vq width - wrap union in union q(us), d(usf), s(usf), h(usf), b(us) v3 - add a vg pseudo register for current width - spacing fixes - use switch/case for whole group - drop fpsr_pos marker - remove unused variables --- target/arm/cpu.h | 7 ++- target/arm/gdbstub.c | 133 +++++++++++++++++++++++++++++++++++++++++++ target/arm/helper.c | 121 ++++++++++++++++++++++++++++++++++++++- 3 files changed, 256 insertions(+), 5 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index cc7258d5f1d..25d34bc5197 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -755,6 +755,7 @@ struct ARMCPU { int32_t cpreg_vmstate_array_len; DynamicGDBXMLInfo dyn_sysreg_xml; + DynamicGDBXMLInfo dyn_svereg_xml; /* Timers used by the generic (architected) timer */ QEMUTimer *gt_timer[NUM_GTIMERS]; @@ -958,10 +959,12 @@ hwaddr arm_cpu_get_phys_page_attrs_debug(CPUState *cpu, vaddr addr, int arm_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); int arm_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); -/* Dynamically generates for gdb stub an XML description of the sysregs from - * the cp_regs hashtable. Returns the registered sysregs number. +/* + * Helpers to dynamically generates XML descriptions of the sysregs + * and SVE registers. Returns the number of registers in each set. */ int arm_gen_dynamic_sysreg_xml(CPUState *cpu, int base_reg); +int arm_gen_dynamic_svereg_xml(CPUState *cpu, int base_reg); /* Returns the dynamically generated XML for the gdb stub. * Returns a pointer to the XML contents for the specified XML file or NULL diff --git a/target/arm/gdbstub.c b/target/arm/gdbstub.c index 69c35462a63..546906dbcb2 100644 --- a/target/arm/gdbstub.c +++ b/target/arm/gdbstub.c @@ -171,12 +171,145 @@ int arm_gen_dynamic_sysreg_xml(CPUState *cs, int base_reg) return cpu->dyn_sysreg_xml.num; } +struct TypeSize { + const char *gdb_type; + int size; + const char sz, suffix; +}; + +static struct TypeSize vec_lanes[] = { + /* quads */ + { "uint128", 128, 'q', 'u' }, + { "int128", 128, 'q', 's' }, + /* 64 bit */ + { "uint64", 64, 'd', 'u' }, + { "int64", 64, 'd', 's' }, + { "ieee_double", 64, 'd', 'f' }, + /* 32 bit */ + { "uint32", 32, 's', 'u' }, + { "int32", 32, 's', 's' }, + { "ieee_single", 32, 's', 'f' }, + /* 16 bit */ + { "uint16", 16, 'h', 'u' }, + { "int16", 16, 'h', 's' }, + { "ieee_half", 16, 'h', 'f' }, + /* bytes */ + { "uint8", 8, 'b', 'u' }, + { "int8", 8, 'b', 's' }, +}; + + +int arm_gen_dynamic_svereg_xml(CPUState *cs, int base_reg) +{ + ARMCPU *cpu = ARM_CPU(cs); + GString *s = g_string_new(NULL); + DynamicGDBXMLInfo *info = &cpu->dyn_svereg_xml; + g_autoptr(GString) ts = g_string_new(""); + int i, bits, reg_width = (cpu->sve_max_vq * 128); + info->num = 0; + g_string_printf(s, ""); + g_string_append_printf(s, ""); + g_string_append_printf(s, ""); + + /* First define types and totals in a whole VL */ + for (i = 0; i < ARRAY_SIZE(vec_lanes); i++) { + int count = reg_width / vec_lanes[i].size; + g_string_printf(ts, "vq%d%c%c", count, + vec_lanes[i].sz, vec_lanes[i].suffix); + g_string_append_printf(s, + "", + ts->str, vec_lanes[i].gdb_type, count); + } + /* + * Now define a union for each size group containing unsigned and + * signed and potentially float versions of each size from 128 to + * 8 bits. + */ + for (bits = 128; bits >= 8; bits /= 2) { + int count = reg_width / bits; + g_string_append_printf(s, "", count); + for (i = 0; i < ARRAY_SIZE(vec_lanes); i++) { + if (vec_lanes[i].size == bits) { + g_string_append_printf(s, "", + vec_lanes[i].suffix, + count, + vec_lanes[i].sz, vec_lanes[i].suffix); + } + } + g_string_append(s, ""); + } + /* And now the final union of unions */ + g_string_append(s, ""); + for (bits = 128; bits >= 8; bits /= 2) { + int count = reg_width / bits; + for (i = 0; i < ARRAY_SIZE(vec_lanes); i++) { + if (vec_lanes[i].size == bits) { + g_string_append_printf(s, "", + vec_lanes[i].sz, count); + break; + } + } + } + g_string_append(s, ""); + + /* Then define each register in parts for each vq */ + for (i = 0; i < 32; i++) { + g_string_append_printf(s, + "", + i, reg_width, base_reg++); + info->num++; + } + /* fpscr & status registers */ + g_string_append_printf(s, "", base_reg++); + g_string_append_printf(s, "", base_reg++); + info->num += 2; + /* + * Predicate registers aren't so big they are worth splitting up + * but we do need to define a type to hold the array of quad + * references. + */ + g_string_append_printf(s, + "", + cpu->sve_max_vq); + for (i = 0; i < 16; i++) { + g_string_append_printf(s, + "", + i, cpu->sve_max_vq * 16, base_reg++); + info->num++; + } + g_string_append_printf(s, + "", + cpu->sve_max_vq * 16, base_reg++); + g_string_append_printf(s, + "", base_reg++); + info->num += 2; + g_string_append_printf(s, ""); + cpu->dyn_svereg_xml.desc = g_string_free(s, false); + + return cpu->dyn_svereg_xml.num; +} + + const char *arm_gdb_get_dynamic_xml(CPUState *cs, const char *xmlname) { ARMCPU *cpu = ARM_CPU(cs); if (strcmp(xmlname, "system-registers.xml") == 0) { return cpu->dyn_sysreg_xml.desc; + } else if (strcmp(xmlname, "sve-registers.xml") == 0) { + return cpu->dyn_svereg_xml.desc; } return NULL; } diff --git a/target/arm/helper.c b/target/arm/helper.c index d00e4fcca86..b6e1fe51d76 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -201,6 +201,15 @@ static void write_raw_cp_reg(CPUARMState *env, const ARMCPRegInfo *ri, } } +/** + * arm_get/set_gdb_*: get/set a gdb register + * @env: the CPU state + * @buf: a buffer to copy to/from + * @reg: register number (offset from start of group) + * + * We return the number of bytes copied + */ + static int arm_gdb_get_sysreg(CPUARMState *env, GByteArray *buf, int reg) { ARMCPU *cpu = env_archcpu(env); @@ -224,6 +233,98 @@ static int arm_gdb_set_sysreg(CPUARMState *env, uint8_t *buf, int reg) return 0; } +#ifdef TARGET_AARCH64 +static int arm_gdb_get_svereg(CPUARMState *env, GByteArray *buf, int reg) +{ + ARMCPU *cpu = env_archcpu(env); + + switch (reg) { + /* The first 32 registers are the zregs */ + case 0 ... 31: + { + int vq, len = 0; + for (vq = 0; vq < cpu->sve_max_vq; vq++) { + len += gdb_get_reg128(buf, + env->vfp.zregs[reg].d[vq * 2 + 1], + env->vfp.zregs[reg].d[vq * 2]); + } + return len; + } + case 32: + return gdb_get_reg32(buf, vfp_get_fpsr(env)); + case 33: + return gdb_get_reg32(buf, vfp_get_fpcr(env)); + /* then 16 predicates and the ffr */ + case 34 ... 50: + { + int preg = reg - 34; + int vq, len = 0; + for (vq = 0; vq < cpu->sve_max_vq; vq = vq + 4) { + len += gdb_get_reg64(buf, env->vfp.pregs[preg].p[vq / 4]); + } + return len; + } + case 51: + return gdb_get_reg64(buf, (cpu->env.vfp.zcr_el[1] & 0xf) + 1); + default: + /* gdbstub asked for something out our range */ + qemu_log_mask(LOG_UNIMP, "%s: out of range register %d", __func__, reg); + break; + } + + return 0; +} + +static int arm_gdb_set_svereg(CPUARMState *env, uint8_t *buf, int reg) +{ + ARMCPU *cpu = env_archcpu(env); + + /* The first 32 registers are the zregs */ + switch (reg) { + /* The first 32 registers are the zregs */ + case 0 ... 31: + { + int vq, len = 0; + uint64_t *p = (uint64_t *) buf; + for (vq = 0; vq < cpu->sve_max_vq; vq++) { + env->vfp.zregs[reg].d[vq * 2 + 1] = *p++; + env->vfp.zregs[reg].d[vq * 2] = *p++; + len += 16; + } + return len; + } + case 32: + vfp_set_fpsr(env, *(uint32_t *)buf); + return 4; + case 33: + vfp_set_fpcr(env, *(uint32_t *)buf); + return 4; + case 34 ... 50: + { + int preg = reg - 34; + int vq, len = 0; + uint64_t *p = (uint64_t *) buf; + for (vq = 0; vq < cpu->sve_max_vq; vq = vq + 4) { + env->vfp.pregs[preg].p[vq / 4] = *p++; + len += 8; + } + return len; + } + case 51: + { + uint64_t val = *(uint64_t *) buf; + cpu->env.vfp.zcr_el[1] = (val - 1) & 0xf; + return 8; + } + default: + /* gdbstub asked for something out our range */ + break; + } + + return 0; +} +#endif /* TARGET_AARCH64 */ + static bool raw_accessors_invalid(const ARMCPRegInfo *ri) { /* Return true if the regdef would cause an assertion if you called @@ -6981,9 +7082,22 @@ void arm_cpu_register_gdb_regs_for_features(ARMCPU *cpu) CPUARMState *env = &cpu->env; if (arm_feature(env, ARM_FEATURE_AARCH64)) { - gdb_register_coprocessor(cs, aarch64_fpu_gdb_get_reg, - aarch64_fpu_gdb_set_reg, - 34, "aarch64-fpu.xml", 0); + /* + * The lower part of each SVE register aliases to the FPU + * registers so we don't need to include both. + */ +#ifdef TARGET_AARCH64 + if (isar_feature_aa64_sve(&cpu->isar)) { + gdb_register_coprocessor(cs, arm_gdb_get_svereg, arm_gdb_set_svereg, + arm_gen_dynamic_svereg_xml(cs, cs->gdb_num_regs), + "sve-registers.xml", 0); + } else +#endif + { + gdb_register_coprocessor(cs, aarch64_fpu_gdb_get_reg, + aarch64_fpu_gdb_set_reg, + 34, "aarch64-fpu.xml", 0); + } } else if (arm_feature(env, ARM_FEATURE_NEON)) { gdb_register_coprocessor(cs, vfp_gdb_get_reg, vfp_gdb_set_reg, 51, "arm-neon.xml", 0); @@ -6997,6 +7111,7 @@ void arm_cpu_register_gdb_regs_for_features(ARMCPU *cpu) gdb_register_coprocessor(cs, arm_gdb_get_sysreg, arm_gdb_set_sysreg, arm_gen_dynamic_sysreg_xml(cs, cs->gdb_num_regs), "system-registers.xml", 0); + } /* Sort alphabetically by type name, except for "any". */ -- 2.20.1 From MAILER-DAEMON Wed Dec 11 13:32:10 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1if6mQ-0001zm-KM for mharc-qemu-arm@gnu.org; Wed, 11 Dec 2019 13:32:10 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:35766) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1if6mN-0001zf-9w for qemu-arm@nongnu.org; Wed, 11 Dec 2019 13:32:09 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1if6mK-0000xw-Vi for qemu-arm@nongnu.org; Wed, 11 Dec 2019 13:32:06 -0500 Received: from beetle.greensocs.com ([5.135.226.135]:53956) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1if6mK-0000vg-CS; Wed, 11 Dec 2019 13:32:04 -0500 Received: from [172.16.11.102] (crumble.bar.greensocs.com [172.16.11.102]) by beetle.greensocs.com (Postfix) with ESMTPSA id 300BF96EF0; Wed, 11 Dec 2019 18:32:00 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=greensocs.com; s=mail; t=1576089121; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=mQ5xyVW08Yw0tiMnTbHBQxwUQsPAL+SLR0RjCN/xVwQ=; b=fAl0Y54H0WvabByUlsIUS+w7FlVJ5wnWmaPKFYP6B9IJyDLtaPdF1nDzKfZ0fXDPHqHjmN yYZKskzRQCnD5AvqmXGgIcSOX0hgc8uKv4aIxM8mwB2wB85bEhPkIhd6d46sKvIWDewdAh 7eLhssqavBHsko38WYhL2ta0EgKkozs= Subject: Re: [PATCH v3 08/20] gdbstub: extend GByteArray to read register helpers To: =?UTF-8?Q?Alex_Benn=c3=a9e?= , qemu-devel@nongnu.org Cc: richard.henderson@linaro.org, alan.hayward@arm.com, luis.machado@linaro.org, =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= , Eduardo Habkost , Marcel Apfelbaum , Richard Henderson , Peter Maydell , "Edgar E. Iglesias" , Paolo Bonzini , Michael Walle , Laurent Vivier , Aurelien Jarno , Aleksandar Markovic , Aleksandar Rikalo , Chris Wulff , Marek Vasut , Stafford Horne , David Gibson , Palmer Dabbelt , Alistair Francis , Sagar Karandikar , Bastian Koppelmann , David Hildenbrand , Cornelia Huck , Mark Cave-Ayland , Artyom Tarasenko , Max Filippov , "open list:ARM TCG CPUs" , "open list:PowerPC TCG CPUs" , "open list:RISC-V TCG CPUs" , "open list:S390 TCG CPUs" References: <20191211170520.7747-1-alex.bennee@linaro.org> <20191211170520.7747-9-alex.bennee@linaro.org> From: Damien Hedde Message-ID: Date: Wed, 11 Dec 2019 19:31:59 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.2.0 MIME-Version: 1.0 In-Reply-To: <20191211170520.7747-9-alex.bennee@linaro.org> Content-Type: text/plain; charset=utf-8 Content-Language: en-US-large ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=greensocs.com; s=mail; t=1576089121; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=mQ5xyVW08Yw0tiMnTbHBQxwUQsPAL+SLR0RjCN/xVwQ=; b=QWFzz8Xc8qssztDzulzl2qUg/Y2Hi3b+740Hj8v5WC7oYh1MVWDFq9M86v9ZfrVFwJ9tFR y3TcCJ8illJ7PbaWhQqvEG6BLU+/Rvec8D0lkx0m9OjRljRSApaCqFsVVNBg46viyjQY4O gW2UoLQW/+EjMSGHrOvGYbBXqfLImMM= ARC-Seal: i=1; s=mail; d=greensocs.com; t=1576089121; a=rsa-sha256; cv=none; b=AdJvTldr38lAKee51wr23drslH+ZiFf69ixXo+bZmkc2IjO+Zts7XspKqv1O1VaoZ7qC+M mBHDotNTEDcdIEctLayxnBt8LgdnrzSdWB63rlOqQENmprqqzK+YeY+gyknZpKZ5U9sWzz /hxW4+LBQmnBHJOLPq26xZHVOC55fJc= ARC-Authentication-Results: i=1; ORIGINATING; auth=pass smtp.auth=damien smtp.mailfrom=damien.hedde@greensocs.com Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 5.135.226.135 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 11 Dec 2019 18:32:09 -0000 Hi Alex, On 12/11/19 6:05 PM, Alex Benn=C3=A9e wrote: > Instead of passing a pointer to memory now just extend the GByteArray > to all the read register helpers. They can then safely append their > data through the normal way. We don't bother with this abstraction for > write registers as we have already ensured the buffer being copied > from is the correct size. >=20 > Signed-off-by: Alex Benn=C3=A9e [...] > diff --git a/target/arm/helper.c b/target/arm/helper.c > index 0ac950d6c71..6476245e789 100644 > --- a/target/arm/helper.c > +++ b/target/arm/helper.c > @@ -47,30 +47,27 @@ static bool get_phys_addr_lpae(CPUARMState *env, ta= rget_ulong address, > =20 > static void switch_mode(CPUARMState *env, int mode); > =20 > -static int vfp_gdb_get_reg(CPUARMState *env, uint8_t *buf, int reg) > +static int vfp_gdb_get_reg(CPUARMState *env, GByteArray *buf, int reg) > { > int nregs; > =20 > /* VFP data registers are always little-endian. */ > nregs =3D arm_feature(env, ARM_FEATURE_VFP3) ? 32 : 16; > if (reg < nregs) { > - stq_le_p(buf, *aa32_vfp_dreg(env, reg)); > - return 8; > + return gdb_get_reg64(buf, *aa32_vfp_dreg(env, reg)); It was a little-endian version, you've put a target-endian version. Is that what you meant ? > } > if (arm_feature(env, ARM_FEATURE_NEON)) { > /* Aliases for Q regs. */ > nregs +=3D 16; > if (reg < nregs) { > uint64_t *q =3D aa32_vfp_qreg(env, reg - 32); > - stq_le_p(buf, q[0]); > - stq_le_p(buf + 8, q[1]); > - return 16; > + return gdb_get_reg128(buf, q[0], q[1]); Ditto here. > } > } > switch (reg - nregs) { > - case 0: stl_p(buf, env->vfp.xregs[ARM_VFP_FPSID]); return 4; > - case 1: stl_p(buf, vfp_get_fpscr(env)); return 4; > - case 2: stl_p(buf, env->vfp.xregs[ARM_VFP_FPEXC]); return 4; > + case 0: return gdb_get_reg32(buf, env->vfp.xregs[ARM_VFP_FPSID]); = break; > + case 1: return gdb_get_reg32(buf, vfp_get_fpscr(env)); break; > + case 2: return gdb_get_reg32(buf, env->vfp.xregs[ARM_VFP_FPEXC]); = break; > } > return 0; > } > @@ -101,7 +98,7 @@ static int vfp_gdb_set_reg(CPUARMState *env, uint8_t= *buf, int reg) > return 0; > } > =20 > -static int aarch64_fpu_gdb_get_reg(CPUARMState *env, uint8_t *buf, int= reg) > +static int aarch64_fpu_gdb_get_reg(CPUARMState *env, GByteArray *buf, = int reg) > { > switch (reg) { > case 0 ... 31: > @@ -204,7 +201,7 @@ static void write_raw_cp_reg(CPUARMState *env, cons= t ARMCPRegInfo *ri, > } > } > =20 > -static int arm_gdb_get_sysreg(CPUARMState *env, uint8_t *buf, int reg) > +static int arm_gdb_get_sysreg(CPUARMState *env, GByteArray *buf, int r= eg) > { > ARMCPU *cpu =3D env_archcpu(env); > const ARMCPRegInfo *ri; [...] > diff --git a/target/ppc/gdbstub.c b/target/ppc/gdbstub.c > index 823759c92e7..6f08021cc22 100644 > --- a/target/ppc/gdbstub.c > +++ b/target/ppc/gdbstub.c > @@ -114,10 +114,11 @@ void ppc_maybe_bswap_register(CPUPPCState *env, u= int8_t *mem_buf, int len) > * the FP regs zero size when talking to a newer gdb. > */ > =20 > -int ppc_cpu_gdb_read_register(CPUState *cs, uint8_t *mem_buf, int n) > +int ppc_cpu_gdb_read_register(CPUState *cs, GByteArray *buf, int n) > { > PowerPCCPU *cpu =3D POWERPC_CPU(cs); > CPUPPCState *env =3D &cpu->env; > + uint8_t *mem_buf; > int r =3D ppc_gdb_register_len(n); > =20 > if (!r) { > @@ -126,17 +127,17 @@ int ppc_cpu_gdb_read_register(CPUState *cs, uint8= _t *mem_buf, int n) > =20 > if (n < 32) { > /* gprs */ > - gdb_get_regl(mem_buf, env->gpr[n]); > + gdb_get_regl(buf, env->gpr[n]); > } else if (n < 64) { > /* fprs */ > - stfq_p(mem_buf, *cpu_fpr_ptr(env, n - 32)); > + gdb_get_reg64(buf, *cpu_fpr_ptr(env, n - 32)); > } else { > switch (n) { > case 64: > - gdb_get_regl(mem_buf, env->nip); > + gdb_get_regl(buf, env->nip); > break; > case 65: > - gdb_get_regl(mem_buf, env->msr); > + gdb_get_regl(buf, env->msr); > break; > case 66: > { > @@ -145,31 +146,33 @@ int ppc_cpu_gdb_read_register(CPUState *cs, uint8= _t *mem_buf, int n) > for (i =3D 0; i < 8; i++) { > cr |=3D env->crf[i] << (32 - ((i + 1) * 4)); > } > - gdb_get_reg32(mem_buf, cr); > + gdb_get_reg32(buf, cr); > break; > } > case 67: > - gdb_get_regl(mem_buf, env->lr); > + gdb_get_regl(buf, env->lr); > break; > case 68: > - gdb_get_regl(mem_buf, env->ctr); > + gdb_get_regl(buf, env->ctr); > break; > case 69: > - gdb_get_reg32(mem_buf, env->xer); > + gdb_get_reg32(buf, env->xer); > break; > case 70: > - gdb_get_reg32(mem_buf, env->fpscr); > + gdb_get_reg32(buf, env->fpscr); > break; > } > } > + mem_buf =3D buf->data - r; Should it not be something more like this ? mem_buf =3D buf->data + buf->len - r; There seem to be the same issue below for every ppc_maybe_bswap_register() call. > ppc_maybe_bswap_register(env, mem_buf, r); > return r; > } > =20 > -int ppc_cpu_gdb_read_register_apple(CPUState *cs, uint8_t *mem_buf, in= t n) > +int ppc_cpu_gdb_read_register_apple(CPUState *cs, GByteArray *buf, int= n) > { > PowerPCCPU *cpu =3D POWERPC_CPU(cs); > CPUPPCState *env =3D &cpu->env; > + uint8_t *mem_buf; > int r =3D ppc_gdb_register_len_apple(n); > =20 > if (!r) { > @@ -178,21 +181,21 @@ int ppc_cpu_gdb_read_register_apple(CPUState *cs,= uint8_t *mem_buf, int n) > =20 > if (n < 32) { > /* gprs */ > - gdb_get_reg64(mem_buf, env->gpr[n]); > + gdb_get_reg64(buf, env->gpr[n]); > } else if (n < 64) { > /* fprs */ > - stfq_p(mem_buf, *cpu_fpr_ptr(env, n - 32)); > + gdb_get_reg64(buf, *cpu_fpr_ptr(env, n - 32)); > } else if (n < 96) { > /* Altivec */ > - stq_p(mem_buf, n - 64); > - stq_p(mem_buf + 8, 0); > + gdb_get_reg64(buf, n - 64); > + gdb_get_reg64(buf, 0); > } else { > switch (n) { > case 64 + 32: > - gdb_get_reg64(mem_buf, env->nip); > + gdb_get_reg64(buf, env->nip); > break; > case 65 + 32: > - gdb_get_reg64(mem_buf, env->msr); > + gdb_get_reg64(buf, env->msr); > break; > case 66 + 32: > { > @@ -201,23 +204,24 @@ int ppc_cpu_gdb_read_register_apple(CPUState *cs,= uint8_t *mem_buf, int n) > for (i =3D 0; i < 8; i++) { > cr |=3D env->crf[i] << (32 - ((i + 1) * 4)); > } > - gdb_get_reg32(mem_buf, cr); > + gdb_get_reg32(buf, cr); > break; > } > case 67 + 32: > - gdb_get_reg64(mem_buf, env->lr); > + gdb_get_reg64(buf, env->lr); > break; > case 68 + 32: > - gdb_get_reg64(mem_buf, env->ctr); > + gdb_get_reg64(buf, env->ctr); > break; > case 69 + 32: > - gdb_get_reg32(mem_buf, env->xer); > + gdb_get_reg32(buf, env->xer); > break; > case 70 + 32: > - gdb_get_reg64(mem_buf, env->fpscr); > + gdb_get_reg64(buf, env->fpscr); > break; > } > } > + mem_buf =3D buf->data - r; > ppc_maybe_bswap_register(env, mem_buf, r); > return r; > } > diff --git a/target/ppc/translate_init.inc.c b/target/ppc/translate_ini= t.inc.c > index ba726dec4d0..154f876e44c 100644 > --- a/target/ppc/translate_init.inc.c > +++ b/target/ppc/translate_init.inc.c > @@ -9587,7 +9587,7 @@ static int gdb_find_spr_idx(CPUPPCState *env, int= n) > return -1; > } > =20 > -static int gdb_get_spr_reg(CPUPPCState *env, uint8_t *mem_buf, int n) > +static int gdb_get_spr_reg(CPUPPCState *env, GByteArray *buf, int n) > { > int reg; > int len; > @@ -9598,8 +9598,8 @@ static int gdb_get_spr_reg(CPUPPCState *env, uint= 8_t *mem_buf, int n) > } > =20 > len =3D TARGET_LONG_SIZE; > - stn_p(mem_buf, len, env->spr[reg]); > - ppc_maybe_bswap_register(env, mem_buf, len); > + gdb_get_regl(buf, env->spr[reg]); > + ppc_maybe_bswap_register(env, buf->data - len, len); > return len; > } > =20 > @@ -9621,15 +9621,18 @@ static int gdb_set_spr_reg(CPUPPCState *env, ui= nt8_t *mem_buf, int n) > } > #endif > =20 > -static int gdb_get_float_reg(CPUPPCState *env, uint8_t *mem_buf, int n= ) > +static int gdb_get_float_reg(CPUPPCState *env, GByteArray *buf, int n) > { > + uint8_t *mem_buf; > if (n < 32) { > - stfq_p(mem_buf, *cpu_fpr_ptr(env, n)); > + gdb_get_reg64(buf, *cpu_fpr_ptr(env, n)); > + mem_buf =3D buf->data - 8; > ppc_maybe_bswap_register(env, mem_buf, 8); > return 8; > } > if (n =3D=3D 32) { > - stl_p(mem_buf, env->fpscr); > + gdb_get_reg32(buf, env->fpscr); > + mem_buf =3D buf->data - 4; > ppc_maybe_bswap_register(env, mem_buf, 4); > return 4; > } > @@ -9651,28 +9654,31 @@ static int gdb_set_float_reg(CPUPPCState *env, = uint8_t *mem_buf, int n) > return 0; > } > =20 > -static int gdb_get_avr_reg(CPUPPCState *env, uint8_t *mem_buf, int n) > +static int gdb_get_avr_reg(CPUPPCState *env, GByteArray *buf, int n) > { > + uint8_t *mem_buf; > + > if (n < 32) { > ppc_avr_t *avr =3D cpu_avr_ptr(env, n); > if (!avr_need_swap(env)) { > - stq_p(mem_buf, avr->u64[0]); > - stq_p(mem_buf + 8, avr->u64[1]); > + gdb_get_reg128(buf, avr->u64[0] , avr->u64[1]); > } else { > - stq_p(mem_buf, avr->u64[1]); > - stq_p(mem_buf + 8, avr->u64[0]); > + gdb_get_reg128(buf, avr->u64[1] , avr->u64[0]); > } > + mem_buf =3D buf->data - 16; > ppc_maybe_bswap_register(env, mem_buf, 8); > ppc_maybe_bswap_register(env, mem_buf + 8, 8); > return 16; > } > if (n =3D=3D 32) { > - stl_p(mem_buf, helper_mfvscr(env)); > + gdb_get_reg32(buf, helper_mfvscr(env)); > + mem_buf =3D buf->data - 4; > ppc_maybe_bswap_register(env, mem_buf, 4);> return 4; > } > if (n =3D=3D 33) { > - stl_p(mem_buf, (uint32_t)env->spr[SPR_VRSAVE]); > + gdb_get_reg32(buf, (uint32_t)env->spr[SPR_VRSAVE]); > + mem_buf =3D buf->data - 4; > ppc_maybe_bswap_register(env, mem_buf, 4); > return 4; > } > @@ -9707,25 +9713,25 @@ static int gdb_set_avr_reg(CPUPPCState *env, ui= nt8_t *mem_buf, int n) > return 0; > } > =20 > -static int gdb_get_spe_reg(CPUPPCState *env, uint8_t *mem_buf, int n) > +static int gdb_get_spe_reg(CPUPPCState *env, GByteArray *buf, int n) > { > if (n < 32) { > #if defined(TARGET_PPC64) > - stl_p(mem_buf, env->gpr[n] >> 32); > - ppc_maybe_bswap_register(env, mem_buf, 4); > + gdb_get_reg32(buf, env->gpr[n] >> 32); > + ppc_maybe_bswap_register(env, buf->data - 4, 4); > #else > - stl_p(mem_buf, env->gprh[n]); > + gdb_get_reg32(buf, env->gprh[n]); > #endif > return 4; > } > if (n =3D=3D 32) { > - stq_p(mem_buf, env->spe_acc); > - ppc_maybe_bswap_register(env, mem_buf, 8); > + gdb_get_reg64(buf, env->spe_acc); > + ppc_maybe_bswap_register(env, buf->data - 8, 8); > return 8; > } > if (n =3D=3D 33) { > - stl_p(mem_buf, env->spe_fscr); > - ppc_maybe_bswap_register(env, mem_buf, 4); > + gdb_get_reg32(buf, env->spe_fscr); > + ppc_maybe_bswap_register(env, buf->data - 4, 4); > return 4; > } > return 0; > @@ -9760,11 +9766,11 @@ static int gdb_set_spe_reg(CPUPPCState *env, ui= nt8_t *mem_buf, int n) > return 0; > } > =20 > -static int gdb_get_vsx_reg(CPUPPCState *env, uint8_t *mem_buf, int n) > +static int gdb_get_vsx_reg(CPUPPCState *env, GByteArray *buf, int n) > { > if (n < 32) { > - stq_p(mem_buf, *cpu_vsrl_ptr(env, n)); > - ppc_maybe_bswap_register(env, mem_buf, 8); > + gdb_get_reg64(buf, *cpu_vsrl_ptr(env, n)); > + ppc_maybe_bswap_register(env, buf->data - 8, 8); > return 8; > } > return 0; Otherwise, other files seem ok. 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[79.181.48.215]) by smtp.gmail.com with ESMTPSA id e2sm1017385qkb.112.2019.12.11.12.40.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 11 Dec 2019 12:41:03 -0800 (PST) Date: Wed, 11 Dec 2019 15:40:56 -0500 From: "Michael S. Tsirkin" To: Auger Eric Cc: yang.zhong@intel.com, peter.maydell@linaro.org, kevin.tian@intel.com, tnowicki@marvell.com, quintela@redhat.com, jean-philippe.brucker@arm.com, qemu-devel@nongnu.org, peterx@redhat.com, armbru@redhat.com, bharatb.linux@gmail.com, qemu-arm@nongnu.org, dgilbert@redhat.com, eric.auger.pro@gmail.com Subject: Re: [PATCH for-5.0 v11 00/20] VIRTIO-IOMMU device Message-ID: <20191211154027-mutt-send-email-mst@kernel.org> References: <20191122182943.4656-1-eric.auger@redhat.com> <20191211113936-mutt-send-email-mst@kernel.org> <306e4e92-4e86-7a82-3777-fd85ffd0303c@redhat.com> MIME-Version: 1.0 In-Reply-To: <306e4e92-4e86-7a82-3777-fd85ffd0303c@redhat.com> X-MC-Unique: iNHDmvOxPEaP9qbisYybzQ-1 X-Mimecast-Spam-Score: 0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: quoted-printable Content-Disposition: inline X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 205.139.110.61 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 11 Dec 2019 20:41:15 -0000 On Wed, Dec 11, 2019 at 05:48:05PM +0100, Auger Eric wrote: > Hi Michael, >=20 > On 12/11/19 5:40 PM, Michael S. Tsirkin wrote: > > On Fri, Nov 22, 2019 at 07:29:23PM +0100, Eric Auger wrote: > >> This series implements the QEMU virtio-iommu device. > >> > >> This matches the v0.12 spec and the corresponding virtio-iommu > >> driver upstreamed in 5.3. > >> > >> The pci proxy for the virtio-iommu device is instantiated using > >> "-device virtio-iommu-pci". This series still relies on ACPI IORT/DT > >> integration. Note the ACPI IORT integration is not yet upstreamed > >> and testing needs to be based on Jean-Philippe's additional > >> kernel patches [1]. > >=20 > > Or the config space approach? I really liked that one. > Yes this corresponds to the paragraph below. > >=20 > >> > >> Work is ongoing to remove IORT adherence and allow the > >> bindings between the IOMMU and the root complex to be defined > >> and written into the PCI device configuration space. The outcome > >> of this work is uncertain at this stage though. See [2]. Oh right. Why is it uncertain? Anything can be done to help? > Thanks >=20 > Eric >=20 > >> > >> So only patches 1-11 fully rely on upstreamed kernel code. Others > >> should be considered as RFC. > >> > >> This respin allows people to test on ARM and x86. It also > >> brings migration support (tested on ARM) and various cleanups. > >> Reserved regions are now passed through an array of properties. > >> A libqos test also is introduced to test the virtio-iommu API. > >> > >> Note integration with vhost devices and vfio devices is not part > >> of this series. Please follow Bharat's respins [3]. > >> > >> The 1st Patch ("migration: Support QLIST migration") was sent > >> separately [4]. > >> > >> Best Regards > >> > >> Eric > >> > >> This series can be found at: > >> https://github.com/eauger/qemu/tree/v4.2-rc2-virtio-iommu-v11 > >> > >> [1] kernel branch to be used for guest > >> https://github.com/eauger/linux/tree/v5.4-rc8-virtio-iommu-iort > >> [2] [RFC 00/13] virtio-iommu on non-devicetree platforms > >> [3] VFIO/VHOST integration is not part of this series. Please follow > >> [PATCH RFC v5 0/5] virtio-iommu: VFIO integration respins > >> [4] [PATCH v6] migration: Support QLIST migration > >> > >> Testing: > >> - tested with guest using virtio-net-pci > >> (,vhost=3Doff,iommu_platform,disable-modern=3Doff,disable-legacy=3Do= n) > >> and virtio-blk-pci > >> - migration on ARM > >> - on x86 PC machine I get some AHCI non translated transactions, > >> very early. This does not prevent the guest from boot and behaving > >> properly. Warnings look like: > >> qemu-system-x86_64: virtio_iommu_translate sid=3D250 is not known!! > >> qemu-system-x86_64: no buffer available in event queue to report event > >> qemu-system-x86_64: AHCI: Failed to start FIS receive engine: bad FIS > >> receive buffer address > >> > >> History: > >> > >> v10 -> v11: > >> - introduce virtio_iommu_handle_req macro > >> - migration support > >> - introduce DEFINE_PROP_INTERVAL and pass reserved regions > >> through an array of those > >> - domain gtree simplification > >> > >> v9 -> v10: > >> - rebase on 4.1.0-rc2, compliance with 0.12 spec > >> - removed ACPI part > >> - cleanup (see individual change logs) > >> - moved to a PATCH series > >> > >> v8 -> v9: > >> - virtio-iommu-pci device needs to be instantiated from the command > >> line (RID is not imposed anymore). > >> - tail structure properly initialized > >> > >> v7 -> v8: > >> - virtio-iommu-pci added > >> - virt instantiation modified > >> - DT and ACPI modified to exclude the iommu RID from the mapping > >> - VIRTIO_IOMMU_F_BYPASS, VIRTIO_F_VERSION_1 features exposed > >> > >> v6 -> v7: > >> - rebase on qemu 3.0.0-rc3 > >> - minor update against v0.7 > >> - fix issue with EP not on pci.0 and ACPI probing > >> - change the instantiation method > >> > >> v5 -> v6: > >> - minor update against v0.6 spec > >> - fix g_hash_table_lookup in virtio_iommu_find_add_as > >> - replace some error_reports by qemu_log_mask(LOG_GUEST_ERROR, ...) > >> > >> v4 -> v5: > >> - event queue and fault reporting > >> - we now return the IOAPIC MSI region if the virtio-iommu is instantia= ted > >> in a PC machine. > >> - we bypass transactions on MSI HW region and fault on reserved ones. > >> - We support ACPI boot with mach-virt (based on IORT proposal) > >> - We moved to the new driver naming conventions > >> - simplified mach-virt instantiation > >> - worked around the disappearing of pci_find_primary_bus > >> - in virtio_iommu_translate, check the dev->as is not NULL > >> - initialize as->device_list in virtio_iommu_get_as > >> - initialize bufstate.error to false in virtio_iommu_probe > >> > >> v3 -> v4: > >> - probe request support although no reserved region is returned at > >> the moment > >> - unmap semantics less strict, as specified in v0.4 > >> - device registration, attach/detach revisited > >> - split into smaller patches to ease review > >> - propose a way to inform the IOMMU mr about the page_size_mask > >> of underlying HW IOMMU, if any > >> - remove warning associated with the translation of the MSI doorbell > >> > >> v2 -> v3: > >> - rebase on top of 2.10-rc0 and especially > >> [PATCH qemu v9 0/2] memory/iommu: QOM'fy IOMMU MemoryRegion > >> - add mutex init > >> - fix as->mappings deletion using g_tree_ref/unref > >> - when a dev is attached whereas it is already attached to > >> another address space, first detach it > >> - fix some error values > >> - page_sizes =3D TARGET_PAGE_MASK; > >> - I haven't changed the unmap() semantics yet, waiting for the > >> next virtio-iommu spec revision. > >> > >> v1 -> v2: > >> - fix redefinition of viommu_as typedef > >> > >> > >> > >> Eric Auger (20): > >> migration: Support QLIST migration > >> virtio-iommu: Add skeleton > >> virtio-iommu: Decode the command payload > >> virtio-iommu: Add the iommu regions > >> virtio-iommu: Endpoint and domains structs and helpers > >> virtio-iommu: Implement attach/detach command > >> virtio-iommu: Implement map/unmap > >> virtio-iommu: Implement translate > >> virtio-iommu: Implement fault reporting > >> virtio-iommu-pci: Add virtio iommu pci support > >> hw/arm/virt: Add the virtio-iommu device tree mappings > >> qapi: Introduce DEFINE_PROP_INTERVAL > >> virtio-iommu: Implement probe request > >> virtio-iommu: Handle reserved regions in the translation process > >> virtio-iommu-pci: Add array of Interval properties > >> hw/arm/virt-acpi-build: Introduce fill_iort_idmap helper > >> hw/arm/virt-acpi-build: Add virtio-iommu node in IORT table > >> virtio-iommu: Support migration > >> pc: Add support for virtio-iommu-pci > >> tests: Add virtio-iommu test > >> > >> hw/arm/virt-acpi-build.c | 91 ++- > >> hw/arm/virt.c | 53 +- > >> hw/core/qdev-properties.c | 90 +++ > >> hw/i386/acpi-build.c | 72 +++ > >> hw/i386/pc.c | 15 +- > >> hw/virtio/Kconfig | 5 + > >> hw/virtio/Makefile.objs | 2 + > >> hw/virtio/trace-events | 22 + > >> hw/virtio/virtio-iommu-pci.c | 91 +++ > >> hw/virtio/virtio-iommu.c | 952 ++++++++++++++++++++++++++++++= + > >> include/exec/memory.h | 6 + > >> include/hw/acpi/acpi-defs.h | 21 +- > >> include/hw/arm/virt.h | 2 + > >> include/hw/i386/pc.h | 2 + > >> include/hw/pci/pci.h | 1 + > >> include/hw/qdev-properties.h | 3 + > >> include/hw/virtio/virtio-iommu.h | 67 +++ > >> include/migration/vmstate.h | 21 + > >> include/qemu/queue.h | 39 ++ > >> include/qemu/typedefs.h | 1 + > >> migration/trace-events | 5 + > >> migration/vmstate-types.c | 70 +++ > >> qdev-monitor.c | 1 + > >> tests/Makefile.include | 2 + > >> tests/libqos/virtio-iommu.c | 177 ++++++ > >> tests/libqos/virtio-iommu.h | 45 ++ > >> tests/test-vmstate.c | 170 ++++++ > >> tests/virtio-iommu-test.c | 261 +++++++++ > >> 28 files changed, 2253 insertions(+), 34 deletions(-) > >> create mode 100644 hw/virtio/virtio-iommu-pci.c > >> create mode 100644 hw/virtio/virtio-iommu.c > >> create mode 100644 include/hw/virtio/virtio-iommu.h > >> create mode 100644 tests/libqos/virtio-iommu.c > >> create mode 100644 tests/libqos/virtio-iommu.h > >> create mode 100644 tests/virtio-iommu-test.c > >> > >> --=20 > >> 2.20.1 > >=20 > >=20 From MAILER-DAEMON Wed Dec 11 17:35:40 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1ifAa4-00080T-Mu for mharc-qemu-arm@gnu.org; Wed, 11 Dec 2019 17:35:40 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:54266) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ifAZt-0007nM-1M for qemu-arm@nongnu.org; Wed, 11 Dec 2019 17:35:38 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ifAZg-0007gK-Hz for qemu-arm@nongnu.org; Wed, 11 Dec 2019 17:35:27 -0500 Received: from mail-io1-xd41.google.com ([2607:f8b0:4864:20::d41]:45472) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ifAZP-00075S-Vx; Wed, 11 Dec 2019 17:35:00 -0500 Received: by mail-io1-xd41.google.com with SMTP id i11so517348ioi.12; Wed, 11 Dec 2019 14:34:59 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=IpAGi6p8GJWeq/Mz+uTJuk0JoMeG5glziVQAmBR8504=; b=WPUtnUQlB5M9duh8SJF3OqQku1JusmvSfr9TcaaySmRaxX7sKSElGxBXcayne3qhUR 8xu9RVA+mr0Tom4LoGV0R0CxjsvV1QkrxytWLVHE8bhCeSPLUxC2VIzv/IGaJTHajeMO F1UX5Stob4IDylBm9qocv4aBdUw9JF6sWTbywkTNC1q7vjho6+Q9NmBLBBJ99YgIy1RK rVrsOdb6sew8jlUOEpF0MC9P04c2LA6RRPc0Y+79QY8XsV0AH4GWjFCfkqyEUDiQ1rS8 4uvLcw+G31/tTsab5GrWkkb1m2P43GtfdPctrMRFx0sM6Da72M1rZPQLgzD6J65iHI0n /Xaw== X-Google-DKIM-Signature: v=1; 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boundary="00000000000013a1430599753d58" X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::d41 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 11 Dec 2019 22:35:38 -0000 --00000000000013a1430599753d58 Content-Type: text/plain; charset="UTF-8" Ping! Anyone would like to comment on this driver? I finished the rework on all previous comments in this series. Currently debugging the hflags error reported by Philippe. After that, I'm ready to send out v2 of these patches. Regards, Niek On Mon, Dec 2, 2019 at 10:10 PM Niek Linnenbank wrote: > The Allwinner H3 System on Chip contains an integrated storage > controller for Secure Digital (SD) and Multi Media Card (MMC) > interfaces. This commit adds support for the Allwinner H3 > SD/MMC storage controller with the following emulated features: > > * DMA transfers > * Direct FIFO I/O > * Short/Long format command responses > * Auto-Stop command (CMD12) > * Insert & remove card detection > > Signed-off-by: Niek Linnenbank > --- > hw/arm/allwinner-h3.c | 20 + > hw/arm/orangepi.c | 17 + > hw/sd/Makefile.objs | 1 + > hw/sd/allwinner-h3-sdhost.c | 791 ++++++++++++++++++++++++++++ > hw/sd/trace-events | 7 + > include/hw/arm/allwinner-h3.h | 2 + > include/hw/sd/allwinner-h3-sdhost.h | 73 +++ > 7 files changed, 911 insertions(+) > create mode 100644 hw/sd/allwinner-h3-sdhost.c > create mode 100644 include/hw/sd/allwinner-h3-sdhost.h > > diff --git a/hw/arm/allwinner-h3.c b/hw/arm/allwinner-h3.c > index 4fc4c8c725..c2972caf88 100644 > --- a/hw/arm/allwinner-h3.c > +++ b/hw/arm/allwinner-h3.c > @@ -50,6 +50,9 @@ static void aw_h3_init(Object *obj) > > sysbus_init_child_obj(obj, "sid", &s->sid, sizeof(s->sid), > TYPE_AW_H3_SID); > + > + sysbus_init_child_obj(obj, "mmc0", &s->mmc0, sizeof(s->mmc0), > + TYPE_AW_H3_SDHOST); > } > > static void aw_h3_realize(DeviceState *dev, Error **errp) > @@ -217,6 +220,23 @@ static void aw_h3_realize(DeviceState *dev, Error > **errp) > } > sysbus_mmio_map(SYS_BUS_DEVICE(&s->sid), 0, AW_H3_SID_BASE); > > + /* SD/MMC */ > + object_property_set_bool(OBJECT(&s->mmc0), true, "realized", &err); > + if (err != NULL) { > + error_propagate(errp, err); > + return; > + } > + sysbusdev = SYS_BUS_DEVICE(&s->mmc0); > + sysbus_mmio_map(sysbusdev, 0, AW_H3_MMC0_BASE); > + sysbus_connect_irq(sysbusdev, 0, s->irq[AW_H3_GIC_SPI_MMC0]); > + > + object_property_add_alias(OBJECT(s), "sd-bus", OBJECT(&s->mmc0), > + "sd-bus", &err); > + if (err) { > + error_propagate(errp, err); > + return; > + } > + > /* Universal Serial Bus */ > sysbus_create_simple(TYPE_AW_H3_EHCI, AW_H3_EHCI0_BASE, > s->irq[AW_H3_GIC_SPI_EHCI0]); > diff --git a/hw/arm/orangepi.c b/hw/arm/orangepi.c > index 5ef2735f81..dee3efaf08 100644 > --- a/hw/arm/orangepi.c > +++ b/hw/arm/orangepi.c > @@ -39,6 +39,10 @@ typedef struct OrangePiState { > static void orangepi_init(MachineState *machine) > { > OrangePiState *s = g_new(OrangePiState, 1); > + DriveInfo *di; > + BlockBackend *blk; > + BusState *bus; > + DeviceState *carddev; > Error *err = NULL; > > s->h3 = AW_H3(object_new(TYPE_AW_H3)); > @@ -64,6 +68,18 @@ static void orangepi_init(MachineState *machine) > exit(1); > } > > + /* Create and plug in the SD card */ > + di = drive_get_next(IF_SD); > + blk = di ? blk_by_legacy_dinfo(di) : NULL; > + bus = qdev_get_child_bus(DEVICE(s->h3), "sd-bus"); > + if (bus == NULL) { > + error_report("No SD/MMC found in H3 object"); > + exit(1); > + } > + carddev = qdev_create(bus, TYPE_SD_CARD); > + qdev_prop_set_drive(carddev, "drive", blk, &error_fatal); > + object_property_set_bool(OBJECT(carddev), true, "realized", > &error_fatal); > + > /* RAM */ > memory_region_allocate_system_memory(&s->sdram, NULL, "orangepi.ram", > machine->ram_size); > @@ -80,6 +96,7 @@ static void orangepi_machine_init(MachineClass *mc) > { > mc->desc = "Orange Pi PC"; > mc->init = orangepi_init; > + mc->block_default_type = IF_SD; > mc->units_per_default_bus = 1; > mc->min_cpus = AW_H3_NUM_CPUS; > mc->max_cpus = AW_H3_NUM_CPUS; > diff --git a/hw/sd/Makefile.objs b/hw/sd/Makefile.objs > index a884c238df..e7cc5ab739 100644 > --- a/hw/sd/Makefile.objs > +++ b/hw/sd/Makefile.objs > @@ -4,6 +4,7 @@ common-obj-$(CONFIG_SD) += sd.o core.o sdmmc-internal.o > common-obj-$(CONFIG_SDHCI) += sdhci.o > common-obj-$(CONFIG_SDHCI_PCI) += sdhci-pci.o > > +obj-$(CONFIG_ALLWINNER_H3) += allwinner-h3-sdhost.o > obj-$(CONFIG_MILKYMIST) += milkymist-memcard.o > obj-$(CONFIG_OMAP) += omap_mmc.o > obj-$(CONFIG_PXA2XX) += pxa2xx_mmci.o > diff --git a/hw/sd/allwinner-h3-sdhost.c b/hw/sd/allwinner-h3-sdhost.c > new file mode 100644 > index 0000000000..26e113a144 > --- /dev/null > +++ b/hw/sd/allwinner-h3-sdhost.c > @@ -0,0 +1,791 @@ > +/* > + * Allwinner H3 SD Host Controller emulation > + * > + * Copyright (C) 2019 Niek Linnenbank > + * > + * This program is free software: you can redistribute it and/or modify > + * it under the terms of the GNU General Public License as published by > + * the Free Software Foundation, either version 2 of the License, or > + * (at your option) any later version. > + * > + * This program is distributed in the hope that it will be useful, > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > + * GNU General Public License for more details. > + * > + * You should have received a copy of the GNU General Public License > + * along with this program. If not, see . > + */ > + > +#include "qemu/osdep.h" > +#include "qemu/log.h" > +#include "qemu/module.h" > +#include "sysemu/blockdev.h" > +#include "hw/irq.h" > +#include "hw/sd/allwinner-h3-sdhost.h" > +#include "migration/vmstate.h" > +#include "trace.h" > + > +#define TYPE_AW_H3_SDHOST_BUS "allwinner-h3-sdhost-bus" > +#define AW_H3_SDHOST_BUS(obj) \ > + OBJECT_CHECK(SDBus, (obj), TYPE_AW_H3_SDHOST_BUS) > + > +/* SD Host register offsets */ > +#define REG_SD_GCTL (0x00) /* Global Control */ > +#define REG_SD_CKCR (0x04) /* Clock Control */ > +#define REG_SD_TMOR (0x08) /* Timeout */ > +#define REG_SD_BWDR (0x0C) /* Bus Width */ > +#define REG_SD_BKSR (0x10) /* Block Size */ > +#define REG_SD_BYCR (0x14) /* Byte Count */ > +#define REG_SD_CMDR (0x18) /* Command */ > +#define REG_SD_CAGR (0x1C) /* Command Argument */ > +#define REG_SD_RESP0 (0x20) /* Response Zero */ > +#define REG_SD_RESP1 (0x24) /* Response One */ > +#define REG_SD_RESP2 (0x28) /* Response Two */ > +#define REG_SD_RESP3 (0x2C) /* Response Three */ > +#define REG_SD_IMKR (0x30) /* Interrupt Mask */ > +#define REG_SD_MISR (0x34) /* Masked Interrupt Status */ > +#define REG_SD_RISR (0x38) /* Raw Interrupt Status */ > +#define REG_SD_STAR (0x3C) /* Status */ > +#define REG_SD_FWLR (0x40) /* FIFO Water Level */ > +#define REG_SD_FUNS (0x44) /* FIFO Function Select */ > +#define REG_SD_DBGC (0x50) /* Debug Enable */ > +#define REG_SD_A12A (0x58) /* Auto command 12 argument */ > +#define REG_SD_NTSR (0x5C) /* SD NewTiming Set */ > +#define REG_SD_SDBG (0x60) /* SD newTiming Set Debug */ > +#define REG_SD_HWRST (0x78) /* Hardware Reset Register */ > +#define REG_SD_DMAC (0x80) /* Internal DMA Controller Control */ > +#define REG_SD_DLBA (0x84) /* Descriptor List Base Address */ > +#define REG_SD_IDST (0x88) /* Internal DMA Controller Status */ > +#define REG_SD_IDIE (0x8C) /* Internal DMA Controller IRQ Enable > */ > +#define REG_SD_THLDC (0x100) /* Card Threshold Control */ > +#define REG_SD_DSBD (0x10C) /* eMMC DDR Start Bit Detection > Control */ > +#define REG_SD_RES_CRC (0x110) /* Response CRC from card/eMMC */ > +#define REG_SD_DATA7_CRC (0x114) /* CRC Data 7 from card/eMMC */ > +#define REG_SD_DATA6_CRC (0x118) /* CRC Data 6 from card/eMMC */ > +#define REG_SD_DATA5_CRC (0x11C) /* CRC Data 5 from card/eMMC */ > +#define REG_SD_DATA4_CRC (0x120) /* CRC Data 4 from card/eMMC */ > +#define REG_SD_DATA3_CRC (0x124) /* CRC Data 3 from card/eMMC */ > +#define REG_SD_DATA2_CRC (0x128) /* CRC Data 2 from card/eMMC */ > +#define REG_SD_DATA1_CRC (0x12C) /* CRC Data 1 from card/eMMC */ > +#define REG_SD_DATA0_CRC (0x130) /* CRC Data 0 from card/eMMC */ > +#define REG_SD_CRC_STA (0x134) /* CRC status from card/eMMC during > write */ > +#define REG_SD_FIFO (0x200) /* Read/Write FIFO */ > + > +/* SD Host register flags */ > +#define SD_GCTL_FIFO_AC_MOD (1 << 31) > +#define SD_GCTL_DDR_MOD_SEL (1 << 10) > +#define SD_GCTL_CD_DBC_ENB (1 << 8) > +#define SD_GCTL_DMA_ENB (1 << 5) > +#define SD_GCTL_INT_ENB (1 << 4) > +#define SD_GCTL_DMA_RST (1 << 2) > +#define SD_GCTL_FIFO_RST (1 << 1) > +#define SD_GCTL_SOFT_RST (1 << 0) > + > +#define SD_CMDR_LOAD (1 << 31) > +#define SD_CMDR_CLKCHANGE (1 << 21) > +#define SD_CMDR_WRITE (1 << 10) > +#define SD_CMDR_AUTOSTOP (1 << 12) > +#define SD_CMDR_DATA (1 << 9) > +#define SD_CMDR_RESPONSE_LONG (1 << 7) > +#define SD_CMDR_RESPONSE (1 << 6) > +#define SD_CMDR_CMDID_MASK (0x3f) > + > +#define SD_RISR_CARD_REMOVE (1 << 31) > +#define SD_RISR_CARD_INSERT (1 << 30) > +#define SD_RISR_AUTOCMD_DONE (1 << 14) > +#define SD_RISR_DATA_COMPLETE (1 << 3) > +#define SD_RISR_CMD_COMPLETE (1 << 2) > +#define SD_RISR_NO_RESPONSE (1 << 1) > + > +#define SD_STAR_CARD_PRESENT (1 << 8) > + > +#define SD_IDST_SUM_RECEIVE_IRQ (1 << 8) > +#define SD_IDST_RECEIVE_IRQ (1 << 1) > +#define SD_IDST_TRANSMIT_IRQ (1 << 0) > +#define SD_IDST_IRQ_MASK (SD_IDST_RECEIVE_IRQ | > SD_IDST_TRANSMIT_IRQ | \ > + SD_IDST_SUM_RECEIVE_IRQ) > +#define SD_IDST_WR_MASK (0x3ff) > + > +/* SD Host register reset values */ > +#define REG_SD_GCTL_RST (0x00000300) > +#define REG_SD_CKCR_RST (0x0) > +#define REG_SD_TMOR_RST (0xFFFFFF40) > +#define REG_SD_BWDR_RST (0x0) > +#define REG_SD_BKSR_RST (0x00000200) > +#define REG_SD_BYCR_RST (0x00000200) > +#define REG_SD_CMDR_RST (0x0) > +#define REG_SD_CAGR_RST (0x0) > +#define REG_SD_RESP_RST (0x0) > +#define REG_SD_IMKR_RST (0x0) > +#define REG_SD_MISR_RST (0x0) > +#define REG_SD_RISR_RST (0x0) > +#define REG_SD_STAR_RST (0x00000100) > +#define REG_SD_FWLR_RST (0x000F0000) > +#define REG_SD_FUNS_RST (0x0) > +#define REG_SD_DBGC_RST (0x0) > +#define REG_SD_A12A_RST (0x0000FFFF) > +#define REG_SD_NTSR_RST (0x00000001) > +#define REG_SD_SDBG_RST (0x0) > +#define REG_SD_HWRST_RST (0x00000001) > +#define REG_SD_DMAC_RST (0x0) > +#define REG_SD_DLBA_RST (0x0) > +#define REG_SD_IDST_RST (0x0) > +#define REG_SD_IDIE_RST (0x0) > +#define REG_SD_THLDC_RST (0x0) > +#define REG_SD_DSBD_RST (0x0) > +#define REG_SD_RES_CRC_RST (0x0) > +#define REG_SD_DATA_CRC_RST (0x0) > +#define REG_SD_CRC_STA_RST (0x0) > +#define REG_SD_FIFO_RST (0x0) > + > +/* Data transfer descriptor for DMA */ > +typedef struct TransferDescriptor { > + uint32_t status; /* Status flags */ > + uint32_t size; /* Data buffer size */ > + uint32_t addr; /* Data buffer address */ > + uint32_t next; /* Physical address of next descriptor */ > +} TransferDescriptor; > + > +/* Data transfer descriptor flags */ > +#define DESC_STATUS_HOLD (1 << 31) /* Set when descriptor is in use by > DMA */ > +#define DESC_STATUS_ERROR (1 << 30) /* Set when DMA transfer error > occurred */ > +#define DESC_STATUS_CHAIN (1 << 4) /* Indicates chained descriptor. */ > +#define DESC_STATUS_FIRST (1 << 3) /* Set on the first descriptor */ > +#define DESC_STATUS_LAST (1 << 2) /* Set on the last descriptor */ > +#define DESC_STATUS_NOIRQ (1 << 1) /* Skip raising interrupt after > transfer */ > + > +#define DESC_SIZE_MASK (0xfffffffc) > + > +static void aw_h3_sdhost_update_irq(AwH3SDHostState *s) > +{ > + uint32_t irq_en = s->global_ctl & SD_GCTL_INT_ENB; > + uint32_t irq = irq_en ? s->irq_status & s->irq_mask : 0; > + > + trace_aw_h3_sdhost_update_irq(irq); > + qemu_set_irq(s->irq, irq); > +} > + > +static void aw_h3_sdhost_update_transfer_cnt(AwH3SDHostState *s, uint32_t > bytes) > +{ > + if (s->transfer_cnt > bytes) { > + s->transfer_cnt -= bytes; > + } else { > + s->transfer_cnt = 0; > + } > + > + if (!s->transfer_cnt) { > + s->irq_status |= SD_RISR_DATA_COMPLETE | SD_RISR_AUTOCMD_DONE; > + } > +} > + > +static void aw_h3_sdhost_set_inserted(DeviceState *dev, bool inserted) > +{ > + AwH3SDHostState *s = AW_H3_SDHOST(dev); > + > + trace_aw_h3_sdhost_set_inserted(inserted); > + > + if (inserted) { > + s->irq_status |= SD_RISR_CARD_INSERT; > + s->irq_status &= ~SD_RISR_CARD_REMOVE; > + s->status |= SD_STAR_CARD_PRESENT; > + } else { > + s->irq_status &= ~SD_RISR_CARD_INSERT; > + s->irq_status |= SD_RISR_CARD_REMOVE; > + s->status &= ~SD_STAR_CARD_PRESENT; > + } > + > + aw_h3_sdhost_update_irq(s); > +} > + > +static void aw_h3_sdhost_send_command(AwH3SDHostState *s) > +{ > + SDRequest request; > + uint8_t resp[16]; > + int rlen; > + > + /* Auto clear load flag */ > + s->command &= ~SD_CMDR_LOAD; > + > + /* Clock change does not actually interact with the SD bus */ > + if (!(s->command & SD_CMDR_CLKCHANGE)) { > + > + /* Prepare request */ > + request.cmd = s->command & SD_CMDR_CMDID_MASK; > + request.arg = s->command_arg; > + > + /* Send request to SD bus */ > + rlen = sdbus_do_command(&s->sdbus, &request, resp); > + if (rlen < 0) { > + goto error; > + } > + > + /* If the command has a response, store it in the response > registers */ > + if ((s->command & SD_CMDR_RESPONSE)) { > + if (rlen == 0 || > + (rlen == 4 && (s->command & SD_CMDR_RESPONSE_LONG))) { > + goto error; > + } > + if (rlen != 4 && rlen != 16) { > + goto error; > + } > + if (rlen == 4) { > + s->response[0] = ldl_be_p(&resp[0]); > + s->response[1] = s->response[2] = s->response[3] = 0; > + } else { > + s->response[0] = ldl_be_p(&resp[12]); > + s->response[1] = ldl_be_p(&resp[8]); > + s->response[2] = ldl_be_p(&resp[4]); > + s->response[3] = ldl_be_p(&resp[0]); > + } > + } > + } > + > + /* Set interrupt status bits */ > + s->irq_status |= SD_RISR_CMD_COMPLETE; > + return; > + > +error: > + s->irq_status |= SD_RISR_NO_RESPONSE; > +} > + > +static void aw_h3_sdhost_auto_stop(AwH3SDHostState *s) > +{ > + /* > + * The stop command (CMD12) ensures the SD bus > + * returns to the transfer state. > + */ > + if ((s->command & SD_CMDR_AUTOSTOP) && (s->transfer_cnt == 0)) { > + /* First save current command registers */ > + uint32_t saved_cmd = s->command; > + uint32_t saved_arg = s->command_arg; > + > + /* Prepare stop command (CMD12) */ > + s->command &= ~SD_CMDR_CMDID_MASK; > + s->command |= 12; /* CMD12 */ > + s->command_arg = 0; > + > + /* Put the command on SD bus */ > + aw_h3_sdhost_send_command(s); > + > + /* Restore command values */ > + s->command = saved_cmd; > + s->command_arg = saved_arg; > + } > +} > + > +static uint32_t aw_h3_sdhost_process_desc(AwH3SDHostState *s, > + hwaddr desc_addr, > + TransferDescriptor *desc, > + bool is_write, uint32_t > max_bytes) > +{ > + uint32_t num_done = 0; > + uint32_t num_bytes = max_bytes; > + uint8_t buf[1024]; > + > + /* Read descriptor */ > + cpu_physical_memory_read(desc_addr, desc, sizeof(*desc)); > + if (desc->size == 0) { > + desc->size = 0xffff + 1; > + } > + if (desc->size < num_bytes) { > + num_bytes = desc->size; > + } > + > + trace_aw_h3_sdhost_process_desc(desc_addr, desc->size, is_write, > max_bytes); > + > + while (num_done < num_bytes) { > + /* Try to completely fill the local buffer */ > + uint32_t buf_bytes = num_bytes - num_done; > + if (buf_bytes > sizeof(buf)) { > + buf_bytes = sizeof(buf); > + } > + > + /* Write to SD bus */ > + if (is_write) { > + cpu_physical_memory_read((desc->addr & DESC_SIZE_MASK) + > num_done, > + buf, buf_bytes); > + > + for (uint32_t i = 0; i < buf_bytes; i++) { > + sdbus_write_data(&s->sdbus, buf[i]); > + } > + > + /* Read from SD bus */ > + } else { > + for (uint32_t i = 0; i < buf_bytes; i++) { > + buf[i] = sdbus_read_data(&s->sdbus); > + } > + cpu_physical_memory_write((desc->addr & DESC_SIZE_MASK) + > num_done, > + buf, buf_bytes); > + } > + num_done += buf_bytes; > + } > + > + /* Clear hold flag and flush descriptor */ > + desc->status &= ~DESC_STATUS_HOLD; > + cpu_physical_memory_write(desc_addr, desc, sizeof(*desc)); > + > + return num_done; > +} > + > +static void aw_h3_sdhost_dma(AwH3SDHostState *s) > +{ > + TransferDescriptor desc; > + hwaddr desc_addr = s->desc_base; > + bool is_write = (s->command & SD_CMDR_WRITE); > + uint32_t bytes_done = 0; > + > + /* Check if DMA can be performed */ > + if (s->byte_count == 0 || s->block_size == 0 || > + !(s->global_ctl & SD_GCTL_DMA_ENB)) { > + return; > + } > + > + /* > + * For read operations, data must be available on the SD bus > + * If not, it is an error and we should not act at all > + */ > + if (!is_write && !sdbus_data_ready(&s->sdbus)) { > + return; > + } > + > + /* Process the DMA descriptors until all data is copied */ > + while (s->byte_count > 0) { > + bytes_done = aw_h3_sdhost_process_desc(s, desc_addr, &desc, > + is_write, s->byte_count); > + aw_h3_sdhost_update_transfer_cnt(s, bytes_done); > + > + if (bytes_done <= s->byte_count) { > + s->byte_count -= bytes_done; > + } else { > + s->byte_count = 0; > + } > + > + if (desc.status & DESC_STATUS_LAST) { > + break; > + } else { > + desc_addr = desc.next; > + } > + } > + > + /* Raise IRQ to signal DMA is completed */ > + s->irq_status |= SD_RISR_DATA_COMPLETE | SD_RISR_AUTOCMD_DONE; > + > + /* Update DMAC bits */ > + if (is_write) { > + s->dmac_status |= SD_IDST_TRANSMIT_IRQ; > + } else { > + s->dmac_status |= (SD_IDST_SUM_RECEIVE_IRQ | SD_IDST_RECEIVE_IRQ); > + } > +} > + > +static uint64_t aw_h3_sdhost_read(void *opaque, hwaddr offset, > + unsigned size) > +{ > + AwH3SDHostState *s = (AwH3SDHostState *)opaque; > + uint32_t res = 0; > + > + switch (offset) { > + case REG_SD_GCTL: /* Global Control */ > + res = s->global_ctl; > + break; > + case REG_SD_CKCR: /* Clock Control */ > + res = s->clock_ctl; > + break; > + case REG_SD_TMOR: /* Timeout */ > + res = s->timeout; > + break; > + case REG_SD_BWDR: /* Bus Width */ > + res = s->bus_width; > + break; > + case REG_SD_BKSR: /* Block Size */ > + res = s->block_size; > + break; > + case REG_SD_BYCR: /* Byte Count */ > + res = s->byte_count; > + break; > + case REG_SD_CMDR: /* Command */ > + res = s->command; > + break; > + case REG_SD_CAGR: /* Command Argument */ > + res = s->command_arg; > + break; > + case REG_SD_RESP0: /* Response Zero */ > + res = s->response[0]; > + break; > + case REG_SD_RESP1: /* Response One */ > + res = s->response[1]; > + break; > + case REG_SD_RESP2: /* Response Two */ > + res = s->response[2]; > + break; > + case REG_SD_RESP3: /* Response Three */ > + res = s->response[3]; > + break; > + case REG_SD_IMKR: /* Interrupt Mask */ > + res = s->irq_mask; > + break; > + case REG_SD_MISR: /* Masked Interrupt Status */ > + res = s->irq_status & s->irq_mask; > + break; > + case REG_SD_RISR: /* Raw Interrupt Status */ > + res = s->irq_status; > + break; > + case REG_SD_STAR: /* Status */ > + res = s->status; > + break; > + case REG_SD_FWLR: /* FIFO Water Level */ > + res = s->fifo_wlevel; > + break; > + case REG_SD_FUNS: /* FIFO Function Select */ > + res = s->fifo_func_sel; > + break; > + case REG_SD_DBGC: /* Debug Enable */ > + res = s->debug_enable; > + break; > + case REG_SD_A12A: /* Auto command 12 argument */ > + res = s->auto12_arg; > + break; > + case REG_SD_NTSR: /* SD NewTiming Set */ > + res = s->newtiming_set; > + break; > + case REG_SD_SDBG: /* SD newTiming Set Debug */ > + res = s->newtiming_debug; > + break; > + case REG_SD_HWRST: /* Hardware Reset Register */ > + res = s->hardware_rst; > + break; > + case REG_SD_DMAC: /* Internal DMA Controller Control */ > + res = s->dmac; > + break; > + case REG_SD_DLBA: /* Descriptor List Base Address */ > + res = s->desc_base; > + break; > + case REG_SD_IDST: /* Internal DMA Controller Status */ > + res = s->dmac_status; > + break; > + case REG_SD_IDIE: /* Internal DMA Controller Interrupt Enable */ > + res = s->dmac_irq; > + break; > + case REG_SD_THLDC: /* Card Threshold Control */ > + res = s->card_threshold; > + break; > + case REG_SD_DSBD: /* eMMC DDR Start Bit Detection Control */ > + res = s->startbit_detect; > + break; > + case REG_SD_RES_CRC: /* Response CRC from card/eMMC */ > + res = s->response_crc; > + break; > + case REG_SD_DATA7_CRC: /* CRC Data 7 from card/eMMC */ > + case REG_SD_DATA6_CRC: /* CRC Data 6 from card/eMMC */ > + case REG_SD_DATA5_CRC: /* CRC Data 5 from card/eMMC */ > + case REG_SD_DATA4_CRC: /* CRC Data 4 from card/eMMC */ > + case REG_SD_DATA3_CRC: /* CRC Data 3 from card/eMMC */ > + case REG_SD_DATA2_CRC: /* CRC Data 2 from card/eMMC */ > + case REG_SD_DATA1_CRC: /* CRC Data 1 from card/eMMC */ > + case REG_SD_DATA0_CRC: /* CRC Data 0 from card/eMMC */ > + res = s->data_crc[((offset - REG_SD_DATA7_CRC) / > sizeof(uint32_t))]; > + break; > + case REG_SD_CRC_STA: /* CRC status from card/eMMC in write > operation */ > + res = s->status_crc; > + break; > + case REG_SD_FIFO: /* Read/Write FIFO */ > + if (sdbus_data_ready(&s->sdbus)) { > + res = sdbus_read_data(&s->sdbus); > + res |= sdbus_read_data(&s->sdbus) << 8; > + res |= sdbus_read_data(&s->sdbus) << 16; > + res |= sdbus_read_data(&s->sdbus) << 24; > + aw_h3_sdhost_update_transfer_cnt(s, sizeof(uint32_t)); > + aw_h3_sdhost_auto_stop(s); > + aw_h3_sdhost_update_irq(s); > + } else { > + qemu_log_mask(LOG_GUEST_ERROR, "%s: no data ready on SD > bus\n", > + __func__); > + } > + break; > + default: > + qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset %"HWADDR_PRIx"\n", > + __func__, offset); > + res = 0; > + break; > + } > + > + trace_aw_h3_sdhost_read(offset, res, size); > + return res; > +} > + > +static void aw_h3_sdhost_write(void *opaque, hwaddr offset, > + uint64_t value, unsigned size) > +{ > + AwH3SDHostState *s = (AwH3SDHostState *)opaque; > + > + trace_aw_h3_sdhost_write(offset, value, size); > + > + switch (offset) { > + case REG_SD_GCTL: /* Global Control */ > + s->global_ctl = value; > + s->global_ctl &= ~(SD_GCTL_DMA_RST | SD_GCTL_FIFO_RST | > + SD_GCTL_SOFT_RST); > + aw_h3_sdhost_update_irq(s); > + break; > + case REG_SD_CKCR: /* Clock Control */ > + s->clock_ctl = value; > + break; > + case REG_SD_TMOR: /* Timeout */ > + s->timeout = value; > + break; > + case REG_SD_BWDR: /* Bus Width */ > + s->bus_width = value; > + break; > + case REG_SD_BKSR: /* Block Size */ > + s->block_size = value; > + break; > + case REG_SD_BYCR: /* Byte Count */ > + s->byte_count = value; > + s->transfer_cnt = value; > + break; > + case REG_SD_CMDR: /* Command */ > + s->command = value; > + if (value & SD_CMDR_LOAD) { > + aw_h3_sdhost_send_command(s); > + aw_h3_sdhost_dma(s); > + aw_h3_sdhost_auto_stop(s); > + } > + aw_h3_sdhost_update_irq(s); > + break; > + case REG_SD_CAGR: /* Command Argument */ > + s->command_arg = value; > + break; > + case REG_SD_RESP0: /* Response Zero */ > + s->response[0] = value; > + break; > + case REG_SD_RESP1: /* Response One */ > + s->response[1] = value; > + break; > + case REG_SD_RESP2: /* Response Two */ > + s->response[2] = value; > + break; > + case REG_SD_RESP3: /* Response Three */ > + s->response[3] = value; > + break; > + case REG_SD_IMKR: /* Interrupt Mask */ > + s->irq_mask = value; > + aw_h3_sdhost_update_irq(s); > + break; > + case REG_SD_MISR: /* Masked Interrupt Status */ > + case REG_SD_RISR: /* Raw Interrupt Status */ > + s->irq_status &= ~value; > + aw_h3_sdhost_update_irq(s); > + break; > + case REG_SD_STAR: /* Status */ > + s->status &= ~value; > + aw_h3_sdhost_update_irq(s); > + break; > + case REG_SD_FWLR: /* FIFO Water Level */ > + s->fifo_wlevel = value; > + break; > + case REG_SD_FUNS: /* FIFO Function Select */ > + s->fifo_func_sel = value; > + break; > + case REG_SD_DBGC: /* Debug Enable */ > + s->debug_enable = value; > + break; > + case REG_SD_A12A: /* Auto command 12 argument */ > + s->auto12_arg = value; > + break; > + case REG_SD_NTSR: /* SD NewTiming Set */ > + s->newtiming_set = value; > + break; > + case REG_SD_SDBG: /* SD newTiming Set Debug */ > + s->newtiming_debug = value; > + break; > + case REG_SD_HWRST: /* Hardware Reset Register */ > + s->hardware_rst = value; > + break; > + case REG_SD_DMAC: /* Internal DMA Controller Control */ > + s->dmac = value; > + aw_h3_sdhost_update_irq(s); > + break; > + case REG_SD_DLBA: /* Descriptor List Base Address */ > + s->desc_base = value; > + break; > + case REG_SD_IDST: /* Internal DMA Controller Status */ > + s->dmac_status &= (~SD_IDST_WR_MASK) | (~value & SD_IDST_WR_MASK); > + aw_h3_sdhost_update_irq(s); > + break; > + case REG_SD_IDIE: /* Internal DMA Controller Interrupt Enable */ > + s->dmac_irq = value; > + aw_h3_sdhost_update_irq(s); > + break; > + case REG_SD_THLDC: /* Card Threshold Control */ > + s->card_threshold = value; > + break; > + case REG_SD_DSBD: /* eMMC DDR Start Bit Detection Control */ > + s->startbit_detect = value; > + break; > + case REG_SD_FIFO: /* Read/Write FIFO */ > + sdbus_write_data(&s->sdbus, value & 0xff); > + sdbus_write_data(&s->sdbus, (value >> 8) & 0xff); > + sdbus_write_data(&s->sdbus, (value >> 16) & 0xff); > + sdbus_write_data(&s->sdbus, (value >> 24) & 0xff); > + aw_h3_sdhost_update_transfer_cnt(s, sizeof(uint32_t)); > + aw_h3_sdhost_auto_stop(s); > + aw_h3_sdhost_update_irq(s); > + break; > + case REG_SD_RES_CRC: /* Response CRC from card/eMMC */ > + case REG_SD_DATA7_CRC: /* CRC Data 7 from card/eMMC */ > + case REG_SD_DATA6_CRC: /* CRC Data 6 from card/eMMC */ > + case REG_SD_DATA5_CRC: /* CRC Data 5 from card/eMMC */ > + case REG_SD_DATA4_CRC: /* CRC Data 4 from card/eMMC */ > + case REG_SD_DATA3_CRC: /* CRC Data 3 from card/eMMC */ > + case REG_SD_DATA2_CRC: /* CRC Data 2 from card/eMMC */ > + case REG_SD_DATA1_CRC: /* CRC Data 1 from card/eMMC */ > + case REG_SD_DATA0_CRC: /* CRC Data 0 from card/eMMC */ > + case REG_SD_CRC_STA: /* CRC status from card/eMMC in write > operation */ > + break; > + default: > + qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset %"HWADDR_PRIx"\n", > + __func__, offset); > + break; > + } > +} > + > +static const MemoryRegionOps aw_h3_sdhost_ops = { > + .read = aw_h3_sdhost_read, > + .write = aw_h3_sdhost_write, > + .endianness = DEVICE_NATIVE_ENDIAN, > +}; > + > +static const VMStateDescription vmstate_aw_h3_sdhost = { > + .name = TYPE_AW_H3_SDHOST, > + .version_id = 1, > + .minimum_version_id = 1, > + .fields = (VMStateField[]) { > + VMSTATE_UINT32(global_ctl, AwH3SDHostState), > + VMSTATE_UINT32(clock_ctl, AwH3SDHostState), > + VMSTATE_UINT32(timeout, AwH3SDHostState), > + VMSTATE_UINT32(bus_width, AwH3SDHostState), > + VMSTATE_UINT32(block_size, AwH3SDHostState), > + VMSTATE_UINT32(byte_count, AwH3SDHostState), > + VMSTATE_UINT32(transfer_cnt, AwH3SDHostState), > + VMSTATE_UINT32(command, AwH3SDHostState), > + VMSTATE_UINT32(command_arg, AwH3SDHostState), > + VMSTATE_UINT32_ARRAY(response, AwH3SDHostState, 4), > + VMSTATE_UINT32(irq_mask, AwH3SDHostState), > + VMSTATE_UINT32(irq_status, AwH3SDHostState), > + VMSTATE_UINT32(status, AwH3SDHostState), > + VMSTATE_UINT32(fifo_wlevel, AwH3SDHostState), > + VMSTATE_UINT32(fifo_func_sel, AwH3SDHostState), > + VMSTATE_UINT32(debug_enable, AwH3SDHostState), > + VMSTATE_UINT32(auto12_arg, AwH3SDHostState), > + VMSTATE_UINT32(newtiming_set, AwH3SDHostState), > + VMSTATE_UINT32(newtiming_debug, AwH3SDHostState), > + VMSTATE_UINT32(hardware_rst, AwH3SDHostState), > + VMSTATE_UINT32(dmac, AwH3SDHostState), > + VMSTATE_UINT32(desc_base, AwH3SDHostState), > + VMSTATE_UINT32(dmac_status, AwH3SDHostState), > + VMSTATE_UINT32(dmac_irq, AwH3SDHostState), > + VMSTATE_UINT32(card_threshold, AwH3SDHostState), > + VMSTATE_UINT32(startbit_detect, AwH3SDHostState), > + VMSTATE_UINT32(response_crc, AwH3SDHostState), > + VMSTATE_UINT32_ARRAY(data_crc, AwH3SDHostState, 8), > + VMSTATE_UINT32(status_crc, AwH3SDHostState), > + VMSTATE_END_OF_LIST() > + } > +}; > + > +static void aw_h3_sdhost_init(Object *obj) > +{ > + AwH3SDHostState *s = AW_H3_SDHOST(obj); > + > + qbus_create_inplace(&s->sdbus, sizeof(s->sdbus), > + TYPE_AW_H3_SDHOST_BUS, DEVICE(s), "sd-bus"); > + > + memory_region_init_io(&s->iomem, obj, &aw_h3_sdhost_ops, s, > + TYPE_AW_H3_SDHOST, AW_H3_SDHOST_REGS_MEM_SIZE); > + sysbus_init_mmio(SYS_BUS_DEVICE(s), &s->iomem); > + sysbus_init_irq(SYS_BUS_DEVICE(s), &s->irq); > +} > + > +static void aw_h3_sdhost_reset(DeviceState *dev) > +{ > + AwH3SDHostState *s = AW_H3_SDHOST(dev); > + > + s->global_ctl = REG_SD_GCTL_RST; > + s->clock_ctl = REG_SD_CKCR_RST; > + s->timeout = REG_SD_TMOR_RST; > + s->bus_width = REG_SD_BWDR_RST; > + s->block_size = REG_SD_BKSR_RST; > + s->byte_count = REG_SD_BYCR_RST; > + s->transfer_cnt = 0; > + > + s->command = REG_SD_CMDR_RST; > + s->command_arg = REG_SD_CAGR_RST; > + > + for (int i = 0; i < sizeof(s->response) / sizeof(s->response[0]); > i++) { > + s->response[i] = REG_SD_RESP_RST; > + } > + > + s->irq_mask = REG_SD_IMKR_RST; > + s->irq_status = REG_SD_RISR_RST; > + s->status = REG_SD_STAR_RST; > + > + s->fifo_wlevel = REG_SD_FWLR_RST; > + s->fifo_func_sel = REG_SD_FUNS_RST; > + s->debug_enable = REG_SD_DBGC_RST; > + s->auto12_arg = REG_SD_A12A_RST; > + s->newtiming_set = REG_SD_NTSR_RST; > + s->newtiming_debug = REG_SD_SDBG_RST; > + s->hardware_rst = REG_SD_HWRST_RST; > + s->dmac = REG_SD_DMAC_RST; > + s->desc_base = REG_SD_DLBA_RST; > + s->dmac_status = REG_SD_IDST_RST; > + s->dmac_irq = REG_SD_IDIE_RST; > + s->card_threshold = REG_SD_THLDC_RST; > + s->startbit_detect = REG_SD_DSBD_RST; > + s->response_crc = REG_SD_RES_CRC_RST; > + > + for (int i = 0; i < sizeof(s->data_crc) / sizeof(s->data_crc[0]); > i++) { > + s->data_crc[i] = REG_SD_DATA_CRC_RST; > + } > + > + s->status_crc = REG_SD_CRC_STA_RST; > +} > + > +static void aw_h3_sdhost_bus_class_init(ObjectClass *klass, void *data) > +{ > + SDBusClass *sbc = SD_BUS_CLASS(klass); > + > + sbc->set_inserted = aw_h3_sdhost_set_inserted; > +} > + > +static void aw_h3_sdhost_class_init(ObjectClass *klass, void *data) > +{ > + DeviceClass *dc = DEVICE_CLASS(klass); > + > + dc->reset = aw_h3_sdhost_reset; > + dc->vmsd = &vmstate_aw_h3_sdhost; > +} > + > +static TypeInfo aw_h3_sdhost_info = { > + .name = TYPE_AW_H3_SDHOST, > + .parent = TYPE_SYS_BUS_DEVICE, > + .instance_size = sizeof(AwH3SDHostState), > + .class_init = aw_h3_sdhost_class_init, > + .instance_init = aw_h3_sdhost_init, > +}; > + > +static const TypeInfo aw_h3_sdhost_bus_info = { > + .name = TYPE_AW_H3_SDHOST_BUS, > + .parent = TYPE_SD_BUS, > + .instance_size = sizeof(SDBus), > + .class_init = aw_h3_sdhost_bus_class_init, > +}; > + > +static void aw_h3_sdhost_register_types(void) > +{ > + type_register_static(&aw_h3_sdhost_info); > + type_register_static(&aw_h3_sdhost_bus_info); > +} > + > +type_init(aw_h3_sdhost_register_types) > diff --git a/hw/sd/trace-events b/hw/sd/trace-events > index efcff666a2..c672a201b5 100644 > --- a/hw/sd/trace-events > +++ b/hw/sd/trace-events > @@ -1,5 +1,12 @@ > # See docs/devel/tracing.txt for syntax documentation. > > +# allwinner-h3-sdhost.c > +aw_h3_sdhost_set_inserted(bool inserted) "inserted %u" > +aw_h3_sdhost_process_desc(uint64_t desc_addr, uint32_t desc_size, bool > is_write, uint32_t max_bytes) "desc_addr 0x%" PRIx64 " desc_size %u > is_write %u max_bytes %u" > +aw_h3_sdhost_read(uint64_t offset, uint64_t data, unsigned size) "offset > 0x%" PRIx64 " data 0x%" PRIx64 " size %u" > +aw_h3_sdhost_write(uint64_t offset, uint64_t data, unsigned size) "offset > 0x%" PRIx64 " data 0x%" PRIx64 " size %u" > +aw_h3_sdhost_update_irq(uint32_t irq) "IRQ bits 0x%x" > + > # bcm2835_sdhost.c > bcm2835_sdhost_read(uint64_t offset, uint64_t data, unsigned size) > "offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u" > bcm2835_sdhost_write(uint64_t offset, uint64_t data, unsigned size) > "offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u" > diff --git a/include/hw/arm/allwinner-h3.h b/include/hw/arm/allwinner-h3.h > index 33602599eb..7aff4ebbd2 100644 > --- a/include/hw/arm/allwinner-h3.h > +++ b/include/hw/arm/allwinner-h3.h > @@ -30,6 +30,7 @@ > #include "hw/misc/allwinner-h3-cpucfg.h" > #include "hw/misc/allwinner-h3-syscon.h" > #include "hw/misc/allwinner-h3-sid.h" > +#include "hw/sd/allwinner-h3-sdhost.h" > #include "target/arm/cpu.h" > > #define AW_H3_SRAM_A1_BASE (0x00000000) > @@ -117,6 +118,7 @@ typedef struct AwH3State { > AwH3CpuCfgState cpucfg; > AwH3SysconState syscon; > AwH3SidState sid; > + AwH3SDHostState mmc0; > GICState gic; > MemoryRegion sram_a1; > MemoryRegion sram_a2; > diff --git a/include/hw/sd/allwinner-h3-sdhost.h > b/include/hw/sd/allwinner-h3-sdhost.h > new file mode 100644 > index 0000000000..6c898a3c84 > --- /dev/null > +++ b/include/hw/sd/allwinner-h3-sdhost.h > @@ -0,0 +1,73 @@ > +/* > + * Allwinner H3 SD Host Controller emulation > + * > + * Copyright (C) 2019 Niek Linnenbank > + * > + * This program is free software: you can redistribute it and/or modify > + * it under the terms of the GNU General Public License as published by > + * the Free Software Foundation, either version 2 of the License, or > + * (at your option) any later version. > + * > + * This program is distributed in the hope that it will be useful, > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > + * GNU General Public License for more details. > + * > + * You should have received a copy of the GNU General Public License > + * along with this program. If not, see . > + */ > + > +#ifndef ALLWINNER_H3_SDHOST_H > +#define ALLWINNER_H3_SDHOST_H > + > +#include "hw/sysbus.h" > +#include "hw/sd/sd.h" > + > +#define AW_H3_SDHOST_REGS_MEM_SIZE (1024) > + > +#define TYPE_AW_H3_SDHOST "allwinner-h3-sdhost" > +#define AW_H3_SDHOST(obj) \ > + OBJECT_CHECK(AwH3SDHostState, (obj), TYPE_AW_H3_SDHOST) > + > +typedef struct { > + SysBusDevice busdev; > + SDBus sdbus; > + MemoryRegion iomem; > + > + uint32_t global_ctl; > + uint32_t clock_ctl; > + uint32_t timeout; > + uint32_t bus_width; > + uint32_t block_size; > + uint32_t byte_count; > + uint32_t transfer_cnt; > + > + uint32_t command; > + uint32_t command_arg; > + uint32_t response[4]; > + > + uint32_t irq_mask; > + uint32_t irq_status; > + uint32_t status; > + > + uint32_t fifo_wlevel; > + uint32_t fifo_func_sel; > + uint32_t debug_enable; > + uint32_t auto12_arg; > + uint32_t newtiming_set; > + uint32_t newtiming_debug; > + uint32_t hardware_rst; > + uint32_t dmac; > + uint32_t desc_base; > + uint32_t dmac_status; > + uint32_t dmac_irq; > + uint32_t card_threshold; > + uint32_t startbit_detect; > + uint32_t response_crc; > + uint32_t data_crc[8]; > + uint32_t status_crc; > + > + qemu_irq irq; > +} AwH3SDHostState; > + > +#endif > -- > 2.17.1 > > -- Niek Linnenbank --00000000000013a1430599753d58 Content-Type: text/html; charset="UTF-8" Content-Transfer-Encoding: quoted-printable
Ping!

Anyone would like to c= omment on this driver?

I finished the rework on al= l previous comments in this series.

Currently debu= gging the hflags error reported by Philippe.
After that, I'm = ready to send out v2 of these patches.

Regards,
Niek

On Mon, Dec 2, 2019 at 10:10 PM Niek Linnenbank <nieklinnenbank@gmail.com> w= rote:
The Allwin= ner H3 System on Chip contains an integrated storage
controller for Secure Digital (SD) and Multi Media Card (MMC)
interfaces. This commit adds support for the Allwinner H3
SD/MMC storage controller with the following emulated features:

=C2=A0* DMA transfers
=C2=A0* Direct FIFO I/O
=C2=A0* Short/Long format command responses
=C2=A0* Auto-Stop command (CMD12)
=C2=A0* Insert & remove card detection

Signed-off-by: Niek Linnenbank <nieklinnenbank@gmail.com>
---
=C2=A0hw/arm/allwinner-h3.c=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0|=C2=A0 20 +
=C2=A0hw/arm/orangepi.c=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0|=C2=A0 17 +
=C2=A0hw/sd/Makefile.objs=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0|=C2=A0 =C2=A01 +
=C2=A0hw/sd/allwinner-h3-sdhost.c=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0| 791 ++= ++++++++++++++++++++++++++
=C2=A0hw/sd/trace-events=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 |=C2=A0 =C2=A07 +
=C2=A0include/hw/arm/allwinner-h3.h=C2=A0 =C2=A0 =C2=A0 =C2=A0|=C2=A0 =C2= =A02 +
=C2=A0include/hw/sd/allwinner-h3-sdhost.h |=C2=A0 73 +++
=C2=A07 files changed, 911 insertions(+)
=C2=A0create mode 100644 hw/sd/allwinner-h3-sdhost.c
=C2=A0create mode 100644 include/hw/sd/allwinner-h3-sdhost.h

diff --git a/hw/arm/allwinner-h3.c b/hw/arm/allwinner-h3.c
index 4fc4c8c725..c2972caf88 100644
--- a/hw/arm/allwinner-h3.c
+++ b/hw/arm/allwinner-h3.c
@@ -50,6 +50,9 @@ static void aw_h3_init(Object *obj)

=C2=A0 =C2=A0 =C2=A0sysbus_init_child_obj(obj, "sid", &s->= sid, sizeof(s->sid),
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0TYPE_AW_H3_SID);
+
+=C2=A0 =C2=A0 sysbus_init_child_obj(obj, "mmc0", &s->mmc0= , sizeof(s->mmc0),
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 TYPE_AW_H3_SDHOST);
=C2=A0}

=C2=A0static void aw_h3_realize(DeviceState *dev, Error **errp)
@@ -217,6 +220,23 @@ static void aw_h3_realize(DeviceState *dev, Error **er= rp)
=C2=A0 =C2=A0 =C2=A0}
=C2=A0 =C2=A0 =C2=A0sysbus_mmio_map(SYS_BUS_DEVICE(&s->sid), 0, AW_H= 3_SID_BASE);

+=C2=A0 =C2=A0 /* SD/MMC */
+=C2=A0 =C2=A0 object_property_set_bool(OBJECT(&s->mmc0), true, &quo= t;realized", &err);
+=C2=A0 =C2=A0 if (err !=3D NULL) {
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 error_propagate(errp, err);
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 return;
+=C2=A0 =C2=A0 }
+=C2=A0 =C2=A0 sysbusdev =3D SYS_BUS_DEVICE(&s->mmc0);
+=C2=A0 =C2=A0 sysbus_mmio_map(sysbusdev, 0, AW_H3_MMC0_BASE);
+=C2=A0 =C2=A0 sysbus_connect_irq(sysbusdev, 0, s->irq[AW_H3_GIC_SPI_MMC= 0]);
+
+=C2=A0 =C2=A0 object_property_add_alias(OBJECT(s), "sd-bus", OBJ= ECT(&s->mmc0),
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 "sd-bus", &err);
+=C2=A0 =C2=A0 if (err) {
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 error_propagate(errp, err);
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 return;
+=C2=A0 =C2=A0 }
+
=C2=A0 =C2=A0 =C2=A0/* Universal Serial Bus */
=C2=A0 =C2=A0 =C2=A0sysbus_create_simple(TYPE_AW_H3_EHCI, AW_H3_EHCI0_BASE,=
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 s->irq[AW_H3_GIC_SPI_EHCI0]);
diff --git a/hw/arm/orangepi.c b/hw/arm/orangepi.c
index 5ef2735f81..dee3efaf08 100644
--- a/hw/arm/orangepi.c
+++ b/hw/arm/orangepi.c
@@ -39,6 +39,10 @@ typedef struct OrangePiState {
=C2=A0static void orangepi_init(MachineState *machine)
=C2=A0{
=C2=A0 =C2=A0 =C2=A0OrangePiState *s =3D g_new(OrangePiState, 1);
+=C2=A0 =C2=A0 DriveInfo *di;
+=C2=A0 =C2=A0 BlockBackend *blk;
+=C2=A0 =C2=A0 BusState *bus;
+=C2=A0 =C2=A0 DeviceState *carddev;
=C2=A0 =C2=A0 =C2=A0Error *err =3D NULL;

=C2=A0 =C2=A0 =C2=A0s->h3 =3D AW_H3(object_new(TYPE_AW_H3));
@@ -64,6 +68,18 @@ static void orangepi_init(MachineState *machine)
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0exit(1);
=C2=A0 =C2=A0 =C2=A0}

+=C2=A0 =C2=A0 /* Create and plug in the SD card */
+=C2=A0 =C2=A0 di =3D drive_get_next(IF_SD);
+=C2=A0 =C2=A0 blk =3D di ? blk_by_legacy_dinfo(di) : NULL;
+=C2=A0 =C2=A0 bus =3D qdev_get_child_bus(DEVICE(s->h3), "sd-bus&qu= ot;);
+=C2=A0 =C2=A0 if (bus =3D=3D NULL) {
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 error_report("No SD/MMC found in H3 objec= t");
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 exit(1);
+=C2=A0 =C2=A0 }
+=C2=A0 =C2=A0 carddev =3D qdev_create(bus, TYPE_SD_CARD);
+=C2=A0 =C2=A0 qdev_prop_set_drive(carddev, "drive", blk, &er= ror_fatal);
+=C2=A0 =C2=A0 object_property_set_bool(OBJECT(carddev), true, "realiz= ed", &error_fatal);
+
=C2=A0 =C2=A0 =C2=A0/* RAM */
=C2=A0 =C2=A0 =C2=A0memory_region_allocate_system_memory(&s->sdram, = NULL, "orangepi.ram",
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 m= achine->ram_size);
@@ -80,6 +96,7 @@ static void orangepi_machine_init(MachineClass *mc)
=C2=A0{
=C2=A0 =C2=A0 =C2=A0mc->desc =3D "Orange Pi PC";
=C2=A0 =C2=A0 =C2=A0mc->init =3D orangepi_init;
+=C2=A0 =C2=A0 mc->block_default_type =3D IF_SD;
=C2=A0 =C2=A0 =C2=A0mc->units_per_default_bus =3D 1;
=C2=A0 =C2=A0 =C2=A0mc->min_cpus =3D AW_H3_NUM_CPUS;
=C2=A0 =C2=A0 =C2=A0mc->max_cpus =3D AW_H3_NUM_CPUS;
diff --git a/hw/sd/Makefile.objs b/hw/sd/Makefile.objs
index a884c238df..e7cc5ab739 100644
--- a/hw/sd/Makefile.objs
+++ b/hw/sd/Makefile.objs
@@ -4,6 +4,7 @@ common-obj-$(CONFIG_SD) +=3D sd.o core.o sdmmc-internal.o =C2=A0common-obj-$(CONFIG_SDHCI) +=3D sdhci.o
=C2=A0common-obj-$(CONFIG_SDHCI_PCI) +=3D sdhci-pci.o

+obj-$(CONFIG_ALLWINNER_H3) +=3D allwinner-h3-sdhost.o
=C2=A0obj-$(CONFIG_MILKYMIST) +=3D milkymist-memcard.o
=C2=A0obj-$(CONFIG_OMAP) +=3D omap_mmc.o
=C2=A0obj-$(CONFIG_PXA2XX) +=3D pxa2xx_mmci.o
diff --git a/hw/sd/allwinner-h3-sdhost.c b/hw/sd/allwinner-h3-sdhost.c
new file mode 100644
index 0000000000..26e113a144
--- /dev/null
+++ b/hw/sd/allwinner-h3-sdhost.c
@@ -0,0 +1,791 @@
+/*
+ * Allwinner H3 SD Host Controller emulation
+ *
+ * Copyright (C) 2019 Niek Linnenbank <nieklinnenbank@gmail.com>
+ *
+ * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.=C2=A0 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.=C2=A0 If not, see <http://www.gnu.org/li= censes/>.
+ */
+
+#include "qemu/osdep.h"
+#include "qemu/log.h"
+#include "qemu/module.h"
+#include "sysemu/blockdev.h"
+#include "hw/irq.h"
+#include "hw/sd/allwinner-h3-sdhost.h"
+#include "migration/vmstate.h"
+#include "trace.h"
+
+#define TYPE_AW_H3_SDHOST_BUS "allwinner-h3-sdhost-bus"
+#define AW_H3_SDHOST_BUS(obj) \
+=C2=A0 =C2=A0 OBJECT_CHECK(SDBus, (obj), TYPE_AW_H3_SDHOST_BUS)
+
+/* SD Host register offsets */
+#define REG_SD_GCTL=C2=A0 =C2=A0 =C2=A0 =C2=A0 (0x00)=C2=A0 /* Global Cont= rol */
+#define REG_SD_CKCR=C2=A0 =C2=A0 =C2=A0 =C2=A0 (0x04)=C2=A0 /* Clock Contr= ol */
+#define REG_SD_TMOR=C2=A0 =C2=A0 =C2=A0 =C2=A0 (0x08)=C2=A0 /* Timeout */<= br> +#define REG_SD_BWDR=C2=A0 =C2=A0 =C2=A0 =C2=A0 (0x0C)=C2=A0 /* Bus Width *= /
+#define REG_SD_BKSR=C2=A0 =C2=A0 =C2=A0 =C2=A0 (0x10)=C2=A0 /* Block Size = */
+#define REG_SD_BYCR=C2=A0 =C2=A0 =C2=A0 =C2=A0 (0x14)=C2=A0 /* Byte Count = */
+#define REG_SD_CMDR=C2=A0 =C2=A0 =C2=A0 =C2=A0 (0x18)=C2=A0 /* Command */<= br> +#define REG_SD_CAGR=C2=A0 =C2=A0 =C2=A0 =C2=A0 (0x1C)=C2=A0 /* Command Arg= ument */
+#define REG_SD_RESP0=C2=A0 =C2=A0 =C2=A0 =C2=A0(0x20)=C2=A0 /* Response Ze= ro */
+#define REG_SD_RESP1=C2=A0 =C2=A0 =C2=A0 =C2=A0(0x24)=C2=A0 /* Response On= e */
+#define REG_SD_RESP2=C2=A0 =C2=A0 =C2=A0 =C2=A0(0x28)=C2=A0 /* Response Tw= o */
+#define REG_SD_RESP3=C2=A0 =C2=A0 =C2=A0 =C2=A0(0x2C)=C2=A0 /* Response Th= ree */
+#define REG_SD_IMKR=C2=A0 =C2=A0 =C2=A0 =C2=A0 (0x30)=C2=A0 /* Interrupt M= ask */
+#define REG_SD_MISR=C2=A0 =C2=A0 =C2=A0 =C2=A0 (0x34)=C2=A0 /* Masked Inte= rrupt Status */
+#define REG_SD_RISR=C2=A0 =C2=A0 =C2=A0 =C2=A0 (0x38)=C2=A0 /* Raw Interru= pt Status */
+#define REG_SD_STAR=C2=A0 =C2=A0 =C2=A0 =C2=A0 (0x3C)=C2=A0 /* Status */ +#define REG_SD_FWLR=C2=A0 =C2=A0 =C2=A0 =C2=A0 (0x40)=C2=A0 /* FIFO Water = Level */
+#define REG_SD_FUNS=C2=A0 =C2=A0 =C2=A0 =C2=A0 (0x44)=C2=A0 /* FIFO Functi= on Select */
+#define REG_SD_DBGC=C2=A0 =C2=A0 =C2=A0 =C2=A0 (0x50)=C2=A0 /* Debug Enabl= e */
+#define REG_SD_A12A=C2=A0 =C2=A0 =C2=A0 =C2=A0 (0x58)=C2=A0 /* Auto comman= d 12 argument */
+#define REG_SD_NTSR=C2=A0 =C2=A0 =C2=A0 =C2=A0 (0x5C)=C2=A0 /* SD NewTimin= g Set */
+#define REG_SD_SDBG=C2=A0 =C2=A0 =C2=A0 =C2=A0 (0x60)=C2=A0 /* SD newTimin= g Set Debug */
+#define REG_SD_HWRST=C2=A0 =C2=A0 =C2=A0 =C2=A0(0x78)=C2=A0 /* Hardware Re= set Register */
+#define REG_SD_DMAC=C2=A0 =C2=A0 =C2=A0 =C2=A0 (0x80)=C2=A0 /* Internal DM= A Controller Control */
+#define REG_SD_DLBA=C2=A0 =C2=A0 =C2=A0 =C2=A0 (0x84)=C2=A0 /* Descriptor = List Base Address */
+#define REG_SD_IDST=C2=A0 =C2=A0 =C2=A0 =C2=A0 (0x88)=C2=A0 /* Internal DM= A Controller Status */
+#define REG_SD_IDIE=C2=A0 =C2=A0 =C2=A0 =C2=A0 (0x8C)=C2=A0 /* Internal DM= A Controller IRQ Enable */
+#define REG_SD_THLDC=C2=A0 =C2=A0 =C2=A0 =C2=A0(0x100) /* Card Threshold C= ontrol */
+#define REG_SD_DSBD=C2=A0 =C2=A0 =C2=A0 =C2=A0 (0x10C) /* eMMC DDR Start B= it Detection Control */
+#define REG_SD_RES_CRC=C2=A0 =C2=A0 =C2=A0(0x110) /* Response CRC from car= d/eMMC */
+#define REG_SD_DATA7_CRC=C2=A0 =C2=A0(0x114) /* CRC Data 7 from card/eMMC = */
+#define REG_SD_DATA6_CRC=C2=A0 =C2=A0(0x118) /* CRC Data 6 from card/eMMC = */
+#define REG_SD_DATA5_CRC=C2=A0 =C2=A0(0x11C) /* CRC Data 5 from card/eMMC = */
+#define REG_SD_DATA4_CRC=C2=A0 =C2=A0(0x120) /* CRC Data 4 from card/eMMC = */
+#define REG_SD_DATA3_CRC=C2=A0 =C2=A0(0x124) /* CRC Data 3 from card/eMMC = */
+#define REG_SD_DATA2_CRC=C2=A0 =C2=A0(0x128) /* CRC Data 2 from card/eMMC = */
+#define REG_SD_DATA1_CRC=C2=A0 =C2=A0(0x12C) /* CRC Data 1 from card/eMMC = */
+#define REG_SD_DATA0_CRC=C2=A0 =C2=A0(0x130) /* CRC Data 0 from card/eMMC = */
+#define REG_SD_CRC_STA=C2=A0 =C2=A0 =C2=A0(0x134) /* CRC status from card/= eMMC during write */
+#define REG_SD_FIFO=C2=A0 =C2=A0 =C2=A0 =C2=A0 (0x200) /* Read/Write FIFO = */
+
+/* SD Host register flags */
+#define SD_GCTL_FIFO_AC_MOD=C2=A0 =C2=A0 =C2=A0(1 << 31)
+#define SD_GCTL_DDR_MOD_SEL=C2=A0 =C2=A0 =C2=A0(1 << 10)
+#define SD_GCTL_CD_DBC_ENB=C2=A0 =C2=A0 =C2=A0 (1 << 8)
+#define SD_GCTL_DMA_ENB=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0(1 << 5) +#define SD_GCTL_INT_ENB=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0(1 << 4) +#define SD_GCTL_DMA_RST=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0(1 << 2) +#define SD_GCTL_FIFO_RST=C2=A0 =C2=A0 =C2=A0 =C2=A0 (1 << 1)
+#define SD_GCTL_SOFT_RST=C2=A0 =C2=A0 =C2=A0 =C2=A0 (1 << 0)
+
+#define SD_CMDR_LOAD=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 (1 << = 31)
+#define SD_CMDR_CLKCHANGE=C2=A0 =C2=A0 =C2=A0 =C2=A0(1 << 21)
+#define SD_CMDR_WRITE=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0(1 << = 10)
+#define SD_CMDR_AUTOSTOP=C2=A0 =C2=A0 =C2=A0 =C2=A0 (1 << 12)
+#define SD_CMDR_DATA=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 (1 << = 9)
+#define SD_CMDR_RESPONSE_LONG=C2=A0 =C2=A0(1 << 7)
+#define SD_CMDR_RESPONSE=C2=A0 =C2=A0 =C2=A0 =C2=A0 (1 << 6)
+#define SD_CMDR_CMDID_MASK=C2=A0 =C2=A0 =C2=A0 (0x3f)
+
+#define SD_RISR_CARD_REMOVE=C2=A0 =C2=A0 =C2=A0(1 << 31)
+#define SD_RISR_CARD_INSERT=C2=A0 =C2=A0 =C2=A0(1 << 30)
+#define SD_RISR_AUTOCMD_DONE=C2=A0 =C2=A0 (1 << 14)
+#define SD_RISR_DATA_COMPLETE=C2=A0 =C2=A0(1 << 3)
+#define SD_RISR_CMD_COMPLETE=C2=A0 =C2=A0 (1 << 2)
+#define SD_RISR_NO_RESPONSE=C2=A0 =C2=A0 =C2=A0(1 << 1)
+
+#define SD_STAR_CARD_PRESENT=C2=A0 =C2=A0 (1 << 8)
+
+#define SD_IDST_SUM_RECEIVE_IRQ (1 << 8)
+#define SD_IDST_RECEIVE_IRQ=C2=A0 =C2=A0 =C2=A0(1 << 1)
+#define SD_IDST_TRANSMIT_IRQ=C2=A0 =C2=A0 (1 << 0)
+#define SD_IDST_IRQ_MASK=C2=A0 =C2=A0 =C2=A0 =C2=A0 (SD_IDST_RECEIVE_IRQ |= SD_IDST_TRANSMIT_IRQ | \
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0SD_IDST_SUM_RECEIVE_IRQ)
+#define SD_IDST_WR_MASK=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0(0x3ff)
+
+/* SD Host register reset values */
+#define REG_SD_GCTL_RST=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0(0x00000300)
+#define REG_SD_CKCR_RST=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0(0x0)
+#define REG_SD_TMOR_RST=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0(0xFFFFFF40)
+#define REG_SD_BWDR_RST=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0(0x0)
+#define REG_SD_BKSR_RST=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0(0x00000200)
+#define REG_SD_BYCR_RST=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0(0x00000200)
+#define REG_SD_CMDR_RST=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0(0x0)
+#define REG_SD_CAGR_RST=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0(0x0)
+#define REG_SD_RESP_RST=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0(0x0)
+#define REG_SD_IMKR_RST=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0(0x0)
+#define REG_SD_MISR_RST=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0(0x0)
+#define REG_SD_RISR_RST=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0(0x0)
+#define REG_SD_STAR_RST=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0(0x00000100)
+#define REG_SD_FWLR_RST=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0(0x000F0000)
+#define REG_SD_FUNS_RST=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0(0x0)
+#define REG_SD_DBGC_RST=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0(0x0)
+#define REG_SD_A12A_RST=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0(0x0000FFFF)
+#define REG_SD_NTSR_RST=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0(0x00000001)
+#define REG_SD_SDBG_RST=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0(0x0)
+#define REG_SD_HWRST_RST=C2=A0 =C2=A0 =C2=A0 =C2=A0 (0x00000001)
+#define REG_SD_DMAC_RST=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0(0x0)
+#define REG_SD_DLBA_RST=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0(0x0)
+#define REG_SD_IDST_RST=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0(0x0)
+#define REG_SD_IDIE_RST=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0(0x0)
+#define REG_SD_THLDC_RST=C2=A0 =C2=A0 =C2=A0 =C2=A0 (0x0)
+#define REG_SD_DSBD_RST=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0(0x0)
+#define REG_SD_RES_CRC_RST=C2=A0 =C2=A0 =C2=A0 (0x0)
+#define REG_SD_DATA_CRC_RST=C2=A0 =C2=A0 =C2=A0(0x0)
+#define REG_SD_CRC_STA_RST=C2=A0 =C2=A0 =C2=A0 (0x0)
+#define REG_SD_FIFO_RST=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0(0x0)
+
+/* Data transfer descriptor for DMA */
+typedef struct TransferDescriptor {
+=C2=A0 =C2=A0 uint32_t status; /* Status flags */
+=C2=A0 =C2=A0 uint32_t size;=C2=A0 =C2=A0/* Data buffer size */
+=C2=A0 =C2=A0 uint32_t addr;=C2=A0 =C2=A0/* Data buffer address */
+=C2=A0 =C2=A0 uint32_t next;=C2=A0 =C2=A0/* Physical address of next descr= iptor */
+} TransferDescriptor;
+
+/* Data transfer descriptor flags */
+#define DESC_STATUS_HOLD=C2=A0 =C2=A0(1 << 31) /* Set when descripto= r is in use by DMA */
+#define DESC_STATUS_ERROR=C2=A0 (1 << 30) /* Set when DMA transfer e= rror occurred */
+#define DESC_STATUS_CHAIN=C2=A0 (1 << 4)=C2=A0 /* Indicates chained = descriptor. */
+#define DESC_STATUS_FIRST=C2=A0 (1 << 3)=C2=A0 /* Set on the first d= escriptor */
+#define DESC_STATUS_LAST=C2=A0 =C2=A0(1 << 2)=C2=A0 /* Set on the la= st descriptor */
+#define DESC_STATUS_NOIRQ=C2=A0 (1 << 1)=C2=A0 /* Skip raising inter= rupt after transfer */
+
+#define DESC_SIZE_MASK=C2=A0 =C2=A0 =C2=A0(0xfffffffc)
+
+static void aw_h3_sdhost_update_irq(AwH3SDHostState *s)
+{
+=C2=A0 =C2=A0 uint32_t irq_en =3D s->global_ctl & SD_GCTL_INT_ENB;<= br> +=C2=A0 =C2=A0 uint32_t irq =3D irq_en ? s->irq_status & s->irq_m= ask : 0;
+
+=C2=A0 =C2=A0 trace_aw_h3_sdhost_update_irq(irq);
+=C2=A0 =C2=A0 qemu_set_irq(s->irq, irq);
+}
+
+static void aw_h3_sdhost_update_transfer_cnt(AwH3SDHostState *s, uint32_t = bytes)
+{
+=C2=A0 =C2=A0 if (s->transfer_cnt > bytes) {
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 s->transfer_cnt -=3D bytes;
+=C2=A0 =C2=A0 } else {
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 s->transfer_cnt =3D 0;
+=C2=A0 =C2=A0 }
+
+=C2=A0 =C2=A0 if (!s->transfer_cnt) {
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 s->irq_status |=3D SD_RISR_DATA_COMPLETE | = SD_RISR_AUTOCMD_DONE;
+=C2=A0 =C2=A0 }
+}
+
+static void aw_h3_sdhost_set_inserted(DeviceState *dev, bool inserted)
+{
+=C2=A0 =C2=A0 AwH3SDHostState *s =3D AW_H3_SDHOST(dev);
+
+=C2=A0 =C2=A0 trace_aw_h3_sdhost_set_inserted(inserted);
+
+=C2=A0 =C2=A0 if (inserted) {
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 s->irq_status |=3D SD_RISR_CARD_INSERT;
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 s->irq_status &=3D ~SD_RISR_CARD_REMOVE= ;
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 s->status |=3D SD_STAR_CARD_PRESENT;
+=C2=A0 =C2=A0 } else {
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 s->irq_status &=3D ~SD_RISR_CARD_INSERT= ;
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 s->irq_status |=3D SD_RISR_CARD_REMOVE;
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 s->status &=3D ~SD_STAR_CARD_PRESENT; +=C2=A0 =C2=A0 }
+
+=C2=A0 =C2=A0 aw_h3_sdhost_update_irq(s);
+}
+
+static void aw_h3_sdhost_send_command(AwH3SDHostState *s)
+{
+=C2=A0 =C2=A0 SDRequest request;
+=C2=A0 =C2=A0 uint8_t resp[16];
+=C2=A0 =C2=A0 int rlen;
+
+=C2=A0 =C2=A0 /* Auto clear load flag */
+=C2=A0 =C2=A0 s->command &=3D ~SD_CMDR_LOAD;
+
+=C2=A0 =C2=A0 /* Clock change does not actually interact with the SD bus *= /
+=C2=A0 =C2=A0 if (!(s->command & SD_CMDR_CLKCHANGE)) {
+
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 /* Prepare request */
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 request.cmd =3D s->command & SD_CMDR_CM= DID_MASK;
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 request.arg =3D s->command_arg;
+
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 /* Send request to SD bus */
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 rlen =3D sdbus_do_command(&s->sdbus, &a= mp;request, resp);
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 if (rlen < 0) {
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 goto error;
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 }
+
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 /* If the command has a response, store it in = the response registers */
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 if ((s->command & SD_CMDR_RESPONSE)) {<= br> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 if (rlen =3D=3D 0 ||
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0(rlen =3D=3D 4 &= ;& (s->command & SD_CMDR_RESPONSE_LONG))) {
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 goto error;
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 }
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 if (rlen !=3D 4 && rlen = !=3D 16) {
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 goto error;
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 }
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 if (rlen =3D=3D 4) {
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 s->response[0] = =3D ldl_be_p(&resp[0]);
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 s->response[1] = =3D s->response[2] =3D s->response[3] =3D 0;
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 } else {
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 s->response[0] = =3D ldl_be_p(&resp[12]);
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 s->response[1] = =3D ldl_be_p(&resp[8]);
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 s->response[2] = =3D ldl_be_p(&resp[4]);
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 s->response[3] = =3D ldl_be_p(&resp[0]);
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 }
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 }
+=C2=A0 =C2=A0 }
+
+=C2=A0 =C2=A0 /* Set interrupt status bits */
+=C2=A0 =C2=A0 s->irq_status |=3D SD_RISR_CMD_COMPLETE;
+=C2=A0 =C2=A0 return;
+
+error:
+=C2=A0 =C2=A0 s->irq_status |=3D SD_RISR_NO_RESPONSE;
+}
+
+static void aw_h3_sdhost_auto_stop(AwH3SDHostState *s)
+{
+=C2=A0 =C2=A0 /*
+=C2=A0 =C2=A0 =C2=A0* The stop command (CMD12) ensures the SD bus
+=C2=A0 =C2=A0 =C2=A0* returns to the transfer state.
+=C2=A0 =C2=A0 =C2=A0*/
+=C2=A0 =C2=A0 if ((s->command & SD_CMDR_AUTOSTOP) && (s->= ;transfer_cnt =3D=3D 0)) {
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 /* First save current command registers */
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 uint32_t saved_cmd =3D s->command;
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 uint32_t saved_arg =3D s->command_arg;
+
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 /* Prepare stop command (CMD12) */
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 s->command &=3D ~SD_CMDR_CMDID_MASK; +=C2=A0 =C2=A0 =C2=A0 =C2=A0 s->command |=3D 12; /* CMD12 */
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 s->command_arg =3D 0;
+
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 /* Put the command on SD bus */
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 aw_h3_sdhost_send_command(s);
+
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 /* Restore command values */
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 s->command =3D saved_cmd;
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 s->command_arg =3D saved_arg;
+=C2=A0 =C2=A0 }
+}
+
+static uint32_t aw_h3_sdhost_process_desc(AwH3SDHostState *s,
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 h= waddr desc_addr,
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 T= ransferDescriptor *desc,
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 b= ool is_write, uint32_t max_bytes)
+{
+=C2=A0 =C2=A0 uint32_t num_done =3D 0;
+=C2=A0 =C2=A0 uint32_t num_bytes =3D max_bytes;
+=C2=A0 =C2=A0 uint8_t buf[1024];
+
+=C2=A0 =C2=A0 /* Read descriptor */
+=C2=A0 =C2=A0 cpu_physical_memory_read(desc_addr, desc, sizeof(*desc)); +=C2=A0 =C2=A0 if (desc->size =3D=3D 0) {
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 desc->size =3D 0xffff + 1;
+=C2=A0 =C2=A0 }
+=C2=A0 =C2=A0 if (desc->size < num_bytes) {
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 num_bytes =3D desc->size;
+=C2=A0 =C2=A0 }
+
+=C2=A0 =C2=A0 trace_aw_h3_sdhost_process_desc(desc_addr, desc->size, is= _write, max_bytes);
+
+=C2=A0 =C2=A0 while (num_done < num_bytes) {
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 /* Try to completely fill the local buffer */<= br> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 uint32_t buf_bytes =3D num_bytes - num_done; +=C2=A0 =C2=A0 =C2=A0 =C2=A0 if (buf_bytes > sizeof(buf)) {
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 buf_bytes =3D sizeof(buf);
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 }
+
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 /* Write to SD bus */
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 if (is_write) {
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 cpu_physical_memory_read((desc-&= gt;addr & DESC_SIZE_MASK) + num_done,
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 buf, buf_bytes)= ;
+
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 for (uint32_t i =3D 0; i < bu= f_bytes; i++) {
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 sdbus_write_data(&= amp;s->sdbus, buf[i]);
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 }
+
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 /* Read from SD bus */
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 } else {
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 for (uint32_t i =3D 0; i < bu= f_bytes; i++) {
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 buf[i] =3D sdbus_r= ead_data(&s->sdbus);
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 }
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 cpu_physical_memory_write((desc-= >addr & DESC_SIZE_MASK) + num_done,
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0buf, buf_= bytes);
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 }
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 num_done +=3D buf_bytes;
+=C2=A0 =C2=A0 }
+
+=C2=A0 =C2=A0 /* Clear hold flag and flush descriptor */
+=C2=A0 =C2=A0 desc->status &=3D ~DESC_STATUS_HOLD;
+=C2=A0 =C2=A0 cpu_physical_memory_write(desc_addr, desc, sizeof(*desc)); +
+=C2=A0 =C2=A0 return num_done;
+}
+
+static void aw_h3_sdhost_dma(AwH3SDHostState *s)
+{
+=C2=A0 =C2=A0 TransferDescriptor desc;
+=C2=A0 =C2=A0 hwaddr desc_addr =3D s->desc_base;
+=C2=A0 =C2=A0 bool is_write =3D (s->command & SD_CMDR_WRITE);
+=C2=A0 =C2=A0 uint32_t bytes_done =3D 0;
+
+=C2=A0 =C2=A0 /* Check if DMA can be performed */
+=C2=A0 =C2=A0 if (s->byte_count =3D=3D 0 || s->block_size =3D=3D 0 |= |
+=C2=A0 =C2=A0 =C2=A0 !(s->global_ctl & SD_GCTL_DMA_ENB)) {
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 return;
+=C2=A0 =C2=A0 }
+
+=C2=A0 =C2=A0 /*
+=C2=A0 =C2=A0 =C2=A0* For read operations, data must be available on the S= D bus
+=C2=A0 =C2=A0 =C2=A0* If not, it is an error and we should not act at all<= br> +=C2=A0 =C2=A0 =C2=A0*/
+=C2=A0 =C2=A0 if (!is_write && !sdbus_data_ready(&s->sdbus)= ) {
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 return;
+=C2=A0 =C2=A0 }
+
+=C2=A0 =C2=A0 /* Process the DMA descriptors until all data is copied */ +=C2=A0 =C2=A0 while (s->byte_count > 0) {
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 bytes_done =3D aw_h3_sdhost_process_desc(s, de= sc_addr, &desc,
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0is_write, s->byte_count);
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 aw_h3_sdhost_update_transfer_cnt(s, bytes_done= );
+
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 if (bytes_done <=3D s->byte_count) {
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 s->byte_count -=3D bytes_done= ;
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 } else {
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 s->byte_count =3D 0;
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 }
+
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 if (desc.status & DESC_STATUS_LAST) {
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 break;
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 } else {
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 desc_addr =3D desc.next;
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 }
+=C2=A0 =C2=A0 }
+
+=C2=A0 =C2=A0 /* Raise IRQ to signal DMA is completed */
+=C2=A0 =C2=A0 s->irq_status |=3D SD_RISR_DATA_COMPLETE | SD_RISR_AUTOCM= D_DONE;
+
+=C2=A0 =C2=A0 /* Update DMAC bits */
+=C2=A0 =C2=A0 if (is_write) {
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 s->dmac_status |=3D SD_IDST_TRANSMIT_IRQ; +=C2=A0 =C2=A0 } else {
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 s->dmac_status |=3D (SD_IDST_SUM_RECEIVE_IR= Q | SD_IDST_RECEIVE_IRQ);
+=C2=A0 =C2=A0 }
+}
+
+static uint64_t aw_h3_sdhost_read(void *opaque, hwaddr offset,
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 unsigned size)
+{
+=C2=A0 =C2=A0 AwH3SDHostState *s =3D (AwH3SDHostState *)opaque;
+=C2=A0 =C2=A0 uint32_t res =3D 0;
+
+=C2=A0 =C2=A0 switch (offset) {
+=C2=A0 =C2=A0 case REG_SD_GCTL:=C2=A0 =C2=A0 =C2=A0 /* Global Control */ +=C2=A0 =C2=A0 =C2=A0 =C2=A0 res =3D s->global_ctl;
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 break;
+=C2=A0 =C2=A0 case REG_SD_CKCR:=C2=A0 =C2=A0 =C2=A0 /* Clock Control */ +=C2=A0 =C2=A0 =C2=A0 =C2=A0 res =3D s->clock_ctl;
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 break;
+=C2=A0 =C2=A0 case REG_SD_TMOR:=C2=A0 =C2=A0 =C2=A0 /* Timeout */
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 res =3D s->timeout;
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 break;
+=C2=A0 =C2=A0 case REG_SD_BWDR:=C2=A0 =C2=A0 =C2=A0 /* Bus Width */
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 res =3D s->bus_width;
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 break;
+=C2=A0 =C2=A0 case REG_SD_BKSR:=C2=A0 =C2=A0 =C2=A0 /* Block Size */
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 res =3D s->block_size;
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 break;
+=C2=A0 =C2=A0 case REG_SD_BYCR:=C2=A0 =C2=A0 =C2=A0 /* Byte Count */
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 res =3D s->byte_count;
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 break;
+=C2=A0 =C2=A0 case REG_SD_CMDR:=C2=A0 =C2=A0 =C2=A0 /* Command */
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 res =3D s->command;
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 break;
+=C2=A0 =C2=A0 case REG_SD_CAGR:=C2=A0 =C2=A0 =C2=A0 /* Command Argument */=
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 res =3D s->command_arg;
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 break;
+=C2=A0 =C2=A0 case REG_SD_RESP0:=C2=A0 =C2=A0 =C2=A0/* Response Zero */ +=C2=A0 =C2=A0 =C2=A0 =C2=A0 res =3D s->response[0];
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 break;
+=C2=A0 =C2=A0 case REG_SD_RESP1:=C2=A0 =C2=A0 =C2=A0/* Response One */
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 res =3D s->response[1];
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 break;
+=C2=A0 =C2=A0 case REG_SD_RESP2:=C2=A0 =C2=A0 =C2=A0/* Response Two */
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 res =3D s->response[2];
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 break;
+=C2=A0 =C2=A0 case REG_SD_RESP3:=C2=A0 =C2=A0 =C2=A0/* Response Three */ +=C2=A0 =C2=A0 =C2=A0 =C2=A0 res =3D s->response[3];
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 break;
+=C2=A0 =C2=A0 case REG_SD_IMKR:=C2=A0 =C2=A0 =C2=A0 /* Interrupt Mask */ +=C2=A0 =C2=A0 =C2=A0 =C2=A0 res =3D s->irq_mask;
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 break;
+=C2=A0 =C2=A0 case REG_SD_MISR:=C2=A0 =C2=A0 =C2=A0 /* Masked Interrupt St= atus */
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 res =3D s->irq_status & s->irq_mask;=
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 break;
+=C2=A0 =C2=A0 case REG_SD_RISR:=C2=A0 =C2=A0 =C2=A0 /* Raw Interrupt Statu= s */
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 res =3D s->irq_status;
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 break;
+=C2=A0 =C2=A0 case REG_SD_STAR:=C2=A0 =C2=A0 =C2=A0 /* Status */
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 res =3D s->status;
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 break;
+=C2=A0 =C2=A0 case REG_SD_FWLR:=C2=A0 =C2=A0 =C2=A0 /* FIFO Water Level */=
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 res =3D s->fifo_wlevel;
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 break;
+=C2=A0 =C2=A0 case REG_SD_FUNS:=C2=A0 =C2=A0 =C2=A0 /* FIFO Function Selec= t */
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 res =3D s->fifo_func_sel;
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 break;
+=C2=A0 =C2=A0 case REG_SD_DBGC:=C2=A0 =C2=A0 =C2=A0 /* Debug Enable */
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 res =3D s->debug_enable;
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 break;
+=C2=A0 =C2=A0 case REG_SD_A12A:=C2=A0 =C2=A0 =C2=A0 /* Auto command 12 arg= ument */
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 res =3D s->auto12_arg;
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 break;
+=C2=A0 =C2=A0 case REG_SD_NTSR:=C2=A0 =C2=A0 =C2=A0 /* SD NewTiming Set */=
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 res =3D s->newtiming_set;
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 break;
+=C2=A0 =C2=A0 case REG_SD_SDBG:=C2=A0 =C2=A0 =C2=A0 /* SD newTiming Set De= bug */
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 res =3D s->newtiming_debug;
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 break;
+=C2=A0 =C2=A0 case REG_SD_HWRST:=C2=A0 =C2=A0 =C2=A0/* Hardware Reset Regi= ster */
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 res =3D s->hardware_rst;
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 break;
+=C2=A0 =C2=A0 case REG_SD_DMAC:=C2=A0 =C2=A0 =C2=A0 /* Internal DMA Contro= ller Control */
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 res =3D s->dmac;
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 break;
+=C2=A0 =C2=A0 case REG_SD_DLBA:=C2=A0 =C2=A0 =C2=A0 /* Descriptor List Bas= e Address */
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 res =3D s->desc_base;
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 break;
+=C2=A0 =C2=A0 case REG_SD_IDST:=C2=A0 =C2=A0 =C2=A0 /* Internal DMA Contro= ller Status */
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 res =3D s->dmac_status;
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 break;
+=C2=A0 =C2=A0 case REG_SD_IDIE:=C2=A0 =C2=A0 =C2=A0 /* Internal DMA Contro= ller Interrupt Enable */
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 res =3D s->dmac_irq;
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 break;
+=C2=A0 =C2=A0 case REG_SD_THLDC:=C2=A0 =C2=A0 =C2=A0/* Card Threshold Cont= rol */
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 res =3D s->card_threshold;
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 break;
+=C2=A0 =C2=A0 case REG_SD_DSBD:=C2=A0 =C2=A0 =C2=A0 /* eMMC DDR Start Bit = Detection Control */
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 res =3D s->startbit_detect;
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 break;
+=C2=A0 =C2=A0 case REG_SD_RES_CRC:=C2=A0 =C2=A0/* Response CRC from card/e= MMC */
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 res =3D s->response_crc;
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 break;
+=C2=A0 =C2=A0 case REG_SD_DATA7_CRC: /* CRC Data 7 from card/eMMC */
+=C2=A0 =C2=A0 case REG_SD_DATA6_CRC: /* CRC Data 6 from card/eMMC */
+=C2=A0 =C2=A0 case REG_SD_DATA5_CRC: /* CRC Data 5 from card/eMMC */
+=C2=A0 =C2=A0 case REG_SD_DATA4_CRC: /* CRC Data 4 from card/eMMC */
+=C2=A0 =C2=A0 case REG_SD_DATA3_CRC: /* CRC Data 3 from card/eMMC */
+=C2=A0 =C2=A0 case REG_SD_DATA2_CRC: /* CRC Data 2 from card/eMMC */
+=C2=A0 =C2=A0 case REG_SD_DATA1_CRC: /* CRC Data 1 from card/eMMC */
+=C2=A0 =C2=A0 case REG_SD_DATA0_CRC: /* CRC Data 0 from card/eMMC */
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 res =3D s->data_crc[((offset - REG_SD_DATA7= _CRC) / sizeof(uint32_t))];
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 break;
+=C2=A0 =C2=A0 case REG_SD_CRC_STA:=C2=A0 =C2=A0/* CRC status from card/eMM= C in write operation */
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 res =3D s->status_crc;
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 break;
+=C2=A0 =C2=A0 case REG_SD_FIFO:=C2=A0 =C2=A0 =C2=A0 /* Read/Write FIFO */<= br> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 if (sdbus_data_ready(&s->sdbus)) {
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 res =3D sdbus_read_data(&s-&= gt;sdbus);
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 res |=3D sdbus_read_data(&s-= >sdbus) << 8;
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 res |=3D sdbus_read_data(&s-= >sdbus) << 16;
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 res |=3D sdbus_read_data(&s-= >sdbus) << 24;
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 aw_h3_sdhost_update_transfer_cnt= (s, sizeof(uint32_t));
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 aw_h3_sdhost_auto_stop(s);
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 aw_h3_sdhost_update_irq(s);
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 } else {
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 qemu_log_mask(LOG_GUEST_ERROR, &= quot;%s: no data ready on SD bus\n",
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 __func__);
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 }
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 break;
+=C2=A0 =C2=A0 default:
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad o= ffset %"HWADDR_PRIx"\n",
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 __func__, offset);
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 res =3D 0;
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 break;
+=C2=A0 =C2=A0 }
+
+=C2=A0 =C2=A0 trace_aw_h3_sdhost_read(offset, res, size);
+=C2=A0 =C2=A0 return res;
+}
+
+static void aw_h3_sdhost_write(void *opaque, hwaddr offset,
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0uint64_t value, unsigned size)
+{
+=C2=A0 =C2=A0 AwH3SDHostState *s =3D (AwH3SDHostState *)opaque;
+
+=C2=A0 =C2=A0 trace_aw_h3_sdhost_write(offset, value, size);
+
+=C2=A0 =C2=A0 switch (offset) {
+=C2=A0 =C2=A0 case REG_SD_GCTL:=C2=A0 =C2=A0 =C2=A0 /* Global Control */ +=C2=A0 =C2=A0 =C2=A0 =C2=A0 s->global_ctl =3D value;
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 s->global_ctl &=3D ~(SD_GCTL_DMA_RST | = SD_GCTL_FIFO_RST |
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0SD_GCTL_SOFT_RST);
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 aw_h3_sdhost_update_irq(s);
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 break;
+=C2=A0 =C2=A0 case REG_SD_CKCR:=C2=A0 =C2=A0 =C2=A0 /* Clock Control */ +=C2=A0 =C2=A0 =C2=A0 =C2=A0 s->clock_ctl =3D value;
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 break;
+=C2=A0 =C2=A0 case REG_SD_TMOR:=C2=A0 =C2=A0 =C2=A0 /* Timeout */
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 s->timeout =3D value;
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 break;
+=C2=A0 =C2=A0 case REG_SD_BWDR:=C2=A0 =C2=A0 =C2=A0 /* Bus Width */
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 s->bus_width =3D value;
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 break;
+=C2=A0 =C2=A0 case REG_SD_BKSR:=C2=A0 =C2=A0 =C2=A0 /* Block Size */
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 s->block_size =3D value;
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 break;
+=C2=A0 =C2=A0 case REG_SD_BYCR:=C2=A0 =C2=A0 =C2=A0 /* Byte Count */
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 s->byte_count =3D value;
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 s->transfer_cnt =3D value;
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 break;
+=C2=A0 =C2=A0 case REG_SD_CMDR:=C2=A0 =C2=A0 =C2=A0 /* Command */
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 s->command =3D value;
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 if (value & SD_CMDR_LOAD) {
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 aw_h3_sdhost_send_command(s); +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 aw_h3_sdhost_dma(s);
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 aw_h3_sdhost_auto_stop(s);
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 }
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 aw_h3_sdhost_update_irq(s);
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 break;
+=C2=A0 =C2=A0 case REG_SD_CAGR:=C2=A0 =C2=A0 =C2=A0 /* Command Argument */=
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 s->command_arg =3D value;
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 break;
+=C2=A0 =C2=A0 case REG_SD_RESP0:=C2=A0 =C2=A0 =C2=A0/* Response Zero */ +=C2=A0 =C2=A0 =C2=A0 =C2=A0 s->response[0] =3D value;
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 break;
+=C2=A0 =C2=A0 case REG_SD_RESP1:=C2=A0 =C2=A0 =C2=A0/* Response One */
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 s->response[1] =3D value;
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 break;
+=C2=A0 =C2=A0 case REG_SD_RESP2:=C2=A0 =C2=A0 =C2=A0/* Response Two */
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 s->response[2] =3D value;
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 break;
+=C2=A0 =C2=A0 case REG_SD_RESP3:=C2=A0 =C2=A0 =C2=A0/* Response Three */ +=C2=A0 =C2=A0 =C2=A0 =C2=A0 s->response[3] =3D value;
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 break;
+=C2=A0 =C2=A0 case REG_SD_IMKR:=C2=A0 =C2=A0 =C2=A0 /* Interrupt Mask */ +=C2=A0 =C2=A0 =C2=A0 =C2=A0 s->irq_mask =3D value;
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 aw_h3_sdhost_update_irq(s);
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 break;
+=C2=A0 =C2=A0 case REG_SD_MISR:=C2=A0 =C2=A0 =C2=A0 /* Masked Interrupt St= atus */
+=C2=A0 =C2=A0 case REG_SD_RISR:=C2=A0 =C2=A0 =C2=A0 /* Raw Interrupt Statu= s */
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 s->irq_status &=3D ~value;
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 aw_h3_sdhost_update_irq(s);
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 break;
+=C2=A0 =C2=A0 case REG_SD_STAR:=C2=A0 =C2=A0 =C2=A0 /* Status */
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 s->status &=3D ~value;
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 aw_h3_sdhost_update_irq(s);
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 break;
+=C2=A0 =C2=A0 case REG_SD_FWLR:=C2=A0 =C2=A0 =C2=A0 /* FIFO Water Level */=
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 s->fifo_wlevel =3D value;
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 break;
+=C2=A0 =C2=A0 case REG_SD_FUNS:=C2=A0 =C2=A0 =C2=A0 /* FIFO Function Selec= t */
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 s->fifo_func_sel =3D value;
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 break;
+=C2=A0 =C2=A0 case REG_SD_DBGC:=C2=A0 =C2=A0 =C2=A0 /* Debug Enable */
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 s->debug_enable =3D value;
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 break;
+=C2=A0 =C2=A0 case REG_SD_A12A:=C2=A0 =C2=A0 =C2=A0 /* Auto command 12 arg= ument */
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 s->auto12_arg =3D value;
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 break;
+=C2=A0 =C2=A0 case REG_SD_NTSR:=C2=A0 =C2=A0 =C2=A0 /* SD NewTiming Set */=
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 s->newtiming_set =3D value;
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 break;
+=C2=A0 =C2=A0 case REG_SD_SDBG:=C2=A0 =C2=A0 =C2=A0 /* SD newTiming Set De= bug */
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 s->newtiming_debug =3D value;
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 break;
+=C2=A0 =C2=A0 case REG_SD_HWRST:=C2=A0 =C2=A0 =C2=A0/* Hardware Reset Regi= ster */
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 s->hardware_rst =3D value;
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 break;
+=C2=A0 =C2=A0 case REG_SD_DMAC:=C2=A0 =C2=A0 =C2=A0 /* Internal DMA Contro= ller Control */
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 s->dmac =3D value;
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 aw_h3_sdhost_update_irq(s);
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 break;
+=C2=A0 =C2=A0 case REG_SD_DLBA:=C2=A0 =C2=A0 =C2=A0 /* Descriptor List Bas= e Address */
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 s->desc_base =3D value;
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 break;
+=C2=A0 =C2=A0 case REG_SD_IDST:=C2=A0 =C2=A0 =C2=A0 /* Internal DMA Contro= ller Status */
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 s->dmac_status &=3D (~SD_IDST_WR_MASK) = | (~value & SD_IDST_WR_MASK);
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 aw_h3_sdhost_update_irq(s);
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 break;
+=C2=A0 =C2=A0 case REG_SD_IDIE:=C2=A0 =C2=A0 =C2=A0 /* Internal DMA Contro= ller Interrupt Enable */
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 s->dmac_irq =3D value;
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 aw_h3_sdhost_update_irq(s);
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 break;
+=C2=A0 =C2=A0 case REG_SD_THLDC:=C2=A0 =C2=A0 =C2=A0/* Card Threshold Cont= rol */
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 s->card_threshold =3D value;
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 break;
+=C2=A0 =C2=A0 case REG_SD_DSBD:=C2=A0 =C2=A0 =C2=A0 /* eMMC DDR Start Bit = Detection Control */
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 s->startbit_detect =3D value;
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 break;
+=C2=A0 =C2=A0 case REG_SD_FIFO:=C2=A0 =C2=A0 =C2=A0 /* Read/Write FIFO */<= br> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 sdbus_write_data(&s->sdbus, value &= 0xff);
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 sdbus_write_data(&s->sdbus, (value >= > 8) & 0xff);
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 sdbus_write_data(&s->sdbus, (value >= > 16) & 0xff);
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 sdbus_write_data(&s->sdbus, (value >= > 24) & 0xff);
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 aw_h3_sdhost_update_transfer_cnt(s, sizeof(uin= t32_t));
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 aw_h3_sdhost_auto_stop(s);
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 aw_h3_sdhost_update_irq(s);
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 break;
+=C2=A0 =C2=A0 case REG_SD_RES_CRC:=C2=A0 =C2=A0/* Response CRC from card/e= MMC */
+=C2=A0 =C2=A0 case REG_SD_DATA7_CRC: /* CRC Data 7 from card/eMMC */
+=C2=A0 =C2=A0 case REG_SD_DATA6_CRC: /* CRC Data 6 from card/eMMC */
+=C2=A0 =C2=A0 case REG_SD_DATA5_CRC: /* CRC Data 5 from card/eMMC */
+=C2=A0 =C2=A0 case REG_SD_DATA4_CRC: /* CRC Data 4 from card/eMMC */
+=C2=A0 =C2=A0 case REG_SD_DATA3_CRC: /* CRC Data 3 from card/eMMC */
+=C2=A0 =C2=A0 case REG_SD_DATA2_CRC: /* CRC Data 2 from card/eMMC */
+=C2=A0 =C2=A0 case REG_SD_DATA1_CRC: /* CRC Data 1 from card/eMMC */
+=C2=A0 =C2=A0 case REG_SD_DATA0_CRC: /* CRC Data 0 from card/eMMC */
+=C2=A0 =C2=A0 case REG_SD_CRC_STA:=C2=A0 =C2=A0/* CRC status from card/eMM= C in write operation */
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 break;
+=C2=A0 =C2=A0 default:
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad o= ffset %"HWADDR_PRIx"\n",
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 __func__, offset);
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 break;
+=C2=A0 =C2=A0 }
+}
+
+static const MemoryRegionOps aw_h3_sdhost_ops =3D {
+=C2=A0 =C2=A0 .read =3D aw_h3_sdhost_read,
+=C2=A0 =C2=A0 .write =3D aw_h3_sdhost_write,
+=C2=A0 =C2=A0 .endianness =3D DEVICE_NATIVE_ENDIAN,
+};
+
+static const VMStateDescription vmstate_aw_h3_sdhost =3D {
+=C2=A0 =C2=A0 .name =3D TYPE_AW_H3_SDHOST,
+=C2=A0 =C2=A0 .version_id =3D 1,
+=C2=A0 =C2=A0 .minimum_version_id =3D 1,
+=C2=A0 =C2=A0 .fields =3D (VMStateField[]) {
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 VMSTATE_UINT32(global_ctl, AwH3SDHostState), +=C2=A0 =C2=A0 =C2=A0 =C2=A0 VMSTATE_UINT32(clock_ctl, AwH3SDHostState), +=C2=A0 =C2=A0 =C2=A0 =C2=A0 VMSTATE_UINT32(timeout, AwH3SDHostState),
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 VMSTATE_UINT32(bus_width, AwH3SDHostState), +=C2=A0 =C2=A0 =C2=A0 =C2=A0 VMSTATE_UINT32(block_size, AwH3SDHostState), +=C2=A0 =C2=A0 =C2=A0 =C2=A0 VMSTATE_UINT32(byte_count, AwH3SDHostState), +=C2=A0 =C2=A0 =C2=A0 =C2=A0 VMSTATE_UINT32(transfer_cnt, AwH3SDHostState),=
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 VMSTATE_UINT32(command, AwH3SDHostState),
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 VMSTATE_UINT32(command_arg, AwH3SDHostState),<= br> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 VMSTATE_UINT32_ARRAY(response, AwH3SDHostState= , 4),
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 VMSTATE_UINT32(irq_mask, AwH3SDHostState),
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 VMSTATE_UINT32(irq_status, AwH3SDHostState), +=C2=A0 =C2=A0 =C2=A0 =C2=A0 VMSTATE_UINT32(status, AwH3SDHostState),
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 VMSTATE_UINT32(fifo_wlevel, AwH3SDHostState),<= br> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 VMSTATE_UINT32(fifo_func_sel, AwH3SDHostState)= ,
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 VMSTATE_UINT32(debug_enable, AwH3SDHostState),=
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 VMSTATE_UINT32(auto12_arg, AwH3SDHostState), +=C2=A0 =C2=A0 =C2=A0 =C2=A0 VMSTATE_UINT32(newtiming_set, AwH3SDHostState)= ,
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 VMSTATE_UINT32(newtiming_debug, AwH3SDHostStat= e),
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 VMSTATE_UINT32(hardware_rst, AwH3SDHostState),=
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 VMSTATE_UINT32(dmac, AwH3SDHostState),
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 VMSTATE_UINT32(desc_base, AwH3SDHostState), +=C2=A0 =C2=A0 =C2=A0 =C2=A0 VMSTATE_UINT32(dmac_status, AwH3SDHostState),<= br> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 VMSTATE_UINT32(dmac_irq, AwH3SDHostState),
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 VMSTATE_UINT32(card_threshold, AwH3SDHostState= ),
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 VMSTATE_UINT32(startbit_detect, AwH3SDHostStat= e),
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 VMSTATE_UINT32(response_crc, AwH3SDHostState),=
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 VMSTATE_UINT32_ARRAY(data_crc, AwH3SDHostState= , 8),
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 VMSTATE_UINT32(status_crc, AwH3SDHostState), +=C2=A0 =C2=A0 =C2=A0 =C2=A0 VMSTATE_END_OF_LIST()
+=C2=A0 =C2=A0 }
+};
+
+static void aw_h3_sdhost_init(Object *obj)
+{
+=C2=A0 =C2=A0 AwH3SDHostState *s =3D AW_H3_SDHOST(obj);
+
+=C2=A0 =C2=A0 qbus_create_inplace(&s->sdbus, sizeof(s->sdbus), +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 TYPE_AW_H3_SDHOST_BUS, DEVICE(s), "sd-bus");
+
+=C2=A0 =C2=A0 memory_region_init_io(&s->iomem, obj, &aw_h3_sdho= st_ops, s,
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 TYPE_AW_H3_SDHOST, AW_H3_SDHOST_REGS_MEM_SIZE);
+=C2=A0 =C2=A0 sysbus_init_mmio(SYS_BUS_DEVICE(s), &s->iomem);
+=C2=A0 =C2=A0 sysbus_init_irq(SYS_BUS_DEVICE(s), &s->irq);
+}
+
+static void aw_h3_sdhost_reset(DeviceState *dev)
+{
+=C2=A0 =C2=A0 AwH3SDHostState *s =3D AW_H3_SDHOST(dev);
+
+=C2=A0 =C2=A0 s->global_ctl =3D REG_SD_GCTL_RST;
+=C2=A0 =C2=A0 s->clock_ctl =3D REG_SD_CKCR_RST;
+=C2=A0 =C2=A0 s->timeout =3D REG_SD_TMOR_RST;
+=C2=A0 =C2=A0 s->bus_width =3D REG_SD_BWDR_RST;
+=C2=A0 =C2=A0 s->block_size =3D REG_SD_BKSR_RST;
+=C2=A0 =C2=A0 s->byte_count =3D REG_SD_BYCR_RST;
+=C2=A0 =C2=A0 s->transfer_cnt =3D 0;
+
+=C2=A0 =C2=A0 s->command =3D REG_SD_CMDR_RST;
+=C2=A0 =C2=A0 s->command_arg =3D REG_SD_CAGR_RST;
+
+=C2=A0 =C2=A0 for (int i =3D 0; i < sizeof(s->response) / sizeof(s-&= gt;response[0]); i++) {
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 s->response[i] =3D REG_SD_RESP_RST;
+=C2=A0 =C2=A0 }
+
+=C2=A0 =C2=A0 s->irq_mask =3D REG_SD_IMKR_RST;
+=C2=A0 =C2=A0 s->irq_status =3D REG_SD_RISR_RST;
+=C2=A0 =C2=A0 s->status =3D REG_SD_STAR_RST;
+
+=C2=A0 =C2=A0 s->fifo_wlevel =3D REG_SD_FWLR_RST;
+=C2=A0 =C2=A0 s->fifo_func_sel =3D REG_SD_FUNS_RST;
+=C2=A0 =C2=A0 s->debug_enable =3D REG_SD_DBGC_RST;
+=C2=A0 =C2=A0 s->auto12_arg =3D REG_SD_A12A_RST;
+=C2=A0 =C2=A0 s->newtiming_set =3D REG_SD_NTSR_RST;
+=C2=A0 =C2=A0 s->newtiming_debug =3D REG_SD_SDBG_RST;
+=C2=A0 =C2=A0 s->hardware_rst =3D REG_SD_HWRST_RST;
+=C2=A0 =C2=A0 s->dmac =3D REG_SD_DMAC_RST;
+=C2=A0 =C2=A0 s->desc_base =3D REG_SD_DLBA_RST;
+=C2=A0 =C2=A0 s->dmac_status =3D REG_SD_IDST_RST;
+=C2=A0 =C2=A0 s->dmac_irq =3D REG_SD_IDIE_RST;
+=C2=A0 =C2=A0 s->card_threshold =3D REG_SD_THLDC_RST;
+=C2=A0 =C2=A0 s->startbit_detect =3D REG_SD_DSBD_RST;
+=C2=A0 =C2=A0 s->response_crc =3D REG_SD_RES_CRC_RST;
+
+=C2=A0 =C2=A0 for (int i =3D 0; i < sizeof(s->data_crc) / sizeof(s-&= gt;data_crc[0]); i++) {
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 s->data_crc[i] =3D REG_SD_DATA_CRC_RST;
+=C2=A0 =C2=A0 }
+
+=C2=A0 =C2=A0 s->status_crc =3D REG_SD_CRC_STA_RST;
+}
+
+static void aw_h3_sdhost_bus_class_init(ObjectClass *klass, void *data) +{
+=C2=A0 =C2=A0 SDBusClass *sbc =3D SD_BUS_CLASS(klass);
+
+=C2=A0 =C2=A0 sbc->set_inserted =3D aw_h3_sdhost_set_inserted;
+}
+
+static void aw_h3_sdhost_class_init(ObjectClass *klass, void *data)
+{
+=C2=A0 =C2=A0 DeviceClass *dc =3D DEVICE_CLASS(klass);
+
+=C2=A0 =C2=A0 dc->reset =3D aw_h3_sdhost_reset;
+=C2=A0 =C2=A0 dc->vmsd =3D &vmstate_aw_h3_sdhost;
+}
+
+static TypeInfo aw_h3_sdhost_info =3D {
+=C2=A0 =C2=A0 .name=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =3D TYPE_AW_H3_SDHOS= T,
+=C2=A0 =C2=A0 .parent=C2=A0 =C2=A0 =C2=A0 =C2=A0 =3D TYPE_SYS_BUS_DEVICE,<= br> +=C2=A0 =C2=A0 .instance_size =3D sizeof(AwH3SDHostState),
+=C2=A0 =C2=A0 .class_init=C2=A0 =C2=A0 =3D aw_h3_sdhost_class_init,
+=C2=A0 =C2=A0 .instance_init =3D aw_h3_sdhost_init,
+};
+
+static const TypeInfo aw_h3_sdhost_bus_info =3D {
+=C2=A0 =C2=A0 .name =3D TYPE_AW_H3_SDHOST_BUS,
+=C2=A0 =C2=A0 .parent =3D TYPE_SD_BUS,
+=C2=A0 =C2=A0 .instance_size =3D sizeof(SDBus),
+=C2=A0 =C2=A0 .class_init =3D aw_h3_sdhost_bus_class_init,
+};
+
+static void aw_h3_sdhost_register_types(void)
+{
+=C2=A0 =C2=A0 type_register_static(&aw_h3_sdhost_info);
+=C2=A0 =C2=A0 type_register_static(&aw_h3_sdhost_bus_info);
+}
+
+type_init(aw_h3_sdhost_register_types)
diff --git a/hw/sd/trace-events b/hw/sd/trace-events
index efcff666a2..c672a201b5 100644
--- a/hw/sd/trace-events
+++ b/hw/sd/trace-events
@@ -1,5 +1,12 @@
=C2=A0# See docs/devel/tracing.txt for syntax documentation.

+# allwinner-h3-sdhost.c
+aw_h3_sdhost_set_inserted(bool inserted) "inserted %u"
+aw_h3_sdhost_process_desc(uint64_t desc_addr, uint32_t desc_size, bool is_= write, uint32_t max_bytes) "desc_addr 0x%" PRIx64 " desc_siz= e %u is_write %u max_bytes %u"
+aw_h3_sdhost_read(uint64_t offset, uint64_t data, unsigned size) "off= set 0x%" PRIx64 " data 0x%" PRIx64 " size %u"
+aw_h3_sdhost_write(uint64_t offset, uint64_t data, unsigned size) "of= fset 0x%" PRIx64 " data 0x%" PRIx64 " size %u"
+aw_h3_sdhost_update_irq(uint32_t irq) "IRQ bits 0x%x"
+
=C2=A0# bcm2835_sdhost.c
=C2=A0bcm2835_sdhost_read(uint64_t offset, uint64_t data, unsigned size) &q= uot;offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u&quo= t;
=C2=A0bcm2835_sdhost_write(uint64_t offset, uint64_t data, unsigned size) &= quot;offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u&qu= ot;
diff --git a/include/hw/arm/allwinner-h3.h b/include/hw/arm/allwinner-h3.h<= br> index 33602599eb..7aff4ebbd2 100644
--- a/include/hw/arm/allwinner-h3.h
+++ b/include/hw/arm/allwinner-h3.h
@@ -30,6 +30,7 @@
=C2=A0#include "hw/misc/allwinner-h3-cpucfg.h"
=C2=A0#include "hw/misc/allwinner-h3-syscon.h"
=C2=A0#include "hw/misc/allwinner-h3-sid.h"
+#include "hw/sd/allwinner-h3-sdhost.h"
=C2=A0#include "target/arm/cpu.h"

=C2=A0#define AW_H3_SRAM_A1_BASE=C2=A0 =C2=A0 =C2=A0(0x00000000)
@@ -117,6 +118,7 @@ typedef struct AwH3State {
=C2=A0 =C2=A0 =C2=A0AwH3CpuCfgState cpucfg;
=C2=A0 =C2=A0 =C2=A0AwH3SysconState syscon;
=C2=A0 =C2=A0 =C2=A0AwH3SidState sid;
+=C2=A0 =C2=A0 AwH3SDHostState mmc0;
=C2=A0 =C2=A0 =C2=A0GICState gic;
=C2=A0 =C2=A0 =C2=A0MemoryRegion sram_a1;
=C2=A0 =C2=A0 =C2=A0MemoryRegion sram_a2;
diff --git a/include/hw/sd/allwinner-h3-sdhost.h b/include/hw/sd/allwinner-= h3-sdhost.h
new file mode 100644
index 0000000000..6c898a3c84
--- /dev/null
+++ b/include/hw/sd/allwinner-h3-sdhost.h
@@ -0,0 +1,73 @@
+/*
+ * Allwinner H3 SD Host Controller emulation
+ *
+ * Copyright (C) 2019 Niek Linnenbank <nieklinnenbank@gmail.com>
+ *
+ * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.=C2=A0 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.=C2=A0 If not, see <http://www.gnu.org/li= censes/>.
+ */
+
+#ifndef ALLWINNER_H3_SDHOST_H
+#define ALLWINNER_H3_SDHOST_H
+
+#include "hw/sysbus.h"
+#include "hw/sd/sd.h"
+
+#define AW_H3_SDHOST_REGS_MEM_SIZE=C2=A0 (1024)
+
+#define TYPE_AW_H3_SDHOST "allwinner-h3-sdhost"
+#define AW_H3_SDHOST(obj) \
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 OBJECT_CHECK(AwH3SDHostState, (obj), TYPE_AW_H= 3_SDHOST)
+
+typedef struct {
+=C2=A0 =C2=A0 SysBusDevice busdev;
+=C2=A0 =C2=A0 SDBus sdbus;
+=C2=A0 =C2=A0 MemoryRegion iomem;
+
+=C2=A0 =C2=A0 uint32_t global_ctl;
+=C2=A0 =C2=A0 uint32_t clock_ctl;
+=C2=A0 =C2=A0 uint32_t timeout;
+=C2=A0 =C2=A0 uint32_t bus_width;
+=C2=A0 =C2=A0 uint32_t block_size;
+=C2=A0 =C2=A0 uint32_t byte_count;
+=C2=A0 =C2=A0 uint32_t transfer_cnt;
+
+=C2=A0 =C2=A0 uint32_t command;
+=C2=A0 =C2=A0 uint32_t command_arg;
+=C2=A0 =C2=A0 uint32_t response[4];
+
+=C2=A0 =C2=A0 uint32_t irq_mask;
+=C2=A0 =C2=A0 uint32_t irq_status;
+=C2=A0 =C2=A0 uint32_t status;
+
+=C2=A0 =C2=A0 uint32_t fifo_wlevel;
+=C2=A0 =C2=A0 uint32_t fifo_func_sel;
+=C2=A0 =C2=A0 uint32_t debug_enable;
+=C2=A0 =C2=A0 uint32_t auto12_arg;
+=C2=A0 =C2=A0 uint32_t newtiming_set;
+=C2=A0 =C2=A0 uint32_t newtiming_debug;
+=C2=A0 =C2=A0 uint32_t hardware_rst;
+=C2=A0 =C2=A0 uint32_t dmac;
+=C2=A0 =C2=A0 uint32_t desc_base;
+=C2=A0 =C2=A0 uint32_t dmac_status;
+=C2=A0 =C2=A0 uint32_t dmac_irq;
+=C2=A0 =C2=A0 uint32_t card_threshold;
+=C2=A0 =C2=A0 uint32_t startbit_detect;
+=C2=A0 =C2=A0 uint32_t response_crc;
+=C2=A0 =C2=A0 uint32_t data_crc[8];
+=C2=A0 =C2=A0 uint32_t status_crc;
+
+=C2=A0 =C2=A0 qemu_irq irq;
+} AwH3SDHostState;
+
+#endif
--
2.17.1



--
Niek Linnenbank

--00000000000013a1430599753d58-- From MAILER-DAEMON Wed Dec 11 19:31:48 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1ifCOS-000312-1c for mharc-qemu-arm@gnu.org; Wed, 11 Dec 2019 19:31:48 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:33663) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ifCOJ-0002uk-CX for qemu-arm@nongnu.org; Wed, 11 Dec 2019 19:31:40 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ifCOI-0008Kf-5S for qemu-arm@nongnu.org; Wed, 11 Dec 2019 19:31:39 -0500 Received: from mail-pl1-x643.google.com ([2607:f8b0:4864:20::643]:45267) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ifCOH-0008Is-VI for qemu-arm@nongnu.org; Wed, 11 Dec 2019 19:31:38 -0500 Received: by mail-pl1-x643.google.com with SMTP id w7so245887plz.12 for ; Wed, 11 Dec 2019 16:31:37 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=subject:to:cc:references:from:message-id:date:user-agent :mime-version:in-reply-to:content-language:content-transfer-encoding; bh=7ahxi1d2bbzjUWQmcsGmCMgx9eDpy5No8A6ZKNnwCcs=; b=Gdyt88Z/Mcr4CQV9POK32maEJHE8LiMsUBTO0adeApEgFJsLWCioRG41OT4Po0ABqQ d1NdjQ8j1wfYVW7tAJH1EY/5iGZrUeSyrw0NYOsMgcRXUZ0ne/mc55QudU1vtvWnQREU 9iXbpdQHPhJJnDMJ4+ZWSUYdGLog8Uys8bWjtW74WM1XBuEfRDmVmFjbVP9udnaD7D+X eontXFbljWwUeVmZKbTUlZQJWkumkl0sI6281zOk22fJMFlAlg7SKK1YUb7cz7CzCgpw kx3nn62bwkSX/n9pV2ZkCgCybhEz0o4Vi/7xoTWJNSvcbgs35OrZtOtexXVdRI8lVNfL Ztfg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:subject:to:cc:references:from:message-id:date :user-agent:mime-version:in-reply-to:content-language :content-transfer-encoding; bh=7ahxi1d2bbzjUWQmcsGmCMgx9eDpy5No8A6ZKNnwCcs=; b=Lfa1N2eIyeiRsEilfp4zu39BDPPh1JD5Cl5sUVV61fq8Iw/oxlCdrY8MFEFi0CeGf4 1YAemaknIfNn0MmyQXx+EkC1zyQ+T6GVi2o+4d9y+iySSocwi/0ltMSuNlMOFutQnt/I R6Xl4Fef6EIho13+71DcAZdJaHUVSQZaC2r/hsbbEPr3AYja35bsZQEIHAn39QhOgcTG G8qQDyt7+YsRriNu67+j3gPFYJsCzJIKX25+JflCdj5DDgH4myhV7UsVqqLrUQpLKK0+ rOfsW2xy8bguBKdja3rJNUbVdQbT5eGmyW54omow42sROjqYBzBzp1W50PGl/pfCk9v7 eIYg== X-Gm-Message-State: APjAAAVjOjTgiqyhnjLESmgFtuB1COBhFiUfaeyfY3rtAIyRaLZOHpo7 onpaIDAXWLXNvIdPvABWEIzoEg== X-Google-Smtp-Source: APXvYqyy6xGMmLJlnhIAxl5T79tL8JwPW3uYtM1zUhYaP9EZFnnJ8zJ9Di2L8uuVAbcHXFjNUHw1fQ== X-Received: by 2002:a17:902:7c0c:: with SMTP id x12mr6449973pll.239.1576110696628; Wed, 11 Dec 2019 16:31:36 -0800 (PST) Received: from [192.168.1.11] (97-113-7-119.tukw.qwest.net. [97.113.7.119]) by smtp.gmail.com with ESMTPSA id h7sm4749443pfq.36.2019.12.11.16.31.35 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 11 Dec 2019 16:31:35 -0800 (PST) Subject: Re: [PATCH] target/arm: ensure we use current exception state after SCR update To: =?UTF-8?Q?Alex_Benn=c3=a9e?= , qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= , Peter Maydell References: <20191209143723.6368-1-alex.bennee@linaro.org> From: Richard Henderson Message-ID: Date: Wed, 11 Dec 2019 16:31:33 -0800 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.2.1 MIME-Version: 1.0 In-Reply-To: <20191209143723.6368-1-alex.bennee@linaro.org> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 8bit X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::643 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 12 Dec 2019 00:31:42 -0000 On 12/9/19 6:37 AM, Alex Bennée wrote: > +/* Re-read the current EL, don't use cached values */ > #define ARM_CP_CURRENTEL (ARM_CP_SPECIAL | 0x0400) > #define ARM_CP_DC_ZVA (ARM_CP_SPECIAL | 0x0500) > #define ARM_LAST_SPECIAL ARM_CP_DC_ZVA ... > @@ -5179,7 +5179,7 @@ static const ARMCPRegInfo el3_cp_reginfo[] = { > .opc0 = 3, .opc1 = 6, .crn = 1, .crm = 1, .opc2 = 0, > .access = PL3_RW, .fieldoffset = offsetof(CPUARMState, cp15.scr_el3), > .resetvalue = 0, .writefn = scr_write }, > - { .name = "SCR", .type = ARM_CP_ALIAS, > + { .name = "SCR", .type = ARM_CP_ALIAS | ARM_CP_CURRENTEL, I don't think you should reuse this value. It is not a simple bit. While ARM_CP_* all appear to implement a 16-bit quantity, the type field is already an int, and so can easily hold more. I think you should use a new bit for this. r~ From MAILER-DAEMON Wed Dec 11 19:36:31 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1ifCT1-000657-OY for mharc-qemu-arm@gnu.org; Wed, 11 Dec 2019 19:36:31 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:52045) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ifCSz-00062J-Fh for qemu-arm@nongnu.org; Wed, 11 Dec 2019 19:36:30 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ifCSy-0008Bs-Ht for qemu-arm@nongnu.org; Wed, 11 Dec 2019 19:36:29 -0500 Received: from mail-pf1-x443.google.com ([2607:f8b0:4864:20::443]:34713) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ifCSy-0008AR-CZ for qemu-arm@nongnu.org; Wed, 11 Dec 2019 19:36:28 -0500 Received: by mail-pf1-x443.google.com with SMTP id l127so171884pfl.1 for ; Wed, 11 Dec 2019 16:36:28 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=subject:to:cc:references:from:message-id:date:user-agent :mime-version:in-reply-to:content-language:content-transfer-encoding; bh=EBXWGM+EyE3h+YSrNPASzXIjTgAbTF+CJziNTgPQOdo=; b=Rom8Njnibqlg71eElLdJ/4Tum17IzXEg9p0+k72itPKxD9n3qpUiPVNbHgdrwfG4kv 9jBr/dEJ9ayyrpTaeTO0YqF3ZX8sC/9Q2jjy3onxueYM5j23eTCOjfT5gKDoMzVPeUU6 xInVMsynMypPVSEYqZmS8J5vzHExhBnTScCnoWxE2h6Z9S5AEOAlfBzgh+YUOprfk9DY W3+cR6PVQNJTSPYL+MfOczw4YxWquCHxIMDXyRVQ/NekD/Jq+cM3mhGnm6UGDkJMnvmc VPP9X/j2IZlWiaGMAxYgfJFZ5frXTnDdqqS/HICUmNUBD4f2RUyNJy93HLnP6przGlLR Jtlg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:subject:to:cc:references:from:message-id:date :user-agent:mime-version:in-reply-to:content-language :content-transfer-encoding; bh=EBXWGM+EyE3h+YSrNPASzXIjTgAbTF+CJziNTgPQOdo=; b=SHE4lXWnNZMuRvkF5tXzUlxqx8Ig2dkJjwdJm4+q4rBNDI2auCeJ3oZKMoOe5gbx+n C+egcuTelXuKWmr8NBG4ESqu3DA2gmQwvod+7wvWPi0yzyaIG2cLzHx0TSib4599l86I Vbbr6gSJRUkNHPXkjwBor50lW7C+gNVLWLNpsEGims5r74bhvc3pFOrJlf0knfzPFzAI JchWX85j79Ed9usQVK7fAlOP35/m+WhFwrdTnaKQadJKA4QX1r7BYBWSAuKCL87OvOeT V1pNwfC1Bj0Lb31+YUpBQBe2fu0FdqAFzHq8uBKJIBonSxnYwVsprFow+jPIE2rfYHYE rvPw== X-Gm-Message-State: APjAAAXu3i5QLde8SuTZQEqsmh6OMrtn2Y1KDb4mXRNm0ZR2NTkxvT4S SyPGIh10JHHjRIl/vBH4K4RNM1er3xo= X-Google-Smtp-Source: APXvYqwPrYv5D14beVLe9QF1KTYggoi6brCUqnoLQX7mZLrMqhFCB1W9EUwdv4iCCoHOj5Zi6fRsiA== X-Received: by 2002:a62:aa13:: with SMTP id e19mr6853409pff.36.1576110986855; Wed, 11 Dec 2019 16:36:26 -0800 (PST) Received: from [192.168.1.11] (97-113-7-119.tukw.qwest.net. [97.113.7.119]) by smtp.gmail.com with ESMTPSA id q6sm4683307pfq.27.2019.12.11.16.36.25 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 11 Dec 2019 16:36:26 -0800 (PST) Subject: Re: [PATCH] target/arm: Display helpful message when hflags mismatch To: =?UTF-8?Q?Alex_Benn=c3=a9e?= , =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= Cc: qemu-devel@nongnu.org, Peter Maydell , qemu-arm@nongnu.org References: <20191209134552.27733-1-philmd@redhat.com> <87d0cx32vv.fsf@linaro.org> From: Richard Henderson Message-ID: <1d51109a-ae9f-7bfe-66d4-0e1e1266df64@linaro.org> Date: Wed, 11 Dec 2019 16:36:24 -0800 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.2.1 MIME-Version: 1.0 In-Reply-To: <87d0cx32vv.fsf@linaro.org> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 8bit X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::443 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 12 Dec 2019 00:36:30 -0000 On 12/9/19 8:00 AM, Alex Bennée wrote: >> -#ifdef CONFIG_DEBUG_TCG >> - assert(flags == rebuild_hflags_internal(env)); >> -#endif >> + assert_hflags_rebuild_correctly(env); > > I'm trying to recall why we don't just use: > > g_assert_cmphex(flags, =, rebuild_hflags_internal(env)) > > I think it came up in one of the reviews. checkpatch.pl. Because, I believe, there is an environment variable that causes this to *not* abort on mismatch. r~ From MAILER-DAEMON Wed Dec 11 20:44:59 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1ifDXH-0001nG-6h for mharc-qemu-arm@gnu.org; Wed, 11 Dec 2019 20:44:59 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:48050) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ifDXF-0001mf-1b for qemu-arm@nongnu.org; Wed, 11 Dec 2019 20:44:57 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ifDXD-0000qo-Rs for qemu-arm@nongnu.org; Wed, 11 Dec 2019 20:44:56 -0500 Received: from mail-pf1-x444.google.com ([2607:f8b0:4864:20::444]:44904) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ifDXD-0000pg-NB for qemu-arm@nongnu.org; Wed, 11 Dec 2019 20:44:55 -0500 Received: by mail-pf1-x444.google.com with SMTP id d199so222713pfd.11 for ; Wed, 11 Dec 2019 17:44:55 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=subject:to:cc:references:from:message-id:date:user-agent :mime-version:in-reply-to:content-language:content-transfer-encoding; bh=TCHmnrkRlOqZCr2wFwT0K+hY8xftWllzo35pAoSr184=; b=Xcbnq6dWxVNKQ9PHm+s6raRNrO1JBPbKqqRx4WGaITmPvYb+AxldCCl9Yuj0dHo2Ik CzTo0qy0OkDf2H6GyMMp1l8UQ7Gu/MHR1K7RpeOthBjOj/ylMDLY/gaipWpVXcU4oSAT Nz5f775eP52sw//qPqipDo2OYR5w8wvKHKiUuHd1ARudTR+3M5VuKEe2jr+hxOSoyrqO TdNv2NF2t6rcQmn2kLI5qVqGvqV/4oU3skOj0wN+FEAdxDLw8YkOhmUOnO92vZMBoNAZ +1fBbs1zrXDXTG/3pda+qqnySVAg7WaD0bZbdSNVtRsD/UKWbWTkUe0NJMsjadrEcWDe Xssg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:subject:to:cc:references:from:message-id:date :user-agent:mime-version:in-reply-to:content-language :content-transfer-encoding; bh=TCHmnrkRlOqZCr2wFwT0K+hY8xftWllzo35pAoSr184=; b=Wh1fZ+78fPwTDQ1+qlypzLSnG104xIogDexhhFZdeqM4uHmJq1IMBmVICyXnKBwE8P 9SSb0g7b7+vJ7OcVFDrJu24f7DEvbuxqCUQ9F9tt5sckN+w+sr1WKMajKr3Me3FsORL7 rIKCEiPYIY910cEWY88+VoXwTKFeKAS81RE6mxPrNu+Gtm2aB17plZruvz6HRrsMJu/y Xncg99yZ/TXJIojNWPwBOaXETC8iowNlS8f5lqL2BKJjXpeDXn74wBDtB1iFZAveSEi8 L4qHG4SB4ZrKdid6Y7SVHDtHAbkBTam46cg2r3RSP3vPgnTFR5IvurMcnnyH0o1HA1py EngQ== X-Gm-Message-State: APjAAAXlNSHY8tLyBwj9fFmPQR6v0I83BbfapIbDntnkYf+2UTzYMle4 hxXBiUiQYzklb1xOvspZTstCt+dBE44= X-Google-Smtp-Source: APXvYqzzDU4q6Fi1ak3VWWokenhkt0/WbG/wlVPpo/4QyoriQTx6IHM/BgiB+WNzauHF0HJi7MMbVg== X-Received: by 2002:aa7:9ab6:: with SMTP id x22mr7030799pfi.260.1576115094279; Wed, 11 Dec 2019 17:44:54 -0800 (PST) Received: from [192.168.1.11] (97-113-7-119.tukw.qwest.net. [97.113.7.119]) by smtp.gmail.com with ESMTPSA id w200sm4451871pfc.93.2019.12.11.17.44.53 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 11 Dec 2019 17:44:53 -0800 (PST) Subject: Re: [PATCH v3 06/20] target/arm: use gdb_get_reg helpers To: =?UTF-8?Q?Alex_Benn=c3=a9e?= , qemu-devel@nongnu.org Cc: alan.hayward@arm.com, luis.machado@linaro.org, damien.hedde@greensocs.com, =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= , Peter Maydell , "open list:ARM TCG CPUs" References: <20191211170520.7747-1-alex.bennee@linaro.org> <20191211170520.7747-7-alex.bennee@linaro.org> From: Richard Henderson Message-ID: <63022f19-cc59-0b08-c3d8-3a002381789d@linaro.org> Date: Wed, 11 Dec 2019 17:44:51 -0800 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.2.1 MIME-Version: 1.0 In-Reply-To: <20191211170520.7747-7-alex.bennee@linaro.org> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 8bit X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::444 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 12 Dec 2019 01:44:58 -0000 On 12/11/19 9:05 AM, Alex Bennée wrote: > This is cleaner than poking memory directly and will make later > clean-ups easier. > > Signed-off-by: Alex Bennée > Reviewed-by: Philippe Mathieu-Daudé > > --- > v2 > - make sure we pass hi/lo correctly as quads are stored in LE order > --- > target/arm/helper.c | 18 +++++++----------- > 1 file changed, 7 insertions(+), 11 deletions(-) Reviewed-by: Richard Henderson r~ From MAILER-DAEMON Wed Dec 11 20:56:05 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1ifDi1-0006Rv-2T for mharc-qemu-arm@gnu.org; Wed, 11 Dec 2019 20:56:05 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:45179) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ifDhy-0006RQ-Uv for qemu-arm@nongnu.org; Wed, 11 Dec 2019 20:56:03 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ifDhx-0001Oh-Pm for qemu-arm@nongnu.org; Wed, 11 Dec 2019 20:56:02 -0500 Received: from mail-pf1-x442.google.com ([2607:f8b0:4864:20::442]:39060) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ifDhx-0001MG-HA for qemu-arm@nongnu.org; Wed, 11 Dec 2019 20:56:01 -0500 Received: by mail-pf1-x442.google.com with SMTP id 2so248728pfx.6 for ; Wed, 11 Dec 2019 17:56:01 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=subject:to:cc:references:from:message-id:date:user-agent :mime-version:in-reply-to:content-language:content-transfer-encoding; bh=ZcpmQQfWOxKGqTFSxMEKdaMLE/l4mvb0EyNfdGxA7g0=; b=WsVL++IzOAmRyHiVEHDRVSBjhsDi/SnZivmlTsKiEChne+P8jVI3yM2Li21eHRcc4c Ev4R+uxUidf08FOChuAKAADyZBsjsfesfaMFolhkQrVDK/LG1K4HWEsW80LnYJbRee2C hmw0A4sKd6PCiSvUnsz0TIWXDYlE7A+5YUSwoVaHfA7vq4Tcqie/A0o1xF57q8R0hW0e V6cgz5z9jGNC93Z00YiTAx4ub9IeqBV9/QWh8+AoIyGAIs9uSt41brEm6cXs05/xad3z hBun3TftB/2OSddVF1XGB4DE0BZcwaNLlIeY6PApnAuU3BN0sul79xBevbwsFPk7oeyI YZ8A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:subject:to:cc:references:from:message-id:date :user-agent:mime-version:in-reply-to:content-language :content-transfer-encoding; bh=ZcpmQQfWOxKGqTFSxMEKdaMLE/l4mvb0EyNfdGxA7g0=; b=dXSwMFDOERSUhKo9KiX/xkEtYjjxvu2okBiUycq0x2oMHbMLGA2+sH8lLPvxS29Ouc pc8G6kQ4JVvSSMwdTsA21l724f0tYNWn2HDwf6bPbNKocINirQJMoBKKLvfqEsPOOn2T 44n3Ek2dLis98hr7nuZ/Tf+ndXBwAEMWHqG9bWE/r3eju5qQWU0Qga4k1IIt2Hej8HGZ ruRhrf53Q7eeXge9sz9+pS2Zx1OC+2HxRxIqdsHJdRTFGZtmP6NoxlW0j3ICBrxUQXZz yN5V+zRwq3/gOAB0Z2CvrKoGIIzq/YnazyHd+qQK31qHmCGdZzhHUF61SiarSNy0mC81 44/w== X-Gm-Message-State: APjAAAUyfVRac1N5hF69FTpWTsdaDhcK3J3DUagc+5/4givp+vYERes3 r6RcY3YXqut6gc3w3XXQAOWncQ== X-Google-Smtp-Source: APXvYqyhITzwXVS5e7icg7DK8QtXs5njvApH9ofZ43U7RW9EK0jR2qhd6W2itNOLUREGZTE7XU+kuA== X-Received: by 2002:a63:4702:: with SMTP id u2mr7765676pga.125.1576115760284; Wed, 11 Dec 2019 17:56:00 -0800 (PST) Received: from [192.168.1.11] (97-113-7-119.tukw.qwest.net. [97.113.7.119]) by smtp.gmail.com with ESMTPSA id u190sm4459483pfb.60.2019.12.11.17.55.58 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 11 Dec 2019 17:55:59 -0800 (PST) Subject: Re: [PATCH v3 08/20] gdbstub: extend GByteArray to read register helpers To: =?UTF-8?Q?Alex_Benn=c3=a9e?= , qemu-devel@nongnu.org Cc: alan.hayward@arm.com, luis.machado@linaro.org, damien.hedde@greensocs.com, =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= , Eduardo Habkost , Marcel Apfelbaum , Richard Henderson , Peter Maydell , "Edgar E. Iglesias" , Paolo Bonzini , Michael Walle , Laurent Vivier , Aurelien Jarno , Aleksandar Markovic , Aleksandar Rikalo , Chris Wulff , Marek Vasut , Stafford Horne , David Gibson , Palmer Dabbelt , Alistair Francis , Sagar Karandikar , Bastian Koppelmann , David Hildenbrand , Cornelia Huck , Mark Cave-Ayland , Artyom Tarasenko , Max Filippov , "open list:ARM TCG CPUs" , "open list:PowerPC TCG CPUs" , "open list:RISC-V TCG CPUs" , "open list:S390 TCG CPUs" References: <20191211170520.7747-1-alex.bennee@linaro.org> <20191211170520.7747-9-alex.bennee@linaro.org> From: Richard Henderson Message-ID: <134bfe14-23c3-4301-bb45-80024f9eb4fb@linaro.org> Date: Wed, 11 Dec 2019 17:55:56 -0800 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.2.1 MIME-Version: 1.0 In-Reply-To: <20191211170520.7747-9-alex.bennee@linaro.org> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 8bit X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::442 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 12 Dec 2019 01:56:04 -0000 On 12/11/19 9:05 AM, Alex Bennée wrote: > Instead of passing a pointer to memory now just extend the GByteArray > to all the read register helpers. They can then safely append their > data through the normal way. We don't bother with this abstraction for > write registers as we have already ensured the buffer being copied > from is the correct size. > > Signed-off-by: Alex Bennée > --- Reviewed-by: Richard Henderson r~ From MAILER-DAEMON Wed Dec 11 21:09:22 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1ifDus-0001cB-2U for mharc-qemu-arm@gnu.org; Wed, 11 Dec 2019 21:09:22 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:46559) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ifDuo-0001YZ-Lv for qemu-arm@nongnu.org; Wed, 11 Dec 2019 21:09:19 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ifDun-00056g-CR for qemu-arm@nongnu.org; Wed, 11 Dec 2019 21:09:18 -0500 Received: from mail-pf1-x444.google.com ([2607:f8b0:4864:20::444]:44040) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ifDun-00054y-5A for qemu-arm@nongnu.org; Wed, 11 Dec 2019 21:09:17 -0500 Received: by mail-pf1-x444.google.com with SMTP id d199so250303pfd.11 for ; Wed, 11 Dec 2019 18:09:17 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=subject:to:cc:references:from:message-id:date:user-agent :mime-version:in-reply-to:content-language:content-transfer-encoding; bh=vyX7QreLgESGZBkcNOCy4sl/B66hsQvvZY/2+o5GCOI=; b=gZScW/0Yfu+Fl9zkya/fv/1Lxf0899+RDyoqhPM5HRs5PjHVaYY4Z4BjFw40brIdPQ rM1MvfuBJEuHawPAQ/NrMubFrvS/tVZxk5mV1+bMcbvYTUtBcluO0EIjquQ7yabWTEfw YqyKY02/y5lmlAq8SVfr0heEvtanZKcfEVQEA6SzJd+cBmlzaXKwMhnK6s/OX1cQYh2l xlSWN5ZP4so/raL8NiDezH3sbQmrlu2xJ6S1iGjYJZqosrjELnhfzps52IbZy+br/aaC 8eG2px1mXoBfaI/MwY9aKVFv4/09Rsie7/1IjaeBQHshhynrc6FowrVOQiMlvTCoQHlN 8SWw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:subject:to:cc:references:from:message-id:date :user-agent:mime-version:in-reply-to:content-language :content-transfer-encoding; bh=vyX7QreLgESGZBkcNOCy4sl/B66hsQvvZY/2+o5GCOI=; b=ZRvSPkbtp3NEbMsNkf5LvZFRcwafUSXWIVBJNUx+ZYGt19+e/EXCY7J34aFJNeC6nY /OxT6nQziQqhaCBtKOiZFo2JY3BT/ZUzI3VOtfTtyTdLdC+jsnTMz8VomzvMVW9MzpjX DRSbodPuXEOJYFCzjVwh/AWP9TMSwcBY2FyMRWU+2zCOXlVrdVX9wv+DA//3egipAsVL 5DG9w+qwA4UqL2qm9d6eYe8FABsTTiDQ40eBpARw7O4JOJ+lAeLBNqhZXJqDXpIRrlss kaT2JF4ZEu/5g2YO+UHRl+HIJcU9GhJfBCDuTEQYNV0Yu4joKUmtlKGdKlCsHQ1Rzhk1 sp+w== X-Gm-Message-State: APjAAAWWwUrth1Yfyfsgq2UtAYzOF3Vwmks/YyJe5XH3R+2wrnfgMCe3 OxRewoPgk2iBN1YPTDc3Lj7O9fyNios= X-Google-Smtp-Source: APXvYqzt4r+JYIP3LxkcoEM74229wKgfDcGlQJIX2BV09qVmfK4Kj+FNn1ehdPwApYD0K0uYiQiwBw== X-Received: by 2002:a62:4ec7:: with SMTP id c190mr6968035pfb.68.1576116555710; Wed, 11 Dec 2019 18:09:15 -0800 (PST) Received: from [192.168.1.11] (97-113-7-119.tukw.qwest.net. [97.113.7.119]) by smtp.gmail.com with ESMTPSA id s130sm4368967pgc.82.2019.12.11.18.09.14 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 11 Dec 2019 18:09:15 -0800 (PST) Subject: Re: [PATCH v3 11/20] target/arm: default SVE length to 64 bytes for linux-user To: =?UTF-8?Q?Alex_Benn=c3=a9e?= , qemu-devel@nongnu.org Cc: alan.hayward@arm.com, luis.machado@linaro.org, damien.hedde@greensocs.com, Peter Maydell , "open list:ARM TCG CPUs" References: <20191211170520.7747-1-alex.bennee@linaro.org> <20191211170520.7747-12-alex.bennee@linaro.org> From: Richard Henderson Message-ID: Date: Wed, 11 Dec 2019 18:09:13 -0800 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.2.1 MIME-Version: 1.0 In-Reply-To: <20191211170520.7747-12-alex.bennee@linaro.org> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 8bit X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::444 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 12 Dec 2019 02:09:19 -0000 On 12/11/19 9:05 AM, Alex Bennée wrote: > The Linux kernel chooses the default of 64 bytes for SVE registers on > the basis that it is the largest size on known hardware that won't > grow the signal frame. We still honour the sve-max-vq property and > userspace can expand the number of lanes by calling PR_SVE_SET_VL. > > This should not make any difference to SVE enabled software as the SVE > is of course vector length agnostic. > > Signed-off-by: Alex Bennée > > --- > v2 > - tweak zcr_el[1] instead > --- > target/arm/cpu.c | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git a/target/arm/cpu.c b/target/arm/cpu.c > index 7a4ac9339bf..d42b88c9b73 100644 > --- a/target/arm/cpu.c > +++ b/target/arm/cpu.c > @@ -199,9 +199,9 @@ static void arm_cpu_reset(CPUState *s) > /* and to the SVE instructions */ > env->cp15.cpacr_el1 = deposit64(env->cp15.cpacr_el1, 16, 2, 3); > env->cp15.cptr_el[3] |= CPTR_EZ; > - /* with maximum vector length */ > + /* with reasonable vector length */ I think this comment should mention the kernel as well. Otherwise, Reviewed-by: Richard Henderson r~ From MAILER-DAEMON Wed Dec 11 21:26:32 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1ifEBU-0005OV-5Y for mharc-qemu-arm@gnu.org; Wed, 11 Dec 2019 21:26:32 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:54023) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ifEBR-0005Ln-RP for qemu-arm@nongnu.org; Wed, 11 Dec 2019 21:26:30 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ifEBQ-0004zC-RN for qemu-arm@nongnu.org; Wed, 11 Dec 2019 21:26:29 -0500 Received: from mail-pf1-x442.google.com ([2607:f8b0:4864:20::442]:39252) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ifEBQ-0004ys-K4 for qemu-arm@nongnu.org; Wed, 11 Dec 2019 21:26:28 -0500 Received: by mail-pf1-x442.google.com with SMTP id 2so284755pfx.6 for ; Wed, 11 Dec 2019 18:26:28 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=subject:to:cc:references:from:message-id:date:user-agent :mime-version:in-reply-to:content-language:content-transfer-encoding; bh=l01TCjoxhhiRwrhGymsnwdBCUwsXAo0f17ZzMIBSSa4=; b=QhXX1opqNF7tkFLSur9SQgoXLDrEYTI/iPypsUYk0zPBfEzb7vaslnO3pTSZ21ynoA uc6HzlaS7j3tQfJX8QR2epgH0wodu6t6VRVqEBGWTaFZOrL5Fn5ySKgpt2Z75jgPov1d aKX8ouffQFQqp3JKqLFTqTjZTGyU2UB3lGzzSNbxbvDg1kXMyarpqJ9r8UV1w/bWJRH7 KDMIZ4fEOMHCweVf9chJRrw60j/6bDzBrMLQ7eG3OOYbFeU/AbDXMAvhxajbtVqt9KOg zaYGGZGUN0R+MpSYkb/GSUIhi6gRno8pD6U/yAwajnSo+fVfAZU4vA9uTK0R2bWJowoo MUow== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:subject:to:cc:references:from:message-id:date :user-agent:mime-version:in-reply-to:content-language :content-transfer-encoding; bh=l01TCjoxhhiRwrhGymsnwdBCUwsXAo0f17ZzMIBSSa4=; b=qlwGdsCr2Ha0D6Yzy7lBMd/it8D4YCH1voqP8dgR6Ph2/lc5d3PcyKNZTdFeJfoFNg h7RyWmeifv/oAloOgtBE8l6YeO+NEq2FHVVaDtFZ93/Aq0rLgomBUG5i2dHalXlyU524 lDwICXerUrAuZaWg2wdIFlhwkiKvzZt39QrZ2/+1PL/5zZajyftfbAhs6j5KNEAJlA1+ rNrCj499jLJnGwatbkwa0aHlkDk1zO+YyQyzaFKWs6sM7a7bwo0eiyNPpzW7maMpIQ6x ZCxVWs8OTqfL8TvQ2JOGuiMMCOBUtj3KA9kXPpDwapA8PNJI1EJ5hXDD+HEcXTRpVacC XVpQ== X-Gm-Message-State: APjAAAV/jL6HxsEMj0gn1xzk7F8T6VHzr/3L518mIhS606abBXD4sgaa GYJ4XXRX3ipCmmTIDrBCg2bVKlMVXVA= X-Google-Smtp-Source: APXvYqzOf8mu/kWOthQCugcummgnnhrMmMXn2oRAw4uQ6g3eTLFPs+ZT6dz+LmcGdTsqK8erHl3iKg== X-Received: by 2002:a62:7b46:: with SMTP id w67mr7325952pfc.113.1576117587348; Wed, 11 Dec 2019 18:26:27 -0800 (PST) Received: from [192.168.1.11] (97-113-7-119.tukw.qwest.net. [97.113.7.119]) by smtp.gmail.com with ESMTPSA id u123sm4586602pfb.109.2019.12.11.18.26.26 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 11 Dec 2019 18:26:26 -0800 (PST) Subject: Re: [PATCH v3 12/20] target/arm: generate xml description of our SVE registers To: =?UTF-8?Q?Alex_Benn=c3=a9e?= , qemu-devel@nongnu.org Cc: alan.hayward@arm.com, luis.machado@linaro.org, damien.hedde@greensocs.com, Peter Maydell , "open list:ARM TCG CPUs" References: <20191211170520.7747-1-alex.bennee@linaro.org> <20191211170520.7747-13-alex.bennee@linaro.org> From: Richard Henderson Message-ID: <69e10c48-8bdf-cbe0-3372-815b647f8312@linaro.org> Date: Wed, 11 Dec 2019 18:26:24 -0800 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.2.1 MIME-Version: 1.0 In-Reply-To: <20191211170520.7747-13-alex.bennee@linaro.org> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 8bit X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::442 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 12 Dec 2019 02:26:30 -0000 On 12/11/19 9:05 AM, Alex Bennée wrote: > +static struct TypeSize vec_lanes[] = { const. > + case 51: > + return gdb_get_reg64(buf, (cpu->env.vfp.zcr_el[1] & 0xf) + 1); You need to use sve_zcr_len_for_el to get the effective vq. Also, I thought vg == 2 * vq. > + case 51: > + { > + uint64_t val = *(uint64_t *) buf; > + cpu->env.vfp.zcr_el[1] = (val - 1) & 0xf; You cannot hard-code EL1 without ifdef CONFIG_USER_ONLY. If the effective vq decreases, you must call aarch64_sve_narrow_vq. You must call arm_rebuild_hflags. r~ From MAILER-DAEMON Wed Dec 11 21:29:25 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1ifEEH-0006Wl-8R for mharc-qemu-arm@gnu.org; Wed, 11 Dec 2019 21:29:25 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:46538) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ifEEE-0006Vs-Cz for qemu-arm@nongnu.org; Wed, 11 Dec 2019 21:29:23 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ifEEC-0000eO-AG for qemu-arm@nongnu.org; Wed, 11 Dec 2019 21:29:21 -0500 Received: from mail-pl1-x642.google.com ([2607:f8b0:4864:20::642]:34417) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ifEEB-0000Yu-8d for qemu-arm@nongnu.org; Wed, 11 Dec 2019 21:29:19 -0500 Received: by mail-pl1-x642.google.com with SMTP id x17so376525pln.1 for ; Wed, 11 Dec 2019 18:29:16 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=subject:to:cc:references:from:message-id:date:user-agent :mime-version:in-reply-to:content-language:content-transfer-encoding; bh=dnSs02hUKWgYOXF+wicFs/wEm5XHaRR03CSW1fVdNiY=; b=LuxnKsYV2P5jw3pWhC4NqH4SbsEWMDd423hp+nxFYkWo4Nej8Twbhm5a8L3IU+Y/ux 0dZCuIl7GmeLYBWt/NHe8hjC2YYt/ibogZfwz8+QSxVSuTj92NAfX62Et4lHAax/v1oN wrWO72GBJmzc1ZuQ/iT67LVSCE8gY82aDeqG9/UH0J3sdwjYusRmt8fZ1C6AqVeklo3c obxAx7E/vwtsmizQc7PitJDbDkJgjpQ6UDhUvC+z+eFSQ9NJPzE/GPVfJ3XjxlLuJMKR Tzdw7EO8DVtVCMp6pwkhI7qMDypNEZnqPCCt/0x+IJIO2szSvqQE8XtjlSZy1ZxxCJk1 zddg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:subject:to:cc:references:from:message-id:date :user-agent:mime-version:in-reply-to:content-language :content-transfer-encoding; bh=dnSs02hUKWgYOXF+wicFs/wEm5XHaRR03CSW1fVdNiY=; b=cv4FzIzYb5zGxxruqbxOsT00jOKFTotO7dAgwJB5CQEW3cgPfP9N3Qn9StznJt/gJq XCePtIq+o8Ur0ZqZM1jYJA24a4/Fhha5oaj5dBpamANUXGIeAOj9/RMzuyhomAey0/Jk yZjCrXX0bnqr7wQdfSkOL7MatdGSrrH6nSayggMg4WvuQPQulaASrSBsuGmv3ljsv9cc Uo+7pPrjHJDehy12+MeI9FqUFmZXYLV1mUA4b3QZu1xWnKyEhTpd4I3W2RYF2jWXfiRT GX7rGnlnLfrBuBGB2AKtOInSJf9t7i1ewog76PcG9PQfRimP/sVd5Zz6K+t0Xtvpb8mx 1zdw== X-Gm-Message-State: APjAAAUoqaATFNkCQ4yczG/mz3WQPiiEuQfVwQoAbRgXWkrlyokJ1XhH 3AoBIohT8Dcfoi5ibWoGfOKncanBeeE= X-Google-Smtp-Source: APXvYqwujqZ69gHWsNo4ORP98IGcjIhEFx7KOpNlkYeIETtq2doROUzqX2vhdew6XoMaU9NXa1BjoA== X-Received: by 2002:a17:902:ac97:: with SMTP id h23mr7050556plr.237.1576117751180; Wed, 11 Dec 2019 18:29:11 -0800 (PST) Received: from [192.168.1.11] (97-113-7-119.tukw.qwest.net. [97.113.7.119]) by smtp.gmail.com with ESMTPSA id z14sm2677828pfg.57.2019.12.11.18.29.10 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 11 Dec 2019 18:29:10 -0800 (PST) Subject: Re: [PATCH v3 14/20] target/arm: don't bother with id_aa64pfr0_read for USER_ONLY To: =?UTF-8?Q?Alex_Benn=c3=a9e?= , qemu-devel@nongnu.org Cc: alan.hayward@arm.com, luis.machado@linaro.org, damien.hedde@greensocs.com, Peter Maydell , "open list:ARM TCG CPUs" References: <20191211170520.7747-1-alex.bennee@linaro.org> <20191211170520.7747-15-alex.bennee@linaro.org> From: Richard Henderson Message-ID: Date: Wed, 11 Dec 2019 18:29:08 -0800 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.2.1 MIME-Version: 1.0 In-Reply-To: <20191211170520.7747-15-alex.bennee@linaro.org> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 8bit X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Received-From: 2607:f8b0:4864:20::642 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 12 Dec 2019 02:29:23 -0000 On 12/11/19 9:05 AM, Alex Bennée wrote: > For system emulation we need to check the state of the GIC before we > report the value. However this isn't relevant to exporting of the > value to linux-user and indeed breaks the exported value as set by > modify_arm_cp_regs. > > Signed-off-by: Alex Bennée > > --- > v2 > - extend the ifdef and make type CONST with no accessfn > --- > target/arm/helper.c | 20 +++++++++++++++----- > 1 file changed, 15 insertions(+), 5 deletions(-) Reviewed-by: Richard Henderson r~ From MAILER-DAEMON Wed Dec 11 21:38:03 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1ifEMd-0000j0-8g for mharc-qemu-arm@gnu.org; Wed, 11 Dec 2019 21:38:03 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:40963) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ifEMb-0000iU-EV for qemu-arm@nongnu.org; Wed, 11 Dec 2019 21:38:02 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ifEMa-0001XF-Ff for qemu-arm@nongnu.org; Wed, 11 Dec 2019 21:38:01 -0500 Received: from mail-pg1-x52a.google.com ([2607:f8b0:4864:20::52a]:44766) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ifEMa-0001X5-AY for qemu-arm@nongnu.org; Wed, 11 Dec 2019 21:38:00 -0500 Received: by mail-pg1-x52a.google.com with SMTP id x7so326397pgl.11 for ; Wed, 11 Dec 2019 18:38:00 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=subject:to:cc:references:from:message-id:date:user-agent :mime-version:in-reply-to:content-language:content-transfer-encoding; bh=pSHE4/4kZo4fmk7WZTpI8ZXurfiJ2m59mz49KBX6aNE=; b=O5TnFHVp7jidZfGX1NaAxdPAQ8fDH2FKgEOoM6KTaCZ9CrNiVQ1FZbyiDh8X++Y9M2 BWh1HjskUxNlZn1kVAk8WRc8lMUqPXQH1wXFTQsMLyDFo58B12nGKiulFJfJtpcgxSY3 GvBzArwvPK2uuBjfuhxN6VZtAm5VpUsn/8s8occ7DYLma9zlZsB7dlX1GjyNhXJ1MM3q wcJ4jVzdieq4NcKRPQGM0JcyzemUr/InjlBtvUnD+Qjm4CwGilw5DMuytoXUWlTVf4mR N3ZBV66fAuJ1MA4I70OW6sXxgOER9WWZGtpNx4wO4vIaGb4qOw0XligjcYRUUFrCwUH9 SWhQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:subject:to:cc:references:from:message-id:date :user-agent:mime-version:in-reply-to:content-language :content-transfer-encoding; bh=pSHE4/4kZo4fmk7WZTpI8ZXurfiJ2m59mz49KBX6aNE=; b=rfLNcIrlvJGNiiGesCHG864K8mSF2i44jy/WWQH0b1n8v2Meskn+ZAsBdt4coI7erF T0Log8Ytil9BIfqFvT1GeaFYCvU6mKKM7RWed1rtgMo/ZPYqFf4sm0x2fm6FZGCP2/My Mem/xSk79TTamjY30+fLs9NQIemQxvwQuQIkSl2wdRxZvJGFuv9KTXQbRpZcBX8QZJ8C mrv5fMnpxceegFwgrRlWE9x6M2QY2GFje584SB9OZDnnE4MNcFDq7zqS1pMpJXUA3DuJ JKxLz+uKdKbJeXMQ3FHi61wttERiyKUzRMu/85viRAGvamHutrpX5Uq+Ewpj2AbpN36N /ujQ== X-Gm-Message-State: APjAAAUnkBgaSyi34Ts1eiz0CaAFg/rGC77IuHmqoY44OUK4D/zr6DWP dZdsZrmO21uvA93MSpWSnAevLOnPmjg= X-Google-Smtp-Source: APXvYqxQPTooAJBxcMUkp7dyDemkvXFk6+p0VEGbeOIoo/p9UEc19YOBL3QyQZdz4JU4X3t8MftpXg== X-Received: by 2002:a62:b509:: with SMTP id y9mr7114028pfe.12.1576118279208; Wed, 11 Dec 2019 18:37:59 -0800 (PST) Received: from [192.168.1.11] (97-113-7-119.tukw.qwest.net. [97.113.7.119]) by smtp.gmail.com with ESMTPSA id b10sm4754340pff.59.2019.12.11.18.37.58 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 11 Dec 2019 18:37:58 -0800 (PST) Subject: Re: [PATCH v3 19/20] tests/tcg/aarch64: add SVE iotcl test To: =?UTF-8?Q?Alex_Benn=c3=a9e?= , qemu-devel@nongnu.org Cc: alan.hayward@arm.com, luis.machado@linaro.org, damien.hedde@greensocs.com, Peter Maydell , "open list:ARM TCG CPUs" References: <20191211170520.7747-1-alex.bennee@linaro.org> <20191211170520.7747-20-alex.bennee@linaro.org> From: Richard Henderson Message-ID: Date: Wed, 11 Dec 2019 18:37:56 -0800 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.2.1 MIME-Version: 1.0 In-Reply-To: <20191211170520.7747-20-alex.bennee@linaro.org> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 8bit X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::52a X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 12 Dec 2019 02:38:02 -0000 On 12/11/19 9:05 AM, Alex Bennée wrote: > +int main(int argc, char **argv) > +{ > + unsigned int sve_feature = (get_cpu_reg(ID_AA64PFR0_EL1) >> 32) & 0xf; > + /* Exit early if we don't support SVE at all */ > + if (sve_feature == 0x1) { > + /* we also need to probe for the ioctl support */ > + if (getauxval(AT_HWCAP) & HWCAP_SVE) { > + return do_sve_ioctl_test(); > + } else { > + printf("SKIP: no HWCAP_SVE on this system\n"); > + return 0; > + } I don't see the point in the PFR0 test. Testing HWCAP_SVE should be sufficient. r~ From MAILER-DAEMON Thu Dec 12 02:00:02 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1ifIS9-0008DW-VQ for mharc-qemu-arm@gnu.org; Thu, 12 Dec 2019 02:00:01 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:56206) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ifIS5-00088m-Ag for qemu-arm@nongnu.org; Thu, 12 Dec 2019 01:59:59 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ifIS3-0005LL-71 for qemu-arm@nongnu.org; Thu, 12 Dec 2019 01:59:57 -0500 Received: from mail-qv1-xf44.google.com ([2607:f8b0:4864:20::f44]:37431) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ifIRy-0005Bh-NA; Thu, 12 Dec 2019 01:59:50 -0500 Received: by mail-qv1-xf44.google.com with SMTP id t7so546189qve.4; Wed, 11 Dec 2019 22:59:50 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=/vGTej3K5tmtqUYcv3LSFifKkGOFV9scq9HXRHw1agQ=; b=kSRvw2KoKQIl0pjSejjCpF0ryhTOhvtfFMsI7eTIqUJxjWR9St8A4HUgjc3lCMFxZy W6Uorx6uSzDU+JQLE+GGTfb/NhbrBftOfcv17/wvbdKopjIa9x9IVmUiHYJZXtDY/RMu fvrOBL4gyNIMfrHiawnOt7r1Usx+wsry0XaGKcJGz6KwGIDK28otWdhY2dy3ZfN4bN8X l6nqYQwE0wS8x5LiJXqbwKo2M+boQhWzU1TjjRZpEzdpwKzWhqkCkoT4ywvciVohizZX 0EAVA0fI5TWpy3wm+zliuYE10X6Sj1CJkR2SetX2p/i2eaU4T72A5T/hgT5z6kwsUXuG TmBA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=/vGTej3K5tmtqUYcv3LSFifKkGOFV9scq9HXRHw1agQ=; b=bVYVWrUyoXD6nEXosDPC5hW/BEFuO0ImcNQKgJRH/AmBlmIOBxeTfp56Zt68BBUAfj Ep8NjjelwHTvDBCtbhfPHTHw5ZulT8hnWNtrqVobcQhqbs+KdK4xpi1qEHdvcB8Uvqcb rvFxY6VNx6oeBVokMPpvhwyrVdDB0IhoGLI2XUCzzXa2B+6X9ac3Aaz6TyDiTw6Dxs4i bq3PyHlO/+iy3nFdiZJCBoH4cupt3GfjGIdTi5gzhE8d08lQN9LEMiXaEeNCZuLTY2Gx Wwp8i1oY3+IwptjUTEUWxWO9eOD92tnwsUg2SrnOtKjIGjAkLzcUXxtchGcBpzpD+DCc 9vXQ== X-Gm-Message-State: APjAAAXbl8a4UAcHOGIurZXLTurt/+7Ck0oFDDyy0ntV+PaRxwnyZP3I f2JgFsIIbFsJhm5E/RoWeC1MghS5ZfLy80tEYY+MnA== X-Google-Smtp-Source: APXvYqxZm/BOVXF9EAicY8Ps4EKfOimZEtCeHtoaHhuZhsmC5qejFZFRQUh1VGlRLzEIf1zaqjUCsmEVygwYYr6l7lI= X-Received: by 2002:a05:6214:14e5:: with SMTP id k5mr6584112qvw.192.1576133989516; Wed, 11 Dec 2019 22:59:49 -0800 (PST) MIME-Version: 1.0 References: <20191210140617.16656-1-bilalwasim676@gmail.com> In-Reply-To: <20191210140617.16656-1-bilalwasim676@gmail.com> From: Bilal Wasim Date: Thu, 12 Dec 2019 11:59:36 +0500 Message-ID: Subject: Re: [PATCH v3] net/imx_fec: Adding support for MAC filtering in the FEC IP implementation. To: qemu-devel@nongnu.org Cc: jasowang@redhat.com, qemu-arm@nongnu.org, Peter Maydell , philmd@redhat.com, mark.cave-ayland@ilande.co.uk Content-Type: multipart/alternative; boundary="000000000000904c1905997c4a91" X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::f44 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 12 Dec 2019 06:59:59 -0000 --000000000000904c1905997c4a91 Content-Type: text/plain; charset="UTF-8" Hi Jason, Mark, Can you please review this patch.. --Bilal On Tue, 10 Dec 2019, 19:06 , wrote: > From: bwasim > > This addition ensures that the IP does NOT boot up in promiscuous mode > by default, and so the software only receives the desired > packets(Unicast, Broadcast, Unicast / Multicast hashed) by default. > The software running on-top of QEMU can also modify these settings and > disable reception of broadcast frames or make the IP receive all packets > (PROM mode). > This patch greatly reduces the number of packets received by the > software running on-top of the QEMU model. Tested with the armv7-a > SABRE_LITE machine. > Testing included running a custom OS with IPv4 / IPv6 support. Hashing > and filtering of packets is tested to work well. Skeleton taken from > the CADENCE_GEM IP and hash generation algorithm from the Linux Kernel. > > Signed-off-by: Bilal Wasim > --- > hw/net/imx_fec.c | 109 ++++++++++++++++++++++++++++++++++++++- > include/hw/net/imx_fec.h | 10 ++++ > 2 files changed, 118 insertions(+), 1 deletion(-) > > diff --git a/hw/net/imx_fec.c b/hw/net/imx_fec.c > index bd99236864..d248f39fb0 100644 > --- a/hw/net/imx_fec.c > +++ b/hw/net/imx_fec.c > @@ -419,6 +419,79 @@ static void imx_enet_write_bd(IMXENETBufDesc *bd, > dma_addr_t addr) > dma_memory_write(&address_space_memory, addr, bd, sizeof(*bd)); > } > > +/* > + * Calculate a FEC MAC Address hash index > + */ > +static unsigned calc_mac_hash(const uint8_t *mac, uint8_t mac_length) > +{ > + uint32_t crc = net_crc32_le(mac, mac_length); > + > + /* > + * only upper 6 bits (FEC_HASH_BITS) are used > + * which point to specific bit in the hash registers > + */ > + return (crc >> (32 - FEC_HASH_BITS)) & 0x3f; > +} > + > +/* > + * fec_mac_address_filter: > + * Accept or reject this destination address? > + */ > +static int fec_mac_address_filter(IMXFECState *s, const uint8_t *packet) > +{ > + const uint8_t broadcast_addr[] = { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF > }; > + uint32_t addr1, addr2; > + uint8_t hash; > + > + /* Promiscuous mode? */ > + if (s->regs[ENET_RCR] & ENET_RCR_PROM) { > + /* Accept all packets in promiscuous mode (even if bc_rej is > set). */ > + return FEC_RX_PROMISCUOUS_ACCEPT; > + } > + > + /* Broadcast packet? */ > + if (!memcmp(packet, broadcast_addr, 6)) { > + /* Reject broadcast packets? */ > + if (s->regs[ENET_RCR] & ENET_RCR_BC_REJ) { > + return FEC_RX_REJECT; > + } > + /* Accept packets from broadcast address. */ > + return FEC_RX_BROADCAST_ACCEPT; > + } > + > + /* Accept packets -w- hash match? */ > + hash = calc_mac_hash(packet, 6); > + > + /* Accept packets -w- multicast hash match? */ > + if ((packet[0] & 0x01) == 0x01) { > + /* Computed hash matches GAUR / GALR register ? */ > + if (((hash < 32) && (s->regs[ENET_GALR] & (1 << hash))) > + || ((hash > 31) && (s->regs[ENET_GAUR] & (1 << (hash - > 32))))) { > + /* Accept multicast hash enabled address. */ > + return FEC_RX_MULTICAST_HASH_ACCEPT; > + } > + } else { > + /* Computed hash matches IAUR / IALR register ? */ > + if (((hash < 32) && (s->regs[ENET_IALR] & (1 << hash))) > + || ((hash > 31) && (s->regs[ENET_IAUR] & (1 << (hash - > 32))))) { > + /* Accept multicast hash enabled address. */ > + return FEC_RX_UNICAST_HASH_ACCEPT; > + } > + } > + > + /* Match Unicast address. */ > + addr1 = g_htonl(s->regs[ENET_PALR]); > + addr2 = g_htonl(s->regs[ENET_PAUR]); > + if (!(memcmp(packet, (uint8_t *) &addr1, 4) || > + memcmp(packet + 4, (uint8_t *) &addr2, 2))) { > + /* Accept packet because it matches my unicast address. */ > + return FEC_RX_UNICAST_ACCEPT; > + } > + > + /* Return -1 because we do NOT support MAC address filtering.. */ > + return FEC_RX_REJECT; > +} > + > static void imx_eth_update(IMXFECState *s) > { > /* > @@ -984,7 +1057,7 @@ static void imx_eth_write(void *opaque, hwaddr > offset, uint64_t value, > case ENET_IALR: > case ENET_GAUR: > case ENET_GALR: > - /* TODO: implement MAC hash filtering. */ > + s->regs[index] |= value; > break; > case ENET_TFWR: > if (s->is_fec) { > @@ -1066,8 +1139,15 @@ static ssize_t imx_fec_receive(NetClientState *nc, > const uint8_t *buf, > uint32_t buf_addr; > uint8_t *crc_ptr; > unsigned int buf_len; > + int maf; > size_t size = len; > > + /* Is this destination MAC address "for us" ? */ > + maf = fec_mac_address_filter(s, buf); > + if (maf == FEC_RX_REJECT) { > + return FEC_RX_REJECT; > + } > + > FEC_PRINTF("len %d\n", (int)size); > > if (!s->regs[ENET_RDAR]) { > @@ -1133,6 +1213,16 @@ static ssize_t imx_fec_receive(NetClientState *nc, > const uint8_t *buf, > } else { > s->regs[ENET_EIR] |= ENET_INT_RXB; > } > + > + /* Update descriptor based on the "maf" flag. */ > + if (maf == FEC_RX_BROADCAST_ACCEPT) { > + /* The packet is destined for the "broadcast" address. */ > + bd.flags |= ENET_BD_BC; > + } else if (maf == FEC_RX_MULTICAST_HASH_ACCEPT) { > + /* The packet is destined for a "multicast" address. */ > + bd.flags |= ENET_BD_MC; > + } > + > imx_fec_write_bd(&bd, addr); > /* Advance to the next descriptor. */ > if ((bd.flags & ENET_BD_W) != 0) { > @@ -1159,8 +1249,15 @@ static ssize_t imx_enet_receive(NetClientState *nc, > const uint8_t *buf, > uint8_t *crc_ptr; > unsigned int buf_len; > size_t size = len; > + int maf; > bool shift16 = s->regs[ENET_RACC] & ENET_RACC_SHIFT16; > > + /* Is this destination MAC address "for us" ? */ > + maf = fec_mac_address_filter(s, buf); > + if (maf == FEC_RX_REJECT) { > + return FEC_RX_REJECT; > + } > + > FEC_PRINTF("len %d\n", (int)size); > > if (!s->regs[ENET_RDAR]) { > @@ -1254,6 +1351,16 @@ static ssize_t imx_enet_receive(NetClientState *nc, > const uint8_t *buf, > s->regs[ENET_EIR] |= ENET_INT_RXB; > } > } > + > + /* Update descriptor based on the "maf" flag. */ > + if (maf == FEC_RX_BROADCAST_ACCEPT) { > + /* The packet is destined for the "broadcast" address. */ > + bd.flags |= ENET_BD_BC; > + } else if (maf == FEC_RX_MULTICAST_HASH_ACCEPT) { > + /* The packet is destined for a "multicast" address. */ > + bd.flags |= ENET_BD_MC; > + } > + > imx_enet_write_bd(&bd, addr); > /* Advance to the next descriptor. */ > if ((bd.flags & ENET_BD_W) != 0) { > diff --git a/include/hw/net/imx_fec.h b/include/hw/net/imx_fec.h > index 7b3faa4019..f9cfcf6af5 100644 > --- a/include/hw/net/imx_fec.h > +++ b/include/hw/net/imx_fec.h > @@ -275,4 +275,14 @@ typedef struct IMXFECState { > uint8_t frame[ENET_MAX_FRAME_SIZE]; > } IMXFECState; > > +/* FEC address filtering defines. */ > +#define FEC_RX_REJECT (-1) > +#define FEC_RX_PROMISCUOUS_ACCEPT (-2) > +#define FEC_RX_BROADCAST_ACCEPT (-3) > +#define FEC_RX_MULTICAST_HASH_ACCEPT (-4) > +#define FEC_RX_UNICAST_HASH_ACCEPT (-5) > +#define FEC_RX_UNICAST_ACCEPT (-6) > + > +#define FEC_HASH_BITS 6 /* #bits in hash */ > + > #endif > -- > 2.19.1.windows.1 > > --000000000000904c1905997c4a91 Content-Type: text/html; charset="UTF-8" Content-Transfer-Encoding: quoted-printable
Hi Jason, Mark,=C2=A0

Can you please review this patch..=C2=A0
<= br>
--Bilal

On Tue, 10 Dec 2019, 19:06 , <bilalwasim676@gmail.com> wr= ote:
From: bwasim <bilalwas= im676@gmail.com>

This addition ensures that the IP does NOT boot up in promiscuous mode
by default, and so the software only receives the desired
packets(Unicast, Broadcast, Unicast / Multicast hashed) by default.
The software running on-top of QEMU can also modify these settings and
disable reception of broadcast frames or make the IP receive all packets (P= ROM mode).
This patch greatly reduces the number of packets received by the
software running on-top of the QEMU model. Tested with the armv7-a SABRE_LI= TE machine.
Testing included running a custom OS with IPv4 / IPv6 support. Hashing
and filtering of packets is tested to work well. Skeleton taken from
the CADENCE_GEM IP and hash generation algorithm from the Linux Kernel.

Signed-off-by: Bilal Wasim <bilalwasim676@gmail.com>
---
=C2=A0hw/net/imx_fec.c=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0| 109 +++++++++++++= +++++++++++++++++++++++++-
=C2=A0include/hw/net/imx_fec.h |=C2=A0 10 ++++
=C2=A02 files changed, 118 insertions(+), 1 deletion(-)

diff --git a/hw/net/imx_fec.c b/hw/net/imx_fec.c
index bd99236864..d248f39fb0 100644
--- a/hw/net/imx_fec.c
+++ b/hw/net/imx_fec.c
@@ -419,6 +419,79 @@ static void imx_enet_write_bd(IMXENETBufDesc *bd, dma_= addr_t addr)
=C2=A0 =C2=A0 =C2=A0dma_memory_write(&address_space_memory, addr, bd, s= izeof(*bd));
=C2=A0}

+/*
+ * Calculate a FEC MAC Address hash index
+ */
+static unsigned calc_mac_hash(const uint8_t *mac, uint8_t mac_length)
+{
+=C2=A0 =C2=A0 uint32_t crc =3D net_crc32_le(mac, mac_length);
+
+=C2=A0 =C2=A0 /*
+=C2=A0 =C2=A0 =C2=A0* only upper 6 bits (FEC_HASH_BITS) are used
+=C2=A0 =C2=A0 =C2=A0* which point to specific bit in the hash registers +=C2=A0 =C2=A0 =C2=A0*/
+=C2=A0 =C2=A0 return (crc >> (32 - FEC_HASH_BITS)) & 0x3f;
+}
+
+/*
+ * fec_mac_address_filter:
+ * Accept or reject this destination address?
+ */
+static int fec_mac_address_filter(IMXFECState *s, const uint8_t *packet) +{
+=C2=A0 =C2=A0 const uint8_t broadcast_addr[] =3D { 0xFF, 0xFF, 0xFF, 0xFF,= 0xFF, 0xFF };
+=C2=A0 =C2=A0 uint32_t addr1, addr2;
+=C2=A0 =C2=A0 uint8_t=C2=A0 hash;
+
+=C2=A0 =C2=A0 /* Promiscuous mode? */
+=C2=A0 =C2=A0 if (s->regs[ENET_RCR] & ENET_RCR_PROM) {
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 /* Accept all packets in promiscuous mode (eve= n if bc_rej is set). */
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 return FEC_RX_PROMISCUOUS_ACCEPT;
+=C2=A0 =C2=A0 }
+
+=C2=A0 =C2=A0 /* Broadcast packet? */
+=C2=A0 =C2=A0 if (!memcmp(packet, broadcast_addr, 6)) {
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 /* Reject broadcast packets? */
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 if (s->regs[ENET_RCR] & ENET_RCR_BC_REJ= ) {
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 return FEC_RX_REJECT;
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 }
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 /* Accept packets from broadcast address. */ +=C2=A0 =C2=A0 =C2=A0 =C2=A0 return FEC_RX_BROADCAST_ACCEPT;
+=C2=A0 =C2=A0 }
+
+=C2=A0 =C2=A0 /* Accept packets -w- hash match? */
+=C2=A0 =C2=A0 hash =3D calc_mac_hash(packet, 6);
+
+=C2=A0 =C2=A0 /* Accept packets -w- multicast hash match? */
+=C2=A0 =C2=A0 if ((packet[0] & 0x01) =3D=3D 0x01) {
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 /* Computed hash matches GAUR / GALR register = ? */
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 if (((hash < 32) && (s->regs[ENE= T_GALR] & (1 << hash)))
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 || ((hash > 31)= && (s->regs[ENET_GAUR] & (1 << (hash - 32))))) {
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 /* Accept multicast hash enabled= address. */
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 return FEC_RX_MULTICAST_HASH_ACC= EPT;
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 }
+=C2=A0 =C2=A0 } else {
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 /* Computed hash matches IAUR / IALR register = ? */
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 if (((hash < 32) && (s->regs[ENE= T_IALR] & (1 << hash)))
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 || ((hash > 31)= && (s->regs[ENET_IAUR] & (1 << (hash - 32))))) {
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 /* Accept multicast hash enabled= address. */
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 return FEC_RX_UNICAST_HASH_ACCEP= T;
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 }
+=C2=A0 =C2=A0 }
+
+=C2=A0 =C2=A0 /* Match Unicast address. */
+=C2=A0 =C2=A0 addr1=C2=A0 =3D g_htonl(s->regs[ENET_PALR]);
+=C2=A0 =C2=A0 addr2=C2=A0 =3D g_htonl(s->regs[ENET_PAUR]);
+=C2=A0 =C2=A0 if (!(memcmp(packet, (uint8_t *) &addr1, 4) ||
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 memcmp(packet + 4, (uint8_t *) &add= r2, 2))) {
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 /* Accept packet because it matches my unicast= address. */
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 return FEC_RX_UNICAST_ACCEPT;
+=C2=A0 =C2=A0 }
+
+=C2=A0 =C2=A0 /* Return -1 because we do NOT support MAC address filtering= .. */
+=C2=A0 =C2=A0 return FEC_RX_REJECT;
+}
+
=C2=A0static void imx_eth_update(IMXFECState *s)
=C2=A0{
=C2=A0 =C2=A0 =C2=A0/*
@@ -984,7 +1057,7 @@ static void imx_eth_write(void *opaque, hwaddr offset,= uint64_t value,
=C2=A0 =C2=A0 =C2=A0case ENET_IALR:
=C2=A0 =C2=A0 =C2=A0case ENET_GAUR:
=C2=A0 =C2=A0 =C2=A0case ENET_GALR:
-=C2=A0 =C2=A0 =C2=A0 =C2=A0 /* TODO: implement MAC hash filtering.=C2=A0 *= /
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 s->regs[index] |=3D value;
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0break;
=C2=A0 =C2=A0 =C2=A0case ENET_TFWR:
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0if (s->is_fec) {
@@ -1066,8 +1139,15 @@ static ssize_t imx_fec_receive(NetClientState *nc, c= onst uint8_t *buf,
=C2=A0 =C2=A0 =C2=A0uint32_t buf_addr;
=C2=A0 =C2=A0 =C2=A0uint8_t *crc_ptr;
=C2=A0 =C2=A0 =C2=A0unsigned int buf_len;
+=C2=A0 =C2=A0 int maf;
=C2=A0 =C2=A0 =C2=A0size_t size =3D len;

+=C2=A0 =C2=A0 /* Is this destination MAC address "for us" ? */ +=C2=A0 =C2=A0 maf =3D fec_mac_address_filter(s, buf);
+=C2=A0 =C2=A0 if (maf =3D=3D FEC_RX_REJECT) {
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 return FEC_RX_REJECT;
+=C2=A0 =C2=A0 }
+
=C2=A0 =C2=A0 =C2=A0FEC_PRINTF("len %d\n", (int)size);

=C2=A0 =C2=A0 =C2=A0if (!s->regs[ENET_RDAR]) {
@@ -1133,6 +1213,16 @@ static ssize_t imx_fec_receive(NetClientState *nc, c= onst uint8_t *buf,
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0} else {
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0s->regs[ENET_EIR] |=3D E= NET_INT_RXB;
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0}
+
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 /* Update descriptor based on the "maf&qu= ot; flag. */
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 if (maf =3D=3D FEC_RX_BROADCAST_ACCEPT) {
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 /* The packet is destined for th= e "broadcast" address. */
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 bd.flags |=3D ENET_BD_BC;
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 } else if (maf =3D=3D FEC_RX_MULTICAST_HASH_AC= CEPT) {
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 /* The packet is destined for a = "multicast" address. */
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 bd.flags |=3D ENET_BD_MC;
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 }
+
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0imx_fec_write_bd(&bd, addr);
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0/* Advance to the next descriptor.=C2=A0 = */
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0if ((bd.flags & ENET_BD_W) !=3D 0) {<= br> @@ -1159,8 +1249,15 @@ static ssize_t imx_enet_receive(NetClientState *nc, = const uint8_t *buf,
=C2=A0 =C2=A0 =C2=A0uint8_t *crc_ptr;
=C2=A0 =C2=A0 =C2=A0unsigned int buf_len;
=C2=A0 =C2=A0 =C2=A0size_t size =3D len;
+=C2=A0 =C2=A0 int maf;
=C2=A0 =C2=A0 =C2=A0bool shift16 =3D s->regs[ENET_RACC] & ENET_RACC_= SHIFT16;

+=C2=A0 =C2=A0 /* Is this destination MAC address "for us" ? */ +=C2=A0 =C2=A0 maf =3D fec_mac_address_filter(s, buf);
+=C2=A0 =C2=A0 if (maf =3D=3D FEC_RX_REJECT) {
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 return FEC_RX_REJECT;
+=C2=A0 =C2=A0 }
+
=C2=A0 =C2=A0 =C2=A0FEC_PRINTF("len %d\n", (int)size);

=C2=A0 =C2=A0 =C2=A0if (!s->regs[ENET_RDAR]) {
@@ -1254,6 +1351,16 @@ static ssize_t imx_enet_receive(NetClientState *nc, = const uint8_t *buf,
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0s->regs[EN= ET_EIR] |=3D ENET_INT_RXB;
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0}
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0}
+
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 /* Update descriptor based on the "maf&qu= ot; flag. */
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 if (maf =3D=3D FEC_RX_BROADCAST_ACCEPT) {
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 /* The packet is destined for th= e "broadcast" address. */
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 bd.flags |=3D ENET_BD_BC;
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 } else if (maf =3D=3D FEC_RX_MULTICAST_HASH_AC= CEPT) {
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 /* The packet is destined for a = "multicast" address. */
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 bd.flags |=3D ENET_BD_MC;
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 }
+
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0imx_enet_write_bd(&bd, addr);
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0/* Advance to the next descriptor.=C2=A0 = */
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0if ((bd.flags & ENET_BD_W) !=3D 0) {<= br> diff --git a/include/hw/net/imx_fec.h b/include/hw/net/imx_fec.h
index 7b3faa4019..f9cfcf6af5 100644
--- a/include/hw/net/imx_fec.h
+++ b/include/hw/net/imx_fec.h
@@ -275,4 +275,14 @@ typedef struct IMXFECState {
=C2=A0 =C2=A0 =C2=A0uint8_t frame[ENET_MAX_FRAME_SIZE];
=C2=A0} IMXFECState;

+/* FEC address filtering defines. */
+#define FEC_RX_REJECT=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0(-1)
+#define FEC_RX_PROMISCUOUS_ACCEPT=C2=A0 =C2=A0 =C2=A0 =C2=A0(-2)
+#define FEC_RX_BROADCAST_ACCEPT=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0(-3)
+#define FEC_RX_MULTICAST_HASH_ACCEPT=C2=A0 =C2=A0 (-4)
+#define FEC_RX_UNICAST_HASH_ACCEPT=C2=A0 =C2=A0 =C2=A0 (-5)
+#define FEC_RX_UNICAST_ACCEPT=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0(-6)=
+
+#define FEC_HASH_BITS=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 6=C2=A0 =C2=A0 /* #bits in hash */
+
=C2=A0#endif
--
2.19.1.windows.1

--000000000000904c1905997c4a91-- From MAILER-DAEMON Thu Dec 12 03:24:18 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1ifJli-0007z3-9y for mharc-qemu-arm@gnu.org; Thu, 12 Dec 2019 03:24:18 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:41649) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ifJlg-0007yr-E5 for qemu-arm@nongnu.org; Thu, 12 Dec 2019 03:24:17 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ifJlf-0005IE-75 for qemu-arm@nongnu.org; Thu, 12 Dec 2019 03:24:16 -0500 Received: from mail-wr1-x443.google.com ([2a00:1450:4864:20::443]:47029) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ifJle-0005F3-TE for qemu-arm@nongnu.org; Thu, 12 Dec 2019 03:24:15 -0500 Received: by mail-wr1-x443.google.com with SMTP id z7so1649830wrl.13 for ; Thu, 12 Dec 2019 00:24:14 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=references:user-agent:from:to:cc:subject:in-reply-to:date :message-id:mime-version:content-transfer-encoding; bh=rxDuF8q057BBMFCFSCcmamg2/fH9WqJQOlSrvULGGrU=; b=F/xr6rCHX3dJUOncFVqtOR6c3PDPXjUbkjsSAwBorTyp5TgliBdxXQaG7+Cx7JfPxh lB0Pq3rFAwSmLkI5fQ88KyVB52Xn3ptfvcsKX86Mi7q+m64YWGhH9CFx8GatnTDpfpPz b7sy+O3oHLqwQM3P77oteerGGaE5/m4FAHNCHyiAST90e46iCAtovQFloRF85ourENU6 HD2mejOaEfE21zihYCEB+6SSAqwOmKZDZNwc1Zl85ukO2vQE6CUzZISNebzkv8KqTPA9 +gasHL14KsZODTlIKqFp6zp7APBv9OEAioHUliCWunlhJWdnzhv/rYXW88ZeRXDpUQNx T4Lg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:references:user-agent:from:to:cc:subject :in-reply-to:date:message-id:mime-version:content-transfer-encoding; bh=rxDuF8q057BBMFCFSCcmamg2/fH9WqJQOlSrvULGGrU=; b=HvGlROrhs9LGl7FJeTboK2Nw2KCvhNfgvbj65t5XYIvVW+QKXv8DR9Zl/zW6QwPw6R 2NauZsRbzykKi81j3SZhYwXbT95CN3SZMktOPZo2GqcOJYhj9Iz2v4Niy82HPx5k8iKY rHLrIETAXvfHiaAOhcDUV+iMJ6iH2SUUXYBkI2HvNHAGd0UQhhe9LVW1dMOfqQR3R+ev J4ZTqn7oZst3mnQxHcx51EItSF1YuPVvr6QnCL7G3EyHX6hJUZS5+TEV6/Yzx2yzYu3/ Wq61qEBNaKL3mWDmpYb7x0X3Cqenv7ftqMSdKq0O6zPek/72Az3Bpj2LerbElk84X1Sm Adow== X-Gm-Message-State: APjAAAW+3/VA34aaQP6xZC0yczfjpxC49/2Mjz2cea5AJFxbFi0MPgKu JsqWA55oivD4g6X4V/O9wTlDDA== X-Google-Smtp-Source: APXvYqxf4wgI/yR8T8tYoBTudiWwU4pMkwZubN8Q0F69OSJLSvPj3yHVxk14tSgSjWOCZhA1NujBBA== X-Received: by 2002:a05:6000:149:: with SMTP id r9mr4722484wrx.147.1576139053386; Thu, 12 Dec 2019 00:24:13 -0800 (PST) Received: from zen.linaroharston ([51.148.130.216]) by smtp.gmail.com with ESMTPSA id 2sm5239886wrq.31.2019.12.12.00.24.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 12 Dec 2019 00:24:12 -0800 (PST) Received: from zen (localhost [127.0.0.1]) by zen.linaroharston (Postfix) with ESMTP id 4B3C51FF87; Thu, 12 Dec 2019 08:24:11 +0000 (GMT) References: <20191211170520.7747-1-alex.bennee@linaro.org> <20191211170520.7747-13-alex.bennee@linaro.org> <69e10c48-8bdf-cbe0-3372-815b647f8312@linaro.org> User-agent: mu4e 1.3.5; emacs 27.0.50 From: Alex =?utf-8?Q?Benn=C3=A9e?= To: Richard Henderson Cc: qemu-devel@nongnu.org, alan.hayward@arm.com, luis.machado@linaro.org, damien.hedde@greensocs.com, Peter Maydell , "open list:ARM TCG CPUs" Subject: Re: [PATCH v3 12/20] target/arm: generate xml description of our SVE registers In-reply-to: <69e10c48-8bdf-cbe0-3372-815b647f8312@linaro.org> Date: Thu, 12 Dec 2019 08:24:11 +0000 Message-ID: <87y2vi0x5g.fsf@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::443 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 12 Dec 2019 08:24:17 -0000 Richard Henderson writes: > On 12/11/19 9:05 AM, Alex Benn=C3=A9e wrote: >> +static struct TypeSize vec_lanes[] =3D { > > const. > >> + case 51: >> + return gdb_get_reg64(buf, (cpu->env.vfp.zcr_el[1] & 0xf) + 1); > > You need to use sve_zcr_len_for_el to get the effective vq. > Also, I thought vg =3D=3D 2 * vq. > > + case 51: >> + { >> + uint64_t val =3D *(uint64_t *) buf; >> + cpu->env.vfp.zcr_el[1] =3D (val - 1) & 0xf; > > You cannot hard-code EL1 without ifdef CONFIG_USER_ONLY. If the effectiv= e vq > decreases, you must call aarch64_sve_narrow_vq. You must call > arm_rebuild_hflags. Hmm thinking about it this is overriding the kernels competencies - it should be read only as it is a "virtual" register. Given gdbserver doesn't use the value and will most likely use dynamic XML we could just drop it altogether.=20 > > > r~ --=20 Alex Benn=C3=A9e From MAILER-DAEMON Thu Dec 12 06:47:55 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1ifMwk-0002nX-Tl for mharc-qemu-arm@gnu.org; Thu, 12 Dec 2019 06:47:54 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:40097) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ifMwi-0002nA-40 for qemu-arm@nongnu.org; Thu, 12 Dec 2019 06:47:53 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ifMwg-0004vh-L4 for qemu-arm@nongnu.org; Thu, 12 Dec 2019 06:47:51 -0500 Received: from mail-wr1-x443.google.com ([2a00:1450:4864:20::443]:39527) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ifMwg-0004tA-BA for qemu-arm@nongnu.org; Thu, 12 Dec 2019 06:47:50 -0500 Received: by mail-wr1-x443.google.com with SMTP id y11so2398084wrt.6 for ; Thu, 12 Dec 2019 03:47:50 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=QM15Kq7l2rtZD3l31WMeE+oAwNwZWxd9GAGGi1JsolM=; b=ktYEIq46Dpaf+Iz5Q+YGqaYUgueNheaKh7TOKJbh4IbqbZkb2PRw35ImuJn/D9PNeU RGiKQ6YKsydAv5LNThtsZYiUQ0LI+O9AVctG9Tzh7gt2AuTCERReMC0HHimzZ7tM7hdT 9Het8vLiSp6ecOQ9AfFZLHJp1mmRH40mU1P5vjajtJ+pKa9yi/63IAHKluLsshGC38FE vqgv1qfbmzlUiRVbkH7Aom9JdKi2erQS965SaTsQyYB0ySLIVQTty9GXgpnlWpGzEaHT WiHzGA1mFE18E4PX29j/SWOBA6nZ76KJElELBJ2TyXGOBJ/R04iDtLpcrl7lNqzaPioX R0yQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=QM15Kq7l2rtZD3l31WMeE+oAwNwZWxd9GAGGi1JsolM=; b=fBy54NAU1Ky9LqZ9TD5wFalYP7w6Qn/y1E+ZQ3Z2+OTHk5n3HUFiuWKnA2V2cYj1Vs 4CH572TT8qwZ9xGfkoR1PWHh8Vkp9NYL1XOiRhjyZFNxXploF6e1PURHlpxcVJBRUKG3 E8+XYvDzMfW43ZwRJ2XbSc761rbUSWD3ScwD5EdjdmOPm6+aFglSjXhYw8ljoJJHb6In rM5z/YayLVhZsM1n6/WRmEqO9BkMrgQpVMR2vzMr8q+EdeD7uJPpDecT9TFhL8GqaZet UDNBeblGuTkIvAZ7OGtxFCXrYf7tGeZX5K53IrSICB0mtu1VqO++UlMeZdnXEsw0Ike2 ZcVA== X-Gm-Message-State: APjAAAWaSdmrG/XB5h9GAGxnhCm6Brzu+yIOjFDpMAz3rUbjR74ZxPvj hkHtoveM5SnyAoX9Npjyjwp4rA== X-Google-Smtp-Source: APXvYqzF7F77ukhJrmaFi6wsHEfW/RR9wOdyj5fjBaXxqJbxPtwNqqWc1ioSSIm+lZoBtrhmTmGYHA== X-Received: by 2002:adf:df0e:: with SMTP id y14mr5404817wrl.377.1576151268470; Thu, 12 Dec 2019 03:47:48 -0800 (PST) Received: from zen.linaroharston ([51.148.130.216]) by smtp.gmail.com with ESMTPSA id n3sm5492409wrs.8.2019.12.12.03.47.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 12 Dec 2019 03:47:46 -0800 (PST) Received: from zen.lan (localhost [127.0.0.1]) by zen.linaroharston (Postfix) with ESMTP id 097061FF87; Thu, 12 Dec 2019 11:47:46 +0000 (GMT) From: =?UTF-8?q?Alex=20Benn=C3=A9e?= To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, =?UTF-8?q?Alex=20Benn=C3=A9e?= , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Richard Henderson , Peter Maydell Subject: [PATCH v2] target/arm: ensure we use current exception state after SCR update Date: Thu, 12 Dec 2019 11:47:34 +0000 Message-Id: <20191212114734.6962-1-alex.bennee@linaro.org> X-Mailer: git-send-email 2.20.1 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::443 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 12 Dec 2019 11:47:53 -0000 A write to the SCR can change the effective EL by droppping the system from secure to non-secure mode. However if we use a cached current_el from before the change we'll rebuild the flags incorrectly. To fix this we introduce the ARM_CP_NEWEL CP flag to indicate the new EL should be used when recomputing the flags. Signed-off-by: Alex Bennée Tested-by: Philippe Mathieu-Daudé Cc: Richard Henderson Message-Id: <20191209143723.6368-1-alex.bennee@linaro.org> --- v2 - don't override a ARM_CP_SPECIAL, use a new flag --- target/arm/cpu.h | 8 ++++++-- target/arm/helper.h | 1 + target/arm/helper.c | 14 +++++++++++++- target/arm/translate.c | 6 +++++- 4 files changed, 25 insertions(+), 4 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 83a809d4bac..c3ab47d8962 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -2238,6 +2238,9 @@ static inline uint64_t cpreg_to_kvm_id(uint32_t cpregid) * RAISES_EXC is for when the read or write hook might raise an exception; * the generated code will synchronize the CPU state before calling the hook * so that it is safe for the hook to call raise_exception(). + * NEWEL is for writes to registers that might change the exception + * level - typically on older ARM chips. For those cases we need to + * re-read the new el when recomputing the translation flags. */ #define ARM_CP_SPECIAL 0x0001 #define ARM_CP_CONST 0x0002 @@ -2257,10 +2260,11 @@ static inline uint64_t cpreg_to_kvm_id(uint32_t cpregid) #define ARM_CP_SVE 0x2000 #define ARM_CP_NO_GDB 0x4000 #define ARM_CP_RAISES_EXC 0x8000 +#define ARM_CP_NEWEL 0x10000 /* Used only as a terminator for ARMCPRegInfo lists */ -#define ARM_CP_SENTINEL 0xffff +#define ARM_CP_SENTINEL 0xfffff /* Mask of only the flag bits in a type field */ -#define ARM_CP_FLAG_MASK 0xf0ff +#define ARM_CP_FLAG_MASK 0x1f0ff /* Valid values for ARMCPRegInfo state field, indicating which of * the AArch32 and AArch64 execution states this register is visible in. diff --git a/target/arm/helper.h b/target/arm/helper.h index 3d4ec267a2c..e345bdb726a 100644 --- a/target/arm/helper.h +++ b/target/arm/helper.h @@ -91,6 +91,7 @@ DEF_HELPER_2(get_user_reg, i32, env, i32) DEF_HELPER_3(set_user_reg, void, env, i32, i32) DEF_HELPER_FLAGS_2(rebuild_hflags_m32, TCG_CALL_NO_RWG, void, env, int) +DEF_HELPER_FLAGS_1(rebuild_hflags_a32_newel, TCG_CALL_NO_RWG, void, env) DEF_HELPER_FLAGS_2(rebuild_hflags_a32, TCG_CALL_NO_RWG, void, env, int) DEF_HELPER_FLAGS_2(rebuild_hflags_a64, TCG_CALL_NO_RWG, void, env, int) diff --git a/target/arm/helper.c b/target/arm/helper.c index 0bf8f53d4b8..b92ef9d1905 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -5096,7 +5096,7 @@ static const ARMCPRegInfo el3_cp_reginfo[] = { .opc0 = 3, .opc1 = 6, .crn = 1, .crm = 1, .opc2 = 0, .access = PL3_RW, .fieldoffset = offsetof(CPUARMState, cp15.scr_el3), .resetvalue = 0, .writefn = scr_write }, - { .name = "SCR", .type = ARM_CP_ALIAS, + { .name = "SCR", .type = ARM_CP_ALIAS | ARM_CP_NEWEL, .cp = 15, .opc1 = 0, .crn = 1, .crm = 1, .opc2 = 0, .access = PL1_RW, .accessfn = access_trap_aa32s_el1, .fieldoffset = offsetoflow32(CPUARMState, cp15.scr_el3), @@ -11332,6 +11332,18 @@ void HELPER(rebuild_hflags_m32)(CPUARMState *env, int el) env->hflags = rebuild_hflags_m32(env, fp_el, mmu_idx); } +/* + * If we have triggered a EL state change we can't rely on the + * translator having passed it too us, we need to recompute. + */ +void HELPER(rebuild_hflags_a32_newel)(CPUARMState *env) +{ + int el = arm_current_el(env); + int fp_el = fp_exception_el(env, el); + ARMMMUIdx mmu_idx = arm_mmu_idx_el(env, el); + env->hflags = rebuild_hflags_a32(env, fp_el, mmu_idx); +} + void HELPER(rebuild_hflags_a32)(CPUARMState *env, int el) { int fp_el = fp_exception_el(env, el); diff --git a/target/arm/translate.c b/target/arm/translate.c index 4d5d4bd8886..83aa331b1ec 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -7083,7 +7083,11 @@ static int disas_coproc_insn(DisasContext *s, uint32_t insn) if (arm_dc_feature(s, ARM_FEATURE_M)) { gen_helper_rebuild_hflags_m32(cpu_env, tcg_el); } else { - gen_helper_rebuild_hflags_a32(cpu_env, tcg_el); + if (ri->type & ARM_CP_NEWEL) { + gen_helper_rebuild_hflags_a32_newel(cpu_env); + } else { + gen_helper_rebuild_hflags_a32(cpu_env, tcg_el); + } } tcg_temp_free_i32(tcg_el); /* -- 2.20.1 From MAILER-DAEMON Thu Dec 12 07:17:59 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1ifNPr-0002ff-Cz for mharc-qemu-arm@gnu.org; Thu, 12 Dec 2019 07:17:59 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:47660) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ifNPn-0002bk-LQ for qemu-arm@nongnu.org; Thu, 12 Dec 2019 07:17:57 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ifNPl-0006SX-Su for qemu-arm@nongnu.org; Thu, 12 Dec 2019 07:17:55 -0500 Received: from us-smtp-delivery-1.mimecast.com ([205.139.110.120]:37976 helo=us-smtp-1.mimecast.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1ifNPl-0006Q6-OI for qemu-arm@nongnu.org; Thu, 12 Dec 2019 07:17:53 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1576153072; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=SPps5pjUQ1DqbB9eL0sR2YL+0LU4DhfwVxAWCNLMeVg=; b=C7/HqZqofy51eTd4+P+CXFs1dW2kzy52P6Sy/dRTfOEhXJ5TjL/sGlZDYG2ac+L1G4jnSX /gQYPb8WD8epY+pE2CVmXu5f2kvTYi+ynV/9jHQRHYzQqYGV4qBr4SasZxpwKZD004qFcU s1yQeTbsvYS3TL1a+TdAXMQ7M8ytA7o= Received: from mimecast-mx01.redhat.com (mimecast-mx01.redhat.com [209.132.183.4]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-142-UphCh6iQPu6JGUu1v8VQgQ-1; Thu, 12 Dec 2019 07:17:51 -0500 Received: from smtp.corp.redhat.com (int-mx04.intmail.prod.int.phx2.redhat.com [10.5.11.14]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx01.redhat.com (Postfix) with ESMTPS id 3EDA4477; Thu, 12 Dec 2019 12:17:49 +0000 (UTC) Received: from blackfin.pond.sub.org (ovpn-116-181.ams2.redhat.com [10.36.116.181]) by smtp.corp.redhat.com (Postfix) with ESMTPS id 73BF15D9C9; Thu, 12 Dec 2019 12:17:41 +0000 (UTC) Received: by blackfin.pond.sub.org (Postfix, from userid 1000) id 08E3111386A7; Thu, 12 Dec 2019 13:17:40 +0100 (CET) From: Markus Armbruster To: Eric Auger Cc: eric.auger.pro@gmail.com, qemu-devel@nongnu.org, qemu-arm@nongnu.org, peter.maydell@linaro.org, mst@redhat.com, armbru@redhat.com, jean-philippe.brucker@arm.com, bharatb.linux@gmail.com, yang.zhong@intel.com, dgilbert@redhat.com, quintela@redhat.com, kevin.tian@intel.com, peterx@redhat.com, tnowicki@marvell.com Subject: Re: [PATCH for-5.0 v11 12/20] qapi: Introduce DEFINE_PROP_INTERVAL References: <20191122182943.4656-1-eric.auger@redhat.com> <20191122182943.4656-13-eric.auger@redhat.com> Date: Thu, 12 Dec 2019 13:17:40 +0100 In-Reply-To: <20191122182943.4656-13-eric.auger@redhat.com> (Eric Auger's message of "Fri, 22 Nov 2019 19:29:35 +0100") Message-ID: <87wob17n6j.fsf@dusky.pond.sub.org> User-Agent: Gnus/5.13 (Gnus v5.13) Emacs/26.2 (gnu/linux) MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.79 on 10.5.11.14 X-MC-Unique: UphCh6iQPu6JGUu1v8VQgQ-1 X-Mimecast-Spam-Score: 0 Content-Type: text/plain Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 205.139.110.120 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 12 Dec 2019 12:17:57 -0000 Eric Auger writes: > Introduce a new property defining a labelled interval: > ,,label. > > This will be used to encode reserved IOVA regions. The label > is left undefined to ease reuse accross use cases. What does the last sentence mean? > For instance, in virtio-iommu use case, reserved IOVA regions > will be passed by the machine code to the virtio-iommu-pci > device (an array of those). The label will match the > virtio_iommu_probe_resv_mem subtype value: > - VIRTIO_IOMMU_RESV_MEM_T_RESERVED (0) > - VIRTIO_IOMMU_RESV_MEM_T_MSI (1) > > This is used to inform the virtio-iommu-pci device it should > bypass the MSI region: 0xfee00000, 0xfeefffff, 1. So the "label" part of ",,label" is a number? Is a number appropriate for your use case, or would an enum be better? > > Signed-off-by: Eric Auger --- >hw/core/qdev-properties.c | 90 ++++++++++++++++++++++++++++++++++++ >include/exec/memory.h | 6 +++ include/hw/qdev-properties.h | 3 ++ >include/qemu/typedefs.h | 1 + 4 files changed, 100 insertions(+) Subject has 'qapi:', but it's actually about qdev. Please adjust the subje= ct. > diff --git a/hw/core/qdev-properties.c b/hw/core/qdev-properties.c > index ac28890e5a..8d70f34e37 100644 > --- a/hw/core/qdev-properties.c > +++ b/hw/core/qdev-properties.c > @@ -13,6 +13,7 @@ > #include "qapi/visitor.h" > #include "chardev/char.h" > #include "qemu/uuid.h" > +#include "qemu/cutils.h" > =20 > void qdev_prop_set_after_realize(DeviceState *dev, const char *name, > Error **errp) > @@ -585,6 +586,95 @@ const PropertyInfo qdev_prop_macaddr =3D { > .set =3D set_mac, > }; > =20 > +/* --- Labelled Interval --- */ > + > +/* > + * accepted syntax versions: "versions"? > + * ,, > + * where low/high addresses are uint64_t in hexa (feat. 0x prefix) "hexa" is not a word. I'm afraid I don't get the parenthesis. > + * and type is an unsigned integer > + */ > +static void get_interval(Object *obj, Visitor *v, const char *name, > + void *opaque, Error **errp) > +{ > + DeviceState *dev =3D DEVICE(obj); > + Property *prop =3D opaque; > + Interval *interval =3D qdev_get_prop_ptr(dev, prop); > + char buffer[64]; > + char *p =3D buffer; > + > + Snprintf(buffer, sizeof(buffer), "0x%"PRIx64",0x%"PRIx64",%d", > + interval->low, interval->high, interval->type); interval->type is unsigned. Use %u, not %d. > + > + visit_type_str(v, name, &p, errp); > +} > + > +static void set_interval(Object *obj, Visitor *v, const char *name, > + void *opaque, Error **errp) > +{ > + DeviceState *dev =3D DEVICE(obj); > + Property *prop =3D opaque; > + Interval *interval =3D qdev_get_prop_ptr(dev, prop); > + Error *local_err =3D NULL; > + unsigned int type; > + gchar **fields; > + uint64_t addr; > + char *str; > + int ret; > + > + if (dev->realized) { > + qdev_prop_set_after_realize(dev, name, errp); > + return; > + } > + > + visit_type_str(v, name, &str, &local_err); > + if (local_err) { > + error_propagate(errp, local_err); > + return; > + } > + > + fields =3D g_strsplit(str, ",", 3); > + > + ret =3D qemu_strtou64(fields[0], NULL, 16, &addr); Aha, the 0x prefix is actually optional. > + if (!ret) { > + interval->low =3D addr; > + } else { > + error_setg(errp, "Failed to decode interval low addr"); > + error_append_hint(errp, > + "should be an address in hexa with 0x prefix\n= "); "hexa" is not a word, and the 0x prefix is actually optional. > + goto out; > + } I prefer if (error) { handle error bail out } handle success over if (success) { handle success if (error) { handle error bail out } In this case: if (ret) { error_setg(errp, "Failed to decode interval low addr"); error_append_hint(errp, "should be an address in hexa with 0x prefix\n= "); goto out; } interval->low =3D addr; > + > + ret =3D qemu_strtou64(fields[1], NULL, 16, &addr); Crash if @str doesn't contain ',', because the g_strsplit(str, ",", 3) yields { [0] =3D str, NULL }. > + if (!ret) { > + interval->high =3D addr; > + } else { > + error_setg(errp, "Failed to decode interval high addr"); > + error_append_hint(errp, > + "should be an address in hexa with 0x prefix\n= "); > + goto out; > + } > + > + ret =3D qemu_strtoui(fields[2], NULL, 10, &type); Likewise, crash if @str contains only one ','. I wouldn't use g_strsplit() here. After ret =3D qemu_strtoui(str, &endptr, 16, &interval->low); @endptr points behind the address. So: if (ret || *endptr !=3D ',') { handle error ... goto out } ret =3D qemu_strtoui(endptr + 1, &endptr, 16, &interval->high); and so forth. Note that the if (ret || *endptr !=3D ',') checks for two distinct errors. Distinct error messages might be more helpful. > + if (!ret) { > + interval->type =3D type; > + } else { > + error_setg(errp, "Failed to decode interval type"); > + error_append_hint(errp, "should be an unsigned int in decimal\n"= ); > + } > +out: > + g_free(str); > + g_strfreev(fields); > + return; > +} > + > +const PropertyInfo qdev_prop_interval =3D { > + .name =3D "labelled_interval", > + .description =3D "Labelled interval, example: 0xFEE00000,0xFEEFFFFF,= 0", > + .get =3D get_interval, > + .set =3D set_interval, > +}; > + > /* --- on/off/auto --- */ > =20 > const PropertyInfo qdev_prop_on_off_auto =3D { > diff --git a/include/exec/memory.h b/include/exec/memory.h > index e499dc215b..e238d1c352 100644 > --- a/include/exec/memory.h > +++ b/include/exec/memory.h > @@ -57,6 +57,12 @@ struct MemoryRegionMmio { > CPUWriteMemoryFunc *write[3]; > }; > =20 > +struct Interval { > + hwaddr low; > + hwaddr high; > + unsigned int type; > +}; This isn't an interval. An interval consists of two values, not three. The third one is called "type" here, and "label" elsewhere. Pick one and stick to it. Then pick a name for the triple. Elsewhere, you call it "labelled interval". > + > typedef struct IOMMUTLBEntry IOMMUTLBEntry; > =20 > /* See address_space_translate: bit 0 is read, bit 1 is write. */ > diff --git a/include/hw/qdev-properties.h b/include/hw/qdev-properties.h > index c6a8cb5516..2ba7c8711b 100644 > --- a/include/hw/qdev-properties.h > +++ b/include/hw/qdev-properties.h > @@ -20,6 +20,7 @@ extern const PropertyInfo qdev_prop_chr; > extern const PropertyInfo qdev_prop_tpm; > extern const PropertyInfo qdev_prop_ptr; > extern const PropertyInfo qdev_prop_macaddr; > +extern const PropertyInfo qdev_prop_interval; > extern const PropertyInfo qdev_prop_on_off_auto; > extern const PropertyInfo qdev_prop_losttickpolicy; > extern const PropertyInfo qdev_prop_blockdev_on_error; > @@ -202,6 +203,8 @@ extern const PropertyInfo qdev_prop_pcie_link_width; > DEFINE_PROP(_n, _s, _f, qdev_prop_drive_iothread, BlockBackend *) > #define DEFINE_PROP_MACADDR(_n, _s, _f) \ > DEFINE_PROP(_n, _s, _f, qdev_prop_macaddr, MACAddr) > +#define DEFINE_PROP_INTERVAL(_n, _s, _f) \ > + DEFINE_PROP(_n, _s, _f, qdev_prop_interval, Interval) > #define DEFINE_PROP_ON_OFF_AUTO(_n, _s, _f, _d) \ > DEFINE_PROP_SIGNED(_n, _s, _f, _d, qdev_prop_on_off_auto, OnOffAuto) > #define DEFINE_PROP_LOSTTICKPOLICY(_n, _s, _f, _d) \ > diff --git a/include/qemu/typedefs.h b/include/qemu/typedefs.h > index 375770a80f..a827c9a3fe 100644 > --- a/include/qemu/typedefs.h > +++ b/include/qemu/typedefs.h > @@ -58,6 +58,7 @@ typedef struct ISABus ISABus; > typedef struct ISADevice ISADevice; > typedef struct IsaDma IsaDma; > typedef struct MACAddr MACAddr; > +typedef struct Interval Interval; > typedef struct MachineClass MachineClass; > typedef struct MachineState MachineState; > typedef struct MemoryListener MemoryListener; From MAILER-DAEMON Thu Dec 12 07:48:58 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1ifNtp-0006F3-Uo for mharc-qemu-arm@gnu.org; Thu, 12 Dec 2019 07:48:57 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:37872) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ifNtn-0006Aw-0p for qemu-arm@nongnu.org; Thu, 12 Dec 2019 07:48:56 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ifNtl-0005sE-Pk for qemu-arm@nongnu.org; Thu, 12 Dec 2019 07:48:54 -0500 Received: from us-smtp-2.mimecast.com ([207.211.31.81]:50051 helo=us-smtp-delivery-1.mimecast.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1ifNtl-0005qz-K7 for qemu-arm@nongnu.org; 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Thu, 12 Dec 2019 12:48:48 +0000 (UTC) Received: from dell-r430-03.lab.eng.brq.redhat.com (dell-r430-03.lab.eng.brq.redhat.com [10.37.153.18]) by smtp.corp.redhat.com (Postfix) with ESMTP id 4E91710013A1; Thu, 12 Dec 2019 12:48:46 +0000 (UTC) From: Igor Mammedov To: qemu-devel@nongnu.org Cc: Eduardo Habkost , Marcel Apfelbaum , Tao Xu , Radoslaw Biernacki , Peter Maydell , Leif Lindholm , qemu-arm@nongnu.org, qemu-stable@nongnu.org Subject: [PATCH 2/2] numa: properly check if numa is supported Date: Thu, 12 Dec 2019 13:48:56 +0100 Message-Id: <1576154936-178362-3-git-send-email-imammedo@redhat.com> In-Reply-To: <1576154936-178362-1-git-send-email-imammedo@redhat.com> References: <1576154936-178362-1-git-send-email-imammedo@redhat.com> X-Scanned-By: MIMEDefang 2.84 on 10.5.11.22 X-MC-Unique: Xs1KILyFN56-Kb0m_Vc_dQ-1 X-Mimecast-Spam-Score: 0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 207.211.31.81 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 12 Dec 2019 12:48:56 -0000 Commit aa57020774b, by mistake used MachineClass::numa_mem_supported to check if NUMA is supported by machine and also as unrelated change set it to true for sbsa-ref board. Luckily change didn't break machines that support NUMA, as the field is set to true for them. But the field is not intended for checking if NUMA is supported and will be flipped to false within this release for new machine types. Fix it: - by using previously used condition !mc->cpu_index_to_instance_props || !mc->get_default_cpu_node_id the first time and then use MachineState::numa_state down the road to check if NUMA is supported - dropping stray sbsa-ref chunk Fixes: aa57020774b690a22be72453b8e91c9b5a68c516 Signed-off-by: Igor Mammedov --- CC: Radoslaw Biernacki CC: Peter Maydell CC: Leif Lindholm CC: qemu-arm@nongnu.org CC: qemu-stable@nongnu.org hw/arm/sbsa-ref.c | 1 - hw/core/machine.c | 4 ++-- 2 files changed, 2 insertions(+), 3 deletions(-) diff --git a/hw/arm/sbsa-ref.c b/hw/arm/sbsa-ref.c index 27046cc..c6261d4 100644 --- a/hw/arm/sbsa-ref.c +++ b/hw/arm/sbsa-ref.c @@ -791,7 +791,6 @@ static void sbsa_ref_class_init(ObjectClass *oc, void *= data) mc->possible_cpu_arch_ids =3D sbsa_ref_possible_cpu_arch_ids; mc->cpu_index_to_instance_props =3D sbsa_ref_cpu_index_to_props; mc->get_default_cpu_node_id =3D sbsa_ref_get_default_cpu_node_id; - mc->numa_mem_supported =3D true; } =20 static const TypeInfo sbsa_ref_info =3D { diff --git a/hw/core/machine.c b/hw/core/machine.c index 1689ad3..aa63231 100644 --- a/hw/core/machine.c +++ b/hw/core/machine.c @@ -958,7 +958,7 @@ static void machine_initfn(Object *obj) NULL); } =20 - if (mc->numa_mem_supported) { + if (mc->cpu_index_to_instance_props && mc->get_default_cpu_node_id) { ms->numa_state =3D g_new0(NumaState, 1); } =20 @@ -1102,7 +1102,7 @@ void machine_run_board_init(MachineState *machine) { MachineClass *machine_class =3D MACHINE_GET_CLASS(machine); =20 - if (machine_class->numa_mem_supported) { + if (machine->numa_state) { numa_complete_configuration(machine); if (machine->numa_state->num_nodes) { machine_numa_finish_cpu_init(machine); --=20 2.7.4 From MAILER-DAEMON Thu Dec 12 09:36:46 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1ifPaA-00048E-KO for mharc-qemu-arm@gnu.org; Thu, 12 Dec 2019 09:36:46 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:37835) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ifPa8-00046M-2y for qemu-arm@nongnu.org; Thu, 12 Dec 2019 09:36:45 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ifPa6-0003DJ-Uq for qemu-arm@nongnu.org; Thu, 12 Dec 2019 09:36:43 -0500 Received: from mail-pl1-x642.google.com ([2607:f8b0:4864:20::642]:40748) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ifPa6-0003Bj-OV for qemu-arm@nongnu.org; Thu, 12 Dec 2019 09:36:42 -0500 Received: by mail-pl1-x642.google.com with SMTP id g6so671822plp.7 for ; Thu, 12 Dec 2019 06:36:42 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=subject:to:cc:references:from:message-id:date:user-agent :mime-version:in-reply-to:content-language:content-transfer-encoding; bh=4I97tvfKMitrkdF5Fr4FiNCpy5zuXp19tZu9yklSAnE=; b=RRSwl4xerrREgUaHPFRGjdEwLZkWmMs/7lhrhHm9aK3lT3xF97ub4nfb2uRMwGB6Ro IBUzG5MPZesDWl7qqgHkQGGifBxYUnGzJjSqQ9dsfmaPAVMN3F37hip/ZExT35+X0JND Y5GhaITJjSIAbEixIOgPTLh4KZ5fSOVucxLDX8P1OBB47kGBFUBpr0u4rpgkRa1pwKwP AcIiBhPbH9jM+A0VOs4X96j4vz55KJcmuWt5d8UDHZu4+QUs1HcnYHPE4KJ4SsdlSaUO RXeJo4kGi8VbbQeAgP2LCGO7nGlMcpkNEywDOLHcsNLWOQfJYUU2zx7b8MW78m+lVjd7 UDsg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:subject:to:cc:references:from:message-id:date :user-agent:mime-version:in-reply-to:content-language :content-transfer-encoding; bh=4I97tvfKMitrkdF5Fr4FiNCpy5zuXp19tZu9yklSAnE=; b=WGqJ5SBA9vwwJJnxhXwFj80kmX4hZQ40A1iGcYV7u+zgbQX6qDiL5IoRZJITps1qLO EbvzEutqJe/CEs0jIk25Ph3eOjxm8c/lLaZMKzZR+7yeliZJJHJCW631TvWp8mfKDE4s wl5n/CaQOG/NKTAKEyWPH4zAS7kfvM/wctKKqxMh/QLuEESizVv90aehIUxfcUC92lS6 waNXnga0H0/SwW8GSkMky0KzhBvkAdqUbGmeL3ZuZXWa6dlLE5RKknva69nGwzPFmg22 //i91N/lIZJ94sEhXadLJh3KRBUCOtiR51byHyIVC3evrJw87v3K8O4vCRhKpPUP86yE FiBA== X-Gm-Message-State: APjAAAVlQpCtPmj0nPhqK0Grrf4AL4CEuLIii2+e2WMKe/+MhHhC46zD t33yqS4Av1wiFuJdUsT8JBaCSA== X-Google-Smtp-Source: APXvYqxxo1ASiEzsNJ9CH27e7rE/AOGr3L8o63vdY9YD+vKSoO5S2to2ES5hdun0/P2lgx5GjCpGeQ== X-Received: by 2002:a17:90a:e4f:: with SMTP id p15mr10084854pja.90.1576161401735; Thu, 12 Dec 2019 06:36:41 -0800 (PST) Received: from [192.168.1.11] (97-113-7-119.tukw.qwest.net. [97.113.7.119]) by smtp.gmail.com with ESMTPSA id k6sm7329224pfi.119.2019.12.12.06.36.40 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 12 Dec 2019 06:36:41 -0800 (PST) Subject: Re: [PATCH v2] target/arm: ensure we use current exception state after SCR update To: =?UTF-8?Q?Alex_Benn=c3=a9e?= , qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= , Peter Maydell References: <20191212114734.6962-1-alex.bennee@linaro.org> From: Richard Henderson Message-ID: Date: Thu, 12 Dec 2019 06:36:39 -0800 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.2.1 MIME-Version: 1.0 In-Reply-To: <20191212114734.6962-1-alex.bennee@linaro.org> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 8bit X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::642 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 12 Dec 2019 14:36:45 -0000 On 12/12/19 3:47 AM, Alex Bennée wrote: > A write to the SCR can change the effective EL by droppping the system > from secure to non-secure mode. However if we use a cached current_el > from before the change we'll rebuild the flags incorrectly. To fix > this we introduce the ARM_CP_NEWEL CP flag to indicate the new EL > should be used when recomputing the flags. > > Signed-off-by: Alex Bennée > Tested-by: Philippe Mathieu-Daudé > Cc: Richard Henderson > Message-Id: <20191209143723.6368-1-alex.bennee@linaro.org> > > --- > v2 > - don't override a ARM_CP_SPECIAL, use a new flag > --- > target/arm/cpu.h | 8 ++++++-- > target/arm/helper.h | 1 + > target/arm/helper.c | 14 +++++++++++++- > target/arm/translate.c | 6 +++++- > 4 files changed, 25 insertions(+), 4 deletions(-) Reviewed-by: Richard Henderson > if (arm_dc_feature(s, ARM_FEATURE_M)) { > gen_helper_rebuild_hflags_m32(cpu_env, tcg_el); > } else { > - gen_helper_rebuild_hflags_a32(cpu_env, tcg_el); > + if (ri->type & ARM_CP_NEWEL) { > + gen_helper_rebuild_hflags_a32_newel(cpu_env); > + } else { > + gen_helper_rebuild_hflags_a32(cpu_env, tcg_el); > + } > } If you tweak this again, an else if would be appropriate. r~ From MAILER-DAEMON Thu Dec 12 10:06:10 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1ifQ2c-0008Hz-Ad for mharc-qemu-arm@gnu.org; Thu, 12 Dec 2019 10:06:10 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:47414) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ifQ2Y-0008DM-R8 for qemu-arm@nongnu.org; Thu, 12 Dec 2019 10:06:08 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ifQ2W-0006w0-EH for qemu-arm@nongnu.org; Thu, 12 Dec 2019 10:06:06 -0500 Received: from us-smtp-1.mimecast.com ([205.139.110.61]:42233) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1ifQ2W-0006tX-7N for qemu-arm@nongnu.org; Thu, 12 Dec 2019 10:06:04 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1576163163; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=tRvGMRJef+LneyeTXCaAFtX1/0kP21CjuhwNYky3o8M=; b=isNuc9B0LYqeMl6AbyPrKiqtdoADOldi+YZwINpM0qRoDoyN3PRfNLS0NsYQvtGmBRJ6I+ pHf9kvea5HMGpB/WcUb7eN1DL/FK1tZLcMi6EDwVFgbHF4KMymQ+IAYX6TknhcjVdAGEi9 RqQfHt7sie/BhDZwG295id8nU0HAO50= Received: from mimecast-mx01.redhat.com (mimecast-mx01.redhat.com [209.132.183.4]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-2-xhfBSYRdOJO6i7ePqdObcg-1; Thu, 12 Dec 2019 10:05:45 -0500 Received: from smtp.corp.redhat.com (int-mx07.intmail.prod.int.phx2.redhat.com [10.5.11.22]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx01.redhat.com (Postfix) with ESMTPS id 6E9F3DBC8; Thu, 12 Dec 2019 15:05:43 +0000 (UTC) Received: from [10.36.116.117] (ovpn-116-117.ams2.redhat.com [10.36.116.117]) by smtp.corp.redhat.com (Postfix) with ESMTPS id C01B810013A1; Thu, 12 Dec 2019 15:05:35 +0000 (UTC) Subject: Re: [PATCH for-5.0 v11 00/20] VIRTIO-IOMMU device To: "Michael S. Tsirkin" Cc: yang.zhong@intel.com, peter.maydell@linaro.org, kevin.tian@intel.com, tnowicki@marvell.com, quintela@redhat.com, jean-philippe.brucker@arm.com, qemu-devel@nongnu.org, peterx@redhat.com, armbru@redhat.com, bharatb.linux@gmail.com, qemu-arm@nongnu.org, dgilbert@redhat.com, eric.auger.pro@gmail.com References: <20191122182943.4656-1-eric.auger@redhat.com> <20191211113936-mutt-send-email-mst@kernel.org> <306e4e92-4e86-7a82-3777-fd85ffd0303c@redhat.com> <20191211154027-mutt-send-email-mst@kernel.org> From: Auger Eric Message-ID: Date: Thu, 12 Dec 2019 16:05:34 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101 Thunderbird/60.4.0 MIME-Version: 1.0 In-Reply-To: <20191211154027-mutt-send-email-mst@kernel.org> Content-Language: en-US X-Scanned-By: MIMEDefang 2.84 on 10.5.11.22 X-MC-Unique: xhfBSYRdOJO6i7ePqdObcg-1 X-Mimecast-Spam-Score: 0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: 7bit X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 205.139.110.61 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 12 Dec 2019 15:06:08 -0000 Hi Michael, On 12/11/19 9:40 PM, Michael S. Tsirkin wrote: > On Wed, Dec 11, 2019 at 05:48:05PM +0100, Auger Eric wrote: >> Hi Michael, >> >> On 12/11/19 5:40 PM, Michael S. Tsirkin wrote: >>> On Fri, Nov 22, 2019 at 07:29:23PM +0100, Eric Auger wrote: >>>> This series implements the QEMU virtio-iommu device. >>>> >>>> This matches the v0.12 spec and the corresponding virtio-iommu >>>> driver upstreamed in 5.3. >>>> >>>> The pci proxy for the virtio-iommu device is instantiated using >>>> "-device virtio-iommu-pci". This series still relies on ACPI IORT/DT >>>> integration. Note the ACPI IORT integration is not yet upstreamed >>>> and testing needs to be based on Jean-Philippe's additional >>>> kernel patches [1]. >>> >>> Or the config space approach? I really liked that one. >> Yes this corresponds to the paragraph below. >>> >>>> >>>> Work is ongoing to remove IORT adherence and allow the >>>> bindings between the IOMMU and the root complex to be defined >>>> and written into the PCI device configuration space. The outcome >>>> of this work is uncertain at this stage though. See [2]. > > Oh right. Why is it uncertain? Anything can be done to help? Jean's series was sent on the same day as this QEMU respin. My understanding is we still need a way to handle platform devices. Also the binding info layout needs to be revised and integrated into the spec + voted. Those are the uncertainties I wanted to point out. Thanks Eric > >> Thanks >> >> Eric >> >>>> >>>> So only patches 1-11 fully rely on upstreamed kernel code. Others >>>> should be considered as RFC. >>>> >>>> This respin allows people to test on ARM and x86. It also >>>> brings migration support (tested on ARM) and various cleanups. >>>> Reserved regions are now passed through an array of properties. >>>> A libqos test also is introduced to test the virtio-iommu API. >>>> >>>> Note integration with vhost devices and vfio devices is not part >>>> of this series. Please follow Bharat's respins [3]. >>>> >>>> The 1st Patch ("migration: Support QLIST migration") was sent >>>> separately [4]. >>>> >>>> Best Regards >>>> >>>> Eric >>>> >>>> This series can be found at: >>>> https://github.com/eauger/qemu/tree/v4.2-rc2-virtio-iommu-v11 >>>> >>>> [1] kernel branch to be used for guest >>>> https://github.com/eauger/linux/tree/v5.4-rc8-virtio-iommu-iort >>>> [2] [RFC 00/13] virtio-iommu on non-devicetree platforms >>>> [3] VFIO/VHOST integration is not part of this series. Please follow >>>> [PATCH RFC v5 0/5] virtio-iommu: VFIO integration respins >>>> [4] [PATCH v6] migration: Support QLIST migration >>>> >>>> Testing: >>>> - tested with guest using virtio-net-pci >>>> (,vhost=off,iommu_platform,disable-modern=off,disable-legacy=on) >>>> and virtio-blk-pci >>>> - migration on ARM >>>> - on x86 PC machine I get some AHCI non translated transactions, >>>> very early. This does not prevent the guest from boot and behaving >>>> properly. Warnings look like: >>>> qemu-system-x86_64: virtio_iommu_translate sid=250 is not known!! >>>> qemu-system-x86_64: no buffer available in event queue to report event >>>> qemu-system-x86_64: AHCI: Failed to start FIS receive engine: bad FIS >>>> receive buffer address >>>> >>>> History: >>>> >>>> v10 -> v11: >>>> - introduce virtio_iommu_handle_req macro >>>> - migration support >>>> - introduce DEFINE_PROP_INTERVAL and pass reserved regions >>>> through an array of those >>>> - domain gtree simplification >>>> >>>> v9 -> v10: >>>> - rebase on 4.1.0-rc2, compliance with 0.12 spec >>>> - removed ACPI part >>>> - cleanup (see individual change logs) >>>> - moved to a PATCH series >>>> >>>> v8 -> v9: >>>> - virtio-iommu-pci device needs to be instantiated from the command >>>> line (RID is not imposed anymore). >>>> - tail structure properly initialized >>>> >>>> v7 -> v8: >>>> - virtio-iommu-pci added >>>> - virt instantiation modified >>>> - DT and ACPI modified to exclude the iommu RID from the mapping >>>> - VIRTIO_IOMMU_F_BYPASS, VIRTIO_F_VERSION_1 features exposed >>>> >>>> v6 -> v7: >>>> - rebase on qemu 3.0.0-rc3 >>>> - minor update against v0.7 >>>> - fix issue with EP not on pci.0 and ACPI probing >>>> - change the instantiation method >>>> >>>> v5 -> v6: >>>> - minor update against v0.6 spec >>>> - fix g_hash_table_lookup in virtio_iommu_find_add_as >>>> - replace some error_reports by qemu_log_mask(LOG_GUEST_ERROR, ...) >>>> >>>> v4 -> v5: >>>> - event queue and fault reporting >>>> - we now return the IOAPIC MSI region if the virtio-iommu is instantiated >>>> in a PC machine. >>>> - we bypass transactions on MSI HW region and fault on reserved ones. >>>> - We support ACPI boot with mach-virt (based on IORT proposal) >>>> - We moved to the new driver naming conventions >>>> - simplified mach-virt instantiation >>>> - worked around the disappearing of pci_find_primary_bus >>>> - in virtio_iommu_translate, check the dev->as is not NULL >>>> - initialize as->device_list in virtio_iommu_get_as >>>> - initialize bufstate.error to false in virtio_iommu_probe >>>> >>>> v3 -> v4: >>>> - probe request support although no reserved region is returned at >>>> the moment >>>> - unmap semantics less strict, as specified in v0.4 >>>> - device registration, attach/detach revisited >>>> - split into smaller patches to ease review >>>> - propose a way to inform the IOMMU mr about the page_size_mask >>>> of underlying HW IOMMU, if any >>>> - remove warning associated with the translation of the MSI doorbell >>>> >>>> v2 -> v3: >>>> - rebase on top of 2.10-rc0 and especially >>>> [PATCH qemu v9 0/2] memory/iommu: QOM'fy IOMMU MemoryRegion >>>> - add mutex init >>>> - fix as->mappings deletion using g_tree_ref/unref >>>> - when a dev is attached whereas it is already attached to >>>> another address space, first detach it >>>> - fix some error values >>>> - page_sizes = TARGET_PAGE_MASK; >>>> - I haven't changed the unmap() semantics yet, waiting for the >>>> next virtio-iommu spec revision. >>>> >>>> v1 -> v2: >>>> - fix redefinition of viommu_as typedef >>>> >>>> >>>> >>>> Eric Auger (20): >>>> migration: Support QLIST migration >>>> virtio-iommu: Add skeleton >>>> virtio-iommu: Decode the command payload >>>> virtio-iommu: Add the iommu regions >>>> virtio-iommu: Endpoint and domains structs and helpers >>>> virtio-iommu: Implement attach/detach command >>>> virtio-iommu: Implement map/unmap >>>> virtio-iommu: Implement translate >>>> virtio-iommu: Implement fault reporting >>>> virtio-iommu-pci: Add virtio iommu pci support >>>> hw/arm/virt: Add the virtio-iommu device tree mappings >>>> qapi: Introduce DEFINE_PROP_INTERVAL >>>> virtio-iommu: Implement probe request >>>> virtio-iommu: Handle reserved regions in the translation process >>>> virtio-iommu-pci: Add array of Interval properties >>>> hw/arm/virt-acpi-build: Introduce fill_iort_idmap helper >>>> hw/arm/virt-acpi-build: Add virtio-iommu node in IORT table >>>> virtio-iommu: Support migration >>>> pc: Add support for virtio-iommu-pci >>>> tests: Add virtio-iommu test >>>> >>>> hw/arm/virt-acpi-build.c | 91 ++- >>>> hw/arm/virt.c | 53 +- >>>> hw/core/qdev-properties.c | 90 +++ >>>> hw/i386/acpi-build.c | 72 +++ >>>> hw/i386/pc.c | 15 +- >>>> hw/virtio/Kconfig | 5 + >>>> hw/virtio/Makefile.objs | 2 + >>>> hw/virtio/trace-events | 22 + >>>> hw/virtio/virtio-iommu-pci.c | 91 +++ >>>> hw/virtio/virtio-iommu.c | 952 +++++++++++++++++++++++++++++++ >>>> include/exec/memory.h | 6 + >>>> include/hw/acpi/acpi-defs.h | 21 +- >>>> include/hw/arm/virt.h | 2 + >>>> include/hw/i386/pc.h | 2 + >>>> include/hw/pci/pci.h | 1 + >>>> include/hw/qdev-properties.h | 3 + >>>> include/hw/virtio/virtio-iommu.h | 67 +++ >>>> include/migration/vmstate.h | 21 + >>>> include/qemu/queue.h | 39 ++ >>>> include/qemu/typedefs.h | 1 + >>>> migration/trace-events | 5 + >>>> migration/vmstate-types.c | 70 +++ >>>> qdev-monitor.c | 1 + >>>> tests/Makefile.include | 2 + >>>> tests/libqos/virtio-iommu.c | 177 ++++++ >>>> tests/libqos/virtio-iommu.h | 45 ++ >>>> tests/test-vmstate.c | 170 ++++++ >>>> tests/virtio-iommu-test.c | 261 +++++++++ >>>> 28 files changed, 2253 insertions(+), 34 deletions(-) >>>> create mode 100644 hw/virtio/virtio-iommu-pci.c >>>> create mode 100644 hw/virtio/virtio-iommu.c >>>> create mode 100644 include/hw/virtio/virtio-iommu.h >>>> create mode 100644 tests/libqos/virtio-iommu.c >>>> create mode 100644 tests/libqos/virtio-iommu.h >>>> create mode 100644 tests/virtio-iommu-test.c >>>> >>>> -- >>>> 2.20.1 >>> >>> > > From MAILER-DAEMON Thu Dec 12 10:13:26 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1ifQ9e-0001sz-OJ for mharc-qemu-arm@gnu.org; Thu, 12 Dec 2019 10:13:26 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:48692) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ifQ9b-0001sW-PN for qemu-arm@nongnu.org; Thu, 12 Dec 2019 10:13:25 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ifQ9Z-0001zV-J2 for qemu-arm@nongnu.org; Thu, 12 Dec 2019 10:13:23 -0500 Received: from us-smtp-2.mimecast.com ([205.139.110.61]:39868 helo=us-smtp-delivery-1.mimecast.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1ifQ9Z-0001wu-Bk for qemu-arm@nongnu.org; Thu, 12 Dec 2019 10:13:21 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1576163600; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=N4fGbcXqbsKwRu/bOJBiDOmHdAb7I+sxr97ThhtjbYs=; b=g2+Q7E4u3YOcWXx6wmkvSSrXmGz6VJyofQkGO2wJvEi773ci/YUnw116aZ7oXBjX8gs5RG UIsnwvlkYnIpUHE73+6r7gRUtD3A6iIwo4FuTlgVk8sZac6t8PKofJ2o49cSiXHrt4qBHE VT4UxJdYeIis2TEpp+h7OPlNsGGtcW0= Received: from mimecast-mx01.redhat.com (mimecast-mx01.redhat.com [209.132.183.4]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-144-DU9iWiCGMEatQzC071nuYg-1; Thu, 12 Dec 2019 10:13:19 -0500 Received: from smtp.corp.redhat.com (int-mx03.intmail.prod.int.phx2.redhat.com [10.5.11.13]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx01.redhat.com (Postfix) with ESMTPS id 73249800D41; Thu, 12 Dec 2019 15:13:17 +0000 (UTC) Received: from [10.36.116.117] (ovpn-116-117.ams2.redhat.com [10.36.116.117]) by smtp.corp.redhat.com (Postfix) with ESMTPS id 5847A67E46; Thu, 12 Dec 2019 15:13:08 +0000 (UTC) Subject: Re: [PATCH for-5.0 v11 12/20] qapi: Introduce DEFINE_PROP_INTERVAL To: Markus Armbruster Cc: yang.zhong@intel.com, peter.maydell@linaro.org, kevin.tian@intel.com, tnowicki@marvell.com, mst@redhat.com, jean-philippe.brucker@arm.com, quintela@redhat.com, qemu-devel@nongnu.org, peterx@redhat.com, bharatb.linux@gmail.com, qemu-arm@nongnu.org, dgilbert@redhat.com, eric.auger.pro@gmail.com References: <20191122182943.4656-1-eric.auger@redhat.com> <20191122182943.4656-13-eric.auger@redhat.com> <87wob17n6j.fsf@dusky.pond.sub.org> From: Auger Eric Message-ID: <66ae0999-bdd8-6b54-f550-f036dafc982b@redhat.com> Date: Thu, 12 Dec 2019 16:13:06 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101 Thunderbird/60.4.0 MIME-Version: 1.0 In-Reply-To: <87wob17n6j.fsf@dusky.pond.sub.org> Content-Language: en-US X-Scanned-By: MIMEDefang 2.79 on 10.5.11.13 X-MC-Unique: DU9iWiCGMEatQzC071nuYg-1 X-Mimecast-Spam-Score: 0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: 7bit X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 205.139.110.61 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 12 Dec 2019 15:13:25 -0000 Hi Markus, On 12/12/19 1:17 PM, Markus Armbruster wrote: > Eric Auger writes: > >> Introduce a new property defining a labelled interval: >> ,,label. >> >> This will be used to encode reserved IOVA regions. The label >> is left undefined to ease reuse accross use cases. > > What does the last sentence mean? The dilemma was shall I specialize this property such as ReservedRegion or shall I leave it generic enough to serve somebody else use case. I first chose the latter but now I think I should rather call it something like ReservedRegion as in any case it has addresses and an integer label. > >> For instance, in virtio-iommu use case, reserved IOVA regions >> will be passed by the machine code to the virtio-iommu-pci >> device (an array of those). The label will match the >> virtio_iommu_probe_resv_mem subtype value: >> - VIRTIO_IOMMU_RESV_MEM_T_RESERVED (0) >> - VIRTIO_IOMMU_RESV_MEM_T_MSI (1) >> >> This is used to inform the virtio-iommu-pci device it should >> bypass the MSI region: 0xfee00000, 0xfeefffff, 1. > > So the "label" part of ",,label" is a number? yes it is. > > Is a number appropriate for your use case, or would an enum be better? I think a number is OK. There might be other types of reserved regions in the future. Also if we want to allow somebody else to reuse that property in another context, I would rather leave it open? > >> >> Signed-off-by: Eric Auger --- >> hw/core/qdev-properties.c | 90 ++++++++++++++++++++++++++++++++++++ >> include/exec/memory.h | 6 +++ include/hw/qdev-properties.h | 3 ++ >> include/qemu/typedefs.h | 1 + 4 files changed, 100 insertions(+) > > Subject has 'qapi:', but it's actually about qdev. Please adjust the subject. OK > >> diff --git a/hw/core/qdev-properties.c b/hw/core/qdev-properties.c >> index ac28890e5a..8d70f34e37 100644 >> --- a/hw/core/qdev-properties.c >> +++ b/hw/core/qdev-properties.c >> @@ -13,6 +13,7 @@ >> #include "qapi/visitor.h" >> #include "chardev/char.h" >> #include "qemu/uuid.h" >> +#include "qemu/cutils.h" >> >> void qdev_prop_set_after_realize(DeviceState *dev, const char *name, >> Error **errp) >> @@ -585,6 +586,95 @@ const PropertyInfo qdev_prop_macaddr = { >> .set = set_mac, >> }; >> >> +/* --- Labelled Interval --- */ >> + >> +/* >> + * accepted syntax versions: > > "versions"? s/versions/version > >> + * ,, >> + * where low/high addresses are uint64_t in hexa (feat. 0x prefix) > > "hexa" is not a word. OK > > I'm afraid I don't get the parenthesis. I wanted to mention the 0x prefix was needed but as you mentionned below it is not needed actually. > >> + * and type is an unsigned integer >> + */ >> +static void get_interval(Object *obj, Visitor *v, const char *name, >> + void *opaque, Error **errp) >> +{ >> + DeviceState *dev = DEVICE(obj); >> + Property *prop = opaque; >> + Interval *interval = qdev_get_prop_ptr(dev, prop); >> + char buffer[64]; >> + char *p = buffer; >> + >> + Snprintf(buffer, sizeof(buffer), "0x%"PRIx64",0x%"PRIx64",%d", >> + interval->low, interval->high, interval->type); > > interval->type is unsigned. Use %u, not %d. OK > >> + >> + visit_type_str(v, name, &p, errp); >> +} >> + >> +static void set_interval(Object *obj, Visitor *v, const char *name, >> + void *opaque, Error **errp) >> +{ >> + DeviceState *dev = DEVICE(obj); >> + Property *prop = opaque; >> + Interval *interval = qdev_get_prop_ptr(dev, prop); >> + Error *local_err = NULL; >> + unsigned int type; >> + gchar **fields; >> + uint64_t addr; >> + char *str; >> + int ret; >> + >> + if (dev->realized) { >> + qdev_prop_set_after_realize(dev, name, errp); >> + return; >> + } >> + >> + visit_type_str(v, name, &str, &local_err); >> + if (local_err) { >> + error_propagate(errp, local_err); >> + return; >> + } >> + >> + fields = g_strsplit(str, ",", 3); >> + >> + ret = qemu_strtou64(fields[0], NULL, 16, &addr); > > Aha, the 0x prefix is actually optional. > >> + if (!ret) { >> + interval->low = addr; >> + } else { >> + error_setg(errp, "Failed to decode interval low addr"); >> + error_append_hint(errp, >> + "should be an address in hexa with 0x prefix\n"); > > "hexa" is not a word, and the 0x prefix is actually optional. OK > >> + goto out; >> + } > > I prefer > > if (error) { > handle error > bail out > } > handle success > > over > > if (success) { > handle success > if (error) { > handle error > bail out > } > > In this case: > > if (ret) { > error_setg(errp, "Failed to decode interval low addr"); > error_append_hint(errp, > "should be an address in hexa with 0x prefix\n"); > goto out; > } > interval->low = addr; OK > > >> + >> + ret = qemu_strtou64(fields[1], NULL, 16, &addr); > > Crash if @str doesn't contain ',', because the g_strsplit(str, ",", 3) > yields { [0] = str, NULL }. > >> + if (!ret) { >> + interval->high = addr; >> + } else { >> + error_setg(errp, "Failed to decode interval high addr"); >> + error_append_hint(errp, >> + "should be an address in hexa with 0x prefix\n"); >> + goto out; >> + } >> + >> + ret = qemu_strtoui(fields[2], NULL, 10, &type); > > Likewise, crash if @str contains only one ','. > > I wouldn't use g_strsplit() here. After > > ret = qemu_strtoui(str, &endptr, 16, &interval->low); > > @endptr points behind the address. So: > > if (ret || *endptr != ',') { > handle error ... > goto out > } > > ret = qemu_strtoui(endptr + 1, &endptr, 16, &interval->high); > > and so forth. > > Note that the if (ret || *endptr != ',') checks for two distinct errors. > Distinct error messages might be more helpful. OK I will revisit that. > >> + if (!ret) { >> + interval->type = type; >> + } else { >> + error_setg(errp, "Failed to decode interval type"); >> + error_append_hint(errp, "should be an unsigned int in decimal\n"); >> + } >> +out: >> + g_free(str); >> + g_strfreev(fields); >> + return; >> +} >> + >> +const PropertyInfo qdev_prop_interval = { >> + .name = "labelled_interval", >> + .description = "Labelled interval, example: 0xFEE00000,0xFEEFFFFF,0", >> + .get = get_interval, >> + .set = set_interval, >> +}; >> + >> /* --- on/off/auto --- */ >> >> const PropertyInfo qdev_prop_on_off_auto = { >> diff --git a/include/exec/memory.h b/include/exec/memory.h >> index e499dc215b..e238d1c352 100644 >> --- a/include/exec/memory.h >> +++ b/include/exec/memory.h >> @@ -57,6 +57,12 @@ struct MemoryRegionMmio { >> CPUWriteMemoryFunc *write[3]; >> }; >> >> +struct Interval { >> + hwaddr low; >> + hwaddr high; >> + unsigned int type; >> +}; > > This isn't an interval. An interval consists of two values, not three. > > The third one is called "type" here, and "label" elsewhere. Pick one > and stick to it. > > Then pick a name for the triple. Elsewhere, you call it "labelled > interval". I would tend to use ReservedRegion now if nobody objects. Thank you for the review! Eric > >> + >> typedef struct IOMMUTLBEntry IOMMUTLBEntry; >> >> /* See address_space_translate: bit 0 is read, bit 1 is write. */ >> diff --git a/include/hw/qdev-properties.h b/include/hw/qdev-properties.h >> index c6a8cb5516..2ba7c8711b 100644 >> --- a/include/hw/qdev-properties.h >> +++ b/include/hw/qdev-properties.h >> @@ -20,6 +20,7 @@ extern const PropertyInfo qdev_prop_chr; >> extern const PropertyInfo qdev_prop_tpm; >> extern const PropertyInfo qdev_prop_ptr; >> extern const PropertyInfo qdev_prop_macaddr; >> +extern const PropertyInfo qdev_prop_interval; >> extern const PropertyInfo qdev_prop_on_off_auto; >> extern const PropertyInfo qdev_prop_losttickpolicy; >> extern const PropertyInfo qdev_prop_blockdev_on_error; >> @@ -202,6 +203,8 @@ extern const PropertyInfo qdev_prop_pcie_link_width; >> DEFINE_PROP(_n, _s, _f, qdev_prop_drive_iothread, BlockBackend *) >> #define DEFINE_PROP_MACADDR(_n, _s, _f) \ >> DEFINE_PROP(_n, _s, _f, qdev_prop_macaddr, MACAddr) >> +#define DEFINE_PROP_INTERVAL(_n, _s, _f) \ >> + DEFINE_PROP(_n, _s, _f, qdev_prop_interval, Interval) >> #define DEFINE_PROP_ON_OFF_AUTO(_n, _s, _f, _d) \ >> DEFINE_PROP_SIGNED(_n, _s, _f, _d, qdev_prop_on_off_auto, OnOffAuto) >> #define DEFINE_PROP_LOSTTICKPOLICY(_n, _s, _f, _d) \ >> diff --git a/include/qemu/typedefs.h b/include/qemu/typedefs.h >> index 375770a80f..a827c9a3fe 100644 >> --- a/include/qemu/typedefs.h >> +++ b/include/qemu/typedefs.h >> @@ -58,6 +58,7 @@ typedef struct ISABus ISABus; >> typedef struct ISADevice ISADevice; >> typedef struct IsaDma IsaDma; >> typedef struct MACAddr MACAddr; >> +typedef struct Interval Interval; >> typedef struct MachineClass MachineClass; >> typedef struct MachineState MachineState; >> typedef struct MemoryListener MemoryListener; > > From MAILER-DAEMON Thu Dec 12 12:33:42 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1ifSLO-0002Gm-HB for mharc-qemu-arm@gnu.org; Thu, 12 Dec 2019 12:33:42 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:43821) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ifSLH-0002Dt-8m for qemu-arm@nongnu.org; Thu, 12 Dec 2019 12:33:37 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ifSLE-0002fC-3u for qemu-arm@nongnu.org; Thu, 12 Dec 2019 12:33:33 -0500 Received: from us-smtp-2.mimecast.com ([207.211.31.81]:45979 helo=us-smtp-delivery-1.mimecast.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1ifSLD-0002aO-R0 for qemu-arm@nongnu.org; Thu, 12 Dec 2019 12:33:32 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1576172009; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding; bh=2EL/bGHWUdBeUlnl5qW+9PCRIIH7sgKnghtEX7B2zvU=; b=hgtC4VrAgyegygxbMgiq/u7L+qvcVIa/UMD0fStmZAG3cxynJznFoCVUltacpQJiuRyrIp QsHlidasPYoA1FwOLtYX9FodhBmYB83lFq6cxbqtYJanMYFBIMjn1qA7bQSl4xKOL+pP7m ioU/frM2UXrDAM9OEVYavjAk1zxZxOk= Received: from mimecast-mx01.redhat.com (mimecast-mx01.redhat.com [209.132.183.4]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-111-ATM9rdhPN16XJQ892c8U_g-1; Thu, 12 Dec 2019 12:33:26 -0500 Received: from smtp.corp.redhat.com (int-mx08.intmail.prod.int.phx2.redhat.com [10.5.11.23]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx01.redhat.com (Postfix) with ESMTPS id 92E02800D41; Thu, 12 Dec 2019 17:33:24 +0000 (UTC) Received: from kamzik.brq.redhat.com (unknown [10.43.2.160]) by smtp.corp.redhat.com (Postfix) with ESMTP id AA78319C4F; Thu, 12 Dec 2019 17:33:21 +0000 (UTC) From: Andrew Jones To: qemu-devel@nongnu.org, qemu-arm@nongnu.org Cc: richard.henderson@linaro.org, peter.maydell@linaro.org, guoheyi@huawei.com, bijan.mottahedeh@oracle.com, maz@kernel.org, msys.mizuma@gmail.com Subject: [RFC PATCH v2 0/5] target/arm/kvm: Adjust virtual time Date: Thu, 12 Dec 2019 18:33:15 +0100 Message-Id: <20191212173320.11610-1-drjones@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.84 on 10.5.11.23 X-MC-Unique: ATM9rdhPN16XJQ892c8U_g-1 X-Mimecast-Spam-Score: 0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 207.211.31.81 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 12 Dec 2019 17:33:37 -0000 v2: - Reworked it enough that I brought back the RFC tag and retitled the series. Also had to drop r-b's from a couple of patches, and even drop patches. - Changed approach from writing the QEMU virtual time to the guest vtime counter to saving and restoring the guest vtime counter. - Changed the kvm-adjvtime property, which was off by default, to a kvm-no-adjvtime property, which is also off by default, meaning the effective "adjust vtime" property is now on by default (but only for 5.0 virt machine types and later) v1: - move from RFC status to v1 - put kvm_arm_vm_state_change() in kvm.c to share among kvm32.c and kvm64.= c - add r-b's from Richard This series is inspired by a series[1] posted by Bijan Mottahedeh over a year ago and by the patch[2] posted by Heyi Guo almost a year ago. The problem described in the cover letter of [1] is easily reproducible and some users would like to have the option to avoid it. However the solution, which is to adjust the virtual counter each time the VM transitions to the running state, introduces a different problem, which is that the virtual and physical counters diverge. As described in the cover letter of [1] this divergence is easily observed when comparing the output of `date` and `hwclock` after suspending the guest, waiting a while, and then resuming it. Because this different problem may actually be worse for some users, unlike [1], the series posted here makes the virtual counter adjustment optional. Besides the adjustment being optional, this series approaches the needed changes differently to apply them in more appropriate locations and also integrates some of the approach posted in [2]. Additional notes ---------------- Note 1 ------ As described above, when running a guest with kvm-no-adjtime disabled it will be less likely the guest OS and guest applications get surprise time jumps when they use the virtual counter. However the counter will no longer reflect real time. It will lag behind. If this is a problem then the guest can resynchronize its time from an external source or even from its physical counter. If the suspend/resume is done with libvirt's virsh, and the guest is running the guest agent, then it's also possible to use a sequence like this $ virsh suspend $GUEST $ virsh resume $GUEST $ virsh domtime --sync $GUEST in order to resynchronize a guest right after the resume. Of course there will still be time when the clock is not right, possibly creating confusing timestamps in logs, for example, and the guest must still be tolerant to the time synchronizations. Note 2 ------ Userspace that wants to set KVM_REG_ARM_TIMER_CNT should beware that the KVM register ID is not correct. This cannot be fixed because it's UAPI and if the UAPI headers are used then it can't be a problem. However, if a userspace attempts to create the ID themselves from the register's specification, then they will get KVM_REG_ARM_TIMER_CVAL instead, as the _CNT and _CVAL definitions have their register parameters swapped. Note 3 ------ I didn't test this with a 32-bit KVM host, but the changes to kvm32.c are the same as kvm64.c. So what could go wrong? Test results would be appreciated. =20 [1] https://lists.gnu.org/archive/html/qemu-devel/2018-11/msg05713.html [2] https://lists.gnu.org/archive/html/qemu-devel/2019-03/msg03695.html Thanks, drew Andrew Jones (5): hw: add compat machines for 5.0 target/arm/kvm64: kvm64 cpus have timer registers target/arm/kvm: Implement virtual time adjustment tests/arm-cpu-features: Check feature default values target/arm/cpu: Add the kvm-no-adjvtime CPU property docs/arm-cpu-features.rst | 31 +++++++++++++++- hw/arm/virt.c | 17 ++++++++- hw/core/machine.c | 3 ++ hw/i386/pc.c | 3 ++ hw/i386/pc_piix.c | 14 ++++++- hw/i386/pc_q35.c | 13 ++++++- hw/ppc/spapr.c | 15 +++++++- hw/s390x/s390-virtio-ccw.c | 15 +++++++- include/hw/arm/virt.h | 1 + include/hw/boards.h | 3 ++ include/hw/i386/pc.h | 3 ++ target/arm/cpu.c | 2 + target/arm/cpu.h | 9 +++++ target/arm/cpu64.c | 1 + target/arm/kvm.c | 76 ++++++++++++++++++++++++++++++++++++++ target/arm/kvm32.c | 3 ++ target/arm/kvm64.c | 4 ++ target/arm/kvm_arm.h | 34 +++++++++++++++++ target/arm/monitor.c | 1 + tests/arm-cpu-features.c | 48 +++++++++++++++++++----- 20 files changed, 280 insertions(+), 16 deletions(-) --=20 2.21.0 From MAILER-DAEMON Thu Dec 12 12:33:50 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1ifSLW-0002QR-5Q for mharc-qemu-arm@gnu.org; Thu, 12 Dec 2019 12:33:50 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:45326) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ifSLQ-0002Jm-VE for qemu-arm@nongnu.org; Thu, 12 Dec 2019 12:33:47 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ifSLO-0002vv-Rs for qemu-arm@nongnu.org; Thu, 12 Dec 2019 12:33:44 -0500 Received: from us-smtp-delivery-1.mimecast.com ([205.139.110.120]:25152 helo=us-smtp-1.mimecast.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1ifSLO-0002rw-If for qemu-arm@nongnu.org; Thu, 12 Dec 2019 12:33:42 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1576172020; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=r69RStoSm0rMO8wwtIxPtrqT52+0T861lC3busDYwak=; b=Wtcl+Le6v0hhSRxyATrCtT8df+xLyJB0vS+Bnkx+nkxUKxSLjofZbTKR86yl3VMEX9Avb7 A0/7IYgTVr+aBNESmy6y0qk7vWmC2hUixEpbkuQ09TRocAPgBsB7qf3/ZBwwknaGR4Z2uH f7RtG+4MMslpRUfRi/O89xEw+nPnp/s= Received: from mimecast-mx01.redhat.com (mimecast-mx01.redhat.com [209.132.183.4]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-352-ByIa6DMzPIaUClIcA_SxXw-1; Thu, 12 Dec 2019 12:33:37 -0500 Received: from smtp.corp.redhat.com (int-mx08.intmail.prod.int.phx2.redhat.com [10.5.11.23]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx01.redhat.com (Postfix) with ESMTPS id 954F218543A1; Thu, 12 Dec 2019 17:33:35 +0000 (UTC) Received: from kamzik.brq.redhat.com (unknown [10.43.2.160]) by smtp.corp.redhat.com (Postfix) with ESMTP id C6A2419C4F; Thu, 12 Dec 2019 17:33:33 +0000 (UTC) From: Andrew Jones To: qemu-devel@nongnu.org, qemu-arm@nongnu.org Cc: richard.henderson@linaro.org, peter.maydell@linaro.org, guoheyi@huawei.com, bijan.mottahedeh@oracle.com, maz@kernel.org, msys.mizuma@gmail.com Subject: [RFC PATCH v2 2/5] target/arm/kvm64: kvm64 cpus have timer registers Date: Thu, 12 Dec 2019 18:33:17 +0100 Message-Id: <20191212173320.11610-3-drjones@redhat.com> In-Reply-To: <20191212173320.11610-1-drjones@redhat.com> References: <20191212173320.11610-1-drjones@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.84 on 10.5.11.23 X-MC-Unique: ByIa6DMzPIaUClIcA_SxXw-1 X-Mimecast-Spam-Score: 0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 205.139.110.120 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 12 Dec 2019 17:33:48 -0000 Add the missing GENERIC_TIMER feature to kvm64 cpus. We don't currently use these registers when KVM is enabled, but it's probably best we add the feature flag for consistency and potential future use. There's also precedent, as we add the PMU feature flag to KVM enabled guests, even though we don't use those registers either. This change was originally posted as a hunk of a different, never merged patch from Bijan Mottahedeh. Signed-off-by: Andrew Jones Reviewed-by: Richard Henderson --- target/arm/kvm64.c | 1 + 1 file changed, 1 insertion(+) diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c index 876184b8fe4d..5cafcb7d36dd 100644 --- a/target/arm/kvm64.c +++ b/target/arm/kvm64.c @@ -605,6 +605,7 @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *= ahcf) set_feature(&features, ARM_FEATURE_NEON); set_feature(&features, ARM_FEATURE_AARCH64); set_feature(&features, ARM_FEATURE_PMU); + set_feature(&features, ARM_FEATURE_GENERIC_TIMER); =20 ahcf->features =3D features; =20 --=20 2.21.0 From MAILER-DAEMON Thu Dec 12 12:33:50 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1ifSLW-0002R7-Oe for mharc-qemu-arm@gnu.org; Thu, 12 Dec 2019 12:33:50 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:45752) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ifSLT-0002MS-6u for qemu-arm@nongnu.org; Thu, 12 Dec 2019 12:33:48 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ifSLP-0002wq-38 for qemu-arm@nongnu.org; Thu, 12 Dec 2019 12:33:46 -0500 Received: from us-smtp-delivery-1.mimecast.com ([207.211.31.120]:47180 helo=us-smtp-1.mimecast.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1ifSLO-0002qa-KM for qemu-arm@nongnu.org; Thu, 12 Dec 2019 12:33:42 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1576172017; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=VSHnNeve0nJFno0tiuZhETFw3aDOpI+ZqpQb8S6dcfM=; b=bZQiSgGWeIN4iwLOkEn0b91z9AxeSx8xMtztKEmbHnpW2mM0nf/SUZNYFlG5v4GNFwKTGT GBbq7v2O/ugOWiIJa8rrMsd7cIM6eFE4s/cJIEDgN08/Nyj1rH+JjE2eaw9L5FD2sbJ1O8 nt0IC5yLP+WYsUlVA+RBg+gT2E3q0tw= Received: from mimecast-mx01.redhat.com (mimecast-mx01.redhat.com [209.132.183.4]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-391-7gC1GShBNBaKdNrdlOwHRQ-1; Thu, 12 Dec 2019 12:33:36 -0500 Received: from smtp.corp.redhat.com (int-mx08.intmail.prod.int.phx2.redhat.com [10.5.11.23]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx01.redhat.com (Postfix) with ESMTPS id 71FBEDB20; Thu, 12 Dec 2019 17:33:33 +0000 (UTC) Received: from kamzik.brq.redhat.com (unknown [10.43.2.160]) by smtp.corp.redhat.com (Postfix) with ESMTP id 0511C19756; Thu, 12 Dec 2019 17:33:24 +0000 (UTC) From: Andrew Jones To: qemu-devel@nongnu.org, qemu-arm@nongnu.org Cc: richard.henderson@linaro.org, peter.maydell@linaro.org, guoheyi@huawei.com, bijan.mottahedeh@oracle.com, maz@kernel.org, msys.mizuma@gmail.com, Eduardo Habkost , Marcel Apfelbaum , "Michael S. Tsirkin" , Paolo Bonzini , Richard Henderson , David Gibson , David Hildenbrand , Cornelia Huck , Halil Pasic , Christian Borntraeger , qemu-ppc@nongnu.org (open list:sPAPR), qemu-s390x@nongnu.org (open list:S390 TCG CPUs) Subject: [RFC PATCH v2 1/5] hw: add compat machines for 5.0 Date: Thu, 12 Dec 2019 18:33:16 +0100 Message-Id: <20191212173320.11610-2-drjones@redhat.com> In-Reply-To: <20191212173320.11610-1-drjones@redhat.com> References: <20191212173320.11610-1-drjones@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.84 on 10.5.11.23 X-MC-Unique: 7gC1GShBNBaKdNrdlOwHRQ-1 X-Mimecast-Spam-Score: 0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 207.211.31.120 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 12 Dec 2019 17:33:50 -0000 Add 5.0 machine types for arm/i440fx/q35/s390x/spapr. Signed-off-by: Andrew Jones --- Hi Eduardo, If we need to do something special for i440fx and q35, as 9aec2e52ce9d ("hw: add compat machines for 4.2") implies, then I'll need guidance as to what. --- hw/arm/virt.c | 9 ++++++++- hw/core/machine.c | 3 +++ hw/i386/pc.c | 3 +++ hw/i386/pc_piix.c | 14 +++++++++++++- hw/i386/pc_q35.c | 13 ++++++++++++- hw/ppc/spapr.c | 15 +++++++++++++-- hw/s390x/s390-virtio-ccw.c | 15 ++++++++++++++- include/hw/boards.h | 3 +++ include/hw/i386/pc.h | 3 +++ 9 files changed, 72 insertions(+), 6 deletions(-) diff --git a/hw/arm/virt.c b/hw/arm/virt.c index d4bedc260712..cb7041e9677a 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -2147,10 +2147,17 @@ static void machvirt_machine_init(void) } type_init(machvirt_machine_init); =20 +static void virt_machine_5_0_options(MachineClass *mc) +{ +} +DEFINE_VIRT_MACHINE_AS_LATEST(5, 0) + static void virt_machine_4_2_options(MachineClass *mc) { + virt_machine_5_0_options(mc); + compat_props_add(mc->compat_props, hw_compat_4_2, hw_compat_4_2_len); } -DEFINE_VIRT_MACHINE_AS_LATEST(4, 2) +DEFINE_VIRT_MACHINE(4, 2) =20 static void virt_machine_4_1_options(MachineClass *mc) { diff --git a/hw/core/machine.c b/hw/core/machine.c index 1689ad3bf8af..21fe2d974817 100644 --- a/hw/core/machine.c +++ b/hw/core/machine.c @@ -27,6 +27,9 @@ #include "hw/pci/pci.h" #include "hw/mem/nvdimm.h" =20 +GlobalProperty hw_compat_4_2[] =3D {}; +const size_t hw_compat_4_2_len =3D G_N_ELEMENTS(hw_compat_4_2); + GlobalProperty hw_compat_4_1[] =3D { { "virtio-pci", "x-pcie-flr-init", "off" }, }; diff --git a/hw/i386/pc.c b/hw/i386/pc.c index ac08e6360437..58867f987d88 100644 --- a/hw/i386/pc.c +++ b/hw/i386/pc.c @@ -103,6 +103,9 @@ =20 struct hpet_fw_config hpet_cfg =3D {.count =3D UINT8_MAX}; =20 +GlobalProperty pc_compat_4_2[] =3D {}; +const size_t pc_compat_4_2_len =3D G_N_ELEMENTS(pc_compat_4_2); + GlobalProperty pc_compat_4_1[] =3D {}; const size_t pc_compat_4_1_len =3D G_N_ELEMENTS(pc_compat_4_1); =20 diff --git a/hw/i386/pc_piix.c b/hw/i386/pc_piix.c index 1bd70d1abbc4..aa2c6147a7ea 100644 --- a/hw/i386/pc_piix.c +++ b/hw/i386/pc_piix.c @@ -424,7 +424,7 @@ static void pc_i440fx_machine_options(MachineClass *m) machine_class_allow_dynamic_sysbus_dev(m, TYPE_RAMFB_DEVICE); } =20 -static void pc_i440fx_4_2_machine_options(MachineClass *m) +static void pc_i440fx_5_0_machine_options(MachineClass *m) { PCMachineClass *pcmc =3D PC_MACHINE_CLASS(m); pc_i440fx_machine_options(m); @@ -433,6 +433,18 @@ static void pc_i440fx_4_2_machine_options(MachineClass= *m) pcmc->default_cpu_version =3D 1; } =20 +DEFINE_I440FX_MACHINE(v5_0, "pc-i440fx-5.0", NULL, + pc_i440fx_5_0_machine_options) + +static void pc_i440fx_4_2_machine_options(MachineClass *m) +{ + pc_i440fx_5_0_machine_options(m); + m->alias =3D NULL; + m->is_default =3D 0; + compat_props_add(m->compat_props, hw_compat_4_2, hw_compat_4_2_len); + compat_props_add(m->compat_props, pc_compat_4_2, pc_compat_4_2_len); +} + DEFINE_I440FX_MACHINE(v4_2, "pc-i440fx-4.2", NULL, pc_i440fx_4_2_machine_options); =20 diff --git a/hw/i386/pc_q35.c b/hw/i386/pc_q35.c index 385e5cffb167..ddd485d608c0 100644 --- a/hw/i386/pc_q35.c +++ b/hw/i386/pc_q35.c @@ -348,7 +348,7 @@ static void pc_q35_machine_options(MachineClass *m) m->max_cpus =3D 288; } =20 -static void pc_q35_4_2_machine_options(MachineClass *m) +static void pc_q35_5_0_machine_options(MachineClass *m) { PCMachineClass *pcmc =3D PC_MACHINE_CLASS(m); pc_q35_machine_options(m); @@ -356,6 +356,17 @@ static void pc_q35_4_2_machine_options(MachineClass *m= ) pcmc->default_cpu_version =3D 1; } =20 +DEFINE_Q35_MACHINE(v5_0, "pc-q35-5.0", NULL, + pc_q35_5_0_machine_options); + +static void pc_q35_4_2_machine_options(MachineClass *m) +{ + pc_q35_5_0_machine_options(m); + m->alias =3D NULL; + compat_props_add(m->compat_props, hw_compat_4_2, hw_compat_4_2_len); + compat_props_add(m->compat_props, pc_compat_4_2, pc_compat_4_2_len); +} + DEFINE_Q35_MACHINE(v4_2, "pc-q35-4.2", NULL, pc_q35_4_2_machine_options); =20 diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c index e076f6023c73..3ae7db156303 100644 --- a/hw/ppc/spapr.c +++ b/hw/ppc/spapr.c @@ -4491,15 +4491,26 @@ static const TypeInfo spapr_machine_info =3D { } \ type_init(spapr_machine_register_##suffix) =20 +/* + * pseries-5.0 + */ +static void spapr_machine_5_0_class_options(MachineClass *mc) +{ + /* Defaults for the latest behaviour inherited from the base class */ +} + +DEFINE_SPAPR_MACHINE(5_0, "5.0", true); + /* * pseries-4.2 */ static void spapr_machine_4_2_class_options(MachineClass *mc) { - /* Defaults for the latest behaviour inherited from the base class */ + spapr_machine_5_0_class_options(mc); + compat_props_add(mc->compat_props, hw_compat_4_2, hw_compat_4_2_len); } =20 -DEFINE_SPAPR_MACHINE(4_2, "4.2", true); +DEFINE_SPAPR_MACHINE(4_2, "4.2", false); =20 /* * pseries-4.1 diff --git a/hw/s390x/s390-virtio-ccw.c b/hw/s390x/s390-virtio-ccw.c index d3edeef0ad92..a40f79e20733 100644 --- a/hw/s390x/s390-virtio-ccw.c +++ b/hw/s390x/s390-virtio-ccw.c @@ -639,14 +639,27 @@ bool css_migration_enabled(void) } = \ type_init(ccw_machine_register_##suffix) =20 + +static void ccw_machine_5_0_instance_options(MachineState *machine) +{ +} + +static void ccw_machine_5_0_class_options(MachineClass *mc) +{ +} +DEFINE_CCW_MACHINE(5_0, "5.0", true); + static void ccw_machine_4_2_instance_options(MachineState *machine) { + ccw_machine_5_0_instance_options(machine); } =20 static void ccw_machine_4_2_class_options(MachineClass *mc) { + ccw_machine_5_0_class_options(mc); + compat_props_add(mc->compat_props, hw_compat_4_2, hw_compat_4_2_len); } -DEFINE_CCW_MACHINE(4_2, "4.2", true); +DEFINE_CCW_MACHINE(4_2, "4.2", false); =20 static void ccw_machine_4_1_instance_options(MachineState *machine) { diff --git a/include/hw/boards.h b/include/hw/boards.h index de45087f34cb..24cbeecbaecc 100644 --- a/include/hw/boards.h +++ b/include/hw/boards.h @@ -329,6 +329,9 @@ struct MachineState { } \ type_init(machine_initfn##_register_types) =20 +extern GlobalProperty hw_compat_4_2[]; +extern const size_t hw_compat_4_2_len; + extern GlobalProperty hw_compat_4_1[]; extern const size_t hw_compat_4_1_len; =20 diff --git a/include/hw/i386/pc.h b/include/hw/i386/pc.h index 1f86eba3f998..61a998de4665 100644 --- a/include/hw/i386/pc.h +++ b/include/hw/i386/pc.h @@ -237,6 +237,9 @@ void pc_system_firmware_init(PCMachineState *pcms, Memo= ryRegion *rom_memory); void pc_madt_cpu_entry(AcpiDeviceIf *adev, int uid, const CPUArchIdList *apic_ids, GArray *entry); =20 +extern GlobalProperty pc_compat_4_2[]; +extern const size_t pc_compat_4_2_len; + extern GlobalProperty pc_compat_4_1[]; extern const size_t pc_compat_4_1_len; =20 --=20 2.21.0 From MAILER-DAEMON Thu Dec 12 12:33:52 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1ifSLY-0002TQ-Ma for mharc-qemu-arm@gnu.org; Thu, 12 Dec 2019 12:33:52 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:45982) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ifSLU-0002Nn-7U for qemu-arm@nongnu.org; Thu, 12 Dec 2019 12:33:49 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ifSLR-00031J-3x for qemu-arm@nongnu.org; Thu, 12 Dec 2019 12:33:48 -0500 Received: from us-smtp-2.mimecast.com ([207.211.31.81]:52373 helo=us-smtp-delivery-1.mimecast.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1ifSLQ-0002ze-N8 for qemu-arm@nongnu.org; Thu, 12 Dec 2019 12:33:44 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; 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Thu, 12 Dec 2019 17:33:35 +0000 (UTC) From: Andrew Jones To: qemu-devel@nongnu.org, qemu-arm@nongnu.org Cc: richard.henderson@linaro.org, peter.maydell@linaro.org, guoheyi@huawei.com, bijan.mottahedeh@oracle.com, maz@kernel.org, msys.mizuma@gmail.com Subject: [RFC PATCH v2 3/5] target/arm/kvm: Implement virtual time adjustment Date: Thu, 12 Dec 2019 18:33:18 +0100 Message-Id: <20191212173320.11610-4-drjones@redhat.com> In-Reply-To: <20191212173320.11610-1-drjones@redhat.com> References: <20191212173320.11610-1-drjones@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.84 on 10.5.11.23 X-MC-Unique: qPAblt0SOpKv5S9d8zcKsQ-1 X-Mimecast-Spam-Score: 0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 207.211.31.81 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 12 Dec 2019 17:33:51 -0000 When a VM is stopped (guest is paused) guest virtual time should stop counting. Otherwise, when the VM is resumed it will experience time jumps and its kernel may report soft lockups. Not counting virtual time while the VM is stopped has the side effect of making the guest's time appear to lag when compared with real time, and even with time derived from the physical counter. For this reason, this change, which is enabled by default, comes with a KVM CPU feature allowing it to be disabled, restoring legacy behavior. This patch only provides the implementation of the virtual time adjustment. A subsequent patch will provide the CPU property allowing the change to be enabled and disabled. Reported-by: Bijan Mottahedeh Signed-off-by: Andrew Jones --- target/arm/cpu.h | 9 +++++++++ target/arm/kvm.c | 48 ++++++++++++++++++++++++++++++++++++++++++++ target/arm/kvm32.c | 3 +++ target/arm/kvm64.c | 3 +++ target/arm/kvm_arm.h | 23 +++++++++++++++++++++ 5 files changed, 86 insertions(+) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 83a809d4bac4..a79ea74125b3 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -821,6 +821,15 @@ struct ARMCPU { /* KVM init features for this CPU */ uint32_t kvm_init_features[7]; =20 + /* KVM CPU features */ + bool kvm_adjvtime; + + /* VCPU virtual counter value used with kvm_adjvtime */ + uint64_t kvm_vtime; + + /* True if the run state is, or transitioning from, RUN_STATE_PAUSED *= / + bool runstate_paused; + /* Uniprocessor system with MP extensions */ bool mp_is_up; =20 diff --git a/target/arm/kvm.c b/target/arm/kvm.c index 5b82cefef608..a55fe7d7aefd 100644 --- a/target/arm/kvm.c +++ b/target/arm/kvm.c @@ -348,6 +348,24 @@ void kvm_arm_register_device(MemoryRegion *mr, uint64_= t devid, uint64_t group, memory_region_ref(kd->mr); } =20 +void kvm_arm_vm_state_change(void *opaque, int running, RunState state) +{ + CPUState *cs =3D opaque; + ARMCPU *cpu =3D ARM_CPU(cs); + + if (running) { + if (cpu->kvm_adjvtime && cpu->runstate_paused) { + kvm_arm_set_virtual_time(cs, cpu->kvm_vtime); + } + cpu->runstate_paused =3D false; + } else if (state =3D=3D RUN_STATE_PAUSED) { + cpu->runstate_paused =3D true; + if (cpu->kvm_adjvtime) { + kvm_arm_get_virtual_time(cs, &cpu->kvm_vtime); + } + } +} + static int compare_u64(const void *a, const void *b) { if (*(uint64_t *)a > *(uint64_t *)b) { @@ -579,6 +597,36 @@ int kvm_arm_sync_mpstate_to_qemu(ARMCPU *cpu) return 0; } =20 +void kvm_arm_get_virtual_time(CPUState *cs, uint64_t *cnt) +{ + struct kvm_one_reg reg =3D { + .id =3D KVM_REG_ARM_TIMER_CNT, + .addr =3D (uintptr_t)cnt, + }; + int ret; + + ret =3D kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, ®); + if (ret) { + error_report("Failed to get KVM_REG_ARM_TIMER_CNT"); + abort(); + } +} + +void kvm_arm_set_virtual_time(CPUState *cs, uint64_t cnt) +{ + struct kvm_one_reg reg =3D { + .id =3D KVM_REG_ARM_TIMER_CNT, + .addr =3D (uintptr_t)&cnt, + }; + int ret; + + ret =3D kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, ®); + if (ret) { + error_report("Failed to set KVM_REG_ARM_TIMER_CNT"); + abort(); + } +} + int kvm_put_vcpu_events(ARMCPU *cpu) { CPUARMState *env =3D &cpu->env; diff --git a/target/arm/kvm32.c b/target/arm/kvm32.c index 32bf8d6757c4..3a8b437eef0b 100644 --- a/target/arm/kvm32.c +++ b/target/arm/kvm32.c @@ -16,6 +16,7 @@ #include "qemu-common.h" #include "cpu.h" #include "qemu/timer.h" +#include "sysemu/runstate.h" #include "sysemu/kvm.h" #include "kvm_arm.h" #include "internals.h" @@ -198,6 +199,8 @@ int kvm_arch_init_vcpu(CPUState *cs) return -EINVAL; } =20 + qemu_add_vm_change_state_handler(kvm_arm_vm_state_change, cs); + /* Determine init features for this CPU */ memset(cpu->kvm_init_features, 0, sizeof(cpu->kvm_init_features)); if (cpu->start_powered_off) { diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c index 5cafcb7d36dd..e486eaf1f944 100644 --- a/target/arm/kvm64.c +++ b/target/arm/kvm64.c @@ -23,6 +23,7 @@ #include "qemu/host-utils.h" #include "qemu/main-loop.h" #include "exec/gdbstub.h" +#include "sysemu/runstate.h" #include "sysemu/kvm.h" #include "sysemu/kvm_int.h" #include "kvm_arm.h" @@ -735,6 +736,8 @@ int kvm_arch_init_vcpu(CPUState *cs) return -EINVAL; } =20 + qemu_add_vm_change_state_handler(kvm_arm_vm_state_change, cs); + /* Determine init features for this CPU */ memset(cpu->kvm_init_features, 0, sizeof(cpu->kvm_init_features)); if (cpu->start_powered_off) { diff --git a/target/arm/kvm_arm.h b/target/arm/kvm_arm.h index 8e14d400e8ab..16b53e45377d 100644 --- a/target/arm/kvm_arm.h +++ b/target/arm/kvm_arm.h @@ -232,6 +232,24 @@ void kvm_arm_sve_get_vls(CPUState *cs, unsigned long *= map); */ void kvm_arm_set_cpu_features_from_host(ARMCPU *cpu); =20 +/** + * void kvm_arm_get_virtual_time: + * @cs: CPUState + * @cnt: the virtual counter to fill in + * + * Gets the VCPU's virtual counter and stores it in @cnt. + */ +void kvm_arm_get_virtual_time(CPUState *cs, uint64_t *cnt); + +/** + * void kvm_arm_set_virtual_time: + * @cs: CPUState + * @cnt: new virtual counter value + * + * Sets the VCPU's virtual counter to @cnt. + */ +void kvm_arm_set_virtual_time(CPUState *cs, uint64_t cnt); + /** * kvm_arm_aarch32_supported: * @cs: CPUState @@ -288,6 +306,8 @@ void kvm_arm_pmu_set_irq(CPUState *cs, int irq); void kvm_arm_pmu_init(CPUState *cs); int kvm_arm_set_irq(int cpu, int irqtype, int irq, int level); =20 +void kvm_arm_vm_state_change(void *opaque, int running, RunState state); + #else =20 static inline void kvm_arm_set_cpu_features_from_host(ARMCPU *cpu) @@ -324,6 +344,9 @@ static inline int kvm_arm_vgic_probe(void) return 0; } =20 +static inline void kvm_arm_get_virtual_time(CPUState *cs, uint64_t *cnt) {= } +static inline void kvm_arm_set_virtual_time(CPUState *cs, uint64_t cnt) {} + static inline void kvm_arm_pmu_set_irq(CPUState *cs, int irq) {} static inline void kvm_arm_pmu_init(CPUState *cs) {} =20 --=20 2.21.0 From MAILER-DAEMON Thu Dec 12 12:33:54 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1ifSLa-0002W2-L7 for mharc-qemu-arm@gnu.org; Thu, 12 Dec 2019 12:33:54 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:46264) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ifSLV-0002PX-G8 for qemu-arm@nongnu.org; Thu, 12 Dec 2019 12:33:50 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ifSLU-000392-5y for qemu-arm@nongnu.org; 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Thu, 12 Dec 2019 12:33:45 -0500 Received: from smtp.corp.redhat.com (int-mx08.intmail.prod.int.phx2.redhat.com [10.5.11.23]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx01.redhat.com (Postfix) with ESMTPS id 13860100550E; Thu, 12 Dec 2019 17:33:43 +0000 (UTC) Received: from kamzik.brq.redhat.com (unknown [10.43.2.160]) by smtp.corp.redhat.com (Postfix) with ESMTP id 84FDC19C4F; Thu, 12 Dec 2019 17:33:38 +0000 (UTC) From: Andrew Jones To: qemu-devel@nongnu.org, qemu-arm@nongnu.org Cc: richard.henderson@linaro.org, peter.maydell@linaro.org, guoheyi@huawei.com, bijan.mottahedeh@oracle.com, maz@kernel.org, msys.mizuma@gmail.com, Eric Auger , Beata Michalska Subject: [RFC PATCH v2 4/5] tests/arm-cpu-features: Check feature default values Date: Thu, 12 Dec 2019 18:33:19 +0100 Message-Id: <20191212173320.11610-5-drjones@redhat.com> In-Reply-To: <20191212173320.11610-1-drjones@redhat.com> References: <20191212173320.11610-1-drjones@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.84 on 10.5.11.23 X-MC-Unique: pGsM3uK6M5qBd83KTUfzeQ-1 X-Mimecast-Spam-Score: 0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 207.211.31.120 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 12 Dec 2019 17:33:52 -0000 If we know what the default value should be then we can test for that as well as the feature existence. Signed-off-by: Andrew Jones Reviewed-by: Richard Henderson --- tests/arm-cpu-features.c | 44 ++++++++++++++++++++++++++++++++-------- 1 file changed, 35 insertions(+), 9 deletions(-) diff --git a/tests/arm-cpu-features.c b/tests/arm-cpu-features.c index 6e99aa951e74..06ed05e934e6 100644 --- a/tests/arm-cpu-features.c +++ b/tests/arm-cpu-features.c @@ -159,6 +159,32 @@ static bool resp_get_feature(QDict *resp, const char *= feature) qobject_unref(_resp); \ }) =20 +#define assert_has_feature_enabled(qts, cpu_type, feature) \ +({ \ + QDict *_resp, *_props; \ + \ + _resp =3D do_query_no_props(qts, cpu_type); \ + g_assert(_resp); \ + g_assert(resp_has_props(_resp)); \ + _props =3D resp_get_props(_resp); \ + g_assert(qdict_get(_props, feature)); \ + g_assert(qdict_get_bool(_props, feature)); \ + qobject_unref(_resp); \ +}) + +#define assert_has_feature_disabled(qts, cpu_type, feature) \ +({ \ + QDict *_resp, *_props; \ + \ + _resp =3D do_query_no_props(qts, cpu_type); \ + g_assert(_resp); \ + g_assert(resp_has_props(_resp)); \ + _props =3D resp_get_props(_resp); \ + g_assert(qdict_get(_props, feature)); \ + g_assert(!qdict_get_bool(_props, feature)); \ + qobject_unref(_resp); \ +}) + static void assert_type_full(QTestState *qts) { const char *error; @@ -405,16 +431,16 @@ static void test_query_cpu_model_expansion(const void= *data) assert_error(qts, "host", "The CPU type 'host' requires KVM", NULL); =20 /* Test expected feature presence/absence for some cpu types */ - assert_has_feature(qts, "max", "pmu"); - assert_has_feature(qts, "cortex-a15", "pmu"); + assert_has_feature_enabled(qts, "max", "pmu"); + assert_has_feature_enabled(qts, "cortex-a15", "pmu"); assert_has_not_feature(qts, "cortex-a15", "aarch64"); =20 if (g_str_equal(qtest_get_arch(), "aarch64")) { - assert_has_feature(qts, "max", "aarch64"); - assert_has_feature(qts, "max", "sve"); - assert_has_feature(qts, "max", "sve128"); - assert_has_feature(qts, "cortex-a57", "pmu"); - assert_has_feature(qts, "cortex-a57", "aarch64"); + assert_has_feature_enabled(qts, "max", "aarch64"); + assert_has_feature_enabled(qts, "max", "sve"); + assert_has_feature_enabled(qts, "max", "sve128"); + assert_has_feature_enabled(qts, "cortex-a57", "pmu"); + assert_has_feature_enabled(qts, "cortex-a57", "aarch64"); =20 sve_tests_default(qts, "max"); =20 @@ -451,8 +477,8 @@ static void test_query_cpu_model_expansion_kvm(const vo= id *data) QDict *resp; char *error; =20 - assert_has_feature(qts, "host", "aarch64"); - assert_has_feature(qts, "host", "pmu"); + assert_has_feature_enabled(qts, "host", "aarch64"); + assert_has_feature_enabled(qts, "host", "pmu"); =20 assert_error(qts, "cortex-a15", "We cannot guarantee the CPU type 'cortex-a15' works " --=20 2.21.0 From MAILER-DAEMON Thu Dec 12 12:33:58 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1ifSLd-0002a9-RU for mharc-qemu-arm@gnu.org; Thu, 12 Dec 2019 12:33:57 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:47039) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ifSLZ-0002Uf-Dg for qemu-arm@nongnu.org; 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Thu, 12 Dec 2019 12:33:46 -0500 Received: from smtp.corp.redhat.com (int-mx08.intmail.prod.int.phx2.redhat.com [10.5.11.23]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx01.redhat.com (Postfix) with ESMTPS id 4742418543A0; Thu, 12 Dec 2019 17:33:45 +0000 (UTC) Received: from kamzik.brq.redhat.com (unknown [10.43.2.160]) by smtp.corp.redhat.com (Postfix) with ESMTP id 7A2621C955; Thu, 12 Dec 2019 17:33:43 +0000 (UTC) From: Andrew Jones To: qemu-devel@nongnu.org, qemu-arm@nongnu.org Cc: richard.henderson@linaro.org, peter.maydell@linaro.org, guoheyi@huawei.com, bijan.mottahedeh@oracle.com, maz@kernel.org, msys.mizuma@gmail.com Subject: [RFC PATCH v2 5/5] target/arm/cpu: Add the kvm-no-adjvtime CPU property Date: Thu, 12 Dec 2019 18:33:20 +0100 Message-Id: <20191212173320.11610-6-drjones@redhat.com> In-Reply-To: <20191212173320.11610-1-drjones@redhat.com> References: <20191212173320.11610-1-drjones@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.84 on 10.5.11.23 X-MC-Unique: qCLQr4uSMVWCSCAc0HmYAg-1 X-Mimecast-Spam-Score: 0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 207.211.31.81 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 12 Dec 2019 17:33:56 -0000 kvm-no-adjvtime is a KVM specific CPU property and a first of its kind. To accommodate it we also add kvm_arm_add_vcpu_properties() and a KVM specific CPU properties description to the CPU features document. Signed-off-by: Andrew Jones --- docs/arm-cpu-features.rst | 31 ++++++++++++++++++++++++++++++- hw/arm/virt.c | 8 ++++++++ include/hw/arm/virt.h | 1 + target/arm/cpu.c | 2 ++ target/arm/cpu64.c | 1 + target/arm/kvm.c | 28 ++++++++++++++++++++++++++++ target/arm/kvm_arm.h | 11 +++++++++++ target/arm/monitor.c | 1 + tests/arm-cpu-features.c | 4 ++++ 9 files changed, 86 insertions(+), 1 deletion(-) diff --git a/docs/arm-cpu-features.rst b/docs/arm-cpu-features.rst index 1b367e22e16e..641ec9cb8f4a 100644 --- a/docs/arm-cpu-features.rst +++ b/docs/arm-cpu-features.rst @@ -31,7 +31,9 @@ supporting the feature or only supporting the feature und= er certain configurations. For example, the `aarch64` CPU feature, which, when disabled, enables the optional AArch32 CPU feature, is only supported when using the KVM accelerator and when running on a host CPU type that -supports the feature. +supports the feature. While `aarch64` currently only works with KVM, +it could work with TCG. CPU features that are specific to KVM are +prefixed with "kvm-" and are described in "KVM VCPU Features". =20 CPU Feature Probing =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D @@ -171,6 +173,33 @@ disabling many SVE vector lengths would be quite verbo= se, the `sve` CPU properties have special semantics (see "SVE CPU Property Parsing Semantics"). =20 +KVM VCPU Features +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D + +KVM VCPU features are CPU features that are specific to KVM, such as +paravirt features or features that enable CPU virtualization extensions. +The features' CPU properties are only available when KVM is enabled and +are named with the prefix "kvm-". KVM VCPU features may be probed, +enabled, and disabled in the same way as other CPU features. Below is the +list of KVM VCPU features and their descriptions. + + kvm-no-adjvtime When disabled, each time the VM transitions + back to running state from the paused state the + VCPU's vitual counter is updated to ensure the + stopped time is not counted. This avoids time + jumps surprising guest OSes and applications, + as long as they use the virtual counter for + timekeeping, but has the side effect of the + virtual and physical counters diverging. All + timekeeping based on the virtual counter will + appear to lag behind any timekeeping that does + not subtract VM stopped time. The guest may + resynchronize its virtual counter with other + time sources as needed. Enabling this KVM VCPU + feature provides the legacy behavior, which is + to also count stopped time with the virtual + counter. + SVE CPU Properties =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D =20 diff --git a/hw/arm/virt.c b/hw/arm/virt.c index cb7041e9677a..e9a08eb883bf 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -1664,6 +1664,11 @@ static void machvirt_init(MachineState *machine) } } =20 + if (vmc->kvm_no_adjvtime && + object_property_find(cpuobj, "kvm-no-adjvtime", NULL)) { + object_property_set_bool(cpuobj, true, "kvm-no-adjvtime", NULL= ); + } + if (vmc->no_pmu && object_property_find(cpuobj, "pmu", NULL)) { object_property_set_bool(cpuobj, false, "pmu", NULL); } @@ -2154,8 +2159,11 @@ DEFINE_VIRT_MACHINE_AS_LATEST(5, 0) =20 static void virt_machine_4_2_options(MachineClass *mc) { + VirtMachineClass *vmc =3D VIRT_MACHINE_CLASS(OBJECT_CLASS(mc)); + virt_machine_5_0_options(mc); compat_props_add(mc->compat_props, hw_compat_4_2, hw_compat_4_2_len); + vmc->kvm_no_adjvtime =3D true; } DEFINE_VIRT_MACHINE(4, 2) =20 diff --git a/include/hw/arm/virt.h b/include/hw/arm/virt.h index 0b41083e9d5c..80e00161b8f2 100644 --- a/include/hw/arm/virt.h +++ b/include/hw/arm/virt.h @@ -109,6 +109,7 @@ typedef struct { bool smbios_old_sys_ver; bool no_highmem_ecam; bool no_ged; /* Machines < 4.2 has no support for ACPI GED device */ + bool kvm_no_adjvtime; } VirtMachineClass; =20 typedef struct { diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 7a4ac9339bf9..53c73c25a67f 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -2482,6 +2482,7 @@ static void arm_max_initfn(Object *obj) =20 if (kvm_enabled()) { kvm_arm_set_cpu_features_from_host(cpu); + kvm_arm_add_vcpu_properties(obj); } else { cortex_a15_initfn(obj); =20 @@ -2673,6 +2674,7 @@ static void arm_host_initfn(Object *obj) if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { aarch64_add_sve_properties(obj); } + kvm_arm_add_vcpu_properties(obj); arm_cpu_post_init(obj); } =20 diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index a39d6fcea34f..3cd416db8089 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -605,6 +605,7 @@ static void aarch64_max_initfn(Object *obj) =20 if (kvm_enabled()) { kvm_arm_set_cpu_features_from_host(cpu); + kvm_arm_add_vcpu_properties(obj); } else { uint64_t t; uint32_t u; diff --git a/target/arm/kvm.c b/target/arm/kvm.c index a55fe7d7aefd..7666b250ab96 100644 --- a/target/arm/kvm.c +++ b/target/arm/kvm.c @@ -17,6 +17,8 @@ #include "qemu/timer.h" #include "qemu/error-report.h" #include "qemu/main-loop.h" +#include "qom/object.h" +#include "qapi/error.h" #include "sysemu/sysemu.h" #include "sysemu/kvm.h" #include "sysemu/kvm_int.h" @@ -179,6 +181,32 @@ void kvm_arm_set_cpu_features_from_host(ARMCPU *cpu) env->features =3D arm_host_cpu_features.features; } =20 +static bool kvm_no_adjvtime_get(Object *obj, Error **errp) +{ + return !ARM_CPU(obj)->kvm_adjvtime; +} + +static void kvm_no_adjvtime_set(Object *obj, bool value, Error **errp) +{ + ARM_CPU(obj)->kvm_adjvtime =3D !value; +} + +/* KVM VCPU properties should be prefixed with "kvm-". */ +void kvm_arm_add_vcpu_properties(Object *obj) +{ + if (!kvm_enabled()) { + return; + } + + ARM_CPU(obj)->kvm_adjvtime =3D true; + object_property_add_bool(obj, "kvm-no-adjvtime", kvm_no_adjvtime_get, + kvm_no_adjvtime_set, &error_abort); + object_property_set_description(obj, "kvm-no-adjvtime", + "Set on to disable the adjustment of " + "the virtual counter. VM stopped time = " + "will be counted.", &error_abort); +} + bool kvm_arm_pmu_supported(CPUState *cpu) { KVMState *s =3D KVM_STATE(current_machine->accelerator); diff --git a/target/arm/kvm_arm.h b/target/arm/kvm_arm.h index 16b53e45377d..7d76f26beaca 100644 --- a/target/arm/kvm_arm.h +++ b/target/arm/kvm_arm.h @@ -232,6 +232,15 @@ void kvm_arm_sve_get_vls(CPUState *cs, unsigned long *= map); */ void kvm_arm_set_cpu_features_from_host(ARMCPU *cpu); =20 +/** + * void kvm_arm_add_vcpu_properties: + * @obj: The CPU object to add the properties to + * + * Add all KVM specific CPU properties to the CPU object. These + * are the CPU properties with "kvm-" prefixed names. + */ +void kvm_arm_add_vcpu_properties(Object *obj); + /** * void kvm_arm_get_virtual_time: * @cs: CPUState @@ -319,6 +328,8 @@ static inline void kvm_arm_set_cpu_features_from_host(A= RMCPU *cpu) cpu->host_cpu_probe_failed =3D true; } =20 +static inline void kvm_arm_add_vcpu_properties(Object *obj) {} + static inline bool kvm_arm_aarch32_supported(CPUState *cs) { return false; diff --git a/target/arm/monitor.c b/target/arm/monitor.c index fa054f8a369c..9725dfff16d4 100644 --- a/target/arm/monitor.c +++ b/target/arm/monitor.c @@ -103,6 +103,7 @@ static const char *cpu_model_advertised_features[] =3D = { "sve128", "sve256", "sve384", "sve512", "sve640", "sve768", "sve896", "sve1024", "sve1152", "sve1280", "sve1408", "sve1536", "sve1664", "sve1792", "sve1920", "sve2048", + "kvm-no-adjvtime", NULL }; =20 diff --git a/tests/arm-cpu-features.c b/tests/arm-cpu-features.c index 06ed05e934e6..738e49447377 100644 --- a/tests/arm-cpu-features.c +++ b/tests/arm-cpu-features.c @@ -435,6 +435,8 @@ static void test_query_cpu_model_expansion(const void *= data) assert_has_feature_enabled(qts, "cortex-a15", "pmu"); assert_has_not_feature(qts, "cortex-a15", "aarch64"); =20 + assert_has_not_feature(qts, "max", "kvm-no-adjvtime"); + if (g_str_equal(qtest_get_arch(), "aarch64")) { assert_has_feature_enabled(qts, "max", "aarch64"); assert_has_feature_enabled(qts, "max", "sve"); @@ -469,6 +471,8 @@ static void test_query_cpu_model_expansion_kvm(const vo= id *data) return; } =20 + assert_has_feature_disabled(qts, "host", "kvm-no-adjvtime"); + if (g_str_equal(qtest_get_arch(), "aarch64")) { bool kvm_supports_sve; char max_name[8], name[8]; --=20 2.21.0 From MAILER-DAEMON Thu Dec 12 13:28:20 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1ifTCG-0007zK-4g for mharc-qemu-arm@gnu.org; Thu, 12 Dec 2019 13:28:20 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:38299) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ifTC6-0007we-4O for qemu-arm@nongnu.org; Thu, 12 Dec 2019 13:28:11 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ifTC3-0003WZ-2Z for qemu-arm@nongnu.org; Thu, 12 Dec 2019 13:28:08 -0500 Received: from us-smtp-2.mimecast.com ([207.211.31.81]:38898 helo=us-smtp-delivery-1.mimecast.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1ifTC2-0003V7-UO for qemu-arm@nongnu.org; Thu, 12 Dec 2019 13:28:07 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1576175284; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references:autocrypt:autocrypt; bh=qXuj2wlIvR0mV4LH44WrMCfAVVXJ4LZPzKVEVs84WzQ=; b=SNmSXnVU+Sbf7hakt1GyqlCSyS+xxRdOm3cXxr6AOwswiaIAooNF/nREWo5D0MsNE2FkaO KUI1S4q3XZ/IEBXf89nsWwMzWkcbD8lfBdHmMkHYAiZKFkeMhnZQ8thKQy14yLNcNCNR2I C3P3pb9p4syh/g7u5nCOzVdSX4wXy7w= Received: from mimecast-mx01.redhat.com (mimecast-mx01.redhat.com [209.132.183.4]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-425-JPSbFPsHM42J2NFIiV00-Q-1; Thu, 12 Dec 2019 13:28:03 -0500 Received: from smtp.corp.redhat.com (int-mx08.intmail.prod.int.phx2.redhat.com [10.5.11.23]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx01.redhat.com (Postfix) with ESMTPS id EB98C100551B; Thu, 12 Dec 2019 18:28:00 +0000 (UTC) Received: from [10.36.117.65] (ovpn-117-65.ams2.redhat.com [10.36.117.65]) by smtp.corp.redhat.com (Postfix) with ESMTP id 2CEA019C4F; Thu, 12 Dec 2019 18:27:54 +0000 (UTC) Subject: Re: [RFC PATCH v2 1/5] hw: add compat machines for 5.0 To: Andrew Jones , qemu-devel@nongnu.org, qemu-arm@nongnu.org Cc: richard.henderson@linaro.org, peter.maydell@linaro.org, guoheyi@huawei.com, bijan.mottahedeh@oracle.com, maz@kernel.org, msys.mizuma@gmail.com, Eduardo Habkost , Marcel Apfelbaum , "Michael S. Tsirkin" , Paolo Bonzini , Richard Henderson , David Gibson , Cornelia Huck , Halil Pasic , Christian Borntraeger , "open list:sPAPR" , "open list:S390 TCG CPUs" References: <20191212173320.11610-1-drjones@redhat.com> <20191212173320.11610-2-drjones@redhat.com> From: David Hildenbrand Autocrypt: addr=david@redhat.com; prefer-encrypt=mutual; keydata= mQINBFXLn5EBEAC+zYvAFJxCBY9Tr1xZgcESmxVNI/0ffzE/ZQOiHJl6mGkmA1R7/uUpiCjJ dBrn+lhhOYjjNefFQou6478faXE6o2AhmebqT4KiQoUQFV4R7y1KMEKoSyy8hQaK1umALTdL QZLQMzNE74ap+GDK0wnacPQFpcG1AE9RMq3aeErY5tujekBS32jfC/7AnH7I0v1v1TbbK3Gp XNeiN4QroO+5qaSr0ID2sz5jtBLRb15RMre27E1ImpaIv2Jw8NJgW0k/D1RyKCwaTsgRdwuK Kx/Y91XuSBdz0uOyU/S8kM1+ag0wvsGlpBVxRR/xw/E8M7TEwuCZQArqqTCmkG6HGcXFT0V9 PXFNNgV5jXMQRwU0O/ztJIQqsE5LsUomE//bLwzj9IVsaQpKDqW6TAPjcdBDPLHvriq7kGjt WhVhdl0qEYB8lkBEU7V2Yb+SYhmhpDrti9Fq1EsmhiHSkxJcGREoMK/63r9WLZYI3+4W2rAc UucZa4OT27U5ZISjNg3Ev0rxU5UH2/pT4wJCfxwocmqaRr6UYmrtZmND89X0KigoFD/XSeVv jwBRNjPAubK9/k5NoRrYqztM9W6sJqrH8+UWZ1Idd/DdmogJh0gNC0+N42Za9yBRURfIdKSb B3JfpUqcWwE7vUaYrHG1nw54pLUoPG6sAA7Mehl3nd4pZUALHwARAQABtCREYXZpZCBIaWxk ZW5icmFuZCA8ZGF2aWRAcmVkaGF0LmNvbT6JAlgEEwEIAEICGwMFCQlmAYAGCwkIBwMCBhUI AgkKCwQWAgMBAh4BAheAFiEEG9nKrXNcTDpGDfzKTd4Q9wD/g1oFAl3pImkCGQEACgkQTd4Q 9wD/g1o+VA//SFvIHUAvul05u6wKv/pIR6aICPdpF9EIgEU448g+7FfDgQwcEny1pbEzAmiw zAXIQ9H0NZh96lcq+yDLtONnXk/bEYWHHUA014A1wqcYNRY8RvY1+eVHb0uu0KYQoXkzvu+s Dncuguk470XPnscL27hs8PgOP6QjG4jt75K2LfZ0eAqTOUCZTJxA8A7E9+XTYuU0hs7QVrWJ jQdFxQbRMrYz7uP8KmTK9/Cnvqehgl4EzyRaZppshruKMeyheBgvgJd5On1wWq4ZUV5PFM4x II3QbD3EJfWbaJMR55jI9dMFa+vK7MFz3rhWOkEx/QR959lfdRSTXdxs8V3zDvChcmRVGN8U Vo93d1YNtWnA9w6oCW1dnDZ4kgQZZSBIjp6iHcA08apzh7DPi08jL7M9UQByeYGr8KuR4i6e RZI6xhlZerUScVzn35ONwOC91VdYiQgjemiVLq1WDDZ3B7DIzUZ4RQTOaIWdtXBWb8zWakt/ ztGhsx0e39Gvt3391O1PgcA7ilhvqrBPemJrlb9xSPPRbaNAW39P8ws/UJnzSJqnHMVxbRZC Am4add/SM+OCP0w3xYss1jy9T+XdZa0lhUvJfLy7tNcjVG/sxkBXOaSC24MFPuwnoC9WvCVQ ZBxouph3kqc4Dt5X1EeXVLeba+466P1fe1rC8MbcwDkoUo65Ag0EVcufkQEQAOfX3n0g0fZz Bgm/S2zF/kxQKCEKP8ID+Vz8sy2GpDvveBq4H2Y34XWsT1zLJdvqPI4af4ZSMxuerWjXbVWb T6d4odQIG0fKx4F8NccDqbgHeZRNajXeeJ3R7gAzvWvQNLz4piHrO/B4tf8svmRBL0ZB5P5A 2uhdwLU3NZuK22zpNn4is87BPWF8HhY0L5fafgDMOqnf4guJVJPYNPhUFzXUbPqOKOkL8ojk CXxkOFHAbjstSK5Ca3fKquY3rdX3DNo+EL7FvAiw1mUtS+5GeYE+RMnDCsVFm/C7kY8c2d0G NWkB9pJM5+mnIoFNxy7YBcldYATVeOHoY4LyaUWNnAvFYWp08dHWfZo9WCiJMuTfgtH9tc75 7QanMVdPt6fDK8UUXIBLQ2TWr/sQKE9xtFuEmoQGlE1l6bGaDnnMLcYu+Asp3kDT0w4zYGsx 5r6XQVRH4+5N6eHZiaeYtFOujp5n+pjBaQK7wUUjDilPQ5QMzIuCL4YjVoylWiBNknvQWBXS lQCWmavOT9sttGQXdPCC5ynI+1ymZC1ORZKANLnRAb0NH/UCzcsstw2TAkFnMEbo9Zu9w7Kv AxBQXWeXhJI9XQssfrf4Gusdqx8nPEpfOqCtbbwJMATbHyqLt7/oz/5deGuwxgb65pWIzufa N7eop7uh+6bezi+rugUI+w6DABEBAAGJAiUEGAECAA8FAlXLn5ECGwwFCQlmAYAACgkQTd4Q 9wD/g1qA6w/+M+ggFv+JdVsz5+ZIc6MSyGUozASX+bmIuPeIecc9UsFRatc91LuJCKMkD9Uv GOcWSeFpLrSGRQ1Z7EMzFVU//qVs6uzhsNk0RYMyS0B6oloW3FpyQ+zOVylFWQCzoyyf227y GW8HnXunJSC+4PtlL2AY4yZjAVAPLK2l6mhgClVXTQ/S7cBoTQKP+jvVJOoYkpnFxWE9pn4t H5QIFk7Ip8TKr5k3fXVWk4lnUi9MTF/5L/mWqdyIO1s7cjharQCstfWCzWrVeVctpVoDfJWp 4LwTuQ5yEM2KcPeElLg5fR7WB2zH97oI6/Ko2DlovmfQqXh9xWozQt0iGy5tWzh6I0JrlcxJ ileZWLccC4XKD1037Hy2FLAjzfoWgwBLA6ULu0exOOdIa58H4PsXtkFPrUF980EEibUp0zFz GotRVekFAceUaRvAj7dh76cToeZkfsjAvBVb4COXuhgX6N4pofgNkW2AtgYu1nUsPAo+NftU CxrhjHtLn4QEBpkbErnXQyMjHpIatlYGutVMS91XTQXYydCh5crMPs7hYVsvnmGHIaB9ZMfB njnuI31KBiLUks+paRkHQlFcgS2N3gkRBzH7xSZ+t7Re3jvXdXEzKBbQ+dC3lpJB0wPnyMcX FOTT3aZT7IgePkt5iC/BKBk3hqKteTnJFeVIT7EC+a6YUFg= Organization: Red Hat GmbH Message-ID: <15037e94-0c85-63f2-e505-fb2c186a1565@redhat.com> Date: Thu, 12 Dec 2019 19:27:52 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.2.2 MIME-Version: 1.0 In-Reply-To: <20191212173320.11610-2-drjones@redhat.com> Content-Language: en-US X-Scanned-By: MIMEDefang 2.84 on 10.5.11.23 X-MC-Unique: JPSbFPsHM42J2NFIiV00-Q-1 X-Mimecast-Spam-Score: 0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: 7bit X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 207.211.31.81 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 12 Dec 2019 18:28:12 -0000 On 12.12.19 18:33, Andrew Jones wrote: > Add 5.0 machine types for arm/i440fx/q35/s390x/spapr. > > Signed-off-by: Andrew Jones > [...] > /* > * pseries-4.1 > diff --git a/hw/s390x/s390-virtio-ccw.c b/hw/s390x/s390-virtio-ccw.c > index d3edeef0ad92..a40f79e20733 100644 > --- a/hw/s390x/s390-virtio-ccw.c > +++ b/hw/s390x/s390-virtio-ccw.c > @@ -639,14 +639,27 @@ bool css_migration_enabled(void) > } \ > type_init(ccw_machine_register_##suffix) > > + > +static void ccw_machine_5_0_instance_options(MachineState *machine) > +{ > +} > + > +static void ccw_machine_5_0_class_options(MachineClass *mc) > +{ > +} > +DEFINE_CCW_MACHINE(5_0, "5.0", true); > + > static void ccw_machine_4_2_instance_options(MachineState *machine) > { > + ccw_machine_5_0_instance_options(machine); > } > > static void ccw_machine_4_2_class_options(MachineClass *mc) > { > + ccw_machine_5_0_class_options(mc); > + compat_props_add(mc->compat_props, hw_compat_4_2, hw_compat_4_2_len); > } > -DEFINE_CCW_MACHINE(4_2, "4.2", true); > +DEFINE_CCW_MACHINE(4_2, "4.2", false); > s390x parts LGTM Reviewed-by: David Hildenbrand -- Thanks, David / dhildenb From MAILER-DAEMON Thu Dec 12 14:24:37 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1ifU4j-0001ee-GX for mharc-qemu-arm@gnu.org; Thu, 12 Dec 2019 14:24:37 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:51494) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ifU4g-0001dB-PV for qemu-arm@nongnu.org; Thu, 12 Dec 2019 14:24:35 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ifU4e-0006ij-98 for qemu-arm@nongnu.org; Thu, 12 Dec 2019 14:24:33 -0500 Received: from us-smtp-delivery-1.mimecast.com ([207.211.31.120]:31333 helo=us-smtp-1.mimecast.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1ifU4d-0006dk-Rl for qemu-arm@nongnu.org; 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Thu, 12 Dec 2019 19:24:25 +0000 (UTC) Received: from localhost (ovpn-116-90.gru2.redhat.com [10.97.116.90]) by smtp.corp.redhat.com (Postfix) with ESMTP id 7E6E260BB9; Thu, 12 Dec 2019 19:24:20 +0000 (UTC) Date: Thu, 12 Dec 2019 16:24:19 -0300 From: Eduardo Habkost To: Andrew Jones Cc: qemu-devel@nongnu.org, qemu-arm@nongnu.org, richard.henderson@linaro.org, peter.maydell@linaro.org, guoheyi@huawei.com, bijan.mottahedeh@oracle.com, maz@kernel.org, msys.mizuma@gmail.com, Marcel Apfelbaum , "Michael S. Tsirkin" , Paolo Bonzini , Richard Henderson , David Gibson , David Hildenbrand , Cornelia Huck , Halil Pasic , Christian Borntraeger , "open list:sPAPR" , "open list:S390 TCG CPUs" Subject: Re: [RFC PATCH v2 1/5] hw: add compat machines for 5.0 Message-ID: <20191212192419.GB498046@habkost.net> References: <20191212173320.11610-1-drjones@redhat.com> <20191212173320.11610-2-drjones@redhat.com> MIME-Version: 1.0 In-Reply-To: <20191212173320.11610-2-drjones@redhat.com> X-Scanned-By: MIMEDefang 2.79 on 10.5.11.11 X-MC-Unique: s7sOpm61NjuN6GKZbrLnhw-1 X-Mimecast-Spam-Score: 0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: quoted-printable Content-Disposition: inline X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 207.211.31.120 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 12 Dec 2019 19:24:36 -0000 On Thu, Dec 12, 2019 at 06:33:16PM +0100, Andrew Jones wrote: > Add 5.0 machine types for arm/i440fx/q35/s390x/spapr. >=20 > Signed-off-by: Andrew Jones >=20 > --- >=20 > Hi Eduardo, >=20 > If we need to do something special for i440fx and q35, as > 9aec2e52ce9d ("hw: add compat machines for 4.2") implies, then > I'll need guidance as to what. Keeping default_cpu_version=3D=3D1 in pc-*-5.0 (like you did) is correct. However, you might want to use Cornelia's patch (which is probably already queued in the s390 tree) instead: https://patchew.org/QEMU/20191112104811.30323-1-cohuck@redhat.com --=20 Eduardo From MAILER-DAEMON Thu Dec 12 18:08:18 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1ifXZC-0001nd-FE for mharc-qemu-arm@gnu.org; Thu, 12 Dec 2019 18:08:18 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:57701) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ifXZ8-0001jE-Co for qemu-arm@nongnu.org; Thu, 12 Dec 2019 18:08:16 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ifXZ5-0001a7-Sl for qemu-arm@nongnu.org; Thu, 12 Dec 2019 18:08:14 -0500 Received: from mail-il1-x132.google.com ([2607:f8b0:4864:20::132]:42401) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ifXZ0-0001Lt-I3; Thu, 12 Dec 2019 18:08:06 -0500 Received: by mail-il1-x132.google.com with SMTP id a6so439968ili.9; Thu, 12 Dec 2019 15:08:06 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=y0TZkHXy72FpeYL3bZsOfbboQwjTGkf66FhGCbZ2cWo=; b=EpE1aob5Wn1nWhkVSECLNHXsYvzq1MnTYMxI01O2w62ZXlbx9M+xn1+NiDaywR5583 14mIVIeN7982sxZF4X2r808h/etbkontxp44IND7g/UVuOMMgLDGh3TPkiLppqbYyn1G N0nme8j8i1TR2vPXvij6o+Qo7WzKcVxgiDPfLqr1YbC+P9rfaYQobRONomIuAawYaZMC fds+k+o8pMLDSXBiRCgMqawG+Zh8x1Tx3P6Lh4FBqlCcmOdRBWsLrlPSzhYAqOAgMAE8 AlHEsoB1Jq/bfBNGMbkKgHNAwTbb0iblECqsK6zb6qnCUv8plR7vyxgnK++3NzpqarCZ Xf7A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=y0TZkHXy72FpeYL3bZsOfbboQwjTGkf66FhGCbZ2cWo=; b=XByAZypPTsdmxqlebCrTtjJIGFWayXDnBnWyvZspQD3/paN0gUvmiYZiHkYN3h/Tty o72B7n7atZNbK8+p+5hRy5VA3iYoW3yA2irPHCtQssK8UmwNWlwRfU/0h9VY2T7qjStK WESj+1sflTdRbI67hwizBwSfHyt+Bsgyhut3kQc9ZW7Bvn94VSGDhmM8bV7NlOFDhC3l lrdQl40xZ/32yDyaz5/KZhWNo90bULG/4GLMIl2nszmWjG6BuDs99X3cBauWOYLWU14Z y20fuR8G+U1ZiNUYBMNJZkgmQKnBq+8fdCImHvQaR9ruDqRm2HUzlcJRsk5EUURncv/n H+Mw== X-Gm-Message-State: APjAAAWXK8atEXa2ykR2R3QSE8Cyj2ZFBcHolqxOiq57GRtAmHZIjPQL V+vHM0oRjP58ntp8NIAOPTeoV659Sgzu5M5y7Sg= X-Google-Smtp-Source: APXvYqwYuKfPkqOtow9XIUsIq+IlSrgq9IeBjp8fK9789tHkj+OK3ByMpMlhIpE5ECqgCDEy2wfV0dczrpASKi/davA= X-Received: by 2002:a92:d5cf:: with SMTP id d15mr10329035ilq.306.1576192085368; Thu, 12 Dec 2019 15:08:05 -0800 (PST) MIME-Version: 1.0 References: <20191202210947.3603-1-nieklinnenbank@gmail.com> <74df65db-1f84-62ba-6d01-edf765fd1dc2@redhat.com> In-Reply-To: From: Niek Linnenbank Date: Fri, 13 Dec 2019 00:07:54 +0100 Message-ID: Subject: Re: [PATCH 00/10] Add Allwinner H3 SoC and Orange Pi PC Machine To: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= Cc: QEMU Developers , Beniamino Galvani , Peter Maydell , qemu-arm , Richard Henderson Content-Type: multipart/alternative; boundary="00000000000058a540059989d12b" X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::132 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 12 Dec 2019 23:08:17 -0000 --00000000000058a540059989d12b Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Hi Philippe, I have discovered that the hflags assertion error you reported is not caused by the Allwinner H3 patches but actually an existing problem. What I did is to use the latest master (v4.2.0 tag) without any patches applied. and tried to boot the raspi2 machine with and without debugging enabled. Without debuggin, the raspi2 machine runs fine and can boot the 5.4.2 linux kernel. With debugging enabled, the same hflags error shows. To reproduce it, build Linux 5.4.2 with the bmc2835_defconfig: $ ARCH=3Darm CROSS_COMPILE=3Darm-linux-gnueabi- make mrproper $ ARCH=3Darm CROSS_COMPILE=3Darm-linux-gnueabi- make bcm2835_defconfig $ ARCH=3Darm CROSS_COMPILE=3Darm-linux-gnueabi- make -j5 ... First build QEMU without debugging and try to boot linux: $ ./configure --target-list=3Darm-softmmu; make clean; make -j5 $ ./arm-softmmu/qemu-system-arm -M raspi2 \ -kernel $HOME/linux-5.4.2/arch/arm/boot/zImage \ -append 'console=3DttyAMA0,115200 earlyprintk debug' \ -dtb $HOME/linux-5.4.2/arch/arm/boot/dts/bcm2836-rpi-2-b.dtb \ -m 1024 -nographic -s [ 0.000000] Booting Linux on physical CPU 0x0 [ 0.000000] Linux version 5.4.2 (me@host) (gcc version 7.4.0 (Ubuntu/Linaro 7.4.0-1ubuntu1~18.04.1)) #1 Thu Dec 12 22:49:14 CET 2019 [ 0.000000] CPU: ARMv7 Processor [410fc075] revision 5 (ARMv7), cr=3D10c= 53c7d ... Then rebuild QEMU with debugging enabled and again try to boot linux: $ ./configure --target-list=3Darm-softmmu --enable-debug --extra-cflags=3D-ggdb; make clean; make -j5 $ ./arm-softmmu/qemu-system-arm -M raspi2 \ -kernel $HOME/linux-5.4.2/arch/arm/boot/zImage \ -append 'console=3DttyAMA0,115200 earlyprintk debug' \ -dtb $HOME/linux-5.4.2/arch/arm/boot/dts/bcm2836-rpi-2-b.dtb \ -m 1024 -nographic -s qemu-system-arm: /home/me/qemu/target/arm/helper.c:11359: cpu_get_tb_cpu_state: Assertion `flags =3D=3D rebuild_hflags_internal(env)' failed. qemu-system-arm: /home/me/qemu/target/arm/helper.c:11359: cpu_get_tb_cpu_state: Assertion `flags =3D=3D rebuild_hflags_internal(env)' failed. qemu-system-arm: /home/me/qemu/target/arm/helper.c:11359: cpu_get_tb_cpu_state: Assertion `flags =3D=3D rebuild_hflags_internal(env)' failed. Aborted (core dumped) $ git describe v4.2.0 What should be the next step? Should this be reported as a bug? Regards, Niek On Tue, Dec 10, 2019 at 9:12 PM Niek Linnenbank wrote: > Hi Philippe, > > On Tue, Dec 10, 2019 at 9:26 AM Philippe Mathieu-Daud=C3=A9 > wrote: > >> On 12/9/19 10:37 PM, Niek Linnenbank wrote: >> > Hi Philippe, >> > >> > On Tue, Dec 3, 2019 at 9:47 AM Philippe Mathieu-Daud=C3=A9 < >> philmd@redhat.com >> > > wrote: >> > >> > On 12/2/19 10:09 PM, Niek Linnenbank wrote: >> > > Dear QEMU developers, >> > > >> > > Hereby I would like to contribute the following set of patches = to >> > QEMU >> > > which add support for the Allwinner H3 System on Chip and the >> > > Orange Pi PC machine. The following features and devices are >> > supported: >> > > >> > > * SMP (Quad Core Cortex A7) >> > > * Generic Interrupt Controller configuration >> > > * SRAM mappings >> > > * Timer device (re-used from Allwinner A10) >> > > * UART >> > > * SD/MMC storage controller >> > > * EMAC ethernet connectivity >> > > * USB 2.0 interfaces >> > > * Clock Control Unit >> > > * System Control module >> > > * Security Identifier device >> > >> > Awesome! >> > >> > > Functionality related to graphical output such as HDMI, GPU, >> > > Display Engine and audio are not included. Recently released >> > > mainline Linux kernels (4.19 up to latest master) and mainline >> U-Boot >> > > are known to work. The SD/MMC code is tested using bonnie++ and >> > > various tools such as fsck, dd and fdisk. The EMAC is verified >> > with iperf3 >> > > using -netdev socket. >> > > >> > > To build a Linux mainline kernel that can be booted by the Oran= ge >> > Pi PC >> > > machine, simply configure the kernel using the sunxi_defconfig >> > configuration: >> > > $ ARCH=3Darm CROSS_COMPILE=3Darm-linux-gnueabi- make mrproper >> > > $ ARCH=3Darm CROSS_COMPILE=3Darm-linux-gnueabi- make >> sunxi_defconfig >> > > >> > > To be able to use USB storage, you need to manually enable the >> > corresponding >> > > configuration item. Start the kconfig configuration tool: >> > > $ ARCH=3Darm CROSS_COMPILE=3Darm-linux-gnueabi- make menuconf= ig >> > > >> > > Navigate to the following item, enable it and save your >> > configuration: >> > > Device Drivers > USB support > USB Mass Storage support >> > > >> > > Build the Linux kernel with: >> > > $ ARCH=3Darm CROSS_COMPILE=3Darm-linux-gnueabi- make -j5 >> > > >> > > To boot the newly build linux kernel in QEMU with the Orange Pi >> > PC machine, use: >> > > $ qemu-system-arm -M orangepi -m 512 -nic user -nographic \ >> > > -kernel /path/to/linux/arch/arm/boot/zImage \ >> > > -append 'console=3DttyS0,115200' \ >> > > -dtb >> /path/to/linux/arch/arm/boot/dts/sun8i-h3-orangepi-pc.dtb >> > > >> > > Note that this kernel does not have a root filesystem. You may >> > provide it >> > > with an official Orange Pi PC image [1] either as an SD card or >> as >> > > USB mass storage. To boot using the Orange Pi PC Debian image o= n >> > SD card, >> > > simply add the -sd argument and provide the proper root=3D kern= el >> > parameter: >> > > $ qemu-system-arm -M orangepi -m 512 -nic user -nographic \ >> > > -kernel /path/to/linux/arch/arm/boot/zImage \ >> > > -append 'console=3DttyS0,115200 root=3D/dev/mmcblk0p2' \ >> > > -dtb >> > /path/to/linux/arch/arm/boot/dts/sun8i-h3-orangepi-pc.dtb \ >> > > -sd OrangePi_pc_debian_stretch_server_linux5.3.5_v1.0.img >> > > >> > > Alternatively, you can also choose to build and boot a recent >> > buildroot [2] >> > > using the orangepi_pc_defconfig or Armbian image [3] for Orange >> > Pi PC. >> > >> > Richard, trying the Armbian image from >> > https://apt.armbian.com/pool/main/l/linux-4.20.7-sunxi/ I get: >> > >> > $ arm-softmmu/qemu-system-arm -M orangepi -m 512 -nic user \ >> > -append 'console=3DttyS0,115200' \ >> > -kernel boot/vmlinuz-4.20.7-sunxi \ >> > -dtb usr/lib/linux-image-dev-sunxi/sun8i-h3-orangepi-pc.dtb \ >> > -serial stdio -d unimp >> > Uncompressing Linux... done, booting the kernel. >> > rtc: unimplemented device write (size 4, value 0x16aa0001, offset >> 0x0) >> > rtc: unimplemented device read (size 4, offset 0x0) >> > rtc: unimplemented device read (size 4, offset 0x0) >> > rtc: unimplemented device read (size 4, offset 0x8) >> > qemu-system-arm: target/arm/helper.c:11359: cpu_get_tb_cpu_state: >> > Assertion `flags =3D=3D rebuild_hflags_internal(env)' failed. >> > Aborted (core dumped) >> > >> > >> > I'm trying to reproduce the error you reported here with my patch set >> on >> > latest master, >> > but so far without any result. The host OS I'm using is Ubuntu 18.04.3 >> > LTS on x86_64. >> > I ran several times using the same 4.20.7-sunxi kernel and same comman= d >> > line. >> > >> > Some questions that might help: >> > 1) Are there any specific steps you did in order to produce this error= ? >> >> I build QEMU with: >> >> ./configure --enable-trace-backends=3Dlog --extra-cflags=3D-ggdb >> --enable-debug >> >> > 2) Could this be a known / existing issue? >> > 3) How many times did you see this error? >> >> Always >> >> > 4) Are you also using Ubuntu 18.04.3 LTS on x86_64, or a different hos= t >> OS? >> >> Host is Fedora 30. >> > > OK thanks, I will try again using the info above after I finished > reworking the other patch comments. > > Niek > > >> >> > >> > Regards, >> > Niek >> >> > > -- > Niek Linnenbank > > --=20 Niek Linnenbank --00000000000058a540059989d12b Content-Type: text/html; charset="UTF-8" Content-Transfer-Encoding: quoted-printable
Hi Phil= ippe,

I have discovered that the hflags assert= ion error you reported is not caused by the Allwinner H3
patches = but actually an existing problem. What I did is to use the latest master (v= 4.2.0 tag) without any patches applied.
and tried to boot the= raspi2 machine with and without debugging enabled. Without debuggin, the r= aspi2
machine runs fine and can boot the 5.4.2 linux kernel. With= debugging enabled, the same hflags error shows.

T= o reproduce it, build Linux 5.4.2 with the bmc2835_defconfig:
$ ARCH=3Darm CROSS_COMPILE=3Darm-linux-gnueabi- make mrproper
$ ARCH=3Darm CROSS_COMPILE=3Darm-linux-gnueabi- make bcm2835_defconfig
$ ARCH=3Darm CROSS_COMPILE=3Darm-linux-gnueabi- make -j5
...

First build QEMU without debugging and = try to boot linux:
$ ./configure --target-list=3Darm-softmmu; mak= e clean; make -j5 $ ./arm-softmmu/qemu-system-arm -M raspi2 \ -kernel $HOME/linux-5.4.2/arch/arm/boot/zImage \ -append 'console=3DttyAMA0,115200 earlyprintk debug' \ -dtb $HOME/linux-5.4.2/arch/arm/boot/dts/bcm2836-rpi-2-b.dtb \ -m 1024 -nographic -s [ 0.000000] Booting Linux on physical CPU 0x0 [ 0.000000] Linux version 5.4.2 (me@host) (gcc version 7.4.0 (Ubuntu/Lin= aro 7.4.0-1ubuntu1~18.04.1)) #1 Thu Dec 12 22:49:14 CET 2019 [ 0.000000] CPU: ARMv7 Processor [410fc075] revision 5 (ARMv7), cr=3D10c= 53c7d ...
Then rebuild QEMU with debugging enable= d and again try to boot linux:
$ ./configure --target-list=3Darm-= softmmu --enable-debug --extra-cflags=3D-ggdb; make clean; make -j5 $ ./arm-softmmu/qemu-system-arm -M raspi2 \ -kernel $HOME/linux-5.4.2/arch/arm/boot/zImage \ -append 'console=3DttyAMA0,115200 earlyprintk debug' \ -dtb $HOME/linux-5.4.2/arch/arm/boot/dts/bcm2836-rpi-2-b.dtb \ -m 1024 -nographic -s qemu-system-arm: /home/me/qemu/target/arm/helper.c:11359: cpu_get_tb_cpu_st= ate: Assertion `flags =3D=3D rebuild_hflags_internal(env)' failed. qemu-system-arm: /home/me/qemu/target/arm/helper.c:11359: cpu_get_tb_cpu_st= ate: Assertion `flags =3D=3D rebuild_hflags_internal(env)' failed. qemu-system-arm: /home/me/qemu/target/arm/helper.c:11359: cpu_get_tb_cpu_st= ate: Assertion `flags =3D=3D rebuild_hflags_internal(env)' failed. Aborted (core dumped) $ git describe v4.2.0

What should be the next step? Should = this be reported as a bug?

Regards,
Niek=

On Tue, Dec 10, 2019 at 9:12 PM Niek Linnenbank <nieklinnenbank@gmail.com> wrote= :
Hi Philippe,

On Tue, Dec 10, 2019 at 9:26 AM Philippe Mathieu-Da= ud=C3=A9 <philmd@= redhat.com> wrote:
On 12/9/19 10:37 PM, Niek Linnenbank wrote:
> Hi Philippe,
>
> On Tue, Dec 3, 2019 at 9:47 AM Philippe Mathieu-Daud=C3=A9 <philmd@redhat.com
> <mailto:phil= md@redhat.com>> wrote:
>
>=C2=A0 =C2=A0 =C2=A0On 12/2/19 10:09 PM, Niek Linnenbank wrote:
>=C2=A0 =C2=A0 =C2=A0 > Dear QEMU developers,
>=C2=A0 =C2=A0 =C2=A0 >
>=C2=A0 =C2=A0 =C2=A0 > Hereby I would like to contribute the followi= ng set of patches to
>=C2=A0 =C2=A0 =C2=A0QEMU
>=C2=A0 =C2=A0 =C2=A0 > which add support for the Allwinner H3 System= on Chip and the
>=C2=A0 =C2=A0 =C2=A0 > Orange Pi PC machine. The following features = and devices are
>=C2=A0 =C2=A0 =C2=A0supported:
>=C2=A0 =C2=A0 =C2=A0 >
>=C2=A0 =C2=A0 =C2=A0 >=C2=A0 =C2=A0* SMP (Quad Core Cortex A7)
>=C2=A0 =C2=A0 =C2=A0 >=C2=A0 =C2=A0* Generic Interrupt Controller co= nfiguration
>=C2=A0 =C2=A0 =C2=A0 >=C2=A0 =C2=A0* SRAM mappings
>=C2=A0 =C2=A0 =C2=A0 >=C2=A0 =C2=A0* Timer device (re-used from Allw= inner A10)
>=C2=A0 =C2=A0 =C2=A0 >=C2=A0 =C2=A0* UART
>=C2=A0 =C2=A0 =C2=A0 >=C2=A0 =C2=A0* SD/MMC storage controller
>=C2=A0 =C2=A0 =C2=A0 >=C2=A0 =C2=A0* EMAC ethernet connectivity
>=C2=A0 =C2=A0 =C2=A0 >=C2=A0 =C2=A0* USB 2.0 interfaces
>=C2=A0 =C2=A0 =C2=A0 >=C2=A0 =C2=A0* Clock Control Unit
>=C2=A0 =C2=A0 =C2=A0 >=C2=A0 =C2=A0* System Control module
>=C2=A0 =C2=A0 =C2=A0 >=C2=A0 =C2=A0* Security Identifier device
>
>=C2=A0 =C2=A0 =C2=A0Awesome!
>
>=C2=A0 =C2=A0 =C2=A0 > Functionality related to graphical output suc= h as HDMI, GPU,
>=C2=A0 =C2=A0 =C2=A0 > Display Engine and audio are not included. Re= cently released
>=C2=A0 =C2=A0 =C2=A0 > mainline Linux kernels (4.19 up to latest mas= ter) and mainline U-Boot
>=C2=A0 =C2=A0 =C2=A0 > are known to work. The SD/MMC code is tested = using bonnie++ and
>=C2=A0 =C2=A0 =C2=A0 > various tools such as fsck, dd and fdisk. The= EMAC is verified
>=C2=A0 =C2=A0 =C2=A0with iperf3
>=C2=A0 =C2=A0 =C2=A0 > using -netdev socket.
>=C2=A0 =C2=A0 =C2=A0 >
>=C2=A0 =C2=A0 =C2=A0 > To build a Linux mainline kernel that can be = booted by the Orange
>=C2=A0 =C2=A0 =C2=A0Pi PC
>=C2=A0 =C2=A0 =C2=A0 > machine, simply configure the kernel using th= e sunxi_defconfig
>=C2=A0 =C2=A0 =C2=A0configuration:
>=C2=A0 =C2=A0 =C2=A0 >=C2=A0 =C2=A0$ ARCH=3Darm CROSS_COMPILE=3Darm-= linux-gnueabi- make mrproper
>=C2=A0 =C2=A0 =C2=A0 >=C2=A0 =C2=A0$ ARCH=3Darm CROSS_COMPILE=3Darm-= linux-gnueabi- make sunxi_defconfig
>=C2=A0 =C2=A0 =C2=A0 >
>=C2=A0 =C2=A0 =C2=A0 > To be able to use USB storage, you need to ma= nually enable the
>=C2=A0 =C2=A0 =C2=A0corresponding
>=C2=A0 =C2=A0 =C2=A0 > configuration item. Start the kconfig configu= ration tool:
>=C2=A0 =C2=A0 =C2=A0 >=C2=A0 =C2=A0$ ARCH=3Darm CROSS_COMPILE=3Darm-= linux-gnueabi- make menuconfig
>=C2=A0 =C2=A0 =C2=A0 >
>=C2=A0 =C2=A0 =C2=A0 > Navigate to the following item, enable it and= save your
>=C2=A0 =C2=A0 =C2=A0configuration:
>=C2=A0 =C2=A0 =C2=A0 >=C2=A0 =C2=A0Device Drivers > USB support &= gt; USB Mass Storage support
>=C2=A0 =C2=A0 =C2=A0 >
>=C2=A0 =C2=A0 =C2=A0 > Build the Linux kernel with:
>=C2=A0 =C2=A0 =C2=A0 >=C2=A0 =C2=A0$ ARCH=3Darm CROSS_COMPILE=3Darm-= linux-gnueabi- make -j5
>=C2=A0 =C2=A0 =C2=A0 >
>=C2=A0 =C2=A0 =C2=A0 > To boot the newly build linux kernel in QEMU = with the Orange Pi
>=C2=A0 =C2=A0 =C2=A0PC machine, use:
>=C2=A0 =C2=A0 =C2=A0 >=C2=A0 =C2=A0$ qemu-system-arm -M orangepi -m = 512 -nic user -nographic \
>=C2=A0 =C2=A0 =C2=A0 >=C2=A0 =C2=A0 =C2=A0 =C2=A0-kernel /path/to/li= nux/arch/arm/boot/zImage \
>=C2=A0 =C2=A0 =C2=A0 >=C2=A0 =C2=A0 =C2=A0 =C2=A0-append 'consol= e=3DttyS0,115200' \
>=C2=A0 =C2=A0 =C2=A0 >=C2=A0 =C2=A0 =C2=A0 =C2=A0-dtb /path/to/linux= /arch/arm/boot/dts/sun8i-h3-orangepi-pc.dtb
>=C2=A0 =C2=A0 =C2=A0 >
>=C2=A0 =C2=A0 =C2=A0 > Note that this kernel does not have a root fi= lesystem. You may
>=C2=A0 =C2=A0 =C2=A0provide it
>=C2=A0 =C2=A0 =C2=A0 > with an official Orange Pi PC image [1] eithe= r as an SD card or as
>=C2=A0 =C2=A0 =C2=A0 > USB mass storage. To boot using the Orange Pi= PC Debian image on
>=C2=A0 =C2=A0 =C2=A0SD card,
>=C2=A0 =C2=A0 =C2=A0 > simply add the -sd argument and provide the p= roper root=3D kernel
>=C2=A0 =C2=A0 =C2=A0parameter:
>=C2=A0 =C2=A0 =C2=A0 >=C2=A0 =C2=A0$ qemu-system-arm -M orangepi -m = 512 -nic user -nographic \
>=C2=A0 =C2=A0 =C2=A0 >=C2=A0 =C2=A0 =C2=A0 =C2=A0-kernel /path/to/li= nux/arch/arm/boot/zImage \
>=C2=A0 =C2=A0 =C2=A0 >=C2=A0 =C2=A0 =C2=A0 =C2=A0-append 'consol= e=3DttyS0,115200 root=3D/dev/mmcblk0p2' \
>=C2=A0 =C2=A0 =C2=A0 >=C2=A0 =C2=A0 =C2=A0 =C2=A0-dtb
>=C2=A0 =C2=A0 =C2=A0/path/to/linux/arch/arm/boot/dts/sun8i-h3-orangepi-= pc.dtb \
>=C2=A0 =C2=A0 =C2=A0 >=C2=A0 =C2=A0 =C2=A0 =C2=A0-sd OrangePi_pc_deb= ian_stretch_server_linux5.3.5_v1.0.img
>=C2=A0 =C2=A0 =C2=A0 >
>=C2=A0 =C2=A0 =C2=A0 > Alternatively, you can also choose to build a= nd boot a recent
>=C2=A0 =C2=A0 =C2=A0buildroot [2]
>=C2=A0 =C2=A0 =C2=A0 > using the orangepi_pc_defconfig or Armbian im= age [3] for Orange
>=C2=A0 =C2=A0 =C2=A0Pi PC.
>
>=C2=A0 =C2=A0 =C2=A0Richard, trying the Armbian image from
>=C2=A0 =C2=A0 =C2=A0https://apt.armbian.c= om/pool/main/l/linux-4.20.7-sunxi/ I get:
>
>=C2=A0 =C2=A0 =C2=A0$ arm-softmmu/qemu-system-arm -M orangepi -m 512 -n= ic user \
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0-append 'console=3DttyS0,115200&#= 39; \
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0-kernel boot/vmlinuz-4.20.7-sunxi \ >=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0-dtb usr/lib/linux-image-dev-sunxi/su= n8i-h3-orangepi-pc.dtb \
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0-serial stdio -d unimp
>=C2=A0 =C2=A0 =C2=A0Uncompressing Linux... done, booting the kernel. >=C2=A0 =C2=A0 =C2=A0rtc: unimplemented device write (size 4, value 0x16= aa0001, offset 0x0)
>=C2=A0 =C2=A0 =C2=A0rtc: unimplemented device read (size 4, offset 0x0)=
>=C2=A0 =C2=A0 =C2=A0rtc: unimplemented device read (size 4, offset 0x0)=
>=C2=A0 =C2=A0 =C2=A0rtc: unimplemented device read (size 4, offset 0x8)=
>=C2=A0 =C2=A0 =C2=A0qemu-system-arm: target/arm/helper.c:11359: cpu_get= _tb_cpu_state:
>=C2=A0 =C2=A0 =C2=A0Assertion `flags =3D=3D rebuild_hflags_internal(env= )' failed.
>=C2=A0 =C2=A0 =C2=A0Aborted (core dumped)
>
>
> I'm trying to reproduce the error you reported here with my patch = set on
> latest master,
> but so far without any result. The host OS I'm using is Ubuntu 18.= 04.3
> LTS on x86_64.
> I ran several times using the same 4.20.7-sunxi kernel and same comman= d
> line.
>
> Some questions that might help:
> 1) Are there any specific steps you did in order to produce this error= ?

I build QEMU with:

./configure --enable-trace-backends=3Dlog --extra-cflags=3D-ggdb --enable-d= ebug

> 2) Could this be a known / existing issue?
> 3) How many times did you see this error?

Always

> 4) Are you also using Ubuntu 18.04.3 LTS on x86_64, or a different hos= t OS?

Host is Fedora 30.

OK thanks, I will tr= y again using the info above after I finished reworking the other patch com= ments.

Niek
=C2=A0

>
> Regards,
> Niek



--
Niek Linnenbank



--
Niek Linnenbank

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[83.42.66.34]) by smtp.gmail.com with ESMTPSA id v188sm7985013wma.10.2019.12.12.15.25.45 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 12 Dec 2019 15:25:45 -0800 (PST) Subject: Re: [PATCH 00/10] Add Allwinner H3 SoC and Orange Pi PC Machine To: Niek Linnenbank , =?UTF-8?Q?Alex_Benn=c3=a9e?= Cc: QEMU Developers , Beniamino Galvani , Peter Maydell , qemu-arm , Richard Henderson References: <20191202210947.3603-1-nieklinnenbank@gmail.com> <74df65db-1f84-62ba-6d01-edf765fd1dc2@redhat.com> From: =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= Message-ID: <7ed70514-e67e-9403-63b3-5a81c59fe952@redhat.com> Date: Fri, 13 Dec 2019 00:25:44 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.2.2 MIME-Version: 1.0 In-Reply-To: Content-Language: en-US X-MC-Unique: EXUoT4qTN3Gv0UcSJyfAZw-1 X-Mimecast-Spam-Score: 0 Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 207.211.31.120 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 12 Dec 2019 23:25:55 -0000 Cc'ing Alex. On 12/13/19 12:07 AM, Niek Linnenbank wrote: > Hi Philippe, >=20 > I have discovered that the hflags assertion error you reported is not=20 > caused by the Allwinner H3 > patches but actually an existing problem. What I did is to use the=20 > latest master (v4.2.0 tag) without any patches applied. > and tried to boot the raspi2 machine with and without debugging enabled.= =20 > Without debuggin, the raspi2 > machine runs fine and can boot the 5.4.2 linux kernel. With debugging=20 > enabled, the same hflags error shows. This might be the same bug I hit last week... Alex suggested a patch: https://www.mail-archive.com/qemu-devel@nongnu.org/msg664500.html Do you mind to try it? If it still fails, you might also add this one on top: https://www.mail-archive.com/qemu-devel@nongnu.org/msg663843.html and report the error. >=20 > To reproduce it, build Linux 5.4.2 with the bmc2835_defconfig: >=20 > $ ARCH=3Darm CROSS_COMPILE=3Darm-linux-gnueabi- make mrproper > $ ARCH=3Darm CROSS_COMPILE=3Darm-linux-gnueabi- make bcm2835_defconfig > $ ARCH=3Darm CROSS_COMPILE=3Darm-linux-gnueabi- make -j5 > ... >=20 > First build QEMU without debugging and try to boot linux: > $ ./configure --target-list=3Darm-softmmu; make clean; make -j5 > $ ./arm-softmmu/qemu-system-arm -M raspi2 \ > -kernel $HOME/linux-5.4.2/arch/arm/boot/zImage \ > -append 'console=3DttyAMA0,115200 earlyprintk debug' \ > -dtb $HOME/linux-5.4.2/arch/arm/boot/dts/bcm2836-rpi-2-b.dtb \ > -m 1024 -nographic -s > [ 0.000000] Booting Linux on physical CPU 0x0 > [ 0.000000] Linux version 5.4.2 (me@host) (gcc version 7.4.0 (Ubuntu/L= inaro 7.4.0-1ubuntu1~18.04.1)) #1 Thu Dec 12 22:49:14 CET 2019 > [ 0.000000] CPU: ARMv7 Processor [410fc075] revision 5 (ARMv7), cr=3D1= 0c53c7d > ... >=20 > Then rebuild QEMU with debugging enabled and again try to boot linux: > $ ./configure --target-list=3Darm-softmmu --enable-debug --extra-cflags= =3D-ggdb; make clean; make -j5 > $ ./arm-softmmu/qemu-system-arm -M raspi2 \ > -kernel $HOME/linux-5.4.2/arch/arm/boot/zImage \ > -append 'console=3DttyAMA0,115200 earlyprintk debug' \ > -dtb $HOME/linux-5.4.2/arch/arm/boot/dts/bcm2836-rpi-2-b.dtb \ > -m 1024 -nographic -s > qemu-system-arm: /home/me/qemu/target/arm/helper.c:11359: cpu_get_tb_cpu_= state: Assertion `flags =3D=3D rebuild_hflags_internal(env)' failed. > qemu-system-arm: /home/me/qemu/target/arm/helper.c:11359: cpu_get_tb_cpu_= state: Assertion `flags =3D=3D rebuild_hflags_internal(env)' failed. > qemu-system-arm: /home/me/qemu/target/arm/helper.c:11359: cpu_get_tb_cpu_= state: Assertion `flags =3D=3D rebuild_hflags_internal(env)' failed. > Aborted (core dumped) >=20 > $ git describe > v4.2.0 >=20 >=20 > What should be the next step? Should this be reported as a bug? In this case we might already have the fix, but if Alex patch doesn't=20 help, you are always welcome to open a bug report: https://bugs.launchpad.net/qemu/+filebug This help to have notes/progress gathered. > On Tue, Dec 10, 2019 at 9:12 PM Niek Linnenbank=20 > > wrote: >=20 > Hi Philippe, >=20 > On Tue, Dec 10, 2019 at 9:26 AM Philippe Mathieu-Daud=C3=A9 > > wrote: >=20 > On 12/9/19 10:37 PM, Niek Linnenbank wrote: > > Hi Philippe, > > > > On Tue, Dec 3, 2019 at 9:47 AM Philippe Mathieu-Daud=C3=A9 > > > >> wrote: > > > >=C2=A0 =C2=A0 =C2=A0On 12/2/19 10:09 PM, Niek Linnenbank wrote: > >=C2=A0 =C2=A0 =C2=A0 > Dear QEMU developers, > >=C2=A0 =C2=A0 =C2=A0 > > >=C2=A0 =C2=A0 =C2=A0 > Hereby I would like to contribute the fo= llowing set of > patches to > >=C2=A0 =C2=A0 =C2=A0QEMU > >=C2=A0 =C2=A0 =C2=A0 > which add support for the Allwinner H3 S= ystem on Chip > and the > >=C2=A0 =C2=A0 =C2=A0 > Orange Pi PC machine. The following feat= ures and > devices are > >=C2=A0 =C2=A0 =C2=A0supported: > >=C2=A0 =C2=A0 =C2=A0 > > >=C2=A0 =C2=A0 =C2=A0 >=C2=A0 =C2=A0* SMP (Quad Core Cortex A7) > >=C2=A0 =C2=A0 =C2=A0 >=C2=A0 =C2=A0* Generic Interrupt Controll= er configuration > >=C2=A0 =C2=A0 =C2=A0 >=C2=A0 =C2=A0* SRAM mappings > >=C2=A0 =C2=A0 =C2=A0 >=C2=A0 =C2=A0* Timer device (re-used from= Allwinner A10) > >=C2=A0 =C2=A0 =C2=A0 >=C2=A0 =C2=A0* UART > >=C2=A0 =C2=A0 =C2=A0 >=C2=A0 =C2=A0* SD/MMC storage controller > >=C2=A0 =C2=A0 =C2=A0 >=C2=A0 =C2=A0* EMAC ethernet connectivity > >=C2=A0 =C2=A0 =C2=A0 >=C2=A0 =C2=A0* USB 2.0 interfaces > >=C2=A0 =C2=A0 =C2=A0 >=C2=A0 =C2=A0* Clock Control Unit > >=C2=A0 =C2=A0 =C2=A0 >=C2=A0 =C2=A0* System Control module > >=C2=A0 =C2=A0 =C2=A0 >=C2=A0 =C2=A0* Security Identifier device > > > >=C2=A0 =C2=A0 =C2=A0Awesome! > > > >=C2=A0 =C2=A0 =C2=A0 > Functionality related to graphical outpu= t such as > HDMI, GPU, > >=C2=A0 =C2=A0 =C2=A0 > Display Engine and audio are not include= d. Recently > released > >=C2=A0 =C2=A0 =C2=A0 > mainline Linux kernels (4.19 up to lates= t master) and > mainline U-Boot > >=C2=A0 =C2=A0 =C2=A0 > are known to work. The SD/MMC code is te= sted using > bonnie++ and > >=C2=A0 =C2=A0 =C2=A0 > various tools such as fsck, dd and fdisk= . The EMAC is > verified > >=C2=A0 =C2=A0 =C2=A0with iperf3 > >=C2=A0 =C2=A0 =C2=A0 > using -netdev socket. > >=C2=A0 =C2=A0 =C2=A0 > > >=C2=A0 =C2=A0 =C2=A0 > To build a Linux mainline kernel that ca= n be booted by > the Orange > >=C2=A0 =C2=A0 =C2=A0Pi PC > >=C2=A0 =C2=A0 =C2=A0 > machine, simply configure the kernel usi= ng the > sunxi_defconfig > >=C2=A0 =C2=A0 =C2=A0configuration: > >=C2=A0 =C2=A0 =C2=A0 >=C2=A0 =C2=A0$ ARCH=3Darm CROSS_COMPILE= =3Darm-linux-gnueabi- make > mrproper > >=C2=A0 =C2=A0 =C2=A0 >=C2=A0 =C2=A0$ ARCH=3Darm CROSS_COMPILE= =3Darm-linux-gnueabi- make > sunxi_defconfig > >=C2=A0 =C2=A0 =C2=A0 > > >=C2=A0 =C2=A0 =C2=A0 > To be able to use USB storage, you need = to manually > enable the > >=C2=A0 =C2=A0 =C2=A0corresponding > >=C2=A0 =C2=A0 =C2=A0 > configuration item. Start the kconfig co= nfiguration tool: > >=C2=A0 =C2=A0 =C2=A0 >=C2=A0 =C2=A0$ ARCH=3Darm CROSS_COMPILE= =3Darm-linux-gnueabi- make > menuconfig > >=C2=A0 =C2=A0 =C2=A0 > > >=C2=A0 =C2=A0 =C2=A0 > Navigate to the following item, enable i= t and save your > >=C2=A0 =C2=A0 =C2=A0configuration: > >=C2=A0 =C2=A0 =C2=A0 >=C2=A0 =C2=A0Device Drivers > USB support= > USB Mass Storage support > >=C2=A0 =C2=A0 =C2=A0 > > >=C2=A0 =C2=A0 =C2=A0 > Build the Linux kernel with: > >=C2=A0 =C2=A0 =C2=A0 >=C2=A0 =C2=A0$ ARCH=3Darm CROSS_COMPILE= =3Darm-linux-gnueabi- make -j5 > >=C2=A0 =C2=A0 =C2=A0 > > >=C2=A0 =C2=A0 =C2=A0 > To boot the newly build linux kernel in = QEMU with the > Orange Pi > >=C2=A0 =C2=A0 =C2=A0PC machine, use: > >=C2=A0 =C2=A0 =C2=A0 >=C2=A0 =C2=A0$ qemu-system-arm -M orangep= i -m 512 -nic user > -nographic \ > >=C2=A0 =C2=A0 =C2=A0 >=C2=A0 =C2=A0 =C2=A0 =C2=A0-kernel /path/= to/linux/arch/arm/boot/zImage \ > >=C2=A0 =C2=A0 =C2=A0 >=C2=A0 =C2=A0 =C2=A0 =C2=A0-append 'conso= le=3DttyS0,115200' \ > >=C2=A0 =C2=A0 =C2=A0 >=C2=A0 =C2=A0 =C2=A0 =C2=A0-dtb > /path/to/linux/arch/arm/boot/dts/sun8i-h3-orangepi-pc.dtb > >=C2=A0 =C2=A0 =C2=A0 > > >=C2=A0 =C2=A0 =C2=A0 > Note that this kernel does not have a ro= ot filesystem. > You may > >=C2=A0 =C2=A0 =C2=A0provide it > >=C2=A0 =C2=A0 =C2=A0 > with an official Orange Pi PC image [1] = either as an > SD card or as > >=C2=A0 =C2=A0 =C2=A0 > USB mass storage. To boot using the Oran= ge Pi PC > Debian image on > >=C2=A0 =C2=A0 =C2=A0SD card, > >=C2=A0 =C2=A0 =C2=A0 > simply add the -sd argument and provide = the proper > root=3D kernel > >=C2=A0 =C2=A0 =C2=A0parameter: > >=C2=A0 =C2=A0 =C2=A0 >=C2=A0 =C2=A0$ qemu-system-arm -M orangep= i -m 512 -nic user > -nographic \ > >=C2=A0 =C2=A0 =C2=A0 >=C2=A0 =C2=A0 =C2=A0 =C2=A0-kernel /path/= to/linux/arch/arm/boot/zImage \ > >=C2=A0 =C2=A0 =C2=A0 >=C2=A0 =C2=A0 =C2=A0 =C2=A0-append 'conso= le=3DttyS0,115200 root=3D/dev/mmcblk0p2' \ > >=C2=A0 =C2=A0 =C2=A0 >=C2=A0 =C2=A0 =C2=A0 =C2=A0-dtb > >=C2=A0 =C2=A0 =C2=A0/path/to/linux/arch/arm/boot/dts/sun8i-h3-o= rangepi-pc.dtb \ > >=C2=A0 =C2=A0 =C2=A0 >=C2=A0 =C2=A0 =C2=A0 =C2=A0-sd > OrangePi_pc_debian_stretch_server_linux5.3.5_v1.0.img > >=C2=A0 =C2=A0 =C2=A0 > > >=C2=A0 =C2=A0 =C2=A0 > Alternatively, you can also choose to bu= ild and boot a > recent > >=C2=A0 =C2=A0 =C2=A0buildroot [2] > >=C2=A0 =C2=A0 =C2=A0 > using the orangepi_pc_defconfig or Armbi= an image [3] > for Orange > >=C2=A0 =C2=A0 =C2=A0Pi PC. > > > >=C2=A0 =C2=A0 =C2=A0Richard, trying the Armbian image from > > https://apt.armbian.com/pool/main/l/linux-4.20.7-sunxi/ I get: > > > >=C2=A0 =C2=A0 =C2=A0$ arm-softmmu/qemu-system-arm -M orangepi -= m 512 -nic user \ > >=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0-append 'console=3DttyS0,1152= 00' \ > >=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0-kernel boot/vmlinuz-4.20.7-s= unxi \ > >=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0-dtb > usr/lib/linux-image-dev-sunxi/sun8i-h3-orangepi-pc.dtb \ > >=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0-serial stdio -d unimp > >=C2=A0 =C2=A0 =C2=A0Uncompressing Linux... done, booting the ke= rnel. > >=C2=A0 =C2=A0 =C2=A0rtc: unimplemented device write (size 4, va= lue > 0x16aa0001, offset 0x0) > >=C2=A0 =C2=A0 =C2=A0rtc: unimplemented device read (size 4, off= set 0x0) > >=C2=A0 =C2=A0 =C2=A0rtc: unimplemented device read (size 4, off= set 0x0) > >=C2=A0 =C2=A0 =C2=A0rtc: unimplemented device read (size 4, off= set 0x8) > >=C2=A0 =C2=A0 =C2=A0qemu-system-arm: target/arm/helper.c:11359: > cpu_get_tb_cpu_state: > >=C2=A0 =C2=A0 =C2=A0Assertion `flags =3D=3D rebuild_hflags_inte= rnal(env)' failed. > >=C2=A0 =C2=A0 =C2=A0Aborted (core dumped) > > > > > > I'm trying to reproduce the error you reported here with my > patch set on > > latest master, > > but so far without any result. The host OS I'm using is > Ubuntu 18.04.3 > > LTS on x86_64. > > I ran several times using the same 4.20.7-sunxi kernel and > same command > > line. > > > > Some questions that might help: > > 1) Are there any specific steps you did in order to produce > this error? >=20 > I build QEMU with: >=20 > ./configure --enable-trace-backends=3Dlog --extra-cflags=3D-ggdb > --enable-debug >=20 > > 2) Could this be a known / existing issue? > > 3) How many times did you see this error? >=20 > Always >=20 > > 4) Are you also using Ubuntu 18.04.3 LTS on x86_64, or a > different host OS? >=20 > Host is Fedora 30. >=20 >=20 > OK thanks, I will try again using the info above after I finished > reworking the other patch comments. >=20 > Niek From MAILER-DAEMON Thu Dec 12 18:56:55 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1ifYKF-0006l6-7U for mharc-qemu-arm@gnu.org; Thu, 12 Dec 2019 18:56:55 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:38738) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ifYK8-0006iG-Ha for qemu-arm@nongnu.org; Thu, 12 Dec 2019 18:56:53 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ifYK4-0002mE-1c for qemu-arm@nongnu.org; Thu, 12 Dec 2019 18:56:48 -0500 Received: from us-smtp-delivery-1.mimecast.com ([207.211.31.120]:22628 helo=us-smtp-1.mimecast.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1ifYK3-0002kn-Ss for qemu-arm@nongnu.org; Thu, 12 Dec 2019 18:56:43 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1576195003; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=CJPa9AQr5Qkt1HBH8pTks8XrKcLWox/hWmcu+vSRJ+U=; b=dznRRO52Qo+PiONZx3uJe/9ZOKL37u+PqtBGild+Tvp3BB/mmovi7edgBiE5Ygf7e5LVkp CbFG0GlFNr5T7IPkD7CxYn7i/X8AMQ0rKdgmEpj6ucxDS8wkIDHKTp+7v8AME7rRJdVSpS HR6/iOOAV7ma6gn1IyEl/Mu5W08uR6w= Received: from mail-wm1-f70.google.com (mail-wm1-f70.google.com [209.85.128.70]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-55-08L9fNkNOta0WnuzGmX83g-1; Thu, 12 Dec 2019 18:56:37 -0500 Received: by mail-wm1-f70.google.com with SMTP id o205so1429894wmo.5 for ; Thu, 12 Dec 2019 15:56:36 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:subject:to:cc:references:from:message-id:date :user-agent:mime-version:in-reply-to:content-language :content-transfer-encoding; bh=PR737s4Q8yWxu6WkWx+coGUZJ7eb4AmfCR+hVn5wWN8=; b=ns22c76UgTL10TPD6wpYyluaPVJtzjdOHvn9tTaLMl+T/Rd6xWQUNmfBnPKe1WzE1s GSWBnCISCKj+WtNglXIHPiavFie9ArujFmiNwU9ilODXc5BwEXfUAV9Gl4FkTzWRQQuN KnCv65ZgwxZviNAOcKlYX3Vh29xDkvR8md8I/IckfszdVA92jTuvI7L+rdc39LK/X3qI nlU0R+vmpglLHJS6yavRF0VtX6WqYYNnmssZIUbamRZALfE9T6SjOJdGz2K82WYdF4uo Sc7YrzWhYXtya8KQXoDbFupKyLKXaJgIfXXXFgyAdwy2HcGmDS92qpZ25da1uLvix7SX PnqQ== X-Gm-Message-State: APjAAAWh5kHQaqGCyC/L6Kwx7M6LxF9LS9gjcX7c0MYYR+5Oscmc+LRZ 15KwHi1/dXq9BqZTnEOEkY1mkwg0kGRgp+p0vNX3u8T+JDaZQPr+hrIxFuPU+5oiXZaV5yEAUHm sxVSDjjujoYq4 X-Received: by 2002:a05:600c:23c9:: with SMTP id p9mr1351821wmb.160.1576194995512; Thu, 12 Dec 2019 15:56:35 -0800 (PST) X-Google-Smtp-Source: APXvYqxb2qr2YofGbEw2rE0wKxY/gDMZiqV4K9J+b+Qg9WH4KUheucdsfZ2yNIiRHZNTgLluHoAeYQ== X-Received: by 2002:a05:600c:23c9:: with SMTP id p9mr1351784wmb.160.1576194994943; Thu, 12 Dec 2019 15:56:34 -0800 (PST) Received: from [192.168.1.35] (34.red-83-42-66.dynamicip.rima-tde.net. [83.42.66.34]) by smtp.gmail.com with ESMTPSA id m7sm7980773wma.39.2019.12.12.15.56.33 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 12 Dec 2019 15:56:34 -0800 (PST) Subject: Re: [PATCH 09/10] arm: allwinner-h3: add SD/MMC host controller To: Niek Linnenbank , QEMU Developers Cc: qemu-arm , Peter Maydell , Beniamino Galvani References: <20191202210947.3603-1-nieklinnenbank@gmail.com> <20191202210947.3603-10-nieklinnenbank@gmail.com> From: =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= Message-ID: <6bee15d7-7d80-0709-ac90-ef2052b39329@redhat.com> Date: Fri, 13 Dec 2019 00:56:33 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.2.2 MIME-Version: 1.0 In-Reply-To: Content-Language: en-US X-MC-Unique: 08L9fNkNOta0WnuzGmX83g-1 X-Mimecast-Spam-Score: 0 Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 207.211.31.120 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 12 Dec 2019 23:56:53 -0000 Hi Niek, On 12/11/19 11:34 PM, Niek Linnenbank wrote: > Ping! >=20 > Anyone would like to comment on this driver? >=20 > I finished the rework on all previous comments in this series. >=20 > Currently debugging the hflags error reported by Philippe. > After that, I'm ready to send out v2 of these patches. >=20 > Regards, > Niek >=20 > On Mon, Dec 2, 2019 at 10:10 PM Niek Linnenbank=20 > > wrote: >=20 > The Allwinner H3 System on Chip contains an integrated storage > controller for Secure Digital (SD) and Multi Media Card (MMC) > interfaces. This commit adds support for the Allwinner H3 > SD/MMC storage controller with the following emulated features: >=20 > =C2=A0* DMA transfers > =C2=A0* Direct FIFO I/O > =C2=A0* Short/Long format command responses > =C2=A0* Auto-Stop command (CMD12) > =C2=A0* Insert & remove card detection >=20 > Signed-off-by: Niek Linnenbank > > --- > =C2=A0hw/arm/allwinner-h3.c=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0|=C2=A0 20 + > =C2=A0hw/arm/orangepi.c=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0|=C2=A0 17 + > =C2=A0hw/sd/Makefile.objs=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0|=C2=A0 =C2=A01 + > =C2=A0hw/sd/allwinner-h3-sdhost.c=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0|= 791 ++++++++++++++++++++++++++++ > =C2=A0hw/sd/trace-events=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 |=C2=A0 =C2=A07 + > =C2=A0include/hw/arm/allwinner-h3.h=C2=A0 =C2=A0 =C2=A0 =C2=A0|=C2= =A0 =C2=A02 + > =C2=A0include/hw/sd/allwinner-h3-sdhost.h |=C2=A0 73 +++ > =C2=A07 files changed, 911 insertions(+) > =C2=A0create mode 100644 hw/sd/allwinner-h3-sdhost.c > =C2=A0create mode 100644 include/hw/sd/allwinner-h3-sdhost.h >=20 > diff --git a/hw/arm/allwinner-h3.c b/hw/arm/allwinner-h3.c > index 4fc4c8c725..c2972caf88 100644 > --- a/hw/arm/allwinner-h3.c > +++ b/hw/arm/allwinner-h3.c > @@ -50,6 +50,9 @@ static void aw_h3_init(Object *obj) >=20 > =C2=A0 =C2=A0 =C2=A0sysbus_init_child_obj(obj, "sid", &s->sid, sizeo= f(s->sid), > =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0TYPE_AW_H3_SID); > + > +=C2=A0 =C2=A0 sysbus_init_child_obj(obj, "mmc0", &s->mmc0, sizeof(s-= >mmc0), > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 TYPE_AW_H3_SDHOST); > =C2=A0} >=20 > =C2=A0static void aw_h3_realize(DeviceState *dev, Error **errp) > @@ -217,6 +220,23 @@ static void aw_h3_realize(DeviceState *dev, > Error **errp) > =C2=A0 =C2=A0 =C2=A0} > =C2=A0 =C2=A0 =C2=A0sysbus_mmio_map(SYS_BUS_DEVICE(&s->sid), 0, AW_H= 3_SID_BASE); >=20 > +=C2=A0 =C2=A0 /* SD/MMC */ > +=C2=A0 =C2=A0 object_property_set_bool(OBJECT(&s->mmc0), true, "real= ized", &err); > +=C2=A0 =C2=A0 if (err !=3D NULL) { > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 error_propagate(errp, err); > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 return; > +=C2=A0 =C2=A0 } > +=C2=A0 =C2=A0 sysbusdev =3D SYS_BUS_DEVICE(&s->mmc0); > +=C2=A0 =C2=A0 sysbus_mmio_map(sysbusdev, 0, AW_H3_MMC0_BASE); > +=C2=A0 =C2=A0 sysbus_connect_irq(sysbusdev, 0, s->irq[AW_H3_GIC_SPI_= MMC0]); > + > +=C2=A0 =C2=A0 object_property_add_alias(OBJECT(s), "sd-bus", OBJECT(= &s->mmc0), > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 "sd-bus", &err); > +=C2=A0 =C2=A0 if (err) { > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 error_propagate(errp, err); > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 return; > +=C2=A0 =C2=A0 } > + > =C2=A0 =C2=A0 =C2=A0/* Universal Serial Bus */ > =C2=A0 =C2=A0 =C2=A0sysbus_create_simple(TYPE_AW_H3_EHCI, AW_H3_EHCI= 0_BASE, > =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 s->irq[AW_H3_GIC_SPI_EHCI0]); > diff --git a/hw/arm/orangepi.c b/hw/arm/orangepi.c > index 5ef2735f81..dee3efaf08 100644 > --- a/hw/arm/orangepi.c > +++ b/hw/arm/orangepi.c > @@ -39,6 +39,10 @@ typedef struct OrangePiState { > =C2=A0static void orangepi_init(MachineState *machine) > =C2=A0{ > =C2=A0 =C2=A0 =C2=A0OrangePiState *s =3D g_new(OrangePiState, 1); > +=C2=A0 =C2=A0 DriveInfo *di; > +=C2=A0 =C2=A0 BlockBackend *blk; > +=C2=A0 =C2=A0 BusState *bus; > +=C2=A0 =C2=A0 DeviceState *carddev; > =C2=A0 =C2=A0 =C2=A0Error *err =3D NULL; >=20 > =C2=A0 =C2=A0 =C2=A0s->h3 =3D AW_H3(object_new(TYPE_AW_H3)); > @@ -64,6 +68,18 @@ static void orangepi_init(MachineState *machine) > =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0exit(1); > =C2=A0 =C2=A0 =C2=A0} >=20 > +=C2=A0 =C2=A0 /* Create and plug in the SD card */ > +=C2=A0 =C2=A0 di =3D drive_get_next(IF_SD); > +=C2=A0 =C2=A0 blk =3D di ? blk_by_legacy_dinfo(di) : NULL; > +=C2=A0 =C2=A0 bus =3D qdev_get_child_bus(DEVICE(s->h3), "sd-bus"); > +=C2=A0 =C2=A0 if (bus =3D=3D NULL) { > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 error_report("No SD/MMC found in H3 obje= ct"); > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 exit(1); > +=C2=A0 =C2=A0 } Your device always creates a bus, so I don't think the if(bus) check is=20 worthwhile. Eventually use an assert(bus)? > +=C2=A0 =C2=A0 carddev =3D qdev_create(bus, TYPE_SD_CARD); > +=C2=A0 =C2=A0 qdev_prop_set_drive(carddev, "drive", blk, &error_fata= l); > +=C2=A0 =C2=A0 object_property_set_bool(OBJECT(carddev), true, "reali= zed", > &error_fatal); > + > =C2=A0 =C2=A0 =C2=A0/* RAM */ > =C2=A0 =C2=A0 =C2=A0memory_region_allocate_system_memory(&s->sdram, = NULL, > "orangepi.ram", > =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 machine->ram_size); > @@ -80,6 +96,7 @@ static void orangepi_machine_init(MachineClass *mc) > =C2=A0{ > =C2=A0 =C2=A0 =C2=A0mc->desc =3D "Orange Pi PC"; > =C2=A0 =C2=A0 =C2=A0mc->init =3D orangepi_init; > +=C2=A0 =C2=A0 mc->block_default_type =3D IF_SD; > =C2=A0 =C2=A0 =C2=A0mc->units_per_default_bus =3D 1; > =C2=A0 =C2=A0 =C2=A0mc->min_cpus =3D AW_H3_NUM_CPUS; > =C2=A0 =C2=A0 =C2=A0mc->max_cpus =3D AW_H3_NUM_CPUS; > diff --git a/hw/sd/Makefile.objs b/hw/sd/Makefile.objs > index a884c238df..e7cc5ab739 100644 > --- a/hw/sd/Makefile.objs > +++ b/hw/sd/Makefile.objs > @@ -4,6 +4,7 @@ common-obj-$(CONFIG_SD) +=3D sd.o core.o sdmmc-intern= al.o > =C2=A0common-obj-$(CONFIG_SDHCI) +=3D sdhci.o > =C2=A0common-obj-$(CONFIG_SDHCI_PCI) +=3D sdhci-pci.o >=20 > +obj-$(CONFIG_ALLWINNER_H3) +=3D allwinner-h3-sdhost.o > =C2=A0obj-$(CONFIG_MILKYMIST) +=3D milkymist-memcard.o > =C2=A0obj-$(CONFIG_OMAP) +=3D omap_mmc.o > =C2=A0obj-$(CONFIG_PXA2XX) +=3D pxa2xx_mmci.o > diff --git a/hw/sd/allwinner-h3-sdhost.c b/hw/sd/allwinner-h3-sdhost.= c > new file mode 100644 > index 0000000000..26e113a144 > --- /dev/null > +++ b/hw/sd/allwinner-h3-sdhost.c > @@ -0,0 +1,791 @@ > +/* > + * Allwinner H3 SD Host Controller emulation > + * > + * Copyright (C) 2019 Niek Linnenbank > > + * > + * This program is free software: you can redistribute it and/or mod= ify > + * it under the terms of the GNU General Public License as published= by > + * the Free Software Foundation, either version 2 of the License, or > + * (at your option) any later version. > + * > + * This program is distributed in the hope that it will be useful, > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.=C2=A0 See th= e > + * GNU General Public License for more details. > + * > + * You should have received a copy of the GNU General Public License > + * along with this program.=C2=A0 If not, see > . > + */ > + > +#include "qemu/osdep.h" > +#include "qemu/log.h" > +#include "qemu/module.h" > +#include "sysemu/blockdev.h" > +#include "hw/irq.h" > +#include "hw/sd/allwinner-h3-sdhost.h" > +#include "migration/vmstate.h" > +#include "trace.h" > + > +#define TYPE_AW_H3_SDHOST_BUS "allwinner-h3-sdhost-bus" > +#define AW_H3_SDHOST_BUS(obj) \ > +=C2=A0 =C2=A0 OBJECT_CHECK(SDBus, (obj), TYPE_AW_H3_SDHOST_BUS) > + > +/* SD Host register offsets */ > +#define REG_SD_GCTL=C2=A0 =C2=A0 =C2=A0 =C2=A0 (0x00)=C2=A0 /* Globa= l Control */ > +#define REG_SD_CKCR=C2=A0 =C2=A0 =C2=A0 =C2=A0 (0x04)=C2=A0 /* Clock= Control */ > +#define REG_SD_TMOR=C2=A0 =C2=A0 =C2=A0 =C2=A0 (0x08)=C2=A0 /* Timeo= ut */ > +#define REG_SD_BWDR=C2=A0 =C2=A0 =C2=A0 =C2=A0 (0x0C)=C2=A0 /* Bus W= idth */ > +#define REG_SD_BKSR=C2=A0 =C2=A0 =C2=A0 =C2=A0 (0x10)=C2=A0 /* Block= Size */ > +#define REG_SD_BYCR=C2=A0 =C2=A0 =C2=A0 =C2=A0 (0x14)=C2=A0 /* Byte = Count */ > +#define REG_SD_CMDR=C2=A0 =C2=A0 =C2=A0 =C2=A0 (0x18)=C2=A0 /* Comma= nd */ > +#define REG_SD_CAGR=C2=A0 =C2=A0 =C2=A0 =C2=A0 (0x1C)=C2=A0 /* Comma= nd Argument */ > +#define REG_SD_RESP0=C2=A0 =C2=A0 =C2=A0 =C2=A0(0x20)=C2=A0 /* Respo= nse Zero */ > +#define REG_SD_RESP1=C2=A0 =C2=A0 =C2=A0 =C2=A0(0x24)=C2=A0 /* Respo= nse One */ > +#define REG_SD_RESP2=C2=A0 =C2=A0 =C2=A0 =C2=A0(0x28)=C2=A0 /* Respo= nse Two */ > +#define REG_SD_RESP3=C2=A0 =C2=A0 =C2=A0 =C2=A0(0x2C)=C2=A0 /* Respo= nse Three */ > +#define REG_SD_IMKR=C2=A0 =C2=A0 =C2=A0 =C2=A0 (0x30)=C2=A0 /* Inter= rupt Mask */ > +#define REG_SD_MISR=C2=A0 =C2=A0 =C2=A0 =C2=A0 (0x34)=C2=A0 /* Maske= d Interrupt Status */ > +#define REG_SD_RISR=C2=A0 =C2=A0 =C2=A0 =C2=A0 (0x38)=C2=A0 /* Raw I= nterrupt Status */ > +#define REG_SD_STAR=C2=A0 =C2=A0 =C2=A0 =C2=A0 (0x3C)=C2=A0 /* Statu= s */ > +#define REG_SD_FWLR=C2=A0 =C2=A0 =C2=A0 =C2=A0 (0x40)=C2=A0 /* FIFO = Water Level */ > +#define REG_SD_FUNS=C2=A0 =C2=A0 =C2=A0 =C2=A0 (0x44)=C2=A0 /* FIFO = Function Select */ > +#define REG_SD_DBGC=C2=A0 =C2=A0 =C2=A0 =C2=A0 (0x50)=C2=A0 /* Debug= Enable */ > +#define REG_SD_A12A=C2=A0 =C2=A0 =C2=A0 =C2=A0 (0x58)=C2=A0 /* Auto = command 12 argument */ > +#define REG_SD_NTSR=C2=A0 =C2=A0 =C2=A0 =C2=A0 (0x5C)=C2=A0 /* SD Ne= wTiming Set */ > +#define REG_SD_SDBG=C2=A0 =C2=A0 =C2=A0 =C2=A0 (0x60)=C2=A0 /* SD ne= wTiming Set Debug */ > +#define REG_SD_HWRST=C2=A0 =C2=A0 =C2=A0 =C2=A0(0x78)=C2=A0 /* Hardw= are Reset Register */ > +#define REG_SD_DMAC=C2=A0 =C2=A0 =C2=A0 =C2=A0 (0x80)=C2=A0 /* Inter= nal DMA Controller > Control */ > +#define REG_SD_DLBA=C2=A0 =C2=A0 =C2=A0 =C2=A0 (0x84)=C2=A0 /* Descr= iptor List Base Address */ > +#define REG_SD_IDST=C2=A0 =C2=A0 =C2=A0 =C2=A0 (0x88)=C2=A0 /* Inter= nal DMA Controller Status */ > +#define REG_SD_IDIE=C2=A0 =C2=A0 =C2=A0 =C2=A0 (0x8C)=C2=A0 /* Inter= nal DMA Controller IRQ > Enable */ > +#define REG_SD_THLDC=C2=A0 =C2=A0 =C2=A0 =C2=A0(0x100) /* Card Thres= hold Control */ > +#define REG_SD_DSBD=C2=A0 =C2=A0 =C2=A0 =C2=A0 (0x10C) /* eMMC DDR S= tart Bit Detection > Control */ > +#define REG_SD_RES_CRC=C2=A0 =C2=A0 =C2=A0(0x110) /* Response CRC fr= om card/eMMC */ > +#define REG_SD_DATA7_CRC=C2=A0 =C2=A0(0x114) /* CRC Data 7 from card= /eMMC */ > +#define REG_SD_DATA6_CRC=C2=A0 =C2=A0(0x118) /* CRC Data 6 from card= /eMMC */ > +#define REG_SD_DATA5_CRC=C2=A0 =C2=A0(0x11C) /* CRC Data 5 from card= /eMMC */ > +#define REG_SD_DATA4_CRC=C2=A0 =C2=A0(0x120) /* CRC Data 4 from card= /eMMC */ > +#define REG_SD_DATA3_CRC=C2=A0 =C2=A0(0x124) /* CRC Data 3 from card= /eMMC */ > +#define REG_SD_DATA2_CRC=C2=A0 =C2=A0(0x128) /* CRC Data 2 from card= /eMMC */ > +#define REG_SD_DATA1_CRC=C2=A0 =C2=A0(0x12C) /* CRC Data 1 from card= /eMMC */ > +#define REG_SD_DATA0_CRC=C2=A0 =C2=A0(0x130) /* CRC Data 0 from card= /eMMC */ > +#define REG_SD_CRC_STA=C2=A0 =C2=A0 =C2=A0(0x134) /* CRC status from= card/eMMC > during write */ > +#define REG_SD_FIFO=C2=A0 =C2=A0 =C2=A0 =C2=A0 (0x200) /* Read/Write= FIFO */ > + > +/* SD Host register flags */ > +#define SD_GCTL_FIFO_AC_MOD=C2=A0 =C2=A0 =C2=A0(1 << 31) > +#define SD_GCTL_DDR_MOD_SEL=C2=A0 =C2=A0 =C2=A0(1 << 10) > +#define SD_GCTL_CD_DBC_ENB=C2=A0 =C2=A0 =C2=A0 (1 << 8) > +#define SD_GCTL_DMA_ENB=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0(1 << 5) > +#define SD_GCTL_INT_ENB=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0(1 << 4) > +#define SD_GCTL_DMA_RST=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0(1 << 2) > +#define SD_GCTL_FIFO_RST=C2=A0 =C2=A0 =C2=A0 =C2=A0 (1 << 1) > +#define SD_GCTL_SOFT_RST=C2=A0 =C2=A0 =C2=A0 =C2=A0 (1 << 0) > + > +#define SD_CMDR_LOAD=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 (1 << = 31) > +#define SD_CMDR_CLKCHANGE=C2=A0 =C2=A0 =C2=A0 =C2=A0(1 << 21) > +#define SD_CMDR_WRITE=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0(1 << = 10) > +#define SD_CMDR_AUTOSTOP=C2=A0 =C2=A0 =C2=A0 =C2=A0 (1 << 12) > +#define SD_CMDR_DATA=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 (1 << = 9) > +#define SD_CMDR_RESPONSE_LONG=C2=A0 =C2=A0(1 << 7) > +#define SD_CMDR_RESPONSE=C2=A0 =C2=A0 =C2=A0 =C2=A0 (1 << 6) > +#define SD_CMDR_CMDID_MASK=C2=A0 =C2=A0 =C2=A0 (0x3f) > + > +#define SD_RISR_CARD_REMOVE=C2=A0 =C2=A0 =C2=A0(1 << 31) > +#define SD_RISR_CARD_INSERT=C2=A0 =C2=A0 =C2=A0(1 << 30) > +#define SD_RISR_AUTOCMD_DONE=C2=A0 =C2=A0 (1 << 14) > +#define SD_RISR_DATA_COMPLETE=C2=A0 =C2=A0(1 << 3) > +#define SD_RISR_CMD_COMPLETE=C2=A0 =C2=A0 (1 << 2) > +#define SD_RISR_NO_RESPONSE=C2=A0 =C2=A0 =C2=A0(1 << 1) > + > +#define SD_STAR_CARD_PRESENT=C2=A0 =C2=A0 (1 << 8) > + > +#define SD_IDST_SUM_RECEIVE_IRQ (1 << 8) > +#define SD_IDST_RECEIVE_IRQ=C2=A0 =C2=A0 =C2=A0(1 << 1) > +#define SD_IDST_TRANSMIT_IRQ=C2=A0 =C2=A0 (1 << 0) > +#define SD_IDST_IRQ_MASK=C2=A0 =C2=A0 =C2=A0 =C2=A0 (SD_IDST_RECEIVE= _IRQ | > SD_IDST_TRANSMIT_IRQ | \ > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0SD_IDST_SUM_RECEIVE_IRQ= ) > +#define SD_IDST_WR_MASK=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0(0x3ff) > + > +/* SD Host register reset values */ > +#define REG_SD_GCTL_RST=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0(0x00000300= ) > +#define REG_SD_CKCR_RST=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0(0x0) > +#define REG_SD_TMOR_RST=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0(0xFFFFFF40= ) > +#define REG_SD_BWDR_RST=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0(0x0) > +#define REG_SD_BKSR_RST=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0(0x00000200= ) > +#define REG_SD_BYCR_RST=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0(0x00000200= ) > +#define REG_SD_CMDR_RST=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0(0x0) > +#define REG_SD_CAGR_RST=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0(0x0) > +#define REG_SD_RESP_RST=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0(0x0) > +#define REG_SD_IMKR_RST=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0(0x0) > +#define REG_SD_MISR_RST=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0(0x0) > +#define REG_SD_RISR_RST=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0(0x0) > +#define REG_SD_STAR_RST=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0(0x00000100= ) > +#define REG_SD_FWLR_RST=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0(0x000F0000= ) > +#define REG_SD_FUNS_RST=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0(0x0) > +#define REG_SD_DBGC_RST=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0(0x0) > +#define REG_SD_A12A_RST=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0(0x0000FFFF= ) > +#define REG_SD_NTSR_RST=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0(0x00000001= ) > +#define REG_SD_SDBG_RST=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0(0x0) > +#define REG_SD_HWRST_RST=C2=A0 =C2=A0 =C2=A0 =C2=A0 (0x00000001) > +#define REG_SD_DMAC_RST=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0(0x0) > +#define REG_SD_DLBA_RST=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0(0x0) > +#define REG_SD_IDST_RST=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0(0x0) > +#define REG_SD_IDIE_RST=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0(0x0) > +#define REG_SD_THLDC_RST=C2=A0 =C2=A0 =C2=A0 =C2=A0 (0x0) > +#define REG_SD_DSBD_RST=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0(0x0) > +#define REG_SD_RES_CRC_RST=C2=A0 =C2=A0 =C2=A0 (0x0) > +#define REG_SD_DATA_CRC_RST=C2=A0 =C2=A0 =C2=A0(0x0) > +#define REG_SD_CRC_STA_RST=C2=A0 =C2=A0 =C2=A0 (0x0) > +#define REG_SD_FIFO_RST=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0(0x0) > + > +/* Data transfer descriptor for DMA */ > +typedef struct TransferDescriptor { > +=C2=A0 =C2=A0 uint32_t status; /* Status flags */ > +=C2=A0 =C2=A0 uint32_t size;=C2=A0 =C2=A0/* Data buffer size */ > +=C2=A0 =C2=A0 uint32_t addr;=C2=A0 =C2=A0/* Data buffer address */ > +=C2=A0 =C2=A0 uint32_t next;=C2=A0 =C2=A0/* Physical address of next= descriptor */ > +} TransferDescriptor; > + > +/* Data transfer descriptor flags */ > +#define DESC_STATUS_HOLD=C2=A0 =C2=A0(1 << 31) /* Set when descripto= r is in > use by DMA */ > +#define DESC_STATUS_ERROR=C2=A0 (1 << 30) /* Set when DMA transfer e= rror > occurred */ > +#define DESC_STATUS_CHAIN=C2=A0 (1 << 4)=C2=A0 /* Indicates chained > descriptor. */ > +#define DESC_STATUS_FIRST=C2=A0 (1 << 3)=C2=A0 /* Set on the first d= escriptor */ > +#define DESC_STATUS_LAST=C2=A0 =C2=A0(1 << 2)=C2=A0 /* Set on the la= st descriptor */ > +#define DESC_STATUS_NOIRQ=C2=A0 (1 << 1)=C2=A0 /* Skip raising inter= rupt > after transfer */ > + > +#define DESC_SIZE_MASK=C2=A0 =C2=A0 =C2=A0(0xfffffffc) > + > +static void aw_h3_sdhost_update_irq(AwH3SDHostState *s) > +{ > +=C2=A0 =C2=A0 uint32_t irq_en =3D s->global_ctl & SD_GCTL_INT_ENB; > +=C2=A0 =C2=A0 uint32_t irq =3D irq_en ? s->irq_status & s->irq_mask = : 0; The previous line is confuse, either use parenthesis or a if statement. uint32_t irq =3D irq_en ? (s->irq_status & s->irq_mask) : 0; > + > +=C2=A0 =C2=A0 trace_aw_h3_sdhost_update_irq(irq); > +=C2=A0 =C2=A0 qemu_set_irq(s->irq, irq); > +} > + > +static void aw_h3_sdhost_update_transfer_cnt(AwH3SDHostState *s, > uint32_t bytes) > +{ > +=C2=A0 =C2=A0 if (s->transfer_cnt > bytes) { > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 s->transfer_cnt -=3D bytes; > +=C2=A0 =C2=A0 } else { > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 s->transfer_cnt =3D 0; > +=C2=A0 =C2=A0 } > + > +=C2=A0 =C2=A0 if (!s->transfer_cnt) { > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 s->irq_status |=3D SD_RISR_DATA_COMPLETE= | SD_RISR_AUTOCMD_DONE; > +=C2=A0 =C2=A0 } > +} > + > +static void aw_h3_sdhost_set_inserted(DeviceState *dev, bool inserte= d) > +{ > +=C2=A0 =C2=A0 AwH3SDHostState *s =3D AW_H3_SDHOST(dev); > + > +=C2=A0 =C2=A0 trace_aw_h3_sdhost_set_inserted(inserted); > + > +=C2=A0 =C2=A0 if (inserted) { > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 s->irq_status |=3D SD_RISR_CARD_INSERT; > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 s->irq_status &=3D ~SD_RISR_CARD_REMOVE; > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 s->status |=3D SD_STAR_CARD_PRESENT; > +=C2=A0 =C2=A0 } else { > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 s->irq_status &=3D ~SD_RISR_CARD_INSERT; > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 s->irq_status |=3D SD_RISR_CARD_REMOVE; > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 s->status &=3D ~SD_STAR_CARD_PRESENT; > +=C2=A0 =C2=A0 } > + > +=C2=A0 =C2=A0 aw_h3_sdhost_update_irq(s); > +} > + > +static void aw_h3_sdhost_send_command(AwH3SDHostState *s) > +{ > +=C2=A0 =C2=A0 SDRequest request; > +=C2=A0 =C2=A0 uint8_t resp[16]; > +=C2=A0 =C2=A0 int rlen; > + > +=C2=A0 =C2=A0 /* Auto clear load flag */ > +=C2=A0 =C2=A0 s->command &=3D ~SD_CMDR_LOAD; > + > +=C2=A0 =C2=A0 /* Clock change does not actually interact with the SD= bus */ > +=C2=A0 =C2=A0 if (!(s->command & SD_CMDR_CLKCHANGE)) { > + > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 /* Prepare request */ > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 request.cmd =3D s->command & SD_CMDR_CMD= ID_MASK; > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 request.arg =3D s->command_arg; > + > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 /* Send request to SD bus */ > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 rlen =3D sdbus_do_command(&s->sdbus, &re= quest, resp); > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 if (rlen < 0) { > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 goto error; > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 } > + > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 /* If the command has a response, store = it in the response > registers */ > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 if ((s->command & SD_CMDR_RESPONSE)) { > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 if (rlen =3D=3D 0 || > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0(rlen =3D=3D = 4 && (s->command & SD_CMDR_RESPONSE_LONG))) { > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 goto error; > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 } > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 if (rlen !=3D 4 && rlen != =3D 16) { > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 goto error; > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 } Maybe remove previous if... > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 if (rlen =3D=3D 4) { > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 s->response[= 0] =3D ldl_be_p(&resp[0]); > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 s->response[= 1] =3D s->response[2] =3D s->response[3] =3D 0; > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 } else { ... } else if (rlen =3D=3D 16) { ... > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 s->response[= 0] =3D ldl_be_p(&resp[12]); > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 s->response[= 1] =3D ldl_be_p(&resp[8]); > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 s->response[= 2] =3D ldl_be_p(&resp[4]); > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 s->response[= 3] =3D ldl_be_p(&resp[0]); ... } else { goto error; > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 } > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 } > +=C2=A0 =C2=A0 } > + > +=C2=A0 =C2=A0 /* Set interrupt status bits */ > +=C2=A0 =C2=A0 s->irq_status |=3D SD_RISR_CMD_COMPLETE; > +=C2=A0 =C2=A0 return; > + > +error: > +=C2=A0 =C2=A0 s->irq_status |=3D SD_RISR_NO_RESPONSE; > +} > + > +static void aw_h3_sdhost_auto_stop(AwH3SDHostState *s) > +{ > +=C2=A0 =C2=A0 /* > +=C2=A0 =C2=A0 =C2=A0* The stop command (CMD12) ensures the SD bus > +=C2=A0 =C2=A0 =C2=A0* returns to the transfer state. > +=C2=A0 =C2=A0 =C2=A0*/ > +=C2=A0 =C2=A0 if ((s->command & SD_CMDR_AUTOSTOP) && (s->transfer_cn= t =3D=3D 0)) { > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 /* First save current command registers = */ > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 uint32_t saved_cmd =3D s->command; > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 uint32_t saved_arg =3D s->command_arg; > + > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 /* Prepare stop command (CMD12) */ > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 s->command &=3D ~SD_CMDR_CMDID_MASK; > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 s->command |=3D 12; /* CMD12 */ > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 s->command_arg =3D 0; > + > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 /* Put the command on SD bus */ > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 aw_h3_sdhost_send_command(s); > + > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 /* Restore command values */ > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 s->command =3D saved_cmd; > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 s->command_arg =3D saved_arg; > +=C2=A0 =C2=A0 } > +} > + > +static uint32_t aw_h3_sdhost_process_desc(AwH3SDHostState *s, > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 hwaddr desc_addr, > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 TransferDescriptor *desc, > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 bool is_write, uint32_t > max_bytes) > +{ > +=C2=A0 =C2=A0 uint32_t num_done =3D 0; > +=C2=A0 =C2=A0 uint32_t num_bytes =3D max_bytes; > +=C2=A0 =C2=A0 uint8_t buf[1024]; > + > +=C2=A0 =C2=A0 /* Read descriptor */ > +=C2=A0 =C2=A0 cpu_physical_memory_read(desc_addr, desc, sizeof(*desc= )); Should we worry about endianess here? > +=C2=A0 =C2=A0 if (desc->size =3D=3D 0) { > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 desc->size =3D 0xffff + 1; Why not write '64 * KiB'? > +=C2=A0 =C2=A0 } > +=C2=A0 =C2=A0 if (desc->size < num_bytes) { > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 num_bytes =3D desc->size; > +=C2=A0 =C2=A0 } > + > +=C2=A0 =C2=A0 trace_aw_h3_sdhost_process_desc(desc_addr, desc->size, > is_write, max_bytes); > + > +=C2=A0 =C2=A0 while (num_done < num_bytes) { > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 /* Try to completely fill the local buff= er */ > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 uint32_t buf_bytes =3D num_bytes - num_d= one; > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 if (buf_bytes > sizeof(buf)) { > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 buf_bytes =3D sizeof(buf); > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 } > + > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 /* Write to SD bus */ > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 if (is_write) { > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 cpu_physical_memory_read((= desc->addr & DESC_SIZE_MASK) > + num_done, > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 buf, buf= _bytes); > + > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 for (uint32_t i =3D 0; i <= buf_bytes; i++) { > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 sdbus_write_= data(&s->sdbus, buf[i]); > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 } > + > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 /* Read from SD bus */ > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 } else { > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 for (uint32_t i =3D 0; i <= buf_bytes; i++) { > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 buf[i] =3D s= dbus_read_data(&s->sdbus); > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 } > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 cpu_physical_memory_write(= (desc->addr & DESC_SIZE_MASK) > + num_done, > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0bu= f, buf_bytes); > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 } > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 num_done +=3D buf_bytes; > +=C2=A0 =C2=A0 } > + > +=C2=A0 =C2=A0 /* Clear hold flag and flush descriptor */ > +=C2=A0 =C2=A0 desc->status &=3D ~DESC_STATUS_HOLD; > +=C2=A0 =C2=A0 cpu_physical_memory_write(desc_addr, desc, sizeof(*des= c)); (Related to previous endianess question). > + > +=C2=A0 =C2=A0 return num_done; > +} > + > +static void aw_h3_sdhost_dma(AwH3SDHostState *s) > +{ > +=C2=A0 =C2=A0 TransferDescriptor desc; > +=C2=A0 =C2=A0 hwaddr desc_addr =3D s->desc_base; > +=C2=A0 =C2=A0 bool is_write =3D (s->command & SD_CMDR_WRITE); > +=C2=A0 =C2=A0 uint32_t bytes_done =3D 0; > + > +=C2=A0 =C2=A0 /* Check if DMA can be performed */ > +=C2=A0 =C2=A0 if (s->byte_count =3D=3D 0 || s->block_size =3D=3D 0 |= | > +=C2=A0 =C2=A0 =C2=A0 !(s->global_ctl & SD_GCTL_DMA_ENB)) { > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 return; > +=C2=A0 =C2=A0 } > + > +=C2=A0 =C2=A0 /* > +=C2=A0 =C2=A0 =C2=A0* For read operations, data must be available on= the SD bus > +=C2=A0 =C2=A0 =C2=A0* If not, it is an error and we should not act a= t all > +=C2=A0 =C2=A0 =C2=A0*/ > +=C2=A0 =C2=A0 if (!is_write && !sdbus_data_ready(&s->sdbus)) { > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 return; > +=C2=A0 =C2=A0 } > + > +=C2=A0 =C2=A0 /* Process the DMA descriptors until all data is copie= d */ > +=C2=A0 =C2=A0 while (s->byte_count > 0) { > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 bytes_done =3D aw_h3_sdhost_process_desc= (s, desc_addr, &desc, > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0is_write, > s->byte_count); > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 aw_h3_sdhost_update_transfer_cnt(s, byte= s_done); > + > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 if (bytes_done <=3D s->byte_count) { > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 s->byte_count -=3D bytes_d= one; > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 } else { > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 s->byte_count =3D 0; > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 } > + > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 if (desc.status & DESC_STATUS_LAST) { > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 break; > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 } else { > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 desc_addr =3D desc.next; > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 } > +=C2=A0 =C2=A0 } > + > +=C2=A0 =C2=A0 /* Raise IRQ to signal DMA is completed */ > +=C2=A0 =C2=A0 s->irq_status |=3D SD_RISR_DATA_COMPLETE | SD_RISR_AUT= OCMD_DONE; > + > +=C2=A0 =C2=A0 /* Update DMAC bits */ > +=C2=A0 =C2=A0 if (is_write) { > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 s->dmac_status |=3D SD_IDST_TRANSMIT_IRQ= ; > +=C2=A0 =C2=A0 } else { > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 s->dmac_status |=3D (SD_IDST_SUM_RECEIVE= _IRQ | > SD_IDST_RECEIVE_IRQ); > +=C2=A0 =C2=A0 } > +} > + > +static uint64_t aw_h3_sdhost_read(void *opaque, hwaddr offset, > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 unsigned size) > +{ > +=C2=A0 =C2=A0 AwH3SDHostState *s =3D (AwH3SDHostState *)opaque; > +=C2=A0 =C2=A0 uint32_t res =3D 0; > + > +=C2=A0 =C2=A0 switch (offset) { > +=C2=A0 =C2=A0 case REG_SD_GCTL:=C2=A0 =C2=A0 =C2=A0 /* Global Contro= l */ > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 res =3D s->global_ctl; > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 break; > +=C2=A0 =C2=A0 case REG_SD_CKCR:=C2=A0 =C2=A0 =C2=A0 /* Clock Control= */ > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 res =3D s->clock_ctl; > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 break; > +=C2=A0 =C2=A0 case REG_SD_TMOR:=C2=A0 =C2=A0 =C2=A0 /* Timeout */ > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 res =3D s->timeout; > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 break; > +=C2=A0 =C2=A0 case REG_SD_BWDR:=C2=A0 =C2=A0 =C2=A0 /* Bus Width */ > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 res =3D s->bus_width; > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 break; > +=C2=A0 =C2=A0 case REG_SD_BKSR:=C2=A0 =C2=A0 =C2=A0 /* Block Size */ > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 res =3D s->block_size; > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 break; > +=C2=A0 =C2=A0 case REG_SD_BYCR:=C2=A0 =C2=A0 =C2=A0 /* Byte Count */ > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 res =3D s->byte_count; > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 break; > +=C2=A0 =C2=A0 case REG_SD_CMDR:=C2=A0 =C2=A0 =C2=A0 /* Command */ > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 res =3D s->command; > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 break; > +=C2=A0 =C2=A0 case REG_SD_CAGR:=C2=A0 =C2=A0 =C2=A0 /* Command Argum= ent */ > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 res =3D s->command_arg; > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 break; > +=C2=A0 =C2=A0 case REG_SD_RESP0:=C2=A0 =C2=A0 =C2=A0/* Response Zero= */ > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 res =3D s->response[0]; > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 break; > +=C2=A0 =C2=A0 case REG_SD_RESP1:=C2=A0 =C2=A0 =C2=A0/* Response One = */ > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 res =3D s->response[1]; > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 break; > +=C2=A0 =C2=A0 case REG_SD_RESP2:=C2=A0 =C2=A0 =C2=A0/* Response Two = */ > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 res =3D s->response[2]; > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 break; > +=C2=A0 =C2=A0 case REG_SD_RESP3:=C2=A0 =C2=A0 =C2=A0/* Response Thre= e */ > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 res =3D s->response[3]; > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 break; > +=C2=A0 =C2=A0 case REG_SD_IMKR:=C2=A0 =C2=A0 =C2=A0 /* Interrupt Mas= k */ > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 res =3D s->irq_mask; > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 break; > +=C2=A0 =C2=A0 case REG_SD_MISR:=C2=A0 =C2=A0 =C2=A0 /* Masked Interr= upt Status */ > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 res =3D s->irq_status & s->irq_mask; > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 break; > +=C2=A0 =C2=A0 case REG_SD_RISR:=C2=A0 =C2=A0 =C2=A0 /* Raw Interrupt= Status */ > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 res =3D s->irq_status; > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 break; > +=C2=A0 =C2=A0 case REG_SD_STAR:=C2=A0 =C2=A0 =C2=A0 /* Status */ > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 res =3D s->status; > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 break; > +=C2=A0 =C2=A0 case REG_SD_FWLR:=C2=A0 =C2=A0 =C2=A0 /* FIFO Water Le= vel */ > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 res =3D s->fifo_wlevel; > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 break; > +=C2=A0 =C2=A0 case REG_SD_FUNS:=C2=A0 =C2=A0 =C2=A0 /* FIFO Function= Select */ > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 res =3D s->fifo_func_sel; > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 break; > +=C2=A0 =C2=A0 case REG_SD_DBGC:=C2=A0 =C2=A0 =C2=A0 /* Debug Enable = */ > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 res =3D s->debug_enable; > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 break; > +=C2=A0 =C2=A0 case REG_SD_A12A:=C2=A0 =C2=A0 =C2=A0 /* Auto command = 12 argument */ > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 res =3D s->auto12_arg; > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 break; > +=C2=A0 =C2=A0 case REG_SD_NTSR:=C2=A0 =C2=A0 =C2=A0 /* SD NewTiming = Set */ > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 res =3D s->newtiming_set; > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 break; > +=C2=A0 =C2=A0 case REG_SD_SDBG:=C2=A0 =C2=A0 =C2=A0 /* SD newTiming = Set Debug */ > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 res =3D s->newtiming_debug; > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 break; > +=C2=A0 =C2=A0 case REG_SD_HWRST:=C2=A0 =C2=A0 =C2=A0/* Hardware Rese= t Register */ > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 res =3D s->hardware_rst; > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 break; > +=C2=A0 =C2=A0 case REG_SD_DMAC:=C2=A0 =C2=A0 =C2=A0 /* Internal DMA = Controller Control */ > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 res =3D s->dmac; > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 break; > +=C2=A0 =C2=A0 case REG_SD_DLBA:=C2=A0 =C2=A0 =C2=A0 /* Descriptor Li= st Base Address */ > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 res =3D s->desc_base; > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 break; > +=C2=A0 =C2=A0 case REG_SD_IDST:=C2=A0 =C2=A0 =C2=A0 /* Internal DMA = Controller Status */ > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 res =3D s->dmac_status; > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 break; > +=C2=A0 =C2=A0 case REG_SD_IDIE:=C2=A0 =C2=A0 =C2=A0 /* Internal DMA = Controller Interrupt > Enable */ > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 res =3D s->dmac_irq; > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 break; > +=C2=A0 =C2=A0 case REG_SD_THLDC:=C2=A0 =C2=A0 =C2=A0/* Card Threshol= d Control */ > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 res =3D s->card_threshold; > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 break; > +=C2=A0 =C2=A0 case REG_SD_DSBD:=C2=A0 =C2=A0 =C2=A0 /* eMMC DDR Star= t Bit Detection Control */ > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 res =3D s->startbit_detect; > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 break; > +=C2=A0 =C2=A0 case REG_SD_RES_CRC:=C2=A0 =C2=A0/* Response CRC from = card/eMMC */ > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 res =3D s->response_crc; > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 break; > +=C2=A0 =C2=A0 case REG_SD_DATA7_CRC: /* CRC Data 7 from card/eMMC */ > +=C2=A0 =C2=A0 case REG_SD_DATA6_CRC: /* CRC Data 6 from card/eMMC */ > +=C2=A0 =C2=A0 case REG_SD_DATA5_CRC: /* CRC Data 5 from card/eMMC */ > +=C2=A0 =C2=A0 case REG_SD_DATA4_CRC: /* CRC Data 4 from card/eMMC */ > +=C2=A0 =C2=A0 case REG_SD_DATA3_CRC: /* CRC Data 3 from card/eMMC */ > +=C2=A0 =C2=A0 case REG_SD_DATA2_CRC: /* CRC Data 2 from card/eMMC */ > +=C2=A0 =C2=A0 case REG_SD_DATA1_CRC: /* CRC Data 1 from card/eMMC */ > +=C2=A0 =C2=A0 case REG_SD_DATA0_CRC: /* CRC Data 0 from card/eMMC */ > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 res =3D s->data_crc[((offset - REG_SD_DA= TA7_CRC) / > sizeof(uint32_t))]; > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 break; > +=C2=A0 =C2=A0 case REG_SD_CRC_STA:=C2=A0 =C2=A0/* CRC status from ca= rd/eMMC in write > operation */ > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 res =3D s->status_crc; > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 break; > +=C2=A0 =C2=A0 case REG_SD_FIFO:=C2=A0 =C2=A0 =C2=A0 /* Read/Write FI= FO */ > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 if (sdbus_data_ready(&s->sdbus)) { > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 res =3D sdbus_read_data(&s= ->sdbus); > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 res |=3D sdbus_read_data(&= s->sdbus) << 8; > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 res |=3D sdbus_read_data(&= s->sdbus) << 16; > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 res |=3D sdbus_read_data(&= s->sdbus) << 24; > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 aw_h3_sdhost_update_transf= er_cnt(s, sizeof(uint32_t)); > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 aw_h3_sdhost_auto_stop(s); > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 aw_h3_sdhost_update_irq(s)= ; > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 } else { > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 qemu_log_mask(LOG_GUEST_ER= ROR, "%s: no data ready on SD > bus\n", > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 __func__); > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 } > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 break; > +=C2=A0 =C2=A0 default: > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad = offset > %"HWADDR_PRIx"\n", > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 __func__, offset); > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 res =3D 0; > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 break; > +=C2=A0 =C2=A0 } > + > +=C2=A0 =C2=A0 trace_aw_h3_sdhost_read(offset, res, size); > +=C2=A0 =C2=A0 return res; > +} > + > +static void aw_h3_sdhost_write(void *opaque, hwaddr offset, > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0uint64_t value, unsigned size) > +{ > +=C2=A0 =C2=A0 AwH3SDHostState *s =3D (AwH3SDHostState *)opaque; > + > +=C2=A0 =C2=A0 trace_aw_h3_sdhost_write(offset, value, size); > + > +=C2=A0 =C2=A0 switch (offset) { > +=C2=A0 =C2=A0 case REG_SD_GCTL:=C2=A0 =C2=A0 =C2=A0 /* Global Contro= l */ > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 s->global_ctl =3D value; > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 s->global_ctl &=3D ~(SD_GCTL_DMA_RST | S= D_GCTL_FIFO_RST | > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0SD_GCTL_SOFT_RST); > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 aw_h3_sdhost_update_irq(s); > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 break; > +=C2=A0 =C2=A0 case REG_SD_CKCR:=C2=A0 =C2=A0 =C2=A0 /* Clock Control= */ > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 s->clock_ctl =3D value; > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 break; > +=C2=A0 =C2=A0 case REG_SD_TMOR:=C2=A0 =C2=A0 =C2=A0 /* Timeout */ > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 s->timeout =3D value; > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 break; > +=C2=A0 =C2=A0 case REG_SD_BWDR:=C2=A0 =C2=A0 =C2=A0 /* Bus Width */ > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 s->bus_width =3D value; > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 break; > +=C2=A0 =C2=A0 case REG_SD_BKSR:=C2=A0 =C2=A0 =C2=A0 /* Block Size */ > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 s->block_size =3D value; > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 break; > +=C2=A0 =C2=A0 case REG_SD_BYCR:=C2=A0 =C2=A0 =C2=A0 /* Byte Count */ > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 s->byte_count =3D value; > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 s->transfer_cnt =3D value; > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 break; > +=C2=A0 =C2=A0 case REG_SD_CMDR:=C2=A0 =C2=A0 =C2=A0 /* Command */ > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 s->command =3D value; > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 if (value & SD_CMDR_LOAD) { > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 aw_h3_sdhost_send_command(= s); > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 aw_h3_sdhost_dma(s); > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 aw_h3_sdhost_auto_stop(s); > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 } > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 aw_h3_sdhost_update_irq(s); > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 break; > +=C2=A0 =C2=A0 case REG_SD_CAGR:=C2=A0 =C2=A0 =C2=A0 /* Command Argum= ent */ > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 s->command_arg =3D value; > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 break; > +=C2=A0 =C2=A0 case REG_SD_RESP0:=C2=A0 =C2=A0 =C2=A0/* Response Zero= */ > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 s->response[0] =3D value; > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 break; > +=C2=A0 =C2=A0 case REG_SD_RESP1:=C2=A0 =C2=A0 =C2=A0/* Response One = */ > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 s->response[1] =3D value; > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 break; > +=C2=A0 =C2=A0 case REG_SD_RESP2:=C2=A0 =C2=A0 =C2=A0/* Response Two = */ > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 s->response[2] =3D value; > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 break; > +=C2=A0 =C2=A0 case REG_SD_RESP3:=C2=A0 =C2=A0 =C2=A0/* Response Thre= e */ > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 s->response[3] =3D value; > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 break; > +=C2=A0 =C2=A0 case REG_SD_IMKR:=C2=A0 =C2=A0 =C2=A0 /* Interrupt Mas= k */ > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 s->irq_mask =3D value; > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 aw_h3_sdhost_update_irq(s); > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 break; > +=C2=A0 =C2=A0 case REG_SD_MISR:=C2=A0 =C2=A0 =C2=A0 /* Masked Interr= upt Status */ > +=C2=A0 =C2=A0 case REG_SD_RISR:=C2=A0 =C2=A0 =C2=A0 /* Raw Interrupt= Status */ > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 s->irq_status &=3D ~value; > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 aw_h3_sdhost_update_irq(s); > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 break; > +=C2=A0 =C2=A0 case REG_SD_STAR:=C2=A0 =C2=A0 =C2=A0 /* Status */ > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 s->status &=3D ~value; > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 aw_h3_sdhost_update_irq(s); > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 break; > +=C2=A0 =C2=A0 case REG_SD_FWLR:=C2=A0 =C2=A0 =C2=A0 /* FIFO Water Le= vel */ > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 s->fifo_wlevel =3D value; > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 break; > +=C2=A0 =C2=A0 case REG_SD_FUNS:=C2=A0 =C2=A0 =C2=A0 /* FIFO Function= Select */ > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 s->fifo_func_sel =3D value; > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 break; > +=C2=A0 =C2=A0 case REG_SD_DBGC:=C2=A0 =C2=A0 =C2=A0 /* Debug Enable = */ > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 s->debug_enable =3D value; > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 break; > +=C2=A0 =C2=A0 case REG_SD_A12A:=C2=A0 =C2=A0 =C2=A0 /* Auto command = 12 argument */ > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 s->auto12_arg =3D value; > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 break; > +=C2=A0 =C2=A0 case REG_SD_NTSR:=C2=A0 =C2=A0 =C2=A0 /* SD NewTiming = Set */ > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 s->newtiming_set =3D value; > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 break; > +=C2=A0 =C2=A0 case REG_SD_SDBG:=C2=A0 =C2=A0 =C2=A0 /* SD newTiming = Set Debug */ > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 s->newtiming_debug =3D value; > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 break; > +=C2=A0 =C2=A0 case REG_SD_HWRST:=C2=A0 =C2=A0 =C2=A0/* Hardware Rese= t Register */ > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 s->hardware_rst =3D value; > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 break; > +=C2=A0 =C2=A0 case REG_SD_DMAC:=C2=A0 =C2=A0 =C2=A0 /* Internal DMA = Controller Control */ > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 s->dmac =3D value; > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 aw_h3_sdhost_update_irq(s); > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 break; > +=C2=A0 =C2=A0 case REG_SD_DLBA:=C2=A0 =C2=A0 =C2=A0 /* Descriptor Li= st Base Address */ > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 s->desc_base =3D value; > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 break; > +=C2=A0 =C2=A0 case REG_SD_IDST:=C2=A0 =C2=A0 =C2=A0 /* Internal DMA = Controller Status */ > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 s->dmac_status &=3D (~SD_IDST_WR_MASK) |= (~value & > SD_IDST_WR_MASK); > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 aw_h3_sdhost_update_irq(s); > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 break; > +=C2=A0 =C2=A0 case REG_SD_IDIE:=C2=A0 =C2=A0 =C2=A0 /* Internal DMA = Controller Interrupt > Enable */ > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 s->dmac_irq =3D value; > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 aw_h3_sdhost_update_irq(s); > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 break; > +=C2=A0 =C2=A0 case REG_SD_THLDC:=C2=A0 =C2=A0 =C2=A0/* Card Threshol= d Control */ > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 s->card_threshold =3D value; > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 break; > +=C2=A0 =C2=A0 case REG_SD_DSBD:=C2=A0 =C2=A0 =C2=A0 /* eMMC DDR Star= t Bit Detection Control */ > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 s->startbit_detect =3D value; > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 break; > +=C2=A0 =C2=A0 case REG_SD_FIFO:=C2=A0 =C2=A0 =C2=A0 /* Read/Write FI= FO */ > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 sdbus_write_data(&s->sdbus, value & 0xff= ); > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 sdbus_write_data(&s->sdbus, (value >> 8)= & 0xff); > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 sdbus_write_data(&s->sdbus, (value >> 16= ) & 0xff); > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 sdbus_write_data(&s->sdbus, (value >> 24= ) & 0xff); > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 aw_h3_sdhost_update_transfer_cnt(s, size= of(uint32_t)); > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 aw_h3_sdhost_auto_stop(s); > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 aw_h3_sdhost_update_irq(s); > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 break; > +=C2=A0 =C2=A0 case REG_SD_RES_CRC:=C2=A0 =C2=A0/* Response CRC from = card/eMMC */ > +=C2=A0 =C2=A0 case REG_SD_DATA7_CRC: /* CRC Data 7 from card/eMMC */ > +=C2=A0 =C2=A0 case REG_SD_DATA6_CRC: /* CRC Data 6 from card/eMMC */ > +=C2=A0 =C2=A0 case REG_SD_DATA5_CRC: /* CRC Data 5 from card/eMMC */ > +=C2=A0 =C2=A0 case REG_SD_DATA4_CRC: /* CRC Data 4 from card/eMMC */ > +=C2=A0 =C2=A0 case REG_SD_DATA3_CRC: /* CRC Data 3 from card/eMMC */ > +=C2=A0 =C2=A0 case REG_SD_DATA2_CRC: /* CRC Data 2 from card/eMMC */ > +=C2=A0 =C2=A0 case REG_SD_DATA1_CRC: /* CRC Data 1 from card/eMMC */ > +=C2=A0 =C2=A0 case REG_SD_DATA0_CRC: /* CRC Data 0 from card/eMMC */ > +=C2=A0 =C2=A0 case REG_SD_CRC_STA:=C2=A0 =C2=A0/* CRC status from ca= rd/eMMC in write > operation */ > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 break; > +=C2=A0 =C2=A0 default: > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad = offset > %"HWADDR_PRIx"\n", > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 __func__, offset); > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 break; > +=C2=A0 =C2=A0 } > +} > + > +static const MemoryRegionOps aw_h3_sdhost_ops =3D { > +=C2=A0 =C2=A0 .read =3D aw_h3_sdhost_read, > +=C2=A0 =C2=A0 .write =3D aw_h3_sdhost_write, > +=C2=A0 =C2=A0 .endianness =3D DEVICE_NATIVE_ENDIAN, I haven't checked .valid accesses from the datasheet. However due to: res =3D s->data_crc[((offset - REG_SD_DATA7_CRC) / sizeof(uint32_t))]; You seem to expect: .impl.min_access_size =3D 4, .impl.max_access_size unset is 8, which should works. > +}; > + > +static const VMStateDescription vmstate_aw_h3_sdhost =3D { > +=C2=A0 =C2=A0 .name =3D TYPE_AW_H3_SDHOST, Do not use TYPE name in VMStateDescription.name, because we might change=20 the value of TYPE, but the migration state has to keep the same name. > +=C2=A0 =C2=A0 .version_id =3D 1, > +=C2=A0 =C2=A0 .minimum_version_id =3D 1, > +=C2=A0 =C2=A0 .fields =3D (VMStateField[]) { > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 VMSTATE_UINT32(global_ctl, AwH3SDHostSta= te), > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 VMSTATE_UINT32(clock_ctl, AwH3SDHostStat= e), > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 VMSTATE_UINT32(timeout, AwH3SDHostState)= , > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 VMSTATE_UINT32(bus_width, AwH3SDHostStat= e), > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 VMSTATE_UINT32(block_size, AwH3SDHostSta= te), > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 VMSTATE_UINT32(byte_count, AwH3SDHostSta= te), > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 VMSTATE_UINT32(transfer_cnt, AwH3SDHostS= tate), > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 VMSTATE_UINT32(command, AwH3SDHostState)= , > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 VMSTATE_UINT32(command_arg, AwH3SDHostSt= ate), > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 VMSTATE_UINT32_ARRAY(response, AwH3SDHos= tState, 4), > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 VMSTATE_UINT32(irq_mask, AwH3SDHostState= ), > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 VMSTATE_UINT32(irq_status, AwH3SDHostSta= te), > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 VMSTATE_UINT32(status, AwH3SDHostState), > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 VMSTATE_UINT32(fifo_wlevel, AwH3SDHostSt= ate), > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 VMSTATE_UINT32(fifo_func_sel, AwH3SDHost= State), > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 VMSTATE_UINT32(debug_enable, AwH3SDHostS= tate), > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 VMSTATE_UINT32(auto12_arg, AwH3SDHostSta= te), > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 VMSTATE_UINT32(newtiming_set, AwH3SDHost= State), > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 VMSTATE_UINT32(newtiming_debug, AwH3SDHo= stState), > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 VMSTATE_UINT32(hardware_rst, AwH3SDHostS= tate), > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 VMSTATE_UINT32(dmac, AwH3SDHostState), > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 VMSTATE_UINT32(desc_base, AwH3SDHostStat= e), > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 VMSTATE_UINT32(dmac_status, AwH3SDHostSt= ate), > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 VMSTATE_UINT32(dmac_irq, AwH3SDHostState= ), > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 VMSTATE_UINT32(card_threshold, AwH3SDHos= tState), > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 VMSTATE_UINT32(startbit_detect, AwH3SDHo= stState), > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 VMSTATE_UINT32(response_crc, AwH3SDHostS= tate), > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 VMSTATE_UINT32_ARRAY(data_crc, AwH3SDHos= tState, 8), > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 VMSTATE_UINT32(status_crc, AwH3SDHostSta= te), > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 VMSTATE_END_OF_LIST() > +=C2=A0 =C2=A0 } > +}; > + > +static void aw_h3_sdhost_init(Object *obj) > +{ > +=C2=A0 =C2=A0 AwH3SDHostState *s =3D AW_H3_SDHOST(obj); > + > +=C2=A0 =C2=A0 qbus_create_inplace(&s->sdbus, sizeof(s->sdbus), > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 TYPE_AW_H3_SDHOST_BUS, DEVICE(s), "sd-bus"); > + > +=C2=A0 =C2=A0 memory_region_init_io(&s->iomem, obj, &aw_h3_sdhost_op= s, s, > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 TYPE_AW_H3_SDHOST, > AW_H3_SDHOST_REGS_MEM_SIZE); > +=C2=A0 =C2=A0 sysbus_init_mmio(SYS_BUS_DEVICE(s), &s->iomem); > +=C2=A0 =C2=A0 sysbus_init_irq(SYS_BUS_DEVICE(s), &s->irq); > +} > + > +static void aw_h3_sdhost_reset(DeviceState *dev) > +{ > +=C2=A0 =C2=A0 AwH3SDHostState *s =3D AW_H3_SDHOST(dev); > + > +=C2=A0 =C2=A0 s->global_ctl =3D REG_SD_GCTL_RST; > +=C2=A0 =C2=A0 s->clock_ctl =3D REG_SD_CKCR_RST; > +=C2=A0 =C2=A0 s->timeout =3D REG_SD_TMOR_RST; > +=C2=A0 =C2=A0 s->bus_width =3D REG_SD_BWDR_RST; > +=C2=A0 =C2=A0 s->block_size =3D REG_SD_BKSR_RST; > +=C2=A0 =C2=A0 s->byte_count =3D REG_SD_BYCR_RST; > +=C2=A0 =C2=A0 s->transfer_cnt =3D 0; > + > +=C2=A0 =C2=A0 s->command =3D REG_SD_CMDR_RST; > +=C2=A0 =C2=A0 s->command_arg =3D REG_SD_CAGR_RST; > + > +=C2=A0 =C2=A0 for (int i =3D 0; i < sizeof(s->response) / > sizeof(s->response[0]); i++) { Please use ARRAY_SIZE(s->response). > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 s->response[i] =3D REG_SD_RESP_RST; > +=C2=A0 =C2=A0 } > + > +=C2=A0 =C2=A0 s->irq_mask =3D REG_SD_IMKR_RST; > +=C2=A0 =C2=A0 s->irq_status =3D REG_SD_RISR_RST; > +=C2=A0 =C2=A0 s->status =3D REG_SD_STAR_RST; > + > +=C2=A0 =C2=A0 s->fifo_wlevel =3D REG_SD_FWLR_RST; > +=C2=A0 =C2=A0 s->fifo_func_sel =3D REG_SD_FUNS_RST; > +=C2=A0 =C2=A0 s->debug_enable =3D REG_SD_DBGC_RST; > +=C2=A0 =C2=A0 s->auto12_arg =3D REG_SD_A12A_RST; > +=C2=A0 =C2=A0 s->newtiming_set =3D REG_SD_NTSR_RST; > +=C2=A0 =C2=A0 s->newtiming_debug =3D REG_SD_SDBG_RST; > +=C2=A0 =C2=A0 s->hardware_rst =3D REG_SD_HWRST_RST; > +=C2=A0 =C2=A0 s->dmac =3D REG_SD_DMAC_RST; > +=C2=A0 =C2=A0 s->desc_base =3D REG_SD_DLBA_RST; > +=C2=A0 =C2=A0 s->dmac_status =3D REG_SD_IDST_RST; > +=C2=A0 =C2=A0 s->dmac_irq =3D REG_SD_IDIE_RST; > +=C2=A0 =C2=A0 s->card_threshold =3D REG_SD_THLDC_RST; > +=C2=A0 =C2=A0 s->startbit_detect =3D REG_SD_DSBD_RST; > +=C2=A0 =C2=A0 s->response_crc =3D REG_SD_RES_CRC_RST; > + > +=C2=A0 =C2=A0 for (int i =3D 0; i < sizeof(s->data_crc) / > sizeof(s->data_crc[0]); i++) { ARRAY_SIZE > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 s->data_crc[i] =3D REG_SD_DATA_CRC_RST; > +=C2=A0 =C2=A0 } > + > +=C2=A0 =C2=A0 s->status_crc =3D REG_SD_CRC_STA_RST; > +} > + > +static void aw_h3_sdhost_bus_class_init(ObjectClass *klass, void *da= ta) > +{ > +=C2=A0 =C2=A0 SDBusClass *sbc =3D SD_BUS_CLASS(klass); > + > +=C2=A0 =C2=A0 sbc->set_inserted =3D aw_h3_sdhost_set_inserted; > +} > + > +static void aw_h3_sdhost_class_init(ObjectClass *klass, void *data) > +{ > +=C2=A0 =C2=A0 DeviceClass *dc =3D DEVICE_CLASS(klass); > + > +=C2=A0 =C2=A0 dc->reset =3D aw_h3_sdhost_reset; > +=C2=A0 =C2=A0 dc->vmsd =3D &vmstate_aw_h3_sdhost; > +} > + > +static TypeInfo aw_h3_sdhost_info =3D { > +=C2=A0 =C2=A0 .name=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =3D TYPE_AW_H3= _SDHOST, > +=C2=A0 =C2=A0 .parent=C2=A0 =C2=A0 =C2=A0 =C2=A0 =3D TYPE_SYS_BUS_DE= VICE, > +=C2=A0 =C2=A0 .instance_size =3D sizeof(AwH3SDHostState), > +=C2=A0 =C2=A0 .class_init=C2=A0 =C2=A0 =3D aw_h3_sdhost_class_init, > +=C2=A0 =C2=A0 .instance_init =3D aw_h3_sdhost_init, > +}; > + > +static const TypeInfo aw_h3_sdhost_bus_info =3D { > +=C2=A0 =C2=A0 .name =3D TYPE_AW_H3_SDHOST_BUS, > +=C2=A0 =C2=A0 .parent =3D TYPE_SD_BUS, > +=C2=A0 =C2=A0 .instance_size =3D sizeof(SDBus), > +=C2=A0 =C2=A0 .class_init =3D aw_h3_sdhost_bus_class_init, > +}; > + > +static void aw_h3_sdhost_register_types(void) > +{ > +=C2=A0 =C2=A0 type_register_static(&aw_h3_sdhost_info); > +=C2=A0 =C2=A0 type_register_static(&aw_h3_sdhost_bus_info); > +} > + > +type_init(aw_h3_sdhost_register_types) > diff --git a/hw/sd/trace-events b/hw/sd/trace-events > index efcff666a2..c672a201b5 100644 > --- a/hw/sd/trace-events > +++ b/hw/sd/trace-events > @@ -1,5 +1,12 @@ > =C2=A0# See docs/devel/tracing.txt for syntax documentation. >=20 > +# allwinner-h3-sdhost.c > +aw_h3_sdhost_set_inserted(bool inserted) "inserted %u" > +aw_h3_sdhost_process_desc(uint64_t desc_addr, uint32_t desc_size, > bool is_write, uint32_t max_bytes) "desc_addr 0x%" PRIx64 " > desc_size %u is_write %u max_bytes %u" Please also use PRIu32 for desc_size/max_bytes. > +aw_h3_sdhost_read(uint64_t offset, uint64_t data, unsigned size) > "offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u" > +aw_h3_sdhost_write(uint64_t offset, uint64_t data, unsigned size) > "offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u" > +aw_h3_sdhost_update_irq(uint32_t irq) "IRQ bits 0x%x" PRIx32 > + > =C2=A0# bcm2835_sdhost.c > =C2=A0bcm2835_sdhost_read(uint64_t offset, uint64_t data, unsigned s= ize) > "offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u" > =C2=A0bcm2835_sdhost_write(uint64_t offset, uint64_t data, unsigned > size) "offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u" > diff --git a/include/hw/arm/allwinner-h3.h > b/include/hw/arm/allwinner-h3.h > index 33602599eb..7aff4ebbd2 100644 > --- a/include/hw/arm/allwinner-h3.h > +++ b/include/hw/arm/allwinner-h3.h > @@ -30,6 +30,7 @@ > =C2=A0#include "hw/misc/allwinner-h3-cpucfg.h" > =C2=A0#include "hw/misc/allwinner-h3-syscon.h" > =C2=A0#include "hw/misc/allwinner-h3-sid.h" > +#include "hw/sd/allwinner-h3-sdhost.h" > =C2=A0#include "target/arm/cpu.h" >=20 > =C2=A0#define AW_H3_SRAM_A1_BASE=C2=A0 =C2=A0 =C2=A0(0x00000000) > @@ -117,6 +118,7 @@ typedef struct AwH3State { > =C2=A0 =C2=A0 =C2=A0AwH3CpuCfgState cpucfg; > =C2=A0 =C2=A0 =C2=A0AwH3SysconState syscon; > =C2=A0 =C2=A0 =C2=A0AwH3SidState sid; > +=C2=A0 =C2=A0 AwH3SDHostState mmc0; > =C2=A0 =C2=A0 =C2=A0GICState gic; > =C2=A0 =C2=A0 =C2=A0MemoryRegion sram_a1; > =C2=A0 =C2=A0 =C2=A0MemoryRegion sram_a2; > diff --git a/include/hw/sd/allwinner-h3-sdhost.h > b/include/hw/sd/allwinner-h3-sdhost.h > new file mode 100644 > index 0000000000..6c898a3c84 > --- /dev/null > +++ b/include/hw/sd/allwinner-h3-sdhost.h > @@ -0,0 +1,73 @@ > +/* > + * Allwinner H3 SD Host Controller emulation > + * > + * Copyright (C) 2019 Niek Linnenbank > > + * > + * This program is free software: you can redistribute it and/or mod= ify > + * it under the terms of the GNU General Public License as published= by > + * the Free Software Foundation, either version 2 of the License, or > + * (at your option) any later version. > + * > + * This program is distributed in the hope that it will be useful, > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.=C2=A0 See th= e > + * GNU General Public License for more details. > + * > + * You should have received a copy of the GNU General Public License > + * along with this program.=C2=A0 If not, see > . > + */ > + > +#ifndef ALLWINNER_H3_SDHOST_H > +#define ALLWINNER_H3_SDHOST_H > + > +#include "hw/sysbus.h" > +#include "hw/sd/sd.h" > + > +#define AW_H3_SDHOST_REGS_MEM_SIZE=C2=A0 (1024) Move this definition to the source file. > + > +#define TYPE_AW_H3_SDHOST "allwinner-h3-sdhost" > +#define AW_H3_SDHOST(obj) \ > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 OBJECT_CHECK(AwH3SDHostState, (obj), TYP= E_AW_H3_SDHOST) > + > +typedef struct { > +=C2=A0 =C2=A0 SysBusDevice busdev; > +=C2=A0 =C2=A0 SDBus sdbus; > +=C2=A0 =C2=A0 MemoryRegion iomem; > + > +=C2=A0 =C2=A0 uint32_t global_ctl; > +=C2=A0 =C2=A0 uint32_t clock_ctl; > +=C2=A0 =C2=A0 uint32_t timeout; > +=C2=A0 =C2=A0 uint32_t bus_width; > +=C2=A0 =C2=A0 uint32_t block_size; > +=C2=A0 =C2=A0 uint32_t byte_count; > +=C2=A0 =C2=A0 uint32_t transfer_cnt; > + > +=C2=A0 =C2=A0 uint32_t command; > +=C2=A0 =C2=A0 uint32_t command_arg; > +=C2=A0 =C2=A0 uint32_t response[4]; > + > +=C2=A0 =C2=A0 uint32_t irq_mask; > +=C2=A0 =C2=A0 uint32_t irq_status; > +=C2=A0 =C2=A0 uint32_t status; > + > +=C2=A0 =C2=A0 uint32_t fifo_wlevel; > +=C2=A0 =C2=A0 uint32_t fifo_func_sel; > +=C2=A0 =C2=A0 uint32_t debug_enable; > +=C2=A0 =C2=A0 uint32_t auto12_arg; > +=C2=A0 =C2=A0 uint32_t newtiming_set; > +=C2=A0 =C2=A0 uint32_t newtiming_debug; > +=C2=A0 =C2=A0 uint32_t hardware_rst; > +=C2=A0 =C2=A0 uint32_t dmac; > +=C2=A0 =C2=A0 uint32_t desc_base; > +=C2=A0 =C2=A0 uint32_t dmac_status; > +=C2=A0 =C2=A0 uint32_t dmac_irq; > +=C2=A0 =C2=A0 uint32_t card_threshold; > +=C2=A0 =C2=A0 uint32_t startbit_detect; > +=C2=A0 =C2=A0 uint32_t response_crc; > +=C2=A0 =C2=A0 uint32_t data_crc[8]; > +=C2=A0 =C2=A0 uint32_t status_crc; > + > +=C2=A0 =C2=A0 qemu_irq irq; > +} AwH3SDHostState; > + > +#endif > --=20 > 2.17.1 I haven't checked the datasheet for all the registers/bits. Patch very clean, chapeau! Regards, Phil. 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[83.42.66.34]) by smtp.gmail.com with ESMTPSA id k13sm8074902wrx.59.2019.12.12.16.03.01 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 12 Dec 2019 16:03:02 -0800 (PST) Subject: Re: [PATCH 03/10] arm: allwinner-h3: add Clock Control Unit To: Niek Linnenbank , qemu-devel@nongnu.org Cc: b.galvani@gmail.com, peter.maydell@linaro.org, qemu-arm@nongnu.org References: <20191202210947.3603-1-nieklinnenbank@gmail.com> <20191202210947.3603-4-nieklinnenbank@gmail.com> From: =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= Message-ID: <7465e284-b8d8-db2b-f59b-4385ed06919b@redhat.com> Date: Fri, 13 Dec 2019 01:03:01 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.2.2 MIME-Version: 1.0 In-Reply-To: <20191202210947.3603-4-nieklinnenbank@gmail.com> Content-Language: en-US X-MC-Unique: 7-GlqD5MPh2GUHLNaBKRZg-1 X-Mimecast-Spam-Score: 0 Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 205.139.110.120 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 13 Dec 2019 00:03:15 -0000 On 12/2/19 10:09 PM, Niek Linnenbank wrote: > The Clock Control Unit is responsible for clock signal generation, > configuration and distribution in the Allwinner H3 System on Chip. > This commit adds support for the Clock Control Unit which emulates > a simple read/write register interface. > > Signed-off-by: Niek Linnenbank > --- > hw/arm/allwinner-h3.c | 11 ++ > hw/misc/Makefile.objs | 1 + > hw/misc/allwinner-h3-clk.c | 227 +++++++++++++++++++++++++++++ > include/hw/arm/allwinner-h3.h | 2 + > include/hw/misc/allwinner-h3-clk.h | 41 ++++++ > 5 files changed, 282 insertions(+) > create mode 100644 hw/misc/allwinner-h3-clk.c > create mode 100644 include/hw/misc/allwinner-h3-clk.h > > diff --git a/hw/arm/allwinner-h3.c b/hw/arm/allwinner-h3.c > index 470fdfebef..5566e979ec 100644 > --- a/hw/arm/allwinner-h3.c > +++ b/hw/arm/allwinner-h3.c > @@ -37,6 +37,9 @@ static void aw_h3_init(Object *obj) > > sysbus_init_child_obj(obj, "timer", &s->timer, sizeof(s->timer), > TYPE_AW_A10_PIT); > + > + sysbus_init_child_obj(obj, "ccu", &s->ccu, sizeof(s->ccu), > + TYPE_AW_H3_CLK); > } > > static void aw_h3_realize(DeviceState *dev, Error **errp) > @@ -172,6 +175,14 @@ static void aw_h3_realize(DeviceState *dev, Error **errp) > memory_region_add_subregion(get_system_memory(), AW_H3_SRAM_C_BASE, > &s->sram_c); > > + /* Clock Control Unit */ > + object_property_set_bool(OBJECT(&s->ccu), true, "realized", &err); > + if (err) { > + error_propagate(errp, err); > + return; > + } > + sysbus_mmio_map(SYS_BUS_DEVICE(&s->ccu), 0, AW_H3_CCU_BASE); > + > /* UART */ > if (serial_hd(0)) { > serial_mm_init(get_system_memory(), AW_H3_UART0_REG_BASE, 2, > diff --git a/hw/misc/Makefile.objs b/hw/misc/Makefile.objs > index ba898a5781..200ed44ce1 100644 > --- a/hw/misc/Makefile.objs > +++ b/hw/misc/Makefile.objs > @@ -28,6 +28,7 @@ common-obj-$(CONFIG_MACIO) += macio/ > > common-obj-$(CONFIG_IVSHMEM_DEVICE) += ivshmem.o > > +common-obj-$(CONFIG_ALLWINNER_H3) += allwinner-h3-clk.o > common-obj-$(CONFIG_REALVIEW) += arm_sysctl.o > common-obj-$(CONFIG_NSERIES) += cbus.o > common-obj-$(CONFIG_ECCMEMCTL) += eccmemctl.o > diff --git a/hw/misc/allwinner-h3-clk.c b/hw/misc/allwinner-h3-clk.c > new file mode 100644 > index 0000000000..77c55b4f92 > --- /dev/null > +++ b/hw/misc/allwinner-h3-clk.c > @@ -0,0 +1,227 @@ > +/* > + * Allwinner H3 Clock Control Unit emulation > + * > + * Copyright (C) 2019 Niek Linnenbank > + * > + * This program is free software: you can redistribute it and/or modify > + * it under the terms of the GNU General Public License as published by > + * the Free Software Foundation, either version 2 of the License, or > + * (at your option) any later version. > + * > + * This program is distributed in the hope that it will be useful, > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > + * GNU General Public License for more details. > + * > + * You should have received a copy of the GNU General Public License > + * along with this program. If not, see . > + */ > + > +#include "qemu/osdep.h" > +#include "hw/sysbus.h" > +#include "migration/vmstate.h" > +#include "qemu/log.h" > +#include "qemu/module.h" > +#include "hw/misc/allwinner-h3-clk.h" > + > +/* CCU register offsets */ > +#define REG_PLL_CPUX (0x0000) /* PLL CPUX Control */ > +#define REG_PLL_AUDIO (0x0008) /* PLL Audio Control */ > +#define REG_PLL_VIDEO (0x0010) /* PLL Video Control */ > +#define REG_PLL_VE (0x0018) /* PLL VE Control */ > +#define REG_PLL_DDR (0x0020) /* PLL DDR Control */ > +#define REG_PLL_PERIPH0 (0x0028) /* PLL Peripherals 0 Control */ > +#define REG_PLL_GPU (0x0038) /* PLL GPU Control */ > +#define REG_PLL_PERIPH1 (0x0044) /* PLL Peripherals 1 Control */ > +#define REG_PLL_DE (0x0048) /* PLL Display Engine Control */ > +#define REG_CPUX_AXI (0x0050) /* CPUX/AXI Configuration */ > +#define REG_APB1 (0x0054) /* ARM Peripheral Bus 1 Config */ > +#define REG_APB2 (0x0058) /* ARM Peripheral Bus 2 Config */ > +#define REG_MBUS (0x00FC) /* MBUS Reset */ > +#define REG_PLL_TIME0 (0x0200) /* PLL Stable Time 0 */ > +#define REG_PLL_TIME1 (0x0204) /* PLL Stable Time 1 */ > +#define REG_PLL_CPUX_BIAS (0x0220) /* PLL CPUX Bias */ > +#define REG_PLL_AUDIO_BIAS (0x0224) /* PLL Audio Bias */ > +#define REG_PLL_VIDEO_BIAS (0x0228) /* PLL Video Bias */ > +#define REG_PLL_VE_BIAS (0x022C) /* PLL VE Bias */ > +#define REG_PLL_DDR_BIAS (0x0230) /* PLL DDR Bias */ > +#define REG_PLL_PERIPH0_BIAS (0x0234) /* PLL Peripherals 0 Bias */ > +#define REG_PLL_GPU_BIAS (0x023C) /* PLL GPU Bias */ > +#define REG_PLL_PERIPH1_BIAS (0x0244) /* PLL Peripherals 1 Bias */ > +#define REG_PLL_DE_BIAS (0x0248) /* PLL Display Engine Bias */ > +#define REG_PLL_CPUX_TUNING (0x0250) /* PLL CPUX Tuning */ > +#define REG_PLL_DDR_TUNING (0x0260) /* PLL DDR Tuning */ > +#define REG_INDEX(offset) (offset / sizeof(uint32_t)) You might want to have a look at the macros from "hw/registerfields.h". > + > +/* CCU register flags */ > +#define REG_PLL_ENABLE (1 << 31) > +#define REG_PLL_LOCK (1 << 28) > + > +/* CCU register reset values */ > +#define REG_PLL_CPUX_RST (0x00001000) > +#define REG_PLL_AUDIO_RST (0x00035514) > +#define REG_PLL_VIDEO_RST (0x03006207) > +#define REG_PLL_VE_RST (0x03006207) > +#define REG_PLL_DDR_RST (0x00001000) > +#define REG_PLL_PERIPH0_RST (0x00041811) > +#define REG_PLL_GPU_RST (0x03006207) > +#define REG_PLL_PERIPH1_RST (0x00041811) > +#define REG_PLL_DE_RST (0x03006207) > +#define REG_CPUX_AXI_RST (0x00010000) > +#define REG_APB1_RST (0x00001010) > +#define REG_APB2_RST (0x01000000) > +#define REG_MBUS_RST (0x80000000) > +#define REG_PLL_TIME0_RST (0x000000FF) > +#define REG_PLL_TIME1_RST (0x000000FF) > +#define REG_PLL_CPUX_BIAS_RST (0x08100200) > +#define REG_PLL_AUDIO_BIAS_RST (0x10100000) > +#define REG_PLL_VIDEO_BIAS_RST (0x10100000) > +#define REG_PLL_VE_BIAS_RST (0x10100000) > +#define REG_PLL_DDR_BIAS_RST (0x81104000) > +#define REG_PLL_PERIPH0_BIAS_RST (0x10100010) > +#define REG_PLL_GPU_BIAS_RST (0x10100000) > +#define REG_PLL_PERIPH1_BIAS_RST (0x10100010) > +#define REG_PLL_DE_BIAS_RST (0x10100000) > +#define REG_PLL_CPUX_TUNING_RST (0x0A101000) > +#define REG_PLL_DDR_TUNING_RST (0x14880000) > + > +static uint64_t allwinner_h3_clk_read(void *opaque, hwaddr offset, > + unsigned size) > +{ > + const AwH3ClockState *s = (AwH3ClockState *)opaque; > + const uint32_t idx = REG_INDEX(offset); > + > + if (idx >= AW_H3_CLK_REGS_NUM) { > + qemu_log_mask(LOG_GUEST_ERROR, "%s: bad read offset 0x%04x\n", > + __func__, (uint32_t)offset); > + return 0; > + } > + > + return s->regs[idx]; > +} > + > +static void allwinner_h3_clk_write(void *opaque, hwaddr offset, > + uint64_t val, unsigned size) > +{ > + AwH3ClockState *s = (AwH3ClockState *)opaque; > + const uint32_t idx = REG_INDEX(offset); > + > + if (idx >= AW_H3_CLK_REGS_NUM) { > + qemu_log_mask(LOG_GUEST_ERROR, "%s: bad write offset 0x%04x\n", > + __func__, (uint32_t)offset); > + return; > + } > + > + switch (offset) { > + case REG_PLL_CPUX: /* PLL CPUX Control */ > + case REG_PLL_AUDIO: /* PLL Audio Control */ > + case REG_PLL_VIDEO: /* PLL Video Control */ > + case REG_PLL_VE: /* PLL VE Control */ > + case REG_PLL_DDR: /* PLL DDR Control */ > + case REG_PLL_PERIPH0: /* PLL Peripherals 0 Control */ > + case REG_PLL_GPU: /* PLL GPU Control */ > + case REG_PLL_PERIPH1: /* PLL Peripherals 1 Control */ > + case REG_PLL_DE: /* PLL Display Engine Control */ > + if (val & REG_PLL_ENABLE) { > + val |= REG_PLL_LOCK; > + } > + break; > + default: Maybe: qemu_log_mask(LOG_UNIMP, ... > + break; > + } > + > + s->regs[idx] = (uint32_t) val; > +} > + > +static const MemoryRegionOps allwinner_h3_clk_ops = { > + .read = allwinner_h3_clk_read, > + .write = allwinner_h3_clk_write, > + .endianness = DEVICE_NATIVE_ENDIAN, > + .valid = { > + .min_access_size = 4, > + .max_access_size = 4, > + .unaligned = false > + } > +}; > + > +static void allwinner_h3_clk_reset(DeviceState *dev) > +{ > + AwH3ClockState *s = AW_H3_CLK(dev); > + > + /* Set default values for registers */ > + s->regs[REG_INDEX(REG_PLL_CPUX)] = REG_PLL_CPUX_RST; > + s->regs[REG_INDEX(REG_PLL_AUDIO)] = REG_PLL_AUDIO_RST; > + s->regs[REG_INDEX(REG_PLL_VIDEO)] = REG_PLL_VIDEO_RST; > + s->regs[REG_INDEX(REG_PLL_VE)] = REG_PLL_VE_RST; > + s->regs[REG_INDEX(REG_PLL_DDR)] = REG_PLL_DDR_RST; > + s->regs[REG_INDEX(REG_PLL_PERIPH0)] = REG_PLL_PERIPH0_RST; > + s->regs[REG_INDEX(REG_PLL_GPU)] = REG_PLL_GPU_RST; > + s->regs[REG_INDEX(REG_PLL_PERIPH1)] = REG_PLL_PERIPH1_RST; > + s->regs[REG_INDEX(REG_PLL_DE)] = REG_PLL_DE_RST; > + s->regs[REG_INDEX(REG_CPUX_AXI)] = REG_CPUX_AXI_RST; > + s->regs[REG_INDEX(REG_APB1)] = REG_APB1_RST; > + s->regs[REG_INDEX(REG_APB2)] = REG_APB2_RST; > + s->regs[REG_INDEX(REG_MBUS)] = REG_MBUS_RST; > + s->regs[REG_INDEX(REG_PLL_TIME0)] = REG_PLL_TIME0_RST; > + s->regs[REG_INDEX(REG_PLL_TIME1)] = REG_PLL_TIME1_RST; > + s->regs[REG_INDEX(REG_PLL_CPUX_BIAS)] = REG_PLL_CPUX_BIAS_RST; > + s->regs[REG_INDEX(REG_PLL_AUDIO_BIAS)] = REG_PLL_AUDIO_BIAS_RST; > + s->regs[REG_INDEX(REG_PLL_VIDEO_BIAS)] = REG_PLL_VIDEO_BIAS_RST; > + s->regs[REG_INDEX(REG_PLL_VE_BIAS)] = REG_PLL_VE_BIAS_RST; > + s->regs[REG_INDEX(REG_PLL_DDR_BIAS)] = REG_PLL_DDR_BIAS_RST; > + s->regs[REG_INDEX(REG_PLL_PERIPH0_BIAS)] = REG_PLL_PERIPH0_BIAS_RST; > + s->regs[REG_INDEX(REG_PLL_GPU_BIAS)] = REG_PLL_GPU_BIAS_RST; > + s->regs[REG_INDEX(REG_PLL_PERIPH1_BIAS)] = REG_PLL_PERIPH1_BIAS_RST; > + s->regs[REG_INDEX(REG_PLL_DE_BIAS)] = REG_PLL_DE_BIAS_RST; > + s->regs[REG_INDEX(REG_PLL_CPUX_TUNING)] = REG_PLL_CPUX_TUNING_RST; > + s->regs[REG_INDEX(REG_PLL_DDR_TUNING)] = REG_PLL_DDR_TUNING_RST; > +} > + > +static void allwinner_h3_clk_realize(DeviceState *dev, Error **errp) > +{ > +} > + > +static void allwinner_h3_clk_init(Object *obj) > +{ > + SysBusDevice *sbd = SYS_BUS_DEVICE(obj); > + AwH3ClockState *s = AW_H3_CLK(obj); > + > + /* Memory mapping */ > + memory_region_init_io(&s->iomem, OBJECT(s), &allwinner_h3_clk_ops, s, > + TYPE_AW_H3_CLK, AW_H3_CLK_REGS_MEM_SIZE); > + sysbus_init_mmio(sbd, &s->iomem); > +} > + > +static const VMStateDescription allwinner_h3_clk_vmstate = { > + .name = TYPE_AW_H3_CLK, Use plain name, not TYPE_NAME. > + .version_id = 1, > + .minimum_version_id = 1, > + .fields = (VMStateField[]) { > + VMSTATE_UINT32_ARRAY(regs, AwH3ClockState, AW_H3_CLK_REGS_NUM), > + VMSTATE_END_OF_LIST() > + } > +}; > + > +static void allwinner_h3_clk_class_init(ObjectClass *klass, void *data) > +{ > + DeviceClass *dc = DEVICE_CLASS(klass); > + > + dc->reset = allwinner_h3_clk_reset; > + dc->realize = allwinner_h3_clk_realize; > + dc->vmsd = &allwinner_h3_clk_vmstate; > +} > + > +static const TypeInfo allwinner_h3_clk_info = { > + .name = TYPE_AW_H3_CLK, > + .parent = TYPE_SYS_BUS_DEVICE, > + .instance_init = allwinner_h3_clk_init, > + .instance_size = sizeof(AwH3ClockState), > + .class_init = allwinner_h3_clk_class_init, > +}; > + > +static void allwinner_h3_clk_register(void) > +{ > + type_register_static(&allwinner_h3_clk_info); > +} > + > +type_init(allwinner_h3_clk_register) > diff --git a/include/hw/arm/allwinner-h3.h b/include/hw/arm/allwinner-h3.h > index af368c2254..e596516c5c 100644 > --- a/include/hw/arm/allwinner-h3.h > +++ b/include/hw/arm/allwinner-h3.h > @@ -26,6 +26,7 @@ > #include "hw/arm/boot.h" > #include "hw/timer/allwinner-a10-pit.h" > #include "hw/intc/arm_gic.h" > +#include "hw/misc/allwinner-h3-clk.h" > #include "target/arm/cpu.h" > > #define AW_H3_SRAM_A1_BASE (0x00000000) > @@ -109,6 +110,7 @@ typedef struct AwH3State { > > qemu_irq irq[AW_H3_GIC_NUM_SPI]; > AwA10PITState timer; > + AwH3ClockState ccu; > GICState gic; > MemoryRegion sram_a1; > MemoryRegion sram_a2; > diff --git a/include/hw/misc/allwinner-h3-clk.h b/include/hw/misc/allwinner-h3-clk.h > new file mode 100644 > index 0000000000..69ea559db1 > --- /dev/null > +++ b/include/hw/misc/allwinner-h3-clk.h > @@ -0,0 +1,41 @@ > +/* > + * Allwinner H3 Clock Control Unit emulation > + * > + * Copyright (C) 2019 Niek Linnenbank > + * > + * This program is free software: you can redistribute it and/or modify > + * it under the terms of the GNU General Public License as published by > + * the Free Software Foundation, either version 2 of the License, or > + * (at your option) any later version. > + * > + * This program is distributed in the hope that it will be useful, > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > + * GNU General Public License for more details. > + * > + * You should have received a copy of the GNU General Public License > + * along with this program. If not, see . > + */ > + > +#ifndef HW_MISC_ALLWINNER_H3_CLK_H > +#define HW_MISC_ALLWINNER_H3_CLK_H > + > +#include "hw/sysbus.h" > + > +#define AW_H3_CLK_REGS_MAX_ADDR (0x304) > +#define AW_H3_CLK_REGS_NUM (AW_H3_CLK_REGS_MAX_ADDR / sizeof(uint32_t)) > +#define AW_H3_CLK_REGS_MEM_SIZE (1024) Move AW_H3_CLK_REGS_MEM_SIZE to source. > + > +#define TYPE_AW_H3_CLK "allwinner-h3-clk" > +#define AW_H3_CLK(obj) OBJECT_CHECK(AwH3ClockState, (obj), TYPE_AW_H3_CLK) > + > +typedef struct AwH3ClockState { > + /*< private >*/ > + SysBusDevice parent_obj; > + /*< public >*/ > + > + MemoryRegion iomem; > + uint32_t regs[AW_H3_CLK_REGS_NUM]; > +} AwH3ClockState; > + > +#endif > Patch looks good. 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[83.42.66.34]) by smtp.gmail.com with ESMTPSA id n16sm7941308wro.88.2019.12.12.16.09.38 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 12 Dec 2019 16:09:39 -0800 (PST) Subject: Re: [PATCH 05/10] arm: allwinner-h3: add System Control module To: Niek Linnenbank , qemu-devel@nongnu.org Cc: b.galvani@gmail.com, peter.maydell@linaro.org, qemu-arm@nongnu.org References: <20191202210947.3603-1-nieklinnenbank@gmail.com> <20191202210947.3603-6-nieklinnenbank@gmail.com> From: =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= Message-ID: <949aec5f-fd92-9fb2-25f4-803cd1bbf601@redhat.com> Date: Fri, 13 Dec 2019 01:09:38 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.2.2 MIME-Version: 1.0 In-Reply-To: <20191202210947.3603-6-nieklinnenbank@gmail.com> Content-Language: en-US X-MC-Unique: kOlSm4n7Mc2fWhg66GffaA-1 X-Mimecast-Spam-Score: 0 Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 207.211.31.81 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 13 Dec 2019 00:09:48 -0000 On 12/2/19 10:09 PM, Niek Linnenbank wrote: > The Allwinner H3 System on Chip has an System Control > module that provides system wide generic controls and > device information. This commit adds support for the > Allwinner H3 System Control module. > > Signed-off-by: Niek Linnenbank > --- > hw/arm/allwinner-h3.c | 11 ++ > hw/misc/Makefile.objs | 1 + > hw/misc/allwinner-h3-syscon.c | 139 ++++++++++++++++++++++++++ > include/hw/arm/allwinner-h3.h | 2 + > include/hw/misc/allwinner-h3-syscon.h | 43 ++++++++ > 5 files changed, 196 insertions(+) > create mode 100644 hw/misc/allwinner-h3-syscon.c > create mode 100644 include/hw/misc/allwinner-h3-syscon.h > > diff --git a/hw/arm/allwinner-h3.c b/hw/arm/allwinner-h3.c > index afeb49c0ac..ebd8fde412 100644 > --- a/hw/arm/allwinner-h3.c > +++ b/hw/arm/allwinner-h3.c > @@ -41,6 +41,9 @@ static void aw_h3_init(Object *obj) > > sysbus_init_child_obj(obj, "ccu", &s->ccu, sizeof(s->ccu), > TYPE_AW_H3_CLK); > + > + sysbus_init_child_obj(obj, "syscon", &s->syscon, sizeof(s->syscon), > + TYPE_AW_H3_SYSCON); > } > > static void aw_h3_realize(DeviceState *dev, Error **errp) > @@ -184,6 +187,14 @@ static void aw_h3_realize(DeviceState *dev, Error **errp) > } > sysbus_mmio_map(SYS_BUS_DEVICE(&s->ccu), 0, AW_H3_CCU_BASE); > > + /* System Control */ > + object_property_set_bool(OBJECT(&s->syscon), true, "realized", &err); > + if (err) { > + error_propagate(errp, err); > + return; > + } > + sysbus_mmio_map(SYS_BUS_DEVICE(&s->syscon), 0, AW_H3_SYSCON_BASE); > + > /* Universal Serial Bus */ > sysbus_create_simple(TYPE_AW_H3_EHCI, AW_H3_EHCI0_BASE, > s->irq[AW_H3_GIC_SPI_EHCI0]); > diff --git a/hw/misc/Makefile.objs b/hw/misc/Makefile.objs > index 200ed44ce1..b234aefba5 100644 > --- a/hw/misc/Makefile.objs > +++ b/hw/misc/Makefile.objs > @@ -29,6 +29,7 @@ common-obj-$(CONFIG_MACIO) += macio/ > common-obj-$(CONFIG_IVSHMEM_DEVICE) += ivshmem.o > > common-obj-$(CONFIG_ALLWINNER_H3) += allwinner-h3-clk.o > +common-obj-$(CONFIG_ALLWINNER_H3) += allwinner-h3-syscon.o > common-obj-$(CONFIG_REALVIEW) += arm_sysctl.o > common-obj-$(CONFIG_NSERIES) += cbus.o > common-obj-$(CONFIG_ECCMEMCTL) += eccmemctl.o > diff --git a/hw/misc/allwinner-h3-syscon.c b/hw/misc/allwinner-h3-syscon.c > new file mode 100644 > index 0000000000..66bd518a05 > --- /dev/null > +++ b/hw/misc/allwinner-h3-syscon.c > @@ -0,0 +1,139 @@ > +/* > + * Allwinner H3 System Control emulation > + * > + * Copyright (C) 2019 Niek Linnenbank > + * > + * This program is free software: you can redistribute it and/or modify > + * it under the terms of the GNU General Public License as published by > + * the Free Software Foundation, either version 2 of the License, or > + * (at your option) any later version. > + * > + * This program is distributed in the hope that it will be useful, > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > + * GNU General Public License for more details. > + * > + * You should have received a copy of the GNU General Public License > + * along with this program. If not, see . > + */ > + > +#include "qemu/osdep.h" > +#include "hw/sysbus.h" > +#include "migration/vmstate.h" > +#include "qemu/log.h" > +#include "qemu/module.h" > +#include "hw/misc/allwinner-h3-syscon.h" > + > +/* SYSCON register offsets */ > +#define REG_VER (0x24) /* Version */ > +#define REG_EMAC_PHY_CLK (0x30) /* EMAC PHY Clock */ > +#define REG_INDEX(offset) (offset / sizeof(uint32_t)) > + > +/* SYSCON register reset values */ > +#define REG_VER_RST (0x0) > +#define REG_EMAC_PHY_CLK_RST (0x58000) > + > +static uint64_t allwinner_h3_syscon_read(void *opaque, hwaddr offset, > + unsigned size) > +{ > + const AwH3SysconState *s = (AwH3SysconState *)opaque; > + const uint32_t idx = REG_INDEX(offset); > + > + if (idx >= AW_H3_SYSCON_REGS_NUM) { > + qemu_log_mask(LOG_GUEST_ERROR, "%s: bad read offset 0x%04x\n", > + __func__, (uint32_t)offset); > + return 0; > + } > + > + return s->regs[idx]; > +} > + > +static void allwinner_h3_syscon_write(void *opaque, hwaddr offset, > + uint64_t val, unsigned size) > +{ > + AwH3SysconState *s = (AwH3SysconState *)opaque; > + const uint32_t idx = REG_INDEX(offset); > + > + if (idx >= AW_H3_SYSCON_REGS_NUM) { > + qemu_log_mask(LOG_GUEST_ERROR, "%s: bad write offset 0x%04x\n", > + __func__, (uint32_t)offset); > + return; > + } > + > + switch (offset) { > + case REG_VER: /* Version */ > + break; > + default: > + s->regs[idx] = (uint32_t) val; > + break; > + } > +} > + > +static const MemoryRegionOps allwinner_h3_syscon_ops = { > + .read = allwinner_h3_syscon_read, > + .write = allwinner_h3_syscon_write, > + .endianness = DEVICE_NATIVE_ENDIAN, > + .valid = { > + .min_access_size = 4, > + .max_access_size = 4, Can you point me to the datasheet page that says this region is restricted to 32-bit accesses? Maybe you want .valid -> .impl instead? > + .unaligned = false > + } > +}; > + > +static void allwinner_h3_syscon_reset(DeviceState *dev) > +{ > + AwH3SysconState *s = AW_H3_SYSCON(dev); > + > + /* Set default values for registers */ > + s->regs[REG_INDEX(REG_VER)] = REG_VER_RST; > + s->regs[REG_INDEX(REG_EMAC_PHY_CLK)] = REG_EMAC_PHY_CLK_RST; > +} > + > +static void allwinner_h3_syscon_realize(DeviceState *dev, Error **errp) > +{ > +} > + > +static void allwinner_h3_syscon_init(Object *obj) > +{ > + SysBusDevice *sbd = SYS_BUS_DEVICE(obj); > + AwH3SysconState *s = AW_H3_SYSCON(obj); > + > + /* Memory mapping */ > + memory_region_init_io(&s->iomem, OBJECT(s), &allwinner_h3_syscon_ops, s, > + TYPE_AW_H3_SYSCON, AW_H3_SYSCON_REGS_MEM_SIZE); This definition isn't very helpful IMO, I'd use the value in place: '4 * KiB'. > + sysbus_init_mmio(sbd, &s->iomem); > +} > + > +static const VMStateDescription allwinner_h3_syscon_vmstate = { > + .name = TYPE_AW_H3_SYSCON, Plain name. > + .version_id = 1, > + .minimum_version_id = 1, > + .fields = (VMStateField[]) { > + VMSTATE_UINT32_ARRAY(regs, AwH3SysconState, AW_H3_SYSCON_REGS_NUM), > + VMSTATE_END_OF_LIST() > + } > +}; > + > +static void allwinner_h3_syscon_class_init(ObjectClass *klass, void *data) > +{ > + DeviceClass *dc = DEVICE_CLASS(klass); > + > + dc->reset = allwinner_h3_syscon_reset; > + dc->realize = allwinner_h3_syscon_realize; > + dc->vmsd = &allwinner_h3_syscon_vmstate; > +} > + > +static const TypeInfo allwinner_h3_syscon_info = { > + .name = TYPE_AW_H3_SYSCON, > + .parent = TYPE_SYS_BUS_DEVICE, > + .instance_init = allwinner_h3_syscon_init, > + .instance_size = sizeof(AwH3SysconState), > + .class_init = allwinner_h3_syscon_class_init, > +}; > + > +static void allwinner_h3_syscon_register(void) > +{ > + type_register_static(&allwinner_h3_syscon_info); > +} > + > +type_init(allwinner_h3_syscon_register) > diff --git a/include/hw/arm/allwinner-h3.h b/include/hw/arm/allwinner-h3.h > index e596516c5c..2bc526b77b 100644 > --- a/include/hw/arm/allwinner-h3.h > +++ b/include/hw/arm/allwinner-h3.h > @@ -27,6 +27,7 @@ > #include "hw/timer/allwinner-a10-pit.h" > #include "hw/intc/arm_gic.h" > #include "hw/misc/allwinner-h3-clk.h" > +#include "hw/misc/allwinner-h3-syscon.h" > #include "target/arm/cpu.h" > > #define AW_H3_SRAM_A1_BASE (0x00000000) > @@ -111,6 +112,7 @@ typedef struct AwH3State { > qemu_irq irq[AW_H3_GIC_NUM_SPI]; > AwA10PITState timer; > AwH3ClockState ccu; > + AwH3SysconState syscon; > GICState gic; > MemoryRegion sram_a1; > MemoryRegion sram_a2; > diff --git a/include/hw/misc/allwinner-h3-syscon.h b/include/hw/misc/allwinner-h3-syscon.h > new file mode 100644 > index 0000000000..22a2f2a11b > --- /dev/null > +++ b/include/hw/misc/allwinner-h3-syscon.h > @@ -0,0 +1,43 @@ > +/* > + * Allwinner H3 System Control emulation > + * > + * Copyright (C) 2019 Niek Linnenbank > + * > + * This program is free software: you can redistribute it and/or modify > + * it under the terms of the GNU General Public License as published by > + * the Free Software Foundation, either version 2 of the License, or > + * (at your option) any later version. > + * > + * This program is distributed in the hope that it will be useful, > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > + * GNU General Public License for more details. > + * > + * You should have received a copy of the GNU General Public License > + * along with this program. If not, see . > + */ > + > +#ifndef HW_MISC_ALLWINNER_H3_SYSCON_H > +#define HW_MISC_ALLWINNER_H3_SYSCON_H > + > +#include "hw/sysbus.h" > + > +#define AW_H3_SYSCON_REGS_MAX_ADDR (0x30) > +#define AW_H3_SYSCON_REGS_NUM ((AW_H3_SYSCON_REGS_MAX_ADDR / \ > + sizeof(uint32_t)) + 1) > +#define AW_H3_SYSCON_REGS_MEM_SIZE (1024) "4.1. Memory Mapping" the System Control is 4KiB, isn't it? > + > +#define TYPE_AW_H3_SYSCON "allwinner-h3-syscon" > +#define AW_H3_SYSCON(obj) OBJECT_CHECK(AwH3SysconState, (obj), \ > + TYPE_AW_H3_SYSCON) > + > +typedef struct AwH3SysconState { > + /*< private >*/ > + SysBusDevice parent_obj; > + /*< public >*/ > + > + MemoryRegion iomem; > + uint32_t regs[AW_H3_SYSCON_REGS_NUM]; > +} AwH3SysconState; > + > +#endif > From MAILER-DAEMON Thu Dec 12 20:33:21 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1ifZpZ-0007La-7K for mharc-qemu-arm@gnu.org; Thu, 12 Dec 2019 20:33:21 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:54787) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ifZpW-0007KQ-AV for qemu-arm@nongnu.org; Thu, 12 Dec 2019 20:33:19 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ifZpV-0002e2-6A for qemu-arm@nongnu.org; Thu, 12 Dec 2019 20:33:18 -0500 Received: from mga03.intel.com ([134.134.136.65]:14945) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1ifZpS-0002WF-93; Thu, 12 Dec 2019 20:33:14 -0500 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga004.fm.intel.com ([10.253.24.48]) by orsmga103.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 12 Dec 2019 17:33:12 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.69,307,1571727600"; d="scan'208";a="239148017" Received: from txu2-mobl.ccr.corp.intel.com (HELO [10.239.196.238]) ([10.239.196.238]) by fmsmga004.fm.intel.com with ESMTP; 12 Dec 2019 17:33:10 -0800 Subject: Re: [PATCH 2/2] numa: properly check if numa is supported To: Igor Mammedov , "qemu-devel@nongnu.org" Cc: Eduardo Habkost , Marcel Apfelbaum , Radoslaw Biernacki , Peter Maydell , Leif Lindholm , "qemu-arm@nongnu.org" , "qemu-stable@nongnu.org" References: <1576154936-178362-1-git-send-email-imammedo@redhat.com> <1576154936-178362-3-git-send-email-imammedo@redhat.com> From: Tao Xu Message-ID: Date: Fri, 13 Dec 2019 09:33:10 +0800 User-Agent: Mozilla/5.0 (Windows NT 10.0; WOW64; rv:60.0) Gecko/20100101 Thunderbird/60.9.1 MIME-Version: 1.0 In-Reply-To: <1576154936-178362-3-git-send-email-imammedo@redhat.com> Content-Type: text/plain; charset=utf-8; format=flowed Content-Language: en-US Content-Transfer-Encoding: 7bit X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 134.134.136.65 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 13 Dec 2019 01:33:19 -0000 On 12/12/2019 8:48 PM, Igor Mammedov wrote: > Commit aa57020774b, by mistake used MachineClass::numa_mem_supported > to check if NUMA is supported by machine and also as unrelated change > set it to true for sbsa-ref board. > > Luckily change didn't break machines that support NUMA, as the field > is set to true for them. > > But the field is not intended for checking if NUMA is supported and > will be flipped to false within this release for new machine types. > > Fix it: > - by using previously used condition > !mc->cpu_index_to_instance_props || !mc->get_default_cpu_node_id > the first time and then use MachineState::numa_state down the road > to check if NUMA is supported > - dropping stray sbsa-ref chunk > > Fixes: aa57020774b690a22be72453b8e91c9b5a68c516 > Signed-off-by: Igor Mammedov > --- > CC: Radoslaw Biernacki > CC: Peter Maydell > CC: Leif Lindholm > CC: qemu-arm@nongnu.org > CC: qemu-stable@nongnu.org > > > hw/arm/sbsa-ref.c | 1 - > hw/core/machine.c | 4 ++-- > 2 files changed, 2 insertions(+), 3 deletions(-) > > diff --git a/hw/arm/sbsa-ref.c b/hw/arm/sbsa-ref.c > index 27046cc..c6261d4 100644 > --- a/hw/arm/sbsa-ref.c > +++ b/hw/arm/sbsa-ref.c > @@ -791,7 +791,6 @@ static void sbsa_ref_class_init(ObjectClass *oc, void *data) > mc->possible_cpu_arch_ids = sbsa_ref_possible_cpu_arch_ids; > mc->cpu_index_to_instance_props = sbsa_ref_cpu_index_to_props; > mc->get_default_cpu_node_id = sbsa_ref_get_default_cpu_node_id; > - mc->numa_mem_supported = true; > } > > static const TypeInfo sbsa_ref_info = { > diff --git a/hw/core/machine.c b/hw/core/machine.c > index 1689ad3..aa63231 100644 > --- a/hw/core/machine.c > +++ b/hw/core/machine.c > @@ -958,7 +958,7 @@ static void machine_initfn(Object *obj) > NULL); > } > > - if (mc->numa_mem_supported) { > + if (mc->cpu_index_to_instance_props && mc->get_default_cpu_node_id) { > ms->numa_state = g_new0(NumaState, 1); > } I am wondering if @numa_mem_supported is unused here, it is unused for QEMU, because the only usage of @numa_mem_supported is to initialize @numa_state. Or there is other usage? So should it be removed from struct MachineClass? From MAILER-DAEMON Thu Dec 12 23:27:21 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1ifcXx-0003Op-4Z for mharc-qemu-arm@gnu.org; Thu, 12 Dec 2019 23:27:21 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:54183) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ifcXu-0003M8-BF for qemu-arm@nongnu.org; Thu, 12 Dec 2019 23:27:19 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ifcXs-0003A9-TO for qemu-arm@nongnu.org; Thu, 12 Dec 2019 23:27:18 -0500 Received: from wout3-smtp.messagingengine.com ([64.147.123.19]:54753) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1ifcXs-00035M-EX; Thu, 12 Dec 2019 23:27:16 -0500 Received: from compute4.internal (compute4.nyi.internal [10.202.2.44]) by mailout.west.internal (Postfix) with ESMTP id F12AD877; Thu, 12 Dec 2019 23:27:13 -0500 (EST) Received: from mailfrontend1 ([10.202.2.162]) by compute4.internal (MEProxy); Thu, 12 Dec 2019 23:27:14 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=aj.id.au; h=from :to:cc:subject:date:message-id:mime-version :content-transfer-encoding; s=fm1; bh=PqgLhpy94OGx/TZUhKr14ouSOm hNdalV2V/031LW2zc=; b=TQ20b1eKD9tveMzCEHh14gs1nOP7CDus0iJBcem7JE W1N7fTq9QC0oDxCMbs6FNEE1OhD/64Ch1F6UnpKqjDF/8hY0BzxrKATiazH5I+5l 7+7cPTCKOIhdo5JuqIKD7E1JG6UlfAcOdihS04W2IBcdG0gD5QSgiMmBxW0LMRd2 5zrP1TPkwu51xCEShImCDtEL791aVNEPcUBX9+Dhca2PDdcyxJG6r1BIMKjo9/wf 19UXE6s3vxWhnVopngjgYU0LCD73aOH9iKUyl1EbUUxr1MSWxeFYVUDGl2gsj549 aOcQh90rGX1AUy3cVLnOW3/Q1Cmw8u+iklmFYnaFnwNQ== DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d= messagingengine.com; h=cc:content-transfer-encoding:date:from :message-id:mime-version:subject:to:x-me-proxy:x-me-proxy :x-me-sender:x-me-sender:x-sasl-enc; s=fm1; bh=PqgLhpy94OGx/TZUh Kr14ouSOmhNdalV2V/031LW2zc=; b=fjtlUuFiyE4jIDZ3KSWKN1GNKe9+zXfZm fpuP9YIwMCvdP62UyS9WOJ/YmQ2PQou19V02LzHCds9lM377pStfrYuRA6C3wJ0S GaY0d4NCUix9qK7H+fJj+fHrn6SL6o2ZPNxSojamgDODokHiaOLzWz56OcY/tv9x C03n3B3z+Jtf3VnV4XdXxEy8tzDjcsKni/YjWp/yNz7pEeGaYGE1EdC/KQCAt/0W Gfh5AsckbHI4xOAHn7NCTpGFIi5T6gtMA8Hwjdjqm4p/tVgwh1DTLP7Jn/mQcgXw xMMuIDkfMxONihV7+doR+dinxwSJ6FMPeMfCdHRQhL8RTSyeGG6wA== X-ME-Sender: X-ME-Proxy-Cause: gggruggvucftvghtrhhoucdtuddrgedufedrudelkedgjedtucetufdoteggodetrfdotf fvucfrrhhofhhilhgvmecuhfgrshhtofgrihhlpdfqfgfvpdfurfetoffkrfgpnffqhgen uceurghilhhouhhtmecufedttdenucenucfjughrpefhvffufffkofgggfestdekredtre dttdenucfhrhhomheptehnughrvgifucflvghffhgvrhihuceorghnughrvgifsegrjhdr ihgurdgruheqnecuffhomhgrihhnpehoiihlrggsshdrohhrghenucfkphepvddtvddrke durddukedrfedtnecurfgrrhgrmhepmhgrihhlfhhrohhmpegrnhgurhgvfiesrghjrdhi ugdrrghunecuvehluhhsthgvrhfuihiivgeptd X-ME-Proxy: Received: from mistburn.au.ibm.com (bh02i525f01.au.ibm.com [202.81.18.30]) by mail.messagingengine.com (Postfix) with ESMTPA id 79FA980063; Thu, 12 Dec 2019 23:27:10 -0500 (EST) From: Andrew Jeffery To: qemu-arm@nongnu.org Cc: clg@kaod.org, peter.maydell@linaro.org, joel@jms.id.au, qemu-devel@nongnu.org Subject: [PATCH v2 0/2] hw/arm: ast2600: Wire up eMMC controller Date: Fri, 13 Dec 2019 14:58:40 +1030 Message-Id: X-Mailer: git-send-email 2.20.1 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 64.147.123.19 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 13 Dec 2019 04:27:19 -0000 Hello, The AST2600 has an additional SDHCI intended for use as an eMMC boot source. These two patches rework the existing ASPEED SDHCI model to accommodate the single-slot nature of the eMMC controller and wire it into the AST2600 SoC. v2 contains some minor refactorings in response to issues pointed out by Cedric. v1 can be found here: https://patchwork.ozlabs.org/cover/1206845/ Please review! Andrew Andrew Jeffery (2): hw/sd: Configure number of slots exposed by the ASPEED SDHCI model hw/arm: ast2600: Wire up the eMMC controller hw/arm/aspeed.c | 27 +++++++++++++++++---------- hw/arm/aspeed_ast2600.c | 23 +++++++++++++++++++++++ hw/arm/aspeed_soc.c | 2 ++ hw/sd/aspeed_sdhci.c | 11 +++++++++-- include/hw/arm/aspeed_soc.h | 2 ++ include/hw/sd/aspeed_sdhci.h | 1 + 6 files changed, 54 insertions(+), 12 deletions(-) base-commit: 6a4ef4e5d1084ce41fafa7d470a644b0fd3d9317 -- git-series 0.9.1 From MAILER-DAEMON Thu Dec 12 23:27:22 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1ifcXy-0003QH-AT for mharc-qemu-arm@gnu.org; Thu, 12 Dec 2019 23:27:22 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:54360) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ifcXv-0003N8-9F for qemu-arm@nongnu.org; Thu, 12 Dec 2019 23:27:20 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ifcXt-0003Ce-TZ for qemu-arm@nongnu.org; Thu, 12 Dec 2019 23:27:19 -0500 Received: from wout3-smtp.messagingengine.com ([64.147.123.19]:54267) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1ifcXt-0003Ai-Lv; Thu, 12 Dec 2019 23:27:17 -0500 Received: from compute4.internal (compute4.nyi.internal [10.202.2.44]) by mailout.west.internal (Postfix) with ESMTP id 7267A87D; Thu, 12 Dec 2019 23:27:16 -0500 (EST) Received: from mailfrontend1 ([10.202.2.162]) by compute4.internal (MEProxy); Thu, 12 Dec 2019 23:27:16 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=aj.id.au; h=from :to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-type:content-transfer-encoding; s=fm1; bh= 0lW1mMLBYhMF9Wt+yQXH47/Bfxh3BxEXaqeyk1Njp9k=; b=WodJyDHBTZL3ni+d 53jU7Qzqp16ZJwPCeyHiyvvK9VetkUfbOqlL+9dI3R/E7N4O8yH8ykytGTlO+Gsu MaOp9w43POdA60NhLLHxV4fl5I4+cE0cnJPf/sgyTMpDELfyjh0PeIxhbMaLLbUx wapi55dgTjPS/wkouwYQTLhJFoVA9OvdBvVpURqIlO3PCQ3FO+R/KAAy3hmzmZco PfI4rPya8AyUGwIU/egeSgul/zFuErtiRirBETTaEGv7ce8zhAZ6C+YS25JFIDXp OqZDg9Vf14OpYuRAHaBYAvJjhOanDhR8/mbS9zkC/j3Rn0foQ8BkmxZnoCpvgilR 4BMHBA== DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d= messagingengine.com; h=cc:content-transfer-encoding:content-type :date:from:in-reply-to:message-id:mime-version:references :subject:to:x-me-proxy:x-me-proxy:x-me-sender:x-me-sender :x-sasl-enc; s=fm1; bh=0lW1mMLBYhMF9Wt+yQXH47/Bfxh3BxEXaqeyk1Njp 9k=; b=XnKiNzXdpUss4L6qJkeBUIJXU3PanyxhmqJ6+vMk4ZAG38htP23jU+bbB 3VAvgNaNgh5A2mcMwPQnxnw+HqnYjvj776l95zqA1eh2wD59dPeeriLTQZOmNUR6 l8S65WQSnbVRFG5tFptTY1dk2IlDKiWhNF1cqOE5fsvxTlsFqkNM3FMG7P+IrfyI xNomE+nl7I9zEPiKPFUaljeV2SHsneOJH5PkAxEuKa8pPbq9wBa3URy3VpY7ZaFr ixlXNGlwtUE9VwAM1uUVQb1uzOKOxK41gi/yCt/vq7Om69iGjJPEoCQsEBwN+fQg BUonlA7J7Dq1nS52VCUsVWCor6DQw== X-ME-Sender: X-ME-Proxy-Cause: gggruggvucftvghtrhhoucdtuddrgedufedrudelkedgjedtucetufdoteggodetrfdotf fvucfrrhhofhhilhgvmecuhfgrshhtofgrihhlpdfqfgfvpdfurfetoffkrfgpnffqhgen uceurghilhhouhhtmecufedttdenucesvcftvggtihhpihgvnhhtshculddquddttddmne cujfgurhephffvufffkffojghfgggtgfesthekredtredtjeenucfhrhhomheptehnughr vgifucflvghffhgvrhihuceorghnughrvgifsegrjhdrihgurdgruheqnecukfhppedvtd dvrdekuddrudekrdeftdenucfrrghrrghmpehmrghilhhfrhhomheprghnughrvgifsegr jhdrihgurdgruhenucevlhhushhtvghrufhiiigvpedt X-ME-Proxy: Received: from mistburn.au.ibm.com (bh02i525f01.au.ibm.com [202.81.18.30]) by mail.messagingengine.com (Postfix) with ESMTPA id 4D73B80066; Thu, 12 Dec 2019 23:27:13 -0500 (EST) From: Andrew Jeffery To: qemu-arm@nongnu.org Cc: clg@kaod.org, peter.maydell@linaro.org, joel@jms.id.au, qemu-devel@nongnu.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH v2 1/2] hw/sd: Configure number of slots exposed by the ASPEED SDHCI model Date: Fri, 13 Dec 2019 14:58:41 +1030 Message-Id: <6281ebb475f652838d10dc48ec70fa5113b1f029.1576211124.git-series.andrew@aj.id.au> X-Mailer: git-send-email 2.20.1 In-Reply-To: References: MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 64.147.123.19 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 13 Dec 2019 04:27:20 -0000 The AST2600 includes a second cut-down version of the SD/MMC controller found in the AST2500, named the eMMC controller. It's cut down in the sense that it only supports one slot rather than two, but it brings the total number of slots supported by the AST2600 to three. The existing code assumed that the SD controller always provided two slots. Rework the SDHCI object to expose the number of slots as a property to be set by the SoC configuration. Signed-off-by: Andrew Jeffery Reviewed-by: Philippe Mathieu-Daudé --- hw/arm/aspeed.c | 2 +- hw/arm/aspeed_ast2600.c | 2 ++ hw/arm/aspeed_soc.c | 2 ++ hw/sd/aspeed_sdhci.c | 11 +++++++++-- include/hw/sd/aspeed_sdhci.h | 1 + 5 files changed, 15 insertions(+), 3 deletions(-) diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c index 028191ff36fc..862549b1f3a9 100644 --- a/hw/arm/aspeed.c +++ b/hw/arm/aspeed.c @@ -259,7 +259,7 @@ static void aspeed_board_init(MachineState *machine, cfg->i2c_init(bmc); } - for (i = 0; i < ARRAY_SIZE(bmc->soc.sdhci.slots); i++) { + for (i = 0; i < bmc->soc.sdhci.num_slots; i++) { SDHCIState *sdhci = &bmc->soc.sdhci.slots[i]; DriveInfo *dinfo = drive_get_next(IF_SD); BlockBackend *blk; diff --git a/hw/arm/aspeed_ast2600.c b/hw/arm/aspeed_ast2600.c index 931887ac681f..931ee5aae183 100644 --- a/hw/arm/aspeed_ast2600.c +++ b/hw/arm/aspeed_ast2600.c @@ -208,6 +208,8 @@ static void aspeed_soc_ast2600_init(Object *obj) sysbus_init_child_obj(obj, "sdc", OBJECT(&s->sdhci), sizeof(s->sdhci), TYPE_ASPEED_SDHCI); + object_property_set_int(OBJECT(&s->sdhci), 2, "num-slots", &error_abort); + /* Init sd card slot class here so that they're under the correct parent */ for (i = 0; i < ASPEED_SDHCI_NUM_SLOTS; ++i) { sysbus_init_child_obj(obj, "sdhci[*]", OBJECT(&s->sdhci.slots[i]), diff --git a/hw/arm/aspeed_soc.c b/hw/arm/aspeed_soc.c index f4fe243458fd..c39a42f914d4 100644 --- a/hw/arm/aspeed_soc.c +++ b/hw/arm/aspeed_soc.c @@ -215,6 +215,8 @@ static void aspeed_soc_init(Object *obj) sysbus_init_child_obj(obj, "sdc", OBJECT(&s->sdhci), sizeof(s->sdhci), TYPE_ASPEED_SDHCI); + object_property_set_int(OBJECT(&s->sdhci), 2, "num-slots", &error_abort); + /* Init sd card slot class here so that they're under the correct parent */ for (i = 0; i < ASPEED_SDHCI_NUM_SLOTS; ++i) { sysbus_init_child_obj(obj, "sdhci[*]", OBJECT(&s->sdhci.slots[i]), diff --git a/hw/sd/aspeed_sdhci.c b/hw/sd/aspeed_sdhci.c index cff3eb7dd21e..939d1510dedb 100644 --- a/hw/sd/aspeed_sdhci.c +++ b/hw/sd/aspeed_sdhci.c @@ -13,6 +13,7 @@ #include "qapi/error.h" #include "hw/irq.h" #include "migration/vmstate.h" +#include "hw/qdev-properties.h" #define ASPEED_SDHCI_INFO 0x00 #define ASPEED_SDHCI_INFO_RESET 0x00030000 @@ -120,14 +121,14 @@ static void aspeed_sdhci_realize(DeviceState *dev, Error **errp) /* Create input irqs for the slots */ qdev_init_gpio_in_named_with_opaque(DEVICE(sbd), aspeed_sdhci_set_irq, - sdhci, NULL, ASPEED_SDHCI_NUM_SLOTS); + sdhci, NULL, sdhci->num_slots); sysbus_init_irq(sbd, &sdhci->irq); memory_region_init_io(&sdhci->iomem, OBJECT(sdhci), &aspeed_sdhci_ops, sdhci, TYPE_ASPEED_SDHCI, 0x1000); sysbus_init_mmio(sbd, &sdhci->iomem); - for (int i = 0; i < ASPEED_SDHCI_NUM_SLOTS; ++i) { + for (int i = 0; i < sdhci->num_slots; ++i) { Object *sdhci_slot = OBJECT(&sdhci->slots[i]); SysBusDevice *sbd_slot = SYS_BUS_DEVICE(&sdhci->slots[i]); @@ -174,6 +175,11 @@ static const VMStateDescription vmstate_aspeed_sdhci = { }, }; +static Property aspeed_sdhci_properties[] = { + DEFINE_PROP_UINT8("num-slots", AspeedSDHCIState, num_slots, 0), + DEFINE_PROP_END_OF_LIST(), +}; + static void aspeed_sdhci_class_init(ObjectClass *classp, void *data) { DeviceClass *dc = DEVICE_CLASS(classp); @@ -181,6 +187,7 @@ static void aspeed_sdhci_class_init(ObjectClass *classp, void *data) dc->realize = aspeed_sdhci_realize; dc->reset = aspeed_sdhci_reset; dc->vmsd = &vmstate_aspeed_sdhci; + dc->props = aspeed_sdhci_properties; } static TypeInfo aspeed_sdhci_info = { diff --git a/include/hw/sd/aspeed_sdhci.h b/include/hw/sd/aspeed_sdhci.h index dfdab4379021..dffbb46946b9 100644 --- a/include/hw/sd/aspeed_sdhci.h +++ b/include/hw/sd/aspeed_sdhci.h @@ -24,6 +24,7 @@ typedef struct AspeedSDHCIState { SysBusDevice parent; SDHCIState slots[ASPEED_SDHCI_NUM_SLOTS]; + uint8_t num_slots; MemoryRegion iomem; qemu_irq irq; -- git-series 0.9.1 From MAILER-DAEMON Thu Dec 12 23:27:24 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1ifcY0-0003Sf-IU for mharc-qemu-arm@gnu.org; Thu, 12 Dec 2019 23:27:24 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:54822) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ifcXx-0003Pv-Vy for qemu-arm@nongnu.org; Thu, 12 Dec 2019 23:27:23 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ifcXw-0003JP-LX for qemu-arm@nongnu.org; Thu, 12 Dec 2019 23:27:21 -0500 Received: from wout3-smtp.messagingengine.com ([64.147.123.19]:43307) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1ifcXw-0003Hg-Cc; Thu, 12 Dec 2019 23:27:20 -0500 Received: from compute4.internal (compute4.nyi.internal [10.202.2.44]) by mailout.west.internal (Postfix) with ESMTP id 3A54888E; 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b=rQMRRQV0 4dW2Mok94avZk2dTwY3A1X3J0WuMnSXxE8638K0ph6/r/qjLj+YST5BV7GaetBUM 6Hcw8aN77rZY4xrP3nq76TFlrOmOoyZoV1l0EGtm0zmVeatWqxrFNIpm8LiKVgjV 3SADrRHHR8wSGYa/0jELfVGCUK5+JRpLNNMKg1sydTrgP3N/Oe6ESH9rlttPDinh Spu2I4Ll0I7kxfDe7az+EuxxEg5YsqtJr5dOfARu05FWrgztm7w8tMqjjWnmJTxc aPUU9XuETT/ymvf49SU75UvTyR8V/d87ZO3wm7uuERRrg4C//sDSOkb6UsvPfhN1 jFPMHHEt5+2h4g== X-ME-Sender: X-ME-Proxy-Cause: gggruggvucftvghtrhhoucdtuddrgedufedrudelkedgjedtucetufdoteggodetrfdotf fvucfrrhhofhhilhgvmecuhfgrshhtofgrihhlpdfqfgfvpdfurfetoffkrfgpnffqhgen uceurghilhhouhhtmecufedttdenucenucfjughrpefhvffufffkofgjfhgggfestdekre dtredttdenucfhrhhomheptehnughrvgifucflvghffhgvrhihuceorghnughrvgifsegr jhdrihgurdgruheqnecukfhppedvtddvrdekuddrudekrdeftdenucfrrghrrghmpehmrg hilhhfrhhomheprghnughrvgifsegrjhdrihgurdgruhenucevlhhushhtvghrufhiiigv pedt X-ME-Proxy: Received: from mistburn.au.ibm.com (bh02i525f01.au.ibm.com [202.81.18.30]) by mail.messagingengine.com (Postfix) with ESMTPA id 6910A80064; Thu, 12 Dec 2019 23:27:16 -0500 (EST) From: Andrew Jeffery To: qemu-arm@nongnu.org Cc: clg@kaod.org, peter.maydell@linaro.org, joel@jms.id.au, qemu-devel@nongnu.org Subject: [PATCH v2 2/2] hw/arm: ast2600: Wire up the eMMC controller Date: Fri, 13 Dec 2019 14:58:42 +1030 Message-Id: <23bbbd829459a9a2508c9e76f0720e428852d92d.1576211124.git-series.andrew@aj.id.au> X-Mailer: git-send-email 2.20.1 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 64.147.123.19 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 13 Dec 2019 04:27:23 -0000 Initialise another SDHCI model instance for the AST2600's eMMC controller and use the SDHCI's num_slots value introduced previously to determine whether we should create an SD card instance for the new slot. Signed-off-by: Andrew Jeffery --- v2: * Extract instantiation of SD cards to helper function hw/arm/aspeed.c | 25 ++++++++++++++++--------- hw/arm/aspeed_ast2600.c | 21 +++++++++++++++++++++ include/hw/arm/aspeed_soc.h | 2 ++ 3 files changed, 39 insertions(+), 9 deletions(-) diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c index 862549b1f3a9..87baac0ea46c 100644 --- a/hw/arm/aspeed.c +++ b/hw/arm/aspeed.c @@ -167,6 +167,18 @@ static void aspeed_board_init_flashes(AspeedSMCState *s, const char *flashtype, } } +static void sdhci_attach_drive(SDHCIState *sdhci, DriveInfo *dinfo) +{ + BlockBackend *blk; + DeviceState *card; + + blk = dinfo ? blk_by_legacy_dinfo(dinfo) : NULL; + card = qdev_create(qdev_get_child_bus(DEVICE(sdhci), "sd-bus"), + TYPE_SD_CARD); + qdev_prop_set_drive(card, "drive", blk, &error_fatal); + object_property_set_bool(OBJECT(card), true, "realized", &error_fatal); +} + static void aspeed_board_init(MachineState *machine, const AspeedBoardConfig *cfg) { @@ -260,16 +272,11 @@ static void aspeed_board_init(MachineState *machine, } for (i = 0; i < bmc->soc.sdhci.num_slots; i++) { - SDHCIState *sdhci = &bmc->soc.sdhci.slots[i]; - DriveInfo *dinfo = drive_get_next(IF_SD); - BlockBackend *blk; - DeviceState *card; + sdhci_attach_drive(&bmc->soc.sdhci.slots[i], drive_get_next(IF_SD)); + } - blk = dinfo ? blk_by_legacy_dinfo(dinfo) : NULL; - card = qdev_create(qdev_get_child_bus(DEVICE(sdhci), "sd-bus"), - TYPE_SD_CARD); - qdev_prop_set_drive(card, "drive", blk, &error_fatal); - object_property_set_bool(OBJECT(card), true, "realized", &error_fatal); + if (bmc->soc.emmc.num_slots) { + sdhci_attach_drive(&bmc->soc.emmc.slots[0], drive_get_next(IF_SD)); } arm_load_kernel(ARM_CPU(first_cpu), machine, &aspeed_board_binfo); diff --git a/hw/arm/aspeed_ast2600.c b/hw/arm/aspeed_ast2600.c index 931ee5aae183..723c8196c8a5 100644 --- a/hw/arm/aspeed_ast2600.c +++ b/hw/arm/aspeed_ast2600.c @@ -46,6 +46,7 @@ static const hwaddr aspeed_soc_ast2600_memmap[] = { [ASPEED_ADC] = 0x1E6E9000, [ASPEED_VIDEO] = 0x1E700000, [ASPEED_SDHCI] = 0x1E740000, + [ASPEED_EMMC] = 0x1E750000, [ASPEED_GPIO] = 0x1E780000, [ASPEED_GPIO_1_8V] = 0x1E780800, [ASPEED_RTC] = 0x1E781000, @@ -64,6 +65,7 @@ static const hwaddr aspeed_soc_ast2600_memmap[] = { #define ASPEED_SOC_AST2600_MAX_IRQ 128 +/* Shared Peripheral Interrupt values below are offset by -32 from datasheet */ static const int aspeed_soc_ast2600_irqmap[] = { [ASPEED_UART1] = 47, [ASPEED_UART2] = 48, @@ -77,6 +79,7 @@ static const int aspeed_soc_ast2600_irqmap[] = { [ASPEED_ADC] = 78, [ASPEED_XDMA] = 6, [ASPEED_SDHCI] = 43, + [ASPEED_EMMC] = 15, [ASPEED_GPIO] = 40, [ASPEED_GPIO_1_8V] = 11, [ASPEED_RTC] = 13, @@ -215,6 +218,14 @@ static void aspeed_soc_ast2600_init(Object *obj) sysbus_init_child_obj(obj, "sdhci[*]", OBJECT(&s->sdhci.slots[i]), sizeof(s->sdhci.slots[i]), TYPE_SYSBUS_SDHCI); } + + sysbus_init_child_obj(obj, "emmc", OBJECT(&s->emmc), sizeof(s->emmc), + TYPE_ASPEED_SDHCI); + + object_property_set_int(OBJECT(&s->emmc), 1, "num-slots", &error_abort); + + sysbus_init_child_obj(obj, "emmc[*]", OBJECT(&s->emmc.slots[0]), + sizeof(s->emmc.slots[0]), TYPE_SYSBUS_SDHCI); } /* @@ -487,6 +498,16 @@ static void aspeed_soc_ast2600_realize(DeviceState *dev, Error **errp) sc->memmap[ASPEED_SDHCI]); sysbus_connect_irq(SYS_BUS_DEVICE(&s->sdhci), 0, aspeed_soc_get_irq(s, ASPEED_SDHCI)); + + /* eMMC */ + object_property_set_bool(OBJECT(&s->emmc), true, "realized", &err); + if (err) { + error_propagate(errp, err); + return; + } + sysbus_mmio_map(SYS_BUS_DEVICE(&s->emmc), 0, sc->memmap[ASPEED_EMMC]); + sysbus_connect_irq(SYS_BUS_DEVICE(&s->emmc), 0, + aspeed_soc_get_irq(s, ASPEED_EMMC)); } static void aspeed_soc_ast2600_class_init(ObjectClass *oc, void *data) diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h index 495c08be1b84..911443f4c071 100644 --- a/include/hw/arm/aspeed_soc.h +++ b/include/hw/arm/aspeed_soc.h @@ -56,6 +56,7 @@ typedef struct AspeedSoCState { AspeedGPIOState gpio; AspeedGPIOState gpio_1_8v; AspeedSDHCIState sdhci; + AspeedSDHCIState emmc; } AspeedSoCState; #define TYPE_ASPEED_SOC "aspeed-soc" @@ -125,6 +126,7 @@ enum { ASPEED_MII4, ASPEED_SDRAM, ASPEED_XDMA, + ASPEED_EMMC, }; #endif /* ASPEED_SOC_H */ -- git-series 0.9.1 From MAILER-DAEMON Fri Dec 13 00:40:00 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1ifdgG-0007dQ-64 for mharc-qemu-arm@gnu.org; Fri, 13 Dec 2019 00:40:00 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:50459) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ifdgC-0007d8-Jm for qemu-arm@nongnu.org; Fri, 13 Dec 2019 00:39:58 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ifdg9-0004Ov-Rc for qemu-arm@nongnu.org; Fri, 13 Dec 2019 00:39:56 -0500 Received: from bilbo.ozlabs.org ([2401:3900:2:1::2]:45643 helo=ozlabs.org) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1ifdg9-0004HL-6R; Fri, 13 Dec 2019 00:39:53 -0500 Received: by ozlabs.org (Postfix, from userid 1007) id 47YzyC6x1Yz9sPL; Fri, 13 Dec 2019 16:39:47 +1100 (AEDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gibson.dropbear.id.au; s=201602; t=1576215587; bh=56eM89FTG1pvXviciouBwME2vyl4LJRakyHsbFicFXw=; h=Date:From:To:Cc:Subject:References:In-Reply-To:From; b=kW7q/l9rA2YfyK6wdsyyds/u3Yd01xGt3h2pnHPBDYewVEAh8AKG8/hDS6jk0qzT4 CLphEkUbeeuJ8f0uNB8oiX/tmeHt6wMgnGEroQZBSxCjUFpt3VleLa/nY0wCB/Bwfs HsVGTXY24nJi20QByygqhDomwDdl2PKDFZyQTVOg= Date: Fri, 13 Dec 2019 16:00:05 +1100 From: David Gibson To: Andrew Jones Cc: qemu-devel@nongnu.org, qemu-arm@nongnu.org, richard.henderson@linaro.org, peter.maydell@linaro.org, guoheyi@huawei.com, bijan.mottahedeh@oracle.com, maz@kernel.org, msys.mizuma@gmail.com, Eduardo Habkost , Marcel Apfelbaum , "Michael S. Tsirkin" , Paolo Bonzini , Richard Henderson , David Hildenbrand , Cornelia Huck , Halil Pasic , Christian Borntraeger , "open list:sPAPR" , "open list:S390 TCG CPUs" Subject: Re: [RFC PATCH v2 1/5] hw: add compat machines for 5.0 Message-ID: <20191213050005.GC207300@umbus.fritz.box> References: <20191212173320.11610-1-drjones@redhat.com> <20191212173320.11610-2-drjones@redhat.com> MIME-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha256; protocol="application/pgp-signature"; boundary="RyB1I56Pcq42iZjE" Content-Disposition: inline In-Reply-To: <20191212173320.11610-2-drjones@redhat.com> User-Agent: Mutt/1.12.1 (2019-06-15) X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2401:3900:2:1::2 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 13 Dec 2019 05:39:58 -0000 --RyB1I56Pcq42iZjE Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Content-Transfer-Encoding: quoted-printable On Thu, Dec 12, 2019 at 06:33:16PM +0100, Andrew Jones wrote: > Add 5.0 machine types for arm/i440fx/q35/s390x/spapr. >=20 > Signed-off-by: Andrew Jones ppc parts Acked-by: David Gibson >=20 > --- >=20 > Hi Eduardo, >=20 > If we need to do something special for i440fx and q35, as > 9aec2e52ce9d ("hw: add compat machines for 4.2") implies, then > I'll need guidance as to what. > --- > hw/arm/virt.c | 9 ++++++++- > hw/core/machine.c | 3 +++ > hw/i386/pc.c | 3 +++ > hw/i386/pc_piix.c | 14 +++++++++++++- > hw/i386/pc_q35.c | 13 ++++++++++++- > hw/ppc/spapr.c | 15 +++++++++++++-- > hw/s390x/s390-virtio-ccw.c | 15 ++++++++++++++- > include/hw/boards.h | 3 +++ > include/hw/i386/pc.h | 3 +++ > 9 files changed, 72 insertions(+), 6 deletions(-) >=20 > diff --git a/hw/arm/virt.c b/hw/arm/virt.c > index d4bedc260712..cb7041e9677a 100644 > --- a/hw/arm/virt.c > +++ b/hw/arm/virt.c > @@ -2147,10 +2147,17 @@ static void machvirt_machine_init(void) > } > type_init(machvirt_machine_init); > =20 > +static void virt_machine_5_0_options(MachineClass *mc) > +{ > +} > +DEFINE_VIRT_MACHINE_AS_LATEST(5, 0) > + > static void virt_machine_4_2_options(MachineClass *mc) > { > + virt_machine_5_0_options(mc); > + compat_props_add(mc->compat_props, hw_compat_4_2, hw_compat_4_2_len); > } > -DEFINE_VIRT_MACHINE_AS_LATEST(4, 2) > +DEFINE_VIRT_MACHINE(4, 2) > =20 > static void virt_machine_4_1_options(MachineClass *mc) > { > diff --git a/hw/core/machine.c b/hw/core/machine.c > index 1689ad3bf8af..21fe2d974817 100644 > --- a/hw/core/machine.c > +++ b/hw/core/machine.c > @@ -27,6 +27,9 @@ > #include "hw/pci/pci.h" > #include "hw/mem/nvdimm.h" > =20 > +GlobalProperty hw_compat_4_2[] =3D {}; > +const size_t hw_compat_4_2_len =3D G_N_ELEMENTS(hw_compat_4_2); > + > GlobalProperty hw_compat_4_1[] =3D { > { "virtio-pci", "x-pcie-flr-init", "off" }, > }; > diff --git a/hw/i386/pc.c b/hw/i386/pc.c > index ac08e6360437..58867f987d88 100644 > --- a/hw/i386/pc.c > +++ b/hw/i386/pc.c > @@ -103,6 +103,9 @@ > =20 > struct hpet_fw_config hpet_cfg =3D {.count =3D UINT8_MAX}; > =20 > +GlobalProperty pc_compat_4_2[] =3D {}; > +const size_t pc_compat_4_2_len =3D G_N_ELEMENTS(pc_compat_4_2); > + > GlobalProperty pc_compat_4_1[] =3D {}; > const size_t pc_compat_4_1_len =3D G_N_ELEMENTS(pc_compat_4_1); > =20 > diff --git a/hw/i386/pc_piix.c b/hw/i386/pc_piix.c > index 1bd70d1abbc4..aa2c6147a7ea 100644 > --- a/hw/i386/pc_piix.c > +++ b/hw/i386/pc_piix.c > @@ -424,7 +424,7 @@ static void pc_i440fx_machine_options(MachineClass *m) > machine_class_allow_dynamic_sysbus_dev(m, TYPE_RAMFB_DEVICE); > } > =20 > -static void pc_i440fx_4_2_machine_options(MachineClass *m) > +static void pc_i440fx_5_0_machine_options(MachineClass *m) > { > PCMachineClass *pcmc =3D PC_MACHINE_CLASS(m); > pc_i440fx_machine_options(m); > @@ -433,6 +433,18 @@ static void pc_i440fx_4_2_machine_options(MachineCla= ss *m) > pcmc->default_cpu_version =3D 1; > } > =20 > +DEFINE_I440FX_MACHINE(v5_0, "pc-i440fx-5.0", NULL, > + pc_i440fx_5_0_machine_options) > + > +static void pc_i440fx_4_2_machine_options(MachineClass *m) > +{ > + pc_i440fx_5_0_machine_options(m); > + m->alias =3D NULL; > + m->is_default =3D 0; > + compat_props_add(m->compat_props, hw_compat_4_2, hw_compat_4_2_len); > + compat_props_add(m->compat_props, pc_compat_4_2, pc_compat_4_2_len); > +} > + > DEFINE_I440FX_MACHINE(v4_2, "pc-i440fx-4.2", NULL, > pc_i440fx_4_2_machine_options); > =20 > diff --git a/hw/i386/pc_q35.c b/hw/i386/pc_q35.c > index 385e5cffb167..ddd485d608c0 100644 > --- a/hw/i386/pc_q35.c > +++ b/hw/i386/pc_q35.c > @@ -348,7 +348,7 @@ static void pc_q35_machine_options(MachineClass *m) > m->max_cpus =3D 288; > } > =20 > -static void pc_q35_4_2_machine_options(MachineClass *m) > +static void pc_q35_5_0_machine_options(MachineClass *m) > { > PCMachineClass *pcmc =3D PC_MACHINE_CLASS(m); > pc_q35_machine_options(m); > @@ -356,6 +356,17 @@ static void pc_q35_4_2_machine_options(MachineClass = *m) > pcmc->default_cpu_version =3D 1; > } > =20 > +DEFINE_Q35_MACHINE(v5_0, "pc-q35-5.0", NULL, > + pc_q35_5_0_machine_options); > + > +static void pc_q35_4_2_machine_options(MachineClass *m) > +{ > + pc_q35_5_0_machine_options(m); > + m->alias =3D NULL; > + compat_props_add(m->compat_props, hw_compat_4_2, hw_compat_4_2_len); > + compat_props_add(m->compat_props, pc_compat_4_2, pc_compat_4_2_len); > +} > + > DEFINE_Q35_MACHINE(v4_2, "pc-q35-4.2", NULL, > pc_q35_4_2_machine_options); > =20 > diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c > index e076f6023c73..3ae7db156303 100644 > --- a/hw/ppc/spapr.c > +++ b/hw/ppc/spapr.c > @@ -4491,15 +4491,26 @@ static const TypeInfo spapr_machine_info =3D { > } \ > type_init(spapr_machine_register_##suffix) > =20 > +/* > + * pseries-5.0 > + */ > +static void spapr_machine_5_0_class_options(MachineClass *mc) > +{ > + /* Defaults for the latest behaviour inherited from the base class */ > +} > + > +DEFINE_SPAPR_MACHINE(5_0, "5.0", true); > + > /* > * pseries-4.2 > */ > static void spapr_machine_4_2_class_options(MachineClass *mc) > { > - /* Defaults for the latest behaviour inherited from the base class */ > + spapr_machine_5_0_class_options(mc); > + compat_props_add(mc->compat_props, hw_compat_4_2, hw_compat_4_2_len); > } > =20 > -DEFINE_SPAPR_MACHINE(4_2, "4.2", true); > +DEFINE_SPAPR_MACHINE(4_2, "4.2", false); > =20 > /* > * pseries-4.1 > diff --git a/hw/s390x/s390-virtio-ccw.c b/hw/s390x/s390-virtio-ccw.c > index d3edeef0ad92..a40f79e20733 100644 > --- a/hw/s390x/s390-virtio-ccw.c > +++ b/hw/s390x/s390-virtio-ccw.c > @@ -639,14 +639,27 @@ bool css_migration_enabled(void) > } = \ > type_init(ccw_machine_register_##suffix) > =20 > + > +static void ccw_machine_5_0_instance_options(MachineState *machine) > +{ > +} > + > +static void ccw_machine_5_0_class_options(MachineClass *mc) > +{ > +} > +DEFINE_CCW_MACHINE(5_0, "5.0", true); > + > static void ccw_machine_4_2_instance_options(MachineState *machine) > { > + ccw_machine_5_0_instance_options(machine); > } > =20 > static void ccw_machine_4_2_class_options(MachineClass *mc) > { > + ccw_machine_5_0_class_options(mc); > + compat_props_add(mc->compat_props, hw_compat_4_2, hw_compat_4_2_len); > } > -DEFINE_CCW_MACHINE(4_2, "4.2", true); > +DEFINE_CCW_MACHINE(4_2, "4.2", false); > =20 > static void ccw_machine_4_1_instance_options(MachineState *machine) > { > diff --git a/include/hw/boards.h b/include/hw/boards.h > index de45087f34cb..24cbeecbaecc 100644 > --- a/include/hw/boards.h > +++ b/include/hw/boards.h > @@ -329,6 +329,9 @@ struct MachineState { > } \ > type_init(machine_initfn##_register_types) > =20 > +extern GlobalProperty hw_compat_4_2[]; > +extern const size_t hw_compat_4_2_len; > + > extern GlobalProperty hw_compat_4_1[]; > extern const size_t hw_compat_4_1_len; > =20 > diff --git a/include/hw/i386/pc.h b/include/hw/i386/pc.h > index 1f86eba3f998..61a998de4665 100644 > --- a/include/hw/i386/pc.h > +++ b/include/hw/i386/pc.h > @@ -237,6 +237,9 @@ void pc_system_firmware_init(PCMachineState *pcms, Me= moryRegion *rom_memory); > void pc_madt_cpu_entry(AcpiDeviceIf *adev, int uid, > const CPUArchIdList *apic_ids, GArray *entry); > =20 > +extern GlobalProperty pc_compat_4_2[]; > +extern const size_t pc_compat_4_2_len; > + > extern GlobalProperty pc_compat_4_1[]; > extern const size_t pc_compat_4_1_len; > =20 --=20 David Gibson | I'll have my music baroque, and my code david AT gibson.dropbear.id.au | minimalist, thank you. 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The AST2600 clocks the generic timer at the rate of HPLL, which is configured to 1125MHz. This is significantly quicker than the currently hard-coded generic timer rate of 62.5MHz and so we see "sticky" behaviour in the guest. v2 can be found here: https://patchwork.ozlabs.org/cover/1203474/ Changes since v2: * Address some minor review comments from Philippe and add tags Changes since v1: * Fix a user mode build failure from partial renaming of gt_cntfrq_period_ns() * Add tags from Cedric and Richard Please review. Andrew Andrew Jeffery (4): target/arm: Remove redundant scaling of nexttick target/arm: Abstract the generic timer frequency target/arm: Prepare generic timer for per-platform CNTFRQ ast2600: Configure CNTFRQ at 1125MHz hw/arm/aspeed_ast2600.c | 3 ++- target/arm/cpu.c | 65 ++++++++++++++++++++++++++++++++++++------ target/arm/cpu.h | 5 +++- target/arm/helper.c | 24 ++++++++++++---- 4 files changed, 83 insertions(+), 14 deletions(-) base-commit: 04c9c81b8fa2ee33f59a26265700fae6fc646062 -- git-series 0.9.1 From MAILER-DAEMON Fri Dec 13 00:48:50 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1ifdoo-000319-R0 for mharc-qemu-arm@gnu.org; Fri, 13 Dec 2019 00:48:50 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:54929) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ifdol-0002yj-IP for qemu-arm@nongnu.org; Fri, 13 Dec 2019 00:48:48 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ifdok-0004fw-9w for qemu-arm@nongnu.org; Fri, 13 Dec 2019 00:48:47 -0500 Received: from wout3-smtp.messagingengine.com ([64.147.123.19]:55527) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1ifdok-0004eA-2a; Fri, 13 Dec 2019 00:48:46 -0500 Received: from compute4.internal (compute4.nyi.internal [10.202.2.44]) by mailout.west.internal (Postfix) with ESMTP id C76068F7; Fri, 13 Dec 2019 00:48:44 -0500 (EST) Received: from mailfrontend1 ([10.202.2.162]) by compute4.internal (MEProxy); Fri, 13 Dec 2019 00:48:45 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=aj.id.au; h=from :to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-type:content-transfer-encoding; s=fm1; bh= 1UCByQUYAsPHw0TDr/9tqYqfBlUQ9Y9+Vdyqo8I6jT0=; b=Mog8UeNjUGLCDyBb 0uRLdhuWZ0qlfpi5XASc7z8WWwpSyFQ7pN2floLJa+a3B0ZAKwloarK9oZ9e0hzY /vhVvOSHPe/HGi3xIncIMthFqvmgJxUELYeivAuNKMmc8un43wE7g1Xv5d0XNlRJ w7u4Awg71DC+EHHiMp6amC3aKVNzVUvoFnoB7JVIt80rTiB3j7cERJt+71qwtzwz 3w1k5yCcxfV66EW5CkMM1W1qkZFdenj/Th9QJ696WVfCULl96tRNPYxs5sIrPv0u g0/yH6KORo9qYNv4Sx3FYsPLjObEYY35aHqRJ7HYwhhgzYEaGOlhYtU950F7nbik MDPDVQ== DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d= messagingengine.com; h=cc:content-transfer-encoding:content-type :date:from:in-reply-to:message-id:mime-version:references :subject:to:x-me-proxy:x-me-proxy:x-me-sender:x-me-sender :x-sasl-enc; s=fm1; bh=1UCByQUYAsPHw0TDr/9tqYqfBlUQ9Y9+Vdyqo8I6j T0=; b=huNnvZ+Q+4YfRQUYbw+RYsKYGLgs/h5sW/7Lcjf2/b8/mNZEIDLhCAI7d Y0ZbojLikiX8c6MWiQBCr9DPkWviEEdf8xqDb2KMyLprfrMoiKVDUREqw/d5E5Q+ Ol8L7V2lC04dPiGFK28O7RZA4sCXuF3JbTU63O64c8rUAx0CO2199Trxt7jDQW2k WAaVZiKVj6M5YRrxkXTQdYuc90wz/MsJniu9N/c+mAq0zjC5XOeyxBGcBiaKdt/O +6rZup5oDrLFackU4BXDd46wp37guwchJ1QT0wJnlAaDqaUoucpyHr86PzsSy+7C LWAjQLPsElhSTHgk/CTbg2yzwokXg== X-ME-Sender: X-ME-Proxy-Cause: gggruggvucftvghtrhhoucdtuddrgedufedrudelkedgkeejucetufdoteggodetrfdotf fvucfrrhhofhhilhgvmecuhfgrshhtofgrihhlpdfqfgfvpdfurfetoffkrfgpnffqhgen uceurghilhhouhhtmecufedttdenucesvcftvggtihhpihgvnhhtshculddquddttddmne cujfgurhephffvufffkffojghfgggtgfesthekredtredtjeenucfhrhhomheptehnughr vgifucflvghffhgvrhihuceorghnughrvgifsegrjhdrihgurdgruheqnecukfhppedvtd dvrdekuddrudekrdeftdenucfrrghrrghmpehmrghilhhfrhhomheprghnughrvgifsegr jhdrihgurdgruhenucevlhhushhtvghrufhiiigvpedt X-ME-Proxy: Received: from mistburn.au.ibm.com (bh02i525f01.au.ibm.com [202.81.18.30]) by mail.messagingengine.com (Postfix) with ESMTPA id 4C6DE80060; Fri, 13 Dec 2019 00:48:41 -0500 (EST) From: Andrew Jeffery To: qemu-arm@nongnu.org Cc: clg@kaod.org, peter.maydell@linaro.org, joel@jms.id.au, qemu-devel@nongnu.org, philmd@redhat.com, Richard Henderson Subject: [PATCH v3 1/4] target/arm: Remove redundant scaling of nexttick Date: Fri, 13 Dec 2019 16:19:48 +1030 Message-Id: X-Mailer: git-send-email 2.20.1 In-Reply-To: References: MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 64.147.123.19 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 13 Dec 2019 05:48:48 -0000 The corner-case codepath was adjusting nexttick such that overflow wouldn't occur when timer_mod() scaled the value back up. Remove a use of GTIMER_SCALE and avoid unnecessary operations by calling timer_mod_ns() directly. Signed-off-by: Andrew Jeffery Reviewed-by: Richard Henderson Reviewed-by: Cédric Le Goater --- target/arm/helper.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index a089fb5a6909..65c4441a3896 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -2446,9 +2446,10 @@ static void gt_recalc_timer(ARMCPU *cpu, int timeridx) * timer expires we will reset the timer for any remaining period. */ if (nexttick > INT64_MAX / GTIMER_SCALE) { - nexttick = INT64_MAX / GTIMER_SCALE; + timer_mod_ns(cpu->gt_timer[timeridx], INT64_MAX); + } else { + timer_mod(cpu->gt_timer[timeridx], nexttick); } - timer_mod(cpu->gt_timer[timeridx], nexttick); trace_arm_gt_recalc(timeridx, irqstate, nexttick); } else { /* Timer disabled: ISTATUS and timer output always clear */ -- git-series 0.9.1 From MAILER-DAEMON Fri Dec 13 00:48:55 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1ifdot-00038d-Gp for mharc-qemu-arm@gnu.org; Fri, 13 Dec 2019 00:48:55 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:55660) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ifdop-000324-ET for qemu-arm@nongnu.org; Fri, 13 Dec 2019 00:48:52 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ifdoo-0004o7-2x for qemu-arm@nongnu.org; Fri, 13 Dec 2019 00:48:51 -0500 Received: from wout3-smtp.messagingengine.com ([64.147.123.19]:58197) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1ifdon-0004mH-O7; Fri, 13 Dec 2019 00:48:49 -0500 Received: from compute4.internal (compute4.nyi.internal [10.202.2.44]) by mailout.west.internal (Postfix) with ESMTP id 70A828F2; Fri, 13 Dec 2019 00:48:48 -0500 (EST) Received: from mailfrontend1 ([10.202.2.162]) by compute4.internal (MEProxy); Fri, 13 Dec 2019 00:48:48 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=aj.id.au; h=from :to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-type:content-transfer-encoding; s=fm1; bh= lF/a3idVNwHnX0XK1rPPf8+9v2Pnt27BJWxzuIfged8=; b=AJOpj6G8P9YissdJ FPD3Nm4ILZwz8ByQTI93Rd2pAS4j8K5JyQkeO72C9ZhpnD5P1cs0tE+8fp9gSI0A 2EzVAA0l/LBvN227uKbRa0tvSN9UOFrAclrvOvuLeBIdkchg2tnivl1PWGpP0GUl HGllpmgY5QudDS1oROw27lOLq9pN50mpxr+Bz5JbptnI7XO5c/4JzZgUl8Xc6ygk QKfmeLqBMFh2aGqOBF9DtdTYaVb/Wj+0JxyXTh4JDP5mpbSIw7gI6f5ESxQAefyH y2n6aZyAPubLE7nHFyKl+d9DEcMFaI4//joQPUk8JSjXua2T39GfdGcbL1eSWkMU Wlw55g== DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d= messagingengine.com; h=cc:content-transfer-encoding:content-type :date:from:in-reply-to:message-id:mime-version:references :subject:to:x-me-proxy:x-me-proxy:x-me-sender:x-me-sender :x-sasl-enc; s=fm1; bh=lF/a3idVNwHnX0XK1rPPf8+9v2Pnt27BJWxzuIfge d8=; b=P4wu3xWK7FbQ6oZtsvBR5BkeS4iYwWthQX18IUMzPjkb7ZMQo2NTjlzKo lufqw4vGzpWEXZlwz2wiV7f8C3J4uP7uLbkRx6IEiIOOfnpHwu7Vu8UrdIAgkflE tv9QmhRthHzjnNH5uHe2DJYbGrOJ1cYCQoVmjj1+i/J+qPqBIT2g/kxmHRY0IFuS FZOUkvebFxQ0s5geC8EeTghQQ+jSvqoqjGvHoXY4ge6B3rFUTSj9isMUYgpfjSHH AbWY4+p1pDSCSydNEszeONquJFcV6oXXr34oRjnA/MdwrY0oOtdcibCTgipXMMvE +7n2vv2dPPgBV3DV2mUPNqVUynVpg== X-ME-Sender: X-ME-Proxy-Cause: gggruggvucftvghtrhhoucdtuddrgedufedrudelkedgkeejucetufdoteggodetrfdotf fvucfrrhhofhhilhgvmecuhfgrshhtofgrihhlpdfqfgfvpdfurfetoffkrfgpnffqhgen uceurghilhhouhhtmecufedttdenucesvcftvggtihhpihgvnhhtshculddquddttddmne cujfgurhephffvufffkffojghfgggtgfesthekredtredtjeenucfhrhhomheptehnughr vgifucflvghffhgvrhihuceorghnughrvgifsegrjhdrihgurdgruheqnecukfhppedvtd dvrdekuddrudekrdeftdenucfrrghrrghmpehmrghilhhfrhhomheprghnughrvgifsegr jhdrihgurdgruhenucevlhhushhtvghrufhiiigvpedu X-ME-Proxy: Received: from mistburn.au.ibm.com (bh02i525f01.au.ibm.com [202.81.18.30]) by mail.messagingengine.com (Postfix) with ESMTPA id C76D180063; Fri, 13 Dec 2019 00:48:44 -0500 (EST) From: Andrew Jeffery To: qemu-arm@nongnu.org Cc: clg@kaod.org, peter.maydell@linaro.org, joel@jms.id.au, qemu-devel@nongnu.org, philmd@redhat.com, Richard Henderson Subject: [PATCH v3 2/4] target/arm: Abstract the generic timer frequency Date: Fri, 13 Dec 2019 16:19:49 +1030 Message-Id: <40bd8df043f66e1ccfb3e9482999d099ac72bb2e.1576215453.git-series.andrew@aj.id.au> X-Mailer: git-send-email 2.20.1 In-Reply-To: References: MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 64.147.123.19 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 13 Dec 2019 05:48:53 -0000 Prepare for SoCs such as the ASPEED AST2600 whose firmware configures CNTFRQ to values significantly larger than the static 62.5MHz value currently derived from GTIMER_SCALE. As the OS potentially derives its timer periods from the CNTFRQ value the lack of support for running QEMUTimers at the appropriate rate leads to sticky behaviour in the guest. Substitute the GTIMER_SCALE constant with use of a helper to derive the period from gt_cntfrq_hz stored in struct ARMCPU. Initially set gt_cntfrq_hz to the frequency associated with GTIMER_SCALE so current behaviour is maintained. Signed-off-by: Andrew Jeffery Reviewed-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daudé --- v3: * Uninline gt_cntfrq_period_ns() * Rename gt_cntfrq to gt_cntfrq_hz target/arm/cpu.c | 8 ++++++++ target/arm/cpu.h | 5 +++++ target/arm/helper.c | 10 +++++++--- 3 files changed, 20 insertions(+), 3 deletions(-) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 7a4ac9339bf9..cd0dbe005d9f 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -974,6 +974,8 @@ static void arm_cpu_initfn(Object *obj) if (tcg_enabled()) { cpu->psci_version = 2; /* TCG implements PSCI 0.2 */ } + + cpu->gt_cntfrq_hz = NANOSECONDS_PER_SECOND / GTIMER_SCALE; } static Property arm_cpu_reset_cbar_property = @@ -1055,6 +1057,12 @@ static void arm_set_init_svtor(Object *obj, Visitor *v, const char *name, visit_type_uint32(v, name, &cpu->init_svtor, errp); } +unsigned int gt_cntfrq_period_ns(ARMCPU *cpu) +{ + return NANOSECONDS_PER_SECOND > cpu->gt_cntfrq_hz ? + NANOSECONDS_PER_SECOND / cpu->gt_cntfrq_hz : 1; +} + void arm_cpu_post_init(Object *obj) { ARMCPU *cpu = ARM_CPU(obj); diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 83a809d4bac4..ff17ec0df545 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -932,8 +932,13 @@ struct ARMCPU { */ DECLARE_BITMAP(sve_vq_map, ARM_MAX_VQ); DECLARE_BITMAP(sve_vq_init, ARM_MAX_VQ); + + /* Generic timer counter frequency, in Hz */ + uint64_t gt_cntfrq_hz; }; +unsigned int gt_cntfrq_period_ns(ARMCPU *cpu); + void arm_cpu_post_init(Object *obj); uint64_t arm_cpu_mp_affinity(int idx, uint8_t clustersz); diff --git a/target/arm/helper.c b/target/arm/helper.c index 65c4441a3896..2622a9a8d02f 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -2409,7 +2409,9 @@ static CPAccessResult gt_stimer_access(CPUARMState *env, static uint64_t gt_get_countervalue(CPUARMState *env) { - return qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) / GTIMER_SCALE; + ARMCPU *cpu = env_archcpu(env); + + return qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) / gt_cntfrq_period_ns(cpu); } static void gt_recalc_timer(ARMCPU *cpu, int timeridx) @@ -2445,7 +2447,7 @@ static void gt_recalc_timer(ARMCPU *cpu, int timeridx) * set the timer for as far in the future as possible. When the * timer expires we will reset the timer for any remaining period. */ - if (nexttick > INT64_MAX / GTIMER_SCALE) { + if (nexttick > INT64_MAX / gt_cntfrq_period_ns(cpu)) { timer_mod_ns(cpu->gt_timer[timeridx], INT64_MAX); } else { timer_mod(cpu->gt_timer[timeridx], nexttick); @@ -2874,11 +2876,13 @@ static const ARMCPRegInfo generic_timer_cp_reginfo[] = { static uint64_t gt_virt_cnt_read(CPUARMState *env, const ARMCPRegInfo *ri) { + ARMCPU *cpu = env_archcpu(env); + /* Currently we have no support for QEMUTimer in linux-user so we * can't call gt_get_countervalue(env), instead we directly * call the lower level functions. */ - return cpu_get_clock() / GTIMER_SCALE; + return cpu_get_clock() / gt_cntfrq_period_ns(cpu); } static const ARMCPRegInfo generic_timer_cp_reginfo[] = { -- git-series 0.9.1 From MAILER-DAEMON Fri Dec 13 00:48:58 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1ifdow-0003DB-F8 for mharc-qemu-arm@gnu.org; Fri, 13 Dec 2019 00:48:58 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:56343) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ifdos-00037n-VM for qemu-arm@nongnu.org; Fri, 13 Dec 2019 00:48:56 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ifdor-0004v6-F2 for qemu-arm@nongnu.org; Fri, 13 Dec 2019 00:48:54 -0500 Received: from wout3-smtp.messagingengine.com ([64.147.123.19]:37341) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1ifdor-0004tR-7N; Fri, 13 Dec 2019 00:48:53 -0500 Received: from compute4.internal (compute4.nyi.internal [10.202.2.44]) by mailout.west.internal (Postfix) with ESMTP id E226890C; Fri, 13 Dec 2019 00:48:51 -0500 (EST) Received: from mailfrontend1 ([10.202.2.162]) by compute4.internal (MEProxy); Fri, 13 Dec 2019 00:48:52 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=aj.id.au; h=from :to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; s=fm1; bh=gNZ9DXDMNR7Ep JAh12OKvhgw7oyqCMhiE3JvRC5PYi4=; b=F9z4/wmlnuMoEM8t3BpJwYqegqG9X l5MYDk1Q+9wp1vL9o/jYbPb+9Rq5vlauosaKqFOPboOJOiFDfV3G6r+FLwuYfSa9 E2dTDYKVwewMidtzTeYzm2JmAqek86JIjsmiaIar+YFbc8zbaBtQt24j7YkjoO+T RhzpFC6HEydyZktcjkEV5EM7efkw6t9hm2wPPM3bg7YDRZFlu5+r6tMfT3PMjXxw nbmFx8vxfvtrBM700q9MRSZlCKOnkSzXxksREtKE9F1xx0jfckGPTUDhthqWW33C A/3/pLK/sqkdjW62RA231xQh0hfoiQ4nKFqWXBOdvfqZhmE9QpueQuLuQ== DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d= messagingengine.com; h=cc:content-transfer-encoding:date:from :in-reply-to:message-id:mime-version:references:subject:to :x-me-proxy:x-me-proxy:x-me-sender:x-me-sender:x-sasl-enc; s= fm1; bh=gNZ9DXDMNR7EpJAh12OKvhgw7oyqCMhiE3JvRC5PYi4=; b=b5PJu6cm yvHUmvH1n0U8Enp1QB0jNq+4crZddxjabwf32CLZFM4a7E08UVwys6x5+rZY/rwk xwP18oHvqZF6OI+9+CNXjD8CboI/RkglPMqYOJ659Swz+7nsvdExLr+fKeQrn01U 9/4NfwQWMZDqiHUaDf2CbWsT3tQjIYgoD0oDwc/NHQPnikxVMpmXflaVMxnQK15+ qAQsBhvfjJ/vhpqjD4IgM6eGJvX113/6Yx9969FqmgsmuWgWfaQpXpeenHjlw8E+ bb9TnDBxWX4ypam124dh163fl8k3yUuLQKI7XjPswhViSg5PFUSoOwGf9Nn2XorE qxbg08B4TPOpMQ== X-ME-Sender: X-ME-Proxy-Cause: gggruggvucftvghtrhhoucdtuddrgedufedrudelkedgkeejucetufdoteggodetrfdotf fvucfrrhhofhhilhgvmecuhfgrshhtofgrihhlpdfqfgfvpdfurfetoffkrfgpnffqhgen uceurghilhhouhhtmecufedttdenucesvcftvggtihhpihgvnhhtshculddquddttddmne cujfgurhephffvufffkffojghfggfgsedtkeertdertddtnecuhfhrohhmpeetnhgurhgv ficulfgvfhhfvghrhicuoegrnhgurhgvfiesrghjrdhiugdrrghuqeenucffohhmrghinh epthgrghdrthgrrhhgvghtnecukfhppedvtddvrdekuddrudekrdeftdenucfrrghrrghm pehmrghilhhfrhhomheprghnughrvgifsegrjhdrihgurdgruhenucevlhhushhtvghruf hiiigvpedt X-ME-Proxy: Received: from mistburn.au.ibm.com (bh02i525f01.au.ibm.com [202.81.18.30]) by mail.messagingengine.com (Postfix) with ESMTPA id 61DDE80060; Fri, 13 Dec 2019 00:48:48 -0500 (EST) From: Andrew Jeffery To: qemu-arm@nongnu.org Cc: clg@kaod.org, peter.maydell@linaro.org, joel@jms.id.au, qemu-devel@nongnu.org, philmd@redhat.com, Richard Henderson Subject: [PATCH v3 3/4] target/arm: Prepare generic timer for per-platform CNTFRQ Date: Fri, 13 Dec 2019 16:19:50 +1030 Message-Id: X-Mailer: git-send-email 2.20.1 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 64.147.123.19 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 13 Dec 2019 05:48:57 -0000 The ASPEED AST2600 clocks the generic timer at the rate of HPLL. On recent firmwares this is at 1125MHz, which is considerably quicker than the assumed 62.5MHz of the current generic timer implementation. The delta between the value as read from CNTFRQ and the true rate of the underlying QEMUTimer leads to sticky behaviour in AST2600 guests. Add a feature-gated property exposing CNTFRQ for ARM CPUs providing the generic timer. This allows platforms to configure CNTFRQ (and the associated QEMUTimer) to the appropriate frequency prior to starting the guest. As the platform can now determine the rate of CNTFRQ we're exposed to limitations of QEMUTimer that didn't previously materialise: In the course of emulation we need to arbitrarily and accurately convert between guest ticks and time, but we're constrained by QEMUTimer's use of an integer scaling factor. The effect is QEMUTimer cannot exactly capture the period of frequencies that do not cleanly divide NANOSECONDS_PER_SECOND for scaling ticks to time. As such, provide an equally inaccurate scaling factor for scaling time to ticks so at least a self-consistent inverse relationship holds. Signed-off-by: Andrew Jeffery Reviewed-by: Richard Henderson --- v3: * Relocate comment as a consequence of uninlining gt_cntfrq_period_ns() in 2/4. Philippe - I haven't moved it to the previous patch based on my reasoning on the list. I'm not sure whether you're satisfied by that, so I haven't added your Reviewed-by tag. target/arm/cpu.c | 61 ++++++++++++++++++++++++++++++++++++++-------- target/arm/helper.c | 9 ++++++- 2 files changed, 59 insertions(+), 11 deletions(-) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index cd0dbe005d9f..7b21eb544eae 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -974,10 +974,12 @@ static void arm_cpu_initfn(Object *obj) if (tcg_enabled()) { cpu->psci_version = 2; /* TCG implements PSCI 0.2 */ } - - cpu->gt_cntfrq_hz = NANOSECONDS_PER_SECOND / GTIMER_SCALE; } +static Property arm_cpu_gt_cntfrq_property = + DEFINE_PROP_UINT64("cntfrq", ARMCPU, gt_cntfrq_hz, + NANOSECONDS_PER_SECOND / GTIMER_SCALE); + static Property arm_cpu_reset_cbar_property = DEFINE_PROP_UINT64("reset-cbar", ARMCPU, reset_cbar, 0); @@ -1059,6 +1061,24 @@ static void arm_set_init_svtor(Object *obj, Visitor *v, const char *name, unsigned int gt_cntfrq_period_ns(ARMCPU *cpu) { + /* + * The exact approach to calculating guest ticks is: + * + * muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), cpu->gt_cntfrq_hz, + * NANOSECONDS_PER_SECOND); + * + * We don't do that. Rather we intentionally use integer division + * truncation below and in the caller for the conversion of host monotonic + * time to guest ticks to provide the exact inverse for the semantics of + * the QEMUTimer scale factor. QEMUTimer's scale facter is an integer, so + * it loses precision when representing frequencies where + * `(NANOSECONDS_PER_SECOND % cpu->gt_cntfrq) > 0` holds. Failing to + * provide an exact inverse leads to scheduling timers with negative + * periods, which in turn leads to sticky behaviour in the guest. + * + * Finally, CNTFRQ is effectively capped at 1GHz to ensure our scale factor + * cannot become zero. + */ return NANOSECONDS_PER_SECOND > cpu->gt_cntfrq_hz ? NANOSECONDS_PER_SECOND / cpu->gt_cntfrq_hz : 1; } @@ -1180,6 +1200,11 @@ void arm_cpu_post_init(Object *obj) qdev_property_add_static(DEVICE(obj), &arm_cpu_cfgend_property, &error_abort); + + if (arm_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER)) { + qdev_property_add_static(DEVICE(cpu), &arm_cpu_gt_cntfrq_property, + &error_abort); + } } static void arm_cpu_finalizefn(Object *obj) @@ -1259,14 +1284,30 @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp) } } - cpu->gt_timer[GTIMER_PHYS] = timer_new(QEMU_CLOCK_VIRTUAL, GTIMER_SCALE, - arm_gt_ptimer_cb, cpu); - cpu->gt_timer[GTIMER_VIRT] = timer_new(QEMU_CLOCK_VIRTUAL, GTIMER_SCALE, - arm_gt_vtimer_cb, cpu); - cpu->gt_timer[GTIMER_HYP] = timer_new(QEMU_CLOCK_VIRTUAL, GTIMER_SCALE, - arm_gt_htimer_cb, cpu); - cpu->gt_timer[GTIMER_SEC] = timer_new(QEMU_CLOCK_VIRTUAL, GTIMER_SCALE, - arm_gt_stimer_cb, cpu); + + { + uint64_t scale; + + if (arm_feature(env, ARM_FEATURE_GENERIC_TIMER)) { + if (!cpu->gt_cntfrq_hz) { + error_setg(errp, "Invalid CNTFRQ: %"PRId64"Hz", + cpu->gt_cntfrq_hz); + return; + } + scale = gt_cntfrq_period_ns(cpu); + } else { + scale = GTIMER_SCALE; + } + + cpu->gt_timer[GTIMER_PHYS] = timer_new(QEMU_CLOCK_VIRTUAL, scale, + arm_gt_ptimer_cb, cpu); + cpu->gt_timer[GTIMER_VIRT] = timer_new(QEMU_CLOCK_VIRTUAL, scale, + arm_gt_vtimer_cb, cpu); + cpu->gt_timer[GTIMER_HYP] = timer_new(QEMU_CLOCK_VIRTUAL, scale, + arm_gt_htimer_cb, cpu); + cpu->gt_timer[GTIMER_SEC] = timer_new(QEMU_CLOCK_VIRTUAL, scale, + arm_gt_stimer_cb, cpu); + } #endif cpu_exec_realizefn(cs, &local_err); diff --git a/target/arm/helper.c b/target/arm/helper.c index 2622a9a8d02f..94a05cd978bc 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -2683,6 +2683,13 @@ void arm_gt_stimer_cb(void *opaque) gt_recalc_timer(cpu, GTIMER_SEC); } +static void arm_gt_cntfrq_reset(CPUARMState *env, const ARMCPRegInfo *opaque) +{ + ARMCPU *cpu = env_archcpu(env); + + cpu->env.cp15.c14_cntfrq = cpu->gt_cntfrq_hz; +} + static const ARMCPRegInfo generic_timer_cp_reginfo[] = { /* Note that CNTFRQ is purely reads-as-written for the benefit * of software; writing it doesn't actually change the timer frequency. @@ -2697,7 +2704,7 @@ static const ARMCPRegInfo generic_timer_cp_reginfo[] = { .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 0, .opc2 = 0, .access = PL1_RW | PL0_R, .accessfn = gt_cntfrq_access, .fieldoffset = offsetof(CPUARMState, cp15.c14_cntfrq), - .resetvalue = (1000 * 1000 * 1000) / GTIMER_SCALE, + .resetfn = arm_gt_cntfrq_reset, }, /* overall control: mostly access permissions */ { .name = "CNTKCTL", .state = ARM_CP_STATE_BOTH, -- git-series 0.9.1 From MAILER-DAEMON Fri Dec 13 00:49:01 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1ifdoz-0003I7-NQ for mharc-qemu-arm@gnu.org; Fri, 13 Dec 2019 00:49:01 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:56914) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ifdov-0003CN-Sq for qemu-arm@nongnu.org; Fri, 13 Dec 2019 00:48:58 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ifdou-00052G-U1 for qemu-arm@nongnu.org; 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Fri, 13 Dec 2019 00:48:51 -0500 (EST) From: Andrew Jeffery To: qemu-arm@nongnu.org Cc: clg@kaod.org, peter.maydell@linaro.org, joel@jms.id.au, qemu-devel@nongnu.org, philmd@redhat.com, Richard Henderson Subject: [PATCH v3 4/4] ast2600: Configure CNTFRQ at 1125MHz Date: Fri, 13 Dec 2019 16:19:51 +1030 Message-Id: <080ca1267a09381c43cf3c50d434fb6c186f2b6e.1576215453.git-series.andrew@aj.id.au> X-Mailer: git-send-email 2.20.1 In-Reply-To: References: MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 64.147.123.19 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 13 Dec 2019 05:49:00 -0000 This matches the configuration set by u-boot on the AST2600. Signed-off-by: Andrew Jeffery Reviewed-by: Richard Henderson Reviewed-by: Cédric Le Goater Reviewed-by: Philippe Mathieu-Daudé --- hw/arm/aspeed_ast2600.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/hw/arm/aspeed_ast2600.c b/hw/arm/aspeed_ast2600.c index 931887ac681f..5aecc3b3caec 100644 --- a/hw/arm/aspeed_ast2600.c +++ b/hw/arm/aspeed_ast2600.c @@ -259,6 +259,9 @@ static void aspeed_soc_ast2600_realize(DeviceState *dev, Error **errp) object_property_set_int(OBJECT(&s->cpu[i]), aspeed_calc_affinity(i), "mp-affinity", &error_abort); + object_property_set_int(OBJECT(&s->cpu[i]), 1125000000, "cntfrq", + &error_abort); + /* * TODO: the secondary CPUs are started and a boot helper * is needed when using -kernel -- git-series 0.9.1 From MAILER-DAEMON Fri Dec 13 02:11:09 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1iff6T-0005wX-De for mharc-qemu-arm@gnu.org; Fri, 13 Dec 2019 02:11:09 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:57913) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iff6Q-0005vL-Gu for qemu-arm@nongnu.org; Fri, 13 Dec 2019 02:11:07 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1iff6N-0001KE-OT for qemu-arm@nongnu.org; Fri, 13 Dec 2019 02:11:04 -0500 Received: from us-smtp-1.mimecast.com ([205.139.110.61]:59308 helo=us-smtp-delivery-1.mimecast.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1iff6N-0001Ic-5u for qemu-arm@nongnu.org; Fri, 13 Dec 2019 02:11:03 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1576221062; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=8Z9481crTfuDxmQqSMOjo03EDWmMJej6UDt1Ym4TNGM=; b=B+3bUnuaaimNMxBWNX9DmtDJqbhW4M6Tj+iOOYG/61EVj05/3s0dHHLOPvQZkU46ZCrAEe WI+0X6hHpEJGmb9ox7dSt0mxJTD2Yl7IJGcfoymKIvXmdPDIv6uYRIdfXx5kWsHm5aWRYe jGZkuwzi5izSdLhkDFxypJPOwRckvFc= Received: from mimecast-mx01.redhat.com (mimecast-mx01.redhat.com [209.132.183.4]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-376-vFNZT84jOtOlevkhw20ZoA-1; Fri, 13 Dec 2019 02:10:58 -0500 Received: from smtp.corp.redhat.com (int-mx01.intmail.prod.int.phx2.redhat.com [10.5.11.11]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx01.redhat.com (Postfix) with ESMTPS id 38444100550E; Fri, 13 Dec 2019 07:10:56 +0000 (UTC) Received: from kamzik.brq.redhat.com (ovpn-204-115.brq.redhat.com [10.40.204.115]) by smtp.corp.redhat.com (Postfix) with ESMTPS id D5CC160474; Fri, 13 Dec 2019 07:10:44 +0000 (UTC) Date: Fri, 13 Dec 2019 08:10:40 +0100 From: Andrew Jones To: Eduardo Habkost Cc: peter.maydell@linaro.org, Cornelia Huck , bijan.mottahedeh@oracle.com, "Michael S. Tsirkin" , maz@kernel.org, David Hildenbrand , richard.henderson@linaro.org, qemu-devel@nongnu.org, Halil Pasic , Christian Borntraeger , "open list:S390 TCG CPUs" , qemu-arm@nongnu.org, "open list:sPAPR" , David Gibson , guoheyi@huawei.com, Paolo Bonzini , msys.mizuma@gmail.com, Richard Henderson Subject: Re: [RFC PATCH v2 1/5] hw: add compat machines for 5.0 Message-ID: <20191213071040.mc52d5mnezedyc54@kamzik.brq.redhat.com> References: <20191212173320.11610-1-drjones@redhat.com> <20191212173320.11610-2-drjones@redhat.com> <20191212192419.GB498046@habkost.net> MIME-Version: 1.0 In-Reply-To: <20191212192419.GB498046@habkost.net> X-Scanned-By: MIMEDefang 2.79 on 10.5.11.11 X-MC-Unique: vFNZT84jOtOlevkhw20ZoA-1 X-Mimecast-Spam-Score: 0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: quoted-printable Content-Disposition: inline X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 205.139.110.61 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 13 Dec 2019 07:11:07 -0000 On Thu, Dec 12, 2019 at 04:24:19PM -0300, Eduardo Habkost wrote: > On Thu, Dec 12, 2019 at 06:33:16PM +0100, Andrew Jones wrote: > > Add 5.0 machine types for arm/i440fx/q35/s390x/spapr. > >=20 > > Signed-off-by: Andrew Jones > >=20 > > --- > >=20 > > Hi Eduardo, > >=20 > > If we need to do something special for i440fx and q35, as > > 9aec2e52ce9d ("hw: add compat machines for 4.2") implies, then > > I'll need guidance as to what. >=20 > Keeping default_cpu_version=3D=3D1 in pc-*-5.0 (like you did) is > correct. >=20 > However, you might want to use Cornelia's patch (which is > probably already queued in the s390 tree) instead: > https://patchew.org/QEMU/20191112104811.30323-1-cohuck@redhat.com > Drat. I did search the mailing list for a posting from someone else first, but I made the mistake of searching subjects for 'machine type' rather than 'compat machines'. Certainly we should use Cornelia's. Mine is just noise. Thank you reviewers, and sorry for the duplicated effort. drew From MAILER-DAEMON Fri Dec 13 02:30:10 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1iffOs-0003eW-F2 for mharc-qemu-arm@gnu.org; Fri, 13 Dec 2019 02:30:10 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:36855) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iffOo-0003aB-Ul for qemu-arm@nongnu.org; Fri, 13 Dec 2019 02:30:08 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1iffOn-00057z-D1 for qemu-arm@nongnu.org; Fri, 13 Dec 2019 02:30:06 -0500 Received: from 19.mo1.mail-out.ovh.net ([178.32.97.206]:43261) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1iffOn-0004sA-5k for qemu-arm@nongnu.org; Fri, 13 Dec 2019 02:30:05 -0500 Received: from player726.ha.ovh.net (unknown [10.108.16.88]) by mo1.mail-out.ovh.net (Postfix) with ESMTP id E80081A4809 for ; Fri, 13 Dec 2019 08:29:51 +0100 (CET) Received: from kaod.org (lfbn-tou-1-1227-223.w90-76.abo.wanadoo.fr [90.76.50.223]) (Authenticated sender: clg@kaod.org) by player726.ha.ovh.net (Postfix) with ESMTPSA id 4D5CBD2C0463; Fri, 13 Dec 2019 07:29:44 +0000 (UTC) Subject: Re: [PATCH v2 1/2] hw/sd: Configure number of slots exposed by the ASPEED SDHCI model To: Andrew Jeffery , qemu-arm@nongnu.org Cc: peter.maydell@linaro.org, joel@jms.id.au, qemu-devel@nongnu.org, =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= References: <6281ebb475f652838d10dc48ec70fa5113b1f029.1576211124.git-series.andrew@aj.id.au> From: =?UTF-8?Q?C=c3=a9dric_Le_Goater?= Message-ID: <863368db-1056-81eb-d52f-d033002b4650@kaod.org> Date: Fri, 13 Dec 2019 08:29:43 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.1.1 MIME-Version: 1.0 In-Reply-To: <6281ebb475f652838d10dc48ec70fa5113b1f029.1576211124.git-series.andrew@aj.id.au> Content-Type: text/plain; charset=utf-8 Content-Language: en-US X-Ovh-Tracer-Id: 4462785757740501795 X-VR-SPAMSTATE: OK X-VR-SPAMSCORE: -100 X-VR-SPAMCAUSE: gggruggvucftvghtrhhoucdtuddrgedufedrudelkedguddtjecutefuodetggdotefrodftvfcurfhrohhfihhlvgemucfqggfjpdevjffgvefmvefgnecuuegrihhlohhuthemucehtddtnecusecvtfgvtghiphhivghnthhsucdlqddutddtmdenucfjughrpefuvfhfhffkffgfgggjtgfgsehtkeertddtfeejnecuhfhrohhmpeevrogurhhitggpnfgvpgfiohgrthgvrhcuoegtlhhgsehkrghougdrohhrgheqnecukfhppedtrddtrddtrddtpdeltddrjeeirdehtddrvddvfeenucfrrghrrghmpehmohguvgepshhmthhpqdhouhhtpdhhvghlohepphhlrgihvghrjedviedrhhgrrdhovhhhrdhnvghtpdhinhgvtheptddrtddrtddrtddpmhgrihhlfhhrohhmpegtlhhgsehkrghougdrohhrghdprhgtphhtthhopehqvghmuhdqrghrmhesnhhonhhgnhhurdhorhhgnecuvehluhhsthgvrhfuihiivgeptd Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 178.32.97.206 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 13 Dec 2019 07:30:08 -0000 On 13/12/2019 05:28, Andrew Jeffery wrote: > The AST2600 includes a second cut-down version of the SD/MMC controller > found in the AST2500, named the eMMC controller. It's cut down in the > sense that it only supports one slot rather than two, but it brings the > total number of slots supported by the AST2600 to three. >=20 > The existing code assumed that the SD controller always provided two > slots. Rework the SDHCI object to expose the number of slots as a > property to be set by the SoC configuration. >=20 > Signed-off-by: Andrew Jeffery > Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: C=C3=A9dric Le Goater > --- > hw/arm/aspeed.c | 2 +- > hw/arm/aspeed_ast2600.c | 2 ++ > hw/arm/aspeed_soc.c | 2 ++ > hw/sd/aspeed_sdhci.c | 11 +++++++++-- > include/hw/sd/aspeed_sdhci.h | 1 + > 5 files changed, 15 insertions(+), 3 deletions(-) >=20 > diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c > index 028191ff36fc..862549b1f3a9 100644 > --- a/hw/arm/aspeed.c > +++ b/hw/arm/aspeed.c > @@ -259,7 +259,7 @@ static void aspeed_board_init(MachineState *machine= , > cfg->i2c_init(bmc); > } > =20 > - for (i =3D 0; i < ARRAY_SIZE(bmc->soc.sdhci.slots); i++) { > + for (i =3D 0; i < bmc->soc.sdhci.num_slots; i++) { > SDHCIState *sdhci =3D &bmc->soc.sdhci.slots[i]; > DriveInfo *dinfo =3D drive_get_next(IF_SD); > BlockBackend *blk; > diff --git a/hw/arm/aspeed_ast2600.c b/hw/arm/aspeed_ast2600.c > index 931887ac681f..931ee5aae183 100644 > --- a/hw/arm/aspeed_ast2600.c > +++ b/hw/arm/aspeed_ast2600.c > @@ -208,6 +208,8 @@ static void aspeed_soc_ast2600_init(Object *obj) > sysbus_init_child_obj(obj, "sdc", OBJECT(&s->sdhci), sizeof(s->sdh= ci), > TYPE_ASPEED_SDHCI); > =20 > + object_property_set_int(OBJECT(&s->sdhci), 2, "num-slots", &error_= abort); > + > /* Init sd card slot class here so that they're under the correct = parent */ > for (i =3D 0; i < ASPEED_SDHCI_NUM_SLOTS; ++i) { > sysbus_init_child_obj(obj, "sdhci[*]", OBJECT(&s->sdhci.slots[= i]), > diff --git a/hw/arm/aspeed_soc.c b/hw/arm/aspeed_soc.c > index f4fe243458fd..c39a42f914d4 100644 > --- a/hw/arm/aspeed_soc.c > +++ b/hw/arm/aspeed_soc.c > @@ -215,6 +215,8 @@ static void aspeed_soc_init(Object *obj) > sysbus_init_child_obj(obj, "sdc", OBJECT(&s->sdhci), sizeof(s->sdh= ci), > TYPE_ASPEED_SDHCI); > =20 > + object_property_set_int(OBJECT(&s->sdhci), 2, "num-slots", &error_= abort); > + > /* Init sd card slot class here so that they're under the correct = parent */ > for (i =3D 0; i < ASPEED_SDHCI_NUM_SLOTS; ++i) { > sysbus_init_child_obj(obj, "sdhci[*]", OBJECT(&s->sdhci.slots[= i]), > diff --git a/hw/sd/aspeed_sdhci.c b/hw/sd/aspeed_sdhci.c > index cff3eb7dd21e..939d1510dedb 100644 > --- a/hw/sd/aspeed_sdhci.c > +++ b/hw/sd/aspeed_sdhci.c > @@ -13,6 +13,7 @@ > #include "qapi/error.h" > #include "hw/irq.h" > #include "migration/vmstate.h" > +#include "hw/qdev-properties.h" > =20 > #define ASPEED_SDHCI_INFO 0x00 > #define ASPEED_SDHCI_INFO_RESET 0x00030000 > @@ -120,14 +121,14 @@ static void aspeed_sdhci_realize(DeviceState *dev= , Error **errp) > =20 > /* Create input irqs for the slots */ > qdev_init_gpio_in_named_with_opaque(DEVICE(sbd), aspeed_sdhci_set_= irq, > - sdhci, NULL, ASPEED_SDHCI_NUM_= SLOTS); > + sdhci, NULL, sdhci->num_slots)= ; > =20 > sysbus_init_irq(sbd, &sdhci->irq); > memory_region_init_io(&sdhci->iomem, OBJECT(sdhci), &aspeed_sdhci_= ops, > sdhci, TYPE_ASPEED_SDHCI, 0x1000); > sysbus_init_mmio(sbd, &sdhci->iomem); > =20 > - for (int i =3D 0; i < ASPEED_SDHCI_NUM_SLOTS; ++i) { > + for (int i =3D 0; i < sdhci->num_slots; ++i) { > Object *sdhci_slot =3D OBJECT(&sdhci->slots[i]); > SysBusDevice *sbd_slot =3D SYS_BUS_DEVICE(&sdhci->slots[i]); > =20 > @@ -174,6 +175,11 @@ static const VMStateDescription vmstate_aspeed_sdh= ci =3D { > }, > }; > =20 > +static Property aspeed_sdhci_properties[] =3D { > + DEFINE_PROP_UINT8("num-slots", AspeedSDHCIState, num_slots, 0), > + DEFINE_PROP_END_OF_LIST(), > +}; > + > static void aspeed_sdhci_class_init(ObjectClass *classp, void *data) > { > DeviceClass *dc =3D DEVICE_CLASS(classp); > @@ -181,6 +187,7 @@ static void aspeed_sdhci_class_init(ObjectClass *cl= assp, void *data) > dc->realize =3D aspeed_sdhci_realize; > dc->reset =3D aspeed_sdhci_reset; > dc->vmsd =3D &vmstate_aspeed_sdhci; > + dc->props =3D aspeed_sdhci_properties; > } > =20 > static TypeInfo aspeed_sdhci_info =3D { > diff --git a/include/hw/sd/aspeed_sdhci.h b/include/hw/sd/aspeed_sdhci.= h > index dfdab4379021..dffbb46946b9 100644 > --- a/include/hw/sd/aspeed_sdhci.h > +++ b/include/hw/sd/aspeed_sdhci.h > @@ -24,6 +24,7 @@ typedef struct AspeedSDHCIState { > SysBusDevice parent; > =20 > SDHCIState slots[ASPEED_SDHCI_NUM_SLOTS]; > + uint8_t num_slots; > =20 > MemoryRegion iomem; > qemu_irq irq; >=20 From MAILER-DAEMON Fri Dec 13 02:30:23 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1iffP4-0003ss-Sl for mharc-qemu-arm@gnu.org; Fri, 13 Dec 2019 02:30:22 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:38664) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iffP0-0003pJ-V5 for qemu-arm@nongnu.org; Fri, 13 Dec 2019 02:30:20 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1iffOz-0005UW-EQ for qemu-arm@nongnu.org; Fri, 13 Dec 2019 02:30:18 -0500 Received: from 1.mo7.mail-out.ovh.net ([178.33.45.51]:44976) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1iffOz-0005S6-7l for qemu-arm@nongnu.org; Fri, 13 Dec 2019 02:30:17 -0500 Received: from player760.ha.ovh.net (unknown [10.108.1.20]) by mo7.mail-out.ovh.net (Postfix) with ESMTP id 5D065146F2A for ; Fri, 13 Dec 2019 08:30:15 +0100 (CET) Received: from kaod.org (lfbn-tou-1-1227-223.w90-76.abo.wanadoo.fr [90.76.50.223]) (Authenticated sender: clg@kaod.org) by player760.ha.ovh.net (Postfix) with ESMTPSA id 60571D41D73B; Fri, 13 Dec 2019 07:30:10 +0000 (UTC) Subject: Re: [PATCH v2 2/2] hw/arm: ast2600: Wire up the eMMC controller To: Andrew Jeffery , qemu-arm@nongnu.org Cc: peter.maydell@linaro.org, joel@jms.id.au, qemu-devel@nongnu.org References: <23bbbd829459a9a2508c9e76f0720e428852d92d.1576211124.git-series.andrew@aj.id.au> From: =?UTF-8?Q?C=c3=a9dric_Le_Goater?= Message-ID: <94b599da-2211-e77e-267a-5826203c522e@kaod.org> Date: Fri, 13 Dec 2019 08:30:07 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.1.1 MIME-Version: 1.0 In-Reply-To: <23bbbd829459a9a2508c9e76f0720e428852d92d.1576211124.git-series.andrew@aj.id.au> Content-Type: text/plain; charset=utf-8 Content-Language: en-US X-Ovh-Tracer-Id: 4469259683614264128 X-VR-SPAMSTATE: OK X-VR-SPAMSCORE: -100 X-VR-SPAMCAUSE: gggruggvucftvghtrhhoucdtuddrgedufedrudelkedguddtlecutefuodetggdotefrodftvfcurfhrohhfihhlvgemucfqggfjpdevjffgvefmvefgnecuuegrihhlohhuthemucehtddtnecusecvtfgvtghiphhivghnthhsucdlqddutddtmdenucfjughrpefuvfhfhffkffgfgggjtgfgsehtkeertddtfeejnecuhfhrohhmpeevrogurhhitggpnfgvpgfiohgrthgvrhcuoegtlhhgsehkrghougdrohhrgheqnecukfhppedtrddtrddtrddtpdeltddrjeeirdehtddrvddvfeenucfrrghrrghmpehmohguvgepshhmthhpqdhouhhtpdhhvghlohepphhlrgihvghrjeeitddrhhgrrdhovhhhrdhnvghtpdhinhgvtheptddrtddrtddrtddpmhgrihhlfhhrohhmpegtlhhgsehkrghougdrohhrghdprhgtphhtthhopehqvghmuhdqrghrmhesnhhonhhgnhhurdhorhhgnecuvehluhhsthgvrhfuihiivgeptd Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 178.33.45.51 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 13 Dec 2019 07:30:20 -0000 On 13/12/2019 05:28, Andrew Jeffery wrote: > Initialise another SDHCI model instance for the AST2600's eMMC > controller and use the SDHCI's num_slots value introduced previously to > determine whether we should create an SD card instance for the new slot= . >=20 > Signed-off-by: Andrew Jeffery Reviewed-by: C=C3=A9dric Le Goater > --- >=20 > v2: > * Extract instantiation of SD cards to helper function >=20 > hw/arm/aspeed.c | 25 ++++++++++++++++--------- > hw/arm/aspeed_ast2600.c | 21 +++++++++++++++++++++ > include/hw/arm/aspeed_soc.h | 2 ++ > 3 files changed, 39 insertions(+), 9 deletions(-) >=20 > diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c > index 862549b1f3a9..87baac0ea46c 100644 > --- a/hw/arm/aspeed.c > +++ b/hw/arm/aspeed.c > @@ -167,6 +167,18 @@ static void aspeed_board_init_flashes(AspeedSMCSta= te *s, const char *flashtype, > } > } > =20 > +static void sdhci_attach_drive(SDHCIState *sdhci, DriveInfo *dinfo) > +{ > + BlockBackend *blk; > + DeviceState *card; > + > + blk =3D dinfo ? blk_by_legacy_dinfo(dinfo) : NULL; > + card =3D qdev_create(qdev_get_child_bus(DEVICE(sdhci), "sd-bus= "), > + TYPE_SD_CARD); > + qdev_prop_set_drive(card, "drive", blk, &error_fatal); > + object_property_set_bool(OBJECT(card), true, "realized", &erro= r_fatal); > +} > + > static void aspeed_board_init(MachineState *machine, > const AspeedBoardConfig *cfg) > { > @@ -260,16 +272,11 @@ static void aspeed_board_init(MachineState *machi= ne, > } > =20 > for (i =3D 0; i < bmc->soc.sdhci.num_slots; i++) { > - SDHCIState *sdhci =3D &bmc->soc.sdhci.slots[i]; > - DriveInfo *dinfo =3D drive_get_next(IF_SD); > - BlockBackend *blk; > - DeviceState *card; > + sdhci_attach_drive(&bmc->soc.sdhci.slots[i], drive_get_next(IF= _SD)); > + } > =20 > - blk =3D dinfo ? blk_by_legacy_dinfo(dinfo) : NULL; > - card =3D qdev_create(qdev_get_child_bus(DEVICE(sdhci), "sd-bus= "), > - TYPE_SD_CARD); > - qdev_prop_set_drive(card, "drive", blk, &error_fatal); > - object_property_set_bool(OBJECT(card), true, "realized", &erro= r_fatal); > + if (bmc->soc.emmc.num_slots) { > + sdhci_attach_drive(&bmc->soc.emmc.slots[0], drive_get_next(IF_= SD)); > } > =20 > arm_load_kernel(ARM_CPU(first_cpu), machine, &aspeed_board_binfo); > diff --git a/hw/arm/aspeed_ast2600.c b/hw/arm/aspeed_ast2600.c > index 931ee5aae183..723c8196c8a5 100644 > --- a/hw/arm/aspeed_ast2600.c > +++ b/hw/arm/aspeed_ast2600.c > @@ -46,6 +46,7 @@ static const hwaddr aspeed_soc_ast2600_memmap[] =3D { > [ASPEED_ADC] =3D 0x1E6E9000, > [ASPEED_VIDEO] =3D 0x1E700000, > [ASPEED_SDHCI] =3D 0x1E740000, > + [ASPEED_EMMC] =3D 0x1E750000, > [ASPEED_GPIO] =3D 0x1E780000, > [ASPEED_GPIO_1_8V] =3D 0x1E780800, > [ASPEED_RTC] =3D 0x1E781000, > @@ -64,6 +65,7 @@ static const hwaddr aspeed_soc_ast2600_memmap[] =3D { > =20 > #define ASPEED_SOC_AST2600_MAX_IRQ 128 > =20 > +/* Shared Peripheral Interrupt values below are offset by -32 from dat= asheet */ > static const int aspeed_soc_ast2600_irqmap[] =3D { > [ASPEED_UART1] =3D 47, > [ASPEED_UART2] =3D 48, > @@ -77,6 +79,7 @@ static const int aspeed_soc_ast2600_irqmap[] =3D { > [ASPEED_ADC] =3D 78, > [ASPEED_XDMA] =3D 6, > [ASPEED_SDHCI] =3D 43, > + [ASPEED_EMMC] =3D 15, > [ASPEED_GPIO] =3D 40, > [ASPEED_GPIO_1_8V] =3D 11, > [ASPEED_RTC] =3D 13, > @@ -215,6 +218,14 @@ static void aspeed_soc_ast2600_init(Object *obj) > sysbus_init_child_obj(obj, "sdhci[*]", OBJECT(&s->sdhci.slots[= i]), > sizeof(s->sdhci.slots[i]), TYPE_SYSBUS_S= DHCI); > } > + > + sysbus_init_child_obj(obj, "emmc", OBJECT(&s->emmc), sizeof(s->emm= c), > + TYPE_ASPEED_SDHCI); > + > + object_property_set_int(OBJECT(&s->emmc), 1, "num-slots", &error_a= bort); > + > + sysbus_init_child_obj(obj, "emmc[*]", OBJECT(&s->emmc.slots[0]), > + sizeof(s->emmc.slots[0]), TYPE_SYSBUS_SDHCI); > } > =20 > /* > @@ -487,6 +498,16 @@ static void aspeed_soc_ast2600_realize(DeviceState= *dev, Error **errp) > sc->memmap[ASPEED_SDHCI]); > sysbus_connect_irq(SYS_BUS_DEVICE(&s->sdhci), 0, > aspeed_soc_get_irq(s, ASPEED_SDHCI)); > + > + /* eMMC */ > + object_property_set_bool(OBJECT(&s->emmc), true, "realized", &err)= ; > + if (err) { > + error_propagate(errp, err); > + return; > + } > + sysbus_mmio_map(SYS_BUS_DEVICE(&s->emmc), 0, sc->memmap[ASPEED_EMM= C]); > + sysbus_connect_irq(SYS_BUS_DEVICE(&s->emmc), 0, > + aspeed_soc_get_irq(s, ASPEED_EMMC)); > } > =20 > static void aspeed_soc_ast2600_class_init(ObjectClass *oc, void *data) > diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h > index 495c08be1b84..911443f4c071 100644 > --- a/include/hw/arm/aspeed_soc.h > +++ b/include/hw/arm/aspeed_soc.h > @@ -56,6 +56,7 @@ typedef struct AspeedSoCState { > AspeedGPIOState gpio; > AspeedGPIOState gpio_1_8v; > AspeedSDHCIState sdhci; > + AspeedSDHCIState emmc; > } AspeedSoCState; > =20 > #define TYPE_ASPEED_SOC "aspeed-soc" > @@ -125,6 +126,7 @@ enum { > ASPEED_MII4, > ASPEED_SDRAM, > ASPEED_XDMA, > + ASPEED_EMMC, > }; > =20 > #endif /* ASPEED_SOC_H */ >=20 From MAILER-DAEMON Fri Dec 13 02:33:57 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1iffSX-0006WQ-Oh for mharc-qemu-arm@gnu.org; Fri, 13 Dec 2019 02:33:57 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:43332) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iffSV-0006TT-9d for qemu-arm@nongnu.org; Fri, 13 Dec 2019 02:33:56 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1iffSU-00030Z-1F for qemu-arm@nongnu.org; Fri, 13 Dec 2019 02:33:55 -0500 Received: from 13.mo5.mail-out.ovh.net ([87.98.182.191]:34593) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1iffST-0002vL-7C for qemu-arm@nongnu.org; Fri, 13 Dec 2019 02:33:53 -0500 Received: from player692.ha.ovh.net (unknown [10.108.42.142]) by mo5.mail-out.ovh.net (Postfix) with ESMTP id E6535262771 for ; Fri, 13 Dec 2019 08:33:50 +0100 (CET) Received: from kaod.org (lfbn-tou-1-1227-223.w90-76.abo.wanadoo.fr [90.76.50.223]) (Authenticated sender: clg@kaod.org) by player692.ha.ovh.net (Postfix) with ESMTPSA id 426B9D1E3521; Fri, 13 Dec 2019 07:33:46 +0000 (UTC) Subject: Re: [PATCH v2 0/2] hw/arm: ast2600: Wire up eMMC controller To: Andrew Jeffery , qemu-arm@nongnu.org Cc: peter.maydell@linaro.org, joel@jms.id.au, qemu-devel@nongnu.org References: From: =?UTF-8?Q?C=c3=a9dric_Le_Goater?= Message-ID: <16c90bb0-a3a9-06ec-e79a-bd98471d9e11@kaod.org> Date: Fri, 13 Dec 2019 08:33:44 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.1.1 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 7bit X-Ovh-Tracer-Id: 4530058279157861184 X-VR-SPAMSTATE: OK X-VR-SPAMSCORE: -100 X-VR-SPAMCAUSE: gggruggvucftvghtrhhoucdtuddrgedufedrudelkedguddtlecutefuodetggdotefrodftvfcurfhrohhfihhlvgemucfqggfjpdevjffgvefmvefgnecuuegrihhlohhuthemucehtddtnecusecvtfgvtghiphhivghnthhsucdlqddutddtmdenucfjughrpefuvfhfhffkffgfgggjtgfgsehtjeertddtfeejnecuhfhrohhmpeevrogurhhitggpnfgvpgfiohgrthgvrhcuoegtlhhgsehkrghougdrohhrgheqnecuffhomhgrihhnpehoiihlrggsshdrohhrghenucfkpheptddrtddrtddrtddpledtrdejiedrhedtrddvvdefnecurfgrrhgrmhepmhhouggvpehsmhhtphdqohhuthdphhgvlhhopehplhgrhigvrheiledvrdhhrgdrohhvhhdrnhgvthdpihhnvghtpedtrddtrddtrddtpdhmrghilhhfrhhomheptghlgheskhgrohgurdhorhhgpdhrtghpthhtohepqhgvmhhuqdgrrhhmsehnohhnghhnuhdrohhrghenucevlhhushhtvghrufhiiigvpedt X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 87.98.182.191 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 13 Dec 2019 07:33:56 -0000 On 13/12/2019 05:28, Andrew Jeffery wrote: > Hello, > > The AST2600 has an additional SDHCI intended for use as an eMMC boot source. > These two patches rework the existing ASPEED SDHCI model to accommodate the > single-slot nature of the eMMC controller and wire it into the AST2600 SoC. > > v2 contains some minor refactorings in response to issues pointed out by > Cedric. I think these patches are based on mainline. I fixed them locally on my aspeed 5.0 branch and I plan to send them along with other aspeed changes in the 5.0 timeframe. Thanks, C. > > v1 can be found here: > > https://patchwork.ozlabs.org/cover/1206845/ > > Please review! > > Andrew > > Andrew Jeffery (2): > hw/sd: Configure number of slots exposed by the ASPEED SDHCI model > hw/arm: ast2600: Wire up the eMMC controller > > hw/arm/aspeed.c | 27 +++++++++++++++++---------- > hw/arm/aspeed_ast2600.c | 23 +++++++++++++++++++++++ > hw/arm/aspeed_soc.c | 2 ++ > hw/sd/aspeed_sdhci.c | 11 +++++++++-- > include/hw/arm/aspeed_soc.h | 2 ++ > include/hw/sd/aspeed_sdhci.h | 1 + > 6 files changed, 54 insertions(+), 12 deletions(-) > > base-commit: 6a4ef4e5d1084ce41fafa7d470a644b0fd3d9317 > From MAILER-DAEMON Fri Dec 13 02:37:39 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1iffW7-0000Xw-6r for mharc-qemu-arm@gnu.org; Fri, 13 Dec 2019 02:37:39 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:53501) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iffW4-0000XL-Lm for qemu-arm@nongnu.org; Fri, 13 Dec 2019 02:37:37 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1iffW3-0001B5-Lv for qemu-arm@nongnu.org; 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Fri, 13 Dec 2019 02:37:33 -0500 (EST) X-Mailer: MessagingEngine.com Webmail Interface User-Agent: Cyrus-JMAP/3.1.7-680-g58d4e90-fmstable-20191213v1 Mime-Version: 1.0 Message-Id: <1d96ac9b-5eb2-43ec-bf21-334ee3fa4420@www.fastmail.com> In-Reply-To: <16c90bb0-a3a9-06ec-e79a-bd98471d9e11@kaod.org> References: <16c90bb0-a3a9-06ec-e79a-bd98471d9e11@kaod.org> Date: Fri, 13 Dec 2019 18:07:11 +1030 From: "Andrew Jeffery" To: =?UTF-8?Q?C=C3=A9dric_Le_Goater?= , qemu-arm@nongnu.org Cc: "Peter Maydell" , "Joel Stanley" , qemu-devel@nongnu.org Subject: Re: [PATCH v2 0/2] hw/arm: ast2600: Wire up eMMC controller Content-Type: text/plain;charset=utf-8 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 66.111.4.27 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 13 Dec 2019 07:37:37 -0000 On Fri, 13 Dec 2019, at 18:03, C=C3=A9dric Le Goater wrote: > On 13/12/2019 05:28, Andrew Jeffery wrote: > > Hello, > >=20 > > The AST2600 has an additional SDHCI intended for use as an eMMC boot= source. > > These two patches rework the existing ASPEED SDHCI model to accommod= ate the > > single-slot nature of the eMMC controller and wire it into the AST26= 00 SoC. > >=20 > > v2 contains some minor refactorings in response to issues pointed ou= t by > > Cedric. > =20 >=20 > I think these patches are based on mainline. I fixed them locally on=20= > my aspeed 5.0 branch and I plan to send them along with other aspeed=20= > changes in the 5.0 timeframe. =20 Yeah, they're based on Peter's tree. I'll base future patches on yours. Andrew From MAILER-DAEMON Fri Dec 13 04:12:34 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1ifgzy-0004Ru-RU for mharc-qemu-arm@gnu.org; Fri, 13 Dec 2019 04:12:34 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:53336) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ifgzv-0004P8-Rf for qemu-arm@nongnu.org; Fri, 13 Dec 2019 04:12:33 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ifgzt-0000su-38 for qemu-arm@nongnu.org; Fri, 13 Dec 2019 04:12:30 -0500 Received: from us-smtp-2.mimecast.com ([205.139.110.61]:49488 helo=us-smtp-delivery-1.mimecast.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1ifgzs-0000pT-LS for qemu-arm@nongnu.org; Fri, 13 Dec 2019 04:12:29 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1576228347; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=g8Vid2Cs8r6/Rmya9pqc2DE1uJoY/si0o8UbX/u+0vQ=; b=CMWSYjzynILl/YyszkPaEDN+fGwegAl3cNM+1KWDhDtgJ5qeDO2ti2p6tYqNRy2dPzU9Hr JncdY6sTpzdHbUfP3NyEKuEH5F+ejNf0a31Ne8G526zvuOiougcBilexyHDEZeNkQ4mYOH /tNditLNizZpDgElIoRevdj1Iwkm2OE= Received: from mimecast-mx01.redhat.com (mimecast-mx01.redhat.com [209.132.183.4]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-216-a5GX5yCGPyOkF52cnlAqFw-1; Fri, 13 Dec 2019 04:12:24 -0500 Received: from smtp.corp.redhat.com (int-mx01.intmail.prod.int.phx2.redhat.com [10.5.11.11]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx01.redhat.com (Postfix) with ESMTPS id A5C351010FC4; Fri, 13 Dec 2019 09:12:22 +0000 (UTC) Received: from localhost (unknown [10.43.2.114]) by smtp.corp.redhat.com (Postfix) with ESMTP id C6546601A2; Fri, 13 Dec 2019 09:12:20 +0000 (UTC) Date: Fri, 13 Dec 2019 10:12:19 +0100 From: Igor Mammedov To: Tao Xu Cc: "qemu-devel@nongnu.org" , Eduardo Habkost , Marcel Apfelbaum , Radoslaw Biernacki , Peter Maydell , Leif Lindholm , "qemu-arm@nongnu.org" , "qemu-stable@nongnu.org" Subject: Re: [PATCH 2/2] numa: properly check if numa is supported Message-ID: <20191213101219.0aa249dc@redhat.com> In-Reply-To: References: <1576154936-178362-1-git-send-email-imammedo@redhat.com> <1576154936-178362-3-git-send-email-imammedo@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.79 on 10.5.11.11 X-MC-Unique: a5GX5yCGPyOkF52cnlAqFw-1 X-Mimecast-Spam-Score: 0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 205.139.110.61 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 13 Dec 2019 09:12:33 -0000 On Fri, 13 Dec 2019 09:33:10 +0800 Tao Xu wrote: > On 12/12/2019 8:48 PM, Igor Mammedov wrote: > > Commit aa57020774b, by mistake used MachineClass::numa_mem_supported > > to check if NUMA is supported by machine and also as unrelated change > > set it to true for sbsa-ref board. > > > > Luckily change didn't break machines that support NUMA, as the field > > is set to true for them. > > > > But the field is not intended for checking if NUMA is supported and > > will be flipped to false within this release for new machine types. > > > > Fix it: > > - by using previously used condition > > !mc->cpu_index_to_instance_props || !mc->get_default_cpu_node_id > > the first time and then use MachineState::numa_state down the road > > to check if NUMA is supported > > - dropping stray sbsa-ref chunk > > > > Fixes: aa57020774b690a22be72453b8e91c9b5a68c516 > > Signed-off-by: Igor Mammedov > > --- > > CC: Radoslaw Biernacki > > CC: Peter Maydell > > CC: Leif Lindholm > > CC: qemu-arm@nongnu.org > > CC: qemu-stable@nongnu.org > > > > > > hw/arm/sbsa-ref.c | 1 - > > hw/core/machine.c | 4 ++-- > > 2 files changed, 2 insertions(+), 3 deletions(-) > > > > diff --git a/hw/arm/sbsa-ref.c b/hw/arm/sbsa-ref.c > > index 27046cc..c6261d4 100644 > > --- a/hw/arm/sbsa-ref.c > > +++ b/hw/arm/sbsa-ref.c > > @@ -791,7 +791,6 @@ static void sbsa_ref_class_init(ObjectClass *oc, void *data) > > mc->possible_cpu_arch_ids = sbsa_ref_possible_cpu_arch_ids; > > mc->cpu_index_to_instance_props = sbsa_ref_cpu_index_to_props; > > mc->get_default_cpu_node_id = sbsa_ref_get_default_cpu_node_id; > > - mc->numa_mem_supported = true; > > } > > > > static const TypeInfo sbsa_ref_info = { > > diff --git a/hw/core/machine.c b/hw/core/machine.c > > index 1689ad3..aa63231 100644 > > --- a/hw/core/machine.c > > +++ b/hw/core/machine.c > > @@ -958,7 +958,7 @@ static void machine_initfn(Object *obj) > > NULL); > > } > > > > - if (mc->numa_mem_supported) { > > + if (mc->cpu_index_to_instance_props && mc->get_default_cpu_node_id) { > > ms->numa_state = g_new0(NumaState, 1); > > } > > I am wondering if @numa_mem_supported is unused here, it is unused for > QEMU, because the only usage of @numa_mem_supported is to initialize > @numa_state. Or there is other usage? So should it be removed from > struct MachineClass? You are wrong, it's not intended for numa_state initialization, read doc comment for it in include/hw/boards.h (for full story look at commit cd5ff8333a3) From MAILER-DAEMON Fri Dec 13 05:03:24 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1ifhn9-000695-8m for mharc-qemu-arm@gnu.org; Fri, 13 Dec 2019 05:03:23 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:43227) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ifhn5-00068S-8p for qemu-arm@nongnu.org; Fri, 13 Dec 2019 05:03:20 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ifhn2-0003wG-2y for qemu-arm@nongnu.org; Fri, 13 Dec 2019 05:03:17 -0500 Received: from us-smtp-delivery-1.mimecast.com ([207.211.31.120]:37914 helo=us-smtp-1.mimecast.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1ifhn1-0003uI-NC for qemu-arm@nongnu.org; Fri, 13 Dec 2019 05:03:16 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1576231394; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=azycGipua+/jyOaHF/EYGm8hN/wv19QybKjhz4VJCro=; b=QoRRu6bbjD2DQ9d1HuuLsvFSVonaKpP5nedc7KdadF2t/RYungd0WEgnhY03VmGfe5Vik8 kcNqkY/YdsY1WGshymw0ZA//x+s7KqMRcPsjZAq2SyibnTWkyJolAyWJ6lmPX4hKx7Qa0e uXl3FhKRHStvQCigJbR7ovhZnEOr1uM= Received: from mimecast-mx01.redhat.com (mimecast-mx01.redhat.com [209.132.183.4]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-153-AUUT5R3MNaenh2LbWNgr2w-1; Fri, 13 Dec 2019 05:03:13 -0500 Received: from smtp.corp.redhat.com (int-mx06.intmail.prod.int.phx2.redhat.com [10.5.11.16]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx01.redhat.com (Postfix) with ESMTPS id A1126800D4E; Fri, 13 Dec 2019 10:03:11 +0000 (UTC) Received: from blackfin.pond.sub.org (ovpn-116-181.ams2.redhat.com [10.36.116.181]) by smtp.corp.redhat.com (Postfix) with ESMTPS id 7CE185C1D4; Fri, 13 Dec 2019 10:03:04 +0000 (UTC) Received: by blackfin.pond.sub.org (Postfix, from userid 1000) id D6F5F11386A7; Fri, 13 Dec 2019 11:03:02 +0100 (CET) From: Markus Armbruster To: Auger Eric Cc: yang.zhong@intel.com, peter.maydell@linaro.org, kevin.tian@intel.com, tnowicki@marvell.com, mst@redhat.com, jean-philippe.brucker@arm.com, quintela@redhat.com, qemu-devel@nongnu.org, peterx@redhat.com, dgilbert@redhat.com, bharatb.linux@gmail.com, qemu-arm@nongnu.org, eric.auger.pro@gmail.com Subject: Re: [PATCH for-5.0 v11 12/20] qapi: Introduce DEFINE_PROP_INTERVAL References: <20191122182943.4656-1-eric.auger@redhat.com> <20191122182943.4656-13-eric.auger@redhat.com> <87wob17n6j.fsf@dusky.pond.sub.org> <66ae0999-bdd8-6b54-f550-f036dafc982b@redhat.com> Date: Fri, 13 Dec 2019 11:03:02 +0100 In-Reply-To: <66ae0999-bdd8-6b54-f550-f036dafc982b@redhat.com> (Auger Eric's message of "Thu, 12 Dec 2019 16:13:06 +0100") Message-ID: <87y2vg4k6h.fsf@dusky.pond.sub.org> User-Agent: Gnus/5.13 (Gnus v5.13) Emacs/26.2 (gnu/linux) MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.79 on 10.5.11.16 X-MC-Unique: AUUT5R3MNaenh2LbWNgr2w-1 X-Mimecast-Spam-Score: 0 Content-Type: text/plain Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 207.211.31.120 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 13 Dec 2019 10:03:20 -0000 Auger Eric writes: > Hi Markus, > > On 12/12/19 1:17 PM, Markus Armbruster wrote: >> Eric Auger writes: >>=20 >>> Introduce a new property defining a labelled interval: >>> ,,label. >>> >>> This will be used to encode reserved IOVA regions. The label >>> is left undefined to ease reuse accross use cases. >>=20 >> What does the last sentence mean? > The dilemma was shall I specialize this property such as ReservedRegion > or shall I leave it generic enough to serve somebody else use case. I > first chose the latter but now I think I should rather call it something > like ReservedRegion as in any case it has addresses and an integer label. >>=20 >>> For instance, in virtio-iommu use case, reserved IOVA regions >>> will be passed by the machine code to the virtio-iommu-pci >>> device (an array of those). The label will match the >>> virtio_iommu_probe_resv_mem subtype value: >>> - VIRTIO_IOMMU_RESV_MEM_T_RESERVED (0) >>> - VIRTIO_IOMMU_RESV_MEM_T_MSI (1) >>> >>> This is used to inform the virtio-iommu-pci device it should >>> bypass the MSI region: 0xfee00000, 0xfeefffff, 1. >>=20 >> So the "label" part of ",,label" is a number? > yes it is. >>=20 >> Is a number appropriate for your use case, or would an enum be better? > I think a number is OK. There might be other types of reserved regions > in the future. Also if we want to allow somebody else to reuse that > property in another context, I would rather leave it open? I'd prioritize the user interface over possible reuse (which might never happen). Mind, I'm not telling you using numbers is a bad user interface. In general, enums are nicer, but I don't know enough about this particular case. >>=20 >>> >>> Signed-off-by: Eric Auger --- [...] >>> diff --git a/include/exec/memory.h b/include/exec/memory.h >>> index e499dc215b..e238d1c352 100644 >>> --- a/include/exec/memory.h >>> +++ b/include/exec/memory.h >>> @@ -57,6 +57,12 @@ struct MemoryRegionMmio { >>> CPUWriteMemoryFunc *write[3]; >>> }; >>> =20 >>> +struct Interval { >>> + hwaddr low; >>> + hwaddr high; >>> + unsigned int type; >>> +}; >>=20 >> This isn't an interval. An interval consists of two values, not three. >>=20 >> The third one is called "type" here, and "label" elsewhere. Pick one >> and stick to it. >>=20 >> Then pick a name for the triple. Elsewhere, you call it "labelled >> interval". > I would tend to use ReservedRegion now if nobody objects. Sounds good to me. > Thank you for the review! You're welcome! From MAILER-DAEMON Fri Dec 13 07:52:28 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1ifkQm-0006JF-Bk for mharc-qemu-arm@gnu.org; Fri, 13 Dec 2019 07:52:28 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:58851) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ifkQj-0006J3-6L for qemu-arm@nongnu.org; Fri, 13 Dec 2019 07:52:26 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ifkQh-0000tZ-Id for qemu-arm@nongnu.org; Fri, 13 Dec 2019 07:52:24 -0500 Received: from lhrrgout.huawei.com ([185.176.76.210]:2057 helo=huawei.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1ifkQh-0000hV-4s; Fri, 13 Dec 2019 07:52:23 -0500 Received: from LHREML711-CAH.china.huawei.com (unknown [172.18.7.107]) by Forcepoint Email with ESMTP id 6351F7A21D9689193AD4; Fri, 13 Dec 2019 12:52:16 +0000 (GMT) Received: from lhreml701-chm.china.huawei.com (10.201.108.50) by LHREML711-CAH.china.huawei.com (10.201.108.34) with Microsoft SMTP Server (TLS) id 14.3.408.0; Fri, 13 Dec 2019 12:52:15 +0000 Received: from lhreml710-chm.china.huawei.com (10.201.108.61) by lhreml701-chm.china.huawei.com (10.201.108.50) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5; Fri, 13 Dec 2019 12:52:15 +0000 Received: from lhreml710-chm.china.huawei.com ([169.254.81.184]) by lhreml710-chm.china.huawei.com ([169.254.81.184]) with mapi id 15.01.1713.004; Fri, 13 Dec 2019 12:52:15 +0000 From: Shameerali Kolothum Thodi To: Igor Mammedov CC: "xiaoguangrong.eric@gmail.com" , "peter.maydell@linaro.org" , "drjones@redhat.com" , "shannon.zhaosl@gmail.com" , "qemu-devel@nongnu.org" , Linuxarm , Auger Eric , "qemu-arm@nongnu.org" , "xuwei (O)" , "lersek@redhat.com" Subject: RE: [PATCH 0/5] ARM virt: Add NVDIMM support Thread-Topic: [PATCH 0/5] ARM virt: Add NVDIMM support Thread-Index: AQHVeswdQv2zL2ZjnU2+5S1CywnCCKdgnucAgAYn2ECANV3CUIAANK6AgAADjLCAARyUgIADW0wAgBGftACAAodbgIADcKzg Date: Fri, 13 Dec 2019 12:52:15 +0000 Message-ID: References: <20191004155302.4632-1-shameerali.kolothum.thodi@huawei.com> <441c818f24084b4191315cf2a6267cef@huawei.com> <20191125164541.3f0a593f@redhat.com> <444efcb441fe42e5aff58b3af3ab14b4@huawei.com> <20191126095655.27227f59@redhat.com> <20191211085727.1ab9564e@redhat.com> In-Reply-To: <20191211085727.1ab9564e@redhat.com> Accept-Language: en-GB, en-US Content-Language: en-US X-MS-Has-Attach: yes X-MS-TNEF-Correlator: x-originating-ip: [10.202.227.237] Content-Type: multipart/mixed; boundary="_003_effeee8f654c4bd985e24dafaf99e5b8huaweicom_" MIME-Version: 1.0 X-CFilter-Loop: Reflected X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 185.176.76.210 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 13 Dec 2019 12:52:26 -0000 --_003_effeee8f654c4bd985e24dafaf99e5b8huaweicom_ Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable Hi Igor, > -----Original Message----- > From: Igor Mammedov [mailto:imammedo@redhat.com] > Sent: 11 December 2019 07:57 > To: Shameerali Kolothum Thodi > Cc: xiaoguangrong.eric@gmail.com; peter.maydell@linaro.org; > drjones@redhat.com; shannon.zhaosl@gmail.com; qemu-devel@nongnu.org; > Linuxarm ; Auger Eric ; > qemu-arm@nongnu.org; xuwei (O) ; > lersek@redhat.com > Subject: Re: [PATCH 0/5] ARM virt: Add NVDIMM support [...] > > I couldn't figure out yet, why this extra 4 bytes are added by aml code= on > ARM64 > > when the nvdimm_dsm_func_read_fit() returns NvdimmFuncReadFITOut > without > > any FIT data. ie, when the FIT buffer len (read_len) is zero. > > > > But the below will fix this issue, > > > > diff --git a/hw/acpi/nvdimm.c b/hw/acpi/nvdimm.c > > index f91eea3802..cddf95f4c1 100644 > > --- a/hw/acpi/nvdimm.c > > +++ b/hw/acpi/nvdimm.c > > @@ -588,7 +588,7 @@ static void > nvdimm_dsm_func_read_fit(NVDIMMState *state, NvdimmDsmIn *in, > > nvdimm_debug("Read FIT: offset %#x FIT size %#x Dirty %s.\n", > > read_fit->offset, fit->len, fit_buf->dirty ? "Yes" : = "No"); > > > > - if (read_fit->offset > fit->len) { > > + if (read_fit->offset >=3D fit->len) { > > func_ret_status =3D NVDIMM_DSM_RET_STATUS_INVALID; > > goto exit; > > } > > > > > > This will return error code to aml in the second iteration when there i= s no > further > > FIT data to report. But, I am not sure why this check was omitted in th= e first > place. > > > > Please let me know if this is acceptable and then probably I can look i= nto a v2 > of this > > series. > Sorry, I don't have capacity to debug this right now, No problem. > but I'd prefer if 'why' question was answered first. Right. > Anyways, if something is unclear in how concrete AML code is build/works, > feel free to ask and I'll try to explain and guide you. Thanks for your help. I did spend some more time debugging this further. I tried to introduce a totally new Buffer field object with different sizes and printing the size after creation. --- SSDT.dsl 2019-12-12 15:28:21.976986949 +0000 +++ SSDT-arm64-dbg.dsl 2019-12-13 12:17:11.026806186 +0000 @@ -18,7 +18,7 @@ * Compiler ID "BXPC" * Compiler Version 0x00000001 (1) */ -DefinitionBlock ("", "SSDT", 1, "BOCHS ", "NVDIMM", 0x00000001) +DefinitionBlock ("", "SSDT", 1, "BOCHS ", "NVDIMM", 0x00000002) { Scope (\_SB) { @@ -48,6 +48,11 @@ RLEN, 32,=20 ODAT, 32736 } + =20 + Field (NRAM, DWordAcc, NoLock, Preserve) + { + NBUF, 32768=20 + } =20 If ((Arg4 =3D=3D Zero)) { @@ -87,6 +92,12 @@ Local3 =3D DerefOf (Local2) FARG =3D Local3 } + =20 + Local2 =3D 0x2=20 + printf("AML:NVDIMM Creating TBUF with bytes %o", Local2) + CreateField (NBUF, Zero, (Local2 << 3), TBUF) + Concatenate (Buffer (Zero){}, TBUF, Local3) + printf("AML:NVDIMM Size of TBUF(Local3) %o", SizeOf(Local3= )) =20 NTFI =3D Local6 Local1 =3D (RLEN - 0x04) And run it by changing Local2 with different values, It looks on ARM64,=20 For cases where, Local2 <8, the created buffer size is always 8 bytes "AML:NVDIMM Creating TBUF with bytes 0000000000000002" "AML:NVDIMM Size of TBUF(Local3) 0000000000000008" ... "AML:NVDIMM Creating TBUF with bytes 0000000000000005" "AML:NVDIMM Size of TBUF(Local3) 0000000000000008" And once Local2 >=3D8, it gets the correct size, "AML:NVDIMM Creating TBUF with bytes 0000000000000009" "AML:NVDIMM Size of TBUF(Local3) 0000000000000009" But on x86, the behavior is like,=20 For cases where, Local2 <4, the created buffer size is always 4 bytes "AML:NVDIMM Creating TBUF with bytes 00000002" "AML:NVDIMM Size of TBUF(Local3) 00000004" .... "AML:NVDIMM Creating TBUF with bytes 00000003" "AML:NVDIMM Size of TBUF(Local3) 00000004" And once Local2 >=3D 4, it is ok "AML:NVDIMM Creating TBUF with bytes 00000005" "AML:NVDIMM Size of TBUF(Local3) 00000005" ... "AML:NVDIMM Creating TBUF with bytes 00000009" "AML:NVDIMM Size of TBUF(Local3) 00000009" This is the reason why it works on x86 and not on ARM64. Because, if you remember on second iteration of the FIT buffer, the requested buffer size i= s 4 . I tried changing the AccessType of the below NBUF field from DWordAcc to ByteAcc/BufferAcc, but no luck. + Field (NRAM, DWordAcc, NoLock, Preserve) + { + NBUF, 32768=20 + } Not sure what we need to change for ARM64 to create buffer object of size 4 here. Please let me know if you have any pointers to debug this further. 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[83.42.66.34]) by smtp.gmail.com with ESMTPSA id m10sm10695455wrx.19.2019.12.13.09.04.18 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 13 Dec 2019 09:04:18 -0800 (PST) Subject: Re: [PATCH v2 0/2] hw/arm: ast2600: Wire up eMMC controller To: Andrew Jeffery , =?UTF-8?Q?C=c3=a9dric_Le_Goater?= , qemu-arm@nongnu.org Cc: Peter Maydell , Joel Stanley , qemu-devel@nongnu.org References: <16c90bb0-a3a9-06ec-e79a-bd98471d9e11@kaod.org> <1d96ac9b-5eb2-43ec-bf21-334ee3fa4420@www.fastmail.com> From: =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= Message-ID: Date: Fri, 13 Dec 2019 18:04:17 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.2.2 MIME-Version: 1.0 In-Reply-To: <1d96ac9b-5eb2-43ec-bf21-334ee3fa4420@www.fastmail.com> Content-Language: en-US X-MC-Unique: Sn3FKhshOUKtixo8MNtecA-1 X-Mimecast-Spam-Score: 0 Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 207.211.31.120 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 13 Dec 2019 17:04:27 -0000 On 12/13/19 8:37 AM, Andrew Jeffery wrote: > On Fri, 13 Dec 2019, at 18:03, C=C3=A9dric Le Goater wrote: >> On 13/12/2019 05:28, Andrew Jeffery wrote: >>> Hello, >>> >>> The AST2600 has an additional SDHCI intended for use as an eMMC boot so= urce. >>> These two patches rework the existing ASPEED SDHCI model to accommodate= the >>> single-slot nature of the eMMC controller and wire it into the AST2600 = SoC. >>> >>> v2 contains some minor refactorings in response to issues pointed out b= y >>> Cedric. >> =20 >> >> I think these patches are based on mainline. I fixed them locally on >> my aspeed 5.0 branch and I plan to send them along with other aspeed >> changes in the 5.0 timeframe. >=20 > Yeah, they're based on Peter's tree. I'll base future patches on yours. To help any reviewer, simply add a note in the cover on which tree your=20 series is based. This also works with individual patch, add the note=20 under the '---' separator. From MAILER-DAEMON Fri Dec 13 13:59:46 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1ifqAB-0000rE-Eq for mharc-qemu-arm@gnu.org; Fri, 13 Dec 2019 13:59:46 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:39548) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ifqA8-0000oS-Ox for qemu-arm@nongnu.org; Fri, 13 Dec 2019 13:59:41 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ifqA6-0006Fx-RA for qemu-arm@nongnu.org; Fri, 13 Dec 2019 13:59:39 -0500 Received: from us-smtp-2.mimecast.com ([207.211.31.81]:47256 helo=us-smtp-delivery-1.mimecast.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1ifqA6-0006CQ-B0 for qemu-arm@nongnu.org; Fri, 13 Dec 2019 13:59:38 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1576263577; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: in-reply-to:in-reply-to:references:references; bh=BTVCt4lo2+JVoxNzS8jAAe82HqlgpftwzzDCvcWKC0o=; b=C0i1ltvFqwe4zeI7v6E/GFBRKbO6Uy4u0Y2gvP4Ib/JW99SpfBOOD35qBfUk8XZjT3+7z5 5YyILYHVT2VUhBzNRJhZRtsXVFN/PWBDgTY2wjwV56CNrfN4UyX5aBLA7EzWW9Qf+abQzP jI3wMJfrNU/fQIif6jKYSk0iZYEmNq0= Received: from mimecast-mx01.redhat.com (mimecast-mx01.redhat.com [209.132.183.4]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-143-nejDi4YpNM-3UQq70rGOwA-1; Fri, 13 Dec 2019 13:59:33 -0500 X-MC-Unique: nejDi4YpNM-3UQq70rGOwA-1 Received: from smtp.corp.redhat.com (int-mx06.intmail.prod.int.phx2.redhat.com [10.5.11.16]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx01.redhat.com (Postfix) with ESMTPS id 2D53785B6FD; Fri, 13 Dec 2019 18:59:31 +0000 (UTC) Received: from kamzik.brq.redhat.com (ovpn-204-115.brq.redhat.com [10.40.204.115]) by smtp.corp.redhat.com (Postfix) with ESMTPS id 63C8466851; Fri, 13 Dec 2019 18:59:18 +0000 (UTC) Date: Fri, 13 Dec 2019 19:59:15 +0100 From: Andrew Jones To: Eric Auger Cc: eric.auger.pro@gmail.com, maz@kernel.org, kvmarm@lists.cs.columbia.edu, kvm@vger.kernel.org, qemu-devel@nongnu.org, qemu-arm@nongnu.org, andrew.murray@arm.com, andre.przywara@arm.com, peter.maydell@linaro.org Subject: Re: [kvm-unit-tests RFC 03/10] pmu: Add a pmu struct Message-ID: <20191213185915.7txbnxybupszis7r@kamzik.brq.redhat.com> References: <20191206172724.947-1-eric.auger@redhat.com> <20191206172724.947-4-eric.auger@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20191206172724.947-4-eric.auger@redhat.com> X-Scanned-By: MIMEDefang 2.79 on 10.5.11.16 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 207.211.31.81 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 13 Dec 2019 18:59:42 -0000 On Fri, Dec 06, 2019 at 06:27:17PM +0100, Eric Auger wrote: > This struct aims at storing information potentially used by > all tests such as the pmu version, the read-only part of the > PMCR, the number of implemented event counters, ... > > Signed-off-by: Eric Auger > --- > arm/pmu.c | 29 ++++++++++++++++++++++++----- > 1 file changed, 24 insertions(+), 5 deletions(-) > > diff --git a/arm/pmu.c b/arm/pmu.c > index 2ad6469..8e95251 100644 > --- a/arm/pmu.c > +++ b/arm/pmu.c > @@ -33,7 +33,15 @@ > > #define NR_SAMPLES 10 > > -static unsigned int pmu_version; > +struct pmu { > + unsigned int version; > + unsigned int nb_implemented_counters; > + uint32_t pmcr_ro; > +}; > + > +static struct pmu pmu; > + > + > #if defined(__arm__) > #define ID_DFR0_PERFMON_SHIFT 24 > #define ID_DFR0_PERFMON_MASK 0xf > @@ -265,7 +273,7 @@ static bool check_cpi(int cpi) > static void pmccntr64_test(void) > { > #ifdef __arm__ > - if (pmu_version == 0x3) { > + if (pmu.version == 0x3) { > if (ERRATA(9e3f7a296940)) { > write_sysreg(0xdead, PMCCNTR64); > report("pmccntr64", read_sysreg(PMCCNTR64) == 0xdead); > @@ -278,9 +286,20 @@ static void pmccntr64_test(void) > /* Return FALSE if no PMU found, otherwise return TRUE */ > static bool pmu_probe(void) > { > - pmu_version = get_pmu_version(); > - report_info("PMU version: %d", pmu_version); > - return pmu_version != 0 && pmu_version != 0xf; > + uint32_t pmcr; > + > + pmu.version = get_pmu_version(); > + report_info("PMU version: %d", pmu.version); > + > + if (pmu.version == 0 || pmu.version == 0xF) ^ stray space > + return false; > + > + pmcr = get_pmcr(); > + pmu.pmcr_ro = pmcr & 0xFFFFFF80; > + pmu.nb_implemented_counters = (pmcr >> PMU_PMCR_N_SHIFT) & PMU_PMCR_N_MASK; > + report_info("Implements %d event counters", pmu.nb_implemented_counters); > + > + return true; > } > > int main(int argc, char *argv[]) > -- > 2.20.1 > From MAILER-DAEMON Fri Dec 13 14:11:24 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1ifqLT-00051p-Tr for mharc-qemu-arm@gnu.org; Fri, 13 Dec 2019 14:11:23 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:41615) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ifqLP-00051O-0J for qemu-arm@nongnu.org; Fri, 13 Dec 2019 14:11:22 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ifqLL-0006OF-Qa for qemu-arm@nongnu.org; Fri, 13 Dec 2019 14:11:17 -0500 Received: from us-smtp-2.mimecast.com ([207.211.31.81]:47361 helo=us-smtp-delivery-1.mimecast.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1ifqLL-0006LR-Eb for qemu-arm@nongnu.org; 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Fri, 13 Dec 2019 19:11:08 +0000 (UTC) Received: from kamzik.brq.redhat.com (ovpn-204-115.brq.redhat.com [10.40.204.115]) by smtp.corp.redhat.com (Postfix) with ESMTPS id 5C8725D9C9; Fri, 13 Dec 2019 19:10:48 +0000 (UTC) Date: Fri, 13 Dec 2019 20:10:43 +0100 From: Andrew Jones To: Eric Auger Cc: eric.auger.pro@gmail.com, maz@kernel.org, kvmarm@lists.cs.columbia.edu, kvm@vger.kernel.org, qemu-devel@nongnu.org, qemu-arm@nongnu.org, andrew.murray@arm.com, andre.przywara@arm.com, peter.maydell@linaro.org Subject: Re: [kvm-unit-tests RFC 04/10] pmu: Check Required Event Support Message-ID: <20191213191043.azvoxkcsahhycmhl@kamzik.brq.redhat.com> References: <20191206172724.947-1-eric.auger@redhat.com> <20191206172724.947-5-eric.auger@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20191206172724.947-5-eric.auger@redhat.com> X-Scanned-By: MIMEDefang 2.79 on 10.5.11.14 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 207.211.31.81 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 13 Dec 2019 19:11:22 -0000 On Fri, Dec 06, 2019 at 06:27:18PM +0100, Eric Auger wrote: > If event counters are implemented check the common events > required by the PMUv3 are implemented. > > Some are unconditionally required (SW_INCR, CPU_CYCLES, > either INST_RETIRED or INST_SPEC). Some others only are > required if the implementation implements some other features. > > Check those wich are unconditionally required. > > This test currently fails on TCG as neither INST_RETIRED > or INST_SPEC are supported. > > Signed-off-by: Eric Auger > --- > arm/pmu.c | 70 +++++++++++++++++++++++++++++++++++++++++++++++ > arm/unittests.cfg | 6 ++++ > 2 files changed, 76 insertions(+) > > diff --git a/arm/pmu.c b/arm/pmu.c > index 8e95251..f78c43f 100644 > --- a/arm/pmu.c > +++ b/arm/pmu.c > @@ -102,6 +102,10 @@ static inline void precise_instrs_loop(int loop, uint32_t pmcr) > : [pmcr] "r" (pmcr), [z] "r" (0) > : "cc"); > } > + > +/* event counter tests only implemented for aarch64 */ > +static void test_event_introspection(void) {} > + > #elif defined(__aarch64__) > #define ID_AA64DFR0_PERFMON_SHIFT 8 > #define ID_AA64DFR0_PERFMON_MASK 0xf > @@ -140,6 +144,69 @@ static inline void precise_instrs_loop(int loop, uint32_t pmcr) > : [pmcr] "r" (pmcr) > : "cc"); > } > + > +#define PMCEID1_EL0 sys_reg(11, 3, 9, 12, 7) > + > +static bool is_event_supported(uint32_t n, bool warn) > +{ > + uint64_t pmceid0 = read_sysreg(pmceid0_el0); > + uint64_t pmceid1 = read_sysreg_s(PMCEID1_EL0); > + bool supported; > + uint32_t reg; > + > + if (n >= 0x0 && n <= 0x1F) { > + reg = pmceid0 & 0xFFFFFFFF; > + } else if (n >= 0x4000 && n <= 0x401F) { > + reg = pmceid0 >> 32; > + } else if (n >= 0x20 && n <= 0x3F) { > + reg = pmceid1 & 0xFFFFFFFF; > + } else if (n >= 0x4020 && n <= 0x403F) { > + reg = pmceid1 >> 32; Lot's of stray spaces in there. Also the 0x4000 should probably get a define, and maybe another for the size 0x20. > + } else { > + abort(); > + } > + supported = reg & (1 << n); > + if (!supported && warn) > + report_info("event %d is not supported", n); > + return supported; > +} > + > +static void test_event_introspection(void) > +{ > + bool required_events; > + > + if (!pmu.nb_implemented_counters) { > + report_skip("No event counter, skip ..."); > + return; > + } > + if (pmu.nb_implemented_counters < 2) > + report_info("%d event counters are implemented. " > + "ARM recommends to implement at least 2", > + pmu.nb_implemented_counters); nit: I'd use {} on these multi-line if's (even if they're just one line) > + > + /* PMUv3 requires an implementation includes some common events */ > + required_events = is_event_supported(0x0, true) /* SW_INCR */ && > + is_event_supported(0x11, true) /* CPU_CYCLES */ && > + (is_event_supported(0x8, true) /* INST_RETIRED */ || > + is_event_supported(0x1B, true) /* INST_PREC */); > + if (!is_event_supported(0x8, false)) > + report_info("ARM strongly recomments INST_RETIRED (0x8) event " ^ recommends > + "to be implemented"); Do we need to report Arm's recommendation? > + > + if (pmu.version == 0x4) { > + /* ARMv8.1 PMU: STALL_FRONTEND and STALL_BACKEND are required */ > + required_events = required_events || > + is_event_supported(0x23, true) || > + is_event_supported(0x24, true); > + } > + > + /* L1D_CACHE_REFILL(0x3) and L1D_CACHE(0x4) are only required if > + L1 data / unified cache. BR_MIS_PRED(0x10), BR_PRED(0x12) are only > + required if program-flow prediction is implemented. */ > + > + report("Check required events are implemented", required_events); > +} > + > #endif > > /* > @@ -324,6 +391,9 @@ int main(int argc, char *argv[]) > report("Monotonically increasing cycle count", check_cycles_increase()); > report("Cycle/instruction ratio", check_cpi(cpi)); > pmccntr64_test(); > + } else if (strcmp(argv[1], "event-introspection") == 0) { > + report_prefix_push(argv[1]); > + test_event_introspection(); > } else { > report_abort("Unknown subtest '%s'", argv[1]); > } > diff --git a/arm/unittests.cfg b/arm/unittests.cfg > index 79f0d7a..4433ef3 100644 > --- a/arm/unittests.cfg > +++ b/arm/unittests.cfg > @@ -66,6 +66,12 @@ file = pmu.flat > groups = pmu > extra_params = -append 'cycle-counter 0' > > +[pmu-event-introspection] > +file = pmu.flat > +groups = pmu > +arch = arm64 > +extra_params = -append 'event-introspection' > + > # Test PMU support (TCG) with -icount IPC=1 > #[pmu-tcg-icount-1] > #file = pmu.flat > -- > 2.20.1 > Thanks, drew From MAILER-DAEMON Fri Dec 13 15:46:19 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1ifrpL-0008Lf-0G for mharc-qemu-arm@gnu.org; Fri, 13 Dec 2019 15:46:19 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:58130) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ifrpF-0008Cu-ER for qemu-arm@nongnu.org; Fri, 13 Dec 2019 15:46:16 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ifrpB-0002QH-TX for qemu-arm@nongnu.org; Fri, 13 Dec 2019 15:46:13 -0500 Received: from mail-io1-xd44.google.com ([2607:f8b0:4864:20::d44]:40756) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ifrp3-00021c-C6; Fri, 13 Dec 2019 15:46:01 -0500 Received: by mail-io1-xd44.google.com with SMTP id x1so988081iop.7; Fri, 13 Dec 2019 12:46:01 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=3wTaebObS2Pqs6jood4W/1S3RjJObJ21+auWyMLqj5U=; b=CW1sM6e44cnlFEG9Gh6emq7kVOpmw3m5B3s61PX0vaGD9HdKo8tb5gJ4qgbu6TWBf2 hDFnlSMGzLBCYiVdkYNtZW1drWQQOFUVkybCIqAlKe8eZOz3vqtzByOUQD9j8pbXdws8 OdX7JbHS8UshK3i8+pDOB4GoJ60c72ebvm+3OOjGqTetFNZPps6noHcLoP99hdmpLXaq GKruhjC2ktIN+w95/oxsGRtLSBg84t6OV3VyHtPLxdRsmyil07ZFpB/oiPVVfKvNSfy/ Gbe+TJOcl8Tzez17xHLr/niuWIVWosG50JUDvkq30YBob+PGTyr6M0If96IocoEBCoUw n8iA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=3wTaebObS2Pqs6jood4W/1S3RjJObJ21+auWyMLqj5U=; b=izfLS+xXvdlPcYdqyyb3i/+GgWuRkeA0DwJCMfmGkjfYZSFuqr/WTVi+juVCuRj3Xq eMzXJlxzGy/g29SliufWumfSX8WM5aBCLymvBbRxQ3qqwIXcuW+IaxOAtgP8At1swAxr k2RufHqdW1uaS9DfzoAc3fZZ3mL3+d5J8AI8qzjSPqM6L1Jv7KHk+3uGlHiKEz/FtnMD wfKDtc+Ms+r9y3bB5xGpr3WgOy3Q3KE4RbeGhDs0yymaw8qG0aiQPz++g+OAyTViB5Ld jtFyN6CkPLpR6EsndFTsJIdDHhvKw0cf6wK6keJ3AHunKNkX6apWRCJzFpcL7eA/CM7g 0nBQ== X-Gm-Message-State: APjAAAXl+nQXmdlMju97PdKGfp9T1DDF/yVfCyELa7U53MFJJw5RcngY kQ9ZHmm/75hA+NcNG5BeIccPsE7TIoTm+zN6o/o= X-Google-Smtp-Source: APXvYqzsNCDTJrJi2yJ9gmmTgAYsS2clX7HbxgZo/r2MVslxXsPqs3/DxxQL1uw4VdgCkL8PYUcr5Xu5FCkqneGZSBw= X-Received: by 2002:a02:8817:: with SMTP id r23mr1315146jai.120.1576269960273; Fri, 13 Dec 2019 12:46:00 -0800 (PST) MIME-Version: 1.0 References: <20191202210947.3603-1-nieklinnenbank@gmail.com> <74df65db-1f84-62ba-6d01-edf765fd1dc2@redhat.com> <7ed70514-e67e-9403-63b3-5a81c59fe952@redhat.com> In-Reply-To: <7ed70514-e67e-9403-63b3-5a81c59fe952@redhat.com> From: Niek Linnenbank Date: Fri, 13 Dec 2019 21:45:48 +0100 Message-ID: Subject: Re: [PATCH 00/10] Add Allwinner H3 SoC and Orange Pi PC Machine To: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= Cc: =?UTF-8?B?QWxleCBCZW5uw6ll?= , QEMU Developers , Beniamino Galvani , Peter Maydell , qemu-arm , Richard Henderson Content-Type: multipart/alternative; boundary="0000000000000d68d305999bf369" X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::d44 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 13 Dec 2019 20:46:17 -0000 --0000000000000d68d305999bf369 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Hi Philippe, On Fri, Dec 13, 2019 at 12:25 AM Philippe Mathieu-Daud=C3=A9 wrote: > Cc'ing Alex. > > On 12/13/19 12:07 AM, Niek Linnenbank wrote: > > Hi Philippe, > > > > I have discovered that the hflags assertion error you reported is not > > caused by the Allwinner H3 > > patches but actually an existing problem. What I did is to use the > > latest master (v4.2.0 tag) without any patches applied. > > and tried to boot the raspi2 machine with and without debugging enabled= . > > Without debuggin, the raspi2 > > machine runs fine and can boot the 5.4.2 linux kernel. With debugging > > enabled, the same hflags error shows. > > This might be the same bug I hit last week... Alex suggested a patch: > https://www.mail-archive.com/qemu-devel@nongnu.org/msg664500.html > > Do you mind to try it? > Ahh OK, I was not aware that this was already seen and solved! Sometimes I try use the lists.gnu.org site to keep an eye out for relevant emails going to qemu-devel, but I totally missed this fix. Too many e-mails. Perhaps instead I should just subscribe to the mailing list and use filters. I retried with the raspi2 machine and alex's patch, and indeed the hflags error is gone and the machine starts fine with debugging enabled. Ofcourse, I also retried with the Allwinner H3 patches + alex's fix applied and the orangepi-pc machine, and unfortunately, there the hflags assertion did still show up. Then I looked further to try and understand what is going on, and it looked to me that the hflags is a state variable, that needs to be rebuild after changing some other fields inside the ARM cpu object. And in my patch #0006 I did just that: I tried to resolve the undefined exceptions I got using arm_set_cpu_on(), by setting CP10,CP11 bits. So I tried to use the arm_rebuild_hflags() function after applying the CP10,CP11 bits, and that solved the assertion issue (see below). Can you verify if this change also resolves the hflags assertion on your side? I'll also reply to the mail for patch #0006 with this info. Regards, Niek diff --git a/target/arm/arm-powerctl.c b/target/arm/arm-powerctl.c index f77a950db6..cf2f3d69ab 100644 --- a/target/arm/arm-powerctl.c +++ b/target/arm/arm-powerctl.c @@ -104,6 +104,9 @@ static void arm_set_cpu_on_async_work(CPUState *target_cpu_state, /* Processor is not in secure mode */ target_cpu->env.cp15.scr_el3 |=3D SCR_NS; + /* Set NSACR.{CP11,CP10} so NS can access the FPU */ + target_cpu->env.cp15.nsacr |=3D 3 << 10; + /* * If QEMU is providing the equivalent of EL3 firmware, then we ne= ed * to make sure a CPU targeting EL2 comes out of reset with a @@ -124,6 +127,9 @@ static void arm_set_cpu_on_async_work(CPUState *target_cpu_state, target_cpu->env.regs[0] =3D info->context_id; } + /* Ensure hflags is rebuild */ + arm_rebuild_hflags(&target_cpu->env); + /* Start the new CPU at the requested address */ cpu_set_pc(target_cpu_state, info->entry); > > If it still fails, you might also add this one on top: > https://www.mail-archive.com/qemu-devel@nongnu.org/msg663843.html > and report the error. > > That patch is indeed very helpful > > > > To reproduce it, build Linux 5.4.2 with the bmc2835_defconfig: > > > > $ ARCH=3Darm CROSS_COMPILE=3Darm-linux-gnueabi- make mrproper > > $ ARCH=3Darm CROSS_COMPILE=3Darm-linux-gnueabi- make bcm2835_defconfig > > $ ARCH=3Darm CROSS_COMPILE=3Darm-linux-gnueabi- make -j5 > > ... > > > > First build QEMU without debugging and try to boot linux: > > $ ./configure --target-list=3Darm-softmmu; make clean; make -j5 > > $ ./arm-softmmu/qemu-system-arm -M raspi2 \ > > -kernel $HOME/linux-5.4.2/arch/arm/boot/zImage \ > > -append 'console=3DttyAMA0,115200 earlyprintk debug' \ > > -dtb $HOME/linux-5.4.2/arch/arm/boot/dts/bcm2836-rpi-2-b.dtb \ > > -m 1024 -nographic -s > > [ 0.000000] Booting Linux on physical CPU 0x0 > > [ 0.000000] Linux version 5.4.2 (me@host) (gcc version 7.4.0 > (Ubuntu/Linaro 7.4.0-1ubuntu1~18.04.1)) #1 Thu Dec 12 22:49:14 CET 2019 > > [ 0.000000] CPU: ARMv7 Processor [410fc075] revision 5 (ARMv7), > cr=3D10c53c7d > > ... > > > > Then rebuild QEMU with debugging enabled and again try to boot linux: > > $ ./configure --target-list=3Darm-softmmu --enable-debug > --extra-cflags=3D-ggdb; make clean; make -j5 > > $ ./arm-softmmu/qemu-system-arm -M raspi2 \ > > -kernel $HOME/linux-5.4.2/arch/arm/boot/zImage \ > > -append 'console=3DttyAMA0,115200 earlyprintk debug' \ > > -dtb $HOME/linux-5.4.2/arch/arm/boot/dts/bcm2836-rpi-2-b.dtb \ > > -m 1024 -nographic -s > > qemu-system-arm: /home/me/qemu/target/arm/helper.c:11359: > cpu_get_tb_cpu_state: Assertion `flags =3D=3D rebuild_hflags_internal(env= )' > failed. > > qemu-system-arm: /home/me/qemu/target/arm/helper.c:11359: > cpu_get_tb_cpu_state: Assertion `flags =3D=3D rebuild_hflags_internal(env= )' > failed. > > qemu-system-arm: /home/me/qemu/target/arm/helper.c:11359: > cpu_get_tb_cpu_state: Assertion `flags =3D=3D rebuild_hflags_internal(env= )' > failed. > > Aborted (core dumped) > > > > $ git describe > > v4.2.0 > > > > > > What should be the next step? Should this be reported as a bug? > > In this case we might already have the fix, but if Alex patch doesn't > help, you are always welcome to open a bug report: > https://bugs.launchpad.net/qemu/+filebug > This help to have notes/progress gathered. > > > On Tue, Dec 10, 2019 at 9:12 PM Niek Linnenbank > > > wrote: > > > > Hi Philippe, > > > > On Tue, Dec 10, 2019 at 9:26 AM Philippe Mathieu-Daud=C3=A9 > > > wrote: > > > > On 12/9/19 10:37 PM, Niek Linnenbank wrote: > > > Hi Philippe, > > > > > > On Tue, Dec 3, 2019 at 9:47 AM Philippe Mathieu-Daud=C3=A9 > > > > > >> wrote= : > > > > > > On 12/2/19 10:09 PM, Niek Linnenbank wrote: > > > > Dear QEMU developers, > > > > > > > > Hereby I would like to contribute the following set o= f > > patches to > > > QEMU > > > > which add support for the Allwinner H3 System on Chip > > and the > > > > Orange Pi PC machine. The following features and > > devices are > > > supported: > > > > > > > > * SMP (Quad Core Cortex A7) > > > > * Generic Interrupt Controller configuration > > > > * SRAM mappings > > > > * Timer device (re-used from Allwinner A10) > > > > * UART > > > > * SD/MMC storage controller > > > > * EMAC ethernet connectivity > > > > * USB 2.0 interfaces > > > > * Clock Control Unit > > > > * System Control module > > > > * Security Identifier device > > > > > > Awesome! > > > > > > > Functionality related to graphical output such as > > HDMI, GPU, > > > > Display Engine and audio are not included. Recently > > released > > > > mainline Linux kernels (4.19 up to latest master) and > > mainline U-Boot > > > > are known to work. The SD/MMC code is tested using > > bonnie++ and > > > > various tools such as fsck, dd and fdisk. The EMAC is > > verified > > > with iperf3 > > > > using -netdev socket. > > > > > > > > To build a Linux mainline kernel that can be booted b= y > > the Orange > > > Pi PC > > > > machine, simply configure the kernel using the > > sunxi_defconfig > > > configuration: > > > > $ ARCH=3Darm CROSS_COMPILE=3Darm-linux-gnueabi- mak= e > > mrproper > > > > $ ARCH=3Darm CROSS_COMPILE=3Darm-linux-gnueabi- mak= e > > sunxi_defconfig > > > > > > > > To be able to use USB storage, you need to manually > > enable the > > > corresponding > > > > configuration item. Start the kconfig configuration > tool: > > > > $ ARCH=3Darm CROSS_COMPILE=3Darm-linux-gnueabi- mak= e > > menuconfig > > > > > > > > Navigate to the following item, enable it and save yo= ur > > > configuration: > > > > Device Drivers > USB support > USB Mass Storage > support > > > > > > > > Build the Linux kernel with: > > > > $ ARCH=3Darm CROSS_COMPILE=3Darm-linux-gnueabi- mak= e -j5 > > > > > > > > To boot the newly build linux kernel in QEMU with the > > Orange Pi > > > PC machine, use: > > > > $ qemu-system-arm -M orangepi -m 512 -nic user > > -nographic \ > > > > -kernel /path/to/linux/arch/arm/boot/zImage \ > > > > -append 'console=3DttyS0,115200' \ > > > > -dtb > > /path/to/linux/arch/arm/boot/dts/sun8i-h3-orangepi-pc.dtb > > > > > > > > Note that this kernel does not have a root filesystem= . > > You may > > > provide it > > > > with an official Orange Pi PC image [1] either as an > > SD card or as > > > > USB mass storage. To boot using the Orange Pi PC > > Debian image on > > > SD card, > > > > simply add the -sd argument and provide the proper > > root=3D kernel > > > parameter: > > > > $ qemu-system-arm -M orangepi -m 512 -nic user > > -nographic \ > > > > -kernel /path/to/linux/arch/arm/boot/zImage \ > > > > -append 'console=3DttyS0,115200 > root=3D/dev/mmcblk0p2' \ > > > > -dtb > > > /path/to/linux/arch/arm/boot/dts/sun8i-h3-orangepi-pc.dt= b > \ > > > > -sd > > OrangePi_pc_debian_stretch_server_linux5.3.5_v1.0.img > > > > > > > > Alternatively, you can also choose to build and boot = a > > recent > > > buildroot [2] > > > > using the orangepi_pc_defconfig or Armbian image [3] > > for Orange > > > Pi PC. > > > > > > Richard, trying the Armbian image from > > > https://apt.armbian.com/pool/main/l/linux-4.20.7-sunxi/ I > get: > > > > > > $ arm-softmmu/qemu-system-arm -M orangepi -m 512 -nic > user \ > > > -append 'console=3DttyS0,115200' \ > > > -kernel boot/vmlinuz-4.20.7-sunxi \ > > > -dtb > > usr/lib/linux-image-dev-sunxi/sun8i-h3-orangepi-pc.dtb \ > > > -serial stdio -d unimp > > > Uncompressing Linux... done, booting the kernel. > > > rtc: unimplemented device write (size 4, value > > 0x16aa0001, offset 0x0) > > > rtc: unimplemented device read (size 4, offset 0x0) > > > rtc: unimplemented device read (size 4, offset 0x0) > > > rtc: unimplemented device read (size 4, offset 0x8) > > > qemu-system-arm: target/arm/helper.c:11359: > > cpu_get_tb_cpu_state: > > > Assertion `flags =3D=3D rebuild_hflags_internal(env)' fa= iled. > > > Aborted (core dumped) > > > > > > > > > I'm trying to reproduce the error you reported here with my > > patch set on > > > latest master, > > > but so far without any result. The host OS I'm using is > > Ubuntu 18.04.3 > > > LTS on x86_64. > > > I ran several times using the same 4.20.7-sunxi kernel and > > same command > > > line. > > > > > > Some questions that might help: > > > 1) Are there any specific steps you did in order to produce > > this error? > > > > I build QEMU with: > > > > ./configure --enable-trace-backends=3Dlog --extra-cflags=3D-ggd= b > > --enable-debug > > > > > 2) Could this be a known / existing issue? > > > 3) How many times did you see this error? > > > > Always > > > > > 4) Are you also using Ubuntu 18.04.3 LTS on x86_64, or a > > different host OS? > > > > Host is Fedora 30. > > > > > > OK thanks, I will try again using the info above after I finished > > reworking the other patch comments. > > > > Niek > > --=20 Niek Linnenbank --0000000000000d68d305999bf369 Content-Type: text/html; charset="UTF-8" Content-Transfer-Encoding: quoted-printable
Hi Philippe,

On Fri, Dec 13, 2019 at 1= 2:25 AM Philippe Mathieu-Daud=C3=A9 <philmd@redhat.com> wrote:
Cc'ing Alex.

On 12/13/19 12:07 AM, Niek Linnenbank wrote:
> Hi Philippe,
>
> I have discovered that the hflags assertion error you reported is not =
> caused by the Allwinner H3
> patches but actually an existing problem. What I did is to use the > latest master (v4.2.0 tag) without any patches applied.
> and tried to boot the raspi2 machine with and without debugging enable= d.
> Without debuggin, the raspi2
> machine runs fine and can boot the 5.4.2 linux kernel. With debugging =
> enabled, the same hflags error shows.

This might be the same bug I hit last week... Alex suggested a patch:
https://www.mail-archive.com/qemu-d= evel@nongnu.org/msg664500.html

Do you mind to try it?

Ahh OK, I was no= t aware that this was already seen and solved!
Sometimes I try us= e the lists.gnu.org site to keep an ey= e out for relevant emails going to qemu-devel,
but I totally miss= ed this fix. Too many e-mails. Perhaps instead I should just subscribe to t= he mailing list and use filters.

I retried wit= h the raspi2 machine and alex's patch, and indeed the hflags error is g= one and
the machine starts fine with debugging enabled.

Ofcourse, I also retried with the Allwinner H3 patches=C2= =A0+ alex's fix applied and the orangepi-pc machine,
and unfo= rtunately, there the hflags assertion did still show up.

Then I looked further to try and understand what is going on, and = it looked to me that the hflags is a
state variable, that needs t= o be rebuild after changing some other fields inside the ARM cpu object.
And in my patch #0006 I did just that: I tried to resolve the = undefined exceptions I got using arm_set_cpu_on(),
by setting CP1= 0,CP11 bits. So I tried to use the arm_rebuild_hflags() function after appl= ying the CP10,CP11 bits,
and that solved the assertion issue (see= below).

Can you verify if this change a= lso resolves the hflags assertion on your side?

I&= #39;ll also reply to the mail for patch #0006 with this info.
Regards,
Niek

diff =
--git a/target/arm/arm-powerctl.c b/target/arm/arm-powerctl.c
index f77a950db6..cf2f3d69ab 100644
--- a/target/arm/arm-powerctl.c
+++ b/target/arm/arm-powerctl.c
@@ -104,6 +104,9 @@ static void arm_set_cpu_on_async_work(CPUState *target_=
cpu_state,
         /* Processor is not in secure mode */
         target_cpu->env.cp15.scr_el3 |=3D SCR_NS;
=20
+        /* Set NSACR.{CP11,CP10} so NS can access the FPU */
+        target_cpu->env.cp15.nsacr |=3D 3 << 10;
+
         /*
          * If QEMU is providing the equivalent of EL3 firmware, then we ne=
ed
          * to make sure a CPU targeting EL2 comes out of reset with a
@@ -124,6 +127,9 @@ static void arm_set_cpu_on_async_work(CPUState *target_=
cpu_state,
         target_cpu->env.regs[0] =3D info->context_id;
     }
=20
+    /* Ensure hflags is rebuild */
+    arm_rebuild_hflags(&target_cpu->env);
+
     /* Start the new CPU at the requested address */
     cpu_set_pc(target_cpu_state, info->entry);
=20
=C2=A0

If it still fails, you might also add this one on top:
https://www.mail-archive.com/qemu-d= evel@nongnu.org/msg663843.html
and report the error.

That patch is indeed very helpful
=C2= =A0
>
> To reproduce it, build Linux 5.4.2 with the bmc2835_defconfig:
>
> $ ARCH=3Darm CROSS_COMPILE=3Darm-linux-gnueabi- make mrproper
> $ ARCH=3Darm CROSS_COMPILE=3Darm-linux-gnueabi- make bcm2835_defconfig=
> $ ARCH=3Darm CROSS_COMPILE=3Darm-linux-gnueabi- make -j5
> ...
>
> First build QEMU without debugging and try to boot linux:
> $ ./configure --target-list=3Darm-softmmu; make clean; make -j5
> $ ./arm-softmmu/qemu-system-arm -M raspi2 \
>=C2=A0 =C2=A0 -kernel $HOME/linux-5.4.2/arch/arm/boot/zImage \
>=C2=A0 =C2=A0 -append 'console=3DttyAMA0,115200 earlyprintk debug&#= 39; \
>=C2=A0 =C2=A0 -dtb $HOME/linux-5.4.2/arch/arm/boot/dts/bcm2836-rpi-2-b.= dtb \
>=C2=A0 =C2=A0 -m 1024 -nographic -s
> [=C2=A0 =C2=A0 0.000000] Booting Linux on physical CPU 0x0
> [=C2=A0 =C2=A0 0.000000] Linux version 5.4.2 (me@host) (gcc version 7.= 4.0 (Ubuntu/Linaro 7.4.0-1ubuntu1~18.04.1)) #1 Thu Dec 12 22:49:14 CET 2019=
> [=C2=A0 =C2=A0 0.000000] CPU: ARMv7 Processor [410fc075] revision 5 (A= RMv7), cr=3D10c53c7d
> ...
>
> Then rebuild QEMU with debugging enabled and again try to boot linux:<= br> > $ ./configure --target-list=3Darm-softmmu --enable-debug --extra-cflag= s=3D-ggdb; make clean; make -j5
> $ ./arm-softmmu/qemu-system-arm -M raspi2 \
>=C2=A0 =C2=A0 -kernel $HOME/linux-5.4.2/arch/arm/boot/zImage \
>=C2=A0 =C2=A0 -append 'console=3DttyAMA0,115200 earlyprintk debug&#= 39; \
>=C2=A0 =C2=A0 -dtb $HOME/linux-5.4.2/arch/arm/boot/dts/bcm2836-rpi-2-b.= dtb \
>=C2=A0 =C2=A0 -m 1024 -nographic -s
> qemu-system-arm: /home/me/qemu/target/arm/helper.c:11359: cpu_get_tb_c= pu_state: Assertion `flags =3D=3D rebuild_hflags_internal(env)' failed.=
> qemu-system-arm: /home/me/qemu/target/arm/helper.c:11359: cpu_get_tb_c= pu_state: Assertion `flags =3D=3D rebuild_hflags_internal(env)' failed.=
> qemu-system-arm: /home/me/qemu/target/arm/helper.c:11359: cpu_get_tb_c= pu_state: Assertion `flags =3D=3D rebuild_hflags_internal(env)' failed.=
> Aborted (core dumped)
>
> $ git describe
> v4.2.0
>
>
> What should be the next step? Should this be reported as a bug?

In this case we might already have the fix, but if Alex patch doesn't <= br> help, you are always welcome to open a bug report:
https://bugs.launchpad.net/qemu/+filebug
This help to have notes/progress gathered.

> On Tue, Dec 10, 2019 at 9:12 PM Niek Linnenbank
> <niek= linnenbank@gmail.com <mailto:nieklinnenbank@gmail.com>> wrote:
>
>=C2=A0 =C2=A0 =C2=A0Hi Philippe,
>
>=C2=A0 =C2=A0 =C2=A0On Tue, Dec 10, 2019 at 9:26 AM Philippe Mathieu-Da= ud=C3=A9
>=C2=A0 =C2=A0 =C2=A0<philmd@redhat.com <mailto:philmd@redhat.com>> wrote:
>
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0On 12/9/19 10:37 PM, Niek Linnenbank = wrote:
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 > Hi Philippe,
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 >
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 > On Tue, Dec 3, 2019 at 9:47 AM = Philippe Mathieu-Daud=C3=A9
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0<philmd@redhat.com <mailto:philmd@redhat.com>
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 > <mailto:philmd@redhat.com <mailto:philmd@redhat.com>&g= t;> wrote:
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 >
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 >=C2=A0 =C2=A0 =C2=A0On 12/2/19 1= 0:09 PM, Niek Linnenbank wrote:
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 >=C2=A0 =C2=A0 =C2=A0 > Dear Q= EMU developers,
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 >=C2=A0 =C2=A0 =C2=A0 >
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 >=C2=A0 =C2=A0 =C2=A0 > Hereby= I would like to contribute the following set of
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0patches to
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 >=C2=A0 =C2=A0 =C2=A0QEMU
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 >=C2=A0 =C2=A0 =C2=A0 > which = add support for the Allwinner H3 System on Chip
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0and the
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 >=C2=A0 =C2=A0 =C2=A0 > Orange= Pi PC machine. The following features and
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0devices are
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 >=C2=A0 =C2=A0 =C2=A0supported: >=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 >=C2=A0 =C2=A0 =C2=A0 >
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 >=C2=A0 =C2=A0 =C2=A0 >=C2=A0 = =C2=A0* SMP (Quad Core Cortex A7)
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 >=C2=A0 =C2=A0 =C2=A0 >=C2=A0 = =C2=A0* Generic Interrupt Controller configuration
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 >=C2=A0 =C2=A0 =C2=A0 >=C2=A0 = =C2=A0* SRAM mappings
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 >=C2=A0 =C2=A0 =C2=A0 >=C2=A0 = =C2=A0* Timer device (re-used from Allwinner A10)
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 >=C2=A0 =C2=A0 =C2=A0 >=C2=A0 = =C2=A0* UART
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 >=C2=A0 =C2=A0 =C2=A0 >=C2=A0 = =C2=A0* SD/MMC storage controller
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 >=C2=A0 =C2=A0 =C2=A0 >=C2=A0 = =C2=A0* EMAC ethernet connectivity
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 >=C2=A0 =C2=A0 =C2=A0 >=C2=A0 = =C2=A0* USB 2.0 interfaces
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 >=C2=A0 =C2=A0 =C2=A0 >=C2=A0 = =C2=A0* Clock Control Unit
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 >=C2=A0 =C2=A0 =C2=A0 >=C2=A0 = =C2=A0* System Control module
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 >=C2=A0 =C2=A0 =C2=A0 >=C2=A0 = =C2=A0* Security Identifier device
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 >
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 >=C2=A0 =C2=A0 =C2=A0Awesome!
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 >
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 >=C2=A0 =C2=A0 =C2=A0 > Functi= onality related to graphical output such as
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0HDMI, GPU,
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 >=C2=A0 =C2=A0 =C2=A0 > Displa= y Engine and audio are not included. Recently
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0released
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 >=C2=A0 =C2=A0 =C2=A0 > mainli= ne Linux kernels (4.19 up to latest master) and
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0mainline U-Boot
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 >=C2=A0 =C2=A0 =C2=A0 > are kn= own to work. The SD/MMC code is tested using
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0bonnie++ and
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 >=C2=A0 =C2=A0 =C2=A0 > variou= s tools such as fsck, dd and fdisk. The EMAC is
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0verified
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 >=C2=A0 =C2=A0 =C2=A0with iperf3<= br> >=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 >=C2=A0 =C2=A0 =C2=A0 > using = -netdev socket.
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 >=C2=A0 =C2=A0 =C2=A0 >
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 >=C2=A0 =C2=A0 =C2=A0 > To bui= ld a Linux mainline kernel that can be booted by
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0the Orange
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 >=C2=A0 =C2=A0 =C2=A0Pi PC
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 >=C2=A0 =C2=A0 =C2=A0 > machin= e, simply configure the kernel using the
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0sunxi_defconfig
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 >=C2=A0 =C2=A0 =C2=A0configuratio= n:
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 >=C2=A0 =C2=A0 =C2=A0 >=C2=A0 = =C2=A0$ ARCH=3Darm CROSS_COMPILE=3Darm-linux-gnueabi- make
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0mrproper
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 >=C2=A0 =C2=A0 =C2=A0 >=C2=A0 = =C2=A0$ ARCH=3Darm CROSS_COMPILE=3Darm-linux-gnueabi- make
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0sunxi_defconfig
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 >=C2=A0 =C2=A0 =C2=A0 >
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 >=C2=A0 =C2=A0 =C2=A0 > To be = able to use USB storage, you need to manually
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0enable the
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 >=C2=A0 =C2=A0 =C2=A0correspondin= g
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 >=C2=A0 =C2=A0 =C2=A0 > config= uration item. Start the kconfig configuration tool:
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 >=C2=A0 =C2=A0 =C2=A0 >=C2=A0 = =C2=A0$ ARCH=3Darm CROSS_COMPILE=3Darm-linux-gnueabi- make
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0menuconfig
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 >=C2=A0 =C2=A0 =C2=A0 >
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 >=C2=A0 =C2=A0 =C2=A0 > Naviga= te to the following item, enable it and save your
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 >=C2=A0 =C2=A0 =C2=A0configuratio= n:
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 >=C2=A0 =C2=A0 =C2=A0 >=C2=A0 = =C2=A0Device Drivers > USB support > USB Mass Storage support
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 >=C2=A0 =C2=A0 =C2=A0 >
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 >=C2=A0 =C2=A0 =C2=A0 > Build = the Linux kernel with:
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 >=C2=A0 =C2=A0 =C2=A0 >=C2=A0 = =C2=A0$ ARCH=3Darm CROSS_COMPILE=3Darm-linux-gnueabi- make -j5
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 >=C2=A0 =C2=A0 =C2=A0 >
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 >=C2=A0 =C2=A0 =C2=A0 > To boo= t the newly build linux kernel in QEMU with the
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0Orange Pi
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 >=C2=A0 =C2=A0 =C2=A0PC machine, = use:
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 >=C2=A0 =C2=A0 =C2=A0 >=C2=A0 = =C2=A0$ qemu-system-arm -M orangepi -m 512 -nic user
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0-nographic \
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 >=C2=A0 =C2=A0 =C2=A0 >=C2=A0 = =C2=A0 =C2=A0 =C2=A0-kernel /path/to/linux/arch/arm/boot/zImage \
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 >=C2=A0 =C2=A0 =C2=A0 >=C2=A0 = =C2=A0 =C2=A0 =C2=A0-append 'console=3DttyS0,115200' \
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 >=C2=A0 =C2=A0 =C2=A0 >=C2=A0 = =C2=A0 =C2=A0 =C2=A0-dtb
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0/path/to/linux/arch/arm/boot/dts/sun8= i-h3-orangepi-pc.dtb
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 >=C2=A0 =C2=A0 =C2=A0 >
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 >=C2=A0 =C2=A0 =C2=A0 > Note t= hat this kernel does not have a root filesystem.
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0You may
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 >=C2=A0 =C2=A0 =C2=A0provide it >=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 >=C2=A0 =C2=A0 =C2=A0 > with a= n official Orange Pi PC image [1] either as an
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0SD card or as
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 >=C2=A0 =C2=A0 =C2=A0 > USB ma= ss storage. To boot using the Orange Pi PC
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0Debian image on
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 >=C2=A0 =C2=A0 =C2=A0SD card,
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 >=C2=A0 =C2=A0 =C2=A0 > simply= add the -sd argument and provide the proper
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0root=3D kernel
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 >=C2=A0 =C2=A0 =C2=A0parameter: >=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 >=C2=A0 =C2=A0 =C2=A0 >=C2=A0 = =C2=A0$ qemu-system-arm -M orangepi -m 512 -nic user
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0-nographic \
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 >=C2=A0 =C2=A0 =C2=A0 >=C2=A0 = =C2=A0 =C2=A0 =C2=A0-kernel /path/to/linux/arch/arm/boot/zImage \
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 >=C2=A0 =C2=A0 =C2=A0 >=C2=A0 = =C2=A0 =C2=A0 =C2=A0-append 'console=3DttyS0,115200 root=3D/dev/mmcblk0= p2' \
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 >=C2=A0 =C2=A0 =C2=A0 >=C2=A0 = =C2=A0 =C2=A0 =C2=A0-dtb
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 >=C2=A0 =C2=A0 =C2=A0/path/to/lin= ux/arch/arm/boot/dts/sun8i-h3-orangepi-pc.dtb \
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 >=C2=A0 =C2=A0 =C2=A0 >=C2=A0 = =C2=A0 =C2=A0 =C2=A0-sd
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0OrangePi_pc_debian_stretch_server_lin= ux5.3.5_v1.0.img
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 >=C2=A0 =C2=A0 =C2=A0 >
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 >=C2=A0 =C2=A0 =C2=A0 > Altern= atively, you can also choose to build and boot a
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0recent
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 >=C2=A0 =C2=A0 =C2=A0buildroot [2= ]
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 >=C2=A0 =C2=A0 =C2=A0 > using = the orangepi_pc_defconfig or Armbian image [3]
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0for Orange
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 >=C2=A0 =C2=A0 =C2=A0Pi PC.
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 >
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 >=C2=A0 =C2=A0 =C2=A0Richard, try= ing the Armbian image from
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 > h= ttps://apt.armbian.com/pool/main/l/linux-4.20.7-sunxi/ I get:
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 >
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 >=C2=A0 =C2=A0 =C2=A0$ arm-softmm= u/qemu-system-arm -M orangepi -m 512 -nic user \
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 >=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0-append 'console=3DttyS0,115200' \
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 >=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0-kernel boot/vmlinuz-4.20.7-sunxi \
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 >=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0-dtb
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0usr/lib/linux-image-dev-sunxi/sun8i-h= 3-orangepi-pc.dtb \
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 >=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0-serial stdio -d unimp
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 >=C2=A0 =C2=A0 =C2=A0Uncompressin= g Linux... done, booting the kernel.
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 >=C2=A0 =C2=A0 =C2=A0rtc: unimple= mented device write (size 4, value
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A00x16aa0001, offset 0x0)
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 >=C2=A0 =C2=A0 =C2=A0rtc: unimple= mented device read (size 4, offset 0x0)
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 >=C2=A0 =C2=A0 =C2=A0rtc: unimple= mented device read (size 4, offset 0x0)
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 >=C2=A0 =C2=A0 =C2=A0rtc: unimple= mented device read (size 4, offset 0x8)
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 >=C2=A0 =C2=A0 =C2=A0qemu-system-= arm: target/arm/helper.c:11359:
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0cpu_get_tb_cpu_state:
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 >=C2=A0 =C2=A0 =C2=A0Assertion `f= lags =3D=3D rebuild_hflags_internal(env)' failed.
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 >=C2=A0 =C2=A0 =C2=A0Aborted (cor= e dumped)
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 >
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 >
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 > I'm trying to reproduce the= error you reported here with my
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0patch set on
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 > latest master,
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 > but so far without any result. = The host OS I'm using is
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0Ubuntu 18.04.3
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 > LTS on x86_64.
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 > I ran several times using the s= ame 4.20.7-sunxi kernel and
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0same command
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 > line.
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 >
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 > Some questions that might help:=
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 > 1) Are there any specific steps= you did in order to produce
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0this error?
>
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0I build QEMU with:
>
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0./configure --enable-trace-backends= =3Dlog --extra-cflags=3D-ggdb
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0--enable-debug
>
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 > 2) Could this be a known / exis= ting issue?
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 > 3) How many times did you see t= his error?
>
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0Always
>
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 > 4) Are you also using Ubuntu 18= .04.3 LTS on x86_64, or a
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0different host OS?
>
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0Host is Fedora 30.
>
>
>=C2=A0 =C2=A0 =C2=A0OK thanks, I will try again using the info above af= ter I finished
>=C2=A0 =C2=A0 =C2=A0reworking the other patch comments.
>
>=C2=A0 =C2=A0 =C2=A0Niek



--
Niek Linnenbank

--0000000000000d68d305999bf369-- From MAILER-DAEMON Fri Dec 13 15:52:41 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1ifrvV-0002eM-EB for mharc-qemu-arm@gnu.org; Fri, 13 Dec 2019 15:52:41 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:42787) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ifrvR-0002ac-LW for qemu-arm@nongnu.org; Fri, 13 Dec 2019 15:52:39 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ifrvQ-00086g-3o for qemu-arm@nongnu.org; Fri, 13 Dec 2019 15:52:37 -0500 Received: from mail-il1-x141.google.com ([2607:f8b0:4864:20::141]:40140) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ifrvM-0007v5-Kc; Fri, 13 Dec 2019 15:52:32 -0500 Received: by mail-il1-x141.google.com with SMTP id b15so540457ila.7; Fri, 13 Dec 2019 12:52:32 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=7O/3muIl5YW9JzXllxM/+0aPIk+ONdsqFZ3gZ4p5TYI=; b=c1EGIIBBlbP87N1dzNs3xElOM4EBJmIMGPQPkrXmKpYT8MjGjaCmezQRlHrTpa/QoP j5O57vytCX4zwpilrml3FJiHyvvHedbJmsXXAmItNbq/RlvPVFKQ5ye/IPsvFP+/Uv5g pPz9OMnZfyXwplsUe1PNAOjMsudT7O/tNcMMpAeqj6Z9+03VwU5ViXim+6x8Gzeiy6GD A8nRSVSEOJpWV/HhIUNKmMV8DQKRoQDSyZioCYDkXgL0cUNPo6GDyLsG7PKc+qGvbhjV VbsmT4RKoVK9rO4vVGrakU6gmEoAUf5la5glX2NifN/WV54vBteFHLYgBzk19I+fZmeu c7Ew== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=7O/3muIl5YW9JzXllxM/+0aPIk+ONdsqFZ3gZ4p5TYI=; b=qcD3PODdYjgrEI3Tc7bbweHSAxcND1tQomAqB1GQ+PUpGJZSXh0BTdWVjjdITsZt5w HK9yuMsr+V/H1dHI5U+6RM38yDEhmRrJV7UGTXfl21ePSafZ0B0d6YhHJL9A5724M0aH MUp4cRBt2KqH2lC0JDjm/uwOXMF8HNhKIG4w2CEJWA9mrUVpoF/UlEWfhHphV0MJN7Fp SDDZCY5ObwQb1wrGX8bINNquRqEOZsUe9xzCazoij+XknwbWJjD1mwYhBs8toSW5zXnK g5e6WxQyyvx3XVELkWfNFopx5zYUOEtNQX1Ur8uE4lCSDzizrBvo0/Sar+1lIpga2nGt I8wA== X-Gm-Message-State: APjAAAUHiDYJuJO2ppIBBJ9y5Feodrf0s1K9l0/Ws4zIwEOBOd4lB+Hv FHy2HIP8rtrLM3A7nF87q32Lbuto6YWpoFONu9k= X-Google-Smtp-Source: APXvYqytaePO8I+sLYzR0SzeHKg9G0ziNraGFu7hd3E2d8oXAc3lzg+yGnyR66uAXpLPKcfr2bsWlJhlxRXY9CcwSLw= X-Received: by 2002:a92:af08:: with SMTP id n8mr1201992ili.217.1576270351912; Fri, 13 Dec 2019 12:52:31 -0800 (PST) MIME-Version: 1.0 References: <20191202210947.3603-1-nieklinnenbank@gmail.com> <20191202210947.3603-7-nieklinnenbank@gmail.com> In-Reply-To: From: Niek Linnenbank Date: Fri, 13 Dec 2019 21:52:21 +0100 Message-ID: Subject: Re: [PATCH 06/10] arm/arm-powerctl: set NSACR.{CP11, CP10} bits in arm_set_cpu_on() To: Peter Maydell , =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= Cc: QEMU Developers , qemu-arm , Beniamino Galvani Content-Type: multipart/alternative; boundary="0000000000006552af05999c0a02" X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::141 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 13 Dec 2019 20:52:39 -0000 --0000000000006552af05999c0a02 Content-Type: text/plain; charset="UTF-8" Hi Peter, Philippe discovered that this patch triggers an hflags assertion error when building QEMU with debugging enabled (--enable-debug and --extra-cflags=-ggdb). See this thread for details: https://www.mail-archive.com/qemu-devel@nongnu.org/msg665049.html What I added to resolve that is to call arm_rebuild_hflags() after setting CP10,CP11. However I'm not sure of any other side effects because I just don't know this area of the code very well. Regards, Niek diff --git a/target/arm/arm-powerctl.c b/target/arm/arm-powerctl.c index f77a950db6..cf2f3d69ab 100644 --- a/target/arm/arm-powerctl.c +++ b/target/arm/arm-powerctl.c @@ -104,6 +104,9 @@ static void arm_set_cpu_on_async_work(CPUState *target_cpu_state, /* Processor is not in secure mode */ target_cpu->env.cp15.scr_el3 |= SCR_NS; + /* Set NSACR.{CP11,CP10} so NS can access the FPU */ + target_cpu->env.cp15.nsacr |= 3 << 10; + /* * If QEMU is providing the equivalent of EL3 firmware, then we need * to make sure a CPU targeting EL2 comes out of reset with a @@ -124,6 +127,9 @@ static void arm_set_cpu_on_async_work(CPUState *target_cpu_state, target_cpu->env.regs[0] = info->context_id; } + /* Ensure hflags is rebuild */ + arm_rebuild_hflags(&target_cpu->env); + /* Start the new CPU at the requested address */ cpu_set_pc(target_cpu_state, info->entry); On Fri, Dec 6, 2019 at 9:01 PM Niek Linnenbank wrote: > Hey Peter, > > On Fri, Dec 6, 2019 at 3:25 PM Peter Maydell > wrote: > >> On Mon, 2 Dec 2019 at 21:10, Niek Linnenbank >> wrote: >> > >> > This change ensures that the FPU can be accessed in Non-Secure mode >> > when the CPU core is reset using the arm_set_cpu_on() function call. >> > The NSACR.{CP11,CP10} bits define the exception level required to >> > access the FPU in Non-Secure mode. Without these bits set, the CPU >> > will give an undefined exception trap on the first FPU access for the >> > secondary cores under Linux. >> > >> > Fixes: fc1120a7f5 >> > Signed-off-by: Niek Linnenbank >> > --- >> >> Oops, another place where we failed to realise the ramifications >> of making NSACR actually do something. >> >> Since this is a bugfix I'm going to fish it out of this patchset >> and apply it to target-arm.next with a cc: stable. >> >> Thanks for the catch! >> > > Sure, I'm happy to help. Note that I only tested this fix with > the Allwinner H3 SoC patches that I'm working on. > > OK, I'll keep an eye out for it. Once it is solved in master, I'll remove > this patch from the patch series. > > Regards, > Niek > >> >> -- PMM >> > > > -- > Niek Linnenbank > > -- Niek Linnenbank --0000000000006552af05999c0a02 Content-Type: text/html; charset="UTF-8" Content-Transfer-Encoding: quoted-printable
Hi Peter,

Philippe discovere= d that this patch triggers an hflags assertion error when building QEMU
with debugging enabled (--enable-debug and --extra-cflags=3D-ggdb).<= /div>

See this thread for details:
What I added to resolve that is to call arm_rebuild_hflags() af= ter setting CP10,CP11.
However I'm not sure of any other side= effects because I just don't know this area of the code very well.
=

Regards,
Niek

<= div>
diff --git a/target/arm/arm-powerctl.c b/target/arm/arm-powerctl.c
index f77a950db6..cf2f3d69ab 100644
--- a/target/arm/arm-powerctl.c
+++ b/target/arm/arm-powerctl.c
@@ -104,6 +104,9 @@ static void arm_set_cpu_on_async_work(CPUState *target_=
cpu_state,
         /* Processor is not in secure mode */
         target_cpu->env.cp15.scr_el3 |=3D SCR_NS;
=20
+        /* Set NSACR.{CP11,CP10} so NS can access the FPU */
+        target_cpu->env.cp15.nsacr |=3D 3 << 10;
+
         /*
          * If QEMU is providing the equivalent of EL3 firmware, then we ne=
ed
          * to make sure a CPU targeting EL2 comes out of reset with a
@@ -124,6 +127,9 @@ static void arm_set_cpu_on_async_work(CPUState *target_=
cpu_state,
         target_cpu->env.regs[0] =3D info->context_id;
     }
=20
+    /* Ensure hflags is rebuild */
+    arm_rebuild_hflags(&target_cpu->env);
+
     /* Start the new CPU at the requested address */
     cpu_set_pc(target_cpu_state, info->entry);
=20



On Fri, Dec 6, 2019 at 9:01 = PM Niek Linnenbank <nieklinn= enbank@gmail.com> wrote:
Hey Peter,

On Fri, Dec 6, 2019 at = 3:25 PM Peter Maydell <peter.maydell@linaro.org> wrote:
On Mon, 2 Dec 2019 at 21:10, Niek Linn= enbank <ni= eklinnenbank@gmail.com> wrote:
>
> This change ensures that the FPU can be accessed in Non-Secure mode > when the CPU core is reset using the arm_set_cpu_on() function call. > The NSACR.{CP11,CP10} bits define the exception level required to
> access the FPU in Non-Secure mode. Without these bits set, the CPU
> will give an undefined exception trap on the first FPU access for the<= br> > secondary cores under Linux.
>
> Fixes: fc1120a7f5
> Signed-off-by: Niek Linnenbank <nieklinnenbank@gmail.com>
> ---

Oops, another place where we failed to realise the ramifications
of making NSACR actually do something.

Since this is a bugfix I'm going to fish it out of this patchset
and apply it to target-arm.next with a cc: stable.

Thanks for the catch!
=C2=A0
Sure, I= 9;m happy to help. Note that I only tested this fix with
the Allw= inner H3 SoC patches that I'm working on.

OK, I'll keep an eye out for it. Once it is solved in master, I'= ll remove this patch from the patch series.
=C2=A0
= Regards,
Niek

-- PMM


--
Niek Linnenbank



--
Niek Linnenbank

--0000000000006552af05999c0a02-- From MAILER-DAEMON Fri Dec 13 16:01:49 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1ifs4L-0007Gh-Gc for mharc-qemu-arm@gnu.org; Fri, 13 Dec 2019 16:01:49 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:58421) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ifs4A-00079D-TK for qemu-arm@nongnu.org; Fri, 13 Dec 2019 16:01:47 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ifs41-0003t9-Vq for qemu-arm@nongnu.org; Fri, 13 Dec 2019 16:01:38 -0500 Received: from mail-il1-x141.google.com ([2607:f8b0:4864:20::141]:36705) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ifs3j-0002eJ-8U; Fri, 13 Dec 2019 16:01:11 -0500 Received: by mail-il1-x141.google.com with SMTP id b15so582694iln.3; Fri, 13 Dec 2019 13:01:11 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=9/BMrQf3mcRwclQo5IjtFuJ54xGqaINnPEy9RJNJTRM=; b=Kj9NciEYK/rHehYvja7ZTaO8ljCKhyaoWXd+2tV3ZKX1Ol+eTvPdUFbl5QQsu0GwKc Un2neIhvGDznUWyyZDfqz2AIQFCYVIc/Br0dl82LGXFk31rIsOa18TnwFRF+lC5ywK2J XffLZs2WMhRc20Sbxhuec7K641yUFrI1cWRhXIjTqU5JsiJmrIq3/Cu0/5ZuG1GexmtS ENGOn6wiSdUIIwrgquXVHGIOnHSIqbvCdJmDVrhqoqWwVLFTw91Tt86Ki0GIfSCJqqCp HryTSck9Cm3+PNhbwnGTG4bFxvwjqEXZyetkYaUEuHPmkFr9A0qcesJPb/p/2Nbz8+7Y Hs5g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=9/BMrQf3mcRwclQo5IjtFuJ54xGqaINnPEy9RJNJTRM=; b=O6d+Kr9cbPHlhA0fFtFw1A3pNOqiSUndiWqQqa4dnzICO9JEF/1ep8gANKxrCl7ACs 8JhGWD2YHIHN4jnKPrqPheAEqkSpiRapnDprvFNx+5c6xf8vIXLtcpXEd+3UCxIiF+9w IRlLweOoI2xFBGHlS06RhXVCJWus4JJtey3K+gFnldKMfi4cZE2PsM5L2U7rPO/I00pP W5be4XPzqRjSenaP5+rwEGfeJFc0NfgGHhZ71HhdUk5NXOt1OZjyVJx1zwu81Kzfublf gelOj+pwXD6ICO9tqGb+SbW1M5LnD6Gq5dOtYN/8uljt4ZJ39H2DqvpsI63045hJB05T YvGA== X-Gm-Message-State: APjAAAUUksuY5gdKpUgzQKTrq2L/TqFXIvotEZ7pm58IiQw3PjP6NMPj Ymi62tS16JYZoToyKFgmJPDBwdUBM+k2MLFxaOk= X-Google-Smtp-Source: APXvYqzvMDaK5AmMw2f+37qHykGNuFhYIX2Sy3AXzP3z+QHbpPk1c1va9TMNPnRUB/3iviaRzH4IpC+cjmXtCh3p3BE= X-Received: by 2002:a92:5a45:: with SMTP id o66mr1227940ilb.67.1576270870130; Fri, 13 Dec 2019 13:01:10 -0800 (PST) MIME-Version: 1.0 References: <20191202210947.3603-1-nieklinnenbank@gmail.com> <20191202210947.3603-10-nieklinnenbank@gmail.com> <6bee15d7-7d80-0709-ac90-ef2052b39329@redhat.com> In-Reply-To: <6bee15d7-7d80-0709-ac90-ef2052b39329@redhat.com> From: Niek Linnenbank Date: Fri, 13 Dec 2019 22:00:59 +0100 Message-ID: Subject: Re: [PATCH 09/10] arm: allwinner-h3: add SD/MMC host controller To: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= Cc: QEMU Developers , qemu-arm , Peter Maydell , Beniamino Galvani Content-Type: multipart/alternative; boundary="00000000000048b6cc05999c2987" X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::141 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 13 Dec 2019 21:01:48 -0000 --00000000000048b6cc05999c2987 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable On Fri, Dec 13, 2019 at 12:56 AM Philippe Mathieu-Daud=C3=A9 wrote: > Hi Niek, > > On 12/11/19 11:34 PM, Niek Linnenbank wrote: > > Ping! > > > > Anyone would like to comment on this driver? > > > > I finished the rework on all previous comments in this series. > > > > Currently debugging the hflags error reported by Philippe. > > After that, I'm ready to send out v2 of these patches. > > > > Regards, > > Niek > > > > On Mon, Dec 2, 2019 at 10:10 PM Niek Linnenbank > > > wrote: > > > > The Allwinner H3 System on Chip contains an integrated storage > > controller for Secure Digital (SD) and Multi Media Card (MMC) > > interfaces. This commit adds support for the Allwinner H3 > > SD/MMC storage controller with the following emulated features: > > > > * DMA transfers > > * Direct FIFO I/O > > * Short/Long format command responses > > * Auto-Stop command (CMD12) > > * Insert & remove card detection > > > > Signed-off-by: Niek Linnenbank > > > > --- > > hw/arm/allwinner-h3.c | 20 + > > hw/arm/orangepi.c | 17 + > > hw/sd/Makefile.objs | 1 + > > hw/sd/allwinner-h3-sdhost.c | 791 > ++++++++++++++++++++++++++++ > > hw/sd/trace-events | 7 + > > include/hw/arm/allwinner-h3.h | 2 + > > include/hw/sd/allwinner-h3-sdhost.h | 73 +++ > > 7 files changed, 911 insertions(+) > > create mode 100644 hw/sd/allwinner-h3-sdhost.c > > create mode 100644 include/hw/sd/allwinner-h3-sdhost.h > > > > diff --git a/hw/arm/allwinner-h3.c b/hw/arm/allwinner-h3.c > > index 4fc4c8c725..c2972caf88 100644 > > --- a/hw/arm/allwinner-h3.c > > +++ b/hw/arm/allwinner-h3.c > > @@ -50,6 +50,9 @@ static void aw_h3_init(Object *obj) > > > > sysbus_init_child_obj(obj, "sid", &s->sid, sizeof(s->sid), > > TYPE_AW_H3_SID); > > + > > + sysbus_init_child_obj(obj, "mmc0", &s->mmc0, sizeof(s->mmc0), > > + TYPE_AW_H3_SDHOST); > > } > > > > static void aw_h3_realize(DeviceState *dev, Error **errp) > > @@ -217,6 +220,23 @@ static void aw_h3_realize(DeviceState *dev, > > Error **errp) > > } > > sysbus_mmio_map(SYS_BUS_DEVICE(&s->sid), 0, AW_H3_SID_BASE); > > > > + /* SD/MMC */ > > + object_property_set_bool(OBJECT(&s->mmc0), true, "realized", > &err); > > + if (err !=3D NULL) { > > + error_propagate(errp, err); > > + return; > > + } > > + sysbusdev =3D SYS_BUS_DEVICE(&s->mmc0); > > + sysbus_mmio_map(sysbusdev, 0, AW_H3_MMC0_BASE); > > + sysbus_connect_irq(sysbusdev, 0, s->irq[AW_H3_GIC_SPI_MMC0]); > > + > > + object_property_add_alias(OBJECT(s), "sd-bus", OBJECT(&s->mmc0= ), > > + "sd-bus", &err); > > + if (err) { > > + error_propagate(errp, err); > > + return; > > + } > > + > > /* Universal Serial Bus */ > > sysbus_create_simple(TYPE_AW_H3_EHCI, AW_H3_EHCI0_BASE, > > s->irq[AW_H3_GIC_SPI_EHCI0]); > > diff --git a/hw/arm/orangepi.c b/hw/arm/orangepi.c > > index 5ef2735f81..dee3efaf08 100644 > > --- a/hw/arm/orangepi.c > > +++ b/hw/arm/orangepi.c > > @@ -39,6 +39,10 @@ typedef struct OrangePiState { > > static void orangepi_init(MachineState *machine) > > { > > OrangePiState *s =3D g_new(OrangePiState, 1); > > + DriveInfo *di; > > + BlockBackend *blk; > > + BusState *bus; > > + DeviceState *carddev; > > Error *err =3D NULL; > > > > s->h3 =3D AW_H3(object_new(TYPE_AW_H3)); > > @@ -64,6 +68,18 @@ static void orangepi_init(MachineState *machine) > > exit(1); > > } > > > > + /* Create and plug in the SD card */ > > + di =3D drive_get_next(IF_SD); > > + blk =3D di ? blk_by_legacy_dinfo(di) : NULL; > > + bus =3D qdev_get_child_bus(DEVICE(s->h3), "sd-bus"); > > + if (bus =3D=3D NULL) { > > + error_report("No SD/MMC found in H3 object"); > > + exit(1); > > + } > > Your device always creates a bus, so I don't think the if(bus) check is > worthwhile. Eventually use an assert(bus)? > > > + carddev =3D qdev_create(bus, TYPE_SD_CARD); > > + qdev_prop_set_drive(carddev, "drive", blk, &error_fatal); > > + object_property_set_bool(OBJECT(carddev), true, "realized", > > &error_fatal); > > + > > /* RAM */ > > memory_region_allocate_system_memory(&s->sdram, NULL, > > "orangepi.ram", > > machine->ram_size); > > @@ -80,6 +96,7 @@ static void orangepi_machine_init(MachineClass *m= c) > > { > > mc->desc =3D "Orange Pi PC"; > > mc->init =3D orangepi_init; > > + mc->block_default_type =3D IF_SD; > > mc->units_per_default_bus =3D 1; > > mc->min_cpus =3D AW_H3_NUM_CPUS; > > mc->max_cpus =3D AW_H3_NUM_CPUS; > > diff --git a/hw/sd/Makefile.objs b/hw/sd/Makefile.objs > > index a884c238df..e7cc5ab739 100644 > > --- a/hw/sd/Makefile.objs > > +++ b/hw/sd/Makefile.objs > > @@ -4,6 +4,7 @@ common-obj-$(CONFIG_SD) +=3D sd.o core.o > sdmmc-internal.o > > common-obj-$(CONFIG_SDHCI) +=3D sdhci.o > > common-obj-$(CONFIG_SDHCI_PCI) +=3D sdhci-pci.o > > > > +obj-$(CONFIG_ALLWINNER_H3) +=3D allwinner-h3-sdhost.o > > obj-$(CONFIG_MILKYMIST) +=3D milkymist-memcard.o > > obj-$(CONFIG_OMAP) +=3D omap_mmc.o > > obj-$(CONFIG_PXA2XX) +=3D pxa2xx_mmci.o > > diff --git a/hw/sd/allwinner-h3-sdhost.c > b/hw/sd/allwinner-h3-sdhost.c > > new file mode 100644 > > index 0000000000..26e113a144 > > --- /dev/null > > +++ b/hw/sd/allwinner-h3-sdhost.c > > @@ -0,0 +1,791 @@ > > +/* > > + * Allwinner H3 SD Host Controller emulation > > + * > > + * Copyright (C) 2019 Niek Linnenbank > > > > + * > > + * This program is free software: you can redistribute it and/or > modify > > + * it under the terms of the GNU General Public License as > published by > > + * the Free Software Foundation, either version 2 of the License, = or > > + * (at your option) any later version. > > + * > > + * This program is distributed in the hope that it will be useful, > > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > > + * GNU General Public License for more details. > > + * > > + * You should have received a copy of the GNU General Public Licen= se > > + * along with this program. If not, see > > . > > + */ > > + > > +#include "qemu/osdep.h" > > +#include "qemu/log.h" > > +#include "qemu/module.h" > > +#include "sysemu/blockdev.h" > > +#include "hw/irq.h" > > +#include "hw/sd/allwinner-h3-sdhost.h" > > +#include "migration/vmstate.h" > > +#include "trace.h" > > + > > +#define TYPE_AW_H3_SDHOST_BUS "allwinner-h3-sdhost-bus" > > +#define AW_H3_SDHOST_BUS(obj) \ > > + OBJECT_CHECK(SDBus, (obj), TYPE_AW_H3_SDHOST_BUS) > > + > > +/* SD Host register offsets */ > > +#define REG_SD_GCTL (0x00) /* Global Control */ > > +#define REG_SD_CKCR (0x04) /* Clock Control */ > > +#define REG_SD_TMOR (0x08) /* Timeout */ > > +#define REG_SD_BWDR (0x0C) /* Bus Width */ > > +#define REG_SD_BKSR (0x10) /* Block Size */ > > +#define REG_SD_BYCR (0x14) /* Byte Count */ > > +#define REG_SD_CMDR (0x18) /* Command */ > > +#define REG_SD_CAGR (0x1C) /* Command Argument */ > > +#define REG_SD_RESP0 (0x20) /* Response Zero */ > > +#define REG_SD_RESP1 (0x24) /* Response One */ > > +#define REG_SD_RESP2 (0x28) /* Response Two */ > > +#define REG_SD_RESP3 (0x2C) /* Response Three */ > > +#define REG_SD_IMKR (0x30) /* Interrupt Mask */ > > +#define REG_SD_MISR (0x34) /* Masked Interrupt Status */ > > +#define REG_SD_RISR (0x38) /* Raw Interrupt Status */ > > +#define REG_SD_STAR (0x3C) /* Status */ > > +#define REG_SD_FWLR (0x40) /* FIFO Water Level */ > > +#define REG_SD_FUNS (0x44) /* FIFO Function Select */ > > +#define REG_SD_DBGC (0x50) /* Debug Enable */ > > +#define REG_SD_A12A (0x58) /* Auto command 12 argument */ > > +#define REG_SD_NTSR (0x5C) /* SD NewTiming Set */ > > +#define REG_SD_SDBG (0x60) /* SD newTiming Set Debug */ > > +#define REG_SD_HWRST (0x78) /* Hardware Reset Register */ > > +#define REG_SD_DMAC (0x80) /* Internal DMA Controller > > Control */ > > +#define REG_SD_DLBA (0x84) /* Descriptor List Base Address > */ > > +#define REG_SD_IDST (0x88) /* Internal DMA Controller > Status */ > > +#define REG_SD_IDIE (0x8C) /* Internal DMA Controller IRQ > > Enable */ > > +#define REG_SD_THLDC (0x100) /* Card Threshold Control */ > > +#define REG_SD_DSBD (0x10C) /* eMMC DDR Start Bit Detection > > Control */ > > +#define REG_SD_RES_CRC (0x110) /* Response CRC from card/eMMC = */ > > +#define REG_SD_DATA7_CRC (0x114) /* CRC Data 7 from card/eMMC */ > > +#define REG_SD_DATA6_CRC (0x118) /* CRC Data 6 from card/eMMC */ > > +#define REG_SD_DATA5_CRC (0x11C) /* CRC Data 5 from card/eMMC */ > > +#define REG_SD_DATA4_CRC (0x120) /* CRC Data 4 from card/eMMC */ > > +#define REG_SD_DATA3_CRC (0x124) /* CRC Data 3 from card/eMMC */ > > +#define REG_SD_DATA2_CRC (0x128) /* CRC Data 2 from card/eMMC */ > > +#define REG_SD_DATA1_CRC (0x12C) /* CRC Data 1 from card/eMMC */ > > +#define REG_SD_DATA0_CRC (0x130) /* CRC Data 0 from card/eMMC */ > > +#define REG_SD_CRC_STA (0x134) /* CRC status from card/eMMC > > during write */ > > +#define REG_SD_FIFO (0x200) /* Read/Write FIFO */ > > + > > +/* SD Host register flags */ > > +#define SD_GCTL_FIFO_AC_MOD (1 << 31) > > +#define SD_GCTL_DDR_MOD_SEL (1 << 10) > > +#define SD_GCTL_CD_DBC_ENB (1 << 8) > > +#define SD_GCTL_DMA_ENB (1 << 5) > > +#define SD_GCTL_INT_ENB (1 << 4) > > +#define SD_GCTL_DMA_RST (1 << 2) > > +#define SD_GCTL_FIFO_RST (1 << 1) > > +#define SD_GCTL_SOFT_RST (1 << 0) > > + > > +#define SD_CMDR_LOAD (1 << 31) > > +#define SD_CMDR_CLKCHANGE (1 << 21) > > +#define SD_CMDR_WRITE (1 << 10) > > +#define SD_CMDR_AUTOSTOP (1 << 12) > > +#define SD_CMDR_DATA (1 << 9) > > +#define SD_CMDR_RESPONSE_LONG (1 << 7) > > +#define SD_CMDR_RESPONSE (1 << 6) > > +#define SD_CMDR_CMDID_MASK (0x3f) > > + > > +#define SD_RISR_CARD_REMOVE (1 << 31) > > +#define SD_RISR_CARD_INSERT (1 << 30) > > +#define SD_RISR_AUTOCMD_DONE (1 << 14) > > +#define SD_RISR_DATA_COMPLETE (1 << 3) > > +#define SD_RISR_CMD_COMPLETE (1 << 2) > > +#define SD_RISR_NO_RESPONSE (1 << 1) > > + > > +#define SD_STAR_CARD_PRESENT (1 << 8) > > + > > +#define SD_IDST_SUM_RECEIVE_IRQ (1 << 8) > > +#define SD_IDST_RECEIVE_IRQ (1 << 1) > > +#define SD_IDST_TRANSMIT_IRQ (1 << 0) > > +#define SD_IDST_IRQ_MASK (SD_IDST_RECEIVE_IRQ | > > SD_IDST_TRANSMIT_IRQ | \ > > + SD_IDST_SUM_RECEIVE_IRQ) > > +#define SD_IDST_WR_MASK (0x3ff) > > + > > +/* SD Host register reset values */ > > +#define REG_SD_GCTL_RST (0x00000300) > > +#define REG_SD_CKCR_RST (0x0) > > +#define REG_SD_TMOR_RST (0xFFFFFF40) > > +#define REG_SD_BWDR_RST (0x0) > > +#define REG_SD_BKSR_RST (0x00000200) > > +#define REG_SD_BYCR_RST (0x00000200) > > +#define REG_SD_CMDR_RST (0x0) > > +#define REG_SD_CAGR_RST (0x0) > > +#define REG_SD_RESP_RST (0x0) > > +#define REG_SD_IMKR_RST (0x0) > > +#define REG_SD_MISR_RST (0x0) > > +#define REG_SD_RISR_RST (0x0) > > +#define REG_SD_STAR_RST (0x00000100) > > +#define REG_SD_FWLR_RST (0x000F0000) > > +#define REG_SD_FUNS_RST (0x0) > > +#define REG_SD_DBGC_RST (0x0) > > +#define REG_SD_A12A_RST (0x0000FFFF) > > +#define REG_SD_NTSR_RST (0x00000001) > > +#define REG_SD_SDBG_RST (0x0) > > +#define REG_SD_HWRST_RST (0x00000001) > > +#define REG_SD_DMAC_RST (0x0) > > +#define REG_SD_DLBA_RST (0x0) > > +#define REG_SD_IDST_RST (0x0) > > +#define REG_SD_IDIE_RST (0x0) > > +#define REG_SD_THLDC_RST (0x0) > > +#define REG_SD_DSBD_RST (0x0) > > +#define REG_SD_RES_CRC_RST (0x0) > > +#define REG_SD_DATA_CRC_RST (0x0) > > +#define REG_SD_CRC_STA_RST (0x0) > > +#define REG_SD_FIFO_RST (0x0) > > + > > +/* Data transfer descriptor for DMA */ > > +typedef struct TransferDescriptor { > > + uint32_t status; /* Status flags */ > > + uint32_t size; /* Data buffer size */ > > + uint32_t addr; /* Data buffer address */ > > + uint32_t next; /* Physical address of next descriptor */ > > +} TransferDescriptor; > > + > > +/* Data transfer descriptor flags */ > > +#define DESC_STATUS_HOLD (1 << 31) /* Set when descriptor is in > > use by DMA */ > > +#define DESC_STATUS_ERROR (1 << 30) /* Set when DMA transfer erro= r > > occurred */ > > +#define DESC_STATUS_CHAIN (1 << 4) /* Indicates chained > > descriptor. */ > > +#define DESC_STATUS_FIRST (1 << 3) /* Set on the first descripto= r > */ > > +#define DESC_STATUS_LAST (1 << 2) /* Set on the last descriptor > */ > > +#define DESC_STATUS_NOIRQ (1 << 1) /* Skip raising interrupt > > after transfer */ > > + > > +#define DESC_SIZE_MASK (0xfffffffc) > > + > > +static void aw_h3_sdhost_update_irq(AwH3SDHostState *s) > > +{ > > + uint32_t irq_en =3D s->global_ctl & SD_GCTL_INT_ENB; > > + uint32_t irq =3D irq_en ? s->irq_status & s->irq_mask : 0; > > The previous line is confuse, either use parenthesis or a if statement. > > uint32_t irq =3D irq_en ? (s->irq_status & s->irq_mask) : 0; > > > + > > + trace_aw_h3_sdhost_update_irq(irq); > > + qemu_set_irq(s->irq, irq); > > +} > > + > > +static void aw_h3_sdhost_update_transfer_cnt(AwH3SDHostState *s, > > uint32_t bytes) > > +{ > > + if (s->transfer_cnt > bytes) { > > + s->transfer_cnt -=3D bytes; > > + } else { > > + s->transfer_cnt =3D 0; > > + } > > + > > + if (!s->transfer_cnt) { > > + s->irq_status |=3D SD_RISR_DATA_COMPLETE | > SD_RISR_AUTOCMD_DONE; > > + } > > +} > > + > > +static void aw_h3_sdhost_set_inserted(DeviceState *dev, bool > inserted) > > +{ > > + AwH3SDHostState *s =3D AW_H3_SDHOST(dev); > > + > > + trace_aw_h3_sdhost_set_inserted(inserted); > > + > > + if (inserted) { > > + s->irq_status |=3D SD_RISR_CARD_INSERT; > > + s->irq_status &=3D ~SD_RISR_CARD_REMOVE; > > + s->status |=3D SD_STAR_CARD_PRESENT; > > + } else { > > + s->irq_status &=3D ~SD_RISR_CARD_INSERT; > > + s->irq_status |=3D SD_RISR_CARD_REMOVE; > > + s->status &=3D ~SD_STAR_CARD_PRESENT; > > + } > > + > > + aw_h3_sdhost_update_irq(s); > > +} > > + > > +static void aw_h3_sdhost_send_command(AwH3SDHostState *s) > > +{ > > + SDRequest request; > > + uint8_t resp[16]; > > + int rlen; > > + > > + /* Auto clear load flag */ > > + s->command &=3D ~SD_CMDR_LOAD; > > + > > + /* Clock change does not actually interact with the SD bus */ > > + if (!(s->command & SD_CMDR_CLKCHANGE)) { > > + > > + /* Prepare request */ > > + request.cmd =3D s->command & SD_CMDR_CMDID_MASK; > > + request.arg =3D s->command_arg; > > + > > + /* Send request to SD bus */ > > + rlen =3D sdbus_do_command(&s->sdbus, &request, resp); > > + if (rlen < 0) { > > + goto error; > > + } > > + > > + /* If the command has a response, store it in the response > > registers */ > > + if ((s->command & SD_CMDR_RESPONSE)) { > > + if (rlen =3D=3D 0 || > > + (rlen =3D=3D 4 && (s->command & SD_CMDR_RESPONSE_LO= NG))) > { > > + goto error; > > + } > > + if (rlen !=3D 4 && rlen !=3D 16) { > > + goto error; > > + } > > Maybe remove previous if... > > > + if (rlen =3D=3D 4) { > > + s->response[0] =3D ldl_be_p(&resp[0]); > > + s->response[1] =3D s->response[2] =3D s->response[= 3] =3D > 0; > > + } else { > > ... > > } else if (rlen =3D=3D 16) { ... > > > + s->response[0] =3D ldl_be_p(&resp[12]); > > + s->response[1] =3D ldl_be_p(&resp[8]); > > + s->response[2] =3D ldl_be_p(&resp[4]); > > + s->response[3] =3D ldl_be_p(&resp[0]); > > ... > > } else { > goto error; > > > + } > > + } > > + } > > + > > + /* Set interrupt status bits */ > > + s->irq_status |=3D SD_RISR_CMD_COMPLETE; > > + return; > > + > > +error: > > + s->irq_status |=3D SD_RISR_NO_RESPONSE; > > +} > > + > > +static void aw_h3_sdhost_auto_stop(AwH3SDHostState *s) > > +{ > > + /* > > + * The stop command (CMD12) ensures the SD bus > > + * returns to the transfer state. > > + */ > > + if ((s->command & SD_CMDR_AUTOSTOP) && (s->transfer_cnt =3D=3D= 0)) { > > + /* First save current command registers */ > > + uint32_t saved_cmd =3D s->command; > > + uint32_t saved_arg =3D s->command_arg; > > + > > + /* Prepare stop command (CMD12) */ > > + s->command &=3D ~SD_CMDR_CMDID_MASK; > > + s->command |=3D 12; /* CMD12 */ > > + s->command_arg =3D 0; > > + > > + /* Put the command on SD bus */ > > + aw_h3_sdhost_send_command(s); > > + > > + /* Restore command values */ > > + s->command =3D saved_cmd; > > + s->command_arg =3D saved_arg; > > + } > > +} > > + > > +static uint32_t aw_h3_sdhost_process_desc(AwH3SDHostState *s, > > + hwaddr desc_addr, > > + TransferDescriptor *desc= , > > + bool is_write, uint32_t > > max_bytes) > > +{ > > + uint32_t num_done =3D 0; > > + uint32_t num_bytes =3D max_bytes; > > + uint8_t buf[1024]; > > + > > + /* Read descriptor */ > > + cpu_physical_memory_read(desc_addr, desc, sizeof(*desc)); > > Should we worry about endianess here? > > > + if (desc->size =3D=3D 0) { > > + desc->size =3D 0xffff + 1; > > Why not write '64 * KiB'? > > > + } > > + if (desc->size < num_bytes) { > > + num_bytes =3D desc->size; > > + } > > + > > + trace_aw_h3_sdhost_process_desc(desc_addr, desc->size, > > is_write, max_bytes); > > + > > + while (num_done < num_bytes) { > > + /* Try to completely fill the local buffer */ > > + uint32_t buf_bytes =3D num_bytes - num_done; > > + if (buf_bytes > sizeof(buf)) { > > + buf_bytes =3D sizeof(buf); > > + } > > + > > + /* Write to SD bus */ > > + if (is_write) { > > + cpu_physical_memory_read((desc->addr & DESC_SIZE_MASK) > > + num_done, > > + buf, buf_bytes); > > + > > + for (uint32_t i =3D 0; i < buf_bytes; i++) { > > + sdbus_write_data(&s->sdbus, buf[i]); > > + } > > + > > + /* Read from SD bus */ > > + } else { > > + for (uint32_t i =3D 0; i < buf_bytes; i++) { > > + buf[i] =3D sdbus_read_data(&s->sdbus); > > + } > > + cpu_physical_memory_write((desc->addr & DESC_SIZE_MASK= ) > > + num_done, > > + buf, buf_bytes); > > + } > > + num_done +=3D buf_bytes; > > + } > > + > > + /* Clear hold flag and flush descriptor */ > > + desc->status &=3D ~DESC_STATUS_HOLD; > > + cpu_physical_memory_write(desc_addr, desc, sizeof(*desc)); > > (Related to previous endianess question). > > > + > > + return num_done; > > +} > > + > > +static void aw_h3_sdhost_dma(AwH3SDHostState *s) > > +{ > > + TransferDescriptor desc; > > + hwaddr desc_addr =3D s->desc_base; > > + bool is_write =3D (s->command & SD_CMDR_WRITE); > > + uint32_t bytes_done =3D 0; > > + > > + /* Check if DMA can be performed */ > > + if (s->byte_count =3D=3D 0 || s->block_size =3D=3D 0 || > > + !(s->global_ctl & SD_GCTL_DMA_ENB)) { > > + return; > > + } > > + > > + /* > > + * For read operations, data must be available on the SD bus > > + * If not, it is an error and we should not act at all > > + */ > > + if (!is_write && !sdbus_data_ready(&s->sdbus)) { > > + return; > > + } > > + > > + /* Process the DMA descriptors until all data is copied */ > > + while (s->byte_count > 0) { > > + bytes_done =3D aw_h3_sdhost_process_desc(s, desc_addr, &de= sc, > > + is_write, > > s->byte_count); > > + aw_h3_sdhost_update_transfer_cnt(s, bytes_done); > > + > > + if (bytes_done <=3D s->byte_count) { > > + s->byte_count -=3D bytes_done; > > + } else { > > + s->byte_count =3D 0; > > + } > > + > > + if (desc.status & DESC_STATUS_LAST) { > > + break; > > + } else { > > + desc_addr =3D desc.next; > > + } > > + } > > + > > + /* Raise IRQ to signal DMA is completed */ > > + s->irq_status |=3D SD_RISR_DATA_COMPLETE | SD_RISR_AUTOCMD_DON= E; > > + > > + /* Update DMAC bits */ > > + if (is_write) { > > + s->dmac_status |=3D SD_IDST_TRANSMIT_IRQ; > > + } else { > > + s->dmac_status |=3D (SD_IDST_SUM_RECEIVE_IRQ | > > SD_IDST_RECEIVE_IRQ); > > + } > > +} > > + > > +static uint64_t aw_h3_sdhost_read(void *opaque, hwaddr offset, > > + unsigned size) > > +{ > > + AwH3SDHostState *s =3D (AwH3SDHostState *)opaque; > > + uint32_t res =3D 0; > > + > > + switch (offset) { > > + case REG_SD_GCTL: /* Global Control */ > > + res =3D s->global_ctl; > > + break; > > + case REG_SD_CKCR: /* Clock Control */ > > + res =3D s->clock_ctl; > > + break; > > + case REG_SD_TMOR: /* Timeout */ > > + res =3D s->timeout; > > + break; > > + case REG_SD_BWDR: /* Bus Width */ > > + res =3D s->bus_width; > > + break; > > + case REG_SD_BKSR: /* Block Size */ > > + res =3D s->block_size; > > + break; > > + case REG_SD_BYCR: /* Byte Count */ > > + res =3D s->byte_count; > > + break; > > + case REG_SD_CMDR: /* Command */ > > + res =3D s->command; > > + break; > > + case REG_SD_CAGR: /* Command Argument */ > > + res =3D s->command_arg; > > + break; > > + case REG_SD_RESP0: /* Response Zero */ > > + res =3D s->response[0]; > > + break; > > + case REG_SD_RESP1: /* Response One */ > > + res =3D s->response[1]; > > + break; > > + case REG_SD_RESP2: /* Response Two */ > > + res =3D s->response[2]; > > + break; > > + case REG_SD_RESP3: /* Response Three */ > > + res =3D s->response[3]; > > + break; > > + case REG_SD_IMKR: /* Interrupt Mask */ > > + res =3D s->irq_mask; > > + break; > > + case REG_SD_MISR: /* Masked Interrupt Status */ > > + res =3D s->irq_status & s->irq_mask; > > + break; > > + case REG_SD_RISR: /* Raw Interrupt Status */ > > + res =3D s->irq_status; > > + break; > > + case REG_SD_STAR: /* Status */ > > + res =3D s->status; > > + break; > > + case REG_SD_FWLR: /* FIFO Water Level */ > > + res =3D s->fifo_wlevel; > > + break; > > + case REG_SD_FUNS: /* FIFO Function Select */ > > + res =3D s->fifo_func_sel; > > + break; > > + case REG_SD_DBGC: /* Debug Enable */ > > + res =3D s->debug_enable; > > + break; > > + case REG_SD_A12A: /* Auto command 12 argument */ > > + res =3D s->auto12_arg; > > + break; > > + case REG_SD_NTSR: /* SD NewTiming Set */ > > + res =3D s->newtiming_set; > > + break; > > + case REG_SD_SDBG: /* SD newTiming Set Debug */ > > + res =3D s->newtiming_debug; > > + break; > > + case REG_SD_HWRST: /* Hardware Reset Register */ > > + res =3D s->hardware_rst; > > + break; > > + case REG_SD_DMAC: /* Internal DMA Controller Control */ > > + res =3D s->dmac; > > + break; > > + case REG_SD_DLBA: /* Descriptor List Base Address */ > > + res =3D s->desc_base; > > + break; > > + case REG_SD_IDST: /* Internal DMA Controller Status */ > > + res =3D s->dmac_status; > > + break; > > + case REG_SD_IDIE: /* Internal DMA Controller Interrupt > > Enable */ > > + res =3D s->dmac_irq; > > + break; > > + case REG_SD_THLDC: /* Card Threshold Control */ > > + res =3D s->card_threshold; > > + break; > > + case REG_SD_DSBD: /* eMMC DDR Start Bit Detection Control > */ > > + res =3D s->startbit_detect; > > + break; > > + case REG_SD_RES_CRC: /* Response CRC from card/eMMC */ > > + res =3D s->response_crc; > > + break; > > + case REG_SD_DATA7_CRC: /* CRC Data 7 from card/eMMC */ > > + case REG_SD_DATA6_CRC: /* CRC Data 6 from card/eMMC */ > > + case REG_SD_DATA5_CRC: /* CRC Data 5 from card/eMMC */ > > + case REG_SD_DATA4_CRC: /* CRC Data 4 from card/eMMC */ > > + case REG_SD_DATA3_CRC: /* CRC Data 3 from card/eMMC */ > > + case REG_SD_DATA2_CRC: /* CRC Data 2 from card/eMMC */ > > + case REG_SD_DATA1_CRC: /* CRC Data 1 from card/eMMC */ > > + case REG_SD_DATA0_CRC: /* CRC Data 0 from card/eMMC */ > > + res =3D s->data_crc[((offset - REG_SD_DATA7_CRC) / > > sizeof(uint32_t))]; > > + break; > > + case REG_SD_CRC_STA: /* CRC status from card/eMMC in write > > operation */ > > + res =3D s->status_crc; > > + break; > > + case REG_SD_FIFO: /* Read/Write FIFO */ > > + if (sdbus_data_ready(&s->sdbus)) { > > + res =3D sdbus_read_data(&s->sdbus); > > + res |=3D sdbus_read_data(&s->sdbus) << 8; > > + res |=3D sdbus_read_data(&s->sdbus) << 16; > > + res |=3D sdbus_read_data(&s->sdbus) << 24; > > + aw_h3_sdhost_update_transfer_cnt(s, sizeof(uint32_t)); > > + aw_h3_sdhost_auto_stop(s); > > + aw_h3_sdhost_update_irq(s); > > + } else { > > + qemu_log_mask(LOG_GUEST_ERROR, "%s: no data ready on S= D > > bus\n", > > + __func__); > > + } > > + break; > > + default: > > + qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset > > %"HWADDR_PRIx"\n", > > + __func__, offset); > > + res =3D 0; > > + break; > > + } > > + > > + trace_aw_h3_sdhost_read(offset, res, size); > > + return res; > > +} > > + > > +static void aw_h3_sdhost_write(void *opaque, hwaddr offset, > > + uint64_t value, unsigned size) > > +{ > > + AwH3SDHostState *s =3D (AwH3SDHostState *)opaque; > > + > > + trace_aw_h3_sdhost_write(offset, value, size); > > + > > + switch (offset) { > > + case REG_SD_GCTL: /* Global Control */ > > + s->global_ctl =3D value; > > + s->global_ctl &=3D ~(SD_GCTL_DMA_RST | SD_GCTL_FIFO_RST | > > + SD_GCTL_SOFT_RST); > > + aw_h3_sdhost_update_irq(s); > > + break; > > + case REG_SD_CKCR: /* Clock Control */ > > + s->clock_ctl =3D value; > > + break; > > + case REG_SD_TMOR: /* Timeout */ > > + s->timeout =3D value; > > + break; > > + case REG_SD_BWDR: /* Bus Width */ > > + s->bus_width =3D value; > > + break; > > + case REG_SD_BKSR: /* Block Size */ > > + s->block_size =3D value; > > + break; > > + case REG_SD_BYCR: /* Byte Count */ > > + s->byte_count =3D value; > > + s->transfer_cnt =3D value; > > + break; > > + case REG_SD_CMDR: /* Command */ > > + s->command =3D value; > > + if (value & SD_CMDR_LOAD) { > > + aw_h3_sdhost_send_command(s); > > + aw_h3_sdhost_dma(s); > > + aw_h3_sdhost_auto_stop(s); > > + } > > + aw_h3_sdhost_update_irq(s); > > + break; > > + case REG_SD_CAGR: /* Command Argument */ > > + s->command_arg =3D value; > > + break; > > + case REG_SD_RESP0: /* Response Zero */ > > + s->response[0] =3D value; > > + break; > > + case REG_SD_RESP1: /* Response One */ > > + s->response[1] =3D value; > > + break; > > + case REG_SD_RESP2: /* Response Two */ > > + s->response[2] =3D value; > > + break; > > + case REG_SD_RESP3: /* Response Three */ > > + s->response[3] =3D value; > > + break; > > + case REG_SD_IMKR: /* Interrupt Mask */ > > + s->irq_mask =3D value; > > + aw_h3_sdhost_update_irq(s); > > + break; > > + case REG_SD_MISR: /* Masked Interrupt Status */ > > + case REG_SD_RISR: /* Raw Interrupt Status */ > > + s->irq_status &=3D ~value; > > + aw_h3_sdhost_update_irq(s); > > + break; > > + case REG_SD_STAR: /* Status */ > > + s->status &=3D ~value; > > + aw_h3_sdhost_update_irq(s); > > + break; > > + case REG_SD_FWLR: /* FIFO Water Level */ > > + s->fifo_wlevel =3D value; > > + break; > > + case REG_SD_FUNS: /* FIFO Function Select */ > > + s->fifo_func_sel =3D value; > > + break; > > + case REG_SD_DBGC: /* Debug Enable */ > > + s->debug_enable =3D value; > > + break; > > + case REG_SD_A12A: /* Auto command 12 argument */ > > + s->auto12_arg =3D value; > > + break; > > + case REG_SD_NTSR: /* SD NewTiming Set */ > > + s->newtiming_set =3D value; > > + break; > > + case REG_SD_SDBG: /* SD newTiming Set Debug */ > > + s->newtiming_debug =3D value; > > + break; > > + case REG_SD_HWRST: /* Hardware Reset Register */ > > + s->hardware_rst =3D value; > > + break; > > + case REG_SD_DMAC: /* Internal DMA Controller Control */ > > + s->dmac =3D value; > > + aw_h3_sdhost_update_irq(s); > > + break; > > + case REG_SD_DLBA: /* Descriptor List Base Address */ > > + s->desc_base =3D value; > > + break; > > + case REG_SD_IDST: /* Internal DMA Controller Status */ > > + s->dmac_status &=3D (~SD_IDST_WR_MASK) | (~value & > > SD_IDST_WR_MASK); > > + aw_h3_sdhost_update_irq(s); > > + break; > > + case REG_SD_IDIE: /* Internal DMA Controller Interrupt > > Enable */ > > + s->dmac_irq =3D value; > > + aw_h3_sdhost_update_irq(s); > > + break; > > + case REG_SD_THLDC: /* Card Threshold Control */ > > + s->card_threshold =3D value; > > + break; > > + case REG_SD_DSBD: /* eMMC DDR Start Bit Detection Control > */ > > + s->startbit_detect =3D value; > > + break; > > + case REG_SD_FIFO: /* Read/Write FIFO */ > > + sdbus_write_data(&s->sdbus, value & 0xff); > > + sdbus_write_data(&s->sdbus, (value >> 8) & 0xff); > > + sdbus_write_data(&s->sdbus, (value >> 16) & 0xff); > > + sdbus_write_data(&s->sdbus, (value >> 24) & 0xff); > > + aw_h3_sdhost_update_transfer_cnt(s, sizeof(uint32_t)); > > + aw_h3_sdhost_auto_stop(s); > > + aw_h3_sdhost_update_irq(s); > > + break; > > + case REG_SD_RES_CRC: /* Response CRC from card/eMMC */ > > + case REG_SD_DATA7_CRC: /* CRC Data 7 from card/eMMC */ > > + case REG_SD_DATA6_CRC: /* CRC Data 6 from card/eMMC */ > > + case REG_SD_DATA5_CRC: /* CRC Data 5 from card/eMMC */ > > + case REG_SD_DATA4_CRC: /* CRC Data 4 from card/eMMC */ > > + case REG_SD_DATA3_CRC: /* CRC Data 3 from card/eMMC */ > > + case REG_SD_DATA2_CRC: /* CRC Data 2 from card/eMMC */ > > + case REG_SD_DATA1_CRC: /* CRC Data 1 from card/eMMC */ > > + case REG_SD_DATA0_CRC: /* CRC Data 0 from card/eMMC */ > > + case REG_SD_CRC_STA: /* CRC status from card/eMMC in write > > operation */ > > + break; > > + default: > > + qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset > > %"HWADDR_PRIx"\n", > > + __func__, offset); > > + break; > > + } > > +} > > + > > +static const MemoryRegionOps aw_h3_sdhost_ops =3D { > > + .read =3D aw_h3_sdhost_read, > > + .write =3D aw_h3_sdhost_write, > > + .endianness =3D DEVICE_NATIVE_ENDIAN, > > I haven't checked .valid accesses from the datasheet. > > However due to: > > res =3D s->data_crc[((offset - REG_SD_DATA7_CRC) / sizeof(uint32_t))]; > > You seem to expect: > > .impl.min_access_size =3D 4, > > .impl.max_access_size unset is 8, which should works. > > > +}; > > + > > +static const VMStateDescription vmstate_aw_h3_sdhost =3D { > > + .name =3D TYPE_AW_H3_SDHOST, > > Do not use TYPE name in VMStateDescription.name, because we might change > the value of TYPE, but the migration state has to keep the same name. > > > + .version_id =3D 1, > > + .minimum_version_id =3D 1, > > + .fields =3D (VMStateField[]) { > > + VMSTATE_UINT32(global_ctl, AwH3SDHostState), > > + VMSTATE_UINT32(clock_ctl, AwH3SDHostState), > > + VMSTATE_UINT32(timeout, AwH3SDHostState), > > + VMSTATE_UINT32(bus_width, AwH3SDHostState), > > + VMSTATE_UINT32(block_size, AwH3SDHostState), > > + VMSTATE_UINT32(byte_count, AwH3SDHostState), > > + VMSTATE_UINT32(transfer_cnt, AwH3SDHostState), > > + VMSTATE_UINT32(command, AwH3SDHostState), > > + VMSTATE_UINT32(command_arg, AwH3SDHostState), > > + VMSTATE_UINT32_ARRAY(response, AwH3SDHostState, 4), > > + VMSTATE_UINT32(irq_mask, AwH3SDHostState), > > + VMSTATE_UINT32(irq_status, AwH3SDHostState), > > + VMSTATE_UINT32(status, AwH3SDHostState), > > + VMSTATE_UINT32(fifo_wlevel, AwH3SDHostState), > > + VMSTATE_UINT32(fifo_func_sel, AwH3SDHostState), > > + VMSTATE_UINT32(debug_enable, AwH3SDHostState), > > + VMSTATE_UINT32(auto12_arg, AwH3SDHostState), > > + VMSTATE_UINT32(newtiming_set, AwH3SDHostState), > > + VMSTATE_UINT32(newtiming_debug, AwH3SDHostState), > > + VMSTATE_UINT32(hardware_rst, AwH3SDHostState), > > + VMSTATE_UINT32(dmac, AwH3SDHostState), > > + VMSTATE_UINT32(desc_base, AwH3SDHostState), > > + VMSTATE_UINT32(dmac_status, AwH3SDHostState), > > + VMSTATE_UINT32(dmac_irq, AwH3SDHostState), > > + VMSTATE_UINT32(card_threshold, AwH3SDHostState), > > + VMSTATE_UINT32(startbit_detect, AwH3SDHostState), > > + VMSTATE_UINT32(response_crc, AwH3SDHostState), > > + VMSTATE_UINT32_ARRAY(data_crc, AwH3SDHostState, 8), > > + VMSTATE_UINT32(status_crc, AwH3SDHostState), > > + VMSTATE_END_OF_LIST() > > + } > > +}; > > + > > +static void aw_h3_sdhost_init(Object *obj) > > +{ > > + AwH3SDHostState *s =3D AW_H3_SDHOST(obj); > > + > > + qbus_create_inplace(&s->sdbus, sizeof(s->sdbus), > > + TYPE_AW_H3_SDHOST_BUS, DEVICE(s), "sd-bus"= ); > > + > > + memory_region_init_io(&s->iomem, obj, &aw_h3_sdhost_ops, s, > > + TYPE_AW_H3_SDHOST, > > AW_H3_SDHOST_REGS_MEM_SIZE); > > + sysbus_init_mmio(SYS_BUS_DEVICE(s), &s->iomem); > > + sysbus_init_irq(SYS_BUS_DEVICE(s), &s->irq); > > +} > > + > > +static void aw_h3_sdhost_reset(DeviceState *dev) > > +{ > > + AwH3SDHostState *s =3D AW_H3_SDHOST(dev); > > + > > + s->global_ctl =3D REG_SD_GCTL_RST; > > + s->clock_ctl =3D REG_SD_CKCR_RST; > > + s->timeout =3D REG_SD_TMOR_RST; > > + s->bus_width =3D REG_SD_BWDR_RST; > > + s->block_size =3D REG_SD_BKSR_RST; > > + s->byte_count =3D REG_SD_BYCR_RST; > > + s->transfer_cnt =3D 0; > > + > > + s->command =3D REG_SD_CMDR_RST; > > + s->command_arg =3D REG_SD_CAGR_RST; > > + > > + for (int i =3D 0; i < sizeof(s->response) / > > sizeof(s->response[0]); i++) { > > Please use ARRAY_SIZE(s->response). > > > + s->response[i] =3D REG_SD_RESP_RST; > > + } > > + > > + s->irq_mask =3D REG_SD_IMKR_RST; > > + s->irq_status =3D REG_SD_RISR_RST; > > + s->status =3D REG_SD_STAR_RST; > > + > > + s->fifo_wlevel =3D REG_SD_FWLR_RST; > > + s->fifo_func_sel =3D REG_SD_FUNS_RST; > > + s->debug_enable =3D REG_SD_DBGC_RST; > > + s->auto12_arg =3D REG_SD_A12A_RST; > > + s->newtiming_set =3D REG_SD_NTSR_RST; > > + s->newtiming_debug =3D REG_SD_SDBG_RST; > > + s->hardware_rst =3D REG_SD_HWRST_RST; > > + s->dmac =3D REG_SD_DMAC_RST; > > + s->desc_base =3D REG_SD_DLBA_RST; > > + s->dmac_status =3D REG_SD_IDST_RST; > > + s->dmac_irq =3D REG_SD_IDIE_RST; > > + s->card_threshold =3D REG_SD_THLDC_RST; > > + s->startbit_detect =3D REG_SD_DSBD_RST; > > + s->response_crc =3D REG_SD_RES_CRC_RST; > > + > > + for (int i =3D 0; i < sizeof(s->data_crc) / > > sizeof(s->data_crc[0]); i++) { > > ARRAY_SIZE > > > + s->data_crc[i] =3D REG_SD_DATA_CRC_RST; > > + } > > + > > + s->status_crc =3D REG_SD_CRC_STA_RST; > > +} > > + > > +static void aw_h3_sdhost_bus_class_init(ObjectClass *klass, void > *data) > > +{ > > + SDBusClass *sbc =3D SD_BUS_CLASS(klass); > > + > > + sbc->set_inserted =3D aw_h3_sdhost_set_inserted; > > +} > > + > > +static void aw_h3_sdhost_class_init(ObjectClass *klass, void *data= ) > > +{ > > + DeviceClass *dc =3D DEVICE_CLASS(klass); > > + > > + dc->reset =3D aw_h3_sdhost_reset; > > + dc->vmsd =3D &vmstate_aw_h3_sdhost; > > +} > > + > > +static TypeInfo aw_h3_sdhost_info =3D { > > + .name =3D TYPE_AW_H3_SDHOST, > > + .parent =3D TYPE_SYS_BUS_DEVICE, > > + .instance_size =3D sizeof(AwH3SDHostState), > > + .class_init =3D aw_h3_sdhost_class_init, > > + .instance_init =3D aw_h3_sdhost_init, > > +}; > > + > > +static const TypeInfo aw_h3_sdhost_bus_info =3D { > > + .name =3D TYPE_AW_H3_SDHOST_BUS, > > + .parent =3D TYPE_SD_BUS, > > + .instance_size =3D sizeof(SDBus), > > + .class_init =3D aw_h3_sdhost_bus_class_init, > > +}; > > + > > +static void aw_h3_sdhost_register_types(void) > > +{ > > + type_register_static(&aw_h3_sdhost_info); > > + type_register_static(&aw_h3_sdhost_bus_info); > > +} > > + > > +type_init(aw_h3_sdhost_register_types) > > diff --git a/hw/sd/trace-events b/hw/sd/trace-events > > index efcff666a2..c672a201b5 100644 > > --- a/hw/sd/trace-events > > +++ b/hw/sd/trace-events > > @@ -1,5 +1,12 @@ > > # See docs/devel/tracing.txt for syntax documentation. > > > > +# allwinner-h3-sdhost.c > > +aw_h3_sdhost_set_inserted(bool inserted) "inserted %u" > > +aw_h3_sdhost_process_desc(uint64_t desc_addr, uint32_t desc_size, > > bool is_write, uint32_t max_bytes) "desc_addr 0x%" PRIx64 " > > desc_size %u is_write %u max_bytes %u" > > Please also use PRIu32 for desc_size/max_bytes. > > > +aw_h3_sdhost_read(uint64_t offset, uint64_t data, unsigned size) > > "offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u" > > +aw_h3_sdhost_write(uint64_t offset, uint64_t data, unsigned size) > > "offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u" > > +aw_h3_sdhost_update_irq(uint32_t irq) "IRQ bits 0x%x" > > PRIx32 > > > + > > # bcm2835_sdhost.c > > bcm2835_sdhost_read(uint64_t offset, uint64_t data, unsigned size= ) > > "offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u" > > bcm2835_sdhost_write(uint64_t offset, uint64_t data, unsigned > > size) "offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u" > > diff --git a/include/hw/arm/allwinner-h3.h > > b/include/hw/arm/allwinner-h3.h > > index 33602599eb..7aff4ebbd2 100644 > > --- a/include/hw/arm/allwinner-h3.h > > +++ b/include/hw/arm/allwinner-h3.h > > @@ -30,6 +30,7 @@ > > #include "hw/misc/allwinner-h3-cpucfg.h" > > #include "hw/misc/allwinner-h3-syscon.h" > > #include "hw/misc/allwinner-h3-sid.h" > > +#include "hw/sd/allwinner-h3-sdhost.h" > > #include "target/arm/cpu.h" > > > > #define AW_H3_SRAM_A1_BASE (0x00000000) > > @@ -117,6 +118,7 @@ typedef struct AwH3State { > > AwH3CpuCfgState cpucfg; > > AwH3SysconState syscon; > > AwH3SidState sid; > > + AwH3SDHostState mmc0; > > GICState gic; > > MemoryRegion sram_a1; > > MemoryRegion sram_a2; > > diff --git a/include/hw/sd/allwinner-h3-sdhost.h > > b/include/hw/sd/allwinner-h3-sdhost.h > > new file mode 100644 > > index 0000000000..6c898a3c84 > > --- /dev/null > > +++ b/include/hw/sd/allwinner-h3-sdhost.h > > @@ -0,0 +1,73 @@ > > +/* > > + * Allwinner H3 SD Host Controller emulation > > + * > > + * Copyright (C) 2019 Niek Linnenbank > > > > + * > > + * This program is free software: you can redistribute it and/or > modify > > + * it under the terms of the GNU General Public License as > published by > > + * the Free Software Foundation, either version 2 of the License, = or > > + * (at your option) any later version. > > + * > > + * This program is distributed in the hope that it will be useful, > > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > > + * GNU General Public License for more details. > > + * > > + * You should have received a copy of the GNU General Public Licen= se > > + * along with this program. If not, see > > . > > + */ > > + > > +#ifndef ALLWINNER_H3_SDHOST_H > > +#define ALLWINNER_H3_SDHOST_H > > + > > +#include "hw/sysbus.h" > > +#include "hw/sd/sd.h" > > + > > +#define AW_H3_SDHOST_REGS_MEM_SIZE (1024) > > Move this definition to the source file. > > > + > > +#define TYPE_AW_H3_SDHOST "allwinner-h3-sdhost" > > +#define AW_H3_SDHOST(obj) \ > > + OBJECT_CHECK(AwH3SDHostState, (obj), TYPE_AW_H3_SDHOST) > > + > > +typedef struct { > > + SysBusDevice busdev; > > + SDBus sdbus; > > + MemoryRegion iomem; > > + > > + uint32_t global_ctl; > > + uint32_t clock_ctl; > > + uint32_t timeout; > > + uint32_t bus_width; > > + uint32_t block_size; > > + uint32_t byte_count; > > + uint32_t transfer_cnt; > > + > > + uint32_t command; > > + uint32_t command_arg; > > + uint32_t response[4]; > > + > > + uint32_t irq_mask; > > + uint32_t irq_status; > > + uint32_t status; > > + > > + uint32_t fifo_wlevel; > > + uint32_t fifo_func_sel; > > + uint32_t debug_enable; > > + uint32_t auto12_arg; > > + uint32_t newtiming_set; > > + uint32_t newtiming_debug; > > + uint32_t hardware_rst; > > + uint32_t dmac; > > + uint32_t desc_base; > > + uint32_t dmac_status; > > + uint32_t dmac_irq; > > + uint32_t card_threshold; > > + uint32_t startbit_detect; > > + uint32_t response_crc; > > + uint32_t data_crc[8]; > > + uint32_t status_crc; > > + > > + qemu_irq irq; > > +} AwH3SDHostState; > > + > > +#endif > > -- > > 2.17.1 > > I haven't checked the datasheet for all the registers/bits. > Thanks again for all of your helpful comments Philippe! I've started to rework the patch. One question about adding tags in the commit message: should I already add 'Reviewed-by: ' when I re-send v2 of this patch? Or should that be added after you have seen the v2 changes? > > Patch very clean, chapeau! > Thank you :-) Regards, Niek > > Regards, > > Phil. > > --=20 Niek Linnenbank --00000000000048b6cc05999c2987 Content-Type: text/html; charset="UTF-8" Content-Transfer-Encoding: base64 PGRpdiBkaXI9Imx0ciI+PGRpdiBkaXI9Imx0ciI+PGJyPjwvZGl2Pjxicj48ZGl2IGNsYXNzPSJn bWFpbF9xdW90ZSI+PGRpdiBkaXI9Imx0ciIgY2xhc3M9ImdtYWlsX2F0dHIiPk9uIEZyaSwgRGVj IDEzLCAyMDE5IGF0IDEyOjU2IEFNIFBoaWxpcHBlIE1hdGhpZXUtRGF1ZMOpICZsdDs8YSBocmVm PSJtYWlsdG86cGhpbG1kQHJlZGhhdC5jb20iPnBoaWxtZEByZWRoYXQuY29tPC9hPiZndDsgd3Jv dGU6PGJyPjwvZGl2PjxibG9ja3F1b3RlIGNsYXNzPSJnbWFpbF9xdW90ZSIgc3R5bGU9Im1hcmdp bjowcHggMHB4IDBweCAwLjhleDtib3JkZXItbGVmdDoxcHggc29saWQgcmdiKDIwNCwyMDQsMjA0 KTtwYWRkaW5nLWxlZnQ6MWV4Ij5IaSBOaWVrLDxicj4NCjxicj4NCk9uIDEyLzExLzE5IDExOjM0 IFBNLCBOaWVrIExpbm5lbmJhbmsgd3JvdGU6PGJyPg0KJmd0OyBQaW5nITxicj4NCiZndDsgPGJy Pg0KJmd0OyBBbnlvbmUgd291bGQgbGlrZSB0byBjb21tZW50IG9uIHRoaXMgZHJpdmVyPzxicj4N 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qemu-arm@nongnu.org; Sat, 14 Dec 2019 05:46:23 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ig4wF-0002jN-Lu for qemu-arm@nongnu.org; Sat, 14 Dec 2019 05:46:21 -0500 Received: from mail.ilande.co.uk ([46.43.2.167]:48408 helo=mail.default.ilande.uk0.bigv.io) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1ig4wE-0001Sz-Tq; Sat, 14 Dec 2019 05:46:19 -0500 Received: from host86-191-82-191.range86-191.btcentralplus.com ([86.191.82.191] helo=[192.168.1.65]) by mail.default.ilande.uk0.bigv.io with esmtpsa (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.89) (envelope-from ) id 1ig4tx-0003f9-7q; Sat, 14 Dec 2019 10:43:57 +0000 To: bilalwasim676@gmail.com, qemu-devel@nongnu.org Cc: peter.maydell@linaro.org, philmd@redhat.com, jasowang@redhat.com, qemu-arm@nongnu.org References: <20191210140617.16656-1-bilalwasim676@gmail.com> From: Mark Cave-Ayland Autocrypt: addr=mark.cave-ayland@ilande.co.uk; keydata= mQENBFQJuzwBCADAYvxrwUh1p/PvUlNFwKosVtVHHplgWi5p29t58QlOUkceZG0DBYSNqk93 3JzBTbtd4JfFcSupo6MNNOrCzdCbCjZ64ik8ycaUOSzK2tKbeQLEXzXoaDL1Y7vuVO7nL9bG E5Ru3wkhCFc7SkoypIoAUqz8EtiB6T89/D9TDEyjdXUacc53R5gu8wEWiMg5MQQuGwzbQy9n PFI+mXC7AaEUqBVc2lBQVpAYXkN0EyqNNT12UfDLdxaxaFpUAE2pCa2LTyo5vn5hEW+i3VdN PkmjyPvL6DdY03fvC01PyY8zaw+UI94QqjlrDisHpUH40IUPpC/NB0LwzL2aQOMkzT2NABEB AAG0ME1hcmsgQ2F2ZS1BeWxhbmQgPG1hcmsuY2F2ZS1heWxhbmRAaWxhbmRlLmNvLnVrPokB OAQTAQIAIgUCVAm7PAIbAwYLCQgHAwIGFQgCCQoLBBYCAwECHgECF4AACgkQW8LFb64PMh9f NAgAuc3ObOEY8NbZko72AGrg2tWKdybcMVITxmcor4hb9155o/OWcA4IDbeATR6cfiDL/oxU mcmtXVgPqOwtW3NYAKr5g/FrZZ3uluQ2mtNYAyTFeALy8YF7N3yhs7LOcpbFP7tEbkSzoXNG z8iYMiYtKwttt40WaheWuRs0ZOLbs6yoczZBDhna3Nj0LA3GpeJKlaV03O4umjKJgACP1c/q T2Pkg+FCBHHFP454+waqojHp4OCBo6HyK+8I4wJRa9Z0EFqXIu8lTDYoggeX0Xd6bWeCFHK3 DhD0/Xi/kegSW33unsp8oVcM4kcFxTkpBgj39dB4KwAUznhTJR0zUHf63LkBDQRUCbs8AQgA y7kyevA4bpetM/EjtuqQX4U05MBhEz/2SFkX6IaGtTG2NNw5wbcAfhOIuNNBYbw6ExuaJ3um 2uLseHnudmvN4VSJ5Hfbd8rhqoMmmO71szgT/ZD9MEe2KHzBdmhmhxJdp+zQNivy215j6H27 14mbC2dia7ktwP1rxPIX1OOfQwPuqlkmYPuVwZP19S4EYnCELOrnJ0m56tZLn5Zj+1jZX9Co YbNLMa28qsktYJ4oU4jtn6V79H+/zpERZAHmH40IRXdR3hA+Ye7iC/ZpWzT2VSDlPbGY9Yja Sp7w2347L5G+LLbAfaVoejHlfy/msPeehUcuKjAdBLoEhSPYzzdvEQARAQABiQEfBBgBAgAJ BQJUCbs8AhsMAAoJEFvCxW+uDzIfabYIAJXmBepHJpvCPiMNEQJNJ2ZSzSjhic84LTMWMbJ+ opQgr5cb8SPQyyb508fc8b4uD8ejlF/cdbbBNktp3BXsHlO5BrmcABgxSP8HYYNsX0n9kERv NMToU0oiBuAaX7O/0K9+BW+3+PGMwiu5ml0cwDqljxfVN0dUBZnQ8kZpLsY+WDrIHmQWjtH+ Ir6VauZs5Gp25XLrL6bh/SL8aK0BX6y79m5nhfKI1/6qtzHAjtMAjqy8ChPvOqVVVqmGUzFg KPsrrIoklWcYHXPyMLj9afispPVR8e0tMKvxzFBWzrWX1mzljbBlnV2n8BIwVXWNbgwpHSsj imgcU9TTGC5qd9g= Message-ID: <21af53f8-a057-b9d4-c6ff-29c3f1df5d69@ilande.co.uk> Date: Sat, 14 Dec 2019 10:43:01 +0000 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.2.2 MIME-Version: 1.0 In-Reply-To: <20191210140617.16656-1-bilalwasim676@gmail.com> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 8bit X-SA-Exim-Connect-IP: 86.191.82.191 X-SA-Exim-Mail-From: mark.cave-ayland@ilande.co.uk Subject: Re: [PATCH v3] net/imx_fec: Adding support for MAC filtering in the FEC IP implementation. X-SA-Exim-Version: 4.2.1 (built Tue, 02 Aug 2016 21:08:31 +0000) X-SA-Exim-Scanned: Yes (on mail.default.ilande.uk0.bigv.io) X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 46.43.2.167 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sat, 14 Dec 2019 10:46:23 -0000 On 10/12/2019 14:06, bilalwasim676@gmail.com wrote: > From: bwasim > > This addition ensures that the IP does NOT boot up in promiscuous mode > by default, and so the software only receives the desired > packets(Unicast, Broadcast, Unicast / Multicast hashed) by default. > The software running on-top of QEMU can also modify these settings and > disable reception of broadcast frames or make the IP receive all packets (PROM mode). > This patch greatly reduces the number of packets received by the > software running on-top of the QEMU model. Tested with the armv7-a SABRE_LITE machine. > Testing included running a custom OS with IPv4 / IPv6 support. Hashing > and filtering of packets is tested to work well. Skeleton taken from > the CADENCE_GEM IP and hash generation algorithm from the Linux Kernel. > > Signed-off-by: Bilal Wasim > --- > hw/net/imx_fec.c | 109 ++++++++++++++++++++++++++++++++++++++- > include/hw/net/imx_fec.h | 10 ++++ > 2 files changed, 118 insertions(+), 1 deletion(-) > > diff --git a/hw/net/imx_fec.c b/hw/net/imx_fec.c > index bd99236864..d248f39fb0 100644 > --- a/hw/net/imx_fec.c > +++ b/hw/net/imx_fec.c > @@ -419,6 +419,79 @@ static void imx_enet_write_bd(IMXENETBufDesc *bd, dma_addr_t addr) > dma_memory_write(&address_space_memory, addr, bd, sizeof(*bd)); > } > > +/* > + * Calculate a FEC MAC Address hash index > + */ > +static unsigned calc_mac_hash(const uint8_t *mac, uint8_t mac_length) > +{ > + uint32_t crc = net_crc32_le(mac, mac_length); > + > + /* > + * only upper 6 bits (FEC_HASH_BITS) are used > + * which point to specific bit in the hash registers > + */ > + return (crc >> (32 - FEC_HASH_BITS)) & 0x3f; > +} Is it worth keeping this in a separate function? This appears to be a standard hash calculation and most other cards simply inline it like below: > +/* > + * fec_mac_address_filter: > + * Accept or reject this destination address? > + */ > +static int fec_mac_address_filter(IMXFECState *s, const uint8_t *packet) > +{ > + const uint8_t broadcast_addr[] = { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }; > + uint32_t addr1, addr2; > + uint8_t hash; > + > + /* Promiscuous mode? */ > + if (s->regs[ENET_RCR] & ENET_RCR_PROM) { > + /* Accept all packets in promiscuous mode (even if bc_rej is set). */ > + return FEC_RX_PROMISCUOUS_ACCEPT; > + } > + > + /* Broadcast packet? */ > + if (!memcmp(packet, broadcast_addr, 6)) { ETH_ALEN? > + /* Reject broadcast packets? */ > + if (s->regs[ENET_RCR] & ENET_RCR_BC_REJ) { > + return FEC_RX_REJECT; > + } > + /* Accept packets from broadcast address. */ > + return FEC_RX_BROADCAST_ACCEPT; > + } > + > + /* Accept packets -w- hash match? */ > + hash = calc_mac_hash(packet, 6); hash = net_crc32_le(buf, ETH_ALEN) >> 26 > + /* Accept packets -w- multicast hash match? */ > + if ((packet[0] & 0x01) == 0x01) { > + /* Computed hash matches GAUR / GALR register ? */ > + if (((hash < 32) && (s->regs[ENET_GALR] & (1 << hash))) > + || ((hash > 31) && (s->regs[ENET_GAUR] & (1 << (hash - 32))))) { > + /* Accept multicast hash enabled address. */ > + return FEC_RX_MULTICAST_HASH_ACCEPT; > + } > + } else { > + /* Computed hash matches IAUR / IALR register ? */ > + if (((hash < 32) && (s->regs[ENET_IALR] & (1 << hash))) > + || ((hash > 31) && (s->regs[ENET_IAUR] & (1 << (hash - 32))))) { > + /* Accept multicast hash enabled address. */ > + return FEC_RX_UNICAST_HASH_ACCEPT; > + } > + } > + > + /* Match Unicast address. */ > + addr1 = g_htonl(s->regs[ENET_PALR]); > + addr2 = g_htonl(s->regs[ENET_PAUR]); > + if (!(memcmp(packet, (uint8_t *) &addr1, 4) || > + memcmp(packet + 4, (uint8_t *) &addr2, 2))) { > + /* Accept packet because it matches my unicast address. */ > + return FEC_RX_UNICAST_ACCEPT; > + } > + > + /* Return -1 because we do NOT support MAC address filtering.. */ > + return FEC_RX_REJECT; > +} > + > static void imx_eth_update(IMXFECState *s) > { > /* > @@ -984,7 +1057,7 @@ static void imx_eth_write(void *opaque, hwaddr offset, uint64_t value, > case ENET_IALR: > case ENET_GAUR: > case ENET_GALR: > - /* TODO: implement MAC hash filtering. */ > + s->regs[index] |= value; > break; > case ENET_TFWR: > if (s->is_fec) { > @@ -1066,8 +1139,15 @@ static ssize_t imx_fec_receive(NetClientState *nc, const uint8_t *buf, > uint32_t buf_addr; > uint8_t *crc_ptr; > unsigned int buf_len; > + int maf; > size_t size = len; > > + /* Is this destination MAC address "for us" ? */ > + maf = fec_mac_address_filter(s, buf); > + if (maf == FEC_RX_REJECT) { > + return FEC_RX_REJECT; > + } > + > FEC_PRINTF("len %d\n", (int)size); > > if (!s->regs[ENET_RDAR]) { > @@ -1133,6 +1213,16 @@ static ssize_t imx_fec_receive(NetClientState *nc, const uint8_t *buf, > } else { > s->regs[ENET_EIR] |= ENET_INT_RXB; > } > + > + /* Update descriptor based on the "maf" flag. */ > + if (maf == FEC_RX_BROADCAST_ACCEPT) { > + /* The packet is destined for the "broadcast" address. */ > + bd.flags |= ENET_BD_BC; > + } else if (maf == FEC_RX_MULTICAST_HASH_ACCEPT) { > + /* The packet is destined for a "multicast" address. */ > + bd.flags |= ENET_BD_MC; > + } > + > imx_fec_write_bd(&bd, addr); > /* Advance to the next descriptor. */ > if ((bd.flags & ENET_BD_W) != 0) { > @@ -1159,8 +1249,15 @@ static ssize_t imx_enet_receive(NetClientState *nc, const uint8_t *buf, > uint8_t *crc_ptr; > unsigned int buf_len; > size_t size = len; > + int maf; > bool shift16 = s->regs[ENET_RACC] & ENET_RACC_SHIFT16; > > + /* Is this destination MAC address "for us" ? */ > + maf = fec_mac_address_filter(s, buf); > + if (maf == FEC_RX_REJECT) { > + return FEC_RX_REJECT; > + } > + > FEC_PRINTF("len %d\n", (int)size); > > if (!s->regs[ENET_RDAR]) { > @@ -1254,6 +1351,16 @@ static ssize_t imx_enet_receive(NetClientState *nc, const uint8_t *buf, > s->regs[ENET_EIR] |= ENET_INT_RXB; > } > } > + > + /* Update descriptor based on the "maf" flag. */ > + if (maf == FEC_RX_BROADCAST_ACCEPT) { > + /* The packet is destined for the "broadcast" address. */ > + bd.flags |= ENET_BD_BC; > + } else if (maf == FEC_RX_MULTICAST_HASH_ACCEPT) { > + /* The packet is destined for a "multicast" address. */ > + bd.flags |= ENET_BD_MC; > + } > + > imx_enet_write_bd(&bd, addr); > /* Advance to the next descriptor. */ > if ((bd.flags & ENET_BD_W) != 0) { > diff --git a/include/hw/net/imx_fec.h b/include/hw/net/imx_fec.h > index 7b3faa4019..f9cfcf6af5 100644 > --- a/include/hw/net/imx_fec.h > +++ b/include/hw/net/imx_fec.h > @@ -275,4 +275,14 @@ typedef struct IMXFECState { > uint8_t frame[ENET_MAX_FRAME_SIZE]; > } IMXFECState; > > +/* FEC address filtering defines. */ > +#define FEC_RX_REJECT (-1) > +#define FEC_RX_PROMISCUOUS_ACCEPT (-2) > +#define FEC_RX_BROADCAST_ACCEPT (-3) > +#define FEC_RX_MULTICAST_HASH_ACCEPT (-4) > +#define FEC_RX_UNICAST_HASH_ACCEPT (-5) > +#define FEC_RX_UNICAST_ACCEPT (-6) > + > +#define FEC_HASH_BITS 6 /* #bits in hash */ If you inline the hash calculation as above then this line is no longer required. > #endif I've done some bits on QEMU networking however I'm not familiar with this particular device which limits me somewhat for further review. ATB, Mark. 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Fri, 13 Dec 2019 21:44:19 -0500 (EST) From: Alistair Francis To: qemu-devel@nongnu.org, peter.maydell@linaro.org Cc: qemu-arm@nongnu.org, alistair23@gmail.com Subject: [PATCH v6 1/4] hw/misc: Add the STM32F4xx Sysconfig device Date: Fri, 13 Dec 2019 18:44:18 -0800 Message-Id: <36b89b7805c66cd115925cc738e6e0594b3241ec.1576227325.git.alistair@alistair23.me> X-Mailer: git-send-email 2.24.0 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 66.111.4.29 X-Mailman-Approved-At: Sat, 14 Dec 2019 08:40:59 -0500 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sat, 14 Dec 2019 02:44:25 -0000 Signed-off-by: Alistair Francis Reviewed-by: Peter Maydell --- default-configs/arm-softmmu.mak | 1 + hw/arm/Kconfig | 9 ++ hw/misc/Kconfig | 3 + hw/misc/Makefile.objs | 1 + hw/misc/stm32f4xx_syscfg.c | 171 +++++++++++++++++++++++++++++ hw/misc/trace-events | 6 + include/hw/misc/stm32f4xx_syscfg.h | 61 ++++++++++ 7 files changed, 252 insertions(+) create mode 100644 hw/misc/stm32f4xx_syscfg.c create mode 100644 include/hw/misc/stm32f4xx_syscfg.h diff --git a/default-configs/arm-softmmu.mak b/default-configs/arm-softmmu.mak index 1f2e0e7fde..645e6201bb 100644 --- a/default-configs/arm-softmmu.mak +++ b/default-configs/arm-softmmu.mak @@ -30,6 +30,7 @@ CONFIG_Z2=y CONFIG_COLLIE=y CONFIG_ASPEED_SOC=y CONFIG_NETDUINO2=y +CONFIG_NETDUINOPLUS2=y CONFIG_MPS2=y CONFIG_RASPI=y CONFIG_DIGIC=y diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig index c6e7782580..4660d14715 100644 --- a/hw/arm/Kconfig +++ b/hw/arm/Kconfig @@ -101,6 +101,10 @@ config NETDUINO2 bool select STM32F205_SOC +config NETDUINOPLUS2 + bool + select STM32F405_SOC + config NSERIES bool select OMAP @@ -307,6 +311,11 @@ config STM32F205_SOC select STM32F2XX_ADC select STM32F2XX_SPI +config STM32F405_SOC + bool + select ARM_V7M + select STM32F4XX_SYSCFG + config XLNX_ZYNQMP_ARM bool select AHCI diff --git a/hw/misc/Kconfig b/hw/misc/Kconfig index 2164646553..72609650b7 100644 --- a/hw/misc/Kconfig +++ b/hw/misc/Kconfig @@ -82,6 +82,9 @@ config IMX config STM32F2XX_SYSCFG bool +config STM32F4XX_SYSCFG + bool + config MIPS_ITU bool diff --git a/hw/misc/Makefile.objs b/hw/misc/Makefile.objs index ba898a5781..ea8025e0bb 100644 --- a/hw/misc/Makefile.objs +++ b/hw/misc/Makefile.objs @@ -58,6 +58,7 @@ common-obj-$(CONFIG_SLAVIO) += slavio_misc.o common-obj-$(CONFIG_ZYNQ) += zynq_slcr.o common-obj-$(CONFIG_ZYNQ) += zynq-xadc.o common-obj-$(CONFIG_STM32F2XX_SYSCFG) += stm32f2xx_syscfg.o +common-obj-$(CONFIG_STM32F4XX_SYSCFG) += stm32f4xx_syscfg.o obj-$(CONFIG_MIPS_CPS) += mips_cmgcr.o obj-$(CONFIG_MIPS_CPS) += mips_cpc.o obj-$(CONFIG_MIPS_ITU) += mips_itu.o diff --git a/hw/misc/stm32f4xx_syscfg.c b/hw/misc/stm32f4xx_syscfg.c new file mode 100644 index 0000000000..dbcdca59f8 --- /dev/null +++ b/hw/misc/stm32f4xx_syscfg.c @@ -0,0 +1,171 @@ +/* + * STM32F4xx SYSCFG + * + * Copyright (c) 2014 Alistair Francis + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#include "qemu/osdep.h" +#include "qemu/log.h" +#include "trace.h" +#include "hw/irq.h" +#include "migration/vmstate.h" +#include "hw/misc/stm32f4xx_syscfg.h" + +static void stm32f4xx_syscfg_reset(DeviceState *dev) +{ + STM32F4xxSyscfgState *s = STM32F4XX_SYSCFG(dev); + + s->syscfg_memrmp = 0x00000000; + s->syscfg_pmc = 0x00000000; + s->syscfg_exticr[0] = 0x00000000; + s->syscfg_exticr[1] = 0x00000000; + s->syscfg_exticr[2] = 0x00000000; + s->syscfg_exticr[3] = 0x00000000; + s->syscfg_cmpcr = 0x00000000; +} + +static void stm32f4xx_syscfg_set_irq(void *opaque, int irq, int level) +{ + STM32F4xxSyscfgState *s = opaque; + int icrreg = irq / 4; + int startbit = (irq & 3) * 4; + uint8_t config = config = irq / 16; + + trace_stm32f4xx_syscfg_set_irq(irq / 16, irq % 16, level); + + g_assert(icrreg < SYSCFG_NUM_EXTICR); + + if (extract32(s->syscfg_exticr[icrreg], startbit, 4) == config) { + qemu_set_irq(s->gpio_out[irq], level); + trace_stm32f4xx_pulse_exti(irq); + } +} + +static uint64_t stm32f4xx_syscfg_read(void *opaque, hwaddr addr, + unsigned int size) +{ + STM32F4xxSyscfgState *s = opaque; + + trace_stm32f4xx_syscfg_read(addr); + + switch (addr) { + case SYSCFG_MEMRMP: + return s->syscfg_memrmp; + case SYSCFG_PMC: + return s->syscfg_pmc; + case SYSCFG_EXTICR1...SYSCFG_EXTICR4: + return s->syscfg_exticr[addr / 4 - SYSCFG_EXTICR1 / 4]; + case SYSCFG_CMPCR: + return s->syscfg_cmpcr; + default: + qemu_log_mask(LOG_GUEST_ERROR, + "%s: Bad offset 0x%"HWADDR_PRIx"\n", __func__, addr); + return 0; + } +} + +static void stm32f4xx_syscfg_write(void *opaque, hwaddr addr, + uint64_t val64, unsigned int size) +{ + STM32F4xxSyscfgState *s = opaque; + uint32_t value = val64; + + trace_stm32f4xx_syscfg_write(value, addr); + + switch (addr) { + case SYSCFG_MEMRMP: + qemu_log_mask(LOG_UNIMP, + "%s: Changing the memory mapping isn't supported " \ + "in QEMU\n", __func__); + return; + case SYSCFG_PMC: + qemu_log_mask(LOG_UNIMP, + "%s: Changing the memory mapping isn't supported " \ + "in QEMU\n", __func__); + return; + case SYSCFG_EXTICR1...SYSCFG_EXTICR4: + s->syscfg_exticr[addr / 4 - SYSCFG_EXTICR1 / 4] = (value & 0xFFFF); + return; + case SYSCFG_CMPCR: + s->syscfg_cmpcr = value; + return; + default: + qemu_log_mask(LOG_GUEST_ERROR, + "%s: Bad offset 0x%"HWADDR_PRIx"\n", __func__, addr); + } +} + +static const MemoryRegionOps stm32f4xx_syscfg_ops = { + .read = stm32f4xx_syscfg_read, + .write = stm32f4xx_syscfg_write, + .endianness = DEVICE_NATIVE_ENDIAN, +}; + +static void stm32f4xx_syscfg_init(Object *obj) +{ + STM32F4xxSyscfgState *s = STM32F4XX_SYSCFG(obj); + + sysbus_init_irq(SYS_BUS_DEVICE(obj), &s->irq); + + memory_region_init_io(&s->mmio, obj, &stm32f4xx_syscfg_ops, s, + TYPE_STM32F4XX_SYSCFG, 0x400); + sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->mmio); + + qdev_init_gpio_in(DEVICE(obj), stm32f4xx_syscfg_set_irq, 16 * 9); + qdev_init_gpio_out(DEVICE(obj), s->gpio_out, 16); +} + +static const VMStateDescription vmstate_stm32f4xx_syscfg = { + .name = TYPE_STM32F4XX_SYSCFG, + .version_id = 1, + .minimum_version_id = 1, + .fields = (VMStateField[]) { + VMSTATE_UINT32(syscfg_memrmp, STM32F4xxSyscfgState), + VMSTATE_UINT32(syscfg_pmc, STM32F4xxSyscfgState), + VMSTATE_UINT32_ARRAY(syscfg_exticr, STM32F4xxSyscfgState, + SYSCFG_NUM_EXTICR), + VMSTATE_UINT32(syscfg_cmpcr, STM32F4xxSyscfgState), + VMSTATE_END_OF_LIST() + } +}; + +static void stm32f4xx_syscfg_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + + dc->reset = stm32f4xx_syscfg_reset; + dc->vmsd = &vmstate_stm32f4xx_syscfg; +} + +static const TypeInfo stm32f4xx_syscfg_info = { + .name = TYPE_STM32F4XX_SYSCFG, + .parent = TYPE_SYS_BUS_DEVICE, + .instance_size = sizeof(STM32F4xxSyscfgState), + .instance_init = stm32f4xx_syscfg_init, + .class_init = stm32f4xx_syscfg_class_init, +}; + +static void stm32f4xx_syscfg_register_types(void) +{ + type_register_static(&stm32f4xx_syscfg_info); +} + +type_init(stm32f4xx_syscfg_register_types) diff --git a/hw/misc/trace-events b/hw/misc/trace-events index 1deb1d08c1..02327562bc 100644 --- a/hw/misc/trace-events +++ b/hw/misc/trace-events @@ -84,6 +84,12 @@ mos6522_set_sr_int(void) "set sr_int" mos6522_write(uint64_t addr, uint64_t val) "reg=0x%"PRIx64 " val=0x%"PRIx64 mos6522_read(uint64_t addr, unsigned val) "reg=0x%"PRIx64 " val=0x%x" +# stm32f4xx_syscfg +stm32f4xx_syscfg_set_irq(int gpio, int line, int level) "Interupt: GPIO: %d, Line: %d; Level: %d" +stm32f4xx_pulse_exti(int irq) "Pulse EXTI: %d" +stm32f4xx_syscfg_read(uint64_t addr) "reg read: addr: 0x%" PRIx64 " " +stm32f4xx_syscfg_write(uint64_t addr, uint64_t data) "reg write: addr: 0x%" PRIx64 " val: 0x%" PRIx64 "" + # tz-mpc.c tz_mpc_reg_read(uint32_t offset, uint64_t data, unsigned size) "TZ MPC regs read: offset 0x%x data 0x%" PRIx64 " size %u" tz_mpc_reg_write(uint32_t offset, uint64_t data, unsigned size) "TZ MPC regs write: offset 0x%x data 0x%" PRIx64 " size %u" diff --git a/include/hw/misc/stm32f4xx_syscfg.h b/include/hw/misc/stm32f4xx_syscfg.h new file mode 100644 index 0000000000..c62c6629e5 --- /dev/null +++ b/include/hw/misc/stm32f4xx_syscfg.h @@ -0,0 +1,61 @@ +/* + * STM32F4xx SYSCFG + * + * Copyright (c) 2014 Alistair Francis + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#ifndef HW_STM_SYSCFG_H +#define HW_STM_SYSCFG_H + +#include "hw/sysbus.h" +#include "hw/hw.h" + +#define SYSCFG_MEMRMP 0x00 +#define SYSCFG_PMC 0x04 +#define SYSCFG_EXTICR1 0x08 +#define SYSCFG_EXTICR2 0x0C +#define SYSCFG_EXTICR3 0x10 +#define SYSCFG_EXTICR4 0x14 +#define SYSCFG_CMPCR 0x20 + +#define TYPE_STM32F4XX_SYSCFG "stm32f4xx-syscfg" +#define STM32F4XX_SYSCFG(obj) \ + OBJECT_CHECK(STM32F4xxSyscfgState, (obj), TYPE_STM32F4XX_SYSCFG) + +#define SYSCFG_NUM_EXTICR 4 + +typedef struct { + /* */ + SysBusDevice parent_obj; + + /* */ + MemoryRegion mmio; + + uint32_t syscfg_memrmp; + uint32_t syscfg_pmc; + uint32_t syscfg_exticr[SYSCFG_NUM_EXTICR]; + uint32_t syscfg_cmpcr; + + qemu_irq irq; + qemu_irq gpio_out[16]; +} STM32F4xxSyscfgState; + +#endif -- 2.24.0 From MAILER-DAEMON Sat Dec 14 08:41:00 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1ig7fI-0007Jq-GR for mharc-qemu-arm@gnu.org; Sat, 14 Dec 2019 08:41:00 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:56822) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ifxPv-0004EC-89 for qemu-arm@nongnu.org; Fri, 13 Dec 2019 21:44:29 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ifxPs-0000jd-N1 for qemu-arm@nongnu.org; Fri, 13 Dec 2019 21:44:27 -0500 Received: from out5-smtp.messagingengine.com ([66.111.4.29]:37313) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1ifxPs-0000iC-BU; Fri, 13 Dec 2019 21:44:24 -0500 Received: from compute7.internal (compute7.nyi.internal [10.202.2.47]) by mailout.nyi.internal (Postfix) with ESMTP id 0A75922452; Fri, 13 Dec 2019 21:44:24 -0500 (EST) Received: from mailfrontend1 ([10.202.2.162]) by compute7.internal (MEProxy); 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Fri, 13 Dec 2019 21:44:23 -0500 (EST) From: Alistair Francis To: qemu-devel@nongnu.org, peter.maydell@linaro.org Cc: qemu-arm@nongnu.org, alistair23@gmail.com Subject: [PATCH v6 2/4] hw/misc: Add the STM32F4xx EXTI device Date: Fri, 13 Dec 2019 18:44:22 -0800 Message-Id: <717e76b6d41e09c352d98a83708c3e3c9fe5d63b.1576227325.git.alistair@alistair23.me> X-Mailer: git-send-email 2.24.0 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 66.111.4.29 X-Mailman-Approved-At: Sat, 14 Dec 2019 08:40:59 -0500 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sat, 14 Dec 2019 02:44:29 -0000 Signed-off-by: Alistair Francis Reviewed-by: Peter Maydell --- hw/arm/Kconfig | 1 + hw/misc/Kconfig | 3 + hw/misc/Makefile.objs | 1 + hw/misc/stm32f4xx_exti.c | 189 +++++++++++++++++++++++++++++++ hw/misc/trace-events | 5 + include/hw/misc/stm32f4xx_exti.h | 60 ++++++++++ 6 files changed, 259 insertions(+) create mode 100644 hw/misc/stm32f4xx_exti.c create mode 100644 include/hw/misc/stm32f4xx_exti.h diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig index 4660d14715..3d86691ae0 100644 --- a/hw/arm/Kconfig +++ b/hw/arm/Kconfig @@ -315,6 +315,7 @@ config STM32F405_SOC bool select ARM_V7M select STM32F4XX_SYSCFG + select STM32F4XX_EXTI config XLNX_ZYNQMP_ARM bool diff --git a/hw/misc/Kconfig b/hw/misc/Kconfig index 72609650b7..bdd77d8020 100644 --- a/hw/misc/Kconfig +++ b/hw/misc/Kconfig @@ -85,6 +85,9 @@ config STM32F2XX_SYSCFG config STM32F4XX_SYSCFG bool +config STM32F4XX_EXTI + bool + config MIPS_ITU bool diff --git a/hw/misc/Makefile.objs b/hw/misc/Makefile.objs index ea8025e0bb..c6ecbdd7b0 100644 --- a/hw/misc/Makefile.objs +++ b/hw/misc/Makefile.objs @@ -59,6 +59,7 @@ common-obj-$(CONFIG_ZYNQ) += zynq_slcr.o common-obj-$(CONFIG_ZYNQ) += zynq-xadc.o common-obj-$(CONFIG_STM32F2XX_SYSCFG) += stm32f2xx_syscfg.o common-obj-$(CONFIG_STM32F4XX_SYSCFG) += stm32f4xx_syscfg.o +common-obj-$(CONFIG_STM32F4XX_EXTI) += stm32f4xx_exti.o obj-$(CONFIG_MIPS_CPS) += mips_cmgcr.o obj-$(CONFIG_MIPS_CPS) += mips_cpc.o obj-$(CONFIG_MIPS_ITU) += mips_itu.o diff --git a/hw/misc/stm32f4xx_exti.c b/hw/misc/stm32f4xx_exti.c new file mode 100644 index 0000000000..7f87a885aa --- /dev/null +++ b/hw/misc/stm32f4xx_exti.c @@ -0,0 +1,189 @@ +/* + * STM32F4XX EXTI + * + * Copyright (c) 2014 Alistair Francis + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#include "qemu/osdep.h" +#include "qemu/log.h" +#include "trace.h" +#include "hw/irq.h" +#include "migration/vmstate.h" +#include "hw/misc/stm32f4xx_exti.h" + +static void stm32f4xx_exti_reset(DeviceState *dev) +{ + STM32F4xxExtiState *s = STM32F4XX_EXTI(dev); + + s->exti_imr = 0x00000000; + s->exti_emr = 0x00000000; + s->exti_rtsr = 0x00000000; + s->exti_ftsr = 0x00000000; + s->exti_swier = 0x00000000; + s->exti_pr = 0x00000000; +} + +static void stm32f4xx_exti_set_irq(void *opaque, int irq, int level) +{ + STM32F4xxExtiState *s = opaque; + + if (!((1 << irq) & s->exti_imr)) { + /* Interrupt is masked */ + return; + } + + trace_stm32f4xx_exti_set_irq(irq, level); + + if (((1 << irq) & s->exti_rtsr) && level) { + /* Rising Edge */ + qemu_irq_pulse(s->irq[irq]); + s->exti_pr |= 1 << irq; + } + + if (((1 << irq) & s->exti_ftsr) && !level) { + /* Falling Edge */ + qemu_irq_pulse(s->irq[irq]); + s->exti_pr |= 1 << irq; + } +} + +static uint64_t stm32f4xx_exti_read(void *opaque, hwaddr addr, + unsigned int size) +{ + STM32F4xxExtiState *s = opaque; + + trace_stm32f4xx_exti_read(addr); + + switch (addr) { + case EXTI_IMR: + return s->exti_imr; + case EXTI_EMR: + return s->exti_emr; + case EXTI_RTSR: + return s->exti_rtsr; + case EXTI_FTSR: + return s->exti_ftsr; + case EXTI_SWIER: + return s->exti_swier; + case EXTI_PR: + return s->exti_pr; + default: + qemu_log_mask(LOG_GUEST_ERROR, + "STM32F4XX_exti_read: Bad offset %x\n", (int)addr); + return 0; + } + return 0; +} + +static void stm32f4xx_exti_write(void *opaque, hwaddr addr, + uint64_t val64, unsigned int size) +{ + STM32F4xxExtiState *s = opaque; + uint32_t value = (uint32_t) val64; + + trace_stm32f4xx_exti_write(addr, value); + + switch (addr) { + case EXTI_IMR: + s->exti_imr = value; + return; + case EXTI_EMR: + s->exti_emr = value; + return; + case EXTI_RTSR: + s->exti_rtsr = value; + return; + case EXTI_FTSR: + s->exti_ftsr = value; + return; + case EXTI_SWIER: + s->exti_swier = value; + return; + case EXTI_PR: + /* This bit is cleared by writing a 1 to it */ + s->exti_pr &= ~value; + return; + default: + qemu_log_mask(LOG_GUEST_ERROR, + "STM32F4XX_exti_write: Bad offset %x\n", (int)addr); + } +} + +static const MemoryRegionOps stm32f4xx_exti_ops = { + .read = stm32f4xx_exti_read, + .write = stm32f4xx_exti_write, + .endianness = DEVICE_NATIVE_ENDIAN, +}; + +static void stm32f4xx_exti_init(Object *obj) +{ + STM32F4xxExtiState *s = STM32F4XX_EXTI(obj); + int i; + + for (i = 0; i < NUM_INTERRUPT_OUT_LINES; i++) { + sysbus_init_irq(SYS_BUS_DEVICE(obj), &s->irq[i]); + } + + memory_region_init_io(&s->mmio, obj, &stm32f4xx_exti_ops, s, + TYPE_STM32F4XX_EXTI, 0x400); + sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->mmio); + + qdev_init_gpio_in(DEVICE(obj), stm32f4xx_exti_set_irq, + NUM_GPIO_EVENT_IN_LINES); +} + +static const VMStateDescription vmstate_stm32f4xx_exti = { + .name = TYPE_STM32F4XX_EXTI, + .version_id = 1, + .minimum_version_id = 1, + .fields = (VMStateField[]) { + VMSTATE_UINT32(exti_imr, STM32F4xxExtiState), + VMSTATE_UINT32(exti_emr, STM32F4xxExtiState), + VMSTATE_UINT32(exti_rtsr, STM32F4xxExtiState), + VMSTATE_UINT32(exti_ftsr, STM32F4xxExtiState), + VMSTATE_UINT32(exti_swier, STM32F4xxExtiState), + VMSTATE_UINT32(exti_pr, STM32F4xxExtiState), + VMSTATE_END_OF_LIST() + } +}; + +static void stm32f4xx_exti_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + + dc->reset = stm32f4xx_exti_reset; + dc->vmsd = &vmstate_stm32f4xx_exti; +} + +static const TypeInfo stm32f4xx_exti_info = { + .name = TYPE_STM32F4XX_EXTI, + .parent = TYPE_SYS_BUS_DEVICE, + .instance_size = sizeof(STM32F4xxExtiState), + .instance_init = stm32f4xx_exti_init, + .class_init = stm32f4xx_exti_class_init, +}; + +static void stm32f4xx_exti_register_types(void) +{ + type_register_static(&stm32f4xx_exti_info); +} + +type_init(stm32f4xx_exti_register_types) diff --git a/hw/misc/trace-events b/hw/misc/trace-events index 02327562bc..91a3794d68 100644 --- a/hw/misc/trace-events +++ b/hw/misc/trace-events @@ -90,6 +90,11 @@ stm32f4xx_pulse_exti(int irq) "Pulse EXTI: %d" stm32f4xx_syscfg_read(uint64_t addr) "reg read: addr: 0x%" PRIx64 " " stm32f4xx_syscfg_write(uint64_t addr, uint64_t data) "reg write: addr: 0x%" PRIx64 " val: 0x%" PRIx64 "" +# stm32f4xx_exti +stm32f4xx_exti_set_irq(int irq, int leve) "Set EXTI: %d to %d" +stm32f4xx_exti_read(uint64_t addr) "reg read: addr: 0x%" PRIx64 " " +stm32f4xx_exti_write(uint64_t addr, uint64_t data) "reg write: addr: 0x%" PRIx64 " val: 0x%" PRIx64 "" + # tz-mpc.c tz_mpc_reg_read(uint32_t offset, uint64_t data, unsigned size) "TZ MPC regs read: offset 0x%x data 0x%" PRIx64 " size %u" tz_mpc_reg_write(uint32_t offset, uint64_t data, unsigned size) "TZ MPC regs write: offset 0x%x data 0x%" PRIx64 " size %u" diff --git a/include/hw/misc/stm32f4xx_exti.h b/include/hw/misc/stm32f4xx_exti.h new file mode 100644 index 0000000000..707036a41b --- /dev/null +++ b/include/hw/misc/stm32f4xx_exti.h @@ -0,0 +1,60 @@ +/* + * STM32F4XX EXTI + * + * Copyright (c) 2014 Alistair Francis + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#ifndef HW_STM_EXTI_H +#define HW_STM_EXTI_H + +#include "hw/sysbus.h" +#include "hw/hw.h" + +#define EXTI_IMR 0x00 +#define EXTI_EMR 0x04 +#define EXTI_RTSR 0x08 +#define EXTI_FTSR 0x0C +#define EXTI_SWIER 0x10 +#define EXTI_PR 0x14 + +#define TYPE_STM32F4XX_EXTI "stm32f4xx-exti" +#define STM32F4XX_EXTI(obj) \ + OBJECT_CHECK(STM32F4xxExtiState, (obj), TYPE_STM32F4XX_EXTI) + +#define NUM_GPIO_EVENT_IN_LINES 16 +#define NUM_INTERRUPT_OUT_LINES 16 + +typedef struct { + SysBusDevice parent_obj; + + MemoryRegion mmio; + + uint32_t exti_imr; + uint32_t exti_emr; + uint32_t exti_rtsr; + uint32_t exti_ftsr; + uint32_t exti_swier; + uint32_t exti_pr; + + qemu_irq irq[NUM_INTERRUPT_OUT_LINES]; +} STM32F4xxExtiState; + +#endif -- 2.24.0 From MAILER-DAEMON Sat Dec 14 08:41:00 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1ig7fI-0007KB-Lm for mharc-qemu-arm@gnu.org; Sat, 14 Dec 2019 08:41:00 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:58879) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ifxQ3-0004PA-77 for qemu-arm@nongnu.org; Fri, 13 Dec 2019 21:44:36 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ifxQ0-00012W-MC for qemu-arm@nongnu.org; Fri, 13 Dec 2019 21:44:35 -0500 Received: from out5-smtp.messagingengine.com ([66.111.4.29]:57055) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1ifxQ0-000102-A5; Fri, 13 Dec 2019 21:44:32 -0500 Received: from compute7.internal (compute7.nyi.internal [10.202.2.47]) by mailout.nyi.internal (Postfix) with ESMTP id 831142244E; Fri, 13 Dec 2019 21:44:31 -0500 (EST) Received: from mailfrontend1 ([10.202.2.162]) by compute7.internal (MEProxy); Fri, 13 Dec 2019 21:44:31 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=alistair23.me; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; s=fm2; bh=kUtIe6kqnG2Fw dUxin7eUzLqjVTtszz1wUf2bM5zKlw=; b=IVi0DfxoEiA4oMjBgdafS+GpKn01a pmRKtf3FLwliDIvpJbhmHVAMv0N8sfhHOOOFffarxyZSGWT+BZM1i53ZmGOWpXJW dLonJMGCZEeDyHT1NZdk5YzNFGmQp7jySBWI5raMXFQxrsskp1bZ168akxhWDXw/ KgF8lC/htqEoSPNKJQm+fHuX7Cu3glA9b10gPM8Et3N4jIfNDIQbbrxFaQRFTffs vrc0ALX7Ao70lLQKbWy+UVcZmMesMIxBZ7isx2S3wZKO/PqYWyrU23WjJaTttsJk WusJX3kNFtxbxPvccidWZc4kkoSbcT5MBc9PGYpUKhV7hTCv/98hmxrvg== DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d= messagingengine.com; h=cc:content-transfer-encoding:date:from :in-reply-to:message-id:mime-version:references:subject:to :x-me-proxy:x-me-proxy:x-me-sender:x-me-sender:x-sasl-enc; s= fm1; bh=kUtIe6kqnG2FwdUxin7eUzLqjVTtszz1wUf2bM5zKlw=; b=WJt0JVfA odkbL40NFx8fkbar6h2WemXVyQ0G4jgCuxA225kzNDnQukym4H/VbHs7VVlf3gbX zX0NRHGsE9SvqcUi51bjWdY180dy+nUEIE7I2qy7TY73LN64oVdbDKL56h2Qtcur /Kh/azSj5sLfPyoPRxt79BenJRD6USdPu8z69lFnj5bA0gVv3sMMGbiah37jZV5Y pz5Y9wnmdTq0Jdd+msmZpZfig6lDKbR07qtrG+lOBOEeIjY1KeKBubYdrPle+OMm 2Hr/tHJ1xSrlXQNa5b29nVH5F1YcaM1qQfaRePQI6dECChFGJvlCXm0kgXM9WbUi G7rNonqJFwt8HA== X-ME-Sender: X-ME-Proxy-Cause: gggruggvucftvghtrhhoucdtuddrgedufedrvddttddggeelucetufdoteggodetrfdotf fvucfrrhhofhhilhgvmecuhfgrshhtofgrihhlpdfqfgfvpdfurfetoffkrfgpnffqhgen uceurghilhhouhhtmecufedttdenucenucfjughrpefhvffufffkofgjfhgggfestdekre dtredttdenucfhrhhomheptehlihhsthgrihhrucfhrhgrnhgtihhsuceorghlihhsthgr ihhrsegrlhhishhtrghirhdvfedrmhgvqeenucfkphepjeefrdelfedrkeegrddvtdekne curfgrrhgrmhepmhgrihhlfhhrohhmpegrlhhishhtrghirhesrghlihhsthgrihhrvdef rdhmvgenucevlhhushhtvghrufhiiigvpeef X-ME-Proxy: Received: from alistair-xps-14z.alistair23.me (c-73-93-84-208.hsd1.ca.comcast.net [73.93.84.208]) by mail.messagingengine.com (Postfix) with ESMTPA id A85518005A; Fri, 13 Dec 2019 21:44:30 -0500 (EST) From: Alistair Francis To: qemu-devel@nongnu.org, peter.maydell@linaro.org Cc: qemu-arm@nongnu.org, alistair23@gmail.com Subject: [PATCH v6 4/4] hw/arm: Add the Netduino Plus 2 Date: Fri, 13 Dec 2019 18:44:29 -0800 Message-Id: <40f97ae32a6f21d8184c1cc46fad2defb302238d.1576227325.git.alistair@alistair23.me> X-Mailer: git-send-email 2.24.0 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 66.111.4.29 X-Mailman-Approved-At: Sat, 14 Dec 2019 08:40:59 -0500 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sat, 14 Dec 2019 02:44:37 -0000 Signed-off-by: Alistair Francis --- MAINTAINERS | 6 +++++ hw/arm/Kconfig | 3 +++ hw/arm/Makefile.objs | 1 + hw/arm/netduinoplus2.c | 52 ++++++++++++++++++++++++++++++++++++++++++ 4 files changed, 62 insertions(+) create mode 100644 hw/arm/netduinoplus2.c diff --git a/MAINTAINERS b/MAINTAINERS index 10230b3212..b9dd2a11bc 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -828,6 +828,12 @@ M: Peter Maydell S: Maintained F: hw/arm/netduino2.c +Netduino Plus 2 +M: Alistair Francis +M: Peter Maydell +S: Maintained +F: hw/arm/netduinoplus2.c + SmartFusion2 M: Subbaraya Sundeep M: Peter Maydell diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig index 7bfdc3a7ac..881e7f56e7 100644 --- a/hw/arm/Kconfig +++ b/hw/arm/Kconfig @@ -105,6 +105,9 @@ config NETDUINOPLUS2 bool select STM32F405_SOC +config NETDUINOPLUS2 + bool + config NSERIES bool select OMAP diff --git a/hw/arm/Makefile.objs b/hw/arm/Makefile.objs index d9d54da7cf..336f6dd374 100644 --- a/hw/arm/Makefile.objs +++ b/hw/arm/Makefile.objs @@ -11,6 +11,7 @@ obj-$(CONFIG_MAINSTONE) += mainstone.o obj-$(CONFIG_MICROBIT) += microbit.o obj-$(CONFIG_MUSICPAL) += musicpal.o obj-$(CONFIG_NETDUINO2) += netduino2.o +obj-$(CONFIG_NETDUINOPLUS2) += netduinoplus2.o obj-$(CONFIG_NSERIES) += nseries.o obj-$(CONFIG_SX1) += omap_sx1.o obj-$(CONFIG_CHEETAH) += palm.o diff --git a/hw/arm/netduinoplus2.c b/hw/arm/netduinoplus2.c new file mode 100644 index 0000000000..e5e247edbe --- /dev/null +++ b/hw/arm/netduinoplus2.c @@ -0,0 +1,52 @@ +/* + * Netduino Plus 2 Machine Model + * + * Copyright (c) 2014 Alistair Francis + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#include "qemu/osdep.h" +#include "qapi/error.h" +#include "hw/boards.h" +#include "hw/qdev-properties.h" +#include "qemu/error-report.h" +#include "hw/arm/stm32f405_soc.h" +#include "hw/arm/boot.h" + +static void netduinoplus2_init(MachineState *machine) +{ + DeviceState *dev; + + dev = qdev_create(NULL, TYPE_STM32F405_SOC); + qdev_prop_set_string(dev, "cpu-type", ARM_CPU_TYPE_NAME("cortex-m4")); + object_property_set_bool(OBJECT(dev), true, "realized", &error_fatal); + + armv7m_load_kernel(ARM_CPU(first_cpu), + machine->kernel_filename, + FLASH_SIZE); +} + +static void netduinoplus2_machine_init(MachineClass *mc) +{ + mc->desc = "Netduino Plus 2 Machine"; + mc->init = netduinoplus2_init; +} + +DEFINE_MACHINE("netduinoplus2", netduinoplus2_machine_init) -- 2.24.0 From MAILER-DAEMON Sat Dec 14 08:41:01 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1ig7fJ-0007MC-R7 for mharc-qemu-arm@gnu.org; Sat, 14 Dec 2019 08:41:01 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:55147) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ifxPo-0004As-RG for qemu-arm@nongnu.org; Fri, 13 Dec 2019 21:44:22 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ifxPn-0000Y3-MT for qemu-arm@nongnu.org; Fri, 13 Dec 2019 21:44:20 -0500 Received: from out5-smtp.messagingengine.com ([66.111.4.29]:34275) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1ifxPn-0000Rh-5I; Fri, 13 Dec 2019 21:44:19 -0500 Received: from compute7.internal (compute7.nyi.internal [10.202.2.47]) by mailout.nyi.internal (Postfix) with ESMTP id 8D01D2243F; Fri, 13 Dec 2019 21:44:16 -0500 (EST) Received: from mailfrontend1 ([10.202.2.162]) by compute7.internal (MEProxy); Fri, 13 Dec 2019 21:44:16 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=alistair23.me; h=from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; s=fm2; bh=NrkT0Bf96hpTUP4A7dCfRMzsYs Uhcjmd2DZMl2Q/4Cs=; b=MIw5L06fz+tyB9cNCuJpzFCPEjQ3Yn4ZEIONPSvMyy BIKT2VrFu5spkh0TAvN0etm1v7LAXQ6QgdoluzIPAkADs2rQzFGvRFwFaMQRifd0 2xoIyZZUxm378sy5iSvomWuGx1gZc3qq+K3v2OtX5JyPIu9DqhKjzNXQ/p+gqoFR pMRLg2t7gptsXDZJWSsuTMMjzlDV/c9TBvTU1RGdKPBN9Wsvi0ByW0OIx4S+RWyz ajYwKuKZBN/G9k16JQCd5+lM7NhMPBBx6FsJgV3fV5at0Xv6bNt8SF2RxXZ0K+Sz yv6AOw4ToRv7ZI3EayITCbskF/zioY5dP3g1r0Hj6ONA== DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d= messagingengine.com; h=cc:content-transfer-encoding:date:from :message-id:mime-version:subject:to:x-me-proxy:x-me-proxy :x-me-sender:x-me-sender:x-sasl-enc; s=fm1; bh=NrkT0Bf96hpTUP4A7 dCfRMzsYsUhcjmd2DZMl2Q/4Cs=; b=pLtyoae1dRqgjU3UzyxuQC94yw5HW5Ms4 WTrzx3DrblYi32UlG469jVZty45S2mjoSpHyuij0Tv8A2cscfuaRuczCTuAJ5nXk JdOXksikNUA7pXhhkQt+R1asMMV5RWZ1Q/43+KfHvrMwEIvlwzE2AtstbGENaWtU 5mv67ZgzhknNweKTxMM/uDvF5vbDgPmYwfB63TcOL+wEwaWCJn8v4YoVdB8XzWU8 KbhIf0MT15y1pquNhVIKOURHZIoxB3j6CpgbIt235VRL3xSD/+pUVoh+Ux2uLnUN SNaErOqwbVHb+t7WTBk1VOG7LE25a6uIZVLNQ3ZiTNIRZMcEsdbIg== X-ME-Sender: X-ME-Proxy-Cause: gggruggvucftvghtrhhoucdtuddrgedufedrvddttddggeelucetufdoteggodetrfdotf fvucfrrhhofhhilhgvmecuhfgrshhtofgrihhlpdfqfgfvpdfurfetoffkrfgpnffqhgen uceurghilhhouhhtmecufedttdenucenucfjughrpefhvffufffkofgggfestdekredtre dttdenucfhrhhomheptehlihhsthgrihhrucfhrhgrnhgtihhsuceorghlihhsthgrihhr segrlhhishhtrghirhdvfedrmhgvqeenucfkphepjeefrdelfedrkeegrddvtdeknecurf grrhgrmhepmhgrihhlfhhrohhmpegrlhhishhtrghirhesrghlihhsthgrihhrvdefrdhm vgenucevlhhushhtvghrufhiiigvpedt X-ME-Proxy: Received: from alistair-xps-14z.alistair23.me (c-73-93-84-208.hsd1.ca.comcast.net [73.93.84.208]) by mail.messagingengine.com (Postfix) with ESMTPA id 82A5680061; Fri, 13 Dec 2019 21:44:15 -0500 (EST) From: Alistair Francis To: qemu-devel@nongnu.org, peter.maydell@linaro.org Cc: qemu-arm@nongnu.org, alistair23@gmail.com Subject: [PATCH v6 0/4] Add the STM32F405 and Netduino Plus 2 machine Date: Fri, 13 Dec 2019 18:44:14 -0800 Message-Id: X-Mailer: git-send-email 2.24.0 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 66.111.4.29 X-Mailman-Approved-At: Sat, 14 Dec 2019 08:40:59 -0500 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sat, 14 Dec 2019 02:44:22 -0000 Now that the Arm-M4 CPU has been added to QEMU we can add the Netduino Plus 2 machine. This is very similar to the STM32F205 and Netduino 2 SoC and machine. v6: - Remove machine specific reset code - Rebase on master v5: - Fix checkpatch failures - Add mising includes v4: - Rebase on master v3: - Remove custom reset handler - Add init-entry and init-sp properties - Rebase on master (including Kconfig changes) v2: - Reorder patchset - Return the kernel entry point instead of using a pointer - Address Peter's comments Alistair Francis (4): hw/misc: Add the STM32F4xx Sysconfig device hw/misc: Add the STM32F4xx EXTI device hw/arm: Add the STM32F4xx SoC hw/arm: Add the Netduino Plus 2 MAINTAINERS | 14 ++ default-configs/arm-softmmu.mak | 1 + hw/arm/Kconfig | 16 ++ hw/arm/Makefile.objs | 2 + hw/arm/netduinoplus2.c | 52 +++++ hw/arm/stm32f405_soc.c | 302 +++++++++++++++++++++++++++++ hw/misc/Kconfig | 6 + hw/misc/Makefile.objs | 2 + hw/misc/stm32f4xx_exti.c | 189 ++++++++++++++++++ hw/misc/stm32f4xx_syscfg.c | 171 ++++++++++++++++ hw/misc/trace-events | 11 ++ include/hw/arm/stm32f405_soc.h | 73 +++++++ include/hw/misc/stm32f4xx_exti.h | 60 ++++++ include/hw/misc/stm32f4xx_syscfg.h | 61 ++++++ 14 files changed, 960 insertions(+) create mode 100644 hw/arm/netduinoplus2.c create mode 100644 hw/arm/stm32f405_soc.c create mode 100644 hw/misc/stm32f4xx_exti.c create mode 100644 hw/misc/stm32f4xx_syscfg.c create mode 100644 include/hw/arm/stm32f405_soc.h create mode 100644 include/hw/misc/stm32f4xx_exti.h create mode 100644 include/hw/misc/stm32f4xx_syscfg.h -- 2.24.0 From MAILER-DAEMON Sat Dec 14 08:41:02 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1ig7fK-0007MW-1i for mharc-qemu-arm@gnu.org; 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Fri, 13 Dec 2019 21:44:26 -0500 (EST) From: Alistair Francis To: qemu-devel@nongnu.org, peter.maydell@linaro.org Cc: qemu-arm@nongnu.org, alistair23@gmail.com Subject: [PATCH v6 3/4] hw/arm: Add the STM32F4xx SoC Date: Fri, 13 Dec 2019 18:44:26 -0800 Message-Id: X-Mailer: git-send-email 2.24.0 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 66.111.4.29 X-Mailman-Approved-At: Sat, 14 Dec 2019 08:40:59 -0500 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sat, 14 Dec 2019 02:44:35 -0000 Signed-off-by: Alistair Francis Reviewed-by: Peter Maydell --- MAINTAINERS | 8 + hw/arm/Kconfig | 3 + hw/arm/Makefile.objs | 1 + hw/arm/stm32f405_soc.c | 302 +++++++++++++++++++++++++++++++++ include/hw/arm/stm32f405_soc.h | 73 ++++++++ 5 files changed, 387 insertions(+) create mode 100644 hw/arm/stm32f405_soc.c create mode 100644 include/hw/arm/stm32f405_soc.h diff --git a/MAINTAINERS b/MAINTAINERS index 5e5e3e52d6..10230b3212 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -814,6 +814,14 @@ F: hw/adc/* F: hw/ssi/stm32f2xx_spi.c F: include/hw/*/stm32*.h +STM32F405 +M: Alistair Francis +M: Peter Maydell +S: Maintained +F: hw/arm/stm32f405_soc.c +F: hw/misc/stm32f4xx_syscfg.c +F: hw/misc/stm32f4xx_exti.c + Netduino 2 M: Alistair Francis M: Peter Maydell diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig index 3d86691ae0..7bfdc3a7ac 100644 --- a/hw/arm/Kconfig +++ b/hw/arm/Kconfig @@ -317,6 +317,9 @@ config STM32F405_SOC select STM32F4XX_SYSCFG select STM32F4XX_EXTI +config STM32F405_SOC + bool + config XLNX_ZYNQMP_ARM bool select AHCI diff --git a/hw/arm/Makefile.objs b/hw/arm/Makefile.objs index fe749f65fd..d9d54da7cf 100644 --- a/hw/arm/Makefile.objs +++ b/hw/arm/Makefile.objs @@ -36,6 +36,7 @@ obj-$(CONFIG_STRONGARM) += strongarm.o obj-$(CONFIG_ALLWINNER_A10) += allwinner-a10.o cubieboard.o obj-$(CONFIG_RASPI) += bcm2835_peripherals.o bcm2836.o raspi.o obj-$(CONFIG_STM32F205_SOC) += stm32f205_soc.o +obj-$(CONFIG_STM32F405_SOC) += stm32f405_soc.o obj-$(CONFIG_XLNX_ZYNQMP_ARM) += xlnx-zynqmp.o xlnx-zcu102.o obj-$(CONFIG_XLNX_VERSAL) += xlnx-versal.o xlnx-versal-virt.o obj-$(CONFIG_FSL_IMX25) += fsl-imx25.o imx25_pdk.o diff --git a/hw/arm/stm32f405_soc.c b/hw/arm/stm32f405_soc.c new file mode 100644 index 0000000000..f22516fdf7 --- /dev/null +++ b/hw/arm/stm32f405_soc.c @@ -0,0 +1,302 @@ +/* + * STM32F405 SoC + * + * Copyright (c) 2014 Alistair Francis + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#include "qemu/osdep.h" +#include "qapi/error.h" +#include "qemu-common.h" +#include "exec/address-spaces.h" +#include "sysemu/sysemu.h" +#include "hw/arm/stm32f405_soc.h" +#include "hw/misc/unimp.h" + +#define SYSCFG_ADD 0x40013800 +static const uint32_t usart_addr[] = { 0x40011000, 0x40004400, 0x40004800, + 0x40004C00, 0x40005000, 0x40011400, + 0x40007800, 0x40007C00 }; +/* At the moment only Timer 2 to 5 are modelled */ +static const uint32_t timer_addr[] = { 0x40000000, 0x40000400, + 0x40000800, 0x40000C00 }; +#define ADC_ADDR 0x40012000 +static const uint32_t spi_addr[] = { 0x40013000, 0x40003800, 0x40003C00, + 0x40013400, 0x40015000, 0x40015400 }; +#define EXTI_ADDR 0x40013C00 + +#define SYSCFG_IRQ 71 +static const int usart_irq[] = { 37, 38, 39, 52, 53, 71, 82, 83 }; +static const int timer_irq[] = { 28, 29, 30, 50 }; +#define ADC_IRQ 18 +static const int spi_irq[] = { 35, 36, 51, 0, 0, 0 }; +static const int exti_irq[] = { 6, 7, 8, 9, 10, 23, 23, 23, 23, 23, 40, + 40, 40, 40, 40, 40} ; + + +static void stm32f405_soc_initfn(Object *obj) +{ + STM32F405State *s = STM32F405_SOC(obj); + int i; + + sysbus_init_child_obj(obj, "armv7m", &s->armv7m, sizeof(s->armv7m), + TYPE_ARMV7M); + + sysbus_init_child_obj(obj, "syscfg", &s->syscfg, sizeof(s->syscfg), + TYPE_STM32F4XX_SYSCFG); + + for (i = 0; i < STM_NUM_USARTS; i++) { + sysbus_init_child_obj(obj, "usart[*]", &s->usart[i], + sizeof(s->usart[i]), TYPE_STM32F2XX_USART); + } + + for (i = 0; i < STM_NUM_TIMERS; i++) { + sysbus_init_child_obj(obj, "timer[*]", &s->timer[i], + sizeof(s->timer[i]), TYPE_STM32F2XX_TIMER); + } + + for (i = 0; i < STM_NUM_ADCS; i++) { + sysbus_init_child_obj(obj, "adc[*]", &s->adc[i], sizeof(s->adc[i]), + TYPE_STM32F2XX_ADC); + } + + for (i = 0; i < STM_NUM_SPIS; i++) { + sysbus_init_child_obj(obj, "spi[*]", &s->spi[i], sizeof(s->spi[i]), + TYPE_STM32F2XX_SPI); + } + + sysbus_init_child_obj(obj, "exti", &s->exti, sizeof(s->exti), + TYPE_STM32F4XX_EXTI); +} + +static void stm32f405_soc_realize(DeviceState *dev_soc, Error **errp) +{ + STM32F405State *s = STM32F405_SOC(dev_soc); + MemoryRegion *system_memory = get_system_memory(); + DeviceState *dev, *armv7m; + SysBusDevice *busdev; + Error *err = NULL; + int i; + + memory_region_init_ram(&s->flash, NULL, "STM32F405.flash", FLASH_SIZE, + &err); + if (err != NULL) { + error_propagate(errp, err); + return; + } + memory_region_init_alias(&s->flash_alias, NULL, "STM32F405.flash.alias", + &s->flash, 0, FLASH_SIZE); + + memory_region_set_readonly(&s->flash, true); + memory_region_set_readonly(&s->flash_alias, true); + + memory_region_add_subregion(system_memory, FLASH_BASE_ADDRESS, &s->flash); + memory_region_add_subregion(system_memory, 0, &s->flash_alias); + + memory_region_init_ram(&s->sram, NULL, "STM32F405.sram", SRAM_SIZE, + &err); + if (err != NULL) { + error_propagate(errp, err); + return; + } + memory_region_add_subregion(system_memory, SRAM_BASE_ADDRESS, &s->sram); + + armv7m = DEVICE(&s->armv7m); + qdev_prop_set_uint32(armv7m, "num-irq", 96); + qdev_prop_set_string(armv7m, "cpu-type", s->cpu_type); + qdev_prop_set_bit(armv7m, "enable-bitband", true); + object_property_set_link(OBJECT(&s->armv7m), OBJECT(system_memory), + "memory", &error_abort); + object_property_set_bool(OBJECT(&s->armv7m), true, "realized", &err); + if (err != NULL) { + error_propagate(errp, err); + return; + } + + /* System configuration controller */ + dev = DEVICE(&s->syscfg); + object_property_set_bool(OBJECT(&s->syscfg), true, "realized", &err); + if (err != NULL) { + error_propagate(errp, err); + return; + } + busdev = SYS_BUS_DEVICE(dev); + sysbus_mmio_map(busdev, 0, SYSCFG_ADD); + sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(armv7m, SYSCFG_IRQ)); + + /* Attach UART (uses USART registers) and USART controllers */ + for (i = 0; i < STM_NUM_USARTS; i++) { + dev = DEVICE(&(s->usart[i])); + qdev_prop_set_chr(dev, "chardev", serial_hd(i)); + object_property_set_bool(OBJECT(&s->usart[i]), true, "realized", &err); + if (err != NULL) { + error_propagate(errp, err); + return; + } + busdev = SYS_BUS_DEVICE(dev); + sysbus_mmio_map(busdev, 0, usart_addr[i]); + sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(armv7m, usart_irq[i])); + } + + /* Timer 2 to 5 */ + for (i = 0; i < STM_NUM_TIMERS; i++) { + dev = DEVICE(&(s->timer[i])); + qdev_prop_set_uint64(dev, "clock-frequency", 1000000000); + object_property_set_bool(OBJECT(&s->timer[i]), true, "realized", &err); + if (err != NULL) { + error_propagate(errp, err); + return; + } + busdev = SYS_BUS_DEVICE(dev); + sysbus_mmio_map(busdev, 0, timer_addr[i]); + sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(armv7m, timer_irq[i])); + } + + /* ADC device, the IRQs are ORed together */ + object_initialize_child(OBJECT(s), "adc-orirq", &s->adc_irqs, + sizeof(s->adc_irqs), TYPE_OR_IRQ, + &err, NULL); + if (err != NULL) { + error_propagate(errp, err); + return; + } + object_property_set_int(OBJECT(&s->adc_irqs), STM_NUM_ADCS, + "num-lines", &err); + object_property_set_bool(OBJECT(&s->adc_irqs), true, "realized", &err); + if (err != NULL) { + error_propagate(errp, err); + return; + } + qdev_connect_gpio_out(DEVICE(&s->adc_irqs), 0, + qdev_get_gpio_in(armv7m, ADC_IRQ)); + + dev = DEVICE(&(s->adc[i])); + object_property_set_bool(OBJECT(&s->adc[i]), true, "realized", &err); + if (err != NULL) { + error_propagate(errp, err); + return; + } + busdev = SYS_BUS_DEVICE(dev); + sysbus_mmio_map(busdev, 0, ADC_ADDR); + sysbus_connect_irq(busdev, 0, + qdev_get_gpio_in(DEVICE(&s->adc_irqs), i)); + + /* SPI devices */ + for (i = 0; i < STM_NUM_SPIS; i++) { + dev = DEVICE(&(s->spi[i])); + object_property_set_bool(OBJECT(&s->spi[i]), true, "realized", &err); + if (err != NULL) { + error_propagate(errp, err); + return; + } + busdev = SYS_BUS_DEVICE(dev); + sysbus_mmio_map(busdev, 0, spi_addr[i]); + sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(armv7m, spi_irq[i])); + } + + /* EXTI device */ + dev = DEVICE(&s->exti); + object_property_set_bool(OBJECT(&s->exti), true, "realized", &err); + if (err != NULL) { + error_propagate(errp, err); + return; + } + busdev = SYS_BUS_DEVICE(dev); + sysbus_mmio_map(busdev, 0, EXTI_ADDR); + for (i = 0; i < 16; i++) { + sysbus_connect_irq(busdev, i, qdev_get_gpio_in(armv7m, exti_irq[i])); + } + for (i = 0; i < 16; i++) { + qdev_connect_gpio_out(DEVICE(&s->syscfg), i, qdev_get_gpio_in(dev, i)); + } + + create_unimplemented_device("timer[7]", 0x40001400, 0x400); + create_unimplemented_device("timer[12]", 0x40001800, 0x400); + create_unimplemented_device("timer[6]", 0x40001000, 0x400); + create_unimplemented_device("timer[13]", 0x40001C00, 0x400); + create_unimplemented_device("timer[14]", 0x40002000, 0x400); + create_unimplemented_device("RTC and BKP", 0x40002800, 0x400); + create_unimplemented_device("WWDG", 0x40002C00, 0x400); + create_unimplemented_device("IWDG", 0x40003000, 0x400); + create_unimplemented_device("I2S2ext", 0x40003000, 0x400); + create_unimplemented_device("I2S3ext", 0x40004000, 0x400); + create_unimplemented_device("I2C1", 0x40005400, 0x400); + create_unimplemented_device("I2C2", 0x40005800, 0x400); + create_unimplemented_device("I2C3", 0x40005C00, 0x400); + create_unimplemented_device("CAN1", 0x40006400, 0x400); + create_unimplemented_device("CAN2", 0x40006800, 0x400); + create_unimplemented_device("PWR", 0x40007000, 0x400); + create_unimplemented_device("DAC", 0x40007400, 0x400); + create_unimplemented_device("timer[1]", 0x40010000, 0x400); + create_unimplemented_device("timer[8]", 0x40010400, 0x400); + create_unimplemented_device("SDIO", 0x40012C00, 0x400); + create_unimplemented_device("timer[9]", 0x40014000, 0x400); + create_unimplemented_device("timer[10]", 0x40014400, 0x400); + create_unimplemented_device("timer[11]", 0x40014800, 0x400); + create_unimplemented_device("GPIOA", 0x40020000, 0x400); + create_unimplemented_device("GPIOB", 0x40020400, 0x400); + create_unimplemented_device("GPIOC", 0x40020800, 0x400); + create_unimplemented_device("GPIOD", 0x40020C00, 0x400); + create_unimplemented_device("GPIOE", 0x40021000, 0x400); + create_unimplemented_device("GPIOF", 0x40021400, 0x400); + create_unimplemented_device("GPIOG", 0x40021800, 0x400); + create_unimplemented_device("GPIOH", 0x40021C00, 0x400); + create_unimplemented_device("GPIOI", 0x40022000, 0x400); + create_unimplemented_device("CRC", 0x40023000, 0x400); + create_unimplemented_device("RCC", 0x40023800, 0x400); + create_unimplemented_device("Flash Int", 0x40023C00, 0x400); + create_unimplemented_device("BKPSRAM", 0x40024000, 0x400); + create_unimplemented_device("DMA1", 0x40026000, 0x400); + create_unimplemented_device("DMA2", 0x40026400, 0x400); + create_unimplemented_device("Ethernet", 0x40028000, 0x1400); + create_unimplemented_device("USB OTG HS", 0x40040000, 0x30000); + create_unimplemented_device("USB OTG FS", 0x50000000, 0x31000); + create_unimplemented_device("DCMI", 0x50050000, 0x400); + create_unimplemented_device("RNG", 0x50060800, 0x400); +} + +static Property stm32f405_soc_properties[] = { + DEFINE_PROP_STRING("cpu-type", STM32F405State, cpu_type), + DEFINE_PROP_END_OF_LIST(), +}; + +static void stm32f405_soc_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + + dc->realize = stm32f405_soc_realize; + dc->props = stm32f405_soc_properties; + /* No vmstate or reset required: device has no internal state */ +} + +static const TypeInfo stm32f405_soc_info = { + .name = TYPE_STM32F405_SOC, + .parent = TYPE_SYS_BUS_DEVICE, + .instance_size = sizeof(STM32F405State), + .instance_init = stm32f405_soc_initfn, + .class_init = stm32f405_soc_class_init, +}; + +static void stm32f405_soc_types(void) +{ + type_register_static(&stm32f405_soc_info); +} + +type_init(stm32f405_soc_types) diff --git a/include/hw/arm/stm32f405_soc.h b/include/hw/arm/stm32f405_soc.h new file mode 100644 index 0000000000..1fe97f8c3a --- /dev/null +++ b/include/hw/arm/stm32f405_soc.h @@ -0,0 +1,73 @@ +/* + * STM32F405 SoC + * + * Copyright (c) 2014 Alistair Francis + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#ifndef HW_ARM_STM32F405_SOC_H +#define HW_ARM_STM32F405_SOC_H + +#include "hw/misc/stm32f4xx_syscfg.h" +#include "hw/timer/stm32f2xx_timer.h" +#include "hw/char/stm32f2xx_usart.h" +#include "hw/adc/stm32f2xx_adc.h" +#include "hw/misc/stm32f4xx_exti.h" +#include "hw/or-irq.h" +#include "hw/ssi/stm32f2xx_spi.h" +#include "hw/arm/armv7m.h" + +#define TYPE_STM32F405_SOC "stm32f405-soc" +#define STM32F405_SOC(obj) \ + OBJECT_CHECK(STM32F405State, (obj), TYPE_STM32F405_SOC) + +#define STM_NUM_USARTS 7 +#define STM_NUM_TIMERS 4 +#define STM_NUM_ADCS 6 +#define STM_NUM_SPIS 6 + +#define FLASH_BASE_ADDRESS 0x08000000 +#define FLASH_SIZE (1024 * 1024) +#define SRAM_BASE_ADDRESS 0x20000000 +#define SRAM_SIZE (192 * 1024) + +typedef struct STM32F405State { + /*< private >*/ + SysBusDevice parent_obj; + /*< public >*/ + + char *cpu_type; + + ARMv7MState armv7m; + + STM32F4xxSyscfgState syscfg; + STM32F4xxExtiState exti; + STM32F2XXUsartState usart[STM_NUM_USARTS]; + STM32F2XXTimerState timer[STM_NUM_TIMERS]; + qemu_or_irq adc_irqs; + STM32F2XXADCState adc[STM_NUM_ADCS]; + STM32F2XXSPIState spi[STM_NUM_SPIS]; + + MemoryRegion sram; + MemoryRegion flash; + MemoryRegion flash_alias; +} STM32F405State; + +#endif -- 2.24.0 From MAILER-DAEMON Sat Dec 14 15:58:09 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1igEUL-0006yj-BJ for mharc-qemu-arm@gnu.org; Sat, 14 Dec 2019 15:58:09 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:44311) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1igEUI-0006yE-IH for qemu-arm@nongnu.org; Sat, 14 Dec 2019 15:58:08 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1igEUG-0003oC-2n for qemu-arm@nongnu.org; Sat, 14 Dec 2019 15:58:04 -0500 Received: from us-smtp-1.mimecast.com ([205.139.110.61]:52870 helo=us-smtp-delivery-1.mimecast.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1igEUF-0003hV-TS for qemu-arm@nongnu.org; Sat, 14 Dec 2019 15:58:04 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1576357081; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding; bh=DU+v1+qSXxMwHczsoakDiicLnkfOmtj3Euf4AZRmwFY=; b=EBDBCsq+k3aa1gdI4dc6bM05PFuNLkd/pFnjyigdnItQ068ofa3/1DdfFhtGi6E5GRj+HJ LLjUYZlQLSpEBkMpjRJHjw2pQenxUsV3grDWvKoggXDucYEudPnleoMPjdO1mmeMUAuDz5 ByAXH3tWn0TRcV+pOmayRn6LU3vqQR8= Received: from mimecast-mx01.redhat.com (mimecast-mx01.redhat.com [209.132.183.4]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-200-9iIaSgdkNYWGuH4yNdMIvw-1; Sat, 14 Dec 2019 10:56:33 -0500 X-MC-Unique: 9iIaSgdkNYWGuH4yNdMIvw-1 Received: from smtp.corp.redhat.com (int-mx05.intmail.prod.int.phx2.redhat.com [10.5.11.15]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx01.redhat.com (Postfix) with ESMTPS id B08321005502; Sat, 14 Dec 2019 15:56:31 +0000 (UTC) Received: from x1w.redhat.com (ovpn-205-147.brq.redhat.com [10.40.205.147]) by smtp.corp.redhat.com (Postfix) with ESMTPS id 234905D6A7; Sat, 14 Dec 2019 15:56:16 +0000 (UTC) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Peter Maydell , Andrew Baumann , Aurelien Jarno , kvm@vger.kernel.org, Alex Williamson , Aleksandar Markovic , Joel Stanley , qemu-arm@nongnu.org, Marcelo Tosatti , Alistair Francis , "Michael S. Tsirkin" , Eduardo Habkost , Richard Henderson , Aleksandar Rikalo , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Paul Burton , Marcel Apfelbaum , "Edgar E. Iglesias" , Paolo Bonzini Subject: [PATCH 0/8] Simplify memory_region_add_subregion_overlap(..., priority=0) Date: Sat, 14 Dec 2019 16:56:06 +0100 Message-Id: <20191214155614.19004-1-philmd@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 X-Scanned-By: MIMEDefang 2.79 on 10.5.11.15 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 205.139.110.61 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sat, 14 Dec 2019 20:58:08 -0000 Hi, In this series we use coccinelle to replace: - memory_region_add_subregion_overlap(..., priority=3D0) + memory_region_add_subregion(...) Rationale is the code is easier to read, and reviewers don't have to worry about overlapping because it isn't used. Last patch is a minor cleanup in variable names. I expect each subsystem maintainer to take the subsystem patches. Regards, Phil. Philippe Mathieu-Daud=C3=A9 (8): hw/arm/nrf51_soc: Use memory_region_add_subregion() when priority is 0 hw/arm/raspi: Use memory_region_add_subregion() when priority is 0 hw/arm/xlnx-versal: Use memory_region_add_subregion() when priority is 0 hw/i386/intel_iommu: Use memory_region_add_subregion when priority is 0 hw/mips/boston: Use memory_region_add_subregion() when priority is 0 hw/vfio/pci: Use memory_region_add_subregion() when priority is 0 target/i386: Use memory_region_add_subregion() when priority is 0 target/i386/cpu: Use 'mr' for MemoryRegion variables target/i386/cpu.h | 2 +- hw/arm/bcm2835_peripherals.c | 4 ++-- hw/arm/nrf51_soc.c | 14 +++++++------- hw/arm/raspi.c | 2 +- hw/arm/xlnx-versal-virt.c | 3 +-- hw/arm/xlnx-versal.c | 4 ++-- hw/i386/intel_iommu.c | 11 ++++------- hw/mips/boston.c | 14 +++++++------- hw/vfio/pci.c | 3 +-- target/i386/cpu.c | 18 +++++++++--------- target/i386/kvm.c | 2 +- 11 files changed, 36 insertions(+), 41 deletions(-) --=20 2.21.0 From MAILER-DAEMON Sat Dec 14 15:59:14 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1igEVO-0007Zl-Lw for mharc-qemu-arm@gnu.org; Sat, 14 Dec 2019 15:59:14 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:37829) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1igEVM-0007ZG-JO for qemu-arm@nongnu.org; Sat, 14 Dec 2019 15:59:13 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1igEVL-0007Br-Co for qemu-arm@nongnu.org; Sat, 14 Dec 2019 15:59:12 -0500 Received: from us-smtp-delivery-1.mimecast.com ([207.211.31.120]:30316 helo=us-smtp-1.mimecast.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1igEVL-00078G-7D for qemu-arm@nongnu.org; Sat, 14 Dec 2019 15:59:11 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1576357150; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=cFyYhSJaR8h39Rbqagf85ifWXxR+w0L7k4hKSrlfago=; b=fFOyT04NXIGFh6MrBpyYxVtESBvmCSsEMcmq3FHJpXkR8amvdf1JEuzvJGBT+WFRvG65sB YVdpeKWcgpgbuQORCPUDVq/3pJfSATITb3BRnhZxFcRf8TG8kZMOZOOsyEvDSqlH9WRcUc j85ksL8/KnGcBvAknSFHUt6WgKde1Nk= Received: from mimecast-mx01.redhat.com (mimecast-mx01.redhat.com [209.132.183.4]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-205-GKZmRrbXNv-VBjqVcGU-Mg-1; Sat, 14 Dec 2019 10:58:20 -0500 X-MC-Unique: GKZmRrbXNv-VBjqVcGU-Mg-1 Received: from smtp.corp.redhat.com (int-mx05.intmail.prod.int.phx2.redhat.com [10.5.11.15]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx01.redhat.com (Postfix) with ESMTPS id 3AAA1801E74; Sat, 14 Dec 2019 15:58:18 +0000 (UTC) Received: from x1w.redhat.com (ovpn-205-147.brq.redhat.com [10.40.205.147]) by smtp.corp.redhat.com (Postfix) with ESMTPS id E18B066A1A; Sat, 14 Dec 2019 15:58:05 +0000 (UTC) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Peter Maydell , Andrew Baumann , Aurelien Jarno , kvm@vger.kernel.org, Alex Williamson , Aleksandar Markovic , Joel Stanley , qemu-arm@nongnu.org, Marcelo Tosatti , Alistair Francis , "Michael S. Tsirkin" , Eduardo Habkost , Richard Henderson , Aleksandar Rikalo , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Paul Burton , Marcel Apfelbaum , "Edgar E. Iglesias" , Paolo Bonzini Subject: [PATCH 8/8] target/i386/cpu: Use 'mr' for MemoryRegion variables Date: Sat, 14 Dec 2019 16:56:14 +0100 Message-Id: <20191214155614.19004-9-philmd@redhat.com> In-Reply-To: <20191214155614.19004-1-philmd@redhat.com> References: <20191214155614.19004-1-philmd@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 X-Scanned-By: MIMEDefang 2.79 on 10.5.11.15 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 207.211.31.120 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sat, 14 Dec 2019 20:59:13 -0000 The codebase use 'as' in variable names for AddressSpace objects, and 'mr' for MemoryRegion objects. Since these variables are MemoryRegion objects, rename them as 'mr' to avoid confusion with AddressSpace objects. Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- target/i386/cpu.h | 2 +- target/i386/cpu.c | 18 +++++++++--------- 2 files changed, 10 insertions(+), 10 deletions(-) diff --git a/target/i386/cpu.h b/target/i386/cpu.h index cde2a16b94..1e5ded6e84 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -1713,7 +1713,7 @@ struct X86CPU { /* in order to simplify APIC support, we leave this pointer to the user */ struct DeviceState *apic_state; - struct MemoryRegion *cpu_as_root, *cpu_as_mem, *smram; + MemoryRegion *cpu_mr_root, *cpu_mr_mem, *smram; Notifier machine_done; =20 struct kvm_msrs *kvm_msr_buf; diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 6131c62f9d..b5d22740b8 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -5983,7 +5983,7 @@ static void x86_cpu_machine_done(Notifier *n, void = *unused) memory_region_init_alias(cpu->smram, OBJECT(cpu), "smram", smram, 0, 1ull << 32); memory_region_set_enabled(cpu->smram, true); - memory_region_add_subregion_overlap(cpu->cpu_as_root, 0, cpu->sm= ram, 1); + memory_region_add_subregion_overlap(cpu->cpu_mr_root, 0, cpu->sm= ram, 1); } } #else @@ -6471,24 +6471,24 @@ static void x86_cpu_realizefn(DeviceState *dev, E= rror **errp) =20 #ifndef CONFIG_USER_ONLY if (tcg_enabled()) { - cpu->cpu_as_mem =3D g_new(MemoryRegion, 1); - cpu->cpu_as_root =3D g_new(MemoryRegion, 1); + cpu->cpu_mr_mem =3D g_new(MemoryRegion, 1); + cpu->cpu_mr_root =3D g_new(MemoryRegion, 1); =20 /* Outer container... */ - memory_region_init(cpu->cpu_as_root, OBJECT(cpu), "memory", ~0ul= l); - memory_region_set_enabled(cpu->cpu_as_root, true); + memory_region_init(cpu->cpu_mr_root, OBJECT(cpu), "memory", ~0ul= l); + memory_region_set_enabled(cpu->cpu_mr_root, true); =20 /* ... with two regions inside: normal system memory with low * priority, and... */ - memory_region_init_alias(cpu->cpu_as_mem, OBJECT(cpu), "memory", + memory_region_init_alias(cpu->cpu_mr_mem, OBJECT(cpu), "memory", get_system_memory(), 0, ~0ull); - memory_region_add_subregion(cpu->cpu_as_root, 0, cpu->cpu_as_mem= ); - memory_region_set_enabled(cpu->cpu_as_mem, true); + memory_region_add_subregion(cpu->cpu_mr_root, 0, cpu->cpu_mr_mem= ); + memory_region_set_enabled(cpu->cpu_mr_mem, true); =20 cs->num_ases =3D 2; cpu_address_space_init(cs, 0, "cpu-memory", cs->memory); - cpu_address_space_init(cs, 1, "cpu-smm", cpu->cpu_as_root); + cpu_address_space_init(cs, 1, "cpu-smm", cpu->cpu_mr_root); =20 /* ... SMRAM with higher priority, linked from /machine/smram. = */ cpu->machine_done.notify =3D x86_cpu_machine_done; --=20 2.21.0 From MAILER-DAEMON Sat Dec 14 15:59:24 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1igEVY-0007o1-1x for mharc-qemu-arm@gnu.org; Sat, 14 Dec 2019 15:59:24 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:40739) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1igEVV-0007kp-AC for qemu-arm@nongnu.org; Sat, 14 Dec 2019 15:59:22 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1igEVU-0007dx-4t for qemu-arm@nongnu.org; Sat, 14 Dec 2019 15:59:21 -0500 Received: from us-smtp-delivery-1.mimecast.com ([205.139.110.120]:52244 helo=us-smtp-1.mimecast.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1igEVT-0007c9-Ue for qemu-arm@nongnu.org; Sat, 14 Dec 2019 15:59:20 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1576357159; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=IiMSoFUEZseoMxLw1sAmT/IUeieWX2EUqAxBTC+j+po=; b=ghzBJP88B4iQgceh0fqNxwlCPfFlOCloNtEFCU0Ib+S32KOsLT92oA5z0PaRWSvm8rQNTE yiwh4E2wGl2Zwhchff9npqOkVrwWM6brULAyac3HyWhDRJI1EHqFNCd0V4itycMvcpo26S tjnB9bFORHcSqThCJn1kFRLDXiWdEcc= Received: from mimecast-mx01.redhat.com (mimecast-mx01.redhat.com [209.132.183.4]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-5-8GfcR2qbM7asPJU8NqZDDA-1; Sat, 14 Dec 2019 10:56:49 -0500 X-MC-Unique: 8GfcR2qbM7asPJU8NqZDDA-1 Received: from smtp.corp.redhat.com (int-mx05.intmail.prod.int.phx2.redhat.com [10.5.11.15]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx01.redhat.com (Postfix) with ESMTPS id 62B71107ACC4; Sat, 14 Dec 2019 15:56:47 +0000 (UTC) Received: from x1w.redhat.com (ovpn-205-147.brq.redhat.com [10.40.205.147]) by smtp.corp.redhat.com (Postfix) with ESMTPS id 4C0F166A1A; Sat, 14 Dec 2019 15:56:32 +0000 (UTC) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Peter Maydell , Andrew Baumann , Aurelien Jarno , kvm@vger.kernel.org, Alex Williamson , Aleksandar Markovic , Joel Stanley , qemu-arm@nongnu.org, Marcelo Tosatti , Alistair Francis , "Michael S. Tsirkin" , Eduardo Habkost , Richard Henderson , Aleksandar Rikalo , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Paul Burton , Marcel Apfelbaum , "Edgar E. Iglesias" , Paolo Bonzini Subject: [PATCH 1/8] hw/arm/nrf51_soc: Use memory_region_add_subregion() when priority is 0 Date: Sat, 14 Dec 2019 16:56:07 +0100 Message-Id: <20191214155614.19004-2-philmd@redhat.com> In-Reply-To: <20191214155614.19004-1-philmd@redhat.com> References: <20191214155614.19004-1-philmd@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 X-Scanned-By: MIMEDefang 2.79 on 10.5.11.15 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 205.139.110.120 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sat, 14 Dec 2019 20:59:22 -0000 It is pointless to overlap a memory subregion with priority 0. Use the simpler memory_region_add_subregion() function. This patch was produced with the following spatch script: @@ expression region; expression offset; expression subregion; @@ -memory_region_add_subregion_overlap(region, offset, subregion, 0) +memory_region_add_subregion(region, offset, subregion) Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- hw/arm/nrf51_soc.c | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/hw/arm/nrf51_soc.c b/hw/arm/nrf51_soc.c index 74029169d0..ade06b225f 100644 --- a/hw/arm/nrf51_soc.c +++ b/hw/arm/nrf51_soc.c @@ -94,7 +94,7 @@ static void nrf51_soc_realize(DeviceState *dev_soc, Err= or **errp) return; } mr =3D sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->uart), 0); - memory_region_add_subregion_overlap(&s->container, NRF51_UART_BASE, = mr, 0); + memory_region_add_subregion(&s->container, NRF51_UART_BASE, mr); sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart), 0, qdev_get_gpio_in(DEVICE(&s->cpu), BASE_TO_IRQ(NRF51_UART_BASE))); @@ -107,7 +107,7 @@ static void nrf51_soc_realize(DeviceState *dev_soc, E= rror **errp) } =20 mr =3D sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->rng), 0); - memory_region_add_subregion_overlap(&s->container, NRF51_RNG_BASE, m= r, 0); + memory_region_add_subregion(&s->container, NRF51_RNG_BASE, mr); sysbus_connect_irq(SYS_BUS_DEVICE(&s->rng), 0, qdev_get_gpio_in(DEVICE(&s->cpu), BASE_TO_IRQ(NRF51_RNG_BASE))); @@ -127,13 +127,13 @@ static void nrf51_soc_realize(DeviceState *dev_soc,= Error **errp) } =20 mr =3D sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->nvm), 0); - memory_region_add_subregion_overlap(&s->container, NRF51_NVMC_BASE, = mr, 0); + memory_region_add_subregion(&s->container, NRF51_NVMC_BASE, mr); mr =3D sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->nvm), 1); - memory_region_add_subregion_overlap(&s->container, NRF51_FICR_BASE, = mr, 0); + memory_region_add_subregion(&s->container, NRF51_FICR_BASE, mr); mr =3D sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->nvm), 2); - memory_region_add_subregion_overlap(&s->container, NRF51_UICR_BASE, = mr, 0); + memory_region_add_subregion(&s->container, NRF51_UICR_BASE, mr); mr =3D sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->nvm), 3); - memory_region_add_subregion_overlap(&s->container, NRF51_FLASH_BASE,= mr, 0); + memory_region_add_subregion(&s->container, NRF51_FLASH_BASE, mr); =20 /* GPIO */ object_property_set_bool(OBJECT(&s->gpio), true, "realized", &err); @@ -143,7 +143,7 @@ static void nrf51_soc_realize(DeviceState *dev_soc, E= rror **errp) } =20 mr =3D sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->gpio), 0); - memory_region_add_subregion_overlap(&s->container, NRF51_GPIO_BASE, = mr, 0); + memory_region_add_subregion(&s->container, NRF51_GPIO_BASE, mr); =20 /* Pass all GPIOs to the SOC layer so they are available to the boar= d */ qdev_pass_gpios(DEVICE(&s->gpio), dev_soc, NULL); --=20 2.21.0 From MAILER-DAEMON Sat Dec 14 15:59:31 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1igEVf-0007z0-3V for mharc-qemu-arm@gnu.org; Sat, 14 Dec 2019 15:59:31 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:42751) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1igEVb-0007tp-NP for qemu-arm@nongnu.org; Sat, 14 Dec 2019 15:59:28 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1igEVa-0007z7-Fj for qemu-arm@nongnu.org; Sat, 14 Dec 2019 15:59:27 -0500 Received: from us-smtp-delivery-1.mimecast.com ([205.139.110.120]:60388 helo=us-smtp-1.mimecast.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1igEVZ-0007v7-Ry for qemu-arm@nongnu.org; Sat, 14 Dec 2019 15:59:26 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1576357165; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=MiLtQtAFIR7WooqjFNP7RA7pxFuVPXkVzD1becE3SHU=; b=buos031Z8ORubbwg0qb79p4ex9zeZFsxAUxe9CgYSIONBNo6hmzTAJsdkiLl//NhjWtqPo ghsiKdAA8Asb9gx/S+aNnNQ41uGqju4zhsndqAZH3MFeSUTRY38H71AuuV5oCo23CO3F6t bFyO55xXLLmjt1ypOSmA509jJplZ12E= Received: from mimecast-mx01.redhat.com (mimecast-mx01.redhat.com [209.132.183.4]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-95-GUjV9-9vPW2uksM1tC2tFw-1; Sat, 14 Dec 2019 10:57:21 -0500 X-MC-Unique: GUjV9-9vPW2uksM1tC2tFw-1 Received: from smtp.corp.redhat.com (int-mx05.intmail.prod.int.phx2.redhat.com [10.5.11.15]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx01.redhat.com (Postfix) with ESMTPS id 6B6CA801E53; Sat, 14 Dec 2019 15:57:19 +0000 (UTC) Received: from x1w.redhat.com (ovpn-205-147.brq.redhat.com [10.40.205.147]) by smtp.corp.redhat.com (Postfix) with ESMTPS id 9F5D75D6A7; Sat, 14 Dec 2019 15:57:09 +0000 (UTC) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Peter Maydell , Andrew Baumann , Aurelien Jarno , kvm@vger.kernel.org, Alex Williamson , Aleksandar Markovic , Joel Stanley , qemu-arm@nongnu.org, Marcelo Tosatti , Alistair Francis , "Michael S. Tsirkin" , Eduardo Habkost , Richard Henderson , Aleksandar Rikalo , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Paul Burton , Marcel Apfelbaum , "Edgar E. Iglesias" , Paolo Bonzini Subject: [PATCH 3/8] hw/arm/xlnx-versal: Use memory_region_add_subregion() when priority is 0 Date: Sat, 14 Dec 2019 16:56:09 +0100 Message-Id: <20191214155614.19004-4-philmd@redhat.com> In-Reply-To: <20191214155614.19004-1-philmd@redhat.com> References: <20191214155614.19004-1-philmd@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 X-Scanned-By: MIMEDefang 2.79 on 10.5.11.15 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 205.139.110.120 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sat, 14 Dec 2019 20:59:29 -0000 It is pointless to overlap a memory subregion with priority 0. Use the simpler memory_region_add_subregion() function. This patch was produced with the following spatch script: @@ expression region; expression offset; expression subregion; @@ -memory_region_add_subregion_overlap(region, offset, subregion, 0) +memory_region_add_subregion(region, offset, subregion) Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- hw/arm/xlnx-versal-virt.c | 3 +-- hw/arm/xlnx-versal.c | 4 ++-- 2 files changed, 3 insertions(+), 4 deletions(-) diff --git a/hw/arm/xlnx-versal-virt.c b/hw/arm/xlnx-versal-virt.c index 462493c467..901e9ed86c 100644 --- a/hw/arm/xlnx-versal-virt.c +++ b/hw/arm/xlnx-versal-virt.c @@ -437,8 +437,7 @@ static void versal_virt_init(MachineState *machine) =20 /* Make the APU cpu address space visible to virtio and other * modules unaware of muliple address-spaces. */ - memory_region_add_subregion_overlap(get_system_memory(), - 0, &s->soc.fpd.apu.mr, 0); + memory_region_add_subregion(get_system_memory(), 0, &s->soc.fpd.apu.= mr); =20 s->binfo.ram_size =3D machine->ram_size; s->binfo.loader_start =3D 0x0; diff --git a/hw/arm/xlnx-versal.c b/hw/arm/xlnx-versal.c index 8b3d8d85b8..538d907f8a 100644 --- a/hw/arm/xlnx-versal.c +++ b/hw/arm/xlnx-versal.c @@ -281,8 +281,8 @@ static void versal_realize(DeviceState *dev, Error **= errp) memory_region_init_ram(&s->lpd.mr_ocm, OBJECT(s), "ocm", MM_OCM_SIZE, &error_fatal); =20 - memory_region_add_subregion_overlap(&s->mr_ps, MM_OCM, &s->lpd.mr_oc= m, 0); - memory_region_add_subregion_overlap(&s->fpd.apu.mr, 0, &s->mr_ps, 0)= ; + memory_region_add_subregion(&s->mr_ps, MM_OCM, &s->lpd.mr_ocm); + memory_region_add_subregion(&s->fpd.apu.mr, 0, &s->mr_ps); } =20 static void versal_init(Object *obj) --=20 2.21.0 From MAILER-DAEMON Sat Dec 14 15:59:32 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1igEVg-00083c-I1 for mharc-qemu-arm@gnu.org; Sat, 14 Dec 2019 15:59:32 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:42779) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1igEVb-0007ty-QF for qemu-arm@nongnu.org; Sat, 14 Dec 2019 15:59:28 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1igEVa-0007yL-Ak for qemu-arm@nongnu.org; Sat, 14 Dec 2019 15:59:27 -0500 Received: from us-smtp-delivery-1.mimecast.com ([205.139.110.120]:55488 helo=us-smtp-1.mimecast.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1igEVZ-0007vE-Na for qemu-arm@nongnu.org; Sat, 14 Dec 2019 15:59:25 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1576357165; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=Os44yYqV4Qf/DGZHPDswJ/Ob+mUvkJTnaZl2qxMI8rM=; b=SPCmSJimnrpzTIquAWYi2pQq9joNW5EoZIyavca/CeGUJDKp8Wh0DSY4m6DmojZ6vwYLOE hfFCAKHGsxHXxiOhlQqbSWcT6cWCOP6Y4vp34pWa5icyBd2thyv6dFI0/gbmWyPgnWFKHf SG1B2nBvc99DVUqnZ3rsczlxdVuTx5o= Received: from mimecast-mx01.redhat.com (mimecast-mx01.redhat.com [209.132.183.4]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-386-BFIqEERuN2SIx64E6tImNQ-1; Sat, 14 Dec 2019 10:57:11 -0500 X-MC-Unique: BFIqEERuN2SIx64E6tImNQ-1 Received: from smtp.corp.redhat.com (int-mx05.intmail.prod.int.phx2.redhat.com [10.5.11.15]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx01.redhat.com (Postfix) with ESMTPS id 2FB26107ACC4; Sat, 14 Dec 2019 15:57:09 +0000 (UTC) Received: from x1w.redhat.com (ovpn-205-147.brq.redhat.com [10.40.205.147]) by smtp.corp.redhat.com (Postfix) with ESMTPS id E3EC45D6A7; Sat, 14 Dec 2019 15:56:47 +0000 (UTC) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Peter Maydell , Andrew Baumann , Aurelien Jarno , kvm@vger.kernel.org, Alex Williamson , Aleksandar Markovic , Joel Stanley , qemu-arm@nongnu.org, Marcelo Tosatti , Alistair Francis , "Michael S. Tsirkin" , Eduardo Habkost , Richard Henderson , Aleksandar Rikalo , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Paul Burton , Marcel Apfelbaum , "Edgar E. Iglesias" , Paolo Bonzini Subject: [PATCH 2/8] hw/arm/raspi: Use memory_region_add_subregion() when priority is 0 Date: Sat, 14 Dec 2019 16:56:08 +0100 Message-Id: <20191214155614.19004-3-philmd@redhat.com> In-Reply-To: <20191214155614.19004-1-philmd@redhat.com> References: <20191214155614.19004-1-philmd@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 X-Scanned-By: MIMEDefang 2.79 on 10.5.11.15 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 205.139.110.120 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sat, 14 Dec 2019 20:59:29 -0000 It is pointless to overlap a memory subregion with priority 0. Use the simpler memory_region_add_subregion() function. This patch was produced with the following spatch script: @@ expression region; expression offset; expression subregion; @@ -memory_region_add_subregion_overlap(region, offset, subregion, 0) +memory_region_add_subregion(region, offset, subregion) Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- hw/arm/bcm2835_peripherals.c | 4 ++-- hw/arm/raspi.c | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/hw/arm/bcm2835_peripherals.c b/hw/arm/bcm2835_peripherals.c index 17207ae07e..f792bd6bb1 100644 --- a/hw/arm/bcm2835_peripherals.c +++ b/hw/arm/bcm2835_peripherals.c @@ -160,8 +160,8 @@ static void bcm2835_peripherals_realize(DeviceState *= dev, Error **errp) for (n =3D 0; n < 4; n++) { memory_region_init_alias(&s->ram_alias[n], OBJECT(s), "bcm2835-gpu-ram-alias[*]", ram, 0, ram= _size); - memory_region_add_subregion_overlap(&s->gpu_bus_mr, (hwaddr)n <<= 30, - &s->ram_alias[n], 0); + memory_region_add_subregion(&s->gpu_bus_mr, (hwaddr)n << 30, + &s->ram_alias[n]); } =20 /* Interrupt Controller */ diff --git a/hw/arm/raspi.c b/hw/arm/raspi.c index 6a510aafc1..3649b75449 100644 --- a/hw/arm/raspi.c +++ b/hw/arm/raspi.c @@ -187,7 +187,7 @@ static void raspi_init(MachineState *machine, int ver= sion) memory_region_allocate_system_memory(&s->ram, OBJECT(machine), "ram"= , machine->ram_size); /* FIXME: Remove when we have custom CPU address space support */ - memory_region_add_subregion_overlap(get_system_memory(), 0, &s->ram,= 0); + memory_region_add_subregion(get_system_memory(), 0, &s->ram); =20 /* Setup the SOC */ object_property_add_const_link(OBJECT(&s->soc), "ram", OBJECT(&s->ra= m), --=20 2.21.0 From MAILER-DAEMON Sat Dec 14 16:00:08 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1igEWG-0000Qs-Fu for mharc-qemu-arm@gnu.org; Sat, 14 Dec 2019 16:00:08 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:55464) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1igEWC-0000Ni-SB for qemu-arm@nongnu.org; Sat, 14 Dec 2019 16:00:06 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1igEWB-0001aC-GF for qemu-arm@nongnu.org; Sat, 14 Dec 2019 16:00:04 -0500 Received: from us-smtp-1.mimecast.com ([207.211.31.81]:26853) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1igEWB-0001XD-5m for qemu-arm@nongnu.org; Sat, 14 Dec 2019 16:00:03 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1576357202; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=1cebHdve3ZnvlZJWxH5a8KchlZuVrxNjKmx0NHd8T+o=; b=AOZSTBzPMR+g53eBKaMsby9yOBMukc9O+tFR5tZBwSq2cRuw1ceadAExwh6FLC3W5lLj7w DN7irXVhR6dGOUqXhvgvEozT5etBtJGVQ8iCoFh99xlMAKwUkaoUM7EPuM65P6ilquUWsA F8NeMDH5gmuGet5A4ATa4CGApKHsxL4= Received: from mimecast-mx01.redhat.com (mimecast-mx01.redhat.com [209.132.183.4]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-30-FmV6NzRAPFqS56q6qZWsiQ-1; Sat, 14 Dec 2019 10:58:07 -0500 X-MC-Unique: FmV6NzRAPFqS56q6qZWsiQ-1 Received: from smtp.corp.redhat.com (int-mx05.intmail.prod.int.phx2.redhat.com [10.5.11.15]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx01.redhat.com (Postfix) with ESMTPS id 74DD11005502; Sat, 14 Dec 2019 15:58:05 +0000 (UTC) Received: from x1w.redhat.com (ovpn-205-147.brq.redhat.com [10.40.205.147]) by smtp.corp.redhat.com (Postfix) with ESMTPS id 7DCAF5D6A7; Sat, 14 Dec 2019 15:57:57 +0000 (UTC) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Peter Maydell , Andrew Baumann , Aurelien Jarno , kvm@vger.kernel.org, Alex Williamson , Aleksandar Markovic , Joel Stanley , qemu-arm@nongnu.org, Marcelo Tosatti , Alistair Francis , "Michael S. Tsirkin" , Eduardo Habkost , Richard Henderson , Aleksandar Rikalo , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Paul Burton , Marcel Apfelbaum , "Edgar E. Iglesias" , Paolo Bonzini Subject: [PATCH 7/8] target/i386: Use memory_region_add_subregion() when priority is 0 Date: Sat, 14 Dec 2019 16:56:13 +0100 Message-Id: <20191214155614.19004-8-philmd@redhat.com> In-Reply-To: <20191214155614.19004-1-philmd@redhat.com> References: <20191214155614.19004-1-philmd@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 X-Scanned-By: MIMEDefang 2.79 on 10.5.11.15 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 207.211.31.81 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sat, 14 Dec 2019 21:00:06 -0000 It is pointless to overlap a memory subregion with priority 0. Use the simpler memory_region_add_subregion() function. This patch was produced with the following spatch script: @@ expression region; expression offset; expression subregion; @@ -memory_region_add_subregion_overlap(region, offset, subregion, 0) +memory_region_add_subregion(region, offset, subregion) Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- target/i386/cpu.c | 2 +- target/i386/kvm.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 69f518a21a..6131c62f9d 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -6483,7 +6483,7 @@ static void x86_cpu_realizefn(DeviceState *dev, Err= or **errp) */ memory_region_init_alias(cpu->cpu_as_mem, OBJECT(cpu), "memory", get_system_memory(), 0, ~0ull); - memory_region_add_subregion_overlap(cpu->cpu_as_root, 0, cpu->cp= u_as_mem, 0); + memory_region_add_subregion(cpu->cpu_as_root, 0, cpu->cpu_as_mem= ); memory_region_set_enabled(cpu->cpu_as_mem, true); =20 cs->num_ases =3D 2; diff --git a/target/i386/kvm.c b/target/i386/kvm.c index 1d10046a6c..4e1ba9d474 100644 --- a/target/i386/kvm.c +++ b/target/i386/kvm.c @@ -2081,7 +2081,7 @@ static void register_smram_listener(Notifier *n, vo= id *unused) */ memory_region_init_alias(&smram_as_mem, OBJECT(kvm_state), "mem-smra= m", get_system_memory(), 0, ~0ull); - memory_region_add_subregion_overlap(&smram_as_root, 0, &smram_as_mem= , 0); + memory_region_add_subregion(&smram_as_root, 0, &smram_as_mem); memory_region_set_enabled(&smram_as_mem, true); =20 if (smram) { --=20 2.21.0 From MAILER-DAEMON Sat Dec 14 16:00:09 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1igEWH-0000Rm-0G for mharc-qemu-arm@gnu.org; Sat, 14 Dec 2019 16:00:09 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:55380) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1igEWC-0000Na-JD for qemu-arm@nongnu.org; Sat, 14 Dec 2019 16:00:05 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1igEWB-0001ZY-B5 for qemu-arm@nongnu.org; Sat, 14 Dec 2019 16:00:04 -0500 Received: from us-smtp-1.mimecast.com ([207.211.31.81]:57808) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1igEWB-0001X1-2P for qemu-arm@nongnu.org; Sat, 14 Dec 2019 16:00:03 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1576357202; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=LRDNXmBjVfes+8mRt7KTS+s8kaJK3nwCAodGqedjxW4=; b=U6Ysk7CKH3hnQSV3zJWl3yLKj3sVtG733qDWXIrnk5CmeawZKj+Ke3NPwIgCXuidUG11wi +sjo6L+vbJ0OmgBoKIAewndNW6tONejicWCHSBGPdXbwckM+7qrOxJ+Cmvvwu9OFZa2q6m WDFxvQE8rq1L1yGj+ZCv+DeSQYGqWzY= Received: from mimecast-mx01.redhat.com (mimecast-mx01.redhat.com [209.132.183.4]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-271-InHhu3ggMleXW3tOq5yXNw-1; Sat, 14 Dec 2019 10:57:59 -0500 X-MC-Unique: InHhu3ggMleXW3tOq5yXNw-1 Received: from smtp.corp.redhat.com (int-mx05.intmail.prod.int.phx2.redhat.com [10.5.11.15]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx01.redhat.com (Postfix) with ESMTPS id C1EA11852E2D; Sat, 14 Dec 2019 15:57:56 +0000 (UTC) Received: from x1w.redhat.com (ovpn-205-147.brq.redhat.com [10.40.205.147]) by smtp.corp.redhat.com (Postfix) with ESMTPS id 88D2B5D6A7; Sat, 14 Dec 2019 15:57:42 +0000 (UTC) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Peter Maydell , Andrew Baumann , Aurelien Jarno , kvm@vger.kernel.org, Alex Williamson , Aleksandar Markovic , Joel Stanley , qemu-arm@nongnu.org, Marcelo Tosatti , Alistair Francis , "Michael S. Tsirkin" , Eduardo Habkost , Richard Henderson , Aleksandar Rikalo , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Paul Burton , Marcel Apfelbaum , "Edgar E. Iglesias" , Paolo Bonzini Subject: [PATCH 6/8] hw/vfio/pci: Use memory_region_add_subregion() when priority is 0 Date: Sat, 14 Dec 2019 16:56:12 +0100 Message-Id: <20191214155614.19004-7-philmd@redhat.com> In-Reply-To: <20191214155614.19004-1-philmd@redhat.com> References: <20191214155614.19004-1-philmd@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 X-Scanned-By: MIMEDefang 2.79 on 10.5.11.15 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 207.211.31.81 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sat, 14 Dec 2019 21:00:06 -0000 It is pointless to overlap a memory subregion with priority 0. Use the simpler memory_region_add_subregion() function. This patch was produced with the following spatch script: @@ expression region; expression offset; expression subregion; @@ -memory_region_add_subregion_overlap(region, offset, subregion, 0) +memory_region_add_subregion(region, offset, subregion) Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- hw/vfio/pci.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/hw/vfio/pci.c b/hw/vfio/pci.c index 2d40b396f2..74b1eb7ddc 100644 --- a/hw/vfio/pci.c +++ b/hw/vfio/pci.c @@ -1095,8 +1095,7 @@ static void vfio_sub_page_bar_update_mapping(PCIDev= ice *pdev, int bar) memory_region_set_size(mmap_mr, size); if (size !=3D vdev->bars[bar].size && memory_region_is_mapped(base_m= r)) { memory_region_del_subregion(r->address_space, base_mr); - memory_region_add_subregion_overlap(r->address_space, - bar_addr, base_mr, 0); + memory_region_add_subregion(r->address_space, bar_addr, base_mr)= ; } =20 memory_region_transaction_commit(); --=20 2.21.0 From MAILER-DAEMON Sat Dec 14 16:00:09 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1igEWH-0000SK-Mc for mharc-qemu-arm@gnu.org; Sat, 14 Dec 2019 16:00:09 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:55530) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1igEWD-0000Nq-3Q for qemu-arm@nongnu.org; Sat, 14 Dec 2019 16:00:06 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1igEWB-0001aB-FY for qemu-arm@nongnu.org; Sat, 14 Dec 2019 16:00:04 -0500 Received: from us-smtp-delivery-1.mimecast.com ([207.211.31.120]:45844 helo=us-smtp-1.mimecast.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1igEWB-0001WB-5S for qemu-arm@nongnu.org; Sat, 14 Dec 2019 16:00:03 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1576357202; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=LVY3k3PXmSJpFd+itDbLg545Lfy8MyLnQ8WHFK1FOqU=; b=HcCFqXiHdYLJtC3TlOlDcgG04EeX+VORp7/uhRWYY9niDo/mBjCj6mUw0fCjNM5S9Ilroc TeLY110yfKf3+Mk4rAEbkWhaZ67Y8mEU7Pz6DVxhZsxACvbUSPfszfDTYCRrP9BIUnPcOG Uze2u+Qkgk1pgtG99P3VkLM1IlD0jOk= Received: from mimecast-mx01.redhat.com (mimecast-mx01.redhat.com [209.132.183.4]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-379-izlcFJRFOTCG14SMImFy1g-1; Sat, 14 Dec 2019 10:57:43 -0500 X-MC-Unique: izlcFJRFOTCG14SMImFy1g-1 Received: from smtp.corp.redhat.com (int-mx05.intmail.prod.int.phx2.redhat.com [10.5.11.15]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx01.redhat.com (Postfix) with ESMTPS id BBADE107ACC4; Sat, 14 Dec 2019 15:57:41 +0000 (UTC) Received: from x1w.redhat.com (ovpn-205-147.brq.redhat.com [10.40.205.147]) by smtp.corp.redhat.com (Postfix) with ESMTPS id 04D3D5D6A7; Sat, 14 Dec 2019 15:57:32 +0000 (UTC) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Peter Maydell , Andrew Baumann , Aurelien Jarno , kvm@vger.kernel.org, Alex Williamson , Aleksandar Markovic , Joel Stanley , qemu-arm@nongnu.org, Marcelo Tosatti , Alistair Francis , "Michael S. Tsirkin" , Eduardo Habkost , Richard Henderson , Aleksandar Rikalo , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Paul Burton , Marcel Apfelbaum , "Edgar E. Iglesias" , Paolo Bonzini Subject: [PATCH 5/8] hw/mips/boston: Use memory_region_add_subregion() when priority is 0 Date: Sat, 14 Dec 2019 16:56:11 +0100 Message-Id: <20191214155614.19004-6-philmd@redhat.com> In-Reply-To: <20191214155614.19004-1-philmd@redhat.com> References: <20191214155614.19004-1-philmd@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 X-Scanned-By: MIMEDefang 2.79 on 10.5.11.15 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 207.211.31.120 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sat, 14 Dec 2019 21:00:07 -0000 It is pointless to overlap a memory subregion with priority 0. Use the simpler memory_region_add_subregion() function. This patch was produced with the following spatch script: @@ expression region; expression offset; expression subregion; @@ -memory_region_add_subregion_overlap(region, offset, subregion, 0) +memory_region_add_subregion(region, offset, subregion) Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- hw/mips/boston.c | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/hw/mips/boston.c b/hw/mips/boston.c index ca7d813a52..a27258b4d1 100644 --- a/hw/mips/boston.c +++ b/hw/mips/boston.c @@ -412,10 +412,10 @@ xilinx_pcie_init(MemoryRegion *sys_mem, uint32_t bu= s_nr, qdev_init_nofail(dev); =20 cfg =3D sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0); - memory_region_add_subregion_overlap(sys_mem, cfg_base, cfg, 0); + memory_region_add_subregion(sys_mem, cfg_base, cfg); =20 mmio =3D sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 1); - memory_region_add_subregion_overlap(sys_mem, 0, mmio, 0); + memory_region_add_subregion(sys_mem, 0, mmio); =20 qdev_connect_gpio_out_named(dev, "interrupt_out", 0, irq); =20 @@ -471,17 +471,17 @@ static void boston_mach_init(MachineState *machine) =20 flash =3D g_new(MemoryRegion, 1); memory_region_init_rom(flash, NULL, "boston.flash", 128 * MiB, &err)= ; - memory_region_add_subregion_overlap(sys_mem, 0x18000000, flash, 0); + memory_region_add_subregion(sys_mem, 0x18000000, flash); =20 ddr =3D g_new(MemoryRegion, 1); memory_region_allocate_system_memory(ddr, NULL, "boston.ddr", machine->ram_size); - memory_region_add_subregion_overlap(sys_mem, 0x80000000, ddr, 0); + memory_region_add_subregion(sys_mem, 0x80000000, ddr); =20 ddr_low_alias =3D g_new(MemoryRegion, 1); memory_region_init_alias(ddr_low_alias, NULL, "boston_low.ddr", ddr, 0, MIN(machine->ram_size, (256 * MiB))= ); - memory_region_add_subregion_overlap(sys_mem, 0, ddr_low_alias, 0); + memory_region_add_subregion(sys_mem, 0, ddr_low_alias); =20 xilinx_pcie_init(sys_mem, 0, 0x10000000, 32 * MiB, @@ -501,7 +501,7 @@ static void boston_mach_init(MachineState *machine) platreg =3D g_new(MemoryRegion, 1); memory_region_init_io(platreg, NULL, &boston_platreg_ops, s, "boston-platregs", 0x1000); - memory_region_add_subregion_overlap(sys_mem, 0x17ffd000, platreg, 0)= ; + memory_region_add_subregion(sys_mem, 0x17ffd000, platreg); =20 s->uart =3D serial_mm_init(sys_mem, 0x17ffe000, 2, get_cps_irq(&s->cps, 3), 10000000, @@ -509,7 +509,7 @@ static void boston_mach_init(MachineState *machine) =20 lcd =3D g_new(MemoryRegion, 1); memory_region_init_io(lcd, NULL, &boston_lcd_ops, s, "boston-lcd", 0= x8); - memory_region_add_subregion_overlap(sys_mem, 0x17fff000, lcd, 0); + memory_region_add_subregion(sys_mem, 0x17fff000, lcd); =20 chr =3D qemu_chr_new("lcd", "vc:320x240", NULL); qemu_chr_fe_init(&s->lcd_display, chr, NULL); --=20 2.21.0 From MAILER-DAEMON Sat Dec 14 16:00:16 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1igEWN-0000XB-Ii for mharc-qemu-arm@gnu.org; Sat, 14 Dec 2019 16:00:15 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:56971) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1igEWI-0000Ti-Ku for qemu-arm@nongnu.org; Sat, 14 Dec 2019 16:00:12 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1igEWH-0001rO-GJ for qemu-arm@nongnu.org; Sat, 14 Dec 2019 16:00:10 -0500 Received: from us-smtp-delivery-1.mimecast.com ([207.211.31.120]:45942 helo=us-smtp-1.mimecast.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1igEWG-0001nY-HO for qemu-arm@nongnu.org; Sat, 14 Dec 2019 16:00:08 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1576357208; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=7SlorlqSNo6p31H7HgBYKxDoBhr5Y5T4+whsDnKxCwo=; b=UL7imkA/BKwGRVDgJT5IiD8P0Y9c1twCKg4fi/XlPKlqwGun78/+sw8+i21+mJBwHfYQmG wdsVS32BRw69tThNncfZDsvWxc4TjdebRlIrrR5Ar4cSzErynzhg26Jp1IJWOfvVU8OHCb I6VlBmczFRegk1dQmJ1Qbi/Euuheu9I= Received: from mimecast-mx01.redhat.com (mimecast-mx01.redhat.com [209.132.183.4]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-245-uNUZ_QilNLChRElt76KaAQ-1; Sat, 14 Dec 2019 10:57:34 -0500 X-MC-Unique: uNUZ_QilNLChRElt76KaAQ-1 Received: from smtp.corp.redhat.com (int-mx05.intmail.prod.int.phx2.redhat.com [10.5.11.15]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx01.redhat.com (Postfix) with ESMTPS id 61F701852E2A; Sat, 14 Dec 2019 15:57:32 +0000 (UTC) Received: from x1w.redhat.com (ovpn-205-147.brq.redhat.com [10.40.205.147]) by smtp.corp.redhat.com (Postfix) with ESMTPS id 0764F5D6A7; Sat, 14 Dec 2019 15:57:19 +0000 (UTC) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Peter Maydell , Andrew Baumann , Aurelien Jarno , kvm@vger.kernel.org, Alex Williamson , Aleksandar Markovic , Joel Stanley , qemu-arm@nongnu.org, Marcelo Tosatti , Alistair Francis , "Michael S. Tsirkin" , Eduardo Habkost , Richard Henderson , Aleksandar Rikalo , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Paul Burton , Marcel Apfelbaum , "Edgar E. Iglesias" , Paolo Bonzini Subject: [PATCH 4/8] hw/i386/intel_iommu: Use memory_region_add_subregion when priority is 0 Date: Sat, 14 Dec 2019 16:56:10 +0100 Message-Id: <20191214155614.19004-5-philmd@redhat.com> In-Reply-To: <20191214155614.19004-1-philmd@redhat.com> References: <20191214155614.19004-1-philmd@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 X-Scanned-By: MIMEDefang 2.79 on 10.5.11.15 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 207.211.31.120 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sat, 14 Dec 2019 21:00:12 -0000 It is pointless to overlap a memory subregion with priority 0. Use the simpler memory_region_add_subregion() function. This patch was produced with the following spatch script: @@ expression region; expression offset; expression subregion; @@ -memory_region_add_subregion_overlap(region, offset, subregion, 0) +memory_region_add_subregion(region, offset, subregion) Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- hw/i386/intel_iommu.c | 11 ++++------- 1 file changed, 4 insertions(+), 7 deletions(-) diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c index 43c94b993b..afa7e07b05 100644 --- a/hw/i386/intel_iommu.c +++ b/hw/i386/intel_iommu.c @@ -3363,11 +3363,9 @@ VTDAddressSpace *vtd_find_add_as(IntelIOMMUState *= s, PCIBus *bus, int devfn) * switch between DMAR & noDMAR by enable/disable * corresponding sub-containers */ - memory_region_add_subregion_overlap(&vtd_dev_as->root, 0, - MEMORY_REGION(&vtd_dev_as->i= ommu), - 0); - memory_region_add_subregion_overlap(&vtd_dev_as->root, 0, - &vtd_dev_as->nodmar, 0); + memory_region_add_subregion(&vtd_dev_as->root, 0, + MEMORY_REGION(&vtd_dev_as->iommu)); + memory_region_add_subregion(&vtd_dev_as->root, 0, &vtd_dev_as->n= odmar); =20 vtd_switch_address_space(vtd_dev_as); } @@ -3764,8 +3762,7 @@ static void vtd_realize(DeviceState *dev, Error **e= rrp) memory_region_init_alias(&s->mr_sys_alias, OBJECT(s), "vtd-sys-alias", get_system_memory(), 0, memory_region_size(get_system_memory())); - memory_region_add_subregion_overlap(&s->mr_nodmar, 0, - &s->mr_sys_alias, 0); + memory_region_add_subregion(&s->mr_nodmar, 0, &s->mr_sys_alias); memory_region_add_subregion_overlap(&s->mr_nodmar, VTD_INTERRUPT_ADDR_FIRST, &s->mr_ir, 1); --=20 2.21.0 From MAILER-DAEMON Sat Dec 14 16:01:06 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1igEXC-0001WN-Hr for mharc-qemu-arm@gnu.org; Sat, 14 Dec 2019 16:01:06 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:45568) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1igEXA-0001T3-2e for qemu-arm@nongnu.org; Sat, 14 Dec 2019 16:01:05 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1igEX8-0004dW-R1 for qemu-arm@nongnu.org; Sat, 14 Dec 2019 16:01:03 -0500 Received: from us-smtp-delivery-1.mimecast.com ([205.139.110.120]:40287 helo=us-smtp-1.mimecast.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1igEX8-0004c0-Ma for qemu-arm@nongnu.org; Sat, 14 Dec 2019 16:01:02 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1576357262; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=joKcrZqse/2rI2WBzidhVM6HneRljCD0MWlkHrQCOPM=; b=JpYlYY6GRr4O0aBKfZh5xMh4bbcZqDw4STW6G34dRxb9pxZk+AL18Fs6ADiuyMhTvTGksy K/Vsyq+z6LG8DVY85o5/g4tYqvuFbK5mj0W3uF+riFG4gYL8JC5SjddIn9prLEzMBP/WV1 qWPSghjMVN8rpWnX3zzKVMY8VZNjpCc= Received: from mail-wr1-f69.google.com (mail-wr1-f69.google.com [209.85.221.69]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-144-U4Ulz7HVPYCnwlkewFBVHQ-1; Sat, 14 Dec 2019 08:59:54 -0500 Received: by mail-wr1-f69.google.com with SMTP id 90so1014979wrq.6 for ; Sat, 14 Dec 2019 05:59:54 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:subject:to:cc:references:from:message-id:date :user-agent:mime-version:in-reply-to:content-language :content-transfer-encoding; bh=8ablovXuvhNSxsWx83+/G5FRg33eclyz++hORIZtpqw=; b=ZtMtuBaWAyLYjUelDxEqkbNC7Fn4qb7rys/rt8tmEuDTn+W5q6As4IABKmOyx43wVd S4UGqzDYs5GRr8s3k+goi1c5dLf1z4BrcVn0jcOPLb3uLPXgVvMC/VOrXciYGEU+xLxd pJsqfJ4eKxLepQPsye6/kdhLU6bYrICjFMr1OLKXyPq+0pNQjovOs7QJTFqFoAuFs3gH nnGh579qU0GFBs7NfG8jganFB3kBlzsx04eco3ct5iKr6ShCzAXLEsvh2nU6ytKWZbPA Ajyssrv576birJjXzZ1QNMCoWSrdkz0uH4m3oKIcU0vPTuK3U/VGDF18cmaFeb0qT7kf +d6Q== X-Gm-Message-State: APjAAAUibtDVP6LZs8YueFMnFRxKiEmyluvS+46HpSmfVUVTxTqMDf5r 7QuHm4TSyi3+x/m1tf7aGhwRkYsmjgTuBCwmsldVgcTkPys8RV9/70knklxj6L7Gkh+yTYblsU7 i/qMOrTjQX8Ia X-Received: by 2002:a05:600c:54b:: with SMTP id k11mr19359951wmc.63.1576331993073; Sat, 14 Dec 2019 05:59:53 -0800 (PST) X-Google-Smtp-Source: APXvYqwrx5HZOidI8oSBXFDAPClc+5D4C097hsRHKYDeM6nDsPjp5XZzhTAKSDZLvYNqNkzmNjJtHw== X-Received: by 2002:a05:600c:54b:: with SMTP id k11mr19359939wmc.63.1576331992865; Sat, 14 Dec 2019 05:59:52 -0800 (PST) Received: from [192.168.1.35] (34.red-83-42-66.dynamicip.rima-tde.net. [83.42.66.34]) by smtp.gmail.com with ESMTPSA id u10sm13781029wmd.1.2019.12.14.05.59.51 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Sat, 14 Dec 2019 05:59:52 -0800 (PST) Subject: Re: [PATCH 09/10] arm: allwinner-h3: add SD/MMC host controller To: Niek Linnenbank Cc: QEMU Developers , qemu-arm , Peter Maydell , Beniamino Galvani References: <20191202210947.3603-1-nieklinnenbank@gmail.com> <20191202210947.3603-10-nieklinnenbank@gmail.com> <6bee15d7-7d80-0709-ac90-ef2052b39329@redhat.com> From: =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= Message-ID: <457e0620-c11e-8e5a-df1c-93f95f52eda8@redhat.com> Date: Sat, 14 Dec 2019 14:59:51 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.2.2 MIME-Version: 1.0 In-Reply-To: Content-Language: en-US X-MC-Unique: U4Ulz7HVPYCnwlkewFBVHQ-1 X-Mimecast-Spam-Score: 0 Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 205.139.110.120 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sat, 14 Dec 2019 21:01:06 -0000 On 12/13/19 10:00 PM, Niek Linnenbank wrote: > On Fri, Dec 13, 2019 at 12:56 AM Philippe Mathieu-Daud=C3=A9=20 > > wrote: >=20 > Hi Niek, >=20 > On 12/11/19 11:34 PM, Niek Linnenbank wrote: > > Ping! > > > > Anyone would like to comment on this driver? > > > > I finished the rework on all previous comments in this series. > > > > Currently debugging the hflags error reported by Philippe. > > After that, I'm ready to send out v2 of these patches. > > > > Regards, > > Niek > > > > On Mon, Dec 2, 2019 at 10:10 PM Niek Linnenbank > > > >> > wrote: > > > >=C2=A0 =C2=A0 =C2=A0The Allwinner H3 System on Chip contains an int= egrated storage > >=C2=A0 =C2=A0 =C2=A0controller for Secure Digital (SD) and Multi Me= dia Card (MMC) > >=C2=A0 =C2=A0 =C2=A0interfaces. This commit adds support for the Al= lwinner H3 > >=C2=A0 =C2=A0 =C2=A0SD/MMC storage controller with the following em= ulated features: > > > >=C2=A0 =C2=A0 =C2=A0 =C2=A0* DMA transfers > >=C2=A0 =C2=A0 =C2=A0 =C2=A0* Direct FIFO I/O > >=C2=A0 =C2=A0 =C2=A0 =C2=A0* Short/Long format command responses > >=C2=A0 =C2=A0 =C2=A0 =C2=A0* Auto-Stop command (CMD12) > >=C2=A0 =C2=A0 =C2=A0 =C2=A0* Insert & remove card detection > > > >=C2=A0 =C2=A0 =C2=A0Signed-off-by: Niek Linnenbank > >=C2=A0 =C2=A0 =C2=A0 >> > >=C2=A0 =C2=A0 =C2=A0--- > >=C2=A0 =C2=A0 =C2=A0 =C2=A0hw/arm/allwinner-h3.c=C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0|=C2=A0 20 + > >=C2=A0 =C2=A0 =C2=A0 =C2=A0hw/arm/orangepi.c=C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0|=C2=A0 17 + > >=C2=A0 =C2=A0 =C2=A0 =C2=A0hw/sd/Makefile.objs=C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0|=C2=A0 =C2=A01 + > >=C2=A0 =C2=A0 =C2=A0 =C2=A0hw/sd/allwinner-h3-sdhost.c=C2=A0 =C2=A0= =C2=A0 =C2=A0 =C2=A0| 791 > ++++++++++++++++++++++++++++ > >=C2=A0 =C2=A0 =C2=A0 =C2=A0hw/sd/trace-events=C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 |=C2=A0 =C2=A07 + > >=C2=A0 =C2=A0 =C2=A0 =C2=A0include/hw/arm/allwinner-h3.h=C2=A0 =C2= =A0 =C2=A0 =C2=A0|=C2=A0 =C2=A02 + > >=C2=A0 =C2=A0 =C2=A0 =C2=A0include/hw/sd/allwinner-h3-sdhost.h |=C2= =A0 73 +++ > >=C2=A0 =C2=A0 =C2=A0 =C2=A07 files changed, 911 insertions(+) > >=C2=A0 =C2=A0 =C2=A0 =C2=A0create mode 100644 hw/sd/allwinner-h3-sd= host.c > >=C2=A0 =C2=A0 =C2=A0 =C2=A0create mode 100644 include/hw/sd/allwinn= er-h3-sdhost.h [...] > Thanks again for all of your helpful comments Philippe! > I've started to rework the patch. >=20 > One question about adding tags in the commit message: should I > already add 'Reviewed-by: ' when I re-send v2 of this patch? Or should > that be added after you have seen the v2 changes? You shouldn't add the Reviewed-by tag until explicitly given by the=20 reviewer. If the changes are trivial, it is easy to conditionally give=20 the tag such "If ... is done: R-b", "With ... fixed: R-b". Since this is your first contribution, I have been more careful. Also=20 since your patch is already of very good quality, I'v been a bit picky=20 regarding few details. Since there are too many comments, so I prefer to fully review the v2 of=20 this patch again. Regards, Phil. From MAILER-DAEMON Sat Dec 14 16:01:30 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1igEXa-0001yZ-6E for mharc-qemu-arm@gnu.org; Sat, 14 Dec 2019 16:01:30 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:52850) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1igEXX-0001v6-9x for qemu-arm@nongnu.org; Sat, 14 Dec 2019 16:01:28 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1igEXV-0005jn-9s for qemu-arm@nongnu.org; Sat, 14 Dec 2019 16:01:27 -0500 Received: from mail-il1-x144.google.com ([2607:f8b0:4864:20::144]:35622) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1igEXP-0005Qs-Rr; Sat, 14 Dec 2019 16:01:20 -0500 Received: by mail-il1-x144.google.com with SMTP id g12so2391745ild.2; Sat, 14 Dec 2019 13:01:19 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=sXWObjGl6OXDF8vN7Nqi0HgJ+038kWVON6shVGrmC1c=; b=CkInd3WLl4a51MtgtS6zQTWZ7yMlPbWRXrd3iJUTv5NfUuPuapCJ4p0fgebx77p6Yh L9c1mEhLw0aMf5ay7e7ukJghXAaiDmBoYW5XsAYiJoLQM3HimU/MxtkVVPyzP0ZFczHu wSaXXGvUeKjpfuua7BHoB8Q86l/E7AgqJ51SwAMlX7AkmDn7Xevsz6UohOWxtU+OMbVf kkesjzw3qYmczaLkLsqX2B6guPS1LRuRu0wHe35yZrFMUJ4vK2OfBOABj6FXxuZwFIgP 6+Bex16D0CGOnsiB9+BOp6wz6cnyywlRzg7o1eSdrXW8S0uslujVq+tfR1dVkpQSvzo/ zzqg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=sXWObjGl6OXDF8vN7Nqi0HgJ+038kWVON6shVGrmC1c=; b=CL7ZYI4i/uYP5DostDVPb44Vv1dziospi2Q/tM9DOoPB65GTfn5+mVpLIrHmQ/Pcwu HZzsHurXWXNpgbPfxmNUKCekHQbaJrKE2GaMLd/r7BcQz2m3kjSyDREHgcKzh+D5ndZe AyGh0z3Tn3REIDWYhR7hjw3MsyZvtYIgwxQoLAyjjMrlwNefAOObPIHKm6ykHA8TVfAM 8I6XUprMj7tUaLucrAoeBrv41we7XjDV8pXxyPxP1SBPpDFPIv3ZwvZuXBJoRaOIebT+ jZN3nGDJi8fTM1m3pFYhqpccMgUw9G19P/ibse1BBDzcXpvwILwyKbZub5une/wBy7NH m/Pw== X-Gm-Message-State: APjAAAW9v56kIoO1tnfumdUwytTqf3Y8RH/c8mESC5OuSrVFnvcyp8Be FfvQQgGlhkSUMP2dZTAy3/7BK6NohklDVfHbVpR6xQ== X-Google-Smtp-Source: APXvYqw8q1mlKhmAF2iTgALI0Y9x9CQqCZmXjzTNgOxbnywffKma10PDNXO+RgCD+gX/HQmLS5s/jZNYLfdCkxPPBXs= X-Received: by 2002:a92:d203:: with SMTP id y3mr5682158ily.28.1576355542949; Sat, 14 Dec 2019 12:32:22 -0800 (PST) MIME-Version: 1.0 References: <20191202210947.3603-1-nieklinnenbank@gmail.com> <20191202210947.3603-10-nieklinnenbank@gmail.com> <6bee15d7-7d80-0709-ac90-ef2052b39329@redhat.com> <457e0620-c11e-8e5a-df1c-93f95f52eda8@redhat.com> In-Reply-To: <457e0620-c11e-8e5a-df1c-93f95f52eda8@redhat.com> From: Niek Linnenbank Date: Sat, 14 Dec 2019 21:32:11 +0100 Message-ID: Subject: Re: [PATCH 09/10] arm: allwinner-h3: add SD/MMC host controller To: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= Cc: QEMU Developers , qemu-arm , Peter Maydell , Beniamino Galvani Content-Type: multipart/alternative; boundary="0000000000002d63fc0599afe013" X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::144 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sat, 14 Dec 2019 21:01:29 -0000 --0000000000002d63fc0599afe013 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable On Sat, Dec 14, 2019 at 2:59 PM Philippe Mathieu-Daud=C3=A9 wrote: > On 12/13/19 10:00 PM, Niek Linnenbank wrote: > > On Fri, Dec 13, 2019 at 12:56 AM Philippe Mathieu-Daud=C3=A9 > > > wrote: > > > > Hi Niek, > > > > On 12/11/19 11:34 PM, Niek Linnenbank wrote: > > > Ping! > > > > > > Anyone would like to comment on this driver? > > > > > > I finished the rework on all previous comments in this series. > > > > > > Currently debugging the hflags error reported by Philippe. > > > After that, I'm ready to send out v2 of these patches. > > > > > > Regards, > > > Niek > > > > > > On Mon, Dec 2, 2019 at 10:10 PM Niek Linnenbank > > > > > >= > > > wrote: > > > > > > The Allwinner H3 System on Chip contains an integrated stora= ge > > > controller for Secure Digital (SD) and Multi Media Card (MMC= ) > > > interfaces. This commit adds support for the Allwinner H3 > > > SD/MMC storage controller with the following emulated > features: > > > > > > * DMA transfers > > > * Direct FIFO I/O > > > * Short/Long format command responses > > > * Auto-Stop command (CMD12) > > > * Insert & remove card detection > > > > > > Signed-off-by: Niek Linnenbank > > > > > >> > > > --- > > > hw/arm/allwinner-h3.c | 20 + > > > hw/arm/orangepi.c | 17 + > > > hw/sd/Makefile.objs | 1 + > > > hw/sd/allwinner-h3-sdhost.c | 791 > > ++++++++++++++++++++++++++++ > > > hw/sd/trace-events | 7 + > > > include/hw/arm/allwinner-h3.h | 2 + > > > include/hw/sd/allwinner-h3-sdhost.h | 73 +++ > > > 7 files changed, 911 insertions(+) > > > create mode 100644 hw/sd/allwinner-h3-sdhost.c > > > create mode 100644 include/hw/sd/allwinner-h3-sdhost.h > [...] > > Thanks again for all of your helpful comments Philippe! > > I've started to rework the patch. > > > > One question about adding tags in the commit message: should I > > already add 'Reviewed-by: ' when I re-send v2 of this patch? Or should > > that be added after you have seen the v2 changes? > > You shouldn't add the Reviewed-by tag until explicitly given by the > reviewer. If the changes are trivial, it is easy to conditionally give > the tag such "If ... is done: R-b", "With ... fixed: R-b". > OK, thanks for clarifying, I'll keep that in mind. > > Since this is your first contribution, I have been more careful. Also > since your patch is already of very good quality, I'v been a bit picky > regarding few details. > Sure, that makes sense indeed. And I very much appreciate your feedback Philippe, so please keep doing that, even about the small details ;-) > > Since there are too many comments, so I prefer to fully review the v2 of > this patch again. > > Yes, true indeed. Regards, Niek > Regards, > > Phil. > > --=20 Niek Linnenbank --0000000000002d63fc0599afe013 Content-Type: text/html; charset="UTF-8" Content-Transfer-Encoding: quoted-printable


=
On Sat, Dec 14, 2019 at 2:59 PM Phili= ppe Mathieu-Daud=C3=A9 <philmd@redh= at.com> wrote:
On 12/13/19 10:00 PM, Niek Linnenbank wrote:
> On Fri, Dec 13, 2019 at 12:56 AM Philippe Mathieu-Daud=C3=A9
> <philmd@redh= at.com <mailto:philmd@redhat.com>> wrote:
>
>=C2=A0 =C2=A0 =C2=A0Hi Niek,
>
>=C2=A0 =C2=A0 =C2=A0On 12/11/19 11:34 PM, Niek Linnenbank wrote:
>=C2=A0 =C2=A0 =C2=A0 > Ping!
>=C2=A0 =C2=A0 =C2=A0 >
>=C2=A0 =C2=A0 =C2=A0 > Anyone would like to comment on this driver?<= br> >=C2=A0 =C2=A0 =C2=A0 >
>=C2=A0 =C2=A0 =C2=A0 > I finished the rework on all previous comment= s in this series.
>=C2=A0 =C2=A0 =C2=A0 >
>=C2=A0 =C2=A0 =C2=A0 > Currently debugging the hflags error reported= by Philippe.
>=C2=A0 =C2=A0 =C2=A0 > After that, I'm ready to send out v2 of t= hese patches.
>=C2=A0 =C2=A0 =C2=A0 >
>=C2=A0 =C2=A0 =C2=A0 > Regards,
>=C2=A0 =C2=A0 =C2=A0 > Niek
>=C2=A0 =C2=A0 =C2=A0 >
>=C2=A0 =C2=A0 =C2=A0 > On Mon, Dec 2, 2019 at 10:10 PM Niek Linnenba= nk
>=C2=A0 =C2=A0 =C2=A0 > <nieklinnenbank@gmail.com <mailto:nieklinnenbank@gmail.com>
>=C2=A0 =C2=A0 =C2=A0<mailto:
nieklinnenbank@gmail.com <mailto:nieklinnenbank@gmail.com>>>
>=C2=A0 =C2=A0 =C2=A0wrote:
>=C2=A0 =C2=A0 =C2=A0 >
>=C2=A0 =C2=A0 =C2=A0 >=C2=A0 =C2=A0 =C2=A0The Allwinner H3 System on= Chip contains an integrated storage
>=C2=A0 =C2=A0 =C2=A0 >=C2=A0 =C2=A0 =C2=A0controller for Secure Digi= tal (SD) and Multi Media Card (MMC)
>=C2=A0 =C2=A0 =C2=A0 >=C2=A0 =C2=A0 =C2=A0interfaces. This commit ad= ds support for the Allwinner H3
>=C2=A0 =C2=A0 =C2=A0 >=C2=A0 =C2=A0 =C2=A0SD/MMC storage controller = with the following emulated features:
>=C2=A0 =C2=A0 =C2=A0 >
>=C2=A0 =C2=A0 =C2=A0 >=C2=A0 =C2=A0 =C2=A0 =C2=A0* DMA transfers
>=C2=A0 =C2=A0 =C2=A0 >=C2=A0 =C2=A0 =C2=A0 =C2=A0* Direct FIFO I/O >=C2=A0 =C2=A0 =C2=A0 >=C2=A0 =C2=A0 =C2=A0 =C2=A0* Short/Long format= command responses
>=C2=A0 =C2=A0 =C2=A0 >=C2=A0 =C2=A0 =C2=A0 =C2=A0* Auto-Stop command= (CMD12)
>=C2=A0 =C2=A0 =C2=A0 >=C2=A0 =C2=A0 =C2=A0 =C2=A0* Insert & remo= ve card detection
>=C2=A0 =C2=A0 =C2=A0 >
>=C2=A0 =C2=A0 =C2=A0 >=C2=A0 =C2=A0 =C2=A0Signed-off-by: Niek Linnen= bank <
niek= linnenbank@gmail.com
>=C2=A0 =C2=A0 =C2=A0<mailto:nieklinnenbank@gmail.com>
>=C2=A0 =C2=A0 =C2=A0 >=C2=A0 =C2=A0 =C2=A0<mailto:nieklinnenbank@gmail.com=
>=C2=A0 =C2=A0 =C2=A0<mailto:nieklinnenbank@gmail.com>>>
>=C2=A0 =C2=A0 =C2=A0 >=C2=A0 =C2=A0 =C2=A0---
>=C2=A0 =C2=A0 =C2=A0 >=C2=A0 =C2=A0 =C2=A0 =C2=A0hw/arm/allwinner-h3= .c=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0|=C2=A0 20 +
>=C2=A0 =C2=A0 =C2=A0 >=C2=A0 =C2=A0 =C2=A0 =C2=A0hw/arm/orangepi.c= =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0|=C2= =A0 17 +
>=C2=A0 =C2=A0 =C2=A0 >=C2=A0 =C2=A0 =C2=A0 =C2=A0hw/sd/Makefile.objs= =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0|=C2=A0 =C2= =A01 +
>=C2=A0 =C2=A0 =C2=A0 >=C2=A0 =C2=A0 =C2=A0 =C2=A0hw/sd/allwinner-h3-= sdhost.c=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0| 791
>=C2=A0 =C2=A0 =C2=A0++++++++++++++++++++++++++++
>=C2=A0 =C2=A0 =C2=A0 >=C2=A0 =C2=A0 =C2=A0 =C2=A0hw/sd/trace-events= =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 |=C2=A0 =C2= =A07 +
>=C2=A0 =C2=A0 =C2=A0 >=C2=A0 =C2=A0 =C2=A0 =C2=A0include/hw/arm/allw= inner-h3.h=C2=A0 =C2=A0 =C2=A0 =C2=A0|=C2=A0 =C2=A02 +
>=C2=A0 =C2=A0 =C2=A0 >=C2=A0 =C2=A0 =C2=A0 =C2=A0include/hw/sd/allwi= nner-h3-sdhost.h |=C2=A0 73 +++
>=C2=A0 =C2=A0 =C2=A0 >=C2=A0 =C2=A0 =C2=A0 =C2=A07 files changed, 91= 1 insertions(+)
>=C2=A0 =C2=A0 =C2=A0 >=C2=A0 =C2=A0 =C2=A0 =C2=A0create mode 100644 = hw/sd/allwinner-h3-sdhost.c
>=C2=A0 =C2=A0 =C2=A0 >=C2=A0 =C2=A0 =C2=A0 =C2=A0create mode 100644 = include/hw/sd/allwinner-h3-sdhost.h
[...]
> Thanks again for all of your helpful comments Philippe!
> I've started to rework the patch.
>
> One question about adding tags in the commit message: should I
> already add 'Reviewed-by: ' when I re-send v2 of this patch? O= r should
> that be added after you have seen the v2 changes?

You shouldn't add the Reviewed-by tag until explicitly given by the reviewer. If the changes are trivial, it is easy to conditionally give
the tag such "If ... is done: R-b", "With ... fixed: R-b&quo= t;.

OK, thanks for clarifying, I'll= keep that in mind.
=C2=A0

Since this is your first contribution, I have been more careful. Also
since your patch is already of very good quality, I'v been a bit picky =
regarding few details.
=C2=A0
Sure, that mak= es sense indeed. And I very much appreciate your feedback Philippe,
so please keep doing that, even about the small details ;-)
=C2=A0

Since there are too many comments, so I prefer to fully review the v2 of this patch again.

Yes, true indeed.

Regard= s,
Niek
=C2=A0
Regards,

Phil.



--
Niek Linnenbank

--0000000000002d63fc0599afe013-- From MAILER-DAEMON Sat Dec 14 16:06:01 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1igEbx-0006vX-2e for mharc-qemu-arm@gnu.org; Sat, 14 Dec 2019 16:06:01 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:57182) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1igEbu-0006sc-7M for qemu-arm@nongnu.org; Sat, 14 Dec 2019 16:05:59 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1igEbs-0002Jo-Tq for qemu-arm@nongnu.org; Sat, 14 Dec 2019 16:05:57 -0500 Received: from mail-oi1-x241.google.com ([2607:f8b0:4864:20::241]:45709) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1igEbs-0002Fr-JJ for qemu-arm@nongnu.org; Sat, 14 Dec 2019 16:05:56 -0500 Received: by mail-oi1-x241.google.com with SMTP id v10so2556262oiv.12 for ; Sat, 14 Dec 2019 13:05:56 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc:content-transfer-encoding; bh=RMrXhnl08yOQWoHsGq/Mqy6tAi/gvfJoz02znJajxJM=; b=n2Ba4DCcTtQy+TuObNMMxs6W75KYEp7QP4qYVJefSlzwufoqhGmr69lW7Y0J7nBj53 NuQ+7XCu3ltts5rk+7ISqXvQ3xyzBoPY6Ii6wmrnZM3UxXbr40UU7IwrgC7I0P0bHIJk LTwV/92yIa74Qi+WpqOjSNELSVLjkJo8l/Nv2hzzMIuOVu7bc1WqJQ9RQQTn0yLspap7 QyW9A+TWkC1Dk6x5DPa7YZ1g+4mOuMRqmjU/HiuM+CvZorTbWbibyjYhDe5PZwP7QI7S iw9ROzPqsjxlY9Bn2L+ipJXy1iV/044q866OBk6qd3XVi1zI0nFNmBQEn1oTSPfOw1np f0oA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc:content-transfer-encoding; bh=RMrXhnl08yOQWoHsGq/Mqy6tAi/gvfJoz02znJajxJM=; b=DC05+X7srV3LT3V9COIatw0SA45VoZ2RYcGmIoK0HzIAmazwthbNXI3Nu9tIbp8eDG Msn9hiG25CBqgwxnPwMkqbcbfV7VyWefw5BxKPbgnrI7Q3BFz9/JQWhweMIuDc3Qyycm 3wMcxi3TWy71/osZOUjfw2AjFV7bZTW8qTVex0S7zAdQSz+kfI69Wx0Tl8PQ/jHArzrY DLv7EkRcCDdr5sm6GIGZE7eU7PlLJ4zVPgzDZaYFFgE2p9mIpmFu2cNN9/1tZDSStBjl L1oR8nCUvRmep2pT/y4u6GqWNMXVG+SKF1DXGOuj9/g+wgvs6qNRgxHVNeTcL4PT5Nr4 fhRw== X-Gm-Message-State: APjAAAVPKRi+5N9JbLZNSLGXj7aqPGU9XrCu2XAfDbVQU93a8gHDp0bh jnWn5BcUgUPlPETQqjms5Jd6rcC92x+26pPwwgsycCuQ X-Google-Smtp-Source: APXvYqzzYIkxNYHSaWs+IMMqyvA2I2sxvou+3EOiMc1p3klHz2Q0lFygIlhZJZ4ZtzbhteGwQHNqN3WCW60QXniIRH4= X-Received: by 2002:a05:6808:996:: with SMTP id a22mr8108069oic.146.1576353716975; Sat, 14 Dec 2019 12:01:56 -0800 (PST) MIME-Version: 1.0 References: <20191214155614.19004-1-philmd@redhat.com> <31acb07b-a61b-1bc4-ee6e-faa511745a61@redhat.com> In-Reply-To: <31acb07b-a61b-1bc4-ee6e-faa511745a61@redhat.com> From: Peter Maydell Date: Sat, 14 Dec 2019 20:01:46 +0000 Message-ID: Subject: Re: [PATCH 0/8] Simplify memory_region_add_subregion_overlap(..., priority=0) To: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= Cc: QEMU Developers , Andrew Baumann , Aurelien Jarno , kvm-devel , Alex Williamson , Aleksandar Markovic , Joel Stanley , qemu-arm , Marcelo Tosatti , Alistair Francis , "Michael S. Tsirkin" , Eduardo Habkost , Richard Henderson , Aleksandar Rikalo , Paul Burton , Marcel Apfelbaum , "Edgar E. Iglesias" , Paolo Bonzini Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::241 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sat, 14 Dec 2019 21:05:59 -0000 On Sat, 14 Dec 2019 at 18:17, Philippe Mathieu-Daud=C3=A9 wrote: > Maybe we can a warning if priority=3D0, to force board designers to use > explicit priority (explicit overlap). Priority 0 is fine, it's just one of the possible positive and negative values. I think what ideally we would complain about is where we see an overlap and both the regions involved have the same priority value, because in that case which one the guest sees is implicitly dependent on (I think) which order the subregions were added, which is fragile if we move code around. I'm not sure how easy that is to test for or how much of our existing code violates it, though. thanks -- PMM From MAILER-DAEMON Sat Dec 14 16:19:11 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1igEoh-0004bt-8D for mharc-qemu-arm@gnu.org; Sat, 14 Dec 2019 16:19:11 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:43066) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1igEoe-0004Xj-Gx for qemu-arm@nongnu.org; Sat, 14 Dec 2019 16:19:09 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1igEoc-0007xK-0H for qemu-arm@nongnu.org; Sat, 14 Dec 2019 16:19:07 -0500 Received: from us-smtp-2.mimecast.com ([205.139.110.61]:40883 helo=us-smtp-delivery-1.mimecast.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1igEob-0007v3-Hn for qemu-arm@nongnu.org; Sat, 14 Dec 2019 16:19:05 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1576358344; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=m5w23wgjLipXGOJApBiDuCElbab9paRwQ4431X44oSE=; b=OkJDwmER+eq+RTYEyAOThqKPxXJrHb4RYpkC2QT7zdGkopE9Q58u+sSDVHgTXtrpet218v CXW7uIqpSp+3cfF6YxCHTNpC6ny/H78VYBXKU3YTquxdYEIUZ5FgHBoka5J8JrtQ7sH4zd upSA2teQC19KsjlxQPVUji0Aok4ipzs= Received: from mail-wr1-f71.google.com (mail-wr1-f71.google.com [209.85.221.71]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-235-S3QGdBqYMKGKiBDfZdtuIg-1; Sat, 14 Dec 2019 13:17:27 -0500 Received: by mail-wr1-f71.google.com with SMTP id z14so1276289wrs.4 for ; Sat, 14 Dec 2019 10:17:27 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:subject:to:cc:references:from:message-id:date :user-agent:mime-version:in-reply-to:content-language :content-transfer-encoding; bh=Sg5IoKLUjPL3d9d5tWOmLplt+9UU7U7u3KeGeq6Z2Ro=; b=IVZf1JXvbtMY4AmvwqzpL+Bvok1ej/zYrdnIyfEmpYr0SuaibG4FjndGKgYnsxSBJe Y7uaO3Kkr31/jQ+SHMruGvE+kXkeYXwkj9x/gwz5tqul145A/WGu+I2ubz+RL5+ux33t L44eV/n6px69IuzQyQwECqcMbMYheew0kI+aj7h0ZpTW4MZHegMiRatSLkseA4a1YZyO c6pIbtH36471hjF18OGmEnmzI9Z3UDJhGq9EL6A5iQGWKBqco1FgQElaexDEciMw2dBn 2x+TXKSv5JpA2SDTblAVpsYyTTEuW0KWcVw4fH8myjLqI4g+vNArONO/McTeKgnvsBdn b9Qw== X-Gm-Message-State: APjAAAWFiDIeSKXC/2axDlkcgqoA9b02QF7ZSz/IX02clcW1kpNd7VAB K4/1FKAwsiERAhqYmQLucIDrCxgJ37k5RoIveZ6ZrUPGG4kHClZcEcfafR6ANpkSL5EEG4dL6BD zsUFff3FNMi57 X-Received: by 2002:adf:ea8a:: with SMTP id s10mr19560648wrm.278.1576347446203; Sat, 14 Dec 2019 10:17:26 -0800 (PST) X-Google-Smtp-Source: APXvYqwa4vn4ff+Qn7Yr7sIor5+nJ8HSxrr0XhsEVlpcFJzSQc5WvO7C89H+O/cXVwaqad6m8td6Hw== X-Received: by 2002:adf:ea8a:: with SMTP id s10mr19560619wrm.278.1576347445986; Sat, 14 Dec 2019 10:17:25 -0800 (PST) Received: from [192.168.1.35] (34.red-83-42-66.dynamicip.rima-tde.net. [83.42.66.34]) by smtp.gmail.com with ESMTPSA id n8sm14941968wrx.42.2019.12.14.10.17.23 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Sat, 14 Dec 2019 10:17:25 -0800 (PST) Subject: Re: [PATCH 0/8] Simplify memory_region_add_subregion_overlap(..., priority=0) To: Peter Maydell Cc: QEMU Developers , Andrew Baumann , Aurelien Jarno , kvm-devel , Alex Williamson , Aleksandar Markovic , Joel Stanley , qemu-arm , Marcelo Tosatti , Alistair Francis , "Michael S. Tsirkin" , Eduardo Habkost , Richard Henderson , Aleksandar Rikalo , Paul Burton , Marcel Apfelbaum , "Edgar E. Iglesias" , Paolo Bonzini References: <20191214155614.19004-1-philmd@redhat.com> From: =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= Message-ID: <31acb07b-a61b-1bc4-ee6e-faa511745a61@redhat.com> Date: Sat, 14 Dec 2019 19:17:23 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.2.2 MIME-Version: 1.0 In-Reply-To: Content-Language: en-US X-MC-Unique: S3QGdBqYMKGKiBDfZdtuIg-1 X-Mimecast-Spam-Score: 0 Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 205.139.110.61 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sat, 14 Dec 2019 21:19:09 -0000 On 12/14/19 5:28 PM, Peter Maydell wrote: > On Sat, 14 Dec 2019 at 15:56, Philippe Mathieu-Daud=C3=A9 wrote: >> >> Hi, >> >> In this series we use coccinelle to replace: >> - memory_region_add_subregion_overlap(..., priority=3D0) >> + memory_region_add_subregion(...) >> >> Rationale is the code is easier to read, and reviewers don't >> have to worry about overlapping because it isn't used. >=20 > So our implementation of these two functions makes them > have the same behaviour, but the documentation comments > in memory.h describe them as different: a subregion added > with memory_region_add_subregion() is not supposed to > overlap any other subregion unless that other subregion > was explicitly marked as overlapping. My intention with the > API design here was that using the _overlap() version is > a statement of intent -- this region is *expected* to be > overlapping with some other regions, which hopefully > have a priority set so they go at the right order wrt this one. I didn't notice the documentation differences, now it is clear. > Use of the non-overlap function says "I don't expect this > to overlap". (It doesn't actually assert that it doesn't > overlap because we have some legacy uses, notably > in the x86 PC machines, which do overlap without using > the right function, which we've never tried to tidy up.) >=20 > We used to have some #if-ed out code in memory.c which > was able to detect incorrect overlap, but it got removed > in commit b613597819587. I thought then and still do > that rather than removing code and API distinctions that > allow us to tell if the board code has done something > wrong (unintentional overlap, especially unintentional > overlap at the same priority value) it would be better to > fix the board bugs so we could enable the warnings/asserts... Maybe we can a warning if priority=3D0, to force board designers to use=20 explicit priority (explicit overlap). From MAILER-DAEMON Sat Dec 14 16:39:04 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1igF7w-0005Mg-Pb for mharc-qemu-arm@gnu.org; Sat, 14 Dec 2019 16:39:04 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:56969) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1igF7r-0005Kx-6O for qemu-arm@nongnu.org; Sat, 14 Dec 2019 16:39:00 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1igF7o-0004Zz-HA for qemu-arm@nongnu.org; Sat, 14 Dec 2019 16:38:58 -0500 Received: from mail-ot1-x341.google.com ([2607:f8b0:4864:20::341]:43581) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1igF7n-0004Z9-3N for qemu-arm@nongnu.org; Sat, 14 Dec 2019 16:38:55 -0500 Received: by mail-ot1-x341.google.com with SMTP id p8so3745316oth.10 for ; Sat, 14 Dec 2019 13:38:53 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc:content-transfer-encoding; bh=p9TiU/p3iswBYZrdHpdDNv4k35V7tGo3wIsIIqH6Ut8=; b=UmX267PJ+IKeDMSTN0V3PZv2FHiub2P2r+RC6k05+7qBd3TWpLmfwXUwrcObbEuAKb qdw9Bqt7kVS39SJgc6/Ht5EdxnlQ9tlvmCURQLW/TS56voA0jqE9+W1zvBYee5PcWgl8 C7YbNPvlcrhW8OhFqvBkqRAAwGJuukZAnU8gbwUDMd1HGvciBzCgd1gg9TgaHVLxHaUP zo915ceyznORJxfbYwib2hxkFL0GYEi2xcMJdiNcSP34NePaydSXsxE9hgCF9oMkCiBn hmC2++LOmgEC++diZ7hJAV0piPgpM6ujTg9HuohGHqdGPz+sBcCW3fe0gJJK2Z7ipFAM 8Vxw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc:content-transfer-encoding; bh=p9TiU/p3iswBYZrdHpdDNv4k35V7tGo3wIsIIqH6Ut8=; b=EqLAqYZ0Fsoil4YxwgIwm0E76LELsph5gjJb/boQtrSaikeaFYmVbGknht2Yy2Qhf+ /SrCp68d9oNR9CYDBH55/fW/MQlOaE/cRMz1s2/AOTdFwNV2h04YX+np/ZkEMPDyvkPV YdwN5PDfmTn2XEcbiFpPrGXE0lAlY/UOgfgCVmsAOBGm+RIHcYT0uZaogEgpfs1zDy4w 7bXTByY3Q73H9Kllv/cas8SAktY6n2XyQbkbxfjSwwzcprYrISQxMQ+FNteWqsAs+R8Q 5AoPkPc6Tx4TG5uGdzeGKNL4oJ1MTaKPMWEvFcdAwARrAQ4ysfYQykQJrUlt6t8TOFCw ThiA== X-Gm-Message-State: APjAAAVnlU+li1CF16yTF6syv6//tJ7y5t+Jw71uIO+ESTFA2V/oLzWV i1XHyIxNyAaUm4FAnA6De1o5PWhdGOHlzSaxbUthCNDc X-Google-Smtp-Source: APXvYqy/OPz3AmlE14QgU8VrRdOrCV26Ga9rccZipU0fmod/VFkxGGBRAPL5BNxU9UP3XWDwpKvIUN6iZPAdYPtQvdc= X-Received: by 2002:a9d:4d8a:: with SMTP id u10mr21854614otk.232.1576340900088; Sat, 14 Dec 2019 08:28:20 -0800 (PST) MIME-Version: 1.0 References: <20191214155614.19004-1-philmd@redhat.com> In-Reply-To: <20191214155614.19004-1-philmd@redhat.com> From: Peter Maydell Date: Sat, 14 Dec 2019 16:28:08 +0000 Message-ID: Subject: Re: [PATCH 0/8] Simplify memory_region_add_subregion_overlap(..., priority=0) To: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= Cc: QEMU Developers , Andrew Baumann , Aurelien Jarno , kvm-devel , Alex Williamson , Aleksandar Markovic , Joel Stanley , qemu-arm , Marcelo Tosatti , Alistair Francis , "Michael S. Tsirkin" , Eduardo Habkost , Richard Henderson , Aleksandar Rikalo , Paul Burton , Marcel Apfelbaum , "Edgar E. Iglesias" , Paolo Bonzini Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::341 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sat, 14 Dec 2019 21:39:00 -0000 On Sat, 14 Dec 2019 at 15:56, Philippe Mathieu-Daud=C3=A9 wrote: > > Hi, > > In this series we use coccinelle to replace: > - memory_region_add_subregion_overlap(..., priority=3D0) > + memory_region_add_subregion(...) > > Rationale is the code is easier to read, and reviewers don't > have to worry about overlapping because it isn't used. So our implementation of these two functions makes them have the same behaviour, but the documentation comments in memory.h describe them as different: a subregion added with memory_region_add_subregion() is not supposed to overlap any other subregion unless that other subregion was explicitly marked as overlapping. My intention with the API design here was that using the _overlap() version is a statement of intent -- this region is *expected* to be overlapping with some other regions, which hopefully have a priority set so they go at the right order wrt this one. Use of the non-overlap function says "I don't expect this to overlap". (It doesn't actually assert that it doesn't overlap because we have some legacy uses, notably in the x86 PC machines, which do overlap without using the right function, which we've never tried to tidy up.) We used to have some #if-ed out code in memory.c which was able to detect incorrect overlap, but it got removed in commit b613597819587. I thought then and still do that rather than removing code and API distinctions that allow us to tell if the board code has done something wrong (unintentional overlap, especially unintentional overlap at the same priority value) it would be better to fix the board bugs so we could enable the warnings/asserts... thanks -- PMM From MAILER-DAEMON Sat Dec 14 16:51:17 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1igFJl-0005Hn-OP for mharc-qemu-arm@gnu.org; Sat, 14 Dec 2019 16:51:17 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:55786) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1igFJh-0005HT-Bk for qemu-arm@nongnu.org; Sat, 14 Dec 2019 16:51:17 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1igFJf-0007RJ-9S for qemu-arm@nongnu.org; Sat, 14 Dec 2019 16:51:13 -0500 Received: from us-smtp-2.mimecast.com ([205.139.110.61]:31569 helo=us-smtp-delivery-1.mimecast.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1igFJf-0007O5-1j for qemu-arm@nongnu.org; Sat, 14 Dec 2019 16:51:11 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1576360270; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=QxlNDlcm8HsAwIL81XV9LrgyeoomdszW36hbadR0U1g=; b=aDiWJzupWuw5/dcojEA/xNS3an9uwLER1HnLQmBnae78pHJk58YbY+Rc8HJ6zoeGPADweO PlvIDPTHvE67PCnYy8aLpNAcYQZSfxsljCNlj5qd/xgP8sT68yYDMEvIQE/gY2cNYIx9n1 7zJqB6CFIuGmtCUpMl55sOYk4wR0nM4= Received: from mail-wr1-f69.google.com (mail-wr1-f69.google.com [209.85.221.69]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-327-8Bu-ODQ7OWigUSOCyO84gw-1; Sat, 14 Dec 2019 08:49:10 -0500 Received: by mail-wr1-f69.google.com with SMTP id f17so998089wrt.19 for ; Sat, 14 Dec 2019 05:49:10 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:subject:to:cc:references:from:message-id:date :user-agent:mime-version:in-reply-to:content-language :content-transfer-encoding; bh=QxlNDlcm8HsAwIL81XV9LrgyeoomdszW36hbadR0U1g=; b=pjmOrTAfI9OJQqI6Gxjum1UBUOpEFl+QMsejkFmgjgHX4kLVbgkhGT1Mj/9JZY2i1V 8Id4zPlEIivCUWbRKV/JRSbAeMptu9uj4Yz2165oGLpSgSP1Sn0AqqOefXJiLBtU4fBe dQlCiskb5FsBiHVNsM3YMr5gbnh/87x3ycyZAkqfK7Wfrx2Y0uXVtcQgjW/sn5MEyVeE 5SEPpx9aR4TF/AmDzo4G0V0fse4ovyoZY8KYcdNMkkjWNi1Sw3rDb62X1B429aq5m9RF VvkXlvzWjstGZKguAqsf14GLYEbI35S8855xCs6zqb7pXmmTarly6FxVZq1gt3RS4KJk eoJg== X-Gm-Message-State: APjAAAV2raC2UiTh8v5zScOGNZmVON1C100m3RknVZdoy2VKU5Zb+pr8 62/cO9ED71zofDwLU3+L494pxvkau0xeyU4n84yrJcCsafXP5Pji9/k5oy0Amc9Qs0aRhBuMDrD +rEeLM7kCGPYX X-Received: by 2002:a5d:52c4:: with SMTP id r4mr17915732wrv.368.1576331349372; Sat, 14 Dec 2019 05:49:09 -0800 (PST) X-Google-Smtp-Source: APXvYqzqvi8Yv1gAgKdRu9tRXcCo6khF6hJCVTPIhVSRHMZUfuwPa3WcoEeICZrrYm/E+fPccfPriA== X-Received: by 2002:a5d:52c4:: with SMTP id r4mr17915697wrv.368.1576331348971; Sat, 14 Dec 2019 05:49:08 -0800 (PST) Received: from [192.168.1.35] (34.red-83-42-66.dynamicip.rima-tde.net. [83.42.66.34]) by smtp.gmail.com with ESMTPSA id h8sm14723069wrx.63.2019.12.14.05.49.08 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Sat, 14 Dec 2019 05:49:08 -0800 (PST) Subject: Re: [PATCH v6 2/4] hw/misc: Add the STM32F4xx EXTI device To: Alistair Francis , qemu-devel@nongnu.org, peter.maydell@linaro.org Cc: alistair23@gmail.com, qemu-arm@nongnu.org References: <717e76b6d41e09c352d98a83708c3e3c9fe5d63b.1576227325.git.alistair@alistair23.me> From: =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= Message-ID: <13f8810e-fb67-24c8-fecf-72f48ac5c7db@redhat.com> Date: Sat, 14 Dec 2019 14:49:07 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.2.2 MIME-Version: 1.0 In-Reply-To: <717e76b6d41e09c352d98a83708c3e3c9fe5d63b.1576227325.git.alistair@alistair23.me> Content-Language: en-US X-MC-Unique: 8Bu-ODQ7OWigUSOCyO84gw-1 X-Mimecast-Spam-Score: 0 Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 7bit X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 205.139.110.61 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sat, 14 Dec 2019 21:51:17 -0000 Hi Alistair, On 12/14/19 3:44 AM, Alistair Francis wrote: > Signed-off-by: Alistair Francis > Reviewed-by: Peter Maydell > --- > hw/arm/Kconfig | 1 + > hw/misc/Kconfig | 3 + > hw/misc/Makefile.objs | 1 + > hw/misc/stm32f4xx_exti.c | 189 +++++++++++++++++++++++++++++++ > hw/misc/trace-events | 5 + > include/hw/misc/stm32f4xx_exti.h | 60 ++++++++++ > 6 files changed, 259 insertions(+) > create mode 100644 hw/misc/stm32f4xx_exti.c > create mode 100644 include/hw/misc/stm32f4xx_exti.h > > diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig > index 4660d14715..3d86691ae0 100644 > --- a/hw/arm/Kconfig > +++ b/hw/arm/Kconfig > @@ -315,6 +315,7 @@ config STM32F405_SOC > bool > select ARM_V7M > select STM32F4XX_SYSCFG > + select STM32F4XX_EXTI > > config XLNX_ZYNQMP_ARM > bool > diff --git a/hw/misc/Kconfig b/hw/misc/Kconfig > index 72609650b7..bdd77d8020 100644 > --- a/hw/misc/Kconfig > +++ b/hw/misc/Kconfig > @@ -85,6 +85,9 @@ config STM32F2XX_SYSCFG > config STM32F4XX_SYSCFG > bool > > +config STM32F4XX_EXTI > + bool > + > config MIPS_ITU > bool > > diff --git a/hw/misc/Makefile.objs b/hw/misc/Makefile.objs > index ea8025e0bb..c6ecbdd7b0 100644 > --- a/hw/misc/Makefile.objs > +++ b/hw/misc/Makefile.objs > @@ -59,6 +59,7 @@ common-obj-$(CONFIG_ZYNQ) += zynq_slcr.o > common-obj-$(CONFIG_ZYNQ) += zynq-xadc.o > common-obj-$(CONFIG_STM32F2XX_SYSCFG) += stm32f2xx_syscfg.o > common-obj-$(CONFIG_STM32F4XX_SYSCFG) += stm32f4xx_syscfg.o > +common-obj-$(CONFIG_STM32F4XX_EXTI) += stm32f4xx_exti.o > obj-$(CONFIG_MIPS_CPS) += mips_cmgcr.o > obj-$(CONFIG_MIPS_CPS) += mips_cpc.o > obj-$(CONFIG_MIPS_ITU) += mips_itu.o > diff --git a/hw/misc/stm32f4xx_exti.c b/hw/misc/stm32f4xx_exti.c > new file mode 100644 > index 0000000000..7f87a885aa > --- /dev/null > +++ b/hw/misc/stm32f4xx_exti.c > @@ -0,0 +1,189 @@ > +/* > + * STM32F4XX EXTI > + * > + * Copyright (c) 2014 Alistair Francis > + * > + * Permission is hereby granted, free of charge, to any person obtaining a copy > + * of this software and associated documentation files (the "Software"), to deal > + * in the Software without restriction, including without limitation the rights > + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell > + * copies of the Software, and to permit persons to whom the Software is > + * furnished to do so, subject to the following conditions: > + * > + * The above copyright notice and this permission notice shall be included in > + * all copies or substantial portions of the Software. > + * > + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR > + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, > + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL > + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER > + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, > + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN > + * THE SOFTWARE. > + */ > + > +#include "qemu/osdep.h" > +#include "qemu/log.h" > +#include "trace.h" > +#include "hw/irq.h" > +#include "migration/vmstate.h" > +#include "hw/misc/stm32f4xx_exti.h" > + > +static void stm32f4xx_exti_reset(DeviceState *dev) > +{ > + STM32F4xxExtiState *s = STM32F4XX_EXTI(dev); > + > + s->exti_imr = 0x00000000; > + s->exti_emr = 0x00000000; > + s->exti_rtsr = 0x00000000; > + s->exti_ftsr = 0x00000000; > + s->exti_swier = 0x00000000; > + s->exti_pr = 0x00000000; > +} > + > +static void stm32f4xx_exti_set_irq(void *opaque, int irq, int level) > +{ > + STM32F4xxExtiState *s = opaque; > + > + if (!((1 << irq) & s->exti_imr)) { > + /* Interrupt is masked */ > + return; I'm not sure this is correct, don't you need to set the bit in the exti_pr register regardless it is masked? Else in masked polling mode the guest will never see IRQ delivered. So I'd drop this if statement, ... > + } > + > + trace_stm32f4xx_exti_set_irq(irq, level); > + > + if (((1 << irq) & s->exti_rtsr) && level) { > + /* Rising Edge */ > + qemu_irq_pulse(s->irq[irq]); ... do not pulse here, ... > + s->exti_pr |= 1 << irq; > + } > + > + if (((1 << irq) & s->exti_ftsr) && !level) { > + /* Falling Edge */ > + qemu_irq_pulse(s->irq[irq]); ... do not pulse here, ... > + s->exti_pr |= 1 << irq; > + } ... and here pulse if not masked: if (!((1 << irq) & s->exti_imr)) { /* Interrupt is masked */ return; } qemu_irq_pulse(s->irq[irq]); (Or invert the if condition). > +} > + > +static uint64_t stm32f4xx_exti_read(void *opaque, hwaddr addr, > + unsigned int size) > +{ > + STM32F4xxExtiState *s = opaque; > + > + trace_stm32f4xx_exti_read(addr); > + > + switch (addr) { > + case EXTI_IMR: > + return s->exti_imr; > + case EXTI_EMR: > + return s->exti_emr; > + case EXTI_RTSR: > + return s->exti_rtsr; > + case EXTI_FTSR: > + return s->exti_ftsr; > + case EXTI_SWIER: > + return s->exti_swier; > + case EXTI_PR: > + return s->exti_pr; > + default: > + qemu_log_mask(LOG_GUEST_ERROR, > + "STM32F4XX_exti_read: Bad offset %x\n", (int)addr); > + return 0; > + } > + return 0; > +} > + > +static void stm32f4xx_exti_write(void *opaque, hwaddr addr, > + uint64_t val64, unsigned int size) > +{ > + STM32F4xxExtiState *s = opaque; > + uint32_t value = (uint32_t) val64; > + > + trace_stm32f4xx_exti_write(addr, value); > + > + switch (addr) { > + case EXTI_IMR: > + s->exti_imr = value; > + return; > + case EXTI_EMR: > + s->exti_emr = value; > + return; > + case EXTI_RTSR: > + s->exti_rtsr = value; > + return; > + case EXTI_FTSR: > + s->exti_ftsr = value; > + return; > + case EXTI_SWIER: > + s->exti_swier = value; > + return; > + case EXTI_PR: > + /* This bit is cleared by writing a 1 to it */ > + s->exti_pr &= ~value; > + return; > + default: > + qemu_log_mask(LOG_GUEST_ERROR, > + "STM32F4XX_exti_write: Bad offset %x\n", (int)addr); > + } > +} > + > +static const MemoryRegionOps stm32f4xx_exti_ops = { > + .read = stm32f4xx_exti_read, > + .write = stm32f4xx_exti_write, > + .endianness = DEVICE_NATIVE_ENDIAN, > +}; > + > +static void stm32f4xx_exti_init(Object *obj) > +{ > + STM32F4xxExtiState *s = STM32F4XX_EXTI(obj); > + int i; > + > + for (i = 0; i < NUM_INTERRUPT_OUT_LINES; i++) { > + sysbus_init_irq(SYS_BUS_DEVICE(obj), &s->irq[i]); > + } > + > + memory_region_init_io(&s->mmio, obj, &stm32f4xx_exti_ops, s, > + TYPE_STM32F4XX_EXTI, 0x400); > + sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->mmio); > + > + qdev_init_gpio_in(DEVICE(obj), stm32f4xx_exti_set_irq, > + NUM_GPIO_EVENT_IN_LINES); > +} > + > +static const VMStateDescription vmstate_stm32f4xx_exti = { > + .name = TYPE_STM32F4XX_EXTI, > + .version_id = 1, > + .minimum_version_id = 1, > + .fields = (VMStateField[]) { > + VMSTATE_UINT32(exti_imr, STM32F4xxExtiState), > + VMSTATE_UINT32(exti_emr, STM32F4xxExtiState), > + VMSTATE_UINT32(exti_rtsr, STM32F4xxExtiState), > + VMSTATE_UINT32(exti_ftsr, STM32F4xxExtiState), > + VMSTATE_UINT32(exti_swier, STM32F4xxExtiState), > + VMSTATE_UINT32(exti_pr, STM32F4xxExtiState), > + VMSTATE_END_OF_LIST() > + } > +}; > + > +static void stm32f4xx_exti_class_init(ObjectClass *klass, void *data) > +{ > + DeviceClass *dc = DEVICE_CLASS(klass); > + > + dc->reset = stm32f4xx_exti_reset; > + dc->vmsd = &vmstate_stm32f4xx_exti; > +} > + > +static const TypeInfo stm32f4xx_exti_info = { > + .name = TYPE_STM32F4XX_EXTI, > + .parent = TYPE_SYS_BUS_DEVICE, > + .instance_size = sizeof(STM32F4xxExtiState), > + .instance_init = stm32f4xx_exti_init, > + .class_init = stm32f4xx_exti_class_init, > +}; > + > +static void stm32f4xx_exti_register_types(void) > +{ > + type_register_static(&stm32f4xx_exti_info); > +} > + > +type_init(stm32f4xx_exti_register_types) > diff --git a/hw/misc/trace-events b/hw/misc/trace-events > index 02327562bc..91a3794d68 100644 > --- a/hw/misc/trace-events > +++ b/hw/misc/trace-events > @@ -90,6 +90,11 @@ stm32f4xx_pulse_exti(int irq) "Pulse EXTI: %d" > stm32f4xx_syscfg_read(uint64_t addr) "reg read: addr: 0x%" PRIx64 " " > stm32f4xx_syscfg_write(uint64_t addr, uint64_t data) "reg write: addr: 0x%" PRIx64 " val: 0x%" PRIx64 "" > > +# stm32f4xx_exti > +stm32f4xx_exti_set_irq(int irq, int leve) "Set EXTI: %d to %d" > +stm32f4xx_exti_read(uint64_t addr) "reg read: addr: 0x%" PRIx64 " " > +stm32f4xx_exti_write(uint64_t addr, uint64_t data) "reg write: addr: 0x%" PRIx64 " val: 0x%" PRIx64 "" > + > # tz-mpc.c > tz_mpc_reg_read(uint32_t offset, uint64_t data, unsigned size) "TZ MPC regs read: offset 0x%x data 0x%" PRIx64 " size %u" > tz_mpc_reg_write(uint32_t offset, uint64_t data, unsigned size) "TZ MPC regs write: offset 0x%x data 0x%" PRIx64 " size %u" > diff --git a/include/hw/misc/stm32f4xx_exti.h b/include/hw/misc/stm32f4xx_exti.h > new file mode 100644 > index 0000000000..707036a41b > --- /dev/null > +++ b/include/hw/misc/stm32f4xx_exti.h > @@ -0,0 +1,60 @@ > +/* > + * STM32F4XX EXTI > + * > + * Copyright (c) 2014 Alistair Francis > + * > + * Permission is hereby granted, free of charge, to any person obtaining a copy > + * of this software and associated documentation files (the "Software"), to deal > + * in the Software without restriction, including without limitation the rights > + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell > + * copies of the Software, and to permit persons to whom the Software is > + * furnished to do so, subject to the following conditions: > + * > + * The above copyright notice and this permission notice shall be included in > + * all copies or substantial portions of the Software. > + * > + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR > + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, > + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL > + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER > + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, > + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN > + * THE SOFTWARE. > + */ > + > +#ifndef HW_STM_EXTI_H > +#define HW_STM_EXTI_H > + > +#include "hw/sysbus.h" > +#include "hw/hw.h" > + > +#define EXTI_IMR 0x00 > +#define EXTI_EMR 0x04 > +#define EXTI_RTSR 0x08 > +#define EXTI_FTSR 0x0C > +#define EXTI_SWIER 0x10 > +#define EXTI_PR 0x14 > + > +#define TYPE_STM32F4XX_EXTI "stm32f4xx-exti" > +#define STM32F4XX_EXTI(obj) \ > + OBJECT_CHECK(STM32F4xxExtiState, (obj), TYPE_STM32F4XX_EXTI) > + > +#define NUM_GPIO_EVENT_IN_LINES 16 > +#define NUM_INTERRUPT_OUT_LINES 16 > + > +typedef struct { > + SysBusDevice parent_obj; > + > + MemoryRegion mmio; > + > + uint32_t exti_imr; > + uint32_t exti_emr; > + uint32_t exti_rtsr; > + uint32_t exti_ftsr; > + uint32_t exti_swier; > + uint32_t exti_pr; > + > + qemu_irq irq[NUM_INTERRUPT_OUT_LINES]; > +} STM32F4xxExtiState; > + > +#endif > From MAILER-DAEMON Sat Dec 14 23:56:58 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1igLxi-000808-0J for mharc-qemu-arm@gnu.org; Sat, 14 Dec 2019 23:56:58 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:35564) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1igLxe-0007zY-6n for qemu-arm@nongnu.org; Sat, 14 Dec 2019 23:56:55 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1igLxc-00089J-TL for qemu-arm@nongnu.org; Sat, 14 Dec 2019 23:56:53 -0500 Received: from us-smtp-delivery-1.mimecast.com ([205.139.110.120]:37291 helo=us-smtp-1.mimecast.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1igLxc-000895-QE for qemu-arm@nongnu.org; Sat, 14 Dec 2019 23:56:52 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1576385812; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=B8HFuknbXINXAAhRk14V53jaomrIIMFMcmuG8o0oqKM=; b=arpcsdHm2emlfJF/5DbOkFzDNPRLEnsvuCQsD8hr8jlLlnv9/gkl1tIbQf7UegsVP+zMMo gnCbqIuIJxl+sVTKG2uRUywK9MZPB0yY2XOWpu3mvALMSVNgjdAVu76qBs816kpEzMhRC/ ZUuZOadkf/1UfeMHeDlwXNHQav1e4Co= Received: from mail-wr1-f70.google.com (mail-wr1-f70.google.com [209.85.221.70]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-26-rTivRZ5aMqaHz091zF4ccA-1; Sat, 14 Dec 2019 23:56:48 -0500 Received: by mail-wr1-f70.google.com with SMTP id f10so1786513wro.14 for ; Sat, 14 Dec 2019 20:56:46 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:subject:to:cc:references:from:message-id:date :user-agent:mime-version:in-reply-to:content-language :content-transfer-encoding; bh=rDlgANhttMxSBGvPj/xsQ6/eaqHcaNJi+vyNymVXSvw=; b=Ehdt98spJl9urBUcHY4j7AxuS/BMsrbgMI8ULl+O+Aa79yug1srLbywVoCcSV7Aeit IbehwV9FJFNul8hMVUqcm32H+1up0YGMnHKVKQmiCg1RPg5l9bK1JX95clU6Az0sx5Au TNd6X1LZsnlEa6ml+JSvSK68o9tTf9REAlPNPDzHV826TxmIpbzXw7ILU5H+VRkIZYHN ZtIGifp6WsKP8a9+YjIZIhGua6WnqdYpOZB/rst/9ur9cKkdHdXjvLL3vUVK2dezjLcN 6rXKJ10+r6IGOM70Kts5CLbr2ofogZAZd36iSnrBpzibQP51MiU+LsedhVQ8xxhPK9c8 3a0g== X-Gm-Message-State: APjAAAVnh8uVCF7i3Q7ud9wEPzeMw9zmuygRcKZl1KobVyM1FCajzsWj 2GGfSnfuqt472weaT2T0nuam+HIJnu70UqELLI/WZlm6NvyJ58TfM+EqSSLrAEvEFQkruHF6/CO cix0mSC4AKuF0 X-Received: by 2002:a1c:f008:: with SMTP id a8mr22594386wmb.81.1576385805913; Sat, 14 Dec 2019 20:56:45 -0800 (PST) X-Google-Smtp-Source: APXvYqzDGyxL3C0sSEiSdhDYkbJdvhGm6ACjRaTBvWeJUbshMRGl3d/M0cKAGnHzaxGExViqWJqyKA== X-Received: by 2002:a1c:f008:: with SMTP id a8mr22594375wmb.81.1576385805703; Sat, 14 Dec 2019 20:56:45 -0800 (PST) Received: from [192.168.1.35] (34.red-83-42-66.dynamicip.rima-tde.net. [83.42.66.34]) by smtp.gmail.com with ESMTPSA id y20sm15499882wmi.25.2019.12.14.20.56.44 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Sat, 14 Dec 2019 20:56:45 -0800 (PST) Subject: Re: [PATCH] target/arm: Display helpful message when hflags mismatch To: Richard Henderson , =?UTF-8?Q?Alex_Benn=c3=a9e?= Cc: qemu-devel@nongnu.org, Peter Maydell , qemu-arm@nongnu.org, "Dr. David Alan Gilbert" References: <20191209134552.27733-1-philmd@redhat.com> <87d0cx32vv.fsf@linaro.org> <1d51109a-ae9f-7bfe-66d4-0e1e1266df64@linaro.org> From: =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= Message-ID: <1407bf23-85c2-fce2-da17-bed6766456f9@redhat.com> Date: Sun, 15 Dec 2019 05:56:44 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.2.2 MIME-Version: 1.0 In-Reply-To: <1d51109a-ae9f-7bfe-66d4-0e1e1266df64@linaro.org> Content-Language: en-US X-MC-Unique: rTivRZ5aMqaHz091zF4ccA-1 X-Mimecast-Spam-Score: 0 Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 205.139.110.120 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sun, 15 Dec 2019 04:56:55 -0000 On 12/12/19 1:36 AM, Richard Henderson wrote: > On 12/9/19 8:00 AM, Alex Benn=C3=A9e wrote: >>> -#ifdef CONFIG_DEBUG_TCG >>> - assert(flags =3D=3D rebuild_hflags_internal(env)); >>> -#endif >>> + assert_hflags_rebuild_correctly(env); >> >> I'm trying to recall why we don't just use: >> >> g_assert_cmphex(flags, =3D, rebuild_hflags_internal(env)) s/=3D/=3D=3D/ ;) >> >> I think it came up in one of the reviews. >=20 > checkpatch.pl. >=20 > Because, I believe, there is an environment variable that causes this to = *not* > abort on mismatch. Indeed, see commit 6e9389563e5: commit 6e9389563e56607f72562bdb72db452fcd7e7f74 Author: Dr. David Alan Gilbert Date: Thu Apr 27 17:55:26 2017 +0100 checkpatch: Disallow glib asserts in main code Glib commit a6a875068779 (from 2013) made many of the glib assert macros non-fatal if a flag is set. This causes two problems: a) Compilers moan that your code is unsafe even though you've put an assert in before the point of use. b) Someone evil could, in a library, call g_test_set_nonfatal_assertions() and cause our assertions in important places not to fail and potentially allow memory=20 overruns. Ban most of the glib assertion functions (basically everything except g_assert and g_assert_not_reached) except in tests/ This makes checkpatch gives an error such as: ERROR: Use g_assert or g_assert_not_reached #77: FILE: vl.c:4725: + g_assert_cmpstr("Chocolate", >, "Cheese"); From MAILER-DAEMON Sun Dec 15 00:43:02 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1igMgI-0001TX-LN for mharc-qemu-arm@gnu.org; Sun, 15 Dec 2019 00:43:02 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:39390) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1igMgD-0001Sk-3h for qemu-arm@nongnu.org; Sun, 15 Dec 2019 00:43:01 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1igMgB-000233-P8 for qemu-arm@nongnu.org; Sun, 15 Dec 2019 00:42:57 -0500 Received: from us-smtp-delivery-1.mimecast.com ([205.139.110.120]:26116 helo=us-smtp-1.mimecast.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1igMgB-00022c-Lp for qemu-arm@nongnu.org; Sun, 15 Dec 2019 00:42:55 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1576388575; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=w0iguMPjCokhk/BvXOjAERKF2ncfLyt4ZTfeIaCQ0W4=; b=hBIk5xKmpXjAK5Km2TRJByT/p9Y9sEoVszVL/cPpqOyTNrq+gTmqc5LaHDF2DJkUBZI2kb Hixx2R/h3mXTZ5JNq14cdwXX9YtP29jujLHTygbrokRk4kvoNTSrGTMXNXfahCW+Hp6BKO mZOct9qKlq6aVKa5d9Xc8p5aGPx9Kto= Received: from mail-wr1-f70.google.com (mail-wr1-f70.google.com [209.85.221.70]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-334-kiqccb5BPG6mhE7BwzzB2w-1; Sun, 15 Dec 2019 00:42:53 -0500 Received: by mail-wr1-f70.google.com with SMTP id r2so1820010wrp.7 for ; Sat, 14 Dec 2019 21:42:52 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:subject:to:cc:references:from:message-id:date :user-agent:mime-version:in-reply-to:content-language :content-transfer-encoding; bh=BBVF+N2UHHpH8XDGBlGPZ8YLFBLf9UkQTyU2RhxBcDk=; b=dhoAHuPki9A/7GhHFDQ9CZ/IgGFdRvNVZGH6/fFck5xRhLdrk2OZs54/dZvnRL81W4 RLuaYv6fmkFyV6i5y2AcRwE12uPqK+PBtr71ZmEHu7ErnScREVyneEsng5TZpxAKHWYU 7mCY7AyVIEUSPhVGEKce7C85xnMx0JJEHUedX6/GxH/2OmKD5Fnt6x4tPf5ImiFy1oHL G2iPrMjlFZjC+fx2GVDPzVfZv2Enhl4bwI+pQqYYqXp0Cvrtmeity4lZFyYSpvS9p+zH kH/wQI9I0r8hB/dZmqJjSZNIDwYmNtbbrUq1pxl9CtsuxiB+jOTRXlVcV+0E9bDFImhd 2WIQ== X-Gm-Message-State: APjAAAXCP6yQ+Huyj+a8X7I0i/MHMN+QyVeDB15sSnCi1ns47z+EkG3D lIH9d87vaMbACR3h1ScI3Z/aBry2VCn6DMmlQ930RrxaWOCnDLnYdjLqd28H7v3nvvHWkDNGSdh JlYWCNp06G2p5 X-Received: by 2002:adf:ea4f:: with SMTP id j15mr23480572wrn.356.1576388571768; Sat, 14 Dec 2019 21:42:51 -0800 (PST) X-Google-Smtp-Source: APXvYqz0IMRQ/u1b3O9B0hxf1VlOP54/dnam0OVKI8Turp8WJ6bhlGi9R5D1a8lS7LBP05lJzWuB5g== X-Received: by 2002:adf:ea4f:: with SMTP id j15mr23480552wrn.356.1576388571564; Sat, 14 Dec 2019 21:42:51 -0800 (PST) Received: from [192.168.1.35] (34.red-83-42-66.dynamicip.rima-tde.net. [83.42.66.34]) by smtp.gmail.com with ESMTPSA id g23sm16521121wmk.14.2019.12.14.21.42.50 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Sat, 14 Dec 2019 21:42:51 -0800 (PST) Subject: Re: [PATCH v4 32/37] omap-intc: remove PROP_PTR To: =?UTF-8?Q?Marc-Andr=c3=a9_Lureau?= , qemu-devel@nongnu.org Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org References: <20191120152442.26657-1-marcandre.lureau@redhat.com> <20191120152442.26657-33-marcandre.lureau@redhat.com> From: =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= Message-ID: Date: Sun, 15 Dec 2019 06:42:50 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.2.2 MIME-Version: 1.0 In-Reply-To: <20191120152442.26657-33-marcandre.lureau@redhat.com> Content-Language: en-US X-MC-Unique: kiqccb5BPG6mhE7BwzzB2w-1 X-Mimecast-Spam-Score: 0 Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 205.139.110.120 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sun, 15 Dec 2019 05:43:01 -0000 On 11/20/19 4:24 PM, Marc-Andr=C3=A9 Lureau wrote: > Since clocks are not QOM objects, replace PROP_PTR of clocks with > setters methods. >=20 > (in theory there should probably be different methods for omap1 & > omap2 intc, but this is left as a future improvement) >=20 > Reviewed-by: Peter Maydell > Signed-off-by: Marc-Andr=C3=A9 Lureau > --- > hw/arm/omap1.c | 4 ++-- > hw/arm/omap2.c | 4 ++-- > hw/intc/omap_intc.c | 17 ++++++++++------- > include/hw/arm/omap.h | 14 ++++++++++++++ > 4 files changed, 28 insertions(+), 11 deletions(-) >=20 > diff --git a/hw/arm/omap1.c b/hw/arm/omap1.c > index 6ce038a453..1afd1d3d7f 100644 > --- a/hw/arm/omap1.c > +++ b/hw/arm/omap1.c > @@ -3889,7 +3889,7 @@ struct omap_mpu_state_s *omap310_mpu_init(MemoryReg= ion *dram, > =20 > s->ih[0] =3D qdev_create(NULL, "omap-intc"); > qdev_prop_set_uint32(s->ih[0], "size", 0x100); > - qdev_prop_set_ptr(s->ih[0], "clk", omap_findclk(s, "arminth_ck")); > + omap_intc_set_iclk(OMAP_INTC(s->ih[0]), omap_findclk(s, "arminth_ck"= )); > qdev_init_nofail(s->ih[0]); > busdev =3D SYS_BUS_DEVICE(s->ih[0]); > sysbus_connect_irq(busdev, 0, > @@ -3899,7 +3899,7 @@ struct omap_mpu_state_s *omap310_mpu_init(MemoryReg= ion *dram, > sysbus_mmio_map(busdev, 0, 0xfffecb00); > s->ih[1] =3D qdev_create(NULL, "omap-intc"); > qdev_prop_set_uint32(s->ih[1], "size", 0x800); > - qdev_prop_set_ptr(s->ih[1], "clk", omap_findclk(s, "arminth_ck")); > + omap_intc_set_iclk(OMAP_INTC(s->ih[1]), omap_findclk(s, "arminth_ck"= )); > qdev_init_nofail(s->ih[1]); > busdev =3D SYS_BUS_DEVICE(s->ih[1]); > sysbus_connect_irq(busdev, 0, > diff --git a/hw/arm/omap2.c b/hw/arm/omap2.c > index 457f152bac..1d7cc435ef 100644 > --- a/hw/arm/omap2.c > +++ b/hw/arm/omap2.c > @@ -2308,8 +2308,8 @@ struct omap_mpu_state_s *omap2420_mpu_init(MemoryRe= gion *sdram, > /* Actually mapped at any 2K boundary in the ARM11 private-peripher= al if */ > s->ih[0] =3D qdev_create(NULL, "omap2-intc"); > qdev_prop_set_uint8(s->ih[0], "revision", 0x21); > - qdev_prop_set_ptr(s->ih[0], "fclk", omap_findclk(s, "mpu_intc_fclk")= ); > - qdev_prop_set_ptr(s->ih[0], "iclk", omap_findclk(s, "mpu_intc_iclk")= ); > + omap_intc_set_fclk(OMAP_INTC(s->ih[0]), omap_findclk(s, "mpu_intc_fc= lk")); > + omap_intc_set_iclk(OMAP_INTC(s->ih[0]), omap_findclk(s, "mpu_intc_ic= lk")); > qdev_init_nofail(s->ih[0]); > busdev =3D SYS_BUS_DEVICE(s->ih[0]); > sysbus_connect_irq(busdev, 0, > diff --git a/hw/intc/omap_intc.c b/hw/intc/omap_intc.c > index 854b709ca0..73bb1c2af4 100644 > --- a/hw/intc/omap_intc.c > +++ b/hw/intc/omap_intc.c > @@ -38,10 +38,6 @@ struct omap_intr_handler_bank_s { > unsigned char priority[32]; > }; > =20 > -#define TYPE_OMAP_INTC "common-omap-intc" > -#define OMAP_INTC(obj) \ > - OBJECT_CHECK(struct omap_intr_handler_s, (obj), TYPE_OMAP_INTC) > - > struct omap_intr_handler_s { > SysBusDevice parent_obj; > =20 > @@ -391,9 +387,18 @@ static void omap_intc_realize(DeviceState *dev, Erro= r **errp) > } > } > =20 > +void omap_intc_set_iclk(omap_intr_handler *intc, omap_clk clk) > +{ > + intc->iclk =3D clk; > +} > + > +void omap_intc_set_fclk(omap_intr_handler *intc, omap_clk clk) > +{ > + intc->fclk =3D clk; > +} > + > static Property omap_intc_properties[] =3D { > DEFINE_PROP_UINT32("size", struct omap_intr_handler_s, size, 0x100)= , > - DEFINE_PROP_PTR("clk", struct omap_intr_handler_s, iclk), > DEFINE_PROP_END_OF_LIST(), > }; > =20 > @@ -647,8 +652,6 @@ static void omap2_intc_realize(DeviceState *dev, Erro= r **errp) > static Property omap2_intc_properties[] =3D { > DEFINE_PROP_UINT8("revision", struct omap_intr_handler_s, > revision, 0x21), > - DEFINE_PROP_PTR("iclk", struct omap_intr_handler_s, iclk), > - DEFINE_PROP_PTR("fclk", struct omap_intr_handler_s, fclk), > DEFINE_PROP_END_OF_LIST(), > }; > =20 > diff --git a/include/hw/arm/omap.h b/include/hw/arm/omap.h > index f3aa670036..bcecf19f89 100644 > --- a/include/hw/arm/omap.h > +++ b/include/hw/arm/omap.h > @@ -67,6 +67,20 @@ void omap_clk_setrate(omap_clk clk, int divide, int mu= ltiply); > int64_t omap_clk_getrate(omap_clk clk); > void omap_clk_reparent(omap_clk clk, omap_clk parent); > =20 > +/* omap_intc.c */ > +#define TYPE_OMAP_INTC "common-omap-intc" > +#define OMAP_INTC(obj) \ > + OBJECT_CHECK(omap_intr_handler, (obj), TYPE_OMAP_INTC) > + > +typedef struct omap_intr_handler_s omap_intr_handler; > + > +/* > + * TODO: Ideally we should have a clock framework that > + * let us wire these clocks up with QOM properties or links. > + */ > +void omap_intc_set_iclk(omap_intr_handler *intc, omap_clk clk); > +void omap_intc_set_fclk(omap_intr_handler *intc, omap_clk clk); > + > /* OMAP2 l4 Interconnect */ > struct omap_l4_s; > struct omap_l4_region_s { >=20 Reviewed-by: Philippe Mathieu-Daud=C3=A9 From MAILER-DAEMON Sun Dec 15 00:43:29 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1igMgj-0001pu-4m for mharc-qemu-arm@gnu.org; Sun, 15 Dec 2019 00:43:29 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:40331) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1igMgg-0001nJ-H7 for qemu-arm@nongnu.org; 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[83.42.66.34]) by smtp.gmail.com with ESMTPSA id p26sm16212404wmc.24.2019.12.14.21.43.14 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Sat, 14 Dec 2019 21:43:14 -0800 (PST) Subject: Re: [PATCH v4 33/37] omap-i2c: remove PROP_PTR To: =?UTF-8?Q?Marc-Andr=c3=a9_Lureau?= , qemu-devel@nongnu.org Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org References: <20191120152442.26657-1-marcandre.lureau@redhat.com> <20191120152442.26657-34-marcandre.lureau@redhat.com> From: =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= Message-ID: <11934efd-128a-2ebf-5b5f-3f6433acf3c6@redhat.com> Date: Sun, 15 Dec 2019 06:43:13 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.2.2 MIME-Version: 1.0 In-Reply-To: <20191120152442.26657-34-marcandre.lureau@redhat.com> Content-Language: en-US X-MC-Unique: sKPjmi1OPiaxsOZoiUyh2w-1 X-Mimecast-Spam-Score: 0 Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 207.211.31.81 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sun, 15 Dec 2019 05:43:28 -0000 On 11/20/19 4:24 PM, Marc-Andr=C3=A9 Lureau wrote: > Since clocks are not QOM objects, replace PROP_PTR of clocks with > setters methods. >=20 > Reviewed-by: Peter Maydell > Reviewed-by: Corey Minyard > Signed-off-by: Marc-Andr=C3=A9 Lureau > --- > hw/arm/omap1.c | 2 +- > hw/arm/omap2.c | 8 ++++---- > hw/i2c/omap_i2c.c | 19 ++++++++++++------- > include/hw/arm/omap.h | 13 +++++++++++++ > 4 files changed, 30 insertions(+), 12 deletions(-) >=20 > diff --git a/hw/arm/omap1.c b/hw/arm/omap1.c > index 1afd1d3d7f..807e5f70d1 100644 > --- a/hw/arm/omap1.c > +++ b/hw/arm/omap1.c > @@ -4030,7 +4030,7 @@ struct omap_mpu_state_s *omap310_mpu_init(MemoryReg= ion *dram, > =20 > s->i2c[0] =3D qdev_create(NULL, "omap_i2c"); > qdev_prop_set_uint8(s->i2c[0], "revision", 0x11); > - qdev_prop_set_ptr(s->i2c[0], "fclk", omap_findclk(s, "mpuper_ck")); > + omap_i2c_set_fclk(OMAP_I2C(s->i2c[0]), omap_findclk(s, "mpuper_ck"))= ; > qdev_init_nofail(s->i2c[0]); > busdev =3D SYS_BUS_DEVICE(s->i2c[0]); > sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(s->ih[1], OMAP_INT_I= 2C)); > diff --git a/hw/arm/omap2.c b/hw/arm/omap2.c > index 1d7cc435ef..171e2d0472 100644 > --- a/hw/arm/omap2.c > +++ b/hw/arm/omap2.c > @@ -2425,8 +2425,8 @@ struct omap_mpu_state_s *omap2420_mpu_init(MemoryRe= gion *sdram, > =20 > s->i2c[0] =3D qdev_create(NULL, "omap_i2c"); > qdev_prop_set_uint8(s->i2c[0], "revision", 0x34); > - qdev_prop_set_ptr(s->i2c[0], "iclk", omap_findclk(s, "i2c1.iclk")); > - qdev_prop_set_ptr(s->i2c[0], "fclk", omap_findclk(s, "i2c1.fclk")); > + omap_i2c_set_iclk(OMAP_I2C(s->i2c[0]), omap_findclk(s, "i2c1.iclk"))= ; > + omap_i2c_set_fclk(OMAP_I2C(s->i2c[0]), omap_findclk(s, "i2c1.fclk"))= ; > qdev_init_nofail(s->i2c[0]); > busdev =3D SYS_BUS_DEVICE(s->i2c[0]); > sysbus_connect_irq(busdev, 0, > @@ -2437,8 +2437,8 @@ struct omap_mpu_state_s *omap2420_mpu_init(MemoryRe= gion *sdram, > =20 > s->i2c[1] =3D qdev_create(NULL, "omap_i2c"); > qdev_prop_set_uint8(s->i2c[1], "revision", 0x34); > - qdev_prop_set_ptr(s->i2c[1], "iclk", omap_findclk(s, "i2c2.iclk")); > - qdev_prop_set_ptr(s->i2c[1], "fclk", omap_findclk(s, "i2c2.fclk")); > + omap_i2c_set_iclk(OMAP_I2C(s->i2c[1]), omap_findclk(s, "i2c2.iclk"))= ; > + omap_i2c_set_fclk(OMAP_I2C(s->i2c[1]), omap_findclk(s, "i2c2.fclk"))= ; > qdev_init_nofail(s->i2c[1]); > busdev =3D SYS_BUS_DEVICE(s->i2c[1]); > sysbus_connect_irq(busdev, 0, > diff --git a/hw/i2c/omap_i2c.c b/hw/i2c/omap_i2c.c > index 3ba965a58f..3ccbd5cc2c 100644 > --- a/hw/i2c/omap_i2c.c > +++ b/hw/i2c/omap_i2c.c > @@ -28,10 +28,7 @@ > #include "qemu/error-report.h" > #include "qapi/error.h" > =20 > -#define TYPE_OMAP_I2C "omap_i2c" > -#define OMAP_I2C(obj) OBJECT_CHECK(OMAPI2CState, (obj), TYPE_OMAP_I2C) > - > -typedef struct OMAPI2CState { > +struct OMAPI2CState { > SysBusDevice parent_obj; > =20 > MemoryRegion iomem; > @@ -56,7 +53,7 @@ typedef struct OMAPI2CState { > uint8_t divider; > uint8_t times[2]; > uint16_t test; > -} OMAPI2CState; > +}; > =20 > #define OMAP2_INTR_REV=090x34 > #define OMAP2_GC_REV=090x34 > @@ -504,10 +501,18 @@ static void omap_i2c_realize(DeviceState *dev, Erro= r **errp) > } > } > =20 > +void omap_i2c_set_iclk(OMAPI2CState *i2c, omap_clk clk) > +{ > + i2c->iclk =3D clk; > +} > + > +void omap_i2c_set_fclk(OMAPI2CState *i2c, omap_clk clk) > +{ > + i2c->fclk =3D clk; > +} > + > static Property omap_i2c_properties[] =3D { > DEFINE_PROP_UINT8("revision", OMAPI2CState, revision, 0), > - DEFINE_PROP_PTR("iclk", OMAPI2CState, iclk), > - DEFINE_PROP_PTR("fclk", OMAPI2CState, fclk), > DEFINE_PROP_END_OF_LIST(), > }; > =20 > diff --git a/include/hw/arm/omap.h b/include/hw/arm/omap.h > index bcecf19f89..39a295ba20 100644 > --- a/include/hw/arm/omap.h > +++ b/include/hw/arm/omap.h > @@ -81,6 +81,19 @@ typedef struct omap_intr_handler_s omap_intr_handler; > void omap_intc_set_iclk(omap_intr_handler *intc, omap_clk clk); > void omap_intc_set_fclk(omap_intr_handler *intc, omap_clk clk); > =20 > +/* omap_i2c.c */ > +#define TYPE_OMAP_I2C "omap_i2c" > +#define OMAP_I2C(obj) OBJECT_CHECK(OMAPI2CState, (obj), TYPE_OMAP_I2C) > + > +typedef struct OMAPI2CState OMAPI2CState; > + > +/* > + * TODO: Ideally we should have a clock framework that > + * let us wire these clocks up with QOM properties or links. > + */ > +void omap_i2c_set_iclk(OMAPI2CState *i2c, omap_clk clk); > +void omap_i2c_set_fclk(OMAPI2CState *i2c, omap_clk clk); > + > /* OMAP2 l4 Interconnect */ > struct omap_l4_s; > struct omap_l4_region_s { >=20 Reviewed-by: Philippe Mathieu-Daud=C3=A9 From MAILER-DAEMON Sun Dec 15 00:44:36 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1igMhn-0003GE-Ut for mharc-qemu-arm@gnu.org; Sun, 15 Dec 2019 00:44:35 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:43452) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1igMhk-0003CG-A5 for qemu-arm@nongnu.org; Sun, 15 Dec 2019 00:44:33 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1igMhi-00034A-Oe for qemu-arm@nongnu.org; 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[83.42.66.34]) by smtp.gmail.com with ESMTPSA id w13sm16640128wru.38.2019.12.14.21.44.26 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Sat, 14 Dec 2019 21:44:26 -0800 (PST) Subject: Re: [PATCH v4 34/37] omap-gpio: remove PROP_PTR To: =?UTF-8?Q?Marc-Andr=c3=a9_Lureau?= , qemu-devel@nongnu.org Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org References: <20191120152442.26657-1-marcandre.lureau@redhat.com> <20191120152442.26657-35-marcandre.lureau@redhat.com> From: =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= Message-ID: <904a5fd6-4b16-9f51-b6eb-0f45e451ccf7@redhat.com> Date: Sun, 15 Dec 2019 06:44:25 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.2.2 MIME-Version: 1.0 In-Reply-To: <20191120152442.26657-35-marcandre.lureau@redhat.com> Content-Language: en-US X-MC-Unique: t9fYAKukPxGFSAyS78B-BA-1 X-Mimecast-Spam-Score: 0 Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 207.211.31.81 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sun, 15 Dec 2019 05:44:34 -0000 On 11/20/19 4:24 PM, Marc-Andr=C3=A9 Lureau wrote: > Since clocks are not QOM objects, replace PROP_PTR of clocks with > setters methods. >=20 > Move/adapt the existing TODO comment about a clock framework. >=20 > Reviewed-by: Peter Maydell > Signed-off-by: Marc-Andr=C3=A9 Lureau > --- > hw/arm/omap1.c | 2 +- > hw/arm/omap2.c | 13 +++++++------ > hw/gpio/omap_gpio.c | 42 +++++++++++++++--------------------------- > include/hw/arm/omap.h | 33 +++++++++++++++++++++++++++++---- > 4 files changed, 52 insertions(+), 38 deletions(-) >=20 > diff --git a/hw/arm/omap1.c b/hw/arm/omap1.c > index 807e5f70d1..761cc17ea9 100644 > --- a/hw/arm/omap1.c > +++ b/hw/arm/omap1.c > @@ -4012,7 +4012,7 @@ struct omap_mpu_state_s *omap310_mpu_init(MemoryReg= ion *dram, > =20 > s->gpio =3D qdev_create(NULL, "omap-gpio"); > qdev_prop_set_int32(s->gpio, "mpu_model", s->mpu_model); > - qdev_prop_set_ptr(s->gpio, "clk", omap_findclk(s, "arm_gpio_ck")); > + omap_gpio_set_clk(OMAP1_GPIO(s->gpio), omap_findclk(s, "arm_gpio_ck"= )); > qdev_init_nofail(s->gpio); > sysbus_connect_irq(SYS_BUS_DEVICE(s->gpio), 0, > qdev_get_gpio_in(s->ih[0], OMAP_INT_GPIO_BANK1))= ; > diff --git a/hw/arm/omap2.c b/hw/arm/omap2.c > index 171e2d0472..e1c11de5ce 100644 > --- a/hw/arm/omap2.c > +++ b/hw/arm/omap2.c > @@ -2449,13 +2449,14 @@ struct omap_mpu_state_s *omap2420_mpu_init(Memory= Region *sdram, > =20 > s->gpio =3D qdev_create(NULL, "omap2-gpio"); > qdev_prop_set_int32(s->gpio, "mpu_model", s->mpu_model); > - qdev_prop_set_ptr(s->gpio, "iclk", omap_findclk(s, "gpio_iclk")); > - qdev_prop_set_ptr(s->gpio, "fclk0", omap_findclk(s, "gpio1_dbclk")); > - qdev_prop_set_ptr(s->gpio, "fclk1", omap_findclk(s, "gpio2_dbclk")); > - qdev_prop_set_ptr(s->gpio, "fclk2", omap_findclk(s, "gpio3_dbclk")); > - qdev_prop_set_ptr(s->gpio, "fclk3", omap_findclk(s, "gpio4_dbclk")); > + omap2_gpio_set_iclk(OMAP2_GPIO(s->gpio), omap_findclk(s, "gpio_iclk"= )); > + omap2_gpio_set_fclk(OMAP2_GPIO(s->gpio), 0, omap_findclk(s, "gpio1_d= bclk")); > + omap2_gpio_set_fclk(OMAP2_GPIO(s->gpio), 1, omap_findclk(s, "gpio2_d= bclk")); > + omap2_gpio_set_fclk(OMAP2_GPIO(s->gpio), 2, omap_findclk(s, "gpio3_d= bclk")); > + omap2_gpio_set_fclk(OMAP2_GPIO(s->gpio), 3, omap_findclk(s, "gpio4_d= bclk")); > if (s->mpu_model =3D=3D omap2430) { > - qdev_prop_set_ptr(s->gpio, "fclk4", omap_findclk(s, "gpio5_dbclk= ")); > + omap2_gpio_set_fclk(OMAP2_GPIO(s->gpio), 4, > + omap_findclk(s, "gpio5_dbclk")); > } > qdev_init_nofail(s->gpio); > busdev =3D SYS_BUS_DEVICE(s->gpio); > diff --git a/hw/gpio/omap_gpio.c b/hw/gpio/omap_gpio.c > index 41e1aa798c..85c16897ae 100644 > --- a/hw/gpio/omap_gpio.c > +++ b/hw/gpio/omap_gpio.c > @@ -40,10 +40,6 @@ struct omap_gpio_s { > uint16_t pins; > }; > =20 > -#define TYPE_OMAP1_GPIO "omap-gpio" > -#define OMAP1_GPIO(obj) \ > - OBJECT_CHECK(struct omap_gpif_s, (obj), TYPE_OMAP1_GPIO) > - > struct omap_gpif_s { > SysBusDevice parent_obj; > =20 > @@ -212,10 +208,6 @@ struct omap2_gpio_s { > uint8_t delay; > }; > =20 > -#define TYPE_OMAP2_GPIO "omap2-gpio" > -#define OMAP2_GPIO(obj) \ > - OBJECT_CHECK(struct omap2_gpif_s, (obj), TYPE_OMAP2_GPIO) > - > struct omap2_gpif_s { > SysBusDevice parent_obj; > =20 > @@ -747,21 +739,13 @@ static void omap2_gpio_realize(DeviceState *dev, Er= ror **errp) > } > } > =20 > -/* Using qdev pointer properties for the clocks is not ideal. > - * qdev should support a generic means of defining a 'port' with > - * an arbitrary interface for connecting two devices. Then we > - * could reframe the omap clock API in terms of clock ports, > - * and get some type safety. For now the best qdev provides is > - * passing an arbitrary pointer. > - * (It's not possible to pass in the string which is the clock > - * name, because this device does not have the necessary information > - * (ie the struct omap_mpu_state_s*) to do the clockname to pointer > - * translation.) > - */ > +void omap_gpio_set_clk(omap_gpif *gpio, omap_clk clk) > +{ > + gpio->clk =3D clk; > +} > =20 > static Property omap_gpio_properties[] =3D { > DEFINE_PROP_INT32("mpu_model", struct omap_gpif_s, mpu_model, 0), > - DEFINE_PROP_PTR("clk", struct omap_gpif_s, clk), > DEFINE_PROP_END_OF_LIST(), > }; > =20 > @@ -784,15 +768,19 @@ static const TypeInfo omap_gpio_info =3D { > .class_init =3D omap_gpio_class_init, > }; > =20 > +void omap2_gpio_set_iclk(omap2_gpif *gpio, omap_clk clk) > +{ > + gpio->iclk =3D clk; > +} > + > +void omap2_gpio_set_fclk(omap2_gpif *gpio, uint8_t i, omap_clk clk) > +{ > + assert(i <=3D 5); > + gpio->fclk[i] =3D clk; > +} > + > static Property omap2_gpio_properties[] =3D { > DEFINE_PROP_INT32("mpu_model", struct omap2_gpif_s, mpu_model, 0), > - DEFINE_PROP_PTR("iclk", struct omap2_gpif_s, iclk), > - DEFINE_PROP_PTR("fclk0", struct omap2_gpif_s, fclk[0]), > - DEFINE_PROP_PTR("fclk1", struct omap2_gpif_s, fclk[1]), > - DEFINE_PROP_PTR("fclk2", struct omap2_gpif_s, fclk[2]), > - DEFINE_PROP_PTR("fclk3", struct omap2_gpif_s, fclk[3]), > - DEFINE_PROP_PTR("fclk4", struct omap2_gpif_s, fclk[4]), > - DEFINE_PROP_PTR("fclk5", struct omap2_gpif_s, fclk[5]), > DEFINE_PROP_END_OF_LIST(), > }; > =20 > diff --git a/include/hw/arm/omap.h b/include/hw/arm/omap.h > index 39a295ba20..6be386d0e2 100644 > --- a/include/hw/arm/omap.h > +++ b/include/hw/arm/omap.h > @@ -77,6 +77,16 @@ typedef struct omap_intr_handler_s omap_intr_handler; > /* > * TODO: Ideally we should have a clock framework that > * let us wire these clocks up with QOM properties or links. > + * > + * qdev should support a generic means of defining a 'port' with > + * an arbitrary interface for connecting two devices. Then we > + * could reframe the omap clock API in terms of clock ports, > + * and get some type safety. For now the best qdev provides is > + * passing an arbitrary pointer. > + * (It's not possible to pass in the string which is the clock > + * name, because this device does not have the necessary information > + * (ie the struct omap_mpu_state_s*) to do the clockname to pointer > + * translation.) > */ > void omap_intc_set_iclk(omap_intr_handler *intc, omap_clk clk); > void omap_intc_set_fclk(omap_intr_handler *intc, omap_clk clk); > @@ -87,13 +97,28 @@ void omap_intc_set_fclk(omap_intr_handler *intc, omap= _clk clk); > =20 > typedef struct OMAPI2CState OMAPI2CState; > =20 > -/* > - * TODO: Ideally we should have a clock framework that > - * let us wire these clocks up with QOM properties or links. > - */ > +/* TODO: clock framework (see above) */ > void omap_i2c_set_iclk(OMAPI2CState *i2c, omap_clk clk); > void omap_i2c_set_fclk(OMAPI2CState *i2c, omap_clk clk); > =20 > +/* omap_gpio.c */ > +#define TYPE_OMAP1_GPIO "omap-gpio" > +#define OMAP1_GPIO(obj) \ > + OBJECT_CHECK(struct omap_gpif_s, (obj), TYPE_OMAP1_GPIO) > + > +#define TYPE_OMAP2_GPIO "omap2-gpio" > +#define OMAP2_GPIO(obj) \ > + OBJECT_CHECK(struct omap2_gpif_s, (obj), TYPE_OMAP2_GPIO) > + > +typedef struct omap_gpif_s omap_gpif; > +typedef struct omap2_gpif_s omap2_gpif; > + > +/* TODO: clock framework (see above) */ > +void omap_gpio_set_clk(omap_gpif *gpio, omap_clk clk); > + > +void omap2_gpio_set_iclk(omap2_gpif *gpio, omap_clk clk); > +void omap2_gpio_set_fclk(omap2_gpif *gpio, uint8_t i, omap_clk clk); > + > /* OMAP2 l4 Interconnect */ > struct omap_l4_s; > struct omap_l4_region_s { >=20 Reviewed-by: Philippe Mathieu-Daud=C3=A9 From MAILER-DAEMON Sun Dec 15 04:52:01 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1igQZE-00040x-SW for mharc-qemu-arm@gnu.org; Sun, 15 Dec 2019 04:52:00 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:46533) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1igQZC-0003zl-0r for qemu-arm@nongnu.org; Sun, 15 Dec 2019 04:51:59 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1igQZ8-0004bh-1Q for qemu-arm@nongnu.org; Sun, 15 Dec 2019 04:51:55 -0500 Received: from us-smtp-1.mimecast.com ([205.139.110.61]:49131) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1igQZ7-0004Ry-EP for qemu-arm@nongnu.org; Sun, 15 Dec 2019 04:51:53 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1576403512; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=Nn4LKYU68iH+rth6Y64y0uJWlIedeSk7Ug0F1c/xxt4=; b=YFPJieUhF1uL0afiXsGIP+NIJXJEPoAAgYHKBdcr4ZqxTm7/UNaZ/GtpY5ObitxVjBME8i IOJxi+D6ieqp6F0uBNHRsFGL5aD2+SsTFc7XFC3HqxV+YXfFRnefEquUHRi7DgEip0TCUY 5gpuBngbafbpPv0OhfeDgGayxDrLF00= Received: from mail-qk1-f198.google.com (mail-qk1-f198.google.com [209.85.222.198]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-8-g5SgWSe8P7eeTSy31BGegA-1; Sun, 15 Dec 2019 04:51:50 -0500 Received: by mail-qk1-f198.google.com with SMTP id s9so2584377qkg.21 for ; Sun, 15 Dec 2019 01:51:50 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:in-reply-to; bh=JexjbKDRWd+HP8U/4Z49W6xylkN1jU7Pq3Ic5X0J99U=; b=iTnpyy1g4nFqFKauGK9g9VZpZG3mXQ5mPIAJqurWPKItg94q0GgU8QdQp4Zvqu1Hem wAbJ3+M986RRTuHpB6figJjipMmU2CQnqbs2gtYsONQY8mx/Xt8dcbQcBtXKAEdMpW/s vxoD4in370vvjaE/AV6LOveClMzOguVhgEM3aFWtMZ3q4CqYOe5i2+ZLXQGNnG333A9P 6UTTqHwczf+s4m7NshcMMnr2gIl3LBcSKV20lF3Myf9Bzks6GUXIY/YuhE7LClaw9RBj oCGDkIlldgb46ofk5hTSQd1e8csv8Lwb0A6uYyUPaPusBP5fP7ha4BOxqddcvcAe7l6z Mhdw== X-Gm-Message-State: APjAAAVzHlb3DtS2/say3icRNVGcRoJUo6nN6JGSgs5B6NXZkfmmlBSs MdkWlJD+TSrv5k7RI409nXuCaR81IRxcYPrArYASNZStoyMcaex2XwqxWuYEnhi/eQjk2zwT4nq Tu1Berr+feVib X-Received: by 2002:a0c:ea81:: with SMTP id d1mr21924158qvp.138.1576403509985; Sun, 15 Dec 2019 01:51:49 -0800 (PST) X-Google-Smtp-Source: APXvYqxfSUATHjxij/OAUPj2Tdys7QBapd5UqToJFM7KqoY6kKOmCY8gDA09+RZPd27hQyxK4UThdA== X-Received: by 2002:a0c:ea81:: with SMTP id d1mr21924140qvp.138.1576403509804; Sun, 15 Dec 2019 01:51:49 -0800 (PST) Received: from redhat.com (bzq-79-181-48-215.red.bezeqint.net. [79.181.48.215]) by smtp.gmail.com with ESMTPSA id h34sm5557924qtc.62.2019.12.15.01.51.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 15 Dec 2019 01:51:49 -0800 (PST) Date: Sun, 15 Dec 2019 04:51:42 -0500 From: "Michael S. Tsirkin" To: Peter Maydell Cc: Philippe =?iso-8859-1?Q?Mathieu-Daud=E9?= , QEMU Developers , Andrew Baumann , Aurelien Jarno , kvm-devel , Alex Williamson , Aleksandar Markovic , Joel Stanley , qemu-arm , Marcelo Tosatti , Alistair Francis , Eduardo Habkost , Richard Henderson , Aleksandar Rikalo , Paul Burton , Marcel Apfelbaum , "Edgar E. Iglesias" , Paolo Bonzini Subject: Re: [PATCH 0/8] Simplify memory_region_add_subregion_overlap(..., priority=0) Message-ID: <20191215044759-mutt-send-email-mst@kernel.org> References: <20191214155614.19004-1-philmd@redhat.com> MIME-Version: 1.0 In-Reply-To: X-MC-Unique: g5SgWSe8P7eeTSy31BGegA-1 X-Mimecast-Spam-Score: 0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: quoted-printable Content-Disposition: inline X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 205.139.110.61 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sun, 15 Dec 2019 09:51:59 -0000 On Sat, Dec 14, 2019 at 04:28:08PM +0000, Peter Maydell wrote: > (It doesn't actually assert that it doesn't > overlap because we have some legacy uses, notably > in the x86 PC machines, which do overlap without using > the right function, which we've never tried to tidy up.) It's not exactly legacy uses. To be more exact, the way the non overlap versions are *used* is to mean "I don't care what happens when they overlap" as opposed to "will never overlap". There are lots of regions where guest can make things overlapping but doesn't, e.g. PCI BARs can be programmed to overlap almost anything. What happens on real hardware if you then access one of the BARs is undefined, but programming itself is harmless. That's why we can't assert. --=20 MST From MAILER-DAEMON Sun Dec 15 04:54:58 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1igQc6-0005Ms-32 for mharc-qemu-arm@gnu.org; Sun, 15 Dec 2019 04:54:58 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:34854) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1igQc3-0005LF-9I for qemu-arm@nongnu.org; Sun, 15 Dec 2019 04:54:56 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1igQc0-00082S-G1 for qemu-arm@nongnu.org; Sun, 15 Dec 2019 04:54:55 -0500 Received: from us-smtp-2.mimecast.com ([207.211.31.81]:21250 helo=us-smtp-delivery-1.mimecast.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1igQc0-0007zZ-BG for qemu-arm@nongnu.org; Sun, 15 Dec 2019 04:54:52 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1576403691; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=QTxGehGAWcnP8d+3tSJ5HofRU1UwAOCQCbBRPOrzAWw=; b=MK7tBXg5UMuz1IZ9mhlmuOscU+eRy2vxPLfK0nho0JixLQIoZ1ZETN6pScWq3yzZ7sz8L6 t4Nc/3UjOuegCIAIgCsl23J+IuOgBS3gMNvyLs1+1ZbHoyZ3X0tw1/fuZ+K97RKoQG+JLs kr7NKf+sycIS/Z6c4KB+tO1XRfR1l+w= Received: from mail-qv1-f70.google.com (mail-qv1-f70.google.com [209.85.219.70]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-405-se6cRPt7P0G61A3ICT667w-1; Sun, 15 Dec 2019 04:54:49 -0500 Received: by mail-qv1-f70.google.com with SMTP id d7so3127030qvq.12 for ; Sun, 15 Dec 2019 01:54:49 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:content-transfer-encoding :in-reply-to; bh=T1f/gy7GAu+tVHMgArCL2bMPC9tQyMSsCzhr+i5i4NQ=; b=PQMUxRQfWWVuMf4sDTcCWI7iAGl1jRrrwBOQN5UVyXB6t/Vv8Rdn/cX1hq8XN2YwSv Anf32OEOCL3z2+l8mYvA06FIf3hHr7+ky0ngIeL8D6tRqsygEEcTvM20AkGLVbO6m3Lt RTJMG+n8592/lC3Coo5099lPl+dnVm2c5KHWyWG8XyabVOkVO43lWPA0gu+YSyKTOvRp 2f5ZePK7+r6f374sIzrNrBYySxXJKMA7OJOAr2dS/whd/OeuBxhUnvYY8YUfPtyoVJNt 1HVypd1zLKo4f9wvaHs55OdeEYOHK0fIydYooUtotIUbhQx8wUDeOzKDxG0sleaDmLFm tRnA== X-Gm-Message-State: APjAAAUAHANgM2kg43WXV00jR74QaxAWTYxAUgJdJXllPtXhW6gGgIb0 Z02YqpaddhO7R30beXUSa9C3rxEWDWgClt6QmKs6xuF4znMk7bepC3Tqx18uQbCWXC6RryouYtN ogV+JLsc+TAC1 X-Received: by 2002:a37:a98e:: with SMTP id s136mr22239268qke.253.1576403689154; Sun, 15 Dec 2019 01:54:49 -0800 (PST) X-Google-Smtp-Source: APXvYqwBjQGeI+OUxK2u+rGe7U2c1Ycf3YvIBLfP1X5FXOC3InLvwFd942CELbUy2R722482FVQ3BQ== X-Received: by 2002:a37:a98e:: with SMTP id s136mr22239245qke.253.1576403688946; Sun, 15 Dec 2019 01:54:48 -0800 (PST) Received: from redhat.com (bzq-79-181-48-215.red.bezeqint.net. [79.181.48.215]) by smtp.gmail.com with ESMTPSA id n7sm4780899qke.121.2019.12.15.01.54.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 15 Dec 2019 01:54:48 -0800 (PST) Date: Sun, 15 Dec 2019 04:54:42 -0500 From: "Michael S. Tsirkin" To: Peter Maydell Cc: Philippe =?iso-8859-1?Q?Mathieu-Daud=E9?= , QEMU Developers , Andrew Baumann , Aurelien Jarno , kvm-devel , Alex Williamson , Aleksandar Markovic , Joel Stanley , qemu-arm , Marcelo Tosatti , Alistair Francis , Eduardo Habkost , Richard Henderson , Aleksandar Rikalo , Paul Burton , Marcel Apfelbaum , "Edgar E. Iglesias" , Paolo Bonzini Subject: Re: [PATCH 0/8] Simplify memory_region_add_subregion_overlap(..., priority=0) Message-ID: <20191215045230-mutt-send-email-mst@kernel.org> References: <20191214155614.19004-1-philmd@redhat.com> <31acb07b-a61b-1bc4-ee6e-faa511745a61@redhat.com> MIME-Version: 1.0 In-Reply-To: X-MC-Unique: se6cRPt7P0G61A3ICT667w-1 X-Mimecast-Spam-Score: 0 Content-Type: text/plain; charset=iso-8859-1 Content-Transfer-Encoding: quoted-printable Content-Disposition: inline X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 207.211.31.81 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sun, 15 Dec 2019 09:54:56 -0000 On Sat, Dec 14, 2019 at 08:01:46PM +0000, Peter Maydell wrote: > On Sat, 14 Dec 2019 at 18:17, Philippe Mathieu-Daud=E9 wrote: > > Maybe we can a warning if priority=3D0, to force board designers to use > > explicit priority (explicit overlap). >=20 > Priority 0 is fine, it's just one of the possible positive and > negative values. I think what ideally we would complain about > is where we see an overlap and both the regions involved > have the same priority value, because in that case which > one the guest sees is implicitly dependent on (I think) which > order the subregions were added, which is fragile if we move > code around. I'm not sure how easy that is to test for or how > much of our existing code violates it, though. >=20 > thanks > -- PMM Problem is it's not uncommon for guests to create such configs, and then just never access them. So the thing to do would be to complain *on access*. --=20 MST From MAILER-DAEMON Sun Dec 15 10:27:28 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1igVns-0007qS-Ll for mharc-qemu-arm@gnu.org; Sun, 15 Dec 2019 10:27:28 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:37028) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1igVnq-0007q4-3t for qemu-arm@nongnu.org; Sun, 15 Dec 2019 10:27:27 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1igVno-0001Zl-PS for qemu-arm@nongnu.org; Sun, 15 Dec 2019 10:27:25 -0500 Received: from mail-ot1-x342.google.com ([2607:f8b0:4864:20::342]:33228) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1igVno-0001WW-JY for qemu-arm@nongnu.org; Sun, 15 Dec 2019 10:27:24 -0500 Received: by mail-ot1-x342.google.com with SMTP id d17so5623766otc.0 for ; Sun, 15 Dec 2019 07:27:24 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=7RRaL3Yvu+i2tlgto54WRPCcxOMll246e8ITYnRGwDI=; b=afNFnLcrQzgm3wKSvboSfSwxBBar1xP6aIEXir1TfRJQmEcuWTD8m3Prm2Zq1+sUXn mufCXi5v4RO9S72Bxj7dEdCY5OMGgbnL9SHZPMT4lPDfwGWZCW6xGMjfFKwSSeGp468G YRwhcW4YLUfvSJhZ/z/W9In99fNBrOcoAY+fPrMzi6LvpiP9gaH4MLQ3TmKbVl/mG5dC gNafKso8pqii1V/qe69nCCWYxcY7r/G0x7cTtKThfdT3IrXKQMmv1S5zO/bcFFPL3gQk ennG+TzktZvgs3k5QvrL37Gf+inJjSzJTez2gfFOsECR4j63ThkjNmuSzGA84iPqgYQy GofA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=7RRaL3Yvu+i2tlgto54WRPCcxOMll246e8ITYnRGwDI=; b=h4mIXLMIbUtfcsPSHAXrMNzx4ySAHZJosXNfVStmGOiglno+gdntlZVe980zFVkw+L kUQ+YVsMbk2rcHQuL8w2uBgYnQ0u/MMXVP7pKclubeStX2EhRZMZVCCab20GGj7ZqrKJ WwLp4ux3VPlEib3Im/vEvCAhS2nqI1lPLkihMbMt61XRyBNT/UQttSO2TZCTgtDW3+zC saVxyPC6PaawGrLfIzxn2hiXNLNqNzkHlLqgSrWa5oRq5h6/qoXiayv8CIv+ovX7kuyE HB+7C0OCFn6Zk0Yn45W93dsd3VKcaFxtfFYx0/5gRozy/l3lRrAnVI3e1KtsS6xm/yyG gs2Q== X-Gm-Message-State: APjAAAVdi8t5Xycrets41d/4I7Vs4b/J+CVeJOA6KNGCot/eoUcY98t+ fwe4s2PszMNdhTcRmGSH6GELDWDDQgSiUMNVv+eXGg== X-Google-Smtp-Source: APXvYqzcSSJVTCjIUsx/inzBCCcsnE8pmcRF5dwcpzLSHO9Pe90yz4G+qrRUaeTTS0bQzZw43vk7O2hwjIga6wmmd6k= X-Received: by 2002:a05:6830:2001:: with SMTP id e1mr25512778otp.97.1576423643528; Sun, 15 Dec 2019 07:27:23 -0800 (PST) MIME-Version: 1.0 References: <20191214155614.19004-1-philmd@redhat.com> <20191215044759-mutt-send-email-mst@kernel.org> In-Reply-To: <20191215044759-mutt-send-email-mst@kernel.org> From: Peter Maydell Date: Sun, 15 Dec 2019 15:27:12 +0000 Message-ID: Subject: Re: [PATCH 0/8] Simplify memory_region_add_subregion_overlap(..., priority=0) To: "Michael S. Tsirkin" Cc: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= , QEMU Developers , Andrew Baumann , Aurelien Jarno , kvm-devel , Alex Williamson , Aleksandar Markovic , Joel Stanley , qemu-arm , Marcelo Tosatti , Alistair Francis , Eduardo Habkost , Richard Henderson , Aleksandar Rikalo , Paul Burton , Marcel Apfelbaum , "Edgar E. Iglesias" , Paolo Bonzini Content-Type: text/plain; charset="UTF-8" X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::342 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sun, 15 Dec 2019 15:27:27 -0000 On Sun, 15 Dec 2019 at 09:51, Michael S. Tsirkin wrote: > > On Sat, Dec 14, 2019 at 04:28:08PM +0000, Peter Maydell wrote: > > (It doesn't actually assert that it doesn't > > overlap because we have some legacy uses, notably > > in the x86 PC machines, which do overlap without using > > the right function, which we've never tried to tidy up.) > > It's not exactly legacy uses. > > To be more exact, the way the non overlap versions > are *used* is to mean "I don't care what happens when they overlap" > as opposed to "will never overlap". Almost all of the use of the non-overlap versions is for "these are never going to overlap" -- devices or ram at fixed addresses in the address space that can't ever be mapped over by anything else. If you want "can overlap but I don't care which one wins" then that would be more clearly expressed by using the _overlap() version but just giving everything that can overlap there the same priority. > There are lots of regions where guest can make things overlapping > but doesn't, e.g. PCI BARs can be programmed to overlap > almost anything. > > What happens on real hardware if you then access one of > the BARs is undefined, but programming itself is harmless. > That's why we can't assert. Yeah, good point, for the special case where it's the guest that's determining the addresses where something's mapped we might want to allow the behaviour to fall out of the implementation. (You could instead specify set of priorities that makes the undefined-behaviour something specific, rather than just an emergent property of the implementation QEMU happens to have, but it seems a bit hard to justify.) thanks -- PMM From MAILER-DAEMON Sun Dec 15 18:08:01 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1igczY-0007wJ-3n for mharc-qemu-arm@gnu.org; Sun, 15 Dec 2019 18:08:00 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:33264) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1igczJ-0007lA-8P for qemu-arm@nongnu.org; Sun, 15 Dec 2019 18:07:57 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1igcz9-0004x6-WA for qemu-arm@nongnu.org; Sun, 15 Dec 2019 18:07:45 -0500 Received: from mail-io1-xd29.google.com ([2607:f8b0:4864:20::d29]:35326) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1igcyp-00046p-7e; Sun, 15 Dec 2019 18:07:15 -0500 Received: by mail-io1-xd29.google.com with SMTP id v18so3992361iol.2; Sun, 15 Dec 2019 15:07:14 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=c8dJjvJGo5ZVUxZwxpbG0omE8CCz6DgfoJ0maa0PpO4=; b=G4P3TrEloWyX/3WsK14FdV+iOXSSXx9UTSeU7oovFfuxbh1BszwkQ0jjtb44aczx4N dt7qjxlEpVJTflQECJ7zsQJVEbOKfT504VmWrOiftFfSrdUmoJANGbT8sfeS4ka5JZra ngwz9m2hDTpzwOtwKvMrRL5dDlwnCCC6JOLiK0dPj+QK4Edv06K885r3GoUz3clVoI7N 7EtiuDdcizT0AKhCzvzyOGebgsAWE3WimPYmsUP2XsapZ0eFwothqxvebIfcfidulwf0 62dx0dCoUKlRro8cEY52yKQx6SBDSCrPHXFMdpvad46sbSyDzijpAfd91sqrFxZySzEK L0Cw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=c8dJjvJGo5ZVUxZwxpbG0omE8CCz6DgfoJ0maa0PpO4=; b=NTeidGHNUD1FnimmG4LACPypy+OWk+dQ1cSO+t39YKb3O2HwTYQ7rqc2KA8FDKHEgM jjrgO54zt9EUx9AvL0yM6rQuXiVpqHsjmnXvNItBm/eSXzg+eDHynfbv/vQX1GBzLqHV rmeOLMsFsy+rPpePeCrxu3P7WgGZjIgi0VsY5QvufnOCymgxv9Hb5pPh5xRX/Gb0P+B4 XY1b6pv1Dl6eDANQXsqUH6m7oiznXbpo+PiAbGJN14DB/dOF86yWUoiHa8tfOepov1+B yadrvtVNPq5unf/NqT0bjh/RfANL98SVXwYN03PnWJtn3mr3ZQMlCa6exfl4y3a62ueZ PmQw== X-Gm-Message-State: APjAAAXewUM7bvxz+ryxEU0zjVZjNeRWbq6ecruwOjVGkoTPSjWhoj2t YJyv/wzGBy05jkboanfcundgtkVb3AmAmdVnN7A= X-Google-Smtp-Source: APXvYqw1j50FQ2Xpw4qhlG2QFuo38R3W8A4tM0NVe/n7PgSdTEZHdcmageDTLzqJ8ExZfCc0WgvoOr91Y5JBh9Prsk0= X-Received: by 2002:a5d:8f17:: with SMTP id f23mr16417304iof.265.1576451233238; Sun, 15 Dec 2019 15:07:13 -0800 (PST) MIME-Version: 1.0 References: <20191202210947.3603-1-nieklinnenbank@gmail.com> <20191202210947.3603-10-nieklinnenbank@gmail.com> <6bee15d7-7d80-0709-ac90-ef2052b39329@redhat.com> In-Reply-To: <6bee15d7-7d80-0709-ac90-ef2052b39329@redhat.com> From: Niek Linnenbank Date: Mon, 16 Dec 2019 00:07:01 +0100 Message-ID: Subject: Re: [PATCH 09/10] arm: allwinner-h3: add SD/MMC host controller To: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= Cc: QEMU Developers , qemu-arm , Peter Maydell , Beniamino Galvani Content-Type: multipart/alternative; boundary="000000000000c3573e0599c627e0" X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::d29 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sun, 15 Dec 2019 23:07:58 -0000 --000000000000c3573e0599c627e0 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable On Fri, Dec 13, 2019 at 12:56 AM Philippe Mathieu-Daud=C3=A9 wrote: > Hi Niek, > > On 12/11/19 11:34 PM, Niek Linnenbank wrote: > > Ping! > > > > Anyone would like to comment on this driver? > > > > I finished the rework on all previous comments in this series. > > > > Currently debugging the hflags error reported by Philippe. > > After that, I'm ready to send out v2 of these patches. > > > > Regards, > > Niek > > > > On Mon, Dec 2, 2019 at 10:10 PM Niek Linnenbank > > > wrote: > > > > The Allwinner H3 System on Chip contains an integrated storage > > controller for Secure Digital (SD) and Multi Media Card (MMC) > > interfaces. This commit adds support for the Allwinner H3 > > SD/MMC storage controller with the following emulated features: > > > > * DMA transfers > > * Direct FIFO I/O > > * Short/Long format command responses > > * Auto-Stop command (CMD12) > > * Insert & remove card detection > > > > Signed-off-by: Niek Linnenbank > > > > --- > > hw/arm/allwinner-h3.c | 20 + > > hw/arm/orangepi.c | 17 + > > hw/sd/Makefile.objs | 1 + > > hw/sd/allwinner-h3-sdhost.c | 791 > ++++++++++++++++++++++++++++ > > hw/sd/trace-events | 7 + > > include/hw/arm/allwinner-h3.h | 2 + > > include/hw/sd/allwinner-h3-sdhost.h | 73 +++ > > 7 files changed, 911 insertions(+) > > create mode 100644 hw/sd/allwinner-h3-sdhost.c > > create mode 100644 include/hw/sd/allwinner-h3-sdhost.h > > > > diff --git a/hw/arm/allwinner-h3.c b/hw/arm/allwinner-h3.c > > index 4fc4c8c725..c2972caf88 100644 > > --- a/hw/arm/allwinner-h3.c > > +++ b/hw/arm/allwinner-h3.c > > @@ -50,6 +50,9 @@ static void aw_h3_init(Object *obj) > > > > sysbus_init_child_obj(obj, "sid", &s->sid, sizeof(s->sid), > > TYPE_AW_H3_SID); > > + > > + sysbus_init_child_obj(obj, "mmc0", &s->mmc0, sizeof(s->mmc0), > > + TYPE_AW_H3_SDHOST); > > } > > > > static void aw_h3_realize(DeviceState *dev, Error **errp) > > @@ -217,6 +220,23 @@ static void aw_h3_realize(DeviceState *dev, > > Error **errp) > > } > > sysbus_mmio_map(SYS_BUS_DEVICE(&s->sid), 0, AW_H3_SID_BASE); > > > > + /* SD/MMC */ > > + object_property_set_bool(OBJECT(&s->mmc0), true, "realized", > &err); > > + if (err !=3D NULL) { > > + error_propagate(errp, err); > > + return; > > + } > > + sysbusdev =3D SYS_BUS_DEVICE(&s->mmc0); > > + sysbus_mmio_map(sysbusdev, 0, AW_H3_MMC0_BASE); > > + sysbus_connect_irq(sysbusdev, 0, s->irq[AW_H3_GIC_SPI_MMC0]); > > + > > + object_property_add_alias(OBJECT(s), "sd-bus", OBJECT(&s->mmc0= ), > > + "sd-bus", &err); > > + if (err) { > > + error_propagate(errp, err); > > + return; > > + } > > + > > /* Universal Serial Bus */ > > sysbus_create_simple(TYPE_AW_H3_EHCI, AW_H3_EHCI0_BASE, > > s->irq[AW_H3_GIC_SPI_EHCI0]); > > diff --git a/hw/arm/orangepi.c b/hw/arm/orangepi.c > > index 5ef2735f81..dee3efaf08 100644 > > --- a/hw/arm/orangepi.c > > +++ b/hw/arm/orangepi.c > > @@ -39,6 +39,10 @@ typedef struct OrangePiState { > > static void orangepi_init(MachineState *machine) > > { > > OrangePiState *s =3D g_new(OrangePiState, 1); > > + DriveInfo *di; > > + BlockBackend *blk; > > + BusState *bus; > > + DeviceState *carddev; > > Error *err =3D NULL; > > > > s->h3 =3D AW_H3(object_new(TYPE_AW_H3)); > > @@ -64,6 +68,18 @@ static void orangepi_init(MachineState *machine) > > exit(1); > > } > > > > + /* Create and plug in the SD card */ > > + di =3D drive_get_next(IF_SD); > > + blk =3D di ? blk_by_legacy_dinfo(di) : NULL; > > + bus =3D qdev_get_child_bus(DEVICE(s->h3), "sd-bus"); > > + if (bus =3D=3D NULL) { > > + error_report("No SD/MMC found in H3 object"); > > + exit(1); > > + } > > Your device always creates a bus, so I don't think the if(bus) check is > worthwhile. Eventually use an assert(bus)? > > > + carddev =3D qdev_create(bus, TYPE_SD_CARD); > > + qdev_prop_set_drive(carddev, "drive", blk, &error_fatal); > > + object_property_set_bool(OBJECT(carddev), true, "realized", > > &error_fatal); > > + > > /* RAM */ > > memory_region_allocate_system_memory(&s->sdram, NULL, > > "orangepi.ram", > > machine->ram_size); > > @@ -80,6 +96,7 @@ static void orangepi_machine_init(MachineClass *m= c) > > { > > mc->desc =3D "Orange Pi PC"; > > mc->init =3D orangepi_init; > > + mc->block_default_type =3D IF_SD; > > mc->units_per_default_bus =3D 1; > > mc->min_cpus =3D AW_H3_NUM_CPUS; > > mc->max_cpus =3D AW_H3_NUM_CPUS; > > diff --git a/hw/sd/Makefile.objs b/hw/sd/Makefile.objs > > index a884c238df..e7cc5ab739 100644 > > --- a/hw/sd/Makefile.objs > > +++ b/hw/sd/Makefile.objs > > @@ -4,6 +4,7 @@ common-obj-$(CONFIG_SD) +=3D sd.o core.o > sdmmc-internal.o > > common-obj-$(CONFIG_SDHCI) +=3D sdhci.o > > common-obj-$(CONFIG_SDHCI_PCI) +=3D sdhci-pci.o > > > > +obj-$(CONFIG_ALLWINNER_H3) +=3D allwinner-h3-sdhost.o > > obj-$(CONFIG_MILKYMIST) +=3D milkymist-memcard.o > > obj-$(CONFIG_OMAP) +=3D omap_mmc.o > > obj-$(CONFIG_PXA2XX) +=3D pxa2xx_mmci.o > > diff --git a/hw/sd/allwinner-h3-sdhost.c > b/hw/sd/allwinner-h3-sdhost.c > > new file mode 100644 > > index 0000000000..26e113a144 > > --- /dev/null > > +++ b/hw/sd/allwinner-h3-sdhost.c > > @@ -0,0 +1,791 @@ > > +/* > > + * Allwinner H3 SD Host Controller emulation > > + * > > + * Copyright (C) 2019 Niek Linnenbank > > > > + * > > + * This program is free software: you can redistribute it and/or > modify > > + * it under the terms of the GNU General Public License as > published by > > + * the Free Software Foundation, either version 2 of the License, = or > > + * (at your option) any later version. > > + * > > + * This program is distributed in the hope that it will be useful, > > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > > + * GNU General Public License for more details. > > + * > > + * You should have received a copy of the GNU General Public Licen= se > > + * along with this program. If not, see > > . > > + */ > > + > > +#include "qemu/osdep.h" > > +#include "qemu/log.h" > > +#include "qemu/module.h" > > +#include "sysemu/blockdev.h" > > +#include "hw/irq.h" > > +#include "hw/sd/allwinner-h3-sdhost.h" > > +#include "migration/vmstate.h" > > +#include "trace.h" > > + > > +#define TYPE_AW_H3_SDHOST_BUS "allwinner-h3-sdhost-bus" > > +#define AW_H3_SDHOST_BUS(obj) \ > > + OBJECT_CHECK(SDBus, (obj), TYPE_AW_H3_SDHOST_BUS) > > + > > +/* SD Host register offsets */ > > +#define REG_SD_GCTL (0x00) /* Global Control */ > > +#define REG_SD_CKCR (0x04) /* Clock Control */ > > +#define REG_SD_TMOR (0x08) /* Timeout */ > > +#define REG_SD_BWDR (0x0C) /* Bus Width */ > > +#define REG_SD_BKSR (0x10) /* Block Size */ > > +#define REG_SD_BYCR (0x14) /* Byte Count */ > > +#define REG_SD_CMDR (0x18) /* Command */ > > +#define REG_SD_CAGR (0x1C) /* Command Argument */ > > +#define REG_SD_RESP0 (0x20) /* Response Zero */ > > +#define REG_SD_RESP1 (0x24) /* Response One */ > > +#define REG_SD_RESP2 (0x28) /* Response Two */ > > +#define REG_SD_RESP3 (0x2C) /* Response Three */ > > +#define REG_SD_IMKR (0x30) /* Interrupt Mask */ > > +#define REG_SD_MISR (0x34) /* Masked Interrupt Status */ > > +#define REG_SD_RISR (0x38) /* Raw Interrupt Status */ > > +#define REG_SD_STAR (0x3C) /* Status */ > > +#define REG_SD_FWLR (0x40) /* FIFO Water Level */ > > +#define REG_SD_FUNS (0x44) /* FIFO Function Select */ > > +#define REG_SD_DBGC (0x50) /* Debug Enable */ > > +#define REG_SD_A12A (0x58) /* Auto command 12 argument */ > > +#define REG_SD_NTSR (0x5C) /* SD NewTiming Set */ > > +#define REG_SD_SDBG (0x60) /* SD newTiming Set Debug */ > > +#define REG_SD_HWRST (0x78) /* Hardware Reset Register */ > > +#define REG_SD_DMAC (0x80) /* Internal DMA Controller > > Control */ > > +#define REG_SD_DLBA (0x84) /* Descriptor List Base Address > */ > > +#define REG_SD_IDST (0x88) /* Internal DMA Controller > Status */ > > +#define REG_SD_IDIE (0x8C) /* Internal DMA Controller IRQ > > Enable */ > > +#define REG_SD_THLDC (0x100) /* Card Threshold Control */ > > +#define REG_SD_DSBD (0x10C) /* eMMC DDR Start Bit Detection > > Control */ > > +#define REG_SD_RES_CRC (0x110) /* Response CRC from card/eMMC = */ > > +#define REG_SD_DATA7_CRC (0x114) /* CRC Data 7 from card/eMMC */ > > +#define REG_SD_DATA6_CRC (0x118) /* CRC Data 6 from card/eMMC */ > > +#define REG_SD_DATA5_CRC (0x11C) /* CRC Data 5 from card/eMMC */ > > +#define REG_SD_DATA4_CRC (0x120) /* CRC Data 4 from card/eMMC */ > > +#define REG_SD_DATA3_CRC (0x124) /* CRC Data 3 from card/eMMC */ > > +#define REG_SD_DATA2_CRC (0x128) /* CRC Data 2 from card/eMMC */ > > +#define REG_SD_DATA1_CRC (0x12C) /* CRC Data 1 from card/eMMC */ > > +#define REG_SD_DATA0_CRC (0x130) /* CRC Data 0 from card/eMMC */ > > +#define REG_SD_CRC_STA (0x134) /* CRC status from card/eMMC > > during write */ > > +#define REG_SD_FIFO (0x200) /* Read/Write FIFO */ > > + > > +/* SD Host register flags */ > > +#define SD_GCTL_FIFO_AC_MOD (1 << 31) > > +#define SD_GCTL_DDR_MOD_SEL (1 << 10) > > +#define SD_GCTL_CD_DBC_ENB (1 << 8) > > +#define SD_GCTL_DMA_ENB (1 << 5) > > +#define SD_GCTL_INT_ENB (1 << 4) > > +#define SD_GCTL_DMA_RST (1 << 2) > > +#define SD_GCTL_FIFO_RST (1 << 1) > > +#define SD_GCTL_SOFT_RST (1 << 0) > > + > > +#define SD_CMDR_LOAD (1 << 31) > > +#define SD_CMDR_CLKCHANGE (1 << 21) > > +#define SD_CMDR_WRITE (1 << 10) > > +#define SD_CMDR_AUTOSTOP (1 << 12) > > +#define SD_CMDR_DATA (1 << 9) > > +#define SD_CMDR_RESPONSE_LONG (1 << 7) > > +#define SD_CMDR_RESPONSE (1 << 6) > > +#define SD_CMDR_CMDID_MASK (0x3f) > > + > > +#define SD_RISR_CARD_REMOVE (1 << 31) > > +#define SD_RISR_CARD_INSERT (1 << 30) > > +#define SD_RISR_AUTOCMD_DONE (1 << 14) > > +#define SD_RISR_DATA_COMPLETE (1 << 3) > > +#define SD_RISR_CMD_COMPLETE (1 << 2) > > +#define SD_RISR_NO_RESPONSE (1 << 1) > > + > > +#define SD_STAR_CARD_PRESENT (1 << 8) > > + > > +#define SD_IDST_SUM_RECEIVE_IRQ (1 << 8) > > +#define SD_IDST_RECEIVE_IRQ (1 << 1) > > +#define SD_IDST_TRANSMIT_IRQ (1 << 0) > > +#define SD_IDST_IRQ_MASK (SD_IDST_RECEIVE_IRQ | > > SD_IDST_TRANSMIT_IRQ | \ > > + SD_IDST_SUM_RECEIVE_IRQ) > > +#define SD_IDST_WR_MASK (0x3ff) > > + > > +/* SD Host register reset values */ > > +#define REG_SD_GCTL_RST (0x00000300) > > +#define REG_SD_CKCR_RST (0x0) > > +#define REG_SD_TMOR_RST (0xFFFFFF40) > > +#define REG_SD_BWDR_RST (0x0) > > +#define REG_SD_BKSR_RST (0x00000200) > > +#define REG_SD_BYCR_RST (0x00000200) > > +#define REG_SD_CMDR_RST (0x0) > > +#define REG_SD_CAGR_RST (0x0) > > +#define REG_SD_RESP_RST (0x0) > > +#define REG_SD_IMKR_RST (0x0) > > +#define REG_SD_MISR_RST (0x0) > > +#define REG_SD_RISR_RST (0x0) > > +#define REG_SD_STAR_RST (0x00000100) > > +#define REG_SD_FWLR_RST (0x000F0000) > > +#define REG_SD_FUNS_RST (0x0) > > +#define REG_SD_DBGC_RST (0x0) > > +#define REG_SD_A12A_RST (0x0000FFFF) > > +#define REG_SD_NTSR_RST (0x00000001) > > +#define REG_SD_SDBG_RST (0x0) > > +#define REG_SD_HWRST_RST (0x00000001) > > +#define REG_SD_DMAC_RST (0x0) > > +#define REG_SD_DLBA_RST (0x0) > > +#define REG_SD_IDST_RST (0x0) > > +#define REG_SD_IDIE_RST (0x0) > > +#define REG_SD_THLDC_RST (0x0) > > +#define REG_SD_DSBD_RST (0x0) > > +#define REG_SD_RES_CRC_RST (0x0) > > +#define REG_SD_DATA_CRC_RST (0x0) > > +#define REG_SD_CRC_STA_RST (0x0) > > +#define REG_SD_FIFO_RST (0x0) > > + > > +/* Data transfer descriptor for DMA */ > > +typedef struct TransferDescriptor { > > + uint32_t status; /* Status flags */ > > + uint32_t size; /* Data buffer size */ > > + uint32_t addr; /* Data buffer address */ > > + uint32_t next; /* Physical address of next descriptor */ > > +} TransferDescriptor; > > + > > +/* Data transfer descriptor flags */ > > +#define DESC_STATUS_HOLD (1 << 31) /* Set when descriptor is in > > use by DMA */ > > +#define DESC_STATUS_ERROR (1 << 30) /* Set when DMA transfer erro= r > > occurred */ > > +#define DESC_STATUS_CHAIN (1 << 4) /* Indicates chained > > descriptor. */ > > +#define DESC_STATUS_FIRST (1 << 3) /* Set on the first descripto= r > */ > > +#define DESC_STATUS_LAST (1 << 2) /* Set on the last descriptor > */ > > +#define DESC_STATUS_NOIRQ (1 << 1) /* Skip raising interrupt > > after transfer */ > > + > > +#define DESC_SIZE_MASK (0xfffffffc) > > + > > +static void aw_h3_sdhost_update_irq(AwH3SDHostState *s) > > +{ > > + uint32_t irq_en =3D s->global_ctl & SD_GCTL_INT_ENB; > > + uint32_t irq =3D irq_en ? s->irq_status & s->irq_mask : 0; > > The previous line is confuse, either use parenthesis or a if statement. > > uint32_t irq =3D irq_en ? (s->irq_status & s->irq_mask) : 0; > > > + > > + trace_aw_h3_sdhost_update_irq(irq); > > + qemu_set_irq(s->irq, irq); > > +} > > + > > +static void aw_h3_sdhost_update_transfer_cnt(AwH3SDHostState *s, > > uint32_t bytes) > > +{ > > + if (s->transfer_cnt > bytes) { > > + s->transfer_cnt -=3D bytes; > > + } else { > > + s->transfer_cnt =3D 0; > > + } > > + > > + if (!s->transfer_cnt) { > > + s->irq_status |=3D SD_RISR_DATA_COMPLETE | > SD_RISR_AUTOCMD_DONE; > > + } > > +} > > + > > +static void aw_h3_sdhost_set_inserted(DeviceState *dev, bool > inserted) > > +{ > > + AwH3SDHostState *s =3D AW_H3_SDHOST(dev); > > + > > + trace_aw_h3_sdhost_set_inserted(inserted); > > + > > + if (inserted) { > > + s->irq_status |=3D SD_RISR_CARD_INSERT; > > + s->irq_status &=3D ~SD_RISR_CARD_REMOVE; > > + s->status |=3D SD_STAR_CARD_PRESENT; > > + } else { > > + s->irq_status &=3D ~SD_RISR_CARD_INSERT; > > + s->irq_status |=3D SD_RISR_CARD_REMOVE; > > + s->status &=3D ~SD_STAR_CARD_PRESENT; > > + } > > + > > + aw_h3_sdhost_update_irq(s); > > +} > > + > > +static void aw_h3_sdhost_send_command(AwH3SDHostState *s) > > +{ > > + SDRequest request; > > + uint8_t resp[16]; > > + int rlen; > > + > > + /* Auto clear load flag */ > > + s->command &=3D ~SD_CMDR_LOAD; > > + > > + /* Clock change does not actually interact with the SD bus */ > > + if (!(s->command & SD_CMDR_CLKCHANGE)) { > > + > > + /* Prepare request */ > > + request.cmd =3D s->command & SD_CMDR_CMDID_MASK; > > + request.arg =3D s->command_arg; > > + > > + /* Send request to SD bus */ > > + rlen =3D sdbus_do_command(&s->sdbus, &request, resp); > > + if (rlen < 0) { > > + goto error; > > + } > > + > > + /* If the command has a response, store it in the response > > registers */ > > + if ((s->command & SD_CMDR_RESPONSE)) { > > + if (rlen =3D=3D 0 || > > + (rlen =3D=3D 4 && (s->command & SD_CMDR_RESPONSE_LO= NG))) > { > > + goto error; > > + } > > + if (rlen !=3D 4 && rlen !=3D 16) { > > + goto error; > > + } > > Maybe remove previous if... > > > + if (rlen =3D=3D 4) { > > + s->response[0] =3D ldl_be_p(&resp[0]); > > + s->response[1] =3D s->response[2] =3D s->response[= 3] =3D > 0; > > + } else { > > ... > > } else if (rlen =3D=3D 16) { ... > > > + s->response[0] =3D ldl_be_p(&resp[12]); > > + s->response[1] =3D ldl_be_p(&resp[8]); > > + s->response[2] =3D ldl_be_p(&resp[4]); > > + s->response[3] =3D ldl_be_p(&resp[0]); > > ... > > } else { > goto error; > > > + } > > + } > > + } > > + > > + /* Set interrupt status bits */ > > + s->irq_status |=3D SD_RISR_CMD_COMPLETE; > > + return; > > + > > +error: > > + s->irq_status |=3D SD_RISR_NO_RESPONSE; > > +} > > + > > +static void aw_h3_sdhost_auto_stop(AwH3SDHostState *s) > > +{ > > + /* > > + * The stop command (CMD12) ensures the SD bus > > + * returns to the transfer state. > > + */ > > + if ((s->command & SD_CMDR_AUTOSTOP) && (s->transfer_cnt =3D=3D= 0)) { > > + /* First save current command registers */ > > + uint32_t saved_cmd =3D s->command; > > + uint32_t saved_arg =3D s->command_arg; > > + > > + /* Prepare stop command (CMD12) */ > > + s->command &=3D ~SD_CMDR_CMDID_MASK; > > + s->command |=3D 12; /* CMD12 */ > > + s->command_arg =3D 0; > > + > > + /* Put the command on SD bus */ > > + aw_h3_sdhost_send_command(s); > > + > > + /* Restore command values */ > > + s->command =3D saved_cmd; > > + s->command_arg =3D saved_arg; > > + } > > +} > > + > > +static uint32_t aw_h3_sdhost_process_desc(AwH3SDHostState *s, > > + hwaddr desc_addr, > > + TransferDescriptor *desc= , > > + bool is_write, uint32_t > > max_bytes) > > +{ > > + uint32_t num_done =3D 0; > > + uint32_t num_bytes =3D max_bytes; > > + uint8_t buf[1024]; > > + > > + /* Read descriptor */ > > + cpu_physical_memory_read(desc_addr, desc, sizeof(*desc)); > > Should we worry about endianess here? > I tried to figure out what is expected, but the Allwinner_H3_Datasheet_V1.2.pdf does not explicitly mention endianness for any of its I/O devices. Currently it seems all devices are happy with using the same endianness as the CPUs. In the MemoryRegionOps has DEVICE_NATIVE_ENDIAN set to match the behavior seen. > > > + if (desc->size =3D=3D 0) { > > + desc->size =3D 0xffff + 1; > > Why not write '64 * KiB'? > > > + } > > + if (desc->size < num_bytes) { > > + num_bytes =3D desc->size; > > + } > > + > > + trace_aw_h3_sdhost_process_desc(desc_addr, desc->size, > > is_write, max_bytes); > > + > > + while (num_done < num_bytes) { > > + /* Try to completely fill the local buffer */ > > + uint32_t buf_bytes =3D num_bytes - num_done; > > + if (buf_bytes > sizeof(buf)) { > > + buf_bytes =3D sizeof(buf); > > + } > > + > > + /* Write to SD bus */ > > + if (is_write) { > > + cpu_physical_memory_read((desc->addr & DESC_SIZE_MASK) > > + num_done, > > + buf, buf_bytes); > > + > > + for (uint32_t i =3D 0; i < buf_bytes; i++) { > > + sdbus_write_data(&s->sdbus, buf[i]); > > + } > > + > > + /* Read from SD bus */ > > + } else { > > + for (uint32_t i =3D 0; i < buf_bytes; i++) { > > + buf[i] =3D sdbus_read_data(&s->sdbus); > > + } > > + cpu_physical_memory_write((desc->addr & DESC_SIZE_MASK= ) > > + num_done, > > + buf, buf_bytes); > > + } > > + num_done +=3D buf_bytes; > > + } > > + > > + /* Clear hold flag and flush descriptor */ > > + desc->status &=3D ~DESC_STATUS_HOLD; > > + cpu_physical_memory_write(desc_addr, desc, sizeof(*desc)); > > (Related to previous endianess question). > > > + > > + return num_done; > > +} > > + > > +static void aw_h3_sdhost_dma(AwH3SDHostState *s) > > +{ > > + TransferDescriptor desc; > > + hwaddr desc_addr =3D s->desc_base; > > + bool is_write =3D (s->command & SD_CMDR_WRITE); > > + uint32_t bytes_done =3D 0; > > + > > + /* Check if DMA can be performed */ > > + if (s->byte_count =3D=3D 0 || s->block_size =3D=3D 0 || > > + !(s->global_ctl & SD_GCTL_DMA_ENB)) { > > + return; > > + } > > + > > + /* > > + * For read operations, data must be available on the SD bus > > + * If not, it is an error and we should not act at all > > + */ > > + if (!is_write && !sdbus_data_ready(&s->sdbus)) { > > + return; > > + } > > + > > + /* Process the DMA descriptors until all data is copied */ > > + while (s->byte_count > 0) { > > + bytes_done =3D aw_h3_sdhost_process_desc(s, desc_addr, &de= sc, > > + is_write, > > s->byte_count); > > + aw_h3_sdhost_update_transfer_cnt(s, bytes_done); > > + > > + if (bytes_done <=3D s->byte_count) { > > + s->byte_count -=3D bytes_done; > > + } else { > > + s->byte_count =3D 0; > > + } > > + > > + if (desc.status & DESC_STATUS_LAST) { > > + break; > > + } else { > > + desc_addr =3D desc.next; > > + } > > + } > > + > > + /* Raise IRQ to signal DMA is completed */ > > + s->irq_status |=3D SD_RISR_DATA_COMPLETE | SD_RISR_AUTOCMD_DON= E; > > + > > + /* Update DMAC bits */ > > + if (is_write) { > > + s->dmac_status |=3D SD_IDST_TRANSMIT_IRQ; > > + } else { > > + s->dmac_status |=3D (SD_IDST_SUM_RECEIVE_IRQ | > > SD_IDST_RECEIVE_IRQ); > > + } > > +} > > + > > +static uint64_t aw_h3_sdhost_read(void *opaque, hwaddr offset, > > + unsigned size) > > +{ > > + AwH3SDHostState *s =3D (AwH3SDHostState *)opaque; > > + uint32_t res =3D 0; > > + > > + switch (offset) { > > + case REG_SD_GCTL: /* Global Control */ > > + res =3D s->global_ctl; > > + break; > > + case REG_SD_CKCR: /* Clock Control */ > > + res =3D s->clock_ctl; > > + break; > > + case REG_SD_TMOR: /* Timeout */ > > + res =3D s->timeout; > > + break; > > + case REG_SD_BWDR: /* Bus Width */ > > + res =3D s->bus_width; > > + break; > > + case REG_SD_BKSR: /* Block Size */ > > + res =3D s->block_size; > > + break; > > + case REG_SD_BYCR: /* Byte Count */ > > + res =3D s->byte_count; > > + break; > > + case REG_SD_CMDR: /* Command */ > > + res =3D s->command; > > + break; > > + case REG_SD_CAGR: /* Command Argument */ > > + res =3D s->command_arg; > > + break; > > + case REG_SD_RESP0: /* Response Zero */ > > + res =3D s->response[0]; > > + break; > > + case REG_SD_RESP1: /* Response One */ > > + res =3D s->response[1]; > > + break; > > + case REG_SD_RESP2: /* Response Two */ > > + res =3D s->response[2]; > > + break; > > + case REG_SD_RESP3: /* Response Three */ > > + res =3D s->response[3]; > > + break; > > + case REG_SD_IMKR: /* Interrupt Mask */ > > + res =3D s->irq_mask; > > + break; > > + case REG_SD_MISR: /* Masked Interrupt Status */ > > + res =3D s->irq_status & s->irq_mask; > > + break; > > + case REG_SD_RISR: /* Raw Interrupt Status */ > > + res =3D s->irq_status; > > + break; > > + case REG_SD_STAR: /* Status */ > > + res =3D s->status; > > + break; > > + case REG_SD_FWLR: /* FIFO Water Level */ > > + res =3D s->fifo_wlevel; > > + break; > > + case REG_SD_FUNS: /* FIFO Function Select */ > > + res =3D s->fifo_func_sel; > > + break; > > + case REG_SD_DBGC: /* Debug Enable */ > > + res =3D s->debug_enable; > > + break; > > + case REG_SD_A12A: /* Auto command 12 argument */ > > + res =3D s->auto12_arg; > > + break; > > + case REG_SD_NTSR: /* SD NewTiming Set */ > > + res =3D s->newtiming_set; > > + break; > > + case REG_SD_SDBG: /* SD newTiming Set Debug */ > > + res =3D s->newtiming_debug; > > + break; > > + case REG_SD_HWRST: /* Hardware Reset Register */ > > + res =3D s->hardware_rst; > > + break; > > + case REG_SD_DMAC: /* Internal DMA Controller Control */ > > + res =3D s->dmac; > > + break; > > + case REG_SD_DLBA: /* Descriptor List Base Address */ > > + res =3D s->desc_base; > > + break; > > + case REG_SD_IDST: /* Internal DMA Controller Status */ > > + res =3D s->dmac_status; > > + break; > > + case REG_SD_IDIE: /* Internal DMA Controller Interrupt > > Enable */ > > + res =3D s->dmac_irq; > > + break; > > + case REG_SD_THLDC: /* Card Threshold Control */ > > + res =3D s->card_threshold; > > + break; > > + case REG_SD_DSBD: /* eMMC DDR Start Bit Detection Control > */ > > + res =3D s->startbit_detect; > > + break; > > + case REG_SD_RES_CRC: /* Response CRC from card/eMMC */ > > + res =3D s->response_crc; > > + break; > > + case REG_SD_DATA7_CRC: /* CRC Data 7 from card/eMMC */ > > + case REG_SD_DATA6_CRC: /* CRC Data 6 from card/eMMC */ > > + case REG_SD_DATA5_CRC: /* CRC Data 5 from card/eMMC */ > > + case REG_SD_DATA4_CRC: /* CRC Data 4 from card/eMMC */ > > + case REG_SD_DATA3_CRC: /* CRC Data 3 from card/eMMC */ > > + case REG_SD_DATA2_CRC: /* CRC Data 2 from card/eMMC */ > > + case REG_SD_DATA1_CRC: /* CRC Data 1 from card/eMMC */ > > + case REG_SD_DATA0_CRC: /* CRC Data 0 from card/eMMC */ > > + res =3D s->data_crc[((offset - REG_SD_DATA7_CRC) / > > sizeof(uint32_t))]; > > + break; > > + case REG_SD_CRC_STA: /* CRC status from card/eMMC in write > > operation */ > > + res =3D s->status_crc; > > + break; > > + case REG_SD_FIFO: /* Read/Write FIFO */ > > + if (sdbus_data_ready(&s->sdbus)) { > > + res =3D sdbus_read_data(&s->sdbus); > > + res |=3D sdbus_read_data(&s->sdbus) << 8; > > + res |=3D sdbus_read_data(&s->sdbus) << 16; > > + res |=3D sdbus_read_data(&s->sdbus) << 24; > > + aw_h3_sdhost_update_transfer_cnt(s, sizeof(uint32_t)); > > + aw_h3_sdhost_auto_stop(s); > > + aw_h3_sdhost_update_irq(s); > > + } else { > > + qemu_log_mask(LOG_GUEST_ERROR, "%s: no data ready on S= D > > bus\n", > > + __func__); > > + } > > + break; > > + default: > > + qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset > > %"HWADDR_PRIx"\n", > > + __func__, offset); > > + res =3D 0; > > + break; > > + } > > + > > + trace_aw_h3_sdhost_read(offset, res, size); > > + return res; > > +} > > + > > +static void aw_h3_sdhost_write(void *opaque, hwaddr offset, > > + uint64_t value, unsigned size) > > +{ > > + AwH3SDHostState *s =3D (AwH3SDHostState *)opaque; > > + > > + trace_aw_h3_sdhost_write(offset, value, size); > > + > > + switch (offset) { > > + case REG_SD_GCTL: /* Global Control */ > > + s->global_ctl =3D value; > > + s->global_ctl &=3D ~(SD_GCTL_DMA_RST | SD_GCTL_FIFO_RST | > > + SD_GCTL_SOFT_RST); > > + aw_h3_sdhost_update_irq(s); > > + break; > > + case REG_SD_CKCR: /* Clock Control */ > > + s->clock_ctl =3D value; > > + break; > > + case REG_SD_TMOR: /* Timeout */ > > + s->timeout =3D value; > > + break; > > + case REG_SD_BWDR: /* Bus Width */ > > + s->bus_width =3D value; > > + break; > > + case REG_SD_BKSR: /* Block Size */ > > + s->block_size =3D value; > > + break; > > + case REG_SD_BYCR: /* Byte Count */ > > + s->byte_count =3D value; > > + s->transfer_cnt =3D value; > > + break; > > + case REG_SD_CMDR: /* Command */ > > + s->command =3D value; > > + if (value & SD_CMDR_LOAD) { > > + aw_h3_sdhost_send_command(s); > > + aw_h3_sdhost_dma(s); > > + aw_h3_sdhost_auto_stop(s); > > + } > > + aw_h3_sdhost_update_irq(s); > > + break; > > + case REG_SD_CAGR: /* Command Argument */ > > + s->command_arg =3D value; > > + break; > > + case REG_SD_RESP0: /* Response Zero */ > > + s->response[0] =3D value; > > + break; > > + case REG_SD_RESP1: /* Response One */ > > + s->response[1] =3D value; > > + break; > > + case REG_SD_RESP2: /* Response Two */ > > + s->response[2] =3D value; > > + break; > > + case REG_SD_RESP3: /* Response Three */ > > + s->response[3] =3D value; > > + break; > > + case REG_SD_IMKR: /* Interrupt Mask */ > > + s->irq_mask =3D value; > > + aw_h3_sdhost_update_irq(s); > > + break; > > + case REG_SD_MISR: /* Masked Interrupt Status */ > > + case REG_SD_RISR: /* Raw Interrupt Status */ > > + s->irq_status &=3D ~value; > > + aw_h3_sdhost_update_irq(s); > > + break; > > + case REG_SD_STAR: /* Status */ > > + s->status &=3D ~value; > > + aw_h3_sdhost_update_irq(s); > > + break; > > + case REG_SD_FWLR: /* FIFO Water Level */ > > + s->fifo_wlevel =3D value; > > + break; > > + case REG_SD_FUNS: /* FIFO Function Select */ > > + s->fifo_func_sel =3D value; > > + break; > > + case REG_SD_DBGC: /* Debug Enable */ > > + s->debug_enable =3D value; > > + break; > > + case REG_SD_A12A: /* Auto command 12 argument */ > > + s->auto12_arg =3D value; > > + break; > > + case REG_SD_NTSR: /* SD NewTiming Set */ > > + s->newtiming_set =3D value; > > + break; > > + case REG_SD_SDBG: /* SD newTiming Set Debug */ > > + s->newtiming_debug =3D value; > > + break; > > + case REG_SD_HWRST: /* Hardware Reset Register */ > > + s->hardware_rst =3D value; > > + break; > > + case REG_SD_DMAC: /* Internal DMA Controller Control */ > > + s->dmac =3D value; > > + aw_h3_sdhost_update_irq(s); > > + break; > > + case REG_SD_DLBA: /* Descriptor List Base Address */ > > + s->desc_base =3D value; > > + break; > > + case REG_SD_IDST: /* Internal DMA Controller Status */ > > + s->dmac_status &=3D (~SD_IDST_WR_MASK) | (~value & > > SD_IDST_WR_MASK); > > + aw_h3_sdhost_update_irq(s); > > + break; > > + case REG_SD_IDIE: /* Internal DMA Controller Interrupt > > Enable */ > > + s->dmac_irq =3D value; > > + aw_h3_sdhost_update_irq(s); > > + break; > > + case REG_SD_THLDC: /* Card Threshold Control */ > > + s->card_threshold =3D value; > > + break; > > + case REG_SD_DSBD: /* eMMC DDR Start Bit Detection Control > */ > > + s->startbit_detect =3D value; > > + break; > > + case REG_SD_FIFO: /* Read/Write FIFO */ > > + sdbus_write_data(&s->sdbus, value & 0xff); > > + sdbus_write_data(&s->sdbus, (value >> 8) & 0xff); > > + sdbus_write_data(&s->sdbus, (value >> 16) & 0xff); > > + sdbus_write_data(&s->sdbus, (value >> 24) & 0xff); > > + aw_h3_sdhost_update_transfer_cnt(s, sizeof(uint32_t)); > > + aw_h3_sdhost_auto_stop(s); > > + aw_h3_sdhost_update_irq(s); > > + break; > > + case REG_SD_RES_CRC: /* Response CRC from card/eMMC */ > > + case REG_SD_DATA7_CRC: /* CRC Data 7 from card/eMMC */ > > + case REG_SD_DATA6_CRC: /* CRC Data 6 from card/eMMC */ > > + case REG_SD_DATA5_CRC: /* CRC Data 5 from card/eMMC */ > > + case REG_SD_DATA4_CRC: /* CRC Data 4 from card/eMMC */ > > + case REG_SD_DATA3_CRC: /* CRC Data 3 from card/eMMC */ > > + case REG_SD_DATA2_CRC: /* CRC Data 2 from card/eMMC */ > > + case REG_SD_DATA1_CRC: /* CRC Data 1 from card/eMMC */ > > + case REG_SD_DATA0_CRC: /* CRC Data 0 from card/eMMC */ > > + case REG_SD_CRC_STA: /* CRC status from card/eMMC in write > > operation */ > > + break; > > + default: > > + qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset > > %"HWADDR_PRIx"\n", > > + __func__, offset); > > + break; > > + } > > +} > > + > > +static const MemoryRegionOps aw_h3_sdhost_ops =3D { > > + .read =3D aw_h3_sdhost_read, > > + .write =3D aw_h3_sdhost_write, > > + .endianness =3D DEVICE_NATIVE_ENDIAN, > > I haven't checked .valid accesses from the datasheet. > > However due to: > > res =3D s->data_crc[((offset - REG_SD_DATA7_CRC) / sizeof(uint32_t))]; > > You seem to expect: > > .impl.min_access_size =3D 4, > > .impl.max_access_size unset is 8, which should works. > > It seems that all registers are aligned on at least 32-bit boundaries. An= d the section 5.3.5.1 mentions that the DMA descriptors must be stored in memory 32-bit aligned. So based on that information, I think 32-bit is a safe choice. I've verified this with Linux mainline and U-Boot drivers and both are still working. > > +}; > > + > > +static const VMStateDescription vmstate_aw_h3_sdhost =3D { > > + .name =3D TYPE_AW_H3_SDHOST, > > Do not use TYPE name in VMStateDescription.name, because we might change > the value of TYPE, but the migration state has to keep the same name. > > OK thanks, I will make that changes in the other commits as well. > > + .version_id =3D 1, > > + .minimum_version_id =3D 1, > > + .fields =3D (VMStateField[]) { > > + VMSTATE_UINT32(global_ctl, AwH3SDHostState), > > + VMSTATE_UINT32(clock_ctl, AwH3SDHostState), > > + VMSTATE_UINT32(timeout, AwH3SDHostState), > > + VMSTATE_UINT32(bus_width, AwH3SDHostState), > > + VMSTATE_UINT32(block_size, AwH3SDHostState), > > + VMSTATE_UINT32(byte_count, AwH3SDHostState), > > + VMSTATE_UINT32(transfer_cnt, AwH3SDHostState), > > + VMSTATE_UINT32(command, AwH3SDHostState), > > + VMSTATE_UINT32(command_arg, AwH3SDHostState), > > + VMSTATE_UINT32_ARRAY(response, AwH3SDHostState, 4), > > + VMSTATE_UINT32(irq_mask, AwH3SDHostState), > > + VMSTATE_UINT32(irq_status, AwH3SDHostState), > > + VMSTATE_UINT32(status, AwH3SDHostState), > > + VMSTATE_UINT32(fifo_wlevel, AwH3SDHostState), > > + VMSTATE_UINT32(fifo_func_sel, AwH3SDHostState), > > + VMSTATE_UINT32(debug_enable, AwH3SDHostState), > > + VMSTATE_UINT32(auto12_arg, AwH3SDHostState), > > + VMSTATE_UINT32(newtiming_set, AwH3SDHostState), > > + VMSTATE_UINT32(newtiming_debug, AwH3SDHostState), > > + VMSTATE_UINT32(hardware_rst, AwH3SDHostState), > > + VMSTATE_UINT32(dmac, AwH3SDHostState), > > + VMSTATE_UINT32(desc_base, AwH3SDHostState), > > + VMSTATE_UINT32(dmac_status, AwH3SDHostState), > > + VMSTATE_UINT32(dmac_irq, AwH3SDHostState), > > + VMSTATE_UINT32(card_threshold, AwH3SDHostState), > > + VMSTATE_UINT32(startbit_detect, AwH3SDHostState), > > + VMSTATE_UINT32(response_crc, AwH3SDHostState), > > + VMSTATE_UINT32_ARRAY(data_crc, AwH3SDHostState, 8), > > + VMSTATE_UINT32(status_crc, AwH3SDHostState), > > + VMSTATE_END_OF_LIST() > > + } > > +}; > > + > > +static void aw_h3_sdhost_init(Object *obj) > > +{ > > + AwH3SDHostState *s =3D AW_H3_SDHOST(obj); > > + > > + qbus_create_inplace(&s->sdbus, sizeof(s->sdbus), > > + TYPE_AW_H3_SDHOST_BUS, DEVICE(s), "sd-bus"= ); > > + > > + memory_region_init_io(&s->iomem, obj, &aw_h3_sdhost_ops, s, > > + TYPE_AW_H3_SDHOST, > > AW_H3_SDHOST_REGS_MEM_SIZE); > > + sysbus_init_mmio(SYS_BUS_DEVICE(s), &s->iomem); > > + sysbus_init_irq(SYS_BUS_DEVICE(s), &s->irq); > > +} > > + > > +static void aw_h3_sdhost_reset(DeviceState *dev) > > +{ > > + AwH3SDHostState *s =3D AW_H3_SDHOST(dev); > > + > > + s->global_ctl =3D REG_SD_GCTL_RST; > > + s->clock_ctl =3D REG_SD_CKCR_RST; > > + s->timeout =3D REG_SD_TMOR_RST; > > + s->bus_width =3D REG_SD_BWDR_RST; > > + s->block_size =3D REG_SD_BKSR_RST; > > + s->byte_count =3D REG_SD_BYCR_RST; > > + s->transfer_cnt =3D 0; > > + > > + s->command =3D REG_SD_CMDR_RST; > > + s->command_arg =3D REG_SD_CAGR_RST; > > + > > + for (int i =3D 0; i < sizeof(s->response) / > > sizeof(s->response[0]); i++) { > > Please use ARRAY_SIZE(s->response). > > > + s->response[i] =3D REG_SD_RESP_RST; > > + } > > + > > + s->irq_mask =3D REG_SD_IMKR_RST; > > + s->irq_status =3D REG_SD_RISR_RST; > > + s->status =3D REG_SD_STAR_RST; > > + > > + s->fifo_wlevel =3D REG_SD_FWLR_RST; > > + s->fifo_func_sel =3D REG_SD_FUNS_RST; > > + s->debug_enable =3D REG_SD_DBGC_RST; > > + s->auto12_arg =3D REG_SD_A12A_RST; > > + s->newtiming_set =3D REG_SD_NTSR_RST; > > + s->newtiming_debug =3D REG_SD_SDBG_RST; > > + s->hardware_rst =3D REG_SD_HWRST_RST; > > + s->dmac =3D REG_SD_DMAC_RST; > > + s->desc_base =3D REG_SD_DLBA_RST; > > + s->dmac_status =3D REG_SD_IDST_RST; > > + s->dmac_irq =3D REG_SD_IDIE_RST; > > + s->card_threshold =3D REG_SD_THLDC_RST; > > + s->startbit_detect =3D REG_SD_DSBD_RST; > > + s->response_crc =3D REG_SD_RES_CRC_RST; > > + > > + for (int i =3D 0; i < sizeof(s->data_crc) / > > sizeof(s->data_crc[0]); i++) { > > ARRAY_SIZE > > > + s->data_crc[i] =3D REG_SD_DATA_CRC_RST; > > + } > > + > > + s->status_crc =3D REG_SD_CRC_STA_RST; > > +} > > + > > +static void aw_h3_sdhost_bus_class_init(ObjectClass *klass, void > *data) > > +{ > > + SDBusClass *sbc =3D SD_BUS_CLASS(klass); > > + > > + sbc->set_inserted =3D aw_h3_sdhost_set_inserted; > > +} > > + > > +static void aw_h3_sdhost_class_init(ObjectClass *klass, void *data= ) > > +{ > > + DeviceClass *dc =3D DEVICE_CLASS(klass); > > + > > + dc->reset =3D aw_h3_sdhost_reset; > > + dc->vmsd =3D &vmstate_aw_h3_sdhost; > > +} > > + > > +static TypeInfo aw_h3_sdhost_info =3D { > > + .name =3D TYPE_AW_H3_SDHOST, > > + .parent =3D TYPE_SYS_BUS_DEVICE, > > + .instance_size =3D sizeof(AwH3SDHostState), > > + .class_init =3D aw_h3_sdhost_class_init, > > + .instance_init =3D aw_h3_sdhost_init, > > +}; > > + > > +static const TypeInfo aw_h3_sdhost_bus_info =3D { > > + .name =3D TYPE_AW_H3_SDHOST_BUS, > > + .parent =3D TYPE_SD_BUS, > > + .instance_size =3D sizeof(SDBus), > > + .class_init =3D aw_h3_sdhost_bus_class_init, > > +}; > > + > > +static void aw_h3_sdhost_register_types(void) > > +{ > > + type_register_static(&aw_h3_sdhost_info); > > + type_register_static(&aw_h3_sdhost_bus_info); > > +} > > + > > +type_init(aw_h3_sdhost_register_types) > > diff --git a/hw/sd/trace-events b/hw/sd/trace-events > > index efcff666a2..c672a201b5 100644 > > --- a/hw/sd/trace-events > > +++ b/hw/sd/trace-events > > @@ -1,5 +1,12 @@ > > # See docs/devel/tracing.txt for syntax documentation. > > > > +# allwinner-h3-sdhost.c > > +aw_h3_sdhost_set_inserted(bool inserted) "inserted %u" > > +aw_h3_sdhost_process_desc(uint64_t desc_addr, uint32_t desc_size, > > bool is_write, uint32_t max_bytes) "desc_addr 0x%" PRIx64 " > > desc_size %u is_write %u max_bytes %u" > > Please also use PRIu32 for desc_size/max_bytes. > > Done. I'll also use PRIu32 / PRIx32 in the other commits that have trace-events changes. > > +aw_h3_sdhost_read(uint64_t offset, uint64_t data, unsigned size) > > "offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u" > > +aw_h3_sdhost_write(uint64_t offset, uint64_t data, unsigned size) > > "offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u" > > +aw_h3_sdhost_update_irq(uint32_t irq) "IRQ bits 0x%x" > > PRIx32 > > > + > > # bcm2835_sdhost.c > > bcm2835_sdhost_read(uint64_t offset, uint64_t data, unsigned size= ) > > "offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u" > > bcm2835_sdhost_write(uint64_t offset, uint64_t data, unsigned > > size) "offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u" > > diff --git a/include/hw/arm/allwinner-h3.h > > b/include/hw/arm/allwinner-h3.h > > index 33602599eb..7aff4ebbd2 100644 > > --- a/include/hw/arm/allwinner-h3.h > > +++ b/include/hw/arm/allwinner-h3.h > > @@ -30,6 +30,7 @@ > > #include "hw/misc/allwinner-h3-cpucfg.h" > > #include "hw/misc/allwinner-h3-syscon.h" > > #include "hw/misc/allwinner-h3-sid.h" > > +#include "hw/sd/allwinner-h3-sdhost.h" > > #include "target/arm/cpu.h" > > > > #define AW_H3_SRAM_A1_BASE (0x00000000) > > @@ -117,6 +118,7 @@ typedef struct AwH3State { > > AwH3CpuCfgState cpucfg; > > AwH3SysconState syscon; > > AwH3SidState sid; > > + AwH3SDHostState mmc0; > > GICState gic; > > MemoryRegion sram_a1; > > MemoryRegion sram_a2; > > diff --git a/include/hw/sd/allwinner-h3-sdhost.h > > b/include/hw/sd/allwinner-h3-sdhost.h > > new file mode 100644 > > index 0000000000..6c898a3c84 > > --- /dev/null > > +++ b/include/hw/sd/allwinner-h3-sdhost.h > > @@ -0,0 +1,73 @@ > > +/* > > + * Allwinner H3 SD Host Controller emulation > > + * > > + * Copyright (C) 2019 Niek Linnenbank > > > > + * > > + * This program is free software: you can redistribute it and/or > modify > > + * it under the terms of the GNU General Public License as > published by > > + * the Free Software Foundation, either version 2 of the License, = or > > + * (at your option) any later version. > > + * > > + * This program is distributed in the hope that it will be useful, > > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > > + * GNU General Public License for more details. > > + * > > + * You should have received a copy of the GNU General Public Licen= se > > + * along with this program. If not, see > > . > > + */ > > + > > +#ifndef ALLWINNER_H3_SDHOST_H > > +#define ALLWINNER_H3_SDHOST_H > > + > > +#include "hw/sysbus.h" > > +#include "hw/sd/sd.h" > > + > > +#define AW_H3_SDHOST_REGS_MEM_SIZE (1024) > > Move this definition to the source file. > > > + > > +#define TYPE_AW_H3_SDHOST "allwinner-h3-sdhost" > > +#define AW_H3_SDHOST(obj) \ > > + OBJECT_CHECK(AwH3SDHostState, (obj), TYPE_AW_H3_SDHOST) > > + > > +typedef struct { > > + SysBusDevice busdev; > > + SDBus sdbus; > > + MemoryRegion iomem; > > + > > + uint32_t global_ctl; > > + uint32_t clock_ctl; > > + uint32_t timeout; > > + uint32_t bus_width; > > + uint32_t block_size; > > + uint32_t byte_count; > > + uint32_t transfer_cnt; > > + > > + uint32_t command; > > + uint32_t command_arg; > > + uint32_t response[4]; > > + > > + uint32_t irq_mask; > > + uint32_t irq_status; > > + uint32_t status; > > + > > + uint32_t fifo_wlevel; > > + uint32_t fifo_func_sel; > > + uint32_t debug_enable; > > + uint32_t auto12_arg; > > + uint32_t newtiming_set; > > + uint32_t newtiming_debug; > > + uint32_t hardware_rst; > > + uint32_t dmac; > > + uint32_t desc_base; > > + uint32_t dmac_status; > > + uint32_t dmac_irq; > > + uint32_t card_threshold; > > + uint32_t startbit_detect; > > + uint32_t response_crc; > > + uint32_t data_crc[8]; > > + uint32_t status_crc; > > + > > + qemu_irq irq; > > +} AwH3SDHostState; > > + > > +#endif > > -- > > 2.17.1 > > I haven't checked the datasheet for all the registers/bits. > > Patch very clean, chapeau! > > Regards, > > Phil. > > --=20 Niek Linnenbank --000000000000c3573e0599c627e0 Content-Type: text/html; charset="UTF-8" Content-Transfer-Encoding: base64 PGRpdiBkaXI9Imx0ciI+PGRpdiBkaXI9Imx0ciI+PGRpdiBkaXI9Imx0ciI+PGRpdiBkaXI9Imx0 ciI+PGJyPjwvZGl2Pjxicj48ZGl2IGNsYXNzPSJnbWFpbF9xdW90ZSI+PGRpdiBkaXI9Imx0ciIg Y2xhc3M9ImdtYWlsX2F0dHIiPk9uIEZyaSwgRGVjIDEzLCAyMDE5IGF0IDEyOjU2IEFNIFBoaWxp cHBlIE1hdGhpZXUtRGF1ZMOpICZsdDs8YSBocmVmPSJtYWlsdG86cGhpbG1kQHJlZGhhdC5jb20i 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+0100 Message-ID: Subject: Re: [PATCH 05/10] arm: allwinner-h3: add System Control module To: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= Cc: QEMU Developers , Beniamino Galvani , Peter Maydell , qemu-arm Content-Type: multipart/alternative; boundary="000000000000478d8a0599c67208" X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::d44 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sun, 15 Dec 2019 23:28:16 -0000 --000000000000478d8a0599c67208 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable On Fri, Dec 13, 2019 at 1:09 AM Philippe Mathieu-Daud=C3=A9 wrote: > On 12/2/19 10:09 PM, Niek Linnenbank wrote: > > The Allwinner H3 System on Chip has an System Control > > module that provides system wide generic controls and > > device information. This commit adds support for the > > Allwinner H3 System Control module. > > > > Signed-off-by: Niek Linnenbank > > --- > > hw/arm/allwinner-h3.c | 11 ++ > > hw/misc/Makefile.objs | 1 + > > hw/misc/allwinner-h3-syscon.c | 139 +++++++++++++++++++++++++= + > > include/hw/arm/allwinner-h3.h | 2 + > > include/hw/misc/allwinner-h3-syscon.h | 43 ++++++++ > > 5 files changed, 196 insertions(+) > > create mode 100644 hw/misc/allwinner-h3-syscon.c > > create mode 100644 include/hw/misc/allwinner-h3-syscon.h > > > > diff --git a/hw/arm/allwinner-h3.c b/hw/arm/allwinner-h3.c > > index afeb49c0ac..ebd8fde412 100644 > > --- a/hw/arm/allwinner-h3.c > > +++ b/hw/arm/allwinner-h3.c > > @@ -41,6 +41,9 @@ static void aw_h3_init(Object *obj) > > > > sysbus_init_child_obj(obj, "ccu", &s->ccu, sizeof(s->ccu), > > TYPE_AW_H3_CLK); > > + > > + sysbus_init_child_obj(obj, "syscon", &s->syscon, sizeof(s->syscon)= , > > + TYPE_AW_H3_SYSCON); > > } > > > > static void aw_h3_realize(DeviceState *dev, Error **errp) > > @@ -184,6 +187,14 @@ static void aw_h3_realize(DeviceState *dev, Error > **errp) > > } > > sysbus_mmio_map(SYS_BUS_DEVICE(&s->ccu), 0, AW_H3_CCU_BASE); > > > > + /* System Control */ > > + object_property_set_bool(OBJECT(&s->syscon), true, "realized", > &err); > > + if (err) { > > + error_propagate(errp, err); > > + return; > > + } > > + sysbus_mmio_map(SYS_BUS_DEVICE(&s->syscon), 0, AW_H3_SYSCON_BASE); > > + > > /* Universal Serial Bus */ > > sysbus_create_simple(TYPE_AW_H3_EHCI, AW_H3_EHCI0_BASE, > > s->irq[AW_H3_GIC_SPI_EHCI0]); > > diff --git a/hw/misc/Makefile.objs b/hw/misc/Makefile.objs > > index 200ed44ce1..b234aefba5 100644 > > --- a/hw/misc/Makefile.objs > > +++ b/hw/misc/Makefile.objs > > @@ -29,6 +29,7 @@ common-obj-$(CONFIG_MACIO) +=3D macio/ > > common-obj-$(CONFIG_IVSHMEM_DEVICE) +=3D ivshmem.o > > > > common-obj-$(CONFIG_ALLWINNER_H3) +=3D allwinner-h3-clk.o > > +common-obj-$(CONFIG_ALLWINNER_H3) +=3D allwinner-h3-syscon.o > > common-obj-$(CONFIG_REALVIEW) +=3D arm_sysctl.o > > common-obj-$(CONFIG_NSERIES) +=3D cbus.o > > common-obj-$(CONFIG_ECCMEMCTL) +=3D eccmemctl.o > > diff --git a/hw/misc/allwinner-h3-syscon.c > b/hw/misc/allwinner-h3-syscon.c > > new file mode 100644 > > index 0000000000..66bd518a05 > > --- /dev/null > > +++ b/hw/misc/allwinner-h3-syscon.c > > @@ -0,0 +1,139 @@ > > +/* > > + * Allwinner H3 System Control emulation > > + * > > + * Copyright (C) 2019 Niek Linnenbank > > + * > > + * This program is free software: you can redistribute it and/or modif= y > > + * it under the terms of the GNU General Public License as published b= y > > + * the Free Software Foundation, either version 2 of the License, or > > + * (at your option) any later version. > > + * > > + * This program is distributed in the hope that it will be useful, > > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > > + * GNU General Public License for more details. > > + * > > + * You should have received a copy of the GNU General Public License > > + * along with this program. If not, see >. > > + */ > > + > > +#include "qemu/osdep.h" > > +#include "hw/sysbus.h" > > +#include "migration/vmstate.h" > > +#include "qemu/log.h" > > +#include "qemu/module.h" > > +#include "hw/misc/allwinner-h3-syscon.h" > > + > > +/* SYSCON register offsets */ > > +#define REG_VER (0x24) /* Version */ > > +#define REG_EMAC_PHY_CLK (0x30) /* EMAC PHY Clock */ > > +#define REG_INDEX(offset) (offset / sizeof(uint32_t)) > > + > > +/* SYSCON register reset values */ > > +#define REG_VER_RST (0x0) > > +#define REG_EMAC_PHY_CLK_RST (0x58000) > > + > > +static uint64_t allwinner_h3_syscon_read(void *opaque, hwaddr offset, > > + unsigned size) > > +{ > > + const AwH3SysconState *s =3D (AwH3SysconState *)opaque; > > + const uint32_t idx =3D REG_INDEX(offset); > > + > > + if (idx >=3D AW_H3_SYSCON_REGS_NUM) { > > + qemu_log_mask(LOG_GUEST_ERROR, "%s: bad read offset 0x%04x\n", > > + __func__, (uint32_t)offset); > > + return 0; > > + } > > + > > + return s->regs[idx]; > > +} > > + > > +static void allwinner_h3_syscon_write(void *opaque, hwaddr offset, > > + uint64_t val, unsigned size) > > +{ > > + AwH3SysconState *s =3D (AwH3SysconState *)opaque; > > + const uint32_t idx =3D REG_INDEX(offset); > > + > > + if (idx >=3D AW_H3_SYSCON_REGS_NUM) { > > + qemu_log_mask(LOG_GUEST_ERROR, "%s: bad write offset 0x%04x\n"= , > > + __func__, (uint32_t)offset); > > + return; > > + } > > + > > + switch (offset) { > > + case REG_VER: /* Version */ > > + break; > > + default: > > + s->regs[idx] =3D (uint32_t) val; > > + break; > > + } > > +} > > + > > +static const MemoryRegionOps allwinner_h3_syscon_ops =3D { > > + .read =3D allwinner_h3_syscon_read, > > + .write =3D allwinner_h3_syscon_write, > > + .endianness =3D DEVICE_NATIVE_ENDIAN, > > + .valid =3D { > > + .min_access_size =3D 4, > > + .max_access_size =3D 4, > > Can you point me to the datasheet page that says this region is > restricted to 32-bit accesses? Maybe you want .valid -> .impl instead? > > Hehe well here I can only give the same answer as for the SD/MMC driver: the datasheet only provides the base address and register offsets, but nothing explicitely mentioned about alignment. I do see that also for this device the registers are 32-bit aligned. Does that mean I should change MemoryRegionOps to . impl instead? > > + .unaligned =3D false > > + } > > +}; > > + > > +static void allwinner_h3_syscon_reset(DeviceState *dev) > > +{ > > + AwH3SysconState *s =3D AW_H3_SYSCON(dev); > > + > > + /* Set default values for registers */ > > + s->regs[REG_INDEX(REG_VER)] =3D REG_VER_RST; > > + s->regs[REG_INDEX(REG_EMAC_PHY_CLK)] =3D REG_EMAC_PHY_CLK_RST; > > +} > > + > > +static void allwinner_h3_syscon_realize(DeviceState *dev, Error **errp= ) > > +{ > > +} > > + > > +static void allwinner_h3_syscon_init(Object *obj) > > +{ > > + SysBusDevice *sbd =3D SYS_BUS_DEVICE(obj); > > + AwH3SysconState *s =3D AW_H3_SYSCON(obj); > > + > > + /* Memory mapping */ > > + memory_region_init_io(&s->iomem, OBJECT(s), > &allwinner_h3_syscon_ops, s, > > + TYPE_AW_H3_SYSCON, > AW_H3_SYSCON_REGS_MEM_SIZE); > > This definition isn't very helpful IMO, I'd use the value in place: '4 * > KiB'. > OK, I'll apply that too in the other drivers. > > > + sysbus_init_mmio(sbd, &s->iomem); > > +} > > + > > +static const VMStateDescription allwinner_h3_syscon_vmstate =3D { > > + .name =3D TYPE_AW_H3_SYSCON, > > Plain name. > > > + .version_id =3D 1, > > + .minimum_version_id =3D 1, > > + .fields =3D (VMStateField[]) { > > + VMSTATE_UINT32_ARRAY(regs, AwH3SysconState, > AW_H3_SYSCON_REGS_NUM), > > + VMSTATE_END_OF_LIST() > > + } > > +}; > > + > > +static void allwinner_h3_syscon_class_init(ObjectClass *klass, void > *data) > > +{ > > + DeviceClass *dc =3D DEVICE_CLASS(klass); > > + > > + dc->reset =3D allwinner_h3_syscon_reset; > > + dc->realize =3D allwinner_h3_syscon_realize; > > + dc->vmsd =3D &allwinner_h3_syscon_vmstate; > > +} > > + > > +static const TypeInfo allwinner_h3_syscon_info =3D { > > + .name =3D TYPE_AW_H3_SYSCON, > > + .parent =3D TYPE_SYS_BUS_DEVICE, > > + .instance_init =3D allwinner_h3_syscon_init, > > + .instance_size =3D sizeof(AwH3SysconState), > > + .class_init =3D allwinner_h3_syscon_class_init, > > +}; > > + > > +static void allwinner_h3_syscon_register(void) > > +{ > > + type_register_static(&allwinner_h3_syscon_info); > > +} > > + > > +type_init(allwinner_h3_syscon_register) > > diff --git a/include/hw/arm/allwinner-h3.h > b/include/hw/arm/allwinner-h3.h > > index e596516c5c..2bc526b77b 100644 > > --- a/include/hw/arm/allwinner-h3.h > > +++ b/include/hw/arm/allwinner-h3.h > > @@ -27,6 +27,7 @@ > > #include "hw/timer/allwinner-a10-pit.h" > > #include "hw/intc/arm_gic.h" > > #include "hw/misc/allwinner-h3-clk.h" > > +#include "hw/misc/allwinner-h3-syscon.h" > > #include "target/arm/cpu.h" > > > > #define AW_H3_SRAM_A1_BASE (0x00000000) > > @@ -111,6 +112,7 @@ typedef struct AwH3State { > > qemu_irq irq[AW_H3_GIC_NUM_SPI]; > > AwA10PITState timer; > > AwH3ClockState ccu; > > + AwH3SysconState syscon; > > GICState gic; > > MemoryRegion sram_a1; > > MemoryRegion sram_a2; > > diff --git a/include/hw/misc/allwinner-h3-syscon.h > b/include/hw/misc/allwinner-h3-syscon.h > > new file mode 100644 > > index 0000000000..22a2f2a11b > > --- /dev/null > > +++ b/include/hw/misc/allwinner-h3-syscon.h > > @@ -0,0 +1,43 @@ > > +/* > > + * Allwinner H3 System Control emulation > > + * > > + * Copyright (C) 2019 Niek Linnenbank > > + * > > + * This program is free software: you can redistribute it and/or modif= y > > + * it under the terms of the GNU General Public License as published b= y > > + * the Free Software Foundation, either version 2 of the License, or > > + * (at your option) any later version. > > + * > > + * This program is distributed in the hope that it will be useful, > > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > > + * GNU General Public License for more details. > > + * > > + * You should have received a copy of the GNU General Public License > > + * along with this program. If not, see >. > > + */ > > + > > +#ifndef HW_MISC_ALLWINNER_H3_SYSCON_H > > +#define HW_MISC_ALLWINNER_H3_SYSCON_H > > + > > +#include "hw/sysbus.h" > > + > > +#define AW_H3_SYSCON_REGS_MAX_ADDR (0x30) > > +#define AW_H3_SYSCON_REGS_NUM ((AW_H3_SYSCON_REGS_MAX_ADDR / \ > > + sizeof(uint32_t)) + 1) > > +#define AW_H3_SYSCON_REGS_MEM_SIZE (1024) > > "4.1. Memory Mapping" the System Control is 4KiB, isn't it? > Correct, I made a mistake there. Thanks, I'll change it and re-check the other files as well. > > > + > > +#define TYPE_AW_H3_SYSCON "allwinner-h3-syscon" > > +#define AW_H3_SYSCON(obj) OBJECT_CHECK(AwH3SysconState, (obj), \ > > + TYPE_AW_H3_SYSCON) > > + > > +typedef struct AwH3SysconState { > > + /*< private >*/ > > + SysBusDevice parent_obj; > > + /*< public >*/ > > + > > + MemoryRegion iomem; > > + uint32_t regs[AW_H3_SYSCON_REGS_NUM]; > > +} AwH3SysconState; > > + > > +#endif > > > > --=20 Niek Linnenbank --000000000000478d8a0599c67208 Content-Type: text/html; charset="UTF-8" Content-Transfer-Encoding: quoted-printable


=
On Fri, Dec 13, 2019 at 1:09 AM Phili= ppe Mathieu-Daud=C3=A9 <philmd@redh= at.com> wrote:
On 12/2/19 10:09 PM, Niek Linnenbank wrote:
> The Allwinner H3 System on Chip has an System Control
> module that provides system wide generic controls and
> device information. This commit adds support for the
> Allwinner H3 System Control module.
>
> Signed-off-by: Niek Linnenbank <nieklinnenbank@gmail.com>
> ---
>=C2=A0 =C2=A0hw/arm/allwinner-h3.c=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0|=C2=A0 11 ++
>=C2=A0 =C2=A0hw/misc/Makefile.objs=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0|=C2=A0 =C2=A01 +
>=C2=A0 =C2=A0hw/misc/allwinner-h3-syscon.c=C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0| 139 ++++++++++++++++++++++++++
>=C2=A0 =C2=A0include/hw/arm/allwinner-h3.h=C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0|=C2=A0 =C2=A02 +
>=C2=A0 =C2=A0include/hw/misc/allwinner-h3-syscon.h |=C2=A0 43 ++++++++<= br> >=C2=A0 =C2=A05 files changed, 196 insertions(+)
>=C2=A0 =C2=A0create mode 100644 hw/misc/allwinner-h3-syscon.c
>=C2=A0 =C2=A0create mode 100644 include/hw/misc/allwinner-h3-syscon.h >
> diff --git a/hw/arm/allwinner-h3.c b/hw/arm/allwinner-h3.c
> index afeb49c0ac..ebd8fde412 100644
> --- a/hw/arm/allwinner-h3.c
> +++ b/hw/arm/allwinner-h3.c
> @@ -41,6 +41,9 @@ static void aw_h3_init(Object *obj)
>=C2=A0 =C2=A0
>=C2=A0 =C2=A0 =C2=A0 =C2=A0sysbus_init_child_obj(obj, "ccu", = &s->ccu, sizeof(s->ccu),
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0TYPE_AW_H3_CLK);
> +
> +=C2=A0 =C2=A0 sysbus_init_child_obj(obj, "syscon", &s-&= gt;syscon, sizeof(s->syscon),
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0 =C2=A0 TYPE_AW_H3_SYSCON);
>=C2=A0 =C2=A0}
>=C2=A0 =C2=A0
>=C2=A0 =C2=A0static void aw_h3_realize(DeviceState *dev, Error **errp)<= br> > @@ -184,6 +187,14 @@ static void aw_h3_realize(DeviceState *dev, Error= **errp)
>=C2=A0 =C2=A0 =C2=A0 =C2=A0}
>=C2=A0 =C2=A0 =C2=A0 =C2=A0sysbus_mmio_map(SYS_BUS_DEVICE(&s->cc= u), 0, AW_H3_CCU_BASE);
>=C2=A0 =C2=A0
> +=C2=A0 =C2=A0 /* System Control */
> +=C2=A0 =C2=A0 object_property_set_bool(OBJECT(&s->syscon), tru= e, "realized", &err);
> +=C2=A0 =C2=A0 if (err) {
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 error_propagate(errp, err);
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 return;
> +=C2=A0 =C2=A0 }
> +=C2=A0 =C2=A0 sysbus_mmio_map(SYS_BUS_DEVICE(&s->syscon), 0, A= W_H3_SYSCON_BASE);
> +
>=C2=A0 =C2=A0 =C2=A0 =C2=A0/* Universal Serial Bus */
>=C2=A0 =C2=A0 =C2=A0 =C2=A0sysbus_create_simple(TYPE_AW_H3_EHCI, AW_H3_= EHCI0_BASE,
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 s->irq[AW_H3_GIC_SPI_EHCI0]);
> diff --git a/hw/misc/Makefile.objs b/hw/misc/Makefile.objs
> index 200ed44ce1..b234aefba5 100644
> --- a/hw/misc/Makefile.objs
> +++ b/hw/misc/Makefile.objs
> @@ -29,6 +29,7 @@ common-obj-$(CONFIG_MACIO) +=3D macio/
>=C2=A0 =C2=A0common-obj-$(CONFIG_IVSHMEM_DEVICE) +=3D ivshmem.o
>=C2=A0 =C2=A0
>=C2=A0 =C2=A0common-obj-$(CONFIG_ALLWINNER_H3) +=3D allwinner-h3-clk.o<= br> > +common-obj-$(CONFIG_ALLWINNER_H3) +=3D allwinner-h3-syscon.o
>=C2=A0 =C2=A0common-obj-$(CONFIG_REALVIEW) +=3D arm_sysctl.o
>=C2=A0 =C2=A0common-obj-$(CONFIG_NSERIES) +=3D cbus.o
>=C2=A0 =C2=A0common-obj-$(CONFIG_ECCMEMCTL) +=3D eccmemctl.o
> diff --git a/hw/misc/allwinner-h3-syscon.c b/hw/misc/allwinner-h3-sysc= on.c
> new file mode 100644
> index 0000000000..66bd518a05
> --- /dev/null
> +++ b/hw/misc/allwinner-h3-syscon.c
> @@ -0,0 +1,139 @@
> +/*
> + * Allwinner H3 System Control emulation
> + *
> + * Copyright (C) 2019 Niek Linnenbank <nieklinnenbank@gmail.com>
> + *
> + * This program is free software: you can redistribute it and/or modi= fy
> + * it under the terms of the GNU General Public License as published = by
> + * the Free Software Foundation, either version 2 of the License, or<= br> > + * (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful, > + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.=C2=A0 See the=
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License<= br> > + * along with this program.=C2=A0 If not, see <http://www.gnu.o= rg/licenses/>.
> + */
> +
> +#include "qemu/osdep.h"
> +#include "hw/sysbus.h"
> +#include "migration/vmstate.h"
> +#include "qemu/log.h"
> +#include "qemu/module.h"
> +#include "hw/misc/allwinner-h3-syscon.h"
> +
> +/* SYSCON register offsets */
> +#define REG_VER=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0(0x24)=C2=A0 /* Version */
> +#define REG_EMAC_PHY_CLK=C2=A0 =C2=A0 =C2=A0 =C2=A0 (0x30)=C2=A0 /* E= MAC PHY Clock */
> +#define REG_INDEX(offset)=C2=A0 =C2=A0 =C2=A0 =C2=A0(offset / sizeof(= uint32_t))
> +
> +/* SYSCON register reset values */
> +#define REG_VER_RST=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0(0= x0)
> +#define REG_EMAC_PHY_CLK_RST=C2=A0 =C2=A0 (0x58000)
> +
> +static uint64_t allwinner_h3_syscon_read(void *opaque, hwaddr offset,=
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0unsigned size)
> +{
> +=C2=A0 =C2=A0 const AwH3SysconState *s =3D (AwH3SysconState *)opaque;=
> +=C2=A0 =C2=A0 const uint32_t idx =3D REG_INDEX(offset);
> +
> +=C2=A0 =C2=A0 if (idx >=3D AW_H3_SYSCON_REGS_NUM) {
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 qemu_log_mask(LOG_GUEST_ERROR, "%s: = bad read offset 0x%04x\n",
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 __func__, (uint32_t)offset);
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 return 0;
> +=C2=A0 =C2=A0 }
> +
> +=C2=A0 =C2=A0 return s->regs[idx];
> +}
> +
> +static void allwinner_h3_syscon_write(void *opaque, hwaddr offset, > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 uint64_t va= l, unsigned size)
> +{
> +=C2=A0 =C2=A0 AwH3SysconState *s =3D (AwH3SysconState *)opaque;
> +=C2=A0 =C2=A0 const uint32_t idx =3D REG_INDEX(offset);
> +
> +=C2=A0 =C2=A0 if (idx >=3D AW_H3_SYSCON_REGS_NUM) {
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 qemu_log_mask(LOG_GUEST_ERROR, "%s: = bad write offset 0x%04x\n",
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 __func__, (uint32_t)offset);
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 return;
> +=C2=A0 =C2=A0 }
> +
> +=C2=A0 =C2=A0 switch (offset) {
> +=C2=A0 =C2=A0 case REG_VER:=C2=A0 =C2=A0 =C2=A0 =C2=A0/* Version */ > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 break;
> +=C2=A0 =C2=A0 default:
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 s->regs[idx] =3D (uint32_t) val;
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 break;
> +=C2=A0 =C2=A0 }
> +}
> +
> +static const MemoryRegionOps allwinner_h3_syscon_ops =3D {
> +=C2=A0 =C2=A0 .read =3D allwinner_h3_syscon_read,
> +=C2=A0 =C2=A0 .write =3D allwinner_h3_syscon_write,
> +=C2=A0 =C2=A0 .endianness =3D DEVICE_NATIVE_ENDIAN,
> +=C2=A0 =C2=A0 .valid =3D {
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 .min_access_size =3D 4,
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 .max_access_size =3D 4,

Can you point me to the datasheet page that says this region is
restricted to 32-bit accesses? Maybe you want .valid -> .impl instead?
Hehe well here I can only give the same answer as for= the SD/MMC driver: the datasheet
only provides the base address = and register offsets, but nothing explicitely mentioned about alignment.
I do see that also for this device the registers are 32-bit aligned= .

Does that mean I should change MemoryRegionOps t= o . impl instead?
=C2=A0
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 .unaligned =3D false
> +=C2=A0 =C2=A0 }
> +};
> +
> +static void allwinner_h3_syscon_reset(DeviceState *dev)
> +{
> +=C2=A0 =C2=A0 AwH3SysconState *s =3D AW_H3_SYSCON(dev);
> +
> +=C2=A0 =C2=A0 /* Set default values for registers */
> +=C2=A0 =C2=A0 s->regs[REG_INDEX(REG_VER)] =3D REG_VER_RST;
> +=C2=A0 =C2=A0 s->regs[REG_INDEX(REG_EMAC_PHY_CLK)] =3D REG_EMAC_PH= Y_CLK_RST;
> +}
> +
> +static void allwinner_h3_syscon_realize(DeviceState *dev, Error **err= p)
> +{
> +}
> +
> +static void allwinner_h3_syscon_init(Object *obj)
> +{
> +=C2=A0 =C2=A0 SysBusDevice *sbd =3D SYS_BUS_DEVICE(obj);
> +=C2=A0 =C2=A0 AwH3SysconState *s =3D AW_H3_SYSCON(obj);
> +
> +=C2=A0 =C2=A0 /* Memory mapping */
> +=C2=A0 =C2=A0 memory_region_init_io(&s->iomem, OBJECT(s), &= ;allwinner_h3_syscon_ops, s,
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0 =C2=A0 TYPE_AW_H3_SYSCON, AW_H3_SYSCON_REGS_MEM_SIZE);

This definition isn't very helpful IMO, I'd use the value in place:= '4 *
KiB'.
OK, I'll apply that too in the other dri= vers.
=C2=A0

> +=C2=A0 =C2=A0 sysbus_init_mmio(sbd, &s->iomem);
> +}
> +
> +static const VMStateDescription allwinner_h3_syscon_vmstate =3D {
> +=C2=A0 =C2=A0 .name =3D TYPE_AW_H3_SYSCON,

Plain name.

> +=C2=A0 =C2=A0 .version_id =3D 1,
> +=C2=A0 =C2=A0 .minimum_version_id =3D 1,
> +=C2=A0 =C2=A0 .fields =3D (VMStateField[]) {
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 VMSTATE_UINT32_ARRAY(regs, AwH3SysconStat= e, AW_H3_SYSCON_REGS_NUM),
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 VMSTATE_END_OF_LIST()
> +=C2=A0 =C2=A0 }
> +};
> +
> +static void allwinner_h3_syscon_class_init(ObjectClass *klass, void *= data)
> +{
> +=C2=A0 =C2=A0 DeviceClass *dc =3D DEVICE_CLASS(klass);
> +
> +=C2=A0 =C2=A0 dc->reset =3D allwinner_h3_syscon_reset;
> +=C2=A0 =C2=A0 dc->realize =3D allwinner_h3_syscon_realize;
> +=C2=A0 =C2=A0 dc->vmsd =3D &allwinner_h3_syscon_vmstate;
> +}
> +
> +static const TypeInfo allwinner_h3_syscon_info =3D {
> +=C2=A0 =C2=A0 .name=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =3D TYPE_AW_H3_= SYSCON,
> +=C2=A0 =C2=A0 .parent=C2=A0 =C2=A0 =C2=A0 =C2=A0 =3D TYPE_SYS_BUS_DEV= ICE,
> +=C2=A0 =C2=A0 .instance_init =3D allwinner_h3_syscon_init,
> +=C2=A0 =C2=A0 .instance_size =3D sizeof(AwH3SysconState),
> +=C2=A0 =C2=A0 .class_init=C2=A0 =C2=A0 =3D allwinner_h3_syscon_class_= init,
> +};
> +
> +static void allwinner_h3_syscon_register(void)
> +{
> +=C2=A0 =C2=A0 type_register_static(&allwinner_h3_syscon_info); > +}
> +
> +type_init(allwinner_h3_syscon_register)
> diff --git a/include/hw/arm/allwinner-h3.h b/include/hw/arm/allwinner-= h3.h
> index e596516c5c..2bc526b77b 100644
> --- a/include/hw/arm/allwinner-h3.h
> +++ b/include/hw/arm/allwinner-h3.h
> @@ -27,6 +27,7 @@
>=C2=A0 =C2=A0#include "hw/timer/allwinner-a10-pit.h"
>=C2=A0 =C2=A0#include "hw/intc/arm_gic.h"
>=C2=A0 =C2=A0#include "hw/misc/allwinner-h3-clk.h"
> +#include "hw/misc/allwinner-h3-syscon.h"
>=C2=A0 =C2=A0#include "target/arm/cpu.h"
>=C2=A0 =C2=A0
>=C2=A0 =C2=A0#define AW_H3_SRAM_A1_BASE=C2=A0 =C2=A0 =C2=A0(0x00000000)=
> @@ -111,6 +112,7 @@ typedef struct AwH3State {
>=C2=A0 =C2=A0 =C2=A0 =C2=A0qemu_irq irq[AW_H3_GIC_NUM_SPI];
>=C2=A0 =C2=A0 =C2=A0 =C2=A0AwA10PITState timer;
>=C2=A0 =C2=A0 =C2=A0 =C2=A0AwH3ClockState ccu;
> +=C2=A0 =C2=A0 AwH3SysconState syscon;
>=C2=A0 =C2=A0 =C2=A0 =C2=A0GICState gic;
>=C2=A0 =C2=A0 =C2=A0 =C2=A0MemoryRegion sram_a1;
>=C2=A0 =C2=A0 =C2=A0 =C2=A0MemoryRegion sram_a2;
> diff --git a/include/hw/misc/allwinner-h3-syscon.h b/include/hw/misc/a= llwinner-h3-syscon.h
> new file mode 100644
> index 0000000000..22a2f2a11b
> --- /dev/null
> +++ b/include/hw/misc/allwinner-h3-syscon.h
> @@ -0,0 +1,43 @@
> +/*
> + * Allwinner H3 System Control emulation
> + *
> + * Copyright (C) 2019 Niek Linnenbank <nieklinnenbank@gmail.com>
> + *
> + * This program is free software: you can redistribute it and/or modi= fy
> + * it under the terms of the GNU General Public License as published = by
> + * the Free Software Foundation, either version 2 of the License, or<= br> > + * (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful, > + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.=C2=A0 See the=
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License<= br> > + * along with this program.=C2=A0 If not, see <http://www.gnu.o= rg/licenses/>.
> + */
> +
> +#ifndef HW_MISC_ALLWINNER_H3_SYSCON_H
> +#define HW_MISC_ALLWINNER_H3_SYSCON_H
> +
> +#include "hw/sysbus.h"
> +
> +#define AW_H3_SYSCON_REGS_MAX_ADDR=C2=A0 (0x30)
> +#define AW_H3_SYSCON_REGS_NUM=C2=A0 =C2=A0 =C2=A0 =C2=A0((AW_H3_SYSCO= N_REGS_MAX_ADDR / \
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 sizeof(uint= 32_t)) + 1)
> +#define AW_H3_SYSCON_REGS_MEM_SIZE=C2=A0 (1024)

"4.1. Memory Mapping" the System Control is 4KiB, isn't it?

Correct, I made a mistake there. Thanks,= I'll change it and re-check the other files as well.
=C2= =A0

> +
> +#define TYPE_AW_H3_SYSCON=C2=A0 =C2=A0 "allwinner-h3-syscon"= ;
> +#define AW_H3_SYSCON(obj)=C2=A0 =C2=A0 OBJECT_CHECK(AwH3SysconState, = (obj), \
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 TYPE_AW_H3_SYSCON)
> +
> +typedef struct AwH3SysconState {
> +=C2=A0 =C2=A0 /*< private >*/
> +=C2=A0 =C2=A0 SysBusDevice parent_obj;
> +=C2=A0 =C2=A0 /*< public >*/
> +
> +=C2=A0 =C2=A0 MemoryRegion iomem;
> +=C2=A0 =C2=A0 uint32_t regs[AW_H3_SYSCON_REGS_NUM];
> +} AwH3SysconState;
> +
> +#endif
>



--
Niek Linnenbank

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[83.42.66.34]) by smtp.gmail.com with ESMTPSA id o15sm19963027wra.83.2019.12.15.16.14.39 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Sun, 15 Dec 2019 16:14:40 -0800 (PST) Subject: Re: [PATCH 09/10] arm: allwinner-h3: add SD/MMC host controller To: Niek Linnenbank Cc: QEMU Developers , qemu-arm , Peter Maydell , Beniamino Galvani References: <20191202210947.3603-1-nieklinnenbank@gmail.com> <20191202210947.3603-10-nieklinnenbank@gmail.com> <6bee15d7-7d80-0709-ac90-ef2052b39329@redhat.com> From: =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= Message-ID: <03a78f1d-e8fe-5a53-b061-d39de9ed7a9e@redhat.com> Date: Mon, 16 Dec 2019 01:14:38 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.2.2 MIME-Version: 1.0 In-Reply-To: Content-Language: en-US X-MC-Unique: BnCMseBrNS-nM023lJJMtA-1 X-Mimecast-Spam-Score: 0 Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 205.139.110.120 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 16 Dec 2019 00:14:51 -0000 On 12/16/19 12:07 AM, Niek Linnenbank wrote: >=20 >=20 > On Fri, Dec 13, 2019 at 12:56 AM Philippe Mathieu-Daud=C3=A9=20 > > wrote: >=20 > Hi Niek, >=20 > On 12/11/19 11:34 PM, Niek Linnenbank wrote: [...] > >=C2=A0 =C2=A0 =C2=A0+static uint32_t aw_h3_sdhost_process_desc(AwH3= SDHostState *s, > >=C2=A0 =C2=A0 =C2=A0+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 hwaddr desc_addr, > >=C2=A0 =C2=A0 =C2=A0+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 TransferDescriptor > *desc, > >=C2=A0 =C2=A0 =C2=A0+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 bool is_write, > uint32_t > >=C2=A0 =C2=A0 =C2=A0max_bytes) > >=C2=A0 =C2=A0 =C2=A0+{ > >=C2=A0 =C2=A0 =C2=A0+=C2=A0 =C2=A0 uint32_t num_done =3D 0; > >=C2=A0 =C2=A0 =C2=A0+=C2=A0 =C2=A0 uint32_t num_bytes =3D max_bytes= ; > >=C2=A0 =C2=A0 =C2=A0+=C2=A0 =C2=A0 uint8_t buf[1024]; > >=C2=A0 =C2=A0 =C2=A0+ > >=C2=A0 =C2=A0 =C2=A0+=C2=A0 =C2=A0 /* Read descriptor */ > >=C2=A0 =C2=A0 =C2=A0+=C2=A0 =C2=A0 cpu_physical_memory_read(desc_ad= dr, desc, sizeof(*desc)); >=20 > Should we worry about endianess here? >=20 >=20 > I tried to figure out what is expected, but the=20 > Allwinner_H3_Datasheet_V1.2.pdf does not > explicitly mention endianness for any of its I/O devices. Currently it=20 > seems all devices are > happy with using the same endianness as the CPUs. In the MemoryRegionOps= =20 > has DEVICE_NATIVE_ENDIAN > set to match the behavior seen. OK. [...] > >=C2=A0 =C2=A0 =C2=A0+static const MemoryRegionOps aw_h3_sdhost_ops = =3D { > >=C2=A0 =C2=A0 =C2=A0+=C2=A0 =C2=A0 .read =3D aw_h3_sdhost_read, > >=C2=A0 =C2=A0 =C2=A0+=C2=A0 =C2=A0 .write =3D aw_h3_sdhost_write, > >=C2=A0 =C2=A0 =C2=A0+=C2=A0 =C2=A0 .endianness =3D DEVICE_NATIVE_EN= DIAN, >=20 > I haven't checked .valid accesses from the datasheet. >=20 > However due to: >=20 > =C2=A0 =C2=A0res =3D s->data_crc[((offset - REG_SD_DATA7_CRC) / size= of(uint32_t))]; >=20 > You seem to expect: >=20 > =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 .impl.min_access_size =3D = 4, >=20 > .impl.max_access_size unset is 8, which should works. >=20 > It seems that all registers are aligned on at least 32-bit boundaries.=20 > And the section 5.3.5.1 mentions > that the DMA descriptors must be stored in memory 32-bit aligned. So=20 > based on that information, So you are describing ".valid.min_access_size =3D 4", which is the minimum= =20 access size on the bus. ".impl.min_access_size" is different, it is what access sizes is ready=20 to handle your model. Your model read/write handlers expect addresses aligned on 32-bit=20 boundary, this is why I suggested to use ".impl.min_access_size =3D 4". If= =20 the guest were using a 16-bit access, your model would be buggy. If you=20 describe your implementation to accept minimum 32-bit and the guest is=20 allowed to use smaller accesses, QEMU will do a 32-bit access to the=20 device, and return the 16-bit part to the guest. This way your model is=20 safe. This is done by access_with_adjusted_size() in memory.c. If you restrict with ".valid.min_access_size =3D 4", you might think we=20 don't need ".valid.min_access_size =3D 4" because all access from guest=20 will be at least 32-bit. However keep in mind someone might find this=20 device in another datasheet not limited to 32-bit, and let's say change=20 to ".valid.min_access_size =3D 2". Without ".impl.min_access_size =3D 4"=20 your model is buggy. So to be safe I'd use: .impl.min_access_size =3D 4, .valid.min_access_size =3D 4, > I think 32-bit is a safe choice. I've verified this with Linux mainline= =20 > and U-Boot drivers and both are still working. Regards, Phil. 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[83.42.66.34]) by smtp.gmail.com with ESMTPSA id e12sm19457469wrn.56.2019.12.15.16.17.33 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Sun, 15 Dec 2019 16:17:33 -0800 (PST) Subject: Re: [PATCH 05/10] arm: allwinner-h3: add System Control module To: Niek Linnenbank Cc: QEMU Developers , Beniamino Galvani , Peter Maydell , qemu-arm References: <20191202210947.3603-1-nieklinnenbank@gmail.com> <20191202210947.3603-6-nieklinnenbank@gmail.com> <949aec5f-fd92-9fb2-25f4-803cd1bbf601@redhat.com> From: =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= Message-ID: <25c838e3-af9a-d742-6946-056c431a8805@redhat.com> Date: Mon, 16 Dec 2019 01:17:32 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.2.2 MIME-Version: 1.0 In-Reply-To: Content-Language: en-US X-MC-Unique: GHd6BL2zPYGf05p9ogYWQA-1 X-Mimecast-Spam-Score: 0 Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 205.139.110.120 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 16 Dec 2019 00:17:41 -0000 On 12/16/19 12:27 AM, Niek Linnenbank wrote: > On Fri, Dec 13, 2019 at 1:09 AM Philippe Mathieu-Daud=C3=A9=20 > > wrote: >=20 > On 12/2/19 10:09 PM, Niek Linnenbank wrote: [...] > > +static const MemoryRegionOps allwinner_h3_syscon_ops =3D { > > +=C2=A0 =C2=A0 .read =3D allwinner_h3_syscon_read, > > +=C2=A0 =C2=A0 .write =3D allwinner_h3_syscon_write, > > +=C2=A0 =C2=A0 .endianness =3D DEVICE_NATIVE_ENDIAN, > > +=C2=A0 =C2=A0 .valid =3D { > > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 .min_access_size =3D 4, > > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 .max_access_size =3D 4, >=20 > Can you point me to the datasheet page that says this region is > restricted to 32-bit accesses? Maybe you want .valid -> .impl instead= ? >=20 > Hehe well here I can only give the same answer as for the SD/MMC driver:= =20 > the datasheet > only provides the base address and register offsets, but nothing=20 > explicitely mentioned about alignment. > I do see that also for this device the registers are 32-bit aligned. >=20 > Does that mean I should change MemoryRegionOps to . impl instead? No, keep them, but add ".impl.min_access_size =3D 4" (see answer to SD/MMC= =20 model patch). From MAILER-DAEMON Sun Dec 15 20:03:48 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1igenc-0000g1-Oj for mharc-qemu-arm@gnu.org; Sun, 15 Dec 2019 20:03:48 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:41409) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1igenZ-0000b8-QW for qemu-arm@nongnu.org; Sun, 15 Dec 2019 20:03:47 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1igenY-0005Ue-J5 for qemu-arm@nongnu.org; Sun, 15 Dec 2019 20:03:45 -0500 Received: from mga01.intel.com ([192.55.52.88]:20795) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1igenU-00053U-Ve; Sun, 15 Dec 2019 20:03:41 -0500 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by fmsmga101.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 15 Dec 2019 17:03:32 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.69,319,1571727600"; d="scan'208";a="414917184" Received: from txu2-mobl.ccr.corp.intel.com (HELO [10.239.196.238]) ([10.239.196.238]) by fmsmga005.fm.intel.com with ESMTP; 15 Dec 2019 17:03:30 -0800 Subject: Re: [PATCH 2/2] numa: properly check if numa is supported To: Igor Mammedov Cc: "qemu-devel@nongnu.org" , Eduardo Habkost , Marcel Apfelbaum , Radoslaw Biernacki , Peter Maydell , Leif Lindholm , "qemu-arm@nongnu.org" , "qemu-stable@nongnu.org" References: <1576154936-178362-1-git-send-email-imammedo@redhat.com> <1576154936-178362-3-git-send-email-imammedo@redhat.com> <20191213101219.0aa249dc@redhat.com> From: Tao Xu Message-ID: Date: Mon, 16 Dec 2019 09:03:30 +0800 User-Agent: Mozilla/5.0 (Windows NT 10.0; WOW64; rv:60.0) Gecko/20100101 Thunderbird/60.9.1 MIME-Version: 1.0 In-Reply-To: <20191213101219.0aa249dc@redhat.com> Content-Type: text/plain; charset=utf-8; format=flowed Content-Language: en-US Content-Transfer-Encoding: 7bit X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 192.55.52.88 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 16 Dec 2019 01:03:47 -0000 On 12/13/2019 5:12 PM, Igor Mammedov wrote: > On Fri, 13 Dec 2019 09:33:10 +0800 > Tao Xu wrote: > >> On 12/12/2019 8:48 PM, Igor Mammedov wrote: >>> Commit aa57020774b, by mistake used MachineClass::numa_mem_supported >>> to check if NUMA is supported by machine and also as unrelated change >>> set it to true for sbsa-ref board. >>> >>> Luckily change didn't break machines that support NUMA, as the field >>> is set to true for them. >>> >>> But the field is not intended for checking if NUMA is supported and >>> will be flipped to false within this release for new machine types. >>> >>> Fix it: >>> - by using previously used condition >>> !mc->cpu_index_to_instance_props || !mc->get_default_cpu_node_id >>> the first time and then use MachineState::numa_state down the road >>> to check if NUMA is supported >>> - dropping stray sbsa-ref chunk >>> >>> Fixes: aa57020774b690a22be72453b8e91c9b5a68c516 >>> Signed-off-by: Igor Mammedov >>> --- >>> CC: Radoslaw Biernacki >>> CC: Peter Maydell >>> CC: Leif Lindholm >>> CC: qemu-arm@nongnu.org >>> CC: qemu-stable@nongnu.org >>> >>> >>> hw/arm/sbsa-ref.c | 1 - >>> hw/core/machine.c | 4 ++-- >>> 2 files changed, 2 insertions(+), 3 deletions(-) >>> >>> diff --git a/hw/arm/sbsa-ref.c b/hw/arm/sbsa-ref.c >>> index 27046cc..c6261d4 100644 >>> --- a/hw/arm/sbsa-ref.c >>> +++ b/hw/arm/sbsa-ref.c >>> @@ -791,7 +791,6 @@ static void sbsa_ref_class_init(ObjectClass *oc, void *data) >>> mc->possible_cpu_arch_ids = sbsa_ref_possible_cpu_arch_ids; >>> mc->cpu_index_to_instance_props = sbsa_ref_cpu_index_to_props; >>> mc->get_default_cpu_node_id = sbsa_ref_get_default_cpu_node_id; >>> - mc->numa_mem_supported = true; >>> } >>> >>> static const TypeInfo sbsa_ref_info = { >>> diff --git a/hw/core/machine.c b/hw/core/machine.c >>> index 1689ad3..aa63231 100644 >>> --- a/hw/core/machine.c >>> +++ b/hw/core/machine.c >>> @@ -958,7 +958,7 @@ static void machine_initfn(Object *obj) >>> NULL); >>> } >>> >>> - if (mc->numa_mem_supported) { >>> + if (mc->cpu_index_to_instance_props && mc->get_default_cpu_node_id) { >>> ms->numa_state = g_new0(NumaState, 1); >>> } >> >> I am wondering if @numa_mem_supported is unused here, it is unused for >> QEMU, because the only usage of @numa_mem_supported is to initialize >> @numa_state. Or there is other usage? So should it be removed from >> struct MachineClass? > You are wrong, it's not intended for numa_state initialization, > read doc comment for it in include/hw/boards.h > (for full story look at commit cd5ff8333a3) > I understand. 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[31.168.111.5]) by smtp.gmail.com with ESMTPSA id u16sm5807903qku.19.2019.12.16.03.39.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 16 Dec 2019 03:40:03 -0800 (PST) Date: Mon, 16 Dec 2019 06:39:56 -0500 From: "Michael S. Tsirkin" To: Peter Maydell Cc: Philippe =?iso-8859-1?Q?Mathieu-Daud=E9?= , QEMU Developers , Andrew Baumann , Aurelien Jarno , kvm-devel , Alex Williamson , Aleksandar Markovic , Joel Stanley , qemu-arm , Marcelo Tosatti , Alistair Francis , Eduardo Habkost , Richard Henderson , Aleksandar Rikalo , Paul Burton , Marcel Apfelbaum , "Edgar E. Iglesias" , Paolo Bonzini Subject: Re: [PATCH 0/8] Simplify memory_region_add_subregion_overlap(..., priority=0) Message-ID: <20191216063529-mutt-send-email-mst@kernel.org> References: <20191214155614.19004-1-philmd@redhat.com> <20191215044759-mutt-send-email-mst@kernel.org> MIME-Version: 1.0 In-Reply-To: X-MC-Unique: I4FJ89naNF6HIY1QbW5UwA-1 X-Mimecast-Spam-Score: 0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: quoted-printable Content-Disposition: inline X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 205.139.110.61 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 16 Dec 2019 11:40:12 -0000 On Sun, Dec 15, 2019 at 03:27:12PM +0000, Peter Maydell wrote: > On Sun, 15 Dec 2019 at 09:51, Michael S. Tsirkin wrote: > > > > On Sat, Dec 14, 2019 at 04:28:08PM +0000, Peter Maydell wrote: > > > (It doesn't actually assert that it doesn't > > > overlap because we have some legacy uses, notably > > > in the x86 PC machines, which do overlap without using > > > the right function, which we've never tried to tidy up.) > > > > It's not exactly legacy uses. > > > > To be more exact, the way the non overlap versions > > are *used* is to mean "I don't care what happens when they overlap" > > as opposed to "will never overlap". >=20 > Almost all of the use of the non-overlap versions is > for "these are never going to overlap" -- devices or ram at > fixed addresses in the address space that can't > ever be mapped over by anything else. If you want > "can overlap but I don't care which one wins" then > that would be more clearly expressed by using the _overlap() > version but just giving everything that can overlap there > the same priority. Problem is device doesn't always know whether something can overlap it. Imagine device A at a fixed address. Guest can program device B to overlap the fixed address. How is device A supposed to know this can happen? > > There are lots of regions where guest can make things overlapping > > but doesn't, e.g. PCI BARs can be programmed to overlap > > almost anything. > > > > What happens on real hardware if you then access one of > > the BARs is undefined, but programming itself is harmless. > > That's why we can't assert. >=20 > Yeah, good point, for the special case where it's the > guest that's determining the addresses where something's > mapped we might want to allow the behaviour to fall out > of the implementation. (You could instead specify set of > priorities that makes the undefined-behaviour something > specific, rather than just an emergent property of > the implementation QEMU happens to have, but it seems > a bit hard to justify.) >=20 > thanks > -- PMM From MAILER-DAEMON Mon Dec 16 06:46:53 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1igopx-0007Gq-FJ for mharc-qemu-arm@gnu.org; Mon, 16 Dec 2019 06:46:53 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:38690) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1igopt-0007Ee-PN for qemu-arm@nongnu.org; Mon, 16 Dec 2019 06:46:52 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1igops-0006OJ-Fz for qemu-arm@nongnu.org; Mon, 16 Dec 2019 06:46:49 -0500 Received: from mail-ot1-x343.google.com ([2607:f8b0:4864:20::343]:46417) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1igops-0006Ju-Ao for qemu-arm@nongnu.org; Mon, 16 Dec 2019 06:46:48 -0500 Received: by mail-ot1-x343.google.com with SMTP id g18so8823157otj.13 for ; Mon, 16 Dec 2019 03:46:48 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=8I5trJBGTW4luMb11Ffwe+Tyg+F3aLb9Oz/+hKtjAZQ=; b=yfj+MJhPaUOx7sxyWSVqpAJ3fhdorMc3yaCPiBcoJGHf3s50+RFX6CsD4btsF+xSNc epRtGKgGbnJcYr0b+57Psp8tbjWI91A+UwqXMW8IC/oT7eShtLBIxYb7eKq1wMyKwPQ7 hDHK3B767lDJVvofvKZem/Aqt3PKjOSZNDB1JlLc4zYu+HdTtUx0gF31MlGxOPJ7M7ha Z+iDvgWzgkUF498+wFV8G9EUAcZ6xu5vn/w+H8bCbsk1CeEoLt0xYd/DPhZEXGjqxCMF oLZb9t8B63ZeKqB1WI752r0JJh7BkK5f9q4W1HbKLXetzOwI8GmThU55YSrFU9rPVH+/ 2aaA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=8I5trJBGTW4luMb11Ffwe+Tyg+F3aLb9Oz/+hKtjAZQ=; b=A4QnaPi8T/ce/mgYh2uVqsLB/yvPQa8/NcYSMKivkylM4hu9vXg/XT9SkXTL4VRR12 VXladGQBsjEDN+gFu6pZobKyf2b5hBwRZL7pPMSzVGdw7bt4aVKnEnuEUe94f844JeHR QNuvm4vZcGyGVfpn7mgZ4bJs1ntM3sGMnfzeayrVE4lPHKrW1BAGuZhkspvYLULS6/eb GuGltD0YXToDT1VbtJbK9gqOWyhOgHphUccaCHe4waLL0EHqwnDNjy60UT2wl7BT/Yx1 3o+KW/G9Hsksp1v8H3BbtbRCGwCiIzbrKOTbYJF2CpcevEnXR5I3GSgV3CMN47lcSqIs wAxA== X-Gm-Message-State: APjAAAXWpwUfYQcmzDlBuIUnO2o1U1FHMVu+ks34lg/tlGQdFBVZf4TH n60jc4p2vlwve2EfvONLU/m8ph2tk9RiNJ5po5xNtA== X-Google-Smtp-Source: APXvYqxU8RwCCG8UHVDxyzHL7AncEdglJUZybQzX82nL6dMWGIqTX5XxVtjPkHDzIBRKKOCDoO1XFnaJ5Vmd7ng4cws= X-Received: by 2002:a05:6830:13d3:: with SMTP id e19mr31703782otq.135.1576496807419; Mon, 16 Dec 2019 03:46:47 -0800 (PST) MIME-Version: 1.0 References: <20191214155614.19004-1-philmd@redhat.com> <20191215044759-mutt-send-email-mst@kernel.org> <20191216063529-mutt-send-email-mst@kernel.org> In-Reply-To: <20191216063529-mutt-send-email-mst@kernel.org> From: Peter Maydell Date: Mon, 16 Dec 2019 11:46:35 +0000 Message-ID: Subject: Re: [PATCH 0/8] Simplify memory_region_add_subregion_overlap(..., priority=0) To: "Michael S. Tsirkin" Cc: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= , QEMU Developers , Andrew Baumann , Aurelien Jarno , kvm-devel , Alex Williamson , Aleksandar Markovic , Joel Stanley , qemu-arm , Marcelo Tosatti , Alistair Francis , Eduardo Habkost , Richard Henderson , Aleksandar Rikalo , Paul Burton , Marcel Apfelbaum , "Edgar E. Iglesias" , Paolo Bonzini Content-Type: text/plain; charset="UTF-8" X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::343 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 16 Dec 2019 11:46:52 -0000 On Mon, 16 Dec 2019 at 11:40, Michael S. Tsirkin wrote: > > On Sun, Dec 15, 2019 at 03:27:12PM +0000, Peter Maydell wrote: > > On Sun, 15 Dec 2019 at 09:51, Michael S. Tsirkin wrote: > > > > > > On Sat, Dec 14, 2019 at 04:28:08PM +0000, Peter Maydell wrote: > > > > (It doesn't actually assert that it doesn't > > > > overlap because we have some legacy uses, notably > > > > in the x86 PC machines, which do overlap without using > > > > the right function, which we've never tried to tidy up.) > > > > > > It's not exactly legacy uses. > > > > > > To be more exact, the way the non overlap versions > > > are *used* is to mean "I don't care what happens when they overlap" > > > as opposed to "will never overlap". > > > > Almost all of the use of the non-overlap versions is > > for "these are never going to overlap" -- devices or ram at > > fixed addresses in the address space that can't > > ever be mapped over by anything else. If you want > > "can overlap but I don't care which one wins" then > > that would be more clearly expressed by using the _overlap() > > version but just giving everything that can overlap there > > the same priority. > > Problem is device doesn't always know whether something can overlap it. > Imagine device A at a fixed address. > Guest can program device B to overlap the fixed address. > How is device A supposed to know this can happen? That's why (the original intention was) only one of the regions needs to be marked 'overlap OK', not both. thanks -- PMM From MAILER-DAEMON Mon Dec 16 08:38:25 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1igqZt-0001a4-GM for mharc-qemu-arm@gnu.org; Mon, 16 Dec 2019 08:38:25 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:50869) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1igqZq-0001W0-3n for qemu-arm@nongnu.org; Mon, 16 Dec 2019 08:38:23 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1igqZp-0006OQ-0F for qemu-arm@nongnu.org; Mon, 16 Dec 2019 08:38:21 -0500 Received: from mail-oi1-x241.google.com ([2607:f8b0:4864:20::241]:41976) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1igqZo-0006Hd-PK for qemu-arm@nongnu.org; Mon, 16 Dec 2019 08:38:20 -0500 Received: by mail-oi1-x241.google.com with SMTP id i1so3309105oie.8 for ; Mon, 16 Dec 2019 05:38:20 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc:content-transfer-encoding; bh=bOiOQS281XKOtaM1Cfka5yGcYTvl+GxoBwrv7dXPzRE=; b=uZNRKMHNPtZbu+4KvM8MpcX4OG/0UGhqrucOETxh2Qn3b4EQ7GuAqmv3TzqG/FrOQi LxpamBdf+KRO92/tXtvaC8wHtOt0iC9HsfeogKO25dz20Gg1ADKL7ZVFsV8+LcODIXvj k61L6YX/Wt3bdGuwc7QE+NuAT1EUNuCCfBfuEaOxWCi6ZH5CDpXEl9cWy2zov54U3DNE 4VJMBP2ypuHT9TvQzGyY4rTHuvw9aPuFpqWwHb+Jp3M9QyycjoFjPIgvg/Q1R3W6TlrX 5KJOr05Nk/F7IyWhspXEgJJAeJXQUIzKOs7IXBb9bSDu/QMz7bxS91u0vFqp6OwRmUbo o+tg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc:content-transfer-encoding; bh=bOiOQS281XKOtaM1Cfka5yGcYTvl+GxoBwrv7dXPzRE=; b=ROL0YMMCJA3IJLSNHanqDcjg7Vf3jGlTd1RTYGpE2o/httMCVH0Io83YMITdqzMtZv ORLxkvZV+LqA+Zhw1dBv3zgw+wcTCnqiQb6DcF9iqZNxpbadUuad77BigtZylttfHfpX 4TXNzZXc/jT7VbfCgK5QCRNaBOXZ565hd/XAfbLXngVA4aerV4x8e8gVsaFh9WiV3pPx 9KBCakZ9XtE65jN5AgzqtMnELQlczENvIiR3ZZCwKOGM17qqNAABCiG+9g7H+8vvscQB LppzDuiMO93K2HK3YfcGoDcx+JZqTSkA+svBGQvnjxTmQvKN7BFIIF589++PI8OKQYvs sV0A== X-Gm-Message-State: APjAAAXNejorPrQZ4u5gMCOCD0XB0ceX+no/W0pdTYGjplBmDON6f5sh EjgHI6DmqMix24PEA7+ZRIL1pK04FockrnqPrLJFNw== X-Google-Smtp-Source: APXvYqyTTxGrF/DBC+wnwjgOgqQgtg9ZauusSN/Nf8cHy6jYbWWOyLnaGadiTTHaQl3gjL8+WVUpOZsMDqpZpbnB48Q= X-Received: by 2002:aca:edd5:: with SMTP id l204mr9820741oih.98.1576503499739; Mon, 16 Dec 2019 05:38:19 -0800 (PST) MIME-Version: 1.0 References: <20191212114734.6962-1-alex.bennee@linaro.org> In-Reply-To: <20191212114734.6962-1-alex.bennee@linaro.org> From: Peter Maydell Date: Mon, 16 Dec 2019 13:38:08 +0000 Message-ID: Subject: Re: [PATCH v2] target/arm: ensure we use current exception state after SCR update To: =?UTF-8?B?QWxleCBCZW5uw6ll?= Cc: QEMU Developers , qemu-arm , =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= , Richard Henderson Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::241 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 16 Dec 2019 13:38:23 -0000 On Thu, 12 Dec 2019 at 11:47, Alex Benn=C3=A9e wro= te: > > A write to the SCR can change the effective EL by droppping the system > from secure to non-secure mode. However if we use a cached current_el > from before the change we'll rebuild the flags incorrectly. To fix > this we introduce the ARM_CP_NEWEL CP flag to indicate the new EL > should be used when recomputing the flags. > > Signed-off-by: Alex Benn=C3=A9e > Tested-by: Philippe Mathieu-Daud=C3=A9 > Cc: Richard Henderson > Message-Id: <20191209143723.6368-1-alex.bennee@linaro.org> > > --- Applied to target-arm.next, thanks (I added a cc-stable). -- PMM From MAILER-DAEMON Mon Dec 16 09:03:39 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1igqyJ-0003dj-G3 for mharc-qemu-arm@gnu.org; Mon, 16 Dec 2019 09:03:39 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:58327) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1igqyG-0003ag-Jt for qemu-arm@nongnu.org; Mon, 16 Dec 2019 09:03:37 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1igqyF-0003fN-L0 for qemu-arm@nongnu.org; Mon, 16 Dec 2019 09:03:36 -0500 Received: from us-smtp-1.mimecast.com ([207.211.31.81]:55023 helo=us-smtp-delivery-1.mimecast.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1igqyF-0003e7-Hv for qemu-arm@nongnu.org; Mon, 16 Dec 2019 09:03:35 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1576505014; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=t6+fViJWtutY+mnVSFTppbDOaIGnV3IhxBHpKWV/0xQ=; b=LDc6WR51wNInv8gAo6dIG2p4Qwracdn5fkDCl2v5mv6i63VkxMq3JkVw5wmwzW1wrqfSuG LcL5vKs5QhTwzxKYRTQbz89hFjMJ9A3RdyuGC+dTC5iBbld1eyoNvVs2dPLeCoAxZY80HQ 0qMLhUGDd2WmPFbW3ssUt/kBL51S7Ug= Received: from mimecast-mx01.redhat.com (mimecast-mx01.redhat.com [209.132.183.4]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-325-EIXWn0LVPAK0NyPECAhhcQ-1; Mon, 16 Dec 2019 09:03:33 -0500 X-MC-Unique: EIXWn0LVPAK0NyPECAhhcQ-1 Received: from smtp.corp.redhat.com (int-mx05.intmail.prod.int.phx2.redhat.com [10.5.11.15]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx01.redhat.com (Postfix) with ESMTPS id 060CF8024DA; Mon, 16 Dec 2019 14:03:31 +0000 (UTC) Received: from laptop.redhat.com (ovpn-116-117.ams2.redhat.com [10.36.116.117]) by smtp.corp.redhat.com (Postfix) with ESMTP id 24908675BF; Mon, 16 Dec 2019 14:03:22 +0000 (UTC) From: Eric Auger To: eric.auger.pro@gmail.com, eric.auger@redhat.com, maz@kernel.org, kvmarm@lists.cs.columbia.edu, kvm@vger.kernel.org, qemu-devel@nongnu.org, qemu-arm@nongnu.org Cc: drjones@redhat.com, andre.przywara@arm.com, peter.maydell@linaro.org, yuzenghui@huawei.com, alexandru.elisei@arm.com, thuth@redhat.com Subject: [kvm-unit-tests PATCH 01/16] libcflat: Add other size defines Date: Mon, 16 Dec 2019 15:02:20 +0100 Message-Id: <20191216140235.10751-2-eric.auger@redhat.com> In-Reply-To: <20191216140235.10751-1-eric.auger@redhat.com> References: <20191216140235.10751-1-eric.auger@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.79 on 10.5.11.15 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 207.211.31.81 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 16 Dec 2019 14:03:37 -0000 Introduce additional SZ_256, SZ_8K, SZ_16K macros that will be used by ITS tests. Signed-off-by: Eric Auger --- lib/libcflat.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/lib/libcflat.h b/lib/libcflat.h index ea19f61..7092af2 100644 --- a/lib/libcflat.h +++ b/lib/libcflat.h @@ -36,7 +36,10 @@ #define ALIGN(x, a) __ALIGN((x), (a)) #define IS_ALIGNED(x, a) (((x) & ((typeof(x))(a) - 1)) =3D=3D 0) =20 +#define SZ_256 (1 << 8) #define SZ_4K (1 << 12) +#define SZ_8K (1 << 13) +#define SZ_16K (1 << 14) #define SZ_64K (1 << 16) #define SZ_2M (1 << 21) #define SZ_1G (1 << 30) --=20 2.20.1 From MAILER-DAEMON Mon Dec 16 09:03:47 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1igqyR-0003q5-MV for mharc-qemu-arm@gnu.org; Mon, 16 Dec 2019 09:03:47 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:58391) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1igqyO-0003mB-Gt for qemu-arm@nongnu.org; Mon, 16 Dec 2019 09:03:45 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1igqyN-0003n1-3V for qemu-arm@nongnu.org; Mon, 16 Dec 2019 09:03:44 -0500 Received: from us-smtp-1.mimecast.com ([207.211.31.81]:27767) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1igqyN-0003mq-06 for qemu-arm@nongnu.org; Mon, 16 Dec 2019 09:03:43 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1576505022; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding; bh=A9SY0krHFjydIQmqzREy9ABCAZgjAKMUQ2ClrNvBGYM=; b=GVTEM8evqKj2Re/gX6NfMwh9Jcgi3WdK4XnPoScBXspRpnSWeiEFYcu/sfa7j0ehiNsP+P 1DMf+jcNSP0kmT5oN/B+Jnm9UKNfqT6jeOoQgZnOviBJT/QPo+euzDCtZ8qUwzztzQWOvj drH3dM6xDT1d15xpJnSl06SBKdIto3o= Received: from mimecast-mx01.redhat.com (mimecast-mx01.redhat.com [209.132.183.4]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-5-KZ0hcHf3OsqMUOdqJHz5Tw-1; Mon, 16 Dec 2019 09:03:25 -0500 X-MC-Unique: KZ0hcHf3OsqMUOdqJHz5Tw-1 Received: from smtp.corp.redhat.com (int-mx05.intmail.prod.int.phx2.redhat.com [10.5.11.15]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx01.redhat.com (Postfix) with ESMTPS id B81C9100550E; Mon, 16 Dec 2019 14:03:22 +0000 (UTC) Received: from laptop.redhat.com (ovpn-116-117.ams2.redhat.com [10.36.116.117]) by smtp.corp.redhat.com (Postfix) with ESMTP id 60B4268860; Mon, 16 Dec 2019 14:03:16 +0000 (UTC) From: Eric Auger To: eric.auger.pro@gmail.com, eric.auger@redhat.com, maz@kernel.org, kvmarm@lists.cs.columbia.edu, kvm@vger.kernel.org, qemu-devel@nongnu.org, qemu-arm@nongnu.org Cc: drjones@redhat.com, andre.przywara@arm.com, peter.maydell@linaro.org, yuzenghui@huawei.com, alexandru.elisei@arm.com, thuth@redhat.com Subject: [kvm-unit-tests PATCH 00/16] arm/arm64: Add ITS tests Date: Mon, 16 Dec 2019 15:02:19 +0100 Message-Id: <20191216140235.10751-1-eric.auger@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.79 on 10.5.11.15 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 207.211.31.81 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 16 Dec 2019 14:03:46 -0000 This series is a revival of an RFC series sent in Dec 2016 [1]. Given the amount of code and the lack of traction at that time, I haven't respinned until now. However a recent bug found around the ITS migration convinced me that this work may deserve to be respinned and enhanced. Tests exercise main ITS commands and also test migration. With the migration framework, we are able to trigger the migration from guest and that is very practical actually. What is particular with the ITS programming is that most of the commands are passed through queues and there is real error handling. Invalid commands are just ignored and that is not really tester friendly. This series includes Andre's patch: "arm: gic: Provide per-IRQ helper functions" [2] The series can be fount at: https://github.com/eauger/kut/tree/its-v1 Best Regards Eric [1] [kvm-unit-tests RFC 00/15] arm/arm64: add ITS framework https://lists.gnu.org/archive/html/qemu-devel/2016-12/msg00575.html [2] [kvm-unit-tests PATCH 00/17] arm: gic: Test SPIs and interrupt groups https://patchwork.kernel.org/cover/11234975/ For ITS migration testing use: ./run_tests.sh -g migration (blocks on TCG but I think it is beyond the scope of that series) For other ITS tests: ./run_tests.sh -g its non migration tests can be launched invidually. For instance: ./arm-run arm/gic.flat -smp 8 -append 'its-trigger' Andre Przywara (1): arm: gic: Provide per-IRQ helper functions Eric Auger (15): libcflat: Add other size defines arm/arm64: gic: Introduce setup_irq() helper arm/arm64: gicv3: Add some re-distributor defines arm/arm64: ITS: Introspection tests arm/arm64: ITS: Test BASER arm/arm64: ITS: Set the LPI config and pending tables arm/arm64: ITS: Init the command queue arm/arm64: ITS: Enable/Disable LPIs at re-distributor level arm/arm64: ITS: its_enable_defaults arm/arm64: ITS: Device and collection Initialization arm/arm64: ITS: commands arm/arm64: ITS: INT functional tests arm/run: Allow Migration tests arm/arm64: ITS: migration tests arm/arm64: ITS: pending table migration test arm/Makefile.common | 3 +- arm/gic.c | 447 +++++++++++++++++++++++++++++++++-- arm/run | 2 +- arm/unittests.cfg | 39 ++++ lib/arm/asm/gic-v3-its.h | 217 +++++++++++++++++ lib/arm/asm/gic-v3.h | 87 +++++++ lib/arm/asm/gic.h | 13 ++ lib/arm/gic-v3-its-cmd.c | 462 +++++++++++++++++++++++++++++++++++++ lib/arm/gic-v3-its.c | 354 ++++++++++++++++++++++++++++ lib/arm/gic.c | 132 ++++++++++- lib/arm/io.c | 13 ++ lib/arm64/asm/gic-v3-its.h | 1 + lib/libcflat.h | 3 + 13 files changed, 1745 insertions(+), 28 deletions(-) create mode 100644 lib/arm/asm/gic-v3-its.h create mode 100644 lib/arm/gic-v3-its-cmd.c create mode 100644 lib/arm/gic-v3-its.c create mode 100644 lib/arm64/asm/gic-v3-its.h --=20 2.20.1 From MAILER-DAEMON Mon Dec 16 09:04:01 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1igqyf-00047i-2F for mharc-qemu-arm@gnu.org; Mon, 16 Dec 2019 09:04:01 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:58455) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1igqyZ-00042a-WB for qemu-arm@nongnu.org; Mon, 16 Dec 2019 09:03:56 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1igqyY-0003r9-Tv for qemu-arm@nongnu.org; Mon, 16 Dec 2019 09:03:55 -0500 Received: from us-smtp-2.mimecast.com ([205.139.110.61]:29679 helo=us-smtp-delivery-1.mimecast.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1igqyY-0003qv-Pq for qemu-arm@nongnu.org; Mon, 16 Dec 2019 09:03:54 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1576505034; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=GOWPhC17h35AGp/dOHacyK3ecv9iQL7rfh6w3pp+A2s=; b=LsBgQxB/0JCpfTSCHtqMwR6TXD+rWkxxPUgHHa2BS5dBmA5ncH2HIAqKyXwUbrvrmm7R7G Nt4WR2StgbL12IiYoHggSC+tcyqIWnnsxEYsWR1REde7r6XUmUGBYfokKieWIM00b9WUSb 4zoPo9V9TI7/R9LZyAbKq7l3vqj/Ifs= Received: from mimecast-mx01.redhat.com (mimecast-mx01.redhat.com [209.132.183.4]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-236-UkzAK9YLPwyQPAgoFtqeUw-1; Mon, 16 Dec 2019 09:03:53 -0500 X-MC-Unique: UkzAK9YLPwyQPAgoFtqeUw-1 Received: from smtp.corp.redhat.com (int-mx05.intmail.prod.int.phx2.redhat.com [10.5.11.15]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx01.redhat.com (Postfix) with ESMTPS id 58472DBE7; Mon, 16 Dec 2019 14:03:51 +0000 (UTC) Received: from laptop.redhat.com (ovpn-116-117.ams2.redhat.com [10.36.116.117]) by smtp.corp.redhat.com (Postfix) with ESMTP id 717CF675B8; Mon, 16 Dec 2019 14:03:48 +0000 (UTC) From: Eric Auger To: eric.auger.pro@gmail.com, eric.auger@redhat.com, maz@kernel.org, kvmarm@lists.cs.columbia.edu, kvm@vger.kernel.org, qemu-devel@nongnu.org, qemu-arm@nongnu.org Cc: drjones@redhat.com, andre.przywara@arm.com, peter.maydell@linaro.org, yuzenghui@huawei.com, alexandru.elisei@arm.com, thuth@redhat.com Subject: [kvm-unit-tests PATCH 04/16] arm/arm64: gicv3: Add some re-distributor defines Date: Mon, 16 Dec 2019 15:02:23 +0100 Message-Id: <20191216140235.10751-5-eric.auger@redhat.com> In-Reply-To: <20191216140235.10751-1-eric.auger@redhat.com> References: <20191216140235.10751-1-eric.auger@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.79 on 10.5.11.15 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 205.139.110.61 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 16 Dec 2019 14:03:57 -0000 PROPBASER, PENDBASE and GICR_CTRL will be used for LPI management. Signed-off-by: Eric Auger --- lib/arm/asm/gic-v3.h | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/lib/arm/asm/gic-v3.h b/lib/arm/asm/gic-v3.h index 4a445a5..d02f4a4 100644 --- a/lib/arm/asm/gic-v3.h +++ b/lib/arm/asm/gic-v3.h @@ -18,6 +18,7 @@ * We expect to be run in Non-secure mode, thus we define the * group1 enable bits with respect to that view. */ +#define GICD_CTLR 0x0000 #define GICD_CTLR_RWP (1U << 31) #define GICD_CTLR_ARE_NS (1U << 4) #define GICD_CTLR_ENABLE_G1A (1U << 1) @@ -35,6 +36,11 @@ #define GICR_ISENABLER0 GICD_ISENABLER #define GICR_IPRIORITYR0 GICD_IPRIORITYR =20 +#define GICR_PROPBASER 0x0070 +#define GICR_PENDBASER 0x0078 +#define GICR_CTLR GICD_CTLR +#define GICR_CTLR_ENABLE_LPIS (1UL << 0) + #define ICC_SGI1R_AFFINITY_1_SHIFT 16 #define ICC_SGI1R_AFFINITY_2_SHIFT 32 #define ICC_SGI1R_AFFINITY_3_SHIFT 48 --=20 2.20.1 From MAILER-DAEMON Mon Dec 16 09:04:03 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1igqyg-000499-VV for mharc-qemu-arm@gnu.org; Mon, 16 Dec 2019 09:04:03 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:58479) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1igqyb-00045O-JM for qemu-arm@nongnu.org; Mon, 16 Dec 2019 09:03:59 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1igqyW-0003qN-JH for qemu-arm@nongnu.org; Mon, 16 Dec 2019 09:03:57 -0500 Received: from us-smtp-2.mimecast.com ([205.139.110.61]:29703 helo=us-smtp-delivery-1.mimecast.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1igqyW-0003q7-GC for qemu-arm@nongnu.org; Mon, 16 Dec 2019 09:03:52 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1576505031; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=wIBn80+V74amPBupfe+F9anDq8XfKyQu39ZmejTiR10=; b=BxJVH3Xah74LAYZCEHLAOxai6gwRpmdRthnFhcGx0cH2C9U5xVKsBJE2ed4Y2dam1Iaoap p5lin7XPmHjffgncFGs0yjeb5uWUbfimQE+EGOpT7n9MvBu3alTJ/q+iT7sOhaamYJ/CPc T/nuUOm4Lm2Z8b6LRYu5wHNiN6dhTf4= Received: from mimecast-mx01.redhat.com (mimecast-mx01.redhat.com [209.132.183.4]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-234-J5MIrWbNMCydWN3sERnNSw-1; Mon, 16 Dec 2019 09:03:50 -0500 X-MC-Unique: J5MIrWbNMCydWN3sERnNSw-1 Received: from smtp.corp.redhat.com (int-mx05.intmail.prod.int.phx2.redhat.com [10.5.11.15]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx01.redhat.com (Postfix) with ESMTPS id 17434DBC9; Mon, 16 Dec 2019 14:03:48 +0000 (UTC) Received: from laptop.redhat.com (ovpn-116-117.ams2.redhat.com [10.36.116.117]) by smtp.corp.redhat.com (Postfix) with ESMTP id C94ED675B9; Mon, 16 Dec 2019 14:03:38 +0000 (UTC) From: Eric Auger To: eric.auger.pro@gmail.com, eric.auger@redhat.com, maz@kernel.org, kvmarm@lists.cs.columbia.edu, kvm@vger.kernel.org, qemu-devel@nongnu.org, qemu-arm@nongnu.org Cc: drjones@redhat.com, andre.przywara@arm.com, peter.maydell@linaro.org, yuzenghui@huawei.com, alexandru.elisei@arm.com, thuth@redhat.com Subject: [kvm-unit-tests PATCH 03/16] arm/arm64: gic: Introduce setup_irq() helper Date: Mon, 16 Dec 2019 15:02:22 +0100 Message-Id: <20191216140235.10751-4-eric.auger@redhat.com> In-Reply-To: <20191216140235.10751-1-eric.auger@redhat.com> References: <20191216140235.10751-1-eric.auger@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.79 on 10.5.11.15 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 205.139.110.61 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 16 Dec 2019 14:04:00 -0000 ipi_enable() code would be reusable for other interrupts than IPI. Let's rename it setup_irq() and pass an interrupt handler pointer. We also export it to use it in other tests such as the PMU's one. Signed-off-by: Eric Auger --- arm/gic.c | 24 +++--------------------- lib/arm/asm/gic.h | 3 +++ lib/arm/gic.c | 11 +++++++++++ 3 files changed, 17 insertions(+), 21 deletions(-) diff --git a/arm/gic.c b/arm/gic.c index fcf4c1f..ba43ae5 100644 --- a/arm/gic.c +++ b/arm/gic.c @@ -215,20 +215,9 @@ static void ipi_test_smp(void) report_prefix_pop(); } =20 -static void ipi_enable(void) -{ - gic_enable_defaults(); -#ifdef __arm__ - install_exception_handler(EXCPTN_IRQ, ipi_handler); -#else - install_irq_handler(EL1H_IRQ, ipi_handler); -#endif - local_irq_enable(); -} - static void ipi_send(void) { - ipi_enable(); + setup_irq(ipi_handler); wait_on_ready(); ipi_test_self(); ipi_test_smp(); @@ -238,7 +227,7 @@ static void ipi_send(void) =20 static void ipi_recv(void) { - ipi_enable(); + setup_irq(ipi_handler); cpumask_set_cpu(smp_processor_id(), &ready); while (1) wfi(); @@ -295,14 +284,7 @@ static void ipi_clear_active_handler(struct pt_regs = *regs __unused) static void run_active_clear_test(void) { report_prefix_push("active"); - gic_enable_defaults(); -#ifdef __arm__ - install_exception_handler(EXCPTN_IRQ, ipi_clear_active_handler); -#else - install_irq_handler(EL1H_IRQ, ipi_clear_active_handler); -#endif - local_irq_enable(); - + setup_irq(ipi_clear_active_handler); ipi_test_self(); report_prefix_pop(); } diff --git a/lib/arm/asm/gic.h b/lib/arm/asm/gic.h index 21cdb58..55dd84b 100644 --- a/lib/arm/asm/gic.h +++ b/lib/arm/asm/gic.h @@ -82,5 +82,8 @@ void gic_set_irq_target(int irq, int cpu); void gic_set_irq_group(int irq, int group); int gic_get_irq_group(int irq); =20 +typedef void (*handler_t)(struct pt_regs *regs __unused); +extern void setup_irq(handler_t handler); + #endif /* !__ASSEMBLY__ */ #endif /* _ASMARM_GIC_H_ */ diff --git a/lib/arm/gic.c b/lib/arm/gic.c index aa9cb86..8416dde 100644 --- a/lib/arm/gic.c +++ b/lib/arm/gic.c @@ -236,3 +236,14 @@ int gic_get_irq_group(int irq) { return gic_masked_irq_bits(irq, GICD_IGROUPR, 1, 0, ACCESS_READ); } + +void setup_irq(handler_t handler) +{ + gic_enable_defaults(); +#ifdef __arm__ + install_exception_handler(EXCPTN_IRQ, handler); +#else + install_irq_handler(EL1H_IRQ, handler); +#endif + local_irq_enable(); +} --=20 2.20.1 From MAILER-DAEMON Mon Dec 16 09:04:08 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1igqym-0004CP-0p for mharc-qemu-arm@gnu.org; Mon, 16 Dec 2019 09:04:08 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:58561) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1igqyf-00047l-FU for qemu-arm@nongnu.org; Mon, 16 Dec 2019 09:04:03 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1igqyc-0003sm-3P for qemu-arm@nongnu.org; Mon, 16 Dec 2019 09:04:00 -0500 Received: from us-smtp-delivery-1.mimecast.com ([205.139.110.120]:23090 helo=us-smtp-1.mimecast.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1igqyb-0003sV-V0 for qemu-arm@nongnu.org; Mon, 16 Dec 2019 09:03:58 -0500 DKIM-Signature: v=1; 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Mon, 16 Dec 2019 14:03:54 +0000 (UTC) Received: from laptop.redhat.com (ovpn-116-117.ams2.redhat.com [10.36.116.117]) by smtp.corp.redhat.com (Postfix) with ESMTP id B2C05675B8; Mon, 16 Dec 2019 14:03:51 +0000 (UTC) From: Eric Auger To: eric.auger.pro@gmail.com, eric.auger@redhat.com, maz@kernel.org, kvmarm@lists.cs.columbia.edu, kvm@vger.kernel.org, qemu-devel@nongnu.org, qemu-arm@nongnu.org Cc: drjones@redhat.com, andre.przywara@arm.com, peter.maydell@linaro.org, yuzenghui@huawei.com, alexandru.elisei@arm.com, thuth@redhat.com Subject: [kvm-unit-tests PATCH 05/16] arm/arm64: ITS: Introspection tests Date: Mon, 16 Dec 2019 15:02:24 +0100 Message-Id: <20191216140235.10751-6-eric.auger@redhat.com> In-Reply-To: <20191216140235.10751-1-eric.auger@redhat.com> References: <20191216140235.10751-1-eric.auger@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.79 on 10.5.11.15 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 205.139.110.120 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 16 Dec 2019 14:04:03 -0000 Detect the presence of an ITS as part of the GICv3 init routine, initialize its base address and read few registers the IIDR, the TYPER to store its dimensioning parameters. This is our first ITS test, belonging to a new "its" group. Signed-off-by: Eric Auger --- arm/Makefile.common | 1 + arm/gic.c | 34 +++++++++++ arm/unittests.cfg | 6 ++ lib/arm/asm/gic-v3-its.h | 116 +++++++++++++++++++++++++++++++++++++ lib/arm/asm/gic.h | 1 + lib/arm/gic-v3-its.c | 41 +++++++++++++ lib/arm/gic.c | 31 ++++++++-- lib/arm64/asm/gic-v3-its.h | 1 + 8 files changed, 226 insertions(+), 5 deletions(-) create mode 100644 lib/arm/asm/gic-v3-its.h create mode 100644 lib/arm/gic-v3-its.c create mode 100644 lib/arm64/asm/gic-v3-its.h diff --git a/arm/Makefile.common b/arm/Makefile.common index b8988f2..1aae5a3 100644 --- a/arm/Makefile.common +++ b/arm/Makefile.common @@ -52,6 +52,7 @@ cflatobjs +=3D lib/arm/psci.o cflatobjs +=3D lib/arm/smp.o cflatobjs +=3D lib/arm/delay.o cflatobjs +=3D lib/arm/gic.o lib/arm/gic-v2.o lib/arm/gic-v3.o +cflatobjs +=3D lib/arm/gic-v3-its.o =20 OBJDIRS +=3D lib/arm =20 diff --git a/arm/gic.c b/arm/gic.c index ba43ae5..adeb981 100644 --- a/arm/gic.c +++ b/arm/gic.c @@ -506,6 +506,36 @@ static void gic_test_mmio(void) test_targets(nr_irqs); } =20 +static void test_its_introspection(void) +{ + struct its_typer *typer =3D &its_data.typer; + + if (!gicv3_its_base()) { + report_skip("No ITS, skip ..."); + return; + } + + /* IIDR */ + report(test_readonly_32(gicv3_its_base() + GITS_IIDR, false), + "GITS_IIDR is read-only"), + + /* TYPER */ + report(test_readonly_32(gicv3_its_base() + GITS_TYPER, false), + "GITS_TYPER is read-only"); + + report(typer->phys_lpi, "ITS supports physical LPIs"); + report_info("vLPI support: %s", typer->virt_lpi ? "yes" : "no"); + report_info("ITT entry size =3D 0x%x", typer->ite_size); + report_info("Bit Count: EventID=3D%d DeviceId=3D%d CollId=3D%d", + typer->eventid_bits, typer->deviceid_bits, + typer->collid_bits); + report(typer->eventid_bits && typer->deviceid_bits && + typer->collid_bits, "ID spaces"); + report(!typer->hw_collections, "collections only in ext memory"); + report_info("Target address format %s", + typer->pta ? "Redist basse address" : "PE #"); +} + int main(int argc, char **argv) { if (!gic_init()) { @@ -537,6 +567,10 @@ int main(int argc, char **argv) report_prefix_push(argv[1]); gic_test_mmio(); report_prefix_pop(); + } else if (strcmp(argv[1], "its-introspection") =3D=3D 0) { + report_prefix_push(argv[1]); + test_its_introspection(); + report_prefix_pop(); } else { report_abort("Unknown subtest '%s'", argv[1]); } diff --git a/arm/unittests.cfg b/arm/unittests.cfg index daeb5a0..bd20460 100644 --- a/arm/unittests.cfg +++ b/arm/unittests.cfg @@ -122,6 +122,12 @@ smp =3D $MAX_SMP extra_params =3D -machine gic-version=3D3 -append 'active' groups =3D gic =20 +[its-introspection] +file =3D gic.flat +smp =3D $MAX_SMP +extra_params =3D -machine gic-version=3D3 -append 'its-introspection' +groups =3D its + # Test PSCI emulation [psci] file =3D psci.flat diff --git a/lib/arm/asm/gic-v3-its.h b/lib/arm/asm/gic-v3-its.h new file mode 100644 index 0000000..2ce483e --- /dev/null +++ b/lib/arm/asm/gic-v3-its.h @@ -0,0 +1,116 @@ +/* + * All ITS* defines are lifted from include/linux/irqchip/arm-gic-v3.h + * + * Copyright (C) 2016, Red Hat Inc, Andrew Jones + * + * This work is licensed under the terms of the GNU LGPL, version 2. + */ +#ifndef _ASMARM_GIC_V3_ITS_H_ +#define _ASMARM_GIC_V3_ITS_H_ + +#ifndef __ASSEMBLY__ + +#define GITS_CTLR 0x0000 +#define GITS_IIDR 0x0004 +#define GITS_TYPER 0x0008 +#define GITS_CBASER 0x0080 +#define GITS_CWRITER 0x0088 +#define GITS_CREADR 0x0090 +#define GITS_BASER 0x0100 + +#define GITS_TYPER_PLPIS (1UL << 0) +#define GITS_TYPER_IDBITS_SHIFT 8 +#define GITS_TYPER_DEVBITS_SHIFT 13 +#define GITS_TYPER_DEVBITS(r) ((((r) >> GITS_TYPER_DEVBITS_SHI= FT) & 0x1f) + 1) +#define GITS_TYPER_PTA (1UL << 19) +#define GITS_TYPER_HWCOLLCNT_SHIFT 24 + +#define GITS_CTLR_ENABLE (1U << 0) + +#define GITS_CBASER_VALID (1UL << 63) +#define GITS_CBASER_SHAREABILITY_SHIFT (10) +#define GITS_CBASER_INNER_CACHEABILITY_SHIFT (59) +#define GITS_CBASER_OUTER_CACHEABILITY_SHIFT (53) +#define GITS_CBASER_SHAREABILITY_MASK = \ + GIC_BASER_SHAREABILITY(GITS_CBASER, SHAREABILITY_MASK) +#define GITS_CBASER_INNER_CACHEABILITY_MASK = \ + GIC_BASER_CACHEABILITY(GITS_CBASER, INNER, MASK) +#define GITS_CBASER_OUTER_CACHEABILITY_MASK = \ + GIC_BASER_CACHEABILITY(GITS_CBASER, OUTER, MASK) +#define GITS_CBASER_CACHEABILITY_MASK GITS_CBASER_INNER_CACHEABILITY_MAS= K + +#define GITS_CBASER_InnerShareable = \ + GIC_BASER_SHAREABILITY(GITS_CBASER, InnerShareable) + +#define GITS_CBASER_nCnB GIC_BASER_CACHEABILITY(GITS_CBASER, INNE= R, nCnB) +#define GITS_CBASER_nC GIC_BASER_CACHEABILITY(GITS_CBASER, INNE= R, nC) +#define GITS_CBASER_RaWt GIC_BASER_CACHEABILITY(GITS_CBASER, INNE= R, RaWt) +#define GITS_CBASER_RaWb GIC_BASER_CACHEABILITY(GITS_CBASER, INNE= R, RaWt) +#define GITS_CBASER_WaWt GIC_BASER_CACHEABILITY(GITS_CBASER, INNE= R, WaWt) +#define GITS_CBASER_WaWb GIC_BASER_CACHEABILITY(GITS_CBASER, INNE= R, WaWb) +#define GITS_CBASER_RaWaWt GIC_BASER_CACHEABILITY(GITS_CBASER, INNE= R, RaWaWt) +#define GITS_CBASER_RaWaWb GIC_BASER_CACHEABILITY(GITS_CBASER, INNE= R, RaWaWb) + +#define GITS_BASER_NR_REGS 8 + +#define GITS_BASER_VALID (1UL << 63) +#define GITS_BASER_INDIRECT (1ULL << 62) + +#define GITS_BASER_INNER_CACHEABILITY_SHIFT (59) +#define GITS_BASER_OUTER_CACHEABILITY_SHIFT (53) +#define GITS_BASER_CACHEABILITY_MASK 0x7 + +#define GITS_BASER_nCnB GIC_BASER_CACHEABILITY(GITS_BASER, INNER= , nCnB) + +#define GITS_BASER_TYPE_SHIFT (56) +#define GITS_BASER_TYPE(r) (((r) >> GITS_BASER_TYPE_SHIFT) = & 7) +#define GITS_BASER_ENTRY_SIZE_SHIFT (48) +#define GITS_BASER_ENTRY_SIZE(r) ((((r) >> GITS_BASER_ENTRY_SIZE_= SHIFT) & 0x1f) + 1) +#define GITS_BASER_SHAREABILITY_SHIFT (10) +#define GITS_BASER_InnerShareable = \ + GIC_BASER_SHAREABILITY(GITS_BASER, InnerShareable) +#define GITS_BASER_PAGE_SIZE_SHIFT (8) +#define GITS_BASER_PAGE_SIZE_4K (0UL << GITS_BASER_PAGE_SIZE_SHI= FT) +#define GITS_BASER_PAGE_SIZE_16K (1UL << GITS_BASER_PAGE_SIZE_SHI= FT) +#define GITS_BASER_PAGE_SIZE_64K (2UL << GITS_BASER_PAGE_SIZE_SHI= FT) +#define GITS_BASER_PAGE_SIZE_MASK (3UL << GITS_BASER_PAGE_SIZE_SHI= FT) +#define GITS_BASER_PAGES_MAX 256 +#define GITS_BASER_PAGES_SHIFT (0) +#define GITS_BASER_NR_PAGES(r) (((r) & 0xff) + 1) +#define GITS_BASER_PHYS_ADDR_MASK 0xFFFFFFFFF000 + +#define GITS_BASER_TYPE_NONE 0 +#define GITS_BASER_TYPE_DEVICE 1 +#define GITS_BASER_TYPE_VCPU 2 +#define GITS_BASER_TYPE_CPU 3 +#define GITS_BASER_TYPE_COLLECTION 4 + +#define ITS_FLAGS_CMDQ_NEEDS_FLUSHING (1ULL << 0) + +struct its_typer { + unsigned int ite_size; + unsigned int eventid_bits; + unsigned int deviceid_bits; + unsigned int collid_bits; + unsigned int hw_collections; + bool pta; + bool cil; + bool cct; + bool phys_lpi; + bool virt_lpi; +}; + +struct its_data { + void *base; + struct its_typer typer; +}; + +extern struct its_data its_data; + +#define gicv3_its_base() (its_data.base) + +extern void its_parse_typer(void); +extern void its_init(void); + +#endif /* !__ASSEMBLY__ */ +#endif /* _ASMARM_GIC_V3_ITS_H_ */ diff --git a/lib/arm/asm/gic.h b/lib/arm/asm/gic.h index 55dd84b..b44da9c 100644 --- a/lib/arm/asm/gic.h +++ b/lib/arm/asm/gic.h @@ -40,6 +40,7 @@ =20 #include #include +#include =20 #define PPI(irq) ((irq) + 16) #define SPI(irq) ((irq) + GIC_FIRST_SPI) diff --git a/lib/arm/gic-v3-its.c b/lib/arm/gic-v3-its.c new file mode 100644 index 0000000..34f4d0e --- /dev/null +++ b/lib/arm/gic-v3-its.c @@ -0,0 +1,41 @@ +/* + * Copyright (C) 2016, Red Hat Inc, Eric Auger + * + * This work is licensed under the terms of the GNU LGPL, version 2. + */ +#include + +struct its_data its_data; + +void its_parse_typer(void) +{ + u64 typer =3D readq(gicv3_its_base() + GITS_TYPER); + + its_data.typer.ite_size =3D ((typer >> 4) & 0xf) + 1; + its_data.typer.pta =3D typer & GITS_TYPER_PTA; + its_data.typer.eventid_bits =3D + ((typer >> GITS_TYPER_IDBITS_SHIFT) & 0x1f) + 1; + its_data.typer.deviceid_bits =3D GITS_TYPER_DEVBITS(typer) + 1; + + its_data.typer.cil =3D (typer >> 36) & 0x1; + if (its_data.typer.cil) + its_data.typer.collid_bits =3D ((typer >> 32) & 0xf) + 1; + else + its_data.typer.collid_bits =3D 16; + + its_data.typer.hw_collections =3D + (typer >> GITS_TYPER_HWCOLLCNT_SHIFT) & 0xff; + + its_data.typer.cct =3D typer & 0x4; + its_data.typer.virt_lpi =3D typer & 0x2; + its_data.typer.phys_lpi =3D typer & GITS_TYPER_PLPIS; +} + +void its_init(void) +{ + if (!its_data.base) + return; + + its_parse_typer(); +} + diff --git a/lib/arm/gic.c b/lib/arm/gic.c index 8416dde..f9a6f57 100644 --- a/lib/arm/gic.c +++ b/lib/arm/gic.c @@ -6,6 +6,7 @@ #include #include #include +#include =20 struct gicv2_data gicv2_data; struct gicv3_data gicv3_data; @@ -44,12 +45,14 @@ static const struct gic_common_ops gicv3_common_ops =3D= { * Documentation/devicetree/bindings/interrupt-controller/arm,gic-v3.txt */ static bool -gic_get_dt_bases(const char *compatible, void **base1, void **base2) +gic_get_dt_bases(const char *compatible, void **base1, void **base2, + void **base3) { struct dt_pbus_reg reg; - struct dt_device gic; + struct dt_device gic, its; struct dt_bus bus; - int node, ret, i; + int node, subnode, ret, i, len; + const void *fdt =3D dt_fdt(); =20 dt_bus_init_defaults(&bus); dt_device_init(&gic, &bus, NULL); @@ -74,19 +77,36 @@ gic_get_dt_bases(const char *compatible, void **base1= , void **base2) base2[i] =3D ioremap(reg.addr, reg.size); } =20 + if (base3 && !strcmp(compatible, "arm,gic-v3")) { + dt_for_each_subnode(node, subnode) { + const struct fdt_property *prop; + + prop =3D fdt_get_property(fdt, subnode, + "compatible", &len); + if (!strcmp((char *)prop->data, "arm,gic-v3-its")) { + dt_device_bind_node(&its, subnode); + ret =3D dt_pbus_translate(&its, 0, ®); + assert(ret =3D=3D 0); + *base3 =3D ioremap(reg.addr, reg.size); + break; + } + } + + } + return true; } =20 int gicv2_init(void) { return gic_get_dt_bases("arm,cortex-a15-gic", - &gicv2_data.dist_base, &gicv2_data.cpu_base); + &gicv2_data.dist_base, &gicv2_data.cpu_base, NULL); } =20 int gicv3_init(void) { return gic_get_dt_bases("arm,gic-v3", &gicv3_data.dist_base, - &gicv3_data.redist_bases[0]); + &gicv3_data.redist_bases[0], &its_data.base); } =20 int gic_version(void) @@ -104,6 +124,7 @@ int gic_init(void) gic_common_ops =3D &gicv2_common_ops; else if (gicv3_init()) gic_common_ops =3D &gicv3_common_ops; + its_init(); return gic_version(); } =20 diff --git a/lib/arm64/asm/gic-v3-its.h b/lib/arm64/asm/gic-v3-its.h new file mode 100644 index 0000000..083cba4 --- /dev/null +++ b/lib/arm64/asm/gic-v3-its.h @@ -0,0 +1 @@ +#include "../../arm/asm/gic-v3-its.h" --=20 2.20.1 From MAILER-DAEMON Mon Dec 16 09:04:10 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1igqym-0004DQ-H1 for mharc-qemu-arm@gnu.org; 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b=GBpT9wgFsiqCBwL1qL8i0ZjoimNi2wlht3Z6STIn+N5GBCf9aZcrGtmgBfngh+WJTCEPvM qKumrRLvLYWpr+f7VbRl4c5gLfCvDoU6P1gScsc40YJjxMMwgXPjTU+fNgDHaVg4fUoIsx l7IsQ+KB++pz7brJSp3Qmst7JKMN6c4= Received: from mimecast-mx01.redhat.com (mimecast-mx01.redhat.com [209.132.183.4]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-394-4Pdl_56RMCGLwFQgWWRfxw-1; Mon, 16 Dec 2019 09:04:00 -0500 X-MC-Unique: 4Pdl_56RMCGLwFQgWWRfxw-1 Received: from smtp.corp.redhat.com (int-mx05.intmail.prod.int.phx2.redhat.com [10.5.11.15]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx01.redhat.com (Postfix) with ESMTPS id DA4FC107ACC9; Mon, 16 Dec 2019 14:03:57 +0000 (UTC) Received: from laptop.redhat.com (ovpn-116-117.ams2.redhat.com [10.36.116.117]) by smtp.corp.redhat.com (Postfix) with ESMTP id F2565675BE; Mon, 16 Dec 2019 14:03:54 +0000 (UTC) From: Eric Auger To: eric.auger.pro@gmail.com, eric.auger@redhat.com, maz@kernel.org, kvmarm@lists.cs.columbia.edu, kvm@vger.kernel.org, qemu-devel@nongnu.org, qemu-arm@nongnu.org Cc: drjones@redhat.com, andre.przywara@arm.com, peter.maydell@linaro.org, yuzenghui@huawei.com, alexandru.elisei@arm.com, thuth@redhat.com Subject: [kvm-unit-tests PATCH 06/16] arm/arm64: ITS: Test BASER Date: Mon, 16 Dec 2019 15:02:25 +0100 Message-Id: <20191216140235.10751-7-eric.auger@redhat.com> In-Reply-To: <20191216140235.10751-1-eric.auger@redhat.com> References: <20191216140235.10751-1-eric.auger@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.79 on 10.5.11.15 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 205.139.110.120 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 16 Dec 2019 14:04:05 -0000 Add helper routines to parse and set up BASER registers. Add a new test dedicated to BASER accesses. Signed-off-by: Eric Auger --- arm/gic.c | 20 ++++++++++ arm/unittests.cfg | 6 +++ lib/arm/asm/gic-v3-its.h | 17 ++++++++ lib/arm/gic-v3-its.c | 84 ++++++++++++++++++++++++++++++++++++++++ 4 files changed, 127 insertions(+) diff --git a/arm/gic.c b/arm/gic.c index adeb981..8b56fce 100644 --- a/arm/gic.c +++ b/arm/gic.c @@ -536,6 +536,22 @@ static void test_its_introspection(void) typer->pta ? "Redist basse address" : "PE #"); } =20 +static void test_its_baser(void) +{ + struct its_baser *dev_baser, *coll_baser; + + if (!gicv3_its_base()) { + report_skip("No ITS, skip ..."); + return; + } + + dev_baser =3D its_lookup_baser(GITS_BASER_TYPE_DEVICE); + coll_baser =3D its_lookup_baser(GITS_BASER_TYPE_COLLECTION); + report(dev_baser && coll_baser, "detect device and collection BASER"); + report_info("device baser entry_size =3D 0x%x", dev_baser->esz); + report_info("collection baser entry_size =3D 0x%x", dev_baser->esz); +} + int main(int argc, char **argv) { if (!gic_init()) { @@ -571,6 +587,10 @@ int main(int argc, char **argv) report_prefix_push(argv[1]); test_its_introspection(); report_prefix_pop(); + } else if (strcmp(argv[1], "its-baser") =3D=3D 0) { + report_prefix_push(argv[1]); + test_its_baser(); + report_prefix_pop(); } else { report_abort("Unknown subtest '%s'", argv[1]); } diff --git a/arm/unittests.cfg b/arm/unittests.cfg index bd20460..2234a0f 100644 --- a/arm/unittests.cfg +++ b/arm/unittests.cfg @@ -128,6 +128,12 @@ smp =3D $MAX_SMP extra_params =3D -machine gic-version=3D3 -append 'its-introspection' groups =3D its =20 +[its-baser] +file =3D gic.flat +smp =3D $MAX_SMP +extra_params =3D -machine gic-version=3D3 -append 'its-baser' +groups =3D its + # Test PSCI emulation [psci] file =3D psci.flat diff --git a/lib/arm/asm/gic-v3-its.h b/lib/arm/asm/gic-v3-its.h index 2ce483e..0c0178d 100644 --- a/lib/arm/asm/gic-v3-its.h +++ b/lib/arm/asm/gic-v3-its.h @@ -100,9 +100,23 @@ struct its_typer { bool virt_lpi; }; =20 +struct its_baser { + unsigned int index; + int type; + u64 cache; + int shr; + size_t psz; + int nr_pages; + bool indirect; + phys_addr_t table_addr; + bool valid; + int esz; +}; + struct its_data { void *base; struct its_typer typer; + struct its_baser baser[GITS_BASER_NR_REGS]; }; =20 extern struct its_data its_data; @@ -111,6 +125,9 @@ extern struct its_data its_data; =20 extern void its_parse_typer(void); extern void its_init(void); +extern int its_parse_baser(int i, struct its_baser *baser); +extern void its_setup_baser(int i, struct its_baser *baser); +extern struct its_baser *its_lookup_baser(int type); =20 #endif /* !__ASSEMBLY__ */ #endif /* _ASMARM_GIC_V3_ITS_H_ */ diff --git a/lib/arm/gic-v3-its.c b/lib/arm/gic-v3-its.c index 34f4d0e..303022f 100644 --- a/lib/arm/gic-v3-its.c +++ b/lib/arm/gic-v3-its.c @@ -4,6 +4,7 @@ * This work is licensed under the terms of the GNU LGPL, version 2. */ #include +#include =20 struct its_data its_data; =20 @@ -31,11 +32,94 @@ void its_parse_typer(void) its_data.typer.phys_lpi =3D typer & GITS_TYPER_PLPIS; } =20 +int its_parse_baser(int i, struct its_baser *baser) +{ + void *reg_addr =3D gicv3_its_base() + GITS_BASER + i * 8; + u64 val =3D readq(reg_addr); + + if (!val) { + memset(baser, 0, sizeof(*baser)); + return -1; + } + + baser->valid =3D val & GITS_BASER_VALID; + baser->indirect =3D val & GITS_BASER_INDIRECT; + baser->type =3D GITS_BASER_TYPE(val); + baser->esz =3D GITS_BASER_ENTRY_SIZE(val); + baser->nr_pages =3D GITS_BASER_NR_PAGES(val); + baser->table_addr =3D val & GITS_BASER_PHYS_ADDR_MASK; + baser->cache =3D (val >> GITS_BASER_INNER_CACHEABILITY_SHIFT) & + GITS_BASER_CACHEABILITY_MASK; + switch (val & GITS_BASER_PAGE_SIZE_MASK) { + case GITS_BASER_PAGE_SIZE_4K: + baser->psz =3D SZ_4K; + break; + case GITS_BASER_PAGE_SIZE_16K: + baser->psz =3D SZ_16K; + break; + case GITS_BASER_PAGE_SIZE_64K: + baser->psz =3D SZ_64K; + break; + default: + baser->psz =3D SZ_64K; + } + baser->shr =3D (val >> 10) & 0x3; + return 0; +} + +struct its_baser *its_lookup_baser(int type) +{ + int i; + + for (i =3D 0; i < GITS_BASER_NR_REGS; i++) { + struct its_baser *baser =3D &its_data.baser[i]; + + if (baser->type =3D=3D type) + return baser; + } + return NULL; +} + void its_init(void) { + int i; if (!its_data.base) return; =20 its_parse_typer(); + for (i =3D 0; i < GITS_BASER_NR_REGS; i++) + its_parse_baser(i, &its_data.baser[i]); +} + +void its_setup_baser(int i, struct its_baser *baser) +{ + unsigned long n =3D (baser->nr_pages * baser->psz) >> PAGE_SHIFT; + unsigned long order =3D is_power_of_2(n) ? fls(n) : fls(n) + 1; + u64 val; + + baser->table_addr =3D (u64)virt_to_phys(alloc_pages(order)); + + val =3D ((u64)baser->table_addr | + ((u64)baser->type << GITS_BASER_TYPE_SHIFT) | + ((u64)(baser->esz - 1) << GITS_BASER_ENTRY_SIZE_SHIFT) | + ((baser->nr_pages - 1) << GITS_BASER_PAGES_SHIFT) | + baser->cache | + baser->shr | + (u64)baser->indirect << 62 | + (u64)baser->valid << 63); + + switch (baser->psz) { + case SZ_4K: + val |=3D GITS_BASER_PAGE_SIZE_4K; + break; + case SZ_16K: + val |=3D GITS_BASER_PAGE_SIZE_16K; + break; + case SZ_64K: + val |=3D GITS_BASER_PAGE_SIZE_64K; + break; + } + + writeq(val, gicv3_its_base() + GITS_BASER + i * 8); } =20 --=20 2.20.1 From MAILER-DAEMON Mon Dec 16 09:04:13 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1igqyr-0004H6-4h for mharc-qemu-arm@gnu.org; Mon, 16 Dec 2019 09:04:13 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:58639) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1igqym-0004DW-SH for qemu-arm@nongnu.org; Mon, 16 Dec 2019 09:04:10 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1igqyl-0003wH-9e for qemu-arm@nongnu.org; Mon, 16 Dec 2019 09:04:08 -0500 Received: from us-smtp-2.mimecast.com ([205.139.110.61]:44535 helo=us-smtp-delivery-1.mimecast.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1igqyk-0003w4-Ty for qemu-arm@nongnu.org; Mon, 16 Dec 2019 09:04:07 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1576505046; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=J4yj3ipSn03wddNlzO5ReaAlW0xImmllc7BWwVZtIu4=; b=GmSkT6+piM9hFNuV9f9tDD6sAKvK4gMPVi0B+vava7JOSErORkMp1TppqLccjV1mjzJuVB TdHqzj3nEmQpiLaDuBXdBfVTVy2aR+/8AERW1MgalYx7c58AKCAq+syo5+d3ib5auo4N4z Pi87qmXz4SA5r6mZ0X2UJW4EpejVomQ= Received: from mimecast-mx01.redhat.com (mimecast-mx01.redhat.com [209.132.183.4]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-298-AMQbqdvGO9uyh3GUAy7FKQ-1; Mon, 16 Dec 2019 09:04:05 -0500 X-MC-Unique: AMQbqdvGO9uyh3GUAy7FKQ-1 Received: from smtp.corp.redhat.com (int-mx05.intmail.prod.int.phx2.redhat.com [10.5.11.15]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx01.redhat.com (Postfix) with ESMTPS id 92B8B100728B; Mon, 16 Dec 2019 14:04:03 +0000 (UTC) Received: from laptop.redhat.com (ovpn-116-117.ams2.redhat.com [10.36.116.117]) by smtp.corp.redhat.com (Postfix) with ESMTP id 3D0E6675B8; Mon, 16 Dec 2019 14:03:58 +0000 (UTC) From: Eric Auger To: eric.auger.pro@gmail.com, eric.auger@redhat.com, maz@kernel.org, kvmarm@lists.cs.columbia.edu, kvm@vger.kernel.org, qemu-devel@nongnu.org, qemu-arm@nongnu.org Cc: drjones@redhat.com, andre.przywara@arm.com, peter.maydell@linaro.org, yuzenghui@huawei.com, alexandru.elisei@arm.com, thuth@redhat.com Subject: [kvm-unit-tests PATCH 07/16] arm/arm64: ITS: Set the LPI config and pending tables Date: Mon, 16 Dec 2019 15:02:26 +0100 Message-Id: <20191216140235.10751-8-eric.auger@redhat.com> In-Reply-To: <20191216140235.10751-1-eric.auger@redhat.com> References: <20191216140235.10751-1-eric.auger@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.79 on 10.5.11.15 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 205.139.110.61 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 16 Dec 2019 14:04:11 -0000 Allocate the LPI configuration and per re-distributor pending table. Set redistributor's PROPBASER and PENDBASER. The LPIs are enabled by default in the config table. Also introduce a helper routine that allows to set the pending table bit for a given LPI. Signed-off-by: Eric Auger --- lib/arm/asm/gic-v3-its.h | 3 ++ lib/arm/asm/gic-v3.h | 79 ++++++++++++++++++++++++++++++++++++++++ lib/arm/gic-v3-its.c | 65 +++++++++++++++++++++++++++++++++ 3 files changed, 147 insertions(+) diff --git a/lib/arm/asm/gic-v3-its.h b/lib/arm/asm/gic-v3-its.h index 0c0178d..0d11aed 100644 --- a/lib/arm/asm/gic-v3-its.h +++ b/lib/arm/asm/gic-v3-its.h @@ -128,6 +128,9 @@ extern void its_init(void); extern int its_parse_baser(int i, struct its_baser *baser); extern void its_setup_baser(int i, struct its_baser *baser); extern struct its_baser *its_lookup_baser(int type); +extern void set_lpi_config(int n, u8 val); +extern u8 get_lpi_config(int n); +extern void set_pending_table_bit(int rdist, int n, bool set); =20 #endif /* !__ASSEMBLY__ */ #endif /* _ASMARM_GIC_V3_ITS_H_ */ diff --git a/lib/arm/asm/gic-v3.h b/lib/arm/asm/gic-v3.h index d02f4a4..5bf9a92 100644 --- a/lib/arm/asm/gic-v3.h +++ b/lib/arm/asm/gic-v3.h @@ -47,6 +47,83 @@ #define MPIDR_TO_SGI_AFFINITY(cluster_id, level) \ (MPIDR_AFFINITY_LEVEL(cluster_id, level) << ICC_SGI1R_AFFINITY_## level= ## _SHIFT) =20 +#define GIC_BASER_CACHE_nCnB 0ULL +#define GIC_BASER_CACHE_SameAsInner 0ULL +#define GIC_BASER_CACHE_nC 1ULL +#define GIC_BASER_CACHE_RaWt 2ULL +#define GIC_BASER_CACHE_RaWb 3ULL +#define GIC_BASER_CACHE_WaWt 4ULL +#define GIC_BASER_CACHE_WaWb 5ULL +#define GIC_BASER_CACHE_RaWaWt 6ULL +#define GIC_BASER_CACHE_RaWaWb 7ULL +#define GIC_BASER_CACHE_MASK 7ULL +#define GIC_BASER_NonShareable 0ULL +#define GIC_BASER_InnerShareable 1ULL +#define GIC_BASER_OuterShareable 2ULL +#define GIC_BASER_SHAREABILITY_MASK 3ULL + +#define GIC_BASER_CACHEABILITY(reg, inner_outer, type) = \ + (GIC_BASER_CACHE_##type << reg##_##inner_outer##_CACHEABILITY_SHIFT) + +#define GIC_BASER_SHAREABILITY(reg, type) = \ + (GIC_BASER_##type << reg##_SHAREABILITY_SHIFT) + +#define GICR_PROPBASER_SHAREABILITY_SHIFT (10) +#define GICR_PROPBASER_INNER_CACHEABILITY_SHIFT (7) +#define GICR_PROPBASER_OUTER_CACHEABILITY_SHIFT (56) +#define GICR_PROPBASER_SHAREABILITY_MASK = \ + GIC_BASER_SHAREABILITY(GICR_PROPBASER, SHAREABILITY_MASK) +#define GICR_PROPBASER_INNER_CACHEABILITY_MASK = \ + GIC_BASER_CACHEABILITY(GICR_PROPBASER, INNER, MASK) +#define GICR_PROPBASER_OUTER_CACHEABILITY_MASK = \ + GIC_BASER_CACHEABILITY(GICR_PROPBASER, OUTER, MASK) +#define GICR_PROPBASER_CACHEABILITY_MASK GICR_PROPBASER_INNER_CACHEABILI= TY_MASK + +#define GICR_PROPBASER_InnerShareable = \ + GIC_BASER_SHAREABILITY(GICR_PROPBASER, InnerShareable) + +#define GICR_PROPBASER_nCnB GIC_BASER_CACHEABILITY(GICR_PROPBASER, I= NNER, nCnB) +#define GICR_PROPBASER_nC GIC_BASER_CACHEABILITY(GICR_PROPBASER, I= NNER, nC) +#define GICR_PROPBASER_RaWt GIC_BASER_CACHEABILITY(GICR_PROPBASER, I= NNER, RaWt) +#define GICR_PROPBASER_RaWb GIC_BASER_CACHEABILITY(GICR_PROPBASER, I= NNER, RaWt) +#define GICR_PROPBASER_WaWt GIC_BASER_CACHEABILITY(GICR_PROPBASER, I= NNER, WaWt) +#define GICR_PROPBASER_WaWb GIC_BASER_CACHEABILITY(GICR_PROPBASER, I= NNER, WaWb) +#define GICR_PROPBASER_RaWaWt GIC_BASER_CACHEABILITY(GICR_PROPBASER, I= NNER, RaWaWt) +#define GICR_PROPBASER_RaWaWb GIC_BASER_CACHEABILITY(GICR_PROPBASER, I= NNER, RaWaWb) + +#define GICR_PROPBASER_IDBITS_MASK (0x1f) + +#define GICR_PENDBASER_SHAREABILITY_SHIFT (10) +#define GICR_PENDBASER_INNER_CACHEABILITY_SHIFT (7) +#define GICR_PENDBASER_OUTER_CACHEABILITY_SHIFT (56) +#define GICR_PENDBASER_SHAREABILITY_MASK = \ + GIC_BASER_SHAREABILITY(GICR_PENDBASER, SHAREABILITY_MASK) +#define GICR_PENDBASER_INNER_CACHEABILITY_MASK = \ + GIC_BASER_CACHEABILITY(GICR_PENDBASER, INNER, MASK) +#define GICR_PENDBASER_OUTER_CACHEABILITY_MASK = \ + GIC_BASER_CACHEABILITY(GICR_PENDBASER, OUTER, MASK) +#define GICR_PENDBASER_CACHEABILITY_MASK GICR_PENDBASER_INNER_CACHEABILI= TY_MASK + +#define GICR_PENDBASER_InnerShareable = \ + GIC_BASER_SHAREABILITY(GICR_PENDBASER, InnerShareable) + +#define GICR_PENDBASER_nCnB GIC_BASER_CACHEABILITY(GICR_PENDBASER, I= NNER, nCnB) +#define GICR_PENDBASER_nC GIC_BASER_CACHEABILITY(GICR_PENDBASER, I= NNER, nC) +#define GICR_PENDBASER_RaWt GIC_BASER_CACHEABILITY(GICR_PENDBASER, I= NNER, RaWt) +#define GICR_PENDBASER_RaWb GIC_BASER_CACHEABILITY(GICR_PENDBASER, I= NNER, RaWt) +#define GICR_PENDBASER_WaWt GIC_BASER_CACHEABILITY(GICR_PENDBASER, I= NNER, WaWt) +#define GICR_PENDBASER_WaWb GIC_BASER_CACHEABILITY(GICR_PENDBASER, I= NNER, WaWb) +#define GICR_PENDBASER_RaWaWt GIC_BASER_CACHEABILITY(GICR_PENDBASER, I= NNER, RaWaWt) +#define GICR_PENDBASER_RaWaWb GIC_BASER_CACHEABILITY(GICR_PENDBASER, I= NNER, RaWaWb) + +#define GICR_PENDBASER_PTZ BIT_ULL(62) + +#define LPI_PROP_GROUP1 (1 << 1) +#define LPI_PROP_ENABLED (1 << 0) +#define LPI_PROP_DEFAULT_PRIO 0xa0 +#define LPI_PROP_DEFAULT (LPI_PROP_DEFAULT_PRIO | \ + LPI_PROP_GROUP1 | LPI_PROP_ENABLED) + #include =20 #ifndef __ASSEMBLY__ @@ -63,6 +140,8 @@ struct gicv3_data { void *dist_base; void *redist_bases[GICV3_NR_REDISTS]; void *redist_base[NR_CPUS]; + void *lpi_prop; + void *lpi_pend[NR_CPUS]; unsigned int irq_nr; }; extern struct gicv3_data gicv3_data; diff --git a/lib/arm/gic-v3-its.c b/lib/arm/gic-v3-its.c index 303022f..0b5a700 100644 --- a/lib/arm/gic-v3-its.c +++ b/lib/arm/gic-v3-its.c @@ -123,3 +123,68 @@ void its_setup_baser(int i, struct its_baser *baser) writeq(val, gicv3_its_base() + GITS_BASER + i * 8); } =20 +inline void set_lpi_config(int n, u8 value) +{ + u8 *entry =3D (u8 *)(gicv3_data.lpi_prop + (n - 8192)); + *entry =3D value; +} + +inline u8 get_lpi_config(int n) +{ + u8 *entry =3D (u8 *)(gicv3_data.lpi_prop + (n - 8192)); + return *entry; +} + +/* alloc_lpi_tables: Allocate LPI config and pending tables */ +void alloc_lpi_tables(void); +void alloc_lpi_tables(void) +{ + unsigned long n =3D SZ_64K >> PAGE_SHIFT; + unsigned long order =3D fls(n); + u64 prop_val; + int cpu; + + gicv3_data.lpi_prop =3D (void *)virt_to_phys(alloc_pages(order)); + + /* ID bits =3D 13, ie. up to 14b LPI INTID */ + prop_val =3D ((u64)gicv3_data.lpi_prop | + GICR_PROPBASER_InnerShareable | + GICR_PROPBASER_WaWb | + (13 & GICR_PROPBASER_IDBITS_MASK)); + + /* + * Allocate pending tables for each redistributor + * and set PROPBASER and PENDBASER + */ + for_each_present_cpu(cpu) { + u64 pend_val; + void *ptr; + + ptr =3D gicv3_data.redist_base[cpu]; + + writeq(prop_val, ptr + GICR_PROPBASER); + + gicv3_data.lpi_pend[cpu] =3D + (void *)virt_to_phys(alloc_pages(order)); + + pend_val =3D ((u64)gicv3_data.lpi_pend[cpu] | + GICR_PENDBASER_InnerShareable | + GICR_PENDBASER_WaWb); + + writeq(pend_val, ptr + GICR_PENDBASER); + } +} + +void set_pending_table_bit(int rdist, int n, bool set) +{ + u8 *ptr =3D phys_to_virt((phys_addr_t)gicv3_data.lpi_pend[rdist]); + u8 mask =3D 1 << (n % 8), byte; + + ptr +=3D (n / 8); + byte =3D *ptr; + if (set) + byte |=3D mask; + else + byte &=3D ~mask; + *ptr =3D byte; +} --=20 2.20.1 From MAILER-DAEMON Mon Dec 16 09:04:17 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1igqyv-0004PS-It for mharc-qemu-arm@gnu.org; Mon, 16 Dec 2019 09:04:17 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:58670) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1igqyt-0004KO-3E for qemu-arm@nongnu.org; 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Mon, 16 Dec 2019 09:04:12 -0500 X-MC-Unique: d9quq6-aOwC9kim1AWnO3A-1 Received: from smtp.corp.redhat.com (int-mx05.intmail.prod.int.phx2.redhat.com [10.5.11.15]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx01.redhat.com (Postfix) with ESMTPS id 85EBD1809A43; Mon, 16 Dec 2019 14:04:10 +0000 (UTC) Received: from laptop.redhat.com (ovpn-116-117.ams2.redhat.com [10.36.116.117]) by smtp.corp.redhat.com (Postfix) with ESMTP id 72116675B8; Mon, 16 Dec 2019 14:04:07 +0000 (UTC) From: Eric Auger To: eric.auger.pro@gmail.com, eric.auger@redhat.com, maz@kernel.org, kvmarm@lists.cs.columbia.edu, kvm@vger.kernel.org, qemu-devel@nongnu.org, qemu-arm@nongnu.org Cc: drjones@redhat.com, andre.przywara@arm.com, peter.maydell@linaro.org, yuzenghui@huawei.com, alexandru.elisei@arm.com, thuth@redhat.com Subject: [kvm-unit-tests PATCH 09/16] arm/arm64: ITS: Enable/Disable LPIs at re-distributor level Date: Mon, 16 Dec 2019 15:02:28 +0100 Message-Id: <20191216140235.10751-10-eric.auger@redhat.com> In-Reply-To: <20191216140235.10751-1-eric.auger@redhat.com> References: <20191216140235.10751-1-eric.auger@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.79 on 10.5.11.15 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 205.139.110.120 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 16 Dec 2019 14:04:17 -0000 This helper function enables or disables the signaling of LPIs at redistributor level. Signed-off-by: Eric Auger --- lib/arm/asm/gic-v3-its.h | 1 + lib/arm/gic-v3-its.c | 18 ++++++++++++++++++ 2 files changed, 19 insertions(+) diff --git a/lib/arm/asm/gic-v3-its.h b/lib/arm/asm/gic-v3-its.h index ed42707..d56a17f 100644 --- a/lib/arm/asm/gic-v3-its.h +++ b/lib/arm/asm/gic-v3-its.h @@ -138,6 +138,7 @@ extern struct its_baser *its_lookup_baser(int type); extern void set_lpi_config(int n, u8 val); extern u8 get_lpi_config(int n); extern void set_pending_table_bit(int rdist, int n, bool set); +extern void gicv3_rdist_ctrl_lpi(u32 redist, bool set); =20 #endif /* !__ASSEMBLY__ */ #endif /* _ASMARM_GIC_V3_ITS_H_ */ diff --git a/lib/arm/gic-v3-its.c b/lib/arm/gic-v3-its.c index 8b6a095..b0f7714 100644 --- a/lib/arm/gic-v3-its.c +++ b/lib/arm/gic-v3-its.c @@ -225,3 +225,21 @@ void init_cmd_queue(void) writeq(0, its_data.base + GITS_CWRITER); writeq(0, its_data.base + GITS_CREADR); } + +void gicv3_rdist_ctrl_lpi(u32 redist, bool set) +{ + void *ptr; + u64 val; + + if (redist >=3D nr_cpus) + report_abort("%s redist=3D%d >=3D cpu_count=3D%d\n", + __func__, redist, nr_cpus); + + ptr =3D gicv3_data.redist_base[redist]; + val =3D readl(ptr + GICR_CTLR); + if (set) + val |=3D GICR_CTLR_ENABLE_LPIS; + else + val &=3D ~GICR_CTLR_ENABLE_LPIS; + writel(val, ptr + GICR_CTLR); +} --=20 2.20.1 From MAILER-DAEMON Mon Dec 16 09:04:18 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1igqyv-0004Q2-T6 for mharc-qemu-arm@gnu.org; Mon, 16 Dec 2019 09:04:17 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:58668) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1igqys-0004Jv-PS for qemu-arm@nongnu.org; Mon, 16 Dec 2019 09:04:15 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1igqyr-0003xq-Hc for qemu-arm@nongnu.org; Mon, 16 Dec 2019 09:04:14 -0500 Received: from us-smtp-delivery-1.mimecast.com ([205.139.110.120]:32346 helo=us-smtp-1.mimecast.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1igqyr-0003xc-Di for qemu-arm@nongnu.org; Mon, 16 Dec 2019 09:04:13 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1576505052; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=go7p3wwISfVA0pTnz3FCaoN35+Sj/LsY9kHumr5FQBc=; b=NngFZxQTzCi0dy/V0rHpIqF4ivGvco6IoqTDiD4sdmSYHDAvyxXBcCi0tmQ7LCpESO283N ynhLF+KCwDZ9WhXsSfMzY+B28IH4PDMUvHVoINsL66qVLKYzdUZgkVnrh1nHkKyPDW/Y8M CL2AWeEQ92zp3vv95hvMBH0t+0Z2LbI= Received: from mimecast-mx01.redhat.com (mimecast-mx01.redhat.com [209.132.183.4]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-218-rtoyeNZEPGCPQmzAG2EvCg-1; Mon, 16 Dec 2019 09:04:08 -0500 X-MC-Unique: rtoyeNZEPGCPQmzAG2EvCg-1 Received: from smtp.corp.redhat.com (int-mx05.intmail.prod.int.phx2.redhat.com [10.5.11.15]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx01.redhat.com (Postfix) with ESMTPS id 199D38024E6; Mon, 16 Dec 2019 14:04:07 +0000 (UTC) Received: from laptop.redhat.com (ovpn-116-117.ams2.redhat.com [10.36.116.117]) by smtp.corp.redhat.com (Postfix) with ESMTP id F0B68675B8; Mon, 16 Dec 2019 14:04:03 +0000 (UTC) From: Eric Auger To: eric.auger.pro@gmail.com, eric.auger@redhat.com, maz@kernel.org, kvmarm@lists.cs.columbia.edu, kvm@vger.kernel.org, qemu-devel@nongnu.org, qemu-arm@nongnu.org Cc: drjones@redhat.com, andre.przywara@arm.com, peter.maydell@linaro.org, yuzenghui@huawei.com, alexandru.elisei@arm.com, thuth@redhat.com Subject: [kvm-unit-tests PATCH 08/16] arm/arm64: ITS: Init the command queue Date: Mon, 16 Dec 2019 15:02:27 +0100 Message-Id: <20191216140235.10751-9-eric.auger@redhat.com> In-Reply-To: <20191216140235.10751-1-eric.auger@redhat.com> References: <20191216140235.10751-1-eric.auger@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.79 on 10.5.11.15 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 205.139.110.120 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 16 Dec 2019 14:04:16 -0000 Allocate the command queue and initialize related registers: CBASER, CREADR, CWRITER. The command queue is 64kB. This aims at not bothing with fullness. Signed-off-by: Eric Auger --- lib/arm/asm/gic-v3-its.h | 7 +++++++ lib/arm/gic-v3-its.c | 37 +++++++++++++++++++++++++++++++++++++ 2 files changed, 44 insertions(+) diff --git a/lib/arm/asm/gic-v3-its.h b/lib/arm/asm/gic-v3-its.h index 0d11aed..ed42707 100644 --- a/lib/arm/asm/gic-v3-its.h +++ b/lib/arm/asm/gic-v3-its.h @@ -113,10 +113,17 @@ struct its_baser { int esz; }; =20 +struct its_cmd_block { + u64 raw_cmd[4]; +}; + struct its_data { void *base; struct its_typer typer; struct its_baser baser[GITS_BASER_NR_REGS]; + struct its_cmd_block *cmd_base; + struct its_cmd_block *cmd_write; + struct its_cmd_block *cmd_readr; }; =20 extern struct its_data its_data; diff --git a/lib/arm/gic-v3-its.c b/lib/arm/gic-v3-its.c index 0b5a700..8b6a095 100644 --- a/lib/arm/gic-v3-its.c +++ b/lib/arm/gic-v3-its.c @@ -188,3 +188,40 @@ void set_pending_table_bit(int rdist, int n, bool se= t) byte &=3D ~mask; *ptr =3D byte; } + +/** + * init_cmd_queue: Allocate the command queue and initialize + * CBASER, CREADR, CWRITER + */ +void init_cmd_queue(void); +void init_cmd_queue(void) +{ + unsigned long n =3D SZ_64K >> PAGE_SHIFT; + unsigned long order =3D fls(n); + u64 cbaser, tmp; + + its_data.cmd_base =3D (void *)virt_to_phys(alloc_pages(order)); + + cbaser =3D ((u64)its_data.cmd_base | + GITS_CBASER_WaWb | + GITS_CBASER_InnerShareable | + (SZ_64K / SZ_4K - 1) | + GITS_CBASER_VALID); + + writeq(cbaser, its_data.base + GITS_CBASER); + tmp =3D readq(its_data.base + GITS_CBASER); + + if ((tmp ^ cbaser) & GITS_CBASER_SHAREABILITY_MASK) { + if (!(tmp & GITS_CBASER_SHAREABILITY_MASK)) { + cbaser &=3D ~(GITS_CBASER_SHAREABILITY_MASK | + GITS_CBASER_CACHEABILITY_MASK); + cbaser |=3D GITS_CBASER_nC; + writeq(cbaser, its_data.base + GITS_CBASER); + } + } + + its_data.cmd_write =3D its_data.cmd_base; + its_data.cmd_readr =3D its_data.cmd_base; + writeq(0, its_data.base + GITS_CWRITER); + writeq(0, its_data.base + GITS_CREADR); +} --=20 2.20.1 From MAILER-DAEMON Mon Dec 16 09:04:22 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1igqz0-0004Xj-AT for mharc-qemu-arm@gnu.org; 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b=hgnAcgRXM2x3rXdv1lny5QtNERSCTW4JomaBDwgMUcmZYYD6KAhXO32H0Cyq3AqHGD1k9y Y2HTT5zw3ijzFirAP/6B7yyQRwc7bxK1W++wqGnrUCa33/oZ+wfT54PazBRggT5BracnEB 1wGsRbz1bZ+1/s/hge8tJ3qTCRYzXas= Received: from mimecast-mx01.redhat.com (mimecast-mx01.redhat.com [209.132.183.4]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-163-LL_HqoBOP4e465DgIlVopg-1; Mon, 16 Dec 2019 09:04:15 -0500 X-MC-Unique: LL_HqoBOP4e465DgIlVopg-1 Received: from smtp.corp.redhat.com (int-mx05.intmail.prod.int.phx2.redhat.com [10.5.11.15]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx01.redhat.com (Postfix) with ESMTPS id CE9591809A54; Mon, 16 Dec 2019 14:04:13 +0000 (UTC) Received: from laptop.redhat.com (ovpn-116-117.ams2.redhat.com [10.36.116.117]) by smtp.corp.redhat.com (Postfix) with ESMTP id E0512675B8; Mon, 16 Dec 2019 14:04:10 +0000 (UTC) From: Eric Auger To: eric.auger.pro@gmail.com, eric.auger@redhat.com, maz@kernel.org, kvmarm@lists.cs.columbia.edu, kvm@vger.kernel.org, qemu-devel@nongnu.org, qemu-arm@nongnu.org Cc: drjones@redhat.com, andre.przywara@arm.com, peter.maydell@linaro.org, yuzenghui@huawei.com, alexandru.elisei@arm.com, thuth@redhat.com Subject: [kvm-unit-tests PATCH 10/16] arm/arm64: ITS: its_enable_defaults Date: Mon, 16 Dec 2019 15:02:29 +0100 Message-Id: <20191216140235.10751-11-eric.auger@redhat.com> In-Reply-To: <20191216140235.10751-1-eric.auger@redhat.com> References: <20191216140235.10751-1-eric.auger@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.79 on 10.5.11.15 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 207.211.31.81 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 16 Dec 2019 14:04:21 -0000 its_enable_defaults() is the top init function that allocates all the requested tables (device, collection, lpi config and pending tables), enable LPIs at distributor level and ITS level. gicv3_enable_defaults must be called before. Signed-off-by: Eric Auger --- lib/arm/asm/gic-v3-its.h | 1 + lib/arm/gic-v3-its.c | 41 ++++++++++++++++++++++++++++++++++++++++ 2 files changed, 42 insertions(+) diff --git a/lib/arm/asm/gic-v3-its.h b/lib/arm/asm/gic-v3-its.h index d56a17f..ab639c5 100644 --- a/lib/arm/asm/gic-v3-its.h +++ b/lib/arm/asm/gic-v3-its.h @@ -139,6 +139,7 @@ extern void set_lpi_config(int n, u8 val); extern u8 get_lpi_config(int n); extern void set_pending_table_bit(int rdist, int n, bool set); extern void gicv3_rdist_ctrl_lpi(u32 redist, bool set); +extern void its_enable_defaults(void); =20 #endif /* !__ASSEMBLY__ */ #endif /* _ASMARM_GIC_V3_ITS_H_ */ diff --git a/lib/arm/gic-v3-its.c b/lib/arm/gic-v3-its.c index b0f7714..9a51ef4 100644 --- a/lib/arm/gic-v3-its.c +++ b/lib/arm/gic-v3-its.c @@ -243,3 +243,44 @@ void gicv3_rdist_ctrl_lpi(u32 redist, bool set) val &=3D ~GICR_CTLR_ENABLE_LPIS; writel(val, ptr + GICR_CTLR); } + +void its_enable_defaults(void) +{ + unsigned int i; + + its_parse_typer(); + + /* Allocate BASER tables (device and collection tables) */ + for (i =3D 0; i < GITS_BASER_NR_REGS; i++) { + struct its_baser *baser =3D &its_data.baser[i]; + int ret; + + ret =3D its_parse_baser(i, baser); + if (ret) + continue; + + switch (baser->type) { + case GITS_BASER_TYPE_DEVICE: + baser->valid =3D true; + baser->cache =3D GITS_BASER_nCnB; + its_setup_baser(i, baser); + break; + case GITS_BASER_TYPE_COLLECTION: + baser->valid =3D true; + its_setup_baser(i, baser); + break; + default: + break; + } + } + + /* Allocate LPI config and pending tables */ + alloc_lpi_tables(); + + init_cmd_queue(); + + for (i =3D 0; i < nr_cpus; i++) + gicv3_rdist_ctrl_lpi(i, true); + + writel(GITS_CTLR_ENABLE, its_data.base + GITS_CTLR); +} --=20 2.20.1 From MAILER-DAEMON Mon Dec 16 09:04:33 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1igqzB-0004m4-5Q for mharc-qemu-arm@gnu.org; Mon, 16 Dec 2019 09:04:33 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:58728) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1igqz7-0004iO-Fh for qemu-arm@nongnu.org; Mon, 16 Dec 2019 09:04:31 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1igqz5-00040b-Ag for qemu-arm@nongnu.org; Mon, 16 Dec 2019 09:04:29 -0500 Received: from us-smtp-delivery-1.mimecast.com ([207.211.31.120]:33036 helo=us-smtp-1.mimecast.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1igqz5-00040R-5L for qemu-arm@nongnu.org; Mon, 16 Dec 2019 09:04:27 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1576505066; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=yx4TrBtKa5gCrkDJ9TaxepAB0mA02b3GX1DebNUYwxc=; b=F85/yixp4AlCP9Qf5HjiaLrCGL1r0Qr/duoBHkH+N4xbSjwHvA2igVSPJtLBxBuyAxwd+Z 25yXvUSG7ExFpLpM35GVSQB4Acj5nBf5AF2EoGwBMa5ngmKsk1ZmybYHLuZ5+kpDf1j1Uc ZbsYeb0gkhxFcVltPqkAKEtoHP8wCIA= Received: from mimecast-mx01.redhat.com (mimecast-mx01.redhat.com [209.132.183.4]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-115-xTdKyRLgN7m_2uvOSnha0w-1; Mon, 16 Dec 2019 09:04:24 -0500 X-MC-Unique: xTdKyRLgN7m_2uvOSnha0w-1 Received: from smtp.corp.redhat.com (int-mx05.intmail.prod.int.phx2.redhat.com [10.5.11.15]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx01.redhat.com (Postfix) with ESMTPS id C497D80258B; Mon, 16 Dec 2019 14:04:22 +0000 (UTC) Received: from laptop.redhat.com (ovpn-116-117.ams2.redhat.com [10.36.116.117]) by smtp.corp.redhat.com (Postfix) with ESMTP id 81C68675BF; Mon, 16 Dec 2019 14:04:17 +0000 (UTC) From: Eric Auger To: eric.auger.pro@gmail.com, eric.auger@redhat.com, maz@kernel.org, kvmarm@lists.cs.columbia.edu, kvm@vger.kernel.org, qemu-devel@nongnu.org, qemu-arm@nongnu.org Cc: drjones@redhat.com, andre.przywara@arm.com, peter.maydell@linaro.org, yuzenghui@huawei.com, alexandru.elisei@arm.com, thuth@redhat.com Subject: [kvm-unit-tests PATCH 12/16] arm/arm64: ITS: commands Date: Mon, 16 Dec 2019 15:02:31 +0100 Message-Id: <20191216140235.10751-13-eric.auger@redhat.com> In-Reply-To: <20191216140235.10751-1-eric.auger@redhat.com> References: <20191216140235.10751-1-eric.auger@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.79 on 10.5.11.15 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 207.211.31.120 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 16 Dec 2019 14:04:32 -0000 Implement main ITS commands. The code is largely inherited from the ITS driver. Signed-off-by: Eric Auger --- arm/Makefile.common | 2 +- lib/arm/asm/gic-v3-its.h | 36 +++ lib/arm/gic-v3-its-cmd.c | 462 +++++++++++++++++++++++++++++++++++++++ 3 files changed, 499 insertions(+), 1 deletion(-) create mode 100644 lib/arm/gic-v3-its-cmd.c diff --git a/arm/Makefile.common b/arm/Makefile.common index 1aae5a3..7cc0f04 100644 --- a/arm/Makefile.common +++ b/arm/Makefile.common @@ -52,7 +52,7 @@ cflatobjs +=3D lib/arm/psci.o cflatobjs +=3D lib/arm/smp.o cflatobjs +=3D lib/arm/delay.o cflatobjs +=3D lib/arm/gic.o lib/arm/gic-v2.o lib/arm/gic-v3.o -cflatobjs +=3D lib/arm/gic-v3-its.o +cflatobjs +=3D lib/arm/gic-v3-its.o lib/arm/gic-v3-its-cmd.o =20 OBJDIRS +=3D lib/arm =20 diff --git a/lib/arm/asm/gic-v3-its.h b/lib/arm/asm/gic-v3-its.h index 245ef61..d074c17 100644 --- a/lib/arm/asm/gic-v3-its.h +++ b/lib/arm/asm/gic-v3-its.h @@ -90,6 +90,24 @@ #define GITS_MAX_DEVICES 8 #define GITS_MAX_COLLECTIONS 8 =20 +/* + * ITS commands + */ +#define GITS_CMD_MAPD 0x08 +#define GITS_CMD_MAPC 0x09 +#define GITS_CMD_MAPTI 0x0a +/* older GIC documentation used MAPVI for this command */ +#define GITS_CMD_MAPVI GITS_CMD_MAPTI +#define GITS_CMD_MAPI 0x0b +#define GITS_CMD_MOVI 0x01 +#define GITS_CMD_DISCARD 0x0f +#define GITS_CMD_INV 0x0c +#define GITS_CMD_MOVALL 0x0e +#define GITS_CMD_INVALL 0x0d +#define GITS_CMD_INT 0x03 +#define GITS_CMD_CLEAR 0x04 +#define GITS_CMD_SYNC 0x05 + struct its_typer { unsigned int ite_size; unsigned int eventid_bits; @@ -161,5 +179,23 @@ extern void its_enable_defaults(void); extern struct its_device *its_create_device(u32 dev_id, int nr_ites); extern struct its_collection *its_create_collection(u32 col_id, u32 targ= et_pe); =20 +extern void its_send_mapd(struct its_device *dev, int valid); +extern void its_send_mapc(struct its_collection *col, int valid); +extern void its_send_mapti(struct its_device *dev, u32 irq_id, + u32 event_id, struct its_collection *col); +extern void its_send_int(struct its_device *dev, u32 event_id); +extern void its_send_inv(struct its_device *dev, u32 event_id); +extern void its_send_discard(struct its_device *dev, u32 event_id); +extern void its_send_clear(struct its_device *dev, u32 event_id); +extern void its_send_invall(struct its_collection *col); +extern void its_send_movi(struct its_device *dev, + struct its_collection *col, u32 id); +extern void its_send_sync(struct its_collection *col); +extern void its_print_cmd_state(void); + +#define ITS_FLAGS_CMDQ_NEEDS_FLUSHING (1ULL << 0) +#define ITS_FLAGS_WORKAROUND_CAVIUM_22375 (1ULL << 1) +#define ITS_FLAGS_WORKAROUND_CAVIUM_23144 (1ULL << 2) + #endif /* !__ASSEMBLY__ */ #endif /* _ASMARM_GIC_V3_ITS_H_ */ diff --git a/lib/arm/gic-v3-its-cmd.c b/lib/arm/gic-v3-its-cmd.c new file mode 100644 index 0000000..4c326cd --- /dev/null +++ b/lib/arm/gic-v3-its-cmd.c @@ -0,0 +1,462 @@ +/* + * Copyright (C) 2016, Red Hat Inc, Eric Auger + * + * Most of the code is copy-pasted from: + * drivers/irqchip/irq-gic-v3-its.c + * This work is licensed under the terms of the GNU LGPL, version 2. + */ +#include +#include + +#define ITS_ITT_ALIGN SZ_256 + +static const char * const its_cmd_string[] =3D { + [GITS_CMD_MAPD] =3D "MAPD", + [GITS_CMD_MAPC] =3D "MAPC", + [GITS_CMD_MAPTI] =3D "MAPTI", + [GITS_CMD_MAPI] =3D "MAPI", + [GITS_CMD_MOVI] =3D "MOVI", + [GITS_CMD_DISCARD] =3D "DISCARD", + [GITS_CMD_INV] =3D "INV", + [GITS_CMD_MOVALL] =3D "MOVALL", + [GITS_CMD_INVALL] =3D "INVALL", + [GITS_CMD_INT] =3D "INT", + [GITS_CMD_CLEAR] =3D "CLEAR", + [GITS_CMD_SYNC] =3D "SYNC", +}; + +struct its_cmd_desc { + union { + struct { + struct its_device *dev; + u32 event_id; + } its_inv_cmd; + + struct { + struct its_device *dev; + u32 event_id; + } its_int_cmd; + + struct { + struct its_device *dev; + bool valid; + } its_mapd_cmd; + + struct { + struct its_collection *col; + bool valid; + } its_mapc_cmd; + + struct { + struct its_device *dev; + u32 phys_id; + u32 event_id; + u32 col_id; + } its_mapti_cmd; + + struct { + struct its_device *dev; + struct its_collection *col; + u32 event_id; + } its_movi_cmd; + + struct { + struct its_device *dev; + u32 event_id; + } its_discard_cmd; + + struct { + struct its_device *dev; + u32 event_id; + } its_clear_cmd; + + struct { + struct its_collection *col; + } its_invall_cmd; + + struct { + struct its_collection *col; + } its_sync_cmd; + }; +}; + +typedef void (*its_cmd_builder_t)(struct its_cmd_block *, + struct its_cmd_desc *); + +/* ITS COMMANDS */ + +static void its_encode_cmd(struct its_cmd_block *cmd, u8 cmd_nr) +{ + cmd->raw_cmd[0] &=3D ~0xffUL; + cmd->raw_cmd[0] |=3D cmd_nr; +} + +static void its_encode_devid(struct its_cmd_block *cmd, u32 devid) +{ + cmd->raw_cmd[0] &=3D BIT_ULL(32) - 1; + cmd->raw_cmd[0] |=3D ((u64)devid) << 32; +} + +static void its_encode_event_id(struct its_cmd_block *cmd, u32 id) +{ + cmd->raw_cmd[1] &=3D ~0xffffffffUL; + cmd->raw_cmd[1] |=3D id; +} + +static void its_encode_phys_id(struct its_cmd_block *cmd, u32 phys_id) +{ + cmd->raw_cmd[1] &=3D 0xffffffffUL; + cmd->raw_cmd[1] |=3D ((u64)phys_id) << 32; +} + +static void its_encode_size(struct its_cmd_block *cmd, u8 size) +{ + cmd->raw_cmd[1] &=3D ~0x1fUL; + cmd->raw_cmd[1] |=3D size & 0x1f; +} + +static void its_encode_itt(struct its_cmd_block *cmd, u64 itt_addr) +{ + cmd->raw_cmd[2] &=3D ~0xffffffffffffUL; + cmd->raw_cmd[2] |=3D itt_addr & 0xffffffffff00UL; +} + +static void its_encode_valid(struct its_cmd_block *cmd, int valid) +{ + cmd->raw_cmd[2] &=3D ~(1UL << 63); + cmd->raw_cmd[2] |=3D ((u64)!!valid) << 63; +} + +static void its_encode_target(struct its_cmd_block *cmd, u64 target_addr= ) +{ + cmd->raw_cmd[2] &=3D ~(0xfffffffffUL << 16); + cmd->raw_cmd[2] |=3D (target_addr & (0xffffffffUL << 16)); +} + +static void its_encode_collection(struct its_cmd_block *cmd, u16 col) +{ + cmd->raw_cmd[2] &=3D ~0xffffUL; + cmd->raw_cmd[2] |=3D col; +} + +static inline void its_fixup_cmd(struct its_cmd_block *cmd) +{ + /* Let's fixup BE commands */ + cmd->raw_cmd[0] =3D cpu_to_le64(cmd->raw_cmd[0]); + cmd->raw_cmd[1] =3D cpu_to_le64(cmd->raw_cmd[1]); + cmd->raw_cmd[2] =3D cpu_to_le64(cmd->raw_cmd[2]); + cmd->raw_cmd[3] =3D cpu_to_le64(cmd->raw_cmd[3]); +} + +static u64 its_cmd_ptr_to_offset(struct its_cmd_block *ptr) +{ + return (ptr - its_data.cmd_base) * sizeof(*ptr); +} + +static struct its_cmd_block *its_post_commands(void) +{ + u64 wr =3D its_cmd_ptr_to_offset(its_data.cmd_write); + + writeq(wr, its_data.base + GITS_CWRITER); + return its_data.cmd_write; +} + + +/* We just assume the queue is large enough */ +static struct its_cmd_block *its_allocate_entry(void) +{ + struct its_cmd_block *cmd; + + cmd =3D its_data.cmd_write++; + return cmd; +} + +static void its_wait_for_range_completion(struct its_cmd_block *from, + struct its_cmd_block *to) +{ + u64 rd_idx, from_idx, to_idx; + u32 count =3D 1000000; /* 1s! */ + + from_idx =3D its_cmd_ptr_to_offset(from); + to_idx =3D its_cmd_ptr_to_offset(to); + while (1) { + rd_idx =3D readq(its_data.base + GITS_CREADR); + if (rd_idx >=3D to_idx || rd_idx < from_idx) + break; + + count--; + if (!count) { + unsigned int cmd_id =3D from->raw_cmd[0] & 0xFF; + + report(false, "%s timeout!", + cmd_id <=3D 0xF ? its_cmd_string[cmd_id] : + "Unexpected"); + return; + } + cpu_relax(); + udelay(1); + } +} + +void its_print_cmd_state(void) +{ + u64 rd, wr; + + rd =3D readq(its_data.base + GITS_CREADR); + wr =3D readq(its_data.base + GITS_CWRITER); + report_info("GITS_CREADR=3D0x%lx GITS_CWRITER=3D0x%lx", rd, wr); +} + +static void its_send_single_command(its_cmd_builder_t builder, + struct its_cmd_desc *desc) +{ + struct its_cmd_block *cmd, *next_cmd; + + cmd =3D its_allocate_entry(); + builder(cmd, desc); + next_cmd =3D its_post_commands(); + + its_wait_for_range_completion(cmd, next_cmd); +} + + +static void its_build_mapd_cmd(struct its_cmd_block *cmd, + struct its_cmd_desc *desc) +{ + unsigned long itt_addr; + u8 size =3D 12; //TODO ilog2(desc->its_mapd_cmd.dev->nr_ites); + + itt_addr =3D (unsigned long)desc->its_mapd_cmd.dev->itt; + itt_addr =3D ALIGN(itt_addr, ITS_ITT_ALIGN); + + its_encode_cmd(cmd, GITS_CMD_MAPD); + its_encode_devid(cmd, desc->its_mapd_cmd.dev->device_id); + its_encode_size(cmd, size - 1); + its_encode_itt(cmd, itt_addr); + its_encode_valid(cmd, desc->its_mapd_cmd.valid); + + its_fixup_cmd(cmd); + report_info("MAPD devid=3D%d size =3D 0x%x itt=3D0x%lx valid=3D%d", + desc->its_mapd_cmd.dev->device_id, + size, itt_addr, desc->its_mapd_cmd.valid); + +} + +static void its_build_mapc_cmd(struct its_cmd_block *cmd, + struct its_cmd_desc *desc) +{ + its_encode_cmd(cmd, GITS_CMD_MAPC); + its_encode_collection(cmd, desc->its_mapc_cmd.col->col_id); + its_encode_target(cmd, desc->its_mapc_cmd.col->target_address); + its_encode_valid(cmd, desc->its_mapc_cmd.valid); + + its_fixup_cmd(cmd); + report_info("MAPC col_id=3D%d target_addr =3D 0x%lx valid=3D%d", + desc->its_mapc_cmd.col->col_id, + desc->its_mapc_cmd.col->target_address, + desc->its_mapc_cmd.valid); +} + +static void its_build_mapti_cmd(struct its_cmd_block *cmd, + struct its_cmd_desc *desc) +{ + its_encode_cmd(cmd, GITS_CMD_MAPTI); + its_encode_devid(cmd, desc->its_mapti_cmd.dev->device_id); + its_encode_event_id(cmd, desc->its_mapti_cmd.event_id); + its_encode_phys_id(cmd, desc->its_mapti_cmd.phys_id); + its_encode_collection(cmd, desc->its_mapti_cmd.col_id); + + its_fixup_cmd(cmd); + report_info("MAPTI dev_id=3D%d event_id=3D%d -> phys_id=3D%d, col_id=3D= %d", + desc->its_mapti_cmd.dev->device_id, + desc->its_mapti_cmd.event_id, + desc->its_mapti_cmd.phys_id, + desc->its_mapti_cmd.col_id); +} + +static void its_build_invall_cmd(struct its_cmd_block *cmd, + struct its_cmd_desc *desc) +{ + its_encode_cmd(cmd, GITS_CMD_INVALL); + its_encode_collection(cmd, desc->its_invall_cmd.col->col_id); + + its_fixup_cmd(cmd); + report_info("INVALL col_id=3D%d", desc->its_invall_cmd.col->col_id); +} + +static void its_build_clear_cmd(struct its_cmd_block *cmd, + struct its_cmd_desc *desc) +{ + its_encode_cmd(cmd, GITS_CMD_CLEAR); + its_encode_devid(cmd, desc->its_clear_cmd.dev->device_id); + its_encode_event_id(cmd, desc->its_clear_cmd.event_id); + + its_fixup_cmd(cmd); + report_info("CLEAR col_id=3D%d", desc->its_invall_cmd.col->col_id); +} + +static void its_build_discard_cmd(struct its_cmd_block *cmd, + struct its_cmd_desc *desc) +{ + its_encode_cmd(cmd, GITS_CMD_DISCARD); + its_encode_devid(cmd, desc->its_discard_cmd.dev->device_id); + its_encode_event_id(cmd, desc->its_discard_cmd.event_id); + + its_fixup_cmd(cmd); + report_info("DISCARD col_id=3D%d", desc->its_invall_cmd.col->col_id); +} + +static void its_build_inv_cmd(struct its_cmd_block *cmd, + struct its_cmd_desc *desc) +{ + its_encode_cmd(cmd, GITS_CMD_INV); + its_encode_devid(cmd, desc->its_inv_cmd.dev->device_id); + its_encode_event_id(cmd, desc->its_inv_cmd.event_id); + + its_fixup_cmd(cmd); + report_info("INV dev_id=3D%d event_id=3D%d", + desc->its_inv_cmd.dev->device_id, + desc->its_inv_cmd.event_id); +} + +static void its_build_int_cmd(struct its_cmd_block *cmd, + struct its_cmd_desc *desc) +{ + its_encode_cmd(cmd, GITS_CMD_INT); + its_encode_devid(cmd, desc->its_int_cmd.dev->device_id); + its_encode_event_id(cmd, desc->its_int_cmd.event_id); + + its_fixup_cmd(cmd); + report_info("INT dev_id=3D%d event_id=3D%d", + desc->its_int_cmd.dev->device_id, + desc->its_int_cmd.event_id); +} + +static void its_build_sync_cmd(struct its_cmd_block *cmd, + struct its_cmd_desc *desc) +{ + its_encode_cmd(cmd, GITS_CMD_SYNC); + its_encode_target(cmd, desc->its_sync_cmd.col->target_address); + its_fixup_cmd(cmd); + report_info("SYNC target_addr =3D 0x%lx", + desc->its_sync_cmd.col->target_address); +} + +static void its_build_movi_cmd(struct its_cmd_block *cmd, + struct its_cmd_desc *desc) +{ + its_encode_cmd(cmd, GITS_CMD_MOVI); + its_encode_devid(cmd, desc->its_movi_cmd.dev->device_id); + its_encode_event_id(cmd, desc->its_movi_cmd.event_id); + its_encode_collection(cmd, desc->its_movi_cmd.col->col_id); + + its_fixup_cmd(cmd); + report_info("MOVI dev_id=3D%d event_id =3D %d col_id=3D%d", + desc->its_movi_cmd.dev->device_id, + desc->its_movi_cmd.event_id, + desc->its_movi_cmd.col->col_id); +} + +void its_send_mapd(struct its_device *dev, int valid) +{ + struct its_cmd_desc desc; + + desc.its_mapd_cmd.dev =3D dev; + desc.its_mapd_cmd.valid =3D !!valid; + + its_send_single_command(its_build_mapd_cmd, &desc); +} + +void its_send_mapc(struct its_collection *col, int valid) +{ + struct its_cmd_desc desc; + + desc.its_mapc_cmd.col =3D col; + desc.its_mapc_cmd.valid =3D !!valid; + + its_send_single_command(its_build_mapc_cmd, &desc); +} + +void its_send_mapti(struct its_device *dev, u32 irq_id, + u32 event_id, struct its_collection *col) +{ + struct its_cmd_desc desc; + + desc.its_mapti_cmd.dev =3D dev; + desc.its_mapti_cmd.phys_id =3D irq_id; + desc.its_mapti_cmd.event_id =3D event_id; + desc.its_mapti_cmd.col_id =3D col->col_id; + + its_send_single_command(its_build_mapti_cmd, &desc); +} + +void its_send_int(struct its_device *dev, u32 event_id) +{ + struct its_cmd_desc desc; + + desc.its_int_cmd.dev =3D dev; + desc.its_int_cmd.event_id =3D event_id; + + its_send_single_command(its_build_int_cmd, &desc); +} + +void its_send_movi(struct its_device *dev, + struct its_collection *col, u32 id) +{ + struct its_cmd_desc desc; + + desc.its_movi_cmd.dev =3D dev; + desc.its_movi_cmd.col =3D col; + desc.its_movi_cmd.event_id =3D id; + + its_send_single_command(its_build_movi_cmd, &desc); +} + +void its_send_invall(struct its_collection *col) +{ + struct its_cmd_desc desc; + + desc.its_invall_cmd.col =3D col; + + its_send_single_command(its_build_invall_cmd, &desc); +} + +void its_send_inv(struct its_device *dev, u32 event_id) +{ + struct its_cmd_desc desc; + + desc.its_inv_cmd.dev =3D dev; + desc.its_inv_cmd.event_id =3D event_id; + + its_send_single_command(its_build_inv_cmd, &desc); +} + +void its_send_discard(struct its_device *dev, u32 event_id) +{ + struct its_cmd_desc desc; + + desc.its_discard_cmd.dev =3D dev; + desc.its_discard_cmd.event_id =3D event_id; + + its_send_single_command(its_build_discard_cmd, &desc); +} + +void its_send_clear(struct its_device *dev, u32 event_id) +{ + struct its_cmd_desc desc; + + desc.its_clear_cmd.dev =3D dev; + desc.its_clear_cmd.event_id =3D event_id; + + its_send_single_command(its_build_clear_cmd, &desc); +} + +void its_send_sync(struct its_collection *col) +{ + struct its_cmd_desc desc; + + desc.its_sync_cmd.col =3D col; + + its_send_single_command(its_build_sync_cmd, &desc); +} + --=20 2.20.1 From MAILER-DAEMON Mon Dec 16 09:04:37 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1igqzF-0004s3-A0 for mharc-qemu-arm@gnu.org; Mon, 16 Dec 2019 09:04:37 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:58754) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1igqzA-0004lb-IX for qemu-arm@nongnu.org; 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Mon, 16 Dec 2019 09:04:27 -0500 X-MC-Unique: n_HoM9aQPTiBfhJ9ttW-PQ-1 Received: from smtp.corp.redhat.com (int-mx05.intmail.prod.int.phx2.redhat.com [10.5.11.15]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx01.redhat.com (Postfix) with ESMTPS id 2BCF41854351; Mon, 16 Dec 2019 14:04:26 +0000 (UTC) Received: from laptop.redhat.com (ovpn-116-117.ams2.redhat.com [10.36.116.117]) by smtp.corp.redhat.com (Postfix) with ESMTP id 26470675B9; Mon, 16 Dec 2019 14:04:22 +0000 (UTC) From: Eric Auger To: eric.auger.pro@gmail.com, eric.auger@redhat.com, maz@kernel.org, kvmarm@lists.cs.columbia.edu, kvm@vger.kernel.org, qemu-devel@nongnu.org, qemu-arm@nongnu.org Cc: drjones@redhat.com, andre.przywara@arm.com, peter.maydell@linaro.org, yuzenghui@huawei.com, alexandru.elisei@arm.com, thuth@redhat.com Subject: [kvm-unit-tests PATCH 13/16] arm/arm64: ITS: INT functional tests Date: Mon, 16 Dec 2019 15:02:32 +0100 Message-Id: <20191216140235.10751-14-eric.auger@redhat.com> In-Reply-To: <20191216140235.10751-1-eric.auger@redhat.com> References: <20191216140235.10751-1-eric.auger@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.79 on 10.5.11.15 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 205.139.110.120 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 16 Dec 2019 14:04:35 -0000 Triggers LPIs through the INT command. the test checks the LPI hits the right CPU and triggers the right LPI intid, ie. the translation is correct. Updates to the config table also are tested, along with inv and invall commands. Signed-off-by: Eric Auger --- arm/gic.c | 174 +++++++++++++++++++++++++++++++++++++++ arm/unittests.cfg | 6 ++ lib/arm/asm/gic-v3-its.h | 14 ++++ 3 files changed, 194 insertions(+) diff --git a/arm/gic.c b/arm/gic.c index 8b56fce..6b73258 100644 --- a/arm/gic.c +++ b/arm/gic.c @@ -34,6 +34,7 @@ static struct gic *gic; static int acked[NR_CPUS], spurious[NR_CPUS]; static int bad_sender[NR_CPUS], bad_irq[NR_CPUS]; static cpumask_t ready; +static struct its_stats lpi_stats; =20 static void nr_cpu_check(int nr) { @@ -158,6 +159,54 @@ static void ipi_handler(struct pt_regs *regs __unuse= d) } } =20 +static void lpi_handler(struct pt_regs *regs __unused) +{ + u32 irqstat =3D gic_read_iar(); + int irqnr =3D gic_iar_irqnr(irqstat); + + gic_write_eoir(irqstat); + if (irqnr < 8192) + report(false, "Unexpected non LPI interrupt received"); + smp_rmb(); /* pairs with wmb in lpi_stats_expect */ + lpi_stats.observed.cpu_id =3D smp_processor_id(); + lpi_stats.observed.lpi_id =3D irqnr; + smp_wmb(); /* pairs with rmb in check_lpi_stats */ +} + +static void lpi_stats_expect(int exp_cpu_id, int exp_lpi_id) +{ + lpi_stats.expected.cpu_id =3D exp_cpu_id; + lpi_stats.expected.lpi_id =3D exp_lpi_id; + lpi_stats.observed.cpu_id =3D -1; + lpi_stats.observed.lpi_id =3D -1; + smp_wmb(); /* pairs with rmb in handler */ +} + +static void check_lpi_stats(void) +{ + mdelay(100); + smp_rmb(); /* pairs with wmb in lpi_handler */ + if ((lpi_stats.observed.cpu_id !=3D lpi_stats.expected.cpu_id) || + (lpi_stats.observed.lpi_id !=3D lpi_stats.expected.lpi_id)) { + if (lpi_stats.observed.cpu_id =3D=3D -1 && + lpi_stats.observed.lpi_id =3D=3D -1) { + report(false, + "No LPI received whereas (cpuid=3D%d, intid=3D%d) " + "was expected", lpi_stats.expected.cpu_id, + lpi_stats.expected.lpi_id); + } else { + report(false, "Unexpected LPI (cpuid=3D%d, intid=3D%d)", + lpi_stats.observed.cpu_id, + lpi_stats.observed.lpi_id); + } + } else if (lpi_stats.expected.lpi_id !=3D -1) { + report(true, "LPI %d on CPU %d", lpi_stats.observed.lpi_id, + lpi_stats.observed.cpu_id); + } else { + report(true, "no LPI received, as expected"); + } +} + static void gicv2_ipi_send_self(void) { writel(2 << 24 | IPI_IRQ, gicv2_dist_base() + GICD_SGIR); @@ -241,6 +290,14 @@ static void ipi_test(void *data __unused) ipi_recv(); } =20 +static void secondary_lpi_test(void) +{ + setup_irq(lpi_handler); + cpumask_set_cpu(smp_processor_id(), &ready); + while (1) + wfi(); +} + static struct gic gicv2 =3D { .ipi =3D { .send_self =3D gicv2_ipi_send_self, @@ -552,6 +609,120 @@ static void test_its_baser(void) report_info("collection baser entry_size =3D 0x%x", dev_baser->esz); } =20 +static int its_prerequisites(int nb_cpus) +{ + int cpu; + + if (!gicv3_its_base()) { + report_skip("No ITS, skip ..."); + return -1; + } + + if (nr_cpus < 4) { + report_skip("Test requires at least %d vcpus", nb_cpus); + return -1; + } + + stats_reset(); + + setup_irq(lpi_handler); + + for_each_present_cpu(cpu) { + if (cpu =3D=3D 0) + continue; + smp_boot_secondary(cpu, secondary_lpi_test); + } + wait_on_ready(); + + its_enable_defaults(); + + lpi_stats_expect(-1, -1); + check_lpi_stats(); + + return 0; +} + +static void test_its_trigger(void) +{ + struct its_collection *col3, *col2; + struct its_device *dev2, *dev7; + + if (its_prerequisites(4)) + return; + + dev2 =3D its_create_device(2 /* dev id */, 8 /* nb_ites */); + dev7 =3D its_create_device(7 /* dev id */, 8 /* nb_ites */); + + col3 =3D its_create_collection(3 /* col id */, 3/* target PE */); + col2 =3D its_create_collection(2 /* col id */, 2/* target PE */); + + set_lpi_config(8195, LPI_PROP_DEFAULT); + set_lpi_config(8196, LPI_PROP_DEFAULT); + + its_send_invall(col2); + its_send_invall(col3); + + report_prefix_push("int"); + + its_send_mapd(dev2, true); + its_send_mapd(dev7, true); + + its_send_mapc(col3, true); + its_send_mapc(col2, true); + + its_send_mapti(dev2, 8195 /* lpi id */, + 20 /* event id */, col3); + its_send_mapti(dev7, 8196 /* lpi id */, + 255 /* event id */, col2); + + lpi_stats_expect(3, 8195); + its_send_int(dev2, 20); + check_lpi_stats(); + + lpi_stats_expect(2, 8196); + its_send_int(dev7, 255); + check_lpi_stats(); + + report_prefix_pop(); + + report_prefix_push("inv/invall"); + + /* disable 8195 */ + set_lpi_config(8195, LPI_PROP_DEFAULT & ~0x1); + its_send_inv(dev2, 20); + + lpi_stats_expect(-1, -1); + its_send_int(dev2, 20); + check_lpi_stats(); + + set_lpi_config(8195, LPI_PROP_DEFAULT); + /* willingly forget the INVALL*/ + lpi_stats_expect(-1, -1); + its_send_int(dev2, 20); + check_lpi_stats(); + + its_send_invall(col3); + lpi_stats_expect(3, 8195); + its_send_int(dev2, 20); + check_lpi_stats(); + + report_prefix_pop(); + + report_prefix_push("mapd valid=3Dfalse"); + its_send_mapd(dev2, false); + lpi_stats_expect(-1, -1); + its_send_int(dev2, 20); + check_lpi_stats(); + report_prefix_pop(); + + report_prefix_push("mapc valid=3Dfalse"); + its_send_mapc(col2, false); + lpi_stats_expect(-1, -1); + its_send_int(dev7, 255); + check_lpi_stats(); +} + + int main(int argc, char **argv) { if (!gic_init()) { @@ -582,6 +753,9 @@ int main(int argc, char **argv) } else if (strcmp(argv[1], "mmio") =3D=3D 0) { report_prefix_push(argv[1]); gic_test_mmio(); + } else if (!strcmp(argv[1], "its-trigger")) { + report_prefix_push(argv[1]); + test_its_trigger(); report_prefix_pop(); } else if (strcmp(argv[1], "its-introspection") =3D=3D 0) { report_prefix_push(argv[1]); diff --git a/arm/unittests.cfg b/arm/unittests.cfg index 2234a0f..80a1d27 100644 --- a/arm/unittests.cfg +++ b/arm/unittests.cfg @@ -134,6 +134,12 @@ smp =3D $MAX_SMP extra_params =3D -machine gic-version=3D3 -append 'its-baser' groups =3D its =20 +[its-trigger] +file =3D gic.flat +smp =3D $MAX_SMP +extra_params =3D -machine gic-version=3D3 -append 'its-trigger' +groups =3D its + # Test PSCI emulation [psci] file =3D psci.flat diff --git a/lib/arm/asm/gic-v3-its.h b/lib/arm/asm/gic-v3-its.h index d074c17..d4fd799 100644 --- a/lib/arm/asm/gic-v3-its.h +++ b/lib/arm/asm/gic-v3-its.h @@ -162,6 +162,16 @@ struct its_data { u32 nb_collections; /* Allocated Collections */ }; =20 +struct its_event { + int cpu_id; + int lpi_id; +}; + +struct its_stats { + struct its_event expected; + struct its_event observed; +}; + extern struct its_data its_data; =20 #define gicv3_its_base() (its_data.base) @@ -178,6 +188,10 @@ extern void gicv3_rdist_ctrl_lpi(u32 redist, bool se= t); extern void its_enable_defaults(void); extern struct its_device *its_create_device(u32 dev_id, int nr_ites); extern struct its_collection *its_create_collection(u32 col_id, u32 targ= et_pe); +extern struct its_collection *its_create_collection(u32 col_id, u32 targ= et); + +extern void set_lpi_config(int n, u8 val); +extern u8 get_lpi_config(int n); =20 extern void its_send_mapd(struct its_device *dev, int valid); extern void its_send_mapc(struct its_collection *col, int valid); --=20 2.20.1 From MAILER-DAEMON Mon Dec 16 09:04:38 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1igqzG-0004uB-KM for mharc-qemu-arm@gnu.org; Mon, 16 Dec 2019 09:04:38 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:58778) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1igqzE-0004ql-51 for qemu-arm@nongnu.org; Mon, 16 Dec 2019 09:04:37 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1igqzC-00043I-SE for qemu-arm@nongnu.org; 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Mon, 16 Dec 2019 09:04:31 -0500 X-MC-Unique: jrVVURoXNyO-sGEQ6te3lw-1 Received: from smtp.corp.redhat.com (int-mx05.intmail.prod.int.phx2.redhat.com [10.5.11.15]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx01.redhat.com (Postfix) with ESMTPS id 6E45C800D50; Mon, 16 Dec 2019 14:04:29 +0000 (UTC) Received: from laptop.redhat.com (ovpn-116-117.ams2.redhat.com [10.36.116.117]) by smtp.corp.redhat.com (Postfix) with ESMTP id 83197675B8; Mon, 16 Dec 2019 14:04:26 +0000 (UTC) From: Eric Auger To: eric.auger.pro@gmail.com, eric.auger@redhat.com, maz@kernel.org, kvmarm@lists.cs.columbia.edu, kvm@vger.kernel.org, qemu-devel@nongnu.org, qemu-arm@nongnu.org Cc: drjones@redhat.com, andre.przywara@arm.com, peter.maydell@linaro.org, yuzenghui@huawei.com, alexandru.elisei@arm.com, thuth@redhat.com Subject: [kvm-unit-tests PATCH 14/16] arm/run: Allow Migration tests Date: Mon, 16 Dec 2019 15:02:33 +0100 Message-Id: <20191216140235.10751-15-eric.auger@redhat.com> In-Reply-To: <20191216140235.10751-1-eric.auger@redhat.com> References: <20191216140235.10751-1-eric.auger@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.79 on 10.5.11.15 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 207.211.31.81 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 16 Dec 2019 14:04:37 -0000 Let's link getchar.o to use puts and getchar from the tests. Then allow tests belonging to the migration group to trigger the migration from the test code by putting "migrate" into the uart. Then the code can wait for the migration completion by using getchar(). The __getchar implement is minimalist as it just reads the data register. It is just meant to read the single character emitted at the end of the migration by the runner script. It is not meant to read more data (FIFOs are not enabled). Signed-off-by: Eric Auger --- arm/Makefile.common | 2 +- arm/run | 2 +- lib/arm/io.c | 13 +++++++++++++ 3 files changed, 15 insertions(+), 2 deletions(-) diff --git a/arm/Makefile.common b/arm/Makefile.common index 7cc0f04..327f112 100644 --- a/arm/Makefile.common +++ b/arm/Makefile.common @@ -32,7 +32,7 @@ CFLAGS +=3D -I $(SRCDIR)/lib -I $(SRCDIR)/lib/libfdt -I= lib asm-offsets =3D lib/$(ARCH)/asm-offsets.h include $(SRCDIR)/scripts/asm-offsets.mak =20 -cflatobjs +=3D lib/util.o +cflatobjs +=3D lib/util.o lib/getchar.o cflatobjs +=3D lib/alloc_phys.o cflatobjs +=3D lib/alloc_page.o cflatobjs +=3D lib/vmalloc.o diff --git a/arm/run b/arm/run index 277db9b..a390ca5 100755 --- a/arm/run +++ b/arm/run @@ -61,6 +61,6 @@ fi M+=3D",accel=3D$ACCEL" command=3D"$qemu -nodefaults $M -cpu $processor $chr_testdev $pci_testde= v" command+=3D" -display none -serial stdio -kernel" -command=3D"$(timeout_cmd) $command" +command=3D"$(migration_cmd) $(timeout_cmd) $command" =20 run_qemu $command "$@" diff --git a/lib/arm/io.c b/lib/arm/io.c index 99fd315..aa9e1b5 100644 --- a/lib/arm/io.c +++ b/lib/arm/io.c @@ -87,6 +87,19 @@ void puts(const char *s) spin_unlock(&uart_lock); } =20 +/* + * Minimalist implementation for migration completion detection. + * Needs to be improved for more advanced Rx cases + */ +int __getchar(void) +{ + int ret; + + ret =3D readb(uart0_base); + if (!ret) + return -1; + return ret; +} =20 /* * Defining halt to take 'code' as an argument guarantees that it will --=20 2.20.1 From MAILER-DAEMON Mon Dec 16 09:04:45 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1igqzN-00055T-9U for mharc-qemu-arm@gnu.org; Mon, 16 Dec 2019 09:04:45 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:58823) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1igqzJ-0004zW-Ks for qemu-arm@nongnu.org; Mon, 16 Dec 2019 09:04:43 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1igqzI-00045t-2c for qemu-arm@nongnu.org; Mon, 16 Dec 2019 09:04:41 -0500 Received: from us-smtp-2.mimecast.com ([205.139.110.61]:42403 helo=us-smtp-delivery-1.mimecast.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1igqzH-00045h-UD for qemu-arm@nongnu.org; Mon, 16 Dec 2019 09:04:40 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1576505079; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=lQJlLjmRnoxnyH5I+FAGf7Zim3+eldLoAm/hBFPMOq8=; b=JpMFaasEnFeDZcKsi5MJ/IEHnghF81Qe3qoaVsptWaboyOQYdZx/iCforGMnd8pDkZqXg7 70+k5YpyzxJeciLdzH6qbRxcw0/z7CncZA80u17xIvzqDcPkeFQB+1JUYq9jonJxlcgcnG B7rG55tt+ongH8dATmQJCXgrT3YNIhQ= Received: from mimecast-mx01.redhat.com (mimecast-mx01.redhat.com [209.132.183.4]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-146-uP40nYjUPiaYgrBYDA816Q-1; Mon, 16 Dec 2019 09:04:37 -0500 X-MC-Unique: uP40nYjUPiaYgrBYDA816Q-1 Received: from smtp.corp.redhat.com (int-mx05.intmail.prod.int.phx2.redhat.com [10.5.11.15]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx01.redhat.com (Postfix) with ESMTPS id 1DC5118543AE; Mon, 16 Dec 2019 14:04:36 +0000 (UTC) Received: from laptop.redhat.com (ovpn-116-117.ams2.redhat.com [10.36.116.117]) by smtp.corp.redhat.com (Postfix) with ESMTP id 253EE675B8; Mon, 16 Dec 2019 14:04:32 +0000 (UTC) From: Eric Auger To: eric.auger.pro@gmail.com, eric.auger@redhat.com, maz@kernel.org, kvmarm@lists.cs.columbia.edu, kvm@vger.kernel.org, qemu-devel@nongnu.org, qemu-arm@nongnu.org Cc: drjones@redhat.com, andre.przywara@arm.com, peter.maydell@linaro.org, yuzenghui@huawei.com, alexandru.elisei@arm.com, thuth@redhat.com Subject: [kvm-unit-tests PATCH 16/16] arm/arm64: ITS: pending table migration test Date: Mon, 16 Dec 2019 15:02:35 +0100 Message-Id: <20191216140235.10751-17-eric.auger@redhat.com> In-Reply-To: <20191216140235.10751-1-eric.auger@redhat.com> References: <20191216140235.10751-1-eric.auger@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.79 on 10.5.11.15 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 205.139.110.61 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 16 Dec 2019 14:04:44 -0000 Add two new migration tests. One testing the migration of a topology where collection were unmapped. The second test checks the migration of the pending table. Signed-off-by: Eric Auger --- arm/gic.c | 148 ++++++++++++++++++++++++++++++++++++++++++++++ arm/unittests.cfg | 16 ++++- 2 files changed, 163 insertions(+), 1 deletion(-) diff --git a/arm/gic.c b/arm/gic.c index 8cca743..fc8cf6e 100644 --- a/arm/gic.c +++ b/arm/gic.c @@ -170,6 +170,7 @@ static void lpi_handler(struct pt_regs *regs __unused= ) smp_rmb(); /* pairs with wmb in lpi_stats_expect */ lpi_stats.observed.cpu_id =3D smp_processor_id(); lpi_stats.observed.lpi_id =3D irqnr; + acked[lpi_stats.observed.cpu_id]++; smp_wmb(); /* pairs with rmb in check_lpi_stats */ } =20 @@ -207,6 +208,18 @@ static void check_lpi_stats(void) } } =20 +static void check_lpi_hits(int *expected) +{ + int i; + + for (i =3D 0; i < nr_cpus; i++) { + if (acked[i] !=3D expected[i]) + report(false, "expected %d LPIs on PE #%d, %d observed", + expected[i], i, acked[i]); + } + report(true, "check LPI on all vcpus"); +} + static void gicv2_ipi_send_self(void) { writel(2 << 24 | IPI_IRQ, gicv2_dist_base() + GICD_SGIR); @@ -642,6 +655,18 @@ static int its_prerequisites(int nb_cpus) return 0; } =20 +static void set_lpi(struct its_device *dev, u32 eventid, u32 physid, + struct its_collection *col) +{ + if (!dev || !col) + report_abort("wrong device or collection"); + + its_send_mapti(dev, physid, eventid, col); + + set_lpi_config(physid, LPI_PROP_DEFAULT); + its_send_invall(col); +} + /* * Setup the configuration for those mappings: * dev_id=3D2 event=3D20 -> vcpu 3, intid=3D8195 @@ -766,6 +791,121 @@ static void test_its_migration(void) check_lpi_stats(); } =20 +static void test_migrate_unmapped_collection(void) +{ + struct its_collection *col; + struct its_device *dev2, *dev7; + u8 config; + + if (its_setup1()) + return; + + col =3D its_create_collection(nr_cpus - 1, nr_cpus - 1); + dev2 =3D its_get_device(2); + dev7 =3D its_get_device(7); + + /* MAPTI with the collection unmapped */ + set_lpi(dev2, 0, 8192, col); + + puts("Now migrate the VM, then press a key to continue...\n"); + (void)getchar(); + report(true, "Migration complete"); + + /* on the destination, map the collection */ + its_send_mapc(col, true); + + lpi_stats_expect(2, 8196); + its_send_int(dev7, 255); + check_lpi_stats(); + + config =3D get_lpi_config(8192); + report(config =3D=3D LPI_PROP_DEFAULT, + "Config of LPI 8192 was properly migrated"); + + lpi_stats_expect(nr_cpus - 1, 8192); + its_send_int(dev2, 0); + check_lpi_stats(); + + /* unmap the collection */ + its_send_mapc(col, false); + + lpi_stats_expect(-1, -1); + its_send_int(dev2, 0); + check_lpi_stats(); + + /* remap event 0 onto lpiid 8193 */ + set_lpi(dev2, 0, 8193, col); + lpi_stats_expect(-1, -1); + its_send_int(dev2, 0); + check_lpi_stats(); + + /* remap the collection */ + its_send_mapc(col, true); + lpi_stats_expect(nr_cpus - 1, 8193); +} + +static void test_its_pending_migration(void) +{ + struct its_device *dev; + struct its_collection *collection[2]; + int expected[NR_CPUS]; + u64 pendbaser; + void *ptr; + int i; + + if (its_prerequisites(4)) + return; + + dev =3D its_create_device(2 /* dev id */, 8 /* nb_ites */); + its_send_mapd(dev, true); + + collection[0] =3D its_create_collection(nr_cpus - 1, nr_cpus - 1); + collection[1] =3D its_create_collection(nr_cpus - 2, nr_cpus - 2); + its_send_mapc(collection[0], true); + its_send_mapc(collection[1], true); + + /* disable lpi at redist level */ + gicv3_rdist_ctrl_lpi(nr_cpus - 1, false); + gicv3_rdist_ctrl_lpi(nr_cpus - 2, false); + + /* even lpis are assigned to even cpu */ + for (i =3D 0; i < 256; i++) { + struct its_collection *col =3D i % 2 ? collection[0] : + collection[1]; + int vcpu =3D col->target_address >> 16; + + its_send_mapti(dev, 8192 + i, i, col); + set_lpi_config(8192 + i, LPI_PROP_DEFAULT); + set_pending_table_bit(vcpu, 8192 + i, true); + } + its_send_invall(collection[0]); + its_send_invall(collection[1]); + + /* Set the PTZ bit on each pendbaser */ + + expected[nr_cpus - 1] =3D 128; + expected[nr_cpus - 2] =3D 128; + + ptr =3D gicv3_data.redist_base[nr_cpus - 1] + GICR_PENDBASER; + pendbaser =3D readq(ptr); + writeq(pendbaser & ~GICR_PENDBASER_PTZ, ptr); + + ptr =3D gicv3_data.redist_base[nr_cpus - 2] + GICR_PENDBASER; + pendbaser =3D readq(ptr); + writeq(pendbaser & ~GICR_PENDBASER_PTZ, ptr); + + gicv3_rdist_ctrl_lpi(nr_cpus - 1, true); + gicv3_rdist_ctrl_lpi(nr_cpus - 2, true); + + puts("Now migrate the VM, then press a key to continue...\n"); + (void)getchar(); + report(true, "Migration complete"); + + mdelay(1000); + + check_lpi_hits(expected); +} + int main(int argc, char **argv) { if (!gic_init()) { @@ -804,6 +944,14 @@ int main(int argc, char **argv) report_prefix_push(argv[1]); test_its_migration(); report_prefix_pop(); + } else if (!strcmp(argv[1], "its-pending-migration")) { + report_prefix_push(argv[1]); + test_its_pending_migration(); + report_prefix_pop(); + } else if (!strcmp(argv[1], "its-migrate-unmapped-collection")) { + report_prefix_push(argv[1]); + test_migrate_unmapped_collection(); + report_prefix_pop(); } else if (strcmp(argv[1], "its-introspection") =3D=3D 0) { report_prefix_push(argv[1]); test_its_introspection(); diff --git a/arm/unittests.cfg b/arm/unittests.cfg index 29e2efc..911f0b7 100644 --- a/arm/unittests.cfg +++ b/arm/unittests.cfg @@ -145,7 +145,21 @@ file =3D gic.flat smp =3D $MAX_SMP accel =3D kvm extra_params =3D -machine gic-version=3D3 -append 'its-migration' -groups =3D its migration +groups =3D migration + +[its-pending-migration] +file =3D gic.flat +smp =3D $MAX_SMP +accel =3D kvm +extra_params =3D -machine gic-version=3D3 -append 'its-pending-migration= ' +groups =3D migration + +[its-migrate-unmapped-collection] +file =3D gic.flat +smp =3D $MAX_SMP +accel =3D kvm +extra_params =3D -machine gic-version=3D3 -append 'its-migrate-unmapped-= collection' +groups =3D migration =20 # Test PSCI emulation [psci] --=20 2.20.1 From MAILER-DAEMON Mon Dec 16 09:04:47 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1igqzP-00059G-FU for mharc-qemu-arm@gnu.org; Mon, 16 Dec 2019 09:04:47 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:58800) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1igqzG-0004te-8J for qemu-arm@nongnu.org; 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Mon, 16 Dec 2019 09:04:34 -0500 X-MC-Unique: Kf2l28LmO9O_7pIkl3byZg-1 Received: from smtp.corp.redhat.com (int-mx05.intmail.prod.int.phx2.redhat.com [10.5.11.15]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx01.redhat.com (Postfix) with ESMTPS id BEA6F593A2; Mon, 16 Dec 2019 14:04:32 +0000 (UTC) Received: from laptop.redhat.com (ovpn-116-117.ams2.redhat.com [10.36.116.117]) by smtp.corp.redhat.com (Postfix) with ESMTP id C8645675BE; Mon, 16 Dec 2019 14:04:29 +0000 (UTC) From: Eric Auger To: eric.auger.pro@gmail.com, eric.auger@redhat.com, maz@kernel.org, kvmarm@lists.cs.columbia.edu, kvm@vger.kernel.org, qemu-devel@nongnu.org, qemu-arm@nongnu.org Cc: drjones@redhat.com, andre.przywara@arm.com, peter.maydell@linaro.org, yuzenghui@huawei.com, alexandru.elisei@arm.com, thuth@redhat.com Subject: [kvm-unit-tests PATCH 15/16] arm/arm64: ITS: migration tests Date: Mon, 16 Dec 2019 15:02:34 +0100 Message-Id: <20191216140235.10751-16-eric.auger@redhat.com> In-Reply-To: <20191216140235.10751-1-eric.auger@redhat.com> References: <20191216140235.10751-1-eric.auger@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.79 on 10.5.11.15 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 205.139.110.61 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 16 Dec 2019 14:04:44 -0000 This test maps LPIs (populates the device table, the collection table, interrupt translation tables, configuration table), migrates and make sure the translation is correct on the destination. Signed-off-by: Eric Auger --- arm/gic.c | 55 +++++++++++++++++++++++++++++++++++++--- arm/unittests.cfg | 7 +++++ lib/arm/asm/gic-v3-its.h | 2 ++ lib/arm/gic-v3-its.c | 22 ++++++++++++++++ 4 files changed, 82 insertions(+), 4 deletions(-) diff --git a/arm/gic.c b/arm/gic.c index 6b73258..8cca743 100644 --- a/arm/gic.c +++ b/arm/gic.c @@ -642,13 +642,19 @@ static int its_prerequisites(int nb_cpus) return 0; } =20 -static void test_its_trigger(void) +/* + * Setup the configuration for those mappings: + * dev_id=3D2 event=3D20 -> vcpu 3, intid=3D8195 + * dev_id=3D7 event=3D255 -> vcpu 2, intid=3D8196 + * LPIs ready to hit + */ +static int its_setup1(void) { struct its_collection *col3, *col2; struct its_device *dev2, *dev7; =20 if (its_prerequisites(4)) - return; + return -1; =20 dev2 =3D its_create_device(2 /* dev id */, 8 /* nb_ites */); dev7 =3D its_create_device(7 /* dev id */, 8 /* nb_ites */); @@ -662,8 +668,6 @@ static void test_its_trigger(void) its_send_invall(col2); its_send_invall(col3); =20 - report_prefix_push("int"); - its_send_mapd(dev2, true); its_send_mapd(dev7, true); =20 @@ -674,6 +678,23 @@ static void test_its_trigger(void) 20 /* event id */, col3); its_send_mapti(dev7, 8196 /* lpi id */, 255 /* event id */, col2); + return 0; +} + +static void test_its_trigger(void) +{ + struct its_collection *col3, *col2; + struct its_device *dev2, *dev7; + + if (its_setup1()) + return; + + col3 =3D its_get_collection(3); + col2 =3D its_get_collection(2); + dev2 =3D its_get_device(2); + dev7 =3D its_get_device(7); + + report_prefix_push("int"); =20 lpi_stats_expect(3, 8195); its_send_int(dev2, 20); @@ -722,6 +743,28 @@ static void test_its_trigger(void) check_lpi_stats(); } =20 +static void test_its_migration(void) +{ + struct its_device *dev2, *dev7; + + if (its_setup1()) + return; + + dev2 =3D its_get_device(2); + dev7 =3D its_get_device(7); + + puts("Now migrate the VM, then press a key to continue...\n"); + (void)getchar(); + report(true, "Migration complete"); + + lpi_stats_expect(3, 8195); + its_send_int(dev2, 20); + check_lpi_stats(); + + lpi_stats_expect(2, 8196); + its_send_int(dev7, 255); + check_lpi_stats(); +} =20 int main(int argc, char **argv) { @@ -757,6 +800,10 @@ int main(int argc, char **argv) report_prefix_push(argv[1]); test_its_trigger(); report_prefix_pop(); + } else if (!strcmp(argv[1], "its-migration")) { + report_prefix_push(argv[1]); + test_its_migration(); + report_prefix_pop(); } else if (strcmp(argv[1], "its-introspection") =3D=3D 0) { report_prefix_push(argv[1]); test_its_introspection(); diff --git a/arm/unittests.cfg b/arm/unittests.cfg index 80a1d27..29e2efc 100644 --- a/arm/unittests.cfg +++ b/arm/unittests.cfg @@ -140,6 +140,13 @@ smp =3D $MAX_SMP extra_params =3D -machine gic-version=3D3 -append 'its-trigger' groups =3D its =20 +[its-migration] +file =3D gic.flat +smp =3D $MAX_SMP +accel =3D kvm +extra_params =3D -machine gic-version=3D3 -append 'its-migration' +groups =3D its migration + # Test PSCI emulation [psci] file =3D psci.flat diff --git a/lib/arm/asm/gic-v3-its.h b/lib/arm/asm/gic-v3-its.h index d4fd799..c38d524 100644 --- a/lib/arm/asm/gic-v3-its.h +++ b/lib/arm/asm/gic-v3-its.h @@ -206,6 +206,8 @@ extern void its_send_movi(struct its_device *dev, struct its_collection *col, u32 id); extern void its_send_sync(struct its_collection *col); extern void its_print_cmd_state(void); +extern struct its_device *its_get_device(u32 id); +extern struct its_collection *its_get_collection(u32 id); =20 #define ITS_FLAGS_CMDQ_NEEDS_FLUSHING (1ULL << 0) #define ITS_FLAGS_WORKAROUND_CAVIUM_22375 (1ULL << 1) diff --git a/lib/arm/gic-v3-its.c b/lib/arm/gic-v3-its.c index 9906428..e2e289c 100644 --- a/lib/arm/gic-v3-its.c +++ b/lib/arm/gic-v3-its.c @@ -330,3 +330,25 @@ struct its_collection *its_create_collection(u32 col= _id, u32 pe) its_data.nb_collections++; return new; } + +struct its_device *its_get_device(u32 id) +{ + int i; + + for (i =3D 0; i < GITS_MAX_DEVICES; i++) { + if (its_data.devices[i].device_id =3D=3D id) + return &its_data.devices[i]; + } + return NULL; +} + +struct its_collection *its_get_collection(u32 id) +{ + int i; + + for (i =3D 0; i < GITS_MAX_COLLECTIONS; i++) { + if (its_data.collections[i].col_id =3D=3D id) + return &its_data.collections[i]; + } + return NULL; +} --=20 2.20.1 From MAILER-DAEMON Mon Dec 16 09:05:13 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1igqzp-0005pU-Qc for mharc-qemu-arm@gnu.org; Mon, 16 Dec 2019 09:05:13 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:58911) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1igqzm-0005iZ-HS for qemu-arm@nongnu.org; Mon, 16 Dec 2019 09:05:11 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1igqzk-0004Ag-Sm for qemu-arm@nongnu.org; Mon, 16 Dec 2019 09:05:10 -0500 Received: from us-smtp-delivery-1.mimecast.com ([207.211.31.120]:33822 helo=us-smtp-1.mimecast.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1igqzk-0004AR-OZ for qemu-arm@nongnu.org; Mon, 16 Dec 2019 09:05:08 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1576505108; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=50Vms+tgESY3M8NHXPohpfNztkjGMy8JPeeKVTKoeLA=; b=WJZi8EbZR5dv6PD/koY1elsdkh2W15JkQL+Ut90O5iaAZ0CoOVOrlfCwFEjz82FmRJ18G9 GwGh1RLuT7d8ID8zd4RQ0jP35HjDrzJuZwXDXYvpHcCAo/m4jKL9Qzu13oaIKF7Vxa1RAB HdqiKKNqCAoc941xealBogZiNbvzxLM= Received: from mimecast-mx01.redhat.com (mimecast-mx01.redhat.com [209.132.183.4]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-215-i2RWS0w7O9OR_4XEIYzBcg-1; Mon, 16 Dec 2019 09:04:19 -0500 X-MC-Unique: i2RWS0w7O9OR_4XEIYzBcg-1 Received: from smtp.corp.redhat.com (int-mx05.intmail.prod.int.phx2.redhat.com [10.5.11.15]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx01.redhat.com (Postfix) with ESMTPS id 2CCD180257B; Mon, 16 Dec 2019 14:04:17 +0000 (UTC) Received: from laptop.redhat.com (ovpn-116-117.ams2.redhat.com [10.36.116.117]) by smtp.corp.redhat.com (Postfix) with ESMTP id 3242968863; Mon, 16 Dec 2019 14:04:14 +0000 (UTC) From: Eric Auger To: eric.auger.pro@gmail.com, eric.auger@redhat.com, maz@kernel.org, kvmarm@lists.cs.columbia.edu, kvm@vger.kernel.org, qemu-devel@nongnu.org, qemu-arm@nongnu.org Cc: drjones@redhat.com, andre.przywara@arm.com, peter.maydell@linaro.org, yuzenghui@huawei.com, alexandru.elisei@arm.com, thuth@redhat.com Subject: [kvm-unit-tests PATCH 11/16] arm/arm64: ITS: Device and collection Initialization Date: Mon, 16 Dec 2019 15:02:30 +0100 Message-Id: <20191216140235.10751-12-eric.auger@redhat.com> In-Reply-To: <20191216140235.10751-1-eric.auger@redhat.com> References: <20191216140235.10751-1-eric.auger@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.79 on 10.5.11.15 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 207.211.31.120 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 16 Dec 2019 14:05:12 -0000 Introduce an helper functions to register - a new device, characterized by its device id and the max number of event IDs that dimension its ITT (Interrupt Translation Table). The function allocates the ITT. - a new collection, characterized by its ID and the target processing engine (PE). Signed-off-by: Eric Auger --- --- lib/arm/asm/gic-v3-its.h | 20 +++++++++++++++++ lib/arm/gic-v3-its.c | 46 ++++++++++++++++++++++++++++++++++++++++ 2 files changed, 66 insertions(+) diff --git a/lib/arm/asm/gic-v3-its.h b/lib/arm/asm/gic-v3-its.h index ab639c5..245ef61 100644 --- a/lib/arm/asm/gic-v3-its.h +++ b/lib/arm/asm/gic-v3-its.h @@ -87,6 +87,9 @@ =20 #define ITS_FLAGS_CMDQ_NEEDS_FLUSHING (1ULL << 0) =20 +#define GITS_MAX_DEVICES 8 +#define GITS_MAX_COLLECTIONS 8 + struct its_typer { unsigned int ite_size; unsigned int eventid_bits; @@ -117,6 +120,17 @@ struct its_cmd_block { u64 raw_cmd[4]; }; =20 +struct its_device { + u32 device_id; /* device ID */ + u32 nr_ites; /* Max Interrupt Translation Entries */ + void *itt; /* Interrupt Translation Table GPA */ +}; + +struct its_collection { + u64 target_address; + u16 col_id; +}; + struct its_data { void *base; struct its_typer typer; @@ -124,6 +138,10 @@ struct its_data { struct its_cmd_block *cmd_base; struct its_cmd_block *cmd_write; struct its_cmd_block *cmd_readr; + struct its_device devices[GITS_MAX_DEVICES]; + u32 nb_devices; /* Allocated Devices */ + struct its_collection collections[GITS_MAX_COLLECTIONS]; + u32 nb_collections; /* Allocated Collections */ }; =20 extern struct its_data its_data; @@ -140,6 +158,8 @@ extern u8 get_lpi_config(int n); extern void set_pending_table_bit(int rdist, int n, bool set); extern void gicv3_rdist_ctrl_lpi(u32 redist, bool set); extern void its_enable_defaults(void); +extern struct its_device *its_create_device(u32 dev_id, int nr_ites); +extern struct its_collection *its_create_collection(u32 col_id, u32 targ= et_pe); =20 #endif /* !__ASSEMBLY__ */ #endif /* _ASMARM_GIC_V3_ITS_H_ */ diff --git a/lib/arm/gic-v3-its.c b/lib/arm/gic-v3-its.c index 9a51ef4..9906428 100644 --- a/lib/arm/gic-v3-its.c +++ b/lib/arm/gic-v3-its.c @@ -284,3 +284,49 @@ void its_enable_defaults(void) =20 writel(GITS_CTLR_ENABLE, its_data.base + GITS_CTLR); } + +struct its_device *its_create_device(u32 device_id, int nr_ites) +{ + struct its_baser *baser; + struct its_device *new; + unsigned long n, order; + + if (its_data.nb_devices >=3D GITS_MAX_DEVICES) + report_abort("%s redimension GITS_MAX_DEVICES", __func__); + + baser =3D its_lookup_baser(GITS_BASER_TYPE_DEVICE); + if (!baser) + return NULL; + + new =3D &its_data.devices[its_data.nb_devices]; + + new->device_id =3D device_id; + new->nr_ites =3D nr_ites; + + n =3D (baser->esz * nr_ites) >> PAGE_SHIFT; + order =3D is_power_of_2(n) ? fls(n) : fls(n) + 1; + new->itt =3D (void *)virt_to_phys(alloc_pages(order)); + + its_data.nb_devices++; + return new; +} + +struct its_collection *its_create_collection(u32 col_id, u32 pe) +{ + struct its_collection *new; + + if (its_data.nb_collections >=3D GITS_MAX_COLLECTIONS) + report_abort("%s redimension GITS_MAX_COLLECTIONS", __func__); + + new =3D &its_data.collections[its_data.nb_collections]; + + new->col_id =3D col_id; + + if (its_data.typer.pta) + new->target_address =3D (u64)gicv3_data.redist_base[pe]; + else + new->target_address =3D pe << 16; + + its_data.nb_collections++; + return new; +} --=20 2.20.1 From MAILER-DAEMON Mon Dec 16 09:05:22 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1igqzx-00064M-VZ for mharc-qemu-arm@gnu.org; Mon, 16 Dec 2019 09:05:21 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:58946) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1igqzs-0005uS-Ds for qemu-arm@nongnu.org; Mon, 16 Dec 2019 09:05:17 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1igqzq-0004GY-Qn for qemu-arm@nongnu.org; Mon, 16 Dec 2019 09:05:16 -0500 Received: from us-smtp-delivery-1.mimecast.com ([207.211.31.120]:41332 helo=us-smtp-1.mimecast.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1igqzq-0004G1-Mg for qemu-arm@nongnu.org; Mon, 16 Dec 2019 09:05:14 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1576505114; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=xlSr73pKSiopKdILGn5ZrLva3IOgBSdl74YTmPimHio=; b=EceEQl2S/7DB5qxiHsjqBoLyzNjSpZMoz0SCSrFLtPTx4N3Ps/cL0odiVpcnVuKYcpK0/v XhaHEI3zE8pm7ZIH3WcUlr2kk0+hxoHjfTGprKhhh7cLZRtRst0EFecn5zD6JrKkY1AVHE zOBXcrdJ75t/mFKdNL1qcwepP+K1dT8= Received: from mimecast-mx01.redhat.com (mimecast-mx01.redhat.com [209.132.183.4]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-275-iwcwYKPnPgyNrdKse5Nt7w-1; Mon, 16 Dec 2019 09:03:40 -0500 X-MC-Unique: iwcwYKPnPgyNrdKse5Nt7w-1 Received: from smtp.corp.redhat.com (int-mx05.intmail.prod.int.phx2.redhat.com [10.5.11.15]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx01.redhat.com (Postfix) with ESMTPS id 70D9DDB33; Mon, 16 Dec 2019 14:03:38 +0000 (UTC) Received: from laptop.redhat.com (ovpn-116-117.ams2.redhat.com [10.36.116.117]) by smtp.corp.redhat.com (Postfix) with ESMTP id 58BE1675B9; Mon, 16 Dec 2019 14:03:31 +0000 (UTC) From: Eric Auger To: eric.auger.pro@gmail.com, eric.auger@redhat.com, maz@kernel.org, kvmarm@lists.cs.columbia.edu, kvm@vger.kernel.org, qemu-devel@nongnu.org, qemu-arm@nongnu.org Cc: drjones@redhat.com, andre.przywara@arm.com, peter.maydell@linaro.org, yuzenghui@huawei.com, alexandru.elisei@arm.com, thuth@redhat.com Subject: [kvm-unit-tests PATCH 02/16] arm: gic: Provide per-IRQ helper functions Date: Mon, 16 Dec 2019 15:02:21 +0100 Message-Id: <20191216140235.10751-3-eric.auger@redhat.com> In-Reply-To: <20191216140235.10751-1-eric.auger@redhat.com> References: <20191216140235.10751-1-eric.auger@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.79 on 10.5.11.15 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 207.211.31.120 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 16 Dec 2019 14:05:19 -0000 From: Andre Przywara A common theme when accessing per-IRQ parameters in the GIC distributor is to set fields of a certain bit width in a range of MMIO registers. Examples are the enabled status (one bit per IRQ), the level/edge configuration (2 bits per IRQ) or the priority (8 bits per IRQ). Add a generic helper function which is able to mask and set the respective number of bits, given the IRQ number and the MMIO offset. Provide wrappers using this function to easily allow configuring an IRQ. For now assume that private IRQ numbers always refer to the current CPU. In a GICv2 accessing the "other" private IRQs is not easily doable (the registers are banked per CPU on the same MMIO address), so we impose the same limitation on GICv3, even though those registers are not banked there anymore. Signed-off-by: Andre Przywara --- initialize reg --- lib/arm/asm/gic-v3.h | 2 + lib/arm/asm/gic.h | 9 +++++ lib/arm/gic.c | 90 ++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 101 insertions(+) diff --git a/lib/arm/asm/gic-v3.h b/lib/arm/asm/gic-v3.h index 347be2f..4a445a5 100644 --- a/lib/arm/asm/gic-v3.h +++ b/lib/arm/asm/gic-v3.h @@ -23,6 +23,8 @@ #define GICD_CTLR_ENABLE_G1A (1U << 1) #define GICD_CTLR_ENABLE_G1 (1U << 0) =20 +#define GICD_IROUTER 0x6000 + /* Re-Distributor registers, offsets from RD_base */ #define GICR_TYPER 0x0008 =20 diff --git a/lib/arm/asm/gic.h b/lib/arm/asm/gic.h index 1fc10a0..21cdb58 100644 --- a/lib/arm/asm/gic.h +++ b/lib/arm/asm/gic.h @@ -15,6 +15,7 @@ #define GICD_IIDR 0x0008 #define GICD_IGROUPR 0x0080 #define GICD_ISENABLER 0x0100 +#define GICD_ICENABLER 0x0180 #define GICD_ISPENDR 0x0200 #define GICD_ICPENDR 0x0280 #define GICD_ISACTIVER 0x0300 @@ -73,5 +74,13 @@ extern void gic_write_eoir(u32 irqstat); extern void gic_ipi_send_single(int irq, int cpu); extern void gic_ipi_send_mask(int irq, const cpumask_t *dest); =20 +void gic_set_irq_bit(int irq, int offset); +void gic_enable_irq(int irq); +void gic_disable_irq(int irq); +void gic_set_irq_priority(int irq, u8 prio); +void gic_set_irq_target(int irq, int cpu); +void gic_set_irq_group(int irq, int group); +int gic_get_irq_group(int irq); + #endif /* !__ASSEMBLY__ */ #endif /* _ASMARM_GIC_H_ */ diff --git a/lib/arm/gic.c b/lib/arm/gic.c index 9430116..aa9cb86 100644 --- a/lib/arm/gic.c +++ b/lib/arm/gic.c @@ -146,3 +146,93 @@ void gic_ipi_send_mask(int irq, const cpumask_t *des= t) assert(gic_common_ops && gic_common_ops->ipi_send_mask); gic_common_ops->ipi_send_mask(irq, dest); } + +enum gic_bit_access { + ACCESS_READ, + ACCESS_SET, + ACCESS_RMW +}; + +static u8 gic_masked_irq_bits(int irq, int offset, int bits, u8 value, + enum gic_bit_access access) +{ + void *base; + int split =3D 32 / bits; + int shift =3D (irq % split) * bits; + u32 reg =3D 0, mask =3D ((1U << bits) - 1) << shift; + + switch (gic_version()) { + case 2: + base =3D gicv2_dist_base(); + break; + case 3: + if (irq < 32) + base =3D gicv3_sgi_base(); + else + base =3D gicv3_dist_base(); + break; + default: + return 0; + } + base +=3D offset + (irq / split) * 4; + + switch (access) { + case ACCESS_READ: + return (readl(base) & mask) >> shift; + case ACCESS_SET: + reg =3D 0; + break; + case ACCESS_RMW: + reg =3D readl(base) & ~mask; + break; + } + + writel(reg | ((u32)value << shift), base); + + return 0; +} + +void gic_set_irq_bit(int irq, int offset) +{ + gic_masked_irq_bits(irq, offset, 1, 1, ACCESS_SET); +} + +void gic_enable_irq(int irq) +{ + gic_set_irq_bit(irq, GICD_ISENABLER); +} + +void gic_disable_irq(int irq) +{ + gic_set_irq_bit(irq, GICD_ICENABLER); +} + +void gic_set_irq_priority(int irq, u8 prio) +{ + gic_masked_irq_bits(irq, GICD_IPRIORITYR, 8, prio, ACCESS_RMW); +} + +void gic_set_irq_target(int irq, int cpu) +{ + if (irq < 32) + return; + + if (gic_version() =3D=3D 2) { + gic_masked_irq_bits(irq, GICD_ITARGETSR, 8, 1U << cpu, + ACCESS_RMW); + + return; + } + + writeq(cpus[cpu], gicv3_dist_base() + GICD_IROUTER + irq * 8); +} + +void gic_set_irq_group(int irq, int group) +{ + gic_masked_irq_bits(irq, GICD_IGROUPR, 1, group, ACCESS_RMW); +} + +int gic_get_irq_group(int irq) +{ + return gic_masked_irq_bits(irq, GICD_IGROUPR, 1, 0, ACCESS_READ); +} --=20 2.20.1 From MAILER-DAEMON Mon Dec 16 09:45:35 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1igrcr-00059X-Qu for mharc-qemu-arm@gnu.org; Mon, 16 Dec 2019 09:45:33 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:43169) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1igrco-00057W-0k for qemu-arm@nongnu.org; Mon, 16 Dec 2019 09:45:31 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1igrcm-0007iR-IM for qemu-arm@nongnu.org; Mon, 16 Dec 2019 09:45:29 -0500 Received: from mail-oi1-x244.google.com ([2607:f8b0:4864:20::244]:32779) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1igrcm-0007i2-1g for qemu-arm@nongnu.org; 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Mon, 16 Dec 2019 06:45:27 -0800 (PST) MIME-Version: 1.0 References: <1576076260-18659-1-git-send-email-sveith@amazon.de> In-Reply-To: <1576076260-18659-1-git-send-email-sveith@amazon.de> From: Peter Maydell Date: Mon, 16 Dec 2019 14:45:16 +0000 Message-ID: Subject: Re: [PATCH v2 0/6] hw/arm/smmuv3: Correct stream ID and event address handling To: Simon Veith Cc: QEMU Developers , qemu-arm , Eric Auger Content-Type: text/plain; charset="UTF-8" X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::244 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 16 Dec 2019 14:45:32 -0000 On Wed, 11 Dec 2019 at 14:58, Simon Veith wrote: > > While working on the Linux SMMUv3 driver, I noticed a few cases where the QEMU > SMMUv3 behavior relating to stream tables was inconsistent with our hardware. > > Also, when debugging those differences, I found that the errors reported through > the QEMU SMMUv3 event queue contained the address fields in an incorrect > position. > > These patches correct the QEMU SMMUv3 behavior to match the specification (and > the behavior that I observed in our hardware). Linux guests normally will not > notice these issues, but other SMMUv3 driver implementations might. > > Simon Veith (6): > hw/arm/smmuv3: Apply address mask to linear strtab base address > hw/arm/smmuv3: Correct SMMU_BASE_ADDR_MASK value > hw/arm/smmuv3: Check stream IDs against actual table LOG2SIZE > hw/arm/smmuv3: Align stream table base address to table size > hw/arm/smmuv3: Use correct bit positions in EVT_SET_ADDR2 macro > hw/arm/smmuv3: Report F_STE_FETCH fault address in correct word > position Something funny seems to have happened when this series got sent out: patches 1,2,3 are correctly followups to the cover letter, but 4,5,6 are followups to patch 3. This has confused patchew, which thinks the series is incomplete: https://patchew.org/QEMU/1576076260-18659-1-git-send-email-sveith@amazon.de/1576076860-24820-1-git-send-email-sveith@amazon.de/ thanks -- PMM From MAILER-DAEMON Mon Dec 16 09:56:39 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1igrnb-0000Jp-1G for mharc-qemu-arm@gnu.org; Mon, 16 Dec 2019 09:56:39 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:48585) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1igrnY-0000Ji-PE for qemu-arm@nongnu.org; Mon, 16 Dec 2019 09:56:37 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1igrnX-0000NA-Nu for qemu-arm@nongnu.org; Mon, 16 Dec 2019 09:56:36 -0500 Received: from smtp-fw-33001.amazon.com ([207.171.190.10]:27175) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1igrnX-0000Kt-E7; Mon, 16 Dec 2019 09:56:35 -0500 DKIM-Signature: v=1; a=rsa-sha256; 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charset="UTF-8" X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::341 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 16 Dec 2019 15:07:13 -0000 On Thu, 12 Dec 2019 at 17:33, Andrew Jones wrote: > > kvm-no-adjvtime is a KVM specific CPU property and a first of its kind. > To accommodate it we also add kvm_arm_add_vcpu_properties() and a > KVM specific CPU properties description to the CPU features document. > > Signed-off-by: Andrew Jones > --- > docs/arm-cpu-features.rst | 31 ++++++++++++++++++++++++++++++- > hw/arm/virt.c | 8 ++++++++ > include/hw/arm/virt.h | 1 + > target/arm/cpu.c | 2 ++ > target/arm/cpu64.c | 1 + > target/arm/kvm.c | 28 ++++++++++++++++++++++++++++ > target/arm/kvm_arm.h | 11 +++++++++++ > target/arm/monitor.c | 1 + > tests/arm-cpu-features.c | 4 ++++ > 9 files changed, 86 insertions(+), 1 deletion(-) > > diff --git a/docs/arm-cpu-features.rst b/docs/arm-cpu-features.rst > index 1b367e22e16e..641ec9cb8f4a 100644 > --- a/docs/arm-cpu-features.rst > +++ b/docs/arm-cpu-features.rst > @@ -31,7 +31,9 @@ supporting the feature or only supporting the feature under certain > configurations. For example, the `aarch64` CPU feature, which, when > disabled, enables the optional AArch32 CPU feature, is only supported > when using the KVM accelerator and when running on a host CPU type that > -supports the feature. > +supports the feature. While `aarch64` currently only works with KVM, > +it could work with TCG. CPU features that are specific to KVM are > +prefixed with "kvm-" and are described in "KVM VCPU Features". > > CPU Feature Probing > =================== > @@ -171,6 +173,33 @@ disabling many SVE vector lengths would be quite verbose, the `sve` CPU > properties have special semantics (see "SVE CPU Property Parsing > Semantics"). > > +KVM VCPU Features > +================= > + > +KVM VCPU features are CPU features that are specific to KVM, such as > +paravirt features or features that enable CPU virtualization extensions. > +The features' CPU properties are only available when KVM is enabled and > +are named with the prefix "kvm-". KVM VCPU features may be probed, > +enabled, and disabled in the same way as other CPU features. Below is the > +list of KVM VCPU features and their descriptions. > + > + kvm-no-adjvtime When disabled, each time the VM transitions > + back to running state from the paused state the > + VCPU's vitual counter is updated to ensure the "virtual" > + stopped time is not counted. This avoids time > + jumps surprising guest OSes and applications, > + as long as they use the virtual counter for > + timekeeping, but has the side effect of the > + virtual and physical counters diverging. All > + timekeeping based on the virtual counter will > + appear to lag behind any timekeeping that does > + not subtract VM stopped time. The guest may > + resynchronize its virtual counter with other > + time sources as needed. Enabling this KVM VCPU > + feature provides the legacy behavior, which is > + to also count stopped time with the virtual > + counter. This phrasing reads a bit confusingly to me. What I would usually expect is that you get name-of-option Description of what the option does. But here we have name-of-option Long description of the default behaviour, taking many lines and several sentences. Brief note at the end that enabling this feature gives the opposite effect. Especially since the default-behaviour description isn't prefaced with "By default" or similar, it's quite easy to start reading the text assuming it's defining what the option is going to do, only to get to the end and realise that it's defining what the option is *not* going to do... Incidentally, if I understand things correctly, for TCG the behaviour is (and has always been) that VM-stopped time is not counted, because we run the emulated versions of these counters off QEMU_CLOCK_VIRTUAL. So having the KVM default be the same as the TCG default is nicely consistent. thanks -- PMM From MAILER-DAEMON Mon Dec 16 10:14:16 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1igs4e-0001cC-PA for mharc-qemu-arm@gnu.org; Mon, 16 Dec 2019 10:14:16 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:52964) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1igs4c-0001aG-L5 for qemu-arm@nongnu.org; Mon, 16 Dec 2019 10:14:15 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1igs4b-0004Od-BH for qemu-arm@nongnu.org; Mon, 16 Dec 2019 10:14:14 -0500 Received: from mail-ot1-x343.google.com ([2607:f8b0:4864:20::343]:40497) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1igs4b-0004N5-5X for qemu-arm@nongnu.org; Mon, 16 Dec 2019 10:14:13 -0500 Received: by mail-ot1-x343.google.com with SMTP id i15so9585355oto.7 for ; Mon, 16 Dec 2019 07:14:12 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=hcPF0Wp6AEwCHVAM39VUCb0pgGQ7HDSvkvxVAmJmL30=; b=YKWpQCS5Q+0IwhiJNjMyx1PDn8ePF6L6JE8d7WNq9HvJzsMn6LE9T55Ko/VKPRXWNy uR5apWZ3kzy/BU2z7iFFyjAVO/fzTSuZUGzChpJwvGdnhN5kWQZ7/fsZFI6CVa+JZWuI OVtF/5yIXAebQPNohZO6eHmQBIwKo4JeBHFBFpdJmlptu57Fi+cXxE3o9XPNYkaSpZ2s MuFrATi/h/vLje4phVHSnAG7Fp9W5uj22mhOf/o7R8xsWOVw35Carau24CPJFSsyuFfC 2dFsSBPmCET1AX9YkpbOGl+3iu8QmJhk6jL36T4goaEqR2pbusuTxgtOe+rdEtfzWIVA PksQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=hcPF0Wp6AEwCHVAM39VUCb0pgGQ7HDSvkvxVAmJmL30=; b=EUpbH7AZ3wSAINngTZfRppsbRZzjSENxWHmQiwzQkZeqFIMpQJwICMAI4Bgg9Ypmok JRIvcICdIscLU7IMuJoKfGRGy8iCQo5aIe/NLuxivb14Rb5QsRSl0lyXiEw1N/PwWZuX 9F3MdBpWnxenpa4kg1ibbI4wkpu/gHDUnCayX2QS22wBjs+X6xJnew0XV66gfyY5lDJG NHiDWdvxRrIIAzLW9J/rZsr9RA4KR+ksGHqm17Y+EfoA7uFZQDO7BeJpWpTED2/E3LPI I0oHgkFP5PDJ808Iumx8cGG6rforMiOs4Ux3Rd75dFwnmYtv1LFMJ7tRVjS2zsegnl8m ckSA== X-Gm-Message-State: APjAAAXboexjiFO+FZS6R8kvfgcFUteHiBLpuuLRo2ThsLTL08b4Uu3h exJnU+jpPK3m0fQk+nW5aXF2P0Hdi2fUj72sgFdsGg== X-Google-Smtp-Source: APXvYqy6v02O7Jw0i7l5EZivPalXSzw9o8ddDZVmMl6Hqot8eaePEC8Ew+WGs+QK8is/usZC5BuM2qENKXp4iX3MKW4= X-Received: by 2002:a05:6830:2001:: with SMTP id e1mr30757996otp.97.1576509251530; Mon, 16 Dec 2019 07:14:11 -0800 (PST) MIME-Version: 1.0 References: <20191212173320.11610-1-drjones@redhat.com> <20191212173320.11610-4-drjones@redhat.com> In-Reply-To: <20191212173320.11610-4-drjones@redhat.com> From: Peter Maydell Date: Mon, 16 Dec 2019 15:14:00 +0000 Message-ID: Subject: Re: [RFC PATCH v2 3/5] target/arm/kvm: Implement virtual time adjustment To: Andrew Jones Cc: QEMU Developers , qemu-arm , Richard Henderson , Heyi Guo , bijan.mottahedeh@oracle.com, Marc Zyngier , msys.mizuma@gmail.com Content-Type: text/plain; charset="UTF-8" X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::343 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 16 Dec 2019 15:14:15 -0000 On Thu, 12 Dec 2019 at 17:33, Andrew Jones wrote: > > When a VM is stopped (guest is paused) guest virtual time > should stop counting. Otherwise, when the VM is resumed it > will experience time jumps and its kernel may report soft > lockups. Not counting virtual time while the VM is stopped > has the side effect of making the guest's time appear to lag > when compared with real time, and even with time derived from > the physical counter. For this reason, this change, which is > enabled by default, comes with a KVM CPU feature allowing it > to be disabled, restoring legacy behavior. > > This patch only provides the implementation of the virtual > time adjustment. A subsequent patch will provide the CPU > property allowing the change to be enabled and disabled. > > Reported-by: Bijan Mottahedeh > Signed-off-by: Andrew Jones > --- > target/arm/cpu.h | 9 +++++++++ > target/arm/kvm.c | 48 ++++++++++++++++++++++++++++++++++++++++++++ > target/arm/kvm32.c | 3 +++ > target/arm/kvm64.c | 3 +++ > target/arm/kvm_arm.h | 23 +++++++++++++++++++++ > 5 files changed, 86 insertions(+) > > diff --git a/target/arm/cpu.h b/target/arm/cpu.h > index 83a809d4bac4..a79ea74125b3 100644 > --- a/target/arm/cpu.h > +++ b/target/arm/cpu.h > @@ -821,6 +821,15 @@ struct ARMCPU { > /* KVM init features for this CPU */ > uint32_t kvm_init_features[7]; > > + /* KVM CPU features */ > + bool kvm_adjvtime; > + > + /* VCPU virtual counter value used with kvm_adjvtime */ > + uint64_t kvm_vtime; How does this new state interact with migration ? > + > + /* True if the run state is, or transitioning from, RUN_STATE_PAUSED */ > + bool runstate_paused; > + > /* Uniprocessor system with MP extensions */ > bool mp_is_up; > > diff --git a/target/arm/kvm.c b/target/arm/kvm.c > index 5b82cefef608..a55fe7d7aefd 100644 > --- a/target/arm/kvm.c > +++ b/target/arm/kvm.c > @@ -348,6 +348,24 @@ void kvm_arm_register_device(MemoryRegion *mr, uint64_t devid, uint64_t group, > memory_region_ref(kd->mr); > } > > +void kvm_arm_vm_state_change(void *opaque, int running, RunState state) > +{ > + CPUState *cs = opaque; > + ARMCPU *cpu = ARM_CPU(cs); > + > + if (running) { > + if (cpu->kvm_adjvtime && cpu->runstate_paused) { > + kvm_arm_set_virtual_time(cs, cpu->kvm_vtime); > + } > + cpu->runstate_paused = false; > + } else if (state == RUN_STATE_PAUSED) { > + cpu->runstate_paused = true; > + if (cpu->kvm_adjvtime) { > + kvm_arm_get_virtual_time(cs, &cpu->kvm_vtime); > + } > + } > +} How does this interact with the usual register sync to/from KVM (ie kvm_arch_get_registers(), which I think will do a GET_ONE_REG read of the TIMER_CNT register the way it does any other sysreg, inside write_kvmstate_to_list(), plus kvm_arch_set_registers() which does the write back to the kernel in write_list_to_kvmstate()) ? Presumably we want this version to take precedence by the set_virtual_time call happening after the kvm_arch_set_registers, but is this guaranteed ? thanks -- PMM From MAILER-DAEMON Mon Dec 16 10:17:02 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1igs7J-0003Tf-Gx for mharc-qemu-arm@gnu.org; Mon, 16 Dec 2019 10:17:02 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:54193) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1igs7G-0003TB-5A for qemu-arm@nongnu.org; Mon, 16 Dec 2019 10:16:59 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1igs7E-0001Qd-Ry for qemu-arm@nongnu.org; Mon, 16 Dec 2019 10:16:58 -0500 Received: from smtp-fw-9101.amazon.com ([207.171.184.25]:41002) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1igs7E-0001KS-L7; Mon, 16 Dec 2019 10:16:56 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amazon.de; i=@amazon.de; q=dns/txt; s=amazon201209; t=1576509417; x=1608045417; h=from:to:cc:subject:date:message-id; bh=v4g8z2qawcZIAo36aaIgjbmv/2+FuGBGNZSCoPqMp7I=; b=eanjws3FCdaf/iNuJine+az7Yy9gKUfZqfdRSuUx/ltX0HnKBPOvU4A7 vtE6bqpGHlFmoO/Clwrr7v5bEi3ImrhdqUrm+9v6jC2qQB9+AnkguLpnI WoGGNkEm/fIC5A28RcGtT1eo+D5sHKmDTRfbBhnyLyBkbz+z5O3gf9aHx M=; IronPort-SDR: D9EMSQn3Q0b/DY1KDgHleuWVth9wiiJEcGZ1hxYEYLvZzVt8HsRusqPSGasQHL7JYqUrvyX18f 30DpgP7HYvzQ== X-IronPort-AV: E=Sophos;i="5.69,322,1571702400"; d="scan'208";a="5381324" Received: from sea32-co-svc-lb4-vlan3.sea.corp.amazon.com (HELO email-inbound-relay-2c-4e7c8266.us-west-2.amazon.com) ([10.47.23.38]) by smtp-border-fw-out-9101.sea19.amazon.com with ESMTP; 16 Dec 2019 15:16:42 +0000 Received: from sveith-desktop.aka.corp.amazon.com (pdx2-ws-svc-lb17-vlan3.amazon.com [10.247.140.70]) by email-inbound-relay-2c-4e7c8266.us-west-2.amazon.com (Postfix) with ESMTPS id 7A5DFA2057; Mon, 16 Dec 2019 15:16:41 +0000 (UTC) Received: from sveith-desktop.aka.corp.amazon.com (localhost [127.0.0.1]) by sveith-desktop.aka.corp.amazon.com (8.15.2/8.15.2/Debian-3) with ESMTP id xBGFGcwp013847; Mon, 16 Dec 2019 16:16:39 +0100 Received: (from sveith@localhost) by sveith-desktop.aka.corp.amazon.com (8.15.2/8.15.2/Submit) id xBGFGcei013845; Mon, 16 Dec 2019 16:16:38 +0100 From: Simon Veith To: qemu-devel@nongnu.org, qemu-arm@nongnu.org Cc: Simon Veith Subject: [PATCH v3 0/6] hw/arm/smmuv3: Correct stream ID and event address handling Date: Mon, 16 Dec 2019 16:15:06 +0100 Message-Id: <1576509312-13083-1-git-send-email-sveith@amazon.de> X-Mailer: git-send-email 2.7.4 Precedence: Bulk X-detected-operating-system: by eggs.gnu.org: FreeBSD 9.x [fuzzy] X-Received-From: 207.171.184.25 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 16 Dec 2019 15:16:59 -0000 While working on the Linux SMMUv3 driver, I noticed a few cases where the QEMU SMMUv3 behavior relating to stream tables was inconsistent with our hardware. Also, when debugging those differences, I found that the errors reported through the QEMU SMMUv3 event queue contained the address fields in an incorrect position. These patches correct the QEMU SMMUv3 behavior to match the specification (and the behavior that I observed in our hardware). Linux guests normally will not notice these issues, but other SMMUv3 driver implementations might. Changes in v2: * New patch "hw/arm/smmuv3: Correct SMMU_BASE_ADDR_MASK value" added * Updated patch "hw/arm/smmuv3: Check stream IDs against actual table LOG2SIZE" * Updated patch "hw/arm/smmuv3: Align stream table base address to table size" Changes in v3: * No changes, but sending again to correct a patch submission mishap that confused Patchew Simon Veith (6): hw/arm/smmuv3: Apply address mask to linear strtab base address hw/arm/smmuv3: Correct SMMU_BASE_ADDR_MASK value hw/arm/smmuv3: Check stream IDs against actual table LOG2SIZE hw/arm/smmuv3: Align stream table base address to table size hw/arm/smmuv3: Use correct bit positions in EVT_SET_ADDR2 macro hw/arm/smmuv3: Report F_STE_FETCH fault address in correct word position hw/arm/smmuv3-internal.h | 6 +++--- hw/arm/smmuv3.c | 28 +++++++++++++++++++++------- 2 files changed, 24 insertions(+), 10 deletions(-) -- 2.7.4 From MAILER-DAEMON Mon Dec 16 10:17:02 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1igs7K-0003Tw-Gr for mharc-qemu-arm@gnu.org; Mon, 16 Dec 2019 10:17:02 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:54192) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1igs7G-0003TA-5g for qemu-arm@nongnu.org; Mon, 16 Dec 2019 10:16:59 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1igs7E-0001QT-QC for qemu-arm@nongnu.org; Mon, 16 Dec 2019 10:16:58 -0500 Received: from smtp-fw-6002.amazon.com ([52.95.49.90]:18037) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1igs7E-0001KT-Ia; Mon, 16 Dec 2019 10:16:56 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amazon.de; i=@amazon.de; q=dns/txt; s=amazon201209; t=1576509416; x=1608045416; h=from:to:cc:subject:date:message-id:in-reply-to: references; bh=mVMZNzfGgCZy2rnEt7SIpbodq72YKWuf3Om7HpAHf2g=; b=seMttDmuf556S4JhsB25HzawlXSy71DW80BU9CQ2+zTK33m7cVNsWiYw AaqEZM++YcNyGD41w4uzPBi28z23J0SEEjvnEYuMkFukGe+b6TsbMEGff RsMes+IRC/GlMQ6MXQ1zGCYml8VRvyQSB8LDrHxUs2K3omHAwB2lA9gYB Q=; IronPort-SDR: Td7t4XrxG8vLi7kFqoN91DaZsotrP8zKsf3WW3ib3YIHRhFtHtt3iAcSY4kZbkeH6//wYfi7r9 aLRjdmhmR+Bg== X-IronPort-AV: E=Sophos;i="5.69,322,1571702400"; d="scan'208";a="7831631" Received: from iad6-co-svc-p1-lb1-vlan3.amazon.com (HELO email-inbound-relay-2a-538b0bfb.us-west-2.amazon.com) ([10.124.125.6]) by smtp-border-fw-out-6002.iad6.amazon.com with ESMTP; 16 Dec 2019 15:16:53 +0000 Received: from sveith-desktop.aka.corp.amazon.com (pdx2-ws-svc-lb17-vlan2.amazon.com [10.247.140.66]) by email-inbound-relay-2a-538b0bfb.us-west-2.amazon.com (Postfix) with ESMTPS id 6CCD1A262A; Mon, 16 Dec 2019 15:16:52 +0000 (UTC) Received: from sveith-desktop.aka.corp.amazon.com (localhost [127.0.0.1]) by sveith-desktop.aka.corp.amazon.com (8.15.2/8.15.2/Debian-3) with ESMTP id xBGFGolE013973; Mon, 16 Dec 2019 16:16:50 +0100 Received: (from sveith@localhost) by sveith-desktop.aka.corp.amazon.com (8.15.2/8.15.2/Submit) id xBGFGn2g013944; Mon, 16 Dec 2019 16:16:49 +0100 From: Simon Veith To: qemu-devel@nongnu.org, qemu-arm@nongnu.org Cc: Simon Veith , Eric Auger Subject: [PATCH v3 2/6] hw/arm/smmuv3: Correct SMMU_BASE_ADDR_MASK value Date: Mon, 16 Dec 2019 16:15:08 +0100 Message-Id: <1576509312-13083-3-git-send-email-sveith@amazon.de> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1576509312-13083-1-git-send-email-sveith@amazon.de> References: <1576509312-13083-1-git-send-email-sveith@amazon.de> Precedence: Bulk X-detected-operating-system: by eggs.gnu.org: FreeBSD 9.x [fuzzy] X-Received-From: 52.95.49.90 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 16 Dec 2019 15:16:59 -0000 There are two issues with the current value of SMMU_BASE_ADDR_MASK: - At the lower end, we are clearing bits [4:0]. Per the SMMUv3 spec, we should also be treating bit 5 as zero in the base address. - At the upper end, we are clearing bits [63:48]. Per the SMMUv3 spec, only bits [63:52] must be explicitly treated as zero. Update the SMMU_BASE_ADDR_MASK value to mask out bits [63:52] and [5:0]. ref. ARM IHI 0070C, section 6.3.23. Signed-off-by: Simon Veith Cc: Eric Auger Cc: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org --- hw/arm/smmuv3-internal.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/arm/smmuv3-internal.h b/hw/arm/smmuv3-internal.h index d190181..042b435 100644 --- a/hw/arm/smmuv3-internal.h +++ b/hw/arm/smmuv3-internal.h @@ -99,7 +99,7 @@ REG32(GERROR_IRQ_CFG2, 0x74) #define A_STRTAB_BASE 0x80 /* 64b */ -#define SMMU_BASE_ADDR_MASK 0xffffffffffe0 +#define SMMU_BASE_ADDR_MASK 0xfffffffffffc0 REG32(STRTAB_BASE_CFG, 0x88) FIELD(STRTAB_BASE_CFG, FMT, 16, 2) -- 2.7.4 From MAILER-DAEMON Mon Dec 16 10:17:08 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1igs7Q-0003as-Le for mharc-qemu-arm@gnu.org; Mon, 16 Dec 2019 10:17:08 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:54271) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1igs7N-0003Wc-ND for qemu-arm@nongnu.org; Mon, 16 Dec 2019 10:17:06 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1igs7M-0001Za-M6 for qemu-arm@nongnu.org; Mon, 16 Dec 2019 10:17:05 -0500 Received: from smtp-fw-9102.amazon.com ([207.171.184.29]:58507) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1igs7M-0001X4-BE; Mon, 16 Dec 2019 10:17:04 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amazon.de; i=@amazon.de; q=dns/txt; s=amazon201209; t=1576509424; x=1608045424; h=from:to:cc:subject:date:message-id:in-reply-to: references; bh=PCOnbhJypslF5hM47QeKN1c0yopkDWzpKcTM5nMU8Xo=; b=JQJA9+u5KO1EVQ97mBzLioreIw1ZHq4WCHY6dgS/hJIhEE12kEikGV1+ KN3cl16LGn9VI+HCEZL/JZU+76smRcOB8sMQeMOvyc4ontaCWBCqkquXt csrydVDtgnsiB3qNKlT64xj6qfDl4s89WprFn+AkH4bpZZsQ4Nch0lZtM Y=; IronPort-SDR: 6xqwswH05mbkLO3HeKVn+kdonjZ3btRLADrYMNbSZTLnQl9BRVmgM4U6N92XGWUObfdsPZHebY fsmvPnGVKmZA== X-IronPort-AV: E=Sophos;i="5.69,322,1571702400"; d="scan'208";a="13787967" Received: from sea32-co-svc-lb4-vlan3.sea.corp.amazon.com (HELO email-inbound-relay-1e-303d0b0e.us-east-1.amazon.com) ([10.47.23.38]) by smtp-border-fw-out-9102.sea19.amazon.com with ESMTP; 16 Dec 2019 15:17:04 +0000 Received: from sveith-desktop.aka.corp.amazon.com (iad7-ws-svc-lb50-vlan3.amazon.com [10.0.93.214]) by email-inbound-relay-1e-303d0b0e.us-east-1.amazon.com (Postfix) with ESMTPS id F4185A1FE4; Mon, 16 Dec 2019 15:17:01 +0000 (UTC) Received: from sveith-desktop.aka.corp.amazon.com (localhost [127.0.0.1]) by sveith-desktop.aka.corp.amazon.com (8.15.2/8.15.2/Debian-3) with ESMTP id xBGFGxjA014019; Mon, 16 Dec 2019 16:16:59 +0100 Received: (from sveith@localhost) by sveith-desktop.aka.corp.amazon.com (8.15.2/8.15.2/Submit) id xBGFGwne014013; Mon, 16 Dec 2019 16:16:58 +0100 From: Simon Veith To: qemu-devel@nongnu.org, qemu-arm@nongnu.org Cc: Simon Veith , Eric Auger Subject: [PATCH v3 3/6] hw/arm/smmuv3: Check stream IDs against actual table LOG2SIZE Date: Mon, 16 Dec 2019 16:15:09 +0100 Message-Id: <1576509312-13083-4-git-send-email-sveith@amazon.de> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1576509312-13083-1-git-send-email-sveith@amazon.de> References: <1576509312-13083-1-git-send-email-sveith@amazon.de> Precedence: Bulk X-detected-operating-system: by eggs.gnu.org: FreeBSD 9.x [fuzzy] X-Received-From: 207.171.184.29 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 16 Dec 2019 15:17:07 -0000 When checking whether a stream ID is in range of the stream table, we have so far been only checking it against our implementation limit (SMMU_IDR1_SIDSIZE). However, the guest can program the STRTAB_BASE_CFG.LOG2SIZE field to a size that is smaller than this limit. Check the stream ID against this limit as well to match the hardware behavior of raising C_BAD_STREAMID events in case the limit is exceeded. Also, ensure that we do not go one entry beyond the end of the table by checking that its index is strictly smaller than the table size. ref. ARM IHI 0070C, section 6.3.24. Signed-off-by: Simon Veith Cc: Eric Auger Cc: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org --- Changed in v2: * Also check that stream ID is strictly lower than the table size hw/arm/smmuv3.c | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c index eef9a18..727558b 100644 --- a/hw/arm/smmuv3.c +++ b/hw/arm/smmuv3.c @@ -377,11 +377,15 @@ static int smmu_find_ste(SMMUv3State *s, uint32_t sid, STE *ste, SMMUEventInfo *event) { dma_addr_t addr; + uint32_t log2size; int ret; trace_smmuv3_find_ste(sid, s->features, s->sid_split); - /* Check SID range */ - if (sid > (1 << SMMU_IDR1_SIDSIZE)) { + log2size = FIELD_EX32(s->strtab_base_cfg, STRTAB_BASE_CFG, LOG2SIZE); + /* + * Check SID range against both guest-configured and implementation limits + */ + if (sid >= (1 << MIN(log2size, SMMU_IDR1_SIDSIZE))) { event->type = SMMU_EVT_C_BAD_STREAMID; return -EINVAL; } -- 2.7.4 From MAILER-DAEMON Mon Dec 16 10:17:09 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1igs7Q-0003bF-To for mharc-qemu-arm@gnu.org; Mon, 16 Dec 2019 10:17:08 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:54260) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1igs7M-0003VS-V5 for qemu-arm@nongnu.org; Mon, 16 Dec 2019 10:17:05 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1igs7L-0001YA-VR for qemu-arm@nongnu.org; Mon, 16 Dec 2019 10:17:04 -0500 Received: from smtp-fw-9102.amazon.com ([207.171.184.29]:58507) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1igs7L-0001X4-NW; Mon, 16 Dec 2019 10:17:03 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amazon.de; i=@amazon.de; q=dns/txt; s=amazon201209; t=1576509424; x=1608045424; h=from:to:cc:subject:date:message-id:in-reply-to: references; bh=syWV6RethZ9zkiIkM27Et4g5OSvaauBfpbT1hVu+9aY=; b=p2UuQMvElHSlnLKSkedp7iu6zc1Te87fsWnxqjSJq9H+x2KqHJSNVQLp 1JeFevw+OrcFM9h1uslLZjPRWEgTqws5XlnEXt0i7TRTCzRVLOhH2qwry bw0BbR9R0PpbFmn3nDQCEsfh7IaC9sOT38z7RAe2/EvfZdlHIOBKnEq2q E=; IronPort-SDR: d2aUp2IqMXXURcCZGkgJ6eC2IDAbm4psYZDe8xXWk8OubI7jUG94fqjYgRQRkm4r5ScrAmXpHI U33CvYSon9hw== X-IronPort-AV: E=Sophos;i="5.69,322,1571702400"; d="scan'208";a="13787925" Received: from sea32-co-svc-lb4-vlan3.sea.corp.amazon.com (HELO email-inbound-relay-1e-27fb8269.us-east-1.amazon.com) ([10.47.23.38]) by smtp-border-fw-out-9102.sea19.amazon.com with ESMTP; 16 Dec 2019 15:16:51 +0000 Received: from sveith-desktop.aka.corp.amazon.com (iad7-ws-svc-lb50-vlan3.amazon.com [10.0.93.214]) by email-inbound-relay-1e-27fb8269.us-east-1.amazon.com (Postfix) with ESMTPS id BBA31A1F8B; Mon, 16 Dec 2019 15:16:48 +0000 (UTC) Received: from sveith-desktop.aka.corp.amazon.com (localhost [127.0.0.1]) by sveith-desktop.aka.corp.amazon.com (8.15.2/8.15.2/Debian-3) with ESMTP id xBGFGkar013914; Mon, 16 Dec 2019 16:16:46 +0100 Received: (from sveith@localhost) by sveith-desktop.aka.corp.amazon.com (8.15.2/8.15.2/Submit) id xBGFGjQT013913; Mon, 16 Dec 2019 16:16:45 +0100 From: Simon Veith To: qemu-devel@nongnu.org, qemu-arm@nongnu.org Cc: Simon Veith , Eric Auger Subject: [PATCH v3 1/6] hw/arm/smmuv3: Apply address mask to linear strtab base address Date: Mon, 16 Dec 2019 16:15:07 +0100 Message-Id: <1576509312-13083-2-git-send-email-sveith@amazon.de> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1576509312-13083-1-git-send-email-sveith@amazon.de> References: <1576509312-13083-1-git-send-email-sveith@amazon.de> Precedence: Bulk X-detected-operating-system: by eggs.gnu.org: FreeBSD 9.x [fuzzy] X-Received-From: 207.171.184.29 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 16 Dec 2019 15:17:07 -0000 In the SMMU_STRTAB_BASE register, the stream table base address only occupies bits [51:6]. Other bits, such as RA (bit [62]), must be masked out to obtain the base address. The branch for 2-level stream tables correctly applies this mask by way of SMMU_BASE_ADDR_MASK, but the one for linear stream tables does not. Apply the missing mask in that case as well so that the correct stream base address is used by guests which configure a linear stream table. Linux guests are unaffected by this change because they choose a 2-level stream table layout for the QEMU SMMUv3, based on the size of its stream ID space. ref. ARM IHI 0070C, section 6.3.23. Signed-off-by: Simon Veith Cc: Eric Auger Cc: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Acked-by: Eric Auger --- hw/arm/smmuv3.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c index e2fbb83..eef9a18 100644 --- a/hw/arm/smmuv3.c +++ b/hw/arm/smmuv3.c @@ -429,7 +429,7 @@ static int smmu_find_ste(SMMUv3State *s, uint32_t sid, STE *ste, } addr = l2ptr + l2_ste_offset * sizeof(*ste); } else { - addr = s->strtab_base + sid * sizeof(*ste); + addr = (s->strtab_base & SMMU_BASE_ADDR_MASK) + sid * sizeof(*ste); } if (smmu_get_ste(s, addr, ste, event)) { -- 2.7.4 From MAILER-DAEMON Mon Dec 16 10:17:21 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1igs7d-0003rW-Cj for mharc-qemu-arm@gnu.org; Mon, 16 Dec 2019 10:17:21 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:54363) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1igs7Z-0003ly-6W for qemu-arm@nongnu.org; Mon, 16 Dec 2019 10:17:18 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1igs7Y-0001lq-76 for qemu-arm@nongnu.org; Mon, 16 Dec 2019 10:17:17 -0500 Received: from smtp-fw-6001.amazon.com ([52.95.48.154]:28350) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1igs7Y-0001l9-1o; Mon, 16 Dec 2019 10:17:16 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amazon.de; i=@amazon.de; q=dns/txt; s=amazon201209; t=1576509437; x=1608045437; h=from:to:cc:subject:date:message-id:in-reply-to: references; bh=DnWdil9M/KHhlCYcqIHDhxnPOJB7mXEYpBcWYuPCZHo=; b=ZjxCzYM84JfFSa9Z9sQVZU8v82yo+3mc/KYDf/dWicJneZqF6m7OCMLM i+a0bM0xCBKERFwoekgt3ujBOPS1Ihp8jf+5C3bQwX04CBUDm32Zh7lzW L/1x23CX6GEuGdvREjVSNeaGVl4t2XHXhkqIK7RVHvcMRqPpqqxQ+g/9f 4=; IronPort-SDR: 7M0g3OtvPRRWfh9g4zkiGG3kZd7aWHFvz0OntyTUBMYpn+YRpnOA6OYJejATP9M7iTDGDeUOGx tzlI5LgVq5TQ== X-IronPort-AV: E=Sophos;i="5.69,322,1571702400"; d="scan'208";a="9275759" Received: from iad6-co-svc-p1-lb1-vlan3.amazon.com (HELO email-inbound-relay-2a-538b0bfb.us-west-2.amazon.com) ([10.124.125.6]) by smtp-border-fw-out-6001.iad6.amazon.com with ESMTP; 16 Dec 2019 15:17:15 +0000 Received: from sveith-desktop.aka.corp.amazon.com (pdx2-ws-svc-lb17-vlan2.amazon.com [10.247.140.66]) by email-inbound-relay-2a-538b0bfb.us-west-2.amazon.com (Postfix) with ESMTPS id 42F47A2651; Mon, 16 Dec 2019 15:17:13 +0000 (UTC) Received: from sveith-desktop.aka.corp.amazon.com (localhost [127.0.0.1]) by sveith-desktop.aka.corp.amazon.com (8.15.2/8.15.2/Debian-3) with ESMTP id xBGFHBbE014128; Mon, 16 Dec 2019 16:17:11 +0100 Received: (from sveith@localhost) by sveith-desktop.aka.corp.amazon.com (8.15.2/8.15.2/Submit) id xBGFHAp4014106; Mon, 16 Dec 2019 16:17:10 +0100 From: Simon Veith To: qemu-devel@nongnu.org, qemu-arm@nongnu.org Cc: Simon Veith , Eric Auger Subject: [PATCH v3 5/6] hw/arm/smmuv3: Use correct bit positions in EVT_SET_ADDR2 macro Date: Mon, 16 Dec 2019 16:15:11 +0100 Message-Id: <1576509312-13083-6-git-send-email-sveith@amazon.de> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1576509312-13083-1-git-send-email-sveith@amazon.de> References: <1576509312-13083-1-git-send-email-sveith@amazon.de> Precedence: Bulk X-detected-operating-system: by eggs.gnu.org: FreeBSD 9.x [fuzzy] X-Received-From: 52.95.48.154 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 16 Dec 2019 15:17:19 -0000 The bit offsets in the EVT_SET_ADDR2 macro do not match those specified in the ARM SMMUv3 Architecture Specification. In all events that use this macro, e.g. F_WALK_EABT, the faulting fetch address or IPA actually occupies the 32-bit words 6 and 7 in the event record contiguously, with the upper and lower unused bits clear due to alignment or maximum supported address bits. How many bits are clear depends on the individual event type. Update the macro to write to the correct words in the event record so that guest drivers can obtain accurate address information on events. ref. ARM IHI 0070C, sections 7.3.12 through 7.3.16. Signed-off-by: Simon Veith Cc: Eric Auger Cc: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Acked-by: Eric Auger --- hw/arm/smmuv3-internal.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/hw/arm/smmuv3-internal.h b/hw/arm/smmuv3-internal.h index 042b435..4112394 100644 --- a/hw/arm/smmuv3-internal.h +++ b/hw/arm/smmuv3-internal.h @@ -461,8 +461,8 @@ typedef struct SMMUEventInfo { } while (0) #define EVT_SET_ADDR2(x, addr) \ do { \ - (x)->word[7] = deposit32((x)->word[7], 3, 29, addr >> 16); \ - (x)->word[7] = deposit32((x)->word[7], 0, 16, addr & 0xffff);\ + (x)->word[7] = (uint32_t)(addr >> 32); \ + (x)->word[6] = (uint32_t)(addr & 0xffffffff); \ } while (0) void smmuv3_record_event(SMMUv3State *s, SMMUEventInfo *event); -- 2.7.4 From MAILER-DAEMON Mon Dec 16 10:17:24 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1igs7g-0003vI-4u for mharc-qemu-arm@gnu.org; Mon, 16 Dec 2019 10:17:24 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:54420) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1igs7c-0003qI-CU for qemu-arm@nongnu.org; Mon, 16 Dec 2019 10:17:21 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1igs7b-0001sf-85 for qemu-arm@nongnu.org; Mon, 16 Dec 2019 10:17:20 -0500 Received: from smtp-fw-33001.amazon.com ([207.171.190.10]:53953) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1igs7b-0001qs-12; Mon, 16 Dec 2019 10:17:19 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amazon.de; i=@amazon.de; q=dns/txt; s=amazon201209; t=1576509439; x=1608045439; h=from:to:cc:subject:date:message-id:in-reply-to: references; bh=tRSad7WoTFOponF+G6UnpmzO4ecidPjoO2ZvHdSbdBA=; b=fewE8YntJ/FWHnvYXTIByiEhniOkO0YmXv7icz6MzYmHYElgL1Vc72vm BvoMJrHD9k+p4vy0lSKLN2NqAH4GpLZHQ8HXWZC1RV6x/foeQZ41Pe+Wz iYBeKdToncyL/CidOzjXPwsjATn41ttlJt/SNwPW4SUHsP/CqUErRHLTP 4=; IronPort-SDR: mnslBslxYJbZJhEZ8OcfCdpE+K3DZv88iBICrIRMc+gsWHv2RpDWm9BKNMwj/dAT/NS2JtydBw dcbjh0+KcVDg== X-IronPort-AV: E=Sophos;i="5.69,322,1571702400"; d="scan'208";a="15161854" Received: from sea32-co-svc-lb4-vlan3.sea.corp.amazon.com (HELO email-inbound-relay-2a-90c42d1d.us-west-2.amazon.com) ([10.47.23.38]) by smtp-border-fw-out-33001.sea14.amazon.com with ESMTP; 16 Dec 2019 15:17:08 +0000 Received: from sveith-desktop.aka.corp.amazon.com (pdx2-ws-svc-lb17-vlan2.amazon.com [10.247.140.66]) by email-inbound-relay-2a-90c42d1d.us-west-2.amazon.com (Postfix) with ESMTPS id CE46AA1F39; Mon, 16 Dec 2019 15:17:06 +0000 (UTC) Received: from sveith-desktop.aka.corp.amazon.com (localhost [127.0.0.1]) by sveith-desktop.aka.corp.amazon.com (8.15.2/8.15.2/Debian-3) with ESMTP id xBGFH4NR014072; Mon, 16 Dec 2019 16:17:04 +0100 Received: (from sveith@localhost) by sveith-desktop.aka.corp.amazon.com (8.15.2/8.15.2/Submit) id xBGFH3iK014070; Mon, 16 Dec 2019 16:17:03 +0100 From: Simon Veith To: qemu-devel@nongnu.org, qemu-arm@nongnu.org Cc: Simon Veith , Eric Auger Subject: [PATCH v3 4/6] hw/arm/smmuv3: Align stream table base address to table size Date: Mon, 16 Dec 2019 16:15:10 +0100 Message-Id: <1576509312-13083-5-git-send-email-sveith@amazon.de> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1576509312-13083-1-git-send-email-sveith@amazon.de> References: <1576509312-13083-1-git-send-email-sveith@amazon.de> Precedence: Bulk X-detected-operating-system: by eggs.gnu.org: FreeBSD 9.x [fuzzy] X-Received-From: 207.171.190.10 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 16 Dec 2019 15:17:23 -0000 Per the specification, and as observed in hardware, the SMMUv3 aligns the SMMU_STRTAB_BASE address to the size of the table by masking out the respective least significant bits in the ADDR field. Apply this masking logic to our smmu_find_ste() lookup function per the specification. ref. ARM IHI 0070C, section 6.3.23. Signed-off-by: Simon Veith Cc: Eric Auger Cc: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org --- Changed in v2: * Now using MAKE_64BIT_MASK() * Eliminated unnecessary branches by using MAX() * Removed unnecessary range check against DMA_ADDR_BITS hw/arm/smmuv3.c | 18 ++++++++++++++---- 1 file changed, 14 insertions(+), 4 deletions(-) diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c index 727558b..31ac3ca 100644 --- a/hw/arm/smmuv3.c +++ b/hw/arm/smmuv3.c @@ -376,8 +376,9 @@ bad_ste: static int smmu_find_ste(SMMUv3State *s, uint32_t sid, STE *ste, SMMUEventInfo *event) { - dma_addr_t addr; + dma_addr_t addr, strtab_base; uint32_t log2size; + int strtab_size_shift; int ret; trace_smmuv3_find_ste(sid, s->features, s->sid_split); @@ -391,10 +392,16 @@ static int smmu_find_ste(SMMUv3State *s, uint32_t sid, STE *ste, } if (s->features & SMMU_FEATURE_2LVL_STE) { int l1_ste_offset, l2_ste_offset, max_l2_ste, span; - dma_addr_t strtab_base, l1ptr, l2ptr; + dma_addr_t l1ptr, l2ptr; STEDesc l1std; - strtab_base = s->strtab_base & SMMU_BASE_ADDR_MASK; + /* + * Align strtab base address to table size. For this purpose, assume it + * is not bounded by SMMU_IDR1_SIDSIZE. + */ + strtab_size_shift = MAX(5, (int)log2size - s->sid_split - 1 + 3); + strtab_base = s->strtab_base & SMMU_BASE_ADDR_MASK & + ~MAKE_64BIT_MASK(0, strtab_size_shift); l1_ste_offset = sid >> s->sid_split; l2_ste_offset = sid & ((1 << s->sid_split) - 1); l1ptr = (dma_addr_t)(strtab_base + l1_ste_offset * sizeof(l1std)); @@ -433,7 +440,10 @@ static int smmu_find_ste(SMMUv3State *s, uint32_t sid, STE *ste, } addr = l2ptr + l2_ste_offset * sizeof(*ste); } else { - addr = (s->strtab_base & SMMU_BASE_ADDR_MASK) + sid * sizeof(*ste); + strtab_size_shift = log2size + 5; + strtab_base = s->strtab_base & SMMU_BASE_ADDR_MASK & + ~MAKE_64BIT_MASK(0, strtab_size_shift); + addr = strtab_base + sid * sizeof(*ste); } if (smmu_get_ste(s, addr, ste, event)) { -- 2.7.4 From MAILER-DAEMON Mon Dec 16 10:17:25 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1igs7h-0003ww-AZ for mharc-qemu-arm@gnu.org; Mon, 16 Dec 2019 10:17:25 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:54437) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1igs7d-0003rC-5b for qemu-arm@nongnu.org; Mon, 16 Dec 2019 10:17:22 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1igs7c-0001va-2V for qemu-arm@nongnu.org; Mon, 16 Dec 2019 10:17:21 -0500 Received: from smtp-fw-6001.amazon.com ([52.95.48.154]:28350) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1igs7b-0001l9-Tf; Mon, 16 Dec 2019 10:17:20 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amazon.de; i=@amazon.de; q=dns/txt; s=amazon201209; t=1576509440; x=1608045440; h=from:to:cc:subject:date:message-id:in-reply-to: references; bh=Z0g33k0fJJlh3np7I7IZdcyVyzV2EJT6J7A5HaBP1Jc=; b=DdQXvSKhl1V1Io4wkW879gc70VYua6X1AQQX1wvqDzEzaUxgvBtCcym2 +pVKbLx7DUeH78UH38X6XNNjkrB28HAbMlJmgYROPCqnkB9eV3BQBQ/i7 7bfY/5089iyGEjLfgBifrb2h5uOCUZ9Og0WHcGm9uyrztUEqZsckaEgSf I=; IronPort-SDR: fw3ADRrLN+ng2QTpfC/KOk7ikWLls4Hna//RYlheOYRyO2E025gTqCHfcvS2suqr9aiNJiFeDx nUvjaVQR7u+g== X-IronPort-AV: E=Sophos;i="5.69,322,1571702400"; d="scan'208";a="9275773" Received: from iad6-co-svc-p1-lb1-vlan3.amazon.com (HELO email-inbound-relay-2b-5bdc5131.us-west-2.amazon.com) ([10.124.125.6]) by smtp-border-fw-out-6001.iad6.amazon.com with ESMTP; 16 Dec 2019 15:17:20 +0000 Received: from sveith-desktop.aka.corp.amazon.com (pdx2-ws-svc-lb17-vlan2.amazon.com [10.247.140.66]) by email-inbound-relay-2b-5bdc5131.us-west-2.amazon.com (Postfix) with ESMTPS id 3CCE3A2197; Mon, 16 Dec 2019 15:17:18 +0000 (UTC) Received: from sveith-desktop.aka.corp.amazon.com (localhost [127.0.0.1]) by sveith-desktop.aka.corp.amazon.com (8.15.2/8.15.2/Debian-3) with ESMTP id xBGFHGdw014168; Mon, 16 Dec 2019 16:17:16 +0100 Received: (from sveith@localhost) by sveith-desktop.aka.corp.amazon.com (8.15.2/8.15.2/Submit) id xBGFHFLS014143; Mon, 16 Dec 2019 16:17:15 +0100 From: Simon Veith To: qemu-devel@nongnu.org, qemu-arm@nongnu.org Cc: Simon Veith , Eric Auger Subject: [PATCH v3 6/6] hw/arm/smmuv3: Report F_STE_FETCH fault address in correct word position Date: Mon, 16 Dec 2019 16:15:12 +0100 Message-Id: <1576509312-13083-7-git-send-email-sveith@amazon.de> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1576509312-13083-1-git-send-email-sveith@amazon.de> References: <1576509312-13083-1-git-send-email-sveith@amazon.de> Precedence: Bulk X-detected-operating-system: by eggs.gnu.org: FreeBSD 9.x [fuzzy] X-Received-From: 52.95.48.154 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 16 Dec 2019 15:17:23 -0000 The smmuv3_record_event() function that generates the F_STE_FETCH error uses the EVT_SET_ADDR macro to record the fetch address, placing it in 32-bit words 4 and 5. The correct position for this address is in words 6 and 7, per the SMMUv3 Architecture Specification. Update the function to use the EVT_SET_ADDR2 macro instead, which is the macro intended for writing to these words. ref. ARM IHI 0070C, section 7.3.4. Signed-off-by: Simon Veith Cc: Eric Auger Cc: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Acked-by: Eric Auger --- hw/arm/smmuv3.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c index 31ac3ca..8b5f157 100644 --- a/hw/arm/smmuv3.c +++ b/hw/arm/smmuv3.c @@ -172,7 +172,7 @@ void smmuv3_record_event(SMMUv3State *s, SMMUEventInfo *info) case SMMU_EVT_F_STE_FETCH: EVT_SET_SSID(&evt, info->u.f_ste_fetch.ssid); EVT_SET_SSV(&evt, info->u.f_ste_fetch.ssv); - EVT_SET_ADDR(&evt, info->u.f_ste_fetch.addr); + EVT_SET_ADDR2(&evt, info->u.f_ste_fetch.addr); break; case SMMU_EVT_C_BAD_STE: EVT_SET_SSID(&evt, info->u.c_bad_ste.ssid); -- 2.7.4 From MAILER-DAEMON Mon Dec 16 10:34:15 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1igsNz-00084W-MC for mharc-qemu-arm@gnu.org; Mon, 16 Dec 2019 10:34:15 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:59707) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1igsNx-00084K-88 for qemu-arm@nongnu.org; Mon, 16 Dec 2019 10:34:14 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1igsNu-0007bP-SD for qemu-arm@nongnu.org; Mon, 16 Dec 2019 10:34:12 -0500 Received: from mail-oi1-x244.google.com ([2607:f8b0:4864:20::244]:46366) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1igsNu-0007b0-HY for qemu-arm@nongnu.org; Mon, 16 Dec 2019 10:34:10 -0500 Received: by mail-oi1-x244.google.com with SMTP id a124so3577504oii.13 for ; Mon, 16 Dec 2019 07:34:09 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=XlFImKkLeBBCYbNKNKMVNzlOgmpDx8oY5F19MpVJ9X0=; b=ac/8lu9Qp8RqTMui7fWYkg3YW0UzDilHTCt07oFtlDFztpucpEj1EuQyWpkzPlI7xK niV9XXnmznXkYllPsnWsQgLejsr2wfbSNyARJFW0aGJSp6L3OeHK3HW4oVZr43p2oohy qybzctq6hNnsIo4THy/YB0ezl9kDLuGikOkmj+wJ2sf1COWNadr70A/5DhzJpZ1QtOVP Noe36WVdcTh31UmRsyLaO63hupD7Xc7abZcZzn1jmzbDFqDtkSBpbjhcYgT+LnHuYBVv GEo6xSfj6Tmiq7++BPfFtymsONqYTynfgarHzh+KPpdTAypq/FIj5M5NS7h45LFT7ZJC kLrA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=XlFImKkLeBBCYbNKNKMVNzlOgmpDx8oY5F19MpVJ9X0=; b=TcZi9hnH3Lbj1kwbvmGsTRXNUUFIdvCm0xffgHnH6YYNuB0b5Y+z/lorOSzlZy6RfT LtqruMyJCwy9QgvjHs4BMXFY5KuNPAzDoNYKYQc+6f1jbUkT90UR+XgnMB8URZKOjUSP lQuNbmI0/2MdcWZmhcGM1Y8ov/Ngj6q2pwZ8QVlMkU/m6/tLiGgWQ8jzhP1EW5dF2gIW DkhHa+fyclOXZ3iVGJhKjItLGr+ku1DfUoaVOgZyMCPlCkDU3Vby3Kg8L/07Ms7XlOx/ OyAyzIHFlXj69TuWy3/55ngW1Om3xZRxn9xRjwceNO85cgHRiy9ivLEzmaN/zWB6D+1+ otxQ== X-Gm-Message-State: APjAAAWX0+aXWVHLhf4DWoV4meeryMzuEAgSwGz+y2dgFaw8u5TlvVuu bK4BlcITB4gbXbKlKnPpMi07GJ3TtKBc3G6rmGRjXA== X-Google-Smtp-Source: APXvYqx6JSojAgU7E1NxJd/LWb+yfZXK/wnaMHAhqtzpEt1CmfEXgx8tHt8lCEUrWdpnkqz4xQ5qQXDhPeYDWJ60Mmo= X-Received: by 2002:aca:f484:: with SMTP id s126mr9237783oih.48.1576510448904; Mon, 16 Dec 2019 07:34:08 -0800 (PST) MIME-Version: 1.0 References: <20191212173320.11610-1-drjones@redhat.com> In-Reply-To: <20191212173320.11610-1-drjones@redhat.com> From: Peter Maydell Date: Mon, 16 Dec 2019 15:33:57 +0000 Message-ID: Subject: Re: [RFC PATCH v2 0/5] target/arm/kvm: Adjust virtual time To: Andrew Jones Cc: QEMU Developers , qemu-arm , Richard Henderson , Heyi Guo , bijan.mottahedeh@oracle.com, Marc Zyngier , msys.mizuma@gmail.com Content-Type: text/plain; charset="UTF-8" X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::244 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 16 Dec 2019 15:34:14 -0000 On Thu, 12 Dec 2019 at 17:33, Andrew Jones wrote: > Userspace that wants to set KVM_REG_ARM_TIMER_CNT should beware that > the KVM register ID is not correct. This cannot be fixed because it's > UAPI and if the UAPI headers are used then it can't be a problem. > However, if a userspace attempts to create the ID themselves from the > register's specification, then they will get KVM_REG_ARM_TIMER_CVAL > instead, as the _CNT and _CVAL definitions have their register > parameters swapped. So, to be clear, you mean that: (1) the kernel headers say: /* EL0 Virtual Timer Registers */ #define KVM_REG_ARM_TIMER_CTL ARM64_SYS_REG(3, 3, 14, 3, 1) #define KVM_REG_ARM_TIMER_CNT ARM64_SYS_REG(3, 3, 14, 3, 2) #define KVM_REG_ARM_TIMER_CVAL ARM64_SYS_REG(3, 3, 14, 0, 2) (2) some of the RHSes of these are wrong (3) but the kernel internally is using the same 'wrong' value, so userspace also needs to use that value, ie trust the #defined name rather than manufacturing one ? That's awkward. I think it would be worth at least having a kernel patch to add a comment clearly documenting this bug. (This error seems to only be in the 64-bit ABI, not 32-bit.) QEMU does assume that the kernel's ID register values match the hardware for sysregs in some ways -- we use this when we construct our mapping from KVM register IDs as returned by KVM_GET_REG_LIST to QEMU cpreg definitions and thus CPUState struct fields. I *think* that in this case the only visible effect will be that gdbstub will show you the CNT value if you ask it to print the value of the CVAL sysreg. thanks -- PMM From MAILER-DAEMON Mon Dec 16 10:40:32 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1igsU4-0004RW-2y for mharc-qemu-arm@gnu.org; Mon, 16 Dec 2019 10:40:32 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:33942) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1igsU1-0004Ls-TH for qemu-arm@nongnu.org; Mon, 16 Dec 2019 10:40:30 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1igsU0-0002UD-Mt for qemu-arm@nongnu.org; Mon, 16 Dec 2019 10:40:29 -0500 Received: from mail-ot1-x343.google.com ([2607:f8b0:4864:20::343]:44051) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1igsU0-0002TG-EM for qemu-arm@nongnu.org; Mon, 16 Dec 2019 10:40:28 -0500 Received: by mail-ot1-x343.google.com with SMTP id x3so9648983oto.11 for ; Mon, 16 Dec 2019 07:40:28 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=57XV+rnHN3MQjm/YspqhKVtAQ2f35QZqw0JR2xiVzc8=; b=NPeDDWY8ko/vEj1cI6b65AeL6fJIrTh+dpSfrqqgmJJkUWQL+1nKgFjI/jQT3Ecz1c 2mPBUUmMfANPMWKx3eifhA88NOBCSuJtvgR67NYP5m36O1oVUU9fHOPinnJvSa540aJK CPrprBWuJTqR8yp4W8A61dyMcC9Pz7DbTYQnl9X620DzAdqQ24woflvxohgzUi7ze+Qk 5eTncjZV1ldp6swPiqTcSFdYcydeVXu1JnM3PzkA6CCvnyddUKftWTQbB3XH4yvLaFnd ZjTZ29i7HgqGpzTxQ+4PUY2GdT5hoYpipHBOzhg4dSiQaEKwqOCqeMs1y7cPswFSuT8r ys1A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=57XV+rnHN3MQjm/YspqhKVtAQ2f35QZqw0JR2xiVzc8=; b=ug6+yDBOrVzpDnnMngd3+Pa5mBdAdjORKjkzS2BIl3hrL+VQw9o5Uaf3RLN/dmeXzI 4p05V6Q+HTJSAyKq2YOUIqlwDAMCeTbZkdzRWca7c7h89E2b0NxhpYvPqm+9QfQWtHw0 o9ObEJ4jKsM92w1WCT7oW3msea9QY0kDCbOmgqJZxjFkWYng8JTngdyVq+2VyXObtOkR FBIoXSK8Z2H0tKKGGch2QPA2SwVtiU6FgOsSZT1e1AjbawhKBTE6DnFMIdhWx1soTvHP wvbkndCKimdR267kW4lAVU/wGgz5+A7sZAdov+M7A7QdoMF0pZT3VbjKyI7tMGSBsUC5 N+aw== X-Gm-Message-State: APjAAAUnMmHNk57U0IFNTf0Bx0ZR0LcpJGRWyfgsn9KaNxK/YTM6TwkY F3Omj645Ki0vHAtD/xTchuNirdotxkXa440pR0iWLw== X-Google-Smtp-Source: APXvYqxJ7jbu4CQNJtVa9Nx5P2BoDNizYRUY3fx4wg463tL4ttO8B8wQqHRqyT/hjSWtPGPYy+eAkweAlrNFs+isyGU= X-Received: by 2002:a9d:6745:: with SMTP id w5mr30804462otm.221.1576510827498; Mon, 16 Dec 2019 07:40:27 -0800 (PST) MIME-Version: 1.0 References: <20191212173320.11610-1-drjones@redhat.com> <20191212173320.11610-4-drjones@redhat.com> In-Reply-To: From: Peter Maydell Date: Mon, 16 Dec 2019 15:40:16 +0000 Message-ID: Subject: Re: [RFC PATCH v2 3/5] target/arm/kvm: Implement virtual time adjustment To: Andrew Jones Cc: QEMU Developers , qemu-arm , Richard Henderson , Heyi Guo , bijan.mottahedeh@oracle.com, Marc Zyngier , msys.mizuma@gmail.com Content-Type: text/plain; charset="UTF-8" X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::343 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 16 Dec 2019 15:40:31 -0000 On Mon, 16 Dec 2019 at 15:14, Peter Maydell wrote: > How does this interact with the usual register sync to/from > KVM (ie kvm_arch_get_registers(), which I think will do a > GET_ONE_REG read of the TIMER_CNT register the way it does > any other sysreg, inside write_kvmstate_to_list(), plus > kvm_arch_set_registers() which does the write back to the > kernel in write_list_to_kvmstate()) ? Presumably we want this > version to take precedence by the set_virtual_time call > happening after the kvm_arch_set_registers, but is this > guaranteed ? ...you might also want to look at the effects of simply removing the KVM_REG_ARM_TIMER_CNT entry from the 'non_runtime_cpregs[]' array -- in commit 4b7a6bf402bd064 we explicitly stopped reading/writing this register's value to/from the kernel except for inbound migration, and it feels like this patchset is now rolling back that approach, so maybe we should also be (configurably) rolling back some of its implementation rather than just leaving it in place. I note also that the commit message there had a remark about inconsistencies between VCPUs -- is the right thing to handle this per-VM rather than per-VCPU somehow? thanks -- PMM From MAILER-DAEMON Mon Dec 16 10:44:21 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1igsXl-0008Q9-7H for mharc-qemu-arm@gnu.org; Mon, 16 Dec 2019 10:44:21 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:36080) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1igsXi-0008Ma-GT for qemu-arm@nongnu.org; Mon, 16 Dec 2019 10:44:19 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1igsXh-0003Rz-Gq for qemu-arm@nongnu.org; Mon, 16 Dec 2019 10:44:18 -0500 Received: from mail-oi1-x242.google.com ([2607:f8b0:4864:20::242]:40266) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1igsXh-0003QW-Bw for qemu-arm@nongnu.org; Mon, 16 Dec 2019 10:44:17 -0500 Received: by mail-oi1-x242.google.com with SMTP id 6so3635448oix.7 for ; Mon, 16 Dec 2019 07:44:17 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=KpCH6ZwqEOP5jhIVF4FH+hLREz6L24C45jAN2PLFqpA=; b=x0IRJblQ0iBiMkD575D3nz/0svhnHhzPDpNjafxUpqhLw3htp0/aeDRRL9OaLTRzt+ huLwhC1kAfqUzaaYCM48hZlaBIR0uOrbnpABy9+IzEKGwjLGfynqs1jIrwjiBoScCL0e S6WsXsveN6vC3JR9SrkfSUJkPypNW7/kTTxnzsSw2vrH+CxfqEXCJw4AbqXhIPsL333S E7G3rh1cmxvslBHFTa9gKngW8R4z9byK3pz7zrNY9yyCoV/sZ/MNODxNYGfCP8bm+qgS V+66KyHIw29QMCt5OLtaUcf0BETTVFJ+eYqx2AxfJeuz6q+2FUxU9Yh5BT0Xz0xMVzYl F3Tw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=KpCH6ZwqEOP5jhIVF4FH+hLREz6L24C45jAN2PLFqpA=; b=MoAqm8jmgSsmcqmDsvn0AxJWNb9ECttYZqtWQSPxiTske2bs1POqVeqPL3ky9JB3nB D0DTWFRvFeVP/3REGtBPLysZRlxZ7ym3GhwHWOlry/Sj631Dg5Hm4KKVO2H9iB1BsHt0 Z2HnJFo6ouenOjzWAw1QyU2wqs/dEPMgO7/li4frCCZq+OGGjxusoiSBZPi5GO+5YuXg Is0ThqmWv1r8CQe8oCwoRiOxtYq1fTY9d72jg3AnGKiwxlHROPRymrpDRwIatookc53f ogKWHNSWDAo72XMgpFD+JmW1+PUElGv1FpHLi+wDB7TV5PtEOsCjOl3hPVufYWR/lt6a AgNA== X-Gm-Message-State: APjAAAUEyW9UB2R9Xrmi74LpM6K1RNUwzoBG+8246Q69yLsMTCcSx97x 6iY3PVbXZtT+pkvlvOKlQqAKR39MlhW+4Wvld7T+fA== X-Google-Smtp-Source: APXvYqyrPCE7hEFiblr1HO+3t89KPshUIN90ep0vRhKrRSceASwyjOqMZ23O9/EMEnHltmYFwRSq3EbvDd//E2E63aw= X-Received: by 2002:aca:edd5:: with SMTP id l204mr10220024oih.98.1576511056477; Mon, 16 Dec 2019 07:44:16 -0800 (PST) MIME-Version: 1.0 References: <20191212173320.11610-1-drjones@redhat.com> In-Reply-To: From: Peter Maydell Date: Mon, 16 Dec 2019 15:44:05 +0000 Message-ID: Subject: Re: [RFC PATCH v2 0/5] target/arm/kvm: Adjust virtual time To: Andrew Jones Cc: QEMU Developers , qemu-arm , Richard Henderson , Heyi Guo , bijan.mottahedeh@oracle.com, Marc Zyngier , msys.mizuma@gmail.com Content-Type: text/plain; charset="UTF-8" X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::242 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 16 Dec 2019 15:44:19 -0000 On Mon, 16 Dec 2019 at 15:33, Peter Maydell wrote: > So, to be clear, you mean that: > > (1) the kernel headers say: > > /* EL0 Virtual Timer Registers */ > #define KVM_REG_ARM_TIMER_CTL ARM64_SYS_REG(3, 3, 14, 3, 1) > #define KVM_REG_ARM_TIMER_CNT ARM64_SYS_REG(3, 3, 14, 3, 2) > #define KVM_REG_ARM_TIMER_CVAL ARM64_SYS_REG(3, 3, 14, 0, 2) > > (2) some of the RHSes of these are wrong > > (3) but the kernel internally is using the same 'wrong' value, so > userspace also needs to use that value, ie trust the #defined name > rather than manufacturing one ? > > That's awkward. I think it would be worth at least having a kernel > patch to add a comment clearly documenting this bug. > > (This error seems to only be in the 64-bit ABI, not 32-bit.) > > QEMU does assume that the kernel's ID register values match > the hardware for sysregs in some ways -- we use this when we > construct our mapping from KVM register IDs as returned by > KVM_GET_REG_LIST to QEMU cpreg definitions and thus CPUState > struct fields. I *think* that in this case the only visible > effect will be that gdbstub will show you the CNT value > if you ask it to print the value of the CVAL sysreg. ...perhaps we should work around this kernel bug in the kvm_to_cpreg_id() and cpreg_to_kvm_id() functions. (Need to think through/test whether that would break migration.) thanks -- PMM From MAILER-DAEMON Mon Dec 16 11:18:38 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1igt4v-00045y-V6 for mharc-qemu-arm@gnu.org; Mon, 16 Dec 2019 11:18:38 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:50902) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1igt4p-0003xA-UF for qemu-arm@nongnu.org; Mon, 16 Dec 2019 11:18:35 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1igt4o-0007sz-Ts for qemu-arm@nongnu.org; Mon, 16 Dec 2019 11:18:31 -0500 Received: from inca-roads.misterjones.org ([213.251.177.50]:50356) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1igt4l-0007gz-JQ; Mon, 16 Dec 2019 11:18:27 -0500 Received: from www-data by cheepnis.misterjones.org with local (Exim 4.80) (envelope-from ) id 1igt4h-0003D3-8K; Mon, 16 Dec 2019 17:18:23 +0100 To: Peter Maydell Subject: Re: [RFC PATCH v2 0/5] target/arm/kvm: Adjust virtual time X-PHP-Originating-Script: 0:main.inc MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Date: Mon, 16 Dec 2019 16:18:23 +0000 From: Marc Zyngier Cc: Andrew Jones , QEMU Developers , qemu-arm , Richard Henderson , Heyi Guo , , In-Reply-To: References: <20191212173320.11610-1-drjones@redhat.com> Message-ID: <4cb9bcfd47dff57c9ae6bb92bae87589@www.loen.fr> X-Sender: maz@kernel.org User-Agent: Roundcube Webmail/0.7.2 X-SA-Exim-Connect-IP: X-SA-Exim-Rcpt-To: peter.maydell@linaro.org, drjones@redhat.com, qemu-devel@nongnu.org, qemu-arm@nongnu.org, richard.henderson@linaro.org, guoheyi@huawei.com, bijan.mottahedeh@oracle.com, msys.mizuma@gmail.com X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on cheepnis.misterjones.org); SAEximRunCond expanded to false X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [fuzzy] X-Received-From: 213.251.177.50 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 16 Dec 2019 16:18:36 -0000 On 2019-12-16 15:33, Peter Maydell wrote: > On Thu, 12 Dec 2019 at 17:33, Andrew Jones > wrote: > >> Userspace that wants to set KVM_REG_ARM_TIMER_CNT should beware that >> the KVM register ID is not correct. This cannot be fixed because >> it's >> UAPI and if the UAPI headers are used then it can't be a problem. >> However, if a userspace attempts to create the ID themselves from >> the >> register's specification, then they will get KVM_REG_ARM_TIMER_CVAL >> instead, as the _CNT and _CVAL definitions have their register >> parameters swapped. > > So, to be clear, you mean that: > > (1) the kernel headers say: > > /* EL0 Virtual Timer Registers */ > #define KVM_REG_ARM_TIMER_CTL ARM64_SYS_REG(3, 3, 14, 3, 1) > #define KVM_REG_ARM_TIMER_CNT ARM64_SYS_REG(3, 3, 14, 3, 2) > #define KVM_REG_ARM_TIMER_CVAL ARM64_SYS_REG(3, 3, 14, 0, 2) > > (2) some of the RHSes of these are wrong > > (3) but the kernel internally is using the same 'wrong' value, so > userspace also needs to use that value, ie trust the #defined name > rather than manufacturing one ? > > That's awkward. I think it would be worth at least having a kernel > patch to add a comment clearly documenting this bug. > > (This error seems to only be in the 64-bit ABI, not 32-bit.) Yeah, this is pretty bad. I wonder how we managed not to notice this for so long... :-(. Andrew, could you please write a patch documenting this (both in the UAPI headers and in the documentation)? Thanks, M. -- Jazz is not dead. It just smells funny... From MAILER-DAEMON Mon Dec 16 11:36:27 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1igtMB-0005Zo-K8 for mharc-qemu-arm@gnu.org; Mon, 16 Dec 2019 11:36:27 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:60548) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1igtM6-0005QX-MK for qemu-arm@nongnu.org; Mon, 16 Dec 2019 11:36:24 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1igtM3-0001qq-85 for qemu-arm@nongnu.org; Mon, 16 Dec 2019 11:36:20 -0500 Received: from us-smtp-2.mimecast.com ([205.139.110.61]:58753 helo=us-smtp-delivery-1.mimecast.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1igtM2-0001ob-GU for qemu-arm@nongnu.org; Mon, 16 Dec 2019 11:36:18 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1576514177; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=b6rU/7SFMPtpuUaSJZL4ZvKzOzPSprKptVNDJXTPh9c=; b=Pt3XpgE3nmgcBt1ke/CUnvLfLRHetfpAA9rJ8YeJtUkBVjLJiyoeSuBy8NoxDo+EP74dux Cee+xcnnUCOU0UUdBaLjE5gaNc0WeiQW6NyOl7jpLMngxxOkwp7gIwAyhhzqwSLh2SE6Ic dI2gkhPAwR/cxrc8uPUoznYYd/GrBkA= Received: from mimecast-mx01.redhat.com (mimecast-mx01.redhat.com [209.132.183.4]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-90-OiXZFFJTMHGYhotQ9JwFmw-1; Mon, 16 Dec 2019 11:36:14 -0500 Received: from smtp.corp.redhat.com (int-mx01.intmail.prod.int.phx2.redhat.com [10.5.11.11]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx01.redhat.com (Postfix) with ESMTPS id 2177A1809A46; Mon, 16 Dec 2019 16:36:11 +0000 (UTC) Received: from kamzik.brq.redhat.com (ovpn-116-122.ams2.redhat.com [10.36.116.122]) by smtp.corp.redhat.com (Postfix) with ESMTPS id AF21D605C9; Mon, 16 Dec 2019 16:36:07 +0000 (UTC) Date: Mon, 16 Dec 2019 17:36:04 +0100 From: Andrew Jones To: Peter Maydell Cc: bijan.mottahedeh@oracle.com, Marc Zyngier , Richard Henderson , QEMU Developers , qemu-arm , Heyi Guo , msys.mizuma@gmail.com Subject: Re: [RFC PATCH v2 3/5] target/arm/kvm: Implement virtual time adjustment Message-ID: <20191216163604.wje5q2mvtytxjqoy@kamzik.brq.redhat.com> References: <20191212173320.11610-1-drjones@redhat.com> <20191212173320.11610-4-drjones@redhat.com> MIME-Version: 1.0 In-Reply-To: X-Scanned-By: MIMEDefang 2.79 on 10.5.11.11 X-MC-Unique: OiXZFFJTMHGYhotQ9JwFmw-1 X-Mimecast-Spam-Score: 0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: quoted-printable Content-Disposition: inline X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 205.139.110.61 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 16 Dec 2019 16:36:26 -0000 On Mon, Dec 16, 2019 at 03:14:00PM +0000, Peter Maydell wrote: > On Thu, 12 Dec 2019 at 17:33, Andrew Jones wrote: > > > > When a VM is stopped (guest is paused) guest virtual time > > should stop counting. Otherwise, when the VM is resumed it > > will experience time jumps and its kernel may report soft > > lockups. Not counting virtual time while the VM is stopped > > has the side effect of making the guest's time appear to lag > > when compared with real time, and even with time derived from > > the physical counter. For this reason, this change, which is > > enabled by default, comes with a KVM CPU feature allowing it > > to be disabled, restoring legacy behavior. > > > > This patch only provides the implementation of the virtual > > time adjustment. A subsequent patch will provide the CPU > > property allowing the change to be enabled and disabled. > > > > Reported-by: Bijan Mottahedeh > > Signed-off-by: Andrew Jones > > --- > > target/arm/cpu.h | 9 +++++++++ > > target/arm/kvm.c | 48 ++++++++++++++++++++++++++++++++++++++++++++ > > target/arm/kvm32.c | 3 +++ > > target/arm/kvm64.c | 3 +++ > > target/arm/kvm_arm.h | 23 +++++++++++++++++++++ > > 5 files changed, 86 insertions(+) > > > > diff --git a/target/arm/cpu.h b/target/arm/cpu.h > > index 83a809d4bac4..a79ea74125b3 100644 > > --- a/target/arm/cpu.h > > +++ b/target/arm/cpu.h > > @@ -821,6 +821,15 @@ struct ARMCPU { > > /* KVM init features for this CPU */ > > uint32_t kvm_init_features[7]; > > > > + /* KVM CPU features */ > > + bool kvm_adjvtime; > > + > > + /* VCPU virtual counter value used with kvm_adjvtime */ > > + uint64_t kvm_vtime; >=20 > How does this new state interact with migration ? I don't think we should need to worry about this state, because migration will do its own save/restore of the virtual counter, and as that restore comes later, it'll take precedence. We still need this state for the usual save/restore when not migrating, though, because KVM_REG_ARM_TIMER_CNT is a non-runtime cpreg with its level set to KVM_PUT_FULL_STATE. >=20 > > + > > + /* True if the run state is, or transitioning from, RUN_STATE_PAUS= ED */ > > + bool runstate_paused; > > + > > /* Uniprocessor system with MP extensions */ > > bool mp_is_up; > > > > diff --git a/target/arm/kvm.c b/target/arm/kvm.c > > index 5b82cefef608..a55fe7d7aefd 100644 > > --- a/target/arm/kvm.c > > +++ b/target/arm/kvm.c > > @@ -348,6 +348,24 @@ void kvm_arm_register_device(MemoryRegion *mr, uin= t64_t devid, uint64_t group, > > memory_region_ref(kd->mr); > > } > > > > +void kvm_arm_vm_state_change(void *opaque, int running, RunState state= ) > > +{ > > + CPUState *cs =3D opaque; > > + ARMCPU *cpu =3D ARM_CPU(cs); > > + > > + if (running) { > > + if (cpu->kvm_adjvtime && cpu->runstate_paused) { > > + kvm_arm_set_virtual_time(cs, cpu->kvm_vtime); > > + } > > + cpu->runstate_paused =3D false; > > + } else if (state =3D=3D RUN_STATE_PAUSED) { > > + cpu->runstate_paused =3D true; > > + if (cpu->kvm_adjvtime) { > > + kvm_arm_get_virtual_time(cs, &cpu->kvm_vtime); > > + } > > + } > > +} >=20 > How does this interact with the usual register sync to/from > KVM (ie kvm_arch_get_registers(), which I think will do a > GET_ONE_REG read of the TIMER_CNT register the way it does > any other sysreg, inside write_kvmstate_to_list(), plus > kvm_arch_set_registers() which does the write back to the > kernel in write_list_to_kvmstate()) ? It will, but only when level =3D=3D KVM_PUT_FULL_STATE. > Presumably we want this > version to take precedence by the set_virtual_time call > happening after the kvm_arch_set_registers, but is this > guaranteed ? Actually it doesn't really matter which takes precedence (I don't think), which is why we can rely on the usual save/restore for migration. We only need the new state this patch adds because we don't have any recent state otherwise, and because then we can be selective and only do the save/restore when transitioning to/from paused state. Thanks, drew From MAILER-DAEMON Mon Dec 16 11:44:16 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1igtTj-0007zr-Rf for mharc-qemu-arm@gnu.org; Mon, 16 Dec 2019 11:44:16 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:37805) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1igtTg-0007wi-PG for qemu-arm@nongnu.org; Mon, 16 Dec 2019 11:44:14 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1igtTd-0005lo-Ta for qemu-arm@nongnu.org; Mon, 16 Dec 2019 11:44:12 -0500 Received: from us-smtp-delivery-1.mimecast.com ([207.211.31.120]:50395 helo=us-smtp-1.mimecast.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1igtTd-0005im-Q0 for qemu-arm@nongnu.org; Mon, 16 Dec 2019 11:44:09 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1576514649; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=lB8rYaM4LIgsPJoAftgjG9mdXpweDU1tAotDnMpOJvo=; b=OR5Vzfu8dVlm7K5OPuVLHdvE/5wmuODT3Ie09mPmuaSxGKRRyvN0WEyPxI/xf2uAwNiTpb iDhqKNob5FVgvByCrKHJzDdTnD8trqdkpVHpcxsuvFJop50Xgxc+A9wyzk/evsyGaz0SoP Wn2hnhAVQGkqsNOWh7rb0fy8L7uMRxE= Received: from mimecast-mx01.redhat.com (mimecast-mx01.redhat.com [209.132.183.4]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-383-C6LwDkwYNX-Ln7KBtyRl8w-1; Mon, 16 Dec 2019 11:44:05 -0500 Received: from smtp.corp.redhat.com (int-mx07.intmail.prod.int.phx2.redhat.com [10.5.11.22]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx01.redhat.com (Postfix) with ESMTPS id 122EA1005512; Mon, 16 Dec 2019 16:44:03 +0000 (UTC) Received: from kamzik.brq.redhat.com (ovpn-116-122.ams2.redhat.com [10.36.116.122]) by smtp.corp.redhat.com (Postfix) with ESMTPS id 0D88210013D9; Mon, 16 Dec 2019 16:43:58 +0000 (UTC) Date: Mon, 16 Dec 2019 17:43:55 +0100 From: Andrew Jones To: Peter Maydell Cc: QEMU Developers , qemu-arm , Richard Henderson , Heyi Guo , bijan.mottahedeh@oracle.com, Marc Zyngier , msys.mizuma@gmail.com Subject: Re: [RFC PATCH v2 3/5] target/arm/kvm: Implement virtual time adjustment Message-ID: <20191216164355.i5rpfuqlfqv2z7m7@kamzik.brq.redhat.com> References: <20191212173320.11610-1-drjones@redhat.com> <20191212173320.11610-4-drjones@redhat.com> MIME-Version: 1.0 In-Reply-To: X-Scanned-By: MIMEDefang 2.84 on 10.5.11.22 X-MC-Unique: C6LwDkwYNX-Ln7KBtyRl8w-1 X-Mimecast-Spam-Score: 0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: quoted-printable Content-Disposition: inline X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 207.211.31.120 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 16 Dec 2019 16:44:14 -0000 On Mon, Dec 16, 2019 at 03:40:16PM +0000, Peter Maydell wrote: > On Mon, 16 Dec 2019 at 15:14, Peter Maydell wr= ote: > > How does this interact with the usual register sync to/from > > KVM (ie kvm_arch_get_registers(), which I think will do a > > GET_ONE_REG read of the TIMER_CNT register the way it does > > any other sysreg, inside write_kvmstate_to_list(), plus > > kvm_arch_set_registers() which does the write back to the > > kernel in write_list_to_kvmstate()) ? Presumably we want this > > version to take precedence by the set_virtual_time call > > happening after the kvm_arch_set_registers, but is this > > guaranteed ? >=20 > ...you might also want to look at the effects of simply > removing the KVM_REG_ARM_TIMER_CNT entry from the > 'non_runtime_cpregs[]' array -- in commit 4b7a6bf402bd064 > we explicitly stopped reading/writing this register's value > to/from the kernel except for inbound migration, and it > feels like this patchset is now rolling back that approach, > so maybe we should also be (configurably) rolling back some > of its implementation rather than just leaving it in place. I feel like I already considered that, maybe even tried it, a few months ago when I first looked at this. I must have decided against it for some reason at the time, but I don't recall what. Now I can say the reason is because we only do this save/restore when we transition to/from paused state, though. >=20 > I note also that the commit message there had a remark > about inconsistencies between VCPUs -- is the right thing > to handle this per-VM rather than per-VCPU somehow? per-VM would make sense, because the counters should be synchronized among the VCPUs. KVM does that for us, though, so whichever VCPU last restores its counter is the one that will determine the final value. Maybe we should have a VM ioctl instead, but ATM we only have VCPU ioctls. Thanks, drew From MAILER-DAEMON Mon Dec 16 11:53:09 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1igtcL-00010R-4z for mharc-qemu-arm@gnu.org; Mon, 16 Dec 2019 11:53:09 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:43684) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1igtcH-0000uQ-Ja for qemu-arm@nongnu.org; Mon, 16 Dec 2019 11:53:06 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1igtcF-0006LL-OC for qemu-arm@nongnu.org; Mon, 16 Dec 2019 11:53:05 -0500 Received: from us-smtp-delivery-1.mimecast.com ([205.139.110.120]:45286 helo=us-smtp-1.mimecast.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1igtcF-0006K3-Jl for qemu-arm@nongnu.org; Mon, 16 Dec 2019 11:53:03 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1576515182; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=6l+ZX6jfRcQPNGxAaff9khunijHeffZz2XH2nVa2low=; b=btCEn1HGXzgjDC8/R+Tn6n3QD6QRA/R23bsnUskpJswO0L4ZIkOcB/4EVB0RJsDwPOJTjN 6xzT5bU8mUW12khnMAQKodflMqlSClAnXoHrWw6cMT3yJ5dn+CRvRNoVLA/DN1jG6jE+9k 9abxjNHuzILjmDhqPYjk0oYFxka++70= Received: from mimecast-mx01.redhat.com (mimecast-mx01.redhat.com [209.132.183.4]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-180-TQ-AMmSSOLaG5TXmBjBmWw-1; Mon, 16 Dec 2019 11:53:01 -0500 Received: from smtp.corp.redhat.com (int-mx01.intmail.prod.int.phx2.redhat.com [10.5.11.11]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx01.redhat.com (Postfix) with ESMTPS id 6F5BE802570; Mon, 16 Dec 2019 16:52:59 +0000 (UTC) Received: from kamzik.brq.redhat.com (ovpn-116-122.ams2.redhat.com [10.36.116.122]) by smtp.corp.redhat.com (Postfix) with ESMTPS id 50C8B60479; Mon, 16 Dec 2019 16:52:56 +0000 (UTC) Date: Mon, 16 Dec 2019 17:52:49 +0100 From: Andrew Jones To: Peter Maydell Cc: bijan.mottahedeh@oracle.com, Marc Zyngier , Richard Henderson , QEMU Developers , qemu-arm , Heyi Guo , msys.mizuma@gmail.com Subject: Re: [RFC PATCH v2 5/5] target/arm/cpu: Add the kvm-no-adjvtime CPU property Message-ID: <20191216165249.lygksiptf2yowqh7@kamzik.brq.redhat.com> References: <20191212173320.11610-1-drjones@redhat.com> <20191212173320.11610-6-drjones@redhat.com> MIME-Version: 1.0 In-Reply-To: X-Scanned-By: MIMEDefang 2.79 on 10.5.11.11 X-MC-Unique: TQ-AMmSSOLaG5TXmBjBmWw-1 X-Mimecast-Spam-Score: 0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: quoted-printable Content-Disposition: inline X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 205.139.110.120 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 16 Dec 2019 16:53:08 -0000 On Mon, Dec 16, 2019 at 03:06:57PM +0000, Peter Maydell wrote: > On Thu, 12 Dec 2019 at 17:33, Andrew Jones wrote: > > > > kvm-no-adjvtime is a KVM specific CPU property and a first of its kind. > > To accommodate it we also add kvm_arm_add_vcpu_properties() and a > > KVM specific CPU properties description to the CPU features document. > > > > Signed-off-by: Andrew Jones > > --- > > docs/arm-cpu-features.rst | 31 ++++++++++++++++++++++++++++++- > > hw/arm/virt.c | 8 ++++++++ > > include/hw/arm/virt.h | 1 + > > target/arm/cpu.c | 2 ++ > > target/arm/cpu64.c | 1 + > > target/arm/kvm.c | 28 ++++++++++++++++++++++++++++ > > target/arm/kvm_arm.h | 11 +++++++++++ > > target/arm/monitor.c | 1 + > > tests/arm-cpu-features.c | 4 ++++ > > 9 files changed, 86 insertions(+), 1 deletion(-) > > > > diff --git a/docs/arm-cpu-features.rst b/docs/arm-cpu-features.rst > > index 1b367e22e16e..641ec9cb8f4a 100644 > > --- a/docs/arm-cpu-features.rst > > +++ b/docs/arm-cpu-features.rst > > @@ -31,7 +31,9 @@ supporting the feature or only supporting the feature= under certain > > configurations. For example, the `aarch64` CPU feature, which, when > > disabled, enables the optional AArch32 CPU feature, is only supported > > when using the KVM accelerator and when running on a host CPU type tha= t > > -supports the feature. > > +supports the feature. While `aarch64` currently only works with KVM, > > +it could work with TCG. CPU features that are specific to KVM are > > +prefixed with "kvm-" and are described in "KVM VCPU Features". > > > > CPU Feature Probing > > =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D > > @@ -171,6 +173,33 @@ disabling many SVE vector lengths would be quite v= erbose, the `sve` CPU > > properties have special semantics (see "SVE CPU Property Parsing > > Semantics"). > > > > +KVM VCPU Features > > +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D > > + > > +KVM VCPU features are CPU features that are specific to KVM, such as > > +paravirt features or features that enable CPU virtualization extension= s. > > +The features' CPU properties are only available when KVM is enabled an= d > > +are named with the prefix "kvm-". KVM VCPU features may be probed, > > +enabled, and disabled in the same way as other CPU features. Below is= the > > +list of KVM VCPU features and their descriptions. > > + > > + kvm-no-adjvtime When disabled, each time the VM transitions > > + back to running state from the paused state= the > > + VCPU's vitual counter is updated to ensure = the >=20 > "virtual" >=20 > > + stopped time is not counted. This avoids t= ime > > + jumps surprising guest OSes and application= s, > > + as long as they use the virtual counter for > > + timekeeping, but has the side effect of the > > + virtual and physical counters diverging. A= ll > > + timekeeping based on the virtual counter wi= ll > > + appear to lag behind any timekeeping that d= oes > > + not subtract VM stopped time. The guest ma= y > > + resynchronize its virtual counter with othe= r > > + time sources as needed. Enabling this KVM = VCPU > > + feature provides the legacy behavior, which= is > > + to also count stopped time with the virtual > > + counter. >=20 > This phrasing reads a bit confusingly to me. What I would usually expect > is that you get > name-of-option Description of what the option does. >=20 > But here we have > name-of-option Long description of the default behaviour, > taking many lines and several sentences. > Brief note at the end that enabling this > feature gives the opposite effect. >=20 > Especially since the default-behaviour description isn't prefaced > with "By default" or similar, it's quite easy to start reading the > text assuming it's defining what the option is going to do, only > to get to the end and realise that it's defining what the option > is *not* going to do... I'll take another stab at this, but my feeling is that a '-no-' option should be one that just turns off the default behavior, which is why I wrote a long description of the default behavior. If you'd prefer the description to be more terse, then I can certainly delete a bunch of the text, but then I fear what this option disables wouldn't be clear enough. >=20 > Incidentally, if I understand things correctly, for TCG the > behaviour is (and has always been) that VM-stopped time is > not counted, because we run the emulated versions of these counters > off QEMU_CLOCK_VIRTUAL. So having the KVM default be the same as > the TCG default is nicely consistent. Thanks, drew From MAILER-DAEMON Mon Dec 16 11:57:20 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1igtgO-0006jC-FX for mharc-qemu-arm@gnu.org; Mon, 16 Dec 2019 11:57:20 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:45294) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1igtgL-0006dW-1g for qemu-arm@nongnu.org; Mon, 16 Dec 2019 11:57:18 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1igtgJ-0001ED-Np for qemu-arm@nongnu.org; Mon, 16 Dec 2019 11:57:16 -0500 Received: from mail-oi1-x241.google.com ([2607:f8b0:4864:20::241]:38967) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1igtgJ-0001B4-8X for qemu-arm@nongnu.org; Mon, 16 Dec 2019 11:57:15 -0500 Received: by mail-oi1-x241.google.com with SMTP id a67so3845124oib.6 for ; Mon, 16 Dec 2019 08:57:14 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=QaFLLYDEWud99qoiUNGEueTX0iNK5/Ih2SGsu7QWWCw=; b=hVDtMmy3zyYCoxN+m2cHJqFkUt9piFFGIUuFoZwabaoY+KnWL6g2duJZedACp2UzsZ 2zy1zKhI3/uWpRvP813LzBbrrm305FHOLT5292dUaOX6iKW+K77R4zCWMoZLovQdVnd6 ZJBK6kWK891LU9P+makBzD/SpDs8gRzB2ubFxDPVueUXt8nUUvC9Rl2pz8lo5euJGxxi V7XgljTgNwAIanV59QEfhVNPB86z4zjZIeUiRYP17VdwSg/1DapxYt1UBxIpf4+cjKLu qofUOA0AG3fNLHEHhjvkiL5zNZyDH/Fb/TH3IGL+y9iwXPqtBHy2mZdzU62wwxgYH9F5 /KoQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=QaFLLYDEWud99qoiUNGEueTX0iNK5/Ih2SGsu7QWWCw=; b=HmwmsF4V6obT2/hfQk3DMndS39w9wHuuWLk4cO/BRvca7Bzuy5DrDJ9lFNQiBcKefV B5K3Govc4CT6eFyd3/wtmDRtrbOo2imSq/dpSeI9UEwmZsM+7nQwN2lNHd2YWloI87ba 7g+3cIHadMRj2OYJKD1/SWoYL3SAlpoSH8wWD/IZ+Idzc8HAM8ati/mfso50EdECBu/B aYRAxBAib0+2cQnQf44eHnUXmuzKtm+QdLAUpD8UIWT+/73sK4MnaspinU44q4WIkU6+ CRuRwK570yS8ITrVDtpetz2spmBvtKwFNPu3l9usWs3QtTEnkV8+fXJevMG+x6xPDLp5 +aIg== X-Gm-Message-State: APjAAAX1Ko5/335GQ6S/TDIIs4LT2q7mOfPyOOapr2gRo4IpjXkmgdiy 19BtzVK6Dq2OyJa9u3HeBa6dhPC0hcgfyslxYvHzTw== X-Google-Smtp-Source: APXvYqz72DDSyAERPvL+ocn3L9YeI8+tIwMoLS3e1UmFlwTNWykfuwpTOSIgTobFrolcChoty2yns6EEPdLTEbkPqUQ= X-Received: by 2002:aca:f5cc:: with SMTP id t195mr10156384oih.163.1576515434294; Mon, 16 Dec 2019 08:57:14 -0800 (PST) MIME-Version: 1.0 References: <20191212173320.11610-1-drjones@redhat.com> <20191212173320.11610-6-drjones@redhat.com> <20191216165249.lygksiptf2yowqh7@kamzik.brq.redhat.com> In-Reply-To: <20191216165249.lygksiptf2yowqh7@kamzik.brq.redhat.com> From: Peter Maydell Date: Mon, 16 Dec 2019 16:57:02 +0000 Message-ID: Subject: Re: [RFC PATCH v2 5/5] target/arm/cpu: Add the kvm-no-adjvtime CPU property To: Andrew Jones Cc: bijan.mottahedeh@oracle.com, Marc Zyngier , Richard Henderson , QEMU Developers , qemu-arm , Heyi Guo , msys.mizuma@gmail.com Content-Type: text/plain; charset="UTF-8" X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::241 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 16 Dec 2019 16:57:19 -0000 On Mon, 16 Dec 2019 at 16:53, Andrew Jones wrote: > > On Mon, Dec 16, 2019 at 03:06:57PM +0000, Peter Maydell wrote: > > This phrasing reads a bit confusingly to me. What I would usually expect > > is that you get > > name-of-option Description of what the option does. > > > > But here we have > > name-of-option Long description of the default behaviour, > > taking many lines and several sentences. > > Brief note at the end that enabling this > > feature gives the opposite effect. > > > > Especially since the default-behaviour description isn't prefaced > > with "By default" or similar, it's quite easy to start reading the > > text assuming it's defining what the option is going to do, only > > to get to the end and realise that it's defining what the option > > is *not* going to do... > > I'll take another stab at this, but my feeling is that a '-no-' option > should be one that just turns off the default behavior, which is why I > wrote a long description of the default behavior. If you'd prefer the > description to be more terse, then I can certainly delete a bunch of > the text, but then I fear what this option disables wouldn't be clear > enough. I'm happy with the length of it; it would definitely be helped a lot just with phrasing that was clearer up front about that it was starting by describing the default behaviour. thanks -- PMM From MAILER-DAEMON Mon Dec 16 11:59:44 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1igtig-0001n9-UW for mharc-qemu-arm@gnu.org; Mon, 16 Dec 2019 11:59:44 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:46186) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1igtia-0001iw-Bl for qemu-arm@nongnu.org; Mon, 16 Dec 2019 11:59:38 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1igtiZ-0008DE-1V for qemu-arm@nongnu.org; Mon, 16 Dec 2019 11:59:36 -0500 Received: from us-smtp-delivery-1.mimecast.com ([205.139.110.120]:31889 helo=us-smtp-1.mimecast.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1igtiX-00087H-Ey for qemu-arm@nongnu.org; Mon, 16 Dec 2019 11:59:33 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1576515573; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=tOQM1/Rz4ycyGW1DEvNcWUzz5svT6E2Jm6LD2YWykoQ=; b=EOBc1hYIQsdkTlNL0/6PsKNKaZKuUHqdRVJCibsuqrtjVsSl6xCwMwjsS2LiF3E/d9Mk3X s5n2H68cxTXOUdL8ljyOQwFL3YyVWO+zwJ+aeKwIsRGlQq5woZ/gqLtTBwqduMwhLb6I1x LTiUJCwkPZU29gmsrjb6LyjrAFxV+z4= Received: from mimecast-mx01.redhat.com (mimecast-mx01.redhat.com [209.132.183.4]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-416-sYxEI4vzMTC5hBXrq0lGtA-1; Mon, 16 Dec 2019 11:59:29 -0500 Received: from smtp.corp.redhat.com (int-mx04.intmail.prod.int.phx2.redhat.com [10.5.11.14]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx01.redhat.com (Postfix) with ESMTPS id EA39E802561; Mon, 16 Dec 2019 16:59:27 +0000 (UTC) Received: from kamzik.brq.redhat.com (ovpn-116-122.ams2.redhat.com [10.36.116.122]) by smtp.corp.redhat.com (Postfix) with ESMTPS id E19715D9D6; Mon, 16 Dec 2019 16:59:23 +0000 (UTC) Date: Mon, 16 Dec 2019 17:59:20 +0100 From: Andrew Jones To: Marc Zyngier Cc: Peter Maydell , bijan.mottahedeh@oracle.com, Richard Henderson , QEMU Developers , qemu-arm , Heyi Guo , msys.mizuma@gmail.com Subject: Re: [RFC PATCH v2 0/5] target/arm/kvm: Adjust virtual time Message-ID: <20191216165920.qsx7ufviir74tbkl@kamzik.brq.redhat.com> References: <20191212173320.11610-1-drjones@redhat.com> <4cb9bcfd47dff57c9ae6bb92bae87589@www.loen.fr> MIME-Version: 1.0 In-Reply-To: <4cb9bcfd47dff57c9ae6bb92bae87589@www.loen.fr> X-Scanned-By: MIMEDefang 2.79 on 10.5.11.14 X-MC-Unique: sYxEI4vzMTC5hBXrq0lGtA-1 X-Mimecast-Spam-Score: 0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: quoted-printable Content-Disposition: inline X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 205.139.110.120 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 16 Dec 2019 16:59:39 -0000 On Mon, Dec 16, 2019 at 04:18:23PM +0000, Marc Zyngier wrote: > On 2019-12-16 15:33, Peter Maydell wrote: > > On Thu, 12 Dec 2019 at 17:33, Andrew Jones wrote: > >=20 > > > Userspace that wants to set KVM_REG_ARM_TIMER_CNT should beware that > > > the KVM register ID is not correct. This cannot be fixed because > > > it's > > > UAPI and if the UAPI headers are used then it can't be a problem. > > > However, if a userspace attempts to create the ID themselves from > > > the > > > register's specification, then they will get KVM_REG_ARM_TIMER_CVAL > > > instead, as the _CNT and _CVAL definitions have their register > > > parameters swapped. > >=20 > > So, to be clear, you mean that: > >=20 > > (1) the kernel headers say: > >=20 > > /* EL0 Virtual Timer Registers */ > > #define KVM_REG_ARM_TIMER_CTL ARM64_SYS_REG(3, 3, 14, 3, 1) > > #define KVM_REG_ARM_TIMER_CNT ARM64_SYS_REG(3, 3, 14, 3, 2) > > #define KVM_REG_ARM_TIMER_CVAL ARM64_SYS_REG(3, 3, 14, 0, 2) > >=20 > > (2) some of the RHSes of these are wrong > >=20 > > (3) but the kernel internally is using the same 'wrong' value, so > > userspace also needs to use that value, ie trust the #defined name > > rather than manufacturing one ? > >=20 > > That's awkward. I think it would be worth at least having a kernel > > patch to add a comment clearly documenting this bug. > >=20 > > (This error seems to only be in the 64-bit ABI, not 32-bit.) >=20 > Yeah, this is pretty bad. I wonder how we managed not to notice > this for so long... :-(. >=20 > Andrew, could you please write a patch documenting this (both in > the UAPI headers and in the documentation)? > Will do. I'll try to get to it this week. Thanks, drew From MAILER-DAEMON Mon Dec 16 12:05:26 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1igtoE-0007vy-3E for mharc-qemu-arm@gnu.org; Mon, 16 Dec 2019 12:05:26 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:48977) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1igto9-0007qZ-Lw for qemu-arm@nongnu.org; Mon, 16 Dec 2019 12:05:22 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1igto8-0008Nc-98 for qemu-arm@nongnu.org; Mon, 16 Dec 2019 12:05:21 -0500 Received: from inca-roads.misterjones.org ([213.251.177.50]:47927) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1igto5-0008KZ-RH; Mon, 16 Dec 2019 12:05:17 -0500 Received: from www-data by cheepnis.misterjones.org with local (Exim 4.80) (envelope-from ) id 1igtnu-0004Nj-E9; Mon, 16 Dec 2019 18:05:06 +0100 To: Andrew Jones Subject: Re: [RFC PATCH v2 0/5] target/arm/kvm: Adjust virtual time X-PHP-Originating-Script: 0:main.inc MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Date: Mon, 16 Dec 2019 17:05:06 +0000 From: Marc Zyngier Cc: Peter Maydell , , Richard Henderson , QEMU Developers , qemu-arm , Heyi Guo , In-Reply-To: <20191216165920.qsx7ufviir74tbkl@kamzik.brq.redhat.com> References: <20191212173320.11610-1-drjones@redhat.com> <4cb9bcfd47dff57c9ae6bb92bae87589@www.loen.fr> <20191216165920.qsx7ufviir74tbkl@kamzik.brq.redhat.com> Message-ID: X-Sender: maz@kernel.org User-Agent: Roundcube Webmail/0.7.2 X-SA-Exim-Connect-IP: X-SA-Exim-Rcpt-To: drjones@redhat.com, peter.maydell@linaro.org, bijan.mottahedeh@oracle.com, richard.henderson@linaro.org, qemu-devel@nongnu.org, qemu-arm@nongnu.org, guoheyi@huawei.com, msys.mizuma@gmail.com X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on cheepnis.misterjones.org); SAEximRunCond expanded to false X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [fuzzy] X-Received-From: 213.251.177.50 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 16 Dec 2019 17:05:24 -0000 On 2019-12-16 16:59, Andrew Jones wrote: > On Mon, Dec 16, 2019 at 04:18:23PM +0000, Marc Zyngier wrote: >> On 2019-12-16 15:33, Peter Maydell wrote: >> > On Thu, 12 Dec 2019 at 17:33, Andrew Jones >> wrote: >> > >> > > Userspace that wants to set KVM_REG_ARM_TIMER_CNT should beware >> that >> > > the KVM register ID is not correct. This cannot be fixed >> because >> > > it's >> > > UAPI and if the UAPI headers are used then it can't be a >> problem. >> > > However, if a userspace attempts to create the ID themselves >> from >> > > the >> > > register's specification, then they will get >> KVM_REG_ARM_TIMER_CVAL >> > > instead, as the _CNT and _CVAL definitions have their register >> > > parameters swapped. >> > >> > So, to be clear, you mean that: >> > >> > (1) the kernel headers say: >> > >> > /* EL0 Virtual Timer Registers */ >> > #define KVM_REG_ARM_TIMER_CTL ARM64_SYS_REG(3, 3, 14, 3, >> 1) >> > #define KVM_REG_ARM_TIMER_CNT ARM64_SYS_REG(3, 3, 14, 3, >> 2) >> > #define KVM_REG_ARM_TIMER_CVAL ARM64_SYS_REG(3, 3, 14, 0, >> 2) >> > >> > (2) some of the RHSes of these are wrong >> > >> > (3) but the kernel internally is using the same 'wrong' value, so >> > userspace also needs to use that value, ie trust the #defined name >> > rather than manufacturing one ? >> > >> > That's awkward. I think it would be worth at least having a kernel >> > patch to add a comment clearly documenting this bug. >> > >> > (This error seems to only be in the 64-bit ABI, not 32-bit.) >> >> Yeah, this is pretty bad. I wonder how we managed not to notice >> this for so long... :-(. >> >> Andrew, could you please write a patch documenting this (both in >> the UAPI headers and in the documentation)? >> > > Will do. I'll try to get to it this week. Thanks a lot. M. -- Jazz is not dead. It just smells funny... From MAILER-DAEMON Mon Dec 16 13:06:49 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1iguld-0008D0-1y for mharc-qemu-arm@gnu.org; Mon, 16 Dec 2019 13:06:49 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:42168) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1igula-00089n-5K for qemu-arm@nongnu.org; Mon, 16 Dec 2019 13:06:47 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1igulX-0001SO-4V for qemu-arm@nongnu.org; Mon, 16 Dec 2019 13:06:46 -0500 Received: from mail-oi1-x242.google.com ([2607:f8b0:4864:20::242]:35146) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1igulW-0001Qq-UY for qemu-arm@nongnu.org; Mon, 16 Dec 2019 13:06:43 -0500 Received: by mail-oi1-x242.google.com with SMTP id k196so4048975oib.2 for ; Mon, 16 Dec 2019 10:06:42 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=MirDbpR4oYKNUHsUc37Lmf2tFcn7WlaGv1P9OqWE3II=; b=O0Xwby5+qMCAZNks4hGLGdbDjf7JhZdBAJMxRR+OkUlf+41I8x8Rmr/7n4BdRII2i/ A4q+wIj6zNJbNWeoeeYQaE8B2GdGEcRKr1BfiLIWZfnJY2OEwF6o9cWnAEvZlK7L6zGr YL8CBPYvWUeSpRoxGKfRvnRxPjPgw7R6ZvKj1JuEeVgDQ6LuDMdPQYT9bSdAbqhBSBs5 BqvsLft43G02Qgl1T8nG7NPWMxBGRwhhCIQMwkFEDVkmofx8yfI+dRyZe//YbOsINzVi JtKeXB69PBPKlCs1nn2/t4nbUri+pCxlYjTn2R6t+FRsvNrh55JpqxBbXqHN3rrKLaNR bwEQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=MirDbpR4oYKNUHsUc37Lmf2tFcn7WlaGv1P9OqWE3II=; b=toKUP3g14D9l4DRj964GYGNVXgOIYafJEVPkIMPkTETO/PNXt6tIMWZz7M+s7IdfF3 hq7Lsc9HMEcmHl4qes4zLuSSLczxd/ekbMkXz8aG3ljwFuS8cl31C0iZ1B2/sCG8NIJI S4c9Zh25mowMe3lhzr9hCOcj/ixCwCvRfioXYXOscO8S9A4mTsQddsxLVTpMkWWeUtvk f1CvHKRYv7z/wOXBGQAcyJJghB0ttM6X+jFdZhIH/vqvrO1kRzoaw+9bTlpKGVkXMS0M FvpE3EqAHnf4eElChKHal1uGu5RVRFdCU9O4JI4ZATjsChQq2k0392eAbB65o3l+chYG LIvA== X-Gm-Message-State: APjAAAVudiL858YqJCM9GhxMe17agdI4oFO02ss8EENgrldV3gFSdIfP kZ5cL3Sqsa+UWQIfULRkHx/f59SsdZ1ZSHT9M+cIMg== X-Google-Smtp-Source: APXvYqwCA+iqnTv4OZy4k7jGOEAVhPzgv9IxxB5Ne9ckGmf8WAi9kgkdqYRqVqmNfi3CQ7w/jlgMr2/wztj14Ku3l94= X-Received: by 2002:aca:f5cc:: with SMTP id t195mr153912oih.163.1576519601929; Mon, 16 Dec 2019 10:06:41 -0800 (PST) MIME-Version: 1.0 References: <20191212173320.11610-1-drjones@redhat.com> <20191212173320.11610-4-drjones@redhat.com> <20191216164355.i5rpfuqlfqv2z7m7@kamzik.brq.redhat.com> In-Reply-To: <20191216164355.i5rpfuqlfqv2z7m7@kamzik.brq.redhat.com> From: Peter Maydell Date: Mon, 16 Dec 2019 18:06:30 +0000 Message-ID: Subject: Re: [RFC PATCH v2 3/5] target/arm/kvm: Implement virtual time adjustment To: Andrew Jones Cc: QEMU Developers , qemu-arm , Richard Henderson , Heyi Guo , bijan.mottahedeh@oracle.com, Marc Zyngier , msys.mizuma@gmail.com Content-Type: text/plain; charset="UTF-8" X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::242 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 16 Dec 2019 18:06:47 -0000 On Mon, 16 Dec 2019 at 16:44, Andrew Jones wrote: > > On Mon, Dec 16, 2019 at 03:40:16PM +0000, Peter Maydell wrote: > > On Mon, 16 Dec 2019 at 15:14, Peter Maydell wrote: > > > How does this interact with the usual register sync to/from > > > KVM (ie kvm_arch_get_registers(), which I think will do a > > > GET_ONE_REG read of the TIMER_CNT register the way it does > > > any other sysreg, inside write_kvmstate_to_list(), plus > > > kvm_arch_set_registers() which does the write back to the > > > kernel in write_list_to_kvmstate()) ? Presumably we want this > > > version to take precedence by the set_virtual_time call > > > happening after the kvm_arch_set_registers, but is this > > > guaranteed ? > > > > ...you might also want to look at the effects of simply > > removing the KVM_REG_ARM_TIMER_CNT entry from the > > 'non_runtime_cpregs[]' array -- in commit 4b7a6bf402bd064 > > we explicitly stopped reading/writing this register's value > > to/from the kernel except for inbound migration, and it > > feels like this patchset is now rolling back that approach, > > so maybe we should also be (configurably) rolling back some > > of its implementation rather than just leaving it in place. > > I feel like I already considered that, maybe even tried it, a few months > ago when I first looked at this. I must have decided against it for some > reason at the time, but I don't recall what. Now I can say the reason is > because we only do this save/restore when we transition to/from paused > state, though. I found the thread which discussed the bug which originally caused us to add commit 4b7a6bf402bd064: https://lists.cs.columbia.edu/pipermail/kvmarm/2015-July/015665.html -- there are some codepaths which cause us to do a sync from/to KVM for one VCPU while others are still running. If we do a read-CNT-and-write-back then we effectively cause time to jump backwards for the other still-running CPUs. So we do still want to have TIMER_CNT listed as being KVM_PUT_FULL_STATE regardless, or we re-introduce that bug. Your approach in this patchset reads and writes on vm-paused, so it won't have the pre-2015 problems. It still feels odd that we're storing this bit of guest state in two places now though -- in kvm_vtime, and also in its usual place in the cpreg_array data structures (we write back the value from kvm_vtime when the VM starts running, and we write back the value from the cpreg_array for a PUT_FULL_STATE, which the comments claim is only on startup or when we just loaded migration state (and also undocumentedly but reasonably on cpu-hotplug, which arm doesn't have yet). I've just spent a little while digging through code, and haven't been able to satisfy myself on the ordering of which writeback wins: for a loadvm I think we first do a cpu_synchronize_all_post_init() (writing back the counter value from the migration data) and then after than we will unpause the VM -- why doesn't this overwrite the correct value with the wrong value from kvm_vtime ? I just noticed also that the logic used in this patch doesn't match what other architectures do in their vm_state_change function -- eg cpu_ppc_clock_vm_state_change() has an "if (running) { load } else { save }", and kvmclock_vm_state_change() for i386 also has "if (running) { ... } else { ... }", though it has an extra wrinkle where it captures "are we PAUSED?" to use in the pre_save function; the comment above kvmclock_pre_save() suggests maybe that would be useful for other than x86, too. kvm_s390_tod_vm_state_change() has logic that's a slightly more complicated variation on just testing the 'running' flag, but it doesn't look at the specific new state. > > I note also that the commit message there had a remark > > about inconsistencies between VCPUs -- is the right thing > > to handle this per-VM rather than per-VCPU somehow? > > per-VM would make sense, because the counters should be synchronized > among the VCPUs. KVM does that for us, though, so whichever VCPU last > restores its counter is the one that will determine the final value. > > Maybe we should have a VM ioctl instead, but ATM we only have VCPU ioctls. I meant more "only do the save/load once per VM in QEMU but do it by working with just one VCPU". But I guess since migration works on all the VCPUs we're ok to do pause-resume the same way (and I've now tracked down what the 'inconsistentencies between VCPUs' were: they're when we were syncing the CNT value for one vCPU when others were still running.) thanks -- PMM From MAILER-DAEMON Mon Dec 16 14:46:23 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1igwJz-0000G5-2p for mharc-qemu-arm@gnu.org; Mon, 16 Dec 2019 14:46:23 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:47228) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1igwJv-0000Cm-Qi for qemu-arm@nongnu.org; Mon, 16 Dec 2019 14:46:21 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1igwJu-0003Le-9C for qemu-arm@nongnu.org; Mon, 16 Dec 2019 14:46:19 -0500 Received: from mail-il1-x142.google.com ([2607:f8b0:4864:20::142]:41284) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1igwJq-0003Ju-Lc; Mon, 16 Dec 2019 14:46:14 -0500 Received: by mail-il1-x142.google.com with SMTP id f10so6392602ils.8; Mon, 16 Dec 2019 11:46:13 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=OsHm0tUSHoKhbWzbKpZ0C/bNOhwpqgtB85Sg/g/m0rU=; b=f4ur0HEHZnc/2TQ0OcuK88IYSlQtgNyjvtVZp2GyoaCJx2PKY9cOXBsp2IIEPU9ZKK DcgfSlo3s+5fNJeRUtbK1wwHsXh73cGUW5k7BfDG6srs62kOpEv96jaBJCuvFXRMaZEp 4MS4/uDr0ECvZav0WetCFdETlkElEKwC5+X9b2tg8035N+ENFpQvXOVYkVGtmEbth1bM FJN4Oykr5oVFZa4wTrYWlpyFRXWdQXu/Vgk2cvN3spbPggHzJm2M8xzEqQczS4njO7ni 3uPjbgxdpsDTHEiP6Aal/QzS4mHAojJ1A3BcRJSLgqLNlyYysHKw413i6lm+OfYUdgWF nMgA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=OsHm0tUSHoKhbWzbKpZ0C/bNOhwpqgtB85Sg/g/m0rU=; b=PRGiZyNtC5E7sDE0O4cYhmvKFjiF71l2e2lmJxGJHo0X+dnaMn90OwkObSrb7YxXX2 3sQ5D81Ol/jIgWKN9EZmV7LN/GLSvDCGzPJvYKasNstxnlqjSayTGvz4xgOq5P3qctwv J4Tytp74eoqWZe4eu6YjdwtyRfoaGm1kJ8TRwEp7OJVvoZyKSxthGqc3+0tTkbdWdEHM SkXdh33ulBi/SBQj+hnhVDaym/7w4rBEMgr8c7WtsEYh+GnAMpPh5ahfoxd24U1SAogi 6nv0OUeehLmyaZWSuXX2bbnntffSWYH2wGj9BCXeLtu2YaPGfdYaobG1ejXnDi3+lmHw WAmw== X-Gm-Message-State: APjAAAWG08DX91Ce11ATi6I7j/tzrB+MY6PO6D6ooUGONWbYoQvhvHiX x9X85aTN97zLh0ZDu7u4aSCV+EzLQhaVYuwN37c= X-Google-Smtp-Source: APXvYqztAQsm5gMqTB3ZjOvI0BjOvZnUSJcYwidpVx6noYr6OaCad7TEt8f4wbMHnLMaKlRLtW9ioIt51zYEPvqUvsc= X-Received: by 2002:a92:d5cf:: with SMTP id d15mr13244508ilq.306.1576525573101; Mon, 16 Dec 2019 11:46:13 -0800 (PST) MIME-Version: 1.0 References: <20191202210947.3603-1-nieklinnenbank@gmail.com> <20191202210947.3603-10-nieklinnenbank@gmail.com> <6bee15d7-7d80-0709-ac90-ef2052b39329@redhat.com> <03a78f1d-e8fe-5a53-b061-d39de9ed7a9e@redhat.com> In-Reply-To: <03a78f1d-e8fe-5a53-b061-d39de9ed7a9e@redhat.com> From: Niek Linnenbank Date: Mon, 16 Dec 2019 20:46:01 +0100 Message-ID: Subject: Re: [PATCH 09/10] arm: allwinner-h3: add SD/MMC host controller To: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= Cc: QEMU Developers , qemu-arm , Peter Maydell , Beniamino Galvani Content-Type: multipart/alternative; boundary="000000000000c39ead0599d776e2" X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::142 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 16 Dec 2019 19:46:21 -0000 --000000000000c39ead0599d776e2 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable On Mon, Dec 16, 2019 at 1:14 AM Philippe Mathieu-Daud=C3=A9 wrote: > On 12/16/19 12:07 AM, Niek Linnenbank wrote: > > > > > > On Fri, Dec 13, 2019 at 12:56 AM Philippe Mathieu-Daud=C3=A9 > > > wrote: > > > > Hi Niek, > > > > On 12/11/19 11:34 PM, Niek Linnenbank wrote: > [...] > > > +static uint32_t aw_h3_sdhost_process_desc(AwH3SDHostState *= s, > > > + hwaddr desc_addr, > > > + TransferDescripto= r > > *desc, > > > + bool is_write, > > uint32_t > > > max_bytes) > > > +{ > > > + uint32_t num_done =3D 0; > > > + uint32_t num_bytes =3D max_bytes; > > > + uint8_t buf[1024]; > > > + > > > + /* Read descriptor */ > > > + cpu_physical_memory_read(desc_addr, desc, sizeof(*desc)= ); > > > > Should we worry about endianess here? > > > > > > I tried to figure out what is expected, but the > > Allwinner_H3_Datasheet_V1.2.pdf does not > > explicitly mention endianness for any of its I/O devices. Currently it > > seems all devices are > > happy with using the same endianness as the CPUs. In the MemoryRegionOp= s > > has DEVICE_NATIVE_ENDIAN > > set to match the behavior seen. > > OK. > > [...] > > > +static const MemoryRegionOps aw_h3_sdhost_ops =3D { > > > + .read =3D aw_h3_sdhost_read, > > > + .write =3D aw_h3_sdhost_write, > > > + .endianness =3D DEVICE_NATIVE_ENDIAN, > > > > I haven't checked .valid accesses from the datasheet. > > > > However due to: > > > > res =3D s->data_crc[((offset - REG_SD_DATA7_CRC) / > sizeof(uint32_t))]; > > > > You seem to expect: > > > > .impl.min_access_size =3D 4, > > > > .impl.max_access_size unset is 8, which should works. > > > > It seems that all registers are aligned on at least 32-bit boundaries. > > And the section 5.3.5.1 mentions > > that the DMA descriptors must be stored in memory 32-bit aligned. So > > based on that information, > > So you are describing ".valid.min_access_size =3D 4", which is the minimu= m > access size on the bus. > ".impl.min_access_size" is different, it is what access sizes is ready > to handle your model. > Your model read/write handlers expect addresses aligned on 32-bit > boundary, this is why I suggested to use ".impl.min_access_size =3D 4". I= f > the guest were using a 16-bit access, your model would be buggy. If you > describe your implementation to accept minimum 32-bit and the guest is > allowed to use smaller accesses, QEMU will do a 32-bit access to the > device, and return the 16-bit part to the guest. This way your model is > safe. This is done by access_with_adjusted_size() in memory.c. > If you restrict with ".valid.min_access_size =3D 4", you might think we > don't need ".valid.min_access_size =3D 4" because all access from guest > will be at least 32-bit. However keep in mind someone might find this > device in another datasheet not limited to 32-bit, and let's say change > to ".valid.min_access_size =3D 2". Without ".impl.min_access_size =3D 4" > your model is buggy. So to be safe I'd use: > > .impl.min_access_size =3D 4, > .valid.min_access_size =3D 4, > Now it makes more sense to me, thanks Philippe for explaining this! Great, I'll add .impl.min_access_size =3D 4. At this point, I've processed all the feedback that I received for all of the patches in this series. Is there anything else you would like to see/discuss/review, or shall I send the v2 when I finish testing? Regards, Niek > > > I think 32-bit is a safe choice. I've verified this with Linux mainline > > and U-Boot drivers and both are still working. > > Regards, > > Phil. > > --=20 Niek Linnenbank --000000000000c39ead0599d776e2 Content-Type: text/html; charset="UTF-8" Content-Transfer-Encoding: quoted-printable


=
On Mon, Dec 16, 2019 at 1:14 AM Phili= ppe Mathieu-Daud=C3=A9 <philmd@redh= at.com> wrote:
On 12/16/19 12:07 AM, Niek Linnenbank wrote:
>
>
> On Fri, Dec 13, 2019 at 12:56 AM Philippe Mathieu-Daud=C3=A9
> <philmd@redh= at.com <mailto:philmd@redhat.com>> wrote:
>
>=C2=A0 =C2=A0 =C2=A0Hi Niek,
>
>=C2=A0 =C2=A0 =C2=A0On 12/11/19 11:34 PM, Niek Linnenbank wrote:
[...]
>=C2=A0 =C2=A0 =C2=A0 >=C2=A0 =C2=A0 =C2=A0+static uint32_t aw_h3_sdh= ost_process_desc(AwH3SDHostState *s,
>=C2=A0 =C2=A0 =C2=A0 >=C2=A0 =C2=A0 =C2=A0+=C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 hwaddr desc_addr,
>=C2=A0 =C2=A0 =C2=A0 >=C2=A0 =C2=A0 =C2=A0+=C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 TransferDescriptor
>=C2=A0 =C2=A0 =C2=A0*desc,
>=C2=A0 =C2=A0 =C2=A0 >=C2=A0 =C2=A0 =C2=A0+=C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 bool is_write,
>=C2=A0 =C2=A0 =C2=A0uint32_t
>=C2=A0 =C2=A0 =C2=A0 >=C2=A0 =C2=A0 =C2=A0max_bytes)
>=C2=A0 =C2=A0 =C2=A0 >=C2=A0 =C2=A0 =C2=A0+{
>=C2=A0 =C2=A0 =C2=A0 >=C2=A0 =C2=A0 =C2=A0+=C2=A0 =C2=A0 uint32_t nu= m_done =3D 0;
>=C2=A0 =C2=A0 =C2=A0 >=C2=A0 =C2=A0 =C2=A0+=C2=A0 =C2=A0 uint32_t nu= m_bytes =3D max_bytes;
>=C2=A0 =C2=A0 =C2=A0 >=C2=A0 =C2=A0 =C2=A0+=C2=A0 =C2=A0 uint8_t buf= [1024];
>=C2=A0 =C2=A0 =C2=A0 >=C2=A0 =C2=A0 =C2=A0+
>=C2=A0 =C2=A0 =C2=A0 >=C2=A0 =C2=A0 =C2=A0+=C2=A0 =C2=A0 /* Read des= criptor */
>=C2=A0 =C2=A0 =C2=A0 >=C2=A0 =C2=A0 =C2=A0+=C2=A0 =C2=A0 cpu_physica= l_memory_read(desc_addr, desc, sizeof(*desc));
>
>=C2=A0 =C2=A0 =C2=A0Should we worry about endianess here?
>
>
> I tried to figure out what is expected, but the
> Allwinner_H3_Datasheet_V1.2.pdf does not
> explicitly mention endianness for any of its I/O devices. Currently it=
> seems all devices are
> happy with using the same endianness as the CPUs. In the MemoryRegionO= ps
> has DEVICE_NATIVE_ENDIAN
> set to match the behavior seen.

OK.

[...]
>=C2=A0 =C2=A0 =C2=A0 >=C2=A0 =C2=A0 =C2=A0+static const MemoryRegion= Ops aw_h3_sdhost_ops =3D {
>=C2=A0 =C2=A0 =C2=A0 >=C2=A0 =C2=A0 =C2=A0+=C2=A0 =C2=A0 .read =3D a= w_h3_sdhost_read,
>=C2=A0 =C2=A0 =C2=A0 >=C2=A0 =C2=A0 =C2=A0+=C2=A0 =C2=A0 .write =3D = aw_h3_sdhost_write,
>=C2=A0 =C2=A0 =C2=A0 >=C2=A0 =C2=A0 =C2=A0+=C2=A0 =C2=A0 .endianness= =3D DEVICE_NATIVE_ENDIAN,
>
>=C2=A0 =C2=A0 =C2=A0I haven't checked .valid accesses from the data= sheet.
>
>=C2=A0 =C2=A0 =C2=A0However due to:
>
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0res =3D s->data_crc[((offset - REG= _SD_DATA7_CRC) / sizeof(uint32_t))];
>
>=C2=A0 =C2=A0 =C2=A0You seem to expect:
>
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 .impl.mi= n_access_size =3D 4,
>
>=C2=A0 =C2=A0 =C2=A0.impl.max_access_size unset is 8, which should work= s.
>
> It seems that all registers are aligned on at least 32-bit boundaries.=
> And the section 5.3.5.1 mentions
> that the DMA descriptors must be stored in memory 32-bit aligned. So <= br> > based on that information,

So you are describing ".valid.min_access_size =3D 4", which is th= e minimum
access size on the bus.
".impl.min_access_size" is different, it is what access sizes is = ready
to handle your model.
Your model read/write handlers expect addresses aligned on 32-bit
boundary, this is why I suggested to use ".impl.min_access_size =3D 4&= quot;. If
the guest were using a 16-bit access, your model would be buggy. If you describe your implementation to accept minimum 32-bit and the guest is
allowed to use smaller accesses, QEMU will do a 32-bit access to the
device, and return the 16-bit part to the guest. This way your model is safe. This is done by access_with_adjusted_size() in memory.c.
If you restrict with ".valid.min_access_size =3D 4", you might th= ink we
don't need ".valid.min_access_size =3D 4" because all access = from guest
will be at least 32-bit. However keep in mind someone might find this
device in another datasheet not limited to 32-bit, and let's say change=
to ".valid.min_access_size =3D 2". Without ".impl.min_access= _size =3D 4"
your model is buggy. So to be safe I'd use:

=C2=A0 =C2=A0.impl.min_access_size =3D 4,
=C2=A0 =C2=A0.valid.min_access_size =3D 4,

<= div>Now it makes more sense to me, thanks Philippe for explaining this!
=
Great, I'll add .impl.min_access_size =3D 4.

<= /div>
At this point, I've processed all the feedback that I receive= d for all of the patches
in this series. Is there anything else y= ou would like to see/discuss/review, or shall I send the v2 when I finish t= esting?

Regards,
Niek
=


> I think 32-bit is a safe choice. I've verified this with Linux mai= nline
> and U-Boot drivers and both are still working.

Regards,

Phil.



--
Niek Linnenbank

--000000000000c39ead0599d776e2-- From MAILER-DAEMON Mon Dec 16 15:48:20 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1igxHv-0006tg-VN for mharc-qemu-arm@gnu.org; Mon, 16 Dec 2019 15:48:19 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:36233) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1igxHs-0006tQ-2D for qemu-arm@nongnu.org; Mon, 16 Dec 2019 15:48:18 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1igxHo-0006Hs-DV for qemu-arm@nongnu.org; Mon, 16 Dec 2019 15:48:13 -0500 Received: from us-smtp-1.mimecast.com ([207.211.31.81]:56311 helo=us-smtp-delivery-1.mimecast.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1igxHn-0006GK-UX for qemu-arm@nongnu.org; Mon, 16 Dec 2019 15:48:12 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1576529291; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding; bh=+Fxv/08Xa0VbcqCSvsm0VgrWIKaPNFsllFhCVnw+YLI=; b=SAZq1dLaiyjjq8I1hzXpiBv+2GUA7ikRYoltPQLwXLcaaw1h7gxM7FG20YIqUE1i080/An bRF2tGA0lfWaZxWhBnmdqwkLaPh78osqDtjt4K/rB6jKaCsj+j0vbxNbgDw2XxImgmzMTw rOqHomWrPBKqWCjzMtsgwYbV++J+/Ro= Received: from mimecast-mx01.redhat.com (mimecast-mx01.redhat.com [209.132.183.4]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-327-_3L8DJ-vNPWrTcGnvlpMrw-1; Mon, 16 Dec 2019 15:48:09 -0500 X-MC-Unique: _3L8DJ-vNPWrTcGnvlpMrw-1 Received: from smtp.corp.redhat.com (int-mx04.intmail.prod.int.phx2.redhat.com [10.5.11.14]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx01.redhat.com (Postfix) with ESMTPS id 9B4708D811D; Mon, 16 Dec 2019 20:48:07 +0000 (UTC) Received: from laptop.redhat.com (ovpn-116-117.ams2.redhat.com [10.36.116.117]) by smtp.corp.redhat.com (Postfix) with ESMTP id 6C11B5D9C9; Mon, 16 Dec 2019 20:48:01 +0000 (UTC) From: Eric Auger To: eric.auger.pro@gmail.com, eric.auger@redhat.com, maz@kernel.org, kvmarm@lists.cs.columbia.edu, kvm@vger.kernel.org, qemu-devel@nongnu.org, qemu-arm@nongnu.org Cc: drjones@redhat.com, andrew.murray@arm.com, andre.przywara@arm.com, peter.maydell@linaro.org, alexandru.elisei@arm.com Subject: [kvm-unit-tests PATCH 00/10] KVM: arm64: PMUv3 Event Counter Tests Date: Mon, 16 Dec 2019 21:47:47 +0100 Message-Id: <20191216204757.4020-1-eric.auger@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.79 on 10.5.11.14 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 207.211.31.81 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 16 Dec 2019 20:48:18 -0000 This series implements tests exercising the PMUv3 event counters. It tests both the 32-bit and 64-bit versions. Overflow interrupts also are checked. Those tests only are written for arm64. It allowed to reveal some issues related to SW_INCR implementation (esp. related to 64-bit implementation), some problems related to 32-bit <-> 64-bit transitions and consistency of enabled states of odd and event counters. Overflow interrupt testing relies of one patch from Andre ("arm: gic: Provide per-IRQ helper functions") to enable the PPI 23, coming from "arm: gic: Test SPIs and interrupt groups" (https://patchwork.kernel.org/cover/11234975/). Drew kindly provided "arm64: Provide read/write_sysreg_s". All PMU tests can be launched with: ./run_tests.sh -g pmu Tests also can be launched individually. For example: ./arm-run arm/pmu.flat -append 'chained-sw-incr' With KVM: - chain-promotion and chained-sw-incr are known to be failing. - Problems were reported upstream. With TCG: - pmu-event-introspection is failing due to missing required events (we may remove this from TCG actually) - chained-sw-incr also fails. I haven't investigated yet. The series can be found at: https://github.com/eauger/kut/tree/pmu_event_counters_v1 History: v1 -> v2: - Use new report() proto - Style cleanup - do not warn about ARM spec recommendations - add a comment about PMCEID0/1 splits Andre Przywara (1): arm: gic: Provide per-IRQ helper functions Andrew Jones (1): arm64: Provide read/write_sysreg_s Eric Auger (8): arm: pmu: Let pmu tests take a sub-test parameter arm: pmu: Add a pmu struct arm: pmu: Check Required Event Support arm: pmu: Basic event counter Tests arm: pmu: Test chained counter arm: pmu: test 32-bit <-> 64-bit transitions arm/arm64: gic: Introduce setup_irq() helper arm: pmu: Test overflow interrupts arm/gic.c | 24 +- arm/pmu.c | 783 ++++++++++++++++++++++++++++++++++++++++- arm/unittests.cfg | 55 ++- lib/arm/asm/gic-v3.h | 2 + lib/arm/asm/gic.h | 12 + lib/arm/gic.c | 101 ++++++ lib/arm64/asm/sysreg.h | 11 + 7 files changed, 950 insertions(+), 38 deletions(-) --=20 2.20.1 From MAILER-DAEMON Mon Dec 16 15:48:22 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1igxHx-0006wX-W9 for mharc-qemu-arm@gnu.org; Mon, 16 Dec 2019 15:48:22 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:36271) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1igxHv-0006te-7q for qemu-arm@nongnu.org; Mon, 16 Dec 2019 15:48:20 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1igxHu-0006N1-B8 for qemu-arm@nongnu.org; Mon, 16 Dec 2019 15:48:19 -0500 Received: from us-smtp-delivery-1.mimecast.com ([207.211.31.120]:35147 helo=us-smtp-1.mimecast.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1igxHu-0006LJ-7g for qemu-arm@nongnu.org; Mon, 16 Dec 2019 15:48:18 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1576529294; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=5QgGQR5lmCzHdU2tw8u26Dp0LVz138MaKuXfv7AyzLc=; b=JuT3wKT0NUxnVUL8Gyg/dpTnyQoBym9nVOgh7O523VxgLg16wTTrR8XwacysfLy3N4Z3VT pxi4oGbx5gpTW6aOO6jv28TTY0FisaXEoQltAep1ztiMamCqhIvgZ3s0jEZoRVpnKQbU75 Im3JH9SwdXCDxTxbinBcqRvqPOntw8c= Received: from mimecast-mx01.redhat.com (mimecast-mx01.redhat.com [209.132.183.4]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-209-BnUFytWeO2mWLhhFFJvweA-1; Mon, 16 Dec 2019 15:48:12 -0500 X-MC-Unique: BnUFytWeO2mWLhhFFJvweA-1 Received: from smtp.corp.redhat.com (int-mx04.intmail.prod.int.phx2.redhat.com [10.5.11.14]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx01.redhat.com (Postfix) with ESMTPS id AA7BC108EE8B; Mon, 16 Dec 2019 20:48:10 +0000 (UTC) Received: from laptop.redhat.com (ovpn-116-117.ams2.redhat.com [10.36.116.117]) by smtp.corp.redhat.com (Postfix) with ESMTP id F38875D9C9; Mon, 16 Dec 2019 20:48:07 +0000 (UTC) From: Eric Auger To: eric.auger.pro@gmail.com, eric.auger@redhat.com, maz@kernel.org, kvmarm@lists.cs.columbia.edu, kvm@vger.kernel.org, qemu-devel@nongnu.org, qemu-arm@nongnu.org Cc: drjones@redhat.com, andrew.murray@arm.com, andre.przywara@arm.com, peter.maydell@linaro.org, alexandru.elisei@arm.com Subject: [kvm-unit-tests PATCH 01/10] arm64: Provide read/write_sysreg_s Date: Mon, 16 Dec 2019 21:47:48 +0100 Message-Id: <20191216204757.4020-2-eric.auger@redhat.com> In-Reply-To: <20191216204757.4020-1-eric.auger@redhat.com> References: <20191216204757.4020-1-eric.auger@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.79 on 10.5.11.14 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 207.211.31.120 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 16 Dec 2019 20:48:20 -0000 From: Andrew Jones Sometimes we need to test access to system registers which are missing assembler mnemonics. Signed-off-by: Andrew Jones Reviewed-by: Alexandru Elisei --- lib/arm64/asm/sysreg.h | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/lib/arm64/asm/sysreg.h b/lib/arm64/asm/sysreg.h index a03830b..a45eebd 100644 --- a/lib/arm64/asm/sysreg.h +++ b/lib/arm64/asm/sysreg.h @@ -38,6 +38,17 @@ asm volatile("msr " xstr(r) ", %x0" : : "rZ" (__val)); \ } while (0) =20 +#define read_sysreg_s(r) ({ \ + u64 __val; \ + asm volatile("mrs_s %0, " xstr(r) : "=3Dr" (__val)); \ + __val; \ +}) + +#define write_sysreg_s(v, r) do { \ + u64 __val =3D (u64)v; \ + asm volatile("msr_s " xstr(r) ", %x0" : : "rZ" (__val));\ +} while (0) + asm( " .irp num,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23= ,24,25,26,27,28,29,30\n" " .equ .L__reg_num_x\\num, \\num\n" --=20 2.20.1 From MAILER-DAEMON Mon Dec 16 15:48:24 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1igxI0-00070v-Dp for mharc-qemu-arm@gnu.org; Mon, 16 Dec 2019 15:48:24 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:36302) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1igxHw-0006ue-SR for qemu-arm@nongnu.org; Mon, 16 Dec 2019 15:48:21 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1igxHv-0006Np-Pz for qemu-arm@nongnu.org; Mon, 16 Dec 2019 15:48:20 -0500 Received: from us-smtp-2.mimecast.com ([205.139.110.61]:23274 helo=us-smtp-delivery-1.mimecast.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1igxHv-0006NL-Lw for qemu-arm@nongnu.org; Mon, 16 Dec 2019 15:48:19 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1576529298; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=UXlYDyzqTLtrcUrTm0BlWqi6aN682MJ2N066VEjbccE=; b=hMiI9ttB+Q9F3kNdHjV7emdT4CdCJ96XB5LjELJt5G2ex459Qu6VUTjJh9fK8N41pnUnBx aPrBx+liVliuppeFJGHKBTx6F3bLJSH6uc144LYwXo8oxYTL8jHpTY6QpzhaoDvsFyd5Jj CZqv/KD67/JQWwphl1WQUJaGkuq4V0o= Received: from mimecast-mx01.redhat.com (mimecast-mx01.redhat.com [209.132.183.4]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-200-9IPC6q1fOY-jzKGQ4MZISw-1; Mon, 16 Dec 2019 15:48:17 -0500 X-MC-Unique: 9IPC6q1fOY-jzKGQ4MZISw-1 Received: from smtp.corp.redhat.com (int-mx04.intmail.prod.int.phx2.redhat.com [10.5.11.14]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx01.redhat.com (Postfix) with ESMTPS id 61C0619264B2; Mon, 16 Dec 2019 20:48:15 +0000 (UTC) Received: from laptop.redhat.com (ovpn-116-117.ams2.redhat.com [10.36.116.117]) by smtp.corp.redhat.com (Postfix) with ESMTP id 0E7ED5D9C9; Mon, 16 Dec 2019 20:48:10 +0000 (UTC) From: Eric Auger To: eric.auger.pro@gmail.com, eric.auger@redhat.com, maz@kernel.org, kvmarm@lists.cs.columbia.edu, kvm@vger.kernel.org, qemu-devel@nongnu.org, qemu-arm@nongnu.org Cc: drjones@redhat.com, andrew.murray@arm.com, andre.przywara@arm.com, peter.maydell@linaro.org, alexandru.elisei@arm.com Subject: [kvm-unit-tests PATCH 02/10] arm: pmu: Let pmu tests take a sub-test parameter Date: Mon, 16 Dec 2019 21:47:49 +0100 Message-Id: <20191216204757.4020-3-eric.auger@redhat.com> In-Reply-To: <20191216204757.4020-1-eric.auger@redhat.com> References: <20191216204757.4020-1-eric.auger@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.79 on 10.5.11.14 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 205.139.110.61 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 16 Dec 2019 20:48:23 -0000 As we intend to introduce more PMU tests, let's add a sub-test parameter that will allow to categorize them. Existing tests are in the cycle-counter category. Signed-off-by: Eric Auger --- arm/pmu.c | 24 +++++++++++++++--------- arm/unittests.cfg | 7 ++++--- 2 files changed, 19 insertions(+), 12 deletions(-) diff --git a/arm/pmu.c b/arm/pmu.c index d5a03a6..e5e012d 100644 --- a/arm/pmu.c +++ b/arm/pmu.c @@ -287,22 +287,28 @@ int main(int argc, char *argv[]) { int cpi =3D 0; =20 - if (argc > 1) - cpi =3D atol(argv[1]); - if (!pmu_probe()) { printf("No PMU found, test skipped...\n"); return report_summary(); } =20 + if (argc < 2) + report_abort("no test specified"); + report_prefix_push("pmu"); =20 - report(check_pmcr(), "Control register"); - report(check_cycles_increase(), - "Monotonically increasing cycle count"); - report(check_cpi(cpi), "Cycle/instruction ratio"); - - pmccntr64_test(); + if (strcmp(argv[1], "cycle-counter") =3D=3D 0) { + report_prefix_push(argv[1]); + if (argc > 2) + cpi =3D atol(argv[2]); + report(check_pmcr(), "Control register"); + report(check_cycles_increase(), + "Monotonically increasing cycle count"); + report(check_cpi(cpi), "Cycle/instruction ratio"); + pmccntr64_test(); + } else { + report_abort("Unknown sub-test '%s'", argv[1]); + } =20 return report_summary(); } diff --git a/arm/unittests.cfg b/arm/unittests.cfg index daeb5a0..79f0d7a 100644 --- a/arm/unittests.cfg +++ b/arm/unittests.cfg @@ -61,21 +61,22 @@ file =3D pci-test.flat groups =3D pci =20 # Test PMU support -[pmu] +[pmu-cycle-counter] file =3D pmu.flat groups =3D pmu +extra_params =3D -append 'cycle-counter 0' =20 # Test PMU support (TCG) with -icount IPC=3D1 #[pmu-tcg-icount-1] #file =3D pmu.flat -#extra_params =3D -icount 0 -append '1' +#extra_params =3D -icount 0 -append 'cycle-counter 1' #groups =3D pmu #accel =3D tcg =20 # Test PMU support (TCG) with -icount IPC=3D256 #[pmu-tcg-icount-256] #file =3D pmu.flat -#extra_params =3D -icount 8 -append '256' +#extra_params =3D -icount 8 -append 'cycle-counter 256' #groups =3D pmu #accel =3D tcg =20 --=20 2.20.1 From MAILER-DAEMON Mon Dec 16 15:48:27 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1igxI3-00076f-M9 for mharc-qemu-arm@gnu.org; Mon, 16 Dec 2019 15:48:27 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:36331) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1igxI0-00070R-0U for qemu-arm@nongnu.org; Mon, 16 Dec 2019 15:48:25 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1igxHy-0006QU-SX for qemu-arm@nongnu.org; Mon, 16 Dec 2019 15:48:23 -0500 Received: from us-smtp-1.mimecast.com ([207.211.31.81]:20548 helo=us-smtp-delivery-1.mimecast.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1igxHy-0006QF-Ou for qemu-arm@nongnu.org; Mon, 16 Dec 2019 15:48:22 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1576529302; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=Dznikfzn+n4WX4926tiKNygB6iX1YlaEs/0YdUiJxdA=; b=FzPSZZR3GUMf2K+z7Zw2QA5KFlhZJiyH/IcqTvVNehhY9SmFu61xIaVkaBlz9BGZi4VQOS RO6BNVdTvkn4RcVTPcTnsMb5IEjMGRVpD53OqjHJaV3023SCSb8qG4NgHASfusH6BOI+pR YfSGTATomzPNvOat6DcdIj4NRxJukRc= Received: from mimecast-mx01.redhat.com (mimecast-mx01.redhat.com [209.132.183.4]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-63-ZsCK1exoNFqIWFgq7Whmzw-1; Mon, 16 Dec 2019 15:48:20 -0500 X-MC-Unique: ZsCK1exoNFqIWFgq7Whmzw-1 Received: from smtp.corp.redhat.com (int-mx04.intmail.prod.int.phx2.redhat.com [10.5.11.14]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx01.redhat.com (Postfix) with ESMTPS id 6D5B28E10CF; Mon, 16 Dec 2019 20:48:18 +0000 (UTC) Received: from laptop.redhat.com (ovpn-116-117.ams2.redhat.com [10.36.116.117]) by smtp.corp.redhat.com (Postfix) with ESMTP id B9BA65D9C9; Mon, 16 Dec 2019 20:48:15 +0000 (UTC) From: Eric Auger To: eric.auger.pro@gmail.com, eric.auger@redhat.com, maz@kernel.org, kvmarm@lists.cs.columbia.edu, kvm@vger.kernel.org, qemu-devel@nongnu.org, qemu-arm@nongnu.org Cc: drjones@redhat.com, andrew.murray@arm.com, andre.przywara@arm.com, peter.maydell@linaro.org, alexandru.elisei@arm.com Subject: [kvm-unit-tests PATCH 03/10] arm: pmu: Add a pmu struct Date: Mon, 16 Dec 2019 21:47:50 +0100 Message-Id: <20191216204757.4020-4-eric.auger@redhat.com> In-Reply-To: <20191216204757.4020-1-eric.auger@redhat.com> References: <20191216204757.4020-1-eric.auger@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.79 on 10.5.11.14 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 207.211.31.81 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 16 Dec 2019 20:48:26 -0000 This struct aims at storing information potentially used by all tests such as the pmu version, the read-only part of the PMCR, the number of implemented event counters, ... Signed-off-by: Eric Auger --- arm/pmu.c | 30 +++++++++++++++++++++++++----- 1 file changed, 25 insertions(+), 5 deletions(-) diff --git a/arm/pmu.c b/arm/pmu.c index e5e012d..d24857e 100644 --- a/arm/pmu.c +++ b/arm/pmu.c @@ -33,7 +33,14 @@ =20 #define NR_SAMPLES 10 =20 -static unsigned int pmu_version; +struct pmu { + unsigned int version; + unsigned int nb_implemented_counters; + uint32_t pmcr_ro; +}; + +static struct pmu pmu; + #if defined(__arm__) #define ID_DFR0_PERFMON_SHIFT 24 #define ID_DFR0_PERFMON_MASK 0xf @@ -265,7 +272,7 @@ static bool check_cpi(int cpi) static void pmccntr64_test(void) { #ifdef __arm__ - if (pmu_version =3D=3D 0x3) { + if (pmu.version =3D=3D 0x3) { if (ERRATA(9e3f7a296940)) { write_sysreg(0xdead, PMCCNTR64); report(read_sysreg(PMCCNTR64) =3D=3D 0xdead, "pmccntr64"); @@ -278,9 +285,22 @@ static void pmccntr64_test(void) /* Return FALSE if no PMU found, otherwise return TRUE */ static bool pmu_probe(void) { - pmu_version =3D get_pmu_version(); - report_info("PMU version: %d", pmu_version); - return pmu_version !=3D 0 && pmu_version !=3D 0xf; + uint32_t pmcr; + + pmu.version =3D get_pmu_version(); + report_info("PMU version: %d", pmu.version); + + if (pmu.version =3D=3D 0 || pmu.version =3D=3D 0xF) + return false; + + pmcr =3D get_pmcr(); + pmu.pmcr_ro =3D pmcr & 0xFFFFFF80; + pmu.nb_implemented_counters =3D + (pmcr >> PMU_PMCR_N_SHIFT) & PMU_PMCR_N_MASK; + report_info("Implements %d event counters", + pmu.nb_implemented_counters); + + return true; } =20 int main(int argc, char *argv[]) --=20 2.20.1 From MAILER-DAEMON Mon Dec 16 15:48:31 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1igxI6-0007CE-SK for mharc-qemu-arm@gnu.org; Mon, 16 Dec 2019 15:48:30 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:36362) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1igxI3-00076i-LG for qemu-arm@nongnu.org; Mon, 16 Dec 2019 15:48:28 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1igxI2-0006SL-Bh for qemu-arm@nongnu.org; Mon, 16 Dec 2019 15:48:27 -0500 Received: from us-smtp-delivery-1.mimecast.com ([207.211.31.120]:42605 helo=us-smtp-1.mimecast.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1igxI2-0006S9-8Y for qemu-arm@nongnu.org; Mon, 16 Dec 2019 15:48:26 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1576529305; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=RjCVoMYbyhxjOhuGwZyyYSLknIArKPWpJID9BdwLtBQ=; b=EWvssBwAfF3kiNCaCHP/LtVmyytVcJOFoi/rO5523lPY4xaj3ZKizHEEQUL7S+OxXHY/nB K0fmYedCWCmsvpc1/qV3CzmJaUClivNmrG9PUVn+sAKXW4LxltWrJ/l2s60BTdfmt+X3O/ gyOFNgVJulAaUJ5olHlrTcBUgT+5z3w= Received: from mimecast-mx01.redhat.com (mimecast-mx01.redhat.com [209.132.183.4]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-129-mAQz2_z2MAmqowES4roMzw-1; Mon, 16 Dec 2019 15:48:24 -0500 X-MC-Unique: mAQz2_z2MAmqowES4roMzw-1 Received: from smtp.corp.redhat.com (int-mx04.intmail.prod.int.phx2.redhat.com [10.5.11.14]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx01.redhat.com (Postfix) with ESMTPS id 7B6C98024E5; Mon, 16 Dec 2019 20:48:21 +0000 (UTC) Received: from laptop.redhat.com (ovpn-116-117.ams2.redhat.com [10.36.116.117]) by smtp.corp.redhat.com (Postfix) with ESMTP id C42505D9C9; Mon, 16 Dec 2019 20:48:18 +0000 (UTC) From: Eric Auger To: eric.auger.pro@gmail.com, eric.auger@redhat.com, maz@kernel.org, kvmarm@lists.cs.columbia.edu, kvm@vger.kernel.org, qemu-devel@nongnu.org, qemu-arm@nongnu.org Cc: drjones@redhat.com, andrew.murray@arm.com, andre.przywara@arm.com, peter.maydell@linaro.org, alexandru.elisei@arm.com Subject: [kvm-unit-tests PATCH 04/10] arm: pmu: Check Required Event Support Date: Mon, 16 Dec 2019 21:47:51 +0100 Message-Id: <20191216204757.4020-5-eric.auger@redhat.com> In-Reply-To: <20191216204757.4020-1-eric.auger@redhat.com> References: <20191216204757.4020-1-eric.auger@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.79 on 10.5.11.14 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 207.211.31.120 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 16 Dec 2019 20:48:29 -0000 If event counters are implemented check the common events required by the PMUv3 are implemented. Some are unconditionally required (SW_INCR, CPU_CYCLES, either INST_RETIRED or INST_SPEC). Some others only are required if the implementation implements some other features. Check those wich are unconditionally required. This test currently fails on TCG as neither INST_RETIRED or INST_SPEC are supported. Signed-off-by: Eric Auger --- v1 ->v2: - add a comment to explain the PMCEID0/1 splits --- arm/pmu.c | 71 +++++++++++++++++++++++++++++++++++++++++++++++ arm/unittests.cfg | 6 ++++ 2 files changed, 77 insertions(+) diff --git a/arm/pmu.c b/arm/pmu.c index d24857e..d88ef22 100644 --- a/arm/pmu.c +++ b/arm/pmu.c @@ -101,6 +101,10 @@ static inline void precise_instrs_loop(int loop, uin= t32_t pmcr) : [pmcr] "r" (pmcr), [z] "r" (0) : "cc"); } + +/* event counter tests only implemented for aarch64 */ +static void test_event_introspection(void) {} + #elif defined(__aarch64__) #define ID_AA64DFR0_PERFMON_SHIFT 8 #define ID_AA64DFR0_PERFMON_MASK 0xf @@ -139,6 +143,70 @@ static inline void precise_instrs_loop(int loop, uin= t32_t pmcr) : [pmcr] "r" (pmcr) : "cc"); } + +#define PMCEID1_EL0 sys_reg(11, 3, 9, 12, 7) + +static bool is_event_supported(uint32_t n, bool warn) +{ + uint64_t pmceid0 =3D read_sysreg(pmceid0_el0); + uint64_t pmceid1 =3D read_sysreg_s(PMCEID1_EL0); + bool supported; + uint32_t reg; + + /* + * The low 32-bits of PMCEID0/1 respectly describe + * event support for events 0-31/32-63. Their High + * 32-bits describe support for extended events + * starting at 0x4000, using the same split. + */ + if (n >=3D 0x0 && n <=3D 0x1F) + reg =3D pmceid0 & 0xFFFFFFFF; + else if (n >=3D 0x4000 && n <=3D 0x401F) + reg =3D pmceid0 >> 32; + else if (n >=3D 0x20 && n <=3D 0x3F) + reg =3D pmceid1 & 0xFFFFFFFF; + else if (n >=3D 0x4020 && n <=3D 0x403F) + reg =3D pmceid1 >> 32; + else + abort(); + + supported =3D reg & (1 << n); + if (!supported && warn) + report_info("event %d is not supported", n); + return supported; +} + +static void test_event_introspection(void) +{ + bool required_events; + + if (!pmu.nb_implemented_counters) { + report_skip("No event counter, skip ..."); + return; + } + + /* PMUv3 requires an implementation includes some common events */ + required_events =3D is_event_supported(0x0, true) /* SW_INCR */ && + is_event_supported(0x11, true) /* CPU_CYCLES */ && + (is_event_supported(0x8, true) /* INST_RETIRED */ || + is_event_supported(0x1B, true) /* INST_PREC */); + + if (pmu.version =3D=3D 0x4) { + /* ARMv8.1 PMU: STALL_FRONTEND and STALL_BACKEND are required */ + required_events =3D required_events || + is_event_supported(0x23, true) || + is_event_supported(0x24, true); + } + + /* + * L1D_CACHE_REFILL(0x3) and L1D_CACHE(0x4) are only required if + * L1 data / unified cache. BR_MIS_PRED(0x10), BR_PRED(0x12) are only + * required if program-flow prediction is implemented. + */ + + report(required_events, "Check required events are implemented"); +} + #endif =20 /* @@ -326,6 +394,9 @@ int main(int argc, char *argv[]) "Monotonically increasing cycle count"); report(check_cpi(cpi), "Cycle/instruction ratio"); pmccntr64_test(); + } else if (strcmp(argv[1], "event-introspection") =3D=3D 0) { + report_prefix_push(argv[1]); + test_event_introspection(); } else { report_abort("Unknown sub-test '%s'", argv[1]); } diff --git a/arm/unittests.cfg b/arm/unittests.cfg index 79f0d7a..4433ef3 100644 --- a/arm/unittests.cfg +++ b/arm/unittests.cfg @@ -66,6 +66,12 @@ file =3D pmu.flat groups =3D pmu extra_params =3D -append 'cycle-counter 0' =20 +[pmu-event-introspection] +file =3D pmu.flat +groups =3D pmu +arch =3D arm64 +extra_params =3D -append 'event-introspection' + # Test PMU support (TCG) with -icount IPC=3D1 #[pmu-tcg-icount-1] #file =3D pmu.flat --=20 2.20.1 From MAILER-DAEMON Mon Dec 16 15:48:38 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1igxIE-0007Qj-2w for mharc-qemu-arm@gnu.org; Mon, 16 Dec 2019 15:48:38 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:36388) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1igxIA-0007J2-OD for qemu-arm@nongnu.org; Mon, 16 Dec 2019 15:48:36 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1igxI9-0006WG-8K for qemu-arm@nongnu.org; Mon, 16 Dec 2019 15:48:34 -0500 Received: from us-smtp-delivery-1.mimecast.com ([207.211.31.120]:54531 helo=us-smtp-1.mimecast.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1igxI9-0006W3-3u for qemu-arm@nongnu.org; Mon, 16 Dec 2019 15:48:33 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1576529312; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=tjYVs+BNNU240LHN8Sh/MBUq5QkpqVGcrM9TYOWuLzo=; b=a7B9y4NZVrX1mWetk7GyO+COcOscsiQ9+6FLayeVndni+q/qJZFvBYWpzqCtLFrQF0xTAE jawjG4swE4JilDrsU8MN+z5e8EfsBjlA5Q53val0bCnDKBAOzXWkukdgX36xS485z8g2M6 Gc6RD8JFBX3EtIl4efelECJZGw59e0M= Received: from mimecast-mx01.redhat.com (mimecast-mx01.redhat.com [209.132.183.4]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-401-N7zJNoN6MZy9JS5P6-AjUQ-1; Mon, 16 Dec 2019 15:48:31 -0500 X-MC-Unique: N7zJNoN6MZy9JS5P6-AjUQ-1 Received: from smtp.corp.redhat.com (int-mx04.intmail.prod.int.phx2.redhat.com [10.5.11.14]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx01.redhat.com (Postfix) with ESMTPS id CEEF78024EB; Mon, 16 Dec 2019 20:48:29 +0000 (UTC) Received: from laptop.redhat.com (ovpn-116-117.ams2.redhat.com [10.36.116.117]) by smtp.corp.redhat.com (Postfix) with ESMTP id 251135D9C9; Mon, 16 Dec 2019 20:48:26 +0000 (UTC) From: Eric Auger To: eric.auger.pro@gmail.com, eric.auger@redhat.com, maz@kernel.org, kvmarm@lists.cs.columbia.edu, kvm@vger.kernel.org, qemu-devel@nongnu.org, qemu-arm@nongnu.org Cc: drjones@redhat.com, andrew.murray@arm.com, andre.przywara@arm.com, peter.maydell@linaro.org, alexandru.elisei@arm.com Subject: [kvm-unit-tests PATCH 06/10] arm: pmu: Test chained counter Date: Mon, 16 Dec 2019 21:47:53 +0100 Message-Id: <20191216204757.4020-7-eric.auger@redhat.com> In-Reply-To: <20191216204757.4020-1-eric.auger@redhat.com> References: <20191216204757.4020-1-eric.auger@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.79 on 10.5.11.14 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 207.211.31.120 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 16 Dec 2019 20:48:37 -0000 Add 2 tests exercising chained counters. The first one uses CPU_CYCLES and the second one uses SW_INCR. Signed-off-by: Eric Auger --- arm/pmu.c | 128 ++++++++++++++++++++++++++++++++++++++++++++++ arm/unittests.cfg | 12 +++++ 2 files changed, 140 insertions(+) diff --git a/arm/pmu.c b/arm/pmu.c index 139dae3..ad98771 100644 --- a/arm/pmu.c +++ b/arm/pmu.c @@ -113,6 +113,8 @@ static void test_event_introspection(void) {} static void test_event_counter_config(void) {} static void test_basic_event_count(void) {} static void test_mem_access(void) {} +static void test_chained_counters(void) {} +static void test_chained_sw_incr(void) {} =20 #elif defined(__aarch64__) #define ID_AA64DFR0_PERFMON_SHIFT 8 @@ -459,6 +461,126 @@ static void test_mem_access(void) read_sysreg(pmovsclr_el0)); } =20 +static void test_chained_counters(void) +{ + uint32_t events[] =3D { 0x11 /* CPU_CYCLES */, 0x1E /* CHAIN */}; + + if (!satisfy_prerequisites(events, ARRAY_SIZE(events))) + return; + + pmu_reset(); + + write_regn(pmevtyper, 0, events[0] | PMEVTYPER_EXCLUDE_EL0); + write_regn(pmevtyper, 1, events[1] | PMEVTYPER_EXCLUDE_EL0); + /* enable counters #0 and #1 */ + write_sysreg_s(0x3, PMCNTENSET_EL0); + /* preset counter #0 at 0xFFFFFFF0 */ + write_regn(pmevcntr, 0, 0xFFFFFFF0); + + precise_instrs_loop(22, pmu.pmcr_ro | PMU_PMCR_E); + + report(read_regn(pmevcntr, 1) =3D=3D 1, "CHAIN counter #1 incremented")= ; + report(!read_sysreg(pmovsclr_el0), "check no overflow is recorded"); + + /* test 64b overflow */ + + pmu_reset(); + write_sysreg_s(0x3, PMCNTENSET_EL0); + + write_regn(pmevcntr, 0, 0xFFFFFFF0); + write_regn(pmevcntr, 1, 0x1); + precise_instrs_loop(22, pmu.pmcr_ro | PMU_PMCR_E); + report_info("overflow reg =3D 0x%lx", read_sysreg(pmovsclr_el0)); + report(read_regn(pmevcntr, 1) =3D=3D 2, "CHAIN counter #1 incremented")= ; + report(!read_sysreg(pmovsclr_el0), "check no overflow is recorded"); + + write_regn(pmevcntr, 0, 0xFFFFFFF0); + write_regn(pmevcntr, 1, 0xFFFFFFFF); + + precise_instrs_loop(22, pmu.pmcr_ro | PMU_PMCR_E); + report_info("overflow reg =3D 0x%lx", read_sysreg(pmovsclr_el0)); + report(!read_regn(pmevcntr, 1), "CHAIN counter #1 wrapped"); + report(read_sysreg(pmovsclr_el0) =3D=3D 0x2, + "check no overflow is recorded"); +} + +static void test_chained_sw_incr(void) +{ + uint32_t events[] =3D { 0x0 /* SW_INCR */, 0x0 /* SW_INCR */}; + int i; + + if (!satisfy_prerequisites(events, ARRAY_SIZE(events))) + return; + + pmu_reset(); + + write_regn(pmevtyper, 0, events[0] | PMEVTYPER_EXCLUDE_EL0); + write_regn(pmevtyper, 1, events[1] | PMEVTYPER_EXCLUDE_EL0); + /* enable counters #0 and #1 */ + write_sysreg_s(0x3, PMCNTENSET_EL0); + + /* preset counter #0 at 0xFFFFFFF0 */ + write_regn(pmevcntr, 0, 0xFFFFFFF0); + + for (i =3D 0; i < 100; i++) + write_sysreg(0x1, pmswinc_el0); + + report_info("SW_INCR counter #0 has value %ld", read_regn(pmevcntr, 0))= ; + report(read_regn(pmevcntr, 0) =3D=3D 0xFFFFFFF0, + "PWSYNC does not increment if PMCR.E is unset"); + + pmu_reset(); + + write_regn(pmevcntr, 0, 0xFFFFFFF0); + write_sysreg_s(0x3, PMCNTENSET_EL0); + set_pmcr(pmu.pmcr_ro | PMU_PMCR_E); + + for (i =3D 0; i < 100; i++) + write_sysreg(0x3, pmswinc_el0); + + report(read_regn(pmevcntr, 0) =3D=3D 84, "counter #1 after + 100 SW_IN= CR"); + report(read_regn(pmevcntr, 1) =3D=3D 100, + "counter #0 after + 100 SW_INCR"); + report_info("counter values after 100 SW_INCR #0=3D%ld #1=3D%ld", + read_regn(pmevcntr, 0), read_regn(pmevcntr, 1)); + report(read_sysreg(pmovsclr_el0) =3D=3D 0x1, + "overflow reg after 100 SW_INCR"); + + /* 64b SW_INCR */ + pmu_reset(); + + events[1] =3D 0x1E /* CHAIN */; + write_regn(pmevtyper, 1, events[1] | PMEVTYPER_EXCLUDE_EL0); + write_regn(pmevcntr, 0, 0xFFFFFFF0); + write_sysreg_s(0x3, PMCNTENSET_EL0); + set_pmcr(pmu.pmcr_ro | PMU_PMCR_E); + for (i =3D 0; i < 100; i++) + write_sysreg(0x3, pmswinc_el0); + + report(!read_sysreg(pmovsclr_el0) && (read_regn(pmevcntr, 1) =3D=3D 1), + "overflow reg after 100 SW_INCR/CHAIN"); + report_info("overflow=3D0x%lx, #0=3D%ld #1=3D%ld", read_sysreg(pmovsclr= _el0), + read_regn(pmevcntr, 0), read_regn(pmevcntr, 1)); + + /* 64b SW_INCR and overflow on CHAIN counter*/ + pmu_reset(); + + write_regn(pmevtyper, 1, events[1] | PMEVTYPER_EXCLUDE_EL0); + write_regn(pmevcntr, 0, 0xFFFFFFF0); + write_regn(pmevcntr, 1, 0xFFFFFFFF); + write_sysreg_s(0x3, PMCNTENSET_EL0); + set_pmcr(pmu.pmcr_ro | PMU_PMCR_E); + for (i =3D 0; i < 100; i++) + write_sysreg(0x3, pmswinc_el0); + + report((read_sysreg(pmovsclr_el0) =3D=3D 0x2) && + (read_regn(pmevcntr, 1) =3D=3D 0) && + (read_regn(pmevcntr, 0) =3D=3D 84), + "overflow reg after 100 SW_INCR/CHAIN"); + report_info("overflow=3D0x%lx, #0=3D%ld #1=3D%ld", read_sysreg(pmovsclr= _el0), + read_regn(pmevcntr, 0), read_regn(pmevcntr, 1)); +} + #endif =20 /* @@ -658,6 +780,12 @@ int main(int argc, char *argv[]) } else if (strcmp(argv[1], "mem-access") =3D=3D 0) { report_prefix_push(argv[1]); test_mem_access(); + } else if (strcmp(argv[1], "chained-counters") =3D=3D 0) { + report_prefix_push(argv[1]); + test_chained_counters(); + } else if (strcmp(argv[1], "chained-sw-incr") =3D=3D 0) { + report_prefix_push(argv[1]); + test_chained_sw_incr(); } else { report_abort("Unknown sub-test '%s'", argv[1]); } diff --git a/arm/unittests.cfg b/arm/unittests.cfg index 7a59403..1bd4319 100644 --- a/arm/unittests.cfg +++ b/arm/unittests.cfg @@ -90,6 +90,18 @@ groups =3D pmu arch =3D arm64 extra_params =3D -append 'mem-access' =20 +[pmu-chained-counters] +file =3D pmu.flat +groups =3D pmu +arch =3D arm64 +extra_params =3D -append 'chained-counters' + +[pmu-chained-sw-incr] +file =3D pmu.flat +groups =3D pmu +arch =3D arm64 +extra_params =3D -append 'chained-sw-incr' + # Test PMU support (TCG) with -icount IPC=3D1 #[pmu-tcg-icount-1] #file =3D pmu.flat --=20 2.20.1 From MAILER-DAEMON Mon Dec 16 15:48:39 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1igxIF-0007Sm-94 for mharc-qemu-arm@gnu.org; Mon, 16 Dec 2019 15:48:39 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:36396) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1igxIB-0007MP-Cq for qemu-arm@nongnu.org; Mon, 16 Dec 2019 15:48:37 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1igxI9-0006WR-FH for qemu-arm@nongnu.org; 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Mon, 16 Dec 2019 20:48:26 +0000 (UTC) Received: from laptop.redhat.com (ovpn-116-117.ams2.redhat.com [10.36.116.117]) by smtp.corp.redhat.com (Postfix) with ESMTP id D30645D9C9; Mon, 16 Dec 2019 20:48:21 +0000 (UTC) From: Eric Auger To: eric.auger.pro@gmail.com, eric.auger@redhat.com, maz@kernel.org, kvmarm@lists.cs.columbia.edu, kvm@vger.kernel.org, qemu-devel@nongnu.org, qemu-arm@nongnu.org Cc: drjones@redhat.com, andrew.murray@arm.com, andre.przywara@arm.com, peter.maydell@linaro.org, alexandru.elisei@arm.com Subject: [kvm-unit-tests PATCH 05/10] arm: pmu: Basic event counter Tests Date: Mon, 16 Dec 2019 21:47:52 +0100 Message-Id: <20191216204757.4020-6-eric.auger@redhat.com> In-Reply-To: <20191216204757.4020-1-eric.auger@redhat.com> References: <20191216204757.4020-1-eric.auger@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.79 on 10.5.11.14 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 207.211.31.81 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 16 Dec 2019 20:48:38 -0000 Adds the following tests: - event-counter-config: test event counter configuration - basic-event-count: - programs counters #0 and #1 to count 2 required events (resp. CPU_CYCLES and INST_RETIRED). Counter #0 is preset to a value close enough to the 32b overflow limit so that we check the overflow bit is set after the execution of the asm loop. - mem-access: counts MEM_ACCESS event on counters #0 and #1 with and without 32-bit overflow. Signed-off-by: Eric Auger --- arm/pmu.c | 261 ++++++++++++++++++++++++++++++++++++++++++++++ arm/unittests.cfg | 18 ++++ 2 files changed, 279 insertions(+) diff --git a/arm/pmu.c b/arm/pmu.c index d88ef22..139dae3 100644 --- a/arm/pmu.c +++ b/arm/pmu.c @@ -18,9 +18,15 @@ #include "asm/barrier.h" #include "asm/sysreg.h" #include "asm/processor.h" +#include +#include =20 #define PMU_PMCR_E (1 << 0) +#define PMU_PMCR_P (1 << 1) #define PMU_PMCR_C (1 << 2) +#define PMU_PMCR_D (1 << 3) +#define PMU_PMCR_X (1 << 4) +#define PMU_PMCR_DP (1 << 5) #define PMU_PMCR_LC (1 << 6) #define PMU_PMCR_N_SHIFT 11 #define PMU_PMCR_N_MASK 0x1f @@ -104,6 +110,9 @@ static inline void precise_instrs_loop(int loop, uint= 32_t pmcr) =20 /* event counter tests only implemented for aarch64 */ static void test_event_introspection(void) {} +static void test_event_counter_config(void) {} +static void test_basic_event_count(void) {} +static void test_mem_access(void) {} =20 #elif defined(__aarch64__) #define ID_AA64DFR0_PERFMON_SHIFT 8 @@ -145,6 +154,32 @@ static inline void precise_instrs_loop(int loop, uin= t32_t pmcr) } =20 #define PMCEID1_EL0 sys_reg(11, 3, 9, 12, 7) +#define PMCNTENSET_EL0 sys_reg(11, 3, 9, 12, 1) +#define PMCNTENCLR_EL0 sys_reg(11, 3, 9, 12, 2) + +#define PMEVTYPER_EXCLUDE_EL1 (1 << 31) +#define PMEVTYPER_EXCLUDE_EL0 (1 << 30) + +#define regn_el0(__reg, __n) __reg ## __n ## _el0 +#define write_regn(__reg, __n, __val) \ + write_sysreg((__val), __reg ## __n ## _el0) + +#define read_regn(__reg, __n) \ + read_sysreg(__reg ## __n ## _el0) + +#define print_pmevtyper(__s, __n) do { \ + uint32_t val; \ + val =3D read_regn(pmevtyper, __n);\ + report_info("%s pmevtyper%d=3D0x%x, eventcount=3D0x%x (p=3D%ld, u=3D%ld= nsk=3D%ld, nsu=3D%ld, nsh=3D%ld m=3D%ld, mt=3D%ld)", \ + (__s), (__n), val, val & 0xFFFF, \ + (BIT_MASK(31) & val) >> 31, \ + (BIT_MASK(30) & val) >> 30, \ + (BIT_MASK(29) & val) >> 29, \ + (BIT_MASK(28) & val) >> 28, \ + (BIT_MASK(27) & val) >> 27, \ + (BIT_MASK(26) & val) >> 26, \ + (BIT_MASK(25) & val) >> 25); \ + } while (0) =20 static bool is_event_supported(uint32_t n, bool warn) { @@ -207,6 +242,223 @@ static void test_event_introspection(void) report(required_events, "Check required events are implemented"); } =20 +static inline void mem_access_loop(void *addr, int loop, uint32_t pmcr) +{ +asm volatile( + " msr pmcr_el0, %[pmcr]\n" + " isb\n" + " mov x10, %[loop]\n" + "1: sub x10, x10, #1\n" + " mov x8, %[addr]\n" + " ldr x9, [x8]\n" + " cmp x10, #0x0\n" + " b.gt 1b\n" + " msr pmcr_el0, xzr\n" + " isb\n" + : + : [addr] "r" (addr), [pmcr] "r" (pmcr), [loop] "r" (loop) + : ); +} + + +static void pmu_reset(void) +{ + /* reset all counters, counting disabled at PMCR level*/ + set_pmcr(pmu.pmcr_ro | PMU_PMCR_LC | PMU_PMCR_C | PMU_PMCR_P); + /* Disable all counters */ + write_sysreg_s(0xFFFFFFFF, PMCNTENCLR_EL0); + /* clear overflow reg */ + write_sysreg(0xFFFFFFFF, pmovsclr_el0); + /* disable overflow interrupts on all counters */ + write_sysreg(0xFFFFFFFF, pmintenclr_el1); + isb(); +} + +static void test_event_counter_config(void) +{ + int i; + + if (!pmu.nb_implemented_counters) { + report_skip("No event counter, skip ..."); + return; + } + + pmu_reset(); + + /* + * Test setting through PMESELR/PMXEVTYPER and PMEVTYPERn read, + * select counter 0 + */ + write_sysreg(1, PMSELR_EL0); + /* program this counter to count unsupported event */ + write_sysreg(0xEA, PMXEVTYPER_EL0); + write_sysreg(0xdeadbeef, PMXEVCNTR_EL0); + report((read_regn(pmevtyper, 1) & 0xFFF) =3D=3D 0xEA, + "PMESELR/PMXEVTYPER/PMEVTYPERn"); + report((read_regn(pmevcntr, 1) =3D=3D 0xdeadbeef), + "PMESELR/PMXEVCNTR/PMEVCNTRn"); + + /* try configure an unsupported event within the range [0x0, 0x3F] */ + for (i =3D 0; i <=3D 0x3F; i++) { + if (!is_event_supported(i, false)) + goto test_unsupported; + } + report_skip("pmevtyper: all events within [0x0, 0x3F] are supported"); + +test_unsupported: + /* select counter 0 */ + write_sysreg(0, PMSELR_EL0); + /* program this counter to count unsupported event */ + write_sysreg(i, PMXEVCNTR_EL0); + /* read the counter value */ + read_sysreg(PMXEVCNTR_EL0); + report(read_sysreg(PMXEVCNTR_EL0) =3D=3D i, + "read of a counter programmed with unsupported event"); + +} + +static bool satisfy_prerequisites(uint32_t *events, unsigned int nb_even= ts) +{ + int i; + + if (pmu.nb_implemented_counters < nb_events) { + report_skip("Skip test as number of counters is too small (%d)", + pmu.nb_implemented_counters); + return false; + } + + for (i =3D 0; i < nb_events; i++) { + if (!is_event_supported(events[i], false)) { + report_skip("Skip test as event %d is not supported", + events[i]); + return false; + } + } + return true; +} + +static void test_basic_event_count(void) +{ + uint32_t implemented_counter_mask, non_implemented_counter_mask; + uint32_t counter_mask; + uint32_t events[] =3D { + 0x11, /* CPU_CYCLES */ + 0x8, /* INST_RETIRED */ + }; + + if (!satisfy_prerequisites(events, ARRAY_SIZE(events))) + return; + + implemented_counter_mask =3D (1 << pmu.nb_implemented_counters) - 1; + non_implemented_counter_mask =3D ~((1 << 31) | implemented_counter_mask= ); + counter_mask =3D implemented_counter_mask | non_implemented_counter_mas= k; + + write_regn(pmevtyper, 0, events[0] | PMEVTYPER_EXCLUDE_EL0); + write_regn(pmevtyper, 1, events[1] | PMEVTYPER_EXCLUDE_EL0); + + /* disable all counters */ + write_sysreg_s(0xFFFFFFFF, PMCNTENCLR_EL0); + report(!read_sysreg_s(PMCNTENCLR_EL0) && !read_sysreg_s(PMCNTENSET_EL0)= , + "pmcntenclr: disable all counters"); + + /* + * clear cycle and all event counters and allow counter enablement + * through PMCNTENSET. LC is RES1. + */ + set_pmcr(pmu.pmcr_ro | PMU_PMCR_LC | PMU_PMCR_C | PMU_PMCR_P); + isb(); + report(get_pmcr() =3D=3D (pmu.pmcr_ro | PMU_PMCR_LC), "pmcr: reset coun= ters"); + + /* Preset counter #0 to 0xFFFFFFF0 to trigger an overflow interrupt */ + write_regn(pmevcntr, 0, 0xFFFFFFF0); + report(read_regn(pmevcntr, 0) =3D=3D 0xFFFFFFF0, + "counter #0 preset to 0xFFFFFFF0"); + report(!read_regn(pmevcntr, 1), "counter #1 is 0"); + + /* + * Enable all implemented counters and also attempt to enable + * not supported counters. Counting still is disabled by !PMCR.E + */ + write_sysreg_s(counter_mask, PMCNTENSET_EL0); + + /* check only those implemented are enabled */ + report((read_sysreg_s(PMCNTENSET_EL0) =3D=3D read_sysreg_s(PMCNTENCLR_E= L0)) && + (read_sysreg_s(PMCNTENSET_EL0) =3D=3D implemented_counter_mask), + "pmcntenset: enabled implemented_counters"); + + /* Disable all counters but counters #0 and #1 */ + write_sysreg_s(~0x3, PMCNTENCLR_EL0); + report((read_sysreg_s(PMCNTENSET_EL0) =3D=3D read_sysreg_s(PMCNTENCLR_E= L0)) && + (read_sysreg_s(PMCNTENSET_EL0) =3D=3D 0x3), + "pmcntenset: just enabled #0 and #1"); + + /* clear overflow register */ + write_sysreg(0xFFFFFFFF, pmovsclr_el0); + report(!read_sysreg(pmovsclr_el0), "check overflow reg is 0"); + + /* disable overflow interrupts on all counters*/ + write_sysreg(0xFFFFFFFF, pmintenclr_el1); + report(!read_sysreg(pmintenclr_el1), + "pmintenclr_el1=3D0, all interrupts disabled"); + + /* enable overflow interrupts on all event counters */ + write_sysreg(implemented_counter_mask | non_implemented_counter_mask, + pmintenset_el1); + report(read_sysreg(pmintenset_el1) =3D=3D implemented_counter_mask, + "overflow interrupts enabled on all implemented counters"); + + /* Set PMCR.E, execute asm code and unset PMCR.E */ + precise_instrs_loop(20, pmu.pmcr_ro | PMU_PMCR_E); + + report_info("counter #0 is 0x%lx (CPU_CYCLES)", + read_regn(pmevcntr, 0)); + report_info("counter #1 is 0x%lx (INST_RETIRED)", + read_regn(pmevcntr, 1)); + + report_info("overflow reg =3D 0x%lx", read_sysreg(pmovsclr_el0)); + report(read_sysreg(pmovsclr_el0) & 0x1, + "check overflow happened on #0 only"); +} + +static void test_mem_access(void) +{ + void *addr =3D malloc(PAGE_SIZE); + uint32_t events[] =3D { + 0x13, /* MEM_ACCESS */ + 0x13, /* MEM_ACCESS */ + }; + + if (!satisfy_prerequisites(events, ARRAY_SIZE(events))) + return; + + pmu_reset(); + + write_regn(pmevtyper, 0, events[0] | PMEVTYPER_EXCLUDE_EL0); + write_regn(pmevtyper, 1, events[1] | PMEVTYPER_EXCLUDE_EL0); + write_sysreg_s(0x3, PMCNTENSET_EL0); + isb(); + mem_access_loop(addr, 20, pmu.pmcr_ro | PMU_PMCR_E); + report_info("counter #0 is %ld (MEM_ACCESS)", read_regn(pmevcntr, 0)); + report_info("counter #1 is %ld (MEM_ACCESS)", read_regn(pmevcntr, 1)); + /* We may not measure exactly 20 mem access. Depends on the platform */ + report((read_regn(pmevcntr, 0) =3D=3D read_regn(pmevcntr, 1)) && + (read_regn(pmevcntr, 0) >=3D 20) && !read_sysreg(pmovsclr_el0), + "Ran 20 mem accesses"); + + pmu_reset(); + + write_regn(pmevcntr, 0, 0xFFFFFFFA); + write_regn(pmevcntr, 1, 0xFFFFFFF0); + write_sysreg_s(0x3, PMCNTENSET_EL0); + isb(); + mem_access_loop(addr, 20, pmu.pmcr_ro | PMU_PMCR_E); + report(read_sysreg(pmovsclr_el0) =3D=3D 0x3, + "Ran 20 mem accesses with expected overflows on both counters"); + report_info("cnt#0 =3D %ld cnt#1=3D%ld overflow=3D0x%lx", + read_regn(pmevcntr, 0), read_regn(pmevcntr, 1), + read_sysreg(pmovsclr_el0)); +} + #endif =20 /* @@ -397,6 +649,15 @@ int main(int argc, char *argv[]) } else if (strcmp(argv[1], "event-introspection") =3D=3D 0) { report_prefix_push(argv[1]); test_event_introspection(); + } else if (strcmp(argv[1], "event-counter-config") =3D=3D 0) { + report_prefix_push(argv[1]); + test_event_counter_config(); + } else if (strcmp(argv[1], "basic-event-count") =3D=3D 0) { + report_prefix_push(argv[1]); + test_basic_event_count(); + } else if (strcmp(argv[1], "mem-access") =3D=3D 0) { + report_prefix_push(argv[1]); + test_mem_access(); } else { report_abort("Unknown sub-test '%s'", argv[1]); } diff --git a/arm/unittests.cfg b/arm/unittests.cfg index 4433ef3..7a59403 100644 --- a/arm/unittests.cfg +++ b/arm/unittests.cfg @@ -72,6 +72,24 @@ groups =3D pmu arch =3D arm64 extra_params =3D -append 'event-introspection' =20 +[pmu-event-counter-config] +file =3D pmu.flat +groups =3D pmu +arch =3D arm64 +extra_params =3D -append 'event-counter-config' + +[pmu-basic-event-count] +file =3D pmu.flat +groups =3D pmu +arch =3D arm64 +extra_params =3D -append 'basic-event-count' + +[pmu-mem-access] +file =3D pmu.flat +groups =3D pmu +arch =3D arm64 +extra_params =3D -append 'mem-access' + # Test PMU support (TCG) with -icount IPC=3D1 #[pmu-tcg-icount-1] #file =3D pmu.flat --=20 2.20.1 From MAILER-DAEMON Mon Dec 16 15:48:42 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1igxII-0007YG-Fg for mharc-qemu-arm@gnu.org; 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Mon, 16 Dec 2019 15:48:35 -0500 X-MC-Unique: 1h7B-h2wNcq0MmOi1a7LSA-1 Received: from smtp.corp.redhat.com (int-mx04.intmail.prod.int.phx2.redhat.com [10.5.11.14]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx01.redhat.com (Postfix) with ESMTPS id E9187A0374; Mon, 16 Dec 2019 20:48:33 +0000 (UTC) Received: from laptop.redhat.com (ovpn-116-117.ams2.redhat.com [10.36.116.117]) by smtp.corp.redhat.com (Postfix) with ESMTP id 33C7C5D9C9; Mon, 16 Dec 2019 20:48:30 +0000 (UTC) From: Eric Auger To: eric.auger.pro@gmail.com, eric.auger@redhat.com, maz@kernel.org, kvmarm@lists.cs.columbia.edu, kvm@vger.kernel.org, qemu-devel@nongnu.org, qemu-arm@nongnu.org Cc: drjones@redhat.com, andrew.murray@arm.com, andre.przywara@arm.com, peter.maydell@linaro.org, alexandru.elisei@arm.com Subject: [kvm-unit-tests PATCH 07/10] arm: pmu: test 32-bit <-> 64-bit transitions Date: Mon, 16 Dec 2019 21:47:54 +0100 Message-Id: <20191216204757.4020-8-eric.auger@redhat.com> In-Reply-To: <20191216204757.4020-1-eric.auger@redhat.com> References: <20191216204757.4020-1-eric.auger@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.79 on 10.5.11.14 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 207.211.31.81 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 16 Dec 2019 20:48:41 -0000 Test configurations where we transit from 32b to 64b counters and conversely. Also tests configuration where chain counters are configured but only one counter is enabled. Signed-off-by: Eric Auger --- arm/pmu.c | 135 ++++++++++++++++++++++++++++++++++++++++++++++ arm/unittests.cfg | 6 +++ 2 files changed, 141 insertions(+) diff --git a/arm/pmu.c b/arm/pmu.c index ad98771..8506544 100644 --- a/arm/pmu.c +++ b/arm/pmu.c @@ -115,6 +115,7 @@ static void test_basic_event_count(void) {} static void test_mem_access(void) {} static void test_chained_counters(void) {} static void test_chained_sw_incr(void) {} +static void test_chain_promotion(void) {} =20 #elif defined(__aarch64__) #define ID_AA64DFR0_PERFMON_SHIFT 8 @@ -581,6 +582,137 @@ static void test_chained_sw_incr(void) read_regn(pmevcntr, 0), read_regn(pmevcntr, 1)); } =20 +static void test_chain_promotion(void) +{ + uint32_t events[] =3D { 0x13 /* MEM_ACCESS */, 0x1E /* CHAIN */}; + void *addr =3D malloc(PAGE_SIZE); + + if (!satisfy_prerequisites(events, ARRAY_SIZE(events))) + return; + + /* Only enable CHAIN counter */ + pmu_reset(); + write_regn(pmevtyper, 0, events[0] | PMEVTYPER_EXCLUDE_EL0); + write_regn(pmevtyper, 1, events[1] | PMEVTYPER_EXCLUDE_EL0); + write_sysreg_s(0x2, PMCNTENSET_EL0); + isb(); + + mem_access_loop(addr, 20, pmu.pmcr_ro | PMU_PMCR_E); + report(!read_regn(pmevcntr, 0), + "chain counter not counting if even counter is disabled"); + + /* Only enable even counter */ + pmu_reset(); + write_regn(pmevcntr, 0, 0xFFFFFFF0); + write_sysreg_s(0x1, PMCNTENSET_EL0); + isb(); + + mem_access_loop(addr, 20, pmu.pmcr_ro | PMU_PMCR_E); + report(!read_regn(pmevcntr, 1) && (read_sysreg(pmovsclr_el0) =3D=3D 0x1= ), + "odd counter did not increment on overflow if disabled"); + report_info("MEM_ACCESS counter #0 has value %ld", + read_regn(pmevcntr, 0)); + report_info("CHAIN counter #1 has value %ld", + read_regn(pmevcntr, 1)); + report_info("overflow counter %ld", read_sysreg(pmovsclr_el0)); + + /* start at 0xFFFFFFDC, +20 with CHAIN enabled, +20 with CHAIN disabled= */ + pmu_reset(); + write_sysreg_s(0x3, PMCNTENSET_EL0); + write_regn(pmevcntr, 0, 0xFFFFFFDC); + isb(); + + mem_access_loop(addr, 20, pmu.pmcr_ro | PMU_PMCR_E); + report_info("MEM_ACCESS counter #0 has value 0x%lx", + read_regn(pmevcntr, 0)); + + /* disable the CHAIN event */ + write_sysreg_s(0x2, PMCNTENCLR_EL0); + mem_access_loop(addr, 20, pmu.pmcr_ro | PMU_PMCR_E); + report_info("MEM_ACCESS counter #0 has value 0x%lx", + read_regn(pmevcntr, 0)); + report(read_sysreg(pmovsclr_el0) =3D=3D 0x1, + "should have triggered an overflow on #0"); + report(!read_regn(pmevcntr, 1), + "CHAIN counter #1 shouldn't have incremented"); + + /* start at 0xFFFFFFDC, +20 with CHAIN disabled, +20 with CHAIN enabled= */ + + pmu_reset(); + write_sysreg_s(0x1, PMCNTENSET_EL0); + write_regn(pmevcntr, 0, 0xFFFFFFDC); + isb(); + report_info("counter #0 =3D 0x%lx, counter #1 =3D 0x%lx overflow=3D0x%l= x", + read_regn(pmevcntr, 0), read_regn(pmevcntr, 1), + read_sysreg(pmovsclr_el0)); + + mem_access_loop(addr, 20, pmu.pmcr_ro | PMU_PMCR_E); + report_info("MEM_ACCESS counter #0 has value 0x%lx", + read_regn(pmevcntr, 0)); + + /* enable the CHAIN event */ + write_sysreg_s(0x3, PMCNTENSET_EL0); + isb(); + mem_access_loop(addr, 20, pmu.pmcr_ro | PMU_PMCR_E); + report_info("MEM_ACCESS counter #0 has value 0x%lx", + read_regn(pmevcntr, 0)); + + report((read_regn(pmevcntr, 1) =3D=3D 1) && !read_sysreg(pmovsclr_el0), + "CHAIN counter #1 should have incremented and no overflow expected"); + + report_info("CHAIN counter #1 =3D 0x%lx, overflow=3D0x%lx", + read_regn(pmevcntr, 1), read_sysreg(pmovsclr_el0)); + + /* start as MEM_ACCESS/CPU_CYCLES and move to CHAIN/MEM_ACCESS */ + pmu_reset(); + write_regn(pmevtyper, 0, 0x13 /* MEM_ACCESS */ | PMEVTYPER_EXCLUDE_EL0)= ; + write_regn(pmevtyper, 1, 0x11 /* CPU_CYCLES */ | PMEVTYPER_EXCLUDE_EL0)= ; + write_sysreg_s(0x3, PMCNTENSET_EL0); + write_regn(pmevcntr, 0, 0xFFFFFFDC); + isb(); + + mem_access_loop(addr, 20, pmu.pmcr_ro | PMU_PMCR_E); + report_info("MEM_ACCESS counter #0 has value 0x%lx", + read_regn(pmevcntr, 0)); + + /* 0 becomes CHAINED */ + write_sysreg_s(0x0, PMCNTENSET_EL0); + write_regn(pmevtyper, 1, 0x1E /* CHAIN */ | PMEVTYPER_EXCLUDE_EL0); + write_sysreg_s(0x3, PMCNTENSET_EL0); + + mem_access_loop(addr, 20, pmu.pmcr_ro | PMU_PMCR_E); + report_info("MEM_ACCESS counter #0 has value 0x%lx", + read_regn(pmevcntr, 0)); + + report((read_regn(pmevcntr, 1) =3D=3D 1) && !read_sysreg(pmovsclr_el0), + "CHAIN counter #1 should have incremented and no overflow expected"); + + report_info("CHAIN counter #1 =3D 0x%lx, overflow=3D0x%lx", + read_regn(pmevcntr, 1), read_sysreg(pmovsclr_el0)); + + /* start as CHAIN/MEM_ACCESS and move to MEM_ACCESS/CPU_CYCLES */ + pmu_reset(); + write_regn(pmevtyper, 0, 0x13 /* MEM_ACCESS */ | PMEVTYPER_EXCLUDE_EL0)= ; + write_regn(pmevtyper, 1, 0x1E /* CHAIN */ | PMEVTYPER_EXCLUDE_EL0); + write_regn(pmevcntr, 0, 0xFFFFFFDC); + write_sysreg_s(0x3, PMCNTENSET_EL0); + + mem_access_loop(addr, 20, pmu.pmcr_ro | PMU_PMCR_E); + report_info("counter #0=3D0x%lx, counter #1=3D0x%lx", + read_regn(pmevcntr, 0), read_regn(pmevcntr, 1)); + + write_sysreg_s(0x0, PMCNTENSET_EL0); + write_regn(pmevtyper, 1, 0x11 /* CPU_CYCLES */ | PMEVTYPER_EXCLUDE_EL0)= ; + write_sysreg_s(0x3, PMCNTENSET_EL0); + + mem_access_loop(addr, 20, pmu.pmcr_ro | PMU_PMCR_E); + report(read_sysreg(pmovsclr_el0) =3D=3D 1, + "overflow is expected on counter 0"); + report_info("counter #0=3D0x%lx, counter #1=3D0x%lx overflow=3D0x%lx", + read_regn(pmevcntr, 0), read_regn(pmevcntr, 1), + read_sysreg(pmovsclr_el0)); +} + #endif =20 /* @@ -786,6 +918,9 @@ int main(int argc, char *argv[]) } else if (strcmp(argv[1], "chained-sw-incr") =3D=3D 0) { report_prefix_push(argv[1]); test_chained_sw_incr(); + } else if (strcmp(argv[1], "chain-promotion") =3D=3D 0) { + report_prefix_push(argv[1]); + test_chain_promotion(); } else { report_abort("Unknown sub-test '%s'", argv[1]); } diff --git a/arm/unittests.cfg b/arm/unittests.cfg index 1bd4319..eb6e87e 100644 --- a/arm/unittests.cfg +++ b/arm/unittests.cfg @@ -102,6 +102,12 @@ groups =3D pmu arch =3D arm64 extra_params =3D -append 'chained-sw-incr' =20 +[pmu-chain-promotion] +file =3D pmu.flat +groups =3D pmu +arch =3D arm64 +extra_params =3D -append 'chain-promotion' + # Test PMU support (TCG) with -icount IPC=3D1 #[pmu-tcg-icount-1] #file =3D pmu.flat --=20 2.20.1 From MAILER-DAEMON Mon Dec 16 15:48:48 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1igxIO-0007it-Km for mharc-qemu-arm@gnu.org; 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b=KWureBRnuqBP2CVxwO0mjGV0YingWtGbOdRyqivR4k3xpe+Hz/tNDaIK3kHV+of8M5mQJT HEXDd2fsnVHn4XwZgX2S2uRyXmUi3VBM24T7cY1/fhb8av5EGtgx50lAdkJJwRcC7v111R x+eszrq80Oco4ZStfZoTOVBMy45UfIM= Received: from mimecast-mx01.redhat.com (mimecast-mx01.redhat.com [209.132.183.4]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-305-gv3zSrO2M92zwqDgWdhoog-1; Mon, 16 Dec 2019 15:48:42 -0500 X-MC-Unique: gv3zSrO2M92zwqDgWdhoog-1 Received: from smtp.corp.redhat.com (int-mx04.intmail.prod.int.phx2.redhat.com [10.5.11.14]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx01.redhat.com (Postfix) with ESMTPS id 12AAB8E10DB; Mon, 16 Dec 2019 20:48:40 +0000 (UTC) Received: from laptop.redhat.com (ovpn-116-117.ams2.redhat.com [10.36.116.117]) by smtp.corp.redhat.com (Postfix) with ESMTP id 5A0485D9C9; Mon, 16 Dec 2019 20:48:37 +0000 (UTC) From: Eric Auger To: eric.auger.pro@gmail.com, eric.auger@redhat.com, maz@kernel.org, kvmarm@lists.cs.columbia.edu, kvm@vger.kernel.org, qemu-devel@nongnu.org, qemu-arm@nongnu.org Cc: drjones@redhat.com, andrew.murray@arm.com, andre.przywara@arm.com, peter.maydell@linaro.org, alexandru.elisei@arm.com Subject: [kvm-unit-tests PATCH 09/10] arm/arm64: gic: Introduce setup_irq() helper Date: Mon, 16 Dec 2019 21:47:56 +0100 Message-Id: <20191216204757.4020-10-eric.auger@redhat.com> In-Reply-To: <20191216204757.4020-1-eric.auger@redhat.com> References: <20191216204757.4020-1-eric.auger@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.79 on 10.5.11.14 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 207.211.31.120 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 16 Dec 2019 20:48:47 -0000 ipi_enable() code would be reusable for other interrupts than IPI. Let's rename it setup_irq() and pass an interrupt handler pointer. We also export it to use it in other tests such as the PMU's one. Signed-off-by: Eric Auger --- arm/gic.c | 24 +++--------------------- lib/arm/asm/gic.h | 3 +++ lib/arm/gic.c | 11 +++++++++++ 3 files changed, 17 insertions(+), 21 deletions(-) diff --git a/arm/gic.c b/arm/gic.c index fcf4c1f..ba43ae5 100644 --- a/arm/gic.c +++ b/arm/gic.c @@ -215,20 +215,9 @@ static void ipi_test_smp(void) report_prefix_pop(); } =20 -static void ipi_enable(void) -{ - gic_enable_defaults(); -#ifdef __arm__ - install_exception_handler(EXCPTN_IRQ, ipi_handler); -#else - install_irq_handler(EL1H_IRQ, ipi_handler); -#endif - local_irq_enable(); -} - static void ipi_send(void) { - ipi_enable(); + setup_irq(ipi_handler); wait_on_ready(); ipi_test_self(); ipi_test_smp(); @@ -238,7 +227,7 @@ static void ipi_send(void) =20 static void ipi_recv(void) { - ipi_enable(); + setup_irq(ipi_handler); cpumask_set_cpu(smp_processor_id(), &ready); while (1) wfi(); @@ -295,14 +284,7 @@ static void ipi_clear_active_handler(struct pt_regs = *regs __unused) static void run_active_clear_test(void) { report_prefix_push("active"); - gic_enable_defaults(); -#ifdef __arm__ - install_exception_handler(EXCPTN_IRQ, ipi_clear_active_handler); -#else - install_irq_handler(EL1H_IRQ, ipi_clear_active_handler); -#endif - local_irq_enable(); - + setup_irq(ipi_clear_active_handler); ipi_test_self(); report_prefix_pop(); } diff --git a/lib/arm/asm/gic.h b/lib/arm/asm/gic.h index 21cdb58..55dd84b 100644 --- a/lib/arm/asm/gic.h +++ b/lib/arm/asm/gic.h @@ -82,5 +82,8 @@ void gic_set_irq_target(int irq, int cpu); void gic_set_irq_group(int irq, int group); int gic_get_irq_group(int irq); =20 +typedef void (*handler_t)(struct pt_regs *regs __unused); +extern void setup_irq(handler_t handler); + #endif /* !__ASSEMBLY__ */ #endif /* _ASMARM_GIC_H_ */ diff --git a/lib/arm/gic.c b/lib/arm/gic.c index aa9cb86..8416dde 100644 --- a/lib/arm/gic.c +++ b/lib/arm/gic.c @@ -236,3 +236,14 @@ int gic_get_irq_group(int irq) { return gic_masked_irq_bits(irq, GICD_IGROUPR, 1, 0, ACCESS_READ); } + +void setup_irq(handler_t handler) +{ + gic_enable_defaults(); +#ifdef __arm__ + install_exception_handler(EXCPTN_IRQ, handler); +#else + install_irq_handler(EL1H_IRQ, handler); +#endif + local_irq_enable(); +} --=20 2.20.1 From MAILER-DAEMON Mon Dec 16 15:48:55 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1igxIV-0007u5-9M for mharc-qemu-arm@gnu.org; Mon, 16 Dec 2019 15:48:55 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:36484) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1igxIQ-0007mE-Fd for qemu-arm@nongnu.org; Mon, 16 Dec 2019 15:48:51 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1igxIO-0006bH-VW for qemu-arm@nongnu.org; Mon, 16 Dec 2019 15:48:50 -0500 Received: from us-smtp-2.mimecast.com ([205.139.110.61]:28948 helo=us-smtp-delivery-1.mimecast.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1igxIO-0006b5-RA for qemu-arm@nongnu.org; Mon, 16 Dec 2019 15:48:48 -0500 DKIM-Signature: v=1; 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Mon, 16 Dec 2019 20:48:45 +0000 (UTC) Received: from laptop.redhat.com (ovpn-116-117.ams2.redhat.com [10.36.116.117]) by smtp.corp.redhat.com (Postfix) with ESMTP id 6A8075D9C9; Mon, 16 Dec 2019 20:48:40 +0000 (UTC) From: Eric Auger To: eric.auger.pro@gmail.com, eric.auger@redhat.com, maz@kernel.org, kvmarm@lists.cs.columbia.edu, kvm@vger.kernel.org, qemu-devel@nongnu.org, qemu-arm@nongnu.org Cc: drjones@redhat.com, andrew.murray@arm.com, andre.przywara@arm.com, peter.maydell@linaro.org, alexandru.elisei@arm.com Subject: [kvm-unit-tests PATCH 10/10] arm: pmu: Test overflow interrupts Date: Mon, 16 Dec 2019 21:47:57 +0100 Message-Id: <20191216204757.4020-11-eric.auger@redhat.com> In-Reply-To: <20191216204757.4020-1-eric.auger@redhat.com> References: <20191216204757.4020-1-eric.auger@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.79 on 10.5.11.14 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 205.139.110.61 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 16 Dec 2019 20:48:52 -0000 Test overflows for MEM_ACCESS and SW_INCR events. Also tests overflows with 64-bit events. Signed-off-by: Eric Auger --- arm/pmu.c | 134 ++++++++++++++++++++++++++++++++++++++++++++++ arm/unittests.cfg | 6 +++ 2 files changed, 140 insertions(+) diff --git a/arm/pmu.c b/arm/pmu.c index 8506544..9af9e42 100644 --- a/arm/pmu.c +++ b/arm/pmu.c @@ -45,6 +45,11 @@ struct pmu { uint32_t pmcr_ro; }; =20 +struct pmu_stats { + unsigned long bitmap; + uint32_t interrupts[32]; +}; + static struct pmu pmu; =20 #if defined(__arm__) @@ -116,6 +121,7 @@ static void test_mem_access(void) {} static void test_chained_counters(void) {} static void test_chained_sw_incr(void) {} static void test_chain_promotion(void) {} +static void test_overflow_interrupt(void) {} =20 #elif defined(__aarch64__) #define ID_AA64DFR0_PERFMON_SHIFT 8 @@ -263,6 +269,43 @@ asm volatile( : ); } =20 +static struct pmu_stats pmu_stats; + +static void irq_handler(struct pt_regs *regs) +{ + uint32_t irqstat, irqnr; + + irqstat =3D gic_read_iar(); + irqnr =3D gic_iar_irqnr(irqstat); + gic_write_eoir(irqstat); + + if (irqnr =3D=3D 23) { + unsigned long overflows =3D read_sysreg(pmovsclr_el0); + int i; + + report_info("--> PMU overflow interrupt %d (counter bitmask 0x%lx)", + irqnr, overflows); + for (i =3D 0; i < 32; i++) { + if (test_and_clear_bit(i, &overflows)) { + pmu_stats.interrupts[i]++; + pmu_stats.bitmap |=3D 1 << i; + } + } + write_sysreg(0xFFFFFFFF, pmovsclr_el0); + } else { + report_info("Unexpected interrupt: %d\n", irqnr); + } +} + +static void pmu_reset_stats(void) +{ + int i; + + for (i =3D 0; i < 32; i++) + pmu_stats.interrupts[i] =3D 0; + + pmu_stats.bitmap =3D 0; +} =20 static void pmu_reset(void) { @@ -274,6 +317,7 @@ static void pmu_reset(void) write_sysreg(0xFFFFFFFF, pmovsclr_el0); /* disable overflow interrupts on all counters */ write_sysreg(0xFFFFFFFF, pmintenclr_el1); + pmu_reset_stats(); isb(); } =20 @@ -713,6 +757,93 @@ static void test_chain_promotion(void) read_sysreg(pmovsclr_el0)); } =20 +static bool expect_interrupts(uint32_t bitmap) +{ + int i; + + if (pmu_stats.bitmap ^ bitmap) + return false; + + for (i =3D 0; i < 32; i++) { + if (test_and_clear_bit(i, &pmu_stats.bitmap)) + if (pmu_stats.interrupts[i] !=3D 1) + return false; + } + return true; +} + +static void test_overflow_interrupt(void) +{ + uint32_t events[] =3D { 0x13 /* MEM_ACCESS */, 0x00 /* SW_INCR */}; + void *addr =3D malloc(PAGE_SIZE); + int i; + + if (!satisfy_prerequisites(events, ARRAY_SIZE(events))) + return; + + setup_irq(irq_handler); + gic_enable_irq(23); + + pmu_reset(); + + write_regn(pmevtyper, 0, events[0] | PMEVTYPER_EXCLUDE_EL0); + write_regn(pmevtyper, 1, events[1] | PMEVTYPER_EXCLUDE_EL0); + write_sysreg_s(0x3, PMCNTENSET_EL0); + write_regn(pmevcntr, 0, 0xFFFFFFF0); + write_regn(pmevcntr, 1, 0xFFFFFFF0); + isb(); + + /* interrupts are disabled */ + + mem_access_loop(addr, 200, pmu.pmcr_ro | PMU_PMCR_E); + report(expect_interrupts(0), "no overflow interrupt received"); + + set_pmcr(pmu.pmcr_ro | PMU_PMCR_E); + for (i =3D 0; i < 100; i++) + write_sysreg(0x2, pmswinc_el0); + + set_pmcr(pmu.pmcr_ro); + report(expect_interrupts(0), "no overflow interrupt received"); + + /* enable interrupts */ + + pmu_reset_stats(); + + write_regn(pmevcntr, 0, 0xFFFFFFF0); + write_regn(pmevcntr, 1, 0xFFFFFFF0); + write_sysreg(0xFFFFFFFF, pmintenset_el1); + isb(); + + mem_access_loop(addr, 200, pmu.pmcr_ro | PMU_PMCR_E); + for (i =3D 0; i < 100; i++) + write_sysreg(0x3, pmswinc_el0); + + mem_access_loop(addr, 200, pmu.pmcr_ro); + report_info("overflow=3D0x%lx", read_sysreg(pmovsclr_el0)); + report(expect_interrupts(0x3), + "overflow interrupts expected on #0 and #1"); + + /* promote to 64-b */ + + pmu_reset_stats(); + + events[1] =3D 0x1E /* CHAIN */; + write_regn(pmevtyper, 1, events[1] | PMEVTYPER_EXCLUDE_EL0); + write_regn(pmevcntr, 0, 0xFFFFFFF0); + isb(); + mem_access_loop(addr, 200, pmu.pmcr_ro | PMU_PMCR_E); + report(expect_interrupts(0), + "no overflow interrupt expected on 32b boundary"); + + /* overflow on odd counter */ + pmu_reset_stats(); + write_regn(pmevcntr, 0, 0xFFFFFFF0); + write_regn(pmevcntr, 1, 0xFFFFFFFF); + isb(); + mem_access_loop(addr, 200, pmu.pmcr_ro | PMU_PMCR_E); + report(expect_interrupts(0x2), + "expect overflow interrupt on odd counter"); +} #endif =20 /* @@ -921,6 +1052,9 @@ int main(int argc, char *argv[]) } else if (strcmp(argv[1], "chain-promotion") =3D=3D 0) { report_prefix_push(argv[1]); test_chain_promotion(); + } else if (strcmp(argv[1], "overflow-interrupt") =3D=3D 0) { + report_prefix_push(argv[1]); + test_overflow_interrupt(); } else { report_abort("Unknown sub-test '%s'", argv[1]); } diff --git a/arm/unittests.cfg b/arm/unittests.cfg index eb6e87e..1d1bc27 100644 --- a/arm/unittests.cfg +++ b/arm/unittests.cfg @@ -108,6 +108,12 @@ groups =3D pmu arch =3D arm64 extra_params =3D -append 'chain-promotion' =20 +[overflow-interrupt] +file =3D pmu.flat +groups =3D pmu +arch =3D arm64 +extra_params =3D -append 'overflow-interrupt' + # Test PMU support (TCG) with -icount IPC=3D1 #[pmu-tcg-icount-1] #file =3D pmu.flat --=20 2.20.1 From MAILER-DAEMON Mon Dec 16 15:49:05 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1igxIf-0008BZ-FO for mharc-qemu-arm@gnu.org; Mon, 16 Dec 2019 15:49:05 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:36520) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1igxIZ-00081N-Gf for qemu-arm@nongnu.org; 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Mon, 16 Dec 2019 15:48:53 -0500 X-MC-Unique: OlX8qa1eNJigoM1oY1pwZA-1 Received: from smtp.corp.redhat.com (int-mx04.intmail.prod.int.phx2.redhat.com [10.5.11.14]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx01.redhat.com (Postfix) with ESMTPS id 027DF10B9593; Mon, 16 Dec 2019 20:48:37 +0000 (UTC) Received: from laptop.redhat.com (ovpn-116-117.ams2.redhat.com [10.36.116.117]) by smtp.corp.redhat.com (Postfix) with ESMTP id 4E2015D9C9; Mon, 16 Dec 2019 20:48:34 +0000 (UTC) From: Eric Auger To: eric.auger.pro@gmail.com, eric.auger@redhat.com, maz@kernel.org, kvmarm@lists.cs.columbia.edu, kvm@vger.kernel.org, qemu-devel@nongnu.org, qemu-arm@nongnu.org Cc: drjones@redhat.com, andrew.murray@arm.com, andre.przywara@arm.com, peter.maydell@linaro.org, alexandru.elisei@arm.com Subject: [kvm-unit-tests PATCH 08/10] arm: gic: Provide per-IRQ helper functions Date: Mon, 16 Dec 2019 21:47:55 +0100 Message-Id: <20191216204757.4020-9-eric.auger@redhat.com> In-Reply-To: <20191216204757.4020-1-eric.auger@redhat.com> References: <20191216204757.4020-1-eric.auger@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.79 on 10.5.11.14 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 205.139.110.120 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 16 Dec 2019 20:49:03 -0000 From: Andre Przywara A common theme when accessing per-IRQ parameters in the GIC distributor is to set fields of a certain bit width in a range of MMIO registers. Examples are the enabled status (one bit per IRQ), the level/edge configuration (2 bits per IRQ) or the priority (8 bits per IRQ). Add a generic helper function which is able to mask and set the respective number of bits, given the IRQ number and the MMIO offset. Provide wrappers using this function to easily allow configuring an IRQ. For now assume that private IRQ numbers always refer to the current CPU. In a GICv2 accessing the "other" private IRQs is not easily doable (the registers are banked per CPU on the same MMIO address), so we impose the same limitation on GICv3, even though those registers are not banked there anymore. Signed-off-by: Andre Przywara --- initialize reg --- lib/arm/asm/gic-v3.h | 2 + lib/arm/asm/gic.h | 9 +++++ lib/arm/gic.c | 90 ++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 101 insertions(+) diff --git a/lib/arm/asm/gic-v3.h b/lib/arm/asm/gic-v3.h index 347be2f..4a445a5 100644 --- a/lib/arm/asm/gic-v3.h +++ b/lib/arm/asm/gic-v3.h @@ -23,6 +23,8 @@ #define GICD_CTLR_ENABLE_G1A (1U << 1) #define GICD_CTLR_ENABLE_G1 (1U << 0) =20 +#define GICD_IROUTER 0x6000 + /* Re-Distributor registers, offsets from RD_base */ #define GICR_TYPER 0x0008 =20 diff --git a/lib/arm/asm/gic.h b/lib/arm/asm/gic.h index 1fc10a0..21cdb58 100644 --- a/lib/arm/asm/gic.h +++ b/lib/arm/asm/gic.h @@ -15,6 +15,7 @@ #define GICD_IIDR 0x0008 #define GICD_IGROUPR 0x0080 #define GICD_ISENABLER 0x0100 +#define GICD_ICENABLER 0x0180 #define GICD_ISPENDR 0x0200 #define GICD_ICPENDR 0x0280 #define GICD_ISACTIVER 0x0300 @@ -73,5 +74,13 @@ extern void gic_write_eoir(u32 irqstat); extern void gic_ipi_send_single(int irq, int cpu); extern void gic_ipi_send_mask(int irq, const cpumask_t *dest); =20 +void gic_set_irq_bit(int irq, int offset); +void gic_enable_irq(int irq); +void gic_disable_irq(int irq); +void gic_set_irq_priority(int irq, u8 prio); +void gic_set_irq_target(int irq, int cpu); +void gic_set_irq_group(int irq, int group); +int gic_get_irq_group(int irq); + #endif /* !__ASSEMBLY__ */ #endif /* _ASMARM_GIC_H_ */ diff --git a/lib/arm/gic.c b/lib/arm/gic.c index 9430116..aa9cb86 100644 --- a/lib/arm/gic.c +++ b/lib/arm/gic.c @@ -146,3 +146,93 @@ void gic_ipi_send_mask(int irq, const cpumask_t *des= t) assert(gic_common_ops && gic_common_ops->ipi_send_mask); gic_common_ops->ipi_send_mask(irq, dest); } + +enum gic_bit_access { + ACCESS_READ, + ACCESS_SET, + ACCESS_RMW +}; + +static u8 gic_masked_irq_bits(int irq, int offset, int bits, u8 value, + enum gic_bit_access access) +{ + void *base; + int split =3D 32 / bits; + int shift =3D (irq % split) * bits; + u32 reg =3D 0, mask =3D ((1U << bits) - 1) << shift; + + switch (gic_version()) { + case 2: + base =3D gicv2_dist_base(); + break; + case 3: + if (irq < 32) + base =3D gicv3_sgi_base(); + else + base =3D gicv3_dist_base(); + break; + default: + return 0; + } + base +=3D offset + (irq / split) * 4; + + switch (access) { + case ACCESS_READ: + return (readl(base) & mask) >> shift; + case ACCESS_SET: + reg =3D 0; + break; + case ACCESS_RMW: + reg =3D readl(base) & ~mask; + break; + } + + writel(reg | ((u32)value << shift), base); + + return 0; +} + +void gic_set_irq_bit(int irq, int offset) +{ + gic_masked_irq_bits(irq, offset, 1, 1, ACCESS_SET); +} + +void gic_enable_irq(int irq) +{ + gic_set_irq_bit(irq, GICD_ISENABLER); +} + +void gic_disable_irq(int irq) +{ + gic_set_irq_bit(irq, GICD_ICENABLER); +} + +void gic_set_irq_priority(int irq, u8 prio) +{ + gic_masked_irq_bits(irq, GICD_IPRIORITYR, 8, prio, ACCESS_RMW); +} + +void gic_set_irq_target(int irq, int cpu) +{ + if (irq < 32) + return; + + if (gic_version() =3D=3D 2) { + gic_masked_irq_bits(irq, GICD_ITARGETSR, 8, 1U << cpu, + ACCESS_RMW); + + return; + } + + writeq(cpus[cpu], gicv3_dist_base() + GICD_IROUTER + irq * 8); +} + +void gic_set_irq_group(int irq, int group) +{ + gic_masked_irq_bits(irq, GICD_IGROUPR, 1, group, ACCESS_RMW); +} + +int gic_get_irq_group(int irq) +{ + return gic_masked_irq_bits(irq, GICD_IGROUPR, 1, 0, ACCESS_READ); +} --=20 2.20.1 From MAILER-DAEMON Mon Dec 16 16:28:30 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1igxuo-0004uq-0W for mharc-qemu-arm@gnu.org; Mon, 16 Dec 2019 16:28:30 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:50007) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1igxul-0004ud-HL for qemu-arm@nongnu.org; Mon, 16 Dec 2019 16:28:29 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1igxuj-0004J6-M0 for qemu-arm@nongnu.org; Mon, 16 Dec 2019 16:28:27 -0500 Received: from mail-yw1-f68.google.com ([209.85.161.68]:38366) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1igxuj-0004Id-Fe; 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Mon, 16 Dec 2019 13:28:24 -0800 (PST) MIME-Version: 1.0 References: <20191202210947.3603-1-nieklinnenbank@gmail.com> <20191202210947.3603-10-nieklinnenbank@gmail.com> <6bee15d7-7d80-0709-ac90-ef2052b39329@redhat.com> <03a78f1d-e8fe-5a53-b061-d39de9ed7a9e@redhat.com> In-Reply-To: From: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= Date: Mon, 16 Dec 2019 22:28:12 +0100 Message-ID: Subject: Re: [PATCH 09/10] arm: allwinner-h3: add SD/MMC host controller To: Niek Linnenbank Cc: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= , Beniamino Galvani , Peter Maydell , qemu-arm , QEMU Developers Content-Type: multipart/alternative; boundary="0000000000003b09be0599d8e485" X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.85.161.68 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 16 Dec 2019 21:28:29 -0000 --0000000000003b09be0599d8e485 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Le lun. 16 d=C3=A9c. 2019 20:46, Niek Linnenbank = a =C3=A9crit : > > > On Mon, Dec 16, 2019 at 1:14 AM Philippe Mathieu-Daud=C3=A9 > wrote: > >> On 12/16/19 12:07 AM, Niek Linnenbank wrote: >> > >> > >> > On Fri, Dec 13, 2019 at 12:56 AM Philippe Mathieu-Daud=C3=A9 >> > > wrote: >> > >> > Hi Niek, >> > >> > On 12/11/19 11:34 PM, Niek Linnenbank wrote: >> [...] >> > > +static uint32_t aw_h3_sdhost_process_desc(AwH3SDHostState >> *s, >> > > + hwaddr desc_addr= , >> > > + TransferDescript= or >> > *desc, >> > > + bool is_write, >> > uint32_t >> > > max_bytes) >> > > +{ >> > > + uint32_t num_done =3D 0; >> > > + uint32_t num_bytes =3D max_bytes; >> > > + uint8_t buf[1024]; >> > > + >> > > + /* Read descriptor */ >> > > + cpu_physical_memory_read(desc_addr, desc, >> sizeof(*desc)); >> > >> > Should we worry about endianess here? >> > >> > >> > I tried to figure out what is expected, but the >> > Allwinner_H3_Datasheet_V1.2.pdf does not >> > explicitly mention endianness for any of its I/O devices. Currently it >> > seems all devices are >> > happy with using the same endianness as the CPUs. In the >> MemoryRegionOps >> > has DEVICE_NATIVE_ENDIAN >> > set to match the behavior seen. >> >> OK. >> >> [...] >> > > +static const MemoryRegionOps aw_h3_sdhost_ops =3D { >> > > + .read =3D aw_h3_sdhost_read, >> > > + .write =3D aw_h3_sdhost_write, >> > > + .endianness =3D DEVICE_NATIVE_ENDIAN, >> > >> > I haven't checked .valid accesses from the datasheet. >> > >> > However due to: >> > >> > res =3D s->data_crc[((offset - REG_SD_DATA7_CRC) / >> sizeof(uint32_t))]; >> > >> > You seem to expect: >> > >> > .impl.min_access_size =3D 4, >> > >> > .impl.max_access_size unset is 8, which should works. >> > >> > It seems that all registers are aligned on at least 32-bit boundaries. >> > And the section 5.3.5.1 mentions >> > that the DMA descriptors must be stored in memory 32-bit aligned. So >> > based on that information, >> >> So you are describing ".valid.min_access_size =3D 4", which is the minim= um >> access size on the bus. >> ".impl.min_access_size" is different, it is what access sizes is ready >> to handle your model. >> Your model read/write handlers expect addresses aligned on 32-bit >> boundary, this is why I suggested to use ".impl.min_access_size =3D 4". = If >> the guest were using a 16-bit access, your model would be buggy. If you >> describe your implementation to accept minimum 32-bit and the guest is >> allowed to use smaller accesses, QEMU will do a 32-bit access to the >> device, and return the 16-bit part to the guest. This way your model is >> safe. This is done by access_with_adjusted_size() in memory.c. >> If you restrict with ".valid.min_access_size =3D 4", you might think we >> don't need ".valid.min_access_size =3D 4" because all access from guest >> will be at least 32-bit. However keep in mind someone might find this >> device in another datasheet not limited to 32-bit, and let's say change >> to ".valid.min_access_size =3D 2". Without ".impl.min_access_size =3D 4" >> your model is buggy. So to be safe I'd use: >> >> .impl.min_access_size =3D 4, >> .valid.min_access_size =3D 4, >> > > Now it makes more sense to me, thanks Philippe for explaining this! > Great, I'll add .impl.min_access_size =3D 4. > > At this point, I've processed all the feedback that I received for all of > the patches > in this series. Is there anything else you would like to > see/discuss/review, or shall I send the v2 when I finish testing? > Send it! We'll discuss on updated v2 :) Regards, Phil. --0000000000003b09be0599d8e485 Content-Type: text/html; charset="UTF-8" Content-Transfer-Encoding: quoted-printable
Le lun. 16 d=C3=A9c. 2019 20:46, Niek Linnenbank <nieklinnenbank@gmail.com> a =C3= =A9crit=C2=A0:


On Mon, Dec 16, 2019 at 1:14 AM Philippe Mathieu-Daud=C3= =A9 <philmd@redhat.com> wrote:
On 12/16/19 12:07 AM, Niek Linnenbank wrote:
>
>
> On Fri, Dec 13, 2019 at 12:56 AM Philippe Mathieu-Daud=C3=A9
> <philmd@redhat.com <mailto:philmd@redhat.com>> wrote= :
>
>=C2=A0 =C2=A0 =C2=A0Hi Niek,
>
>=C2=A0 =C2=A0 =C2=A0On 12/11/19 11:34 PM, Niek Linnenbank wrote:
[...]
>=C2=A0 =C2=A0 =C2=A0 >=C2=A0 =C2=A0 =C2=A0+static uint32_t aw_h3_sdh= ost_process_desc(AwH3SDHostState *s,
>=C2=A0 =C2=A0 =C2=A0 >=C2=A0 =C2=A0 =C2=A0+=C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 hwaddr desc_addr,
>=C2=A0 =C2=A0 =C2=A0 >=C2=A0 =C2=A0 =C2=A0+=C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 TransferDescriptor
>=C2=A0 =C2=A0 =C2=A0*desc,
>=C2=A0 =C2=A0 =C2=A0 >=C2=A0 =C2=A0 =C2=A0+=C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 bool is_write,
>=C2=A0 =C2=A0 =C2=A0uint32_t
>=C2=A0 =C2=A0 =C2=A0 >=C2=A0 =C2=A0 =C2=A0max_bytes)
>=C2=A0 =C2=A0 =C2=A0 >=C2=A0 =C2=A0 =C2=A0+{
>=C2=A0 =C2=A0 =C2=A0 >=C2=A0 =C2=A0 =C2=A0+=C2=A0 =C2=A0 uint32_t nu= m_done =3D 0;
>=C2=A0 =C2=A0 =C2=A0 >=C2=A0 =C2=A0 =C2=A0+=C2=A0 =C2=A0 uint32_t nu= m_bytes =3D max_bytes;
>=C2=A0 =C2=A0 =C2=A0 >=C2=A0 =C2=A0 =C2=A0+=C2=A0 =C2=A0 uint8_t buf= [1024];
>=C2=A0 =C2=A0 =C2=A0 >=C2=A0 =C2=A0 =C2=A0+
>=C2=A0 =C2=A0 =C2=A0 >=C2=A0 =C2=A0 =C2=A0+=C2=A0 =C2=A0 /* Read des= criptor */
>=C2=A0 =C2=A0 =C2=A0 >=C2=A0 =C2=A0 =C2=A0+=C2=A0 =C2=A0 cpu_physica= l_memory_read(desc_addr, desc, sizeof(*desc));
>
>=C2=A0 =C2=A0 =C2=A0Should we worry about endianess here?
>
>
> I tried to figure out what is expected, but the
> Allwinner_H3_Datasheet_V1.2.pdf does not
> explicitly mention endianness for any of its I/O devices. Currently it=
> seems all devices are
> happy with using the same endianness as the CPUs. In the MemoryRegionO= ps
> has DEVICE_NATIVE_ENDIAN
> set to match the behavior seen.

OK.

[...]
>=C2=A0 =C2=A0 =C2=A0 >=C2=A0 =C2=A0 =C2=A0+static const MemoryRegion= Ops aw_h3_sdhost_ops =3D {
>=C2=A0 =C2=A0 =C2=A0 >=C2=A0 =C2=A0 =C2=A0+=C2=A0 =C2=A0 .read =3D a= w_h3_sdhost_read,
>=C2=A0 =C2=A0 =C2=A0 >=C2=A0 =C2=A0 =C2=A0+=C2=A0 =C2=A0 .write =3D = aw_h3_sdhost_write,
>=C2=A0 =C2=A0 =C2=A0 >=C2=A0 =C2=A0 =C2=A0+=C2=A0 =C2=A0 .endianness= =3D DEVICE_NATIVE_ENDIAN,
>
>=C2=A0 =C2=A0 =C2=A0I haven't checked .valid accesses from the data= sheet.
>
>=C2=A0 =C2=A0 =C2=A0However due to:
>
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0res =3D s->data_crc[((offset - REG= _SD_DATA7_CRC) / sizeof(uint32_t))];
>
>=C2=A0 =C2=A0 =C2=A0You seem to expect:
>
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 .impl.mi= n_access_size =3D 4,
>
>=C2=A0 =C2=A0 =C2=A0.impl.max_access_size unset is 8, which should work= s.
>
> It seems that all registers are aligned on at least 32-bit boundaries.=
> And the section 5.3.5.1 mentions
> that the DMA descriptors must be stored in memory 32-bit aligned. So <= br> > based on that information,

So you are describing ".valid.min_access_size =3D 4", which is th= e minimum
access size on the bus.
".impl.min_access_size" is different, it is what access sizes is = ready
to handle your model.
Your model read/write handlers expect addresses aligned on 32-bit
boundary, this is why I suggested to use ".impl.min_access_size =3D 4&= quot;. If
the guest were using a 16-bit access, your model would be buggy. If you describe your implementation to accept minimum 32-bit and the guest is
allowed to use smaller accesses, QEMU will do a 32-bit access to the
device, and return the 16-bit part to the guest. This way your model is safe. This is done by access_with_adjusted_size() in memory.c.
If you restrict with ".valid.min_access_size =3D 4", you might th= ink we
don't need ".valid.min_access_size =3D 4" because all access = from guest
will be at least 32-bit. However keep in mind someone might find this
device in another datasheet not limited to 32-bit, and let's say change=
to ".valid.min_access_size =3D 2". Without ".impl.min_access= _size =3D 4"
your model is buggy. So to be safe I'd use:

=C2=A0 =C2=A0.impl.min_access_size =3D 4,
=C2=A0 =C2=A0.valid.min_access_size =3D 4,

<= div>Now it makes more sense to me, thanks Philippe for explaining this!
=
Great, I'll add .impl.min_access_size =3D 4.

<= /div>
At this point, I've processed all the feedback that I receive= d for all of the patches
in this series. Is there anything else y= ou would like to see/discuss/review, or shall I send the v2 when I finish t= esting?
Send it! We'll discuss on updated v2 :)
<= div dir=3D"auto">
Regards,=C2=A0

Phil.
--0000000000003b09be0599d8e485-- From MAILER-DAEMON Mon Dec 16 18:36:09 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1igzuL-0006jZ-4t for mharc-qemu-arm@gnu.org; Mon, 16 Dec 2019 18:36:09 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:50250) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1igzuG-0006bu-KS for qemu-arm@nongnu.org; Mon, 16 Dec 2019 18:36:06 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1igzuE-0002i5-QL for qemu-arm@nongnu.org; Mon, 16 Dec 2019 18:36:04 -0500 Received: from mail-wm1-x341.google.com ([2a00:1450:4864:20::341]:40621) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1igzuB-0002bL-Iq; Mon, 16 Dec 2019 18:35:59 -0500 Received: by mail-wm1-x341.google.com with SMTP id t14so1089529wmi.5; Mon, 16 Dec 2019 15:35:59 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=56k1gd9w0pzweQ0pdSRVAAe2bI3hcno8MwlnwkRM6ZM=; b=GjXqTY/ih7teLgDrI7tdcAfP6FdrS/tg4tyIQlG+Va8lA0ejPhApBtoeU7Gn17L/DB UAMECp1O8NZ4JyWBXK7AA6ucMHnLQLyLgJHnXICECNzNefL55Ix1u/hfhYxubxrNVRbs OBzczXp1m697AplJg7C9lcmCWEuwgVMxtE9BYVdHO5nIrDjn+6LwCBZ5o0mPQAP5nnJy eEd0ozY8kCoY4xrSbc1EFgR7+9RMpcChZZ5e5Nf5PdbapjP0b5OAHvSlPCT5Rsv20hmF CQveeZsttOomZ2miOnTGp6io2+ne51SNSp0MIdn6NaqztQWnRA2QnP12n4czglYhhGaA hV+w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=56k1gd9w0pzweQ0pdSRVAAe2bI3hcno8MwlnwkRM6ZM=; b=QvEuTV494i6AZdQC9PFKHENb+gotnQEpBxncHNpXXQbdn99Q/9GBOHiPmzrDXZ6j9l 17reOF3ps3ldrxgeXDwlh8g2M/CkFduZvE1aGSun8E8MzWhneNuCE3dDY64e04gW2RQR oxduiPkvlAiyD1kk4fBQRwYffK/LF6hnUzk/NfBazQKmdwISSzIe9cYgMknBJD9UcgNJ OziW/RuHekQ7X/2OaTneEUDV3vwjmQZM0xwM+MQlNWf5fO0fuw5RBjV45x0+3udf1lqC hwvxQORjkBtQ7i9PYyn7HN+oKxXAKG+WACB+95sYMzt9mbUeUDtYYgOq2dCwrcjzgeT1 jqrw== X-Gm-Message-State: APjAAAXxMv1JhxBWVRBuXW51QrSFjwmDc2Tq+RhC9O4tvQ3mDZ315g9M dKWOZg2LTK1bMZdCczl09nVm+k2u X-Google-Smtp-Source: APXvYqxHJsDUECQUP0Q50PY96e8rOKZaO8x7NBoR98Xby9ML67U+rg2/PncZ+/L4+lLM0glmJzXfvA== X-Received: by 2002:a7b:c114:: with SMTP id w20mr1660722wmi.151.1576539358199; Mon, 16 Dec 2019 15:35:58 -0800 (PST) Received: from pavilion.home ([2a02:a456:6be8:1:8edc:d4ff:fe8b:18b7]) by smtp.gmail.com with ESMTPSA id z83sm984501wmg.2.2019.12.16.15.35.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 16 Dec 2019 15:35:57 -0800 (PST) From: Niek Linnenbank To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, peter.maydell@linaro.org, philmd@redhat.com, Niek Linnenbank Subject: [PATCH v2 02/10] hw: arm: add Xunlong Orange Pi PC machine Date: Tue, 17 Dec 2019 00:35:11 +0100 Message-Id: <20191216233519.29030-3-nieklinnenbank@gmail.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20191216233519.29030-1-nieklinnenbank@gmail.com> References: <20191216233519.29030-1-nieklinnenbank@gmail.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::341 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 16 Dec 2019 23:36:07 -0000 The Xunlong Orange Pi PC is an Allwinner H3 System on Chip based embedded computer with mainline support in both U-Boot and Linux. The board comes with a Quad Core Cortex A7 @ 1.3GHz, 512MB RAM, 100Mbit ethernet, USB, SD/MMC, USB, HDMI and various other I/O. This commit add support for the Xunlong Orange Pi PC machine. Signed-off-by: Niek Linnenbank Tested-by: KONRAD Frederic --- hw/arm/orangepi.c | 101 +++++++++++++++++++++++++++++++++++++++++++ MAINTAINERS | 1 + hw/arm/Makefile.objs | 2 +- 3 files changed, 103 insertions(+), 1 deletion(-) create mode 100644 hw/arm/orangepi.c diff --git a/hw/arm/orangepi.c b/hw/arm/orangepi.c new file mode 100644 index 0000000000..62cefc8c06 --- /dev/null +++ b/hw/arm/orangepi.c @@ -0,0 +1,101 @@ +/* + * Orange Pi emulation + * + * Copyright (C) 2019 Niek Linnenbank + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#include "qemu/osdep.h" +#include "exec/address-spaces.h" +#include "qapi/error.h" +#include "cpu.h" +#include "hw/sysbus.h" +#include "hw/boards.h" +#include "hw/qdev-properties.h" +#include "hw/arm/allwinner-h3.h" + +static struct arm_boot_info orangepi_binfo = { + .board_id = -1, +}; + +typedef struct OrangePiState { + AwH3State *h3; + MemoryRegion sdram; +} OrangePiState; + +static void orangepi_init(MachineState *machine) +{ + OrangePiState *s = g_new(OrangePiState, 1); + + /* Only allow Cortex-A7 for this board */ + if (strcmp(machine->cpu_type, ARM_CPU_TYPE_NAME("cortex-a7")) != 0) { + error_report("This board can only be used with cortex-a7 CPU"); + exit(1); + } + + s->h3 = AW_H3(object_new(TYPE_AW_H3)); + + /* Setup timer properties */ + object_property_set_int(OBJECT(&s->h3->timer), 32768, "clk0-freq", + &error_abort); + if (error_abort != NULL) { + error_reportf_err(error_abort, "Couldn't set clk0 frequency: "); + exit(1); + } + + object_property_set_int(OBJECT(&s->h3->timer), 24000000, "clk1-freq", + &error_abort); + if (error_abort != NULL) { + error_reportf_err(error_abort, "Couldn't set clk1 frequency: "); + exit(1); + } + + /* Mark H3 object realized */ + object_property_set_bool(OBJECT(s->h3), true, "realized", &error_abort); + if (error_abort != NULL) { + error_reportf_err(error_abort, "Couldn't realize Allwinner H3: "); + exit(1); + } + + /* RAM */ + if (machine->ram_size > 1 * GiB) { + error_report("Requested ram size is too large for this machine: " + "maximum is 1GB"); + exit(1); + } + memory_region_allocate_system_memory(&s->sdram, NULL, "orangepi.ram", + machine->ram_size); + memory_region_add_subregion(get_system_memory(), s->h3->memmap[AW_H3_SDRAM], + &s->sdram); + + /* Load target kernel */ + orangepi_binfo.loader_start = s->h3->memmap[AW_H3_SDRAM]; + orangepi_binfo.ram_size = machine->ram_size; + orangepi_binfo.nb_cpus = AW_H3_NUM_CPUS; + arm_load_kernel(ARM_CPU(first_cpu), machine, &orangepi_binfo); +} + +static void orangepi_machine_init(MachineClass *mc) +{ + mc->desc = "Orange Pi PC"; + mc->init = orangepi_init; + mc->units_per_default_bus = 1; + mc->min_cpus = AW_H3_NUM_CPUS; + mc->max_cpus = AW_H3_NUM_CPUS; + mc->default_cpus = AW_H3_NUM_CPUS; + mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-a7"); +} + +DEFINE_MACHINE("orangepi-pc", orangepi_machine_init) diff --git a/MAINTAINERS b/MAINTAINERS index aae1a049b4..db682e49ca 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -486,6 +486,7 @@ L: qemu-arm@nongnu.org S: Maintained F: hw/*/allwinner-h3* F: include/hw/*/allwinner-h3* +F: hw/arm/orangepi.c ARM PrimeCell and CMSDK devices M: Peter Maydell diff --git a/hw/arm/Makefile.objs b/hw/arm/Makefile.objs index 956e496052..8d5ea453d5 100644 --- a/hw/arm/Makefile.objs +++ b/hw/arm/Makefile.objs @@ -34,7 +34,7 @@ obj-$(CONFIG_DIGIC) += digic.o obj-$(CONFIG_OMAP) += omap1.o omap2.o obj-$(CONFIG_STRONGARM) += strongarm.o obj-$(CONFIG_ALLWINNER_A10) += allwinner-a10.o cubieboard.o -obj-$(CONFIG_ALLWINNER_H3) += allwinner-h3.o +obj-$(CONFIG_ALLWINNER_H3) += allwinner-h3.o orangepi.o obj-$(CONFIG_RASPI) += bcm2835_peripherals.o bcm2836.o raspi.o obj-$(CONFIG_STM32F205_SOC) += stm32f205_soc.o obj-$(CONFIG_XLNX_ZYNQMP_ARM) += xlnx-zynqmp.o xlnx-zcu102.o -- 2.17.1 From MAILER-DAEMON Mon Dec 16 18:36:09 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1igzuL-0006ju-BU for mharc-qemu-arm@gnu.org; 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Mon, 16 Dec 2019 15:36:00 -0800 (PST) From: Niek Linnenbank To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, peter.maydell@linaro.org, philmd@redhat.com, Niek Linnenbank Subject: [PATCH v2 06/10] arm/arm-powerctl: rebuild hflags after setting CP15 bits in arm_set_cpu_on() Date: Tue, 17 Dec 2019 00:35:15 +0100 Message-Id: <20191216233519.29030-7-nieklinnenbank@gmail.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20191216233519.29030-1-nieklinnenbank@gmail.com> References: <20191216233519.29030-1-nieklinnenbank@gmail.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::341 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 16 Dec 2019 23:36:08 -0000 After setting CP15 bits in arm_set_cpu_on() the cached hflags must be rebuild to reflect the changed processor state. Without rebuilding, the cached hflags would be inconsistent until the next call to arm_rebuild_hflags(). When QEMU is compiled with debugging enabled (--enable-debug), this problem is captured shortly after the first call to arm_set_cpu_on() for CPUs running in ARM 32-bit non-secure mode: qemu-system-arm: target/arm/helper.c:11359: cpu_get_tb_cpu_state: Assertion `flags == rebuild_hflags_internal(env)' failed. Aborted (core dumped) Fixes: 0c7f8c43daf65 Signed-off-by: Niek Linnenbank --- target/arm/arm-powerctl.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/target/arm/arm-powerctl.c b/target/arm/arm-powerctl.c index b064513d44..b75f813b40 100644 --- a/target/arm/arm-powerctl.c +++ b/target/arm/arm-powerctl.c @@ -127,6 +127,9 @@ static void arm_set_cpu_on_async_work(CPUState *target_cpu_state, target_cpu->env.regs[0] = info->context_id; } + /* CP15 update requires rebuilding hflags */ + arm_rebuild_hflags(&target_cpu->env); + /* Start the new CPU at the requested address */ cpu_set_pc(target_cpu_state, info->entry); -- 2.17.1 From MAILER-DAEMON Mon Dec 16 18:36:10 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1igzuM-0006me-Qa for mharc-qemu-arm@gnu.org; Mon, 16 Dec 2019 18:36:10 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:50288) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1igzuH-0006dZ-JA for qemu-arm@nongnu.org; Mon, 16 Dec 2019 18:36:06 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1igzuF-0002lX-RU for qemu-arm@nongnu.org; Mon, 16 Dec 2019 18:36:05 -0500 Received: from mail-wm1-x342.google.com ([2a00:1450:4864:20::342]:40622) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1igzuC-0002dj-VS; Mon, 16 Dec 2019 18:36:01 -0500 Received: by mail-wm1-x342.google.com with SMTP id t14so1089575wmi.5; Mon, 16 Dec 2019 15:36:00 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=SmQGHNsBURH4ZGvWc+jJV85ra1jitK2x3YLYu4ESBHA=; b=eebgMRtOxy/MIixwrQ7v/tJFD5RvEvCgFrI/G5lyGQjhVl2R/WPOL+SmDdH8JW5AOI v6Y/5KgLr4tseL8EduoDkw3k0d2kgLJjJgUGrm+VchDM9FiDkOA5bsJp5MA4p3EwxNDi LmrnxWtA7DnLR37goPp2BVCEWi4+z2kL9wReqzyhR3RoVdXGanmjoTkWenVCMAYzJ/XR kUN1qKvxy3lEnU66DyOPDY02JaASCf/IBByDhJ5f9P5owl8pDCpTSnDbmTeV/oAq+ehU 5D0k+iJ2BP/ujHSOIlJAIs6DVNZjg7p1psrmK1/Bs9Zn15WZr4A8Pfmk1JTA1JW/ejyw Tamg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=SmQGHNsBURH4ZGvWc+jJV85ra1jitK2x3YLYu4ESBHA=; b=WoJCBBjXguzYGrkZyjOyGUB/CriY/l+NYAT+6JvA0okQnEF59DmTrozEBuCWLSyPFz 8C2/hHrRivPnlKgauO48XA/XH2mqHpAeSfO5eUKsIxGfgtO0qw/ssYQB/Fyn8Ef/55QN JWllBv99xGMNB96ho+0JVOWP+0SxO5bDuI1GTBeuQtHndu5r9R3S5j4IXaD+pStAWsyl DqbjbMRLeFz4LL3id3ZL6uM3RKHpEcmXuQ67+5C4/99oV5+5MwgAF82O3N4bGitZIyS8 QavC4Ql/EEIcWus9micOpCp+S39mEJNUGKBzTIDLt9U/7JmWgWYPX6MaQTyuqUQ5cA2S 8myg== X-Gm-Message-State: APjAAAVidfUI+XGUsopPjVn0DIuKm27uR4jOHJGT84TaMW3O3YoAQstN omBQxBh8FO061V262Ql+Lrmw+tD0 X-Google-Smtp-Source: APXvYqx6GvsRlwi2V+TZgCgxtfgIUs+UHh8h53/oJoHFj83YBteiUEYKoUF9Y+DCN04p0v/qGxwmPw== X-Received: by 2002:a1c:8095:: with SMTP id b143mr1759229wmd.7.1576539359747; Mon, 16 Dec 2019 15:35:59 -0800 (PST) Received: from pavilion.home ([2a02:a456:6be8:1:8edc:d4ff:fe8b:18b7]) by smtp.gmail.com with ESMTPSA id z83sm984501wmg.2.2019.12.16.15.35.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 16 Dec 2019 15:35:59 -0800 (PST) From: Niek Linnenbank To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, peter.maydell@linaro.org, philmd@redhat.com, Niek Linnenbank Subject: [PATCH v2 04/10] arm: allwinner-h3: add USB host controller Date: Tue, 17 Dec 2019 00:35:13 +0100 Message-Id: <20191216233519.29030-5-nieklinnenbank@gmail.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20191216233519.29030-1-nieklinnenbank@gmail.com> References: <20191216233519.29030-1-nieklinnenbank@gmail.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::342 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 16 Dec 2019 23:36:08 -0000 The Allwinner H3 System on Chip contains multiple USB 2.0 bus connections which provide software access using the Enhanced Host Controller Interface (EHCI) and Open Host Controller Interface (OHCI) interfaces. This commit adds support for both interfaces in the Allwinner H3 System on Chip. Signed-off-by: Niek Linnenbank Reviewed-by: Gerd Hoffmann --- hw/usb/hcd-ehci.h | 1 + hw/arm/allwinner-h3.c | 28 ++++++++++++++++++++++++++++ hw/usb/hcd-ehci-sysbus.c | 17 +++++++++++++++++ 3 files changed, 46 insertions(+) diff --git a/hw/usb/hcd-ehci.h b/hw/usb/hcd-ehci.h index 0298238f0b..edb59311c4 100644 --- a/hw/usb/hcd-ehci.h +++ b/hw/usb/hcd-ehci.h @@ -342,6 +342,7 @@ typedef struct EHCIPCIState { #define TYPE_SYS_BUS_EHCI "sysbus-ehci-usb" #define TYPE_PLATFORM_EHCI "platform-ehci-usb" #define TYPE_EXYNOS4210_EHCI "exynos4210-ehci-usb" +#define TYPE_AW_H3_EHCI "aw-h3-ehci-usb" #define TYPE_TEGRA2_EHCI "tegra2-ehci-usb" #define TYPE_PPC4xx_EHCI "ppc4xx-ehci-usb" #define TYPE_FUSBH200_EHCI "fusbh200-ehci-usb" diff --git a/hw/arm/allwinner-h3.c b/hw/arm/allwinner-h3.c index 0da09188d1..f0ea088852 100644 --- a/hw/arm/allwinner-h3.c +++ b/hw/arm/allwinner-h3.c @@ -26,6 +26,7 @@ #include "hw/sysbus.h" #include "hw/arm/allwinner-h3.h" #include "hw/misc/unimp.h" +#include "hw/usb/hcd-ehci.h" #include "sysemu/sysemu.h" /* Memory map */ @@ -317,6 +318,33 @@ static void aw_h3_realize(DeviceState *dev, Error **errp) qdev_init_nofail(DEVICE(&s->ccu)); sysbus_mmio_map(SYS_BUS_DEVICE(&s->ccu), 0, s->memmap[AW_H3_CCU]); + /* Universal Serial Bus */ + sysbus_create_simple(TYPE_AW_H3_EHCI, s->memmap[AW_H3_EHCI0], + qdev_get_gpio_in(DEVICE(&s->gic), + AW_H3_GIC_SPI_EHCI0)); + sysbus_create_simple(TYPE_AW_H3_EHCI, s->memmap[AW_H3_EHCI1], + qdev_get_gpio_in(DEVICE(&s->gic), + AW_H3_GIC_SPI_EHCI1)); + sysbus_create_simple(TYPE_AW_H3_EHCI, s->memmap[AW_H3_EHCI2], + qdev_get_gpio_in(DEVICE(&s->gic), + AW_H3_GIC_SPI_EHCI2)); + sysbus_create_simple(TYPE_AW_H3_EHCI, s->memmap[AW_H3_EHCI3], + qdev_get_gpio_in(DEVICE(&s->gic), + AW_H3_GIC_SPI_EHCI3)); + + sysbus_create_simple("sysbus-ohci", s->memmap[AW_H3_OHCI0], + qdev_get_gpio_in(DEVICE(&s->gic), + AW_H3_GIC_SPI_OHCI0)); + sysbus_create_simple("sysbus-ohci", s->memmap[AW_H3_OHCI1], + qdev_get_gpio_in(DEVICE(&s->gic), + AW_H3_GIC_SPI_OHCI1)); + sysbus_create_simple("sysbus-ohci", s->memmap[AW_H3_OHCI2], + qdev_get_gpio_in(DEVICE(&s->gic), + AW_H3_GIC_SPI_OHCI2)); + sysbus_create_simple("sysbus-ohci", s->memmap[AW_H3_OHCI3], + qdev_get_gpio_in(DEVICE(&s->gic), + AW_H3_GIC_SPI_OHCI3)); + /* UART0 */ serial_mm_init(get_system_memory(), s->memmap[AW_H3_UART0], 2, qdev_get_gpio_in(DEVICE(&s->gic), AW_H3_GIC_SPI_UART0), diff --git a/hw/usb/hcd-ehci-sysbus.c b/hw/usb/hcd-ehci-sysbus.c index 020211fd10..174c3446ef 100644 --- a/hw/usb/hcd-ehci-sysbus.c +++ b/hw/usb/hcd-ehci-sysbus.c @@ -145,6 +145,22 @@ static const TypeInfo ehci_exynos4210_type_info = { .class_init = ehci_exynos4210_class_init, }; +static void ehci_aw_h3_class_init(ObjectClass *oc, void *data) +{ + SysBusEHCIClass *sec = SYS_BUS_EHCI_CLASS(oc); + DeviceClass *dc = DEVICE_CLASS(oc); + + sec->capsbase = 0x0; + sec->opregbase = 0x10; + set_bit(DEVICE_CATEGORY_USB, dc->categories); +} + +static const TypeInfo ehci_aw_h3_type_info = { + .name = TYPE_AW_H3_EHCI, + .parent = TYPE_SYS_BUS_EHCI, + .class_init = ehci_aw_h3_class_init, +}; + static void ehci_tegra2_class_init(ObjectClass *oc, void *data) { SysBusEHCIClass *sec = SYS_BUS_EHCI_CLASS(oc); @@ -267,6 +283,7 @@ static void ehci_sysbus_register_types(void) type_register_static(&ehci_platform_type_info); type_register_static(&ehci_xlnx_type_info); type_register_static(&ehci_exynos4210_type_info); + type_register_static(&ehci_aw_h3_type_info); type_register_static(&ehci_tegra2_type_info); type_register_static(&ehci_ppc4xx_type_info); type_register_static(&ehci_fusbh200_type_info); -- 2.17.1 From MAILER-DAEMON Mon Dec 16 18:36:11 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1igzuN-0006np-Ha for mharc-qemu-arm@gnu.org; Mon, 16 Dec 2019 18:36:11 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:50281) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1igzuH-0006dA-CQ for qemu-arm@nongnu.org; Mon, 16 Dec 2019 18:36:07 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1igzuF-0002iU-2M for qemu-arm@nongnu.org; Mon, 16 Dec 2019 18:36:05 -0500 Received: from mail-wr1-x42f.google.com ([2a00:1450:4864:20::42f]:40361) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1igzuA-0002Ye-UY; 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Mon, 16 Dec 2019 15:35:56 -0800 (PST) Received: from pavilion.home ([2a02:a456:6be8:1:8edc:d4ff:fe8b:18b7]) by smtp.gmail.com with ESMTPSA id z83sm984501wmg.2.2019.12.16.15.35.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 16 Dec 2019 15:35:55 -0800 (PST) From: Niek Linnenbank To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, peter.maydell@linaro.org, philmd@redhat.com, Niek Linnenbank Subject: [PATCH v2 00/10] Add Allwinner H3 SoC and Orange Pi PC Machine Date: Tue, 17 Dec 2019 00:35:09 +0100 Message-Id: <20191216233519.29030-1-nieklinnenbank@gmail.com> X-Mailer: git-send-email 2.17.1 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::42f X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 16 Dec 2019 23:36:08 -0000 Dear QEMU developers, Hereby I would like to contribute the following set of patches to QEMU which add support for the Allwinner H3 System on Chip and the Orange Pi PC machine. The following features and devices are supported: * SMP (Quad Core Cortex A7) * Generic Interrupt Controller configuration * SRAM mappings * Timer device (re-used from Allwinner A10) * UART * SD/MMC storage controller * EMAC ethernet connectivity * USB 2.0 interfaces * Clock Control Unit * System Control module * Security Identifier device Functionality related to graphical output such as HDMI, GPU, Display Engine and audio are not included. Recently released mainline Linux kernels (4.19 up to latest master) and mainline U-Boot are known to work. The SD/MMC code is tested using bonnie++ and various tools such as fsck, dd and fdisk. The EMAC is verified with iperf3 using -netdev socket. To build a Linux mainline kernel that can be booted by the Orange Pi PC machine, simply configure the kernel using the sunxi_defconfig configuration: $ ARCH=arm CROSS_COMPILE=arm-linux-gnueabi- make mrproper $ ARCH=arm CROSS_COMPILE=arm-linux-gnueabi- make sunxi_defconfig To be able to use USB storage, you need to manually enable the corresponding configuration item. Start the kconfig configuration tool: $ ARCH=arm CROSS_COMPILE=arm-linux-gnueabi- make menuconfig Navigate to the following item, enable it and save your configuration: Device Drivers > USB support > USB Mass Storage support Build the Linux kernel with: $ ARCH=arm CROSS_COMPILE=arm-linux-gnueabi- make -j5 To boot the newly build linux kernel in QEMU with the Orange Pi PC machine, use: $ qemu-system-arm -M orangepi-pc -m 512 -nic user -nographic \ -kernel /path/to/linux/arch/arm/boot/zImage \ -append 'console=ttyS0,115200' \ -dtb /path/to/linux/arch/arm/boot/dts/sun8i-h3-orangepi-pc.dtb Note that this kernel does not have a root filesystem. You may provide it with an official Orange Pi PC image [1] either as an SD card or as USB mass storage. To boot using the Orange Pi PC Debian image on SD card, simply add the -sd argument and provide the proper root= kernel parameter: $ qemu-system-arm -M orangepi-pc -m 512 -nic user -nographic \ -kernel /path/to/linux/arch/arm/boot/zImage \ -append 'console=ttyS0,115200 root=/dev/mmcblk0p2' \ -dtb /path/to/linux/arch/arm/boot/dts/sun8i-h3-orangepi-pc.dtb \ -sd OrangePi_pc_debian_stretch_server_linux5.3.5_v1.0.img Alternatively, you can also choose to build and boot a recent buildroot [2] using the orangepi_pc_defconfig or Armbian image [3] for Orange Pi PC. To attach an USB mass storage device to the machine, simply append to the command: -drive if=none,id=stick,file=myimage.img \ -device usb-storage,bus=usb-bus.0,drive=stick U-Boot mainline can be build and configured using the orangepi_pc_defconfig using similar commands as describe above for Linux. To start U-Boot using the Orange Pi PC machine, provide the u-boot binary to the -kernel argument: $ qemu-system-arm -M orangepi-pc -m 512 -nic user -nographic \ -kernel /path/to/uboot/u-boot -sd disk.img Use the following U-boot commands to load and boot a Linux kernel from SD card: -> setenv bootargs console=ttyS0,115200 -> ext2load mmc 0 0x42000000 zImage -> ext2load mmc 0 0x43000000 sun8i-h3-orangepi-pc.dtb -> bootz 0x42000000 - 0x43000000 Looking forward to your review comments. I will do my best to update the patches where needed. ===== CHANGELOG ===== v2: * hw/arm/allwinner-h3.c: use cpus array in AwH3State instead of object_new() * hw/arm/allwinner-h3.c: use error_abort in aw_h3_realize() * hw/arm/allwinner-h3.c: use qdev_init_nofail() in aw_h3_realize() * hw/arm/allwinner-h3.c: use qdev_get_gpio_in() instead of irq array * hw/arm/allwinner-h3.c: add all missing unimplemented devices (memory map is complete) * hw/arm/allwinner-h3.c: add UART1, UART2, UART3 and remove 'if (serial_hd(...))' * hw/arm/allwinner-h3.c: remove sysbusdev variable and use SYS_BUS_DEVICE() directly * include/hw/arm/allwinner-h3.h: move PPI/SPI defines to allwinner-h3.c as enum * include/hw/arm/allwinner-h3.h: replace mem base/size defines with enum and memmap (like aspeed_soc.h) * hw/arm/orangepi.c: Only allow Cortex-A7 in machine->cpu_type * hw/arm/orangepi.c: Set mc->default_cpu_type to ARM_CPU_TYPE_NAME("cortex-a7") * hw/arm/orangepi.c: Use error_abort in orangepi_init() * hw/arm/orangepi.c: only allow maximum 1GiB RAM * hw/arm/orangepi.c: renamed machine name to 'orangepi-pc' * hw/arm/orangepi.c: remove mc->ignore_memory_transaction_failures = true * hw/arm/orangepi.c: remove unnecessary check for 'sd-bus' * hw/net/allwinner-h3-emac.c: use AW_H3_EMAC() for opaque in read/write functions * hw/sd/allwinner-h3-sdhost.c: replace register defines with enums * hw/sd/allwinner-h3-sdhost.c: remove 'irq_en' and use if() to set 'irq' in update_irq function * hw/sd/allwinner-h3-sdhost.c: simplified if (rlen==) conditions in send_command function * hw/sd/allwinner-h3-sdhost.c: use KiB macro to set desc->size * hw/sd/allwinner-h3-sdhost.c: use ARRAY_SIZE() macro in reset function * hw/misc/allwinner-h3-sid.c: replace randomized identifier with QemuUUID property * hw/misc/allwinner-h3-sid.c: add tracing for read/write functions * hw/misc/allwinner-h3-sid.c: fix incorrect usage of REG_PRCTL_OP_LOCK/REG_PRCTL_WRITE * hw/misc/trace-events: add allwinner_h3_cpucfg* entries in correct patch (#7) * hw/*/trace-events: use PRIu32/PRIx32 macros for size and max fields * hw/*/allwinner-h3-*.c: set .impl.min_access_size = 4 to restrict MMIO access to 32-bit aligned * hw/*/allwinner-h3-*.c: replace register defines with enums * hw/*/allwinner-h3-*.c: set VMStateDescription.name with inline string (dont use TYPE macro) * include/hw/*/allwinner-h3-*.h: remove MEM_SIZE define and use size inline in the source file * target/arm/arm-powerctl.c: invoke arm_rebuild_hflags() after setting CP15 bits With kind regards, Niek Linnenbank [1] http://www.orangepi.org/downloadresources/ [2] https://buildroot.org/download.html [3] https://www.armbian.com/orange-pi-pc/ Niek Linnenbank (10): hw: arm: add Allwinner H3 System-on-Chip hw: arm: add Xunlong Orange Pi PC machine arm: allwinner-h3: add Clock Control Unit arm: allwinner-h3: add USB host controller arm: allwinner-h3: add System Control module arm/arm-powerctl: rebuild hflags after setting CP15 bits in arm_set_cpu_on() arm: allwinner-h3: add CPU Configuration module arm: allwinner-h3: add Security Identifier device arm: allwinner-h3: add SD/MMC host controller arm: allwinner-h3: add EMAC ethernet device default-configs/arm-softmmu.mak | 1 + hw/usb/hcd-ehci.h | 1 + include/hw/arm/allwinner-h3.h | 93 +++ include/hw/misc/allwinner-h3-clk.h | 40 ++ include/hw/misc/allwinner-h3-cpucfg.h | 42 ++ include/hw/misc/allwinner-h3-sid.h | 40 ++ include/hw/misc/allwinner-h3-syscon.h | 42 ++ include/hw/net/allwinner-h3-emac.h | 67 +++ include/hw/sd/allwinner-h3-sdhost.h | 71 +++ hw/arm/allwinner-h3.c | 442 ++++++++++++++ hw/arm/orangepi.c | 127 ++++ hw/misc/allwinner-h3-clk.c | 238 ++++++++ hw/misc/allwinner-h3-cpucfg.c | 288 +++++++++ hw/misc/allwinner-h3-sid.c | 179 ++++++ hw/misc/allwinner-h3-syscon.c | 146 +++++ hw/net/allwinner-h3-emac.c | 829 ++++++++++++++++++++++++++ hw/sd/allwinner-h3-sdhost.c | 813 +++++++++++++++++++++++++ hw/usb/hcd-ehci-sysbus.c | 17 + target/arm/arm-powerctl.c | 3 + MAINTAINERS | 8 + hw/arm/Kconfig | 9 + hw/arm/Makefile.objs | 1 + hw/misc/Makefile.objs | 4 + hw/misc/trace-events | 9 + hw/net/Kconfig | 3 + hw/net/Makefile.objs | 1 + hw/net/trace-events | 10 + hw/sd/Makefile.objs | 1 + hw/sd/trace-events | 7 + 29 files changed, 3532 insertions(+) create mode 100644 include/hw/arm/allwinner-h3.h create mode 100644 include/hw/misc/allwinner-h3-clk.h create mode 100644 include/hw/misc/allwinner-h3-cpucfg.h create mode 100644 include/hw/misc/allwinner-h3-sid.h create mode 100644 include/hw/misc/allwinner-h3-syscon.h create mode 100644 include/hw/net/allwinner-h3-emac.h create mode 100644 include/hw/sd/allwinner-h3-sdhost.h create mode 100644 hw/arm/allwinner-h3.c create mode 100644 hw/arm/orangepi.c create mode 100644 hw/misc/allwinner-h3-clk.c create mode 100644 hw/misc/allwinner-h3-cpucfg.c create mode 100644 hw/misc/allwinner-h3-sid.c create mode 100644 hw/misc/allwinner-h3-syscon.c create mode 100644 hw/net/allwinner-h3-emac.c create mode 100644 hw/sd/allwinner-h3-sdhost.c -- 2.17.1 From MAILER-DAEMON Mon Dec 16 18:36:12 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1igzuO-0006pQ-Gg for mharc-qemu-arm@gnu.org; Mon, 16 Dec 2019 18:36:12 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:50355) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1igzuK-0006hw-65 for qemu-arm@nongnu.org; Mon, 16 Dec 2019 18:36:09 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1igzuI-0002rX-3L for qemu-arm@nongnu.org; Mon, 16 Dec 2019 18:36:08 -0500 Received: from mail-wm1-x331.google.com ([2a00:1450:4864:20::331]:40519) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1igzuD-0002fA-TJ; Mon, 16 Dec 2019 18:36:02 -0500 Received: by mail-wm1-x331.google.com with SMTP id t14so1089609wmi.5; Mon, 16 Dec 2019 15:36:01 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; 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<20191216233519.29030-1-nieklinnenbank@gmail.com> References: <20191216233519.29030-1-nieklinnenbank@gmail.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::331 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 16 Dec 2019 23:36:11 -0000 The Allwinner H3 System on Chip has an System Control module that provides system wide generic controls and device information. This commit adds support for the Allwinner H3 System Control module. Signed-off-by: Niek Linnenbank --- include/hw/arm/allwinner-h3.h | 2 + include/hw/misc/allwinner-h3-syscon.h | 42 ++++++++ hw/arm/allwinner-h3.c | 7 ++ hw/misc/allwinner-h3-syscon.c | 146 ++++++++++++++++++++++++++ hw/misc/Makefile.objs | 1 + 5 files changed, 198 insertions(+) create mode 100644 include/hw/misc/allwinner-h3-syscon.h create mode 100644 hw/misc/allwinner-h3-syscon.c diff --git a/include/hw/arm/allwinner-h3.h b/include/hw/arm/allwinner-h3.h index 47d6f82cc4..bead6d4f85 100644 --- a/include/hw/arm/allwinner-h3.h +++ b/include/hw/arm/allwinner-h3.h @@ -27,6 +27,7 @@ #include "hw/timer/allwinner-a10-pit.h" #include "hw/intc/arm_gic.h" #include "hw/misc/allwinner-h3-clk.h" +#include "hw/misc/allwinner-h3-syscon.h" #include "target/arm/cpu.h" enum { @@ -73,6 +74,7 @@ typedef struct AwH3State { const hwaddr *memmap; AwA10PITState timer; AwH3ClockState ccu; + AwH3SysconState syscon; GICState gic; MemoryRegion sram_a1; MemoryRegion sram_a2; diff --git a/include/hw/misc/allwinner-h3-syscon.h b/include/hw/misc/allwinner-h3-syscon.h new file mode 100644 index 0000000000..830e1a5061 --- /dev/null +++ b/include/hw/misc/allwinner-h3-syscon.h @@ -0,0 +1,42 @@ +/* + * Allwinner H3 System Control emulation + * + * Copyright (C) 2019 Niek Linnenbank + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#ifndef HW_MISC_ALLWINNER_H3_SYSCON_H +#define HW_MISC_ALLWINNER_H3_SYSCON_H + +#include "hw/sysbus.h" + +#define AW_H3_SYSCON_REGS_MAX_ADDR (0x30) +#define AW_H3_SYSCON_REGS_NUM ((AW_H3_SYSCON_REGS_MAX_ADDR / \ + sizeof(uint32_t)) + 1) + +#define TYPE_AW_H3_SYSCON "allwinner-h3-syscon" +#define AW_H3_SYSCON(obj) OBJECT_CHECK(AwH3SysconState, (obj), \ + TYPE_AW_H3_SYSCON) + +typedef struct AwH3SysconState { + /*< private >*/ + SysBusDevice parent_obj; + /*< public >*/ + + MemoryRegion iomem; + uint32_t regs[AW_H3_SYSCON_REGS_NUM]; +} AwH3SysconState; + +#endif diff --git a/hw/arm/allwinner-h3.c b/hw/arm/allwinner-h3.c index f0ea088852..8482d616e7 100644 --- a/hw/arm/allwinner-h3.c +++ b/hw/arm/allwinner-h3.c @@ -190,6 +190,9 @@ static void aw_h3_init(Object *obj) sysbus_init_child_obj(obj, "ccu", &s->ccu, sizeof(s->ccu), TYPE_AW_H3_CLK); + + sysbus_init_child_obj(obj, "syscon", &s->syscon, sizeof(s->syscon), + TYPE_AW_H3_SYSCON); } static void aw_h3_realize(DeviceState *dev, Error **errp) @@ -318,6 +321,10 @@ static void aw_h3_realize(DeviceState *dev, Error **errp) qdev_init_nofail(DEVICE(&s->ccu)); sysbus_mmio_map(SYS_BUS_DEVICE(&s->ccu), 0, s->memmap[AW_H3_CCU]); + /* System Control */ + qdev_init_nofail(DEVICE(&s->syscon)); + sysbus_mmio_map(SYS_BUS_DEVICE(&s->syscon), 0, s->memmap[AW_H3_SYSCON]); + /* Universal Serial Bus */ sysbus_create_simple(TYPE_AW_H3_EHCI, s->memmap[AW_H3_EHCI0], qdev_get_gpio_in(DEVICE(&s->gic), diff --git a/hw/misc/allwinner-h3-syscon.c b/hw/misc/allwinner-h3-syscon.c new file mode 100644 index 0000000000..9c5d42dd49 --- /dev/null +++ b/hw/misc/allwinner-h3-syscon.c @@ -0,0 +1,146 @@ +/* + * Allwinner H3 System Control emulation + * + * Copyright (C) 2019 Niek Linnenbank + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#include "qemu/osdep.h" +#include "qemu/units.h" +#include "hw/sysbus.h" +#include "migration/vmstate.h" +#include "qemu/log.h" +#include "qemu/module.h" +#include "hw/misc/allwinner-h3-syscon.h" + +/* SYSCON register offsets */ +enum { + REG_VER = 0x24, /* Version */ + REG_EMAC_PHY_CLK = 0x30, /* EMAC PHY Clock */ +}; + +#define REG_INDEX(offset) (offset / sizeof(uint32_t)) + +/* SYSCON register reset values */ +enum { + REG_VER_RST = 0x0, + REG_EMAC_PHY_CLK_RST = 0x58000, +}; + +static uint64_t allwinner_h3_syscon_read(void *opaque, hwaddr offset, + unsigned size) +{ + const AwH3SysconState *s = (AwH3SysconState *)opaque; + const uint32_t idx = REG_INDEX(offset); + + if (idx >= AW_H3_SYSCON_REGS_NUM) { + qemu_log_mask(LOG_GUEST_ERROR, "%s: bad read offset 0x%04x\n", + __func__, (uint32_t)offset); + return 0; + } + + return s->regs[idx]; +} + +static void allwinner_h3_syscon_write(void *opaque, hwaddr offset, + uint64_t val, unsigned size) +{ + AwH3SysconState *s = (AwH3SysconState *)opaque; + const uint32_t idx = REG_INDEX(offset); + + if (idx >= AW_H3_SYSCON_REGS_NUM) { + qemu_log_mask(LOG_GUEST_ERROR, "%s: bad write offset 0x%04x\n", + __func__, (uint32_t)offset); + return; + } + + switch (offset) { + case REG_VER: /* Version */ + break; + default: + s->regs[idx] = (uint32_t) val; + break; + } +} + +static const MemoryRegionOps allwinner_h3_syscon_ops = { + .read = allwinner_h3_syscon_read, + .write = allwinner_h3_syscon_write, + .endianness = DEVICE_NATIVE_ENDIAN, + .valid = { + .min_access_size = 4, + .max_access_size = 4, + .unaligned = false + }, + .impl.min_access_size = 4, +}; + +static void allwinner_h3_syscon_reset(DeviceState *dev) +{ + AwH3SysconState *s = AW_H3_SYSCON(dev); + + /* Set default values for registers */ + s->regs[REG_INDEX(REG_VER)] = REG_VER_RST; + s->regs[REG_INDEX(REG_EMAC_PHY_CLK)] = REG_EMAC_PHY_CLK_RST; +} + +static void allwinner_h3_syscon_realize(DeviceState *dev, Error **errp) +{ +} + +static void allwinner_h3_syscon_init(Object *obj) +{ + SysBusDevice *sbd = SYS_BUS_DEVICE(obj); + AwH3SysconState *s = AW_H3_SYSCON(obj); + + /* Memory mapping */ + memory_region_init_io(&s->iomem, OBJECT(s), &allwinner_h3_syscon_ops, s, + TYPE_AW_H3_SYSCON, 4 * KiB); + sysbus_init_mmio(sbd, &s->iomem); +} + +static const VMStateDescription allwinner_h3_syscon_vmstate = { + .name = "allwinner-h3-syscon", + .version_id = 1, + .minimum_version_id = 1, + .fields = (VMStateField[]) { + VMSTATE_UINT32_ARRAY(regs, AwH3SysconState, AW_H3_SYSCON_REGS_NUM), + VMSTATE_END_OF_LIST() + } +}; + +static void allwinner_h3_syscon_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + + dc->reset = allwinner_h3_syscon_reset; + dc->realize = allwinner_h3_syscon_realize; + dc->vmsd = &allwinner_h3_syscon_vmstate; +} + +static const TypeInfo allwinner_h3_syscon_info = { + .name = TYPE_AW_H3_SYSCON, + .parent = TYPE_SYS_BUS_DEVICE, + .instance_init = allwinner_h3_syscon_init, + .instance_size = sizeof(AwH3SysconState), + .class_init = allwinner_h3_syscon_class_init, +}; + +static void allwinner_h3_syscon_register(void) +{ + type_register_static(&allwinner_h3_syscon_info); +} + +type_init(allwinner_h3_syscon_register) diff --git a/hw/misc/Makefile.objs b/hw/misc/Makefile.objs index 200ed44ce1..b234aefba5 100644 --- a/hw/misc/Makefile.objs +++ b/hw/misc/Makefile.objs @@ -29,6 +29,7 @@ common-obj-$(CONFIG_MACIO) += macio/ common-obj-$(CONFIG_IVSHMEM_DEVICE) += ivshmem.o common-obj-$(CONFIG_ALLWINNER_H3) += allwinner-h3-clk.o +common-obj-$(CONFIG_ALLWINNER_H3) += allwinner-h3-syscon.o common-obj-$(CONFIG_REALVIEW) += arm_sysctl.o common-obj-$(CONFIG_NSERIES) += cbus.o common-obj-$(CONFIG_ECCMEMCTL) += eccmemctl.o -- 2.17.1 From MAILER-DAEMON Mon Dec 16 18:36:13 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1igzuP-0006rX-Mr for mharc-qemu-arm@gnu.org; Mon, 16 Dec 2019 18:36:13 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:50347) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1igzuJ-0006hI-NG for qemu-arm@nongnu.org; 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Mon, 16 Dec 2019 15:35:58 -0800 (PST) From: Niek Linnenbank To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, peter.maydell@linaro.org, philmd@redhat.com, Niek Linnenbank Subject: [PATCH v2 03/10] arm: allwinner-h3: add Clock Control Unit Date: Tue, 17 Dec 2019 00:35:12 +0100 Message-Id: <20191216233519.29030-4-nieklinnenbank@gmail.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20191216233519.29030-1-nieklinnenbank@gmail.com> References: <20191216233519.29030-1-nieklinnenbank@gmail.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::442 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 16 Dec 2019 23:36:11 -0000 The Clock Control Unit is responsible for clock signal generation, configuration and distribution in the Allwinner H3 System on Chip. This commit adds support for the Clock Control Unit which emulates a simple read/write register interface. Signed-off-by: Niek Linnenbank --- include/hw/arm/allwinner-h3.h | 2 + include/hw/misc/allwinner-h3-clk.h | 40 +++++ hw/arm/allwinner-h3.c | 7 + hw/misc/allwinner-h3-clk.c | 238 +++++++++++++++++++++++++++++ hw/misc/Makefile.objs | 1 + 5 files changed, 288 insertions(+) create mode 100644 include/hw/misc/allwinner-h3-clk.h create mode 100644 hw/misc/allwinner-h3-clk.c diff --git a/include/hw/arm/allwinner-h3.h b/include/hw/arm/allwinner-h3.h index e50caeffaa..47d6f82cc4 100644 --- a/include/hw/arm/allwinner-h3.h +++ b/include/hw/arm/allwinner-h3.h @@ -26,6 +26,7 @@ #include "hw/arm/boot.h" #include "hw/timer/allwinner-a10-pit.h" #include "hw/intc/arm_gic.h" +#include "hw/misc/allwinner-h3-clk.h" #include "target/arm/cpu.h" enum { @@ -71,6 +72,7 @@ typedef struct AwH3State { ARMCPU cpus[AW_H3_NUM_CPUS]; const hwaddr *memmap; AwA10PITState timer; + AwH3ClockState ccu; GICState gic; MemoryRegion sram_a1; MemoryRegion sram_a2; diff --git a/include/hw/misc/allwinner-h3-clk.h b/include/hw/misc/allwinner-h3-clk.h new file mode 100644 index 0000000000..ce058a900b --- /dev/null +++ b/include/hw/misc/allwinner-h3-clk.h @@ -0,0 +1,40 @@ +/* + * Allwinner H3 Clock Control Unit emulation + * + * Copyright (C) 2019 Niek Linnenbank + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#ifndef HW_MISC_ALLWINNER_H3_CLK_H +#define HW_MISC_ALLWINNER_H3_CLK_H + +#include "hw/sysbus.h" + +#define AW_H3_CLK_REGS_MAX_ADDR (0x304) +#define AW_H3_CLK_REGS_NUM (AW_H3_CLK_REGS_MAX_ADDR / sizeof(uint32_t)) + +#define TYPE_AW_H3_CLK "allwinner-h3-clk" +#define AW_H3_CLK(obj) OBJECT_CHECK(AwH3ClockState, (obj), TYPE_AW_H3_CLK) + +typedef struct AwH3ClockState { + /*< private >*/ + SysBusDevice parent_obj; + /*< public >*/ + + MemoryRegion iomem; + uint32_t regs[AW_H3_CLK_REGS_NUM]; +} AwH3ClockState; + +#endif diff --git a/hw/arm/allwinner-h3.c b/hw/arm/allwinner-h3.c index 1a47de56f5..0da09188d1 100644 --- a/hw/arm/allwinner-h3.c +++ b/hw/arm/allwinner-h3.c @@ -186,6 +186,9 @@ static void aw_h3_init(Object *obj) sysbus_init_child_obj(obj, "timer", &s->timer, sizeof(s->timer), TYPE_AW_A10_PIT); + + sysbus_init_child_obj(obj, "ccu", &s->ccu, sizeof(s->ccu), + TYPE_AW_H3_CLK); } static void aw_h3_realize(DeviceState *dev, Error **errp) @@ -310,6 +313,10 @@ static void aw_h3_realize(DeviceState *dev, Error **errp) memory_region_add_subregion(get_system_memory(), s->memmap[AW_H3_SRAM_C], &s->sram_c); + /* Clock Control Unit */ + qdev_init_nofail(DEVICE(&s->ccu)); + sysbus_mmio_map(SYS_BUS_DEVICE(&s->ccu), 0, s->memmap[AW_H3_CCU]); + /* UART0 */ serial_mm_init(get_system_memory(), s->memmap[AW_H3_UART0], 2, qdev_get_gpio_in(DEVICE(&s->gic), AW_H3_GIC_SPI_UART0), diff --git a/hw/misc/allwinner-h3-clk.c b/hw/misc/allwinner-h3-clk.c new file mode 100644 index 0000000000..4758cd4d7e --- /dev/null +++ b/hw/misc/allwinner-h3-clk.c @@ -0,0 +1,238 @@ +/* + * Allwinner H3 Clock Control Unit emulation + * + * Copyright (C) 2019 Niek Linnenbank + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#include "qemu/osdep.h" +#include "qemu/units.h" +#include "hw/sysbus.h" +#include "migration/vmstate.h" +#include "qemu/log.h" +#include "qemu/module.h" +#include "hw/misc/allwinner-h3-clk.h" + +/* CCU register offsets */ +enum { + REG_PLL_CPUX = 0x0000, /* PLL CPUX Control */ + REG_PLL_AUDIO = 0x0008, /* PLL Audio Control */ + REG_PLL_VIDEO = 0x0010, /* PLL Video Control */ + REG_PLL_VE = 0x0018, /* PLL VE Control */ + REG_PLL_DDR = 0x0020, /* PLL DDR Control */ + REG_PLL_PERIPH0 = 0x0028, /* PLL Peripherals 0 Control */ + REG_PLL_GPU = 0x0038, /* PLL GPU Control */ + REG_PLL_PERIPH1 = 0x0044, /* PLL Peripherals 1 Control */ + REG_PLL_DE = 0x0048, /* PLL Display Engine Control */ + REG_CPUX_AXI = 0x0050, /* CPUX/AXI Configuration */ + REG_APB1 = 0x0054, /* ARM Peripheral Bus 1 Config */ + REG_APB2 = 0x0058, /* ARM Peripheral Bus 2 Config */ + REG_MBUS = 0x00FC, /* MBUS Reset */ + REG_PLL_TIME0 = 0x0200, /* PLL Stable Time 0 */ + REG_PLL_TIME1 = 0x0204, /* PLL Stable Time 1 */ + REG_PLL_CPUX_BIAS = 0x0220, /* PLL CPUX Bias */ + REG_PLL_AUDIO_BIAS = 0x0224, /* PLL Audio Bias */ + REG_PLL_VIDEO_BIAS = 0x0228, /* PLL Video Bias */ + REG_PLL_VE_BIAS = 0x022C, /* PLL VE Bias */ + REG_PLL_DDR_BIAS = 0x0230, /* PLL DDR Bias */ + REG_PLL_PERIPH0_BIAS = 0x0234, /* PLL Peripherals 0 Bias */ + REG_PLL_GPU_BIAS = 0x023C, /* PLL GPU Bias */ + REG_PLL_PERIPH1_BIAS = 0x0244, /* PLL Peripherals 1 Bias */ + REG_PLL_DE_BIAS = 0x0248, /* PLL Display Engine Bias */ + REG_PLL_CPUX_TUNING = 0x0250, /* PLL CPUX Tuning */ + REG_PLL_DDR_TUNING = 0x0260, /* PLL DDR Tuning */ +}; + +#define REG_INDEX(offset) (offset / sizeof(uint32_t)) + +/* CCU register flags */ +enum { + REG_PLL_ENABLE = (1 << 31), + REG_PLL_LOCK = (1 << 28), +}; + +/* CCU register reset values */ +enum { + REG_PLL_CPUX_RST = 0x00001000, + REG_PLL_AUDIO_RST = 0x00035514, + REG_PLL_VIDEO_RST = 0x03006207, + REG_PLL_VE_RST = 0x03006207, + REG_PLL_DDR_RST = 0x00001000, + REG_PLL_PERIPH0_RST = 0x00041811, + REG_PLL_GPU_RST = 0x03006207, + REG_PLL_PERIPH1_RST = 0x00041811, + REG_PLL_DE_RST = 0x03006207, + REG_CPUX_AXI_RST = 0x00010000, + REG_APB1_RST = 0x00001010, + REG_APB2_RST = 0x01000000, + REG_MBUS_RST = 0x80000000, + REG_PLL_TIME0_RST = 0x000000FF, + REG_PLL_TIME1_RST = 0x000000FF, + REG_PLL_CPUX_BIAS_RST = 0x08100200, + REG_PLL_AUDIO_BIAS_RST = 0x10100000, + REG_PLL_VIDEO_BIAS_RST = 0x10100000, + REG_PLL_VE_BIAS_RST = 0x10100000, + REG_PLL_DDR_BIAS_RST = 0x81104000, + REG_PLL_PERIPH0_BIAS_RST = 0x10100010, + REG_PLL_GPU_BIAS_RST = 0x10100000, + REG_PLL_PERIPH1_BIAS_RST = 0x10100010, + REG_PLL_DE_BIAS_RST = 0x10100000, + REG_PLL_CPUX_TUNING_RST = 0x0A101000, + REG_PLL_DDR_TUNING_RST = 0x14880000, +}; + +static uint64_t allwinner_h3_clk_read(void *opaque, hwaddr offset, + unsigned size) +{ + const AwH3ClockState *s = (AwH3ClockState *)opaque; + const uint32_t idx = REG_INDEX(offset); + + if (idx >= AW_H3_CLK_REGS_NUM) { + qemu_log_mask(LOG_GUEST_ERROR, "%s: bad read offset 0x%04x\n", + __func__, (uint32_t)offset); + return 0; + } + + return s->regs[idx]; +} + +static void allwinner_h3_clk_write(void *opaque, hwaddr offset, + uint64_t val, unsigned size) +{ + AwH3ClockState *s = (AwH3ClockState *)opaque; + const uint32_t idx = REG_INDEX(offset); + + if (idx >= AW_H3_CLK_REGS_NUM) { + qemu_log_mask(LOG_GUEST_ERROR, "%s: bad write offset 0x%04x\n", + __func__, (uint32_t)offset); + return; + } + + switch (offset) { + case REG_PLL_CPUX: /* PLL CPUX Control */ + case REG_PLL_AUDIO: /* PLL Audio Control */ + case REG_PLL_VIDEO: /* PLL Video Control */ + case REG_PLL_VE: /* PLL VE Control */ + case REG_PLL_DDR: /* PLL DDR Control */ + case REG_PLL_PERIPH0: /* PLL Peripherals 0 Control */ + case REG_PLL_GPU: /* PLL GPU Control */ + case REG_PLL_PERIPH1: /* PLL Peripherals 1 Control */ + case REG_PLL_DE: /* PLL Display Engine Control */ + if (val & REG_PLL_ENABLE) { + val |= REG_PLL_LOCK; + } + break; + default: + qemu_log_mask(LOG_UNIMP, "%s: unimplemented write offset 0x%04x\n", + __func__, (uint32_t)offset); + break; + } + + s->regs[idx] = (uint32_t) val; +} + +static const MemoryRegionOps allwinner_h3_clk_ops = { + .read = allwinner_h3_clk_read, + .write = allwinner_h3_clk_write, + .endianness = DEVICE_NATIVE_ENDIAN, + .valid = { + .min_access_size = 4, + .max_access_size = 4, + .unaligned = false + }, + .impl.min_access_size = 4, +}; + +static void allwinner_h3_clk_reset(DeviceState *dev) +{ + AwH3ClockState *s = AW_H3_CLK(dev); + + /* Set default values for registers */ + s->regs[REG_INDEX(REG_PLL_CPUX)] = REG_PLL_CPUX_RST; + s->regs[REG_INDEX(REG_PLL_AUDIO)] = REG_PLL_AUDIO_RST; + s->regs[REG_INDEX(REG_PLL_VIDEO)] = REG_PLL_VIDEO_RST; + s->regs[REG_INDEX(REG_PLL_VE)] = REG_PLL_VE_RST; + s->regs[REG_INDEX(REG_PLL_DDR)] = REG_PLL_DDR_RST; + s->regs[REG_INDEX(REG_PLL_PERIPH0)] = REG_PLL_PERIPH0_RST; + s->regs[REG_INDEX(REG_PLL_GPU)] = REG_PLL_GPU_RST; + s->regs[REG_INDEX(REG_PLL_PERIPH1)] = REG_PLL_PERIPH1_RST; + s->regs[REG_INDEX(REG_PLL_DE)] = REG_PLL_DE_RST; + s->regs[REG_INDEX(REG_CPUX_AXI)] = REG_CPUX_AXI_RST; + s->regs[REG_INDEX(REG_APB1)] = REG_APB1_RST; + s->regs[REG_INDEX(REG_APB2)] = REG_APB2_RST; + s->regs[REG_INDEX(REG_MBUS)] = REG_MBUS_RST; + s->regs[REG_INDEX(REG_PLL_TIME0)] = REG_PLL_TIME0_RST; + s->regs[REG_INDEX(REG_PLL_TIME1)] = REG_PLL_TIME1_RST; + s->regs[REG_INDEX(REG_PLL_CPUX_BIAS)] = REG_PLL_CPUX_BIAS_RST; + s->regs[REG_INDEX(REG_PLL_AUDIO_BIAS)] = REG_PLL_AUDIO_BIAS_RST; + s->regs[REG_INDEX(REG_PLL_VIDEO_BIAS)] = REG_PLL_VIDEO_BIAS_RST; + s->regs[REG_INDEX(REG_PLL_VE_BIAS)] = REG_PLL_VE_BIAS_RST; + s->regs[REG_INDEX(REG_PLL_DDR_BIAS)] = REG_PLL_DDR_BIAS_RST; + s->regs[REG_INDEX(REG_PLL_PERIPH0_BIAS)] = REG_PLL_PERIPH0_BIAS_RST; + s->regs[REG_INDEX(REG_PLL_GPU_BIAS)] = REG_PLL_GPU_BIAS_RST; + s->regs[REG_INDEX(REG_PLL_PERIPH1_BIAS)] = REG_PLL_PERIPH1_BIAS_RST; + s->regs[REG_INDEX(REG_PLL_DE_BIAS)] = REG_PLL_DE_BIAS_RST; + s->regs[REG_INDEX(REG_PLL_CPUX_TUNING)] = REG_PLL_CPUX_TUNING_RST; + s->regs[REG_INDEX(REG_PLL_DDR_TUNING)] = REG_PLL_DDR_TUNING_RST; +} + +static void allwinner_h3_clk_realize(DeviceState *dev, Error **errp) +{ +} + +static void allwinner_h3_clk_init(Object *obj) +{ + SysBusDevice *sbd = SYS_BUS_DEVICE(obj); + AwH3ClockState *s = AW_H3_CLK(obj); + + /* Memory mapping */ + memory_region_init_io(&s->iomem, OBJECT(s), &allwinner_h3_clk_ops, s, + TYPE_AW_H3_CLK, 1 * KiB); + sysbus_init_mmio(sbd, &s->iomem); +} + +static const VMStateDescription allwinner_h3_clk_vmstate = { + .name = "allwinner-h3-clk", + .version_id = 1, + .minimum_version_id = 1, + .fields = (VMStateField[]) { + VMSTATE_UINT32_ARRAY(regs, AwH3ClockState, AW_H3_CLK_REGS_NUM), + VMSTATE_END_OF_LIST() + } +}; + +static void allwinner_h3_clk_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + + dc->reset = allwinner_h3_clk_reset; + dc->realize = allwinner_h3_clk_realize; + dc->vmsd = &allwinner_h3_clk_vmstate; +} + +static const TypeInfo allwinner_h3_clk_info = { + .name = TYPE_AW_H3_CLK, + .parent = TYPE_SYS_BUS_DEVICE, + .instance_init = allwinner_h3_clk_init, + .instance_size = sizeof(AwH3ClockState), + .class_init = allwinner_h3_clk_class_init, +}; + +static void allwinner_h3_clk_register(void) +{ + type_register_static(&allwinner_h3_clk_info); +} + +type_init(allwinner_h3_clk_register) diff --git a/hw/misc/Makefile.objs b/hw/misc/Makefile.objs index ba898a5781..200ed44ce1 100644 --- a/hw/misc/Makefile.objs +++ b/hw/misc/Makefile.objs @@ -28,6 +28,7 @@ common-obj-$(CONFIG_MACIO) += macio/ common-obj-$(CONFIG_IVSHMEM_DEVICE) += ivshmem.o +common-obj-$(CONFIG_ALLWINNER_H3) += allwinner-h3-clk.o common-obj-$(CONFIG_REALVIEW) += arm_sysctl.o common-obj-$(CONFIG_NSERIES) += cbus.o common-obj-$(CONFIG_ECCMEMCTL) += eccmemctl.o -- 2.17.1 From MAILER-DAEMON Mon Dec 16 18:36:15 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1igzuR-0006tm-0Z for mharc-qemu-arm@gnu.org; Mon, 16 Dec 2019 18:36:15 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:50349) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1igzuJ-0006hM-R1 for qemu-arm@nongnu.org; Mon, 16 Dec 2019 18:36:10 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1igzuG-0002np-Li for qemu-arm@nongnu.org; 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X-Received-From: 2a00:1450:4864:20::343 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 16 Dec 2019 23:36:12 -0000 The Allwinner H3 is a System on Chip containing four ARM Cortex A7 processor cores. Features and specifications include DDR2/DDR3 memory, SD/MMC storage cards, 10/100/1000Mbit ethernet, USB 2.0, HDMI and various I/O modules. This commit adds support for the Allwinner H3 System on Chip. Signed-off-by: Niek Linnenbank --- default-configs/arm-softmmu.mak | 1 + include/hw/arm/allwinner-h3.h | 80 +++++++ hw/arm/allwinner-h3.c | 360 ++++++++++++++++++++++++++++++++ MAINTAINERS | 7 + hw/arm/Kconfig | 8 + hw/arm/Makefile.objs | 1 + 6 files changed, 457 insertions(+) create mode 100644 include/hw/arm/allwinner-h3.h create mode 100644 hw/arm/allwinner-h3.c diff --git a/default-configs/arm-softmmu.mak b/default-configs/arm-softmmu.mak index 1f2e0e7fde..d75a239c2c 100644 --- a/default-configs/arm-softmmu.mak +++ b/default-configs/arm-softmmu.mak @@ -40,3 +40,4 @@ CONFIG_FSL_IMX25=y CONFIG_FSL_IMX7=y CONFIG_FSL_IMX6UL=y CONFIG_SEMIHOSTING=y +CONFIG_ALLWINNER_H3=y diff --git a/include/hw/arm/allwinner-h3.h b/include/hw/arm/allwinner-h3.h new file mode 100644 index 0000000000..e50caeffaa --- /dev/null +++ b/include/hw/arm/allwinner-h3.h @@ -0,0 +1,80 @@ +/* + * Allwinner H3 System on Chip emulation + * + * Copyright (C) 2019 Niek Linnenbank + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#ifndef HW_ARM_ALLWINNER_H3_H +#define HW_ARM_ALLWINNER_H3_H + +#include "qemu/error-report.h" +#include "qemu/units.h" +#include "hw/char/serial.h" +#include "hw/arm/boot.h" +#include "hw/timer/allwinner-a10-pit.h" +#include "hw/intc/arm_gic.h" +#include "target/arm/cpu.h" + +enum { + AW_H3_SRAM_A1, + AW_H3_SRAM_A2, + AW_H3_SRAM_C, + AW_H3_SYSCON, + AW_H3_SID, + AW_H3_CCU, + AW_H3_PIT, + AW_H3_UART0, + AW_H3_UART1, + AW_H3_UART2, + AW_H3_UART3, + AW_H3_EMAC, + AW_H3_MMC0, + AW_H3_EHCI0, + AW_H3_OHCI0, + AW_H3_EHCI1, + AW_H3_OHCI1, + AW_H3_EHCI2, + AW_H3_OHCI2, + AW_H3_EHCI3, + AW_H3_OHCI3, + AW_H3_GIC_DIST, + AW_H3_GIC_CPU, + AW_H3_GIC_HYP, + AW_H3_GIC_VCPU, + AW_H3_CPUCFG, + AW_H3_SDRAM +}; + +#define AW_H3_NUM_CPUS (4) + +#define TYPE_AW_H3 "allwinner-h3" +#define AW_H3(obj) OBJECT_CHECK(AwH3State, (obj), TYPE_AW_H3) + +typedef struct AwH3State { + /*< private >*/ + DeviceState parent_obj; + /*< public >*/ + + ARMCPU cpus[AW_H3_NUM_CPUS]; + const hwaddr *memmap; + AwA10PITState timer; + GICState gic; + MemoryRegion sram_a1; + MemoryRegion sram_a2; + MemoryRegion sram_c; +} AwH3State; + +#endif diff --git a/hw/arm/allwinner-h3.c b/hw/arm/allwinner-h3.c new file mode 100644 index 0000000000..1a47de56f5 --- /dev/null +++ b/hw/arm/allwinner-h3.c @@ -0,0 +1,360 @@ +/* + * Allwinner H3 System on Chip emulation + * + * Copyright (C) 2019 Niek Linnenbank + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#include "qemu/osdep.h" +#include "exec/address-spaces.h" +#include "qapi/error.h" +#include "qemu/module.h" +#include "qemu/units.h" +#include "cpu.h" +#include "hw/sysbus.h" +#include "hw/arm/allwinner-h3.h" +#include "hw/misc/unimp.h" +#include "sysemu/sysemu.h" + +/* Memory map */ +const hwaddr aw_h3_memmap[] = { + [AW_H3_SRAM_A1] = 0x00000000, + [AW_H3_SRAM_A2] = 0x00044000, + [AW_H3_SRAM_C] = 0x00010000, + [AW_H3_SYSCON] = 0x01c00000, + [AW_H3_SID] = 0x01c14000, + [AW_H3_CCU] = 0x01c20000, + [AW_H3_PIT] = 0x01c20c00, + [AW_H3_UART0] = 0x01c28000, + [AW_H3_UART1] = 0x01c28400, + [AW_H3_UART2] = 0x01c28800, + [AW_H3_UART3] = 0x01c28c00, + [AW_H3_EMAC] = 0x01c30000, + [AW_H3_MMC0] = 0x01c0f000, + [AW_H3_EHCI0] = 0x01c1a000, + [AW_H3_OHCI0] = 0x01c1a400, + [AW_H3_EHCI1] = 0x01c1b000, + [AW_H3_OHCI1] = 0x01c1b400, + [AW_H3_EHCI2] = 0x01c1c000, + [AW_H3_OHCI2] = 0x01c1c400, + [AW_H3_EHCI3] = 0x01c1d000, + [AW_H3_OHCI3] = 0x01c1d400, + [AW_H3_GIC_DIST] = 0x01c81000, + [AW_H3_GIC_CPU] = 0x01c82000, + [AW_H3_GIC_HYP] = 0x01c84000, + [AW_H3_GIC_VCPU] = 0x01c86000, + [AW_H3_CPUCFG] = 0x01f01c00, + [AW_H3_SDRAM] = 0x40000000 +}; + +/* List of unimplemented devices */ +struct AwH3Unimplemented { + const char *device_name; + hwaddr base; + hwaddr size; +} unimplemented[] = { + { "d-engine", 0x01000000, 4 * MiB }, + { "d-inter", 0x01400000, 128 * KiB }, + { "dma", 0x01c02000, 4 * KiB }, + { "nfdc", 0x01c03000, 4 * KiB }, + { "ts", 0x01c06000, 4 * KiB }, + { "keymem", 0x01c0b000, 4 * KiB }, + { "lcd0", 0x01c0c000, 4 * KiB }, + { "lcd1", 0x01c0d000, 4 * KiB }, + { "ve", 0x01c0e000, 4 * KiB }, + { "mmc1", 0x01c10000, 4 * KiB }, + { "mmc2", 0x01c11000, 4 * KiB }, + { "crypto", 0x01c15000, 4 * KiB }, + { "msgbox", 0x01c17000, 4 * KiB }, + { "spinlock", 0x01c18000, 4 * KiB }, + { "usb0-otg", 0x01c19000, 4 * KiB }, + { "usb0-phy", 0x01c1a000, 4 * KiB }, + { "usb1-phy", 0x01c1b000, 4 * KiB }, + { "usb2-phy", 0x01c1c000, 4 * KiB }, + { "usb3-phy", 0x01c1d000, 4 * KiB }, + { "smc", 0x01c1e000, 4 * KiB }, + { "pio", 0x01c20800, 1 * KiB }, + { "owa", 0x01c21000, 1 * KiB }, + { "pwm", 0x01c21400, 1 * KiB }, + { "keyadc", 0x01c21800, 1 * KiB }, + { "pcm0", 0x01c22000, 1 * KiB }, + { "pcm1", 0x01c22400, 1 * KiB }, + { "pcm2", 0x01c22800, 1 * KiB }, + { "audio", 0x01c22c00, 2 * KiB }, + { "smta", 0x01c23400, 1 * KiB }, + { "ths", 0x01c25000, 1 * KiB }, + { "uart0", 0x01c28000, 1 * KiB }, + { "uart1", 0x01c28400, 1 * KiB }, + { "uart2", 0x01c28800, 1 * KiB }, + { "uart3", 0x01c28c00, 1 * KiB }, + { "twi0", 0x01c2ac00, 1 * KiB }, + { "twi1", 0x01c2b000, 1 * KiB }, + { "twi2", 0x01c2b400, 1 * KiB }, + { "scr", 0x01c2c400, 1 * KiB }, + { "gpu", 0x01c40000, 64 * KiB }, + { "hstmr", 0x01c60000, 4 * KiB }, + { "dramcom", 0x01c62000, 4 * KiB }, + { "dramctl0", 0x01c63000, 4 * KiB }, + { "dramphy0", 0x01c65000, 4 * KiB }, + { "spi0", 0x01c68000, 4 * KiB }, + { "spi1", 0x01c69000, 4 * KiB }, + { "csi", 0x01cb0000, 320 * KiB }, + { "tve", 0x01e00000, 64 * KiB }, + { "hdmi", 0x01ee0000, 128 * KiB }, + { "rtc", 0x01f00000, 1 * KiB }, + { "r_timer", 0x01f00800, 1 * KiB }, + { "r_intc", 0x01f00c00, 1 * KiB }, + { "r_wdog", 0x01f01000, 1 * KiB }, + { "r_prcm", 0x01f01400, 1 * KiB }, + { "r_twd", 0x01f01800, 1 * KiB }, + { "r_cpucfg", 0x01f01c00, 1 * KiB }, + { "r_cir-rx", 0x01f02000, 1 * KiB }, + { "r_twi", 0x01f02400, 1 * KiB }, + { "r_uart", 0x01f02800, 1 * KiB }, + { "r_pio", 0x01f02c00, 1 * KiB }, + { "r_pwm", 0x01f03800, 1 * KiB }, + { "core-dbg", 0x3f500000, 128 * KiB }, + { "tsgen-ro", 0x3f506000, 4 * KiB }, + { "tsgen-ctl", 0x3f507000, 4 * KiB }, + { "ddr-mem", 0x40000000, 2 * GiB }, + { "n-brom", 0xffff0000, 32 * KiB }, + { "s-brom", 0xffff0000, 64 * KiB } +}; + +/* Per Processor Interrupts */ +enum { + AW_H3_GIC_PPI_MAINT = 9, + AW_H3_GIC_PPI_HYPTIMER = 10, + AW_H3_GIC_PPI_VIRTTIMER = 11, + AW_H3_GIC_PPI_SECTIMER = 13, + AW_H3_GIC_PPI_PHYSTIMER = 14 +}; + +/* Shared Processor Interrupts */ +enum { + AW_H3_GIC_SPI_UART0 = 0, + AW_H3_GIC_SPI_UART1 = 1, + AW_H3_GIC_SPI_UART2 = 2, + AW_H3_GIC_SPI_UART3 = 3, + AW_H3_GIC_SPI_TIMER0 = 18, + AW_H3_GIC_SPI_TIMER1 = 19, + AW_H3_GIC_SPI_MMC0 = 60, + AW_H3_GIC_SPI_MMC1 = 61, + AW_H3_GIC_SPI_MMC2 = 62, + AW_H3_GIC_SPI_EHCI0 = 72, + AW_H3_GIC_SPI_OHCI0 = 73, + AW_H3_GIC_SPI_EHCI1 = 74, + AW_H3_GIC_SPI_OHCI1 = 75, + AW_H3_GIC_SPI_EHCI2 = 76, + AW_H3_GIC_SPI_OHCI2 = 77, + AW_H3_GIC_SPI_EHCI3 = 78, + AW_H3_GIC_SPI_OHCI3 = 79, + AW_H3_GIC_SPI_EMAC = 82 +}; + +/* Allwinner H3 constants */ +enum { + AW_H3_GIC_NUM_SPI = 128 +}; + +static void aw_h3_init(Object *obj) +{ + AwH3State *s = AW_H3(obj); + + s->memmap = aw_h3_memmap; + + for (int i = 0; i < AW_H3_NUM_CPUS; i++) { + object_initialize_child(obj, "cpu[*]", &s->cpus[i], sizeof(s->cpus[i]), + ARM_CPU_TYPE_NAME("cortex-a7"), + &error_abort, NULL); + } + + sysbus_init_child_obj(obj, "gic", &s->gic, sizeof(s->gic), + TYPE_ARM_GIC); + + sysbus_init_child_obj(obj, "timer", &s->timer, sizeof(s->timer), + TYPE_AW_A10_PIT); +} + +static void aw_h3_realize(DeviceState *dev, Error **errp) +{ + AwH3State *s = AW_H3(dev); + unsigned i = 0; + + /* CPUs */ + for (i = 0; i < AW_H3_NUM_CPUS; i++) { + + /* Provide Power State Coordination Interface */ + object_property_set_int(OBJECT(&s->cpus[i]), QEMU_PSCI_CONDUIT_HVC, + "psci-conduit", &error_abort); + if (error_abort != NULL) { + error_propagate(errp, error_abort); + return; + } + + /* Disable secondary CPUs */ + object_property_set_bool(OBJECT(&s->cpus[i]), i > 0, + "start-powered-off", &error_abort); + if (error_abort != NULL) { + error_propagate(errp, error_abort); + return; + } + + /* All exception levels required */ + object_property_set_bool(OBJECT(&s->cpus[i]), + true, "has_el3", &error_abort); + if (error_abort != NULL) { + error_propagate(errp, error_abort); + return; + } + + object_property_set_bool(OBJECT(&s->cpus[i]), + true, "has_el2", &error_abort); + if (error_abort != NULL) { + error_propagate(errp, error_abort); + return; + } + + /* Mark realized */ + qdev_init_nofail(DEVICE(&s->cpus[i])); + } + + /* Generic Interrupt Controller */ + qdev_prop_set_uint32(DEVICE(&s->gic), "num-irq", AW_H3_GIC_NUM_SPI + + GIC_INTERNAL); + qdev_prop_set_uint32(DEVICE(&s->gic), "revision", 2); + qdev_prop_set_uint32(DEVICE(&s->gic), "num-cpu", AW_H3_NUM_CPUS); + qdev_prop_set_bit(DEVICE(&s->gic), "has-security-extensions", false); + qdev_prop_set_bit(DEVICE(&s->gic), "has-virtualization-extensions", true); + qdev_init_nofail(DEVICE(&s->gic)); + + sysbus_mmio_map(SYS_BUS_DEVICE(&s->gic), 0, s->memmap[AW_H3_GIC_DIST]); + sysbus_mmio_map(SYS_BUS_DEVICE(&s->gic), 1, s->memmap[AW_H3_GIC_CPU]); + sysbus_mmio_map(SYS_BUS_DEVICE(&s->gic), 2, s->memmap[AW_H3_GIC_HYP]); + sysbus_mmio_map(SYS_BUS_DEVICE(&s->gic), 3, s->memmap[AW_H3_GIC_VCPU]); + + /* + * Wire the outputs from each CPU's generic timer and the GICv3 + * maintenance interrupt signal to the appropriate GIC PPI inputs, + * and the GIC's IRQ/FIQ/VIRQ/VFIQ interrupt outputs to the CPU's inputs. + */ + for (i = 0; i < AW_H3_NUM_CPUS; i++) { + DeviceState *cpudev = DEVICE(qemu_get_cpu(i)); + int ppibase = AW_H3_GIC_NUM_SPI + i * GIC_INTERNAL + GIC_NR_SGIS; + int irq; + /* + * Mapping from the output timer irq lines from the CPU to the + * GIC PPI inputs used for this board. + */ + const int timer_irq[] = { + [GTIMER_PHYS] = AW_H3_GIC_PPI_PHYSTIMER, + [GTIMER_VIRT] = AW_H3_GIC_PPI_VIRTTIMER, + [GTIMER_HYP] = AW_H3_GIC_PPI_HYPTIMER, + [GTIMER_SEC] = AW_H3_GIC_PPI_SECTIMER, + }; + + /* Connect CPU timer outputs to GIC PPI inputs */ + for (irq = 0; irq < ARRAY_SIZE(timer_irq); irq++) { + qdev_connect_gpio_out(cpudev, irq, + qdev_get_gpio_in(DEVICE(&s->gic), + ppibase + timer_irq[irq])); + } + + /* Connect GIC outputs to CPU interrupt inputs */ + sysbus_connect_irq(SYS_BUS_DEVICE(&s->gic), i, + qdev_get_gpio_in(cpudev, ARM_CPU_IRQ)); + sysbus_connect_irq(SYS_BUS_DEVICE(&s->gic), i + AW_H3_NUM_CPUS, + qdev_get_gpio_in(cpudev, ARM_CPU_FIQ)); + sysbus_connect_irq(SYS_BUS_DEVICE(&s->gic), i + (2 * AW_H3_NUM_CPUS), + qdev_get_gpio_in(cpudev, ARM_CPU_VIRQ)); + sysbus_connect_irq(SYS_BUS_DEVICE(&s->gic), i + (3 * AW_H3_NUM_CPUS), + qdev_get_gpio_in(cpudev, ARM_CPU_VFIQ)); + + /* GIC maintenance signal */ + sysbus_connect_irq(SYS_BUS_DEVICE(&s->gic), i + (4 * AW_H3_NUM_CPUS), + qdev_get_gpio_in(DEVICE(&s->gic), + ppibase + AW_H3_GIC_PPI_MAINT)); + } + + /* Timer */ + qdev_init_nofail(DEVICE(&s->timer)); + sysbus_mmio_map(SYS_BUS_DEVICE(&s->timer), 0, s->memmap[AW_H3_PIT]); + sysbus_connect_irq(SYS_BUS_DEVICE(&s->timer), 0, + qdev_get_gpio_in(DEVICE(&s->gic), AW_H3_GIC_SPI_TIMER0)); + sysbus_connect_irq(SYS_BUS_DEVICE(&s->timer), 1, + qdev_get_gpio_in(DEVICE(&s->gic), AW_H3_GIC_SPI_TIMER1)); + + /* SRAM */ + memory_region_init_ram(&s->sram_a1, OBJECT(dev), "sram A1", + 64 * KiB, &error_abort); + memory_region_init_ram(&s->sram_a2, OBJECT(dev), "sram A2", + 32 * KiB, &error_abort); + memory_region_init_ram(&s->sram_c, OBJECT(dev), "sram C", + 44 * KiB, &error_abort); + memory_region_add_subregion(get_system_memory(), s->memmap[AW_H3_SRAM_A1], + &s->sram_a1); + memory_region_add_subregion(get_system_memory(), s->memmap[AW_H3_SRAM_A2], + &s->sram_a2); + memory_region_add_subregion(get_system_memory(), s->memmap[AW_H3_SRAM_C], + &s->sram_c); + + /* UART0 */ + serial_mm_init(get_system_memory(), s->memmap[AW_H3_UART0], 2, + qdev_get_gpio_in(DEVICE(&s->gic), AW_H3_GIC_SPI_UART0), + 115200, serial_hd(0), DEVICE_NATIVE_ENDIAN); + /* UART1 */ + serial_mm_init(get_system_memory(), s->memmap[AW_H3_UART1], 2, + qdev_get_gpio_in(DEVICE(&s->gic), AW_H3_GIC_SPI_UART1), + 115200, serial_hd(1), DEVICE_NATIVE_ENDIAN); + /* UART2 */ + serial_mm_init(get_system_memory(), s->memmap[AW_H3_UART2], 2, + qdev_get_gpio_in(DEVICE(&s->gic), AW_H3_GIC_SPI_UART2), + 115200, serial_hd(2), DEVICE_NATIVE_ENDIAN); + /* UART3 */ + serial_mm_init(get_system_memory(), s->memmap[AW_H3_UART3], 2, + qdev_get_gpio_in(DEVICE(&s->gic), AW_H3_GIC_SPI_UART3), + 115200, serial_hd(3), DEVICE_NATIVE_ENDIAN); + + /* Unimplemented devices */ + for (int i = 0; i < ARRAY_SIZE(unimplemented); i++) { + create_unimplemented_device(unimplemented[i].device_name, + unimplemented[i].base, + unimplemented[i].size); + } +} + +static void aw_h3_class_init(ObjectClass *oc, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(oc); + + dc->realize = aw_h3_realize; + /* Reason: uses serial_hds and nd_table */ + dc->user_creatable = false; +} + +static const TypeInfo aw_h3_type_info = { + .name = TYPE_AW_H3, + .parent = TYPE_DEVICE, + .instance_size = sizeof(AwH3State), + .instance_init = aw_h3_init, + .class_init = aw_h3_class_init, +}; + +static void aw_h3_register_types(void) +{ + type_register_static(&aw_h3_type_info); +} + +type_init(aw_h3_register_types) diff --git a/MAINTAINERS b/MAINTAINERS index 740401bcbb..aae1a049b4 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -480,6 +480,13 @@ F: hw/*/allwinner* F: include/hw/*/allwinner* F: hw/arm/cubieboard.c +Allwinner-h3 +M: Niek Linnenbank +L: qemu-arm@nongnu.org +S: Maintained +F: hw/*/allwinner-h3* +F: include/hw/*/allwinner-h3* + ARM PrimeCell and CMSDK devices M: Peter Maydell L: qemu-arm@nongnu.org diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig index c6e7782580..ebf8d2325f 100644 --- a/hw/arm/Kconfig +++ b/hw/arm/Kconfig @@ -291,6 +291,14 @@ config ALLWINNER_A10 select SERIAL select UNIMP +config ALLWINNER_H3 + bool + select ALLWINNER_A10_PIT + select SERIAL + select ARM_TIMER + select ARM_GIC + select UNIMP + config RASPI bool select FRAMEBUFFER diff --git a/hw/arm/Makefile.objs b/hw/arm/Makefile.objs index fe749f65fd..956e496052 100644 --- a/hw/arm/Makefile.objs +++ b/hw/arm/Makefile.objs @@ -34,6 +34,7 @@ obj-$(CONFIG_DIGIC) += digic.o obj-$(CONFIG_OMAP) += omap1.o omap2.o obj-$(CONFIG_STRONGARM) += strongarm.o obj-$(CONFIG_ALLWINNER_A10) += allwinner-a10.o cubieboard.o +obj-$(CONFIG_ALLWINNER_H3) += allwinner-h3.o obj-$(CONFIG_RASPI) += bcm2835_peripherals.o bcm2836.o raspi.o obj-$(CONFIG_STM32F205_SOC) += stm32f205_soc.o obj-$(CONFIG_XLNX_ZYNQMP_ARM) += xlnx-zynqmp.o xlnx-zcu102.o -- 2.17.1 From MAILER-DAEMON Mon Dec 16 18:36:16 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1igzuS-0006vl-6t for mharc-qemu-arm@gnu.org; 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Mon, 16 Dec 2019 15:36:02 -0800 (PST) From: Niek Linnenbank To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, peter.maydell@linaro.org, philmd@redhat.com, Niek Linnenbank Subject: [PATCH v2 08/10] arm: allwinner-h3: add Security Identifier device Date: Tue, 17 Dec 2019 00:35:17 +0100 Message-Id: <20191216233519.29030-9-nieklinnenbank@gmail.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20191216233519.29030-1-nieklinnenbank@gmail.com> References: <20191216233519.29030-1-nieklinnenbank@gmail.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::342 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 16 Dec 2019 23:36:14 -0000 The Security Identifier device in Allwinner H3 System on Chip gives applications a per-board unique identifier. This commit adds support for the Allwinner H3 Security Identifier using a 128-bit UUID value as input. Signed-off-by: Niek Linnenbank --- include/hw/arm/allwinner-h3.h | 2 + include/hw/misc/allwinner-h3-sid.h | 40 +++++++ hw/arm/allwinner-h3.c | 7 ++ hw/arm/orangepi.c | 4 + hw/misc/allwinner-h3-sid.c | 179 +++++++++++++++++++++++++++++ hw/misc/Makefile.objs | 1 + hw/misc/trace-events | 4 + 7 files changed, 237 insertions(+) create mode 100644 include/hw/misc/allwinner-h3-sid.h create mode 100644 hw/misc/allwinner-h3-sid.c diff --git a/include/hw/arm/allwinner-h3.h b/include/hw/arm/allwinner-h3.h index 8128ae6131..c98c1972a6 100644 --- a/include/hw/arm/allwinner-h3.h +++ b/include/hw/arm/allwinner-h3.h @@ -29,6 +29,7 @@ #include "hw/misc/allwinner-h3-clk.h" #include "hw/misc/allwinner-h3-cpucfg.h" #include "hw/misc/allwinner-h3-syscon.h" +#include "hw/misc/allwinner-h3-sid.h" #include "target/arm/cpu.h" enum { @@ -77,6 +78,7 @@ typedef struct AwH3State { AwH3ClockState ccu; AwH3CpuCfgState cpucfg; AwH3SysconState syscon; + AwH3SidState sid; GICState gic; MemoryRegion sram_a1; MemoryRegion sram_a2; diff --git a/include/hw/misc/allwinner-h3-sid.h b/include/hw/misc/allwinner-h3-sid.h new file mode 100644 index 0000000000..79c9a24459 --- /dev/null +++ b/include/hw/misc/allwinner-h3-sid.h @@ -0,0 +1,40 @@ +/* + * Allwinner H3 Security ID emulation + * + * Copyright (C) 2019 Niek Linnenbank + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#ifndef HW_MISC_ALLWINNER_H3_SID_H +#define HW_MISC_ALLWINNER_H3_SID_H + +#include "hw/sysbus.h" +#include "qemu/uuid.h" + +#define TYPE_AW_H3_SID "allwinner-h3-sid" +#define AW_H3_SID(obj) OBJECT_CHECK(AwH3SidState, (obj), TYPE_AW_H3_SID) + +typedef struct AwH3SidState { + /*< private >*/ + SysBusDevice parent_obj; + /*< public >*/ + + MemoryRegion iomem; + uint32_t control; + uint32_t rdkey; + QemuUUID identifier; +} AwH3SidState; + +#endif diff --git a/hw/arm/allwinner-h3.c b/hw/arm/allwinner-h3.c index 1a9748ab2e..ba34f905cd 100644 --- a/hw/arm/allwinner-h3.c +++ b/hw/arm/allwinner-h3.c @@ -196,6 +196,9 @@ static void aw_h3_init(Object *obj) sysbus_init_child_obj(obj, "cpucfg", &s->cpucfg, sizeof(s->cpucfg), TYPE_AW_H3_CPUCFG); + + sysbus_init_child_obj(obj, "sid", &s->sid, sizeof(s->sid), + TYPE_AW_H3_SID); } static void aw_h3_realize(DeviceState *dev, Error **errp) @@ -332,6 +335,10 @@ static void aw_h3_realize(DeviceState *dev, Error **errp) qdev_init_nofail(DEVICE(&s->cpucfg)); sysbus_mmio_map(SYS_BUS_DEVICE(&s->cpucfg), 0, s->memmap[AW_H3_CPUCFG]); + /* Security Identifier */ + qdev_init_nofail(DEVICE(&s->sid)); + sysbus_mmio_map(SYS_BUS_DEVICE(&s->sid), 0, s->memmap[AW_H3_SID]); + /* Universal Serial Bus */ sysbus_create_simple(TYPE_AW_H3_EHCI, s->memmap[AW_H3_EHCI0], qdev_get_gpio_in(DEVICE(&s->gic), diff --git a/hw/arm/orangepi.c b/hw/arm/orangepi.c index 62cefc8c06..b01c4b4f01 100644 --- a/hw/arm/orangepi.c +++ b/hw/arm/orangepi.c @@ -62,6 +62,10 @@ static void orangepi_init(MachineState *machine) exit(1); } + /* Setup SID properties */ + qdev_prop_set_string(DEVICE(&s->h3->sid), "identifier", + "8100c002-0001-0002-0003-000044556677"); + /* Mark H3 object realized */ object_property_set_bool(OBJECT(s->h3), true, "realized", &error_abort); if (error_abort != NULL) { diff --git a/hw/misc/allwinner-h3-sid.c b/hw/misc/allwinner-h3-sid.c new file mode 100644 index 0000000000..c472f2bcc6 --- /dev/null +++ b/hw/misc/allwinner-h3-sid.c @@ -0,0 +1,179 @@ +/* + * Allwinner H3 Security ID emulation + * + * Copyright (C) 2019 Niek Linnenbank + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#include "qemu/osdep.h" +#include "qemu/units.h" +#include "hw/sysbus.h" +#include "migration/vmstate.h" +#include "qemu/log.h" +#include "qemu/module.h" +#include "qemu/guest-random.h" +#include "qapi/error.h" +#include "hw/qdev-properties.h" +#include "hw/misc/allwinner-h3-sid.h" +#include "trace.h" + +/* SID register offsets */ +enum { + REG_PRCTL = 0x40, /* Control */ + REG_RDKEY = 0x60, /* Read Key */ +}; + +/* SID register flags */ +enum { + REG_PRCTL_WRITE = 0x0002, /* Unknown write flag */ + REG_PRCTL_OP_LOCK = 0xAC00, /* Lock operation */ +}; + +static uint64_t allwinner_h3_sid_read(void *opaque, hwaddr offset, + unsigned size) +{ + const AwH3SidState *s = (AwH3SidState *)opaque; + uint64_t val = 0; + + switch (offset) { + case REG_PRCTL: /* Control */ + val = s->control; + break; + case REG_RDKEY: /* Read Key */ + val = s->rdkey; + break; + default: + qemu_log_mask(LOG_GUEST_ERROR, "%s: bad read offset 0x%04x\n", + __func__, (uint32_t)offset); + return 0; + } + + trace_allwinner_h3_sid_read(offset, val, size); + + return val; +} + +static void allwinner_h3_sid_write(void *opaque, hwaddr offset, + uint64_t val, unsigned size) +{ + AwH3SidState *s = (AwH3SidState *)opaque; + + trace_allwinner_h3_sid_write(offset, val, size); + + switch (offset) { + case REG_PRCTL: /* Control */ + s->control = val; + + if ((s->control & REG_PRCTL_OP_LOCK) && + (s->control & REG_PRCTL_WRITE)) { + uint32_t id = s->control >> 16; + + if (id < sizeof(QemuUUID)) { + s->rdkey = (s->identifier.data[id]) | + (s->identifier.data[id + 1] << 8) | + (s->identifier.data[id + 2] << 16) | + (s->identifier.data[id + 3] << 24); + } + } + s->control &= ~REG_PRCTL_WRITE; + break; + case REG_RDKEY: /* Read Key */ + break; + default: + qemu_log_mask(LOG_GUEST_ERROR, "%s: bad write offset 0x%04x\n", + __func__, (uint32_t)offset); + break; + } +} + +static const MemoryRegionOps allwinner_h3_sid_ops = { + .read = allwinner_h3_sid_read, + .write = allwinner_h3_sid_write, + .endianness = DEVICE_NATIVE_ENDIAN, + .valid = { + .min_access_size = 4, + .max_access_size = 4, + .unaligned = false + }, + .impl.min_access_size = 4, +}; + +static void allwinner_h3_sid_reset(DeviceState *dev) +{ + AwH3SidState *s = AW_H3_SID(dev); + + /* Set default values for registers */ + s->control = 0; + s->rdkey = 0; +} + +static void allwinner_h3_sid_realize(DeviceState *dev, Error **errp) +{ +} + +static void allwinner_h3_sid_init(Object *obj) +{ + SysBusDevice *sbd = SYS_BUS_DEVICE(obj); + AwH3SidState *s = AW_H3_SID(obj); + + /* Fill UUID with zeroes by default */ + qemu_uuid_parse(UUID_NONE, &s->identifier); + + /* Memory mapping */ + memory_region_init_io(&s->iomem, OBJECT(s), &allwinner_h3_sid_ops, s, + TYPE_AW_H3_SID, 1 * KiB); + sysbus_init_mmio(sbd, &s->iomem); +} + +static Property allwinner_h3_sid_properties[] = { + DEFINE_PROP_UUID_NODEFAULT("identifier", AwH3SidState, identifier), + DEFINE_PROP_END_OF_LIST() +}; + +static const VMStateDescription allwinner_h3_sid_vmstate = { + .name = "allwinner-h3-sid", + .version_id = 1, + .minimum_version_id = 1, + .fields = (VMStateField[]) { + VMSTATE_UINT32(control, AwH3SidState), + VMSTATE_UINT32(rdkey, AwH3SidState), + VMSTATE_END_OF_LIST() + } +}; + +static void allwinner_h3_sid_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + + dc->reset = allwinner_h3_sid_reset; + dc->realize = allwinner_h3_sid_realize; + dc->vmsd = &allwinner_h3_sid_vmstate; + dc->props = allwinner_h3_sid_properties; +} + +static const TypeInfo allwinner_h3_sid_info = { + .name = TYPE_AW_H3_SID, + .parent = TYPE_SYS_BUS_DEVICE, + .instance_init = allwinner_h3_sid_init, + .instance_size = sizeof(AwH3SidState), + .class_init = allwinner_h3_sid_class_init, +}; + +static void allwinner_h3_sid_register(void) +{ + type_register_static(&allwinner_h3_sid_info); +} + +type_init(allwinner_h3_sid_register) diff --git a/hw/misc/Makefile.objs b/hw/misc/Makefile.objs index c4ca2ed689..f3620eee4e 100644 --- a/hw/misc/Makefile.objs +++ b/hw/misc/Makefile.objs @@ -31,6 +31,7 @@ common-obj-$(CONFIG_IVSHMEM_DEVICE) += ivshmem.o common-obj-$(CONFIG_ALLWINNER_H3) += allwinner-h3-clk.o obj-$(CONFIG_ALLWINNER_H3) += allwinner-h3-cpucfg.o common-obj-$(CONFIG_ALLWINNER_H3) += allwinner-h3-syscon.o +common-obj-$(CONFIG_ALLWINNER_H3) += allwinner-h3-sid.o common-obj-$(CONFIG_REALVIEW) += arm_sysctl.o common-obj-$(CONFIG_NSERIES) += cbus.o common-obj-$(CONFIG_ECCMEMCTL) += eccmemctl.o diff --git a/hw/misc/trace-events b/hw/misc/trace-events index b93089d010..a777844ca3 100644 --- a/hw/misc/trace-events +++ b/hw/misc/trace-events @@ -5,6 +5,10 @@ allwinner_h3_cpucfg_cpu_reset(uint8_t cpu_id, uint32_t reset_addr) "H3-CPUCFG: c allwinner_h3_cpucfg_read(uint64_t offset, uint64_t data, unsigned size) "H3-CPUCFG: read: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %" PRIu32 allwinner_h3_cpucfg_write(uint64_t offset, uint64_t data, unsigned size) "H3-CPUCFG: write: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %" PRIu32 +# allwinner-h3-sid.c +allwinner_h3_sid_read(uint64_t offset, uint64_t data, unsigned size) "H3-SID: read: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %" PRIu32 +allwinner_h3_sid_write(uint64_t offset, uint64_t data, unsigned size) "H3-SID: write: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %" PRIu32 + # eccmemctl.c ecc_mem_writel_mer(uint32_t val) "Write memory enable 0x%08x" ecc_mem_writel_mdr(uint32_t val) "Write memory delay 0x%08x" -- 2.17.1 From MAILER-DAEMON Mon Dec 16 18:36:16 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1igzuS-0006w9-Ed for mharc-qemu-arm@gnu.org; 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Mon, 16 Dec 2019 15:36:01 -0800 (PST) From: Niek Linnenbank To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, peter.maydell@linaro.org, philmd@redhat.com, Niek Linnenbank Subject: [PATCH v2 07/10] arm: allwinner-h3: add CPU Configuration module Date: Tue, 17 Dec 2019 00:35:16 +0100 Message-Id: <20191216233519.29030-8-nieklinnenbank@gmail.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20191216233519.29030-1-nieklinnenbank@gmail.com> References: <20191216233519.29030-1-nieklinnenbank@gmail.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::341 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 16 Dec 2019 23:36:14 -0000 The Allwinner H3 System on Chip design contains four ARM Cortex A7 processors that can be configured and reset using the CPU Configuration module interface. This commit adds support for the CPU configuration interface which emulates the following features: * CPU reset * Shared 64-bit timer Signed-off-by: Niek Linnenbank --- include/hw/arm/allwinner-h3.h | 2 + include/hw/misc/allwinner-h3-cpucfg.h | 42 ++++ hw/arm/allwinner-h3.c | 7 + hw/misc/allwinner-h3-cpucfg.c | 288 ++++++++++++++++++++++++++ hw/misc/Makefile.objs | 1 + hw/misc/trace-events | 5 + 6 files changed, 345 insertions(+) create mode 100644 include/hw/misc/allwinner-h3-cpucfg.h create mode 100644 hw/misc/allwinner-h3-cpucfg.c diff --git a/include/hw/arm/allwinner-h3.h b/include/hw/arm/allwinner-h3.h index bead6d4f85..8128ae6131 100644 --- a/include/hw/arm/allwinner-h3.h +++ b/include/hw/arm/allwinner-h3.h @@ -27,6 +27,7 @@ #include "hw/timer/allwinner-a10-pit.h" #include "hw/intc/arm_gic.h" #include "hw/misc/allwinner-h3-clk.h" +#include "hw/misc/allwinner-h3-cpucfg.h" #include "hw/misc/allwinner-h3-syscon.h" #include "target/arm/cpu.h" @@ -74,6 +75,7 @@ typedef struct AwH3State { const hwaddr *memmap; AwA10PITState timer; AwH3ClockState ccu; + AwH3CpuCfgState cpucfg; AwH3SysconState syscon; GICState gic; MemoryRegion sram_a1; diff --git a/include/hw/misc/allwinner-h3-cpucfg.h b/include/hw/misc/allwinner-h3-cpucfg.h new file mode 100644 index 0000000000..92b2dcbe2f --- /dev/null +++ b/include/hw/misc/allwinner-h3-cpucfg.h @@ -0,0 +1,42 @@ +/* + * Allwinner H3 CPU Configuration Module emulation + * + * Copyright (C) 2019 Niek Linnenbank + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#ifndef HW_MISC_ALLWINNER_H3_CPUCFG_H +#define HW_MISC_ALLWINNER_H3_CPUCFG_H + +#include "hw/sysbus.h" + +#define TYPE_AW_H3_CPUCFG "allwinner-h3-cpucfg" +#define AW_H3_CPUCFG(obj) OBJECT_CHECK(AwH3CpuCfgState, (obj), \ + TYPE_AW_H3_CPUCFG) + +typedef struct AwH3CpuCfgState { + /*< private >*/ + SysBusDevice parent_obj; + /*< public >*/ + + MemoryRegion iomem; + uint32_t gen_ctrl; + uint32_t super_standby; + uint32_t entry_addr; + uint32_t counter_ctrl; + +} AwH3CpuCfgState; + +#endif diff --git a/hw/arm/allwinner-h3.c b/hw/arm/allwinner-h3.c index 8482d616e7..1a9748ab2e 100644 --- a/hw/arm/allwinner-h3.c +++ b/hw/arm/allwinner-h3.c @@ -193,6 +193,9 @@ static void aw_h3_init(Object *obj) sysbus_init_child_obj(obj, "syscon", &s->syscon, sizeof(s->syscon), TYPE_AW_H3_SYSCON); + + sysbus_init_child_obj(obj, "cpucfg", &s->cpucfg, sizeof(s->cpucfg), + TYPE_AW_H3_CPUCFG); } static void aw_h3_realize(DeviceState *dev, Error **errp) @@ -325,6 +328,10 @@ static void aw_h3_realize(DeviceState *dev, Error **errp) qdev_init_nofail(DEVICE(&s->syscon)); sysbus_mmio_map(SYS_BUS_DEVICE(&s->syscon), 0, s->memmap[AW_H3_SYSCON]); + /* CPU Configuration */ + qdev_init_nofail(DEVICE(&s->cpucfg)); + sysbus_mmio_map(SYS_BUS_DEVICE(&s->cpucfg), 0, s->memmap[AW_H3_CPUCFG]); + /* Universal Serial Bus */ sysbus_create_simple(TYPE_AW_H3_EHCI, s->memmap[AW_H3_EHCI0], qdev_get_gpio_in(DEVICE(&s->gic), diff --git a/hw/misc/allwinner-h3-cpucfg.c b/hw/misc/allwinner-h3-cpucfg.c new file mode 100644 index 0000000000..1d238c5c78 --- /dev/null +++ b/hw/misc/allwinner-h3-cpucfg.c @@ -0,0 +1,288 @@ +/* + * Allwinner H3 CPU Configuration Module emulation + * + * Copyright (C) 2019 Niek Linnenbank + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#include "qemu/osdep.h" +#include "qemu/units.h" +#include "hw/sysbus.h" +#include "migration/vmstate.h" +#include "qemu/log.h" +#include "qemu/module.h" +#include "qemu/error-report.h" +#include "qemu/timer.h" +#include "hw/core/cpu.h" +#include "arm-powerctl.h" +#include "hw/misc/allwinner-h3-cpucfg.h" +#include "trace.h" + +/* CPUCFG register offsets */ +enum { + REG_CPUS_RST_CTRL = 0x0000, /* CPUs Reset Control */ + REG_CPU0_RST_CTRL = 0x0040, /* CPU#0 Reset Control */ + REG_CPU0_CTRL = 0x0044, /* CPU#0 Control */ + REG_CPU0_STATUS = 0x0048, /* CPU#0 Status */ + REG_CPU1_RST_CTRL = 0x0080, /* CPU#1 Reset Control */ + REG_CPU1_CTRL = 0x0084, /* CPU#1 Control */ + REG_CPU1_STATUS = 0x0088, /* CPU#1 Status */ + REG_CPU2_RST_CTRL = 0x00C0, /* CPU#2 Reset Control */ + REG_CPU2_CTRL = 0x00C4, /* CPU#2 Control */ + REG_CPU2_STATUS = 0x00C8, /* CPU#2 Status */ + REG_CPU3_RST_CTRL = 0x0100, /* CPU#3 Reset Control */ + REG_CPU3_CTRL = 0x0104, /* CPU#3 Control */ + REG_CPU3_STATUS = 0x0108, /* CPU#3 Status */ + REG_CPU_SYS_RST = 0x0140, /* CPU System Reset */ + REG_CLK_GATING = 0x0144, /* CPU Clock Gating */ + REG_GEN_CTRL = 0x0184, /* General Control */ + REG_SUPER_STANDBY = 0x01A0, /* Super Standby Flag */ + REG_ENTRY_ADDR = 0x01A4, /* Reset Entry Address */ + REG_DBG_EXTERN = 0x01E4, /* Debug External */ + REG_CNT64_CTRL = 0x0280, /* 64-bit Counter Control */ + REG_CNT64_LOW = 0x0284, /* 64-bit Counter Low */ + REG_CNT64_HIGH = 0x0288, /* 64-bit Counter High */ +}; + +/* CPUCFG register flags */ +enum { + CPUX_RESET_RELEASED = ((1 << 1) | (1 << 0)), + CPUX_STATUS_SMP = (1 << 0), + CPU_SYS_RESET_RELEASED = (1 << 0), + CLK_GATING_ENABLE = ((1 << 8) | 0xF), +}; + +/* CPUCFG register reset values */ +enum { + REG_CLK_GATING_RST = 0x0000010F, + REG_GEN_CTRL_RST = 0x00000020, + REG_SUPER_STANDBY_RST = 0x0, + REG_CNT64_CTRL_RST = 0x0, +}; + +static void allwinner_h3_cpucfg_cpu_reset(AwH3CpuCfgState *s, uint8_t cpu_id) +{ + int ret; + + trace_allwinner_h3_cpucfg_cpu_reset(cpu_id, s->entry_addr); + + ret = arm_set_cpu_on(cpu_id, s->entry_addr, 0, 3, false); + if (ret != QEMU_ARM_POWERCTL_RET_SUCCESS) { + error_report("%s: failed to bring up CPU %d: err %d", + __func__, cpu_id, ret); + return; + } +} + +static uint64_t allwinner_h3_cpucfg_read(void *opaque, hwaddr offset, + unsigned size) +{ + const AwH3CpuCfgState *s = (AwH3CpuCfgState *)opaque; + uint64_t val = 0; + + switch (offset) { + case REG_CPUS_RST_CTRL: /* CPUs Reset Control */ + case REG_CPU_SYS_RST: /* CPU System Reset */ + val = CPU_SYS_RESET_RELEASED; + break; + case REG_CPU0_RST_CTRL: /* CPU#0 Reset Control */ + case REG_CPU1_RST_CTRL: /* CPU#1 Reset Control */ + case REG_CPU2_RST_CTRL: /* CPU#2 Reset Control */ + case REG_CPU3_RST_CTRL: /* CPU#3 Reset Control */ + val = CPUX_RESET_RELEASED; + break; + case REG_CPU0_CTRL: /* CPU#0 Control */ + case REG_CPU1_CTRL: /* CPU#1 Control */ + case REG_CPU2_CTRL: /* CPU#2 Control */ + case REG_CPU3_CTRL: /* CPU#3 Control */ + val = 0; + break; + case REG_CPU0_STATUS: /* CPU#0 Status */ + case REG_CPU1_STATUS: /* CPU#1 Status */ + case REG_CPU2_STATUS: /* CPU#2 Status */ + case REG_CPU3_STATUS: /* CPU#3 Status */ + val = CPUX_STATUS_SMP; + break; + case REG_CLK_GATING: /* CPU Clock Gating */ + val = CLK_GATING_ENABLE; + break; + case REG_GEN_CTRL: /* General Control */ + val = s->gen_ctrl; + break; + case REG_SUPER_STANDBY: /* Super Standby Flag */ + val = s->super_standby; + break; + case REG_ENTRY_ADDR: /* Reset Entry Address */ + val = s->entry_addr; + break; + case REG_DBG_EXTERN: /* Debug External */ + break; + case REG_CNT64_CTRL: /* 64-bit Counter Control */ + val = s->counter_ctrl; + break; + case REG_CNT64_LOW: /* 64-bit Counter Low */ + val = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) & 0xffffffff; + break; + case REG_CNT64_HIGH: /* 64-bit Counter High */ + val = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) >> 32; + break; + default: + qemu_log_mask(LOG_GUEST_ERROR, "%s: bad read offset 0x%04x\n", + __func__, (uint32_t)offset); + return 0; + } + + trace_allwinner_h3_cpucfg_read(offset, val, size); + + return val; +} + +static void allwinner_h3_cpucfg_write(void *opaque, hwaddr offset, + uint64_t val, unsigned size) +{ + AwH3CpuCfgState *s = (AwH3CpuCfgState *)opaque; + + trace_allwinner_h3_cpucfg_write(offset, val, size); + + switch (offset) { + case REG_CPUS_RST_CTRL: /* CPUs Reset Control */ + case REG_CPU_SYS_RST: /* CPU System Reset */ + break; + case REG_CPU0_RST_CTRL: /* CPU#0 Reset Control */ + if (val) { + allwinner_h3_cpucfg_cpu_reset(s, 0); + } + break; + case REG_CPU1_RST_CTRL: /* CPU#1 Reset Control */ + if (val) { + allwinner_h3_cpucfg_cpu_reset(s, 1); + } + break; + case REG_CPU2_RST_CTRL: /* CPU#2 Reset Control */ + if (val) { + allwinner_h3_cpucfg_cpu_reset(s, 2); + } + break; + case REG_CPU3_RST_CTRL: /* CPU#3 Reset Control */ + if (val) { + allwinner_h3_cpucfg_cpu_reset(s, 3); + } + break; + case REG_CPU0_CTRL: /* CPU#0 Control */ + case REG_CPU1_CTRL: /* CPU#1 Control */ + case REG_CPU2_CTRL: /* CPU#2 Control */ + case REG_CPU3_CTRL: /* CPU#3 Control */ + case REG_CPU0_STATUS: /* CPU#0 Status */ + case REG_CPU1_STATUS: /* CPU#1 Status */ + case REG_CPU2_STATUS: /* CPU#2 Status */ + case REG_CPU3_STATUS: /* CPU#3 Status */ + case REG_CLK_GATING: /* CPU Clock Gating */ + case REG_GEN_CTRL: /* General Control */ + s->gen_ctrl = val; + break; + case REG_SUPER_STANDBY: /* Super Standby Flag */ + s->super_standby = val; + break; + case REG_ENTRY_ADDR: /* Reset Entry Address */ + s->entry_addr = val; + break; + case REG_DBG_EXTERN: /* Debug External */ + break; + case REG_CNT64_CTRL: /* 64-bit Counter Control */ + s->counter_ctrl = val; + break; + case REG_CNT64_LOW: /* 64-bit Counter Low */ + case REG_CNT64_HIGH: /* 64-bit Counter High */ + break; + default: + qemu_log_mask(LOG_GUEST_ERROR, "%s: bad write offset 0x%04x\n", + __func__, (uint32_t)offset); + return; + } +} + +static const MemoryRegionOps allwinner_h3_cpucfg_ops = { + .read = allwinner_h3_cpucfg_read, + .write = allwinner_h3_cpucfg_write, + .endianness = DEVICE_NATIVE_ENDIAN, + .valid = { + .min_access_size = 4, + .max_access_size = 4, + .unaligned = false + }, + .impl.min_access_size = 4, +}; + +static void allwinner_h3_cpucfg_reset(DeviceState *dev) +{ + AwH3CpuCfgState *s = AW_H3_CPUCFG(dev); + + /* Set default values for registers */ + s->gen_ctrl = REG_GEN_CTRL_RST; + s->super_standby = REG_SUPER_STANDBY_RST; + s->entry_addr = 0; + s->counter_ctrl = REG_CNT64_CTRL_RST; +} + +static void allwinner_h3_cpucfg_realize(DeviceState *dev, Error **errp) +{ +} + +static void allwinner_h3_cpucfg_init(Object *obj) +{ + SysBusDevice *sbd = SYS_BUS_DEVICE(obj); + AwH3CpuCfgState *s = AW_H3_CPUCFG(obj); + + /* Memory mapping */ + memory_region_init_io(&s->iomem, OBJECT(s), &allwinner_h3_cpucfg_ops, s, + TYPE_AW_H3_CPUCFG, 1 * KiB); + sysbus_init_mmio(sbd, &s->iomem); +} + +static const VMStateDescription allwinner_h3_cpucfg_vmstate = { + .name = "allwinner-h3-cpucfg", + .version_id = 1, + .minimum_version_id = 1, + .fields = (VMStateField[]) { + VMSTATE_UINT32(gen_ctrl, AwH3CpuCfgState), + VMSTATE_UINT32(super_standby, AwH3CpuCfgState), + VMSTATE_UINT32(counter_ctrl, AwH3CpuCfgState), + VMSTATE_END_OF_LIST() + } +}; + +static void allwinner_h3_cpucfg_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + + dc->reset = allwinner_h3_cpucfg_reset; + dc->realize = allwinner_h3_cpucfg_realize; + dc->vmsd = &allwinner_h3_cpucfg_vmstate; +} + +static const TypeInfo allwinner_h3_cpucfg_info = { + .name = TYPE_AW_H3_CPUCFG, + .parent = TYPE_SYS_BUS_DEVICE, + .instance_init = allwinner_h3_cpucfg_init, + .instance_size = sizeof(AwH3CpuCfgState), + .class_init = allwinner_h3_cpucfg_class_init, +}; + +static void allwinner_h3_cpucfg_register(void) +{ + type_register_static(&allwinner_h3_cpucfg_info); +} + +type_init(allwinner_h3_cpucfg_register) diff --git a/hw/misc/Makefile.objs b/hw/misc/Makefile.objs index b234aefba5..c4ca2ed689 100644 --- a/hw/misc/Makefile.objs +++ b/hw/misc/Makefile.objs @@ -29,6 +29,7 @@ common-obj-$(CONFIG_MACIO) += macio/ common-obj-$(CONFIG_IVSHMEM_DEVICE) += ivshmem.o common-obj-$(CONFIG_ALLWINNER_H3) += allwinner-h3-clk.o +obj-$(CONFIG_ALLWINNER_H3) += allwinner-h3-cpucfg.o common-obj-$(CONFIG_ALLWINNER_H3) += allwinner-h3-syscon.o common-obj-$(CONFIG_REALVIEW) += arm_sysctl.o common-obj-$(CONFIG_NSERIES) += cbus.o diff --git a/hw/misc/trace-events b/hw/misc/trace-events index 1deb1d08c1..b93089d010 100644 --- a/hw/misc/trace-events +++ b/hw/misc/trace-events @@ -1,5 +1,10 @@ # See docs/devel/tracing.txt for syntax documentation. +# allwinner-h3-cpucfg.c +allwinner_h3_cpucfg_cpu_reset(uint8_t cpu_id, uint32_t reset_addr) "H3-CPUCFG: cpu_reset: id %u, reset_addr 0x%" PRIu32 +allwinner_h3_cpucfg_read(uint64_t offset, uint64_t data, unsigned size) "H3-CPUCFG: read: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %" PRIu32 +allwinner_h3_cpucfg_write(uint64_t offset, uint64_t data, unsigned size) "H3-CPUCFG: write: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %" PRIu32 + # eccmemctl.c ecc_mem_writel_mer(uint32_t val) "Write memory enable 0x%08x" ecc_mem_writel_mdr(uint32_t val) "Write memory delay 0x%08x" -- 2.17.1 From MAILER-DAEMON Mon Dec 16 18:36:23 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1igzuZ-00078J-Dw for mharc-qemu-arm@gnu.org; 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Mon, 16 Dec 2019 15:36:03 -0800 (PST) From: Niek Linnenbank To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, peter.maydell@linaro.org, philmd@redhat.com, Niek Linnenbank Subject: [PATCH v2 10/10] arm: allwinner-h3: add EMAC ethernet device Date: Tue, 17 Dec 2019 00:35:19 +0100 Message-Id: <20191216233519.29030-11-nieklinnenbank@gmail.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20191216233519.29030-1-nieklinnenbank@gmail.com> References: <20191216233519.29030-1-nieklinnenbank@gmail.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::343 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 16 Dec 2019 23:36:22 -0000 The Allwinner H3 System on Chip includes an Ethernet MAC (EMAC) which provides 10M/100M/1000M Ethernet connectivity. This commit adds support for the Allwinner H3 EMAC, including emulation for the following functionality: * DMA transfers * MII interface * Transmit CRC calculation Signed-off-by: Niek Linnenbank --- include/hw/arm/allwinner-h3.h | 2 + include/hw/net/allwinner-h3-emac.h | 67 +++ hw/arm/allwinner-h3.c | 13 + hw/arm/orangepi.c | 7 + hw/net/allwinner-h3-emac.c | 831 +++++++++++++++++++++++++++++ hw/arm/Kconfig | 1 + hw/net/Kconfig | 3 + hw/net/Makefile.objs | 1 + hw/net/trace-events | 10 + 9 files changed, 935 insertions(+) create mode 100644 include/hw/net/allwinner-h3-emac.h create mode 100644 hw/net/allwinner-h3-emac.c diff --git a/include/hw/arm/allwinner-h3.h b/include/hw/arm/allwinner-h3.h index ab564987be..357bdfa711 100644 --- a/include/hw/arm/allwinner-h3.h +++ b/include/hw/arm/allwinner-h3.h @@ -31,6 +31,7 @@ #include "hw/misc/allwinner-h3-syscon.h" #include "hw/misc/allwinner-h3-sid.h" #include "hw/sd/allwinner-h3-sdhost.h" +#include "hw/net/allwinner-h3-emac.h" #include "target/arm/cpu.h" enum { @@ -81,6 +82,7 @@ typedef struct AwH3State { AwH3SysconState syscon; AwH3SidState sid; AwH3SDHostState mmc0; + AwH3EmacState emac; GICState gic; MemoryRegion sram_a1; MemoryRegion sram_a2; diff --git a/include/hw/net/allwinner-h3-emac.h b/include/hw/net/allwinner-h3-emac.h new file mode 100644 index 0000000000..8fb2bd6e87 --- /dev/null +++ b/include/hw/net/allwinner-h3-emac.h @@ -0,0 +1,67 @@ +/* + * Allwinner H3 EMAC emulation + * + * Copyright (C) 2019 Niek Linnenbank + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#ifndef ALLWINNER_H3_EMAC_H +#define ALLWINNER_H3_EMAC_H + +#include "qemu/units.h" +#include "net/net.h" +#include "qemu/fifo8.h" +#include "hw/net/mii.h" +#include "hw/sysbus.h" + +#define TYPE_AW_H3_EMAC "allwinner-h3-emac" +#define AW_H3_EMAC(obj) OBJECT_CHECK(AwH3EmacState, (obj), TYPE_AW_H3_EMAC) + +typedef struct AwH3EmacState { + /*< private >*/ + SysBusDevice parent_obj; + /*< public >*/ + + MemoryRegion iomem; + qemu_irq irq; + NICState *nic; + NICConf conf; + + uint8_t mii_phy_addr; + uint32_t mii_cmd; + uint32_t mii_data; + uint32_t mii_cr; + uint32_t mii_st; + + uint32_t basic_ctl0; + uint32_t basic_ctl1; + uint32_t int_en; + uint32_t int_sta; + uint32_t frm_flt; + + uint32_t rx_ctl0; + uint32_t rx_ctl1; + uint32_t rx_desc_head; + uint32_t rx_desc_curr; + + uint32_t tx_ctl0; + uint32_t tx_ctl1; + uint32_t tx_desc_head; + uint32_t tx_desc_curr; + uint32_t tx_flowctl; + +} AwH3EmacState; + +#endif diff --git a/hw/arm/allwinner-h3.c b/hw/arm/allwinner-h3.c index b4ee524ee0..b49f8d81ac 100644 --- a/hw/arm/allwinner-h3.c +++ b/hw/arm/allwinner-h3.c @@ -202,6 +202,9 @@ static void aw_h3_init(Object *obj) sysbus_init_child_obj(obj, "mmc0", &s->mmc0, sizeof(s->mmc0), TYPE_AW_H3_SDHOST); + + sysbus_init_child_obj(obj, "emac", &s->emac, sizeof(s->emac), + TYPE_AW_H3_EMAC); } static void aw_h3_realize(DeviceState *dev, Error **errp) @@ -355,6 +358,16 @@ static void aw_h3_realize(DeviceState *dev, Error **errp) return; } + /* EMAC */ + if (nd_table[0].used) { + qemu_check_nic_model(&nd_table[0], TYPE_AW_H3_EMAC); + qdev_set_nic_properties(DEVICE(&s->emac), &nd_table[0]); + } + qdev_init_nofail(DEVICE(&s->emac)); + sysbus_mmio_map(SYS_BUS_DEVICE(&s->emac), 0, s->memmap[AW_H3_EMAC]); + sysbus_connect_irq(SYS_BUS_DEVICE(&s->emac), 0, + qdev_get_gpio_in(DEVICE(&s->gic), AW_H3_GIC_SPI_EMAC)); + /* Universal Serial Bus */ sysbus_create_simple(TYPE_AW_H3_EHCI, s->memmap[AW_H3_EHCI0], qdev_get_gpio_in(DEVICE(&s->gic), diff --git a/hw/arm/orangepi.c b/hw/arm/orangepi.c index 87968505ae..119f370924 100644 --- a/hw/arm/orangepi.c +++ b/hw/arm/orangepi.c @@ -70,6 +70,13 @@ static void orangepi_init(MachineState *machine) qdev_prop_set_string(DEVICE(&s->h3->sid), "identifier", "8100c002-0001-0002-0003-000044556677"); + /* Setup EMAC properties */ + object_property_set_int(OBJECT(&s->h3->emac), 1, "phy-addr", &error_abort); + if (error_abort != NULL) { + error_reportf_err(error_abort, "Couldn't set phy address: "); + exit(1); + } + /* Mark H3 object realized */ object_property_set_bool(OBJECT(s->h3), true, "realized", &error_abort); if (error_abort != NULL) { diff --git a/hw/net/allwinner-h3-emac.c b/hw/net/allwinner-h3-emac.c new file mode 100644 index 0000000000..7a0daced83 --- /dev/null +++ b/hw/net/allwinner-h3-emac.c @@ -0,0 +1,831 @@ +/* + * Allwinner H3 EMAC emulation + * + * Copyright (C) 2019 Niek Linnenbank + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#include "qemu/osdep.h" +#include "qemu/units.h" +#include "hw/sysbus.h" +#include "migration/vmstate.h" +#include "net/net.h" +#include "hw/irq.h" +#include "hw/qdev-properties.h" +#include "qemu/log.h" +#include "trace.h" +#include "net/checksum.h" +#include "qemu/module.h" +#include "exec/cpu-common.h" +#include "hw/net/allwinner-h3-emac.h" + +/* EMAC register offsets */ +enum { + REG_BASIC_CTL_0 = 0x0000, /* Basic Control 0 */ + REG_BASIC_CTL_1 = 0x0004, /* Basic Control 1 */ + REG_INT_STA = 0x0008, /* Interrupt Status */ + REG_INT_EN = 0x000C, /* Interrupt Enable */ + REG_TX_CTL_0 = 0x0010, /* Transmit Control 0 */ + REG_TX_CTL_1 = 0x0014, /* Transmit Control 1 */ + REG_TX_FLOW_CTL = 0x001C, /* Transmit Flow Control */ + REG_TX_DMA_DESC_LIST = 0x0020, /* Transmit Descriptor List Address */ + REG_RX_CTL_0 = 0x0024, /* Receive Control 0 */ + REG_RX_CTL_1 = 0x0028, /* Receive Control 1 */ + REG_RX_DMA_DESC_LIST = 0x0034, /* Receive Descriptor List Address */ + REG_FRM_FLT = 0x0038, /* Receive Frame Filter */ + REG_RX_HASH_0 = 0x0040, /* Receive Hash Table 0 */ + REG_RX_HASH_1 = 0x0044, /* Receive Hash Table 1 */ + REG_MII_CMD = 0x0048, /* Management Interface Command */ + REG_MII_DATA = 0x004C, /* Management Interface Data */ + REG_ADDR_HIGH = 0x0050, /* MAC Address High */ + REG_ADDR_LOW = 0x0054, /* MAC Address Low */ + REG_TX_DMA_STA = 0x00B0, /* Transmit DMA Status */ + REG_TX_CUR_DESC = 0x00B4, /* Transmit Current Descriptor */ + REG_TX_CUR_BUF = 0x00B8, /* Transmit Current Buffer */ + REG_RX_DMA_STA = 0x00C0, /* Receive DMA Status */ + REG_RX_CUR_DESC = 0x00C4, /* Receive Current Descriptor */ + REG_RX_CUR_BUF = 0x00C8, /* Receive Current Buffer */ + REG_RGMII_STA = 0x00D0, /* RGMII Status */ +}; + +/* EMAC register flags */ +enum { + BASIC_CTL0_100Mbps = (0b11 << 2), + BASIC_CTL0_FD = (1 << 0), + BASIC_CTL1_SOFTRST = (1 << 0), +}; + +enum { + INT_STA_RGMII_LINK = (1 << 16), + INT_STA_RX_EARLY = (1 << 13), + INT_STA_RX_OVERFLOW = (1 << 12), + INT_STA_RX_TIMEOUT = (1 << 11), + INT_STA_RX_DMA_STOP = (1 << 10), + INT_STA_RX_BUF_UA = (1 << 9), + INT_STA_RX = (1 << 8), + INT_STA_TX_EARLY = (1 << 5), + INT_STA_TX_UNDERFLOW = (1 << 4), + INT_STA_TX_TIMEOUT = (1 << 3), + INT_STA_TX_BUF_UA = (1 << 2), + INT_STA_TX_DMA_STOP = (1 << 1), + INT_STA_TX = (1 << 0), +}; + +enum { + INT_EN_RX_EARLY = (1 << 13), + INT_EN_RX_OVERFLOW = (1 << 12), + INT_EN_RX_TIMEOUT = (1 << 11), + INT_EN_RX_DMA_STOP = (1 << 10), + INT_EN_RX_BUF_UA = (1 << 9), + INT_EN_RX = (1 << 8), + INT_EN_TX_EARLY = (1 << 5), + INT_EN_TX_UNDERFLOW = (1 << 4), + INT_EN_TX_TIMEOUT = (1 << 3), + INT_EN_TX_BUF_UA = (1 << 2), + INT_EN_TX_DMA_STOP = (1 << 1), + INT_EN_TX = (1 << 0), +}; + +enum { + TX_CTL0_TX_EN = (1 << 31), + TX_CTL1_TX_DMA_START = (1 << 31), + TX_CTL1_TX_DMA_EN = (1 << 30), + TX_CTL1_TX_FLUSH = (1 << 0), +}; + +enum { + RX_CTL0_RX_EN = (1 << 31), + RX_CTL0_STRIP_FCS = (1 << 28), + RX_CTL0_CRC_IPV4 = (1 << 27), +}; + +enum { + RX_CTL1_RX_DMA_START = (1 << 31), + RX_CTL1_RX_DMA_EN = (1 << 30), + RX_CTL1_RX_MD = (1 << 1), +}; + +enum { + RX_FRM_FLT_DIS_ADDR = (1 << 31), +}; + +enum { + MII_CMD_PHY_ADDR_SHIFT = (12), + MII_CMD_PHY_ADDR_MASK = (0xf000), + MII_CMD_PHY_REG_SHIFT = (4), + MII_CMD_PHY_REG_MASK = (0xf0), + MII_CMD_PHY_RW = (1 << 1), + MII_CMD_PHY_BUSY = (1 << 0), +}; + +enum { + TX_DMA_STA_STOP = (0b000), + TX_DMA_STA_RUN_FETCH = (0b001), + TX_DMA_STA_WAIT_STA = (0b010), +}; + +enum { + RX_DMA_STA_STOP = (0b000), + RX_DMA_STA_RUN_FETCH = (0b001), + RX_DMA_STA_WAIT_FRM = (0b011), +}; + +enum { + RGMII_LINK_UP = (1 << 3), + RGMII_FD = (1 << 0), +}; + +/* EMAC register reset values */ +enum { + REG_BASIC_CTL_1_RST = 0x08000000, +}; + +/* EMAC constants */ +enum { + AW_H3_EMAC_MIN_PKT_SZ = 64 +}; + +/* Transmit/receive frame descriptor */ +typedef struct FrameDescriptor { + uint32_t status; + uint32_t status2; + uint32_t addr; + uint32_t next; +} FrameDescriptor; + +/* Frame descriptor flags */ +enum { + DESC_STATUS_CTL = (1 << 31), + DESC_STATUS2_BUF_SIZE_MASK = (0x7ff), +}; + +/* Transmit frame descriptor flags */ +enum { + TX_DESC_STATUS_LENGTH_ERR = (1 << 14), + TX_DESC_STATUS2_FIRST_DESC = (1 << 29), + TX_DESC_STATUS2_LAST_DESC = (1 << 30), + TX_DESC_STATUS2_CHECKSUM_MASK = (0x3 << 27), +}; + +/* Receive frame descriptor flags */ +enum { + RX_DESC_STATUS_FIRST_DESC = (1 << 9), + RX_DESC_STATUS_LAST_DESC = (1 << 8), + RX_DESC_STATUS_FRM_LEN_MASK = (0x3fff0000), + RX_DESC_STATUS_FRM_LEN_SHIFT = (16), + RX_DESC_STATUS_NO_BUF = (1 << 14), + RX_DESC_STATUS_HEADER_ERR = (1 << 7), + RX_DESC_STATUS_LENGTH_ERR = (1 << 4), + RX_DESC_STATUS_CRC_ERR = (1 << 1), + RX_DESC_STATUS_PAYLOAD_ERR = (1 << 0), + RX_DESC_STATUS2_RX_INT_CTL = (1 << 31), +}; + +/* MII register offsets */ +enum { + MII_REG_CR = (0x0), + MII_REG_ST = (0x1), + MII_REG_ID_HIGH = (0x2), + MII_REG_ID_LOW = (0x3), +}; + +/* MII register flags */ +enum { + MII_REG_CR_RESET = (1 << 15), + MII_REG_CR_POWERDOWN = (1 << 11), + MII_REG_CR_10Mbit = (0), + MII_REG_CR_100Mbit = (1 << 13), + MII_REG_CR_1000Mbit = (1 << 6), + MII_REG_CR_AUTO_NEG = (1 << 12), + MII_REG_CR_AUTO_NEG_RESTART = (1 << 9), + MII_REG_CR_FULLDUPLEX = (1 << 8), +}; + +enum { + MII_REG_ST_100BASE_T4 = (1 << 15), + MII_REG_ST_100BASE_X_FD = (1 << 14), + MII_REG_ST_100BASE_X_HD = (1 << 13), + MII_REG_ST_10_FD = (1 << 12), + MII_REG_ST_10_HD = (1 << 11), + MII_REG_ST_100BASE_T2_FD = (1 << 10), + MII_REG_ST_100BASE_T2_HD = (1 << 9), + MII_REG_ST_AUTONEG_COMPLETE = (1 << 5), + MII_REG_ST_AUTONEG_AVAIL = (1 << 3), + MII_REG_ST_LINK_UP = (1 << 2), +}; + +/* MII constants */ +enum { + MII_PHY_ID_HIGH = 0x0044, + MII_PHY_ID_LOW = 0x1400, +}; + +static void aw_h3_emac_mii_set_link(AwH3EmacState *s, bool link_active) +{ + if (link_active) { + s->mii_st |= MII_REG_ST_LINK_UP; + } else { + s->mii_st &= ~MII_REG_ST_LINK_UP; + } +} + +static void aw_h3_emac_mii_reset(AwH3EmacState *s, bool link_active) +{ + s->mii_cr = MII_REG_CR_100Mbit | MII_REG_CR_AUTO_NEG | + MII_REG_CR_FULLDUPLEX; + s->mii_st = MII_REG_ST_100BASE_T4 | MII_REG_ST_100BASE_X_FD | + MII_REG_ST_100BASE_X_HD | MII_REG_ST_10_FD | MII_REG_ST_10_HD | + MII_REG_ST_100BASE_T2_FD | MII_REG_ST_100BASE_T2_HD | + MII_REG_ST_AUTONEG_COMPLETE | MII_REG_ST_AUTONEG_AVAIL; + + aw_h3_emac_mii_set_link(s, link_active); +} + +static void aw_h3_emac_mii_cmd(AwH3EmacState *s) +{ + uint8_t addr, reg; + + addr = (s->mii_cmd & MII_CMD_PHY_ADDR_MASK) >> MII_CMD_PHY_ADDR_SHIFT; + reg = (s->mii_cmd & MII_CMD_PHY_REG_MASK) >> MII_CMD_PHY_REG_SHIFT; + + if (addr != s->mii_phy_addr) { + return; + } + + /* Read or write a PHY register? */ + if (s->mii_cmd & MII_CMD_PHY_RW) { + trace_aw_h3_emac_mii_write_reg(reg, s->mii_data); + + switch (reg) { + case MII_REG_CR: + if (s->mii_data & MII_REG_CR_RESET) { + aw_h3_emac_mii_reset(s, s->mii_st & MII_REG_ST_LINK_UP); + } else { + s->mii_cr = s->mii_data & ~(MII_REG_CR_RESET | + MII_REG_CR_AUTO_NEG_RESTART); + } + break; + default: + qemu_log_mask(LOG_UNIMP, "allwinner-h3-emac: write access to " + "unknown MII register 0x%x\n", reg); + break; + } + } else { + switch (reg) { + case MII_REG_CR: + s->mii_data = s->mii_cr; + break; + case MII_REG_ST: + s->mii_data = s->mii_st; + break; + case MII_REG_ID_HIGH: + s->mii_data = MII_PHY_ID_HIGH; + break; + case MII_REG_ID_LOW: + s->mii_data = MII_PHY_ID_LOW; + break; + default: + qemu_log_mask(LOG_UNIMP, "allwinner-h3-emac: read access to " + "unknown MII register 0x%x\n", reg); + s->mii_data = 0; + break; + } + + trace_aw_h3_emac_mii_read_reg(reg, s->mii_data); + } +} + +static void aw_h3_emac_update_irq(AwH3EmacState *s) +{ + qemu_set_irq(s->irq, (s->int_sta & s->int_en) != 0); +} + +static uint32_t aw_h3_emac_next_desc(FrameDescriptor *desc, size_t min_size) +{ + uint32_t paddr = desc->next; + + cpu_physical_memory_read(paddr, desc, sizeof(*desc)); + + if ((desc->status & DESC_STATUS_CTL) && + (desc->status2 & DESC_STATUS2_BUF_SIZE_MASK) >= min_size) { + return paddr; + } else { + return 0; + } +} + +static uint32_t aw_h3_emac_get_desc(FrameDescriptor *desc, uint32_t start_addr, + size_t min_size) +{ + uint32_t desc_addr = start_addr; + + /* Note that the list is a cycle. Last entry points back to the head. */ + while (desc_addr != 0) { + cpu_physical_memory_read(desc_addr, desc, sizeof(*desc)); + + if ((desc->status & DESC_STATUS_CTL) && + (desc->status2 & DESC_STATUS2_BUF_SIZE_MASK) >= min_size) { + return desc_addr; + } else if (desc->next == start_addr) { + break; + } else { + desc_addr = desc->next; + } + } + + return 0; +} + +static uint32_t aw_h3_emac_get_rx_desc(AwH3EmacState *s, FrameDescriptor *desc, + size_t min_size) +{ + return aw_h3_emac_get_desc(desc, s->rx_desc_curr, min_size); +} + +static uint32_t aw_h3_emac_get_tx_desc(AwH3EmacState *s, FrameDescriptor *desc, + size_t min_size) +{ + return aw_h3_emac_get_desc(desc, s->tx_desc_head, min_size); +} + +static void aw_h3_emac_flush_desc(FrameDescriptor *desc, uint32_t phys_addr) +{ + cpu_physical_memory_write(phys_addr, desc, sizeof(*desc)); +} + +static int aw_h3_emac_can_receive(NetClientState *nc) +{ + AwH3EmacState *s = qemu_get_nic_opaque(nc); + FrameDescriptor desc; + + return (s->rx_ctl0 & RX_CTL0_RX_EN) && + (aw_h3_emac_get_rx_desc(s, &desc, 0) != 0); +} + +static ssize_t aw_h3_emac_receive(NetClientState *nc, const uint8_t *buf, + size_t size) +{ + AwH3EmacState *s = qemu_get_nic_opaque(nc); + FrameDescriptor desc; + size_t bytes_left = size; + size_t desc_bytes = 0; + size_t pad_fcs_size = 4; + size_t padding = 0; + + if (!(s->rx_ctl0 & RX_CTL0_RX_EN)) { + return -1; + } + + s->rx_desc_curr = aw_h3_emac_get_rx_desc(s, &desc, AW_H3_EMAC_MIN_PKT_SZ); + if (!s->rx_desc_curr) { + s->int_sta |= INT_STA_RX_BUF_UA; + } + + /* Keep filling RX descriptors until the whole frame is written */ + while (s->rx_desc_curr && bytes_left > 0) { + desc.status &= ~DESC_STATUS_CTL; + desc.status &= ~RX_DESC_STATUS_FRM_LEN_MASK; + + if (bytes_left == size) { + desc.status |= RX_DESC_STATUS_FIRST_DESC; + } + + if ((desc.status2 & DESC_STATUS2_BUF_SIZE_MASK) < + (bytes_left + pad_fcs_size)) { + desc_bytes = desc.status2 & DESC_STATUS2_BUF_SIZE_MASK; + desc.status |= desc_bytes << RX_DESC_STATUS_FRM_LEN_SHIFT; + } else { + padding = pad_fcs_size; + if (bytes_left < AW_H3_EMAC_MIN_PKT_SZ) { + padding += (AW_H3_EMAC_MIN_PKT_SZ - bytes_left); + } + + desc_bytes = (bytes_left); + desc.status |= RX_DESC_STATUS_LAST_DESC; + desc.status |= (bytes_left + padding) + << RX_DESC_STATUS_FRM_LEN_SHIFT; + } + + cpu_physical_memory_write(desc.addr, buf, desc_bytes); + aw_h3_emac_flush_desc(&desc, s->rx_desc_curr); + trace_aw_h3_emac_receive(s->rx_desc_curr, desc.addr, desc_bytes); + + /* Check if frame needs to raise the receive interrupt */ + if (!(desc.status2 & RX_DESC_STATUS2_RX_INT_CTL)) { + s->int_sta |= INT_STA_RX; + } + + /* Increment variables */ + buf += desc_bytes; + bytes_left -= desc_bytes; + + /* Move to the next descriptor */ + s->rx_desc_curr = aw_h3_emac_next_desc(&desc, 64); + if (!s->rx_desc_curr) { + /* Not enough buffer space available */ + s->int_sta |= INT_STA_RX_BUF_UA; + s->rx_desc_curr = s->rx_desc_head; + break; + } + } + + /* Report receive DMA is finished */ + s->rx_ctl1 &= ~RX_CTL1_RX_DMA_START; + aw_h3_emac_update_irq(s); + + return size; +} + +static void aw_h3_emac_transmit(AwH3EmacState *s) +{ + NetClientState *nc = qemu_get_queue(s->nic); + FrameDescriptor desc; + size_t bytes = 0; + size_t packet_bytes = 0; + size_t transmitted = 0; + static uint8_t packet_buf[2048]; + + s->tx_desc_curr = aw_h3_emac_get_tx_desc(s, &desc, 0); + + /* Read all transmit descriptors */ + while (s->tx_desc_curr != 0) { + + /* Read from physical memory into packet buffer */ + bytes = desc.status2 & DESC_STATUS2_BUF_SIZE_MASK; + if (bytes + packet_bytes > sizeof(packet_buf)) { + desc.status |= TX_DESC_STATUS_LENGTH_ERR; + break; + } + cpu_physical_memory_read(desc.addr, packet_buf + packet_bytes, bytes); + packet_bytes += bytes; + desc.status &= ~DESC_STATUS_CTL; + aw_h3_emac_flush_desc(&desc, s->tx_desc_curr); + + /* After the last descriptor, send the packet */ + if (desc.status2 & TX_DESC_STATUS2_LAST_DESC) { + if (desc.status2 & TX_DESC_STATUS2_CHECKSUM_MASK) { + net_checksum_calculate(packet_buf, packet_bytes); + } + + qemu_send_packet(nc, packet_buf, packet_bytes); + trace_aw_h3_emac_transmit(s->tx_desc_curr, desc.addr, bytes); + + packet_bytes = 0; + transmitted++; + } + s->tx_desc_curr = aw_h3_emac_next_desc(&desc, 0); + } + + /* Raise transmit completed interrupt */ + if (transmitted > 0) { + s->int_sta |= INT_STA_TX; + s->tx_ctl1 &= ~TX_CTL1_TX_DMA_START; + aw_h3_emac_update_irq(s); + } +} + +static void aw_h3_emac_reset(DeviceState *dev) +{ + AwH3EmacState *s = AW_H3_EMAC(dev); + NetClientState *nc = qemu_get_queue(s->nic); + + trace_aw_h3_emac_reset(); + + s->mii_cmd = 0; + s->mii_data = 0; + s->basic_ctl0 = 0; + s->basic_ctl1 = 0; + s->int_en = 0; + s->int_sta = 0; + s->frm_flt = 0; + s->rx_ctl0 = 0; + s->rx_ctl1 = RX_CTL1_RX_MD; + s->rx_desc_head = 0; + s->rx_desc_curr = 0; + s->tx_ctl0 = 0; + s->tx_ctl1 = 0; + s->tx_desc_head = 0; + s->tx_desc_curr = 0; + s->tx_flowctl = 0; + + aw_h3_emac_mii_reset(s, !nc->link_down); +} + +static uint64_t aw_h3_emac_read(void *opaque, hwaddr offset, unsigned size) +{ + AwH3EmacState *s = AW_H3_EMAC(opaque); + uint64_t value = 0; + FrameDescriptor desc; + + switch (offset) { + case REG_BASIC_CTL_0: /* Basic Control 0 */ + value = s->basic_ctl0; + break; + case REG_BASIC_CTL_1: /* Basic Control 1 */ + value = s->basic_ctl1; + break; + case REG_INT_STA: /* Interrupt Status */ + value = s->int_sta; + break; + case REG_INT_EN: /* Interupt Enable */ + value = s->int_en; + break; + case REG_TX_CTL_0: /* Transmit Control 0 */ + value = s->tx_ctl0; + break; + case REG_TX_CTL_1: /* Transmit Control 1 */ + value = s->tx_ctl1; + break; + case REG_TX_FLOW_CTL: /* Transmit Flow Control */ + value = s->tx_flowctl; + break; + case REG_TX_DMA_DESC_LIST: /* Transmit Descriptor List Address */ + value = s->tx_desc_head; + break; + case REG_RX_CTL_0: /* Receive Control 0 */ + value = s->rx_ctl0; + break; + case REG_RX_CTL_1: /* Receive Control 1 */ + value = s->rx_ctl1; + break; + case REG_RX_DMA_DESC_LIST: /* Receive Descriptor List Address */ + value = s->rx_desc_head; + break; + case REG_FRM_FLT: /* Receive Frame Filter */ + value = s->frm_flt; + break; + case REG_RX_HASH_0: /* Receive Hash Table 0 */ + case REG_RX_HASH_1: /* Receive Hash Table 1 */ + break; + case REG_MII_CMD: /* Management Interface Command */ + value = s->mii_cmd; + break; + case REG_MII_DATA: /* Management Interface Data */ + value = s->mii_data; + break; + case REG_ADDR_HIGH: /* MAC Address High */ + value = *(((uint32_t *) (s->conf.macaddr.a)) + 1); + break; + case REG_ADDR_LOW: /* MAC Address Low */ + value = *(uint32_t *) (s->conf.macaddr.a); + break; + case REG_TX_DMA_STA: /* Transmit DMA Status */ + break; + case REG_TX_CUR_DESC: /* Transmit Current Descriptor */ + value = s->tx_desc_curr; + break; + case REG_TX_CUR_BUF: /* Transmit Current Buffer */ + if (s->tx_desc_curr != 0) { + cpu_physical_memory_read(s->tx_desc_curr, &desc, sizeof(desc)); + value = desc.addr; + } else { + value = 0; + } + break; + case REG_RX_DMA_STA: /* Receive DMA Status */ + break; + case REG_RX_CUR_DESC: /* Receive Current Descriptor */ + value = s->rx_desc_curr; + break; + case REG_RX_CUR_BUF: /* Receive Current Buffer */ + if (s->rx_desc_curr != 0) { + cpu_physical_memory_read(s->rx_desc_curr, &desc, sizeof(desc)); + value = desc.addr; + } else { + value = 0; + } + break; + default: + qemu_log_mask(LOG_UNIMP, "allwinner-h3-emac: read access to unknown " + "EMAC register 0x" TARGET_FMT_plx "\n", + offset); + } + + trace_aw_h3_emac_read(offset, value); + return value; +} + +static void aw_h3_emac_write(void *opaque, hwaddr offset, uint64_t value, + unsigned size) +{ + AwH3EmacState *s = AW_H3_EMAC(opaque); + NetClientState *nc = qemu_get_queue(s->nic); + + trace_aw_h3_emac_write(offset, value); + + switch (offset) { + case REG_BASIC_CTL_0: /* Basic Control 0 */ + s->basic_ctl0 = value; + break; + case REG_BASIC_CTL_1: /* Basic Control 1 */ + if (value & BASIC_CTL1_SOFTRST) { + aw_h3_emac_reset(DEVICE(s)); + value &= ~BASIC_CTL1_SOFTRST; + } + s->basic_ctl1 = value; + if (aw_h3_emac_can_receive(nc)) { + qemu_flush_queued_packets(nc); + } + break; + case REG_INT_STA: /* Interrupt Status */ + s->int_sta &= ~value; + aw_h3_emac_update_irq(s); + break; + case REG_INT_EN: /* Interrupt Enable */ + s->int_en = value; + aw_h3_emac_update_irq(s); + break; + case REG_TX_CTL_0: /* Transmit Control 0 */ + s->tx_ctl0 = value; + break; + case REG_TX_CTL_1: /* Transmit Control 1 */ + s->tx_ctl1 = value; + if (value & TX_CTL1_TX_DMA_EN) { + aw_h3_emac_transmit(s); + } + break; + case REG_TX_FLOW_CTL: /* Transmit Flow Control */ + s->tx_flowctl = value; + break; + case REG_TX_DMA_DESC_LIST: /* Transmit Descriptor List Address */ + s->tx_desc_head = value; + s->tx_desc_curr = value; + break; + case REG_RX_CTL_0: /* Receive Control 0 */ + s->rx_ctl0 = value; + break; + case REG_RX_CTL_1: /* Receive Control 1 */ + s->rx_ctl1 = value | RX_CTL1_RX_MD; + if ((value & RX_CTL1_RX_DMA_EN) && aw_h3_emac_can_receive(nc)) { + qemu_flush_queued_packets(nc); + } + break; + case REG_RX_DMA_DESC_LIST: /* Receive Descriptor List Address */ + s->rx_desc_head = value; + s->rx_desc_curr = value; + break; + case REG_FRM_FLT: /* Receive Frame Filter */ + s->frm_flt = value; + break; + case REG_RX_HASH_0: /* Receive Hash Table 0 */ + case REG_RX_HASH_1: /* Receive Hash Table 1 */ + break; + case REG_MII_CMD: /* Management Interface Command */ + s->mii_cmd = value & ~MII_CMD_PHY_BUSY; + aw_h3_emac_mii_cmd(s); + break; + case REG_MII_DATA: /* Management Interface Data */ + s->mii_data = value; + break; + case REG_ADDR_HIGH: /* MAC Address High */ + s->conf.macaddr.a[4] = (value & 0xff); + s->conf.macaddr.a[5] = (value & 0xff00) >> 8; + break; + case REG_ADDR_LOW: /* MAC Address Low */ + s->conf.macaddr.a[0] = (value & 0xff); + s->conf.macaddr.a[1] = (value & 0xff00) >> 8; + s->conf.macaddr.a[2] = (value & 0xff0000) >> 16; + s->conf.macaddr.a[3] = (value & 0xff000000) >> 24; + break; + case REG_TX_DMA_STA: /* Transmit DMA Status */ + case REG_TX_CUR_DESC: /* Transmit Current Descriptor */ + case REG_TX_CUR_BUF: /* Transmit Current Buffer */ + case REG_RX_DMA_STA: /* Receive DMA Status */ + case REG_RX_CUR_DESC: /* Receive Current Descriptor */ + case REG_RX_CUR_BUF: /* Receive Current Buffer */ + case REG_RGMII_STA: /* RGMII Status */ + break; + default: + qemu_log_mask(LOG_UNIMP, "allwinner-h3-emac: write access to unknown " + "EMAC register 0x" TARGET_FMT_plx "\n", + offset); + } +} + +static void aw_h3_emac_set_link(NetClientState *nc) +{ + AwH3EmacState *s = qemu_get_nic_opaque(nc); + + trace_aw_h3_emac_set_link(!nc->link_down); + aw_h3_emac_mii_set_link(s, !nc->link_down); +} + +static const MemoryRegionOps aw_h3_emac_mem_ops = { + .read = aw_h3_emac_read, + .write = aw_h3_emac_write, + .endianness = DEVICE_NATIVE_ENDIAN, + .valid = { + .min_access_size = 4, + .max_access_size = 4, + .unaligned = false, + }, + .impl.min_access_size = 4, +}; + +static NetClientInfo net_aw_h3_emac_info = { + .type = NET_CLIENT_DRIVER_NIC, + .size = sizeof(NICState), + .can_receive = aw_h3_emac_can_receive, + .receive = aw_h3_emac_receive, + .link_status_changed = aw_h3_emac_set_link, +}; + +static void aw_h3_emac_init(Object *obj) +{ + SysBusDevice *sbd = SYS_BUS_DEVICE(obj); + AwH3EmacState *s = AW_H3_EMAC(obj); + + memory_region_init_io(&s->iomem, OBJECT(s), &aw_h3_emac_mem_ops, s, + TYPE_AW_H3_EMAC, 64 * KiB); + sysbus_init_mmio(sbd, &s->iomem); + sysbus_init_irq(sbd, &s->irq); +} + +static void aw_h3_emac_realize(DeviceState *dev, Error **errp) +{ + AwH3EmacState *s = AW_H3_EMAC(dev); + + qemu_macaddr_default_if_unset(&s->conf.macaddr); + s->nic = qemu_new_nic(&net_aw_h3_emac_info, &s->conf, + object_get_typename(OBJECT(dev)), dev->id, s); + qemu_format_nic_info_str(qemu_get_queue(s->nic), s->conf.macaddr.a); +} + +static Property aw_h3_emac_properties[] = { + DEFINE_NIC_PROPERTIES(AwH3EmacState, conf), + DEFINE_PROP_UINT8("phy-addr", AwH3EmacState, mii_phy_addr, 0), + DEFINE_PROP_END_OF_LIST(), +}; + +static int aw_h3_emac_post_load(void *opaque, int version_id) +{ + AwH3EmacState *s = opaque; + + aw_h3_emac_set_link(qemu_get_queue(s->nic)); + + return 0; +} + +static const VMStateDescription vmstate_aw_emac = { + .name = "allwinner-h3-emac", + .version_id = 1, + .minimum_version_id = 1, + .post_load = aw_h3_emac_post_load, + .fields = (VMStateField[]) { + VMSTATE_UINT8(mii_phy_addr, AwH3EmacState), + VMSTATE_UINT32(mii_cmd, AwH3EmacState), + VMSTATE_UINT32(mii_data, AwH3EmacState), + VMSTATE_UINT32(basic_ctl0, AwH3EmacState), + VMSTATE_UINT32(basic_ctl1, AwH3EmacState), + VMSTATE_UINT32(int_en, AwH3EmacState), + VMSTATE_UINT32(int_sta, AwH3EmacState), + VMSTATE_UINT32(frm_flt, AwH3EmacState), + VMSTATE_UINT32(rx_ctl0, AwH3EmacState), + VMSTATE_UINT32(rx_ctl1, AwH3EmacState), + VMSTATE_UINT32(rx_desc_head, AwH3EmacState), + VMSTATE_UINT32(rx_desc_curr, AwH3EmacState), + VMSTATE_UINT32(tx_ctl0, AwH3EmacState), + VMSTATE_UINT32(tx_ctl1, AwH3EmacState), + VMSTATE_UINT32(tx_desc_head, AwH3EmacState), + VMSTATE_UINT32(tx_desc_curr, AwH3EmacState), + VMSTATE_UINT32(tx_flowctl, AwH3EmacState), + VMSTATE_END_OF_LIST() + } +}; + +static void aw_h3_emac_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + + dc->realize = aw_h3_emac_realize; + dc->props = aw_h3_emac_properties; + dc->reset = aw_h3_emac_reset; + dc->vmsd = &vmstate_aw_emac; +} + +static const TypeInfo aw_h3_emac_info = { + .name = TYPE_AW_H3_EMAC, + .parent = TYPE_SYS_BUS_DEVICE, + .instance_size = sizeof(AwH3EmacState), + .instance_init = aw_h3_emac_init, + .class_init = aw_h3_emac_class_init, +}; + +static void aw_h3_emac_register_types(void) +{ + type_register_static(&aw_h3_emac_info); +} + +type_init(aw_h3_emac_register_types) diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig index ebf8d2325f..551cff3442 100644 --- a/hw/arm/Kconfig +++ b/hw/arm/Kconfig @@ -294,6 +294,7 @@ config ALLWINNER_A10 config ALLWINNER_H3 bool select ALLWINNER_A10_PIT + select ALLWINNER_H3_EMAC select SERIAL select ARM_TIMER select ARM_GIC diff --git a/hw/net/Kconfig b/hw/net/Kconfig index 3856417d42..36d3923992 100644 --- a/hw/net/Kconfig +++ b/hw/net/Kconfig @@ -74,6 +74,9 @@ config MIPSNET config ALLWINNER_EMAC bool +config ALLWINNER_H3_EMAC + bool + config IMX_FEC bool diff --git a/hw/net/Makefile.objs b/hw/net/Makefile.objs index 7907d2c199..5548deb07a 100644 --- a/hw/net/Makefile.objs +++ b/hw/net/Makefile.objs @@ -23,6 +23,7 @@ common-obj-$(CONFIG_XGMAC) += xgmac.o common-obj-$(CONFIG_MIPSNET) += mipsnet.o common-obj-$(CONFIG_XILINX_AXI) += xilinx_axienet.o common-obj-$(CONFIG_ALLWINNER_EMAC) += allwinner_emac.o +common-obj-$(CONFIG_ALLWINNER_H3_EMAC) += allwinner-h3-emac.o common-obj-$(CONFIG_IMX_FEC) += imx_fec.o common-obj-$(CONFIG_CADENCE) += cadence_gem.o diff --git a/hw/net/trace-events b/hw/net/trace-events index e70f12bee1..b972c53f75 100644 --- a/hw/net/trace-events +++ b/hw/net/trace-events @@ -1,5 +1,15 @@ # See docs/devel/tracing.txt for syntax documentation. +# allwinner-h3-emac.c +aw_h3_emac_mii_write_reg(uint32_t reg, uint32_t value) "MII write: reg=0x%" PRIx32 " value=0x%" PRIx32 +aw_h3_emac_mii_read_reg(uint32_t reg, uint32_t value) "MII read: reg=0x%" PRIx32 " value=0x%" PRIx32 +aw_h3_emac_receive(uint32_t desc, uint32_t paddr, uint32_t bytes) "RX packet: desc=0x%" PRIx32 " paddr=0x%" PRIx32 " bytes=%" PRIu32 +aw_h3_emac_transmit(uint32_t desc, uint32_t paddr, uint32_t bytes) "TX packet: desc=0x%" PRIx32 " paddr=0x%" PRIx32 " bytes=%" PRIu32 +aw_h3_emac_reset(void) "HW reset" +aw_h3_emac_set_link(bool active) "Set link: active=%u" +aw_h3_emac_read(uint64_t offset, uint64_t val) "MMIO read: offset=0x%" PRIx64 " value=0x%" PRIx64 +aw_h3_emac_write(uint64_t offset, uint64_t val) "MMIO write: offset=0x%" PRIx64 " value=0x%" PRIx64 + # etraxfs_eth.c mdio_phy_read(int regnum, uint16_t value) "read phy_reg:%d value:0x%04x" mdio_phy_write(int regnum, uint16_t value) "write phy_reg:%d value:0x%04x" -- 2.17.1 From MAILER-DAEMON Mon Dec 16 18:36:23 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1igzuZ-00078k-MS for mharc-qemu-arm@gnu.org; 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Mon, 16 Dec 2019 15:36:02 -0800 (PST) From: Niek Linnenbank To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, peter.maydell@linaro.org, philmd@redhat.com, Niek Linnenbank Subject: [PATCH v2 09/10] arm: allwinner-h3: add SD/MMC host controller Date: Tue, 17 Dec 2019 00:35:18 +0100 Message-Id: <20191216233519.29030-10-nieklinnenbank@gmail.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20191216233519.29030-1-nieklinnenbank@gmail.com> References: <20191216233519.29030-1-nieklinnenbank@gmail.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::42d X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 16 Dec 2019 23:36:22 -0000 The Allwinner H3 System on Chip contains an integrated storage controller for Secure Digital (SD) and Multi Media Card (MMC) interfaces. This commit adds support for the Allwinner H3 SD/MMC storage controller with the following emulated features: * DMA transfers * Direct FIFO I/O * Short/Long format command responses * Auto-Stop command (CMD12) * Insert & remove card detection Signed-off-by: Niek Linnenbank --- include/hw/arm/allwinner-h3.h | 2 + include/hw/sd/allwinner-h3-sdhost.h | 71 +++ hw/arm/allwinner-h3.c | 16 + hw/arm/orangepi.c | 15 + hw/sd/allwinner-h3-sdhost.c | 813 ++++++++++++++++++++++++++++ hw/sd/Makefile.objs | 1 + hw/sd/trace-events | 7 + 7 files changed, 925 insertions(+) create mode 100644 include/hw/sd/allwinner-h3-sdhost.h create mode 100644 hw/sd/allwinner-h3-sdhost.c diff --git a/include/hw/arm/allwinner-h3.h b/include/hw/arm/allwinner-h3.h index c98c1972a6..ab564987be 100644 --- a/include/hw/arm/allwinner-h3.h +++ b/include/hw/arm/allwinner-h3.h @@ -30,6 +30,7 @@ #include "hw/misc/allwinner-h3-cpucfg.h" #include "hw/misc/allwinner-h3-syscon.h" #include "hw/misc/allwinner-h3-sid.h" +#include "hw/sd/allwinner-h3-sdhost.h" #include "target/arm/cpu.h" enum { @@ -79,6 +80,7 @@ typedef struct AwH3State { AwH3CpuCfgState cpucfg; AwH3SysconState syscon; AwH3SidState sid; + AwH3SDHostState mmc0; GICState gic; MemoryRegion sram_a1; MemoryRegion sram_a2; diff --git a/include/hw/sd/allwinner-h3-sdhost.h b/include/hw/sd/allwinner-h3-sdhost.h new file mode 100644 index 0000000000..4a93405e6c --- /dev/null +++ b/include/hw/sd/allwinner-h3-sdhost.h @@ -0,0 +1,71 @@ +/* + * Allwinner H3 SD Host Controller emulation + * + * Copyright (C) 2019 Niek Linnenbank + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#ifndef ALLWINNER_H3_SDHOST_H +#define ALLWINNER_H3_SDHOST_H + +#include "hw/sysbus.h" +#include "hw/sd/sd.h" + +#define TYPE_AW_H3_SDHOST "allwinner-h3-sdhost" +#define AW_H3_SDHOST(obj) \ + OBJECT_CHECK(AwH3SDHostState, (obj), TYPE_AW_H3_SDHOST) + +typedef struct { + SysBusDevice busdev; + SDBus sdbus; + MemoryRegion iomem; + + uint32_t global_ctl; + uint32_t clock_ctl; + uint32_t timeout; + uint32_t bus_width; + uint32_t block_size; + uint32_t byte_count; + uint32_t transfer_cnt; + + uint32_t command; + uint32_t command_arg; + uint32_t response[4]; + + uint32_t irq_mask; + uint32_t irq_status; + uint32_t status; + + uint32_t fifo_wlevel; + uint32_t fifo_func_sel; + uint32_t debug_enable; + uint32_t auto12_arg; + uint32_t newtiming_set; + uint32_t newtiming_debug; + uint32_t hardware_rst; + uint32_t dmac; + uint32_t desc_base; + uint32_t dmac_status; + uint32_t dmac_irq; + uint32_t card_threshold; + uint32_t startbit_detect; + uint32_t response_crc; + uint32_t data_crc[8]; + uint32_t status_crc; + + qemu_irq irq; +} AwH3SDHostState; + +#endif diff --git a/hw/arm/allwinner-h3.c b/hw/arm/allwinner-h3.c index ba34f905cd..b4ee524ee0 100644 --- a/hw/arm/allwinner-h3.c +++ b/hw/arm/allwinner-h3.c @@ -199,6 +199,9 @@ static void aw_h3_init(Object *obj) sysbus_init_child_obj(obj, "sid", &s->sid, sizeof(s->sid), TYPE_AW_H3_SID); + + sysbus_init_child_obj(obj, "mmc0", &s->mmc0, sizeof(s->mmc0), + TYPE_AW_H3_SDHOST); } static void aw_h3_realize(DeviceState *dev, Error **errp) @@ -339,6 +342,19 @@ static void aw_h3_realize(DeviceState *dev, Error **errp) qdev_init_nofail(DEVICE(&s->sid)); sysbus_mmio_map(SYS_BUS_DEVICE(&s->sid), 0, s->memmap[AW_H3_SID]); + /* SD/MMC */ + qdev_init_nofail(DEVICE(&s->mmc0)); + sysbus_mmio_map(SYS_BUS_DEVICE(&s->mmc0), 0, s->memmap[AW_H3_MMC0]); + sysbus_connect_irq(SYS_BUS_DEVICE(&s->mmc0), 0, + qdev_get_gpio_in(DEVICE(&s->gic), AW_H3_GIC_SPI_MMC0)); + + object_property_add_alias(OBJECT(s), "sd-bus", OBJECT(&s->mmc0), + "sd-bus", &error_abort); + if (error_abort) { + error_propagate(errp, error_abort); + return; + } + /* Universal Serial Bus */ sysbus_create_simple(TYPE_AW_H3_EHCI, s->memmap[AW_H3_EHCI0], qdev_get_gpio_in(DEVICE(&s->gic), diff --git a/hw/arm/orangepi.c b/hw/arm/orangepi.c index b01c4b4f01..87968505ae 100644 --- a/hw/arm/orangepi.c +++ b/hw/arm/orangepi.c @@ -38,6 +38,10 @@ typedef struct OrangePiState { static void orangepi_init(MachineState *machine) { OrangePiState *s = g_new(OrangePiState, 1); + DriveInfo *di; + BlockBackend *blk; + BusState *bus; + DeviceState *carddev; /* Only allow Cortex-A7 for this board */ if (strcmp(machine->cpu_type, ARM_CPU_TYPE_NAME("cortex-a7")) != 0) { @@ -73,6 +77,16 @@ static void orangepi_init(MachineState *machine) exit(1); } + /* Retrieve SD bus */ + di = drive_get_next(IF_SD); + blk = di ? blk_by_legacy_dinfo(di) : NULL; + bus = qdev_get_child_bus(DEVICE(s->h3), "sd-bus"); + + /* Plug in SD card */ + carddev = qdev_create(bus, TYPE_SD_CARD); + qdev_prop_set_drive(carddev, "drive", blk, &error_fatal); + object_property_set_bool(OBJECT(carddev), true, "realized", &error_fatal); + /* RAM */ if (machine->ram_size > 1 * GiB) { error_report("Requested ram size is too large for this machine: " @@ -95,6 +109,7 @@ static void orangepi_machine_init(MachineClass *mc) { mc->desc = "Orange Pi PC"; mc->init = orangepi_init; + mc->block_default_type = IF_SD; mc->units_per_default_bus = 1; mc->min_cpus = AW_H3_NUM_CPUS; mc->max_cpus = AW_H3_NUM_CPUS; diff --git a/hw/sd/allwinner-h3-sdhost.c b/hw/sd/allwinner-h3-sdhost.c new file mode 100644 index 0000000000..c6661af614 --- /dev/null +++ b/hw/sd/allwinner-h3-sdhost.c @@ -0,0 +1,813 @@ +/* + * Allwinner H3 SD Host Controller emulation + * + * Copyright (C) 2019 Niek Linnenbank + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#include "qemu/osdep.h" +#include "qemu/log.h" +#include "qemu/module.h" +#include "qemu/units.h" +#include "sysemu/blockdev.h" +#include "hw/irq.h" +#include "hw/sd/allwinner-h3-sdhost.h" +#include "migration/vmstate.h" +#include "trace.h" + +#define TYPE_AW_H3_SDHOST_BUS "allwinner-h3-sdhost-bus" +#define AW_H3_SDHOST_BUS(obj) \ + OBJECT_CHECK(SDBus, (obj), TYPE_AW_H3_SDHOST_BUS) + +/* SD Host register offsets */ +enum { + REG_SD_GCTL = 0x00, /* Global Control */ + REG_SD_CKCR = 0x04, /* Clock Control */ + REG_SD_TMOR = 0x08, /* Timeout */ + REG_SD_BWDR = 0x0C, /* Bus Width */ + REG_SD_BKSR = 0x10, /* Block Size */ + REG_SD_BYCR = 0x14, /* Byte Count */ + REG_SD_CMDR = 0x18, /* Command */ + REG_SD_CAGR = 0x1C, /* Command Argument */ + REG_SD_RESP0 = 0x20, /* Response Zero */ + REG_SD_RESP1 = 0x24, /* Response One */ + REG_SD_RESP2 = 0x28, /* Response Two */ + REG_SD_RESP3 = 0x2C, /* Response Three */ + REG_SD_IMKR = 0x30, /* Interrupt Mask */ + REG_SD_MISR = 0x34, /* Masked Interrupt Status */ + REG_SD_RISR = 0x38, /* Raw Interrupt Status */ + REG_SD_STAR = 0x3C, /* Status */ + REG_SD_FWLR = 0x40, /* FIFO Water Level */ + REG_SD_FUNS = 0x44, /* FIFO Function Select */ + REG_SD_DBGC = 0x50, /* Debug Enable */ + REG_SD_A12A = 0x58, /* Auto command 12 argument */ + REG_SD_NTSR = 0x5C, /* SD NewTiming Set */ + REG_SD_SDBG = 0x60, /* SD newTiming Set Debug */ + REG_SD_HWRST = 0x78, /* Hardware Reset Register */ + REG_SD_DMAC = 0x80, /* Internal DMA Controller Control */ + REG_SD_DLBA = 0x84, /* Descriptor List Base Address */ + REG_SD_IDST = 0x88, /* Internal DMA Controller Status */ + REG_SD_IDIE = 0x8C, /* Internal DMA Controller IRQ Enable */ + REG_SD_THLDC = 0x100, /* Card Threshold Control */ + REG_SD_DSBD = 0x10C, /* eMMC DDR Start Bit Detection Control */ + REG_SD_RES_CRC = 0x110, /* Response CRC from card/eMMC */ + REG_SD_DATA7_CRC = 0x114, /* CRC Data 7 from card/eMMC */ + REG_SD_DATA6_CRC = 0x118, /* CRC Data 6 from card/eMMC */ + REG_SD_DATA5_CRC = 0x11C, /* CRC Data 5 from card/eMMC */ + REG_SD_DATA4_CRC = 0x120, /* CRC Data 4 from card/eMMC */ + REG_SD_DATA3_CRC = 0x124, /* CRC Data 3 from card/eMMC */ + REG_SD_DATA2_CRC = 0x128, /* CRC Data 2 from card/eMMC */ + REG_SD_DATA1_CRC = 0x12C, /* CRC Data 1 from card/eMMC */ + REG_SD_DATA0_CRC = 0x130, /* CRC Data 0 from card/eMMC */ + REG_SD_CRC_STA = 0x134, /* CRC status from card/eMMC during write */ + REG_SD_FIFO = 0x200, /* Read/Write FIFO */ +}; + +/* SD Host register flags */ +enum { + SD_GCTL_FIFO_AC_MOD = (1 << 31), + SD_GCTL_DDR_MOD_SEL = (1 << 10), + SD_GCTL_CD_DBC_ENB = (1 << 8), + SD_GCTL_DMA_ENB = (1 << 5), + SD_GCTL_INT_ENB = (1 << 4), + SD_GCTL_DMA_RST = (1 << 2), + SD_GCTL_FIFO_RST = (1 << 1), + SD_GCTL_SOFT_RST = (1 << 0), +}; + +enum { + SD_CMDR_LOAD = (1 << 31), + SD_CMDR_CLKCHANGE = (1 << 21), + SD_CMDR_WRITE = (1 << 10), + SD_CMDR_AUTOSTOP = (1 << 12), + SD_CMDR_DATA = (1 << 9), + SD_CMDR_RESPONSE_LONG = (1 << 7), + SD_CMDR_RESPONSE = (1 << 6), + SD_CMDR_CMDID_MASK = (0x3f), +}; + +enum { + SD_RISR_CARD_REMOVE = (1 << 31), + SD_RISR_CARD_INSERT = (1 << 30), + SD_RISR_AUTOCMD_DONE = (1 << 14), + SD_RISR_DATA_COMPLETE = (1 << 3), + SD_RISR_CMD_COMPLETE = (1 << 2), + SD_RISR_NO_RESPONSE = (1 << 1), +}; + +enum { + SD_STAR_CARD_PRESENT = (1 << 8), +}; + +enum { + SD_IDST_SUM_RECEIVE_IRQ = (1 << 8), + SD_IDST_RECEIVE_IRQ = (1 << 1), + SD_IDST_TRANSMIT_IRQ = (1 << 0), + SD_IDST_IRQ_MASK = (1 << 1) | (1 << 0) | (1 << 8), + SD_IDST_WR_MASK = (0x3ff), +}; + +/* SD Host register reset values */ +enum { + REG_SD_GCTL_RST = 0x00000300, + REG_SD_CKCR_RST = 0x0, + REG_SD_TMOR_RST = 0xFFFFFF40, + REG_SD_BWDR_RST = 0x0, + REG_SD_BKSR_RST = 0x00000200, + REG_SD_BYCR_RST = 0x00000200, + REG_SD_CMDR_RST = 0x0, + REG_SD_CAGR_RST = 0x0, + REG_SD_RESP_RST = 0x0, + REG_SD_IMKR_RST = 0x0, + REG_SD_MISR_RST = 0x0, + REG_SD_RISR_RST = 0x0, + REG_SD_STAR_RST = 0x00000100, + REG_SD_FWLR_RST = 0x000F0000, + REG_SD_FUNS_RST = 0x0, + REG_SD_DBGC_RST = 0x0, + REG_SD_A12A_RST = 0x0000FFFF, + REG_SD_NTSR_RST = 0x00000001, + REG_SD_SDBG_RST = 0x0, + REG_SD_HWRST_RST = 0x00000001, + REG_SD_DMAC_RST = 0x0, + REG_SD_DLBA_RST = 0x0, + REG_SD_IDST_RST = 0x0, + REG_SD_IDIE_RST = 0x0, + REG_SD_THLDC_RST = 0x0, + REG_SD_DSBD_RST = 0x0, + REG_SD_RES_CRC_RST = 0x0, + REG_SD_DATA_CRC_RST = 0x0, + REG_SD_CRC_STA_RST = 0x0, + REG_SD_FIFO_RST = 0x0, +}; + +/* Data transfer descriptor for DMA */ +typedef struct TransferDescriptor { + uint32_t status; /* Status flags */ + uint32_t size; /* Data buffer size */ + uint32_t addr; /* Data buffer address */ + uint32_t next; /* Physical address of next descriptor */ +} TransferDescriptor; + +/* Data transfer descriptor flags */ +enum { + DESC_STATUS_HOLD = (1 << 31), /* Set when descriptor is in use by DMA */ + DESC_STATUS_ERROR = (1 << 30), /* Set when DMA transfer error occurred */ + DESC_STATUS_CHAIN = (1 << 4), /* Indicates chained descriptor. */ + DESC_STATUS_FIRST = (1 << 3), /* Set on the first descriptor */ + DESC_STATUS_LAST = (1 << 2), /* Set on the last descriptor */ + DESC_STATUS_NOIRQ = (1 << 1), /* Skip raising interrupt after transfer */ + DESC_SIZE_MASK = (0xfffffffc) +}; + +static void aw_h3_sdhost_update_irq(AwH3SDHostState *s) +{ + uint32_t irq; + + if (s->global_ctl & SD_GCTL_INT_ENB) { + irq = s->irq_status & s->irq_mask; + } else { + irq = 0; + } + + trace_aw_h3_sdhost_update_irq(irq); + qemu_set_irq(s->irq, irq); +} + +static void aw_h3_sdhost_update_transfer_cnt(AwH3SDHostState *s, uint32_t bytes) +{ + if (s->transfer_cnt > bytes) { + s->transfer_cnt -= bytes; + } else { + s->transfer_cnt = 0; + } + + if (!s->transfer_cnt) { + s->irq_status |= SD_RISR_DATA_COMPLETE | SD_RISR_AUTOCMD_DONE; + } +} + +static void aw_h3_sdhost_set_inserted(DeviceState *dev, bool inserted) +{ + AwH3SDHostState *s = AW_H3_SDHOST(dev); + + trace_aw_h3_sdhost_set_inserted(inserted); + + if (inserted) { + s->irq_status |= SD_RISR_CARD_INSERT; + s->irq_status &= ~SD_RISR_CARD_REMOVE; + s->status |= SD_STAR_CARD_PRESENT; + } else { + s->irq_status &= ~SD_RISR_CARD_INSERT; + s->irq_status |= SD_RISR_CARD_REMOVE; + s->status &= ~SD_STAR_CARD_PRESENT; + } + + aw_h3_sdhost_update_irq(s); +} + +static void aw_h3_sdhost_send_command(AwH3SDHostState *s) +{ + SDRequest request; + uint8_t resp[16]; + int rlen; + + /* Auto clear load flag */ + s->command &= ~SD_CMDR_LOAD; + + /* Clock change does not actually interact with the SD bus */ + if (!(s->command & SD_CMDR_CLKCHANGE)) { + + /* Prepare request */ + request.cmd = s->command & SD_CMDR_CMDID_MASK; + request.arg = s->command_arg; + + /* Send request to SD bus */ + rlen = sdbus_do_command(&s->sdbus, &request, resp); + if (rlen < 0) { + goto error; + } + + /* If the command has a response, store it in the response registers */ + if ((s->command & SD_CMDR_RESPONSE)) { + if (rlen == 4 && !(s->command & SD_CMDR_RESPONSE_LONG)) { + s->response[0] = ldl_be_p(&resp[0]); + s->response[1] = s->response[2] = s->response[3] = 0; + + } else if (rlen == 16 && (s->command & SD_CMDR_RESPONSE_LONG)) { + s->response[0] = ldl_be_p(&resp[12]); + s->response[1] = ldl_be_p(&resp[8]); + s->response[2] = ldl_be_p(&resp[4]); + s->response[3] = ldl_be_p(&resp[0]); + } else { + goto error; + } + } + } + + /* Set interrupt status bits */ + s->irq_status |= SD_RISR_CMD_COMPLETE; + return; + +error: + s->irq_status |= SD_RISR_NO_RESPONSE; +} + +static void aw_h3_sdhost_auto_stop(AwH3SDHostState *s) +{ + /* + * The stop command (CMD12) ensures the SD bus + * returns to the transfer state. + */ + if ((s->command & SD_CMDR_AUTOSTOP) && (s->transfer_cnt == 0)) { + /* First save current command registers */ + uint32_t saved_cmd = s->command; + uint32_t saved_arg = s->command_arg; + + /* Prepare stop command (CMD12) */ + s->command &= ~SD_CMDR_CMDID_MASK; + s->command |= 12; /* CMD12 */ + s->command_arg = 0; + + /* Put the command on SD bus */ + aw_h3_sdhost_send_command(s); + + /* Restore command values */ + s->command = saved_cmd; + s->command_arg = saved_arg; + } +} + +static uint32_t aw_h3_sdhost_process_desc(AwH3SDHostState *s, + hwaddr desc_addr, + TransferDescriptor *desc, + bool is_write, uint32_t max_bytes) +{ + uint32_t num_done = 0; + uint32_t num_bytes = max_bytes; + uint8_t buf[1024]; + + /* Read descriptor */ + cpu_physical_memory_read(desc_addr, desc, sizeof(*desc)); + if (desc->size == 0) { + desc->size = 64 * KiB; + } + if (desc->size < num_bytes) { + num_bytes = desc->size; + } + + trace_aw_h3_sdhost_process_desc(desc_addr, desc->size, is_write, max_bytes); + + while (num_done < num_bytes) { + /* Try to completely fill the local buffer */ + uint32_t buf_bytes = num_bytes - num_done; + if (buf_bytes > sizeof(buf)) { + buf_bytes = sizeof(buf); + } + + /* Write to SD bus */ + if (is_write) { + cpu_physical_memory_read((desc->addr & DESC_SIZE_MASK) + num_done, + buf, buf_bytes); + + for (uint32_t i = 0; i < buf_bytes; i++) { + sdbus_write_data(&s->sdbus, buf[i]); + } + + /* Read from SD bus */ + } else { + for (uint32_t i = 0; i < buf_bytes; i++) { + buf[i] = sdbus_read_data(&s->sdbus); + } + cpu_physical_memory_write((desc->addr & DESC_SIZE_MASK) + num_done, + buf, buf_bytes); + } + num_done += buf_bytes; + } + + /* Clear hold flag and flush descriptor */ + desc->status &= ~DESC_STATUS_HOLD; + cpu_physical_memory_write(desc_addr, desc, sizeof(*desc)); + + return num_done; +} + +static void aw_h3_sdhost_dma(AwH3SDHostState *s) +{ + TransferDescriptor desc; + hwaddr desc_addr = s->desc_base; + bool is_write = (s->command & SD_CMDR_WRITE); + uint32_t bytes_done = 0; + + /* Check if DMA can be performed */ + if (s->byte_count == 0 || s->block_size == 0 || + !(s->global_ctl & SD_GCTL_DMA_ENB)) { + return; + } + + /* + * For read operations, data must be available on the SD bus + * If not, it is an error and we should not act at all + */ + if (!is_write && !sdbus_data_ready(&s->sdbus)) { + return; + } + + /* Process the DMA descriptors until all data is copied */ + while (s->byte_count > 0) { + bytes_done = aw_h3_sdhost_process_desc(s, desc_addr, &desc, + is_write, s->byte_count); + aw_h3_sdhost_update_transfer_cnt(s, bytes_done); + + if (bytes_done <= s->byte_count) { + s->byte_count -= bytes_done; + } else { + s->byte_count = 0; + } + + if (desc.status & DESC_STATUS_LAST) { + break; + } else { + desc_addr = desc.next; + } + } + + /* Raise IRQ to signal DMA is completed */ + s->irq_status |= SD_RISR_DATA_COMPLETE | SD_RISR_AUTOCMD_DONE; + + /* Update DMAC bits */ + if (is_write) { + s->dmac_status |= SD_IDST_TRANSMIT_IRQ; + } else { + s->dmac_status |= (SD_IDST_SUM_RECEIVE_IRQ | SD_IDST_RECEIVE_IRQ); + } +} + +static uint64_t aw_h3_sdhost_read(void *opaque, hwaddr offset, + unsigned size) +{ + AwH3SDHostState *s = (AwH3SDHostState *)opaque; + uint32_t res = 0; + + switch (offset) { + case REG_SD_GCTL: /* Global Control */ + res = s->global_ctl; + break; + case REG_SD_CKCR: /* Clock Control */ + res = s->clock_ctl; + break; + case REG_SD_TMOR: /* Timeout */ + res = s->timeout; + break; + case REG_SD_BWDR: /* Bus Width */ + res = s->bus_width; + break; + case REG_SD_BKSR: /* Block Size */ + res = s->block_size; + break; + case REG_SD_BYCR: /* Byte Count */ + res = s->byte_count; + break; + case REG_SD_CMDR: /* Command */ + res = s->command; + break; + case REG_SD_CAGR: /* Command Argument */ + res = s->command_arg; + break; + case REG_SD_RESP0: /* Response Zero */ + res = s->response[0]; + break; + case REG_SD_RESP1: /* Response One */ + res = s->response[1]; + break; + case REG_SD_RESP2: /* Response Two */ + res = s->response[2]; + break; + case REG_SD_RESP3: /* Response Three */ + res = s->response[3]; + break; + case REG_SD_IMKR: /* Interrupt Mask */ + res = s->irq_mask; + break; + case REG_SD_MISR: /* Masked Interrupt Status */ + res = s->irq_status & s->irq_mask; + break; + case REG_SD_RISR: /* Raw Interrupt Status */ + res = s->irq_status; + break; + case REG_SD_STAR: /* Status */ + res = s->status; + break; + case REG_SD_FWLR: /* FIFO Water Level */ + res = s->fifo_wlevel; + break; + case REG_SD_FUNS: /* FIFO Function Select */ + res = s->fifo_func_sel; + break; + case REG_SD_DBGC: /* Debug Enable */ + res = s->debug_enable; + break; + case REG_SD_A12A: /* Auto command 12 argument */ + res = s->auto12_arg; + break; + case REG_SD_NTSR: /* SD NewTiming Set */ + res = s->newtiming_set; + break; + case REG_SD_SDBG: /* SD newTiming Set Debug */ + res = s->newtiming_debug; + break; + case REG_SD_HWRST: /* Hardware Reset Register */ + res = s->hardware_rst; + break; + case REG_SD_DMAC: /* Internal DMA Controller Control */ + res = s->dmac; + break; + case REG_SD_DLBA: /* Descriptor List Base Address */ + res = s->desc_base; + break; + case REG_SD_IDST: /* Internal DMA Controller Status */ + res = s->dmac_status; + break; + case REG_SD_IDIE: /* Internal DMA Controller Interrupt Enable */ + res = s->dmac_irq; + break; + case REG_SD_THLDC: /* Card Threshold Control */ + res = s->card_threshold; + break; + case REG_SD_DSBD: /* eMMC DDR Start Bit Detection Control */ + res = s->startbit_detect; + break; + case REG_SD_RES_CRC: /* Response CRC from card/eMMC */ + res = s->response_crc; + break; + case REG_SD_DATA7_CRC: /* CRC Data 7 from card/eMMC */ + case REG_SD_DATA6_CRC: /* CRC Data 6 from card/eMMC */ + case REG_SD_DATA5_CRC: /* CRC Data 5 from card/eMMC */ + case REG_SD_DATA4_CRC: /* CRC Data 4 from card/eMMC */ + case REG_SD_DATA3_CRC: /* CRC Data 3 from card/eMMC */ + case REG_SD_DATA2_CRC: /* CRC Data 2 from card/eMMC */ + case REG_SD_DATA1_CRC: /* CRC Data 1 from card/eMMC */ + case REG_SD_DATA0_CRC: /* CRC Data 0 from card/eMMC */ + res = s->data_crc[((offset - REG_SD_DATA7_CRC) / sizeof(uint32_t))]; + break; + case REG_SD_CRC_STA: /* CRC status from card/eMMC in write operation */ + res = s->status_crc; + break; + case REG_SD_FIFO: /* Read/Write FIFO */ + if (sdbus_data_ready(&s->sdbus)) { + res = sdbus_read_data(&s->sdbus); + res |= sdbus_read_data(&s->sdbus) << 8; + res |= sdbus_read_data(&s->sdbus) << 16; + res |= sdbus_read_data(&s->sdbus) << 24; + aw_h3_sdhost_update_transfer_cnt(s, sizeof(uint32_t)); + aw_h3_sdhost_auto_stop(s); + aw_h3_sdhost_update_irq(s); + } else { + qemu_log_mask(LOG_GUEST_ERROR, "%s: no data ready on SD bus\n", + __func__); + } + break; + default: + qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset %"HWADDR_PRIx"\n", + __func__, offset); + res = 0; + break; + } + + trace_aw_h3_sdhost_read(offset, res, size); + return res; +} + +static void aw_h3_sdhost_write(void *opaque, hwaddr offset, + uint64_t value, unsigned size) +{ + AwH3SDHostState *s = (AwH3SDHostState *)opaque; + + trace_aw_h3_sdhost_write(offset, value, size); + + switch (offset) { + case REG_SD_GCTL: /* Global Control */ + s->global_ctl = value; + s->global_ctl &= ~(SD_GCTL_DMA_RST | SD_GCTL_FIFO_RST | + SD_GCTL_SOFT_RST); + aw_h3_sdhost_update_irq(s); + break; + case REG_SD_CKCR: /* Clock Control */ + s->clock_ctl = value; + break; + case REG_SD_TMOR: /* Timeout */ + s->timeout = value; + break; + case REG_SD_BWDR: /* Bus Width */ + s->bus_width = value; + break; + case REG_SD_BKSR: /* Block Size */ + s->block_size = value; + break; + case REG_SD_BYCR: /* Byte Count */ + s->byte_count = value; + s->transfer_cnt = value; + break; + case REG_SD_CMDR: /* Command */ + s->command = value; + if (value & SD_CMDR_LOAD) { + aw_h3_sdhost_send_command(s); + aw_h3_sdhost_dma(s); + aw_h3_sdhost_auto_stop(s); + } + aw_h3_sdhost_update_irq(s); + break; + case REG_SD_CAGR: /* Command Argument */ + s->command_arg = value; + break; + case REG_SD_RESP0: /* Response Zero */ + s->response[0] = value; + break; + case REG_SD_RESP1: /* Response One */ + s->response[1] = value; + break; + case REG_SD_RESP2: /* Response Two */ + s->response[2] = value; + break; + case REG_SD_RESP3: /* Response Three */ + s->response[3] = value; + break; + case REG_SD_IMKR: /* Interrupt Mask */ + s->irq_mask = value; + aw_h3_sdhost_update_irq(s); + break; + case REG_SD_MISR: /* Masked Interrupt Status */ + case REG_SD_RISR: /* Raw Interrupt Status */ + s->irq_status &= ~value; + aw_h3_sdhost_update_irq(s); + break; + case REG_SD_STAR: /* Status */ + s->status &= ~value; + aw_h3_sdhost_update_irq(s); + break; + case REG_SD_FWLR: /* FIFO Water Level */ + s->fifo_wlevel = value; + break; + case REG_SD_FUNS: /* FIFO Function Select */ + s->fifo_func_sel = value; + break; + case REG_SD_DBGC: /* Debug Enable */ + s->debug_enable = value; + break; + case REG_SD_A12A: /* Auto command 12 argument */ + s->auto12_arg = value; + break; + case REG_SD_NTSR: /* SD NewTiming Set */ + s->newtiming_set = value; + break; + case REG_SD_SDBG: /* SD newTiming Set Debug */ + s->newtiming_debug = value; + break; + case REG_SD_HWRST: /* Hardware Reset Register */ + s->hardware_rst = value; + break; + case REG_SD_DMAC: /* Internal DMA Controller Control */ + s->dmac = value; + aw_h3_sdhost_update_irq(s); + break; + case REG_SD_DLBA: /* Descriptor List Base Address */ + s->desc_base = value; + break; + case REG_SD_IDST: /* Internal DMA Controller Status */ + s->dmac_status &= (~SD_IDST_WR_MASK) | (~value & SD_IDST_WR_MASK); + aw_h3_sdhost_update_irq(s); + break; + case REG_SD_IDIE: /* Internal DMA Controller Interrupt Enable */ + s->dmac_irq = value; + aw_h3_sdhost_update_irq(s); + break; + case REG_SD_THLDC: /* Card Threshold Control */ + s->card_threshold = value; + break; + case REG_SD_DSBD: /* eMMC DDR Start Bit Detection Control */ + s->startbit_detect = value; + break; + case REG_SD_FIFO: /* Read/Write FIFO */ + sdbus_write_data(&s->sdbus, value & 0xff); + sdbus_write_data(&s->sdbus, (value >> 8) & 0xff); + sdbus_write_data(&s->sdbus, (value >> 16) & 0xff); + sdbus_write_data(&s->sdbus, (value >> 24) & 0xff); + aw_h3_sdhost_update_transfer_cnt(s, sizeof(uint32_t)); + aw_h3_sdhost_auto_stop(s); + aw_h3_sdhost_update_irq(s); + break; + case REG_SD_RES_CRC: /* Response CRC from card/eMMC */ + case REG_SD_DATA7_CRC: /* CRC Data 7 from card/eMMC */ + case REG_SD_DATA6_CRC: /* CRC Data 6 from card/eMMC */ + case REG_SD_DATA5_CRC: /* CRC Data 5 from card/eMMC */ + case REG_SD_DATA4_CRC: /* CRC Data 4 from card/eMMC */ + case REG_SD_DATA3_CRC: /* CRC Data 3 from card/eMMC */ + case REG_SD_DATA2_CRC: /* CRC Data 2 from card/eMMC */ + case REG_SD_DATA1_CRC: /* CRC Data 1 from card/eMMC */ + case REG_SD_DATA0_CRC: /* CRC Data 0 from card/eMMC */ + case REG_SD_CRC_STA: /* CRC status from card/eMMC in write operation */ + break; + default: + qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset %"HWADDR_PRIx"\n", + __func__, offset); + break; + } +} + +static const MemoryRegionOps aw_h3_sdhost_ops = { + .read = aw_h3_sdhost_read, + .write = aw_h3_sdhost_write, + .endianness = DEVICE_NATIVE_ENDIAN, + .valid = { + .min_access_size = 4, + .max_access_size = 4, + .unaligned = false + }, + .impl.min_access_size = 4, +}; + +static const VMStateDescription vmstate_aw_h3_sdhost = { + .name = "allwinner-h3-sdhost", + .version_id = 1, + .minimum_version_id = 1, + .fields = (VMStateField[]) { + VMSTATE_UINT32(global_ctl, AwH3SDHostState), + VMSTATE_UINT32(clock_ctl, AwH3SDHostState), + VMSTATE_UINT32(timeout, AwH3SDHostState), + VMSTATE_UINT32(bus_width, AwH3SDHostState), + VMSTATE_UINT32(block_size, AwH3SDHostState), + VMSTATE_UINT32(byte_count, AwH3SDHostState), + VMSTATE_UINT32(transfer_cnt, AwH3SDHostState), + VMSTATE_UINT32(command, AwH3SDHostState), + VMSTATE_UINT32(command_arg, AwH3SDHostState), + VMSTATE_UINT32_ARRAY(response, AwH3SDHostState, 4), + VMSTATE_UINT32(irq_mask, AwH3SDHostState), + VMSTATE_UINT32(irq_status, AwH3SDHostState), + VMSTATE_UINT32(status, AwH3SDHostState), + VMSTATE_UINT32(fifo_wlevel, AwH3SDHostState), + VMSTATE_UINT32(fifo_func_sel, AwH3SDHostState), + VMSTATE_UINT32(debug_enable, AwH3SDHostState), + VMSTATE_UINT32(auto12_arg, AwH3SDHostState), + VMSTATE_UINT32(newtiming_set, AwH3SDHostState), + VMSTATE_UINT32(newtiming_debug, AwH3SDHostState), + VMSTATE_UINT32(hardware_rst, AwH3SDHostState), + VMSTATE_UINT32(dmac, AwH3SDHostState), + VMSTATE_UINT32(desc_base, AwH3SDHostState), + VMSTATE_UINT32(dmac_status, AwH3SDHostState), + VMSTATE_UINT32(dmac_irq, AwH3SDHostState), + VMSTATE_UINT32(card_threshold, AwH3SDHostState), + VMSTATE_UINT32(startbit_detect, AwH3SDHostState), + VMSTATE_UINT32(response_crc, AwH3SDHostState), + VMSTATE_UINT32_ARRAY(data_crc, AwH3SDHostState, 8), + VMSTATE_UINT32(status_crc, AwH3SDHostState), + VMSTATE_END_OF_LIST() + } +}; + +static void aw_h3_sdhost_init(Object *obj) +{ + AwH3SDHostState *s = AW_H3_SDHOST(obj); + + qbus_create_inplace(&s->sdbus, sizeof(s->sdbus), + TYPE_AW_H3_SDHOST_BUS, DEVICE(s), "sd-bus"); + + memory_region_init_io(&s->iomem, obj, &aw_h3_sdhost_ops, s, + TYPE_AW_H3_SDHOST, 4 * KiB); + sysbus_init_mmio(SYS_BUS_DEVICE(s), &s->iomem); + sysbus_init_irq(SYS_BUS_DEVICE(s), &s->irq); +} + +static void aw_h3_sdhost_reset(DeviceState *dev) +{ + AwH3SDHostState *s = AW_H3_SDHOST(dev); + + s->global_ctl = REG_SD_GCTL_RST; + s->clock_ctl = REG_SD_CKCR_RST; + s->timeout = REG_SD_TMOR_RST; + s->bus_width = REG_SD_BWDR_RST; + s->block_size = REG_SD_BKSR_RST; + s->byte_count = REG_SD_BYCR_RST; + s->transfer_cnt = 0; + + s->command = REG_SD_CMDR_RST; + s->command_arg = REG_SD_CAGR_RST; + + for (int i = 0; i < ARRAY_SIZE(s->response); i++) { + s->response[i] = REG_SD_RESP_RST; + } + + s->irq_mask = REG_SD_IMKR_RST; + s->irq_status = REG_SD_RISR_RST; + s->status = REG_SD_STAR_RST; + + s->fifo_wlevel = REG_SD_FWLR_RST; + s->fifo_func_sel = REG_SD_FUNS_RST; + s->debug_enable = REG_SD_DBGC_RST; + s->auto12_arg = REG_SD_A12A_RST; + s->newtiming_set = REG_SD_NTSR_RST; + s->newtiming_debug = REG_SD_SDBG_RST; + s->hardware_rst = REG_SD_HWRST_RST; + s->dmac = REG_SD_DMAC_RST; + s->desc_base = REG_SD_DLBA_RST; + s->dmac_status = REG_SD_IDST_RST; + s->dmac_irq = REG_SD_IDIE_RST; + s->card_threshold = REG_SD_THLDC_RST; + s->startbit_detect = REG_SD_DSBD_RST; + s->response_crc = REG_SD_RES_CRC_RST; + + for (int i = 0; i < ARRAY_SIZE(s->data_crc); i++) { + s->data_crc[i] = REG_SD_DATA_CRC_RST; + } + + s->status_crc = REG_SD_CRC_STA_RST; +} + +static void aw_h3_sdhost_bus_class_init(ObjectClass *klass, void *data) +{ + SDBusClass *sbc = SD_BUS_CLASS(klass); + + sbc->set_inserted = aw_h3_sdhost_set_inserted; +} + +static void aw_h3_sdhost_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + + dc->reset = aw_h3_sdhost_reset; + dc->vmsd = &vmstate_aw_h3_sdhost; +} + +static TypeInfo aw_h3_sdhost_info = { + .name = TYPE_AW_H3_SDHOST, + .parent = TYPE_SYS_BUS_DEVICE, + .instance_size = sizeof(AwH3SDHostState), + .class_init = aw_h3_sdhost_class_init, + .instance_init = aw_h3_sdhost_init, +}; + +static const TypeInfo aw_h3_sdhost_bus_info = { + .name = TYPE_AW_H3_SDHOST_BUS, + .parent = TYPE_SD_BUS, + .instance_size = sizeof(SDBus), + .class_init = aw_h3_sdhost_bus_class_init, +}; + +static void aw_h3_sdhost_register_types(void) +{ + type_register_static(&aw_h3_sdhost_info); + type_register_static(&aw_h3_sdhost_bus_info); +} + +type_init(aw_h3_sdhost_register_types) diff --git a/hw/sd/Makefile.objs b/hw/sd/Makefile.objs index a884c238df..e7cc5ab739 100644 --- a/hw/sd/Makefile.objs +++ b/hw/sd/Makefile.objs @@ -4,6 +4,7 @@ common-obj-$(CONFIG_SD) += sd.o core.o sdmmc-internal.o common-obj-$(CONFIG_SDHCI) += sdhci.o common-obj-$(CONFIG_SDHCI_PCI) += sdhci-pci.o +obj-$(CONFIG_ALLWINNER_H3) += allwinner-h3-sdhost.o obj-$(CONFIG_MILKYMIST) += milkymist-memcard.o obj-$(CONFIG_OMAP) += omap_mmc.o obj-$(CONFIG_PXA2XX) += pxa2xx_mmci.o diff --git a/hw/sd/trace-events b/hw/sd/trace-events index efcff666a2..5016cefc78 100644 --- a/hw/sd/trace-events +++ b/hw/sd/trace-events @@ -1,5 +1,12 @@ # See docs/devel/tracing.txt for syntax documentation. +# allwinner-h3-sdhost.c +aw_h3_sdhost_set_inserted(bool inserted) "inserted %u" +aw_h3_sdhost_process_desc(uint64_t desc_addr, uint32_t desc_size, bool is_write, uint32_t max_bytes) "desc_addr 0x%" PRIx64 " desc_size %" PRIu32 " is_write %u max_bytes %" PRIu32 +aw_h3_sdhost_read(uint64_t offset, uint64_t data, unsigned size) "offset 0x%" PRIx64 " data 0x%" PRIx64 " size %" PRIu32 +aw_h3_sdhost_write(uint64_t offset, uint64_t data, unsigned size) "offset 0x%" PRIx64 " data 0x%" PRIx64 " size %" PRIu32 +aw_h3_sdhost_update_irq(uint32_t irq) "IRQ bits 0x%" PRIx32 + # bcm2835_sdhost.c bcm2835_sdhost_read(uint64_t offset, uint64_t data, unsigned size) "offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u" bcm2835_sdhost_write(uint64_t offset, uint64_t data, unsigned size) "offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u" -- 2.17.1 From MAILER-DAEMON Mon Dec 16 18:44:16 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1ih02C-00013o-IF for mharc-qemu-arm@gnu.org; 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boundary="000000000000d007770599dac93a" X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::144 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 16 Dec 2019 23:44:15 -0000 --000000000000d007770599dac93a Content-Type: text/plain; charset="UTF-8" Hello Peter, In the previous version of this patch series I included the fix for setting CP10,CP11 bits in arm_set_cpu_on(), which is now in master (0c7f8c43daf65560). While that worked, I did not realize that setting those bits require rebuilding the flags. Philippe reported this [1] initially, later on during review we discussed [2] and attempted to correct it [3]. Could you please have a short look at this? Right now I don't see anymore issues, but I'm just not very familiar with this area of the code. Regards, Niek [1] https://lists.gnu.org/archive/html/qemu-devel/2019-12/msg01920.html [2] https://lists.gnu.org/archive/html/qemu-devel/2019-12/msg02784.html [3] https://lists.gnu.org/archive/html/qemu-devel/2019-12/msg02785.html On Tue, Dec 17, 2019 at 12:36 AM Niek Linnenbank wrote: > After setting CP15 bits in arm_set_cpu_on() the cached hflags must > be rebuild to reflect the changed processor state. Without rebuilding, > the cached hflags would be inconsistent until the next call to > arm_rebuild_hflags(). When QEMU is compiled with debugging enabled > (--enable-debug), this problem is captured shortly after the first > call to arm_set_cpu_on() for CPUs running in ARM 32-bit non-secure mode: > > qemu-system-arm: target/arm/helper.c:11359: cpu_get_tb_cpu_state: > Assertion `flags == rebuild_hflags_internal(env)' failed. > Aborted (core dumped) > > Fixes: 0c7f8c43daf65 > Signed-off-by: Niek Linnenbank > --- > target/arm/arm-powerctl.c | 3 +++ > 1 file changed, 3 insertions(+) > > diff --git a/target/arm/arm-powerctl.c b/target/arm/arm-powerctl.c > index b064513d44..b75f813b40 100644 > --- a/target/arm/arm-powerctl.c > +++ b/target/arm/arm-powerctl.c > @@ -127,6 +127,9 @@ static void arm_set_cpu_on_async_work(CPUState > *target_cpu_state, > target_cpu->env.regs[0] = info->context_id; > } > > + /* CP15 update requires rebuilding hflags */ > + arm_rebuild_hflags(&target_cpu->env); > + > /* Start the new CPU at the requested address */ > cpu_set_pc(target_cpu_state, info->entry); > > -- > 2.17.1 > > -- Niek Linnenbank --000000000000d007770599dac93a Content-Type: text/html; charset="UTF-8" Content-Transfer-Encoding: quoted-printable
Hello Peter,

In the previous= version of this patch series I included the fix for setting CP10,CP11 bits=
in arm_set_cpu_on(), which is now in master (0c7f8c43daf65560). = While that worked, I did not
realize that setting those bits requ= ire rebuilding the flags. Philippe reported this [1] initially,
l= ater on during review we discussed [2] and attempted to correct it [3].

Could you please have a short look at this? Right now= I don't see anymore
issues, but I'm just not very famili= ar with this area of the code.

Regards,
=
Niek

[1] =
https://lists.gnu.org/archive/html/qemu-devel/2019-12/msg01920.html
[2] https://lists.gnu.org/archive/html/qemu-devel/2019-12/msg02784.htm=
l
[3] https://lists.gnu.org/archive/html/qemu-devel/2019-12/msg02785.htm=
l

On Tu= e, Dec 17, 2019 at 12:36 AM Niek Linnenbank <nieklinnenbank@gmail.com> wrote:
After setting CP15 bits in arm_set= _cpu_on() the cached hflags must
be rebuild to reflect the changed processor state. Without rebuilding,
the cached hflags would be inconsistent until the next call to
arm_rebuild_hflags(). When QEMU is compiled with debugging enabled
(--enable-debug), this problem is captured shortly after the first
call to arm_set_cpu_on() for CPUs running in ARM 32-bit non-secure mode:
=C2=A0 qemu-system-arm: target/arm/helper.c:11359: cpu_get_tb_cpu_state: =C2=A0 Assertion `flags =3D=3D rebuild_hflags_internal(env)' failed. =C2=A0 Aborted (core dumped)

Fixes: 0c7f8c43daf65
Signed-off-by: Niek Linnenbank <nieklinnenbank@gmail.com>
---
=C2=A0target/arm/arm-powerctl.c | 3 +++
=C2=A01 file changed, 3 insertions(+)

diff --git a/target/arm/arm-powerctl.c b/target/arm/arm-powerctl.c
index b064513d44..b75f813b40 100644
--- a/target/arm/arm-powerctl.c
+++ b/target/arm/arm-powerctl.c
@@ -127,6 +127,9 @@ static void arm_set_cpu_on_async_work(CPUState *target_= cpu_state,
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0target_cpu->env.regs[0] =3D info->c= ontext_id;
=C2=A0 =C2=A0 =C2=A0}

+=C2=A0 =C2=A0 /* CP15 update requires rebuilding hflags */
+=C2=A0 =C2=A0 arm_rebuild_hflags(&target_cpu->env);
+
=C2=A0 =C2=A0 =C2=A0/* Start the new CPU at the requested address */
=C2=A0 =C2=A0 =C2=A0cpu_set_pc(target_cpu_state, info->entry);

--
2.17.1



--
Niek Linnenbank

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[83.42.66.34]) by smtp.gmail.com with ESMTPSA id t1sm1990179wma.43.2019.12.16.23.31.27 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 16 Dec 2019 23:31:28 -0800 (PST) Subject: Re: [PATCH v2 02/10] hw: arm: add Xunlong Orange Pi PC machine To: Niek Linnenbank , qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, peter.maydell@linaro.org References: <20191216233519.29030-1-nieklinnenbank@gmail.com> <20191216233519.29030-3-nieklinnenbank@gmail.com> From: =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= Message-ID: Date: Tue, 17 Dec 2019 08:31:27 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.2.2 MIME-Version: 1.0 In-Reply-To: <20191216233519.29030-3-nieklinnenbank@gmail.com> Content-Language: en-US X-MC-Unique: ZB4KCPvSMpmAvob2LVA5qw-1 X-Mimecast-Spam-Score: 0 Content-Type: text/plain; charset=WINDOWS-1252; format=flowed Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 207.211.31.81 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 17 Dec 2019 07:31:40 -0000 Hi Niek, On 12/17/19 12:35 AM, Niek Linnenbank wrote: > The Xunlong Orange Pi PC is an Allwinner H3 System on Chip > based embedded computer with mainline support in both U-Boot > and Linux. The board comes with a Quad Core Cortex A7 @ 1.3GHz, > 512MB RAM, 100Mbit ethernet, USB, SD/MMC, USB, HDMI and > various other I/O. This commit add support for the Xunlong > Orange Pi PC machine. >=20 > Signed-off-by: Niek Linnenbank > Tested-by: KONRAD Frederic > --- > hw/arm/orangepi.c | 101 +++++++++++++++++++++++++++++++++++++++++++ > MAINTAINERS | 1 + > hw/arm/Makefile.objs | 2 +- > 3 files changed, 103 insertions(+), 1 deletion(-) > create mode 100644 hw/arm/orangepi.c >=20 > diff --git a/hw/arm/orangepi.c b/hw/arm/orangepi.c > new file mode 100644 > index 0000000000..62cefc8c06 > --- /dev/null > +++ b/hw/arm/orangepi.c > @@ -0,0 +1,101 @@ > +/* > + * Orange Pi emulation > + * > + * Copyright (C) 2019 Niek Linnenbank > + * > + * This program is free software: you can redistribute it and/or modify > + * it under the terms of the GNU General Public License as published by > + * the Free Software Foundation, either version 2 of the License, or > + * (at your option) any later version. > + * > + * This program is distributed in the hope that it will be useful, > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > + * GNU General Public License for more details. > + * > + * You should have received a copy of the GNU General Public License > + * along with this program. If not, see . > + */ > + > +#include "qemu/osdep.h" > +#include "exec/address-spaces.h" > +#include "qapi/error.h" > +#include "cpu.h" > +#include "hw/sysbus.h" > +#include "hw/boards.h" > +#include "hw/qdev-properties.h" > +#include "hw/arm/allwinner-h3.h" > + > +static struct arm_boot_info orangepi_binfo =3D { > + .board_id =3D -1, > +}; > + > +typedef struct OrangePiState { > + AwH3State *h3; > + MemoryRegion sdram; > +} OrangePiState; > + > +static void orangepi_init(MachineState *machine) > +{ > + OrangePiState *s =3D g_new(OrangePiState, 1); > + > + /* Only allow Cortex-A7 for this board */ > + if (strcmp(machine->cpu_type, ARM_CPU_TYPE_NAME("cortex-a7")) !=3D 0= ) { > + error_report("This board can only be used with cortex-a7 CPU"); > + exit(1); > + } > + > + s->h3 =3D AW_H3(object_new(TYPE_AW_H3)); > + > + /* Setup timer properties */ > + object_property_set_int(OBJECT(&s->h3->timer), 32768, "clk0-freq", > + &error_abort); You access the timer object which is contained inside the soc object,=20 but the soc isn't realized yet... I wonder if this is OK. Usually what=20 we do is, either: - add a 'xtal-freq-hz' property to the SoC, set it here in the board,=20 then in soc::realize() set the property to the timer - add an alias in the SoC to the timer 'freq-hz' property: object_property_add_alias(soc, "xtal-freq-hz", OBJECT(&s->timer), "freq-hz", &error_abort); Also, if you use &error_abort, a failure in object_property_set_int()=20 triggers abort(). See "qapi/error.h": * If @errp is &error_abort, print a suitable message and abort(). * If @errp is &error_fatal, print a suitable message and exit(1). > + if (error_abort !=3D NULL) { > + error_reportf_err(error_abort, "Couldn't set clk0 frequency: "); > + exit(1); > + } So this if() block is useless. > + > + object_property_set_int(OBJECT(&s->h3->timer), 24000000, "clk1-freq"= , > + &error_abort); > + if (error_abort !=3D NULL) { > + error_reportf_err(error_abort, "Couldn't set clk1 frequency: "); > + exit(1); > + } Similarly, remove if() block. > + > + /* Mark H3 object realized */ > + object_property_set_bool(OBJECT(s->h3), true, "realized", &error_abo= rt); > + if (error_abort !=3D NULL) { > + error_reportf_err(error_abort, "Couldn't realize Allwinner H3: "= ); > + exit(1); > + } Similarly, remove if() block. > + > + /* RAM */ > + if (machine->ram_size > 1 * GiB) { > + error_report("Requested ram size is too large for this machine: = " > + "maximum is 1GB"); Per http://www.orangepi.org/orangepipc/ this board comes with a specific=20 amount of RAM. I'd enforce the default (1GiB) and refuse other cases. I noticed this by testing your series, without specifying the memory=20 size you suggested in the cover (512) it defaults to 128 MiB, and the=20 Raspian userland fails: [ *** ] (2 of 4) A start job is running for=85Persistent Storage (37s /=20 2min 1s) [ *** ] (2 of 4) A start job is running for=85Persistent Storage (38s /=20 2min 1s) [ OK ] Started Flush Journal to Persistent Storage. Starting Create Volatile Files and Directories... Starting Armbian ZRAM config... [ **] (3 of 6) A start job is running for=85s and Directories (55s / no= =20 limit) [ *] (3 of 6) A start job is running for=85s and Directories (55s / no= =20 limit) [ **] (3 of 6) A start job is running for=85s and Directories (56s / no= =20 limit) [ OK ] Started Create Volatile Files and Directories. [*** ] (5 of 6) A start job is running for=85 ZRAM config (1min 10s /=20 1min 19s) [** ] (5 of 6) A start job is running for=85 ZRAM config (1min 12s /=20 1min 19s) [* ] (5 of 6) A start job is running for=85 ZRAM config (1min 13s /=20 1min 19s) [FAILED] Failed to start Armbian ZRAM config. See 'systemctl status armbian-zram-config.service' for details. > + exit(1); > + } > + memory_region_allocate_system_memory(&s->sdram, NULL, "orangepi.ram"= , There is only one type of ram on this machine, I'd simply name this "sdram"= . > + machine->ram_size); > + memory_region_add_subregion(get_system_memory(), s->h3->memmap[AW_H3= _SDRAM], > + &s->sdram); > + > + /* Load target kernel */ > + orangepi_binfo.loader_start =3D s->h3->memmap[AW_H3_SDRAM]; > + orangepi_binfo.ram_size =3D machine->ram_size; > + orangepi_binfo.nb_cpus =3D AW_H3_NUM_CPUS; > + arm_load_kernel(ARM_CPU(first_cpu), machine, &orangepi_binfo); I wonder if we should tell the user '-bios' is not supported on this=20 machine. > +} > + > +static void orangepi_machine_init(MachineClass *mc) > +{ > + mc->desc =3D "Orange Pi PC"; > + mc->init =3D orangepi_init; > + mc->units_per_default_bus =3D 1; Maybe "units_per_default_bus =3D 1" belongs to patch 9 "add SD/MMC host=20 controller". > + mc->min_cpus =3D AW_H3_NUM_CPUS; > + mc->max_cpus =3D AW_H3_NUM_CPUS; > + mc->default_cpus =3D AW_H3_NUM_CPUS; > + mc->default_cpu_type =3D ARM_CPU_TYPE_NAME("cortex-a7"); Please add: mc->default_ram_size =3D 1 * GiB; > +} > + > +DEFINE_MACHINE("orangepi-pc", orangepi_machine_init) > diff --git a/MAINTAINERS b/MAINTAINERS > index aae1a049b4..db682e49ca 100644 > --- a/MAINTAINERS > +++ b/MAINTAINERS > @@ -486,6 +486,7 @@ L: qemu-arm@nongnu.org > S: Maintained > F: hw/*/allwinner-h3* > F: include/hw/*/allwinner-h3* > +F: hw/arm/orangepi.c > =20 > ARM PrimeCell and CMSDK devices > M: Peter Maydell > diff --git a/hw/arm/Makefile.objs b/hw/arm/Makefile.objs > index 956e496052..8d5ea453d5 100644 > --- a/hw/arm/Makefile.objs > +++ b/hw/arm/Makefile.objs > @@ -34,7 +34,7 @@ obj-$(CONFIG_DIGIC) +=3D digic.o > obj-$(CONFIG_OMAP) +=3D omap1.o omap2.o > obj-$(CONFIG_STRONGARM) +=3D strongarm.o > obj-$(CONFIG_ALLWINNER_A10) +=3D allwinner-a10.o cubieboard.o > -obj-$(CONFIG_ALLWINNER_H3) +=3D allwinner-h3.o > +obj-$(CONFIG_ALLWINNER_H3) +=3D allwinner-h3.o orangepi.o > obj-$(CONFIG_RASPI) +=3D bcm2835_peripherals.o bcm2836.o raspi.o > obj-$(CONFIG_STM32F205_SOC) +=3D stm32f205_soc.o > obj-$(CONFIG_XLNX_ZYNQMP_ARM) +=3D xlnx-zynqmp.o xlnx-zcu102.o >=20 From MAILER-DAEMON Tue Dec 17 02:45:46 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1ih7YA-00054E-90 for mharc-qemu-arm@gnu.org; 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[83.42.66.34]) by smtp.gmail.com with ESMTPSA id p15sm1919624wma.40.2019.12.16.23.45.32 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 16 Dec 2019 23:45:33 -0800 (PST) Subject: Re: [PATCH v2 08/10] arm: allwinner-h3: add Security Identifier device To: Niek Linnenbank , qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, peter.maydell@linaro.org References: <20191216233519.29030-1-nieklinnenbank@gmail.com> <20191216233519.29030-9-nieklinnenbank@gmail.com> From: =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= Message-ID: <7153b766-4c3b-5272-3c3e-33e973e74e8f@redhat.com> Date: Tue, 17 Dec 2019 08:45:32 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.2.2 MIME-Version: 1.0 In-Reply-To: <20191216233519.29030-9-nieklinnenbank@gmail.com> Content-Language: en-US X-MC-Unique: zN1Hb9gANTSQ9YiVv7r0yg-1 X-Mimecast-Spam-Score: 0 Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 207.211.31.120 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 17 Dec 2019 07:45:45 -0000 Hi Niek, On 12/17/19 12:35 AM, Niek Linnenbank wrote: > The Security Identifier device in Allwinner H3 System on Chip > gives applications a per-board unique identifier. This commit > adds support for the Allwinner H3 Security Identifier using > a 128-bit UUID value as input. > > Signed-off-by: Niek Linnenbank > --- > include/hw/arm/allwinner-h3.h | 2 + > include/hw/misc/allwinner-h3-sid.h | 40 +++++++ > hw/arm/allwinner-h3.c | 7 ++ > hw/arm/orangepi.c | 4 + > hw/misc/allwinner-h3-sid.c | 179 +++++++++++++++++++++++++++++ > hw/misc/Makefile.objs | 1 + > hw/misc/trace-events | 4 + > 7 files changed, 237 insertions(+) > create mode 100644 include/hw/misc/allwinner-h3-sid.h > create mode 100644 hw/misc/allwinner-h3-sid.c > > diff --git a/include/hw/arm/allwinner-h3.h b/include/hw/arm/allwinner-h3.h > index 8128ae6131..c98c1972a6 100644 > --- a/include/hw/arm/allwinner-h3.h > +++ b/include/hw/arm/allwinner-h3.h > @@ -29,6 +29,7 @@ > #include "hw/misc/allwinner-h3-clk.h" > #include "hw/misc/allwinner-h3-cpucfg.h" > #include "hw/misc/allwinner-h3-syscon.h" > +#include "hw/misc/allwinner-h3-sid.h" > #include "target/arm/cpu.h" > > enum { > @@ -77,6 +78,7 @@ typedef struct AwH3State { > AwH3ClockState ccu; > AwH3CpuCfgState cpucfg; > AwH3SysconState syscon; > + AwH3SidState sid; > GICState gic; > MemoryRegion sram_a1; > MemoryRegion sram_a2; > diff --git a/include/hw/misc/allwinner-h3-sid.h b/include/hw/misc/allwinner-h3-sid.h > new file mode 100644 > index 0000000000..79c9a24459 > --- /dev/null > +++ b/include/hw/misc/allwinner-h3-sid.h > @@ -0,0 +1,40 @@ > +/* > + * Allwinner H3 Security ID emulation > + * > + * Copyright (C) 2019 Niek Linnenbank > + * > + * This program is free software: you can redistribute it and/or modify > + * it under the terms of the GNU General Public License as published by > + * the Free Software Foundation, either version 2 of the License, or > + * (at your option) any later version. > + * > + * This program is distributed in the hope that it will be useful, > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > + * GNU General Public License for more details. > + * > + * You should have received a copy of the GNU General Public License > + * along with this program. If not, see . > + */ > + > +#ifndef HW_MISC_ALLWINNER_H3_SID_H > +#define HW_MISC_ALLWINNER_H3_SID_H > + > +#include "hw/sysbus.h" > +#include "qemu/uuid.h" > + > +#define TYPE_AW_H3_SID "allwinner-h3-sid" > +#define AW_H3_SID(obj) OBJECT_CHECK(AwH3SidState, (obj), TYPE_AW_H3_SID) > + > +typedef struct AwH3SidState { > + /*< private >*/ > + SysBusDevice parent_obj; > + /*< public >*/ > + > + MemoryRegion iomem; > + uint32_t control; > + uint32_t rdkey; > + QemuUUID identifier; > +} AwH3SidState; > + > +#endif > diff --git a/hw/arm/allwinner-h3.c b/hw/arm/allwinner-h3.c > index 1a9748ab2e..ba34f905cd 100644 > --- a/hw/arm/allwinner-h3.c > +++ b/hw/arm/allwinner-h3.c > @@ -196,6 +196,9 @@ static void aw_h3_init(Object *obj) > > sysbus_init_child_obj(obj, "cpucfg", &s->cpucfg, sizeof(s->cpucfg), > TYPE_AW_H3_CPUCFG); > + > + sysbus_init_child_obj(obj, "sid", &s->sid, sizeof(s->sid), > + TYPE_AW_H3_SID); Here add a property alias: object_property_add_alias(obj, "identifier", OBJECT(&s->sid), "identifier", &error_abort); > } > > static void aw_h3_realize(DeviceState *dev, Error **errp) > @@ -332,6 +335,10 @@ static void aw_h3_realize(DeviceState *dev, Error **errp) > qdev_init_nofail(DEVICE(&s->cpucfg)); > sysbus_mmio_map(SYS_BUS_DEVICE(&s->cpucfg), 0, s->memmap[AW_H3_CPUCFG]); > > + /* Security Identifier */ > + qdev_init_nofail(DEVICE(&s->sid)); > + sysbus_mmio_map(SYS_BUS_DEVICE(&s->sid), 0, s->memmap[AW_H3_SID]); > + > /* Universal Serial Bus */ > sysbus_create_simple(TYPE_AW_H3_EHCI, s->memmap[AW_H3_EHCI0], > qdev_get_gpio_in(DEVICE(&s->gic), > diff --git a/hw/arm/orangepi.c b/hw/arm/orangepi.c > index 62cefc8c06..b01c4b4f01 100644 > --- a/hw/arm/orangepi.c > +++ b/hw/arm/orangepi.c > @@ -62,6 +62,10 @@ static void orangepi_init(MachineState *machine) > exit(1); > } > > + /* Setup SID properties */ > + qdev_prop_set_string(DEVICE(&s->h3->sid), "identifier", > + "8100c002-0001-0002-0003-000044556677"); And here use the alias: qdev_prop_set_string(DEVICE(&s->h3), "identifier", "8100c002-0001-0002-0003-000044556677"); What means this value? Don't you want to be able to set it from command line? > /* Mark H3 object realized */ > object_property_set_bool(OBJECT(s->h3), true, "realized", &error_abort); > if (error_abort != NULL) { > diff --git a/hw/misc/allwinner-h3-sid.c b/hw/misc/allwinner-h3-sid.c > new file mode 100644 > index 0000000000..c472f2bcc6 > --- /dev/null > +++ b/hw/misc/allwinner-h3-sid.c > @@ -0,0 +1,179 @@ > +/* > + * Allwinner H3 Security ID emulation > + * > + * Copyright (C) 2019 Niek Linnenbank > + * > + * This program is free software: you can redistribute it and/or modify > + * it under the terms of the GNU General Public License as published by > + * the Free Software Foundation, either version 2 of the License, or > + * (at your option) any later version. > + * > + * This program is distributed in the hope that it will be useful, > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > + * GNU General Public License for more details. > + * > + * You should have received a copy of the GNU General Public License > + * along with this program. If not, see . > + */ > + > +#include "qemu/osdep.h" > +#include "qemu/units.h" > +#include "hw/sysbus.h" > +#include "migration/vmstate.h" > +#include "qemu/log.h" > +#include "qemu/module.h" > +#include "qemu/guest-random.h" > +#include "qapi/error.h" > +#include "hw/qdev-properties.h" > +#include "hw/misc/allwinner-h3-sid.h" > +#include "trace.h" > + > +/* SID register offsets */ > +enum { > + REG_PRCTL = 0x40, /* Control */ > + REG_RDKEY = 0x60, /* Read Key */ > +}; > + > +/* SID register flags */ > +enum { > + REG_PRCTL_WRITE = 0x0002, /* Unknown write flag */ > + REG_PRCTL_OP_LOCK = 0xAC00, /* Lock operation */ > +}; > + > +static uint64_t allwinner_h3_sid_read(void *opaque, hwaddr offset, > + unsigned size) > +{ > + const AwH3SidState *s = (AwH3SidState *)opaque; > + uint64_t val = 0; > + > + switch (offset) { > + case REG_PRCTL: /* Control */ > + val = s->control; > + break; > + case REG_RDKEY: /* Read Key */ > + val = s->rdkey; > + break; > + default: > + qemu_log_mask(LOG_GUEST_ERROR, "%s: bad read offset 0x%04x\n", > + __func__, (uint32_t)offset); > + return 0; > + } > + > + trace_allwinner_h3_sid_read(offset, val, size); > + > + return val; > +} > + > +static void allwinner_h3_sid_write(void *opaque, hwaddr offset, > + uint64_t val, unsigned size) > +{ > + AwH3SidState *s = (AwH3SidState *)opaque; > + > + trace_allwinner_h3_sid_write(offset, val, size); > + > + switch (offset) { > + case REG_PRCTL: /* Control */ > + s->control = val; > + > + if ((s->control & REG_PRCTL_OP_LOCK) && > + (s->control & REG_PRCTL_WRITE)) { > + uint32_t id = s->control >> 16; > + > + if (id < sizeof(QemuUUID)) { > + s->rdkey = (s->identifier.data[id]) | > + (s->identifier.data[id + 1] << 8) | > + (s->identifier.data[id + 2] << 16) | > + (s->identifier.data[id + 3] << 24); This is: s->rdkey = ldl_le_p(&s->identifier.data[id]); > + } > + } > + s->control &= ~REG_PRCTL_WRITE; > + break; > + case REG_RDKEY: /* Read Key */ Read in a write()? Maybe we can simply /* fall through */ LOG_GUEST_ERROR? > + break; > + default: > + qemu_log_mask(LOG_GUEST_ERROR, "%s: bad write offset 0x%04x\n", > + __func__, (uint32_t)offset); > + break; > + } > +} > + > +static const MemoryRegionOps allwinner_h3_sid_ops = { > + .read = allwinner_h3_sid_read, > + .write = allwinner_h3_sid_write, > + .endianness = DEVICE_NATIVE_ENDIAN, > + .valid = { > + .min_access_size = 4, > + .max_access_size = 4, > + .unaligned = false 'false' is the default value, maybe we can omit it? > + }, > + .impl.min_access_size = 4, > +}; > + > +static void allwinner_h3_sid_reset(DeviceState *dev) > +{ > + AwH3SidState *s = AW_H3_SID(dev); > + > + /* Set default values for registers */ > + s->control = 0; > + s->rdkey = 0; > +} > + > +static void allwinner_h3_sid_realize(DeviceState *dev, Error **errp) > +{ > +} If you don't need realize(), just remove it. However maybe we want to check if the identifier is null, either warn/abort or generate a random one? > + > +static void allwinner_h3_sid_init(Object *obj) > +{ > + SysBusDevice *sbd = SYS_BUS_DEVICE(obj); > + AwH3SidState *s = AW_H3_SID(obj); > + > + /* Fill UUID with zeroes by default */ > + qemu_uuid_parse(UUID_NONE, &s->identifier); AwH3SidState is zeroed just before this init() call. I think we don't need to zeroes the UUID again. > + > + /* Memory mapping */ > + memory_region_init_io(&s->iomem, OBJECT(s), &allwinner_h3_sid_ops, s, > + TYPE_AW_H3_SID, 1 * KiB); > + sysbus_init_mmio(sbd, &s->iomem); > +} > + > +static Property allwinner_h3_sid_properties[] = { > + DEFINE_PROP_UUID_NODEFAULT("identifier", AwH3SidState, identifier), > + DEFINE_PROP_END_OF_LIST() > +}; > + > +static const VMStateDescription allwinner_h3_sid_vmstate = { > + .name = "allwinner-h3-sid", > + .version_id = 1, > + .minimum_version_id = 1, > + .fields = (VMStateField[]) { > + VMSTATE_UINT32(control, AwH3SidState), > + VMSTATE_UINT32(rdkey, AwH3SidState), > + VMSTATE_END_OF_LIST() > + } > +}; > + > +static void allwinner_h3_sid_class_init(ObjectClass *klass, void *data) > +{ > + DeviceClass *dc = DEVICE_CLASS(klass); > + > + dc->reset = allwinner_h3_sid_reset; > + dc->realize = allwinner_h3_sid_realize; > + dc->vmsd = &allwinner_h3_sid_vmstate; > + dc->props = allwinner_h3_sid_properties; > +} > + > +static const TypeInfo allwinner_h3_sid_info = { > + .name = TYPE_AW_H3_SID, > + .parent = TYPE_SYS_BUS_DEVICE, > + .instance_init = allwinner_h3_sid_init, > + .instance_size = sizeof(AwH3SidState), > + .class_init = allwinner_h3_sid_class_init, > +}; > + > +static void allwinner_h3_sid_register(void) > +{ > + type_register_static(&allwinner_h3_sid_info); > +} > + > +type_init(allwinner_h3_sid_register) > diff --git a/hw/misc/Makefile.objs b/hw/misc/Makefile.objs > index c4ca2ed689..f3620eee4e 100644 > --- a/hw/misc/Makefile.objs > +++ b/hw/misc/Makefile.objs > @@ -31,6 +31,7 @@ common-obj-$(CONFIG_IVSHMEM_DEVICE) += ivshmem.o > common-obj-$(CONFIG_ALLWINNER_H3) += allwinner-h3-clk.o > obj-$(CONFIG_ALLWINNER_H3) += allwinner-h3-cpucfg.o > common-obj-$(CONFIG_ALLWINNER_H3) += allwinner-h3-syscon.o > +common-obj-$(CONFIG_ALLWINNER_H3) += allwinner-h3-sid.o > common-obj-$(CONFIG_REALVIEW) += arm_sysctl.o > common-obj-$(CONFIG_NSERIES) += cbus.o > common-obj-$(CONFIG_ECCMEMCTL) += eccmemctl.o > diff --git a/hw/misc/trace-events b/hw/misc/trace-events > index b93089d010..a777844ca3 100644 > --- a/hw/misc/trace-events > +++ b/hw/misc/trace-events > @@ -5,6 +5,10 @@ allwinner_h3_cpucfg_cpu_reset(uint8_t cpu_id, uint32_t reset_addr) "H3-CPUCFG: c > allwinner_h3_cpucfg_read(uint64_t offset, uint64_t data, unsigned size) "H3-CPUCFG: read: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %" PRIu32 > allwinner_h3_cpucfg_write(uint64_t offset, uint64_t data, unsigned size) "H3-CPUCFG: write: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %" PRIu32 > > +# allwinner-h3-sid.c > +allwinner_h3_sid_read(uint64_t offset, uint64_t data, unsigned size) "H3-SID: read: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %" PRIu32 > +allwinner_h3_sid_write(uint64_t offset, uint64_t data, unsigned size) "H3-SID: write: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %" PRIu32 > + > # eccmemctl.c > ecc_mem_writel_mer(uint32_t val) "Write memory enable 0x%08x" > ecc_mem_writel_mdr(uint32_t val) "Write memory delay 0x%08x" > From MAILER-DAEMON Tue Dec 17 03:38:26 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1ih8N8-0001G7-OR for mharc-qemu-arm@gnu.org; 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Tue, 17 Dec 2019 00:38:16 -0800 (PST) Received: from zen (localhost [127.0.0.1]) by zen.linaroharston (Postfix) with ESMTP id A15FC1FF87; Tue, 17 Dec 2019 08:38:15 +0000 (GMT) References: <87h83w4dod.fsf@keithp.com> <20191104204230.12249-1-keithp@keithp.com> User-agent: mu4e 1.3.5; emacs 27.0.50 From: Alex =?utf-8?Q?Benn=C3=A9e?= To: Keith Packard Cc: qemu-devel@nongnu.org, Peter Maydell , Riku Voipio , Laurent Vivier , Paolo Bonzini , qemu-arm@nongnu.org Subject: Re: [PATCH] Semihost SYS_READC implementation (v6) In-reply-to: <20191104204230.12249-1-keithp@keithp.com> Date: Tue, 17 Dec 2019 08:38:15 +0000 Message-ID: <87h81zwdmw.fsf@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::442 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 17 Dec 2019 08:38:25 -0000 Keith Packard writes: > Provides a blocking call to read a character from the console using > semihosting.chardev, if specified. This takes some careful command > line options to use stdio successfully as the serial ports, monitor > and semihost all want to use stdio. Here's a sample set of command > line options which share stdio betwen semihost, monitor and serial > ports: > > qemu \ > -chardev stdio,mux=3Don,id=3Dstdio0 \ > -serial chardev:stdio0 \ > -semihosting-config enable=3Don,chardev=3Dstdio0 \ > -mon chardev=3Dstdio0,mode=3Dreadline > > This creates a chardev hooked to stdio and then connects all of the > subsystems to it. A shorter mechanism would be good to hear about. > > Signed-off-by: Keith Packard > > --- > > v2: > Add implementation in linux-user/arm/semihost.c > > v3: (thanks to Paolo Bonzini ) > Replace hand-rolled fifo with fifo8 > Avoid mixing code and declarations > Remove spurious (void) cast of function parameters > Define qemu_semihosting_console_init when CONFIG_USER_ONLY > > v4: > Add qemu_semihosting_console_init to stubs/semihost.c for > hosts that don't support semihosting > > v5: > Move #include statements to the top of the file. > Actually include the stubs/semihost.c patch that was > supposed to be in v4 > v6: > Move call to qemu_semihosting_console_init earlier in > main so that the mux starts connected to the serial device > --- > hw/semihosting/console.c | 72 +++++++++++++++++++++++++++++++ > include/hw/semihosting/console.h | 12 ++++++ > include/hw/semihosting/semihost.h | 4 ++ > linux-user/arm/semihost.c | 23 ++++++++++ > stubs/semihost.c | 4 ++ > target/arm/arm-semi.c | 3 +- > vl.c | 3 ++ > 7 files changed, 119 insertions(+), 2 deletions(-) > > diff --git a/hw/semihosting/console.c b/hw/semihosting/console.c > index b4b17c8afb..4db68d6227 100644 > --- a/hw/semihosting/console.c > +++ b/hw/semihosting/console.c > @@ -22,6 +22,12 @@ > #include "exec/gdbstub.h" > #include "qemu/log.h" > #include "chardev/char.h" > +#include > +#include "chardev/char-fe.h" > +#include "sysemu/sysemu.h" > +#include "qemu/main-loop.h" > +#include "qapi/error.h" > +#include "qemu/fifo8.h" >=20=20 > int qemu_semihosting_log_out(const char *s, int len) > { > @@ -98,3 +104,69 @@ void qemu_semihosting_console_outc(CPUArchState *env,= target_ulong addr) > __func__, addr); > } > } > + > +#define FIFO_SIZE 1024 > + > +typedef struct SemihostingConsole { > + CharBackend backend; > + pthread_mutex_t mutex; > + pthread_cond_t cond; > + bool got; > + Fifo8 fifo; > +} SemihostingConsole; > + > +static SemihostingConsole console =3D { > + .mutex =3D PTHREAD_MUTEX_INITIALIZER, > + .cond =3D PTHREAD_COND_INITIALIZER > +}; > + > +static int console_can_read(void *opaque) > +{ > + SemihostingConsole *c =3D opaque; > + int ret; > + pthread_mutex_lock(&c->mutex); > + ret =3D (int) fifo8_num_free(&c->fifo); > + pthread_mutex_unlock(&c->mutex); > + return ret; > +} > + > +static void console_read(void *opaque, const uint8_t *buf, int size) > +{ > + SemihostingConsole *c =3D opaque; > + pthread_mutex_lock(&c->mutex); > + while (size-- && !fifo8_is_full(&c->fifo)) { > + fifo8_push(&c->fifo, *buf++); > + } > + pthread_cond_broadcast(&c->cond); > + pthread_mutex_unlock(&c->mutex); > +} > + > +target_ulong qemu_semihosting_console_inc(CPUArchState *env) > +{ > + uint8_t ch; > + SemihostingConsole *c =3D &console; > + qemu_mutex_unlock_iothread(); > + pthread_mutex_lock(&c->mutex); > + while (fifo8_is_empty(&c->fifo)) { > + pthread_cond_wait(&c->cond, &c->mutex); > + } > + ch =3D fifo8_pop(&c->fifo); > + pthread_mutex_unlock(&c->mutex); > + qemu_mutex_lock_iothread(); > + return (target_ulong) ch; > +} I've been trying to exercise this code with a new test case: https://github.com/stsquad/semihosting-tests/tree/readc-test But I end up deadlocked. Even worse when I issue quit via the mmio we end up hanging on something that will never complete: (gdb) thread apply all bt Thread 3 (Thread 0x7f8b1959e700 (LWP 14017)): #0 0x00007f8b2ada900c in futex_wait_cancelable (private=3D0, expected=3D= 0, futex_word=3D0x56213f5482e8 ) at ../sysdeps/unix/sysv/linux= /futex-internal.h:88 #1 0x00007f8b2ada900c in __pthread_cond_wait_common (abstime=3D0x0, mute= x=3D0x56213f548298 , cond=3D0x56213f5482c0 ) at pth= read_cond_wait.c:502 #2 0x00007f8b2ada900c in __pthread_cond_wait (cond=3Dcond@entry=3D0x5621= 3f5482c0 , mutex=3Dmutex@entry=3D0x56213f548298 ) a= t pthread_cond_wait.c:655 #3 0x000056213ea31a40 in qemu_semihosting_console_inc (env=3Denv@entry= =3D0x56214138a680) at /home/alex/lsrc/qemu.git/hw/semihosting/console.c:151 #4 0x000056213eab96e8 in do_arm_semihosting (env=3Denv@entry=3D0x5621413= 8a680) at /home/alex/lsrc/qemu.git/target/arm/arm-semi.c:805 #5 0x000056213eacd521 in handle_semihosting (cs=3D) at /h= ome/alex/lsrc/qemu.git/target/arm/helper.c:8476 #6 0x000056213eacd521 in arm_cpu_do_interrupt (cs=3D) at = /home/alex/lsrc/qemu.git/target/arm/helper.c:8522 #7 0x000056213e9e53d0 in cpu_handle_exception (ret=3D= , cpu=3D0x5621411fe2f0) at /home/alex/lsrc/qemu.git/accel/tcg/cpu-exec.c:503 #8 0x000056213e9e53d0 in cpu_exec (cpu=3Dcpu@entry=3D0x562141381550) at = /home/alex/lsrc/qemu.git/accel/tcg/cpu-exec.c:711 #9 0x000056213e9b4f1f in tcg_cpu_exec (cpu=3D0x562141381550) at /home/al= ex/lsrc/qemu.git/cpus.c:1473 #10 0x000056213e9b715b in qemu_tcg_cpu_thread_fn (arg=3Darg@entry=3D0x562= 141381550) at /home/alex/lsrc/qemu.git/cpus.c:1781 #11 0x000056213ef026fa in qemu_thread_start (args=3D) at /= home/alex/lsrc/qemu.git/util/qemu-thread-posix.c:519 #12 0x00007f8b2ada2fa3 in start_thread (arg=3D) at pthread= _create.c:486 #13 0x00007f8b2acd14cf in clone () at ../sysdeps/unix/sysv/linux/x86_64/c= lone.S:95 Thread 2 (Thread 0x7f8b1c012700 (LWP 14016)): #0 0x00007f8b2accbf59 in syscall () at ../sysdeps/unix/sysv/linux/x86_64= /syscall.S:38 #1 0x000056213ef034ab in qemu_futex_wait (val=3D, f=3D) at /home/alex/lsrc/qemu.git/util/qemu-thread-posix.c:455 #2 0x000056213ef034ab in qemu_event_wait (ev=3Dev@entry=3D0x56213f55ffe0= ) at /home/alex/lsrc/qemu.git/util/qemu-thread-posix.c:459 #3 0x000056213ef14dc7 in wait_for_readers () at /home/alex/lsrc/qemu.git= /util/rcu.c:134 #4 0x000056213ef14dc7 in synchronize_rcu () at /home/alex/lsrc/qemu.git/= util/rcu.c:170 #5 0x000056213ef1508d in call_rcu_thread (opaque=3Dopaque@entry=3D0x0) a= t /home/alex/lsrc/qemu.git/util/rcu.c:267 #6 0x000056213ef026fa in qemu_thread_start (args=3D) at /= home/alex/lsrc/qemu.git/util/qemu-thread-posix.c:519 #7 0x00007f8b2ada2fa3 in start_thread (arg=3D) at pthread= _create.c:486 #8 0x00007f8b2acd14cf in clone () at ../sysdeps/unix/sysv/linux/x86_64/c= lone.S:95 Thread 1 (Thread 0x7f8b1c151680 (LWP 14010)): #0 0x00007f8b2ada900c in futex_wait_cancelable (private=3D0, expected=3D= 0, futex_word=3D0x56213f52c7c8 ) at ../sysdeps/unix/sys= v/linux/futex-internal.h:88 #1 0x00007f8b2ada900c in __pthread_cond_wait_common (abstime=3D0x0, mute= x=3D0x56213f52c8c0 , cond=3D0x56213f52c7a0 ) at pthread_cond_wait.c:502 #2 0x00007f8b2ada900c in __pthread_cond_wait (cond=3Dcond@entry=3D0x5621= 3f52c7a0 , mutex=3Dmutex@entry=3D0x56213f52c8c0 ) at pthread_cond_wait.c:655 #3 0x000056213ef02e2b in qemu_cond_wait_impl (cond=3D0x56213f52c7a0 , mutex=3D0x56213f52c8c0 , file=3D0x56213ef= 43700 "/home/alex/lsrc/qemu.git/cpus.c", line=3D1943) at /home/alex/lsrc/qe= mu.git/util/qemu-thread-posix.c:173 #4 0x000056213e9b74a4 in pause_all_vcpus () at /home/alex/lsrc/qemu.git/= cpus.c:1943 #5 0x000056213e9b74a4 in pause_all_vcpus () at /home/alex/lsrc/qemu.git/= cpus.c:1923 #6 0x000056213e9b7532 in do_vm_stop (state=3DRUN_STATE_SHUTDOWN, send_st= op=3D) at /home/alex/lsrc/qemu.git/cpus.c:1102 #7 0x000056213e96b8fc in main (argc=3D, argv=3D, envp=3D) at /home/alex/lsrc/qemu.git/vl.c:4473 I guess my first question is why do we need a separate mutex/cond variable for this operation? This seems like the sort of thing that the BQL could protect. Secondly if the vCPU is paused (via console or gdbstub) we need to unwind from our blocking position and be in a position to restart cleanly. > + > +void qemu_semihosting_console_init(void) > +{ > + Chardev *chr =3D semihosting_get_chardev(); > + > + if (chr) { > + fifo8_create(&console.fifo, FIFO_SIZE); > + qemu_chr_fe_init(&console.backend, chr, &error_abort); > + qemu_chr_fe_set_handlers(&console.backend, > + console_can_read, > + console_read, > + NULL, NULL, &console, > + NULL, true); > + } > +} > diff --git a/include/hw/semihosting/console.h b/include/hw/semihosting/co= nsole.h > index 9be9754bcd..f7d5905b41 100644 > --- a/include/hw/semihosting/console.h > +++ b/include/hw/semihosting/console.h > @@ -37,6 +37,18 @@ int qemu_semihosting_console_outs(CPUArchState *env, t= arget_ulong s); > */ > void qemu_semihosting_console_outc(CPUArchState *env, target_ulong c); >=20=20 > +/** > + * qemu_semihosting_console_inc: > + * @env: CPUArchState > + * > + * Receive single character from debug console. This > + * may be the remote gdb session if a softmmu guest is currently being > + * debugged. > + * > + * Returns: character read or -1 on error > + */ > +target_ulong qemu_semihosting_console_inc(CPUArchState *env); > + > /** > * qemu_semihosting_log_out: > * @s: pointer to string > diff --git a/include/hw/semihosting/semihost.h b/include/hw/semihosting/s= emihost.h > index 60fc42d851..b8ce5117ae 100644 > --- a/include/hw/semihosting/semihost.h > +++ b/include/hw/semihosting/semihost.h > @@ -56,6 +56,9 @@ static inline Chardev *semihosting_get_chardev(void) > { > return NULL; > } > +static inline void qemu_semihosting_console_init(void) > +{ > +} > #else /* !CONFIG_USER_ONLY */ > bool semihosting_enabled(void); > SemihostingTarget semihosting_get_target(void); > @@ -68,6 +71,7 @@ Chardev *semihosting_get_chardev(void); > void qemu_semihosting_enable(void); > int qemu_semihosting_config_options(const char *opt); > void qemu_semihosting_connect_chardevs(void); > +void qemu_semihosting_console_init(void); > #endif /* CONFIG_USER_ONLY */ >=20=20 > #endif /* SEMIHOST_H */ > diff --git a/linux-user/arm/semihost.c b/linux-user/arm/semihost.c > index a16b525eec..4f998d6220 100644 > --- a/linux-user/arm/semihost.c > +++ b/linux-user/arm/semihost.c > @@ -14,6 +14,7 @@ > #include "cpu.h" > #include "hw/semihosting/console.h" > #include "qemu.h" > +#include >=20=20 > int qemu_semihosting_console_outs(CPUArchState *env, target_ulong addr) > { > @@ -47,3 +48,25 @@ void qemu_semihosting_console_outc(CPUArchState *env, = target_ulong addr) > } > } > } > + > +target_ulong qemu_semihosting_console_inc(CPUArchState *env) > +{ > + uint8_t c; > + struct pollfd pollfd =3D { > + .fd =3D STDIN_FILENO, > + .events =3D POLLIN > + }; > + > + if (poll(&pollfd, 1, -1) !=3D 1) { > + qemu_log_mask(LOG_UNIMP, "%s: unexpected read from stdin failure= ", > + __func__); > + return (target_ulong) -1; > + } > + > + if (read(STDIN_FILENO, &c, 1) !=3D 1) { > + qemu_log_mask(LOG_UNIMP, "%s: unexpected read from stdin failure= ", > + __func__); > + return (target_ulong) -1; > + } > + return (target_ulong) c; > +} > diff --git a/stubs/semihost.c b/stubs/semihost.c > index f90589259c..1d8b37f7b2 100644 > --- a/stubs/semihost.c > +++ b/stubs/semihost.c > @@ -69,3 +69,7 @@ void semihosting_arg_fallback(const char *file, const c= har *cmd) > void qemu_semihosting_connect_chardevs(void) > { > } > + > +void qemu_semihosting_console_init(void) > +{ > +} > diff --git a/target/arm/arm-semi.c b/target/arm/arm-semi.c > index 6f7b6d801b..47d61f6fe1 100644 > --- a/target/arm/arm-semi.c > +++ b/target/arm/arm-semi.c > @@ -802,8 +802,7 @@ target_ulong do_arm_semihosting(CPUARMState *env) >=20=20 > return guestfd_fns[gf->type].readfn(cpu, gf, arg1, len); > case TARGET_SYS_READC: > - qemu_log_mask(LOG_UNIMP, "%s: SYS_READC not implemented", __func= __); > - return 0; > + return qemu_semihosting_console_inc(env); > case TARGET_SYS_ISTTY: > GET_ARG(0); >=20=20 > diff --git a/vl.c b/vl.c > index 4489cfb2bb..7ea8a907fd 100644 > --- a/vl.c > +++ b/vl.c > @@ -4284,6 +4284,9 @@ int main(int argc, char **argv, char **envp) > qemu_opts_foreach(qemu_find_opts("mon"), > mon_init_func, NULL, &error_fatal); >=20=20 > + /* connect semihosting console input if requested */ > + qemu_semihosting_console_init(); > + > if (foreach_device_config(DEV_SERIAL, serial_parse) < 0) > exit(1); > if (foreach_device_config(DEV_PARALLEL, parallel_parse) < 0) --=20 Alex Benn=C3=A9e From MAILER-DAEMON Tue Dec 17 03:55:12 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1ih8dM-00023E-Hg for mharc-qemu-arm@gnu.org; Tue, 17 Dec 2019 03:55:12 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:37756) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ih8dJ-000232-R8 for qemu-arm@nongnu.org; Tue, 17 Dec 2019 03:55:10 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ih8dI-0006XQ-9U for qemu-arm@nongnu.org; Tue, 17 Dec 2019 03:55:09 -0500 Received: from us-smtp-2.mimecast.com ([207.211.31.81]:51742 helo=us-smtp-1.mimecast.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1ih8dI-0006X4-3R for qemu-arm@nongnu.org; Tue, 17 Dec 2019 03:55:08 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1576572907; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=4cCzvUMPeYUWri5dkvEAVyVTWUXotoL4CI59FxQhSps=; b=NcZNa7Vknj9NIbes4BpFw3BmjBI0fPx4PLjrGUxVI9y+egpL3SIz5k7yr2OKTID1igAMsj r+3XgprsEjEoQH5dUy/llbuTRNuxKIEfCLAxX25VsXeW7rb36Mzc1f6CpAZYadmQyMn6Jm yewHloYn/hJMmcbLvtFoWerNbhmioo0= Received: from mimecast-mx01.redhat.com (mimecast-mx01.redhat.com [209.132.183.4]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-1-qGU9WmU4PJ6mX_u7VaknPA-1; Tue, 17 Dec 2019 03:55:05 -0500 Received: from smtp.corp.redhat.com (int-mx02.intmail.prod.int.phx2.redhat.com [10.5.11.12]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx01.redhat.com (Postfix) with ESMTPS id 9127E18FF662; Tue, 17 Dec 2019 08:55:04 +0000 (UTC) Received: from [10.36.116.117] (ovpn-116-117.ams2.redhat.com [10.36.116.117]) by smtp.corp.redhat.com (Postfix) with ESMTPS id B10616106E; Tue, 17 Dec 2019 08:55:03 +0000 (UTC) Subject: Re: [PATCH v3 2/6] hw/arm/smmuv3: Correct SMMU_BASE_ADDR_MASK value To: Simon Veith , qemu-devel@nongnu.org, qemu-arm@nongnu.org References: <1576509312-13083-1-git-send-email-sveith@amazon.de> <1576509312-13083-3-git-send-email-sveith@amazon.de> From: Auger Eric Message-ID: <9a0ca836-7c0c-d203-eb54-ca7e439f5e8d@redhat.com> Date: Tue, 17 Dec 2019 09:55:02 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101 Thunderbird/60.4.0 MIME-Version: 1.0 In-Reply-To: <1576509312-13083-3-git-send-email-sveith@amazon.de> Content-Language: en-US X-Scanned-By: MIMEDefang 2.79 on 10.5.11.12 X-MC-Unique: qGU9WmU4PJ6mX_u7VaknPA-1 X-Mimecast-Spam-Score: 0 Content-Type: text/plain; charset=windows-1252 Content-Transfer-Encoding: 7bit X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 207.211.31.81 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 17 Dec 2019 08:55:10 -0000 Hi Simon, On 12/16/19 4:15 PM, Simon Veith wrote: > There are two issues with the current value of SMMU_BASE_ADDR_MASK: > > - At the lower end, we are clearing bits [4:0]. Per the SMMUv3 spec, > we should also be treating bit 5 as zero in the base address. > - At the upper end, we are clearing bits [63:48]. Per the SMMUv3 spec, > only bits [63:52] must be explicitly treated as zero. > > Update the SMMU_BASE_ADDR_MASK value to mask out bits [63:52] and [5:0]. > > ref. ARM IHI 0070C, section 6.3.23. > > Signed-off-by: Simon Veith > Cc: Eric Auger > Cc: qemu-devel@nongnu.org > Cc: qemu-arm@nongnu.org Acked-by: Eric Auger Thanks Eric > --- > hw/arm/smmuv3-internal.h | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/hw/arm/smmuv3-internal.h b/hw/arm/smmuv3-internal.h > index d190181..042b435 100644 > --- a/hw/arm/smmuv3-internal.h > +++ b/hw/arm/smmuv3-internal.h > @@ -99,7 +99,7 @@ REG32(GERROR_IRQ_CFG2, 0x74) > > #define A_STRTAB_BASE 0x80 /* 64b */ > > -#define SMMU_BASE_ADDR_MASK 0xffffffffffe0 > +#define SMMU_BASE_ADDR_MASK 0xfffffffffffc0 > > REG32(STRTAB_BASE_CFG, 0x88) > FIELD(STRTAB_BASE_CFG, FMT, 16, 2) > From MAILER-DAEMON Tue Dec 17 03:55:42 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1ih8dq-0002Z4-R8 for mharc-qemu-arm@gnu.org; Tue, 17 Dec 2019 03:55:42 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:37940) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ih8dn-0002XM-US for qemu-arm@nongnu.org; Tue, 17 Dec 2019 03:55:40 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ih8dm-00080A-Tc for qemu-arm@nongnu.org; Tue, 17 Dec 2019 03:55:39 -0500 Received: from us-smtp-delivery-1.mimecast.com ([205.139.110.120]:34260 helo=us-smtp-1.mimecast.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1ih8dm-0007ws-Os for qemu-arm@nongnu.org; Tue, 17 Dec 2019 03:55:38 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1576572938; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=vKs83JLl70hHBwVyUSD2vxluT9kCZg5KhTNlr3C81qU=; b=Lo2a5p1rJ8KmEcRkhWij2Dourqc+4jDspVBOhUzR5pwk7qipAJn9UEiWBLqKyiUvuLszIQ aZNqi0gfC0SZRyA/yHJDfQV8PrAv0UYR9byabzofiIqVG3EqpXt4CF0fP/n6legvy+YKAX fh+IfQWcuOpWH9L8xcnDobJzpgsfM50= Received: from mimecast-mx01.redhat.com (mimecast-mx01.redhat.com [209.132.183.4]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-224-e4qIWUrfNSKDjYFT8uenog-1; Tue, 17 Dec 2019 03:54:51 -0500 Received: from smtp.corp.redhat.com (int-mx08.intmail.prod.int.phx2.redhat.com [10.5.11.23]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx01.redhat.com (Postfix) with ESMTPS id 61A061051461; Tue, 17 Dec 2019 08:54:50 +0000 (UTC) Received: from [10.36.116.117] (ovpn-116-117.ams2.redhat.com [10.36.116.117]) by smtp.corp.redhat.com (Postfix) with ESMTPS id 7813826DF9; Tue, 17 Dec 2019 08:54:49 +0000 (UTC) Subject: Re: [PATCH v3 3/6] hw/arm/smmuv3: Check stream IDs against actual table LOG2SIZE To: Simon Veith , qemu-devel@nongnu.org, qemu-arm@nongnu.org References: <1576509312-13083-1-git-send-email-sveith@amazon.de> <1576509312-13083-4-git-send-email-sveith@amazon.de> From: Auger Eric Message-ID: <51c6ef39-f714-0d6b-7b14-2b49b298e556@redhat.com> Date: Tue, 17 Dec 2019 09:54:47 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101 Thunderbird/60.4.0 MIME-Version: 1.0 In-Reply-To: <1576509312-13083-4-git-send-email-sveith@amazon.de> Content-Language: en-US X-Scanned-By: MIMEDefang 2.84 on 10.5.11.23 X-MC-Unique: e4qIWUrfNSKDjYFT8uenog-1 X-Mimecast-Spam-Score: 0 Content-Type: text/plain; charset=windows-1252 Content-Transfer-Encoding: 7bit X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 205.139.110.120 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 17 Dec 2019 08:55:41 -0000 Hi Simon, On 12/16/19 4:15 PM, Simon Veith wrote: > When checking whether a stream ID is in range of the stream table, we > have so far been only checking it against our implementation limit > (SMMU_IDR1_SIDSIZE). However, the guest can program the > STRTAB_BASE_CFG.LOG2SIZE field to a size that is smaller than this > limit. > > Check the stream ID against this limit as well to match the hardware > behavior of raising C_BAD_STREAMID events in case the limit is exceeded. > Also, ensure that we do not go one entry beyond the end of the table by > checking that its index is strictly smaller than the table size. > > ref. ARM IHI 0070C, section 6.3.24. > > Signed-off-by: Simon Veith > Cc: Eric Auger > Cc: qemu-devel@nongnu.org > Cc: qemu-arm@nongnu.org Acked-by: Eric Auger Thanks Eric > --- > Changed in v2: > > * Also check that stream ID is strictly lower than the table size > > hw/arm/smmuv3.c | 8 ++++++-- > 1 file changed, 6 insertions(+), 2 deletions(-) > > diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c > index eef9a18..727558b 100644 > --- a/hw/arm/smmuv3.c > +++ b/hw/arm/smmuv3.c > @@ -377,11 +377,15 @@ static int smmu_find_ste(SMMUv3State *s, uint32_t sid, STE *ste, > SMMUEventInfo *event) > { > dma_addr_t addr; > + uint32_t log2size; > int ret; > > trace_smmuv3_find_ste(sid, s->features, s->sid_split); > - /* Check SID range */ > - if (sid > (1 << SMMU_IDR1_SIDSIZE)) { > + log2size = FIELD_EX32(s->strtab_base_cfg, STRTAB_BASE_CFG, LOG2SIZE); > + /* > + * Check SID range against both guest-configured and implementation limits > + */ > + if (sid >= (1 << MIN(log2size, SMMU_IDR1_SIDSIZE))) { > event->type = SMMU_EVT_C_BAD_STREAMID; > return -EINVAL; > } > From MAILER-DAEMON Tue Dec 17 04:08:31 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1ih8qF-0005Ko-OK for mharc-qemu-arm@gnu.org; Tue, 17 Dec 2019 04:08:31 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:41093) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ih8qC-0005Jd-NY for qemu-arm@nongnu.org; Tue, 17 Dec 2019 04:08:29 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ih8qA-0002YW-R4 for qemu-arm@nongnu.org; Tue, 17 Dec 2019 04:08:28 -0500 Received: from us-smtp-delivery-1.mimecast.com ([207.211.31.120]:37926 helo=us-smtp-1.mimecast.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1ih8qA-0002Xc-Ne for qemu-arm@nongnu.org; Tue, 17 Dec 2019 04:08:26 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1576573706; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=9HJKWolAg41zL7hPO63dV0aW6bVfWeULBzkYg6u1AE8=; b=h7pqApxu/+tTHI+rTTw4nOnvIMoJt0U5J/wABmExQTWnYOXwS+rSkTCRHnNlTI2/4bq4Tt TIlbQ0oqhG9J/M8xo5R/tXaturqSv29hsEU5TOxoC/gTQ1UVXYMjHiSMlx9WfGHQuus7ro aTBpVSt+9kYjsnSD3Ef5Ql7ZNe6fsn8= Received: from mail-wr1-f71.google.com (mail-wr1-f71.google.com [209.85.221.71]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-181-MDJjIkMHNsC6HbYjkGl8LA-1; Tue, 17 Dec 2019 04:08:24 -0500 Received: by mail-wr1-f71.google.com with SMTP id b13so3678870wrx.22 for ; Tue, 17 Dec 2019 01:08:24 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:subject:to:cc:references:from:message-id:date :user-agent:mime-version:in-reply-to:content-language :content-transfer-encoding; bh=+qsBbSaHrwEfAZlKjDrHR4p3vP6YgzY79tvkGNrzuPk=; b=KUK4vtViz6o19chS5JTcI5tcFwk8dSsgZC6tphIS3H0csMT/vgfjFqO5wPMifxsvqJ 2LOjaye0dTrg2Cr/EOrbraQcsXWayAClgi1JzaK5Nf/9KJdlEMsVVAIVOBp+0wh0j8XC iN1/1wy4V+ZpfRWdz95zjZ6wB4hlftFVDjR7uq7Wuspt/8hsbTfLSohq1Vlgc9OSdpPN Y+EN4JyPsu4MUTHl/i6bck2MuiUNQcIkHPjvwH9CVClqlbwzizuGqfvrliQTz1JgLUE2 uhuQufTn8/fsi8iL86DxbVJX0LszklroTHo5QkXQ2wXBIkQYniGTDlo0uaj8Nv2zfdhm TbtA== X-Gm-Message-State: APjAAAWtboSkLFRTXtZV6RDzyvZl0Hr5pcZASzUflil5Tzy9a/PIUdJy VrWsrohSH8+q+neL9GPcQbHLpGWR9GCIkzgW3uXZ48PQvXN5tbjoMUGJNhaI9KB0jNDfZ0py/ny rWic5dbPppfU1 X-Received: by 2002:a1c:41c4:: with SMTP id o187mr4184753wma.24.1576573703670; Tue, 17 Dec 2019 01:08:23 -0800 (PST) X-Google-Smtp-Source: APXvYqxUpZpHRkB6Lb9wmlJR1M48WMujjO4O4ayYRBFoGfnVUqoAx0DdGomaJN9YciA4hGk56OW7pg== X-Received: by 2002:a1c:41c4:: with SMTP id o187mr4184726wma.24.1576573703355; Tue, 17 Dec 2019 01:08:23 -0800 (PST) Received: from ?IPv6:2001:b07:6468:f312:503f:4ffc:fc4a:f29a? ([2001:b07:6468:f312:503f:4ffc:fc4a:f29a]) by smtp.gmail.com with ESMTPSA id x6sm2222288wmi.44.2019.12.17.01.08.22 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 17 Dec 2019 01:08:22 -0800 (PST) Subject: Re: [PATCH] Semihost SYS_READC implementation (v6) To: =?UTF-8?Q?Alex_Benn=c3=a9e?= , Keith Packard Cc: qemu-devel@nongnu.org, Peter Maydell , Riku Voipio , Laurent Vivier , qemu-arm@nongnu.org References: <87h83w4dod.fsf@keithp.com> <20191104204230.12249-1-keithp@keithp.com> <87h81zwdmw.fsf@linaro.org> From: Paolo Bonzini Message-ID: <5a3b1155-4242-831c-8ae4-e9fb07f1cdb2@redhat.com> Date: Tue, 17 Dec 2019 10:08:23 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.1.1 MIME-Version: 1.0 In-Reply-To: <87h81zwdmw.fsf@linaro.org> Content-Language: en-US X-MC-Unique: MDJjIkMHNsC6HbYjkGl8LA-1 X-Mimecast-Spam-Score: 0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 207.211.31.120 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 17 Dec 2019 09:08:30 -0000 On 17/12/19 09:38, Alex Benn=C3=A9e wrote: > Thread 3 (Thread 0x7f8b1959e700 (LWP 14017)): > #0 0x00007f8b2ada900c in futex_wait_cancelable (private=3D0, expected= =3D0, futex_word=3D0x56213f5482e8 ) at ../sysdeps/unix/sysv/li= nux/futex-internal.h:88 > #1 0x00007f8b2ada900c in __pthread_cond_wait_common (abstime=3D0x0, mu= tex=3D0x56213f548298 , cond=3D0x56213f5482c0 ) at p= thread_cond_wait.c:502 > #2 0x00007f8b2ada900c in __pthread_cond_wait (cond=3Dcond@entry=3D0x56= 213f5482c0 , mutex=3Dmutex@entry=3D0x56213f548298 )= at pthread_cond_wait.c:655 > #3 0x000056213ea31a40 in qemu_semihosting_console_inc (env=3Denv@entry= =3D0x56214138a680) at /home/alex/lsrc/qemu.git/hw/semihosting/console.c:151 > #4 0x000056213eab96e8 in do_arm_semihosting (env=3Denv@entry=3D0x56214= 138a680) at /home/alex/lsrc/qemu.git/target/arm/arm-semi.c:805 > #5 0x000056213eacd521 in handle_semihosting (cs=3D) at = /home/alex/lsrc/qemu.git/target/arm/helper.c:8476 > #6 0x000056213eacd521 in arm_cpu_do_interrupt (cs=3D) a= t /home/alex/lsrc/qemu.git/target/arm/helper.c:8522 > #7 0x000056213e9e53d0 in cpu_handle_exception (ret=3D, cpu=3D0x5621411fe2f0) at /home/alex/lsrc/qemu.git/accel/tcg/cpu-exec.c:= 503 > #8 0x000056213e9e53d0 in cpu_exec (cpu=3Dcpu@entry=3D0x562141381550) a= t /home/alex/lsrc/qemu.git/accel/tcg/cpu-exec.c:711 > #9 0x000056213e9b4f1f in tcg_cpu_exec (cpu=3D0x562141381550) at /home/= alex/lsrc/qemu.git/cpus.c:1473 > #10 0x000056213e9b715b in qemu_tcg_cpu_thread_fn (arg=3Darg@entry=3D0x5= 62141381550) at /home/alex/lsrc/qemu.git/cpus.c:1781 > #11 0x000056213ef026fa in qemu_thread_start (args=3D) at= /home/alex/lsrc/qemu.git/util/qemu-thread-posix.c:519 > #12 0x00007f8b2ada2fa3 in start_thread (arg=3D) at pthre= ad_create.c:486 > #13 0x00007f8b2acd14cf in clone () at ../sysdeps/unix/sysv/linux/x86_64= /clone.S:95 >=20 > Thread 1 (Thread 0x7f8b1c151680 (LWP 14010)): > #0 0x00007f8b2ada900c in futex_wait_cancelable (private=3D0, expected= =3D0, futex_word=3D0x56213f52c7c8 ) at ../sysdeps/unix/= sysv/linux/futex-internal.h:88 > #1 0x00007f8b2ada900c in __pthread_cond_wait_common (abstime=3D0x0, mu= tex=3D0x56213f52c8c0 , cond=3D0x56213f52c7a0 ) at pthread_cond_wait.c:502 > #2 0x00007f8b2ada900c in __pthread_cond_wait (cond=3Dcond@entry=3D0x56= 213f52c7a0 , mutex=3Dmutex@entry=3D0x56213f52c8c0 ) at pthread_cond_wait.c:655 > #3 0x000056213ef02e2b in qemu_cond_wait_impl (cond=3D0x56213f52c7a0 , mutex=3D0x56213f52c8c0 , file=3D0x56213= ef43700 "/home/alex/lsrc/qemu.git/cpus.c", line=3D1943) at /home/alex/lsrc/= qemu.git/util/qemu-thread-posix.c:173 > #4 0x000056213e9b74a4 in pause_all_vcpus () at /home/alex/lsrc/qemu.gi= t/cpus.c:1943 > #5 0x000056213e9b74a4 in pause_all_vcpus () at /home/alex/lsrc/qemu.gi= t/cpus.c:1923 > #6 0x000056213e9b7532 in do_vm_stop (state=3DRUN_STATE_SHUTDOWN, send_= stop=3D) at /home/alex/lsrc/qemu.git/cpus.c:1102 > #7 0x000056213e96b8fc in main (argc=3D, argv=3D, envp=3D) at /home/alex/lsrc/qemu.git/vl.c:4473 >=20 > I guess my first question is why do we need a separate mutex/cond > variable for this operation? This seems like the sort of thing that the > BQL could protect. No, please do not introduce more uses of the BQL from the CPU thread. The problem seems to lie with the condition variable, not the mutex. > Secondly if the vCPU is paused (via console or gdbstub) we need to > unwind from our blocking position and be in a position to restart > cleanly. Perhaps if fifo8_is_empty(&c->fifo) the CPU could update the PC back to the SVC instruction and enter a halted state? Perhaps with a new CPU_INTERRUPT_* flag that would be checked in arm_cpu_has_work. Paolo From MAILER-DAEMON Tue Dec 17 04:40:29 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1ih9LA-0004Xd-Sg for mharc-qemu-arm@gnu.org; Tue, 17 Dec 2019 04:40:28 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:53223) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ih9L8-0004VP-5M for qemu-arm@nongnu.org; Tue, 17 Dec 2019 04:40:27 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ih9L4-0004yl-Mt for qemu-arm@nongnu.org; Tue, 17 Dec 2019 04:40:23 -0500 Received: from us-smtp-1.mimecast.com ([207.211.31.81]:30774 helo=us-smtp-delivery-1.mimecast.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1ih9L4-0004yO-6a for qemu-arm@nongnu.org; Tue, 17 Dec 2019 04:40:22 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1576575621; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=AtKy5mnNV7pDyud3HaDZYd/omSd7p3W/KoK9NNhXKOk=; b=TNyX02SfcHnhh0OM/ZwsCgw/URsVNDvuA3tvq6gf08/PAnzTrU0nCzeC/rcT2pRIVMESXf SDCLKKkdmkNGi0AFEG1okvqhNy2h+bcAFl0Ad//TDiisB9y8l00WFVaCfj/nchjVDP7Etr uAIyflxqnYRIgCAOXrVJMI+a4c9Aa1s= Received: from mimecast-mx01.redhat.com (mimecast-mx01.redhat.com [209.132.183.4]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-297-JgchU4QeMq6aXlw9Hs__2w-1; Tue, 17 Dec 2019 04:40:20 -0500 Received: from smtp.corp.redhat.com (int-mx04.intmail.prod.int.phx2.redhat.com [10.5.11.14]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx01.redhat.com (Postfix) with ESMTPS id F40921809A29; Tue, 17 Dec 2019 09:40:18 +0000 (UTC) Received: from [10.36.116.117] (ovpn-116-117.ams2.redhat.com [10.36.116.117]) by smtp.corp.redhat.com (Postfix) with ESMTPS id F30505D9E2; Tue, 17 Dec 2019 09:40:17 +0000 (UTC) Subject: Re: [PATCH v3 4/6] hw/arm/smmuv3: Align stream table base address to table size To: Simon Veith , qemu-devel@nongnu.org, qemu-arm@nongnu.org References: <1576509312-13083-1-git-send-email-sveith@amazon.de> <1576509312-13083-5-git-send-email-sveith@amazon.de> From: Auger Eric Message-ID: <48ccf9fe-eb28-d138-7de7-3c658c5458a4@redhat.com> Date: Tue, 17 Dec 2019 10:40:16 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101 Thunderbird/60.4.0 MIME-Version: 1.0 In-Reply-To: <1576509312-13083-5-git-send-email-sveith@amazon.de> Content-Language: en-US X-Scanned-By: MIMEDefang 2.79 on 10.5.11.14 X-MC-Unique: JgchU4QeMq6aXlw9Hs__2w-1 X-Mimecast-Spam-Score: 0 Content-Type: text/plain; charset=windows-1252 Content-Transfer-Encoding: 7bit X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 207.211.31.81 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 17 Dec 2019 09:40:27 -0000 Hi Simon, On 12/16/19 4:15 PM, Simon Veith wrote: > Per the specification, and as observed in hardware, the SMMUv3 aligns > the SMMU_STRTAB_BASE address to the size of the table by masking out the > respective least significant bits in the ADDR field. > > Apply this masking logic to our smmu_find_ste() lookup function per the > specification. > > ref. ARM IHI 0070C, section 6.3.23. > > Signed-off-by: Simon Veith > Cc: Eric Auger > Cc: qemu-devel@nongnu.org > Cc: qemu-arm@nongnu.org Looks good to me. Acked-by: Eric Auger Thanks Eric > --- > Changed in v2: > > * Now using MAKE_64BIT_MASK() > * Eliminated unnecessary branches by using MAX() > * Removed unnecessary range check against DMA_ADDR_BITS > > hw/arm/smmuv3.c | 18 ++++++++++++++---- > 1 file changed, 14 insertions(+), 4 deletions(-) > > diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c > index 727558b..31ac3ca 100644 > --- a/hw/arm/smmuv3.c > +++ b/hw/arm/smmuv3.c > @@ -376,8 +376,9 @@ bad_ste: > static int smmu_find_ste(SMMUv3State *s, uint32_t sid, STE *ste, > SMMUEventInfo *event) > { > - dma_addr_t addr; > + dma_addr_t addr, strtab_base; > uint32_t log2size; > + int strtab_size_shift; > int ret; > > trace_smmuv3_find_ste(sid, s->features, s->sid_split); > @@ -391,10 +392,16 @@ static int smmu_find_ste(SMMUv3State *s, uint32_t sid, STE *ste, > } > if (s->features & SMMU_FEATURE_2LVL_STE) { > int l1_ste_offset, l2_ste_offset, max_l2_ste, span; > - dma_addr_t strtab_base, l1ptr, l2ptr; > + dma_addr_t l1ptr, l2ptr; > STEDesc l1std; > > - strtab_base = s->strtab_base & SMMU_BASE_ADDR_MASK; > + /* > + * Align strtab base address to table size. For this purpose, assume it > + * is not bounded by SMMU_IDR1_SIDSIZE. > + */ > + strtab_size_shift = MAX(5, (int)log2size - s->sid_split - 1 + 3); > + strtab_base = s->strtab_base & SMMU_BASE_ADDR_MASK & > + ~MAKE_64BIT_MASK(0, strtab_size_shift); > l1_ste_offset = sid >> s->sid_split; > l2_ste_offset = sid & ((1 << s->sid_split) - 1); > l1ptr = (dma_addr_t)(strtab_base + l1_ste_offset * sizeof(l1std)); > @@ -433,7 +440,10 @@ static int smmu_find_ste(SMMUv3State *s, uint32_t sid, STE *ste, > } > addr = l2ptr + l2_ste_offset * sizeof(*ste); > } else { > - addr = (s->strtab_base & SMMU_BASE_ADDR_MASK) + sid * sizeof(*ste); > + strtab_size_shift = log2size + 5; > + strtab_base = s->strtab_base & SMMU_BASE_ADDR_MASK & > + ~MAKE_64BIT_MASK(0, strtab_size_shift); > + addr = strtab_base + sid * sizeof(*ste); > } > > if (smmu_get_ste(s, addr, ste, event)) { > From MAILER-DAEMON Tue Dec 17 04:51:21 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1ih9Vh-0006nf-F7 for mharc-qemu-arm@gnu.org; Tue, 17 Dec 2019 04:51:21 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:58580) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ih9Ve-0006nM-IT for qemu-arm@nongnu.org; Tue, 17 Dec 2019 04:51:20 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ih9Vd-0005m7-1J for qemu-arm@nongnu.org; Tue, 17 Dec 2019 04:51:18 -0500 Received: from mail-wr1-x444.google.com ([2a00:1450:4864:20::444]:33064) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ih9Vc-0005lC-PM for qemu-arm@nongnu.org; Tue, 17 Dec 2019 04:51:16 -0500 Received: by mail-wr1-x444.google.com with SMTP id b6so10580330wrq.0 for ; Tue, 17 Dec 2019 01:51:16 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=references:user-agent:from:to:cc:subject:in-reply-to:date :message-id:mime-version:content-transfer-encoding; bh=NaKJgMspXK96PXPoxqU5GH9h7fCR/dnwBXYabK2mpw0=; b=cAIc/AxKJtt2hHo7ofHUIhkREZgqGhaYIhJdMu08F3fPmStTWD3NPY5NI05Rd46Qxi zbXBmsW1dxBOsnZBqohXZuHxNqQ5r2ZNl9Po5hYD0cvJ9LCKvX6aSVwlA7i+KNfggC32 VzugRsX2/UATIKcYp+/CMY/Hd0wAevcLlKFnqxNwC9pW52qOHTorLraFAG7wu7fbSdci jJh0JHLlKq/CQjwg1TiWR4YYVwQlNvy+ASg2vFw+XBX0/Kla3rVFHSpcuxFBAIWypvLm rBegYoHaRKmON6jbS7A6JxLLOZXZxLarPGe0LwwM5hduy5Nl/0C0O5/NKIjIGReF0O/A 8gpw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:references:user-agent:from:to:cc:subject :in-reply-to:date:message-id:mime-version:content-transfer-encoding; bh=NaKJgMspXK96PXPoxqU5GH9h7fCR/dnwBXYabK2mpw0=; b=hL1bHOhF0FTF6oeTdgZLU/i7BjSFvsWvIcQ71isfpY515hJqVNHGTMHndH/fNE39ci LLWXR6fiOajxNAhHKnpHEqaoJiBYGwgSKYTbSzpBTcYTQPGYdmD2DxCMxzEm4E73VHxK Shmg3mqOl4oy+3yVjmdfutWG87KF3fTwT9Vq0M6OtnUZodyH0bhm8ruYs9BEpEb036uq A2rbRFfgWbp/pTN/cgXcQ2T/W/5gAFViTnFtSpVnscqn/G8FX3QOM6JNYl3PQG6c5Cyt 5fWMr/r3XEANHKq40vBQ59M5ns2OOETjXuk+ZeMZ8oc6kCQVQ/ZLp7GMIY95Td5hr1v3 8SFg== X-Gm-Message-State: APjAAAULUvBWtY7vsZbJti5oYVCbS/7BZT3v476vPiiZMI+jA6G+t6f2 Ku05K/Q1BmpfFjvhwQQeQ6DxfQ== X-Google-Smtp-Source: APXvYqxsdWLa7CWRH1VHH+fWhTsR8W03M/+76VkWVTBrHbb/FIArc9XIx2y/QA0c/A+hZFUoHZCwLQ== X-Received: by 2002:a05:6000:1052:: with SMTP id c18mr35828773wrx.268.1576576275364; Tue, 17 Dec 2019 01:51:15 -0800 (PST) Received: from zen.linaroharston ([51.148.130.216]) by smtp.gmail.com with ESMTPSA id w22sm2250615wmk.34.2019.12.17.01.51.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 17 Dec 2019 01:51:14 -0800 (PST) Received: from zen (localhost [127.0.0.1]) by zen.linaroharston (Postfix) with ESMTP id 4A9FD1FF87; Tue, 17 Dec 2019 09:51:13 +0000 (GMT) References: <87h83w4dod.fsf@keithp.com> <20191104204230.12249-1-keithp@keithp.com> <87h81zwdmw.fsf@linaro.org> <5a3b1155-4242-831c-8ae4-e9fb07f1cdb2@redhat.com> User-agent: mu4e 1.3.5; emacs 27.0.50 From: Alex =?utf-8?Q?Benn=C3=A9e?= To: Paolo Bonzini Cc: Keith Packard , qemu-devel@nongnu.org, Peter Maydell , Riku Voipio , Laurent Vivier , qemu-arm@nongnu.org Subject: Re: [PATCH] Semihost SYS_READC implementation (v6) In-reply-to: <5a3b1155-4242-831c-8ae4-e9fb07f1cdb2@redhat.com> Date: Tue, 17 Dec 2019 09:51:13 +0000 Message-ID: <87eex3wa9a.fsf@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::444 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 17 Dec 2019 09:51:20 -0000 Paolo Bonzini writes: > On 17/12/19 09:38, Alex Benn=C3=A9e wrote: >> Thread 3 (Thread 0x7f8b1959e700 (LWP 14017)): >> #0 0x00007f8b2ada900c in futex_wait_cancelable (private=3D0, expected= =3D0, futex_word=3D0x56213f5482e8 ) at ../sysdeps/unix/sysv/li= nux/futex-internal.h:88 >> #1 0x00007f8b2ada900c in __pthread_cond_wait_common (abstime=3D0x0, m= utex=3D0x56213f548298 , cond=3D0x56213f5482c0 ) at = pthread_cond_wait.c:502 >> #2 0x00007f8b2ada900c in __pthread_cond_wait (cond=3Dcond@entry=3D0x5= 6213f5482c0 , mutex=3Dmutex@entry=3D0x56213f548298 = ) at pthread_cond_wait.c:655 >> #3 0x000056213ea31a40 in qemu_semihosting_console_inc (env=3Denv@entr= y=3D0x56214138a680) at /home/alex/lsrc/qemu.git/hw/semihosting/console.c:151 >> #4 0x000056213eab96e8 in do_arm_semihosting (env=3Denv@entry=3D0x5621= 4138a680) at /home/alex/lsrc/qemu.git/target/arm/arm-semi.c:805 >> #5 0x000056213eacd521 in handle_semihosting (cs=3D) at= /home/alex/lsrc/qemu.git/target/arm/helper.c:8476 >> #6 0x000056213eacd521 in arm_cpu_do_interrupt (cs=3D) = at /home/alex/lsrc/qemu.git/target/arm/helper.c:8522 >> #7 0x000056213e9e53d0 in cpu_handle_exception (ret=3D, cpu=3D0x5621411fe2f0) at /home/alex/lsrc/qemu.git/accel/tcg/cpu-exec.c= :503 >> #8 0x000056213e9e53d0 in cpu_exec (cpu=3Dcpu@entry=3D0x562141381550) = at /home/alex/lsrc/qemu.git/accel/tcg/cpu-exec.c:711 >> #9 0x000056213e9b4f1f in tcg_cpu_exec (cpu=3D0x562141381550) at /home= /alex/lsrc/qemu.git/cpus.c:1473 >> #10 0x000056213e9b715b in qemu_tcg_cpu_thread_fn (arg=3Darg@entry=3D0x= 562141381550) at /home/alex/lsrc/qemu.git/cpus.c:1781 >> #11 0x000056213ef026fa in qemu_thread_start (args=3D) a= t /home/alex/lsrc/qemu.git/util/qemu-thread-posix.c:519 >> #12 0x00007f8b2ada2fa3 in start_thread (arg=3D) at pthr= ead_create.c:486 >> #13 0x00007f8b2acd14cf in clone () at ../sysdeps/unix/sysv/linux/x86_6= 4/clone.S:95 >> >> Thread 1 (Thread 0x7f8b1c151680 (LWP 14010)): >> #0 0x00007f8b2ada900c in futex_wait_cancelable (private=3D0, expected= =3D0, futex_word=3D0x56213f52c7c8 ) at ../sysdeps/unix/= sysv/linux/futex-internal.h:88 >> #1 0x00007f8b2ada900c in __pthread_cond_wait_common (abstime=3D0x0, m= utex=3D0x56213f52c8c0 , cond=3D0x56213f52c7a0 ) at pthread_cond_wait.c:502 >> #2 0x00007f8b2ada900c in __pthread_cond_wait (cond=3Dcond@entry=3D0x5= 6213f52c7a0 , mutex=3Dmutex@entry=3D0x56213f52c8c0 ) at pthread_cond_wait.c:655 >> #3 0x000056213ef02e2b in qemu_cond_wait_impl (cond=3D0x56213f52c7a0 <= qemu_pause_cond>, mutex=3D0x56213f52c8c0 , file=3D0x5621= 3ef43700 "/home/alex/lsrc/qemu.git/cpus.c", line=3D1943) at /home/alex/lsrc= /qemu.git/util/qemu-thread-posix.c:173 >> #4 0x000056213e9b74a4 in pause_all_vcpus () at /home/alex/lsrc/qemu.g= it/cpus.c:1943 >> #5 0x000056213e9b74a4 in pause_all_vcpus () at /home/alex/lsrc/qemu.g= it/cpus.c:1923 >> #6 0x000056213e9b7532 in do_vm_stop (state=3DRUN_STATE_SHUTDOWN, send= _stop=3D) at /home/alex/lsrc/qemu.git/cpus.c:1102 >> #7 0x000056213e96b8fc in main (argc=3D, argv=3D, envp=3D) at /home/alex/lsrc/qemu.git/vl.c:4473 >> >> I guess my first question is why do we need a separate mutex/cond >> variable for this operation? This seems like the sort of thing that the >> BQL could protect. > > No, please do not introduce more uses of the BQL from the CPU thread. > The problem seems to lie with the condition variable, not the mutex. Well in this case we are holding the BQL anyway as we are being called from the interrupt context. The BQL protects all shared HW state outside of MMIO which is explicitly marked as doing it's own locking. That said I don't know if the semihosting console will always be called from a BQL held context. > >> Secondly if the vCPU is paused (via console or gdbstub) we need to >> unwind from our blocking position and be in a position to restart >> cleanly. > > Perhaps if fifo8_is_empty(&c->fifo) the CPU could update the PC back to > the SVC instruction and enter a halted state? Perhaps with a new > CPU_INTERRUPT_* flag that would be checked in arm_cpu_has_work. I don't think the PC has been updated at this point - but we don't want that logic in the common semihosting code. If we cpu_loop_exit the exception is still in effect and will re-run when we start again. What we really want to do is fall back to the same halting semantics that leave us in qemu_wait_io_event until there is something to process. Is there any particular reason a blocking semihosting event isn't like any other IO event? > > Paolo -- Alex Benn=C3=A9e From MAILER-DAEMON Tue Dec 17 05:04:11 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1ih9i7-0002Uh-F7 for mharc-qemu-arm@gnu.org; Tue, 17 Dec 2019 05:04:11 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:35947) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ih9i4-0002U9-4p for qemu-arm@nongnu.org; Tue, 17 Dec 2019 05:04:09 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ih9i3-00069S-55 for qemu-arm@nongnu.org; Tue, 17 Dec 2019 05:04:08 -0500 Received: from us-smtp-1.mimecast.com ([205.139.110.61]:52798 helo=us-smtp-delivery-1.mimecast.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1ih9i3-00069N-1l for qemu-arm@nongnu.org; Tue, 17 Dec 2019 05:04:07 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1576577046; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=YTdJ9BlYlKA52aob596FqEnZ+Y7D0Vb4IPmF21pH2xE=; b=iXDgfssS+voa5Nm0EnIQqSjlNvkMRazNB5qInEMQoOVDnY2t+pgQVeMgjrlWc6zSXQk/OL 0vHF3N/GEU/ODT5PvyqsJGsEB+ZLK6Nn05PD3uvZY4vrSyXwWY8tlVQlfQP7N2MRaBSctN NRSak4M0qZmzmtr/5FBVwQh0oyCcqpY= Received: from mimecast-mx01.redhat.com (mimecast-mx01.redhat.com [209.132.183.4]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-40-ct_whX23NC2rkIxa7qnbow-1; Tue, 17 Dec 2019 05:04:03 -0500 Received: from smtp.corp.redhat.com (int-mx03.intmail.prod.int.phx2.redhat.com [10.5.11.13]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx01.redhat.com (Postfix) with ESMTPS id 6C012107ACC7; Tue, 17 Dec 2019 10:04:02 +0000 (UTC) Received: from [10.36.116.117] (ovpn-116-117.ams2.redhat.com [10.36.116.117]) by smtp.corp.redhat.com (Postfix) with ESMTPS id 8D3A37C836; Tue, 17 Dec 2019 10:04:01 +0000 (UTC) Subject: Re: [PATCH v3 0/6] hw/arm/smmuv3: Correct stream ID and event address handling To: Simon Veith , qemu-devel@nongnu.org, qemu-arm@nongnu.org References: <1576509312-13083-1-git-send-email-sveith@amazon.de> From: Auger Eric Message-ID: Date: Tue, 17 Dec 2019 11:03:59 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101 Thunderbird/60.4.0 MIME-Version: 1.0 In-Reply-To: <1576509312-13083-1-git-send-email-sveith@amazon.de> Content-Language: en-US X-Scanned-By: MIMEDefang 2.79 on 10.5.11.13 X-MC-Unique: ct_whX23NC2rkIxa7qnbow-1 X-Mimecast-Spam-Score: 0 Content-Type: text/plain; charset=windows-1252 Content-Transfer-Encoding: 7bit X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 205.139.110.61 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 17 Dec 2019 10:04:09 -0000 Hi, On 12/16/19 4:15 PM, Simon Veith wrote: > While working on the Linux SMMUv3 driver, I noticed a few cases where the QEMU > SMMUv3 behavior relating to stream tables was inconsistent with our hardware. > > Also, when debugging those differences, I found that the errors reported through > the QEMU SMMUv3 event queue contained the address fields in an incorrect > position. > > These patches correct the QEMU SMMUv3 behavior to match the specification (and > the behavior that I observed in our hardware). Linux guests normally will not > notice these issues, but other SMMUv3 driver implementations might. > > Changes in v2: > > * New patch "hw/arm/smmuv3: Correct SMMU_BASE_ADDR_MASK value" added > * Updated patch "hw/arm/smmuv3: Check stream IDs against actual table LOG2SIZE" > * Updated patch "hw/arm/smmuv3: Align stream table base address to table size" > > Changes in v3: > > * No changes, but sending again to correct a patch submission mishap that > confused Patchew > > Simon Veith (6): > hw/arm/smmuv3: Apply address mask to linear strtab base address > hw/arm/smmuv3: Correct SMMU_BASE_ADDR_MASK value > hw/arm/smmuv3: Check stream IDs against actual table LOG2SIZE > hw/arm/smmuv3: Align stream table base address to table size > hw/arm/smmuv3: Use correct bit positions in EVT_SET_ADDR2 macro > hw/arm/smmuv3: Report F_STE_FETCH fault address in correct word > position The series looks good to me. Also tested against non regression. Tested-by: Eric Auger Thanks Eric > > hw/arm/smmuv3-internal.h | 6 +++--- > hw/arm/smmuv3.c | 28 +++++++++++++++++++++------- > 2 files changed, 24 insertions(+), 10 deletions(-) > From MAILER-DAEMON Tue Dec 17 05:04:45 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1ih9if-00038p-O4 for mharc-qemu-arm@gnu.org; Tue, 17 Dec 2019 05:04:45 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:35989) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ih9iZ-00031q-Es for qemu-arm@nongnu.org; Tue, 17 Dec 2019 05:04:44 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ih9iY-0006En-Dm for qemu-arm@nongnu.org; Tue, 17 Dec 2019 05:04:39 -0500 Received: from us-smtp-delivery-1.mimecast.com ([205.139.110.120]:25315 helo=us-smtp-1.mimecast.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1ih9iY-0006Ec-Al for qemu-arm@nongnu.org; Tue, 17 Dec 2019 05:04:38 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1576577077; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=loAK4kVwopibUcm9RXYBoS7F17AJtpqG86ZIEZJUItE=; b=EYzMOHii4hYjKZmVmwsEU53avx8e53dyuhrXTujWJ5OEJhIEE85MScDR0ep0SXIWR5ECu7 AkX/6yI+YNn6KDW45nizX9yHsOHYUX8yTygp8dzxedsDisJiwYxWEh+X9lMPpmaZIGQ3e3 4nXax4TvxPowOpf3lm3AqzRXfXx77P8= Received: from mail-wr1-f72.google.com (mail-wr1-f72.google.com [209.85.221.72]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-414-4vvbIthCPZ6JJe8jmeVPzg-1; Tue, 17 Dec 2019 05:04:35 -0500 Received: by mail-wr1-f72.google.com with SMTP id c17so5114328wrp.10 for ; Tue, 17 Dec 2019 02:04:35 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:subject:to:cc:references:from:message-id:date :user-agent:mime-version:in-reply-to:content-language :content-transfer-encoding; bh=D6qcer7pEfC9pWYO7pBi1lXIWSygHQ8u1k+W/Teuk1I=; b=B2q58OjI9LdySISYiwGmxUYDnD693UJ+4nERNa7Oy9inlC6iNdbn/mc/NN4f5s2MqJ vQBBNhTk09fHC+8tkMWzmlfGV4n7N0F1RjWXxPLCZQbu4D7YgcmKfCv0U2kWyF71VP+6 LnlgLi53/hklEex+w/JzBA3CEuBL/qFK50bMKGmYFShbv1Gc7XMTgaRHiUPO1wka+Pp5 gEJg/HRfO9Nwotbg5ur8B/r65bawRz3QmqAcq3FRmxoLQ2KMEZpA94PNYcX20lo85SKW 7t9OZuVbQH8t9lfSfAxFcWBCklETNDGJ2TNJLKcxqW8wKVZ/XRby2Mc5yTYSaaCJJ9ub G0OQ== X-Gm-Message-State: APjAAAWH83XIZSeSgrjODqnTUQcz/uZDWg8dmjQbP7jl06zsCJJ4aTNw wybfP+DFbJdl8ibJ0dLgelEsig7nb8xOOJf/X0cmFpixppIXqEAGXV1b8Zb5P4Y+ad0897CoaK0 7GC2zqHzCX1ZT X-Received: by 2002:a7b:cc97:: with SMTP id p23mr4646945wma.89.1576577074003; Tue, 17 Dec 2019 02:04:34 -0800 (PST) X-Google-Smtp-Source: APXvYqxjBawQMNs9dzsP9xZl/9p00EI/6jhUNWsR0TLx5Mmfp3lKCVP1M4gP5if+xKyTno73Wi6ryQ== X-Received: by 2002:a7b:cc97:: with SMTP id p23mr4646911wma.89.1576577073720; Tue, 17 Dec 2019 02:04:33 -0800 (PST) Received: from ?IPv6:2001:b07:6468:f312:503f:4ffc:fc4a:f29a? ([2001:b07:6468:f312:503f:4ffc:fc4a:f29a]) by smtp.gmail.com with ESMTPSA id v83sm2480731wmg.16.2019.12.17.02.04.32 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 17 Dec 2019 02:04:33 -0800 (PST) Subject: Re: [PATCH] Semihost SYS_READC implementation (v6) To: =?UTF-8?Q?Alex_Benn=c3=a9e?= Cc: Keith Packard , qemu-devel@nongnu.org, Peter Maydell , Riku Voipio , Laurent Vivier , qemu-arm@nongnu.org References: <87h83w4dod.fsf@keithp.com> <20191104204230.12249-1-keithp@keithp.com> <87h81zwdmw.fsf@linaro.org> <5a3b1155-4242-831c-8ae4-e9fb07f1cdb2@redhat.com> <87eex3wa9a.fsf@linaro.org> From: Paolo Bonzini Message-ID: <77dd4863-6301-b17d-529c-451d491d4794@redhat.com> Date: Tue, 17 Dec 2019 11:04:33 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.1.1 MIME-Version: 1.0 In-Reply-To: <87eex3wa9a.fsf@linaro.org> Content-Language: en-US X-MC-Unique: 4vvbIthCPZ6JJe8jmeVPzg-1 X-Mimecast-Spam-Score: 0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 205.139.110.120 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 17 Dec 2019 10:04:44 -0000 On 17/12/19 10:51, Alex Benn=C3=A9e wrote: >>> Secondly if the vCPU is paused (via console or gdbstub) we need to >>> unwind from our blocking position and be in a position to restart >>> cleanly. >> Perhaps if fifo8_is_empty(&c->fifo) the CPU could update the PC back to >> the SVC instruction and enter a halted state? Perhaps with a new >> CPU_INTERRUPT_* flag that would be checked in arm_cpu_has_work. > I don't think the PC has been updated at this point - but we don't want > that logic in the common semihosting code. If we cpu_loop_exit the > exception is still in effect and will re-run when we start again. So that would work? cpu_loop_exit if the FIFO is empty, reentering via cpu_interrupt and clearing the interrupt signal in do_arm_semihosting. > What we really want to do is fall back to the same halting semantics > that leave us in qemu_wait_io_event until there is something to process. > Is there any particular reason a blocking semihosting event isn't like > any other IO event? The "io" in wait_io_event really stands for "iothread". Usually in system emulation "waiting for I/O events" means "waiting for an interrupt" with a halt instruction (for ARM, WFE/WFI), hence my suggestion. Thanks, Paolo From MAILER-DAEMON Tue Dec 17 10:25:28 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1ihEj2-0002x7-FP for mharc-qemu-arm@gnu.org; Tue, 17 Dec 2019 10:25:28 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:48633) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ihEiz-0002vb-3T for qemu-arm@nongnu.org; Tue, 17 Dec 2019 10:25:26 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ihEix-0000Fw-D9 for qemu-arm@nongnu.org; Tue, 17 Dec 2019 10:25:24 -0500 Received: from mail-oi1-x241.google.com ([2607:f8b0:4864:20::241]:36304) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ihEix-00007J-5u for qemu-arm@nongnu.org; Tue, 17 Dec 2019 10:25:23 -0500 Received: by mail-oi1-x241.google.com with SMTP id c16so4882471oic.3 for ; Tue, 17 Dec 2019 07:25:22 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=O1r3TUAOg93CqYB/EqAX5MDLFd3UQVOc322Wa0FEsFo=; b=eIL0GvhZlsZfWhCqXhOuOjIlI/H1KiFYYdsdfwqzsfTSkLm/nMGu4AmJLRBQ93oh4F NjWewEWYr9bXQHGC5ETYFY7YpnfYDpW321rVzuRvAIpscY+Y/i88jAHlWIC3yZIXmAsh uReP53ITxTynhp93oBw0xr4QWNHDA+R3HYdSUXiQatErkfxq/FmNgjYBr4UaLEZsPKYh JmNV82E91rGRa5Adb6cMqzn9D3Zlzpk+rGblS7+Of7KUfmyhHCpEzLGBoh68jTMf5o9e 9Hzh4wTlin/5V51LBqX1AVQW/HyWTupfmYrGGj9ikF/R1YTuVDBqgSmWjOaV4iSCWwCB T4NA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=O1r3TUAOg93CqYB/EqAX5MDLFd3UQVOc322Wa0FEsFo=; b=tYyhAcqJGbFGrWOwsAHo88vAtiXeUlyJOCRr7bAm+NgqUF7psPpTuYe9fajXJf9T9P EDkQ3H2eRgQeknV8iLevjSh1JNGID4DoMaYwd3oOmYqH9YpxPzzCk1MjsE2Tiv4IM1rf 5eQb7YymAnvrFKwU31ZIB/R/Aq5jo7mSQJh9IwuGbTaUorBBnWustnUbAdEgRFQcVkcF vUxNV9gOqYScm6GvhANsCVsH05wx8ABbQIJ7YemzwPJKmr5pSPgXfVWO90J/huuhjC2S LJESaL9aVEzuiAzJSUDp3DIUfH0AVTgCUFYyYZL1dF5e2SQ8CKZFtTM2V5+D7m8g7XA8 Szng== X-Gm-Message-State: APjAAAVtFQPWP7DRCKxTendJSXZVA6YB64ZsXGbbr1IPdcmrcEN21tPH CVRkt8N9ujHF1wveBQ9XIOFLvImPCYKNNdqipis/NO9K X-Google-Smtp-Source: APXvYqzB0L7+zB5wZq+qzxFGi71HyTkNBnmrBXnv95tupDZwv3uCZSD/pAuvxBU6/h0ku3PA2dxE29PlgH0cGzqtzOY= X-Received: by 2002:aca:3182:: with SMTP id x124mr1903142oix.170.1576596321508; Tue, 17 Dec 2019 07:25:21 -0800 (PST) MIME-Version: 1.0 References: <1576509312-13083-1-git-send-email-sveith@amazon.de> In-Reply-To: From: Peter Maydell Date: Tue, 17 Dec 2019 15:25:10 +0000 Message-ID: Subject: Re: [PATCH v3 0/6] hw/arm/smmuv3: Correct stream ID and event address handling To: Auger Eric Cc: Simon Veith , QEMU Developers , qemu-arm Content-Type: text/plain; charset="UTF-8" X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::241 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 17 Dec 2019 15:25:26 -0000 On Tue, 17 Dec 2019 at 10:04, Auger Eric wrote: > > Hi, > > On 12/16/19 4:15 PM, Simon Veith wrote: > > While working on the Linux SMMUv3 driver, I noticed a few cases where the QEMU > > SMMUv3 behavior relating to stream tables was inconsistent with our hardware. > > > > Also, when debugging those differences, I found that the errors reported through > > the QEMU SMMUv3 event queue contained the address fields in an incorrect > > position. > > > > These patches correct the QEMU SMMUv3 behavior to match the specification (and > > the behavior that I observed in our hardware). Linux guests normally will not > > notice these issues, but other SMMUv3 driver implementations might. > > > > Changes in v2: > > > > * New patch "hw/arm/smmuv3: Correct SMMU_BASE_ADDR_MASK value" added > > * Updated patch "hw/arm/smmuv3: Check stream IDs against actual table LOG2SIZE" > > * Updated patch "hw/arm/smmuv3: Align stream table base address to table size" > > > > Changes in v3: > > > > * No changes, but sending again to correct a patch submission mishap that > > confused Patchew > > > > Simon Veith (6): > > hw/arm/smmuv3: Apply address mask to linear strtab base address > > hw/arm/smmuv3: Correct SMMU_BASE_ADDR_MASK value > > hw/arm/smmuv3: Check stream IDs against actual table LOG2SIZE > > hw/arm/smmuv3: Align stream table base address to table size > > hw/arm/smmuv3: Use correct bit positions in EVT_SET_ADDR2 macro > > hw/arm/smmuv3: Report F_STE_FETCH fault address in correct word > > position > > The series looks good to me. Also tested against non regression. > > Tested-by: Eric Auger Applied to target-arm.next, thanks. -- PMM From MAILER-DAEMON Tue Dec 17 10:26:05 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1ihEjd-0003e4-0a for mharc-qemu-arm@gnu.org; Tue, 17 Dec 2019 10:26:05 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:48866) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ihEja-0003aq-9e for qemu-arm@nongnu.org; Tue, 17 Dec 2019 10:26:03 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ihEjZ-00025p-26 for qemu-arm@nongnu.org; Tue, 17 Dec 2019 10:26:02 -0500 Received: from mail-oi1-x241.google.com ([2607:f8b0:4864:20::241]:43520) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ihEjY-00024n-TM for qemu-arm@nongnu.org; Tue, 17 Dec 2019 10:26:01 -0500 Received: by mail-oi1-x241.google.com with SMTP id x14so5621022oic.10 for ; Tue, 17 Dec 2019 07:26:00 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=8ZQpcmdFhoPYSXkvpwaIE1fkKiMdAPMiKMIsGUobd3g=; b=PV10CPPsYxW9zOszmgbucaI7wfLtUv0kHYU/nYgnM4Q0Zg1q8PC0QDf7jkJsu7thhP tjkM+QSQjOCpPxm3lWNo79Wx4NkYPq0OgkwrzD5EWpq+Ia6uV1wj6CGMAHamEnbeEwqm iktMkEuSnQhOrCWQ/wK8sQ5fE6MH2KxCfxk9Dz1H038tOrqVzS6wT7JMQ7EUlkeFBUmh mTUDN0tG6IMifNYcK1yzdbm9zF3SM1p97x23oRcEx47VGZdMu0vYjrlFRP84jk/4pyvv mZXO6lavmldyKHpVydkocdwEMY5wBlFZ9CR9XZwjfGAenIbwH+U1W54RtrI0qEVfCYnS Dc0w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=8ZQpcmdFhoPYSXkvpwaIE1fkKiMdAPMiKMIsGUobd3g=; b=QCYKCcJuMXIhBoJyFQEBrXtRqgE2Zvs6b+ecRvj0BF7aDjWGlLtt84WZ0vwL5qJG0o OVXzO23uutWMtdL1Fg57kB9RmZsb2JRQkKx5NtaXy2k5/qF3djELfaRViLr+8JY1UrzK 7R/JWPmrBwiyi6ThUi5Enfk74IH4KCSKp/9yKjmq6SqlbGdjdmmordydowyUXC3IgKH0 9te3xMB4yDltUlGXt4ufBd+8UO3mlEZD4cAYtoOV1DWX3vOYBfmbj/anfmf6Sgc1Rx7/ ZbFKoymSCHfSjexuQe10Dw8zaT6ScZTnLRObF/ytE54+oo1oGHVg4oUrua6v843LeNMc ayjQ== X-Gm-Message-State: APjAAAXcg2Rp/Flc3f9gTP1CE+8gZt2NNOXAnjk8vU0Eg7vVu2BVTPDe a9xLMqVoJOVQjk9YZY//4O32rkdP43gw+7cDwDBCuw== X-Google-Smtp-Source: APXvYqxYNd37Hpw4uovWW10bDgdN296lEMBikaqrj9beALKlzgcAiTaj8Vr2TZylbvQysub6fI10sIbEykjYYCnhAYo= X-Received: by 2002:aca:edd5:: with SMTP id l204mr1888883oih.98.1576596360313; Tue, 17 Dec 2019 07:26:00 -0800 (PST) MIME-Version: 1.0 References: In-Reply-To: From: Peter Maydell Date: Tue, 17 Dec 2019 15:25:49 +0000 Message-ID: Subject: Re: [PATCH v3 0/4] Expose GT CNTFRQ as a CPU property to support AST2600 To: Andrew Jeffery Cc: qemu-arm , =?UTF-8?Q?C=C3=A9dric_Le_Goater?= , Joel Stanley , QEMU Developers , =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= Content-Type: text/plain; charset="UTF-8" X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::241 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 17 Dec 2019 15:26:03 -0000 On Fri, 13 Dec 2019 at 05:48, Andrew Jeffery wrote: > > Hello, > > This is a v3 of the belated follow-up from a few of my earlier attempts to fix > up the ARM generic timer for correct behaviour on the ASPEED AST2600 SoC. The > AST2600 clocks the generic timer at the rate of HPLL, which is configured to > 1125MHz. This is significantly quicker than the currently hard-coded generic > timer rate of 62.5MHz and so we see "sticky" behaviour in the guest. > > v2 can be found here: > > https://patchwork.ozlabs.org/cover/1203474/ > > Changes since v2: > > * Address some minor review comments from Philippe and add tags > > Changes since v1: > > * Fix a user mode build failure from partial renaming of gt_cntfrq_period_ns() > * Add tags from Cedric and Richard > > Please review. > > Andrew > > Andrew Jeffery (4): > target/arm: Remove redundant scaling of nexttick > target/arm: Abstract the generic timer frequency > target/arm: Prepare generic timer for per-platform CNTFRQ > ast2600: Configure CNTFRQ at 1125MHz Applied to target-arm.next, thanks. -- PMM From MAILER-DAEMON Tue Dec 17 11:02:50 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1ihFJC-00030b-Ec for mharc-qemu-arm@gnu.org; Tue, 17 Dec 2019 11:02:50 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:37299) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ihFJA-0002zQ-2G for qemu-arm@nongnu.org; Tue, 17 Dec 2019 11:02:48 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ihFJ5-00076D-Cc for qemu-arm@nongnu.org; Tue, 17 Dec 2019 11:02:48 -0500 Received: from mail-ed1-x544.google.com ([2a00:1450:4864:20::544]:47095) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ihFJ5-00071N-5H for qemu-arm@nongnu.org; Tue, 17 Dec 2019 11:02:43 -0500 Received: by mail-ed1-x544.google.com with SMTP id m8so8415114edi.13 for ; Tue, 17 Dec 2019 08:02:43 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc:content-transfer-encoding; bh=mhgCXR0RlBMimws/8kYwml/G5AJF/CxRXmyzmxV/rEo=; b=miOFCoWACa1t7Ub1bcvz0Ej4/d+taBjjZPa5gSWdGYACB64UtIIBcZ8HsmEhazR7dz 1YflF0CxhZzTavgbIsjX2XnYddaum3mO+R08PN5Fpd+a53wSlw01FdriBUzuhPDmuptJ GKGb4M1cVG/qmrJF7Fq8V9A3nHrZOeJCKcRA3oVKG/1RNs5TEmrLmcXRqqPc+9/lH/hc 16MF55XHvtVq3PgP38LtuqHLPzw3grO7fk+PybO00zYm4k3SYC2XSD+s2Tw6SrmOLhUO AH9e7UH0kQ2YR/pbX2rjOxJKhMLFDw7Kc+263U643KUGPWzME94yTTAUUxT9EM+hDDhI t6gQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc:content-transfer-encoding; bh=mhgCXR0RlBMimws/8kYwml/G5AJF/CxRXmyzmxV/rEo=; b=KLAhTOe73KC0PNOktkz6UvQjuhgWyI5DaJYPIFfEzPkLQuQT1+xjaD/CCSPjZ7HjLy aO1ZoupIplM6WK46XxslvVNWls36N17QMhI90k0gKIYuTB755sb8ylSI0JL3qbw6DwsI NoPuz5nQibVD+GpKnAx306eM3kfusSEsskY/UDptE2MeOKkZJXxp05QtL7UH0cPStNLi so+fjG4BlF5Ru7hrXjp6zCCqTXlvvgUeTs2MD5dLELqEv307Q2C4xQwzCcX8I+zZsGa/ qxG2AGIsXzTq9ncUonFjLC/KiySvq2oZlI5OQdjL5p9SJuAIoVD/camzQwQeQsMQ5f5y 0ijg== X-Gm-Message-State: APjAAAUEx9A6nHihnK4fqrTI/ab/OVTpmy3vLCfv9XYfQQokZcKWT/qc +0jY77WXiSGi96TN0yk46wXIAKcb2Lr1O3/DLZWICQ== X-Google-Smtp-Source: APXvYqxBSSOhLFpaeMebz38V3lBaKHQf3pf4H3iwBzUFZPINt86gunvL/UTw+4C6IJE+i946iOVQPJQ/OROSIXwUbug= X-Received: by 2002:a05:6402:149a:: with SMTP id e26mr6197507edv.198.1576598561770; Tue, 17 Dec 2019 08:02:41 -0800 (PST) MIME-Version: 1.0 References: <20191209134552.27733-1-philmd@redhat.com> In-Reply-To: <20191209134552.27733-1-philmd@redhat.com> From: Richard Henderson Date: Tue, 17 Dec 2019 06:02:30 -1000 Message-ID: Subject: Re: [PATCH] target/arm: Display helpful message when hflags mismatch To: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= Cc: "qemu-devel@nongnu.org Developers" , Peter Maydell , qemu-arm , =?UTF-8?B?QWxleCBCZW5uw6ll?= Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::544 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 17 Dec 2019 16:02:49 -0000 On Mon, 9 Dec 2019 at 03:46, Philippe Mathieu-Daud=C3=A9 wrote: > > Instead of crashing in a confuse way, give some hint to the user > about why we aborted. He might report the issue without having > to use a debugger. > > Signed-off-by: Philippe Mathieu-Daud=C3=A9 > --- > target/arm/helper.c | 18 +++++++++++++++--- > 1 file changed, 15 insertions(+), 3 deletions(-) Reviewed-by: Richard Henderson r~ From MAILER-DAEMON Tue Dec 17 11:03:58 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1ihFKH-0004O8-SQ for mharc-qemu-arm@gnu.org; Tue, 17 Dec 2019 11:03:58 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:38016) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ihFKF-0004Lt-Nk for qemu-arm@nongnu.org; Tue, 17 Dec 2019 11:03:56 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ihFKE-0002F1-GL for qemu-arm@nongnu.org; Tue, 17 Dec 2019 11:03:55 -0500 Received: from mail-ot1-x342.google.com ([2607:f8b0:4864:20::342]:34853) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ihFKE-0002EQ-B4 for qemu-arm@nongnu.org; Tue, 17 Dec 2019 11:03:54 -0500 Received: by mail-ot1-x342.google.com with SMTP id f71so4738555otf.2 for ; Tue, 17 Dec 2019 08:03:54 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=Q/JxMM3NAomx6ykwazS1RjvqreMPIS0r/3fmUpKXorI=; b=axWRYFefeye5FfP+zMd5OTAmZRPvQUMATaOUIjVCy01y/g02z276Dwd+UP+AvBEYUh j4W2isW0KUNnTOZVYJo3QUorypyQwhQnzY1sEd7OtkJXHxeWlDhu1hlNsUylknMhyQWD vij+TnOdp29T+M5Q+zZnE/JqXRWcgv2Lhwt3HpquviOOcIAE5yz7fECqTNplInIoJKJ0 u0YLGk8y+LU4GtJyyWutVF8/u00Jsb6mKbuBo9avs7IDzarVL68TQXXAw7A5QazbArDA IDPDIYaSAC3oi1wwPAMQjttLyHJF4kD3gq1dyRlGoUY6hlCTfyq/S+0DjOzt51gehsju wqOQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=Q/JxMM3NAomx6ykwazS1RjvqreMPIS0r/3fmUpKXorI=; b=aOd6Vt8RCN3ls4BeBVVh8XmCp6mVqhMFlKp5uUO+QJ5ay7yLbBzQtlnxMw2zOItlqL CNBU3MpmKl8TfYn7v9BmjWsUVssZP9P6S7BBm0F1XLV3hIedFy5b3+G5bTP/iTUSCeA4 mLycDY0fnSZDf22JvQQYlgTG8fhzqmpGlsOlxMBPstB3J+UiNzIhLm2ipMCSAbsQCDw/ a9zheZL8KSPn8zXbSXBC9W93X4+GWmThTSY90F16oJtUx2rlxKEStpwAP9NjPNluxlSp /8LxPQUDu9qXMYpOBknrF6p75gRBjI4LM/eMZquXKztnm4KtrXwHrKHYxHyW7WnT0oOp LJ+g== X-Gm-Message-State: APjAAAWiFPFJTy1LrVSMRYoesRY9pEEn31XWDyxIzFUGD39TxxNMo3H0 96oajUSRaCBSTwkS4nktkQubwU4vawb5Qy9aBlnCLg== X-Google-Smtp-Source: APXvYqygUW70HQie5uMEgMKon0Mbjh7W5Mlwexza/X748hWAM7/UxdvvZalg9kqRZKB3P/vbtZskLcKGZApSJFfXBHA= X-Received: by 2002:a05:6830:4a4:: with SMTP id l4mr38999964otd.91.1576598633324; Tue, 17 Dec 2019 08:03:53 -0800 (PST) MIME-Version: 1.0 References: <40f97ae32a6f21d8184c1cc46fad2defb302238d.1576227325.git.alistair@alistair23.me> In-Reply-To: <40f97ae32a6f21d8184c1cc46fad2defb302238d.1576227325.git.alistair@alistair23.me> From: Peter Maydell Date: Tue, 17 Dec 2019 16:03:42 +0000 Message-ID: Subject: Re: [PATCH v6 4/4] hw/arm: Add the Netduino Plus 2 To: Alistair Francis Cc: QEMU Developers , qemu-arm , Alistair Francis Content-Type: text/plain; charset="UTF-8" X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::342 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 17 Dec 2019 16:03:56 -0000 On Sat, 14 Dec 2019 at 02:44, Alistair Francis wrote: > > Signed-off-by: Alistair Francis > --- > MAINTAINERS | 6 +++++ > hw/arm/Kconfig | 3 +++ > hw/arm/Makefile.objs | 1 + > hw/arm/netduinoplus2.c | 52 ++++++++++++++++++++++++++++++++++++++++++ > 4 files changed, 62 insertions(+) > create mode 100644 hw/arm/netduinoplus2.c > > diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig > index 7bfdc3a7ac..881e7f56e7 100644 > --- a/hw/arm/Kconfig > +++ b/hw/arm/Kconfig > @@ -105,6 +105,9 @@ config NETDUINOPLUS2 > bool > select STM32F405_SOC > > +config NETDUINOPLUS2 > + bool > + > config NSERIES > bool > select OMAP Something odd has happened here -- your patch 1/4 already had a stanza: +config NETDUINOPLUS2 + bool + select STM32F405_SOC so either that should be in this patch or this fragment here should just be deleted. Assuming you sort that out, Reviewed-by: Peter Maydell thanks -- PMM From MAILER-DAEMON Tue Dec 17 11:08:23 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1ihFOZ-0006Yr-J7 for mharc-qemu-arm@gnu.org; Tue, 17 Dec 2019 11:08:23 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:40717) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ihFOX-0006YM-LT for qemu-arm@nongnu.org; Tue, 17 Dec 2019 11:08:22 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ihFOW-0000v8-KA for qemu-arm@nongnu.org; Tue, 17 Dec 2019 11:08:21 -0500 Received: from mail-ot1-x343.google.com ([2607:f8b0:4864:20::343]:41785) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ihFOW-0000pp-EB for qemu-arm@nongnu.org; Tue, 17 Dec 2019 11:08:20 -0500 Received: by mail-ot1-x343.google.com with SMTP id r27so14283707otc.8 for ; Tue, 17 Dec 2019 08:08:20 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc:content-transfer-encoding; bh=quqEcBZm6ZgH7nO7zteu3tS9msScNxiSze5l+g6Ih0s=; b=thbUYW6z3+m5Mb/+UCGDLkQYDETFM2hu7mD54159R36+SJxuQaHh+0pwixvIb859zn D4/GpaiHGtTb6SIsM6n1+B5g73qpAWKmP2lhhfZUqwWWXa+x9qrCZNJTnGJ3gL960Cr6 GmnNcd1c8EDiOD762zh75QETdVp7Xw1D8QLFEAGWd5r9pzvlwgK5gDTrzp9llGDt+VmJ pGNpQwQg8r/ueAC1AVlHVY/vyNagTGFZIQUKbKP1hT5p34R45HRPsTc/KSoj2zkO/bEq kS5RM2buHs8HnqokwsnXmLLqBTE0yTLNsvospMcsEL27V/eNHYDPdb4mY1oubS2shpeC 69Mw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc:content-transfer-encoding; bh=quqEcBZm6ZgH7nO7zteu3tS9msScNxiSze5l+g6Ih0s=; b=eYLmpjdX+rds5GaMyytfJ3V1ZLHZ/+TkfTmYrkvXBPw747orskHhYDTNozsXulOxG5 sKF1NZWgBL56lZFg87cCgOexRgc+qCQUJ6aLaSwOmuOF/fA/s+n4idF0c0yEbGokieVR RB+V9F64ElVTPrDXcP78ea63L/eB6Jvjjhc1sC4zEWX8WSQxwUcXNrXvqJ2XcOkLR1cT lVlTu5umVzy/uLzv2nv6MlwNh2Kns5XfNqreu8GuKi4aaZREvWn+UHfCGpHCjSoINzrJ 1ooCILchI4uY1xEGW17mB3+GcYISmYa11c44YaXDf83cRzoVqJtS3n6Wgzt8IYxAGVXK G75A== X-Gm-Message-State: APjAAAWAyQhchrQWG82xxN0j8FbhW5ysgParOKEDY7UHjx9Wrd1OILqW rBbzj0q4QrHqtRfaTwZtnbr5jO9SeFt4Nq78VN/9cg== X-Google-Smtp-Source: APXvYqykcXklOc7RDYpkUhPnXIsOB5/MahrIm4DlsnpzKF726qk5Bs4tPFjqvu5WrXrB7xVIlzJPoS25S/Pb5hOAEPU= X-Received: by 2002:a05:6830:13d3:: with SMTP id e19mr38870538otq.135.1576598899525; Tue, 17 Dec 2019 08:08:19 -0800 (PST) MIME-Version: 1.0 References: <20191209134552.27733-1-philmd@redhat.com> In-Reply-To: From: Peter Maydell Date: Tue, 17 Dec 2019 16:08:08 +0000 Message-ID: Subject: Re: [PATCH] target/arm: Display helpful message when hflags mismatch To: Richard Henderson Cc: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= , "qemu-devel@nongnu.org Developers" , qemu-arm , =?UTF-8?B?QWxleCBCZW5uw6ll?= Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::343 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 17 Dec 2019 16:08:22 -0000 On Tue, 17 Dec 2019 at 16:02, Richard Henderson wrote: > > On Mon, 9 Dec 2019 at 03:46, Philippe Mathieu-Daud=C3=A9 wrote: > > > > Instead of crashing in a confuse way, give some hint to the user > > about why we aborted. He might report the issue without having > > to use a debugger. > > > > Signed-off-by: Philippe Mathieu-Daud=C3=A9 > > --- > > target/arm/helper.c | 18 +++++++++++++++--- > > 1 file changed, 15 insertions(+), 3 deletions(-) > > Reviewed-by: Richard Henderson Applied to target-arm.next, thanks. -- PMM From MAILER-DAEMON Tue Dec 17 11:11:18 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1ihFRO-0008Hp-Be for mharc-qemu-arm@gnu.org; Tue, 17 Dec 2019 11:11:18 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:42652) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ihFRL-0008HF-2l for qemu-arm@nongnu.org; Tue, 17 Dec 2019 11:11:16 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ihFRJ-0003hj-8u for qemu-arm@nongnu.org; Tue, 17 Dec 2019 11:11:14 -0500 Received: from us-smtp-1.mimecast.com ([205.139.110.61]:28842 helo=us-smtp-delivery-1.mimecast.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1ihFRJ-0003c7-5J for qemu-arm@nongnu.org; Tue, 17 Dec 2019 11:11:13 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1576599071; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=2h83AL8aS2w2Rnp2P4AIH18JYDJUV85rQtELdieBzDw=; b=R3rztyWB8oOsSR9OWE+CLl+IpWEWKZQ8F8qRbG2HpLjsXTQpx7/fblAGni092gG7LNAkNT GaxlcstCwPiWmj9ncDYfYmrTKnW8liSTMXpbWpRPSPtzuV2JvVjCG2GXLP1NR2MlV/L3EK sFv1eGaI8dKkqa2uh6iNX6Zdi1/FNTQ= Received: from mail-wr1-f71.google.com (mail-wr1-f71.google.com [209.85.221.71]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-232-O1Q4BDzgMTm-xNF0HkyTfQ-1; Tue, 17 Dec 2019 11:11:08 -0500 Received: by mail-wr1-f71.google.com with SMTP id z15so5578456wrw.0 for ; Tue, 17 Dec 2019 08:11:07 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:subject:to:cc:references:from:message-id:date :user-agent:mime-version:in-reply-to:content-language :content-transfer-encoding; bh=yn+84cH9XOOvHfsX9iXhmgM1ZPfhhA7dJdWcLpX+LnQ=; b=VHN2sSFOZ0w81iOGk8AcVN/uy8ig+Q615mS+s3s//kwGatBzmb5DDBOzHA7gYYnGKc CUBzTNK1AnDc67i0mMm2QCzSh/8I6donqykSn+8onw7yGR34GEtfEs2NWnJ4No4nKH58 09ypBTLpDsLyyCv45r7wY+097MKaaDvQqPtFCx6UhBFNQkpI5lrdDQxIVY1WHLsctjoO 6vLgkC9xQW13QHwGWANCGAQZuIoPIu1k3HCLnIIMzrGJmGzlDqaXIoWSnfjJX+Xfr1hE H5aSDNJ3+5yI/qugvqiC0+LdAiA5M97dP7lZHvvgaxONlXB6RIQsB3TCHc2mX5kDkN6x RMtA== X-Gm-Message-State: APjAAAXgIqByjIxFySTIGA18WmX5oafbE4i5f+412sg1Q49j2AboC7LD qWDZTzxz5NyxzgK6fkMcEA2/EvP3QiDsnl4TtpIa3nDraR9W1yUkaD2q5As8WGK05T/WDhIG7Ac KCl7WgvzwRUVv X-Received: by 2002:adf:e58d:: with SMTP id l13mr36464899wrm.135.1576599066995; Tue, 17 Dec 2019 08:11:06 -0800 (PST) X-Google-Smtp-Source: APXvYqxEr6MebCPVQYgmeqNnXuFr69J0IHlVTply6shSwblgeoSETJS/MCN9oT6owRynq7mhdfF65w== X-Received: by 2002:adf:e58d:: with SMTP id l13mr36464861wrm.135.1576599066777; Tue, 17 Dec 2019 08:11:06 -0800 (PST) Received: from [192.168.1.35] (34.red-83-42-66.dynamicip.rima-tde.net. [83.42.66.34]) by smtp.gmail.com with ESMTPSA id t81sm3521182wmg.6.2019.12.17.08.11.05 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 17 Dec 2019 08:11:06 -0800 (PST) Subject: Re: [PATCH] target/arm: Display helpful message when hflags mismatch To: Peter Maydell , Richard Henderson , Niek Linnenbank Cc: "qemu-devel@nongnu.org Developers" , qemu-arm , =?UTF-8?Q?Alex_Benn=c3=a9e?= References: <20191209134552.27733-1-philmd@redhat.com> From: =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= Message-ID: <34ff9b70-8779-e0fa-abb3-89f99df93975@redhat.com> Date: Tue, 17 Dec 2019 17:11:04 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.2.2 MIME-Version: 1.0 In-Reply-To: Content-Language: en-US X-MC-Unique: O1Q4BDzgMTm-xNF0HkyTfQ-1 X-Mimecast-Spam-Score: 0 Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 205.139.110.61 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 17 Dec 2019 16:11:16 -0000 On 12/17/19 5:08 PM, Peter Maydell wrote: > On Tue, 17 Dec 2019 at 16:02, Richard Henderson > wrote: >> >> On Mon, 9 Dec 2019 at 03:46, Philippe Mathieu-Daud=C3=A9 wrote: >>> >>> Instead of crashing in a confuse way, give some hint to the user >>> about why we aborted. He might report the issue without having >>> to use a debugger. >>> >>> Signed-off-by: Philippe Mathieu-Daud=C3=A9 >>> --- >>> target/arm/helper.c | 18 +++++++++++++++--- >>> 1 file changed, 15 insertions(+), 3 deletions(-) >> >> Reviewed-by: Richard Henderson >=20 >=20 >=20 > Applied to target-arm.next, thanks. Thanks, you can also add (from a different thread): Tested-by: Niek Linnenbank From MAILER-DAEMON Tue Dec 17 11:12:32 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1ihFSa-0000vF-SG for mharc-qemu-arm@gnu.org; Tue, 17 Dec 2019 11:12:32 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:43399) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ihFSW-0000sg-Nl for qemu-arm@nongnu.org; Tue, 17 Dec 2019 11:12:30 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ihFSV-0000me-87 for qemu-arm@nongnu.org; Tue, 17 Dec 2019 11:12:28 -0500 Received: from mail-oi1-x242.google.com ([2607:f8b0:4864:20::242]:44077) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ihFSV-0000lC-1V for qemu-arm@nongnu.org; Tue, 17 Dec 2019 11:12:27 -0500 Received: by mail-oi1-x242.google.com with SMTP id d62so5747336oia.11 for ; Tue, 17 Dec 2019 08:12:26 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=9eA6rPNcaU2ZWLl5G0XTFFRhC0j4AKLKeAJsM48P8eE=; b=gUJAhbf/BbeTUy3EGzWR9W7DUBuThSDmXWfPvtpqb6pqMlwHbG0RRVJm+myNSSmU78 NCg5wHcTaOGqjsKc20aXQ27zPWoeiPes6/PxS721vk62iSYftaCBCrwuMiqx04TKEg9s AY2M8wr7PyKTmmfq50oe8FUmIXwWR8QABEZDShPS+b3MrqBJpTrfkLfpGHWwXS+8tmiN B8q1lt7/JWetuPYTKdJYdiE20GBKKpyQ6OEp3nZKUaoFv1W53FtG6IENGoEnOWDf6Rp9 fUt3FWwj1oV/jnuy72kSs4QBSaDTtPFFU4N4FFET/75OS3uJF47rsCnAa9H9Idt320AK ZNog== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=9eA6rPNcaU2ZWLl5G0XTFFRhC0j4AKLKeAJsM48P8eE=; b=Ppiky/ofChuaH+nZDx6a+APnQA4m+C5LSynLgGMpqCdb2mEYqT3xtzjoUYOfS4E219 hrDbLUxNdJoIq2YFP3KdTMLUcBq9PWD+BvhNyqjkccYH4FJA8Are1sym7bysz2JsVLh4 0MmKitiSBAuxM1t5TpR3dHYx8hQ0WCO+U9i5o0CcNhKVsAiZ39xVcskQbt+OKw94ranT JXmAcUTj6sGXQvcOWYi1XILl0FGoDaLDf0BsE7AbZqaEhmIPALH62frMDif2U04Wg3Zf EtCtNqY9Z7XDGO53/hiFvhZ1hN/4cj6uvwhq0wvaYnRNeh5IqicG4ywpgq5z+sG9CxNk 6EFg== X-Gm-Message-State: APjAAAWPLGKhSO1jEkEKF8QWk9EGx8xMJrBg8mPZKJxvSzxaQwEcyVOP ol2bTLySh9NT/Zzn7o3YpWVcZPtkhSCrjAXMm5IDDg== X-Google-Smtp-Source: APXvYqwzGDak71LvB29wk53UXrEGzwIRXhTgsDlJuSgITAfVpisvsNs6ocsWWIv3/tOzdszF6TAGWFUwSJR1O1iAM3Q= X-Received: by 2002:aca:f5cc:: with SMTP id t195mr1919853oih.163.1576599145997; Tue, 17 Dec 2019 08:12:25 -0800 (PST) MIME-Version: 1.0 References: <20191216233519.29030-1-nieklinnenbank@gmail.com> <20191216233519.29030-7-nieklinnenbank@gmail.com> In-Reply-To: From: Peter Maydell Date: Tue, 17 Dec 2019 16:12:15 +0000 Message-ID: Subject: Re: [PATCH v2 06/10] arm/arm-powerctl: rebuild hflags after setting CP15 bits in arm_set_cpu_on() To: Niek Linnenbank Cc: qemu-arm , =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= , QEMU Developers , Richard Henderson Content-Type: text/plain; charset="UTF-8" X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::242 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 17 Dec 2019 16:12:30 -0000 Cc'ing Richard : this is one for you I think... (surely we need to rebuild the hflags from scratch when we power up a CPU anyway?) thanks -- PMM On Mon, 16 Dec 2019 at 23:44, Niek Linnenbank wrote: > > Hello Peter, > > In the previous version of this patch series I included the fix for setting CP10,CP11 bits > in arm_set_cpu_on(), which is now in master (0c7f8c43daf65560). While that worked, I did not > realize that setting those bits require rebuilding the flags. Philippe reported this [1] initially, > later on during review we discussed [2] and attempted to correct it [3]. > > Could you please have a short look at this? Right now I don't see anymore > issues, but I'm just not very familiar with this area of the code. > > Regards, > Niek > > [1] https://lists.gnu.org/archive/html/qemu-devel/2019-12/msg01920.html > [2] https://lists.gnu.org/archive/html/qemu-devel/2019-12/msg02784.html > [3] https://lists.gnu.org/archive/html/qemu-devel/2019-12/msg02785.html > > > On Tue, Dec 17, 2019 at 12:36 AM Niek Linnenbank wrote: >> >> After setting CP15 bits in arm_set_cpu_on() the cached hflags must >> be rebuild to reflect the changed processor state. Without rebuilding, >> the cached hflags would be inconsistent until the next call to >> arm_rebuild_hflags(). When QEMU is compiled with debugging enabled >> (--enable-debug), this problem is captured shortly after the first >> call to arm_set_cpu_on() for CPUs running in ARM 32-bit non-secure mode: >> >> qemu-system-arm: target/arm/helper.c:11359: cpu_get_tb_cpu_state: >> Assertion `flags == rebuild_hflags_internal(env)' failed. >> Aborted (core dumped) >> >> Fixes: 0c7f8c43daf65 >> Signed-off-by: Niek Linnenbank >> --- >> target/arm/arm-powerctl.c | 3 +++ >> 1 file changed, 3 insertions(+) >> >> diff --git a/target/arm/arm-powerctl.c b/target/arm/arm-powerctl.c >> index b064513d44..b75f813b40 100644 >> --- a/target/arm/arm-powerctl.c >> +++ b/target/arm/arm-powerctl.c >> @@ -127,6 +127,9 @@ static void arm_set_cpu_on_async_work(CPUState *target_cpu_state, >> target_cpu->env.regs[0] = info->context_id; >> } >> >> + /* CP15 update requires rebuilding hflags */ >> + arm_rebuild_hflags(&target_cpu->env); >> + >> /* Start the new CPU at the requested address */ >> cpu_set_pc(target_cpu_state, info->entry); >> >> -- >> 2.17.1 >> > > > -- > Niek Linnenbank From MAILER-DAEMON Tue Dec 17 11:38:58 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1ihFs9-0005PZ-Rg for mharc-qemu-arm@gnu.org; Tue, 17 Dec 2019 11:38:57 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:51166) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ihFs3-0005KL-7Z for qemu-arm@nongnu.org; Tue, 17 Dec 2019 11:38:55 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ihFrz-00009F-77 for qemu-arm@nongnu.org; Tue, 17 Dec 2019 11:38:51 -0500 Received: from us-smtp-delivery-1.mimecast.com ([205.139.110.120]:54048 helo=us-smtp-1.mimecast.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1ihFrz-00008b-2V for qemu-arm@nongnu.org; Tue, 17 Dec 2019 11:38:47 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1576600726; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding; bh=6a8mxHo3cySJx2vpicwTxKmGILKeHDrQeQCRS52voSg=; b=g6xCKi38tPOVUmOBnb9RND0bedDBQKsv4DAr0C1laBvbIHub1Y554yFpxGRoZerHRLiImi lD4F2Zcc6zUOIusz1kqnzq+PtCfhakw7Cx/vIgvXMCGH3KsjFzfxpcGiA4Io58jItekm5I jj62X/QZ9EOEN9VM1U+fXuLVfCE+yKs= Received: from mimecast-mx01.redhat.com (mimecast-mx01.redhat.com [209.132.183.4]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-424-rojm5KUGNQak6JPZ_E3JYA-1; Tue, 17 Dec 2019 11:38:44 -0500 Received: from smtp.corp.redhat.com (int-mx05.intmail.prod.int.phx2.redhat.com [10.5.11.15]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx01.redhat.com (Postfix) with ESMTPS id C9102DBA5; Tue, 17 Dec 2019 16:38:39 +0000 (UTC) Received: from x1w.redhat.com (ovpn-205-147.brq.redhat.com [10.40.205.147]) by smtp.corp.redhat.com (Postfix) with ESMTPS id 4C22D675BF; Tue, 17 Dec 2019 16:38:11 +0000 (UTC) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: Paolo Bonzini , =?UTF-8?q?Marc-Andr=C3=A9=20Lureau?= , qemu-devel@nongnu.org Cc: Cornelia Huck , Zhang Chen , "Michael S. Tsirkin" , Fabien Chouteau , Paul Burton , Peter Maydell , KONRAD Frederic , Aurelien Jarno , Jason Wang , qemu-block@nongnu.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Corey Minyard , Max Reitz , Li Zhijian , Gerd Hoffmann , Michael Walle , Markus Armbruster , Laurent Vivier , Igor Mitsyanko , Joel Stanley , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Bastian Koppelmann , Alberto Garcia , Peter Chubb , "Edgar E. Iglesias" , "Dr. David Alan Gilbert" , Christian Borntraeger , Andrzej Zaborowski , Aleksandar Rikalo , Aleksandar Markovic , Sagar Karandikar , Antony Pavlov , qemu-arm@nongnu.org, Alistair Francis , Kevin Wolf , qemu-s390x@nongnu.org, "Gonglei (Arei)" , Palmer Dabbelt , Samuel Thibault , Amit Shah , qemu-riscv@nongnu.org, Halil Pasic , Thomas Huth Subject: [PATCH 00/14] chardev: Use QEMUChrEvent enum in IOEventHandler typedef Date: Tue, 17 Dec 2019 17:37:54 +0100 Message-Id: <20191217163808.20068-1-philmd@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.79 on 10.5.11.15 X-MC-Unique: rojm5KUGNQak6JPZ_E3JYA-1 X-Mimecast-Spam-Score: 0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 205.139.110.120 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 17 Dec 2019 16:38:56 -0000 Hi, After this chat on #qemu IRC: 13:20 so what is the difference between a IOReadHandler and IOEve= ntHandler? 13:25 stsquad: one is in-band and the other out-of-band? 13:26 f4bug: ahh yes it seems so - connect/disconnect etc... 13:27 see QEMUChrEvent for IOEventHandler I thought it might be a good opportunity to make the IOEventHandler typedef meaning more obvious, by using the QEMUChrEvent enum. To be able to build I had to explicit a 'default' case when frontends use a switch(event) case and do not handle all events. Then I used a coccinelle spatch to change the various IOEventHandler. I don't think the last patch can be split, but suggestions are welcome! Regards, Phil. PD: I use git-publish. To avoid spamming too much, I'm using per-patch Cc tag, after the '---' separator. This way each recipient should get the cover and the specific patches of interests, + the last one. Sent with: 'git publish --suppress-cc=3Dcccmd' Cc: "Gonglei (Arei)" Cc: "Marc-Andr=C3=A9 Lureau" Cc: Paolo Bonzini Cc: "Alex Benn=C3=A9e" Cc: "Philippe Mathieu-Daud=C3=A9" Cc: Andrzej Zaborowski Cc: Peter Maydell Cc: "Michael S. Tsirkin" Cc: Kevin Wolf Cc: Max Reitz Cc: "Edgar E. Iglesias" Cc: Alistair Francis Cc: Antony Pavlov Cc: Igor Mitsyanko Cc: Fabien Chouteau Cc: KONRAD Frederic Cc: Peter Chubb Cc: Alberto Garcia Cc: Michael Walle Cc: Thomas Huth Cc: Joel Stanley Cc: Cornelia Huck Cc: Halil Pasic Cc: Christian Borntraeger Cc: Laurent Vivier Cc: Amit Shah Cc: Corey Minyard Cc: Paul Burton Cc: Aleksandar Rikalo Cc: Aurelien Jarno Cc: Aleksandar Markovic Cc: Palmer Dabbelt Cc: Sagar Karandikar Cc: Bastian Koppelmann Cc: Gerd Hoffmann Cc: Samuel Thibault Cc: "Dr. David Alan Gilbert" Cc: Markus Armbruster Cc: Zhang Chen Cc: Li Zhijian Cc: Jason Wang Cc: qemu-arm@nongnu.org Cc: qemu-block@nongnu.org Cc: qemu-s390x@nongnu.org Cc: qemu-riscv@nongnu.org Philippe Mathieu-Daud=C3=A9 (14): hw/ipmi: Remove unnecessary declarations chardev/char: Explicit we ignore some QEMUChrEvent in IOEventHandler vhost-user: Explicit we ignore some QEMUChrEvent in IOEventHandler virtio-console: Explicit we ignore some QEMUChrEvent in IOEventHandler hw/ipmi: Explicit we ignore some QEMUChrEvent in IOEventHandler hw/usb/dev-serial: Explicit we ignore few QEMUChrEvent in IOEventHandler ccid-card-passthru: Explicit we ignore QEMUChrEvent in IOEventHandler hw/usb/redirect: Explicit we ignore few QEMUChrEvent in IOEventHandler monitor/qmp: Explicit we ignore few QEMUChrEvent in IOEventHandler monitor/hmp: Explicit we ignore a QEMUChrEvent in IOEventHandler net/vhost-user: Explicit we ignore few QEMUChrEvent in IOEventHandler vhost-user-blk: Explicit we ignore few QEMUChrEvent in IOEventHandler hw/char/terminal3270: Explicit ignored QEMUChrEvent in IOEventHandler chardev: Use QEMUChrEvent enum in IOEventHandler typedef include/chardev/char-fe.h | 2 +- include/chardev/char-mux.h | 2 +- include/chardev/char.h | 4 ++-- backends/cryptodev-vhost-user.c | 5 ++++- chardev/char-mux.c | 8 ++++---- chardev/char.c | 7 +++++-- gdbstub.c | 2 +- hw/arm/pxa2xx.c | 2 +- hw/arm/strongarm.c | 2 +- hw/block/vhost-user-blk.c | 5 ++++- hw/char/cadence_uart.c | 2 +- hw/char/digic-uart.c | 2 +- hw/char/escc.c | 2 +- hw/char/etraxfs_ser.c | 2 +- hw/char/exynos4210_uart.c | 2 +- hw/char/grlib_apbuart.c | 2 +- hw/char/imx_serial.c | 2 +- hw/char/ipoctal232.c | 2 +- hw/char/lm32_juart.c | 2 +- hw/char/lm32_uart.c | 2 +- hw/char/mcf_uart.c | 2 +- hw/char/milkymist-uart.c | 2 +- hw/char/nrf51_uart.c | 2 +- hw/char/pl011.c | 2 +- hw/char/serial.c | 2 +- hw/char/sh_serial.c | 2 +- hw/char/terminal3270.c | 5 ++++- hw/char/virtio-console.c | 5 ++++- hw/char/xilinx_uartlite.c | 2 +- hw/ipmi/ipmi_bmc_extern.c | 10 +++++----- hw/mips/boston.c | 2 +- hw/mips/mips_malta.c | 2 +- hw/riscv/riscv_htif.c | 2 +- hw/riscv/sifive_uart.c | 2 +- hw/usb/ccid-card-passthru.c | 5 ++++- hw/usb/dev-serial.c | 5 ++++- hw/usb/redirect.c | 5 ++++- monitor/hmp.c | 6 +++++- monitor/qmp.c | 5 ++++- net/filter-mirror.c | 2 +- net/vhost-user.c | 7 +++++-- qtest.c | 2 +- tests/test-char.c | 6 +++--- tests/vhost-user-test.c | 2 +- 44 files changed, 90 insertions(+), 56 deletions(-) --=20 2.21.0 From MAILER-DAEMON Tue Dec 17 11:39:24 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1ihFsa-0005wm-1r for mharc-qemu-arm@gnu.org; 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bh=kbJd97UPYoKV5uP5HIXzv9iTL8Rz6OLSDFPr7bKkBZU=; b=ZMSFuT6raREBnK6aflTAdsyGLUofp+a6oLDGkblIsQN7ru9s3lAVM3kbxirs6dKBqF7Dme DXjOTFGTVPi+jKYTkf2GHUGR9c8Zg/JOzwguULKIzTqbRIdgedDE5MVGj8hSxuurW8Gdks FKSN/WgBbMt6HP1K/vmw9fcYg3P8BLo= Received: from mimecast-mx01.redhat.com (mimecast-mx01.redhat.com [209.132.183.4]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-246-JyYpJwhBNOmUrZpBXPsPvA-1; Tue, 17 Dec 2019 11:39:17 -0500 Received: from smtp.corp.redhat.com (int-mx05.intmail.prod.int.phx2.redhat.com [10.5.11.15]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx01.redhat.com (Postfix) with ESMTPS id 67CE810054E3; Tue, 17 Dec 2019 16:39:12 +0000 (UTC) Received: from x1w.redhat.com (ovpn-205-147.brq.redhat.com [10.40.205.147]) by smtp.corp.redhat.com (Postfix) with ESMTPS id 8131468877; Tue, 17 Dec 2019 16:38:40 +0000 (UTC) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: Paolo Bonzini , =?UTF-8?q?Marc-Andr=C3=A9=20Lureau?= , qemu-devel@nongnu.org Cc: Cornelia Huck , Zhang Chen , "Michael S. Tsirkin" , Fabien Chouteau , Paul Burton , Peter Maydell , KONRAD Frederic , Aurelien Jarno , Jason Wang , qemu-block@nongnu.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Corey Minyard , Max Reitz , Li Zhijian , Gerd Hoffmann , Michael Walle , Markus Armbruster , Laurent Vivier , Igor Mitsyanko , Joel Stanley , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Bastian Koppelmann , Alberto Garcia , Peter Chubb , "Edgar E. Iglesias" , "Dr. David Alan Gilbert" , Christian Borntraeger , Andrzej Zaborowski , Aleksandar Rikalo , Aleksandar Markovic , Sagar Karandikar , Antony Pavlov , qemu-arm@nongnu.org, Alistair Francis , Kevin Wolf , qemu-s390x@nongnu.org, "Gonglei (Arei)" , Palmer Dabbelt , Samuel Thibault , Amit Shah , qemu-riscv@nongnu.org, Halil Pasic , Thomas Huth , Corey Minyard , qemu-trivial@nongnu.org Subject: [PATCH 01/14] hw/ipmi: Remove unnecessary declarations Date: Tue, 17 Dec 2019 17:37:55 +0100 Message-Id: <20191217163808.20068-2-philmd@redhat.com> In-Reply-To: <20191217163808.20068-1-philmd@redhat.com> References: <20191217163808.20068-1-philmd@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.79 on 10.5.11.15 X-MC-Unique: JyYpJwhBNOmUrZpBXPsPvA-1 X-Mimecast-Spam-Score: 0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 205.139.110.61 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 17 Dec 2019 16:39:23 -0000 Since we don't use these methods before defining them, no need to forward-declare them. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Acked-by: Corey Minyard --- Cc: Corey Minyard In case the other patches are rejected: Cc: qemu-trivial@nongnu.org --- hw/ipmi/ipmi_bmc_extern.c | 4 ---- 1 file changed, 4 deletions(-) diff --git a/hw/ipmi/ipmi_bmc_extern.c b/hw/ipmi/ipmi_bmc_extern.c index 87da9ff99c..450926e5fb 100644 --- a/hw/ipmi/ipmi_bmc_extern.c +++ b/hw/ipmi/ipmi_bmc_extern.c @@ -87,10 +87,6 @@ typedef struct IPMIBmcExtern { bool send_reset; } IPMIBmcExtern; =20 -static int can_receive(void *opaque); -static void receive(void *opaque, const uint8_t *buf, int size); -static void chr_event(void *opaque, int event); - static unsigned char ipmb_checksum(const unsigned char *data, int size, unsigned char start) { --=20 2.21.0 From MAILER-DAEMON Tue Dec 17 11:39:51 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1ihFt1-0006ei-PI for mharc-qemu-arm@gnu.org; Tue, 17 Dec 2019 11:39:51 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:51504) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ihFsy-0006bF-UG for qemu-arm@nongnu.org; Tue, 17 Dec 2019 11:39:49 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ihFsx-0001Mw-Rz for qemu-arm@nongnu.org; Tue, 17 Dec 2019 11:39:48 -0500 Received: from us-smtp-delivery-1.mimecast.com ([205.139.110.120]:55083 helo=us-smtp-1.mimecast.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1ihFsx-0001MM-O2 for qemu-arm@nongnu.org; Tue, 17 Dec 2019 11:39:47 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1576600787; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=M5eisbppqcSSLnhV695pR3rX79aTKoSsMq1feLLMG84=; b=cVEOSojg6DdTohvNT/8RGjoUaYXPZ1ZIYKnBngroWxImaUiMg0QJAnQkOVaOUUCH1gyEQO lcJ5Fta55Xg4aacIUy9BEAuOZeBoGDQEi7AQfCMqfgThxKQhZXLEFtxNXj847kPArlsYu5 OMkb4Lc3yutCY87I7gY3BMM0DyAUlk4= Received: from mimecast-mx01.redhat.com (mimecast-mx01.redhat.com [209.132.183.4]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-96-DAQQ_TLkMuupDsbn6svgGg-1; Tue, 17 Dec 2019 11:39:45 -0500 Received: from smtp.corp.redhat.com (int-mx05.intmail.prod.int.phx2.redhat.com [10.5.11.15]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx01.redhat.com (Postfix) with ESMTPS id 70B7F800053; Tue, 17 Dec 2019 16:39:41 +0000 (UTC) Received: from x1w.redhat.com (ovpn-205-147.brq.redhat.com [10.40.205.147]) by smtp.corp.redhat.com (Postfix) with ESMTPS id 63EB5675BF; Tue, 17 Dec 2019 16:39:12 +0000 (UTC) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: Paolo Bonzini , =?UTF-8?q?Marc-Andr=C3=A9=20Lureau?= , qemu-devel@nongnu.org Cc: Cornelia Huck , Zhang Chen , "Michael S. Tsirkin" , Fabien Chouteau , Paul Burton , Peter Maydell , KONRAD Frederic , Aurelien Jarno , Jason Wang , qemu-block@nongnu.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Corey Minyard , Max Reitz , Li Zhijian , Gerd Hoffmann , Michael Walle , Markus Armbruster , Laurent Vivier , Igor Mitsyanko , Joel Stanley , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Bastian Koppelmann , Alberto Garcia , Peter Chubb , "Edgar E. Iglesias" , "Dr. David Alan Gilbert" , Christian Borntraeger , Andrzej Zaborowski , Aleksandar Rikalo , Aleksandar Markovic , Sagar Karandikar , Antony Pavlov , qemu-arm@nongnu.org, Alistair Francis , Kevin Wolf , qemu-s390x@nongnu.org, "Gonglei (Arei)" , Palmer Dabbelt , Samuel Thibault , Amit Shah , qemu-riscv@nongnu.org, Halil Pasic , Thomas Huth Subject: [RFC PATCH 02/14] chardev/char: Explicit we ignore some QEMUChrEvent in IOEventHandler Date: Tue, 17 Dec 2019 17:37:56 +0100 Message-Id: <20191217163808.20068-3-philmd@redhat.com> In-Reply-To: <20191217163808.20068-1-philmd@redhat.com> References: <20191217163808.20068-1-philmd@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.79 on 10.5.11.15 X-MC-Unique: DAQQ_TLkMuupDsbn6svgGg-1 X-Mimecast-Spam-Score: 0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 205.139.110.120 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 17 Dec 2019 16:39:50 -0000 The Chardev events are listed in the QEMUChrEvent enum. To be able to use this enum in the IOEventHandler typedef, we need to explicit when frontends ignore some events, to silent GCC the following warnings: chardev/char.c: In function =E2=80=98qemu_chr_be_event=E2=80=99: chardev/char.c:65:5: error: enumeration value =E2=80=98CHR_EVENT_BREAK=E2= =80=99 not handled in switch [-Werror=3Dswitch] 65 | switch (event) { | ^~~~~~ chardev/char.c:65:5: error: enumeration value =E2=80=98CHR_EVENT_MUX_IN= =E2=80=99 not handled in switch [-Werror=3Dswitch] chardev/char.c:65:5: error: enumeration value =E2=80=98CHR_EVENT_MUX_OUT= =E2=80=99 not handled in switch [-Werror=3Dswitch] cc1: all warnings being treated as errors Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- Cc: "Marc-Andr=C3=A9 Lureau" Cc: Paolo Bonzini --- chardev/char.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/chardev/char.c b/chardev/char.c index 7b6b2cb123..c4b6bbc55a 100644 --- a/chardev/char.c +++ b/chardev/char.c @@ -69,6 +69,9 @@ void qemu_chr_be_event(Chardev *s, int event) case CHR_EVENT_CLOSED: s->be_open =3D 0; break; + default: + /* Ignore */ + break; } =20 CHARDEV_GET_CLASS(s)->chr_be_event(s, event); --=20 2.21.0 From MAILER-DAEMON Tue Dec 17 11:40:24 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1ihFtY-0007F0-EH for mharc-qemu-arm@gnu.org; Tue, 17 Dec 2019 11:40:24 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:51743) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ihFtT-00079O-V9 for qemu-arm@nongnu.org; Tue, 17 Dec 2019 11:40:22 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ihFtS-00023X-QM for qemu-arm@nongnu.org; Tue, 17 Dec 2019 11:40:19 -0500 Received: from us-smtp-2.mimecast.com ([207.211.31.81]:57065 helo=us-smtp-delivery-1.mimecast.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1ihFtS-0001zH-Lx for qemu-arm@nongnu.org; Tue, 17 Dec 2019 11:40:18 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1576600815; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=UyNiSII4bECQvnQNLsrJWX7wCLrL6i3l3plxAAkIibg=; b=FvSrI5jNcjscxO87wz5nSL9+5BF+au2w3g7N+VM9pleU5g0say2m65rOv3ODiOyCPH5/mC cVbkJgRvJXJzlqx1EerMd3oXyQVzXjfh8Fodi8jkZqz8b/D1u5SqpSA1koMpA1dtqslWNB zIyFj6ZCcTBPKxiOzB1oJnBqgcWcVsg= Received: from mimecast-mx01.redhat.com (mimecast-mx01.redhat.com [209.132.183.4]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-339-XjCk825XO-Sq4YcNnMKgDA-1; Tue, 17 Dec 2019 11:40:13 -0500 Received: from smtp.corp.redhat.com (int-mx05.intmail.prod.int.phx2.redhat.com [10.5.11.15]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx01.redhat.com (Postfix) with ESMTPS id AA5E8800EBF; Tue, 17 Dec 2019 16:40:08 +0000 (UTC) Received: from x1w.redhat.com (ovpn-205-147.brq.redhat.com [10.40.205.147]) by smtp.corp.redhat.com (Postfix) with ESMTPS id 22850675B0; Tue, 17 Dec 2019 16:39:41 +0000 (UTC) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: Paolo Bonzini , =?UTF-8?q?Marc-Andr=C3=A9=20Lureau?= , qemu-devel@nongnu.org Cc: Cornelia Huck , Zhang Chen , "Michael S. Tsirkin" , Fabien Chouteau , Paul Burton , Peter Maydell , KONRAD Frederic , Aurelien Jarno , Jason Wang , qemu-block@nongnu.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Corey Minyard , Max Reitz , Li Zhijian , Gerd Hoffmann , Michael Walle , Markus Armbruster , Laurent Vivier , Igor Mitsyanko , Joel Stanley , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Bastian Koppelmann , Alberto Garcia , Peter Chubb , "Edgar E. Iglesias" , "Dr. David Alan Gilbert" , Christian Borntraeger , Andrzej Zaborowski , Aleksandar Rikalo , Aleksandar Markovic , Sagar Karandikar , Antony Pavlov , qemu-arm@nongnu.org, Alistair Francis , Kevin Wolf , qemu-s390x@nongnu.org, "Gonglei (Arei)" , Palmer Dabbelt , Samuel Thibault , Amit Shah , qemu-riscv@nongnu.org, Halil Pasic , Thomas Huth Subject: [RFC PATCH 03/14] vhost-user: Explicit we ignore some QEMUChrEvent in IOEventHandler Date: Tue, 17 Dec 2019 17:37:57 +0100 Message-Id: <20191217163808.20068-4-philmd@redhat.com> In-Reply-To: <20191217163808.20068-1-philmd@redhat.com> References: <20191217163808.20068-1-philmd@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.79 on 10.5.11.15 X-MC-Unique: XjCk825XO-Sq4YcNnMKgDA-1 X-Mimecast-Spam-Score: 0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 207.211.31.81 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 17 Dec 2019 16:40:23 -0000 The Chardev events are listed in the QEMUChrEvent enum. To be able to use this enum in the IOEventHandler typedef, we need to explicit when frontends ignore some events, to silent GCC the following warnings: CC backends/cryptodev-vhost-user.o backends/cryptodev-vhost-user.c: In function =E2=80=98cryptodev_vhost_use= r_event=E2=80=99: backends/cryptodev-vhost-user.c:163:5: error: enumeration value =E2=80=98= CHR_EVENT_BREAK=E2=80=99 not handled in switch [-Werror=3Dswitch] 163 | switch (event) { | ^~~~~~ backends/cryptodev-vhost-user.c:163:5: error: enumeration value =E2=80=98= CHR_EVENT_MUX_IN=E2=80=99 not handled in switch [-Werror=3Dswitch] backends/cryptodev-vhost-user.c:163:5: error: enumeration value =E2=80=98= CHR_EVENT_MUX_OUT=E2=80=99 not handled in switch [-Werror=3Dswitch] cc1: all warnings being treated as errors Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- Cc: "Gonglei (Arei)" --- backends/cryptodev-vhost-user.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/backends/cryptodev-vhost-user.c b/backends/cryptodev-vhost-use= r.c index b344283940..d700934a0e 100644 --- a/backends/cryptodev-vhost-user.c +++ b/backends/cryptodev-vhost-user.c @@ -171,6 +171,9 @@ static void cryptodev_vhost_user_event(void *opaque, in= t event) b->ready =3D false; cryptodev_vhost_user_stop(queues, s); break; + default: + /* Ignore */ + break; } } =20 --=20 2.21.0 From MAILER-DAEMON Tue Dec 17 11:40:47 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1ihFtu-0007iz-Ui for mharc-qemu-arm@gnu.org; Tue, 17 Dec 2019 11:40:46 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:51908) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ihFtr-0007d4-Cq for qemu-arm@nongnu.org; Tue, 17 Dec 2019 11:40:44 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ihFtq-0002MM-6y for qemu-arm@nongnu.org; Tue, 17 Dec 2019 11:40:43 -0500 Received: from us-smtp-delivery-1.mimecast.com ([207.211.31.120]:51446 helo=us-smtp-1.mimecast.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1ihFtq-0002Kn-3E for qemu-arm@nongnu.org; Tue, 17 Dec 2019 11:40:42 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1576600840; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=7hfjipPNHS05FZX4gKyoZHOjOIm+A4c3HTMdvd0V9Mc=; b=FHhJGVVeUzXjRcj/gkDlmOiXr911ot3L89fsjHtBw2Kh2LTS39Er8VhXUcgM12Kuh10Q4K mfpjCjtuF6Ty51YaLCKy/i7RHtZVNpyNsaFMs2L72np4HhRApC0421P7uLYbsHSO6TKzMW 65vziEPU13/X1Zz1Za86/j9mQpWDvP4= Received: from mimecast-mx01.redhat.com (mimecast-mx01.redhat.com [209.132.183.4]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-397-FouF0qVGOieVWA7x8cLNmA-1; Tue, 17 Dec 2019 11:40:38 -0500 Received: from smtp.corp.redhat.com (int-mx05.intmail.prod.int.phx2.redhat.com [10.5.11.15]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx01.redhat.com (Postfix) with ESMTPS id 19AAC800D55; Tue, 17 Dec 2019 16:40:34 +0000 (UTC) Received: from x1w.redhat.com (ovpn-205-147.brq.redhat.com [10.40.205.147]) by smtp.corp.redhat.com (Postfix) with ESMTPS id 76D8F68865; Tue, 17 Dec 2019 16:40:09 +0000 (UTC) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: Paolo Bonzini , =?UTF-8?q?Marc-Andr=C3=A9=20Lureau?= , qemu-devel@nongnu.org Cc: Cornelia Huck , Zhang Chen , "Michael S. Tsirkin" , Fabien Chouteau , Paul Burton , Peter Maydell , KONRAD Frederic , Aurelien Jarno , Jason Wang , qemu-block@nongnu.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Corey Minyard , Max Reitz , Li Zhijian , Gerd Hoffmann , Michael Walle , Markus Armbruster , Laurent Vivier , Igor Mitsyanko , Joel Stanley , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Bastian Koppelmann , Alberto Garcia , Peter Chubb , "Edgar E. Iglesias" , "Dr. David Alan Gilbert" , Christian Borntraeger , Andrzej Zaborowski , Aleksandar Rikalo , Aleksandar Markovic , Sagar Karandikar , Antony Pavlov , qemu-arm@nongnu.org, Alistair Francis , Kevin Wolf , qemu-s390x@nongnu.org, "Gonglei (Arei)" , Palmer Dabbelt , Samuel Thibault , Amit Shah , qemu-riscv@nongnu.org, Halil Pasic , Thomas Huth Subject: [RFC PATCH 04/14] virtio-console: Explicit we ignore some QEMUChrEvent in IOEventHandler Date: Tue, 17 Dec 2019 17:37:58 +0100 Message-Id: <20191217163808.20068-5-philmd@redhat.com> In-Reply-To: <20191217163808.20068-1-philmd@redhat.com> References: <20191217163808.20068-1-philmd@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.79 on 10.5.11.15 X-MC-Unique: FouF0qVGOieVWA7x8cLNmA-1 X-Mimecast-Spam-Score: 0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 207.211.31.120 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 17 Dec 2019 16:40:45 -0000 The Chardev events are listed in the QEMUChrEvent enum. To be able to use this enum in the IOEventHandler typedef, we need to explicit when frontends ignore some events, to silent GCC the following warnings: CC hw/char/virtio-console.o hw/char/virtio-console.c: In function =E2=80=98chr_event=E2=80=99: hw/char/virtio-console.c:154:5: error: enumeration value =E2=80=98CHR_EVE= NT_BREAK=E2=80=99 not handled in switch [-Werror=3Dswitch] 154 | switch (event) { | ^~~~~~ hw/char/virtio-console.c:154:5: error: enumeration value =E2=80=98CHR_EVE= NT_MUX_IN=E2=80=99 not handled in switch [-Werror=3Dswitch] hw/char/virtio-console.c:154:5: error: enumeration value =E2=80=98CHR_EVE= NT_MUX_OUT=E2=80=99 not handled in switch [-Werror=3Dswitch] cc1: all warnings being treated as errors Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- Cc: "Michael S. Tsirkin" Cc: Laurent Vivier Cc: Amit Shah Cc: "Marc-Andr=C3=A9 Lureau" Cc: Paolo Bonzini --- hw/char/virtio-console.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/hw/char/virtio-console.c b/hw/char/virtio-console.c index c13649f1ef..d3f7ba36fe 100644 --- a/hw/char/virtio-console.c +++ b/hw/char/virtio-console.c @@ -162,6 +162,9 @@ static void chr_event(void *opaque, int event) } virtio_serial_close(port); break; + default: + /* Ignore */ + break; } } =20 --=20 2.21.0 From MAILER-DAEMON Tue Dec 17 11:41:31 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1ihFuc-0000RK-TK for mharc-qemu-arm@gnu.org; Tue, 17 Dec 2019 11:41:30 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:52171) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ihFuZ-0000LF-6q for qemu-arm@nongnu.org; Tue, 17 Dec 2019 11:41:28 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ihFuX-0003DH-Su for qemu-arm@nongnu.org; Tue, 17 Dec 2019 11:41:27 -0500 Received: from us-smtp-2.mimecast.com ([205.139.110.61]:29821 helo=us-smtp-delivery-1.mimecast.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1ihFuX-0003Cc-PB for qemu-arm@nongnu.org; Tue, 17 Dec 2019 11:41:25 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1576600885; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=evC+sSxtNpMvTh5wC5Sh3YUUefjPdijlTohqC3qDS2A=; b=FdwzHp/lP5sHuZ7ttGBe8+Bp64eZdSnCvUaVkaZe2KNKOzeKiA0xtjpJNdRZ/yD1aXTfCb RkaV4OJSHt2sxyWUjvl0HeWye7s/QlESSHxJpH36b2L12k4x2IS9em56hbHuJaabTNUTr8 S7EejjDt8FKXJ4M27IoYq2HLnQ8HfRQ= Received: from mimecast-mx01.redhat.com (mimecast-mx01.redhat.com [209.132.183.4]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-322-VG_OKgThMUSaVLGhASXBGA-1; Tue, 17 Dec 2019 11:41:21 -0500 Received: from smtp.corp.redhat.com (int-mx05.intmail.prod.int.phx2.redhat.com [10.5.11.15]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx01.redhat.com (Postfix) with ESMTPS id 214938E3E0C; Tue, 17 Dec 2019 16:41:17 +0000 (UTC) Received: from x1w.redhat.com (ovpn-205-147.brq.redhat.com [10.40.205.147]) by smtp.corp.redhat.com (Postfix) with ESMTPS id A85586888E; Tue, 17 Dec 2019 16:40:34 +0000 (UTC) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: Paolo Bonzini , =?UTF-8?q?Marc-Andr=C3=A9=20Lureau?= , qemu-devel@nongnu.org Cc: Cornelia Huck , Zhang Chen , "Michael S. Tsirkin" , Fabien Chouteau , Paul Burton , Peter Maydell , KONRAD Frederic , Aurelien Jarno , Jason Wang , qemu-block@nongnu.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Corey Minyard , Max Reitz , Li Zhijian , Gerd Hoffmann , Michael Walle , Markus Armbruster , Laurent Vivier , Igor Mitsyanko , Joel Stanley , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Bastian Koppelmann , Alberto Garcia , Peter Chubb , "Edgar E. Iglesias" , "Dr. David Alan Gilbert" , Christian Borntraeger , Andrzej Zaborowski , Aleksandar Rikalo , Aleksandar Markovic , Sagar Karandikar , Antony Pavlov , qemu-arm@nongnu.org, Alistair Francis , Kevin Wolf , qemu-s390x@nongnu.org, "Gonglei (Arei)" , Palmer Dabbelt , Samuel Thibault , Amit Shah , qemu-riscv@nongnu.org, Halil Pasic , Thomas Huth Subject: [RFC PATCH 05/14] hw/ipmi: Explicit we ignore some QEMUChrEvent in IOEventHandler Date: Tue, 17 Dec 2019 17:37:59 +0100 Message-Id: <20191217163808.20068-6-philmd@redhat.com> In-Reply-To: <20191217163808.20068-1-philmd@redhat.com> References: <20191217163808.20068-1-philmd@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.79 on 10.5.11.15 X-MC-Unique: VG_OKgThMUSaVLGhASXBGA-1 X-Mimecast-Spam-Score: 0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 205.139.110.61 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 17 Dec 2019 16:41:29 -0000 The Chardev events are listed in the QEMUChrEvent enum. To be able to use this enum in the IOEventHandler typedef, we need to explicit when frontends ignore some events, to silent GCC the following warnings: hw/ipmi/ipmi_bmc_extern.c: In function =E2=80=98chr_event=E2=80=99: hw/ipmi/ipmi_bmc_extern.c:389:5: error: enumeration value =E2=80=98CHR_EV= ENT_BREAK=E2=80=99 not handled in switch [-Werror=3Dswitch] 389 | switch (event) { | ^~~~~~ hw/ipmi/ipmi_bmc_extern.c:389:5: error: enumeration value =E2=80=98CHR_EV= ENT_MUX_IN=E2=80=99 not handled in switch [-Werror=3Dswitch] hw/ipmi/ipmi_bmc_extern.c:389:5: error: enumeration value =E2=80=98CHR_EV= ENT_MUX_OUT=E2=80=99 not handled in switch [-Werror=3Dswitch] cc1: all warnings being treated as errors Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- Cc: Corey Minyard --- hw/ipmi/ipmi_bmc_extern.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/hw/ipmi/ipmi_bmc_extern.c b/hw/ipmi/ipmi_bmc_extern.c index 450926e5fb..9d67e6a4a5 100644 --- a/hw/ipmi/ipmi_bmc_extern.c +++ b/hw/ipmi/ipmi_bmc_extern.c @@ -435,6 +435,10 @@ static void chr_event(void *opaque, int event) k->handle_rsp(s, ibe->outbuf[0], ibe->inbuf + 1, 3); } break; + + default: + /* Ignore */ + break; } } =20 --=20 2.21.0 From MAILER-DAEMON Tue Dec 17 11:41:59 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1ihFv5-0001HN-IX for mharc-qemu-arm@gnu.org; Tue, 17 Dec 2019 11:41:59 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:52356) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ihFv2-0001Bs-8o for qemu-arm@nongnu.org; Tue, 17 Dec 2019 11:41:57 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ihFv0-0003bW-V8 for qemu-arm@nongnu.org; Tue, 17 Dec 2019 11:41:56 -0500 Received: from us-smtp-1.mimecast.com ([207.211.31.81]:56862 helo=us-smtp-delivery-1.mimecast.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1ihFv0-0003Zx-Rj for qemu-arm@nongnu.org; Tue, 17 Dec 2019 11:41:54 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1576600914; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=aNeyU7/Lv4XpR7KzxXHIM4Nb2F8VTLxcvwFNAQff+7M=; b=EvzdZtdmAApTryXwtAOo7yMv+yhLqtNCUWabet+VDmINXW7Ipfpo5BbC51pOMnflKBa734 iXZ6koR/nRlJbDxO/r3fCOnX24wsHgapjrT27j4AnHRCaVV28JP4of3I5Cd6GDb8dU9zOD 99DL4oQ5CAeao04wl361IB/VcM//BaM= Received: from mimecast-mx01.redhat.com (mimecast-mx01.redhat.com [209.132.183.4]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-155-0NjUTsbmNF-QwDxiAk6QrA-1; Tue, 17 Dec 2019 11:41:49 -0500 Received: from smtp.corp.redhat.com (int-mx05.intmail.prod.int.phx2.redhat.com [10.5.11.15]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx01.redhat.com (Postfix) with ESMTPS id B5BBF1034B23; Tue, 17 Dec 2019 16:41:43 +0000 (UTC) Received: from x1w.redhat.com (ovpn-205-147.brq.redhat.com [10.40.205.147]) by smtp.corp.redhat.com (Postfix) with ESMTPS id 9588C77C80; Tue, 17 Dec 2019 16:41:17 +0000 (UTC) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: Paolo Bonzini , =?UTF-8?q?Marc-Andr=C3=A9=20Lureau?= , qemu-devel@nongnu.org Cc: Cornelia Huck , Zhang Chen , "Michael S. Tsirkin" , Fabien Chouteau , Paul Burton , Peter Maydell , KONRAD Frederic , Aurelien Jarno , Jason Wang , qemu-block@nongnu.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Corey Minyard , Max Reitz , Li Zhijian , Gerd Hoffmann , Michael Walle , Markus Armbruster , Laurent Vivier , Igor Mitsyanko , Joel Stanley , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Bastian Koppelmann , Alberto Garcia , Peter Chubb , "Edgar E. Iglesias" , "Dr. David Alan Gilbert" , Christian Borntraeger , Andrzej Zaborowski , Aleksandar Rikalo , Aleksandar Markovic , Sagar Karandikar , Antony Pavlov , qemu-arm@nongnu.org, Alistair Francis , Kevin Wolf , qemu-s390x@nongnu.org, "Gonglei (Arei)" , Palmer Dabbelt , Samuel Thibault , Amit Shah , qemu-riscv@nongnu.org, Halil Pasic , Thomas Huth Subject: [RFC PATCH 06/14] hw/usb/dev-serial: Explicit we ignore few QEMUChrEvent in IOEventHandler Date: Tue, 17 Dec 2019 17:38:00 +0100 Message-Id: <20191217163808.20068-7-philmd@redhat.com> In-Reply-To: <20191217163808.20068-1-philmd@redhat.com> References: <20191217163808.20068-1-philmd@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.79 on 10.5.11.15 X-MC-Unique: 0NjUTsbmNF-QwDxiAk6QrA-1 X-Mimecast-Spam-Score: 0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 207.211.31.81 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 17 Dec 2019 16:41:58 -0000 The Chardev events are listed in the QEMUChrEvent enum. To be able to use this enum in the IOEventHandler typedef, we need to explicit when frontends ignore some events, to silent GCC the following warnings: hw/usb/dev-serial.c: In function =E2=80=98usb_serial_event=E2=80=99: hw/usb/dev-serial.c:468:5: error: enumeration value =E2=80=98CHR_EVENT_MU= X_IN=E2=80=99 not handled in switch [-Werror=3Dswitch] 468 | switch (event) { | ^~~~~~ hw/usb/dev-serial.c:468:5: error: enumeration value =E2=80=98CHR_EVENT_MU= X_OUT=E2=80=99 not handled in switch [-Werror=3Dswitch] cc1: all warnings being treated as errors Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- Cc: Gerd Hoffmann Cc: Samuel Thibault --- hw/usb/dev-serial.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/hw/usb/dev-serial.c b/hw/usb/dev-serial.c index 45cc74128a..497f932a5a 100644 --- a/hw/usb/dev-serial.c +++ b/hw/usb/dev-serial.c @@ -479,6 +479,9 @@ static void usb_serial_event(void *opaque, int event) usb_device_detach(&s->dev); } break; + default: + /* Ignore */ + break; } } =20 --=20 2.21.0 From MAILER-DAEMON Tue Dec 17 11:42:02 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1ihFv8-0001LD-2N for mharc-qemu-arm@gnu.org; Tue, 17 Dec 2019 11:42:02 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:52407) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ihFv4-0001FZ-Tq for qemu-arm@nongnu.org; Tue, 17 Dec 2019 11:42:00 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ihFv3-0003eo-C7 for qemu-arm@nongnu.org; Tue, 17 Dec 2019 11:41:58 -0500 Received: from mail-pj1-x1041.google.com ([2607:f8b0:4864:20::1041]:36166) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ihFv3-0003du-3n for qemu-arm@nongnu.org; Tue, 17 Dec 2019 11:41:57 -0500 Received: by mail-pj1-x1041.google.com with SMTP id n59so96984pjb.1 for ; Tue, 17 Dec 2019 08:41:57 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=subject:to:cc:references:from:message-id:date:user-agent :mime-version:in-reply-to:content-language:content-transfer-encoding; bh=43Dbd2S1AzJNiOKd7dHnjOLXefnUc+FpgARmyexaboI=; b=gvup+FblALos6y8TtuxoA/RhPQpTbv5FW4Eja/poTMM4RUe+emsfSWVnmd8OcYY+8e NFPx2P00XGu2YLVQ9x6u9ZiFOw4ZcxquK0NT5DBPaGukkS73Rb6C8cs96mdJ6qE0ZMty /H2RBDMnuCfJNIVZQBETlxRm0fK8OnIXhndOFO4HYqmZGxqjerN2KUi6PnBa2Fnz4I7Z xPsVaCehtEL/nz7qRXVPiW9evzP7BTFINABk7rjTbV9t0x2M210v1U9IBS0QvGrB02mS EnyCY0ZdLYQI6JjX/APFOdhzgL75gwd+5bU0zqeXrkUIgShAenqfKJOaCC0dk8cwHaGV BnxA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:subject:to:cc:references:from:message-id:date :user-agent:mime-version:in-reply-to:content-language :content-transfer-encoding; bh=43Dbd2S1AzJNiOKd7dHnjOLXefnUc+FpgARmyexaboI=; b=m+MAa/9n2T1wPVYwLqpYbRsFrNyikZ8wW2JIqRXsMjZRUpfZgFEEzPl0pbkgl0ySoE asucXlJqUgURhVQzHBXpMbA33BNsekvXRaX7ZOTtE24cMNsb87sN0Hs4vkkoMFcghTmO NbjXMhdKJnMcoYvsDTenHbMv03v8NpbsvguU0nw3QgcvHKazoXPb9w3NjYFKYBTee4h0 JzHqHFNKC2xsl7p+G7l+8BPOqGBt15xuXTDyB5xL9swY4KMWFj86c17nc99lwWXY3Edm ZKTxafFd1TSsrk6Oflez/7Wf+s4E+cAXAA1MrJv+L8WGz5T6MZDP4dEHpj7UfnE/MYQ0 Bh9Q== X-Gm-Message-State: APjAAAWuDqC3r+TWOZGO0bnpaBRUkmxA2lVCmg+iyJGDsSv95glIoVYg 9cQGMcFHAhwDWWOfZFrFGNQLcQ== X-Google-Smtp-Source: APXvYqyBNwGeeOIQBndVpfipHxTpMo6e7mgI4szvoGmDgeO7aLHz2x5VyjbpD+Br/+eskhzEPgEZpg== X-Received: by 2002:a17:90a:e28e:: with SMTP id d14mr7467390pjz.56.1576600916139; Tue, 17 Dec 2019 08:41:56 -0800 (PST) Received: from ?IPv6:2605:e000:c74f:dc00:6838:d2b2:17e2:8445? ([2605:e000:c74f:dc00:6838:d2b2:17e2:8445]) by smtp.gmail.com with ESMTPSA id k190sm27695401pga.73.2019.12.17.08.41.54 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 17 Dec 2019 08:41:55 -0800 (PST) Subject: Re: [PATCH v2 06/10] arm/arm-powerctl: rebuild hflags after setting CP15 bits in arm_set_cpu_on() To: Peter Maydell , Niek Linnenbank Cc: qemu-arm , =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= , QEMU Developers References: <20191216233519.29030-1-nieklinnenbank@gmail.com> <20191216233519.29030-7-nieklinnenbank@gmail.com> From: Richard Henderson Message-ID: <19e4f2ac-6067-f61f-f340-108545fb0f02@linaro.org> Date: Tue, 17 Dec 2019 06:41:52 -1000 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.2.2 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 7bit X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::1041 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 17 Dec 2019 16:42:01 -0000 On 12/17/19 6:12 AM, Peter Maydell wrote: > Cc'ing Richard : this is one for you I think... (surely we > need to rebuild the hflags from scratch when we power up > a CPU anyway?) We do compute hflags from scratch in reset. It has also turned out that there were a few board models that poked at the contents of the cpu and needed special help. Some of that I would imagine would be fixed properly with the multi-phase reset patches, where we could rebuild hflags when *leaving* reset. In arm_set_cpu_on_async_work, we start by resetting the cpu and then start poking at the contents of some system registers. So, yes, we do need to rebuild after doing that. Also, I'm not sure how this function should fit into the multi-phase reset future. So: >> On Tue, Dec 17, 2019 at 12:36 AM Niek Linnenbank wrote: >>> >>> After setting CP15 bits in arm_set_cpu_on() the cached hflags must >>> be rebuild to reflect the changed processor state. Without rebuilding, >>> the cached hflags would be inconsistent until the next call to >>> arm_rebuild_hflags(). When QEMU is compiled with debugging enabled >>> (--enable-debug), this problem is captured shortly after the first >>> call to arm_set_cpu_on() for CPUs running in ARM 32-bit non-secure mode: >>> >>> qemu-system-arm: target/arm/helper.c:11359: cpu_get_tb_cpu_state: >>> Assertion `flags == rebuild_hflags_internal(env)' failed. >>> Aborted (core dumped) >>> >>> Fixes: 0c7f8c43daf65 >>> Signed-off-by: Niek Linnenbank >>> --- >>> target/arm/arm-powerctl.c | 3 +++ >>> 1 file changed, 3 insertions(+) >>> >>> diff --git a/target/arm/arm-powerctl.c b/target/arm/arm-powerctl.c >>> index b064513d44..b75f813b40 100644 >>> --- a/target/arm/arm-powerctl.c >>> +++ b/target/arm/arm-powerctl.c >>> @@ -127,6 +127,9 @@ static void arm_set_cpu_on_async_work(CPUState *target_cpu_state, >>> target_cpu->env.regs[0] = info->context_id; >>> } >>> >>> + /* CP15 update requires rebuilding hflags */ >>> + arm_rebuild_hflags(&target_cpu->env); >>> + >>> /* Start the new CPU at the requested address */ >>> cpu_set_pc(target_cpu_state, info->entry); >>> Reviewed-by: Richard Henderson r~ From MAILER-DAEMON Tue Dec 17 11:42:21 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1ihFvQ-0001t0-R4 for mharc-qemu-arm@gnu.org; Tue, 17 Dec 2019 11:42:20 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:52556) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ihFvN-0001my-2y for qemu-arm@nongnu.org; Tue, 17 Dec 2019 11:42:18 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ihFvM-00045b-03 for qemu-arm@nongnu.org; Tue, 17 Dec 2019 11:42:16 -0500 Received: from us-smtp-delivery-1.mimecast.com ([205.139.110.120]:52353 helo=us-smtp-1.mimecast.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1ihFvL-000432-SY for qemu-arm@nongnu.org; Tue, 17 Dec 2019 11:42:15 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1576600935; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=ZWk3zkMpgfU3ZN3J4EBBgjkfYGLkbV6WwKoyJTF7Ddg=; b=Q2MgumvdGvUajQdfGBqiQYwIMW9Qic7W5nkAzNlx1wgpI1UmMjlgTKLvdfGUWSIe4A6aNQ OAM8EFB++J8vl8pWjSaXFxynHNplww8c19ywjTaqhPZEzEZtdpF8k9FFN1GxqBWdBdnCOj DsmSG7plpGce4+fkFbbce+smJLFojyw= Received: from mimecast-mx01.redhat.com (mimecast-mx01.redhat.com [209.132.183.4]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-258-tPNfmaoHPaSfPXAbkkq9zQ-1; Tue, 17 Dec 2019 11:42:11 -0500 Received: from smtp.corp.redhat.com (int-mx05.intmail.prod.int.phx2.redhat.com [10.5.11.15]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx01.redhat.com (Postfix) with ESMTPS id 77E7080256C; Tue, 17 Dec 2019 16:42:07 +0000 (UTC) Received: from x1w.redhat.com (ovpn-205-147.brq.redhat.com [10.40.205.147]) by smtp.corp.redhat.com (Postfix) with ESMTPS id 7CA6C675B0; Tue, 17 Dec 2019 16:41:44 +0000 (UTC) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: Paolo Bonzini , =?UTF-8?q?Marc-Andr=C3=A9=20Lureau?= , qemu-devel@nongnu.org Cc: Cornelia Huck , Zhang Chen , "Michael S. Tsirkin" , Fabien Chouteau , Paul Burton , Peter Maydell , KONRAD Frederic , Aurelien Jarno , Jason Wang , qemu-block@nongnu.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Corey Minyard , Max Reitz , Li Zhijian , Gerd Hoffmann , Michael Walle , Markus Armbruster , Laurent Vivier , Igor Mitsyanko , Joel Stanley , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Bastian Koppelmann , Alberto Garcia , Peter Chubb , "Edgar E. Iglesias" , "Dr. David Alan Gilbert" , Christian Borntraeger , Andrzej Zaborowski , Aleksandar Rikalo , Aleksandar Markovic , Sagar Karandikar , Antony Pavlov , qemu-arm@nongnu.org, Alistair Francis , Kevin Wolf , qemu-s390x@nongnu.org, "Gonglei (Arei)" , Palmer Dabbelt , Samuel Thibault , Amit Shah , qemu-riscv@nongnu.org, Halil Pasic , Thomas Huth Subject: [RFC PATCH 07/14] ccid-card-passthru: Explicit we ignore QEMUChrEvent in IOEventHandler Date: Tue, 17 Dec 2019 17:38:01 +0100 Message-Id: <20191217163808.20068-8-philmd@redhat.com> In-Reply-To: <20191217163808.20068-1-philmd@redhat.com> References: <20191217163808.20068-1-philmd@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.79 on 10.5.11.15 X-MC-Unique: tPNfmaoHPaSfPXAbkkq9zQ-1 X-Mimecast-Spam-Score: 0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 205.139.110.120 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 17 Dec 2019 16:42:19 -0000 The Chardev events are listed in the QEMUChrEvent enum. To be able to use this enum in the IOEventHandler typedef, we need to explicit when frontends ignore some events, to silent GCC the following warnings: hw/usb/ccid-card-passthru.c: In function =E2=80=98ccid_card_vscard_event= =E2=80=99: hw/usb/ccid-card-passthru.c:314:5: error: enumeration value =E2=80=98CHR_= EVENT_MUX_IN=E2=80=99 not handled in switch [-Werror=3Dswitch] 314 | switch (event) { | ^~~~~~ hw/usb/ccid-card-passthru.c:314:5: error: enumeration value =E2=80=98CHR_= EVENT_MUX_OUT=E2=80=99 not handled in switch [-Werror=3Dswitch] hw/usb/ccid-card-passthru.c:314:5: error: enumeration value =E2=80=98CHR_= EVENT_CLOSED=E2=80=99 not handled in switch [-Werror=3Dswitch] cc1: all warnings being treated as errors Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- Cc: Gerd Hoffmann --- hw/usb/ccid-card-passthru.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/hw/usb/ccid-card-passthru.c b/hw/usb/ccid-card-passthru.c index 267ed9a8a0..190f268da2 100644 --- a/hw/usb/ccid-card-passthru.c +++ b/hw/usb/ccid-card-passthru.c @@ -318,6 +318,9 @@ static void ccid_card_vscard_event(void *opaque, int ev= ent) case CHR_EVENT_OPENED: DPRINTF(card, D_INFO, "%s: CHR_EVENT_OPENED\n", __func__); break; + default: + /* Ignore */ + break; } } =20 --=20 2.21.0 From MAILER-DAEMON Tue Dec 17 11:42:46 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1ihFvq-0002ah-E3 for mharc-qemu-arm@gnu.org; Tue, 17 Dec 2019 11:42:46 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:52803) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ihFvm-0002WM-Uf for qemu-arm@nongnu.org; Tue, 17 Dec 2019 11:42:44 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ihFvl-0004t0-P3 for qemu-arm@nongnu.org; Tue, 17 Dec 2019 11:42:42 -0500 Received: from us-smtp-delivery-1.mimecast.com ([205.139.110.120]:54834 helo=us-smtp-1.mimecast.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1ihFvl-0004sZ-Jg for qemu-arm@nongnu.org; Tue, 17 Dec 2019 11:42:41 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1576600961; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=1q0+8G9RTWbeMkR4IbHhx3lZKW72mNyCaGGTfMLDypg=; b=KhjVgIQOJeERrHh59Uic7l81qFudpOo5sS4d4+09CI7s4jfg3Z9LukbP5jJxfjBAT5DNFe rprGpolUU0GQbQ0LeEqolPp8MkQt0A/CrTdFtlUAkFjzZozKu4SVACinhyT8+bjXvHFG2U 4BAYA+qg3jnG+VLEHkq7zwfMj/Q2fh8= Received: from mimecast-mx01.redhat.com (mimecast-mx01.redhat.com [209.132.183.4]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-374-FX8W9uU1OgGW6LcCMY_TFA-1; Tue, 17 Dec 2019 11:42:35 -0500 Received: from smtp.corp.redhat.com (int-mx05.intmail.prod.int.phx2.redhat.com [10.5.11.15]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx01.redhat.com (Postfix) with ESMTPS id 62959593D8; Tue, 17 Dec 2019 16:42:31 +0000 (UTC) Received: from x1w.redhat.com (ovpn-205-147.brq.redhat.com [10.40.205.147]) by smtp.corp.redhat.com (Postfix) with ESMTPS id 3B4AF68865; Tue, 17 Dec 2019 16:42:07 +0000 (UTC) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: Paolo Bonzini , =?UTF-8?q?Marc-Andr=C3=A9=20Lureau?= , qemu-devel@nongnu.org Cc: Cornelia Huck , Zhang Chen , "Michael S. Tsirkin" , Fabien Chouteau , Paul Burton , Peter Maydell , KONRAD Frederic , Aurelien Jarno , Jason Wang , qemu-block@nongnu.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Corey Minyard , Max Reitz , Li Zhijian , Gerd Hoffmann , Michael Walle , Markus Armbruster , Laurent Vivier , Igor Mitsyanko , Joel Stanley , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Bastian Koppelmann , Alberto Garcia , Peter Chubb , "Edgar E. Iglesias" , "Dr. David Alan Gilbert" , Christian Borntraeger , Andrzej Zaborowski , Aleksandar Rikalo , Aleksandar Markovic , Sagar Karandikar , Antony Pavlov , qemu-arm@nongnu.org, Alistair Francis , Kevin Wolf , qemu-s390x@nongnu.org, "Gonglei (Arei)" , Palmer Dabbelt , Samuel Thibault , Amit Shah , qemu-riscv@nongnu.org, Halil Pasic , Thomas Huth Subject: [RFC PATCH 08/14] hw/usb/redirect: Explicit we ignore few QEMUChrEvent in IOEventHandler Date: Tue, 17 Dec 2019 17:38:02 +0100 Message-Id: <20191217163808.20068-9-philmd@redhat.com> In-Reply-To: <20191217163808.20068-1-philmd@redhat.com> References: <20191217163808.20068-1-philmd@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.79 on 10.5.11.15 X-MC-Unique: FX8W9uU1OgGW6LcCMY_TFA-1 X-Mimecast-Spam-Score: 0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 205.139.110.120 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 17 Dec 2019 16:42:44 -0000 The Chardev events are listed in the QEMUChrEvent enum. To be able to use this enum in the IOEventHandler typedef, we need to explicit when frontends ignore some events, to silent GCC the following warnings: CC hw/usb/redirect.o hw/usb/redirect.c: In function =E2=80=98usbredir_chardev_event=E2=80=99: hw/usb/redirect.c:1361:5: error: enumeration value =E2=80=98CHR_EVENT_BRE= AK=E2=80=99 not handled in switch [-Werror=3Dswitch] 1361 | switch (event) { | ^~~~~~ hw/usb/redirect.c:1361:5: error: enumeration value =E2=80=98CHR_EVENT_MUX= _IN=E2=80=99 not handled in switch [-Werror=3Dswitch] hw/usb/redirect.c:1361:5: error: enumeration value =E2=80=98CHR_EVENT_MUX= _OUT=E2=80=99 not handled in switch [-Werror=3Dswitch] cc1: all warnings being treated as errors Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- Cc: Gerd Hoffmann --- hw/usb/redirect.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/hw/usb/redirect.c b/hw/usb/redirect.c index e0f5ca6f81..acc376cc95 100644 --- a/hw/usb/redirect.c +++ b/hw/usb/redirect.c @@ -1370,6 +1370,9 @@ static void usbredir_chardev_event(void *opaque, int = event) DPRINTF("chardev close\n"); qemu_bh_schedule(dev->chardev_close_bh); break; + default: + /* Ignore */ + break; } } =20 --=20 2.21.0 From MAILER-DAEMON Tue Dec 17 11:43:11 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1ihFwF-0003Bh-PY for mharc-qemu-arm@gnu.org; Tue, 17 Dec 2019 11:43:11 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:52978) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ihFwC-00036f-4A for qemu-arm@nongnu.org; Tue, 17 Dec 2019 11:43:09 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ihFwB-0005OS-2H for qemu-arm@nongnu.org; Tue, 17 Dec 2019 11:43:07 -0500 Received: from us-smtp-1.mimecast.com ([207.211.31.81]:24392 helo=us-smtp-delivery-1.mimecast.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1ihFwA-0005Ns-V4 for qemu-arm@nongnu.org; Tue, 17 Dec 2019 11:43:07 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1576600986; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=LWPdmhlylc1YC5H9DvoZFc9kbqPgnBG8SfVBw2Anx8I=; b=PXJo1+fbrtrISifAMs+xnXJAp8Z8JpikzQ9xdtf/5hia42uzWLYq613BHhxy8RNBG4LCyc PezH1RB7JBytPSeY1shT8HWRy/hVNfQFOHqhHR2CgKNe+bEB1NZ27RHVJfo9uH5ez5lD/n lo3GM6fR5PSC091J5b8B6w9UjVxZ1yk= Received: from mimecast-mx01.redhat.com (mimecast-mx01.redhat.com [209.132.183.4]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-253-itWGShRrPOK60sk3Fmx78g-1; Tue, 17 Dec 2019 11:43:03 -0500 Received: from smtp.corp.redhat.com (int-mx05.intmail.prod.int.phx2.redhat.com [10.5.11.15]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx01.redhat.com (Postfix) with ESMTPS id 6EDC86A2A6; Tue, 17 Dec 2019 16:42:57 +0000 (UTC) Received: from x1w.redhat.com (ovpn-205-147.brq.redhat.com [10.40.205.147]) by smtp.corp.redhat.com (Postfix) with ESMTPS id C5A5B68865; Tue, 17 Dec 2019 16:42:31 +0000 (UTC) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: Paolo Bonzini , =?UTF-8?q?Marc-Andr=C3=A9=20Lureau?= , qemu-devel@nongnu.org Cc: Cornelia Huck , Zhang Chen , "Michael S. Tsirkin" , Fabien Chouteau , Paul Burton , Peter Maydell , KONRAD Frederic , Aurelien Jarno , Jason Wang , qemu-block@nongnu.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Corey Minyard , Max Reitz , Li Zhijian , Gerd Hoffmann , Michael Walle , Markus Armbruster , Laurent Vivier , Igor Mitsyanko , Joel Stanley , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Bastian Koppelmann , Alberto Garcia , Peter Chubb , "Edgar E. Iglesias" , "Dr. David Alan Gilbert" , Christian Borntraeger , Andrzej Zaborowski , Aleksandar Rikalo , Aleksandar Markovic , Sagar Karandikar , Antony Pavlov , qemu-arm@nongnu.org, Alistair Francis , Kevin Wolf , qemu-s390x@nongnu.org, "Gonglei (Arei)" , Palmer Dabbelt , Samuel Thibault , Amit Shah , qemu-riscv@nongnu.org, Halil Pasic , Thomas Huth Subject: [RFC PATCH 09/14] monitor/qmp: Explicit we ignore few QEMUChrEvent in IOEventHandler Date: Tue, 17 Dec 2019 17:38:03 +0100 Message-Id: <20191217163808.20068-10-philmd@redhat.com> In-Reply-To: <20191217163808.20068-1-philmd@redhat.com> References: <20191217163808.20068-1-philmd@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.79 on 10.5.11.15 X-MC-Unique: itWGShRrPOK60sk3Fmx78g-1 X-Mimecast-Spam-Score: 0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 207.211.31.81 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 17 Dec 2019 16:43:10 -0000 The Chardev events are listed in the QEMUChrEvent enum. To be able to use this enum in the IOEventHandler typedef, we need to explicit when frontends ignore some events, to silent GCC the following warnings: CC monitor/qmp.o monitor/qmp.c: In function =E2=80=98monitor_qmp_event=E2=80=99: monitor/qmp.c:345:5: error: enumeration value =E2=80=98CHR_EVENT_BREAK=E2= =80=99 not handled in switch [-Werror=3Dswitch] 345 | switch (event) { | ^~~~~~ monitor/qmp.c:345:5: error: enumeration value =E2=80=98CHR_EVENT_MUX_IN= =E2=80=99 not handled in switch [-Werror=3Dswitch] monitor/qmp.c:345:5: error: enumeration value =E2=80=98CHR_EVENT_MUX_OUT= =E2=80=99 not handled in switch [-Werror=3Dswitch] cc1: all warnings being treated as errors Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- Cc: Markus Armbruster --- monitor/qmp.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/monitor/qmp.c b/monitor/qmp.c index b67a8e7d1f..d666b07e68 100644 --- a/monitor/qmp.c +++ b/monitor/qmp.c @@ -365,6 +365,9 @@ static void monitor_qmp_event(void *opaque, int event) mon_refcount--; monitor_fdsets_cleanup(); break; + default: + /* Ignore */ + break; } } =20 --=20 2.21.0 From MAILER-DAEMON Tue Dec 17 11:43:39 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1ihFwh-0003xf-Qh for mharc-qemu-arm@gnu.org; Tue, 17 Dec 2019 11:43:39 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:53342) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ihFwe-0003rF-6d for qemu-arm@nongnu.org; Tue, 17 Dec 2019 11:43:37 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ihFwd-0006AN-2n for qemu-arm@nongnu.org; Tue, 17 Dec 2019 11:43:35 -0500 Received: from us-smtp-delivery-1.mimecast.com ([205.139.110.120]:57080 helo=us-smtp-1.mimecast.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1ihFwc-00069x-VM for qemu-arm@nongnu.org; Tue, 17 Dec 2019 11:43:35 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1576601014; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=VieRlOSNQiL1buz6KYPsrx/GicOx3CeNAj0YsqGdShM=; b=XXPTUo+H1SSrwVRjqGB/PxhTyZVU5SYj9fXz40wEwwRrvktxkyr5cSE4jzBMWrJRv2nEv3 ToJ5Slb1C5fuosQhj+NrmHNhHA1AUwRLfkb5IDQpUgOGwqprz2AT7hivnfRx87bkA/L8an oUmCNcbkuE+xv6kWNi8RY8KkRGb5iFg= Received: from mimecast-mx01.redhat.com (mimecast-mx01.redhat.com [209.132.183.4]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-40-SwlvgClkOOWB37uaT4TC1A-1; Tue, 17 Dec 2019 11:43:30 -0500 Received: from smtp.corp.redhat.com (int-mx05.intmail.prod.int.phx2.redhat.com [10.5.11.15]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx01.redhat.com (Postfix) with ESMTPS id BF70F18B6394; Tue, 17 Dec 2019 16:43:25 +0000 (UTC) Received: from x1w.redhat.com (ovpn-205-147.brq.redhat.com [10.40.205.147]) by smtp.corp.redhat.com (Postfix) with ESMTPS id 039D368865; Tue, 17 Dec 2019 16:42:57 +0000 (UTC) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: Paolo Bonzini , =?UTF-8?q?Marc-Andr=C3=A9=20Lureau?= , qemu-devel@nongnu.org Cc: Cornelia Huck , Zhang Chen , "Michael S. Tsirkin" , Fabien Chouteau , Paul Burton , Peter Maydell , KONRAD Frederic , Aurelien Jarno , Jason Wang , qemu-block@nongnu.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Corey Minyard , Max Reitz , Li Zhijian , Gerd Hoffmann , Michael Walle , Markus Armbruster , Laurent Vivier , Igor Mitsyanko , Joel Stanley , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Bastian Koppelmann , Alberto Garcia , Peter Chubb , "Edgar E. Iglesias" , "Dr. David Alan Gilbert" , Christian Borntraeger , Andrzej Zaborowski , Aleksandar Rikalo , Aleksandar Markovic , Sagar Karandikar , Antony Pavlov , qemu-arm@nongnu.org, Alistair Francis , Kevin Wolf , qemu-s390x@nongnu.org, "Gonglei (Arei)" , Palmer Dabbelt , Samuel Thibault , Amit Shah , qemu-riscv@nongnu.org, Halil Pasic , Thomas Huth Subject: [RFC PATCH 10/14] monitor/hmp: Explicit we ignore a QEMUChrEvent in IOEventHandler Date: Tue, 17 Dec 2019 17:38:04 +0100 Message-Id: <20191217163808.20068-11-philmd@redhat.com> In-Reply-To: <20191217163808.20068-1-philmd@redhat.com> References: <20191217163808.20068-1-philmd@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.79 on 10.5.11.15 X-MC-Unique: SwlvgClkOOWB37uaT4TC1A-1 X-Mimecast-Spam-Score: 0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 205.139.110.120 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 17 Dec 2019 16:43:38 -0000 The Chardev events are listed in the QEMUChrEvent enum. To be able to use this enum in the IOEventHandler typedef, we need to explicit when frontends ignore some events, to silent GCC the following warnings: CC monitor/hmp.o monitor/hmp.c: In function =E2=80=98monitor_event=E2=80=99: monitor/hmp.c:1330:5: error: enumeration value =E2=80=98CHR_EVENT_BREAK= =E2=80=99 not handled in switch [-Werror=3Dswitch] 1330 | switch (event) { | ^~~~~~ cc1: all warnings being treated as errors Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- Cc: "Dr. David Alan Gilbert" --- monitor/hmp.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/monitor/hmp.c b/monitor/hmp.c index 8942e28933..d84238c120 100644 --- a/monitor/hmp.c +++ b/monitor/hmp.c @@ -1371,6 +1371,10 @@ static void monitor_event(void *opaque, int event) mon_refcount--; monitor_fdsets_cleanup(); break; + + default: + /* Ignore */ + break; } } =20 --=20 2.21.0 From MAILER-DAEMON Tue Dec 17 11:44:04 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1ihFx6-0004Nm-Bc for mharc-qemu-arm@gnu.org; Tue, 17 Dec 2019 11:44:04 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:53564) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ihFx3-0004Lc-F2 for qemu-arm@nongnu.org; Tue, 17 Dec 2019 11:44:02 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ihFx1-0006pa-59 for qemu-arm@nongnu.org; Tue, 17 Dec 2019 11:44:00 -0500 Received: from us-smtp-1.mimecast.com ([207.211.31.81]:26044) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1ihFx1-0006oW-1W for qemu-arm@nongnu.org; Tue, 17 Dec 2019 11:43:59 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1576601038; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=KFfF62p0wtfpbuoQUs8fUU7/4Wwx9UtbFBKJZwS7G3M=; b=SGmsAHzClc+DEc2K6fdH7BqAXGTLei4Z+4ch+sOtlcdwyHP7Do9N2F0BsWc1I/P7VZdYMh CDoS+JD+VdAmD6cb4bkK1aPrwUnrci2ilyjBUWmt91apVFHujPnHqBoVLrTquVwKW24VZx wMJv22t4dsdG7KTbX4P7FL1JnkiZkXI= Received: from mimecast-mx01.redhat.com (mimecast-mx01.redhat.com [209.132.183.4]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-1-7TX2JT0qOyim0MLRiwnoeg-1; Tue, 17 Dec 2019 11:43:54 -0500 Received: from smtp.corp.redhat.com (int-mx05.intmail.prod.int.phx2.redhat.com [10.5.11.15]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx01.redhat.com (Postfix) with ESMTPS id 16A93A0A6B; Tue, 17 Dec 2019 16:43:50 +0000 (UTC) Received: from x1w.redhat.com (ovpn-205-147.brq.redhat.com [10.40.205.147]) by smtp.corp.redhat.com (Postfix) with ESMTPS id 2B5E468877; Tue, 17 Dec 2019 16:43:25 +0000 (UTC) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: Paolo Bonzini , =?UTF-8?q?Marc-Andr=C3=A9=20Lureau?= , qemu-devel@nongnu.org Cc: Cornelia Huck , Zhang Chen , "Michael S. Tsirkin" , Fabien Chouteau , Paul Burton , Peter Maydell , KONRAD Frederic , Aurelien Jarno , Jason Wang , qemu-block@nongnu.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Corey Minyard , Max Reitz , Li Zhijian , Gerd Hoffmann , Michael Walle , Markus Armbruster , Laurent Vivier , Igor Mitsyanko , Joel Stanley , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Bastian Koppelmann , Alberto Garcia , Peter Chubb , "Edgar E. Iglesias" , "Dr. David Alan Gilbert" , Christian Borntraeger , Andrzej Zaborowski , Aleksandar Rikalo , Aleksandar Markovic , Sagar Karandikar , Antony Pavlov , qemu-arm@nongnu.org, Alistair Francis , Kevin Wolf , qemu-s390x@nongnu.org, "Gonglei (Arei)" , Palmer Dabbelt , Samuel Thibault , Amit Shah , qemu-riscv@nongnu.org, Halil Pasic , Thomas Huth Subject: [RFC PATCH 11/14] net/vhost-user: Explicit we ignore few QEMUChrEvent in IOEventHandler Date: Tue, 17 Dec 2019 17:38:05 +0100 Message-Id: <20191217163808.20068-12-philmd@redhat.com> In-Reply-To: <20191217163808.20068-1-philmd@redhat.com> References: <20191217163808.20068-1-philmd@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.79 on 10.5.11.15 X-MC-Unique: 7TX2JT0qOyim0MLRiwnoeg-1 X-Mimecast-Spam-Score: 0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 207.211.31.81 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 17 Dec 2019 16:44:02 -0000 The Chardev events are listed in the QEMUChrEvent enum. To be able to use this enum in the IOEventHandler typedef, we need to explicit when frontends ignore some events, to silent GCC the following warnings: CC net/vhost-user.o net/vhost-user.c: In function =E2=80=98net_vhost_user_event=E2=80=99: net/vhost-user.c:269:5: error: enumeration value =E2=80=98CHR_EVENT_BREAK= =E2=80=99 not handled in switch [-Werror=3Dswitch] 269 | switch (event) { | ^~~~~~ net/vhost-user.c:269:5: error: enumeration value =E2=80=98CHR_EVENT_MUX_I= N=E2=80=99 not handled in switch [-Werror=3Dswitch] net/vhost-user.c:269:5: error: enumeration value =E2=80=98CHR_EVENT_MUX_O= UT=E2=80=99 not handled in switch [-Werror=3Dswitch] cc1: all warnings being treated as errors Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- Cc: "Michael S. Tsirkin" Cc: Jason Wang --- net/vhost-user.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/net/vhost-user.c b/net/vhost-user.c index 014199d600..383d68024e 100644 --- a/net/vhost-user.c +++ b/net/vhost-user.c @@ -294,6 +294,9 @@ static void net_vhost_user_event(void *opaque, int even= t) aio_bh_schedule_oneshot(ctx, chr_closed_bh, opaque); } break; + default: + /* Ignore */ + break; } =20 if (err) { --=20 2.21.0 From MAILER-DAEMON Tue Dec 17 11:44:29 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1ihFxV-0004na-DJ for mharc-qemu-arm@gnu.org; Tue, 17 Dec 2019 11:44:29 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:53762) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ihFxR-0004hP-Gl for qemu-arm@nongnu.org; Tue, 17 Dec 2019 11:44:26 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ihFxQ-0007Fz-AA for qemu-arm@nongnu.org; Tue, 17 Dec 2019 11:44:25 -0500 Received: from us-smtp-1.mimecast.com ([207.211.31.81]:50716 helo=us-smtp-delivery-1.mimecast.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1ihFxQ-0007FZ-56 for qemu-arm@nongnu.org; Tue, 17 Dec 2019 11:44:24 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1576601063; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=MYVIpFLxZh/foCyP2XwIVnvo4LnIBsgaGRLRhMaYw14=; b=PRqc/4FSK0EezMtFucpWfaxMAvKfPmdv8O7abU8yVdZQ3Cch10WgYk1xIdXKN4cXn8Wqnz Wu9eWtTpKD9OXwBjKfhMz8woVhSUZJnb6vjvsG69P0UN0lt8b8DYStKP1ai2zwEW0AWryU WmEli4lyDxsVgxivK5++v+O4qIvxueE= Received: from mimecast-mx01.redhat.com (mimecast-mx01.redhat.com [209.132.183.4]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-279-wgik6hrlOhGkOgAq2xvtuQ-1; Tue, 17 Dec 2019 11:44:19 -0500 Received: from smtp.corp.redhat.com (int-mx05.intmail.prod.int.phx2.redhat.com [10.5.11.15]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx01.redhat.com (Postfix) with ESMTPS id 770751023150; Tue, 17 Dec 2019 16:44:15 +0000 (UTC) Received: from x1w.redhat.com (ovpn-205-147.brq.redhat.com [10.40.205.147]) by smtp.corp.redhat.com (Postfix) with ESMTPS id 7598D68877; Tue, 17 Dec 2019 16:43:50 +0000 (UTC) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: Paolo Bonzini , =?UTF-8?q?Marc-Andr=C3=A9=20Lureau?= , qemu-devel@nongnu.org Cc: Cornelia Huck , Zhang Chen , "Michael S. Tsirkin" , Fabien Chouteau , Paul Burton , Peter Maydell , KONRAD Frederic , Aurelien Jarno , Jason Wang , qemu-block@nongnu.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Corey Minyard , Max Reitz , Li Zhijian , Gerd Hoffmann , Michael Walle , Markus Armbruster , Laurent Vivier , Igor Mitsyanko , Joel Stanley , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Bastian Koppelmann , Alberto Garcia , Peter Chubb , "Edgar E. Iglesias" , "Dr. David Alan Gilbert" , Christian Borntraeger , Andrzej Zaborowski , Aleksandar Rikalo , Aleksandar Markovic , Sagar Karandikar , Antony Pavlov , qemu-arm@nongnu.org, Alistair Francis , Kevin Wolf , qemu-s390x@nongnu.org, "Gonglei (Arei)" , Palmer Dabbelt , Samuel Thibault , Amit Shah , qemu-riscv@nongnu.org, Halil Pasic , Thomas Huth Subject: [RFC PATCH 12/14] vhost-user-blk: Explicit we ignore few QEMUChrEvent in IOEventHandler Date: Tue, 17 Dec 2019 17:38:06 +0100 Message-Id: <20191217163808.20068-13-philmd@redhat.com> In-Reply-To: <20191217163808.20068-1-philmd@redhat.com> References: <20191217163808.20068-1-philmd@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.79 on 10.5.11.15 X-MC-Unique: wgik6hrlOhGkOgAq2xvtuQ-1 X-Mimecast-Spam-Score: 0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 207.211.31.81 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 17 Dec 2019 16:44:27 -0000 The Chardev events are listed in the QEMUChrEvent enum. To be able to use this enum in the IOEventHandler typedef, we need to explicit when frontends ignore some events, to silent GCC the following warnings: CC s390x-softmmu/hw/block/vhost-user-blk.o hw/block/vhost-user-blk.c: In function =E2=80=98vhost_user_blk_event=E2= =80=99: hw/block/vhost-user-blk.c:370:5: error: enumeration value =E2=80=98CHR_EV= ENT_BREAK=E2=80=99 not handled in switch [-Werror=3Dswitch] 370 | switch (event) { | ^~~~~~ hw/block/vhost-user-blk.c:370:5: error: enumeration value =E2=80=98CHR_EV= ENT_MUX_IN=E2=80=99 not handled in switch [-Werror=3Dswitch] hw/block/vhost-user-blk.c:370:5: error: enumeration value =E2=80=98CHR_EV= ENT_MUX_OUT=E2=80=99 not handled in switch [-Werror=3Dswitch] cc1: all warnings being treated as errors Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- Cc: "Michael S. Tsirkin" Cc: Kevin Wolf Cc: Max Reitz Cc: qemu-block@nongnu.org --- hw/block/vhost-user-blk.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/hw/block/vhost-user-blk.c b/hw/block/vhost-user-blk.c index 63da9bb619..4e2b2efdd3 100644 --- a/hw/block/vhost-user-blk.c +++ b/hw/block/vhost-user-blk.c @@ -383,6 +383,9 @@ static void vhost_user_blk_event(void *opaque, int even= t) s->watch =3D 0; } break; + default: + /* Ignore */ + break; } } =20 --=20 2.21.0 From MAILER-DAEMON Tue Dec 17 11:44:55 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1ihFxv-0005F3-7N for mharc-qemu-arm@gnu.org; Tue, 17 Dec 2019 11:44:55 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:54020) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ihFxr-0005AK-Gj for qemu-arm@nongnu.org; Tue, 17 Dec 2019 11:44:52 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ihFxq-0007ce-AC for qemu-arm@nongnu.org; Tue, 17 Dec 2019 11:44:51 -0500 Received: from us-smtp-delivery-1.mimecast.com ([207.211.31.120]:59233 helo=us-smtp-1.mimecast.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1ihFxq-0007cG-5w for qemu-arm@nongnu.org; Tue, 17 Dec 2019 11:44:50 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1576601089; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=cgmzu31Rt2ux67Lpas/rsmhkVxbL3amuZtxQ77YbDhM=; b=A3ynwGswjViAkFb7MBzdTpRJHjBvjoEn/64MlPl7XdH3ckSyUSUEE8644+j0+Qn3Q+E4IU 6WuH6aQLtvYjKxo0P82lfGIj8Epx4PFT43YvdbtsbLp4XRCZK8QKV50Zuc0//EZKL4OvFm 67SAAwUE/29Z+0Fm4uOexvKOZhmvQGk= Received: from mimecast-mx01.redhat.com (mimecast-mx01.redhat.com [209.132.183.4]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-189-K55-sau0PYefSDfGkLWuzg-1; Tue, 17 Dec 2019 11:44:46 -0500 Received: from smtp.corp.redhat.com (int-mx05.intmail.prod.int.phx2.redhat.com [10.5.11.15]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx01.redhat.com (Postfix) with ESMTPS id 0F0631183E1A; Tue, 17 Dec 2019 16:44:41 +0000 (UTC) Received: from x1w.redhat.com (ovpn-205-147.brq.redhat.com [10.40.205.147]) by smtp.corp.redhat.com (Postfix) with ESMTPS id EB86F68894; Tue, 17 Dec 2019 16:44:15 +0000 (UTC) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: Paolo Bonzini , =?UTF-8?q?Marc-Andr=C3=A9=20Lureau?= , qemu-devel@nongnu.org Cc: Cornelia Huck , Zhang Chen , "Michael S. Tsirkin" , Fabien Chouteau , Paul Burton , Peter Maydell , KONRAD Frederic , Aurelien Jarno , Jason Wang , qemu-block@nongnu.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Corey Minyard , Max Reitz , Li Zhijian , Gerd Hoffmann , Michael Walle , Markus Armbruster , Laurent Vivier , Igor Mitsyanko , Joel Stanley , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Bastian Koppelmann , Alberto Garcia , Peter Chubb , "Edgar E. Iglesias" , "Dr. David Alan Gilbert" , Christian Borntraeger , Andrzej Zaborowski , Aleksandar Rikalo , Aleksandar Markovic , Sagar Karandikar , Antony Pavlov , qemu-arm@nongnu.org, Alistair Francis , Kevin Wolf , qemu-s390x@nongnu.org, "Gonglei (Arei)" , Palmer Dabbelt , Samuel Thibault , Amit Shah , qemu-riscv@nongnu.org, Halil Pasic , Thomas Huth Subject: [RFC PATCH 13/14] hw/char/terminal3270: Explicit ignored QEMUChrEvent in IOEventHandler Date: Tue, 17 Dec 2019 17:38:07 +0100 Message-Id: <20191217163808.20068-14-philmd@redhat.com> In-Reply-To: <20191217163808.20068-1-philmd@redhat.com> References: <20191217163808.20068-1-philmd@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.79 on 10.5.11.15 X-MC-Unique: K55-sau0PYefSDfGkLWuzg-1 X-Mimecast-Spam-Score: 0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 207.211.31.120 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 17 Dec 2019 16:44:53 -0000 The Chardev events are listed in the QEMUChrEvent enum. To be able to use this enum in the IOEventHandler typedef, we need to explicit when frontends ignore some events, to silent GCC the following warnings: CC s390x-softmmu/hw/char/terminal3270.o hw/char/terminal3270.c: In function =E2=80=98chr_event=E2=80=99: hw/char/terminal3270.c:156:5: error: enumeration value =E2=80=98CHR_EVENT= _BREAK=E2=80=99 not handled in switch [-Werror=3Dswitch] 156 | switch (event) { | ^~~~~~ hw/char/terminal3270.c:156:5: error: enumeration value =E2=80=98CHR_EVENT= _MUX_IN=E2=80=99 not handled in switch [-Werror=3Dswitch] hw/char/terminal3270.c:156:5: error: enumeration value =E2=80=98CHR_EVENT= _MUX_OUT=E2=80=99 not handled in switch [-Werror=3Dswitch] cc1: all warnings being treated as errors Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- Cc: Cornelia Huck Cc: Halil Pasic Cc: Christian Borntraeger Cc: "Marc-Andr=C3=A9 Lureau" Cc: Paolo Bonzini Cc: qemu-s390x@nongnu.org --- hw/char/terminal3270.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/hw/char/terminal3270.c b/hw/char/terminal3270.c index 6859c1bcb2..9e59a2d92b 100644 --- a/hw/char/terminal3270.c +++ b/hw/char/terminal3270.c @@ -166,6 +166,9 @@ static void chr_event(void *opaque, int event) sch->curr_status.scsw.dstat =3D SCSW_DSTAT_DEVICE_END; css_conditional_io_interrupt(sch); break; + default: + /* Ignore */ + break; } } =20 --=20 2.21.0 From MAILER-DAEMON Tue Dec 17 11:45:32 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1ihFyW-00061W-P1 for mharc-qemu-arm@gnu.org; Tue, 17 Dec 2019 11:45:32 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:54316) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ihFyN-0005tq-Nt for qemu-arm@nongnu.org; Tue, 17 Dec 2019 11:45:28 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ihFyJ-0008Rx-8D for qemu-arm@nongnu.org; Tue, 17 Dec 2019 11:45:23 -0500 Received: from us-smtp-1.mimecast.com ([207.211.31.81]:21435 helo=us-smtp-delivery-1.mimecast.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1ihFyI-0008Oi-RB for qemu-arm@nongnu.org; Tue, 17 Dec 2019 11:45:18 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1576601118; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=eSKAIfhZrf4AzOzwxHf94n1FTTYtkdtk5h8oMtIkBhQ=; b=RdURpsDFoyI4zswFaaK8DtPBb0nzazYF2Ha8V5wpRa9yoFYcZq1JV8460/bhjC2CNe85iv W4HpwYtgVXXraby94QMXrOp4x3XQ0JQylbOPIvoJ8RnBxdmqGnnJFZQJdEOBxwHvMIvckG o/FXviZ0OVDgGvYEfMKCXkdifeCJygo= Received: from mimecast-mx01.redhat.com (mimecast-mx01.redhat.com [209.132.183.4]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-243-1NDoE56uPtOn0SM-We1RLw-1; Tue, 17 Dec 2019 11:45:14 -0500 Received: from smtp.corp.redhat.com (int-mx05.intmail.prod.int.phx2.redhat.com [10.5.11.15]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx01.redhat.com (Postfix) with ESMTPS id 5C408800C80; Tue, 17 Dec 2019 16:45:09 +0000 (UTC) Received: from x1w.redhat.com (ovpn-205-147.brq.redhat.com [10.40.205.147]) by smtp.corp.redhat.com (Postfix) with ESMTPS id B888B68882; Tue, 17 Dec 2019 16:44:41 +0000 (UTC) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: Paolo Bonzini , =?UTF-8?q?Marc-Andr=C3=A9=20Lureau?= , qemu-devel@nongnu.org Cc: Cornelia Huck , Zhang Chen , "Michael S. Tsirkin" , Fabien Chouteau , Paul Burton , Peter Maydell , KONRAD Frederic , Aurelien Jarno , Jason Wang , qemu-block@nongnu.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Corey Minyard , Max Reitz , Li Zhijian , Gerd Hoffmann , Michael Walle , Markus Armbruster , Laurent Vivier , Igor Mitsyanko , Joel Stanley , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Bastian Koppelmann , Alberto Garcia , Peter Chubb , "Edgar E. Iglesias" , "Dr. David Alan Gilbert" , Christian Borntraeger , Andrzej Zaborowski , Aleksandar Rikalo , Aleksandar Markovic , Sagar Karandikar , Antony Pavlov , qemu-arm@nongnu.org, Alistair Francis , Kevin Wolf , qemu-s390x@nongnu.org, "Gonglei (Arei)" , Palmer Dabbelt , Samuel Thibault , Amit Shah , qemu-riscv@nongnu.org, Halil Pasic , Thomas Huth Subject: [PATCH 14/14] chardev: Use QEMUChrEvent enum in IOEventHandler typedef Date: Tue, 17 Dec 2019 17:38:08 +0100 Message-Id: <20191217163808.20068-15-philmd@redhat.com> In-Reply-To: <20191217163808.20068-1-philmd@redhat.com> References: <20191217163808.20068-1-philmd@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.79 on 10.5.11.15 X-MC-Unique: 1NDoE56uPtOn0SM-We1RLw-1 X-Mimecast-Spam-Score: 0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 207.211.31.81 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 17 Dec 2019 16:45:29 -0000 The Chardev events are listed in the QEMUChrEvent enum. By using the enum in the IOEventHandler typedef we: - make the IOEventHandler type more explicit (this handler process out-of-band information, while the IOReadHandler is in-band), - help static code analyzers. This patch was produced with the following spatch script: @match@ expression backend, opaque, context, set_open; identifier fd_can_read, fd_read, fd_event, be_change; @@ qemu_chr_fe_set_handlers(backend, fd_can_read, fd_read, fd_event, be_change, opaque, context, set_open); @depends on match@ identifier opaque, event; identifier match.fd_event; @@ static -void fd_event(void *opaque, int event) +void fd_event(void *opaque, QEMUChrEvent event) { ... } Then the following files were manually modified: - include/chardev/char-fe.h - include/chardev/char.h - include/chardev/char-mux.h - chardev/char.c - chardev/char-mux.c Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- Cc: "Gonglei (Arei)" Cc: "Marc-Andr=C3=A9 Lureau" Cc: Paolo Bonzini Cc: "Alex Benn=C3=A9e" Cc: "Philippe Mathieu-Daud=C3=A9" Cc: Andrzej Zaborowski Cc: Peter Maydell Cc: "Michael S. Tsirkin" Cc: Kevin Wolf Cc: Max Reitz Cc: "Edgar E. Iglesias" Cc: Alistair Francis Cc: Antony Pavlov Cc: Igor Mitsyanko Cc: Fabien Chouteau Cc: KONRAD Frederic Cc: Peter Chubb Cc: Alberto Garcia Cc: Michael Walle Cc: Thomas Huth Cc: Joel Stanley Cc: Cornelia Huck Cc: Halil Pasic Cc: Christian Borntraeger Cc: Laurent Vivier Cc: Amit Shah Cc: Corey Minyard Cc: Paul Burton Cc: Aleksandar Rikalo Cc: Aurelien Jarno Cc: Aleksandar Markovic Cc: Palmer Dabbelt Cc: Sagar Karandikar Cc: Bastian Koppelmann Cc: Gerd Hoffmann Cc: Samuel Thibault Cc: "Dr. David Alan Gilbert" Cc: Markus Armbruster Cc: Zhang Chen Cc: Li Zhijian Cc: Jason Wang Cc: qemu-arm@nongnu.org Cc: qemu-block@nongnu.org Cc: qemu-s390x@nongnu.org Cc: qemu-riscv@nongnu.org --- include/chardev/char-fe.h | 2 +- include/chardev/char-mux.h | 2 +- include/chardev/char.h | 4 ++-- backends/cryptodev-vhost-user.c | 2 +- chardev/char-mux.c | 8 ++++---- chardev/char.c | 4 ++-- gdbstub.c | 2 +- hw/arm/pxa2xx.c | 2 +- hw/arm/strongarm.c | 2 +- hw/block/vhost-user-blk.c | 2 +- hw/char/cadence_uart.c | 2 +- hw/char/digic-uart.c | 2 +- hw/char/escc.c | 2 +- hw/char/etraxfs_ser.c | 2 +- hw/char/exynos4210_uart.c | 2 +- hw/char/grlib_apbuart.c | 2 +- hw/char/imx_serial.c | 2 +- hw/char/ipoctal232.c | 2 +- hw/char/lm32_juart.c | 2 +- hw/char/lm32_uart.c | 2 +- hw/char/mcf_uart.c | 2 +- hw/char/milkymist-uart.c | 2 +- hw/char/nrf51_uart.c | 2 +- hw/char/pl011.c | 2 +- hw/char/serial.c | 2 +- hw/char/sh_serial.c | 2 +- hw/char/terminal3270.c | 2 +- hw/char/virtio-console.c | 2 +- hw/char/xilinx_uartlite.c | 2 +- hw/ipmi/ipmi_bmc_extern.c | 2 +- hw/mips/boston.c | 2 +- hw/mips/mips_malta.c | 2 +- hw/riscv/riscv_htif.c | 2 +- hw/riscv/sifive_uart.c | 2 +- hw/usb/ccid-card-passthru.c | 2 +- hw/usb/dev-serial.c | 2 +- hw/usb/redirect.c | 2 +- monitor/hmp.c | 2 +- monitor/qmp.c | 2 +- net/filter-mirror.c | 2 +- net/vhost-user.c | 4 ++-- qtest.c | 2 +- tests/test-char.c | 6 +++--- tests/vhost-user-test.c | 2 +- 44 files changed, 52 insertions(+), 52 deletions(-) diff --git a/include/chardev/char-fe.h b/include/chardev/char-fe.h index 67601dc9a4..a553843364 100644 --- a/include/chardev/char-fe.h +++ b/include/chardev/char-fe.h @@ -4,7 +4,7 @@ #include "chardev/char.h" #include "qemu/main-loop.h" =20 -typedef void IOEventHandler(void *opaque, int event); +typedef void IOEventHandler(void *opaque, QEMUChrEvent event); typedef int BackendChangeHandler(void *opaque); =20 /* This is the backend as seen by frontend, the actual backend is diff --git a/include/chardev/char-mux.h b/include/chardev/char-mux.h index 572cefd517..417fe32eed 100644 --- a/include/chardev/char-mux.h +++ b/include/chardev/char-mux.h @@ -56,6 +56,6 @@ typedef struct MuxChardev { object_dynamic_cast(OBJECT(chr), TYPE_CHARDEV_MUX) =20 void mux_set_focus(Chardev *chr, int focus); -void mux_chr_send_all_event(Chardev *chr, int event); +void mux_chr_send_all_event(Chardev *chr, QEMUChrEvent event); =20 #endif /* CHAR_MUX_H */ diff --git a/include/chardev/char.h b/include/chardev/char.h index 087b202b62..00589a6025 100644 --- a/include/chardev/char.h +++ b/include/chardev/char.h @@ -210,7 +210,7 @@ void qemu_chr_be_update_read_handlers(Chardev *s, * * Send an event from the back end to the front end. */ -void qemu_chr_be_event(Chardev *s, int event); +void qemu_chr_be_event(Chardev *s, QEMUChrEvent event); =20 int qemu_chr_add_client(Chardev *s, int fd); Chardev *qemu_chr_find(const char *name); @@ -273,7 +273,7 @@ typedef struct ChardevClass { void (*chr_accept_input)(Chardev *chr); void (*chr_set_echo)(Chardev *chr, bool echo); void (*chr_set_fe_open)(Chardev *chr, int fe_open); - void (*chr_be_event)(Chardev *s, int event); + void (*chr_be_event)(Chardev *s, QEMUChrEvent event); /* Return 0 if succeeded, 1 if failed */ int (*chr_machine_done)(Chardev *chr); } ChardevClass; diff --git a/backends/cryptodev-vhost-user.c b/backends/cryptodev-vhost-use= r.c index d700934a0e..10e74c0b96 100644 --- a/backends/cryptodev-vhost-user.c +++ b/backends/cryptodev-vhost-user.c @@ -152,7 +152,7 @@ cryptodev_vhost_claim_chardev(CryptoDevBackendVhostUser= *s, return chr; } =20 -static void cryptodev_vhost_user_event(void *opaque, int event) +static void cryptodev_vhost_user_event(void *opaque, QEMUChrEvent event) { CryptoDevBackendVhostUser *s =3D opaque; CryptoDevBackend *b =3D CRYPTODEV_BACKEND(s); diff --git a/chardev/char-mux.c b/chardev/char-mux.c index 200c62a0d0..46c44af67c 100644 --- a/chardev/char-mux.c +++ b/chardev/char-mux.c @@ -117,7 +117,7 @@ static void mux_print_help(Chardev *chr) } } =20 -static void mux_chr_send_event(MuxChardev *d, int mux_nr, int event) +static void mux_chr_send_event(MuxChardev *d, int mux_nr, QEMUChrEvent eve= nt) { CharBackend *be =3D d->backends[mux_nr]; =20 @@ -126,7 +126,7 @@ static void mux_chr_send_event(MuxChardev *d, int mux_n= r, int event) } } =20 -static void mux_chr_be_event(Chardev *chr, int event) +static void mux_chr_be_event(Chardev *chr, QEMUChrEvent event) { MuxChardev *d =3D MUX_CHARDEV(chr); =20 @@ -232,7 +232,7 @@ static void mux_chr_read(void *opaque, const uint8_t *b= uf, int size) } } =20 -void mux_chr_send_all_event(Chardev *chr, int event) +void mux_chr_send_all_event(Chardev *chr, QEMUChrEvent event) { MuxChardev *d =3D MUX_CHARDEV(chr); int i; @@ -247,7 +247,7 @@ void mux_chr_send_all_event(Chardev *chr, int event) } } =20 -static void mux_chr_event(void *opaque, int event) +static void mux_chr_event(void *opaque, QEMUChrEvent event) { mux_chr_send_all_event(CHARDEV(opaque), event); } diff --git a/chardev/char.c b/chardev/char.c index c4b6bbc55a..3b60799813 100644 --- a/chardev/char.c +++ b/chardev/char.c @@ -48,7 +48,7 @@ static Object *get_chardevs_root(void) return container_get(object_get_root(), "/chardevs"); } =20 -static void chr_be_event(Chardev *s, int event) +static void chr_be_event(Chardev *s, QEMUChrEvent event) { CharBackend *be =3D s->be; =20 @@ -59,7 +59,7 @@ static void chr_be_event(Chardev *s, int event) be->chr_event(be->opaque, event); } =20 -void qemu_chr_be_event(Chardev *s, int event) +void qemu_chr_be_event(Chardev *s, QEMUChrEvent event) { /* Keep track if the char device is open */ switch (event) { diff --git a/gdbstub.c b/gdbstub.c index 4cf8af365e..ce304ff482 100644 --- a/gdbstub.c +++ b/gdbstub.c @@ -3171,7 +3171,7 @@ static void gdb_chr_receive(void *opaque, const uint8= _t *buf, int size) } } =20 -static void gdb_chr_event(void *opaque, int event) +static void gdb_chr_event(void *opaque, QEMUChrEvent event) { int i; GDBState *s =3D (GDBState *) opaque; diff --git a/hw/arm/pxa2xx.c b/hw/arm/pxa2xx.c index cdafde2f76..950ff4239a 100644 --- a/hw/arm/pxa2xx.c +++ b/hw/arm/pxa2xx.c @@ -1955,7 +1955,7 @@ static void pxa2xx_fir_rx(void *opaque, const uint8_t= *buf, int size) pxa2xx_fir_update(s); } =20 -static void pxa2xx_fir_event(void *opaque, int event) +static void pxa2xx_fir_event(void *opaque, QEMUChrEvent event) { } =20 diff --git a/hw/arm/strongarm.c b/hw/arm/strongarm.c index 6bee034914..c6776e8479 100644 --- a/hw/arm/strongarm.c +++ b/hw/arm/strongarm.c @@ -1093,7 +1093,7 @@ static void strongarm_uart_receive(void *opaque, cons= t uint8_t *buf, int size) strongarm_uart_update_int_status(s); } =20 -static void strongarm_uart_event(void *opaque, int event) +static void strongarm_uart_event(void *opaque, QEMUChrEvent event) { StrongARMUARTState *s =3D opaque; if (event =3D=3D CHR_EVENT_BREAK) { diff --git a/hw/block/vhost-user-blk.c b/hw/block/vhost-user-blk.c index 4e2b2efdd3..f4e7a53688 100644 --- a/hw/block/vhost-user-blk.c +++ b/hw/block/vhost-user-blk.c @@ -361,7 +361,7 @@ static gboolean vhost_user_blk_watch(GIOChannel *chan, = GIOCondition cond, return true; } =20 -static void vhost_user_blk_event(void *opaque, int event) +static void vhost_user_blk_event(void *opaque, QEMUChrEvent event) { DeviceState *dev =3D opaque; VirtIODevice *vdev =3D VIRTIO_DEVICE(dev); diff --git a/hw/char/cadence_uart.c b/hw/char/cadence_uart.c index 0e315b2376..51791bd217 100644 --- a/hw/char/cadence_uart.c +++ b/hw/char/cadence_uart.c @@ -348,7 +348,7 @@ static void uart_receive(void *opaque, const uint8_t *b= uf, int size) } } =20 -static void uart_event(void *opaque, int event) +static void uart_event(void *opaque, QEMUChrEvent event) { CadenceUARTState *s =3D opaque; uint8_t buf =3D '\0'; diff --git a/hw/char/digic-uart.c b/hw/char/digic-uart.c index 974a2619dd..033eba0a6a 100644 --- a/hw/char/digic-uart.c +++ b/hw/char/digic-uart.c @@ -131,7 +131,7 @@ static void uart_rx(void *opaque, const uint8_t *buf, i= nt size) s->reg_rx =3D *buf; } =20 -static void uart_event(void *opaque, int event) +static void uart_event(void *opaque, QEMUChrEvent event) { } =20 diff --git a/hw/char/escc.c b/hw/char/escc.c index 8f7bf322cb..c40c1d28f1 100644 --- a/hw/char/escc.c +++ b/hw/char/escc.c @@ -634,7 +634,7 @@ static void serial_receive1(void *opaque, const uint8_t= *buf, int size) serial_receive_byte(s, buf[0]); } =20 -static void serial_event(void *opaque, int event) +static void serial_event(void *opaque, QEMUChrEvent event) { ESCCChannelState *s =3D opaque; if (event =3D=3D CHR_EVENT_BREAK) diff --git a/hw/char/etraxfs_ser.c b/hw/char/etraxfs_ser.c index 15ac12ef22..f34f767c60 100644 --- a/hw/char/etraxfs_ser.c +++ b/hw/char/etraxfs_ser.c @@ -202,7 +202,7 @@ static int serial_can_receive(void *opaque) return sizeof(s->rx_fifo) - s->rx_fifo_len; } =20 -static void serial_event(void *opaque, int event) +static void serial_event(void *opaque, QEMUChrEvent event) { =20 } diff --git a/hw/char/exynos4210_uart.c b/hw/char/exynos4210_uart.c index d6b6b62366..7e5c5ce789 100644 --- a/hw/char/exynos4210_uart.c +++ b/hw/char/exynos4210_uart.c @@ -528,7 +528,7 @@ static void exynos4210_uart_receive(void *opaque, const= uint8_t *buf, int size) } =20 =20 -static void exynos4210_uart_event(void *opaque, int event) +static void exynos4210_uart_event(void *opaque, QEMUChrEvent event) { Exynos4210UartState *s =3D (Exynos4210UartState *)opaque; =20 diff --git a/hw/char/grlib_apbuart.c b/hw/char/grlib_apbuart.c index fe3cbf41a3..8e59c3bc6e 100644 --- a/hw/char/grlib_apbuart.c +++ b/hw/char/grlib_apbuart.c @@ -155,7 +155,7 @@ static void grlib_apbuart_receive(void *opaque, const u= int8_t *buf, int size) } } =20 -static void grlib_apbuart_event(void *opaque, int event) +static void grlib_apbuart_event(void *opaque, QEMUChrEvent event) { trace_grlib_apbuart_event(event); } diff --git a/hw/char/imx_serial.c b/hw/char/imx_serial.c index fddde9b43d..d09c210709 100644 --- a/hw/char/imx_serial.c +++ b/hw/char/imx_serial.c @@ -323,7 +323,7 @@ static void imx_receive(void *opaque, const uint8_t *bu= f, int size) imx_put_data(opaque, *buf); } =20 -static void imx_event(void *opaque, int event) +static void imx_event(void *opaque, QEMUChrEvent event) { if (event =3D=3D CHR_EVENT_BREAK) { imx_put_data(opaque, URXD_BRK | URXD_FRMERR | URXD_ERR); diff --git a/hw/char/ipoctal232.c b/hw/char/ipoctal232.c index 66c163ba26..80e9dff701 100644 --- a/hw/char/ipoctal232.c +++ b/hw/char/ipoctal232.c @@ -503,7 +503,7 @@ static void hostdev_receive(void *opaque, const uint8_t= *buf, int size) } } =20 -static void hostdev_event(void *opaque, int event) +static void hostdev_event(void *opaque, QEMUChrEvent event) { SCC2698Channel *ch =3D opaque; switch (event) { diff --git a/hw/char/lm32_juart.c b/hw/char/lm32_juart.c index e0b1bd6555..da9dd5668b 100644 --- a/hw/char/lm32_juart.c +++ b/hw/char/lm32_juart.c @@ -104,7 +104,7 @@ static int juart_can_rx(void *opaque) return !(s->jrx & JRX_FULL); } =20 -static void juart_event(void *opaque, int event) +static void juart_event(void *opaque, QEMUChrEvent event) { } =20 diff --git a/hw/char/lm32_uart.c b/hw/char/lm32_uart.c index 32f29c44cf..8d7a475c91 100644 --- a/hw/char/lm32_uart.c +++ b/hw/char/lm32_uart.c @@ -235,7 +235,7 @@ static int uart_can_rx(void *opaque) return !(s->regs[R_LSR] & LSR_DR); } =20 -static void uart_event(void *opaque, int event) +static void uart_event(void *opaque, QEMUChrEvent event) { } =20 diff --git a/hw/char/mcf_uart.c b/hw/char/mcf_uart.c index 58323baf43..2de3680b5d 100644 --- a/hw/char/mcf_uart.c +++ b/hw/char/mcf_uart.c @@ -256,7 +256,7 @@ static void mcf_uart_push_byte(mcf_uart_state *s, uint8= _t data) mcf_uart_update(s); } =20 -static void mcf_uart_event(void *opaque, int event) +static void mcf_uart_event(void *opaque, QEMUChrEvent event) { mcf_uart_state *s =3D (mcf_uart_state *)opaque; =20 diff --git a/hw/char/milkymist-uart.c b/hw/char/milkymist-uart.c index c358ca07f3..1c7b61480e 100644 --- a/hw/char/milkymist-uart.c +++ b/hw/char/milkymist-uart.c @@ -180,7 +180,7 @@ static int uart_can_rx(void *opaque) return !(s->regs[R_STAT] & STAT_RX_EVT); } =20 -static void uart_event(void *opaque, int event) +static void uart_event(void *opaque, QEMUChrEvent event) { } =20 diff --git a/hw/char/nrf51_uart.c b/hw/char/nrf51_uart.c index 2777afe366..b67fd21089 100644 --- a/hw/char/nrf51_uart.c +++ b/hw/char/nrf51_uart.c @@ -245,7 +245,7 @@ static int uart_can_receive(void *opaque) return s->rx_started ? (UART_FIFO_LENGTH - s->rx_fifo_len) : 0; } =20 -static void uart_event(void *opaque, int event) +static void uart_event(void *opaque, QEMUChrEvent event) { NRF51UARTState *s =3D NRF51_UART(opaque); =20 diff --git a/hw/char/pl011.c b/hw/char/pl011.c index 84ad8ff9fb..23cd544cc5 100644 --- a/hw/char/pl011.c +++ b/hw/char/pl011.c @@ -280,7 +280,7 @@ static void pl011_receive(void *opaque, const uint8_t *= buf, int size) pl011_put_fifo(opaque, *buf); } =20 -static void pl011_event(void *opaque, int event) +static void pl011_event(void *opaque, QEMUChrEvent event) { if (event =3D=3D CHR_EVENT_BREAK) pl011_put_fifo(opaque, 0x400); diff --git a/hw/char/serial.c b/hw/char/serial.c index b4aa250950..992b5ee944 100644 --- a/hw/char/serial.c +++ b/hw/char/serial.c @@ -634,7 +634,7 @@ static void serial_receive1(void *opaque, const uint8_t= *buf, int size) serial_update_irq(s); } =20 -static void serial_event(void *opaque, int event) +static void serial_event(void *opaque, QEMUChrEvent event) { SerialState *s =3D opaque; DPRINTF("event %x\n", event); diff --git a/hw/char/sh_serial.c b/hw/char/sh_serial.c index 07dc16be13..167f4d8cb9 100644 --- a/hw/char/sh_serial.c +++ b/hw/char/sh_serial.c @@ -358,7 +358,7 @@ static void sh_serial_receive1(void *opaque, const uint= 8_t *buf, int size) } } =20 -static void sh_serial_event(void *opaque, int event) +static void sh_serial_event(void *opaque, QEMUChrEvent event) { sh_serial_state *s =3D opaque; if (event =3D=3D CHR_EVENT_BREAK) diff --git a/hw/char/terminal3270.c b/hw/char/terminal3270.c index 9e59a2d92b..4ae9e1cff2 100644 --- a/hw/char/terminal3270.c +++ b/hw/char/terminal3270.c @@ -142,7 +142,7 @@ static void terminal_read(void *opaque, const uint8_t *= buf, int size) } } =20 -static void chr_event(void *opaque, int event) +static void chr_event(void *opaque, QEMUChrEvent event) { Terminal3270 *t =3D opaque; CcwDevice *ccw_dev =3D CCW_DEVICE(t); diff --git a/hw/char/virtio-console.c b/hw/char/virtio-console.c index d3f7ba36fe..35e31a4515 100644 --- a/hw/char/virtio-console.c +++ b/hw/char/virtio-console.c @@ -145,7 +145,7 @@ static void chr_read(void *opaque, const uint8_t *buf, = int size) virtio_serial_write(port, buf, size); } =20 -static void chr_event(void *opaque, int event) +static void chr_event(void *opaque, QEMUChrEvent event) { VirtConsole *vcon =3D opaque; VirtIOSerialPort *port =3D VIRTIO_SERIAL_PORT(vcon); diff --git a/hw/char/xilinx_uartlite.c b/hw/char/xilinx_uartlite.c index 2c47275068..aa6bf02e21 100644 --- a/hw/char/xilinx_uartlite.c +++ b/hw/char/xilinx_uartlite.c @@ -206,7 +206,7 @@ static int uart_can_rx(void *opaque) return s->rx_fifo_len < sizeof(s->rx_fifo); } =20 -static void uart_event(void *opaque, int event) +static void uart_event(void *opaque, QEMUChrEvent event) { =20 } diff --git a/hw/ipmi/ipmi_bmc_extern.c b/hw/ipmi/ipmi_bmc_extern.c index 9d67e6a4a5..4dfb3ae8f5 100644 --- a/hw/ipmi/ipmi_bmc_extern.c +++ b/hw/ipmi/ipmi_bmc_extern.c @@ -379,7 +379,7 @@ static void receive(void *opaque, const uint8_t *buf, i= nt size) handle_hw_op(ibe, hw_op); } =20 -static void chr_event(void *opaque, int event) +static void chr_event(void *opaque, QEMUChrEvent event) { IPMIBmcExtern *ibe =3D opaque; IPMIInterface *s =3D ibe->parent.intf; diff --git a/hw/mips/boston.c b/hw/mips/boston.c index ca7d813a52..29b476b4bd 100644 --- a/hw/mips/boston.c +++ b/hw/mips/boston.c @@ -98,7 +98,7 @@ enum boston_plat_reg { PLAT_SYS_CTL =3D 0x48, }; =20 -static void boston_lcd_event(void *opaque, int event) +static void boston_lcd_event(void *opaque, QEMUChrEvent event) { BostonState *s =3D opaque; if (event =3D=3D CHR_EVENT_OPENED && !s->lcd_inited) { diff --git a/hw/mips/mips_malta.c b/hw/mips/mips_malta.c index 783cd99848..72c03baa8e 100644 --- a/hw/mips/mips_malta.c +++ b/hw/mips/mips_malta.c @@ -545,7 +545,7 @@ static void malta_fpga_reset(void *opaque) snprintf(s->display_text, 9, " "); } =20 -static void malta_fgpa_display_event(void *opaque, int event) +static void malta_fgpa_display_event(void *opaque, QEMUChrEvent event) { MaltaFPGAState *s =3D opaque; =20 diff --git a/hw/riscv/riscv_htif.c b/hw/riscv/riscv_htif.c index 4f7b11dc37..ca87a5cf9f 100644 --- a/hw/riscv/riscv_htif.c +++ b/hw/riscv/riscv_htif.c @@ -96,7 +96,7 @@ static void htif_recv(void *opaque, const uint8_t *buf, i= nt size) * Called by the char dev to supply special events to the HTIF console. * Not used for HTIF. */ -static void htif_event(void *opaque, int event) +static void htif_event(void *opaque, QEMUChrEvent event) { =20 } diff --git a/hw/riscv/sifive_uart.c b/hw/riscv/sifive_uart.c index a403ae90f5..9350482662 100644 --- a/hw/riscv/sifive_uart.c +++ b/hw/riscv/sifive_uart.c @@ -162,7 +162,7 @@ static int uart_can_rx(void *opaque) return s->rx_fifo_len < sizeof(s->rx_fifo); } =20 -static void uart_event(void *opaque, int event) +static void uart_event(void *opaque, QEMUChrEvent event) { } =20 diff --git a/hw/usb/ccid-card-passthru.c b/hw/usb/ccid-card-passthru.c index 190f268da2..cfaddf7f45 100644 --- a/hw/usb/ccid-card-passthru.c +++ b/hw/usb/ccid-card-passthru.c @@ -307,7 +307,7 @@ static void ccid_card_vscard_read(void *opaque, const u= int8_t *buf, int size) } } =20 -static void ccid_card_vscard_event(void *opaque, int event) +static void ccid_card_vscard_event(void *opaque, QEMUChrEvent event) { PassthruState *card =3D opaque; =20 diff --git a/hw/usb/dev-serial.c b/hw/usb/dev-serial.c index 497f932a5a..3504e6505a 100644 --- a/hw/usb/dev-serial.c +++ b/hw/usb/dev-serial.c @@ -461,7 +461,7 @@ static void usb_serial_read(void *opaque, const uint8_t= *buf, int size) s->recv_used +=3D size; } =20 -static void usb_serial_event(void *opaque, int event) +static void usb_serial_event(void *opaque, QEMUChrEvent event) { USBSerialState *s =3D opaque; =20 diff --git a/hw/usb/redirect.c b/hw/usb/redirect.c index acc376cc95..d5f85851b9 100644 --- a/hw/usb/redirect.c +++ b/hw/usb/redirect.c @@ -1354,7 +1354,7 @@ static void usbredir_chardev_read(void *opaque, const= uint8_t *buf, int size) usbredirparser_do_write(dev->parser); } =20 -static void usbredir_chardev_event(void *opaque, int event) +static void usbredir_chardev_event(void *opaque, QEMUChrEvent event) { USBRedirDevice *dev =3D opaque; =20 diff --git a/monitor/hmp.c b/monitor/hmp.c index d84238c120..ad9a599a88 100644 --- a/monitor/hmp.c +++ b/monitor/hmp.c @@ -1322,7 +1322,7 @@ static void monitor_read(void *opaque, const uint8_t = *buf, int size) cur_mon =3D old_mon; } =20 -static void monitor_event(void *opaque, int event) +static void monitor_event(void *opaque, QEMUChrEvent event) { Monitor *mon =3D opaque; MonitorHMP *hmp_mon =3D container_of(mon, MonitorHMP, common); diff --git a/monitor/qmp.c b/monitor/qmp.c index d666b07e68..1c7cbbfff0 100644 --- a/monitor/qmp.c +++ b/monitor/qmp.c @@ -337,7 +337,7 @@ static QDict *qmp_greeting(MonitorQMP *mon) ver, cap_list); } =20 -static void monitor_qmp_event(void *opaque, int event) +static void monitor_qmp_event(void *opaque, QEMUChrEvent event) { QDict *data; MonitorQMP *mon =3D opaque; diff --git a/net/filter-mirror.c b/net/filter-mirror.c index 8d36009c53..d83e815545 100644 --- a/net/filter-mirror.c +++ b/net/filter-mirror.c @@ -132,7 +132,7 @@ static void redirector_chr_read(void *opaque, const uin= t8_t *buf, int size) } } =20 -static void redirector_chr_event(void *opaque, int event) +static void redirector_chr_event(void *opaque, QEMUChrEvent event) { NetFilterState *nf =3D opaque; MirrorState *s =3D FILTER_REDIRECTOR(nf); diff --git a/net/vhost-user.c b/net/vhost-user.c index 383d68024e..051e1dbd6e 100644 --- a/net/vhost-user.c +++ b/net/vhost-user.c @@ -218,7 +218,7 @@ static gboolean net_vhost_user_watch(GIOChannel *chan, = GIOCondition cond, return TRUE; } =20 -static void net_vhost_user_event(void *opaque, int event); +static void net_vhost_user_event(void *opaque, QEMUChrEvent event); =20 static void chr_closed_bh(void *opaque) { @@ -249,7 +249,7 @@ static void chr_closed_bh(void *opaque) } } =20 -static void net_vhost_user_event(void *opaque, int event) +static void net_vhost_user_event(void *opaque, QEMUChrEvent event) { const char *name =3D opaque; NetClientState *ncs[MAX_QUEUE_NUM]; diff --git a/qtest.c b/qtest.c index 8b50e2783e..12432f99cf 100644 --- a/qtest.c +++ b/qtest.c @@ -722,7 +722,7 @@ static int qtest_can_read(void *opaque) return 1024; } =20 -static void qtest_event(void *opaque, int event) +static void qtest_event(void *opaque, QEMUChrEvent event) { int i; =20 diff --git a/tests/test-char.c b/tests/test-char.c index 45e42af290..3afc9b1b8d 100644 --- a/tests/test-char.c +++ b/tests/test-char.c @@ -54,7 +54,7 @@ static void fe_read(void *opaque, const uint8_t *buf, int= size) quit =3D true; } =20 -static void fe_event(void *opaque, int event) +static void fe_event(void *opaque, QEMUChrEvent event) { FeHandler *h =3D opaque; bool new_open_state; @@ -633,7 +633,7 @@ typedef struct { =20 =20 static void -char_socket_event(void *opaque, int event) +char_socket_event(void *opaque, QEMUChrEvent event) { CharSocketTestData *data =3D opaque; data->event =3D event; @@ -1006,7 +1006,7 @@ static void char_socket_client_test(gconstpointer opa= que) } =20 static void -count_closed_event(void *opaque, int event) +count_closed_event(void *opaque, QEMUChrEvent event) { int *count =3D opaque; if (event =3D=3D CHR_EVENT_CLOSED) { diff --git a/tests/vhost-user-test.c b/tests/vhost-user-test.c index 91ea373ba5..2324b964ad 100644 --- a/tests/vhost-user-test.c +++ b/tests/vhost-user-test.c @@ -499,7 +499,7 @@ static TestServer *test_server_new(const gchar *name) return server; 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[83.42.66.34]) by smtp.gmail.com with ESMTPSA id s1sm3636122wmc.23.2019.12.17.08.50.37 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 17 Dec 2019 08:50:39 -0800 (PST) Subject: Re: [PATCH 00/14] chardev: Use QEMUChrEvent enum in IOEventHandler typedef To: Paolo Bonzini , =?UTF-8?Q?Marc-Andr=c3=a9_Lureau?= , qemu-devel@nongnu.org, Stefan Hajnoczi Cc: Cornelia Huck , Zhang Chen , "Michael S. Tsirkin" , Fabien Chouteau , Paul Burton , Peter Maydell , KONRAD Frederic , Aurelien Jarno , Jason Wang , qemu-block@nongnu.org, Corey Minyard , Max Reitz , Li Zhijian , Gerd Hoffmann , Michael Walle , Markus Armbruster , Laurent Vivier , Igor Mitsyanko , Joel Stanley , =?UTF-8?Q?Alex_Benn=c3=a9e?= , Bastian Koppelmann , Alberto Garcia , Peter Chubb , "Edgar E. Iglesias" , "Dr. David Alan Gilbert" , Christian Borntraeger , Andrzej Zaborowski , Aleksandar Rikalo , Aleksandar Markovic , Sagar Karandikar , Antony Pavlov , qemu-arm@nongnu.org, Alistair Francis , Kevin Wolf , qemu-s390x@nongnu.org, "Gonglei (Arei)" , Palmer Dabbelt , Samuel Thibault , Amit Shah , qemu-riscv@nongnu.org, Halil Pasic , Thomas Huth References: <20191217163808.20068-1-philmd@redhat.com> From: =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= Message-ID: <154a68ee-c683-d5c5-dad8-df483aa00c20@redhat.com> Date: Tue, 17 Dec 2019 17:50:37 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.2.2 MIME-Version: 1.0 In-Reply-To: <20191217163808.20068-1-philmd@redhat.com> Content-Language: en-US X-MC-Unique: AQkEv2F6PiWJCBFPjD9vAg-1 X-Mimecast-Spam-Score: 0 Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 205.139.110.120 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 17 Dec 2019 16:50:52 -0000 On 12/17/19 5:37 PM, Philippe Mathieu-Daud=C3=A9 wrote: > Hi, >=20 > After this chat on #qemu IRC: > 13:20 so what is the difference between a IOReadHandler and IOE= ventHandler? > 13:25 stsquad: one is in-band and the other out-of-band? > 13:26 f4bug: ahh yes it seems so - connect/disconnect etc... > 13:27 see QEMUChrEvent for IOEventHandler >=20 > I thought it might be a good opportunity to make the IOEventHandler > typedef meaning more obvious, by using the QEMUChrEvent enum. >=20 > To be able to build I had to explicit a 'default' case when frontends > use a switch(event) case and do not handle all events. >=20 > Then I used a coccinelle spatch to change the various IOEventHandler. > I don't think the last patch can be split, but suggestions are welcome! >=20 > Regards, >=20 > Phil. >=20 > PD: I use git-publish. To avoid spamming too much, I'm using per-patch > Cc tag, after the '---' separator. This way each recipient should get > the cover and the specific patches of interests, + the last one. >=20 > Sent with: 'git publish --suppress-cc=3Dcccmd' While 'git-publish --verbose' show it was adding recipient from the tags: (mbox) Adding cc: ... (mbox) Adding cc: ... It still sent each patch to everybody from the cover: Server: MAIL FROM: RCPT TO: ... RCPT TO: ... Maybe the list was cached in the tag and I should have use the=20 --override-cc flag too: --override-cc Ignore any profile or saved CC emails I apologize for the no-relevant patches I spammed you with :( > Cc: "Gonglei (Arei)" > Cc: "Marc-Andr=C3=A9 Lureau" > Cc: Paolo Bonzini > Cc: "Alex Benn=C3=A9e" > Cc: "Philippe Mathieu-Daud=C3=A9" > Cc: Andrzej Zaborowski > Cc: Peter Maydell > Cc: "Michael S. Tsirkin" > Cc: Kevin Wolf > Cc: Max Reitz > Cc: "Edgar E. Iglesias" > Cc: Alistair Francis > Cc: Antony Pavlov > Cc: Igor Mitsyanko > Cc: Fabien Chouteau > Cc: KONRAD Frederic > Cc: Peter Chubb > Cc: Alberto Garcia > Cc: Michael Walle > Cc: Thomas Huth > Cc: Joel Stanley > Cc: Cornelia Huck > Cc: Halil Pasic > Cc: Christian Borntraeger > Cc: Laurent Vivier > Cc: Amit Shah > Cc: Corey Minyard > Cc: Paul Burton > Cc: Aleksandar Rikalo > Cc: Aurelien Jarno > Cc: Aleksandar Markovic > Cc: Palmer Dabbelt > Cc: Sagar Karandikar > Cc: Bastian Koppelmann > Cc: Gerd Hoffmann > Cc: Samuel Thibault > Cc: "Dr. David Alan Gilbert" > Cc: Markus Armbruster > Cc: Zhang Chen > Cc: Li Zhijian > Cc: Jason Wang > Cc: qemu-arm@nongnu.org > Cc: qemu-block@nongnu.org > Cc: qemu-s390x@nongnu.org > Cc: qemu-riscv@nongnu.org From MAILER-DAEMON Tue Dec 17 12:33:28 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1ihGiu-0000AK-OA for mharc-qemu-arm@gnu.org; Tue, 17 Dec 2019 12:33:28 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:45018) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ihGir-000082-4S for qemu-arm@nongnu.org; Tue, 17 Dec 2019 12:33:26 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ihGio-0005bu-JC for qemu-arm@nongnu.org; Tue, 17 Dec 2019 12:33:23 -0500 Received: from us-smtp-delivery-1.mimecast.com ([207.211.31.120]:45824 helo=us-smtp-1.mimecast.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1ihGio-0005Zy-9l for qemu-arm@nongnu.org; Tue, 17 Dec 2019 12:33:22 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1576604001; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding; bh=nO8L9Ff0gTs0Ghul9qOGY/vgywrMy48c7WRyGNxm0bk=; b=hILAafoJCE8SllL86u9H9CT0hSHE8hortfnFc4H98w3KwitSNwp8y/oLPy3kX6V/hmQswl CqRYJBk1VTZ4cZCkwQFzaSFeQRf6xgLvn9cf8kMpN7UosocePK9aH7eyxr7/J4wSqwQAsX kFpUmNn38Wgeh2+sTdN+mvbyrE6jzzc= Received: from mimecast-mx01.redhat.com (mimecast-mx01.redhat.com [209.132.183.4]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-169-UBfwbRvfMCW-lwDPShNRGA-1; Tue, 17 Dec 2019 12:33:18 -0500 Received: from smtp.corp.redhat.com (int-mx03.intmail.prod.int.phx2.redhat.com [10.5.11.13]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx01.redhat.com (Postfix) with ESMTPS id 38484189CD14; Tue, 17 Dec 2019 17:33:16 +0000 (UTC) Received: from x1w.redhat.com (ovpn-205-147.brq.redhat.com [10.40.205.147]) by smtp.corp.redhat.com (Postfix) with ESMTPS id 90A977C82C; Tue, 17 Dec 2019 17:33:02 +0000 (UTC) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: qemu-trivial@nongnu.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Max Reitz , Fam Zheng , Peter Chubb , qemu-arm@nongnu.org, Joel Stanley , Peter Maydell , Mark Cave-Ayland , Paolo Bonzini , Kevin Wolf , Jason Wang , qemu-block@nongnu.org, Andrew Jeffery , Gerd Hoffmann , Hannes Reinecke Subject: [PATCH 0/6] Fix more GCC9 -O3 warnings Date: Tue, 17 Dec 2019 18:32:46 +0100 Message-Id: <20191217173252.4672-1-philmd@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.79 on 10.5.11.13 X-MC-Unique: UBfwbRvfMCW-lwDPShNRGA-1 X-Mimecast-Spam-Score: 0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 207.211.31.120 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 17 Dec 2019 17:33:26 -0000 Fix some trivial warnings when building with -O3. Philippe Mathieu-Daud=C3=A9 (6): audio/audio: Add missing fall through comment hw/display/tcx: Add missing fall through comments hw/net/imx_fec: Rewrite fall through comments hw/timer/aspeed_timer: Add a fall through comment hw/scsi/megasas: Silent GCC9 duplicated-cond warning qemu-io-cmds: Silent GCC9 format-overflow warning audio/audio.c | 1 + hw/display/tcx.c | 2 ++ hw/net/imx_fec.c | 8 +++++--- hw/scsi/megasas.c | 3 ++- hw/timer/aspeed_timer.c | 2 +- qemu-io-cmds.c | 1 + 6 files changed, 12 insertions(+), 5 deletions(-) --=20 2.21.0 From MAILER-DAEMON Tue Dec 17 12:34:54 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1ihGkI-0001U9-6r for mharc-qemu-arm@gnu.org; Tue, 17 Dec 2019 12:34:54 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:45981) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ihGkF-0001Sd-HJ for qemu-arm@nongnu.org; Tue, 17 Dec 2019 12:34:52 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ihGkE-000822-KS for qemu-arm@nongnu.org; Tue, 17 Dec 2019 12:34:51 -0500 Received: from us-smtp-delivery-1.mimecast.com ([205.139.110.120]:22026 helo=us-smtp-1.mimecast.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1ihGkE-00080j-Gd for qemu-arm@nongnu.org; Tue, 17 Dec 2019 12:34:50 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1576604089; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding; bh=nO8L9Ff0gTs0Ghul9qOGY/vgywrMy48c7WRyGNxm0bk=; b=EOhYqfoxAYGrhWZIvpRW5Shdf8tIoiM5hT15Uz+IkVkBhGH168zm9s6XuxGoUCg4gerSiR ckYyJGOGs+ykh2rKOTEzOOqZxygV3vpKShNzlDE0tNQoRZjvo2Qp/y7YP0h1u9lB3lAoag C5LfyaczIMV+OTT0sNRj3lrIQUmH0q8= Received: from mimecast-mx01.redhat.com (mimecast-mx01.redhat.com [209.132.183.4]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-56-DndLY13tOwGjhVK3iHR_uQ-1; Tue, 17 Dec 2019 12:34:48 -0500 Received: from smtp.corp.redhat.com (int-mx08.intmail.prod.int.phx2.redhat.com [10.5.11.23]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx01.redhat.com (Postfix) with ESMTPS id 54908100551A; Tue, 17 Dec 2019 17:34:46 +0000 (UTC) Received: from x1w.redhat.com (ovpn-205-147.brq.redhat.com [10.40.205.147]) by smtp.corp.redhat.com (Postfix) with ESMTPS id 8B89226DC6; Tue, 17 Dec 2019 17:34:31 +0000 (UTC) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: qemu-trivial@nongnu.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Max Reitz , Fam Zheng , Peter Chubb , qemu-arm@nongnu.org, Joel Stanley , Peter Maydell , Mark Cave-Ayland , Paolo Bonzini , Kevin Wolf , Jason Wang , qemu-block@nongnu.org, Andrew Jeffery , Gerd Hoffmann , Hannes Reinecke , =?UTF-8?q?K=C5=91v=C3=A1g=C3=B3=2C=20Zolt=C3=A1n?= Subject: [PATCH 0/6] Fix more GCC9 -O3 warnings Date: Tue, 17 Dec 2019 18:34:19 +0100 Message-Id: <20191217173425.5082-1-philmd@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.84 on 10.5.11.23 X-MC-Unique: DndLY13tOwGjhVK3iHR_uQ-1 X-Mimecast-Spam-Score: 0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 205.139.110.120 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 17 Dec 2019 17:34:52 -0000 Fix some trivial warnings when building with -O3. Philippe Mathieu-Daud=C3=A9 (6): audio/audio: Add missing fall through comment hw/display/tcx: Add missing fall through comments hw/net/imx_fec: Rewrite fall through comments hw/timer/aspeed_timer: Add a fall through comment hw/scsi/megasas: Silent GCC9 duplicated-cond warning qemu-io-cmds: Silent GCC9 format-overflow warning audio/audio.c | 1 + hw/display/tcx.c | 2 ++ hw/net/imx_fec.c | 8 +++++--- hw/scsi/megasas.c | 3 ++- hw/timer/aspeed_timer.c | 2 +- qemu-io-cmds.c | 1 + 6 files changed, 12 insertions(+), 5 deletions(-) --=20 2.21.0 From MAILER-DAEMON Tue Dec 17 12:35:09 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1ihGkW-0001uM-VB for mharc-qemu-arm@gnu.org; Tue, 17 Dec 2019 12:35:08 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:46238) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ihGkT-0001oK-3m for qemu-arm@nongnu.org; Tue, 17 Dec 2019 12:35:06 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ihGkR-00009b-Vf for qemu-arm@nongnu.org; Tue, 17 Dec 2019 12:35:04 -0500 Received: from us-smtp-delivery-1.mimecast.com ([207.211.31.120]:48875 helo=us-smtp-1.mimecast.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1ihGkR-000090-SL for qemu-arm@nongnu.org; Tue, 17 Dec 2019 12:35:03 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1576604103; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=JerXtiZg/NdV0y3V9bJw7XC5WMrWi8gnxmPCM/s6nsY=; b=Xz7V6hYQAKWAaICBYEXW/vJfU4bVXDjtJ9PCOmi7rB3ypcXNDd1U80vcFZFI4Zz2dnKAP0 ILftMqHCsFYlV0EsE6v/HzUnGNRhDm96m14eTCNH/UDNC9Ybqp51tBDxq9tMNFfYNKfFmF 7Z42KuzqPxIGIuT3sIaX9ONC/8P2vqE= Received: from mimecast-mx01.redhat.com (mimecast-mx01.redhat.com [209.132.183.4]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-249-uWLPNUfoMs6bVftKDHCoMw-1; Tue, 17 Dec 2019 12:35:00 -0500 Received: from smtp.corp.redhat.com (int-mx08.intmail.prod.int.phx2.redhat.com [10.5.11.23]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx01.redhat.com (Postfix) with ESMTPS id D9DAA18C35C0; Tue, 17 Dec 2019 17:34:58 +0000 (UTC) Received: from x1w.redhat.com (ovpn-205-147.brq.redhat.com [10.40.205.147]) by smtp.corp.redhat.com (Postfix) with ESMTPS id 7616D19C4F; Tue, 17 Dec 2019 17:34:53 +0000 (UTC) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: qemu-trivial@nongnu.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Peter Chubb , Peter Maydell , Jason Wang , qemu-arm@nongnu.org Subject: [PATCH 3/6] hw/net/imx_fec: Rewrite fall through comments Date: Tue, 17 Dec 2019 18:34:22 +0100 Message-Id: <20191217173425.5082-4-philmd@redhat.com> In-Reply-To: <20191217173425.5082-1-philmd@redhat.com> References: <20191217173425.5082-1-philmd@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.84 on 10.5.11.23 X-MC-Unique: uWLPNUfoMs6bVftKDHCoMw-1 X-Mimecast-Spam-Score: 0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 207.211.31.120 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 17 Dec 2019 17:35:07 -0000 GCC9 is confused by this comment when building with CFLAG -Wimplicit-fallthrough=3D2: hw/net/imx_fec.c: In function =E2=80=98imx_eth_write=E2=80=99: hw/net/imx_fec.c:906:12: error: this statement may fall through [-Werror= =3Dimplicit-fallthrough=3D] 906 | if (unlikely(single_tx_ring)) { | ^ hw/net/imx_fec.c:912:5: note: here 912 | case ENET_TDAR: /* FALLTHROUGH */ | ^~~~ cc1: all warnings being treated as errors Rewrite the comments in the correct place, using 'fall through' which is recognized by GCC and static analyzers. Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- Cc: Peter Chubb Cc: Peter Maydell Cc: Jason Wang Cc: qemu-arm@nongnu.org --- hw/net/imx_fec.c | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/hw/net/imx_fec.c b/hw/net/imx_fec.c index bd99236864..30cc07753d 100644 --- a/hw/net/imx_fec.c +++ b/hw/net/imx_fec.c @@ -901,15 +901,17 @@ static void imx_eth_write(void *opaque, hwaddr offset= , uint64_t value, s->regs[index] =3D 0; } break; - case ENET_TDAR1: /* FALLTHROUGH */ - case ENET_TDAR2: /* FALLTHROUGH */ + /* fall through */ + case ENET_TDAR1: + case ENET_TDAR2: if (unlikely(single_tx_ring)) { qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: trying to access TDAR2 or TDAR1\n", TYPE_IMX_FEC, __func__); return; } - case ENET_TDAR: /* FALLTHROUGH */ + /* fall through */ + case ENET_TDAR: if (s->regs[ENET_ECR] & ENET_ECR_ETHEREN) { s->regs[index] =3D ENET_TDAR_TDAR; imx_eth_do_tx(s, index); --=20 2.21.0 From MAILER-DAEMON Tue Dec 17 12:35:13 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1ihGkb-000213-2k for mharc-qemu-arm@gnu.org; Tue, 17 Dec 2019 12:35:13 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:46320) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ihGkX-0001vK-F7 for qemu-arm@nongnu.org; Tue, 17 Dec 2019 12:35:10 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ihGkW-0000Ne-Ad for qemu-arm@nongnu.org; Tue, 17 Dec 2019 12:35:09 -0500 Received: from us-smtp-1.mimecast.com ([207.211.31.81]:53555 helo=us-smtp-delivery-1.mimecast.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1ihGkW-0000MH-76 for qemu-arm@nongnu.org; Tue, 17 Dec 2019 12:35:08 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1576604107; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=HM0BAidIfenT9MqU4w2ULCCF6forF8fZZ3ED/PgaTLg=; b=HKuB69O5j1hvhslsC7mhmX8Ai9v2sUGbH1S1ViCLDv1Jab4hFGyQ6+9D1ILJ4RTt4iLtUI fP1D1paUsTEcK7Sh1conbD1MYcRR7+tc5IafB7FvYe3sKh6UHAR0AYIAdUFnRBCCS+40Bf pdASUo0e21jjjwV7oeDQCMWUdSPcZyw= Received: from mimecast-mx01.redhat.com (mimecast-mx01.redhat.com [209.132.183.4]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-209-o2RGE3-LP9WZo3T31gvbNw-1; Tue, 17 Dec 2019 12:35:04 -0500 Received: from smtp.corp.redhat.com (int-mx08.intmail.prod.int.phx2.redhat.com [10.5.11.23]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx01.redhat.com (Postfix) with ESMTPS id 845A7100728C; Tue, 17 Dec 2019 17:35:02 +0000 (UTC) Received: from x1w.redhat.com (ovpn-205-147.brq.redhat.com [10.40.205.147]) by smtp.corp.redhat.com (Postfix) with ESMTPS id 8095E26571; Tue, 17 Dec 2019 17:34:59 +0000 (UTC) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: qemu-trivial@nongnu.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Peter Maydell , Andrew Jeffery , Joel Stanley , qemu-arm@nongnu.org Subject: [PATCH 4/6] hw/timer/aspeed_timer: Add a fall through comment Date: Tue, 17 Dec 2019 18:34:23 +0100 Message-Id: <20191217173425.5082-5-philmd@redhat.com> In-Reply-To: <20191217173425.5082-1-philmd@redhat.com> References: <20191217173425.5082-1-philmd@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.84 on 10.5.11.23 X-MC-Unique: o2RGE3-LP9WZo3T31gvbNw-1 X-Mimecast-Spam-Score: 0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 207.211.31.81 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 17 Dec 2019 17:35:10 -0000 Reported by GCC9 when building with CFLAG -Wimplicit-fallthrough=3D2: hw/timer/aspeed_timer.c: In function =E2=80=98aspeed_timer_set_value=E2= =80=99: hw/timer/aspeed_timer.c:283:24: error: this statement may fall through [-= Werror=3Dimplicit-fallthrough=3D] 283 | if (old_reload || !t->reload) { | ~~~~~~~~~~~^~~~~~~~~~~~~ hw/timer/aspeed_timer.c:287:5: note: here 287 | case TIMER_REG_STATUS: | ^~~~ cc1: all warnings being treated as errors Add the missing fall through comment. Fixes: 1403f364472 Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- Cc: "C=C3=A9dric Le Goater" Cc: Peter Maydell Cc: Andrew Jeffery Cc: Joel Stanley Cc: qemu-arm@nongnu.org --- hw/timer/aspeed_timer.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/timer/aspeed_timer.c b/hw/timer/aspeed_timer.c index a8c38cc118..c91f18415c 100644 --- a/hw/timer/aspeed_timer.c +++ b/hw/timer/aspeed_timer.c @@ -283,7 +283,7 @@ static void aspeed_timer_set_value(AspeedTimerCtrlState= *s, int timer, int reg, if (old_reload || !t->reload) { break; } - + /* fall through to re-enable */ case TIMER_REG_STATUS: if (timer_enabled(t)) { uint64_t now =3D qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); --=20 2.21.0 From MAILER-DAEMON Tue Dec 17 12:39:22 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1ihGoc-0000pN-5m for mharc-qemu-arm@gnu.org; Tue, 17 Dec 2019 12:39:22 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:49291) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ihGoW-0000gs-8B for qemu-arm@nongnu.org; Tue, 17 Dec 2019 12:39:17 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ihGoV-0007k6-1L for qemu-arm@nongnu.org; Tue, 17 Dec 2019 12:39:15 -0500 Received: from mail-oi1-x243.google.com ([2607:f8b0:4864:20::243]:32978) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ihGoU-0007gu-Lt for qemu-arm@nongnu.org; Tue, 17 Dec 2019 12:39:14 -0500 Received: by mail-oi1-x243.google.com with SMTP id v140so6055321oie.0 for ; Tue, 17 Dec 2019 09:39:14 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=r6nMlH6NQ/zXzXEPNeLi6nAjmBQajsuEkVBCjNWQcD0=; b=gubyXtSh0zHIgd1Re0/fWLr0b0mA3drEhj/W9zkdeQOx/PRivitrxOyU2vII8ACCiW RLJX90qNIllHkvM9VELh/n9gw0TCy1HRFZ0b1HJSYrXnRSK15qsDqy513O9sE3MTUTzO DGsm+cfW24w5bdDwRU/RnV7hyTr0HzcK70vFSTzokUUT2zevhXAYWhVFFQul9Pbd84uf iFB1i8ksaAcm4190NS/AhLRrRO/KF+dBELhlLNH1Pgm17ihdIMmAh7zec7J4+p9m7SU8 AO2pyInuDPggJEWqw83Wv+1NLM6WBYwortx8/EQc2BgbhCpeKrxBhXQ0/QYUtdWiGA6f c7cQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=r6nMlH6NQ/zXzXEPNeLi6nAjmBQajsuEkVBCjNWQcD0=; b=Z4Y9XbAFml/z4ac1+NeSrCB9iicmqeKVppP3jIoaJcenBhQE4+5ebruWe3hoo8cVpe ivH6IpIqJceixfz8pmQ7WnrmGfHPhUHeCfCIPH6S3b8izBlywWhYX42mmFmgc/PMQ8AA H7m1jLPPKMTJA9aY2XD8kM7ioqzWvocFRjcRr5NHmIXnjaCIFLMAop7GblIoaz9ZYi3f sHb1uQFngc52xlNGsdccZWkbTBwuZiQ3EnqNA2wH0NsDuKWVN31hlOSWVxCDb+/z0Kxx OeVIvMTYdZlYWx3BVJoi06Rqga+uCy9j+0Hu5Jy2WRdvR60/PYjMMKGu9/hEeExAI8QL lbSQ== X-Gm-Message-State: APjAAAXxMdrStQdKVEeEKI3wwjkwr9u+5qebdvIc/n2+nEHMdlB8G1zn swMBe7tvDxnoSKL5GSY9wK3a85YKeWyL1oZzkr/0Yg== X-Google-Smtp-Source: APXvYqzL8ssQdFbcn8W7G6YxFMKH2/1Rfsh8FGWBvv+exO3TO894Sz604o0/OIpKK8ZdlRRwXNdN/ty70Ne+IhJU7/4= X-Received: by 2002:a05:6808:996:: with SMTP id a22mr2135701oic.146.1576604353813; Tue, 17 Dec 2019 09:39:13 -0800 (PST) MIME-Version: 1.0 References: <20191216233519.29030-1-nieklinnenbank@gmail.com> <20191216233519.29030-7-nieklinnenbank@gmail.com> <19e4f2ac-6067-f61f-f340-108545fb0f02@linaro.org> In-Reply-To: <19e4f2ac-6067-f61f-f340-108545fb0f02@linaro.org> From: Peter Maydell Date: Tue, 17 Dec 2019 17:39:02 +0000 Message-ID: Subject: Re: [PATCH v2 06/10] arm/arm-powerctl: rebuild hflags after setting CP15 bits in arm_set_cpu_on() To: Richard Henderson Cc: Niek Linnenbank , qemu-arm , =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= , QEMU Developers Content-Type: text/plain; charset="UTF-8" X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::243 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 17 Dec 2019 17:39:17 -0000 On Tue, 17 Dec 2019 at 16:41, Richard Henderson wrote: > > On 12/17/19 6:12 AM, Peter Maydell wrote: > > Cc'ing Richard : this is one for you I think... (surely we > > need to rebuild the hflags from scratch when we power up > > a CPU anyway?) > > We do compute hflags from scratch in reset. > > It has also turned out that there were a few board models that poked at the > contents of the cpu and needed special help. Some of that I would imagine > would be fixed properly with the multi-phase reset patches, where we could > rebuild hflags when *leaving* reset. > > In arm_set_cpu_on_async_work, we start by resetting the cpu and then start > poking at the contents of some system registers. So, yes, we do need to > rebuild after doing that. Also, I'm not sure how this function should fit into > the multi-phase reset future. > > So: > > Reviewed-by: Richard Henderson Thanks; I've applied this patch to target-arm.next. -- PMM From MAILER-DAEMON Tue Dec 17 12:39:59 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1ihGpD-0001rM-6G for mharc-qemu-arm@gnu.org; Tue, 17 Dec 2019 12:39:59 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:49932) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ihGpA-0001nT-Sw for qemu-arm@nongnu.org; Tue, 17 Dec 2019 12:39:57 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ihGp9-0000w0-Nw for qemu-arm@nongnu.org; Tue, 17 Dec 2019 12:39:56 -0500 Received: from us-smtp-delivery-1.mimecast.com ([207.211.31.120]:37892 helo=us-smtp-1.mimecast.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1ihGp9-0000uE-Kq for qemu-arm@nongnu.org; Tue, 17 Dec 2019 12:39:55 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1576604395; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=otHh6o7oxDp9j6yghQWHjKyedFvOrFKCAiJYw7JbOso=; b=Oa4el7hgorSjs4LQAij3xLR9HJMV28e4dAt7bzVWEeLCROMJLXpXYA17q7nocuSY+Nw9he EfwW0z9yeeNg+/0LSTdF1Iax5ydqg3rv94bfHRovb1A/vRk05ahXwK5YoBCpetGyVKbVRO FgYfDeajgSE9KoDFfJj5FSUlagdyiFc= Received: from mail-wm1-f71.google.com (mail-wm1-f71.google.com [209.85.128.71]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-415-S95hVrELPPG_9zVvc3ou5w-1; Tue, 17 Dec 2019 12:39:52 -0500 Received: by mail-wm1-f71.google.com with SMTP id y125so1005783wmg.1 for ; Tue, 17 Dec 2019 09:39:51 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:subject:to:cc:references:from:message-id:date :user-agent:mime-version:in-reply-to:content-language :content-transfer-encoding; bh=bAAJWyVVZ1IKai9f9il7x2Z+RsApLRgS+QHt3wBYLSA=; b=igHjmBG+JTQYvBdZHd9mbTO/ftqGufTyOlyCPpQVPDFCBCc9LK1zJp1TkwF+01opyc 8dYF94Hh4qg9POLWZHZpM1g9jSfQvLJZsNGhTr9HzgjSSeOrM5pJC4uESlYLqsIUtekC p+iLByVAxZJoXrror5i8eeks9Es6oYoxw/gqC6VtG0dKzMAueyDQAnFxDigc9BPYqZ+E InHp6EGBQ0M0j7YTLEEWlUmQ+PHFxJHCm1wllLSX7sMbxTCewg8XfQZfkUQqdo+P4Y4o 1egm3Z9tSuVq+lljW52vwvYvnj3qwCZ2KnL2zSp2hgMkq8R1KMVstNEZgOvuzoY4HwQW jYmA== X-Gm-Message-State: APjAAAVpn/wa3dO0rdqbRmJJmWtmj9JCxdseVcQxkIx778fQ3FWgv9Am 70mAB7IMQ7iP+jna6iMS2pFELCVeO+a8yDeTjUPElICKSbX8rEdLedKOPbQlz3KfmQ4Vy2YSoE8 pmA6v9LOZhaQl X-Received: by 2002:a5d:6a0f:: with SMTP id m15mr38388336wru.40.1576604390831; Tue, 17 Dec 2019 09:39:50 -0800 (PST) X-Google-Smtp-Source: APXvYqzFBpSiHMJZuiUp5KC+DdlpgXyZDlJKyko8FRSj5XpUtFN/99wAgHNrx1ZQ4OV5F9Cdqp7BRQ== X-Received: by 2002:a5d:6a0f:: with SMTP id m15mr38388290wru.40.1576604390534; Tue, 17 Dec 2019 09:39:50 -0800 (PST) Received: from [192.168.1.35] (34.red-83-42-66.dynamicip.rima-tde.net. [83.42.66.34]) by smtp.gmail.com with ESMTPSA id h17sm27417449wrs.18.2019.12.17.09.39.49 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 17 Dec 2019 09:39:50 -0800 (PST) Subject: Re: [PATCH 0/6] Fix more GCC9 -O3 warnings To: qemu-devel@nongnu.org Cc: qemu-trivial@nongnu.org, =?UTF-8?Q?C=c3=a9dric_Le_Goater?= , Max Reitz , Fam Zheng , Peter Chubb , qemu-arm@nongnu.org, Joel Stanley , Peter Maydell , Mark Cave-Ayland , Paolo Bonzini , Kevin Wolf , Jason Wang , qemu-block@nongnu.org, Andrew Jeffery , Gerd Hoffmann , Hannes Reinecke , =?UTF-8?B?S8WRdsOhZ8OzLCBab2x0w6Fu?= References: <20191217173252.4672-1-philmd@redhat.com> From: =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= Message-ID: <6a8266c6-7c6d-3139-249f-2dd46c98e02f@redhat.com> Date: Tue, 17 Dec 2019 18:39:48 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.2.2 MIME-Version: 1.0 In-Reply-To: <20191217173252.4672-1-philmd@redhat.com> Content-Language: en-US X-MC-Unique: S95hVrELPPG_9zVvc3ou5w-1 X-Mimecast-Spam-Score: 0 Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 207.211.31.120 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 17 Dec 2019 17:39:58 -0000 On 12/17/19 6:32 PM, Philippe Mathieu-Daud=C3=A9 wrote: > Fix some trivial warnings when building with -O3. >=20 > Philippe Mathieu-Daud=C3=A9 (6): > audio/audio: Add missing fall through comment > hw/display/tcx: Add missing fall through comments > hw/net/imx_fec: Rewrite fall through comments > hw/timer/aspeed_timer: Add a fall through comment > hw/scsi/megasas: Silent GCC9 duplicated-cond warning > qemu-io-cmds: Silent GCC9 format-overflow warning Sorry, this series failed because I used this tag in the first patch: Cc: K=C5=91v=C3=A1g=C3=B3, Zolt=C3=A1n Then git-send-email was happy with --dry-run, but then failed: (body) Adding cc: K=C5=91v=C3=A1g=C3=B3, Zolt=C3=A1n from line 'Cc:=20 K=C5=91v=C3=A1g=C3=B3, Zolt=C3=A1n ' 5.1.1 : Recipient address rejected: User unknown in local=20 recipient table Note to self, enclose utf-8 names, as: Cc: "K=C5=91v=C3=A1g=C3=B3, Zolt=C3=A1n" From MAILER-DAEMON Tue Dec 17 12:54:57 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1ihH3h-0006x8-L0 for mharc-qemu-arm@gnu.org; Tue, 17 Dec 2019 12:54:57 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:59836) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ihH3e-0006vg-Om for qemu-arm@nongnu.org; Tue, 17 Dec 2019 12:54:55 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ihH3d-0008UN-LN for qemu-arm@nongnu.org; Tue, 17 Dec 2019 12:54:54 -0500 Received: from 8.mo179.mail-out.ovh.net ([46.105.75.26]:45792) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1ihH3d-0008HJ-Fr for qemu-arm@nongnu.org; Tue, 17 Dec 2019 12:54:53 -0500 Received: from player711.ha.ovh.net (unknown [10.109.146.131]) by mo179.mail-out.ovh.net (Postfix) with ESMTP id 23AF314E6D1 for ; Tue, 17 Dec 2019 18:54:41 +0100 (CET) Received: from kaod.org (lfbn-tou-1-1227-223.w90-76.abo.wanadoo.fr [90.76.50.223]) (Authenticated sender: clg@kaod.org) by player711.ha.ovh.net (Postfix) with ESMTPSA id 5CE0FD4A870A; Tue, 17 Dec 2019 17:54:34 +0000 (UTC) Subject: Re: [PATCH 4/6] hw/timer/aspeed_timer: Add a fall through comment To: =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= , qemu-devel@nongnu.org Cc: qemu-trivial@nongnu.org, Peter Maydell , Andrew Jeffery , Joel Stanley , qemu-arm@nongnu.org References: <20191217173425.5082-1-philmd@redhat.com> <20191217173425.5082-5-philmd@redhat.com> From: =?UTF-8?Q?C=c3=a9dric_Le_Goater?= Message-ID: <9bbdf21b-a330-b8d2-5fa6-8649adeb9143@kaod.org> Date: Tue, 17 Dec 2019 18:54:31 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.1.1 MIME-Version: 1.0 In-Reply-To: <20191217173425.5082-5-philmd@redhat.com> Content-Type: text/plain; charset=utf-8 Content-Language: en-US X-Ovh-Tracer-Id: 1612570142561831856 X-VR-SPAMSTATE: OK X-VR-SPAMSCORE: -100 X-VR-SPAMCAUSE: gggruggvucftvghtrhhoucdtuddrgedufedrvddtjedguddthecutefuodetggdotefrodftvfcurfhrohhfihhlvgemucfqggfjpdevjffgvefmvefgnecuuegrihhlohhuthemucehtddtnecusecvtfgvtghiphhivghnthhsucdlqddutddtmdenucfjughrpefuvfhfhffkffgfgggjtgfgsehtkeertddtfeejnecuhfhrohhmpeevrogurhhitggpnfgvpgfiohgrthgvrhcuoegtlhhgsehkrghougdrohhrgheqnecukfhppedtrddtrddtrddtpdeltddrjeeirdehtddrvddvfeenucfrrghrrghmpehmohguvgepshhmthhpqdhouhhtpdhhvghlohepphhlrgihvghrjeduuddrhhgrrdhovhhhrdhnvghtpdhinhgvtheptddrtddrtddrtddpmhgrihhlfhhrohhmpegtlhhgsehkrghougdrohhrghdprhgtphhtthhopehqvghmuhdqrghrmhesnhhonhhgnhhurdhorhhgnecuvehluhhsthgvrhfuihiivgeptd Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 46.105.75.26 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 17 Dec 2019 17:54:55 -0000 On 17/12/2019 18:34, Philippe Mathieu-Daud=C3=A9 wrote: > Reported by GCC9 when building with CFLAG -Wimplicit-fallthrough=3D2: >=20 > hw/timer/aspeed_timer.c: In function =E2=80=98aspeed_timer_set_value=E2= =80=99: > hw/timer/aspeed_timer.c:283:24: error: this statement may fall throug= h [-Werror=3Dimplicit-fallthrough=3D] > 283 | if (old_reload || !t->reload) { > | ~~~~~~~~~~~^~~~~~~~~~~~~ > hw/timer/aspeed_timer.c:287:5: note: here > 287 | case TIMER_REG_STATUS: > | ^~~~ > cc1: all warnings being treated as errors >=20 > Add the missing fall through comment. >=20 > Fixes: 1403f364472 > Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: C=C3=A9dric Le Goater > --- > Cc: "C=C3=A9dric Le Goater" > Cc: Peter Maydell > Cc: Andrew Jeffery > Cc: Joel Stanley > Cc: qemu-arm@nongnu.org > --- > hw/timer/aspeed_timer.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) >=20 > diff --git a/hw/timer/aspeed_timer.c b/hw/timer/aspeed_timer.c > index a8c38cc118..c91f18415c 100644 > --- a/hw/timer/aspeed_timer.c > +++ b/hw/timer/aspeed_timer.c > @@ -283,7 +283,7 @@ static void aspeed_timer_set_value(AspeedTimerCtrlS= tate *s, int timer, int reg, > if (old_reload || !t->reload) { > break; > } > - > + /* fall through to re-enable */ > case TIMER_REG_STATUS: > if (timer_enabled(t)) { > uint64_t now =3D qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); >=20 From MAILER-DAEMON Tue Dec 17 12:56:05 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1ihH4m-00084s-H2 for mharc-qemu-arm@gnu.org; Tue, 17 Dec 2019 12:56:05 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:60389) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ihH4h-00081M-Lt for qemu-arm@nongnu.org; Tue, 17 Dec 2019 12:56:01 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ihH4g-0002M7-LK for qemu-arm@nongnu.org; Tue, 17 Dec 2019 12:55:59 -0500 Received: from us-smtp-delivery-1.mimecast.com ([205.139.110.120]:55064 helo=us-smtp-1.mimecast.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1ihH4g-0002Kg-Ho for qemu-arm@nongnu.org; Tue, 17 Dec 2019 12:55:58 -0500 DKIM-Signature: v=1; a=rsa-sha256; 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Tue, 17 Dec 2019 17:55:49 +0000 (UTC) Subject: Re: [PATCH 3/6] hw/net/imx_fec: Rewrite fall through comments To: =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= , qemu-devel@nongnu.org Cc: Peter Maydell , qemu-trivial@nongnu.org, Jason Wang , qemu-arm@nongnu.org, Peter Chubb References: <20191217173425.5082-1-philmd@redhat.com> <20191217173425.5082-4-philmd@redhat.com> From: Thomas Huth Openpgp: preference=signencrypt Message-ID: <2fc74b64-0a0b-c437-e925-4c16d3907da7@redhat.com> Date: Tue, 17 Dec 2019 18:55:47 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101 Thunderbird/60.9.0 MIME-Version: 1.0 In-Reply-To: <20191217173425.5082-4-philmd@redhat.com> Content-Language: en-US X-Scanned-By: MIMEDefang 2.79 on 10.5.11.12 X-MC-Unique: 94uUp8tSNAyWNMdnECtJXQ-1 X-Mimecast-Spam-Score: 0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 205.139.110.120 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 17 Dec 2019 17:56:03 -0000 On 17/12/2019 18.34, Philippe Mathieu-Daud=C3=A9 wrote: > GCC9 is confused by this comment when building with CFLAG > -Wimplicit-fallthrough=3D2: >=20 > hw/net/imx_fec.c: In function =E2=80=98imx_eth_write=E2=80=99: > hw/net/imx_fec.c:906:12: error: this statement may fall through [-Werro= r=3Dimplicit-fallthrough=3D] > 906 | if (unlikely(single_tx_ring)) { > | ^ > hw/net/imx_fec.c:912:5: note: here > 912 | case ENET_TDAR: /* FALLTHROUGH */ > | ^~~~ > cc1: all warnings being treated as errors >=20 > Rewrite the comments in the correct place, using 'fall through' > which is recognized by GCC and static analyzers. >=20 > Signed-off-by: Philippe Mathieu-Daud=C3=A9 > --- > Cc: Peter Chubb > Cc: Peter Maydell > Cc: Jason Wang > Cc: qemu-arm@nongnu.org > --- > hw/net/imx_fec.c | 8 +++++--- > 1 file changed, 5 insertions(+), 3 deletions(-) >=20 > diff --git a/hw/net/imx_fec.c b/hw/net/imx_fec.c > index bd99236864..30cc07753d 100644 > --- a/hw/net/imx_fec.c > +++ b/hw/net/imx_fec.c > @@ -901,15 +901,17 @@ static void imx_eth_write(void *opaque, hwaddr offs= et, uint64_t value, > s->regs[index] =3D 0; > } > break; > - case ENET_TDAR1: /* FALLTHROUGH */ > - case ENET_TDAR2: /* FALLTHROUGH */ > + /* fall through */ Wrong location. And I think you don't need any comment here at all, GCC should stay silent without it? > + case ENET_TDAR1: > + case ENET_TDAR2: > if (unlikely(single_tx_ring)) { > qemu_log_mask(LOG_GUEST_ERROR, > "[%s]%s: trying to access TDAR2 or TDAR1\n", > TYPE_IMX_FEC, __func__); > return; > } > - case ENET_TDAR: /* FALLTHROUGH */ > + /* fall through */ I'd suggest to simply remove it, too. > + case ENET_TDAR: > if (s->regs[ENET_ECR] & ENET_ECR_ETHEREN) { > s->regs[index] =3D ENET_TDAR_TDAR; > imx_eth_do_tx(s, index); >=20 Thomas From MAILER-DAEMON Tue Dec 17 13:27:41 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1ihHZN-0001B5-Ne for mharc-qemu-arm@gnu.org; Tue, 17 Dec 2019 13:27:41 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:46052) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ihHZK-00016W-Oh for qemu-arm@nongnu.org; Tue, 17 Dec 2019 13:27:39 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ihHZJ-0003aH-My for qemu-arm@nongnu.org; Tue, 17 Dec 2019 13:27:38 -0500 Received: from mail-wr1-x441.google.com ([2a00:1450:4864:20::441]:40352) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ihHZG-0003X4-F2; Tue, 17 Dec 2019 13:27:34 -0500 Received: by mail-wr1-x441.google.com with SMTP id c14so12407099wrn.7; Tue, 17 Dec 2019 10:27:33 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=sWACAQsf60rInZdjnYNJIzYNJovtyKvCUnze/9ZfBDg=; b=cj4L/hfrqJ1dS8TQp6lUfRYWKHFhndilaAQXzyv04YBZe5enQgyzB6HZEmOrFQmGeQ Eg/0khdTe2ZlrfqPZksbu3OYIs3mAE4030q6rabkxsBiYqvmnVni0ccEncTgmMR/dJ8d RhWX6CBaAdjXyyHLoI+p4ShOCNtA0j3pB6kqcrEuftcSv7CRDFKb2WE5nNnrQFI+WBgG 5mKeJ0tllZx98t87/RmyZPneN/uMO/Dwn3j7c55MviZQb7bzzRIgFIBUXg9G43OasMlf PfBJBNzboHCB1R77wlrF+XT4JD/7EyETnthW3uCRPYkkokb5Ue7gb3sHj48TfticjB+z vg0g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :mime-version:content-transfer-encoding; bh=sWACAQsf60rInZdjnYNJIzYNJovtyKvCUnze/9ZfBDg=; b=uY0Tdyv6W876gz5wHs7w3KoVm10H04RqF2J6NA+JHzKMfF2FRGGjAvCc7Rx9Um5xpl VSfuyqxIoqBupDwfx3I1rydqgOyztflzra4VrMYSAZjr+yh5xOevy/l7lCiJlFzh+jIG UTOm1VQdnppiSRZkj55arlEDPV+OZR6HrB5fSMacZjkf1V30vwsQ4Tf74UszQ47RITI7 M4Or3whgn6lqstqOIhCCNOpkCUo/jyhOJkZyn0Hk1LbZJ3JRdUuJHPZJeXg6wIZJmBwS IYpxpWxZIJULRHJWFVpW3Whl4lrE8siPq+N7hx+y8YkT/LL+b/DFpX/Y0vsTw+RWsj5F zrSA== X-Gm-Message-State: APjAAAUSj4p61B4JpnsQaxat8ZqzFJW7inlHnYfgYdvggNkk6q/UlBPI 5Eb9P1B8WrqF15r/pQ859vP3Tps3 X-Google-Smtp-Source: APXvYqwf8A894T4a5VQdrdHMhirdZXGVO1EmaZk0q3fDn66iJ1I3ycbS8qjdyh5PRD0Bq+edlC4tNQ== X-Received: by 2002:a5d:6ac5:: with SMTP id u5mr2863265wrw.271.1576607252684; Tue, 17 Dec 2019 10:27:32 -0800 (PST) Received: from x1w.redhat.com (34.red-83-42-66.dynamicip.rima-tde.net. [83.42.66.34]) by smtp.gmail.com with ESMTPSA id u18sm26006975wrt.26.2019.12.17.10.27.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 17 Dec 2019 10:27:31 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Guenter Roeck , Cleber Rosa , Niek Linnenbank , Peter Maydell , qemu-arm@nongnu.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH 0/5] tests/boot_linux_console: Add various OrangePi PC tests Date: Tue, 17 Dec 2019 19:27:25 +0100 Message-Id: <20191217182730.943-1-f4bug@amsat.org> X-Mailer: git-send-email 2.21.0 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 8bit X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::441 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 17 Dec 2019 18:27:40 -0000 This series collect the examples given by Niek on: https://www.mail-archive.com/qemu-devel@nongnu.org/msg665532.html Based-on: <20191216233519.29030-1-nieklinnenbank@gmail.com> Philippe Mathieu-Daudé (5): tests/boot_linux_console: Add a quick test for the OrangePi PC board tests/boot_linux_console: Add initrd test for the Orange Pi PC board tests/boot_linux_console: Add a SD card test for the OrangePi PC board !fixup "hw: arm: add Xunlong Orange Pi PC machine" tests/boot_linux_console: Add a SLOW test booting Ubuntu on OrangePi PC hw/arm/orangepi.c | 1 + tests/acceptance/boot_linux_console.py | 150 +++++++++++++++++++++++++ 2 files changed, 151 insertions(+) -- 2.21.0 From MAILER-DAEMON Tue Dec 17 13:27:44 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1ihHZQ-0001FA-1f for mharc-qemu-arm@gnu.org; Tue, 17 Dec 2019 13:27:44 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:46097) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ihHZM-00019Q-L6 for qemu-arm@nongnu.org; Tue, 17 Dec 2019 13:27:42 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ihHZL-0003cN-9V for qemu-arm@nongnu.org; Tue, 17 Dec 2019 13:27:40 -0500 Received: from mail-wr1-x42e.google.com ([2a00:1450:4864:20::42e]:33810) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ihHZI-0003XA-1e; Tue, 17 Dec 2019 13:27:36 -0500 Received: by mail-wr1-x42e.google.com with SMTP id t2so12436438wrr.1; Tue, 17 Dec 2019 10:27:34 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=sEW+kg5xC2YTirRGSRWpCZbEvF55I4jI+uWx8tZT5Y4=; b=NS5ugS7vx4/S7BIEVz9EeCDVOQf5t/m480ixDlTHC7YDnUnuFpTQHaEslilESETdon M0OYDZmUgsFoHMrRopdDme0TGtPcQUMM+Q/M1AuOb7qrZGi+MFOT5xwUR13a+QR6C4nk z9DmIf0mPODU+kKRwUFbbA/ZlKMuiSa0XHJ0Af0DKh5Map2JSxgp3TL/HvcIdjuIgwHp KsOoFhclZ5qLkGtBJih5/Gd0IJR8KVlNexAU4Yg0OP7p1PWTILclLpAdFVRFsS6SkbEl b61vB2mhuI+Z/WThYslezxql/KsJswfDdpQazojZCosdsYdZQx1YNHgBkC1FCGEgeuYT EuCA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=sEW+kg5xC2YTirRGSRWpCZbEvF55I4jI+uWx8tZT5Y4=; b=peeFGm59jz66CVJOqj9N9a6fTv5wXW3FPhAXhyCOjS3pWQszsvbhhgF4yHWo8F2zKN cGXlBTjbCxHF/6SyQnqH0Y7BA+W+0l2X5UW3vg/fuByHrG1rGs+z4MTo8RwpD6EbRM8z 9qj3M5f86lrByKS+w5mxm0Vw8yB7JGIvTX9NGDfWh4/QD5syN2ufOq+7ddAuoZjZ0Hho PNZTi24L31zKAVTcR3Uj3F7zmwYgZEfIh1nYFJyrLS/mEj58QCJS44oVYoYkNBwC5/Fd BwNDhRr9B6048MXndY5BrY2+fFtcG6i71uqSRMrFol6jtN3pEVtiJfRddhnV/QcUeHFM UdGw== X-Gm-Message-State: APjAAAUTTYiGlZ0no9TybSNtMiTJCijQAZL8ngjEQzrEBN+HRXzY+DF/ nB9Qyzkd8QSV39mKnO5N/iF0CBSp X-Google-Smtp-Source: APXvYqzpXQi06tQWf5yEBuaBxI/VIok4gQaqZtBBAMpBoAEsSmbJRuhthuaIrrhlVdFX/PPOgITSaQ== X-Received: by 2002:a5d:4204:: with SMTP id n4mr27800031wrq.123.1576607253854; Tue, 17 Dec 2019 10:27:33 -0800 (PST) Received: from x1w.redhat.com (34.red-83-42-66.dynamicip.rima-tde.net. [83.42.66.34]) by smtp.gmail.com with ESMTPSA id u18sm26006975wrt.26.2019.12.17.10.27.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 17 Dec 2019 10:27:33 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Guenter Roeck , Cleber Rosa , Niek Linnenbank , Peter Maydell , qemu-arm@nongnu.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH 1/5] tests/boot_linux_console: Add a quick test for the OrangePi PC board Date: Tue, 17 Dec 2019 19:27:26 +0100 Message-Id: <20191217182730.943-2-f4bug@amsat.org> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20191217182730.943-1-f4bug@amsat.org> References: <20191217182730.943-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 8bit X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::42e X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 17 Dec 2019 18:27:42 -0000 This test boots a Linux kernel on a OrangePi PC board and verify the serial output is working. The kernel image and DeviceTree blob are built by the Raspbian project (based on Debian): https://www.raspbian.org/RaspbianImages If ARM is a target being built, "make check-acceptance" will automatically include this test by the use of the "arch:arm" tags. Alternatively, this test can be run using: $ make check-venv $ ./tests/venv/bin/avocado --show=console,app run -t machine:orangepi-pc tests/acceptance/boot_linux_console.py JOB ID : 2e4d15eceb13c33672af406f08171e6e9de1414a JOB LOG : ~/job-results/job-2019-12-17T05.46-2e4d15e/job.log (1/1) tests/acceptance/boot_linux_console.py:BootLinuxConsole.test_arm_orangepi: console: Uncompressing Linux... done, booting the kernel. console: Booting Linux on physical CPU 0x0 console: Linux version 4.20.7-sunxi (root@armbian.com) (gcc version 7.2.1 20171011 (Linaro GCC 7.2-2017.11)) #5.75 SMP Fri Feb 8 09:02:10 CET 2019 console: CPU: ARMv7 Processor [410fc075] revision 5 (ARMv7), cr=50c5387d console: CPU: div instructions available: patching division code console: CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing instruction cache console: OF: fdt: Machine model: Xunlong Orange Pi PC console: Memory policy: Data cache writealloc console: OF: reserved mem: failed to allocate memory for node 'cma@4a000000' console: cma: Failed to reserve 128 MiB console: psci: probing for conduit method from DT. console: psci: PSCIv0.2 detected in firmware. console: psci: Using standard PSCI v0.2 function IDs console: psci: Trusted OS migration not required console: random: get_random_bytes called from start_kernel+0x8d/0x3c2 with crng_init=0 console: percpu: Embedded 18 pages/cpu @(ptrval) s41228 r8192 d24308 u73728 console: Built 1 zonelists, mobility grouping on. Total pages: 32480 console: Kernel command line: printk.time=0 console=ttyS0,115200 PASS (8.59 s) JOB TIME : 8.81 s Signed-off-by: Philippe Mathieu-Daudé --- tests/acceptance/boot_linux_console.py | 26 ++++++++++++++++++++++++++ 1 file changed, 26 insertions(+) diff --git a/tests/acceptance/boot_linux_console.py b/tests/acceptance/boot_linux_console.py index 7e41cebd47..820239e439 100644 --- a/tests/acceptance/boot_linux_console.py +++ b/tests/acceptance/boot_linux_console.py @@ -411,6 +411,32 @@ class BootLinuxConsole(Test): self.wait_for_console_pattern('Boot successful.') # TODO user command, for now the uart is stuck + def test_arm_orangepi(self): + """ + :avocado: tags=arch:arm + :avocado: tags=machine:orangepi-pc + """ + deb_url = ('https://apt.armbian.com/pool/main/l/' + 'linux-4.20.7-sunxi/linux-image-dev-sunxi_5.75_armhf.deb') + deb_hash = '1334c29c44d984ffa05ed10de8c3361f33d78315' + deb_path = self.fetch_asset(deb_url, asset_hash=deb_hash) + kernel_path = self.extract_from_deb(deb_path, + '/boot/vmlinuz-4.20.7-sunxi') + dtb_path = '/usr/lib/linux-image-dev-sunxi/sun8i-h3-orangepi-pc.dtb' + dtb_path = self.extract_from_deb(deb_path, dtb_path) + + self.vm.set_machine('orangepi-pc') + self.vm.set_console() + kernel_command_line = (self.KERNEL_COMMON_COMMAND_LINE + + 'console=ttyS0,115200n8 ' + 'earlycon=uart,mmio32,0x1c28000') + self.vm.add_args('-kernel', kernel_path, + '-dtb', dtb_path, + '-append', kernel_command_line) + self.vm.launch() + console_pattern = 'Kernel command line: %s' % kernel_command_line + self.wait_for_console_pattern(console_pattern) + def test_s390x_s390_ccw_virtio(self): """ :avocado: tags=arch:s390x -- 2.21.0 From MAILER-DAEMON Tue Dec 17 13:27:45 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1ihHZR-0001HR-Dl for mharc-qemu-arm@gnu.org; Tue, 17 Dec 2019 13:27:45 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:46129) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ihHZO-0001CQ-Eq for qemu-arm@nongnu.org; Tue, 17 Dec 2019 13:27:43 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ihHZN-0003dr-CM for qemu-arm@nongnu.org; Tue, 17 Dec 2019 13:27:42 -0500 Received: from mail-wr1-x444.google.com ([2a00:1450:4864:20::444]:45858) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ihHZK-0003bH-Ue; Tue, 17 Dec 2019 13:27:39 -0500 Received: by mail-wr1-x444.google.com with SMTP id j42so8205346wrj.12; Tue, 17 Dec 2019 10:27:38 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=X3aoTKFOEPvDjRCIHjLD6crQEVS/A3CYuC7Vv8K4W3k=; b=kE56C8E/NbtpZjNbq9bhK3mGzU1Wq7Vkr0T1aZ+irlcv+JVhVJbQZeK/GkmmUjPju+ aqeuC+SDPJKdaM+MVDpdUwsHj5QPE19K9fwW1kU5InIhrclIsNU4mF3KU3ioxA6ouA1E 0dY8N5rj+87UJFNwwkWUE0Qg+mTHTXZvuy93OtV5p6rwvzx/laizm27jZeyRudxywUl1 qi741fKh57GmrzMODQpVA5ShhHLJL8qEzdwti49fvJ8613lTkLpyPUX+hPtUKzyBpTTE S9JjiwbHQuRlj6cHSU9Cj7hZZVWdKq27eIFyfyoqwF2WNaA3W1Fh295WFpBbmjmIMIve X0eA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=X3aoTKFOEPvDjRCIHjLD6crQEVS/A3CYuC7Vv8K4W3k=; b=tQQOhSmi4/yAByk00U67litF7PxyBrQYvBQE4WtPM4eGEe6kV7G/GylkV0CYfjZ5w6 REpaloGwcq4kGBcO474Iz9ewNiGaQU/eHidCYVXYIgq+Ugvxktz0NBnwLblGKzs1gsg5 eQ+um/76t0jT07dXYXjTx/Ffm/2pYCx3VK1dxfx6WIBYCkG4fBa2uDk+0FndJGPYEecf hPZP7Y4bYTvr2xnpzRLkj2QMa5WzBrzIvCVCVggrK2Cep8gd4McALrTIYiqwM9uGdSTk d/kti2NOirNTAo1hyX8RobomIfzHmSqqmvu+ozhLVB78NU/RGUFp4buyYAVWgcMRzENA pGiw== X-Gm-Message-State: APjAAAWGXGD3HXQjiX5+RZLO/jLevr0OamvSotEvwafQnrrCHmmmqrLd wnnahsWKFMLTAb/uff8okIC1UruD X-Google-Smtp-Source: APXvYqyZ5JCy9eLjrKZCQjIZvdUJdMtMSyEFMXoHKNU/gOHTb+kA2mYIpF43cVJO7t+vk/W1a6WFkA== X-Received: by 2002:a5d:6144:: with SMTP id y4mr38472286wrt.15.1576607257776; Tue, 17 Dec 2019 10:27:37 -0800 (PST) Received: from x1w.redhat.com (34.red-83-42-66.dynamicip.rima-tde.net. [83.42.66.34]) by smtp.gmail.com with ESMTPSA id u18sm26006975wrt.26.2019.12.17.10.27.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 17 Dec 2019 10:27:37 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Guenter Roeck , Cleber Rosa , Niek Linnenbank , Peter Maydell , qemu-arm@nongnu.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [RFC PATCH 4/5] !fixup "hw: arm: add Xunlong Orange Pi PC machine" Date: Tue, 17 Dec 2019 19:27:29 +0100 Message-Id: <20191217182730.943-5-f4bug@amsat.org> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20191217182730.943-1-f4bug@amsat.org> References: <20191217182730.943-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 8bit X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::444 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 17 Dec 2019 18:27:44 -0000 Without this, the machine starts with default 128MB, and Ubuntu Bionic fails: [ *** ] (2 of 4) A start job is running for…Persistent Storage (37s / 2min 1s) [ *** ] (2 of 4) A start job is running for…Persistent Storage (38s / 2min 1s) [ OK ] Started Flush Journal to Persistent Storage. Starting Create Volatile Files and Directories... Starting Armbian ZRAM config... [ **] (3 of 6) A start job is running for…s and Directories (55s / no limit) [ *] (3 of 6) A start job is running for…s and Directories (55s / no limit) [ **] (3 of 6) A start job is running for…s and Directories (56s / no limit) [ OK ] Started Create Volatile Files and Directories. [*** ] (5 of 6) A start job is running for… ZRAM config (1min 10s / 1min 19s) [** ] (5 of 6) A start job is running for… ZRAM config (1min 12s / 1min 19s) [* ] (5 of 6) A start job is running for… ZRAM config (1min 13s / 1min 19s) [FAILED] Failed to start Armbian ZRAM config. See 'systemctl status armbian-zram-config.service' for details. Signed-off-by: Philippe Mathieu-Daudé --- hw/arm/orangepi.c | 1 + 1 file changed, 1 insertion(+) diff --git a/hw/arm/orangepi.c b/hw/arm/orangepi.c index 119f370924..da758d7eba 100644 --- a/hw/arm/orangepi.c +++ b/hw/arm/orangepi.c @@ -122,6 +122,7 @@ static void orangepi_machine_init(MachineClass *mc) mc->max_cpus = AW_H3_NUM_CPUS; mc->default_cpus = AW_H3_NUM_CPUS; mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-a7"); + mc->default_ram_size = 1 * GiB; } DEFINE_MACHINE("orangepi-pc", orangepi_machine_init) -- 2.21.0 From MAILER-DAEMON Tue Dec 17 13:27:46 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1ihHZS-0001JD-C1 for mharc-qemu-arm@gnu.org; Tue, 17 Dec 2019 13:27:46 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:46112) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ihHZN-0001Ah-DF for qemu-arm@nongnu.org; Tue, 17 Dec 2019 13:27:42 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ihHZL-0003cr-Od for qemu-arm@nongnu.org; Tue, 17 Dec 2019 13:27:41 -0500 Received: from mail-wm1-x333.google.com ([2a00:1450:4864:20::333]:52909) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ihHZI-0003Xb-Eb; Tue, 17 Dec 2019 13:27:36 -0500 Received: by mail-wm1-x333.google.com with SMTP id p9so3947301wmc.2; Tue, 17 Dec 2019 10:27:36 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=viU+DDZUT4ghn6789AdHJEf+Umo/KWlf1a8ZVE1hUZI=; b=pyrLdMSBAiijNyXKq1hGBJvkw5RmyUVPsa6aeoBLHPHSJXqGEG5IfEKV8pkSpsQ7Iu s/CWJLWEBNJG39EgiQnCoE+0npwfwXx14wpzNJDkanxVrxjPQtnZ6zffUgwyVva/9ZXp AFTvebeje5mpNmUx5MAWa1IOUCr2MNh7Ns9uFfe3N/f8mUP/RP7ExVEtAY1u1nDGppQ6 HkRl/YXpw8cWkXXO34DWdDdsevXqGXjOTSAWQK84Q0hmJbJP5pEgBVmVccCL5VMhzX3J FdBxVp6E2LWE8wfUhUso0gZc6V9e+k1gP9FmVIddDakvv17gRngi44Ix+nY1CWV1RQms xi8g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=viU+DDZUT4ghn6789AdHJEf+Umo/KWlf1a8ZVE1hUZI=; b=jwrtxmHG3+CEjQR9kkexePjSUhp4vAnyZi4rNwpBVqhw3ixvvzuAOXTWourihFguox Aldgx04vxkEaZuyi2D+C39LhMjVsQOnj9UWrBw+tWYE/jdRXUwuBbMAZ42YIgPVxwD+s Vz9NC937lY50SVRzU/O5ahTR99F2w5vFlL70ZUbIhrh8Tpoqvd8gWNQiEAKe1zc1bsu4 r45wHJ/vPmLM+TpRGlGg1ByiA7TT1fTnPJ+QmVvkUZ9dKkyegQhJU4IABhU7UNdyXgln 6Iu9xcdjZ3YKLtEW1arAwuJEepIvSO56GfJFoX7/dtLdeWfg0RFNgFotapiuMcC8VusZ KOsA== X-Gm-Message-State: APjAAAV9YLwlhVz8p7O+z27V9y04sAd0AuexEMe5JNzAA14qM3aF3Q6k EWo3WGlK/wkbChcGHuuk3NCCEMOk X-Google-Smtp-Source: APXvYqwtyS8dA3jInb2IPr0oKM1w6Fng0HYwbtOnDkpRULgH84yGt0h/t27f/04iZa8MB85DJty5Sg== X-Received: by 2002:a1c:1f56:: with SMTP id f83mr7181656wmf.93.1576607255198; Tue, 17 Dec 2019 10:27:35 -0800 (PST) Received: from x1w.redhat.com (34.red-83-42-66.dynamicip.rima-tde.net. [83.42.66.34]) by smtp.gmail.com with ESMTPSA id u18sm26006975wrt.26.2019.12.17.10.27.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 17 Dec 2019 10:27:34 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Guenter Roeck , Cleber Rosa , Niek Linnenbank , Peter Maydell , qemu-arm@nongnu.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH 2/5] tests/boot_linux_console: Add initrd test for the Orange Pi PC board Date: Tue, 17 Dec 2019 19:27:27 +0100 Message-Id: <20191217182730.943-3-f4bug@amsat.org> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20191217182730.943-1-f4bug@amsat.org> References: <20191217182730.943-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 8bit X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::333 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 17 Dec 2019 18:27:44 -0000 This test boots a Linux kernel on a OrangePi PC board and verify the serial output is working. The kernel image and DeviceTree blob are built by the Raspbian project (based on Debian): https://www.raspbian.org/RaspbianImages The cpio image used comes from the linux-build-test project: https://github.com/groeck/linux-build-test If ARM is a target being built, "make check-acceptance" will automatically include this test by the use of the "arch:arm" tags. Alternatively, this test can be run using: $ avocado --show=console run -t machine:orangepi-pc tests/acceptance/boot_linux_console.py console: Uncompressing Linux... done, booting the kernel. console: Booting Linux on physical CPU 0x0 console: Linux version 4.20.7-sunxi (root@armbian.com) (gcc version 7.2.1 20171011 (Linaro GCC 7.2-2017.11)) #5.75 SMP Fri Feb 8 09:02:10 CET 2019 console: CPU: ARMv7 Processor [410fc075] revision 5 (ARMv7), cr=50c5387d console: CPU: div instructions available: patching division code console: CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing instruction cache console: OF: fdt: Machine model: Xunlong Orange Pi PC [...] console: Trying to unpack rootfs image as initramfs... console: Freeing initrd memory: 3256K console: Freeing unused kernel memory: 1024K console: Run /init as init process console: mount: mounting devtmpfs on /dev failed: Device or resource busy console: Starting logging: OK console: Initializing random number generator... random: dd: uninitialized urandom read (512 bytes read) console: done. console: Starting network: OK console: Found console ttyS0 console: Linux version 4.20.7-sunxi (root@armbian.com) (gcc version 7.2.1 20171011 (Linaro GCC 7.2-2017.11)) #5.75 SMP Fri Feb 8 09:02:10 CET 2019 console: Boot successful. console: cat /proc/cpuinfo console: / # cat /proc/cpuinfo console: processor : 0 console: model name : ARMv7 Processor rev 5 (v7l) console: BogoMIPS : 125.00 console: Features : half thumb fastmult vfp edsp neon vfpv3 tls vfpv4 idiva idivt vfpd32 lpae evtstrm console: CPU implementer : 0x41 console: CPU architecture: 7 console: CPU variant : 0x0 console: CPU part : 0xc07 console: CPU revision : 5 [...] console: processor : 3 console: model name : ARMv7 Processor rev 5 (v7l) console: BogoMIPS : 125.00 console: Features : half thumb fastmult vfp edsp neon vfpv3 tls vfpv4 idiva idivt vfpd32 lpae evtstrm console: CPU implementer : 0x41 console: CPU architecture: 7 console: CPU variant : 0x0 console: CPU part : 0xc07 console: CPU revision : 5 console: Hardware : Allwinner sun8i Family console: Revision : 0000 console: Serial : 0000000000000000 console: cat /proc/iomem console: / # cat /proc/iomem console: 01000000-010fffff : clock@1000000 console: 01c00000-01c00fff : system-control@1c00000 console: 01c02000-01c02fff : dma-controller@1c02000 [...] console: reboot console: / # reboot console: / # Found console ttyS0 console: Stopping network: OK console: hrtimer: interrupt took 21852064 ns console: Saving random seed... random: dd: uninitialized urandom read (512 bytes read) console: done. console: Stopping logging: OK console: umount: devtmpfs busy - remounted read-only console: umount: can't unmount /: Invalid argument console: The system is going down NOW! console: Sent SIGTERM to all processes console: Sent SIGKILL to all processes console: Requesting system reboot console: reboot: Restarting system PASS (48.32 s) JOB TIME : 49.16 s Signed-off-by: Philippe Mathieu-Daudé --- tests/acceptance/boot_linux_console.py | 41 ++++++++++++++++++++++++++ 1 file changed, 41 insertions(+) diff --git a/tests/acceptance/boot_linux_console.py b/tests/acceptance/boot_linux_console.py index 820239e439..daabd47404 100644 --- a/tests/acceptance/boot_linux_console.py +++ b/tests/acceptance/boot_linux_console.py @@ -437,6 +437,47 @@ class BootLinuxConsole(Test): console_pattern = 'Kernel command line: %s' % kernel_command_line self.wait_for_console_pattern(console_pattern) + def test_arm_orangepi_initrd(self): + """ + :avocado: tags=arch:arm + :avocado: tags=machine:orangepi-pc + """ + deb_url = ('https://apt.armbian.com/pool/main/l/' + 'linux-4.20.7-sunxi/linux-image-dev-sunxi_5.75_armhf.deb') + deb_hash = '1334c29c44d984ffa05ed10de8c3361f33d78315' + deb_path = self.fetch_asset(deb_url, asset_hash=deb_hash) + kernel_path = self.extract_from_deb(deb_path, + '/boot/vmlinuz-4.20.7-sunxi') + dtb_path = '/usr/lib/linux-image-dev-sunxi/sun8i-h3-orangepi-pc.dtb' + dtb_path = self.extract_from_deb(deb_path, dtb_path) + initrd_url = ('https://github.com/groeck/linux-build-test/raw/' + '2eb0a73b5d5a28df3170c546ddaaa9757e1e0848/rootfs/' + 'arm/rootfs-armv7a.cpio.gz') + initrd_hash = '604b2e45cdf35045846b8bbfbf2129b1891bdc9c' + initrd_path_gz = self.fetch_asset(initrd_url, asset_hash=initrd_hash) + initrd_path = os.path.join(self.workdir, 'rootfs.cpio') + archive.gzip_uncompress(initrd_path_gz, initrd_path) + + self.vm.set_machine('orangepi-pc') + self.vm.set_console() + kernel_command_line = (self.KERNEL_COMMON_COMMAND_LINE + + 'console=ttyS0,115200 ' + 'panic=-1 noreboot') + self.vm.add_args('-kernel', kernel_path, + '-dtb', dtb_path, + '-initrd', initrd_path, + '-append', kernel_command_line, + '-no-reboot') + self.vm.launch() + self.wait_for_console_pattern('Boot successful.') + + exec_command_and_wait_for_pattern(self, 'cat /proc/cpuinfo', + 'Allwinner sun8i Family') + exec_command_and_wait_for_pattern(self, 'cat /proc/iomem', + 'system-control@1c00000') + exec_command_and_wait_for_pattern(self, 'reboot', + 'reboot: Restarting system') + def test_s390x_s390_ccw_virtio(self): """ :avocado: tags=arch:s390x -- 2.21.0 From MAILER-DAEMON Tue Dec 17 13:27:48 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1ihHZU-0001Mu-JR for mharc-qemu-arm@gnu.org; Tue, 17 Dec 2019 13:27:48 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:46155) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ihHZR-0001H8-5x for qemu-arm@nongnu.org; Tue, 17 Dec 2019 13:27:46 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ihHZP-0003fr-Hh for qemu-arm@nongnu.org; Tue, 17 Dec 2019 13:27:45 -0500 Received: from mail-wr1-x431.google.com ([2a00:1450:4864:20::431]:45602) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ihHZM-0003cn-5h; Tue, 17 Dec 2019 13:27:40 -0500 Received: by mail-wr1-x431.google.com with SMTP id j42so8205416wrj.12; Tue, 17 Dec 2019 10:27:40 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=2/FzkBv2p4X12H/+2U7qu7eJmZZZlUhmWwgrYm57BRk=; b=I4esM/wInfAajD5fjP2FN5D/DtuPeSkz7Rz9wzeBG8TJMI3r8yllu6LpJTuDBTe/36 qbCrXGMuwOZjAIcYnoEDROFPd5PJayl0LHOIQm3JAX06bcFDos9VhMW9NbAc9B3uNHI6 kgJ5cnQR7I0hmcNX7RLAP6ONR32vepz9RGDi4jKF+dV8+ySV5D65av2OpzgGBlgMp7eb hwZXXRZGCsMBLFWXjUxv8851AoW800fHAeZdFLW03qF+EjSj+6BJwVof3oy78OL2ygop f9uKG32B9LerkRnfxj8tSgywHjDj42FamycLuyfyhs/tyxvyI2LGErVvIr9fcfSceFQQ owcQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=2/FzkBv2p4X12H/+2U7qu7eJmZZZlUhmWwgrYm57BRk=; b=RE5EQAhKXjnxBfd6hPXXMd6QfFFzBQ1Q4lA71U1ihmXSM6pqHj8jrZIJYn9QIuCllH bfFRTly7HeEWscOa/naObnCuv/XVel88f+O+23qJaF44wpPzh8mXX9qsr+LdX3OtgWuG MXNoSlTT2tZ9Vsy2QH4lVHtvY3nbDZFjz+rp/VIWWO4zH7syY0hySHB0SpIpr0dgvFWh M/3+SzRehobd/KnSIRZLk7e/o4yDKp285qKKzeg4ie0ForDO8FG4ea2xQLQUEwvCJOoQ ncyXkkya/cJctmNgxTSZNiJQAxuxaai8duWE2LRx6XYFeXNufmB1I3BpHPGsq9ev+RqF hDyg== X-Gm-Message-State: APjAAAXTxDjzafgesGFl900Dxc1A0RsULVv+JyJfnkPU8lXKTUPOvIvK b1y4IfBFcZdZqUkD/niNKjg9qnVQ X-Google-Smtp-Source: APXvYqxLOhGl9Qj+8rVMc+HHu+QL9rH2y2oSRpiKD3Sqgd1lb7V4UXWUqNQhyFaFd73AwXvz48zTTg== X-Received: by 2002:a05:6000:1288:: with SMTP id f8mr38305876wrx.66.1576607258930; Tue, 17 Dec 2019 10:27:38 -0800 (PST) Received: from x1w.redhat.com (34.red-83-42-66.dynamicip.rima-tde.net. [83.42.66.34]) by smtp.gmail.com with ESMTPSA id u18sm26006975wrt.26.2019.12.17.10.27.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 17 Dec 2019 10:27:38 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Guenter Roeck , Cleber Rosa , Niek Linnenbank , Peter Maydell , qemu-arm@nongnu.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [RFC PATCH 5/5] tests/boot_linux_console: Add a SLOW test booting Ubuntu on OrangePi PC Date: Tue, 17 Dec 2019 19:27:30 +0100 Message-Id: <20191217182730.943-6-f4bug@amsat.org> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20191217182730.943-1-f4bug@amsat.org> References: <20191217182730.943-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 8bit X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::431 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 17 Dec 2019 18:27:47 -0000 This test boots Ubuntu Bionic on a OrangePi PC board. As it requires 1GB of storage, and is slow, this test is disabled on automatic CI testing. It is useful for workstation testing. Currently Avocado timeouts too quickly, so we can't run userland commands. The kernel image and DeviceTree blob are built by the Raspbian project (based on Debian): https://www.raspbian.org/RaspbianImages The Ubuntu image is downloaded from: https://dl.armbian.com/orangepipc/Bionic_current This test can be run using: $ AVOCADO_ALLOW_LARGE_STORAGE=yes \ avocado --show=app,console run -t machine:orangepi-pc \ tests/acceptance/boot_linux_console.py console: Uncompressing Linux... done, booting the kernel. console: Booting Linux on physical CPU 0x0 console: Linux version 4.20.7-sunxi (root@armbian.com) (gcc version 7.2.1 20171011 (Linaro GCC 7.2-2017.11)) #5.75 SMP Fri Feb 8 09:02:10 CET 2019 console: CPU: ARMv7 Processor [410fc075] revision 5 (ARMv7), cr=50c5387d console: CPU: div instructions available: patching division code console: CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing instruction cache console: OF: fdt: Machine model: Xunlong Orange Pi PC [...] console: sunxi-mmc 1c0f000.mmc: initialized, max. request size: 16384 KB console: NET: Registered protocol family 10 console: mmc0: host does not support reading read-only switch, assuming write-enable console: mmc0: Problem switching card into high-speed mode! console: mmc0: new SD card at address 4567 console: mmcblk0: mmc0:4567 QEMU! 932 MiB console: Segment Routing with IPv6 console: NET: Registered protocol family 17 console: NET: Registered protocol family 15 console: bridge: filtering via arp/ip/ip6tables is no longer available by default. Update your scripts to load br_netfilter if you need this. console: 8021q: 802.1Q VLAN Support v1.8 console: Key type dns_resolver registered console: Registering SWP/SWPB emulation handler console: mmcblk0: p1 [...] console: Freeing unused kernel memory: 1024K console: Run /sbin/init as init process console: random: fast init done console: systemd[1]: System time before build time, advancing clock. console: systemd[1]: systemd 237 running in system mode. (+PAM +AUDIT +SELINUX +IMA +APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT +GNUTLS +ACL +XZ +LZ4 +SECCOMP +BLKID +ELFUTILS +KMOD -IDN2 +IDN -PCRE2 default-hierarchy=hybrid) console: systemd[1]: Detected architecture arm. console: Welcome to Ubuntu 18.04.3 LTS! console: systemd[1]: Set hostname to . console: random: systemd: uninitialized urandom read (16 bytes read) Signed-off-by: Philippe Mathieu-Daudé --- RFC because this is not the definitive test, but it is helpful so for for testing Niek work. --- tests/acceptance/boot_linux_console.py | 41 ++++++++++++++++++++++++++ 1 file changed, 41 insertions(+) diff --git a/tests/acceptance/boot_linux_console.py b/tests/acceptance/boot_linux_console.py index 8179b45910..663290e0c7 100644 --- a/tests/acceptance/boot_linux_console.py +++ b/tests/acceptance/boot_linux_console.py @@ -520,6 +520,47 @@ class BootLinuxConsole(Test): exec_command_and_wait_for_pattern(self, 'reboot', 'reboot: Restarting system') + @skipUnless(os.getenv('AVOCADO_ALLOW_LARGE_STORAGE'), 'storage limited') + def test_arm_orangepi_bionic(self): + """ + :avocado: tags=arch:arm + :avocado: tags=machine:orangepi-pc + """ + # This test download a 196MB compressed image and expand it to 932MB... + deb_url = ('https://apt.armbian.com/pool/main/l/' + 'linux-4.20.7-sunxi/linux-image-dev-sunxi_5.75_armhf.deb') + deb_hash = '1334c29c44d984ffa05ed10de8c3361f33d78315' + deb_path = self.fetch_asset(deb_url, asset_hash=deb_hash) + kernel_path = self.extract_from_deb(deb_path, + '/boot/vmlinuz-4.20.7-sunxi') + dtb_path = '/usr/lib/linux-image-dev-sunxi/sun8i-h3-orangepi-pc.dtb' + dtb_path = self.extract_from_deb(deb_path, dtb_path) + image_url = ('https://dl.armbian.com/orangepipc/archive/' + 'Armbian_19.11.3_Orangepipc_bionic_current_5.3.9.7z') + image_hash = '196a8ffb72b0123d92cea4a070894813d305c71e' + image_path_xz = self.fetch_asset(image_url, asset_hash=image_hash) + image_name = 'Armbian_19.11.3_Orangepipc_bionic_current_5.3.9.img' + image_path = os.path.join(self.workdir, image_name) + archive.lzma_uncompress(image_path_xz, image_path) + + self.vm.set_machine('orangepi-pc') + self.vm.set_console() + kernel_command_line = (self.KERNEL_COMMON_COMMAND_LINE + + 'console=ttyS0,115200 ' + 'root=/dev/mmcblk0p1 rootwait rw ' + 'systemd.mask=dev-ttyS0.device ' + 'systemd.mask=armbian-zram-config.service ' + 'systemd.mask=armbian-ramlog.service') + self.vm.add_args('-kernel', kernel_path, + '-dtb', dtb_path, + '-drive', 'file=' + image_path + ',if=sd,format=raw', + '-append', kernel_command_line, + '-nic', 'user', + '-no-reboot') + self.vm.launch() + self.wait_for_console_pattern('Welcome to Ubuntu 18.04.3 LTS!') + self.wait_for_console_pattern('Started Armbian filesystem resize.') + def test_s390x_s390_ccw_virtio(self): """ :avocado: tags=arch:s390x -- 2.21.0 From MAILER-DAEMON Tue Dec 17 13:27:49 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1ihHZV-0001Oz-Pq for mharc-qemu-arm@gnu.org; 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[83.42.66.34]) by smtp.gmail.com with ESMTPSA id u18sm26006975wrt.26.2019.12.17.10.27.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 17 Dec 2019 10:27:35 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Guenter Roeck , Cleber Rosa , Niek Linnenbank , Peter Maydell , qemu-arm@nongnu.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH 3/5] tests/boot_linux_console: Add a SD card test for the OrangePi PC board Date: Tue, 17 Dec 2019 19:27:28 +0100 Message-Id: <20191217182730.943-4-f4bug@amsat.org> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20191217182730.943-1-f4bug@amsat.org> References: <20191217182730.943-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 8bit X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::334 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 17 Dec 2019 18:27:48 -0000 The kernel image and DeviceTree blob are built by the Raspbian project (based on Debian): https://www.raspbian.org/RaspbianImages The SD image is from the kernelci.org project: https://kernelci.org/faq/#the-code If ARM is a target being built, "make check-acceptance" will automatically include this test by the use of the "arch:arm" tags. Alternatively, this test can be run using: $ avocado --show=console run -t machine:orangepi-pc tests/acceptance/boot_linux_console.py console: Uncompressing Linux... done, booting the kernel. console: Booting Linux on physical CPU 0x0 console: Linux version 4.20.7-sunxi (root@armbian.com) (gcc version 7.2.1 20171011 (Linaro GCC 7.2-2017.11)) #5.75 SMP Fri Feb 8 09:02:10 CET 2019 console: CPU: ARMv7 Processor [410fc075] revision 5 (ARMv7), cr=50c5387d [...] console: sunxi-wdt 1c20ca0.watchdog: Watchdog enabled (timeout=16 sec, nowayout=0) console: sunxi-mmc 1c0f000.mmc: Linked as a consumer to regulator.2 console: sunxi-mmc 1c0f000.mmc: Got CD GPIO console: ledtrig-cpu: registered to indicate activity on CPUs console: hidraw: raw HID events driver (C) Jiri Kosina console: usbcore: registered new interface driver usbhid console: usbhid: USB HID core driver console: Initializing XFRM netlink socket console: sunxi-mmc 1c0f000.mmc: initialized, max. request size: 16384 KB console: NET: Registered protocol family 10 console: mmc0: host does not support reading read-only switch, assuming write-enable console: mmc0: Problem switching card into high-speed mode! console: mmc0: new SD card at address 4567 console: mmcblk0: mmc0:4567 QEMU! 60.0 MiB [...] console: EXT4-fs (mmcblk0): mounting ext2 file system using the ext4 subsystem console: EXT4-fs (mmcblk0): mounted filesystem without journal. Opts: (null) console: VFS: Mounted root (ext2 filesystem) on device 179:0. console: Run /sbin/init as init process console: EXT4-fs (mmcblk0): re-mounted. Opts: block_validity,barrier,user_xattr,acl console: Starting syslogd: OK console: Starting klogd: OK console: Populating /dev using udev: udevd[203]: starting version 3.2.7 console: /bin/sh: can't access tty; job control turned off console: cat /proc/partitions console: / # cat /proc/partitions console: major minor #blocks name console: 1 0 4096 ram0 console: 1 1 4096 ram1 console: 1 2 4096 ram2 console: 1 3 4096 ram3 console: 179 0 61440 mmcblk0 console: reboot console: / # reboot console: umount: devtmpfs busy - remounted read-only console: EXT4-fs (mmcblk0): re-mounted. Opts: (null) console: The system is going down NOW! console: Sent SIGTERM to all processes console: Sent SIGKILL to all processes console: Requesting system reboot console: reboot: Restarting system JOB TIME : 68.64 s Signed-off-by: Philippe Mathieu-Daudé --- tests/acceptance/boot_linux_console.py | 42 ++++++++++++++++++++++++++ 1 file changed, 42 insertions(+) diff --git a/tests/acceptance/boot_linux_console.py b/tests/acceptance/boot_linux_console.py index daabd47404..8179b45910 100644 --- a/tests/acceptance/boot_linux_console.py +++ b/tests/acceptance/boot_linux_console.py @@ -478,6 +478,48 @@ class BootLinuxConsole(Test): exec_command_and_wait_for_pattern(self, 'reboot', 'reboot: Restarting system') + def test_arm_orangepi_sd(self): + """ + :avocado: tags=arch:arm + :avocado: tags=machine:orangepi-pc + """ + deb_url = ('https://apt.armbian.com/pool/main/l/' + 'linux-4.20.7-sunxi/linux-image-dev-sunxi_5.75_armhf.deb') + deb_hash = '1334c29c44d984ffa05ed10de8c3361f33d78315' + deb_path = self.fetch_asset(deb_url, asset_hash=deb_hash) + kernel_path = self.extract_from_deb(deb_path, + '/boot/vmlinuz-4.20.7-sunxi') + dtb_path = '/usr/lib/linux-image-dev-sunxi/sun8i-h3-orangepi-pc.dtb' + dtb_path = self.extract_from_deb(deb_path, dtb_path) + rootfs_url = ('http://storage.kernelci.org/images/rootfs/buildroot/' + 'kci-2019.02/armel/base/rootfs.ext2.xz') + rootfs_hash = '692510cb625efda31640d1de0a8d60e26040f061' + rootfs_path_xz = self.fetch_asset(rootfs_url, asset_hash=rootfs_hash) + rootfs_path = os.path.join(self.workdir, 'rootfs.cpio') + archive.lzma_uncompress(rootfs_path_xz, rootfs_path) + + self.vm.set_machine('orangepi-pc') + self.vm.set_console() + kernel_command_line = (self.KERNEL_COMMON_COMMAND_LINE + + 'console=ttyS0,115200 ' + 'root=/dev/mmcblk0 rootwait rw ' + 'panic=-1 noreboot') + self.vm.add_args('-kernel', kernel_path, + '-dtb', dtb_path, + '-drive', 'file=' + rootfs_path + ',if=sd,format=raw', + '-append', kernel_command_line, + '-no-reboot') + self.vm.launch() + shell_ready = "/bin/sh: can't access tty; job control turned off" + self.wait_for_console_pattern(shell_ready) + + exec_command_and_wait_for_pattern(self, 'cat /proc/cpuinfo', + 'Allwinner sun8i Family') + exec_command_and_wait_for_pattern(self, 'cat /proc/partitions', + 'mmcblk0') + exec_command_and_wait_for_pattern(self, 'reboot', + 'reboot: Restarting system') + def test_s390x_s390_ccw_virtio(self): """ :avocado: tags=arch:s390x -- 2.21.0 From MAILER-DAEMON Tue Dec 17 16:50:02 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1ihKjC-00015c-HS for mharc-qemu-arm@gnu.org; Tue, 17 Dec 2019 16:50:02 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:59191) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ihKj9-000131-PK for qemu-arm@nongnu.org; Tue, 17 Dec 2019 16:50:00 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ihKj8-0003KP-Gu for qemu-arm@nongnu.org; Tue, 17 Dec 2019 16:49:59 -0500 Received: from act-mtaout3.csiro.au ([2405:b000:e00:257::7:39]:14830) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1ihKix-0003Dp-0v; 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Tue, 17 Dec 2019 21:49:35 +0000 Received: from MEAPR01MB3734.ausprd01.prod.outlook.com ([fe80::f88a:bacd:6866:d53f]) by MEAPR01MB3734.ausprd01.prod.outlook.com ([fe80::f88a:bacd:6866:d53f%6]) with mapi id 15.20.2538.019; Tue, 17 Dec 2019 21:49:35 +0000 From: "Chubb, Peter (Data61, Kensington NSW)" To: =?iso-8859-1?Q?Philippe_Mathieu-Daud=E9?= CC: "qemu-devel@nongnu.org" , "qemu-trivial@nongnu.org" , =?iso-8859-1?Q?C=E9dric_Le_Goater?= , Max Reitz , Fam Zheng , Peter Chubb , "qemu-arm@nongnu.org" , Joel Stanley , Peter Maydell , Mark Cave-Ayland , Paolo Bonzini , Kevin Wolf , "Jason Wang" , "qemu-block@nongnu.org" , Andrew Jeffery , Gerd Hoffmann , "Hannes Reinecke" Subject: Re: [PATCH 0/6] Fix more GCC9 -O3 warnings Thread-Topic: [PATCH 0/6] Fix more GCC9 -O3 warnings Thread-Index: AQHVtQAZ6Ml9ApUzXk+fEju4sv41Uqe+3bwA Date: Tue, 17 Dec 2019 21:49:35 +0000 Message-ID: <84fthiaahd.wl-Peter.Chubb@data61.csiro.au> References: <20191217173252.4672-1-philmd@redhat.com> In-Reply-To: <20191217173252.4672-1-philmd@redhat.com> Accept-Language: en-AU, en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: authentication-results: spf=none (sender IP is ) smtp.mailfrom=Peter.Chubb@data61.csiro.au; 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charset="iso-8859-1" Content-ID: Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-MS-Exchange-CrossTenant-Network-Message-Id: a43f49b0-2c64-47c6-c025-08d7833b0201 X-MS-Exchange-CrossTenant-originalarrivaltime: 17 Dec 2019 21:49:35.5793 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 0fe05593-19ac-4f98-adbf-0375fce7f160 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: RVDyJtkhXJY0zrm+o+Lhpw4wsozuQuTvGQMhriD/BvLNSBdyGo+lVx1/VWKaKJaT X-MS-Exchange-Transport-CrossTenantHeadersStamped: MEAPR01MB3157 X-OriginatorOrg: data61.csiro.au X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2405:b000:e00:257::7:39 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 17 Dec 2019 21:50:01 -0000 >>>>> "Philippe" =3D=3D Philippe Mathieu-Daud=E9 writes= : Philippe> Fix some trivial warnings when building with -O3. For compatibility with lint and other older checkers, it'd be good to keep this as /* FALLTHROUGH */ (which gcc should accept according to its manual). Fixing the comments' placement is a different matter, and should be done. Seems to me that until gcc started warning for this, noone had actually run a checker, and the comments were just for human info. Peter C --=20 Dr Peter Chubb Tel: +61 2 9490 5852 http://ts.data61.csiro.au/ Trustworthy Systems Group Data61 (formerly NICTA)= From MAILER-DAEMON Tue Dec 17 17:23:24 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1ihLFT-0002ks-VI for mharc-qemu-arm@gnu.org; Tue, 17 Dec 2019 17:23:23 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:48527) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ihJzN-0007HT-GH for qemu-arm@nongnu.org; Tue, 17 Dec 2019 16:02:42 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ihJzM-0006u3-2C for qemu-arm@nongnu.org; Tue, 17 Dec 2019 16:02:41 -0500 Received: from mail.dornerworks.com ([12.207.209.150]:48067 helo=webmail.dornerworks.com) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ihJzL-0006no-QA; Tue, 17 Dec 2019 16:02:40 -0500 From: Jeff Kubascik To: Peter Maydell , , CC: Jarvis Roach , Stewart Hildebrand Subject: [PATCH] target/arm: fix IL bit for data abort exceptions Date: Tue, 17 Dec 2019 16:02:30 -0500 Message-ID: <20191217210230.99559-1-jeff.kubascik@dornerworks.com> X-Mailer: git-send-email 2.17.1 MIME-Version: 1.0 Content-Type: text/plain X-Originating-IP: [172.27.13.171] X-ClientProxiedBy: Mcbain.dw.local (172.27.1.45) To Mcbain.dw.local (172.27.1.45) X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 12.207.209.150 X-Mailman-Approved-At: Tue, 17 Dec 2019 17:23:22 -0500 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 17 Dec 2019 21:02:42 -0000 The Instruction Length bit of the Exception Syndrome Register was fixed to 1 for data aborts. This bit is used by the Xen hypervisor to determine how to increment the program counter after a mmio handler is successful and returns control back to the guest virtual machine. With this value fixed to 1, the hypervisor would always increment the program counter by 0x4. This is a problem when the guest virtual machine is using Thumb instructions, as the instruction that caused the exception may be 16 bits. This adds a is_16bit flag to the disassembler context to keep track of the current instruction length. For load/store instructions, the instruction length bit is stored with the instruction syndrome data, to be later used if the data abort occurs. Signed-off-by: Jeff Kubascik --- Hello, I am using the ARMv8 version of QEMU to run the Xen hypervisor with a guest virtual machine compiled for AArch32/Thumb code. I have noticed that when the guest VM tries to write to an emulated PL011 register, the mmio handler always increments the program counter by 4, even if the store instruction that caused the exception was a 16-bit Thumb instruction. I have traced this back to the IL bit in the ESR_EL2 register. Xen uses the IL bit to determine how to increment the program counter. However, QEMU does not correctly emulate this bit, always setting it to 1 (32-bit instruction). The above patch works for my setup. However, I am not very familiar with the QEMU code base, so it may not be the best way to do it, or even be correct. Any feedback would be greatly appreciated. Sincerely, Jeff Kubascik --- target/arm/tlb_helper.c | 2 +- target/arm/translate-a64.c | 1 + target/arm/translate.c | 4 +++- target/arm/translate.h | 2 ++ 4 files changed, 7 insertions(+), 2 deletions(-) diff --git a/target/arm/tlb_helper.c b/target/arm/tlb_helper.c index 5feb312941..e63f8bda29 100644 --- a/target/arm/tlb_helper.c +++ b/target/arm/tlb_helper.c @@ -44,7 +44,7 @@ static inline uint32_t merge_syn_data_abort(uint32_t template_syn, syn = syn_data_abort_with_iss(same_el, 0, 0, 0, 0, 0, ea, 0, s1ptw, is_write, fsc, - false); + true); /* Merge the runtime syndrome with the template syndrome. */ syn |= template_syn; } diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index d4bebbe629..a3c618fdd9 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -14045,6 +14045,7 @@ static void disas_a64_insn(CPUARMState *env, DisasContext *s) s->pc_curr = s->base.pc_next; insn = arm_ldl_code(env, s->base.pc_next, s->sctlr_b); s->insn = insn; + s->is_16bit = false; s->base.pc_next += 4; s->fp_access_checked = false; diff --git a/target/arm/translate.c b/target/arm/translate.c index 2b6c1f91bf..300480f1b7 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -8555,7 +8555,7 @@ static ISSInfo make_issinfo(DisasContext *s, int rd, bool p, bool w) /* ISS not valid if writeback */ if (p && !w) { - ret = rd; + ret = rd | (s->is_16bit ? ISSIs16Bit : 0); } else { ret = ISSInvalid; } @@ -11057,6 +11057,7 @@ static void arm_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu) dc->pc_curr = dc->base.pc_next; insn = arm_ldl_code(env, dc->base.pc_next, dc->sctlr_b); dc->insn = insn; + dc->is_16bit = false; dc->base.pc_next += 4; disas_arm_insn(dc, insn); @@ -11126,6 +11127,7 @@ static void thumb_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu) dc->pc_curr = dc->base.pc_next; insn = arm_lduw_code(env, dc->base.pc_next, dc->sctlr_b); is_16bit = thumb_insn_is_16bit(dc, dc->base.pc_next, insn); + dc->is_16bit = is_16bit; dc->base.pc_next += 2; if (!is_16bit) { uint32_t insn2 = arm_lduw_code(env, dc->base.pc_next, dc->sctlr_b); diff --git a/target/arm/translate.h b/target/arm/translate.h index b837b7fcbf..c16f434477 100644 --- a/target/arm/translate.h +++ b/target/arm/translate.h @@ -14,6 +14,8 @@ typedef struct DisasContext { target_ulong pc_curr; target_ulong page_start; uint32_t insn; + /* 16-bit instruction flag */ + bool is_16bit; /* Nonzero if this instruction has been conditionally skipped. */ int condjmp; /* The label that will be jumped to when the instruction is skipped. */ -- 2.17.1 From MAILER-DAEMON Tue Dec 17 17:55:43 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1ihLkl-0003YE-LQ for mharc-qemu-arm@gnu.org; Tue, 17 Dec 2019 17:55:43 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:48032) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ihLkj-0003Xb-G0 for qemu-arm@nongnu.org; Tue, 17 Dec 2019 17:55:42 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ihLke-0006JK-LO for qemu-arm@nongnu.org; Tue, 17 Dec 2019 17:55:41 -0500 Received: from wout4-smtp.messagingengine.com ([64.147.123.20]:38723) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1ihLke-0006Cv-1W; Tue, 17 Dec 2019 17:55:36 -0500 Received: from compute4.internal (compute4.nyi.internal [10.202.2.44]) by mailout.west.internal (Postfix) with ESMTP id CE2E842D; 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Tue, 17 Dec 2019 17:55:31 -0500 (EST) X-Mailer: MessagingEngine.com Webmail Interface User-Agent: Cyrus-JMAP/3.1.7-689-g5a57b82-fmstable-20191216v1 Mime-Version: 1.0 Message-Id: In-Reply-To: References: Date: Wed, 18 Dec 2019 09:27:14 +1030 From: "Andrew Jeffery" To: "Peter Maydell" Cc: qemu-arm , =?UTF-8?Q?C=C3=A9dric_Le_Goater?= , "Joel Stanley" , "QEMU Developers" , =?UTF-8?Q?Philippe_Mathieu-Daud=C3=A9?= Subject: =?UTF-8?Q?Re:_[PATCH_v3_0/4]_Expose_GT_CNTFRQ_as_a_CPU_property_to_suppo?= =?UTF-8?Q?rt_AST2600?= Content-Type: text/plain X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 64.147.123.20 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 17 Dec 2019 22:55:43 -0000 On Wed, 18 Dec 2019, at 01:55, Peter Maydell wrote: > On Fri, 13 Dec 2019 at 05:48, Andrew Jeffery wrote: > > > > Hello, > > > > This is a v3 of the belated follow-up from a few of my earlier attempts to fix > > up the ARM generic timer for correct behaviour on the ASPEED AST2600 SoC. The > > AST2600 clocks the generic timer at the rate of HPLL, which is configured to > > 1125MHz. This is significantly quicker than the currently hard-coded generic > > timer rate of 62.5MHz and so we see "sticky" behaviour in the guest. > > > > v2 can be found here: > > > > https://patchwork.ozlabs.org/cover/1203474/ > > > > Changes since v2: > > > > * Address some minor review comments from Philippe and add tags > > > > Changes since v1: > > > > * Fix a user mode build failure from partial renaming of gt_cntfrq_period_ns() > > * Add tags from Cedric and Richard > > > > Please review. > > > > Andrew > > > > Andrew Jeffery (4): > > target/arm: Remove redundant scaling of nexttick > > target/arm: Abstract the generic timer frequency > > target/arm: Prepare generic timer for per-platform CNTFRQ > > ast2600: Configure CNTFRQ at 1125MHz > > > > > Applied to target-arm.next, thanks. Thanks for your feedback throughout. Andrew From MAILER-DAEMON Tue Dec 17 20:03:29 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1ihNkP-0005Jr-1j for mharc-qemu-arm@gnu.org; Tue, 17 Dec 2019 20:03:29 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:48614) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ihNkL-0005Il-Fi for qemu-arm@nongnu.org; Tue, 17 Dec 2019 20:03:26 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ihNkI-000059-Bi for qemu-arm@nongnu.org; Tue, 17 Dec 2019 20:03:24 -0500 Received: from mail-pl1-x641.google.com ([2607:f8b0:4864:20::641]:44121) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ihNkI-0008V9-50 for qemu-arm@nongnu.org; Tue, 17 Dec 2019 20:03:22 -0500 Received: by mail-pl1-x641.google.com with SMTP id az3so171968plb.11 for ; Tue, 17 Dec 2019 17:03:21 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=subject:to:cc:references:from:message-id:date:user-agent :mime-version:in-reply-to:content-language:content-transfer-encoding; bh=qDktnqJFILHEe9UmAzxJWXQjAQ6RxhjYlF1ehUzBsNk=; b=lJUv67jzPq4LKQonclJjvnnyhUhhAIy9tGQrdLTOsjQxF7iZbkt84zeRZhP3d1tBcv k85ICsohSFopESlOZuQjOItYNN1d94TIG/yKM6l2mIwGYpuSfB2Z6cQOxcBEIZtACicG 12Ilzr6J7TVL8yLGG29S2Q9Ynpk6q8u/BO2UB6s+k1duiyuZ+4gP4TBOx+tZXL2SOqw8 ZzksMZvD7bPG4LvzW069p/Ls1+f/6Oo3POaJnVyLU3Pz/nXgAUUJf+yenw5RB+l0JWc7 eMXC8Jn26fDDq7uqzvXsLQ6IiFuQWdRubbUAMI+FF9vDj8TA+zkDnYn4u7ln9WHeV5d/ ozwA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:subject:to:cc:references:from:message-id:date :user-agent:mime-version:in-reply-to:content-language :content-transfer-encoding; bh=qDktnqJFILHEe9UmAzxJWXQjAQ6RxhjYlF1ehUzBsNk=; b=lSTlYXns42pnLGrAd4PbROHnZ09GLkHSq0xXQ79E0/OyYgyG8VZzHI1/RJj0RcfeIV ojoRpKifHU3xR557ZpUInyKnFxiy3Xx8+jA8KB7GVrjVQyheVzdfh5ujSBSJ1dlteq8G ZoZs5v2gjIRCeMH1UI0CEA/6mrqZrUyYVnk/Aq18EoCCoGx2M+yJfCOu6eLTsJkkYmyg CAkZqC9Qd5FbwIZlWmMNWDmoM8rg6K8f8hdiTSYnhvqR2Futz3jPH0cPrIU24zdegnkn TKdN4sSg722fTCZxUoSSeE1q0hVzYvjZwxtI2X+YhDJJeeTz/rnqaAJOuTWVulFNeXrv OBLA== X-Gm-Message-State: APjAAAWcu1D2GAdYghYRxiI/TTuVii0aa2a+I0kSlXY8gGNQPuVXb4uf I35KviDDs+iPnGmC6VQma5Nkew== X-Google-Smtp-Source: APXvYqxnZmkqQRgcxw31QdkFyaBeasPChr58EeAao/NwDX9By51ZylYy6wOPucD7LXGKKnGCIl/GTg== X-Received: by 2002:a17:90a:26ec:: with SMTP id m99mr279651pje.130.1576631000487; Tue, 17 Dec 2019 17:03:20 -0800 (PST) Received: from ?IPv6:2605:e000:c74f:dc00:6838:d2b2:17e2:8445? ([2605:e000:c74f:dc00:6838:d2b2:17e2:8445]) by smtp.gmail.com with ESMTPSA id o8sm177926pjo.7.2019.12.17.17.03.18 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 17 Dec 2019 17:03:19 -0800 (PST) Subject: Re: [PATCH] target/arm: fix IL bit for data abort exceptions To: Jeff Kubascik , Peter Maydell , qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Stewart Hildebrand , Jarvis Roach References: <20191217210230.99559-1-jeff.kubascik@dornerworks.com> From: Richard Henderson Message-ID: <7a274247-e593-5828-73f8-2042971e8633@linaro.org> Date: Tue, 17 Dec 2019 15:03:16 -1000 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.2.2 MIME-Version: 1.0 In-Reply-To: <20191217210230.99559-1-jeff.kubascik@dornerworks.com> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 7bit X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::641 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 18 Dec 2019 01:03:26 -0000 On 12/17/19 11:02 AM, Jeff Kubascik wrote: > diff --git a/target/arm/tlb_helper.c b/target/arm/tlb_helper.c > index 5feb312941..e63f8bda29 100644 > --- a/target/arm/tlb_helper.c > +++ b/target/arm/tlb_helper.c > @@ -44,7 +44,7 @@ static inline uint32_t merge_syn_data_abort(uint32_t template_syn, > syn = syn_data_abort_with_iss(same_el, > 0, 0, 0, 0, 0, > ea, 0, s1ptw, is_write, fsc, > - false); > + true); > /* Merge the runtime syndrome with the template syndrome. */ > syn |= template_syn; This doesn't look correct. Surely the IL bit should come from template_syn? > diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c > index d4bebbe629..a3c618fdd9 100644 > --- a/target/arm/translate-a64.c > +++ b/target/arm/translate-a64.c > @@ -14045,6 +14045,7 @@ static void disas_a64_insn(CPUARMState *env, DisasContext *s) > s->pc_curr = s->base.pc_next; > insn = arm_ldl_code(env, s->base.pc_next, s->sctlr_b); > s->insn = insn; > + s->is_16bit = false; > s->base.pc_next += 4; Should not be necessary, as the field is not read along any a64 path. (Also, while it's not yet in master, there's a patch on list that zero initializes the entire structure.) > diff --git a/target/arm/translate.c b/target/arm/translate.c > index 2b6c1f91bf..300480f1b7 100644 > --- a/target/arm/translate.c > +++ b/target/arm/translate.c > @@ -8555,7 +8555,7 @@ static ISSInfo make_issinfo(DisasContext *s, int rd, bool p, bool w) > > /* ISS not valid if writeback */ > if (p && !w) { > - ret = rd; > + ret = rd | (s->is_16bit ? ISSIs16Bit : 0); > } else { > ret = ISSInvalid; > } > @@ -11057,6 +11057,7 @@ static void arm_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu) > dc->pc_curr = dc->base.pc_next; > insn = arm_ldl_code(env, dc->base.pc_next, dc->sctlr_b); > dc->insn = insn; > + dc->is_16bit = false; > dc->base.pc_next += 4; > disas_arm_insn(dc, insn); > > @@ -11126,6 +11127,7 @@ static void thumb_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu) > dc->pc_curr = dc->base.pc_next; > insn = arm_lduw_code(env, dc->base.pc_next, dc->sctlr_b); > is_16bit = thumb_insn_is_16bit(dc, dc->base.pc_next, insn); > + dc->is_16bit = is_16bit; > dc->base.pc_next += 2; > if (!is_16bit) { > uint32_t insn2 = arm_lduw_code(env, dc->base.pc_next, dc->sctlr_b); > diff --git a/target/arm/translate.h b/target/arm/translate.h > index b837b7fcbf..c16f434477 100644 > --- a/target/arm/translate.h > +++ b/target/arm/translate.h > @@ -14,6 +14,8 @@ typedef struct DisasContext { > target_ulong pc_curr; > target_ulong page_start; > uint32_t insn; > + /* 16-bit instruction flag */ > + bool is_16bit; > /* Nonzero if this instruction has been conditionally skipped. */ > int condjmp; > /* The label that will be jumped to when the instruction is skipped. */ The rest of this looks both correct and necessary. r~ From MAILER-DAEMON Tue Dec 17 22:45:53 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1ihQHZ-0001UV-Ge for mharc-qemu-arm@gnu.org; Tue, 17 Dec 2019 22:45:53 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:46973) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ihQHX-0001SM-BX for qemu-arm@nongnu.org; Tue, 17 Dec 2019 22:45:52 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ihQHW-0003jo-7H for qemu-arm@nongnu.org; Tue, 17 Dec 2019 22:45:51 -0500 Received: from mail-pg1-x543.google.com ([2607:f8b0:4864:20::543]:45958) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ihQHW-0003hu-0d for qemu-arm@nongnu.org; Tue, 17 Dec 2019 22:45:50 -0500 Received: by mail-pg1-x543.google.com with SMTP id b9so463699pgk.12 for ; Tue, 17 Dec 2019 19:45:49 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=subject:to:cc:references:from:message-id:date:user-agent :mime-version:in-reply-to:content-language:content-transfer-encoding; bh=bGfARsdCLz5Bkj4bxAAz0ZLKVs1p1DoNYlG/3BcpDrQ=; b=blXkoP5I8XVTLn9OHLlMkkqo+8h9Wd+G48X2meg7HYdfqneVVvsLgXlto7tKLCWxam QBoKsS+S12w7avHTOwV5PWm66kx1KK/ka02jJM26+kZvrDoa8WJLvEmZkYlesH/TJvJW UsaIG2MRihbh7tt7b0khHpbBPO40Zv/sHhm+rT3JgjH65Z8n71PWy5XGY8woGsvG+is0 khzX/866sULBnSrrbiUwic36PI0c+L1Q54RSZqDu5kZ151HBjGaM8a85IGwJg0ZcBgCn QIAleerw/dy8GM4soIzjikNYOPrd3gQaouQkmGFWHnIdFBa5m+UIJt4OJ7v8JOg0vJg9 oAnQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:subject:to:cc:references:from:message-id:date :user-agent:mime-version:in-reply-to:content-language :content-transfer-encoding; bh=bGfARsdCLz5Bkj4bxAAz0ZLKVs1p1DoNYlG/3BcpDrQ=; b=E9ieRmVg/jvssrga9mnrRi57wqNDuLkUIpxVEqRBywhjJKinWl6eJFvQYFgt1kidrW aqQAyhcl8zkWpZNp34BQ8pk4nqse3dtDMYzhRdubOFVrNUvIBzEpQGTFYJDVZhRETuj8 QOdH1x2urDsuAq/O+TUzoJSpsvVvcl45Bq3EfU3J/LcdB1FPsRUNlSmVLy30to3eQ3Av ljGjybhdpj4tYRzGH+yx4LUxXRPqQxqRC2FWKoHvjBte0Da8hqqu30ngxg3SqKaRXE6E ESRB2vLCgjkpAkDFdhFQuUfGDmVYwb0JNfChsSWTR814ige+UedErZHhF1jQxjLSatSK gUdw== X-Gm-Message-State: APjAAAWY4yqlGaqoPxPBvUVK3afd5LdC1cv0ctWH97BxE30BK79mCKAy ILvawpXbmYupV8LwQ3xtLuggSA== X-Google-Smtp-Source: APXvYqyRnnFSqx+UTMvs81vZfubBhd+o+BdbF2S46aqTYgPqURfT3vZeFqmEmLNRXHA8yEoPeEW5Bg== X-Received: by 2002:a63:e80d:: with SMTP id s13mr475383pgh.134.1576640748924; Tue, 17 Dec 2019 19:45:48 -0800 (PST) Received: from ?IPv6:2605:e000:c74f:dc00:6838:d2b2:17e2:8445? ([2605:e000:c74f:dc00:6838:d2b2:17e2:8445]) by smtp.gmail.com with ESMTPSA id a6sm567390pgg.25.2019.12.17.19.45.47 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 17 Dec 2019 19:45:48 -0800 (PST) Subject: Re: [PATCH 3/6] hw/net/imx_fec: Rewrite fall through comments To: =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= , qemu-devel@nongnu.org Cc: Peter Maydell , qemu-trivial@nongnu.org, Jason Wang , qemu-arm@nongnu.org, Peter Chubb References: <20191217173425.5082-1-philmd@redhat.com> <20191217173425.5082-4-philmd@redhat.com> From: Richard Henderson Message-ID: Date: Tue, 17 Dec 2019 17:45:45 -1000 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.2.2 MIME-Version: 1.0 In-Reply-To: <20191217173425.5082-4-philmd@redhat.com> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 8bit X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::543 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 18 Dec 2019 03:45:52 -0000 On 12/17/19 7:34 AM, Philippe Mathieu-Daudé wrote: > GCC9 is confused by this comment when building with CFLAG > -Wimplicit-fallthrough=2: > > hw/net/imx_fec.c: In function ‘imx_eth_write’: > hw/net/imx_fec.c:906:12: error: this statement may fall through [-Werror=implicit-fallthrough=] > 906 | if (unlikely(single_tx_ring)) { > | ^ > hw/net/imx_fec.c:912:5: note: here > 912 | case ENET_TDAR: /* FALLTHROUGH */ > | ^~~~ > cc1: all warnings being treated as errors > > Rewrite the comments in the correct place, using 'fall through' > which is recognized by GCC and static analyzers. > > Signed-off-by: Philippe Mathieu-Daudé > --- > Cc: Peter Chubb > Cc: Peter Maydell > Cc: Jason Wang > Cc: qemu-arm@nongnu.org > --- > hw/net/imx_fec.c | 8 +++++--- > 1 file changed, 5 insertions(+), 3 deletions(-) Reviewed-by: Richard Henderson r~ From MAILER-DAEMON Tue Dec 17 22:47:21 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1ihQIy-0002ck-Us for mharc-qemu-arm@gnu.org; Tue, 17 Dec 2019 22:47:20 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:52189) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ihQIu-0002Xi-PP for qemu-arm@nongnu.org; Tue, 17 Dec 2019 22:47:18 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ihQIq-0005ZK-DC for qemu-arm@nongnu.org; Tue, 17 Dec 2019 22:47:14 -0500 Received: from szxga07-in.huawei.com ([45.249.212.35]:59690 helo=huawei.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1ihQIl-00051v-52; Tue, 17 Dec 2019 22:47:09 -0500 Received: from DGGEMS412-HUB.china.huawei.com (unknown [172.30.72.60]) by Forcepoint Email with ESMTP id 6ABE29A27480C7A027BF; Wed, 18 Dec 2019 11:46:44 +0800 (CST) Received: from [127.0.0.1] (10.173.222.27) by DGGEMS412-HUB.china.huawei.com (10.3.19.212) with Microsoft SMTP Server id 14.3.439.0; Wed, 18 Dec 2019 11:46:36 +0800 Subject: Re: [kvm-unit-tests PATCH 05/16] arm/arm64: ITS: Introspection tests To: Eric Auger , , , , , , CC: , , , , References: <20191216140235.10751-1-eric.auger@redhat.com> <20191216140235.10751-6-eric.auger@redhat.com> From: Zenghui Yu Message-ID: Date: Wed, 18 Dec 2019 11:46:34 +0800 User-Agent: Mozilla/5.0 (Windows NT 10.0; WOW64; rv:68.0) Gecko/20100101 Thunderbird/68.2.0 MIME-Version: 1.0 In-Reply-To: <20191216140235.10751-6-eric.auger@redhat.com> Content-Type: text/plain; charset="utf-8"; format=flowed Content-Language: en-US Content-Transfer-Encoding: 7bit X-Originating-IP: [10.173.222.27] X-CFilter-Loop: Reflected X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 45.249.212.35 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 18 Dec 2019 03:47:18 -0000 Hi Eric, I have to admit that this is the first time I've looked into the kvm-unit-tests code, so only some minor comments inline :) On 2019/12/16 22:02, Eric Auger wrote: > Detect the presence of an ITS as part of the GICv3 init > routine, initialize its base address and read few registers > the IIDR, the TYPER to store its dimensioning parameters. > > This is our first ITS test, belonging to a new "its" group. > > Signed-off-by: Eric Auger [...] > diff --git a/lib/arm/asm/gic-v3-its.h b/lib/arm/asm/gic-v3-its.h > new file mode 100644 > index 0000000..2ce483e > --- /dev/null > +++ b/lib/arm/asm/gic-v3-its.h > @@ -0,0 +1,116 @@ > +/* > + * All ITS* defines are lifted from include/linux/irqchip/arm-gic-v3.h > + * > + * Copyright (C) 2016, Red Hat Inc, Andrew Jones > + * > + * This work is licensed under the terms of the GNU LGPL, version 2. > + */ > +#ifndef _ASMARM_GIC_V3_ITS_H_ > +#define _ASMARM_GIC_V3_ITS_H_ > + > +#ifndef __ASSEMBLY__ > + > +#define GITS_CTLR 0x0000 > +#define GITS_IIDR 0x0004 > +#define GITS_TYPER 0x0008 > +#define GITS_CBASER 0x0080 > +#define GITS_CWRITER 0x0088 > +#define GITS_CREADR 0x0090 > +#define GITS_BASER 0x0100 > + > +#define GITS_TYPER_PLPIS (1UL << 0) > +#define GITS_TYPER_IDBITS_SHIFT 8 > +#define GITS_TYPER_DEVBITS_SHIFT 13 > +#define GITS_TYPER_DEVBITS(r) ((((r) >> GITS_TYPER_DEVBITS_SHIFT) & 0x1f) + 1) > +#define GITS_TYPER_PTA (1UL << 19) > +#define GITS_TYPER_HWCOLLCNT_SHIFT 24 > + > +#define GITS_CTLR_ENABLE (1U << 0) > + > +#define GITS_CBASER_VALID (1UL << 63) > +#define GITS_CBASER_SHAREABILITY_SHIFT (10) > +#define GITS_CBASER_INNER_CACHEABILITY_SHIFT (59) > +#define GITS_CBASER_OUTER_CACHEABILITY_SHIFT (53) > +#define GITS_CBASER_SHAREABILITY_MASK \ > + GIC_BASER_SHAREABILITY(GITS_CBASER, SHAREABILITY_MASK) > +#define GITS_CBASER_INNER_CACHEABILITY_MASK \ > + GIC_BASER_CACHEABILITY(GITS_CBASER, INNER, MASK) > +#define GITS_CBASER_OUTER_CACHEABILITY_MASK \ > + GIC_BASER_CACHEABILITY(GITS_CBASER, OUTER, MASK) > +#define GITS_CBASER_CACHEABILITY_MASK GITS_CBASER_INNER_CACHEABILITY_MASK > + > +#define GITS_CBASER_InnerShareable \ > + GIC_BASER_SHAREABILITY(GITS_CBASER, InnerShareable) > + > +#define GITS_CBASER_nCnB GIC_BASER_CACHEABILITY(GITS_CBASER, INNER, nCnB) > +#define GITS_CBASER_nC GIC_BASER_CACHEABILITY(GITS_CBASER, INNER, nC) > +#define GITS_CBASER_RaWt GIC_BASER_CACHEABILITY(GITS_CBASER, INNER, RaWt) > +#define GITS_CBASER_RaWb GIC_BASER_CACHEABILITY(GITS_CBASER, INNER, RaWt) s/RaWt/RaWb/ > +#define GITS_CBASER_WaWt GIC_BASER_CACHEABILITY(GITS_CBASER, INNER, WaWt) > +#define GITS_CBASER_WaWb GIC_BASER_CACHEABILITY(GITS_CBASER, INNER, WaWb) > +#define GITS_CBASER_RaWaWt GIC_BASER_CACHEABILITY(GITS_CBASER, INNER, RaWaWt) > +#define GITS_CBASER_RaWaWb GIC_BASER_CACHEABILITY(GITS_CBASER, INNER, RaWaWb) > + > +#define GITS_BASER_NR_REGS 8 > + > +#define GITS_BASER_VALID (1UL << 63) > +#define GITS_BASER_INDIRECT (1ULL << 62) > + > +#define GITS_BASER_INNER_CACHEABILITY_SHIFT (59) > +#define GITS_BASER_OUTER_CACHEABILITY_SHIFT (53) > +#define GITS_BASER_CACHEABILITY_MASK 0x7 > + > +#define GITS_BASER_nCnB GIC_BASER_CACHEABILITY(GITS_BASER, INNER, nCnB) > + > +#define GITS_BASER_TYPE_SHIFT (56) > +#define GITS_BASER_TYPE(r) (((r) >> GITS_BASER_TYPE_SHIFT) & 7) > +#define GITS_BASER_ENTRY_SIZE_SHIFT (48) > +#define GITS_BASER_ENTRY_SIZE(r) ((((r) >> GITS_BASER_ENTRY_SIZE_SHIFT) & 0x1f) + 1) > +#define GITS_BASER_SHAREABILITY_SHIFT (10) > +#define GITS_BASER_InnerShareable \ > + GIC_BASER_SHAREABILITY(GITS_BASER, InnerShareable) > +#define GITS_BASER_PAGE_SIZE_SHIFT (8) > +#define GITS_BASER_PAGE_SIZE_4K (0UL << GITS_BASER_PAGE_SIZE_SHIFT) > +#define GITS_BASER_PAGE_SIZE_16K (1UL << GITS_BASER_PAGE_SIZE_SHIFT) > +#define GITS_BASER_PAGE_SIZE_64K (2UL << GITS_BASER_PAGE_SIZE_SHIFT) > +#define GITS_BASER_PAGE_SIZE_MASK (3UL << GITS_BASER_PAGE_SIZE_SHIFT) > +#define GITS_BASER_PAGES_MAX 256 > +#define GITS_BASER_PAGES_SHIFT (0) > +#define GITS_BASER_NR_PAGES(r) (((r) & 0xff) + 1) > +#define GITS_BASER_PHYS_ADDR_MASK 0xFFFFFFFFF000 > + > +#define GITS_BASER_TYPE_NONE 0 > +#define GITS_BASER_TYPE_DEVICE 1 > +#define GITS_BASER_TYPE_VCPU 2 > +#define GITS_BASER_TYPE_CPU 3 '3' is one of the reserved values of the GITS_BASER.Type field, and what do we expect with a "GITS_BASER_TYPE_CPU" table type? ;-) I think we can copy (and might update in the future) all these macros against the latest Linux kernel. > +#define GITS_BASER_TYPE_COLLECTION 4 > + > +#define ITS_FLAGS_CMDQ_NEEDS_FLUSHING (1ULL << 0) > + > +struct its_typer { > + unsigned int ite_size; > + unsigned int eventid_bits; > + unsigned int deviceid_bits; > + unsigned int collid_bits; > + unsigned int hw_collections; > + bool pta; > + bool cil; > + bool cct; > + bool phys_lpi; > + bool virt_lpi; > +}; > + > +struct its_data { > + void *base; > + struct its_typer typer; > +}; > + > +extern struct its_data its_data; > + > +#define gicv3_its_base() (its_data.base) > + > +extern void its_parse_typer(void); > +extern void its_init(void); > + > +#endif /* !__ASSEMBLY__ */ > +#endif /* _ASMARM_GIC_V3_ITS_H_ */ > diff --git a/lib/arm/asm/gic.h b/lib/arm/asm/gic.h > index 55dd84b..b44da9c 100644 > --- a/lib/arm/asm/gic.h > +++ b/lib/arm/asm/gic.h > @@ -40,6 +40,7 @@ > > #include > #include > +#include > > #define PPI(irq) ((irq) + 16) > #define SPI(irq) ((irq) + GIC_FIRST_SPI) > diff --git a/lib/arm/gic-v3-its.c b/lib/arm/gic-v3-its.c > new file mode 100644 > index 0000000..34f4d0e > --- /dev/null > +++ b/lib/arm/gic-v3-its.c > @@ -0,0 +1,41 @@ > +/* > + * Copyright (C) 2016, Red Hat Inc, Eric Auger > + * > + * This work is licensed under the terms of the GNU LGPL, version 2. > + */ > +#include > + > +struct its_data its_data; > + > +void its_parse_typer(void) > +{ > + u64 typer = readq(gicv3_its_base() + GITS_TYPER); > + > + its_data.typer.ite_size = ((typer >> 4) & 0xf) + 1; > + its_data.typer.pta = typer & GITS_TYPER_PTA; > + its_data.typer.eventid_bits = > + ((typer >> GITS_TYPER_IDBITS_SHIFT) & 0x1f) + 1; > + its_data.typer.deviceid_bits = GITS_TYPER_DEVBITS(typer) + 1; No need to '+1'. As GITS_TYPER_DEVBITS already helps us to calculate the implemented DeviceID bits. > + > + its_data.typer.cil = (typer >> 36) & 0x1; > + if (its_data.typer.cil) > + its_data.typer.collid_bits = ((typer >> 32) & 0xf) + 1; > + else > + its_data.typer.collid_bits = 16; > + > + its_data.typer.hw_collections = > + (typer >> GITS_TYPER_HWCOLLCNT_SHIFT) & 0xff; > + > + its_data.typer.cct = typer & 0x4; > + its_data.typer.virt_lpi = typer & 0x2; > + its_data.typer.phys_lpi = typer & GITS_TYPER_PLPIS; Personally, mix using of GITS_TYPER_* macros and some magic constants to parse the TYPER makes it a bit difficult to review the code. Maybe we can have more such kinds of macros in the header file and get rid of all hardcoded numbers? Thanks, Zenghui From MAILER-DAEMON Tue Dec 17 23:04:50 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1ihQZu-0008Tu-C0 for mharc-qemu-arm@gnu.org; Tue, 17 Dec 2019 23:04:50 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:49648) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ihQZq-0008PG-NZ for qemu-arm@nongnu.org; Tue, 17 Dec 2019 23:04:48 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ihQZo-0007zs-Os for qemu-arm@nongnu.org; Tue, 17 Dec 2019 23:04:46 -0500 Received: from mail-lf1-x142.google.com ([2a00:1450:4864:20::142]:39504) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ihQZj-0007sJ-Jz; Tue, 17 Dec 2019 23:04:40 -0500 Received: by mail-lf1-x142.google.com with SMTP id y1so610410lfb.6; Tue, 17 Dec 2019 20:04:39 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc:content-transfer-encoding; bh=Gn5u53AcHsOLz5ep22Df1IpTEhdGFxnRJsa3OabeLBc=; b=YGDg11vwcL+UhzjCHOiuSKvx265s/lEQvYo3cIesUfstc1TMTDUMkMiWmpyTz7Mele hKSFvocS2uhzd2UCm6SS7bD2P7QETvd9rruaqSM8iKWYGzOLE+jTnwTBNPzWI1BegX5g wFsLyUtzckrxrCx9pYYAxGDens6LyE5zJkCF4unfe0hcyeVWuRxEYm2N17Bu5E/8OieJ Emlaiog6kkWMXwHYXxlIttymvudvvr8eL/t85T4+kW4ZeEFcXXaGIitO4w1zdMqIhurM znxRssPERJMwK3Q9wVznR1b9u8uKHCcr9xzP9NZW+/Q/X4LhWZKSblXAA58ABDEaasVG F9Uw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc:content-transfer-encoding; bh=Gn5u53AcHsOLz5ep22Df1IpTEhdGFxnRJsa3OabeLBc=; b=LkE2LZqrClCQzHwV5sBPGzRYDuDO6yUvctZjQPaZS92MFiYp+D4wY4Y4uu2wqvIa8N Q1Wd7828k+4jUimF423U+5gV8gb6ZUq1DBhdSFUGac+vE2vzsYvE18EDVN37zW6NMZaA n9F44z/f3ihmXDFS5eKvrZwdR54YUa6wGXC+Pc1xwHj7mset8se9nQWovydJs0C+qGs2 Sd5jA0MdHTTGY6R1cIFpn2XB4BH87q/48vWob0MXn1606+wR99AHRL0Mx05+5Pm+rmc1 ycnQIZrQi+EU90+oVVI04NU+H6g+D37/2zGw86R8TzhZgGP7qu+xGpfujRs2gR1jgEHr iD8Q== X-Gm-Message-State: APjAAAV+LAyRrXRRPXBelHa8q2iE6MupwpEnEtjbHjg8MwOK2AvpKBsN 68qtWNt/pCDlez/IWp+vN6EhpWeQ5z2sand/eOo= X-Google-Smtp-Source: APXvYqyiYBUqf1sj2C46JhJxggWvBzGTc0kaZPa4soYBZ1TLz+J5BgHio6D7yQ6P0oN3g4BPYKjCtBPztq9+oisj+gc= X-Received: by 2002:a19:8a41:: with SMTP id m62mr270749lfd.5.1576641877204; Tue, 17 Dec 2019 20:04:37 -0800 (PST) MIME-Version: 1.0 References: <717e76b6d41e09c352d98a83708c3e3c9fe5d63b.1576227325.git.alistair@alistair23.me> <13f8810e-fb67-24c8-fecf-72f48ac5c7db@redhat.com> In-Reply-To: <13f8810e-fb67-24c8-fecf-72f48ac5c7db@redhat.com> From: Alistair Francis Date: Tue, 17 Dec 2019 20:04:07 -0800 Message-ID: Subject: Re: [PATCH v6 2/4] hw/misc: Add the STM32F4xx EXTI device To: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= Cc: Alistair Francis , "qemu-devel@nongnu.org Developers" , Peter Maydell , qemu-arm Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::142 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 18 Dec 2019 04:04:49 -0000 On Sat, Dec 14, 2019 at 5:49 AM Philippe Mathieu-Daud=C3=A9 wrote: > > Hi Alistair, > > On 12/14/19 3:44 AM, Alistair Francis wrote: > > Signed-off-by: Alistair Francis > > Reviewed-by: Peter Maydell > > --- > > hw/arm/Kconfig | 1 + > > hw/misc/Kconfig | 3 + > > hw/misc/Makefile.objs | 1 + > > hw/misc/stm32f4xx_exti.c | 189 ++++++++++++++++++++++++++++++= + > > hw/misc/trace-events | 5 + > > include/hw/misc/stm32f4xx_exti.h | 60 ++++++++++ > > 6 files changed, 259 insertions(+) > > create mode 100644 hw/misc/stm32f4xx_exti.c > > create mode 100644 include/hw/misc/stm32f4xx_exti.h > > > > diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig > > index 4660d14715..3d86691ae0 100644 > > --- a/hw/arm/Kconfig > > +++ b/hw/arm/Kconfig > > @@ -315,6 +315,7 @@ config STM32F405_SOC > > bool > > select ARM_V7M > > select STM32F4XX_SYSCFG > > + select STM32F4XX_EXTI > > > > config XLNX_ZYNQMP_ARM > > bool > > diff --git a/hw/misc/Kconfig b/hw/misc/Kconfig > > index 72609650b7..bdd77d8020 100644 > > --- a/hw/misc/Kconfig > > +++ b/hw/misc/Kconfig > > @@ -85,6 +85,9 @@ config STM32F2XX_SYSCFG > > config STM32F4XX_SYSCFG > > bool > > > > +config STM32F4XX_EXTI > > + bool > > + > > config MIPS_ITU > > bool > > > > diff --git a/hw/misc/Makefile.objs b/hw/misc/Makefile.objs > > index ea8025e0bb..c6ecbdd7b0 100644 > > --- a/hw/misc/Makefile.objs > > +++ b/hw/misc/Makefile.objs > > @@ -59,6 +59,7 @@ common-obj-$(CONFIG_ZYNQ) +=3D zynq_slcr.o > > common-obj-$(CONFIG_ZYNQ) +=3D zynq-xadc.o > > common-obj-$(CONFIG_STM32F2XX_SYSCFG) +=3D stm32f2xx_syscfg.o > > common-obj-$(CONFIG_STM32F4XX_SYSCFG) +=3D stm32f4xx_syscfg.o > > +common-obj-$(CONFIG_STM32F4XX_EXTI) +=3D stm32f4xx_exti.o > > obj-$(CONFIG_MIPS_CPS) +=3D mips_cmgcr.o > > obj-$(CONFIG_MIPS_CPS) +=3D mips_cpc.o > > obj-$(CONFIG_MIPS_ITU) +=3D mips_itu.o > > diff --git a/hw/misc/stm32f4xx_exti.c b/hw/misc/stm32f4xx_exti.c > > new file mode 100644 > > index 0000000000..7f87a885aa > > --- /dev/null > > +++ b/hw/misc/stm32f4xx_exti.c > > @@ -0,0 +1,189 @@ > > +/* > > + * STM32F4XX EXTI > > + * > > + * Copyright (c) 2014 Alistair Francis > > + * > > + * Permission is hereby granted, free of charge, to any person obtaini= ng a copy > > + * of this software and associated documentation files (the "Software"= ), to deal > > + * in the Software without restriction, including without limitation t= he rights > > + * to use, copy, modify, merge, publish, distribute, sublicense, and/o= r sell > > + * copies of the Software, and to permit persons to whom the Software = is > > + * furnished to do so, subject to the following conditions: > > + * > > + * The above copyright notice and this permission notice shall be incl= uded in > > + * all copies or substantial portions of the Software. > > + * > > + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXP= RESS OR > > + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABI= LITY, > > + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT S= HALL > > + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES O= R OTHER > > + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARI= SING FROM, > > + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALI= NGS IN > > + * THE SOFTWARE. > > + */ > > + > > +#include "qemu/osdep.h" > > +#include "qemu/log.h" > > +#include "trace.h" > > +#include "hw/irq.h" > > +#include "migration/vmstate.h" > > +#include "hw/misc/stm32f4xx_exti.h" > > + > > +static void stm32f4xx_exti_reset(DeviceState *dev) > > +{ > > + STM32F4xxExtiState *s =3D STM32F4XX_EXTI(dev); > > + > > + s->exti_imr =3D 0x00000000; > > + s->exti_emr =3D 0x00000000; > > + s->exti_rtsr =3D 0x00000000; > > + s->exti_ftsr =3D 0x00000000; > > + s->exti_swier =3D 0x00000000; > > + s->exti_pr =3D 0x00000000; > > +} > > + > > +static void stm32f4xx_exti_set_irq(void *opaque, int irq, int level) > > +{ > > + STM32F4xxExtiState *s =3D opaque; > > + > > + if (!((1 << irq) & s->exti_imr)) { > > + /* Interrupt is masked */ > > + return; > > I'm not sure this is correct, don't you need to set the bit in the > exti_pr register regardless it is masked? Else in masked polling mode > the guest will never see IRQ delivered. > > So I'd drop this if statement, ... > > > + } > > + > > + trace_stm32f4xx_exti_set_irq(irq, level); > > + > > + if (((1 << irq) & s->exti_rtsr) && level) { > > + /* Rising Edge */ > > + qemu_irq_pulse(s->irq[irq]); > > ... do not pulse here, ... > > > + s->exti_pr |=3D 1 << irq; > > + } > > + > > + if (((1 << irq) & s->exti_ftsr) && !level) { > > + /* Falling Edge */ > > + qemu_irq_pulse(s->irq[irq]); > > ... do not pulse here, ... > > > + s->exti_pr |=3D 1 << irq; > > + } > > ... and here pulse if not masked: > > if (!((1 << irq) & s->exti_imr)) { > /* Interrupt is masked */ > return; > } > qemu_irq_pulse(s->irq[irq]); > > (Or invert the if condition). Good point. I have updated this. Alistair > > > +} > > + > > +static uint64_t stm32f4xx_exti_read(void *opaque, hwaddr addr, > > + unsigned int size) > > +{ > > + STM32F4xxExtiState *s =3D opaque; > > + > > + trace_stm32f4xx_exti_read(addr); > > + > > + switch (addr) { > > + case EXTI_IMR: > > + return s->exti_imr; > > + case EXTI_EMR: > > + return s->exti_emr; > > + case EXTI_RTSR: > > + return s->exti_rtsr; > > + case EXTI_FTSR: > > + return s->exti_ftsr; > > + case EXTI_SWIER: > > + return s->exti_swier; > > + case EXTI_PR: > > + return s->exti_pr; > > + default: > > + qemu_log_mask(LOG_GUEST_ERROR, > > + "STM32F4XX_exti_read: Bad offset %x\n", (int)add= r); > > + return 0; > > + } > > + return 0; > > +} > > + > > +static void stm32f4xx_exti_write(void *opaque, hwaddr addr, > > + uint64_t val64, unsigned int size) > > +{ > > + STM32F4xxExtiState *s =3D opaque; > > + uint32_t value =3D (uint32_t) val64; > > + > > + trace_stm32f4xx_exti_write(addr, value); > > + > > + switch (addr) { > > + case EXTI_IMR: > > + s->exti_imr =3D value; > > + return; > > + case EXTI_EMR: > > + s->exti_emr =3D value; > > + return; > > + case EXTI_RTSR: > > + s->exti_rtsr =3D value; > > + return; > > + case EXTI_FTSR: > > + s->exti_ftsr =3D value; > > + return; > > + case EXTI_SWIER: > > + s->exti_swier =3D value; > > + return; > > + case EXTI_PR: > > + /* This bit is cleared by writing a 1 to it */ > > + s->exti_pr &=3D ~value; > > + return; > > + default: > > + qemu_log_mask(LOG_GUEST_ERROR, > > + "STM32F4XX_exti_write: Bad offset %x\n", (int)ad= dr); > > + } > > +} > > + > > +static const MemoryRegionOps stm32f4xx_exti_ops =3D { > > + .read =3D stm32f4xx_exti_read, > > + .write =3D stm32f4xx_exti_write, > > + .endianness =3D DEVICE_NATIVE_ENDIAN, > > +}; > > + > > +static void stm32f4xx_exti_init(Object *obj) > > +{ > > + STM32F4xxExtiState *s =3D STM32F4XX_EXTI(obj); > > + int i; > > + > > + for (i =3D 0; i < NUM_INTERRUPT_OUT_LINES; i++) { > > + sysbus_init_irq(SYS_BUS_DEVICE(obj), &s->irq[i]); > > + } > > + > > + memory_region_init_io(&s->mmio, obj, &stm32f4xx_exti_ops, s, > > + TYPE_STM32F4XX_EXTI, 0x400); > > + sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->mmio); > > + > > + qdev_init_gpio_in(DEVICE(obj), stm32f4xx_exti_set_irq, > > + NUM_GPIO_EVENT_IN_LINES); > > +} > > + > > +static const VMStateDescription vmstate_stm32f4xx_exti =3D { > > + .name =3D TYPE_STM32F4XX_EXTI, > > + .version_id =3D 1, > > + .minimum_version_id =3D 1, > > + .fields =3D (VMStateField[]) { > > + VMSTATE_UINT32(exti_imr, STM32F4xxExtiState), > > + VMSTATE_UINT32(exti_emr, STM32F4xxExtiState), > > + VMSTATE_UINT32(exti_rtsr, STM32F4xxExtiState), > > + VMSTATE_UINT32(exti_ftsr, STM32F4xxExtiState), > > + VMSTATE_UINT32(exti_swier, STM32F4xxExtiState), > > + VMSTATE_UINT32(exti_pr, STM32F4xxExtiState), > > + VMSTATE_END_OF_LIST() > > + } > > +}; > > + > > +static void stm32f4xx_exti_class_init(ObjectClass *klass, void *data) > > +{ > > + DeviceClass *dc =3D DEVICE_CLASS(klass); > > + > > + dc->reset =3D stm32f4xx_exti_reset; > > + dc->vmsd =3D &vmstate_stm32f4xx_exti; > > +} > > + > > +static const TypeInfo stm32f4xx_exti_info =3D { > > + .name =3D TYPE_STM32F4XX_EXTI, > > + .parent =3D TYPE_SYS_BUS_DEVICE, > > + .instance_size =3D sizeof(STM32F4xxExtiState), > > + .instance_init =3D stm32f4xx_exti_init, > > + .class_init =3D stm32f4xx_exti_class_init, > > +}; > > + > > +static void stm32f4xx_exti_register_types(void) > > +{ > > + type_register_static(&stm32f4xx_exti_info); > > +} > > + > > +type_init(stm32f4xx_exti_register_types) > > diff --git a/hw/misc/trace-events b/hw/misc/trace-events > > index 02327562bc..91a3794d68 100644 > > --- a/hw/misc/trace-events > > +++ b/hw/misc/trace-events > > @@ -90,6 +90,11 @@ stm32f4xx_pulse_exti(int irq) "Pulse EXTI: %d" > > stm32f4xx_syscfg_read(uint64_t addr) "reg read: addr: 0x%" PRIx64 " " > > stm32f4xx_syscfg_write(uint64_t addr, uint64_t data) "reg write: addr= : 0x%" PRIx64 " val: 0x%" PRIx64 "" > > > > +# stm32f4xx_exti > > +stm32f4xx_exti_set_irq(int irq, int leve) "Set EXTI: %d to %d" > > +stm32f4xx_exti_read(uint64_t addr) "reg read: addr: 0x%" PRIx64 " " > > +stm32f4xx_exti_write(uint64_t addr, uint64_t data) "reg write: addr: 0= x%" PRIx64 " val: 0x%" PRIx64 "" > > + > > # tz-mpc.c > > tz_mpc_reg_read(uint32_t offset, uint64_t data, unsigned size) "TZ MP= C regs read: offset 0x%x data 0x%" PRIx64 " size %u" > > tz_mpc_reg_write(uint32_t offset, uint64_t data, unsigned size) "TZ M= PC regs write: offset 0x%x data 0x%" PRIx64 " size %u" > > diff --git a/include/hw/misc/stm32f4xx_exti.h b/include/hw/misc/stm32f4= xx_exti.h > > new file mode 100644 > > index 0000000000..707036a41b > > --- /dev/null > > +++ b/include/hw/misc/stm32f4xx_exti.h > > @@ -0,0 +1,60 @@ > > +/* > > + * STM32F4XX EXTI > > + * > > + * Copyright (c) 2014 Alistair Francis > > + * > > + * Permission is hereby granted, free of charge, to any person obtaini= ng a copy > > + * of this software and associated documentation files (the "Software"= ), to deal > > + * in the Software without restriction, including without limitation t= he rights > > + * to use, copy, modify, merge, publish, distribute, sublicense, and/o= r sell > > + * copies of the Software, and to permit persons to whom the Software = is > > + * furnished to do so, subject to the following conditions: > > + * > > + * The above copyright notice and this permission notice shall be incl= uded in > > + * all copies or substantial portions of the Software. > > + * > > + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXP= RESS OR > > + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABI= LITY, > > + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT S= HALL > > + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES O= R OTHER > > + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARI= SING FROM, > > + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALI= NGS IN > > + * THE SOFTWARE. > > + */ > > + > > +#ifndef HW_STM_EXTI_H > > +#define HW_STM_EXTI_H > > + > > +#include "hw/sysbus.h" > > +#include "hw/hw.h" > > + > > +#define EXTI_IMR 0x00 > > +#define EXTI_EMR 0x04 > > +#define EXTI_RTSR 0x08 > > +#define EXTI_FTSR 0x0C > > +#define EXTI_SWIER 0x10 > > +#define EXTI_PR 0x14 > > + > > +#define TYPE_STM32F4XX_EXTI "stm32f4xx-exti" > > +#define STM32F4XX_EXTI(obj) \ > > + OBJECT_CHECK(STM32F4xxExtiState, (obj), TYPE_STM32F4XX_EXTI) > > + > > +#define NUM_GPIO_EVENT_IN_LINES 16 > > +#define NUM_INTERRUPT_OUT_LINES 16 > > + > > +typedef struct { > > + SysBusDevice parent_obj; > > + > > + MemoryRegion mmio; > > + > > + uint32_t exti_imr; > > + uint32_t exti_emr; > > + uint32_t exti_rtsr; > > + uint32_t exti_ftsr; > > + uint32_t exti_swier; > > + uint32_t exti_pr; > > + > > + qemu_irq irq[NUM_INTERRUPT_OUT_LINES]; > > +} STM32F4xxExtiState; > > + > > +#endif > > > From MAILER-DAEMON Tue Dec 17 23:14:32 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1ihQjH-0002jP-Tl for mharc-qemu-arm@gnu.org; Tue, 17 Dec 2019 23:14:31 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:36881) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ihQjF-0002hL-Tj for qemu-arm@nongnu.org; Tue, 17 Dec 2019 23:14:30 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ihQjE-0006Zi-Vm for qemu-arm@nongnu.org; Tue, 17 Dec 2019 23:14:29 -0500 Received: from mail-lf1-x141.google.com ([2a00:1450:4864:20::141]:33497) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ihQjC-0006WO-CZ; Tue, 17 Dec 2019 23:14:26 -0500 Received: by mail-lf1-x141.google.com with SMTP id n25so642654lfl.0; Tue, 17 Dec 2019 20:14:26 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=gqJcASg9fWaiY51VT0yBYeRUW0LCqDwhoxU/57LYi1o=; b=pnvPTOs4gOnztIMN0fnJF90cWRS0Th7ouPshuUe/KKtG/pNJUIW97L7nJW8sq6UJW5 kFxSaRDrmTRhPYpgYYpezy8SoYosnvY0udgAHAuqp/pOwL2upagPqAhR7RCKfuP/1CDp hG+KLus61eWTSZu4MZVYqNf5qHs3OJNUh9p6JkxPnncSmF6NbZWX3vy31iiU4+R7nix6 Lf0pS67oBxxG37Tf6m65TtbAKfdRJG3LYKYaCwODJzIIY/nRWnoG5///SveSdpvYFaXL jLVW9uxhqhC7OAw5M6yU581kDP6OCDnXerW8BejpNPdY7SMqvtT3n2O47gmi5dEUhHmS 3N+g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=gqJcASg9fWaiY51VT0yBYeRUW0LCqDwhoxU/57LYi1o=; b=S3mFHaH5NQtjk0q6YeRF+tBiTT6ZDOa5NNuU0613q8hWR1mwH7qFIkI9+sor52SJ6B 0bLmBlj9niTW3fWIbk/A78Yk37ddWk/EB+LHhoNB8FC3e3rz0adwbg/qZGxY4ViX9Pwq 6aBRL8rcuKRX7MJ/D5zhJL4CVrxW7GEF0rpB7IsqnY2bFT3FvMlkzGJzErSo6uVysKjn yIq/RUq5lU/hCEXUhAjiJO6XE7HmTBOUSsDFM3gDanXIW3malcFy6KRxI7Aic0eymYtu +pdEa//aXpTI95yu36iIkcPV5ZX8MEzh49kj+mSyRSz50CHwiE/eAPsorRrNf80ZuzTd mDdg== X-Gm-Message-State: APjAAAUgzgCF3cwrkyCM4XMTsnKqBdVTyE+D5UCpyg49QVDrjL5TJ4KN IeyYONs/w3e47FJ026pcKMI4fxibEyni7j0szjI= X-Google-Smtp-Source: APXvYqy39MP/1DtLP0ie8Kmtm+bKwmGNIjOIuqz9KXHXCcaMVOTo/ggQQvrgJVvFOAsM3Kysro/o8Hp/zVyRQikCEo4= X-Received: by 2002:ac2:4945:: with SMTP id o5mr284247lfi.93.1576642464995; Tue, 17 Dec 2019 20:14:24 -0800 (PST) MIME-Version: 1.0 References: <40f97ae32a6f21d8184c1cc46fad2defb302238d.1576227325.git.alistair@alistair23.me> In-Reply-To: From: Alistair Francis Date: Tue, 17 Dec 2019 20:13:55 -0800 Message-ID: Subject: Re: [PATCH v6 4/4] hw/arm: Add the Netduino Plus 2 To: Peter Maydell Cc: Alistair Francis , QEMU Developers , qemu-arm Content-Type: text/plain; charset="UTF-8" X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::141 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 18 Dec 2019 04:14:31 -0000 On Tue, Dec 17, 2019 at 8:03 AM Peter Maydell wrote: > > On Sat, 14 Dec 2019 at 02:44, Alistair Francis wrote: > > > > Signed-off-by: Alistair Francis > > --- > > MAINTAINERS | 6 +++++ > > hw/arm/Kconfig | 3 +++ > > hw/arm/Makefile.objs | 1 + > > hw/arm/netduinoplus2.c | 52 ++++++++++++++++++++++++++++++++++++++++++ > > 4 files changed, 62 insertions(+) > > create mode 100644 hw/arm/netduinoplus2.c > > > > diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig > > index 7bfdc3a7ac..881e7f56e7 100644 > > --- a/hw/arm/Kconfig > > +++ b/hw/arm/Kconfig > > @@ -105,6 +105,9 @@ config NETDUINOPLUS2 > > bool > > select STM32F405_SOC > > > > +config NETDUINOPLUS2 > > + bool > > + > > config NSERIES > > bool > > select OMAP > > Something odd has happened here -- your patch 1/4 already > had a stanza: > > +config NETDUINOPLUS2 > + bool > + select STM32F405_SOC > > so either that should be in this patch or this fragment here > should just be deleted. Good catch. It kind of makes sense to have that fragment in this patch, but then I don't see a nice way to build the flies as they are added, so I removed the fragment from this patch. > > Assuming you sort that out, > Reviewed-by: Peter Maydell Thanks Peter Alistair > > thanks > -- PMM From MAILER-DAEMON Wed Dec 18 01:05:22 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1ihSSY-0004vc-Km for mharc-qemu-arm@gnu.org; Wed, 18 Dec 2019 01:05:22 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:58916) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ihSSW-0004rO-57 for qemu-arm@nongnu.org; Wed, 18 Dec 2019 01:05:21 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ihSST-0005wq-E1 for qemu-arm@nongnu.org; Wed, 18 Dec 2019 01:05:18 -0500 Received: from us-smtp-delivery-1.mimecast.com ([205.139.110.120]:53711 helo=us-smtp-1.mimecast.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1ihSSS-0005u5-U3 for qemu-arm@nongnu.org; Wed, 18 Dec 2019 01:05:17 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1576649116; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=Dxu7JekNHm3dJ9ZpgeBC7AVH7BJaW+wzgYxjoq4cflo=; b=Po5e/outreWza5/qjFb6It0moJfA4cJ2xiiP1aIaFuAHWVBSg/pjPdrduo8haaNYE8bagU ZZri6CqO8wmNM9Sg+BmnMKLM8TknvLPjD7W5qi/ZlDNaHe/Cop3B74qCgcmWbHmm1bhaUZ ScwiRozwC4azxCSO+IJP14R8lpH6o+U= Received: from mimecast-mx01.redhat.com (mimecast-mx01.redhat.com [209.132.183.4]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-402-G2M3ZjM2MKScFvK70WmcPg-1; Wed, 18 Dec 2019 01:05:14 -0500 Received: from smtp.corp.redhat.com (int-mx02.intmail.prod.int.phx2.redhat.com [10.5.11.12]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx01.redhat.com (Postfix) with ESMTPS id 100FC8017DF; Wed, 18 Dec 2019 06:05:12 +0000 (UTC) Received: from blackfin.pond.sub.org (ovpn-116-42.ams2.redhat.com [10.36.116.42]) by smtp.corp.redhat.com (Postfix) with ESMTPS id 4CAD660C18; Wed, 18 Dec 2019 06:05:05 +0000 (UTC) Received: by blackfin.pond.sub.org (Postfix, from userid 1000) id C037D11386A7; Wed, 18 Dec 2019 07:05:03 +0100 (CET) From: Markus Armbruster To: "Chubb\, Peter \(Data61\, Kensington NSW\)" Cc: Philippe =?utf-8?Q?Mathieu-Daud=C3=A9?= , Fam Zheng , Peter Maydell , Hannes Reinecke , Gerd Hoffmann , "qemu-block\@nongnu.org" , "qemu-trivial\@nongnu.org" , Jason Wang , Mark Cave-Ayland , "qemu-devel\@nongnu.org" , Max Reitz , Andrew Jeffery , "qemu-arm\@nongnu.org" , Peter Chubb , =?utf-8?Q?C=C3=A9dric?= Le Goater , Kevin Wolf , Paolo Bonzini , Joel Stanley Subject: Re: [PATCH 0/6] Fix more GCC9 -O3 warnings References: <20191217173252.4672-1-philmd@redhat.com> <84fthiaahd.wl-Peter.Chubb@data61.csiro.au> Date: Wed, 18 Dec 2019 07:05:03 +0100 In-Reply-To: <84fthiaahd.wl-Peter.Chubb@data61.csiro.au> (Peter Chubb's message of "Tue, 17 Dec 2019 21:49:35 +0000") Message-ID: <87a77q9njk.fsf@dusky.pond.sub.org> User-Agent: Gnus/5.13 (Gnus v5.13) Emacs/26.2 (gnu/linux) MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.79 on 10.5.11.12 X-MC-Unique: G2M3ZjM2MKScFvK70WmcPg-1 X-Mimecast-Spam-Score: 0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 205.139.110.120 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 18 Dec 2019 06:05:21 -0000 "Chubb, Peter (Data61, Kensington NSW)" writes: >>>>>> "Philippe" =3D=3D Philippe Mathieu-Daud=C3=A9 wr= ites: > > Philippe> Fix some trivial warnings when building with -O3. > > For compatibility with lint and other older checkers, it'd be good to kee= p > this as /* FALLTHROUGH */ (which gcc should accept according to its > manual). We have hundreds of /* fall through */ comments already. > Fixing the comments' placement is a different matter, and should be > done. Seems to me that until gcc started warning for this, noone had > actually run a checker, and the comments were just for human info. > > Peter C From MAILER-DAEMON Wed Dec 18 03:00:38 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1ihUG6-00064c-CW for mharc-qemu-arm@gnu.org; Wed, 18 Dec 2019 03:00:38 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:39371) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ihUFz-0005ti-Ir for qemu-arm@nongnu.org; Wed, 18 Dec 2019 03:00:36 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ihUFy-0006Yu-0q for qemu-arm@nongnu.org; Wed, 18 Dec 2019 03:00:31 -0500 Received: from mail-ot1-x342.google.com ([2607:f8b0:4864:20::342]:41642) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ihUFn-0006HM-Re; Wed, 18 Dec 2019 03:00:20 -0500 Received: by mail-ot1-x342.google.com with SMTP id r27so1365501otc.8; Wed, 18 Dec 2019 00:00:19 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=mime-version:in-reply-to:references:from:date:message-id:subject:to :cc; bh=JVg5swbti9AOC9j2cReONmB/j54YHwCcla5puT1Fw9k=; b=JMpkN3LDA9P1R3Nz6bjWK0wdn/gYJ9F8Hc2kiNbWI9z8zdVx85D3oF4/Y9jRE7+hvn pg5GU3qnqfU0pVZE8DA47f1s8F10/Vi8H3qPu7SMs+7jOUNmqdgkZ8V/6OVrkavbO6Pc FdvasuscH4/449gcawLtsHO8AEal0gQmwh81OZnLvKC4QIMllxkd0sCBn3CKmGHZQev2 UlC1gk5P/9WkHpo2AhfLReQhsuIw2ppe+gvCcLWF8EsmR+nCazf3RnhL90OHUK4LctcV QVlilYx6cgDpSeK/TlGCsHq5I8kpr7wCYncPlWTWJLreU3DNuHyavQo+bKmDVRRwZBO7 osqw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:in-reply-to:references:from:date :message-id:subject:to:cc; bh=JVg5swbti9AOC9j2cReONmB/j54YHwCcla5puT1Fw9k=; b=AJdNZgQEwD9E5CiALp/9VHGTmyAdocF3AjuAlfvAuOGLWm35uBEf6RA3VGcYeEBzCB 5ZWpfwxbEqef4Hw0KaBJ/6jTukFwMZ1RHSsgVEApJcJTfYuCew9Mgrhvciiw+cEw5I6q 7JrNeDw98Yo8BzYUDMgWLcHjeBF8L+BUKo6LRyimACjtdXnbnJf3IXGSbpw9th7Veq/I SaBgtN6OokT81n9JuoKmXdlmlGUcerI+OrGK9hxNUMdu8cQhsjbR4c9jtTH3BzoIFInC yLq2HX4EmIKRs0OoyuCVww3OCMokg3+G+Mnh6Iu/5ZgHqnKwazwqF6FlQD/5khWTvvxh tVfQ== X-Gm-Message-State: APjAAAWOwzeCIkTknxWaHDmfYuHV8dKg5M363zNcdZOG9uYCDIdDi9Tg lhg/S1D6Cko/wR6znvuYNY9t2r0vg65UhMMvsZo= X-Google-Smtp-Source: APXvYqz2Cf4NRh6bsfKgT8Mqda057xivdINKLU+mwyKu3rxpJemaCJt9VVBH3r22KVjLscppbsHsEafl6ydALrVDxR0= X-Received: by 2002:a9d:7305:: with SMTP id e5mr1251528otk.64.1576656018700; Wed, 18 Dec 2019 00:00:18 -0800 (PST) MIME-Version: 1.0 Received: by 2002:a9d:d21:0:0:0:0:0 with HTTP; Wed, 18 Dec 2019 00:00:18 -0800 (PST) In-Reply-To: <20191217173425.5082-4-philmd@redhat.com> References: <20191217173425.5082-1-philmd@redhat.com> <20191217173425.5082-4-philmd@redhat.com> From: Aleksandar Markovic Date: Wed, 18 Dec 2019 09:00:18 +0100 Message-ID: Subject: Re: [PATCH 3/6] hw/net/imx_fec: Rewrite fall through comments To: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= Cc: "qemu-devel@nongnu.org" , Peter Maydell , "qemu-trivial@nongnu.org" , Jason Wang , "qemu-arm@nongnu.org" , Peter Chubb Content-Type: multipart/alternative; boundary="000000000000ed7c3f0599f5d58f" X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::342 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 18 Dec 2019 08:00:37 -0000 --000000000000ed7c3f0599f5d58f Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable On Tuesday, December 17, 2019, Philippe Mathieu-Daud=C3=A9 wrote: > GCC9 is confused by this comment when building with CFLAG > -Wimplicit-fallthrough=3D2: > > hw/net/imx_fec.c: In function =E2=80=98imx_eth_write=E2=80=99: > hw/net/imx_fec.c:906:12: error: this statement may fall through > [-Werror=3Dimplicit-fallthrough=3D] > 906 | if (unlikely(single_tx_ring)) { > | ^ > hw/net/imx_fec.c:912:5: note: here > 912 | case ENET_TDAR: /* FALLTHROUGH */ > | ^~~~ > cc1: all warnings being treated as errors > > Rewrite the comments in the correct place, using 'fall through' > which is recognized by GCC and static analyzers. > > Signed-off-by: Philippe Mathieu-Daud=C3=A9 > --- > Cc: Peter Chubb > Cc: Peter Maydell > Cc: Jason Wang > Cc: qemu-arm@nongnu.org > --- > hw/net/imx_fec.c | 8 +++++--- > 1 file changed, 5 insertions(+), 3 deletions(-) > > Here we can truly say that gcc is confused (as opposed to another patch from this series). The new positions of comments/annotations are good. Reviewed-by: Aleksandar Markovic > diff --git a/hw/net/imx_fec.c b/hw/net/imx_fec.c > index bd99236864..30cc07753d 100644 > --- a/hw/net/imx_fec.c > +++ b/hw/net/imx_fec.c > @@ -901,15 +901,17 @@ static void imx_eth_write(void *opaque, hwaddr > offset, uint64_t value, > s->regs[index] =3D 0; > } > break; > - case ENET_TDAR1: /* FALLTHROUGH */ > - case ENET_TDAR2: /* FALLTHROUGH */ > + /* fall through */ > + case ENET_TDAR1: > + case ENET_TDAR2: > if (unlikely(single_tx_ring)) { > qemu_log_mask(LOG_GUEST_ERROR, > "[%s]%s: trying to access TDAR2 or TDAR1\n", > TYPE_IMX_FEC, __func__); > return; > } > - case ENET_TDAR: /* FALLTHROUGH */ > + /* fall through */ > + case ENET_TDAR: > if (s->regs[ENET_ECR] & ENET_ECR_ETHEREN) { > s->regs[index] =3D ENET_TDAR_TDAR; > imx_eth_do_tx(s, index); > -- > 2.21.0 > > > --000000000000ed7c3f0599f5d58f Content-Type: text/html; charset="UTF-8" Content-Transfer-Encoding: quoted-printable

On Tuesday, December 17, 2019, Philippe Mathieu-Daud=C3=A9 <philmd@redhat.com> wrote:
GCC9 is confused by this comment when building wit= h CFLAG
-Wimplicit-fallthrough=3D2:

=C2=A0 hw/net/imx_fec.c: In function =E2=80=98imx_eth_write=E2=80=99:
=C2=A0 hw/net/imx_fec.c:906:12: error: this statement may fall through [-We= rror=3Dimplicit-fallthrough=3D]
=C2=A0 =C2=A0 906 |=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0if (unlikely(single_tx= _ring)) {
=C2=A0 =C2=A0 =C2=A0 =C2=A0 |=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 ^ =C2=A0 hw/net/imx_fec.c:912:5: note: here
=C2=A0 =C2=A0 912 |=C2=A0 =C2=A0 =C2=A0case ENET_TDAR:=C2=A0 =C2=A0 =C2=A0/= * FALLTHROUGH */
=C2=A0 =C2=A0 =C2=A0 =C2=A0 |=C2=A0 =C2=A0 =C2=A0^~~~
=C2=A0 cc1: all warnings being treated as errors

Rewrite the comments in the correct place,=C2=A0 using 'fall through= 9;
which is recognized by GCC and static analyzers.

Signed-off-by: Philippe Mathieu-Daud=C3=A9 <philmd@redhat.com>
---
Cc: Peter Chubb <peter.chubb= @nicta.com.au>
Cc: Peter Maydell <peter.may= dell@linaro.org>
Cc: Jason Wang <jasowang@redhat.c= om>
Cc: qemu-arm@nongnu.org
---
=C2=A0hw/net/imx_fec.c | 8 +++++---
=C2=A01 file changed, 5 insertions(+), 3 deletions(-)


Here we can truly say that gcc is conf= used (as opposed to another patch from this series).

The new positions of comments/annotations are good.

=
Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com>

=C2=A0
diff --git a/hw/net/imx_fec.c b/hw/net/imx_fec.c
index bd99236864..30cc07753d 100644
--- a/hw/net/imx_fec.c
+++ b/hw/net/imx_fec.c
@@ -901,15 +901,17 @@ static void imx_eth_write(void *opaque, hwaddr offset= , uint64_t value,
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0s->regs[index] =3D 0; =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0}
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0break;
-=C2=A0 =C2=A0 case ENET_TDAR1:=C2=A0 =C2=A0 /* FALLTHROUGH */
-=C2=A0 =C2=A0 case ENET_TDAR2:=C2=A0 =C2=A0 /* FALLTHROUGH */
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 /* fall through */
+=C2=A0 =C2=A0 case ENET_TDAR1:
+=C2=A0 =C2=A0 case ENET_TDAR2:
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0if (unlikely(single_tx_ring)) {
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0qemu_log_mask(LOG_GUEST_ERR= OR,
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0"[%s]%s: trying to access TDAR2 or TDAR1\n&quo= t;,
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0TYPE_IMX_FEC, __func__);
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0return;
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0}
-=C2=A0 =C2=A0 case ENET_TDAR:=C2=A0 =C2=A0 =C2=A0/* FALLTHROUGH */
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 /* fall through */
+=C2=A0 =C2=A0 case ENET_TDAR:
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0if (s->regs[ENET_ECR] & ENET_ECR_E= THEREN) {
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0s->regs[index] =3D ENET_= TDAR_TDAR;
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0imx_eth_do_tx(s, index); --
2.21.0


--000000000000ed7c3f0599f5d58f-- From MAILER-DAEMON Wed Dec 18 03:27:06 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1ihUfi-0002rD-MN for mharc-qemu-arm@gnu.org; Wed, 18 Dec 2019 03:27:06 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:51122) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ihUfe-0002lX-TS for qemu-arm@nongnu.org; Wed, 18 Dec 2019 03:27:04 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ihUfd-0003C4-Qz for qemu-arm@nongnu.org; Wed, 18 Dec 2019 03:27:02 -0500 Received: from mail-ot1-x344.google.com ([2607:f8b0:4864:20::344]:34378) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ihUfZ-00031l-Aw; Wed, 18 Dec 2019 03:26:57 -0500 Received: by mail-ot1-x344.google.com with SMTP id a15so1495171otf.1; Wed, 18 Dec 2019 00:26:57 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc:content-transfer-encoding; bh=m9f/p9XSU77rE+9iAxpKkClXlh3MNGFo2vxjttUKlLU=; b=dYe4i0OMKE+jxWkvmY2y0GreyxyeHE1HuXAl4CTHSlwlRSBe6tiYcRmcGcAbXBLvZ+ yOsR2cJAtSgm2ozhm1aKcUBo/CG8vlDwtWfwjHvWZUTucSfZduWCDqJJS2Qh1TxljJpT e5jSsrWqc9laFmCBiGMSDPhqL0YkUnWJq9BrWQAzl/63mV9MzVSi4uRVxjPJeFvxVRPf y5BQoXsq1Ovx0wqLeA57aQbWgf+Qrd3NJL93NoavzuZqyTgItQ3Hj8yEFpBtM2KnUX82 /Ov1pc2pkhUarGtWgpgDVqphLN5Z5P2I3Iry9jXTZHpbbb/IaCNFDJPIYgDZDLQPBIUK izVA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc:content-transfer-encoding; bh=m9f/p9XSU77rE+9iAxpKkClXlh3MNGFo2vxjttUKlLU=; b=hO/zFS1dMW014+U2Qld0rk19OvasC47q6J/sf+lgkdOQFbqtjKrX6WoywShCz3x2Rl xA7EDdXGUGyhCO1kG5a+Onax1uU33dPslQzrldprlYlUwUgZe0Zvd5xSFo02jnfAPaQd uFTatBtxvBLRK42amizP1VYjxG8gBkI+iN4e6dSG5IMAJ+XhDeLsyox9XdHLfG6H4cG7 S2iGvYjuYpYKlntAx+eLB3Vgxs3M7heu4XwathqFcwYs5YNZEmyi6fYr3+4DV45kbfki KOlTM914//cwOsLMPhEqY0QKtwwX6NHlOXAFvAMNRArkp5NT3HxAKuNiY53Zy0c68YD6 3wmw== X-Gm-Message-State: APjAAAVvtRPBPyuda7y8yeXYJP5JTLosdzhalnJMD1L1mxoa+8pkAhbP JrEIO21NiLiVdPZTT8SGdsS83V0FC+ojofyug1c= X-Google-Smtp-Source: APXvYqzlSiRQ0xVigKKFcn3M08hSox4Z4LC1Jo20tplcsid6WPy8NGf9OI0kHp03TraCLNt20iKVy9yEz2t5MPNAG9U= X-Received: by 2002:a05:6830:3054:: with SMTP id p20mr1313877otr.121.1576657616346; Wed, 18 Dec 2019 00:26:56 -0800 (PST) MIME-Version: 1.0 References: <20191217173425.5082-1-philmd@redhat.com> <20191217173425.5082-5-philmd@redhat.com> In-Reply-To: <20191217173425.5082-5-philmd@redhat.com> From: Aleksandar Markovic Date: Wed, 18 Dec 2019 09:26:45 +0100 Message-ID: Subject: Re: [PATCH 4/6] hw/timer/aspeed_timer: Add a fall through comment To: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= Cc: QEMU Developers , Peter Maydell , QEMU Trivial , Andrew Jeffery , "open list:Stellaris" , Joel Stanley , =?UTF-8?Q?C=C3=A9dric_Le_Goater?= Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::344 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 18 Dec 2019 08:27:05 -0000 On Tue, Dec 17, 2019 at 6:37 PM Philippe Mathieu-Daud=C3=A9 wrote: > > Reported by GCC9 when building with CFLAG -Wimplicit-fallthrough=3D2: > > hw/timer/aspeed_timer.c: In function =E2=80=98aspeed_timer_set_value=E2= =80=99: > hw/timer/aspeed_timer.c:283:24: error: this statement may fall through = [-Werror=3Dimplicit-fallthrough=3D] > 283 | if (old_reload || !t->reload) { > | ~~~~~~~~~~~^~~~~~~~~~~~~ > hw/timer/aspeed_timer.c:287:5: note: here > 287 | case TIMER_REG_STATUS: > | ^~~~ > cc1: all warnings being treated as errors > > Add the missing fall through comment. > > Fixes: 1403f364472 > Signed-off-by: Philippe Mathieu-Daud=C3=A9 > --- Reviewed-by: Aleksandar Markovic > Cc: "C=C3=A9dric Le Goater" > Cc: Peter Maydell > Cc: Andrew Jeffery > Cc: Joel Stanley > Cc: qemu-arm@nongnu.org > --- > hw/timer/aspeed_timer.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/hw/timer/aspeed_timer.c b/hw/timer/aspeed_timer.c > index a8c38cc118..c91f18415c 100644 > --- a/hw/timer/aspeed_timer.c > +++ b/hw/timer/aspeed_timer.c > @@ -283,7 +283,7 @@ static void aspeed_timer_set_value(AspeedTimerCtrlSta= te *s, int timer, int reg, > if (old_reload || !t->reload) { > break; > } > - > + /* fall through to re-enable */ > case TIMER_REG_STATUS: > if (timer_enabled(t)) { > uint64_t now =3D qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); > -- > 2.21.0 > > From MAILER-DAEMON Wed Dec 18 03:34:36 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1ihUmy-0003j0-2I for mharc-qemu-arm@gnu.org; Wed, 18 Dec 2019 03:34:36 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:42711) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ihUmq-0003ce-Ik for qemu-arm@nongnu.org; Wed, 18 Dec 2019 03:34:30 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ihUmm-0007Ej-Hi for qemu-arm@nongnu.org; Wed, 18 Dec 2019 03:34:26 -0500 Received: from us-smtp-delivery-1.mimecast.com ([205.139.110.120]:48937 helo=us-smtp-1.mimecast.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1ihUml-0007Bm-Pq for qemu-arm@nongnu.org; Wed, 18 Dec 2019 03:34:24 -0500 DKIM-Signature: v=1; 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Wed, 18 Dec 2019 08:34:14 +0000 (UTC) Received: from [10.36.116.117] (ovpn-116-117.ams2.redhat.com [10.36.116.117]) by smtp.corp.redhat.com (Postfix) with ESMTPS id DA86E1891F; Wed, 18 Dec 2019 08:34:11 +0000 (UTC) Subject: Re: [kvm-unit-tests PATCH 05/16] arm/arm64: ITS: Introspection tests To: Zenghui Yu , eric.auger.pro@gmail.com, maz@kernel.org, kvmarm@lists.cs.columbia.edu, kvm@vger.kernel.org, qemu-devel@nongnu.org, qemu-arm@nongnu.org Cc: andre.przywara@arm.com, drjones@redhat.com, alexandru.elisei@arm.com, thuth@redhat.com, peter.maydell@linaro.org References: <20191216140235.10751-1-eric.auger@redhat.com> <20191216140235.10751-6-eric.auger@redhat.com> From: Auger Eric Message-ID: <6542297b-74d2-f3c2-63d8-04bb284414df@redhat.com> Date: Wed, 18 Dec 2019 09:34:10 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101 Thunderbird/60.4.0 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=utf-8 Content-Language: en-US X-Scanned-By: MIMEDefang 2.79 on 10.5.11.15 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 205.139.110.120 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 18 Dec 2019 08:34:30 -0000 Hi Zenghui, On 12/18/19 4:46 AM, Zenghui Yu wrote: > Hi Eric, >=20 > I have to admit that this is the first time I've looked into > the kvm-unit-tests code, so only some minor comments inline :) no problem. Thank you for looking at this. By the way, with patch 16 I was able to test yout fix: "KVM: arm/arm64: vgic: Don't rely on the wrong pending table". Reverting it produced an error. I forgot to mention that. >=20 > On 2019/12/16 22:02, Eric Auger wrote: >> Detect the presence of an ITS as part of the GICv3 init >> routine, initialize its base address and read few registers >> the IIDR, the TYPER to store its dimensioning parameters. >> >> This is our first ITS test, belonging to a new "its" group. >> >> Signed-off-by: Eric Auger >=20 > [...] >=20 >> diff --git a/lib/arm/asm/gic-v3-its.h b/lib/arm/asm/gic-v3-its.h >> new file mode 100644 >> index 0000000..2ce483e >> --- /dev/null >> +++ b/lib/arm/asm/gic-v3-its.h >> @@ -0,0 +1,116 @@ >> +/* >> + * All ITS* defines are lifted from include/linux/irqchip/arm-gic-v3.= h >> + * >> + * Copyright (C) 2016, Red Hat Inc, Andrew Jones >> + * >> + * This work is licensed under the terms of the GNU LGPL, version 2. >> + */ >> +#ifndef _ASMARM_GIC_V3_ITS_H_ >> +#define _ASMARM_GIC_V3_ITS_H_ >> + >> +#ifndef __ASSEMBLY__ >> + >> +#define GITS_CTLR=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0 0x0000 >> +#define GITS_IIDR=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0 0x0004 >> +#define GITS_TYPER=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0 0x0008 >> +#define GITS_CBASER=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0 0x0080 >> +#define GITS_CWRITER=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0 0x0088 >> +#define GITS_CREADR=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0 0x0090 >> +#define GITS_BASER=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0 0x0100 >> + >> +#define GITS_TYPER_PLPIS=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 (1UL << 0) >> +#define GITS_TYPER_IDBITS_SHIFT=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0 8 >> +#define GITS_TYPER_DEVBITS_SHIFT=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0 13 >> +#define GITS_TYPER_DEVBITS(r)=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0=C2=A0 ((((r) >> >> GITS_TYPER_DEVBITS_SHIFT) & 0x1f) + 1) >> +#define GITS_TYPER_PTA=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 (1UL << 19) >> +#define GITS_TYPER_HWCOLLCNT_SHIFT=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 24 >> + >> +#define GITS_CTLR_ENABLE=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 (1U << 0) >> + >> +#define GITS_CBASER_VALID=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0 (1UL << 63) >> +#define GITS_CBASER_SHAREABILITY_SHIFT=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0=C2=A0 (10) >> +#define GITS_CBASER_INNER_CACHEABILITY_SHIFT=C2=A0=C2=A0=C2=A0 (59) >> +#define GITS_CBASER_OUTER_CACHEABILITY_SHIFT=C2=A0=C2=A0=C2=A0 (53) >> +#define >> GITS_CBASER_SHAREABILITY_MASK=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0 \ >> +=C2=A0=C2=A0=C2=A0 GIC_BASER_SHAREABILITY(GITS_CBASER, SHAREABILITY_M= ASK) >> +#define >> GITS_CBASER_INNER_CACHEABILITY_MASK=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 \ >> +=C2=A0=C2=A0=C2=A0 GIC_BASER_CACHEABILITY(GITS_CBASER, INNER, MASK) >> +#define >> GITS_CBASER_OUTER_CACHEABILITY_MASK=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 \ >> +=C2=A0=C2=A0=C2=A0 GIC_BASER_CACHEABILITY(GITS_CBASER, OUTER, MASK) >> +#define GITS_CBASER_CACHEABILITY_MASK >> GITS_CBASER_INNER_CACHEABILITY_MASK >> + >> +#define >> GITS_CBASER_InnerShareable=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0=C2=A0=C2=A0 \ >> +=C2=A0=C2=A0=C2=A0 GIC_BASER_SHAREABILITY(GITS_CBASER, InnerShareable= ) >> + >> +#define GITS_CBASER_nCnB=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 GI= C_BASER_CACHEABILITY(GITS_CBASER, >> INNER, nCnB) >> +#define GITS_CBASER_nC=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0 GIC_BASER_CACHEABILITY(GITS_CBASER, >> INNER, nC) >> +#define GITS_CBASER_RaWt=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 GI= C_BASER_CACHEABILITY(GITS_CBASER, >> INNER, RaWt) >> +#define GITS_CBASER_RaWb=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 GI= C_BASER_CACHEABILITY(GITS_CBASER, >> INNER, RaWt) >=20 > s/RaWt/RaWb/ OK >=20 >> +#define GITS_CBASER_WaWt=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 GI= C_BASER_CACHEABILITY(GITS_CBASER, >> INNER, WaWt) >> +#define GITS_CBASER_WaWb=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 GI= C_BASER_CACHEABILITY(GITS_CBASER, >> INNER, WaWb) >> +#define GITS_CBASER_RaWaWt=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 GIC_BASER_CA= CHEABILITY(GITS_CBASER, >> INNER, RaWaWt) >> +#define GITS_CBASER_RaWaWb=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 GIC_BASER_CA= CHEABILITY(GITS_CBASER, >> INNER, RaWaWb) >> + >> +#define GITS_BASER_NR_REGS=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 8 >> + >> +#define GITS_BASER_VALID=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0=C2=A0 (1UL << 63) >> +#define GITS_BASER_INDIRECT=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0 (1ULL << 62) >> + >> +#define GITS_BASER_INNER_CACHEABILITY_SHIFT=C2=A0=C2=A0=C2=A0=C2=A0 (= 59) >> +#define GITS_BASER_OUTER_CACHEABILITY_SHIFT=C2=A0=C2=A0=C2=A0=C2=A0 (= 53) >> +#define GITS_BASER_CACHEABILITY_MASK=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0 0x7 >> + >> +#define GITS_BASER_nCnB=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= GIC_BASER_CACHEABILITY(GITS_BASER, >> INNER, nCnB) >> + >> +#define GITS_BASER_TYPE_SHIFT=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 (56) >> +#define GITS_BASER_TYPE(r)=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 (((r) >> >> GITS_BASER_TYPE_SHIFT) & 7) >> +#define GITS_BASER_ENTRY_SIZE_SHIFT=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 (48) >> +#define GITS_BASER_ENTRY_SIZE(r)=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0 ((((r) >> >> GITS_BASER_ENTRY_SIZE_SHIFT) & 0x1f) + 1) >> +#define GITS_BASER_SHAREABILITY_SHIFT=C2=A0=C2=A0 (10) >> +#define >> GITS_BASER_InnerShareable=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 \ >> +=C2=A0=C2=A0=C2=A0 GIC_BASER_SHAREABILITY(GITS_BASER, InnerShareable) >> +#define GITS_BASER_PAGE_SIZE_SHIFT=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 (8) >> +#define GITS_BASER_PAGE_SIZE_4K=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0 (0UL << >> GITS_BASER_PAGE_SIZE_SHIFT) >> +#define GITS_BASER_PAGE_SIZE_16K=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0 (1UL << >> GITS_BASER_PAGE_SIZE_SHIFT) >> +#define GITS_BASER_PAGE_SIZE_64K=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0 (2UL << >> GITS_BASER_PAGE_SIZE_SHIFT) >> +#define GITS_BASER_PAGE_SIZE_MASK=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= (3UL << >> GITS_BASER_PAGE_SIZE_SHIFT) >> +#define GITS_BASER_PAGES_MAX=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0=C2=A0=C2=A0 256 >> +#define GITS_BASER_PAGES_SHIFT=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0 (0) >> +#define GITS_BASER_NR_PAGES(r)=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0 (((r) & 0xff) + 1) >> +#define GITS_BASER_PHYS_ADDR_MASK=C2=A0=C2=A0=C2=A0 0xFFFFFFFFF000 >> + >> +#define GITS_BASER_TYPE_NONE=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0=C2=A0=C2=A0 0 >> +#define GITS_BASER_TYPE_DEVICE=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0 1 >> +#define GITS_BASER_TYPE_VCPU=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0=C2=A0=C2=A0 2 >> +#define GITS_BASER_TYPE_CPU=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 3 >=20 > '3' is one of the reserved values of the GITS_BASER.Type field, and > what do we expect with a "GITS_BASER_TYPE_CPU" table type? ;-) Yes I agree. This is code extracted from the irqchip header in Dec 2016. I should have checked again. I only use DEVICE and COLLECTION here. I will remove all the defines I am not using at the moment. I guess most of the defines related to memory/cache mgt are not mandated either. >=20 > I think we can copy (and might update in the future) all these > macros against the latest Linux kernel. >=20 >> +#define GITS_BASER_TYPE_COLLECTION=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 4 >> + >> +#define ITS_FLAGS_CMDQ_NEEDS_FLUSHING=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0=C2=A0=C2=A0 (1ULL << 0) > + >> +struct its_typer { >> +=C2=A0=C2=A0=C2=A0 unsigned int ite_size; >> +=C2=A0=C2=A0=C2=A0 unsigned int eventid_bits; >> +=C2=A0=C2=A0=C2=A0 unsigned int deviceid_bits; >> +=C2=A0=C2=A0=C2=A0 unsigned int collid_bits; >> +=C2=A0=C2=A0=C2=A0 unsigned int hw_collections; >> +=C2=A0=C2=A0=C2=A0 bool pta; >> +=C2=A0=C2=A0=C2=A0 bool cil; >> +=C2=A0=C2=A0=C2=A0 bool cct; >> +=C2=A0=C2=A0=C2=A0 bool phys_lpi; >> +=C2=A0=C2=A0=C2=A0 bool virt_lpi; >> +}; >> + >> +struct its_data { >> +=C2=A0=C2=A0=C2=A0 void *base; >> +=C2=A0=C2=A0=C2=A0 struct its_typer typer; >> +}; >> + >> +extern struct its_data its_data; >> + >> +#define gicv3_its_base()=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 (i= ts_data.base) >> + >> +extern void its_parse_typer(void); >> +extern void its_init(void); >> + >> +#endif /* !__ASSEMBLY__ */ >> +#endif /* _ASMARM_GIC_V3_ITS_H_ */ >> diff --git a/lib/arm/asm/gic.h b/lib/arm/asm/gic.h >> index 55dd84b..b44da9c 100644 >> --- a/lib/arm/asm/gic.h >> +++ b/lib/arm/asm/gic.h >> @@ -40,6 +40,7 @@ >> =C2=A0 =C2=A0 #include >> =C2=A0 #include >> +#include >> =C2=A0 =C2=A0 #define PPI(irq)=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0=C2=A0=C2=A0 ((irq) + 16) >> =C2=A0 #define SPI(irq)=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0=C2=A0 ((irq) + GIC_FIRST_SPI) >> diff --git a/lib/arm/gic-v3-its.c b/lib/arm/gic-v3-its.c >> new file mode 100644 >> index 0000000..34f4d0e >> --- /dev/null >> +++ b/lib/arm/gic-v3-its.c >> @@ -0,0 +1,41 @@ >> +/* >> + * Copyright (C) 2016, Red Hat Inc, Eric Auger >> + * >> + * This work is licensed under the terms of the GNU LGPL, version 2. >> + */ >> +#include >> + >> +struct its_data its_data; >> + >> +void its_parse_typer(void) >> +{ >> +=C2=A0=C2=A0=C2=A0 u64 typer =3D readq(gicv3_its_base() + GITS_TYPER)= ; >> + >> +=C2=A0=C2=A0=C2=A0 its_data.typer.ite_size =3D ((typer >> 4) & 0xf) += 1; >> +=C2=A0=C2=A0=C2=A0 its_data.typer.pta =3D typer & GITS_TYPER_PTA; >> +=C2=A0=C2=A0=C2=A0 its_data.typer.eventid_bits =3D >> +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 ((typer >> GITS_TYPER_IDBI= TS_SHIFT) & 0x1f) + 1; >> +=C2=A0=C2=A0=C2=A0 its_data.typer.deviceid_bits =3D GITS_TYPER_DEVBIT= S(typer) + 1; >=20 > No need to '+1'. As GITS_TYPER_DEVBITS already helps us to calculate > the implemented DeviceID bits. OK >=20 >> + >> +=C2=A0=C2=A0=C2=A0 its_data.typer.cil =3D (typer >> 36) & 0x1; >> +=C2=A0=C2=A0=C2=A0 if (its_data.typer.cil) >> +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 its_data.typer.collid_bits= =3D ((typer >> 32) & 0xf) + 1; >> +=C2=A0=C2=A0=C2=A0 else >> +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 its_data.typer.collid_bits= =3D 16; >> + >> +=C2=A0=C2=A0=C2=A0 its_data.typer.hw_collections =3D >> +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 (typer >> GITS_TYPER_HWCOL= LCNT_SHIFT) & 0xff; >> + >> +=C2=A0=C2=A0=C2=A0 its_data.typer.cct =3D typer & 0x4; >> +=C2=A0=C2=A0=C2=A0 its_data.typer.virt_lpi =3D typer & 0x2; >> +=C2=A0=C2=A0=C2=A0 its_data.typer.phys_lpi =3D typer & GITS_TYPER_PLP= IS; >=20 > Personally, mix using of GITS_TYPER_* macros and some magic constants t= o > parse the TYPER makes it a bit difficult to review the code. Maybe we > can have more such kinds of macros in the header file and get rid of al= l > hardcoded numbers? Sure I will clean that up. Thanks! Eric >=20 >=20 > Thanks, > Zenghui >=20 >=20 From MAILER-DAEMON Wed Dec 18 06:18:30 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1ihXLa-00006k-9E for mharc-qemu-arm@gnu.org; Wed, 18 Dec 2019 06:18:30 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:36000) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ihXLX-0008VB-Ic for qemu-arm@nongnu.org; Wed, 18 Dec 2019 06:18:28 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ihXLW-0000zM-GW for qemu-arm@nongnu.org; Wed, 18 Dec 2019 06:18:27 -0500 Received: from mout.kundenserver.de ([212.227.126.130]:39265) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1ihXLS-0000Hz-BI; Wed, 18 Dec 2019 06:18:22 -0500 Received: from [192.168.100.1] ([78.238.229.36]) by mrelayeu.kundenserver.de (mreue012 [213.165.67.103]) with ESMTPSA (Nemesis) id 1Mo6WJ-1hsqNC2nOt-00pgeU; Wed, 18 Dec 2019 12:18:13 +0100 Subject: Re: [PATCH 1/3] MAINTAINERS: Add hw/sd/ssi-sd.c in the SD section To: =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= , qemu-devel@nongnu.org Cc: QEMU Trivial , Esteban Bosse , qemu-arm@nongnu.org, Vladimir Sementsov-Ogievskiy , Peter Maydell References: <20191012065426.10772-1-philmd@redhat.com> <20191012065426.10772-2-philmd@redhat.com> <46d94900-e916-54e2-06e6-1963fbed3bb8@redhat.com> From: Laurent Vivier Autocrypt: addr=laurent@vivier.eu; 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Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.2.2 MIME-Version: 1.0 In-Reply-To: <46d94900-e916-54e2-06e6-1963fbed3bb8@redhat.com> Content-Type: text/plain; charset=utf-8 Content-Language: fr Content-Transfer-Encoding: 8bit X-Provags-ID: V03:K1:l/xGEgRKYjXPvP7jQ97OLkGJxmRbN7XfBZtzwebu296FMZF9PB5 OzSVuNvXeM/f72xtPyi6hvZnDS5KqmIqgaRKo3yYUe0r6pLjD68qCMcrclPbXGb6VcONMgZ NpYMH+u+JmGxEIJ/l7yRxbUhM+1qLFLaKVLt+/uqsYRcsOiue4jcfAZjkyHZ+lnOITTMCSA iDmiwau4tkXg+xlNI+GHQ== X-UI-Out-Filterresults: notjunk:1;V03:K0:3FGB5m0FLwE=:QntDuNVqTdITqF2FI9YdUB MK6yiGM2ElHAmh67cfaqHdYMQumCgKTQEffOQcqc5TBwIq6qpS/nZ3T9XVjV+MS35qVQblebE eNX98Wls2uAz8syJsxBbVx4PkSaeVLFsTpQU58v5GT59trzaxC9R9Ke5TuZrZL4vKL6bPwxkm OTojT4GCJGBs1qW77mOk+0GIfBC83PcCCvQtQ/omCr/gwKdpBFBt9xk9EreqRGSVwCUe16gg1 lWzTvvAEqFXTn/jcng2B0MlTsM3fu5mfBwZg6WuoO74WK5BplWFrYb5gZ+fUdrOzZvya88Pr/ sLwT/H8PgaTtwQjX4V6P1JK3Wv5OSBr556Xe7ZwR2FC0jljrO25e6cG53yrS4g4hlq5FXADV4 XeHSmgmYC7Zkqz7Nc0XoVSHt2o8DS6cWYJXISAqQS+2ZCIiiL5QdY2wQvS0LcEja60UwGH6BV 678lZE4bhDqKDZ6ombdJd0cQNXBfqXGuzKrAmzj3XQyPgy4Wh6xty+GYPk87h6qu0/3mI05SD oNvputVHo/HoR9+VFUo8moJYXVlo59JUQxLcNfdo/heuyC+NC3TTS7CeAx92VqhTXoDR6S1Ba tPCvtM3UZ4t3scmS4rZlMYstNrbBmmvetEnUAhFMCjuriUc/+x3Dsg9p9h40AYMAwtVn6FABQ 21sM+vJZwJhfsVFQ1CDHO1JUbBru81rpMfoer2keHuQEHgoAdvjhTmMT4ASSlKm16IPqwUbu6 AAbobpTBS3v2Sxl4CfltPBeFUWig72hgWiYrXeWCEg25FSHh8pvtT44bAO29RJ/NzunRmhoPa jfyjURlhG8LFx9ZKkmePbUDEB+SIFG0J80lwrzrCKNhEKday7kURbo8YPjZ/bDBmOhSX4u0LC DvTV0ffrQMh+iGzOxWegAe4gxTv+NuzbQE8umZqUE= X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 212.227.126.130 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 18 Dec 2019 11:18:28 -0000 Le 18/11/2019 à 13:26, Philippe Mathieu-Daudé a écrit : > Cc'ing qemu-trivial@ > > On 10/12/19 8:54 AM, Philippe Mathieu-Daudé wrote: >> The hw/sd/ssi-sd.c file is orphean, add it to the SD section. >> >> Signed-off-by: Philippe Mathieu-Daudé >> --- >>   MAINTAINERS | 1 + >>   1 file changed, 1 insertion(+) >> >> diff --git a/MAINTAINERS b/MAINTAINERS >> index 3ca814850e..47eae9fc46 100644 >> --- a/MAINTAINERS >> +++ b/MAINTAINERS >> @@ -1445,6 +1445,7 @@ S: Odd Fixes >>   F: include/hw/sd/sd* >>   F: hw/sd/core.c >>   F: hw/sd/sd* >> +F: hw/sd/ssi-sd.c >>   F: tests/sd* >>     USB >> > > Applied to my trivial-patches branch. Thanks, Laurent From MAILER-DAEMON Wed Dec 18 12:21:01 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1ihd0P-0007n7-GW for mharc-qemu-arm@gnu.org; Wed, 18 Dec 2019 12:21:01 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:37364) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ihd0J-0007j3-Jn for qemu-arm@nongnu.org; Wed, 18 Dec 2019 12:20:59 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ihd0E-0008FD-UJ for qemu-arm@nongnu.org; Wed, 18 Dec 2019 12:20:53 -0500 Received: from us-smtp-delivery-1.mimecast.com ([205.139.110.120]:37483 helo=us-smtp-1.mimecast.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1ihd0E-000870-Bp for qemu-arm@nongnu.org; Wed, 18 Dec 2019 12:20:50 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1576689648; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding; bh=D0xFFDti/vGXy58bqKD5OhN2HcF80Gcn3Awn01okJwQ=; b=h0pbIGqTxGsgtmt4ecsrpd1B8OMbBMqREV9c3HlIn36nVrOKEZ3MNxtBGGFr9zROA0jAZr 2/rUtolHRGpoNWhHOVyEku+HeccAj3p2pVOl904ImSyoqUmM8QK8Jl7IWBaScpIRSz4yOr 7roWaRqUHC9543GyW9GUjcDnyc9zpP0= Received: from mimecast-mx01.redhat.com (mimecast-mx01.redhat.com [209.132.183.4]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-310-t7rIPLpnM5O-B_mxO9_VMA-1; Wed, 18 Dec 2019 12:20:46 -0500 Received: from smtp.corp.redhat.com (int-mx07.intmail.prod.int.phx2.redhat.com [10.5.11.22]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx01.redhat.com (Postfix) with ESMTPS id 4F06DDC21; Wed, 18 Dec 2019 17:20:42 +0000 (UTC) Received: from x1w.redhat.com (ovpn-116-235.ams2.redhat.com [10.36.116.235]) by smtp.corp.redhat.com (Postfix) with ESMTPS id B7F94100EBA4; Wed, 18 Dec 2019 17:20:15 +0000 (UTC) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , "Gonglei (Arei)" , =?UTF-8?q?Marc-Andr=C3=A9=20Lureau?= , Paolo Bonzini , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Andrzej Zaborowski , Peter Maydell , "Michael S. Tsirkin" , Kevin Wolf , Max Reitz , "Edgar E. Iglesias" , Alistair Francis , Antony Pavlov , Igor Mitsyanko , Fabien Chouteau , KONRAD Frederic , Peter Chubb , Alberto Garcia , Michael Walle , Thomas Huth , Joel Stanley , Cornelia Huck , Halil Pasic , Christian Borntraeger , Laurent Vivier , Amit Shah , Corey Minyard , Paul Burton , Aleksandar Rikalo , Aurelien Jarno , Aleksandar Markovic , Palmer Dabbelt , Sagar Karandikar , Bastian Koppelmann , Gerd Hoffmann , Samuel Thibault , "Dr. David Alan Gilbert" , Markus Armbruster , Zhang Chen , Li Zhijian , Jason Wang , qemu-arm@nongnu.org, qemu-block@nongnu.org, qemu-s390x@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH v2 00/14] chardev: Use QEMUChrEvent enum in IOEventHandler typedef Date: Wed, 18 Dec 2019 18:19:55 +0100 Message-Id: <20191218172009.8868-1-philmd@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.84 on 10.5.11.22 X-MC-Unique: t7rIPLpnM5O-B_mxO9_VMA-1 X-Mimecast-Spam-Score: 0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 205.139.110.120 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 18 Dec 2019 17:21:00 -0000 Hi, After this chat on #qemu IRC: 13:20 so what is the difference between a IOReadHandler and IOEve= ntHandler? 13:25 stsquad: one is in-band and the other out-of-band? 13:26 f4bug: ahh yes it seems so - connect/disconnect etc... 13:27 see QEMUChrEvent for IOEventHandler I thought it might be a good opportunity to make the IOEventHandler typedef meaning more obvious, by using the QEMUChrEvent enum. To be able to build I had to explicit all enums ignored in the switch(event) statement by these frontends. Then I used a coccinelle spatch to change the various IOEventHandler. I don't think the last patch can be split, but suggestions are welcome! Regards, Phil. v2: - do blindly ignore all events using a 'default' case. Philippe Mathieu-Daud=C3=A9 (14): hw/ipmi: Remove unnecessary declarations hw/ipmi: Explicit we ignore some QEMUChrEvent in IOEventHandler hw/char/terminal3270: Explicit ignored QEMUChrEvent in IOEventHandler hw/usb/dev-serial: Explicit we ignore few QEMUChrEvent in IOEventHandler hw/usb/redirect: Explicit we ignore few QEMUChrEvent in IOEventHandler ccid-card-passthru: Explicit we ignore QEMUChrEvent in IOEventHandler vhost-user-crypto: Explicit we ignore some QEMUChrEvent in IOEventHandler vhost-user-net: Explicit we ignore few QEMUChrEvent in IOEventHandler vhost-user-blk: Explicit we ignore few QEMUChrEvent in IOEventHandler virtio-console: Explicit we ignore some QEMUChrEvent in IOEventHandler monitor/qmp: Explicit we ignore few QEMUChrEvent in IOEventHandler monitor/hmp: Explicit we ignore a QEMUChrEvent in IOEventHandler chardev/char: Explicit we ignore some QEMUChrEvent in IOEventHandler chardev: Use QEMUChrEvent enum in IOEventHandler typedef include/chardev/char-fe.h | 2 +- include/chardev/char-mux.h | 2 +- include/chardev/char.h | 4 ++-- backends/cryptodev-vhost-user.c | 7 ++++++- chardev/char-mux.c | 8 ++++---- chardev/char.c | 9 +++++++-- gdbstub.c | 2 +- hw/arm/pxa2xx.c | 2 +- hw/arm/strongarm.c | 2 +- hw/block/vhost-user-blk.c | 7 ++++++- hw/char/cadence_uart.c | 2 +- hw/char/digic-uart.c | 2 +- hw/char/escc.c | 2 +- hw/char/etraxfs_ser.c | 2 +- hw/char/exynos4210_uart.c | 2 +- hw/char/grlib_apbuart.c | 2 +- hw/char/imx_serial.c | 2 +- hw/char/ipoctal232.c | 2 +- hw/char/lm32_juart.c | 2 +- hw/char/lm32_uart.c | 2 +- hw/char/mcf_uart.c | 2 +- hw/char/milkymist-uart.c | 2 +- hw/char/nrf51_uart.c | 2 +- hw/char/pl011.c | 2 +- hw/char/serial.c | 2 +- hw/char/sh_serial.c | 2 +- hw/char/terminal3270.c | 7 ++++++- hw/char/virtio-console.c | 7 ++++++- hw/char/xilinx_uartlite.c | 2 +- hw/ipmi/ipmi_bmc_extern.c | 12 +++++++----- hw/mips/boston.c | 2 +- hw/mips/mips_malta.c | 2 +- hw/riscv/riscv_htif.c | 2 +- hw/riscv/sifive_uart.c | 2 +- hw/usb/ccid-card-passthru.c | 7 ++++++- hw/usb/dev-serial.c | 6 +++++- hw/usb/redirect.c | 7 ++++++- monitor/hmp.c | 6 +++++- monitor/qmp.c | 7 ++++++- net/filter-mirror.c | 2 +- net/vhost-user.c | 9 +++++++-- qtest.c | 2 +- tests/test-char.c | 6 +++--- tests/vhost-user-test.c | 2 +- 44 files changed, 111 insertions(+), 56 deletions(-) Cc: "Gonglei (Arei)" Cc: "Marc-Andr=C3=A9 Lureau" Cc: Paolo Bonzini Cc: "Alex Benn=C3=A9e" Cc: "Philippe Mathieu-Daud=C3=A9" Cc: Andrzej Zaborowski Cc: Peter Maydell Cc: "Michael S. Tsirkin" Cc: Kevin Wolf Cc: Max Reitz Cc: "Edgar E. Iglesias" Cc: Alistair Francis Cc: Antony Pavlov Cc: Igor Mitsyanko Cc: Fabien Chouteau Cc: KONRAD Frederic Cc: Peter Chubb Cc: Alberto Garcia Cc: Michael Walle Cc: Thomas Huth Cc: Joel Stanley Cc: Cornelia Huck Cc: Halil Pasic Cc: Christian Borntraeger Cc: Laurent Vivier Cc: Amit Shah Cc: Corey Minyard Cc: Paul Burton Cc: Aleksandar Rikalo Cc: Aurelien Jarno Cc: Aleksandar Markovic Cc: Palmer Dabbelt Cc: Sagar Karandikar Cc: Bastian Koppelmann Cc: Gerd Hoffmann Cc: Samuel Thibault Cc: "Dr. David Alan Gilbert" Cc: Markus Armbruster Cc: Zhang Chen Cc: Li Zhijian Cc: Jason Wang Cc: qemu-arm@nongnu.org Cc: qemu-block@nongnu.org Cc: qemu-s390x@nongnu.org Cc: qemu-riscv@nongnu.org --=20 2.21.0 From MAILER-DAEMON Wed Dec 18 12:22:08 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1ihd1T-0000pL-SO for mharc-qemu-arm@gnu.org; Wed, 18 Dec 2019 12:22:07 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:44316) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ihd1N-0000fm-Pk for qemu-arm@nongnu.org; Wed, 18 Dec 2019 12:22:06 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ihd1E-0004G2-7x for qemu-arm@nongnu.org; Wed, 18 Dec 2019 12:22:01 -0500 Received: from us-smtp-delivery-1.mimecast.com ([207.211.31.120]:35180 helo=us-smtp-1.mimecast.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1ihd1D-0004Bb-FE for qemu-arm@nongnu.org; Wed, 18 Dec 2019 12:21:52 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1576689708; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=525ClwqyHmAK0f1GceJlwmwpPfqMT3AVM4HwwB7KZ10=; b=GGmAKjOW8vBQAGrBsze+MoLMf4Q3+jxJ+LWVVl3kD0bqtnWTg3F+EkeAnNPR32y00jIB0+ A40KAVswRVSSLXMWmhtmJVsn8E7FGe27zNJhJcvzojN33motpSG9FOxwPsCLVtZM1pQAO0 eoRvQQDIiudgIyXew1IKmv5cf4hWqrk= Received: from mimecast-mx01.redhat.com (mimecast-mx01.redhat.com [209.132.183.4]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-173-usGP6UGCPxa86cxFS3wPjg-1; Wed, 18 Dec 2019 12:21:47 -0500 Received: from smtp.corp.redhat.com (int-mx07.intmail.prod.int.phx2.redhat.com [10.5.11.22]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx01.redhat.com (Postfix) with ESMTPS id 2D404100550E; Wed, 18 Dec 2019 17:21:42 +0000 (UTC) Received: from x1w.redhat.com (ovpn-116-235.ams2.redhat.com [10.36.116.235]) by smtp.corp.redhat.com (Postfix) with ESMTPS id 996DB1001281; Wed, 18 Dec 2019 17:21:27 +0000 (UTC) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , "Gonglei (Arei)" , =?UTF-8?q?Marc-Andr=C3=A9=20Lureau?= , Paolo Bonzini , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Andrzej Zaborowski , Peter Maydell , "Michael S. Tsirkin" , Kevin Wolf , Max Reitz , "Edgar E. Iglesias" , Alistair Francis , Antony Pavlov , Igor Mitsyanko , Fabien Chouteau , KONRAD Frederic , Peter Chubb , Alberto Garcia , Michael Walle , Thomas Huth , Joel Stanley , Cornelia Huck , Halil Pasic , Christian Borntraeger , Laurent Vivier , Amit Shah , Corey Minyard , Paul Burton , Aleksandar Rikalo , Aurelien Jarno , Aleksandar Markovic , Palmer Dabbelt , Sagar Karandikar , Bastian Koppelmann , Gerd Hoffmann , Samuel Thibault , "Dr. David Alan Gilbert" , Markus Armbruster , Zhang Chen , Li Zhijian , Jason Wang , qemu-arm@nongnu.org, qemu-block@nongnu.org, qemu-s390x@nongnu.org, qemu-riscv@nongnu.org Subject: [RFC PATCH v2 14/14] chardev: Use QEMUChrEvent enum in IOEventHandler typedef Date: Wed, 18 Dec 2019 18:20:09 +0100 Message-Id: <20191218172009.8868-15-philmd@redhat.com> In-Reply-To: <20191218172009.8868-1-philmd@redhat.com> References: <20191218172009.8868-1-philmd@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.84 on 10.5.11.22 X-MC-Unique: usGP6UGCPxa86cxFS3wPjg-1 X-Mimecast-Spam-Score: 0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 207.211.31.120 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 18 Dec 2019 17:22:06 -0000 The Chardev events are listed in the QEMUChrEvent enum. By using the enum in the IOEventHandler typedef we: - make the IOEventHandler type more explicit (this handler process out-of-band information, while the IOReadHandler is in-band), - help static code analyzers. This patch was produced with the following spatch script: @match@ expression backend, opaque, context, set_open; identifier fd_can_read, fd_read, fd_event, be_change; @@ qemu_chr_fe_set_handlers(backend, fd_can_read, fd_read, fd_event, be_change, opaque, context, set_open); @depends on match@ identifier opaque, event; identifier match.fd_event; @@ static -void fd_event(void *opaque, int event) +void fd_event(void *opaque, QEMUChrEvent event) { ... } Then the following files were manually modified: - include/chardev/char-fe.h - include/chardev/char.h - include/chardev/char-mux.h - chardev/char.c - chardev/char-mux.c Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- Cc: "Gonglei (Arei)" Cc: "Marc-Andr=C3=A9 Lureau" Cc: Paolo Bonzini Cc: "Alex Benn=C3=A9e" Cc: "Philippe Mathieu-Daud=C3=A9" Cc: Andrzej Zaborowski Cc: Peter Maydell Cc: "Michael S. Tsirkin" Cc: Kevin Wolf Cc: Max Reitz Cc: "Edgar E. Iglesias" Cc: Alistair Francis Cc: Antony Pavlov Cc: Igor Mitsyanko Cc: Fabien Chouteau Cc: KONRAD Frederic Cc: Peter Chubb Cc: Alberto Garcia Cc: Michael Walle Cc: Thomas Huth Cc: Joel Stanley Cc: Cornelia Huck Cc: Halil Pasic Cc: Christian Borntraeger Cc: Laurent Vivier Cc: Amit Shah Cc: Corey Minyard Cc: Paul Burton Cc: Aleksandar Rikalo Cc: Aurelien Jarno Cc: Aleksandar Markovic Cc: Palmer Dabbelt Cc: Sagar Karandikar Cc: Bastian Koppelmann Cc: Gerd Hoffmann Cc: Samuel Thibault Cc: "Dr. David Alan Gilbert" Cc: Markus Armbruster Cc: Zhang Chen Cc: Li Zhijian Cc: Jason Wang Cc: qemu-arm@nongnu.org Cc: qemu-block@nongnu.org Cc: qemu-s390x@nongnu.org Cc: qemu-riscv@nongnu.org --- include/chardev/char-fe.h | 2 +- include/chardev/char-mux.h | 2 +- include/chardev/char.h | 4 ++-- backends/cryptodev-vhost-user.c | 2 +- chardev/char-mux.c | 8 ++++---- chardev/char.c | 4 ++-- gdbstub.c | 2 +- hw/arm/pxa2xx.c | 2 +- hw/arm/strongarm.c | 2 +- hw/block/vhost-user-blk.c | 2 +- hw/char/cadence_uart.c | 2 +- hw/char/digic-uart.c | 2 +- hw/char/escc.c | 2 +- hw/char/etraxfs_ser.c | 2 +- hw/char/exynos4210_uart.c | 2 +- hw/char/grlib_apbuart.c | 2 +- hw/char/imx_serial.c | 2 +- hw/char/ipoctal232.c | 2 +- hw/char/lm32_juart.c | 2 +- hw/char/lm32_uart.c | 2 +- hw/char/mcf_uart.c | 2 +- hw/char/milkymist-uart.c | 2 +- hw/char/nrf51_uart.c | 2 +- hw/char/pl011.c | 2 +- hw/char/serial.c | 2 +- hw/char/sh_serial.c | 2 +- hw/char/terminal3270.c | 2 +- hw/char/virtio-console.c | 2 +- hw/char/xilinx_uartlite.c | 2 +- hw/ipmi/ipmi_bmc_extern.c | 2 +- hw/mips/boston.c | 2 +- hw/mips/mips_malta.c | 2 +- hw/riscv/riscv_htif.c | 2 +- hw/riscv/sifive_uart.c | 2 +- hw/usb/ccid-card-passthru.c | 2 +- hw/usb/dev-serial.c | 2 +- hw/usb/redirect.c | 2 +- monitor/hmp.c | 2 +- monitor/qmp.c | 2 +- net/filter-mirror.c | 2 +- net/vhost-user.c | 4 ++-- qtest.c | 2 +- tests/test-char.c | 6 +++--- tests/vhost-user-test.c | 2 +- 44 files changed, 52 insertions(+), 52 deletions(-) diff --git a/include/chardev/char-fe.h b/include/chardev/char-fe.h index 67601dc9a4..a553843364 100644 --- a/include/chardev/char-fe.h +++ b/include/chardev/char-fe.h @@ -4,7 +4,7 @@ #include "chardev/char.h" #include "qemu/main-loop.h" =20 -typedef void IOEventHandler(void *opaque, int event); +typedef void IOEventHandler(void *opaque, QEMUChrEvent event); typedef int BackendChangeHandler(void *opaque); =20 /* This is the backend as seen by frontend, the actual backend is diff --git a/include/chardev/char-mux.h b/include/chardev/char-mux.h index 572cefd517..417fe32eed 100644 --- a/include/chardev/char-mux.h +++ b/include/chardev/char-mux.h @@ -56,6 +56,6 @@ typedef struct MuxChardev { object_dynamic_cast(OBJECT(chr), TYPE_CHARDEV_MUX) =20 void mux_set_focus(Chardev *chr, int focus); -void mux_chr_send_all_event(Chardev *chr, int event); +void mux_chr_send_all_event(Chardev *chr, QEMUChrEvent event); =20 #endif /* CHAR_MUX_H */ diff --git a/include/chardev/char.h b/include/chardev/char.h index 087b202b62..00589a6025 100644 --- a/include/chardev/char.h +++ b/include/chardev/char.h @@ -210,7 +210,7 @@ void qemu_chr_be_update_read_handlers(Chardev *s, * * Send an event from the back end to the front end. */ -void qemu_chr_be_event(Chardev *s, int event); +void qemu_chr_be_event(Chardev *s, QEMUChrEvent event); =20 int qemu_chr_add_client(Chardev *s, int fd); Chardev *qemu_chr_find(const char *name); @@ -273,7 +273,7 @@ typedef struct ChardevClass { void (*chr_accept_input)(Chardev *chr); void (*chr_set_echo)(Chardev *chr, bool echo); void (*chr_set_fe_open)(Chardev *chr, int fe_open); - void (*chr_be_event)(Chardev *s, int event); + void (*chr_be_event)(Chardev *s, QEMUChrEvent event); /* Return 0 if succeeded, 1 if failed */ int (*chr_machine_done)(Chardev *chr); } ChardevClass; diff --git a/backends/cryptodev-vhost-user.c b/backends/cryptodev-vhost-use= r.c index f1b407955f..6edada8e9e 100644 --- a/backends/cryptodev-vhost-user.c +++ b/backends/cryptodev-vhost-user.c @@ -152,7 +152,7 @@ cryptodev_vhost_claim_chardev(CryptoDevBackendVhostUser= *s, return chr; } =20 -static void cryptodev_vhost_user_event(void *opaque, int event) +static void cryptodev_vhost_user_event(void *opaque, QEMUChrEvent event) { CryptoDevBackendVhostUser *s =3D opaque; CryptoDevBackend *b =3D CRYPTODEV_BACKEND(s); diff --git a/chardev/char-mux.c b/chardev/char-mux.c index 200c62a0d0..46c44af67c 100644 --- a/chardev/char-mux.c +++ b/chardev/char-mux.c @@ -117,7 +117,7 @@ static void mux_print_help(Chardev *chr) } } =20 -static void mux_chr_send_event(MuxChardev *d, int mux_nr, int event) +static void mux_chr_send_event(MuxChardev *d, int mux_nr, QEMUChrEvent eve= nt) { CharBackend *be =3D d->backends[mux_nr]; =20 @@ -126,7 +126,7 @@ static void mux_chr_send_event(MuxChardev *d, int mux_n= r, int event) } } =20 -static void mux_chr_be_event(Chardev *chr, int event) +static void mux_chr_be_event(Chardev *chr, QEMUChrEvent event) { MuxChardev *d =3D MUX_CHARDEV(chr); =20 @@ -232,7 +232,7 @@ static void mux_chr_read(void *opaque, const uint8_t *b= uf, int size) } } =20 -void mux_chr_send_all_event(Chardev *chr, int event) +void mux_chr_send_all_event(Chardev *chr, QEMUChrEvent event) { MuxChardev *d =3D MUX_CHARDEV(chr); int i; @@ -247,7 +247,7 @@ void mux_chr_send_all_event(Chardev *chr, int event) } } =20 -static void mux_chr_event(void *opaque, int event) +static void mux_chr_event(void *opaque, QEMUChrEvent event) { mux_chr_send_all_event(CHARDEV(opaque), event); } diff --git a/chardev/char.c b/chardev/char.c index 739da1155b..4f598f8175 100644 --- a/chardev/char.c +++ b/chardev/char.c @@ -48,7 +48,7 @@ static Object *get_chardevs_root(void) return container_get(object_get_root(), "/chardevs"); } =20 -static void chr_be_event(Chardev *s, int event) +static void chr_be_event(Chardev *s, QEMUChrEvent event) { CharBackend *be =3D s->be; =20 @@ -59,7 +59,7 @@ static void chr_be_event(Chardev *s, int event) be->chr_event(be->opaque, event); } =20 -void qemu_chr_be_event(Chardev *s, int event) +void qemu_chr_be_event(Chardev *s, QEMUChrEvent event) { /* Keep track if the char device is open */ switch (event) { diff --git a/gdbstub.c b/gdbstub.c index 4cf8af365e..ce304ff482 100644 --- a/gdbstub.c +++ b/gdbstub.c @@ -3171,7 +3171,7 @@ static void gdb_chr_receive(void *opaque, const uint8= _t *buf, int size) } } =20 -static void gdb_chr_event(void *opaque, int event) +static void gdb_chr_event(void *opaque, QEMUChrEvent event) { int i; GDBState *s =3D (GDBState *) opaque; diff --git a/hw/arm/pxa2xx.c b/hw/arm/pxa2xx.c index cdafde2f76..950ff4239a 100644 --- a/hw/arm/pxa2xx.c +++ b/hw/arm/pxa2xx.c @@ -1955,7 +1955,7 @@ static void pxa2xx_fir_rx(void *opaque, const uint8_t= *buf, int size) pxa2xx_fir_update(s); } =20 -static void pxa2xx_fir_event(void *opaque, int event) +static void pxa2xx_fir_event(void *opaque, QEMUChrEvent event) { } =20 diff --git a/hw/arm/strongarm.c b/hw/arm/strongarm.c index 6bee034914..c6776e8479 100644 --- a/hw/arm/strongarm.c +++ b/hw/arm/strongarm.c @@ -1093,7 +1093,7 @@ static void strongarm_uart_receive(void *opaque, cons= t uint8_t *buf, int size) strongarm_uart_update_int_status(s); } =20 -static void strongarm_uart_event(void *opaque, int event) +static void strongarm_uart_event(void *opaque, QEMUChrEvent event) { StrongARMUARTState *s =3D opaque; if (event =3D=3D CHR_EVENT_BREAK) { diff --git a/hw/block/vhost-user-blk.c b/hw/block/vhost-user-blk.c index ccaf2ad978..98b383f90e 100644 --- a/hw/block/vhost-user-blk.c +++ b/hw/block/vhost-user-blk.c @@ -361,7 +361,7 @@ static gboolean vhost_user_blk_watch(GIOChannel *chan, = GIOCondition cond, return true; } =20 -static void vhost_user_blk_event(void *opaque, int event) +static void vhost_user_blk_event(void *opaque, QEMUChrEvent event) { DeviceState *dev =3D opaque; VirtIODevice *vdev =3D VIRTIO_DEVICE(dev); diff --git a/hw/char/cadence_uart.c b/hw/char/cadence_uart.c index 0e315b2376..51791bd217 100644 --- a/hw/char/cadence_uart.c +++ b/hw/char/cadence_uart.c @@ -348,7 +348,7 @@ static void uart_receive(void *opaque, const uint8_t *b= uf, int size) } } =20 -static void uart_event(void *opaque, int event) +static void uart_event(void *opaque, QEMUChrEvent event) { CadenceUARTState *s =3D opaque; uint8_t buf =3D '\0'; diff --git a/hw/char/digic-uart.c b/hw/char/digic-uart.c index 974a2619dd..033eba0a6a 100644 --- a/hw/char/digic-uart.c +++ b/hw/char/digic-uart.c @@ -131,7 +131,7 @@ static void uart_rx(void *opaque, const uint8_t *buf, i= nt size) s->reg_rx =3D *buf; } =20 -static void uart_event(void *opaque, int event) +static void uart_event(void *opaque, QEMUChrEvent event) { } =20 diff --git a/hw/char/escc.c b/hw/char/escc.c index 8f7bf322cb..c40c1d28f1 100644 --- a/hw/char/escc.c +++ b/hw/char/escc.c @@ -634,7 +634,7 @@ static void serial_receive1(void *opaque, const uint8_t= *buf, int size) serial_receive_byte(s, buf[0]); } =20 -static void serial_event(void *opaque, int event) +static void serial_event(void *opaque, QEMUChrEvent event) { ESCCChannelState *s =3D opaque; if (event =3D=3D CHR_EVENT_BREAK) diff --git a/hw/char/etraxfs_ser.c b/hw/char/etraxfs_ser.c index 15ac12ef22..f34f767c60 100644 --- a/hw/char/etraxfs_ser.c +++ b/hw/char/etraxfs_ser.c @@ -202,7 +202,7 @@ static int serial_can_receive(void *opaque) return sizeof(s->rx_fifo) - s->rx_fifo_len; } =20 -static void serial_event(void *opaque, int event) +static void serial_event(void *opaque, QEMUChrEvent event) { =20 } diff --git a/hw/char/exynos4210_uart.c b/hw/char/exynos4210_uart.c index d6b6b62366..7e5c5ce789 100644 --- a/hw/char/exynos4210_uart.c +++ b/hw/char/exynos4210_uart.c @@ -528,7 +528,7 @@ static void exynos4210_uart_receive(void *opaque, const= uint8_t *buf, int size) } =20 =20 -static void exynos4210_uart_event(void *opaque, int event) +static void exynos4210_uart_event(void *opaque, QEMUChrEvent event) { Exynos4210UartState *s =3D (Exynos4210UartState *)opaque; =20 diff --git a/hw/char/grlib_apbuart.c b/hw/char/grlib_apbuart.c index fe3cbf41a3..8e59c3bc6e 100644 --- a/hw/char/grlib_apbuart.c +++ b/hw/char/grlib_apbuart.c @@ -155,7 +155,7 @@ static void grlib_apbuart_receive(void *opaque, const u= int8_t *buf, int size) } } =20 -static void grlib_apbuart_event(void *opaque, int event) +static void grlib_apbuart_event(void *opaque, QEMUChrEvent event) { trace_grlib_apbuart_event(event); } diff --git a/hw/char/imx_serial.c b/hw/char/imx_serial.c index fddde9b43d..d09c210709 100644 --- a/hw/char/imx_serial.c +++ b/hw/char/imx_serial.c @@ -323,7 +323,7 @@ static void imx_receive(void *opaque, const uint8_t *bu= f, int size) imx_put_data(opaque, *buf); } =20 -static void imx_event(void *opaque, int event) +static void imx_event(void *opaque, QEMUChrEvent event) { if (event =3D=3D CHR_EVENT_BREAK) { imx_put_data(opaque, URXD_BRK | URXD_FRMERR | URXD_ERR); diff --git a/hw/char/ipoctal232.c b/hw/char/ipoctal232.c index 66c163ba26..80e9dff701 100644 --- a/hw/char/ipoctal232.c +++ b/hw/char/ipoctal232.c @@ -503,7 +503,7 @@ static void hostdev_receive(void *opaque, const uint8_t= *buf, int size) } } =20 -static void hostdev_event(void *opaque, int event) +static void hostdev_event(void *opaque, QEMUChrEvent event) { SCC2698Channel *ch =3D opaque; switch (event) { diff --git a/hw/char/lm32_juart.c b/hw/char/lm32_juart.c index e0b1bd6555..da9dd5668b 100644 --- a/hw/char/lm32_juart.c +++ b/hw/char/lm32_juart.c @@ -104,7 +104,7 @@ static int juart_can_rx(void *opaque) return !(s->jrx & JRX_FULL); } =20 -static void juart_event(void *opaque, int event) +static void juart_event(void *opaque, QEMUChrEvent event) { } =20 diff --git a/hw/char/lm32_uart.c b/hw/char/lm32_uart.c index 32f29c44cf..8d7a475c91 100644 --- a/hw/char/lm32_uart.c +++ b/hw/char/lm32_uart.c @@ -235,7 +235,7 @@ static int uart_can_rx(void *opaque) return !(s->regs[R_LSR] & LSR_DR); } =20 -static void uart_event(void *opaque, int event) +static void uart_event(void *opaque, QEMUChrEvent event) { } =20 diff --git a/hw/char/mcf_uart.c b/hw/char/mcf_uart.c index 58323baf43..2de3680b5d 100644 --- a/hw/char/mcf_uart.c +++ b/hw/char/mcf_uart.c @@ -256,7 +256,7 @@ static void mcf_uart_push_byte(mcf_uart_state *s, uint8= _t data) mcf_uart_update(s); } =20 -static void mcf_uart_event(void *opaque, int event) +static void mcf_uart_event(void *opaque, QEMUChrEvent event) { mcf_uart_state *s =3D (mcf_uart_state *)opaque; =20 diff --git a/hw/char/milkymist-uart.c b/hw/char/milkymist-uart.c index c358ca07f3..1c7b61480e 100644 --- a/hw/char/milkymist-uart.c +++ b/hw/char/milkymist-uart.c @@ -180,7 +180,7 @@ static int uart_can_rx(void *opaque) return !(s->regs[R_STAT] & STAT_RX_EVT); } =20 -static void uart_event(void *opaque, int event) +static void uart_event(void *opaque, QEMUChrEvent event) { } =20 diff --git a/hw/char/nrf51_uart.c b/hw/char/nrf51_uart.c index 2777afe366..b67fd21089 100644 --- a/hw/char/nrf51_uart.c +++ b/hw/char/nrf51_uart.c @@ -245,7 +245,7 @@ static int uart_can_receive(void *opaque) return s->rx_started ? (UART_FIFO_LENGTH - s->rx_fifo_len) : 0; } =20 -static void uart_event(void *opaque, int event) +static void uart_event(void *opaque, QEMUChrEvent event) { NRF51UARTState *s =3D NRF51_UART(opaque); =20 diff --git a/hw/char/pl011.c b/hw/char/pl011.c index 84ad8ff9fb..23cd544cc5 100644 --- a/hw/char/pl011.c +++ b/hw/char/pl011.c @@ -280,7 +280,7 @@ static void pl011_receive(void *opaque, const uint8_t *= buf, int size) pl011_put_fifo(opaque, *buf); } =20 -static void pl011_event(void *opaque, int event) +static void pl011_event(void *opaque, QEMUChrEvent event) { if (event =3D=3D CHR_EVENT_BREAK) pl011_put_fifo(opaque, 0x400); diff --git a/hw/char/serial.c b/hw/char/serial.c index b4aa250950..992b5ee944 100644 --- a/hw/char/serial.c +++ b/hw/char/serial.c @@ -634,7 +634,7 @@ static void serial_receive1(void *opaque, const uint8_t= *buf, int size) serial_update_irq(s); } =20 -static void serial_event(void *opaque, int event) +static void serial_event(void *opaque, QEMUChrEvent event) { SerialState *s =3D opaque; DPRINTF("event %x\n", event); diff --git a/hw/char/sh_serial.c b/hw/char/sh_serial.c index 07dc16be13..167f4d8cb9 100644 --- a/hw/char/sh_serial.c +++ b/hw/char/sh_serial.c @@ -358,7 +358,7 @@ static void sh_serial_receive1(void *opaque, const uint= 8_t *buf, int size) } } =20 -static void sh_serial_event(void *opaque, int event) +static void sh_serial_event(void *opaque, QEMUChrEvent event) { sh_serial_state *s =3D opaque; if (event =3D=3D CHR_EVENT_BREAK) diff --git a/hw/char/terminal3270.c b/hw/char/terminal3270.c index 2aab04fd4b..f7aba12565 100644 --- a/hw/char/terminal3270.c +++ b/hw/char/terminal3270.c @@ -142,7 +142,7 @@ static void terminal_read(void *opaque, const uint8_t *= buf, int size) } } =20 -static void chr_event(void *opaque, int event) +static void chr_event(void *opaque, QEMUChrEvent event) { Terminal3270 *t =3D opaque; CcwDevice *ccw_dev =3D CCW_DEVICE(t); diff --git a/hw/char/virtio-console.c b/hw/char/virtio-console.c index cbb304d270..a7d34fe0ed 100644 --- a/hw/char/virtio-console.c +++ b/hw/char/virtio-console.c @@ -145,7 +145,7 @@ static void chr_read(void *opaque, const uint8_t *buf, = int size) virtio_serial_write(port, buf, size); } =20 -static void chr_event(void *opaque, int event) +static void chr_event(void *opaque, QEMUChrEvent event) { VirtConsole *vcon =3D opaque; VirtIOSerialPort *port =3D VIRTIO_SERIAL_PORT(vcon); diff --git a/hw/char/xilinx_uartlite.c b/hw/char/xilinx_uartlite.c index 2c47275068..aa6bf02e21 100644 --- a/hw/char/xilinx_uartlite.c +++ b/hw/char/xilinx_uartlite.c @@ -206,7 +206,7 @@ static int uart_can_rx(void *opaque) return s->rx_fifo_len < sizeof(s->rx_fifo); } =20 -static void uart_event(void *opaque, int event) +static void uart_event(void *opaque, QEMUChrEvent event) { =20 } diff --git a/hw/ipmi/ipmi_bmc_extern.c b/hw/ipmi/ipmi_bmc_extern.c index adf2afe728..16a4117ab0 100644 --- a/hw/ipmi/ipmi_bmc_extern.c +++ b/hw/ipmi/ipmi_bmc_extern.c @@ -379,7 +379,7 @@ static void receive(void *opaque, const uint8_t *buf, i= nt size) handle_hw_op(ibe, hw_op); } =20 -static void chr_event(void *opaque, int event) +static void chr_event(void *opaque, QEMUChrEvent event) { IPMIBmcExtern *ibe =3D opaque; IPMIInterface *s =3D ibe->parent.intf; diff --git a/hw/mips/boston.c b/hw/mips/boston.c index ca7d813a52..29b476b4bd 100644 --- a/hw/mips/boston.c +++ b/hw/mips/boston.c @@ -98,7 +98,7 @@ enum boston_plat_reg { PLAT_SYS_CTL =3D 0x48, }; =20 -static void boston_lcd_event(void *opaque, int event) +static void boston_lcd_event(void *opaque, QEMUChrEvent event) { BostonState *s =3D opaque; if (event =3D=3D CHR_EVENT_OPENED && !s->lcd_inited) { diff --git a/hw/mips/mips_malta.c b/hw/mips/mips_malta.c index 783cd99848..72c03baa8e 100644 --- a/hw/mips/mips_malta.c +++ b/hw/mips/mips_malta.c @@ -545,7 +545,7 @@ static void malta_fpga_reset(void *opaque) snprintf(s->display_text, 9, " "); } =20 -static void malta_fgpa_display_event(void *opaque, int event) +static void malta_fgpa_display_event(void *opaque, QEMUChrEvent event) { MaltaFPGAState *s =3D opaque; =20 diff --git a/hw/riscv/riscv_htif.c b/hw/riscv/riscv_htif.c index 4f7b11dc37..ca87a5cf9f 100644 --- a/hw/riscv/riscv_htif.c +++ b/hw/riscv/riscv_htif.c @@ -96,7 +96,7 @@ static void htif_recv(void *opaque, const uint8_t *buf, i= nt size) * Called by the char dev to supply special events to the HTIF console. * Not used for HTIF. */ -static void htif_event(void *opaque, int event) +static void htif_event(void *opaque, QEMUChrEvent event) { =20 } diff --git a/hw/riscv/sifive_uart.c b/hw/riscv/sifive_uart.c index a403ae90f5..9350482662 100644 --- a/hw/riscv/sifive_uart.c +++ b/hw/riscv/sifive_uart.c @@ -162,7 +162,7 @@ static int uart_can_rx(void *opaque) return s->rx_fifo_len < sizeof(s->rx_fifo); } =20 -static void uart_event(void *opaque, int event) +static void uart_event(void *opaque, QEMUChrEvent event) { } =20 diff --git a/hw/usb/ccid-card-passthru.c b/hw/usb/ccid-card-passthru.c index e53696c07a..3d40b700db 100644 --- a/hw/usb/ccid-card-passthru.c +++ b/hw/usb/ccid-card-passthru.c @@ -307,7 +307,7 @@ static void ccid_card_vscard_read(void *opaque, const u= int8_t *buf, int size) } } =20 -static void ccid_card_vscard_event(void *opaque, int event) +static void ccid_card_vscard_event(void *opaque, QEMUChrEvent event) { PassthruState *card =3D opaque; =20 diff --git a/hw/usb/dev-serial.c b/hw/usb/dev-serial.c index 2ba6870b37..9646fe77da 100644 --- a/hw/usb/dev-serial.c +++ b/hw/usb/dev-serial.c @@ -461,7 +461,7 @@ static void usb_serial_read(void *opaque, const uint8_t= *buf, int size) s->recv_used +=3D size; } =20 -static void usb_serial_event(void *opaque, int event) +static void usb_serial_event(void *opaque, QEMUChrEvent event) { USBSerialState *s =3D opaque; =20 diff --git a/hw/usb/redirect.c b/hw/usb/redirect.c index ddc1a59cb4..0068aa8a19 100644 --- a/hw/usb/redirect.c +++ b/hw/usb/redirect.c @@ -1354,7 +1354,7 @@ static void usbredir_chardev_read(void *opaque, const= uint8_t *buf, int size) usbredirparser_do_write(dev->parser); } =20 -static void usbredir_chardev_event(void *opaque, int event) +static void usbredir_chardev_event(void *opaque, QEMUChrEvent event) { USBRedirDevice *dev =3D opaque; =20 diff --git a/monitor/hmp.c b/monitor/hmp.c index 706ebe7074..944fa9651e 100644 --- a/monitor/hmp.c +++ b/monitor/hmp.c @@ -1322,7 +1322,7 @@ static void monitor_read(void *opaque, const uint8_t = *buf, int size) cur_mon =3D old_mon; } =20 -static void monitor_event(void *opaque, int event) +static void monitor_event(void *opaque, QEMUChrEvent event) { Monitor *mon =3D opaque; MonitorHMP *hmp_mon =3D container_of(mon, MonitorHMP, common); diff --git a/monitor/qmp.c b/monitor/qmp.c index 6c46be40f8..54c06ba824 100644 --- a/monitor/qmp.c +++ b/monitor/qmp.c @@ -337,7 +337,7 @@ static QDict *qmp_greeting(MonitorQMP *mon) ver, cap_list); } =20 -static void monitor_qmp_event(void *opaque, int event) +static void monitor_qmp_event(void *opaque, QEMUChrEvent event) { QDict *data; MonitorQMP *mon =3D opaque; diff --git a/net/filter-mirror.c b/net/filter-mirror.c index 8d36009c53..d83e815545 100644 --- a/net/filter-mirror.c +++ b/net/filter-mirror.c @@ -132,7 +132,7 @@ static void redirector_chr_read(void *opaque, const uin= t8_t *buf, int size) } } =20 -static void redirector_chr_event(void *opaque, int event) +static void redirector_chr_event(void *opaque, QEMUChrEvent event) { NetFilterState *nf =3D opaque; MirrorState *s =3D FILTER_REDIRECTOR(nf); diff --git a/net/vhost-user.c b/net/vhost-user.c index c54c9c7d4c..17532daaf3 100644 --- a/net/vhost-user.c +++ b/net/vhost-user.c @@ -218,7 +218,7 @@ static gboolean net_vhost_user_watch(GIOChannel *chan, = GIOCondition cond, return TRUE; } =20 -static void net_vhost_user_event(void *opaque, int event); +static void net_vhost_user_event(void *opaque, QEMUChrEvent event); =20 static void chr_closed_bh(void *opaque) { @@ -249,7 +249,7 @@ static void chr_closed_bh(void *opaque) } } =20 -static void net_vhost_user_event(void *opaque, int event) +static void net_vhost_user_event(void *opaque, QEMUChrEvent event) { const char *name =3D opaque; NetClientState *ncs[MAX_QUEUE_NUM]; diff --git a/qtest.c b/qtest.c index 8b50e2783e..12432f99cf 100644 --- a/qtest.c +++ b/qtest.c @@ -722,7 +722,7 @@ static int qtest_can_read(void *opaque) return 1024; } =20 -static void qtest_event(void *opaque, int event) +static void qtest_event(void *opaque, QEMUChrEvent event) { int i; =20 diff --git a/tests/test-char.c b/tests/test-char.c index 45e42af290..3afc9b1b8d 100644 --- a/tests/test-char.c +++ b/tests/test-char.c @@ -54,7 +54,7 @@ static void fe_read(void *opaque, const uint8_t *buf, int= size) quit =3D true; } =20 -static void fe_event(void *opaque, int event) +static void fe_event(void *opaque, QEMUChrEvent event) { FeHandler *h =3D opaque; bool new_open_state; @@ -633,7 +633,7 @@ typedef struct { =20 =20 static void -char_socket_event(void *opaque, int event) +char_socket_event(void *opaque, QEMUChrEvent event) { CharSocketTestData *data =3D opaque; data->event =3D event; @@ -1006,7 +1006,7 @@ static void char_socket_client_test(gconstpointer opa= que) } =20 static void -count_closed_event(void *opaque, int event) +count_closed_event(void *opaque, QEMUChrEvent event) { int *count =3D opaque; if (event =3D=3D CHR_EVENT_CLOSED) { diff --git a/tests/vhost-user-test.c b/tests/vhost-user-test.c index 91ea373ba5..2324b964ad 100644 --- a/tests/vhost-user-test.c +++ b/tests/vhost-user-test.c @@ -499,7 +499,7 @@ static TestServer *test_server_new(const gchar *name) return server; } =20 -static void chr_event(void *opaque, int event) +static void chr_event(void *opaque, QEMUChrEvent event) { TestServer *s =3D opaque; =20 --=20 2.21.0 From MAILER-DAEMON Wed Dec 18 13:00:50 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1ihdcv-0004tg-7d for mharc-qemu-arm@gnu.org; Wed, 18 Dec 2019 13:00:49 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:60027) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ihdcj-0004q2-1Z for qemu-arm@nongnu.org; Wed, 18 Dec 2019 13:00:44 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ihdcg-0002Of-Bp for qemu-arm@nongnu.org; Wed, 18 Dec 2019 13:00:36 -0500 Received: from mail-wm1-x344.google.com ([2a00:1450:4864:20::344]:50238) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ihdcg-0002Kj-1r for qemu-arm@nongnu.org; Wed, 18 Dec 2019 13:00:34 -0500 Received: by mail-wm1-x344.google.com with SMTP id a5so2800320wmb.0 for ; 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Wed, 18 Dec 2019 10:00:33 -0800 (PST) Received: from zen.linaroharston ([51.148.130.216]) by smtp.gmail.com with ESMTPSA id v83sm3304469wmg.16.2019.12.18.10.00.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 18 Dec 2019 10:00:30 -0800 (PST) Received: from zen.lan (localhost [127.0.0.1]) by zen.linaroharston (Postfix) with ESMTP id 0EEB91FF8C; Wed, 18 Dec 2019 18:00:30 +0000 (GMT) From: =?UTF-8?q?Alex=20Benn=C3=A9e?= To: qemu-devel@nongnu.org Cc: keithp@keithp.com, pbonzini@redhat.com, =?UTF-8?q?Alex=20Benn=C3=A9e?= , Peter Maydell , qemu-arm@nongnu.org (open list:ARM TCG CPUs) Subject: [PATCH v1 1/4] target/arm: remove unused EXCP_SEMIHOST leg Date: Wed, 18 Dec 2019 18:00:26 +0000 Message-Id: <20191218180029.6744-2-alex.bennee@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20191218180029.6744-1-alex.bennee@linaro.org> References: <20191218180029.6744-1-alex.bennee@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::344 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 18 Dec 2019 18:00:44 -0000 All semihosting exceptions are dealt with earlier in the common code so we should never get here. Signed-off-by: Alex Bennée --- target/arm/helper.c | 6 ------ 1 file changed, 6 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 5074b5f69ca..b4dc2274c8b 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -8554,12 +8554,6 @@ static void arm_cpu_do_interrupt_aarch64(CPUState *cs) case EXCP_VFIQ: addr += 0x100; break; - case EXCP_SEMIHOST: - qemu_log_mask(CPU_LOG_INT, - "...handling as semihosting call 0x%" PRIx64 "\n", - env->xregs[0]); - env->xregs[0] = do_arm_semihosting(env); - return; default: cpu_abort(cs, "Unhandled exception 0x%x\n", cs->exception_index); } -- 2.20.1 From MAILER-DAEMON Wed Dec 18 13:00:56 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1ihdd2-0004wr-QG for mharc-qemu-arm@gnu.org; Wed, 18 Dec 2019 13:00:56 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:60269) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ihdcs-0004st-Ag for qemu-arm@nongnu.org; Wed, 18 Dec 2019 13:00:55 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ihdck-0002XC-QG for qemu-arm@nongnu.org; Wed, 18 Dec 2019 13:00:44 -0500 Received: from mail-wm1-x342.google.com ([2a00:1450:4864:20::342]:51641) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ihdcj-0002Qc-02 for qemu-arm@nongnu.org; Wed, 18 Dec 2019 13:00:38 -0500 Received: by mail-wm1-x342.google.com with SMTP id d73so2799610wmd.1 for ; Wed, 18 Dec 2019 10:00:35 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=OJ0FWXyVgln1qSkZCWjjhNl0S2nBbp6lHjR8Gp2aWVw=; b=DmtBHwawVEeNJgubLkaQbh2rFgv8NVyg+uGpxb5hWGcn4HIEMSMhwwbJN/BACYx6ny 9iXAnybbzx1em2J/g9jp9OGiDz7VG9FeQMiZn9EgGKRvV055JZwrgqfd6NLWhCNwLn+s iKTSLq6W5iKjsfy4IYGcfk/nVvlBe1+uPCKAvAJ6SJkT3CxFE1WAI5buLgRxMMn6woQs FyLGjcTugTK6XJvmH/D1nELbCPCDEQuJF2eaLPB7/yS6e/nlVYMHCzkVz8meAYY6Z1VT X98ZIJ3Yprn6xRF8Hz9RJLwR9b1CT3KAJGRwyI47lbyOlDk+0bUbxp9ZljdUfUYDin7e 7ozA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=OJ0FWXyVgln1qSkZCWjjhNl0S2nBbp6lHjR8Gp2aWVw=; b=Wu/lh1jRVUQcj+deZ0i77ClCb/vJM1TmxZpTGQ3ecdTXFqzyO5onF5vxO+garljF6I RKLDwy8maIgdRPLioEhcnmgXjl3U+gdeKHZJ+SGmI0WLvN+2UjsRqVsWQoxCU9eoFbFk EZ3Kleyi6JZNnaM1gq/6I4pIkD3ymXc4NcNGaO0Fi/4YBbSaRbEAY4jD22TSKb3vhKCY eOU+az4CSyx2/vtSbjuvyvBpXrqR4IZZxWCf6Q2E+Bxy2EkQCFFygFa4eTa01uAbCz79 YZwcTgqHrFLA9Q+GT4tZG5xNMCmsRjK5Pm8FCvaBagTgMLnjgdpFzxcvBCzSVtwmxLbz OU+Q== X-Gm-Message-State: APjAAAXcup9hUkEQS80dfsoZEyGt9nf0cWx1KrJHW55n/CVTDy4AhApG b15sDOE2N9v1G9EIKXH8X49JRQ== X-Google-Smtp-Source: APXvYqwAaJtrW7vvxjim3Mq/1fo3QKUsJw6jhZFf6oMrKmgGnX0gPEm2KsPPG7FpmnkQTQ+ij1pGJg== X-Received: by 2002:a1c:4008:: with SMTP id n8mr4441035wma.121.1576692034227; Wed, 18 Dec 2019 10:00:34 -0800 (PST) Received: from zen.linaroharston ([51.148.130.216]) by smtp.gmail.com with ESMTPSA id k13sm3391284wrx.59.2019.12.18.10.00.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 18 Dec 2019 10:00:33 -0800 (PST) Received: from zen.lan (localhost [127.0.0.1]) by zen.linaroharston (Postfix) with ESMTP id 4D33E1FF8F; Wed, 18 Dec 2019 18:00:30 +0000 (GMT) From: =?UTF-8?q?Alex=20Benn=C3=A9e?= To: qemu-devel@nongnu.org Cc: keithp@keithp.com, pbonzini@redhat.com, =?UTF-8?q?Alex=20Benn=C3=A9e?= , Riku Voipio , Laurent Vivier , Peter Maydell , qemu-arm@nongnu.org (open list:ARM TCG CPUs) Subject: [PATCH v1 2/4] target/arm: only update pc after semihosting completes Date: Wed, 18 Dec 2019 18:00:27 +0000 Message-Id: <20191218180029.6744-3-alex.bennee@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20191218180029.6744-1-alex.bennee@linaro.org> References: <20191218180029.6744-1-alex.bennee@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::342 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 18 Dec 2019 18:00:55 -0000 Before we introduce blocking semihosting calls we need to ensure we can restart the system on semi hosting exception. To be able to do this the EXCP_SEMIHOST operation should be idempotent until it finally completes. Practically this means ensureing we only update the pc after the semihosting call has completed. Signed-off-by: Alex Bennée --- linux-user/aarch64/cpu_loop.c | 1 + linux-user/arm/cpu_loop.c | 1 + target/arm/helper.c | 2 ++ target/arm/m_helper.c | 1 + target/arm/translate-a64.c | 2 +- target/arm/translate.c | 6 +++--- 6 files changed, 9 insertions(+), 4 deletions(-) diff --git a/linux-user/aarch64/cpu_loop.c b/linux-user/aarch64/cpu_loop.c index 31c845a70d4..bbe9fefca81 100644 --- a/linux-user/aarch64/cpu_loop.c +++ b/linux-user/aarch64/cpu_loop.c @@ -130,6 +130,7 @@ void cpu_loop(CPUARMState *env) break; case EXCP_SEMIHOST: env->xregs[0] = do_arm_semihosting(env); + env->pc += 4; break; case EXCP_YIELD: /* nothing to do here for user-mode, just resume guest code */ diff --git a/linux-user/arm/cpu_loop.c b/linux-user/arm/cpu_loop.c index 7be40717518..1fae90c6dfc 100644 --- a/linux-user/arm/cpu_loop.c +++ b/linux-user/arm/cpu_loop.c @@ -377,6 +377,7 @@ void cpu_loop(CPUARMState *env) break; case EXCP_SEMIHOST: env->regs[0] = do_arm_semihosting(env); + env->regs[15] += env->thumb ? 2 : 4; break; case EXCP_INTERRUPT: /* just indicate that signals should be handled asap */ diff --git a/target/arm/helper.c b/target/arm/helper.c index b4dc2274c8b..088e2693df8 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -8602,11 +8602,13 @@ static void handle_semihosting(CPUState *cs) "...handling as semihosting call 0x%" PRIx64 "\n", env->xregs[0]); env->xregs[0] = do_arm_semihosting(env); + env->pc += 4; } else { qemu_log_mask(CPU_LOG_INT, "...handling as semihosting call 0x%x\n", env->regs[0]); env->regs[0] = do_arm_semihosting(env); + env->regs[15] += env->thumb ? 2 : 4; } } #endif diff --git a/target/arm/m_helper.c b/target/arm/m_helper.c index 76de317e6af..33d414a684b 100644 --- a/target/arm/m_helper.c +++ b/target/arm/m_helper.c @@ -2185,6 +2185,7 @@ void arm_v7m_cpu_do_interrupt(CPUState *cs) "...handling as semihosting call 0x%x\n", env->regs[0]); env->regs[0] = do_arm_semihosting(env); + env->regs[15] += env->thumb ? 2 : 4; return; case EXCP_BKPT: armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_DEBUG, false); diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index d4bebbe6295..972c28c3c95 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -1937,7 +1937,7 @@ static void disas_exc(DisasContext *s, uint32_t insn) break; } #endif - gen_exception_internal_insn(s, s->base.pc_next, EXCP_SEMIHOST); + gen_exception_internal_insn(s, s->pc_curr, EXCP_SEMIHOST); } else { unsupported_encoding(s, insn); } diff --git a/target/arm/translate.c b/target/arm/translate.c index 2b6c1f91bf9..5185e08641b 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -1124,7 +1124,7 @@ static inline void gen_hlt(DisasContext *s, int imm) s->current_el != 0 && #endif (imm == (s->thumb ? 0x3c : 0xf000))) { - gen_exception_internal_insn(s, s->base.pc_next, EXCP_SEMIHOST); + gen_exception_internal_insn(s, s->pc_curr, EXCP_SEMIHOST); return; } @@ -8457,7 +8457,7 @@ static bool trans_BKPT(DisasContext *s, arg_BKPT *a) !IS_USER(s) && #endif (a->imm == 0xab)) { - gen_exception_internal_insn(s, s->base.pc_next, EXCP_SEMIHOST); + gen_exception_internal_insn(s, s->pc_curr, EXCP_SEMIHOST); } else { gen_exception_bkpt_insn(s, syn_aa32_bkpt(a->imm, false)); } @@ -10266,7 +10266,7 @@ static bool trans_SVC(DisasContext *s, arg_SVC *a) !IS_USER(s) && #endif (a->imm == semihost_imm)) { - gen_exception_internal_insn(s, s->base.pc_next, EXCP_SEMIHOST); + gen_exception_internal_insn(s, s->pc_curr, EXCP_SEMIHOST); } else { gen_set_pc_im(s, s->base.pc_next); s->svc_imm = a->imm; -- 2.20.1 From MAILER-DAEMON Wed Dec 18 13:00:57 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1ihdd3-0004xF-1E for mharc-qemu-arm@gnu.org; Wed, 18 Dec 2019 13:00:57 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:60465) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ihdcv-0004tl-GC for qemu-arm@nongnu.org; Wed, 18 Dec 2019 13:00:51 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ihdcs-0002eQ-HP for qemu-arm@nongnu.org; Wed, 18 Dec 2019 13:00:47 -0500 Received: from mail-wr1-x444.google.com ([2a00:1450:4864:20::444]:43872) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ihdck-0002V4-U3 for qemu-arm@nongnu.org; Wed, 18 Dec 2019 13:00:44 -0500 Received: by mail-wr1-x444.google.com with SMTP id d16so3265316wre.10 for ; Wed, 18 Dec 2019 10:00:37 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=/fziV75QNz3yxBKb+2AS+Ep/ueUtdymBYxSkJU+JtSY=; b=t1/rW/JEf3QKkVLVHg/gMsC+Ct+fbSOVTMHB6e3lPTf8+mVzhJNsJicHkXGdsSuXGm v2HjumhoPfj+8dgr3Jn5ygkIPsvtEj/VtgMSQ2rMdVXJXF51FwDRkkxJOiDmmuzk/toR cwDd33Si5xtF5J1Ss8konCvEY/g6yNuWxOZBHwIB36G3pd242Gis0QblrX4ZIjlyoZPF 5MNkwic/du7t/sp7sRWnRrIKmkpJ7e+AB4UxPtJkUzorX8/0mWfWSJmiqo/wXDP8VrF4 q9q3yuWWd+87zXz1GhkNFJoIh2q2RWu6bbWyyWjJr9qcTDS+5VjuC3OeuimccTHKibAl Bk6Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=/fziV75QNz3yxBKb+2AS+Ep/ueUtdymBYxSkJU+JtSY=; b=A5jJRCwKIfp+/3bXA9MKFi0sKgjdDlui2aXcoCtyJAATsqFM2ZY8HQnC7fgaawL1rR 8ywn9MgOjbWEqHCFbGD41WF2pcm+NfpXiluro1mmSkUlKGPmxJGxNeBABz4CBOTlyw5s 64hqfOMyGQbCBbsefvakl85hTFRkcwWsOw2CHMkSmlay4mgD4yaxB+MIuODMRtWHSYKC Lg3X7aMniib18RqrVg6hvhRCV2UKjosmDgwsi4TD2jMA1MQwRSUTJy3V+VTXur5ucwt/ xqd2BZPzI/iyid/8REU+Tq0NEgOwhR4HDbLz3qWfMZt1W94ywYp4qjsAqexiT0JxrtM+ cu7A== X-Gm-Message-State: APjAAAVrY1Gxw9B7+BqgYqaPFdvP6gXf8dR5Z7pCXQ3rKgVDxkFRDVuw RCS8yI1hFr54w1gB25CnckwR1A== X-Google-Smtp-Source: APXvYqxORnpNvCZ1TWKw5pjTA2FxMC7ZCXLs9w3zhiQZoxiNteuM6bF9kbEMVWkL/M3E8N9Y7wF8ag== X-Received: by 2002:adf:e812:: with SMTP id o18mr4105823wrm.127.1576692036528; Wed, 18 Dec 2019 10:00:36 -0800 (PST) Received: from zen.linaroharston ([51.148.130.216]) by smtp.gmail.com with ESMTPSA id q19sm3164111wmc.12.2019.12.18.10.00.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 18 Dec 2019 10:00:33 -0800 (PST) Received: from zen.lan (localhost [127.0.0.1]) by zen.linaroharston (Postfix) with ESMTP id CB2F41FF91; Wed, 18 Dec 2019 18:00:30 +0000 (GMT) From: =?UTF-8?q?Alex=20Benn=C3=A9e?= To: qemu-devel@nongnu.org Cc: keithp@keithp.com, pbonzini@redhat.com, =?UTF-8?q?Alex=20Benn=C3=A9e?= , Peter Maydell , qemu-arm@nongnu.org (open list:ARM TCG CPUs) Subject: [PATCH v1 4/4] tests/tcg: add a dumb-as-bricks semihosting console test Date: Wed, 18 Dec 2019 18:00:29 +0000 Message-Id: <20191218180029.6744-5-alex.bennee@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20191218180029.6744-1-alex.bennee@linaro.org> References: <20191218180029.6744-1-alex.bennee@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::444 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 18 Dec 2019 18:00:55 -0000 We don't run this during check-tcg as we would need to check stuff is echoed back. However we can still build the binary so people can test it manually. Signed-off-by: Alex Bennée --- tests/tcg/aarch64/system/semiconsole.c | 36 +++++++++++++++++++++++ tests/tcg/aarch64/Makefile.softmmu-target | 9 +++++- 2 files changed, 44 insertions(+), 1 deletion(-) create mode 100644 tests/tcg/aarch64/system/semiconsole.c diff --git a/tests/tcg/aarch64/system/semiconsole.c b/tests/tcg/aarch64/system/semiconsole.c new file mode 100644 index 00000000000..636537fbe4b --- /dev/null +++ b/tests/tcg/aarch64/system/semiconsole.c @@ -0,0 +1,36 @@ +/* + * Semihosting Console Test + * + * Copyright (c) 2019 Linaro Ltd + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include +#include + +#define SYS_READC 0x7 + +uintptr_t __semi_call(uintptr_t type, uintptr_t arg0) +{ + register uintptr_t t asm("x0") = type; + register uintptr_t a0 asm("x1") = arg0; + asm("hlt 0xf000" + : "=r" (t) + : "r" (t), "r" (a0)); +} + +int main(void) +{ + char c; + + ml_printf("Semihosting Console Test\n"); + ml_printf("hit X to exit:"); + + do { + c = __semi_call(SYS_READC, 0); + __sys_outc(c); + } while (c != 'X'); + + return 0; +} diff --git a/tests/tcg/aarch64/Makefile.softmmu-target b/tests/tcg/aarch64/Makefile.softmmu-target index 950dbb4bac2..9bdcfd9e7e4 100644 --- a/tests/tcg/aarch64/Makefile.softmmu-target +++ b/tests/tcg/aarch64/Makefile.softmmu-target @@ -31,7 +31,14 @@ LDFLAGS+=-static -nostdlib $(CRT_OBJS) $(MINILIB_OBJS) -lgcc memory: CFLAGS+=-DCHECK_UNALIGNED=1 # Running -QEMU_OPTS+=-M virt -cpu max -display none -semihosting-config enable=on,target=native,chardev=output -kernel +QEMU_BASE_MACHINE=-M virt -cpu max -display none +QEMU_OPTS+=$(QEMU_BASE_MACHINE) -semihosting-config enable=on,target=native,chardev=output -kernel + +# console test is manual only +QEMU_SEMIHOST=-chardev stdio,mux=on,id=stdio0 -semihosting-config enable=on,chardev=stdio0 -mon chardev=stdio0,mode=readline +run-semiconsole: QEMU_OPTS=$(QEMU_BASE_MACHINE) $(QEMU_SEMIHOST) -kernel +run-semiconsole: semiconsole + $(call skip-test, $<, "MANUAL ONLY") # Simple Record/Replay Test .PHONY: memory-record -- 2.20.1 From MAILER-DAEMON Wed Dec 18 13:00:58 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1ihdd4-0004zJ-FK for mharc-qemu-arm@gnu.org; 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Wed, 18 Dec 2019 10:00:33 -0800 (PST) Received: from zen.lan (localhost [127.0.0.1]) by zen.linaroharston (Postfix) with ESMTP id 9B1EE1FF90; Wed, 18 Dec 2019 18:00:30 +0000 (GMT) From: =?UTF-8?q?Alex=20Benn=C3=A9e?= To: qemu-devel@nongnu.org Cc: keithp@keithp.com, pbonzini@redhat.com, =?UTF-8?q?Alex=20Benn=C3=A9e?= , Riku Voipio , Laurent Vivier , Peter Maydell , qemu-arm@nongnu.org (open list:ARM TCG CPUs) Subject: [PATCH v1 3/4] semihosting: add qemu_semihosting_console_inc for SYS_READC Date: Wed, 18 Dec 2019 18:00:28 +0000 Message-Id: <20191218180029.6744-4-alex.bennee@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20191218180029.6744-1-alex.bennee@linaro.org> References: <20191218180029.6744-1-alex.bennee@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::443 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 18 Dec 2019 18:00:50 -0000 From: Keith Packard Provides a blocking call to read a character from the console using semihosting.chardev, if specified. This takes some careful command line options to use stdio successfully as the serial ports, monitor and semihost all want to use stdio. Here's a sample set of command line options which share stdio betwen semihost, monitor and serial ports: qemu \ -chardev stdio,mux=on,id=stdio0 \ -serial chardev:stdio0 \ -semihosting-config enable=on,chardev=stdio0 \ -mon chardev=stdio0,mode=readline This creates a chardev hooked to stdio and then connects all of the subsystems to it. A shorter mechanism would be good to hear about. Signed-off-by: Keith Packard Message-Id: <20191104204230.12249-1-keithp@keithp.com> [AJB: fixed up deadlock, minor commit title reword] Signed-off-by: Alex Bennée Cc: Paolo Bonzini --- v7 - reword commit title - remove mutexs, halt CPU until data available - document cpu_loop_exit behavior in function API --- include/hw/semihosting/console.h | 16 +++++++ include/hw/semihosting/semihost.h | 4 ++ hw/semihosting/console.c | 78 +++++++++++++++++++++++++++++++ linux-user/arm/semihost.c | 23 +++++++++ stubs/semihost.c | 4 ++ target/arm/arm-semi.c | 3 +- vl.c | 3 ++ 7 files changed, 129 insertions(+), 2 deletions(-) diff --git a/include/hw/semihosting/console.h b/include/hw/semihosting/console.h index 9be9754bcdf..a3bd6ca2419 100644 --- a/include/hw/semihosting/console.h +++ b/include/hw/semihosting/console.h @@ -37,6 +37,22 @@ int qemu_semihosting_console_outs(CPUArchState *env, target_ulong s); */ void qemu_semihosting_console_outc(CPUArchState *env, target_ulong c); +/** + * qemu_semihosting_console_inc: + * @env: CPUArchState + * + * Receive single character from debug console. This may be the remote + * gdb session if a softmmu guest is currently being debugged. As this + * call may block if no data is available we suspend the CPU and will + * rexecute the instruction when data is there. Therefor two + * conditions must be met: + * - CPUState is syncronised before callinging this function + * - pc is only updated once the character is succesfully returned + * + * Returns: character read OR cpu_loop_exit! + */ +target_ulong qemu_semihosting_console_inc(CPUArchState *env); + /** * qemu_semihosting_log_out: * @s: pointer to string diff --git a/include/hw/semihosting/semihost.h b/include/hw/semihosting/semihost.h index 60fc42d851e..b8ce5117ae0 100644 --- a/include/hw/semihosting/semihost.h +++ b/include/hw/semihosting/semihost.h @@ -56,6 +56,9 @@ static inline Chardev *semihosting_get_chardev(void) { return NULL; } +static inline void qemu_semihosting_console_init(void) +{ +} #else /* !CONFIG_USER_ONLY */ bool semihosting_enabled(void); SemihostingTarget semihosting_get_target(void); @@ -68,6 +71,7 @@ Chardev *semihosting_get_chardev(void); void qemu_semihosting_enable(void); int qemu_semihosting_config_options(const char *opt); void qemu_semihosting_connect_chardevs(void); +void qemu_semihosting_console_init(void); #endif /* CONFIG_USER_ONLY */ #endif /* SEMIHOST_H */ diff --git a/hw/semihosting/console.c b/hw/semihosting/console.c index b4b17c8afbc..6180f33ef21 100644 --- a/hw/semihosting/console.c +++ b/hw/semihosting/console.c @@ -20,8 +20,15 @@ #include "hw/semihosting/semihost.h" #include "hw/semihosting/console.h" #include "exec/gdbstub.h" +#include "exec/exec-all.h" #include "qemu/log.h" #include "chardev/char.h" +#include +#include "chardev/char-fe.h" +#include "sysemu/sysemu.h" +#include "qemu/main-loop.h" +#include "qapi/error.h" +#include "qemu/fifo8.h" int qemu_semihosting_log_out(const char *s, int len) { @@ -98,3 +105,74 @@ void qemu_semihosting_console_outc(CPUArchState *env, target_ulong addr) __func__, addr); } } + +#define FIFO_SIZE 1024 + +typedef struct SemihostingConsole { + CharBackend backend; + GSList *sleeping_cpus; + bool got; + Fifo8 fifo; +} SemihostingConsole; + +static SemihostingConsole console; + +static int console_can_read(void *opaque) +{ + SemihostingConsole *c = opaque; + int ret; + g_assert(qemu_mutex_iothread_locked()); + ret = (int) fifo8_num_free(&c->fifo); + return ret; +} + +static void console_wake_up(gpointer data, gpointer user_data) +{ + CPUState *cs = (CPUState *) data; + /* cpu_handle_halt won't know we have work so just unbung here */ + cs->halted = 0; + qemu_cpu_kick(cs); +} + +static void console_read(void *opaque, const uint8_t *buf, int size) +{ + SemihostingConsole *c = opaque; + g_assert(qemu_mutex_iothread_locked()); + while (size-- && !fifo8_is_full(&c->fifo)) { + fifo8_push(&c->fifo, *buf++); + } + g_slist_foreach(c->sleeping_cpus, console_wake_up, NULL); +} + +target_ulong qemu_semihosting_console_inc(CPUArchState *env) +{ + uint8_t ch; + SemihostingConsole *c = &console; + g_assert(qemu_mutex_iothread_locked()); + g_assert(current_cpu); + if (fifo8_is_empty(&c->fifo)) { + c->sleeping_cpus = g_slist_prepend(c->sleeping_cpus, current_cpu); + current_cpu->halted = 1; + current_cpu->exception_index = EXCP_HALTED; + cpu_loop_exit(current_cpu); + /* never returns */ + } + c->sleeping_cpus = g_slist_remove_all(c->sleeping_cpus, current_cpu); + ch = fifo8_pop(&c->fifo); + return (target_ulong) ch; +} + +void qemu_semihosting_console_init(void) +{ + Chardev *chr = semihosting_get_chardev(); + + if (chr) { + fifo8_create(&console.fifo, FIFO_SIZE); + qemu_chr_fe_init(&console.backend, chr, &error_abort); + qemu_chr_fe_set_handlers(&console.backend, + console_can_read, + console_read, + NULL, NULL, &console, + NULL, true); + } +} diff --git a/linux-user/arm/semihost.c b/linux-user/arm/semihost.c index a16b525eec0..4f998d62201 100644 --- a/linux-user/arm/semihost.c +++ b/linux-user/arm/semihost.c @@ -14,6 +14,7 @@ #include "cpu.h" #include "hw/semihosting/console.h" #include "qemu.h" +#include int qemu_semihosting_console_outs(CPUArchState *env, target_ulong addr) { @@ -47,3 +48,25 @@ void qemu_semihosting_console_outc(CPUArchState *env, target_ulong addr) } } } + +target_ulong qemu_semihosting_console_inc(CPUArchState *env) +{ + uint8_t c; + struct pollfd pollfd = { + .fd = STDIN_FILENO, + .events = POLLIN + }; + + if (poll(&pollfd, 1, -1) != 1) { + qemu_log_mask(LOG_UNIMP, "%s: unexpected read from stdin failure", + __func__); + return (target_ulong) -1; + } + + if (read(STDIN_FILENO, &c, 1) != 1) { + qemu_log_mask(LOG_UNIMP, "%s: unexpected read from stdin failure", + __func__); + return (target_ulong) -1; + } + return (target_ulong) c; +} diff --git a/stubs/semihost.c b/stubs/semihost.c index f90589259c0..1d8b37f7b2f 100644 --- a/stubs/semihost.c +++ b/stubs/semihost.c @@ -69,3 +69,7 @@ void semihosting_arg_fallback(const char *file, const char *cmd) void qemu_semihosting_connect_chardevs(void) { } + +void qemu_semihosting_console_init(void) +{ +} diff --git a/target/arm/arm-semi.c b/target/arm/arm-semi.c index 6f7b6d801bf..47d61f6fe1f 100644 --- a/target/arm/arm-semi.c +++ b/target/arm/arm-semi.c @@ -802,8 +802,7 @@ target_ulong do_arm_semihosting(CPUARMState *env) return guestfd_fns[gf->type].readfn(cpu, gf, arg1, len); case TARGET_SYS_READC: - qemu_log_mask(LOG_UNIMP, "%s: SYS_READC not implemented", __func__); - return 0; + return qemu_semihosting_console_inc(env); case TARGET_SYS_ISTTY: GET_ARG(0); diff --git a/vl.c b/vl.c index 94508300c3c..1912f87822b 100644 --- a/vl.c +++ b/vl.c @@ -4142,6 +4142,9 @@ int main(int argc, char **argv, char **envp) qemu_opts_foreach(qemu_find_opts("mon"), mon_init_func, NULL, &error_fatal); + /* connect semihosting console input if requested */ + qemu_semihosting_console_init(); + if (foreach_device_config(DEV_SERIAL, serial_parse) < 0) exit(1); if (foreach_device_config(DEV_PARALLEL, parallel_parse) < 0) -- 2.20.1 From MAILER-DAEMON Wed Dec 18 13:43:02 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1iheHm-0007bc-S0 for mharc-qemu-arm@gnu.org; Wed, 18 Dec 2019 13:43:02 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:59597) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iheHi-0007aG-12 for qemu-arm@nongnu.org; Wed, 18 Dec 2019 13:43:01 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1iheHd-0004ld-Mb for qemu-arm@nongnu.org; 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[2001:470:b8f6:1b::1]) by smtp.gmail.com with ESMTPSA id f3sm1060407oto.57.2019.12.18.10.42.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 18 Dec 2019 10:42:51 -0800 (PST) Sender: Corey Minyard Received: from minyard.net (unknown [IPv6:2001:470:b8f6:1b:69de:55d9:4498:6ca0]) by serve.minyard.net (Postfix) with ESMTPSA id 816DB180058; Wed, 18 Dec 2019 18:42:50 +0000 (UTC) Date: Wed, 18 Dec 2019 12:42:49 -0600 From: Corey Minyard To: Philippe =?utf-8?Q?Mathieu-Daud=C3=A9?= Cc: qemu-devel@nongnu.org, "Gonglei (Arei)" , =?utf-8?Q?Marc-Andr=C3=A9?= Lureau , Paolo Bonzini , Alex =?utf-8?Q?Benn=C3=A9e?= , Andrzej Zaborowski , Peter Maydell , "Michael S. Tsirkin" , Kevin Wolf , Max Reitz , "Edgar E. Iglesias" , Alistair Francis , Antony Pavlov , Igor Mitsyanko , Fabien Chouteau , KONRAD Frederic , Peter Chubb , Alberto Garcia , Michael Walle , Thomas Huth , Joel Stanley , Cornelia Huck , Halil Pasic , Christian Borntraeger , Laurent Vivier , Amit Shah , Paul Burton , Aleksandar Rikalo , Aurelien Jarno , Aleksandar Markovic , Palmer Dabbelt , Sagar Karandikar , Bastian Koppelmann , Gerd Hoffmann , Samuel Thibault , "Dr. David Alan Gilbert" , Markus Armbruster , Zhang Chen , Li Zhijian , Jason Wang , qemu-arm@nongnu.org, qemu-block@nongnu.org, qemu-s390x@nongnu.org, qemu-riscv@nongnu.org Subject: Re: [RFC PATCH v2 14/14] chardev: Use QEMUChrEvent enum in IOEventHandler typedef Message-ID: <20191218184249.GF7025@minyard.net> Reply-To: minyard@acm.org References: <20191218172009.8868-1-philmd@redhat.com> <20191218172009.8868-15-philmd@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <20191218172009.8868-15-philmd@redhat.com> User-Agent: Mutt/1.9.4 (2018-02-28) X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::344 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 18 Dec 2019 18:43:02 -0000 On Wed, Dec 18, 2019 at 06:20:09PM +0100, Philippe Mathieu-Daudé wrote: > The Chardev events are listed in the QEMUChrEvent enum. > > By using the enum in the IOEventHandler typedef we: > > - make the IOEventHandler type more explicit (this handler > process out-of-band information, while the IOReadHandler > is in-band), > - help static code analyzers. For the IPMI part: Acked-by: Corey Minyard > > This patch was produced with the following spatch script: > > @match@ > expression backend, opaque, context, set_open; > identifier fd_can_read, fd_read, fd_event, be_change; > @@ > qemu_chr_fe_set_handlers(backend, fd_can_read, fd_read, fd_event, > be_change, opaque, context, set_open); > > @depends on match@ > identifier opaque, event; > identifier match.fd_event; > @@ > static > -void fd_event(void *opaque, int event) > +void fd_event(void *opaque, QEMUChrEvent event) > { > ... > } > > Then the following files were manually modified: > > - include/chardev/char-fe.h > - include/chardev/char.h > - include/chardev/char-mux.h > - chardev/char.c > - chardev/char-mux.c > > Signed-off-by: Philippe Mathieu-Daudé > --- > Cc: "Gonglei (Arei)" > Cc: "Marc-André Lureau" > Cc: Paolo Bonzini > Cc: "Alex Bennée" > Cc: "Philippe Mathieu-Daudé" > Cc: Andrzej Zaborowski > Cc: Peter Maydell > Cc: "Michael S. Tsirkin" > Cc: Kevin Wolf > Cc: Max Reitz > Cc: "Edgar E. Iglesias" > Cc: Alistair Francis > Cc: Antony Pavlov > Cc: Igor Mitsyanko > Cc: Fabien Chouteau > Cc: KONRAD Frederic > Cc: Peter Chubb > Cc: Alberto Garcia > Cc: Michael Walle > Cc: Thomas Huth > Cc: Joel Stanley > Cc: Cornelia Huck > Cc: Halil Pasic > Cc: Christian Borntraeger > Cc: Laurent Vivier > Cc: Amit Shah > Cc: Corey Minyard > Cc: Paul Burton > Cc: Aleksandar Rikalo > Cc: Aurelien Jarno > Cc: Aleksandar Markovic > Cc: Palmer Dabbelt > Cc: Sagar Karandikar > Cc: Bastian Koppelmann > Cc: Gerd Hoffmann > Cc: Samuel Thibault > Cc: "Dr. David Alan Gilbert" > Cc: Markus Armbruster > Cc: Zhang Chen > Cc: Li Zhijian > Cc: Jason Wang > Cc: qemu-arm@nongnu.org > Cc: qemu-block@nongnu.org > Cc: qemu-s390x@nongnu.org > Cc: qemu-riscv@nongnu.org > --- > include/chardev/char-fe.h | 2 +- > include/chardev/char-mux.h | 2 +- > include/chardev/char.h | 4 ++-- > backends/cryptodev-vhost-user.c | 2 +- > chardev/char-mux.c | 8 ++++---- > chardev/char.c | 4 ++-- > gdbstub.c | 2 +- > hw/arm/pxa2xx.c | 2 +- > hw/arm/strongarm.c | 2 +- > hw/block/vhost-user-blk.c | 2 +- > hw/char/cadence_uart.c | 2 +- > hw/char/digic-uart.c | 2 +- > hw/char/escc.c | 2 +- > hw/char/etraxfs_ser.c | 2 +- > hw/char/exynos4210_uart.c | 2 +- > hw/char/grlib_apbuart.c | 2 +- > hw/char/imx_serial.c | 2 +- > hw/char/ipoctal232.c | 2 +- > hw/char/lm32_juart.c | 2 +- > hw/char/lm32_uart.c | 2 +- > hw/char/mcf_uart.c | 2 +- > hw/char/milkymist-uart.c | 2 +- > hw/char/nrf51_uart.c | 2 +- > hw/char/pl011.c | 2 +- > hw/char/serial.c | 2 +- > hw/char/sh_serial.c | 2 +- > hw/char/terminal3270.c | 2 +- > hw/char/virtio-console.c | 2 +- > hw/char/xilinx_uartlite.c | 2 +- > hw/ipmi/ipmi_bmc_extern.c | 2 +- > hw/mips/boston.c | 2 +- > hw/mips/mips_malta.c | 2 +- > hw/riscv/riscv_htif.c | 2 +- > hw/riscv/sifive_uart.c | 2 +- > hw/usb/ccid-card-passthru.c | 2 +- > hw/usb/dev-serial.c | 2 +- > hw/usb/redirect.c | 2 +- > monitor/hmp.c | 2 +- > monitor/qmp.c | 2 +- > net/filter-mirror.c | 2 +- > net/vhost-user.c | 4 ++-- > qtest.c | 2 +- > tests/test-char.c | 6 +++--- > tests/vhost-user-test.c | 2 +- > 44 files changed, 52 insertions(+), 52 deletions(-) > > diff --git a/include/chardev/char-fe.h b/include/chardev/char-fe.h > index 67601dc9a4..a553843364 100644 > --- a/include/chardev/char-fe.h > +++ b/include/chardev/char-fe.h > @@ -4,7 +4,7 @@ > #include "chardev/char.h" > #include "qemu/main-loop.h" > > -typedef void IOEventHandler(void *opaque, int event); > +typedef void IOEventHandler(void *opaque, QEMUChrEvent event); > typedef int BackendChangeHandler(void *opaque); > > /* This is the backend as seen by frontend, the actual backend is > diff --git a/include/chardev/char-mux.h b/include/chardev/char-mux.h > index 572cefd517..417fe32eed 100644 > --- a/include/chardev/char-mux.h > +++ b/include/chardev/char-mux.h > @@ -56,6 +56,6 @@ typedef struct MuxChardev { > object_dynamic_cast(OBJECT(chr), TYPE_CHARDEV_MUX) > > void mux_set_focus(Chardev *chr, int focus); > -void mux_chr_send_all_event(Chardev *chr, int event); > +void mux_chr_send_all_event(Chardev *chr, QEMUChrEvent event); > > #endif /* CHAR_MUX_H */ > diff --git a/include/chardev/char.h b/include/chardev/char.h > index 087b202b62..00589a6025 100644 > --- a/include/chardev/char.h > +++ b/include/chardev/char.h > @@ -210,7 +210,7 @@ void qemu_chr_be_update_read_handlers(Chardev *s, > * > * Send an event from the back end to the front end. > */ > -void qemu_chr_be_event(Chardev *s, int event); > +void qemu_chr_be_event(Chardev *s, QEMUChrEvent event); > > int qemu_chr_add_client(Chardev *s, int fd); > Chardev *qemu_chr_find(const char *name); > @@ -273,7 +273,7 @@ typedef struct ChardevClass { > void (*chr_accept_input)(Chardev *chr); > void (*chr_set_echo)(Chardev *chr, bool echo); > void (*chr_set_fe_open)(Chardev *chr, int fe_open); > - void (*chr_be_event)(Chardev *s, int event); > + void (*chr_be_event)(Chardev *s, QEMUChrEvent event); > /* Return 0 if succeeded, 1 if failed */ > int (*chr_machine_done)(Chardev *chr); > } ChardevClass; > diff --git a/backends/cryptodev-vhost-user.c b/backends/cryptodev-vhost-user.c > index f1b407955f..6edada8e9e 100644 > --- a/backends/cryptodev-vhost-user.c > +++ b/backends/cryptodev-vhost-user.c > @@ -152,7 +152,7 @@ cryptodev_vhost_claim_chardev(CryptoDevBackendVhostUser *s, > return chr; > } > > -static void cryptodev_vhost_user_event(void *opaque, int event) > +static void cryptodev_vhost_user_event(void *opaque, QEMUChrEvent event) > { > CryptoDevBackendVhostUser *s = opaque; > CryptoDevBackend *b = CRYPTODEV_BACKEND(s); > diff --git a/chardev/char-mux.c b/chardev/char-mux.c > index 200c62a0d0..46c44af67c 100644 > --- a/chardev/char-mux.c > +++ b/chardev/char-mux.c > @@ -117,7 +117,7 @@ static void mux_print_help(Chardev *chr) > } > } > > -static void mux_chr_send_event(MuxChardev *d, int mux_nr, int event) > +static void mux_chr_send_event(MuxChardev *d, int mux_nr, QEMUChrEvent event) > { > CharBackend *be = d->backends[mux_nr]; > > @@ -126,7 +126,7 @@ static void mux_chr_send_event(MuxChardev *d, int mux_nr, int event) > } > } > > -static void mux_chr_be_event(Chardev *chr, int event) > +static void mux_chr_be_event(Chardev *chr, QEMUChrEvent event) > { > MuxChardev *d = MUX_CHARDEV(chr); > > @@ -232,7 +232,7 @@ static void mux_chr_read(void *opaque, const uint8_t *buf, int size) > } > } > > -void mux_chr_send_all_event(Chardev *chr, int event) > +void mux_chr_send_all_event(Chardev *chr, QEMUChrEvent event) > { > MuxChardev *d = MUX_CHARDEV(chr); > int i; > @@ -247,7 +247,7 @@ void mux_chr_send_all_event(Chardev *chr, int event) > } > } > > -static void mux_chr_event(void *opaque, int event) > +static void mux_chr_event(void *opaque, QEMUChrEvent event) > { > mux_chr_send_all_event(CHARDEV(opaque), event); > } > diff --git a/chardev/char.c b/chardev/char.c > index 739da1155b..4f598f8175 100644 > --- a/chardev/char.c > +++ b/chardev/char.c > @@ -48,7 +48,7 @@ static Object *get_chardevs_root(void) > return container_get(object_get_root(), "/chardevs"); > } > > -static void chr_be_event(Chardev *s, int event) > +static void chr_be_event(Chardev *s, QEMUChrEvent event) > { > CharBackend *be = s->be; > > @@ -59,7 +59,7 @@ static void chr_be_event(Chardev *s, int event) > be->chr_event(be->opaque, event); > } > > -void qemu_chr_be_event(Chardev *s, int event) > +void qemu_chr_be_event(Chardev *s, QEMUChrEvent event) > { > /* Keep track if the char device is open */ > switch (event) { > diff --git a/gdbstub.c b/gdbstub.c > index 4cf8af365e..ce304ff482 100644 > --- a/gdbstub.c > +++ b/gdbstub.c > @@ -3171,7 +3171,7 @@ static void gdb_chr_receive(void *opaque, const uint8_t *buf, int size) > } > } > > -static void gdb_chr_event(void *opaque, int event) > +static void gdb_chr_event(void *opaque, QEMUChrEvent event) > { > int i; > GDBState *s = (GDBState *) opaque; > diff --git a/hw/arm/pxa2xx.c b/hw/arm/pxa2xx.c > index cdafde2f76..950ff4239a 100644 > --- a/hw/arm/pxa2xx.c > +++ b/hw/arm/pxa2xx.c > @@ -1955,7 +1955,7 @@ static void pxa2xx_fir_rx(void *opaque, const uint8_t *buf, int size) > pxa2xx_fir_update(s); > } > > -static void pxa2xx_fir_event(void *opaque, int event) > +static void pxa2xx_fir_event(void *opaque, QEMUChrEvent event) > { > } > > diff --git a/hw/arm/strongarm.c b/hw/arm/strongarm.c > index 6bee034914..c6776e8479 100644 > --- a/hw/arm/strongarm.c > +++ b/hw/arm/strongarm.c > @@ -1093,7 +1093,7 @@ static void strongarm_uart_receive(void *opaque, const uint8_t *buf, int size) > strongarm_uart_update_int_status(s); > } > > -static void strongarm_uart_event(void *opaque, int event) > +static void strongarm_uart_event(void *opaque, QEMUChrEvent event) > { > StrongARMUARTState *s = opaque; > if (event == CHR_EVENT_BREAK) { > diff --git a/hw/block/vhost-user-blk.c b/hw/block/vhost-user-blk.c > index ccaf2ad978..98b383f90e 100644 > --- a/hw/block/vhost-user-blk.c > +++ b/hw/block/vhost-user-blk.c > @@ -361,7 +361,7 @@ static gboolean vhost_user_blk_watch(GIOChannel *chan, GIOCondition cond, > return true; > } > > -static void vhost_user_blk_event(void *opaque, int event) > +static void vhost_user_blk_event(void *opaque, QEMUChrEvent event) > { > DeviceState *dev = opaque; > VirtIODevice *vdev = VIRTIO_DEVICE(dev); > diff --git a/hw/char/cadence_uart.c b/hw/char/cadence_uart.c > index 0e315b2376..51791bd217 100644 > --- a/hw/char/cadence_uart.c > +++ b/hw/char/cadence_uart.c > @@ -348,7 +348,7 @@ static void uart_receive(void *opaque, const uint8_t *buf, int size) > } > } > > -static void uart_event(void *opaque, int event) > +static void uart_event(void *opaque, QEMUChrEvent event) > { > CadenceUARTState *s = opaque; > uint8_t buf = '\0'; > diff --git a/hw/char/digic-uart.c b/hw/char/digic-uart.c > index 974a2619dd..033eba0a6a 100644 > --- a/hw/char/digic-uart.c > +++ b/hw/char/digic-uart.c > @@ -131,7 +131,7 @@ static void uart_rx(void *opaque, const uint8_t *buf, int size) > s->reg_rx = *buf; > } > > -static void uart_event(void *opaque, int event) > +static void uart_event(void *opaque, QEMUChrEvent event) > { > } > > diff --git a/hw/char/escc.c b/hw/char/escc.c > index 8f7bf322cb..c40c1d28f1 100644 > --- a/hw/char/escc.c > +++ b/hw/char/escc.c > @@ -634,7 +634,7 @@ static void serial_receive1(void *opaque, const uint8_t *buf, int size) > serial_receive_byte(s, buf[0]); > } > > -static void serial_event(void *opaque, int event) > +static void serial_event(void *opaque, QEMUChrEvent event) > { > ESCCChannelState *s = opaque; > if (event == CHR_EVENT_BREAK) > diff --git a/hw/char/etraxfs_ser.c b/hw/char/etraxfs_ser.c > index 15ac12ef22..f34f767c60 100644 > --- a/hw/char/etraxfs_ser.c > +++ b/hw/char/etraxfs_ser.c > @@ -202,7 +202,7 @@ static int serial_can_receive(void *opaque) > return sizeof(s->rx_fifo) - s->rx_fifo_len; > } > > -static void serial_event(void *opaque, int event) > +static void serial_event(void *opaque, QEMUChrEvent event) > { > > } > diff --git a/hw/char/exynos4210_uart.c b/hw/char/exynos4210_uart.c > index d6b6b62366..7e5c5ce789 100644 > --- a/hw/char/exynos4210_uart.c > +++ b/hw/char/exynos4210_uart.c > @@ -528,7 +528,7 @@ static void exynos4210_uart_receive(void *opaque, const uint8_t *buf, int size) > } > > > -static void exynos4210_uart_event(void *opaque, int event) > +static void exynos4210_uart_event(void *opaque, QEMUChrEvent event) > { > Exynos4210UartState *s = (Exynos4210UartState *)opaque; > > diff --git a/hw/char/grlib_apbuart.c b/hw/char/grlib_apbuart.c > index fe3cbf41a3..8e59c3bc6e 100644 > --- a/hw/char/grlib_apbuart.c > +++ b/hw/char/grlib_apbuart.c > @@ -155,7 +155,7 @@ static void grlib_apbuart_receive(void *opaque, const uint8_t *buf, int size) > } > } > > -static void grlib_apbuart_event(void *opaque, int event) > +static void grlib_apbuart_event(void *opaque, QEMUChrEvent event) > { > trace_grlib_apbuart_event(event); > } > diff --git a/hw/char/imx_serial.c b/hw/char/imx_serial.c > index fddde9b43d..d09c210709 100644 > --- a/hw/char/imx_serial.c > +++ b/hw/char/imx_serial.c > @@ -323,7 +323,7 @@ static void imx_receive(void *opaque, const uint8_t *buf, int size) > imx_put_data(opaque, *buf); > } > > -static void imx_event(void *opaque, int event) > +static void imx_event(void *opaque, QEMUChrEvent event) > { > if (event == CHR_EVENT_BREAK) { > imx_put_data(opaque, URXD_BRK | URXD_FRMERR | URXD_ERR); > diff --git a/hw/char/ipoctal232.c b/hw/char/ipoctal232.c > index 66c163ba26..80e9dff701 100644 > --- a/hw/char/ipoctal232.c > +++ b/hw/char/ipoctal232.c > @@ -503,7 +503,7 @@ static void hostdev_receive(void *opaque, const uint8_t *buf, int size) > } > } > > -static void hostdev_event(void *opaque, int event) > +static void hostdev_event(void *opaque, QEMUChrEvent event) > { > SCC2698Channel *ch = opaque; > switch (event) { > diff --git a/hw/char/lm32_juart.c b/hw/char/lm32_juart.c > index e0b1bd6555..da9dd5668b 100644 > --- a/hw/char/lm32_juart.c > +++ b/hw/char/lm32_juart.c > @@ -104,7 +104,7 @@ static int juart_can_rx(void *opaque) > return !(s->jrx & JRX_FULL); > } > > -static void juart_event(void *opaque, int event) > +static void juart_event(void *opaque, QEMUChrEvent event) > { > } > > diff --git a/hw/char/lm32_uart.c b/hw/char/lm32_uart.c > index 32f29c44cf..8d7a475c91 100644 > --- a/hw/char/lm32_uart.c > +++ b/hw/char/lm32_uart.c > @@ -235,7 +235,7 @@ static int uart_can_rx(void *opaque) > return !(s->regs[R_LSR] & LSR_DR); > } > > -static void uart_event(void *opaque, int event) > +static void uart_event(void *opaque, QEMUChrEvent event) > { > } > > diff --git a/hw/char/mcf_uart.c b/hw/char/mcf_uart.c > index 58323baf43..2de3680b5d 100644 > --- a/hw/char/mcf_uart.c > +++ b/hw/char/mcf_uart.c > @@ -256,7 +256,7 @@ static void mcf_uart_push_byte(mcf_uart_state *s, uint8_t data) > mcf_uart_update(s); > } > > -static void mcf_uart_event(void *opaque, int event) > +static void mcf_uart_event(void *opaque, QEMUChrEvent event) > { > mcf_uart_state *s = (mcf_uart_state *)opaque; > > diff --git a/hw/char/milkymist-uart.c b/hw/char/milkymist-uart.c > index c358ca07f3..1c7b61480e 100644 > --- a/hw/char/milkymist-uart.c > +++ b/hw/char/milkymist-uart.c > @@ -180,7 +180,7 @@ static int uart_can_rx(void *opaque) > return !(s->regs[R_STAT] & STAT_RX_EVT); > } > > -static void uart_event(void *opaque, int event) > +static void uart_event(void *opaque, QEMUChrEvent event) > { > } > > diff --git a/hw/char/nrf51_uart.c b/hw/char/nrf51_uart.c > index 2777afe366..b67fd21089 100644 > --- a/hw/char/nrf51_uart.c > +++ b/hw/char/nrf51_uart.c > @@ -245,7 +245,7 @@ static int uart_can_receive(void *opaque) > return s->rx_started ? (UART_FIFO_LENGTH - s->rx_fifo_len) : 0; > } > > -static void uart_event(void *opaque, int event) > +static void uart_event(void *opaque, QEMUChrEvent event) > { > NRF51UARTState *s = NRF51_UART(opaque); > > diff --git a/hw/char/pl011.c b/hw/char/pl011.c > index 84ad8ff9fb..23cd544cc5 100644 > --- a/hw/char/pl011.c > +++ b/hw/char/pl011.c > @@ -280,7 +280,7 @@ static void pl011_receive(void *opaque, const uint8_t *buf, int size) > pl011_put_fifo(opaque, *buf); > } > > -static void pl011_event(void *opaque, int event) > +static void pl011_event(void *opaque, QEMUChrEvent event) > { > if (event == CHR_EVENT_BREAK) > pl011_put_fifo(opaque, 0x400); > diff --git a/hw/char/serial.c b/hw/char/serial.c > index b4aa250950..992b5ee944 100644 > --- a/hw/char/serial.c > +++ b/hw/char/serial.c > @@ -634,7 +634,7 @@ static void serial_receive1(void *opaque, const uint8_t *buf, int size) > serial_update_irq(s); > } > > -static void serial_event(void *opaque, int event) > +static void serial_event(void *opaque, QEMUChrEvent event) > { > SerialState *s = opaque; > DPRINTF("event %x\n", event); > diff --git a/hw/char/sh_serial.c b/hw/char/sh_serial.c > index 07dc16be13..167f4d8cb9 100644 > --- a/hw/char/sh_serial.c > +++ b/hw/char/sh_serial.c > @@ -358,7 +358,7 @@ static void sh_serial_receive1(void *opaque, const uint8_t *buf, int size) > } > } > > -static void sh_serial_event(void *opaque, int event) > +static void sh_serial_event(void *opaque, QEMUChrEvent event) > { > sh_serial_state *s = opaque; > if (event == CHR_EVENT_BREAK) > diff --git a/hw/char/terminal3270.c b/hw/char/terminal3270.c > index 2aab04fd4b..f7aba12565 100644 > --- a/hw/char/terminal3270.c > +++ b/hw/char/terminal3270.c > @@ -142,7 +142,7 @@ static void terminal_read(void *opaque, const uint8_t *buf, int size) > } > } > > -static void chr_event(void *opaque, int event) > +static void chr_event(void *opaque, QEMUChrEvent event) > { > Terminal3270 *t = opaque; > CcwDevice *ccw_dev = CCW_DEVICE(t); > diff --git a/hw/char/virtio-console.c b/hw/char/virtio-console.c > index cbb304d270..a7d34fe0ed 100644 > --- a/hw/char/virtio-console.c > +++ b/hw/char/virtio-console.c > @@ -145,7 +145,7 @@ static void chr_read(void *opaque, const uint8_t *buf, int size) > virtio_serial_write(port, buf, size); > } > > -static void chr_event(void *opaque, int event) > +static void chr_event(void *opaque, QEMUChrEvent event) > { > VirtConsole *vcon = opaque; > VirtIOSerialPort *port = VIRTIO_SERIAL_PORT(vcon); > diff --git a/hw/char/xilinx_uartlite.c b/hw/char/xilinx_uartlite.c > index 2c47275068..aa6bf02e21 100644 > --- a/hw/char/xilinx_uartlite.c > +++ b/hw/char/xilinx_uartlite.c > @@ -206,7 +206,7 @@ static int uart_can_rx(void *opaque) > return s->rx_fifo_len < sizeof(s->rx_fifo); > } > > -static void uart_event(void *opaque, int event) > +static void uart_event(void *opaque, QEMUChrEvent event) > { > > } > diff --git a/hw/ipmi/ipmi_bmc_extern.c b/hw/ipmi/ipmi_bmc_extern.c > index adf2afe728..16a4117ab0 100644 > --- a/hw/ipmi/ipmi_bmc_extern.c > +++ b/hw/ipmi/ipmi_bmc_extern.c > @@ -379,7 +379,7 @@ static void receive(void *opaque, const uint8_t *buf, int size) > handle_hw_op(ibe, hw_op); > } > > -static void chr_event(void *opaque, int event) > +static void chr_event(void *opaque, QEMUChrEvent event) > { > IPMIBmcExtern *ibe = opaque; > IPMIInterface *s = ibe->parent.intf; > diff --git a/hw/mips/boston.c b/hw/mips/boston.c > index ca7d813a52..29b476b4bd 100644 > --- a/hw/mips/boston.c > +++ b/hw/mips/boston.c > @@ -98,7 +98,7 @@ enum boston_plat_reg { > PLAT_SYS_CTL = 0x48, > }; > > -static void boston_lcd_event(void *opaque, int event) > +static void boston_lcd_event(void *opaque, QEMUChrEvent event) > { > BostonState *s = opaque; > if (event == CHR_EVENT_OPENED && !s->lcd_inited) { > diff --git a/hw/mips/mips_malta.c b/hw/mips/mips_malta.c > index 783cd99848..72c03baa8e 100644 > --- a/hw/mips/mips_malta.c > +++ b/hw/mips/mips_malta.c > @@ -545,7 +545,7 @@ static void malta_fpga_reset(void *opaque) > snprintf(s->display_text, 9, " "); > } > > -static void malta_fgpa_display_event(void *opaque, int event) > +static void malta_fgpa_display_event(void *opaque, QEMUChrEvent event) > { > MaltaFPGAState *s = opaque; > > diff --git a/hw/riscv/riscv_htif.c b/hw/riscv/riscv_htif.c > index 4f7b11dc37..ca87a5cf9f 100644 > --- a/hw/riscv/riscv_htif.c > +++ b/hw/riscv/riscv_htif.c > @@ -96,7 +96,7 @@ static void htif_recv(void *opaque, const uint8_t *buf, int size) > * Called by the char dev to supply special events to the HTIF console. > * Not used for HTIF. > */ > -static void htif_event(void *opaque, int event) > +static void htif_event(void *opaque, QEMUChrEvent event) > { > > } > diff --git a/hw/riscv/sifive_uart.c b/hw/riscv/sifive_uart.c > index a403ae90f5..9350482662 100644 > --- a/hw/riscv/sifive_uart.c > +++ b/hw/riscv/sifive_uart.c > @@ -162,7 +162,7 @@ static int uart_can_rx(void *opaque) > return s->rx_fifo_len < sizeof(s->rx_fifo); > } > > -static void uart_event(void *opaque, int event) > +static void uart_event(void *opaque, QEMUChrEvent event) > { > } > > diff --git a/hw/usb/ccid-card-passthru.c b/hw/usb/ccid-card-passthru.c > index e53696c07a..3d40b700db 100644 > --- a/hw/usb/ccid-card-passthru.c > +++ b/hw/usb/ccid-card-passthru.c > @@ -307,7 +307,7 @@ static void ccid_card_vscard_read(void *opaque, const uint8_t *buf, int size) > } > } > > -static void ccid_card_vscard_event(void *opaque, int event) > +static void ccid_card_vscard_event(void *opaque, QEMUChrEvent event) > { > PassthruState *card = opaque; > > diff --git a/hw/usb/dev-serial.c b/hw/usb/dev-serial.c > index 2ba6870b37..9646fe77da 100644 > --- a/hw/usb/dev-serial.c > +++ b/hw/usb/dev-serial.c > @@ -461,7 +461,7 @@ static void usb_serial_read(void *opaque, const uint8_t *buf, int size) > s->recv_used += size; > } > > -static void usb_serial_event(void *opaque, int event) > +static void usb_serial_event(void *opaque, QEMUChrEvent event) > { > USBSerialState *s = opaque; > > diff --git a/hw/usb/redirect.c b/hw/usb/redirect.c > index ddc1a59cb4..0068aa8a19 100644 > --- a/hw/usb/redirect.c > +++ b/hw/usb/redirect.c > @@ -1354,7 +1354,7 @@ static void usbredir_chardev_read(void *opaque, const uint8_t *buf, int size) > usbredirparser_do_write(dev->parser); > } > > -static void usbredir_chardev_event(void *opaque, int event) > +static void usbredir_chardev_event(void *opaque, QEMUChrEvent event) > { > USBRedirDevice *dev = opaque; > > diff --git a/monitor/hmp.c b/monitor/hmp.c > index 706ebe7074..944fa9651e 100644 > --- a/monitor/hmp.c > +++ b/monitor/hmp.c > @@ -1322,7 +1322,7 @@ static void monitor_read(void *opaque, const uint8_t *buf, int size) > cur_mon = old_mon; > } > > -static void monitor_event(void *opaque, int event) > +static void monitor_event(void *opaque, QEMUChrEvent event) > { > Monitor *mon = opaque; > MonitorHMP *hmp_mon = container_of(mon, MonitorHMP, common); > diff --git a/monitor/qmp.c b/monitor/qmp.c > index 6c46be40f8..54c06ba824 100644 > --- a/monitor/qmp.c > +++ b/monitor/qmp.c > @@ -337,7 +337,7 @@ static QDict *qmp_greeting(MonitorQMP *mon) > ver, cap_list); > } > > -static void monitor_qmp_event(void *opaque, int event) > +static void monitor_qmp_event(void *opaque, QEMUChrEvent event) > { > QDict *data; > MonitorQMP *mon = opaque; > diff --git a/net/filter-mirror.c b/net/filter-mirror.c > index 8d36009c53..d83e815545 100644 > --- a/net/filter-mirror.c > +++ b/net/filter-mirror.c > @@ -132,7 +132,7 @@ static void redirector_chr_read(void *opaque, const uint8_t *buf, int size) > } > } > > -static void redirector_chr_event(void *opaque, int event) > +static void redirector_chr_event(void *opaque, QEMUChrEvent event) > { > NetFilterState *nf = opaque; > MirrorState *s = FILTER_REDIRECTOR(nf); > diff --git a/net/vhost-user.c b/net/vhost-user.c > index c54c9c7d4c..17532daaf3 100644 > --- a/net/vhost-user.c > +++ b/net/vhost-user.c > @@ -218,7 +218,7 @@ static gboolean net_vhost_user_watch(GIOChannel *chan, GIOCondition cond, > return TRUE; > } > > -static void net_vhost_user_event(void *opaque, int event); > +static void net_vhost_user_event(void *opaque, QEMUChrEvent event); > > static void chr_closed_bh(void *opaque) > { > @@ -249,7 +249,7 @@ static void chr_closed_bh(void *opaque) > } > } > > -static void net_vhost_user_event(void *opaque, int event) > +static void net_vhost_user_event(void *opaque, QEMUChrEvent event) > { > const char *name = opaque; > NetClientState *ncs[MAX_QUEUE_NUM]; > diff --git a/qtest.c b/qtest.c > index 8b50e2783e..12432f99cf 100644 > --- a/qtest.c > +++ b/qtest.c > @@ -722,7 +722,7 @@ static int qtest_can_read(void *opaque) > return 1024; > } > > -static void qtest_event(void *opaque, int event) > +static void qtest_event(void *opaque, QEMUChrEvent event) > { > int i; > > diff --git a/tests/test-char.c b/tests/test-char.c > index 45e42af290..3afc9b1b8d 100644 > --- a/tests/test-char.c > +++ b/tests/test-char.c > @@ -54,7 +54,7 @@ static void fe_read(void *opaque, const uint8_t *buf, int size) > quit = true; > } > > -static void fe_event(void *opaque, int event) > +static void fe_event(void *opaque, QEMUChrEvent event) > { > FeHandler *h = opaque; > bool new_open_state; > @@ -633,7 +633,7 @@ typedef struct { > > > static void > -char_socket_event(void *opaque, int event) > +char_socket_event(void *opaque, QEMUChrEvent event) > { > CharSocketTestData *data = opaque; > data->event = event; > @@ -1006,7 +1006,7 @@ static void char_socket_client_test(gconstpointer opaque) > } > > static void > -count_closed_event(void *opaque, int event) > +count_closed_event(void *opaque, QEMUChrEvent event) > { > int *count = opaque; > if (event == CHR_EVENT_CLOSED) { > diff --git a/tests/vhost-user-test.c b/tests/vhost-user-test.c > index 91ea373ba5..2324b964ad 100644 > --- a/tests/vhost-user-test.c > +++ b/tests/vhost-user-test.c > @@ -499,7 +499,7 @@ static TestServer *test_server_new(const gchar *name) > return server; > } > > -static void chr_event(void *opaque, int event) > +static void chr_event(void *opaque, QEMUChrEvent event) > { > TestServer *s = opaque; > > -- > 2.21.0 > From MAILER-DAEMON Wed Dec 18 14:26:03 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1ihexP-0007wf-H5 for mharc-qemu-arm@gnu.org; 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b=ek+mjTLHTOQcNSHk/dHQvj4eR83KV93+73b8c+gTvPprYH3OZw3El78yWY8okKL286EHuD yIFGAaSJ846GkBREMeXUTFUowvd8TuugzVJ3nxepl/dtuPmTugHQpZ10qyK0up3Cf2OB+s F3XNI4+Jetq50fEalq6qALa6bGotRzQ= Received: from mimecast-mx01.redhat.com (mimecast-mx01.redhat.com [209.132.183.4]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-363-Q_lPehRgNsK5fS0IdCXJ9Q-1; Wed, 18 Dec 2019 14:25:55 -0500 Received: from smtp.corp.redhat.com (int-mx02.intmail.prod.int.phx2.redhat.com [10.5.11.12]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx01.redhat.com (Postfix) with ESMTPS id 4B8A6107ACC4; Wed, 18 Dec 2019 19:25:52 +0000 (UTC) Received: from x1w.redhat.com (ovpn-116-235.ams2.redhat.com [10.36.116.235]) by smtp.corp.redhat.com (Postfix) with ESMTPS id 1697D60C81; Wed, 18 Dec 2019 19:25:40 +0000 (UTC) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Aleksandar Markovic , Andrew Jeffery , Andrey Smirnov , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Gerd Hoffmann , Jason Wang , Joel Stanley , =?UTF-8?q?K=C5=91v=C3=A1g=C3=B3=2C=20Zolt=C3=A1n?= , Mark Cave-Ayland , Markus Armbruster , Olivier Danet , Peter Chubb , Peter Maydell , qemu-arm@nongnu.org Subject: [PATCH v2 0/6] Fix more GCC9 -O3 warnings Date: Wed, 18 Dec 2019 20:25:20 +0100 Message-Id: <20191218192526.13845-1-philmd@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.79 on 10.5.11.12 X-MC-Unique: Q_lPehRgNsK5fS0IdCXJ9Q-1 X-Mimecast-Spam-Score: 0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 207.211.31.81 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 18 Dec 2019 19:26:02 -0000 Fix some trivial warnings when building with -O3. v2: - addressed Thomas and Aleksandar comments - dropped 'hw/scsi/megasas: Silent GCC9 duplicated-cond warning' - dropped 'qemu-io-cmds: Silent GCC9 format-overflow warning' Philippe Mathieu-Daud=C3=A9 (6): audio/audio: Add missing fall through comment hw/display/tcx: Add missing fall through comments hw/timer/aspeed_timer: Add a fall through comment hw/net/imx_fec: Rewrite fall through comments hw/net/imx_fec: Remove unuseful FALLTHROUGH comments hw/pci-host/designware: Remove unuseful FALLTHROUGH comment audio/audio.c | 1 + hw/display/tcx.c | 2 ++ hw/net/imx_fec.c | 7 ++++--- hw/pci-host/designware.c | 2 +- hw/timer/aspeed_timer.c | 2 +- 5 files changed, 9 insertions(+), 5 deletions(-) Cc: Aleksandar Markovic Cc: Andrew Jeffery Cc: Andrey Smirnov Cc: "C=C3=A9dric Le Goater" Cc: Gerd Hoffmann Cc: Jason Wang Cc: Joel Stanley Cc: "K=C5=91v=C3=A1g=C3=B3, Zolt=C3=A1n" Cc: Mark Cave-Ayland Cc: Markus Armbruster Cc: Olivier Danet Cc: Peter Chubb Cc: Peter Maydell Cc: qemu-arm@nongnu.org --=20 2.21.0 From MAILER-DAEMON Wed Dec 18 14:26:23 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1ihexj-0008Jl-E0 for mharc-qemu-arm@gnu.org; Wed, 18 Dec 2019 14:26:23 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:34314) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ihexZ-00088r-2T for qemu-arm@nongnu.org; Wed, 18 Dec 2019 14:26:17 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ihexW-0003ur-5i for qemu-arm@nongnu.org; Wed, 18 Dec 2019 14:26:12 -0500 Received: from us-smtp-delivery-1.mimecast.com ([207.211.31.120]:34673 helo=us-smtp-1.mimecast.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1ihexV-0003s1-Sd for qemu-arm@nongnu.org; Wed, 18 Dec 2019 14:26:09 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1576697169; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=TdxvmB9Qgxghb+PTOnONzrGSfc8UbEoa7GDLETeQHLY=; b=FufARakBJ6wVGTURsUbZuLvPkirJJDQxQJge8R0RQmPigHYH/y+6vxG76xeKjsWjJR1FPh nOmwEny/dQhdpH+fXgSSKVBLal6K3Adheb/8I/OUqFFC0fOzGvz/pNVyImiK8wuoXq9QEr jfCnWIY8CeYd7+KjKXmhOo/ddJ3p/E8= Received: from mimecast-mx01.redhat.com (mimecast-mx01.redhat.com [209.132.183.4]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-325-xXWuz7rlM1Cc8jiMhQbi7g-1; Wed, 18 Dec 2019 14:26:08 -0500 Received: from smtp.corp.redhat.com (int-mx02.intmail.prod.int.phx2.redhat.com [10.5.11.12]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx01.redhat.com (Postfix) with ESMTPS id 9FB5D8024D3; Wed, 18 Dec 2019 19:26:06 +0000 (UTC) Received: from x1w.redhat.com (ovpn-116-235.ams2.redhat.com [10.36.116.235]) by smtp.corp.redhat.com (Postfix) with ESMTPS id 98C6B60C81; Wed, 18 Dec 2019 19:26:01 +0000 (UTC) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Richard Henderson , Aleksandar Markovic , Peter Chubb , Peter Maydell , Jason Wang , qemu-arm@nongnu.org Subject: [PATCH v2 4/6] hw/net/imx_fec: Rewrite fall through comments Date: Wed, 18 Dec 2019 20:25:24 +0100 Message-Id: <20191218192526.13845-5-philmd@redhat.com> In-Reply-To: <20191218192526.13845-1-philmd@redhat.com> References: <20191218192526.13845-1-philmd@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.79 on 10.5.11.12 X-MC-Unique: xXWuz7rlM1Cc8jiMhQbi7g-1 X-Mimecast-Spam-Score: 0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 207.211.31.120 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 18 Dec 2019 19:26:19 -0000 GCC9 is confused by this comment when building with CFLAG -Wimplicit-fallthrough=3D2: hw/net/imx_fec.c: In function =E2=80=98imx_eth_write=E2=80=99: hw/net/imx_fec.c:906:12: error: this statement may fall through [-Werror= =3Dimplicit-fallthrough=3D] 906 | if (unlikely(single_tx_ring)) { | ^ hw/net/imx_fec.c:912:5: note: here 912 | case ENET_TDAR: /* FALLTHROUGH */ | ^~~~ cc1: all warnings being treated as errors Rewrite the comments in the correct place, using 'fall through' which is recognized by GCC and static analyzers. Reviewed-by: Richard Henderson Reviewed-by: Aleksandar Markovic Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- Cc: Peter Chubb Cc: Peter Maydell Cc: Jason Wang Cc: qemu-arm@nongnu.org --- hw/net/imx_fec.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/hw/net/imx_fec.c b/hw/net/imx_fec.c index bd99236864..c01ce4f078 100644 --- a/hw/net/imx_fec.c +++ b/hw/net/imx_fec.c @@ -909,7 +909,8 @@ static void imx_eth_write(void *opaque, hwaddr offset, = uint64_t value, TYPE_IMX_FEC, __func__); return; } - case ENET_TDAR: /* FALLTHROUGH */ + /* fall through */ + case ENET_TDAR: if (s->regs[ENET_ECR] & ENET_ECR_ETHEREN) { s->regs[index] =3D ENET_TDAR_TDAR; imx_eth_do_tx(s, index); --=20 2.21.0 From MAILER-DAEMON Wed Dec 18 14:26:23 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1ihexj-0008Jp-JJ for mharc-qemu-arm@gnu.org; Wed, 18 Dec 2019 14:26:23 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:34382) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ihexd-0008DJ-OQ for qemu-arm@nongnu.org; Wed, 18 Dec 2019 14:26:19 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ihexV-0003sr-Px for qemu-arm@nongnu.org; Wed, 18 Dec 2019 14:26:12 -0500 Received: from us-smtp-1.mimecast.com ([207.211.31.81]:42155 helo=us-smtp-delivery-1.mimecast.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1ihexV-0003q6-Gq for qemu-arm@nongnu.org; Wed, 18 Dec 2019 14:26:09 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1576697169; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=gvKn3E3vtip/x6nya4V8EKu5DfUXiZ0uZoETj2uOGIA=; b=XY7zuboI4EDk1jbicx6fgWAMwqopGyBorE6PU7djruSg42ylBNsiV8o1xRDGeotdOLZz2p 15TGVjZD0GMOPlPCPPCbgZPmTOiM7AgmRMX5GxWl5lQWSo4t0aTRZ3Kj9W47RGXRfL02zy 0mfw+W6+kTgzY1KyHfnsN1Uf8Ljsjj8= Received: from mimecast-mx01.redhat.com (mimecast-mx01.redhat.com [209.132.183.4]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-207-0lMZT4nyOxiOKML3-m51UQ-1; Wed, 18 Dec 2019 14:26:03 -0500 Received: from smtp.corp.redhat.com (int-mx02.intmail.prod.int.phx2.redhat.com [10.5.11.12]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx01.redhat.com (Postfix) with ESMTPS id 42AE212BA84; Wed, 18 Dec 2019 19:26:01 +0000 (UTC) Received: from x1w.redhat.com (ovpn-116-235.ams2.redhat.com [10.36.116.235]) by smtp.corp.redhat.com (Postfix) with ESMTPS id 9C44D60C81; Wed, 18 Dec 2019 19:25:58 +0000 (UTC) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Aleksandar Markovic , Peter Maydell , Andrew Jeffery , Joel Stanley , qemu-arm@nongnu.org Subject: [PATCH v2 3/6] hw/timer/aspeed_timer: Add a fall through comment Date: Wed, 18 Dec 2019 20:25:23 +0100 Message-Id: <20191218192526.13845-4-philmd@redhat.com> In-Reply-To: <20191218192526.13845-1-philmd@redhat.com> References: <20191218192526.13845-1-philmd@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.79 on 10.5.11.12 X-MC-Unique: 0lMZT4nyOxiOKML3-m51UQ-1 X-Mimecast-Spam-Score: 0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 207.211.31.81 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 18 Dec 2019 19:26:19 -0000 Reported by GCC9 when building with CFLAG -Wimplicit-fallthrough=3D2: hw/timer/aspeed_timer.c: In function =E2=80=98aspeed_timer_set_value=E2= =80=99: hw/timer/aspeed_timer.c:283:24: error: this statement may fall through [-= Werror=3Dimplicit-fallthrough=3D] 283 | if (old_reload || !t->reload) { | ~~~~~~~~~~~^~~~~~~~~~~~~ hw/timer/aspeed_timer.c:287:5: note: here 287 | case TIMER_REG_STATUS: | ^~~~ cc1: all warnings being treated as errors Add the missing fall through comment. Fixes: 1403f364472 Reviewed-by: C=C3=A9dric Le Goater Reviewed-by: Aleksandar Markovic Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- Cc: "C=C3=A9dric Le Goater" Cc: Peter Maydell Cc: Andrew Jeffery Cc: Joel Stanley Cc: qemu-arm@nongnu.org --- hw/timer/aspeed_timer.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/timer/aspeed_timer.c b/hw/timer/aspeed_timer.c index a8c38cc118..c91f18415c 100644 --- a/hw/timer/aspeed_timer.c +++ b/hw/timer/aspeed_timer.c @@ -283,7 +283,7 @@ static void aspeed_timer_set_value(AspeedTimerCtrlState= *s, int timer, int reg, if (old_reload || !t->reload) { break; } - + /* fall through to re-enable */ case TIMER_REG_STATUS: if (timer_enabled(t)) { uint64_t now =3D qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); --=20 2.21.0 From MAILER-DAEMON Wed Dec 18 14:26:26 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1ihexm-0008PR-Bq for mharc-qemu-arm@gnu.org; Wed, 18 Dec 2019 14:26:26 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:34556) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ihexi-0008IO-7K for qemu-arm@nongnu.org; Wed, 18 Dec 2019 14:26:24 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ihexf-00044j-ST for qemu-arm@nongnu.org; Wed, 18 Dec 2019 14:26:21 -0500 Received: from us-smtp-delivery-1.mimecast.com ([207.211.31.120]:42349 helo=us-smtp-1.mimecast.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1ihexf-0003yN-NQ for qemu-arm@nongnu.org; Wed, 18 Dec 2019 14:26:19 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1576697172; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=vYieTMV2GGryjAYltk1B6hSeskuepnCEd/upKBPg6sc=; b=M6fdaq1Yt4oPBsyMg23IXo+khTps7qQ4oAiOYM7Jdk3A8HUd74Bdk2qMjW3oCyyHMyeUIC o6hGUi3YanVcgqP6rWNsMaNwjWh1cQx/xHmwDlki4FN5OpSwV+cWMNXVv8pulelNWpxQeB Npcv9svB4bLl2xw7SfZ1UyODNFM+2y8= Received: from mimecast-mx01.redhat.com (mimecast-mx01.redhat.com [209.132.183.4]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-223-GKU3JQVBO16wNXnwHLjn3A-1; Wed, 18 Dec 2019 14:26:11 -0500 Received: from smtp.corp.redhat.com (int-mx02.intmail.prod.int.phx2.redhat.com [10.5.11.12]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx01.redhat.com (Postfix) with ESMTPS id E3E60801E6C; Wed, 18 Dec 2019 19:26:09 +0000 (UTC) Received: from x1w.redhat.com (ovpn-116-235.ams2.redhat.com [10.36.116.235]) by smtp.corp.redhat.com (Postfix) with ESMTPS id 002A260C84; Wed, 18 Dec 2019 19:26:06 +0000 (UTC) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Thomas Huth , Peter Chubb , Markus Armbruster , Peter Maydell , Jason Wang , qemu-arm@nongnu.org Subject: [RFC PATCH v2 5/6] hw/net/imx_fec: Remove unuseful FALLTHROUGH comments Date: Wed, 18 Dec 2019 20:25:25 +0100 Message-Id: <20191218192526.13845-6-philmd@redhat.com> In-Reply-To: <20191218192526.13845-1-philmd@redhat.com> References: <20191218192526.13845-1-philmd@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.79 on 10.5.11.12 X-MC-Unique: GKU3JQVBO16wNXnwHLjn3A-1 X-Mimecast-Spam-Score: 0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 207.211.31.120 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 18 Dec 2019 19:26:25 -0000 We don't need to explicit these obvious switch fall through comments. Stay consistent with the rest of the codebase. Suggested-by: Thomas Huth Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- Cc: Peter Chubb Cc: Markus Armbruster Cc: Peter Maydell Cc: Jason Wang Cc: qemu-arm@nongnu.org --- hw/net/imx_fec.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/hw/net/imx_fec.c b/hw/net/imx_fec.c index c01ce4f078..5a83678f64 100644 --- a/hw/net/imx_fec.c +++ b/hw/net/imx_fec.c @@ -901,8 +901,8 @@ static void imx_eth_write(void *opaque, hwaddr offset, = uint64_t value, s->regs[index] =3D 0; } break; - case ENET_TDAR1: /* FALLTHROUGH */ - case ENET_TDAR2: /* FALLTHROUGH */ + case ENET_TDAR1: + case ENET_TDAR2: if (unlikely(single_tx_ring)) { qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: trying to access TDAR2 or TDAR1\n", --=20 2.21.0 From MAILER-DAEMON Wed Dec 18 14:26:27 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1ihexn-0008Rq-IG for mharc-qemu-arm@gnu.org; Wed, 18 Dec 2019 14:26:27 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:34620) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ihexj-0008Jq-H2 for qemu-arm@nongnu.org; Wed, 18 Dec 2019 14:26:24 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ihexh-00045s-LH for qemu-arm@nongnu.org; Wed, 18 Dec 2019 14:26:23 -0500 Received: from us-smtp-1.mimecast.com ([205.139.110.61]:55824 helo=us-smtp-delivery-1.mimecast.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1ihexf-00040H-NT for qemu-arm@nongnu.org; Wed, 18 Dec 2019 14:26:19 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1576697175; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=Y6YG32m8JkF0CpWQ1Sg7hx1MiUEtHJOD6PbN9L9fnDQ=; b=G3LIoWHe7MpEawC90M2Ah2AbGBmAhOqMXGDk4+PRrh7JQZ+YzTTMFI+2OG9O8Sz64xlSsu k9T1cRDsIttFm3rhu628aUcc244d5CY4BVfEF9Btczy1INh+8WXdscJP/Gj/jaraEsi0rA lapxt94JmgMY59eCwpUwF1FK8SUt7Qg= Received: from mimecast-mx01.redhat.com (mimecast-mx01.redhat.com [209.132.183.4]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-86-TnFNLP5ZPDqKdARPyQIwwA-1; Wed, 18 Dec 2019 14:26:14 -0500 Received: from smtp.corp.redhat.com (int-mx02.intmail.prod.int.phx2.redhat.com [10.5.11.12]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx01.redhat.com (Postfix) with ESMTPS id C530A12BA84; Wed, 18 Dec 2019 19:26:12 +0000 (UTC) Received: from x1w.redhat.com (ovpn-116-235.ams2.redhat.com [10.36.116.235]) by smtp.corp.redhat.com (Postfix) with ESMTPS id 7C51B60C81; Wed, 18 Dec 2019 19:26:10 +0000 (UTC) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Peter Chubb , Markus Armbruster , Peter Maydell , Andrey Smirnov , qemu-arm@nongnu.org Subject: [RFC PATCH v2 6/6] hw/pci-host/designware: Remove unuseful FALLTHROUGH comment Date: Wed, 18 Dec 2019 20:25:26 +0100 Message-Id: <20191218192526.13845-7-philmd@redhat.com> In-Reply-To: <20191218192526.13845-1-philmd@redhat.com> References: <20191218192526.13845-1-philmd@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.79 on 10.5.11.12 X-MC-Unique: TnFNLP5ZPDqKdARPyQIwwA-1 X-Mimecast-Spam-Score: 0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 205.139.110.61 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 18 Dec 2019 19:26:25 -0000 We don't need to explicit this obvious switch fall through. Stay consistent with the rest of the codebase. Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- Cc: Peter Chubb Cc: Markus Armbruster Cc: Peter Maydell Cc: Andrey Smirnov Cc: qemu-arm@nongnu.org --- hw/pci-host/designware.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/pci-host/designware.c b/hw/pci-host/designware.c index 71e9b0d9b5..dd245516dd 100644 --- a/hw/pci-host/designware.c +++ b/hw/pci-host/designware.c @@ -182,7 +182,7 @@ designware_pcie_root_config_read(PCIDevice *d, uint32_t= address, int len) break; =20 case DESIGNWARE_PCIE_ATU_CR1: - case DESIGNWARE_PCIE_ATU_CR2: /* FALLTHROUGH */ + case DESIGNWARE_PCIE_ATU_CR2: val =3D viewport->cr[(address - DESIGNWARE_PCIE_ATU_CR1) / sizeof(uint32_t)]; break; --=20 2.21.0 From MAILER-DAEMON Wed Dec 18 14:28:48 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1ihf04-0002vT-3P for mharc-qemu-arm@gnu.org; Wed, 18 Dec 2019 14:28:48 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:56462) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ihf01-0002pf-4R for qemu-arm@nongnu.org; Wed, 18 Dec 2019 14:28:46 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ihezy-0003st-UF for qemu-arm@nongnu.org; Wed, 18 Dec 2019 14:28:43 -0500 Received: from us-smtp-2.mimecast.com ([207.211.31.81]:45457 helo=us-smtp-delivery-1.mimecast.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1ihezy-0003nG-LJ for qemu-arm@nongnu.org; Wed, 18 Dec 2019 14:28:42 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1576697319; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references:openpgp:openpgp; bh=sWLA50tMKnGCQKtua0vEBQXsCJiICSj38z3R+eLXr84=; b=XgEAO99TB2chaovLg3d3SvYtSiqkXiLSW0CPoiLtyAz6jVD07NJx4mpgjIQuOQT/ganIB0 99eZxdthSfwM/Qoffd3pIpCyK2P9/L/O6akcq0ZpjXE18SgS5ItSx+ANd0i8aHCQ2doJIK 0AVB5su9ZQxzRPneSNH5ExLZnadLYoU= Received: from mimecast-mx01.redhat.com (mimecast-mx01.redhat.com [209.132.183.4]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-333-KNTBxx16P4StjFBZEgxsig-1; Wed, 18 Dec 2019 14:28:38 -0500 Received: from smtp.corp.redhat.com (int-mx04.intmail.prod.int.phx2.redhat.com [10.5.11.14]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx01.redhat.com (Postfix) with ESMTPS id 54A01800D41; Wed, 18 Dec 2019 19:28:37 +0000 (UTC) Received: from thuth.remote.csb (ovpn-116-120.ams2.redhat.com [10.36.116.120]) by smtp.corp.redhat.com (Postfix) with ESMTPS id 33ED15D9E2; Wed, 18 Dec 2019 19:28:32 +0000 (UTC) Subject: Re: [RFC PATCH v2 5/6] hw/net/imx_fec: Remove unuseful FALLTHROUGH comments To: =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= , qemu-devel@nongnu.org Cc: Peter Chubb , Markus Armbruster , Peter Maydell , Jason Wang , qemu-arm@nongnu.org References: <20191218192526.13845-1-philmd@redhat.com> <20191218192526.13845-6-philmd@redhat.com> From: Thomas Huth Openpgp: preference=signencrypt Message-ID: <4a2cd906-0094-2e10-d882-24d6794245e0@redhat.com> Date: Wed, 18 Dec 2019 20:28:31 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101 Thunderbird/60.9.0 MIME-Version: 1.0 In-Reply-To: <20191218192526.13845-6-philmd@redhat.com> Content-Language: en-US X-Scanned-By: MIMEDefang 2.79 on 10.5.11.14 X-MC-Unique: KNTBxx16P4StjFBZEgxsig-1 X-Mimecast-Spam-Score: 0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 207.211.31.81 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 18 Dec 2019 19:28:47 -0000 On 18/12/2019 20.25, Philippe Mathieu-Daud=C3=A9 wrote: > We don't need to explicit these obvious switch fall through > comments. Stay consistent with the rest of the codebase. >=20 > Suggested-by: Thomas Huth > Signed-off-by: Philippe Mathieu-Daud=C3=A9 ... > diff --git a/hw/net/imx_fec.c b/hw/net/imx_fec.c > index c01ce4f078..5a83678f64 100644 > --- a/hw/net/imx_fec.c > +++ b/hw/net/imx_fec.c > @@ -901,8 +901,8 @@ static void imx_eth_write(void *opaque, hwaddr offset= , uint64_t value, > s->regs[index] =3D 0; > } > break; > - case ENET_TDAR1: /* FALLTHROUGH */ > - case ENET_TDAR2: /* FALLTHROUGH */ > + case ENET_TDAR1: > + case ENET_TDAR2: > if (unlikely(single_tx_ring)) { > qemu_log_mask(LOG_GUEST_ERROR, > "[%s]%s: trying to access TDAR2 or TDAR1\n", Reviewed-by: Thomas Huth From MAILER-DAEMON Wed Dec 18 14:33:09 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1ihf4G-0007D9-QO for mharc-qemu-arm@gnu.org; Wed, 18 Dec 2019 14:33:08 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:34825) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ihf4E-00079I-44 for qemu-arm@nongnu.org; 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Wed, 18 Dec 2019 14:32:59 -0500 Received: from smtp.corp.redhat.com (int-mx08.intmail.prod.int.phx2.redhat.com [10.5.11.23]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx01.redhat.com (Postfix) with ESMTPS id 251441005502; Wed, 18 Dec 2019 19:32:58 +0000 (UTC) Received: from thuth.remote.csb (ovpn-116-120.ams2.redhat.com [10.36.116.120]) by smtp.corp.redhat.com (Postfix) with ESMTPS id 31D1F19C58; Wed, 18 Dec 2019 19:32:52 +0000 (UTC) Subject: Re: [RFC PATCH v2 6/6] hw/pci-host/designware: Remove unuseful FALLTHROUGH comment To: =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= , qemu-devel@nongnu.org Cc: Peter Maydell , Andrey Smirnov , Markus Armbruster , qemu-arm@nongnu.org, Peter Chubb References: <20191218192526.13845-1-philmd@redhat.com> <20191218192526.13845-7-philmd@redhat.com> From: Thomas Huth Openpgp: preference=signencrypt Message-ID: <1f498b45-f32d-7883-69dc-8a75a39a89bd@redhat.com> Date: Wed, 18 Dec 2019 20:32:51 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101 Thunderbird/60.9.0 MIME-Version: 1.0 In-Reply-To: <20191218192526.13845-7-philmd@redhat.com> Content-Language: en-US X-Scanned-By: MIMEDefang 2.84 on 10.5.11.23 X-MC-Unique: 8BShiiLxMCaMY3Xu5ZA6RA-1 X-Mimecast-Spam-Score: 0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 205.139.110.120 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 18 Dec 2019 19:33:07 -0000 On 18/12/2019 20.25, Philippe Mathieu-Daud=C3=A9 wrote: > We don't need to explicit this obvious switch fall through. > Stay consistent with the rest of the codebase. >=20 > Signed-off-by: Philippe Mathieu-Daud=C3=A9 > --- > Cc: Peter Chubb > Cc: Markus Armbruster > Cc: Peter Maydell > Cc: Andrey Smirnov > Cc: qemu-arm@nongnu.org > --- > hw/pci-host/designware.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) >=20 > diff --git a/hw/pci-host/designware.c b/hw/pci-host/designware.c > index 71e9b0d9b5..dd245516dd 100644 > --- a/hw/pci-host/designware.c > +++ b/hw/pci-host/designware.c > @@ -182,7 +182,7 @@ designware_pcie_root_config_read(PCIDevice *d, uint32= _t address, int len) > break; > =20 > case DESIGNWARE_PCIE_ATU_CR1: > - case DESIGNWARE_PCIE_ATU_CR2: /* FALLTHROUGH */ > + case DESIGNWARE_PCIE_ATU_CR2: > val =3D viewport->cr[(address - DESIGNWARE_PCIE_ATU_CR1) / > sizeof(uint32_t)]; > break; >=20 Reviewed-by: Thomas Huth From MAILER-DAEMON Wed Dec 18 14:35:41 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1ihf6j-00014s-EP for mharc-qemu-arm@gnu.org; Wed, 18 Dec 2019 14:35:41 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:35293) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ihf6g-00011x-Fm for qemu-arm@nongnu.org; Wed, 18 Dec 2019 14:35:39 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ihf6e-0003Rd-SL for qemu-arm@nongnu.org; Wed, 18 Dec 2019 14:35:38 -0500 Received: from mail-ot1-x343.google.com ([2607:f8b0:4864:20::343]:39974) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ihf6b-0003CP-W4; Wed, 18 Dec 2019 14:35:34 -0500 Received: by mail-ot1-x343.google.com with SMTP id i15so3832751oto.7; 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Wed, 18 Dec 2019 11:35:32 -0800 (PST) MIME-Version: 1.0 References: <20191218192526.13845-1-philmd@redhat.com> <20191218192526.13845-7-philmd@redhat.com> In-Reply-To: <20191218192526.13845-7-philmd@redhat.com> From: Aleksandar Markovic Date: Wed, 18 Dec 2019 20:35:21 +0100 Message-ID: Subject: Re: [RFC PATCH v2 6/6] hw/pci-host/designware: Remove unuseful FALLTHROUGH comment To: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= Cc: QEMU Developers , Peter Maydell , Andrey Smirnov , Markus Armbruster , "open list:Stellaris" , Peter Chubb Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::343 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 18 Dec 2019 19:35:39 -0000 On Wed, Dec 18, 2019 at 8:29 PM Philippe Mathieu-Daud=C3=A9 wrote: > > We don't need to explicit this obvious switch fall through. > Stay consistent with the rest of the codebase. > > Signed-off-by: Philippe Mathieu-Daud=C3=A9 > --- Reviewed-by: Aleksandar Markovic > Cc: Peter Chubb > Cc: Markus Armbruster > Cc: Peter Maydell > Cc: Andrey Smirnov > Cc: qemu-arm@nongnu.org > --- > hw/pci-host/designware.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/hw/pci-host/designware.c b/hw/pci-host/designware.c > index 71e9b0d9b5..dd245516dd 100644 > --- a/hw/pci-host/designware.c > +++ b/hw/pci-host/designware.c > @@ -182,7 +182,7 @@ designware_pcie_root_config_read(PCIDevice *d, uint32= _t address, int len) > break; > > case DESIGNWARE_PCIE_ATU_CR1: > - case DESIGNWARE_PCIE_ATU_CR2: /* FALLTHROUGH */ > + case DESIGNWARE_PCIE_ATU_CR2: > val =3D viewport->cr[(address - DESIGNWARE_PCIE_ATU_CR1) / > sizeof(uint32_t)]; > break; > -- > 2.21.0 > > From MAILER-DAEMON Wed Dec 18 14:36:00 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1ihf72-0001Kc-Gm for mharc-qemu-arm@gnu.org; Wed, 18 Dec 2019 14:36:00 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:37288) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ihf70-0001Hj-AT for qemu-arm@nongnu.org; Wed, 18 Dec 2019 14:35:59 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ihf6z-0004IR-58 for qemu-arm@nongnu.org; Wed, 18 Dec 2019 14:35:58 -0500 Received: from mail-oi1-x244.google.com ([2607:f8b0:4864:20::244]:39610) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ihf6w-000459-HH; Wed, 18 Dec 2019 14:35:54 -0500 Received: by mail-oi1-x244.google.com with SMTP id a67so1739415oib.6; Wed, 18 Dec 2019 11:35:54 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc:content-transfer-encoding; bh=VK5GlKScKbS+LVQgUi0a1RrhyXld8LpQu4ZIhT+sCNU=; b=GcHqLelclak/OyqMf38yZqxV5ZiMqkKMutruD8DaF04uaoSjHPCNUV2AGeYFzx7A6b g3AGX2NBV1YTqljlNJ+WHHw+ovx1dg01hKfl5OlVI/ainIUZV3Qen0wGzLPvqCiXOVfJ KSR6fbVWjf+GSF18wfEh/YnclX2/NLrR+mHGfPw1favDLCKwekrI32nhxSCRw4NIW+o8 EIDrYllbHbJcwtp70emV3nQIvrzpwehKinz3nbuJQsRiKV1O630MEJ/4nplsrl1HbINt idFseZ5JscYmRBrpaEzYxJ6tu3SK1hvaDhjUF2uztkGrLmV4n5Of7ghOnP/aLwHCtCEl 8d/w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc:content-transfer-encoding; bh=VK5GlKScKbS+LVQgUi0a1RrhyXld8LpQu4ZIhT+sCNU=; b=D/ht3JyrkRoY4pP5UWir+AiS6bFg6MqLhrjydOY4WfElv00kQF/RYmGefn98HRaL5R 8finnP9fVA05+gbEvJGBQ/hAXlhyyUAxtUZDrxQCMECKFcnnZpF+FdfV8PPaIef92IXk P/kUVu29nsN2m/PqIE20J6rgzoQg5F9IxJE3AktHXDkxIeECswB3N6z+w3xo7wX0fj4I pKU0GjjDEJxCx+4/4MHsAcAseo0RK+xoKxMjmxmPwmVYDpfzurA5dUkg8qe8KgETJT5T NMbzyFpisGm/rZ8JW6dhdESpG+loomjHZEvBvZs2Afkqndz+32pHWmEupTwWFlMvQp7r 63rg== X-Gm-Message-State: APjAAAU3UVhovvlFNfuCTv4WqWkPqFp0Q6em+U55Rno0kX+7wrpfhUV/ to7X7e+EdF031gzZQl11pBe0iCRUS6QY/ucuGeg= X-Google-Smtp-Source: APXvYqxzcBNqABZZ37apWPolbGs8nBof19JxLJKIrqt9w8Y6lh583PclgQR9rFTXLwwoiwUCC3WuRdD3gnNX55kTrmM= X-Received: by 2002:aca:1b08:: with SMTP id b8mr1236876oib.106.1576697753655; Wed, 18 Dec 2019 11:35:53 -0800 (PST) MIME-Version: 1.0 References: <20191218192526.13845-1-philmd@redhat.com> <20191218192526.13845-6-philmd@redhat.com> In-Reply-To: <20191218192526.13845-6-philmd@redhat.com> From: Aleksandar Markovic Date: Wed, 18 Dec 2019 20:35:42 +0100 Message-ID: Subject: Re: [RFC PATCH v2 5/6] hw/net/imx_fec: Remove unuseful FALLTHROUGH comments To: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= Cc: QEMU Developers , Peter Maydell , Thomas Huth , Jason Wang , Markus Armbruster , "open list:Stellaris" , Peter Chubb Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::244 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 18 Dec 2019 19:35:59 -0000 On Wed, Dec 18, 2019 at 8:29 PM Philippe Mathieu-Daud=C3=A9 wrote: > > We don't need to explicit these obvious switch fall through > comments. Stay consistent with the rest of the codebase. > > Suggested-by: Thomas Huth > Signed-off-by: Philippe Mathieu-Daud=C3=A9 > --- Reviewed-by: Aleksandar Markovic > Cc: Peter Chubb > Cc: Markus Armbruster > Cc: Peter Maydell > Cc: Jason Wang > Cc: qemu-arm@nongnu.org > --- > hw/net/imx_fec.c | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git a/hw/net/imx_fec.c b/hw/net/imx_fec.c > index c01ce4f078..5a83678f64 100644 > --- a/hw/net/imx_fec.c > +++ b/hw/net/imx_fec.c > @@ -901,8 +901,8 @@ static void imx_eth_write(void *opaque, hwaddr offset= , uint64_t value, > s->regs[index] =3D 0; > } > break; > - case ENET_TDAR1: /* FALLTHROUGH */ > - case ENET_TDAR2: /* FALLTHROUGH */ > + case ENET_TDAR1: > + case ENET_TDAR2: > if (unlikely(single_tx_ring)) { > qemu_log_mask(LOG_GUEST_ERROR, > "[%s]%s: trying to access TDAR2 or TDAR1\n", > -- > 2.21.0 > > From MAILER-DAEMON Wed Dec 18 14:36:17 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1ihf7I-0001ef-T8 for mharc-qemu-arm@gnu.org; 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bh=GiprSwdHZ/Z6TSNz/6DxrHEnQe0kiuxGby8tvQrTjLc=; b=EPzTB81Y8skjfkM8vtZC19G/vLoAopcKCqiCdGhCb9O2jLqpkek2qR5EHg6R8Ckl5oztFb eNpNo/i58IDeB7izjH8GmxsZiTC7bVin+uzCNHCYsDMt1tOg0YpmgSOcvpt2OuwXkIkvmF isv92fl4CRIZ5fIzSfrQ9FM/2kY09K8= Received: from mimecast-mx01.redhat.com (mimecast-mx01.redhat.com [209.132.183.4]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-320-WxuNooOsNP2TC_FJfZ2PFQ-1; Wed, 18 Dec 2019 14:35:57 -0500 Received: from smtp.corp.redhat.com (int-mx04.intmail.prod.int.phx2.redhat.com [10.5.11.14]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx01.redhat.com (Postfix) with ESMTPS id 5E8C4102CE16; Wed, 18 Dec 2019 19:35:54 +0000 (UTC) Received: from thuth.remote.csb (ovpn-116-120.ams2.redhat.com [10.36.116.120]) by smtp.corp.redhat.com (Postfix) with ESMTPS id 56DAE5D9E2; Wed, 18 Dec 2019 19:35:50 +0000 (UTC) Subject: Re: [PATCH 3/6] hw/net/imx_fec: Rewrite fall through comments From: Thomas Huth To: =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= , qemu-devel@nongnu.org Cc: Peter Maydell , qemu-trivial@nongnu.org, Jason Wang , qemu-arm@nongnu.org, Peter Chubb References: <20191217173425.5082-1-philmd@redhat.com> <20191217173425.5082-4-philmd@redhat.com> <2fc74b64-0a0b-c437-e925-4c16d3907da7@redhat.com> Openpgp: preference=signencrypt Message-ID: <54e5071f-b5c2-3cc7-514c-ecc2b7e2bed4@redhat.com> Date: Wed, 18 Dec 2019 20:35:48 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101 Thunderbird/60.9.0 MIME-Version: 1.0 In-Reply-To: <2fc74b64-0a0b-c437-e925-4c16d3907da7@redhat.com> Content-Language: en-US X-Scanned-By: MIMEDefang 2.79 on 10.5.11.14 X-MC-Unique: WxuNooOsNP2TC_FJfZ2PFQ-1 X-Mimecast-Spam-Score: 0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 205.139.110.61 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 18 Dec 2019 19:36:15 -0000 On 17/12/2019 18.55, Thomas Huth wrote: > On 17/12/2019 18.34, Philippe Mathieu-Daud=C3=A9 wrote: >> GCC9 is confused by this comment when building with CFLAG >> -Wimplicit-fallthrough=3D2: >> >> hw/net/imx_fec.c: In function =E2=80=98imx_eth_write=E2=80=99: >> hw/net/imx_fec.c:906:12: error: this statement may fall through [-Werr= or=3Dimplicit-fallthrough=3D] >> 906 | if (unlikely(single_tx_ring)) { >> | ^ >> hw/net/imx_fec.c:912:5: note: here >> 912 | case ENET_TDAR: /* FALLTHROUGH */ >> | ^~~~ >> cc1: all warnings being treated as errors >> >> Rewrite the comments in the correct place, using 'fall through' >> which is recognized by GCC and static analyzers. >> >> Signed-off-by: Philippe Mathieu-Daud=C3=A9 >> --- >> Cc: Peter Chubb >> Cc: Peter Maydell >> Cc: Jason Wang >> Cc: qemu-arm@nongnu.org >> --- >> hw/net/imx_fec.c | 8 +++++--- >> 1 file changed, 5 insertions(+), 3 deletions(-) >> >> diff --git a/hw/net/imx_fec.c b/hw/net/imx_fec.c >> index bd99236864..30cc07753d 100644 >> --- a/hw/net/imx_fec.c >> +++ b/hw/net/imx_fec.c >> @@ -901,15 +901,17 @@ static void imx_eth_write(void *opaque, hwaddr off= set, uint64_t value, >> s->regs[index] =3D 0; >> } >> break; >> - case ENET_TDAR1: /* FALLTHROUGH */ >> - case ENET_TDAR2: /* FALLTHROUGH */ >> + /* fall through */ >=20 > Wrong location. And I think you don't need any comment here at all, GCC > should stay silent without it? >=20 >> + case ENET_TDAR1: >> + case ENET_TDAR2: >> if (unlikely(single_tx_ring)) { >> qemu_log_mask(LOG_GUEST_ERROR, >> "[%s]%s: trying to access TDAR2 or TDAR1\n", >> TYPE_IMX_FEC, __func__); >> return; >> } >> - case ENET_TDAR: /* FALLTHROUGH */ >> + /* fall through */ >=20 > I'd suggest to simply remove it, too. /me needsmorecoffee ... of course this hunk was fine. Good that you kept it in v2. Thomas >> + case ENET_TDAR: >> if (s->regs[ENET_ECR] & ENET_ECR_ETHEREN) { >> s->regs[index] =3D ENET_TDAR_TDAR; >> imx_eth_do_tx(s, index); >> >=20 > Thomas >=20 From MAILER-DAEMON Wed Dec 18 14:36:39 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1ihf7f-00027g-4R for mharc-qemu-arm@gnu.org; Wed, 18 Dec 2019 14:36:39 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:43415) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ihf7c-00021q-DT for qemu-arm@nongnu.org; Wed, 18 Dec 2019 14:36:37 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ihf7b-0006g6-88 for qemu-arm@nongnu.org; Wed, 18 Dec 2019 14:36:36 -0500 Received: from us-smtp-delivery-1.mimecast.com ([207.211.31.120]:56484 helo=us-smtp-1.mimecast.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1ihf7a-0006cL-Vu for qemu-arm@nongnu.org; Wed, 18 Dec 2019 14:36:35 -0500 DKIM-Signature: v=1; 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Wed, 18 Dec 2019 19:36:27 +0000 (UTC) Received: from thuth.remote.csb (ovpn-116-120.ams2.redhat.com [10.36.116.120]) by smtp.corp.redhat.com (Postfix) with ESMTPS id 5D5A219C58; Wed, 18 Dec 2019 19:36:21 +0000 (UTC) Subject: Re: [PATCH v2 4/6] hw/net/imx_fec: Rewrite fall through comments To: =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= , qemu-devel@nongnu.org Cc: Peter Maydell , Jason Wang , Richard Henderson , qemu-arm@nongnu.org, Peter Chubb , Aleksandar Markovic References: <20191218192526.13845-1-philmd@redhat.com> <20191218192526.13845-5-philmd@redhat.com> From: Thomas Huth Openpgp: preference=signencrypt Message-ID: <4586faa9-31ed-d90c-730c-f6c32657dceb@redhat.com> Date: Wed, 18 Dec 2019 20:36:19 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101 Thunderbird/60.9.0 MIME-Version: 1.0 In-Reply-To: <20191218192526.13845-5-philmd@redhat.com> Content-Language: en-US X-Scanned-By: MIMEDefang 2.84 on 10.5.11.23 X-MC-Unique: z8cuo0vYOviCYyfeKs03mw-1 X-Mimecast-Spam-Score: 0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 207.211.31.120 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 18 Dec 2019 19:36:38 -0000 On 18/12/2019 20.25, Philippe Mathieu-Daud=C3=A9 wrote: > GCC9 is confused by this comment when building with CFLAG > -Wimplicit-fallthrough=3D2: >=20 > hw/net/imx_fec.c: In function =E2=80=98imx_eth_write=E2=80=99: > hw/net/imx_fec.c:906:12: error: this statement may fall through [-Werro= r=3Dimplicit-fallthrough=3D] > 906 | if (unlikely(single_tx_ring)) { > | ^ > hw/net/imx_fec.c:912:5: note: here > 912 | case ENET_TDAR: /* FALLTHROUGH */ > | ^~~~ > cc1: all warnings being treated as errors >=20 > Rewrite the comments in the correct place, using 'fall through' > which is recognized by GCC and static analyzers. >=20 > Reviewed-by: Richard Henderson > Reviewed-by: Aleksandar Markovic > Signed-off-by: Philippe Mathieu-Daud=C3=A9 > --- > Cc: Peter Chubb > Cc: Peter Maydell > Cc: Jason Wang > Cc: qemu-arm@nongnu.org > --- > hw/net/imx_fec.c | 3 ++- > 1 file changed, 2 insertions(+), 1 deletion(-) >=20 > diff --git a/hw/net/imx_fec.c b/hw/net/imx_fec.c > index bd99236864..c01ce4f078 100644 > --- a/hw/net/imx_fec.c > +++ b/hw/net/imx_fec.c > @@ -909,7 +909,8 @@ static void imx_eth_write(void *opaque, hwaddr offset= , uint64_t value, > TYPE_IMX_FEC, __func__); > return; > } > - case ENET_TDAR: /* FALLTHROUGH */ > + /* fall through */ > + case ENET_TDAR: > if (s->regs[ENET_ECR] & ENET_ECR_ETHEREN) { > s->regs[index] =3D ENET_TDAR_TDAR; > imx_eth_do_tx(s, index); >=20 Reviewed-by: Thomas Huth From MAILER-DAEMON Wed Dec 18 14:36:49 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1ihf7o-0002Jv-5G for mharc-qemu-arm@gnu.org; Wed, 18 Dec 2019 14:36:48 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:44791) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ihf7k-0002Eu-3Z for qemu-arm@nongnu.org; Wed, 18 Dec 2019 14:36:45 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ihf7i-0007Eq-PK for qemu-arm@nongnu.org; Wed, 18 Dec 2019 14:36:43 -0500 Received: from mail-pl1-x641.google.com ([2607:f8b0:4864:20::641]:37404) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ihf7i-00079G-A5 for qemu-arm@nongnu.org; Wed, 18 Dec 2019 14:36:42 -0500 Received: by mail-pl1-x641.google.com with SMTP id c23so1430680plz.4 for ; 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([2605:e000:c74f:dc00:6838:d2b2:17e2:8445]) by smtp.gmail.com with ESMTPSA id z13sm3893825pjz.15.2019.12.18.11.36.39 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 18 Dec 2019 11:36:40 -0800 (PST) Subject: Re: [PATCH v1 1/4] target/arm: remove unused EXCP_SEMIHOST leg To: =?UTF-8?Q?Alex_Benn=c3=a9e?= , qemu-devel@nongnu.org Cc: pbonzini@redhat.com, keithp@keithp.com, "open list:ARM TCG CPUs" , Peter Maydell References: <20191218180029.6744-1-alex.bennee@linaro.org> <20191218180029.6744-2-alex.bennee@linaro.org> From: Richard Henderson Message-ID: <23ab51e5-12fc-fa62-b8ca-942089bd7bec@linaro.org> Date: Wed, 18 Dec 2019 09:36:37 -1000 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.2.2 MIME-Version: 1.0 In-Reply-To: <20191218180029.6744-2-alex.bennee@linaro.org> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 8bit X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::641 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 18 Dec 2019 19:36:45 -0000 On 12/18/19 8:00 AM, Alex Bennée wrote: > All semihosting exceptions are dealt with earlier in the common code > so we should never get here. > > Signed-off-by: Alex Bennée > --- > target/arm/helper.c | 6 ------ > 1 file changed, 6 deletions(-) Reviewed-by: Richard Henderson r~ From MAILER-DAEMON Wed Dec 18 14:45:25 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1ihfG9-0000gr-8W for mharc-qemu-arm@gnu.org; Wed, 18 Dec 2019 14:45:25 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:37041) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ihfG7-0000en-0O for qemu-arm@nongnu.org; Wed, 18 Dec 2019 14:45:24 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ihfG5-0003jW-KA for qemu-arm@nongnu.org; Wed, 18 Dec 2019 14:45:22 -0500 Received: from mail-pg1-x543.google.com ([2607:f8b0:4864:20::543]:36687) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ihfG5-0003fS-90 for qemu-arm@nongnu.org; Wed, 18 Dec 2019 14:45:21 -0500 Received: by mail-pg1-x543.google.com with SMTP id k3so1818683pgc.3 for ; Wed, 18 Dec 2019 11:45:21 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=subject:to:cc:references:from:message-id:date:user-agent :mime-version:in-reply-to:content-language:content-transfer-encoding; bh=5yWhXSDHqZ6Ptt+fDE9oY+B4VtUt/ihK9EgFsH/5ncQ=; b=kTfqO40hjB86KvVFg8zQOwVp8sikOfTL8G2qFFhxggD2IQlKeyOAh0kV9VrI4OavMl r3kuVsAoY9IjxYRX6m6cPgj24bbRGXfUgL1pdY1jtKWSdn3vSAw5r9ZEjejQ9xrvtF+3 Z/leHGxeWi0xIub3aexwz7404CYR/npQ4tKDoj9nNHD5lmC5/K1k2sEkdqA5GRLGz4L2 Zg1qE3vFCrjm7Bq9zBAOM/Q0KuwS4CRPrzbWJhLxOy1zp1YcdiyjIuQpXVi8SlBXOPcM hbRLeXP9f14lhnyBiH7XXWLdsqOkz519mNOWejdjKFmheYzAiyq0B8VuGZbJjDDSwfX4 gVpA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:subject:to:cc:references:from:message-id:date :user-agent:mime-version:in-reply-to:content-language :content-transfer-encoding; bh=5yWhXSDHqZ6Ptt+fDE9oY+B4VtUt/ihK9EgFsH/5ncQ=; b=GQ2tXyethwsVadHFKPUP1F2a2HkEljC/JykSmTF2RRGMTZqQdqhguUDb9wRa6sRUQo 51qtlsaCIM9YO4Zfz4CI1stMXhiLTquplku4jjfG3tOvk4n7U4PG7EKTFP7FRAUNa3En R6x0tdBHnVmdnzyuOAt3p+IGsbC/FhmPGNjkmnelClvgpGNCseruNzOdsCe7oRSPhFfR 23J7d9yVtnlu8XoPgMf+MPt0qw3VdEzWxb7wetwlcgyyvxJ5xKzncJsgD3Z3UyuxpcSf u4rS8ENO8JQnvT0OZpkW4rl8ZhiCOiuXY2L2sTGbdnkbeRqgfRcdudUe29MhAvAh7EY+ mDBQ== X-Gm-Message-State: APjAAAXXaRuj2BVHZ964w6/HKvKrzXlwtywZXrMs+49y4GKALIAreJaO WIinMECGNEfjWiOI+2lYO0v38w== X-Google-Smtp-Source: APXvYqxxlXTfq6IhZoBP10LCI+WbXwmAPsUr/eltnFJomiXaiCRM4tan07WAGjJVkhIFuqxGKE3WkA== X-Received: by 2002:a63:e14b:: with SMTP id h11mr4693189pgk.297.1576698319987; Wed, 18 Dec 2019 11:45:19 -0800 (PST) Received: from ?IPv6:2605:e000:c74f:dc00:6838:d2b2:17e2:8445? ([2605:e000:c74f:dc00:6838:d2b2:17e2:8445]) by smtp.gmail.com with ESMTPSA id h26sm4665845pfr.9.2019.12.18.11.45.18 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 18 Dec 2019 11:45:19 -0800 (PST) Subject: Re: [PATCH v1 2/4] target/arm: only update pc after semihosting completes To: =?UTF-8?Q?Alex_Benn=c3=a9e?= , qemu-devel@nongnu.org Cc: Peter Maydell , keithp@keithp.com, Riku Voipio , Laurent Vivier , "open list:ARM TCG CPUs" , pbonzini@redhat.com References: <20191218180029.6744-1-alex.bennee@linaro.org> <20191218180029.6744-3-alex.bennee@linaro.org> From: Richard Henderson Message-ID: <975db858-8470-d2dd-de53-278423984e46@linaro.org> Date: Wed, 18 Dec 2019 09:45:15 -1000 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.2.2 MIME-Version: 1.0 In-Reply-To: <20191218180029.6744-3-alex.bennee@linaro.org> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 8bit X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::543 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 18 Dec 2019 19:45:24 -0000 On 12/18/19 8:00 AM, Alex Bennée wrote: > Before we introduce blocking semihosting calls we need to ensure we > can restart the system on semi hosting exception. To be able to do > this the EXCP_SEMIHOST operation should be idempotent until it finally > completes. Practically this means ensureing we only update the pc ensuring. > after the semihosting call has completed. > > Signed-off-by: Alex Bennée > --- > linux-user/aarch64/cpu_loop.c | 1 + > linux-user/arm/cpu_loop.c | 1 + > target/arm/helper.c | 2 ++ > target/arm/m_helper.c | 1 + > target/arm/translate-a64.c | 2 +- > target/arm/translate.c | 6 +++--- > 6 files changed, 9 insertions(+), 4 deletions(-) ... > +++ b/target/arm/m_helper.c > @@ -2185,6 +2185,7 @@ void arm_v7m_cpu_do_interrupt(CPUState *cs) > "...handling as semihosting call 0x%x\n", > env->regs[0]); > env->regs[0] = do_arm_semihosting(env); > + env->regs[15] += env->thumb ? 2 : 4; ... although thumb should never be false here, it does match the other instances. I do wonder if it's worth inventing do_arm{32,64}_semihosting wrappers that consolidate this register manipulation. But either way, Reviewed-by: Richard Henderson r~ From MAILER-DAEMON Wed Dec 18 15:14:32 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1ihfiK-0000WE-J6 for mharc-qemu-arm@gnu.org; Wed, 18 Dec 2019 15:14:32 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:55994) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ihfiF-0000MY-Kg for qemu-arm@nongnu.org; Wed, 18 Dec 2019 15:14:31 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ihfiC-0004XL-3k for qemu-arm@nongnu.org; Wed, 18 Dec 2019 15:14:27 -0500 Received: from mail-io1-xd2b.google.com ([2607:f8b0:4864:20::d2b]:41986) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ihfi3-0003p8-D6; Wed, 18 Dec 2019 15:14:15 -0500 Received: by mail-io1-xd2b.google.com with SMTP id n11so1799723iom.9; Wed, 18 Dec 2019 12:14:14 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=K/OdqGuEDKTr2+zKYT0b1sCPvCwUANs/aupGGTK6asA=; b=Vy1AoD6i8DA/NQHmL1R+TTJgY+d7lm+tnFSzomlnnOXp70o0ODkFoXrayAcgLXyEV5 VuAUjVQgCrHtoZFN/bbmTM1+mONePE9Bc2kk4ESSAiIgQz41r9EdQUBo2JSXgLjs6ZNn a1xYAzbhf5YVkqUpvTrfXIKOwLJOj1Dl+wr0PfbKFSPH5o2we/qsfu2+TzVbLZDgl/x+ a80rjh8sh4Uq5cD9THC1aOZTx4oyTXkFS2iKgdhCzzpprX6Wp1AFP12W6tua8J3dAJGb CHSYxm68Qz+FqubNd1dvT/Om5J8f1p4H/hCgbe5+DT6nDxHiUvIlFydqWxGdkBemRSTW t2Gw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=K/OdqGuEDKTr2+zKYT0b1sCPvCwUANs/aupGGTK6asA=; b=s6AHXc+kybQXqXTzAMQcG0hEQRLodS0CdwsxR4qkWMIJESkHO46ROdGqR+VRPeOvT7 ZUWjiL+/t/WXb+VMuPdSf5mDrtKStz7dVM3U08h7k6qnFdLBEpF3xS78wU19I2FXkHXB yVSfQb8I+H9mVHyEsFrCia0zrGni461WUN5RRB+nDeAYKK2pIufOrqSImFt2483MrEmt ZfXYz5Ax/ZZJlWATN2RAkv5wbrc/WnZ/SYO0BpxBzSQAAqslvzhqHpCMgPZE6kJ0jOqG P8YcGp/uhu8D/H8DYBPxJltyYwdb7isbtDLE5Xw0IMM9J2Tikgu9y2+CXY2vNtVlaBtl eYtQ== X-Gm-Message-State: APjAAAXm7KH2oPGXggMRlIoXjE8tn5wsW3+3O2Me776/CwD46+weN9ow YWZgZiwUPuQs5NNDWL6Q95CBs66yKsmRNraahKg= X-Google-Smtp-Source: APXvYqzihjYbHBQosCEt1vDQGVC9X4rhg7CZAqISQwk/pRqflDvpcA9AOcVgXxoP966OE8cuRPQHWepO1GvcRLDWKhc= X-Received: by 2002:a6b:d912:: with SMTP id r18mr3003884ioc.306.1576700053798; Wed, 18 Dec 2019 12:14:13 -0800 (PST) MIME-Version: 1.0 References: <20191216233519.29030-1-nieklinnenbank@gmail.com> <20191216233519.29030-3-nieklinnenbank@gmail.com> In-Reply-To: From: Niek Linnenbank Date: Wed, 18 Dec 2019 21:14:02 +0100 Message-ID: Subject: Re: [PATCH v2 02/10] hw: arm: add Xunlong Orange Pi PC machine To: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= Cc: QEMU Developers , qemu-arm , Peter Maydell Content-Type: multipart/alternative; boundary="0000000000009fcf3d059a00167c" X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::d2b X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 18 Dec 2019 20:14:31 -0000 --0000000000009fcf3d059a00167c Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Hi Philippe, Thanks again for your quick and helpful feedback! :-) On Tue, Dec 17, 2019 at 8:31 AM Philippe Mathieu-Daud=C3=A9 wrote: > Hi Niek, > > On 12/17/19 12:35 AM, Niek Linnenbank wrote: > > The Xunlong Orange Pi PC is an Allwinner H3 System on Chip > > based embedded computer with mainline support in both U-Boot > > and Linux. The board comes with a Quad Core Cortex A7 @ 1.3GHz, > > 512MB RAM, 100Mbit ethernet, USB, SD/MMC, USB, HDMI and > > various other I/O. This commit add support for the Xunlong > > Orange Pi PC machine. > > > > Signed-off-by: Niek Linnenbank > > Tested-by: KONRAD Frederic > > --- > > hw/arm/orangepi.c | 101 ++++++++++++++++++++++++++++++++++++++++++= + > > MAINTAINERS | 1 + > > hw/arm/Makefile.objs | 2 +- > > 3 files changed, 103 insertions(+), 1 deletion(-) > > create mode 100644 hw/arm/orangepi.c > > > > diff --git a/hw/arm/orangepi.c b/hw/arm/orangepi.c > > new file mode 100644 > > index 0000000000..62cefc8c06 > > --- /dev/null > > +++ b/hw/arm/orangepi.c > > @@ -0,0 +1,101 @@ > > +/* > > + * Orange Pi emulation > > + * > > + * Copyright (C) 2019 Niek Linnenbank > > + * > > + * This program is free software: you can redistribute it and/or modif= y > > + * it under the terms of the GNU General Public License as published b= y > > + * the Free Software Foundation, either version 2 of the License, or > > + * (at your option) any later version. > > + * > > + * This program is distributed in the hope that it will be useful, > > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > > + * GNU General Public License for more details. > > + * > > + * You should have received a copy of the GNU General Public License > > + * along with this program. If not, see >. > > + */ > > + > > +#include "qemu/osdep.h" > > +#include "exec/address-spaces.h" > > +#include "qapi/error.h" > > +#include "cpu.h" > > +#include "hw/sysbus.h" > > +#include "hw/boards.h" > > +#include "hw/qdev-properties.h" > > +#include "hw/arm/allwinner-h3.h" > > + > > +static struct arm_boot_info orangepi_binfo =3D { > > + .board_id =3D -1, > > +}; > > + > > +typedef struct OrangePiState { > > + AwH3State *h3; > > + MemoryRegion sdram; > > +} OrangePiState; > > + > > +static void orangepi_init(MachineState *machine) > > +{ > > + OrangePiState *s =3D g_new(OrangePiState, 1); > > + > > + /* Only allow Cortex-A7 for this board */ > > + if (strcmp(machine->cpu_type, ARM_CPU_TYPE_NAME("cortex-a7")) !=3D= 0) > { > > + error_report("This board can only be used with cortex-a7 CPU")= ; > > + exit(1); > > + } > > + > > + s->h3 =3D AW_H3(object_new(TYPE_AW_H3)); > > + > > + /* Setup timer properties */ > > + object_property_set_int(OBJECT(&s->h3->timer), 32768, "clk0-freq", > > + &error_abort); > > You access the timer object which is contained inside the soc object, > but the soc isn't realized yet... I wonder if this is OK. Usually what > we do is, either: > - add a 'xtal-freq-hz' property to the SoC, set it here in the board, > then in soc::realize() set the property to the timer > - add an alias in the SoC to the timer 'freq-hz' property: > object_property_add_alias(soc, "xtal-freq-hz", OBJECT(&s->timer), > "freq-hz", &error_abort); > Good point. I shall rework that part using your suggestion. Actually, I copied the timer support code from the existing cubieboard.c that has the Allwinner A10, so potentially the same problem is there. While looking more closer at this part, I now also discovered that the timer module from the Allwinner H3 is mostly a stripped down version of the timer module in the Allwinner A10: Allwinner A10, 10.2 Timer Register List, page 85: https://linux-sunxi.org/images/1/1e/Allwinner_A10_User_manual_V1.5.pdf The A10 version has six timers, where the H3 has only two. That should be fine I would say, the guest would simply use those available on H3 and ignore the rest. There is however one conflicting difference: the WDOG0 registers in the Allwinner H3 start at a different offset and are also different. The current A10 timer does not currently implement the watchdog part. The watchdog part of this timer is relevant for the 'reset' command in U-Boot: that does not work right now, because U-Boot implements the reset for the Allwinner H3 boards by letting this watchdog expire (and we dont emulate it). Also, this timer module is required for booting Linux, without it the kernel crashes using the sunxi_defconfig: [ 0.000000] PC is at sun4i_timer_init+0x34/0x168 [ 0.000000] LR is at sun4i_timer_init+0x2c/0x168 [ 0.000000] pc : [] lr : [] psr: 600000d3 [ 0.000000] sp : c0a03f70 ip : eec00188 fp : ef7ed040 ... [ 0.000000] [] (sun4i_timer_init) from [] (timer_probe+0x74/0xe4) [ 0.000000] [] (timer_probe) from [] (start_kernel+0x2e0/0x440) [ 0.000000] [] (start_kernel) from [<00000000>] (0x0) So in my opinion its a bit of a trade off here: we can keep it like this and re-use the A10 timer for now, and perhaps attempt to generalize that module for proper use in both SoCs. Or we can introduce a new H3 specific timer module. What do you think? > > Also, if you use &error_abort, a failure in object_property_set_int() > triggers abort(). See "qapi/error.h": > > * If @errp is &error_abort, print a suitable message and abort(). > * If @errp is &error_fatal, print a suitable message and exit(1). > > > + if (error_abort !=3D NULL) { > > + error_reportf_err(error_abort, "Couldn't set clk0 frequency: "= ); > > + exit(1); > > + } > > So this if() block is useless. > > Ah ok, I'll remove them. > > + > > + object_property_set_int(OBJECT(&s->h3->timer), 24000000, > "clk1-freq", > > + &error_abort); > > + if (error_abort !=3D NULL) { > > + error_reportf_err(error_abort, "Couldn't set clk1 frequency: "= ); > > + exit(1); > > + } > > Similarly, remove if() block. > > > + > > + /* Mark H3 object realized */ > > + object_property_set_bool(OBJECT(s->h3), true, "realized", > &error_abort); > > + if (error_abort !=3D NULL) { > > + error_reportf_err(error_abort, "Couldn't realize Allwinner H3: > "); > > + exit(1); > > + } > > Similarly, remove if() block. > > > + > > + /* RAM */ > > + if (machine->ram_size > 1 * GiB) { > > + error_report("Requested ram size is too large for this machine= : > " > > + "maximum is 1GB"); > > Per http://www.orangepi.org/orangepipc/ this board comes with a specific > amount of RAM. I'd enforce the default (1GiB) and refuse other cases. > OK sure, I'll change it to a enforcing 1GiB. I do recall we briefly discussed this in v1. Then we agreed to make it an upper limit for use cases where resources are limited which is why I changed it like this. > I noticed this by testing your series, without specifying the memory > size you suggested in the cover (512) it defaults to 128 MiB, and the > Raspian userland fails: > Indeed! By the way, this is also the case for U-Boot: it freezes when using 128MiB. Actually when working on the initial code I searched a bit for a way to set a default ram size, but could not find it at that time. But now I see in your comment below, it can be done simply with mc->default_ram_size. Thanks a lot, I will surely add that! > > [ *** ] (2 of 4) A start job is running for=E2=80=A6Persistent Storage (= 37s / > 2min 1s) > [ *** ] (2 of 4) A start job is running for=E2=80=A6Persistent Storage (= 38s / > 2min 1s) > [ OK ] Started Flush Journal to Persistent Storage. > Starting Create Volatile Files and Directories... > Starting Armbian ZRAM config... > [ **] (3 of 6) A start job is running for=E2=80=A6s and Directories (5= 5s / no > limit) > [ *] (3 of 6) A start job is running for=E2=80=A6s and Directories (5= 5s / no > limit) > [ **] (3 of 6) A start job is running for=E2=80=A6s and Directories (5= 6s / no > limit) > [ OK ] Started Create Volatile Files and Directories. > [*** ] (5 of 6) A start job is running for=E2=80=A6 ZRAM config (1min 1= 0s / > 1min 19s) > [** ] (5 of 6) A start job is running for=E2=80=A6 ZRAM config (1min 1= 2s / > 1min 19s) > [* ] (5 of 6) A start job is running for=E2=80=A6 ZRAM config (1min 1= 3s / > 1min 19s) > [FAILED] Failed to start Armbian ZRAM config. > See 'systemctl status armbian-zram-config.service' for details. > > > + exit(1); > > + } > > + memory_region_allocate_system_memory(&s->sdram, NULL, > "orangepi.ram", > > There is only one type of ram on this machine, I'd simply name this > "sdram". > OK! > > + machine->ram_size); > > + memory_region_add_subregion(get_system_memory(), > s->h3->memmap[AW_H3_SDRAM], > > + &s->sdram); > > + > > + /* Load target kernel */ > > + orangepi_binfo.loader_start =3D s->h3->memmap[AW_H3_SDRAM]; > > + orangepi_binfo.ram_size =3D machine->ram_size; > > + orangepi_binfo.nb_cpus =3D AW_H3_NUM_CPUS; > > + arm_load_kernel(ARM_CPU(first_cpu), machine, &orangepi_binfo); > > I wonder if we should tell the user '-bios' is not supported on this > machine. > Good suggestion, its not handled, at least not anywhere in the code I added for H3 support. Shall I make it an error_report followed by exit(1), similar to the 1GiB check? > > > +} > > + > > +static void orangepi_machine_init(MachineClass *mc) > > +{ > > + mc->desc =3D "Orange Pi PC"; > > + mc->init =3D orangepi_init; > > + mc->units_per_default_bus =3D 1; > > Maybe "units_per_default_bus =3D 1" belongs to patch 9 "add SD/MMC host > controller". > True, it should be in patch 9 indeed. I overlooked this when separating the work in individual patches. Now I am also wondering if I actually need this setting. Without it, the SD device still works fine. I did some greps in the code to discover what it is used for, but its not very clear to me yet. Is this ment to restrict machines to only one harddisk (or SD card)? If I try to supply multiple SD cards with multiple -sd arguments, this error is printed, regardless of having units_per_default_bus=3D1 or no= t: qemu-system-arm: -sd test3.ext2: machine type does not support if=3Dsd,bus=3D1,unit=3D0 > > > + mc->min_cpus =3D AW_H3_NUM_CPUS; > > + mc->max_cpus =3D AW_H3_NUM_CPUS; > > + mc->default_cpus =3D AW_H3_NUM_CPUS; > > + mc->default_cpu_type =3D ARM_CPU_TYPE_NAME("cortex-a7"); > > Please add: > > mc->default_ram_size =3D 1 * GiB; > Yes, thanks! > > > +} > > + > > +DEFINE_MACHINE("orangepi-pc", orangepi_machine_init) > > diff --git a/MAINTAINERS b/MAINTAINERS > > index aae1a049b4..db682e49ca 100644 > > --- a/MAINTAINERS > > +++ b/MAINTAINERS > > @@ -486,6 +486,7 @@ L: qemu-arm@nongnu.org > > S: Maintained > > F: hw/*/allwinner-h3* > > F: include/hw/*/allwinner-h3* > > +F: hw/arm/orangepi.c > > > > ARM PrimeCell and CMSDK devices > > M: Peter Maydell > > diff --git a/hw/arm/Makefile.objs b/hw/arm/Makefile.objs > > index 956e496052..8d5ea453d5 100644 > > --- a/hw/arm/Makefile.objs > > +++ b/hw/arm/Makefile.objs > > @@ -34,7 +34,7 @@ obj-$(CONFIG_DIGIC) +=3D digic.o > > obj-$(CONFIG_OMAP) +=3D omap1.o omap2.o > > obj-$(CONFIG_STRONGARM) +=3D strongarm.o > > obj-$(CONFIG_ALLWINNER_A10) +=3D allwinner-a10.o cubieboard.o > > -obj-$(CONFIG_ALLWINNER_H3) +=3D allwinner-h3.o > > +obj-$(CONFIG_ALLWINNER_H3) +=3D allwinner-h3.o orangepi.o > > obj-$(CONFIG_RASPI) +=3D bcm2835_peripherals.o bcm2836.o raspi.o > > obj-$(CONFIG_STM32F205_SOC) +=3D stm32f205_soc.o > > obj-$(CONFIG_XLNX_ZYNQMP_ARM) +=3D xlnx-zynqmp.o xlnx-zcu102.o > > > > Regards, Niek --=20 Niek Linnenbank --0000000000009fcf3d059a00167c Content-Type: text/html; charset="UTF-8" Content-Transfer-Encoding: quoted-printable
Hi Philippe,

Thanks again for your quick and helpful feedback! :-)

On Tue= , Dec 17, 2019 at 8:31 AM Philippe Mathieu-Daud=C3=A9 <philmd@redhat.com> wrote:
Hi Niek,

On 12/17/19 12:35 AM, Niek Linnenbank wrote:
> The Xunlong Orange Pi PC is an Allwinner H3 System on Chip
> based embedded computer with mainline support in both U-Boot
> and Linux. The board comes with a Quad Core Cortex A7 @ 1.3GHz,
> 512MB RAM, 100Mbit ethernet, USB, SD/MMC, USB, HDMI and
> various other I/O. This commit add support for the Xunlong
> Orange Pi PC machine.
>
> Signed-off-by: Niek Linnenbank <nieklinnenbank@gmail.com>
> Tested-by: KONRAD Frederic <frederic.konrad@adacore.com>
> ---
>=C2=A0 =C2=A0hw/arm/orangepi.c=C2=A0 =C2=A0 | 101 +++++++++++++++++++++= ++++++++++++++++++++++
>=C2=A0 =C2=A0MAINTAINERS=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 |=C2=A0 =C2= =A01 +
>=C2=A0 =C2=A0hw/arm/Makefile.objs |=C2=A0 =C2=A02 +-
>=C2=A0 =C2=A03 files changed, 103 insertions(+), 1 deletion(-)
>=C2=A0 =C2=A0create mode 100644 hw/arm/orangepi.c
>
> diff --git a/hw/arm/orangepi.c b/hw/arm/orangepi.c
> new file mode 100644
> index 0000000000..62cefc8c06
> --- /dev/null
> +++ b/hw/arm/orangepi.c
> @@ -0,0 +1,101 @@
> +/*
> + * Orange Pi emulation
> + *
> + * Copyright (C) 2019 Niek Linnenbank <nieklinnenbank@gmail.com>
> + *
> + * This program is free software: you can redistribute it and/or modi= fy
> + * it under the terms of the GNU General Public License as published = by
> + * the Free Software Foundation, either version 2 of the License, or<= br> > + * (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful, > + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.=C2=A0 See the=
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License<= br> > + * along with this program.=C2=A0 If not, see <http://www.gnu.o= rg/licenses/>.
> + */
> +
> +#include "qemu/osdep.h"
> +#include "exec/address-spaces.h"
> +#include "qapi/error.h"
> +#include "cpu.h"
> +#include "hw/sysbus.h"
> +#include "hw/boards.h"
> +#include "hw/qdev-properties.h"
> +#include "hw/arm/allwinner-h3.h"
> +
> +static struct arm_boot_info orangepi_binfo =3D {
> +=C2=A0 =C2=A0 .board_id =3D -1,
> +};
> +
> +typedef struct OrangePiState {
> +=C2=A0 =C2=A0 AwH3State *h3;
> +=C2=A0 =C2=A0 MemoryRegion sdram;
> +} OrangePiState;
> +
> +static void orangepi_init(MachineState *machine)
> +{
> +=C2=A0 =C2=A0 OrangePiState *s =3D g_new(OrangePiState, 1);
> +
> +=C2=A0 =C2=A0 /* Only allow Cortex-A7 for this board */
> +=C2=A0 =C2=A0 if (strcmp(machine->cpu_type, ARM_CPU_TYPE_NAME(&quo= t;cortex-a7")) !=3D 0) {
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 error_report("This board can only be= used with cortex-a7 CPU");
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 exit(1);
> +=C2=A0 =C2=A0 }
> +
> +=C2=A0 =C2=A0 s->h3 =3D AW_H3(object_new(TYPE_AW_H3));
> +
> +=C2=A0 =C2=A0 /* Setup timer properties */
> +=C2=A0 =C2=A0 object_property_set_int(OBJECT(&s->h3->timer)= , 32768, "clk0-freq",
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0 =C2=A0 =C2=A0 &error_abort);

You access the timer object which is contained inside the soc object,
but the soc isn't realized yet... I wonder if this is OK. Usually what =
we do is, either:
- add a 'xtal-freq-hz' property to the SoC, set it here in the boar= d,
then in soc::realize() set the property to the timer
- add an alias in the SoC to the timer 'freq-hz' property:
=C2=A0 =C2=A0 =C2=A0object_property_add_alias(soc, "xtal-freq-hz"= , OBJECT(&s->timer),
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 "freq-hz", &= amp;error_abort);
Good point. I shall rework that part= using your suggestion.
Actually, I copied the timer support code= from the existing cubieboard.c that has
the Allwinner A10, so po= tentially the same problem is there.

While loo= king more closer at this part, I now also discovered that the timer module = from the Allwinner H3 is
mostly a stripped down version of the ti= mer module in the Allwinner A10:

=C2=A0 Allwi= nner A10, 10.2 Timer Register List, page 85:

The A10 version has six timers, where the = H3 has only two. That should be fine I would say, the guest would simply
use those available on H3 and ignore the rest. There is however one= conflicting difference: the WDOG0 registers in the Allwinner H3 start
at a different offset and are also different. The current A10 timer d= oes not currently implement the watchdog part.

The= watchdog part of this timer is relevant for the 'reset' command in= U-Boot: that does not work right now, because
U-Boot implements = the reset for the Allwinner H3 boards by letting this watchdog expire (and = we dont emulate it).
Also, this timer module is required for boot= ing Linux, without it the kernel crashes using the sunxi_defconfig:

[    0.000000] PC is at sun4i_timer_init+0x34/0x168
[    0.000000] LR is at sun4i_timer_init+0x2c/0x168
[    0.000000] pc : [<c07fa634>]    lr : [<c07fa62c>]    psr: 6=
00000d3
[    0.000000] sp : c0a03f70  ip : eec00188  fp : ef7ed040
...
[ 0= .000000] [<c07fa634>] (sun4i_timer_init) from [<c07fa4e8>] (tim= er_probe+0x74/0xe4) [ 0.000000] [<c07fa4e8>] (timer_probe) from [<c07d9c10>] (st= art_kernel+0x2e0/0x440) [ 0.000000] [<c07d9c10>] (start_kernel) from [<00000000>] (0= x0)

So in my opinion its a bit of a trade off h= ere: we can keep it like this and re-use the A10 timer for now, and perhaps=
attempt to generalize that module for proper use in both SoCs. O= r we can introduce a new H3 specific timer module.
What do you th= ink?
=C2=A0

Also, if you use &error_abort, a failure in object_property_set_int() <= br> triggers abort(). See "qapi/error.h":

=C2=A0 * If @errp is &error_abort, print a suitable message and abort()= .
=C2=A0 * If @errp is &error_fatal, print a suitable message and exit(1)= .

> +=C2=A0 =C2=A0 if (error_abort !=3D NULL) {
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 error_reportf_err(error_abort, "Coul= dn't set clk0 frequency: ");
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 exit(1);
> +=C2=A0 =C2=A0 }

So this if() block is useless.

Ah ok, I'll remove them.
=C2=A0
> +
> +=C2=A0 =C2=A0 object_property_set_int(OBJECT(&s->h3->timer)= , 24000000, "clk1-freq",
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0 =C2=A0 =C2=A0 &error_abort);
> +=C2=A0 =C2=A0 if (error_abort !=3D NULL) {
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 error_reportf_err(error_abort, "Coul= dn't set clk1 frequency: ");
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 exit(1);
> +=C2=A0 =C2=A0 }

Similarly, remove if() block.

> +
> +=C2=A0 =C2=A0 /* Mark H3 object realized */
> +=C2=A0 =C2=A0 object_property_set_bool(OBJECT(s->h3), true, "= realized", &error_abort);
> +=C2=A0 =C2=A0 if (error_abort !=3D NULL) {
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 error_reportf_err(error_abort, "Coul= dn't realize Allwinner H3: ");
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 exit(1);
> +=C2=A0 =C2=A0 }

Similarly, remove if() block.

> +
> +=C2=A0 =C2=A0 /* RAM */
> +=C2=A0 =C2=A0 if (machine->ram_size > 1 * GiB) {
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 error_report("Requested ram size is = too large for this machine: "
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0"maximum is 1GB");

Per http://www.orangepi.org/orangepipc/ this board comes with= a specific
amount of RAM. I'd enforce the default (1GiB) and refuse other cases.

OK sure, I'll change it to a enforci= ng 1GiB. I do recall we briefly discussed this
in v1. Then we agr= eed to make it an upper limit for use cases where resources are
l= imited which is why I changed it like this.


I noticed this by testing your series, without specifying the memory
size you suggested in the cover (512) it defaults to 128 MiB, and the
Raspian userland fails:

Indeed! By the= way, this is also the case for U-Boot: it freezes when using 128MiB.
=
Actually when working on the initial code I searched a bit for a way
to set a default ram size, but could not find it at that time. But= now I see in your comment below,
it can be done simply with mc-&= gt;default_ram_size. Thanks a lot, I will surely add that!
= =C2=A0

[ ***=C2=A0 ] (2 of 4) A start job is running for=E2=80=A6Persistent Storag= e (37s /
2min 1s)
[=C2=A0 *** ] (2 of 4) A start job is running for=E2=80=A6Persistent Storag= e (38s /
2min 1s)
[=C2=A0 OK=C2=A0 ] Started Flush Journal to Persistent Storage.
Starting Create Volatile Files and Directories...
Starting Armbian ZRAM config...
[=C2=A0 =C2=A0 **] (3 of 6) A start job is running for=E2=80=A6s and Direct= ories (55s / no
limit)
[=C2=A0 =C2=A0 =C2=A0*] (3 of 6) A start job is running for=E2=80=A6s and D= irectories (55s / no
limit)
[=C2=A0 =C2=A0 **] (3 of 6) A start job is running for=E2=80=A6s and Direct= ories (56s / no
limit)
[=C2=A0 OK=C2=A0 ] Started Create Volatile Files and Directories.
[***=C2=A0 =C2=A0] (5 of 6) A start job is running for=E2=80=A6 ZRAM config= (1min 10s /
1min 19s)
[**=C2=A0 =C2=A0 ] (5 of 6) A start job is running for=E2=80=A6 ZRAM config= (1min 12s /
1min 19s)
[*=C2=A0 =C2=A0 =C2=A0] (5 of 6) A start job is running for=E2=80=A6 ZRAM c= onfig (1min 13s /
1min 19s)
[FAILED] Failed to start Armbian ZRAM config.
See 'systemctl status armbian-zram-config.service' for details.

> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 exit(1);
> +=C2=A0 =C2=A0 }
> +=C2=A0 =C2=A0 memory_region_allocate_system_memory(&s->sdram, = NULL, "orangepi.ram",

There is only one type of ram on this machine, I'd simply name this &qu= ot;sdram".

OK!


> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0machine->ram_size);
> +=C2=A0 =C2=A0 memory_region_add_subregion(get_system_memory(), s->= h3->memmap[AW_H3_SDRAM],
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 &s->sdram);
> +
> +=C2=A0 =C2=A0 /* Load target kernel */
> +=C2=A0 =C2=A0 orangepi_binfo.loader_start =3D s->h3->memmap[AW_= H3_SDRAM];
> +=C2=A0 =C2=A0 orangepi_binfo.ram_size =3D machine->ram_size;
> +=C2=A0 =C2=A0 orangepi_binfo.nb_cpus=C2=A0 =3D AW_H3_NUM_CPUS;
> +=C2=A0 =C2=A0 arm_load_kernel(ARM_CPU(first_cpu), machine, &orang= epi_binfo);

I wonder if we should tell the user '-bios' is not supported on thi= s
machine.

Good suggestion, its not handl= ed, at least not anywhere in the code I added for H3 support.
Sha= ll I make it an error_report followed by exit(1), similar to the 1GiB check= ?
=C2=A0

> +}
> +
> +static void orangepi_machine_init(MachineClass *mc)
> +{
> +=C2=A0 =C2=A0 mc->desc =3D "Orange Pi PC";
> +=C2=A0 =C2=A0 mc->init =3D orangepi_init;
> +=C2=A0 =C2=A0 mc->units_per_default_bus =3D 1;

Maybe "units_per_default_bus =3D 1" belongs to patch 9 "add = SD/MMC host
controller".
True, it should be in patch 9 indeed= . I overlooked this when separating the work in individual patches.
Now I am also wondering if I actually need this setting. Without it, the= SD device still works fine.
I did some greps in the code to disc= over what it is used for, but its not very clear to me yet. Is this ment to=
restrict machines to only one harddisk (or SD card)? If I try to= supply multiple SD cards with multiple -sd arguments,
this error= is printed, regardless of having units_per_default_bus=3D1 or not:
=C2=A0=C2=A0 qemu-system-arm: -sd = test3.ext2: machine type does not support if=3Dsd,bus=3D1,unit=3D0
=C2=A0

> +=C2=A0 =C2=A0 mc->min_cpus =3D AW_H3_NUM_CPUS;
> +=C2=A0 =C2=A0 mc->max_cpus =3D AW_H3_NUM_CPUS;
> +=C2=A0 =C2=A0 mc->default_cpus =3D AW_H3_NUM_CPUS;
> +=C2=A0 =C2=A0 mc->default_cpu_type =3D ARM_CPU_TYPE_NAME("cor= tex-a7");

Please add:

=C2=A0 =C2=A0 =C2=A0 =C2=A0 mc->default_ram_size =3D 1 * GiB;
Yes, thanks!
=C2=A0

> +}
> +
> +DEFINE_MACHINE("orangepi-pc", orangepi_machine_init)
> diff --git a/MAINTAINERS b/MAINTAINERS
> index aae1a049b4..db682e49ca 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -486,6 +486,7 @@ L: qemu-arm@nongnu.org
>=C2=A0 =C2=A0S: Maintained
>=C2=A0 =C2=A0F: hw/*/allwinner-h3*
>=C2=A0 =C2=A0F: include/hw/*/allwinner-h3*
> +F: hw/arm/orangepi.c
>=C2=A0 =C2=A0
>=C2=A0 =C2=A0ARM PrimeCell and CMSDK devices
>=C2=A0 =C2=A0M: Peter Maydell <peter.maydell@linaro.org>
> diff --git a/hw/arm/Makefile.objs b/hw/arm/Makefile.objs
> index 956e496052..8d5ea453d5 100644
> --- a/hw/arm/Makefile.objs
> +++ b/hw/arm/Makefile.objs
> @@ -34,7 +34,7 @@ obj-$(CONFIG_DIGIC) +=3D digic.o
>=C2=A0 =C2=A0obj-$(CONFIG_OMAP) +=3D omap1.o omap2.o
>=C2=A0 =C2=A0obj-$(CONFIG_STRONGARM) +=3D strongarm.o
>=C2=A0 =C2=A0obj-$(CONFIG_ALLWINNER_A10) +=3D allwinner-a10.o cubieboar= d.o
> -obj-$(CONFIG_ALLWINNER_H3) +=3D allwinner-h3.o
> +obj-$(CONFIG_ALLWINNER_H3) +=3D allwinner-h3.o orangepi.o
>=C2=A0 =C2=A0obj-$(CONFIG_RASPI) +=3D bcm2835_peripherals.o bcm2836.o r= aspi.o
>=C2=A0 =C2=A0obj-$(CONFIG_STM32F205_SOC) +=3D stm32f205_soc.o
>=C2=A0 =C2=A0obj-$(CONFIG_XLNX_ZYNQMP_ARM) +=3D xlnx-zynqmp.o xlnx-zcu1= 02.o
>


Regards,
Niek
--
Ni= ek Linnenbank

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([2605:e000:c74f:dc00:6838:d2b2:17e2:8445]) by smtp.gmail.com with ESMTPSA id r3sm4434114pfg.145.2019.12.18.12.16.34 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 18 Dec 2019 12:16:35 -0800 (PST) Subject: Re: [PATCH v1 3/4] semihosting: add qemu_semihosting_console_inc for SYS_READC To: =?UTF-8?Q?Alex_Benn=c3=a9e?= , qemu-devel@nongnu.org Cc: Peter Maydell , keithp@keithp.com, Riku Voipio , Laurent Vivier , "open list:ARM TCG CPUs" , pbonzini@redhat.com References: <20191218180029.6744-1-alex.bennee@linaro.org> <20191218180029.6744-4-alex.bennee@linaro.org> From: Richard Henderson Message-ID: <5ca1462e-5129-2b32-f014-a732a26a0587@linaro.org> Date: Wed, 18 Dec 2019 10:16:32 -1000 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.2.2 MIME-Version: 1.0 In-Reply-To: <20191218180029.6744-4-alex.bennee@linaro.org> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 8bit X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::444 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 18 Dec 2019 20:16:42 -0000 On 12/18/19 8:00 AM, Alex Bennée wrote: > From: Keith Packard > > Provides a blocking call to read a character from the console using > semihosting.chardev, if specified. This takes some careful command > line options to use stdio successfully as the serial ports, monitor > and semihost all want to use stdio. Here's a sample set of command > line options which share stdio betwen semihost, monitor and serial between. > +/** > + * qemu_semihosting_console_inc: > + * @env: CPUArchState > + * > + * Receive single character from debug console. This may be the remote > + * gdb session if a softmmu guest is currently being debugged. As this > + * call may block if no data is available we suspend the CPU and will > + * rexecute the instruction when data is there. Therefor two re-execute, Therefore > + * conditions must be met: > + * - CPUState is syncronised before callinging this function synchronized, calling > + * - pc is only updated once the character is succesfully returned successfully. > +static int console_can_read(void *opaque) > +{ > + SemihostingConsole *c = opaque; > + int ret; > + g_assert(qemu_mutex_iothread_locked()); > + ret = (int) fifo8_num_free(&c->fifo); > + return ret; > +} Boolean result; better as return fifo8_num_free(&c->fifo) > 0 (We could usefully change IOCanReadHandler to return bool to emphasize this.) > +static void console_wake_up(gpointer data, gpointer user_data) > +{ > + CPUState *cs = (CPUState *) data; > + /* cpu_handle_halt won't know we have work so just unbung here */ > + cs->halted = 0; > + qemu_cpu_kick(cs); > +} > + > +static void console_read(void *opaque, const uint8_t *buf, int size) > +{ > + SemihostingConsole *c = opaque; > + g_assert(qemu_mutex_iothread_locked()); > + while (size-- && !fifo8_is_full(&c->fifo)) { > + fifo8_push(&c->fifo, *buf++); > + } > + g_slist_foreach(c->sleeping_cpus, console_wake_up, NULL); > +} I think you should be clearing sleeping_cpus here, after they've all been kicked. > +target_ulong qemu_semihosting_console_inc(CPUArchState *env) > +{ > + uint8_t ch; > + SemihostingConsole *c = &console; > + g_assert(qemu_mutex_iothread_locked()); > + g_assert(current_cpu); > + if (fifo8_is_empty(&c->fifo)) { > + c->sleeping_cpus = g_slist_prepend(c->sleeping_cpus, current_cpu); > + current_cpu->halted = 1; > + current_cpu->exception_index = EXCP_HALTED; > + cpu_loop_exit(current_cpu); > + /* never returns */ > + } > + c->sleeping_cpus = g_slist_remove_all(c->sleeping_cpus, current_cpu); Which would mean you would not have to do this, because current_cpu is only on the list when it is halted. I presume all semihosting holds the BQL before we reach here, and we are not racing on this datastructure? > +target_ulong qemu_semihosting_console_inc(CPUArchState *env) > +{ > + uint8_t c; > + struct pollfd pollfd = { > + .fd = STDIN_FILENO, > + .events = POLLIN > + }; > + > + if (poll(&pollfd, 1, -1) != 1) { > + qemu_log_mask(LOG_UNIMP, "%s: unexpected read from stdin failure", > + __func__); > + return (target_ulong) -1; > + } Why are you polling stdin? linux-user isn't system mode, there isn't a separate monitor thread to get blocked, and you aren't even blocking the thread to try again just returning -1 to the guest. r~ From MAILER-DAEMON Wed Dec 18 15:20:31 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1ihfo6-0003Jf-W2 for mharc-qemu-arm@gnu.org; Wed, 18 Dec 2019 15:20:31 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:46127) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ihfo4-0003JP-Bd for qemu-arm@nongnu.org; Wed, 18 Dec 2019 15:20:29 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ihfo2-0005Lf-VM for qemu-arm@nongnu.org; Wed, 18 Dec 2019 15:20:27 -0500 Received: from mail-pg1-x541.google.com ([2607:f8b0:4864:20::541]:42984) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ihfo2-0005HZ-6w for qemu-arm@nongnu.org; Wed, 18 Dec 2019 15:20:26 -0500 Received: by mail-pg1-x541.google.com with SMTP id s64so1851095pgb.9 for ; Wed, 18 Dec 2019 12:20:25 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=subject:to:cc:references:from:message-id:date:user-agent :mime-version:in-reply-to:content-language:content-transfer-encoding; bh=e0F0O5XBsMvA6TFnNmXgjcc4PZlPDbOS60e2ICRnBf8=; b=ReDrUKnywIGJbaTsMy/auWkGB8LPssXluYZt0Gr/tynRYUb/CKJjrCHJgfMdoxbKKI Nn+GCjrNrsBPaphuWhWtLg2IOnBdXKvMOQe9ZOUhU3q9FAfZPqmcdXRuq5I9dOffl9KB Igc8hB2zknS04dx4pAW+kecBkpQKlymE2r/mfBhd0CuxkR7qjhB1Et9Y65Awg4MJPiMt 93rmAPAuBpdAZml4FBw5BCMWd+gx4VNvc2RbOQnXdUKqgos450IB/f1QnyM5c4RI+rPG CRbbpNyDUgejWHAef5VDzdTUGXmBBGqr8aZwWR3aeEiHEsKBKDhU+WetwwShgPU9Fi31 2uRw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:subject:to:cc:references:from:message-id:date :user-agent:mime-version:in-reply-to:content-language :content-transfer-encoding; bh=e0F0O5XBsMvA6TFnNmXgjcc4PZlPDbOS60e2ICRnBf8=; b=t+6gqSO9m6hxygTQ4Yygo2JHirODVmsXGEPDWI21tYdZYC8o/S2EfBiz1tgMa3eDjx H6YOxouxfLvsTpi0woEZb9cANTi3S/M9VWTdzrrooWt4scM0nJLhaVrZoGdfaY30X1pM L6+dmUlEg0URQbzE18+tc4mXdnrL1R2Cd+ToQZo8DyO1J+tVfO0JCkd0iB4fykK2+NJ5 XNw4Vc7QWpC2VbHDmC0ODsIpanKCu94hTC3be7UUaWJXztpsn9p0ZzQzyLUgCeZWF68L wwl+6UM9XRQHVG0Y7jUbZL+rd06HSRBsolITqBtvzCGSQiyFWRC4jcPzzi2TAPGPkJrm +MMw== X-Gm-Message-State: APjAAAUeapPf0+crWCjtGKkFhmPwwRc5bRFb0LF0HSNxEfCZjnosskxH s5MinuYHiLicoZJShia3yBYiSQ== X-Google-Smtp-Source: APXvYqyC6nsJ598nxWFCRrSBW9fXqdLaopHZS+dIH1PjffQM5MsiiFQTgK3eM0eEHF8pF5jC9fC0eg== X-Received: by 2002:a62:7b54:: with SMTP id w81mr5124131pfc.127.1576700424336; Wed, 18 Dec 2019 12:20:24 -0800 (PST) Received: from ?IPv6:2605:e000:c74f:dc00:6838:d2b2:17e2:8445? ([2605:e000:c74f:dc00:6838:d2b2:17e2:8445]) by smtp.gmail.com with ESMTPSA id q13sm3918673pjc.4.2019.12.18.12.20.22 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 18 Dec 2019 12:20:23 -0800 (PST) Subject: Re: [PATCH v1 4/4] tests/tcg: add a dumb-as-bricks semihosting console test To: =?UTF-8?Q?Alex_Benn=c3=a9e?= , qemu-devel@nongnu.org Cc: pbonzini@redhat.com, keithp@keithp.com, "open list:ARM TCG CPUs" , Peter Maydell References: <20191218180029.6744-1-alex.bennee@linaro.org> <20191218180029.6744-5-alex.bennee@linaro.org> From: Richard Henderson Message-ID: <593c8577-b1f8-f821-94cd-cf017300043a@linaro.org> Date: Wed, 18 Dec 2019 10:20:20 -1000 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.2.2 MIME-Version: 1.0 In-Reply-To: <20191218180029.6744-5-alex.bennee@linaro.org> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 8bit X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::541 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 18 Dec 2019 20:20:29 -0000 On 12/18/19 8:00 AM, Alex Bennée wrote: > We don't run this during check-tcg as we would need to check stuff is > echoed back. However we can still build the binary so people can test > it manually. > > Signed-off-by: Alex Bennée > --- > tests/tcg/aarch64/system/semiconsole.c | 36 +++++++++++++++++++++++ > tests/tcg/aarch64/Makefile.softmmu-target | 9 +++++- > 2 files changed, 44 insertions(+), 1 deletion(-) > create mode 100644 tests/tcg/aarch64/system/semiconsole.c Reviewed-by: Richard Henderson r~ From MAILER-DAEMON Wed Dec 18 15:31:00 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1ihfyG-0006ec-KK for mharc-qemu-arm@gnu.org; Wed, 18 Dec 2019 15:31:00 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:54376) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ihfyB-0006eE-U7 for qemu-arm@nongnu.org; Wed, 18 Dec 2019 15:30:57 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ihfy7-0004Vh-UC for qemu-arm@nongnu.org; Wed, 18 Dec 2019 15:30:53 -0500 Received: from mail-pf1-x444.google.com ([2607:f8b0:4864:20::444]:46168) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ihfy6-0004SG-4Q for qemu-arm@nongnu.org; Wed, 18 Dec 2019 15:30:51 -0500 Received: by mail-pf1-x444.google.com with SMTP id y14so1833309pfm.13 for ; Wed, 18 Dec 2019 12:30:49 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=subject:to:cc:references:from:message-id:date:user-agent :mime-version:in-reply-to:content-language:content-transfer-encoding; bh=Zwl2+Ft+3Qu+jRfq+fQCSw9Ftp5WH4Fwu9KoZnjQnYQ=; b=wDS+QciKsWnATGZ3S7yh04TBaSWMvEFWXTR0MnNheetTSCV7jjDK9sPngID3T5UJCP YpefQwyT2xKKNs5Q+vNcteHdw05WCiNKWtOTDsbtob+xAy7fkkTq9IS+LCoYyfhNOixK 8QoOmTu41zPi8aQ6Dr+7OORkEvsvApj5Yqu1lHOSV+2tAu/nTibTUGxwiunF2WA10Jak GGGLbL20aU8OqUbL4YuSQ1AX7qMQVaEmKyoNw/XV9buZ7MG6xpqPR46FkRpV/idI+MPJ YwY3hCb1WTgGa87t/RGjsTAdsOs05i9vdBqgzeY4bY+WpbfixoYaZH9DZShAo8AnXpjP 52kg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:subject:to:cc:references:from:message-id:date :user-agent:mime-version:in-reply-to:content-language :content-transfer-encoding; bh=Zwl2+Ft+3Qu+jRfq+fQCSw9Ftp5WH4Fwu9KoZnjQnYQ=; b=Ca7dZCO6gcR/D9XPl6rxJ6Momrr/jjAxF2zBegerAUxJdMg+rRxGwZg4IHsFu7+4UE L17ilwSLMf1byTS6aer0rWXui8ERAEVuK4ANQNiTMCXAmhRSKwmUoe1PpNiqGgzblL1u kXRqHbUVHsDQ35se24dzMdb0AVSCzkpaHWHimAWgrVt+5e3d8r6JrFai5p0PUr8NiT7q e0zB6Qcn2yv2P9cuMIsNWxOrqeOX0SRHJxkFrvn2Gmx2YTksVwJdu6VG4l3+vjRU1akP FBtALx2FHeKmwM53bhktBhWDbuXOgqvU28GO1CV8iwR/z8gVLu7rGIEiwph6Z/PBWJhr 2EwA== X-Gm-Message-State: APjAAAUhER5AtQKmWGVIaQgAjaQtIGLtPTTB6czbWQ0Q/Ki3JIfkSadE PeQ8brIMfafI8eDfVy8/IwyyQQ== X-Google-Smtp-Source: APXvYqw7f6sHKDhQfvFjYP9hr8Za8kGh2BUH3rg5tyOj5FE3kttKTyavZ823zuh2TR+0dYElgPU0mA== X-Received: by 2002:a62:e30f:: with SMTP id g15mr5103872pfh.124.1576701048672; Wed, 18 Dec 2019 12:30:48 -0800 (PST) Received: from ?IPv6:2605:e000:c74f:dc00:6838:d2b2:17e2:8445? ([2605:e000:c74f:dc00:6838:d2b2:17e2:8445]) by smtp.gmail.com with ESMTPSA id g9sm4613637pfm.150.2019.12.18.12.30.46 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 18 Dec 2019 12:30:47 -0800 (PST) Subject: Re: [RFC PATCH v2 5/6] hw/net/imx_fec: Remove unuseful FALLTHROUGH comments To: =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= , qemu-devel@nongnu.org Cc: Peter Maydell , Thomas Huth , Jason Wang , Markus Armbruster , qemu-arm@nongnu.org, Peter Chubb References: <20191218192526.13845-1-philmd@redhat.com> <20191218192526.13845-6-philmd@redhat.com> From: Richard Henderson Message-ID: Date: Wed, 18 Dec 2019 10:30:44 -1000 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.2.2 MIME-Version: 1.0 In-Reply-To: <20191218192526.13845-6-philmd@redhat.com> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 8bit X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::444 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 18 Dec 2019 20:30:57 -0000 On 12/18/19 9:25 AM, Philippe Mathieu-Daudé wrote: > We don't need to explicit these obvious switch fall through > comments. Stay consistent with the rest of the codebase. > > Suggested-by: Thomas Huth > Signed-off-by: Philippe Mathieu-Daudé > --- > Cc: Peter Chubb > Cc: Markus Armbruster > Cc: Peter Maydell > Cc: Jason Wang > Cc: qemu-arm@nongnu.org > --- > hw/net/imx_fec.c | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) Reviewed-by: Richard Henderson r~ From MAILER-DAEMON Wed Dec 18 15:31:37 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1ihfyr-000724-Ji for mharc-qemu-arm@gnu.org; Wed, 18 Dec 2019 15:31:37 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:58682) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ihfyn-0006yj-6E for qemu-arm@nongnu.org; Wed, 18 Dec 2019 15:31:35 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ihfyj-000652-IX for qemu-arm@nongnu.org; Wed, 18 Dec 2019 15:31:31 -0500 Received: from mail-pl1-x641.google.com ([2607:f8b0:4864:20::641]:47096) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ihfyf-00061t-U7 for qemu-arm@nongnu.org; Wed, 18 Dec 2019 15:31:27 -0500 Received: by mail-pl1-x641.google.com with SMTP id y8so1477788pll.13 for ; Wed, 18 Dec 2019 12:31:24 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=subject:to:cc:references:from:message-id:date:user-agent :mime-version:in-reply-to:content-language:content-transfer-encoding; bh=EgquuMahjEW5YEjdy3ojcA50VUIAktcr/XHmJSYUEiA=; b=o+/C0LqEINS+QtcNH/yIGAolsHPlUAquez6q0HgFiwy7J3Y3tKgV4JSKiBOuiupnjF YTzkN5WgaKYmhQb6qDP6zQjiPJCbsVFIVj+siZKqZCMhwUnC0HAME93OuJhG1owQhxI3 I8sTlifa6jncQxO6Fgbw+vhdXvcsK9vZdrpL7N6rC6nt2dg1m4Aw5PsJC4K92sRVOgkp qx/SYpURXuLMFC+KWRSpOBCGjKTUpbBWK88lf28W/RhrQAf6NFp/HufOggGwCxRXPC73 ffzUAt8Km5qBPNoNLc8V8ynKy4Bg6yUA79HYhEyp43iG7oVPcRwHoz8mSngC+QQ/NzoO XwBg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:subject:to:cc:references:from:message-id:date :user-agent:mime-version:in-reply-to:content-language :content-transfer-encoding; bh=EgquuMahjEW5YEjdy3ojcA50VUIAktcr/XHmJSYUEiA=; b=Hv/cf7R0u3gO0fXAIkDJztWbfzviwFFHIr6S2eDVqJK6YgtvmpDsLFF6uN1l6RHMTy zn+0jAA1i3DNHw3tWImCOYh81AjC2sVKROQhrmeuQd2z95aVntII8QrESmP0GiUnMVNf UacfPtWj1oinTza96uiMbDukg9DxrNq7oM0cRtjooapgSgUuXcJ5ANOisFdWe0eGjXW3 rk3hBiTNVZw6xMtWGdGbQ9PPximdOLcvPabqR4DDwDqShVAcrP2Tc6Ho8Vmhr6XAHnwI 5wRNhdBIK2v9hHALT/ZpMNcrLY+KbTeJ9AzdCBpGysc4v0MdjLwct89Gj7Un5cXCwdrr s+wQ== X-Gm-Message-State: APjAAAU1DvtbKWCv8kVikKrfGl8O/6RA/Q7rUmTwhlL0Blcfy3ArpGpZ 54nPasy5hkknT6BPM3j0dXChAg== X-Google-Smtp-Source: APXvYqzDxaFVta1H5y7LC61KAMLQ/pohVFpzDLNjModXZAIVe5PZBVWZDXIKOHfHPipZq+pJP0wGUw== X-Received: by 2002:a17:902:b902:: with SMTP id bf2mr4817097plb.137.1576701083484; Wed, 18 Dec 2019 12:31:23 -0800 (PST) Received: from ?IPv6:2605:e000:c74f:dc00:6838:d2b2:17e2:8445? ([2605:e000:c74f:dc00:6838:d2b2:17e2:8445]) by smtp.gmail.com with ESMTPSA id m101sm3955868pje.13.2019.12.18.12.31.21 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 18 Dec 2019 12:31:22 -0800 (PST) Subject: Re: [RFC PATCH v2 6/6] hw/pci-host/designware: Remove unuseful FALLTHROUGH comment To: =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= , qemu-devel@nongnu.org Cc: Peter Maydell , Andrey Smirnov , Markus Armbruster , qemu-arm@nongnu.org, Peter Chubb References: <20191218192526.13845-1-philmd@redhat.com> <20191218192526.13845-7-philmd@redhat.com> From: Richard Henderson Message-ID: Date: Wed, 18 Dec 2019 10:31:19 -1000 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.2.2 MIME-Version: 1.0 In-Reply-To: <20191218192526.13845-7-philmd@redhat.com> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 8bit X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::641 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 18 Dec 2019 20:31:35 -0000 On 12/18/19 9:25 AM, Philippe Mathieu-Daudé wrote: > We don't need to explicit this obvious switch fall through. > Stay consistent with the rest of the codebase. > > Signed-off-by: Philippe Mathieu-Daudé > --- > Cc: Peter Chubb > Cc: Markus Armbruster > Cc: Peter Maydell > Cc: Andrey Smirnov > Cc: qemu-arm@nongnu.org > --- > hw/pci-host/designware.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) Reviewed-by: Richard Henderson r~ From MAILER-DAEMON Wed Dec 18 15:44:38 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1ihgBR-0002ee-TJ for mharc-qemu-arm@gnu.org; Wed, 18 Dec 2019 15:44:37 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:35789) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ihgBO-0002cs-I8 for qemu-arm@nongnu.org; Wed, 18 Dec 2019 15:44:35 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ihgBM-0005zl-TO for qemu-arm@nongnu.org; Wed, 18 Dec 2019 15:44:34 -0500 Received: from mail-pj1-x1043.google.com ([2607:f8b0:4864:20::1043]:50221) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ihgBM-0005u4-Eg for qemu-arm@nongnu.org; Wed, 18 Dec 2019 15:44:32 -0500 Received: by mail-pj1-x1043.google.com with SMTP id r67so1425367pjb.0 for ; Wed, 18 Dec 2019 12:44:32 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=subject:to:cc:references:from:message-id:date:user-agent :mime-version:in-reply-to:content-language:content-transfer-encoding; bh=hx95OyaG6MqHCdsFBIXIiXsvovMiVCSH3FKPDjN/6WY=; b=UsNnZgRbhrHE74s+Y0gT23UUgUs1jGC47yo1iLtrOGZpR4nYucTXmbtGGb5MHA8dIf 4RjYWukG1+PXQgM+WvoXqVwMd6dsnhsfeEMp88gTGi4zssIU56jIuRyN7bZikZvg2oY9 5QQuOB2CeEqjG58lsS8yJD/HI14Mceq4BGE4194tENFkxkdHkhutttnJWQ/maa/3v5hI xMwybm+viLIQQ7O1Gcl1QrHWU/IAjO25g2gWwUJOMsOfK1R/rsApvajg5atogy1fnnM1 9M2b7yzgi7/2Es3mOzVpzZnNu/farTn+N3wof0vTuOa2VGjnAwijYOV/f+sMP9a6wTKe WPSQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:subject:to:cc:references:from:message-id:date :user-agent:mime-version:in-reply-to:content-language :content-transfer-encoding; bh=hx95OyaG6MqHCdsFBIXIiXsvovMiVCSH3FKPDjN/6WY=; b=fB6BJD/hIZI3schoU5l5hKmw9KV6V/63j/yHcm/3a5hhg49Wogs9nbuERc3WwntnmH bNO8bG7tgiaAGTJNQg6mMnmSdtPg8o8tHJexQgBdAyyrb0WeKXgpmhWaP5HVZbtXZrIT quLh1t1t5RvCuNalfgrVIigJ3dS2AFdK8MDXcVdthtxME026y6A6oGul+Lerm/GB5LUk 0dHj0gjeC3crfuquWZfiq5VosBUb80GhUPTFIOh3cA8a0jKm8ZnJ9SDS1JAdGVYXR4dq n+TsFkECEetRfPG5ojTYUQ5QTIwRL74v870MJ8EcQ0d5MlRzDlEoWXxrTFMbiH8iUFjI 53Iw== X-Gm-Message-State: APjAAAXb/7GN3kLWE785hz5rv3dpbsF+B+o2xC3zxz1V95coDpeKQg+5 mpxHLZNwXZMtr0pf4oyQR0rmQg== X-Google-Smtp-Source: APXvYqwVxVL3Hy6fs5yv8x16VFaZHBLw+vLi/oQiTCjEj3vG/sK7eDsdh4TZ3GUPpQeDAknI3gdWsg== X-Received: by 2002:a17:902:363:: with SMTP id 90mr4845316pld.71.1576701871230; Wed, 18 Dec 2019 12:44:31 -0800 (PST) Received: from ?IPv6:2605:e000:c74f:dc00:6838:d2b2:17e2:8445? ([2605:e000:c74f:dc00:6838:d2b2:17e2:8445]) by smtp.gmail.com with ESMTPSA id ep12sm2325545pjb.7.2019.12.18.12.44.26 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 18 Dec 2019 12:44:30 -0800 (PST) Subject: Re: [RFC PATCH v2 14/14] chardev: Use QEMUChrEvent enum in IOEventHandler typedef To: =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= , qemu-devel@nongnu.org Cc: Peter Maydell , Sagar Karandikar , "Michael S. Tsirkin" , Jason Wang , KONRAD Frederic , Gerd Hoffmann , "Edgar E. Iglesias" , Paul Burton , Alberto Garcia , Li Zhijian , qemu-block@nongnu.org, Zhang Chen , Markus Armbruster , Halil Pasic , Christian Borntraeger , "Gonglei (Arei)" , Antony Pavlov , =?UTF-8?Q?Marc-Andr=c3=a9_Lureau?= , Aleksandar Rikalo , Joel Stanley , Laurent Vivier , Corey Minyard , Amit Shah , Alistair Francis , "Dr. David Alan Gilbert" , Fabien Chouteau , qemu-s390x@nongnu.org, qemu-arm@nongnu.org, Peter Chubb , Samuel Thibault , =?UTF-8?Q?Alex_Benn=c3=a9e?= , Kevin Wolf , qemu-riscv@nongnu.org, Igor Mitsyanko , Cornelia Huck , Max Reitz , Thomas Huth , Michael Walle , Palmer Dabbelt , Aleksandar Markovic , Bastian Koppelmann , Paolo Bonzini , Aurelien Jarno References: <20191218172009.8868-1-philmd@redhat.com> <20191218172009.8868-15-philmd@redhat.com> From: Richard Henderson Message-ID: Date: Wed, 18 Dec 2019 10:44:23 -1000 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.2.2 MIME-Version: 1.0 In-Reply-To: <20191218172009.8868-15-philmd@redhat.com> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 8bit X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::1043 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 18 Dec 2019 20:44:35 -0000 On 12/18/19 7:20 AM, Philippe Mathieu-Daudé wrote: > The Chardev events are listed in the QEMUChrEvent enum. > > By using the enum in the IOEventHandler typedef we: > > - make the IOEventHandler type more explicit (this handler > process out-of-band information, while the IOReadHandler > is in-band), > - help static code analyzers. > > This patch was produced with the following spatch script: > > @match@ > expression backend, opaque, context, set_open; > identifier fd_can_read, fd_read, fd_event, be_change; > @@ > qemu_chr_fe_set_handlers(backend, fd_can_read, fd_read, fd_event, > be_change, opaque, context, set_open); > > @depends on match@ > identifier opaque, event; > identifier match.fd_event; > @@ > static > -void fd_event(void *opaque, int event) > +void fd_event(void *opaque, QEMUChrEvent event) > { > ... > } > > Then the following files were manually modified: > > - include/chardev/char-fe.h > - include/chardev/char.h > - include/chardev/char-mux.h > - chardev/char.c > - chardev/char-mux.c My guess is that the only change that must be done at the same time as the spatch is the typedef in char-fe.h. In particular, > -static void mux_chr_send_event(MuxChardev *d, int mux_nr, int event) > +static void mux_chr_send_event(MuxChardev *d, int mux_nr, QEMUChrEvent event) this doesn't appear to be required -- int will implicitly convert to enum when performing the call, and it can't be related to the typedef. Yes, we do want to propagate the type up the call stack, but it would be nice to see the spatch results on their own. r~ From MAILER-DAEMON Wed Dec 18 15:49:48 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1ihgGS-0005rF-Qi for mharc-qemu-arm@gnu.org; Wed, 18 Dec 2019 15:49:48 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:59068) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ihgGN-0005mM-RA for qemu-arm@nongnu.org; Wed, 18 Dec 2019 15:49:47 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ihgGJ-0006a6-NL for qemu-arm@nongnu.org; Wed, 18 Dec 2019 15:49:43 -0500 Received: from mail-il1-x141.google.com ([2607:f8b0:4864:20::141]:36436) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ihgGB-0006S4-T6; Wed, 18 Dec 2019 15:49:32 -0500 Received: by mail-il1-x141.google.com with SMTP id b15so2884251iln.3; Wed, 18 Dec 2019 12:49:28 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=iWtEX5iWpfFX5/5aJLaNvyTdKGsb22z6bJhbArJSwiE=; b=N3nmx0KFkypTD+KP24XDB4xd9WyaUu93VbNdo/yjD2pMqVko+uXPk0CHrOHAOK6uTa qReru/+FdKJ7KFL9yT0f5RGO238uK4VRsojWE2uuH2qwY0iIEZJUCWfWvEfg3GgHsuPC tNlkox6qpCGaRCcjvLe8wO/fD95yvr2sc5bcftDHV0LdjJJDhZycFNqYWhvGJ88C5auJ ri8EKELpb7LxlY5xuIfqeqkNYJB32Rc77pcoURsWgg54ka6jZa2DL85fBmrE5EAGamiF h7rIhx0hn+yYuffyrS9IBLrxypp5hxc8TvVlYvk+WJDJfP4EX43Eo3hUVgFz7Pm4++zp FOyg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=iWtEX5iWpfFX5/5aJLaNvyTdKGsb22z6bJhbArJSwiE=; b=ErnadzqMCQiawgC4iz/XCxPcyvKc/eZNHqzWOnHJLldfwa2a/tee8mIDknaCe17yB5 VRSxhzx1WDz7tnMd3mtKd11txoQ4MLxXObeX/t/pmgzy9Rue42dz7P7Y/tkEMVKmmt0L 0FjDzYYbkKplxvaR6YcUSqBzvEVsSssoYGa0TWC9kVucbSYs+tEB2hUYonQt65rodSBm AbrR1yWnHmf5r8BKyVapV3tp14lZRsCl0mWgj2O0JEkZ2l32FORg6FV4itN/lacBxy0g bInAh+Q5XfLvF9ooFonO0YioikzoXBsZIgidK9eEW1sZ/sSM3+v0O4vKJg44zjGsZ7fM 5oFg== X-Gm-Message-State: APjAAAU2HmbD5ls1HCndNZZLrEieNNlEI3Prvuz3lYpK6YdS0xjenjyf j4DNDEGIjjaOsPfwpNwzv3dVjR+zuyasIUmP07w= X-Google-Smtp-Source: APXvYqzaaodGzAqIqWZPz2CrYnXD7dsyUeUpz8QRfLIYf8IKTU1xkkZxlruPFbPiqEDy2naR+D6IS4bJCxaMZ4AtscA= X-Received: by 2002:a92:c647:: with SMTP id 7mr3832792ill.28.1576702167837; Wed, 18 Dec 2019 12:49:27 -0800 (PST) MIME-Version: 1.0 References: <20191216233519.29030-1-nieklinnenbank@gmail.com> <20191216233519.29030-9-nieklinnenbank@gmail.com> <7153b766-4c3b-5272-3c3e-33e973e74e8f@redhat.com> In-Reply-To: <7153b766-4c3b-5272-3c3e-33e973e74e8f@redhat.com> From: Niek Linnenbank Date: Wed, 18 Dec 2019 21:49:15 +0100 Message-ID: Subject: Re: [PATCH v2 08/10] arm: allwinner-h3: add Security Identifier device To: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= Cc: QEMU Developers , qemu-arm , Peter Maydell Content-Type: multipart/alternative; boundary="000000000000a170b4059a0094dc" X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::141 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 18 Dec 2019 20:49:47 -0000 --000000000000a170b4059a0094dc Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Hi Philippe, On Tue, Dec 17, 2019 at 8:45 AM Philippe Mathieu-Daud=C3=A9 wrote: > Hi Niek, > > On 12/17/19 12:35 AM, Niek Linnenbank wrote: > > The Security Identifier device in Allwinner H3 System on Chip > > gives applications a per-board unique identifier. This commit > > adds support for the Allwinner H3 Security Identifier using > > a 128-bit UUID value as input. > > > > Signed-off-by: Niek Linnenbank > > --- > > include/hw/arm/allwinner-h3.h | 2 + > > include/hw/misc/allwinner-h3-sid.h | 40 +++++++ > > hw/arm/allwinner-h3.c | 7 ++ > > hw/arm/orangepi.c | 4 + > > hw/misc/allwinner-h3-sid.c | 179 ++++++++++++++++++++++++++++= + > > hw/misc/Makefile.objs | 1 + > > hw/misc/trace-events | 4 + > > 7 files changed, 237 insertions(+) > > create mode 100644 include/hw/misc/allwinner-h3-sid.h > > create mode 100644 hw/misc/allwinner-h3-sid.c > > > > diff --git a/include/hw/arm/allwinner-h3.h > b/include/hw/arm/allwinner-h3.h > > index 8128ae6131..c98c1972a6 100644 > > --- a/include/hw/arm/allwinner-h3.h > > +++ b/include/hw/arm/allwinner-h3.h > > @@ -29,6 +29,7 @@ > > #include "hw/misc/allwinner-h3-clk.h" > > #include "hw/misc/allwinner-h3-cpucfg.h" > > #include "hw/misc/allwinner-h3-syscon.h" > > +#include "hw/misc/allwinner-h3-sid.h" > > #include "target/arm/cpu.h" > > > > enum { > > @@ -77,6 +78,7 @@ typedef struct AwH3State { > > AwH3ClockState ccu; > > AwH3CpuCfgState cpucfg; > > AwH3SysconState syscon; > > + AwH3SidState sid; > > GICState gic; > > MemoryRegion sram_a1; > > MemoryRegion sram_a2; > > diff --git a/include/hw/misc/allwinner-h3-sid.h > b/include/hw/misc/allwinner-h3-sid.h > > new file mode 100644 > > index 0000000000..79c9a24459 > > --- /dev/null > > +++ b/include/hw/misc/allwinner-h3-sid.h > > @@ -0,0 +1,40 @@ > > +/* > > + * Allwinner H3 Security ID emulation > > + * > > + * Copyright (C) 2019 Niek Linnenbank > > + * > > + * This program is free software: you can redistribute it and/or modif= y > > + * it under the terms of the GNU General Public License as published b= y > > + * the Free Software Foundation, either version 2 of the License, or > > + * (at your option) any later version. > > + * > > + * This program is distributed in the hope that it will be useful, > > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > > + * GNU General Public License for more details. > > + * > > + * You should have received a copy of the GNU General Public License > > + * along with this program. If not, see >. > > + */ > > + > > +#ifndef HW_MISC_ALLWINNER_H3_SID_H > > +#define HW_MISC_ALLWINNER_H3_SID_H > > + > > +#include "hw/sysbus.h" > > +#include "qemu/uuid.h" > > + > > +#define TYPE_AW_H3_SID "allwinner-h3-sid" > > +#define AW_H3_SID(obj) OBJECT_CHECK(AwH3SidState, (obj), > TYPE_AW_H3_SID) > > + > > +typedef struct AwH3SidState { > > + /*< private >*/ > > + SysBusDevice parent_obj; > > + /*< public >*/ > > + > > + MemoryRegion iomem; > > + uint32_t control; > > + uint32_t rdkey; > > + QemuUUID identifier; > > +} AwH3SidState; > > + > > +#endif > > diff --git a/hw/arm/allwinner-h3.c b/hw/arm/allwinner-h3.c > > index 1a9748ab2e..ba34f905cd 100644 > > --- a/hw/arm/allwinner-h3.c > > +++ b/hw/arm/allwinner-h3.c > > @@ -196,6 +196,9 @@ static void aw_h3_init(Object *obj) > > > > sysbus_init_child_obj(obj, "cpucfg", &s->cpucfg, sizeof(s->cpucfg= ), > > TYPE_AW_H3_CPUCFG); > > + > > + sysbus_init_child_obj(obj, "sid", &s->sid, sizeof(s->sid), > > + TYPE_AW_H3_SID); > > Here add a property alias: > > object_property_add_alias(obj, "identifier", OBJECT(&s->sid), > "identifier", &error_abort); > > > } > > > > static void aw_h3_realize(DeviceState *dev, Error **errp) > > @@ -332,6 +335,10 @@ static void aw_h3_realize(DeviceState *dev, Error > **errp) > > qdev_init_nofail(DEVICE(&s->cpucfg)); > > sysbus_mmio_map(SYS_BUS_DEVICE(&s->cpucfg), 0, > s->memmap[AW_H3_CPUCFG]); > > > > + /* Security Identifier */ > > + qdev_init_nofail(DEVICE(&s->sid)); > > + sysbus_mmio_map(SYS_BUS_DEVICE(&s->sid), 0, s->memmap[AW_H3_SID]); > > + > > /* Universal Serial Bus */ > > sysbus_create_simple(TYPE_AW_H3_EHCI, s->memmap[AW_H3_EHCI0], > > qdev_get_gpio_in(DEVICE(&s->gic), > > diff --git a/hw/arm/orangepi.c b/hw/arm/orangepi.c > > index 62cefc8c06..b01c4b4f01 100644 > > --- a/hw/arm/orangepi.c > > +++ b/hw/arm/orangepi.c > > @@ -62,6 +62,10 @@ static void orangepi_init(MachineState *machine) > > exit(1); > > } > > > > + /* Setup SID properties */ > > + qdev_prop_set_string(DEVICE(&s->h3->sid), "identifier", > > + "8100c002-0001-0002-0003-000044556677"); > > And here use the alias: > > qdev_prop_set_string(DEVICE(&s->h3), "identifier", > "8100c002-0001-0002-0003-000044556677"); > Ah OK, I see what you mean. The boards should be using the SoC object only and not directly any of its sub devices, correct? > > What means this value? Don't you want to be able to set it from command > line? > The first word 0x02c00081 is the identifying word for the H3 SoC in the SID data. After that come the per-device unique specific bytes. This is documented at the end of this page in 'Currently known SID's' on the linux-sunxi.org Wiki= : https://linux-sunxi.org/SID_Register_Guide The remaining parts of this value I simply made up without any real meaning= . And yes, it would in fact make sense to have the user be able to override it from the command line. It is used by U-boot as an input for generating the MAC address. Linux also reads it, but I did not investigate how it us used there. I think I did make a TODO of using a cmdline argument, but later forgot to actually implement it. Do you have a suggestion how to best provide the command line argument? I do see '-device driver[,prop=3Dvalue]' is there in the --help for qemu-system-arm, but it looks like that should be used by the user for adding PCI / USB devices? > > /* Mark H3 object realized */ > > object_property_set_bool(OBJECT(s->h3), true, "realized", > &error_abort); > > if (error_abort !=3D NULL) { > > diff --git a/hw/misc/allwinner-h3-sid.c b/hw/misc/allwinner-h3-sid.c > > new file mode 100644 > > index 0000000000..c472f2bcc6 > > --- /dev/null > > +++ b/hw/misc/allwinner-h3-sid.c > > @@ -0,0 +1,179 @@ > > +/* > > + * Allwinner H3 Security ID emulation > > + * > > + * Copyright (C) 2019 Niek Linnenbank > > + * > > + * This program is free software: you can redistribute it and/or modif= y > > + * it under the terms of the GNU General Public License as published b= y > > + * the Free Software Foundation, either version 2 of the License, or > > + * (at your option) any later version. > > + * > > + * This program is distributed in the hope that it will be useful, > > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > > + * GNU General Public License for more details. > > + * > > + * You should have received a copy of the GNU General Public License > > + * along with this program. If not, see >. > > + */ > > + > > +#include "qemu/osdep.h" > > +#include "qemu/units.h" > > +#include "hw/sysbus.h" > > +#include "migration/vmstate.h" > > +#include "qemu/log.h" > > +#include "qemu/module.h" > > +#include "qemu/guest-random.h" > > +#include "qapi/error.h" > > +#include "hw/qdev-properties.h" > > +#include "hw/misc/allwinner-h3-sid.h" > > +#include "trace.h" > > + > > +/* SID register offsets */ > > +enum { > > + REG_PRCTL =3D 0x40, /* Control */ > > + REG_RDKEY =3D 0x60, /* Read Key */ > > +}; > > + > > +/* SID register flags */ > > +enum { > > + REG_PRCTL_WRITE =3D 0x0002, /* Unknown write flag */ > > + REG_PRCTL_OP_LOCK =3D 0xAC00, /* Lock operation */ > > +}; > > + > > +static uint64_t allwinner_h3_sid_read(void *opaque, hwaddr offset, > > + unsigned size) > > +{ > > + const AwH3SidState *s =3D (AwH3SidState *)opaque; > > + uint64_t val =3D 0; > > + > > + switch (offset) { > > + case REG_PRCTL: /* Control */ > > + val =3D s->control; > > + break; > > + case REG_RDKEY: /* Read Key */ > > + val =3D s->rdkey; > > + break; > > + default: > > + qemu_log_mask(LOG_GUEST_ERROR, "%s: bad read offset 0x%04x\n", > > + __func__, (uint32_t)offset); > > + return 0; > > + } > > + > > + trace_allwinner_h3_sid_read(offset, val, size); > > + > > + return val; > > +} > > + > > +static void allwinner_h3_sid_write(void *opaque, hwaddr offset, > > + uint64_t val, unsigned size) > > +{ > > + AwH3SidState *s =3D (AwH3SidState *)opaque; > > + > > + trace_allwinner_h3_sid_write(offset, val, size); > > + > > + switch (offset) { > > + case REG_PRCTL: /* Control */ > > + s->control =3D val; > > + > > + if ((s->control & REG_PRCTL_OP_LOCK) && > > + (s->control & REG_PRCTL_WRITE)) { > > + uint32_t id =3D s->control >> 16; > > + > > + if (id < sizeof(QemuUUID)) { > > + s->rdkey =3D (s->identifier.data[id]) | > > + (s->identifier.data[id + 1] << 8) | > > + (s->identifier.data[id + 2] << 16) | > > + (s->identifier.data[id + 3] << 24); > > This is: > > s->rdkey =3D ldl_le_p(&s->identifier.data[id]); > > > + } > > + } > > + s->control &=3D ~REG_PRCTL_WRITE; > > + break; > > + case REG_RDKEY: /* Read Key */ > > Read in a write()? > > Maybe we can simply /* fall through */ LOG_GUEST_ERROR? > When writing this module, I looked at how U-Boot is using the SID registers and simply named the registers after the names used by U-Boot. You can find this part in arch/arm/mach-sunxi/cpu_info.c:111, functions sun8i_efuse_read() and sunxi_get_sid(). U-Boot defines SIDC_RDKEY, so I named the register also rdkey. I used the U-Boot source because the Allwinner H3 datasheet does not document the registers. Later I found the SID page on the linux-sunxi wiki that I mentioned earlier, and they also describe the same register names: https://linux-sunxi.org/SID_Register_Guide I suspect the information on this page is written based on the source code from the original SDK (which I did not study btw) > > > + break; > > + default: > > + qemu_log_mask(LOG_GUEST_ERROR, "%s: bad write offset 0x%04x\n"= , > > + __func__, (uint32_t)offset); > > + break; > > + } > > +} > > + > > +static const MemoryRegionOps allwinner_h3_sid_ops =3D { > > + .read =3D allwinner_h3_sid_read, > > + .write =3D allwinner_h3_sid_write, > > + .endianness =3D DEVICE_NATIVE_ENDIAN, > > + .valid =3D { > > + .min_access_size =3D 4, > > + .max_access_size =3D 4, > > + .unaligned =3D false > > 'false' is the default value, maybe we can omit it? > Sure, I'll remove it. > > > + }, > > + .impl.min_access_size =3D 4, > > +}; > > + > > +static void allwinner_h3_sid_reset(DeviceState *dev) > > +{ > > + AwH3SidState *s =3D AW_H3_SID(dev); > > + > > + /* Set default values for registers */ > > + s->control =3D 0; > > + s->rdkey =3D 0; > > +} > > + > > +static void allwinner_h3_sid_realize(DeviceState *dev, Error **errp) > > +{ > > +} > > If you don't need realize(), just remove it. However maybe we want to > check if the identifier is null, either warn/abort or generate a random > one? > OK, removing it! > > > + > > +static void allwinner_h3_sid_init(Object *obj) > > +{ > > + SysBusDevice *sbd =3D SYS_BUS_DEVICE(obj); > > + AwH3SidState *s =3D AW_H3_SID(obj); > > + > > + /* Fill UUID with zeroes by default */ > > + qemu_uuid_parse(UUID_NONE, &s->identifier); > > AwH3SidState is zeroed just before this init() call. I think we don't > need to zeroes the UUID again. > Ah OK, so you mean new objects are always zeroed. That makes it much easier indeed. Thanks, I'll remove those lines. > > > + > > + /* Memory mapping */ > > + memory_region_init_io(&s->iomem, OBJECT(s), &allwinner_h3_sid_ops, > s, > > + TYPE_AW_H3_SID, 1 * KiB); > > + sysbus_init_mmio(sbd, &s->iomem); > > +} > > + > > +static Property allwinner_h3_sid_properties[] =3D { > > + DEFINE_PROP_UUID_NODEFAULT("identifier", AwH3SidState, identifier)= , > > + DEFINE_PROP_END_OF_LIST() > > +}; > > + > > +static const VMStateDescription allwinner_h3_sid_vmstate =3D { > > + .name =3D "allwinner-h3-sid", > > + .version_id =3D 1, > > + .minimum_version_id =3D 1, > > + .fields =3D (VMStateField[]) { > > + VMSTATE_UINT32(control, AwH3SidState), > > + VMSTATE_UINT32(rdkey, AwH3SidState), > > + VMSTATE_END_OF_LIST() > > + } > > +}; > > + > > +static void allwinner_h3_sid_class_init(ObjectClass *klass, void *data= ) > > +{ > > + DeviceClass *dc =3D DEVICE_CLASS(klass); > > + > > + dc->reset =3D allwinner_h3_sid_reset; > > + dc->realize =3D allwinner_h3_sid_realize; > > + dc->vmsd =3D &allwinner_h3_sid_vmstate; > > + dc->props =3D allwinner_h3_sid_properties; > > +} > > + > > +static const TypeInfo allwinner_h3_sid_info =3D { > > + .name =3D TYPE_AW_H3_SID, > > + .parent =3D TYPE_SYS_BUS_DEVICE, > > + .instance_init =3D allwinner_h3_sid_init, > > + .instance_size =3D sizeof(AwH3SidState), > > + .class_init =3D allwinner_h3_sid_class_init, > > +}; > > + > > +static void allwinner_h3_sid_register(void) > > +{ > > + type_register_static(&allwinner_h3_sid_info); > > +} > > + > > +type_init(allwinner_h3_sid_register) > > diff --git a/hw/misc/Makefile.objs b/hw/misc/Makefile.objs > > index c4ca2ed689..f3620eee4e 100644 > > --- a/hw/misc/Makefile.objs > > +++ b/hw/misc/Makefile.objs > > @@ -31,6 +31,7 @@ common-obj-$(CONFIG_IVSHMEM_DEVICE) +=3D ivshmem.o > > common-obj-$(CONFIG_ALLWINNER_H3) +=3D allwinner-h3-clk.o > > obj-$(CONFIG_ALLWINNER_H3) +=3D allwinner-h3-cpucfg.o > > common-obj-$(CONFIG_ALLWINNER_H3) +=3D allwinner-h3-syscon.o > > +common-obj-$(CONFIG_ALLWINNER_H3) +=3D allwinner-h3-sid.o > > common-obj-$(CONFIG_REALVIEW) +=3D arm_sysctl.o > > common-obj-$(CONFIG_NSERIES) +=3D cbus.o > > common-obj-$(CONFIG_ECCMEMCTL) +=3D eccmemctl.o > > diff --git a/hw/misc/trace-events b/hw/misc/trace-events > > index b93089d010..a777844ca3 100644 > > --- a/hw/misc/trace-events > > +++ b/hw/misc/trace-events > > @@ -5,6 +5,10 @@ allwinner_h3_cpucfg_cpu_reset(uint8_t cpu_id, uint32_t > reset_addr) "H3-CPUCFG: c > > allwinner_h3_cpucfg_read(uint64_t offset, uint64_t data, unsigned > size) "H3-CPUCFG: read: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %" > PRIu32 > > allwinner_h3_cpucfg_write(uint64_t offset, uint64_t data, unsigned > size) "H3-CPUCFG: write: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %" > PRIu32 > > > > +# allwinner-h3-sid.c > > +allwinner_h3_sid_read(uint64_t offset, uint64_t data, unsigned size) > "H3-SID: read: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %" PRIu32 > > +allwinner_h3_sid_write(uint64_t offset, uint64_t data, unsigned size) > "H3-SID: write: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %" PRIu32 > > + > > # eccmemctl.c > > ecc_mem_writel_mer(uint32_t val) "Write memory enable 0x%08x" > > ecc_mem_writel_mdr(uint32_t val) "Write memory delay 0x%08x" > > > > Regards, Niek --=20 Niek Linnenbank --000000000000a170b4059a0094dc Content-Type: text/html; charset="UTF-8" Content-Transfer-Encoding: quoted-printable
Hi Philippe,

=
On Tue, Dec 17, 2019 at 8:45 AM Phili= ppe Mathieu-Daud=C3=A9 <philmd@redh= at.com> wrote:
Hi Niek,

On 12/17/19 12:35 AM, Niek Linnenbank wrote:
> The Security Identifier device in Allwinner H3 System on Chip
> gives applications a per-board unique identifier. This commit
> adds support for the Allwinner H3 Security Identifier using
> a 128-bit UUID value as input.
>
> Signed-off-by: Niek Linnenbank <nieklinnenbank@gmail.com>
> ---
>=C2=A0 =C2=A0include/hw/arm/allwinner-h3.h=C2=A0 =C2=A0 =C2=A0 |=C2=A0 = =C2=A02 +
>=C2=A0 =C2=A0include/hw/misc/allwinner-h3-sid.h |=C2=A0 40 +++++++
>=C2=A0 =C2=A0hw/arm/allwinner-h3.c=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 |=C2=A0 =C2=A07 ++
>=C2=A0 =C2=A0hw/arm/orangepi.c=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0 =C2=A0 |=C2=A0 =C2=A04 +
>=C2=A0 =C2=A0hw/misc/allwinner-h3-sid.c=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0| 179 +++++++++++++++++++++++++++++
>=C2=A0 =C2=A0hw/misc/Makefile.objs=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 |=C2=A0 =C2=A01 +
>=C2=A0 =C2=A0hw/misc/trace-events=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0|=C2=A0 =C2=A04 +
>=C2=A0 =C2=A07 files changed, 237 insertions(+)
>=C2=A0 =C2=A0create mode 100644 include/hw/misc/allwinner-h3-sid.h
>=C2=A0 =C2=A0create mode 100644 hw/misc/allwinner-h3-sid.c
>
> diff --git a/include/hw/arm/allwinner-h3.h b/include/hw/arm/allwinner-= h3.h
> index 8128ae6131..c98c1972a6 100644
> --- a/include/hw/arm/allwinner-h3.h
> +++ b/include/hw/arm/allwinner-h3.h
> @@ -29,6 +29,7 @@
>=C2=A0 =C2=A0#include "hw/misc/allwinner-h3-clk.h"
>=C2=A0 =C2=A0#include "hw/misc/allwinner-h3-cpucfg.h"
>=C2=A0 =C2=A0#include "hw/misc/allwinner-h3-syscon.h"
> +#include "hw/misc/allwinner-h3-sid.h"
>=C2=A0 =C2=A0#include "target/arm/cpu.h"
>=C2=A0 =C2=A0
>=C2=A0 =C2=A0enum {
> @@ -77,6 +78,7 @@ typedef struct AwH3State {
>=C2=A0 =C2=A0 =C2=A0 =C2=A0AwH3ClockState ccu;
>=C2=A0 =C2=A0 =C2=A0 =C2=A0AwH3CpuCfgState cpucfg;
>=C2=A0 =C2=A0 =C2=A0 =C2=A0AwH3SysconState syscon;
> +=C2=A0 =C2=A0 AwH3SidState sid;
>=C2=A0 =C2=A0 =C2=A0 =C2=A0GICState gic;
>=C2=A0 =C2=A0 =C2=A0 =C2=A0MemoryRegion sram_a1;
>=C2=A0 =C2=A0 =C2=A0 =C2=A0MemoryRegion sram_a2;
> diff --git a/include/hw/misc/allwinner-h3-sid.h b/include/hw/misc/allw= inner-h3-sid.h
> new file mode 100644
> index 0000000000..79c9a24459
> --- /dev/null
> +++ b/include/hw/misc/allwinner-h3-sid.h
> @@ -0,0 +1,40 @@
> +/*
> + * Allwinner H3 Security ID emulation
> + *
> + * Copyright (C) 2019 Niek Linnenbank <nieklinnenbank@gmail.com>
> + *
> + * This program is free software: you can redistribute it and/or modi= fy
> + * it under the terms of the GNU General Public License as published = by
> + * the Free Software Foundation, either version 2 of the License, or<= br> > + * (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful, > + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.=C2=A0 See the=
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License<= br> > + * along with this program.=C2=A0 If not, see <http://www.gnu.o= rg/licenses/>.
> + */
> +
> +#ifndef HW_MISC_ALLWINNER_H3_SID_H
> +#define HW_MISC_ALLWINNER_H3_SID_H
> +
> +#include "hw/sysbus.h"
> +#include "qemu/uuid.h"
> +
> +#define TYPE_AW_H3_SID=C2=A0 =C2=A0 "allwinner-h3-sid"
> +#define AW_H3_SID(obj)=C2=A0 =C2=A0 OBJECT_CHECK(AwH3SidState, (obj),= TYPE_AW_H3_SID)
> +
> +typedef struct AwH3SidState {
> +=C2=A0 =C2=A0 /*< private >*/
> +=C2=A0 =C2=A0 SysBusDevice parent_obj;
> +=C2=A0 =C2=A0 /*< public >*/
> +
> +=C2=A0 =C2=A0 MemoryRegion iomem;
> +=C2=A0 =C2=A0 uint32_t control;
> +=C2=A0 =C2=A0 uint32_t rdkey;
> +=C2=A0 =C2=A0 QemuUUID identifier;
> +} AwH3SidState;
> +
> +#endif
> diff --git a/hw/arm/allwinner-h3.c b/hw/arm/allwinner-h3.c
> index 1a9748ab2e..ba34f905cd 100644
> --- a/hw/arm/allwinner-h3.c
> +++ b/hw/arm/allwinner-h3.c
> @@ -196,6 +196,9 @@ static void aw_h3_init(Object *obj)
>=C2=A0 =C2=A0
>=C2=A0 =C2=A0 =C2=A0 =C2=A0sysbus_init_child_obj(obj, "cpucfg"= ;, &s->cpucfg, sizeof(s->cpucfg),
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0TYPE_AW_H3_CPUCFG);
> +
> +=C2=A0 =C2=A0 sysbus_init_child_obj(obj, "sid", &s->= sid, sizeof(s->sid),
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0 =C2=A0 TYPE_AW_H3_SID);

Here add a property alias:

=C2=A0 =C2=A0 =C2=A0 =C2=A0 object_property_add_alias(obj, "identifier= ", OBJECT(&s->sid),
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 "identifier", &= error_abort);

>=C2=A0 =C2=A0}
>=C2=A0 =C2=A0
>=C2=A0 =C2=A0static void aw_h3_realize(DeviceState *dev, Error **errp)<= br> > @@ -332,6 +335,10 @@ static void aw_h3_realize(DeviceState *dev, Error= **errp)
>=C2=A0 =C2=A0 =C2=A0 =C2=A0qdev_init_nofail(DEVICE(&s->cpucfg));=
>=C2=A0 =C2=A0 =C2=A0 =C2=A0sysbus_mmio_map(SYS_BUS_DEVICE(&s->cp= ucfg), 0, s->memmap[AW_H3_CPUCFG]);
>=C2=A0 =C2=A0
> +=C2=A0 =C2=A0 /* Security Identifier */
> +=C2=A0 =C2=A0 qdev_init_nofail(DEVICE(&s->sid));
> +=C2=A0 =C2=A0 sysbus_mmio_map(SYS_BUS_DEVICE(&s->sid), 0, s-&g= t;memmap[AW_H3_SID]);
> +
>=C2=A0 =C2=A0 =C2=A0 =C2=A0/* Universal Serial Bus */
>=C2=A0 =C2=A0 =C2=A0 =C2=A0sysbus_create_simple(TYPE_AW_H3_EHCI, s->= memmap[AW_H3_EHCI0],
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 qdev_get_gpio_in(DEVICE(&s->gic),
> diff --git a/hw/arm/orangepi.c b/hw/arm/orangepi.c
> index 62cefc8c06..b01c4b4f01 100644
> --- a/hw/arm/orangepi.c
> +++ b/hw/arm/orangepi.c
> @@ -62,6 +62,10 @@ static void orangepi_init(MachineState *machine) >=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0exit(1);
>=C2=A0 =C2=A0 =C2=A0 =C2=A0}
>=C2=A0 =C2=A0
> +=C2=A0 =C2=A0 /* Setup SID properties */
> +=C2=A0 =C2=A0 qdev_prop_set_string(DEVICE(&s->h3->sid), &qu= ot;identifier",
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0 =C2=A0"8100c002-0001-0002-0003-000044556677");

And here use the alias:

=C2=A0 =C2=A0 =C2=A0 =C2=A0 qdev_prop_set_string(DEVICE(&s->h3), &qu= ot;identifier",
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0"8100c002-0001-0002-0003-000044556677&q= uot;);

Ah OK, I see what you mean. The = boards should be using the SoC object only and
not directly any o= f its sub devices, correct?

=C2=A0

What means this value? Don't you want to be able to set it from command=
line?
The first word 0x02c00081 is the identifying wor= d for the H3 SoC in the SID data.
After that come the per-device = unique specific bytes. This is documented at the end of this page in 'C= urrently known SID's' on the lin= ux-sunxi.org Wiki:

The remaining parts of this value I simply made up without= any real meaning.
And yes, it would in fact make sense to have t= he user be able to override it from the command line.
It is used = by U-boot as an input for generating the MAC address. Linux also reads it, = but I did not investigate
how it us used there. I think I did mak= e a TODO of using a cmdline argument, but later forgot to actually implemen= t it.

Do you have a suggestion how to best provide= the command line argument? I do see '-device driver[,prop=3Dvalue]'= ;
is there in the --help for qemu-system-arm, but it looks like t= hat should be used by the user for adding PCI / USB devices?
=

>=C2=A0 =C2=A0 =C2=A0 =C2=A0/* Mark H3 object realized */
>=C2=A0 =C2=A0 =C2=A0 =C2=A0object_property_set_bool(OBJECT(s->h3), t= rue, "realized", &error_abort);
>=C2=A0 =C2=A0 =C2=A0 =C2=A0if (error_abort !=3D NULL) {
> diff --git a/hw/misc/allwinner-h3-sid.c b/hw/misc/allwinner-h3-sid.c > new file mode 100644
> index 0000000000..c472f2bcc6
> --- /dev/null
> +++ b/hw/misc/allwinner-h3-sid.c
> @@ -0,0 +1,179 @@
> +/*
> + * Allwinner H3 Security ID emulation
> + *
> + * Copyright (C) 2019 Niek Linnenbank <nieklinnenbank@gmail.com>
> + *
> + * This program is free software: you can redistribute it and/or modi= fy
> + * it under the terms of the GNU General Public License as published = by
> + * the Free Software Foundation, either version 2 of the License, or<= br> > + * (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful, > + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.=C2=A0 See the=
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License<= br> > + * along with this program.=C2=A0 If not, see <http://www.gnu.o= rg/licenses/>.
> + */
> +
> +#include "qemu/osdep.h"
> +#include "qemu/units.h"
> +#include "hw/sysbus.h"
> +#include "migration/vmstate.h"
> +#include "qemu/log.h"
> +#include "qemu/module.h"
> +#include "qemu/guest-random.h"
> +#include "qapi/error.h"
> +#include "hw/qdev-properties.h"
> +#include "hw/misc/allwinner-h3-sid.h"
> +#include "trace.h"
> +
> +/* SID register offsets */
> +enum {
> +=C2=A0 =C2=A0 REG_PRCTL =3D 0x40,=C2=A0 =C2=A0/* Control */
> +=C2=A0 =C2=A0 REG_RDKEY =3D 0x60,=C2=A0 =C2=A0/* Read Key */
> +};
> +
> +/* SID register flags */
> +enum {
> +=C2=A0 =C2=A0 REG_PRCTL_WRITE=C2=A0 =C2=A0=3D 0x0002, /* Unknown writ= e flag */
> +=C2=A0 =C2=A0 REG_PRCTL_OP_LOCK =3D 0xAC00, /* Lock operation */
> +};
> +
> +static uint64_t allwinner_h3_sid_read(void *opaque, hwaddr offset, > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 unsigned si= ze)
> +{
> +=C2=A0 =C2=A0 const AwH3SidState *s =3D (AwH3SidState *)opaque;
> +=C2=A0 =C2=A0 uint64_t val =3D 0;
> +
> +=C2=A0 =C2=A0 switch (offset) {
> +=C2=A0 =C2=A0 case REG_PRCTL:=C2=A0 =C2=A0 /* Control */
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 val =3D s->control;
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 break;
> +=C2=A0 =C2=A0 case REG_RDKEY:=C2=A0 =C2=A0 /* Read Key */
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 val =3D s->rdkey;
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 break;
> +=C2=A0 =C2=A0 default:
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 qemu_log_mask(LOG_GUEST_ERROR, "%s: = bad read offset 0x%04x\n",
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 __func__, (uint32_t)offset);
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 return 0;
> +=C2=A0 =C2=A0 }
> +
> +=C2=A0 =C2=A0 trace_allwinner_h3_sid_read(offset, val, size);
> +
> +=C2=A0 =C2=A0 return val;
> +}
> +
> +static void allwinner_h3_sid_write(void *opaque, hwaddr offset,
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0uint64_t val, unsig= ned size)
> +{
> +=C2=A0 =C2=A0 AwH3SidState *s =3D (AwH3SidState *)opaque;
> +
> +=C2=A0 =C2=A0 trace_allwinner_h3_sid_write(offset, val, size);
> +
> +=C2=A0 =C2=A0 switch (offset) {
> +=C2=A0 =C2=A0 case REG_PRCTL:=C2=A0 =C2=A0 /* Control */
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 s->control =3D val;
> +
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 if ((s->control & REG_PRCTL_OP_LOC= K) &&
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 (s->control & REG_PR= CTL_WRITE)) {
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 uint32_t id =3D s->contr= ol >> 16;
> +
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 if (id < sizeof(QemuUUID= )) {
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 s->rdkey = =3D (s->identifier.data[id]) |
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0 =C2=A0 =C2=A0(s->identifier.data[id + 1] << 8) | > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0 =C2=A0 =C2=A0(s->identifier.data[id + 2] << 16) | > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0 =C2=A0 =C2=A0(s->identifier.data[id + 3] << 24);
This is:

=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 s->= ;rdkey =3D ldl_le_p(&s->identifier.data[id]);

> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 }
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 }
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 s->control &=3D ~REG_PRCTL_WRITE;<= br> > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 break;
> +=C2=A0 =C2=A0 case REG_RDKEY:=C2=A0 =C2=A0 /* Read Key */

Read in a write()?

Maybe we can simply /* fall through */ LOG_GUEST_ERROR?

When writing this module, I looked at how U-Boot is using = the SID registers and simply
named the registers after the names = used by U-Boot. You can find this part in arch/arm/mach-sunxi/cpu_info.c:11= 1,
functions sun8i_efuse_read() and sunxi_get_sid(). U-Boot defin= es SIDC_RDKEY, so I named the register also rdkey.
I used the U-= Boot source because the Allwinner H3 datasheet does not document the regist= ers. Later I
found the SID page on the linux-sunxi wiki that I me= ntioned earlier, and they also describe the same register names:
<= div>

I suspect the information on this page is written based on the sou= rce code from the original SDK (which I did not study btw)
= =C2=A0

> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 break;
> +=C2=A0 =C2=A0 default:
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 qemu_log_mask(LOG_GUEST_ERROR, "%s: = bad write offset 0x%04x\n",
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 __func__, (uint32_t)offset);
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 break;
> +=C2=A0 =C2=A0 }
> +}
> +
> +static const MemoryRegionOps allwinner_h3_sid_ops =3D {
> +=C2=A0 =C2=A0 .read =3D allwinner_h3_sid_read,
> +=C2=A0 =C2=A0 .write =3D allwinner_h3_sid_write,
> +=C2=A0 =C2=A0 .endianness =3D DEVICE_NATIVE_ENDIAN,
> +=C2=A0 =C2=A0 .valid =3D {
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 .min_access_size =3D 4,
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 .max_access_size =3D 4,
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 .unaligned =3D false

'false' is the default value, maybe we can omit it?

Sure, I'll remove it.
=C2=A0

> +=C2=A0 =C2=A0 },
> +=C2=A0 =C2=A0 .impl.min_access_size =3D 4,
> +};
> +
> +static void allwinner_h3_sid_reset(DeviceState *dev)
> +{
> +=C2=A0 =C2=A0 AwH3SidState *s =3D AW_H3_SID(dev);
> +
> +=C2=A0 =C2=A0 /* Set default values for registers */
> +=C2=A0 =C2=A0 s->control =3D 0;
> +=C2=A0 =C2=A0 s->rdkey =3D 0;
> +}
> +
> +static void allwinner_h3_sid_realize(DeviceState *dev, Error **errp)<= br> > +{
> +}

If you don't need realize(), just remove it. However maybe we want to <= br> check if the identifier is null, either warn/abort or generate a random one= ?
OK, removing it!
=C2=A0

> +
> +static void allwinner_h3_sid_init(Object *obj)
> +{
> +=C2=A0 =C2=A0 SysBusDevice *sbd =3D SYS_BUS_DEVICE(obj);
> +=C2=A0 =C2=A0 AwH3SidState *s =3D AW_H3_SID(obj);
> +
> +=C2=A0 =C2=A0 /* Fill UUID with zeroes by default */
> +=C2=A0 =C2=A0 qemu_uuid_parse(UUID_NONE, &s->identifier);

AwH3SidState is zeroed just before this init() call. I think we don't <= br> need to zeroes the UUID again.

Ah OK, s= o you mean new objects are always zeroed. That makes it
much easi= er indeed. Thanks, I'll remove those lines.
=C2=A0
<= blockquote class=3D"gmail_quote" style=3D"margin:0px 0px 0px 0.8ex;border-l= eft:1px solid rgb(204,204,204);padding-left:1ex">
> +
> +=C2=A0 =C2=A0 /* Memory mapping */
> +=C2=A0 =C2=A0 memory_region_init_io(&s->iomem, OBJECT(s), &= ;allwinner_h3_sid_ops, s,
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0 =C2=A0 TYPE_AW_H3_SID, 1 * KiB);
> +=C2=A0 =C2=A0 sysbus_init_mmio(sbd, &s->iomem);
> +}
> +
> +static Property allwinner_h3_sid_properties[] =3D {
> +=C2=A0 =C2=A0 DEFINE_PROP_UUID_NODEFAULT("identifier", AwH3= SidState, identifier),
> +=C2=A0 =C2=A0 DEFINE_PROP_END_OF_LIST()
> +};
> +
> +static const VMStateDescription allwinner_h3_sid_vmstate =3D {
> +=C2=A0 =C2=A0 .name =3D "allwinner-h3-sid",
> +=C2=A0 =C2=A0 .version_id =3D 1,
> +=C2=A0 =C2=A0 .minimum_version_id =3D 1,
> +=C2=A0 =C2=A0 .fields =3D (VMStateField[]) {
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 VMSTATE_UINT32(control, AwH3SidState), > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 VMSTATE_UINT32(rdkey, AwH3SidState),
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 VMSTATE_END_OF_LIST()
> +=C2=A0 =C2=A0 }
> +};
> +
> +static void allwinner_h3_sid_class_init(ObjectClass *klass, void *dat= a)
> +{
> +=C2=A0 =C2=A0 DeviceClass *dc =3D DEVICE_CLASS(klass);
> +
> +=C2=A0 =C2=A0 dc->reset =3D allwinner_h3_sid_reset;
> +=C2=A0 =C2=A0 dc->realize =3D allwinner_h3_sid_realize;
> +=C2=A0 =C2=A0 dc->vmsd =3D &allwinner_h3_sid_vmstate;
> +=C2=A0 =C2=A0 dc->props =3D allwinner_h3_sid_properties;
> +}
> +
> +static const TypeInfo allwinner_h3_sid_info =3D {
> +=C2=A0 =C2=A0 .name=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =3D TYPE_AW_H3_= SID,
> +=C2=A0 =C2=A0 .parent=C2=A0 =C2=A0 =C2=A0 =C2=A0 =3D TYPE_SYS_BUS_DEV= ICE,
> +=C2=A0 =C2=A0 .instance_init =3D allwinner_h3_sid_init,
> +=C2=A0 =C2=A0 .instance_size =3D sizeof(AwH3SidState),
> +=C2=A0 =C2=A0 .class_init=C2=A0 =C2=A0 =3D allwinner_h3_sid_class_ini= t,
> +};
> +
> +static void allwinner_h3_sid_register(void)
> +{
> +=C2=A0 =C2=A0 type_register_static(&allwinner_h3_sid_info);
> +}
> +
> +type_init(allwinner_h3_sid_register)
> diff --git a/hw/misc/Makefile.objs b/hw/misc/Makefile.objs
> index c4ca2ed689..f3620eee4e 100644
> --- a/hw/misc/Makefile.objs
> +++ b/hw/misc/Makefile.objs
> @@ -31,6 +31,7 @@ common-obj-$(CONFIG_IVSHMEM_DEVICE) +=3D ivshmem.o >=C2=A0 =C2=A0common-obj-$(CONFIG_ALLWINNER_H3) +=3D allwinner-h3-clk.o<= br> >=C2=A0 =C2=A0obj-$(CONFIG_ALLWINNER_H3) +=3D allwinner-h3-cpucfg.o
>=C2=A0 =C2=A0common-obj-$(CONFIG_ALLWINNER_H3) +=3D allwinner-h3-syscon= .o
> +common-obj-$(CONFIG_ALLWINNER_H3) +=3D allwinner-h3-sid.o
>=C2=A0 =C2=A0common-obj-$(CONFIG_REALVIEW) +=3D arm_sysctl.o
>=C2=A0 =C2=A0common-obj-$(CONFIG_NSERIES) +=3D cbus.o
>=C2=A0 =C2=A0common-obj-$(CONFIG_ECCMEMCTL) +=3D eccmemctl.o
> diff --git a/hw/misc/trace-events b/hw/misc/trace-events
> index b93089d010..a777844ca3 100644
> --- a/hw/misc/trace-events
> +++ b/hw/misc/trace-events
> @@ -5,6 +5,10 @@ allwinner_h3_cpucfg_cpu_reset(uint8_t cpu_id, uint32_= t reset_addr) "H3-CPUCFG: c
>=C2=A0 =C2=A0allwinner_h3_cpucfg_read(uint64_t offset, uint64_t data, u= nsigned size) "H3-CPUCFG: read: offset 0x%" PRIx64 " data 0x= %" PRIx64 " size %" PRIu32
>=C2=A0 =C2=A0allwinner_h3_cpucfg_write(uint64_t offset, uint64_t data, = unsigned size) "H3-CPUCFG: write: offset 0x%" PRIx64 " data = 0x%" PRIx64 " size %" PRIu32
>=C2=A0 =C2=A0
> +# allwinner-h3-sid.c
> +allwinner_h3_sid_read(uint64_t offset, uint64_t data, unsigned size) = "H3-SID: read: offset 0x%" PRIx64 " data 0x%" PRIx64 &q= uot; size %" PRIu32
> +allwinner_h3_sid_write(uint64_t offset, uint64_t data, unsigned size)= "H3-SID: write: offset 0x%" PRIx64 " data 0x%" PRIx64 = " size %" PRIu32
> +
>=C2=A0 =C2=A0# eccmemctl.c
>=C2=A0 =C2=A0ecc_mem_writel_mer(uint32_t val) "Write memory enable= 0x%08x"
>=C2=A0 =C2=A0ecc_mem_writel_mdr(uint32_t val) "Write memory delay = 0x%08x"
>


Regards,
Niek
--
Ni= ek Linnenbank

--000000000000a170b4059a0094dc-- From MAILER-DAEMON Wed Dec 18 16:02:27 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1ihgSh-0001L0-K7 for mharc-qemu-arm@gnu.org; Wed, 18 Dec 2019 16:02:27 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:37796) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ihgSd-0001Gl-60 for qemu-arm@nongnu.org; Wed, 18 Dec 2019 16:02:26 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ihgSX-0006uW-7m for qemu-arm@nongnu.org; Wed, 18 Dec 2019 16:02:19 -0500 Received: from mail-il1-x143.google.com ([2607:f8b0:4864:20::143]:39167) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ihgSV-0006dK-23; Wed, 18 Dec 2019 16:02:16 -0500 Received: by mail-il1-x143.google.com with SMTP id x5so2914653ila.6; Wed, 18 Dec 2019 13:02:08 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=ZHGtntswR8W4mR3O18kwKAC9ejq3lYrTZEGigFPxDeI=; b=aIMhcUuwnOSRH7aLtb/p3PcYjjrEgbuqUXOC+Mg9eopCE6A5B3tQe4R594GTjYvJEy T5OzfzkxnQZwlx0Zq6z18tHfH0wpcir65t3cIdmiN8wyFyxxD/RTcTOjot0r7cxpKuwd Uu6bT9qafpeNaLNuwtEKhBo4gFpSe8ulYIHiZWTKOv6vqrCQvSs1VL7hCtrXGhHbG9oO oS1oLnrVNxXzsprcS6u8iEAnm7a3S5Gjb1bhq92TDsuCjrogTOfp4sIv9c+LP0K+Neo7 2h1dlv49e/1qgKzy1Sx7SrFnP5cItyA5ekE7K6s2NBkIxJqKqOBiZytF5ZyRZuhkI5wd Apgw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=ZHGtntswR8W4mR3O18kwKAC9ejq3lYrTZEGigFPxDeI=; b=NUKDFlKLqs9UQW7l4+5MsoqNbK7T2weMRebb0Pr8p4dMs2eEN33BhHUQi/ZrSKa+fv pqtKMTEcbLNmg3XLWraa3YbMElQIuGJKixAtn6gRv4ne8/DjdM8Ti9sDqrNfKWuo55W4 4wgarpeoUpqTXyqirc45a490KhbxH5FuYN+vEMRD7fJBbSs3lUZPMImyXGEjUc54+Wq0 LZ8HACxERL41IOflEgHGzekQLdphAYkTd9PnD+sRixm+V7Rtgm6AC4HJfSi6zDbKWlh+ BPIGYElWLDFa+2H44hL4VkzrjzawWn+32rl/5PbejgXkfbNyKiqXXKMLjZSLCr/npplU ghTw== X-Gm-Message-State: APjAAAVCKGFZdnMN6qw1ELV9miRvnFB55BFNwOIME7pnDN6hIbTe+kDR yNYwmdAK1P1tMC+yKkqg/e7QsAavFYoZ1T4Zetg= X-Google-Smtp-Source: APXvYqzEdHEXc8x71A7Lpg+O8/J2t/UQpCJw7Pvw0MsGMq9LcLw2529wHUXGewWV/tUwdU/h2fs1Tloh6y3sII83o9I= X-Received: by 2002:a92:5a45:: with SMTP id o66mr3672544ilb.67.1576702925654; Wed, 18 Dec 2019 13:02:05 -0800 (PST) MIME-Version: 1.0 References: <20191216233519.29030-1-nieklinnenbank@gmail.com> <20191216233519.29030-7-nieklinnenbank@gmail.com> <19e4f2ac-6067-f61f-f340-108545fb0f02@linaro.org> In-Reply-To: <19e4f2ac-6067-f61f-f340-108545fb0f02@linaro.org> From: Niek Linnenbank Date: Wed, 18 Dec 2019 22:01:54 +0100 Message-ID: Subject: Re: [PATCH v2 06/10] arm/arm-powerctl: rebuild hflags after setting CP15 bits in arm_set_cpu_on() To: Richard Henderson Cc: Peter Maydell , qemu-arm , =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= , QEMU Developers Content-Type: multipart/alternative; boundary="000000000000cccf81059a00c1c9" X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Received-From: 2607:f8b0:4864:20::143 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 18 Dec 2019 21:02:26 -0000 --000000000000cccf81059a00c1c9 Content-Type: text/plain; charset="UTF-8" Hello Richard, On Tue, Dec 17, 2019 at 5:41 PM Richard Henderson < richard.henderson@linaro.org> wrote: > On 12/17/19 6:12 AM, Peter Maydell wrote: > > Cc'ing Richard : this is one for you I think... (surely we > > need to rebuild the hflags from scratch when we power up > > a CPU anyway?) > > We do compute hflags from scratch in reset. > > It has also turned out that there were a few board models that poked at the > contents of the cpu and needed special help. Some of that I would imagine > would be fixed properly with the multi-phase reset patches, where we could > rebuild hflags when *leaving* reset. > > In arm_set_cpu_on_async_work, we start by resetting the cpu and then start > poking at the contents of some system registers. So, yes, we do need to > rebuild after doing that. Also, I'm not sure how this function should fit > into > the multi-phase reset future. > Great, thanks a lot for confirming and clarifying this! You mention the multi-phase reset feature, is that going to replace the arm_set_cpu_on() functionality? Currently I chose to use this function for implementing the CPU configuration module in the Allwinner H3 Soc. U-Boot needs the CPU configuration module to provide PSCI which Linux uses to bring up the secondary cores. And basically the CPU configuration module needs something to let the secondary CPUs power on, reset and start executing at some address. Would you suggest to keep using arm_set_cpu_on() for this, or should I instead use a different function? Regards, Niek > > So: > > >> On Tue, Dec 17, 2019 at 12:36 AM Niek Linnenbank < > nieklinnenbank@gmail.com> wrote: > >>> > >>> After setting CP15 bits in arm_set_cpu_on() the cached hflags must > >>> be rebuild to reflect the changed processor state. Without rebuilding, > >>> the cached hflags would be inconsistent until the next call to > >>> arm_rebuild_hflags(). When QEMU is compiled with debugging enabled > >>> (--enable-debug), this problem is captured shortly after the first > >>> call to arm_set_cpu_on() for CPUs running in ARM 32-bit non-secure > mode: > >>> > >>> qemu-system-arm: target/arm/helper.c:11359: cpu_get_tb_cpu_state: > >>> Assertion `flags == rebuild_hflags_internal(env)' failed. > >>> Aborted (core dumped) > >>> > >>> Fixes: 0c7f8c43daf65 > >>> Signed-off-by: Niek Linnenbank > >>> --- > >>> target/arm/arm-powerctl.c | 3 +++ > >>> 1 file changed, 3 insertions(+) > >>> > >>> diff --git a/target/arm/arm-powerctl.c b/target/arm/arm-powerctl.c > >>> index b064513d44..b75f813b40 100644 > >>> --- a/target/arm/arm-powerctl.c > >>> +++ b/target/arm/arm-powerctl.c > >>> @@ -127,6 +127,9 @@ static void arm_set_cpu_on_async_work(CPUState > *target_cpu_state, > >>> target_cpu->env.regs[0] = info->context_id; > >>> } > >>> > >>> + /* CP15 update requires rebuilding hflags */ > >>> + arm_rebuild_hflags(&target_cpu->env); > >>> + > >>> /* Start the new CPU at the requested address */ > >>> cpu_set_pc(target_cpu_state, info->entry); > >>> > > Reviewed-by: Richard Henderson > > > r~ > -- Niek Linnenbank --000000000000cccf81059a00c1c9 Content-Type: text/html; charset="UTF-8" Content-Transfer-Encoding: quoted-printable
Hello Richard,

On Tue, Dec 17, 2019 at 5:41 PM Ric= hard Henderson <richard.= henderson@linaro.org> wrote:
On 12/17/19 6:12 AM, Peter Maydell wrote:
> Cc'ing Richard : this is one for you I think... (surely we
> need to rebuild the hflags from scratch when we power up
> a CPU anyway?)

We do compute hflags from scratch in reset.

It has also turned out that there were a few board models that poked at the=
contents of the cpu and needed special help.=C2=A0 Some of that I would ima= gine
would be fixed properly with the multi-phase reset patches, where we could<= br> rebuild hflags when *leaving* reset.

In arm_set_cpu_on_async_work, we start by resetting the cpu and then start<= br> poking at the contents of some system registers.=C2=A0 So, yes, we do need = to
rebuild after doing that.=C2=A0 Also, I'm not sure how this function sh= ould fit into
the multi-phase reset future.

Great, th= anks a lot for confirming and clarifying this!
You mention the mu= lti-phase reset feature, is that going to replace the arm_set_cpu_on() func= tionality?
Currently I chose to use this function for implementin= g the CPU configuration module in the Allwinner H3 Soc.
U-Bo= ot needs the CPU configuration module to provide PSCI which Linux uses to b= ring up the secondary cores.
And basically the CPU configur= ation module needs something to let the secondary CPUs power on, reset and = start executing at some address.

Would you suggest= to keep using arm_set_cpu_on() for this, or should I instead use a differe= nt function?

Regards,
Niek
=

So:

>> On Tue, Dec 17, 2019 at 12:36 AM Niek Linnenbank <nieklinnenbank@gmail.com> wrote:
>>>
>>> After setting CP15 bits in arm_set_cpu_on() the cached hflags = must
>>> be rebuild to reflect the changed processor state. Without reb= uilding,
>>> the cached hflags would be inconsistent until the next call to=
>>> arm_rebuild_hflags(). When QEMU is compiled with debugging ena= bled
>>> (--enable-debug), this problem is captured shortly after the f= irst
>>> call to arm_set_cpu_on() for CPUs running in ARM 32-bit non-se= cure mode:
>>>
>>>=C2=A0 =C2=A0qemu-system-arm: target/arm/helper.c:11359: cpu_ge= t_tb_cpu_state:
>>>=C2=A0 =C2=A0Assertion `flags =3D=3D rebuild_hflags_internal(en= v)' failed.
>>>=C2=A0 =C2=A0Aborted (core dumped)
>>>
>>> Fixes: 0c7f8c43daf65
>>> Signed-off-by: Niek Linnenbank <
nieklinnenbank@gmail.com>
>>> ---
>>>=C2=A0 target/arm/arm-powerctl.c | 3 +++
>>>=C2=A0 1 file changed, 3 insertions(+)
>>>
>>> diff --git a/target/arm/arm-powerctl.c b/target/arm/arm-powerc= tl.c
>>> index b064513d44..b75f813b40 100644
>>> --- a/target/arm/arm-powerctl.c
>>> +++ b/target/arm/arm-powerctl.c
>>> @@ -127,6 +127,9 @@ static void arm_set_cpu_on_async_work(CPUS= tate *target_cpu_state,
>>>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 target_cpu->env.regs[0] = =3D info->context_id;
>>>=C2=A0 =C2=A0 =C2=A0 }
>>>
>>> +=C2=A0 =C2=A0 /* CP15 update requires rebuilding hflags */ >>> +=C2=A0 =C2=A0 arm_rebuild_hflags(&target_cpu->env); >>> +
>>>=C2=A0 =C2=A0 =C2=A0 /* Start the new CPU at the requested addr= ess */
>>>=C2=A0 =C2=A0 =C2=A0 cpu_set_pc(target_cpu_state, info->entr= y);
>>>

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>


r~


--
Niek Linnenbank

--000000000000cccf81059a00c1c9-- From MAILER-DAEMON Wed Dec 18 16:20:42 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1ihgkM-0003zB-Ba for mharc-qemu-arm@gnu.org; Wed, 18 Dec 2019 16:20:42 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:47606) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ihgkI-0003v6-1w for qemu-arm@nongnu.org; Wed, 18 Dec 2019 16:20:39 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ihgkF-0008M7-GM for qemu-arm@nongnu.org; Wed, 18 Dec 2019 16:20:37 -0500 Received: from mail-io1-xd43.google.com ([2607:f8b0:4864:20::d43]:32812) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ihgk4-0008FG-8t; Wed, 18 Dec 2019 16:20:24 -0500 Received: by mail-io1-xd43.google.com with SMTP id z8so3544132ioh.0; Wed, 18 Dec 2019 13:20:22 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=wiaxJVCuSNQJMhOQMKQIbuNI/IgcNMi1SSwkGVjCgKE=; b=A2TmBwhJbdSS7XeABnir6EeXy+cEKIX/OERrZokc2j1UINXvRkqj9JBF7V+Ol17KPt QT8HBBTiq+UJrBdmxW5YUyIlJpw9/loh/sduyHwclcQ6VbkeD6UlTqXRyY9gJ8VkVztD 9XgYaw3jiyntgKK3RZpl8kzD2XWJveJuDLDk6fWpE8jGAdQkih2wGC6cndbJL6gcv7Ev QPLCCgJcV6W4fIkKBtXs6/XZlbCpPqopz9e+l0JJdwi/0LwAQT0wRo7ItzIA2t+bUIDE mwN4hUQa7A9to1TMfaJ2wTQhN09/Sj7KXXilDn5WA0WkiCCTdie/kz3pm9BSGlNShyEZ kIdw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=wiaxJVCuSNQJMhOQMKQIbuNI/IgcNMi1SSwkGVjCgKE=; b=NEiZ6ElNGu1u5/SKzyFgfECKxO4ufB7Ld4lwx/pViTiV84ItB3w7CCyM2QEABuNIdI zkruwngE+ZuGgtpXwETUzVM3AV5trvY+45Y4br8zzkmvEy0NBKtL3jYAVnkKqOZZRLve H8sEeCRWsSeoMXeyfA4ldFhbFow54smEd8Vmd9KMA1EHjpaLmWs4djkTxCeXZuK6+lqO aZUymWEpTwNP7qlMt5vC6zP7x2/owrm19PieciRIqebki0w6/+f5EqosYQmFfooZZLP3 Ql3qfq0rOOuJvVCGY+6hETrkwkrW7NEl0eAQHMv6ypuiicLjohuVjaPXEWZmhM4Yivyr 0yLw== X-Gm-Message-State: APjAAAXt008a7aRfuIGRAk7Scpk7EYi9mReyYVljdN6JiGpNXR4WJf7S ATkCuJlS8LG6gnzJhwtfRNigXW8r8EENI1lqmXc= X-Google-Smtp-Source: APXvYqyNzw0K/A6R8YcBkWDBWHGY8ZYQtiho3Ae4SHcNyav8OUVBuySIcxTLqHJD8BHPOlBEX1WiF6YS36eGnDqBlWA= X-Received: by 2002:a6b:6f01:: with SMTP id k1mr3371292ioc.28.1576704021596; Wed, 18 Dec 2019 13:20:21 -0800 (PST) MIME-Version: 1.0 References: <20191217182730.943-1-f4bug@amsat.org> <20191217182730.943-2-f4bug@amsat.org> In-Reply-To: <20191217182730.943-2-f4bug@amsat.org> From: Niek Linnenbank Date: Wed, 18 Dec 2019 22:20:10 +0100 Message-ID: Subject: Re: [PATCH 1/5] tests/boot_linux_console: Add a quick test for the OrangePi PC board To: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= Cc: QEMU Developers , Guenter Roeck , Cleber Rosa , Peter Maydell , qemu-arm Content-Type: multipart/alternative; boundary="0000000000001f929d059a010365" X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::d43 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 18 Dec 2019 21:20:40 -0000 --0000000000001f929d059a010365 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Hey Philippe, Super!! Fantastic, now we can automatically test the H3 based boards and use that to verify they keep working as expected when changing the code= . Great, I'm going to use these tests also from now on (previously I had some small bash scripts). This quick test is working fine for me, so: Tested-by: Niek Linnenbank Regards, Niek On Tue, Dec 17, 2019 at 7:27 PM Philippe Mathieu-Daud=C3=A9 wrote: > This test boots a Linux kernel on a OrangePi PC board and verify > the serial output is working. > > The kernel image and DeviceTree blob are built by the Raspbian > project (based on Debian): > https://www.raspbian.org/RaspbianImages > > If ARM is a target being built, "make check-acceptance" will > automatically include this test by the use of the "arch:arm" tags. > > Alternatively, this test can be run using: > > $ make check-venv > $ ./tests/venv/bin/avocado --show=3Dconsole,app run -t machine:orangepi= -pc > tests/acceptance/boot_linux_console.py > JOB ID : 2e4d15eceb13c33672af406f08171e6e9de1414a > JOB LOG : ~/job-results/job-2019-12-17T05.46-2e4d15e/job.log > (1/1) > tests/acceptance/boot_linux_console.py:BootLinuxConsole.test_arm_orangepi= : > console: Uncompressing Linux... done, booting the kernel. > console: Booting Linux on physical CPU 0x0 > console: Linux version 4.20.7-sunxi (root@armbian.com) (gcc version > 7.2.1 20171011 (Linaro GCC 7.2-2017.11)) #5.75 SMP Fri Feb 8 09:02:10 CET > 2019 > console: CPU: ARMv7 Processor [410fc075] revision 5 (ARMv7), cr=3D50c53= 87d > console: CPU: div instructions available: patching division code > console: CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing > instruction cache > console: OF: fdt: Machine model: Xunlong Orange Pi PC > console: Memory policy: Data cache writealloc > console: OF: reserved mem: failed to allocate memory for node > 'cma@4a000000' > console: cma: Failed to reserve 128 MiB > console: psci: probing for conduit method from DT. > console: psci: PSCIv0.2 detected in firmware. > console: psci: Using standard PSCI v0.2 function IDs > console: psci: Trusted OS migration not required > console: random: get_random_bytes called from start_kernel+0x8d/0x3c2 > with crng_init=3D0 > console: percpu: Embedded 18 pages/cpu @(ptrval) s41228 r8192 d24308 > u73728 > console: Built 1 zonelists, mobility grouping on. Total pages: 32480 > console: Kernel command line: printk.time=3D0 console=3DttyS0,115200 > PASS (8.59 s) > JOB TIME : 8.81 s > > Signed-off-by: Philippe Mathieu-Daud=C3=A9 > --- > tests/acceptance/boot_linux_console.py | 26 ++++++++++++++++++++++++++ > 1 file changed, 26 insertions(+) > > diff --git a/tests/acceptance/boot_linux_console.py > b/tests/acceptance/boot_linux_console.py > index 7e41cebd47..820239e439 100644 > --- a/tests/acceptance/boot_linux_console.py > +++ b/tests/acceptance/boot_linux_console.py > @@ -411,6 +411,32 @@ class BootLinuxConsole(Test): > self.wait_for_console_pattern('Boot successful.') > # TODO user command, for now the uart is stuck > > + def test_arm_orangepi(self): > + """ > + :avocado: tags=3Darch:arm > + :avocado: tags=3Dmachine:orangepi-pc > + """ > + deb_url =3D ('https://apt.armbian.com/pool/main/l/' > + > 'linux-4.20.7-sunxi/linux-image-dev-sunxi_5.75_armhf.deb') > + deb_hash =3D '1334c29c44d984ffa05ed10de8c3361f33d78315' > + deb_path =3D self.fetch_asset(deb_url, asset_hash=3Ddeb_hash) > + kernel_path =3D self.extract_from_deb(deb_path, > + '/boot/vmlinuz-4.20.7-sunxi'= ) > + dtb_path =3D > '/usr/lib/linux-image-dev-sunxi/sun8i-h3-orangepi-pc.dtb' > + dtb_path =3D self.extract_from_deb(deb_path, dtb_path) > + > + self.vm.set_machine('orangepi-pc') > + self.vm.set_console() > + kernel_command_line =3D (self.KERNEL_COMMON_COMMAND_LINE + > + 'console=3DttyS0,115200n8 ' > + 'earlycon=3Duart,mmio32,0x1c28000') > + self.vm.add_args('-kernel', kernel_path, > + '-dtb', dtb_path, > + '-append', kernel_command_line) > + self.vm.launch() > + console_pattern =3D 'Kernel command line: %s' % kernel_command_l= ine > + self.wait_for_console_pattern(console_pattern) > + > def test_s390x_s390_ccw_virtio(self): > """ > :avocado: tags=3Darch:s390x > -- > 2.21.0 > > --=20 Niek Linnenbank --0000000000001f929d059a010365 Content-Type: text/html; charset="UTF-8" Content-Transfer-Encoding: quoted-printable
Hey Philippe,

Super!! Fantas= tic, now we can automatically test the H3 based boards
and us= e that to verify they keep working as expected when changing the code.

Great, I'm going to use these tests also from now = on (previously I had some small
bash scripts).

=
This quick test is working fine for me, so:

=
Tested-by: Niek Linnenbank <nieklinnenbank@gmail.com>

Regards,=
Niek



On Tue, Dec 17, 2019= at 7:27 PM Philippe Mathieu-Daud=C3=A9 <f4bug@amsat.org> wrote:
This test boots a Linux kernel on a OrangePi PC board an= d verify
the serial output is working.

The kernel image and DeviceTree blob are built by the Raspbian
project (based on Debian):
https://www.raspbian.org/RaspbianImages

If ARM is a target being built, "make check-acceptance" will
automatically include this test by the use of the "arch:arm" tags= .

Alternatively, this test can be run using:

=C2=A0 $ make check-venv
=C2=A0 $ ./tests/venv/bin/avocado --show=3Dconsole,app run -t machine:orang= epi-pc tests/acceptance/boot_linux_console.py
=C2=A0 JOB ID=C2=A0 =C2=A0 =C2=A0: 2e4d15eceb13c33672af406f08171e6e9de1414a=
=C2=A0 JOB LOG=C2=A0 =C2=A0 : ~/job-results/job-2019-12-17T05.46-2e4d15e/jo= b.log
=C2=A0 (1/1) tests/acceptance/boot_linux_console.py:BootLinuxConsole.test_a= rm_orangepi:
=C2=A0 console: Uncompressing Linux... done, booting the kernel.
=C2=A0 console: Booting Linux on physical CPU 0x0
=C2=A0 console: Linux version 4.20.7-sunxi (root@armbian.com) (gcc version 7.2.1 20171011 (L= inaro GCC 7.2-2017.11)) #5.75 SMP Fri Feb 8 09:02:10 CET 2019
=C2=A0 console: CPU: ARMv7 Processor [410fc075] revision 5 (ARMv7), cr=3D50= c5387d
=C2=A0 console: CPU: div instructions available: patching division code
=C2=A0 console: CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing inst= ruction cache
=C2=A0 console: OF: fdt: Machine model: Xunlong Orange Pi PC
=C2=A0 console: Memory policy: Data cache writealloc
=C2=A0 console: OF: reserved mem: failed to allocate memory for node 'c= ma@4a000000'
=C2=A0 console: cma: Failed to reserve 128 MiB
=C2=A0 console: psci: probing for conduit method from DT.
=C2=A0 console: psci: PSCIv0.2 detected in firmware.
=C2=A0 console: psci: Using standard PSCI v0.2 function IDs
=C2=A0 console: psci: Trusted OS migration not required
=C2=A0 console: random: get_random_bytes called from start_kernel+0x8d/0x3c= 2 with crng_init=3D0
=C2=A0 console: percpu: Embedded 18 pages/cpu @(ptrval) s41228 r8192 d24308= u73728
=C2=A0 console: Built 1 zonelists, mobility grouping on.=C2=A0 Total pages:= 32480
=C2=A0 console: Kernel command line: printk.time=3D0 console=3DttyS0,115200=
=C2=A0 PASS (8.59 s)
=C2=A0 JOB TIME=C2=A0 =C2=A0: 8.81 s

Signed-off-by: Philippe Mathieu-Daud=C3=A9 <f4bug@amsat.org>
---
=C2=A0tests/acceptance/boot_linux_console.py | 26 +++++++++++++++++++++++++= +
=C2=A01 file changed, 26 insertions(+)

diff --git a/tests/acceptance/boot_linux_console.py b/tests/acceptance/boot= _linux_console.py
index 7e41cebd47..820239e439 100644
--- a/tests/acceptance/boot_linux_console.py
+++ b/tests/acceptance/boot_linux_console.py
@@ -411,6 +411,32 @@ class BootLinuxConsole(Test):
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0self.wait_for_console_pattern('Boot s= uccessful.')
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0# TODO user command, for now the uart is = stuck

+=C2=A0 =C2=A0 def test_arm_orangepi(self):
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 """
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 :avocado: tags=3Darch:arm
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 :avocado: tags=3Dmachine:orangepi-pc
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 """
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 deb_url =3D ('https://apt.armbi= an.com/pool/main/l/'
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0'= linux-4.20.7-sunxi/linux-image-dev-sunxi_5.75_armhf.deb')
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 deb_hash =3D '1334c29c44d984ffa05ed10de8c3= 361f33d78315'
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 deb_path =3D self.fetch_asset(deb_url, asset_h= ash=3Ddeb_hash)
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 kernel_path =3D self.extract_from_deb(deb_path= ,
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 '/boot/vmlinuz-4.20.7-sunxi')
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 dtb_path =3D '/usr/lib/linux-image-dev-sun= xi/sun8i-h3-orangepi-pc.dtb'
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 dtb_path =3D self.extract_from_deb(deb_path, d= tb_path)
+
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 self.vm.set_machine('orangepi-pc')
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 self.vm.set_console()
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 kernel_command_line =3D (self.KERNEL_COMMON_CO= MMAND_LINE +
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0'console=3DttyS0,115200n8 ' +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0'earlycon=3Duart,mmio32,0x1c28000= ')
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 self.vm.add_args('-kernel', kernel_pat= h,
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0'-dtb', dtb_path,
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0'-append', kernel_command_line)
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 self.vm.launch()
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 console_pattern =3D 'Kernel command line: = %s' % kernel_command_line
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 self.wait_for_console_pattern(console_pattern)=
+
=C2=A0 =C2=A0 =C2=A0def test_s390x_s390_ccw_virtio(self):
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0"""
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0:avocado: tags=3Darch:s390x
--
2.21.0



--
Niek Linnenbank

--0000000000001f929d059a010365-- From MAILER-DAEMON Wed Dec 18 16:21:33 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1ihglB-0004kf-Oh for mharc-qemu-arm@gnu.org; Wed, 18 Dec 2019 16:21:33 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:49283) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ihgl8-0004hS-90 for qemu-arm@nongnu.org; Wed, 18 Dec 2019 16:21:32 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ihgl5-00010F-UP for qemu-arm@nongnu.org; Wed, 18 Dec 2019 16:21:30 -0500 Received: from mail-il1-x12b.google.com ([2607:f8b0:4864:20::12b]:32790) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ihgl0-0000tb-Vh; Wed, 18 Dec 2019 16:21:23 -0500 Received: by mail-il1-x12b.google.com with SMTP id v15so2979358iln.0; Wed, 18 Dec 2019 13:21:22 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=eYOQYD7N468B9qLiuc+fIol2HVdnn3O8hnxJaHLAR74=; b=q79xBpfa6sMS3V6cd4FV5Gr3IhTdrdVLHJ9ywxwepUVH3mk7lAwFjgHSA2RiLttoLb al87Mf00mz2U0HtNnIZkIYxdGzGXaRUXtti65ohi5muYPWEMgIoKdCHSV0UtR/8QrUQx F7SIIlWLmPZBsD/SVSyGxXO16CRvQJzNiOZ30fpW1q1oj0AxXqOwSDbKeDwJVR9Tm7p/ noasGN4FxAiYa5ptWdfMzQSkHrohaMqB0pvv64R+9dNOmIz7q+arvN8Pcpb+pFUBXYKj fsBZvNxTsmgmPwU73FMEJkj32fVtN+X8Y3p5fcNPr/op6wpFEII+zbwwYKcskpjAgLuB LpbQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=eYOQYD7N468B9qLiuc+fIol2HVdnn3O8hnxJaHLAR74=; b=RKa86a+ol+KVhR/qPSpklfnX6xBf4iIvLkJhdzNI7C30e+gwAP7Be6pA5sdf7mbE+A G7h1FT9R9jlI3vjsAVpXbOY/VWAmRi5SQ9zMJesvDP8rJPewJw6BPXxPlLuizds8ra5D /PYxyUC86/5qImpS44fNaRrd9D9y1pUNxTMbtB1p4Ju3lj3t4OkfpD8cuuntECvcH8Qz hRLrvG/oDXsg8nI4EzME+CzF8M5s+KikoACWnM1ssGb0EnbcXCIERyS5d7GpJAk9W9n4 2cXrwyG3y5nbi0o++kry0OPqGBfa0+1GtjMNIxBLgarnI9CMB0cgQWzGLTXbzggj3a7D CqWA== X-Gm-Message-State: APjAAAX+h8iDJWBK80GW+D/8q9tO30q2jjNhlbnP3t+HIYy5PXepgWjT 6ATjCz8L6snlUe0d1lyCBi+u8NBxTol/QKvuZ7U= X-Google-Smtp-Source: APXvYqzrtrtEHZP/g8KDI3c8WeSDu5eweQ24GxMBopYnuGgnXkdZnv3ACKG/q5U9LqMinHJbVb4yxYg0xxpAEDeO5f4= X-Received: by 2002:a92:a103:: with SMTP id v3mr3372445ili.265.1576704082031; Wed, 18 Dec 2019 13:21:22 -0800 (PST) MIME-Version: 1.0 References: <20191217182730.943-1-f4bug@amsat.org> <20191217182730.943-3-f4bug@amsat.org> In-Reply-To: <20191217182730.943-3-f4bug@amsat.org> From: Niek Linnenbank Date: Wed, 18 Dec 2019 22:21:11 +0100 Message-ID: Subject: Re: [PATCH 2/5] tests/boot_linux_console: Add initrd test for the Orange Pi PC board To: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= Cc: QEMU Developers , Guenter Roeck , Cleber Rosa , Peter Maydell , qemu-arm , =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= Content-Type: multipart/alternative; boundary="000000000000b9bbe2059a010660" X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::12b X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 18 Dec 2019 21:21:32 -0000 --000000000000b9bbe2059a010660 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable This one also works fine on my host (Ubuntu 18.04 LTS): Tested-by: Niek Linnenbank On Tue, Dec 17, 2019 at 7:27 PM Philippe Mathieu-Daud=C3=A9 wrote: > This test boots a Linux kernel on a OrangePi PC board and verify > the serial output is working. > > The kernel image and DeviceTree blob are built by the Raspbian > project (based on Debian): > https://www.raspbian.org/RaspbianImages > > The cpio image used comes from the linux-build-test project: > https://github.com/groeck/linux-build-test > > If ARM is a target being built, "make check-acceptance" will > automatically include this test by the use of the "arch:arm" tags. > > Alternatively, this test can be run using: > > $ avocado --show=3Dconsole run -t machine:orangepi-pc > tests/acceptance/boot_linux_console.py > console: Uncompressing Linux... done, booting the kernel. > console: Booting Linux on physical CPU 0x0 > console: Linux version 4.20.7-sunxi (root@armbian.com) (gcc version > 7.2.1 20171011 (Linaro GCC 7.2-2017.11)) #5.75 SMP Fri Feb 8 09:02:10 CET > 2019 > console: CPU: ARMv7 Processor [410fc075] revision 5 (ARMv7), cr=3D50c53= 87d > console: CPU: div instructions available: patching division code > console: CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing > instruction cache > console: OF: fdt: Machine model: Xunlong Orange Pi PC > [...] > console: Trying to unpack rootfs image as initramfs... > console: Freeing initrd memory: 3256K > console: Freeing unused kernel memory: 1024K > console: Run /init as init process > console: mount: mounting devtmpfs on /dev failed: Device or resource bu= sy > console: Starting logging: OK > console: Initializing random number generator... random: dd: > uninitialized urandom read (512 bytes read) > console: done. > console: Starting network: OK > console: Found console ttyS0 > console: Linux version 4.20.7-sunxi (root@armbian.com) (gcc version > 7.2.1 20171011 (Linaro GCC 7.2-2017.11)) #5.75 SMP Fri Feb 8 09:02:10 CET > 2019 > console: Boot successful. > console: cat /proc/cpuinfo > console: / # cat /proc/cpuinfo > console: processor : 0 > console: model name : ARMv7 Processor rev 5 (v7l) > console: BogoMIPS : 125.00 > console: Features : half thumb fastmult vfp edsp neon vfpv3 tls > vfpv4 idiva idivt vfpd32 lpae evtstrm > console: CPU implementer : 0x41 > console: CPU architecture: 7 > console: CPU variant : 0x0 > console: CPU part : 0xc07 > console: CPU revision : 5 > [...] > console: processor : 3 > console: model name : ARMv7 Processor rev 5 (v7l) > console: BogoMIPS : 125.00 > console: Features : half thumb fastmult vfp edsp neon vfpv3 tls > vfpv4 idiva idivt vfpd32 lpae evtstrm > console: CPU implementer : 0x41 > console: CPU architecture: 7 > console: CPU variant : 0x0 > console: CPU part : 0xc07 > console: CPU revision : 5 > console: Hardware : Allwinner sun8i Family > console: Revision : 0000 > console: Serial : 0000000000000000 > console: cat /proc/iomem > console: / # cat /proc/iomem > console: 01000000-010fffff : clock@1000000 > console: 01c00000-01c00fff : system-control@1c00000 > console: 01c02000-01c02fff : dma-controller@1c02000 > [...] > console: reboot > console: / # reboot > console: / # Found console ttyS0 > console: Stopping network: OK > console: hrtimer: interrupt took 21852064 ns > console: Saving random seed... random: dd: uninitialized urandom read > (512 bytes read) > console: done. > console: Stopping logging: OK > console: umount: devtmpfs busy - remounted read-only > console: umount: can't unmount /: Invalid argument > console: The system is going down NOW! > console: Sent SIGTERM to all processes > console: Sent SIGKILL to all processes > console: Requesting system reboot > console: reboot: Restarting system > PASS (48.32 s) > JOB TIME : 49.16 s > > Signed-off-by: Philippe Mathieu-Daud=C3=A9 > --- > tests/acceptance/boot_linux_console.py | 41 ++++++++++++++++++++++++++ > 1 file changed, 41 insertions(+) > > diff --git a/tests/acceptance/boot_linux_console.py > b/tests/acceptance/boot_linux_console.py > index 820239e439..daabd47404 100644 > --- a/tests/acceptance/boot_linux_console.py > +++ b/tests/acceptance/boot_linux_console.py > @@ -437,6 +437,47 @@ class BootLinuxConsole(Test): > console_pattern =3D 'Kernel command line: %s' % kernel_command_l= ine > self.wait_for_console_pattern(console_pattern) > > + def test_arm_orangepi_initrd(self): > + """ > + :avocado: tags=3Darch:arm > + :avocado: tags=3Dmachine:orangepi-pc > + """ > + deb_url =3D ('https://apt.armbian.com/pool/main/l/' > + > 'linux-4.20.7-sunxi/linux-image-dev-sunxi_5.75_armhf.deb') > + deb_hash =3D '1334c29c44d984ffa05ed10de8c3361f33d78315' > + deb_path =3D self.fetch_asset(deb_url, asset_hash=3Ddeb_hash) > + kernel_path =3D self.extract_from_deb(deb_path, > + '/boot/vmlinuz-4.20.7-sunxi'= ) > + dtb_path =3D > '/usr/lib/linux-image-dev-sunxi/sun8i-h3-orangepi-pc.dtb' > + dtb_path =3D self.extract_from_deb(deb_path, dtb_path) > + initrd_url =3D ('https://github.com/groeck/linux-build-test/raw/= ' > + '2eb0a73b5d5a28df3170c546ddaaa9757e1e0848/rootfs/' > + 'arm/rootfs-armv7a.cpio.gz') > + initrd_hash =3D '604b2e45cdf35045846b8bbfbf2129b1891bdc9c' > + initrd_path_gz =3D self.fetch_asset(initrd_url, > asset_hash=3Dinitrd_hash) > + initrd_path =3D os.path.join(self.workdir, 'rootfs.cpio') > + archive.gzip_uncompress(initrd_path_gz, initrd_path) > + > + self.vm.set_machine('orangepi-pc') > + self.vm.set_console() > + kernel_command_line =3D (self.KERNEL_COMMON_COMMAND_LINE + > + 'console=3DttyS0,115200 ' > + 'panic=3D-1 noreboot') > + self.vm.add_args('-kernel', kernel_path, > + '-dtb', dtb_path, > + '-initrd', initrd_path, > + '-append', kernel_command_line, > + '-no-reboot') > + self.vm.launch() > + self.wait_for_console_pattern('Boot successful.') > + > + exec_command_and_wait_for_pattern(self, 'cat /proc/cpuinfo', > + 'Allwinner sun8i Family'= ) > + exec_command_and_wait_for_pattern(self, 'cat /proc/iomem', > + 'system-control@1c00000'= ) > + exec_command_and_wait_for_pattern(self, 'reboot', > + 'reboot: Restarting > system') > + > def test_s390x_s390_ccw_virtio(self): > """ > :avocado: tags=3Darch:s390x > -- > 2.21.0 > > --=20 Niek Linnenbank --000000000000b9bbe2059a010660 Content-Type: text/html; charset="UTF-8" Content-Transfer-Encoding: quoted-printable
This one also works fine on my host (Ubuntu 18.04 LTS= ):

=C2=A0 Tested-by: Niek Linnenbank <nieklinnenbank@gmail.com>

On= Tue, Dec 17, 2019 at 7:27 PM Philippe Mathieu-Daud=C3=A9 <f4bug@amsat.org> wrote:
This test boots a Linux kernel on a Or= angePi PC board and verify
the serial output is working.

The kernel image and DeviceTree blob are built by the Raspbian
project (based on Debian):
https://www.raspbian.org/RaspbianImages

The cpio image used comes from the linux-build-test project:
https://github.com/groeck/linux-build-test

If ARM is a target being built, "make check-acceptance" will
automatically include this test by the use of the "arch:arm" tags= .

Alternatively, this test can be run using:

=C2=A0 $ avocado --show=3Dconsole run -t machine:orangepi-pc tests/acceptan= ce/boot_linux_console.py
=C2=A0 console: Uncompressing Linux... done, booting the kernel.
=C2=A0 console: Booting Linux on physical CPU 0x0
=C2=A0 console: Linux version 4.20.7-sunxi (root@armbian.com) (gcc version 7.2.1 20171011 (L= inaro GCC 7.2-2017.11)) #5.75 SMP Fri Feb 8 09:02:10 CET 2019
=C2=A0 console: CPU: ARMv7 Processor [410fc075] revision 5 (ARMv7), cr=3D50= c5387d
=C2=A0 console: CPU: div instructions available: patching division code
=C2=A0 console: CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing inst= ruction cache
=C2=A0 console: OF: fdt: Machine model: Xunlong Orange Pi PC
=C2=A0 [...]
=C2=A0 console: Trying to unpack rootfs image as initramfs...
=C2=A0 console: Freeing initrd memory: 3256K
=C2=A0 console: Freeing unused kernel memory: 1024K
=C2=A0 console: Run /init as init process
=C2=A0 console: mount: mounting devtmpfs on /dev failed: Device or resource= busy
=C2=A0 console: Starting logging: OK
=C2=A0 console: Initializing random number generator... random: dd: uniniti= alized urandom read (512 bytes read)
=C2=A0 console: done.
=C2=A0 console: Starting network: OK
=C2=A0 console: Found console ttyS0
=C2=A0 console: Linux version 4.20.7-sunxi (root@armbian.com) (gcc version 7.2.1 20171011 (L= inaro GCC 7.2-2017.11)) #5.75 SMP Fri Feb 8 09:02:10 CET 2019
=C2=A0 console: Boot successful.
=C2=A0 console: cat /proc/cpuinfo
=C2=A0 console: / # cat /proc/cpuinfo
=C2=A0 console: processor=C2=A0 =C2=A0 =C2=A0 : 0
=C2=A0 console: model name=C2=A0 =C2=A0 =C2=A0: ARMv7 Processor rev 5 (v7l)=
=C2=A0 console: BogoMIPS=C2=A0 =C2=A0 =C2=A0 =C2=A0: 125.00
=C2=A0 console: Features=C2=A0 =C2=A0 =C2=A0 =C2=A0: half thumb fastmult vf= p edsp neon vfpv3 tls vfpv4 idiva idivt vfpd32 lpae evtstrm
=C2=A0 console: CPU implementer=C2=A0 =C2=A0 =C2=A0 =C2=A0 : 0x41
=C2=A0 console: CPU architecture: 7
=C2=A0 console: CPU variant=C2=A0 =C2=A0 : 0x0
=C2=A0 console: CPU part=C2=A0 =C2=A0 =C2=A0 =C2=A0: 0xc07
=C2=A0 console: CPU revision=C2=A0 =C2=A0: 5
=C2=A0 [...]
=C2=A0 console: processor=C2=A0 =C2=A0 =C2=A0 : 3
=C2=A0 console: model name=C2=A0 =C2=A0 =C2=A0: ARMv7 Processor rev 5 (v7l)=
=C2=A0 console: BogoMIPS=C2=A0 =C2=A0 =C2=A0 =C2=A0: 125.00
=C2=A0 console: Features=C2=A0 =C2=A0 =C2=A0 =C2=A0: half thumb fastmult vf= p edsp neon vfpv3 tls vfpv4 idiva idivt vfpd32 lpae evtstrm
=C2=A0 console: CPU implementer=C2=A0 =C2=A0 =C2=A0 =C2=A0 : 0x41
=C2=A0 console: CPU architecture: 7
=C2=A0 console: CPU variant=C2=A0 =C2=A0 : 0x0
=C2=A0 console: CPU part=C2=A0 =C2=A0 =C2=A0 =C2=A0: 0xc07
=C2=A0 console: CPU revision=C2=A0 =C2=A0: 5
=C2=A0 console: Hardware=C2=A0 =C2=A0 =C2=A0 =C2=A0: Allwinner sun8i Family=
=C2=A0 console: Revision=C2=A0 =C2=A0 =C2=A0 =C2=A0: 0000
=C2=A0 console: Serial=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0: 0000000000000000<= br> =C2=A0 console: cat /proc/iomem
=C2=A0 console: / # cat /proc/iomem
=C2=A0 console: 01000000-010fffff : clock@1000000
=C2=A0 console: 01c00000-01c00fff : system-control@1c00000
=C2=A0 console: 01c02000-01c02fff : dma-controller@1c02000
=C2=A0 [...]
=C2=A0 console: reboot
=C2=A0 console: / # reboot
=C2=A0 console: / # Found console ttyS0
=C2=A0 console: Stopping network: OK
=C2=A0 console: hrtimer: interrupt took 21852064 ns
=C2=A0 console: Saving random seed... random: dd: uninitialized urandom rea= d (512 bytes read)
=C2=A0 console: done.
=C2=A0 console: Stopping logging: OK
=C2=A0 console: umount: devtmpfs busy - remounted read-only
=C2=A0 console: umount: can't unmount /: Invalid argument
=C2=A0 console: The system is going down NOW!
=C2=A0 console: Sent SIGTERM to all processes
=C2=A0 console: Sent SIGKILL to all processes
=C2=A0 console: Requesting system reboot
=C2=A0 console: reboot: Restarting system
=C2=A0 PASS (48.32 s)
=C2=A0 JOB TIME=C2=A0 =C2=A0: 49.16 s

Signed-off-by: Philippe Mathieu-Daud=C3=A9 <philmd@redhat.com>
---
=C2=A0tests/acceptance/boot_linux_console.py | 41 +++++++++++++++++++++++++= +
=C2=A01 file changed, 41 insertions(+)

diff --git a/tests/acceptance/boot_linux_console.py b/tests/acceptance/boot= _linux_console.py
index 820239e439..daabd47404 100644
--- a/tests/acceptance/boot_linux_console.py
+++ b/tests/acceptance/boot_linux_console.py
@@ -437,6 +437,47 @@ class BootLinuxConsole(Test):
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0console_pattern =3D 'Kernel command l= ine: %s' % kernel_command_line
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0self.wait_for_console_pattern(console_pat= tern)

+=C2=A0 =C2=A0 def test_arm_orangepi_initrd(self):
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 """
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 :avocado: tags=3Darch:arm
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 :avocado: tags=3Dmachine:orangepi-pc
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 """
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 deb_url =3D ('https://apt.armbi= an.com/pool/main/l/'
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0'= linux-4.20.7-sunxi/linux-image-dev-sunxi_5.75_armhf.deb')
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 deb_hash =3D '1334c29c44d984ffa05ed10de8c3= 361f33d78315'
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 deb_path =3D self.fetch_asset(deb_url, asset_h= ash=3Ddeb_hash)
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 kernel_path =3D self.extract_from_deb(deb_path= ,
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 '/boot/vmlinuz-4.20.7-sunxi')
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 dtb_path =3D '/usr/lib/linux-image-dev-sun= xi/sun8i-h3-orangepi-pc.dtb'
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 dtb_path =3D self.extract_from_deb(deb_path, d= tb_path)
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 initrd_url =3D ('htt= ps://github.com/groeck/linux-build-test/raw/'
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 '2eb0a73b5d5a28df3170c546ddaaa9757e1e0848/rootfs/'
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 'arm/rootfs-armv7a.cpio.gz')
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 initrd_hash =3D '604b2e45cdf35045846b8bbfb= f2129b1891bdc9c'
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 initrd_path_gz =3D self.fetch_asset(initrd_url= , asset_hash=3Dinitrd_hash)
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 initrd_path =3D os.path.join(self.workdir, = 9;rootfs.cpio')
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 archive.gzip_uncompress(initrd_path_gz, initrd= _path)
+
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 self.vm.set_machine('orangepi-pc')
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 self.vm.set_console()
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 kernel_command_line =3D (self.KERNEL_COMMON_CO= MMAND_LINE +
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0'console=3DttyS0,115200 '
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0'panic=3D-1 noreboot')
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 self.vm.add_args('-kernel', kernel_pat= h,
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0'-dtb', dtb_path,
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0'-initrd', initrd_path,
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0'-append', kernel_command_line,
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0'-no-reboot')
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 self.vm.launch()
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 self.wait_for_console_pattern('Boot succes= sful.')
+
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 exec_command_and_wait_for_pattern(self, 'c= at /proc/cpuinfo',
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 'Allwinner sun8i Family')
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 exec_command_and_wait_for_pattern(self, 'c= at /proc/iomem',
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 'system-control@1c00000')
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 exec_command_and_wait_for_pattern(self, 'r= eboot',
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 'reboot: Restarting system')
+
=C2=A0 =C2=A0 =C2=A0def test_s390x_s390_ccw_virtio(self):
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0"""
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0:avocado: tags=3Darch:s390x
--
2.21.0



--
Niek Linnenbank

--000000000000b9bbe2059a010660-- From MAILER-DAEMON Wed Dec 18 16:22:24 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1ihgm0-0005dH-0Q for mharc-qemu-arm@gnu.org; Wed, 18 Dec 2019 16:22:24 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:51008) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ihglv-0005TO-6n for qemu-arm@nongnu.org; Wed, 18 Dec 2019 16:22:22 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ihglt-0002BL-0s for qemu-arm@nongnu.org; Wed, 18 Dec 2019 16:22:19 -0500 Received: from mail-io1-xd42.google.com ([2607:f8b0:4864:20::d42]:42930) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ihglo-00024F-Hb; Wed, 18 Dec 2019 16:22:12 -0500 Received: by mail-io1-xd42.google.com with SMTP id n11so1994101iom.9; Wed, 18 Dec 2019 13:22:12 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=YnmFDxFVtARO0HY7CapVcOOi+YIONeWeB7RC8ILYGCQ=; b=d8/vEC7X5f3vFQCrQCnYAq+CI0HWEthyo9JmYtqemqIAgw5cx7an/j7Ct8u/RsAV+9 rC+TTLkNaKDww1tFZTNKJpDKfLkdfSMM0SsgAV8vtUAHV4OOV1orcrxHzHJJx3ka4tuh 0+8e2t82QNUwAkgYTVEBifHMSQ+xu6AK8slddWmgmAPJabflDL9rXJQjXPzbAxRJEIdL C9NQifkxXN9ktdNbyyDjtcWGMsNYOnCRF05DojAsVJxCxvLMSZDOpSKUKzlozCn+LqL+ 7FVUozMkGHM+DdDMUvtA/WVVai2iRkB1jIcHmguVB7HJk91WVNFRUZTMAps7F5zBSS4V pYfw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=YnmFDxFVtARO0HY7CapVcOOi+YIONeWeB7RC8ILYGCQ=; b=amYe/4DbZXg7qMNEEIs3KL+tlappRH3jfINYZv6kuDJBLhlnRy74JmLX6QI3GOtO9w MHGls3/oQpuATcsCaut7UIaC3onf0WCwawzVkO6mAegYejVnVsrh7lArE25BaZeh3u+O CgSzzRTpXe7nMu4DGyXqQyUR4BcocKL0XnGX9QSg+RDXbnklDg4s+rehkrru75fMOs9k eVQM0qBT+rJSwzSvkhJdTfQAtBqyBR1XWlIOHWS3Qw22GEndGjqSsG/8tYLTgkbjl061 T/7XXB0NXHB1Al4YceAo4DIIp+XV9btj/Y/SGGubhI9pHq5IdLlh9EiyZ0tDcj6fLoG2 Mo6w== X-Gm-Message-State: APjAAAVCATnLODx29kQlZYXh7BSAoyFBJPdVO8lTJKMteatbT3AiPODz bJdviz4zbvuXsyi2KY++3G5geVMSE+PCGpihqq4= X-Google-Smtp-Source: APXvYqy1acOSEA2Tj0Loes/Z9CTkDJotrgtVMiaZUfTU7ECXojJmFZXVei7wioE7VdXse9GILax2k1k74UfPzPmYqOo= X-Received: by 2002:a6b:d912:: with SMTP id r18mr3231835ioc.306.1576704131649; Wed, 18 Dec 2019 13:22:11 -0800 (PST) MIME-Version: 1.0 References: <20191217182730.943-1-f4bug@amsat.org> <20191217182730.943-4-f4bug@amsat.org> In-Reply-To: <20191217182730.943-4-f4bug@amsat.org> From: Niek Linnenbank Date: Wed, 18 Dec 2019 22:22:00 +0100 Message-ID: Subject: Re: [PATCH 3/5] tests/boot_linux_console: Add a SD card test for the OrangePi PC board To: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= Cc: QEMU Developers , Guenter Roeck , Cleber Rosa , Peter Maydell , qemu-arm Content-Type: multipart/alternative; boundary="000000000000aee4c7059a01095f" X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::d42 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 18 Dec 2019 21:22:22 -0000 --000000000000aee4c7059a01095f Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Same, this one also runs fine for me: Tested-by: Niek Linnenbank On Tue, Dec 17, 2019 at 7:27 PM Philippe Mathieu-Daud=C3=A9 wrote: > The kernel image and DeviceTree blob are built by the Raspbian > project (based on Debian): > https://www.raspbian.org/RaspbianImages > > The SD image is from the kernelci.org project: > https://kernelci.org/faq/#the-code > > If ARM is a target being built, "make check-acceptance" will > automatically include this test by the use of the "arch:arm" tags. > > Alternatively, this test can be run using: > > $ avocado --show=3Dconsole run -t machine:orangepi-pc > tests/acceptance/boot_linux_console.py > console: Uncompressing Linux... done, booting the kernel. > console: Booting Linux on physical CPU 0x0 > console: Linux version 4.20.7-sunxi (root@armbian.com) (gcc version > 7.2.1 20171011 (Linaro GCC 7.2-2017.11)) #5.75 SMP Fri Feb 8 09:02:10 CET > 2019 > console: CPU: ARMv7 Processor [410fc075] revision 5 (ARMv7), cr=3D50c53= 87d > [...] > console: sunxi-wdt 1c20ca0.watchdog: Watchdog enabled (timeout=3D16 sec= , > nowayout=3D0) > console: sunxi-mmc 1c0f000.mmc: Linked as a consumer to regulator.2 > console: sunxi-mmc 1c0f000.mmc: Got CD GPIO > console: ledtrig-cpu: registered to indicate activity on CPUs > console: hidraw: raw HID events driver (C) Jiri Kosina > console: usbcore: registered new interface driver usbhid > console: usbhid: USB HID core driver > console: Initializing XFRM netlink socket > console: sunxi-mmc 1c0f000.mmc: initialized, max. request size: 16384 K= B > console: NET: Registered protocol family 10 > console: mmc0: host does not support reading read-only switch, assuming > write-enable > console: mmc0: Problem switching card into high-speed mode! > console: mmc0: new SD card at address 4567 > console: mmcblk0: mmc0:4567 QEMU! 60.0 MiB > [...] > console: EXT4-fs (mmcblk0): mounting ext2 file system using the ext4 > subsystem > console: EXT4-fs (mmcblk0): mounted filesystem without journal. Opts: > (null) > console: VFS: Mounted root (ext2 filesystem) on device 179:0. > console: Run /sbin/init as init process > console: EXT4-fs (mmcblk0): re-mounted. Opts: > block_validity,barrier,user_xattr,acl > console: Starting syslogd: OK > console: Starting klogd: OK > console: Populating /dev using udev: udevd[203]: starting version 3.2.7 > console: /bin/sh: can't access tty; job control turned off > console: cat /proc/partitions > console: / # cat /proc/partitions > console: major minor #blocks name > console: 1 0 4096 ram0 > console: 1 1 4096 ram1 > console: 1 2 4096 ram2 > console: 1 3 4096 ram3 > console: 179 0 61440 mmcblk0 > console: reboot > console: / # reboot > console: umount: devtmpfs busy - remounted read-only > console: EXT4-fs (mmcblk0): re-mounted. Opts: (null) > console: The system is going down NOW! > console: Sent SIGTERM to all processes > console: Sent SIGKILL to all processes > console: Requesting system reboot > console: reboot: Restarting system > JOB TIME : 68.64 s > > Signed-off-by: Philippe Mathieu-Daud=C3=A9 > --- > tests/acceptance/boot_linux_console.py | 42 ++++++++++++++++++++++++++ > 1 file changed, 42 insertions(+) > > diff --git a/tests/acceptance/boot_linux_console.py > b/tests/acceptance/boot_linux_console.py > index daabd47404..8179b45910 100644 > --- a/tests/acceptance/boot_linux_console.py > +++ b/tests/acceptance/boot_linux_console.py > @@ -478,6 +478,48 @@ class BootLinuxConsole(Test): > exec_command_and_wait_for_pattern(self, 'reboot', > 'reboot: Restarting > system') > > + def test_arm_orangepi_sd(self): > + """ > + :avocado: tags=3Darch:arm > + :avocado: tags=3Dmachine:orangepi-pc > + """ > + deb_url =3D ('https://apt.armbian.com/pool/main/l/' > + > 'linux-4.20.7-sunxi/linux-image-dev-sunxi_5.75_armhf.deb') > + deb_hash =3D '1334c29c44d984ffa05ed10de8c3361f33d78315' > + deb_path =3D self.fetch_asset(deb_url, asset_hash=3Ddeb_hash) > + kernel_path =3D self.extract_from_deb(deb_path, > + '/boot/vmlinuz-4.20.7-sunxi'= ) > + dtb_path =3D > '/usr/lib/linux-image-dev-sunxi/sun8i-h3-orangepi-pc.dtb' > + dtb_path =3D self.extract_from_deb(deb_path, dtb_path) > + rootfs_url =3D (' > http://storage.kernelci.org/images/rootfs/buildroot/' > + 'kci-2019.02/armel/base/rootfs.ext2.xz') > + rootfs_hash =3D '692510cb625efda31640d1de0a8d60e26040f061' > + rootfs_path_xz =3D self.fetch_asset(rootfs_url, > asset_hash=3Drootfs_hash) > + rootfs_path =3D os.path.join(self.workdir, 'rootfs.cpio') > + archive.lzma_uncompress(rootfs_path_xz, rootfs_path) > + > + self.vm.set_machine('orangepi-pc') > + self.vm.set_console() > + kernel_command_line =3D (self.KERNEL_COMMON_COMMAND_LINE + > + 'console=3DttyS0,115200 ' > + 'root=3D/dev/mmcblk0 rootwait rw ' > + 'panic=3D-1 noreboot') > + self.vm.add_args('-kernel', kernel_path, > + '-dtb', dtb_path, > + '-drive', 'file=3D' + rootfs_path + > ',if=3Dsd,format=3Draw', > + '-append', kernel_command_line, > + '-no-reboot') > + self.vm.launch() > + shell_ready =3D "/bin/sh: can't access tty; job control turned o= ff" > + self.wait_for_console_pattern(shell_ready) > + > + exec_command_and_wait_for_pattern(self, 'cat /proc/cpuinfo', > + 'Allwinner sun8i Family'= ) > + exec_command_and_wait_for_pattern(self, 'cat /proc/partitions', > + 'mmcblk0') > + exec_command_and_wait_for_pattern(self, 'reboot', > + 'reboot: Restarting > system') > + > def test_s390x_s390_ccw_virtio(self): > """ > :avocado: tags=3Darch:s390x > -- > 2.21.0 > > --=20 Niek Linnenbank --000000000000aee4c7059a01095f Content-Type: text/html; charset="UTF-8" Content-Transfer-Encoding: quoted-printable
Same, this one also runs fine for me:

<= /div>
=C2=A0 Tested-by: Niek Linnenbank <nieklinnenbank@gmail.com>

On Tue, Dec 17, = 2019 at 7:27 PM Philippe Mathieu-Daud=C3=A9 <f4bug@amsat.org> wrote:
The kernel image and DeviceTree blob are built by th= e Raspbian
project (based on Debian):
https://www.raspbian.org/RaspbianImages

The SD image is from the kernelci.org project:
https://kernelci.org/faq/#the-code

If ARM is a target being built, "make check-acceptance" will
automatically include this test by the use of the "arch:arm" tags= .

Alternatively, this test can be run using:

=C2=A0 $ avocado --show=3Dconsole run -t machine:orangepi-pc tests/acceptan= ce/boot_linux_console.py
=C2=A0 console: Uncompressing Linux... done, booting the kernel.
=C2=A0 console: Booting Linux on physical CPU 0x0
=C2=A0 console: Linux version 4.20.7-sunxi (root@armbian.com) (gcc version 7.2.1 20171011 (L= inaro GCC 7.2-2017.11)) #5.75 SMP Fri Feb 8 09:02:10 CET 2019
=C2=A0 console: CPU: ARMv7 Processor [410fc075] revision 5 (ARMv7), cr=3D50= c5387d
=C2=A0 [...]
=C2=A0 console: sunxi-wdt 1c20ca0.watchdog: Watchdog enabled (timeout=3D16 = sec, nowayout=3D0)
=C2=A0 console: sunxi-mmc 1c0f000.mmc: Linked as a consumer to regulator.2<= br> =C2=A0 console: sunxi-mmc 1c0f000.mmc: Got CD GPIO
=C2=A0 console: ledtrig-cpu: registered to indicate activity on CPUs
=C2=A0 console: hidraw: raw HID events driver (C) Jiri Kosina
=C2=A0 console: usbcore: registered new interface driver usbhid
=C2=A0 console: usbhid: USB HID core driver
=C2=A0 console: Initializing XFRM netlink socket
=C2=A0 console: sunxi-mmc 1c0f000.mmc: initialized, max. request size: 1638= 4 KB
=C2=A0 console: NET: Registered protocol family 10
=C2=A0 console: mmc0: host does not support reading read-only switch, assum= ing write-enable
=C2=A0 console: mmc0: Problem switching card into high-speed mode!
=C2=A0 console: mmc0: new SD card at address 4567
=C2=A0 console: mmcblk0: mmc0:4567 QEMU! 60.0 MiB
=C2=A0 [...]
=C2=A0 console: EXT4-fs (mmcblk0): mounting ext2 file system using the ext4= subsystem
=C2=A0 console: EXT4-fs (mmcblk0): mounted filesystem without journal. Opts= : (null)
=C2=A0 console: VFS: Mounted root (ext2 filesystem) on device 179:0.
=C2=A0 console: Run /sbin/init as init process
=C2=A0 console: EXT4-fs (mmcblk0): re-mounted. Opts: block_validity,barrier= ,user_xattr,acl
=C2=A0 console: Starting syslogd: OK
=C2=A0 console: Starting klogd: OK
=C2=A0 console: Populating /dev using udev: udevd[203]: starting version 3.= 2.7
=C2=A0 console: /bin/sh: can't access tty; job control turned off
=C2=A0 console: cat /proc/partitions
=C2=A0 console: / # cat /proc/partitions
=C2=A0 console: major minor=C2=A0 #blocks=C2=A0 name
=C2=A0 console: 1=C2=A0 =C2=A0 =C2=A0 =C2=A0 0=C2=A0 =C2=A0 =C2=A0 =C2=A040= 96 ram0
=C2=A0 console: 1=C2=A0 =C2=A0 =C2=A0 =C2=A0 1=C2=A0 =C2=A0 =C2=A0 =C2=A040= 96 ram1
=C2=A0 console: 1=C2=A0 =C2=A0 =C2=A0 =C2=A0 2=C2=A0 =C2=A0 =C2=A0 =C2=A040= 96 ram2
=C2=A0 console: 1=C2=A0 =C2=A0 =C2=A0 =C2=A0 3=C2=A0 =C2=A0 =C2=A0 =C2=A040= 96 ram3
=C2=A0 console: 179=C2=A0 =C2=A0 =C2=A0 =C2=A0 0=C2=A0 =C2=A0 =C2=A0 61440 = mmcblk0
=C2=A0 console: reboot
=C2=A0 console: / # reboot
=C2=A0 console: umount: devtmpfs busy - remounted read-only
=C2=A0 console: EXT4-fs (mmcblk0): re-mounted. Opts: (null)
=C2=A0 console: The system is going down NOW!
=C2=A0 console: Sent SIGTERM to all processes
=C2=A0 console: Sent SIGKILL to all processes
=C2=A0 console: Requesting system reboot
=C2=A0 console: reboot: Restarting system
=C2=A0 JOB TIME=C2=A0 =C2=A0: 68.64 s

Signed-off-by: Philippe Mathieu-Daud=C3=A9 <f4bug@amsat.org>
---
=C2=A0tests/acceptance/boot_linux_console.py | 42 +++++++++++++++++++++++++= +
=C2=A01 file changed, 42 insertions(+)

diff --git a/tests/acceptance/boot_linux_console.py b/tests/acceptance/boot= _linux_console.py
index daabd47404..8179b45910 100644
--- a/tests/acceptance/boot_linux_console.py
+++ b/tests/acceptance/boot_linux_console.py
@@ -478,6 +478,48 @@ class BootLinuxConsole(Test):
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0exec_command_and_wait_for_pattern(self, &= #39;reboot',
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0'reboot: Restarting system')

+=C2=A0 =C2=A0 def test_arm_orangepi_sd(self):
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 """
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 :avocado: tags=3Darch:arm
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 :avocado: tags=3Dmachine:orangepi-pc
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 """
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 deb_url =3D ('https://apt.armbi= an.com/pool/main/l/'
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0'= linux-4.20.7-sunxi/linux-image-dev-sunxi_5.75_armhf.deb')
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 deb_hash =3D '1334c29c44d984ffa05ed10de8c3= 361f33d78315'
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 deb_path =3D self.fetch_asset(deb_url, asset_h= ash=3Ddeb_hash)
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 kernel_path =3D self.extract_from_deb(deb_path= ,
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 '/boot/vmlinuz-4.20.7-sunxi')
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 dtb_path =3D '/usr/lib/linux-image-dev-sun= xi/sun8i-h3-orangepi-pc.dtb'
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 dtb_path =3D self.extract_from_deb(deb_path, d= tb_path)
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 rootfs_url =3D ('http://storage.kernelci.org/images/rootfs/buildroot/'
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 'kci-2019.02/armel/base/rootfs.ext2.xz')
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 rootfs_hash =3D '692510cb625efda31640d1de0= a8d60e26040f061'
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 rootfs_path_xz =3D self.fetch_asset(rootfs_url= , asset_hash=3Drootfs_hash)
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 rootfs_path =3D os.path.join(self.workdir, = 9;rootfs.cpio')
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 archive.lzma_uncompress(rootfs_path_xz, rootfs= _path)
+
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 self.vm.set_machine('orangepi-pc')
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 self.vm.set_console()
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 kernel_command_line =3D (self.KERNEL_COMMON_CO= MMAND_LINE +
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0'console=3DttyS0,115200 '
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0'root=3D/dev/mmcblk0 rootwait rw = '
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0'panic=3D-1 noreboot')
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 self.vm.add_args('-kernel', kernel_pat= h,
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0'-dtb', dtb_path,
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0'-drive', 'file=3D' + rootfs_path + ',= if=3Dsd,format=3Draw',
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0'-append', kernel_command_line,
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0'-no-reboot')
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 self.vm.launch()
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 shell_ready =3D "/bin/sh: can't acces= s tty; job control turned off"
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 self.wait_for_console_pattern(shell_ready)
+
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 exec_command_and_wait_for_pattern(self, 'c= at /proc/cpuinfo',
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 'Allwinner sun8i Family')
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 exec_command_and_wait_for_pattern(self, 'c= at /proc/partitions',
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 'mmcblk0')
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 exec_command_and_wait_for_pattern(self, 'r= eboot',
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 'reboot: Restarting system')
+
=C2=A0 =C2=A0 =C2=A0def test_s390x_s390_ccw_virtio(self):
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0"""
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0:avocado: tags=3Darch:s390x
--
2.21.0



--
Niek Linnenbank

--000000000000aee4c7059a01095f-- From MAILER-DAEMON Wed Dec 18 16:23:51 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1ihgnP-0007K3-CR for mharc-qemu-arm@gnu.org; Wed, 18 Dec 2019 16:23:51 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:53920) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ihgnM-0007Ft-39 for qemu-arm@nongnu.org; Wed, 18 Dec 2019 16:23:49 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ihgnK-0004Ax-R3 for qemu-arm@nongnu.org; Wed, 18 Dec 2019 16:23:48 -0500 Received: from mail-io1-xd43.google.com ([2607:f8b0:4864:20::d43]:36233) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ihgnH-00043R-Sm; Wed, 18 Dec 2019 16:23:44 -0500 Received: by mail-io1-xd43.google.com with SMTP id r13so3542887ioa.3; Wed, 18 Dec 2019 13:23:43 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=WtKoWcYA4eLIkTD5hhsie5xpQCIYiUwxTm3208IaOxQ=; b=VB+vxT/N6AhQaOfbqc9J8H2pfyaQ1f2YM0CnHaQOsHkvoQf423NiJKfcQ4LlY8QivG dTOxiOVp6h6uF7vKsetAHW1zdH2kUY19wofGZOkZvS4DbLi5TfJPMSsAhuJcLBg68MMr b6d1s4d3cgaajIu4pHKDh7w+sn7/X3tn/1+W7aPwUN0wJqdD0vuu0Xt6lpH43RFgZI+6 +JCBiyjCniMu5AlMV8W3eSuOSm7JPKq4lNGUTQJX7xkFNobUB+hDBl6plMB3bsZShVes Ntg3G2YETn2Ep7n0XP2QOMAWljtgAh1gixenT8PfYDWbWyJTiC5yl8VWt6fqe2KJDRdt qI9g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=WtKoWcYA4eLIkTD5hhsie5xpQCIYiUwxTm3208IaOxQ=; b=BEDoeq/+Q/nhjJIrm/FNCVsmEzIE8mV5n5W40I/5eNZ/4Y/Jo/F/0gqAgGfTP65EfZ 3n1kSdJ2Z5eJ0oV5VDlC4uXXYXeZm2V4VVd+6ZcDZezJqPxF3bN0w8YONyO0rBGXJHL+ yj+BH+p1rCBlj7hx3rNgeeXXtc1JfhF9eK+oin0X0JaaZkJCm76x1ZxMLHHtqu17AvW2 yu5UkbRy8FkXLjS7tlKcAl0gAhvQdTpLoALuRtPc6Ke+w30IRuQtyPsCwKV2QTgnoVK8 QMXjy4/xezH/C/ITde9MDHBFXEYidWGZWT4ViJaawA05l2nyuUKApUIAbSvpH4GbJB1w pPwg== X-Gm-Message-State: APjAAAUydaQHHbh0FZ5UUOj0pL3gz0bSAGztZ8EUbohaUUMfEg73yEon a66H/stgkVaVgMuPkAd0IukYiOHCqHpXG5zdsD0= X-Google-Smtp-Source: APXvYqwnw6dhg98pv1fDSDdgEea4/1/0StD071ln9a2/MIcBmJCoxMIqn40ZP8h/TBgc+4ljrPrz4fd7bxeYNDpp9T8= X-Received: by 2002:a02:7fd0:: with SMTP id r199mr4373763jac.126.1576704223115; Wed, 18 Dec 2019 13:23:43 -0800 (PST) MIME-Version: 1.0 References: <20191217182730.943-1-f4bug@amsat.org> <20191217182730.943-5-f4bug@amsat.org> In-Reply-To: <20191217182730.943-5-f4bug@amsat.org> From: Niek Linnenbank Date: Wed, 18 Dec 2019 22:23:32 +0100 Message-ID: Subject: Re: [RFC PATCH 4/5] !fixup "hw: arm: add Xunlong Orange Pi PC machine" To: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= Cc: QEMU Developers , Guenter Roeck , Cleber Rosa , Peter Maydell , qemu-arm Content-Type: multipart/alternative; boundary="0000000000002281e1059a010fc4" X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::d43 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 18 Dec 2019 21:23:49 -0000 --0000000000002281e1059a010fc4 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Hi Philippe, Noted. I'll make sure mc->default_ram_size =3D 1 * GiB is added for the nex= t reworked patch set v3. Regards, Niek On Tue, Dec 17, 2019 at 7:27 PM Philippe Mathieu-Daud=C3=A9 wrote: > Without this, the machine starts with default 128MB, and Ubuntu Bionic > fails: > > [ *** ] (2 of 4) A start job is running for=E2=80=A6Persistent Storage (= 37s / > 2min 1s) > [ *** ] (2 of 4) A start job is running for=E2=80=A6Persistent Storage (= 38s / > 2min 1s) > [ OK ] Started Flush Journal to Persistent Storage. > Starting Create Volatile Files and Directories... > Starting Armbian ZRAM config... > [ **] (3 of 6) A start job is running for=E2=80=A6s and Directories (5= 5s / no > limit) > [ *] (3 of 6) A start job is running for=E2=80=A6s and Directories (5= 5s / no > limit) > [ **] (3 of 6) A start job is running for=E2=80=A6s and Directories (5= 6s / no > limit) > [ OK ] Started Create Volatile Files and Directories. > [*** ] (5 of 6) A start job is running for=E2=80=A6 ZRAM config (1min 1= 0s / 1min > 19s) > [** ] (5 of 6) A start job is running for=E2=80=A6 ZRAM config (1min 1= 2s / 1min > 19s) > [* ] (5 of 6) A start job is running for=E2=80=A6 ZRAM config (1min 1= 3s / 1min > 19s) > [FAILED] Failed to start Armbian ZRAM config. > See 'systemctl status armbian-zram-config.service' for details. > > Signed-off-by: Philippe Mathieu-Daud=C3=A9 > --- > hw/arm/orangepi.c | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/hw/arm/orangepi.c b/hw/arm/orangepi.c > index 119f370924..da758d7eba 100644 > --- a/hw/arm/orangepi.c > +++ b/hw/arm/orangepi.c > @@ -122,6 +122,7 @@ static void orangepi_machine_init(MachineClass *mc) > mc->max_cpus =3D AW_H3_NUM_CPUS; > mc->default_cpus =3D AW_H3_NUM_CPUS; > mc->default_cpu_type =3D ARM_CPU_TYPE_NAME("cortex-a7"); > + mc->default_ram_size =3D 1 * GiB; > } > > DEFINE_MACHINE("orangepi-pc", orangepi_machine_init) > -- > 2.21.0 > > --=20 Niek Linnenbank --0000000000002281e1059a010fc4 Content-Type: text/html; charset="UTF-8" Content-Transfer-Encoding: quoted-printable
Hi Philippe,

Noted. I'll= make sure mc->default_ram_size =3D 1 * GiB is added for the next rework= ed patch set v3.

Regards,
Niek
=

= On Tue, Dec 17, 2019 at 7:27 PM Philippe Mathieu-Daud=C3=A9 <f4bug@amsat.org> wrote:
Without this, the machine starts wit= h default 128MB, and Ubuntu Bionic
fails:

[ ***=C2=A0 ] (2 of 4) A start job is running for=E2=80=A6Persistent Storag= e (37s / 2min 1s)
[=C2=A0 *** ] (2 of 4) A start job is running for=E2=80=A6Persistent Storag= e (38s / 2min 1s)
[=C2=A0 OK=C2=A0 ] Started Flush Journal to Persistent Storage.
Starting Create Volatile Files and Directories...
Starting Armbian ZRAM config...
[=C2=A0 =C2=A0 **] (3 of 6) A start job is running for=E2=80=A6s and Direct= ories (55s / no limit)
[=C2=A0 =C2=A0 =C2=A0*] (3 of 6) A start job is running for=E2=80=A6s and D= irectories (55s / no limit)
[=C2=A0 =C2=A0 **] (3 of 6) A start job is running for=E2=80=A6s and Direct= ories (56s / no limit)
[=C2=A0 OK=C2=A0 ] Started Create Volatile Files and Directories.
[***=C2=A0 =C2=A0] (5 of 6) A start job is running for=E2=80=A6 ZRAM config= (1min 10s / 1min 19s)
[**=C2=A0 =C2=A0 ] (5 of 6) A start job is running for=E2=80=A6 ZRAM config= (1min 12s / 1min 19s)
[*=C2=A0 =C2=A0 =C2=A0] (5 of 6) A start job is running for=E2=80=A6 ZRAM c= onfig (1min 13s / 1min 19s)
[FAILED] Failed to start Armbian ZRAM config.
See 'systemctl status armbian-zram-config.service' for details.

Signed-off-by: Philippe Mathieu-Daud=C3=A9 <f4bug@amsat.org>
---
=C2=A0hw/arm/orangepi.c | 1 +
=C2=A01 file changed, 1 insertion(+)

diff --git a/hw/arm/orangepi.c b/hw/arm/orangepi.c
index 119f370924..da758d7eba 100644
--- a/hw/arm/orangepi.c
+++ b/hw/arm/orangepi.c
@@ -122,6 +122,7 @@ static void orangepi_machine_init(MachineClass *mc)
=C2=A0 =C2=A0 =C2=A0mc->max_cpus =3D AW_H3_NUM_CPUS;
=C2=A0 =C2=A0 =C2=A0mc->default_cpus =3D AW_H3_NUM_CPUS;
=C2=A0 =C2=A0 =C2=A0mc->default_cpu_type =3D ARM_CPU_TYPE_NAME("cor= tex-a7");
+=C2=A0 =C2=A0 mc->default_ram_size =3D 1 * GiB;
=C2=A0}

=C2=A0DEFINE_MACHINE("orangepi-pc", orangepi_machine_init)
--
2.21.0



--
Niek Linnenbank

--0000000000002281e1059a010fc4-- From MAILER-DAEMON Wed Dec 18 16:26:33 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1ihgq1-0000l9-5r for mharc-qemu-arm@gnu.org; Wed, 18 Dec 2019 16:26:33 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:59225) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ihgpw-0000gZ-NX for qemu-arm@nongnu.org; Wed, 18 Dec 2019 16:26:31 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ihgpu-0007XL-4M for qemu-arm@nongnu.org; Wed, 18 Dec 2019 16:26:28 -0500 Received: from mail-il1-x142.google.com ([2607:f8b0:4864:20::142]:41592) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ihgpo-0007Pi-B2; Wed, 18 Dec 2019 16:26:20 -0500 Received: by mail-il1-x142.google.com with SMTP id f10so2954841ils.8; Wed, 18 Dec 2019 13:26:20 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=hjzXs3cozJZpZgcBx2emjmDsMBr6Ew/+q/IvgzsBb8w=; b=V6aQ1bwWnawCdghS0qJqu026jJFFdUR3TRnJQvEoIY7rG5QyY+lsNHTYDJWRARCVnw r8Q9DdWTBbBsFWGHz+RNZqD89mC5wVQCACHO5CXB51ACjv1S7i8GLM8g0SdAxyJTJIr3 DqMcfw1gbsb3obBHf2FbeHOMCZ7ptcbBfvVRGTHyspQoaSNVwU7/CsnEdu+xepW7XwW1 VkLGxQr0DC7FlCqk/K0v9gi33M2+1lwNZ1JfmiHbGLACPB7k5HdlCUl+EHSWKgJbjL2p TP6x+8bsqzj4zD3Utfc5sWs0NT4OoBIa7Yh/uGQoA1e9Rrg9LkqlPZJrphma17LJiWpO IJCQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=hjzXs3cozJZpZgcBx2emjmDsMBr6Ew/+q/IvgzsBb8w=; b=jRA92cD25CRwqxeEoGbtAiHlsq2/viKxc/yHlHjFaH/Hrd2bEQYQiIp7IrC/fy5D6z 40yZwVWfM99dPEYgH4C7XDX3VgxFqwjWyPdzXrYNSegIkcTzmJry8haIML4Mbntlo+9H gdgPUbW0O+kKXnVBeLfPQ41WS4YRXVxuL9CHcR7jO4uUWT2t1ldeguLBj/Gt1P4snpqM GA/ilLw6YiafBlde0bg/nG/VmhQP2T8+4moCT0wz1mvlo2TWu2oXyiJ4uCj6myc/taxC S2Dv+M9MYKhBc2iIDXEeowat/FiwWOGyNf8jmfd0EhdUGK3ggxqGgQuDOfFFZs4+s9wC Hetg== X-Gm-Message-State: APjAAAWe3CNQ8gZw9tswRNevSde9uUGiGB8xzDgmiRFqtPOZcLto0M+o MC2LG9lWcbcAbY27YDlBzZXxx4Bpe/BLcS2rAXg= X-Google-Smtp-Source: APXvYqwKSEtndlV3DBntk3ds6pQdl1TR7iyuSNThsYyKUi/G5tgzHbmUZWwMei52oy37D8A9rJcHTX3pFuoTG5kwxU0= X-Received: by 2002:a92:a103:: with SMTP id v3mr3394346ili.265.1576704379474; Wed, 18 Dec 2019 13:26:19 -0800 (PST) MIME-Version: 1.0 References: <20191217182730.943-1-f4bug@amsat.org> <20191217182730.943-6-f4bug@amsat.org> In-Reply-To: <20191217182730.943-6-f4bug@amsat.org> From: Niek Linnenbank Date: Wed, 18 Dec 2019 22:26:08 +0100 Message-ID: Subject: Re: [RFC PATCH 5/5] tests/boot_linux_console: Add a SLOW test booting Ubuntu on OrangePi PC To: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= Cc: QEMU Developers , Guenter Roeck , Cleber Rosa , Peter Maydell , qemu-arm Content-Type: multipart/alternative; boundary="000000000000745858059a0118b3" X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::142 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 18 Dec 2019 21:26:32 -0000 --000000000000745858059a0118b3 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Hi Philippe, This test has some problems on my host (Ubuntu 18.04.3 LTS, avocado 73.0, python 3.6.9): (4/4) tests/acceptance/boot_linux_console.py:BootLinuxConsole.test_arm_ora= ngepi_bionic: ERROR: Input format not supported by decoder (3.25 s) RESULTS : PASS 3 | ERROR 1 | FAIL 0 | SKIP 0 | WARN 0 | INTERRUPT 0 | CANCEL 0 JOB TIME : 46.22 s I suspect it didn't download the image correctly. Regards, Niek On Tue, Dec 17, 2019 at 7:27 PM Philippe Mathieu-Daud=C3=A9 wrote: > This test boots Ubuntu Bionic on a OrangePi PC board. > > As it requires 1GB of storage, and is slow, this test is disabled > on automatic CI testing. > > It is useful for workstation testing. Currently Avocado timeouts too > quickly, so we can't run userland commands. > > The kernel image and DeviceTree blob are built by the Raspbian > project (based on Debian): > https://www.raspbian.org/RaspbianImages > > The Ubuntu image is downloaded from: > https://dl.armbian.com/orangepipc/Bionic_current > > This test can be run using: > > $ AVOCADO_ALLOW_LARGE_STORAGE=3Dyes \ > avocado --show=3Dapp,console run -t machine:orangepi-pc \ > tests/acceptance/boot_linux_console.py > console: Uncompressing Linux... done, booting the kernel. > console: Booting Linux on physical CPU 0x0 > console: Linux version 4.20.7-sunxi (root@armbian.com) (gcc version > 7.2.1 20171011 (Linaro GCC 7.2-2017.11)) #5.75 SMP Fri Feb 8 09:02:10 CET > 2019 > console: CPU: ARMv7 Processor [410fc075] revision 5 (ARMv7), cr=3D50c53= 87d > console: CPU: div instructions available: patching division code > console: CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing > instruction cache > console: OF: fdt: Machine model: Xunlong Orange Pi PC > [...] > console: sunxi-mmc 1c0f000.mmc: initialized, max. request size: 16384 K= B > console: NET: Registered protocol family 10 > console: mmc0: host does not support reading read-only switch, assuming > write-enable > console: mmc0: Problem switching card into high-speed mode! > console: mmc0: new SD card at address 4567 > console: mmcblk0: mmc0:4567 QEMU! 932 MiB > console: Segment Routing with IPv6 > console: NET: Registered protocol family 17 > console: NET: Registered protocol family 15 > console: bridge: filtering via arp/ip/ip6tables is no longer available > by default. Update your scripts to load br_netfilter if you need this. > console: 8021q: 802.1Q VLAN Support v1.8 > console: Key type dns_resolver registered > console: Registering SWP/SWPB emulation handler > console: mmcblk0: p1 > [...] > console: Freeing unused kernel memory: 1024K > console: Run /sbin/init as init process > console: random: fast init done > console: systemd[1]: System time before build time, advancing clock. > console: systemd[1]: systemd 237 running in system mode. (+PAM +AUDIT > +SELINUX +IMA +APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT > +GNUTLS +ACL +XZ +LZ4 +SECCOMP +BLKID +ELFUTILS +KMOD -IDN2 +IDN -PCRE2 > default-hierarchy=3Dhybrid) > console: systemd[1]: Detected architecture arm. > console: Welcome to Ubuntu 18.04.3 LTS! > console: systemd[1]: Set hostname to . > console: random: systemd: uninitialized urandom read (16 bytes read) > > Signed-off-by: Philippe Mathieu-Daud=C3=A9 > --- > RFC because this is not the definitive test, but it is helpful so > for for testing Niek work. > --- > tests/acceptance/boot_linux_console.py | 41 ++++++++++++++++++++++++++ > 1 file changed, 41 insertions(+) > > diff --git a/tests/acceptance/boot_linux_console.py > b/tests/acceptance/boot_linux_console.py > index 8179b45910..663290e0c7 100644 > --- a/tests/acceptance/boot_linux_console.py > +++ b/tests/acceptance/boot_linux_console.py > @@ -520,6 +520,47 @@ class BootLinuxConsole(Test): > exec_command_and_wait_for_pattern(self, 'reboot', > 'reboot: Restarting > system') > > + @skipUnless(os.getenv('AVOCADO_ALLOW_LARGE_STORAGE'), 'storage > limited') > + def test_arm_orangepi_bionic(self): > + """ > + :avocado: tags=3Darch:arm > + :avocado: tags=3Dmachine:orangepi-pc > + """ > + # This test download a 196MB compressed image and expand it to > 932MB... > + deb_url =3D ('https://apt.armbian.com/pool/main/l/' > + > 'linux-4.20.7-sunxi/linux-image-dev-sunxi_5.75_armhf.deb') > + deb_hash =3D '1334c29c44d984ffa05ed10de8c3361f33d78315' > + deb_path =3D self.fetch_asset(deb_url, asset_hash=3Ddeb_hash) > + kernel_path =3D self.extract_from_deb(deb_path, > + '/boot/vmlinuz-4.20.7-sunxi'= ) > + dtb_path =3D > '/usr/lib/linux-image-dev-sunxi/sun8i-h3-orangepi-pc.dtb' > + dtb_path =3D self.extract_from_deb(deb_path, dtb_path) > + image_url =3D ('https://dl.armbian.com/orangepipc/archive/' > + 'Armbian_19.11.3_Orangepipc_bionic_current_5.3.9.7z= ') > + image_hash =3D '196a8ffb72b0123d92cea4a070894813d305c71e' > + image_path_xz =3D self.fetch_asset(image_url, asset_hash=3Dimage= _hash) > + image_name =3D 'Armbian_19.11.3_Orangepipc_bionic_current_5.3.9.= img' > + image_path =3D os.path.join(self.workdir, image_name) > + archive.lzma_uncompress(image_path_xz, image_path) > + > + self.vm.set_machine('orangepi-pc') > + self.vm.set_console() > + kernel_command_line =3D (self.KERNEL_COMMON_COMMAND_LINE + > + 'console=3DttyS0,115200 ' > + 'root=3D/dev/mmcblk0p1 rootwait rw ' > + 'systemd.mask=3Ddev-ttyS0.device ' > + 'systemd.mask=3Darmbian-zram-config.servi= ce ' > + 'systemd.mask=3Darmbian-ramlog.service') > + self.vm.add_args('-kernel', kernel_path, > + '-dtb', dtb_path, > + '-drive', 'file=3D' + image_path + > ',if=3Dsd,format=3Draw', > + '-append', kernel_command_line, > + '-nic', 'user', > + '-no-reboot') > + self.vm.launch() > + self.wait_for_console_pattern('Welcome to Ubuntu 18.04.3 LTS!') > + self.wait_for_console_pattern('Started Armbian filesystem > resize.') > + > def test_s390x_s390_ccw_virtio(self): > """ > :avocado: tags=3Darch:s390x > -- > 2.21.0 > > --=20 Niek Linnenbank --000000000000745858059a0118b3 Content-Type: text/html; charset="UTF-8" Content-Transfer-Encoding: quoted-printable
Hi Philippe,

This test has s= ome problems on my host (Ubuntu 18.04.3 LTS, avocado 73.0, python 3.6.9):
 (4/4) tests/acceptance/boot_linux_console.py:BootLinuxConsole.test_=
arm_orangepi_bionic: ERROR: Input format not supported by decoder (3.25 s)
RESULTS    : PASS 3 | ERROR 1 | FAIL 0 | SKIP 0 | WARN 0 | INTERRUPT 0 | CA=
NCEL 0
JOB TIME   : 46.22 s
I suspect it didn't download the image correctly.

Regards,
Niek

On Tue, Dec 17, = 2019 at 7:27 PM Philippe Mathieu-Daud=C3=A9 <f4bug@amsat.org> wrote:
This test boots Ubuntu Bionic on a OrangePi PC board= .

As it requires 1GB of storage, and is slow, this test is disabled
on automatic CI testing.

It is useful for workstation testing. Currently Avocado timeouts too
quickly, so we can't run userland commands.

The kernel image and DeviceTree blob are built by the Raspbian
project (based on Debian):
https://www.raspbian.org/RaspbianImages

The Ubuntu image is downloaded from:
https://dl.armbian.com/orangepipc/Bionic_current=

This test can be run using:

=C2=A0 $ AVOCADO_ALLOW_LARGE_STORAGE=3Dyes \
=C2=A0 =C2=A0 avocado --show=3Dapp,console run -t machine:orangepi-pc \
=C2=A0 =C2=A0 =C2=A0 tests/acceptance/boot_linux_console.py
=C2=A0 console: Uncompressing Linux... done, booting the kernel.
=C2=A0 console: Booting Linux on physical CPU 0x0
=C2=A0 console: Linux version 4.20.7-sunxi (root@armbian.com) (gcc version 7.2.1 20171011 (L= inaro GCC 7.2-2017.11)) #5.75 SMP Fri Feb 8 09:02:10 CET 2019
=C2=A0 console: CPU: ARMv7 Processor [410fc075] revision 5 (ARMv7), cr=3D50= c5387d
=C2=A0 console: CPU: div instructions available: patching division code
=C2=A0 console: CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing inst= ruction cache
=C2=A0 console: OF: fdt: Machine model: Xunlong Orange Pi PC
=C2=A0 [...]
=C2=A0 console: sunxi-mmc 1c0f000.mmc: initialized, max. request size: 1638= 4 KB
=C2=A0 console: NET: Registered protocol family 10
=C2=A0 console: mmc0: host does not support reading read-only switch, assum= ing write-enable
=C2=A0 console: mmc0: Problem switching card into high-speed mode!
=C2=A0 console: mmc0: new SD card at address 4567
=C2=A0 console: mmcblk0: mmc0:4567 QEMU! 932 MiB
=C2=A0 console: Segment Routing with IPv6
=C2=A0 console: NET: Registered protocol family 17
=C2=A0 console: NET: Registered protocol family 15
=C2=A0 console: bridge: filtering via arp/ip/ip6tables is no longer availab= le by default. Update your scripts to load br_netfilter if you need this. =C2=A0 console: 8021q: 802.1Q VLAN Support v1.8
=C2=A0 console: Key type dns_resolver registered
=C2=A0 console: Registering SWP/SWPB emulation handler
=C2=A0 console: mmcblk0: p1
=C2=A0 [...]
=C2=A0 console: Freeing unused kernel memory: 1024K
=C2=A0 console: Run /sbin/init as init process
=C2=A0 console: random: fast init done
=C2=A0 console: systemd[1]: System time before build time, advancing clock.=
=C2=A0 console: systemd[1]: systemd 237 running in system mode. (+PAM +AUDI= T +SELINUX +IMA +APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT +GN= UTLS +ACL +XZ +LZ4 +SECCOMP +BLKID +ELFUTILS +KMOD -IDN2 +IDN -PCRE2 defaul= t-hierarchy=3Dhybrid)
=C2=A0 console: systemd[1]: Detected architecture arm.
=C2=A0 console: Welcome to Ubuntu 18.04.3 LTS!
=C2=A0 console: systemd[1]: Set hostname to <orangepipc>.
=C2=A0 console: random: systemd: uninitialized urandom read (16 bytes read)=

Signed-off-by: Philippe Mathieu-Daud=C3=A9 <f4bug@amsat.org>
---
RFC because this is not the definitive test, but it is helpful so
for for testing Niek work.
---
=C2=A0tests/acceptance/boot_linux_console.py | 41 +++++++++++++++++++++++++= +
=C2=A01 file changed, 41 insertions(+)

diff --git a/tests/acceptance/boot_linux_console.py b/tests/acceptance/boot= _linux_console.py
index 8179b45910..663290e0c7 100644
--- a/tests/acceptance/boot_linux_console.py
+++ b/tests/acceptance/boot_linux_console.py
@@ -520,6 +520,47 @@ class BootLinuxConsole(Test):
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0exec_command_and_wait_for_pattern(self, &= #39;reboot',
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0'reboot: Restarting system')

+=C2=A0 =C2=A0 @skipUnless(os.getenv('AVOCADO_ALLOW_LARGE_STORAGE')= , 'storage limited')
+=C2=A0 =C2=A0 def test_arm_orangepi_bionic(self):
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 """
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 :avocado: tags=3Darch:arm
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 :avocado: tags=3Dmachine:orangepi-pc
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 """
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 # This test download a 196MB compressed image = and expand it to 932MB...
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 deb_url =3D ('https://apt.armbi= an.com/pool/main/l/'
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0'= linux-4.20.7-sunxi/linux-image-dev-sunxi_5.75_armhf.deb')
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 deb_hash =3D '1334c29c44d984ffa05ed10de8c3= 361f33d78315'
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 deb_path =3D self.fetch_asset(deb_url, asset_h= ash=3Ddeb_hash)
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 kernel_path =3D self.extract_from_deb(deb_path= ,
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 '/boot/vmlinuz-4.20.7-sunxi')
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 dtb_path =3D '/usr/lib/linux-image-dev-sun= xi/sun8i-h3-orangepi-pc.dtb'
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 dtb_path =3D self.extract_from_deb(deb_path, d= tb_path)
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 image_url =3D ('https://d= l.armbian.com/orangepipc/archive/'
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0'Armbian_19.11.3_Orangepipc_bionic_current_5.3.9.7z')
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 image_hash =3D '196a8ffb72b0123d92cea4a070= 894813d305c71e'
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 image_path_xz =3D self.fetch_asset(image_url, = asset_hash=3Dimage_hash)
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 image_name =3D 'Armbian_19.11.3_Orangepipc= _bionic_current_5.3.9.img'
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 image_path =3D os.path.join(self.workdir, imag= e_name)
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 archive.lzma_uncompress(image_path_xz, image_p= ath)
+
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 self.vm.set_machine('orangepi-pc')
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 self.vm.set_console()
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 kernel_command_line =3D (self.KERNEL_COMMON_CO= MMAND_LINE +
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0'console=3DttyS0,115200 '
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0'root=3D/dev/mmcblk0p1 rootwait r= w '
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0'systemd.mask=3Ddev-ttyS0.device = '
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0'systemd.mask=3Darmbian-zram-conf= ig.service '
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0'systemd.mask=3Darmbian-ramlog.se= rvice')
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 self.vm.add_args('-kernel', kernel_pat= h,
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0'-dtb', dtb_path,
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0'-drive', 'file=3D' + image_path + ',i= f=3Dsd,format=3Draw',
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0'-append', kernel_command_line,
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0'-nic', 'user',
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0'-no-reboot')
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 self.vm.launch()
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 self.wait_for_console_pattern('Welcome to = Ubuntu 18.04.3 LTS!')
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 self.wait_for_console_pattern('Started Arm= bian filesystem resize.')
+
=C2=A0 =C2=A0 =C2=A0def test_s390x_s390_ccw_virtio(self):
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0"""
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0:avocado: tags=3Darch:s390x
--
2.21.0



--
Niek Linnenbank

--000000000000745858059a0118b3-- From MAILER-DAEMON Wed Dec 18 16:29:19 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1ihgsh-0003Tj-II for mharc-qemu-arm@gnu.org; Wed, 18 Dec 2019 16:29:19 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:36730) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ihgse-0003PD-P5 for qemu-arm@nongnu.org; Wed, 18 Dec 2019 16:29:17 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ihgsd-0002ml-P1 for qemu-arm@nongnu.org; Wed, 18 Dec 2019 16:29:16 -0500 Received: from mail-oi1-x241.google.com ([2607:f8b0:4864:20::241]:42848) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ihgsX-0002hV-4T; Wed, 18 Dec 2019 16:29:09 -0500 Received: by mail-oi1-x241.google.com with SMTP id 18so1251227oin.9; Wed, 18 Dec 2019 13:29:09 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc:content-transfer-encoding; bh=/wTMVe3mHFcJ+GRI7GSpvgLdvogiRtHuB4BVxZXVU9s=; b=O3fRKKTGyd4E2NdolzDIwvJANQqdz1yhDuM/LCkaqacqt/xC1yXbyg3lngBdkpoIwr KhyCRTNwkjKwy582TvLU9ZDxhMP4oBvQXtExSqEuuOcvenloNKuTPURaQctNMO5LXk58 OdzqM8+llpqFlbaJoKGsFJb4tq8wUw+DLGxHceSsdTcIjb4opR6xU5CQVoqR2d9JQCet JzDm2W6zq9eK8Y6OBD6SZMceBIl7+vwp6DUkNNiYjPtrDXEooalmUWHmuZu694k50NPw GM0zVT79BCPVUmu2LZL6t9jXEiXSj/JBWtIYJNFyWQUs1A2Nye/osNkOPjDgRPmcBMUd D1dw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc:content-transfer-encoding; bh=/wTMVe3mHFcJ+GRI7GSpvgLdvogiRtHuB4BVxZXVU9s=; b=cM5KB6Zu7nI+sTNFFcwdQLRAGUucM7ab8MjvKL59niGrSJQO8Q9ScjAvq8gqYiKSMf hqMocF0vijZMv4gxcpcS7Py4x++GeLnCg7G+MZ4P/KsHIESRofSMtHNJvCwsffAGH5z9 k24Rgi+NT7cjm5YsZ/TRq+LCpfrB7Nzy5WtkfaNG45bLrNlsKNIzUKBV1CJRZoN4ImWi l+GOndO8XA9FSWoUIBuzAVCBVvrvRCFqhy44mOeNd2tPYStiCjFNk3oPbI2XrNQgmk+V HlOeAfC2+UcUAogMc15GkRJngCyyfzI8JTy1gHK9AGSaKf5Ke6ouFLa7jTbiMVKFAwK6 TWyw== X-Gm-Message-State: APjAAAW/+vHpNWLi+rWp9RTlOlXjlpc+3PXEBiEDx+h2ehKuqSWBlzsh 5c3/DH2udlb2XnpPxJOPxZz85mO8pxuNLWDfKJo= X-Google-Smtp-Source: APXvYqwLdJjQeX2pO+HZdDCCv/Syb0ahbil8ZJgKSyWjb0VmGWROe2BhXihCULqjAqo8fUt0/NziUX53p0u7w7t9d0c= X-Received: by 2002:a05:6808:2d5:: with SMTP id a21mr1548161oid.62.1576704548297; Wed, 18 Dec 2019 13:29:08 -0800 (PST) MIME-Version: 1.0 References: <20191218192526.13845-1-philmd@redhat.com> <20191218192526.13845-7-philmd@redhat.com> In-Reply-To: <20191218192526.13845-7-philmd@redhat.com> From: Aleksandar Markovic Date: Wed, 18 Dec 2019 22:28:57 +0100 Message-ID: Subject: Re: [RFC PATCH v2 6/6] hw/pci-host/designware: Remove unuseful FALLTHROUGH comment To: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= Cc: QEMU Developers , Peter Maydell , Andrey Smirnov , Markus Armbruster , "open list:Stellaris" , Peter Chubb Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::241 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 18 Dec 2019 21:29:17 -0000 On Wed, Dec 18, 2019 at 8:29 PM Philippe Mathieu-Daud=C3=A9 wrote: > > We don't need to explicit this obvious switch fall through. > Stay consistent with the rest of the codebase. > > Signed-off-by: Philippe Mathieu-Daud=C3=A9 > --- I see you covered two cases of such comment (in patches 5 and 6). But why didn't you than cover the following cases: block/vhdx.c: case PAYLOAD_BLOCK_NOT_PRESENT: /* fall through */ block/vhdx.c: case PAYLOAD_BLOCK_NOT_PRESENT: /* fall through */ hw/net/rtl8139.c: case 1: /* fall through */ hw/net/rtl8139.c: case 2: /* fall through */ contrib/vhost-user-scsi/vhost-user-scsi.c: case 1: /* fall through */ (this one needs full switch block reformatting, but can this be changed, since it is in "contrib"?) ? Thanks, Aleksandar > Cc: Peter Chubb > Cc: Markus Armbruster > Cc: Peter Maydell > Cc: Andrey Smirnov > Cc: qemu-arm@nongnu.org > --- > hw/pci-host/designware.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/hw/pci-host/designware.c b/hw/pci-host/designware.c > index 71e9b0d9b5..dd245516dd 100644 > --- a/hw/pci-host/designware.c > +++ b/hw/pci-host/designware.c > @@ -182,7 +182,7 @@ designware_pcie_root_config_read(PCIDevice *d, uint32= _t address, int len) > break; > > case DESIGNWARE_PCIE_ATU_CR1: > - case DESIGNWARE_PCIE_ATU_CR2: /* FALLTHROUGH */ > + case DESIGNWARE_PCIE_ATU_CR2: > val =3D viewport->cr[(address - DESIGNWARE_PCIE_ATU_CR1) / > sizeof(uint32_t)]; > break; > -- > 2.21.0 > > From MAILER-DAEMON Wed Dec 18 18:25:48 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1ihihP-0007p1-U6 for mharc-qemu-arm@gnu.org; Wed, 18 Dec 2019 18:25:47 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:35554) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ihihM-0007j6-P3 for qemu-arm@nongnu.org; Wed, 18 Dec 2019 18:25:45 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ihihL-0003lu-D6 for qemu-arm@nongnu.org; Wed, 18 Dec 2019 18:25:44 -0500 Received: from mail-pg1-x542.google.com ([2607:f8b0:4864:20::542]:42489) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ihihL-0003kQ-5n for qemu-arm@nongnu.org; Wed, 18 Dec 2019 18:25:43 -0500 Received: by mail-pg1-x542.google.com with SMTP id s64so2078436pgb.9 for ; Wed, 18 Dec 2019 15:25:42 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=subject:to:cc:references:from:message-id:date:user-agent :mime-version:in-reply-to:content-language:content-transfer-encoding; bh=Eren9MLX7bzFjzWNgpuKzO0ZxiULws5PT2XeNzaV3mk=; b=vt7d/WjxHgqZ4rfBM2Boqfjy0fqwZRtQnv6QVXOQfkKRb1RVQ7OBoYYrBA0e0zHO/v F1ILRgO982EiuNMkkflR3gIjfnQNIIwRsu1nihJEqaNxN+VDYmVRictlAlttajZ0sNUD l4HMhVBYYvsO72WcTiFOc3cT1Jxx9Xg3gygVPk98QkVgwWOC2h9RSPk59WpB5NNZwsv0 hR6vVQUgafApwPiemnZcW7fXDdxN3yVRbyGNgy9yokLoaZpdBdnNkonhDnE1uF0hFYJf idRyj/eBBTmxHkdJdrmUfReOxcZwOpz8Sr+rQgPfoxR+h68En5+xIi9zutCxtpKuYufS yQpA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:subject:to:cc:references:from:message-id:date :user-agent:mime-version:in-reply-to:content-language :content-transfer-encoding; bh=Eren9MLX7bzFjzWNgpuKzO0ZxiULws5PT2XeNzaV3mk=; b=PGtqQ86t1MzdVT423vzpfN3oanNALnlrBww39ybak/XaN2n12PdNJKcFytpZXCFfez JQtoPTeW3mBllXm7cRDc7Agvdd39UItXAnv4DfwbGjaiEz6X8ITQ/M6ODRcc72Jyi8rT vv0VQPMT5gxup+8YMKwRTFKkgNF8ZYsB+sw1pg+7cIb9Ta56Oa+SNlGbtqrxJfJ73X1w qCUDRIdpdoU/8ONoz6Wn3XKEzXEH5zS1D4JJQzBSk9jXq4QUJGJqmuZwXilaGQFOoI8m GzAZkMBEQvlBDtxO0ACjggrXUUm9bTUHg/lZRqC3sUSpMKZsUgkkqr4n13RcnoZQhZeE 15Yw== X-Gm-Message-State: APjAAAXNwdnwurhvsd9OKoL/mjTw+L2Fe0Fp4HxF+jAtj+sMbvUMQ2XP q0/eqCnMdpgVnYs8i2K8pdriQA== X-Google-Smtp-Source: APXvYqzPfxbrhkosH1bAF1xjw5Fd+MK03TPU/srZz7hsp7GX1cRPwkh6K3QYcL6gBoQFSEzjVUpZ0Q== X-Received: by 2002:a63:d00f:: with SMTP id z15mr5779169pgf.143.1576711541896; Wed, 18 Dec 2019 15:25:41 -0800 (PST) Received: from ?IPv6:2605:e000:c74f:dc00:6838:d2b2:17e2:8445? ([2605:e000:c74f:dc00:6838:d2b2:17e2:8445]) by smtp.gmail.com with ESMTPSA id i127sm5108224pfe.54.2019.12.18.15.25.40 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 18 Dec 2019 15:25:41 -0800 (PST) Subject: Re: [PATCH v2 06/10] arm/arm-powerctl: rebuild hflags after setting CP15 bits in arm_set_cpu_on() To: Niek Linnenbank Cc: Peter Maydell , qemu-arm , =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= , QEMU Developers References: <20191216233519.29030-1-nieklinnenbank@gmail.com> <20191216233519.29030-7-nieklinnenbank@gmail.com> <19e4f2ac-6067-f61f-f340-108545fb0f02@linaro.org> From: Richard Henderson Message-ID: <6ec61650-30e1-4377-6b22-5b6ef827e69c@linaro.org> Date: Wed, 18 Dec 2019 13:25:37 -1000 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.2.2 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 8bit X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::542 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 18 Dec 2019 23:25:46 -0000 On 12/18/19 11:01 AM, Niek Linnenbank wrote: > Hello Richard, > > On Tue, Dec 17, 2019 at 5:41 PM Richard Henderson > wrote: > > On 12/17/19 6:12 AM, Peter Maydell wrote: > > Cc'ing Richard : this is one for you I think... (surely we > > need to rebuild the hflags from scratch when we power up > > a CPU anyway?) > > We do compute hflags from scratch in reset. > > It has also turned out that there were a few board models that poked at the > contents of the cpu and needed special help.  Some of that I would imagine > would be fixed properly with the multi-phase reset patches, where we could > rebuild hflags when *leaving* reset. > > In arm_set_cpu_on_async_work, we start by resetting the cpu and then start > poking at the contents of some system registers.  So, yes, we do need to > rebuild after doing that.  Also, I'm not sure how this function should fit into > the multi-phase reset future. > > > Great, thanks a lot for confirming and clarifying this! > You mention the multi-phase reset feature, is that going to replace the > arm_set_cpu_on() functionality? I don't think so, but I'm not sure. As I said above, I don't immediately see how arm_set_cpu_on() will integrate. In any case, multi-phase reset is still pending, though I believe it is high on Peter's priority queue for the 5.0 development cycle. r~ From MAILER-DAEMON Wed Dec 18 20:05:32 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1ihkFv-0000Bl-Sw for mharc-qemu-arm@gnu.org; Wed, 18 Dec 2019 20:05:31 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:47318) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ihkFs-00008f-9b for qemu-arm@nongnu.org; Wed, 18 Dec 2019 20:05:29 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ihkFo-0002KK-Td for qemu-arm@nongnu.org; Wed, 18 Dec 2019 20:05:26 -0500 Received: from us-smtp-1.mimecast.com ([205.139.110.61]:48782 helo=us-smtp-delivery-1.mimecast.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1ihkFo-0002II-Fm for qemu-arm@nongnu.org; Wed, 18 Dec 2019 20:05:24 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; 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Thu, 19 Dec 2019 01:05:13 +0000 (UTC) Date: Wed, 18 Dec 2019 20:05:11 -0500 From: Cleber Rosa To: Philippe =?iso-8859-1?Q?Mathieu-Daud=E9?= Cc: qemu-devel@nongnu.org, Guenter Roeck , Niek Linnenbank , Peter Maydell , qemu-arm@nongnu.org Subject: Re: [PATCH 1/5] tests/boot_linux_console: Add a quick test for the OrangePi PC board Message-ID: <20191219010511.GA3582@localhost.localdomain> References: <20191217182730.943-1-f4bug@amsat.org> <20191217182730.943-2-f4bug@amsat.org> MIME-Version: 1.0 In-Reply-To: <20191217182730.943-2-f4bug@amsat.org> X-Scanned-By: MIMEDefang 2.84 on 10.5.11.23 X-Mimecast-Spam-Score: 0 Content-Type: multipart/signed; micalg=pgp-sha256; protocol="application/pgp-signature"; boundary="T4sUOijqQbZv57TR" Content-Disposition: inline X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 205.139.110.61 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 19 Dec 2019 01:05:30 -0000 --T4sUOijqQbZv57TR Content-Type: text/plain; charset=iso-8859-1 Content-Disposition: inline Content-Transfer-Encoding: quoted-printable On Tue, Dec 17, 2019 at 07:27:26PM +0100, Philippe Mathieu-Daud=E9 wrote: > This test boots a Linux kernel on a OrangePi PC board and verify > the serial output is working. >=20 > The kernel image and DeviceTree blob are built by the Raspbian > project (based on Debian): > https://www.raspbian.org/RaspbianImages >=20 > If ARM is a target being built, "make check-acceptance" will > automatically include this test by the use of the "arch:arm" tags. >=20 > Alternatively, this test can be run using: >=20 > $ make check-venv > $ ./tests/venv/bin/avocado --show=3Dconsole,app run -t machine:orangepi= -pc tests/acceptance/boot_linux_console.py > JOB ID : 2e4d15eceb13c33672af406f08171e6e9de1414a > JOB LOG : ~/job-results/job-2019-12-17T05.46-2e4d15e/job.log > (1/1) tests/acceptance/boot_linux_console.py:BootLinuxConsole.test_arm_= orangepi: > console: Uncompressing Linux... done, booting the kernel. > console: Booting Linux on physical CPU 0x0 > console: Linux version 4.20.7-sunxi (root@armbian.com) (gcc version 7.2= .1 20171011 (Linaro GCC 7.2-2017.11)) #5.75 SMP Fri Feb 8 09:02:10 CET 2019 > console: CPU: ARMv7 Processor [410fc075] revision 5 (ARMv7), cr=3D50c53= 87d > console: CPU: div instructions available: patching division code > console: CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing instruc= tion cache > console: OF: fdt: Machine model: Xunlong Orange Pi PC > console: Memory policy: Data cache writealloc > console: OF: reserved mem: failed to allocate memory for node 'cma@4a00= 0000' > console: cma: Failed to reserve 128 MiB > console: psci: probing for conduit method from DT. > console: psci: PSCIv0.2 detected in firmware. > console: psci: Using standard PSCI v0.2 function IDs > console: psci: Trusted OS migration not required > console: random: get_random_bytes called from start_kernel+0x8d/0x3c2 w= ith crng_init=3D0 > console: percpu: Embedded 18 pages/cpu @(ptrval) s41228 r8192 d24308 u7= 3728 > console: Built 1 zonelists, mobility grouping on. Total pages: 32480 > console: Kernel command line: printk.time=3D0 console=3DttyS0,115200 > PASS (8.59 s) > JOB TIME : 8.81 s >=20 > Signed-off-by: Philippe Mathieu-Daud=E9 > --- > tests/acceptance/boot_linux_console.py | 26 ++++++++++++++++++++++++++ > 1 file changed, 26 insertions(+) >=20 > diff --git a/tests/acceptance/boot_linux_console.py b/tests/acceptance/bo= ot_linux_console.py > index 7e41cebd47..820239e439 100644 > --- a/tests/acceptance/boot_linux_console.py > +++ b/tests/acceptance/boot_linux_console.py > @@ -411,6 +411,32 @@ class BootLinuxConsole(Test): > self.wait_for_console_pattern('Boot successful.') > # TODO user command, for now the uart is stuck > =20 > + def test_arm_orangepi(self): Maybe rename the test to include the full machine type? I mean, "test_arm_orangepi_pc"? > + """ > + :avocado: tags=3Darch:arm > + :avocado: tags=3Dmachine:orangepi-pc > + """ > + deb_url =3D ('https://apt.armbian.com/pool/main/l/' > + 'linux-4.20.7-sunxi/linux-image-dev-sunxi_5.75_armhf.= deb') > + deb_hash =3D '1334c29c44d984ffa05ed10de8c3361f33d78315' > + deb_path =3D self.fetch_asset(deb_url, asset_hash=3Ddeb_hash) > + kernel_path =3D self.extract_from_deb(deb_path, > + '/boot/vmlinuz-4.20.7-sunxi'= ) > + dtb_path =3D '/usr/lib/linux-image-dev-sunxi/sun8i-h3-orangepi-p= c.dtb' > + dtb_path =3D self.extract_from_deb(deb_path, dtb_path) > + > + self.vm.set_machine('orangepi-pc') > + self.vm.set_console() > + kernel_command_line =3D (self.KERNEL_COMMON_COMMAND_LINE + > + 'console=3DttyS0,115200n8 ' > + 'earlycon=3Duart,mmio32,0x1c28000') > + self.vm.add_args('-kernel', kernel_path, > + '-dtb', dtb_path, > + '-append', kernel_command_line) > + self.vm.launch() > + console_pattern =3D 'Kernel command line: %s' % kernel_command_l= ine > + self.wait_for_console_pattern(console_pattern) > + > def test_s390x_s390_ccw_virtio(self): > """ > :avocado: tags=3Darch:s390x > --=20 > 2.21.0 >=20 Either way, Reviewed-by: Cleber Rosa Tested-by: Cleber Rosa --T4sUOijqQbZv57TR Content-Type: application/pgp-signature; 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Wed, 18 Dec 2019 23:06:38 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:47224) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ihn57-0005gu-Nk for qemu-arm@nongnu.org; Wed, 18 Dec 2019 23:06:35 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ihn53-0003gk-Ur for qemu-arm@nongnu.org; Wed, 18 Dec 2019 23:06:31 -0500 Received: from us-smtp-delivery-1.mimecast.com ([205.139.110.120]:33864 helo=us-smtp-1.mimecast.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1ihn53-0003bz-Ko for qemu-arm@nongnu.org; Wed, 18 Dec 2019 23:06:29 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1576728388; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding; bh=h61PaYXdE53o1HsslQmw6NieA6e1HNb0TnT6MMXOAY0=; b=dZNyQKtNUxuv7TgOr+TXWWG2yUFxaSv0caggicF3hV2JmEQtnf5p88DeJfjMcHpYFZX9RF lDmCjQ73G8FrpTvLObe/Qg2uPRvRY7uqfFtj+3zBVDNrc0i8s7AgEhQRMlnydswYcmTtuY mp1jMUs6Ki45CYulIuz+pGOErEwemw4= Received: from mimecast-mx01.redhat.com (mimecast-mx01.redhat.com [209.132.183.4]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-182-P8bUrv1XPCeMt36PxENRFw-1; Wed, 18 Dec 2019 23:06:25 -0500 Received: from smtp.corp.redhat.com (int-mx06.intmail.prod.int.phx2.redhat.com [10.5.11.16]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx01.redhat.com (Postfix) with ESMTPS id 015F818557C2; Thu, 19 Dec 2019 04:06:24 +0000 (UTC) Received: from localhost.localdomain.com (vpn2-54-48.bne.redhat.com [10.64.54.48]) by smtp.corp.redhat.com (Postfix) with ESMTP id 103CE5C298; Thu, 19 Dec 2019 04:06:18 +0000 (UTC) From: Gavin Shan To: qemu-arm@nongnu.org Cc: qemu-devel@nongnu.org, peter.maydell@linaro.org, drjones@redhat.com, eric.auger@redhat.com Subject: [RFC PATCH] hw/arm/virt: Support NMI injection Date: Thu, 19 Dec 2019 15:06:12 +1100 Message-Id: <20191219040612.28431-1-gshan@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.79 on 10.5.11.16 X-MC-Unique: P8bUrv1XPCeMt36PxENRFw-1 X-Mimecast-Spam-Score: 0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 205.139.110.120 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 19 Dec 2019 04:06:36 -0000 This supports NMI injection for virtual machine and currently it's only supported on GICv3 controller, which is emulated by qemu or host kernel. The design is highlighted as below: * The NMI is identified by its priority (0x20). In the guest (linux) kernel, the GICC_PMR is set to 0x80, to block all interrupts except the NMIs when the external interrupt is disabled. It means the FIQ and IRQ bit in PSTATE isn't touched when the functionality (NMI) is functional. * LPIs aren't considered as NMIs because of their nature. It means NMI is either SPI or PPI. Besides, the NMIs are injected in round-robin fashion is there are multiple NMIs existing. * When the GICv3 controller is emulated by qemu, the interrupt states (e.g. enabled, priority) is fetched from the corresponding data struct directly. However, we have to pause all CPUs to fetch the interrupt states from host in advance if the GICv3 controller is emulated by host. The testing scenario is to tweak guest (linux) kernel where the pl011 SPI can be enabled as NMI by request_nmi(). Check "/proc/interrupts" after inje= cting several NMIs, to see if the interrupt count is increased or not. The result is just as expected. Signed-off-by: Gavin Shan --- hw/arm/virt.c | 24 ++++++++ hw/intc/arm_gicv3.c | 76 ++++++++++++++++++++++++ hw/intc/arm_gicv3_kvm.c | 92 ++++++++++++++++++++++++++++++ include/hw/intc/arm_gicv3_common.h | 2 + 4 files changed, 194 insertions(+) diff --git a/hw/arm/virt.c b/hw/arm/virt.c index 39ab5f47e0..fc58ee70b4 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -71,6 +71,8 @@ #include "hw/mem/pc-dimm.h" #include "hw/mem/nvdimm.h" #include "hw/acpi/generic_event_device.h" +#include "hw/nmi.h" +#include "hw/intc/arm_gicv3.h" =20 #define DEFINE_VIRT_MACHINE_LATEST(major, minor, latest) \ static void virt_##major##_##minor##_class_init(ObjectClass *oc, \ @@ -1980,6 +1982,25 @@ static void virt_machine_device_unplug_request_cb(Ho= tplugHandler *hotplug_dev, " type: %s", object_get_typename(OBJECT(dev))); } =20 +static void virt_nmi(NMIState *n, int cpu_index, Error **errp) +{ + VirtMachineState *vms =3D VIRT_MACHINE(n); + ARMGICv3CommonClass *agcc; + + if (vms->gic_version !=3D 3) { + error_setg(errp, "NMI is only supported by GICv3"); + return; + } + + agcc =3D ARM_GICV3_COMMON_GET_CLASS(vms->gic); + if (agcc->inject_nmi) { + agcc->inject_nmi(vms->gic, cpu_index, errp); + } else { + error_setg(errp, "NMI injection isn't supported by %s", + object_get_typename(OBJECT(vms->gic))); + } +} + static HotplugHandler *virt_machine_get_hotplug_handler(MachineState *mach= ine, DeviceState *dev) { @@ -2025,6 +2046,7 @@ static void virt_machine_class_init(ObjectClass *oc, = void *data) { MachineClass *mc =3D MACHINE_CLASS(oc); HotplugHandlerClass *hc =3D HOTPLUG_HANDLER_CLASS(oc); + NMIClass *nc =3D NMI_CLASS(oc); =20 mc->init =3D machvirt_init; /* Start with max_cpus set to 512, which is the maximum supported by K= VM. @@ -2051,6 +2073,7 @@ static void virt_machine_class_init(ObjectClass *oc, = void *data) hc->pre_plug =3D virt_machine_device_pre_plug_cb; hc->plug =3D virt_machine_device_plug_cb; hc->unplug_request =3D virt_machine_device_unplug_request_cb; + nc->nmi_monitor_handler =3D virt_nmi; mc->numa_mem_supported =3D true; mc->auto_enable_numa_with_memhp =3D true; } @@ -2136,6 +2159,7 @@ static const TypeInfo virt_machine_info =3D { .instance_init =3D virt_instance_init, .interfaces =3D (InterfaceInfo[]) { { TYPE_HOTPLUG_HANDLER }, + { TYPE_NMI }, { } }, }; diff --git a/hw/intc/arm_gicv3.c b/hw/intc/arm_gicv3.c index 66eaa97198..d3409cb6ef 100644 --- a/hw/intc/arm_gicv3.c +++ b/hw/intc/arm_gicv3.c @@ -338,6 +338,81 @@ static void gicv3_set_irq(void *opaque, int irq, int l= evel) } } =20 +static bool arm_gicv3_inject_nmi_once(GICv3State*s, int start, int end) +{ + GICv3CPUState *cs; + int irq_count =3D (s->num_irq + (GIC_INTERNAL * (s->num_cpu - 1))); + int i, cpu, irq; + + /* SPIs */ + for (i =3D start; (i < end) && (i < (s->num_irq - GIC_INTERNAL)); i++)= { + if (gicv3_gicd_enabled_test(s, i + GIC_INTERNAL) && + s->gicd_ipriority[i + GIC_INTERNAL] =3D=3D 0x20) { + + /* + * Reset the level and toggling the pending bit will ensure + * the interrupt is queued. + */ + if (gicv3_gicd_level_test(s, i + GIC_INTERNAL)) { + gicv3_set_irq(s, i, false); + } + + gicv3_gicd_pending_set(s, i + GIC_INTERNAL); + gicv3_set_irq(s, i, true); + + s->last_nmi_index =3D (i + 1); + return true; + } + } + + /* PPIs */ + if (start < (s->num_irq - GIC_INTERNAL)) { + start =3D (s->num_irq - GIC_INTERNAL); + } + + for (i =3D start; (i < end) && (i < irq_count); i++) { + cpu =3D (i - ((s->num_irq - GIC_INTERNAL))) / GIC_INTERNAL; + irq =3D (i - ((s->num_irq - GIC_INTERNAL))) % GIC_INTERNAL; + cs =3D &s->cpu[cpu]; + + if ((cs->gicr_ienabler0 & (1 << irq)) && + cs->gicr_ipriorityr[irq] =3D=3D 0x20) { + + if (extract32(cs->level, irq, 1)) { + gicv3_set_irq(s, i, false); + } + + deposit32(cs->gicr_ipendr0, irq, 1, 1); + gicv3_set_irq(s, i, true); + + s->last_nmi_index =3D (i + 1); + if (s->last_nmi_index > irq_count) { + s->last_nmi_index =3D 0; + } + + return true; + } + } + + return false; +} + +static void arm_gicv3_inject_nmi(DeviceState *dev, int cpu_index, Error **= errp) +{ + GICv3State *s =3D ARM_GICV3(dev); + int irq_count =3D (s->num_irq + (GIC_INTERNAL * (s->num_cpu - 1))); + bool injected; + + injected =3D arm_gicv3_inject_nmi_once(s, s->last_nmi_index, irq_count= ); + if (!injected) { + injected =3D arm_gicv3_inject_nmi_once(s, 0, s->last_nmi_index); + } + + if (!injected) { + error_setg(errp, "No NMI found"); + } +} + static void arm_gicv3_post_load(GICv3State *s) { /* Recalculate our cached idea of the current highest priority @@ -395,6 +470,7 @@ static void arm_gicv3_class_init(ObjectClass *klass, vo= id *data) ARMGICv3CommonClass *agcc =3D ARM_GICV3_COMMON_CLASS(klass); ARMGICv3Class *agc =3D ARM_GICV3_CLASS(klass); =20 + agcc->inject_nmi =3D arm_gicv3_inject_nmi; agcc->post_load =3D arm_gicv3_post_load; device_class_set_parent_realize(dc, arm_gic_realize, &agc->parent_real= ize); } diff --git a/hw/intc/arm_gicv3_kvm.c b/hw/intc/arm_gicv3_kvm.c index 9c7f4ab871..b076d67c52 100644 --- a/hw/intc/arm_gicv3_kvm.c +++ b/hw/intc/arm_gicv3_kvm.c @@ -31,6 +31,7 @@ #include "gicv3_internal.h" #include "vgic_common.h" #include "migration/blocker.h" +#include "sysemu/cpus.h" =20 #ifdef DEBUG_GICV3_KVM #define DPRINTF(fmt, ...) \ @@ -506,6 +507,96 @@ static void kvm_arm_gicv3_put(GICv3State *s) } } =20 +static bool kvm_arm_gicv3_inject_nmi_once(GICv3State *s, int start, int en= d) +{ + GICv3CPUState *cs; + int irq_count =3D (s->num_irq + (GIC_INTERNAL * (s->num_cpu - 1))); + int i, cpu, irq; + + /* SPIs */ + for (i =3D start; (i < end) && (i < (s->num_irq - GIC_INTERNAL)); i++)= { + if (gicv3_gicd_enabled_test(s, i + GIC_INTERNAL) && + s->gicd_ipriority[i + GIC_INTERNAL] =3D=3D 0x20) { + kvm_arm_gicv3_set_irq(s, i, true); + + s->last_nmi_index =3D (i + 1); + return true; + } + } + + /* PPIs */ + if (start < (s->num_irq - GIC_INTERNAL)) { + start =3D (s->num_irq - GIC_INTERNAL); + } + + for (i =3D start; (i < end) && (i < irq_count); i++) { + cpu =3D (i - ((s->num_irq - GIC_INTERNAL))) / GIC_INTERNAL; + irq =3D (i - ((s->num_irq - GIC_INTERNAL))) % GIC_INTERNAL; + cs =3D &s->cpu[cpu]; + + if ((cs->gicr_ienabler0 & (1 << irq)) && + cs->gicr_ipriorityr[irq] =3D=3D 0x20) { + kvm_arm_gicv3_set_irq(s, i, true); + + s->last_nmi_index =3D (i + 1); + if (s->last_nmi_index > irq_count) { + s->last_nmi_index =3D 0; + } + + return true; + } + } + + return false; +} + +static void kvm_arm_gicv3_snapshot(GICv3State *s) +{ + GICv3CPUState *c; + uint32_t val; + int i, j; + + pause_all_vcpus(); + + kvm_dist_getbmp(s, GICD_ISENABLER, s->enabled); + kvm_dist_get_priority(s, GICD_IPRIORITYR, s->gicd_ipriority); + for (i =3D 0; i < s->num_cpu; i++) { + c =3D &s->cpu[i]; + + kvm_gicr_access(s, GICR_ISENABLER0, i, &val, false); + c->gicr_ienabler0 =3D val; + + for (j =3D 0; j < GIC_INTERNAL; j +=3D 4) { + kvm_gicr_access(s, GICR_IPRIORITYR + j, i, &val, false); + c->gicr_ipriorityr[j] =3D extract32(val, 0, 8); + c->gicr_ipriorityr[j + 1] =3D extract32(val, 8, 8); + c->gicr_ipriorityr[j + 2] =3D extract32(val, 16, 8); + c->gicr_ipriorityr[j + 3] =3D extract32(val, 24, 8); + } + } + + resume_all_vcpus(); +} + +static void kvm_arm_gicv3_inject_nmi(DeviceState *dev, + int cpu_index, Error **errp) +{ + GICv3State *s =3D KVM_ARM_GICV3(dev); + int irq_count =3D (s->num_irq + (GIC_INTERNAL * (s->num_cpu - 1))); + bool injected; + + kvm_arm_gicv3_snapshot(s); + + injected =3D kvm_arm_gicv3_inject_nmi_once(s, s->last_nmi_index, irq_c= ount); + if (!injected) { + injected =3D kvm_arm_gicv3_inject_nmi_once(s, 0, s->last_nmi_index= ); + } + + if (!injected) { + error_setg(errp, "No NMI found"); + } +} + static void kvm_arm_gicv3_get(GICv3State *s) { uint32_t regl, regh, reg; @@ -882,6 +973,7 @@ static void kvm_arm_gicv3_class_init(ObjectClass *klass= , void *data) ARMGICv3CommonClass *agcc =3D ARM_GICV3_COMMON_CLASS(klass); KVMARMGICv3Class *kgc =3D KVM_ARM_GICV3_CLASS(klass); =20 + agcc->inject_nmi =3D kvm_arm_gicv3_inject_nmi; agcc->pre_save =3D kvm_arm_gicv3_get; agcc->post_load =3D kvm_arm_gicv3_put; device_class_set_parent_realize(dc, kvm_arm_gicv3_realize, diff --git a/include/hw/intc/arm_gicv3_common.h b/include/hw/intc/arm_gicv3= _common.h index 31ec9a1ae4..0ae9c45aa2 100644 --- a/include/hw/intc/arm_gicv3_common.h +++ b/include/hw/intc/arm_gicv3_common.h @@ -225,6 +225,7 @@ struct GICv3State { =20 int dev_fd; /* kvm device fd if backed by kvm vgic support */ Error *migration_blocker; + int last_nmi_index; =20 /* Distributor */ =20 @@ -291,6 +292,7 @@ typedef struct ARMGICv3CommonClass { SysBusDeviceClass parent_class; /*< public >*/ =20 + void (*inject_nmi)(DeviceState *dev, int cpu_index, Error **errp); void (*pre_save)(GICv3State *s); void (*post_load)(GICv3State *s); } ARMGICv3CommonClass; --=20 2.23.0 From MAILER-DAEMON Thu Dec 19 00:22:50 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1ihoGw-0004RS-80 for mharc-qemu-arm@gnu.org; Thu, 19 Dec 2019 00:22:50 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:55366) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ihoGt-0004R3-Hu for qemu-arm@nongnu.org; Thu, 19 Dec 2019 00:22:48 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ihoGs-00026V-GF for qemu-arm@nongnu.org; Thu, 19 Dec 2019 00:22:47 -0500 Received: from wout4-smtp.messagingengine.com ([64.147.123.20]:34549) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1ihoGr-0001qh-W4; Thu, 19 Dec 2019 00:22:46 -0500 Received: from compute7.internal (compute7.nyi.internal [10.202.2.47]) by mailout.west.internal (Postfix) with ESMTP id 484BA48A; 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Thu, 19 Dec 2019 00:22:41 -0500 (EST) From: Alistair Francis To: qemu-devel@nongnu.org, peter.maydell@linaro.org, qemu-arm@nongnu.org, philmd@redhat.com Cc: alistair23@gmail.com Subject: [PATCH v7 0/4] Add the STM32F405 and Netduino Plus 2 machine Date: Wed, 18 Dec 2019 21:22:40 -0800 Message-Id: X-Mailer: git-send-email 2.24.0 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 64.147.123.20 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 19 Dec 2019 05:22:48 -0000 Now that the Arm-M4 CPU has been added to QEMU we can add the Netduino Plus 2 machine. This is very similar to the STM32F205 and Netduino 2 SoC and machine. v7: - Fix the EXTI IRQ - Remove the duplicate configs v6: - Remove machine specific reset code - Rebase on master v5: - Fix checkpatch failures - Add mising includes v4: - Rebase on master v3: - Remove custom reset handler - Add init-entry and init-sp properties - Rebase on master (including Kconfig changes) v2: - Reorder patchset - Return the kernel entry point instead of using a pointer - Address Peter's comments Alistair Francis (4): hw/misc: Add the STM32F4xx Sysconfig device hw/misc: Add the STM32F4xx EXTI device hw/arm: Add the STM32F4xx SoC hw/arm: Add the Netduino Plus 2 MAINTAINERS | 14 ++ default-configs/arm-softmmu.mak | 1 + hw/arm/Kconfig | 10 + hw/arm/Makefile.objs | 2 + hw/arm/netduinoplus2.c | 52 +++++ hw/arm/stm32f405_soc.c | 302 +++++++++++++++++++++++++++++ hw/misc/Kconfig | 6 + hw/misc/Makefile.objs | 2 + hw/misc/stm32f4xx_exti.c | 188 ++++++++++++++++++ hw/misc/stm32f4xx_syscfg.c | 171 ++++++++++++++++ hw/misc/trace-events | 11 ++ include/hw/arm/stm32f405_soc.h | 73 +++++++ include/hw/misc/stm32f4xx_exti.h | 60 ++++++ include/hw/misc/stm32f4xx_syscfg.h | 61 ++++++ 14 files changed, 953 insertions(+) create mode 100644 hw/arm/netduinoplus2.c create mode 100644 hw/arm/stm32f405_soc.c create mode 100644 hw/misc/stm32f4xx_exti.c create mode 100644 hw/misc/stm32f4xx_syscfg.c create mode 100644 include/hw/arm/stm32f405_soc.h create mode 100644 include/hw/misc/stm32f4xx_exti.h create mode 100644 include/hw/misc/stm32f4xx_syscfg.h -- 2.24.0 From MAILER-DAEMON Thu Dec 19 00:22:53 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1ihoGz-0004Tb-03 for mharc-qemu-arm@gnu.org; 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Thu, 19 Dec 2019 00:22:45 -0500 (EST) From: Alistair Francis To: qemu-devel@nongnu.org, peter.maydell@linaro.org, qemu-arm@nongnu.org, philmd@redhat.com Cc: alistair23@gmail.com Subject: [PATCH v7 1/4] hw/misc: Add the STM32F4xx Sysconfig device Date: Wed, 18 Dec 2019 21:22:44 -0800 Message-Id: <49b01423a09cef2ca832ff73a84a996568f1a8fc.1576658572.git.alistair@alistair23.me> X-Mailer: git-send-email 2.24.0 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 64.147.123.20 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 19 Dec 2019 05:22:52 -0000 Signed-off-by: Alistair Francis Reviewed-by: Peter Maydell --- default-configs/arm-softmmu.mak | 1 + hw/arm/Kconfig | 9 ++ hw/misc/Kconfig | 3 + hw/misc/Makefile.objs | 1 + hw/misc/stm32f4xx_syscfg.c | 171 +++++++++++++++++++++++++++++ hw/misc/trace-events | 6 + include/hw/misc/stm32f4xx_syscfg.h | 61 ++++++++++ 7 files changed, 252 insertions(+) create mode 100644 hw/misc/stm32f4xx_syscfg.c create mode 100644 include/hw/misc/stm32f4xx_syscfg.h diff --git a/default-configs/arm-softmmu.mak b/default-configs/arm-softmmu.mak index 1f2e0e7fde..645e6201bb 100644 --- a/default-configs/arm-softmmu.mak +++ b/default-configs/arm-softmmu.mak @@ -30,6 +30,7 @@ CONFIG_Z2=y CONFIG_COLLIE=y CONFIG_ASPEED_SOC=y CONFIG_NETDUINO2=y +CONFIG_NETDUINOPLUS2=y CONFIG_MPS2=y CONFIG_RASPI=y CONFIG_DIGIC=y diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig index c6e7782580..4660d14715 100644 --- a/hw/arm/Kconfig +++ b/hw/arm/Kconfig @@ -101,6 +101,10 @@ config NETDUINO2 bool select STM32F205_SOC +config NETDUINOPLUS2 + bool + select STM32F405_SOC + config NSERIES bool select OMAP @@ -307,6 +311,11 @@ config STM32F205_SOC select STM32F2XX_ADC select STM32F2XX_SPI +config STM32F405_SOC + bool + select ARM_V7M + select STM32F4XX_SYSCFG + config XLNX_ZYNQMP_ARM bool select AHCI diff --git a/hw/misc/Kconfig b/hw/misc/Kconfig index 2164646553..72609650b7 100644 --- a/hw/misc/Kconfig +++ b/hw/misc/Kconfig @@ -82,6 +82,9 @@ config IMX config STM32F2XX_SYSCFG bool +config STM32F4XX_SYSCFG + bool + config MIPS_ITU bool diff --git a/hw/misc/Makefile.objs b/hw/misc/Makefile.objs index ba898a5781..ea8025e0bb 100644 --- a/hw/misc/Makefile.objs +++ b/hw/misc/Makefile.objs @@ -58,6 +58,7 @@ common-obj-$(CONFIG_SLAVIO) += slavio_misc.o common-obj-$(CONFIG_ZYNQ) += zynq_slcr.o common-obj-$(CONFIG_ZYNQ) += zynq-xadc.o common-obj-$(CONFIG_STM32F2XX_SYSCFG) += stm32f2xx_syscfg.o +common-obj-$(CONFIG_STM32F4XX_SYSCFG) += stm32f4xx_syscfg.o obj-$(CONFIG_MIPS_CPS) += mips_cmgcr.o obj-$(CONFIG_MIPS_CPS) += mips_cpc.o obj-$(CONFIG_MIPS_ITU) += mips_itu.o diff --git a/hw/misc/stm32f4xx_syscfg.c b/hw/misc/stm32f4xx_syscfg.c new file mode 100644 index 0000000000..dbcdca59f8 --- /dev/null +++ b/hw/misc/stm32f4xx_syscfg.c @@ -0,0 +1,171 @@ +/* + * STM32F4xx SYSCFG + * + * Copyright (c) 2014 Alistair Francis + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#include "qemu/osdep.h" +#include "qemu/log.h" +#include "trace.h" +#include "hw/irq.h" +#include "migration/vmstate.h" +#include "hw/misc/stm32f4xx_syscfg.h" + +static void stm32f4xx_syscfg_reset(DeviceState *dev) +{ + STM32F4xxSyscfgState *s = STM32F4XX_SYSCFG(dev); + + s->syscfg_memrmp = 0x00000000; + s->syscfg_pmc = 0x00000000; + s->syscfg_exticr[0] = 0x00000000; + s->syscfg_exticr[1] = 0x00000000; + s->syscfg_exticr[2] = 0x00000000; + s->syscfg_exticr[3] = 0x00000000; + s->syscfg_cmpcr = 0x00000000; +} + +static void stm32f4xx_syscfg_set_irq(void *opaque, int irq, int level) +{ + STM32F4xxSyscfgState *s = opaque; + int icrreg = irq / 4; + int startbit = (irq & 3) * 4; + uint8_t config = config = irq / 16; + + trace_stm32f4xx_syscfg_set_irq(irq / 16, irq % 16, level); + + g_assert(icrreg < SYSCFG_NUM_EXTICR); + + if (extract32(s->syscfg_exticr[icrreg], startbit, 4) == config) { + qemu_set_irq(s->gpio_out[irq], level); + trace_stm32f4xx_pulse_exti(irq); + } +} + +static uint64_t stm32f4xx_syscfg_read(void *opaque, hwaddr addr, + unsigned int size) +{ + STM32F4xxSyscfgState *s = opaque; + + trace_stm32f4xx_syscfg_read(addr); + + switch (addr) { + case SYSCFG_MEMRMP: + return s->syscfg_memrmp; + case SYSCFG_PMC: + return s->syscfg_pmc; + case SYSCFG_EXTICR1...SYSCFG_EXTICR4: + return s->syscfg_exticr[addr / 4 - SYSCFG_EXTICR1 / 4]; + case SYSCFG_CMPCR: + return s->syscfg_cmpcr; + default: + qemu_log_mask(LOG_GUEST_ERROR, + "%s: Bad offset 0x%"HWADDR_PRIx"\n", __func__, addr); + return 0; + } +} + +static void stm32f4xx_syscfg_write(void *opaque, hwaddr addr, + uint64_t val64, unsigned int size) +{ + STM32F4xxSyscfgState *s = opaque; + uint32_t value = val64; + + trace_stm32f4xx_syscfg_write(value, addr); + + switch (addr) { + case SYSCFG_MEMRMP: + qemu_log_mask(LOG_UNIMP, + "%s: Changing the memory mapping isn't supported " \ + "in QEMU\n", __func__); + return; + case SYSCFG_PMC: + qemu_log_mask(LOG_UNIMP, + "%s: Changing the memory mapping isn't supported " \ + "in QEMU\n", __func__); + return; + case SYSCFG_EXTICR1...SYSCFG_EXTICR4: + s->syscfg_exticr[addr / 4 - SYSCFG_EXTICR1 / 4] = (value & 0xFFFF); + return; + case SYSCFG_CMPCR: + s->syscfg_cmpcr = value; + return; + default: + qemu_log_mask(LOG_GUEST_ERROR, + "%s: Bad offset 0x%"HWADDR_PRIx"\n", __func__, addr); + } +} + +static const MemoryRegionOps stm32f4xx_syscfg_ops = { + .read = stm32f4xx_syscfg_read, + .write = stm32f4xx_syscfg_write, + .endianness = DEVICE_NATIVE_ENDIAN, +}; + +static void stm32f4xx_syscfg_init(Object *obj) +{ + STM32F4xxSyscfgState *s = STM32F4XX_SYSCFG(obj); + + sysbus_init_irq(SYS_BUS_DEVICE(obj), &s->irq); + + memory_region_init_io(&s->mmio, obj, &stm32f4xx_syscfg_ops, s, + TYPE_STM32F4XX_SYSCFG, 0x400); + sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->mmio); + + qdev_init_gpio_in(DEVICE(obj), stm32f4xx_syscfg_set_irq, 16 * 9); + qdev_init_gpio_out(DEVICE(obj), s->gpio_out, 16); +} + +static const VMStateDescription vmstate_stm32f4xx_syscfg = { + .name = TYPE_STM32F4XX_SYSCFG, + .version_id = 1, + .minimum_version_id = 1, + .fields = (VMStateField[]) { + VMSTATE_UINT32(syscfg_memrmp, STM32F4xxSyscfgState), + VMSTATE_UINT32(syscfg_pmc, STM32F4xxSyscfgState), + VMSTATE_UINT32_ARRAY(syscfg_exticr, STM32F4xxSyscfgState, + SYSCFG_NUM_EXTICR), + VMSTATE_UINT32(syscfg_cmpcr, STM32F4xxSyscfgState), + VMSTATE_END_OF_LIST() + } +}; + +static void stm32f4xx_syscfg_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + + dc->reset = stm32f4xx_syscfg_reset; + dc->vmsd = &vmstate_stm32f4xx_syscfg; +} + +static const TypeInfo stm32f4xx_syscfg_info = { + .name = TYPE_STM32F4XX_SYSCFG, + .parent = TYPE_SYS_BUS_DEVICE, + .instance_size = sizeof(STM32F4xxSyscfgState), + .instance_init = stm32f4xx_syscfg_init, + .class_init = stm32f4xx_syscfg_class_init, +}; + +static void stm32f4xx_syscfg_register_types(void) +{ + type_register_static(&stm32f4xx_syscfg_info); +} + +type_init(stm32f4xx_syscfg_register_types) diff --git a/hw/misc/trace-events b/hw/misc/trace-events index 1deb1d08c1..02327562bc 100644 --- a/hw/misc/trace-events +++ b/hw/misc/trace-events @@ -84,6 +84,12 @@ mos6522_set_sr_int(void) "set sr_int" mos6522_write(uint64_t addr, uint64_t val) "reg=0x%"PRIx64 " val=0x%"PRIx64 mos6522_read(uint64_t addr, unsigned val) "reg=0x%"PRIx64 " val=0x%x" +# stm32f4xx_syscfg +stm32f4xx_syscfg_set_irq(int gpio, int line, int level) "Interupt: GPIO: %d, Line: %d; Level: %d" +stm32f4xx_pulse_exti(int irq) "Pulse EXTI: %d" +stm32f4xx_syscfg_read(uint64_t addr) "reg read: addr: 0x%" PRIx64 " " +stm32f4xx_syscfg_write(uint64_t addr, uint64_t data) "reg write: addr: 0x%" PRIx64 " val: 0x%" PRIx64 "" + # tz-mpc.c tz_mpc_reg_read(uint32_t offset, uint64_t data, unsigned size) "TZ MPC regs read: offset 0x%x data 0x%" PRIx64 " size %u" tz_mpc_reg_write(uint32_t offset, uint64_t data, unsigned size) "TZ MPC regs write: offset 0x%x data 0x%" PRIx64 " size %u" diff --git a/include/hw/misc/stm32f4xx_syscfg.h b/include/hw/misc/stm32f4xx_syscfg.h new file mode 100644 index 0000000000..c62c6629e5 --- /dev/null +++ b/include/hw/misc/stm32f4xx_syscfg.h @@ -0,0 +1,61 @@ +/* + * STM32F4xx SYSCFG + * + * Copyright (c) 2014 Alistair Francis + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#ifndef HW_STM_SYSCFG_H +#define HW_STM_SYSCFG_H + +#include "hw/sysbus.h" +#include "hw/hw.h" + +#define SYSCFG_MEMRMP 0x00 +#define SYSCFG_PMC 0x04 +#define SYSCFG_EXTICR1 0x08 +#define SYSCFG_EXTICR2 0x0C +#define SYSCFG_EXTICR3 0x10 +#define SYSCFG_EXTICR4 0x14 +#define SYSCFG_CMPCR 0x20 + +#define TYPE_STM32F4XX_SYSCFG "stm32f4xx-syscfg" +#define STM32F4XX_SYSCFG(obj) \ + OBJECT_CHECK(STM32F4xxSyscfgState, (obj), TYPE_STM32F4XX_SYSCFG) + +#define SYSCFG_NUM_EXTICR 4 + +typedef struct { + /* */ + SysBusDevice parent_obj; + + /* */ + MemoryRegion mmio; + + uint32_t syscfg_memrmp; + uint32_t syscfg_pmc; + uint32_t syscfg_exticr[SYSCFG_NUM_EXTICR]; + uint32_t syscfg_cmpcr; + + qemu_irq irq; + qemu_irq gpio_out[16]; +} STM32F4xxSyscfgState; + +#endif -- 2.24.0 From MAILER-DAEMON Thu Dec 19 00:22:59 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1ihoH5-0004dL-Jz for mharc-qemu-arm@gnu.org; Thu, 19 Dec 2019 00:22:59 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:56796) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ihoH1-0004Yc-Ts for qemu-arm@nongnu.org; Thu, 19 Dec 2019 00:22:57 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ihoGz-0002kN-L4 for qemu-arm@nongnu.org; Thu, 19 Dec 2019 00:22:55 -0500 Received: from wout4-smtp.messagingengine.com ([64.147.123.20]:49285) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1ihoGz-0002Wm-Bw; Thu, 19 Dec 2019 00:22:53 -0500 Received: from compute7.internal (compute7.nyi.internal [10.202.2.47]) by mailout.west.internal (Postfix) with ESMTP id 3FE4C48C; Thu, 19 Dec 2019 00:22:50 -0500 (EST) Received: from mailfrontend1 ([10.202.2.162]) by compute7.internal (MEProxy); Thu, 19 Dec 2019 00:22:50 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=alistair23.me; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; s=fm2; bh=mkb9XvzbP8BUx 9v/BWnZw9OFlGMX5weIvYh+iI7dGAw=; b=1iK6pMtr4EZIoHc5s3T0CX7XV/Xdp HLgTxjpDolkG2dHcm2cqOn3FtvFoOdIHXlsvOOi+B2ddzt8mc2RwIzE+0A43RDoF /H8k/Oy5QG47+7DZ+PZ8TFA0DMW7eErpzKzF6NzV4C0qKkx/EN01BwOs3j6gxtj3 Pa5Fd5hpXS4eN7plTg9klcEu1VCNEfzxi2W3YPU2c89wL8Yxs8CuKXnVnD2dy0FH PVhkZn0U+psjlKozPSHmT5HMPLrSLO1friRV49LgTh4mDg7sIEGYNUdISHm355N4 qJ0gDYv9/Cj2cU7EgwmjGO497nTphhDVZV5x6ID5q1+HhDtkpCdONYBDg== DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d= messagingengine.com; h=cc:content-transfer-encoding:date:from :in-reply-to:message-id:mime-version:references:subject:to :x-me-proxy:x-me-proxy:x-me-sender:x-me-sender:x-sasl-enc; s= fm1; bh=mkb9XvzbP8BUx9v/BWnZw9OFlGMX5weIvYh+iI7dGAw=; b=U4UneaZN XzP9q2OoudJjP9WKgTjQSmvfCRvQf+aRPnZFhqeSGMxRqpOA+GCAKbKEKplfmSzf RdoS97uYViWlCD+IwwJC2vYT2SM4usHmMLux69ehHtIJeY0r6dqEOM//FR9WHVXK 0xZ8Fsn0k/3J1YWvfi1V3RdvS0RucOKJgoKHlWON3pGf9pkuvYoWLYTfreg6+wuk ojVs4vJc53WiQxb/uTQQZ1lMEWFdz5qQt3vHrkOpEVkbikcXgIQSBwX6u+D8YvTd JVjDatggXpgINgip0NvgAwraOssQyJCzoaROwwkADQLTnKoiSazBudfLyiiadQWH MCqWi0kyYjNRRg== X-ME-Sender: X-ME-Proxy-Cause: gggruggvucftvghtrhhoucdtuddrgedufedrvddutddgkeduucetufdoteggodetrfdotf fvucfrrhhofhhilhgvmecuhfgrshhtofgrihhlpdfqfgfvpdfurfetoffkrfgpnffqhgen uceurghilhhouhhtmecufedttdenucenucfjughrpefhvffufffkofgjfhgggfestdekre dtredttdenucfhrhhomheptehlihhsthgrihhrucfhrhgrnhgtihhsuceorghlihhsthgr ihhrsegrlhhishhtrghirhdvfedrmhgvqeenucfkphepjeefrdelfedrkeegrddvtdekne curfgrrhgrmhepmhgrihhlfhhrohhmpegrlhhishhtrghirhesrghlihhsthgrihhrvdef rdhmvgenucevlhhushhtvghrufhiiigvpedu X-ME-Proxy: Received: from alistair-xps-14z.alistair23.me (c-73-93-84-208.hsd1.ca.comcast.net [73.93.84.208]) by mail.messagingengine.com (Postfix) with ESMTPA id 0B33080060; Thu, 19 Dec 2019 00:22:48 -0500 (EST) From: Alistair Francis To: qemu-devel@nongnu.org, peter.maydell@linaro.org, qemu-arm@nongnu.org, philmd@redhat.com Cc: alistair23@gmail.com Subject: [PATCH v7 2/4] hw/misc: Add the STM32F4xx EXTI device Date: Wed, 18 Dec 2019 21:22:48 -0800 Message-Id: X-Mailer: git-send-email 2.24.0 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 64.147.123.20 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 19 Dec 2019 05:22:58 -0000 Signed-off-by: Alistair Francis Reviewed-by: Peter Maydell --- hw/arm/Kconfig | 1 + hw/misc/Kconfig | 3 + hw/misc/Makefile.objs | 1 + hw/misc/stm32f4xx_exti.c | 188 +++++++++++++++++++++++++++++++ hw/misc/trace-events | 5 + include/hw/misc/stm32f4xx_exti.h | 60 ++++++++++ 6 files changed, 258 insertions(+) create mode 100644 hw/misc/stm32f4xx_exti.c create mode 100644 include/hw/misc/stm32f4xx_exti.h diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig index 4660d14715..3d86691ae0 100644 --- a/hw/arm/Kconfig +++ b/hw/arm/Kconfig @@ -315,6 +315,7 @@ config STM32F405_SOC bool select ARM_V7M select STM32F4XX_SYSCFG + select STM32F4XX_EXTI config XLNX_ZYNQMP_ARM bool diff --git a/hw/misc/Kconfig b/hw/misc/Kconfig index 72609650b7..bdd77d8020 100644 --- a/hw/misc/Kconfig +++ b/hw/misc/Kconfig @@ -85,6 +85,9 @@ config STM32F2XX_SYSCFG config STM32F4XX_SYSCFG bool +config STM32F4XX_EXTI + bool + config MIPS_ITU bool diff --git a/hw/misc/Makefile.objs b/hw/misc/Makefile.objs index ea8025e0bb..c6ecbdd7b0 100644 --- a/hw/misc/Makefile.objs +++ b/hw/misc/Makefile.objs @@ -59,6 +59,7 @@ common-obj-$(CONFIG_ZYNQ) += zynq_slcr.o common-obj-$(CONFIG_ZYNQ) += zynq-xadc.o common-obj-$(CONFIG_STM32F2XX_SYSCFG) += stm32f2xx_syscfg.o common-obj-$(CONFIG_STM32F4XX_SYSCFG) += stm32f4xx_syscfg.o +common-obj-$(CONFIG_STM32F4XX_EXTI) += stm32f4xx_exti.o obj-$(CONFIG_MIPS_CPS) += mips_cmgcr.o obj-$(CONFIG_MIPS_CPS) += mips_cpc.o obj-$(CONFIG_MIPS_ITU) += mips_itu.o diff --git a/hw/misc/stm32f4xx_exti.c b/hw/misc/stm32f4xx_exti.c new file mode 100644 index 0000000000..02e7810046 --- /dev/null +++ b/hw/misc/stm32f4xx_exti.c @@ -0,0 +1,188 @@ +/* + * STM32F4XX EXTI + * + * Copyright (c) 2014 Alistair Francis + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#include "qemu/osdep.h" +#include "qemu/log.h" +#include "trace.h" +#include "hw/irq.h" +#include "migration/vmstate.h" +#include "hw/misc/stm32f4xx_exti.h" + +static void stm32f4xx_exti_reset(DeviceState *dev) +{ + STM32F4xxExtiState *s = STM32F4XX_EXTI(dev); + + s->exti_imr = 0x00000000; + s->exti_emr = 0x00000000; + s->exti_rtsr = 0x00000000; + s->exti_ftsr = 0x00000000; + s->exti_swier = 0x00000000; + s->exti_pr = 0x00000000; +} + +static void stm32f4xx_exti_set_irq(void *opaque, int irq, int level) +{ + STM32F4xxExtiState *s = opaque; + + trace_stm32f4xx_exti_set_irq(irq, level); + + if (((1 << irq) & s->exti_rtsr) && level) { + /* Rising Edge */ + s->exti_pr |= 1 << irq; + } + + if (((1 << irq) & s->exti_ftsr) && !level) { + /* Falling Edge */ + s->exti_pr |= 1 << irq; + } + + if (!((1 << irq) & s->exti_imr)) { + /* Interrupt is masked */ + return; + } + qemu_irq_pulse(s->irq[irq]); +} + +static uint64_t stm32f4xx_exti_read(void *opaque, hwaddr addr, + unsigned int size) +{ + STM32F4xxExtiState *s = opaque; + + trace_stm32f4xx_exti_read(addr); + + switch (addr) { + case EXTI_IMR: + return s->exti_imr; + case EXTI_EMR: + return s->exti_emr; + case EXTI_RTSR: + return s->exti_rtsr; + case EXTI_FTSR: + return s->exti_ftsr; + case EXTI_SWIER: + return s->exti_swier; + case EXTI_PR: + return s->exti_pr; + default: + qemu_log_mask(LOG_GUEST_ERROR, + "STM32F4XX_exti_read: Bad offset %x\n", (int)addr); + return 0; + } + return 0; +} + +static void stm32f4xx_exti_write(void *opaque, hwaddr addr, + uint64_t val64, unsigned int size) +{ + STM32F4xxExtiState *s = opaque; + uint32_t value = (uint32_t) val64; + + trace_stm32f4xx_exti_write(addr, value); + + switch (addr) { + case EXTI_IMR: + s->exti_imr = value; + return; + case EXTI_EMR: + s->exti_emr = value; + return; + case EXTI_RTSR: + s->exti_rtsr = value; + return; + case EXTI_FTSR: + s->exti_ftsr = value; + return; + case EXTI_SWIER: + s->exti_swier = value; + return; + case EXTI_PR: + /* This bit is cleared by writing a 1 to it */ + s->exti_pr &= ~value; + return; + default: + qemu_log_mask(LOG_GUEST_ERROR, + "STM32F4XX_exti_write: Bad offset %x\n", (int)addr); + } +} + +static const MemoryRegionOps stm32f4xx_exti_ops = { + .read = stm32f4xx_exti_read, + .write = stm32f4xx_exti_write, + .endianness = DEVICE_NATIVE_ENDIAN, +}; + +static void stm32f4xx_exti_init(Object *obj) +{ + STM32F4xxExtiState *s = STM32F4XX_EXTI(obj); + int i; + + for (i = 0; i < NUM_INTERRUPT_OUT_LINES; i++) { + sysbus_init_irq(SYS_BUS_DEVICE(obj), &s->irq[i]); + } + + memory_region_init_io(&s->mmio, obj, &stm32f4xx_exti_ops, s, + TYPE_STM32F4XX_EXTI, 0x400); + sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->mmio); + + qdev_init_gpio_in(DEVICE(obj), stm32f4xx_exti_set_irq, + NUM_GPIO_EVENT_IN_LINES); +} + +static const VMStateDescription vmstate_stm32f4xx_exti = { + .name = TYPE_STM32F4XX_EXTI, + .version_id = 1, + .minimum_version_id = 1, + .fields = (VMStateField[]) { + VMSTATE_UINT32(exti_imr, STM32F4xxExtiState), + VMSTATE_UINT32(exti_emr, STM32F4xxExtiState), + VMSTATE_UINT32(exti_rtsr, STM32F4xxExtiState), + VMSTATE_UINT32(exti_ftsr, STM32F4xxExtiState), + VMSTATE_UINT32(exti_swier, STM32F4xxExtiState), + VMSTATE_UINT32(exti_pr, STM32F4xxExtiState), + VMSTATE_END_OF_LIST() + } +}; + +static void stm32f4xx_exti_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + + dc->reset = stm32f4xx_exti_reset; + dc->vmsd = &vmstate_stm32f4xx_exti; +} + +static const TypeInfo stm32f4xx_exti_info = { + .name = TYPE_STM32F4XX_EXTI, + .parent = TYPE_SYS_BUS_DEVICE, + .instance_size = sizeof(STM32F4xxExtiState), + .instance_init = stm32f4xx_exti_init, + .class_init = stm32f4xx_exti_class_init, +}; + +static void stm32f4xx_exti_register_types(void) +{ + type_register_static(&stm32f4xx_exti_info); +} + +type_init(stm32f4xx_exti_register_types) diff --git a/hw/misc/trace-events b/hw/misc/trace-events index 02327562bc..91a3794d68 100644 --- a/hw/misc/trace-events +++ b/hw/misc/trace-events @@ -90,6 +90,11 @@ stm32f4xx_pulse_exti(int irq) "Pulse EXTI: %d" stm32f4xx_syscfg_read(uint64_t addr) "reg read: addr: 0x%" PRIx64 " " stm32f4xx_syscfg_write(uint64_t addr, uint64_t data) "reg write: addr: 0x%" PRIx64 " val: 0x%" PRIx64 "" +# stm32f4xx_exti +stm32f4xx_exti_set_irq(int irq, int leve) "Set EXTI: %d to %d" +stm32f4xx_exti_read(uint64_t addr) "reg read: addr: 0x%" PRIx64 " " +stm32f4xx_exti_write(uint64_t addr, uint64_t data) "reg write: addr: 0x%" PRIx64 " val: 0x%" PRIx64 "" + # tz-mpc.c tz_mpc_reg_read(uint32_t offset, uint64_t data, unsigned size) "TZ MPC regs read: offset 0x%x data 0x%" PRIx64 " size %u" tz_mpc_reg_write(uint32_t offset, uint64_t data, unsigned size) "TZ MPC regs write: offset 0x%x data 0x%" PRIx64 " size %u" diff --git a/include/hw/misc/stm32f4xx_exti.h b/include/hw/misc/stm32f4xx_exti.h new file mode 100644 index 0000000000..707036a41b --- /dev/null +++ b/include/hw/misc/stm32f4xx_exti.h @@ -0,0 +1,60 @@ +/* + * STM32F4XX EXTI + * + * Copyright (c) 2014 Alistair Francis + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#ifndef HW_STM_EXTI_H +#define HW_STM_EXTI_H + +#include "hw/sysbus.h" +#include "hw/hw.h" + +#define EXTI_IMR 0x00 +#define EXTI_EMR 0x04 +#define EXTI_RTSR 0x08 +#define EXTI_FTSR 0x0C +#define EXTI_SWIER 0x10 +#define EXTI_PR 0x14 + +#define TYPE_STM32F4XX_EXTI "stm32f4xx-exti" +#define STM32F4XX_EXTI(obj) \ + OBJECT_CHECK(STM32F4xxExtiState, (obj), TYPE_STM32F4XX_EXTI) + +#define NUM_GPIO_EVENT_IN_LINES 16 +#define NUM_INTERRUPT_OUT_LINES 16 + +typedef struct { + SysBusDevice parent_obj; + + MemoryRegion mmio; + + uint32_t exti_imr; + uint32_t exti_emr; + uint32_t exti_rtsr; + uint32_t exti_ftsr; + uint32_t exti_swier; + uint32_t exti_pr; + + qemu_irq irq[NUM_INTERRUPT_OUT_LINES]; +} STM32F4xxExtiState; + +#endif -- 2.24.0 From MAILER-DAEMON Thu Dec 19 00:23:02 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1ihoH8-0004hN-Pg for mharc-qemu-arm@gnu.org; Thu, 19 Dec 2019 00:23:02 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:57172) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ihoH4-0004am-1i for qemu-arm@nongnu.org; Thu, 19 Dec 2019 00:23:00 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ihoH1-0002wd-Hf for qemu-arm@nongnu.org; Thu, 19 Dec 2019 00:22:57 -0500 Received: from wout4-smtp.messagingengine.com ([64.147.123.20]:52107) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1ihoH1-0002qf-6U; Thu, 19 Dec 2019 00:22:55 -0500 Received: from compute7.internal (compute7.nyi.internal [10.202.2.47]) by mailout.west.internal (Postfix) with ESMTP id 1001F567; Thu, 19 Dec 2019 00:22:54 -0500 (EST) Received: from mailfrontend1 ([10.202.2.162]) by compute7.internal (MEProxy); Thu, 19 Dec 2019 00:22:54 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=alistair23.me; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; s=fm2; bh=6RHuwo5pGYT2U K5SBHhz3Pj6gJwYbfnXjsnlsNgPp3w=; b=bozbNveiaB4F+BsnL22lt7G8qZHzw VrDpWtr3zpyZnufIZJFVEhM4RRmLzmz22ejVJUddfnWCKOCR41fZDJYJpIrvT2nK PRmOm3F2RdKV1xjsM3OOjhupLisz4xZ/04tnuZpeOUcLFOy8KfJrdsSGO5rzrkvA uq2E2v2jb90eFppUm+mxjhPd9evob+jCqonWYa2hItj5l4Dwhs+mqhPvzLg0ajhG r0J6vP3uXaxA9Q6l8XM46jIS86OTCcSgSs3kqViSGv5rdumbLwfRVBgpM25eS8cT RSnbrhNLv2bStarmChRj6UkVQctGtCuX59CTUWVS908CTNsHnFy7bdi5A== DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d= messagingengine.com; h=cc:content-transfer-encoding:date:from :in-reply-to:message-id:mime-version:references:subject:to :x-me-proxy:x-me-proxy:x-me-sender:x-me-sender:x-sasl-enc; s= fm1; bh=6RHuwo5pGYT2UK5SBHhz3Pj6gJwYbfnXjsnlsNgPp3w=; b=c87CV1gk UcGRak8BEVbjB+Lc6btfCcXbbmY5IOAgxKliwjmj18eeHW0Zeu7g7fGqkZRLHjc9 GsFW0qhQl/89ueHgpGCDE9ocZdAMqY+S/iqknADqF5TDJnqVHVIFbkR9yxkHAtim X3GHaFazwoLKAwzhgOcY48qSThUNEH9djxce3zeXkxgHtTSCB/JfqKjVFx9SwofO CwPFzGXjdN0ZxXIZBWI59eK2hQpGOOVpbZHBvhJPzQxoLtuX0nvjaEBQyKgV/Hbl xh8AWvSQYrW7WrGuvDgwx5WAweQsgMic4Xb0WtzbmMwF0NJT8GhK03pcci2pXWQ+ PEnFeg0jOrshIg== X-ME-Sender: X-ME-Proxy-Cause: gggruggvucftvghtrhhoucdtuddrgedufedrvddutddgkeduucetufdoteggodetrfdotf fvucfrrhhofhhilhgvmecuhfgrshhtofgrihhlpdfqfgfvpdfurfetoffkrfgpnffqhgen uceurghilhhouhhtmecufedttdenucenucfjughrpefhvffufffkofgjfhgggfestdekre dtredttdenucfhrhhomheptehlihhsthgrihhrucfhrhgrnhgtihhsuceorghlihhsthgr ihhrsegrlhhishhtrghirhdvfedrmhgvqeenucfkphepjeefrdelfedrkeegrddvtdekne curfgrrhgrmhepmhgrihhlfhhrohhmpegrlhhishhtrghirhesrghlihhsthgrihhrvdef rdhmvgenucevlhhushhtvghrufhiiigvpedv X-ME-Proxy: Received: from alistair-xps-14z.alistair23.me (c-73-93-84-208.hsd1.ca.comcast.net [73.93.84.208]) by mail.messagingengine.com (Postfix) with ESMTPA id C5F1980059; Thu, 19 Dec 2019 00:22:52 -0500 (EST) From: Alistair Francis To: qemu-devel@nongnu.org, peter.maydell@linaro.org, qemu-arm@nongnu.org, philmd@redhat.com Cc: alistair23@gmail.com Subject: [PATCH v7 3/4] hw/arm: Add the STM32F4xx SoC Date: Wed, 18 Dec 2019 21:22:52 -0800 Message-Id: <1d145c4c13e5fa140caf131232a6f524c88fcd72.1576658572.git.alistair@alistair23.me> X-Mailer: git-send-email 2.24.0 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 64.147.123.20 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 19 Dec 2019 05:23:01 -0000 Signed-off-by: Alistair Francis Reviewed-by: Peter Maydell --- MAINTAINERS | 8 + hw/arm/Makefile.objs | 1 + hw/arm/stm32f405_soc.c | 302 +++++++++++++++++++++++++++++++++ include/hw/arm/stm32f405_soc.h | 73 ++++++++ 4 files changed, 384 insertions(+) create mode 100644 hw/arm/stm32f405_soc.c create mode 100644 include/hw/arm/stm32f405_soc.h diff --git a/MAINTAINERS b/MAINTAINERS index 740401bcbb..bda53628a5 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -815,6 +815,14 @@ F: hw/adc/* F: hw/ssi/stm32f2xx_spi.c F: include/hw/*/stm32*.h +STM32F405 +M: Alistair Francis +M: Peter Maydell +S: Maintained +F: hw/arm/stm32f405_soc.c +F: hw/misc/stm32f4xx_syscfg.c +F: hw/misc/stm32f4xx_exti.c + Netduino 2 M: Alistair Francis M: Peter Maydell diff --git a/hw/arm/Makefile.objs b/hw/arm/Makefile.objs index fe749f65fd..d9d54da7cf 100644 --- a/hw/arm/Makefile.objs +++ b/hw/arm/Makefile.objs @@ -36,6 +36,7 @@ obj-$(CONFIG_STRONGARM) += strongarm.o obj-$(CONFIG_ALLWINNER_A10) += allwinner-a10.o cubieboard.o obj-$(CONFIG_RASPI) += bcm2835_peripherals.o bcm2836.o raspi.o obj-$(CONFIG_STM32F205_SOC) += stm32f205_soc.o +obj-$(CONFIG_STM32F405_SOC) += stm32f405_soc.o obj-$(CONFIG_XLNX_ZYNQMP_ARM) += xlnx-zynqmp.o xlnx-zcu102.o obj-$(CONFIG_XLNX_VERSAL) += xlnx-versal.o xlnx-versal-virt.o obj-$(CONFIG_FSL_IMX25) += fsl-imx25.o imx25_pdk.o diff --git a/hw/arm/stm32f405_soc.c b/hw/arm/stm32f405_soc.c new file mode 100644 index 0000000000..f22516fdf7 --- /dev/null +++ b/hw/arm/stm32f405_soc.c @@ -0,0 +1,302 @@ +/* + * STM32F405 SoC + * + * Copyright (c) 2014 Alistair Francis + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#include "qemu/osdep.h" +#include "qapi/error.h" +#include "qemu-common.h" +#include "exec/address-spaces.h" +#include "sysemu/sysemu.h" +#include "hw/arm/stm32f405_soc.h" +#include "hw/misc/unimp.h" + +#define SYSCFG_ADD 0x40013800 +static const uint32_t usart_addr[] = { 0x40011000, 0x40004400, 0x40004800, + 0x40004C00, 0x40005000, 0x40011400, + 0x40007800, 0x40007C00 }; +/* At the moment only Timer 2 to 5 are modelled */ +static const uint32_t timer_addr[] = { 0x40000000, 0x40000400, + 0x40000800, 0x40000C00 }; +#define ADC_ADDR 0x40012000 +static const uint32_t spi_addr[] = { 0x40013000, 0x40003800, 0x40003C00, + 0x40013400, 0x40015000, 0x40015400 }; +#define EXTI_ADDR 0x40013C00 + +#define SYSCFG_IRQ 71 +static const int usart_irq[] = { 37, 38, 39, 52, 53, 71, 82, 83 }; +static const int timer_irq[] = { 28, 29, 30, 50 }; +#define ADC_IRQ 18 +static const int spi_irq[] = { 35, 36, 51, 0, 0, 0 }; +static const int exti_irq[] = { 6, 7, 8, 9, 10, 23, 23, 23, 23, 23, 40, + 40, 40, 40, 40, 40} ; + + +static void stm32f405_soc_initfn(Object *obj) +{ + STM32F405State *s = STM32F405_SOC(obj); + int i; + + sysbus_init_child_obj(obj, "armv7m", &s->armv7m, sizeof(s->armv7m), + TYPE_ARMV7M); + + sysbus_init_child_obj(obj, "syscfg", &s->syscfg, sizeof(s->syscfg), + TYPE_STM32F4XX_SYSCFG); + + for (i = 0; i < STM_NUM_USARTS; i++) { + sysbus_init_child_obj(obj, "usart[*]", &s->usart[i], + sizeof(s->usart[i]), TYPE_STM32F2XX_USART); + } + + for (i = 0; i < STM_NUM_TIMERS; i++) { + sysbus_init_child_obj(obj, "timer[*]", &s->timer[i], + sizeof(s->timer[i]), TYPE_STM32F2XX_TIMER); + } + + for (i = 0; i < STM_NUM_ADCS; i++) { + sysbus_init_child_obj(obj, "adc[*]", &s->adc[i], sizeof(s->adc[i]), + TYPE_STM32F2XX_ADC); + } + + for (i = 0; i < STM_NUM_SPIS; i++) { + sysbus_init_child_obj(obj, "spi[*]", &s->spi[i], sizeof(s->spi[i]), + TYPE_STM32F2XX_SPI); + } + + sysbus_init_child_obj(obj, "exti", &s->exti, sizeof(s->exti), + TYPE_STM32F4XX_EXTI); +} + +static void stm32f405_soc_realize(DeviceState *dev_soc, Error **errp) +{ + STM32F405State *s = STM32F405_SOC(dev_soc); + MemoryRegion *system_memory = get_system_memory(); + DeviceState *dev, *armv7m; + SysBusDevice *busdev; + Error *err = NULL; + int i; + + memory_region_init_ram(&s->flash, NULL, "STM32F405.flash", FLASH_SIZE, + &err); + if (err != NULL) { + error_propagate(errp, err); + return; + } + memory_region_init_alias(&s->flash_alias, NULL, "STM32F405.flash.alias", + &s->flash, 0, FLASH_SIZE); + + memory_region_set_readonly(&s->flash, true); + memory_region_set_readonly(&s->flash_alias, true); + + memory_region_add_subregion(system_memory, FLASH_BASE_ADDRESS, &s->flash); + memory_region_add_subregion(system_memory, 0, &s->flash_alias); + + memory_region_init_ram(&s->sram, NULL, "STM32F405.sram", SRAM_SIZE, + &err); + if (err != NULL) { + error_propagate(errp, err); + return; + } + memory_region_add_subregion(system_memory, SRAM_BASE_ADDRESS, &s->sram); + + armv7m = DEVICE(&s->armv7m); + qdev_prop_set_uint32(armv7m, "num-irq", 96); + qdev_prop_set_string(armv7m, "cpu-type", s->cpu_type); + qdev_prop_set_bit(armv7m, "enable-bitband", true); + object_property_set_link(OBJECT(&s->armv7m), OBJECT(system_memory), + "memory", &error_abort); + object_property_set_bool(OBJECT(&s->armv7m), true, "realized", &err); + if (err != NULL) { + error_propagate(errp, err); + return; + } + + /* System configuration controller */ + dev = DEVICE(&s->syscfg); + object_property_set_bool(OBJECT(&s->syscfg), true, "realized", &err); + if (err != NULL) { + error_propagate(errp, err); + return; + } + busdev = SYS_BUS_DEVICE(dev); + sysbus_mmio_map(busdev, 0, SYSCFG_ADD); + sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(armv7m, SYSCFG_IRQ)); + + /* Attach UART (uses USART registers) and USART controllers */ + for (i = 0; i < STM_NUM_USARTS; i++) { + dev = DEVICE(&(s->usart[i])); + qdev_prop_set_chr(dev, "chardev", serial_hd(i)); + object_property_set_bool(OBJECT(&s->usart[i]), true, "realized", &err); + if (err != NULL) { + error_propagate(errp, err); + return; + } + busdev = SYS_BUS_DEVICE(dev); + sysbus_mmio_map(busdev, 0, usart_addr[i]); + sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(armv7m, usart_irq[i])); + } + + /* Timer 2 to 5 */ + for (i = 0; i < STM_NUM_TIMERS; i++) { + dev = DEVICE(&(s->timer[i])); + qdev_prop_set_uint64(dev, "clock-frequency", 1000000000); + object_property_set_bool(OBJECT(&s->timer[i]), true, "realized", &err); + if (err != NULL) { + error_propagate(errp, err); + return; + } + busdev = SYS_BUS_DEVICE(dev); + sysbus_mmio_map(busdev, 0, timer_addr[i]); + sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(armv7m, timer_irq[i])); + } + + /* ADC device, the IRQs are ORed together */ + object_initialize_child(OBJECT(s), "adc-orirq", &s->adc_irqs, + sizeof(s->adc_irqs), TYPE_OR_IRQ, + &err, NULL); + if (err != NULL) { + error_propagate(errp, err); + return; + } + object_property_set_int(OBJECT(&s->adc_irqs), STM_NUM_ADCS, + "num-lines", &err); + object_property_set_bool(OBJECT(&s->adc_irqs), true, "realized", &err); + if (err != NULL) { + error_propagate(errp, err); + return; + } + qdev_connect_gpio_out(DEVICE(&s->adc_irqs), 0, + qdev_get_gpio_in(armv7m, ADC_IRQ)); + + dev = DEVICE(&(s->adc[i])); + object_property_set_bool(OBJECT(&s->adc[i]), true, "realized", &err); + if (err != NULL) { + error_propagate(errp, err); + return; + } + busdev = SYS_BUS_DEVICE(dev); + sysbus_mmio_map(busdev, 0, ADC_ADDR); + sysbus_connect_irq(busdev, 0, + qdev_get_gpio_in(DEVICE(&s->adc_irqs), i)); + + /* SPI devices */ + for (i = 0; i < STM_NUM_SPIS; i++) { + dev = DEVICE(&(s->spi[i])); + object_property_set_bool(OBJECT(&s->spi[i]), true, "realized", &err); + if (err != NULL) { + error_propagate(errp, err); + return; + } + busdev = SYS_BUS_DEVICE(dev); + sysbus_mmio_map(busdev, 0, spi_addr[i]); + sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(armv7m, spi_irq[i])); + } + + /* EXTI device */ + dev = DEVICE(&s->exti); + object_property_set_bool(OBJECT(&s->exti), true, "realized", &err); + if (err != NULL) { + error_propagate(errp, err); + return; + } + busdev = SYS_BUS_DEVICE(dev); + sysbus_mmio_map(busdev, 0, EXTI_ADDR); + for (i = 0; i < 16; i++) { + sysbus_connect_irq(busdev, i, qdev_get_gpio_in(armv7m, exti_irq[i])); + } + for (i = 0; i < 16; i++) { + qdev_connect_gpio_out(DEVICE(&s->syscfg), i, qdev_get_gpio_in(dev, i)); + } + + create_unimplemented_device("timer[7]", 0x40001400, 0x400); + create_unimplemented_device("timer[12]", 0x40001800, 0x400); + create_unimplemented_device("timer[6]", 0x40001000, 0x400); + create_unimplemented_device("timer[13]", 0x40001C00, 0x400); + create_unimplemented_device("timer[14]", 0x40002000, 0x400); + create_unimplemented_device("RTC and BKP", 0x40002800, 0x400); + create_unimplemented_device("WWDG", 0x40002C00, 0x400); + create_unimplemented_device("IWDG", 0x40003000, 0x400); + create_unimplemented_device("I2S2ext", 0x40003000, 0x400); + create_unimplemented_device("I2S3ext", 0x40004000, 0x400); + create_unimplemented_device("I2C1", 0x40005400, 0x400); + create_unimplemented_device("I2C2", 0x40005800, 0x400); + create_unimplemented_device("I2C3", 0x40005C00, 0x400); + create_unimplemented_device("CAN1", 0x40006400, 0x400); + create_unimplemented_device("CAN2", 0x40006800, 0x400); + create_unimplemented_device("PWR", 0x40007000, 0x400); + create_unimplemented_device("DAC", 0x40007400, 0x400); + create_unimplemented_device("timer[1]", 0x40010000, 0x400); + create_unimplemented_device("timer[8]", 0x40010400, 0x400); + create_unimplemented_device("SDIO", 0x40012C00, 0x400); + create_unimplemented_device("timer[9]", 0x40014000, 0x400); + create_unimplemented_device("timer[10]", 0x40014400, 0x400); + create_unimplemented_device("timer[11]", 0x40014800, 0x400); + create_unimplemented_device("GPIOA", 0x40020000, 0x400); + create_unimplemented_device("GPIOB", 0x40020400, 0x400); + create_unimplemented_device("GPIOC", 0x40020800, 0x400); + create_unimplemented_device("GPIOD", 0x40020C00, 0x400); + create_unimplemented_device("GPIOE", 0x40021000, 0x400); + create_unimplemented_device("GPIOF", 0x40021400, 0x400); + create_unimplemented_device("GPIOG", 0x40021800, 0x400); + create_unimplemented_device("GPIOH", 0x40021C00, 0x400); + create_unimplemented_device("GPIOI", 0x40022000, 0x400); + create_unimplemented_device("CRC", 0x40023000, 0x400); + create_unimplemented_device("RCC", 0x40023800, 0x400); + create_unimplemented_device("Flash Int", 0x40023C00, 0x400); + create_unimplemented_device("BKPSRAM", 0x40024000, 0x400); + create_unimplemented_device("DMA1", 0x40026000, 0x400); + create_unimplemented_device("DMA2", 0x40026400, 0x400); + create_unimplemented_device("Ethernet", 0x40028000, 0x1400); + create_unimplemented_device("USB OTG HS", 0x40040000, 0x30000); + create_unimplemented_device("USB OTG FS", 0x50000000, 0x31000); + create_unimplemented_device("DCMI", 0x50050000, 0x400); + create_unimplemented_device("RNG", 0x50060800, 0x400); +} + +static Property stm32f405_soc_properties[] = { + DEFINE_PROP_STRING("cpu-type", STM32F405State, cpu_type), + DEFINE_PROP_END_OF_LIST(), +}; + +static void stm32f405_soc_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + + dc->realize = stm32f405_soc_realize; + dc->props = stm32f405_soc_properties; + /* No vmstate or reset required: device has no internal state */ +} + +static const TypeInfo stm32f405_soc_info = { + .name = TYPE_STM32F405_SOC, + .parent = TYPE_SYS_BUS_DEVICE, + .instance_size = sizeof(STM32F405State), + .instance_init = stm32f405_soc_initfn, + .class_init = stm32f405_soc_class_init, +}; + +static void stm32f405_soc_types(void) +{ + type_register_static(&stm32f405_soc_info); +} + +type_init(stm32f405_soc_types) diff --git a/include/hw/arm/stm32f405_soc.h b/include/hw/arm/stm32f405_soc.h new file mode 100644 index 0000000000..1fe97f8c3a --- /dev/null +++ b/include/hw/arm/stm32f405_soc.h @@ -0,0 +1,73 @@ +/* + * STM32F405 SoC + * + * Copyright (c) 2014 Alistair Francis + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#ifndef HW_ARM_STM32F405_SOC_H +#define HW_ARM_STM32F405_SOC_H + +#include "hw/misc/stm32f4xx_syscfg.h" +#include "hw/timer/stm32f2xx_timer.h" +#include "hw/char/stm32f2xx_usart.h" +#include "hw/adc/stm32f2xx_adc.h" +#include "hw/misc/stm32f4xx_exti.h" +#include "hw/or-irq.h" +#include "hw/ssi/stm32f2xx_spi.h" +#include "hw/arm/armv7m.h" + +#define TYPE_STM32F405_SOC "stm32f405-soc" +#define STM32F405_SOC(obj) \ + OBJECT_CHECK(STM32F405State, (obj), TYPE_STM32F405_SOC) + +#define STM_NUM_USARTS 7 +#define STM_NUM_TIMERS 4 +#define STM_NUM_ADCS 6 +#define STM_NUM_SPIS 6 + +#define FLASH_BASE_ADDRESS 0x08000000 +#define FLASH_SIZE (1024 * 1024) +#define SRAM_BASE_ADDRESS 0x20000000 +#define SRAM_SIZE (192 * 1024) + +typedef struct STM32F405State { + /*< private >*/ + SysBusDevice parent_obj; + /*< public >*/ + + char *cpu_type; + + ARMv7MState armv7m; + + STM32F4xxSyscfgState syscfg; + STM32F4xxExtiState exti; + STM32F2XXUsartState usart[STM_NUM_USARTS]; + STM32F2XXTimerState timer[STM_NUM_TIMERS]; + qemu_or_irq adc_irqs; + STM32F2XXADCState adc[STM_NUM_ADCS]; + STM32F2XXSPIState spi[STM_NUM_SPIS]; + + MemoryRegion sram; + MemoryRegion flash; + MemoryRegion flash_alias; +} STM32F405State; + +#endif -- 2.24.0 From MAILER-DAEMON Thu Dec 19 00:23:05 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1ihoHB-0004kR-Kj for mharc-qemu-arm@gnu.org; Thu, 19 Dec 2019 00:23:05 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:57619) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ihoH6-0004fA-KB for qemu-arm@nongnu.org; Thu, 19 Dec 2019 00:23:01 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ihoH5-0003In-AJ for qemu-arm@nongnu.org; Thu, 19 Dec 2019 00:23:00 -0500 Received: from wout4-smtp.messagingengine.com ([64.147.123.20]:36931) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1ihoH5-0003CM-0z; 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Thu, 19 Dec 2019 00:22:56 -0500 (EST) From: Alistair Francis To: qemu-devel@nongnu.org, peter.maydell@linaro.org, qemu-arm@nongnu.org, philmd@redhat.com Cc: alistair23@gmail.com Subject: [PATCH v7 4/4] hw/arm: Add the Netduino Plus 2 Date: Wed, 18 Dec 2019 21:22:55 -0800 Message-Id: X-Mailer: git-send-email 2.24.0 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 64.147.123.20 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 19 Dec 2019 05:23:02 -0000 Signed-off-by: Alistair Francis Reviewed-by: Peter Maydell --- MAINTAINERS | 6 +++++ hw/arm/Makefile.objs | 1 + hw/arm/netduinoplus2.c | 52 ++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 59 insertions(+) create mode 100644 hw/arm/netduinoplus2.c diff --git a/MAINTAINERS b/MAINTAINERS index bda53628a5..203ced66e0 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -829,6 +829,12 @@ M: Peter Maydell S: Maintained F: hw/arm/netduino2.c +Netduino Plus 2 +M: Alistair Francis +M: Peter Maydell +S: Maintained +F: hw/arm/netduinoplus2.c + SmartFusion2 M: Subbaraya Sundeep M: Peter Maydell diff --git a/hw/arm/Makefile.objs b/hw/arm/Makefile.objs index d9d54da7cf..336f6dd374 100644 --- a/hw/arm/Makefile.objs +++ b/hw/arm/Makefile.objs @@ -11,6 +11,7 @@ obj-$(CONFIG_MAINSTONE) += mainstone.o obj-$(CONFIG_MICROBIT) += microbit.o obj-$(CONFIG_MUSICPAL) += musicpal.o obj-$(CONFIG_NETDUINO2) += netduino2.o +obj-$(CONFIG_NETDUINOPLUS2) += netduinoplus2.o obj-$(CONFIG_NSERIES) += nseries.o obj-$(CONFIG_SX1) += omap_sx1.o obj-$(CONFIG_CHEETAH) += palm.o diff --git a/hw/arm/netduinoplus2.c b/hw/arm/netduinoplus2.c new file mode 100644 index 0000000000..e5e247edbe --- /dev/null +++ b/hw/arm/netduinoplus2.c @@ -0,0 +1,52 @@ +/* + * Netduino Plus 2 Machine Model + * + * Copyright (c) 2014 Alistair Francis + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#include "qemu/osdep.h" +#include "qapi/error.h" +#include "hw/boards.h" +#include "hw/qdev-properties.h" +#include "qemu/error-report.h" +#include "hw/arm/stm32f405_soc.h" +#include "hw/arm/boot.h" + +static void netduinoplus2_init(MachineState *machine) +{ + DeviceState *dev; + + dev = qdev_create(NULL, TYPE_STM32F405_SOC); + qdev_prop_set_string(dev, "cpu-type", ARM_CPU_TYPE_NAME("cortex-m4")); + object_property_set_bool(OBJECT(dev), true, "realized", &error_fatal); + + armv7m_load_kernel(ARM_CPU(first_cpu), + machine->kernel_filename, + FLASH_SIZE); +} + +static void netduinoplus2_machine_init(MachineClass *mc) +{ + mc->desc = "Netduino Plus 2 Machine"; + mc->init = netduinoplus2_init; +} + +DEFINE_MACHINE("netduinoplus2", netduinoplus2_machine_init) -- 2.24.0 From MAILER-DAEMON Thu Dec 19 01:49:30 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1ihpco-0000eC-H9 for mharc-qemu-arm@gnu.org; Thu, 19 Dec 2019 01:49:30 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:39122) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ihpcm-0000dx-6m for qemu-arm@nongnu.org; Thu, 19 Dec 2019 01:49:29 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ihpcl-0006Ki-06 for qemu-arm@nongnu.org; Thu, 19 Dec 2019 01:49:28 -0500 Received: from szxga06-in.huawei.com ([45.249.212.32]:42606 helo=huawei.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1ihpck-0005iX-JF; Thu, 19 Dec 2019 01:49:26 -0500 Received: from DGGEMS410-HUB.china.huawei.com (unknown [172.30.72.60]) by Forcepoint Email with ESMTP id 64E7DF7544FEBC85BDD4; Thu, 19 Dec 2019 14:49:19 +0800 (CST) Received: from linux-CPUxgZ.huawei.com (10.175.104.212) by DGGEMS410-HUB.china.huawei.com (10.3.19.210) with Microsoft SMTP Server id 14.3.439.0; Thu, 19 Dec 2019 14:49:13 +0800 From: Heyi Guo To: , CC: , Heyi Guo , Peter Maydell , "Michael S. Tsirkin" , "Igor Mammedov" , Shannon Zhao Subject: [PATCH 1/2] arm/virt/acpi: remove meaningless sub device "PR0" from PCI0 Date: Thu, 19 Dec 2019 14:47:58 +0800 Message-ID: <20191219064759.35053-2-guoheyi@huawei.com> X-Mailer: git-send-email 2.19.1 In-Reply-To: <20191219064759.35053-1-guoheyi@huawei.com> References: <20191219064759.35053-1-guoheyi@huawei.com> MIME-Version: 1.0 Content-Type: text/plain X-Originating-IP: [10.175.104.212] X-CFilter-Loop: Reflected Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 45.249.212.32 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 19 Dec 2019 06:49:29 -0000 The sub device "PR0" under PCI0 in ACPI/DSDT does not make any sense, so simply remote it. Signed-off-by: Heyi Guo --- Cc: Peter Maydell Cc: "Michael S. Tsirkin" Cc: Igor Mammedov Cc: Shannon Zhao Cc: qemu-arm@nongnu.org Cc: qemu-devel@nongnu.org --- hw/arm/virt-acpi-build.c | 4 ---- tests/data/acpi/virt/DSDT | Bin 18462 -> 18449 bytes tests/data/acpi/virt/DSDT.memhp | Bin 19799 -> 19786 bytes tests/data/acpi/virt/DSDT.numamem | Bin 18462 -> 18449 bytes 4 files changed, 4 deletions(-) diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c index bd5f771e9b..9f4c7d1889 100644 --- a/hw/arm/virt-acpi-build.c +++ b/hw/arm/virt-acpi-build.c @@ -317,10 +317,6 @@ static void acpi_dsdt_add_pci(Aml *scope, const MemM= apEntry *memmap, aml_append(method, aml_return(buf)); aml_append(dev, method); =20 - Aml *dev_rp0 =3D aml_device("%s", "RP0"); - aml_append(dev_rp0, aml_name_decl("_ADR", aml_int(0))); - aml_append(dev, dev_rp0); - Aml *dev_res0 =3D aml_device("%s", "RES0"); aml_append(dev_res0, aml_name_decl("_HID", aml_string("PNP0C02"))); crs =3D aml_resource_template(); diff --git a/tests/data/acpi/virt/DSDT b/tests/data/acpi/virt/DSDT index d0f3afeb134fdf1c11f64cd06dbcdd30be603b80..b5895cb22446860a0b9be3d32= ec856feb388be4c 100644 GIT binary patch delta 39 vcmbO?fpOvlMlP3Nmk>b@1_q`B6S<_Bdg?Z+cXBfI+}XT|v(|R9jr$`2@RSW) delta 50 zcmbO@fpOjhMlP3Nmk>D*1_q{tiCof5o%I{lJ2{y;?{412S!>J19TZ>?&k^tF5;R%I G{V4!>hYx%J diff --git a/tests/data/acpi/virt/DSDT.memhp b/tests/data/acpi/virt/DSDT.= memhp index 41ccc6431b917252bcbaac86c33b340c796be5ce..69ad844f65d047973a3e55198= beecd45a35b8fce 100644 GIT binary patch delta 40 wcmcaUi}BPfMlP3Nmk=3D*s1_q}3iCof5t(P{ccXBfI+}XT|v(|RAjk`1(02g)*ivR!s delta 51 zcmX>#i}Cs_MlP3NmymE@1_mbiiCof5O_w*ScXBdy-rc;3v(}c2J1D>)o+IATC1|sb HyBr$;t7;Fc diff --git a/tests/data/acpi/virt/DSDT.numamem b/tests/data/acpi/virt/DSD= T.numamem index d0f3afeb134fdf1c11f64cd06dbcdd30be603b80..b5895cb22446860a0b9be3d32= ec856feb388be4c 100644 GIT binary patch delta 39 vcmbO?fpOvlMlP3Nmk>b@1_q`B6S<_Bdg?Z+cXBfI+}XT|v(|R9jr$`2@RSW) delta 50 zcmbO@fpOjhMlP3Nmk>D*1_q{tiCof5o%I{lJ2{y;?{412S!>J19TZ>?&k^tF5;R%I G{V4!>hYx%J --=20 2.19.1 From MAILER-DAEMON Thu Dec 19 01:49:31 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1ihpcp-0000fH-Bj for mharc-qemu-arm@gnu.org; Thu, 19 Dec 2019 01:49:31 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:39064) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ihpcm-0000dw-3Q for qemu-arm@nongnu.org; Thu, 19 Dec 2019 01:49:29 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ihpcl-0006Kg-0M for qemu-arm@nongnu.org; Thu, 19 Dec 2019 01:49:27 -0500 Received: from szxga07-in.huawei.com ([45.249.212.35]:42254 helo=huawei.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1ihpck-0005ic-IW; Thu, 19 Dec 2019 01:49:26 -0500 Received: from DGGEMS410-HUB.china.huawei.com (unknown [172.30.72.58]) by Forcepoint Email with ESMTP id 31D6DF709F93C050493A; Thu, 19 Dec 2019 14:49:19 +0800 (CST) Received: from linux-CPUxgZ.huawei.com (10.175.104.212) by DGGEMS410-HUB.china.huawei.com (10.3.19.210) with Microsoft SMTP Server id 14.3.439.0; Thu, 19 Dec 2019 14:49:12 +0800 From: Heyi Guo To: , CC: , Heyi Guo , Peter Maydell , "Michael S. Tsirkin" , "Igor Mammedov" , Shannon Zhao Subject: [PATCH 0/2] Some cleanup in arm/virt/acpi Date: Thu, 19 Dec 2019 14:47:57 +0800 Message-ID: <20191219064759.35053-1-guoheyi@huawei.com> X-Mailer: git-send-email 2.19.1 MIME-Version: 1.0 Content-Type: text/plain X-Originating-IP: [10.175.104.212] X-CFilter-Loop: Reflected Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 45.249.212.35 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 19 Dec 2019 06:49:29 -0000 Remove useless device node and conflict _ADR objects in ACPI/DSDT. Cc: Peter Maydell Cc: "Michael S. Tsirkin" Cc: Igor Mammedov Cc: Shannon Zhao Cc: qemu-arm@nongnu.org Cc: qemu-devel@nongnu.org Heyi Guo (2): arm/virt/acpi: remove meaningless sub device "PR0" from PCI0 arm/virt/acpi: remove _ADR from devices identified by _HID hw/arm/virt-acpi-build.c | 12 ------------ tests/data/acpi/virt/DSDT | Bin 18462 -> 18426 bytes tests/data/acpi/virt/DSDT.memhp | Bin 19799 -> 19763 bytes tests/data/acpi/virt/DSDT.numamem | Bin 18462 -> 18426 bytes 4 files changed, 12 deletions(-) --=20 2.19.1 From MAILER-DAEMON Thu Dec 19 01:49:33 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1ihpcr-0000jB-My for mharc-qemu-arm@gnu.org; Thu, 19 Dec 2019 01:49:33 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:39342) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ihpcn-0000e3-Cp for qemu-arm@nongnu.org; Thu, 19 Dec 2019 01:49:30 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ihpcm-0006Qx-4f for qemu-arm@nongnu.org; Thu, 19 Dec 2019 01:49:29 -0500 Received: from szxga06-in.huawei.com ([45.249.212.32]:42764 helo=huawei.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1ihpcl-00067O-Nb; Thu, 19 Dec 2019 01:49:28 -0500 Received: from DGGEMS410-HUB.china.huawei.com (unknown [172.30.72.59]) by Forcepoint Email with ESMTP id 474A6F41EA539C7D2369; Thu, 19 Dec 2019 14:49:24 +0800 (CST) Received: from linux-CPUxgZ.huawei.com (10.175.104.212) by DGGEMS410-HUB.china.huawei.com (10.3.19.210) with Microsoft SMTP Server id 14.3.439.0; Thu, 19 Dec 2019 14:49:14 +0800 From: Heyi Guo To: , CC: , Heyi Guo , Shannon Zhao , Peter Maydell , "Michael S. Tsirkin" , Igor Mammedov Subject: [PATCH 2/2] arm/virt/acpi: remove _ADR from devices identified by _HID Date: Thu, 19 Dec 2019 14:47:59 +0800 Message-ID: <20191219064759.35053-3-guoheyi@huawei.com> X-Mailer: git-send-email 2.19.1 In-Reply-To: <20191219064759.35053-1-guoheyi@huawei.com> References: <20191219064759.35053-1-guoheyi@huawei.com> MIME-Version: 1.0 Content-Type: text/plain X-Originating-IP: [10.175.104.212] X-CFilter-Loop: Reflected Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 45.249.212.32 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 19 Dec 2019 06:49:30 -0000 According to ACPI spec, _ADR should be used for device which is on a bus that has a standard enumeration algorithm. It does not make sense to have a _ADR object for devices which already have _HID and will be enumerated by OSPM. Signed-off-by: Heyi Guo --- Cc: Shannon Zhao Cc: Peter Maydell Cc: "Michael S. Tsirkin" Cc: Igor Mammedov Cc: qemu-arm@nongnu.org Cc: qemu-devel@nongnu.org --- hw/arm/virt-acpi-build.c | 8 -------- tests/data/acpi/virt/DSDT | Bin 18449 -> 18426 bytes tests/data/acpi/virt/DSDT.memhp | Bin 19786 -> 19763 bytes tests/data/acpi/virt/DSDT.numamem | Bin 18449 -> 18426 bytes 4 files changed, 8 deletions(-) diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c index 9f4c7d1889..be752c0ad8 100644 --- a/hw/arm/virt-acpi-build.c +++ b/hw/arm/virt-acpi-build.c @@ -78,11 +78,6 @@ static void acpi_dsdt_add_uart(Aml *scope, const MemMa= pEntry *uart_memmap, AML_EXCLUSIVE, &uart_irq, 1)); aml_append(dev, aml_name_decl("_CRS", crs)); =20 - /* The _ADR entry is used to link this device to the UART described - * in the SPCR table, i.e. SPCR.base_address.address =3D=3D _ADR. - */ - aml_append(dev, aml_name_decl("_ADR", aml_int(uart_memmap->base))); - aml_append(scope, dev); } =20 @@ -170,7 +165,6 @@ static void acpi_dsdt_add_pci(Aml *scope, const MemMa= pEntry *memmap, aml_append(dev, aml_name_decl("_CID", aml_string("PNP0A03"))); aml_append(dev, aml_name_decl("_SEG", aml_int(0))); aml_append(dev, aml_name_decl("_BBN", aml_int(0))); - aml_append(dev, aml_name_decl("_ADR", aml_int(0))); aml_append(dev, aml_name_decl("_UID", aml_string("PCI0"))); aml_append(dev, aml_name_decl("_STR", aml_unicode("PCIe 0 Device")))= ; aml_append(dev, aml_name_decl("_CCA", aml_int(1))); @@ -334,7 +328,6 @@ static void acpi_dsdt_add_gpio(Aml *scope, const MemM= apEntry *gpio_memmap, { Aml *dev =3D aml_device("GPO0"); aml_append(dev, aml_name_decl("_HID", aml_string("ARMH0061"))); - aml_append(dev, aml_name_decl("_ADR", aml_int(0))); aml_append(dev, aml_name_decl("_UID", aml_int(0))); =20 Aml *crs =3D aml_resource_template(); @@ -364,7 +357,6 @@ static void acpi_dsdt_add_power_button(Aml *scope) { Aml *dev =3D aml_device(ACPI_POWER_BUTTON_DEVICE); aml_append(dev, aml_name_decl("_HID", aml_string("PNP0C0C"))); - aml_append(dev, aml_name_decl("_ADR", aml_int(0))); aml_append(dev, aml_name_decl("_UID", aml_int(0))); aml_append(scope, dev); } diff --git a/tests/data/acpi/virt/DSDT b/tests/data/acpi/virt/DSDT index b5895cb22446860a0b9be3d32ec856feb388be4c..a759ff739a071d5fbf50519a6= aea296e5e0f1e0c 100644 GIT binary patch delta 72 zcmbO@f$>*ABbQ6COUN&G1_q{66S<_BT5Bh&t1wzk^tIeLL4lL8ZSqD=3DgU!!5x$Pt+ c1HyxxIO07#U3dfh0t}oDoEbRcLp@y>07w882mk;8 delta 94 zcmey>&p2@cBbQ6CONgKc0|V26iCof5J#`b+RhV2^Ci+-%al|{i1o1F1FmP^cRp4ao tnY@hCfEg&X`7$S;oxFTNc#soEyoaX?Z-8HbfwO@#16Tu)4E1zj005fm7mWY_ diff --git a/tests/data/acpi/virt/DSDT.memhp b/tests/data/acpi/virt/DSDT.= memhp index 69ad844f65d047973a3e55198beecd45a35b8fce..6e5cc61977e4cd24f765fec06= 93f75a528c144c1 100644 GIT binary patch delta 72 zcmX>#i*fTTMlP3Nmk?uL1_q|eiCof5eHSLGt1wzk^tIeLL4lL8ZSqD=3DgU!!5U7RH) c1HyxxIO07#U3dfh0t}oDoEbRcLp@y>03)CjmjD0& delta 94 zcmdlyi}BPfMlP3Nmk=3D*s1_q}3iCof5t(PXMt1!8;O!Tqj;)r*23F2X3VBp-?s=3D&$E tGkF=3DO0W(l&^JPwVXL*ABbQ6COUN&G1_q{66S<_BT5Bh&t1wzk^tIeLL4lL8ZSqD=3DgU!!5x$Pt+ c1HyxxIO07#U3dfh0t}oDoEbRcLp@y>07w882mk;8 delta 94 zcmey>&p2@cBbQ6CONgKc0|V26iCof5J#`b+RhV2^Ci+-%al|{i1o1F1FmP^cRp4ao tnY@hCfEg&X`7$S;oxFTNc#soEyoaX?Z-8HbfwO@#16Tu)4E1zj005fm7mWY_ --=20 2.19.1 From MAILER-DAEMON Thu Dec 19 01:53:16 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1ihpgS-0004Ao-Fy for mharc-qemu-arm@gnu.org; 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bh=qxzXx+71n4empVY6KRCherhudWNv9rkASvNeiT9MKds=; b=PEhenpcSKql1NJ+LJNevdY/njzw4ir/2ZN+UWeor2+Oh4htAVVJGLYtq4UgHMEs6nKtgnx eMRE15MRwUjRLrnWl5ec7ISd41hFEW12RnYqasd5FlVWkag0oaV/emUooy9ZGK59hGpCiR EdPxKkNkG3xEjBOHrvKHuRboFHCkkC8= Received: from mimecast-mx01.redhat.com (mimecast-mx01.redhat.com [209.132.183.4]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-46-M1OOxZS7ODWAYahXKaS8VA-1; Thu, 19 Dec 2019 01:53:04 -0500 Received: from smtp.corp.redhat.com (int-mx07.intmail.prod.int.phx2.redhat.com [10.5.11.22]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx01.redhat.com (Postfix) with ESMTPS id 6EFE7184BEC0; Thu, 19 Dec 2019 06:52:59 +0000 (UTC) Received: from blackfin.pond.sub.org (ovpn-116-42.ams2.redhat.com [10.36.116.42]) by smtp.corp.redhat.com (Postfix) with ESMTPS id 1788D10013A1; Thu, 19 Dec 2019 06:52:48 +0000 (UTC) Received: by blackfin.pond.sub.org (Postfix, from userid 1000) id 9EAB111386A7; Thu, 19 Dec 2019 07:52:46 +0100 (CET) From: Markus Armbruster To: Philippe =?utf-8?Q?Mathieu-Daud=C3=A9?= Cc: Paolo Bonzini , =?utf-8?Q?Marc-Andr=C3=A9?= Lureau , qemu-devel@nongnu.org, Peter Maydell , Li Zhijian , Paul Burton , Jason Wang , KONRAD Frederic , Gerd Hoffmann , "Edgar E. Iglesias" , Alberto Garcia , Sagar Karandikar , qemu-block@nongnu.org, "Michael S. Tsirkin" , Markus Armbruster , Halil Pasic , Christian Borntraeger , "Gonglei \(Arei\)" , Joel Stanley , Samuel Thibault , Aleksandar Rikalo , Antony Pavlov , Laurent Vivier , Corey Minyard , Amit Shah , Alistair Francis , "Dr. David Alan Gilbert" , Fabien Chouteau , qemu-s390x@nongnu.org, qemu-arm@nongnu.org, Peter Chubb , Alex =?utf-8?Q?Benn=C3=A9e?= , Kevin Wolf , qemu-riscv@nongnu.org, Igor Mitsyanko , Bastian Koppelmann , Cornelia Huck , Max Reitz , Zhang Chen , Michael Walle , Palmer Dabbelt , Thomas Huth , Aleksandar Markovic , Aurelien Jarno Subject: Re: [RFC PATCH 13/14] hw/char/terminal3270: Explicit ignored QEMUChrEvent in IOEventHandler References: <20191217163808.20068-1-philmd@redhat.com> <20191217163808.20068-14-philmd@redhat.com> Date: Thu, 19 Dec 2019 07:52:46 +0100 In-Reply-To: <20191217163808.20068-14-philmd@redhat.com> ("Philippe =?utf-8?Q?Mathieu-Daud=C3=A9=22's?= message of "Tue, 17 Dec 2019 17:38:07 +0100") Message-ID: <87sglgx0w1.fsf@dusky.pond.sub.org> User-Agent: Gnus/5.13 (Gnus v5.13) Emacs/26.2 (gnu/linux) MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.84 on 10.5.11.22 X-MC-Unique: M1OOxZS7ODWAYahXKaS8VA-1 X-Mimecast-Spam-Score: 0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 205.139.110.120 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 19 Dec 2019 06:53:14 -0000 Philippe Mathieu-Daud=C3=A9 writes: > The Chardev events are listed in the QEMUChrEvent enum. To be > able to use this enum in the IOEventHandler typedef, we need to > explicit when frontends ignore some events, to silent GCC the > following warnings: > > CC s390x-softmmu/hw/char/terminal3270.o > hw/char/terminal3270.c: In function =E2=80=98chr_event=E2=80=99: > hw/char/terminal3270.c:156:5: error: enumeration value =E2=80=98CHR_EVE= NT_BREAK=E2=80=99 not handled in switch [-Werror=3Dswitch] > 156 | switch (event) { > | ^~~~~~ > hw/char/terminal3270.c:156:5: error: enumeration value =E2=80=98CHR_EVE= NT_MUX_IN=E2=80=99 not handled in switch [-Werror=3Dswitch] > hw/char/terminal3270.c:156:5: error: enumeration value =E2=80=98CHR_EVE= NT_MUX_OUT=E2=80=99 not handled in switch [-Werror=3Dswitch] > cc1: all warnings being treated as errors > > Signed-off-by: Philippe Mathieu-Daud=C3=A9 > --- > Cc: Cornelia Huck > Cc: Halil Pasic > Cc: Christian Borntraeger > Cc: "Marc-Andr=C3=A9 Lureau" > Cc: Paolo Bonzini > Cc: qemu-s390x@nongnu.org > --- > hw/char/terminal3270.c | 3 +++ > 1 file changed, 3 insertions(+) > > diff --git a/hw/char/terminal3270.c b/hw/char/terminal3270.c > index 6859c1bcb2..9e59a2d92b 100644 > --- a/hw/char/terminal3270.c > +++ b/hw/char/terminal3270.c > @@ -166,6 +166,9 @@ static void chr_event(void *opaque, int event) > sch->curr_status.scsw.dstat =3D SCSW_DSTAT_DEVICE_END; > css_conditional_io_interrupt(sch); > break; > + default: > + /* Ignore */ > + break; > } > } I doubt the /* Ignore */ comment is worth its keep. Splitting PATCH 02-13 feels excessive to me. From MAILER-DAEMON Thu Dec 19 05:31:01 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1iht5B-0005hM-Ea for mharc-qemu-arm@gnu.org; Thu, 19 Dec 2019 05:31:01 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:41424) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iht57-0005gz-VR for qemu-arm@nongnu.org; Thu, 19 Dec 2019 05:30:59 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1iht55-0007uQ-6y for qemu-arm@nongnu.org; Thu, 19 Dec 2019 05:30:56 -0500 Received: from us-smtp-1.mimecast.com ([205.139.110.61]:58701 helo=us-smtp-delivery-1.mimecast.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1iht54-0007ni-Ls for qemu-arm@nongnu.org; Thu, 19 Dec 2019 05:30:55 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1576751453; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=tygimuW6/XhKjBMlfyKJvIAh68dK23wap9XfVLQOs0Q=; b=LuTBZJz+RX+p7Hl9KLQSpiM4dWl97Zqp8YqNBdjd72zxE88n4xK2UZxYZ9rdQWp7CBRYwH xSBuSt1dSy50npeXHP6t4/X362t1OrmHDiX8ezjIFkWDTFLJFyhJR3XwYTD7udA0QEP9d+ +kzo6CeC91+jbAPHYVhOFrZ9PRZORNA= Received: from mimecast-mx01.redhat.com (mimecast-mx01.redhat.com [209.132.183.4]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-84-FsVGmdpaPqKk1x9Eqj-ylw-1; Thu, 19 Dec 2019 05:30:52 -0500 Received: from smtp.corp.redhat.com (int-mx05.intmail.prod.int.phx2.redhat.com [10.5.11.15]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx01.redhat.com (Postfix) with ESMTPS id C5CCB800D5B; Thu, 19 Dec 2019 10:30:50 +0000 (UTC) Received: from [10.36.116.117] (ovpn-116-117.ams2.redhat.com [10.36.116.117]) by smtp.corp.redhat.com (Postfix) with ESMTPS id 890516888D; Thu, 19 Dec 2019 10:30:42 +0000 (UTC) Subject: Re: [PATCH for-5.0 v11 08/20] virtio-iommu: Implement translate To: Peter Xu Cc: eric.auger.pro@gmail.com, qemu-devel@nongnu.org, qemu-arm@nongnu.org, peter.maydell@linaro.org, mst@redhat.com, armbru@redhat.com, jean-philippe.brucker@arm.com, bharatb.linux@gmail.com, yang.zhong@intel.com, dgilbert@redhat.com, quintela@redhat.com, kevin.tian@intel.com, tnowicki@marvell.com References: <20191122182943.4656-1-eric.auger@redhat.com> <20191122182943.4656-9-eric.auger@redhat.com> <20191210193342.GJ3352@xz-x1> From: Auger Eric Message-ID: <44c0041d-68ad-796f-16cc-4bab7ba0f164@redhat.com> Date: Thu, 19 Dec 2019 11:30:40 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101 Thunderbird/60.4.0 MIME-Version: 1.0 In-Reply-To: <20191210193342.GJ3352@xz-x1> Content-Language: en-US X-Scanned-By: MIMEDefang 2.79 on 10.5.11.15 X-MC-Unique: FsVGmdpaPqKk1x9Eqj-ylw-1 X-Mimecast-Spam-Score: 0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: 7bit X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 205.139.110.61 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 19 Dec 2019 10:30:59 -0000 Hi Peter, On 12/10/19 8:33 PM, Peter Xu wrote: > On Fri, Nov 22, 2019 at 07:29:31PM +0100, Eric Auger wrote: >> This patch implements the translate callback >> >> Signed-off-by: Eric Auger >> >> --- >> >> v10 -> v11: >> - take into account the new value struct and use >> g_tree_lookup_extended >> - switched to error_report_once >> >> v6 -> v7: >> - implemented bypass-mode >> >> v5 -> v6: >> - replace error_report by qemu_log_mask >> >> v4 -> v5: >> - check the device domain is not NULL >> - s/printf/error_report >> - set flags to IOMMU_NONE in case of all translation faults >> --- >> hw/virtio/trace-events | 1 + >> hw/virtio/virtio-iommu.c | 63 +++++++++++++++++++++++++++++++++++++++- >> 2 files changed, 63 insertions(+), 1 deletion(-) >> >> diff --git a/hw/virtio/trace-events b/hw/virtio/trace-events >> index f25359cee2..de7cbb3c8f 100644 >> --- a/hw/virtio/trace-events >> +++ b/hw/virtio/trace-events >> @@ -72,3 +72,4 @@ virtio_iommu_get_endpoint(uint32_t ep_id) "Alloc endpoint=%d" >> virtio_iommu_put_endpoint(uint32_t ep_id) "Free endpoint=%d" >> virtio_iommu_get_domain(uint32_t domain_id) "Alloc domain=%d" >> virtio_iommu_put_domain(uint32_t domain_id) "Free domain=%d" >> +virtio_iommu_translate_out(uint64_t virt_addr, uint64_t phys_addr, uint32_t sid) "0x%"PRIx64" -> 0x%"PRIx64 " for sid=%d" >> diff --git a/hw/virtio/virtio-iommu.c b/hw/virtio/virtio-iommu.c >> index f0a56833a2..a83666557b 100644 >> --- a/hw/virtio/virtio-iommu.c >> +++ b/hw/virtio/virtio-iommu.c >> @@ -412,19 +412,80 @@ static IOMMUTLBEntry virtio_iommu_translate(IOMMUMemoryRegion *mr, hwaddr addr, >> int iommu_idx) >> { >> IOMMUDevice *sdev = container_of(mr, IOMMUDevice, iommu_mr); >> + viommu_interval interval, *mapping_key; >> + viommu_mapping *mapping_value; >> + VirtIOIOMMU *s = sdev->viommu; >> + viommu_endpoint *ep; >> + bool bypass_allowed; >> uint32_t sid; >> + bool found; >> + >> + interval.low = addr; >> + interval.high = addr + 1; >> >> IOMMUTLBEntry entry = { >> .target_as = &address_space_memory, >> .iova = addr, >> .translated_addr = addr, >> - .addr_mask = ~(hwaddr)0, >> + .addr_mask = (1 << ctz32(s->config.page_size_mask)) - 1, >> .perm = IOMMU_NONE, >> }; >> >> + bypass_allowed = virtio_has_feature(s->acked_features, >> + VIRTIO_IOMMU_F_BYPASS); >> + > > Would it be easier to check bypass_allowed here once and then drop the > latter [1] and [2] check? bypass_allowed does not mean you systematically bypass. You bypass if the SID is unknown or if the device is not attached to any domain. Otherwise you translate. But maybe I miss your point. > >> sid = virtio_iommu_get_sid(sdev); >> >> trace_virtio_iommu_translate(mr->parent_obj.name, sid, addr, flag); >> + qemu_mutex_lock(&s->mutex); >> + >> + ep = g_tree_lookup(s->endpoints, GUINT_TO_POINTER(sid)); >> + if (!ep) { >> + if (!bypass_allowed) { > > [1] > >> + error_report_once("%s sid=%d is not known!!", __func__, sid); >> + } else { >> + entry.perm = flag; >> + } >> + goto unlock; >> + } >> + >> + if (!ep->domain) { >> + if (!bypass_allowed) { > > [2] > >> + qemu_log_mask(LOG_GUEST_ERROR, >> + "%s %02x:%02x.%01x not attached to any domain\n", >> + __func__, PCI_BUS_NUM(sid), >> + PCI_SLOT(sid), PCI_FUNC(sid)); >> + } else { >> + entry.perm = flag; >> + } >> + goto unlock; >> + } >> + >> + found = g_tree_lookup_extended(ep->domain->mappings, (gpointer)(&interval), >> + (void **)&mapping_key, >> + (void **)&mapping_value); >> + if (!found) { >> + qemu_log_mask(LOG_GUEST_ERROR, >> + "%s no mapping for 0x%"PRIx64" for sid=%d\n", >> + __func__, addr, sid); > > I would still suggest that we use the same logging interface (either > error_report_once() or qemu_log_mask(), not use them randomly). OK I will switch to error_report_once() then > >> + goto unlock; >> + } >> + >> + if (((flag & IOMMU_RO) && >> + !(mapping_value->flags & VIRTIO_IOMMU_MAP_F_READ)) || >> + ((flag & IOMMU_WO) && >> + !(mapping_value->flags & VIRTIO_IOMMU_MAP_F_WRITE))) { >> + qemu_log_mask(LOG_GUEST_ERROR, >> + "Permission error on 0x%"PRIx64"(%d): allowed=%d\n", >> + addr, flag, mapping_value->flags); > > (Btw, IIUC this may not be a guest error. Say, what if the device is > simply broken?) > >> + goto unlock; >> + } >> + entry.translated_addr = addr - mapping_key->low + mapping_value->phys_addr; >> + entry.perm = flag; >> + trace_virtio_iommu_translate_out(addr, entry.translated_addr, sid); >> + >> +unlock: >> + qemu_mutex_unlock(&s->mutex); >> return entry; >> } >> >> -- >> 2.20.1 >> > Thanks Eric From MAILER-DAEMON Thu Dec 19 05:31:19 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1iht5S-0005vj-Sf for mharc-qemu-arm@gnu.org; Thu, 19 Dec 2019 05:31:18 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:42510) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iht5R-0005uI-Bl for qemu-arm@nongnu.org; Thu, 19 Dec 2019 05:31:18 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1iht5Q-000061-AA for qemu-arm@nongnu.org; Thu, 19 Dec 2019 05:31:17 -0500 Received: from us-smtp-1.mimecast.com ([205.139.110.61]:43889 helo=us-smtp-delivery-1.mimecast.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1iht5O-0008VJ-8e for qemu-arm@nongnu.org; Thu, 19 Dec 2019 05:31:14 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1576751473; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=gf2YGeZfVn/qtENW1rrykbXMg9iGRIwEYDRSt4RketE=; b=FhpBGbTHQ6IlFiL7j0RNekZbW/ZP7L6lTmJJfZ65g/2WlZvNZzG+vTCojjEpgTP4jmUlOr zUXPj/cpK1/+DbGCbH1nD0XxQjEu7PFg4nCva4XXakEHSdScZTzE+jpVQFKM12Y7uT+T/x UrILrauP5g2+VM/7kjVydcFKwMQefnM= Received: from mimecast-mx01.redhat.com (mimecast-mx01.redhat.com [209.132.183.4]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-388-KaY59EmoPbCKxOBAcFMz2w-1; Thu, 19 Dec 2019 05:31:10 -0500 Received: from smtp.corp.redhat.com (int-mx05.intmail.prod.int.phx2.redhat.com [10.5.11.15]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx01.redhat.com (Postfix) with ESMTPS id 68FBA18557C0; Thu, 19 Dec 2019 10:31:08 +0000 (UTC) Received: from [10.36.116.117] (ovpn-116-117.ams2.redhat.com [10.36.116.117]) by smtp.corp.redhat.com (Postfix) with ESMTPS id AFC4269AE2; Thu, 19 Dec 2019 10:31:02 +0000 (UTC) Subject: Re: [PATCH for-5.0 v11 02/20] virtio-iommu: Add skeleton To: Jean-Philippe Brucker Cc: eric.auger.pro@gmail.com, qemu-devel@nongnu.org, qemu-arm@nongnu.org, peter.maydell@linaro.org, mst@redhat.com, armbru@redhat.com, jean-philippe.brucker@arm.com, bharatb.linux@gmail.com, yang.zhong@intel.com, dgilbert@redhat.com, quintela@redhat.com, kevin.tian@intel.com, peterx@redhat.com, tnowicki@marvell.com References: <20191122182943.4656-1-eric.auger@redhat.com> <20191122182943.4656-3-eric.auger@redhat.com> <20191210163155.GA277340@myrica> From: Auger Eric Message-ID: Date: Thu, 19 Dec 2019 11:31:01 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101 Thunderbird/60.4.0 MIME-Version: 1.0 In-Reply-To: <20191210163155.GA277340@myrica> Content-Language: en-US X-Scanned-By: MIMEDefang 2.79 on 10.5.11.15 X-MC-Unique: KaY59EmoPbCKxOBAcFMz2w-1 X-Mimecast-Spam-Score: 0 Content-Type: text/plain; charset=windows-1252 Content-Transfer-Encoding: 7bit X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 205.139.110.61 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 19 Dec 2019 10:31:18 -0000 Hi Jean, On 12/10/19 5:31 PM, Jean-Philippe Brucker wrote: > Hi Eric, > > On Fri, Nov 22, 2019 at 07:29:25PM +0100, Eric Auger wrote: >> +typedef struct VirtIOIOMMU { >> + VirtIODevice parent_obj; >> + VirtQueue *req_vq; >> + VirtQueue *event_vq; >> + struct virtio_iommu_config config; >> + uint64_t features; >> + uint64_t acked_features; > > We already have guest_features in the parent object. That's correct. I also removed the set_features() specific implementation as I can rely on the default one. > >> + GHashTable *as_by_busptr; >> + IOMMUPciBus *as_by_bus_num[IOMMU_PCI_BUS_MAX]; > > Doesn't seem used anymore. removed > > Thanks, > Jean > >> + PCIBus *primary_bus; >> + GTree *domains; >> + QemuMutex mutex; >> + GTree *endpoints; >> +} VirtIOIOMMU; >> + >> +#endif >> -- >> 2.20.1 >> >> > Thanks Eric From MAILER-DAEMON Thu Dec 19 06:04:02 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1ihtb7-0001iO-V9 for mharc-qemu-arm@gnu.org; Thu, 19 Dec 2019 06:04:01 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:59676) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ihtb4-0001eV-Q9 for qemu-arm@nongnu.org; Thu, 19 Dec 2019 06:03:59 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ihtb3-0001fo-G8 for qemu-arm@nongnu.org; Thu, 19 Dec 2019 06:03:58 -0500 Received: from us-smtp-delivery-1.mimecast.com ([205.139.110.120]:45855 helo=us-smtp-1.mimecast.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1ihtb3-0001d0-9F for qemu-arm@nongnu.org; Thu, 19 Dec 2019 06:03:57 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1576753436; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=c/XZkYHGQZ+Qe6fjvAxBLlDlAWbyR1Du9b+N0e7LYn8=; b=PH49SUkWg4v3BmkHzTGlKbqi5azeAcvwBST8URaMxvgqtcycSQzEB5dll8o99mGe7jV7Ch rgQi4I81u8B4p5z21T7y862UejjbRVCTYhJGeCqMPVuwerLaC+qHErUJHgniNmkk2fHXK+ 8e0MmIFOYyjF8M4EgkM7kfQtAOMyqmA= Received: from mimecast-mx01.redhat.com (mimecast-mx01.redhat.com [209.132.183.4]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-420-3ze0b_d8Pu6b0pOpxszu2w-1; Thu, 19 Dec 2019 06:03:55 -0500 Received: from smtp.corp.redhat.com (int-mx05.intmail.prod.int.phx2.redhat.com [10.5.11.15]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx01.redhat.com (Postfix) with ESMTPS id 1D962477; Thu, 19 Dec 2019 11:03:53 +0000 (UTC) Received: from [10.36.116.117] (ovpn-116-117.ams2.redhat.com [10.36.116.117]) by smtp.corp.redhat.com (Postfix) with ESMTPS id DFA3A6889D; Thu, 19 Dec 2019 11:03:43 +0000 (UTC) Subject: Re: [PATCH for-5.0 v11 18/20] virtio-iommu: Support migration To: Jean-Philippe Brucker Cc: eric.auger.pro@gmail.com, qemu-devel@nongnu.org, qemu-arm@nongnu.org, peter.maydell@linaro.org, mst@redhat.com, armbru@redhat.com, jean-philippe.brucker@arm.com, bharatb.linux@gmail.com, yang.zhong@intel.com, dgilbert@redhat.com, quintela@redhat.com, kevin.tian@intel.com, peterx@redhat.com, tnowicki@marvell.com References: <20191122182943.4656-1-eric.auger@redhat.com> <20191122182943.4656-19-eric.auger@redhat.com> <20191210165006.GP277340@myrica> From: Auger Eric Message-ID: Date: Thu, 19 Dec 2019 12:03:41 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101 Thunderbird/60.4.0 MIME-Version: 1.0 In-Reply-To: <20191210165006.GP277340@myrica> Content-Language: en-US X-Scanned-By: MIMEDefang 2.79 on 10.5.11.15 X-MC-Unique: 3ze0b_d8Pu6b0pOpxszu2w-1 X-Mimecast-Spam-Score: 0 Content-Type: text/plain; charset=windows-1252 Content-Transfer-Encoding: 7bit X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 205.139.110.120 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 19 Dec 2019 11:04:00 -0000 Hi Jean, On 12/10/19 5:50 PM, Jean-Philippe Brucker wrote: > On Fri, Nov 22, 2019 at 07:29:41PM +0100, Eric Auger wrote: >> +static const VMStateDescription vmstate_virtio_iommu_device = { >> + .name = "virtio-iommu-device", >> + .minimum_version_id = 1, >> + .version_id = 1, >> + .post_load = iommu_post_load, >> + .fields = (VMStateField[]) { >> + VMSTATE_GTREE_DIRECT_KEY_V(domains, VirtIOIOMMU, 1, >> + &vmstate_domain, viommu_domain), >> + VMSTATE_GTREE_DIRECT_KEY_V(endpoints, VirtIOIOMMU, 1, >> + &vmstate_endpoint, viommu_endpoint), > > So if I understand correctly these fields are state that is modified by > the guest? We don't need to save/load fields that cannot be modified by > the guest, static information that is created from the QEMU command-line. Yes that's correct. > > I think the above covers everything we need to migrate in VirtIOIOMMU > then, except for acked_features, which (as I pointed out on another patch) > seems redundant anyway since there is vdev->guest_features. you're right, acked features were not properly migrated. > > Reviewed-by: Jean-Philippe Brucker Thanks! Eric > >> + VMSTATE_END_OF_LIST() >> + }, >> +}; >> + >> + >> static const VMStateDescription vmstate_virtio_iommu = { >> .name = "virtio-iommu", >> .minimum_version_id = 1, >> -- >> 2.20.1 >> >> > From MAILER-DAEMON Thu Dec 19 06:14:11 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1ihtkx-000741-6d for mharc-qemu-arm@gnu.org; Thu, 19 Dec 2019 06:14:11 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:54459) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ihtku-0006yb-42 for qemu-arm@nongnu.org; Thu, 19 Dec 2019 06:14:09 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ihtks-0001oM-F1 for qemu-arm@nongnu.org; Thu, 19 Dec 2019 06:14:07 -0500 Received: from mail-wr1-x443.google.com ([2a00:1450:4864:20::443]:34836) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ihtks-0001gy-2K for qemu-arm@nongnu.org; Thu, 19 Dec 2019 06:14:06 -0500 Received: by mail-wr1-x443.google.com with SMTP id g17so5571846wro.2 for ; Thu, 19 Dec 2019 03:14:05 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=references:user-agent:from:to:cc:subject:in-reply-to:date :message-id:mime-version:content-transfer-encoding; bh=VchYwTa2XZqXtmbNsj17z0nYkcR5SFWBD4w1ltQiuOs=; b=giXFkS34AnJyf72FIsuqEn1+uy5V3xNnK5y9ZDzXmwpM/iqIRnAE6WhQElQPQZ+EXk ZxhZFmS7k9gTPxQ3zp8VUIHtLO61MFxcvjTxgSAVj9VV+h9BvGl9/tcTgtKnwMUytxkH 9bAleAaGRNusAmRrRQcylQiEwYIlitMlmixUZOhUfiPDhKdJVlepbo8E6bAX58AkIAM9 Jkwdg1V/qCvhU9KEjmtDdlw6P78ajHDwb8n3sMBlxYr1sCL9erfqv0o66RPdeU5WSZ6y 3YpGgF6k49lBaUnNjE441ZUQJuUauiMJDNvahKOGcNAE5Z+IZfdQszJWwDStN0qoR0il pmdA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:references:user-agent:from:to:cc:subject :in-reply-to:date:message-id:mime-version:content-transfer-encoding; bh=VchYwTa2XZqXtmbNsj17z0nYkcR5SFWBD4w1ltQiuOs=; b=f4HZ23yBHdb2DvdfkYaO+MDOHoWKC2rHE4aYU6rsQR4OXU3YG6/uNM2CIoK4VwUZGj JuBqVgjl4T13F0PTBwpu3w8QEVRtUA9iGzwcBwOGYQ9Ukp7dmJHB5WGbkTLr8i4B/z5P uySzgbi0WuU27Pem7qB7b8VKn9eg44eYp5zfyAwbDnk8cUvlj4LuKdxs2IEcaDCzdZSe AE59pBacqrCl4n/wan79LWsn0/GredfcgU3NiuJmQ5N/Vzw1Ba8vXtbLxOCkKbKgLnzT nKaJK2jzREelgqivgue6f3+AftngTuFJ5b05M4T0j5BKirPPoFKtv7BYhe+Qsr+bkvxl JMvg== X-Gm-Message-State: APjAAAW02emM6kpnIYX/ypc0Msg4EimSlgzZUXFWYdVQXsQFjiAcNB8J RgidURiDdVEnT5pyeeA6xSBhwg== X-Google-Smtp-Source: APXvYqwpvNuavAY7KsgD9NvMVbGYQI7HztWiALQ3LAp5QxUVp8JeIiYqxIaFuMCcopa9zpZb1DxogA== X-Received: by 2002:adf:f6c1:: with SMTP id y1mr9417416wrp.17.1576754044251; Thu, 19 Dec 2019 03:14:04 -0800 (PST) Received: from zen.linaroharston ([51.148.130.216]) by smtp.gmail.com with ESMTPSA id c15sm6022465wrt.1.2019.12.19.03.14.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 19 Dec 2019 03:14:02 -0800 (PST) Received: from zen (localhost [127.0.0.1]) by zen.linaroharston (Postfix) with ESMTP id AA3A81FF87; Thu, 19 Dec 2019 11:14:01 +0000 (GMT) References: <20191218180029.6744-1-alex.bennee@linaro.org> <20191218180029.6744-4-alex.bennee@linaro.org> <5ca1462e-5129-2b32-f014-a732a26a0587@linaro.org> User-agent: mu4e 1.3.5; emacs 27.0.50 From: Alex =?utf-8?Q?Benn=C3=A9e?= To: Richard Henderson Cc: qemu-devel@nongnu.org, Peter Maydell , keithp@keithp.com, Riku Voipio , Laurent Vivier , "open list:ARM TCG CPUs" , pbonzini@redhat.com Subject: Re: [PATCH v1 3/4] semihosting: add qemu_semihosting_console_inc for SYS_READC In-reply-to: <5ca1462e-5129-2b32-f014-a732a26a0587@linaro.org> Date: Thu, 19 Dec 2019 11:14:01 +0000 Message-ID: <87v9qcefeu.fsf@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::443 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 19 Dec 2019 11:14:09 -0000 Richard Henderson writes: > On 12/18/19 8:00 AM, Alex Benn=C3=A9e wrote: >> From: Keith Packard >>=20 >> Provides a blocking call to read a character from the console using >> semihosting.chardev, if specified. This takes some careful command >> line options to use stdio successfully as the serial ports, monitor >> and semihost all want to use stdio. Here's a sample set of command >> line options which share stdio betwen semihost, monitor and serial > > between. > >> +/** >> + * qemu_semihosting_console_inc: >> + * @env: CPUArchState >> + * >> + * Receive single character from debug console. This may be the remote >> + * gdb session if a softmmu guest is currently being debugged. As this >> + * call may block if no data is available we suspend the CPU and will >> + * rexecute the instruction when data is there. Therefor two > > re-execute, Therefore > >> + * conditions must be met: >> + * - CPUState is syncronised before callinging this function > > synchronized, calling > >> + * - pc is only updated once the character is succesfully returned > > successfully. > > >> +static int console_can_read(void *opaque) >> +{ >> + SemihostingConsole *c =3D opaque; >> + int ret; >> + g_assert(qemu_mutex_iothread_locked()); >> + ret =3D (int) fifo8_num_free(&c->fifo); >> + return ret; >> +} > > Boolean result; better as > > return fifo8_num_free(&c->fifo) > 0 > > (We could usefully change IOCanReadHandler to return bool to emphasize > this.) It's documented as the amount you can read and other handlers return amounts as well. I'm not sure I want to go messing with the chardev code in this series (although I need to look at Phillipe's series). > >> +static void console_wake_up(gpointer data, gpointer user_data) >> +{ >> + CPUState *cs =3D (CPUState *) data; >> + /* cpu_handle_halt won't know we have work so just unbung here */ >> + cs->halted =3D 0; >> + qemu_cpu_kick(cs); >> +} >> + >> +static void console_read(void *opaque, const uint8_t *buf, int size) >> +{ >> + SemihostingConsole *c =3D opaque; >> + g_assert(qemu_mutex_iothread_locked()); >> + while (size-- && !fifo8_is_full(&c->fifo)) { >> + fifo8_push(&c->fifo, *buf++); >> + } >> + g_slist_foreach(c->sleeping_cpus, console_wake_up, NULL); >> +} > > I think you should be clearing sleeping_cpus here, after they've all been= kicked. > >> +target_ulong qemu_semihosting_console_inc(CPUArchState *env) >> +{ >> + uint8_t ch; >> + SemihostingConsole *c =3D &console; >> + g_assert(qemu_mutex_iothread_locked()); >> + g_assert(current_cpu); >> + if (fifo8_is_empty(&c->fifo)) { >> + c->sleeping_cpus =3D g_slist_prepend(c->sleeping_cpus, current_= cpu); >> + current_cpu->halted =3D 1; >> + current_cpu->exception_index =3D EXCP_HALTED; >> + cpu_loop_exit(current_cpu); >> + /* never returns */ >> + } >> + c->sleeping_cpus =3D g_slist_remove_all(c->sleeping_cpus, current_c= pu); > > Which would mean you would not have to do this, because current_cpu is on= ly on > the list when it is halted. > > I presume all semihosting holds the BQL before we reach here, and we are = not > racing on this datastructure? Yeah this is all under BQL - which I assert is the case. I'll add a comment to the structure. > >> +target_ulong qemu_semihosting_console_inc(CPUArchState *env) >> +{ >> + uint8_t c; >> + struct pollfd pollfd =3D { >> + .fd =3D STDIN_FILENO, >> + .events =3D POLLIN >> + }; >> + >> + if (poll(&pollfd, 1, -1) !=3D 1) { >> + qemu_log_mask(LOG_UNIMP, "%s: unexpected read from stdin failur= e", >> + __func__); >> + return (target_ulong) -1; >> + } > > Why are you polling stdin? linux-user isn't system mode, there isn't a > separate monitor thread to get blocked, and you aren't even blocking the = thread > to try again just returning -1 to the guest. Hmm not sure - I guess we should just bite the bullet and potentially block here. semihosting is linux-user is a bit of a weird use case because we are not providing "hardware" but it seems it is used by a bunch of testcases that want to test things like M-profile non-glibc binaries without the baggage of a full simulation. > > > r~ --=20 Alex Benn=C3=A9e From MAILER-DAEMON Thu Dec 19 07:16:14 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1ihuj0-0007ew-IF for mharc-qemu-arm@gnu.org; Thu, 19 Dec 2019 07:16:14 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:59148) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ihuix-0007da-Fj for qemu-arm@nongnu.org; Thu, 19 Dec 2019 07:16:12 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ihuiu-0002qe-TN for qemu-arm@nongnu.org; Thu, 19 Dec 2019 07:16:11 -0500 Received: from us-smtp-delivery-1.mimecast.com ([207.211.31.120]:27951 helo=us-smtp-1.mimecast.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1ihuiu-0002mG-MN for qemu-arm@nongnu.org; Thu, 19 Dec 2019 07:16:08 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1576757768; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=BG6PkLmSL2pjmhhB/FbOkgZYwFjUekTzuEU4/82gflc=; b=P1mmEqwQzIP8F0ZMMgVcccM5bJXW2PTvl7wNxtygQ3Eiw79KmIffT8PI19hPmsSGm20Wbx 61/eS5pfTdzYhZtccWL7OxCnid4q+iUCRpPdwqr7q7ObAgt2F8DtXCJELGzC70IpCpBqVi K4l8WdjOc8juB2plIPWoJxn8L4obFiI= Received: from mimecast-mx01.redhat.com (mimecast-mx01.redhat.com [209.132.183.4]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-183-tSMJREfxMfiGGg5W44LUMg-1; Thu, 19 Dec 2019 07:16:06 -0500 Received: from smtp.corp.redhat.com (int-mx06.intmail.prod.int.phx2.redhat.com [10.5.11.16]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx01.redhat.com (Postfix) with ESMTPS id 7DCF5107ACC5; Thu, 19 Dec 2019 12:16:01 +0000 (UTC) Received: from gondolin (ovpn-117-134.ams2.redhat.com [10.36.117.134]) by smtp.corp.redhat.com (Postfix) with ESMTP id 248825C54A; Thu, 19 Dec 2019 12:15:30 +0000 (UTC) Date: Thu, 19 Dec 2019 13:15:26 +0100 From: Cornelia Huck To: Philippe =?UTF-8?B?TWF0aGlldS1EYXVkw6k=?= Cc: qemu-devel@nongnu.org, "Gonglei (Arei)" , =?UTF-8?B?TWFyYy1BbmRyw6k=?= Lureau , Paolo Bonzini , Alex =?UTF-8?B?QmVubsOpZQ==?= , Andrzej Zaborowski , Peter Maydell , "Michael S. Tsirkin" , Kevin Wolf , Max Reitz , "Edgar E. Iglesias" , Alistair Francis , Antony Pavlov , Igor Mitsyanko , Fabien Chouteau , KONRAD Frederic , Peter Chubb , Alberto Garcia , Michael Walle , Thomas Huth , Joel Stanley , Halil Pasic , Christian Borntraeger , Laurent Vivier , Amit Shah , Corey Minyard , Paul Burton , Aleksandar Rikalo , Aurelien Jarno , Aleksandar Markovic , Palmer Dabbelt , Sagar Karandikar , Bastian Koppelmann , Gerd Hoffmann , Samuel Thibault , "Dr. David Alan Gilbert" , Markus Armbruster , Zhang Chen , Li Zhijian , Jason Wang , qemu-arm@nongnu.org, qemu-block@nongnu.org, qemu-s390x@nongnu.org, qemu-riscv@nongnu.org Subject: Re: [RFC PATCH v2 14/14] chardev: Use QEMUChrEvent enum in IOEventHandler typedef Message-ID: <20191219131526.776cdcb0.cohuck@redhat.com> In-Reply-To: <20191218172009.8868-15-philmd@redhat.com> References: <20191218172009.8868-1-philmd@redhat.com> <20191218172009.8868-15-philmd@redhat.com> Organization: Red Hat GmbH MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.79 on 10.5.11.16 X-MC-Unique: tSMJREfxMfiGGg5W44LUMg-1 X-Mimecast-Spam-Score: 0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 207.211.31.120 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 19 Dec 2019 12:16:12 -0000 On Wed, 18 Dec 2019 18:20:09 +0100 Philippe Mathieu-Daud=C3=A9 wrote: > The Chardev events are listed in the QEMUChrEvent enum. >=20 > By using the enum in the IOEventHandler typedef we: >=20 > - make the IOEventHandler type more explicit (this handler > process out-of-band information, while the IOReadHandler > is in-band), > - help static code analyzers. >=20 > This patch was produced with the following spatch script: >=20 > @match@ > expression backend, opaque, context, set_open; > identifier fd_can_read, fd_read, fd_event, be_change; > @@ > qemu_chr_fe_set_handlers(backend, fd_can_read, fd_read, fd_event, > be_change, opaque, context, set_open); >=20 > @depends on match@ > identifier opaque, event; > identifier match.fd_event; > @@ > static > -void fd_event(void *opaque, int event) > +void fd_event(void *opaque, QEMUChrEvent event) > { > ... > } >=20 > Then the following files were manually modified: >=20 > - include/chardev/char-fe.h > - include/chardev/char.h > - include/chardev/char-mux.h > - chardev/char.c > - chardev/char-mux.c >=20 > Signed-off-by: Philippe Mathieu-Daud=C3=A9 (...) > diff --git a/hw/char/terminal3270.c b/hw/char/terminal3270.c > index 2aab04fd4b..f7aba12565 100644 > --- a/hw/char/terminal3270.c > +++ b/hw/char/terminal3270.c > @@ -142,7 +142,7 @@ static void terminal_read(void *opaque, const uint8_t= *buf, int size) > } > } > =20 > -static void chr_event(void *opaque, int event) > +static void chr_event(void *opaque, QEMUChrEvent event) > { > Terminal3270 *t =3D opaque; > CcwDevice *ccw_dev =3D CCW_DEVICE(t); Acked-by: Cornelia Huck From MAILER-DAEMON Thu Dec 19 07:34:16 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1ihv0S-0003hQ-QK for mharc-qemu-arm@gnu.org; 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[79.181.48.215]) by smtp.gmail.com with ESMTPSA id t15sm1674215qkg.49.2019.12.19.04.34.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 19 Dec 2019 04:34:05 -0800 (PST) Date: Thu, 19 Dec 2019 07:34:00 -0500 From: "Michael S. Tsirkin" To: Heyi Guo Cc: qemu-devel@nongnu.org, qemu-arm@nongnu.org, wanghaibin.wang@huawei.com, Peter Maydell , Igor Mammedov , Shannon Zhao Subject: Re: [PATCH 0/2] Some cleanup in arm/virt/acpi Message-ID: <20191219073344-mutt-send-email-mst@kernel.org> References: <20191219064759.35053-1-guoheyi@huawei.com> MIME-Version: 1.0 In-Reply-To: <20191219064759.35053-1-guoheyi@huawei.com> X-MC-Unique: 8_XrQUXDOlq7v6zeNxpm6A-1 X-Mimecast-Spam-Score: 0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: quoted-printable Content-Disposition: inline X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 205.139.110.120 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 19 Dec 2019 12:34:16 -0000 On Thu, Dec 19, 2019 at 02:47:57PM +0800, Heyi Guo wrote: > Remove useless device node and conflict _ADR objects in ACPI/DSDT. >=20 > Cc: Peter Maydell > Cc: "Michael S. Tsirkin" > Cc: Igor Mammedov > Cc: Shannon Zhao > Cc: qemu-arm@nongnu.org > Cc: qemu-devel@nongnu.org Acked-by: Michael S. Tsirkin Pls feel free to merge through ARM tree. > Heyi Guo (2): > arm/virt/acpi: remove meaningless sub device "PR0" from PCI0 > arm/virt/acpi: remove _ADR from devices identified by _HID >=20 > hw/arm/virt-acpi-build.c | 12 ------------ > tests/data/acpi/virt/DSDT | Bin 18462 -> 18426 bytes > tests/data/acpi/virt/DSDT.memhp | Bin 19799 -> 19763 bytes > tests/data/acpi/virt/DSDT.numamem | Bin 18462 -> 18426 bytes > 4 files changed, 12 deletions(-) >=20 > --=20 > 2.19.1 From MAILER-DAEMON Thu Dec 19 07:44:06 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1ihv9y-0000eT-LY for mharc-qemu-arm@gnu.org; Thu, 19 Dec 2019 07:44:06 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:56257) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ihv9t-0000Xq-NO for qemu-arm@nongnu.org; Thu, 19 Dec 2019 07:44:02 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ihv9q-0001FO-48 for qemu-arm@nongnu.org; Thu, 19 Dec 2019 07:44:01 -0500 Received: from mail-ot1-x341.google.com ([2607:f8b0:4864:20::341]:46294) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ihv9p-000182-Q5 for qemu-arm@nongnu.org; Thu, 19 Dec 2019 07:43:57 -0500 Received: by mail-ot1-x341.google.com with SMTP id c22so7064580otj.13 for ; Thu, 19 Dec 2019 04:43:57 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=j03bvTj8hmciPAmrh7pM7iJu7uCWP2HD0yo3OK6rh70=; b=hqZnlI1WgGL0a2W2GYcjcJNnZG18GLBC5jaC7cOmKTLG0kOkC0ZzPwzoMVHTY5SH5g kDwJ5SgOhPMi0rpbmMXiF6X1h3lgPPhCXKjhIbd9i1Nf2pBaIv8nIOM+Zgakzm0CxSik 12i1X1wmdBzK8ejvKq7ylj4xb3yMzYy8hMOWKCv7GZKIl07+wcc+B87HgMKSfxd7hKqP a1G+qEINv8zhZQWDlA2bdaPVn63IEkMOsf4iK0osd25xtUoPllGh6Hx0r2OjkgAwtIDJ kHINPG5ucfA+7ySpCqoktCfKDJIzpJqYYI4pHhexWk5vxHmpwTr68iZqo3eqvJyI9KUJ AsHQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=j03bvTj8hmciPAmrh7pM7iJu7uCWP2HD0yo3OK6rh70=; b=q1PaMThuS2DIXTNc1MzzC3D31Dh51tU+z2+OWZ+oYExG0TPhqZZI8UERp+69rXGUXx q9sI2L9ZJiiUwqdV0us7L0xvwYjbpVeXjl5xqnDHeYIlaz0+lBbAL31YZO0a+N6VmI0k 9k2IHmGb4TiRF+/c6jswHI8Dzy+3jY+8TJ654vUpAdl5/mDnBUMij4s9HstcbuPVXCbe 2VX6NgnSXtjTzIyV3M7ViFIfgSk5FTe5+g8O425HTtCWK2qioom+yck+5zTLOztbwDZZ 0xUNyazPiHRMSqn3JQYjqg9g6R64siO69POE/pw9y+0Kfvqng/K22hx0dySAcbRH1ZiR C+sg== X-Gm-Message-State: APjAAAX1iYT93AVhGleBpBMZtLSvVL4AsFen1iXjfDYF2cnBoIEgTPxG xMzcYjxRtLSgqGjOrILtRBr7nrlhVG2vhGwYXH2T6w== X-Google-Smtp-Source: APXvYqylSpwFKqvccJOPnj7nz3IOGQ5pVGvShhbN+8qPpK51wbu6huekTEn3yaSUWGR+WCaSAstdO8PerowrjAD+r88= X-Received: by 2002:a05:6830:2001:: with SMTP id e1mr8197502otp.97.1576759436211; Thu, 19 Dec 2019 04:43:56 -0800 (PST) MIME-Version: 1.0 References: <20191217210230.99559-1-jeff.kubascik@dornerworks.com> <7a274247-e593-5828-73f8-2042971e8633@linaro.org> In-Reply-To: <7a274247-e593-5828-73f8-2042971e8633@linaro.org> From: Peter Maydell Date: Thu, 19 Dec 2019 12:43:45 +0000 Message-ID: Subject: Re: [PATCH] target/arm: fix IL bit for data abort exceptions To: Richard Henderson Cc: Jeff Kubascik , qemu-arm , QEMU Developers , Stewart Hildebrand , Jarvis Roach Content-Type: text/plain; charset="UTF-8" X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::341 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 19 Dec 2019 12:44:04 -0000 On Wed, 18 Dec 2019 at 01:03, Richard Henderson wrote: > > On 12/17/19 11:02 AM, Jeff Kubascik wrote: > > diff --git a/target/arm/tlb_helper.c b/target/arm/tlb_helper.c > > index 5feb312941..e63f8bda29 100644 > > --- a/target/arm/tlb_helper.c > > +++ b/target/arm/tlb_helper.c > > @@ -44,7 +44,7 @@ static inline uint32_t merge_syn_data_abort(uint32_t template_syn, > > syn = syn_data_abort_with_iss(same_el, > > 0, 0, 0, 0, 0, > > ea, 0, s1ptw, is_write, fsc, > > - false); > > + true); > > /* Merge the runtime syndrome with the template syndrome. */ > > syn |= template_syn; > > This doesn't look correct. Surely the IL bit should come from template_syn? Yes. In translate.c we put it into the syndrome information by passing true/false to syn_data_abort_with_iss() depending on whether the issinfo passed in to disas_set_da_iss() has the ISSIs16Bit flag set. I think this is a regression introduced in commit 46beb58efbb8a2a32 when we converted the Thumb decoder over to decodetree. Before that 16 bit Thumb insns were in a different place in the old decoder and the 16-bit Thumb path passed ISSIs16Bit in with its issflags. (We should cc: qemu-stable@nongnu.org on the fix for this.) > > diff --git a/target/arm/translate.c b/target/arm/translate.c > > index 2b6c1f91bf..300480f1b7 100644 > > --- a/target/arm/translate.c > > +++ b/target/arm/translate.c > > @@ -8555,7 +8555,7 @@ static ISSInfo make_issinfo(DisasContext *s, int rd, bool p, bool w) > > > > /* ISS not valid if writeback */ > > if (p && !w) { > > - ret = rd; > > + ret = rd | (s->is_16bit ? ISSIs16Bit : 0); > > } else { > > ret = ISSInvalid; > > } Rather than setting an is_16bit flag, we could just use "dc->base.pc_next - dc->pc_curr == 2", couldn't we? thanks -- PMM From MAILER-DAEMON Thu Dec 19 08:10:02 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1ihvZ3-0001oE-1S for mharc-qemu-arm@gnu.org; Thu, 19 Dec 2019 08:10:01 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:35447) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ihvYy-0001ka-So for qemu-arm@nongnu.org; Thu, 19 Dec 2019 08:09:59 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ihvYv-0006yB-Vf for qemu-arm@nongnu.org; Thu, 19 Dec 2019 08:09:56 -0500 Received: from us-smtp-delivery-1.mimecast.com ([205.139.110.120]:47029 helo=us-smtp-1.mimecast.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1ihvYu-0006oh-NZ for qemu-arm@nongnu.org; Thu, 19 Dec 2019 08:09:53 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1576760991; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=SuzS+0RI392neHe9EkEjexF+DgTfoqg6pQIc+0/RiGk=; b=BG5bgpOlcZCOc34IZa9IDTwbAF624+Ozykpd+fRWXYWpM0V6HwKcD1co3NQaalSqwpFGV1 eTwY0o0a53iQupFtoFzuNTBjMDhwQk3fsPlQa551f54S4kBXs6APpDs2i+cKbgJ6qAUgPX 9nhpqlcyHbWf7x0Dn22JrEQsAAuWCDQ= Received: from mail-ed1-f69.google.com (mail-ed1-f69.google.com [209.85.208.69]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-134-ef9rkdw_OjmryNHTdiQLDg-1; Thu, 19 Dec 2019 08:09:49 -0500 Received: by mail-ed1-f69.google.com with SMTP id a5so3453500edn.14 for ; Thu, 19 Dec 2019 05:09:49 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:subject:to:cc:references:from:message-id:date :user-agent:mime-version:in-reply-to:content-language :content-transfer-encoding; bh=Ni05vfEtEsgSJx+IszN8ATEGfrX2nnauYNLHkipway8=; b=gnvrSNSsJeHFBU4C3NY7+xQpJQ+UA2pdrp+T4K6H8ACCHr3DXADhGqjnDiYDGTfnAv HZaOlDJcqIV2PmmIGoFmOsI3vCSKafAINBBJmePIzN00V6KLanOt2EeLPkW8MrrOyGA/ s7QnDBVKeIQeVMxM6TOqU5SHenCbpDbe9IAd9j3ghxGDVPYKDKqlxub3MAgf3yeoUonH Jg/7qckcASkXx/bMbanrDik+0VIIZVecID80LBIetAAUz1IlhDF8Q8aTvXLuvNIueQxc cZfMQzbQ+S5a8BmxM8C/sW6B/qXZ7N4+jjLMgHbQyq+TyaIwUnu93BHL7fhNvzrZn26Z uMyw== X-Gm-Message-State: APjAAAU41LWEf32ZMNGZ870HdniN7c6cgRQgi6N0w+S+Ld+P1rqSMjpc E4XmYm7cjw4Wk+rMJAmFbYXQO3AMiUEJDo0x2NEmKh3AhALEF5fSo0xcTI/w5ZIX0EBNs/KXUEg Oj6AyXP3bete+ X-Received: by 2002:a50:8522:: with SMTP id 31mr9076195edr.237.1576760987690; Thu, 19 Dec 2019 05:09:47 -0800 (PST) X-Google-Smtp-Source: APXvYqz/adgrbgJoCgmy56SiGC2LIO/SZZdbSv5QlB93ULWzoIEaQX5tN2zW1BKIP1XXj+7bB7rUng== X-Received: by 2002:a50:8522:: with SMTP id 31mr9076104edr.237.1576760986995; Thu, 19 Dec 2019 05:09:46 -0800 (PST) Received: from [192.168.1.35] (34.red-83-42-66.dynamicip.rima-tde.net. [83.42.66.34]) by smtp.gmail.com with ESMTPSA id e2sm474808eja.37.2019.12.19.05.09.43 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 19 Dec 2019 05:09:46 -0800 (PST) Subject: Re: [RFC PATCH 13/14] hw/char/terminal3270: Explicit ignored QEMUChrEvent in IOEventHandler To: Markus Armbruster Cc: Paolo Bonzini , =?UTF-8?Q?Marc-Andr=c3=a9_Lureau?= , qemu-devel@nongnu.org, Peter Maydell , Li Zhijian , Paul Burton , Jason Wang , KONRAD Frederic , Gerd Hoffmann , "Edgar E. Iglesias" , Alberto Garcia , Sagar Karandikar , qemu-block@nongnu.org, "Michael S. Tsirkin" , Halil Pasic , Christian Borntraeger , "Gonglei (Arei)" , Joel Stanley , Samuel Thibault , Aleksandar Rikalo , Antony Pavlov , Laurent Vivier , Corey Minyard , Amit Shah , Alistair Francis , "Dr. David Alan Gilbert" , Fabien Chouteau , qemu-s390x@nongnu.org, qemu-arm@nongnu.org, Peter Chubb , =?UTF-8?Q?Alex_Benn=c3=a9e?= , Kevin Wolf , qemu-riscv@nongnu.org, Igor Mitsyanko , Bastian Koppelmann , Cornelia Huck , Max Reitz , Zhang Chen , Michael Walle , Palmer Dabbelt , Thomas Huth , Aleksandar Markovic , Aurelien Jarno References: <20191217163808.20068-1-philmd@redhat.com> <20191217163808.20068-14-philmd@redhat.com> <87sglgx0w1.fsf@dusky.pond.sub.org> From: =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= Message-ID: <214a1da6-d974-4f98-0113-ea0b1ea9f244@redhat.com> Date: Thu, 19 Dec 2019 14:09:42 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.2.2 MIME-Version: 1.0 In-Reply-To: <87sglgx0w1.fsf@dusky.pond.sub.org> Content-Language: en-US X-MC-Unique: ef9rkdw_OjmryNHTdiQLDg-1 X-Mimecast-Spam-Score: 0 Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 205.139.110.120 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 19 Dec 2019 13:09:59 -0000 Hi Markus, On 12/19/19 7:52 AM, Markus Armbruster wrote: > Philippe Mathieu-Daud=C3=A9 writes: >=20 >> The Chardev events are listed in the QEMUChrEvent enum. To be >> able to use this enum in the IOEventHandler typedef, we need to >> explicit when frontends ignore some events, to silent GCC the >> following warnings: >> >> CC s390x-softmmu/hw/char/terminal3270.o >> hw/char/terminal3270.c: In function =E2=80=98chr_event=E2=80=99: >> hw/char/terminal3270.c:156:5: error: enumeration value =E2=80=98CHR_E= VENT_BREAK=E2=80=99 not handled in switch [-Werror=3Dswitch] >> 156 | switch (event) { >> | ^~~~~~ >> hw/char/terminal3270.c:156:5: error: enumeration value =E2=80=98CHR_E= VENT_MUX_IN=E2=80=99 not handled in switch [-Werror=3Dswitch] >> hw/char/terminal3270.c:156:5: error: enumeration value =E2=80=98CHR_E= VENT_MUX_OUT=E2=80=99 not handled in switch [-Werror=3Dswitch] >> cc1: all warnings being treated as errors >> >> Signed-off-by: Philippe Mathieu-Daud=C3=A9 >> --- >> Cc: Cornelia Huck >> Cc: Halil Pasic >> Cc: Christian Borntraeger >> Cc: "Marc-Andr=C3=A9 Lureau" >> Cc: Paolo Bonzini >> Cc: qemu-s390x@nongnu.org >> --- >> hw/char/terminal3270.c | 3 +++ >> 1 file changed, 3 insertions(+) >> >> diff --git a/hw/char/terminal3270.c b/hw/char/terminal3270.c >> index 6859c1bcb2..9e59a2d92b 100644 >> --- a/hw/char/terminal3270.c >> +++ b/hw/char/terminal3270.c >> @@ -166,6 +166,9 @@ static void chr_event(void *opaque, int event) >> sch->curr_status.scsw.dstat =3D SCSW_DSTAT_DEVICE_END; >> css_conditional_io_interrupt(sch); >> break; >> + default: >> + /* Ignore */ >> + break; >> } >> } >=20 > I doubt the /* Ignore */ comment is worth its keep. OK I don't mind dropping it. > Splitting PATCH 02-13 feels excessive to me. I agree, but I have the feeling when a patch touch many subsystems, we=20 don't wait for all the maintainers to Ack it, we are fine with 2 or 3. In this case, maybe a subsystem neglected a QEMUChrEvent case, so I=20 prefer to have each of them to confirm we can ignore the missing cases. In v2 I don't replace by a 'default' entry, all the cases are explicit. Regards, Phil. From MAILER-DAEMON Thu Dec 19 08:33:23 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1ihvvf-0000Nm-HF for mharc-qemu-arm@gnu.org; Thu, 19 Dec 2019 08:33:23 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:53128) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ihvvZ-00008y-GI for qemu-arm@nongnu.org; Thu, 19 Dec 2019 08:33:19 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ihvvX-0001MH-5S for qemu-arm@nongnu.org; Thu, 19 Dec 2019 08:33:16 -0500 Received: from us-smtp-1.mimecast.com ([205.139.110.61]:40033 helo=us-smtp-delivery-1.mimecast.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1ihvvW-0001Gm-Ug for qemu-arm@nongnu.org; Thu, 19 Dec 2019 08:33:15 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1576762393; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; 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Thu, 19 Dec 2019 05:33:10 -0800 (PST) X-Google-Smtp-Source: APXvYqy+Y10/rRZvyBzfotd49vjBuDPt/SmkpwCsOiXKB3hnaDeEBf6axwtUUnl1kQv4fFZv7T7trQ== X-Received: by 2002:ac8:461a:: with SMTP id p26mr6702178qtn.317.1576762390528; Thu, 19 Dec 2019 05:33:10 -0800 (PST) Received: from xz-x1 ([2607:9880:19c0:3f::2]) by smtp.gmail.com with ESMTPSA id j7sm1735320qkd.46.2019.12.19.05.33.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 19 Dec 2019 05:33:09 -0800 (PST) Date: Thu, 19 Dec 2019 08:33:08 -0500 From: Peter Xu To: Auger Eric Cc: eric.auger.pro@gmail.com, qemu-devel@nongnu.org, qemu-arm@nongnu.org, peter.maydell@linaro.org, mst@redhat.com, armbru@redhat.com, jean-philippe.brucker@arm.com, bharatb.linux@gmail.com, yang.zhong@intel.com, dgilbert@redhat.com, quintela@redhat.com, kevin.tian@intel.com, tnowicki@marvell.com Subject: Re: [PATCH for-5.0 v11 08/20] virtio-iommu: Implement translate Message-ID: <20191219133308.GA4246@xz-x1> References: <20191122182943.4656-1-eric.auger@redhat.com> <20191122182943.4656-9-eric.auger@redhat.com> <20191210193342.GJ3352@xz-x1> <44c0041d-68ad-796f-16cc-4bab7ba0f164@redhat.com> MIME-Version: 1.0 In-Reply-To: <44c0041d-68ad-796f-16cc-4bab7ba0f164@redhat.com> X-MC-Unique: g5K16dX1NZC7xP-1hulEMQ-1 X-Mimecast-Spam-Score: 0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable Content-Disposition: inline X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 205.139.110.61 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 19 Dec 2019 13:33:20 -0000 On Thu, Dec 19, 2019 at 11:30:40AM +0100, Auger Eric wrote: > Hi Peter, > On 12/10/19 8:33 PM, Peter Xu wrote: > > On Fri, Nov 22, 2019 at 07:29:31PM +0100, Eric Auger wrote: > >> This patch implements the translate callback > >> > >> Signed-off-by: Eric Auger > >> > >> --- > >> > >> v10 -> v11: > >> - take into account the new value struct and use > >> g_tree_lookup_extended > >> - switched to error_report_once > >> > >> v6 -> v7: > >> - implemented bypass-mode > >> > >> v5 -> v6: > >> - replace error_report by qemu_log_mask > >> > >> v4 -> v5: > >> - check the device domain is not NULL > >> - s/printf/error_report > >> - set flags to IOMMU_NONE in case of all translation faults > >> --- > >> hw/virtio/trace-events | 1 + > >> hw/virtio/virtio-iommu.c | 63 +++++++++++++++++++++++++++++++++++++++= - > >> 2 files changed, 63 insertions(+), 1 deletion(-) > >> > >> diff --git a/hw/virtio/trace-events b/hw/virtio/trace-events > >> index f25359cee2..de7cbb3c8f 100644 > >> --- a/hw/virtio/trace-events > >> +++ b/hw/virtio/trace-events > >> @@ -72,3 +72,4 @@ virtio_iommu_get_endpoint(uint32_t ep_id) "Alloc end= point=3D%d" > >> virtio_iommu_put_endpoint(uint32_t ep_id) "Free endpoint=3D%d" > >> virtio_iommu_get_domain(uint32_t domain_id) "Alloc domain=3D%d" > >> virtio_iommu_put_domain(uint32_t domain_id) "Free domain=3D%d" > >> +virtio_iommu_translate_out(uint64_t virt_addr, uint64_t phys_addr, ui= nt32_t sid) "0x%"PRIx64" -> 0x%"PRIx64 " for sid=3D%d" > >> diff --git a/hw/virtio/virtio-iommu.c b/hw/virtio/virtio-iommu.c > >> index f0a56833a2..a83666557b 100644 > >> --- a/hw/virtio/virtio-iommu.c > >> +++ b/hw/virtio/virtio-iommu.c > >> @@ -412,19 +412,80 @@ static IOMMUTLBEntry virtio_iommu_translate(IOMM= UMemoryRegion *mr, hwaddr addr, > >> int iommu_idx) > >> { > >> IOMMUDevice *sdev =3D container_of(mr, IOMMUDevice, iommu_mr); > >> + viommu_interval interval, *mapping_key; > >> + viommu_mapping *mapping_value; > >> + VirtIOIOMMU *s =3D sdev->viommu; > >> + viommu_endpoint *ep; > >> + bool bypass_allowed; > >> uint32_t sid; > >> + bool found; > >> + > >> + interval.low =3D addr; > >> + interval.high =3D addr + 1; > >> =20 > >> IOMMUTLBEntry entry =3D { > >> .target_as =3D &address_space_memory, > >> .iova =3D addr, > >> .translated_addr =3D addr, > >> - .addr_mask =3D ~(hwaddr)0, > >> + .addr_mask =3D (1 << ctz32(s->config.page_size_mask)) - 1, > >> .perm =3D IOMMU_NONE, > >> }; > >> =20 > >> + bypass_allowed =3D virtio_has_feature(s->acked_features, > >> + VIRTIO_IOMMU_F_BYPASS); > >> + > >=20 > > Would it be easier to check bypass_allowed here once and then drop the > > latter [1] and [2] check? > bypass_allowed does not mean you systematically bypass. You bypass if > the SID is unknown or if the device is not attached to any domain. > Otherwise you translate. But maybe I miss your point. Ah ok, then could I ask how will this VIRTIO_IOMMU_F_BYPASS be used? For example, I think VT-d defines passthrough in a totally different way in that the PT mark will be stored in the per-device context entries, then we can allow a specific device to be pass-through when doing DMA. That information is explicit (e.g., unknown SID will always fail the DMA), and per-device. Here do you mean that you just don't put a device into any domain to show it wants to use PT? Then I'm not sure how do you identify whether this is a legal PT or a malicious device (e.g., an unknown device that even does not have any driver bound to it, which will also satisfy "unknown SID" and "not attached to any domain", iiuc). Thanks, --=20 Peter Xu From MAILER-DAEMON Thu Dec 19 09:30:30 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1ihwow-0002tD-7B for mharc-qemu-arm@gnu.org; Thu, 19 Dec 2019 09:30:30 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:39807) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ihwoq-0002lu-Ji for qemu-arm@nongnu.org; Thu, 19 Dec 2019 09:30:26 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ihwok-0002PZ-II for qemu-arm@nongnu.org; Thu, 19 Dec 2019 09:30:24 -0500 Received: from us-smtp-2.mimecast.com ([207.211.31.81]:36962 helo=us-smtp-delivery-1.mimecast.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1ihwok-0002MO-AW for qemu-arm@nongnu.org; Thu, 19 Dec 2019 09:30:18 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1576765817; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=28rSLX4X8eSxZ8C3IwwotEZqVgOkmB31hF2ovohmpwg=; b=DFck97H6c2dZQ0jkNrDfAESajZuT6sjjZy/uUuTVh4TqD4YvOZ5/IxudMJmD3RniPes2nn f67YNoO/+Cry/LdrNn/bGQtRpf3XI63d9PBryCih0p6HahPSz7qv/EhnVbB6U+s/b7YS9b KKtuP+KI4dKsdSo0PwVLKcm8P6EG5WY= Received: from mimecast-mx01.redhat.com (mimecast-mx01.redhat.com [209.132.183.4]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-249-t6Nxs0jWMMOjzt_qKRNfUg-1; Thu, 19 Dec 2019 09:30:14 -0500 Received: from smtp.corp.redhat.com (int-mx05.intmail.prod.int.phx2.redhat.com [10.5.11.15]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx01.redhat.com (Postfix) with ESMTPS id A6EE81005502; Thu, 19 Dec 2019 14:30:12 +0000 (UTC) Received: from kamzik.brq.redhat.com (unknown [10.36.118.50]) by smtp.corp.redhat.com (Postfix) with ESMTPS id 41F816B566; Thu, 19 Dec 2019 14:30:08 +0000 (UTC) Date: Thu, 19 Dec 2019 15:30:05 +0100 From: Andrew Jones To: Peter Maydell Cc: bijan.mottahedeh@oracle.com, Marc Zyngier , Richard Henderson , QEMU Developers , qemu-arm , Heyi Guo , msys.mizuma@gmail.com Subject: Re: [RFC PATCH v2 3/5] target/arm/kvm: Implement virtual time adjustment Message-ID: <20191219143005.gw43k2hug2n5nvto@kamzik.brq.redhat.com> References: <20191212173320.11610-1-drjones@redhat.com> <20191212173320.11610-4-drjones@redhat.com> <20191216164355.i5rpfuqlfqv2z7m7@kamzik.brq.redhat.com> MIME-Version: 1.0 In-Reply-To: X-Scanned-By: MIMEDefang 2.79 on 10.5.11.15 X-MC-Unique: t6Nxs0jWMMOjzt_qKRNfUg-1 X-Mimecast-Spam-Score: 0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: quoted-printable Content-Disposition: inline X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 207.211.31.81 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 19 Dec 2019 14:30:27 -0000 On Mon, Dec 16, 2019 at 06:06:30PM +0000, Peter Maydell wrote: > On Mon, 16 Dec 2019 at 16:44, Andrew Jones wrote: > > > > On Mon, Dec 16, 2019 at 03:40:16PM +0000, Peter Maydell wrote: > > > On Mon, 16 Dec 2019 at 15:14, Peter Maydell wrote: > > > > How does this interact with the usual register sync to/from > > > > KVM (ie kvm_arch_get_registers(), which I think will do a > > > > GET_ONE_REG read of the TIMER_CNT register the way it does > > > > any other sysreg, inside write_kvmstate_to_list(), plus > > > > kvm_arch_set_registers() which does the write back to the > > > > kernel in write_list_to_kvmstate()) ? Presumably we want this > > > > version to take precedence by the set_virtual_time call > > > > happening after the kvm_arch_set_registers, but is this > > > > guaranteed ? > > > > > > ...you might also want to look at the effects of simply > > > removing the KVM_REG_ARM_TIMER_CNT entry from the > > > 'non_runtime_cpregs[]' array -- in commit 4b7a6bf402bd064 > > > we explicitly stopped reading/writing this register's value > > > to/from the kernel except for inbound migration, and it > > > feels like this patchset is now rolling back that approach, > > > so maybe we should also be (configurably) rolling back some > > > of its implementation rather than just leaving it in place. > > > > I feel like I already considered that, maybe even tried it, a few month= s > > ago when I first looked at this. I must have decided against it for som= e > > reason at the time, but I don't recall what. Now I can say the reason i= s > > because we only do this save/restore when we transition to/from paused > > state, though. >=20 > I found the thread which discussed the bug which originally > caused us to add commit 4b7a6bf402bd064: > https://lists.cs.columbia.edu/pipermail/kvmarm/2015-July/015665.html > -- there are some codepaths which cause us to do a sync from/to > KVM for one VCPU while others are still running. If we do a > read-CNT-and-write-back then we effectively cause time to jump > backwards for the other still-running CPUs. >=20 > So we do still want to have TIMER_CNT listed as being KVM_PUT_FULL_STATE > regardless, or we re-introduce that bug. Thanks for digging that up. I now recall also having read that history back when I first discovered KVM_REG_ARM_TIMER_CNT was special. >=20 > Your approach in this patchset reads and writes on vm-paused, > so it won't have the pre-2015 problems. >=20 > It still feels odd that we're storing this bit of guest state > in two places now though -- in kvm_vtime, and also in its usual > place in the cpreg_array data structures (we write back the > value from kvm_vtime when the VM starts running, and we write > back the value from the cpreg_array for a PUT_FULL_STATE, which > the comments claim is only on startup or when we just loaded > migration state (and also undocumentedly but reasonably on > cpu-hotplug, which arm doesn't have yet). >=20 > I've just spent a little while digging through code, and > haven't been able to satisfy myself on the ordering of which > writeback wins: for a loadvm I think we first do a > cpu_synchronize_all_post_init() (writing back the counter > value from the migration data) and then after than we will > unpause the VM -- why doesn't this overwrite the correct > value with the wrong value from kvm_vtime ? Hmm... I think I may have gotten lost when I went through this before. I just went through again, and still won't claim that I'm not a bit lost, but it does appear I got it backwards. When I get a chance I'll try to test this properly. We could use the same location as normal, in the cpreg_array. I'd just need to add a search of cpreg_indexes[] in order to get the index needed for cpreg_values[].=20 >=20 > I just noticed also that the logic used in this patch > doesn't match what other architectures do in their vm_state_change > function -- eg cpu_ppc_clock_vm_state_change() has an > "if (running) { load } else { save }", and kvmclock_vm_state_change() > for i386 also has "if (running) { ... } else { ... }", though > it has an extra wrinkle where it captures "are we PAUSED?" > to use in the pre_save function; the comment above > kvmclock_pre_save() suggests maybe that would be useful for other > than x86, too. kvm_s390_tod_vm_state_change() has > logic that's a slightly more complicated variation on just > testing the 'running' flag, but it doesn't look at the > specific new state. Yes, originally I had just if (running) {} else {}, but after looking at https://lists.gnu.org/archive/html/qemu-devel/2019-03/msg03695.html and seeing that the other architectures were careful to track the "are we paused" state, I got the feeling that we should be more specific and changed to if (running) {} else if (paused) {}. That's probably wrong, though, if we want to track all vm-stopped time. >=20 > > > I note also that the commit message there had a remark > > > about inconsistencies between VCPUs -- is the right thing > > > to handle this per-VM rather than per-VCPU somehow? > > > > per-VM would make sense, because the counters should be synchronized > > among the VCPUs. KVM does that for us, though, so whichever VCPU last > > restores its counter is the one that will determine the final value. > > > > Maybe we should have a VM ioctl instead, but ATM we only have VCPU ioct= ls. >=20 > I meant more "only do the save/load once per VM in QEMU but > do it by working with just one VCPU". But I guess since migration > works on all the VCPUs we're ok to do pause-resume the same way > (and I've now tracked down what the 'inconsistentencies between VCPUs' > were: they're when we were syncing the CNT value for one vCPU when > others were still running.) >=20 > thanks > -- PMM >=20 Thanks, drew From MAILER-DAEMON Thu Dec 19 09:39:02 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1ihwxA-0005Bh-Sn for mharc-qemu-arm@gnu.org; Thu, 19 Dec 2019 09:39:01 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:57898) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ihwx6-00053y-U7 for qemu-arm@nongnu.org; Thu, 19 Dec 2019 09:38:58 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ihwx5-000666-5L for qemu-arm@nongnu.org; Thu, 19 Dec 2019 09:38:56 -0500 Received: from us-smtp-delivery-1.mimecast.com ([207.211.31.120]:35575 helo=us-smtp-1.mimecast.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1ihwx4-00063I-TL for qemu-arm@nongnu.org; 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Thu, 19 Dec 2019 14:38:49 +0000 (UTC) Received: from [10.36.116.117] (ovpn-116-117.ams2.redhat.com [10.36.116.117]) by smtp.corp.redhat.com (Postfix) with ESMTPS id 16F685E243; Thu, 19 Dec 2019 14:38:36 +0000 (UTC) Subject: Re: [PATCH for-5.0 v11 08/20] virtio-iommu: Implement translate To: Peter Xu Cc: yang.zhong@intel.com, peter.maydell@linaro.org, kevin.tian@intel.com, tnowicki@marvell.com, mst@redhat.com, jean-philippe.brucker@arm.com, quintela@redhat.com, qemu-devel@nongnu.org, armbru@redhat.com, bharatb.linux@gmail.com, qemu-arm@nongnu.org, dgilbert@redhat.com, eric.auger.pro@gmail.com References: <20191122182943.4656-1-eric.auger@redhat.com> <20191122182943.4656-9-eric.auger@redhat.com> <20191210193342.GJ3352@xz-x1> <44c0041d-68ad-796f-16cc-4bab7ba0f164@redhat.com> <20191219133308.GA4246@xz-x1> From: Auger Eric Message-ID: <9d58b293-ada0-353e-bba2-ad1f538dfc62@redhat.com> Date: Thu, 19 Dec 2019 15:38:34 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101 Thunderbird/60.4.0 MIME-Version: 1.0 In-Reply-To: <20191219133308.GA4246@xz-x1> Content-Language: en-US X-Scanned-By: MIMEDefang 2.79 on 10.5.11.14 X-MC-Unique: tCVEtQx3MAuaBq0xoDMSjQ-1 X-Mimecast-Spam-Score: 0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: 7bit X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 207.211.31.120 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 19 Dec 2019 14:38:59 -0000 Hi Peter, On 12/19/19 2:33 PM, Peter Xu wrote: > On Thu, Dec 19, 2019 at 11:30:40AM +0100, Auger Eric wrote: >> Hi Peter, >> On 12/10/19 8:33 PM, Peter Xu wrote: >>> On Fri, Nov 22, 2019 at 07:29:31PM +0100, Eric Auger wrote: >>>> This patch implements the translate callback >>>> >>>> Signed-off-by: Eric Auger >>>> >>>> --- >>>> >>>> v10 -> v11: >>>> - take into account the new value struct and use >>>> g_tree_lookup_extended >>>> - switched to error_report_once >>>> >>>> v6 -> v7: >>>> - implemented bypass-mode >>>> >>>> v5 -> v6: >>>> - replace error_report by qemu_log_mask >>>> >>>> v4 -> v5: >>>> - check the device domain is not NULL >>>> - s/printf/error_report >>>> - set flags to IOMMU_NONE in case of all translation faults >>>> --- >>>> hw/virtio/trace-events | 1 + >>>> hw/virtio/virtio-iommu.c | 63 +++++++++++++++++++++++++++++++++++++++- >>>> 2 files changed, 63 insertions(+), 1 deletion(-) >>>> >>>> diff --git a/hw/virtio/trace-events b/hw/virtio/trace-events >>>> index f25359cee2..de7cbb3c8f 100644 >>>> --- a/hw/virtio/trace-events >>>> +++ b/hw/virtio/trace-events >>>> @@ -72,3 +72,4 @@ virtio_iommu_get_endpoint(uint32_t ep_id) "Alloc endpoint=%d" >>>> virtio_iommu_put_endpoint(uint32_t ep_id) "Free endpoint=%d" >>>> virtio_iommu_get_domain(uint32_t domain_id) "Alloc domain=%d" >>>> virtio_iommu_put_domain(uint32_t domain_id) "Free domain=%d" >>>> +virtio_iommu_translate_out(uint64_t virt_addr, uint64_t phys_addr, uint32_t sid) "0x%"PRIx64" -> 0x%"PRIx64 " for sid=%d" >>>> diff --git a/hw/virtio/virtio-iommu.c b/hw/virtio/virtio-iommu.c >>>> index f0a56833a2..a83666557b 100644 >>>> --- a/hw/virtio/virtio-iommu.c >>>> +++ b/hw/virtio/virtio-iommu.c >>>> @@ -412,19 +412,80 @@ static IOMMUTLBEntry virtio_iommu_translate(IOMMUMemoryRegion *mr, hwaddr addr, >>>> int iommu_idx) >>>> { >>>> IOMMUDevice *sdev = container_of(mr, IOMMUDevice, iommu_mr); >>>> + viommu_interval interval, *mapping_key; >>>> + viommu_mapping *mapping_value; >>>> + VirtIOIOMMU *s = sdev->viommu; >>>> + viommu_endpoint *ep; >>>> + bool bypass_allowed; >>>> uint32_t sid; >>>> + bool found; >>>> + >>>> + interval.low = addr; >>>> + interval.high = addr + 1; >>>> >>>> IOMMUTLBEntry entry = { >>>> .target_as = &address_space_memory, >>>> .iova = addr, >>>> .translated_addr = addr, >>>> - .addr_mask = ~(hwaddr)0, >>>> + .addr_mask = (1 << ctz32(s->config.page_size_mask)) - 1, >>>> .perm = IOMMU_NONE, >>>> }; >>>> >>>> + bypass_allowed = virtio_has_feature(s->acked_features, >>>> + VIRTIO_IOMMU_F_BYPASS); >>>> + >>> >>> Would it be easier to check bypass_allowed here once and then drop the >>> latter [1] and [2] check? >> bypass_allowed does not mean you systematically bypass. You bypass if >> the SID is unknown or if the device is not attached to any domain. >> Otherwise you translate. But maybe I miss your point. > > Ah ok, then could I ask how will this VIRTIO_IOMMU_F_BYPASS be used? > For example, I think VT-d defines passthrough in a totally different > way in that the PT mark will be stored in the per-device context > entries, then we can allow a specific device to be pass-through when > doing DMA. That information is explicit (e.g., unknown SID will > always fail the DMA), and per-device. > > Here do you mean that you just don't put a device into any domain to > show it wants to use PT? Then I'm not sure how do you identify > whether this is a legal PT or a malicious device (e.g., an unknown > device that even does not have any driver bound to it, which will also > satisfy "unknown SID" and "not attached to any domain", iiuc). The virtio-iommu spec currently says: "If the VIRTIO_IOMMU_F_BYPASS feature is negotiated, all accesses from unattached endpoints are allowed and translated by the IOMMU using the identity function. If the feature is not negotiated, any memory access from an unattached endpoint fails. Upon attaching an endpoint in bypass mode to a new domain, any memory access from the endpoint fails, since the domain does not contain any mapping. " I guess this can serve the purpose of devices doing early accesses, before the guest OS gets the hand and maps them? Thanks Eric > > Thanks, > From MAILER-DAEMON Thu Dec 19 09:49:49 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1ihx7d-00041i-LU for mharc-qemu-arm@gnu.org; Thu, 19 Dec 2019 09:49:49 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:59272) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ihx7Z-0003vU-6e for qemu-arm@nongnu.org; Thu, 19 Dec 2019 09:49:46 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ihx7X-0004XZ-MB for qemu-arm@nongnu.org; Thu, 19 Dec 2019 09:49:44 -0500 Received: from us-smtp-1.mimecast.com ([205.139.110.61]:41812 helo=us-smtp-delivery-1.mimecast.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1ihx7X-0004TA-HD for qemu-arm@nongnu.org; Thu, 19 Dec 2019 09:49:43 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1576766982; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; 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Thu, 19 Dec 2019 06:49:38 -0800 (PST) X-Google-Smtp-Source: APXvYqzDSmMC1/uJcrp/vMGki65iYTB2oZsfrn+xtKSFdAmqx+R5HSXTeKZNXOkI5VZxj1YfU58TRg== X-Received: by 2002:ac8:7b9b:: with SMTP id p27mr7455812qtu.2.1576766978297; Thu, 19 Dec 2019 06:49:38 -0800 (PST) Received: from xz-x1 ([104.156.64.74]) by smtp.gmail.com with ESMTPSA id f42sm1969151qta.0.2019.12.19.06.49.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 19 Dec 2019 06:49:37 -0800 (PST) Date: Thu, 19 Dec 2019 09:49:36 -0500 From: Peter Xu To: Auger Eric Cc: yang.zhong@intel.com, peter.maydell@linaro.org, kevin.tian@intel.com, tnowicki@marvell.com, mst@redhat.com, jean-philippe.brucker@arm.com, quintela@redhat.com, qemu-devel@nongnu.org, armbru@redhat.com, bharatb.linux@gmail.com, qemu-arm@nongnu.org, dgilbert@redhat.com, eric.auger.pro@gmail.com Subject: Re: [PATCH for-5.0 v11 08/20] virtio-iommu: Implement translate Message-ID: <20191219144936.GB50561@xz-x1> References: <20191122182943.4656-1-eric.auger@redhat.com> <20191122182943.4656-9-eric.auger@redhat.com> <20191210193342.GJ3352@xz-x1> <44c0041d-68ad-796f-16cc-4bab7ba0f164@redhat.com> <20191219133308.GA4246@xz-x1> <9d58b293-ada0-353e-bba2-ad1f538dfc62@redhat.com> MIME-Version: 1.0 In-Reply-To: <9d58b293-ada0-353e-bba2-ad1f538dfc62@redhat.com> X-MC-Unique: dLgWb-TqONeZYkkhvwuxaQ-1 X-Mimecast-Spam-Score: 0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable Content-Disposition: inline X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 205.139.110.61 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 19 Dec 2019 14:49:48 -0000 On Thu, Dec 19, 2019 at 03:38:34PM +0100, Auger Eric wrote: > Hi Peter, >=20 > On 12/19/19 2:33 PM, Peter Xu wrote: > > On Thu, Dec 19, 2019 at 11:30:40AM +0100, Auger Eric wrote: > >> Hi Peter, > >> On 12/10/19 8:33 PM, Peter Xu wrote: > >>> On Fri, Nov 22, 2019 at 07:29:31PM +0100, Eric Auger wrote: > >>>> This patch implements the translate callback > >>>> > >>>> Signed-off-by: Eric Auger > >>>> > >>>> --- > >>>> > >>>> v10 -> v11: > >>>> - take into account the new value struct and use > >>>> g_tree_lookup_extended > >>>> - switched to error_report_once > >>>> > >>>> v6 -> v7: > >>>> - implemented bypass-mode > >>>> > >>>> v5 -> v6: > >>>> - replace error_report by qemu_log_mask > >>>> > >>>> v4 -> v5: > >>>> - check the device domain is not NULL > >>>> - s/printf/error_report > >>>> - set flags to IOMMU_NONE in case of all translation faults > >>>> --- > >>>> hw/virtio/trace-events | 1 + > >>>> hw/virtio/virtio-iommu.c | 63 +++++++++++++++++++++++++++++++++++++= ++- > >>>> 2 files changed, 63 insertions(+), 1 deletion(-) > >>>> > >>>> diff --git a/hw/virtio/trace-events b/hw/virtio/trace-events > >>>> index f25359cee2..de7cbb3c8f 100644 > >>>> --- a/hw/virtio/trace-events > >>>> +++ b/hw/virtio/trace-events > >>>> @@ -72,3 +72,4 @@ virtio_iommu_get_endpoint(uint32_t ep_id) "Alloc e= ndpoint=3D%d" > >>>> virtio_iommu_put_endpoint(uint32_t ep_id) "Free endpoint=3D%d" > >>>> virtio_iommu_get_domain(uint32_t domain_id) "Alloc domain=3D%d" > >>>> virtio_iommu_put_domain(uint32_t domain_id) "Free domain=3D%d" > >>>> +virtio_iommu_translate_out(uint64_t virt_addr, uint64_t phys_addr, = uint32_t sid) "0x%"PRIx64" -> 0x%"PRIx64 " for sid=3D%d" > >>>> diff --git a/hw/virtio/virtio-iommu.c b/hw/virtio/virtio-iommu.c > >>>> index f0a56833a2..a83666557b 100644 > >>>> --- a/hw/virtio/virtio-iommu.c > >>>> +++ b/hw/virtio/virtio-iommu.c > >>>> @@ -412,19 +412,80 @@ static IOMMUTLBEntry virtio_iommu_translate(IO= MMUMemoryRegion *mr, hwaddr addr, > >>>> int iommu_idx) > >>>> { > >>>> IOMMUDevice *sdev =3D container_of(mr, IOMMUDevice, iommu_mr); > >>>> + viommu_interval interval, *mapping_key; > >>>> + viommu_mapping *mapping_value; > >>>> + VirtIOIOMMU *s =3D sdev->viommu; > >>>> + viommu_endpoint *ep; > >>>> + bool bypass_allowed; > >>>> uint32_t sid; > >>>> + bool found; > >>>> + > >>>> + interval.low =3D addr; > >>>> + interval.high =3D addr + 1; > >>>> =20 > >>>> IOMMUTLBEntry entry =3D { > >>>> .target_as =3D &address_space_memory, > >>>> .iova =3D addr, > >>>> .translated_addr =3D addr, > >>>> - .addr_mask =3D ~(hwaddr)0, > >>>> + .addr_mask =3D (1 << ctz32(s->config.page_size_mask)) - 1, > >>>> .perm =3D IOMMU_NONE, > >>>> }; > >>>> =20 > >>>> + bypass_allowed =3D virtio_has_feature(s->acked_features, > >>>> + VIRTIO_IOMMU_F_BYPASS); > >>>> + > >>> > >>> Would it be easier to check bypass_allowed here once and then drop th= e > >>> latter [1] and [2] check? > >> bypass_allowed does not mean you systematically bypass. You bypass if > >> the SID is unknown or if the device is not attached to any domain. > >> Otherwise you translate. But maybe I miss your point. > >=20 > > Ah ok, then could I ask how will this VIRTIO_IOMMU_F_BYPASS be used? > > For example, I think VT-d defines passthrough in a totally different > > way in that the PT mark will be stored in the per-device context > > entries, then we can allow a specific device to be pass-through when > > doing DMA. That information is explicit (e.g., unknown SID will > > always fail the DMA), and per-device. > >=20 > > Here do you mean that you just don't put a device into any domain to > > show it wants to use PT? Then I'm not sure how do you identify > > whether this is a legal PT or a malicious device (e.g., an unknown > > device that even does not have any driver bound to it, which will also > > satisfy "unknown SID" and "not attached to any domain", iiuc). >=20 > The virtio-iommu spec currently says: >=20 > "If the VIRTIO_IOMMU_F_BYPASS feature is negotiated, all accesses from > unattached endpoints are > allowed and translated by the IOMMU using the identity function. If the > feature is not negotiated, any > memory access from an unattached endpoint fails. Upon attaching an > endpoint in bypass mode to a new > domain, any memory access from the endpoint fails, since the domain does > not contain any mapping. > " >=20 > I guess this can serve the purpose of devices doing early accesses, > before the guest OS gets the hand and maps them? OK, so there's no global enablement knob for virtio-iommu? Hmm... Then: - This flag is a must for all virtio-iommu emulation, right? (otherwise I can't see how system bootstraps..) - Should this flag be gone right after OS starts (otherwise I think we still have the issue that any malicious device can be seen as in PT mode as default)? How is that done? Thanks, --=20 Peter Xu From MAILER-DAEMON Thu Dec 19 10:10:18 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1ihxRS-0002gE-4p for mharc-qemu-arm@gnu.org; Thu, 19 Dec 2019 10:10:18 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:35207) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ihxRP-0002aK-QW for qemu-arm@nongnu.org; Thu, 19 Dec 2019 10:10:17 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ihxRN-0002Wi-CL for qemu-arm@nongnu.org; Thu, 19 Dec 2019 10:10:14 -0500 Received: from us-smtp-2.mimecast.com ([205.139.110.61]:45729 helo=us-smtp-delivery-1.mimecast.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1ihxRM-0002Tr-96 for qemu-arm@nongnu.org; Thu, 19 Dec 2019 10:10:12 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1576768210; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=K0UTtIepKxxGnA5XLSDgUjbcapXtoa0Q6IZaZy2NQbM=; b=ISbEIS4SH9qQ0lX/hmRRObmE43xT5PZP+uau5nuo5y7eWQrRqAhKN0/1Ir0lARFv5S2DOP dsnW96m4qmqxoi+QR2YxT04YR1C8+BZqWkOgY9EuCOLkwXc8EtYYircMzAO9ANy7OfZ/30 oDb8KLwlgAhyubxXf5tlPgncWqExy4I= Received: from mimecast-mx01.redhat.com (mimecast-mx01.redhat.com [209.132.183.4]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-356-P934_7KrNnW88u4Xt8GOAQ-1; Thu, 19 Dec 2019 10:10:01 -0500 Received: from smtp.corp.redhat.com (int-mx03.intmail.prod.int.phx2.redhat.com [10.5.11.13]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx01.redhat.com (Postfix) with ESMTPS id 333D59B5A7; Thu, 19 Dec 2019 15:10:00 +0000 (UTC) Received: from [10.36.116.117] (ovpn-116-117.ams2.redhat.com [10.36.116.117]) by smtp.corp.redhat.com (Postfix) with ESMTPS id 44DF76E3F7; Thu, 19 Dec 2019 15:09:52 +0000 (UTC) Subject: Re: [PATCH for-5.0 v11 08/20] virtio-iommu: Implement translate To: Peter Xu Cc: yang.zhong@intel.com, peter.maydell@linaro.org, kevin.tian@intel.com, tnowicki@marvell.com, mst@redhat.com, jean-philippe.brucker@arm.com, quintela@redhat.com, qemu-devel@nongnu.org, armbru@redhat.com, bharatb.linux@gmail.com, qemu-arm@nongnu.org, dgilbert@redhat.com, eric.auger.pro@gmail.com References: <20191122182943.4656-1-eric.auger@redhat.com> <20191122182943.4656-9-eric.auger@redhat.com> <20191210193342.GJ3352@xz-x1> <44c0041d-68ad-796f-16cc-4bab7ba0f164@redhat.com> <20191219133308.GA4246@xz-x1> <9d58b293-ada0-353e-bba2-ad1f538dfc62@redhat.com> <20191219144936.GB50561@xz-x1> From: Auger Eric Message-ID: <9ec9d0d5-062b-f96b-c72c-4d15865ff9a1@redhat.com> Date: Thu, 19 Dec 2019 16:09:47 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101 Thunderbird/60.4.0 MIME-Version: 1.0 In-Reply-To: <20191219144936.GB50561@xz-x1> Content-Language: en-US X-Scanned-By: MIMEDefang 2.79 on 10.5.11.13 X-MC-Unique: P934_7KrNnW88u4Xt8GOAQ-1 X-Mimecast-Spam-Score: 0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: 7bit X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 205.139.110.61 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 19 Dec 2019 15:10:17 -0000 Hi Peter, jean, On 12/19/19 3:49 PM, Peter Xu wrote: > On Thu, Dec 19, 2019 at 03:38:34PM +0100, Auger Eric wrote: >> Hi Peter, >> >> On 12/19/19 2:33 PM, Peter Xu wrote: >>> On Thu, Dec 19, 2019 at 11:30:40AM +0100, Auger Eric wrote: >>>> Hi Peter, >>>> On 12/10/19 8:33 PM, Peter Xu wrote: >>>>> On Fri, Nov 22, 2019 at 07:29:31PM +0100, Eric Auger wrote: >>>>>> This patch implements the translate callback >>>>>> >>>>>> Signed-off-by: Eric Auger >>>>>> >>>>>> --- >>>>>> >>>>>> v10 -> v11: >>>>>> - take into account the new value struct and use >>>>>> g_tree_lookup_extended >>>>>> - switched to error_report_once >>>>>> >>>>>> v6 -> v7: >>>>>> - implemented bypass-mode >>>>>> >>>>>> v5 -> v6: >>>>>> - replace error_report by qemu_log_mask >>>>>> >>>>>> v4 -> v5: >>>>>> - check the device domain is not NULL >>>>>> - s/printf/error_report >>>>>> - set flags to IOMMU_NONE in case of all translation faults >>>>>> --- >>>>>> hw/virtio/trace-events | 1 + >>>>>> hw/virtio/virtio-iommu.c | 63 +++++++++++++++++++++++++++++++++++++++- >>>>>> 2 files changed, 63 insertions(+), 1 deletion(-) >>>>>> >>>>>> diff --git a/hw/virtio/trace-events b/hw/virtio/trace-events >>>>>> index f25359cee2..de7cbb3c8f 100644 >>>>>> --- a/hw/virtio/trace-events >>>>>> +++ b/hw/virtio/trace-events >>>>>> @@ -72,3 +72,4 @@ virtio_iommu_get_endpoint(uint32_t ep_id) "Alloc endpoint=%d" >>>>>> virtio_iommu_put_endpoint(uint32_t ep_id) "Free endpoint=%d" >>>>>> virtio_iommu_get_domain(uint32_t domain_id) "Alloc domain=%d" >>>>>> virtio_iommu_put_domain(uint32_t domain_id) "Free domain=%d" >>>>>> +virtio_iommu_translate_out(uint64_t virt_addr, uint64_t phys_addr, uint32_t sid) "0x%"PRIx64" -> 0x%"PRIx64 " for sid=%d" >>>>>> diff --git a/hw/virtio/virtio-iommu.c b/hw/virtio/virtio-iommu.c >>>>>> index f0a56833a2..a83666557b 100644 >>>>>> --- a/hw/virtio/virtio-iommu.c >>>>>> +++ b/hw/virtio/virtio-iommu.c >>>>>> @@ -412,19 +412,80 @@ static IOMMUTLBEntry virtio_iommu_translate(IOMMUMemoryRegion *mr, hwaddr addr, >>>>>> int iommu_idx) >>>>>> { >>>>>> IOMMUDevice *sdev = container_of(mr, IOMMUDevice, iommu_mr); >>>>>> + viommu_interval interval, *mapping_key; >>>>>> + viommu_mapping *mapping_value; >>>>>> + VirtIOIOMMU *s = sdev->viommu; >>>>>> + viommu_endpoint *ep; >>>>>> + bool bypass_allowed; >>>>>> uint32_t sid; >>>>>> + bool found; >>>>>> + >>>>>> + interval.low = addr; >>>>>> + interval.high = addr + 1; >>>>>> >>>>>> IOMMUTLBEntry entry = { >>>>>> .target_as = &address_space_memory, >>>>>> .iova = addr, >>>>>> .translated_addr = addr, >>>>>> - .addr_mask = ~(hwaddr)0, >>>>>> + .addr_mask = (1 << ctz32(s->config.page_size_mask)) - 1, >>>>>> .perm = IOMMU_NONE, >>>>>> }; >>>>>> >>>>>> + bypass_allowed = virtio_has_feature(s->acked_features, >>>>>> + VIRTIO_IOMMU_F_BYPASS); >>>>>> + >>>>> >>>>> Would it be easier to check bypass_allowed here once and then drop the >>>>> latter [1] and [2] check? >>>> bypass_allowed does not mean you systematically bypass. You bypass if >>>> the SID is unknown or if the device is not attached to any domain. >>>> Otherwise you translate. But maybe I miss your point. >>> >>> Ah ok, then could I ask how will this VIRTIO_IOMMU_F_BYPASS be used? >>> For example, I think VT-d defines passthrough in a totally different >>> way in that the PT mark will be stored in the per-device context >>> entries, then we can allow a specific device to be pass-through when >>> doing DMA. That information is explicit (e.g., unknown SID will >>> always fail the DMA), and per-device. >>> >>> Here do you mean that you just don't put a device into any domain to >>> show it wants to use PT? Then I'm not sure how do you identify >>> whether this is a legal PT or a malicious device (e.g., an unknown >>> device that even does not have any driver bound to it, which will also >>> satisfy "unknown SID" and "not attached to any domain", iiuc). >> >> The virtio-iommu spec currently says: >> >> "If the VIRTIO_IOMMU_F_BYPASS feature is negotiated, all accesses from >> unattached endpoints are >> allowed and translated by the IOMMU using the identity function. If the >> feature is not negotiated, any >> memory access from an unattached endpoint fails. Upon attaching an >> endpoint in bypass mode to a new >> domain, any memory access from the endpoint fails, since the domain does >> not contain any mapping. >> " >> >> I guess this can serve the purpose of devices doing early accesses, >> before the guest OS gets the hand and maps them? > > OK, so there's no global enablement knob for virtio-iommu? Hmm... Then: well this is a global knob. If this is bot negotiated any unmapped device can PT. My assumption above must be wrong as this is a negotiated feature so anyway the virtio-iommu driver should be involved. I don't really remember the rationale of the feature bit tbh. In "[virtio-dev] RE: [RFC] virtio-iommu version 0.4 " Jean discussed that with Kevein. Sorry I cannot find the link. " If the endpoint is not attached to any address space, then the device MAY abort the transaction." Kevin> From definition of BYPASS, it's orthogonal to whether there is an address space attached, then should we still allow "May abort" behavior? Jean> The behavior is left as an implementation choice, and I'm not sure it's worth enforcing in the architecture. If the endpoint isn't attached to any domain then (unless VIRTIO_IOMMU_F_BYPASS is negotiated), it isn't necessarily able to do DMA at all. The virtio-iommu device may setup DMA mastering lazily, in which case any DMA transaction would abort, or have setup DMA already, in which case the endpoint can access MEM_T_BYPASS regions. Hopefully Jean will remember and comment on this. Thanks Eric > > - This flag is a must for all virtio-iommu emulation, right? > (otherwise I can't see how system bootstraps..) > > - Should this flag be gone right after OS starts (otherwise I think > we still have the issue that any malicious device can be seen as > in PT mode as default)? How is that done? > > Thanks, > From MAILER-DAEMON Thu Dec 19 12:50:13 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1ihzwC-0002u6-Vp for mharc-qemu-arm@gnu.org; Thu, 19 Dec 2019 12:50:13 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:50298) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ihzw8-0002nH-Gw for qemu-arm@nongnu.org; Thu, 19 Dec 2019 12:50:10 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ihzw6-0001zY-JG for qemu-arm@nongnu.org; Thu, 19 Dec 2019 12:50:08 -0500 Received: from mail-wr1-x441.google.com ([2a00:1450:4864:20::441]:33508) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ihzw6-0001vn-6h for qemu-arm@nongnu.org; Thu, 19 Dec 2019 12:50:06 -0500 Received: by mail-wr1-x441.google.com with SMTP id b6so6922352wrq.0 for ; Thu, 19 Dec 2019 09:50:04 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=references:user-agent:from:to:cc:subject:in-reply-to:date :message-id:mime-version:content-transfer-encoding; bh=+7J6cwWsK5m8RqJIJw6UIA4O+t2/hnH9oWFBaj1UuGk=; b=aqmdw2Fxer+fvZqA0W7mDAfv3bUKgoVaVNuTu1BbpO4Sh7mH/QseDpDry+Y2fds+qu vEw48Q7sd5ZaGYJa9O5z/x/m/+IqONfjxP6BYR//UsU7nU7MHpM9MYVOio82jTd4ay5k /Dmhih6XpTVhDBtxQ0L0lBLhj8D+kRj/XbSltCWnVe0xZk/Yo7lcH9I3REA4xottjyC+ 1hNCbx6IbOhtfOjPnJjnqPGvEWNDePIwIcKrA17s+tcTo+ge34AZhy54rywi/25LqkC4 o275hzNubYxw0OJ4FApSuYhP0yvZX/2PfXlU+yIv1uz1nT8U34Lco+2zmQXseuvjAEAb R2KA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:references:user-agent:from:to:cc:subject :in-reply-to:date:message-id:mime-version:content-transfer-encoding; bh=+7J6cwWsK5m8RqJIJw6UIA4O+t2/hnH9oWFBaj1UuGk=; b=YmlfRHNqEf4uiU01rMNPbdfsP4vc1RCfb2S8y2IG51W4M9OkbagHISuoo+5/wiSWt/ 7ZZXRv6Jxgdtj2uXcjMFiPVzHhpbPDohUAuNASACMs9Gdd2sSVObYHGyRA6Uu0aW01Hh kn30bhytWHEigB/U9JneVUsfaIK42dQZbN16FfgYm7MQ7G7SmS61klG8yjH7P4EvJwWB 7n1MDJfbMeKfEdWsZYN80O2xijuUqWCacF4YJiDKBdhs4fqBCSbBFosDnG9iUvmkO8n7 u4PYTgW1V2B/PtO04HGaU5x1faLV0lYXHbh6ext1AC6rXaW/ZXHuRvML2CPRWwKPs/mg 4cmA== X-Gm-Message-State: APjAAAVgGhdUy4aF6NQpbYO4Os3+7Qou50DME62zFuoS4ls8BcG/SLO7 g6ch1gx1ZT0o88wLmxAnWPIqiA== X-Google-Smtp-Source: APXvYqz13j+q5pdEgvqzsgbPKB8JtdS/k6KeljD9N1df6AJ+pYoOVFElzTAtoGfaBs0k0l0e37/Krw== X-Received: by 2002:adf:fa12:: with SMTP id m18mr10353018wrr.309.1576777803448; Thu, 19 Dec 2019 09:50:03 -0800 (PST) Received: from zen.linaroharston ([51.148.130.216]) by smtp.gmail.com with ESMTPSA id x10sm6945535wrv.60.2019.12.19.09.50.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 19 Dec 2019 09:50:01 -0800 (PST) Received: from zen (localhost [127.0.0.1]) by zen.linaroharston (Postfix) with ESMTP id C55D51FF87; Thu, 19 Dec 2019 17:50:00 +0000 (GMT) References: <20191211170520.7747-1-alex.bennee@linaro.org> <20191211170520.7747-9-alex.bennee@linaro.org> User-agent: mu4e 1.3.5; emacs 27.0.50 From: Alex =?utf-8?Q?Benn=C3=A9e?= To: Damien Hedde Cc: qemu-devel@nongnu.org, richard.henderson@linaro.org, alan.hayward@arm.com, luis.machado@linaro.org, Philippe =?utf-8?Q?Mathieu?= =?utf-8?Q?-Daud=C3=A9?= , Eduardo Habkost , Marcel Apfelbaum , Richard Henderson , Peter Maydell , "Edgar E. Iglesias" , Paolo Bonzini , Michael Walle , Laurent Vivier , Aurelien Jarno , Aleksandar Markovic , Aleksandar Rikalo , Chris Wulff , Marek Vasut , Stafford Horne , David Gibson , Palmer Dabbelt , Alistair Francis , Sagar Karandikar , Bastian Koppelmann , David Hildenbrand , Cornelia Huck , Mark Cave-Ayland , Artyom Tarasenko , Max Filippov , "open list:ARM TCG CPUs" , "open list:PowerPC TCG CPUs" , "open list:RISC-V TCG CPUs" , "open list:S390 TCG CPUs" Subject: Re: [PATCH v3 08/20] gdbstub: extend GByteArray to read register helpers In-reply-to: Date: Thu, 19 Dec 2019 17:50:00 +0000 Message-ID: <87mubodx2v.fsf@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::441 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 19 Dec 2019 17:50:11 -0000 Damien Hedde writes: > Hi Alex, > > On 12/11/19 6:05 PM, Alex Benn=C3=A9e wrote: >> Instead of passing a pointer to memory now just extend the GByteArray >> to all the read register helpers. They can then safely append their >> data through the normal way. We don't bother with this abstraction for >> write registers as we have already ensured the buffer being copied >> from is the correct size. >>=20 >> Signed-off-by: Alex Benn=C3=A9e > > [...] > >> diff --git a/target/arm/helper.c b/target/arm/helper.c >> index 0ac950d6c71..6476245e789 100644 >> --- a/target/arm/helper.c >> +++ b/target/arm/helper.c >> @@ -47,30 +47,27 @@ static bool get_phys_addr_lpae(CPUARMState *env, tar= get_ulong address, >>=20=20 >> static void switch_mode(CPUARMState *env, int mode); >>=20=20 >> -static int vfp_gdb_get_reg(CPUARMState *env, uint8_t *buf, int reg) >> +static int vfp_gdb_get_reg(CPUARMState *env, GByteArray *buf, int reg) >> { >> int nregs; >>=20=20 >> /* VFP data registers are always little-endian. */ >> nregs =3D arm_feature(env, ARM_FEATURE_VFP3) ? 32 : 16; >> if (reg < nregs) { >> - stq_le_p(buf, *aa32_vfp_dreg(env, reg)); >> - return 8; >> + return gdb_get_reg64(buf, *aa32_vfp_dreg(env, reg)); > > It was a little-endian version, you've put a target-endian version. > Is that what you meant ? Yes - I suspect this would have been broken if used by a big-endian system. gdbstub generally (SVE excepted) wants things in target order. > >> } >> if (arm_feature(env, ARM_FEATURE_NEON)) { >> /* Aliases for Q regs. */ >> nregs +=3D 16; >> if (reg < nregs) { >> uint64_t *q =3D aa32_vfp_qreg(env, reg - 32); >> - stq_le_p(buf, q[0]); >> - stq_le_p(buf + 8, q[1]); >> - return 16; >> + return gdb_get_reg128(buf, q[0], q[1]); > > Ditto here. > >> } >> } >> switch (reg - nregs) { >> - case 0: stl_p(buf, env->vfp.xregs[ARM_VFP_FPSID]); return 4; >> - case 1: stl_p(buf, vfp_get_fpscr(env)); return 4; >> - case 2: stl_p(buf, env->vfp.xregs[ARM_VFP_FPEXC]); return 4; >> + case 0: return gdb_get_reg32(buf, env->vfp.xregs[ARM_VFP_FPSID]); b= reak; >> + case 1: return gdb_get_reg32(buf, vfp_get_fpscr(env)); break; >> + case 2: return gdb_get_reg32(buf, env->vfp.xregs[ARM_VFP_FPEXC]); b= reak; >> } >> return 0; >> } >> @@ -101,7 +98,7 @@ static int vfp_gdb_set_reg(CPUARMState *env, uint8_t = *buf, int reg) >> return 0; >> } >>=20=20 >> -static int aarch64_fpu_gdb_get_reg(CPUARMState *env, uint8_t *buf, int = reg) >> +static int aarch64_fpu_gdb_get_reg(CPUARMState *env, GByteArray *buf, i= nt reg) >> { >> switch (reg) { >> case 0 ... 31: >> @@ -204,7 +201,7 @@ static void write_raw_cp_reg(CPUARMState *env, const= ARMCPRegInfo *ri, >> } >> } >>=20=20 >> -static int arm_gdb_get_sysreg(CPUARMState *env, uint8_t *buf, int reg) >> +static int arm_gdb_get_sysreg(CPUARMState *env, GByteArray *buf, int re= g) >> { >> ARMCPU *cpu =3D env_archcpu(env); >> const ARMCPRegInfo *ri; > > [...] > >> diff --git a/target/ppc/gdbstub.c b/target/ppc/gdbstub.c >> index 823759c92e7..6f08021cc22 100644 >> --- a/target/ppc/gdbstub.c >> +++ b/target/ppc/gdbstub.c >> @@ -114,10 +114,11 @@ void ppc_maybe_bswap_register(CPUPPCState *env, ui= nt8_t *mem_buf, int len) >> * the FP regs zero size when talking to a newer gdb. >> */ >>=20=20 >> -int ppc_cpu_gdb_read_register(CPUState *cs, uint8_t *mem_buf, int n) >> +int ppc_cpu_gdb_read_register(CPUState *cs, GByteArray *buf, int n) >> { >> PowerPCCPU *cpu =3D POWERPC_CPU(cs); >> CPUPPCState *env =3D &cpu->env; >> + uint8_t *mem_buf; >> int r =3D ppc_gdb_register_len(n); >>=20=20 >> if (!r) { >> @@ -126,17 +127,17 @@ int ppc_cpu_gdb_read_register(CPUState *cs, uint8_= t *mem_buf, int n) >>=20=20 >> if (n < 32) { >> /* gprs */ >> - gdb_get_regl(mem_buf, env->gpr[n]); >> + gdb_get_regl(buf, env->gpr[n]); >> } else if (n < 64) { >> /* fprs */ >> - stfq_p(mem_buf, *cpu_fpr_ptr(env, n - 32)); >> + gdb_get_reg64(buf, *cpu_fpr_ptr(env, n - 32)); >> } else { >> switch (n) { >> case 64: >> - gdb_get_regl(mem_buf, env->nip); >> + gdb_get_regl(buf, env->nip); >> break; >> case 65: >> - gdb_get_regl(mem_buf, env->msr); >> + gdb_get_regl(buf, env->msr); >> break; >> case 66: >> { >> @@ -145,31 +146,33 @@ int ppc_cpu_gdb_read_register(CPUState *cs, uint8_= t *mem_buf, int n) >> for (i =3D 0; i < 8; i++) { >> cr |=3D env->crf[i] << (32 - ((i + 1) * 4)); >> } >> - gdb_get_reg32(mem_buf, cr); >> + gdb_get_reg32(buf, cr); >> break; >> } >> case 67: >> - gdb_get_regl(mem_buf, env->lr); >> + gdb_get_regl(buf, env->lr); >> break; >> case 68: >> - gdb_get_regl(mem_buf, env->ctr); >> + gdb_get_regl(buf, env->ctr); >> break; >> case 69: >> - gdb_get_reg32(mem_buf, env->xer); >> + gdb_get_reg32(buf, env->xer); >> break; >> case 70: >> - gdb_get_reg32(mem_buf, env->fpscr); >> + gdb_get_reg32(buf, env->fpscr); >> break; >> } >> } >> + mem_buf =3D buf->data - r; > > Should it not be something more like this ? > mem_buf =3D buf->data + buf->len - r; Good catch. > > There seem to be the same issue below for every > ppc_maybe_bswap_register() call. Fixed. --=20 Alex Benn=C3=A9e From MAILER-DAEMON Thu Dec 19 12:51:10 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1ihzx8-00044e-4a for mharc-qemu-arm@gnu.org; Thu, 19 Dec 2019 12:51:10 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:54691) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ihzx4-0003yZ-Jd for qemu-arm@nongnu.org; Thu, 19 Dec 2019 12:51:07 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ihzx3-0004zV-JF for qemu-arm@nongnu.org; Thu, 19 Dec 2019 12:51:06 -0500 Received: from mail-pg1-x542.google.com ([2607:f8b0:4864:20::542]:35803) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ihzx3-0004tc-8s for qemu-arm@nongnu.org; Thu, 19 Dec 2019 12:51:05 -0500 Received: by mail-pg1-x542.google.com with SMTP id l24so3516408pgk.2 for ; Thu, 19 Dec 2019 09:51:04 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=subject:to:cc:references:from:message-id:date:user-agent :mime-version:in-reply-to:content-language:content-transfer-encoding; bh=4r1dJHdQo0OjsGUYx+/2Vrzn84OYJujOtfe17Ka8aVE=; b=R7m8dzSXDXUEWY8YDLMUipwCYPic6/eXVvFpCcf+FFwBSwrjL/GH3xJrXv8E+nq6C9 xxrPvYbL8zbsWC9TijBP5toRPx7yXUKrnYuPRJsAG5rfGquefKqCs4QSLE7kiR5h0Zgv +Hq88OpkYenBEYgaoOh3dTkb488LL/wKRgOO+vwhUO5DFBYp73iaqHDLoVIJxKKl/fP5 RSJDFbSmqXTzKWsfeGHvuAAyovmTfTBm2HfrLu1zKwuDZ6OQBhdN+aycelVE/0L3fsgj EXOgBIKOkkBQBMR8qHfo/Zp9y5dbfqPp+C0x+sV5+/HHz9xmwR81jhqSDOofnV9paz89 SVmQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:subject:to:cc:references:from:message-id:date :user-agent:mime-version:in-reply-to:content-language :content-transfer-encoding; bh=4r1dJHdQo0OjsGUYx+/2Vrzn84OYJujOtfe17Ka8aVE=; b=nIozfe0/I/N1FDJAtOolqj0I2dwjYAm4axI7pXf3/RtjXaiqciGuoEO1yY/hKJ2YrA OTEFWsnVSkgAN8AzLt5RL9w0wjSIDBFilkZv8NeIW5NJ7bNomForeyGF0Rf/KaOy38T2 uGScvEEb6VcV+/QHn8AN1aCZJeaa+1jAygyNrwkFsu0i1UC1IXHT+O934rsbnSRNYkdV wT5ksG9RD+86n+DkjUdEumSl2kBm/r/nJ8nHDyOccjKcFNOa6eiNdyMkAOL58qI8YlIv /xdjSeZqEUTgiOwWVmP0j8orUoN7jTv/nK2wMhs6MZS/APW+4dU24szg5nf/M1RaKLrP Hoxg== X-Gm-Message-State: APjAAAXQlaD872kFSAvbuAKOe7KPICzw6ijvtMJJJ3vls5WYLyIirWpu z5C3ishMsrZbqBIVAtPYW64Vag== X-Google-Smtp-Source: APXvYqy8h6VOJ/GQhC0URqg5jF1nyaMRXxNe5Kj9AWDZBeTP2bQJINRIN6Mxve2qOXc9j8iqfPuViQ== X-Received: by 2002:a63:4d4c:: with SMTP id n12mr10509796pgl.212.1576777863828; Thu, 19 Dec 2019 09:51:03 -0800 (PST) Received: from ?IPv6:2605:e000:c74f:dc00:9de9:bce2:6ae3:53c4? ([2605:e000:c74f:dc00:9de9:bce2:6ae3:53c4]) by smtp.gmail.com with ESMTPSA id r1sm8091054pgp.15.2019.12.19.09.51.02 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 19 Dec 2019 09:51:03 -0800 (PST) Subject: Re: [PATCH] target/arm: fix IL bit for data abort exceptions To: Peter Maydell Cc: Jeff Kubascik , qemu-arm , QEMU Developers , Stewart Hildebrand , Jarvis Roach References: <20191217210230.99559-1-jeff.kubascik@dornerworks.com> <7a274247-e593-5828-73f8-2042971e8633@linaro.org> From: Richard Henderson Message-ID: <64d31889-6269-1f6d-6aad-8e863310cf79@linaro.org> Date: Thu, 19 Dec 2019 07:50:59 -1000 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.2.2 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 7bit X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::542 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 19 Dec 2019 17:51:08 -0000 On 12/19/19 2:43 AM, Peter Maydell wrote: > I think this is a regression introduced in commit 46beb58efbb8a2a32 > when we converted the Thumb decoder over to decodetree. Before that > 16 bit Thumb insns were in a different place in the old decoder and > the 16-bit Thumb path passed ISSIs16Bit in with its issflags. > (We should cc: qemu-stable@nongnu.org on the fix for this.) Oops, yes, that would be my fault. >>> /* ISS not valid if writeback */ >>> if (p && !w) { >>> - ret = rd; >>> + ret = rd | (s->is_16bit ? ISSIs16Bit : 0); >>> } else { >>> ret = ISSInvalid; >>> } > > Rather than setting an is_16bit flag, we could just use > "dc->base.pc_next - dc->pc_curr == 2", couldn't we? We could, yes. r~ From MAILER-DAEMON Thu Dec 19 12:57:59 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1ii03j-0006AI-Nj for mharc-qemu-arm@gnu.org; Thu, 19 Dec 2019 12:57:59 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:41350) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ii03g-00065M-VW for qemu-arm@nongnu.org; Thu, 19 Dec 2019 12:57:58 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ii03f-0000dd-1h for qemu-arm@nongnu.org; Thu, 19 Dec 2019 12:57:55 -0500 Received: from us-smtp-1.mimecast.com ([205.139.110.61]:53921 helo=us-smtp-delivery-1.mimecast.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1ii03e-0000Y8-Q7 for qemu-arm@nongnu.org; Thu, 19 Dec 2019 12:57:54 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1576778273; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=vgoAJPsyBWGNUC0qdNBP37n+f8fXPIZIj+IKfmqzm1g=; b=GBSANB5ksrEh6jKz5CUcCVySYFLVzDUCqCqWQaiZvwUnTfRGxraOMG5qFdngCp4G5U/Cwx mH9COQLmIU74YN5IoL8a6mJSfU22gLiNLd9yDbsMXUP/RUDv7M99uZqe38PS+VdM8ZBB7d K14SWsrQaZ/8gYD9ohSKG5+7BZ5JB9U= Received: from mimecast-mx01.redhat.com (mimecast-mx01.redhat.com [209.132.183.4]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-72-OuNnLlQAMuKqHMASxHVo6w-1; Thu, 19 Dec 2019 12:57:44 -0500 Received: from smtp.corp.redhat.com (int-mx03.intmail.prod.int.phx2.redhat.com [10.5.11.13]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx01.redhat.com (Postfix) with ESMTPS id 58A481856A8A; Thu, 19 Dec 2019 17:57:43 +0000 (UTC) Received: from localhost (ovpn-116-90.gru2.redhat.com [10.97.116.90]) by smtp.corp.redhat.com (Postfix) with ESMTP id DE2707EB64; Thu, 19 Dec 2019 17:57:42 +0000 (UTC) Date: Thu, 19 Dec 2019 14:57:41 -0300 From: Eduardo Habkost To: Igor Mammedov Cc: qemu-devel@nongnu.org, Marcel Apfelbaum , Tao Xu , Radoslaw Biernacki , Peter Maydell , Leif Lindholm , qemu-arm@nongnu.org, qemu-stable@nongnu.org Subject: Re: [PATCH 2/2] numa: properly check if numa is supported Message-ID: <20191219175741.GT498046@habkost.net> References: <1576154936-178362-1-git-send-email-imammedo@redhat.com> <1576154936-178362-3-git-send-email-imammedo@redhat.com> MIME-Version: 1.0 In-Reply-To: <1576154936-178362-3-git-send-email-imammedo@redhat.com> X-Scanned-By: MIMEDefang 2.79 on 10.5.11.13 X-MC-Unique: OuNnLlQAMuKqHMASxHVo6w-1 X-Mimecast-Spam-Score: 0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: quoted-printable Content-Disposition: inline X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 205.139.110.61 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 19 Dec 2019 17:57:59 -0000 On Thu, Dec 12, 2019 at 01:48:56PM +0100, Igor Mammedov wrote: > Commit aa57020774b, by mistake used MachineClass::numa_mem_supported > to check if NUMA is supported by machine and also as unrelated change > set it to true for sbsa-ref board. >=20 > Luckily change didn't break machines that support NUMA, as the field > is set to true for them. >=20 > But the field is not intended for checking if NUMA is supported and > will be flipped to false within this release for new machine types. >=20 > Fix it: > - by using previously used condition > !mc->cpu_index_to_instance_props || !mc->get_default_cpu_node_id > the first time and then use MachineState::numa_state down the road > to check if NUMA is supported > - dropping stray sbsa-ref chunk >=20 > Fixes: aa57020774b690a22be72453b8e91c9b5a68c516 > Signed-off-by: Igor Mammedov Reviewed-by: Eduardo Habkost I'm queueing this and plan to submit a pull request soon. --=20 Eduardo From MAILER-DAEMON Thu Dec 19 13:11:30 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1ii0Go-0007Jg-FZ for mharc-qemu-arm@gnu.org; Thu, 19 Dec 2019 13:11:30 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:60370) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ii0Gl-0007Dj-D3 for qemu-arm@nongnu.org; Thu, 19 Dec 2019 13:11:28 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ii0Gk-0005jT-3G for qemu-arm@nongnu.org; Thu, 19 Dec 2019 13:11:27 -0500 Received: from us-smtp-delivery-1.mimecast.com ([207.211.31.120]:22064 helo=us-smtp-1.mimecast.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1ii0Gj-0005dY-Qu for qemu-arm@nongnu.org; Thu, 19 Dec 2019 13:11:25 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1576779084; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=n6pbrKZ+N3J8EgOEAGNWuIizLRnL3QASgl8e3eexOCs=; b=DHrepha4rthFacIa/46JRZZ7aH5NS6cyv/2MXI2qO3JK18guiDXfY2bBEXwf8voiCvp0/G N8jmtvsUYxWctOHGGfHNN+ESOvozkcwkk6ouyOpQ0YRcHYQxYymWYiZ9F81NcQ0HMQABqh CU+e6AGnybsyR0JiK3yUGxZvWbH124g= Received: from mimecast-mx01.redhat.com (mimecast-mx01.redhat.com [209.132.183.4]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-53-vwIQXQheNmuIBjzxexoFXA-1; Thu, 19 Dec 2019 13:11:21 -0500 Received: from smtp.corp.redhat.com (int-mx06.intmail.prod.int.phx2.redhat.com [10.5.11.16]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx01.redhat.com (Postfix) with ESMTPS id 48206801E7E; Thu, 19 Dec 2019 18:11:19 +0000 (UTC) Received: from [10.36.116.117] (ovpn-116-117.ams2.redhat.com [10.36.116.117]) by smtp.corp.redhat.com (Postfix) with ESMTPS id 727165C1B0; Thu, 19 Dec 2019 18:11:10 +0000 (UTC) Subject: Re: [PATCH for-5.0 v11 04/20] virtio-iommu: Add the iommu regions To: Jean-Philippe Brucker Cc: eric.auger.pro@gmail.com, qemu-devel@nongnu.org, qemu-arm@nongnu.org, peter.maydell@linaro.org, mst@redhat.com, armbru@redhat.com, jean-philippe.brucker@arm.com, bharatb.linux@gmail.com, yang.zhong@intel.com, dgilbert@redhat.com, quintela@redhat.com, kevin.tian@intel.com, peterx@redhat.com, tnowicki@marvell.com References: <20191122182943.4656-1-eric.auger@redhat.com> <20191122182943.4656-5-eric.auger@redhat.com> <20191210163440.GC277340@myrica> From: Auger Eric Message-ID: <1bf85182-19dd-5e84-dbb7-1734be927e82@redhat.com> Date: Thu, 19 Dec 2019 19:11:08 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101 Thunderbird/60.4.0 MIME-Version: 1.0 In-Reply-To: <20191210163440.GC277340@myrica> Content-Language: en-US X-Scanned-By: MIMEDefang 2.79 on 10.5.11.16 X-MC-Unique: vwIQXQheNmuIBjzxexoFXA-1 X-Mimecast-Spam-Score: 0 Content-Type: text/plain; charset=windows-1252 Content-Transfer-Encoding: 7bit X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 207.211.31.120 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 19 Dec 2019 18:11:29 -0000 Hi Jean, On 12/10/19 5:34 PM, Jean-Philippe Brucker wrote: > Two small things below, but looks good overall > > Reviewed-by: Jean-Philippe Brucker > > On Fri, Nov 22, 2019 at 07:29:27PM +0100, Eric Auger wrote: >> +static AddressSpace *virtio_iommu_find_add_as(PCIBus *bus, void *opaque, >> + int devfn) >> +{ >> + VirtIOIOMMU *s = opaque; >> + IOMMUPciBus *sbus = g_hash_table_lookup(s->as_by_busptr, bus); >> + static uint32_t mr_index; >> + IOMMUDevice *sdev; >> + >> + if (!sbus) { >> + sbus = g_malloc0(sizeof(IOMMUPciBus) + >> + sizeof(IOMMUDevice *) * IOMMU_PCI_DEVFN_MAX); >> + sbus->bus = bus; >> + g_hash_table_insert(s->as_by_busptr, bus, sbus); >> + } >> + >> + sdev = sbus->pbdev[devfn]; >> + if (!sdev) { >> + char *name = g_strdup_printf("%s-%d-%d", >> + TYPE_VIRTIO_IOMMU_MEMORY_REGION, >> + mr_index++, devfn); >> + sdev = sbus->pbdev[devfn] = g_malloc0(sizeof(IOMMUDevice)); >> + >> + sdev->viommu = s; >> + sdev->bus = bus; >> + sdev->devfn = devfn; > > It might be better to store the endpoint ID in IOMMUDevice, then you could > get rid of virtio_iommu_get_sid(), and remove a tiny bit of overhead in > virtio_iommu_translate(). But I doubt it's significant. virtio_iommu_find_add_as() gets called on PCI bus enumeration. At that point, the bus number may not be resolved. So I cannot retrieve and set the bus_number in this function. When virtio_iommu_get_sid() is called we are sure pci_bus_num(dev->bus) returns a correct value. > > [...] >> +static const TypeInfo virtio_iommu_memory_region_info = { >> + .parent = TYPE_IOMMU_MEMORY_REGION, >> + .name = TYPE_VIRTIO_IOMMU_MEMORY_REGION, >> + .class_init = virtio_iommu_memory_region_class_init, >> +}; >> + >> + > > nit: newline. Thanks Eric > > Thanks, > Jean > From MAILER-DAEMON Thu Dec 19 13:23:03 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1ii0Rz-0004ew-5l for mharc-qemu-arm@gnu.org; Thu, 19 Dec 2019 13:23:03 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:37212) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ii0Rv-0004WY-5b for qemu-arm@nongnu.org; Thu, 19 Dec 2019 13:23:00 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ii0Rr-0003gJ-UB for qemu-arm@nongnu.org; Thu, 19 Dec 2019 13:22:57 -0500 Received: from us-smtp-delivery-1.mimecast.com ([205.139.110.120]:55805 helo=us-smtp-1.mimecast.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1ii0Rr-0003an-FW for qemu-arm@nongnu.org; Thu, 19 Dec 2019 13:22:55 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1576779774; 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(ovpn-116-70.gru2.redhat.com [10.97.116.70]) by smtp.corp.redhat.com (Postfix) with ESMTPS id 45B9226E6E; Thu, 19 Dec 2019 18:22:43 +0000 (UTC) Date: Thu, 19 Dec 2019 13:22:39 -0500 From: Cleber Rosa To: Philippe =?iso-8859-1?Q?Mathieu-Daud=E9?= Cc: qemu-devel@nongnu.org, Guenter Roeck , Niek Linnenbank , Peter Maydell , qemu-arm@nongnu.org, Philippe =?iso-8859-1?Q?Mathieu-Daud=E9?= Subject: Re: [PATCH 2/5] tests/boot_linux_console: Add initrd test for the Orange Pi PC board Message-ID: <20191219182239.GA24165@localhost.localdomain> References: <20191217182730.943-1-f4bug@amsat.org> <20191217182730.943-3-f4bug@amsat.org> MIME-Version: 1.0 In-Reply-To: <20191217182730.943-3-f4bug@amsat.org> X-Scanned-By: MIMEDefang 2.84 on 10.5.11.23 X-Mimecast-Spam-Score: 0 Content-Type: multipart/signed; micalg=pgp-sha256; protocol="application/pgp-signature"; boundary="jRHKVT23PllUwdXP" Content-Disposition: inline X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 205.139.110.120 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 19 Dec 2019 18:23:01 -0000 --jRHKVT23PllUwdXP Content-Type: text/plain; charset=iso-8859-1 Content-Disposition: inline Content-Transfer-Encoding: quoted-printable On Tue, Dec 17, 2019 at 07:27:27PM +0100, Philippe Mathieu-Daud=E9 wrote: > This test boots a Linux kernel on a OrangePi PC board and verify > the serial output is working. >=20 > The kernel image and DeviceTree blob are built by the Raspbian > project (based on Debian): > https://www.raspbian.org/RaspbianImages >=20 > The cpio image used comes from the linux-build-test project: > https://github.com/groeck/linux-build-test >=20 > If ARM is a target being built, "make check-acceptance" will > automatically include this test by the use of the "arch:arm" tags. >=20 > Alternatively, this test can be run using: >=20 > $ avocado --show=3Dconsole run -t machine:orangepi-pc tests/acceptance/= boot_linux_console.py > console: Uncompressing Linux... done, booting the kernel. > console: Booting Linux on physical CPU 0x0 > console: Linux version 4.20.7-sunxi (root@armbian.com) (gcc version 7.2= .1 20171011 (Linaro GCC 7.2-2017.11)) #5.75 SMP Fri Feb 8 09:02:10 CET 2019 > console: CPU: ARMv7 Processor [410fc075] revision 5 (ARMv7), cr=3D50c53= 87d > console: CPU: div instructions available: patching division code > console: CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing instruc= tion cache > console: OF: fdt: Machine model: Xunlong Orange Pi PC > [...] > console: Trying to unpack rootfs image as initramfs... > console: Freeing initrd memory: 3256K > console: Freeing unused kernel memory: 1024K > console: Run /init as init process > console: mount: mounting devtmpfs on /dev failed: Device or resource bu= sy > console: Starting logging: OK > console: Initializing random number generator... random: dd: uninitiali= zed urandom read (512 bytes read) > console: done. > console: Starting network: OK > console: Found console ttyS0 > console: Linux version 4.20.7-sunxi (root@armbian.com) (gcc version 7.2= .1 20171011 (Linaro GCC 7.2-2017.11)) #5.75 SMP Fri Feb 8 09:02:10 CET 2019 > console: Boot successful. > console: cat /proc/cpuinfo > console: / # cat /proc/cpuinfo > console: processor : 0 > console: model name : ARMv7 Processor rev 5 (v7l) > console: BogoMIPS : 125.00 > console: Features : half thumb fastmult vfp edsp neon vfpv3 tls v= fpv4 idiva idivt vfpd32 lpae evtstrm > console: CPU implementer : 0x41 > console: CPU architecture: 7 > console: CPU variant : 0x0 > console: CPU part : 0xc07 > console: CPU revision : 5 > [...] > console: processor : 3 > console: model name : ARMv7 Processor rev 5 (v7l) > console: BogoMIPS : 125.00 > console: Features : half thumb fastmult vfp edsp neon vfpv3 tls v= fpv4 idiva idivt vfpd32 lpae evtstrm > console: CPU implementer : 0x41 > console: CPU architecture: 7 > console: CPU variant : 0x0 > console: CPU part : 0xc07 > console: CPU revision : 5 > console: Hardware : Allwinner sun8i Family > console: Revision : 0000 > console: Serial : 0000000000000000 > console: cat /proc/iomem > console: / # cat /proc/iomem > console: 01000000-010fffff : clock@1000000 > console: 01c00000-01c00fff : system-control@1c00000 > console: 01c02000-01c02fff : dma-controller@1c02000 > [...] > console: reboot > console: / # reboot > console: / # Found console ttyS0 > console: Stopping network: OK > console: hrtimer: interrupt took 21852064 ns > console: Saving random seed... random: dd: uninitialized urandom read (= 512 bytes read) > console: done. > console: Stopping logging: OK > console: umount: devtmpfs busy - remounted read-only > console: umount: can't unmount /: Invalid argument > console: The system is going down NOW! > console: Sent SIGTERM to all processes > console: Sent SIGKILL to all processes > console: Requesting system reboot > console: reboot: Restarting system > PASS (48.32 s) > JOB TIME : 49.16 s >=20 > Signed-off-by: Philippe Mathieu-Daud=E9 > --- > tests/acceptance/boot_linux_console.py | 41 ++++++++++++++++++++++++++ > 1 file changed, 41 insertions(+) >=20 > diff --git a/tests/acceptance/boot_linux_console.py b/tests/acceptance/bo= ot_linux_console.py > index 820239e439..daabd47404 100644 > --- a/tests/acceptance/boot_linux_console.py > +++ b/tests/acceptance/boot_linux_console.py > @@ -437,6 +437,47 @@ class BootLinuxConsole(Test): > console_pattern =3D 'Kernel command line: %s' % kernel_command_l= ine > self.wait_for_console_pattern(console_pattern) > =20 > + def test_arm_orangepi_initrd(self): Like in the previous patch, isn't it a good idea to name this after the exa= ct machine model, that is, test_arm_orangepi_pc_initrd? > + """ > + :avocado: tags=3Darch:arm > + :avocado: tags=3Dmachine:orangepi-pc > + """ > + deb_url =3D ('https://apt.armbian.com/pool/main/l/' > + 'linux-4.20.7-sunxi/linux-image-dev-sunxi_5.75_armhf.= deb') > + deb_hash =3D '1334c29c44d984ffa05ed10de8c3361f33d78315' > + deb_path =3D self.fetch_asset(deb_url, asset_hash=3Ddeb_hash) > + kernel_path =3D self.extract_from_deb(deb_path, > + '/boot/vmlinuz-4.20.7-sunxi'= ) > + dtb_path =3D '/usr/lib/linux-image-dev-sunxi/sun8i-h3-orangepi-p= c.dtb' > + dtb_path =3D self.extract_from_deb(deb_path, dtb_path) > + initrd_url =3D ('https://github.com/groeck/linux-build-test/raw/= ' > + '2eb0a73b5d5a28df3170c546ddaaa9757e1e0848/rootfs/' > + 'arm/rootfs-armv7a.cpio.gz') > + initrd_hash =3D '604b2e45cdf35045846b8bbfbf2129b1891bdc9c' > + initrd_path_gz =3D self.fetch_asset(initrd_url, asset_hash=3Dini= trd_hash) > + initrd_path =3D os.path.join(self.workdir, 'rootfs.cpio') > + archive.gzip_uncompress(initrd_path_gz, initrd_path) > + > + self.vm.set_machine('orangepi-pc') There's no need to set the machine type manually since ba21bde93, the one set by the ":avocado: tags=3Dmachine" will be used. Tested-by: Cleber Rosa If this line is dropped: Reviewed-by: Cleber Rosa --jRHKVT23PllUwdXP Content-Type: application/pgp-signature; name="signature.asc" -----BEGIN PGP SIGNATURE----- iQIzBAEBCAAdFiEEeruW64tGuU1eD+m7ZX6NM6XyCfMFAl37v+0ACgkQZX6NM6Xy CfM0UQ/+KlZKFMP1Z+n+3P/dhHONJSxepUZJp83ZFVIuF+F1I10LUj6E0xCy4MYV c+ic+zkPof0RDrx3kZg7SSxC0G1k4eJlr5rVgK5uKEIJaTHBR/oRrPXxKTj553qL CZWk4JZy+25rPrC5jSRYm3hWv6eLFbKyir6xmHnD2f39QrBD64Ywn+9ZJD+Gg/VC MmmVfUrOSaEEK29tI1kY7YsRsKMWny/FE/+cy6jpiq88zWx/AS2L9/+Ew6FB7hjJ eVBNxTdt6xBxe3+fQrDE/3TxWD8GuABOqR0x4fwfo9Mv2uRzzASh0D8vv6poT8Ru EoqZoHy2TrNTSuXFZItJ3FS3N7KcEI/nn90gQJd4XNL9s4kz3IWzhM0iFaTe0ZKW KmWC7q+oAQBXBieIdgnqscHPS08ZdD+WMlOw2pO5YEntyAJlJ6+kzOC2ilIfosB0 AWplQE0DfGWtIfcj+UgU0Lm4AySq4lGe8T2zzbqVVIvgUK9/LuHckc8tTfvVuJ9R sCkP9klYlkgpVy7m9zDqzd45RXX4uFxnLNrooMX24MF6kIksfIp31qDQ6vABMaSt f1MPA4ujyMsdCLud+PG94WRQ9M5ooYwfltaIJjbje6YBuMMfnzbFMX7MHAaQvf6H pv+uO7j87Jf4LBbOXZbPzxGcGGZpHSgMn5EIWfOrbCixjd2ytM8= =av1r -----END PGP SIGNATURE----- --jRHKVT23PllUwdXP-- From MAILER-DAEMON Thu Dec 19 13:25:28 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1ii0UK-00080X-Bv for mharc-qemu-arm@gnu.org; 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Thu, 19 Dec 2019 13:25:18 -0500 X-MC-Unique: _ARlPYcwNPa6UVu-fWkD1Q-1 Received: from smtp.corp.redhat.com (int-mx06.intmail.prod.int.phx2.redhat.com [10.5.11.16]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx01.redhat.com (Postfix) with ESMTPS id AC7271005513; Thu, 19 Dec 2019 18:25:16 +0000 (UTC) Received: from localhost.localdomain (ovpn-116-70.gru2.redhat.com [10.97.116.70]) by smtp.corp.redhat.com (Postfix) with ESMTPS id 18C155C1B0; Thu, 19 Dec 2019 18:25:14 +0000 (UTC) Date: Thu, 19 Dec 2019 13:25:12 -0500 From: Cleber Rosa To: Philippe =?iso-8859-1?Q?Mathieu-Daud=E9?= Cc: qemu-devel@nongnu.org, Guenter Roeck , Niek Linnenbank , Peter Maydell , qemu-arm@nongnu.org Subject: Re: [PATCH 1/5] tests/boot_linux_console: Add a quick test for the OrangePi PC board Message-ID: <20191219182512.GA25306@localhost.localdomain> References: <20191217182730.943-1-f4bug@amsat.org> <20191217182730.943-2-f4bug@amsat.org> <20191219010511.GA3582@localhost.localdomain> MIME-Version: 1.0 In-Reply-To: <20191219010511.GA3582@localhost.localdomain> X-Scanned-By: MIMEDefang 2.79 on 10.5.11.16 X-Mimecast-Spam-Score: 0 Content-Type: multipart/signed; micalg=pgp-sha256; protocol="application/pgp-signature"; boundary="fdj2RfSjLxBAspz7" Content-Disposition: inline X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 205.139.110.61 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 19 Dec 2019 18:25:27 -0000 --fdj2RfSjLxBAspz7 Content-Type: text/plain; charset=iso-8859-1 Content-Disposition: inline Content-Transfer-Encoding: quoted-printable On Wed, Dec 18, 2019 at 08:05:15PM -0500, Cleber Rosa wrote: > On Tue, Dec 17, 2019 at 07:27:26PM +0100, Philippe Mathieu-Daud=E9 wrote: > > This test boots a Linux kernel on a OrangePi PC board and verify > > the serial output is working. > >=20 > > The kernel image and DeviceTree blob are built by the Raspbian > > project (based on Debian): > > https://www.raspbian.org/RaspbianImages > >=20 > > If ARM is a target being built, "make check-acceptance" will > > automatically include this test by the use of the "arch:arm" tags. > >=20 > > Alternatively, this test can be run using: > >=20 > > $ make check-venv > > $ ./tests/venv/bin/avocado --show=3Dconsole,app run -t machine:orange= pi-pc tests/acceptance/boot_linux_console.py > > JOB ID : 2e4d15eceb13c33672af406f08171e6e9de1414a > > JOB LOG : ~/job-results/job-2019-12-17T05.46-2e4d15e/job.log > > (1/1) tests/acceptance/boot_linux_console.py:BootLinuxConsole.test_ar= m_orangepi: > > console: Uncompressing Linux... done, booting the kernel. > > console: Booting Linux on physical CPU 0x0 > > console: Linux version 4.20.7-sunxi (root@armbian.com) (gcc version 7= .2.1 20171011 (Linaro GCC 7.2-2017.11)) #5.75 SMP Fri Feb 8 09:02:10 CET 20= 19 > > console: CPU: ARMv7 Processor [410fc075] revision 5 (ARMv7), cr=3D50c= 5387d > > console: CPU: div instructions available: patching division code > > console: CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing instr= uction cache > > console: OF: fdt: Machine model: Xunlong Orange Pi PC > > console: Memory policy: Data cache writealloc > > console: OF: reserved mem: failed to allocate memory for node 'cma@4a= 000000' > > console: cma: Failed to reserve 128 MiB > > console: psci: probing for conduit method from DT. > > console: psci: PSCIv0.2 detected in firmware. > > console: psci: Using standard PSCI v0.2 function IDs > > console: psci: Trusted OS migration not required > > console: random: get_random_bytes called from start_kernel+0x8d/0x3c2= with crng_init=3D0 > > console: percpu: Embedded 18 pages/cpu @(ptrval) s41228 r8192 d24308 = u73728 > > console: Built 1 zonelists, mobility grouping on. Total pages: 32480 > > console: Kernel command line: printk.time=3D0 console=3DttyS0,115200 > > PASS (8.59 s) > > JOB TIME : 8.81 s > >=20 > > Signed-off-by: Philippe Mathieu-Daud=E9 > > --- > > tests/acceptance/boot_linux_console.py | 26 ++++++++++++++++++++++++++ > > 1 file changed, 26 insertions(+) > >=20 > > diff --git a/tests/acceptance/boot_linux_console.py b/tests/acceptance/= boot_linux_console.py > > index 7e41cebd47..820239e439 100644 > > --- a/tests/acceptance/boot_linux_console.py > > +++ b/tests/acceptance/boot_linux_console.py > > @@ -411,6 +411,32 @@ class BootLinuxConsole(Test): > > self.wait_for_console_pattern('Boot successful.') > > # TODO user command, for now the uart is stuck > > =20 > > + def test_arm_orangepi(self): >=20 > Maybe rename the test to include the full machine type? I mean, > "test_arm_orangepi_pc"? >=20 > > + """ > > + :avocado: tags=3Darch:arm > > + :avocado: tags=3Dmachine:orangepi-pc > > + """ > > + deb_url =3D ('https://apt.armbian.com/pool/main/l/' > > + 'linux-4.20.7-sunxi/linux-image-dev-sunxi_5.75_armh= f.deb') > > + deb_hash =3D '1334c29c44d984ffa05ed10de8c3361f33d78315' > > + deb_path =3D self.fetch_asset(deb_url, asset_hash=3Ddeb_hash) > > + kernel_path =3D self.extract_from_deb(deb_path, > > + '/boot/vmlinuz-4.20.7-sunx= i') > > + dtb_path =3D '/usr/lib/linux-image-dev-sunxi/sun8i-h3-orangepi= -pc.dtb' > > + dtb_path =3D self.extract_from_deb(deb_path, dtb_path) > > + > > + self.vm.set_machine('orangepi-pc') Missed this on the previous message: you should drop this line, as the machine type will be set automatically (given a machine tag exists) since ba21bde93. - Cleber. > > + self.vm.set_console() > > + kernel_command_line =3D (self.KERNEL_COMMON_COMMAND_LINE + > > + 'console=3DttyS0,115200n8 ' > > + 'earlycon=3Duart,mmio32,0x1c28000') > > + self.vm.add_args('-kernel', kernel_path, > > + '-dtb', dtb_path, > > + '-append', kernel_command_line) > > + self.vm.launch() > > + console_pattern =3D 'Kernel command line: %s' % kernel_command= _line > > + self.wait_for_console_pattern(console_pattern) > > + > > def test_s390x_s390_ccw_virtio(self): > > """ > > :avocado: tags=3Darch:s390x > > --=20 > > 2.21.0 > >=20 >=20 > Either way, >=20 > Reviewed-by: Cleber Rosa > Tested-by: Cleber Rosa --fdj2RfSjLxBAspz7 Content-Type: application/pgp-signature; name="signature.asc" -----BEGIN PGP SIGNATURE----- iQIzBAEBCAAdFiEEeruW64tGuU1eD+m7ZX6NM6XyCfMFAl37wIgACgkQZX6NM6Xy CfNZnw//a7BYM529Tkgrssl/gkKEqJeyT0Ftz5baaz659b38cO6jsjlbAFJse7pJ MEebW+309wuhQaXWOPdtKCc3ynzzrSg4RaK1Vp4XTwyXkEQHTg6T2pZNM/pcOrne 4wra3kMSTkxCR2yFUJ07aGHgU9rJN80N2uT1GNLvd7PUGz3rPqR473y0FWLG9Nc+ bmO8XCOnglsE+MAkCQ1n/aJHINDpMRdEZdaJgTWj2OsPDGYvg1fDL8KN9liGfDOd 2FFImZwEwRecz7qsN8xBatWvm63iry3WYq974BixmJxeYsKuDNFHoJoEcByTBIT9 39E+dlb/y8Nuqtsjn7N3plZVxnatevrGS5oC5Pj/4TkHalhD4IZ6qxGN7zAhJ6Lf swdEnX1INuH+37SF9BBK6Zk9NThaxR5UrARKt5byzaD2I3ReFgd1aGnXn3uyRhSb ks9oauPF32KocY6TKp/qpXch2umTeU9gKOt60er4Rp+5bI4aTigNW6ZcW/Rxzqt5 3ATWjsy9yEYvN5KJhLO2EpF6qOWukfuCgCJI/qcdAggYr5Djk1ELxZJlP5GFiIqo uY2rfG0cG7KYy9A+acdBYoXoF9BgJ6T3Qq5kp4oGIASMHlzpGLyCiMKxYFycrHnW fUUq7CERgCjsAK8WU1XQqWTestlwxvthA9GepOSa8X6DJiDwZNw= =hkcH -----END PGP SIGNATURE----- --fdj2RfSjLxBAspz7-- From MAILER-DAEMON Thu Dec 19 13:31:36 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1ii0aE-0006nj-GW for mharc-qemu-arm@gnu.org; Thu, 19 Dec 2019 13:31:36 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:55375) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ii0aB-0006nN-7I for qemu-arm@nongnu.org; Thu, 19 Dec 2019 13:31:32 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ii0a7-0007nt-6k for qemu-arm@nongnu.org; Thu, 19 Dec 2019 13:31:28 -0500 Received: from us-smtp-1.mimecast.com ([207.211.31.81]:31967 helo=us-smtp-delivery-1.mimecast.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1ii0a5-0007kc-G9 for qemu-arm@nongnu.org; Thu, 19 Dec 2019 13:31:25 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1576780284; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=L9FWGWBUkF9tQ616rpbMJG8NkogpoEn8oAXnWBtYw1A=; b=Laf8Y/ehnldXarz2/eDStd39h2f//hiKD1Py7GDUCOneN5/FflwFKvDoFAtXiNTooWWiYx xc4Mx38K1RTMueowc7MiCCR9Y4lL9Kz+HlmFzRLkXi6lOSOvhVLgaKLbYLLu57l4h/VDeh xIDABnkW6qhNWHo5zWxGc8+RPZgqNcU= Received: from mimecast-mx01.redhat.com (mimecast-mx01.redhat.com [209.132.183.4]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-379-z_A4zvb8OBGejzTjLIywcQ-1; Thu, 19 Dec 2019 13:31:23 -0500 Received: from smtp.corp.redhat.com (int-mx06.intmail.prod.int.phx2.redhat.com [10.5.11.16]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx01.redhat.com (Postfix) with ESMTPS id 1D572800D48; Thu, 19 Dec 2019 18:31:21 +0000 (UTC) Received: from [10.36.116.117] (ovpn-116-117.ams2.redhat.com [10.36.116.117]) by smtp.corp.redhat.com (Postfix) with ESMTPS id E833E5C1B0; Thu, 19 Dec 2019 18:31:10 +0000 (UTC) Subject: Re: [PATCH for-5.0 v11 05/20] virtio-iommu: Endpoint and domains structs and helpers To: Jean-Philippe Brucker Cc: eric.auger.pro@gmail.com, qemu-devel@nongnu.org, qemu-arm@nongnu.org, peter.maydell@linaro.org, mst@redhat.com, armbru@redhat.com, jean-philippe.brucker@arm.com, bharatb.linux@gmail.com, yang.zhong@intel.com, dgilbert@redhat.com, quintela@redhat.com, kevin.tian@intel.com, peterx@redhat.com, tnowicki@marvell.com References: <20191122182943.4656-1-eric.auger@redhat.com> <20191122182943.4656-6-eric.auger@redhat.com> <20191210163716.GD277340@myrica> From: Auger Eric Message-ID: <28597404-b9ac-8c16-e9e8-ad5793f2f5a3@redhat.com> Date: Thu, 19 Dec 2019 19:31:08 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101 Thunderbird/60.4.0 MIME-Version: 1.0 In-Reply-To: <20191210163716.GD277340@myrica> Content-Language: en-US X-Scanned-By: MIMEDefang 2.79 on 10.5.11.16 X-MC-Unique: z_A4zvb8OBGejzTjLIywcQ-1 X-Mimecast-Spam-Score: 0 Content-Type: text/plain; charset=windows-1252 Content-Transfer-Encoding: 7bit X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 207.211.31.81 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 19 Dec 2019 18:31:32 -0000 Hi Jean, On 12/10/19 5:37 PM, Jean-Philippe Brucker wrote: > On Fri, Nov 22, 2019 at 07:29:28PM +0100, Eric Auger wrote: >> +typedef struct viommu_domain { >> + uint32_t id; >> + GTree *mappings; >> + QLIST_HEAD(, viommu_endpoint) endpoint_list; >> +} viommu_domain; >> + >> +typedef struct viommu_endpoint { >> + uint32_t id; >> + viommu_domain *domain; >> + QLIST_ENTRY(viommu_endpoint) next; >> +} viommu_endpoint; > > There might be a way to merge viommu_endpoint and the IOMMUDevice > structure introduced in patch 4, since they both represent one endpoint. > Maybe virtio_iommu_find_add_pci_as() could add the IOMMUDevice to > s->endpoints, and IOMMUDevice could store the endpoint ID rather than bus > and devfn. On PCI bus enumeration we locally store the PCI bus hierarchy under the form of GHashTable of IOMMUDevice indexed by iommu_pci_bus pointer. Those are all the devices attached to the downstream buses. We also use an array of iommu pci bus pointers indexed by bus number that is lazily populated due to the fact, at enumeration time we do know the bus number yet. As you pointed, I haven't used the array of iommu pci bus pointers indexed by bus number in this series and I should actually. Currently I am not checking on attach that the sid effectively corresponds to a sid protected by this iommu. I will add this in my next version. The above structures are used in intel_iommu and smmu code as well and I think eventually this may be factorized a common base class.. on the other hand the gtree of viommu_endpoint - soon renamed in CamelCase form ;-) - corresponds to the EPs that are actually attached to any domain. It is indexed by sid and not by bus pointer. This is more adapted to the virtio-iommu case. So, despite your suggestion, I am tempted to keep the different structures as the first ones are common to all iommu emulation code and the last is adapted to the virtio-iommu operations. Thoughts? Eric > >> +typedef struct viommu_interval { >> + uint64_t low; >> + uint64_t high; >> +} viommu_interval; > > I guess these should be named in CamelCase? Although if we're allowed to > choose my vote goes to underscores :) > > Thanks, > Jean > From MAILER-DAEMON Thu Dec 19 13:51:39 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1ii0tf-000735-Dz for mharc-qemu-arm@gnu.org; Thu, 19 Dec 2019 13:51:39 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:39306) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ii0tc-0006zq-Nv for qemu-arm@nongnu.org; Thu, 19 Dec 2019 13:51:37 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ii0tb-0007aw-MP for qemu-arm@nongnu.org; Thu, 19 Dec 2019 13:51:36 -0500 Received: from mail-wr1-x433.google.com ([2a00:1450:4864:20::433]:45402) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ii0tZ-0007F6-9M; Thu, 19 Dec 2019 13:51:33 -0500 Received: by mail-wr1-x433.google.com with SMTP id j42so7019940wrj.12; Thu, 19 Dec 2019 10:51:32 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=eIBy99noocVmlwSAa63POWN6vKv6FpnLkLhwBwwq9LM=; b=rzuwWUvW7fxrR8Q8rS5X13OM54/eLmN+zTAKxDRco/Oq+BgWmNrUIl1hDDIWXer+Fy L8YnYjYdzu/VREz33h1DmdVp1ZV1AaGR3fO9NBba+UOJNV1pQdpBbqAuC6dumVMl6qZP UlGW6/h5H1PWsw/K4YpyEoRngGgWynIlAal3ptwF+FFioIhDWpw+Nq8o5FPwZrYlr7ar RnhS792N/crlExsgvEPRX4/UKZi+f9ovgG6Jb2hguh3dgpmivk+BHr6KLFHkKHrWyiuZ 1Srq0elLFhgW9+pZ9HOj/JnX1wLx8CeNIT5NUZhw64eSIcTOLtRs4lFRTlIbMI0qA6pc JTTg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=eIBy99noocVmlwSAa63POWN6vKv6FpnLkLhwBwwq9LM=; b=f8DydsLICYizaAkKFyJFFmJB+Lu4/GBxutH+i2NeRTYCPzGUiatAsi1WtJoFdaSD5W XiiofyIQlmJY3gbourO/156bVSCQlSHWgf1Bh22xgurwjyK0fTWGsej0jcrJWnWRQWZn uyhvtRNEf2iuTXKGMgL6zvTEc8iRuLnegl/1vz0gSgBA3zWdutVo3SZudvvEkq6JPEtS 3L+gI+JuHGI7XkK8PoiDRQ9Z0fqkiUhKYcsh/sJ8fgXd0/4+SyHcmiA/ilJmFOFnFWf8 tnf2KkYiC43kx5jziqrsCbeVd/QXEvhjPOCe2XsMCDg790BTgKE9iMWO/pAzZUwP8q8k AYUQ== X-Gm-Message-State: APjAAAVcnU76KWeiUNlDt/eI6/YzskyYRDTXQZyw5Zxa8GD8mFNLYScB drQWW4G6qaQ0mfN4OpTTZzjB850g X-Google-Smtp-Source: APXvYqznBI30MLzRunuvTH94RbArJIo8XyU1MvwcT9Wtl4G1B96s4+YMJ9L6JV0fFjxe8mEQ6WjUCw== X-Received: by 2002:adf:c746:: with SMTP id b6mr10451458wrh.298.1576781490780; Thu, 19 Dec 2019 10:51:30 -0800 (PST) Received: from x1w.redhat.com (34.red-83-42-66.dynamicip.rima-tde.net. [83.42.66.34]) by smtp.gmail.com with ESMTPSA id b67sm7435494wmc.38.2019.12.19.10.51.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 19 Dec 2019 10:51:30 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org, Niek Linnenbank Cc: Peter Maydell , Beniamino Galvani , qemu-arm@nongnu.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH 01/13] hw/timer/allwinner: Use the AW_A10_PIT_TIMER_NR definition Date: Thu, 19 Dec 2019 19:51:15 +0100 Message-Id: <20191219185127.24388-2-f4bug@amsat.org> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20191219185127.24388-1-f4bug@amsat.org> References: <20191219185127.24388-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 8bit X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::433 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 19 Dec 2019 18:51:37 -0000 We have a definition for this magic value '6', use it. Signed-off-by: Philippe Mathieu-Daudé --- include/hw/timer/allwinner-a10-pit.h | 2 +- hw/timer/allwinner-a10-pit.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/include/hw/timer/allwinner-a10-pit.h b/include/hw/timer/allwinner-a10-pit.h index 871c95b512..6aceda81ee 100644 --- a/include/hw/timer/allwinner-a10-pit.h +++ b/include/hw/timer/allwinner-a10-pit.h @@ -32,7 +32,7 @@ #define AW_A10_PIT_TIMER_BASE 0x10 #define AW_A10_PIT_TIMER_BASE_END \ - (AW_A10_PIT_TIMER_BASE * 6 + AW_A10_PIT_TIMER_COUNT) + (AW_A10_PIT_TIMER_BASE * AW_A10_PIT_TIMER_NR + AW_A10_PIT_TIMER_COUNT) #define AW_A10_PIT_DEFAULT_CLOCK 0x4 diff --git a/hw/timer/allwinner-a10-pit.c b/hw/timer/allwinner-a10-pit.c index aae880f5b3..117e5c7bf8 100644 --- a/hw/timer/allwinner-a10-pit.c +++ b/hw/timer/allwinner-a10-pit.c @@ -225,7 +225,7 @@ static void a10_pit_reset(DeviceState *dev) s->irq_status = 0; a10_pit_update_irq(s); - for (i = 0; i < 6; i++) { + for (i = 0; i < AW_A10_PIT_TIMER_NR; i++) { s->control[i] = AW_A10_PIT_DEFAULT_CLOCK; s->interval[i] = 0; s->count[i] = 0; -- 2.21.0 From MAILER-DAEMON Thu Dec 19 13:51:41 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1ii0tg-00075U-Qs for mharc-qemu-arm@gnu.org; Thu, 19 Dec 2019 13:51:40 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:39434) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ii0td-00070m-Ng for qemu-arm@nongnu.org; Thu, 19 Dec 2019 13:51:38 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ii0tc-0007gg-LB for qemu-arm@nongnu.org; Thu, 19 Dec 2019 13:51:37 -0500 Received: from mail-wm1-x336.google.com ([2a00:1450:4864:20::336]:54934) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ii0ta-0007Q0-BO; Thu, 19 Dec 2019 13:51:34 -0500 Received: by mail-wm1-x336.google.com with SMTP id b19so6513403wmj.4; Thu, 19 Dec 2019 10:51:34 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=VamSeBNb0W35YTaE5KKNIilAYQcTaYH0JIGT88S7LVU=; b=lGlEoLZ4HCVjqxq5Zd6ssPum8e5x3eIbiQJpheWrOxKN3wrx+79F/RLx/vlxq+4i7W LpOCvnyKz6ylR8adNjWfnacEyamkPFYJv87LZbZH1mtuIfQ6/qF6hZgUZHZqdxymdxhB uBrVjYLtfnTPlTg09rViCGByK7IlCKgql+jqlMiKO9hPtKry/mJ4KHe1ca2wiH8tjyZi rovV5W1qLoXynRm9FveDA38efOUnPnJ9dKnvQDnkksSzerFb2Ek6QKmijmdBalS0x0R9 9GzPMSVLz0kLhshbDTOeTbggNB2T75Z+pnO3IQbdvmdbumKrSCAOnzF7gfkvCrC9zsZX 3x+g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=VamSeBNb0W35YTaE5KKNIilAYQcTaYH0JIGT88S7LVU=; b=jbYRrjmLStT2+Rs4M9x9byoNx4hf8LsLriyG2wvjvAOhITDWs8BZVCVPUQB9m+FreT AUGo7OuFQKlZItpTZObApyhY/4qaJ/6VsYM2qYJJWqNMYqKO0TTA3vg0rTRIXslFRVEN lr3s62HvNLbJciOYP9hFUCc3TLyBKNTKpiM9U+1hfhaFokuAUubVEgBkjRIcBCfwMaIA qHSLPhCU0ZDwFRRJHck6Rr7GnBPw2wBMmkXnYe6TV1Q+395zalqdfUD2w53rdSVUfsKU JhxOHRx4zpewnXsCU1UlD1fle4vaSuPQgBhbGsUSrFJgFhUgtdaOu45b8hgNIgTXq515 S52Q== X-Gm-Message-State: APjAAAUV5SCG7VvdKACPH90pL+mowS4rXmV6+mHFcxWtfLDPaCh8jezF 5q49i8DlDuA25SCHOJEze4pF16d9 X-Google-Smtp-Source: APXvYqwKapHrfvD9zEOM0bF3NslhKK+w/LqCR67Y4N46elVy09iw3Y9Tf8OT2pQqLTSwycC32rZ/yg== X-Received: by 2002:a1c:cc06:: with SMTP id h6mr11140075wmb.118.1576781493163; Thu, 19 Dec 2019 10:51:33 -0800 (PST) Received: from x1w.redhat.com (34.red-83-42-66.dynamicip.rima-tde.net. [83.42.66.34]) by smtp.gmail.com with ESMTPSA id b67sm7435494wmc.38.2019.12.19.10.51.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 19 Dec 2019 10:51:32 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org, Niek Linnenbank Cc: Peter Maydell , Beniamino Galvani , qemu-arm@nongnu.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH 03/13] hw/timer/allwinner: Remove unused definitions Date: Thu, 19 Dec 2019 19:51:17 +0100 Message-Id: <20191219185127.24388-4-f4bug@amsat.org> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20191219185127.24388-1-f4bug@amsat.org> References: <20191219185127.24388-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 8bit X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::336 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 19 Dec 2019 18:51:39 -0000 Keeping unused definition is rather confusing when reviewing. Remove them. Signed-off-by: Philippe Mathieu-Daudé --- include/hw/timer/allwinner-a10-pit.h | 2 -- 1 file changed, 2 deletions(-) diff --git a/include/hw/timer/allwinner-a10-pit.h b/include/hw/timer/allwinner-a10-pit.h index 54c40c7db6..e4a644add9 100644 --- a/include/hw/timer/allwinner-a10-pit.h +++ b/include/hw/timer/allwinner-a10-pit.h @@ -10,8 +10,6 @@ #define AW_PIT_TIMER_MAX 6 #define AW_A10_PIT_TIMER_NR 6 -#define AW_A10_PIT_TIMER_IRQ 0x1 -#define AW_A10_PIT_WDOG_IRQ 0x100 #define AW_A10_PIT_TIMER_IRQ_EN 0 #define AW_A10_PIT_TIMER_IRQ_ST 0x4 -- 2.21.0 From MAILER-DAEMON Thu Dec 19 13:51:42 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1ii0ti-00077a-0S for mharc-qemu-arm@gnu.org; Thu, 19 Dec 2019 13:51:42 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:39486) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ii0te-00071F-77 for qemu-arm@nongnu.org; Thu, 19 Dec 2019 13:51:39 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ii0tc-0007hI-Ob for qemu-arm@nongnu.org; Thu, 19 Dec 2019 13:51:37 -0500 Received: from mail-wm1-x332.google.com ([2a00:1450:4864:20::332]:39782) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ii0tX-00077M-MV; Thu, 19 Dec 2019 13:51:31 -0500 Received: by mail-wm1-x332.google.com with SMTP id 20so6637350wmj.4; Thu, 19 Dec 2019 10:51:31 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=kawbqCEjPPYKCsVnRVsa55n98nVaL/1o+fmH2TsyLNE=; b=hlmMNCLNwX+RKju0XCfr9FBOQbehZMq5UQz4OtXjSkx2kDsWMOmkiJVcAocgiUOMCq dk429h3d4vhPgkXjx+0WXlbk0ZwbwtqpfTaGGhU2wGDQyzUcX0Db5zmGi9nlpIKP8n3Z xO0qpuuMEp0etQ5PzaxG8tWIcGc6UhfqfO97S5MPVIjSG4Qpdp9enG08SgnGx62SFJWH uvzr3jee9R8X3QgiZaldjIdQivqTRrnekv/dryvXYfLjD5Mg0Fn2dyzKrGu5tit5unHX o1TqASqFhTZvwXviwl5GKkr03feprp2aHRUlDiy/KTkHVpvxKrnC2qIizd9qvxfYoS2v 9NyQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :mime-version:content-transfer-encoding; bh=kawbqCEjPPYKCsVnRVsa55n98nVaL/1o+fmH2TsyLNE=; b=YivAMyzbDWZvJ2ZTv6FOMqXVr0ndZqJwoW14LVWBjLoOLRi1ouv2emYAzS0deycGsc jWsm+uixisoBGsmQnLOdq5H/vVcOzXXmg7yNOa88g5s7beLr+R5w1xmeha/66u8ut97x fOCN8+UIWW08Km7HymLMM1tOGvgdvCqp1JzOFedgGQsx4B9wEdjH4j8Pc2UmKQZmsblu PgmXWIl857pm4eaKGwnuYJfMr5xs2rDpqRPITWA3FbSyBgbLt2wCJShpIoMgpEBpowmx 2J5yAXYW3PtA5SHCeH4ubhK8mPY9v5WQCM6yth4qYbdmrwq5LbmY3PImlX1ytEEHYMSx bpRA== X-Gm-Message-State: APjAAAWT23b2QUZUyioLJs4ICOAGtQ7pCR/4EdEC+hSH4puGitcnSIYI VsFtdwFglSUeyULfsP/OAGmvQc8h X-Google-Smtp-Source: APXvYqz4Ia2RBAjPZFSasg71WzEA+swTRfYLvHFWg23ljEMzGUeSrng+dCuiQyyrZTCYkU3rdmzt7Q== X-Received: by 2002:a1c:486:: with SMTP id 128mr12132694wme.163.1576781489342; Thu, 19 Dec 2019 10:51:29 -0800 (PST) Received: from x1w.redhat.com (34.red-83-42-66.dynamicip.rima-tde.net. [83.42.66.34]) by smtp.gmail.com with ESMTPSA id b67sm7435494wmc.38.2019.12.19.10.51.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 19 Dec 2019 10:51:28 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org, Niek Linnenbank Cc: Peter Maydell , Beniamino Galvani , qemu-arm@nongnu.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [RFC PATCH 00/13] hw/timer/allwinner: Make it reusable Date: Thu, 19 Dec 2019 19:51:14 +0100 Message-Id: <20191219185127.24388-1-f4bug@amsat.org> X-Mailer: git-send-email 2.21.0 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 8bit X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::332 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 19 Dec 2019 18:51:39 -0000 Hi, Niek added the H3 SoC in [1] and noticed in [2] the timer controller is very similar (less timers, watchdog register placed at different address). On 12/18/19 9:14 PM, Niek Linnenbank wrote: > Actually, I copied the timer support code from the existing cubieboard.c > that has > the Allwinner A10, so potentially the same problem is there. > > While looking more closer at this part, I now also discovered that the > timer module from the Allwinner H3 is > mostly a stripped down version of the timer module in the Allwinner A10: > > Allwinner A10, 10.2 Timer Register List, page 85: > https://linux-sunxi.org/images/1/1e/Allwinner_A10_User_manual_V1.5.pdf > > The A10 version has six timers, where the H3 has only two. That should > be fine I would say, the guest would simply > use those available on H3 and ignore the rest. There is however one > conflicting difference: the WDOG0 registers in the Allwinner H3 start > at a different offset and are also different. The current A10 timer does > not currently implement the watchdog part. [...] > So in my opinion its a bit of a trade off here: we can keep it like this > and re-use the A10 timer for now, and perhaps > attempt to generalize that module for proper use in both SoCs. Or we can > introduce a new H3 specific timer module. > What do you think? As an answer to his question, this series is to help him to reuse the A10 timer controller instead of adding a new model to the codebase. [1] https://www.mail-archive.com/qemu-devel@nongnu.org/msg665532.html [2] https://www.mail-archive.com/qemu-devel@nongnu.org/msg666304.html Philippe Mathieu-Daudé (13): hw/timer/allwinner: Use the AW_A10_PIT_TIMER_NR definition hw/timer/allwinner: Add AW_PIT_TIMER_MAX definition hw/timer/allwinner: Remove unused definitions hw/timer/allwinner: Move definitions from header to source hw/timer/allwinner: Rename the ptimer field hw/timer/allwinner: Rename 'timer_context' as 'timer' hw/timer/allwinner: Move timer specific fields into AwA10TimerContext hw/timer/allwinner: Add a timer_count field hw/timer/allwinner: Rename AwA10TimerContext as AllwinnerTmrState hw/timer/allwinner: Rename AwA10PITState as AllwinnerTmrCtrlState hw/timer/allwinner: Introduce TYPE_AW_COMMON_PIT abstract device hw/timer/allwinner: Rename AW_A10_PIT() as AW_TIMER_CTRL() hw/timer/allwinner: Rename functions not specific to the A10 SoC include/hw/arm/allwinner-a10.h | 2 +- include/hw/timer/allwinner-a10-pit.h | 54 ++---- hw/timer/allwinner-a10-pit.c | 271 +++++++++++++++++---------- 3 files changed, 192 insertions(+), 135 deletions(-) -- 2.21.0 From MAILER-DAEMON Thu Dec 19 13:51:43 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1ii0tj-00079c-76 for mharc-qemu-arm@gnu.org; Thu, 19 Dec 2019 13:51:43 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:39703) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ii0tg-00074E-0N for qemu-arm@nongnu.org; Thu, 19 Dec 2019 13:51:41 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ii0te-0007rj-OJ for qemu-arm@nongnu.org; Thu, 19 Dec 2019 13:51:39 -0500 Received: from mail-wm1-x343.google.com ([2a00:1450:4864:20::343]:53867) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ii0tb-0007Xp-PD; Thu, 19 Dec 2019 13:51:35 -0500 Received: by mail-wm1-x343.google.com with SMTP id m24so6507350wmc.3; Thu, 19 Dec 2019 10:51:35 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=jIg+33KeWZZoVU4KTC1Qs/cBS+U2tDHwXFCUA5+HzbM=; b=DOOoXp7wOhfRVuo831S05oCEi09rbGM+mhvGwoAW9kVI0AW+Oi4238dlMdG1HOQLPi fv1sR8UjxVUOg9aff+Rn+lxEEBAqc4IWv8QwbdkXnkjj1xZMT8iYSKrthF2l7zzOTr+f kSuwqJcEKaudzWgZISsd9EjkoaD+uKrDdGo54li47kwOPP/+gvfVHoNifBXg9VmFaeUm wIqWtyMYSnb/S/bYWWX3fNHNxI1dnDqTD5KQhO61QRvJOZmWmqYvUwrVYoBqSmnmQ/tw Ltilcsgh3Db1J+pjsZg4GO1nShWstMrzDDMz/AbdPwCOLkQgcINIA0f1COTK23QyDxzg mwow== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=jIg+33KeWZZoVU4KTC1Qs/cBS+U2tDHwXFCUA5+HzbM=; b=g6rH1vb0qUz2V/LctLMY0bRjoukLHEKNrHaJ5/wLhWJ8MuOxvwZ+jhR2yDn3FBFFf9 jZgEDXd69zznrvo4Z8Flrx0xTOhh/dftH8xmWMes3uVprBFqi3AWIz/dMOqpPaqgnax3 +zo4yTfyv9CjtrPS+4ZHBk06kcdo8UPK58ugH2GaEObtn6SaupRLMHthjVKm/h0iS4T7 Eqv2a+6L5J1zM1fjK/bl+kUhWGl2QszMZkr6CQqnQiCS6jU+tzUuX+rm+Tv15uDOhruy dORsHThzVzmBkeA1FjVAV1pgJH5Urbfjat7HYUWGJtnABkXff61myXZj8TsWBDa3wjZr kdHw== X-Gm-Message-State: APjAAAXXO31ZbwhRw2O7PQ2k958YCFObxARqlVSTJdPEnGkvH/cKntAh 22H4gY1KGRjy466RmVvvKAWc3pSm X-Google-Smtp-Source: APXvYqx4/zuBzYIXCe0BcvOfXwN1MN94M8leEwqrgzY3pRbmv0q7FlOQyPpkYLKO5pfpunluWXKUUA== X-Received: by 2002:a1c:4b09:: with SMTP id y9mr12136089wma.103.1576781494368; Thu, 19 Dec 2019 10:51:34 -0800 (PST) Received: from x1w.redhat.com (34.red-83-42-66.dynamicip.rima-tde.net. [83.42.66.34]) by smtp.gmail.com with ESMTPSA id b67sm7435494wmc.38.2019.12.19.10.51.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 19 Dec 2019 10:51:33 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org, Niek Linnenbank Cc: Peter Maydell , Beniamino Galvani , qemu-arm@nongnu.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH 04/13] hw/timer/allwinner: Move definitions from header to source Date: Thu, 19 Dec 2019 19:51:18 +0100 Message-Id: <20191219185127.24388-5-f4bug@amsat.org> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20191219185127.24388-1-f4bug@amsat.org> References: <20191219185127.24388-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 8bit X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::343 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 19 Dec 2019 18:51:41 -0000 These definitions are only used in the implementation, thus don't need to be exported. Move them in the source file. Signed-off-by: Philippe Mathieu-Daudé --- include/hw/timer/allwinner-a10-pit.h | 28 -------------------------- hw/timer/allwinner-a10-pit.c | 30 ++++++++++++++++++++++++++++ 2 files changed, 30 insertions(+), 28 deletions(-) diff --git a/include/hw/timer/allwinner-a10-pit.h b/include/hw/timer/allwinner-a10-pit.h index e4a644add9..c28ee5ca47 100644 --- a/include/hw/timer/allwinner-a10-pit.h +++ b/include/hw/timer/allwinner-a10-pit.h @@ -5,37 +5,9 @@ #include "hw/sysbus.h" #define TYPE_AW_A10_PIT "allwinner-A10-timer" -#define AW_A10_PIT(obj) OBJECT_CHECK(AwA10PITState, (obj), TYPE_AW_A10_PIT) #define AW_PIT_TIMER_MAX 6 -#define AW_A10_PIT_TIMER_NR 6 - -#define AW_A10_PIT_TIMER_IRQ_EN 0 -#define AW_A10_PIT_TIMER_IRQ_ST 0x4 - -#define AW_A10_PIT_TIMER_CONTROL 0x0 -#define AW_A10_PIT_TIMER_EN 0x1 -#define AW_A10_PIT_TIMER_RELOAD 0x2 -#define AW_A10_PIT_TIMER_MODE 0x80 - -#define AW_A10_PIT_TIMER_INTERVAL 0x4 -#define AW_A10_PIT_TIMER_COUNT 0x8 -#define AW_A10_PIT_WDOG_CONTROL 0x90 -#define AW_A10_PIT_WDOG_MODE 0x94 - -#define AW_A10_PIT_COUNT_CTL 0xa0 -#define AW_A10_PIT_COUNT_RL_EN 0x2 -#define AW_A10_PIT_COUNT_CLR_EN 0x1 -#define AW_A10_PIT_COUNT_LO 0xa4 -#define AW_A10_PIT_COUNT_HI 0xa8 - -#define AW_A10_PIT_TIMER_BASE 0x10 -#define AW_A10_PIT_TIMER_BASE_END \ - (AW_A10_PIT_TIMER_BASE * AW_A10_PIT_TIMER_NR + AW_A10_PIT_TIMER_COUNT) - -#define AW_A10_PIT_DEFAULT_CLOCK 0x4 - typedef struct AwA10PITState AwA10PITState; typedef struct AwA10TimerContext { diff --git a/hw/timer/allwinner-a10-pit.c b/hw/timer/allwinner-a10-pit.c index b31a0bcd43..00f7cc492d 100644 --- a/hw/timer/allwinner-a10-pit.c +++ b/hw/timer/allwinner-a10-pit.c @@ -24,6 +24,36 @@ #include "qemu/log.h" #include "qemu/module.h" +#define AW_A10_PIT_TIMER_NR 6 + +#define AW_A10_PIT_TIMER_IRQ_EN 0 +#define AW_A10_PIT_TIMER_IRQ_ST 0x4 + +#define AW_A10_PIT_TIMER_CONTROL 0x0 +#define AW_A10_PIT_TIMER_EN 0x1 +#define AW_A10_PIT_TIMER_RELOAD 0x2 +#define AW_A10_PIT_TIMER_MODE 0x80 + +#define AW_A10_PIT_TIMER_INTERVAL 0x4 +#define AW_A10_PIT_TIMER_COUNT 0x8 +#define AW_A10_PIT_WDOG_CONTROL 0x90 +#define AW_A10_PIT_WDOG_MODE 0x94 + +#define AW_A10_PIT_COUNT_CTL 0xa0 +#define AW_A10_PIT_COUNT_RL_EN 0x2 +#define AW_A10_PIT_COUNT_CLR_EN 0x1 +#define AW_A10_PIT_COUNT_LO 0xa4 +#define AW_A10_PIT_COUNT_HI 0xa8 + +#define AW_A10_PIT_TIMER_BASE 0x10 +#define AW_A10_PIT_TIMER_BASE_END \ + (AW_A10_PIT_TIMER_BASE * AW_A10_PIT_TIMER_NR + AW_A10_PIT_TIMER_COUNT) + +#define AW_A10_PIT_DEFAULT_CLOCK 0x4 + +#define AW_A10_PIT(obj) \ + OBJECT_CHECK(AwA10PITState, (obj), TYPE_AW_A10_PIT) + static void a10_pit_update_irq(AwA10PITState *s) { int i; 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[83.42.66.34]) by smtp.gmail.com with ESMTPSA id b67sm7435494wmc.38.2019.12.19.10.51.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 19 Dec 2019 10:51:31 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org, Niek Linnenbank Cc: Peter Maydell , Beniamino Galvani , qemu-arm@nongnu.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH 02/13] hw/timer/allwinner: Add AW_PIT_TIMER_MAX definition Date: Thu, 19 Dec 2019 19:51:16 +0100 Message-Id: <20191219185127.24388-3-f4bug@amsat.org> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20191219185127.24388-1-f4bug@amsat.org> References: <20191219185127.24388-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 8bit X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::341 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 19 Dec 2019 18:51:41 -0000 This controller is able to use up to 6 timers. Later we will reuse part of it to model other similar controllers but with less timers. To simplify the VMSTATE, we'll keep a max of 6 timers. Add a definition for that value. Signed-off-by: Philippe Mathieu-Daudé --- include/hw/timer/allwinner-a10-pit.h | 14 ++++++++------ hw/timer/allwinner-a10-pit.c | 8 ++++---- 2 files changed, 12 insertions(+), 10 deletions(-) diff --git a/include/hw/timer/allwinner-a10-pit.h b/include/hw/timer/allwinner-a10-pit.h index 6aceda81ee..54c40c7db6 100644 --- a/include/hw/timer/allwinner-a10-pit.h +++ b/include/hw/timer/allwinner-a10-pit.h @@ -7,6 +7,8 @@ #define TYPE_AW_A10_PIT "allwinner-A10-timer" #define AW_A10_PIT(obj) OBJECT_CHECK(AwA10PITState, (obj), TYPE_AW_A10_PIT) +#define AW_PIT_TIMER_MAX 6 + #define AW_A10_PIT_TIMER_NR 6 #define AW_A10_PIT_TIMER_IRQ 0x1 #define AW_A10_PIT_WDOG_IRQ 0x100 @@ -47,17 +49,17 @@ struct AwA10PITState { /*< private >*/ SysBusDevice parent_obj; /*< public >*/ - qemu_irq irq[AW_A10_PIT_TIMER_NR]; - ptimer_state * timer[AW_A10_PIT_TIMER_NR]; - AwA10TimerContext timer_context[AW_A10_PIT_TIMER_NR]; + qemu_irq irq[AW_PIT_TIMER_MAX]; + ptimer_state * timer[AW_PIT_TIMER_MAX]; + AwA10TimerContext timer_context[AW_PIT_TIMER_MAX]; MemoryRegion iomem; uint32_t clk_freq[4]; uint32_t irq_enable; uint32_t irq_status; - uint32_t control[AW_A10_PIT_TIMER_NR]; - uint32_t interval[AW_A10_PIT_TIMER_NR]; - uint32_t count[AW_A10_PIT_TIMER_NR]; + uint32_t control[AW_PIT_TIMER_MAX]; + uint32_t interval[AW_PIT_TIMER_MAX]; + uint32_t count[AW_PIT_TIMER_MAX]; uint32_t watch_dog_mode; uint32_t watch_dog_control; uint32_t count_lo; diff --git a/hw/timer/allwinner-a10-pit.c b/hw/timer/allwinner-a10-pit.c index 117e5c7bf8..b31a0bcd43 100644 --- a/hw/timer/allwinner-a10-pit.c +++ b/hw/timer/allwinner-a10-pit.c @@ -203,15 +203,15 @@ static const VMStateDescription vmstate_a10_pit = { .fields = (VMStateField[]) { VMSTATE_UINT32(irq_enable, AwA10PITState), VMSTATE_UINT32(irq_status, AwA10PITState), - VMSTATE_UINT32_ARRAY(control, AwA10PITState, AW_A10_PIT_TIMER_NR), - VMSTATE_UINT32_ARRAY(interval, AwA10PITState, AW_A10_PIT_TIMER_NR), - VMSTATE_UINT32_ARRAY(count, AwA10PITState, AW_A10_PIT_TIMER_NR), + VMSTATE_UINT32_ARRAY(control, AwA10PITState, AW_PIT_TIMER_MAX), + VMSTATE_UINT32_ARRAY(interval, AwA10PITState, AW_PIT_TIMER_MAX), + VMSTATE_UINT32_ARRAY(count, AwA10PITState, AW_PIT_TIMER_MAX), VMSTATE_UINT32(watch_dog_mode, AwA10PITState), VMSTATE_UINT32(watch_dog_control, AwA10PITState), VMSTATE_UINT32(count_lo, AwA10PITState), VMSTATE_UINT32(count_hi, AwA10PITState), VMSTATE_UINT32(count_ctl, AwA10PITState), - VMSTATE_PTIMER_ARRAY(timer, AwA10PITState, AW_A10_PIT_TIMER_NR), + VMSTATE_PTIMER_ARRAY(timer, AwA10PITState, AW_PIT_TIMER_MAX), VMSTATE_END_OF_LIST() } }; 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[83.42.66.34]) by smtp.gmail.com with ESMTPSA id b67sm7435494wmc.38.2019.12.19.10.51.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 19 Dec 2019 10:51:36 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org, Niek Linnenbank Cc: Peter Maydell , Beniamino Galvani , qemu-arm@nongnu.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [RFC PATCH 06/13] hw/timer/allwinner: Rename 'timer_context' as 'timer' Date: Thu, 19 Dec 2019 19:51:20 +0100 Message-Id: <20191219185127.24388-7-f4bug@amsat.org> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20191219185127.24388-1-f4bug@amsat.org> References: <20191219185127.24388-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 8bit X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::342 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 19 Dec 2019 18:51:44 -0000 The previous 'timer' field has been renamed as 'ptimer'. The 'timer_context' can now be simplified as 'timer'. Signed-off-by: Philippe Mathieu-Daudé --- include/hw/timer/allwinner-a10-pit.h | 2 +- hw/timer/allwinner-a10-pit.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/include/hw/timer/allwinner-a10-pit.h b/include/hw/timer/allwinner-a10-pit.h index a60b9f3031..b5ac6898fa 100644 --- a/include/hw/timer/allwinner-a10-pit.h +++ b/include/hw/timer/allwinner-a10-pit.h @@ -21,7 +21,7 @@ struct AwA10PITState { /*< public >*/ qemu_irq irq[AW_PIT_TIMER_MAX]; ptimer_state * ptimer[AW_PIT_TIMER_MAX]; - AwA10TimerContext timer_context[AW_PIT_TIMER_MAX]; + AwA10TimerContext timer[AW_PIT_TIMER_MAX]; MemoryRegion iomem; uint32_t clk_freq[4]; diff --git a/hw/timer/allwinner-a10-pit.c b/hw/timer/allwinner-a10-pit.c index effdf91344..44e6eee3a8 100644 --- a/hw/timer/allwinner-a10-pit.c +++ b/hw/timer/allwinner-a10-pit.c @@ -301,7 +301,7 @@ static void a10_pit_init(Object *obj) sysbus_init_mmio(sbd, &s->iomem); for (i = 0; i < AW_A10_PIT_TIMER_NR; i++) { - AwA10TimerContext *tc = &s->timer_context[i]; + AwA10TimerContext *tc = &s->timer[i]; tc->container = s; tc->index = i; -- 2.21.0 From MAILER-DAEMON Thu Dec 19 13:51:45 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1ii0tl-0007Dk-Jy for mharc-qemu-arm@gnu.org; Thu, 19 Dec 2019 13:51:45 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:39889) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ii0th-00077F-La for qemu-arm@nongnu.org; Thu, 19 Dec 2019 13:51:42 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ii0tg-00081U-Bc for qemu-arm@nongnu.org; Thu, 19 Dec 2019 13:51:41 -0500 Received: from mail-wm1-x344.google.com ([2a00:1450:4864:20::344]:40531) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ii0td-0007fY-4k; Thu, 19 Dec 2019 13:51:37 -0500 Received: by mail-wm1-x344.google.com with SMTP id t14so6738813wmi.5; Thu, 19 Dec 2019 10:51:37 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=JsHtfge5h+5q2LZhmNIpaj2lzwktX3gFRpdUNeSwNQI=; b=AxqVhc0AEZh1OEee/AvnEa+KucuM+1JvChO4bzf1IaK0NMw5Oluazg5ZXm+As+ki/r GRBOh8OwvUfomKIztwEauMgbCIV4GWs/nXTVh1IYG63uzuLGiMLOKvhgyBdRD6a9ExTr BW/OAqhnZH6rIxNJGzCcVdZCBUDr7ekksShf4lG3rRy7n71M5hcdfnejebT3xGi48flk //ynxSxEVIVoWMUg2EwESTsawVVVZnADKFQpOyoHEfqQZaz6SRYEk9gQzLT9lTBDGi+7 rMcUb/Ml0z4XNL4H0cjurPaDrolA0OvTuKPF1n2kR/YB27oafAv4FVdpcN8xMzCDTOM0 UE8w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=JsHtfge5h+5q2LZhmNIpaj2lzwktX3gFRpdUNeSwNQI=; b=gIcVtE2Xe6O/DDYyGgS0mPT7HKUlVO0s/hToe50722XWi08KOO+1DxMVQXYHPklFn0 eRUe7k+2ssUKr7NuEV1WypUi/gbZUTpyNXAFJDgUB4lqaRaT5MrJvnsS3rVOFY/skHJt q1lFipGQR5yc+nWPkLHn+CPxKONsD0bhbsSyggDJgH9U/oVPUUNHxlczPHPwh2AT2p8q /c86qGUDgr5bZb6RWFW+eTqoY0L9zy+FmNjQ+8cjGi2qQGbOJZLDe7HCLe2/08xQRF29 coI7D2rs6A1HIF4Zsi742n7UqDk6km4TO4kZbdDOo0fDmKWuRKq06yWlybA9GsSvO2Zj fG9w== X-Gm-Message-State: APjAAAWvehfFsVpY0iX08Rq/++yKoUXQ6uWvYOnwoTpBA3z4kkwmxn+Y GYv4Q5GlcTFZA9b2y3CQUIRNp0UG X-Google-Smtp-Source: APXvYqwWRKu9WQ9vVRJb36FShcdSAo7xQFL8A2h3uVIibUKhG9vH+y7w0fPBXskoRo9posLcaJ2sbw== X-Received: by 2002:a05:600c:54c:: with SMTP id k12mr11859443wmc.124.1576781495869; Thu, 19 Dec 2019 10:51:35 -0800 (PST) Received: from x1w.redhat.com (34.red-83-42-66.dynamicip.rima-tde.net. [83.42.66.34]) by smtp.gmail.com with ESMTPSA id b67sm7435494wmc.38.2019.12.19.10.51.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 19 Dec 2019 10:51:35 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org, Niek Linnenbank Cc: Peter Maydell , Beniamino Galvani , qemu-arm@nongnu.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [RFC PATCH 05/13] hw/timer/allwinner: Rename the ptimer field Date: Thu, 19 Dec 2019 19:51:19 +0100 Message-Id: <20191219185127.24388-6-f4bug@amsat.org> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20191219185127.24388-1-f4bug@amsat.org> References: <20191219185127.24388-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 8bit X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::344 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 19 Dec 2019 18:51:44 -0000 We will later use the 'timer' field name to access all the timer related fields. The name is already use, we need to rename first. 'ptimer' is a good name. Signed-off-by: Philippe Mathieu-Daudé --- include/hw/timer/allwinner-a10-pit.h | 2 +- hw/timer/allwinner-a10-pit.c | 34 ++++++++++++++-------------- 2 files changed, 18 insertions(+), 18 deletions(-) diff --git a/include/hw/timer/allwinner-a10-pit.h b/include/hw/timer/allwinner-a10-pit.h index c28ee5ca47..a60b9f3031 100644 --- a/include/hw/timer/allwinner-a10-pit.h +++ b/include/hw/timer/allwinner-a10-pit.h @@ -20,7 +20,7 @@ struct AwA10PITState { SysBusDevice parent_obj; /*< public >*/ qemu_irq irq[AW_PIT_TIMER_MAX]; - ptimer_state * timer[AW_PIT_TIMER_MAX]; + ptimer_state * ptimer[AW_PIT_TIMER_MAX]; AwA10TimerContext timer_context[AW_PIT_TIMER_MAX]; MemoryRegion iomem; uint32_t clk_freq[4]; diff --git a/hw/timer/allwinner-a10-pit.c b/hw/timer/allwinner-a10-pit.c index 00f7cc492d..effdf91344 100644 --- a/hw/timer/allwinner-a10-pit.c +++ b/hw/timer/allwinner-a10-pit.c @@ -83,7 +83,7 @@ static uint64_t a10_pit_read(void *opaque, hwaddr offset, unsigned size) case AW_A10_PIT_TIMER_INTERVAL: return s->interval[index]; case AW_A10_PIT_TIMER_COUNT: - s->count[index] = ptimer_get_count(s->timer[index]); + s->count[index] = ptimer_get_count(s->ptimer[index]); return s->count[index]; default: qemu_log_mask(LOG_GUEST_ERROR, @@ -109,7 +109,7 @@ static uint64_t a10_pit_read(void *opaque, hwaddr offset, unsigned size) return 0; } -/* Must be called inside a ptimer transaction block for s->timer[index] */ +/* Must be called inside a ptimer transaction block for s->ptimer[index] */ static void a10_pit_set_freq(AwA10PITState *s, int index) { uint32_t prescaler, source, source_freq; @@ -119,7 +119,7 @@ static void a10_pit_set_freq(AwA10PITState *s, int index) source_freq = s->clk_freq[source]; if (source_freq) { - ptimer_set_freq(s->timer[index], source_freq / prescaler); + ptimer_set_freq(s->ptimer[index], source_freq / prescaler); } else { qemu_log_mask(LOG_GUEST_ERROR, "%s: Invalid clock source %u\n", __func__, source); @@ -148,27 +148,27 @@ static void a10_pit_write(void *opaque, hwaddr offset, uint64_t value, switch (offset & 0x0f) { case AW_A10_PIT_TIMER_CONTROL: s->control[index] = value; - ptimer_transaction_begin(s->timer[index]); + ptimer_transaction_begin(s->ptimer[index]); a10_pit_set_freq(s, index); if (s->control[index] & AW_A10_PIT_TIMER_RELOAD) { - ptimer_set_count(s->timer[index], s->interval[index]); + ptimer_set_count(s->ptimer[index], s->interval[index]); } if (s->control[index] & AW_A10_PIT_TIMER_EN) { int oneshot = 0; if (s->control[index] & AW_A10_PIT_TIMER_MODE) { oneshot = 1; } - ptimer_run(s->timer[index], oneshot); + ptimer_run(s->ptimer[index], oneshot); } else { - ptimer_stop(s->timer[index]); + ptimer_stop(s->ptimer[index]); } - ptimer_transaction_commit(s->timer[index]); + ptimer_transaction_commit(s->ptimer[index]); break; case AW_A10_PIT_TIMER_INTERVAL: s->interval[index] = value; - ptimer_transaction_begin(s->timer[index]); - ptimer_set_limit(s->timer[index], s->interval[index], 1); - ptimer_transaction_commit(s->timer[index]); + ptimer_transaction_begin(s->ptimer[index]); + ptimer_set_limit(s->ptimer[index], s->interval[index], 1); + ptimer_transaction_commit(s->ptimer[index]); break; case AW_A10_PIT_TIMER_COUNT: s->count[index] = value; @@ -241,7 +241,7 @@ static const VMStateDescription vmstate_a10_pit = { VMSTATE_UINT32(count_lo, AwA10PITState), VMSTATE_UINT32(count_hi, AwA10PITState), VMSTATE_UINT32(count_ctl, AwA10PITState), - VMSTATE_PTIMER_ARRAY(timer, AwA10PITState, AW_PIT_TIMER_MAX), + VMSTATE_PTIMER_ARRAY(ptimer, AwA10PITState, AW_PIT_TIMER_MAX), VMSTATE_END_OF_LIST() } }; @@ -259,10 +259,10 @@ static void a10_pit_reset(DeviceState *dev) s->control[i] = AW_A10_PIT_DEFAULT_CLOCK; s->interval[i] = 0; s->count[i] = 0; - ptimer_transaction_begin(s->timer[i]); - ptimer_stop(s->timer[i]); + ptimer_transaction_begin(s->ptimer[i]); + ptimer_stop(s->ptimer[i]); a10_pit_set_freq(s, i); - ptimer_transaction_commit(s->timer[i]); + ptimer_transaction_commit(s->ptimer[i]); } s->watch_dog_mode = 0; s->watch_dog_control = 0; @@ -280,7 +280,7 @@ static void a10_pit_timer_cb(void *opaque) if (s->control[i] & AW_A10_PIT_TIMER_EN) { s->irq_status |= 1 << i; if (s->control[i] & AW_A10_PIT_TIMER_MODE) { - ptimer_stop(s->timer[i]); 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[83.42.66.34]) by smtp.gmail.com with ESMTPSA id b67sm7435494wmc.38.2019.12.19.10.51.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 19 Dec 2019 10:51:38 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org, Niek Linnenbank Cc: Peter Maydell , Beniamino Galvani , qemu-arm@nongnu.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [RFC PATCH 08/13] hw/timer/allwinner: Add a timer_count field Date: Thu, 19 Dec 2019 19:51:22 +0100 Message-Id: <20191219185127.24388-9-f4bug@amsat.org> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20191219185127.24388-1-f4bug@amsat.org> References: <20191219185127.24388-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 8bit X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::444 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 19 Dec 2019 18:51:46 -0000 To be able to support controllers with less than 6 timers, we need a field to be able to iterate over the different count. Signed-off-by: Philippe Mathieu-Daudé --- include/hw/timer/allwinner-a10-pit.h | 1 + hw/timer/allwinner-a10-pit.c | 10 ++++++---- 2 files changed, 7 insertions(+), 4 deletions(-) diff --git a/include/hw/timer/allwinner-a10-pit.h b/include/hw/timer/allwinner-a10-pit.h index e0f864a954..8c64c33f01 100644 --- a/include/hw/timer/allwinner-a10-pit.h +++ b/include/hw/timer/allwinner-a10-pit.h @@ -24,6 +24,7 @@ struct AwA10PITState { /*< private >*/ SysBusDevice parent_obj; /*< public >*/ + size_t timer_count; AwA10TimerContext timer[AW_PIT_TIMER_MAX]; MemoryRegion iomem; uint32_t clk_freq[4]; diff --git a/hw/timer/allwinner-a10-pit.c b/hw/timer/allwinner-a10-pit.c index ea92fdda32..3f47588703 100644 --- a/hw/timer/allwinner-a10-pit.c +++ b/hw/timer/allwinner-a10-pit.c @@ -58,7 +58,7 @@ static void a10_pit_update_irq(AwA10PITState *s) { int i; - for (i = 0; i < AW_A10_PIT_TIMER_NR; i++) { + for (i = 0; i < s->timer_count; i++) { qemu_set_irq(s->timer[i].irq, !!(s->irq_status & s->irq_enable & (1 << i))); } @@ -271,7 +271,7 @@ static void a10_pit_reset(DeviceState *dev) s->irq_status = 0; a10_pit_update_irq(s); - for (i = 0; i < AW_A10_PIT_TIMER_NR; i++) { + for (i = 0; i < s->timer_count; i++) { s->timer[i].control = AW_A10_PIT_DEFAULT_CLOCK; s->timer[i].interval = 0; s->timer[i].count = 0; @@ -309,14 +309,16 @@ static void a10_pit_init(Object *obj) SysBusDevice *sbd = SYS_BUS_DEVICE(obj); uint8_t i; - for (i = 0; i < AW_A10_PIT_TIMER_NR; i++) { + s->timer_count = AW_A10_PIT_TIMER_NR; + + for (i = 0; i < s->timer_count; i++) { sysbus_init_irq(sbd, &s->timer[i].irq); } memory_region_init_io(&s->iomem, OBJECT(s), &a10_pit_ops, s, TYPE_AW_A10_PIT, 0x400); sysbus_init_mmio(sbd, &s->iomem); - for (i = 0; i < AW_A10_PIT_TIMER_NR; i++) { + for (i = 0; i < s->timer_count; i++) { AwA10TimerContext *tc = &s->timer[i]; tc->container = s; -- 2.21.0 From MAILER-DAEMON Thu Dec 19 13:51:49 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1ii0tp-0007Ln-17 for mharc-qemu-arm@gnu.org; Thu, 19 Dec 2019 13:51:49 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:40373) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ii0tm-0007GQ-8e for qemu-arm@nongnu.org; Thu, 19 Dec 2019 13:51:47 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ii0tk-0008Ri-SR for qemu-arm@nongnu.org; Thu, 19 Dec 2019 13:51:45 -0500 Received: from mail-wr1-x442.google.com ([2a00:1450:4864:20::442]:45868) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ii0th-00085U-R3; Thu, 19 Dec 2019 13:51:42 -0500 Received: by mail-wr1-x442.google.com with SMTP id j42so7020432wrj.12; Thu, 19 Dec 2019 10:51:41 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=xqTqck0MunQzlvW3fvG1Eh5JVsO+310wsc6ir4XWOg8=; b=DbT48iy/7ZvB5pfzW11tJNj8wYlfwPabB00bOKJ0VQCM46ByzLZ4a49Xm0UmmMz/Gk BGzwYIr+W3WolPSvYe9MMm2oHybcm/jmi0jszdd7i557I3GQ8/ltFe9RruaamPmLfoT4 4K9qkxJazaD2em1FwLUI1ZgEiOG4Xr8mXmYLBhkIZwAX/ZGsvPCvMEa8vu6jWHGFP0PL O+xvyO5ZZTE8Hes37CPKCnSis217ZDk27eSmewXK8UAnA3FEL4qSTxfQfTJda/nPg9P8 yaXQlotZOlEeiz77X81NBHRWjEV+39FKZ1wBvsb8kXvsvscMZ6XMp5zazNLXq+f9fbf2 bY7A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=xqTqck0MunQzlvW3fvG1Eh5JVsO+310wsc6ir4XWOg8=; b=d2OQgjyq82a1PfZoGPtPp3E0PZoBd+NU15oX7Yxg0aKBoWwPbtEWxH/SLftSsNIUgf 3b/xdxUqhcjxrNtvWM857PcTeKAGtWoQJiZo9YlZzdE8h6RG/UbvZqN5sI98hpH8olDq Pq7wlLJ53QaneO4IhYMV0x9Q18EcgAfs+wyShfJTCOIKcP3et0zx9HuDs3QAEVF3Wrhu 7F7pwsO35d/6IPWU0KQ5Ho1QMSPxpJu1RQ8Zl3S9sOfBKUMrPqJRivaurVKhKA3dTAam oDw+J38GqZaspBh1xk25rPIeYgOgEV+BC3SrrH5jS3bZNpeSqzzf5KLLr828AufvYeFV qfLQ== X-Gm-Message-State: APjAAAUn3ZFZnEY+xycK7s/WBPyufXVtWZIsYIeVwJg8MlSFM+4NG6T6 U9FTqCdIMIoVKWbC73/Gla6VDdQu X-Google-Smtp-Source: APXvYqx/VGHdVWsKIJFPURExgJ03KjIrRp4uQuR5eGkcfc5bbnhAU+9EE5LXjLtXy9fSJPgB7ME4Ig== X-Received: by 2002:a5d:6144:: with SMTP id y4mr11215374wrt.367.1576781500573; Thu, 19 Dec 2019 10:51:40 -0800 (PST) Received: from x1w.redhat.com (34.red-83-42-66.dynamicip.rima-tde.net. [83.42.66.34]) by smtp.gmail.com with ESMTPSA id b67sm7435494wmc.38.2019.12.19.10.51.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 19 Dec 2019 10:51:40 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org, Niek Linnenbank Cc: Peter Maydell , Beniamino Galvani , qemu-arm@nongnu.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [RFC PATCH 09/13] hw/timer/allwinner: Rename AwA10TimerContext as AllwinnerTmrState Date: Thu, 19 Dec 2019 19:51:23 +0100 Message-Id: <20191219185127.24388-10-f4bug@amsat.org> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20191219185127.24388-1-f4bug@amsat.org> References: <20191219185127.24388-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 8bit X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::442 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 19 Dec 2019 18:51:48 -0000 This structure will be common to various Allwinner timer controllers, rename it. Signed-off-by: Philippe Mathieu-Daudé --- include/hw/timer/allwinner-a10-pit.h | 6 +++--- hw/timer/allwinner-a10-pit.c | 14 +++++++------- 2 files changed, 10 insertions(+), 10 deletions(-) diff --git a/include/hw/timer/allwinner-a10-pit.h b/include/hw/timer/allwinner-a10-pit.h index 8c64c33f01..3a47633cc4 100644 --- a/include/hw/timer/allwinner-a10-pit.h +++ b/include/hw/timer/allwinner-a10-pit.h @@ -10,7 +10,7 @@ typedef struct AwA10PITState AwA10PITState; -typedef struct AwA10TimerContext { +typedef struct AllwinnerTmrState { AwA10PITState *container; int index; ptimer_state *ptimer; @@ -18,14 +18,14 @@ typedef struct AwA10TimerContext { uint32_t control; uint32_t interval; uint32_t count; -} AwA10TimerContext; +} AllwinnerTmrState; struct AwA10PITState { /*< private >*/ SysBusDevice parent_obj; /*< public >*/ size_t timer_count; - AwA10TimerContext timer[AW_PIT_TIMER_MAX]; + AllwinnerTmrState timer[AW_PIT_TIMER_MAX]; MemoryRegion iomem; uint32_t clk_freq[4]; diff --git a/hw/timer/allwinner-a10-pit.c b/hw/timer/allwinner-a10-pit.c index 3f47588703..ecfc198937 100644 --- a/hw/timer/allwinner-a10-pit.c +++ b/hw/timer/allwinner-a10-pit.c @@ -234,10 +234,10 @@ static const VMStateDescription vmstate_aw_timer = { .version_id = 0, .minimum_version_id = 0, .fields = (VMStateField[]) { - VMSTATE_UINT32(control, AwA10TimerContext), - VMSTATE_UINT32(interval, AwA10TimerContext), - VMSTATE_UINT32(count, AwA10TimerContext), - VMSTATE_PTIMER(ptimer, AwA10TimerContext), + VMSTATE_UINT32(control, AllwinnerTmrState), + VMSTATE_UINT32(interval, AllwinnerTmrState), + VMSTATE_UINT32(count, AllwinnerTmrState), + VMSTATE_PTIMER(ptimer, AllwinnerTmrState), VMSTATE_END_OF_LIST() } }; @@ -252,7 +252,7 @@ static const VMStateDescription vmstate_a10_pit = { VMSTATE_STRUCT_ARRAY(timer, AwA10PITState, AW_PIT_TIMER_MAX, 0, vmstate_aw_timer, - AwA10TimerContext), + AllwinnerTmrState), VMSTATE_UINT32(watch_dog_mode, AwA10PITState), VMSTATE_UINT32(watch_dog_control, AwA10PITState), VMSTATE_UINT32(count_lo, AwA10PITState), @@ -289,7 +289,7 @@ static void a10_pit_reset(DeviceState *dev) static void a10_pit_timer_cb(void *opaque) { - AwA10TimerContext *tc = opaque; + AllwinnerTmrState *tc = opaque; AwA10PITState *s = tc->container; uint8_t i = tc->index; @@ -319,7 +319,7 @@ static void a10_pit_init(Object *obj) sysbus_init_mmio(sbd, &s->iomem); for (i = 0; i < s->timer_count; i++) { - AwA10TimerContext *tc = &s->timer[i]; + AllwinnerTmrState *tc = &s->timer[i]; tc->container = s; tc->index = i; -- 2.21.0 From MAILER-DAEMON Thu Dec 19 13:51:50 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1ii0tq-0007Nv-8F for mharc-qemu-arm@gnu.org; Thu, 19 Dec 2019 13:51:50 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:40380) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ii0tm-0007Ga-CH for qemu-arm@nongnu.org; Thu, 19 Dec 2019 13:51:47 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ii0tk-0008OR-9u for qemu-arm@nongnu.org; Thu, 19 Dec 2019 13:51:45 -0500 Received: from mail-wm1-x343.google.com ([2a00:1450:4864:20::343]:52233) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ii0tg-0007yc-F1; Thu, 19 Dec 2019 13:51:40 -0500 Received: by mail-wm1-x343.google.com with SMTP id p9so6523558wmc.2; Thu, 19 Dec 2019 10:51:40 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=ut5YgBRvjV0s9vJYJb1Jm2VxjMe8Smrb/fftQKlotks=; b=tlF1dLp9sSYb8LMXVv7K7cDXZlqumuq9LifLg45AsPkz5CeM5+i6LSNjhc8gBBXPDo YsEcvuQ8Zx/AmvldOwOmHna/+YAIB1HQt/zbvalN2mgZNZof0MwB/fK6D99EhA7nowgx 1E6IWPASbpIk38Ci6t+AJRXyg7MuuJwNrDQ3ANnKhifhOH7r3hgihgFScbtwzqDebmsu Yh8PVGvAktM9Ot0bgGIFC4MxZCH/nyUU4fwJpE7+IGLIHX/PbMy+LXqyFD+hovWemJtu LP7BvI8zCl4Ju2l4vZUfsL2uRXassV8+/zdX81E7lTF8Yb0qIo+1Cxs2slS8jDuw9Vzp lasw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=ut5YgBRvjV0s9vJYJb1Jm2VxjMe8Smrb/fftQKlotks=; b=l0nyZCRyJ6JkbBfp8AXW56Y5d9CQVflpNOYHa3iG3c5t3AbwsZ6lAA0HEW9fIiubng voFHB12Ou6yeuT4uzhY8t1c6zyejgmIWjlRgydWZfdsebX53/tVYO7siNwKn3Ka01pZR JLOfx2AtTcVUwB8HhOBO/R2iesjb2WfAqDeWyPuOIyi5SbytsyUu7yPFbMmrZBEYJ5El 9nfZLTL9EAcDttU2ZSBU92IpZeM8xt3X/m5S9GVnSduNmnn8Qgw+JXF0s+zMwGgaQ9H5 uluXlsmCo43se1kzDKVCXqk2PUhk3DuJW+D7TnBnfIYWNZRW0W4AbqRZqbd5tmltEskM eOIQ== X-Gm-Message-State: APjAAAUKXEtbDxsitxP1haJHg0GnOm9KrcYn2ZGDggMN2w/5mU/W0ql/ zFV2Cs2wUv0yGdDSnsG/aQn1BMlx X-Google-Smtp-Source: APXvYqwFJu/ocP0dt38fiw9hi6XsBa0pFZ0dZoHv5eBxSfExfizRYD91ZAkeJ4XoRUjOGNkp7kTN1A== X-Received: by 2002:a1c:7215:: with SMTP id n21mr12019344wmc.154.1576781498236; Thu, 19 Dec 2019 10:51:38 -0800 (PST) Received: from x1w.redhat.com (34.red-83-42-66.dynamicip.rima-tde.net. [83.42.66.34]) by smtp.gmail.com with ESMTPSA id b67sm7435494wmc.38.2019.12.19.10.51.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 19 Dec 2019 10:51:37 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org, Niek Linnenbank Cc: Peter Maydell , Beniamino Galvani , qemu-arm@nongnu.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [RFC PATCH 07/13] hw/timer/allwinner: Move timer specific fields into AwA10TimerContext Date: Thu, 19 Dec 2019 19:51:21 +0100 Message-Id: <20191219185127.24388-8-f4bug@amsat.org> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20191219185127.24388-1-f4bug@amsat.org> References: <20191219185127.24388-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 8bit X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::343 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 19 Dec 2019 18:51:48 -0000 Move all the timer-related fields into the same structure. We scrambled the migration structure, so we need to increase the version_id. Signed-off-by: Philippe Mathieu-Daudé --- Before I was using g_new(), now I keep AW_PIT_TIMER_MAX so We might avoid this patch. --- include/hw/timer/allwinner-a10-pit.h | 10 +-- hw/timer/allwinner-a10-pit.c | 99 ++++++++++++++++------------ 2 files changed, 63 insertions(+), 46 deletions(-) diff --git a/include/hw/timer/allwinner-a10-pit.h b/include/hw/timer/allwinner-a10-pit.h index b5ac6898fa..e0f864a954 100644 --- a/include/hw/timer/allwinner-a10-pit.h +++ b/include/hw/timer/allwinner-a10-pit.h @@ -13,23 +13,23 @@ typedef struct AwA10PITState AwA10PITState; typedef struct AwA10TimerContext { AwA10PITState *container; int index; + ptimer_state *ptimer; + qemu_irq irq; + uint32_t control; + uint32_t interval; + uint32_t count; } AwA10TimerContext; struct AwA10PITState { /*< private >*/ SysBusDevice parent_obj; /*< public >*/ - qemu_irq irq[AW_PIT_TIMER_MAX]; - ptimer_state * ptimer[AW_PIT_TIMER_MAX]; AwA10TimerContext timer[AW_PIT_TIMER_MAX]; MemoryRegion iomem; uint32_t clk_freq[4]; uint32_t irq_enable; uint32_t irq_status; - uint32_t control[AW_PIT_TIMER_MAX]; - uint32_t interval[AW_PIT_TIMER_MAX]; - uint32_t count[AW_PIT_TIMER_MAX]; uint32_t watch_dog_mode; uint32_t watch_dog_control; uint32_t count_lo; diff --git a/hw/timer/allwinner-a10-pit.c b/hw/timer/allwinner-a10-pit.c index 44e6eee3a8..ea92fdda32 100644 --- a/hw/timer/allwinner-a10-pit.c +++ b/hw/timer/allwinner-a10-pit.c @@ -59,7 +59,8 @@ static void a10_pit_update_irq(AwA10PITState *s) int i; for (i = 0; i < AW_A10_PIT_TIMER_NR; i++) { - qemu_set_irq(s->irq[i], !!(s->irq_status & s->irq_enable & (1 << i))); + qemu_set_irq(s->timer[i].irq, + !!(s->irq_status & s->irq_enable & (1 << i))); } } @@ -79,12 +80,12 @@ static uint64_t a10_pit_read(void *opaque, hwaddr offset, unsigned size) index -= 1; switch (offset & 0x0f) { case AW_A10_PIT_TIMER_CONTROL: - return s->control[index]; + return s->timer[index].control; case AW_A10_PIT_TIMER_INTERVAL: - return s->interval[index]; + return s->timer[index].interval; case AW_A10_PIT_TIMER_COUNT: - s->count[index] = ptimer_get_count(s->ptimer[index]); - return s->count[index]; + s->timer[index].count = ptimer_get_count(s->timer[index].ptimer); + return s->timer[index].count; default: qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%x\n", __func__, (int)offset); @@ -109,17 +110,17 @@ static uint64_t a10_pit_read(void *opaque, hwaddr offset, unsigned size) return 0; } -/* Must be called inside a ptimer transaction block for s->ptimer[index] */ +/* Must be called inside a ptimer transaction block for s->timer[idx].ptimer */ static void a10_pit_set_freq(AwA10PITState *s, int index) { uint32_t prescaler, source, source_freq; - prescaler = 1 << extract32(s->control[index], 4, 3); - source = extract32(s->control[index], 2, 2); + prescaler = 1 << extract32(s->timer[index].control, 4, 3); + source = extract32(s->timer[index].control, 2, 2); source_freq = s->clk_freq[source]; if (source_freq) { - ptimer_set_freq(s->ptimer[index], source_freq / prescaler); + ptimer_set_freq(s->timer[index].ptimer, source_freq / prescaler); } else { qemu_log_mask(LOG_GUEST_ERROR, "%s: Invalid clock source %u\n", __func__, source); @@ -147,31 +148,33 @@ static void a10_pit_write(void *opaque, hwaddr offset, uint64_t value, index -= 1; switch (offset & 0x0f) { case AW_A10_PIT_TIMER_CONTROL: - s->control[index] = value; - ptimer_transaction_begin(s->ptimer[index]); + s->timer[index].control = value; + ptimer_transaction_begin(s->timer[index].ptimer); a10_pit_set_freq(s, index); - if (s->control[index] & AW_A10_PIT_TIMER_RELOAD) { - ptimer_set_count(s->ptimer[index], s->interval[index]); + if (s->timer[index].control & AW_A10_PIT_TIMER_RELOAD) { + ptimer_set_count(s->timer[index].ptimer, + s->timer[index].interval); } - if (s->control[index] & AW_A10_PIT_TIMER_EN) { + if (s->timer[index].control & AW_A10_PIT_TIMER_EN) { int oneshot = 0; - if (s->control[index] & AW_A10_PIT_TIMER_MODE) { + if (s->timer[index].control & AW_A10_PIT_TIMER_MODE) { oneshot = 1; } - ptimer_run(s->ptimer[index], oneshot); + ptimer_run(s->timer[index].ptimer, oneshot); } else { - ptimer_stop(s->ptimer[index]); + ptimer_stop(s->timer[index].ptimer); } - ptimer_transaction_commit(s->ptimer[index]); + ptimer_transaction_commit(s->timer[index].ptimer); break; case AW_A10_PIT_TIMER_INTERVAL: - s->interval[index] = value; - ptimer_transaction_begin(s->ptimer[index]); - ptimer_set_limit(s->ptimer[index], s->interval[index], 1); - ptimer_transaction_commit(s->ptimer[index]); + s->timer[index].interval = value; + ptimer_transaction_begin(s->timer[index].ptimer); + ptimer_set_limit(s->timer[index].ptimer, + s->timer[index].interval, 1); + ptimer_transaction_commit(s->timer[index].ptimer); break; case AW_A10_PIT_TIMER_COUNT: - s->count[index] = value; + s->timer[index].count = value; break; default: qemu_log_mask(LOG_GUEST_ERROR, @@ -226,22 +229,35 @@ static Property a10_pit_properties[] = { DEFINE_PROP_END_OF_LIST(), }; +static const VMStateDescription vmstate_aw_timer = { + .name = "aw_timer", + .version_id = 0, + .minimum_version_id = 0, + .fields = (VMStateField[]) { + VMSTATE_UINT32(control, AwA10TimerContext), + VMSTATE_UINT32(interval, AwA10TimerContext), + VMSTATE_UINT32(count, AwA10TimerContext), + VMSTATE_PTIMER(ptimer, AwA10TimerContext), + VMSTATE_END_OF_LIST() + } +}; + static const VMStateDescription vmstate_a10_pit = { .name = "a10.pit", - .version_id = 1, - .minimum_version_id = 1, + .version_id = 2, + .minimum_version_id = 2, .fields = (VMStateField[]) { VMSTATE_UINT32(irq_enable, AwA10PITState), VMSTATE_UINT32(irq_status, AwA10PITState), - VMSTATE_UINT32_ARRAY(control, AwA10PITState, AW_PIT_TIMER_MAX), - VMSTATE_UINT32_ARRAY(interval, AwA10PITState, AW_PIT_TIMER_MAX), - VMSTATE_UINT32_ARRAY(count, AwA10PITState, AW_PIT_TIMER_MAX), + VMSTATE_STRUCT_ARRAY(timer, AwA10PITState, + AW_PIT_TIMER_MAX, + 0, vmstate_aw_timer, + AwA10TimerContext), VMSTATE_UINT32(watch_dog_mode, AwA10PITState), VMSTATE_UINT32(watch_dog_control, AwA10PITState), VMSTATE_UINT32(count_lo, AwA10PITState), VMSTATE_UINT32(count_hi, AwA10PITState), VMSTATE_UINT32(count_ctl, AwA10PITState), - VMSTATE_PTIMER_ARRAY(ptimer, AwA10PITState, AW_PIT_TIMER_MAX), VMSTATE_END_OF_LIST() } }; @@ -256,13 +272,13 @@ static void a10_pit_reset(DeviceState *dev) a10_pit_update_irq(s); for (i = 0; i < AW_A10_PIT_TIMER_NR; i++) { - s->control[i] = AW_A10_PIT_DEFAULT_CLOCK; - s->interval[i] = 0; - s->count[i] = 0; - ptimer_transaction_begin(s->ptimer[i]); - ptimer_stop(s->ptimer[i]); + s->timer[i].control = AW_A10_PIT_DEFAULT_CLOCK; + s->timer[i].interval = 0; + s->timer[i].count = 0; + ptimer_transaction_begin(s->timer[i].ptimer); + ptimer_stop(s->timer[i].ptimer); a10_pit_set_freq(s, i); - ptimer_transaction_commit(s->ptimer[i]); + ptimer_transaction_commit(s->timer[i].ptimer); } s->watch_dog_mode = 0; s->watch_dog_control = 0; @@ -277,11 +293,11 @@ static void a10_pit_timer_cb(void *opaque) AwA10PITState *s = tc->container; uint8_t i = tc->index; - if (s->control[i] & AW_A10_PIT_TIMER_EN) { + if (s->timer[i].control & AW_A10_PIT_TIMER_EN) { s->irq_status |= 1 << i; - if (s->control[i] & AW_A10_PIT_TIMER_MODE) { - ptimer_stop(s->ptimer[i]); - s->control[i] &= ~AW_A10_PIT_TIMER_EN; + if (s->timer[i].control & AW_A10_PIT_TIMER_MODE) { + ptimer_stop(s->timer[i].ptimer); + s->timer[i].control &= ~AW_A10_PIT_TIMER_EN; } a10_pit_update_irq(s); } @@ -294,7 +310,7 @@ static void a10_pit_init(Object *obj) uint8_t i; for (i = 0; i < AW_A10_PIT_TIMER_NR; i++) { - sysbus_init_irq(sbd, &s->irq[i]); + sysbus_init_irq(sbd, &s->timer[i].irq); } memory_region_init_io(&s->iomem, OBJECT(s), &a10_pit_ops, s, TYPE_AW_A10_PIT, 0x400); @@ -305,7 +321,8 @@ static void a10_pit_init(Object *obj) tc->container = s; tc->index = i; - s->ptimer[i] = ptimer_init(a10_pit_timer_cb, tc, PTIMER_POLICY_DEFAULT); + s->timer[i].ptimer = ptimer_init(a10_pit_timer_cb, tc, + PTIMER_POLICY_DEFAULT); } } -- 2.21.0 From MAILER-DAEMON Thu Dec 19 13:51:52 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1ii0ts-0007RU-Hb for mharc-qemu-arm@gnu.org; Thu, 19 Dec 2019 13:51:52 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:40587) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ii0to-0007Kd-9p for qemu-arm@nongnu.org; Thu, 19 Dec 2019 13:51:49 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ii0tm-00009o-Jy for qemu-arm@nongnu.org; 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[83.42.66.34]) by smtp.gmail.com with ESMTPSA id b67sm7435494wmc.38.2019.12.19.10.51.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 19 Dec 2019 10:51:41 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org, Niek Linnenbank Cc: Peter Maydell , Beniamino Galvani , qemu-arm@nongnu.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [RFC PATCH 10/13] hw/timer/allwinner: Rename AwA10PITState as AllwinnerTmrCtrlState Date: Thu, 19 Dec 2019 19:51:24 +0100 Message-Id: <20191219185127.24388-11-f4bug@amsat.org> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20191219185127.24388-1-f4bug@amsat.org> References: <20191219185127.24388-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 8bit X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::441 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 19 Dec 2019 18:51:50 -0000 This structure will be common to various Allwinner timer controllers, rename it. Signed-off-by: Philippe Mathieu-Daudé --- include/hw/arm/allwinner-a10.h | 2 +- include/hw/timer/allwinner-a10-pit.h | 6 ++-- hw/timer/allwinner-a10-pit.c | 42 ++++++++++++++-------------- 3 files changed, 25 insertions(+), 25 deletions(-) diff --git a/include/hw/arm/allwinner-a10.h b/include/hw/arm/allwinner-a10.h index 7d2d215630..28c043db39 100644 --- a/include/hw/arm/allwinner-a10.h +++ b/include/hw/arm/allwinner-a10.h @@ -30,7 +30,7 @@ typedef struct AwA10State { ARMCPU cpu; qemu_irq irq[AW_A10_PIC_INT_NR]; - AwA10PITState timer; + AllwinnerTmrCtrlState timer; AwA10PICState intc; AwEmacState emac; AllwinnerAHCIState sata; diff --git a/include/hw/timer/allwinner-a10-pit.h b/include/hw/timer/allwinner-a10-pit.h index 3a47633cc4..9e28c6697a 100644 --- a/include/hw/timer/allwinner-a10-pit.h +++ b/include/hw/timer/allwinner-a10-pit.h @@ -8,10 +8,10 @@ #define AW_PIT_TIMER_MAX 6 -typedef struct AwA10PITState AwA10PITState; +typedef struct AllwinnerTmrCtrlState AllwinnerTmrCtrlState; typedef struct AllwinnerTmrState { - AwA10PITState *container; + AllwinnerTmrCtrlState *container; int index; ptimer_state *ptimer; qemu_irq irq; @@ -20,7 +20,7 @@ typedef struct AllwinnerTmrState { uint32_t count; } AllwinnerTmrState; -struct AwA10PITState { +struct AllwinnerTmrCtrlState { /*< private >*/ SysBusDevice parent_obj; /*< public >*/ diff --git a/hw/timer/allwinner-a10-pit.c b/hw/timer/allwinner-a10-pit.c index ecfc198937..f2ac271e80 100644 --- a/hw/timer/allwinner-a10-pit.c +++ b/hw/timer/allwinner-a10-pit.c @@ -52,9 +52,9 @@ #define AW_A10_PIT_DEFAULT_CLOCK 0x4 #define AW_A10_PIT(obj) \ - OBJECT_CHECK(AwA10PITState, (obj), TYPE_AW_A10_PIT) + OBJECT_CHECK(AllwinnerTmrCtrlState, (obj), TYPE_AW_A10_PIT) -static void a10_pit_update_irq(AwA10PITState *s) +static void a10_pit_update_irq(AllwinnerTmrCtrlState *s) { int i; @@ -66,7 +66,7 @@ static void a10_pit_update_irq(AwA10PITState *s) static uint64_t a10_pit_read(void *opaque, hwaddr offset, unsigned size) { - AwA10PITState *s = AW_A10_PIT(opaque); + AllwinnerTmrCtrlState *s = AW_A10_PIT(opaque); uint8_t index; switch (offset) { @@ -111,7 +111,7 @@ static uint64_t a10_pit_read(void *opaque, hwaddr offset, unsigned size) } /* Must be called inside a ptimer transaction block for s->timer[idx].ptimer */ -static void a10_pit_set_freq(AwA10PITState *s, int index) +static void a10_pit_set_freq(AllwinnerTmrCtrlState *s, int index) { uint32_t prescaler, source, source_freq; @@ -130,7 +130,7 @@ static void a10_pit_set_freq(AwA10PITState *s, int index) static void a10_pit_write(void *opaque, hwaddr offset, uint64_t value, unsigned size) { - AwA10PITState *s = AW_A10_PIT(opaque); + AllwinnerTmrCtrlState *s = AW_A10_PIT(opaque); uint8_t index; switch (offset) { @@ -222,10 +222,10 @@ static const MemoryRegionOps a10_pit_ops = { }; static Property a10_pit_properties[] = { - DEFINE_PROP_UINT32("clk0-freq", AwA10PITState, clk_freq[0], 0), - DEFINE_PROP_UINT32("clk1-freq", AwA10PITState, clk_freq[1], 0), - DEFINE_PROP_UINT32("clk2-freq", AwA10PITState, clk_freq[2], 0), - DEFINE_PROP_UINT32("clk3-freq", AwA10PITState, clk_freq[3], 0), + DEFINE_PROP_UINT32("clk0-freq", AllwinnerTmrCtrlState, clk_freq[0], 0), + DEFINE_PROP_UINT32("clk1-freq", AllwinnerTmrCtrlState, clk_freq[1], 0), + DEFINE_PROP_UINT32("clk2-freq", AllwinnerTmrCtrlState, clk_freq[2], 0), + DEFINE_PROP_UINT32("clk3-freq", AllwinnerTmrCtrlState, clk_freq[3], 0), DEFINE_PROP_END_OF_LIST(), }; @@ -247,24 +247,24 @@ static const VMStateDescription vmstate_a10_pit = { .version_id = 2, .minimum_version_id = 2, .fields = (VMStateField[]) { - VMSTATE_UINT32(irq_enable, AwA10PITState), - VMSTATE_UINT32(irq_status, AwA10PITState), - VMSTATE_STRUCT_ARRAY(timer, AwA10PITState, + VMSTATE_UINT32(irq_enable, AllwinnerTmrCtrlState), + VMSTATE_UINT32(irq_status, AllwinnerTmrCtrlState), + VMSTATE_STRUCT_ARRAY(timer, AllwinnerTmrCtrlState, AW_PIT_TIMER_MAX, 0, vmstate_aw_timer, AllwinnerTmrState), - VMSTATE_UINT32(watch_dog_mode, AwA10PITState), - VMSTATE_UINT32(watch_dog_control, AwA10PITState), - VMSTATE_UINT32(count_lo, AwA10PITState), - VMSTATE_UINT32(count_hi, AwA10PITState), - VMSTATE_UINT32(count_ctl, AwA10PITState), + VMSTATE_UINT32(watch_dog_mode, AllwinnerTmrCtrlState), + VMSTATE_UINT32(watch_dog_control, AllwinnerTmrCtrlState), + VMSTATE_UINT32(count_lo, AllwinnerTmrCtrlState), + VMSTATE_UINT32(count_hi, AllwinnerTmrCtrlState), + VMSTATE_UINT32(count_ctl, AllwinnerTmrCtrlState), VMSTATE_END_OF_LIST() } }; static void a10_pit_reset(DeviceState *dev) { - AwA10PITState *s = AW_A10_PIT(dev); + AllwinnerTmrCtrlState *s = AW_A10_PIT(dev); uint8_t i; s->irq_enable = 0; @@ -290,7 +290,7 @@ static void a10_pit_reset(DeviceState *dev) static void a10_pit_timer_cb(void *opaque) { AllwinnerTmrState *tc = opaque; - AwA10PITState *s = tc->container; + AllwinnerTmrCtrlState *s = tc->container; uint8_t i = tc->index; if (s->timer[i].control & AW_A10_PIT_TIMER_EN) { @@ -305,7 +305,7 @@ static void a10_pit_timer_cb(void *opaque) static void a10_pit_init(Object *obj) { - AwA10PITState *s = AW_A10_PIT(obj); + AllwinnerTmrCtrlState *s = AW_A10_PIT(obj); SysBusDevice *sbd = SYS_BUS_DEVICE(obj); uint8_t i; @@ -341,7 +341,7 @@ static void a10_pit_class_init(ObjectClass *klass, void *data) static const TypeInfo a10_pit_info = { .name = TYPE_AW_A10_PIT, .parent = TYPE_SYS_BUS_DEVICE, - .instance_size = sizeof(AwA10PITState), + .instance_size = sizeof(AllwinnerTmrCtrlState), .instance_init = a10_pit_init, .class_init = a10_pit_class_init, }; -- 2.21.0 From MAILER-DAEMON Thu Dec 19 13:51:53 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1ii0tt-0007Sz-Gd for mharc-qemu-arm@gnu.org; Thu, 19 Dec 2019 13:51:53 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:40633) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ii0to-0007LO-N3 for qemu-arm@nongnu.org; Thu, 19 Dec 2019 13:51:49 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ii0tn-0000D3-EF for qemu-arm@nongnu.org; Thu, 19 Dec 2019 13:51:48 -0500 Received: from mail-wr1-x444.google.com ([2a00:1450:4864:20::444]:37721) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ii0tk-0008Kp-9k; Thu, 19 Dec 2019 13:51:44 -0500 Received: by mail-wr1-x444.google.com with SMTP id w15so7076584wru.4; Thu, 19 Dec 2019 10:51:44 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; 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[83.42.66.34]) by smtp.gmail.com with ESMTPSA id b67sm7435494wmc.38.2019.12.19.10.51.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 19 Dec 2019 10:51:42 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org, Niek Linnenbank Cc: Peter Maydell , Beniamino Galvani , qemu-arm@nongnu.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [RFC PATCH 11/13] hw/timer/allwinner: Introduce TYPE_AW_COMMON_PIT abstract device Date: Thu, 19 Dec 2019 19:51:25 +0100 Message-Id: <20191219185127.24388-12-f4bug@amsat.org> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20191219185127.24388-1-f4bug@amsat.org> References: <20191219185127.24388-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 8bit X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::444 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 19 Dec 2019 18:51:51 -0000 Extract the common code from the TYPE_AW_A10_PIT device into a new abstract device: TYPE_AW_COMMON_PIT, then use it as parent, so we inherit the same functionalities. Signed-off-by: Philippe Mathieu-Daudé --- At this point, the only fields we can modify are the timer_count and the region_size. Not enough to implement the H3 timer, since we need to move the WDOG register. Still some progress, so Niek can continue ;) --- include/hw/timer/allwinner-a10-pit.h | 1 + hw/timer/allwinner-a10-pit.c | 50 +++++++++++++++++++++++----- 2 files changed, 43 insertions(+), 8 deletions(-) diff --git a/include/hw/timer/allwinner-a10-pit.h b/include/hw/timer/allwinner-a10-pit.h index 9e28c6697a..8453a62706 100644 --- a/include/hw/timer/allwinner-a10-pit.h +++ b/include/hw/timer/allwinner-a10-pit.h @@ -4,6 +4,7 @@ #include "hw/ptimer.h" #include "hw/sysbus.h" +#define TYPE_AW_COMMON_PIT "allwinner-timer-controller" #define TYPE_AW_A10_PIT "allwinner-A10-timer" #define AW_PIT_TIMER_MAX 6 diff --git a/hw/timer/allwinner-a10-pit.c b/hw/timer/allwinner-a10-pit.c index f2ac271e80..ad409b96a1 100644 --- a/hw/timer/allwinner-a10-pit.c +++ b/hw/timer/allwinner-a10-pit.c @@ -54,6 +54,20 @@ #define AW_A10_PIT(obj) \ OBJECT_CHECK(AllwinnerTmrCtrlState, (obj), TYPE_AW_A10_PIT) +typedef struct AllwinnerTmrCtrlClass { + /*< private >*/ + SysBusDeviceClass parent_class; + /*< public >*/ + + size_t timer_count; + size_t region_size; +} AllwinnerTmrCtrlClass; + +#define AW_TIMER_CLASS(klass) \ + OBJECT_CLASS_CHECK(AllwinnerTmrCtrlClass, (klass), TYPE_AW_COMMON_PIT) +#define AW_TIMER_GET_CLASS(obj) \ + OBJECT_GET_CLASS(AllwinnerTmrCtrlClass, (obj), TYPE_AW_COMMON_PIT) + static void a10_pit_update_irq(AllwinnerTmrCtrlState *s) { int i; @@ -303,19 +317,20 @@ static void a10_pit_timer_cb(void *opaque) } } -static void a10_pit_init(Object *obj) +static void aw_pit_instance_init(Object *obj) { AllwinnerTmrCtrlState *s = AW_A10_PIT(obj); + AllwinnerTmrCtrlClass *c = AW_TIMER_GET_CLASS(s); SysBusDevice *sbd = SYS_BUS_DEVICE(obj); uint8_t i; - s->timer_count = AW_A10_PIT_TIMER_NR; + s->timer_count = c->timer_count; for (i = 0; i < s->timer_count; i++) { sysbus_init_irq(sbd, &s->timer[i].irq); } memory_region_init_io(&s->iomem, OBJECT(s), &a10_pit_ops, s, - TYPE_AW_A10_PIT, 0x400); + TYPE_AW_A10_PIT, c->region_size); sysbus_init_mmio(sbd, &s->iomem); for (i = 0; i < s->timer_count; i++) { @@ -328,26 +343,45 @@ static void a10_pit_init(Object *obj) } } -static void a10_pit_class_init(ObjectClass *klass, void *data) +static void aw_timer_class_init(ObjectClass *klass, void *data) { DeviceClass *dc = DEVICE_CLASS(klass); dc->reset = a10_pit_reset; dc->props = a10_pit_properties; - dc->desc = "allwinner a10 timer"; + dc->desc = "Allwinner Timer Controller"; dc->vmsd = &vmstate_a10_pit; } +static const TypeInfo allwinner_pit_info = { + .name = TYPE_AW_COMMON_PIT, + .parent = TYPE_SYS_BUS_DEVICE, + .instance_init = aw_pit_instance_init, + .instance_size = sizeof(AllwinnerTmrCtrlState), + .class_init = aw_timer_class_init, + .class_size = sizeof(AllwinnerTmrCtrlClass), + .abstract = true, +}; + +static void a10_pit_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + AllwinnerTmrCtrlClass *atc = AW_TIMER_CLASS(klass); + + dc->desc = "Allwinner A10 Timer Controller"; + atc->timer_count = AW_A10_PIT_TIMER_NR; + atc->region_size = 0x400; +} + static const TypeInfo a10_pit_info = { .name = TYPE_AW_A10_PIT, - .parent = TYPE_SYS_BUS_DEVICE, - .instance_size = sizeof(AllwinnerTmrCtrlState), - .instance_init = a10_pit_init, + .parent = TYPE_AW_COMMON_PIT, .class_init = a10_pit_class_init, }; static void a10_register_types(void) { + type_register_static(&allwinner_pit_info); type_register_static(&a10_pit_info); } -- 2.21.0 From MAILER-DAEMON Thu Dec 19 13:51:54 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1ii0tt-0007Tf-Vo for mharc-qemu-arm@gnu.org; Thu, 19 Dec 2019 13:51:53 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:40726) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ii0tp-0007Mu-HC for qemu-arm@nongnu.org; Thu, 19 Dec 2019 13:51:50 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ii0to-0000Il-Az for qemu-arm@nongnu.org; Thu, 19 Dec 2019 13:51:49 -0500 Received: from mail-wr1-x442.google.com ([2a00:1450:4864:20::442]:45869) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ii0tl-0008Rd-H0; Thu, 19 Dec 2019 13:51:45 -0500 Received: by mail-wr1-x442.google.com with SMTP id j42so7020594wrj.12; Thu, 19 Dec 2019 10:51:45 -0800 (PST) DKIM-Signature: v=1; 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[83.42.66.34]) by smtp.gmail.com with ESMTPSA id b67sm7435494wmc.38.2019.12.19.10.51.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 19 Dec 2019 10:51:43 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org, Niek Linnenbank Cc: Peter Maydell , Beniamino Galvani , qemu-arm@nongnu.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [RFC PATCH 12/13] hw/timer/allwinner: Rename AW_A10_PIT() as AW_TIMER_CTRL() Date: Thu, 19 Dec 2019 19:51:26 +0100 Message-Id: <20191219185127.24388-13-f4bug@amsat.org> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20191219185127.24388-1-f4bug@amsat.org> References: <20191219185127.24388-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 8bit X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::442 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 19 Dec 2019 18:51:52 -0000 This macro is now used by different Allwinner timer controllers, rename it. Signed-off-by: Philippe Mathieu-Daudé --- hw/timer/allwinner-a10-pit.c | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/hw/timer/allwinner-a10-pit.c b/hw/timer/allwinner-a10-pit.c index ad409b96a1..7413f046cc 100644 --- a/hw/timer/allwinner-a10-pit.c +++ b/hw/timer/allwinner-a10-pit.c @@ -51,8 +51,8 @@ #define AW_A10_PIT_DEFAULT_CLOCK 0x4 -#define AW_A10_PIT(obj) \ - OBJECT_CHECK(AllwinnerTmrCtrlState, (obj), TYPE_AW_A10_PIT) +#define AW_TIMER_CTRL(obj) \ + OBJECT_CHECK(AllwinnerTmrCtrlState, (obj), TYPE_AW_COMMON_PIT) typedef struct AllwinnerTmrCtrlClass { /*< private >*/ @@ -80,7 +80,7 @@ static void a10_pit_update_irq(AllwinnerTmrCtrlState *s) static uint64_t a10_pit_read(void *opaque, hwaddr offset, unsigned size) { - AllwinnerTmrCtrlState *s = AW_A10_PIT(opaque); + AllwinnerTmrCtrlState *s = AW_TIMER_CTRL(opaque); uint8_t index; switch (offset) { @@ -144,7 +144,7 @@ static void a10_pit_set_freq(AllwinnerTmrCtrlState *s, int index) static void a10_pit_write(void *opaque, hwaddr offset, uint64_t value, unsigned size) { - AllwinnerTmrCtrlState *s = AW_A10_PIT(opaque); + AllwinnerTmrCtrlState *s = AW_TIMER_CTRL(opaque); uint8_t index; switch (offset) { @@ -278,7 +278,7 @@ static const VMStateDescription vmstate_a10_pit = { static void a10_pit_reset(DeviceState *dev) { - AllwinnerTmrCtrlState *s = AW_A10_PIT(dev); + AllwinnerTmrCtrlState *s = AW_TIMER_CTRL(dev); uint8_t i; s->irq_enable = 0; @@ -319,7 +319,7 @@ static void a10_pit_timer_cb(void *opaque) static void aw_pit_instance_init(Object *obj) { - AllwinnerTmrCtrlState *s = AW_A10_PIT(obj); + AllwinnerTmrCtrlState *s = AW_TIMER_CTRL(obj); AllwinnerTmrCtrlClass *c = AW_TIMER_GET_CLASS(s); SysBusDevice *sbd = SYS_BUS_DEVICE(obj); uint8_t i; @@ -330,7 +330,7 @@ static void aw_pit_instance_init(Object *obj) sysbus_init_irq(sbd, &s->timer[i].irq); } memory_region_init_io(&s->iomem, OBJECT(s), &a10_pit_ops, s, - TYPE_AW_A10_PIT, c->region_size); + TYPE_AW_COMMON_PIT, c->region_size); sysbus_init_mmio(sbd, &s->iomem); for (i = 0; i < s->timer_count; i++) { -- 2.21.0 From MAILER-DAEMON Thu Dec 19 13:51:56 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1ii0tw-0007XN-Lt for mharc-qemu-arm@gnu.org; Thu, 19 Dec 2019 13:51:56 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:41010) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ii0ts-0007RJ-8a for qemu-arm@nongnu.org; Thu, 19 Dec 2019 13:51:54 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ii0tq-0000WW-LG for qemu-arm@nongnu.org; Thu, 19 Dec 2019 13:51:52 -0500 Received: from mail-wr1-x442.google.com ([2a00:1450:4864:20::442]:34084) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ii0tm-00007T-UD; Thu, 19 Dec 2019 13:51:47 -0500 Received: by mail-wr1-x442.google.com with SMTP id t2so7079099wrr.1; Thu, 19 Dec 2019 10:51:46 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=YyPr5A6rnL1yXh0BplYIOMYBILGoNVomOgJvBtF2zv8=; b=gUuO85EmTJkhrApzSOHS/sPi8S4du85fP8278KxyPehzc58JtzuXRUDCRLHkbiuvp3 NPazvAgtkPY9ecZf5T0lc7UizXq/gbCP/e70LfomtWKylgfOUoWoig1KNrPvqKdjTVut kj4T5ALd+fG02eGAUgloEo/sTga7V1oWywzZXCmyYy/XtgytdRuvGZz+D0Bvf19x/EXk ZP/lw86I7jo9M4e6zkHA9y4I2guuaSO4Tula4t3nu6W8Foa3lL1D7/miOnbr9lrICrvB PYp1a7J1Pdew9MiHsTcWogWyYLKMKiqXu0FmbzU6APBcnc2YOW+zCerMqrPuxJO9fBcN GWLw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=YyPr5A6rnL1yXh0BplYIOMYBILGoNVomOgJvBtF2zv8=; b=bDf3O4bo4QDGUDPRcTShc3X1Di+4fJN8pA/VOFJj+25oQVS9kVzdDb3s+HU1hAYuhq kON0/utza1Q7536jopm/IMYZPMpHomldISpEON3E1bWNi9SlhLvmVp4nZsgphXavVr06 268AiIu/mtNoA/hMc7Ju+Lkbts2e3X41aCDLxiCswMWIMXOTm8K84py6YIrI8A7MI8pq 6gVXt+KFd6+7oU9h7/YbG1aa9G05qedlCitXsDvc9XoSb9Mwk+2FHyN9/5UUMHFaXlY6 ECNYZleXvFnfdllRTPPhU1PN4xytQJ4arVr1YCaHzwaunF6ybxQrjeQxnaKMd8d94DTJ 2K3A== X-Gm-Message-State: APjAAAU8kHw3/qFbu1Ip0A/2901COuryXBYofBpXotztEvrM5sleL8Fg yw1YJW6O7qySU5Pbp/qp17TB5BC4 X-Google-Smtp-Source: APXvYqyLyNogYXoyqkJOSnD1UD2EBFCbaWURl03eELNPKujhSBXoRXU2zHSTo8NDkUW5Kqs2meGf+A== X-Received: by 2002:a05:6000:cb:: with SMTP id q11mr10656214wrx.14.1576781505386; Thu, 19 Dec 2019 10:51:45 -0800 (PST) Received: from x1w.redhat.com (34.red-83-42-66.dynamicip.rima-tde.net. [83.42.66.34]) by smtp.gmail.com with ESMTPSA id b67sm7435494wmc.38.2019.12.19.10.51.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 19 Dec 2019 10:51:44 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org, Niek Linnenbank Cc: Peter Maydell , Beniamino Galvani , qemu-arm@nongnu.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [RFC PATCH 13/13] hw/timer/allwinner: Rename functions not specific to the A10 SoC Date: Thu, 19 Dec 2019 19:51:27 +0100 Message-Id: <20191219185127.24388-14-f4bug@amsat.org> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20191219185127.24388-1-f4bug@amsat.org> References: <20191219185127.24388-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 8bit X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::442 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 19 Dec 2019 18:51:55 -0000 These functions are used by different Allwinner timer controllers, rename them. Signed-off-by: Philippe Mathieu-Daudé --- hw/timer/allwinner-a10-pit.c | 52 ++++++++++++++++++------------------ 1 file changed, 26 insertions(+), 26 deletions(-) diff --git a/hw/timer/allwinner-a10-pit.c b/hw/timer/allwinner-a10-pit.c index 7413f046cc..dff534cfef 100644 --- a/hw/timer/allwinner-a10-pit.c +++ b/hw/timer/allwinner-a10-pit.c @@ -68,7 +68,7 @@ typedef struct AllwinnerTmrCtrlClass { #define AW_TIMER_GET_CLASS(obj) \ OBJECT_GET_CLASS(AllwinnerTmrCtrlClass, (obj), TYPE_AW_COMMON_PIT) -static void a10_pit_update_irq(AllwinnerTmrCtrlState *s) +static void allwinner_timer_update_irq(AllwinnerTmrCtrlState *s) { int i; @@ -78,7 +78,7 @@ static void a10_pit_update_irq(AllwinnerTmrCtrlState *s) } } -static uint64_t a10_pit_read(void *opaque, hwaddr offset, unsigned size) +static uint64_t allwinner_timer_read(void *opaque, hwaddr offset, unsigned size) { AllwinnerTmrCtrlState *s = AW_TIMER_CTRL(opaque); uint8_t index; @@ -125,7 +125,7 @@ static uint64_t a10_pit_read(void *opaque, hwaddr offset, unsigned size) } /* Must be called inside a ptimer transaction block for s->timer[idx].ptimer */ -static void a10_pit_set_freq(AllwinnerTmrCtrlState *s, int index) +static void allwinner_ptimer_set_freq(AllwinnerTmrCtrlState *s, int index) { uint32_t prescaler, source, source_freq; @@ -141,8 +141,8 @@ static void a10_pit_set_freq(AllwinnerTmrCtrlState *s, int index) } } -static void a10_pit_write(void *opaque, hwaddr offset, uint64_t value, - unsigned size) +static void allwinner_timer_write(void *opaque, hwaddr offset, + uint64_t value, unsigned size) { AllwinnerTmrCtrlState *s = AW_TIMER_CTRL(opaque); uint8_t index; @@ -150,11 +150,11 @@ static void a10_pit_write(void *opaque, hwaddr offset, uint64_t value, switch (offset) { case AW_A10_PIT_TIMER_IRQ_EN: s->irq_enable = value; - a10_pit_update_irq(s); + allwinner_timer_update_irq(s); break; case AW_A10_PIT_TIMER_IRQ_ST: s->irq_status &= ~value; - a10_pit_update_irq(s); + allwinner_timer_update_irq(s); break; case AW_A10_PIT_TIMER_BASE ... AW_A10_PIT_TIMER_BASE_END: index = offset & 0xf0; @@ -164,7 +164,7 @@ static void a10_pit_write(void *opaque, hwaddr offset, uint64_t value, case AW_A10_PIT_TIMER_CONTROL: s->timer[index].control = value; ptimer_transaction_begin(s->timer[index].ptimer); - a10_pit_set_freq(s, index); + allwinner_ptimer_set_freq(s, index); if (s->timer[index].control & AW_A10_PIT_TIMER_RELOAD) { ptimer_set_count(s->timer[index].ptimer, s->timer[index].interval); @@ -229,13 +229,13 @@ static void a10_pit_write(void *opaque, hwaddr offset, uint64_t value, } } -static const MemoryRegionOps a10_pit_ops = { - .read = a10_pit_read, - .write = a10_pit_write, +static const MemoryRegionOps allwinner_timer_ops = { + .read = allwinner_timer_read, + .write = allwinner_timer_write, .endianness = DEVICE_NATIVE_ENDIAN, }; -static Property a10_pit_properties[] = { +static Property allwinner_timer_properties[] = { DEFINE_PROP_UINT32("clk0-freq", AllwinnerTmrCtrlState, clk_freq[0], 0), DEFINE_PROP_UINT32("clk1-freq", AllwinnerTmrCtrlState, clk_freq[1], 0), DEFINE_PROP_UINT32("clk2-freq", AllwinnerTmrCtrlState, clk_freq[2], 0), @@ -276,14 +276,14 @@ static const VMStateDescription vmstate_a10_pit = { } }; -static void a10_pit_reset(DeviceState *dev) +static void allwinner_timer_reset(DeviceState *dev) { AllwinnerTmrCtrlState *s = AW_TIMER_CTRL(dev); uint8_t i; s->irq_enable = 0; s->irq_status = 0; - a10_pit_update_irq(s); + allwinner_timer_update_irq(s); for (i = 0; i < s->timer_count; i++) { s->timer[i].control = AW_A10_PIT_DEFAULT_CLOCK; @@ -291,7 +291,7 @@ static void a10_pit_reset(DeviceState *dev) s->timer[i].count = 0; ptimer_transaction_begin(s->timer[i].ptimer); ptimer_stop(s->timer[i].ptimer); - a10_pit_set_freq(s, i); + allwinner_ptimer_set_freq(s, i); ptimer_transaction_commit(s->timer[i].ptimer); } s->watch_dog_mode = 0; @@ -301,7 +301,7 @@ static void a10_pit_reset(DeviceState *dev) s->count_ctl = 0; } -static void a10_pit_timer_cb(void *opaque) +static void allwinner_ptimer_cb(void *opaque) { AllwinnerTmrState *tc = opaque; AllwinnerTmrCtrlState *s = tc->container; @@ -313,11 +313,11 @@ static void a10_pit_timer_cb(void *opaque) ptimer_stop(s->timer[i].ptimer); s->timer[i].control &= ~AW_A10_PIT_TIMER_EN; } - a10_pit_update_irq(s); + allwinner_timer_update_irq(s); } } -static void aw_pit_instance_init(Object *obj) +static void allwinner_timer_instance_init(Object *obj) { AllwinnerTmrCtrlState *s = AW_TIMER_CTRL(obj); AllwinnerTmrCtrlClass *c = AW_TIMER_GET_CLASS(s); @@ -329,8 +329,8 @@ static void aw_pit_instance_init(Object *obj) for (i = 0; i < s->timer_count; i++) { sysbus_init_irq(sbd, &s->timer[i].irq); } - memory_region_init_io(&s->iomem, OBJECT(s), &a10_pit_ops, s, - TYPE_AW_COMMON_PIT, c->region_size); + memory_region_init_io(&s->iomem, OBJECT(s), &allwinner_timer_ops, + s, TYPE_AW_COMMON_PIT, c->region_size); sysbus_init_mmio(sbd, &s->iomem); for (i = 0; i < s->timer_count; i++) { @@ -338,7 +338,7 @@ static void aw_pit_instance_init(Object *obj) tc->container = s; tc->index = i; - s->timer[i].ptimer = ptimer_init(a10_pit_timer_cb, tc, + s->timer[i].ptimer = ptimer_init(allwinner_ptimer_cb, tc, PTIMER_POLICY_DEFAULT); } } @@ -347,8 +347,8 @@ static void aw_timer_class_init(ObjectClass *klass, void *data) { DeviceClass *dc = DEVICE_CLASS(klass); - dc->reset = a10_pit_reset; - dc->props = a10_pit_properties; + dc->reset = allwinner_timer_reset; + dc->props = allwinner_timer_properties; dc->desc = "Allwinner Timer Controller"; dc->vmsd = &vmstate_a10_pit; } @@ -356,7 +356,7 @@ static void aw_timer_class_init(ObjectClass *klass, void *data) static const TypeInfo allwinner_pit_info = { .name = TYPE_AW_COMMON_PIT, .parent = TYPE_SYS_BUS_DEVICE, - .instance_init = aw_pit_instance_init, + .instance_init = allwinner_timer_instance_init, .instance_size = sizeof(AllwinnerTmrCtrlState), .class_init = aw_timer_class_init, .class_size = sizeof(AllwinnerTmrCtrlClass), @@ -379,10 +379,10 @@ static const TypeInfo a10_pit_info = { .class_init = a10_pit_class_init, }; -static void a10_register_types(void) +static void allwinner_timer_register_types(void) { type_register_static(&allwinner_pit_info); type_register_static(&a10_pit_info); } -type_init(a10_register_types); +type_init(allwinner_timer_register_types); -- 2.21.0 From MAILER-DAEMON Thu Dec 19 14:06:51 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1ii18N-0007tT-Ov for mharc-qemu-arm@gnu.org; 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[83.42.66.34]) by smtp.gmail.com with ESMTPSA id g7sm7360592wrq.21.2019.12.19.11.06.37 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 19 Dec 2019 11:06:37 -0800 (PST) Subject: Re: [PATCH v2 02/10] hw: arm: add Xunlong Orange Pi PC machine To: Niek Linnenbank Cc: QEMU Developers , qemu-arm , Peter Maydell References: <20191216233519.29030-1-nieklinnenbank@gmail.com> <20191216233519.29030-3-nieklinnenbank@gmail.com> From: =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= Message-ID: Date: Thu, 19 Dec 2019 20:06:36 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.2.2 MIME-Version: 1.0 In-Reply-To: Content-Language: en-US X-MC-Unique: bpQPLGkpNyqhjER7HgkbnQ-1 X-Mimecast-Spam-Score: 0 Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 207.211.31.81 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 19 Dec 2019 19:06:50 -0000 On 12/18/19 9:14 PM, Niek Linnenbank wrote: > Hi Philippe, >=20 > Thanks again for your quick and helpful feedback! :-) >=20 > On Tue, Dec 17, 2019 at 8:31 AM Philippe Mathieu-Daud=C3=A9=20 > > wrote: >=20 > Hi Niek, >=20 > On 12/17/19 12:35 AM, Niek Linnenbank wrote: > > The Xunlong Orange Pi PC is an Allwinner H3 System on Chip > > based embedded computer with mainline support in both U-Boot > > and Linux. The board comes with a Quad Core Cortex A7 @ 1.3GHz, > > 512MB RAM, 100Mbit ethernet, USB, SD/MMC, USB, HDMI and > > various other I/O. This commit add support for the Xunlong > > Orange Pi PC machine. > > > > Signed-off-by: Niek Linnenbank > > > Tested-by: KONRAD Frederic > > > --- > >=C2=A0 =C2=A0hw/arm/orangepi.c=C2=A0 =C2=A0 | 101 > +++++++++++++++++++++++++++++++++++++++++++ > >=C2=A0 =C2=A0MAINTAINERS=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 |=C2=A0 = =C2=A01 + > >=C2=A0 =C2=A0hw/arm/Makefile.objs |=C2=A0 =C2=A02 +- > >=C2=A0 =C2=A03 files changed, 103 insertions(+), 1 deletion(-) > >=C2=A0 =C2=A0create mode 100644 hw/arm/orangepi.c > > > > diff --git a/hw/arm/orangepi.c b/hw/arm/orangepi.c > > new file mode 100644 > > index 0000000000..62cefc8c06 > > --- /dev/null > > +++ b/hw/arm/orangepi.c > > @@ -0,0 +1,101 @@ > > +/* > > + * Orange Pi emulation > > + * > > + * Copyright (C) 2019 Niek Linnenbank > > > + * > > + * This program is free software: you can redistribute it and/or > modify > > + * it under the terms of the GNU General Public License as > published by > > + * the Free Software Foundation, either version 2 of the License,= or > > + * (at your option) any later version. > > + * > > + * This program is distributed in the hope that it will be useful= , > > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.=C2=A0 See= the > > + * GNU General Public License for more details. > > + * > > + * You should have received a copy of the GNU General Public Lice= nse > > + * along with this program.=C2=A0 If not, see > . > > + */ > > + > > +#include "qemu/osdep.h" > > +#include "exec/address-spaces.h" > > +#include "qapi/error.h" > > +#include "cpu.h" > > +#include "hw/sysbus.h" > > +#include "hw/boards.h" > > +#include "hw/qdev-properties.h" > > +#include "hw/arm/allwinner-h3.h" > > + > > +static struct arm_boot_info orangepi_binfo =3D { > > +=C2=A0 =C2=A0 .board_id =3D -1, > > +}; > > + > > +typedef struct OrangePiState { > > +=C2=A0 =C2=A0 AwH3State *h3; > > +=C2=A0 =C2=A0 MemoryRegion sdram; > > +} OrangePiState; > > + > > +static void orangepi_init(MachineState *machine) > > +{ > > +=C2=A0 =C2=A0 OrangePiState *s =3D g_new(OrangePiState, 1); > > + > > +=C2=A0 =C2=A0 /* Only allow Cortex-A7 for this board */ > > +=C2=A0 =C2=A0 if (strcmp(machine->cpu_type, > ARM_CPU_TYPE_NAME("cortex-a7")) !=3D 0) { > > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 error_report("This board can only be = used with cortex-a7 > CPU"); > > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 exit(1); > > +=C2=A0 =C2=A0 } > > + > > +=C2=A0 =C2=A0 s->h3 =3D AW_H3(object_new(TYPE_AW_H3)); > > + > > +=C2=A0 =C2=A0 /* Setup timer properties */ > > +=C2=A0 =C2=A0 object_property_set_int(OBJECT(&s->h3->timer), 3276= 8, > "clk0-freq", > > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 &error_abort); >=20 > You access the timer object which is contained inside the soc object, > but the soc isn't realized yet... I wonder if this is OK. Usually wha= t > we do is, either: > - add a 'xtal-freq-hz' property to the SoC, set it here in the board, > then in soc::realize() set the property to the timer > - add an alias in the SoC to the timer 'freq-hz' property: > =C2=A0 =C2=A0 =C2=A0object_property_add_alias(soc, "xtal-freq-hz", O= BJECT(&s->timer), > =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 "freq-hz", &err= or_abort); >=20 > Good point. I shall rework that part using your suggestion. > Actually, I copied the timer support code from the existing cubieboard.c= =20 > that has > the Allwinner A10, so potentially the same problem is there. >=20 > While looking more closer at this part, I now also discovered that the=20 > timer module from the Allwinner H3 is > mostly a stripped down version of the timer module in the Allwinner A10: >=20 > =C2=A0 Allwinner A10, 10.2 Timer Register List, page 85: > https://linux-sunxi.org/images/1/1e/Allwinner_A10_User_manual_V1.5.pdf >=20 > The A10 version has six timers, where the H3 has only two. That should=20 > be fine I would say, the guest would simply > use those available on H3 and ignore the rest. There is however one=20 > conflicting difference: the WDOG0 registers in the Allwinner H3 start > at a different offset and are also different. The current A10 timer does= =20 > not currently implement the watchdog part. >=20 > The watchdog part of this timer is relevant for the 'reset' command in=20 > U-Boot: that does not work right now, because > U-Boot implements the reset for the Allwinner H3 boards by letting this= =20 > watchdog expire (and we dont emulate it). > Also, this timer module is required for booting Linux, without it the=20 > kernel crashes using the sunxi_defconfig: >=20 > [ 0.000000] PC is at sun4i_timer_init+0x34/0x168 > [ 0.000000] LR is at sun4i_timer_init+0x2c/0x168 > [ 0.000000] pc : [] lr : [] psr: 600000d3 > [ 0.000000] sp : c0a03f70 ip : eec00188 fp : ef7ed040 > ... > [ 0.000000] [] (sun4i_timer_init) from [] (timer_p= robe+0x74/0xe4) > [ 0.000000] [] (timer_probe) from [] (start_kernel= +0x2e0/0x440) > [ 0.000000] [] (start_kernel) from [<00000000>] (0x0) >=20 >=20 > So in my opinion its a bit of a trade off here: we can keep it like this= =20 > and re-use the A10 timer for now, and perhaps > attempt to generalize that module for proper use in both SoCs. Or we can= =20 > introduce a new H3 specific timer module. > What do you think? See my answer about generalize/reuse here: http://mid.mail-archive.com/20191219185127.24388-1-f4bug@amsat.org From MAILER-DAEMON Thu Dec 19 14:15:47 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1ii1H1-0007O0-6S for mharc-qemu-arm@gnu.org; Thu, 19 Dec 2019 14:15:47 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:40622) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ii1Gy-0007L2-5P for qemu-arm@nongnu.org; Thu, 19 Dec 2019 14:15:45 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ii1Gr-0002FS-AZ for qemu-arm@nongnu.org; Thu, 19 Dec 2019 14:15:40 -0500 Received: from mail-wr1-x443.google.com ([2a00:1450:4864:20::443]:41246) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ii1Go-0002Cm-2G for qemu-arm@nongnu.org; Thu, 19 Dec 2019 14:15:34 -0500 Received: by mail-wr1-x443.google.com with SMTP id c9so7113116wrw.8 for ; Thu, 19 Dec 2019 11:15:33 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=references:user-agent:from:to:cc:subject:in-reply-to:date :message-id:mime-version:content-transfer-encoding; bh=WdFoefIyBmEmGr0Uzh61Q3jXTyhvbdrVyQ7nh5f6AmE=; b=C9l4Gt7B4s4ujVu/sTR17tZJvFCbVod5yGQZXUDFST5By834c+cvnLPyTMSi4wciWU 24F3RS+iGOupASA61Dt15SWuUmwmI8QcklBAcKIytGQ+FInly4TIU9dWj1oUj265K1Tt HJlxULyTY98IBvmcMAvNMkN/GnNGz4525Xy6KDVJ70Kh6WExvnuM+i9GfizMTxKyFvwk QKTh6fDyJrno6FwPK57kBd4rFMF7DivHjqDLiHidU6gLUTti8svTMLLIFtZlTS5fi2RY o5fmd4TLGU2o0AqwEhBl6reFkuwRajyouNmL0p4C1Fi0zqLqkIEcOHxjgCIgUuC1bu7/ gocQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:references:user-agent:from:to:cc:subject :in-reply-to:date:message-id:mime-version:content-transfer-encoding; bh=WdFoefIyBmEmGr0Uzh61Q3jXTyhvbdrVyQ7nh5f6AmE=; b=MRfPMwwq7jKF8CZUYpOFc0YGMtqyv7UWNez6qIDp0kUO76SJmBF1O75k90n8hyB+rz +bABkmJwY4oTfGY9m6SL4lhzp53y66oPuXbFdp+kBPTLHX7asLLpiqWHr5hH+HmgnQ/V Xkh6d6evryPuzRiJFwKGg8vnocEEELJI/0xZgfe3538aEHstFAWfNsxMu1jhi6dM7Q+H gpM+8fAdadCcwlDekf/dXs1gtbuHbi9iz7VW/glfzQqZoL/+ppcj5Ga6o8OrosjuWbkQ TE6ALArNdCaIxYUnW0sszB7cYKPG2997QHPjnSginP2+Qlh5Igc/knWEx5i3AtlO16MR +Ebg== X-Gm-Message-State: APjAAAXm9DrV0OS4mttZg4Qe8Y4F/4nH/01KzsGYrpawVVlNy1thz2Xp JBJPTqH649JUmqsTohD0SKSbrA== X-Google-Smtp-Source: APXvYqyEJhgNDMsqninN1OqJnsXLx2jpKOkQEorDzivi5zZj0b5CNTZSN9BFcNTv60HjWjBpSI/QWw== X-Received: by 2002:adf:a308:: with SMTP id c8mr10908033wrb.240.1576782932498; Thu, 19 Dec 2019 11:15:32 -0800 (PST) Received: from zen.linaroharston ([51.148.130.216]) by smtp.gmail.com with ESMTPSA id x17sm7156560wrt.74.2019.12.19.11.15.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 19 Dec 2019 11:15:31 -0800 (PST) Received: from zen (localhost [127.0.0.1]) by zen.linaroharston (Postfix) with ESMTP id 7919E1FF87; Thu, 19 Dec 2019 19:15:30 +0000 (GMT) References: <20191211170520.7747-1-alex.bennee@linaro.org> <20191211170520.7747-13-alex.bennee@linaro.org> <69e10c48-8bdf-cbe0-3372-815b647f8312@linaro.org> User-agent: mu4e 1.3.5; emacs 27.0.50 From: Alex =?utf-8?Q?Benn=C3=A9e?= To: Richard Henderson Cc: qemu-devel@nongnu.org, alan.hayward@arm.com, luis.machado@linaro.org, damien.hedde@greensocs.com, Peter Maydell , "open list:ARM TCG CPUs" Subject: Re: [PATCH v3 12/20] target/arm: generate xml description of our SVE registers In-reply-to: <69e10c48-8bdf-cbe0-3372-815b647f8312@linaro.org> Date: Thu, 19 Dec 2019 19:15:30 +0000 Message-ID: <87k16sdt4d.fsf@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::443 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 19 Dec 2019 19:15:45 -0000 Richard Henderson writes: > On 12/11/19 9:05 AM, Alex Benn=C3=A9e wrote: >> +static struct TypeSize vec_lanes[] =3D { > > const. > >> + case 51: >> + return gdb_get_reg64(buf, (cpu->env.vfp.zcr_el[1] & 0xf) + 1); > > You need to use sve_zcr_len_for_el to get the effective vq. > Also, I thought vg =3D=3D 2 * vq. > > + case 51: >> + { >> + uint64_t val =3D *(uint64_t *) buf; >> + cpu->env.vfp.zcr_el[1] =3D (val - 1) & 0xf; > > You cannot hard-code EL1 without ifdef CONFIG_USER_ONLY. If the effectiv= e vq > decreases, you must call aarch64_sve_narrow_vq. You must call arm_rebuil= d_hflags. I'm just going to drop vg (and therefor the ability to set it) from the regset. It was only meant to be an indicator and gdb doesn't actually look to it to size it's output. The likely dynamic extension will just re-transmit the whole XML when a change occurs. --=20 Alex Benn=C3=A9e From MAILER-DAEMON Thu Dec 19 15:04:51 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1ii22V-0000KU-Ds for mharc-qemu-arm@gnu.org; Thu, 19 Dec 2019 15:04:51 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:52026) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ii22S-0000Fx-1v for qemu-arm@nongnu.org; Thu, 19 Dec 2019 15:04:49 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ii22O-0003jy-RL for qemu-arm@nongnu.org; Thu, 19 Dec 2019 15:04:46 -0500 Received: from us-smtp-2.mimecast.com ([207.211.31.81]:58258 helo=us-smtp-delivery-1.mimecast.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1ii22O-0003cI-BC for qemu-arm@nongnu.org; Thu, 19 Dec 2019 15:04:44 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; 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Thu, 19 Dec 2019 20:04:36 +0000 (UTC) Date: Thu, 19 Dec 2019 15:04:33 -0500 From: Cleber Rosa To: Philippe =?iso-8859-1?Q?Mathieu-Daud=E9?= Cc: qemu-devel@nongnu.org, Guenter Roeck , Niek Linnenbank , Peter Maydell , qemu-arm@nongnu.org Subject: Re: [PATCH 3/5] tests/boot_linux_console: Add a SD card test for the OrangePi PC board Message-ID: <20191219200433.GA28892@localhost.localdomain> References: <20191217182730.943-1-f4bug@amsat.org> <20191217182730.943-4-f4bug@amsat.org> MIME-Version: 1.0 In-Reply-To: <20191217182730.943-4-f4bug@amsat.org> X-Scanned-By: MIMEDefang 2.79 on 10.5.11.14 X-Mimecast-Spam-Score: 0 Content-Type: multipart/signed; micalg=pgp-sha256; protocol="application/pgp-signature"; boundary="n8g4imXOkfNTN/H1" Content-Disposition: inline X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 207.211.31.81 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 19 Dec 2019 20:04:49 -0000 --n8g4imXOkfNTN/H1 Content-Type: text/plain; charset=iso-8859-1 Content-Disposition: inline Content-Transfer-Encoding: quoted-printable On Tue, Dec 17, 2019 at 07:27:28PM +0100, Philippe Mathieu-Daud=E9 wrote: > The kernel image and DeviceTree blob are built by the Raspbian > project (based on Debian): > https://www.raspbian.org/RaspbianImages >=20 > The SD image is from the kernelci.org project: > https://kernelci.org/faq/#the-code >=20 > If ARM is a target being built, "make check-acceptance" will > automatically include this test by the use of the "arch:arm" tags. >=20 > Alternatively, this test can be run using: >=20 > $ avocado --show=3Dconsole run -t machine:orangepi-pc tests/acceptance/= boot_linux_console.py > console: Uncompressing Linux... done, booting the kernel. > console: Booting Linux on physical CPU 0x0 > console: Linux version 4.20.7-sunxi (root@armbian.com) (gcc version 7.2= .1 20171011 (Linaro GCC 7.2-2017.11)) #5.75 SMP Fri Feb 8 09:02:10 CET 2019 > console: CPU: ARMv7 Processor [410fc075] revision 5 (ARMv7), cr=3D50c53= 87d > [...] > console: sunxi-wdt 1c20ca0.watchdog: Watchdog enabled (timeout=3D16 sec= , nowayout=3D0) > console: sunxi-mmc 1c0f000.mmc: Linked as a consumer to regulator.2 > console: sunxi-mmc 1c0f000.mmc: Got CD GPIO > console: ledtrig-cpu: registered to indicate activity on CPUs > console: hidraw: raw HID events driver (C) Jiri Kosina > console: usbcore: registered new interface driver usbhid > console: usbhid: USB HID core driver > console: Initializing XFRM netlink socket > console: sunxi-mmc 1c0f000.mmc: initialized, max. request size: 16384 K= B > console: NET: Registered protocol family 10 > console: mmc0: host does not support reading read-only switch, assuming= write-enable > console: mmc0: Problem switching card into high-speed mode! > console: mmc0: new SD card at address 4567 > console: mmcblk0: mmc0:4567 QEMU! 60.0 MiB > [...] > console: EXT4-fs (mmcblk0): mounting ext2 file system using the ext4 su= bsystem > console: EXT4-fs (mmcblk0): mounted filesystem without journal. Opts: (= null) > console: VFS: Mounted root (ext2 filesystem) on device 179:0. > console: Run /sbin/init as init process > console: EXT4-fs (mmcblk0): re-mounted. Opts: block_validity,barrier,us= er_xattr,acl > console: Starting syslogd: OK > console: Starting klogd: OK > console: Populating /dev using udev: udevd[203]: starting version 3.2.7 > console: /bin/sh: can't access tty; job control turned off > console: cat /proc/partitions > console: / # cat /proc/partitions > console: major minor #blocks name > console: 1 0 4096 ram0 > console: 1 1 4096 ram1 > console: 1 2 4096 ram2 > console: 1 3 4096 ram3 > console: 179 0 61440 mmcblk0 > console: reboot > console: / # reboot > console: umount: devtmpfs busy - remounted read-only > console: EXT4-fs (mmcblk0): re-mounted. Opts: (null) > console: The system is going down NOW! > console: Sent SIGTERM to all processes > console: Sent SIGKILL to all processes > console: Requesting system reboot > console: reboot: Restarting system > JOB TIME : 68.64 s >=20 > Signed-off-by: Philippe Mathieu-Daud=E9 > --- > tests/acceptance/boot_linux_console.py | 42 ++++++++++++++++++++++++++ > 1 file changed, 42 insertions(+) >=20 > diff --git a/tests/acceptance/boot_linux_console.py b/tests/acceptance/bo= ot_linux_console.py > index daabd47404..8179b45910 100644 > --- a/tests/acceptance/boot_linux_console.py > +++ b/tests/acceptance/boot_linux_console.py > @@ -478,6 +478,48 @@ class BootLinuxConsole(Test): > exec_command_and_wait_for_pattern(self, 'reboot', > 'reboot: Restarting syst= em') > =20 > + def test_arm_orangepi_sd(self): Same suggestion wrt test name as previous two patches. > + """ > + :avocado: tags=3Darch:arm > + :avocado: tags=3Dmachine:orangepi-pc > + """ > + deb_url =3D ('https://apt.armbian.com/pool/main/l/' > + 'linux-4.20.7-sunxi/linux-image-dev-sunxi_5.75_armhf.= deb') > + deb_hash =3D '1334c29c44d984ffa05ed10de8c3361f33d78315' > + deb_path =3D self.fetch_asset(deb_url, asset_hash=3Ddeb_hash) > + kernel_path =3D self.extract_from_deb(deb_path, > + '/boot/vmlinuz-4.20.7-sunxi'= ) > + dtb_path =3D '/usr/lib/linux-image-dev-sunxi/sun8i-h3-orangepi-p= c.dtb' > + dtb_path =3D self.extract_from_deb(deb_path, dtb_path) > + rootfs_url =3D ('http://storage.kernelci.org/images/rootfs/build= root/' > + 'kci-2019.02/armel/base/rootfs.ext2.xz') > + rootfs_hash =3D '692510cb625efda31640d1de0a8d60e26040f061' > + rootfs_path_xz =3D self.fetch_asset(rootfs_url, asset_hash=3Droo= tfs_hash) > + rootfs_path =3D os.path.join(self.workdir, 'rootfs.cpio') > + archive.lzma_uncompress(rootfs_path_xz, rootfs_path) > + > + self.vm.set_machine('orangepi-pc') Can/should be dropped. With this, Tested-by: Cleber Rosa Reviewed-by: Cleber Rosa --n8g4imXOkfNTN/H1 Content-Type: application/pgp-signature; name="signature.asc" -----BEGIN PGP SIGNATURE----- iQIzBAEBCAAdFiEEeruW64tGuU1eD+m7ZX6NM6XyCfMFAl37184ACgkQZX6NM6Xy CfPeKQ//f8A9dzXc3+7b2/5oE1MTF1SOR4ETQmtNH+nd74Ga+a/0bkSGYMP9L/2h XHL+eXivbOt4LU1/WjKVU9BgmzyeoOcTKsQKWT0S+6dtE5ROJdnXb3RzM00nwPpW 8e5SdgPLnNz0D+G1pyV6EntoRpBibddtlCFgl5uCNkV7NcpdnjjTHZwGdo21EucP bEFWTVaTmfYBp67OQtHvTW+vWpkfueovj5hhOvicjIRqZ2qpqEwk6rcPDvk5zass ASvH6E9MYlw1wwwlZresqKKk5aunStwaacft/cO2/FkTKZBSDkrYDcCBfGnRfrV+ 5yFYrqpc3/9ODdWWZndOnEFE9DC9R/reegkj05qL74lQZ525c9MZdmur6m0FzJW+ IGtJaphmpyywUGXJgjl4pfP4r/2g8rEC/peCLkP+4IjfpjXV5bcADis6U7Zith4C BX5HYZNnxYFr6HDB1LzlQrH/csBipDinSQsQqSMgl0c3KDP+Hdx0buQ/zn/Wwh6W 691zG2YMb1NJouNFZzOR2X5rkC4XZn9JRlQu0SAh7LTomwbJnnXWy41umkU2cCdR 29lizLyaTjP3whNO9np0UNBcUyESJ/xNCI/F5BRDCuMDOSyS/apLio+aOlDpGSuf dkK2ysaPWz76a0VlO4EpUAagMeifOCBXmAjVIq09RUuS6VRgyUc= =7UWe -----END PGP SIGNATURE----- --n8g4imXOkfNTN/H1-- From MAILER-DAEMON Thu Dec 19 17:54:57 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1ii4h7-0003bd-GW for mharc-qemu-arm@gnu.org; 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Thu, 19 Dec 2019 17:54:32 -0500 X-MC-Unique: hLHPCOmKOSOMh7M0vxkLVA-1 Received: from smtp.corp.redhat.com (int-mx04.intmail.prod.int.phx2.redhat.com [10.5.11.14]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx01.redhat.com (Postfix) with ESMTPS id D5C57800EB8; Thu, 19 Dec 2019 22:54:30 +0000 (UTC) Received: from localhost.localdomain (ovpn-116-70.gru2.redhat.com [10.97.116.70]) by smtp.corp.redhat.com (Postfix) with ESMTPS id C42A95D9E2; Thu, 19 Dec 2019 22:54:28 +0000 (UTC) Date: Thu, 19 Dec 2019 17:54:25 -0500 From: Cleber Rosa To: Niek Linnenbank Cc: Philippe =?iso-8859-1?Q?Mathieu-Daud=E9?= , QEMU Developers , Guenter Roeck , Peter Maydell , qemu-arm Subject: Re: [RFC PATCH 5/5] tests/boot_linux_console: Add a SLOW test booting Ubuntu on OrangePi PC Message-ID: <20191219225425.GB28892@localhost.localdomain> References: <20191217182730.943-1-f4bug@amsat.org> <20191217182730.943-6-f4bug@amsat.org> MIME-Version: 1.0 In-Reply-To: X-Scanned-By: MIMEDefang 2.79 on 10.5.11.14 X-Mimecast-Spam-Score: 0 Content-Type: multipart/signed; micalg=pgp-sha256; protocol="application/pgp-signature"; boundary="dc+cDN39EJAMEtIO" Content-Disposition: inline X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 205.139.110.61 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 19 Dec 2019 22:54:55 -0000 --dc+cDN39EJAMEtIO Content-Type: text/plain; charset=iso-8859-1 Content-Disposition: inline Content-Transfer-Encoding: quoted-printable On Wed, Dec 18, 2019 at 10:26:08PM +0100, Niek Linnenbank wrote: > Hi Philippe, >=20 > This test has some problems on my host (Ubuntu 18.04.3 LTS, avocado 73.0, > python 3.6.9): >=20 > (4/4) tests/acceptance/boot_linux_console.py:BootLinuxConsole.test_arm_o= rangepi_bionic: > ERROR: Input format not supported by decoder (3.25 s) > RESULTS : PASS 3 | ERROR 1 | FAIL 0 | SKIP 0 | WARN 0 | INTERRUPT 0 > | CANCEL 0 > JOB TIME : 46.22 s >=20 > I suspect it didn't download the image correctly. > I don't think it's download related, because the "archive.lzma_uncompress(image_path_xz, image_path)" line is not capable of uncompressing that 7z archive. > Regards, > Niek >=20 > On Tue, Dec 17, 2019 at 7:27 PM Philippe Mathieu-Daud=E9 > wrote: >=20 > > This test boots Ubuntu Bionic on a OrangePi PC board. > > > > As it requires 1GB of storage, and is slow, this test is disabled > > on automatic CI testing. > > > > It is useful for workstation testing. Currently Avocado timeouts too > > quickly, so we can't run userland commands. > > > > The kernel image and DeviceTree blob are built by the Raspbian > > project (based on Debian): > > https://www.raspbian.org/RaspbianImages > > > > The Ubuntu image is downloaded from: > > https://dl.armbian.com/orangepipc/Bionic_current > > > > This test can be run using: > > > > $ AVOCADO_ALLOW_LARGE_STORAGE=3Dyes \ > > avocado --show=3Dapp,console run -t machine:orangepi-pc \ > > tests/acceptance/boot_linux_console.py > > console: Uncompressing Linux... done, booting the kernel. > > console: Booting Linux on physical CPU 0x0 > > console: Linux version 4.20.7-sunxi (root@armbian.com) (gcc version > > 7.2.1 20171011 (Linaro GCC 7.2-2017.11)) #5.75 SMP Fri Feb 8 09:02:10 C= ET > > 2019 > > console: CPU: ARMv7 Processor [410fc075] revision 5 (ARMv7), cr=3D50c= 5387d > > console: CPU: div instructions available: patching division code > > console: CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing > > instruction cache > > console: OF: fdt: Machine model: Xunlong Orange Pi PC > > [...] > > console: sunxi-mmc 1c0f000.mmc: initialized, max. request size: 16384= KB > > console: NET: Registered protocol family 10 > > console: mmc0: host does not support reading read-only switch, assumi= ng > > write-enable > > console: mmc0: Problem switching card into high-speed mode! > > console: mmc0: new SD card at address 4567 > > console: mmcblk0: mmc0:4567 QEMU! 932 MiB > > console: Segment Routing with IPv6 > > console: NET: Registered protocol family 17 > > console: NET: Registered protocol family 15 > > console: bridge: filtering via arp/ip/ip6tables is no longer availabl= e > > by default. Update your scripts to load br_netfilter if you need this. > > console: 8021q: 802.1Q VLAN Support v1.8 > > console: Key type dns_resolver registered > > console: Registering SWP/SWPB emulation handler > > console: mmcblk0: p1 > > [...] > > console: Freeing unused kernel memory: 1024K > > console: Run /sbin/init as init process > > console: random: fast init done > > console: systemd[1]: System time before build time, advancing clock. > > console: systemd[1]: systemd 237 running in system mode. (+PAM +AUDIT > > +SELINUX +IMA +APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT > > +GNUTLS +ACL +XZ +LZ4 +SECCOMP +BLKID +ELFUTILS +KMOD -IDN2 +IDN -PCRE2 > > default-hierarchy=3Dhybrid) > > console: systemd[1]: Detected architecture arm. > > console: Welcome to Ubuntu 18.04.3 LTS! > > console: systemd[1]: Set hostname to . > > console: random: systemd: uninitialized urandom read (16 bytes read) > > > > Signed-off-by: Philippe Mathieu-Daud=E9 > > --- > > RFC because this is not the definitive test, but it is helpful so > > for for testing Niek work. > > --- > > tests/acceptance/boot_linux_console.py | 41 ++++++++++++++++++++++++++ > > 1 file changed, 41 insertions(+) > > > > diff --git a/tests/acceptance/boot_linux_console.py > > b/tests/acceptance/boot_linux_console.py > > index 8179b45910..663290e0c7 100644 > > --- a/tests/acceptance/boot_linux_console.py > > +++ b/tests/acceptance/boot_linux_console.py > > @@ -520,6 +520,47 @@ class BootLinuxConsole(Test): > > exec_command_and_wait_for_pattern(self, 'reboot', > > 'reboot: Restarting > > system') > > > > + @skipUnless(os.getenv('AVOCADO_ALLOW_LARGE_STORAGE'), 'storage > > limited') > > + def test_arm_orangepi_bionic(self): > > + """ > > + :avocado: tags=3Darch:arm > > + :avocado: tags=3Dmachine:orangepi-pc > > + """ > > + # This test download a 196MB compressed image and expand it to > > 932MB... > > + deb_url =3D ('https://apt.armbian.com/pool/main/l/' > > + > > 'linux-4.20.7-sunxi/linux-image-dev-sunxi_5.75_armhf.deb') > > + deb_hash =3D '1334c29c44d984ffa05ed10de8c3361f33d78315' > > + deb_path =3D self.fetch_asset(deb_url, asset_hash=3Ddeb_hash) > > + kernel_path =3D self.extract_from_deb(deb_path, > > + '/boot/vmlinuz-4.20.7-sunx= i') > > + dtb_path =3D > > '/usr/lib/linux-image-dev-sunxi/sun8i-h3-orangepi-pc.dtb' > > + dtb_path =3D self.extract_from_deb(deb_path, dtb_path) > > + image_url =3D ('https://dl.armbian.com/orangepipc/archive/' > > + 'Armbian_19.11.3_Orangepipc_bionic_current_5.3.9.= 7z') > > + image_hash =3D '196a8ffb72b0123d92cea4a070894813d305c71e' > > + image_path_xz =3D self.fetch_asset(image_url, asset_hash=3Dima= ge_hash) > > + image_name =3D 'Armbian_19.11.3_Orangepipc_bionic_current_5.3.= 9.img' > > + image_path =3D os.path.join(self.workdir, image_name) > > + archive.lzma_uncompress(image_path_xz, image_path) I'm not sure what magic Philippe was able to do here, but I can not uncompress this file with lzma_uncompress. I'm looking into adding proper 7z support to avocado.utils.archive module, by means of either the 7z library or the py7zr Python module. - Cleber. > > + > > + self.vm.set_machine('orangepi-pc') > > + self.vm.set_console() > > + kernel_command_line =3D (self.KERNEL_COMMON_COMMAND_LINE + > > + 'console=3DttyS0,115200 ' > > + 'root=3D/dev/mmcblk0p1 rootwait rw ' > > + 'systemd.mask=3Ddev-ttyS0.device ' > > + 'systemd.mask=3Darmbian-zram-config.ser= vice ' > > + 'systemd.mask=3Darmbian-ramlog.service'= ) > > + self.vm.add_args('-kernel', kernel_path, > > + '-dtb', dtb_path, > > + '-drive', 'file=3D' + image_path + > > ',if=3Dsd,format=3Draw', > > + '-append', kernel_command_line, > > + '-nic', 'user', > > + '-no-reboot') > > + self.vm.launch() > > + self.wait_for_console_pattern('Welcome to Ubuntu 18.04.3 LTS!'= ) > > + self.wait_for_console_pattern('Started Armbian filesystem > > resize.') > > + > > def test_s390x_s390_ccw_virtio(self): > > """ > > :avocado: tags=3Darch:s390x > > -- > > 2.21.0 > > > > >=20 > --=20 > Niek Linnenbank --dc+cDN39EJAMEtIO Content-Type: application/pgp-signature; name="signature.asc" -----BEGIN PGP SIGNATURE----- iQIzBAEBCAAdFiEEeruW64tGuU1eD+m7ZX6NM6XyCfMFAl37/54ACgkQZX6NM6Xy CfMEvQ/+PsiPjMkjihxXJCuq45EIl8L+BOQhHzZ/wEO3GJZFg/Isq4w3BSlwgf5C W3HZU7BC0nPIZ7SCyQF7wq39Y9+8KiziiM0TxtgOs3UhR9JsFCZNu5RAXND36Tkn oWuq0WTneYTFXsCTlVzTxXwQfCaMYzbO+m699oE561EN91OL61uQqlq1pV/MpVKm lTyuNIR4ssyO7mtH/IF+EiFbLzN+XefyhzxCLmFChbRcmobn3CGuwdec7oHu9V5o FkJfAkOHtR6WuVS6DdYyymSHQmMwJjwzuWqJIBrFVikLNaoV0lxeoOxSUHPBrgtC iy61IqHEuJWT4JnKoVAff8ciS8t8vt2VMbs/f4ijSVj0N40bkxnQghJwDVrDCSZ0 NSZN2ezS+OnpgnMJFCfqyuHOxBbhmSlf4VApxrdxd/phEmHvaAnz8QhfUDWPLNhO BQ99C2+EDm+Mah9i+vndO4fYjNRgyhaQF2ro4++31cHunEUFODnV5OkKzlgfo7gf unAs/cjHEt10lND+Mqdoq7smc/zwnN1SU3u3xsdlRGjiT+mUSGuszl3sS4mpVbcR BDYBA/r2PR+e/iH8IPBKljRIcDpmXqswmj0tGKqBq0HjXGsY4CHph1nrRf3mD2Ml nJrbqA/FjHRJZv6+26Bvu5H3J29PoFi/H58Ur+waz3u+Vim5CUQ= =0fgK -----END PGP SIGNATURE----- --dc+cDN39EJAMEtIO-- From MAILER-DAEMON Fri Dec 20 01:59:34 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1iiCG6-0004n1-5T for mharc-qemu-arm@gnu.org; Fri, 20 Dec 2019 01:59:34 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:58591) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iiCG1-0004mc-Qw for qemu-arm@nongnu.org; Fri, 20 Dec 2019 01:59:31 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1iiCG0-0005Dx-4A for qemu-arm@nongnu.org; Fri, 20 Dec 2019 01:59:29 -0500 Received: from szxga07-in.huawei.com ([45.249.212.35]:42154 helo=huawei.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1iiCFz-0004kK-KR; Fri, 20 Dec 2019 01:59:27 -0500 Received: from DGGEMS413-HUB.china.huawei.com (unknown [172.30.72.60]) by Forcepoint Email with ESMTP id 9298DCC466B9D8C9D7BB; Fri, 20 Dec 2019 14:59:16 +0800 (CST) Received: from [127.0.0.1] (10.173.222.27) by DGGEMS413-HUB.china.huawei.com (10.3.19.213) with Microsoft SMTP Server id 14.3.439.0; Fri, 20 Dec 2019 14:59:09 +0800 Subject: Re: [kvm-unit-tests PATCH 06/16] arm/arm64: ITS: Test BASER To: Eric Auger , , , , , , CC: , , , , References: <20191216140235.10751-1-eric.auger@redhat.com> <20191216140235.10751-7-eric.auger@redhat.com> From: Zenghui Yu Message-ID: <172f58d7-5a7c-43e0-c647-a7935f5d4b43@huawei.com> Date: Fri, 20 Dec 2019 14:59:07 +0800 User-Agent: Mozilla/5.0 (Windows NT 10.0; WOW64; rv:68.0) Gecko/20100101 Thunderbird/68.2.0 MIME-Version: 1.0 In-Reply-To: <20191216140235.10751-7-eric.auger@redhat.com> Content-Type: text/plain; charset="utf-8"; format=flowed Content-Language: en-US Content-Transfer-Encoding: 7bit X-Originating-IP: [10.173.222.27] X-CFilter-Loop: Reflected X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 45.249.212.35 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 20 Dec 2019 06:59:31 -0000 Hi Eric, On 2019/12/16 22:02, Eric Auger wrote: > Add helper routines to parse and set up BASER registers. > Add a new test dedicated to BASER accesses. > > Signed-off-by: Eric Auger > --- > arm/gic.c | 20 ++++++++++ > arm/unittests.cfg | 6 +++ > lib/arm/asm/gic-v3-its.h | 17 ++++++++ > lib/arm/gic-v3-its.c | 84 ++++++++++++++++++++++++++++++++++++++++ > 4 files changed, 127 insertions(+) > > diff --git a/arm/gic.c b/arm/gic.c > index adeb981..8b56fce 100644 > --- a/arm/gic.c > +++ b/arm/gic.c > @@ -536,6 +536,22 @@ static void test_its_introspection(void) > typer->pta ? "Redist basse address" : "PE #"); > } > > +static void test_its_baser(void) > +{ > + struct its_baser *dev_baser, *coll_baser; > + > + if (!gicv3_its_base()) { > + report_skip("No ITS, skip ..."); > + return; > + } > + > + dev_baser = its_lookup_baser(GITS_BASER_TYPE_DEVICE); > + coll_baser = its_lookup_baser(GITS_BASER_TYPE_COLLECTION); > + report(dev_baser && coll_baser, "detect device and collection BASER"); > + report_info("device baser entry_size = 0x%x", dev_baser->esz); > + report_info("collection baser entry_size = 0x%x", dev_baser->esz); s/dev_baser/coll_baser/ > +} > + > int main(int argc, char **argv) > { > if (!gic_init()) { > @@ -571,6 +587,10 @@ int main(int argc, char **argv) > report_prefix_push(argv[1]); > test_its_introspection(); > report_prefix_pop(); > + } else if (strcmp(argv[1], "its-baser") == 0) { > + report_prefix_push(argv[1]); > + test_its_baser(); > + report_prefix_pop(); > } else { > report_abort("Unknown subtest '%s'", argv[1]); > } > diff --git a/arm/unittests.cfg b/arm/unittests.cfg > index bd20460..2234a0f 100644 > --- a/arm/unittests.cfg > +++ b/arm/unittests.cfg > @@ -128,6 +128,12 @@ smp = $MAX_SMP > extra_params = -machine gic-version=3 -append 'its-introspection' > groups = its > > +[its-baser] > +file = gic.flat > +smp = $MAX_SMP > +extra_params = -machine gic-version=3 -append 'its-baser' > +groups = its > + > # Test PSCI emulation > [psci] > file = psci.flat > diff --git a/lib/arm/asm/gic-v3-its.h b/lib/arm/asm/gic-v3-its.h > index 2ce483e..0c0178d 100644 > --- a/lib/arm/asm/gic-v3-its.h > +++ b/lib/arm/asm/gic-v3-its.h > @@ -100,9 +100,23 @@ struct its_typer { > bool virt_lpi; > }; > > +struct its_baser { > + unsigned int index; We've already maintained an array of GITS_BASERs, so 'index' is not needed. > + int type; > + u64 cache; > + int shr; > + size_t psz; > + int nr_pages; > + bool indirect; > + phys_addr_t table_addr; > + bool valid; > + int esz; > +}; > + > struct its_data { > void *base; > struct its_typer typer; > + struct its_baser baser[GITS_BASER_NR_REGS]; > }; > > extern struct its_data its_data; > @@ -111,6 +125,9 @@ extern struct its_data its_data; > > extern void its_parse_typer(void); > extern void its_init(void); > +extern int its_parse_baser(int i, struct its_baser *baser); > +extern void its_setup_baser(int i, struct its_baser *baser); > +extern struct its_baser *its_lookup_baser(int type); > > #endif /* !__ASSEMBLY__ */ > #endif /* _ASMARM_GIC_V3_ITS_H_ */ > diff --git a/lib/arm/gic-v3-its.c b/lib/arm/gic-v3-its.c > index 34f4d0e..303022f 100644 > --- a/lib/arm/gic-v3-its.c > +++ b/lib/arm/gic-v3-its.c > @@ -4,6 +4,7 @@ > * This work is licensed under the terms of the GNU LGPL, version 2. > */ > #include > +#include > > struct its_data its_data; > > @@ -31,11 +32,94 @@ void its_parse_typer(void) > its_data.typer.phys_lpi = typer & GITS_TYPER_PLPIS; > } > > +int its_parse_baser(int i, struct its_baser *baser) > +{ > + void *reg_addr = gicv3_its_base() + GITS_BASER + i * 8; > + u64 val = readq(reg_addr); > + > + if (!val) { > + memset(baser, 0, sizeof(*baser)); > + return -1; > + } > + > + baser->valid = val & GITS_BASER_VALID; > + baser->indirect = val & GITS_BASER_INDIRECT; > + baser->type = GITS_BASER_TYPE(val); > + baser->esz = GITS_BASER_ENTRY_SIZE(val); > + baser->nr_pages = GITS_BASER_NR_PAGES(val); > + baser->table_addr = val & GITS_BASER_PHYS_ADDR_MASK; > + baser->cache = (val >> GITS_BASER_INNER_CACHEABILITY_SHIFT) & > + GITS_BASER_CACHEABILITY_MASK; > + switch (val & GITS_BASER_PAGE_SIZE_MASK) { > + case GITS_BASER_PAGE_SIZE_4K: > + baser->psz = SZ_4K; > + break; > + case GITS_BASER_PAGE_SIZE_16K: > + baser->psz = SZ_16K; > + break; > + case GITS_BASER_PAGE_SIZE_64K: > + baser->psz = SZ_64K; > + break; > + default: > + baser->psz = SZ_64K; > + } > + baser->shr = (val >> 10) & 0x3; > + return 0; > +} > + > +struct its_baser *its_lookup_baser(int type) > +{ > + int i; > + > + for (i = 0; i < GITS_BASER_NR_REGS; i++) { > + struct its_baser *baser = &its_data.baser[i]; > + > + if (baser->type == type) > + return baser; > + } > + return NULL; > +} > + > void its_init(void) > { > + int i; Please add a blank line here. > if (!its_data.base) > return; > > its_parse_typer(); > + for (i = 0; i < GITS_BASER_NR_REGS; i++) > + its_parse_baser(i, &its_data.baser[i]); > +} > + > +void its_setup_baser(int i, struct its_baser *baser) > +{ > + unsigned long n = (baser->nr_pages * baser->psz) >> PAGE_SHIFT; > + unsigned long order = is_power_of_2(n) ? fls(n) : fls(n) + 1; > + u64 val; > + > + baser->table_addr = (u64)virt_to_phys(alloc_pages(order)); > + > + val = ((u64)baser->table_addr | > + ((u64)baser->type << GITS_BASER_TYPE_SHIFT) | > + ((u64)(baser->esz - 1) << GITS_BASER_ENTRY_SIZE_SHIFT) | > + ((baser->nr_pages - 1) << GITS_BASER_PAGES_SHIFT) | > + baser->cache | > + baser->shr | baser->cache << GITS_BASER_INNER_CACHEABILITY_SHIFT | baser->shr << 10 (GITS_BASER_SHAREABILITY_SHIFT) ? Thanks, Zenghui > + (u64)baser->indirect << 62 | > + (u64)baser->valid << 63); > + > + switch (baser->psz) { > + case SZ_4K: > + val |= GITS_BASER_PAGE_SIZE_4K; > + break; > + case SZ_16K: > + val |= GITS_BASER_PAGE_SIZE_16K; > + break; > + case SZ_64K: > + val |= GITS_BASER_PAGE_SIZE_64K; > + break; > + } > + > + writeq(val, gicv3_its_base() + GITS_BASER + i * 8); > } > > From MAILER-DAEMON Fri Dec 20 02:10:48 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1iiCQy-0000Rz-OV for mharc-qemu-arm@gnu.org; Fri, 20 Dec 2019 02:10:48 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:43695) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iiCQw-0000PP-9O for qemu-arm@nongnu.org; Fri, 20 Dec 2019 02:10:47 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1iiCQu-0000sf-Rf for qemu-arm@nongnu.org; Fri, 20 Dec 2019 02:10:45 -0500 Received: from szxga05-in.huawei.com ([45.249.212.191]:2280 helo=huawei.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1iiCQu-0000Xc-8m; Fri, 20 Dec 2019 02:10:44 -0500 Received: from DGGEMS414-HUB.china.huawei.com (unknown [172.30.72.58]) by Forcepoint Email with ESMTP id 2F8FC377EBD1CE8A33B3; Fri, 20 Dec 2019 15:10:39 +0800 (CST) Received: from [127.0.0.1] (10.173.222.27) by DGGEMS414-HUB.china.huawei.com (10.3.19.214) with Microsoft SMTP Server id 14.3.439.0; Fri, 20 Dec 2019 15:10:31 +0800 Subject: Re: [kvm-unit-tests PATCH 08/16] arm/arm64: ITS: Init the command queue To: Eric Auger , , , , , , CC: , , , , References: <20191216140235.10751-1-eric.auger@redhat.com> <20191216140235.10751-9-eric.auger@redhat.com> From: Zenghui Yu Message-ID: <37c8b078-900b-a474-04a0-0273c3a32aed@huawei.com> Date: Fri, 20 Dec 2019 15:10:29 +0800 User-Agent: Mozilla/5.0 (Windows NT 10.0; WOW64; rv:68.0) Gecko/20100101 Thunderbird/68.2.0 MIME-Version: 1.0 In-Reply-To: <20191216140235.10751-9-eric.auger@redhat.com> Content-Type: text/plain; charset="utf-8"; format=flowed Content-Language: en-US Content-Transfer-Encoding: 7bit X-Originating-IP: [10.173.222.27] X-CFilter-Loop: Reflected X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 45.249.212.191 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 20 Dec 2019 07:10:47 -0000 Hi Eric, On 2019/12/16 22:02, Eric Auger wrote: > Allocate the command queue and initialize related registers: > CBASER, CREADR, CWRITER. > > The command queue is 64kB. This aims at not bothing with fullness. > > Signed-off-by: Eric Auger > --- > lib/arm/asm/gic-v3-its.h | 7 +++++++ > lib/arm/gic-v3-its.c | 37 +++++++++++++++++++++++++++++++++++++ > 2 files changed, 44 insertions(+) > > diff --git a/lib/arm/asm/gic-v3-its.h b/lib/arm/asm/gic-v3-its.h > index 0d11aed..ed42707 100644 > --- a/lib/arm/asm/gic-v3-its.h > +++ b/lib/arm/asm/gic-v3-its.h > @@ -113,10 +113,17 @@ struct its_baser { > int esz; > }; > > +struct its_cmd_block { > + u64 raw_cmd[4]; > +}; > + > struct its_data { > void *base; > struct its_typer typer; > struct its_baser baser[GITS_BASER_NR_REGS]; > + struct its_cmd_block *cmd_base; > + struct its_cmd_block *cmd_write; > + struct its_cmd_block *cmd_readr; I think we can just get rid of the 'cmd_readr'. As GITS_CREADR is generally manipulated by the ITS, and ... > }; > > extern struct its_data its_data; > diff --git a/lib/arm/gic-v3-its.c b/lib/arm/gic-v3-its.c > index 0b5a700..8b6a095 100644 > --- a/lib/arm/gic-v3-its.c > +++ b/lib/arm/gic-v3-its.c > @@ -188,3 +188,40 @@ void set_pending_table_bit(int rdist, int n, bool set) > byte &= ~mask; > *ptr = byte; > } > + > +/** > + * init_cmd_queue: Allocate the command queue and initialize > + * CBASER, CREADR, CWRITER > + */ > +void init_cmd_queue(void); > +void init_cmd_queue(void) > +{ > + unsigned long n = SZ_64K >> PAGE_SHIFT; > + unsigned long order = fls(n); > + u64 cbaser, tmp; > + > + its_data.cmd_base = (void *)virt_to_phys(alloc_pages(order)); > + > + cbaser = ((u64)its_data.cmd_base | > + GITS_CBASER_WaWb | > + GITS_CBASER_InnerShareable | > + (SZ_64K / SZ_4K - 1) | > + GITS_CBASER_VALID); > + > + writeq(cbaser, its_data.base + GITS_CBASER); ..."(CREADR) is cleared to 0 when a value is written to GITS_CBASER." -- from IHI0069E 9.19.3 > + tmp = readq(its_data.base + GITS_CBASER); > + > + if ((tmp ^ cbaser) & GITS_CBASER_SHAREABILITY_MASK) { > + if (!(tmp & GITS_CBASER_SHAREABILITY_MASK)) { > + cbaser &= ~(GITS_CBASER_SHAREABILITY_MASK | > + GITS_CBASER_CACHEABILITY_MASK); > + cbaser |= GITS_CBASER_nC; > + writeq(cbaser, its_data.base + GITS_CBASER); > + } > + } > + > + its_data.cmd_write = its_data.cmd_base; > + its_data.cmd_readr = its_data.cmd_base; > + writeq(0, its_data.base + GITS_CWRITER); > + writeq(0, its_data.base + GITS_CREADR); So this writeq() is also not needed. Or I've just missed the point that this is done by intention to test "whether the GITS_CREADR implemented by KVM is Write Ignored"? If so, please ignore all of the comments above :) Thanks, Zenghui From MAILER-DAEMON Fri Dec 20 02:25:54 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1iiCfY-0005EQ-SJ for mharc-qemu-arm@gnu.org; Fri, 20 Dec 2019 02:25:53 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:42317) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iiCfV-0005EG-BF for qemu-arm@nongnu.org; Fri, 20 Dec 2019 02:25:50 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1iiCfT-0006e2-Nb for qemu-arm@nongnu.org; Fri, 20 Dec 2019 02:25:48 -0500 Received: from szxga04-in.huawei.com ([45.249.212.190]:2225 helo=huawei.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1iiCfT-0006GT-69; Fri, 20 Dec 2019 02:25:47 -0500 Received: from DGGEMS408-HUB.china.huawei.com (unknown [172.30.72.60]) by Forcepoint Email with ESMTP id CC1CB548BD8CEBBBEDAE; Fri, 20 Dec 2019 15:25:41 +0800 (CST) Received: from [127.0.0.1] (10.173.222.27) by DGGEMS408-HUB.china.huawei.com (10.3.19.208) with Microsoft SMTP Server id 14.3.439.0; Fri, 20 Dec 2019 15:25:33 +0800 Subject: Re: [kvm-unit-tests PATCH 11/16] arm/arm64: ITS: Device and collection Initialization To: Eric Auger , , , , , , CC: , , , , References: <20191216140235.10751-1-eric.auger@redhat.com> <20191216140235.10751-12-eric.auger@redhat.com> From: Zenghui Yu Message-ID: <1f170d74-0ee5-6415-d84e-cd7de4d0f071@huawei.com> Date: Fri, 20 Dec 2019 15:25:30 +0800 User-Agent: Mozilla/5.0 (Windows NT 10.0; WOW64; rv:68.0) Gecko/20100101 Thunderbird/68.2.0 MIME-Version: 1.0 In-Reply-To: <20191216140235.10751-12-eric.auger@redhat.com> Content-Type: text/plain; charset="utf-8"; format=flowed Content-Language: en-US Content-Transfer-Encoding: 7bit X-Originating-IP: [10.173.222.27] X-CFilter-Loop: Reflected X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 45.249.212.190 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 20 Dec 2019 07:25:50 -0000 Hi Eric, On 2019/12/16 22:02, Eric Auger wrote: > Introduce an helper functions to register > - a new device, characterized by its device id and the > max number of event IDs that dimension its ITT (Interrupt > Translation Table). The function allocates the ITT. > > - a new collection, characterized by its ID and the > target processing engine (PE). > > Signed-off-by: Eric Auger > > --- > --- > lib/arm/asm/gic-v3-its.h | 20 +++++++++++++++++ > lib/arm/gic-v3-its.c | 46 ++++++++++++++++++++++++++++++++++++++++ > 2 files changed, 66 insertions(+) > > diff --git a/lib/arm/asm/gic-v3-its.h b/lib/arm/asm/gic-v3-its.h > index ab639c5..245ef61 100644 > --- a/lib/arm/asm/gic-v3-its.h > +++ b/lib/arm/asm/gic-v3-its.h > @@ -87,6 +87,9 @@ > > #define ITS_FLAGS_CMDQ_NEEDS_FLUSHING (1ULL << 0) > > +#define GITS_MAX_DEVICES 8 > +#define GITS_MAX_COLLECTIONS 8 > + > struct its_typer { > unsigned int ite_size; > unsigned int eventid_bits; > @@ -117,6 +120,17 @@ struct its_cmd_block { > u64 raw_cmd[4]; > }; > > +struct its_device { > + u32 device_id; /* device ID */ > + u32 nr_ites; /* Max Interrupt Translation Entries */ > + void *itt; /* Interrupt Translation Table GPA */ > +}; > + > +struct its_collection { > + u64 target_address; > + u16 col_id; > +}; > + > struct its_data { > void *base; > struct its_typer typer; > @@ -124,6 +138,10 @@ struct its_data { > struct its_cmd_block *cmd_base; > struct its_cmd_block *cmd_write; > struct its_cmd_block *cmd_readr; > + struct its_device devices[GITS_MAX_DEVICES]; > + u32 nb_devices; /* Allocated Devices */ > + struct its_collection collections[GITS_MAX_COLLECTIONS]; > + u32 nb_collections; /* Allocated Collections */ ('nr_*' may be the more widely used one.) > }; > > extern struct its_data its_data; > @@ -140,6 +158,8 @@ extern u8 get_lpi_config(int n); > extern void set_pending_table_bit(int rdist, int n, bool set); > extern void gicv3_rdist_ctrl_lpi(u32 redist, bool set); > extern void its_enable_defaults(void); > +extern struct its_device *its_create_device(u32 dev_id, int nr_ites); > +extern struct its_collection *its_create_collection(u32 col_id, u32 target_pe); > > #endif /* !__ASSEMBLY__ */ > #endif /* _ASMARM_GIC_V3_ITS_H_ */ > diff --git a/lib/arm/gic-v3-its.c b/lib/arm/gic-v3-its.c > index 9a51ef4..9906428 100644 > --- a/lib/arm/gic-v3-its.c > +++ b/lib/arm/gic-v3-its.c > @@ -284,3 +284,49 @@ void its_enable_defaults(void) > > writel(GITS_CTLR_ENABLE, its_data.base + GITS_CTLR); > } > + > +struct its_device *its_create_device(u32 device_id, int nr_ites) > +{ > + struct its_baser *baser; > + struct its_device *new; > + unsigned long n, order; > + > + if (its_data.nb_devices >= GITS_MAX_DEVICES) > + report_abort("%s redimension GITS_MAX_DEVICES", __func__); > + > + baser = its_lookup_baser(GITS_BASER_TYPE_DEVICE); > + if (!baser) > + return NULL; > + > + new = &its_data.devices[its_data.nb_devices]; > + > + new->device_id = device_id; > + new->nr_ites = nr_ites; > + > + n = (baser->esz * nr_ites) >> PAGE_SHIFT; baser->esz is GITS_BASER.Entry_Size, which indicates the size of Device Table entry. We're allocating ITT for this device now, shouldn't we use its_data.typer.esz? Thanks, Zenghui > + order = is_power_of_2(n) ? fls(n) : fls(n) + 1; > + new->itt = (void *)virt_to_phys(alloc_pages(order)); > + > + its_data.nb_devices++; > + return new; > +} > + > +struct its_collection *its_create_collection(u32 col_id, u32 pe) > +{ > + struct its_collection *new; > + > + if (its_data.nb_collections >= GITS_MAX_COLLECTIONS) > + report_abort("%s redimension GITS_MAX_COLLECTIONS", __func__); > + > + new = &its_data.collections[its_data.nb_collections]; > + > + new->col_id = col_id; > + > + if (its_data.typer.pta) > + new->target_address = (u64)gicv3_data.redist_base[pe]; > + else > + new->target_address = pe << 16; > + > + its_data.nb_collections++; > + return new; > +} > From MAILER-DAEMON Fri Dec 20 02:29:38 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1iiCjC-0007PB-CD for mharc-qemu-arm@gnu.org; Fri, 20 Dec 2019 02:29:38 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:48076) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iiCjA-0007Oq-FF for qemu-arm@nongnu.org; Fri, 20 Dec 2019 02:29:37 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1iiCj8-0003Dl-Dn for qemu-arm@nongnu.org; Fri, 20 Dec 2019 02:29:35 -0500 Received: from szxga06-in.huawei.com ([45.249.212.32]:51698 helo=huawei.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1iiCj5-00039h-2i; Fri, 20 Dec 2019 02:29:32 -0500 Received: from DGGEMS412-HUB.china.huawei.com (unknown [172.30.72.58]) by Forcepoint Email with ESMTP id 7EF0A9E8FB0866428E41; Fri, 20 Dec 2019 15:29:27 +0800 (CST) Received: from [127.0.0.1] (10.173.222.27) by DGGEMS412-HUB.china.huawei.com (10.3.19.212) with Microsoft SMTP Server id 14.3.439.0; Fri, 20 Dec 2019 15:29:16 +0800 Subject: Re: [kvm-unit-tests PATCH 12/16] arm/arm64: ITS: commands To: Eric Auger , , , , , , CC: , , , , References: <20191216140235.10751-1-eric.auger@redhat.com> <20191216140235.10751-13-eric.auger@redhat.com> From: Zenghui Yu Message-ID: Date: Fri, 20 Dec 2019 15:29:15 +0800 User-Agent: Mozilla/5.0 (Windows NT 10.0; WOW64; rv:68.0) Gecko/20100101 Thunderbird/68.2.0 MIME-Version: 1.0 In-Reply-To: <20191216140235.10751-13-eric.auger@redhat.com> Content-Type: text/plain; charset="utf-8"; format=flowed Content-Language: en-US Content-Transfer-Encoding: 7bit X-Originating-IP: [10.173.222.27] X-CFilter-Loop: Reflected X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 45.249.212.32 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 20 Dec 2019 07:29:37 -0000 Hi Eric, On 2019/12/16 22:02, Eric Auger wrote: > Implement main ITS commands. The code is largely inherited from > the ITS driver. > > Signed-off-by: Eric Auger > --- [...] > diff --git a/lib/arm/asm/gic-v3-its.h b/lib/arm/asm/gic-v3-its.h > index 245ef61..d074c17 100644 > --- a/lib/arm/asm/gic-v3-its.h > +++ b/lib/arm/asm/gic-v3-its.h > @@ -161,5 +179,23 @@ extern void its_enable_defaults(void); > extern struct its_device *its_create_device(u32 dev_id, int nr_ites); > extern struct its_collection *its_create_collection(u32 col_id, u32 target_pe); > > +extern void its_send_mapd(struct its_device *dev, int valid); > +extern void its_send_mapc(struct its_collection *col, int valid); > +extern void its_send_mapti(struct its_device *dev, u32 irq_id, > + u32 event_id, struct its_collection *col); > +extern void its_send_int(struct its_device *dev, u32 event_id); > +extern void its_send_inv(struct its_device *dev, u32 event_id); > +extern void its_send_discard(struct its_device *dev, u32 event_id); > +extern void its_send_clear(struct its_device *dev, u32 event_id); > +extern void its_send_invall(struct its_collection *col); > +extern void its_send_movi(struct its_device *dev, > + struct its_collection *col, u32 id); > +extern void its_send_sync(struct its_collection *col); > +extern void its_print_cmd_state(void); This function is not used by later patches, I guess it's mostly used for debug. (Assuming the Linux ITS driver has done the right thing ;-), I just skip looking at this patch.) Thanks, Zenghui From MAILER-DAEMON Fri Dec 20 02:34:38 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1iiCo2-00020i-EC for mharc-qemu-arm@gnu.org; Fri, 20 Dec 2019 02:34:38 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:53761) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iiCo0-0001ti-0I for qemu-arm@nongnu.org; Fri, 20 Dec 2019 02:34:36 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1iiCny-00009r-QY for qemu-arm@nongnu.org; Fri, 20 Dec 2019 02:34:35 -0500 Received: from szxga04-in.huawei.com ([45.249.212.190]:2226 helo=huawei.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1iiCny-0008IH-Ay; Fri, 20 Dec 2019 02:34:34 -0500 Received: from DGGEMS408-HUB.china.huawei.com (unknown [172.30.72.60]) by Forcepoint Email with ESMTP id 3DF20FFEDCEF0B4DF2E7; Fri, 20 Dec 2019 15:34:29 +0800 (CST) Received: from [127.0.0.1] (10.173.222.27) by DGGEMS408-HUB.china.huawei.com (10.3.19.208) with Microsoft SMTP Server id 14.3.439.0; Fri, 20 Dec 2019 15:34:22 +0800 Subject: Re: [kvm-unit-tests PATCH 05/16] arm/arm64: ITS: Introspection tests To: Auger Eric , , , , , , CC: , , , , References: <20191216140235.10751-1-eric.auger@redhat.com> <20191216140235.10751-6-eric.auger@redhat.com> <6542297b-74d2-f3c2-63d8-04bb284414df@redhat.com> From: Zenghui Yu Message-ID: Date: Fri, 20 Dec 2019 15:34:21 +0800 User-Agent: Mozilla/5.0 (Windows NT 10.0; WOW64; rv:68.0) Gecko/20100101 Thunderbird/68.2.0 MIME-Version: 1.0 In-Reply-To: <6542297b-74d2-f3c2-63d8-04bb284414df@redhat.com> Content-Type: text/plain; charset="utf-8"; format=flowed Content-Language: en-US Content-Transfer-Encoding: 7bit X-Originating-IP: [10.173.222.27] X-CFilter-Loop: Reflected X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 45.249.212.190 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 20 Dec 2019 07:34:37 -0000 On 2019/12/18 16:34, Auger Eric wrote: > Hi Zenghui, > > On 12/18/19 4:46 AM, Zenghui Yu wrote: >> Hi Eric, >> >> I have to admit that this is the first time I've looked into >> the kvm-unit-tests code, so only some minor comments inline :) > > no problem. Thank you for looking at this. > > By the way, with patch 16 I was able to test yout fix: "KVM: arm/arm64: > vgic: Don't rely on the wrong pending table". Reverting it produced an > error. which is great! Thanks for your work! Zenghui From MAILER-DAEMON Fri Dec 20 07:05:05 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1iiH1l-0004tI-3k for mharc-qemu-arm@gnu.org; Fri, 20 Dec 2019 07:05:05 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:53574) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iiH1f-0004qT-1r for qemu-arm@nongnu.org; Fri, 20 Dec 2019 07:05:03 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1iiH1Z-0007ql-L0 for qemu-arm@nongnu.org; Fri, 20 Dec 2019 07:04:58 -0500 Received: from mail-wm1-x343.google.com ([2a00:1450:4864:20::343]:54025) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1iiH1Y-0007k6-IY for qemu-arm@nongnu.org; Fri, 20 Dec 2019 07:04:52 -0500 Received: by mail-wm1-x343.google.com with SMTP id m24so8676915wmc.3 for ; Fri, 20 Dec 2019 04:04:52 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=yP04C6ThOAXjLefYFBP1Rp4bmt2cBEv6NwVmKqtKkDw=; b=LuPL37ZAkEEmEi+yqJ9WADzmqnLZrz+RJ1ojuwkeqTFWjZWglfHrlUo+yK37mRjyZ0 uHIir3/Jqn78UzcjUndn5Dw4i4rDuovNnUx/XgHE6FGoCZEqX3Arh6JLtcbTr5tmFQG5 SKAj2i6eGnLxfltMBbkJF4Vnboz5XMFC5EyBKkorUm016VRyd2n5d1Z+Kx9HSGZjoJId WolhnPylDDM/imY+lIo2y/AAJKdfo+TwTDgKBEFZy4rEFNEpXDwRjmq+zrnaZSMMvag0 lP14JfWmS/CWyFwt0nZwkPI9vPzT81ub4r78E2S7+TR0TIkqU4gK+JzJlf65b2kZXCE6 Qsrw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=yP04C6ThOAXjLefYFBP1Rp4bmt2cBEv6NwVmKqtKkDw=; b=etV6gbMipPuAD/+yOcFkNK8Y6HsA92VZO3XHs3MvnYWPO3HZyV0zojZkloJFlxs6Gi bbwAGoLOCQIVZ86iGX5IbJH6u4h7uDfhbvbHBnxrU9SUUsjl7Uuj/dKJ5cBQFsAjf6er 0tVjD3Vn5qbaF5dKjso8E3ZkKLa6e5+bmvZMLQn/F/vSuAQg7+iSPKWpVPV00iLlNeJU nZ2LKUbDXVwc2hIW9hUAB7krwHlnTz4EDCgNr2589B0EbSP72n1qUVJCKquGEKvC3vp/ wEIPrashtJKsvJSfoUGntyKUNyvKVPCH9XiTJCxVfdmXuz8y2Q5Tpb0/ougkL2t2ozKA KUrw== X-Gm-Message-State: APjAAAX4myzYMC4+RoOgC8Y8qFWkh65PrqELHtwx8cp9thfk6aaMHEF8 xMdRG0d90G3XnE5UiibpfNAkjA== X-Google-Smtp-Source: APXvYqyvumcnFZnL/JzZ9GcYtuAspnT5f62Y+tBwsLNxOJYXcjvMrNznje1K7Sso/vTenmXWRmlVrA== X-Received: by 2002:a1c:e108:: with SMTP id y8mr15629231wmg.147.1576843491069; Fri, 20 Dec 2019 04:04:51 -0800 (PST) Received: from zen.linaroharston ([51.148.130.216]) by smtp.gmail.com with ESMTPSA id m7sm9462105wrr.40.2019.12.20.04.04.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 20 Dec 2019 04:04:46 -0800 (PST) Received: from zen.lan (localhost [127.0.0.1]) by zen.linaroharston (Postfix) with ESMTP id 6B5541FF93; Fri, 20 Dec 2019 12:04:39 +0000 (GMT) From: =?UTF-8?q?Alex=20Benn=C3=A9e?= To: qemu-devel@nongnu.org Cc: alan.hayward@arm.com, luis.machado@linaro.org, damien.hedde@greensocs.com, =?UTF-8?q?Alex=20Benn=C3=A9e?= , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Richard Henderson , Peter Maydell , qemu-arm@nongnu.org (open list:ARM TCG CPUs) Subject: [PATCH v4 06/21] target/arm: use gdb_get_reg helpers Date: Fri, 20 Dec 2019 12:04:23 +0000 Message-Id: <20191220120438.16114-7-alex.bennee@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20191220120438.16114-1-alex.bennee@linaro.org> References: <20191220120438.16114-1-alex.bennee@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::343 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 20 Dec 2019 12:05:04 -0000 This is cleaner than poking memory directly and will make later clean-ups easier. Signed-off-by: Alex Bennée Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson --- v2 - make sure we pass hi/lo correctly as quads are stored in LE order --- target/arm/helper.c | 18 +++++++----------- 1 file changed, 7 insertions(+), 11 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 5074b5f69ca..6f3b6ca7d3f 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -105,21 +105,17 @@ static int aarch64_fpu_gdb_get_reg(CPUARMState *env, uint8_t *buf, int reg) { switch (reg) { case 0 ... 31: - /* 128 bit FP register */ - { - uint64_t *q = aa64_vfp_qreg(env, reg); - stq_le_p(buf, q[0]); - stq_le_p(buf + 8, q[1]); - return 16; - } + { + /* 128 bit FP register - quads are in LE order */ + uint64_t *q = aa64_vfp_qreg(env, reg); + return gdb_get_reg128(buf, q[1], q[0]); + } case 32: /* FPSR */ - stl_p(buf, vfp_get_fpsr(env)); - return 4; + return gdb_get_reg32(buf, vfp_get_fpsr(env)); case 33: /* FPCR */ - stl_p(buf, vfp_get_fpcr(env)); - return 4; + return gdb_get_reg32(buf,vfp_get_fpcr(env)); default: return 0; } -- 2.20.1 From MAILER-DAEMON Fri Dec 20 07:05:07 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1iiH1n-0004w3-Aa for mharc-qemu-arm@gnu.org; Fri, 20 Dec 2019 07:05:07 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:53714) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iiH1j-0004rr-Vo for qemu-arm@nongnu.org; Fri, 20 Dec 2019 07:05:05 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1iiH1e-000885-3J for qemu-arm@nongnu.org; Fri, 20 Dec 2019 07:04:59 -0500 Received: from mail-wr1-x441.google.com ([2a00:1450:4864:20::441]:38696) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1iiH1d-00084r-PK for qemu-arm@nongnu.org; Fri, 20 Dec 2019 07:04:57 -0500 Received: by mail-wr1-x441.google.com with SMTP id y17so9206871wrh.5 for ; Fri, 20 Dec 2019 04:04:57 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=czanuspGcHlKRukvMkLTGjn1x611kvgV7PuFbsiK1Pk=; b=zf7pxHfwzEDlsgRvDI3Gpj1CcG5uUIUIUl+xMsUxnlOyJB36nmqqsRU13tXmumM6wE ermA5ztZ5EUFjEwiltk/zFWK3SlxhyX9NJsWvpHaE8oHnMt5cXPwt5jie6ltUhWb7nIN NE8ASZTwlhjYp94hG0KAiDQ5YFbGwqN8KzMUmh9z1U/0rkyZVVunc4wcXd+DMOxg97F1 u/Vi0PHP0FMuyTN7kpVMfztgcnollB369IYvxO+giX790Q/vYNln4EyPNbdnDXLnc7FR xsyHzvmM3OV5qSpFFTJQ0yzREZTUR5eTaOk2YiJecv5szmGQf3N3yJ+QyDRQNsFKwIgW KSCA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=czanuspGcHlKRukvMkLTGjn1x611kvgV7PuFbsiK1Pk=; b=hftaN6jL22BObDCAwtkGaZp0p4Kl6z26uFycGoCfxWNS1+6tDIrOMKEFXZxf++cHNL bpjhtzxFvs95RC74blI5cMORvxzw6s2/Yp7HYOLaF2C2kKgo3ohA7xc+puaGGQtltVSB wEaeokeC1IhNMp0p1y+kUaA0ev6/z908+ccUi0GGew4lh9bHkZl8ilzJWDYsObPbMBTJ iPyL+AaAJfJGsVmm2/fJFSm2qsuEW6kxTolXmfnqfEOABirMTDkcgspfML2GRuo93Amb 7joOjOXy8A0OZP4qt0nH9/sDalb9+E89xwXUoxlLfcxu6hXehsJCkpENs/btaIt3loo4 tnhA== X-Gm-Message-State: APjAAAViC14WIlzb27wdCFSrjaltFocau98tpt9zAulibKLJE7UKIaS6 idkOx9nf6cC1kgjm5pzB0nwzdg== X-Google-Smtp-Source: APXvYqwW8fe0/xNziM0ZOCOgjAW9iOuK8v7BwY08j3wDMTtO7/hIhiK820+uRKoDbduZ354IXct4Yw== X-Received: by 2002:a5d:690e:: with SMTP id t14mr14764377wru.65.1576843496579; Fri, 20 Dec 2019 04:04:56 -0800 (PST) Received: from zen.linaroharston ([51.148.130.216]) by smtp.gmail.com with ESMTPSA id v22sm8994211wml.11.2019.12.20.04.04.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 20 Dec 2019 04:04:48 -0800 (PST) Received: from zen.lan (localhost [127.0.0.1]) by zen.linaroharston (Postfix) with ESMTP id 00A051FF99; Fri, 20 Dec 2019 12:04:40 +0000 (GMT) From: =?UTF-8?q?Alex=20Benn=C3=A9e?= To: qemu-devel@nongnu.org Cc: alan.hayward@arm.com, luis.machado@linaro.org, damien.hedde@greensocs.com, =?UTF-8?q?Alex=20Benn=C3=A9e?= , Peter Maydell , qemu-arm@nongnu.org (open list:ARM TCG CPUs) Subject: [PATCH v4 09/21] target/arm: prepare for multiple dynamic XMLs Date: Fri, 20 Dec 2019 12:04:26 +0000 Message-Id: <20191220120438.16114-10-alex.bennee@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20191220120438.16114-1-alex.bennee@linaro.org> References: <20191220120438.16114-1-alex.bennee@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::441 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 20 Dec 2019 12:05:06 -0000 We will want to generate similar dynamic XML for gdbstub support of SVE registers (the upstream doesn't use XML). To that end lightly rename a few things to make the distinction. Signed-off-by: Alex Bennée --- target/arm/cpu.h | 20 +++++++++++++------- target/arm/gdbstub.c | 30 +++++++++++++++--------------- target/arm/helper.c | 4 ++-- 3 files changed, 30 insertions(+), 24 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 19b3ac32113..59d5dbae31f 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -128,14 +128,20 @@ enum { /** * DynamicGDBXMLInfo: * @desc: Contains the XML descriptions. - * @num_cpregs: Number of the Coprocessor registers seen by GDB. - * @cpregs_keys: Array that contains the corresponding Key of - * a given cpreg with the same order of the cpreg in the XML description. + * @num: Number of the registers in this XML seen by GDB. + * @data: A union with data specific to the set of registers + * @cpregs_keys: Array that contains the corresponding Key of + * a given cpreg with the same order of the cpreg + * in the XML description. */ typedef struct DynamicGDBXMLInfo { char *desc; - int num_cpregs; - uint32_t *cpregs_keys; + int num; + union { + struct { + uint32_t *keys; + } cpregs; + } data; } DynamicGDBXMLInfo; /* CPU state for each instance of a generic timer (in cp15 c14) */ @@ -748,7 +754,7 @@ struct ARMCPU { uint64_t *cpreg_vmstate_values; int32_t cpreg_vmstate_array_len; - DynamicGDBXMLInfo dyn_xml; + DynamicGDBXMLInfo dyn_sysreg_xml; /* Timers used by the generic (architected) timer */ QEMUTimer *gt_timer[NUM_GTIMERS]; @@ -955,7 +961,7 @@ int arm_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); /* Dynamically generates for gdb stub an XML description of the sysregs from * the cp_regs hashtable. Returns the registered sysregs number. */ -int arm_gen_dynamic_xml(CPUState *cpu); +int arm_gen_dynamic_sysreg_xml(CPUState *cpu); /* Returns the dynamically generated XML for the gdb stub. * Returns a pointer to the XML contents for the specified XML file or NULL diff --git a/target/arm/gdbstub.c b/target/arm/gdbstub.c index 4557775d245..1f68ab98c3b 100644 --- a/target/arm/gdbstub.c +++ b/target/arm/gdbstub.c @@ -106,15 +106,15 @@ int arm_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n) return 0; } -static void arm_gen_one_xml_reg_tag(GString *s, DynamicGDBXMLInfo *dyn_xml, - ARMCPRegInfo *ri, uint32_t ri_key, - int bitsize) +static void arm_gen_one_xml_sysreg_tag(GString *s, DynamicGDBXMLInfo *dyn_xml, + ARMCPRegInfo *ri, uint32_t ri_key, + int bitsize) { g_string_append_printf(s, "name); g_string_append_printf(s, " bitsize=\"%d\"", bitsize); g_string_append_printf(s, " group=\"cp_regs\"/>"); - dyn_xml->num_cpregs++; - dyn_xml->cpregs_keys[dyn_xml->num_cpregs - 1] = ri_key; + dyn_xml->data.cpregs.keys[dyn_xml->num] = ri_key; + dyn_xml->num++; } static void arm_register_sysreg_for_xml(gpointer key, gpointer value, @@ -126,12 +126,12 @@ static void arm_register_sysreg_for_xml(gpointer key, gpointer value, GString *s = param->s; ARMCPU *cpu = ARM_CPU(param->cs); CPUARMState *env = &cpu->env; - DynamicGDBXMLInfo *dyn_xml = &cpu->dyn_xml; + DynamicGDBXMLInfo *dyn_xml = &cpu->dyn_sysreg_xml; if (!(ri->type & (ARM_CP_NO_RAW | ARM_CP_NO_GDB))) { if (arm_feature(env, ARM_FEATURE_AARCH64)) { if (ri->state == ARM_CP_STATE_AA64) { - arm_gen_one_xml_reg_tag(s , dyn_xml, ri, ri_key, 64); + arm_gen_one_xml_sysreg_tag(s , dyn_xml, ri, ri_key, 64); } } else { if (ri->state == ARM_CP_STATE_AA32) { @@ -140,30 +140,30 @@ static void arm_register_sysreg_for_xml(gpointer key, gpointer value, return; } if (ri->type & ARM_CP_64BIT) { - arm_gen_one_xml_reg_tag(s , dyn_xml, ri, ri_key, 64); + arm_gen_one_xml_sysreg_tag(s , dyn_xml, ri, ri_key, 64); } else { - arm_gen_one_xml_reg_tag(s , dyn_xml, ri, ri_key, 32); + arm_gen_one_xml_sysreg_tag(s , dyn_xml, ri, ri_key, 32); } } } } } -int arm_gen_dynamic_xml(CPUState *cs) +int arm_gen_dynamic_sysreg_xml(CPUState *cs) { ARMCPU *cpu = ARM_CPU(cs); GString *s = g_string_new(NULL); RegisterSysregXmlParam param = {cs, s}; - cpu->dyn_xml.num_cpregs = 0; - cpu->dyn_xml.cpregs_keys = g_new(uint32_t, g_hash_table_size(cpu->cp_regs)); + cpu->dyn_sysreg_xml.num = 0; + cpu->dyn_sysreg_xml.data.cpregs.keys = g_new(uint32_t, g_hash_table_size(cpu->cp_regs)); g_string_printf(s, ""); g_string_append_printf(s, ""); g_string_append_printf(s, ""); g_hash_table_foreach(cpu->cp_regs, arm_register_sysreg_for_xml, ¶m); g_string_append_printf(s, ""); - cpu->dyn_xml.desc = g_string_free(s, false); - return cpu->dyn_xml.num_cpregs; + cpu->dyn_sysreg_xml.desc = g_string_free(s, false); + return cpu->dyn_sysreg_xml.num; } const char *arm_gdb_get_dynamic_xml(CPUState *cs, const char *xmlname) @@ -171,7 +171,7 @@ const char *arm_gdb_get_dynamic_xml(CPUState *cs, const char *xmlname) ARMCPU *cpu = ARM_CPU(cs); if (strcmp(xmlname, "system-registers.xml") == 0) { - return cpu->dyn_xml.desc; + return cpu->dyn_sysreg_xml.desc; } return NULL; } diff --git a/target/arm/helper.c b/target/arm/helper.c index 36872627a5d..0a3bc53124e 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -207,7 +207,7 @@ static int arm_gdb_get_sysreg(CPUARMState *env, GByteArray *buf, int reg) const ARMCPRegInfo *ri; uint32_t key; - key = cpu->dyn_xml.cpregs_keys[reg]; + key = cpu->dyn_sysreg_xml.data.cpregs.keys[reg]; ri = get_arm_cp_reginfo(cpu->cp_regs, key); if (ri) { if (cpreg_field_is_64bit(ri)) { @@ -7129,7 +7129,7 @@ void arm_cpu_register_gdb_regs_for_features(ARMCPU *cpu) 19, "arm-vfp.xml", 0); } gdb_register_coprocessor(cs, arm_gdb_get_sysreg, arm_gdb_set_sysreg, - arm_gen_dynamic_xml(cs), + arm_gen_dynamic_sysreg_xml(cs), "system-registers.xml", 0); } -- 2.20.1 From MAILER-DAEMON Fri Dec 20 07:05:09 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1iiH1p-0004yf-FH for mharc-qemu-arm@gnu.org; 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Fri, 20 Dec 2019 04:04:48 -0800 (PST) Received: from zen.lan (localhost [127.0.0.1]) by zen.linaroharston (Postfix) with ESMTP id 1760C1FF9A; Fri, 20 Dec 2019 12:04:40 +0000 (GMT) From: =?UTF-8?q?Alex=20Benn=C3=A9e?= To: qemu-devel@nongnu.org Cc: alan.hayward@arm.com, luis.machado@linaro.org, damien.hedde@greensocs.com, =?UTF-8?q?Alex=20Benn=C3=A9e?= , Richard Henderson , Peter Maydell , qemu-arm@nongnu.org (open list:ARM TCG CPUs) Subject: [PATCH v4 10/21] target/arm: explicitly encode regnum in our XML Date: Fri, 20 Dec 2019 12:04:27 +0000 Message-Id: <20191220120438.16114-11-alex.bennee@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20191220120438.16114-1-alex.bennee@linaro.org> References: <20191220120438.16114-1-alex.bennee@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::443 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 20 Dec 2019 12:05:07 -0000 This is described as optional but I'm not convinced of the numbering when multiple target fragments are sent. Signed-off-by: Alex Bennée Reviewed-by: Richard Henderson --- v2 - post inc param->n in place so we don't get out count wrong --- target/arm/cpu.h | 2 +- target/arm/gdbstub.c | 17 +++++++++++------ target/arm/helper.c | 2 +- 3 files changed, 13 insertions(+), 8 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 59d5dbae31f..40591b5dc70 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -961,7 +961,7 @@ int arm_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); /* Dynamically generates for gdb stub an XML description of the sysregs from * the cp_regs hashtable. Returns the registered sysregs number. */ -int arm_gen_dynamic_sysreg_xml(CPUState *cpu); +int arm_gen_dynamic_sysreg_xml(CPUState *cpu, int base_reg); /* Returns the dynamically generated XML for the gdb stub. * Returns a pointer to the XML contents for the specified XML file or NULL diff --git a/target/arm/gdbstub.c b/target/arm/gdbstub.c index 1f68ab98c3b..69c35462a63 100644 --- a/target/arm/gdbstub.c +++ b/target/arm/gdbstub.c @@ -24,6 +24,7 @@ typedef struct RegisterSysregXmlParam { CPUState *cs; GString *s; + int n; } RegisterSysregXmlParam; /* Old gdb always expect FPA registers. Newer (xml-aware) gdb only expect @@ -108,10 +109,11 @@ int arm_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n) static void arm_gen_one_xml_sysreg_tag(GString *s, DynamicGDBXMLInfo *dyn_xml, ARMCPRegInfo *ri, uint32_t ri_key, - int bitsize) + int bitsize, int regnum) { g_string_append_printf(s, "name); g_string_append_printf(s, " bitsize=\"%d\"", bitsize); + g_string_append_printf(s, " regnum=\"%d\"", regnum); g_string_append_printf(s, " group=\"cp_regs\"/>"); dyn_xml->data.cpregs.keys[dyn_xml->num] = ri_key; dyn_xml->num++; @@ -131,7 +133,8 @@ static void arm_register_sysreg_for_xml(gpointer key, gpointer value, if (!(ri->type & (ARM_CP_NO_RAW | ARM_CP_NO_GDB))) { if (arm_feature(env, ARM_FEATURE_AARCH64)) { if (ri->state == ARM_CP_STATE_AA64) { - arm_gen_one_xml_sysreg_tag(s , dyn_xml, ri, ri_key, 64); + arm_gen_one_xml_sysreg_tag(s , dyn_xml, ri, ri_key, 64, + param->n++); } } else { if (ri->state == ARM_CP_STATE_AA32) { @@ -140,20 +143,22 @@ static void arm_register_sysreg_for_xml(gpointer key, gpointer value, return; } if (ri->type & ARM_CP_64BIT) { - arm_gen_one_xml_sysreg_tag(s , dyn_xml, ri, ri_key, 64); + arm_gen_one_xml_sysreg_tag(s , dyn_xml, ri, ri_key, 64, + param->n++); } else { - arm_gen_one_xml_sysreg_tag(s , dyn_xml, ri, ri_key, 32); + arm_gen_one_xml_sysreg_tag(s , dyn_xml, ri, ri_key, 32, + param->n++); } } } } } -int arm_gen_dynamic_sysreg_xml(CPUState *cs) +int arm_gen_dynamic_sysreg_xml(CPUState *cs, int base_reg) { ARMCPU *cpu = ARM_CPU(cs); GString *s = g_string_new(NULL); - RegisterSysregXmlParam param = {cs, s}; + RegisterSysregXmlParam param = {cs, s, base_reg}; cpu->dyn_sysreg_xml.num = 0; cpu->dyn_sysreg_xml.data.cpregs.keys = g_new(uint32_t, g_hash_table_size(cpu->cp_regs)); diff --git a/target/arm/helper.c b/target/arm/helper.c index 0a3bc53124e..488fdbf61a9 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -7129,7 +7129,7 @@ void arm_cpu_register_gdb_regs_for_features(ARMCPU *cpu) 19, "arm-vfp.xml", 0); } gdb_register_coprocessor(cs, arm_gdb_get_sysreg, arm_gdb_set_sysreg, - arm_gen_dynamic_sysreg_xml(cs), + arm_gen_dynamic_sysreg_xml(cs, cs->gdb_num_regs), "system-registers.xml", 0); } -- 2.20.1 From MAILER-DAEMON Fri Dec 20 07:05:18 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1iiH1x-00056S-M9 for mharc-qemu-arm@gnu.org; Fri, 20 Dec 2019 07:05:18 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:54213) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iiH1r-00051I-Te for qemu-arm@nongnu.org; Fri, 20 Dec 2019 07:05:14 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1iiH1p-0008Ph-3R for qemu-arm@nongnu.org; Fri, 20 Dec 2019 07:05:11 -0500 Received: from mail-wr1-x436.google.com ([2a00:1450:4864:20::436]:36017) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1iiH1n-0008Mu-Oe for qemu-arm@nongnu.org; Fri, 20 Dec 2019 07:05:08 -0500 Received: by mail-wr1-x436.google.com with SMTP id z3so9200173wru.3 for ; Fri, 20 Dec 2019 04:05:07 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; 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Fri, 20 Dec 2019 04:05:05 -0800 (PST) Received: from zen.linaroharston ([51.148.130.216]) by smtp.gmail.com with ESMTPSA id s128sm9713941wme.39.2019.12.20.04.04.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 20 Dec 2019 04:04:53 -0800 (PST) Received: from zen.lan (localhost [127.0.0.1]) by zen.linaroharston (Postfix) with ESMTP id AF5D61FFA5; Fri, 20 Dec 2019 12:04:40 +0000 (GMT) From: =?UTF-8?q?Alex=20Benn=C3=A9e?= To: qemu-devel@nongnu.org Cc: alan.hayward@arm.com, luis.machado@linaro.org, damien.hedde@greensocs.com, =?UTF-8?q?Alex=20Benn=C3=A9e?= , Peter Maydell , qemu-arm@nongnu.org (open list:ARM TCG CPUs) Subject: [PATCH v4 17/21] tests/tcg/aarch64: add a gdbstub testcase for SVE registers Date: Fri, 20 Dec 2019 12:04:34 +0000 Message-Id: <20191220120438.16114-18-alex.bennee@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20191220120438.16114-1-alex.bennee@linaro.org> References: <20191220120438.16114-1-alex.bennee@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::436 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 20 Dec 2019 12:05:14 -0000 We don't plumb this in yet as there are complications involved with binutils and cross-architectiure debugging but it is one step closer. Example: ./tests/guest-debug/run-test.py \ --qemu ./aarch64-linux-user/qemu-aarch64 \ --qargs "-cpu max" \ --bin ./tests/tcg/aarch64-linux-user/hello \ --test ~/lsrc/qemu.git/tests/tcg/aarch64/gdbstub/test-sve.py \ --gdb /home/alex/src/tools/binutils-gdb.git/install/bin/gdb Signed-off-by: Alex Bennée --- tests/.gitignore | 1 + tests/tcg/aarch64/gdbstub/test-sve.py | 75 +++++++++++++++++++++++++++ 2 files changed, 76 insertions(+) create mode 100644 tests/tcg/aarch64/gdbstub/test-sve.py diff --git a/tests/.gitignore b/tests/.gitignore index f9c01708812..8cc428b58bb 100644 --- a/tests/.gitignore +++ b/tests/.gitignore @@ -10,6 +10,7 @@ qht-bench rcutorture test-* !test-*.c +!test-*.py !docker/test-* test-qapi-commands.[ch] include/test-qapi-commands-sub-module.[ch] diff --git a/tests/tcg/aarch64/gdbstub/test-sve.py b/tests/tcg/aarch64/gdbstub/test-sve.py new file mode 100644 index 00000000000..11bc96fc06d --- /dev/null +++ b/tests/tcg/aarch64/gdbstub/test-sve.py @@ -0,0 +1,75 @@ +from __future__ import print_function +# +# Test the SVE registers are visable and changeable via gdbstub +# +# This is launched via tests/guest-debug/run-test.py +# + +import gdb + +MAGIC = 0xDEADBEEF + +failcount = 0 + +def report(cond, msg): + "Report success/fail of test" + if cond: + print ("PASS: %s" % (msg)) + else: + print ("FAIL: %s" % (msg)) + global failcount + failcount += 1 + +def run_test(): + "Run through the tests one by one" + + gdb.execute("info registers") + report(True, "info registers") + + gdb.execute("info registers vector") + report(True, "info registers vector") + + # Now all the zregs + frame = gdb.selected_frame() + for i in range(0, 32): + rname = "z%d" % (i) + zreg = frame.read_register(rname) + report(True, "Reading %s" % rname) + for j in range(0, 4): + cmd = "set $%s.q.u[%d] = 0x%x" % (rname, j, MAGIC) + gdb.execute(cmd) + report(True, "%s" % cmd) + for j in range(0, 4): + reg = "$%s.q.u[%d]" % (rname, j) + v = gdb.parse_and_eval(reg) + report(str(v.type) == "uint128_t", "size of %s" % (reg)) + for j in range(0, 8): + cmd = "set $%s.d.u[%d] = 0x%x" % (rname, j, MAGIC) + gdb.execute(cmd) + report(True, "%s" % cmd) + for j in range(0, 8): + reg = "$%s.d.u[%d]" % (rname, j) + v = gdb.parse_and_eval(reg) + report(str(v.type) == "uint64_t", "size of %s" % (reg)) + report(int(v) == MAGIC, "%s is 0x%x" % (reg, MAGIC)) + +# +# This runs as the script it sourced (via -x, via run-test.py) +# + +try: + # These are not very useful in scripts + gdb.execute("set pagination off") + gdb.execute("set confirm off") + + # Run the actual tests + run_test() +except: + print ("GDB Exception: %s" % (sys.exc_info()[0])) + failcount += 1 + +print("All tests complete: %d failures" % failcount) + +# Finally kill the inferior and exit gdb with a count of failures +gdb.execute("kill") +exit(failcount) -- 2.20.1 From MAILER-DAEMON Fri Dec 20 07:05:18 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1iiH1y-00057K-EL for mharc-qemu-arm@gnu.org; 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Fri, 20 Dec 2019 04:04:51 -0800 (PST) Received: from zen.lan (localhost [127.0.0.1]) by zen.linaroharston (Postfix) with ESMTP id 2C4A81FF9B; Fri, 20 Dec 2019 12:04:40 +0000 (GMT) From: =?UTF-8?q?Alex=20Benn=C3=A9e?= To: qemu-devel@nongnu.org Cc: alan.hayward@arm.com, luis.machado@linaro.org, damien.hedde@greensocs.com, =?UTF-8?q?Alex=20Benn=C3=A9e?= , Richard Henderson , Peter Maydell , qemu-arm@nongnu.org (open list:ARM TCG CPUs) Subject: [PATCH v4 11/21] target/arm: default SVE length to 64 bytes for linux-user Date: Fri, 20 Dec 2019 12:04:28 +0000 Message-Id: <20191220120438.16114-12-alex.bennee@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20191220120438.16114-1-alex.bennee@linaro.org> References: <20191220120438.16114-1-alex.bennee@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::344 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 20 Dec 2019 12:05:14 -0000 The Linux kernel chooses the default of 64 bytes for SVE registers on the basis that it is the largest size on known hardware that won't grow the signal frame. We still honour the sve-max-vq property and userspace can expand the number of lanes by calling PR_SVE_SET_VL. This should not make any difference to SVE enabled software as the SVE is of course vector length agnostic. Signed-off-by: Alex Bennée Reviewed-by: Richard Henderson --- v2 - tweak zcr_el[1] instead --- target/arm/cpu.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index dd51adac059..2d2e786245b 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -199,9 +199,9 @@ static void arm_cpu_reset(CPUState *s) /* and to the SVE instructions */ env->cp15.cpacr_el1 = deposit64(env->cp15.cpacr_el1, 16, 2, 3); env->cp15.cptr_el[3] |= CPTR_EZ; - /* with maximum vector length */ + /* with reasonable vector length */ env->vfp.zcr_el[1] = cpu_isar_feature(aa64_sve, cpu) ? - cpu->sve_max_vq - 1 : 0; + MIN(cpu->sve_max_vq - 1, 3) : 0; env->vfp.zcr_el[2] = env->vfp.zcr_el[1]; env->vfp.zcr_el[3] = env->vfp.zcr_el[1]; /* -- 2.20.1 From MAILER-DAEMON Fri Dec 20 07:05:26 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1iiH22-0005DN-Cv for mharc-qemu-arm@gnu.org; Fri, 20 Dec 2019 07:05:26 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:54284) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iiH1s-000520-KM for qemu-arm@nongnu.org; Fri, 20 Dec 2019 07:05:19 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1iiH1l-0008JN-1n for qemu-arm@nongnu.org; Fri, 20 Dec 2019 07:05:11 -0500 Received: from mail-wm1-x341.google.com ([2a00:1450:4864:20::341]:54025) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1iiH1j-0008Fk-TT for qemu-arm@nongnu.org; Fri, 20 Dec 2019 07:05:04 -0500 Received: by mail-wm1-x341.google.com with SMTP id m24so8677479wmc.3 for ; Fri, 20 Dec 2019 04:05:02 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=2Gl3w5dXDGfherWie7OLbv8FKPkn1YuYJp7v+pvZORo=; b=LFMRgoeWys+pvnbQppS+YEGIwEHjaSatO55vdZpNde/OjlaBnTP/yOn7Lf90yFFmHb Ee8iiOHVFuLLg3SvVLG/Q/BMzXaURmiyjaBBSNPVN+jATv0rYZ1VWZ/4HQkkmOFhW+jY xpmqbeXEQ+DMrVNW2AyE4B88/Iu25U7bSNypIJld6YIWeNqJX+PFUbsRMsNZf6HfOn6z u05hAns0bVKuXY4eBk8tJHFrCNncPElZm/xRUnRqQUJOFgs7vdLJLVm2rOSC7YG51/Dj NJp0g4cnVVyi2yKV8ce8sNmW56+WWH9AQh3d9aDqKd1SLyYbPc+muTPFQ56gg74Ih41K h8vA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=2Gl3w5dXDGfherWie7OLbv8FKPkn1YuYJp7v+pvZORo=; b=E1WMB8OdqEnnuPmCTLp9PqESCMA64apQVEgJN6fe35OhdBwqHUSChrYyC712n2yMio aZ0AAxtWp83rNPM4LMQ++8sKnTqANf2Hbj1x0EqgFYOR6PEfPMyBLSIFsweLmHLQ72H9 yOXj/LRUp9t5oskRtdTVPdYc9HzIY4pag1f43kbRUlAoSj4GPV37QincXG+hty7HKixz QN2/jZBVyUYNZ/DkB6v7jSVXBAQ+COK4NV7oe/0mX4MV7lJORIsuvM97rTqUeT2hpmgl wl4N3pJAH5OXVI6xSS3P4QkQL3aZKu63wKZP4wAyfAUh0kBJX5ExVsiQWgLIM2XPyP0m ysUw== X-Gm-Message-State: APjAAAWGl18vkneDxQowFsmRiZG+xPdJWBKS6XZOQBdkG9hfTduhe5GA kOWNFuBK/ZG1qla6T56jCJuNIw== X-Google-Smtp-Source: APXvYqxjXrvhvVExYz5ZSrkSgagoDXlpydAPBsjXoMs8DQ6Bn5Qqu0LX3K5txkplxWF2vLLsm8QuNQ== X-Received: by 2002:a1c:7901:: with SMTP id l1mr15695925wme.67.1576843500868; Fri, 20 Dec 2019 04:05:00 -0800 (PST) Received: from zen.linaroharston ([51.148.130.216]) by smtp.gmail.com with ESMTPSA id n10sm9391168wrt.14.2019.12.20.04.04.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 20 Dec 2019 04:04:48 -0800 (PST) Received: from zen.lan (localhost [127.0.0.1]) by zen.linaroharston (Postfix) with ESMTP id DB0F01FF98; Fri, 20 Dec 2019 12:04:39 +0000 (GMT) From: =?UTF-8?q?Alex=20Benn=C3=A9e?= To: qemu-devel@nongnu.org Cc: alan.hayward@arm.com, luis.machado@linaro.org, damien.hedde@greensocs.com, =?UTF-8?q?Alex=20Benn=C3=A9e?= , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Eduardo Habkost , Marcel Apfelbaum , Richard Henderson , Peter Maydell , "Edgar E. Iglesias" , Paolo Bonzini , Michael Walle , Laurent Vivier , Aurelien Jarno , Aleksandar Markovic , Aleksandar Rikalo , Chris Wulff , Marek Vasut , Stafford Horne , David Gibson , Palmer Dabbelt , Alistair Francis , Sagar Karandikar , Bastian Koppelmann , Cornelia Huck , David Hildenbrand , Mark Cave-Ayland , Artyom Tarasenko , Max Filippov , qemu-arm@nongnu.org (open list:ARM TCG CPUs), qemu-ppc@nongnu.org (open list:PowerPC TCG CPUs), qemu-riscv@nongnu.org (open list:RISC-V TCG CPUs), qemu-s390x@nongnu.org (open list:S390 general arch...) Subject: [PATCH v4 08/21] gdbstub: extend GByteArray to read register helpers Date: Fri, 20 Dec 2019 12:04:25 +0000 Message-Id: <20191220120438.16114-9-alex.bennee@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20191220120438.16114-1-alex.bennee@linaro.org> References: <20191220120438.16114-1-alex.bennee@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::341 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 20 Dec 2019 12:05:20 -0000 Instead of passing a pointer to memory now just extend the GByteArray to all the read register helpers. They can then safely append their data through the normal way. We don't bother with this abstraction for write registers as we have already ensured the buffer being copied from is the correct size. Signed-off-by: Alex Bennée --- v4 - fix mem_buf calculation for ppc_maybe_bswap_register --- include/exec/gdbstub.h | 46 +++++++++++++++++----------- include/hw/core/cpu.h | 2 +- target/alpha/cpu.h | 2 +- target/arm/cpu.h | 4 +-- target/cris/cpu.h | 4 +-- target/hppa/cpu.h | 2 +- target/i386/cpu.h | 2 +- target/lm32/cpu.h | 2 +- target/m68k/cpu.h | 2 +- target/microblaze/cpu.h | 2 +- target/mips/internal.h | 2 +- target/openrisc/cpu.h | 2 +- target/ppc/cpu.h | 4 +-- target/riscv/cpu.h | 2 +- target/s390x/internal.h | 2 +- target/sh4/cpu.h | 2 +- target/sparc/cpu.h | 2 +- target/xtensa/cpu.h | 2 +- gdbstub.c | 20 ++++++------ hw/core/cpu.c | 2 +- target/alpha/gdbstub.c | 2 +- target/arm/gdbstub.c | 2 +- target/arm/gdbstub64.c | 2 +- target/arm/helper.c | 19 +++++------- target/cris/gdbstub.c | 4 +-- target/hppa/gdbstub.c | 2 +- target/i386/gdbstub.c | 2 +- target/lm32/gdbstub.c | 2 +- target/m68k/gdbstub.c | 2 +- target/m68k/helper.c | 4 +-- target/microblaze/gdbstub.c | 2 +- target/mips/gdbstub.c | 2 +- target/nios2/cpu.c | 2 +- target/openrisc/gdbstub.c | 2 +- target/ppc/gdbstub.c | 48 +++++++++++++++-------------- target/ppc/translate_init.inc.c | 54 ++++++++++++++++++--------------- target/riscv/gdbstub.c | 18 +++++------ target/s390x/gdbstub.c | 30 +++++++++--------- target/sh4/gdbstub.c | 2 +- target/sparc/gdbstub.c | 2 +- target/xtensa/gdbstub.c | 2 +- 41 files changed, 165 insertions(+), 148 deletions(-) diff --git a/include/exec/gdbstub.h b/include/exec/gdbstub.h index 59e366ba3af..ef79e32708c 100644 --- a/include/exec/gdbstub.h +++ b/include/exec/gdbstub.h @@ -68,49 +68,59 @@ void gdb_signalled(CPUArchState *, int); void gdbserver_fork(CPUState *); #endif /* Get or set a register. Returns the size of the register. */ -typedef int (*gdb_reg_cb)(CPUArchState *env, uint8_t *buf, int reg); +typedef int (*gdb_get_reg_cb)(CPUArchState *env, GByteArray *buf, int reg); +typedef int (*gdb_set_reg_cb)(CPUArchState *env, uint8_t *buf, int reg); void gdb_register_coprocessor(CPUState *cpu, - gdb_reg_cb get_reg, gdb_reg_cb set_reg, + gdb_get_reg_cb get_reg, gdb_set_reg_cb set_reg, int num_regs, const char *xml, int g_pos); -/* The GDB remote protocol transfers values in target byte order. This means - * we can use the raw memory access routines to access the value buffer. - * Conveniently, these also handle the case where the buffer is mis-aligned. +/* + * The GDB remote protocol transfers values in target byte order. As + * the gdbstub may be batching up several register values we always + * append to the array. */ -static inline int gdb_get_reg8(uint8_t *mem_buf, uint8_t val) +static inline int gdb_get_reg8(GByteArray *buf, uint8_t val) { - stb_p(mem_buf, val); + g_byte_array_append(buf, &val, 1); return 1; } -static inline int gdb_get_reg16(uint8_t *mem_buf, uint16_t val) +static inline int gdb_get_reg16(GByteArray *buf, uint16_t val) { - stw_p(mem_buf, val); + uint16_t to_word = tswap16(val); + g_byte_array_append(buf, (uint8_t *) &to_word, 2); return 2; } -static inline int gdb_get_reg32(uint8_t *mem_buf, uint32_t val) +static inline int gdb_get_reg32(GByteArray *buf, uint32_t val) { - stl_p(mem_buf, val); + uint32_t to_long = tswap32(val); + g_byte_array_append(buf, (uint8_t *) &to_long, 4); return 4; } -static inline int gdb_get_reg64(uint8_t *mem_buf, uint64_t val) +static inline int gdb_get_reg64(GByteArray *buf, uint64_t val) { - stq_p(mem_buf, val); + uint64_t to_quad = tswap64(val); + g_byte_array_append(buf, (uint8_t *) &to_quad, 8); return 8; } -static inline int gdb_get_reg128(uint8_t *mem_buf, uint64_t val_hi, +static inline int gdb_get_reg128(GByteArray *buf, uint64_t val_hi, uint64_t val_lo) { + uint64_t to_quad; #ifdef TARGET_WORDS_BIGENDIAN - stq_p(mem_buf, val_hi); - stq_p(mem_buf + 8, val_lo); + to_quad = tswap64(val_hi); + g_byte_array_append(buf, (uint8_t *) &to_quad, 8); + to_quad = tswap64(val_lo); + g_byte_array_append(buf, (uint8_t *) &to_quad, 8); #else - stq_p(mem_buf, val_lo); - stq_p(mem_buf + 8, val_hi); + to_quad = tswap64(val_lo); + g_byte_array_append(buf, (uint8_t *) &to_quad, 8); + to_quad = tswap64(val_hi); + g_byte_array_append(buf, (uint8_t *) &to_quad, 8); #endif return 16; } diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h index 77c6f052990..e85ec519add 100644 --- a/include/hw/core/cpu.h +++ b/include/hw/core/cpu.h @@ -195,7 +195,7 @@ typedef struct CPUClass { hwaddr (*get_phys_page_attrs_debug)(CPUState *cpu, vaddr addr, MemTxAttrs *attrs); int (*asidx_from_attrs)(CPUState *cpu, MemTxAttrs attrs); - int (*gdb_read_register)(CPUState *cpu, uint8_t *buf, int reg); + int (*gdb_read_register)(CPUState *cpu, GByteArray *buf, int reg); int (*gdb_write_register)(CPUState *cpu, uint8_t *buf, int reg); bool (*debug_check_watchpoint)(CPUState *cpu, CPUWatchpoint *wp); void (*debug_excp_handler)(CPUState *cpu); diff --git a/target/alpha/cpu.h b/target/alpha/cpu.h index a530249a5bf..faa09768424 100644 --- a/target/alpha/cpu.h +++ b/target/alpha/cpu.h @@ -282,7 +282,7 @@ void alpha_cpu_do_interrupt(CPUState *cpu); bool alpha_cpu_exec_interrupt(CPUState *cpu, int int_req); void alpha_cpu_dump_state(CPUState *cs, FILE *f, int flags); hwaddr alpha_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); -int alpha_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg); +int alpha_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); int alpha_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); void alpha_cpu_do_unaligned_access(CPUState *cpu, vaddr addr, MMUAccessType access_type, diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 5f70e9e0438..19b3ac32113 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -949,7 +949,7 @@ bool arm_cpu_exec_interrupt(CPUState *cpu, int int_req); hwaddr arm_cpu_get_phys_page_attrs_debug(CPUState *cpu, vaddr addr, MemTxAttrs *attrs); -int arm_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg); +int arm_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); int arm_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); /* Dynamically generates for gdb stub an XML description of the sysregs from @@ -969,7 +969,7 @@ int arm_cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cs, int cpuid, void *opaque); #ifdef TARGET_AARCH64 -int aarch64_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg); +int aarch64_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); int aarch64_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); void aarch64_sve_narrow_vq(CPUARMState *env, unsigned vq); void aarch64_sve_change_el(CPUARMState *env, int old_el, diff --git a/target/cris/cpu.h b/target/cris/cpu.h index aba0a664744..333ee5b171a 100644 --- a/target/cris/cpu.h +++ b/target/cris/cpu.h @@ -194,8 +194,8 @@ void cris_cpu_dump_state(CPUState *cs, FILE *f, int flags); hwaddr cris_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); -int crisv10_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg); -int cris_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg); +int crisv10_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); +int cris_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); int cris_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); /* you can call this signal handler from your SIGBUS and SIGSEGV diff --git a/target/hppa/cpu.h b/target/hppa/cpu.h index 6713d04f111..801a4fb1bae 100644 --- a/target/hppa/cpu.h +++ b/target/hppa/cpu.h @@ -321,7 +321,7 @@ void cpu_hppa_change_prot_id(CPUHPPAState *env); int cpu_hppa_signal_handler(int host_signum, void *pinfo, void *puc); hwaddr hppa_cpu_get_phys_page_debug(CPUState *cs, vaddr addr); -int hppa_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg); +int hppa_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); int hppa_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); void hppa_cpu_do_interrupt(CPUState *cpu); bool hppa_cpu_exec_interrupt(CPUState *cpu, int int_req); diff --git a/target/i386/cpu.h b/target/i386/cpu.h index af282936a78..63b0031c5bf 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -1760,7 +1760,7 @@ void x86_cpu_dump_state(CPUState *cs, FILE *f, int flags); hwaddr x86_cpu_get_phys_page_attrs_debug(CPUState *cpu, vaddr addr, MemTxAttrs *attrs); -int x86_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg); +int x86_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); int x86_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); void x86_cpu_exec_enter(CPUState *cpu); diff --git a/target/lm32/cpu.h b/target/lm32/cpu.h index 064c6b1267e..01d408eb55d 100644 --- a/target/lm32/cpu.h +++ b/target/lm32/cpu.h @@ -202,7 +202,7 @@ void lm32_cpu_do_interrupt(CPUState *cpu); bool lm32_cpu_exec_interrupt(CPUState *cs, int int_req); void lm32_cpu_dump_state(CPUState *cpu, FILE *f, int flags); hwaddr lm32_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); -int lm32_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg); +int lm32_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); int lm32_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); typedef enum { diff --git a/target/m68k/cpu.h b/target/m68k/cpu.h index 20de3c379aa..cdb08c269f6 100644 --- a/target/m68k/cpu.h +++ b/target/m68k/cpu.h @@ -168,7 +168,7 @@ void m68k_cpu_do_interrupt(CPUState *cpu); bool m68k_cpu_exec_interrupt(CPUState *cpu, int int_req); void m68k_cpu_dump_state(CPUState *cpu, FILE *f, int flags); hwaddr m68k_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); -int m68k_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg); +int m68k_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); int m68k_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); void m68k_tcg_init(void); diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h index 95773089aa3..987e4629b0a 100644 --- a/target/microblaze/cpu.h +++ b/target/microblaze/cpu.h @@ -313,7 +313,7 @@ void mb_cpu_do_interrupt(CPUState *cs); bool mb_cpu_exec_interrupt(CPUState *cs, int int_req); void mb_cpu_dump_state(CPUState *cpu, FILE *f, int flags); hwaddr mb_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); -int mb_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg); +int mb_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); int mb_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); void mb_tcg_init(void); diff --git a/target/mips/internal.h b/target/mips/internal.h index 3f435b5e631..c5ae86360f5 100644 --- a/target/mips/internal.h +++ b/target/mips/internal.h @@ -82,7 +82,7 @@ void mips_cpu_do_interrupt(CPUState *cpu); bool mips_cpu_exec_interrupt(CPUState *cpu, int int_req); void mips_cpu_dump_state(CPUState *cpu, FILE *f, int flags); hwaddr mips_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); -int mips_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg); +int mips_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); int mips_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); void mips_cpu_do_unaligned_access(CPUState *cpu, vaddr addr, MMUAccessType access_type, diff --git a/target/openrisc/cpu.h b/target/openrisc/cpu.h index 0ad02eab794..d9484b802f3 100644 --- a/target/openrisc/cpu.h +++ b/target/openrisc/cpu.h @@ -320,7 +320,7 @@ void openrisc_cpu_do_interrupt(CPUState *cpu); bool openrisc_cpu_exec_interrupt(CPUState *cpu, int int_req); void openrisc_cpu_dump_state(CPUState *cpu, FILE *f, int flags); hwaddr openrisc_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); -int openrisc_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg); +int openrisc_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); int openrisc_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); void openrisc_translate_init(void); bool openrisc_cpu_tlb_fill(CPUState *cs, vaddr address, int size, diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index 103bfe9dc27..41e009ae3c9 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -1256,8 +1256,8 @@ bool ppc_cpu_exec_interrupt(CPUState *cpu, int int_req); void ppc_cpu_dump_state(CPUState *cpu, FILE *f, int flags); void ppc_cpu_dump_statistics(CPUState *cpu, int flags); hwaddr ppc_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); -int ppc_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg); -int ppc_cpu_gdb_read_register_apple(CPUState *cpu, uint8_t *buf, int reg); +int ppc_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); +int ppc_cpu_gdb_read_register_apple(CPUState *cpu, GByteArray *buf, int reg); int ppc_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); int ppc_cpu_gdb_write_register_apple(CPUState *cpu, uint8_t *buf, int reg); #ifndef CONFIG_USER_ONLY diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index e59343e13c0..fe0b8861021 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -243,7 +243,7 @@ extern const char * const riscv_excp_names[]; extern const char * const riscv_intr_names[]; void riscv_cpu_do_interrupt(CPUState *cpu); -int riscv_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg); +int riscv_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); int riscv_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); bool riscv_cpu_exec_interrupt(CPUState *cs, int interrupt_request); bool riscv_cpu_fp_enabled(CPURISCVState *env); diff --git a/target/s390x/internal.h b/target/s390x/internal.h index d37816104dd..8c95c734dbe 100644 --- a/target/s390x/internal.h +++ b/target/s390x/internal.h @@ -292,7 +292,7 @@ uint16_t float128_dcmask(CPUS390XState *env, float128 f1); /* gdbstub.c */ -int s390_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg); +int s390_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); int s390_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); void s390_cpu_gdb_init(CPUState *cs); diff --git a/target/sh4/cpu.h b/target/sh4/cpu.h index ecaa7a18a94..d7a1bffd600 100644 --- a/target/sh4/cpu.h +++ b/target/sh4/cpu.h @@ -208,7 +208,7 @@ void superh_cpu_do_interrupt(CPUState *cpu); bool superh_cpu_exec_interrupt(CPUState *cpu, int int_req); void superh_cpu_dump_state(CPUState *cpu, FILE *f, int flags); hwaddr superh_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); -int superh_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg); +int superh_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); int superh_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); void superh_cpu_do_unaligned_access(CPUState *cpu, vaddr addr, MMUAccessType access_type, diff --git a/target/sparc/cpu.h b/target/sparc/cpu.h index ae97c7d9f79..b9369398f24 100644 --- a/target/sparc/cpu.h +++ b/target/sparc/cpu.h @@ -571,7 +571,7 @@ extern const VMStateDescription vmstate_sparc_cpu; void sparc_cpu_do_interrupt(CPUState *cpu); void sparc_cpu_dump_state(CPUState *cpu, FILE *f, int flags); hwaddr sparc_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); -int sparc_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg); +int sparc_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); int sparc_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); void QEMU_NORETURN sparc_cpu_do_unaligned_access(CPUState *cpu, vaddr addr, MMUAccessType access_type, diff --git a/target/xtensa/cpu.h b/target/xtensa/cpu.h index b363ffcf106..b20be1f5814 100644 --- a/target/xtensa/cpu.h +++ b/target/xtensa/cpu.h @@ -569,7 +569,7 @@ void xtensa_cpu_dump_state(CPUState *cpu, FILE *f, int flags); hwaddr xtensa_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); void xtensa_count_regs(const XtensaConfig *config, unsigned *n_regs, unsigned *n_core_regs); -int xtensa_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg); +int xtensa_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); int xtensa_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); void xtensa_cpu_do_unaligned_access(CPUState *cpu, vaddr addr, MMUAccessType access_type, diff --git a/gdbstub.c b/gdbstub.c index 736e3cc1052..287d0535b12 100644 --- a/gdbstub.c +++ b/gdbstub.c @@ -319,8 +319,8 @@ static int gdb_signal_to_target (int sig) typedef struct GDBRegisterState { int base_reg; int num_regs; - gdb_reg_cb get_reg; - gdb_reg_cb set_reg; + gdb_get_reg_cb get_reg; + gdb_set_reg_cb set_reg; const char *xml; struct GDBRegisterState *next; } GDBRegisterState; @@ -905,19 +905,19 @@ static const char *get_feature_xml(const char *p, const char **newp, return name ? xml_builtin[i][1] : NULL; } -static int gdb_read_register(CPUState *cpu, uint8_t *mem_buf, int reg) +static int gdb_read_register(CPUState *cpu, GByteArray *buf, int reg) { CPUClass *cc = CPU_GET_CLASS(cpu); CPUArchState *env = cpu->env_ptr; GDBRegisterState *r; if (reg < cc->gdb_num_core_regs) { - return cc->gdb_read_register(cpu, mem_buf, reg); + return cc->gdb_read_register(cpu, buf, reg); } for (r = cpu->gdb_regs; r; r = r->next) { if (r->base_reg <= reg && reg < r->base_reg + r->num_regs) { - return r->get_reg(env, mem_buf, reg - r->base_reg); + return r->get_reg(env, buf, reg - r->base_reg); } } return 0; @@ -948,7 +948,7 @@ static int gdb_write_register(CPUState *cpu, uint8_t *mem_buf, int reg) */ void gdb_register_coprocessor(CPUState *cpu, - gdb_reg_cb get_reg, gdb_reg_cb set_reg, + gdb_get_reg_cb get_reg, gdb_set_reg_cb set_reg, int num_regs, const char *xml, int g_pos) { GDBRegisterState *s; @@ -1739,7 +1739,7 @@ static void handle_get_reg(GdbCmdContext *gdb_ctx, void *user_ctx) } reg_size = gdb_read_register(gdbserver_state.g_cpu, - gdbserver_state.mem_buf->data, + gdbserver_state.mem_buf, gdb_ctx->params[0].val_ull); if (!reg_size) { put_packet("E14"); @@ -1832,14 +1832,14 @@ static void handle_read_all_regs(GdbCmdContext *gdb_ctx, void *user_ctx) target_ulong addr, len; cpu_synchronize_state(gdbserver_state.g_cpu); + g_byte_array_set_size(gdbserver_state.mem_buf, 0); len = 0; for (addr = 0; addr < gdbserver_state.g_cpu->gdb_num_g_regs; addr++) { len += gdb_read_register(gdbserver_state.g_cpu, - gdbserver_state.mem_buf->data + len, + gdbserver_state.mem_buf, addr); } - /* FIXME: This is after the fact sizing */ - g_byte_array_set_size(gdbserver_state.mem_buf, len); + g_assert(len == gdbserver_state.mem_buf->len); memtohex(gdbserver_state.str_buf, gdbserver_state.mem_buf->data, len); put_strbuf(); diff --git a/hw/core/cpu.c b/hw/core/cpu.c index db1a03c6bbb..9cd1a2a54fb 100644 --- a/hw/core/cpu.c +++ b/hw/core/cpu.c @@ -177,7 +177,7 @@ static int cpu_common_write_elf64_note(WriteCoreDumpFunction f, } -static int cpu_common_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg) +static int cpu_common_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg) { return 0; } diff --git a/target/alpha/gdbstub.c b/target/alpha/gdbstub.c index 7f9cc092a9c..0cd76ddaa9e 100644 --- a/target/alpha/gdbstub.c +++ b/target/alpha/gdbstub.c @@ -21,7 +21,7 @@ #include "cpu.h" #include "exec/gdbstub.h" -int alpha_cpu_gdb_read_register(CPUState *cs, uint8_t *mem_buf, int n) +int alpha_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n) { AlphaCPU *cpu = ALPHA_CPU(cs); CPUAlphaState *env = &cpu->env; diff --git a/target/arm/gdbstub.c b/target/arm/gdbstub.c index 1239abd9842..4557775d245 100644 --- a/target/arm/gdbstub.c +++ b/target/arm/gdbstub.c @@ -32,7 +32,7 @@ typedef struct RegisterSysregXmlParam { We hack round this by giving the FPA regs zero size when talking to a newer gdb. */ -int arm_cpu_gdb_read_register(CPUState *cs, uint8_t *mem_buf, int n) +int arm_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n) { ARMCPU *cpu = ARM_CPU(cs); CPUARMState *env = &cpu->env; diff --git a/target/arm/gdbstub64.c b/target/arm/gdbstub64.c index 665ebb3ef64..35d0b80c2de 100644 --- a/target/arm/gdbstub64.c +++ b/target/arm/gdbstub64.c @@ -20,7 +20,7 @@ #include "cpu.h" #include "exec/gdbstub.h" -int aarch64_cpu_gdb_read_register(CPUState *cs, uint8_t *mem_buf, int n) +int aarch64_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n) { ARMCPU *cpu = ARM_CPU(cs); CPUARMState *env = &cpu->env; diff --git a/target/arm/helper.c b/target/arm/helper.c index 6f3b6ca7d3f..36872627a5d 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -47,30 +47,27 @@ static bool get_phys_addr_lpae(CPUARMState *env, target_ulong address, static void switch_mode(CPUARMState *env, int mode); -static int vfp_gdb_get_reg(CPUARMState *env, uint8_t *buf, int reg) +static int vfp_gdb_get_reg(CPUARMState *env, GByteArray *buf, int reg) { int nregs; /* VFP data registers are always little-endian. */ nregs = arm_feature(env, ARM_FEATURE_VFP3) ? 32 : 16; if (reg < nregs) { - stq_le_p(buf, *aa32_vfp_dreg(env, reg)); - return 8; + return gdb_get_reg64(buf, *aa32_vfp_dreg(env, reg)); } if (arm_feature(env, ARM_FEATURE_NEON)) { /* Aliases for Q regs. */ nregs += 16; if (reg < nregs) { uint64_t *q = aa32_vfp_qreg(env, reg - 32); - stq_le_p(buf, q[0]); - stq_le_p(buf + 8, q[1]); - return 16; + return gdb_get_reg128(buf, q[0], q[1]); } } switch (reg - nregs) { - case 0: stl_p(buf, env->vfp.xregs[ARM_VFP_FPSID]); return 4; - case 1: stl_p(buf, vfp_get_fpscr(env)); return 4; - case 2: stl_p(buf, env->vfp.xregs[ARM_VFP_FPEXC]); return 4; + case 0: return gdb_get_reg32(buf, env->vfp.xregs[ARM_VFP_FPSID]); break; + case 1: return gdb_get_reg32(buf, vfp_get_fpscr(env)); break; + case 2: return gdb_get_reg32(buf, env->vfp.xregs[ARM_VFP_FPEXC]); break; } return 0; } @@ -101,7 +98,7 @@ static int vfp_gdb_set_reg(CPUARMState *env, uint8_t *buf, int reg) return 0; } -static int aarch64_fpu_gdb_get_reg(CPUARMState *env, uint8_t *buf, int reg) +static int aarch64_fpu_gdb_get_reg(CPUARMState *env, GByteArray *buf, int reg) { switch (reg) { case 0 ... 31: @@ -204,7 +201,7 @@ static void write_raw_cp_reg(CPUARMState *env, const ARMCPRegInfo *ri, } } -static int arm_gdb_get_sysreg(CPUARMState *env, uint8_t *buf, int reg) +static int arm_gdb_get_sysreg(CPUARMState *env, GByteArray *buf, int reg) { ARMCPU *cpu = env_archcpu(env); const ARMCPRegInfo *ri; diff --git a/target/cris/gdbstub.c b/target/cris/gdbstub.c index a3d76d2e8c2..b01b2aa0811 100644 --- a/target/cris/gdbstub.c +++ b/target/cris/gdbstub.c @@ -21,7 +21,7 @@ #include "cpu.h" #include "exec/gdbstub.h" -int crisv10_cpu_gdb_read_register(CPUState *cs, uint8_t *mem_buf, int n) +int crisv10_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n) { CRISCPU *cpu = CRIS_CPU(cs); CPUCRISState *env = &cpu->env; @@ -53,7 +53,7 @@ int crisv10_cpu_gdb_read_register(CPUState *cs, uint8_t *mem_buf, int n) return 0; } -int cris_cpu_gdb_read_register(CPUState *cs, uint8_t *mem_buf, int n) +int cris_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n) { CRISCPU *cpu = CRIS_CPU(cs); CPUCRISState *env = &cpu->env; diff --git a/target/hppa/gdbstub.c b/target/hppa/gdbstub.c index 341888a9da0..a6428a2893f 100644 --- a/target/hppa/gdbstub.c +++ b/target/hppa/gdbstub.c @@ -21,7 +21,7 @@ #include "cpu.h" #include "exec/gdbstub.h" -int hppa_cpu_gdb_read_register(CPUState *cs, uint8_t *mem_buf, int n) +int hppa_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n) { HPPACPU *cpu = HPPA_CPU(cs); CPUHPPAState *env = &cpu->env; diff --git a/target/i386/gdbstub.c b/target/i386/gdbstub.c index aef25b70f10..38324498f33 100644 --- a/target/i386/gdbstub.c +++ b/target/i386/gdbstub.c @@ -79,7 +79,7 @@ static const int gpr_map32[8] = { 0, 1, 2, 3, 4, 5, 6, 7 }; #endif -int x86_cpu_gdb_read_register(CPUState *cs, uint8_t *mem_buf, int n) +int x86_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n) { X86CPU *cpu = X86_CPU(cs); CPUX86State *env = &cpu->env; diff --git a/target/lm32/gdbstub.c b/target/lm32/gdbstub.c index 82ede436e12..b6fe12e1d61 100644 --- a/target/lm32/gdbstub.c +++ b/target/lm32/gdbstub.c @@ -22,7 +22,7 @@ #include "exec/gdbstub.h" #include "hw/lm32/lm32_pic.h" -int lm32_cpu_gdb_read_register(CPUState *cs, uint8_t *mem_buf, int n) +int lm32_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n) { LM32CPU *cpu = LM32_CPU(cs); CPULM32State *env = &cpu->env; diff --git a/target/m68k/gdbstub.c b/target/m68k/gdbstub.c index fdc96f57fff..eb2d030e148 100644 --- a/target/m68k/gdbstub.c +++ b/target/m68k/gdbstub.c @@ -21,7 +21,7 @@ #include "cpu.h" #include "exec/gdbstub.h" -int m68k_cpu_gdb_read_register(CPUState *cs, uint8_t *mem_buf, int n) +int m68k_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n) { M68kCPU *cpu = M68K_CPU(cs); CPUM68KState *env = &cpu->env; diff --git a/target/m68k/helper.c b/target/m68k/helper.c index 2573ee7a535..6f9099cd937 100644 --- a/target/m68k/helper.c +++ b/target/m68k/helper.c @@ -68,7 +68,7 @@ void m68k_cpu_list(void) g_slist_free(list); } -static int cf_fpu_gdb_get_reg(CPUM68KState *env, uint8_t *mem_buf, int n) +static int cf_fpu_gdb_get_reg(CPUM68KState *env, GByteArray *mem_buf, int n) { if (n < 8) { float_status s; @@ -105,7 +105,7 @@ static int cf_fpu_gdb_set_reg(CPUM68KState *env, uint8_t *mem_buf, int n) return 0; } -static int m68k_fpu_gdb_get_reg(CPUM68KState *env, uint8_t *mem_buf, int n) +static int m68k_fpu_gdb_get_reg(CPUM68KState *env, GByteArray *mem_buf, int n) { if (n < 8) { int len = gdb_get_reg16(mem_buf, env->fregs[n].l.upper); diff --git a/target/microblaze/gdbstub.c b/target/microblaze/gdbstub.c index 30677b6d1f4..f41ebf1f33b 100644 --- a/target/microblaze/gdbstub.c +++ b/target/microblaze/gdbstub.c @@ -21,7 +21,7 @@ #include "cpu.h" #include "exec/gdbstub.h" -int mb_cpu_gdb_read_register(CPUState *cs, uint8_t *mem_buf, int n) +int mb_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n) { MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs); CPUMBState *env = &cpu->env; diff --git a/target/mips/gdbstub.c b/target/mips/gdbstub.c index bbb25449391..98f56e660d2 100644 --- a/target/mips/gdbstub.c +++ b/target/mips/gdbstub.c @@ -22,7 +22,7 @@ #include "internal.h" #include "exec/gdbstub.h" -int mips_cpu_gdb_read_register(CPUState *cs, uint8_t *mem_buf, int n) +int mips_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n) { MIPSCPU *cpu = MIPS_CPU(cs); CPUMIPSState *env = &cpu->env; diff --git a/target/nios2/cpu.c b/target/nios2/cpu.c index ca9c7a6df5d..17d868421ed 100644 --- a/target/nios2/cpu.c +++ b/target/nios2/cpu.c @@ -124,7 +124,7 @@ static void nios2_cpu_disas_set_info(CPUState *cpu, disassemble_info *info) #endif } -static int nios2_cpu_gdb_read_register(CPUState *cs, uint8_t *mem_buf, int n) +static int nios2_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n) { Nios2CPU *cpu = NIOS2_CPU(cs); CPUClass *cc = CPU_GET_CLASS(cs); diff --git a/target/openrisc/gdbstub.c b/target/openrisc/gdbstub.c index 0fcdb79668c..095bf76c12c 100644 --- a/target/openrisc/gdbstub.c +++ b/target/openrisc/gdbstub.c @@ -21,7 +21,7 @@ #include "cpu.h" #include "exec/gdbstub.h" -int openrisc_cpu_gdb_read_register(CPUState *cs, uint8_t *mem_buf, int n) +int openrisc_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n) { OpenRISCCPU *cpu = OPENRISC_CPU(cs); CPUOpenRISCState *env = &cpu->env; diff --git a/target/ppc/gdbstub.c b/target/ppc/gdbstub.c index 823759c92e7..eb362dd9aec 100644 --- a/target/ppc/gdbstub.c +++ b/target/ppc/gdbstub.c @@ -114,10 +114,11 @@ void ppc_maybe_bswap_register(CPUPPCState *env, uint8_t *mem_buf, int len) * the FP regs zero size when talking to a newer gdb. */ -int ppc_cpu_gdb_read_register(CPUState *cs, uint8_t *mem_buf, int n) +int ppc_cpu_gdb_read_register(CPUState *cs, GByteArray *buf, int n) { PowerPCCPU *cpu = POWERPC_CPU(cs); CPUPPCState *env = &cpu->env; + uint8_t *mem_buf; int r = ppc_gdb_register_len(n); if (!r) { @@ -126,17 +127,17 @@ int ppc_cpu_gdb_read_register(CPUState *cs, uint8_t *mem_buf, int n) if (n < 32) { /* gprs */ - gdb_get_regl(mem_buf, env->gpr[n]); + gdb_get_regl(buf, env->gpr[n]); } else if (n < 64) { /* fprs */ - stfq_p(mem_buf, *cpu_fpr_ptr(env, n - 32)); + gdb_get_reg64(buf, *cpu_fpr_ptr(env, n - 32)); } else { switch (n) { case 64: - gdb_get_regl(mem_buf, env->nip); + gdb_get_regl(buf, env->nip); break; case 65: - gdb_get_regl(mem_buf, env->msr); + gdb_get_regl(buf, env->msr); break; case 66: { @@ -145,31 +146,33 @@ int ppc_cpu_gdb_read_register(CPUState *cs, uint8_t *mem_buf, int n) for (i = 0; i < 8; i++) { cr |= env->crf[i] << (32 - ((i + 1) * 4)); } - gdb_get_reg32(mem_buf, cr); + gdb_get_reg32(buf, cr); break; } case 67: - gdb_get_regl(mem_buf, env->lr); + gdb_get_regl(buf, env->lr); break; case 68: - gdb_get_regl(mem_buf, env->ctr); + gdb_get_regl(buf, env->ctr); break; case 69: - gdb_get_reg32(mem_buf, env->xer); + gdb_get_reg32(buf, env->xer); break; case 70: - gdb_get_reg32(mem_buf, env->fpscr); + gdb_get_reg32(buf, env->fpscr); break; } } + mem_buf = buf->data + buf->len - r; ppc_maybe_bswap_register(env, mem_buf, r); return r; } -int ppc_cpu_gdb_read_register_apple(CPUState *cs, uint8_t *mem_buf, int n) +int ppc_cpu_gdb_read_register_apple(CPUState *cs, GByteArray *buf, int n) { PowerPCCPU *cpu = POWERPC_CPU(cs); CPUPPCState *env = &cpu->env; + uint8_t *mem_buf; int r = ppc_gdb_register_len_apple(n); if (!r) { @@ -178,21 +181,21 @@ int ppc_cpu_gdb_read_register_apple(CPUState *cs, uint8_t *mem_buf, int n) if (n < 32) { /* gprs */ - gdb_get_reg64(mem_buf, env->gpr[n]); + gdb_get_reg64(buf, env->gpr[n]); } else if (n < 64) { /* fprs */ - stfq_p(mem_buf, *cpu_fpr_ptr(env, n - 32)); + gdb_get_reg64(buf, *cpu_fpr_ptr(env, n - 32)); } else if (n < 96) { /* Altivec */ - stq_p(mem_buf, n - 64); - stq_p(mem_buf + 8, 0); + gdb_get_reg64(buf, n - 64); + gdb_get_reg64(buf, 0); } else { switch (n) { case 64 + 32: - gdb_get_reg64(mem_buf, env->nip); + gdb_get_reg64(buf, env->nip); break; case 65 + 32: - gdb_get_reg64(mem_buf, env->msr); + gdb_get_reg64(buf, env->msr); break; case 66 + 32: { @@ -201,23 +204,24 @@ int ppc_cpu_gdb_read_register_apple(CPUState *cs, uint8_t *mem_buf, int n) for (i = 0; i < 8; i++) { cr |= env->crf[i] << (32 - ((i + 1) * 4)); } - gdb_get_reg32(mem_buf, cr); + gdb_get_reg32(buf, cr); break; } case 67 + 32: - gdb_get_reg64(mem_buf, env->lr); + gdb_get_reg64(buf, env->lr); break; case 68 + 32: - gdb_get_reg64(mem_buf, env->ctr); + gdb_get_reg64(buf, env->ctr); break; case 69 + 32: - gdb_get_reg32(mem_buf, env->xer); + gdb_get_reg32(buf, env->xer); break; case 70 + 32: - gdb_get_reg64(mem_buf, env->fpscr); + gdb_get_reg64(buf, env->fpscr); break; } } + mem_buf = buf->data + buf->len - r; ppc_maybe_bswap_register(env, mem_buf, r); return r; } diff --git a/target/ppc/translate_init.inc.c b/target/ppc/translate_init.inc.c index d33d65dff70..ca241d7f5e6 100644 --- a/target/ppc/translate_init.inc.c +++ b/target/ppc/translate_init.inc.c @@ -9845,7 +9845,7 @@ static int gdb_find_spr_idx(CPUPPCState *env, int n) return -1; } -static int gdb_get_spr_reg(CPUPPCState *env, uint8_t *mem_buf, int n) +static int gdb_get_spr_reg(CPUPPCState *env, GByteArray *buf, int n) { int reg; int len; @@ -9856,8 +9856,8 @@ static int gdb_get_spr_reg(CPUPPCState *env, uint8_t *mem_buf, int n) } len = TARGET_LONG_SIZE; - stn_p(mem_buf, len, env->spr[reg]); - ppc_maybe_bswap_register(env, mem_buf, len); + gdb_get_regl(buf, env->spr[reg]); + ppc_maybe_bswap_register(env, buf->data - len, len); return len; } @@ -9879,15 +9879,18 @@ static int gdb_set_spr_reg(CPUPPCState *env, uint8_t *mem_buf, int n) } #endif -static int gdb_get_float_reg(CPUPPCState *env, uint8_t *mem_buf, int n) +static int gdb_get_float_reg(CPUPPCState *env, GByteArray *buf, int n) { + uint8_t *mem_buf; if (n < 32) { - stfq_p(mem_buf, *cpu_fpr_ptr(env, n)); + gdb_get_reg64(buf, *cpu_fpr_ptr(env, n)); + mem_buf = buf->data - 8; ppc_maybe_bswap_register(env, mem_buf, 8); return 8; } if (n == 32) { - stl_p(mem_buf, env->fpscr); + gdb_get_reg32(buf, env->fpscr); + mem_buf = buf->data - 4; ppc_maybe_bswap_register(env, mem_buf, 4); return 4; } @@ -9909,28 +9912,31 @@ static int gdb_set_float_reg(CPUPPCState *env, uint8_t *mem_buf, int n) return 0; } -static int gdb_get_avr_reg(CPUPPCState *env, uint8_t *mem_buf, int n) +static int gdb_get_avr_reg(CPUPPCState *env, GByteArray *buf, int n) { + uint8_t *mem_buf; + if (n < 32) { ppc_avr_t *avr = cpu_avr_ptr(env, n); if (!avr_need_swap(env)) { - stq_p(mem_buf, avr->u64[0]); - stq_p(mem_buf + 8, avr->u64[1]); + gdb_get_reg128(buf, avr->u64[0] , avr->u64[1]); } else { - stq_p(mem_buf, avr->u64[1]); - stq_p(mem_buf + 8, avr->u64[0]); + gdb_get_reg128(buf, avr->u64[1] , avr->u64[0]); } + mem_buf = buf->data - 16; ppc_maybe_bswap_register(env, mem_buf, 8); ppc_maybe_bswap_register(env, mem_buf + 8, 8); return 16; } if (n == 32) { - stl_p(mem_buf, helper_mfvscr(env)); + gdb_get_reg32(buf, helper_mfvscr(env)); + mem_buf = buf->data - 4; ppc_maybe_bswap_register(env, mem_buf, 4); return 4; } if (n == 33) { - stl_p(mem_buf, (uint32_t)env->spr[SPR_VRSAVE]); + gdb_get_reg32(buf, (uint32_t)env->spr[SPR_VRSAVE]); + mem_buf = buf->data - 4; ppc_maybe_bswap_register(env, mem_buf, 4); return 4; } @@ -9965,25 +9971,25 @@ static int gdb_set_avr_reg(CPUPPCState *env, uint8_t *mem_buf, int n) return 0; } -static int gdb_get_spe_reg(CPUPPCState *env, uint8_t *mem_buf, int n) +static int gdb_get_spe_reg(CPUPPCState *env, GByteArray *buf, int n) { if (n < 32) { #if defined(TARGET_PPC64) - stl_p(mem_buf, env->gpr[n] >> 32); - ppc_maybe_bswap_register(env, mem_buf, 4); + gdb_get_reg32(buf, env->gpr[n] >> 32); + ppc_maybe_bswap_register(env, buf->data - 4, 4); #else - stl_p(mem_buf, env->gprh[n]); + gdb_get_reg32(buf, env->gprh[n]); #endif return 4; } if (n == 32) { - stq_p(mem_buf, env->spe_acc); - ppc_maybe_bswap_register(env, mem_buf, 8); + gdb_get_reg64(buf, env->spe_acc); + ppc_maybe_bswap_register(env, buf->data - 8, 8); return 8; } if (n == 33) { - stl_p(mem_buf, env->spe_fscr); - ppc_maybe_bswap_register(env, mem_buf, 4); + gdb_get_reg32(buf, env->spe_fscr); + ppc_maybe_bswap_register(env, buf->data - 4, 4); return 4; } return 0; @@ -10018,11 +10024,11 @@ static int gdb_set_spe_reg(CPUPPCState *env, uint8_t *mem_buf, int n) return 0; } -static int gdb_get_vsx_reg(CPUPPCState *env, uint8_t *mem_buf, int n) +static int gdb_get_vsx_reg(CPUPPCState *env, GByteArray *buf, int n) { if (n < 32) { - stq_p(mem_buf, *cpu_vsrl_ptr(env, n)); - ppc_maybe_bswap_register(env, mem_buf, 8); + gdb_get_reg64(buf, *cpu_vsrl_ptr(env, n)); + ppc_maybe_bswap_register(env, buf->data - 8, 8); return 8; } return 0; diff --git a/target/riscv/gdbstub.c b/target/riscv/gdbstub.c index 1a7947e0198..05442215a4b 100644 --- a/target/riscv/gdbstub.c +++ b/target/riscv/gdbstub.c @@ -269,7 +269,7 @@ static int csr_register_map[] = { CSR_MHCOUNTEREN, }; -int riscv_cpu_gdb_read_register(CPUState *cs, uint8_t *mem_buf, int n) +int riscv_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n) { RISCVCPU *cpu = RISCV_CPU(cs); CPURISCVState *env = &cpu->env; @@ -300,10 +300,10 @@ int riscv_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n) return 0; } -static int riscv_gdb_get_fpu(CPURISCVState *env, uint8_t *mem_buf, int n) +static int riscv_gdb_get_fpu(CPURISCVState *env, GByteArray *buf, int n) { if (n < 32) { - return gdb_get_reg64(mem_buf, env->fpr[n]); + return gdb_get_reg64(buf, env->fpr[n]); /* there is hole between ft11 and fflags in fpu.xml */ } else if (n < 36 && n > 32) { target_ulong val = 0; @@ -316,7 +316,7 @@ static int riscv_gdb_get_fpu(CPURISCVState *env, uint8_t *mem_buf, int n) result = riscv_csrrw_debug(env, n - 33 + csr_register_map[8], &val, 0, 0); if (result == 0) { - return gdb_get_regl(mem_buf, val); + return gdb_get_regl(buf, val); } } return 0; @@ -345,7 +345,7 @@ static int riscv_gdb_set_fpu(CPURISCVState *env, uint8_t *mem_buf, int n) return 0; } -static int riscv_gdb_get_csr(CPURISCVState *env, uint8_t *mem_buf, int n) +static int riscv_gdb_get_csr(CPURISCVState *env, GByteArray *buf, int n) { if (n < ARRAY_SIZE(csr_register_map)) { target_ulong val = 0; @@ -353,7 +353,7 @@ static int riscv_gdb_get_csr(CPURISCVState *env, uint8_t *mem_buf, int n) result = riscv_csrrw_debug(env, csr_register_map[n], &val, 0, 0); if (result == 0) { - return gdb_get_regl(mem_buf, val); + return gdb_get_regl(buf, val); } } return 0; @@ -373,13 +373,13 @@ static int riscv_gdb_set_csr(CPURISCVState *env, uint8_t *mem_buf, int n) return 0; } -static int riscv_gdb_get_virtual(CPURISCVState *cs, uint8_t *mem_buf, int n) +static int riscv_gdb_get_virtual(CPURISCVState *cs, GByteArray *buf, int n) { if (n == 0) { #ifdef CONFIG_USER_ONLY - return gdb_get_regl(mem_buf, 0); + return gdb_get_regl(buf, 0); #else - return gdb_get_regl(mem_buf, cs->priv); + return gdb_get_regl(buf, cs->priv); #endif } return 0; diff --git a/target/s390x/gdbstub.c b/target/s390x/gdbstub.c index e24a49f4a91..d6fce5ff1e1 100644 --- a/target/s390x/gdbstub.c +++ b/target/s390x/gdbstub.c @@ -27,7 +27,7 @@ #include "sysemu/hw_accel.h" #include "sysemu/tcg.h" -int s390_cpu_gdb_read_register(CPUState *cs, uint8_t *mem_buf, int n) +int s390_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n) { S390CPU *cpu = S390_CPU(cs); CPUS390XState *env = &cpu->env; @@ -82,11 +82,11 @@ int s390_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n) /* total number of registers in s390-acr.xml */ #define S390_NUM_AC_REGS 16 -static int cpu_read_ac_reg(CPUS390XState *env, uint8_t *mem_buf, int n) +static int cpu_read_ac_reg(CPUS390XState *env, GByteArray *buf, int n) { switch (n) { case S390_A0_REGNUM ... S390_A15_REGNUM: - return gdb_get_reg32(mem_buf, env->aregs[n]); + return gdb_get_reg32(buf, env->aregs[n]); default: return 0; } @@ -111,13 +111,13 @@ static int cpu_write_ac_reg(CPUS390XState *env, uint8_t *mem_buf, int n) /* total number of registers in s390-fpr.xml */ #define S390_NUM_FP_REGS 17 -static int cpu_read_fp_reg(CPUS390XState *env, uint8_t *mem_buf, int n) +static int cpu_read_fp_reg(CPUS390XState *env, GByteArray *buf, int n) { switch (n) { case S390_FPC_REGNUM: - return gdb_get_reg32(mem_buf, env->fpc); + return gdb_get_reg32(buf, env->fpc); case S390_F0_REGNUM ... S390_F15_REGNUM: - return gdb_get_reg64(mem_buf, *get_freg(env, n - S390_F0_REGNUM)); + return gdb_get_reg64(buf, *get_freg(env, n - S390_F0_REGNUM)); default: return 0; } @@ -145,17 +145,17 @@ static int cpu_write_fp_reg(CPUS390XState *env, uint8_t *mem_buf, int n) /* total number of registers in s390-vx.xml */ #define S390_NUM_VREGS 32 -static int cpu_read_vreg(CPUS390XState *env, uint8_t *mem_buf, int n) +static int cpu_read_vreg(CPUS390XState *env, GByteArray *buf, int n) { int ret; switch (n) { case S390_V0L_REGNUM ... S390_V15L_REGNUM: - ret = gdb_get_reg64(mem_buf, env->vregs[n][1]); + ret = gdb_get_reg64(buf, env->vregs[n][1]); break; case S390_V16_REGNUM ... S390_V31_REGNUM: - ret = gdb_get_reg64(mem_buf, env->vregs[n][0]); - ret += gdb_get_reg64(mem_buf + 8, env->vregs[n][1]); + ret = gdb_get_reg64(buf, env->vregs[n][0]); + ret += gdb_get_reg64(buf, env->vregs[n][1]); break; default: ret = 0; @@ -186,11 +186,11 @@ static int cpu_write_vreg(CPUS390XState *env, uint8_t *mem_buf, int n) #define S390_NUM_C_REGS 16 #ifndef CONFIG_USER_ONLY -static int cpu_read_c_reg(CPUS390XState *env, uint8_t *mem_buf, int n) +static int cpu_read_c_reg(CPUS390XState *env, GByteArray *buf, int n) { switch (n) { case S390_C0_REGNUM ... S390_C15_REGNUM: - return gdb_get_regl(mem_buf, env->cregs[n]); + return gdb_get_regl(buf, env->cregs[n]); default: return 0; } @@ -223,7 +223,7 @@ static int cpu_write_c_reg(CPUS390XState *env, uint8_t *mem_buf, int n) /* total number of registers in s390-virt.xml */ #define S390_NUM_VIRT_REGS 8 -static int cpu_read_virt_reg(CPUS390XState *env, uint8_t *mem_buf, int n) +static int cpu_read_virt_reg(CPUS390XState *env, GByteArray *mem_buf, int n) { switch (n) { case S390_VIRT_CKC_REGNUM: @@ -296,9 +296,9 @@ static int cpu_write_virt_reg(CPUS390XState *env, uint8_t *mem_buf, int n) /* total number of registers in s390-gs.xml */ #define S390_NUM_GS_REGS 4 -static int cpu_read_gs_reg(CPUS390XState *env, uint8_t *mem_buf, int n) +static int cpu_read_gs_reg(CPUS390XState *env, GByteArray *buf, int n) { - return gdb_get_regl(mem_buf, env->gscb[n]); + return gdb_get_regl(buf, env->gscb[n]); } static int cpu_write_gs_reg(CPUS390XState *env, uint8_t *mem_buf, int n) diff --git a/target/sh4/gdbstub.c b/target/sh4/gdbstub.c index 44c1679e9db..49fc4a0cc69 100644 --- a/target/sh4/gdbstub.c +++ b/target/sh4/gdbstub.c @@ -24,7 +24,7 @@ /* Hint: Use "set architecture sh4" in GDB to see fpu registers */ /* FIXME: We should use XML for this. */ -int superh_cpu_gdb_read_register(CPUState *cs, uint8_t *mem_buf, int n) +int superh_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n) { SuperHCPU *cpu = SUPERH_CPU(cs); CPUSH4State *env = &cpu->env; diff --git a/target/sparc/gdbstub.c b/target/sparc/gdbstub.c index 8be742b5a3d..78dc8dcc980 100644 --- a/target/sparc/gdbstub.c +++ b/target/sparc/gdbstub.c @@ -27,7 +27,7 @@ #define gdb_get_rega(buf, val) gdb_get_regl(buf, val) #endif -int sparc_cpu_gdb_read_register(CPUState *cs, uint8_t *mem_buf, int n) +int sparc_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n) { SPARCCPU *cpu = SPARC_CPU(cs); CPUSPARCState *env = &cpu->env; diff --git a/target/xtensa/gdbstub.c b/target/xtensa/gdbstub.c index 54727881f38..0ee3feabe54 100644 --- a/target/xtensa/gdbstub.c +++ b/target/xtensa/gdbstub.c @@ -63,7 +63,7 @@ void xtensa_count_regs(const XtensaConfig *config, } } -int xtensa_cpu_gdb_read_register(CPUState *cs, uint8_t *mem_buf, int n) +int xtensa_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n) { XtensaCPU *cpu = XTENSA_CPU(cs); CPUXtensaState *env = &cpu->env; -- 2.20.1 From MAILER-DAEMON Fri Dec 20 07:05:29 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1iiH29-0005Fu-Cc for mharc-qemu-arm@gnu.org; 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Fri, 20 Dec 2019 04:04:53 -0800 (PST) Received: from zen.lan (localhost [127.0.0.1]) by zen.linaroharston (Postfix) with ESMTP id C87411FFA6; Fri, 20 Dec 2019 12:04:40 +0000 (GMT) From: =?UTF-8?q?Alex=20Benn=C3=A9e?= To: qemu-devel@nongnu.org Cc: alan.hayward@arm.com, luis.machado@linaro.org, damien.hedde@greensocs.com, =?UTF-8?q?Alex=20Benn=C3=A9e?= , Peter Maydell , qemu-arm@nongnu.org (open list:ARM TCG CPUs) Subject: [PATCH v4 18/21] tests/tcg/aarch64: add SVE iotcl test Date: Fri, 20 Dec 2019 12:04:35 +0000 Message-Id: <20191220120438.16114-19-alex.bennee@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20191220120438.16114-1-alex.bennee@linaro.org> References: <20191220120438.16114-1-alex.bennee@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::343 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 20 Dec 2019 12:05:26 -0000 This is a fairly bare-bones test of setting the various vector sizes for SVE which will only fail if the PR_SVE_SET_VL can't reduce the user-space vector length by powers of 2. However we will also be able to use it in a future test which exercises the GDB stub. Signed-off-by: Alex Bennée --- v3 - use index to fill zreg - CROSS_CC_HAS_SVE --- tests/tcg/aarch64/sve-ioctls.c | 77 +++++++++++++++++++++++++++++++ tests/tcg/aarch64/Makefile.target | 4 ++ 2 files changed, 81 insertions(+) create mode 100644 tests/tcg/aarch64/sve-ioctls.c diff --git a/tests/tcg/aarch64/sve-ioctls.c b/tests/tcg/aarch64/sve-ioctls.c new file mode 100644 index 00000000000..d7bb64d53f9 --- /dev/null +++ b/tests/tcg/aarch64/sve-ioctls.c @@ -0,0 +1,77 @@ +/* + * SVE ioctls tests + * + * Test the SVE width setting ioctls work and provide a base for + * testing the gdbstub. + * + * Copyright (c) 2019 Linaro Ltd + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ +#include +#include +#include +#include +#include +#include + +#ifndef HWCAP_CPUID +#define HWCAP_CPUID (1 << 11) +#endif + +#define SVE_MAX_QUADS (2048 / 128) +#define BYTES_PER_QUAD (128 / 8) + +#define get_cpu_reg(id) ({ \ + unsigned long __val; \ + asm("mrs %0, "#id : "=r" (__val)); \ + __val; \ + }) + +static int do_sve_ioctl_test(void) +{ + int i, res, init_vq; + + res = prctl(PR_SVE_GET_VL, 0, 0, 0, 0); + if (res < 0) { + printf("FAILED to PR_SVE_GET_VL (%d)", res); + return -1; + } + init_vq = res & PR_SVE_VL_LEN_MASK; + + for (i = init_vq; i > 15; i /= 2) { + printf("Checking PR_SVE_SET_VL=%d\n", i); + res = prctl(PR_SVE_SET_VL, i, 0, 0, 0, 0); + if (res < 0) { + printf("FAILED to PR_SVE_SET_VL (%d)", res); + return -1; + } + asm("index z0.b, #0, #1\n" + ".global __sve_ld_done\n" + "__sve_ld_done:\n" + "mov z0.b, #0\n" + : /* no outputs kept */ + : /* no inputs */ + : "memory", "z0"); + } + printf("PASS\n"); + return 0; +} + +int main(int argc, char **argv) +{ + unsigned int sve_feature = (get_cpu_reg(ID_AA64PFR0_EL1) >> 32) & 0xf; + /* Exit early if we don't support SVE at all */ + if (sve_feature == 0x1) { + /* we also need to probe for the ioctl support */ + if (getauxval(AT_HWCAP) & HWCAP_SVE) { + return do_sve_ioctl_test(); + } else { + printf("SKIP: no HWCAP_SVE on this system\n"); + return 0; + } + } else { + printf("SKIP: no SVE on this system\n"); + return 0; + } +} diff --git a/tests/tcg/aarch64/Makefile.target b/tests/tcg/aarch64/Makefile.target index 3f8783ada5c..209c79a1ddb 100644 --- a/tests/tcg/aarch64/Makefile.target +++ b/tests/tcg/aarch64/Makefile.target @@ -36,6 +36,10 @@ ifneq ($(DOCKER_IMAGE)$(CROSS_CC_HAS_SVE),) # System Registers Tests AARCH64_TESTS += sysregs sysregs: CFLAGS+=-march=armv8.1-a+sve + +# SVE ioctl test +AARCH64_TESTS += sve-ioctls +sve-ioctls: CFLAGS+=-march=armv8.1-a+sve endif TESTS += $(AARCH64_TESTS) -- 2.20.1 From MAILER-DAEMON Fri Dec 20 07:05:30 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1iiH2A-0005HX-Hm for mharc-qemu-arm@gnu.org; Fri, 20 Dec 2019 07:05:30 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:54442) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iiH1y-000586-QH for qemu-arm@nongnu.org; Fri, 20 Dec 2019 07:05:21 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1iiH1t-000050-0b for qemu-arm@nongnu.org; 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Fri, 20 Dec 2019 04:04:51 -0800 (PST) Received: from zen.lan (localhost [127.0.0.1]) by zen.linaroharston (Postfix) with ESMTP id 44E8A1FF9C; Fri, 20 Dec 2019 12:04:40 +0000 (GMT) From: =?UTF-8?q?Alex=20Benn=C3=A9e?= To: qemu-devel@nongnu.org Cc: alan.hayward@arm.com, luis.machado@linaro.org, damien.hedde@greensocs.com, =?UTF-8?q?Alex=20Benn=C3=A9e?= , Peter Maydell , qemu-arm@nongnu.org (open list:ARM TCG CPUs) Subject: [PATCH v4 12/21] target/arm: generate xml description of our SVE registers Date: Fri, 20 Dec 2019 12:04:29 +0000 Message-Id: <20191220120438.16114-13-alex.bennee@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20191220120438.16114-1-alex.bennee@linaro.org> References: <20191220120438.16114-1-alex.bennee@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::344 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 20 Dec 2019 12:05:22 -0000 We also expose a the helpers to read/write the the registers. Signed-off-by: Alex Bennée --- v2 - instead of zNpM expose zN at sve_max_vq width - wrap union in union q(us), d(usf), s(usf), h(usf), b(us) v3 - add a vg pseudo register for current width - spacing fixes - use switch/case for whole group - drop fpsr_pos marker - remove unused variables v4 - const-ify vec_lanes - drop vg --- target/arm/cpu.h | 7 ++- target/arm/gdbstub.c | 129 +++++++++++++++++++++++++++++++++++++++++++ target/arm/helper.c | 113 ++++++++++++++++++++++++++++++++++++- 3 files changed, 244 insertions(+), 5 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 40591b5dc70..33b96a0c066 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -755,6 +755,7 @@ struct ARMCPU { int32_t cpreg_vmstate_array_len; DynamicGDBXMLInfo dyn_sysreg_xml; + DynamicGDBXMLInfo dyn_svereg_xml; /* Timers used by the generic (architected) timer */ QEMUTimer *gt_timer[NUM_GTIMERS]; @@ -958,10 +959,12 @@ hwaddr arm_cpu_get_phys_page_attrs_debug(CPUState *cpu, vaddr addr, int arm_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); int arm_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); -/* Dynamically generates for gdb stub an XML description of the sysregs from - * the cp_regs hashtable. Returns the registered sysregs number. +/* + * Helpers to dynamically generates XML descriptions of the sysregs + * and SVE registers. Returns the number of registers in each set. */ int arm_gen_dynamic_sysreg_xml(CPUState *cpu, int base_reg); +int arm_gen_dynamic_svereg_xml(CPUState *cpu, int base_reg); /* Returns the dynamically generated XML for the gdb stub. * Returns a pointer to the XML contents for the specified XML file or NULL diff --git a/target/arm/gdbstub.c b/target/arm/gdbstub.c index 69c35462a63..d9dc6b3fb41 100644 --- a/target/arm/gdbstub.c +++ b/target/arm/gdbstub.c @@ -171,12 +171,141 @@ int arm_gen_dynamic_sysreg_xml(CPUState *cs, int base_reg) return cpu->dyn_sysreg_xml.num; } +struct TypeSize { + const char *gdb_type; + int size; + const char sz, suffix; +}; + +static const struct TypeSize vec_lanes[] = { + /* quads */ + { "uint128", 128, 'q', 'u' }, + { "int128", 128, 'q', 's' }, + /* 64 bit */ + { "uint64", 64, 'd', 'u' }, + { "int64", 64, 'd', 's' }, + { "ieee_double", 64, 'd', 'f' }, + /* 32 bit */ + { "uint32", 32, 's', 'u' }, + { "int32", 32, 's', 's' }, + { "ieee_single", 32, 's', 'f' }, + /* 16 bit */ + { "uint16", 16, 'h', 'u' }, + { "int16", 16, 'h', 's' }, + { "ieee_half", 16, 'h', 'f' }, + /* bytes */ + { "uint8", 8, 'b', 'u' }, + { "int8", 8, 'b', 's' }, +}; + + +int arm_gen_dynamic_svereg_xml(CPUState *cs, int base_reg) +{ + ARMCPU *cpu = ARM_CPU(cs); + GString *s = g_string_new(NULL); + DynamicGDBXMLInfo *info = &cpu->dyn_svereg_xml; + g_autoptr(GString) ts = g_string_new(""); + int i, bits, reg_width = (cpu->sve_max_vq * 128); + info->num = 0; + g_string_printf(s, ""); + g_string_append_printf(s, ""); + g_string_append_printf(s, ""); + + /* First define types and totals in a whole VL */ + for (i = 0; i < ARRAY_SIZE(vec_lanes); i++) { + int count = reg_width / vec_lanes[i].size; + g_string_printf(ts, "vq%d%c%c", count, + vec_lanes[i].sz, vec_lanes[i].suffix); + g_string_append_printf(s, + "", + ts->str, vec_lanes[i].gdb_type, count); + } + /* + * Now define a union for each size group containing unsigned and + * signed and potentially float versions of each size from 128 to + * 8 bits. + */ + for (bits = 128; bits >= 8; bits /= 2) { + int count = reg_width / bits; + g_string_append_printf(s, "", count); + for (i = 0; i < ARRAY_SIZE(vec_lanes); i++) { + if (vec_lanes[i].size == bits) { + g_string_append_printf(s, "", + vec_lanes[i].suffix, + count, + vec_lanes[i].sz, vec_lanes[i].suffix); + } + } + g_string_append(s, ""); + } + /* And now the final union of unions */ + g_string_append(s, ""); + for (bits = 128; bits >= 8; bits /= 2) { + int count = reg_width / bits; + for (i = 0; i < ARRAY_SIZE(vec_lanes); i++) { + if (vec_lanes[i].size == bits) { + g_string_append_printf(s, "", + vec_lanes[i].sz, count); + break; + } + } + } + g_string_append(s, ""); + + /* Then define each register in parts for each vq */ + for (i = 0; i < 32; i++) { + g_string_append_printf(s, + "", + i, reg_width, base_reg++); + info->num++; + } + /* fpscr & status registers */ + g_string_append_printf(s, "", base_reg++); + g_string_append_printf(s, "", base_reg++); + info->num += 2; + /* + * Predicate registers aren't so big they are worth splitting up + * but we do need to define a type to hold the array of quad + * references. + */ + g_string_append_printf(s, + "", + cpu->sve_max_vq); + for (i = 0; i < 16; i++) { + g_string_append_printf(s, + "", + i, cpu->sve_max_vq * 16, base_reg++); + info->num++; + } + g_string_append_printf(s, + "", + cpu->sve_max_vq * 16, base_reg++); + info->num += 1; + g_string_append_printf(s, ""); + cpu->dyn_svereg_xml.desc = g_string_free(s, false); + + return cpu->dyn_svereg_xml.num; +} + + const char *arm_gdb_get_dynamic_xml(CPUState *cs, const char *xmlname) { ARMCPU *cpu = ARM_CPU(cs); if (strcmp(xmlname, "system-registers.xml") == 0) { return cpu->dyn_sysreg_xml.desc; + } else if (strcmp(xmlname, "sve-registers.xml") == 0) { + return cpu->dyn_svereg_xml.desc; } return NULL; } diff --git a/target/arm/helper.c b/target/arm/helper.c index 488fdbf61a9..857581feba4 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -201,6 +201,15 @@ static void write_raw_cp_reg(CPUARMState *env, const ARMCPRegInfo *ri, } } +/** + * arm_get/set_gdb_*: get/set a gdb register + * @env: the CPU state + * @buf: a buffer to copy to/from + * @reg: register number (offset from start of group) + * + * We return the number of bytes copied + */ + static int arm_gdb_get_sysreg(CPUARMState *env, GByteArray *buf, int reg) { ARMCPU *cpu = env_archcpu(env); @@ -224,6 +233,90 @@ static int arm_gdb_set_sysreg(CPUARMState *env, uint8_t *buf, int reg) return 0; } +#ifdef TARGET_AARCH64 +static int arm_gdb_get_svereg(CPUARMState *env, GByteArray *buf, int reg) +{ + ARMCPU *cpu = env_archcpu(env); + + switch (reg) { + /* The first 32 registers are the zregs */ + case 0 ... 31: + { + int vq, len = 0; + for (vq = 0; vq < cpu->sve_max_vq; vq++) { + len += gdb_get_reg128(buf, + env->vfp.zregs[reg].d[vq * 2 + 1], + env->vfp.zregs[reg].d[vq * 2]); + } + return len; + } + case 32: + return gdb_get_reg32(buf, vfp_get_fpsr(env)); + case 33: + return gdb_get_reg32(buf, vfp_get_fpcr(env)); + /* then 16 predicates and the ffr */ + case 34 ... 50: + { + int preg = reg - 34; + int vq, len = 0; + for (vq = 0; vq < cpu->sve_max_vq; vq = vq + 4) { + len += gdb_get_reg64(buf, env->vfp.pregs[preg].p[vq / 4]); + } + return len; + } + default: + /* gdbstub asked for something out our range */ + qemu_log_mask(LOG_UNIMP, "%s: out of range register %d", __func__, reg); + break; + } + + return 0; +} + +static int arm_gdb_set_svereg(CPUARMState *env, uint8_t *buf, int reg) +{ + ARMCPU *cpu = env_archcpu(env); + + /* The first 32 registers are the zregs */ + switch (reg) { + /* The first 32 registers are the zregs */ + case 0 ... 31: + { + int vq, len = 0; + uint64_t *p = (uint64_t *) buf; + for (vq = 0; vq < cpu->sve_max_vq; vq++) { + env->vfp.zregs[reg].d[vq * 2 + 1] = *p++; + env->vfp.zregs[reg].d[vq * 2] = *p++; + len += 16; + } + return len; + } + case 32: + vfp_set_fpsr(env, *(uint32_t *)buf); + return 4; + case 33: + vfp_set_fpcr(env, *(uint32_t *)buf); + return 4; + case 34 ... 50: + { + int preg = reg - 34; + int vq, len = 0; + uint64_t *p = (uint64_t *) buf; + for (vq = 0; vq < cpu->sve_max_vq; vq = vq + 4) { + env->vfp.pregs[preg].p[vq / 4] = *p++; + len += 8; + } + return len; + } + default: + /* gdbstub asked for something out our range */ + break; + } + + return 0; +} +#endif /* TARGET_AARCH64 */ + static bool raw_accessors_invalid(const ARMCPRegInfo *ri) { /* Return true if the regdef would cause an assertion if you called @@ -7115,9 +7208,22 @@ void arm_cpu_register_gdb_regs_for_features(ARMCPU *cpu) CPUARMState *env = &cpu->env; if (arm_feature(env, ARM_FEATURE_AARCH64)) { - gdb_register_coprocessor(cs, aarch64_fpu_gdb_get_reg, - aarch64_fpu_gdb_set_reg, - 34, "aarch64-fpu.xml", 0); + /* + * The lower part of each SVE register aliases to the FPU + * registers so we don't need to include both. + */ +#ifdef TARGET_AARCH64 + if (isar_feature_aa64_sve(&cpu->isar)) { + gdb_register_coprocessor(cs, arm_gdb_get_svereg, arm_gdb_set_svereg, + arm_gen_dynamic_svereg_xml(cs, cs->gdb_num_regs), + "sve-registers.xml", 0); + } else +#endif + { + gdb_register_coprocessor(cs, aarch64_fpu_gdb_get_reg, + aarch64_fpu_gdb_set_reg, + 34, "aarch64-fpu.xml", 0); + } } else if (arm_feature(env, ARM_FEATURE_NEON)) { gdb_register_coprocessor(cs, vfp_gdb_get_reg, vfp_gdb_set_reg, 51, "arm-neon.xml", 0); @@ -7131,6 +7237,7 @@ void arm_cpu_register_gdb_regs_for_features(ARMCPU *cpu) gdb_register_coprocessor(cs, arm_gdb_get_sysreg, arm_gdb_set_sysreg, arm_gen_dynamic_sysreg_xml(cs, cs->gdb_num_regs), "system-registers.xml", 0); + } /* Sort alphabetically by type name, except for "any". */ -- 2.20.1 From MAILER-DAEMON Fri Dec 20 07:05:32 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1iiH2B-0005Ic-Mc for mharc-qemu-arm@gnu.org; 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Fri, 20 Dec 2019 04:04:53 -0800 (PST) Received: from zen.lan (localhost [127.0.0.1]) by zen.linaroharston (Postfix) with ESMTP id 83A771FF9F; Fri, 20 Dec 2019 12:04:40 +0000 (GMT) From: =?UTF-8?q?Alex=20Benn=C3=A9e?= To: qemu-devel@nongnu.org Cc: alan.hayward@arm.com, luis.machado@linaro.org, damien.hedde@greensocs.com, =?UTF-8?q?Alex=20Benn=C3=A9e?= , Peter Maydell , qemu-arm@nongnu.org (open list:ARM TCG CPUs) Subject: [PATCH v4 15/21] tests/tcg/aarch64: userspace system register test Date: Fri, 20 Dec 2019 12:04:32 +0000 Message-Id: <20191220120438.16114-16-alex.bennee@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20191220120438.16114-1-alex.bennee@linaro.org> References: <20191220120438.16114-1-alex.bennee@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::443 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 20 Dec 2019 12:05:26 -0000 This tests a bunch of registers that the kernel allows userspace to read including the CPUID registers. We need a SVE aware compiler as we are testing the id_aa64zfr0_el1 register in the set. Signed-off-by: Alex Bennée Message-Id: <20190205190224.2198-7-alex.bennee@linaro.org> --- vgdbstub - don't build unless using docker or CROSS_CC_HAS_SVE --- tests/tcg/aarch64/sysregs.c | 172 ++++++++++++++++++++++++++++++ tests/tcg/aarch64/Makefile.target | 6 ++ 2 files changed, 178 insertions(+) create mode 100644 tests/tcg/aarch64/sysregs.c diff --git a/tests/tcg/aarch64/sysregs.c b/tests/tcg/aarch64/sysregs.c new file mode 100644 index 00000000000..40cf8d2877e --- /dev/null +++ b/tests/tcg/aarch64/sysregs.c @@ -0,0 +1,172 @@ +/* + * Check emulated system register access for linux-user mode. + * + * See: https://www.kernel.org/doc/Documentation/arm64/cpu-feature-registers.txt + * + * Copyright (c) 2019 Linaro + * + * This work is licensed under the terms of the GNU GPL, version 2 or later. + * See the COPYING file in the top-level directory. + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include +#include +#include +#include +#include +#include + +#ifndef HWCAP_CPUID +#define HWCAP_CPUID (1 << 11) +#endif + +int failed_bit_count; + +/* Read and print system register `id' value */ +#define get_cpu_reg(id) ({ \ + unsigned long __val = 0xdeadbeef; \ + asm("mrs %0, "#id : "=r" (__val)); \ + printf("%-20s: 0x%016lx\n", #id, __val); \ + __val; \ + }) + +/* As above but also check no bits outside of `mask' are set*/ +#define get_cpu_reg_check_mask(id, mask) ({ \ + unsigned long __cval = get_cpu_reg(id); \ + unsigned long __extra = __cval & ~mask; \ + if (__extra) { \ + printf("%-20s: 0x%016lx\n", " !!extra bits!!", __extra); \ + failed_bit_count++; \ + } \ +}) + +/* As above but check RAZ */ +#define get_cpu_reg_check_zero(id) ({ \ + unsigned long __val = 0xdeadbeef; \ + asm("mrs %0, "#id : "=r" (__val)); \ + if (__val) { \ + printf("%-20s: 0x%016lx (not RAZ!)\n", #id, __val); \ + failed_bit_count++; \ + } \ +}) + +/* Chunk up mask into 63:48, 47:32, 31:16, 15:0 to ease counting */ +#define _m(a, b, c, d) (0x ## a ## b ## c ## d ##ULL) + +bool should_fail; +int should_fail_count; +int should_not_fail_count; +uintptr_t failed_pc[10]; + +void sigill_handler(int signo, siginfo_t *si, void *data) +{ + ucontext_t *uc = (ucontext_t *)data; + + if (should_fail) { + should_fail_count++; + } else { + uintptr_t pc = (uintptr_t) uc->uc_mcontext.pc; + failed_pc[should_not_fail_count++] = pc; + } + uc->uc_mcontext.pc += 4; +} + +int main(void) +{ + struct sigaction sa; + + /* Hook in a SIGILL handler */ + memset(&sa, 0, sizeof(struct sigaction)); + sa.sa_flags = SA_SIGINFO; + sa.sa_sigaction = &sigill_handler; + sigemptyset(&sa.sa_mask); + + if (sigaction(SIGILL, &sa, 0) != 0) { + perror("sigaction"); + return 1; + } + + /* Counter values have been exposed since Linux 4.12 */ + printf("Checking Counter registers\n"); + + get_cpu_reg(ctr_el0); + get_cpu_reg(cntvct_el0); + get_cpu_reg(cntfrq_el0); + + /* HWCAP_CPUID indicates we can read feature registers, since Linux 4.11 */ + if (!(getauxval(AT_HWCAP) & HWCAP_CPUID)) { + printf("CPUID registers unavailable\n"); + return 1; + } else { + printf("Checking CPUID registers\n"); + } + + /* + * Some registers only expose some bits to user-space. Anything + * that is IMPDEF is exported as 0 to user-space. The _mask checks + * assert no extra bits are set. + * + * This check is *not* comprehensive as some fields are set to + * minimum valid fields - for the purposes of this check allowed + * to have non-zero values. + */ + get_cpu_reg_check_mask(id_aa64isar0_el1, _m(00ff,ffff,f0ff,fff0)); + get_cpu_reg_check_mask(id_aa64isar1_el1, _m(0000,00f0,ffff,ffff)); + /* TGran4 & TGran64 as pegged to -1 */ + get_cpu_reg_check_mask(id_aa64mmfr0_el1, _m(0000,0000,ff00,0000)); + get_cpu_reg_check_zero(id_aa64mmfr1_el1); + /* EL1/EL0 reported as AA64 only */ + get_cpu_reg_check_mask(id_aa64pfr0_el1, _m(000f,000f,00ff,0011)); + get_cpu_reg_check_mask(id_aa64pfr1_el1, _m(0000,0000,0000,00f0)); + /* all hidden, DebugVer fixed to 0x6 (ARMv8 debug architecture) */ + get_cpu_reg_check_mask(id_aa64dfr0_el1, _m(0000,0000,0000,0006)); + get_cpu_reg_check_zero(id_aa64dfr1_el1); + get_cpu_reg_check_zero(id_aa64zfr0_el1); + + get_cpu_reg_check_zero(id_aa64afr0_el1); + get_cpu_reg_check_zero(id_aa64afr1_el1); + + get_cpu_reg_check_mask(midr_el1, _m(0000,0000,ffff,ffff)); + /* mpidr sets bit 31, everything else hidden */ + get_cpu_reg_check_mask(mpidr_el1, _m(0000,0000,8000,0000)); + /* REVIDR is all IMPDEF so should be all zeros to user-space */ + get_cpu_reg_check_zero(revidr_el1); + + /* + * There are a block of more registers that are RAZ in the rest of + * the Op0=3, Op1=0, CRn=0, CRm=0,4,5,6,7 space. However for + * brevity we don't check stuff that is currently un-allocated + * here. Feel free to add them ;-) + */ + + printf("Remaining registers should fail\n"); + should_fail = true; + + /* Unexposed register access causes SIGILL */ + get_cpu_reg(id_mmfr0_el1); + get_cpu_reg(id_mmfr1_el1); + get_cpu_reg(id_mmfr2_el1); + get_cpu_reg(id_mmfr3_el1); + + get_cpu_reg(mvfr0_el1); + get_cpu_reg(mvfr1_el1); + + if (should_not_fail_count > 0) { + int i; + for (i = 0; i < should_not_fail_count; i++) { + uintptr_t pc = failed_pc[i]; + uint32_t insn = *(uint32_t *) pc; + printf("insn %#x @ %#lx unexpected FAIL\n", insn, pc); + } + return 1; + } + + if (failed_bit_count > 0) { + printf("Extra information leaked to user-space!\n"); + return 1; + } + + return should_fail_count == 6 ? 0 : 1; +} diff --git a/tests/tcg/aarch64/Makefile.target b/tests/tcg/aarch64/Makefile.target index 96d2321045a..3f8783ada5c 100644 --- a/tests/tcg/aarch64/Makefile.target +++ b/tests/tcg/aarch64/Makefile.target @@ -32,4 +32,10 @@ run-plugin-semihosting-with-%: $(call strip-plugin,$<) 2> $<.err, \ "$< on $(TARGET_NAME) with $*") +ifneq ($(DOCKER_IMAGE)$(CROSS_CC_HAS_SVE),) +# System Registers Tests +AARCH64_TESTS += sysregs +sysregs: CFLAGS+=-march=armv8.1-a+sve +endif + TESTS += $(AARCH64_TESTS) -- 2.20.1 From MAILER-DAEMON Fri Dec 20 07:14:32 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1iiHAu-0000jM-Qa for mharc-qemu-arm@gnu.org; Fri, 20 Dec 2019 07:14:32 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:36262) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iiHAr-0000dp-VJ for qemu-arm@nongnu.org; Fri, 20 Dec 2019 07:14:31 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1iiHAq-0001Fh-Ba for qemu-arm@nongnu.org; Fri, 20 Dec 2019 07:14:29 -0500 Received: from mail-wr1-x442.google.com ([2a00:1450:4864:20::442]:33774) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1iiHAp-00019v-T2 for qemu-arm@nongnu.org; Fri, 20 Dec 2019 07:14:28 -0500 Received: by mail-wr1-x442.google.com with SMTP id b6so9246903wrq.0 for ; Fri, 20 Dec 2019 04:14:27 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=KRu49EbgGVQ7V2rxhXNHs855imxrN5MTwZSo9giC7oo=; b=H7fqNRwdjB5hRPbOqjSzn3+92GkPWo2OL6At9HiFJ849JvF6TXaExMH38Jhn65KSh1 qoPED6b3NLZASeBJKKMcPoWXptmNZglhfPOaQxVR6gLA6Ao5So503ISzRoJZxqKm4PVX X1Qgk/bP5I2fSIFfCxTWiKGLvuYlkan7LYKxQDYCVj+hibAwZ6oThn5C9j5xoh9Wjvl0 3Y60fPxB28nL2F0HMdn1xQgKBOy1ofEXAuapr+thnXdzyMidic8Y125WGysvN1pAD57m PGNArncAjLnLlNYOD2qlV7DZcPbfZHvlNNQGfjXfAqHmBS/35mG2COdGwcLe3XzjFhP9 D1qA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=KRu49EbgGVQ7V2rxhXNHs855imxrN5MTwZSo9giC7oo=; b=NyBaTwWKfrWf/XpMtMxDS2y7mvqhp8IEXo2tWJZabFjcNbC56Ruhj+M9nM7mtRioMi rsaAhQj8g9hi44OB8if5enaxmC+EsMI1BVb9ga7NM0DFvvQLw9iV93yBfXkM+b8jdE3C /1jJI39s0fQMqZqZZ9OWSbjAHXAWcIiiGuDujLzNfTC/cva8FS1ANF989SwLDuQ1PlIF E0bkRIKYRpSh22NhwdD5X5zjks136KhFOTUrFssn3Ek3V9Z1npyrosCIQpegQN2fbZP1 XbJfJ8/iQvHPz/iAryv4yp22mAuzie9feH5qdLfCUfxOWz3Cbj4xWaCmc9g8BMUEsFmI 4h7A== X-Gm-Message-State: APjAAAVRCNEte0DVclDXSb5eNSE9eHJkMMn3l3rkU5wYaOhw/wbc4+al tjFujspJGuur0KYPG0dHrH0/fQ== X-Google-Smtp-Source: APXvYqwG1E79S18wR/U2W5oNawtlyC/jVDVN0LjN5nXvRKi5Yb44+oYVxdxib3HrqULreqS1hJ/W0A== X-Received: by 2002:adf:93c5:: with SMTP id 63mr15130458wrp.236.1576844066353; Fri, 20 Dec 2019 04:14:26 -0800 (PST) Received: from zen.linaroharston ([51.148.130.216]) by smtp.gmail.com with ESMTPSA id f207sm10901781wme.9.2019.12.20.04.14.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 20 Dec 2019 04:14:25 -0800 (PST) Received: from zen.lan (localhost [127.0.0.1]) by zen.linaroharston (Postfix) with ESMTP id 6CBB11FF9E; Fri, 20 Dec 2019 12:04:40 +0000 (GMT) From: =?UTF-8?q?Alex=20Benn=C3=A9e?= To: qemu-devel@nongnu.org Cc: alan.hayward@arm.com, luis.machado@linaro.org, damien.hedde@greensocs.com, =?UTF-8?q?Alex=20Benn=C3=A9e?= , Richard Henderson , Peter Maydell , qemu-arm@nongnu.org (open list:ARM TCG CPUs) Subject: [PATCH v4 14/21] target/arm: don't bother with id_aa64pfr0_read for USER_ONLY Date: Fri, 20 Dec 2019 12:04:31 +0000 Message-Id: <20191220120438.16114-15-alex.bennee@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20191220120438.16114-1-alex.bennee@linaro.org> References: <20191220120438.16114-1-alex.bennee@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::442 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 20 Dec 2019 12:14:31 -0000 For system emulation we need to check the state of the GIC before we report the value. However this isn't relevant to exporting of the value to linux-user and indeed breaks the exported value as set by modify_arm_cp_regs. Signed-off-by: Alex Bennée Reviewed-by: Richard Henderson --- v2 - extend the ifdef and make type CONST with no accessfn --- target/arm/helper.c | 20 +++++++++++++++----- 1 file changed, 15 insertions(+), 5 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 857581feba4..23de21f8820 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -5912,6 +5912,7 @@ static uint64_t id_pfr1_read(CPUARMState *env, const ARMCPRegInfo *ri) return pfr1; } +#ifndef CONFIG_USER_ONLY static uint64_t id_aa64pfr0_read(CPUARMState *env, const ARMCPRegInfo *ri) { ARMCPU *cpu = env_archcpu(env); @@ -5922,6 +5923,7 @@ static uint64_t id_aa64pfr0_read(CPUARMState *env, const ARMCPRegInfo *ri) } return pfr0; } +#endif /* Shared logic between LORID and the rest of the LOR* registers. * Secure state has already been delt with. @@ -6414,16 +6416,24 @@ void register_cp_regs_for_features(ARMCPU *cpu) * define new registers here. */ ARMCPRegInfo v8_idregs[] = { - /* ID_AA64PFR0_EL1 is not a plain ARM_CP_CONST because we don't - * know the right value for the GIC field until after we - * define these regs. + /* + * ID_AA64PFR0_EL1 is not a plain ARM_CP_CONST in system + * emulation because we don't know the right value for the + * GIC field until after we define these regs. */ { .name = "ID_AA64PFR0_EL1", .state = ARM_CP_STATE_AA64, .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 0, - .access = PL1_R, .type = ARM_CP_NO_RAW, + .access = PL1_R, +#ifdef CONFIG_USER_ONLY + .type = ARM_CP_CONST, + .resetvalue = cpu->isar.id_aa64pfr0 +#else + .type = ARM_CP_NO_RAW, .accessfn = access_aa64_tid3, .readfn = id_aa64pfr0_read, - .writefn = arm_cp_write_ignore }, + .writefn = arm_cp_write_ignore +#endif + }, { .name = "ID_AA64PFR1_EL1", .state = ARM_CP_STATE_AA64, .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 1, .access = PL1_R, .type = ARM_CP_CONST, -- 2.20.1 From MAILER-DAEMON Fri Dec 20 07:14:34 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1iiHAv-0000m4-Tk for mharc-qemu-arm@gnu.org; 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Fri, 20 Dec 2019 04:14:25 -0800 (PST) Received: from zen.lan (localhost [127.0.0.1]) by zen.linaroharston (Postfix) with ESMTP id DE3101FFA9; Fri, 20 Dec 2019 12:04:40 +0000 (GMT) From: =?UTF-8?q?Alex=20Benn=C3=A9e?= To: qemu-devel@nongnu.org Cc: alan.hayward@arm.com, luis.machado@linaro.org, damien.hedde@greensocs.com, =?UTF-8?q?Alex=20Benn=C3=A9e?= , Peter Maydell , qemu-arm@nongnu.org (open list:ARM TCG CPUs) Subject: [PATCH v4 19/21] tests/tcg/aarch64: add test-sve-ioctl guest-debug test Date: Fri, 20 Dec 2019 12:04:36 +0000 Message-Id: <20191220120438.16114-20-alex.bennee@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20191220120438.16114-1-alex.bennee@linaro.org> References: <20191220120438.16114-1-alex.bennee@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::341 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 20 Dec 2019 12:14:33 -0000 This test exercises the gdbstub while runing the sve-iotcl test. I haven't plubmed it into make system as we need a way of verifying if gdb has the right support for SVE. Signed-off-by: Alex Bennée --- v4 - interrogate ZCR_EL1 directly as no longer have vg --- tests/tcg/aarch64/gdbstub/test-sve-ioctl.py | 71 +++++++++++++++++++++ 1 file changed, 71 insertions(+) create mode 100644 tests/tcg/aarch64/gdbstub/test-sve-ioctl.py diff --git a/tests/tcg/aarch64/gdbstub/test-sve-ioctl.py b/tests/tcg/aarch64/gdbstub/test-sve-ioctl.py new file mode 100644 index 00000000000..6b6b6c83f2d --- /dev/null +++ b/tests/tcg/aarch64/gdbstub/test-sve-ioctl.py @@ -0,0 +1,71 @@ +from __future__ import print_function +# +# Test the SVE ZReg reports the right amount of data. It uses the +# sve-ioctl test and examines the register data each time the +# __sve_ld_done breakpoint is hit. +# +# This is launched via tests/guest-debug/run-test.py +# + +import gdb + +initial_vlen = 0 +failcount = 0 + +def report(cond, msg): + "Report success/fail of test" + if cond: + print ("PASS: %s" % (msg)) + else: + print ("FAIL: %s" % (msg)) + global failcount + failcount += 1 + +class TestBreakpoint(gdb.Breakpoint): + def __init__(self, sym_name="__sve_ld_done"): + super(TestBreakpoint, self).__init__(sym_name) + # self.sym, ok = gdb.lookup_symbol(sym_name) + + def stop(self): + val_i = gdb.parse_and_eval('i') + global initial_vlen + for i in range(0, int(val_i)): + val_z = gdb.parse_and_eval("$z0.b.u[%d]" % i) + report(int(val_z) == i, "z0.b.u[%d] == %d" % (i, i)) + for i in range(i + 1, initial_vlen): + val_z = gdb.parse_and_eval("$z0.b.u[%d]" % i) + report(int(val_z) == 0, "z0.b.u[%d] == 0" % (i)) + + +def run_test(): + "Run through the tests one by one" + + print ("Setup breakpoint") + bp = TestBreakpoint() + + global initial_vlen + vg = gdb.parse_and_eval("$ZCR_EL1") + initial_vlen = int(vg) * 16 + + gdb.execute("c") + +# +# This runs as the script it sourced (via -x, via run-test.py) +# + +try: + # These are not very useful in scripts + gdb.execute("set pagination off") + gdb.execute("set confirm off") + + # Run the actual tests + run_test() +except: + print ("GDB Exception: %s" % (sys.exc_info()[0])) + failcount += 1 + import code + code.InteractiveConsole(locals=globals()).interact() + raise + +print("All tests complete: %d failures" % failcount) +exit(failcount) -- 2.20.1 From MAILER-DAEMON Fri Dec 20 08:14:41 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1iiI77-0001uI-QG for mharc-qemu-arm@gnu.org; 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Fri, 20 Dec 2019 05:14:32 -0800 (PST) Received: from zen (localhost [127.0.0.1]) by zen.linaroharston (Postfix) with ESMTP id 915261FF87; Fri, 20 Dec 2019 13:14:31 +0000 (GMT) References: <20191211170520.7747-1-alex.bennee@linaro.org> <20191211170520.7747-13-alex.bennee@linaro.org> <69e10c48-8bdf-cbe0-3372-815b647f8312@linaro.org> <87k16sdt4d.fsf@linaro.org> <5c6dd0a9-23ba-63ff-5738-8bac11aad810@linaro.org> User-agent: mu4e 1.3.5; emacs 27.0.50 From: Alex =?utf-8?Q?Benn=C3=A9e?= To: Luis Machado Cc: Richard Henderson , qemu-devel@nongnu.org, alan.hayward@arm.com, damien.hedde@greensocs.com, Peter Maydell , "open list:ARM TCG CPUs" Subject: Re: [PATCH v3 12/20] target/arm: generate xml description of our SVE registers In-reply-to: <5c6dd0a9-23ba-63ff-5738-8bac11aad810@linaro.org> Date: Fri, 20 Dec 2019 13:14:31 +0000 Message-ID: <87eewzdtqg.fsf@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::343 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 20 Dec 2019 13:14:40 -0000 Luis Machado writes: > On 12/19/19 4:15 PM, Alex Benn=C3=A9e wrote: >> Richard Henderson writes: >>=20 >>> On 12/11/19 9:05 AM, Alex Benn=C3=A9e wrote: >>>> +static struct TypeSize vec_lanes[] =3D { >>> >>> const. >>> >>>> + case 51: >>>> + return gdb_get_reg64(buf, (cpu->env.vfp.zcr_el[1] & 0xf) + 1); >>> >>> You need to use sve_zcr_len_for_el to get the effective vq. >>> Also, I thought vg =3D=3D 2 * vq. >>> > + case 51: >>>> + { >>>> + uint64_t val =3D *(uint64_t *) buf; >>>> + cpu->env.vfp.zcr_el[1] =3D (val - 1) & 0xf; >>> >>> You cannot hard-code EL1 without ifdef CONFIG_USER_ONLY. If the effect= ive vq >>> decreases, you must call aarch64_sve_narrow_vq. You must call arm_rebu= ild_hflags. >> I'm just going to drop vg (and therefor the ability to set it) from >> the >> regset. It was only meant to be an indicator and gdb doesn't actually >> look to it to size it's output. The likely dynamic extension will just >> re-transmit the whole XML when a change occurs. >>=20 > > I'd verify with GDB first if vg isn't actually required. It works with my tests but perhaps we use our own namespaced XML rather than the gdbstub XML. > From looking at GDB's code, it does set vg as one of the register > names, and this is regardless of any XML input. It does reference VG=20 > here and there in the code, even though it may not use it to size its > output. But this is all special casing for feature name=3D"org.gnu.gdb.aarch64.sve" right? --=20 Alex Benn=C3=A9e From MAILER-DAEMON Fri Dec 20 08:22:56 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1iiIF6-0007UZ-5m for mharc-qemu-arm@gnu.org; Fri, 20 Dec 2019 08:22:56 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:42448) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iiIF3-0007Rw-7U for qemu-arm@nongnu.org; Fri, 20 Dec 2019 08:22:54 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1iiIF1-0005Qq-RG for qemu-arm@nongnu.org; Fri, 20 Dec 2019 08:22:52 -0500 Received: from mail-wm1-x344.google.com ([2a00:1450:4864:20::344]:55652) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1iiIF1-0005NF-Ev for qemu-arm@nongnu.org; Fri, 20 Dec 2019 08:22:51 -0500 Received: by mail-wm1-x344.google.com with SMTP id q9so8928685wmj.5 for ; Fri, 20 Dec 2019 05:22:51 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=tq4uTuTrF1sjaAQeE45sTsyrBhoioBCJJ0MxAc2jFgg=; b=n2+bLZoXUIjpILnemC+nImUg3xPzAb+dJGK3kwH6yv2Pw7+0XsroNA+cITIssOScdH 5fO9iilbZSj+ygSANDaLmWhOKGTmzyvqJMKRWzHrzyeNZVwUdWY1drgWc5ZAe+F08qyc uu1w+bQecM3O7j2y50K/aQ8OMbs1aE2PhJ3X9tSE3PSh+khjbuv/oOcoZwrDtY6b2BpQ v7RtUSQ3ktfSOtNb1vE5ybW/OA8TFC+Fr12uJR9EEq4Jqv/JKV4qr2CJZmpFj9e0oZE+ Kzg1RFbyL1tvX3qjq+tODsNyIWB7DIYFPA4SOl/P+OUWpbI9aWyepAWBDwRLsobbSN8M nD/A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=tq4uTuTrF1sjaAQeE45sTsyrBhoioBCJJ0MxAc2jFgg=; b=LRikknImaWXY6HRsk0Mkhfi9UTjy5sXyQHNLaAt69cQOPkpQVntn1nS3oMv6MaYwvI 69vcN2goqzv79d1LrRcxMRE63mmli495b8nqifFVd/9kgs6IwRPEE1bNbREH+bBGB4MR QWbtS/rXTxnauMWeqnqa2bI9AjqMsPZdCtrrwy6bFD1L+fNpx6eVoKF8iUOrqWrceaH1 gH65I2ynqCowPHqq2/EOYHuUeDcXRP1Y0RC5XnWy83Gb2sxClhyQCIv5EPTveS7g4n8v q82AyhEYZBcDxTLu/6eQdO7MRXuwVnqLVagdcuapPXC6ZTPC4h6pUND1+SBN2GuPMzJ+ PWCA== X-Gm-Message-State: APjAAAVvpOlntA9GpNgTco8pBaATJ+P5Fsp03X16KVgKqsnVnHKZ2DmJ PUEIj9g1Erm//1URI6TpoyNc3Q3Or1s= X-Google-Smtp-Source: APXvYqwPPRuJrhjFoxxUPR7D/zHH4ZkVaEVPFnI2YqCqBv6g/C/ERIkCv9Gp7rQ8wcBFiSK8lueBlg== X-Received: by 2002:a7b:c216:: with SMTP id x22mr15708176wmi.51.1576848170053; Fri, 20 Dec 2019 05:22:50 -0800 (PST) Received: from zen.linaroharston ([51.148.130.216]) by smtp.gmail.com with ESMTPSA id t1sm9763073wma.43.2019.12.20.05.22.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 20 Dec 2019 05:22:47 -0800 (PST) Received: from zen.lan (localhost [127.0.0.1]) by zen.linaroharston (Postfix) with ESMTP id ABC081FF8C; Fri, 20 Dec 2019 13:22:46 +0000 (GMT) From: =?UTF-8?q?Alex=20Benn=C3=A9e?= To: qemu-devel@nongnu.org Cc: keithp@keithp.com, =?UTF-8?q?Alex=20Benn=C3=A9e?= , Richard Henderson , Peter Maydell , qemu-arm@nongnu.org (open list:ARM TCG CPUs) Subject: [PATCH v2 1/5] target/arm: remove unused EXCP_SEMIHOST leg Date: Fri, 20 Dec 2019 13:22:42 +0000 Message-Id: <20191220132246.6759-2-alex.bennee@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20191220132246.6759-1-alex.bennee@linaro.org> References: <20191220132246.6759-1-alex.bennee@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::344 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 20 Dec 2019 13:22:54 -0000 All semihosting exceptions are dealt with earlier in the common code so we should never get here. Signed-off-by: Alex Bennée Reviewed-by: Richard Henderson Reviewed-by: Keith Packard Tested-by: Keith Packard --- target/arm/helper.c | 6 ------ 1 file changed, 6 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 5074b5f69ca..b4dc2274c8b 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -8554,12 +8554,6 @@ static void arm_cpu_do_interrupt_aarch64(CPUState *cs) case EXCP_VFIQ: addr += 0x100; break; - case EXCP_SEMIHOST: - qemu_log_mask(CPU_LOG_INT, - "...handling as semihosting call 0x%" PRIx64 "\n", - env->xregs[0]); - env->xregs[0] = do_arm_semihosting(env); - return; default: cpu_abort(cs, "Unhandled exception 0x%x\n", cs->exception_index); } -- 2.20.1 From MAILER-DAEMON Fri Dec 20 08:22:56 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1iiIF6-0007V1-Do for mharc-qemu-arm@gnu.org; Fri, 20 Dec 2019 08:22:56 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:42382) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iiIF2-0007Ru-RP for qemu-arm@nongnu.org; Fri, 20 Dec 2019 08:22:54 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1iiIF1-0005P9-0c for qemu-arm@nongnu.org; Fri, 20 Dec 2019 08:22:52 -0500 Received: from mail-wm1-x343.google.com ([2a00:1450:4864:20::343]:52542) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1iiIF0-0005Jn-L9 for qemu-arm@nongnu.org; Fri, 20 Dec 2019 08:22:50 -0500 Received: by mail-wm1-x343.google.com with SMTP id p9so8928355wmc.2 for ; Fri, 20 Dec 2019 05:22:50 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=ovdoYf7CDyOfpwifeooI731QUTwDX4W14EjWn1WUyGo=; b=nUE6pb+O2XFAC6oAOxFwExUDYou7LIo786nSmjUlddRcNzddNEYeFFxianF5IawxwU 9IuUsKaA5o9JPQ64aTV0rR6Ldko71fXr7D/+Wq26rgG9JxhJr6hFScLjRqxPWYJjHavX YlEZkWkK4MGwfroFzlBD/XXxYt85CeZ5/UhSm1JUJthnFDPoosS0drSS72CaOs/tCndz vkUb14CtQ57a+YljskAKWVmgn+6QiNzUSFy1/Gzjk3/KRohoxb7YNrrgvcUa2ZDXWCqR jlqb0HKyBBBoZOC+Km6IIHViLDgHRV1HVY7tzLgnZLgdJGlmoejgt6diU/S/4+PBK/7U OL3Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=ovdoYf7CDyOfpwifeooI731QUTwDX4W14EjWn1WUyGo=; b=oyxXfyWmNn3E2KVEwptqbZQZCEaOIgJBfI1yOI++hOhIYrIK5jgsOdDQebqkkk2aV/ iGYDZSJw95iDvrtMCmYtIMFfKm+ZC2/nCvuSgSck/BGZ1weWhPALlATmJEOn4cMLXPcV 9fP3QU8epkcjEvm6fQPN7oQQWGcY+gcpwOIgkKNQRqn8AIHwhfGbaTsd9+R79rmE8Jyi EtaeKiWPPDqlBTkief7PzXZtIHT/v4oK0uvgJXFQ2DQp5IaCDd3X/NLz/cthSYT/Yo66 aaT0ygg/xK5ebXpWVH5yjfoIoIThgQvoCLHaiTtPUniz2xPGs22/4TMEJr+rzpDTpgJH 2Uyg== X-Gm-Message-State: APjAAAWHIqFn6I7WDDdM/r06pZjd0WeWAb7Q3Xf7PTCicC37bi9GnGij Ht6mw1J39fsDJbU0XBf4LOC/iA== X-Google-Smtp-Source: APXvYqzgEsLHk7u7rRHF4JlGBj4Qdgiz96dtsKDRxiOtOOz/g6qS2KIFeSl6ZXvWBwXYQ+bJ4Caj7A== X-Received: by 2002:a05:600c:1:: with SMTP id g1mr15717810wmc.131.1576848168910; Fri, 20 Dec 2019 05:22:48 -0800 (PST) Received: from zen.linaroharston ([51.148.130.216]) by smtp.gmail.com with ESMTPSA id i11sm9852109wrs.10.2019.12.20.05.22.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 20 Dec 2019 05:22:47 -0800 (PST) Received: from zen.lan (localhost [127.0.0.1]) by zen.linaroharston (Postfix) with ESMTP id C85C41FF8F; Fri, 20 Dec 2019 13:22:46 +0000 (GMT) From: =?UTF-8?q?Alex=20Benn=C3=A9e?= To: qemu-devel@nongnu.org Cc: keithp@keithp.com, =?UTF-8?q?Alex=20Benn=C3=A9e?= , Richard Henderson , Riku Voipio , Laurent Vivier , Peter Maydell , qemu-arm@nongnu.org (open list:ARM TCG CPUs) Subject: [PATCH v2 2/5] target/arm: only update pc after semihosting completes Date: Fri, 20 Dec 2019 13:22:43 +0000 Message-Id: <20191220132246.6759-3-alex.bennee@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20191220132246.6759-1-alex.bennee@linaro.org> References: <20191220132246.6759-1-alex.bennee@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::343 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 20 Dec 2019 13:22:54 -0000 Before we introduce blocking semihosting calls we need to ensure we can restart the system on semi hosting exception. To be able to do this the EXCP_SEMIHOST operation should be idempotent until it finally completes. Practically this means ensureing we only update the pc after the semihosting call has completed. Signed-off-by: Alex Bennée Reviewed-by: Richard Henderson Reviewed-by: Keith Packard Tested-by: Keith Packard --- linux-user/aarch64/cpu_loop.c | 1 + linux-user/arm/cpu_loop.c | 1 + target/arm/helper.c | 2 ++ target/arm/m_helper.c | 1 + target/arm/translate-a64.c | 2 +- target/arm/translate.c | 6 +++--- 6 files changed, 9 insertions(+), 4 deletions(-) diff --git a/linux-user/aarch64/cpu_loop.c b/linux-user/aarch64/cpu_loop.c index 31c845a70d4..bbe9fefca81 100644 --- a/linux-user/aarch64/cpu_loop.c +++ b/linux-user/aarch64/cpu_loop.c @@ -130,6 +130,7 @@ void cpu_loop(CPUARMState *env) break; case EXCP_SEMIHOST: env->xregs[0] = do_arm_semihosting(env); + env->pc += 4; break; case EXCP_YIELD: /* nothing to do here for user-mode, just resume guest code */ diff --git a/linux-user/arm/cpu_loop.c b/linux-user/arm/cpu_loop.c index 7be40717518..1fae90c6dfc 100644 --- a/linux-user/arm/cpu_loop.c +++ b/linux-user/arm/cpu_loop.c @@ -377,6 +377,7 @@ void cpu_loop(CPUARMState *env) break; case EXCP_SEMIHOST: env->regs[0] = do_arm_semihosting(env); + env->regs[15] += env->thumb ? 2 : 4; break; case EXCP_INTERRUPT: /* just indicate that signals should be handled asap */ diff --git a/target/arm/helper.c b/target/arm/helper.c index b4dc2274c8b..088e2693df8 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -8602,11 +8602,13 @@ static void handle_semihosting(CPUState *cs) "...handling as semihosting call 0x%" PRIx64 "\n", env->xregs[0]); env->xregs[0] = do_arm_semihosting(env); + env->pc += 4; } else { qemu_log_mask(CPU_LOG_INT, "...handling as semihosting call 0x%x\n", env->regs[0]); env->regs[0] = do_arm_semihosting(env); + env->regs[15] += env->thumb ? 2 : 4; } } #endif diff --git a/target/arm/m_helper.c b/target/arm/m_helper.c index 76de317e6af..33d414a684b 100644 --- a/target/arm/m_helper.c +++ b/target/arm/m_helper.c @@ -2185,6 +2185,7 @@ void arm_v7m_cpu_do_interrupt(CPUState *cs) "...handling as semihosting call 0x%x\n", env->regs[0]); env->regs[0] = do_arm_semihosting(env); + env->regs[15] += env->thumb ? 2 : 4; return; case EXCP_BKPT: armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_DEBUG, false); diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index d4bebbe6295..972c28c3c95 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -1937,7 +1937,7 @@ static void disas_exc(DisasContext *s, uint32_t insn) break; } #endif - gen_exception_internal_insn(s, s->base.pc_next, EXCP_SEMIHOST); + gen_exception_internal_insn(s, s->pc_curr, EXCP_SEMIHOST); } else { unsupported_encoding(s, insn); } diff --git a/target/arm/translate.c b/target/arm/translate.c index 2b6c1f91bf9..5185e08641b 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -1124,7 +1124,7 @@ static inline void gen_hlt(DisasContext *s, int imm) s->current_el != 0 && #endif (imm == (s->thumb ? 0x3c : 0xf000))) { - gen_exception_internal_insn(s, s->base.pc_next, EXCP_SEMIHOST); + gen_exception_internal_insn(s, s->pc_curr, EXCP_SEMIHOST); return; } @@ -8457,7 +8457,7 @@ static bool trans_BKPT(DisasContext *s, arg_BKPT *a) !IS_USER(s) && #endif (a->imm == 0xab)) { - gen_exception_internal_insn(s, s->base.pc_next, EXCP_SEMIHOST); + gen_exception_internal_insn(s, s->pc_curr, EXCP_SEMIHOST); } else { gen_exception_bkpt_insn(s, syn_aa32_bkpt(a->imm, false)); } @@ -10266,7 +10266,7 @@ static bool trans_SVC(DisasContext *s, arg_SVC *a) !IS_USER(s) && #endif (a->imm == semihost_imm)) { - gen_exception_internal_insn(s, s->base.pc_next, EXCP_SEMIHOST); + gen_exception_internal_insn(s, s->pc_curr, EXCP_SEMIHOST); } else { gen_set_pc_im(s, s->base.pc_next); s->svc_imm = a->imm; -- 2.20.1 From MAILER-DAEMON Fri Dec 20 08:23:01 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1iiIFA-0007f0-VE for mharc-qemu-arm@gnu.org; Fri, 20 Dec 2019 08:23:00 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:42870) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iiIF6-0007Ur-7Z for qemu-arm@nongnu.org; Fri, 20 Dec 2019 08:22:58 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1iiIF4-0005YS-AH for qemu-arm@nongnu.org; Fri, 20 Dec 2019 08:22:56 -0500 Received: from mail-wr1-x441.google.com ([2a00:1450:4864:20::441]:42493) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1iiIF3-0005V8-UC for qemu-arm@nongnu.org; Fri, 20 Dec 2019 08:22:54 -0500 Received: by mail-wr1-x441.google.com with SMTP id q6so9377345wro.9 for ; Fri, 20 Dec 2019 05:22:53 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=hcqHu7KDcCniaxK/ApCQCt8iC+h5jHtgiGByxeELqFg=; b=f5v+1xGr4FBueJFTCDKKxXapZ2QxRklVXyYs6w5KH7F4tMYnf9tSQTq2cTw+aUozv9 DZmQ9oV7mWaniO8Mn0DebpPisqwYWmu+x8W7Jd7vuchP6uuMG3to1RP6cl4nNkn2ix5/ XTM/thSTKS0AY3NVJz1JoCl3ANKpLGGlT+dwKrbMrid4bMMqE9AYFCQB+nv78a2y6XHP qLxcaCKZUtDjiX3zwDwNPLLTuZMpJiwIOTxiqB4kZhr/H37cNtM9D38tGYJWsjreiTxD 0Xzt9Tesjt6SzyEHIUPdVErt/N9yv56EaktqnAejYDQ6U6IvMQcr4kBJbP14a8aipNk0 746g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=hcqHu7KDcCniaxK/ApCQCt8iC+h5jHtgiGByxeELqFg=; b=EaGCYF7z224otwIdXpTngFpIVCip09Zwe04MpjhKP8z4sZtq6m/LignnFuhroiQaB6 TE0+0s0MrHLGa11TMsw0m5ARWaKVgWHO9TJrYqKVYeAepgo57dgpuBkjiuRwsKwBTqDf Lfn5W8t7Tf91jZPIbeSFvMs3txhTtt6nveDvis9JeFb9/zkQ8Nf+7ik+SatvnUCjd7On q+WRHsjv/YsDeBNEIQe0KasqrHz6c2Im3JjQYpVrvCD1K5+awid396vR4gNSL/vl5bJz MLxaUq16W5SyhjKhoUp4uIE7pnwRnub2VzzxOqMY46PYwJR964wv/YFEty78YSN4lIFa sMUQ== X-Gm-Message-State: APjAAAV+PJRC6Ggvhp9iYOzyt4wrmU840zykOuWcA0PVTMEXYauXnChf idcCKtlHia39NTAfI7c3VasPOQ== X-Google-Smtp-Source: APXvYqzuAZWcvG4klfykSoXsgbBsdiDzg4FmbhTHT8UHzQUwjDTjupgb384O4iSUsZbJVVUmVsTpvw== X-Received: by 2002:a5d:6692:: with SMTP id l18mr16289208wru.382.1576848172572; Fri, 20 Dec 2019 05:22:52 -0800 (PST) Received: from zen.linaroharston ([51.148.130.216]) by smtp.gmail.com with ESMTPSA id 25sm9240360wmi.32.2019.12.20.05.22.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 20 Dec 2019 05:22:47 -0800 (PST) Received: from zen.lan (localhost [127.0.0.1]) by zen.linaroharston (Postfix) with ESMTP id E8DB51FF90; Fri, 20 Dec 2019 13:22:46 +0000 (GMT) From: =?UTF-8?q?Alex=20Benn=C3=A9e?= To: qemu-devel@nongnu.org Cc: keithp@keithp.com, =?UTF-8?q?Alex=20Benn=C3=A9e?= , Paolo Bonzini , Riku Voipio , Laurent Vivier , Peter Maydell , qemu-arm@nongnu.org (open list:ARM TCG CPUs) Subject: [PATCH v2 3/5] semihosting: add qemu_semihosting_console_inc for SYS_READC Date: Fri, 20 Dec 2019 13:22:44 +0000 Message-Id: <20191220132246.6759-4-alex.bennee@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20191220132246.6759-1-alex.bennee@linaro.org> References: <20191220132246.6759-1-alex.bennee@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::441 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 20 Dec 2019 13:22:59 -0000 From: Keith Packard Provides a blocking call to read a character from the console using semihosting.chardev, if specified. This takes some careful command line options to use stdio successfully as the serial ports, monitor and semihost all want to use stdio. Here's a sample set of command line options which share stdio between semihost, monitor and serial ports: qemu \ -chardev stdio,mux=on,id=stdio0 \ -serial chardev:stdio0 \ -semihosting-config enable=on,chardev=stdio0 \ -mon chardev=stdio0,mode=readline This creates a chardev hooked to stdio and then connects all of the subsystems to it. A shorter mechanism would be good to hear about. Signed-off-by: Keith Packard Message-Id: <20191104204230.12249-1-keithp@keithp.com> [AJB: fixed up deadlock, minor commit title reword] Signed-off-by: Alex Bennée Cc: Paolo Bonzini Reviewed-by: Keith Packard Tested-by: Keith Packard --- v8 - allow linux-user to block using unbuffered IO - spelling and wording fixes v7 - reword commit title - remove mutexs, halt CPU until data available - document cpu_loop_exit behavior in function API squash! semihosting: add qemu_semihosting_console_inc for SYS_READC --- include/hw/semihosting/console.h | 16 +++++++ include/hw/semihosting/semihost.h | 4 ++ hw/semihosting/console.c | 79 +++++++++++++++++++++++++++++++ linux-user/arm/semihost.c | 27 +++++++++++ stubs/semihost.c | 4 ++ target/arm/arm-semi.c | 3 +- vl.c | 3 ++ 7 files changed, 134 insertions(+), 2 deletions(-) diff --git a/include/hw/semihosting/console.h b/include/hw/semihosting/console.h index 9be9754bcdf..0238f540f4b 100644 --- a/include/hw/semihosting/console.h +++ b/include/hw/semihosting/console.h @@ -37,6 +37,22 @@ int qemu_semihosting_console_outs(CPUArchState *env, target_ulong s); */ void qemu_semihosting_console_outc(CPUArchState *env, target_ulong c); +/** + * qemu_semihosting_console_inc: + * @env: CPUArchState + * + * Receive single character from debug console. This may be the remote + * gdb session if a softmmu guest is currently being debugged. As this + * call may block if no data is available we suspend the CPU and will + * re-execute the instruction when data is there. Therefore two + * conditions must be met: + * - CPUState is synchronized before calling this function + * - pc is only updated once the character is successfully returned + * + * Returns: character read OR cpu_loop_exit! + */ +target_ulong qemu_semihosting_console_inc(CPUArchState *env); + /** * qemu_semihosting_log_out: * @s: pointer to string diff --git a/include/hw/semihosting/semihost.h b/include/hw/semihosting/semihost.h index 60fc42d851e..b8ce5117ae0 100644 --- a/include/hw/semihosting/semihost.h +++ b/include/hw/semihosting/semihost.h @@ -56,6 +56,9 @@ static inline Chardev *semihosting_get_chardev(void) { return NULL; } +static inline void qemu_semihosting_console_init(void) +{ +} #else /* !CONFIG_USER_ONLY */ bool semihosting_enabled(void); SemihostingTarget semihosting_get_target(void); @@ -68,6 +71,7 @@ Chardev *semihosting_get_chardev(void); void qemu_semihosting_enable(void); int qemu_semihosting_config_options(const char *opt); void qemu_semihosting_connect_chardevs(void); +void qemu_semihosting_console_init(void); #endif /* CONFIG_USER_ONLY */ #endif /* SEMIHOST_H */ diff --git a/hw/semihosting/console.c b/hw/semihosting/console.c index b4b17c8afbc..6346bd7f506 100644 --- a/hw/semihosting/console.c +++ b/hw/semihosting/console.c @@ -20,8 +20,15 @@ #include "hw/semihosting/semihost.h" #include "hw/semihosting/console.h" #include "exec/gdbstub.h" +#include "exec/exec-all.h" #include "qemu/log.h" #include "chardev/char.h" +#include +#include "chardev/char-fe.h" +#include "sysemu/sysemu.h" +#include "qemu/main-loop.h" +#include "qapi/error.h" +#include "qemu/fifo8.h" int qemu_semihosting_log_out(const char *s, int len) { @@ -98,3 +105,75 @@ void qemu_semihosting_console_outc(CPUArchState *env, target_ulong addr) __func__, addr); } } + +#define FIFO_SIZE 1024 + +/* Access to this structure is protected by the BQL */ +typedef struct SemihostingConsole { + CharBackend backend; + GSList *sleeping_cpus; + bool got; + Fifo8 fifo; +} SemihostingConsole; + +static SemihostingConsole console; + +static int console_can_read(void *opaque) +{ + SemihostingConsole *c = opaque; + int ret; + g_assert(qemu_mutex_iothread_locked()); + ret = (int) fifo8_num_free(&c->fifo); + return ret; +} + +static void console_wake_up(gpointer data, gpointer user_data) +{ + CPUState *cs = (CPUState *) data; + /* cpu_handle_halt won't know we have work so just unbung here */ + cs->halted = 0; + qemu_cpu_kick(cs); +} + +static void console_read(void *opaque, const uint8_t *buf, int size) +{ + SemihostingConsole *c = opaque; + g_assert(qemu_mutex_iothread_locked()); + while (size-- && !fifo8_is_full(&c->fifo)) { + fifo8_push(&c->fifo, *buf++); + } + g_slist_foreach(c->sleeping_cpus, console_wake_up, NULL); + c->sleeping_cpus = NULL; +} + +target_ulong qemu_semihosting_console_inc(CPUArchState *env) +{ + uint8_t ch; + SemihostingConsole *c = &console; + g_assert(qemu_mutex_iothread_locked()); + g_assert(current_cpu); + if (fifo8_is_empty(&c->fifo)) { + c->sleeping_cpus = g_slist_prepend(c->sleeping_cpus, current_cpu); + current_cpu->halted = 1; + current_cpu->exception_index = EXCP_HALTED; + cpu_loop_exit(current_cpu); + /* never returns */ + } + ch = fifo8_pop(&c->fifo); + return (target_ulong) ch; +} + +void qemu_semihosting_console_init(void) +{ + Chardev *chr = semihosting_get_chardev(); + + if (chr) { + fifo8_create(&console.fifo, FIFO_SIZE); + qemu_chr_fe_init(&console.backend, chr, &error_abort); + qemu_chr_fe_set_handlers(&console.backend, + console_can_read, + console_read, + NULL, NULL, &console, + NULL, true); + } +} diff --git a/linux-user/arm/semihost.c b/linux-user/arm/semihost.c index a16b525eec0..a1f0f6050ea 100644 --- a/linux-user/arm/semihost.c +++ b/linux-user/arm/semihost.c @@ -14,6 +14,7 @@ #include "cpu.h" #include "hw/semihosting/console.h" #include "qemu.h" +#include int qemu_semihosting_console_outs(CPUArchState *env, target_ulong addr) { @@ -47,3 +48,29 @@ void qemu_semihosting_console_outc(CPUArchState *env, target_ulong addr) } } } + +/* + * For linux-user we can safely block. However as we want to return as + * soon as a character is read we need to tweak the termio to disable + * line buffering. We restore the old mode afterwards in case the + * program is expecting more normal behaviour. This is slow but + * nothing using semihosting console reading is expecting to be fast. + */ +target_ulong qemu_semihosting_console_inc(CPUArchState *env) +{ + uint8_t c; + struct termios old_tio, new_tio; + + /* Disable line-buffering and echo */ + tcgetattr(STDIN_FILENO, &old_tio); + new_tio = old_tio; + new_tio.c_lflag &= (~ICANON & ~ECHO); + tcsetattr(STDIN_FILENO, TCSANOW, &new_tio); + + c = getchar(); + + /* restore config */ + tcsetattr(STDIN_FILENO, TCSANOW, &old_tio); + + return (target_ulong) c; +} diff --git a/stubs/semihost.c b/stubs/semihost.c index f90589259c0..1d8b37f7b2f 100644 --- a/stubs/semihost.c +++ b/stubs/semihost.c @@ -69,3 +69,7 @@ void semihosting_arg_fallback(const char *file, const char *cmd) void qemu_semihosting_connect_chardevs(void) { } + +void qemu_semihosting_console_init(void) +{ +} diff --git a/target/arm/arm-semi.c b/target/arm/arm-semi.c index 6f7b6d801bf..47d61f6fe1f 100644 --- a/target/arm/arm-semi.c +++ b/target/arm/arm-semi.c @@ -802,8 +802,7 @@ target_ulong do_arm_semihosting(CPUARMState *env) return guestfd_fns[gf->type].readfn(cpu, gf, arg1, len); case TARGET_SYS_READC: - qemu_log_mask(LOG_UNIMP, "%s: SYS_READC not implemented", __func__); - return 0; + return qemu_semihosting_console_inc(env); case TARGET_SYS_ISTTY: GET_ARG(0); diff --git a/vl.c b/vl.c index 94508300c3c..1912f87822b 100644 --- a/vl.c +++ b/vl.c @@ -4142,6 +4142,9 @@ int main(int argc, char **argv, char **envp) qemu_opts_foreach(qemu_find_opts("mon"), mon_init_func, NULL, &error_fatal); + /* connect semihosting console input if requested */ + qemu_semihosting_console_init(); + if (foreach_device_config(DEV_SERIAL, serial_parse) < 0) exit(1); if (foreach_device_config(DEV_PARALLEL, parallel_parse) < 0) -- 2.20.1 From MAILER-DAEMON Fri Dec 20 08:23:01 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1iiIFB-0007fV-4R for mharc-qemu-arm@gnu.org; Fri, 20 Dec 2019 08:23:01 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:42982) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iiIF6-0007Wb-Sb for qemu-arm@nongnu.org; Fri, 20 Dec 2019 08:22:58 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1iiIF5-0005cs-H6 for qemu-arm@nongnu.org; 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Fri, 20 Dec 2019 05:22:47 -0800 (PST) Received: from zen.lan (localhost [127.0.0.1]) by zen.linaroharston (Postfix) with ESMTP id 0C7811FF91; Fri, 20 Dec 2019 13:22:47 +0000 (GMT) From: =?UTF-8?q?Alex=20Benn=C3=A9e?= To: qemu-devel@nongnu.org Cc: keithp@keithp.com, =?UTF-8?q?Alex=20Benn=C3=A9e?= , Richard Henderson , Peter Maydell , qemu-arm@nongnu.org (open list:ARM TCG CPUs) Subject: [PATCH v2 4/5] tests/tcg: add a dumb-as-bricks semihosting console test Date: Fri, 20 Dec 2019 13:22:45 +0000 Message-Id: <20191220132246.6759-5-alex.bennee@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20191220132246.6759-1-alex.bennee@linaro.org> References: <20191220132246.6759-1-alex.bennee@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::444 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 20 Dec 2019 13:22:59 -0000 We don't run this during check-tcg as we would need to check stuff is echoed back. However we can still build the binary so people can test it manually. Signed-off-by: Alex Bennée Reviewed-by: Richard Henderson --- v8 - actually return the result! --- tests/tcg/aarch64/system/semiconsole.c | 38 +++++++++++++++++++++++ tests/tcg/aarch64/Makefile.softmmu-target | 9 +++++- 2 files changed, 46 insertions(+), 1 deletion(-) create mode 100644 tests/tcg/aarch64/system/semiconsole.c diff --git a/tests/tcg/aarch64/system/semiconsole.c b/tests/tcg/aarch64/system/semiconsole.c new file mode 100644 index 00000000000..bfe7c9e26b4 --- /dev/null +++ b/tests/tcg/aarch64/system/semiconsole.c @@ -0,0 +1,38 @@ +/* + * Semihosting Console Test + * + * Copyright (c) 2019 Linaro Ltd + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include +#include + +#define SYS_READC 0x7 + +uintptr_t __semi_call(uintptr_t type, uintptr_t arg0) +{ + register uintptr_t t asm("x0") = type; + register uintptr_t a0 asm("x1") = arg0; + asm("hlt 0xf000" + : "=r" (t) + : "r" (t), "r" (a0)); + + return t; +} + +int main(void) +{ + char c; + + ml_printf("Semihosting Console Test\n"); + ml_printf("hit X to exit:"); + + do { + c = __semi_call(SYS_READC, 0); + __sys_outc(c); + } while (c != 'X'); + + return 0; +} diff --git a/tests/tcg/aarch64/Makefile.softmmu-target b/tests/tcg/aarch64/Makefile.softmmu-target index 950dbb4bac2..9bdcfd9e7e4 100644 --- a/tests/tcg/aarch64/Makefile.softmmu-target +++ b/tests/tcg/aarch64/Makefile.softmmu-target @@ -31,7 +31,14 @@ LDFLAGS+=-static -nostdlib $(CRT_OBJS) $(MINILIB_OBJS) -lgcc memory: CFLAGS+=-DCHECK_UNALIGNED=1 # Running -QEMU_OPTS+=-M virt -cpu max -display none -semihosting-config enable=on,target=native,chardev=output -kernel +QEMU_BASE_MACHINE=-M virt -cpu max -display none +QEMU_OPTS+=$(QEMU_BASE_MACHINE) -semihosting-config enable=on,target=native,chardev=output -kernel + +# console test is manual only +QEMU_SEMIHOST=-chardev stdio,mux=on,id=stdio0 -semihosting-config enable=on,chardev=stdio0 -mon chardev=stdio0,mode=readline +run-semiconsole: QEMU_OPTS=$(QEMU_BASE_MACHINE) $(QEMU_SEMIHOST) -kernel +run-semiconsole: semiconsole + $(call skip-test, $<, "MANUAL ONLY") # Simple Record/Replay Test .PHONY: memory-record -- 2.20.1 From MAILER-DAEMON Fri Dec 20 08:23:02 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1iiIFC-0007iD-Ch for mharc-qemu-arm@gnu.org; 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Fri, 20 Dec 2019 05:22:53 -0800 (PST) Received: from zen.lan (localhost [127.0.0.1]) by zen.linaroharston (Postfix) with ESMTP id 259591FF92; Fri, 20 Dec 2019 13:22:47 +0000 (GMT) From: =?UTF-8?q?Alex=20Benn=C3=A9e?= To: qemu-devel@nongnu.org Cc: keithp@keithp.com, =?UTF-8?q?Alex=20Benn=C3=A9e?= , Peter Maydell , qemu-arm@nongnu.org (open list:ARM TCG CPUs) Subject: [PATCH v2 5/5] tests/tcg: add user version of dumb-as-bricks semiconsole test Date: Fri, 20 Dec 2019 13:22:46 +0000 Message-Id: <20191220132246.6759-6-alex.bennee@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20191220132246.6759-1-alex.bennee@linaro.org> References: <20191220132246.6759-1-alex.bennee@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::330 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 20 Dec 2019 13:23:00 -0000 There are linux-user users of semihosting so we'd better check things work for them as well. Signed-off-by: Alex Bennée --- tests/tcg/arm/semiconsole.c | 47 +++++++++++++++++++++++++++++++++++ tests/tcg/arm/Makefile.target | 7 ++++++ 2 files changed, 54 insertions(+) create mode 100644 tests/tcg/arm/semiconsole.c diff --git a/tests/tcg/arm/semiconsole.c b/tests/tcg/arm/semiconsole.c new file mode 100644 index 00000000000..cc9266b87df --- /dev/null +++ b/tests/tcg/arm/semiconsole.c @@ -0,0 +1,47 @@ +/* + * linux-user semihosting console + * + * Copyright (c) 2019 + * Written by Alex Bennée + * + * SPDX-License-Identifier: GPL-3.0-or-later + */ + +#include +#include + +#define SYS_READC 0x7 + +uintptr_t __semi_call(uintptr_t type, uintptr_t arg0) +{ +#if defined(__arm__) + register uintptr_t t asm("r0") = type; + register uintptr_t a0 asm("r1") = arg0; + asm("svc 0xab" + : "=r" (t) + : "r" (t), "r" (a0)); +#else + register uintptr_t t asm("x0") = type; + register uintptr_t a0 asm("x1") = arg0; + asm("hlt 0xf000" + : "=r" (t) + : "r" (t), "r" (a0)); +#endif + + return t; +} + +int main(void) +{ + char c; + + printf("Semihosting Console Test\n"); + printf("hit X to exit:"); + + do { + c = __semi_call(SYS_READC, 0); + printf("got '%c'\n", c); + } while (c != 'X'); + + return 0; +} diff --git a/tests/tcg/arm/Makefile.target b/tests/tcg/arm/Makefile.target index 0765f37ff04..997e6e78ed9 100644 --- a/tests/tcg/arm/Makefile.target +++ b/tests/tcg/arm/Makefile.target @@ -40,6 +40,13 @@ run-plugin-semihosting-with-%: $(call strip-plugin,$<) 2> $<.err, \ "$< on $(TARGET_NAME) with $*") +ARM_TESTS += semiconsole +run-semiconsole: semiconsole + $(call skip-test, $<, "MANUAL ONLY") + +run-semiconsole-with-%: + $(call skip-test, $<, "MANUAL ONLY") + TESTS += $(ARM_TESTS) # On ARM Linux only supports 4k pages -- 2.20.1 From MAILER-DAEMON Fri Dec 20 08:32:46 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1iiIOc-0003P6-01 for mharc-qemu-arm@gnu.org; Fri, 20 Dec 2019 08:32:46 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:46413) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iiIOR-0003Ku-Mt for qemu-arm@nongnu.org; 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Fri, 20 Dec 2019 05:32:23 -0800 (PST) X-Google-Smtp-Source: APXvYqxzNNKy3nwyIyaRG68ex95G+yRBCxBbFtkyPOP+yD/WrT3Ctc5S07fpiFH6Itusz2nOMfpdiy2YiQvieMeAdbs= X-Received: by 2002:a9d:730e:: with SMTP id e14mr14225352otk.62.1576848743262; Fri, 20 Dec 2019 05:32:23 -0800 (PST) MIME-Version: 1.0 References: <20191218172009.8868-1-philmd@redhat.com> In-Reply-To: <20191218172009.8868-1-philmd@redhat.com> From: =?UTF-8?B?TWFyYy1BbmRyw6kgTHVyZWF1?= Date: Fri, 20 Dec 2019 17:32:11 +0400 Message-ID: Subject: Re: [PATCH v2 00/14] chardev: Use QEMUChrEvent enum in IOEventHandler typedef To: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= Cc: qemu-devel , "Gonglei (Arei)" , Paolo Bonzini , =?UTF-8?B?QWxleCBCZW5uw6ll?= , Andrzej Zaborowski , Peter Maydell , "Michael S. Tsirkin" , Kevin Wolf , Max Reitz , "Edgar E. Iglesias" , Alistair Francis , Antony Pavlov , Igor Mitsyanko , Fabien Chouteau , KONRAD Frederic , Peter Chubb , Alberto Garcia , Michael Walle , Thomas Huth , Joel Stanley , Cornelia Huck , Halil Pasic , Christian Borntraeger , Laurent Vivier , Amit Shah , Corey Minyard , Paul Burton , Aleksandar Rikalo , Aurelien Jarno , Aleksandar Markovic , Palmer Dabbelt , Sagar Karandikar , Bastian Koppelmann , Gerd Hoffmann , Samuel Thibault , "Dr. David Alan Gilbert" , Markus Armbruster , Zhang Chen , Li Zhijian , Jason Wang , qemu-arm , qemu-block , qemu-s390x@nongnu.org, qemu-riscv@nongnu.org X-MC-Unique: 69FMHjRKM-GebQ6qtWKSww-1 X-Mimecast-Spam-Score: 0 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 205.139.110.61 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 20 Dec 2019 13:32:40 -0000 On Wed, Dec 18, 2019 at 9:20 PM Philippe Mathieu-Daud=C3=A9 wrote: > > Hi, > > After this chat on #qemu IRC: > 13:20 so what is the difference between a IOReadHandler and IOE= ventHandler? > 13:25 stsquad: one is in-band and the other out-of-band? > 13:26 f4bug: ahh yes it seems so - connect/disconnect etc... > 13:27 see QEMUChrEvent for IOEventHandler > > I thought it might be a good opportunity to make the IOEventHandler > typedef meaning more obvious, by using the QEMUChrEvent enum. > > To be able to build I had to explicit all enums ignored in the > switch(event) statement by these frontends. > > Then I used a coccinelle spatch to change the various IOEventHandler. > I don't think the last patch can be split, but suggestions are welcome! > > Regards, > > Phil. > > v2: > - do blindly ignore all events using a 'default' case. > > Philippe Mathieu-Daud=C3=A9 (14): > hw/ipmi: Remove unnecessary declarations > hw/ipmi: Explicit we ignore some QEMUChrEvent in IOEventHandler > hw/char/terminal3270: Explicit ignored QEMUChrEvent in IOEventHandler > hw/usb/dev-serial: Explicit we ignore few QEMUChrEvent in IOEventHandle= r > hw/usb/redirect: Explicit we ignore few QEMUChrEvent in IOEventHandler > ccid-card-passthru: Explicit we ignore QEMUChrEvent in IOEventHandler > vhost-user-crypto: Explicit we ignore some QEMUChrEvent in IOEventHandl= er > vhost-user-net: Explicit we ignore few QEMUChrEvent in IOEventHandler > vhost-user-blk: Explicit we ignore few QEMUChrEvent in IOEventHandler > virtio-console: Explicit we ignore some QEMUChrEvent in IOEventHandler > monitor/qmp: Explicit we ignore few QEMUChrEvent in IOEventHandler > monitor/hmp: Explicit we ignore a QEMUChrEvent in IOEventHandler > chardev/char: Explicit we ignore some QEMUChrEvent in IOEventHandler > chardev: Use QEMUChrEvent enum in IOEventHandler typedef Reviewed-by: Marc-Andr=C3=A9 Lureau (I guess Paolo will take the series for next PR?) > > include/chardev/char-fe.h | 2 +- > include/chardev/char-mux.h | 2 +- > include/chardev/char.h | 4 ++-- > backends/cryptodev-vhost-user.c | 7 ++++++- > chardev/char-mux.c | 8 ++++---- > chardev/char.c | 9 +++++++-- > gdbstub.c | 2 +- > hw/arm/pxa2xx.c | 2 +- > hw/arm/strongarm.c | 2 +- > hw/block/vhost-user-blk.c | 7 ++++++- > hw/char/cadence_uart.c | 2 +- > hw/char/digic-uart.c | 2 +- > hw/char/escc.c | 2 +- > hw/char/etraxfs_ser.c | 2 +- > hw/char/exynos4210_uart.c | 2 +- > hw/char/grlib_apbuart.c | 2 +- > hw/char/imx_serial.c | 2 +- > hw/char/ipoctal232.c | 2 +- > hw/char/lm32_juart.c | 2 +- > hw/char/lm32_uart.c | 2 +- > hw/char/mcf_uart.c | 2 +- > hw/char/milkymist-uart.c | 2 +- > hw/char/nrf51_uart.c | 2 +- > hw/char/pl011.c | 2 +- > hw/char/serial.c | 2 +- > hw/char/sh_serial.c | 2 +- > hw/char/terminal3270.c | 7 ++++++- > hw/char/virtio-console.c | 7 ++++++- > hw/char/xilinx_uartlite.c | 2 +- > hw/ipmi/ipmi_bmc_extern.c | 12 +++++++----- > hw/mips/boston.c | 2 +- > hw/mips/mips_malta.c | 2 +- > hw/riscv/riscv_htif.c | 2 +- > hw/riscv/sifive_uart.c | 2 +- > hw/usb/ccid-card-passthru.c | 7 ++++++- > hw/usb/dev-serial.c | 6 +++++- > hw/usb/redirect.c | 7 ++++++- > monitor/hmp.c | 6 +++++- > monitor/qmp.c | 7 ++++++- > net/filter-mirror.c | 2 +- > net/vhost-user.c | 9 +++++++-- > qtest.c | 2 +- > tests/test-char.c | 6 +++--- > tests/vhost-user-test.c | 2 +- > 44 files changed, 111 insertions(+), 56 deletions(-) > > Cc: "Gonglei (Arei)" > Cc: "Marc-Andr=C3=A9 Lureau" > Cc: Paolo Bonzini > Cc: "Alex Benn=C3=A9e" > Cc: "Philippe Mathieu-Daud=C3=A9" > Cc: Andrzej Zaborowski > Cc: Peter Maydell > Cc: "Michael S. Tsirkin" > Cc: Kevin Wolf > Cc: Max Reitz > Cc: "Edgar E. Iglesias" > Cc: Alistair Francis > Cc: Antony Pavlov > Cc: Igor Mitsyanko > Cc: Fabien Chouteau > Cc: KONRAD Frederic > Cc: Peter Chubb > Cc: Alberto Garcia > Cc: Michael Walle > Cc: Thomas Huth > Cc: Joel Stanley > Cc: Cornelia Huck > Cc: Halil Pasic > Cc: Christian Borntraeger > Cc: Laurent Vivier > Cc: Amit Shah > Cc: Corey Minyard > Cc: Paul Burton > Cc: Aleksandar Rikalo > Cc: Aurelien Jarno > Cc: Aleksandar Markovic > Cc: Palmer Dabbelt > Cc: Sagar Karandikar > Cc: Bastian Koppelmann > Cc: Gerd Hoffmann > Cc: Samuel Thibault > Cc: "Dr. David Alan Gilbert" > Cc: Markus Armbruster > Cc: Zhang Chen > Cc: Li Zhijian > Cc: Jason Wang > Cc: qemu-arm@nongnu.org > Cc: qemu-block@nongnu.org > Cc: qemu-s390x@nongnu.org > Cc: qemu-riscv@nongnu.org > > -- > 2.21.0 > From MAILER-DAEMON Fri Dec 20 08:44:56 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1iiIaO-00016J-Ao for mharc-qemu-arm@gnu.org; Fri, 20 Dec 2019 08:44:56 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:44326) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iiIaK-000159-VS for qemu-arm@nongnu.org; Fri, 20 Dec 2019 08:44:54 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1iiIaJ-00007u-AM for qemu-arm@nongnu.org; Fri, 20 Dec 2019 08:44:52 -0500 Received: from mail-ot1-x341.google.com ([2607:f8b0:4864:20::341]:37130) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1iiIaI-0008Vf-KZ for qemu-arm@nongnu.org; Fri, 20 Dec 2019 08:44:50 -0500 Received: by mail-ot1-x341.google.com with SMTP id k14so11940204otn.4 for ; Fri, 20 Dec 2019 05:44:50 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=VRcUdbDrthaJqJ9M/pTbzkrtzAV4OuFcKXWsaWcpvV0=; b=FMqwFIBqHUOoVfxBI1lFPwqfetK5uXzkNUimwNggnBjmix0mcKsswpCbKkOwAj26cL WBD/1cajMSgO+xQTJqqFyx9mqyXS4PJZqjLzY0YYWPNiHcsxUOkAN0un+RVT9mKzZ0py jG1H4kRtP5crTlVocfgUoXJYbRXJPpzWz/Hr1UmJSzLy4lhc+fQtfCru0/NgmSajKuud +C4Ra2gHtETI+pyIPBslGjKdJvC+C+AQlPVpE6DDEklGj+/Q9EVKGTCiJ5WnsFF1E6gp Q9/rk2PA4cIN0IgBvLUoh9trAsJFbImluXoeVg3LvPGk5u0jesq6OJTkte2/zwcCgyD2 NjdQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=VRcUdbDrthaJqJ9M/pTbzkrtzAV4OuFcKXWsaWcpvV0=; b=YLERErOz6+PLLLPSczGq5YMwpFPYTJRdKwgmbBUM0PvBcDRIphafijpRS8FPnLfp0T gLvNaMaFfr3vOwUoiL1/l9orlCIP8Pur2tI7Y41qm2zIoDKTLjNo8BzZpXVs7cvNXgxT 7P0uGerNja3RZZDy6cfUfDPolpLk9X5pyolLgczOTQb2Jht44rFiDz5uHI5mjYRHmIIt V8M5LHXqqec2zOqML13kty0R5W/3WQz56ZzvIgU+5JLvT3YS44BiDNRTa5tuC3sP8x3g 9Hj/R+brfWjn/slM4sS1JMLUx1ebmHh/IEDHF29HLcyeIuJTNgjBIvIsYW0yDbaytY3D 9y6g== X-Gm-Message-State: APjAAAWUnqgud0yFeiG8X0TTEe1h9GwF8myboFgKGQMhnae6dKCdwsYJ V7pgQAt38QVI1T1cHjXK5KyZYXB6/H/1aOrqCgiF4w== X-Google-Smtp-Source: APXvYqymzDItEWgVmv+DrsM2Q0919+2QU+g2Ojb5VTEGgHCQhW9fXonGfmyp8foWjy4rN1PKdP9xPhghQmfy0jOKxrU= X-Received: by 2002:a9d:3f21:: with SMTP id m30mr1208123otc.232.1576849489459; Fri, 20 Dec 2019 05:44:49 -0800 (PST) MIME-Version: 1.0 References: <20191105091056.9541-1-guoheyi@huawei.com> In-Reply-To: <20191105091056.9541-1-guoheyi@huawei.com> From: Peter Maydell Date: Fri, 20 Dec 2019 13:44:38 +0000 Message-ID: Subject: Re: [RFC v2 00/14] Add SDEI support for arm64 To: Heyi Guo Cc: qemu-arm , QEMU Developers , wanghaibin.wang@huawei.com, Dave Martin , Marc Zyngier , Mark Rutland , James Morse , "Michael S. Tsirkin" , Cornelia Huck , Paolo Bonzini , Shannon Zhao , Igor Mammedov Content-Type: text/plain; charset="UTF-8" X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::341 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 20 Dec 2019 13:44:54 -0000 On Tue, 5 Nov 2019 at 09:12, Heyi Guo wrote: > SDEI is for ARM "Software Delegated Exception Interface". AS ARM64 doesn't have > native non-maskable interrupt (NMI), we rely on higher privileged (larger > exception level) software to change the execution flow of lower privileged > (smaller exception level) software when certain events occur, to emulate NMI > mechanism, and SDEI is the standard interfaces between the two levels of > privileged software. It is based on SMC/HVC calls. > > The higher privileged software implements an SDEI dispatcher to handle SDEI > related SMC/HVC calls and trigger SDEI events; the lower privileged software > implements an SDEI client to request SDEI services and handle SDEI events. Hi; I read through these patches last week, but I didn't reply then because although there are some aspects to the design that I don't like, I don't have a clear idea of what a better approach to the problems it's trying to solve would be. However I didn't want to go home for the end of the year without providing at least some response. So I'm going to lay out the parts I have issues with and perhaps somebody else will have a good idea. The first part that I dislike here is that this is implementing an entire ABI which in real hardware is provided by firmware. I think that QEMU's design works best when QEMU provides emulation of hardware or hardware-like facilities, which guest code (either in the kernel, or firmware/bios running in the guest) can then make use of. Once we start getting into implementing firmware interfaces directly in QEMU this rapidly becomes a large amount of work and code, and it's unclear where it should stop. Should we implement also the equivalent of firmware for omap boards? For imx* boards? For the raspberry pi? For xilinx boards? Are we going to end up reimplementing more of ARM Trusted Firmware functionality inside QEMU? The code to implement firmware-equivalent ABIs in all these boards would I think quickly become a large part of the codebase. My second concern is that to do the things it wants to do, the implementation here does some pretty invasive things: * intercepting interrupt lines which ought to just be emulated hardware signals between devices and the GIC * capturing register values of other CPUs, and arbitrarily stopping those other CPUs and making them run other code at a later point in time I'm really uncomfortable with what's just an 'emulated firmware' interface for one specific board model doing this kind of thing. Finally, the stated rationale for the patchset ("we'd like an emulated NMI equivalent") doesn't really feel to me like it's strong enough to counterbalance the amount of code here and the degree to which it's moving us into a swamp I'd prefer it if we could stay out of. I'd be much happier with a design where QEMU provides simple facilities to the guest and the guest firmware and kernel deal with making use of them. I appreciate that it's not clear how that would work though, given that in real hardware this works by the firmware running at EL3 and KVM not providing a mechanism that allows guest code that runs at a higher (effective or emulated) privilege level than the guest kernel... thanks -- PMM From MAILER-DAEMON Fri Dec 20 08:53:50 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1iiIj0-0006BR-Bg for mharc-qemu-arm@gnu.org; Fri, 20 Dec 2019 08:53:50 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:60195) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iiIiw-00063R-Le for qemu-arm@nongnu.org; Fri, 20 Dec 2019 08:53:47 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1iiIiv-0004U2-65 for qemu-arm@nongnu.org; Fri, 20 Dec 2019 08:53:46 -0500 Received: from mail.dornerworks.com ([12.207.209.150]:48884 helo=webmail.dornerworks.com) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1iiIir-0004BF-9x; Fri, 20 Dec 2019 08:53:41 -0500 Subject: Re: [PATCH] target/arm: fix IL bit for data abort exceptions To: Peter Maydell , Richard Henderson CC: qemu-arm , QEMU Developers , Stewart Hildebrand , Jarvis Roach References: <20191217210230.99559-1-jeff.kubascik@dornerworks.com> <7a274247-e593-5828-73f8-2042971e8633@linaro.org> From: Jeff Kubascik Message-ID: Date: Fri, 20 Dec 2019 08:54:30 -0500 User-Agent: Mozilla/5.0 (Windows NT 10.0; WOW64; rv:68.0) Gecko/20100101 Thunderbird/68.3.1 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset="utf-8" Content-Language: en-US Content-Transfer-Encoding: 7bit X-Originating-IP: [99.18.96.11] X-ClientProxiedBy: Mcbain.dw.local (172.27.1.45) To Mcbain.dw.local (172.27.1.45) X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 12.207.209.150 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 20 Dec 2019 13:53:49 -0000 On 12/19/2019 7:43 AM, Peter Maydell wrote: > On Wed, 18 Dec 2019 at 01:03, Richard Henderson > wrote: >> >> On 12/17/19 11:02 AM, Jeff Kubascik wrote: >>> diff --git a/target/arm/tlb_helper.c b/target/arm/tlb_helper.c >>> index 5feb312941..e63f8bda29 100644 >>> --- a/target/arm/tlb_helper.c >>> +++ b/target/arm/tlb_helper.c >>> @@ -44,7 +44,7 @@ static inline uint32_t merge_syn_data_abort(uint32_t template_syn, >>> syn = syn_data_abort_with_iss(same_el, >>> 0, 0, 0, 0, 0, >>> ea, 0, s1ptw, is_write, fsc, >>> - false); >>> + true); >>> /* Merge the runtime syndrome with the template syndrome. */ >>> syn |= template_syn; >> >> This doesn't look correct. Surely the IL bit should come from template_syn? > > Yes. In translate.c we put it into the syndrome information by > passing true/false to syn_data_abort_with_iss() depending on > whether the issinfo passed in to disas_set_da_iss() has the > ISSIs16Bit flag set. > > I think this is a regression introduced in commit 46beb58efbb8a2a32 > when we converted the Thumb decoder over to decodetree. Before that > 16 bit Thumb insns were in a different place in the old decoder and > the 16-bit Thumb path passed ISSIs16Bit in with its issflags. > (We should cc: qemu-stable@nongnu.org on the fix for this.) The problem here was syn_data_abort_with_iss would return syn with the IL bit set, which carries through when it gets or'd with template_syn. I had to change the is_16bit argument to true so that it clear the IL bit. >>> diff --git a/target/arm/translate.c b/target/arm/translate.c >>> index 2b6c1f91bf..300480f1b7 100644 >>> --- a/target/arm/translate.c >>> +++ b/target/arm/translate.c >>> @@ -8555,7 +8555,7 @@ static ISSInfo make_issinfo(DisasContext *s, int rd, bool p, bool w) >>> >>> /* ISS not valid if writeback */ >>> if (p && !w) { >>> - ret = rd; >>> + ret = rd | (s->is_16bit ? ISSIs16Bit : 0); >>> } else { >>> ret = ISSInvalid; >>> } > > Rather than setting an is_16bit flag, we could just use > "dc->base.pc_next - dc->pc_curr == 2", couldn't we? > > thanks > -- PMM > Sincerely, Jeff Kubascik From MAILER-DAEMON Fri Dec 20 09:00:03 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1iiIp0-0007kk-RQ for mharc-qemu-arm@gnu.org; Fri, 20 Dec 2019 09:00:02 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:58752) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iiIow-0007fI-UA for qemu-arm@nongnu.org; Fri, 20 Dec 2019 09:00:00 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1iiIov-0001jh-BE for qemu-arm@nongnu.org; Fri, 20 Dec 2019 08:59:58 -0500 Received: from mail-ot1-x342.google.com ([2607:f8b0:4864:20::342]:41384) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1iiIou-0001fO-V8 for qemu-arm@nongnu.org; Fri, 20 Dec 2019 08:59:57 -0500 Received: by mail-ot1-x342.google.com with SMTP id r27so11970043otc.8 for ; Fri, 20 Dec 2019 05:59:56 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=ELpgbcB63eyC8D0t7Z4Fvx7gbMm7zBoq3zJjp0z7mJs=; b=C2WsHvtXy749gvkXphiJQTFHdm/9pOO9gjYmzXfaMLqdg68HFmS3occ6TK1MSzXdyb uUmtq1l2Po1yfQpIgwdvSzEpC1uFhJAh+kyjBMD+mNCVzYn6dXscMcqBrGEh3zzEnZsO 8JyRWZtXbDIB5QdXXP2eFjy4UT5TlMOPrJZUCExUXpdPXMejY+y9M+Xwr0Vvkd4AxszA z28XwAmP270e3O4nXANpuVyISK8HH/ZfARLCWsT8YvVejQkspcLyKx/t/uPMDb6bULvj P6l0OlDwUPI+f/VomsNt6imSbigMkNHTUseeuFb0hbKpa91s00rtXGiGZOTJcW9tAMTr jATw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=ELpgbcB63eyC8D0t7Z4Fvx7gbMm7zBoq3zJjp0z7mJs=; b=mN8EcwdniY8Gkv8osQBY5ehzItP+9a879mymkQbHOyEtsASU6nA5Ngla51rLYwtwY9 1FxBP0CeDOJx3CM5ojRTF+iBzqTOHezJsSg8I1SoazJvGJkMlPAKHoZSmIinyfzvc/NT DUO0YVYYw5ROTdN2HWUXX/VZtON6VhLDj+yRcX6i8ztjtBJG5JTxNjCkCv5HM4oZPnRG CECiI//VG1W5FOrS5Kjmwc1ytwYVIqcRu2B4ULv/dI906w+WRPkOgJxkGIAaUsPgMbX+ x1v1F27xmZAWEFa9pgXyEOG1DNL0tWqE9ZSYh75d+cTUmJ87U3KKFxstlXxKUK9f0Aqo LJ6w== X-Gm-Message-State: APjAAAV6Ouf632HlutshYkQ6IC3ErWF6aRRf7HEsaZUBwV8D09w0i7lr b8BsrcTxovnGtFqe3dq+FrX6Xqsl2oXkfhtr2CDmRQ== X-Google-Smtp-Source: APXvYqx7n0BA5B96/Ii01kjGjFm+xgRen7pmR5PfmX7v1txRP32lWTBvNQpd//WBSZzfX7adDf5Ee80hbYzlEgEMyeU= X-Received: by 2002:a9d:8cb:: with SMTP id 69mr1308538otf.221.1576850395953; Fri, 20 Dec 2019 05:59:55 -0800 (PST) MIME-Version: 1.0 References: <20191217210230.99559-1-jeff.kubascik@dornerworks.com> <7a274247-e593-5828-73f8-2042971e8633@linaro.org> In-Reply-To: From: Peter Maydell Date: Fri, 20 Dec 2019 13:59:45 +0000 Message-ID: Subject: Re: [PATCH] target/arm: fix IL bit for data abort exceptions To: Jeff Kubascik Cc: Richard Henderson , qemu-arm , QEMU Developers , Stewart Hildebrand , Jarvis Roach Content-Type: text/plain; charset="UTF-8" X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::342 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 20 Dec 2019 14:00:01 -0000 On Fri, 20 Dec 2019 at 13:53, Jeff Kubascik wrote: > > On 12/19/2019 7:43 AM, Peter Maydell wrote: > > On Wed, 18 Dec 2019 at 01:03, Richard Henderson > > wrote: > >> > >> On 12/17/19 11:02 AM, Jeff Kubascik wrote: > >>> diff --git a/target/arm/tlb_helper.c b/target/arm/tlb_helper.c > >>> index 5feb312941..e63f8bda29 100644 > >>> --- a/target/arm/tlb_helper.c > >>> +++ b/target/arm/tlb_helper.c > >>> @@ -44,7 +44,7 @@ static inline uint32_t merge_syn_data_abort(uint32_t template_syn, > >>> syn = syn_data_abort_with_iss(same_el, > >>> 0, 0, 0, 0, 0, > >>> ea, 0, s1ptw, is_write, fsc, > >>> - false); > >>> + true); > >>> /* Merge the runtime syndrome with the template syndrome. */ > >>> syn |= template_syn; > >> > >> This doesn't look correct. Surely the IL bit should come from template_syn? > > > > Yes. In translate.c we put it into the syndrome information by > > passing true/false to syn_data_abort_with_iss() depending on > > whether the issinfo passed in to disas_set_da_iss() has the > > ISSIs16Bit flag set. > > > > I think this is a regression introduced in commit 46beb58efbb8a2a32 > > when we converted the Thumb decoder over to decodetree. Before that > > 16 bit Thumb insns were in a different place in the old decoder and > > the 16-bit Thumb path passed ISSIs16Bit in with its issflags. > > (We should cc: qemu-stable@nongnu.org on the fix for this.) > > The problem here was syn_data_abort_with_iss would return syn with the IL bit > set, which carries through when it gets or'd with template_syn. I had to change > the is_16bit argument to true so that it clear the IL bit. Interesting. I think that's an entirely separate (and long standing) bug to the regression where we forgot to fill in ISSIs16Bit in the issinfo field, and it masks the other bug... thanks -- PMM From MAILER-DAEMON Fri Dec 20 09:00:47 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1iiIpi-0000Aq-VU for mharc-qemu-arm@gnu.org; Fri, 20 Dec 2019 09:00:46 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:48943) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iiGiq-0008Th-3e for qemu-arm@nongnu.org; Fri, 20 Dec 2019 06:45:33 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1iiGio-0002zl-O4 for qemu-arm@nongnu.org; Fri, 20 Dec 2019 06:45:31 -0500 Received: from mail-pl1-x643.google.com ([2607:f8b0:4864:20::643]:41048) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1iiGio-0002sl-7s for qemu-arm@nongnu.org; Fri, 20 Dec 2019 06:45:30 -0500 Received: by mail-pl1-x643.google.com with SMTP id bd4so3990836plb.8 for ; Fri, 20 Dec 2019 03:45:29 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=subject:to:cc:references:from:message-id:date:user-agent :mime-version:in-reply-to:content-language:content-transfer-encoding; bh=crfuNxBVCngqn0yvcbXKI5joADyERlYsV08zUGbPnBM=; b=mXwiQ1qUCvgaJHQLSrLD2pyQ+Or67gNf9z6ByTLgw5V7NT5OdsG7SqJWbAdDh4DHjy lgWGn6vrRy5AiocNZdYdwW1G3ftJ/bz9vKyeTJApnhMGB+MU6ahImZv6v9yxDxs2us6U ViOOkcbBd+KUSNpFuIjqMxcmBiZQEwFUJ0iK1EXKE/gXPjaSJE+eh9BOD6xbZ7sPaeUn 3e/tUTg1inb0qChDmsLvo6CvHUC6+XhE1pV4NkzJPGYIdslH30p/woiYJHJoL2IkVWkz 4+ZpOSqNLnXxC38q5PcfqaORoSkB5ZCccriOPnJ4btqXNA6aGnIeHgzdf6wA8KOi1Yoy IpFQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:subject:to:cc:references:from:message-id:date :user-agent:mime-version:in-reply-to:content-language :content-transfer-encoding; bh=crfuNxBVCngqn0yvcbXKI5joADyERlYsV08zUGbPnBM=; b=tkvv7V71zmgBORplxfiHWzj9MD4mcM9VmdMt+50Q2SKJkjCamLnZF4a1Bc2EaFh2Et ncPDy3qmEibtYXuhutEXuKDvntp8ssHfXOIKF2dUZ2wYECcLa6EpEHOR0oz+0JnA/26F 8/3lxjGL8V4OuSgLlf091Sm/6hTfyX/+AGN7jLkmOrt1L0a5E4GRwNuAiVQby6mj1je4 D+eejNZzVekmSr1ONj1i6anDMvEPv4koa08c9TOluaLKO/bTS3j9oxi7G0A8F34O9mMR Yp3fbfqYjtoGCVcKcvuVZPNZBxoBsKIDQOj9pPwkNNfWaC9law7HUHkgKCEo/JbK9xf1 rk8Q== X-Gm-Message-State: APjAAAWFDo1UGblVXvpQ/Uhhcq5cEdj0nO8PEuMee5RQwzAgvHdl8zzd EzK+Y4enlzfcqhSc38Ae6xaqts40ZnI= X-Google-Smtp-Source: APXvYqy2A+HB4lsHrr0ctuBOSy+8/zDyRdZHtoUdoS1b73lFX1aPoTFty7SFmks11dVvkQCssWYh9g== X-Received: by 2002:a17:90a:26ab:: with SMTP id m40mr15812980pje.42.1576842328163; Fri, 20 Dec 2019 03:45:28 -0800 (PST) Received: from ?IPv6:2804:7f0:8282:d06:e0aa:310d:b742:862f? ([2804:7f0:8282:d06:e0aa:310d:b742:862f]) by smtp.gmail.com with ESMTPSA id h6sm10822686pgq.61.2019.12.20.03.45.24 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 20 Dec 2019 03:45:27 -0800 (PST) Subject: Re: [PATCH v3 12/20] target/arm: generate xml description of our SVE registers To: =?UTF-8?Q?Alex_Benn=c3=a9e?= , Richard Henderson Cc: qemu-devel@nongnu.org, alan.hayward@arm.com, damien.hedde@greensocs.com, Peter Maydell , "open list:ARM TCG CPUs" References: <20191211170520.7747-1-alex.bennee@linaro.org> <20191211170520.7747-13-alex.bennee@linaro.org> <69e10c48-8bdf-cbe0-3372-815b647f8312@linaro.org> <87k16sdt4d.fsf@linaro.org> From: Luis Machado Message-ID: <5c6dd0a9-23ba-63ff-5738-8bac11aad810@linaro.org> Date: Fri, 20 Dec 2019 08:45:22 -0300 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.2.2 MIME-Version: 1.0 In-Reply-To: <87k16sdt4d.fsf@linaro.org> Content-Type: text/plain; charset=utf-8; format=flowed Content-Language: en-US Content-Transfer-Encoding: 8bit X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::643 X-Mailman-Approved-At: Fri, 20 Dec 2019 09:00:41 -0500 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 20 Dec 2019 11:45:33 -0000 On 12/19/19 4:15 PM, Alex Bennée wrote: > > Richard Henderson writes: > >> On 12/11/19 9:05 AM, Alex Bennée wrote: >>> +static struct TypeSize vec_lanes[] = { >> >> const. >> >>> + case 51: >>> + return gdb_get_reg64(buf, (cpu->env.vfp.zcr_el[1] & 0xf) + 1); >> >> You need to use sve_zcr_len_for_el to get the effective vq. >> Also, I thought vg == 2 * vq. >> > + case 51: >>> + { >>> + uint64_t val = *(uint64_t *) buf; >>> + cpu->env.vfp.zcr_el[1] = (val - 1) & 0xf; >> >> You cannot hard-code EL1 without ifdef CONFIG_USER_ONLY. If the effective vq >> decreases, you must call aarch64_sve_narrow_vq. You must call arm_rebuild_hflags. > > I'm just going to drop vg (and therefor the ability to set it) from the > regset. It was only meant to be an indicator and gdb doesn't actually > look to it to size it's output. The likely dynamic extension will just > re-transmit the whole XML when a change occurs. > I'd verify with GDB first if vg isn't actually required. From looking at GDB's code, it does set vg as one of the register names, and this is regardless of any XML input. It does reference VG here and there in the code, even though it may not use it to size its output. From MAILER-DAEMON Fri Dec 20 09:00:47 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1iiIpj-0000BI-6H for mharc-qemu-arm@gnu.org; Fri, 20 Dec 2019 09:00:47 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:37082) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iiIBL-00062H-Ob for qemu-arm@nongnu.org; Fri, 20 Dec 2019 08:19:04 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1iiIBK-0000N9-A1 for qemu-arm@nongnu.org; Fri, 20 Dec 2019 08:19:03 -0500 Received: from mail-pj1-x1041.google.com ([2607:f8b0:4864:20::1041]:36002) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1iiIBJ-0000Hc-QZ for qemu-arm@nongnu.org; Fri, 20 Dec 2019 08:19:02 -0500 Received: by mail-pj1-x1041.google.com with SMTP id n59so4130578pjb.1 for ; Fri, 20 Dec 2019 05:19:01 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=subject:to:cc:references:from:message-id:date:user-agent :mime-version:in-reply-to:content-language:content-transfer-encoding; bh=4aK/ve40XlXyED/AEPJ4m4wmtwjR1LdUmhAHwiSmLJo=; b=l6IlTDNsvGyoB0tXXWQHti/s95zZOjKD7QSM/iiqgWQHlu/BNJKjy77573eoZHiRi1 UyU2sc9LkhbSxqBYipLylqXs1qrcfzErjz/wKniNoOZl8UgQKTd6A/VomCu5IOBsM3df lR8pGwT0Np5uEp4ZIwaractOxLEN5EMloX02ENBokjLaT4dN9CpRYcRiMWvyo444hcAA 7PjuDbvkMtY5RhbpJGeZMrMROIS10rmFSKNjldTmt608Q6wOTYS8mbFaAhZFGL8f3mW+ NqXtJ7M5S7ld3WmWIOlJYMuYNuyx15LsUqWJei9hloiV5lW+9965EcoOCmzmTDuRkqt+ tYVQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:subject:to:cc:references:from:message-id:date :user-agent:mime-version:in-reply-to:content-language :content-transfer-encoding; bh=4aK/ve40XlXyED/AEPJ4m4wmtwjR1LdUmhAHwiSmLJo=; b=B000tD3RmGkxCNC9TCchAiIC+NhQlthK9irVPTjoWacgV1mzP26YCaj+DxHkNSMYug tat8QexBNW82PoOceIOX0XTeSP6L6a4vBJo8bgV/ekVO/tD088xaDPjKVAINIZH+1379 7kFYRwQ/ZCkip0HgZ7w4sI+oEYT7nyKoxq8QHp5aTZ7ih0sMfoCU0Oi+q6JAVoB8N6o4 n05Q0DLM5p295g7BsvHiNIAsT92NcXJWP+LjRBKFs0dl8jJjsZexDSLrVk5tMt1l0w8V fd8CO+k2aG6XO81TKucWRf+ubkRT2fDv1voRImioz2lioAzCb6NsTdJJjvGM9Gw+ju57 W3wA== X-Gm-Message-State: APjAAAVzhV0vAV313lxRXoADswEpPC9jxo3hbRMgFFX9LgNWl1dXMmxe 5Faie4ahc8dwmP2inzy5aUUtEVhaxNE= X-Google-Smtp-Source: APXvYqyWN9m1C/V/VpQl/BKNVN/sNfLzvNeD66xVzRfevTHKsRReemtDQ6psnbh0PHz+NZi9wIDdyg== X-Received: by 2002:a17:90a:8a0e:: with SMTP id w14mr16312526pjn.51.1576847940320; Fri, 20 Dec 2019 05:19:00 -0800 (PST) Received: from ?IPv6:2804:7f0:8282:d06:e0aa:310d:b742:862f? ([2804:7f0:8282:d06:e0aa:310d:b742:862f]) by smtp.gmail.com with ESMTPSA id 199sm13643132pfv.81.2019.12.20.05.18.56 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 20 Dec 2019 05:18:59 -0800 (PST) Subject: Re: [PATCH v3 12/20] target/arm: generate xml description of our SVE registers To: =?UTF-8?Q?Alex_Benn=c3=a9e?= Cc: Richard Henderson , qemu-devel@nongnu.org, alan.hayward@arm.com, damien.hedde@greensocs.com, Peter Maydell , "open list:ARM TCG CPUs" References: <20191211170520.7747-1-alex.bennee@linaro.org> <20191211170520.7747-13-alex.bennee@linaro.org> <69e10c48-8bdf-cbe0-3372-815b647f8312@linaro.org> <87k16sdt4d.fsf@linaro.org> <5c6dd0a9-23ba-63ff-5738-8bac11aad810@linaro.org> <87eewzdtqg.fsf@linaro.org> From: Luis Machado Message-ID: <81e43d43-29f8-ec56-5270-bb90dd1bc077@linaro.org> Date: Fri, 20 Dec 2019 10:18:54 -0300 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.2.2 MIME-Version: 1.0 In-Reply-To: <87eewzdtqg.fsf@linaro.org> Content-Type: text/plain; charset=utf-8; format=flowed Content-Language: en-US Content-Transfer-Encoding: 8bit X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::1041 X-Mailman-Approved-At: Fri, 20 Dec 2019 09:00:41 -0500 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 20 Dec 2019 13:19:05 -0000 On 12/20/19 10:14 AM, Alex Bennée wrote: > > Luis Machado writes: > >> On 12/19/19 4:15 PM, Alex Bennée wrote: >>> Richard Henderson writes: >>> >>>> On 12/11/19 9:05 AM, Alex Bennée wrote: >>>>> +static struct TypeSize vec_lanes[] = { >>>> >>>> const. >>>> >>>>> + case 51: >>>>> + return gdb_get_reg64(buf, (cpu->env.vfp.zcr_el[1] & 0xf) + 1); >>>> >>>> You need to use sve_zcr_len_for_el to get the effective vq. >>>> Also, I thought vg == 2 * vq. >>>> > + case 51: >>>>> + { >>>>> + uint64_t val = *(uint64_t *) buf; >>>>> + cpu->env.vfp.zcr_el[1] = (val - 1) & 0xf; >>>> >>>> You cannot hard-code EL1 without ifdef CONFIG_USER_ONLY. If the effective vq >>>> decreases, you must call aarch64_sve_narrow_vq. You must call arm_rebuild_hflags. >>> I'm just going to drop vg (and therefor the ability to set it) from >>> the >>> regset. It was only meant to be an indicator and gdb doesn't actually >>> look to it to size it's output. The likely dynamic extension will just >>> re-transmit the whole XML when a change occurs. >>> >> >> I'd verify with GDB first if vg isn't actually required. > > It works with my tests but perhaps we use our own namespaced XML rather > than the gdbstub XML. > >> From looking at GDB's code, it does set vg as one of the register >> names, and this is regardless of any XML input. It does reference VG >> here and there in the code, even though it may not use it to size its >> output. > > But this is all special casing for feature > name="org.gnu.gdb.aarch64.sve" right? > Yes, vg is only available if feature org.gnu.gdb.aarch64.sve is available. From MAILER-DAEMON Fri Dec 20 09:46:32 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1iiJY0-0006ki-D2 for mharc-qemu-arm@gnu.org; Fri, 20 Dec 2019 09:46:32 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:50050) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iiJXx-0006cm-DR for qemu-arm@nongnu.org; Fri, 20 Dec 2019 09:46:31 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1iiJXv-0007xi-Un for qemu-arm@nongnu.org; Fri, 20 Dec 2019 09:46:29 -0500 Received: from beetle.greensocs.com ([5.135.226.135]:52538) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1iiJXv-0007wL-18; Fri, 20 Dec 2019 09:46:27 -0500 Received: from crumble.bar.greensocs.com (crumble.bar.greensocs.com [172.16.11.102]) by beetle.greensocs.com (Postfix) with ESMTPS id D0BA996EF0; Fri, 20 Dec 2019 14:46:24 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=greensocs.com; s=mail; t=1576853185; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding; bh=UeyalBXBvVZ3C0vBcE1FLzrTdcmMSL8XKpGFDkbsK7s=; b=Mz9ExDYFMGYz+PeNHRzPLCYksUn7MOsvWoJtyiZjAqVgo+C3Sa1PpJSqLceW1fEI+xQJCi qFmaMTII1wdzynDzBE6ATJrVfzKQndTOcrD4qsEw8pcLTwG5x4MWm2Cdcr8imcmGGxF/iF wd/4Yb58z0a03zeXY1fd+KePhhgR4QQ= From: Damien Hedde To: qemu-devel@nongnu.org Cc: Damien Hedde , qemu-arm@nongnu.org, philmd@redhat.com, Andrew.Baumann@microsoft.com, peter.maydell@linaro.org Subject: [PATCH 0/3] Raspi sd-bus cleanup and multiphase reset Date: Fri, 20 Dec 2019 15:46:13 +0100 Message-Id: <20191220144616.911466-1-damien.hedde@greensocs.com> X-Mailer: git-send-email 2.24.0 MIME-Version: 1.0 ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=greensocs.com; s=mail; t=1576853185; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding; bh=UeyalBXBvVZ3C0vBcE1FLzrTdcmMSL8XKpGFDkbsK7s=; b=5a2nOH7WTm9TEMUOH3NWeCEAUJaaEmRMS0hO4H1ulFUsMJ/E1Wwi63QhH9Z00QJNXSi40Z R8SJ44oMFUg1DQnH1MMu12TDwQd+MfOBsYtD95h3vCEBUJRsM5pR7B0bVlYRRAKQzHpy4N ruenPZtLD2dNggqk3KrANOma1I2S/ss= ARC-Seal: i=1; s=mail; d=greensocs.com; t=1576853185; a=rsa-sha256; cv=none; b=sYUV/YeUGgYWhFcvqWKWCvOkFbgaJ77/29kbXOMLsUZkC1yGO7q337fBDA9kViR+O8RB/l mFNLEcBvURob2x0DIeE1mysXu5ybLXiRaM9lT1WHiC1FdFXDfA6vdSvrmDbc2NIxEq8bEs t3IdI59a4tu48btmtAncpOLnrI9NimI= ARC-Authentication-Results: i=1; beetle.greensocs.com; none Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 5.135.226.135 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 20 Dec 2019 14:46:31 -0000 Hi All, This series is a follow-up of my reset series, https://lists.gnu.org/archive/html/qemu-devel/2019-12/msg04664.html I've extracted the raspberry-pi related patches. As suggested by Peter in the previous version of the reset serie, these patches do a cleanup of the raspberry-pi sd-bus then does the multiphase reset switch of the gpio soc part. Patch 1 remove the bcm2835_gpio sd-bus which is only used to host the sd-card before the machine initial reset. As the soc exhibits the "defaul= t" sd-bus to the machine using an alias, we can simply exhibit the sdhci ins= tead. Patch 2 prepare the multiphase reset switch by isolating the sd-card pare= nt change. Patch 3 finally does the multiphase transition of the bcm2835_gpi= o. Thanks for your feedback, Damien Based-on: <20191220115035.709876-1-damien.hedde@greensocs.com> Damien Hedde (3): hw/arm/bcm2835: remove gpio/sd-bus hw/gpio/bcm2835_gpio: Isolate sdbus reparenting hw/gpio/bcm2835_gpio: Update to resettable include/hw/gpio/bcm2835_gpio.h | 1 - hw/arm/bcm2835_peripherals.c | 2 +- hw/gpio/bcm2835_gpio.c | 35 +++++++++++++++++++++++----------- 3 files changed, 25 insertions(+), 13 deletions(-) --=20 2.24.0 From MAILER-DAEMON Fri Dec 20 09:46:33 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1iiJY1-0006n4-J8 for mharc-qemu-arm@gnu.org; Fri, 20 Dec 2019 09:46:33 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:50225) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iiJXy-0006fx-EN for qemu-arm@nongnu.org; Fri, 20 Dec 2019 09:46:31 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1iiJXx-00080T-6t for qemu-arm@nongnu.org; Fri, 20 Dec 2019 09:46:30 -0500 Received: from beetle.greensocs.com ([5.135.226.135]:52552) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1iiJXw-0007yN-Qr; Fri, 20 Dec 2019 09:46:29 -0500 Received: from crumble.bar.greensocs.com (crumble.bar.greensocs.com [172.16.11.102]) by beetle.greensocs.com (Postfix) with ESMTPS id 94A7396EF2; Fri, 20 Dec 2019 14:46:27 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=greensocs.com; s=mail; t=1576853187; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=SbgvYJhx6Lit3rs3j+nNkUTo6mP2ku7nAV624s9t11k=; b=pLxt1y8YeyRjjFOiEwU4gagAknZGqxqWTGjKTT9U+mWGN0sXPLzYwIHeDIGucqkrUrT+qd tATMQgU+kdBTh8aOnIKeASvvTlqhte4XIqfNk4lO3BiH1Ch49ugeQNZqg/z3TFYrq2yc4l TpEfot6HSwDHUQj0hnm8vP2R/m5QIJ0= From: Damien Hedde To: qemu-devel@nongnu.org Cc: Damien Hedde , qemu-arm@nongnu.org, philmd@redhat.com, Andrew.Baumann@microsoft.com, peter.maydell@linaro.org Subject: [PATCH 1/3] hw/arm/bcm2835: remove gpio/sd-bus Date: Fri, 20 Dec 2019 15:46:14 +0100 Message-Id: <20191220144616.911466-2-damien.hedde@greensocs.com> X-Mailer: git-send-email 2.24.0 In-Reply-To: <20191220144616.911466-1-damien.hedde@greensocs.com> References: <20191220144616.911466-1-damien.hedde@greensocs.com> MIME-Version: 1.0 ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=greensocs.com; s=mail; t=1576853187; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=SbgvYJhx6Lit3rs3j+nNkUTo6mP2ku7nAV624s9t11k=; b=MI6qLUDmaWiMtZ3wTmX4U+UnYBrHtvhcLZ+Zh6LmHC+M4LB6m2UPZwYqRBXRv0lnrVWsqk nHhdJIQc3cHFoA4M4H/cKVszyxb2K6mC9EWgDlFbJMuMyelG80EtIcDI76nG1BfmPsYla2 ElP6436uEPVv9LCeG9VwkdH7Ahc7Slc= ARC-Seal: i=1; s=mail; d=greensocs.com; t=1576853187; a=rsa-sha256; cv=none; b=MxI/C14GDculPwqELFq5jEitYIDfAKg3A5TE7rxod3NVWQ2WuOakifmty2f/MXV+a29S3B P7fm0WjKiybmRabInhNXuzBYXpdxZBuB34q5Ld8nzw7mtJawAdWUxEcEPHVIWcWbYUlfOl 4A7kNuLl3YtmwU9y/cVKiC09jR+2KcQ= ARC-Authentication-Results: i=1; beetle.greensocs.com; none Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 5.135.226.135 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 20 Dec 2019 14:46:31 -0000 Remove gpio/sdbus which is only used to host the sd card before reset. Instead directly we exhibit the sdhci bus to the soc and machine. Thus the sd card is created on the sdhci bus and do not need to be moved during first reset. Signed-off-by: Damien Hedde --- include/hw/gpio/bcm2835_gpio.h | 1 - hw/arm/bcm2835_peripherals.c | 2 +- hw/gpio/bcm2835_gpio.c | 6 ------ 3 files changed, 1 insertion(+), 8 deletions(-) diff --git a/include/hw/gpio/bcm2835_gpio.h b/include/hw/gpio/bcm2835_gpi= o.h index b0de0a3c74..f8416d43d3 100644 --- a/include/hw/gpio/bcm2835_gpio.h +++ b/include/hw/gpio/bcm2835_gpio.h @@ -23,7 +23,6 @@ typedef struct BCM2835GpioState { MemoryRegion iomem; =20 /* SDBus selector */ - SDBus sdbus; SDBus *sdbus_sdhci; SDBus *sdbus_sdhost; =20 diff --git a/hw/arm/bcm2835_peripherals.c b/hw/arm/bcm2835_peripherals.c index 17207ae07e..93477c5b2f 100644 --- a/hw/arm/bcm2835_peripherals.c +++ b/hw/arm/bcm2835_peripherals.c @@ -360,7 +360,7 @@ static void bcm2835_peripherals_realize(DeviceState *= dev, Error **errp) memory_region_add_subregion(&s->peri_mr, GPIO_OFFSET, sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->gpio), 0)); =20 - object_property_add_alias(OBJECT(s), "sd-bus", OBJECT(&s->gpio), "sd= -bus", + object_property_add_alias(OBJECT(s), "sd-bus", OBJECT(&s->sdhci), "s= d-bus", &err); if (err) { error_propagate(errp, err); diff --git a/hw/gpio/bcm2835_gpio.c b/hw/gpio/bcm2835_gpio.c index 91ce3d10cc..25c180423f 100644 --- a/hw/gpio/bcm2835_gpio.c +++ b/hw/gpio/bcm2835_gpio.c @@ -267,9 +267,6 @@ static void bcm2835_gpio_reset(DeviceState *dev) =20 s->sd_fsel =3D 0; =20 - /* SDHCI is selected by default */ - sdbus_reparent_card(&s->sdbus, s->sdbus_sdhci); - s->lev0 =3D 0; s->lev1 =3D 0; } @@ -299,9 +296,6 @@ static void bcm2835_gpio_init(Object *obj) DeviceState *dev =3D DEVICE(obj); SysBusDevice *sbd =3D SYS_BUS_DEVICE(obj); =20 - qbus_create_inplace(&s->sdbus, sizeof(s->sdbus), - TYPE_SD_BUS, DEVICE(s), "sd-bus"); - memory_region_init_io(&s->iomem, obj, &bcm2835_gpio_ops, s, "bcm2835_gpio", 0x1000); sysbus_init_mmio(sbd, &s->iomem); --=20 2.24.0 From MAILER-DAEMON Fri Dec 20 09:46:38 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1iiJY6-0006xN-L4 for mharc-qemu-arm@gnu.org; Fri, 20 Dec 2019 09:46:38 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:50896) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iiJY2-0006ou-DJ for qemu-arm@nongnu.org; Fri, 20 Dec 2019 09:46:35 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1iiJY0-0008GL-V3 for qemu-arm@nongnu.org; Fri, 20 Dec 2019 09:46:34 -0500 Received: from beetle.greensocs.com ([5.135.226.135]:52582) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1iiJY0-0008BK-Je; Fri, 20 Dec 2019 09:46:32 -0500 Received: from crumble.bar.greensocs.com (crumble.bar.greensocs.com [172.16.11.102]) by beetle.greensocs.com (Postfix) with ESMTPS id 4A98296EF0; Fri, 20 Dec 2019 14:46:31 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=greensocs.com; s=mail; t=1576853191; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=bUI425C+0o7N1J/sQKvdILj2VDsYvQDc77nK8FmyVMw=; b=mnFhCOtLHBzDl4db+ogmJ95bJMXPzMHAs/c9TT/mkczrEsfTaVOlyFXVdCh7eiP1NrygN+ ZFNqobWMXhS7IiLlCt6tqHhF02A5TOQkMoFY+1JaZoxCevzAoah4nu921X0GqZ+JU9K7B7 axqL7fuKqlDCO7lzq1GAB0XhgFyy62g= From: Damien Hedde To: qemu-devel@nongnu.org Cc: Damien Hedde , qemu-arm@nongnu.org, philmd@redhat.com, Andrew.Baumann@microsoft.com, peter.maydell@linaro.org Subject: [PATCH 3/3] hw/gpio/bcm2835_gpio: Update to resettable Date: Fri, 20 Dec 2019 15:46:16 +0100 Message-Id: <20191220144616.911466-4-damien.hedde@greensocs.com> X-Mailer: git-send-email 2.24.0 In-Reply-To: <20191220144616.911466-1-damien.hedde@greensocs.com> References: <20191220144616.911466-1-damien.hedde@greensocs.com> MIME-Version: 1.0 ARC-Message-Signature: i=1; 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The sdbus reparenting is delayed in hold phase to respect resettable side-effect rules. Signed-off-by: Damien Hedde Reviewed-by: Peter Maydell --- hw/gpio/bcm2835_gpio.c | 21 ++++++++++++++++----- 1 file changed, 16 insertions(+), 5 deletions(-) diff --git a/hw/gpio/bcm2835_gpio.c b/hw/gpio/bcm2835_gpio.c index 88dc652018..4d393c6a47 100644 --- a/hw/gpio/bcm2835_gpio.c +++ b/hw/gpio/bcm2835_gpio.c @@ -260,9 +260,9 @@ err_out: __func__, offset); } =20 -static void bcm2835_gpio_reset(DeviceState *dev) +static void bcm2835_gpio_reset_enter(Object *obj, ResetType type) { - BCM2835GpioState *s =3D BCM2835_GPIO(dev); + BCM2835GpioState *s =3D BCM2835_GPIO(obj); =20 int i; /* @@ -272,13 +272,22 @@ static void bcm2835_gpio_reset(DeviceState *dev) for (i =3D 0; i < 6; i++) { gpfsel_set(s, i, 0); } - /* Update s->sd_fsel and move the sd card */ - gpfsel_update_sdbus(s); =20 s->lev0 =3D 0; s->lev1 =3D 0; } =20 +static void bcm2835_gpio_reset_hold(Object *obj) +{ + BCM2835GpioState *s =3D BCM2835_GPIO(obj); + + /* + * Update s->sd_fsel and move the sd card according to the config se= t in + * bcm2835_gpio_reset_enter(). + */ + gpfsel_update_sdbus(s); +} + static const MemoryRegionOps bcm2835_gpio_ops =3D { .read =3D bcm2835_gpio_read, .write =3D bcm2835_gpio_write, @@ -336,10 +345,12 @@ static void bcm2835_gpio_realize(DeviceState *dev, = Error **errp) static void bcm2835_gpio_class_init(ObjectClass *klass, void *data) { DeviceClass *dc =3D DEVICE_CLASS(klass); + ResettableClass *rc =3D RESETTABLE_CLASS(klass); =20 dc->vmsd =3D &vmstate_bcm2835_gpio; dc->realize =3D &bcm2835_gpio_realize; - dc->reset =3D &bcm2835_gpio_reset; + rc->phases.enter =3D &bcm2835_gpio_reset_enter; + rc->phases.hold =3D &bcm2835_gpio_reset_hold; } =20 static const TypeInfo bcm2835_gpio_info =3D { --=20 2.24.0 From MAILER-DAEMON Fri Dec 20 09:46:34 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1iiJY1-0006np-VC for mharc-qemu-arm@gnu.org; Fri, 20 Dec 2019 09:46:33 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:50434) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iiJXz-0006j1-J3 for qemu-arm@nongnu.org; Fri, 20 Dec 2019 09:46:32 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1iiJXy-00085f-FW for qemu-arm@nongnu.org; Fri, 20 Dec 2019 09:46:31 -0500 Received: from beetle.greensocs.com ([5.135.226.135]:52566) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1iiJXy-00081w-7P; Fri, 20 Dec 2019 09:46:30 -0500 Received: from crumble.bar.greensocs.com (crumble.bar.greensocs.com [172.16.11.102]) by beetle.greensocs.com (Postfix) with ESMTPS id F2B3796F50; Fri, 20 Dec 2019 14:46:28 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=greensocs.com; s=mail; t=1576853189; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=lM12RI0EHDUNjslinRXmoW1BfejdQGdartCVRRzWAmE=; b=Vvt1dya3SavXYQzVTEWVATCFU2MszH4rUbjkT4YbxDGgkf40K/XO1F7h5sImmdoN2GO9Hl LrW5VV8RMsWTRaigIu6Y3ez9+fh5i8aqTvzv0itAzmbBbpI77Glhwgachzbdxma3lfeFvS kAmKnZWC/V0e1HLdtQIBYJ+rXlvMD9k= From: Damien Hedde To: qemu-devel@nongnu.org Cc: Damien Hedde , qemu-arm@nongnu.org, philmd@redhat.com, Andrew.Baumann@microsoft.com, peter.maydell@linaro.org Subject: [PATCH 2/3] hw/gpio/bcm2835_gpio: Isolate sdbus reparenting Date: Fri, 20 Dec 2019 15:46:15 +0100 Message-Id: <20191220144616.911466-3-damien.hedde@greensocs.com> X-Mailer: git-send-email 2.24.0 In-Reply-To: <20191220144616.911466-1-damien.hedde@greensocs.com> References: <20191220144616.911466-1-damien.hedde@greensocs.com> MIME-Version: 1.0 ARC-Message-Signature: i=1; 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Update call sites of gpfsel_set() to also call gpfsel_update_sdbus(). This commit is a preparation to switch to multiphase reset. Signed-off-by: Damien Hedde --- hw/gpio/bcm2835_gpio.c | 12 ++++++++++-- 1 file changed, 10 insertions(+), 2 deletions(-) diff --git a/hw/gpio/bcm2835_gpio.c b/hw/gpio/bcm2835_gpio.c index 25c180423f..88dc652018 100644 --- a/hw/gpio/bcm2835_gpio.c +++ b/hw/gpio/bcm2835_gpio.c @@ -75,7 +75,10 @@ static void gpfsel_set(BCM2835GpioState *s, uint8_t re= g, uint32_t value) s->fsel[index] =3D fsel; } } +} =20 +static void gpfsel_update_sdbus(BCM2835GpioState *s) +{ /* SD controller selection (48-53) */ if (s->sd_fsel !=3D 0 && (s->fsel[48] =3D=3D 0) /* SD_CLK_R */ @@ -210,6 +213,7 @@ static void bcm2835_gpio_write(void *opaque, hwaddr o= ffset, case GPFSEL4: case GPFSEL5: gpfsel_set(s, offset / 4, value); + gpfsel_update_sdbus(s); break; case GPSET0: gpset(s, value, 0, 32, &s->lev0); @@ -261,11 +265,15 @@ static void bcm2835_gpio_reset(DeviceState *dev) BCM2835GpioState *s =3D BCM2835_GPIO(dev); =20 int i; + /* + * Initialize the gpfsel registers. In particular, it selects the SD= HCI bus + * for the sd card. + */ for (i =3D 0; i < 6; i++) { gpfsel_set(s, i, 0); } - - s->sd_fsel =3D 0; + /* Update s->sd_fsel and move the sd card */ + gpfsel_update_sdbus(s); =20 s->lev0 =3D 0; s->lev1 =3D 0; --=20 2.24.0 From MAILER-DAEMON Fri Dec 20 10:23:50 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1iiK86-0001g4-EV for mharc-qemu-arm@gnu.org; Fri, 20 Dec 2019 10:23:50 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:34604) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iiK82-0001dR-Jh for qemu-arm@nongnu.org; Fri, 20 Dec 2019 10:23:48 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1iiK80-0003KL-TL for qemu-arm@nongnu.org; Fri, 20 Dec 2019 10:23:46 -0500 Received: from beetle.greensocs.com ([5.135.226.135]:53978) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1iiK80-0003IO-BI; Fri, 20 Dec 2019 10:23:44 -0500 Received: from [172.16.11.102] (crumble.bar.greensocs.com [172.16.11.102]) by beetle.greensocs.com (Postfix) with ESMTPSA id CC19996EF0; Fri, 20 Dec 2019 15:23:40 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=greensocs.com; s=mail; t=1576855422; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=v4F/97wPp1VqI7JzGMEVYBc5gcEooO+7EhMvJDjBxpY=; b=tp4vK3hTSz0UOzuyT7+m4m82B2dOFRNTKMGgkeYXk09X/ya9S05UxUgK3IqNR2oQLoiMzV vHSHs8FLjNzBS1uWOiRfjkh/0hA1aeThIfNcyeYHsPn86CPf6Xj4GekkxR7rDzKLARB59K 8teXt1e3ohoha2EFqHmCqT2uqym05do= Subject: Re: [PATCH v4 08/21] gdbstub: extend GByteArray to read register helpers To: =?UTF-8?Q?Alex_Benn=c3=a9e?= , qemu-devel@nongnu.org Cc: alan.hayward@arm.com, luis.machado@linaro.org, =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= , Eduardo Habkost , Marcel Apfelbaum , Richard Henderson , Peter Maydell , "Edgar E. Iglesias" , Paolo Bonzini , Michael Walle , Laurent Vivier , Aurelien Jarno , Aleksandar Markovic , Aleksandar Rikalo , Chris Wulff , Marek Vasut , Stafford Horne , David Gibson , Palmer Dabbelt , Alistair Francis , Sagar Karandikar , Bastian Koppelmann , Cornelia Huck , David Hildenbrand , Mark Cave-Ayland , Artyom Tarasenko , Max Filippov , "open list:ARM TCG CPUs" , "open list:PowerPC TCG CPUs" , "open list:RISC-V TCG CPUs" , "open list:S390 general arch..." References: <20191220120438.16114-1-alex.bennee@linaro.org> <20191220120438.16114-9-alex.bennee@linaro.org> From: Damien Hedde Message-ID: <2ea7692c-02a8-8267-de6d-529731958a8f@greensocs.com> Date: Fri, 20 Dec 2019 16:23:40 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.2.0 MIME-Version: 1.0 In-Reply-To: <20191220120438.16114-9-alex.bennee@linaro.org> Content-Type: text/plain; charset=utf-8 Content-Language: en-US-large ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=greensocs.com; s=mail; t=1576855422; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=v4F/97wPp1VqI7JzGMEVYBc5gcEooO+7EhMvJDjBxpY=; b=LQ37Df4kzJ1p6Aek/NpUqOfH2I0cAHJblZ9fj1U7jfagEBqACto/8A6jALVy4cJCtW+xAA nFoR4IatTn6hP+LYwj7dV/tlRqh6GQq46oKRs48maP5+NBDNhu/POs//n0l1QLw0c/L7VQ VtmNckOBac9HoGXiS7gNGSrS4DFU9Q0= ARC-Seal: i=1; s=mail; d=greensocs.com; t=1576855422; a=rsa-sha256; cv=none; b=aBgcSmy4GQ7c0C6bwBXvdFx9JiRCTgJCYKDOm2HnQ29tjrMWKVsxrs1i0ytlkiIz1nZ7iL 2vu2VDds16sh+0fbNVbh17laRC4XLQoBuzVMcrF292WDpHa+PrM/28pQkAUQOpQxhnOAub eDRu/NcCJFkOaE0YfZ2K02nMuweXO0g= ARC-Authentication-Results: i=1; ORIGINATING; auth=pass smtp.auth=damien smtp.mailfrom=damien.hedde@greensocs.com Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 5.135.226.135 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 20 Dec 2019 15:23:48 -0000 On 12/20/19 1:04 PM, Alex Benn=C3=A9e wrote: > Instead of passing a pointer to memory now just extend the GByteArray > to all the read register helpers. They can then safely append their > data through the normal way. We don't bother with this abstraction for > write registers as we have already ensured the buffer being copied > from is the correct size. >=20 > Signed-off-by: Alex Benn=C3=A9e >=20 > --- > v4 > - fix mem_buf calculation for ppc_maybe_bswap_register > --- Hi Alex, You missed the ppc_maybe_bswap_register() calls in ppc/translate_init.inc= .c > diff --git a/target/ppc/translate_init.inc.c b/target/ppc/translate_ini= t.inc.c > index d33d65dff70..ca241d7f5e6 100644 > --- a/target/ppc/translate_init.inc.c > +++ b/target/ppc/translate_init.inc.c > @@ -9845,7 +9845,7 @@ static int gdb_find_spr_idx(CPUPPCState *env, int= n) > return -1; > } > =20 > -static int gdb_get_spr_reg(CPUPPCState *env, uint8_t *mem_buf, int n) > +static int gdb_get_spr_reg(CPUPPCState *env, GByteArray *buf, int n) > { > int reg; > int len; > @@ -9856,8 +9856,8 @@ static int gdb_get_spr_reg(CPUPPCState *env, uint= 8_t *mem_buf, int n) > } > =20 > len =3D TARGET_LONG_SIZE; > - stn_p(mem_buf, len, env->spr[reg]); > - ppc_maybe_bswap_register(env, mem_buf, len); > + gdb_get_regl(buf, env->spr[reg]); > + ppc_maybe_bswap_register(env, buf->data - len, len); ppc_maybe_bswap_register(env, buf->data + buf->len - len, len); > return len; > } > =20 > @@ -9879,15 +9879,18 @@ static int gdb_set_spr_reg(CPUPPCState *env, ui= nt8_t *mem_buf, int n) > } > #endif > =20 > -static int gdb_get_float_reg(CPUPPCState *env, uint8_t *mem_buf, int n= ) > +static int gdb_get_float_reg(CPUPPCState *env, GByteArray *buf, int n) > { > + uint8_t *mem_buf; > if (n < 32) { > - stfq_p(mem_buf, *cpu_fpr_ptr(env, n)); > + gdb_get_reg64(buf, *cpu_fpr_ptr(env, n)); > + mem_buf =3D buf->data - 8; mem_buf =3D buf->data + buf->len - 8; > ppc_maybe_bswap_register(env, mem_buf, 8); > return 8; > } > if (n =3D=3D 32) { > - stl_p(mem_buf, env->fpscr); > + gdb_get_reg32(buf, env->fpscr); > + mem_buf =3D buf->data - 4; mem_buf =3D buf->data + buf->len - 4; > ppc_maybe_bswap_register(env, mem_buf, 4);> return 4; > } > @@ -9909,28 +9912,31 @@ static int gdb_set_float_reg(CPUPPCState *env, = uint8_t *mem_buf, int n) > return 0; > } > =20 > -static int gdb_get_avr_reg(CPUPPCState *env, uint8_t *mem_buf, int n) > +static int gdb_get_avr_reg(CPUPPCState *env, GByteArray *buf, int n) > { > + uint8_t *mem_buf; > + > if (n < 32) { > ppc_avr_t *avr =3D cpu_avr_ptr(env, n); > if (!avr_need_swap(env)) { > - stq_p(mem_buf, avr->u64[0]); > - stq_p(mem_buf + 8, avr->u64[1]); > + gdb_get_reg128(buf, avr->u64[0] , avr->u64[1]); > } else { > - stq_p(mem_buf, avr->u64[1]); > - stq_p(mem_buf + 8, avr->u64[0]); > + gdb_get_reg128(buf, avr->u64[1] , avr->u64[0]); > } > + mem_buf =3D buf->data - 16; mem_buf =3D buf->data + buf->len - 16; > ppc_maybe_bswap_register(env, mem_buf, 8); > ppc_maybe_bswap_register(env, mem_buf + 8, 8); > return 16; > } > if (n =3D=3D 32) { > - stl_p(mem_buf, helper_mfvscr(env)); > + gdb_get_reg32(buf, helper_mfvscr(env)); > + mem_buf =3D buf->data - 4; mem_buf =3D buf->data + buf->len - 4; > ppc_maybe_bswap_register(env, mem_buf, 4); > return 4; > } > if (n =3D=3D 33) { > - stl_p(mem_buf, (uint32_t)env->spr[SPR_VRSAVE]); > + gdb_get_reg32(buf, (uint32_t)env->spr[SPR_VRSAVE]); > + mem_buf =3D buf->data - 4; mem_buf =3D buf->data + buf->len - 4; > ppc_maybe_bswap_register(env, mem_buf, 4); > return 4; > } > @@ -9965,25 +9971,25 @@ static int gdb_set_avr_reg(CPUPPCState *env, ui= nt8_t *mem_buf, int n) > return 0; > } > =20 > -static int gdb_get_spe_reg(CPUPPCState *env, uint8_t *mem_buf, int n) > +static int gdb_get_spe_reg(CPUPPCState *env, GByteArray *buf, int n) > { > if (n < 32) { > #if defined(TARGET_PPC64) > - stl_p(mem_buf, env->gpr[n] >> 32); > - ppc_maybe_bswap_register(env, mem_buf, 4); > + gdb_get_reg32(buf, env->gpr[n] >> 32); > + ppc_maybe_bswap_register(env, buf->data - 4, 4); ppc_maybe_bswap_register(env, buf->data + buf->len - 4, 4); > #else > - stl_p(mem_buf, env->gprh[n]); > + gdb_get_reg32(buf, env->gprh[n]); > #endif > return 4; > } > if (n =3D=3D 32) { > - stq_p(mem_buf, env->spe_acc); > - ppc_maybe_bswap_register(env, mem_buf, 8); > + gdb_get_reg64(buf, env->spe_acc); > + ppc_maybe_bswap_register(env, buf->data - 8, 8); ppc_maybe_bswap_register(env, buf->data + buf->len - 8, 8); > return 8; > } > if (n =3D=3D 33) { > - stl_p(mem_buf, env->spe_fscr); > - ppc_maybe_bswap_register(env, mem_buf, 4); > + gdb_get_reg32(buf, env->spe_fscr); > + ppc_maybe_bswap_register(env, buf->data - 4, 4); ppc_maybe_bswap_register(env, buf->data + buf->len - 4, 4); > return 4; > } > return 0; > @@ -10018,11 +10024,11 @@ static int gdb_set_spe_reg(CPUPPCState *env, = uint8_t *mem_buf, int n) > return 0; > } > =20 > -static int gdb_get_vsx_reg(CPUPPCState *env, uint8_t *mem_buf, int n) > +static int gdb_get_vsx_reg(CPUPPCState *env, GByteArray *buf, int n) > { > if (n < 32) { > - stq_p(mem_buf, *cpu_vsrl_ptr(env, n)); > - ppc_maybe_bswap_register(env, mem_buf, 8); > + gdb_get_reg64(buf, *cpu_vsrl_ptr(env, n)); > + ppc_maybe_bswap_register(env, buf->data - 8, 8); ppc_maybe_bswap_register(env, buf->data + buf->len - 8, 8); > return 8; > } > return 0; With these fixes, Reviewed-by: Damien Hedde Damien From MAILER-DAEMON Fri Dec 20 11:26:55 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1iiL79-0000fj-GO for mharc-qemu-arm@gnu.org; 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[84.227.176.239]) by smtp.gmail.com with ESMTPSA id g25sm14129132wmh.3.2019.12.20.08.26.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 20 Dec 2019 08:26:47 -0800 (PST) Date: Fri, 20 Dec 2019 17:26:42 +0100 From: Jean-Philippe Brucker To: Auger Eric Cc: Peter Xu , yang.zhong@intel.com, peter.maydell@linaro.org, kevin.tian@intel.com, tnowicki@marvell.com, mst@redhat.com, jean-philippe.brucker@arm.com, quintela@redhat.com, qemu-devel@nongnu.org, armbru@redhat.com, bharatb.linux@gmail.com, qemu-arm@nongnu.org, dgilbert@redhat.com, eric.auger.pro@gmail.com Subject: Re: [PATCH for-5.0 v11 08/20] virtio-iommu: Implement translate Message-ID: <20191220162642.GA2626852@myrica> References: <20191122182943.4656-1-eric.auger@redhat.com> <20191122182943.4656-9-eric.auger@redhat.com> <20191210193342.GJ3352@xz-x1> <44c0041d-68ad-796f-16cc-4bab7ba0f164@redhat.com> <20191219133308.GA4246@xz-x1> <9d58b293-ada0-353e-bba2-ad1f538dfc62@redhat.com> <20191219144936.GB50561@xz-x1> <9ec9d0d5-062b-f96b-c72c-4d15865ff9a1@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <9ec9d0d5-062b-f96b-c72c-4d15865ff9a1@redhat.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::343 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 20 Dec 2019 16:26:54 -0000 On Thu, Dec 19, 2019 at 04:09:47PM +0100, Auger Eric wrote: > >>>>>> @@ -412,19 +412,80 @@ static IOMMUTLBEntry virtio_iommu_translate(IOMMUMemoryRegion *mr, hwaddr addr, > >>>>>> int iommu_idx) > >>>>>> { > >>>>>> IOMMUDevice *sdev = container_of(mr, IOMMUDevice, iommu_mr); > >>>>>> + viommu_interval interval, *mapping_key; > >>>>>> + viommu_mapping *mapping_value; > >>>>>> + VirtIOIOMMU *s = sdev->viommu; > >>>>>> + viommu_endpoint *ep; > >>>>>> + bool bypass_allowed; > >>>>>> uint32_t sid; > >>>>>> + bool found; > >>>>>> + > >>>>>> + interval.low = addr; > >>>>>> + interval.high = addr + 1; > >>>>>> > >>>>>> IOMMUTLBEntry entry = { > >>>>>> .target_as = &address_space_memory, > >>>>>> .iova = addr, > >>>>>> .translated_addr = addr, > >>>>>> - .addr_mask = ~(hwaddr)0, > >>>>>> + .addr_mask = (1 << ctz32(s->config.page_size_mask)) - 1, > >>>>>> .perm = IOMMU_NONE, > >>>>>> }; > >>>>>> > >>>>>> + bypass_allowed = virtio_has_feature(s->acked_features, > >>>>>> + VIRTIO_IOMMU_F_BYPASS); > >>>>>> + > >>>>> > >>>>> Would it be easier to check bypass_allowed here once and then drop the > >>>>> latter [1] and [2] check? > >>>> bypass_allowed does not mean you systematically bypass. You bypass if > >>>> the SID is unknown or if the device is not attached to any domain. > >>>> Otherwise you translate. But maybe I miss your point. > >>> > >>> Ah ok, then could I ask how will this VIRTIO_IOMMU_F_BYPASS be used? > >>> For example, I think VT-d defines passthrough in a totally different > >>> way in that the PT mark will be stored in the per-device context > >>> entries, then we can allow a specific device to be pass-through when > >>> doing DMA. That information is explicit (e.g., unknown SID will > >>> always fail the DMA), and per-device. > >>> > >>> Here do you mean that you just don't put a device into any domain to > >>> show it wants to use PT? Then I'm not sure how do you identify > >>> whether this is a legal PT or a malicious device (e.g., an unknown > >>> device that even does not have any driver bound to it, which will also > >>> satisfy "unknown SID" and "not attached to any domain", iiuc). > >> > >> The virtio-iommu spec currently says: > >> > >> "If the VIRTIO_IOMMU_F_BYPASS feature is negotiated, all accesses from > >> unattached endpoints are > >> allowed and translated by the IOMMU using the identity function. If the > >> feature is not negotiated, any > >> memory access from an unattached endpoint fails. Upon attaching an > >> endpoint in bypass mode to a new > >> domain, any memory access from the endpoint fails, since the domain does > >> not contain any mapping. > >> " > >> > >> I guess this can serve the purpose of devices doing early accesses, > >> before the guest OS gets the hand and maps them? > > > > OK, so there's no global enablement knob for virtio-iommu? Hmm... Then: There is at the virtio transport level: the driver sets status to FEATURES_OK once it accepted the feature bits, and to DRIVER_OK once its fully operational. The virtio-iommu spec says: If the driver does not accept the VIRTIO_IOMMU_F_BYPASS feature, the device SHOULD NOT let endpoints access the guest-physical address space. So before features negotiation, there is no access. Afterwards it depends if the VIRTIO_IOMMU_F_BYPASS has been accepted by the driver. > well this is a global knob. If this is bot negotiated any unmapped > device can PT. > > My assumption above must be wrong as this is a negotiated feature so > anyway the virtio-iommu driver should be involved. > > I don't really remember the rationale of the feature bit tbh. I don't remember writing down a rationale for this bit, it was in the very first version (I think someone suggested it during the initial internal discussion) and I didn't remove it afterwards because it seems useful: Say a guest only wants to use the vIOMMU for userspace assignment and wants all other endpoints to bypass translation, which is our primary use-case. In other words booting Linux with iommu.passthrough=1. It can either create an identity domain for each endpoint (one MAP request with VA==PA) or it can set the VIRTIO_IOMMU_F_BYPASS bit. The device-side implementation should be more efficient with the latter, since you don't need to lookup the domain + address space for each access. > In "[virtio-dev] RE: [RFC] virtio-iommu version 0.4 " Jean discussed > that with Kevein. Sorry I cannot find the link. > > " If the endpoint is not attached to any address space, > then the device MAY abort the transaction." Hmm, that was regarding a "bypass" reserved memory region, which isn't in the current spec. > Kevin> From definition of BYPASS, it's orthogonal to whether there is an > address space attached, then should we still allow "May abort" behavior? > > Jean> The behavior is left as an implementation choice, and I'm not sure > it's worth enforcing in the architecture. If the endpoint isn't attached > to any domain then (unless VIRTIO_IOMMU_F_BYPASS is negotiated), it > isn't necessarily able to do DMA at all. The virtio-iommu device may > setup DMA mastering lazily, in which case any DMA transaction would > abort, or have setup DMA already, in which case the endpoint can access > MEM_T_BYPASS regions. > > Hopefully Jean will remember and comment on this. > > Thanks > > Eric > > > > > - This flag is a must for all virtio-iommu emulation, right? > > (otherwise I can't see how system bootstraps..) What do you mean by system bootstrap? One thing I've been wondering, and may be related, is how to handle a bootloader that wants to read for example an initrd from a virtio-block device that's behind the IOMMU. Either we allow the device to let any DMA bypass the device until FEATURES_OK, which is a source of vulnerabilities [1], or we have to implement some support for the virtio-iommu in the BIOS. Again the F_BYPASS bit would help for this, since all the BIOS has to do is set it on boot. However, F_BYPASS is optional, and more complex support is needed for setting up identity mappings. [1] See "IOMMU protection against I/O attacks: a vulnerability and a proof of concept" by Morgan et al, where a malicious device bypassing the IOMMU overwrites the IOMMU configuration as it is being created by the OS. Arguably we're not too concerned about malicious devices at the moment, but I'm not comfortable relaxing this. > > - Should this flag be gone right after OS starts (otherwise I think > > we still have the issue that any malicious device can be seen as > > in PT mode as default)? How is that done? Yes bypass mode assumes that devices and drivers aren't malicious, and the IOMMU is only used for things like assigning devices to guest userspace, or having large contiguous DMA buffers. Thanks, Jean From MAILER-DAEMON Fri Dec 20 11:51:14 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1iiLUg-0004yB-Jy for mharc-qemu-arm@gnu.org; Fri, 20 Dec 2019 11:51:14 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:58012) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iiLUd-0004wz-Du for qemu-arm@nongnu.org; Fri, 20 Dec 2019 11:51:13 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1iiLUb-0004cm-2j for qemu-arm@nongnu.org; Fri, 20 Dec 2019 11:51:10 -0500 Received: from us-smtp-1.mimecast.com ([207.211.31.81]:48268 helo=us-smtp-delivery-1.mimecast.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1iiLUa-0004ac-Ux for qemu-arm@nongnu.org; Fri, 20 Dec 2019 11:51:09 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1576860665; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=fgDeFh4F3QrW0JWVNUfCDpbGQwy2NPJTa62L0c+x87Q=; b=RAhaKftn/CbE+XljeBS3Mi/epoax9zeSvBdarztp/xJ1MfFREoZaFO4JuRK5HIgeoxcY21 aNGOG9jvsIEeG0fmNniHe773KcG9/JV44QbJfn+PhhqGMD0LGKSaJIQgYLXy+Io1+hUnch Cg63QOjtrKXk9rrWT6t50daa+O7r+Wg= Received: from mail-qk1-f199.google.com (mail-qk1-f199.google.com [209.85.222.199]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-49-MDNAwYF_Pj-n3VqHm1slzg-1; Fri, 20 Dec 2019 11:51:04 -0500 Received: by mail-qk1-f199.google.com with SMTP id w64so6321330qka.3 for ; Fri, 20 Dec 2019 08:51:03 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:in-reply-to; bh=dqOt5cZrKPUthXykYWOf9AFQe5eQNRQAfjnOmuE7SuI=; b=YGFf48Vz4dLXncT28SmuBsqlL0Fasi/b1S0WNcbVGg32U7Bh4+La9fByJ1eVJ29+54 zZjFdJVvwUayceU2PjFOIq7B8IXyHN+n8R37+YZRh+S6S02XmoYI5usOET8vcVRaqBBF ePmu5snjmwrQOFaNDRU56shC8tcIzoPRW+msDcAnNy/28Ze+w9SjE+b84ZNvYqoNzy2m BhjwS5DTdA0D01W9OZyV0yQFSLMCDvk/exOQlp4aLN92/OqhKQDIX2hpguSPQBka6xJD y5fXXNzmpMhpD/UF4MnQOcEHBsOtKDNVWlStHYA/S6NuUq4Hsin9ir03PRoFIRhUJcZM W8HQ== X-Gm-Message-State: APjAAAWdvy0TGERTALATtFsRe9mBsNdG0Ld5lEntRiDxU+d4hPSK79rR 5egiKROm30s8kMWRRc7AtKdxDAaCMMU+26yB/ArhOc8TxAF60uTQGDTUp0AQQVFvIH0zuWyhSeM ia/Y4meIhAN+h X-Received: by 2002:ac8:64a:: with SMTP id e10mr12270078qth.292.1576860663546; Fri, 20 Dec 2019 08:51:03 -0800 (PST) X-Google-Smtp-Source: APXvYqyLZHgYuZYFF7vIQT83vdhv5/yqOfH04evSC0QflDwKBTzxOmKBg0YYa7iSmUMAIAOWmeNzRQ== X-Received: by 2002:ac8:64a:: with SMTP id e10mr12270058qth.292.1576860663224; Fri, 20 Dec 2019 08:51:03 -0800 (PST) Received: from xz-x1 ([104.156.64.74]) by smtp.gmail.com with ESMTPSA id 2sm3002867qkv.98.2019.12.20.08.51.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 20 Dec 2019 08:51:02 -0800 (PST) Date: Fri, 20 Dec 2019 11:51:00 -0500 From: Peter Xu To: Jean-Philippe Brucker Cc: Auger Eric , yang.zhong@intel.com, peter.maydell@linaro.org, kevin.tian@intel.com, tnowicki@marvell.com, mst@redhat.com, jean-philippe.brucker@arm.com, quintela@redhat.com, qemu-devel@nongnu.org, armbru@redhat.com, bharatb.linux@gmail.com, qemu-arm@nongnu.org, dgilbert@redhat.com, eric.auger.pro@gmail.com Subject: Re: [PATCH for-5.0 v11 08/20] virtio-iommu: Implement translate Message-ID: <20191220165100.GA3780@xz-x1> References: <20191122182943.4656-1-eric.auger@redhat.com> <20191122182943.4656-9-eric.auger@redhat.com> <20191210193342.GJ3352@xz-x1> <44c0041d-68ad-796f-16cc-4bab7ba0f164@redhat.com> <20191219133308.GA4246@xz-x1> <9d58b293-ada0-353e-bba2-ad1f538dfc62@redhat.com> <20191219144936.GB50561@xz-x1> <9ec9d0d5-062b-f96b-c72c-4d15865ff9a1@redhat.com> <20191220162642.GA2626852@myrica> MIME-Version: 1.0 In-Reply-To: <20191220162642.GA2626852@myrica> X-MC-Unique: MDNAwYF_Pj-n3VqHm1slzg-1 X-Mimecast-Spam-Score: 0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable Content-Disposition: inline X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 207.211.31.81 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 20 Dec 2019 16:51:13 -0000 On Fri, Dec 20, 2019 at 05:26:42PM +0100, Jean-Philippe Brucker wrote: > There is at the virtio transport level: the driver sets status to > FEATURES_OK once it accepted the feature bits, and to DRIVER_OK once its > fully operational. The virtio-iommu spec says: >=20 > If the driver does not accept the VIRTIO_IOMMU_F_BYPASS feature, the > device SHOULD NOT let endpoints access the guest-physical address space= . >=20 > So before features negotiation, there is no access. Afterwards it depends > if the VIRTIO_IOMMU_F_BYPASS has been accepted by the driver. Before enabling virtio-iommu device, should we still let the devices to access the whole system address space? I believe that's at least what Intel IOMMUs are doing. From code-wise, its: if (likely(s->dmar_enabled)) { success =3D vtd_do_iommu_translate(vtd_as, vtd_as->bus, vtd_as->dev= fn, addr, flag & IOMMU_WO, &iotlb); } else { /* DMAR disabled, passthrough, use 4k-page*/ iotlb.iova =3D addr & VTD_PAGE_MASK_4K; iotlb.translated_addr =3D addr & VTD_PAGE_MASK_4K; iotlb.addr_mask =3D ~VTD_PAGE_MASK_4K; iotlb.perm =3D IOMMU_RW; success =3D true; } >From hardware-wise, an IOMMU should be close to transparent if you never enable it, imho. Otherwise I'm confused on how a guest (with virtio-iommu) could boot with a normal BIOS that does not contain a virtio-iommu driver. For example, what if the BIOS needs to read some block sectors (as you mentioned)? > > > - This flag is a must for all virtio-iommu emulation, right? > > > (otherwise I can't see how system bootstraps..) >=20 > What do you mean by system bootstrap? Sorry, I meant when the system boots before the OS. >=20 > One thing I've been wondering, and may be related, is how to handle a > bootloader that wants to read for example an initrd from a virtio-block > device that's behind the IOMMU. My understanding is that virtio devices are special in that they can use the VIRTIO_F_IOMMU_PLATFORM flag to bypass any vIOMMU (though, I don't think that'll work when virtio hardwares comes to the world.. because they can't really bypass the IOMMU hardware). > Either we allow the device to let any DMA > bypass the device until FEATURES_OK, which is a source of vulnerabilities > [1], or we have to implement some support for the virtio-iommu in the > BIOS. Again the F_BYPASS bit would help for this, since all the BIOS has > to do is set it on boot. However, F_BYPASS is optional, and more complex > support is needed for setting up identity mappings. >=20 > [1] See "IOMMU protection against I/O attacks: a vulnerability and a proo= f > of concept" by Morgan et al, where a malicious device bypassing the IOMMU > overwrites the IOMMU configuration as it is being created by the OS. > Arguably we're not too concerned about malicious devices at the moment, > but I'm not comfortable relaxing this. >=20 > > > - Should this flag be gone right after OS starts (otherwise I think > > > we still have the issue that any malicious device can be seen as > > > in PT mode as default)? How is that done? >=20 > Yes bypass mode assumes that devices and drivers aren't malicious, and th= e > IOMMU is only used for things like assigning devices to guest userspace, > or having large contiguous DMA buffers. Yes I agree. However again when the BYPASS flag was introduced, have you thought of introducing that flag per-device? IMHO that could be better because you have a finer granularity on controlling all these, so you'll be able to reject malicious devices but at the meantime grant permission to trusted devices. Thanks, --=20 Peter Xu From MAILER-DAEMON Fri Dec 20 12:00:46 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1iiLdt-0000JA-4u for mharc-qemu-arm@gnu.org; Fri, 20 Dec 2019 12:00:46 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:40077) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iiLdm-0000Cb-4s for qemu-arm@nongnu.org; Fri, 20 Dec 2019 12:00:40 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1iiLdk-0007js-EN for qemu-arm@nongnu.org; Fri, 20 Dec 2019 12:00:37 -0500 Received: from mail-wr1-x441.google.com ([2a00:1450:4864:20::441]:35896) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1iiLdk-0007hz-2n for qemu-arm@nongnu.org; Fri, 20 Dec 2019 12:00:36 -0500 Received: by mail-wr1-x441.google.com with SMTP id z3so10108251wru.3 for ; Fri, 20 Dec 2019 09:00:35 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=date:from:to:cc:subject:message-id:references:mime-version :content-disposition:in-reply-to; bh=WS8ChejV4YO4dWg6kHYPfKg+xFnECZ3CCJJ2MBa8TKg=; b=R6Wb0GI3tLLJX1jKbcK6dL58ItO88nB1eLyPF9Xal+jobILpJSw3vgUjiZjljSuPKe j2xj5ZZDj1fBgRP1ge6bMhNq6Pa57PW5XG/S55HtjqxPX1/KqiVWr14CdiZQOwaBhbou e9CL5yV3YzWwb1CINwwlTS18Y8ZGo9fg75fPqdCojqI/4UdHHlcBsudznM82wbntNJ2H hWjCrtmnmMkdZmmL9ZUpWqtl6uUZft91JFAWwJCMojwRgIFvy4G5pgClZeX8EJYd77R0 hd5la9W/Ys14oieLR8SYbYFM7cSaNG7qG+cCojMEA9AT03FogkPuev5C5iT5oROZVxXE rpLA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:in-reply-to; bh=WS8ChejV4YO4dWg6kHYPfKg+xFnECZ3CCJJ2MBa8TKg=; b=QOUUGt+D2Qs0VZWXG4I3JZEh108jyUkuP63tu/frH5kcG03aqUCJ7rS81YDu5txxxd V/Qe2pOAO6GqkRRgatvCw5/cPDNacbVmvylWxmOhWtTj75nKEMtVgGAfTlBh3p2aMCXk 6hJ7opWZsnu1QgwNp5Nv9nYBb8b6FxHHiwwheexVeAf3C1lan56IM+2bT6xZ7EhpR7xw 85WdS+KaMV2d0gxt3Xu94Q7lt6P0hBUzOWimZsZA/zfLuf7kB+FOdhImajh2irvExA7d Vn62z+nNDF/xgaVLdEnmtXD0Jxzilsnl4AlFnVji1FnRkgQb+FvlWyegEICxpZg2we8T 60TQ== X-Gm-Message-State: APjAAAW7FGR+UemDI8KjCx85TMDVbJr3kdeCyeDAYH6BTlB8/5P995s0 ut7ecvQRlzRRZAlzIX+dWEzp7w== X-Google-Smtp-Source: APXvYqwnZvVHn8hXeig+Bwh4VMxvawK2cCdKC7uN3pVtR2RbsYsuU75RJD75st50/HbgS3s0iPUbJQ== X-Received: by 2002:a5d:6a83:: with SMTP id s3mr15575656wru.99.1576861234459; Fri, 20 Dec 2019 09:00:34 -0800 (PST) Received: from myrica (adsl-84-227-176-239.adslplus.ch. [84.227.176.239]) by smtp.gmail.com with ESMTPSA id x11sm10337438wmg.46.2019.12.20.09.00.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 20 Dec 2019 09:00:33 -0800 (PST) Date: Fri, 20 Dec 2019 18:00:28 +0100 From: Jean-Philippe Brucker To: Auger Eric Cc: yang.zhong@intel.com, peter.maydell@linaro.org, kevin.tian@intel.com, tnowicki@marvell.com, mst@redhat.com, jean-philippe.brucker@arm.com, quintela@redhat.com, qemu-devel@nongnu.org, peterx@redhat.com, armbru@redhat.com, bharatb.linux@gmail.com, qemu-arm@nongnu.org, dgilbert@redhat.com, eric.auger.pro@gmail.com Subject: Re: [PATCH for-5.0 v11 05/20] virtio-iommu: Endpoint and domains structs and helpers Message-ID: <20191220170028.GB2626852@myrica> References: <20191122182943.4656-1-eric.auger@redhat.com> <20191122182943.4656-6-eric.auger@redhat.com> <20191210163716.GD277340@myrica> <28597404-b9ac-8c16-e9e8-ad5793f2f5a3@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <28597404-b9ac-8c16-e9e8-ad5793f2f5a3@redhat.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::441 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 20 Dec 2019 17:00:41 -0000 On Thu, Dec 19, 2019 at 07:31:08PM +0100, Auger Eric wrote: > Hi Jean, > > On 12/10/19 5:37 PM, Jean-Philippe Brucker wrote: > > On Fri, Nov 22, 2019 at 07:29:28PM +0100, Eric Auger wrote: > >> +typedef struct viommu_domain { > >> + uint32_t id; > >> + GTree *mappings; > >> + QLIST_HEAD(, viommu_endpoint) endpoint_list; > >> +} viommu_domain; > >> + > >> +typedef struct viommu_endpoint { > >> + uint32_t id; > >> + viommu_domain *domain; > >> + QLIST_ENTRY(viommu_endpoint) next; > >> +} viommu_endpoint; > > > > There might be a way to merge viommu_endpoint and the IOMMUDevice > > structure introduced in patch 4, since they both represent one endpoint. > > Maybe virtio_iommu_find_add_pci_as() could add the IOMMUDevice to > > s->endpoints, and IOMMUDevice could store the endpoint ID rather than bus > > and devfn. > > On PCI bus enumeration we locally store the PCI bus hierarchy under the > form of GHashTable of IOMMUDevice indexed by iommu_pci_bus pointer. > Those are all the devices attached to the downstream buses. We also use > an array of iommu pci bus pointers indexed by bus number that is lazily > populated due to the fact, at enumeration time we do know the bus number > yet. As you pointed, I haven't used the array of iommu pci bus pointers > indexed by bus number in this series and I should actually. Currently I > am not checking on attach that the sid effectively corresponds to a sid > protected by this iommu. I will add this in my next version. The above > structures are used in intel_iommu and smmu code as well and I think > eventually this may be factorized a common base class.. > > on the other hand the gtree of viommu_endpoint - soon renamed in > CamelCase form ;-) - corresponds to the EPs that are actually attached > to any domain. It is indexed by sid and not by bus pointer. This is more > adapted to the virtio-iommu case. > > So, despite your suggestion, I am tempted to keep the different > structures as the first ones are common to all iommu emulation code and > the last is adapted to the virtio-iommu operations. > > Thoughts? Makes sense, it seems better to keep them separate. I had missed that the PCI bus number is resolved later, and started to move the endpoint ID into IOMMUDevice when adding MMIO support, but I'll need to revisit this. I'll be off for two weeks, have a nice holiday! Thanks, Jean From MAILER-DAEMON Fri Dec 20 15:27:33 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1iiOs0-0005GZ-Uz for mharc-qemu-arm@gnu.org; Fri, 20 Dec 2019 15:27:32 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:49817) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iiOry-0005G4-Fl for qemu-arm@nongnu.org; Fri, 20 Dec 2019 15:27:31 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1iiOrx-0001BE-9o for qemu-arm@nongnu.org; Fri, 20 Dec 2019 15:27:30 -0500 Received: from mail-lf1-x144.google.com ([2a00:1450:4864:20::144]:33416) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1iiOrx-00015Y-1i for qemu-arm@nongnu.org; Fri, 20 Dec 2019 15:27:29 -0500 Received: by mail-lf1-x144.google.com with SMTP id n25so8010058lfl.0 for ; Fri, 20 Dec 2019 12:27:28 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id; bh=+A6IT4c/+pZUoS/jx9YhK15VZ2D9C+6KzH019NBL3Lk=; b=sRgnOA159MyHYpx+XgaZ2+0MqiPQfUdXtPZYnI1SalCGd9/1Egm0LqXKt9rkloQdVl yvFWA10B/ZJUYJeKy7/tVG4cFp3qI9kRtqkdDx4nq97w+hOhRNUYnLGv2UjfFJ6CYuyd VoaLPQqhiYoPIW7oXQNptnUvE+1ZGoTABUaFdjemdNkxu3XlM7UumAw5Qxl73SS9EGen /BSaTB1dFTLlbIjJa6Zl+9yIW1imsUFhUEOM42MPAjVwuh2U9tk4TgrbVS0j8BXVr7Mm enKm0PezY/uS1742I+jVKc8NcEbOzpdTT5WuUWvcFvrXDJabWvxy54GHH29JYDAeJzBT 7/1g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=+A6IT4c/+pZUoS/jx9YhK15VZ2D9C+6KzH019NBL3Lk=; b=WniMeccHpZKxjp6yeIWQQP4x4PZluLtWyckTDTPqIxLYgxHwghVNmuJbc/1wqVyedF UdB4iAXd04m9PvrqnJgT/CHY9c2RCASdFZGk2T1R9v6h3Xz2EchTip45Vf9FLBHa8iIC EnrceU099d9A5RZPEqxgciInDSuCjFf+4IjAThm7ryKAAFts4L6Cb7zbtxtKXpDliTap uVeJ1VVUskg3JR1zQRaaud2BEJ4N+Fn7NBKpre3igaaE/QBejLQc52G0iuWqUaW6Ns5n 5D2UApfi2i9fvWmU9dG8gOUE5jCkz7N3YYIMb3N3cTeRUkoqm7PWNbaygl833Gy9ykrQ jdMQ== X-Gm-Message-State: APjAAAVFW4cbXxLq/M2/HFYsuRXa2OeKubV4Cnx/4YrYRzkdwK0hzDRZ 64L41QgT/2XKDXXVacg55CGe8Q== X-Google-Smtp-Source: APXvYqxQKOwc4bc9qs9P6M84ZzOLdO8TbugCAJSKar1LucSgOlT0wTbMiQStstUY8GQdmKFXUg79PA== X-Received: by 2002:a19:dc14:: with SMTP id t20mr10166439lfg.47.1576873646930; Fri, 20 Dec 2019 12:27:26 -0800 (PST) Received: from moi-limbo-9350.arm.com (user44-177.satfilm.com.pl. [77.91.44.177]) by smtp.gmail.com with ESMTPSA id g27sm4482353lfj.49.2019.12.20.12.27.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 20 Dec 2019 12:27:26 -0800 (PST) From: Beata Michalska To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, peter.maydell@linaro.org, pbonzini@redhat.com, Christoffer.Dall@arm.com Subject: [RFC PATCH 0/1] target/arm: kvm: Support for KVM DABT without valid ISS Date: Fri, 20 Dec 2019 20:27:06 +0000 Message-Id: <20191220202707.30641-1-beata.michalska@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::144 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 20 Dec 2019 20:27:31 -0000 Some of the ARMv7 & ARMv8 load/store instructions might trigger a data abort exception with no valid ISS info to be decoded. The lack of decode info makes it at least tricky to emulate the instruction which is one of the (many) reasons why KVM will not even try to do so. So far, if a guest made an attempt to access memory outside the memory slot, KVM reported vague ENOSYS. As a result QEMU exited with no useful information being provided or even a clue on what has just happened. Recently ARM KVM introduced support for notifying guest of an attempt to execute an instruction that resulted in dabt with no valid ISS decoding info. This still leaves QEMU to handle the case, but at least now, it can enable further debugging of the encountered issue by being more verbose in a (hopefully) useful way. Beata Michalska (1): target/arm: kvm: Handle DABT with no valid ISS accel/kvm/kvm-all.c | 15 +++++++ accel/stubs/kvm-stub.c | 4 ++ include/sysemu/kvm.h | 1 + target/arm/cpu.h | 3 +- target/arm/kvm.c | 95 ++++++++++++++++++++++++++++++++++++++++++ target/arm/kvm32.c | 3 ++ target/arm/kvm64.c | 3 ++ target/arm/kvm_arm.h | 19 +++++++++ 8 files changed, 142 insertions(+), 1 deletion(-) -- 2.17.1 From MAILER-DAEMON Fri Dec 20 15:27:39 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1iiOs7-0005Rp-Fh for mharc-qemu-arm@gnu.org; Fri, 20 Dec 2019 15:27:39 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:50945) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iiOs4-0005Ms-Fa for qemu-arm@nongnu.org; Fri, 20 Dec 2019 15:27:38 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1iiOs2-0001RY-J3 for qemu-arm@nongnu.org; Fri, 20 Dec 2019 15:27:36 -0500 Received: from mail-lf1-x142.google.com ([2a00:1450:4864:20::142]:33415) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1iiOs2-0001NK-7W for qemu-arm@nongnu.org; Fri, 20 Dec 2019 15:27:34 -0500 Received: by mail-lf1-x142.google.com with SMTP id n25so8010272lfl.0 for ; Fri, 20 Dec 2019 12:27:34 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=cRpSiBbQozDmyYgJRa0I9YSzeC8XG/jZayq+30fJx3E=; b=WJHVnI6L78/ZVkBh0jEK/DmML47DTl/cF+Sp7lG64oOvpW615FqzqSl3V5bg1d1Lu0 wMSnkJLmd1wyrqhX1SsYXGEkr2kAxGVZUt31ORKQbx6adTNJg2t2pPaLLzmDZjs/i9kn OozMmQ46BBOKwCBAIuUAWqqNQpW0lv8wwCP4BxGN/vSE16El7BWr7Ku47Qmn0xOa+Cf+ 26ImWFIOJM0gyhGkNp0AG3scipjDlwv7q9Ks8wa9aQkNlwApFeUXzDft2ThAXl4Txv09 n5RX5TkOi/8OXwgC35Aff4cIfAF6HbPhU/szAQWDXjcovVxDKoiOSBzvfy10KSCHxNj1 UjGw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=cRpSiBbQozDmyYgJRa0I9YSzeC8XG/jZayq+30fJx3E=; b=Mx0+b7c4dQsKS6JPTPp19GmgthZYS6xqOYwfX8vNDjRZTh2Q109RBMLqGrUR/iGCrI gqLKXn2YrvKrz/BD6rOVPvn13Ma5K1cLqgxCz8+QCbSWwcgx7/SEDjnZWx823vntYI97 YIOkjwxNMaasq5tfggdn/kyGKQZyIXgdSXU/iNB4FITYQpoGLdQs1lxekBD1TnnLrcGo 6/q8EwYazEfohs5OLRlFsx3zVAxfPDFk6Ifst8fzTW00z6B/Jvi8u4Y3LI7Dz6DO+bEe yrZZpUG56pSWppDI4kHbpjiNpKeeHyt3gxQw+b0GyzBjVBVlrfG7nbMEUL+wVEZRaNXs llZQ== X-Gm-Message-State: APjAAAXqWmbfDId7lDCR5eSqdxVhdnd+fHyJbfkO79fCYSqLv4WtE7DZ /MfCZnPYySGUBDXsVF/UPt3Odg== X-Google-Smtp-Source: APXvYqw1rEQ4Qf2bq7sRNo/PD3v4StFCkIUoDTB/R6Iy7iyQTYfklYncyaY8xeEsy6o01ed7sCh9Tg== X-Received: by 2002:ac2:47ec:: with SMTP id b12mr9689410lfp.162.1576873652736; Fri, 20 Dec 2019 12:27:32 -0800 (PST) Received: from moi-limbo-9350.arm.com (user44-177.satfilm.com.pl. [77.91.44.177]) by smtp.gmail.com with ESMTPSA id g27sm4482353lfj.49.2019.12.20.12.27.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 20 Dec 2019 12:27:32 -0800 (PST) From: Beata Michalska To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, peter.maydell@linaro.org, pbonzini@redhat.com, Christoffer.Dall@arm.com Subject: [RFC PATCH 1/1] target/arm: kvm: Handle DABT with no valid ISS Date: Fri, 20 Dec 2019 20:27:07 +0000 Message-Id: <20191220202707.30641-2-beata.michalska@linaro.org> In-Reply-To: <20191220202707.30641-1-beata.michalska@linaro.org> References: <20191220202707.30641-1-beata.michalska@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::142 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 20 Dec 2019 20:27:38 -0000 On ARMv7 & ARMv8 some load/store instructions might trigger a data abort exception with no valid ISS info to be decoded. The lack of decode info makes it at least tricky to emulate those instruction which is one of the (many) reasons why KVM will not even try to do so. Add suport for handling those by requesting KVM to inject external dabt into the quest. Signed-off-by: Beata Michalska --- accel/kvm/kvm-all.c | 15 +++++++ accel/stubs/kvm-stub.c | 4 ++ include/sysemu/kvm.h | 1 + target/arm/cpu.h | 3 +- target/arm/kvm.c | 95 ++++++++++++++++++++++++++++++++++++++++++ target/arm/kvm32.c | 3 ++ target/arm/kvm64.c | 3 ++ target/arm/kvm_arm.h | 19 +++++++++ 8 files changed, 142 insertions(+), 1 deletion(-) diff --git a/accel/kvm/kvm-all.c b/accel/kvm/kvm-all.c index ca00daa2f5..a3ee038142 100644 --- a/accel/kvm/kvm-all.c +++ b/accel/kvm/kvm-all.c @@ -2174,6 +2174,14 @@ static void do_kvm_cpu_synchronize_state(CPUState *cpu, run_on_cpu_data arg) } } +static void do_kvm_cpu_synchronize_state_force(CPUState *cpu, + run_on_cpu_data arg) +{ + kvm_arch_get_registers(cpu); + cpu->vcpu_dirty = true; +} + + void kvm_cpu_synchronize_state(CPUState *cpu) { if (!cpu->vcpu_dirty) { @@ -2181,6 +2189,13 @@ void kvm_cpu_synchronize_state(CPUState *cpu) } } +void kvm_cpu_synchronize_state_force(CPUState *cpu) +{ + /* Force the sync */ + run_on_cpu(cpu, do_kvm_cpu_synchronize_state_force, RUN_ON_CPU_NULL); +} + + static void do_kvm_cpu_synchronize_post_reset(CPUState *cpu, run_on_cpu_data arg) { kvm_arch_put_registers(cpu, KVM_PUT_RESET_STATE); diff --git a/accel/stubs/kvm-stub.c b/accel/stubs/kvm-stub.c index 82f118d2df..e917d1d55e 100644 --- a/accel/stubs/kvm-stub.c +++ b/accel/stubs/kvm-stub.c @@ -58,6 +58,10 @@ void kvm_cpu_synchronize_post_init(CPUState *cpu) { } +void kvm_cpu_synchronize_state_force(CPUState *cpu) +{ +} + int kvm_cpu_exec(CPUState *cpu) { abort(); diff --git a/include/sysemu/kvm.h b/include/sysemu/kvm.h index 9fe233b9bf..0cacc61d8a 100644 --- a/include/sysemu/kvm.h +++ b/include/sysemu/kvm.h @@ -483,6 +483,7 @@ void kvm_cpu_synchronize_state(CPUState *cpu); void kvm_cpu_synchronize_post_reset(CPUState *cpu); void kvm_cpu_synchronize_post_init(CPUState *cpu); void kvm_cpu_synchronize_pre_loadvm(CPUState *cpu); +void kvm_cpu_synchronize_state_force(CPUState *cpu); void kvm_init_cpu_signals(CPUState *cpu); diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 5f70e9e043..e11b5e7438 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -558,7 +558,8 @@ typedef struct CPUARMState { uint8_t has_esr; uint64_t esr; } serror; - + /* Status field for pending extarnal dabt */ + uint8_t ext_dabt_pending; /* State of our input IRQ/FIQ/VIRQ/VFIQ lines */ uint32_t irq_line_state; diff --git a/target/arm/kvm.c b/target/arm/kvm.c index 5b82cefef6..10fe739c2d 100644 --- a/target/arm/kvm.c +++ b/target/arm/kvm.c @@ -37,6 +37,7 @@ const KVMCapabilityInfo kvm_arch_required_capabilities[] = { static bool cap_has_mp_state; static bool cap_has_inject_serror_esr; +static bool cap_has_inject_ext_dabt; /* KVM_CAP_ARM_INJECT_EXT_DABT */ static ARMHostCPUFeatures arm_host_cpu_features; @@ -62,6 +63,12 @@ void kvm_arm_init_serror_injection(CPUState *cs) KVM_CAP_ARM_INJECT_SERROR_ESR); } +void kvm_arm_init_ext_dabt_injection(CPUState *cs) +{ + cap_has_inject_ext_dabt = kvm_check_extension(cs->kvm_state, + KVM_CAP_ARM_INJECT_EXT_DABT); +} + bool kvm_arm_create_scratch_host_vcpu(const uint32_t *cpus_to_try, int *fdarray, struct kvm_vcpu_init *init) @@ -218,6 +225,11 @@ int kvm_arch_init(MachineState *ms, KVMState *s) ret = -EINVAL; } + if (kvm_check_extension(s, KVM_CAP_ARM_NISV_TO_USER)) + if (kvm_vm_enable_cap(s, KVM_CAP_ARM_NISV_TO_USER, 0)) { + warn_report("Failed to enable DABT NISV cap"); + } + return ret; } @@ -600,6 +612,10 @@ int kvm_put_vcpu_events(ARMCPU *cpu) events.exception.serror_esr = env->serror.esr; } + if (cap_has_inject_ext_dabt) { + events.exception.ext_dabt_pending = env->ext_dabt_pending; + } + ret = kvm_vcpu_ioctl(CPU(cpu), KVM_SET_VCPU_EVENTS, &events); if (ret) { error_report("failed to put vcpu events"); @@ -629,6 +645,8 @@ int kvm_get_vcpu_events(ARMCPU *cpu) env->serror.has_esr = events.exception.serror_has_esr; env->serror.esr = events.exception.serror_esr; + env->ext_dabt_pending = events.exception.ext_dabt_pending; + return 0; } @@ -701,6 +719,11 @@ int kvm_arch_handle_exit(CPUState *cs, struct kvm_run *run) ret = EXCP_DEBUG; } /* otherwise return to guest */ break; + case KVM_EXIT_ARM_NISV: + /* External DAB with no valid iss to decode */ + ret = kvm_arm_handle_dabt_nisv(cs, run->arm_nisv.esr_iss, + run->arm_nisv.fault_ipa); + break; default: qemu_log_mask(LOG_UNIMP, "%s: un-handled exit reason %d\n", __func__, run->exit_reason); @@ -835,3 +858,75 @@ int kvm_arch_msi_data_to_gsi(uint32_t data) { return (data - 32) & 0xffff; } + +int kvm_arm_handle_dabt_nisv(CPUState *cs, uint64_t esr_iss, + uint64_t fault_ipa) +{ + ARMCPU *cpu = ARM_CPU(cs); + CPUARMState *env = &cpu->env; + hwaddr xlat, len; + AddressSpace *as = cs->as ? cs->as : &address_space_memory; + int store_ins = ((esr_iss >> 6) & 1); /* WnR bit */ + int ret; + + /* + * Note: The ioctl for SET_EVENTS will be triggered before next + * KVM_RUN call though the vcpu regs need to be updated before hand + * so to not to overwrite changes done by KVM upon injecting the abort. + * This sadly requires running sync twice - shame ... + */ + kvm_cpu_synchronize_state(cs); + /* + * ISS [23:14] is invalid so there is a limited info + * on what has just happened so the only *useful* thing that can + * be retrieved from ISS is WnR & DFSC (though in some cases WnR + * might be less of a value as well) + */ + /* Verify whether the memory being accessed is even recognisable */ + if (!address_space_translate(as, fault_ipa, &xlat, &len, + store_ins, MEMTXATTRS_UNSPECIFIED)) { + error_report("An attemp to access memory outside of the boundries" + "at 0x" TARGET_FMT_lx, (target_ulong) fault_ipa); + } else { + uint32_t ins; + uint8_t ins_fetched; + + /* + * Get current PC before it will get updated to except vector entry + */ + target_ulong ins_addr = is_a64(env) ? env->pc + /* AArch32 mode vs T32 aka Thumb mode */ + : env->regs[15] - (env->thumb ? 4 : 8); + + /* + * Get the faulting instruction + * Instructions have a fixed length of 32 bits + * and are always little-endian + */ + ins_fetched = !cpu_memory_rw_debug(cs, ins_addr, (uint8_t *) &ins, + sizeof(uint32_t), store_ins) ; + + error_report("Data abort exception with no valid ISS generated by " + "memory access at 0x" TARGET_FMT_lx, + (target_ulong)fault_ipa); + error_report(ins_fetched ? "%s: 0x%" PRIx32 " (encoded)" : "%s", + "Unable to emulate memory instruction", + (!ins_fetched ? 0 : ldl_le_p(&ins))); + + error_report("Faulting instruction at 0x" TARGET_FMT_lx, ins_addr); + } + /* + * Set pending ext dabt amd trigger SET_EVENTS so that + * KVM can inject the abort + */ + env->ext_dabt_pending = 1; + + ret = kvm_put_vcpu_events(cpu); + + /* Get the most up-tp-date state */ + if (!ret) { + /* Hacky but the sync needs to be forced */ + kvm_cpu_synchronize_state_force(cs); + } + return ret; +} diff --git a/target/arm/kvm32.c b/target/arm/kvm32.c index 32bf8d6757..5539c3a3f2 100644 --- a/target/arm/kvm32.c +++ b/target/arm/kvm32.c @@ -240,6 +240,9 @@ int kvm_arch_init_vcpu(CPUState *cs) /* Check whether userspace can specify guest syndrome value */ kvm_arm_init_serror_injection(cs); + /* Set status for supporting the extarnal dabt injection */ + kvm_arm_init_ext_dabt_injection(cs); + return kvm_arm_init_cpreg_list(cpu); } diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c index 876184b8fe..3da4e2e70e 100644 --- a/target/arm/kvm64.c +++ b/target/arm/kvm64.c @@ -792,6 +792,9 @@ int kvm_arch_init_vcpu(CPUState *cs) /* Check whether user space can specify guest syndrome value */ kvm_arm_init_serror_injection(cs); + /* Set status for supporting the extarnal dabt injection */ + kvm_arm_init_ext_dabt_injection(cs); + return kvm_arm_init_cpreg_list(cpu); } diff --git a/target/arm/kvm_arm.h b/target/arm/kvm_arm.h index 8e14d400e8..fe019f2fc9 100644 --- a/target/arm/kvm_arm.h +++ b/target/arm/kvm_arm.h @@ -143,6 +143,14 @@ void kvm_arm_reset_vcpu(ARMCPU *cpu); */ void kvm_arm_init_serror_injection(CPUState *cs); +/** + * kvm_arm_init_ext_dabt_injection + * @cs: CPUState + * + * Set status for KVM support for Ext DABT injection + */ +void kvm_arm_init_ext_dabt_injection(CPUState *cs); + /** * kvm_get_vcpu_events: * @cpu: ARMCPU @@ -371,6 +379,17 @@ static inline const char *gicv3_class_name(void) */ bool kvm_arm_handle_debug(CPUState *cs, struct kvm_debug_exit_arch *debug_exit); +/** + * kvm_arm_handle_dabt_nisv + * @cs: CPUState + * @esr_iss: ISS encoding (limited) for the exception from Data Abort + * ISV bit set to '0b0' -> no valid instruction syndrome + * @fault_ipa: faulting address for the synch data abort + * + * Returns: 0 if the exception has been handled + */ +int kvm_arm_handle_dabt_nisv(CPUState *cs, uint64_t esr_iss, + uint64_t fault_ipa); /** * kvm_arm_hw_debug_active: * @cs: CPU State -- 2.17.1 From MAILER-DAEMON Fri Dec 20 15:53:47 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1iiPHO-0000Ky-Tb for mharc-qemu-arm@gnu.org; Fri, 20 Dec 2019 15:53:46 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:43633) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iiPHL-0000Gn-9V for qemu-arm@nongnu.org; Fri, 20 Dec 2019 15:53:45 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1iiPHJ-0005mM-9J for qemu-arm@nongnu.org; Fri, 20 Dec 2019 15:53:43 -0500 Received: from mail-il1-x142.google.com ([2607:f8b0:4864:20::142]:40729) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1iiPHE-0005Lx-Me; Fri, 20 Dec 2019 15:53:36 -0500 Received: by mail-il1-x142.google.com with SMTP id c4so9086565ilo.7; Fri, 20 Dec 2019 12:53:36 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; 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Fri, 20 Dec 2019 12:53:34 -0800 (PST) MIME-Version: 1.0 References: <20191219185127.24388-1-f4bug@amsat.org> In-Reply-To: <20191219185127.24388-1-f4bug@amsat.org> From: Niek Linnenbank Date: Fri, 20 Dec 2019 21:53:23 +0100 Message-ID: Subject: Re: [RFC PATCH 00/13] hw/timer/allwinner: Make it reusable To: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= Cc: QEMU Developers , Peter Maydell , Beniamino Galvani , qemu-arm Content-Type: multipart/alternative; boundary="00000000000005d230059a28df59" X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::142 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 20 Dec 2019 20:53:45 -0000 --00000000000005d230059a28df59 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Hi Philippe, On Thu, Dec 19, 2019 at 7:51 PM Philippe Mathieu-Daud=C3=A9 wrote: > Hi, > > Niek added the H3 SoC in [1] and noticed in [2] the timer > controller is very similar (less timers, watchdog register > placed at different address). > > On 12/18/19 9:14 PM, Niek Linnenbank wrote: > > Actually, I copied the timer support code from the existing cubieboard.= c > > that has > > the Allwinner A10, so potentially the same problem is there. > > > > While looking more closer at this part, I now also discovered that the > > timer module from the Allwinner H3 is > > mostly a stripped down version of the timer module in the Allwinner A10= : > > > > Allwinner A10, 10.2 Timer Register List, page 85: > > https://linux-sunxi.org/images/1/1e/Allwinner_A10_User_manual_V1.5.pdf > > > > The A10 version has six timers, where the H3 has only two. That should > > be fine I would say, the guest would simply > > use those available on H3 and ignore the rest. There is however one > > conflicting difference: the WDOG0 registers in the Allwinner H3 start > > at a different offset and are also different. The current A10 timer doe= s > > not currently implement the watchdog part. > [...] > > So in my opinion its a bit of a trade off here: we can keep it like thi= s > > and re-use the A10 timer for now, and perhaps > > attempt to generalize that module for proper use in both SoCs. Or we ca= n > > introduce a new H3 specific timer module. > > What do you think? > > As an answer to his question, this series is to help him to > reuse the A10 timer controller instead of adding a new model > to the codebase. > Great!! This certainly answers my question indeed! I've applied this patch on top of the allwinner H3 v2 series to test it, and after changing the type from AwA10PITState to the new AllwinnerTmrCtrlState, the code compiled and ran linux/u-boot without any problems: diff --git a/include/hw/arm/allwinner-h3.h b/include/hw/arm/allwinner-h3.h index 357bdfa711..fa0219fa1b 100644 --- a/include/hw/arm/allwinner-h3.h +++ b/include/hw/arm/allwinner-h3.h @@ -76,7 +76,7 @@ typedef struct AwH3State { ARMCPU cpus[AW_H3_NUM_CPUS]; const hwaddr *memmap; - AwA10PITState timer; + AllwinnerTmrCtrlState timer; AwH3ClockState ccu; AwH3CpuCfgState cpucfg; AwH3SysconState syscon; Also, I tested with the A10 cubieboard machine, and it also still works fine: ./arm-softmmu/qemu-system-arm -M cubieboard -kernel zImage -nographic -append 'console=3DttyS0,115200 earlyprintk usbcore.nousb root=3D/dev/sda r= o init=3D/sbin/init' -dtb sun4i-a10-cubieboard.dtb -m 512 -drive file=3Drootfs.ext2,if=3Dnone,id=3Ddrive-sata0-0-0,format=3Draw -device ide-hd,bus=3Dide.0,drive=3Ddrive-sata0-0-0,id=3Dsata0-0-0 -nic user [ 0.000000] Booting Linux on physical CPU 0x0 [ 0.000000] Linux version 5.2.11 (me@host) (gcc version 5.4.0 20160609 (Ubuntu/Linaro 5.4.0-6ubuntu1~16.04.9)) #1 SMP Fri Sep 13 22:48:39 CEST 201= 9 [ 0.000000] CPU: ARMv7 Processor [410fc080] revision 0 (ARMv7), cr=3D10c5387d [ 0.000000] CPU: PIPT / VIPT nonaliasing data cache, VIPT nonaliasing instruction cache [ 0.000000] OF: fdt: Machine model: Cubietech Cubieboard ... So for me this works with both the H3 and A10: Tested-by: Niek Linnenbank Regards, Niek > > [1] https://www.mail-archive.com/qemu-devel@nongnu.org/msg665532.html > [2] https://www.mail-archive.com/qemu-devel@nongnu.org/msg666304.html > > Philippe Mathieu-Daud=C3=A9 (13): > hw/timer/allwinner: Use the AW_A10_PIT_TIMER_NR definition > hw/timer/allwinner: Add AW_PIT_TIMER_MAX definition > hw/timer/allwinner: Remove unused definitions > hw/timer/allwinner: Move definitions from header to source > hw/timer/allwinner: Rename the ptimer field > hw/timer/allwinner: Rename 'timer_context' as 'timer' > hw/timer/allwinner: Move timer specific fields into AwA10TimerContext > hw/timer/allwinner: Add a timer_count field > hw/timer/allwinner: Rename AwA10TimerContext as AllwinnerTmrState > hw/timer/allwinner: Rename AwA10PITState as AllwinnerTmrCtrlState > hw/timer/allwinner: Introduce TYPE_AW_COMMON_PIT abstract device > hw/timer/allwinner: Rename AW_A10_PIT() as AW_TIMER_CTRL() > hw/timer/allwinner: Rename functions not specific to the A10 SoC > > include/hw/arm/allwinner-a10.h | 2 +- > include/hw/timer/allwinner-a10-pit.h | 54 ++---- > hw/timer/allwinner-a10-pit.c | 271 +++++++++++++++++---------- > 3 files changed, 192 insertions(+), 135 deletions(-) > > -- > 2.21.0 > > --=20 Niek Linnenbank --00000000000005d230059a28df59 Content-Type: text/html; charset="UTF-8" Content-Transfer-Encoding: quoted-printable
Hi Philippe,

On Thu, Dec 19, 2019 at 7:51 P= M Philippe Mathieu-Daud=C3=A9 <f4bug@= amsat.org> wrote:
Hi,

Niek added the H3 SoC in [1] and noticed in [2] the timer
controller is very similar (less timers, watchdog register
placed at different address).

On 12/18/19 9:14 PM, Niek Linnenbank wrote:
> Actually, I copied the timer support code from the existing cubieboard= .c
> that has
> the Allwinner A10, so potentially the same problem is there.
>
> While looking more closer at this part, I now also discovered that the=
> timer module from the Allwinner H3 is
> mostly a stripped down version of the timer module in the Allwinner A1= 0:
>
>=C2=A0 =C2=A0 Allwinner A10, 10.2 Timer Register List, page 85:
> https://linux-sunxi.org/i= mages/1/1e/Allwinner_A10_User_manual_V1.5.pdf
>
> The A10 version has six timers, where the H3 has only two. That should=
> be fine I would say, the guest would simply
> use those available on H3 and ignore the rest. There is however one > conflicting difference: the WDOG0 registers in the Allwinner H3 start<= br> > at a different offset and are also different. The current A10 timer do= es
> not currently implement the watchdog part.
[...]
> So in my opinion its a bit of a trade off here: we can keep it like th= is
> and re-use the A10 timer for now, and perhaps
> attempt to generalize that module for proper use in both SoCs. Or we c= an
> introduce a new H3 specific timer module.
> What do you think?

As an answer to his question, this series is to help him to
reuse the A10 timer controller instead of adding a new model
to the codebase.

Great!! This certainly= answers my question indeed!

I've applied this= patch on top of the allwinner H3 v2 series to test it, and after
changing the type from AwA10PITState to the new AllwinnerTmrCtrlState,
the code compiled and ran linux/u-boot without any problems:

diff --git a/includ= e/hw/arm/allwinner-h3.h b/include/hw/arm/allwinner-h3.h
index 357bdfa711= ..fa0219fa1b 100644
--- a/include/hw/arm/allwinner-h3.h
+++ b/include= /hw/arm/allwinner-h3.h
@@ -76,7 +76,7 @@ typedef struct AwH3State {
= =C2=A0
=C2=A0 =C2=A0 =C2=A0ARMCPU cpus[AW_H3_NUM_CPUS];
=C2=A0 =C2=A0= =C2=A0const hwaddr *memmap;
- =C2=A0 =C2=A0AwA10PITState timer;
+ = =C2=A0 =C2=A0AllwinnerTmrCtrlState timer;
=C2=A0 =C2=A0 =C2=A0AwH3ClockS= tate ccu;
=C2=A0 =C2=A0 =C2=A0AwH3CpuCfgState cpucfg;
=C2=A0 =C2=A0 = =C2=A0AwH3SysconState syscon;

Also, I t= ested with the A10 cubieboard machine, and it also still works fine:
<= div>
./arm-softmmu/qemu= -system-arm -M cubieboard -kernel zImage -nographic -append 'console=3D= ttyS0,115200 earlyprintk usbcore.nousb root=3D/dev/sda ro init=3D/sbin/init= ' -dtb sun4i-a10-cubieboard.dtb -m 512 -drive file=3Drootfs.ext2,if=3Dn= one,id=3Ddrive-sata0-0-0,format=3Draw -device ide-hd,bus=3Dide.0,drive=3Ddr= ive-sata0-0-0,id=3Dsata0-0-0 -nic user
[ =C2=A0 =C2=A00.000000] Booting Linux on physical = CPU 0x0
[ =C2=A0 =C2=A00.000000] Linux version 5.2.11 (me@host) (gcc ver= sion 5.4.0 20160609 (Ubuntu/Linaro 5.4.0-6ubuntu1~16.04.9)) #1 SMP Fri Sep = 13 22:48:39 CEST 2019
[ =C2=A0 =C2=A00.000000] CPU: ARMv7 Processor [410= fc080] revision 0 (ARMv7), cr=3D10c5387d
[ =C2=A0 =C2=A00.000000] CPU: P= IPT / VIPT nonaliasing data cache, VIPT nonaliasing instruction cache
[ = =C2=A0 =C2=A00.000000] OF: fdt: Machine model: Cubietech Cubieboard
...

So for me this works w= ith both the H3 and A10:
=C2=A0 Tested-by: Niek Lin= nenbank <nieklinnenbank@gmai= l.com>
=C2=A0
Regards,
Niek

[1] https://www.mail-archive.com/qe= mu-devel@nongnu.org/msg665532.html
[2] https://www.mail-archive.com/qe= mu-devel@nongnu.org/msg666304.html

Philippe Mathieu-Daud=C3=A9 (13):
=C2=A0 hw/timer/allwinner: Use the AW_A10_PIT_TIMER_NR definition
=C2=A0 hw/timer/allwinner: Add AW_PIT_TIMER_MAX definition
=C2=A0 hw/timer/allwinner: Remove unused definitions
=C2=A0 hw/timer/allwinner: Move definitions from header to source
=C2=A0 hw/timer/allwinner: Rename the ptimer field
=C2=A0 hw/timer/allwinner: Rename 'timer_context' as 'timer'= ;
=C2=A0 hw/timer/allwinner: Move timer specific fields into AwA10TimerContex= t
=C2=A0 hw/timer/allwinner: Add a timer_count field
=C2=A0 hw/timer/allwinner: Rename AwA10TimerContext as AllwinnerTmrState =C2=A0 hw/timer/allwinner: Rename AwA10PITState as AllwinnerTmrCtrlState =C2=A0 hw/timer/allwinner: Introduce TYPE_AW_COMMON_PIT abstract device
=C2=A0 hw/timer/allwinner: Rename AW_A10_PIT() as AW_TIMER_CTRL()
=C2=A0 hw/timer/allwinner: Rename functions not specific to the A10 SoC

=C2=A0include/hw/arm/allwinner-a10.h=C2=A0 =C2=A0 =C2=A0 =C2=A0|=C2=A0 =C2= =A02 +-
=C2=A0include/hw/timer/allwinner-a10-pit.h |=C2=A0 54 ++----
=C2=A0hw/timer/allwinner-a10-pit.c=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0| 271 += ++++++++++++++++----------
=C2=A03 files changed, 192 insertions(+), 135 deletions(-)

--
2.21.0



--
Niek Linnenbank

--00000000000005d230059a28df59-- From MAILER-DAEMON Fri Dec 20 16:11:26 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1iiPYT-0002Dm-U7 for mharc-qemu-arm@gnu.org; Fri, 20 Dec 2019 16:11:25 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:59525) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iiPYP-0002Ag-PA for qemu-arm@nongnu.org; Fri, 20 Dec 2019 16:11:24 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1iiPYO-0004Cu-2N for qemu-arm@nongnu.org; Fri, 20 Dec 2019 16:11:21 -0500 Received: from mail-io1-xd44.google.com ([2607:f8b0:4864:20::d44]:34910) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1iiPYJ-0003kA-Ec; Fri, 20 Dec 2019 16:11:15 -0500 Received: by mail-io1-xd44.google.com with SMTP id v18so10792979iol.2; Fri, 20 Dec 2019 13:11:12 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=VvkgRQ4HhizmbLmgoQ+HomXQu31tz6OEWac2k/Z2GhI=; b=GwBpUab8Bvm53uyrZiKJk6wxuBXApq1m0twa1ILg2vcYXx6/q9lAPhtmUk1f6/2Dkk jZISrzG4WXJcsdVRfxu7rJT6jw61Gb6DV/N7YCXye753EDTE2PgPuNBQY9yLdwDVCalE piT7gCA5LxtWzHO55Fs6Vvyp/U6NfRr9towqGfGqQA/6HOgKY7wOqLUht08aqMoJZRkO fUj/H67FJvF6g2MPAF2J+lotnzproXZ6UBZNRX2GSAYUrHxXv0PDpy0PoZhAB/dH+gM4 +u7iPjN3ap42WApqaJbuoCvUuYfuwl3oT1/h5wmHx4VJ6YfR4d7mi8NUplUkyiuz4/Pb GqzA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=VvkgRQ4HhizmbLmgoQ+HomXQu31tz6OEWac2k/Z2GhI=; b=UiVi49+WbX1Hni2Jubh+UATVMgWFFgUOtz52UnRuGwq7Fg+nBEeHlykQdnTI4MJDha Ge3M//UrEwmT7WQEkVKLBAOLt5SHj9AIxRp9n+h/XgPzAJqssC8GU5eLk01RIiFyMhXG HQox6YRT5wjYqX3KQP7oJyvYoCBlqaujyHJc4xCix2lUnrCOtyiFzOGOSYJ+jM4Dn9o4 DwhfW5N6lB2oZqkV7QUThsxDrY+x/6ExpH+Bqu+tP+O1PU7FBcZNKXd5tnAJ6q5gceAj XAvtlY+V1n8s7E6QhIojrQMl2lBpidv6H1LVNU+3wgY0oBYK7TuZiTHBqgCXCt0Pk6Jg GyXA== X-Gm-Message-State: APjAAAUftwM1tAnr7NuQIA9pRwe4VYEDWozEbalq2ln1SjXLq/lCd0PL A1rrY8V9PmZtPi1iIZQsvF8XRizBDkphgyctisg= X-Google-Smtp-Source: APXvYqyKR9mUFkbbOsIGGOs6h2zziu44MclJqjiqYpshiKTyVc6fYbjnkArddSUDIKn0TivfMaHXzhdhs7ElGLaY5Nc= X-Received: by 2002:a6b:d912:: with SMTP id r18mr5454210ioc.306.1576876271643; Fri, 20 Dec 2019 13:11:11 -0800 (PST) MIME-Version: 1.0 References: <20191219185127.24388-1-f4bug@amsat.org> <20191219185127.24388-12-f4bug@amsat.org> In-Reply-To: <20191219185127.24388-12-f4bug@amsat.org> From: Niek Linnenbank Date: Fri, 20 Dec 2019 22:11:00 +0100 Message-ID: Subject: Re: [RFC PATCH 11/13] hw/timer/allwinner: Introduce TYPE_AW_COMMON_PIT abstract device To: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= Cc: QEMU Developers , Peter Maydell , Beniamino Galvani , qemu-arm Content-Type: multipart/alternative; boundary="00000000000006aff2059a291ebc" X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::d44 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 20 Dec 2019 21:11:24 -0000 --00000000000006aff2059a291ebc Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Hi Philippe, On Thu, Dec 19, 2019 at 7:51 PM Philippe Mathieu-Daud=C3=A9 wrote: > Extract the common code from the TYPE_AW_A10_PIT device into a new > abstract device: TYPE_AW_COMMON_PIT, then use it as parent, so we > inherit the same functionalities. > > Signed-off-by: Philippe Mathieu-Daud=C3=A9 > --- > At this point, the only fields we can modify are the timer_count > and the region_size. Not enough to implement the H3 timer, since > we need to move the WDOG register. Still some progress, so Niek > can continue ;) > --- > include/hw/timer/allwinner-a10-pit.h | 1 + > hw/timer/allwinner-a10-pit.c | 50 +++++++++++++++++++++++----- > 2 files changed, 43 insertions(+), 8 deletions(-) > > diff --git a/include/hw/timer/allwinner-a10-pit.h > b/include/hw/timer/allwinner-a10-pit.h > index 9e28c6697a..8453a62706 100644 > --- a/include/hw/timer/allwinner-a10-pit.h > +++ b/include/hw/timer/allwinner-a10-pit.h > @@ -4,6 +4,7 @@ > #include "hw/ptimer.h" > #include "hw/sysbus.h" > > +#define TYPE_AW_COMMON_PIT "allwinner-timer-controller" > #define TYPE_AW_A10_PIT "allwinner-A10-timer" > So for the Allwinner H3, that means we'll need another TYPE_AW_H3_PIT definition? > > #define AW_PIT_TIMER_MAX 6 > diff --git a/hw/timer/allwinner-a10-pit.c b/hw/timer/allwinner-a10-pit.c > index f2ac271e80..ad409b96a1 100644 > --- a/hw/timer/allwinner-a10-pit.c > +++ b/hw/timer/allwinner-a10-pit.c > Perhaps we can rename the hw/timer/allwinner-a10-pit.c to a generic name, for example hw/timer/allwinner-pit.c ? > @@ -54,6 +54,20 @@ > #define AW_A10_PIT(obj) \ > OBJECT_CHECK(AllwinnerTmrCtrlState, (obj), TYPE_AW_A10_PIT) > > +typedef struct AllwinnerTmrCtrlClass { > + /*< private >*/ > + SysBusDeviceClass parent_class; > + /*< public >*/ > + > + size_t timer_count; > + size_t region_size; > +} AllwinnerTmrCtrlClass; > + > +#define AW_TIMER_CLASS(klass) \ > + OBJECT_CLASS_CHECK(AllwinnerTmrCtrlClass, (klass), > TYPE_AW_COMMON_PIT) > +#define AW_TIMER_GET_CLASS(obj) \ > + OBJECT_GET_CLASS(AllwinnerTmrCtrlClass, (obj), TYPE_AW_COMMON_PIT) > + > static void a10_pit_update_irq(AllwinnerTmrCtrlState *s) > { > int i; > @@ -303,19 +317,20 @@ static void a10_pit_timer_cb(void *opaque) > } > } > > -static void a10_pit_init(Object *obj) > +static void aw_pit_instance_init(Object *obj) > { > AllwinnerTmrCtrlState *s =3D AW_A10_PIT(obj); > + AllwinnerTmrCtrlClass *c =3D AW_TIMER_GET_CLASS(s); > SysBusDevice *sbd =3D SYS_BUS_DEVICE(obj); > uint8_t i; > > - s->timer_count =3D AW_A10_PIT_TIMER_NR; > + s->timer_count =3D c->timer_count; > > for (i =3D 0; i < s->timer_count; i++) { > sysbus_init_irq(sbd, &s->timer[i].irq); > } > memory_region_init_io(&s->iomem, OBJECT(s), &a10_pit_ops, s, > I am curious how to support the different WDOG0 registers for the Allwinner H3 while keeping the A10 functionality also working :-) Will you give the TYPE_AW_H3_PIT its own MemoryRegionOps with read/write? > - TYPE_AW_A10_PIT, 0x400); > + TYPE_AW_A10_PIT, c->region_size); > sysbus_init_mmio(sbd, &s->iomem); > > for (i =3D 0; i < s->timer_count; i++) { > @@ -328,26 +343,45 @@ static void a10_pit_init(Object *obj) > } > } > > -static void a10_pit_class_init(ObjectClass *klass, void *data) > +static void aw_timer_class_init(ObjectClass *klass, void *data) > { > DeviceClass *dc =3D DEVICE_CLASS(klass); > > dc->reset =3D a10_pit_reset; > dc->props =3D a10_pit_properties; > - dc->desc =3D "allwinner a10 timer"; > + dc->desc =3D "Allwinner Timer Controller"; > dc->vmsd =3D &vmstate_a10_pit; > } > > +static const TypeInfo allwinner_pit_info =3D { > + .name =3D TYPE_AW_COMMON_PIT, > + .parent =3D TYPE_SYS_BUS_DEVICE, > + .instance_init =3D aw_pit_instance_init, > + .instance_size =3D sizeof(AllwinnerTmrCtrlState), > + .class_init =3D aw_timer_class_init, > + .class_size =3D sizeof(AllwinnerTmrCtrlClass), > + .abstract =3D true, > +}; > + > +static void a10_pit_class_init(ObjectClass *klass, void *data) > +{ > + DeviceClass *dc =3D DEVICE_CLASS(klass); > + AllwinnerTmrCtrlClass *atc =3D AW_TIMER_CLASS(klass); > + > + dc->desc =3D "Allwinner A10 Timer Controller"; > + atc->timer_count =3D AW_A10_PIT_TIMER_NR; > + atc->region_size =3D 0x400; > +} > + > static const TypeInfo a10_pit_info =3D { > .name =3D TYPE_AW_A10_PIT, > - .parent =3D TYPE_SYS_BUS_DEVICE, > - .instance_size =3D sizeof(AllwinnerTmrCtrlState), > - .instance_init =3D a10_pit_init, > + .parent =3D TYPE_AW_COMMON_PIT, > .class_init =3D a10_pit_class_init, > }; > > static void a10_register_types(void) > { > + type_register_static(&allwinner_pit_info); > type_register_static(&a10_pit_info); > } > > -- > 2.21.0 > > --=20 Niek Linnenbank --00000000000006aff2059a291ebc Content-Type: text/html; charset="UTF-8" Content-Transfer-Encoding: quoted-printable
Hi Philippe,

=
On Thu, Dec 19, 2019 at 7:51 PM Phili= ppe Mathieu-Daud=C3=A9 <f4bug@amsat.o= rg> wrote:
f4bug@amsat.org>
---
At this point, the only fields we can modify are the timer_count
and the region_size. Not enough to implement the H3 timer, since
we need to move the WDOG register. Still some progress, so Niek
can continue ;)
---
=C2=A0include/hw/timer/allwinner-a10-pit.h |=C2=A0 1 +
=C2=A0hw/timer/allwinner-a10-pit.c=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0| 50 ++= +++++++++++++++++++++-----
=C2=A02 files changed, 43 insertions(+), 8 deletions(-)

diff --git a/include/hw/timer/allwinner-a10-pit.h b/include/hw/timer/allwin= ner-a10-pit.h
index 9e28c6697a..8453a62706 100644
--- a/include/hw/timer/allwinner-a10-pit.h
+++ b/include/hw/timer/allwinner-a10-pit.h
@@ -4,6 +4,7 @@
=C2=A0#include "hw/ptimer.h"
=C2=A0#include "hw/sysbus.h"

+#define TYPE_AW_COMMON_PIT "allwinner-timer-controller"
=C2=A0#define TYPE_AW_A10_PIT "allwinner-A10-timer"

So for the Allwinner H3, that means we'll need a= nother TYPE_AW_H3_PIT definition?
=C2=A0

=C2=A0#define AW_PIT_TIMER_MAX=C2=A0 =C2=A0 =C2=A0 =C2=A0 6
diff --git a/hw/timer/allwinner-a10-pit.c b/hw/timer/allwinner-a10-pit.c index f2ac271e80..ad409b96a1 100644
--- a/hw/timer/allwinner-a10-pit.c
+++ b/hw/timer/allwinner-a10-pit.c

Perh= aps we can rename the hw/timer/allwinner-a10-pit.c to a generic name, for e= xample hw/timer/allwinner-pit.c ?
=C2=A0
@@ -54,6 +54,20 @@
=C2=A0#define AW_A10_PIT(obj) \
=C2=A0 =C2=A0 =C2=A0OBJECT_CHECK(AllwinnerTmrCtrlState, (obj), TYPE_AW_A10_= PIT)

+typedef struct AllwinnerTmrCtrlClass {
+=C2=A0 =C2=A0 /*< private >*/
+=C2=A0 =C2=A0 SysBusDeviceClass parent_class;
+=C2=A0 =C2=A0 /*< public >*/
+
+=C2=A0 =C2=A0 size_t timer_count;
+=C2=A0 =C2=A0 size_t region_size;
+} AllwinnerTmrCtrlClass;
+
+#define AW_TIMER_CLASS(klass) \
+=C2=A0 =C2=A0 =C2=A0OBJECT_CLASS_CHECK(AllwinnerTmrCtrlClass, (klass), TYP= E_AW_COMMON_PIT)
+#define AW_TIMER_GET_CLASS(obj) \
+=C2=A0 =C2=A0 =C2=A0OBJECT_GET_CLASS(AllwinnerTmrCtrlClass, (obj), TYPE_AW= _COMMON_PIT)
+
=C2=A0static void a10_pit_update_irq(AllwinnerTmrCtrlState *s)
=C2=A0{
=C2=A0 =C2=A0 =C2=A0int i;
@@ -303,19 +317,20 @@ static void a10_pit_timer_cb(void *opaque)
=C2=A0 =C2=A0 =C2=A0}
=C2=A0}

-static void a10_pit_init(Object *obj)
+static void aw_pit_instance_init(Object *obj)
=C2=A0{
=C2=A0 =C2=A0 =C2=A0AllwinnerTmrCtrlState *s =3D AW_A10_PIT(obj);
+=C2=A0 =C2=A0 AllwinnerTmrCtrlClass *c =3D AW_TIMER_GET_CLASS(s);
=C2=A0 =C2=A0 =C2=A0SysBusDevice *sbd =3D SYS_BUS_DEVICE(obj);
=C2=A0 =C2=A0 =C2=A0uint8_t i;

-=C2=A0 =C2=A0 s->timer_count =3D AW_A10_PIT_TIMER_NR;
+=C2=A0 =C2=A0 s->timer_count =3D c->timer_count;

=C2=A0 =C2=A0 =C2=A0for (i =3D 0; i < s->timer_count; i++) {
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0sysbus_init_irq(sbd, &s->timer[i].= irq);
=C2=A0 =C2=A0 =C2=A0}
=C2=A0 =C2=A0 =C2=A0memory_region_init_io(&s->iomem, OBJECT(s), &= ;a10_pit_ops, s,

I am curious how to su= pport the different WDOG0 registers for the Allwinner H3 while keeping
the A10 functionality also working :-) Will you give the TYPE_AW_H3_P= IT=C2=A0 its own MemoryRegionOps with read/write?
=C2=A0
-=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 TYPE_AW_A10_PIT, 0x400);
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 TYPE_AW_A10_PIT, c->region_size);
=C2=A0 =C2=A0 =C2=A0sysbus_init_mmio(sbd, &s->iomem);

=C2=A0 =C2=A0 =C2=A0for (i =3D 0; i < s->timer_count; i++) {
@@ -328,26 +343,45 @@ static void a10_pit_init(Object *obj)
=C2=A0 =C2=A0 =C2=A0}
=C2=A0}

-static void a10_pit_class_init(ObjectClass *klass, void *data)
+static void aw_timer_class_init(ObjectClass *klass, void *data)
=C2=A0{
=C2=A0 =C2=A0 =C2=A0DeviceClass *dc =3D DEVICE_CLASS(klass);

=C2=A0 =C2=A0 =C2=A0dc->reset =3D a10_pit_reset;
=C2=A0 =C2=A0 =C2=A0dc->props =3D a10_pit_properties;
-=C2=A0 =C2=A0 dc->desc =3D "allwinner a10 timer";
+=C2=A0 =C2=A0 dc->desc =3D "Allwinner Timer Controller";
=C2=A0 =C2=A0 =C2=A0dc->vmsd =3D &vmstate_a10_pit;
=C2=A0}

+static const TypeInfo allwinner_pit_info =3D {
+=C2=A0 =C2=A0 .name =3D TYPE_AW_COMMON_PIT,
+=C2=A0 =C2=A0 .parent =3D TYPE_SYS_BUS_DEVICE,
+=C2=A0 =C2=A0 .instance_init =3D aw_pit_instance_init,
+=C2=A0 =C2=A0 .instance_size =3D sizeof(AllwinnerTmrCtrlState),
+=C2=A0 =C2=A0 .class_init =3D aw_timer_class_init,
+=C2=A0 =C2=A0 .class_size =3D sizeof(AllwinnerTmrCtrlClass),
+=C2=A0 =C2=A0 .abstract=C2=A0 =C2=A0=3D true,
+};
+
+static void a10_pit_class_init(ObjectClass *klass, void *data)
+{
+=C2=A0 =C2=A0 DeviceClass *dc =3D DEVICE_CLASS(klass);
+=C2=A0 =C2=A0 AllwinnerTmrCtrlClass *atc =3D AW_TIMER_CLASS(klass);
+
+=C2=A0 =C2=A0 dc->desc =3D "Allwinner A10 Timer Controller";<= br> +=C2=A0 =C2=A0 atc->timer_count =3D AW_A10_PIT_TIMER_NR;
+=C2=A0 =C2=A0 atc->region_size =3D 0x400;
+}
+
=C2=A0static const TypeInfo a10_pit_info =3D {
=C2=A0 =C2=A0 =C2=A0.name =3D TYPE_AW_A10_PIT,
-=C2=A0 =C2=A0 .parent =3D TYPE_SYS_BUS_DEVICE,
-=C2=A0 =C2=A0 .instance_size =3D sizeof(AllwinnerTmrCtrlState),
-=C2=A0 =C2=A0 .instance_init =3D a10_pit_init,
+=C2=A0 =C2=A0 .parent =3D TYPE_AW_COMMON_PIT,
=C2=A0 =C2=A0 =C2=A0.class_init =3D a10_pit_class_init,
=C2=A0};

=C2=A0static void a10_register_types(void)
=C2=A0{
+=C2=A0 =C2=A0 type_register_static(&allwinner_pit_info);
=C2=A0 =C2=A0 =C2=A0type_register_static(&a10_pit_info);
=C2=A0}

--
2.21.0



--
Niek Linnenbank

--00000000000006aff2059a291ebc-- From MAILER-DAEMON Fri Dec 20 16:19:51 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1iiPgd-0000Y1-Dn for mharc-qemu-arm@gnu.org; Fri, 20 Dec 2019 16:19:51 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:46601) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iiPga-0000Rw-D8 for qemu-arm@nongnu.org; Fri, 20 Dec 2019 16:19:49 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1iiPgZ-0006OK-3C for qemu-arm@nongnu.org; Fri, 20 Dec 2019 16:19:48 -0500 Received: from mail-io1-xd44.google.com ([2607:f8b0:4864:20::d44]:36143) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1iiPgW-000633-0p; Fri, 20 Dec 2019 16:19:44 -0500 Received: by mail-io1-xd44.google.com with SMTP id r13so723292ioa.3; Fri, 20 Dec 2019 13:19:43 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=wvK5100t3Ru3PwlfUk2/v4Xei+KIXGvop7OqFB75Hek=; b=URm1iCJyy1LNBjRcjhwN9rXbzIegcj60MtDPxNz3Nl5fYc0icXOzRNkGfxGkPbU7+H KXgj98ZdmP/JZ1ureuzK+XTKoZ/qu7/8/VTw9BMOTrfUmZjQTFsUHUxrZHFFWQxar7JT IUID/vyyduOqaVLorokkuRje+uubkegQvz4B9cKhXvPVmzXS97+XSRFy1WH82Zmya2hy 3koqiapc/vqoFC18cxwxEH+YhStyvOxWfb3pLivsp2iVRaowtmLcaArTbdo0g8k1gGvM uoQRYb3wYJFsVyBnnKZzusWfbKPLhQsEdGXtcTep9ctTjYI/VpSPwbtXFFmOlfQVFSwF D1Rg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=wvK5100t3Ru3PwlfUk2/v4Xei+KIXGvop7OqFB75Hek=; b=h/dawX8OZGW8w64zwhx+ykrh3d5bKmJv80e7+YnUxmaIPUob9cNcfOq0Jg9+qFoKg6 FAjXDc8lSgFDPK8JHe0CWHgqJb4n5O9wlgOZirrNDSot2a9SggFiEDWORdd9lSC0DBaY C6UrJBukwOTso9efN4UVKH1H7Wg5xOKVSzgjnHHha2yUhIfpKQgcON7IMYoUZrZ7wH3A Ew3l9MYJIEEywxIYOsqsoJoeXm+eq771ImwH2362cGvmDkUXj9DkbyzQiYjqbF7ktCGj JsLDIjF9bkEjK+WeZX+2ET3ZhcG2DPyEMHAA4ijIXS0wLekCongu6gfJZW3tL+jVVKHQ 88bA== X-Gm-Message-State: APjAAAWPhx7BHU6BNtC1831R7OXh0hwQO+eEfCnWWTNB6XyclwHT1dDH v9H4RtGv64zvWNF6HgcE1JoCOPwSza+9pS7oxlI= X-Google-Smtp-Source: APXvYqzi54ej9Aw+JJeM+h/Mfc57Z57Hfdgo/4amgnk8MvJI+JVnT+d7eMmYiTrTnzlXBV7DGfjmLBstTPK9hNnZRDg= X-Received: by 2002:a02:856a:: with SMTP id g97mr13625535jai.97.1576876783067; Fri, 20 Dec 2019 13:19:43 -0800 (PST) MIME-Version: 1.0 References: <20191219185127.24388-1-f4bug@amsat.org> <20191219185127.24388-2-f4bug@amsat.org> In-Reply-To: <20191219185127.24388-2-f4bug@amsat.org> From: Niek Linnenbank Date: Fri, 20 Dec 2019 22:19:31 +0100 Message-ID: Subject: Re: [PATCH 01/13] hw/timer/allwinner: Use the AW_A10_PIT_TIMER_NR definition To: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= Cc: QEMU Developers , Peter Maydell , Beniamino Galvani , qemu-arm Content-Type: multipart/alternative; boundary="0000000000008268b1059a293c14" X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::d44 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 20 Dec 2019 21:19:50 -0000 --0000000000008268b1059a293c14 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable On Thu, Dec 19, 2019 at 7:51 PM Philippe Mathieu-Daud=C3=A9 wrote: > We have a definition for this magic value '6', use it. > > Signed-off-by: Philippe Mathieu-Daud=C3=A9 > --- > include/hw/timer/allwinner-a10-pit.h | 2 +- > hw/timer/allwinner-a10-pit.c | 2 +- > 2 files changed, 2 insertions(+), 2 deletions(-) > > diff --git a/include/hw/timer/allwinner-a10-pit.h > b/include/hw/timer/allwinner-a10-pit.h > index 871c95b512..6aceda81ee 100644 > --- a/include/hw/timer/allwinner-a10-pit.h > +++ b/include/hw/timer/allwinner-a10-pit.h > @@ -32,7 +32,7 @@ > > #define AW_A10_PIT_TIMER_BASE 0x10 > #define AW_A10_PIT_TIMER_BASE_END \ > - (AW_A10_PIT_TIMER_BASE * 6 + AW_A10_PIT_TIMER_COUNT) > + (AW_A10_PIT_TIMER_BASE * AW_A10_PIT_TIMER_NR + AW_A10_PIT_TIMER_COUN= T) > > #define AW_A10_PIT_DEFAULT_CLOCK 0x4 > > diff --git a/hw/timer/allwinner-a10-pit.c b/hw/timer/allwinner-a10-pit.c > index aae880f5b3..117e5c7bf8 100644 > --- a/hw/timer/allwinner-a10-pit.c > +++ b/hw/timer/allwinner-a10-pit.c > @@ -225,7 +225,7 @@ static void a10_pit_reset(DeviceState *dev) > s->irq_status =3D 0; > a10_pit_update_irq(s); > > - for (i =3D 0; i < 6; i++) { > + for (i =3D 0; i < AW_A10_PIT_TIMER_NR; i++) { > s->control[i] =3D AW_A10_PIT_DEFAULT_CLOCK; > s->interval[i] =3D 0; > s->count[i] =3D 0; > -- > 2.21.0 > > Change looks fine to me: Reviewed-by: Niek Linnenbank Works fine with -M orangepi-pc and -M cubieboard: Tested-by: Niek Linnenbank --=20 Niek Linnenbank --0000000000008268b1059a293c14 Content-Type: text/html; charset="UTF-8" Content-Transfer-Encoding: quoted-printable


=
On Thu, Dec 19, 2019 at 7:51 PM Phili= ppe Mathieu-Daud=C3=A9 <f4bug@amsat.o= rg> wrote:
f4bug@amsat.org>
---
=C2=A0include/hw/timer/allwinner-a10-pit.h | 2 +-
=C2=A0hw/timer/allwinner-a10-pit.c=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0| 2 +-<= br> =C2=A02 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/include/hw/timer/allwinner-a10-pit.h b/include/hw/timer/allwin= ner-a10-pit.h
index 871c95b512..6aceda81ee 100644
--- a/include/hw/timer/allwinner-a10-pit.h
+++ b/include/hw/timer/allwinner-a10-pit.h
@@ -32,7 +32,7 @@

=C2=A0#define AW_A10_PIT_TIMER_BASE=C2=A0 =C2=A0 =C2=A0 0x10
=C2=A0#define AW_A10_PIT_TIMER_BASE_END=C2=A0 \
-=C2=A0 =C2=A0 (AW_A10_PIT_TIMER_BASE * 6 + AW_A10_PIT_TIMER_COUNT)
+=C2=A0 =C2=A0 (AW_A10_PIT_TIMER_BASE * AW_A10_PIT_TIMER_NR + AW_A10_PIT_TI= MER_COUNT)

=C2=A0#define AW_A10_PIT_DEFAULT_CLOCK=C2=A0 =C2=A00x4

diff --git a/hw/timer/allwinner-a10-pit.c b/hw/timer/allwinner-a10-pit.c index aae880f5b3..117e5c7bf8 100644
--- a/hw/timer/allwinner-a10-pit.c
+++ b/hw/timer/allwinner-a10-pit.c
@@ -225,7 +225,7 @@ static void a10_pit_reset(DeviceState *dev)
=C2=A0 =C2=A0 =C2=A0s->irq_status =3D 0;
=C2=A0 =C2=A0 =C2=A0a10_pit_update_irq(s);

-=C2=A0 =C2=A0 for (i =3D 0; i < 6; i++) {
+=C2=A0 =C2=A0 for (i =3D 0; i < AW_A10_PIT_TIMER_NR; i++) {
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0s->control[i] =3D AW_A10_PIT_DEFAULT_C= LOCK;
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0s->interval[i] =3D 0;
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0s->count[i] =3D 0;
--
2.21.0

Change looks fine to me:
=C2=A0 Reviewed-by= : Niek Linnenbank <nieklinne= nbank@gmail.com>

Works fine with -M ora= ngepi-pc and -M cubieboard:
=C2=A0 Tested-by: Niek Linnenbank <= ;nieklinnenbank@gmail.com&g= t;
=C2=A0


--
Niek Linnenbank
--0000000000008268b1059a293c14-- From MAILER-DAEMON Fri Dec 20 16:28:05 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1iiPob-0000Wg-3k for mharc-qemu-arm@gnu.org; Fri, 20 Dec 2019 16:28:05 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:56273) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iiPoW-0000PO-V4 for qemu-arm@nongnu.org; Fri, 20 Dec 2019 16:28:02 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1iiPoU-0007jI-Ce for qemu-arm@nongnu.org; Fri, 20 Dec 2019 16:27:59 -0500 Received: from mail-il1-x141.google.com ([2607:f8b0:4864:20::141]:38848) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1iiPoQ-0007KG-QL; Fri, 20 Dec 2019 16:27:55 -0500 Received: by mail-il1-x141.google.com with SMTP id f5so9154478ilq.5; Fri, 20 Dec 2019 13:27:53 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=5FKcFFoz/FT1jFBsPVyN5pMqwGAlqiO1LFE+/xNc0UA=; b=tBktb9Te0Cy0czwH6xaDZSPAhCAn/X4Zs1txiJTvo4H8qMFHdXeqlS0X5CXF4xxEBJ jMdnWc2p6fbFF8F+DalqECCNQ1VtzFCMX/cMU27dOqukNHgxICoF9/ZT7+0vIwZ1BOD7 fhgKi+efaZKodH24LZYhKmfK2LvD67Y8DpIALoOjrtf39jye9I9jQsH+z6OJd6plpZRb lHvlnrlifIBJN7NgbOc6ibIukpRQJpqgMwx7BrjmFa7o82La30FCIKVdjVuDOMJADK53 lUyzVYK/eLIfIWvRgXeaP+AUwd7twibcFilwnJk641IGZxztkJ2MOqeLnXD/LQJJwR7P 4X5w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=5FKcFFoz/FT1jFBsPVyN5pMqwGAlqiO1LFE+/xNc0UA=; b=sOcGJpKQWROR0Edr1y+V0vdcuaQh902pq8jZlXShzHuhBMPzi3fZtEWCfQehpbmUvM jXpHSoTDoWyGUkGofhRe7tGqK2CGCEfKbO1wfrbZnSJY5MHTFEEVFQO/6zd6Q6mq4Tk5 T7ZsJmjivvXo76vhJpv2pl9Ild0Yl/FJ8fUZ+xxdIYMm9/MaA6qKPxQ5vG9N8v4d+oA5 zN0qWpNkKVPGm51d1nrqusMbtK8WnalYr/cAXzBYv7uldec0y98iqnAvxisOTrIF0U6z qQlmQyNH74hPA4z08JHDRZSyRqCQs4fMmG99dQ6augwU72ANsMOobOgdD4zgrc84MeRe bU1g== X-Gm-Message-State: APjAAAX2pKhXFIn5s8NDnghYB8Z+GSIPzkExaHaqHDgj8R7xYY4cwVGv Y+9ZyCqrbFPd9E8rmE5G9ZtAYXuR7t9G4dNo92s= X-Google-Smtp-Source: APXvYqwUikgHVtfEuW+pvMNsJ8zEV6yAAGNu4df6ofkReXjKvvhSrjr1rG+mJZPBkxAiC1n5wT6HmFHjpgD5S98wKlI= X-Received: by 2002:a92:5a45:: with SMTP id o66mr13722170ilb.67.1576877272941; Fri, 20 Dec 2019 13:27:52 -0800 (PST) MIME-Version: 1.0 References: <20191219185127.24388-1-f4bug@amsat.org> <20191219185127.24388-3-f4bug@amsat.org> In-Reply-To: <20191219185127.24388-3-f4bug@amsat.org> From: Niek Linnenbank Date: Fri, 20 Dec 2019 22:27:41 +0100 Message-ID: Subject: Re: [PATCH 02/13] hw/timer/allwinner: Add AW_PIT_TIMER_MAX definition To: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= Cc: QEMU Developers , Peter Maydell , Beniamino Galvani , qemu-arm Content-Type: multipart/alternative; boundary="000000000000b54b3e059a2959eb" X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::141 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 20 Dec 2019 21:28:03 -0000 --000000000000b54b3e059a2959eb Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable On Thu, Dec 19, 2019 at 7:51 PM Philippe Mathieu-Daud=C3=A9 wrote: > This controller is able to use up to 6 timers. > Later we will reuse part of it to model other similar controllers > but with less timers. To simplify the VMSTATE, we'll keep a max > of 6 timers. Add a definition for that value. > > Signed-off-by: Philippe Mathieu-Daud=C3=A9 > --- > include/hw/timer/allwinner-a10-pit.h | 14 ++++++++------ > hw/timer/allwinner-a10-pit.c | 8 ++++---- > 2 files changed, 12 insertions(+), 10 deletions(-) > > diff --git a/include/hw/timer/allwinner-a10-pit.h > b/include/hw/timer/allwinner-a10-pit.h > index 6aceda81ee..54c40c7db6 100644 > --- a/include/hw/timer/allwinner-a10-pit.h > +++ b/include/hw/timer/allwinner-a10-pit.h > @@ -7,6 +7,8 @@ > #define TYPE_AW_A10_PIT "allwinner-A10-timer" > #define AW_A10_PIT(obj) OBJECT_CHECK(AwA10PITState, (obj), > TYPE_AW_A10_PIT) > > +#define AW_PIT_TIMER_MAX 6 > + > #define AW_A10_PIT_TIMER_NR 6 > #define AW_A10_PIT_TIMER_IRQ 0x1 > #define AW_A10_PIT_WDOG_IRQ 0x100 > @@ -47,17 +49,17 @@ struct AwA10PITState { > /*< private >*/ > SysBusDevice parent_obj; > /*< public >*/ > - qemu_irq irq[AW_A10_PIT_TIMER_NR]; > - ptimer_state * timer[AW_A10_PIT_TIMER_NR]; > - AwA10TimerContext timer_context[AW_A10_PIT_TIMER_NR]; > + qemu_irq irq[AW_PIT_TIMER_MAX]; > + ptimer_state * timer[AW_PIT_TIMER_MAX]; > + AwA10TimerContext timer_context[AW_PIT_TIMER_MAX]; > MemoryRegion iomem; > uint32_t clk_freq[4]; > > uint32_t irq_enable; > uint32_t irq_status; > - uint32_t control[AW_A10_PIT_TIMER_NR]; > - uint32_t interval[AW_A10_PIT_TIMER_NR]; > - uint32_t count[AW_A10_PIT_TIMER_NR]; > + uint32_t control[AW_PIT_TIMER_MAX]; > + uint32_t interval[AW_PIT_TIMER_MAX]; > + uint32_t count[AW_PIT_TIMER_MAX]; > uint32_t watch_dog_mode; > uint32_t watch_dog_control; > uint32_t count_lo; > diff --git a/hw/timer/allwinner-a10-pit.c b/hw/timer/allwinner-a10-pit.c > index 117e5c7bf8..b31a0bcd43 100644 > --- a/hw/timer/allwinner-a10-pit.c > +++ b/hw/timer/allwinner-a10-pit.c > @@ -203,15 +203,15 @@ static const VMStateDescription vmstate_a10_pit =3D= { > .fields =3D (VMStateField[]) { > VMSTATE_UINT32(irq_enable, AwA10PITState), > VMSTATE_UINT32(irq_status, AwA10PITState), > - VMSTATE_UINT32_ARRAY(control, AwA10PITState, AW_A10_PIT_TIMER_NR= ), > - VMSTATE_UINT32_ARRAY(interval, AwA10PITState, > AW_A10_PIT_TIMER_NR), > - VMSTATE_UINT32_ARRAY(count, AwA10PITState, AW_A10_PIT_TIMER_NR), > + VMSTATE_UINT32_ARRAY(control, AwA10PITState, AW_PIT_TIMER_MAX), > + VMSTATE_UINT32_ARRAY(interval, AwA10PITState, AW_PIT_TIMER_MAX), > + VMSTATE_UINT32_ARRAY(count, AwA10PITState, AW_PIT_TIMER_MAX), > VMSTATE_UINT32(watch_dog_mode, AwA10PITState), > VMSTATE_UINT32(watch_dog_control, AwA10PITState), > VMSTATE_UINT32(count_lo, AwA10PITState), > VMSTATE_UINT32(count_hi, AwA10PITState), > VMSTATE_UINT32(count_ctl, AwA10PITState), > - VMSTATE_PTIMER_ARRAY(timer, AwA10PITState, AW_A10_PIT_TIMER_NR), > + VMSTATE_PTIMER_ARRAY(timer, AwA10PITState, AW_PIT_TIMER_MAX), > VMSTATE_END_OF_LIST() > } > }; > -- > 2.21.0 > > Looks good and works fine with -M orangepi-pc and -M cubieboard. Reviewed-by: Niek Linnenbank Tested-by: Niek Linnenbank --=20 Niek Linnenbank --000000000000b54b3e059a2959eb Content-Type: text/html; charset="UTF-8" Content-Transfer-Encoding: quoted-printable


=
On Thu, Dec 19, 2019 at 7:51 PM Phili= ppe Mathieu-Daud=C3=A9 <f4bug@amsat.o= rg> wrote:
f4bug@amsat.org>
---
=C2=A0include/hw/timer/allwinner-a10-pit.h | 14 ++++++++------
=C2=A0hw/timer/allwinner-a10-pit.c=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0|=C2=A0= 8 ++++----
=C2=A02 files changed, 12 insertions(+), 10 deletions(-)

diff --git a/include/hw/timer/allwinner-a10-pit.h b/include/hw/timer/allwin= ner-a10-pit.h
index 6aceda81ee..54c40c7db6 100644
--- a/include/hw/timer/allwinner-a10-pit.h
+++ b/include/hw/timer/allwinner-a10-pit.h
@@ -7,6 +7,8 @@
=C2=A0#define TYPE_AW_A10_PIT "allwinner-A10-timer"
=C2=A0#define AW_A10_PIT(obj) OBJECT_CHECK(AwA10PITState, (obj), TYPE_AW_A1= 0_PIT)

+#define AW_PIT_TIMER_MAX=C2=A0 =C2=A0 =C2=A0 =C2=A0 6
+
=C2=A0#define AW_A10_PIT_TIMER_NR=C2=A0 =C2=A0 6
=C2=A0#define AW_A10_PIT_TIMER_IRQ=C2=A0 =C2=A00x1
=C2=A0#define AW_A10_PIT_WDOG_IRQ=C2=A0 =C2=A0 0x100
@@ -47,17 +49,17 @@ struct AwA10PITState {
=C2=A0 =C2=A0 =C2=A0/*< private >*/
=C2=A0 =C2=A0 =C2=A0SysBusDevice parent_obj;
=C2=A0 =C2=A0 =C2=A0/*< public >*/
-=C2=A0 =C2=A0 qemu_irq irq[AW_A10_PIT_TIMER_NR];
-=C2=A0 =C2=A0 ptimer_state * timer[AW_A10_PIT_TIMER_NR];
-=C2=A0 =C2=A0 AwA10TimerContext timer_context[AW_A10_PIT_TIMER_NR];
+=C2=A0 =C2=A0 qemu_irq irq[AW_PIT_TIMER_MAX];
+=C2=A0 =C2=A0 ptimer_state * timer[AW_PIT_TIMER_MAX];
+=C2=A0 =C2=A0 AwA10TimerContext timer_context[AW_PIT_TIMER_MAX];
=C2=A0 =C2=A0 =C2=A0MemoryRegion iomem;
=C2=A0 =C2=A0 =C2=A0uint32_t clk_freq[4];

=C2=A0 =C2=A0 =C2=A0uint32_t irq_enable;
=C2=A0 =C2=A0 =C2=A0uint32_t irq_status;
-=C2=A0 =C2=A0 uint32_t control[AW_A10_PIT_TIMER_NR];
-=C2=A0 =C2=A0 uint32_t interval[AW_A10_PIT_TIMER_NR];
-=C2=A0 =C2=A0 uint32_t count[AW_A10_PIT_TIMER_NR];
+=C2=A0 =C2=A0 uint32_t control[AW_PIT_TIMER_MAX];
+=C2=A0 =C2=A0 uint32_t interval[AW_PIT_TIMER_MAX];
+=C2=A0 =C2=A0 uint32_t count[AW_PIT_TIMER_MAX];
=C2=A0 =C2=A0 =C2=A0uint32_t watch_dog_mode;
=C2=A0 =C2=A0 =C2=A0uint32_t watch_dog_control;
=C2=A0 =C2=A0 =C2=A0uint32_t count_lo;
diff --git a/hw/timer/allwinner-a10-pit.c b/hw/timer/allwinner-a10-pit.c index 117e5c7bf8..b31a0bcd43 100644
--- a/hw/timer/allwinner-a10-pit.c
+++ b/hw/timer/allwinner-a10-pit.c
@@ -203,15 +203,15 @@ static const VMStateDescription vmstate_a10_pit =3D {=
=C2=A0 =C2=A0 =C2=A0.fields =3D (VMStateField[]) {
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0VMSTATE_UINT32(irq_enable, AwA10PITState)= ,
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0VMSTATE_UINT32(irq_status, AwA10PITState)= ,
-=C2=A0 =C2=A0 =C2=A0 =C2=A0 VMSTATE_UINT32_ARRAY(control, AwA10PITState, A= W_A10_PIT_TIMER_NR),
-=C2=A0 =C2=A0 =C2=A0 =C2=A0 VMSTATE_UINT32_ARRAY(interval, AwA10PITState, = AW_A10_PIT_TIMER_NR),
-=C2=A0 =C2=A0 =C2=A0 =C2=A0 VMSTATE_UINT32_ARRAY(count, AwA10PITState, AW_= A10_PIT_TIMER_NR),
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 VMSTATE_UINT32_ARRAY(control, AwA10PITState, A= W_PIT_TIMER_MAX),
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 VMSTATE_UINT32_ARRAY(interval, AwA10PITState, = AW_PIT_TIMER_MAX),
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 VMSTATE_UINT32_ARRAY(count, AwA10PITState, AW_= PIT_TIMER_MAX),
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0VMSTATE_UINT32(watch_dog_mode, AwA10PITSt= ate),
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0VMSTATE_UINT32(watch_dog_control, AwA10PI= TState),
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0VMSTATE_UINT32(count_lo, AwA10PITState),<= br> =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0VMSTATE_UINT32(count_hi, AwA10PITState),<= br> =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0VMSTATE_UINT32(count_ctl, AwA10PITState),=
-=C2=A0 =C2=A0 =C2=A0 =C2=A0 VMSTATE_PTIMER_ARRAY(timer, AwA10PITState, AW_= A10_PIT_TIMER_NR),
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 VMSTATE_PTIMER_ARRAY(timer, AwA10PITState, AW_= PIT_TIMER_MAX),
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0VMSTATE_END_OF_LIST()
=C2=A0 =C2=A0 =C2=A0}
=C2=A0};
--
2.21.0

Looks good and works fine with -M orangepi-pc and -= M cubieboard.

Reviewed-by: Niek Linnenbank <nieklinnenbank@gmail.com>
Tested-by: Niek Linnenbank <nieklinnenbank@gmail.com>


--
Niek Lin= nenbank

--000000000000b54b3e059a2959eb-- From MAILER-DAEMON Fri Dec 20 16:36:54 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1iiPx8-0006mM-C9 for mharc-qemu-arm@gnu.org; Fri, 20 Dec 2019 16:36:54 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:38935) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iiPx5-0006kj-JB for qemu-arm@nongnu.org; Fri, 20 Dec 2019 16:36:52 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1iiPx4-0000hb-B0 for qemu-arm@nongnu.org; Fri, 20 Dec 2019 16:36:51 -0500 Received: from mail-il1-x144.google.com ([2607:f8b0:4864:20::144]:33708) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1iiPx1-0000Sf-MH; Fri, 20 Dec 2019 16:36:47 -0500 Received: by mail-il1-x144.google.com with SMTP id v15so9189604iln.0; Fri, 20 Dec 2019 13:36:43 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=qaNduU8pI7n8V/CKKVcoUQRc3In0xX5bjD7Gmv/Y+hc=; b=ts5KbL8gyyQ/p5//AlI3tqSjROTPVziRDg2LpRLvJ0cF/ZZ/YsEInO9QpS3Y8gSZWT MSFrM7ic5tyXr/Zh2K36PRr1ZXbSrKkxeJOymhVuARIIFCLwi3lyJNV2M5pvkfzti9Jx 6W1OOthh5u6HCUqFfnRdAbO30u5L5PkE3mkiGj/r+Bvn/RMeHtkZg9rDa2QCBH6Uc/eV jELaXUCnrxmKglNhFV4TwL+alSTV0XW9sdWNmxIxQiTWLuwSoogZ6qQhKX74iZ9lCtpa FTHkWcN/lIIavRhoznr/xYl9qOCZ0zHw4Dvouo9SGkFlcIFMTdxplym3H1HM/fDymVFD Y4cw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=qaNduU8pI7n8V/CKKVcoUQRc3In0xX5bjD7Gmv/Y+hc=; b=sDK0gy5tpFiL1TacigLwHVfrEnDIe4Dyge2kmye1Us0vzMNrCpeXsf76z0jGxcJSfN jS4+tPWM74fUgRnlRfoe0QSrDQ33U6HMKiy8iOxqCb2DpzmnaluN8e4QHkqyUNnWkhWw Fq10wIEZmHYNwRgE2nxzIL2Uz2FcwzcXRnJNj+KETeOFjz3CA0yqF+nZ/hPV0y344DLB hXzZcXiVBcNt239zQ+VigA13XR7ZFbx05PMOTJ7anDJNQGT0ESGpy5WWyy9gNkZdggfm 9eS7BLuiv9DkrWLzcXisJMHtRCZ5FgOJknWKJEd3fRwxFbFZ3IexqMxGMVDaIIHoc34G LWDg== X-Gm-Message-State: APjAAAUwt/pm0VS17Duqn5QZtXw5J7rf3xsxB9rcb99fB9MBvas1iFGL CljQsJ8HCdmjSVJTg3kRzlFaziUWTH0XoWtpgBQ= X-Google-Smtp-Source: APXvYqy0ejjKb+evxfxYiekibHgX3aK03HXa1usu+LcJM6GlM32fOk4eGuolB2K98JotFfFJJ9oOPHwDaKsmczJP8Bs= X-Received: by 2002:a92:af08:: with SMTP id n8mr13914978ili.217.1576877803146; Fri, 20 Dec 2019 13:36:43 -0800 (PST) MIME-Version: 1.0 References: <20191219185127.24388-1-f4bug@amsat.org> <20191219185127.24388-4-f4bug@amsat.org> In-Reply-To: <20191219185127.24388-4-f4bug@amsat.org> From: Niek Linnenbank Date: Fri, 20 Dec 2019 22:36:32 +0100 Message-ID: Subject: Re: [PATCH 03/13] hw/timer/allwinner: Remove unused definitions To: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= Cc: QEMU Developers , Peter Maydell , Beniamino Galvani , qemu-arm Content-Type: multipart/alternative; boundary="0000000000004f9359059a297968" X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::144 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 20 Dec 2019 21:36:52 -0000 --0000000000004f9359059a297968 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable On Thu, Dec 19, 2019 at 7:51 PM Philippe Mathieu-Daud=C3=A9 wrote: > Keeping unused definition is rather confusing when reviewing. > Remove them. > Perhaps make it more clear that the definitions are unused IRQ defines? > > Signed-off-by: Philippe Mathieu-Daud=C3=A9 > --- > include/hw/timer/allwinner-a10-pit.h | 2 -- > 1 file changed, 2 deletions(-) > > diff --git a/include/hw/timer/allwinner-a10-pit.h > b/include/hw/timer/allwinner-a10-pit.h > index 54c40c7db6..e4a644add9 100644 > --- a/include/hw/timer/allwinner-a10-pit.h > +++ b/include/hw/timer/allwinner-a10-pit.h > @@ -10,8 +10,6 @@ > #define AW_PIT_TIMER_MAX 6 > > #define AW_A10_PIT_TIMER_NR 6 > -#define AW_A10_PIT_TIMER_IRQ 0x1 > -#define AW_A10_PIT_WDOG_IRQ 0x100 > > #define AW_A10_PIT_TIMER_IRQ_EN 0 > #define AW_A10_PIT_TIMER_IRQ_ST 0x4 > -- > 2.21.0 > > Reviewed-by: Niek Linnenbank Tested-by: Niek Linnenbank --=20 Niek Linnenbank --0000000000004f9359059a297968 Content-Type: text/html; charset="UTF-8" Content-Transfer-Encoding: quoted-printable


=
On Thu, Dec 19, 2019 at 7:51 PM Phili= ppe Mathieu-Daud=C3=A9 <f4bug@amsat.o= rg> wrote:

Signed-off-by: Philippe Mathieu-Daud=C3=A9 <f4bug@amsat.org>
---
=C2=A0include/hw/timer/allwinner-a10-pit.h | 2 --
=C2=A01 file changed, 2 deletions(-)

diff --git a/include/hw/timer/allwinner-a10-pit.h b/include/hw/timer/allwin= ner-a10-pit.h
index 54c40c7db6..e4a644add9 100644
--- a/include/hw/timer/allwinner-a10-pit.h
+++ b/include/hw/timer/allwinner-a10-pit.h
@@ -10,8 +10,6 @@
=C2=A0#define AW_PIT_TIMER_MAX=C2=A0 =C2=A0 =C2=A0 =C2=A0 6

=C2=A0#define AW_A10_PIT_TIMER_NR=C2=A0 =C2=A0 6
-#define AW_A10_PIT_TIMER_IRQ=C2=A0 =C2=A00x1
-#define AW_A10_PIT_WDOG_IRQ=C2=A0 =C2=A0 0x100

=C2=A0#define AW_A10_PIT_TIMER_IRQ_EN=C2=A0 =C2=A0 0
=C2=A0#define AW_A10_PIT_TIMER_IRQ_ST=C2=A0 =C2=A0 0x4
--
2.21.0

Reviewed-by: Niek Linnenbank <nieklinnenbank@gmail.com>
Tested-b= y: Niek Linnenbank <nieklinn= enbank@gmail.com>


--
Niek Linnenbank<= br>
--0000000000004f9359059a297968-- From MAILER-DAEMON Fri Dec 20 16:41:34 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1iiQ1d-0000wT-Nv for mharc-qemu-arm@gnu.org; Fri, 20 Dec 2019 16:41:34 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:46931) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iiQ1a-0000uT-GG for qemu-arm@nongnu.org; Fri, 20 Dec 2019 16:41:31 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1iiQ1Y-0000y5-Kl for qemu-arm@nongnu.org; Fri, 20 Dec 2019 16:41:30 -0500 Received: from mail-il1-x142.google.com ([2607:f8b0:4864:20::142]:34966) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1iiQ1U-0000ht-7d; Fri, 20 Dec 2019 16:41:24 -0500 Received: by mail-il1-x142.google.com with SMTP id g12so9200578ild.2; Fri, 20 Dec 2019 13:41:24 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=VtAkNhpFNr5u4e9iNM3vzKqzfaaIUqBY0YwX3FjL5BU=; b=PfN3MXIn0z5Yc1TBM+3+QBtfIdPRRDO64ligJREStb4AaqhatrSqTImziSM+WYVzE/ J62ebPPCUQx3B41n25SH0SAEX+C59gI5MDI/31apjjK1rudCjG5Zf5mtUxUX1BUSE5LV W8gTjxT7aGk/L9EdzE4BwIOu6+UCADisAUDS/rrXvFBaSoMP6uNAarDqmP0Ojz58TFmu mhqcMI2+lOEXcB6aZpdj6rjKpAXDGbbKDQ7aRH6E9H91pSK6Xelr90hmKdrtHceP1FWS FOTTAPpcxc15bn4LNwycua9bBuTlsA0H+wT0hM/BkhgqhFPTwTJT6k6lz94RW4zCozSw E/2g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=VtAkNhpFNr5u4e9iNM3vzKqzfaaIUqBY0YwX3FjL5BU=; b=G2qUB470vTwNbqt14rshBVM+KPGmgToc5lLQQR2NIy46kG4CSAB/LoNsByxG0wt7vr RhuRzkHyYf5Yx3tQ0uGn3SQBnuoilvpLXyhUZKEeO3kmqcf6WmmadYnFM8WYVBs242H4 db59bhKCemdwoaxZwZvGGkFPPlyFFZpEiFzl1uNZDkfvfrp65IjA2TZA1ma6dcdypazv Fk0LNV3e1HnJ04fj/0tHnU9eYddygaiMF7do4rSTS8oAaM40JMryOTzyiwCPVjfaCGcq 2iL0o76plhdq03A9YpR+xyoH8SoMbDaNzubUhn2ZR7gykHRAF1xpq4EQjmF8XijJ0A2t niKA== X-Gm-Message-State: APjAAAW7AaSYciG1Pc6sijFT8v2JiAGJPvpIkEXUdm73wIU3Ka6FscHE cIirf5LYIuSG4JQjNbPVYocgpXiQY7xRYtEUcW4= X-Google-Smtp-Source: APXvYqw6SqoUT02xxtVUGNHoDjlzuZ8yfYjIe2K6IGSMAaqB74Twn/qJqchKHgQ2XXLJljRbH/fkrPAkVWGTX8ktmjc= X-Received: by 2002:a92:d5cf:: with SMTP id d15mr13820251ilq.306.1576878083021; Fri, 20 Dec 2019 13:41:23 -0800 (PST) MIME-Version: 1.0 References: <20191219185127.24388-1-f4bug@amsat.org> <20191219185127.24388-5-f4bug@amsat.org> In-Reply-To: <20191219185127.24388-5-f4bug@amsat.org> From: Niek Linnenbank Date: Fri, 20 Dec 2019 22:41:12 +0100 Message-ID: Subject: Re: [PATCH 04/13] hw/timer/allwinner: Move definitions from header to source To: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= Cc: QEMU Developers , Peter Maydell , Beniamino Galvani , qemu-arm Content-Type: multipart/alternative; boundary="000000000000fe217a059a2989ed" X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::142 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 20 Dec 2019 21:41:32 -0000 --000000000000fe217a059a2989ed Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable On Thu, Dec 19, 2019 at 7:51 PM Philippe Mathieu-Daud=C3=A9 wrote: > These definitions are only used in the implementation, thus don't > need to be exported. Move them in the source file. > > Signed-off-by: Philippe Mathieu-Daud=C3=A9 > --- > include/hw/timer/allwinner-a10-pit.h | 28 -------------------------- > hw/timer/allwinner-a10-pit.c | 30 ++++++++++++++++++++++++++++ > 2 files changed, 30 insertions(+), 28 deletions(-) > > diff --git a/include/hw/timer/allwinner-a10-pit.h > b/include/hw/timer/allwinner-a10-pit.h > index e4a644add9..c28ee5ca47 100644 > --- a/include/hw/timer/allwinner-a10-pit.h > +++ b/include/hw/timer/allwinner-a10-pit.h > @@ -5,37 +5,9 @@ > #include "hw/sysbus.h" > > #define TYPE_AW_A10_PIT "allwinner-A10-timer" > -#define AW_A10_PIT(obj) OBJECT_CHECK(AwA10PITState, (obj), > TYPE_AW_A10_PIT) > > #define AW_PIT_TIMER_MAX 6 > > -#define AW_A10_PIT_TIMER_NR 6 > - > -#define AW_A10_PIT_TIMER_IRQ_EN 0 > -#define AW_A10_PIT_TIMER_IRQ_ST 0x4 > - > -#define AW_A10_PIT_TIMER_CONTROL 0x0 > -#define AW_A10_PIT_TIMER_EN 0x1 > -#define AW_A10_PIT_TIMER_RELOAD 0x2 > -#define AW_A10_PIT_TIMER_MODE 0x80 > - > -#define AW_A10_PIT_TIMER_INTERVAL 0x4 > -#define AW_A10_PIT_TIMER_COUNT 0x8 > -#define AW_A10_PIT_WDOG_CONTROL 0x90 > -#define AW_A10_PIT_WDOG_MODE 0x94 > - > -#define AW_A10_PIT_COUNT_CTL 0xa0 > -#define AW_A10_PIT_COUNT_RL_EN 0x2 > -#define AW_A10_PIT_COUNT_CLR_EN 0x1 > -#define AW_A10_PIT_COUNT_LO 0xa4 > -#define AW_A10_PIT_COUNT_HI 0xa8 > - > -#define AW_A10_PIT_TIMER_BASE 0x10 > -#define AW_A10_PIT_TIMER_BASE_END \ > - (AW_A10_PIT_TIMER_BASE * AW_A10_PIT_TIMER_NR + AW_A10_PIT_TIMER_COUN= T) > - > -#define AW_A10_PIT_DEFAULT_CLOCK 0x4 > - > typedef struct AwA10PITState AwA10PITState; > > typedef struct AwA10TimerContext { > diff --git a/hw/timer/allwinner-a10-pit.c b/hw/timer/allwinner-a10-pit.c > index b31a0bcd43..00f7cc492d 100644 > --- a/hw/timer/allwinner-a10-pit.c > +++ b/hw/timer/allwinner-a10-pit.c > @@ -24,6 +24,36 @@ > #include "qemu/log.h" > #include "qemu/module.h" > > +#define AW_A10_PIT_TIMER_NR 6 > + > +#define AW_A10_PIT_TIMER_IRQ_EN 0 > +#define AW_A10_PIT_TIMER_IRQ_ST 0x4 > + > +#define AW_A10_PIT_TIMER_CONTROL 0x0 > +#define AW_A10_PIT_TIMER_EN 0x1 > +#define AW_A10_PIT_TIMER_RELOAD 0x2 > +#define AW_A10_PIT_TIMER_MODE 0x80 > + > +#define AW_A10_PIT_TIMER_INTERVAL 0x4 > +#define AW_A10_PIT_TIMER_COUNT 0x8 > +#define AW_A10_PIT_WDOG_CONTROL 0x90 > +#define AW_A10_PIT_WDOG_MODE 0x94 > + > +#define AW_A10_PIT_COUNT_CTL 0xa0 > +#define AW_A10_PIT_COUNT_RL_EN 0x2 > +#define AW_A10_PIT_COUNT_CLR_EN 0x1 > +#define AW_A10_PIT_COUNT_LO 0xa4 > +#define AW_A10_PIT_COUNT_HI 0xa8 > + > +#define AW_A10_PIT_TIMER_BASE 0x10 > +#define AW_A10_PIT_TIMER_BASE_END \ > + (AW_A10_PIT_TIMER_BASE * AW_A10_PIT_TIMER_NR + AW_A10_PIT_TIMER_COUN= T) > + > +#define AW_A10_PIT_DEFAULT_CLOCK 0x4 > + > +#define AW_A10_PIT(obj) \ > + OBJECT_CHECK(AwA10PITState, (obj), TYPE_AW_A10_PIT) > + > static void a10_pit_update_irq(AwA10PITState *s) > { > int i; > -- > 2.21.0 > > Looks fine and tested on -M orangepi-pc, -M cubieboard: Tested-by: Niek Linnenbank Reviewed-by: Niek Linnenbank --=20 Niek Linnenbank --000000000000fe217a059a2989ed Content-Type: text/html; charset="UTF-8" Content-Transfer-Encoding: quoted-printable


=
On Thu, Dec 19, 2019 at 7:51 PM Phili= ppe Mathieu-Daud=C3=A9 <f4bug@amsat.o= rg> wrote:
f4bug@amsat.org>
---
=C2=A0include/hw/timer/allwinner-a10-pit.h | 28 --------------------------<= br> =C2=A0hw/timer/allwinner-a10-pit.c=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0| 30 ++= ++++++++++++++++++++++++++
=C2=A02 files changed, 30 insertions(+), 28 deletions(-)

diff --git a/include/hw/timer/allwinner-a10-pit.h b/include/hw/timer/allwin= ner-a10-pit.h
index e4a644add9..c28ee5ca47 100644
--- a/include/hw/timer/allwinner-a10-pit.h
+++ b/include/hw/timer/allwinner-a10-pit.h
@@ -5,37 +5,9 @@
=C2=A0#include "hw/sysbus.h"

=C2=A0#define TYPE_AW_A10_PIT "allwinner-A10-timer"
-#define AW_A10_PIT(obj) OBJECT_CHECK(AwA10PITState, (obj), TYPE_AW_A10_PIT= )

=C2=A0#define AW_PIT_TIMER_MAX=C2=A0 =C2=A0 =C2=A0 =C2=A0 6

-#define AW_A10_PIT_TIMER_NR=C2=A0 =C2=A0 6
-
-#define AW_A10_PIT_TIMER_IRQ_EN=C2=A0 =C2=A0 0
-#define AW_A10_PIT_TIMER_IRQ_ST=C2=A0 =C2=A0 0x4
-
-#define AW_A10_PIT_TIMER_CONTROL=C2=A0 =C2=A00x0
-#define AW_A10_PIT_TIMER_EN=C2=A0 =C2=A0 =C2=A0 =C2=A0 0x1
-#define AW_A10_PIT_TIMER_RELOAD=C2=A0 =C2=A0 0x2
-#define AW_A10_PIT_TIMER_MODE=C2=A0 =C2=A0 =C2=A0 0x80
-
-#define AW_A10_PIT_TIMER_INTERVAL=C2=A0 0x4
-#define AW_A10_PIT_TIMER_COUNT=C2=A0 =C2=A0 =C2=A00x8
-#define AW_A10_PIT_WDOG_CONTROL=C2=A0 =C2=A0 0x90
-#define AW_A10_PIT_WDOG_MODE=C2=A0 =C2=A0 =C2=A0 =C2=A00x94
-
-#define AW_A10_PIT_COUNT_CTL=C2=A0 =C2=A0 =C2=A0 =C2=A00xa0
-#define AW_A10_PIT_COUNT_RL_EN=C2=A0 =C2=A0 =C2=A00x2
-#define AW_A10_PIT_COUNT_CLR_EN=C2=A0 =C2=A0 0x1
-#define AW_A10_PIT_COUNT_LO=C2=A0 =C2=A0 =C2=A0 =C2=A0 0xa4
-#define AW_A10_PIT_COUNT_HI=C2=A0 =C2=A0 =C2=A0 =C2=A0 0xa8
-
-#define AW_A10_PIT_TIMER_BASE=C2=A0 =C2=A0 =C2=A0 0x10
-#define AW_A10_PIT_TIMER_BASE_END=C2=A0 \
-=C2=A0 =C2=A0 (AW_A10_PIT_TIMER_BASE * AW_A10_PIT_TIMER_NR + AW_A10_PIT_TI= MER_COUNT)
-
-#define AW_A10_PIT_DEFAULT_CLOCK=C2=A0 =C2=A00x4
-
=C2=A0typedef struct AwA10PITState AwA10PITState;

=C2=A0typedef struct AwA10TimerContext {
diff --git a/hw/timer/allwinner-a10-pit.c b/hw/timer/allwinner-a10-pit.c index b31a0bcd43..00f7cc492d 100644
--- a/hw/timer/allwinner-a10-pit.c
+++ b/hw/timer/allwinner-a10-pit.c
@@ -24,6 +24,36 @@
=C2=A0#include "qemu/log.h"
=C2=A0#include "qemu/module.h"

+#define AW_A10_PIT_TIMER_NR=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A06
+
+#define AW_A10_PIT_TIMER_IRQ_EN=C2=A0 =C2=A0 =C2=A00
+#define AW_A10_PIT_TIMER_IRQ_ST=C2=A0 =C2=A0 =C2=A00x4
+
+#define AW_A10_PIT_TIMER_CONTROL=C2=A0 =C2=A0 0x0
+#define AW_A10_PIT_TIMER_EN=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A00x1
+#define AW_A10_PIT_TIMER_RELOAD=C2=A0 =C2=A0 =C2=A00x2
+#define AW_A10_PIT_TIMER_MODE=C2=A0 =C2=A0 =C2=A0 =C2=A00x80
+
+#define AW_A10_PIT_TIMER_INTERVAL=C2=A0 =C2=A00x4
+#define AW_A10_PIT_TIMER_COUNT=C2=A0 =C2=A0 =C2=A0 0x8
+#define AW_A10_PIT_WDOG_CONTROL=C2=A0 =C2=A0 =C2=A00x90
+#define AW_A10_PIT_WDOG_MODE=C2=A0 =C2=A0 =C2=A0 =C2=A0 0x94
+
+#define AW_A10_PIT_COUNT_CTL=C2=A0 =C2=A0 =C2=A0 =C2=A0 0xa0
+#define AW_A10_PIT_COUNT_RL_EN=C2=A0 =C2=A0 =C2=A0 0x2
+#define AW_A10_PIT_COUNT_CLR_EN=C2=A0 =C2=A0 =C2=A00x1
+#define AW_A10_PIT_COUNT_LO=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A00xa4
+#define AW_A10_PIT_COUNT_HI=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A00xa8
+
+#define AW_A10_PIT_TIMER_BASE=C2=A0 =C2=A0 =C2=A0 =C2=A00x10
+#define AW_A10_PIT_TIMER_BASE_END=C2=A0 =C2=A0\
+=C2=A0 =C2=A0 (AW_A10_PIT_TIMER_BASE * AW_A10_PIT_TIMER_NR + AW_A10_PIT_TI= MER_COUNT)
+
+#define AW_A10_PIT_DEFAULT_CLOCK=C2=A0 =C2=A0 0x4
+
+#define AW_A10_PIT(obj) \
+=C2=A0 =C2=A0 OBJECT_CHECK(AwA10PITState, (obj), TYPE_AW_A10_PIT)
+
=C2=A0static void a10_pit_update_irq(AwA10PITState *s)
=C2=A0{
=C2=A0 =C2=A0 =C2=A0int i;
--
2.21.0


Looks fine and tested on -M orangepi= -pc, -M cubieboard:
=C2=A0=C2=A0 Tested-by: Niek Linnenbank <<= a href=3D"mailto:nieklinnenbank@gmail.com">nieklinnenbank@gmail.com>=
=C2=A0=C2=A0 Reviewed-by: Niek Linnenbank <nieklinnenbank@gmail.com>

-- =
Niek L= innenbank

--000000000000fe217a059a2989ed-- From MAILER-DAEMON Sat Dec 21 07:36:13 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1iidzR-0004t7-LM for mharc-qemu-arm@gnu.org; Sat, 21 Dec 2019 07:36:13 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:50904) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iidzO-0004sy-Nj for qemu-arm@nongnu.org; Sat, 21 Dec 2019 07:36:11 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1iidzN-0000Wd-AC for qemu-arm@nongnu.org; Sat, 21 Dec 2019 07:36:10 -0500 Received: from szxga07-in.huawei.com ([45.249.212.35]:48738 helo=huawei.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1iidzM-0007xw-Lu; Sat, 21 Dec 2019 07:36:09 -0500 Received: from DGGEMS411-HUB.china.huawei.com (unknown [172.30.72.59]) by Forcepoint Email with ESMTP id 5BEC98C9039688F26A78; Sat, 21 Dec 2019 20:35:53 +0800 (CST) Received: from [127.0.0.1] (10.142.68.147) by DGGEMS411-HUB.china.huawei.com (10.3.19.211) with Microsoft SMTP Server id 14.3.439.0; Sat, 21 Dec 2019 20:35:46 +0800 Subject: Re: [RESEND PATCH v21 5/6] target-arm: kvm64: handle SIGBUS signal from kernel or KVM To: Igor Mammedov , Xiang Zheng CC: , , , , , , , , , , , , , , , References: <20191111014048.21296-1-zhengxiang9@huawei.com> <20191111014048.21296-6-zhengxiang9@huawei.com> <20191115173713.795e5f63@redhat.com> From: gengdongjiu Message-ID: <38f13f15-960d-3e56-78f5-42b1ec61a322@huawei.com> Date: Sat, 21 Dec 2019 20:35:44 +0800 User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:52.0) Gecko/20100101 Thunderbird/52.3.0 MIME-Version: 1.0 In-Reply-To: <20191115173713.795e5f63@redhat.com> Content-Type: text/plain; charset="windows-1252" Content-Language: en-US Content-Transfer-Encoding: 7bit X-Originating-IP: [10.142.68.147] X-CFilter-Loop: Reflected X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 45.249.212.35 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sat, 21 Dec 2019 12:36:11 -0000 On 2019/11/16 0:37, Igor Mammedov wrote: >> + >> + /* zero means OSPM does not acknowledge the error */ >> + if (!read_ack_register) { >> + if (loop < 3) { >> + usleep(100 * 1000); >> + loop++; >> + goto retry; > as minimum this loop can stall guest repeatedly for 0.3s if guest triggers BQL, > until it handles error. I think reparations for 0.3s is reasonable. 1. 0.3s is the worst case to repeat, if guest acknowledge it in before 0.3s, the guest can not stall 2. if the previous error is not acknowledged, the next error will be lost, error handling(safety) is more important than others. > > (not sure what to suggest here though) > > (not sure what to suggest here though) > From MAILER-DAEMON Sat Dec 21 13:23:01 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1iijP2-0004F5-VG for mharc-qemu-arm@gnu.org; Sat, 21 Dec 2019 13:23:00 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:53485) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iijOz-00048o-34 for qemu-arm@nongnu.org; Sat, 21 Dec 2019 13:22:58 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1iijOx-00063K-2R for qemu-arm@nongnu.org; Sat, 21 Dec 2019 13:22:56 -0500 Received: from mail-il1-x141.google.com ([2607:f8b0:4864:20::141]:40593) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1iijOs-0005gh-TC; Sat, 21 Dec 2019 13:22:51 -0500 Received: by mail-il1-x141.google.com with SMTP id c4so10822963ilo.7; Sat, 21 Dec 2019 10:22:50 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=ZLCFWTYU9xOMO++Bg3cHTj2xEbQKJXfwi0dTYdgU4sw=; b=D0Rki1Pvmo/C3zY+q5P99TxRAfzWtGptRkGD/giuD0wG5JVn+DTXb4HchyYTJgbJ5B iCcGHwrBXrKeXP+Krw/liYEB2qhS1N+zYXCDiqubRp5XT78AhyzA549AA3B2Plc+iSqx t1KZXliCtn/rl+TvGiqwzL3gEo6RhCcprMvQs+RMuJ/zHGLVduub/ff+y2A5RnNelF1t pbXmIaRbUGLcRgG4TeSkice/6AAu+tT4cauleS6tZ8VtNBeUsLivlG7yiMu0YAtCdEvL xg61sld5oLNIMfZ3BDNeLSuVQvLWNped2uLWxrUse+P/lV+YX6CgJeMQ2nXHnIuWdpHt ei1g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=ZLCFWTYU9xOMO++Bg3cHTj2xEbQKJXfwi0dTYdgU4sw=; b=E8x19HAnkFttnXnFm+66wXq3Kj9WcHWU7I1YtMyHc/ckCydt6tO0hGj/z/fahpnHls VbnHufPJ7TcUgM0n+Oi5NSH9HME8cMHNwZ/TUw4GDsfkVVcX1+BYx3Itv3eQ0GJDz5b5 IZTnW++AY+Zs/v2a89vredRnMZGT28UXJUcSckaHljaLZBfhvsg+/3OedTe265Z04IZG eu1kHZKD3X6p4B0/lfi/++RC3pYQkvOsod62ECrmWSE73wrSz1bg09mp2CAoMCuBeVsG jkE1/pF+93FMnvyH8+jirP5bSr/cOtpfusTEpOJA/cXjXC/zXd0p+CfSNNfMZd3/3DB4 ykMg== X-Gm-Message-State: APjAAAVQhEWmfVL1pwoBkuXT6R72cCt2qpW7i4plm/slhOyGTlPiXUaJ j511IxXRnYZF8mMXf/hY1Ld3BI1DaPh5Wv1JZ8w= X-Google-Smtp-Source: APXvYqxkpCRbPNm3bZzkc2Tg+zMuqmUEWgCoSt4HtC/1ERDMf3cJB/f3A6hrGQj8aQ9iHcp0/qvvEOYRcK0KZwMqbWQ= X-Received: by 2002:a92:af08:: with SMTP id n8mr17618555ili.217.1576952569890; Sat, 21 Dec 2019 10:22:49 -0800 (PST) MIME-Version: 1.0 References: <20191217182730.943-1-f4bug@amsat.org> <20191217182730.943-2-f4bug@amsat.org> In-Reply-To: <20191217182730.943-2-f4bug@amsat.org> From: Niek Linnenbank Date: Sat, 21 Dec 2019 19:22:38 +0100 Message-ID: Subject: Re: [PATCH 1/5] tests/boot_linux_console: Add a quick test for the OrangePi PC board To: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= Cc: QEMU Developers , Guenter Roeck , Cleber Rosa , Peter Maydell , qemu-arm Content-Type: multipart/alternative; boundary="000000000000c18efa059a3ae11e" X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::141 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sat, 21 Dec 2019 18:22:59 -0000 --000000000000c18efa059a3ae11e Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Hi Philippe, On Tue, Dec 17, 2019 at 7:27 PM Philippe Mathieu-Daud=C3=A9 wrote: > This test boots a Linux kernel on a OrangePi PC board and verify > the serial output is working. > > The kernel image and DeviceTree blob are built by the Raspbian > project (based on Debian): > https://www.raspbian.org/RaspbianImages One minor remark: I noticed here you refer to Raspbian, while the actual image used is from Armbian :-) > > If ARM is a target being built, "make check-acceptance" will > automatically include this test by the use of the "arch:arm" tags. > > Alternatively, this test can be run using: > > $ make check-venv > $ ./tests/venv/bin/avocado --show=3Dconsole,app run -t machine:orangepi= -pc > tests/acceptance/boot_linux_console.py > JOB ID : 2e4d15eceb13c33672af406f08171e6e9de1414a > JOB LOG : ~/job-results/job-2019-12-17T05.46-2e4d15e/job.log > (1/1) > tests/acceptance/boot_linux_console.py:BootLinuxConsole.test_arm_orangepi= : > console: Uncompressing Linux... done, booting the kernel. > console: Booting Linux on physical CPU 0x0 > console: Linux version 4.20.7-sunxi (root@armbian.com) (gcc version > 7.2.1 20171011 (Linaro GCC 7.2-2017.11)) #5.75 SMP Fri Feb 8 09:02:10 CET > 2019 > console: CPU: ARMv7 Processor [410fc075] revision 5 (ARMv7), cr=3D50c53= 87d > console: CPU: div instructions available: patching division code > console: CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing > instruction cache > console: OF: fdt: Machine model: Xunlong Orange Pi PC > console: Memory policy: Data cache writealloc > console: OF: reserved mem: failed to allocate memory for node > 'cma@4a000000' > console: cma: Failed to reserve 128 MiB > console: psci: probing for conduit method from DT. > console: psci: PSCIv0.2 detected in firmware. > console: psci: Using standard PSCI v0.2 function IDs > console: psci: Trusted OS migration not required > console: random: get_random_bytes called from start_kernel+0x8d/0x3c2 > with crng_init=3D0 > console: percpu: Embedded 18 pages/cpu @(ptrval) s41228 r8192 d24308 > u73728 > console: Built 1 zonelists, mobility grouping on. Total pages: 32480 > console: Kernel command line: printk.time=3D0 console=3DttyS0,115200 > PASS (8.59 s) > JOB TIME : 8.81 s > > Signed-off-by: Philippe Mathieu-Daud=C3=A9 > --- > tests/acceptance/boot_linux_console.py | 26 ++++++++++++++++++++++++++ > 1 file changed, 26 insertions(+) > > diff --git a/tests/acceptance/boot_linux_console.py > b/tests/acceptance/boot_linux_console.py > index 7e41cebd47..820239e439 100644 > --- a/tests/acceptance/boot_linux_console.py > +++ b/tests/acceptance/boot_linux_console.py > @@ -411,6 +411,32 @@ class BootLinuxConsole(Test): > self.wait_for_console_pattern('Boot successful.') > # TODO user command, for now the uart is stuck > > + def test_arm_orangepi(self): > + """ > + :avocado: tags=3Darch:arm > + :avocado: tags=3Dmachine:orangepi-pc > + """ > + deb_url =3D ('https://apt.armbian.com/pool/main/l/' > + > 'linux-4.20.7-sunxi/linux-image-dev-sunxi_5.75_armhf.deb') > + deb_hash =3D '1334c29c44d984ffa05ed10de8c3361f33d78315' > + deb_path =3D self.fetch_asset(deb_url, asset_hash=3Ddeb_hash) > + kernel_path =3D self.extract_from_deb(deb_path, > + '/boot/vmlinuz-4.20.7-sunxi'= ) > + dtb_path =3D > '/usr/lib/linux-image-dev-sunxi/sun8i-h3-orangepi-pc.dtb' > + dtb_path =3D self.extract_from_deb(deb_path, dtb_path) > + > + self.vm.set_machine('orangepi-pc') > + self.vm.set_console() > + kernel_command_line =3D (self.KERNEL_COMMON_COMMAND_LINE + > + 'console=3DttyS0,115200n8 ' > + 'earlycon=3Duart,mmio32,0x1c28000') > + self.vm.add_args('-kernel', kernel_path, > + '-dtb', dtb_path, > + '-append', kernel_command_line) > + self.vm.launch() > + console_pattern =3D 'Kernel command line: %s' % kernel_command_l= ine > + self.wait_for_console_pattern(console_pattern) > + > def test_s390x_s390_ccw_virtio(self): > """ > :avocado: tags=3Darch:s390x > -- > 2.21.0 > > --=20 Niek Linnenbank --000000000000c18efa059a3ae11e Content-Type: text/html; charset="UTF-8" Content-Transfer-Encoding: quoted-printable
Hi Philippe,

=
On Tue, Dec 17, 2019 at 7:27 PM Phili= ppe Mathieu-Daud=C3=A9 <f4bug@amsat.o= rg> wrote:
https://www.raspbian.org/RaspbianImages
=
One minor remark: I noticed here you refer to Raspbian, whil= e the actual image
used is from Armbian :-)



If ARM is a target being built, "make check-acceptance" will
automatically include this test by the use of the "arch:arm" tags= .

Alternatively, this test can be run using:

=C2=A0 $ make check-venv
=C2=A0 $ ./tests/venv/bin/avocado --show=3Dconsole,app run -t machine:orang= epi-pc tests/acceptance/boot_linux_console.py
=C2=A0 JOB ID=C2=A0 =C2=A0 =C2=A0: 2e4d15eceb13c33672af406f08171e6e9de1414a=
=C2=A0 JOB LOG=C2=A0 =C2=A0 : ~/job-results/job-2019-12-17T05.46-2e4d15e/jo= b.log
=C2=A0 (1/1) tests/acceptance/boot_linux_console.py:BootLinuxConsole.test_a= rm_orangepi:
=C2=A0 console: Uncompressing Linux... done, booting the kernel.
=C2=A0 console: Booting Linux on physical CPU 0x0
=C2=A0 console: Linux version 4.20.7-sunxi (root@armbian.com) (gcc version 7.2.1 20171011 (L= inaro GCC 7.2-2017.11)) #5.75 SMP Fri Feb 8 09:02:10 CET 2019
=C2=A0 console: CPU: ARMv7 Processor [410fc075] revision 5 (ARMv7), cr=3D50= c5387d
=C2=A0 console: CPU: div instructions available: patching division code
=C2=A0 console: CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing inst= ruction cache
=C2=A0 console: OF: fdt: Machine model: Xunlong Orange Pi PC
=C2=A0 console: Memory policy: Data cache writealloc
=C2=A0 console: OF: reserved mem: failed to allocate memory for node 'c= ma@4a000000'
=C2=A0 console: cma: Failed to reserve 128 MiB
=C2=A0 console: psci: probing for conduit method from DT.
=C2=A0 console: psci: PSCIv0.2 detected in firmware.
=C2=A0 console: psci: Using standard PSCI v0.2 function IDs
=C2=A0 console: psci: Trusted OS migration not required
=C2=A0 console: random: get_random_bytes called from start_kernel+0x8d/0x3c= 2 with crng_init=3D0
=C2=A0 console: percpu: Embedded 18 pages/cpu @(ptrval) s41228 r8192 d24308= u73728
=C2=A0 console: Built 1 zonelists, mobility grouping on.=C2=A0 Total pages:= 32480
=C2=A0 console: Kernel command line: printk.time=3D0 console=3DttyS0,115200=
=C2=A0 PASS (8.59 s)
=C2=A0 JOB TIME=C2=A0 =C2=A0: 8.81 s

Signed-off-by: Philippe Mathieu-Daud=C3=A9 <f4bug@amsat.org>
---
=C2=A0tests/acceptance/boot_linux_console.py | 26 +++++++++++++++++++++++++= +
=C2=A01 file changed, 26 insertions(+)

diff --git a/tests/acceptance/boot_linux_console.py b/tests/acceptance/boot= _linux_console.py
index 7e41cebd47..820239e439 100644
--- a/tests/acceptance/boot_linux_console.py
+++ b/tests/acceptance/boot_linux_console.py
@@ -411,6 +411,32 @@ class BootLinuxConsole(Test):
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0self.wait_for_console_pattern('Boot s= uccessful.')
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0# TODO user command, for now the uart is = stuck

+=C2=A0 =C2=A0 def test_arm_orangepi(self):
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 """
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 :avocado: tags=3Darch:arm
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 :avocado: tags=3Dmachine:orangepi-pc
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 """
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 deb_url =3D ('https://apt.armbi= an.com/pool/main/l/'
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0'= linux-4.20.7-sunxi/linux-image-dev-sunxi_5.75_armhf.deb')
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 deb_hash =3D '1334c29c44d984ffa05ed10de8c3= 361f33d78315'
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 deb_path =3D self.fetch_asset(deb_url, asset_h= ash=3Ddeb_hash)
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 kernel_path =3D self.extract_from_deb(deb_path= ,
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 '/boot/vmlinuz-4.20.7-sunxi')
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 dtb_path =3D '/usr/lib/linux-image-dev-sun= xi/sun8i-h3-orangepi-pc.dtb'
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 dtb_path =3D self.extract_from_deb(deb_path, d= tb_path)
+
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 self.vm.set_machine('orangepi-pc')
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 self.vm.set_console()
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 kernel_command_line =3D (self.KERNEL_COMMON_CO= MMAND_LINE +
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0'console=3DttyS0,115200n8 ' +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0'earlycon=3Duart,mmio32,0x1c28000= ')
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 self.vm.add_args('-kernel', kernel_pat= h,
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0'-dtb', dtb_path,
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0'-append', kernel_command_line)
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 self.vm.launch()
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 console_pattern =3D 'Kernel command line: = %s' % kernel_command_line
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 self.wait_for_console_pattern(console_pattern)=
+
=C2=A0 =C2=A0 =C2=A0def test_s390x_s390_ccw_virtio(self):
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0"""
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0:avocado: tags=3Darch:s390x
--
2.21.0



--
Niek Linnenbank

--000000000000c18efa059a3ae11e-- From MAILER-DAEMON Mon Dec 23 03:21:21 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1ijIxr-00025U-UA for mharc-qemu-arm@gnu.org; Mon, 23 Dec 2019 03:21:21 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:38335) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ijIxo-00022x-4P for qemu-arm@nongnu.org; Mon, 23 Dec 2019 03:21:17 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ijIxm-0005yE-5k for qemu-arm@nongnu.org; Mon, 23 Dec 2019 03:21:15 -0500 Received: from szxga04-in.huawei.com ([45.249.212.190]:2227 helo=huawei.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1ijIxl-0005RB-OP; Mon, 23 Dec 2019 03:21:14 -0500 Received: from DGGEMS405-HUB.china.huawei.com (unknown [172.30.72.60]) by Forcepoint Email with ESMTP id E3E14B45958003554A93; Mon, 23 Dec 2019 16:21:05 +0800 (CST) Received: from [127.0.0.1] (10.133.216.73) by DGGEMS405-HUB.china.huawei.com (10.3.19.205) with Microsoft SMTP Server id 14.3.439.0; Mon, 23 Dec 2019 16:20:56 +0800 Subject: Re: [RFC v2 00/14] Add SDEI support for arm64 To: Peter Maydell CC: qemu-arm , QEMU Developers , , Dave Martin , Marc Zyngier , Mark Rutland , James Morse , "Michael S. Tsirkin" , Cornelia Huck , Paolo Bonzini , Shannon Zhao , Igor Mammedov References: <20191105091056.9541-1-guoheyi@huawei.com> From: Guoheyi Message-ID: <5aece614-4341-35e5-53a6-2f3d788e6e8d@huawei.com> Date: Mon, 23 Dec 2019 16:20:55 +0800 User-Agent: Mozilla/5.0 (Windows NT 10.0; WOW64; rv:68.0) Gecko/20100101 Thunderbird/68.2.2 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset="utf-8"; format=flowed X-Originating-IP: [10.133.216.73] X-CFilter-Loop: Reflected Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 45.249.212.190 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 23 Dec 2019 08:21:17 -0000 Hi Peter, Really appreciate your comments. For other platforms/boards emulated in qemu, like omap, imx*, etc, are=20 they just TCG platforms? Can we just enable security and EL3 emulation=20 for these platforms instead of implementing copies of firmware=20 interfaces in qemu? Also I think it is possible to optimize the code to=20 support all KVM enabled virtual boards with one single copy of SDEI=20 code, so at least the duplication of code inside qemu might be avoided. I can understand your concerns; the exsiting SDEI code in ARM Trusted=20 Firmware also tempted me when I started to writing the code in qemu. I=20 agree the ideal way is to use the existing firmware directly, but how=20 can we achieve that? Either I don't think it is good to modify the=20 firmware code too much, for firmware should be kept simple and reliable. Does James or Marc have any idea? Thanks, Heyi =E5=9C=A8 2019/12/20 21:44, Peter Maydell =E5=86=99=E9=81=93: > On Tue, 5 Nov 2019 at 09:12, Heyi Guo wrote: >> SDEI is for ARM "Software Delegated Exception Interface". AS ARM64 doe= sn't have >> native non-maskable interrupt (NMI), we rely on higher privileged (lar= ger >> exception level) software to change the execution flow of lower privil= eged >> (smaller exception level) software when certain events occur, to emula= te NMI >> mechanism, and SDEI is the standard interfaces between the two levels = of >> privileged software. It is based on SMC/HVC calls. >> >> The higher privileged software implements an SDEI dispatcher to handle= SDEI >> related SMC/HVC calls and trigger SDEI events; the lower privileged so= ftware >> implements an SDEI client to request SDEI services and handle SDEI eve= nts. > Hi; I read through these patches last week, but I didn't reply > then because although there are some aspects to the design that > I don't like, I don't have a clear idea of what a better approach > to the problems it's trying to solve would be. However I didn't > want to go home for the end of the year without providing at > least some response. So I'm going to lay out the parts I have > issues with and perhaps somebody else will have a good idea. > > The first part that I dislike here is that this is implementing > an entire ABI which in real hardware is provided by firmware. I > think that QEMU's design works best when QEMU provides emulation of > hardware or hardware-like facilities, which guest code (either > in the kernel, or firmware/bios running in the guest) can then > make use of. Once we start getting into implementing firmware > interfaces directly in QEMU this rapidly becomes a large amount > of work and code, and it's unclear where it should stop. Should > we implement also the equivalent of firmware for omap boards? > For imx* boards? For the raspberry pi? For xilinx boards? > Are we going to end up reimplementing more of ARM Trusted Firmware > functionality inside QEMU? The code to implement firmware-equivalent > ABIs in all these boards would I think quickly become a large part > of the codebase. > > My second concern is that to do the things it wants to do, > the implementation here does some pretty invasive things: > * intercepting interrupt lines which ought to just be > emulated hardware signals between devices and the GIC > * capturing register values of other CPUs, and arbitrarily > stopping those other CPUs and making them run other code > at a later point in time > I'm really uncomfortable with what's just an 'emulated firmware' > interface for one specific board model doing this kind of thing. > > Finally, the stated rationale for the patchset ("we'd like an > emulated NMI equivalent") doesn't really feel to me like it's > strong enough to counterbalance the amount of code here and > the degree to which it's moving us into a swamp I'd prefer > it if we could stay out of. > > I'd be much happier with a design where QEMU provides simple > facilities to the guest and the guest firmware and kernel > deal with making use of them. I appreciate that it's not > clear how that would work though, given that in real hardware > this works by the firmware running at EL3 and KVM not > providing a mechanism that allows guest code that runs at > a higher (effective or emulated) privilege level than the > guest kernel... > > thanks > -- PMM > > . From MAILER-DAEMON Mon Dec 23 04:12:01 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1ijJkv-00018X-8Y for mharc-qemu-arm@gnu.org; Mon, 23 Dec 2019 04:12:01 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:58009) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ijJks-00018I-Qu for qemu-arm@nongnu.org; Mon, 23 Dec 2019 04:12:00 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ijJkq-0003rd-A3 for qemu-arm@nongnu.org; Mon, 23 Dec 2019 04:11:57 -0500 Received: from us-smtp-2.mimecast.com ([205.139.110.61]:24227 helo=us-smtp-1.mimecast.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1ijJkp-0003kQ-QM for qemu-arm@nongnu.org; Mon, 23 Dec 2019 04:11:56 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1577092314; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=f/xlkTrstnlRNO4FHVwyPI1ENajclFfywGWkCwYYhL8=; b=Eit4hSy9tg++TF/RK5CnRU04vqMS9Cqn1XS1nZ8eI91j+zhPDdrB90ng4WXcX9PIYA3Cau ypAi3bPXMCoKAbvK3bbAkcAYhxTg7b1lmHBt23p3s3mTC94k1UboqS4kCDLg73YAFYXzO9 NP8+01S8eZs19zaEOvY1WIk7sAopa/E= Received: from mimecast-mx01.redhat.com (mimecast-mx01.redhat.com [209.132.183.4]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-18-msKCyRmkPfiF8ozY0gdOAw-1; Mon, 23 Dec 2019 04:11:53 -0500 Received: from smtp.corp.redhat.com (int-mx02.intmail.prod.int.phx2.redhat.com [10.5.11.12]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx01.redhat.com (Postfix) with ESMTPS id BA48D189DF40; Mon, 23 Dec 2019 09:11:51 +0000 (UTC) Received: from [10.36.116.117] (ovpn-116-117.ams2.redhat.com [10.36.116.117]) by smtp.corp.redhat.com (Postfix) with ESMTPS id BCED260BE0; Mon, 23 Dec 2019 09:11:41 +0000 (UTC) Subject: Re: [PATCH for-5.0 v11 05/20] virtio-iommu: Endpoint and domains structs and helpers To: Jean-Philippe Brucker Cc: yang.zhong@intel.com, peter.maydell@linaro.org, kevin.tian@intel.com, tnowicki@marvell.com, mst@redhat.com, jean-philippe.brucker@arm.com, quintela@redhat.com, qemu-devel@nongnu.org, peterx@redhat.com, armbru@redhat.com, bharatb.linux@gmail.com, qemu-arm@nongnu.org, dgilbert@redhat.com, eric.auger.pro@gmail.com References: <20191122182943.4656-1-eric.auger@redhat.com> <20191122182943.4656-6-eric.auger@redhat.com> <20191210163716.GD277340@myrica> <28597404-b9ac-8c16-e9e8-ad5793f2f5a3@redhat.com> <20191220170028.GB2626852@myrica> From: Auger Eric Message-ID: Date: Mon, 23 Dec 2019 10:11:37 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101 Thunderbird/60.4.0 MIME-Version: 1.0 In-Reply-To: <20191220170028.GB2626852@myrica> Content-Language: en-US X-Scanned-By: MIMEDefang 2.79 on 10.5.11.12 X-MC-Unique: msKCyRmkPfiF8ozY0gdOAw-1 X-Mimecast-Spam-Score: 0 Content-Type: text/plain; charset=windows-1252 Content-Transfer-Encoding: 7bit X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 205.139.110.61 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 23 Dec 2019 09:12:00 -0000 Hi Jean, On 12/20/19 6:00 PM, Jean-Philippe Brucker wrote: > On Thu, Dec 19, 2019 at 07:31:08PM +0100, Auger Eric wrote: >> Hi Jean, >> >> On 12/10/19 5:37 PM, Jean-Philippe Brucker wrote: >>> On Fri, Nov 22, 2019 at 07:29:28PM +0100, Eric Auger wrote: >>>> +typedef struct viommu_domain { >>>> + uint32_t id; >>>> + GTree *mappings; >>>> + QLIST_HEAD(, viommu_endpoint) endpoint_list; >>>> +} viommu_domain; >>>> + >>>> +typedef struct viommu_endpoint { >>>> + uint32_t id; >>>> + viommu_domain *domain; >>>> + QLIST_ENTRY(viommu_endpoint) next; >>>> +} viommu_endpoint; >>> >>> There might be a way to merge viommu_endpoint and the IOMMUDevice >>> structure introduced in patch 4, since they both represent one endpoint. >>> Maybe virtio_iommu_find_add_pci_as() could add the IOMMUDevice to >>> s->endpoints, and IOMMUDevice could store the endpoint ID rather than bus >>> and devfn. >> >> On PCI bus enumeration we locally store the PCI bus hierarchy under the >> form of GHashTable of IOMMUDevice indexed by iommu_pci_bus pointer. >> Those are all the devices attached to the downstream buses. We also use >> an array of iommu pci bus pointers indexed by bus number that is lazily >> populated due to the fact, at enumeration time we do know the bus number >> yet. As you pointed, I haven't used the array of iommu pci bus pointers >> indexed by bus number in this series and I should actually. Currently I >> am not checking on attach that the sid effectively corresponds to a sid >> protected by this iommu. I will add this in my next version. The above >> structures are used in intel_iommu and smmu code as well and I think >> eventually this may be factorized a common base class.. >> >> on the other hand the gtree of viommu_endpoint - soon renamed in >> CamelCase form ;-) - corresponds to the EPs that are actually attached >> to any domain. It is indexed by sid and not by bus pointer. This is more >> adapted to the virtio-iommu case. >> >> So, despite your suggestion, I am tempted to keep the different >> structures as the first ones are common to all iommu emulation code and >> the last is adapted to the virtio-iommu operations. >> >> Thoughts? > > Makes sense, it seems better to keep them separate. I had missed that the > PCI bus number is resolved later, and started to move the endpoint ID into > IOMMUDevice when adding MMIO support, but I'll need to revisit this. > > I'll be off for two weeks, have a nice holiday! Thanks, you too. Merry Christmas! :-) Eric > > Thanks, > Jean > From MAILER-DAEMON Mon Dec 23 04:14:34 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1ijJnO-0003Ms-Jj for mharc-qemu-arm@gnu.org; Mon, 23 Dec 2019 04:14:34 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:36021) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ijJnM-0003Ke-Jl for qemu-arm@nongnu.org; Mon, 23 Dec 2019 04:14:33 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ijJnL-0006sw-An for qemu-arm@nongnu.org; Mon, 23 Dec 2019 04:14:32 -0500 Received: from us-smtp-delivery-1.mimecast.com ([207.211.31.120]:36632 helo=us-smtp-1.mimecast.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1ijJnL-0006qF-5f for qemu-arm@nongnu.org; Mon, 23 Dec 2019 04:14:31 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1577092470; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=mbQBLxoCEwlwW3ReN5aW2HRPYMTYuCRL7C8tlTZoOLM=; b=epPGXEZc4ya6ZEqRa4VjaGvzvoqSEH8hMAfuAXLmu0xl2vBN6moCxNJZUaFwCYr5ed5wGY 7ViNdSSYmPyWdObnqw1xPfxGZ+vzzZ9CCoHPeWb7q4dEnK4La5TCWfwWaVBA485n9hsWTM 4LO+XJjMVElECDERnfYOWAzdiXDgVyE= Received: from mimecast-mx01.redhat.com (mimecast-mx01.redhat.com [209.132.183.4]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-387-1rjFu8BaP1OQ4D2Lz402PA-1; Mon, 23 Dec 2019 04:14:29 -0500 Received: from smtp.corp.redhat.com (int-mx04.intmail.prod.int.phx2.redhat.com [10.5.11.14]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx01.redhat.com (Postfix) with ESMTPS id C4738DB60; Mon, 23 Dec 2019 09:14:27 +0000 (UTC) Received: from [10.36.116.117] (ovpn-116-117.ams2.redhat.com [10.36.116.117]) by smtp.corp.redhat.com (Postfix) with ESMTPS id 4A0F95D9D6; Mon, 23 Dec 2019 09:14:11 +0000 (UTC) Subject: Re: [PATCH for-5.0 v11 06/20] virtio-iommu: Implement attach/detach command To: Jean-Philippe Brucker Cc: eric.auger.pro@gmail.com, qemu-devel@nongnu.org, qemu-arm@nongnu.org, peter.maydell@linaro.org, mst@redhat.com, armbru@redhat.com, jean-philippe.brucker@arm.com, bharatb.linux@gmail.com, yang.zhong@intel.com, dgilbert@redhat.com, quintela@redhat.com, kevin.tian@intel.com, peterx@redhat.com, tnowicki@marvell.com References: <20191122182943.4656-1-eric.auger@redhat.com> <20191122182943.4656-7-eric.auger@redhat.com> <20191210164156.GE277340@myrica> From: Auger Eric Message-ID: <531cb6d7-6a2b-1278-a4d2-f4ea11442967@redhat.com> Date: Mon, 23 Dec 2019 10:14:09 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101 Thunderbird/60.4.0 MIME-Version: 1.0 In-Reply-To: <20191210164156.GE277340@myrica> Content-Language: en-US X-Scanned-By: MIMEDefang 2.79 on 10.5.11.14 X-MC-Unique: 1rjFu8BaP1OQ4D2Lz402PA-1 X-Mimecast-Spam-Score: 0 Content-Type: text/plain; charset=windows-1252 Content-Transfer-Encoding: 7bit X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 207.211.31.120 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 23 Dec 2019 09:14:34 -0000 Hi Jean, On 12/10/19 5:41 PM, Jean-Philippe Brucker wrote: > On Fri, Nov 22, 2019 at 07:29:29PM +0100, Eric Auger wrote: >> diff --git a/hw/virtio/virtio-iommu.c b/hw/virtio/virtio-iommu.c >> index 235bde2203..138d5b2a9c 100644 >> --- a/hw/virtio/virtio-iommu.c >> +++ b/hw/virtio/virtio-iommu.c >> @@ -77,11 +77,12 @@ static gint interval_cmp(gconstpointer a, gconstpointer b, gpointer user_data) >> static void virtio_iommu_detach_endpoint_from_domain(viommu_endpoint *ep) >> { >> QLIST_REMOVE(ep, next); >> + g_tree_unref(ep->domain->mappings); >> ep->domain = NULL; >> } >> >> -viommu_endpoint *virtio_iommu_get_endpoint(VirtIOIOMMU *s, uint32_t ep_id); >> -viommu_endpoint *virtio_iommu_get_endpoint(VirtIOIOMMU *s, uint32_t ep_id) >> +static viommu_endpoint *virtio_iommu_get_endpoint(VirtIOIOMMU *s, >> + uint32_t ep_id) >> { >> viommu_endpoint *ep; >> >> @@ -102,15 +103,14 @@ static void virtio_iommu_put_endpoint(gpointer data) >> >> if (ep->domain) { >> virtio_iommu_detach_endpoint_from_domain(ep); >> - g_tree_unref(ep->domain->mappings); >> } >> >> trace_virtio_iommu_put_endpoint(ep->id); >> g_free(ep); >> } >> >> -viommu_domain *virtio_iommu_get_domain(VirtIOIOMMU *s, uint32_t domain_id); >> -viommu_domain *virtio_iommu_get_domain(VirtIOIOMMU *s, uint32_t domain_id) >> +static viommu_domain *virtio_iommu_get_domain(VirtIOIOMMU *s, >> + uint32_t domain_id) > > Looks like the above change belong to patch 5? virtio_iommu_get_domain was not used yet in last patch. I turn it into static now it gets used. > >> { >> viommu_domain *domain; >> >> @@ -137,7 +137,6 @@ static void virtio_iommu_put_domain(gpointer data) >> QLIST_FOREACH_SAFE(iter, &domain->endpoint_list, next, tmp) { >> virtio_iommu_detach_endpoint_from_domain(iter); >> } >> - g_tree_destroy(domain->mappings); > > When created by virtio_iommu_get_domain(), mappings has one reference. > Then for each attach (including the first one) an additional reference is > taken, and freed by virtio_iommu_detach_endpoint_from_domain(). So I think > there are two problems: > > * virtio_iommu_put_domain() drops one ref for each endpoint, but we still > have one reference to mappings, so they're not freed. We do need this > g_tree_destroy() > > * After detaching all the endpoints, the guest may reuse the domain ID for > another domain, but the previous mappings haven't been erased. Not sure > how to fix this using the g_tree refs, because dropping all the > references will free the internal tree data and it won't be reusable. You're perfectly right, mappings were not destroyed and I missed that. So I made 2 modifications: - do not increment the ref count on the first EP addition - destroy the domain when its EP list get empty. Thanks Eric > > Thanks, > Jean > From MAILER-DAEMON Mon Dec 23 04:43:01 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1ijKEv-0001FQ-LR for mharc-qemu-arm@gnu.org; Mon, 23 Dec 2019 04:43:01 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:43609) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ijKEr-0001EW-OD for qemu-arm@nongnu.org; Mon, 23 Dec 2019 04:42:59 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ijKEp-0001fL-Bc for qemu-arm@nongnu.org; Mon, 23 Dec 2019 04:42:56 -0500 Received: from us-smtp-1.mimecast.com ([207.211.31.81]:41213 helo=us-smtp-delivery-1.mimecast.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1ijKEp-0001V9-09 for qemu-arm@nongnu.org; Mon, 23 Dec 2019 04:42:55 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1577094173; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=p5WFdi2YPr6EXHNmft+uuLWxzpFSEFohSYCFOmJOj0M=; b=GG7t1jzpeBHtxecBK7SQzKw9tdNHimfnoq5n/fIT9X4T+uJnVOpx4GomNdcKfh0+Yx8rhX lMFh7MkPN4jT55EiQLX6LxAth1AmDO+3d/cTuXlf+yIAfc9A9ztAbY1NafvWA1ww3Qnm+i TeNcA4dFVEuQeFqd14IklBpfLQPXSTA= Received: from mimecast-mx01.redhat.com (mimecast-mx01.redhat.com [209.132.183.4]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-27-3yZPyScBOgK4c8ouKzDSjw-1; Mon, 23 Dec 2019 04:42:52 -0500 Received: from smtp.corp.redhat.com (int-mx02.intmail.prod.int.phx2.redhat.com [10.5.11.12]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx01.redhat.com (Postfix) with ESMTPS id 0E6C5184B44D; Mon, 23 Dec 2019 09:42:51 +0000 (UTC) Received: from [10.36.116.117] (ovpn-116-117.ams2.redhat.com [10.36.116.117]) by smtp.corp.redhat.com (Postfix) with ESMTPS id CC49360BF1; Mon, 23 Dec 2019 09:42:39 +0000 (UTC) Subject: Re: [PATCH for-5.0 v11 07/20] virtio-iommu: Implement map/unmap To: Jean-Philippe Brucker Cc: eric.auger.pro@gmail.com, qemu-devel@nongnu.org, qemu-arm@nongnu.org, peter.maydell@linaro.org, mst@redhat.com, armbru@redhat.com, jean-philippe.brucker@arm.com, bharatb.linux@gmail.com, yang.zhong@intel.com, dgilbert@redhat.com, quintela@redhat.com, kevin.tian@intel.com, peterx@redhat.com, tnowicki@marvell.com References: <20191122182943.4656-1-eric.auger@redhat.com> <20191122182943.4656-8-eric.auger@redhat.com> <20191210164328.GF277340@myrica> From: Auger Eric Message-ID: Date: Mon, 23 Dec 2019 10:42:37 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101 Thunderbird/60.4.0 MIME-Version: 1.0 In-Reply-To: <20191210164328.GF277340@myrica> Content-Language: en-US X-Scanned-By: MIMEDefang 2.79 on 10.5.11.12 X-MC-Unique: 3yZPyScBOgK4c8ouKzDSjw-1 X-Mimecast-Spam-Score: 0 Content-Type: text/plain; charset=windows-1252 Content-Transfer-Encoding: 7bit X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 207.211.31.81 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 23 Dec 2019 09:43:00 -0000 Hi jean, On 12/10/19 5:43 PM, Jean-Philippe Brucker wrote: > On Fri, Nov 22, 2019 at 07:29:30PM +0100, Eric Auger wrote: >> @@ -238,10 +244,35 @@ static int virtio_iommu_map(VirtIOIOMMU *s, >> uint64_t virt_start = le64_to_cpu(req->virt_start); >> uint64_t virt_end = le64_to_cpu(req->virt_end); >> uint32_t flags = le32_to_cpu(req->flags); >> + viommu_domain *domain; >> + viommu_interval *interval; >> + viommu_mapping *mapping; > > Additional checks would be good. Most importantly we need to return > S_INVAL if we don't recognize a bit in flags (a MUST in the spec). Sure It > might be good to check that addresses are aligned on the page granule as > well, and return S_RANGE if they aren't (a SHOULD in the spec), but I > don't care as much. with KVM accelerated guest I don't have access to the guest page size, hence the choice of not checking it. > >> + >> + interval = g_malloc0(sizeof(*interval)); >> + >> + interval->low = virt_start; >> + interval->high = virt_end; >> + >> + domain = g_tree_lookup(s->domains, GUINT_TO_POINTER(domain_id)); >> + if (!domain) { >> + return VIRTIO_IOMMU_S_NOENT; > > Leaks interval, I guess you could allocate it after this block. Sure Thanks! Eric > > Thanks, > Jean > >> + } >> + >> + mapping = g_tree_lookup(domain->mappings, (gpointer)interval); >> + if (mapping) { >> + g_free(interval); >> + return VIRTIO_IOMMU_S_INVAL; >> + } >> >> trace_virtio_iommu_map(domain_id, virt_start, virt_end, phys_start, flags); >> >> - return VIRTIO_IOMMU_S_UNSUPP; >> + mapping = g_malloc0(sizeof(*mapping)); >> + mapping->phys_addr = phys_start; >> + mapping->flags = flags; >> + >> + g_tree_insert(domain->mappings, interval, mapping); >> + >> + return VIRTIO_IOMMU_S_OK; > From MAILER-DAEMON Tue Dec 24 02:40:01 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1ijenR-0000Ef-B6 for mharc-qemu-arm@gnu.org; Tue, 24 Dec 2019 02:40:01 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:56073) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ijenN-0000DK-R6 for qemu-arm@nongnu.org; Tue, 24 Dec 2019 02:39:59 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ijenL-0002mZ-0x for qemu-arm@nongnu.org; Tue, 24 Dec 2019 02:39:55 -0500 Received: from us-smtp-2.mimecast.com ([205.139.110.61]:51869 helo=us-smtp-delivery-1.mimecast.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1ijenI-0002lq-88 for qemu-arm@nongnu.org; Tue, 24 Dec 2019 02:39:54 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1577173191; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=wGJP6+ula4Kds+MGAy+5EyTiOxYEIVarv7O6UPBDLFI=; b=U2liXCVDbwqNicoVBuJsP9l1bX1dzHB4LEEN5yTpQFZiJjjAWphecyOkRNW5eNTRU1ExES CV8DG094nTRWFt/i8ghFOHqIB1WV50s2SKqhIuaAijN1A5o1wJU239KBLz+84vm3PCMNW0 L36qH6pM9MQ8yEbli4zkvuSbMh7S7PQ= Received: from mimecast-mx01.redhat.com (mimecast-mx01.redhat.com [209.132.183.4]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-428-CP2_L6rzNKWoMperVLFUlA-1; Tue, 24 Dec 2019 02:39:47 -0500 Received: from smtp.corp.redhat.com (int-mx03.intmail.prod.int.phx2.redhat.com [10.5.11.13]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx01.redhat.com (Postfix) with ESMTPS id 862D4107ACC4; Tue, 24 Dec 2019 07:39:45 +0000 (UTC) Received: from [10.36.116.117] (ovpn-116-117.ams2.redhat.com [10.36.116.117]) by smtp.corp.redhat.com (Postfix) with ESMTPS id 9F1DA81740; Tue, 24 Dec 2019 07:39:34 +0000 (UTC) Subject: Re: [PATCH for-5.0 v11 18/20] virtio-iommu: Support migration To: Peter Xu Cc: eric.auger.pro@gmail.com, qemu-devel@nongnu.org, qemu-arm@nongnu.org, peter.maydell@linaro.org, mst@redhat.com, armbru@redhat.com, jean-philippe.brucker@arm.com, bharatb.linux@gmail.com, yang.zhong@intel.com, dgilbert@redhat.com, quintela@redhat.com, kevin.tian@intel.com, tnowicki@marvell.com References: <20191122182943.4656-1-eric.auger@redhat.com> <20191122182943.4656-19-eric.auger@redhat.com> <20191210200110.GM3352@xz-x1> From: Auger Eric Message-ID: <8b4829a5-f0f4-d4c6-c47e-a6dfc182a283@redhat.com> Date: Tue, 24 Dec 2019 08:39:30 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101 Thunderbird/60.4.0 MIME-Version: 1.0 In-Reply-To: <20191210200110.GM3352@xz-x1> Content-Language: en-US X-Scanned-By: MIMEDefang 2.79 on 10.5.11.13 X-MC-Unique: CP2_L6rzNKWoMperVLFUlA-1 X-Mimecast-Spam-Score: 0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: 7bit X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 205.139.110.61 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 24 Dec 2019 07:39:59 -0000 Hi Peter, On 12/10/19 9:01 PM, Peter Xu wrote: > On Fri, Nov 22, 2019 at 07:29:41PM +0100, Eric Auger wrote: >> +static const VMStateDescription vmstate_virtio_iommu_device = { >> + .name = "virtio-iommu-device", >> + .minimum_version_id = 1, >> + .version_id = 1, >> + .post_load = iommu_post_load, >> + .fields = (VMStateField[]) { >> + VMSTATE_GTREE_DIRECT_KEY_V(domains, VirtIOIOMMU, 1, >> + &vmstate_domain, viommu_domain), >> + VMSTATE_GTREE_DIRECT_KEY_V(endpoints, VirtIOIOMMU, 1, >> + &vmstate_endpoint, viommu_endpoint), > > IIUC vmstate_domain already contains all the endpoint information (in > endpoint_list of vmstate_domain), but here we migrate it twice. I migrated both because at that time I considered we could have endpoints not attached to any domains but I think I can now simplify based on the fact any EP is attached. I > suppose that's why now we need reconstruct_ep_domain_link() to fixup > the duplicated migration? Even if I only migrate the domain gtree, I need to reconstruct the ep->domain which was not migrated, on purpose, as it pointed to the old domain in the origin. > > Then I'll instead ask whether we can skip migrating here? Then in > post_load we simply: > > foreach(domain) > foreach(endpoint in domain) > g_tree_insert(s->endpoints); > > It might help to avoid the reconstruct_ep_domain_link ugliness? I agree that it is simpler. Also need to update the ep->domain as mentionned above. Thank you for the suggestion. > > And besides, I also agree with Jean that the endpoint data structure > could be reused with IOMMUDevice somehow. As I replied to Jean, I think it makes sense to keep both structures as endpoints are not indexed by the same key and the bus number is resolved later. Thanks Eric > > Thanks, > From MAILER-DAEMON Tue Dec 24 02:40:08 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1ijenY-0000Lc-H2 for mharc-qemu-arm@gnu.org; Tue, 24 Dec 2019 02:40:08 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:56139) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ijenW-0000JS-EB for qemu-arm@nongnu.org; Tue, 24 Dec 2019 02:40:07 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ijenV-0002pC-1i for qemu-arm@nongnu.org; Tue, 24 Dec 2019 02:40:06 -0500 Received: from us-smtp-1.mimecast.com ([207.211.31.81]:59167 helo=us-smtp-delivery-1.mimecast.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1ijenU-0002op-Tf for qemu-arm@nongnu.org; Tue, 24 Dec 2019 02:40:04 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1577173204; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=j4NknF9ba4R5CHHAR6Mw5Q57fD8rHs5SRd5mZFYdoNU=; b=HYMZCPBTVC2dSohoT1835E/nmiiq7uYKCCQZj7GlnRpS4CLwYxykbuqBLxV0uKBYvs4OWi 92rTW12i1IkPMlUCSC1cnmb6a7lsqO34FmiC2IMN0ptwdkxCyQUytU2ZpKdPPXe18mMaNm vTfoWV95sqenKzxwJajbjWIp77ThywM= Received: from mimecast-mx01.redhat.com (mimecast-mx01.redhat.com [209.132.183.4]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-171-ayroffloNl-pgEI11xxYSw-1; Tue, 24 Dec 2019 02:40:03 -0500 Received: from smtp.corp.redhat.com (int-mx02.intmail.prod.int.phx2.redhat.com [10.5.11.12]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx01.redhat.com (Postfix) with ESMTPS id 934F7DB20; Tue, 24 Dec 2019 07:39:59 +0000 (UTC) Received: from [10.36.116.117] (ovpn-116-117.ams2.redhat.com [10.36.116.117]) by smtp.corp.redhat.com (Postfix) with ESMTPS id 2732160BE2; Tue, 24 Dec 2019 07:39:43 +0000 (UTC) Subject: Re: [PATCH for-5.0 v11 19/20] pc: Add support for virtio-iommu-pci To: Jean-Philippe Brucker Cc: eric.auger.pro@gmail.com, qemu-devel@nongnu.org, qemu-arm@nongnu.org, peter.maydell@linaro.org, mst@redhat.com, armbru@redhat.com, jean-philippe.brucker@arm.com, bharatb.linux@gmail.com, yang.zhong@intel.com, dgilbert@redhat.com, quintela@redhat.com, kevin.tian@intel.com, peterx@redhat.com, tnowicki@marvell.com References: <20191122182943.4656-1-eric.auger@redhat.com> <20191122182943.4656-20-eric.auger@redhat.com> <20191210165032.GQ277340@myrica> From: Auger Eric Message-ID: <336ecbf4-bcda-36a3-201f-d052da885ae2@redhat.com> Date: Tue, 24 Dec 2019 08:39:42 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101 Thunderbird/60.4.0 MIME-Version: 1.0 In-Reply-To: <20191210165032.GQ277340@myrica> Content-Language: en-US X-Scanned-By: MIMEDefang 2.79 on 10.5.11.12 X-MC-Unique: ayroffloNl-pgEI11xxYSw-1 X-Mimecast-Spam-Score: 0 Content-Type: text/plain; charset=windows-1252 Content-Transfer-Encoding: 7bit X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 207.211.31.81 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 24 Dec 2019 07:40:07 -0000 Hi Jean, On 12/10/19 5:50 PM, Jean-Philippe Brucker wrote: > On Fri, Nov 22, 2019 at 07:29:42PM +0100, Eric Auger wrote: >> The virtio-iommu-pci is instantiated through the -device QEMU >> option. However if instantiated it also requires an IORT ACPI table >> to describe the ID mappings between the root complex and the iommu. >> >> This patch adds the generation of the IORT table if the >> virtio-iommu-pci device is instantiated. >> >> We also declare the [0xfee00000 - 0xfeefffff] MSI reserved region >> so that it gets bypassed by the IOMMU. >> >> Signed-off-by: Eric Auger > > It would be nice to factor the IORT code with arm, but this looks OK. I factorized the iort table code generation. Not sure this will be used eventually but well. Thanks Eric > > Reviewed-by: Jean-Philippe Brucker > From MAILER-DAEMON Fri Dec 27 10:18:12 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1ikrNS-0002Rp-CB for mharc-qemu-arm@gnu.org; Fri, 27 Dec 2019 10:18:11 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:58013) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ikXJW-0006Yx-1o for qemu-arm@nongnu.org; Thu, 26 Dec 2019 12:52:47 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ikXJU-0008Aw-2x for qemu-arm@nongnu.org; Thu, 26 Dec 2019 12:52:45 -0500 Received: from viti.kaiser.cx ([2a01:238:43fe:e600:cd0c:bd4a:7a3:8e9f]:54334) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1ikXJT-00089H-TH; Thu, 26 Dec 2019 12:52:44 -0500 Received: from hsi-kbw-46-223-81-144.hsi.kabel-badenwuerttemberg.de ([46.223.81.144] helo=martin-debian-1.paytec.ch) by viti.kaiser.cx with esmtpsa (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.89) (envelope-from ) id 1ikXJM-0003GG-RE; Thu, 26 Dec 2019 18:52:37 +0100 From: Martin Kaiser To: Peter Maydell , Jean-Christophe Dubois , Peter Chubb Cc: qemu-arm@nongnu.org, qemu-devel@nongnu.org, Martin Kaiser Subject: [PATCH] i.MX: add an emulation for RNGC Date: Thu, 26 Dec 2019 18:51:32 +0100 Message-Id: <20191226175132.28116-1-martin@kaiser.cx> X-Mailer: git-send-email 2.11.0 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 2a01:238:43fe:e600:cd0c:bd4a:7a3:8e9f X-Mailman-Approved-At: Fri, 27 Dec 2019 10:18:07 -0500 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 26 Dec 2019 17:52:48 -0000 Add an emulation for the RNGC random number generator and the compatible RNGB variant. These peripherals are included (at least) in imx25 and imx35 chipsets. The emulation supports the initial self test, reseeding the prng and reading random numbers. Signed-off-by: Martin Kaiser --- hw/arm/fsl-imx25.c | 11 ++ hw/misc/Makefile.objs | 1 + hw/misc/imx_rngc.c | 262 +++++++++++++++++++++++++++++++++++++++++++++ include/hw/arm/fsl-imx25.h | 5 + include/hw/misc/imx_rngc.h | 36 +++++++ 5 files changed, 315 insertions(+) create mode 100644 hw/misc/imx_rngc.c create mode 100644 include/hw/misc/imx_rngc.h diff --git a/hw/arm/fsl-imx25.c b/hw/arm/fsl-imx25.c index 3cb5a8fdfd..da3471b395 100644 --- a/hw/arm/fsl-imx25.c +++ b/hw/arm/fsl-imx25.c @@ -62,6 +62,9 @@ static void fsl_imx25_init(Object *obj) sysbus_init_child_obj(obj, "fec", &s->fec, sizeof(s->fec), TYPE_IMX_FEC); + sysbus_init_child_obj(obj, "rngc", &s->rngc, sizeof(s->rngc), + TYPE_IMX_RNGC); + for (i = 0; i < FSL_IMX25_NUM_I2CS; i++) { sysbus_init_child_obj(obj, "i2c[*]", &s->i2c[i], sizeof(s->i2c[i]), TYPE_IMX_I2C); @@ -188,6 +191,14 @@ static void fsl_imx25_realize(DeviceState *dev, Error **errp) sysbus_connect_irq(SYS_BUS_DEVICE(&s->fec), 0, qdev_get_gpio_in(DEVICE(&s->avic), FSL_IMX25_FEC_IRQ)); + object_property_set_bool(OBJECT(&s->rngc), true, "realized", &err); + if (err) { + error_propagate(errp, err); + return; + } + sysbus_mmio_map(SYS_BUS_DEVICE(&s->rngc), 0, FSL_IMX25_RNGC_ADDR); + sysbus_connect_irq(SYS_BUS_DEVICE(&s->rngc), 0, + qdev_get_gpio_in(DEVICE(&s->avic), FSL_IMX25_RNGC_IRQ)); /* Initialize all I2C */ for (i = 0; i < FSL_IMX25_NUM_I2CS; i++) { diff --git a/hw/misc/Makefile.objs b/hw/misc/Makefile.objs index ba898a5781..2b28f8c096 100644 --- a/hw/misc/Makefile.objs +++ b/hw/misc/Makefile.objs @@ -42,6 +42,7 @@ common-obj-$(CONFIG_IMX) += imx7_ccm.o common-obj-$(CONFIG_IMX) += imx2_wdt.o common-obj-$(CONFIG_IMX) += imx7_snvs.o common-obj-$(CONFIG_IMX) += imx7_gpr.o +common-obj-$(CONFIG_IMX) += imx_rngc.o common-obj-$(CONFIG_MILKYMIST) += milkymist-hpdmc.o common-obj-$(CONFIG_MILKYMIST) += milkymist-pfpu.o common-obj-$(CONFIG_MAINSTONE) += mst_fpga.o diff --git a/hw/misc/imx_rngc.c b/hw/misc/imx_rngc.c new file mode 100644 index 0000000000..f935ec46a6 --- /dev/null +++ b/hw/misc/imx_rngc.c @@ -0,0 +1,262 @@ +/* + * Freescale i.MX RNGC emulation + * + * Copyright (C) 2019 Martin Kaiser + * + * This work is licensed under the terms of the GNU GPL, version 2 or later. + * See the COPYING file in the top-level directory. + * + * This driver provides the minimum functionality to initialize and seed + * an rngc and to read random numbers. The rngb that is found in imx25 + * chipsets is also supported. + */ + + +#include "qemu/osdep.h" +#include "qemu/main-loop.h" +#include "qemu/module.h" +#include "qemu/log.h" +#include "qemu/guest-random.h" +#include "hw/irq.h" +#include "hw/misc/imx_rngc.h" + +#define RNGC_VER_ID 0x00 +#define RNGC_COMMAND 0x04 +#define RNGC_CONTROL 0x08 +#define RNGC_STATUS 0x0C +#define RNGC_FIFO 0x14 + +/* These version info are reported by the rngb in an imx258 chip. */ +#define RNG_TYPE_RNGB 0x1 +#define V_MAJ 0x2 +#define V_MIN 0x40 + +#define RNGC_CMD_BIT_SW_RST 0x40 +#define RNGC_CMD_BIT_CLR_ERR 0x20 +#define RNGC_CMD_BIT_CLR_INT 0x10 +#define RNGC_CMD_BIT_SEED 0x02 +#define RNGC_CMD_BIT_SELF_TEST 0x01 + +#define RNGC_CTRL_BIT_MASK_ERR 0x40 +#define RNGC_CTRL_BIT_MASK_DONE 0x20 +#define RNGC_CTRL_BIT_AUTO_SEED 0x10 + +/* the current status for self-test and seed operations */ +#define OP_IDLE 0 +#define OP_RUN 1 +#define OP_DONE 2 + +static uint64_t imx_rngc_read(void *opaque, hwaddr offset, unsigned size) +{ + IMXRNGCState *s = IMX_RNGC(opaque); + uint64_t val = 0; + + switch (offset) { + case RNGC_VER_ID: + val |= RNG_TYPE_RNGB << 28 | V_MAJ << 8 | V_MIN; + break; + + case RNGC_COMMAND: + if (s->op_seed == OP_RUN) { + val |= RNGC_CMD_BIT_SEED; + } + if (s->op_self_test == OP_RUN) { + val |= RNGC_CMD_BIT_SELF_TEST; + } + break; + + case RNGC_CONTROL: + /* + * The CTL_ACC and VERIF_MODE bits are not supported yet. + * They read as 0. + */ + val |= s->mask; + if (s->auto_seed) { + val |= RNGC_CTRL_BIT_AUTO_SEED; + } + /* + * We don't have an internal fifo like the real hardware. + * There's no need for strategy to handle fifo underflows. + * We return the FIFO_UFLOW_RESPONSE bits as 0. + */ + break; + + case RNGC_STATUS: + /* + * We never report any statistics test or self-test errors or any + * other errors. STAT_TEST_PF, ST_PF and ERROR are always 0. + */ + + /* + * We don't have an internal fifo, see above. Therefore, we + * report back the default fifo size (5 32-bit words) and + * indicate that our fifo is always full. + */ + val |= 5 << 12 | 5 << 8; + + /* We always have a new seed available. */ + val |= 1 << 6; + + if (s->op_seed == OP_DONE) { + val |= 1 << 5; + } + if (s->op_self_test == OP_DONE) { + val |= 1 << 4; + } + if (s->op_seed == OP_RUN || s->op_self_test == OP_RUN) { + /* + * We're busy if self-test is running or if we're + * seeding the prng. + */ + val |= 1 << 1; + } else { + /* + * We're ready to provide secure random numbers whenever + * we're not busy. + */ + val |= 1; + } + break; + + case RNGC_FIFO: + qemu_guest_getrandom_nofail(&val, sizeof(val)); + break; + } + + return val; +} + +static void __imx_rngc_reset(IMXRNGCState *s) +{ + s->op_self_test = OP_IDLE; + s->op_seed = OP_IDLE; + s->mask = 0; + s->auto_seed = false; +} + +static void imx_rngc_write(void *opaque, hwaddr offset, uint64_t value, + unsigned size) +{ + IMXRNGCState *s = IMX_RNGC(opaque); + + switch (offset) { + case RNGC_COMMAND: + if (value & RNGC_CMD_BIT_SW_RST) { + __imx_rngc_reset(s); + } + + /* + * For now, both CLR_ERR and CLR_INT clear the interrupt. We + * don't report any erors yet. + */ + if (value & (RNGC_CMD_BIT_CLR_ERR | RNGC_CMD_BIT_CLR_INT)) { + qemu_irq_lower(s->irq); + } + + if (value & RNGC_CMD_BIT_SEED) { + s->op_seed = OP_RUN; + qemu_bh_schedule(s->seed_bh); + } + + if (value & RNGC_CMD_BIT_SELF_TEST) { + s->op_self_test = OP_RUN; + qemu_bh_schedule(s->self_test_bh); + } + break; + + case RNGC_CONTROL: + /* + * The CTL_ACC and VERIF_MODE bits are not supported yet. + * We ignore them if they're set by the caller. + */ + + if (value & RNGC_CTRL_BIT_MASK_ERR) { + s->mask |= RNGC_CTRL_BIT_MASK_ERR; + } else { + s->mask &= ~RNGC_CTRL_BIT_MASK_ERR; + } + + if (value & RNGC_CTRL_BIT_MASK_DONE) { + s->mask |= RNGC_CTRL_BIT_MASK_DONE; + } else { + s->mask &= ~RNGC_CTRL_BIT_MASK_DONE; + } + + if (value & RNGC_CTRL_BIT_AUTO_SEED) { + s->auto_seed = true; + } else { + s->auto_seed = false; + } + break; + } +} + +static const MemoryRegionOps imx_rngc_ops = { + .read = imx_rngc_read, + .write = imx_rngc_write, + .endianness = DEVICE_NATIVE_ENDIAN, +}; + +static void imx_rngc_self_test(void *opaque) +{ + IMXRNGCState *s = IMX_RNGC(opaque); + + s->op_self_test = OP_DONE; + if (!(s->mask & RNGC_CTRL_BIT_MASK_DONE)) { + qemu_irq_raise(s->irq); + } +} + +static void imx_rngc_seed(void *opaque) +{ + IMXRNGCState *s = IMX_RNGC(opaque); + + s->op_seed = OP_DONE; + if (!(s->mask & RNGC_CTRL_BIT_MASK_DONE)) { + qemu_irq_raise(s->irq); + } +} + +static void imx_rngc_realize(DeviceState *dev, Error **errp) +{ + IMXRNGCState *s = IMX_RNGC(dev); + SysBusDevice *sbd = SYS_BUS_DEVICE(dev); + + memory_region_init_io(&s->iomem, OBJECT(s), &imx_rngc_ops, s, + TYPE_IMX_RNGC, 0x1000); + sysbus_init_mmio(sbd, &s->iomem); + + sysbus_init_irq(sbd, &s->irq); + s->self_test_bh = qemu_bh_new(imx_rngc_self_test, s); + s->seed_bh = qemu_bh_new(imx_rngc_seed, s); +} + +static void imx_rngc_reset(DeviceState *dev) +{ + IMXRNGCState *s = IMX_RNGC(dev); + + __imx_rngc_reset(s); +} + +static void imx_rngc_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + + dc->realize = imx_rngc_realize; + dc->reset = imx_rngc_reset; + dc->desc = "i.MX RNGC"; +} + +static const TypeInfo imx_rngc_info = { + .name = TYPE_IMX_RNGC, + .parent = TYPE_SYS_BUS_DEVICE, + .instance_size = sizeof(IMXRNGCState), + .class_init = imx_rngc_class_init, +}; + +static void imx_rngc_register_types(void) +{ + type_register_static(&imx_rngc_info); +} + +type_init(imx_rngc_register_types) diff --git a/include/hw/arm/fsl-imx25.h b/include/hw/arm/fsl-imx25.h index 241efb52ae..1c86bb55fb 100644 --- a/include/hw/arm/fsl-imx25.h +++ b/include/hw/arm/fsl-imx25.h @@ -24,6 +24,7 @@ #include "hw/timer/imx_gpt.h" #include "hw/timer/imx_epit.h" #include "hw/net/imx_fec.h" +#include "hw/misc/imx_rngc.h" #include "hw/i2c/imx_i2c.h" #include "hw/gpio/imx_gpio.h" #include "exec/memory.h" @@ -50,6 +51,7 @@ typedef struct FslIMX25State { IMXGPTState gpt[FSL_IMX25_NUM_GPTS]; IMXEPITState epit[FSL_IMX25_NUM_EPITS]; IMXFECState fec; + IMXRNGCState rngc; IMXI2CState i2c[FSL_IMX25_NUM_I2CS]; IMXGPIOState gpio[FSL_IMX25_NUM_GPIOS]; MemoryRegion rom[2]; @@ -211,6 +213,8 @@ typedef struct FslIMX25State { #define FSL_IMX25_GPIO4_SIZE 0x4000 #define FSL_IMX25_GPIO3_ADDR 0x53FA4000 #define FSL_IMX25_GPIO3_SIZE 0x4000 +#define FSL_IMX25_RNGC_ADDR 0x53FB0000 +#define FSL_IMX25_RNGC_SIZE 0x4000 #define FSL_IMX25_GPIO1_ADDR 0x53FCC000 #define FSL_IMX25_GPIO1_SIZE 0x4000 #define FSL_IMX25_GPIO2_ADDR 0x53FD0000 @@ -238,6 +242,7 @@ typedef struct FslIMX25State { #define FSL_IMX25_EPIT1_IRQ 28 #define FSL_IMX25_EPIT2_IRQ 27 #define FSL_IMX25_FEC_IRQ 57 +#define FSL_IMX25_RNGC_IRQ 22 #define FSL_IMX25_I2C1_IRQ 3 #define FSL_IMX25_I2C2_IRQ 4 #define FSL_IMX25_I2C3_IRQ 10 diff --git a/include/hw/misc/imx_rngc.h b/include/hw/misc/imx_rngc.h new file mode 100644 index 0000000000..43e0bc1323 --- /dev/null +++ b/include/hw/misc/imx_rngc.h @@ -0,0 +1,36 @@ +/* + * Freescale i.MX RNGC emulation + * + * Copyright (C) 2019 Martin Kaiser + * + * This work is licensed under the terms of the GNU GPL, version 2 or later. + * See the COPYING file in the top-level directory. + */ + +#ifndef IMX_RNGC_H +#define IMX_RNGC_H + +#include "hw/sysbus.h" + +#define TYPE_IMX_RNGC "imx.rngc" +#define IMX_RNGC(obj) OBJECT_CHECK(IMXRNGCState, (obj), TYPE_IMX_RNGC) + +typedef struct IMXRNGCState { + /*< private >*/ + SysBusDevice parent_obj; + + /*< public >*/ + MemoryRegion iomem; + + uint8_t op_self_test; + uint8_t op_seed; + uint8_t mask; + bool auto_seed; + + QEMUBH *self_test_bh; + QEMUBH *seed_bh; + qemu_irq irq; +} IMXRNGCState; + + +#endif /* IMX_RNGC_H */ -- 2.11.0 From MAILER-DAEMON Sat Dec 28 21:55:23 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1ilOjj-0000B4-Rk for mharc-qemu-arm@gnu.org; Sat, 28 Dec 2019 21:55:23 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:52992) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ilOjh-0000Ab-IK for qemu-arm@nongnu.org; Sat, 28 Dec 2019 21:55:22 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ilOjf-0000yd-SI for qemu-arm@nongnu.org; Sat, 28 Dec 2019 21:55:21 -0500 Received: from mail-pl1-x632.google.com ([2607:f8b0:4864:20::632]:42609) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ilOjf-0000vu-M5 for qemu-arm@nongnu.org; Sat, 28 Dec 2019 21:55:19 -0500 Received: by mail-pl1-x632.google.com with SMTP id p9so13332908plk.9 for ; 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[194.223.58.9]) by smtp.gmail.com with ESMTPSA id t187sm45508694pfd.21.2019.12.28.18.55.15 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Sat, 28 Dec 2019 18:55:17 -0800 (PST) Subject: Re: [PATCH v2 5/5] tests/tcg: add user version of dumb-as-bricks semiconsole test To: =?UTF-8?Q?Alex_Benn=c3=a9e?= , qemu-devel@nongnu.org Cc: Peter Maydell , keithp@keithp.com, "open list:ARM TCG CPUs" References: <20191220132246.6759-1-alex.bennee@linaro.org> <20191220132246.6759-6-alex.bennee@linaro.org> From: Richard Henderson Message-ID: <09322c6e-74d9-08d0-1138-f2d5581a7244@linaro.org> Date: Sun, 29 Dec 2019 13:55:12 +1100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.2.2 MIME-Version: 1.0 In-Reply-To: <20191220132246.6759-6-alex.bennee@linaro.org> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 8bit X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::632 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sun, 29 Dec 2019 02:55:22 -0000 On 12/21/19 12:22 AM, Alex Bennée wrote: > +#if defined(__arm__) > + register uintptr_t t asm("r0") = type; > + register uintptr_t a0 asm("r1") = arg0; > + asm("svc 0xab" > + : "=r" (t) > + : "r" (t), "r" (a0)); This is the #ifdef __thumb__ svc code. Are you enforcing that with command-line arguments? Might as well fix this, then test both arm and thumb. r~ From MAILER-DAEMON Sat Dec 28 21:57:37 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1ilOlt-0001Bx-Cr for mharc-qemu-arm@gnu.org; Sat, 28 Dec 2019 21:57:37 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:57556) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ilOlr-0001Bk-89 for qemu-arm@nongnu.org; Sat, 28 Dec 2019 21:57:36 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ilOlq-0007Ol-Ap for qemu-arm@nongnu.org; Sat, 28 Dec 2019 21:57:35 -0500 Received: from mail-pl1-x644.google.com ([2607:f8b0:4864:20::644]:38818) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ilOlq-0007Ma-5j for qemu-arm@nongnu.org; Sat, 28 Dec 2019 21:57:34 -0500 Received: by mail-pl1-x644.google.com with SMTP id f20so13342847plj.5 for ; Sat, 28 Dec 2019 18:57:34 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=subject:to:cc:references:from:message-id:date:user-agent :mime-version:in-reply-to:content-language:content-transfer-encoding; bh=yLaqwPIFuNuKqoOfcXmFF2FZpBhCNI7L5ivEi70Tx7A=; b=NbA0oMwyNZ+xHiqx6KaWXfxDiL+pOlrQaZiXHwVeym3kJzJFrKbLErxhcRKN5lnWwQ pu36YjNLL/9jjXLwB0yRA7HPW2AK1G5TJxE20vcLRVBsCOLm7iqI5VbEctvNdZVwukrA tKUJrGKmNdGdlw1izmxlYjtYAP5w1viZr7XVSPz/KiQ+rG7ROmv+UIwpI1Lcq2/q9/61 kkAuXipaTjXcsUzYpwQfiKRbBrorAK6eBEfb10a794gVrLnz5nHZgdz+SpTQor0+R1wR ePugyLpAxwR7J/ymPr8kZQimGyzyJOUiCz8ELa7zQkro0TtyKB3tTtiz7HGkrWxwifLT A+3Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:subject:to:cc:references:from:message-id:date :user-agent:mime-version:in-reply-to:content-language :content-transfer-encoding; bh=yLaqwPIFuNuKqoOfcXmFF2FZpBhCNI7L5ivEi70Tx7A=; b=a3YcKbkaNY1fnO0Bxq9k57Nl/3IWCZ8CnkCEplvnxpH5P8xVXr4gssOhZmnEFBbjc2 CMVUfSCjVVQnQeNaUvbpsKET6LyhQybdT2CeEIwe4fvSVKAdwCfnW/ZZ8mZowAs4VvD8 FMK3L1SWZlS/0FGzjeU/Ljxp7i1a0Zx0tSuakWHdrJ5NCqUgfw1BzCUi0/NdIWC5N3No yHisUwN6Yt4VPeJuojnUt1G5RZXIDTF+WJMXGrQhKl4Zr36l1y0NMraJKy2d0Nj/9q68 r3fe0bEi5LFqtAPTrOKKILJSOLLNiJQTCHI/gGzCeAYzoezo5bm0sc2mqIDyW3Tr3rox RQ7A== X-Gm-Message-State: APjAAAXNl9XYNeCtpzpFH54rjdM8e53I6Av0Nv2v24XuLSDCVyBTd8XW /fZplrQ9OHbnbf/7P7LY4qKZ3rBRxr0N5A== X-Google-Smtp-Source: APXvYqwHLFGBtdQq3j/i+kaQWDuhG9WqLrDYK3G6uy+PcAqmC0j/2qwGQruwkABv4sH3+ivN+2VuJQ== X-Received: by 2002:a17:902:760e:: with SMTP id k14mr62031009pll.238.1577588252927; Sat, 28 Dec 2019 18:57:32 -0800 (PST) Received: from [192.168.1.118] (194-223-58-9.tpgi.com.au. [194.223.58.9]) by smtp.gmail.com with ESMTPSA id q15sm42618719pgi.55.2019.12.28.18.57.29 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Sat, 28 Dec 2019 18:57:32 -0800 (PST) Subject: Re: [PATCH v2 4/5] tests/tcg: add a dumb-as-bricks semihosting console test To: =?UTF-8?Q?Alex_Benn=c3=a9e?= , qemu-devel@nongnu.org Cc: keithp@keithp.com, Peter Maydell , "open list:ARM TCG CPUs" References: <20191220132246.6759-1-alex.bennee@linaro.org> <20191220132246.6759-5-alex.bennee@linaro.org> From: Richard Henderson Message-ID: <557f36ea-159f-ebb2-b7aa-e96b0844e1ae@linaro.org> Date: Sun, 29 Dec 2019 13:57:26 +1100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.2.2 MIME-Version: 1.0 In-Reply-To: <20191220132246.6759-5-alex.bennee@linaro.org> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 8bit X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::644 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sun, 29 Dec 2019 02:57:36 -0000 On 12/21/19 12:22 AM, Alex Bennée wrote: > We don't run this during check-tcg as we would need to check stuff is > echoed back. However we can still build the binary so people can test > it manually. > > Signed-off-by: Alex Bennée > Reviewed-by: Richard Henderson > > --- > v8 > - actually return the result! > --- > tests/tcg/aarch64/system/semiconsole.c | 38 +++++++++++++++++++++++ > tests/tcg/aarch64/Makefile.softmmu-target | 9 +++++- > 2 files changed, 46 insertions(+), 1 deletion(-) > create mode 100644 tests/tcg/aarch64/system/semiconsole.c There probably is a way to easily test this with python, but I don't want to write that script either, so. Reviewed-by: Richard Henderson :-) r~ From MAILER-DAEMON Sat Dec 28 21:58:27 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1ilOmh-0001t6-IQ for mharc-qemu-arm@gnu.org; Sat, 28 Dec 2019 21:58:27 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:59223) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ilOmf-0001qq-6R for qemu-arm@nongnu.org; Sat, 28 Dec 2019 21:58:26 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ilOme-0000iY-4O for qemu-arm@nongnu.org; Sat, 28 Dec 2019 21:58:25 -0500 Received: from mail-pj1-x1043.google.com ([2607:f8b0:4864:20::1043]:36035) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ilOmd-0000gS-Tk for qemu-arm@nongnu.org; Sat, 28 Dec 2019 21:58:24 -0500 Received: by mail-pj1-x1043.google.com with SMTP id n59so6710724pjb.1 for ; Sat, 28 Dec 2019 18:58:23 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=subject:to:cc:references:from:message-id:date:user-agent :mime-version:in-reply-to:content-language:content-transfer-encoding; bh=sKTtw6iLCBEzEWlSLDwQfYCTUbvbbN6mdX1NAs6ay7c=; b=H70OHFsrftMWCZ+UDyLDurr+aPNwErsai9BBFaX7OZuBVJHeCw+YhsseNa5qig4qul My0e593G5MjbbDkLwwQloDRfWc+3JiehgSohGtCNBR2nWZnWxWEaUvecQko5aMs3Yexv z2e2Vt4EdGebmCa0BH6ctK9zDDOjbatoG4DD2BLPjhRwauYxM1kr248IeiYMKIyQbObN 9X4/tP2/XwqCX/a5Ymz65w8CnV4FSGPEXN90wnIsVmf+Bk5b8p/nfazfoMp3Jy41KuwL HF2N0pfvX3C0rwWaMZ+/3+37gmORQ1FmcUJRat1GvYV7t+YFh60Yvwdt1aGGTCTj+B43 MO7Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:subject:to:cc:references:from:message-id:date :user-agent:mime-version:in-reply-to:content-language :content-transfer-encoding; bh=sKTtw6iLCBEzEWlSLDwQfYCTUbvbbN6mdX1NAs6ay7c=; b=tj/v8W6RZ8xtg3t+shXQsF70PBl9vE/w6BBUFvt8/X6xn1hp+jaywmjj9Ok9QVpVed h2FraGXFei2LzRAzqUaCGjtqFkglf8tscbIo2JtPIfvZIpxPBMBRjPrJdIy8pzcHzDVy pk1DW0MG8PQM53Xr47dyklnESj2bLpUiWKYDUJZp7dUhEIcE78oGVRhs/CodeWFXDUWQ bvC38g1zDmCpNEKZakEpQan1wNvUPYWTG+bi2iwwuXrjlJWlvyiVFpHWm0aPehYVTi03 oZyI20UHMICUUf6oJTFtvH9W6BZ0J/jsU6EaC8kxhx3LXEoV3YJL+ZZ9CNCDK+otEoUX 3P3A== X-Gm-Message-State: APjAAAXmQcxNCBjT4b54W1kN32r4JcoRA4OQYeVZeNoc92TOisSPnLip c+E0oByBFyxGoNGqkXFOqkSPS+rz9QPFnQ== X-Google-Smtp-Source: APXvYqwZX7YM1CM5Aw6RCoQfQjKAHAnIC3xDHjYOmV0bqMLkst+9ANruVM+de+7AdO65vBs5ufcyyg== X-Received: by 2002:a17:90a:aa84:: with SMTP id l4mr36952343pjq.143.1577588303071; Sat, 28 Dec 2019 18:58:23 -0800 (PST) Received: from [192.168.1.118] (194-223-58-9.tpgi.com.au. [194.223.58.9]) by smtp.gmail.com with ESMTPSA id x11sm44613813pfn.53.2019.12.28.18.58.17 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Sat, 28 Dec 2019 18:58:22 -0800 (PST) Subject: Re: [PATCH v2 3/5] semihosting: add qemu_semihosting_console_inc for SYS_READC To: =?UTF-8?Q?Alex_Benn=c3=a9e?= , qemu-devel@nongnu.org Cc: Peter Maydell , keithp@keithp.com, Riku Voipio , Laurent Vivier , "open list:ARM TCG CPUs" , Paolo Bonzini References: <20191220132246.6759-1-alex.bennee@linaro.org> <20191220132246.6759-4-alex.bennee@linaro.org> From: Richard Henderson Message-ID: Date: Sun, 29 Dec 2019 13:58:15 +1100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.2.2 MIME-Version: 1.0 In-Reply-To: <20191220132246.6759-4-alex.bennee@linaro.org> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 8bit X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::1043 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sun, 29 Dec 2019 02:58:26 -0000 On 12/21/19 12:22 AM, Alex Bennée wrote: > From: Keith Packard > > Provides a blocking call to read a character from the console using > semihosting.chardev, if specified. This takes some careful command > line options to use stdio successfully as the serial ports, monitor > and semihost all want to use stdio. Here's a sample set of command > line options which share stdio between semihost, monitor and serial > ports: > > qemu \ > -chardev stdio,mux=on,id=stdio0 \ > -serial chardev:stdio0 \ > -semihosting-config enable=on,chardev=stdio0 \ > -mon chardev=stdio0,mode=readline > > This creates a chardev hooked to stdio and then connects all of the > subsystems to it. A shorter mechanism would be good to hear about. > > Signed-off-by: Keith Packard > Message-Id: <20191104204230.12249-1-keithp@keithp.com> > [AJB: fixed up deadlock, minor commit title reword] > Signed-off-by: Alex Bennée > Cc: Paolo Bonzini > Reviewed-by: Keith Packard > Tested-by: Keith Packard Reviewed-by: Richard Henderson r~ From MAILER-DAEMON Mon Dec 30 04:09:37 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1ilr3Q-0006Ib-VY for mharc-qemu-arm@gnu.org; Mon, 30 Dec 2019 04:09:36 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:46161) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ilr3N-0006Hc-UE for qemu-arm@nongnu.org; Mon, 30 Dec 2019 04:09:35 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ilr3L-0008OP-SG for qemu-arm@nongnu.org; Mon, 30 Dec 2019 04:09:33 -0500 Received: from us-smtp-delivery-1.mimecast.com ([205.139.110.120]:34570 helo=us-smtp-1.mimecast.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1ilr3L-0008NY-Bk for qemu-arm@nongnu.org; Mon, 30 Dec 2019 04:09:31 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1577696970; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding; bh=YdbmsnBhJ0g5NW+3S/cmQT+u1hJcl4/8moRbY7Q0gaI=; b=afanjB2UWoyNZbQW8WdxO054KPeD7UARQXyuEg1ma9weKO1SJPaRiN1L/Y2llU5GQTZ00/ Lv+79pfWhv4R4+iJjDPiaQ2ZeLkEHDShjDFwKIxs7iJPg4HPa10zlWiGOkAjMTXrKztgi0 lH+2+plioH5tt3eeNmxBvcqLHA4cbqw= Received: from mimecast-mx01.redhat.com (mimecast-mx01.redhat.com [209.132.183.4]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-374-kj3syISaMd2KuTUr17DQFA-1; Mon, 30 Dec 2019 04:09:28 -0500 Received: from smtp.corp.redhat.com (int-mx07.intmail.prod.int.phx2.redhat.com [10.5.11.22]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx01.redhat.com (Postfix) with ESMTPS id E7DC3800EBF; Mon, 30 Dec 2019 09:09:22 +0000 (UTC) Received: from x1w.redhat.com (ovpn-116-185.ams2.redhat.com [10.36.116.185]) by smtp.corp.redhat.com (Postfix) with ESMTPS id 537D21036D1B; Mon, 30 Dec 2019 09:09:02 +0000 (UTC) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org, Markus Armbruster , Richard Henderson Cc: Aurelien Jarno , qemu-ppc@nongnu.org, Peter Maydell , Riku Voipio , Aleksandar Rikalo , Andrzej Zaborowski , Laurent Vivier , Paolo Bonzini , Max Filippov , Claudio Fontana , qemu-s390x@nongnu.org, Sagar Karandikar , Marek Vasut , Artyom Tarasenko , Chris Wulff , Bastian Koppelmann , Cornelia Huck , Palmer Dabbelt , Stefan Weil , Richard Henderson , qemu-arm@nongnu.org, "Edgar E. Iglesias" , Mark Cave-Ayland , David Hildenbrand , Anthony Green , Eduardo Habkost , Alistair Francis , Stafford Horne , Guan Xuetao , Michael Walle , Aleksandar Markovic , David Gibson , qemu-riscv@nongnu.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH 0/2] tcg: Include tcg files using tcg/ dirname, reduce cpp search path list Date: Mon, 30 Dec 2019 10:08:58 +0100 Message-Id: <20191230090900.446-1-philmd@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.84 on 10.5.11.22 X-MC-Unique: kj3syISaMd2KuTUr17DQFA-1 X-Mimecast-Spam-Score: 0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 205.139.110.120 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 30 Dec 2019 09:09:35 -0000 Noticed we could clean this while reviewing Richard patch last night: https://www.mail-archive.com/qemu-devel@nongnu.org/msg667606.html Philippe Mathieu-Daud=C3=A9 (2): tcg: Search includes from the project root source directory configure: Remove tcg/ from the preprocessor include search list configure | 1 - include/exec/cpu_ldst.h | 2 +- tcg/i386/tcg-target.h | 2 +- tcg/tcg-op.h | 2 +- tcg/tcg.h | 4 ++-- accel/tcg/cpu-exec.c | 2 +- accel/tcg/tcg-runtime-gvec.c | 2 +- accel/tcg/translate-all.c | 2 +- accel/tcg/user-exec.c | 2 +- bsd-user/main.c | 2 +- cpus.c | 2 +- exec.c | 2 +- linux-user/main.c | 2 +- target/alpha/translate.c | 2 +- target/arm/helper-a64.c | 2 +- target/arm/translate-a64.c | 4 ++-- target/arm/translate-sve.c | 6 +++--- target/arm/translate.c | 4 ++-- target/cris/translate.c | 2 +- target/hppa/translate.c | 2 +- target/i386/mem_helper.c | 2 +- target/i386/translate.c | 2 +- target/lm32/translate.c | 2 +- target/m68k/translate.c | 2 +- target/microblaze/translate.c | 2 +- target/mips/translate.c | 2 +- target/moxie/translate.c | 2 +- target/nios2/translate.c | 2 +- target/openrisc/translate.c | 2 +- target/ppc/mem_helper.c | 2 +- target/ppc/translate.c | 4 ++-- target/riscv/cpu_helper.c | 2 +- target/riscv/translate.c | 2 +- target/s390x/translate.c | 4 ++-- target/sh4/translate.c | 2 +- target/sparc/ldst_helper.c | 2 +- target/sparc/translate.c | 2 +- target/tilegx/translate.c | 2 +- target/tricore/translate.c | 2 +- target/unicore32/translate.c | 2 +- target/xtensa/translate.c | 2 +- tcg/aarch64/tcg-target.inc.c | 4 ++-- tcg/arm/tcg-target.inc.c | 4 ++-- tcg/i386/tcg-target.inc.c | 4 ++-- tcg/mips/tcg-target.inc.c | 2 +- tcg/optimize.c | 2 +- tcg/ppc/tcg-target.inc.c | 4 ++-- tcg/riscv/tcg-target.inc.c | 4 ++-- tcg/s390/tcg-target.inc.c | 4 ++-- tcg/sparc/tcg-target.inc.c | 2 +- tcg/tcg-common.c | 2 +- tcg/tcg-op-gvec.c | 8 ++++---- tcg/tcg-op-vec.c | 6 +++--- tcg/tcg-op.c | 6 +++--- tcg/tcg.c | 2 +- tcg/tci.c | 2 +- 56 files changed, 75 insertions(+), 76 deletions(-) --=20 2.21.0 From MAILER-DAEMON Mon Dec 30 04:09:52 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1ilr3f-0006fp-Ry for mharc-qemu-arm@gnu.org; Mon, 30 Dec 2019 04:09:51 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:46235) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ilr3b-0006aW-3k for qemu-arm@nongnu.org; Mon, 30 Dec 2019 04:09:50 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ilr3X-00005v-QY for qemu-arm@nongnu.org; Mon, 30 Dec 2019 04:09:47 -0500 Received: from us-smtp-2.mimecast.com ([205.139.110.61]:50103 helo=us-smtp-delivery-1.mimecast.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1ilr3X-00005K-K5 for qemu-arm@nongnu.org; Mon, 30 Dec 2019 04:09:43 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1577696983; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=vOvzVhf78WO8VfJkjB3Re+89JSBGc4Plztfnfs+bDbM=; b=UVpKZBJxduA8WxMZUCjR1887P7kPt6NQVWtahcevs81ohhD3KGsR/dGt3StK9xLZpa0H4K BUGuuF9hh0FEAmbg/Uj93Du2GzR2TU7Gcmgcz314Wl0CLu6ZXBofayHxymDoxVb0+FoZHm 6CRbPa3G5vsw7pT5cPpKZvi1o49Ak5g= Received: from mimecast-mx01.redhat.com (mimecast-mx01.redhat.com [209.132.183.4]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-428-7S9MT5LfNUO9CvEvMgtnWA-1; Mon, 30 Dec 2019 04:09:40 -0500 Received: from smtp.corp.redhat.com (int-mx07.intmail.prod.int.phx2.redhat.com [10.5.11.22]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx01.redhat.com (Postfix) with ESMTPS id A8675107ACC7; Mon, 30 Dec 2019 09:09:36 +0000 (UTC) Received: from x1w.redhat.com (ovpn-116-185.ams2.redhat.com [10.36.116.185]) by smtp.corp.redhat.com (Postfix) with ESMTPS id AF32D1081325; Mon, 30 Dec 2019 09:09:23 +0000 (UTC) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org, Markus Armbruster , Richard Henderson Cc: Aurelien Jarno , qemu-ppc@nongnu.org, Peter Maydell , Riku Voipio , Aleksandar Rikalo , Andrzej Zaborowski , Laurent Vivier , Paolo Bonzini , Max Filippov , Claudio Fontana , qemu-s390x@nongnu.org, Sagar Karandikar , Marek Vasut , Artyom Tarasenko , Chris Wulff , Bastian Koppelmann , Cornelia Huck , Palmer Dabbelt , Stefan Weil , Richard Henderson , qemu-arm@nongnu.org, "Edgar E. Iglesias" , Mark Cave-Ayland , David Hildenbrand , Anthony Green , Eduardo Habkost , Alistair Francis , Stafford Horne , Guan Xuetao , Michael Walle , Aleksandar Markovic , David Gibson , qemu-riscv@nongnu.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH 1/2] tcg: Search includes from the project root source directory Date: Mon, 30 Dec 2019 10:08:59 +0100 Message-Id: <20191230090900.446-2-philmd@redhat.com> In-Reply-To: <20191230090900.446-1-philmd@redhat.com> References: <20191230090900.446-1-philmd@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.84 on 10.5.11.22 X-MC-Unique: 7S9MT5LfNUO9CvEvMgtnWA-1 X-Mimecast-Spam-Score: 0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 205.139.110.61 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 30 Dec 2019 09:09:50 -0000 We currently search both the root and the tcg/ directories for tcg files: $ git grep '#include "tcg/' | wc -l 28 $ git grep '#include "tcg[^/]' | wc -l 94 To simplify the preprocessor search path, unify by expliciting the tcg/ directory. Patch created mechanically by running: $ for x in $(ls tcg/*.{c,h} | sed s,tcg/,,); do \ sed -i "s,#include \"$x\",#include \"tcg/$x\"," \ $(git grep -l "#include \"$x\""); \ done Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- include/exec/cpu_ldst.h | 2 +- tcg/i386/tcg-target.h | 2 +- tcg/tcg-op.h | 2 +- tcg/tcg.h | 4 ++-- accel/tcg/cpu-exec.c | 2 +- accel/tcg/tcg-runtime-gvec.c | 2 +- accel/tcg/translate-all.c | 2 +- accel/tcg/user-exec.c | 2 +- bsd-user/main.c | 2 +- cpus.c | 2 +- exec.c | 2 +- linux-user/main.c | 2 +- target/alpha/translate.c | 2 +- target/arm/helper-a64.c | 2 +- target/arm/translate-a64.c | 4 ++-- target/arm/translate-sve.c | 6 +++--- target/arm/translate.c | 4 ++-- target/cris/translate.c | 2 +- target/hppa/translate.c | 2 +- target/i386/mem_helper.c | 2 +- target/i386/translate.c | 2 +- target/lm32/translate.c | 2 +- target/m68k/translate.c | 2 +- target/microblaze/translate.c | 2 +- target/mips/translate.c | 2 +- target/moxie/translate.c | 2 +- target/nios2/translate.c | 2 +- target/openrisc/translate.c | 2 +- target/ppc/mem_helper.c | 2 +- target/ppc/translate.c | 4 ++-- target/riscv/cpu_helper.c | 2 +- target/riscv/translate.c | 2 +- target/s390x/translate.c | 4 ++-- target/sh4/translate.c | 2 +- target/sparc/ldst_helper.c | 2 +- target/sparc/translate.c | 2 +- target/tilegx/translate.c | 2 +- target/tricore/translate.c | 2 +- target/unicore32/translate.c | 2 +- target/xtensa/translate.c | 2 +- tcg/aarch64/tcg-target.inc.c | 4 ++-- tcg/arm/tcg-target.inc.c | 4 ++-- tcg/i386/tcg-target.inc.c | 4 ++-- tcg/mips/tcg-target.inc.c | 2 +- tcg/optimize.c | 2 +- tcg/ppc/tcg-target.inc.c | 4 ++-- tcg/riscv/tcg-target.inc.c | 4 ++-- tcg/s390/tcg-target.inc.c | 4 ++-- tcg/sparc/tcg-target.inc.c | 2 +- tcg/tcg-common.c | 2 +- tcg/tcg-op-gvec.c | 8 ++++---- tcg/tcg-op-vec.c | 6 +++--- tcg/tcg-op.c | 6 +++--- tcg/tcg.c | 2 +- tcg/tci.c | 2 +- 55 files changed, 75 insertions(+), 75 deletions(-) diff --git a/include/exec/cpu_ldst.h b/include/exec/cpu_ldst.h index fd499f7e2f..9c637f6e89 100644 --- a/include/exec/cpu_ldst.h +++ b/include/exec/cpu_ldst.h @@ -153,7 +153,7 @@ static inline void clear_helper_retaddr(void) #else =20 /* The memory helpers for tcg-generated code need tcg_target_long etc. */ -#include "tcg.h" +#include "tcg/tcg.h" =20 static inline target_ulong tlb_addr_write(const CPUTLBEntry *entry) { diff --git a/tcg/i386/tcg-target.h b/tcg/i386/tcg-target.h index 928e8b87bb..bfb3f5f6e9 100644 --- a/tcg/i386/tcg-target.h +++ b/tcg/i386/tcg-target.h @@ -223,7 +223,7 @@ static inline void tb_target_set_jmp_target(uintptr_t t= c_ptr, * The x86 has a pretty strong memory ordering which only really * allows for some stores to be re-ordered after loads. */ -#include "tcg-mo.h" +#include "tcg/tcg-mo.h" =20 #define TCG_TARGET_DEFAULT_MO (TCG_MO_ALL & ~TCG_MO_ST_LD) =20 diff --git a/tcg/tcg-op.h b/tcg/tcg-op.h index 4af272daa5..230db6e022 100644 --- a/tcg/tcg-op.h +++ b/tcg/tcg-op.h @@ -25,7 +25,7 @@ #ifndef TCG_TCG_OP_H #define TCG_TCG_OP_H =20 -#include "tcg.h" +#include "tcg/tcg.h" #include "exec/helper-proto.h" #include "exec/helper-gen.h" =20 diff --git a/tcg/tcg.h b/tcg/tcg.h index 92ca10dffc..bb59027240 100644 --- a/tcg/tcg.h +++ b/tcg/tcg.h @@ -31,7 +31,7 @@ #include "qemu/bitops.h" #include "qemu/plugin.h" #include "qemu/queue.h" -#include "tcg-mo.h" +#include "tcg/tcg-mo.h" #include "tcg-target.h" #include "qemu/int128.h" =20 @@ -211,7 +211,7 @@ typedef uint64_t TCGRegSet; =20 typedef enum TCGOpcode { #define DEF(name, oargs, iargs, cargs, flags) INDEX_op_ ## name, -#include "tcg-opc.h" +#include "tcg/tcg-opc.h" #undef DEF NB_OPS, } TCGOpcode; diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c index 62068d10c3..2560c90eec 100644 --- a/accel/tcg/cpu-exec.c +++ b/accel/tcg/cpu-exec.c @@ -23,7 +23,7 @@ #include "trace.h" #include "disas/disas.h" #include "exec/exec-all.h" -#include "tcg.h" +#include "tcg/tcg.h" #include "qemu/atomic.h" #include "sysemu/qtest.h" #include "qemu/timer.h" diff --git a/accel/tcg/tcg-runtime-gvec.c b/accel/tcg/tcg-runtime-gvec.c index 51cb29ca79..5b1902d591 100644 --- a/accel/tcg/tcg-runtime-gvec.c +++ b/accel/tcg/tcg-runtime-gvec.c @@ -21,7 +21,7 @@ #include "qemu/host-utils.h" #include "cpu.h" #include "exec/helper-proto.h" -#include "tcg-gvec-desc.h" +#include "tcg/tcg-gvec-desc.h" =20 =20 /* Virtually all hosts support 16-byte vectors. Those that don't can emul= ate diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c index bb325a2bc4..a08ab11f65 100644 --- a/accel/tcg/translate-all.c +++ b/accel/tcg/translate-all.c @@ -25,7 +25,7 @@ #include "trace.h" #include "disas/disas.h" #include "exec/exec-all.h" -#include "tcg.h" +#include "tcg/tcg.h" #if defined(CONFIG_USER_ONLY) #include "qemu.h" #if defined(__FreeBSD__) || defined(__FreeBSD_kernel__) diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c index b09f7a1577..2d45613231 100644 --- a/accel/tcg/user-exec.c +++ b/accel/tcg/user-exec.c @@ -20,7 +20,7 @@ #include "cpu.h" #include "disas/disas.h" #include "exec/exec-all.h" -#include "tcg.h" +#include "tcg/tcg.h" #include "qemu/bitops.h" #include "exec/cpu_ldst.h" #include "translate-all.h" diff --git a/bsd-user/main.c b/bsd-user/main.c index 7f4e3cd627..770c2b267a 100644 --- a/bsd-user/main.c +++ b/bsd-user/main.c @@ -33,7 +33,7 @@ #include "qemu/module.h" #include "cpu.h" #include "exec/exec-all.h" -#include "tcg.h" +#include "tcg/tcg.h" #include "qemu/timer.h" #include "qemu/envlist.h" #include "exec/log.h" diff --git a/cpus.c b/cpus.c index b472378b70..18f56572fa 100644 --- a/cpus.c +++ b/cpus.c @@ -53,7 +53,7 @@ #include "qemu/bitmap.h" #include "qemu/seqlock.h" #include "qemu/guest-random.h" -#include "tcg.h" +#include "tcg/tcg.h" #include "hw/nmi.h" #include "sysemu/replay.h" #include "sysemu/runstate.h" diff --git a/exec.c b/exec.c index d4b769d0d4..0f6b087f57 100644 --- a/exec.c +++ b/exec.c @@ -25,7 +25,7 @@ #include "cpu.h" #include "exec/exec-all.h" #include "exec/target_page.h" -#include "tcg.h" +#include "tcg/tcg.h" #include "hw/qdev-core.h" #include "hw/qdev-properties.h" #if !defined(CONFIG_USER_ONLY) diff --git a/linux-user/main.c b/linux-user/main.c index 8718d03ee2..fba833aac9 100644 --- a/linux-user/main.c +++ b/linux-user/main.c @@ -37,7 +37,7 @@ #include "qemu/plugin.h" #include "cpu.h" #include "exec/exec-all.h" -#include "tcg.h" +#include "tcg/tcg.h" #include "qemu/timer.h" #include "qemu/envlist.h" #include "qemu/guest-random.h" diff --git a/target/alpha/translate.c b/target/alpha/translate.c index f7f1ed0f41..8870284f57 100644 --- a/target/alpha/translate.c +++ b/target/alpha/translate.c @@ -23,7 +23,7 @@ #include "disas/disas.h" #include "qemu/host-utils.h" #include "exec/exec-all.h" -#include "tcg-op.h" +#include "tcg/tcg-op.h" #include "exec/cpu_ldst.h" #include "exec/helper-proto.h" #include "exec/helper-gen.h" diff --git a/target/arm/helper-a64.c b/target/arm/helper-a64.c index b4cd680fc4..36aa6badfd 100644 --- a/target/arm/helper-a64.c +++ b/target/arm/helper-a64.c @@ -31,7 +31,7 @@ #include "exec/cpu_ldst.h" #include "qemu/int128.h" #include "qemu/atomic128.h" -#include "tcg.h" +#include "tcg/tcg.h" #include "fpu/softfloat.h" #include /* For crc32 */ =20 diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index d4bebbe629..a1d4dce4fa 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -20,8 +20,8 @@ =20 #include "cpu.h" #include "exec/exec-all.h" -#include "tcg-op.h" -#include "tcg-op-gvec.h" +#include "tcg/tcg-op.h" +#include "tcg/tcg-op-gvec.h" #include "qemu/log.h" #include "arm_ldst.h" #include "translate.h" diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c index 5d7edd0907..b35bad245e 100644 --- a/target/arm/translate-sve.c +++ b/target/arm/translate-sve.c @@ -20,9 +20,9 @@ #include "qemu/osdep.h" #include "cpu.h" #include "exec/exec-all.h" -#include "tcg-op.h" -#include "tcg-op-gvec.h" -#include "tcg-gvec-desc.h" +#include "tcg/tcg-op.h" +#include "tcg/tcg-op-gvec.h" +#include "tcg/tcg-gvec-desc.h" #include "qemu/log.h" #include "arm_ldst.h" #include "translate.h" diff --git a/target/arm/translate.c b/target/arm/translate.c index 2b6c1f91bf..39821d040b 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -24,8 +24,8 @@ #include "internals.h" #include "disas/disas.h" #include "exec/exec-all.h" -#include "tcg-op.h" -#include "tcg-op-gvec.h" +#include "tcg/tcg-op.h" +#include "tcg/tcg-op-gvec.h" #include "qemu/log.h" #include "qemu/bitops.h" #include "arm_ldst.h" diff --git a/target/cris/translate.c b/target/cris/translate.c index cb57516a44..aaa46b5bca 100644 --- a/target/cris/translate.c +++ b/target/cris/translate.c @@ -27,7 +27,7 @@ #include "cpu.h" #include "disas/disas.h" #include "exec/exec-all.h" -#include "tcg-op.h" +#include "tcg/tcg-op.h" #include "exec/helper-proto.h" #include "mmu.h" #include "exec/cpu_ldst.h" diff --git a/target/hppa/translate.c b/target/hppa/translate.c index 2f8d407a82..f25927aeca 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -22,7 +22,7 @@ #include "disas/disas.h" #include "qemu/host-utils.h" #include "exec/exec-all.h" -#include "tcg-op.h" +#include "tcg/tcg-op.h" #include "exec/cpu_ldst.h" #include "exec/helper-proto.h" #include "exec/helper-gen.h" diff --git a/target/i386/mem_helper.c b/target/i386/mem_helper.c index d50d4b0c40..acf41f8885 100644 --- a/target/i386/mem_helper.c +++ b/target/i386/mem_helper.c @@ -24,7 +24,7 @@ #include "exec/cpu_ldst.h" #include "qemu/int128.h" #include "qemu/atomic128.h" -#include "tcg.h" +#include "tcg/tcg.h" =20 void helper_cmpxchg8b_unlocked(CPUX86State *env, target_ulong a0) { diff --git a/target/i386/translate.c b/target/i386/translate.c index 7c99ef1385..d9af8f4078 100644 --- a/target/i386/translate.c +++ b/target/i386/translate.c @@ -22,7 +22,7 @@ #include "cpu.h" #include "disas/disas.h" #include "exec/exec-all.h" -#include "tcg-op.h" +#include "tcg/tcg-op.h" #include "exec/cpu_ldst.h" #include "exec/translator.h" =20 diff --git a/target/lm32/translate.c b/target/lm32/translate.c index 73db9654d6..e583d52d03 100644 --- a/target/lm32/translate.c +++ b/target/lm32/translate.c @@ -23,7 +23,7 @@ #include "exec/helper-proto.h" #include "exec/exec-all.h" #include "exec/translator.h" -#include "tcg-op.h" +#include "tcg/tcg-op.h" #include "qemu/qemu-print.h" =20 #include "exec/cpu_ldst.h" diff --git a/target/m68k/translate.c b/target/m68k/translate.c index fcdb7bc8e4..31b743717e 100644 --- a/target/m68k/translate.c +++ b/target/m68k/translate.c @@ -22,7 +22,7 @@ #include "cpu.h" #include "disas/disas.h" #include "exec/exec-all.h" -#include "tcg-op.h" +#include "tcg/tcg-op.h" #include "qemu/log.h" #include "qemu/qemu-print.h" #include "exec/cpu_ldst.h" diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index 525115b041..37a844db99 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -22,7 +22,7 @@ #include "cpu.h" #include "disas/disas.h" #include "exec/exec-all.h" -#include "tcg-op.h" +#include "tcg/tcg-op.h" #include "exec/helper-proto.h" #include "microblaze-decode.h" #include "exec/cpu_ldst.h" diff --git a/target/mips/translate.c b/target/mips/translate.c index 4bff585bd6..efe75e6be0 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -26,7 +26,7 @@ #include "internal.h" #include "disas/disas.h" #include "exec/exec-all.h" -#include "tcg-op.h" +#include "tcg/tcg-op.h" #include "exec/cpu_ldst.h" #include "hw/mips/cpudevs.h" =20 diff --git a/target/moxie/translate.c b/target/moxie/translate.c index c87e9ec2b1..d5fb27dfb8 100644 --- a/target/moxie/translate.c +++ b/target/moxie/translate.c @@ -26,7 +26,7 @@ #include "cpu.h" #include "exec/exec-all.h" #include "disas/disas.h" -#include "tcg-op.h" +#include "tcg/tcg-op.h" #include "exec/cpu_ldst.h" #include "qemu/qemu-print.h" =20 diff --git a/target/nios2/translate.c b/target/nios2/translate.c index 82107bf270..6c34cd3193 100644 --- a/target/nios2/translate.c +++ b/target/nios2/translate.c @@ -23,7 +23,7 @@ =20 #include "qemu/osdep.h" #include "cpu.h" -#include "tcg-op.h" +#include "tcg/tcg-op.h" #include "exec/exec-all.h" #include "disas/disas.h" #include "exec/helper-proto.h" diff --git a/target/openrisc/translate.c b/target/openrisc/translate.c index 8dd28d6cf1..52323a16df 100644 --- a/target/openrisc/translate.c +++ b/target/openrisc/translate.c @@ -22,7 +22,7 @@ #include "cpu.h" #include "exec/exec-all.h" #include "disas/disas.h" -#include "tcg-op.h" +#include "tcg/tcg-op.h" #include "qemu/log.h" #include "qemu/bitops.h" #include "qemu/qemu-print.h" diff --git a/target/ppc/mem_helper.c b/target/ppc/mem_helper.c index 1351b53f28..7404b14bed 100644 --- a/target/ppc/mem_helper.c +++ b/target/ppc/mem_helper.c @@ -25,7 +25,7 @@ #include "exec/helper-proto.h" #include "helper_regs.h" #include "exec/cpu_ldst.h" -#include "tcg.h" +#include "tcg/tcg.h" #include "internal.h" #include "qemu/atomic128.h" =20 diff --git a/target/ppc/translate.c b/target/ppc/translate.c index f5fe5d0611..9dcf8dc261 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c @@ -23,8 +23,8 @@ #include "internal.h" #include "disas/disas.h" #include "exec/exec-all.h" -#include "tcg-op.h" -#include "tcg-op-gvec.h" +#include "tcg/tcg-op.h" +#include "tcg/tcg-op-gvec.h" #include "qemu/host-utils.h" #include "qemu/main-loop.h" #include "exec/cpu_ldst.h" diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 767c8762ac..85403da9c8 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -22,7 +22,7 @@ #include "qemu/main-loop.h" #include "cpu.h" #include "exec/exec-all.h" -#include "tcg-op.h" +#include "tcg/tcg-op.h" #include "trace.h" =20 int riscv_cpu_mmu_index(CPURISCVState *env, bool ifetch) diff --git a/target/riscv/translate.c b/target/riscv/translate.c index ab6a891dc3..56b1b1fe7b 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -19,7 +19,7 @@ #include "qemu/osdep.h" #include "qemu/log.h" #include "cpu.h" -#include "tcg-op.h" +#include "tcg/tcg-op.h" #include "disas/disas.h" #include "exec/cpu_ldst.h" #include "exec/exec-all.h" diff --git a/target/s390x/translate.c b/target/s390x/translate.c index 4292bb0dd0..b764ec3140 100644 --- a/target/s390x/translate.c +++ b/target/s390x/translate.c @@ -33,8 +33,8 @@ #include "internal.h" #include "disas/disas.h" #include "exec/exec-all.h" -#include "tcg-op.h" -#include "tcg-op-gvec.h" +#include "tcg/tcg-op.h" +#include "tcg/tcg-op-gvec.h" #include "qemu/log.h" #include "qemu/host-utils.h" #include "exec/cpu_ldst.h" diff --git a/target/sh4/translate.c b/target/sh4/translate.c index 922785e225..6192d83e8c 100644 --- a/target/sh4/translate.c +++ b/target/sh4/translate.c @@ -23,7 +23,7 @@ #include "cpu.h" #include "disas/disas.h" #include "exec/exec-all.h" -#include "tcg-op.h" +#include "tcg/tcg-op.h" #include "exec/cpu_ldst.h" #include "exec/helper-proto.h" #include "exec/helper-gen.h" diff --git a/target/sparc/ldst_helper.c b/target/sparc/ldst_helper.c index 7345827a96..e91cfdecd3 100644 --- a/target/sparc/ldst_helper.c +++ b/target/sparc/ldst_helper.c @@ -19,7 +19,7 @@ =20 #include "qemu/osdep.h" #include "cpu.h" -#include "tcg.h" +#include "tcg/tcg.h" #include "exec/helper-proto.h" #include "exec/exec-all.h" #include "exec/cpu_ldst.h" diff --git a/target/sparc/translate.c b/target/sparc/translate.c index edc23a7c40..9416a551cf 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -24,7 +24,7 @@ #include "disas/disas.h" #include "exec/helper-proto.h" #include "exec/exec-all.h" -#include "tcg-op.h" +#include "tcg/tcg-op.h" #include "exec/cpu_ldst.h" =20 #include "exec/helper-gen.h" diff --git a/target/tilegx/translate.c b/target/tilegx/translate.c index abce7e1c75..65f1c91f4f 100644 --- a/target/tilegx/translate.c +++ b/target/tilegx/translate.c @@ -24,7 +24,7 @@ #include "exec/log.h" #include "disas/disas.h" #include "exec/exec-all.h" -#include "tcg-op.h" +#include "tcg/tcg-op.h" #include "exec/cpu_ldst.h" #include "linux-user/syscall_defs.h" =20 diff --git a/target/tricore/translate.c b/target/tricore/translate.c index c574638c9f..609d75ae8a 100644 --- a/target/tricore/translate.c +++ b/target/tricore/translate.c @@ -22,7 +22,7 @@ #include "cpu.h" #include "disas/disas.h" #include "exec/exec-all.h" -#include "tcg-op.h" +#include "tcg/tcg-op.h" #include "exec/cpu_ldst.h" #include "qemu/qemu-print.h" =20 diff --git a/target/unicore32/translate.c b/target/unicore32/translate.c index 0f6891b8aa..d4b06df672 100644 --- a/target/unicore32/translate.c +++ b/target/unicore32/translate.c @@ -13,7 +13,7 @@ #include "cpu.h" #include "disas/disas.h" #include "exec/exec-all.h" -#include "tcg-op.h" +#include "tcg/tcg-op.h" #include "qemu/log.h" #include "exec/cpu_ldst.h" #include "exec/translator.h" diff --git a/target/xtensa/translate.c b/target/xtensa/translate.c index a99f5296e2..f5510ef043 100644 --- a/target/xtensa/translate.c +++ b/target/xtensa/translate.c @@ -33,7 +33,7 @@ #include "cpu.h" #include "exec/exec-all.h" #include "disas/disas.h" -#include "tcg-op.h" +#include "tcg/tcg-op.h" #include "qemu/log.h" #include "qemu/qemu-print.h" #include "exec/cpu_ldst.h" diff --git a/tcg/aarch64/tcg-target.inc.c b/tcg/aarch64/tcg-target.inc.c index 3f921015d3..3d9b696260 100644 --- a/tcg/aarch64/tcg-target.inc.c +++ b/tcg/aarch64/tcg-target.inc.c @@ -10,7 +10,7 @@ * See the COPYING file in the top-level directory for details. */ =20 -#include "tcg-pool.inc.c" +#include "tcg/tcg-pool.inc.c" #include "qemu/bitops.h" =20 /* We're going to re-use TCGType in setting of the SF bit, which controls @@ -1541,7 +1541,7 @@ static void tcg_out_cltz(TCGContext *s, TCGType ext, = TCGReg d, } =20 #ifdef CONFIG_SOFTMMU -#include "tcg-ldst.inc.c" +#include "tcg/tcg-ldst.inc.c" =20 /* helper signature: helper_ret_ld_mmu(CPUState *env, target_ulong addr, * TCGMemOpIdx oi, uintptr_t ra) diff --git a/tcg/arm/tcg-target.inc.c b/tcg/arm/tcg-target.inc.c index 94d80d79d1..0497b6a2a5 100644 --- a/tcg/arm/tcg-target.inc.c +++ b/tcg/arm/tcg-target.inc.c @@ -23,7 +23,7 @@ */ =20 #include "elf.h" -#include "tcg-pool.inc.c" +#include "tcg/tcg-pool.inc.c" =20 int arm_arch =3D __ARM_ARCH; =20 @@ -1131,7 +1131,7 @@ static TCGCond tcg_out_cmp2(TCGContext *s, const TCGA= rg *args, } =20 #ifdef CONFIG_SOFTMMU -#include "tcg-ldst.inc.c" +#include "tcg/tcg-ldst.inc.c" =20 /* helper signature: helper_ret_ld_mmu(CPUState *env, target_ulong addr, * int mmu_idx, uintptr_t ra) diff --git a/tcg/i386/tcg-target.inc.c b/tcg/i386/tcg-target.inc.c index 9d8ed974e0..115b7be347 100644 --- a/tcg/i386/tcg-target.inc.c +++ b/tcg/i386/tcg-target.inc.c @@ -22,7 +22,7 @@ * THE SOFTWARE. */ =20 -#include "tcg-pool.inc.c" +#include "tcg/tcg-pool.inc.c" =20 #ifdef CONFIG_DEBUG_TCG static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] =3D { @@ -1647,7 +1647,7 @@ static void tcg_out_nopn(TCGContext *s, int n) } =20 #if defined(CONFIG_SOFTMMU) -#include "tcg-ldst.inc.c" +#include "tcg/tcg-ldst.inc.c" =20 /* helper signature: helper_ret_ld_mmu(CPUState *env, target_ulong addr, * int mmu_idx, uintptr_t ra) diff --git a/tcg/mips/tcg-target.inc.c b/tcg/mips/tcg-target.inc.c index 5442167045..06370bd52c 100644 --- a/tcg/mips/tcg-target.inc.c +++ b/tcg/mips/tcg-target.inc.c @@ -1107,7 +1107,7 @@ static void tcg_out_call(TCGContext *s, tcg_insn_unit= *arg) } =20 #if defined(CONFIG_SOFTMMU) -#include "tcg-ldst.inc.c" +#include "tcg/tcg-ldst.inc.c" =20 static void * const qemu_ld_helpers[16] =3D { [MO_UB] =3D helper_ret_ldub_mmu, diff --git a/tcg/optimize.c b/tcg/optimize.c index f7f4e873c9..53aa8e5329 100644 --- a/tcg/optimize.c +++ b/tcg/optimize.c @@ -24,7 +24,7 @@ */ =20 #include "qemu/osdep.h" -#include "tcg-op.h" +#include "tcg/tcg-op.h" =20 #define CASE_OP_32_64(x) \ glue(glue(case INDEX_op_, x), _i32): \ diff --git a/tcg/ppc/tcg-target.inc.c b/tcg/ppc/tcg-target.inc.c index d308d69aba..1008b1baee 100644 --- a/tcg/ppc/tcg-target.inc.c +++ b/tcg/ppc/tcg-target.inc.c @@ -23,7 +23,7 @@ */ =20 #include "elf.h" -#include "tcg-pool.inc.c" +#include "tcg/tcg-pool.inc.c" =20 #if defined _CALL_DARWIN || defined __APPLE__ #define TCG_TARGET_CALL_DARWIN @@ -1845,7 +1845,7 @@ static const uint32_t qemu_exts_opc[4] =3D { }; =20 #if defined (CONFIG_SOFTMMU) -#include "tcg-ldst.inc.c" +#include "tcg/tcg-ldst.inc.c" =20 /* helper signature: helper_ld_mmu(CPUState *env, target_ulong addr, * int mmu_idx, uintptr_t ra) diff --git a/tcg/riscv/tcg-target.inc.c b/tcg/riscv/tcg-target.inc.c index 7018509693..75a96cd189 100644 --- a/tcg/riscv/tcg-target.inc.c +++ b/tcg/riscv/tcg-target.inc.c @@ -27,7 +27,7 @@ * THE SOFTWARE. */ =20 -#include "tcg-pool.inc.c" +#include "tcg/tcg-pool.inc.c" =20 #ifdef CONFIG_DEBUG_TCG static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] =3D { @@ -921,7 +921,7 @@ static void tcg_out_mb(TCGContext *s, TCGArg a0) */ =20 #if defined(CONFIG_SOFTMMU) -#include "tcg-ldst.inc.c" +#include "tcg/tcg-ldst.inc.c" =20 /* helper signature: helper_ret_ld_mmu(CPUState *env, target_ulong addr, * TCGMemOpIdx oi, uintptr_t ra) diff --git a/tcg/s390/tcg-target.inc.c b/tcg/s390/tcg-target.inc.c index 8aaa4cebe8..1f428cd1d0 100644 --- a/tcg/s390/tcg-target.inc.c +++ b/tcg/s390/tcg-target.inc.c @@ -29,7 +29,7 @@ #error "unsupported code generation mode" #endif =20 -#include "tcg-pool.inc.c" +#include "tcg/tcg-pool.inc.c" #include "elf.h" =20 /* ??? The translation blocks produced by TCG are generally small enough t= o @@ -1536,7 +1536,7 @@ static void tcg_out_qemu_st_direct(TCGContext *s, Mem= Op opc, TCGReg data, } =20 #if defined(CONFIG_SOFTMMU) -#include "tcg-ldst.inc.c" +#include "tcg/tcg-ldst.inc.c" =20 /* We're expecting to use a 20-bit negative offset on the tlb memory ops. = */ QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) > 0); diff --git a/tcg/sparc/tcg-target.inc.c b/tcg/sparc/tcg-target.inc.c index d7986cda5c..71da9c199b 100644 --- a/tcg/sparc/tcg-target.inc.c +++ b/tcg/sparc/tcg-target.inc.c @@ -22,7 +22,7 @@ * THE SOFTWARE. */ =20 -#include "tcg-pool.inc.c" +#include "tcg/tcg-pool.inc.c" =20 #ifdef CONFIG_DEBUG_TCG static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] =3D { diff --git a/tcg/tcg-common.c b/tcg/tcg-common.c index 97305a3efc..7e1992e79e 100644 --- a/tcg/tcg-common.c +++ b/tcg/tcg-common.c @@ -32,7 +32,7 @@ uintptr_t tci_tb_ptr; TCGOpDef tcg_op_defs[] =3D { #define DEF(s, oargs, iargs, cargs, flags) \ { #s, oargs, iargs, cargs, iargs + oargs + cargs, flags }, -#include "tcg-opc.h" +#include "tcg/tcg-opc.h" #undef DEF }; const size_t tcg_op_defs_max =3D ARRAY_SIZE(tcg_op_defs); diff --git a/tcg/tcg-op-gvec.c b/tcg/tcg-op-gvec.c index 5c95ecd51c..41b4a3c661 100644 --- a/tcg/tcg-op-gvec.c +++ b/tcg/tcg-op-gvec.c @@ -18,11 +18,11 @@ */ =20 #include "qemu/osdep.h" -#include "tcg.h" -#include "tcg-op.h" -#include "tcg-op-gvec.h" +#include "tcg/tcg.h" +#include "tcg/tcg-op.h" +#include "tcg/tcg-op-gvec.h" #include "qemu/main-loop.h" -#include "tcg-gvec-desc.h" +#include "tcg/tcg-gvec-desc.h" =20 #define MAX_UNROLL 4 =20 diff --git a/tcg/tcg-op-vec.c b/tcg/tcg-op-vec.c index 6714991bf4..b6937e8d64 100644 --- a/tcg/tcg-op-vec.c +++ b/tcg/tcg-op-vec.c @@ -19,9 +19,9 @@ =20 #include "qemu/osdep.h" #include "cpu.h" -#include "tcg.h" -#include "tcg-op.h" -#include "tcg-mo.h" +#include "tcg/tcg.h" +#include "tcg/tcg-op.h" +#include "tcg/tcg-mo.h" =20 /* Reduce the number of ifdefs below. This assumes that all uses of TCGV_HIGH and TCGV_LOW are properly protected by a conditional that diff --git a/tcg/tcg-op.c b/tcg/tcg-op.c index c245126f98..7d782002e3 100644 --- a/tcg/tcg-op.c +++ b/tcg/tcg-op.c @@ -25,9 +25,9 @@ #include "qemu/osdep.h" #include "cpu.h" #include "exec/exec-all.h" -#include "tcg.h" -#include "tcg-op.h" -#include "tcg-mo.h" +#include "tcg/tcg.h" +#include "tcg/tcg-op.h" +#include "tcg/tcg-mo.h" #include "trace-tcg.h" #include "trace/mem.h" #include "exec/plugin-gen.h" diff --git a/tcg/tcg.c b/tcg/tcg.c index 4f616ba38b..dd4b3d7684 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -48,7 +48,7 @@ #include "hw/boards.h" #endif =20 -#include "tcg-op.h" +#include "tcg/tcg-op.h" =20 #if UINTPTR_MAX =3D=3D UINT32_MAX # define ELF_CLASS ELFCLASS32 diff --git a/tcg/tci.c b/tcg/tci.c index a6208653e8..46fe9ce63f 100644 --- a/tcg/tci.c +++ b/tcg/tci.c @@ -30,7 +30,7 @@ #include "qemu-common.h" #include "tcg/tcg.h" /* MAX_OPC_PARAM_IARGS */ #include "exec/cpu_ldst.h" -#include "tcg-op.h" +#include "tcg/tcg-op.h" =20 /* Marker for missing code. */ #define TODO() \ --=20 2.21.0 From MAILER-DAEMON Mon Dec 30 04:10:01 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1ilr3o-0006vd-Vg for mharc-qemu-arm@gnu.org; Mon, 30 Dec 2019 04:10:00 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:46313) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ilr3l-0006ot-1q for qemu-arm@nongnu.org; Mon, 30 Dec 2019 04:09:57 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ilr3j-0000FX-WD for qemu-arm@nongnu.org; Mon, 30 Dec 2019 04:09:56 -0500 Received: from us-smtp-delivery-1.mimecast.com ([205.139.110.120]:37672 helo=us-smtp-1.mimecast.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1ilr3j-0000Ey-SD for qemu-arm@nongnu.org; Mon, 30 Dec 2019 04:09:55 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1577696995; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=huQ1XM2FC9X4C7Ug0J2Ty+HzCEUy30TWjQVBOx/Tu5I=; b=iqPw3B2IMrJ/IX3z98TThLWTEsKJcPe/FTfdHS6fLn6w156kaZ6wiIjRLz8bqtpBmuuqK+ fy06srPJ8xQgTlYesE2aCiqiUQAiUC1gON6k3tcXw4wpIphNLLNLgEg4ZBG1IVPunGIA/b 37jKqXRU63NCdpzq+mOk4j0BkgqQKVc= Received: from mimecast-mx01.redhat.com (mimecast-mx01.redhat.com [209.132.183.4]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-330-Eep-3rfQPkaErD9Vf8OLaw-1; Mon, 30 Dec 2019 04:09:52 -0500 Received: from smtp.corp.redhat.com (int-mx07.intmail.prod.int.phx2.redhat.com [10.5.11.22]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx01.redhat.com (Postfix) with ESMTPS id 03C52107ACC4; Mon, 30 Dec 2019 09:09:49 +0000 (UTC) Received: from x1w.redhat.com (ovpn-116-185.ams2.redhat.com [10.36.116.185]) by smtp.corp.redhat.com (Postfix) with ESMTPS id 161291036D1B; Mon, 30 Dec 2019 09:09:36 +0000 (UTC) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org, Markus Armbruster , Richard Henderson Cc: Aurelien Jarno , qemu-ppc@nongnu.org, Peter Maydell , Riku Voipio , Aleksandar Rikalo , Andrzej Zaborowski , Laurent Vivier , Paolo Bonzini , Max Filippov , Claudio Fontana , qemu-s390x@nongnu.org, Sagar Karandikar , Marek Vasut , Artyom Tarasenko , Chris Wulff , Bastian Koppelmann , Cornelia Huck , Palmer Dabbelt , Stefan Weil , Richard Henderson , qemu-arm@nongnu.org, "Edgar E. Iglesias" , Mark Cave-Ayland , David Hildenbrand , Anthony Green , Eduardo Habkost , Alistair Francis , Stafford Horne , Guan Xuetao , Michael Walle , Aleksandar Markovic , David Gibson , qemu-riscv@nongnu.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH 2/2] configure: Remove tcg/ from the preprocessor include search list Date: Mon, 30 Dec 2019 10:09:00 +0100 Message-Id: <20191230090900.446-3-philmd@redhat.com> In-Reply-To: <20191230090900.446-1-philmd@redhat.com> References: <20191230090900.446-1-philmd@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.84 on 10.5.11.22 X-MC-Unique: Eep-3rfQPkaErD9Vf8OLaw-1 X-Mimecast-Spam-Score: 0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 205.139.110.120 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 30 Dec 2019 09:09:58 -0000 All tcg includes are relative to the repository root directory, we can safely remove the tcg/ directory from the include search path list. Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- configure | 1 - 1 file changed, 1 deletion(-) diff --git a/configure b/configure index 940bf9e87a..74dad08580 100755 --- a/configure +++ b/configure @@ -7436,7 +7436,6 @@ elif test "$ARCH" =3D "riscv32" || test "$ARCH" =3D "= riscv64" ; then else QEMU_INCLUDES=3D"-iquote \$(SRC_PATH)/tcg/\$(ARCH) $QEMU_INCLUDES" fi -QEMU_INCLUDES=3D"-iquote \$(SRC_PATH)/tcg $QEMU_INCLUDES" =20 echo "TOOLS=3D$tools" >> $config_host_mak echo "ROMS=3D$roms" >> $config_host_mak --=20 2.21.0 From MAILER-DAEMON Mon Dec 30 04:53:10 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1ilrjZ-0008T1-Sw for mharc-qemu-arm@gnu.org; Mon, 30 Dec 2019 04:53:09 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:53409) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ilrjX-0008SJ-3q for qemu-arm@nongnu.org; Mon, 30 Dec 2019 04:53:08 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ilrjV-0002Ri-Tn for qemu-arm@nongnu.org; Mon, 30 Dec 2019 04:53:06 -0500 Received: from mail.weilnetz.de ([37.120.169.71]:37452 helo=v2201612906741603.powersrv.de) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1ilrjV-0002Px-Kg; Mon, 30 Dec 2019 04:53:05 -0500 Received: from localhost (localhost [127.0.0.1]) by v2201612906741603.powersrv.de (Postfix) with ESMTP id DEE60DB9A6A; Mon, 30 Dec 2019 10:53:02 +0100 (CET) X-Virus-Scanned: Debian amavisd-new at v2201612906741603.powersrv.de Received: from v2201612906741603.powersrv.de ([127.0.0.1]) by localhost (v2201612906741603.powersrv.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id FIlKc108VSlr; Mon, 30 Dec 2019 10:53:01 +0100 (CET) Received: from edv-macbook-pro.fritz.box (pD9EC3B33.dip0.t-ipconnect.de [217.236.59.51]) (using TLSv1.3 with cipher TLS_AES_128_GCM_SHA256 (128/128 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by v2201612906741603.powersrv.de (Postfix) with ESMTPSA id 0D0CFDA0376; Mon, 30 Dec 2019 10:53:01 +0100 (CET) Subject: Re: [PATCH 1/2] tcg: Search includes from the project root source directory To: =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= , qemu-devel@nongnu.org, Markus Armbruster , Richard Henderson Cc: Aurelien Jarno , qemu-ppc@nongnu.org, Peter Maydell , Riku Voipio , Aleksandar Rikalo , Andrzej Zaborowski , Laurent Vivier , Paolo Bonzini , Max Filippov , Claudio Fontana , qemu-s390x@nongnu.org, Sagar Karandikar , Marek Vasut , Artyom Tarasenko , Chris Wulff , Bastian Koppelmann , Cornelia Huck , Palmer Dabbelt , Richard Henderson , qemu-arm@nongnu.org, "Edgar E. Iglesias" , Mark Cave-Ayland , David Hildenbrand , Anthony Green , Eduardo Habkost , Alistair Francis , Stafford Horne , Guan Xuetao , Michael Walle , Aleksandar Markovic , David Gibson , qemu-riscv@nongnu.org References: <20191230090900.446-1-philmd@redhat.com> <20191230090900.446-2-philmd@redhat.com> From: Stefan Weil Autocrypt: addr=sw@weilnetz.de; keydata= mQINBFXCNBcBEACUbHx9FWsS1ATrhLGAS+Nc6bFQHPR3CpUQ4v++RiMg25bF6Ov1RsYEcovI 0DXGh6Ma+l6dRlvUXV8tMvNwqghDUr5KY7LN6tgcFKjBbXdv9VlKiWiMLKBrARcFKxx1sfLp 1P8RiaUdKsgy2Hq4T1PPy9ENTL1/FBG6P/Rw0rO9zOB+yNHcRJ5diDnERbi3x7qoaPUra2Ig lmQk/uxXKC0aNIhpNLNiQ+YpwTUN9q3eG6B9/3CG8RGtFzH9vDPlLvtUX+01a2gCifTi3iH3 8EEK8ACXIRs2dszlxMneKTvflXfvyCM1O+59wGcICQxltxLLhHSCJjOQyWdR2JUtn//XjVWM mf6bBT7Imx3DhhfFRlA+/Lw9Zah66DJrZgiV0LqoN/2f031TzD3FCBiGQEMC072MvSQ1DdJN OiRE1iWO0teLOxaFSbvJS9ij8CFSQQTnSVZs0YXGBal+1kMeaKo9sO4tkaAR2190IlMNanig CTJfeFqxzZkoki378grSHdGUTGKfwNPflTOA6Pw6xuUcxW55LB3lBsPqb0289P8o9dTR7582 e6XTkpzqe/z/fYmfI9YXIjGY8WBMRbsuQA30JLq1/n/zwxAOr2P9y4nqTMMgFOtQS8w4G46K UMY/5IspZp2VnPwvazUo2zpYiUSLo1hFHx2jrePYNu2KLROXpwARAQABtBxTdGVmYW4gV2Vp bCA8c3dAd2VpbG5ldHouZGU+iQI6BBMBCAAkAhsDBQsJCAcDBRUKCQgLBRYCAwEAAh4BAheA BQJV04LlAhkBAAoJEOCMIdVndFCtP5QP/1U8yWZzHeHufRFxtMsK1PERiLuKyGRH2oE5NWVc 5QQHZZ2ypXu53o2ZbZxmdy8+4lXiPWWwYVqto3V7bPaMTvQhIT0I3c3ZEZsvwyEEE6QdRs52 haZwX+TzNMQ5mOePdM2m4WqO0oU7YHU2WFf54MBmAGtj3FAQEAlZAaMiJs2aApw/4t35ICL1 Sb0FY8d8lKBbIFOAaFfrlQTC3y8eMTk1QxOVtdXpRrOl6OE0alWn97NRqeZlBm0P+BEvdgTP Qt+9rxbe4ulgKME2LkbDhLqf0m2+xMXb7T4LiHbQYnnWKGZyogpFaw3PuRVd9m8uxx1F8b4U jNzI9x2Ez5LDv8NHpSY0LGwvVmkgELYbcbyiftbuw81gJuM7k4IW5GR85kTH6y/Sq6JNaI4p 909IK8X4eeoCkAqEVmDOo1D5DytgxIV/PErrin82OIDXLENzOWfPPtUTO+H7qUe80NS2HLPG IveYSjuYKBB6n2JhPkUD7xxMEdh5Ukqi1WIBSV4Tuk3/ubHajP5bqg4QP3Wo1AyICX09A1QQ DajtMkyxXhYxr826EGcRD2WUUprGNYwaks4YiPuvOAJxSYprKWT6UDHzE3S8u4uZZm9H8cyg Fa3pysJwTmbmrBAP1lMolwXHky60dPnKPmFyArGC0utAH7QELXzBybnE/vSNttNT1D+HuQIN BFXcnj0BEAC32cCu2MWeqZEcvShjkoKsXk42mHrGbeuh/viVn8JOQbTO706GZtazoww2weAz uVEYhwqi7u9RATz9MReHf7R5F0KIRhc/2NhNNeixT/7L+E5jffH1LD+0IQdeLPoz6unvg7U/ 7OpdKWbHzPM3Lfd0N1dRP5sXULpjtYQKEgiOU58sc4F5rM10KoPFEMz8Ip4j9RbH/CbTPUM0 S4PxytRciB3Fjd0ECbVsErTjX7cZc/yBgs3ip7BPVWgbflhrc+utML/MwC6ZqCOIXf/U0ICY fp5I7PDbUSWgMFHvorWegMYJ9EzZ2nTvytL8E75C2U3j5RZAuQH5ysfGpdaTS76CRrYDtkEc ViTL+hRUgrX9qvqzCdNEePbQZr6u6TNx3FBEnaTAZ5GuosfUk7ynvam2+zAzLNU+GTywTZL2 WU+tvOePp9z1/mbLnH2LkWHgy3bPu77AFJ1yTbBXl5OEQ/PtTOJeC1urvgeNru26hDFSFyk4 gFcqXxswu2PGU7tWYffXZXN+IFipCS718eDcT8eL66ifZ8lqJ8Vu5WJmp9mr1spP9RYbT7Rw pzZ3iiz7e7AZyOtpSMIVJeYZTbtiqJbyN4zukhrTdCgCFYgf0CkA5UGpYXp2sXPr+gVxKX2p tj/gid4n95vR7KMeWV6DJ0YS4hKGtdhkuJCpJfjKP/e8TwARAQABiQIfBBgBCAAJBQJV3J49 AhsMAAoJEOCMIdVndFCtYRoQAJOu3RZTEvUBPoFqsnd849VmOKKg77cs+HD3xyLtp95JwQrz hwa/4ouDFrC86jt1vARfpVx5C8nQtNnWhg+5h5kyOIbtB1/27CCTdXAd/hL2k3GyrJXEc+i0 31E9bCqgf2KGY7+aXu4LeAfRIWJT9FGVzdz1f+77pJuRIRRmtSs8VAond2l+OcDdEI9Mjd9M qvyPJwDkDkDvsNptrcv4xeNzvX+2foxkJmYru6dJ+leritsasiAxacUowGB5E41RZEUg6bmV F4SMseIAEKWLy3hPGvYBOzADhq2YLgnM/wn9Y9Z7bEMy+w5e75saBbkFI7TncxDPUnIl/UTE KU1ORi5WWbvXYkUTtfNzZyD0/v3oojcIoZvK1OlpOtXHdlqOodjXF9nLe8eiVHyl8ZnzFxhe EW2QPvX8FLKqmSs9W9saQtk6bhv9LNYIYINjH3EEH/+bbmV+ln4O7a73Wm8L3tnpC3LmdGn2 Rm8B6J2ZK6ci1TRDiMpCUWefpnIuE+TibC5VJR5zx0Yh11rxxBFob8mWktRmLZyeEoCcZoBo sbJxD80QxWO03zPpkcJ7d4BrVsQ/BJkBtEe4Jn4iqHqA/OcrzwuEZSv+/MdgoqfblBZhDusm LYfVy7wFDeVClG6eQIiK2EnmDChLRkVIQzbkV0iG+NJVVJHLGK7/OsO47+zq Message-ID: <273bf2e5-1223-3d01-f930-394195c037e4@weilnetz.de> Date: Mon, 30 Dec 2019 10:53:00 +0100 User-Agent: Mozilla/5.0 (Macintosh; Intel Mac OS X 10.15; rv:68.0) Gecko/20100101 Thunderbird/68.3.1 MIME-Version: 1.0 In-Reply-To: <20191230090900.446-2-philmd@redhat.com> Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 37.120.169.71 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 30 Dec 2019 09:53:08 -0000 Am 30.12.19 um 10:08 schrieb Philippe Mathieu-Daud=C3=A9: [...] > tcg/tcg-op.h | 2 +- > tcg/tcg.h | 4 ++-- > tcg/tcg-common.c | 2 +- > tcg/tcg-op-gvec.c | 8 ++++---- > tcg/tcg-op-vec.c | 6 +++--- > tcg/tcg-op.c | 6 +++--- > tcg/tcg.c | 2 +- > tcg/tci.c | 2 +- Source files in the tcg directory should not need any change because they find include files in the same directory without searching. If we add a tcg/ include file prefix for them as well, that has the advantage that it might look prettier and more uniform, but it has the disadvantage of requiring a search by the preprocessor. I'd prefer not changing those files. Regards and best wished for 2020 Stefan From MAILER-DAEMON Mon Dec 30 04:59:51 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1ilrq2-0001WX-VC for mharc-qemu-arm@gnu.org; Mon, 30 Dec 2019 04:59:50 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:54008) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ilrq0-0001VT-Ey for qemu-arm@nongnu.org; Mon, 30 Dec 2019 04:59:49 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ilrpy-0006PO-TQ for qemu-arm@nongnu.org; Mon, 30 Dec 2019 04:59:47 -0500 Received: from us-smtp-2.mimecast.com ([207.211.31.81]:31796 helo=us-smtp-delivery-1.mimecast.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1ilrpy-0006OJ-Or for qemu-arm@nongnu.org; Mon, 30 Dec 2019 04:59:46 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1577699985; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=gqFk+x0X9D60pam+u0Foq5BjemwZC+N+k+hZLjLiTVE=; b=NDhY5mmnrtmuDKefml9XuGrwjgMU3wuwdnBUCnMm0Yc0KXKdeDHjALTCsTu+0aSnWfgu3m BlFMMb2tc77nMA1UagFLotYgx0Gt4ruyOave3rUPBGqHLopZNyKEPdXNyx9Gl/D3iGm0Ga LGaKkpvLV5mDvyI4BRPMCUjvRqosNFw= Received: from mail-wm1-f72.google.com (mail-wm1-f72.google.com [209.85.128.72]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-253-wWAka8_AMPmBCdKu6lachg-1; Mon, 30 Dec 2019 04:59:44 -0500 Received: by mail-wm1-f72.google.com with SMTP id n17so1458530wmk.1 for ; Mon, 30 Dec 2019 01:59:44 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:subject:to:cc:references:from:message-id:date :user-agent:mime-version:in-reply-to:content-language :content-transfer-encoding; bh=nHtO6Vsw0hLQyKeVXTvkdGim74QMEL7005MktoQeb/g=; b=PXMo0S6t93R01i9boUPbmg3GN02buVI6PmioU3CTJB/jaMcrPGnsYSe9ILKplhovGt mR7c99hRP+QpNQeapewxMMJ+snYJmxfrrjncTXFflZhZ/7juW1mJVro+7DFHHVFkND2V qt1X6HUYxf0UDWiU4AlGKZUDTvzw7p7NLGw1vl3nfpGObPOb+KKf3zaJW5wun5pmABpK 9kLSfOgXrTUJZVcWZcs5Xfe+3zSulRlbbBsEgr2Dz/zntcs6gl2+mOUb/qT0y0gBD7f6 280bm+DdA0uo3TE/d47r4k2ELJ1e4b6DK+LbN6DgW9v/F4rMMIRg1zC5P2OospAgJBol XRvw== X-Gm-Message-State: APjAAAUayawxfHe6cyQnpjn5hDVrxemO3S1PMrazMiNS0NMIvmLFd4xT F0rJ8GTbHigLwqd8bwa1dbj7IFLWDoMg+1lJO3/UKqFVBtleLKAwES0s82BvC01/US5MrARguE/ vG7r8OZm0bkSi X-Received: by 2002:a1c:4454:: with SMTP id r81mr33061270wma.117.1577699983544; Mon, 30 Dec 2019 01:59:43 -0800 (PST) X-Google-Smtp-Source: APXvYqzQJMPuSs+59lxAJOKH6KCCABboI19InCFscJ7xeEBu6XQWYAjfD10FKvWAF/jvDgOikM0V3Q== X-Received: by 2002:a1c:4454:: with SMTP id r81mr33061234wma.117.1577699983295; Mon, 30 Dec 2019 01:59:43 -0800 (PST) Received: from ?IPv6:2a01:cb18:8372:6b00:691b:aac5:8837:d4da? ([2a01:cb18:8372:6b00:691b:aac5:8837:d4da]) by smtp.gmail.com with ESMTPSA id i16sm20447753wmb.36.2019.12.30.01.59.41 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 30 Dec 2019 01:59:42 -0800 (PST) Subject: Re: [PATCH 1/2] tcg: Search includes from the project root source directory To: Stefan Weil , qemu-devel@nongnu.org, Markus Armbruster , Richard Henderson Cc: Aurelien Jarno , qemu-ppc@nongnu.org, Peter Maydell , Riku Voipio , Aleksandar Rikalo , Andrzej Zaborowski , Laurent Vivier , Paolo Bonzini , Max Filippov , Claudio Fontana , qemu-s390x@nongnu.org, Sagar Karandikar , Marek Vasut , Artyom Tarasenko , Chris Wulff , Bastian Koppelmann , Cornelia Huck , Palmer Dabbelt , Richard Henderson , qemu-arm@nongnu.org, "Edgar E. Iglesias" , Mark Cave-Ayland , David Hildenbrand , Anthony Green , Eduardo Habkost , Alistair Francis , Stafford Horne , Guan Xuetao , Michael Walle , Aleksandar Markovic , David Gibson , qemu-riscv@nongnu.org References: <20191230090900.446-1-philmd@redhat.com> <20191230090900.446-2-philmd@redhat.com> <273bf2e5-1223-3d01-f930-394195c037e4@weilnetz.de> From: =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= Message-ID: <64c2434d-3b2b-1a3e-5358-e4b5acfbe8e8@redhat.com> Date: Mon, 30 Dec 2019 10:59:40 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.2.2 MIME-Version: 1.0 In-Reply-To: <273bf2e5-1223-3d01-f930-394195c037e4@weilnetz.de> Content-Language: en-US X-MC-Unique: wWAka8_AMPmBCdKu6lachg-1 X-Mimecast-Spam-Score: 0 Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 207.211.31.81 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 30 Dec 2019 09:59:49 -0000 Hi Stefan, On 12/30/19 10:53 AM, Stefan Weil wrote: > Am 30.12.19 um 10:08 schrieb Philippe Mathieu-Daud=C3=A9: >=20 > [...] >=20 >> tcg/tcg-op.h | 2 +- >> tcg/tcg.h | 4 ++-- >> tcg/tcg-common.c | 2 +- >> tcg/tcg-op-gvec.c | 8 ++++---- >> tcg/tcg-op-vec.c | 6 +++--- >> tcg/tcg-op.c | 6 +++--- >> tcg/tcg.c | 2 +- >> tcg/tci.c | 2 +- >=20 >=20 > Source files in the tcg directory should not need any change because > they find include files in the same directory without searching. >=20 > If we add a tcg/ include file prefix for them as well, that has the > advantage that it might look prettier and more uniform, but it has the > disadvantage of requiring a search by the preprocessor. Yeah, I was not sure about these specific files. My first attempt was=20 without modifying them, but then I thought it would be better to keep=20 the codebase uniform, as you said. >=20 > I'd prefer not changing those files. OK, I'll wait to see what Richard/Markus prefer. > Regards and best wished for 2020 Thanks ;) From MAILER-DAEMON Mon Dec 30 05:33:43 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1ilsMp-0007Xj-0B for mharc-qemu-arm@gnu.org; Mon, 30 Dec 2019 05:33:43 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:58909) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ilsMm-0007Wz-M1 for qemu-arm@nongnu.org; Mon, 30 Dec 2019 05:33:41 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ilsMk-0002CR-MK for qemu-arm@nongnu.org; Mon, 30 Dec 2019 05:33:39 -0500 Received: from us-smtp-delivery-1.mimecast.com ([207.211.31.120]:46487 helo=us-smtp-1.mimecast.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1ilsMk-0002C2-JK for qemu-arm@nongnu.org; Mon, 30 Dec 2019 05:33:38 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1577702018; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: in-reply-to:in-reply-to:references:references; bh=osz1+gLyr114GefbdMEHHWsIMT6EPaU/DWBMxBOMOeQ=; b=RE2TvwwdhpBUua6EMr2t/AOYMF1f9rTYGZdEyyDDY3mBTk4uhkGqqOHLwiaRyLBC/juJLY 3osUysJ9ujtRE3Lwr052ewS/2Pu6Z1JaClKGz2kz6x52qzeiDFX0SQi4oMZjwW4MGm38mq q5t0rvS4Ts8myTmf1riVDWDkQDrvA5I= Received: from mail-ed1-f69.google.com (mail-ed1-f69.google.com [209.85.208.69]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-189-HmYTunk-M-qACIwoirQWaw-1; Mon, 30 Dec 2019 05:33:34 -0500 Received: by mail-ed1-f69.google.com with SMTP id c2so20136024edx.19 for ; Mon, 30 Dec 2019 02:33:34 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=osz1+gLyr114GefbdMEHHWsIMT6EPaU/DWBMxBOMOeQ=; b=ZNhvJ8vzmWA1jPlsPTHoLw72nCo9gSbvkz3Kb5+SkSB+kmoOgfdjoG/rJZtq5vUJPg 0iT8rz7xubLZlmzplwt6pmwf48Q0IxiDeUHmo5+XbuOgVSgcIjo7UOUa/Q/fcohaFsm3 4WkwnWTsYGJ+yQvueooZpZgTNFYyOMQ3rK7pJ7WjmV/nbRdCL2GTWZrMm16dSyK+ePiT fOsaSo5l4Szh5O/SGLCDx1QmfwC5WXNy9Z8jBrAPnxRAm6EQaKdXICcMRfKH5EGsVwUb xC475WXHhs17e4tvwZz96IxXPWI7TLtLZhMi6q0lXrVDT5q9nC9R9hK5PDrGM8IKhFHO fhxA== X-Gm-Message-State: APjAAAXb9VYZCdPuvePsA74WzH6KB0F3cBMz2U1e5C3dfcFHANXf8XSK /J/7BWnEXNWII3TAZs0+XIVgVFmW13AOSAtK+GFoKjhVfvNg2g/y8bnnpQkfIMgFAtdANczSFl7 B6Ibm7d8Bf7dkgxjAk87VMb96ZRAW X-Received: by 2002:a17:906:7fd0:: with SMTP id r16mr67457070ejs.319.1577702013586; Mon, 30 Dec 2019 02:33:33 -0800 (PST) X-Google-Smtp-Source: APXvYqw1w2ArI0LpE0GqHdw+xKfIcqSZqxPDmQ0Rqbq3Ub7H8CXU01ZbI2JJ/85FUZ9NjgX/OwTJ+TiYi3EVqCnrUxc= X-Received: by 2002:a17:906:7fd0:: with SMTP id r16mr67457016ejs.319.1577702013308; Mon, 30 Dec 2019 02:33:33 -0800 (PST) MIME-Version: 1.0 References: <20191230090900.446-1-philmd@redhat.com> <20191230090900.446-2-philmd@redhat.com> <273bf2e5-1223-3d01-f930-394195c037e4@weilnetz.de> <64c2434d-3b2b-1a3e-5358-e4b5acfbe8e8@redhat.com> In-Reply-To: <64c2434d-3b2b-1a3e-5358-e4b5acfbe8e8@redhat.com> From: Paolo Bonzini Date: Mon, 30 Dec 2019 10:33:21 +0000 Message-ID: Subject: Re: [PATCH 1/2] tcg: Search includes from the project root source directory To: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= Cc: Stefan Weil , qemu-devel , Markus Armbruster , Richard Henderson , Aurelien Jarno , qemu-ppc@nongnu.org, Peter Maydell , Riku Voipio , Aleksandar Rikalo , Andrzej Zaborowski , Laurent Vivier , Max Filippov , Claudio Fontana , qemu-s390x@nongnu.org, Sagar Karandikar , Marek Vasut , Artyom Tarasenko , Chris Wulff , Bastian Koppelmann , Cornelia Huck , Palmer Dabbelt , Richard Henderson , qemu-arm@nongnu.org, "Edgar E. Iglesias" , Mark Cave-Ayland , David Hildenbrand , Anthony Green , Eduardo Habkost , Alistair Francis , Stafford Horne , Guan Xuetao , Michael Walle , Aleksandar Markovic , David Gibson , qemu-riscv@nongnu.org X-MC-Unique: HmYTunk-M-qACIwoirQWaw-1 X-Mimecast-Spam-Score: 0 Content-Type: multipart/alternative; boundary="00000000000010b1de059ae96084" X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 207.211.31.120 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 30 Dec 2019 10:33:42 -0000 --00000000000010b1de059ae96084 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Il lun 30 dic 2019, 09:59 Philippe Mathieu-Daud=C3=A9 h= a scritto: > > I'd prefer not changing those files. > > OK, I'll wait to see what Richard/Markus prefer. > I think it's best if you keep the include directives as-is for files only needed from tcg/, and move the other headers (those that are needed from other directories only) to include/tcg. Thanks and happy new year! Paolo > > > Regards and best wished for 2020 > > Thanks ;) > > --00000000000010b1de059ae96084 Content-Type: text/html; charset="UTF-8" Content-Transfer-Encoding: quoted-printable


Il lun 30 dic 2019, 09:59 Philippe Mathieu-Daud=C3=A9 = <philmd@redhat.com> ha scrit= to:
> I'd prefer not changin= g those files.

OK, I'll wait to see what Richard/Markus prefer.
=

I think it's best i= f you keep the include directives as-is for files only needed from tcg/, an= d move the other headers (those that are needed from other directories only= ) to include/tcg.

Thanks= and happy new year!

Pao= lo

> Regards and best wished for 2020

Thanks ;)

--00000000000010b1de059ae96084-- From MAILER-DAEMON Mon Dec 30 06:10:02 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1ilsvy-0005UW-0P for mharc-qemu-arm@gnu.org; Mon, 30 Dec 2019 06:10:02 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:35290) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ilsvv-0005SJ-Sn for qemu-arm@nongnu.org; Mon, 30 Dec 2019 06:10:00 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ilsvu-00037K-R1 for qemu-arm@nongnu.org; Mon, 30 Dec 2019 06:09:59 -0500 Received: from mail-wm1-x32f.google.com ([2a00:1450:4864:20::32f]:55280) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ilsvs-00035q-JP; Mon, 30 Dec 2019 06:09:56 -0500 Received: by mail-wm1-x32f.google.com with SMTP id b19so13627535wmj.4; Mon, 30 Dec 2019 03:09:56 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=jFReq7E825k+36Vj4KnB4Ttzw5P5x4uoxxDy/kudsL8=; b=QcyPq1zcjS0NG3GzjIvcKo0woTeiWd3MDk/avS3IP7Zqqp9UqM9b8V2qPA0MrlGps9 VMcV2ToEoRC6RD0hGlx0yju5JQkxNJYzgsV1n7uD2IJssxZN2a4xCFuCdl9KJNswopdI osaF3zzSdKi9kyzUweJkiu6gjEP4yWlGh2y/HqpXpASyikN8CdmJq9T6S4vmaQ7SL2zf RaSejGuWaG46K9KzYz6eSChBljQnA/lHZDzh+Ms3iPFphROM5SG03LkEc7aFxeqevRD+ 6KZ1L8fGVTKdq0NzH3fx0WpApgSjuh8uYSfdP06Gk+52w6aVjyq7PTVcCZEEK1Vp+QUb aZFg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :mime-version:content-transfer-encoding; bh=jFReq7E825k+36Vj4KnB4Ttzw5P5x4uoxxDy/kudsL8=; b=M8BJ1JB+JIIex8oOJ6tOpKuApFyriE4DANxj7+K+xk9jHzBE54DkXqsq+M1wX+yOTZ dT1xhLbbq7v8g9x1nCyeimWVZ8YgxtlzbfMtUAISCU2EqiIOTCHJvUFIdhtnjHLoKGcy P8y6Aa0DulGKSaFON6vGVdQt5PdTQCJEmd/OFWy5an0Fi5ca4j7whDhGWe4F9LVYImwA zJAoxj4ImABxdE7ZEtSZrtyjFVA8s0NYg1It/Osh3dOktUKHtVNifq2Xcd7IigVayrLq tychNOtQw8GUaoLI3MtmZFcVL5dLnnDJcPpvn4ytlCCIiItBTNvniwKfwcpMhgIqP8yC yXww== X-Gm-Message-State: APjAAAVcgOVZYa4PePiaxzaEfZwne8GK1eENXWVkw9Aq/dy9foh5LiwJ WJJ1nHUEtXynQJL5h3ee02/ON+sK11w= X-Google-Smtp-Source: APXvYqyoIg7m3paOrdLpc0D+CvDPqx8OfdgI6oFyqe2vAmERKkmCKub+HqFQ5Sh7ytkUuJ5xZCwElw== X-Received: by 2002:a7b:cc82:: with SMTP id p2mr35056743wma.159.1577704195299; Mon, 30 Dec 2019 03:09:55 -0800 (PST) Received: from x1w.redhat.com ([2a01:cb18:8372:6b00:691b:aac5:8837:d4da]) by smtp.gmail.com with ESMTPSA id p15sm20442738wma.40.2019.12.30.03.09.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 30 Dec 2019 03:09:54 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Beniamino Galvani , Niek Linnenbank , Willian Rampazzo , Peter Maydell , Wainer dos Santos Moschetta , qemu-arm@nongnu.org, Cleber Rosa , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH 0/6] hw/arm/cubieboard: Few cleanups, add acceptance tests Date: Mon, 30 Dec 2019 12:09:47 +0100 Message-Id: <20191230110953.25496-1-f4bug@amsat.org> X-Mailer: git-send-email 2.21.0 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 8bit X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::32f X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 30 Dec 2019 11:10:01 -0000 After looking at Niek Linnenbank implementation of the Allwinner H3 [1], I looked what is common in the A10 [2]. Add some tests before modifying the code further. [1] https://www.mail-archive.com/qemu-devel@nongnu.org/msg665532.html [2] https://www.mail-archive.com/qemu-devel@nongnu.org/msg666809.html Philippe Mathieu-Daudé (6): tests/boot_linux_console: Add initrd test for the CubieBoard tests/boot_linux_console: Add a SD card test for the CubieBoard hw/arm/allwinner-a10: Move SoC definitions out of header hw/arm/allwinner-a10: Simplify by passing IRQs with qdev_pass_gpios() hw/arm/allwinner-a10: Remove local qemu_irq variables hw/arm/cubieboard: Disable unsupported M-USB in device tree blob [RFC] include/hw/arm/allwinner-a10.h | 7 --- hw/arm/allwinner-a10.c | 39 ++++++------ hw/arm/cubieboard.c | 24 ++++++++ tests/acceptance/boot_linux_console.py | 85 ++++++++++++++++++++++++++ 4 files changed, 130 insertions(+), 25 deletions(-) -- 2.21.0 From MAILER-DAEMON Mon Dec 30 06:10:06 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1ilsw2-0005bd-2o for mharc-qemu-arm@gnu.org; Mon, 30 Dec 2019 06:10:06 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:35332) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ilsvy-0005VT-EY for qemu-arm@nongnu.org; Mon, 30 Dec 2019 06:10:03 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ilsvw-000389-Qg for qemu-arm@nongnu.org; Mon, 30 Dec 2019 06:10:02 -0500 Received: from mail-wr1-x441.google.com ([2a00:1450:4864:20::441]:43680) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ilsvt-00036q-RC; Mon, 30 Dec 2019 06:09:57 -0500 Received: by mail-wr1-x441.google.com with SMTP id d16so32323473wre.10; Mon, 30 Dec 2019 03:09:57 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=0VHBWRhd3KqP211ZzR+SgyokvYmniIT+KSexWzYW+s8=; b=PpvCtBNsAsOshF6Mh6IJ76rG1Vk1YFBPmaasDrb0/9508RJjWDIS6nlPBmLwchlMLI kX37HKxWQUMyB5sfJBjGjfsC8peWdOrHk8r+zPjHFTXGoF7zrPzjOWO2LAM8q1bxB5Gr sxCJa/d/5rfJGQsc7kMtn8MsjZoBZcs71BiG2OSlJ1GvHoDUNf8gF1edoklnSceV29D8 yx7HEif7sb9DVs/jgmLMR09GXog7r2NQpuJoh2YBpj+z61ig+k9/rtwiHsSWe5p9aJNg oZmO+tkKDwNn9sPeIi1BjhF5NfMx5mdqpQIqWAevyOfhZ5J1q1kbUJRZU8tqs+j987XI 5Gug== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=0VHBWRhd3KqP211ZzR+SgyokvYmniIT+KSexWzYW+s8=; b=dnxvAUf55+95WFfpKPeVn7EdwjyYzDC7GHux5RjtwqY11QjoFj3yV3aSM8HeaI28Vx xOyafUt530/y0ham7VLPyQuVS60NSAqgFEjHqLfJzrFERIG1Bx+KrMsIQcEAK08VB3eL OV30u1oIJmd2yPwP+X4dJXhQ3W+grap2tvNgBD0iXk34Sv9/M4Wa1o3vcCQuK55lW8Jq F6OHaL8fEuQqXLqvp+UMtp1FO2ZvN1/oAoUgiK2UoFDka9Dkl1AUTAcBjfWK+6gEQp6f KT8Im2hPmLqUQ/MCXjURZ3wlXX66mFUIR2HVzNdFSsYsbAYcT1jKsUWZ+N+s2wV0hBpr KmJg== X-Gm-Message-State: APjAAAVSMyFLLNZmVNZOxLOTVdPN5It1LL8pJV9rulWip7MD6nGhnTGP bRmRuB5Jnz1Q0NL82OKfZwAChRVJvm4= X-Google-Smtp-Source: APXvYqyQiyZqj0JWubnyplhi7MmFgi2PRddKeEy1ba6GkWj40ZHpNhdJiqq/MK7VsB1Wc5S8Ky2Ccg== X-Received: by 2002:a5d:5452:: with SMTP id w18mr51941433wrv.333.1577704196590; Mon, 30 Dec 2019 03:09:56 -0800 (PST) Received: from x1w.redhat.com ([2a01:cb18:8372:6b00:691b:aac5:8837:d4da]) by smtp.gmail.com with ESMTPSA id p15sm20442738wma.40.2019.12.30.03.09.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 30 Dec 2019 03:09:56 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Beniamino Galvani , Niek Linnenbank , Willian Rampazzo , Peter Maydell , Wainer dos Santos Moschetta , qemu-arm@nongnu.org, Cleber Rosa , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH 1/6] tests/boot_linux_console: Add initrd test for the CubieBoard Date: Mon, 30 Dec 2019 12:09:48 +0100 Message-Id: <20191230110953.25496-2-f4bug@amsat.org> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20191230110953.25496-1-f4bug@amsat.org> References: <20191230110953.25496-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 8bit X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::441 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 30 Dec 2019 11:10:04 -0000 This test boots a Linux kernel on a CubieBoard and verify the serial output is working. The kernel image and DeviceTree blob are built by the Armbian project (based on Debian): https://docs.armbian.com/Developer-Guide_Build-Preparation/ The cpio image used comes from the linux-build-test project: https://github.com/groeck/linux-build-test If ARM is a target being built, "make check-acceptance" will automatically include this test by the use of the "arch:arm" tags. Alternatively, this test can be run using: $ avocado --show=console run -t machine:cubieboard tests/acceptance/boot_linux_console.py console: Uncompressing Linux... done, booting the kernel. console: Booting Linux on physical CPU 0x0 console: Linux version 4.20.7-sunxi (root@armbian.com) (gcc version 7.2.1 20171011 (Linaro GCC 7.2-2017.11)) #5.75 SMP Fri Feb 8 09:02:10 CET 2019 console: CPU: ARMv7 Processor [410fc080] revision 0 (ARMv7), cr=50c5387d console: CPU: PIPT / VIPT nonaliasing data cache, VIPT nonaliasing instruction cache console: OF: fdt: Machine model: Cubietech Cubieboard [...] console: Boot successful. console: cat /proc/cpuinfo console: / # cat /proc/cpuinfo console: processor : 0 console: model name : ARMv7 Processor rev 0 (v7l) console: BogoMIPS : 832.51 [...] console: Hardware : Allwinner sun4i/sun5i Families console: Revision : 0000 console: Serial : 0000000000000000 console: cat /proc/iomem console: / # cat /proc/iomem console: 01c00000-01c0002f : system-control@1c00000 console: 01c02000-01c02fff : dma-controller@1c02000 console: 01c05000-01c05fff : spi@1c05000 console: 01c0b080-01c0b093 : mdio@1c0b080 console: 01c0c000-01c0cfff : lcd-controller@1c0c000 console: 01c0d000-01c0dfff : lcd-controller@1c0d000 console: 01c0f000-01c0ffff : mmc@1c0f000 [...] PASS (54.35 s) Signed-off-by: Philippe Mathieu-Daudé --- tests/acceptance/boot_linux_console.py | 41 ++++++++++++++++++++++++++ 1 file changed, 41 insertions(+) diff --git a/tests/acceptance/boot_linux_console.py b/tests/acceptance/boot_linux_console.py index 9c6aa2040a..4643f60e37 100644 --- a/tests/acceptance/boot_linux_console.py +++ b/tests/acceptance/boot_linux_console.py @@ -400,6 +400,47 @@ class BootLinuxConsole(Test): self.wait_for_console_pattern('Boot successful.') # TODO user command, for now the uart is stuck + def test_arm_cubieboard_initrd(self): + """ + :avocado: tags=arch:arm + :avocado: tags=machine:cubieboard + """ + deb_url = ('https://apt.armbian.com/pool/main/l/' + 'linux-4.20.7-sunxi/linux-image-dev-sunxi_5.75_armhf.deb') + deb_hash = '1334c29c44d984ffa05ed10de8c3361f33d78315' + deb_path = self.fetch_asset(deb_url, asset_hash=deb_hash) + kernel_path = self.extract_from_deb(deb_path, + '/boot/vmlinuz-4.20.7-sunxi') + dtb_path = '/usr/lib/linux-image-dev-sunxi/sun4i-a10-cubieboard.dtb' + dtb_path = self.extract_from_deb(deb_path, dtb_path) + initrd_url = ('https://github.com/groeck/linux-build-test/raw/' + '2eb0a73b5d5a28df3170c546ddaaa9757e1e0848/rootfs/' + 'arm/rootfs-armv5.cpio.gz') + initrd_hash = '2b50f1873e113523967806f4da2afe385462ff9b' + initrd_path_gz = self.fetch_asset(initrd_url, asset_hash=initrd_hash) + initrd_path = os.path.join(self.workdir, 'rootfs.cpio') + archive.gzip_uncompress(initrd_path_gz, initrd_path) + + self.vm.set_console() + kernel_command_line = (self.KERNEL_COMMON_COMMAND_LINE + + 'console=ttyS0,115200 ' + 'usbcore.nousb ' + 'panic=-1 noreboot') + self.vm.add_args('-kernel', kernel_path, + '-dtb', dtb_path, + '-initrd', initrd_path, + '-append', kernel_command_line, + '-no-reboot') + self.vm.launch() + self.wait_for_console_pattern('Boot successful.') + + exec_command_and_wait_for_pattern(self, 'cat /proc/cpuinfo', + 'Allwinner sun4i/sun5i') + exec_command_and_wait_for_pattern(self, 'cat /proc/iomem', + 'system-control@1c00000') + exec_command_and_wait_for_pattern(self, 'reboot', + 'reboot: Restarting system') + def test_s390x_s390_ccw_virtio(self): """ :avocado: tags=arch:s390x -- 2.21.0 From MAILER-DAEMON Mon Dec 30 06:10:07 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1ilsw3-0005eV-OZ for mharc-qemu-arm@gnu.org; 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Mon, 30 Dec 2019 03:09:58 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Beniamino Galvani , Niek Linnenbank , Willian Rampazzo , Peter Maydell , Wainer dos Santos Moschetta , qemu-arm@nongnu.org, Cleber Rosa , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH 3/6] hw/arm/allwinner-a10: Move SoC definitions out of header Date: Mon, 30 Dec 2019 12:09:50 +0100 Message-Id: <20191230110953.25496-4-f4bug@amsat.org> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20191230110953.25496-1-f4bug@amsat.org> References: <20191230110953.25496-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 8bit X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::343 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 30 Dec 2019 11:10:06 -0000 These definitions are specific to the A10 SoC and don't need to be exported to the different Allwinner peripherals. Signed-off-by: Philippe Mathieu-Daudé --- include/hw/arm/allwinner-a10.h | 6 ------ hw/arm/allwinner-a10.c | 6 ++++++ 2 files changed, 6 insertions(+), 6 deletions(-) diff --git a/include/hw/arm/allwinner-a10.h b/include/hw/arm/allwinner-a10.h index 7d2d215630..941c61e533 100644 --- a/include/hw/arm/allwinner-a10.h +++ b/include/hw/arm/allwinner-a10.h @@ -12,12 +12,6 @@ #include "target/arm/cpu.h" -#define AW_A10_PIC_REG_BASE 0x01c20400 -#define AW_A10_PIT_REG_BASE 0x01c20c00 -#define AW_A10_UART0_REG_BASE 0x01c28000 -#define AW_A10_EMAC_BASE 0x01c0b000 -#define AW_A10_SATA_BASE 0x01c18000 - #define AW_A10_SDRAM_BASE 0x40000000 #define TYPE_AW_A10 "allwinner-a10" diff --git a/hw/arm/allwinner-a10.c b/hw/arm/allwinner-a10.c index 118032c8c7..0f1af5a880 100644 --- a/hw/arm/allwinner-a10.c +++ b/hw/arm/allwinner-a10.c @@ -25,6 +25,12 @@ #include "hw/misc/unimp.h" #include "sysemu/sysemu.h" +#define AW_A10_PIC_REG_BASE 0x01c20400 +#define AW_A10_PIT_REG_BASE 0x01c20c00 +#define AW_A10_UART0_REG_BASE 0x01c28000 +#define AW_A10_EMAC_BASE 0x01c0b000 +#define AW_A10_SATA_BASE 0x01c18000 + static void aw_a10_init(Object *obj) { AwA10State *s = AW_A10(obj); -- 2.21.0 From MAILER-DAEMON Mon Dec 30 06:10:09 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1ilsw5-0005hg-GA for mharc-qemu-arm@gnu.org; Mon, 30 Dec 2019 06:10:09 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:35373) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ilsw0-0005Z6-K9 for qemu-arm@nongnu.org; Mon, 30 Dec 2019 06:10:06 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ilsvy-000397-LX for qemu-arm@nongnu.org; Mon, 30 Dec 2019 06:10:04 -0500 Received: from mail-wr1-x443.google.com ([2a00:1450:4864:20::443]:33679) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ilsvv-00037F-4d; Mon, 30 Dec 2019 06:09:59 -0500 Received: by mail-wr1-x443.google.com with SMTP id b6so32383486wrq.0; Mon, 30 Dec 2019 03:09:59 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=lDvl9OWYCQ+LaIr8sH3FxUkOS9yo66/i86UY7kFYO98=; b=MFV8HTDgPYP4dOq+ORH7gOSXdEnuV93fMKiChRUMlv0CJ+RJOZzI2WfapcMkUFwyvm 96jf64uNwdfCoArtuhFJBb3KCKrUfvJ2VQ2LRxnIbgUIGbp4wLMksbtr+jNOVqMShUpX haaghnbORtrIaQweP5wD7Azardn2xduDvuvtk2dP+ZQpBSQ7DR3GM1qUZoA6EQqjw6/y sT8/NCc93PZ/OPbYRtovWDdWc9CdtawXui7v9CNwRPG/MVFwE6zT3YzqvPLex2DN4i27 TEyxruwg6jkQwrHWcf70ShKxajl8/29SVlKLrpqa/VZg21gO60MSDgSoqljVlimCYr+/ CMYw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=lDvl9OWYCQ+LaIr8sH3FxUkOS9yo66/i86UY7kFYO98=; b=kHgfr+GwODoJy//Xd2LZC/Qf3ao+LAIR2+kZODqDthAWp01NSBg404+1Yv1DmAnc03 DtTbaveO+kU2+BNd5G+kSMRvfPL2w1jvoLQ6+RQranInWs/+KzTT6rqcvPjrtj4lvEpt 0RBBA46mbesbwx24S3ceUr/3AqTXJcfAhDI+/KVzFtdhv0j5+lqdNy3bKt7rJNcBUQOQ fNAXyuqChXe+IZGrLqLe3lrZtUGbKQBgwEM1zcxS0Caw1mxMepgZD/bNs6g7zVd6XFLj lxW/cJ6WlCIBXJSPu2P21pZzj5DxwHi4erwYLT4599So0BvSyZveSv3QVUper+OYc5U0 STng== X-Gm-Message-State: APjAAAWgzb9m8k+ISFMyyfcKSZ5N8VvooN6C2EGHkwt4Z0FbJWdNo3eU +5iHXONvEZythU3KN+IkL2+Q5ylYxl0= X-Google-Smtp-Source: APXvYqzVxi8rRQLiB8oWvny3QTy1St40R7j78PvKI0GFN7i82av/g1vd7X6bRaC3Rcj0/82Qu32hAA== X-Received: by 2002:a5d:4cc9:: with SMTP id c9mr64528295wrt.70.1577704197905; Mon, 30 Dec 2019 03:09:57 -0800 (PST) Received: from x1w.redhat.com ([2a01:cb18:8372:6b00:691b:aac5:8837:d4da]) by smtp.gmail.com with ESMTPSA id p15sm20442738wma.40.2019.12.30.03.09.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 30 Dec 2019 03:09:57 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Beniamino Galvani , Niek Linnenbank , Willian Rampazzo , Peter Maydell , Wainer dos Santos Moschetta , qemu-arm@nongnu.org, Cleber Rosa , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH 2/6] tests/boot_linux_console: Add a SD card test for the CubieBoard Date: Mon, 30 Dec 2019 12:09:49 +0100 Message-Id: <20191230110953.25496-3-f4bug@amsat.org> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20191230110953.25496-1-f4bug@amsat.org> References: <20191230110953.25496-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 8bit X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::443 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 30 Dec 2019 11:10:07 -0000 The kernel image and DeviceTree blob are built by the Armbian project (based on Debian): https://docs.armbian.com/Developer-Guide_Build-Preparation/ The cpio image used comes from the linux-build-test project: https://github.com/groeck/linux-build-test If ARM is a target being built, "make check-acceptance" will automatically include this test by the use of the "arch:arm" tags. Alternatively, this test can be run using: $ avocado --show=console run -t machine:cubieboard tests/acceptance/boot_linux_console.py console: Uncompressing Linux... done, booting the kernel. console: Booting Linux on physical CPU 0x0 console: Linux version 4.20.7-sunxi (root@armbian.com) (gcc version 7.2.1 20171011 (Linaro GCC 7.2-2017.11)) #5.75 SMP Fri Feb 8 09:02:10 CET 2019 [...] console: ahci-sunxi 1c18000.sata: Linked as a consumer to regulator.4 console: ahci-sunxi 1c18000.sata: controller can't do 64bit DMA, forcing 32bit console: ahci-sunxi 1c18000.sata: AHCI 0001.0000 32 slots 1 ports 1.5 Gbps 0x1 impl platform mode console: ahci-sunxi 1c18000.sata: flags: ncq only console: scsi host0: ahci-sunxi console: ata1: SATA max UDMA/133 mmio [mem 0x01c18000-0x01c18fff] port 0x100 irq 27 console: of_cfs_init console: of_cfs_init: OK console: vcc3v0: disabling console: vcc5v0: disabling console: usb1-vbus: disabling console: usb2-vbus: disabling console: ata1: SATA link up 1.5 Gbps (SStatus 113 SControl 300) console: ata1.00: ATA-7: QEMU HARDDISK, 2.5+, max UDMA/100 console: ata1.00: 40960 sectors, multi 16: LBA48 NCQ (depth 32) console: ata1.00: applying bridge limits console: ata1.00: configured for UDMA/100 console: scsi 0:0:0:0: Direct-Access ATA QEMU HARDDISK 2.5+ PQ: 0 ANSI: 5 console: sd 0:0:0:0: Attached scsi generic sg0 type 0 console: sd 0:0:0:0: [sda] 40960 512-byte logical blocks: (21.0 MB/20.0 MiB) console: sd 0:0:0:0: [sda] Write Protect is off console: sd 0:0:0:0: [sda] Write cache: enabled, read cache: enabled, doesn't support DPO or FUA console: sd 0:0:0:0: [sda] Attached SCSI disk console: EXT4-fs (sda): mounting ext2 file system using the ext4 subsystem console: EXT4-fs (sda): mounted filesystem without journal. Opts: (null) console: VFS: Mounted root (ext2 filesystem) readonly on device 8:0. [...] console: cat /proc/partitions console: / # cat /proc/partitions console: major minor #blocks name console: 1 0 4096 ram0 console: 1 1 4096 ram1 console: 1 2 4096 ram2 console: 1 3 4096 ram3 console: 8 0 20480 sda console: reboot console: / # reboot [...] console: sd 0:0:0:0: [sda] Synchronizing SCSI cache console: reboot: Restarting system PASS (48.39 s) Signed-off-by: Philippe Mathieu-Daudé --- tests/acceptance/boot_linux_console.py | 44 ++++++++++++++++++++++++++ 1 file changed, 44 insertions(+) diff --git a/tests/acceptance/boot_linux_console.py b/tests/acceptance/boot_linux_console.py index 4643f60e37..e40b84651b 100644 --- a/tests/acceptance/boot_linux_console.py +++ b/tests/acceptance/boot_linux_console.py @@ -441,6 +441,50 @@ class BootLinuxConsole(Test): exec_command_and_wait_for_pattern(self, 'reboot', 'reboot: Restarting system') + def test_arm_cubieboard_sata(self): + """ + :avocado: tags=arch:arm + :avocado: tags=machine:cubieboard + """ + deb_url = ('https://apt.armbian.com/pool/main/l/' + 'linux-4.20.7-sunxi/linux-image-dev-sunxi_5.75_armhf.deb') + deb_hash = '1334c29c44d984ffa05ed10de8c3361f33d78315' + deb_path = self.fetch_asset(deb_url, asset_hash=deb_hash) + kernel_path = self.extract_from_deb(deb_path, + '/boot/vmlinuz-4.20.7-sunxi') + dtb_path = '/usr/lib/linux-image-dev-sunxi/sun4i-a10-cubieboard.dtb' + dtb_path = self.extract_from_deb(deb_path, dtb_path) + rootfs_url = ('https://github.com/groeck/linux-build-test/raw/' + '2eb0a73b5d5a28df3170c546ddaaa9757e1e0848/rootfs/' + 'arm/rootfs-armv5.ext2.gz') + rootfs_hash = '093e89d2b4d982234bf528bc9fb2f2f17a9d1f93' + rootfs_path_gz = self.fetch_asset(rootfs_url, asset_hash=rootfs_hash) + rootfs_path = os.path.join(self.workdir, 'rootfs.cpio') + archive.gzip_uncompress(rootfs_path_gz, rootfs_path) + + self.vm.set_console() + kernel_command_line = (self.KERNEL_COMMON_COMMAND_LINE + + 'console=ttyS0,115200 ' + 'usbcore.nousb ' + 'root=/dev/sda ro ' + 'panic=-1 noreboot') + self.vm.add_args('-kernel', kernel_path, + '-dtb', dtb_path, + '-drive', 'if=none,format=raw,id=disk0,file=' + + rootfs_path, + '-device', 'ide-hd,bus=ide.0,drive=disk0', + '-append', kernel_command_line, + '-no-reboot') + self.vm.launch() + self.wait_for_console_pattern('Boot successful.') + + exec_command_and_wait_for_pattern(self, 'cat /proc/cpuinfo', + 'Allwinner sun4i/sun5i') + exec_command_and_wait_for_pattern(self, 'cat /proc/partitions', + 'sda') + exec_command_and_wait_for_pattern(self, 'reboot', + 'reboot: Restarting system') + def test_s390x_s390_ccw_virtio(self): """ :avocado: tags=arch:s390x -- 2.21.0 From MAILER-DAEMON Mon Dec 30 06:10:10 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1ilsw6-0005jd-O5 for mharc-qemu-arm@gnu.org; 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Mon, 30 Dec 2019 03:10:01 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Beniamino Galvani , Niek Linnenbank , Willian Rampazzo , Peter Maydell , Wainer dos Santos Moschetta , qemu-arm@nongnu.org, Cleber Rosa , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH 5/6] hw/arm/allwinner-a10: Remove local qemu_irq variables Date: Mon, 30 Dec 2019 12:09:52 +0100 Message-Id: <20191230110953.25496-6-f4bug@amsat.org> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20191230110953.25496-1-f4bug@amsat.org> References: <20191230110953.25496-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 8bit X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::444 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 30 Dec 2019 11:10:09 -0000 We won't reuse the CPU IRQ/FIQ variables. Simplify by calling qdev_get_gpio_in() in place. Signed-off-by: Philippe Mathieu-Daudé --- hw/arm/allwinner-a10.c | 9 ++++----- 1 file changed, 4 insertions(+), 5 deletions(-) diff --git a/hw/arm/allwinner-a10.c b/hw/arm/allwinner-a10.c index 966fbd4a6e..1cde165611 100644 --- a/hw/arm/allwinner-a10.c +++ b/hw/arm/allwinner-a10.c @@ -55,7 +55,6 @@ static void aw_a10_realize(DeviceState *dev, Error **errp) { AwA10State *s = AW_A10(dev); SysBusDevice *sysbusdev; - qemu_irq fiq, irq; Error *err = NULL; object_property_set_bool(OBJECT(&s->cpu), true, "realized", &err); @@ -63,8 +62,6 @@ static void aw_a10_realize(DeviceState *dev, Error **errp) error_propagate(errp, err); return; } - irq = qdev_get_gpio_in(DEVICE(&s->cpu), ARM_CPU_IRQ); - fiq = qdev_get_gpio_in(DEVICE(&s->cpu), ARM_CPU_FIQ); object_property_set_bool(OBJECT(&s->intc), true, "realized", &err); if (err != NULL) { @@ -73,8 +70,10 @@ static void aw_a10_realize(DeviceState *dev, Error **errp) } sysbusdev = SYS_BUS_DEVICE(&s->intc); sysbus_mmio_map(sysbusdev, 0, AW_A10_PIC_REG_BASE); - sysbus_connect_irq(sysbusdev, 0, irq); - sysbus_connect_irq(sysbusdev, 1, fiq); + sysbus_connect_irq(sysbusdev, 0, + qdev_get_gpio_in(DEVICE(&s->cpu), ARM_CPU_IRQ)); + sysbus_connect_irq(sysbusdev, 1, + qdev_get_gpio_in(DEVICE(&s->cpu), ARM_CPU_FIQ)); qdev_pass_gpios(DEVICE(&s->intc), dev, NULL); object_property_set_bool(OBJECT(&s->timer), true, "realized", &err); -- 2.21.0 From MAILER-DAEMON Mon Dec 30 06:10:11 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1ilsw7-0005kj-BL for mharc-qemu-arm@gnu.org; Mon, 30 Dec 2019 06:10:11 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:35393) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ilsw2-0005bP-0A for qemu-arm@nongnu.org; Mon, 30 Dec 2019 06:10:07 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ilsw0-0003Al-JN for qemu-arm@nongnu.org; Mon, 30 Dec 2019 06:10:05 -0500 Received: from mail-wr1-x442.google.com ([2a00:1450:4864:20::442]:41477) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ilsvx-00038J-QE; Mon, 30 Dec 2019 06:10:01 -0500 Received: by mail-wr1-x442.google.com with SMTP id c9so32333596wrw.8; Mon, 30 Dec 2019 03:10:01 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=N8YaSe87ak8uhHmiFp5CcDUPJZv1Grr3iIYPennz/Fg=; b=pqAWoWpJK71sx/Jygy1TAsWw9WBir7sjma/NtvScrYwW4w/zun0VShlyr7KPOj5l1Y CdXaYT0yumPDS6/JYQE8DXzDHmQUqBb+HP3gVBKsB7as1SRH8kdnX+8HblR1byQg4UdD K5F2a8Zt45M/AfVo5DsHFRsM5Pi6cvyREax74Wp5hDSlriecEWZJT8D4wF4rWsWgBwtY HbST8dO7yrUfJ+YipMt1Y66DTm2gXV1GMTd2BqhcJVik2n33FXpc7mn1aft5xuCaCeug uyi+1A9VkOx2GTtqdp+Im3A7cVHtVKu2K5SgQ3L2GE5BTw5mZ86DSPV2tPd/M2/njnMW 0ALg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=N8YaSe87ak8uhHmiFp5CcDUPJZv1Grr3iIYPennz/Fg=; b=He3GvTrGmuugk1xtnljsgEhkXWhb3tXm0OtrW36ydsWfZo6MjMQ7jdnFQPK+oAv2OB GZo/N9cy6xtKaNH+QikWTqG0S3ZysJHtBQSbPHANJqJajswHNjBKIPdCIJNOjEm4CW4Z eQUePTdJlhkC9p1GlREi3U1j2ZKQX+zWv/IhD1GcgIoYOauO29ysajX0JYOeRGD2sFiq 5gYxPgaaru3o5a0obJSCGslQLy16rRCwjcZrtQ6HW6gUlDz7FAUZNheeAFVNwkjfhAY0 x4fsz8tIVyXAscgFBqAVArKnb/f0Ze4O+kzxwGqBs/5J7B8u2523Pv67SCMO+eaqTsGn 0yBw== X-Gm-Message-State: APjAAAX1CghQrOxKwLh7iqFI9Cn/YSZazqVtKN2rQl+TMD780j2T7356 jUXeCOtb5Bvjqaz1ccl1OS9xGXjEBQw= X-Google-Smtp-Source: APXvYqyzaM+xC09z7CU/Fu5tXjFqT9yeosSG2EHnEfpAuGzSfexIxtXgQ2RRt2IpyTeN9BIw0fj1nw== X-Received: by 2002:a5d:488c:: with SMTP id g12mr65591723wrq.67.1577704200633; Mon, 30 Dec 2019 03:10:00 -0800 (PST) Received: from x1w.redhat.com ([2a01:cb18:8372:6b00:691b:aac5:8837:d4da]) by smtp.gmail.com with ESMTPSA id p15sm20442738wma.40.2019.12.30.03.09.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 30 Dec 2019 03:10:00 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Beniamino Galvani , Niek Linnenbank , Willian Rampazzo , Peter Maydell , Wainer dos Santos Moschetta , qemu-arm@nongnu.org, Cleber Rosa , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH 4/6] hw/arm/allwinner-a10: Simplify by passing IRQs with qdev_pass_gpios() Date: Mon, 30 Dec 2019 12:09:51 +0100 Message-Id: <20191230110953.25496-5-f4bug@amsat.org> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20191230110953.25496-1-f4bug@amsat.org> References: <20191230110953.25496-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 8bit X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::442 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 30 Dec 2019 11:10:08 -0000 By calling qdev_pass_gpios() we don't need to hold a copy of the IRQs from the INTC into the SoC state. Instead of filling an array of qemu_irq and passing it around, we can now directly call qdev_get_gpio_in() on the SoC. Signed-off-by: Philippe Mathieu-Daudé --- include/hw/arm/allwinner-a10.h | 1 - hw/arm/allwinner-a10.c | 24 +++++++++++------------- 2 files changed, 11 insertions(+), 14 deletions(-) diff --git a/include/hw/arm/allwinner-a10.h b/include/hw/arm/allwinner-a10.h index 941c61e533..40d0b1d9c0 100644 --- a/include/hw/arm/allwinner-a10.h +++ b/include/hw/arm/allwinner-a10.h @@ -23,7 +23,6 @@ typedef struct AwA10State { /*< public >*/ ARMCPU cpu; - qemu_irq irq[AW_A10_PIC_INT_NR]; AwA10PITState timer; AwA10PICState intc; AwEmacState emac; diff --git a/hw/arm/allwinner-a10.c b/hw/arm/allwinner-a10.c index 0f1af5a880..966fbd4a6e 100644 --- a/hw/arm/allwinner-a10.c +++ b/hw/arm/allwinner-a10.c @@ -55,7 +55,6 @@ static void aw_a10_realize(DeviceState *dev, Error **errp) { AwA10State *s = AW_A10(dev); SysBusDevice *sysbusdev; - uint8_t i; qemu_irq fiq, irq; Error *err = NULL; @@ -76,9 +75,7 @@ static void aw_a10_realize(DeviceState *dev, Error **errp) sysbus_mmio_map(sysbusdev, 0, AW_A10_PIC_REG_BASE); sysbus_connect_irq(sysbusdev, 0, irq); sysbus_connect_irq(sysbusdev, 1, fiq); - for (i = 0; i < AW_A10_PIC_INT_NR; i++) { - s->irq[i] = qdev_get_gpio_in(DEVICE(&s->intc), i); - } + qdev_pass_gpios(DEVICE(&s->intc), dev, NULL); object_property_set_bool(OBJECT(&s->timer), true, "realized", &err); if (err != NULL) { @@ -87,12 +84,12 @@ static void aw_a10_realize(DeviceState *dev, Error **errp) } sysbusdev = SYS_BUS_DEVICE(&s->timer); sysbus_mmio_map(sysbusdev, 0, AW_A10_PIT_REG_BASE); - sysbus_connect_irq(sysbusdev, 0, s->irq[22]); - sysbus_connect_irq(sysbusdev, 1, s->irq[23]); - sysbus_connect_irq(sysbusdev, 2, s->irq[24]); - sysbus_connect_irq(sysbusdev, 3, s->irq[25]); - sysbus_connect_irq(sysbusdev, 4, s->irq[67]); - sysbus_connect_irq(sysbusdev, 5, s->irq[68]); + sysbus_connect_irq(sysbusdev, 0, qdev_get_gpio_in(dev, 22)); + sysbus_connect_irq(sysbusdev, 1, qdev_get_gpio_in(dev, 23)); + sysbus_connect_irq(sysbusdev, 2, qdev_get_gpio_in(dev, 24)); + sysbus_connect_irq(sysbusdev, 3, qdev_get_gpio_in(dev, 25)); + sysbus_connect_irq(sysbusdev, 4, qdev_get_gpio_in(dev, 67)); + sysbus_connect_irq(sysbusdev, 5, qdev_get_gpio_in(dev, 68)); memory_region_init_ram(&s->sram_a, OBJECT(dev), "sram A", 48 * KiB, &error_fatal); @@ -111,7 +108,7 @@ static void aw_a10_realize(DeviceState *dev, Error **errp) } sysbusdev = SYS_BUS_DEVICE(&s->emac); sysbus_mmio_map(sysbusdev, 0, AW_A10_EMAC_BASE); - sysbus_connect_irq(sysbusdev, 0, s->irq[55]); + sysbus_connect_irq(sysbusdev, 0, qdev_get_gpio_in(dev, 55)); object_property_set_bool(OBJECT(&s->sata), true, "realized", &err); if (err) { @@ -119,10 +116,11 @@ static void aw_a10_realize(DeviceState *dev, Error **errp) return; } sysbus_mmio_map(SYS_BUS_DEVICE(&s->sata), 0, AW_A10_SATA_BASE); - sysbus_connect_irq(SYS_BUS_DEVICE(&s->sata), 0, s->irq[56]); + sysbus_connect_irq(SYS_BUS_DEVICE(&s->sata), 0, qdev_get_gpio_in(dev, 56)); /* FIXME use a qdev chardev prop instead of serial_hd() */ - serial_mm_init(get_system_memory(), AW_A10_UART0_REG_BASE, 2, s->irq[1], + serial_mm_init(get_system_memory(), AW_A10_UART0_REG_BASE, 2, + qdev_get_gpio_in(dev, 1), 115200, serial_hd(0), DEVICE_NATIVE_ENDIAN); } -- 2.21.0 From MAILER-DAEMON Mon Dec 30 06:10:13 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1ilsw9-0005oJ-HS for mharc-qemu-arm@gnu.org; Mon, 30 Dec 2019 06:10:13 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:35425) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ilsw5-0005hS-A2 for qemu-arm@nongnu.org; Mon, 30 Dec 2019 06:10:10 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ilsw3-0003Hc-Rs for qemu-arm@nongnu.org; Mon, 30 Dec 2019 06:10:09 -0500 Received: from mail-wm1-x344.google.com ([2a00:1450:4864:20::344]:32841) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ilsw0-0003AP-Iv; Mon, 30 Dec 2019 06:10:04 -0500 Received: by mail-wm1-x344.google.com with SMTP id d139so11394629wmd.0; Mon, 30 Dec 2019 03:10:04 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; 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Mon, 30 Dec 2019 03:10:03 -0800 (PST) Received: from x1w.redhat.com ([2a01:cb18:8372:6b00:691b:aac5:8837:d4da]) by smtp.gmail.com with ESMTPSA id p15sm20442738wma.40.2019.12.30.03.10.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 30 Dec 2019 03:10:02 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Beniamino Galvani , Niek Linnenbank , Willian Rampazzo , Peter Maydell , Wainer dos Santos Moschetta , qemu-arm@nongnu.org, Cleber Rosa , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [RFC PATCH 6/6] hw/arm/cubieboard: Disable unsupported M-USB in device tree blob Date: Mon, 30 Dec 2019 12:09:53 +0100 Message-Id: <20191230110953.25496-7-f4bug@amsat.org> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20191230110953.25496-1-f4bug@amsat.org> References: <20191230110953.25496-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 8bit X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::344 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 30 Dec 2019 11:10:12 -0000 We do not model the Sunxi Multipoint USB. The Linux kernel OOPS when booting: ------------[ cut here ]------------ WARNING: CPU: 0 PID: 144 at drivers/usb/musb/sunxi.c:400 sunxi_musb_ep_offset+0x39/0x3c sunxi_musb_ep_offset called with non 0 offset Modules linked in: CPU: 0 PID: 144 Comm: kworker/0:2 Not tainted 4.20.7-sunxi #5.75 Hardware name: Allwinner sun4i/sun5i Families Workqueue: events deferred_probe_work_func [] (unwind_backtrace) from [] (show_stack+0x11/0x14) [] (show_stack) from [] (dump_stack+0x69/0x78) [] (dump_stack) from [] (__warn+0xa1/0xb4) [] (__warn) from [] (warn_slowpath_fmt+0x33/0x48) [] (warn_slowpath_fmt) from [] (sunxi_musb_ep_offset+0x39/0x3c) [] (sunxi_musb_ep_offset) from [] (ep_config_from_hw+0x99/0x104) [] (ep_config_from_hw) from [] (musb_probe+0x765/0xa0c) [] (musb_probe) from [] (platform_drv_probe+0x33/0x68) [] (platform_drv_probe) from [] (really_probe+0x16f/0x1e0) [] (really_probe) from [] (driver_probe_device+0x43/0x11c) [] (driver_probe_device) from [] (bus_for_each_drv+0x37/0x70) [] (bus_for_each_drv) from [] (__device_attach+0x83/0xc8) [] (__device_attach) from [] (bus_probe_device+0x5b/0x60) [] (bus_probe_device) from [] (device_add+0x2f5/0x474) [] (device_add) from [] (platform_device_add+0xb7/0x184) [] (platform_device_add) from [] (platform_device_register_full+0xb3/0xc4) [] (platform_device_register_full) from [] (sunxi_musb_probe+0x1d7/0x2f4) [] (sunxi_musb_probe) from [] (platform_drv_probe+0x33/0x68) [] (platform_drv_probe) from [] (really_probe+0x16f/0x1e0) [] (really_probe) from [] (driver_probe_device+0x43/0x11c) [] (driver_probe_device) from [] (bus_for_each_drv+0x37/0x70) [] (bus_for_each_drv) from [] (__device_attach+0x83/0xc8) [] (__device_attach) from [] (bus_probe_device+0x5b/0x60) [] (bus_probe_device) from [] (deferred_probe_work_func+0x4b/0x6c) [] (deferred_probe_work_func) from [] (process_one_work+0x167/0x384) [] (process_one_work) from [] (worker_thread+0x251/0x3fc) [] (worker_thread) from [] (kthread+0xfd/0x104) [] (kthread) from [] (ret_from_fork+0x11/0x38) Exception stack(0xc6999fb0 to 0xc6999ff8) 9fa0: 00000000 00000000 00000000 00000000 9fc0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 9fe0: 00000000 00000000 00000000 00000000 00000013 00000000 ---[ end trace b309edbca98c7de2 ]--- musb-sunxi 1c13000.usb: Error unknown readb offset 128 musb-hdrc musb-hdrc.1.auto: musb_init_controller failed with status -22 musb-hdrc: probe of musb-hdrc.1.auto failed with error -22 This is not critical but confusing. To avoid the Linux kernel to probe this device, mark it disabled in the device tree blob. Signed-off-by: Philippe Mathieu-Daudé --- I'm not sure if this is a QEMU anti-pattern or bad practice. I know we prefer to be as close to the hardware as possible, but here the hardware is not changed, the dtb is. However this makes the guest behave differently. At least we don't have to manually edit the dts. If this is only annoying for acceptance testing, we might consider manually editing the dts in the tests setup(). --- hw/arm/cubieboard.c | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/hw/arm/cubieboard.c b/hw/arm/cubieboard.c index 6dc2f1d6b6..dd10577696 100644 --- a/hw/arm/cubieboard.c +++ b/hw/arm/cubieboard.c @@ -22,10 +22,34 @@ #include "hw/sysbus.h" #include "hw/boards.h" #include "hw/arm/allwinner-a10.h" +#include + +static void cubieboard_modify_dtb(const struct arm_boot_info *info, void *fdt) +{ + static const char unsupported_compat[] = "allwinner,sun4i-a10-musb"; + char node_path[72]; + int offset; + + offset = fdt_node_offset_by_compatible(fdt, -1, unsupported_compat); + while (offset >= 0) { + int r = fdt_get_path(fdt, offset, node_path, sizeof(node_path)); + assert(r >= 0); + r = fdt_setprop_string(fdt, offset, "status", "disabled"); + if (r < 0) { + error_report("%s: Couldn't disable %s: %s", __func__, + unsupported_compat, fdt_strerror(r)); + exit(1); + } + warn_report("cubieboard: disabled unsupported node %s (%s) " + "in device tree", node_path, unsupported_compat); + offset = fdt_node_offset_by_compatible(fdt, offset, unsupported_compat); + } +} static struct arm_boot_info cubieboard_binfo = { .loader_start = AW_A10_SDRAM_BASE, .board_id = 0x1008, + .modify_dtb = cubieboard_modify_dtb, }; typedef struct CubieBoardState { -- 2.21.0 From MAILER-DAEMON Mon Dec 30 06:29:06 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1iltEQ-0006mx-EJ for mharc-qemu-arm@gnu.org; Mon, 30 Dec 2019 06:29:06 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:37550) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iltEL-0006fd-Iu for qemu-arm@nongnu.org; Mon, 30 Dec 2019 06:29:04 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1iltEI-0004eU-7S for qemu-arm@nongnu.org; Mon, 30 Dec 2019 06:29:01 -0500 Received: from mail-il1-x143.google.com ([2607:f8b0:4864:20::143]:41573) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1iltEB-0004bW-FS; Mon, 30 Dec 2019 06:28:51 -0500 Received: by mail-il1-x143.google.com with SMTP id f10so27583709ils.8; Mon, 30 Dec 2019 03:28:51 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=8CR/JzFbTBly2wjxWR88f/CmSC+C3LPoyCZNuYGI6Cs=; b=p6nj5/bwcHRrDH/2TW2KYPRm+Nc7LiZFvccv5J9j4awECvVnIXl1Po9pAPbeV7SkOB xJCgP12lkmdyXgv9yelMy3nWh6898hRqjdxg2hUGF62p2/RgonZbp2ANweWeLWh27Odf h3Ul302Gc1xZS3H4ySeb5g8xNeCwrRZqpYOAP7hoiQt5arxPkQrxtzOx9+4Ut5+FfTb0 TKe53oEF5fWvwBJQxLweanE1SBKp5MiO7BtzILd/dWJOQ1Q29Ci39sUa5HIzff5vKVCS FeF5ro23KNYnpZHXhS+7WfMww/DdjlVWmMJe87hajK/gUKxzwjc2vJdPsXeUvX4KSYbL BJKA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=8CR/JzFbTBly2wjxWR88f/CmSC+C3LPoyCZNuYGI6Cs=; b=SiAUt2+7pfXBhbr0c3j1C22WntBty4epQy6XoBNazIS1BHgUwU35ziUH7ZHgsE8gXN YaIdXXk8xcaMkxnrSgPbgOFKbXzIlPd7LXMwEnF5X7NM0Gfs6+by+Y8edGF8egJhJLt4 f3QxI/anLfSxWgu3sfHjXLSdc5xFW90Cs6k6BWSRKSzZZpdRgFvn0naYKUBQ5mZ5vI1l xmxsgOvavzAtso4ppqS0FaWdV2QqADTcqJKRiZFmpp54+4/zSZHrxU1J4lp20wjhJtjj nhcsdoX/F/jF1V1nRftkYufk/l4lRjNFPMNFVRbKmQ9QQvmDEQTl05Np4X4Mzh3Butrb Qo/g== X-Gm-Message-State: APjAAAWGgMfnpP734eAe0T0lzvQnH9ZELYDNSonkfh2RtTbVr3aqmr/V dQIyROI0h/3xC6M41NiNqAU/B0pW/A1WSru1g+INrC3Z X-Google-Smtp-Source: APXvYqwL18LUSw75GoFSUeeKbzIcnZ6rjKZOYvJnKUFcsN7Ew8z91+ZCurG+SoSK3FpC5C4KXR7lVEwMcYAd/aYggJk= X-Received: by 2002:a92:d5cf:: with SMTP id d15mr54563487ilq.306.1577705330014; Mon, 30 Dec 2019 03:28:50 -0800 (PST) MIME-Version: 1.0 References: <20191216233519.29030-1-nieklinnenbank@gmail.com> In-Reply-To: <20191216233519.29030-1-nieklinnenbank@gmail.com> From: Niek Linnenbank Date: Mon, 30 Dec 2019 12:28:38 +0100 Message-ID: Subject: Re: [PATCH v2 00/10] Add Allwinner H3 SoC and Orange Pi PC Machine To: QEMU Developers Cc: qemu-arm , Peter Maydell , =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= Content-Type: multipart/alternative; boundary="000000000000c17ee8059aea2500" X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::143 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 30 Dec 2019 11:29:05 -0000 --000000000000c17ee8059aea2500 Content-Type: text/plain; charset="UTF-8" Hi, Here a short status report of this patch series. For V3 update I already prepared the following: - reworked all review comments from Philippe, except: - patch#8: question for the SID, whether command-line override is required (and how is the best way for machine-specific cli arg?) [1] - added BootROM support, allows booting with only specifying -sd - added SDRAM controller driver, for U-Boot SPL - added Allwinner generic RTC driver (for both Cubieboard and OrangePi PC, supports sun4i, sun6i, sun7i) - small fixes for EMAC My current TODO: - integrate Philips acceptance tests in the series - integrate Philips work for generalizing the Allwinner timer, and finish it - test and fix BSD targets (NetBSD, FreeBSD) [2, 3] - further generalize the series to cover very similar SoCs: H2+, H5 Does anyone have more comments/requests for the V3 update? [1] https://lists.gnu.org/archive/html/qemu-devel/2019-12/msg04049.html [2] https://wiki.netbsd.org/ports/evbarm/allwinner/ [3] https://wiki.freebsd.org/action/show/arm/Allwinner?action=show&redirect=FreeBSD%2Farm%2FAllwinner On Tue, Dec 17, 2019 at 12:35 AM Niek Linnenbank wrote: > Dear QEMU developers, > > Hereby I would like to contribute the following set of patches to QEMU > which add support for the Allwinner H3 System on Chip and the > Orange Pi PC machine. The following features and devices are supported: > > * SMP (Quad Core Cortex A7) > * Generic Interrupt Controller configuration > * SRAM mappings > * Timer device (re-used from Allwinner A10) > * UART > * SD/MMC storage controller > * EMAC ethernet connectivity > * USB 2.0 interfaces > * Clock Control Unit > * System Control module > * Security Identifier device > > Functionality related to graphical output such as HDMI, GPU, > Display Engine and audio are not included. Recently released > mainline Linux kernels (4.19 up to latest master) and mainline U-Boot > are known to work. The SD/MMC code is tested using bonnie++ and > various tools such as fsck, dd and fdisk. The EMAC is verified with iperf3 > using -netdev socket. > > To build a Linux mainline kernel that can be booted by the Orange Pi PC > machine, simply configure the kernel using the sunxi_defconfig > configuration: > $ ARCH=arm CROSS_COMPILE=arm-linux-gnueabi- make mrproper > $ ARCH=arm CROSS_COMPILE=arm-linux-gnueabi- make sunxi_defconfig > > To be able to use USB storage, you need to manually enable the > corresponding > configuration item. Start the kconfig configuration tool: > $ ARCH=arm CROSS_COMPILE=arm-linux-gnueabi- make menuconfig > > Navigate to the following item, enable it and save your configuration: > Device Drivers > USB support > USB Mass Storage support > > Build the Linux kernel with: > $ ARCH=arm CROSS_COMPILE=arm-linux-gnueabi- make -j5 > > To boot the newly build linux kernel in QEMU with the Orange Pi PC > machine, use: > $ qemu-system-arm -M orangepi-pc -m 512 -nic user -nographic \ > -kernel /path/to/linux/arch/arm/boot/zImage \ > -append 'console=ttyS0,115200' \ > -dtb /path/to/linux/arch/arm/boot/dts/sun8i-h3-orangepi-pc.dtb > > Note that this kernel does not have a root filesystem. You may provide it > with an official Orange Pi PC image [1] either as an SD card or as > USB mass storage. To boot using the Orange Pi PC Debian image on SD card, > simply add the -sd argument and provide the proper root= kernel parameter: > $ qemu-system-arm -M orangepi-pc -m 512 -nic user -nographic \ > -kernel /path/to/linux/arch/arm/boot/zImage \ > -append 'console=ttyS0,115200 root=/dev/mmcblk0p2' \ > -dtb /path/to/linux/arch/arm/boot/dts/sun8i-h3-orangepi-pc.dtb \ > -sd OrangePi_pc_debian_stretch_server_linux5.3.5_v1.0.img > > Alternatively, you can also choose to build and boot a recent buildroot [2] > using the orangepi_pc_defconfig or Armbian image [3] for Orange Pi PC. > To attach an USB mass storage device to the machine, simply append to the > command: > -drive if=none,id=stick,file=myimage.img \ > -device usb-storage,bus=usb-bus.0,drive=stick > > U-Boot mainline can be build and configured using the orangepi_pc_defconfig > using similar commands as describe above for Linux. To start U-Boot using > the Orange Pi PC machine, provide the u-boot binary to the -kernel > argument: > $ qemu-system-arm -M orangepi-pc -m 512 -nic user -nographic \ > -kernel /path/to/uboot/u-boot -sd disk.img > > Use the following U-boot commands to load and boot a Linux kernel from SD > card: > -> setenv bootargs console=ttyS0,115200 > -> ext2load mmc 0 0x42000000 zImage > -> ext2load mmc 0 0x43000000 sun8i-h3-orangepi-pc.dtb > -> bootz 0x42000000 - 0x43000000 > > Looking forward to your review comments. I will do my best > to update the patches where needed. > > ===== CHANGELOG ===== > > v2: > * hw/arm/allwinner-h3.c: use cpus array in AwH3State instead of > object_new() > * hw/arm/allwinner-h3.c: use error_abort in aw_h3_realize() > * hw/arm/allwinner-h3.c: use qdev_init_nofail() in aw_h3_realize() > * hw/arm/allwinner-h3.c: use qdev_get_gpio_in() instead of irq array > * hw/arm/allwinner-h3.c: add all missing unimplemented devices (memory > map is complete) > * hw/arm/allwinner-h3.c: add UART1, UART2, UART3 and remove 'if > (serial_hd(...))' > * hw/arm/allwinner-h3.c: remove sysbusdev variable and use > SYS_BUS_DEVICE() directly > * include/hw/arm/allwinner-h3.h: move PPI/SPI defines to allwinner-h3.c > as enum > * include/hw/arm/allwinner-h3.h: replace mem base/size defines with enum > and memmap (like aspeed_soc.h) > * hw/arm/orangepi.c: Only allow Cortex-A7 in machine->cpu_type > * hw/arm/orangepi.c: Set mc->default_cpu_type to > ARM_CPU_TYPE_NAME("cortex-a7") > * hw/arm/orangepi.c: Use error_abort in orangepi_init() > * hw/arm/orangepi.c: only allow maximum 1GiB RAM > * hw/arm/orangepi.c: renamed machine name to 'orangepi-pc' > * hw/arm/orangepi.c: remove mc->ignore_memory_transaction_failures = true > * hw/arm/orangepi.c: remove unnecessary check for 'sd-bus' > * hw/net/allwinner-h3-emac.c: use AW_H3_EMAC() for opaque in read/write > functions > * hw/sd/allwinner-h3-sdhost.c: replace register defines with enums > * hw/sd/allwinner-h3-sdhost.c: remove 'irq_en' and use if() to set 'irq' > in update_irq function > * hw/sd/allwinner-h3-sdhost.c: simplified if (rlen==) conditions in > send_command function > * hw/sd/allwinner-h3-sdhost.c: use KiB macro to set desc->size > * hw/sd/allwinner-h3-sdhost.c: use ARRAY_SIZE() macro in reset function > * hw/misc/allwinner-h3-sid.c: replace randomized identifier with QemuUUID > property > * hw/misc/allwinner-h3-sid.c: add tracing for read/write functions > * hw/misc/allwinner-h3-sid.c: fix incorrect usage of > REG_PRCTL_OP_LOCK/REG_PRCTL_WRITE > * hw/misc/trace-events: add allwinner_h3_cpucfg* entries in correct patch > (#7) > * hw/*/trace-events: use PRIu32/PRIx32 macros for size and max fields > * hw/*/allwinner-h3-*.c: set .impl.min_access_size = 4 to restrict MMIO > access to 32-bit aligned > * hw/*/allwinner-h3-*.c: replace register defines with enums > * hw/*/allwinner-h3-*.c: set VMStateDescription.name with inline string > (dont use TYPE macro) > * include/hw/*/allwinner-h3-*.h: remove MEM_SIZE define and use size > inline in the source file > * target/arm/arm-powerctl.c: invoke arm_rebuild_hflags() after setting > CP15 bits > > With kind regards, > > Niek Linnenbank > > [1] http://www.orangepi.org/downloadresources/ > [2] https://buildroot.org/download.html > [3] https://www.armbian.com/orange-pi-pc/ > > Niek Linnenbank (10): > hw: arm: add Allwinner H3 System-on-Chip > hw: arm: add Xunlong Orange Pi PC machine > arm: allwinner-h3: add Clock Control Unit > arm: allwinner-h3: add USB host controller > arm: allwinner-h3: add System Control module > arm/arm-powerctl: rebuild hflags after setting CP15 bits in > arm_set_cpu_on() > arm: allwinner-h3: add CPU Configuration module > arm: allwinner-h3: add Security Identifier device > arm: allwinner-h3: add SD/MMC host controller > arm: allwinner-h3: add EMAC ethernet device > > default-configs/arm-softmmu.mak | 1 + > hw/usb/hcd-ehci.h | 1 + > include/hw/arm/allwinner-h3.h | 93 +++ > include/hw/misc/allwinner-h3-clk.h | 40 ++ > include/hw/misc/allwinner-h3-cpucfg.h | 42 ++ > include/hw/misc/allwinner-h3-sid.h | 40 ++ > include/hw/misc/allwinner-h3-syscon.h | 42 ++ > include/hw/net/allwinner-h3-emac.h | 67 +++ > include/hw/sd/allwinner-h3-sdhost.h | 71 +++ > hw/arm/allwinner-h3.c | 442 ++++++++++++++ > hw/arm/orangepi.c | 127 ++++ > hw/misc/allwinner-h3-clk.c | 238 ++++++++ > hw/misc/allwinner-h3-cpucfg.c | 288 +++++++++ > hw/misc/allwinner-h3-sid.c | 179 ++++++ > hw/misc/allwinner-h3-syscon.c | 146 +++++ > hw/net/allwinner-h3-emac.c | 829 ++++++++++++++++++++++++++ > hw/sd/allwinner-h3-sdhost.c | 813 +++++++++++++++++++++++++ > hw/usb/hcd-ehci-sysbus.c | 17 + > target/arm/arm-powerctl.c | 3 + > MAINTAINERS | 8 + > hw/arm/Kconfig | 9 + > hw/arm/Makefile.objs | 1 + > hw/misc/Makefile.objs | 4 + > hw/misc/trace-events | 9 + > hw/net/Kconfig | 3 + > hw/net/Makefile.objs | 1 + > hw/net/trace-events | 10 + > hw/sd/Makefile.objs | 1 + > hw/sd/trace-events | 7 + > 29 files changed, 3532 insertions(+) > create mode 100644 include/hw/arm/allwinner-h3.h > create mode 100644 include/hw/misc/allwinner-h3-clk.h > create mode 100644 include/hw/misc/allwinner-h3-cpucfg.h > create mode 100644 include/hw/misc/allwinner-h3-sid.h > create mode 100644 include/hw/misc/allwinner-h3-syscon.h > create mode 100644 include/hw/net/allwinner-h3-emac.h > create mode 100644 include/hw/sd/allwinner-h3-sdhost.h > create mode 100644 hw/arm/allwinner-h3.c > create mode 100644 hw/arm/orangepi.c > create mode 100644 hw/misc/allwinner-h3-clk.c > create mode 100644 hw/misc/allwinner-h3-cpucfg.c > create mode 100644 hw/misc/allwinner-h3-sid.c > create mode 100644 hw/misc/allwinner-h3-syscon.c > create mode 100644 hw/net/allwinner-h3-emac.c > create mode 100644 hw/sd/allwinner-h3-sdhost.c > > -- > 2.17.1 > > -- Niek Linnenbank --000000000000c17ee8059aea2500 Content-Type: text/html; charset="UTF-8" Content-Transfer-Encoding: quoted-printable
Hi,

Here a short status repo= rt of this patch series.

For V3 update I already p= repared the following:
=C2=A0- reworked all review comments from = Philippe, except:
=C2=A0=C2=A0 - patch#8: question for the SID, w= hether command-line override is required (and how is the best way for machi= ne-specific cli arg?) [1]
- added BootROM support, allows booting= with only specifying -sd <IMG>
- added SDRAM controlle= r driver, for U-Boot SPL
- added Allwinner generic RTC driver (fo= r both Cubieboard and OrangePi PC, supports sun4i, sun6i, sun7i)
= - small fixes for EMAC

My current TODO:
= =C2=A0- integrate Philips acceptance tests in the series
=C2=A0- = integrate Philips work for generalizing the Allwinner timer, and finish it<= /div>
=C2=A0- test and fix BSD targets (NetBSD, FreeBSD) [2, 3]
=C2=A0- further generalize the series to cover very similar SoCs: H2+, H= 5

Does anyone have more comments/requests for = the V3 update?


On Tue, Dec 17, 2019 at 12:= 35 AM Niek Linnenbank <niekl= innenbank@gmail.com> wrote:
Dear QEMU developers,

Hereby I would like to contribute the following set of patches to QEMU
which add support for the Allwinner H3 System on Chip and the
Orange Pi PC machine. The following features and devices are supported:

=C2=A0* SMP (Quad Core Cortex A7)
=C2=A0* Generic Interrupt Controller configuration
=C2=A0* SRAM mappings
=C2=A0* Timer device (re-used from Allwinner A10)
=C2=A0* UART
=C2=A0* SD/MMC storage controller
=C2=A0* EMAC ethernet connectivity
=C2=A0* USB 2.0 interfaces
=C2=A0* Clock Control Unit
=C2=A0* System Control module
=C2=A0* Security Identifier device

Functionality related to graphical output such as HDMI, GPU,
Display Engine and audio are not included. Recently released
mainline Linux kernels (4.19 up to latest master) and mainline U-Boot
are known to work. The SD/MMC code is tested using bonnie++ and
various tools such as fsck, dd and fdisk. The EMAC is verified with iperf3<= br> using -netdev socket.

To build a Linux mainline kernel that can be booted by the Orange Pi PC
machine, simply configure the kernel using the sunxi_defconfig configuratio= n:
=C2=A0$ ARCH=3Darm CROSS_COMPILE=3Darm-linux-gnueabi- make mrproper
=C2=A0$ ARCH=3Darm CROSS_COMPILE=3Darm-linux-gnueabi- make sunxi_defconfig<= br>
To be able to use USB storage, you need to manually enable the correspondin= g
configuration item. Start the kconfig configuration tool:
=C2=A0$ ARCH=3Darm CROSS_COMPILE=3Darm-linux-gnueabi- make menuconfig

Navigate to the following item, enable it and save your configuration:
=C2=A0Device Drivers > USB support > USB Mass Storage support

Build the Linux kernel with:
=C2=A0$ ARCH=3Darm CROSS_COMPILE=3Darm-linux-gnueabi- make -j5

To boot the newly build linux kernel in QEMU with the Orange Pi PC machine,= use:
=C2=A0$ qemu-system-arm -M orangepi-pc -m 512 -nic user -nographic \
=C2=A0 =C2=A0 =C2=A0-kernel /path/to/linux/arch/arm/boot/zImage \
=C2=A0 =C2=A0 =C2=A0-append 'console=3DttyS0,115200' \
=C2=A0 =C2=A0 =C2=A0-dtb /path/to/linux/arch/arm/boot/dts/sun8i-h3-orangepi= -pc.dtb

Note that this kernel does not have a root filesystem. You may provide it with an official Orange Pi PC image [1] either as an SD card or as
USB mass storage. To boot using the Orange Pi PC Debian image on SD card, simply add the -sd argument and provide the proper root=3D kernel parameter= :
=C2=A0$ qemu-system-arm -M orangepi-pc -m 512 -nic user -nographic \
=C2=A0 =C2=A0 =C2=A0-kernel /path/to/linux/arch/arm/boot/zImage \
=C2=A0 =C2=A0 =C2=A0-append 'console=3DttyS0,115200 root=3D/dev/mmcblk0= p2' \
=C2=A0 =C2=A0 =C2=A0-dtb /path/to/linux/arch/arm/boot/dts/sun8i-h3-orangepi= -pc.dtb \
=C2=A0 =C2=A0 =C2=A0-sd OrangePi_pc_debian_stretch_server_linux5.3.5_v1.0.i= mg

Alternatively, you can also choose to build and boot a recent buildroot [2]=
using the orangepi_pc_defconfig or Armbian image [3] for Orange Pi PC.
To attach an USB mass storage device to the machine, simply append to the c= ommand:
=C2=A0-drive if=3Dnone,id=3Dstick,file=3Dmyimage.img \
=C2=A0-device usb-storage,bus=3Dusb-bus.0,drive=3Dstick

U-Boot mainline can be build and configured using the orangepi_pc_defconfig=
using similar commands as describe above for Linux. To start U-Boot using the Orange Pi PC machine, provide the u-boot binary to the -kernel argument= :
=C2=A0$ qemu-system-arm -M orangepi-pc -m 512 -nic user -nographic \
=C2=A0 =C2=A0 =C2=A0-kernel /path/to/uboot/u-boot -sd disk.img

Use the following U-boot commands to load and boot a Linux kernel from SD c= ard:
=C2=A0-> setenv bootargs console=3DttyS0,115200
=C2=A0-> ext2load mmc 0 0x42000000 zImage
=C2=A0-> ext2load mmc 0 0x43000000 sun8i-h3-orangepi-pc.dtb
=C2=A0-> bootz 0x42000000 - 0x43000000

Looking forward to your review comments. I will do my best
to update the patches where needed.

=3D=3D=3D=3D=3D CHANGELOG =3D=3D=3D=3D=3D

v2:
=C2=A0* hw/arm/allwinner-h3.c: use cpus array in AwH3State instead of objec= t_new()
=C2=A0* hw/arm/allwinner-h3.c: use error_abort in aw_h3_realize()
=C2=A0* hw/arm/allwinner-h3.c: use qdev_init_nofail() in aw_h3_realize() =C2=A0* hw/arm/allwinner-h3.c: use qdev_get_gpio_in() instead of irq array<= br> =C2=A0* hw/arm/allwinner-h3.c: add all missing unimplemented devices (memor= y map is complete)
=C2=A0* hw/arm/allwinner-h3.c: add UART1, UART2, UART3 and remove 'if (= serial_hd(...))'
=C2=A0* hw/arm/allwinner-h3.c: remove sysbusdev variable and use SYS_BUS_DE= VICE() directly
=C2=A0* include/hw/arm/allwinner-h3.h: move PPI/SPI defines to allwinner-h3= .c as enum
=C2=A0* include/hw/arm/allwinner-h3.h: replace mem base/size defines with e= num and memmap (like aspeed_soc.h)
=C2=A0* hw/arm/orangepi.c: Only allow Cortex-A7 in machine->cpu_type
=C2=A0* hw/arm/orangepi.c: Set mc->default_cpu_type to ARM_CPU_TYPE_NAME= ("cortex-a7")
=C2=A0* hw/arm/orangepi.c: Use error_abort in orangepi_init()
=C2=A0* hw/arm/orangepi.c: only allow maximum 1GiB RAM
=C2=A0* hw/arm/orangepi.c: renamed machine name to 'orangepi-pc' =C2=A0* hw/arm/orangepi.c: remove mc->ignore_memory_transaction_failures= =3D true
=C2=A0* hw/arm/orangepi.c: remove unnecessary check for 'sd-bus' =C2=A0* hw/net/allwinner-h3-emac.c: use AW_H3_EMAC() for opaque in read/wri= te functions
=C2=A0* hw/sd/allwinner-h3-sdhost.c: replace register defines with enums =C2=A0* hw/sd/allwinner-h3-sdhost.c: remove 'irq_en' and use if() t= o set 'irq' in update_irq function
=C2=A0* hw/sd/allwinner-h3-sdhost.c: simplified if (rlen=3D=3D) conditions = in send_command function
=C2=A0* hw/sd/allwinner-h3-sdhost.c: use KiB macro to set desc->size
=C2=A0* hw/sd/allwinner-h3-sdhost.c: use ARRAY_SIZE() macro in reset functi= on
=C2=A0* hw/misc/allwinner-h3-sid.c: replace randomized identifier with Qemu= UUID property
=C2=A0* hw/misc/allwinner-h3-sid.c: add tracing for read/write functions =C2=A0* hw/misc/allwinner-h3-sid.c: fix incorrect usage of REG_PRCTL_OP_LOC= K/REG_PRCTL_WRITE
=C2=A0* hw/misc/trace-events: add allwinner_h3_cpucfg* entries in correct p= atch (#7)
=C2=A0* hw/*/trace-events: use PRIu32/PRIx32 macros for size and max fields=
=C2=A0* hw/*/allwinner-h3-*.c: set .impl.min_access_size =3D 4 to restrict = MMIO access to 32-bit aligned
=C2=A0* hw/*/allwinner-h3-*.c: replace register defines with enums
=C2=A0* hw/*/allwinner-h3-*.c: set VMStateDescription.name with inline stri= ng (dont use TYPE macro)
=C2=A0* include/hw/*/allwinner-h3-*.h: remove MEM_SIZE define and use size = inline in the source file
=C2=A0* target/arm/arm-powerctl.c: invoke arm_rebuild_hflags() after settin= g CP15 bits

With kind regards,

Niek Linnenbank

[1] http://www.orangepi.org/downloadresources/
[2] https://buildroot.org/download.html
[3] https://www.armbian.com/orange-pi-pc/

Niek Linnenbank (10):
=C2=A0 hw: arm: add Allwinner H3 System-on-Chip
=C2=A0 hw: arm: add Xunlong Orange Pi PC machine
=C2=A0 arm: allwinner-h3: add Clock Control Unit
=C2=A0 arm: allwinner-h3: add USB host controller
=C2=A0 arm: allwinner-h3: add System Control module
=C2=A0 arm/arm-powerctl: rebuild hflags after setting CP15 bits in
=C2=A0 =C2=A0 arm_set_cpu_on()
=C2=A0 arm: allwinner-h3: add CPU Configuration module
=C2=A0 arm: allwinner-h3: add Security Identifier device
=C2=A0 arm: allwinner-h3: add SD/MMC host controller
=C2=A0 arm: allwinner-h3: add EMAC ethernet device

=C2=A0default-configs/arm-softmmu.mak=C2=A0 =C2=A0 =C2=A0 =C2=A0|=C2=A0 =C2= =A01 +
=C2=A0hw/usb/hcd-ehci.h=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0|=C2=A0 =C2=A01 +
=C2=A0include/hw/arm/allwinner-h3.h=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0|=C2= =A0 93 +++
=C2=A0include/hw/misc/allwinner-h3-clk.h=C2=A0 =C2=A0 |=C2=A0 40 ++
=C2=A0include/hw/misc/allwinner-h3-cpucfg.h |=C2=A0 42 ++
=C2=A0include/hw/misc/allwinner-h3-sid.h=C2=A0 =C2=A0 |=C2=A0 40 ++
=C2=A0include/hw/misc/allwinner-h3-syscon.h |=C2=A0 42 ++
=C2=A0include/hw/net/allwinner-h3-emac.h=C2=A0 =C2=A0 |=C2=A0 67 +++
=C2=A0include/hw/sd/allwinner-h3-sdhost.h=C2=A0 =C2=A0|=C2=A0 71 +++
=C2=A0hw/arm/allwinner-h3.c=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0| 442 ++++++++++++++
=C2=A0hw/arm/orangepi.c=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0| 127 ++++
=C2=A0hw/misc/allwinner-h3-clk.c=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 |= 238 ++++++++
=C2=A0hw/misc/allwinner-h3-cpucfg.c=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0| 288 = +++++++++
=C2=A0hw/misc/allwinner-h3-sid.c=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 |= 179 ++++++
=C2=A0hw/misc/allwinner-h3-syscon.c=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0| 146 = +++++
=C2=A0hw/net/allwinner-h3-emac.c=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 |= 829 ++++++++++++++++++++++++++
=C2=A0hw/sd/allwinner-h3-sdhost.c=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0|= 813 +++++++++++++++++++++++++
=C2=A0hw/usb/hcd-ehci-sysbus.c=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 |=C2=A0 17 +
=C2=A0target/arm/arm-powerctl.c=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0|=C2=A0 =C2=A03 +
=C2=A0MAINTAINERS=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0|=C2=A0 =C2=A08 +
=C2=A0hw/arm/Kconfig=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0 =C2=A0 =C2=A0 |=C2=A0 =C2=A09 +
=C2=A0hw/arm/Makefile.objs=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 |=C2=A0 =C2=A01 +
=C2=A0hw/misc/Makefile.objs=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0|=C2=A0 =C2=A04 +
=C2=A0hw/misc/trace-events=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 |=C2=A0 =C2=A09 +
=C2=A0hw/net/Kconfig=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0 =C2=A0 =C2=A0 |=C2=A0 =C2=A03 +
=C2=A0hw/net/Makefile.objs=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 |=C2=A0 =C2=A01 +
=C2=A0hw/net/trace-events=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0|=C2=A0 10 +
=C2=A0hw/sd/Makefile.objs=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0|=C2=A0 =C2=A01 +
=C2=A0hw/sd/trace-events=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 |=C2=A0 =C2=A07 +
=C2=A029 files changed, 3532 insertions(+)
=C2=A0create mode 100644 include/hw/arm/allwinner-h3.h
=C2=A0create mode 100644 include/hw/misc/allwinner-h3-clk.h
=C2=A0create mode 100644 include/hw/misc/allwinner-h3-cpucfg.h
=C2=A0create mode 100644 include/hw/misc/allwinner-h3-sid.h
=C2=A0create mode 100644 include/hw/misc/allwinner-h3-syscon.h
=C2=A0create mode 100644 include/hw/net/allwinner-h3-emac.h
=C2=A0create mode 100644 include/hw/sd/allwinner-h3-sdhost.h
=C2=A0create mode 100644 hw/arm/allwinner-h3.c
=C2=A0create mode 100644 hw/arm/orangepi.c
=C2=A0create mode 100644 hw/misc/allwinner-h3-clk.c
=C2=A0create mode 100644 hw/misc/allwinner-h3-cpucfg.c
=C2=A0create mode 100644 hw/misc/allwinner-h3-sid.c
=C2=A0create mode 100644 hw/misc/allwinner-h3-syscon.c
=C2=A0create mode 100644 hw/net/allwinner-h3-emac.c
=C2=A0create mode 100644 hw/sd/allwinner-h3-sdhost.c

--
2.17.1



--
Niek Linnenbank

--000000000000c17ee8059aea2500-- From MAILER-DAEMON Mon Dec 30 06:34:23 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1iltJX-0008Ln-26 for mharc-qemu-arm@gnu.org; Mon, 30 Dec 2019 06:34:23 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:38253) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iltJT-0008Id-ML for qemu-arm@nongnu.org; Mon, 30 Dec 2019 06:34:21 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1iltJQ-0007e5-IA for qemu-arm@nongnu.org; Mon, 30 Dec 2019 06:34:19 -0500 Received: from mail-io1-xd42.google.com ([2607:f8b0:4864:20::d42]:36827) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1iltJL-0007X5-UE; Mon, 30 Dec 2019 06:34:12 -0500 Received: by mail-io1-xd42.google.com with SMTP id r13so21107206ioa.3; Mon, 30 Dec 2019 03:34:11 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=UvT7Unor9M3eflo5yQDL/TjbsnMQ6Gi8P0jhCttW2S4=; b=I63uBrV0C7P9yGBlOg9o5Xq27pdMZ9KGBQ3sW7+dt0u5wJJIheCuqnH/BWHdNnefDb QoxgISi+sDHzH60jrg5ME7Bv/sjkjGLt+Qh2JJ2uOLd4sqYNPS+8hGbyaMrKp1AwBE4b OkeYP9Rn4tQfjZzcS+nM3k+nuEeWWdTFlSgsXGHMRIhCcQ4wsSzHcr7p1XpcHMXpiSfT disfJVGnyDvKHKSuLmBhn4Z0QjbjhAHqO84dwhnbtnAM3d7LC7q0gPAnxTMM31ZtrXXh KJ67scZDE1CC5cgwZS1KBAwRmHtDKoOwuLp2A2wknXJjE9bWZZBtpnn8llyiJhxIkqA+ rYrQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=UvT7Unor9M3eflo5yQDL/TjbsnMQ6Gi8P0jhCttW2S4=; b=aRWok2NQ8jphQeFTXSpGPzWr3W/emeC3C45Tl04DR3X9BSpLpT7jGHxDKI6R9cMPPR OuffurTAFaNTANPWth7F5MmiWk6Mcz931KMs5YaY+y5KneK5y996GAGLYIwsKCPyV1Ra 7ZKkQ8IuErLw/FzAHNHOeHfCHbxwXlGvMCJUUdLNYsYaGnPo9LkIO9e7jW8YhzULoCJa rMW+C7TUvlZmIHfCDJg60UOOwtWSjgXz4OUH/qGMbZv9LJJNIHXoOexZj1E/FMzrLQcF p2dHaoWSpu3m6C9bf1I4+XICLsJ2JddhoKRXWSSS19yO/OFVM4F8+r6bES+sOuVXKARJ LvFw== X-Gm-Message-State: APjAAAVBfBzy0Wg8lWWG2oPe7VDIHCeQLCLCVVO3v8YjWcedB5srXXuX jbbx2u7GxVRQqG3nLdSi8Wp1bCUaa5neNSVetQA= X-Google-Smtp-Source: APXvYqyPBwL6ASBueqR5If8MxbgSFvxgQ9sBnBAKX+F3hqBZJ0IvLS8HqQP7YTJnFL5OHPVVz7jX7V071uKCH1XGzAE= X-Received: by 2002:a02:8817:: with SMTP id r23mr53067919jai.120.1577705650467; Mon, 30 Dec 2019 03:34:10 -0800 (PST) MIME-Version: 1.0 References: <20191230110953.25496-1-f4bug@amsat.org> <20191230110953.25496-7-f4bug@amsat.org> In-Reply-To: <20191230110953.25496-7-f4bug@amsat.org> From: Niek Linnenbank Date: Mon, 30 Dec 2019 12:33:59 +0100 Message-ID: Subject: Re: [RFC PATCH 6/6] hw/arm/cubieboard: Disable unsupported M-USB in device tree blob To: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= Cc: QEMU Developers , Beniamino Galvani , Willian Rampazzo , Peter Maydell , Wainer dos Santos Moschetta , qemu-arm , Cleber Rosa Content-Type: multipart/alternative; boundary="000000000000db36df059aea38a4" X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::d42 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 30 Dec 2019 11:34:21 -0000 --000000000000db36df059aea38a4 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Hello Philippe, I have a suggestion: probably you can apply (almost) the same patch to get USB working for A10 as I did in the Allwinner H3, in patch #4 "add USB host controller" [1] That way you can avoid the DTB modifications and with low effort get USB working as well for this board. As far as I can see, in Section 21.1 in the A10 user manual [2] has the same description as for the H3. It basically has the standard EHCI and OHCI interfaces. [1] https://lists.gnu.org/archive/html/qemu-devel/2019-12/msg03266.html [2] https://linux-sunxi.org/File:Allwinner_A10_User_manual_V1.5.pdf Regards, Niek On Mon, Dec 30, 2019 at 12:10 PM Philippe Mathieu-Daud=C3=A9 wrote: > We do not model the Sunxi Multipoint USB. > The Linux kernel OOPS when booting: > > ------------[ cut here ]------------ > WARNING: CPU: 0 PID: 144 at drivers/usb/musb/sunxi.c:400 > sunxi_musb_ep_offset+0x39/0x3c > sunxi_musb_ep_offset called with non 0 offset > Modules linked in: > CPU: 0 PID: 144 Comm: kworker/0:2 Not tainted 4.20.7-sunxi #5.75 > Hardware name: Allwinner sun4i/sun5i Families > Workqueue: events deferred_probe_work_func > [] (unwind_backtrace) from [] (show_stack+0x11/0x14= ) > [] (show_stack) from [] (dump_stack+0x69/0x78) > [] (dump_stack) from [] (__warn+0xa1/0xb4) > [] (__warn) from [] (warn_slowpath_fmt+0x33/0x48) > [] (warn_slowpath_fmt) from [] > (sunxi_musb_ep_offset+0x39/0x3c) > [] (sunxi_musb_ep_offset) from [] > (ep_config_from_hw+0x99/0x104) > [] (ep_config_from_hw) from [] > (musb_probe+0x765/0xa0c) > [] (musb_probe) from [] > (platform_drv_probe+0x33/0x68) > [] (platform_drv_probe) from [] > (really_probe+0x16f/0x1e0) > [] (really_probe) from [] > (driver_probe_device+0x43/0x11c) > [] (driver_probe_device) from [] > (bus_for_each_drv+0x37/0x70) > [] (bus_for_each_drv) from [] > (__device_attach+0x83/0xc8) > [] (__device_attach) from [] > (bus_probe_device+0x5b/0x60) > [] (bus_probe_device) from [] > (device_add+0x2f5/0x474) > [] (device_add) from [] > (platform_device_add+0xb7/0x184) > [] (platform_device_add) from [] > (platform_device_register_full+0xb3/0xc4) > [] (platform_device_register_full) from [] > (sunxi_musb_probe+0x1d7/0x2f4) > [] (sunxi_musb_probe) from [] > (platform_drv_probe+0x33/0x68) > [] (platform_drv_probe) from [] > (really_probe+0x16f/0x1e0) > [] (really_probe) from [] > (driver_probe_device+0x43/0x11c) > [] (driver_probe_device) from [] > (bus_for_each_drv+0x37/0x70) > [] (bus_for_each_drv) from [] > (__device_attach+0x83/0xc8) > [] (__device_attach) from [] > (bus_probe_device+0x5b/0x60) > [] (bus_probe_device) from [] > (deferred_probe_work_func+0x4b/0x6c) > [] (deferred_probe_work_func) from [] > (process_one_work+0x167/0x384) > [] (process_one_work) from [] > (worker_thread+0x251/0x3fc) > [] (worker_thread) from [] (kthread+0xfd/0x104) > [] (kthread) from [] (ret_from_fork+0x11/0x38) > Exception stack(0xc6999fb0 to 0xc6999ff8) > 9fa0: 00000000 00000000 00000000 > 00000000 > 9fc0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 > 00000000 > 9fe0: 00000000 00000000 00000000 00000000 00000013 00000000 > ---[ end trace b309edbca98c7de2 ]--- > musb-sunxi 1c13000.usb: Error unknown readb offset 128 > musb-hdrc musb-hdrc.1.auto: musb_init_controller failed with status -22 > musb-hdrc: probe of musb-hdrc.1.auto failed with error -22 > > This is not critical but confusing. To avoid the Linux kernel to > probe this device, mark it disabled in the device tree blob. > > Signed-off-by: Philippe Mathieu-Daud=C3=A9 > --- > I'm not sure if this is a QEMU anti-pattern or bad practice. > I know we prefer to be as close to the hardware as possible, > but here the hardware is not changed, the dtb is. However > this makes the guest behave differently. At least we don't > have to manually edit the dts. If this is only annoying for > acceptance testing, we might consider manually editing the > dts in the tests setup(). > --- > hw/arm/cubieboard.c | 24 ++++++++++++++++++++++++ > 1 file changed, 24 insertions(+) > > diff --git a/hw/arm/cubieboard.c b/hw/arm/cubieboard.c > index 6dc2f1d6b6..dd10577696 100644 > --- a/hw/arm/cubieboard.c > +++ b/hw/arm/cubieboard.c > @@ -22,10 +22,34 @@ > #include "hw/sysbus.h" > #include "hw/boards.h" > #include "hw/arm/allwinner-a10.h" > +#include > + > +static void cubieboard_modify_dtb(const struct arm_boot_info *info, void > *fdt) > +{ > + static const char unsupported_compat[] =3D "allwinner,sun4i-a10-musb= "; > + char node_path[72]; > + int offset; > + > + offset =3D fdt_node_offset_by_compatible(fdt, -1, unsupported_compat= ); > + while (offset >=3D 0) { > + int r =3D fdt_get_path(fdt, offset, node_path, sizeof(node_path)= ); > + assert(r >=3D 0); > + r =3D fdt_setprop_string(fdt, offset, "status", "disabled"); > + if (r < 0) { > + error_report("%s: Couldn't disable %s: %s", __func__, > + unsupported_compat, fdt_strerror(r)); > + exit(1); > + } > + warn_report("cubieboard: disabled unsupported node %s (%s) " > + "in device tree", node_path, unsupported_compat); > + offset =3D fdt_node_offset_by_compatible(fdt, offset, > unsupported_compat); > + } > +} > > static struct arm_boot_info cubieboard_binfo =3D { > .loader_start =3D AW_A10_SDRAM_BASE, > .board_id =3D 0x1008, > + .modify_dtb =3D cubieboard_modify_dtb, > }; > > typedef struct CubieBoardState { > -- > 2.21.0 > > --=20 Niek Linnenbank --000000000000db36df059aea38a4 Content-Type: text/html; charset="UTF-8" Content-Transfer-Encoding: quoted-printable
Hello Philippe,

I have a sug= gestion: probably you can apply (almost) the same patch to get USB
working for A10 as I did in the Allwinner H3, in patch #4 "add USB h= ost controller" [1]
That way you can avoid the DTB modificat= ions and with low effort get USB working as well for this board.
<= div>As far as I can see, in Section 21.1 in the A10 user manual [2] has the= same description
as for the H3. It basically has the standard EH= CI and OHCI interfaces.

[2] h= ttps://linux-sunxi.org/File:Allwinner_A10_User_manual_V1.5.pdf

Regards,
Niek

On Mon, Dec 30, 2019 at 1= 2:10 PM Philippe Mathieu-Daud=C3=A9 <= f4bug@amsat.org> wrote:
We do not model the Sunxi Multipoint USB.
The Linux kernel OOPS when booting:

=C2=A0 ------------[ cut here ]------------
=C2=A0 WARNING: CPU: 0 PID: 144 at drivers/usb/musb/sunxi.c:400 sunxi_musb_= ep_offset+0x39/0x3c
=C2=A0 sunxi_musb_ep_offset called with non 0 offset
=C2=A0 Modules linked in:
=C2=A0 CPU: 0 PID: 144 Comm: kworker/0:2 Not tainted 4.20.7-sunxi #5.75
=C2=A0 Hardware name: Allwinner sun4i/sun5i Families
=C2=A0 Workqueue: events deferred_probe_work_func
=C2=A0 [<c010d77d>] (unwind_backtrace) from [<c010a425>] (show_= stack+0x11/0x14)
=C2=A0 [<c010a425>] (show_stack) from [<c08d9141>] (dump_stack+= 0x69/0x78)
=C2=A0 [<c08d9141>] (dump_stack) from [<c011b161>] (__warn+0xa1= /0xb4)
=C2=A0 [<c011b161>] (__warn) from [<c011b1a7>] (warn_slowpath_f= mt+0x33/0x48)
=C2=A0 [<c011b1a7>] (warn_slowpath_fmt) from [<c0725c81>] (sunx= i_musb_ep_offset+0x39/0x3c)
=C2=A0 [<c0725c81>] (sunxi_musb_ep_offset) from [<c071b481>] (e= p_config_from_hw+0x99/0x104)
=C2=A0 [<c071b481>] (ep_config_from_hw) from [<c071c8d9>] (musb= _probe+0x765/0xa0c)
=C2=A0 [<c071c8d9>] (musb_probe) from [<c063fa4f>] (platform_dr= v_probe+0x33/0x68)
=C2=A0 [<c063fa4f>] (platform_drv_probe) from [<c063e4ef>] (rea= lly_probe+0x16f/0x1e0)
=C2=A0 [<c063e4ef>] (really_probe) from [<c063e67f>] (driver_pr= obe_device+0x43/0x11c)
=C2=A0 [<c063e67f>] (driver_probe_device) from [<c063d0cf>] (bu= s_for_each_drv+0x37/0x70)
=C2=A0 [<c063d0cf>] (bus_for_each_drv) from [<c063e32f>] (__dev= ice_attach+0x83/0xc8)
=C2=A0 [<c063e32f>] (__device_attach) from [<c063da8b>] (bus_pr= obe_device+0x5b/0x60)
=C2=A0 [<c063da8b>] (bus_probe_device) from [<c063b7a5>] (devic= e_add+0x2f5/0x474)
=C2=A0 [<c063b7a5>] (device_add) from [<c063f8ef>] (platform_de= vice_add+0xb7/0x184)
=C2=A0 [<c063f8ef>] (platform_device_add) from [<c06400df>] (pl= atform_device_register_full+0xb3/0xc4)
=C2=A0 [<c06400df>] (platform_device_register_full) from [<c0725a2= f>] (sunxi_musb_probe+0x1d7/0x2f4)
=C2=A0 [<c0725a2f>] (sunxi_musb_probe) from [<c063fa4f>] (platf= orm_drv_probe+0x33/0x68)
=C2=A0 [<c063fa4f>] (platform_drv_probe) from [<c063e4ef>] (rea= lly_probe+0x16f/0x1e0)
=C2=A0 [<c063e4ef>] (really_probe) from [<c063e67f>] (driver_pr= obe_device+0x43/0x11c)
=C2=A0 [<c063e67f>] (driver_probe_device) from [<c063d0cf>] (bu= s_for_each_drv+0x37/0x70)
=C2=A0 [<c063d0cf>] (bus_for_each_drv) from [<c063e32f>] (__dev= ice_attach+0x83/0xc8)
=C2=A0 [<c063e32f>] (__device_attach) from [<c063da8b>] (bus_pr= obe_device+0x5b/0x60)
=C2=A0 [<c063da8b>] (bus_probe_device) from [<c063ddcf>] (defer= red_probe_work_func+0x4b/0x6c)
=C2=A0 [<c063ddcf>] (deferred_probe_work_func) from [<c012e38b>= ] (process_one_work+0x167/0x384)
=C2=A0 [<c012e38b>] (process_one_work) from [<c012f07d>] (worke= r_thread+0x251/0x3fc)
=C2=A0 [<c012f07d>] (worker_thread) from [<c0132949>] (kthread+= 0xfd/0x104)
=C2=A0 [<c0132949>] (kthread) from [<c01010f9>] (ret_from_fork+= 0x11/0x38)
=C2=A0 Exception stack(0xc6999fb0 to 0xc6999ff8)
=C2=A0 9fa0:=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0000000= 00 00000000 00000000 00000000
=C2=A0 9fc0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000= 00000000
=C2=A0 9fe0: 00000000 00000000 00000000 00000000 00000013 00000000
=C2=A0 ---[ end trace b309edbca98c7de2 ]---
=C2=A0 musb-sunxi 1c13000.usb: Error unknown readb offset 128
=C2=A0 musb-hdrc musb-hdrc.1.auto: musb_init_controller failed with status = -22
=C2=A0 musb-hdrc: probe of musb-hdrc.1.auto failed with error -22

This is not critical but confusing. To avoid the Linux kernel to
probe this device, mark it disabled in the device tree blob.

Signed-off-by: Philippe Mathieu-Daud=C3=A9 <f4bug@amsat.org>
---
I'm not sure if this is a QEMU anti-pattern or bad practice.
I know we prefer to be as close to the hardware as possible,
but here the hardware is not changed, the dtb is. However
this makes the guest behave differently. At least we don't
have to manually edit the dts. If this is only annoying for
acceptance testing, we might consider manually editing the
dts in the tests setup().
---
=C2=A0hw/arm/cubieboard.c | 24 ++++++++++++++++++++++++
=C2=A01 file changed, 24 insertions(+)

diff --git a/hw/arm/cubieboard.c b/hw/arm/cubieboard.c
index 6dc2f1d6b6..dd10577696 100644
--- a/hw/arm/cubieboard.c
+++ b/hw/arm/cubieboard.c
@@ -22,10 +22,34 @@
=C2=A0#include "hw/sysbus.h"
=C2=A0#include "hw/boards.h"
=C2=A0#include "hw/arm/allwinner-a10.h"
+#include <libfdt.h>
+
+static void cubieboard_modify_dtb(const struct arm_boot_info *info, void *= fdt)
+{
+=C2=A0 =C2=A0 static const char unsupported_compat[] =3D "allwinner,s= un4i-a10-musb";
+=C2=A0 =C2=A0 char node_path[72];
+=C2=A0 =C2=A0 int offset;
+
+=C2=A0 =C2=A0 offset =3D fdt_node_offset_by_compatible(fdt, -1, unsupporte= d_compat);
+=C2=A0 =C2=A0 while (offset >=3D 0) {
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 int r =3D fdt_get_path(fdt, offset, node_path,= sizeof(node_path));
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 assert(r >=3D 0);
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 r =3D fdt_setprop_string(fdt, offset, "st= atus", "disabled");
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 if (r < 0) {
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 error_report("%s: Couldn= 9;t disable %s: %s", __func__,
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0unsupported_compat, fdt_strerror(r));
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 exit(1);
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 }
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 warn_report("cubieboard: disabled unsuppo= rted node %s (%s) "
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 &quo= t;in device tree", node_path, unsupported_compat);
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 offset =3D fdt_node_offset_by_compatible(fdt, = offset, unsupported_compat);
+=C2=A0 =C2=A0 }
+}

=C2=A0static struct arm_boot_info cubieboard_binfo =3D {
=C2=A0 =C2=A0 =C2=A0.loader_start =3D AW_A10_SDRAM_BASE,
=C2=A0 =C2=A0 =C2=A0.board_id =3D 0x1008,
+=C2=A0 =C2=A0 .modify_dtb =3D cubieboard_modify_dtb,
=C2=A0};

=C2=A0typedef struct CubieBoardState {
--
2.21.0



--
Niek Linnenbank

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[92.134.161.92]) by smtp.gmail.com with ESMTPSA id b15sm20694410wmj.13.2019.12.30.05.55.58 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 30 Dec 2019 05:55:58 -0800 (PST) Subject: Re: [RFC PATCH 6/6] hw/arm/cubieboard: Disable unsupported M-USB in device tree blob To: Niek Linnenbank , =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= Cc: Peter Maydell , QEMU Developers , Wainer dos Santos Moschetta , Beniamino Galvani , qemu-arm , Willian Rampazzo , Cleber Rosa References: <20191230110953.25496-1-f4bug@amsat.org> <20191230110953.25496-7-f4bug@amsat.org> From: =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= Message-ID: <9cdbe625-fe29-cb91-2ed4-1231953b3148@redhat.com> Date: Mon, 30 Dec 2019 14:55:57 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.2.2 MIME-Version: 1.0 In-Reply-To: Content-Language: en-US X-MC-Unique: wqi4qTYnPdesnLpOViH-Dw-1 X-Mimecast-Spam-Score: 0 Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 7bit X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 205.139.110.120 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 30 Dec 2019 13:56:07 -0000 On 12/30/19 12:33 PM, Niek Linnenbank wrote: > Hello Philippe, > > I have a suggestion: probably you can apply (almost) the same patch to > get USB > working for A10 as I did in the Allwinner H3, in patch #4 "add USB host > controller" [1] > That way you can avoid the DTB modifications and with low effort get USB > working as well for this board. > As far as I can see, in Section 21.1 in the A10 user manual [2] has the > same description > as for the H3. It basically has the standard EHCI and OHCI interfaces. Oh good news. I guess in the long term we want a AllwinnerSoc parent class where all common blocks are mapped, and A10/H3 children with the differences. But we'll worry about that after your H3 series get merged. > [1] https://lists.gnu.org/archive/html/qemu-devel/2019-12/msg03266.html > [2] https://linux-sunxi.org/File:Allwinner_A10_User_manual_V1.5.pdf > > Regards, > Niek From MAILER-DAEMON Mon Dec 30 09:02:18 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1ilvcg-0002oi-Qw for mharc-qemu-arm@gnu.org; Mon, 30 Dec 2019 09:02:18 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:60301) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ilvce-0002mZ-HQ for qemu-arm@nongnu.org; Mon, 30 Dec 2019 09:02:17 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ilvcZ-0008Tp-IP for qemu-arm@nongnu.org; Mon, 30 Dec 2019 09:02:16 -0500 Received: from us-smtp-2.mimecast.com ([207.211.31.81]:53616 helo=us-smtp-delivery-1.mimecast.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1ilvcZ-0008TH-FI for qemu-arm@nongnu.org; Mon, 30 Dec 2019 09:02:11 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1577714530; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=4fFnOsfrdzXZNd/V8o3HYvj6SVkAdaSl9sgyoNeK6yc=; b=bjfoxgqedXj/rTu85y396wKZ+HW3fkFc/p3ns5JOgAlZZrknIokkRHc1l1qUulr89Dp7lz EFgFM6gVPOUt6KV0B/qPciXF0fcMIq+87l+lDg5epzGr1jS2/tv49KHet5zq3nBFrUR5Ib MgCgV0uo6B09l4RPUamFhU7myEQk+xc= Received: from mail-wr1-f72.google.com (mail-wr1-f72.google.com [209.85.221.72]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-101-bTx0vbebNc2mznIkUY9smw-1; Mon, 30 Dec 2019 09:02:07 -0500 Received: by mail-wr1-f72.google.com with SMTP id l20so10659652wrc.13 for ; Mon, 30 Dec 2019 06:02:06 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:subject:to:cc:references:from:message-id:date :user-agent:mime-version:in-reply-to:content-language :content-transfer-encoding; bh=/J+Rnxkgh1lDLNt07hjUKRxIL0vPpkp6G8hyPyXwQiE=; b=qJgy43XR1b6JtjERKfcOQZ4gvy3lAn0Yas/l154wHcHBXfyJLkBBTV89/u8YxH5vK2 zMOfnbK/3VvoHTxhuL6pKa4XaLj+H2L2QD9trO1B4WwHXKpDsULqSh4swU5fdZZwfYvB be0jGguBBV5gjmv0h3dT6ii4FDY2l/sPfaalq8UbZSxRzFz7TsKHeaomnd08cDZL31yW 2TAzFcw+J6FpGVF0r11U7SqNvr06zFczt85fllWNqrnio586O5j9DODTU3cy1iaUecg8 wXsJUGxwA1WvJ0Usf+5tn+zHpkbaU4w+jNa3rPS7X/Enn+c92F9vutI6lX++0L2WQqvV 3SXQ== X-Gm-Message-State: APjAAAWstXIlzyON4IiAoKHC+fvukXLlrdGP+BnlE5mTAFTvj8MwzRqU jvmQJYxbRZP0elDu7t+4Ma8+lYMPUwnkk6W0WgQny4c2sDQITp5HGzdxEqivZhpes6zT03lL8Kq KBH5UspFkCnHb X-Received: by 2002:a05:600c:2046:: with SMTP id p6mr35197801wmg.110.1577714526087; Mon, 30 Dec 2019 06:02:06 -0800 (PST) X-Google-Smtp-Source: APXvYqxPO5H/bXv6lj5lAuUtRoNV7gc8w0vMUBMR2MKDR333Asy4R45shkFvfdokwIkLvjqeAuoJVQ== X-Received: by 2002:a05:600c:2046:: with SMTP id p6mr35197742wmg.110.1577714525829; Mon, 30 Dec 2019 06:02:05 -0800 (PST) Received: from [192.168.1.25] (abayonne-654-1-186-92.w92-134.abo.wanadoo.fr. [92.134.161.92]) by smtp.gmail.com with ESMTPSA id f1sm46608781wrp.93.2019.12.30.06.02.02 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 30 Dec 2019 06:02:04 -0800 (PST) Subject: Re: [PATCH 1/2] tcg: Search includes from the project root source directory To: Paolo Bonzini Cc: Stefan Weil , qemu-devel , Markus Armbruster , Richard Henderson , Aurelien Jarno , qemu-ppc@nongnu.org, Peter Maydell , Riku Voipio , Aleksandar Rikalo , Andrzej Zaborowski , Laurent Vivier , Max Filippov , Claudio Fontana , qemu-s390x@nongnu.org, Sagar Karandikar , Marek Vasut , Artyom Tarasenko , Chris Wulff , Bastian Koppelmann , Cornelia Huck , Palmer Dabbelt , Richard Henderson , qemu-arm@nongnu.org, "Edgar E. Iglesias" , Mark Cave-Ayland , David Hildenbrand , Anthony Green , Eduardo Habkost , Alistair Francis , Stafford Horne , Guan Xuetao , Michael Walle , Aleksandar Markovic , David Gibson , qemu-riscv@nongnu.org References: <20191230090900.446-1-philmd@redhat.com> <20191230090900.446-2-philmd@redhat.com> <273bf2e5-1223-3d01-f930-394195c037e4@weilnetz.de> <64c2434d-3b2b-1a3e-5358-e4b5acfbe8e8@redhat.com> From: =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= Message-ID: Date: Mon, 30 Dec 2019 15:02:01 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.2.2 MIME-Version: 1.0 In-Reply-To: Content-Language: en-US X-MC-Unique: bTx0vbebNc2mznIkUY9smw-1 X-Mimecast-Spam-Score: 0 Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 207.211.31.81 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 30 Dec 2019 14:02:17 -0000 On 12/30/19 11:33 AM, Paolo Bonzini wrote: >=20 >=20 > Il lun 30 dic 2019, 09:59 Philippe Mathieu-Daud=C3=A9 > ha scritto: >=20 > > I'd prefer not changing those files. >=20 > OK, I'll wait to see what Richard/Markus prefer. >=20 >=20 > I think it's best if you keep the include directives as-is for files=20 > only needed from tcg/, and move the other headers (those that are needed= =20 > from other directories only) to include/tcg. I thought moving headers to include/tcg would diverge too much from=20 libtcg, but this project already did it, so why not: https://github.com/S2E/libtcg/tree/master/include/tcg From MAILER-DAEMON Mon Dec 30 09:49:59 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1ilwMp-0002nm-9G for mharc-qemu-arm@gnu.org; Mon, 30 Dec 2019 09:49:59 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:38274) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ilwMm-0002nG-6W for qemu-arm@nongnu.org; Mon, 30 Dec 2019 09:49:58 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ilwMi-0003IG-Ee for qemu-arm@nongnu.org; Mon, 30 Dec 2019 09:49:54 -0500 Received: from us-smtp-delivery-1.mimecast.com ([207.211.31.120]:43885 helo=us-smtp-1.mimecast.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1ilwMi-0003I1-2U for qemu-arm@nongnu.org; Mon, 30 Dec 2019 09:49:52 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1577717391; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=Lrpu6V3wX71ICYQBEXZeC9yIM+STjVSVOoUxUHos4Gw=; b=LRrTtwORbMRlL+HuByeI1U1TMuDl2qCnsPojqWBOofpZktEdOuaUaroRqlfayQ7N9/Zpxh rCPT/vI+IgjdOTHOBBgsOccioeLg/DREQI+pw+P0OE/Eops6sX6dCFIylcnXi7cK+r3U4T V+9FEHnjU6WPBnYzYed3nbhQiWdGrCo= Received: from mail-wm1-f71.google.com (mail-wm1-f71.google.com [209.85.128.71]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-15-Gpt1OJpyOyeMe61gR88QwA-1; Mon, 30 Dec 2019 09:49:47 -0500 Received: by mail-wm1-f71.google.com with SMTP id w205so1689706wmb.5 for ; Mon, 30 Dec 2019 06:49:47 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:subject:to:cc:references:from:message-id:date :user-agent:mime-version:in-reply-to:content-language :content-transfer-encoding; bh=BZeMlQiIAONvIA8+KFCtML8THv8dGccbixbZz/14GKQ=; b=fAYtGNJmXtq05V7DR+JZQr9OOLOHMdsPDTSy1IazBWUGh7eElrE5vERy/9pWgeBL8Z EmlR5H74G/beRUTSUGiS9zxXfJGPl+saIr/FXJAOmgTb2m9cbWZKC1t/RDkegc8BAG/2 YOZB2nu3EwUJGoEkDP+IBEoUL32OJhdm7AjR09262cvGpy0ThfIDW13zOjhFFGGgT5cQ Xl7nMBmAOixEmrizloRHxAY5qN5xIKof2EJXlzVJ3i+qGrLiuRonf0enw4SlG+HXH+3q PXH99sIZLaydQrrTP0rwtImXjAXyZo7eAw8Ji3y4vvplJZtn+3IR+WU+8QEf/bjpAHUX 3ieg== X-Gm-Message-State: APjAAAW0j/PjWc4DnxqcJwo14FKXD3+Gd3IeVkc8Rb+ofL+OOPzFnmS/ s5r7EAfuauX8Xus3n2gEt5VO6hQgLfh34HjS5brKkR921scV2Bfo82EYHZObV+vnf9QQik1VTJx u1y0i0jRjk8Yr X-Received: by 2002:a05:6000:149:: with SMTP id r9mr58817830wrx.147.1577717386112; Mon, 30 Dec 2019 06:49:46 -0800 (PST) X-Google-Smtp-Source: APXvYqwoyCdJS9iCb7LWzNPNnx67VSQqhCv03xRq5fFJzhc/QHHr508jpNegf4aTX18joJxuxPlS0g== X-Received: by 2002:a05:6000:149:: with SMTP id r9mr58817801wrx.147.1577717385596; Mon, 30 Dec 2019 06:49:45 -0800 (PST) Received: from [192.168.1.25] (abayonne-654-1-186-92.w92-134.abo.wanadoo.fr. [92.134.161.92]) by smtp.gmail.com with ESMTPSA id p18sm21233033wmg.4.2019.12.30.06.49.44 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 30 Dec 2019 06:49:45 -0800 (PST) Subject: Re: [PATCH v2 08/10] arm: allwinner-h3: add Security Identifier device To: Niek Linnenbank Cc: QEMU Developers , qemu-arm , Peter Maydell References: <20191216233519.29030-1-nieklinnenbank@gmail.com> <20191216233519.29030-9-nieklinnenbank@gmail.com> <7153b766-4c3b-5272-3c3e-33e973e74e8f@redhat.com> From: =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= Message-ID: Date: Mon, 30 Dec 2019 15:49:43 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.2.2 MIME-Version: 1.0 In-Reply-To: Content-Language: en-US X-MC-Unique: Gpt1OJpyOyeMe61gR88QwA-1 X-Mimecast-Spam-Score: 0 Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 207.211.31.120 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 30 Dec 2019 14:49:58 -0000 On 12/18/19 9:49 PM, Niek Linnenbank wrote: > Hi Philippe, >=20 > On Tue, Dec 17, 2019 at 8:45 AM Philippe Mathieu-Daud=C3=A9=20 > > wrote: >=20 > Hi Niek, >=20 > On 12/17/19 12:35 AM, Niek Linnenbank wrote: > > The Security Identifier device in Allwinner H3 System on Chip > > gives applications a per-board unique identifier. This commit > > adds support for the Allwinner H3 Security Identifier using > > a 128-bit UUID value as input. > > > > Signed-off-by: Niek Linnenbank > > > --- > >=C2=A0 =C2=A0include/hw/arm/allwinner-h3.h=C2=A0 =C2=A0 =C2=A0 |=C2= =A0 =C2=A02 + > >=C2=A0 =C2=A0include/hw/misc/allwinner-h3-sid.h |=C2=A0 40 +++++++ > >=C2=A0 =C2=A0hw/arm/allwinner-h3.c=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 |=C2=A0 =C2=A07 ++ > >=C2=A0 =C2=A0hw/arm/orangepi.c=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 |=C2=A0 =C2=A04 + > >=C2=A0 =C2=A0hw/misc/allwinner-h3-sid.c=C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0| 179 > +++++++++++++++++++++++++++++ > >=C2=A0 =C2=A0hw/misc/Makefile.objs=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 |=C2=A0 =C2=A01 + > >=C2=A0 =C2=A0hw/misc/trace-events=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0 =C2=A0|=C2=A0 =C2=A04 + > >=C2=A0 =C2=A07 files changed, 237 insertions(+) > >=C2=A0 =C2=A0create mode 100644 include/hw/misc/allwinner-h3-sid.h > >=C2=A0 =C2=A0create mode 100644 hw/misc/allwinner-h3-sid.c > > > > diff --git a/include/hw/arm/allwinner-h3.h > b/include/hw/arm/allwinner-h3.h > > index 8128ae6131..c98c1972a6 100644 > > --- a/include/hw/arm/allwinner-h3.h > > +++ b/include/hw/arm/allwinner-h3.h > > @@ -29,6 +29,7 @@ > >=C2=A0 =C2=A0#include "hw/misc/allwinner-h3-clk.h" > >=C2=A0 =C2=A0#include "hw/misc/allwinner-h3-cpucfg.h" > >=C2=A0 =C2=A0#include "hw/misc/allwinner-h3-syscon.h" > > +#include "hw/misc/allwinner-h3-sid.h" > >=C2=A0 =C2=A0#include "target/arm/cpu.h" > > > >=C2=A0 =C2=A0enum { > > @@ -77,6 +78,7 @@ typedef struct AwH3State { > >=C2=A0 =C2=A0 =C2=A0 =C2=A0AwH3ClockState ccu; > >=C2=A0 =C2=A0 =C2=A0 =C2=A0AwH3CpuCfgState cpucfg; > >=C2=A0 =C2=A0 =C2=A0 =C2=A0AwH3SysconState syscon; > > +=C2=A0 =C2=A0 AwH3SidState sid; > >=C2=A0 =C2=A0 =C2=A0 =C2=A0GICState gic; > >=C2=A0 =C2=A0 =C2=A0 =C2=A0MemoryRegion sram_a1; > >=C2=A0 =C2=A0 =C2=A0 =C2=A0MemoryRegion sram_a2; > > diff --git a/include/hw/misc/allwinner-h3-sid.h > b/include/hw/misc/allwinner-h3-sid.h > > new file mode 100644 > > index 0000000000..79c9a24459 > > --- /dev/null > > +++ b/include/hw/misc/allwinner-h3-sid.h > > @@ -0,0 +1,40 @@ > > +/* > > + * Allwinner H3 Security ID emulation > > + * > > + * Copyright (C) 2019 Niek Linnenbank > > > + * > > + * This program is free software: you can redistribute it and/or > modify > > + * it under the terms of the GNU General Public License as > published by > > + * the Free Software Foundation, either version 2 of the License,= or > > + * (at your option) any later version. > > + * > > + * This program is distributed in the hope that it will be useful= , > > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.=C2=A0 See= the > > + * GNU General Public License for more details. > > + * > > + * You should have received a copy of the GNU General Public Lice= nse > > + * along with this program.=C2=A0 If not, see > . > > + */ > > + > > +#ifndef HW_MISC_ALLWINNER_H3_SID_H > > +#define HW_MISC_ALLWINNER_H3_SID_H > > + > > +#include "hw/sysbus.h" > > +#include "qemu/uuid.h" > > + > > +#define TYPE_AW_H3_SID=C2=A0 =C2=A0 "allwinner-h3-sid" > > +#define AW_H3_SID(obj)=C2=A0 =C2=A0 OBJECT_CHECK(AwH3SidState, (o= bj), > TYPE_AW_H3_SID) > > + > > +typedef struct AwH3SidState { > > +=C2=A0 =C2=A0 /*< private >*/ > > +=C2=A0 =C2=A0 SysBusDevice parent_obj; > > +=C2=A0 =C2=A0 /*< public >*/ > > + > > +=C2=A0 =C2=A0 MemoryRegion iomem; > > +=C2=A0 =C2=A0 uint32_t control; > > +=C2=A0 =C2=A0 uint32_t rdkey; > > +=C2=A0 =C2=A0 QemuUUID identifier; > > +} AwH3SidState; > > + > > +#endif > > diff --git a/hw/arm/allwinner-h3.c b/hw/arm/allwinner-h3.c > > index 1a9748ab2e..ba34f905cd 100644 > > --- a/hw/arm/allwinner-h3.c > > +++ b/hw/arm/allwinner-h3.c > > @@ -196,6 +196,9 @@ static void aw_h3_init(Object *obj) > > > >=C2=A0 =C2=A0 =C2=A0 =C2=A0sysbus_init_child_obj(obj, "cpucfg", &s-= >cpucfg, > sizeof(s->cpucfg), > >=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0TYPE_AW_H3_CPUCFG); > > + > > +=C2=A0 =C2=A0 sysbus_init_child_obj(obj, "sid", &s->sid, sizeof(s= ->sid), > > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 TYPE_AW_H3_SID); >=20 > Here add a property alias: >=20 > =C2=A0 =C2=A0 =C2=A0 =C2=A0 object_property_add_alias(obj, "identifi= er", OBJECT(&s->sid), > =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 "identifier", &error_a= bort); >=20 > >=C2=A0 =C2=A0} > > > >=C2=A0 =C2=A0static void aw_h3_realize(DeviceState *dev, Error **er= rp) > > @@ -332,6 +335,10 @@ static void aw_h3_realize(DeviceState *dev, > Error **errp) > >=C2=A0 =C2=A0 =C2=A0 =C2=A0qdev_init_nofail(DEVICE(&s->cpucfg)); > >=C2=A0 =C2=A0 =C2=A0 =C2=A0sysbus_mmio_map(SYS_BUS_DEVICE(&s->cpucf= g), 0, > s->memmap[AW_H3_CPUCFG]); > > > > +=C2=A0 =C2=A0 /* Security Identifier */ > > +=C2=A0 =C2=A0 qdev_init_nofail(DEVICE(&s->sid)); > > +=C2=A0 =C2=A0 sysbus_mmio_map(SYS_BUS_DEVICE(&s->sid), 0, > s->memmap[AW_H3_SID]); > > + > >=C2=A0 =C2=A0 =C2=A0 =C2=A0/* Universal Serial Bus */ > >=C2=A0 =C2=A0 =C2=A0 =C2=A0sysbus_create_simple(TYPE_AW_H3_EHCI, s-= >memmap[AW_H3_EHCI0], > >=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 qdev_get_gpio_in(DEVICE(&s->gic), > > diff --git a/hw/arm/orangepi.c b/hw/arm/orangepi.c > > index 62cefc8c06..b01c4b4f01 100644 > > --- a/hw/arm/orangepi.c > > +++ b/hw/arm/orangepi.c > > @@ -62,6 +62,10 @@ static void orangepi_init(MachineState *machine= ) > >=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0exit(1); > >=C2=A0 =C2=A0 =C2=A0 =C2=A0} > > > > +=C2=A0 =C2=A0 /* Setup SID properties */ > > +=C2=A0 =C2=A0 qdev_prop_set_string(DEVICE(&s->h3->sid), "identifi= er", > > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0"8100c002-0001-0002-0003-000044556677"); >=20 > And here use the alias: >=20 > =C2=A0 =C2=A0 =C2=A0 =C2=A0 qdev_prop_set_string(DEVICE(&s->h3), "id= entifier", > =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0"8100c002-0001-0002-0003-000044556677= "); >=20 >=20 > Ah OK, I see what you mean. The boards should be using the SoC object=20 > only and > not directly any of its sub devices, correct? >=20 >=20 > What means this value? Don't you want to be able to set it from comma= nd > line? >=20 > The first word 0x02c00081 is the identifying word for the H3 SoC in the= =20 > SID data. > After that come the per-device unique specific bytes. This is documented= =20 > at the end of this page in 'Currently known SID's' on the=20 > linux-sunxi.org Wiki: > https://linux-sunxi.org/SID_Register_Guide >=20 > The remaining parts of this value I simply made up without any real meani= ng. > And yes, it would in fact make sense to have the user be able to=20 > override it from the command line. > It is used by U-boot as an input for generating the MAC address. Linux=20 > also reads it, but I did not investigate > how it us used there. I think I did make a TODO of using a cmdline=20 > argument, but later forgot to actually implement it. >=20 > Do you have a suggestion how to best provide the command line argument?= =20 > I do see '-device driver[,prop=3Dvalue]' > is there in the --help for qemu-system-arm, but it looks like that=20 > should be used by the user for adding PCI / USB devices? Look for '-global' in the manpage: -global driver.prop=3Dvalue -global driver=3Ddriver,property=3Dproperty,value=3Dvalue Set default value of driver's property prop to value. In particular, you can use this to set driver properties for devices which are created automatically by the machine model. To create a device which is not created automatically and set properties on it, use -device. -global driver.prop=3Dvalue is shorthand for -global driver=3Ddriver,property=3Dprop,value=3Dvalue. So this should work for your device: -global=20 allwinner-h3-sid.identifier=3D8100c002-0001-0002-0003-000044556677 >=20 >=20 > >=C2=A0 =C2=A0 =C2=A0 =C2=A0/* Mark H3 object realized */ > >=C2=A0 =C2=A0 =C2=A0 =C2=A0object_property_set_bool(OBJECT(s->h3), = true, "realized", > &error_abort); > >=C2=A0 =C2=A0 =C2=A0 =C2=A0if (error_abort !=3D NULL) { > > diff --git a/hw/misc/allwinner-h3-sid.c b/hw/misc/allwinner-h3-sid= .c > > new file mode 100644 > > index 0000000000..c472f2bcc6 > > --- /dev/null > > +++ b/hw/misc/allwinner-h3-sid.c > > @@ -0,0 +1,179 @@ > > +/* > > + * Allwinner H3 Security ID emulation > > + * > > + * Copyright (C) 2019 Niek Linnenbank > > > + * > > + * This program is free software: you can redistribute it and/or > modify > > + * it under the terms of the GNU General Public License as > published by > > + * the Free Software Foundation, either version 2 of the License,= or > > + * (at your option) any later version. > > + * > > + * This program is distributed in the hope that it will be useful= , > > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.=C2=A0 See= the > > + * GNU General Public License for more details. > > + * > > + * You should have received a copy of the GNU General Public Lice= nse > > + * along with this program.=C2=A0 If not, see > . > > + */ > > + > > +#include "qemu/osdep.h" > > +#include "qemu/units.h" > > +#include "hw/sysbus.h" > > +#include "migration/vmstate.h" > > +#include "qemu/log.h" > > +#include "qemu/module.h" > > +#include "qemu/guest-random.h" > > +#include "qapi/error.h" > > +#include "hw/qdev-properties.h" > > +#include "hw/misc/allwinner-h3-sid.h" > > +#include "trace.h" > > + > > +/* SID register offsets */ > > +enum { > > +=C2=A0 =C2=A0 REG_PRCTL =3D 0x40,=C2=A0 =C2=A0/* Control */ > > +=C2=A0 =C2=A0 REG_RDKEY =3D 0x60,=C2=A0 =C2=A0/* Read Key */ > > +}; > > + > > +/* SID register flags */ > > +enum { > > +=C2=A0 =C2=A0 REG_PRCTL_WRITE=C2=A0 =C2=A0=3D 0x0002, /* Unknown = write flag */ > > +=C2=A0 =C2=A0 REG_PRCTL_OP_LOCK =3D 0xAC00, /* Lock operation */ > > +}; > > + > > +static uint64_t allwinner_h3_sid_read(void *opaque, hwaddr offset= , > > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 unsig= ned size) > > +{ > > +=C2=A0 =C2=A0 const AwH3SidState *s =3D (AwH3SidState *)opaque; > > +=C2=A0 =C2=A0 uint64_t val =3D 0; > > + > > +=C2=A0 =C2=A0 switch (offset) { > > +=C2=A0 =C2=A0 case REG_PRCTL:=C2=A0 =C2=A0 /* Control */ > > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 val =3D s->control; > > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 break; > > +=C2=A0 =C2=A0 case REG_RDKEY:=C2=A0 =C2=A0 /* Read Key */ > > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 val =3D s->rdkey; > > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 break; > > +=C2=A0 =C2=A0 default: > > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 qemu_log_mask(LOG_GUEST_ERROR, "%s: b= ad read offset > 0x%04x\n", > > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 __func__, (uint32_t)offset); > > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 return 0; > > +=C2=A0 =C2=A0 } > > + > > +=C2=A0 =C2=A0 trace_allwinner_h3_sid_read(offset, val, size); > > + > > +=C2=A0 =C2=A0 return val; > > +} > > + > > +static void allwinner_h3_sid_write(void *opaque, hwaddr offset, > > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0uint64_t val,= unsigned size) > > +{ > > +=C2=A0 =C2=A0 AwH3SidState *s =3D (AwH3SidState *)opaque; > > + > > +=C2=A0 =C2=A0 trace_allwinner_h3_sid_write(offset, val, size); > > + > > +=C2=A0 =C2=A0 switch (offset) { > > +=C2=A0 =C2=A0 case REG_PRCTL:=C2=A0 =C2=A0 /* Control */ > > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 s->control =3D val; > > + > > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 if ((s->control & REG_PRCTL_OP_LOCK) = && > > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 (s->control & REG_PRCTL= _WRITE)) { > > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 uint32_t id =3D s->cont= rol >> 16; > > + > > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 if (id < sizeof(QemuUUI= D)) { > > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 s->rdkey = =3D (s->identifier.data[id]) | > > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0(s->identifier.data[id + 1] << 8) | > > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0(s->identifier.data[id + 2] << 16) | > > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0(s->identifier.data[id + 3] << 24); >=20 > This is: >=20 > =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 s->rdkey =3D ldl_le_p(&s->identifier.data[id]); >=20 > > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 } > > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 } > > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 s->control &=3D ~REG_PRCTL_WRITE; > > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 break; > > +=C2=A0 =C2=A0 case REG_RDKEY:=C2=A0 =C2=A0 /* Read Key */ >=20 > Read in a write()? >=20 > Maybe we can simply /* fall through */ LOG_GUEST_ERROR? >=20 >=20 > When writing this module, I looked at how U-Boot is using the SID=20 > registers and simply > named the registers after the names used by U-Boot. You can find this=20 > part in arch/arm/mach-sunxi/cpu_info.c:111, > functions sun8i_efuse_read() and sunxi_get_sid(). U-Boot defines=20 > SIDC_RDKEY, so I named the register also rdkey. > I used the U-Boot source because the Allwinner H3 datasheet does not=20 > document the registers. Later I > found the SID page on the linux-sunxi wiki that I mentioned earlier, and= =20 > they also describe the same register names: >=20 > https://linux-sunxi.org/SID_Register_Guide Hmm this page describe this register as RW, odd. I think this is wrong=20 because we deal with a fuse, and we program it via the REG_PRKEY=20 register. Does Linux/U-Boot do write access to this register? We can start logging LOG_GUEST_ERROR, and correct it if we notice this=20 register is really writable (which I doubt). >=20 > I suspect the information on this page is written based on the source=20 > code from the original SDK (which I did not study btw) [...] From MAILER-DAEMON Mon Dec 30 09:56:29 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1ilwT5-0004J0-Gt for mharc-qemu-arm@gnu.org; Mon, 30 Dec 2019 09:56:28 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:38967) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ilwT1-0004Ij-K8 for qemu-arm@nongnu.org; Mon, 30 Dec 2019 09:56:25 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ilwSz-0005X0-RN for qemu-arm@nongnu.org; Mon, 30 Dec 2019 09:56:23 -0500 Received: from us-smtp-1.mimecast.com ([205.139.110.61]:53783 helo=us-smtp-delivery-1.mimecast.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1ilwSz-0005Wj-Ms for qemu-arm@nongnu.org; Mon, 30 Dec 2019 09:56:21 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1577717780; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=wgFR1xDac1SK2J4H43k2WJfgpKX1rkcdRy+S1pJTjLg=; b=OL0Xr5HFkPagZ47Z3KaqK4oMBnQ+vYOUFRe8DlPo36Sv0bulxAwbsNkqFzBv0o5SndP4UN Ti2DF9kyNx0qoFzKyCqw0TD55BBYa9Tv0P2if3IOuRUMc0YJDNFwSJ9Sbe4HudybxzpXt7 FpolfrbCI4TcJv1qRJLxOodJIqctQM4= Received: from mail-wm1-f71.google.com (mail-wm1-f71.google.com [209.85.128.71]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-178-fNi3vCv7OY6BBakGRkNAwg-1; Mon, 30 Dec 2019 09:56:16 -0500 Received: by mail-wm1-f71.google.com with SMTP id f25so1695394wmb.1 for ; Mon, 30 Dec 2019 06:56:16 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:subject:to:cc:references:from:message-id:date :user-agent:mime-version:in-reply-to:content-language :content-transfer-encoding; bh=03s0E4aQWCdqgJM1YJTbLIKn6CEi/zKfH+0EXS+0kcs=; b=WPxyltAEpp1gs1UeIlIBsk+E5w4H6mP6IW5I0yL+qEIf1iyMC0eyuZYh+bZJOGHTJX AxzOjXqcLAxva5Vo1jjHdJu4/ZlvR0eLQdn0yzz03eRuPzT67aJXCloRKvBm6yOfA9gx CfiyWA37Yz3x6elPI1wsypIPbDpH/wFuy5R53KMiJk9UqJH5hCaY/P/8CVE381yAlJB/ uHuItYAj29GVNGEfwkynHgj66dljOF30wAtqFsctP7MUrWc4IVdDFyld6GsPjT57h83E ctHHoa2dKkKp7BUob6Eo5g3GKd5MCzKh5PJOwvxokmZnNOKn5IK/n6nE7tRiV7LAUZwV dviA== X-Gm-Message-State: APjAAAUhRjW9q7PXuR/22G4ImJb21wDxK2f5SumPP1zcxtaemM2Vo8+p bobY37LwyUZ961k6n7esSu1ADXSQTm+OMkH9n7M2Er9dXyNif08ofc/j0uZbxXzbA/aCCYpsL3o 7VSeIosiyH8t+ X-Received: by 2002:adf:e547:: with SMTP id z7mr69179057wrm.258.1577717775674; Mon, 30 Dec 2019 06:56:15 -0800 (PST) X-Google-Smtp-Source: APXvYqw+9xqU6Ep/6gY5aLLj5xtJwpsRB/bWxg+qSeZqTgRPKb8dNES0beO6L4ICVQ6SxWjKmUgwRg== X-Received: by 2002:adf:e547:: with SMTP id z7mr69179042wrm.258.1577717775489; Mon, 30 Dec 2019 06:56:15 -0800 (PST) Received: from [192.168.1.25] (abayonne-654-1-186-92.w92-134.abo.wanadoo.fr. [92.134.161.92]) by smtp.gmail.com with ESMTPSA id i8sm46050169wro.47.2019.12.30.06.56.13 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 30 Dec 2019 06:56:14 -0800 (PST) Subject: Re: [PATCH v2 00/10] Add Allwinner H3 SoC and Orange Pi PC Machine To: Niek Linnenbank , QEMU Developers Cc: qemu-arm , Peter Maydell References: <20191216233519.29030-1-nieklinnenbank@gmail.com> From: =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= Message-ID: <9756419b-55bf-23a9-556a-d5bc5fb29331@redhat.com> Date: Mon, 30 Dec 2019 15:56:08 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.2.2 MIME-Version: 1.0 In-Reply-To: Content-Language: en-US X-MC-Unique: fNi3vCv7OY6BBakGRkNAwg-1 X-Mimecast-Spam-Score: 0 Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 205.139.110.61 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 30 Dec 2019 14:56:25 -0000 On 12/30/19 12:28 PM, Niek Linnenbank wrote: > Hi, >=20 > Here a short status report of this patch series. Good idea! >=20 > For V3 update I already prepared the following: > =C2=A0- reworked all review comments from Philippe, except: > =C2=A0=C2=A0 - patch#8: question for the SID, whether command-line overr= ide is=20 > required (and how is the best way for machine-specific cli arg?) [1] Answered recently. > - added BootROM support, allows booting with only specifying -sd > - added SDRAM controller driver, for U-Boot SPL > - added Allwinner generic RTC driver (for both Cubieboard and OrangePi=20 > PC, supports sun4i, sun6i, sun7i) > - small fixes for EMAC >=20 > My current TODO: > =C2=A0- integrate Philips acceptance tests in the series You can queue them in your series, adding your Signed-off-by tag after=20 mine. See: https://www.kernel.org/doc/html/latest/process/submitting-patches.html#sign= -your-work-the-developer-s-certificate-of-origin The sign-off is a simple line at the end of the explanation for the=20 patch, which certifies that you wrote it or otherwise have the right to=20 pass it on as an open-source patch. See point (c). > =C2=A0- integrate Philips work for generalizing the Allwinner timer, and= =20 > finish it We can also do that later, and get your work merged first. > =C2=A0- test and fix BSD targets (NetBSD, FreeBSD) [2, 3] > =C2=A0- further generalize the series to cover very similar SoCs: H2+, H= 5 >=20 > Does anyone have more comments/requests for the V3 update? >=20 > [1] https://lists.gnu.org/archive/html/qemu-devel/2019-12/msg04049.html > [2] https://wiki.netbsd.org/ports/evbarm/allwinner/ > [3]=20 > https://wiki.freebsd.org/action/show/arm/Allwinner?action=3Dshow&redirect= =3DFreeBSD%2Farm%2FAllwinner From MAILER-DAEMON Mon Dec 30 10:48:58 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1ilxHu-0007BO-7u for mharc-qemu-arm@gnu.org; Mon, 30 Dec 2019 10:48:58 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:45661) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ilxHr-0007At-Es for qemu-arm@nongnu.org; Mon, 30 Dec 2019 10:48:56 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ilxHo-0005jV-Vn for qemu-arm@nongnu.org; Mon, 30 Dec 2019 10:48:54 -0500 Received: from us-smtp-delivery-1.mimecast.com ([205.139.110.120]:38107 helo=us-smtp-1.mimecast.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1ilxHo-0005jC-Rr for qemu-arm@nongnu.org; Mon, 30 Dec 2019 10:48:52 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1577720932; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=eie/6KGuYr/9B08JptfZ0j1vbtpHyZvG/k91jGibVJI=; b=U7SrG0GZRALE9LI+quLHuM/1NPTegvkCuBNBq9M/1U1tpTo038WDe+8J7amnudxQ9E+M8k ApJ72Ab05Wkc5dsb54wUxQYqS9q49t8c3H+H3AUBLv+9qvYT1UTrXFZBJpXOwafUs0YR28 /IoibORBlHh8JZrwX3MmeUcamhv1fw4= Received: from mail-wr1-f72.google.com (mail-wr1-f72.google.com [209.85.221.72]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-400-Ea5d1odFO3yRl4YqTr75-A-1; Mon, 30 Dec 2019 10:48:50 -0500 Received: by mail-wr1-f72.google.com with SMTP id 90so17778541wrq.6 for ; Mon, 30 Dec 2019 07:48:50 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc:content-transfer-encoding; bh=eie/6KGuYr/9B08JptfZ0j1vbtpHyZvG/k91jGibVJI=; b=Ky4T9T1ZW0N3BYGz0T2Om7nTzJ5+HMwx2mPCdy34gikrHuUkpaiEjwfvkcexp15taz 4Be49RD5XkKTm35ki0ldoRdqlMqcG26yyEII8NN+29tOWTduJz4NV+kVVzcQhP01wMOh CUUTcU+tIvsQekqoxKSUi2IhVPGmA48qgaIuZJgLHOvJ1uobTYdPq+h2HdVGFnHJHFK8 KCywWpNebmyZSMJk9x34DcKnMZjb4GWWfN8DZPLE13xoGTIP3KN1eeHQP6xdf3NWF2re 2szWanjPdfmt7pvkUXSuK9wmlwpAw07yHozoNg+5AuBMBf8JhSo6btwY2g3Mor3J5/eu R2YA== X-Gm-Message-State: APjAAAVdVA0krRuyc2QCOvabf4f9/iVlQvw8aTP8N1XyytjW22i+ZleH 9Hl/ptXqUGX5wPZD4CPigHHkXRR95ZwkVKxbER6i6iTVMK239XOc2QAEMZHRB213BhhK+SeXYIc /mtcGDDWvV/mZjj4nBPP2khJuc9vU X-Received: by 2002:adf:f20b:: with SMTP id p11mr65711242wro.195.1577720929381; Mon, 30 Dec 2019 07:48:49 -0800 (PST) X-Google-Smtp-Source: APXvYqy3CnY+as7x2kI0Y6CBZEeBLW/sV1Fr9aas6dYnp/Xbl2nb3n59pazc3GXJTotgX7e+xWtVEzEAKTxk0ILTwPE= X-Received: by 2002:adf:f20b:: with SMTP id p11mr65711205wro.195.1577720929179; Mon, 30 Dec 2019 07:48:49 -0800 (PST) MIME-Version: 1.0 References: <20191230090900.446-1-philmd@redhat.com> <20191230090900.446-2-philmd@redhat.com> <273bf2e5-1223-3d01-f930-394195c037e4@weilnetz.de> <64c2434d-3b2b-1a3e-5358-e4b5acfbe8e8@redhat.com> In-Reply-To: From: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= Date: Mon, 30 Dec 2019 16:48:38 +0100 Message-ID: Subject: Re: [PATCH 1/2] tcg: Search includes from the project root source directory To: Paolo Bonzini Cc: Stefan Weil , qemu-devel , Markus Armbruster , Richard Henderson , Aurelien Jarno , "open list:sPAPR" , Peter Maydell , Riku Voipio , Aleksandar Rikalo , Andrzej Zaborowski , Laurent Vivier , Max Filippov , Claudio Fontana , "open list:S390 Virtio-ccw" , Sagar Karandikar , Marek Vasut , Artyom Tarasenko , Chris Wulff , Bastian Koppelmann , Cornelia Huck , Palmer Dabbelt , Richard Henderson , qemu-arm , "Edgar E. Iglesias" , Mark Cave-Ayland , David Hildenbrand , Anthony Green , Eduardo Habkost , Alistair Francis , Stafford Horne , Guan Xuetao , Michael Walle , Aleksandar Markovic , David Gibson , "open list:RISC-V" X-MC-Unique: Ea5d1odFO3yRl4YqTr75-A-1 X-Mimecast-Spam-Score: 0 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 205.139.110.120 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 30 Dec 2019 15:48:57 -0000 On Mon, Dec 30, 2019 at 3:02 PM Philippe Mathieu-Daud=C3=A9 wrote: > On 12/30/19 11:33 AM, Paolo Bonzini wrote: > > Il lun 30 dic 2019, 09:59 Philippe Mathieu-Daud=C3=A9 > > ha scritto: > > > > > I'd prefer not changing those files. > > > > OK, I'll wait to see what Richard/Markus prefer. > > > > > > I think it's best if you keep the include directives as-is for files > > only needed from tcg/, and move the other headers (those that are neede= d > > from other directories only) to include/tcg. Assuming we don't want to add include/tcg/ in the path search list, we still need to update the tcg/*.c include directives to use "tcg/": tcg/tcg-op-gvec.c:21:10: fatal error: tcg.h: No such file or directory 21 | #include "tcg.h" | ^~~~~~~ compilation terminated. make[1]: *** [rules.mak:69: tcg/tcg-op-gvec.o] Error 1 make[1]: *** Waiting for unfinished jobs.... CC mips64el-softmmu/accel/tcg/translate-all.o tcg/optimize.c:27:10: fatal error: tcg-op.h: No such file or directory 27 | #include "tcg-op.h" | ^~~~~~~~~~ compilation terminated. make[1]: *** [rules.mak:69: tcg/optimize.o] Error 1 tcg/tcg-op-vec.c:22:10: fatal error: tcg.h: No such file or directory 22 | #include "tcg.h" | ^~~~~~~ compilation terminated. make[1]: *** [rules.mak:69: tcg/tcg-op-vec.o] Error 1 tcg/tcg-common.c:35:10: fatal error: tcg-opc.h: No such file or directory 35 | #include "tcg-opc.h" | ^~~~~~~~~~~ compilation terminated. make[1]: *** [rules.mak:69: tcg/tcg-common.o] Error 1 tcg/tcg-op.c:28:10: fatal error: tcg.h: No such file or directory 28 | #include "tcg.h" | ^~~~~~~ compilation terminated. make[1]: *** [rules.mak:69: tcg/tcg-op.o] Error 1 tcg/tcg.c:51:10: fatal error: tcg-op.h: No such file or directory 51 | #include "tcg-op.h" | ^~~~~~~~~~ compilation terminated. > I thought moving headers to include/tcg would diverge too much from > libtcg, but this project already did it, so why not: > https://github.com/S2E/libtcg/tree/master/include/tcg From MAILER-DAEMON Mon Dec 30 12:47:35 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1ilz8h-00019U-Ml for mharc-qemu-arm@gnu.org; Mon, 30 Dec 2019 12:47:35 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:58348) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ilz8e-00018r-Ti for qemu-arm@nongnu.org; Mon, 30 Dec 2019 12:47:34 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ilz8d-00089I-3o for qemu-arm@nongnu.org; Mon, 30 Dec 2019 12:47:32 -0500 Received: from us-smtp-delivery-1.mimecast.com ([205.139.110.120]:37778 helo=us-smtp-1.mimecast.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1ilz8d-00088w-0b for qemu-arm@nongnu.org; Mon, 30 Dec 2019 12:47:31 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1577728050; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: in-reply-to:in-reply-to:references:references; bh=MJStdeV/YujZAu6ZNEHr5cAMDE1K9kOphOPj3BCNNbs=; b=XueBamnL8bybun48zCS8NyN3nWMA5IhnH/a4IGTKu5PxK28aYGGk1uMr+WqSweP0Qef7U9 09ch9GU62ejee9Sj/zOSrItocEzwC/R+Oz7OotqNXlSOisC+TitA82bKSjoWEWYITgwLH/ Bo7IUain5MW4caRloAZL7zUsrKhaAUo= Received: from mail-ed1-f70.google.com (mail-ed1-f70.google.com [209.85.208.70]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-44-0D84hdv-PDOOVJBHYMj4YA-1; Mon, 30 Dec 2019 12:47:27 -0500 Received: by mail-ed1-f70.google.com with SMTP id cy24so18952895edb.12 for ; Mon, 30 Dec 2019 09:47:27 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=MJStdeV/YujZAu6ZNEHr5cAMDE1K9kOphOPj3BCNNbs=; b=gjeg+ejoIDeQnHlUlSNU2n1t9wbZZqb/9RFaqhNbuGQ+KTsG6dXnOUZQNdlwIy/gid SSIzcgGziwB6k1nRLZFiPWzBQbcTqnPZTwPcNLcHBkitlIdafEtTPtmK5IncUqJUUwtF hV9HABaQEr5t57oYy0dh7vPijN+nUrrN1CqF/OQzl3J0OjiufFS6qbnoCvRVHi2VjKdg A/891QzQ6EBUihpw66FjRBr8RjWGHbNlcBcpF21ElWXTI4wKN1a5QYyqAkmIJXcL0A85 zJ1PRrhVhwZ4xY0+t1zSn2OwmBYouWmj/34wqNf9+3UbMw1mGmH/zcG+MTeQ+BbtoIiZ xNuw== X-Gm-Message-State: APjAAAVrtWNxrl6s92uXYAK2vHNWJKfV0e/7gMQ33B885sSMr+9jaEFC lLMlMorM81fonlyuR9BVc8oaNc1LBl0/RXtjZHsvILJtkD6hlvormrIlVtfbh6pkPSbuTDcoQ57 RNHe/ihmLx533kBRsGRSk9FCY/wHF X-Received: by 2002:aa7:d9c6:: with SMTP id v6mr72198552eds.107.1577728046184; Mon, 30 Dec 2019 09:47:26 -0800 (PST) X-Google-Smtp-Source: APXvYqyqZ1wCnv2+UU94l9WCkgm0AhWdAWlM9y7C1eMgbU9R91PpZZoZ+bMWivxkmpNuVXjfIt0cXlAv+6Iz1hz2+r8= X-Received: by 2002:aa7:d9c6:: with SMTP id v6mr72198492eds.107.1577728045890; Mon, 30 Dec 2019 09:47:25 -0800 (PST) MIME-Version: 1.0 References: <20191230090900.446-1-philmd@redhat.com> <20191230090900.446-2-philmd@redhat.com> <273bf2e5-1223-3d01-f930-394195c037e4@weilnetz.de> <64c2434d-3b2b-1a3e-5358-e4b5acfbe8e8@redhat.com> In-Reply-To: From: Paolo Bonzini Date: Mon, 30 Dec 2019 18:46:37 +0100 Message-ID: Subject: Re: [PATCH 1/2] tcg: Search includes from the project root source directory To: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= Cc: Stefan Weil , qemu-devel , Markus Armbruster , Richard Henderson , Aurelien Jarno , "open list:sPAPR" , Peter Maydell , Riku Voipio , Aleksandar Rikalo , Andrzej Zaborowski , Laurent Vivier , Max Filippov , Claudio Fontana , "open list:S390 Virtio-ccw" , Sagar Karandikar , Marek Vasut , Artyom Tarasenko , Chris Wulff , Bastian Koppelmann , Cornelia Huck , Palmer Dabbelt , Richard Henderson , qemu-arm , "Edgar E. Iglesias" , Mark Cave-Ayland , David Hildenbrand , Anthony Green , Eduardo Habkost , Alistair Francis , Stafford Horne , Guan Xuetao , Michael Walle , Aleksandar Markovic , David Gibson , "open list:RISC-V" X-MC-Unique: 0D84hdv-PDOOVJBHYMj4YA-1 X-Mimecast-Spam-Score: 0 Content-Type: multipart/alternative; boundary="000000000000ba6063059aef6f6f" X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 205.139.110.120 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 30 Dec 2019 17:47:34 -0000 --000000000000ba6063059aef6f6f Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Yes, of course (I thought it would be clear from the message, but perhaps it was a bit implicit). Paolo Il lun 30 dic 2019, 16:48 Philippe Mathieu-Daud=C3=A9 h= a scritto: > On Mon, Dec 30, 2019 at 3:02 PM Philippe Mathieu-Daud=C3=A9 > wrote: > > On 12/30/19 11:33 AM, Paolo Bonzini wrote: > > > Il lun 30 dic 2019, 09:59 Philippe Mathieu-Daud=C3=A9 > > > ha scritto: > > > > > > > I'd prefer not changing those files. > > > > > > OK, I'll wait to see what Richard/Markus prefer. > > > > > > > > > I think it's best if you keep the include directives as-is for files > > > only needed from tcg/, and move the other headers (those that are > needed > > > from other directories only) to include/tcg. > > Assuming we don't want to add include/tcg/ in the path search list, we > still need to update the tcg/*.c include directives to use "tcg/": > > tcg/tcg-op-gvec.c:21:10: fatal error: tcg.h: No such file or directory > 21 | #include "tcg.h" > | ^~~~~~~ > compilation terminated. > make[1]: *** [rules.mak:69: tcg/tcg-op-gvec.o] Error 1 > make[1]: *** Waiting for unfinished jobs.... > CC mips64el-softmmu/accel/tcg/translate-all.o > tcg/optimize.c:27:10: fatal error: tcg-op.h: No such file or directory > 27 | #include "tcg-op.h" > | ^~~~~~~~~~ > compilation terminated. > make[1]: *** [rules.mak:69: tcg/optimize.o] Error 1 > tcg/tcg-op-vec.c:22:10: fatal error: tcg.h: No such file or directory > 22 | #include "tcg.h" > | ^~~~~~~ > compilation terminated. > make[1]: *** [rules.mak:69: tcg/tcg-op-vec.o] Error 1 > tcg/tcg-common.c:35:10: fatal error: tcg-opc.h: No such file or directory > 35 | #include "tcg-opc.h" > | ^~~~~~~~~~~ > compilation terminated. > make[1]: *** [rules.mak:69: tcg/tcg-common.o] Error 1 > tcg/tcg-op.c:28:10: fatal error: tcg.h: No such file or directory > 28 | #include "tcg.h" > | ^~~~~~~ > compilation terminated. > make[1]: *** [rules.mak:69: tcg/tcg-op.o] Error 1 > tcg/tcg.c:51:10: fatal error: tcg-op.h: No such file or directory > 51 | #include "tcg-op.h" > | ^~~~~~~~~~ > compilation terminated. > > > I thought moving headers to include/tcg would diverge too much from > > libtcg, but this project already did it, so why not: > > https://github.com/S2E/libtcg/tree/master/include/tcg > > --000000000000ba6063059aef6f6f Content-Type: text/html; charset="UTF-8" Content-Transfer-Encoding: quoted-printable
Yes, of course (I thought it would be clear from the mess= age, but perhaps it was a bit implicit).

Paolo

Il lun 30 dic 2019, 16:48 Philippe Mathieu-Daud=C3=A9= <philmd@redhat.com> ha scri= tto:
On Mon, Dec 30, 2019 at 3:02 P= M Philippe Mathieu-Daud=C3=A9
<philmd@redhat.com> wrote:
> On 12/30/19 11:33 AM, Paolo Bonzini wrote:
> > Il lun 30 dic 2019, 09:59 Philippe Mathieu-Daud=C3=A9 <philmd@r= edhat.com
> > <mailto:philmd@redhat.com>> ha scritto:
> >
> >=C2=A0 =C2=A0 =C2=A0 > I'd prefer not changing those files.=
> >
> >=C2=A0 =C2=A0 =C2=A0OK, I'll wait to see what Richard/Markus p= refer.
> >
> >
> > I think it's best if you keep the include directives as-is fo= r files
> > only needed from tcg/, and move the other headers (those that are= needed
> > from other directories only) to include/tcg.

Assuming we don't want to add include/tcg/ in the path search list, we<= br> still need to update the tcg/*.c include directives to use "tcg/"= :

tcg/tcg-op-gvec.c:21:10: fatal error: tcg.h: No such file or directory
=C2=A0 =C2=A021 | #include "tcg.h"
=C2=A0 =C2=A0 =C2=A0 |=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 ^~~~~~~
compilation terminated.
make[1]: *** [rules.mak:69: tcg/tcg-op-gvec.o] Error 1
make[1]: *** Waiting for unfinished jobs....
=C2=A0 CC=C2=A0 =C2=A0 =C2=A0 mips64el-softmmu/accel/tcg/translate-all.o tcg/optimize.c:27:10: fatal error: tcg-op.h: No such file or directory
=C2=A0 =C2=A027 | #include "tcg-op.h"
=C2=A0 =C2=A0 =C2=A0 |=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 ^~~~~~~~~~
compilation terminated.
make[1]: *** [rules.mak:69: tcg/optimize.o] Error 1
tcg/tcg-op-vec.c:22:10: fatal error: tcg.h: No such file or directory
=C2=A0 =C2=A022 | #include "tcg.h"
=C2=A0 =C2=A0 =C2=A0 |=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 ^~~~~~~
compilation terminated.
make[1]: *** [rules.mak:69: tcg/tcg-op-vec.o] Error 1
tcg/tcg-common.c:35:10: fatal error: tcg-opc.h: No such file or directory =C2=A0 =C2=A035 | #include "tcg-opc.h"
=C2=A0 =C2=A0 =C2=A0 |=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 ^~~~~~~~~~~
compilation terminated.
make[1]: *** [rules.mak:69: tcg/tcg-common.o] Error 1
tcg/tcg-op.c:28:10: fatal error: tcg.h: No such file or directory
=C2=A0 =C2=A028 | #include "tcg.h"
=C2=A0 =C2=A0 =C2=A0 |=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 ^~~~~~~
compilation terminated.
make[1]: *** [rules.mak:69: tcg/tcg-op.o] Error 1
tcg/tcg.c:51:10: fatal error: tcg-op.h: No such file or directory
=C2=A0 =C2=A051 | #include "tcg-op.h"
=C2=A0 =C2=A0 =C2=A0 |=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 ^~~~~~~~~~
compilation terminated.

> I thought moving headers to include/tcg would diverge too much from > libtcg, but this project already did it, so why not:
> https://github.com/S2E/libtcg/= tree/master/include/tcg

--000000000000ba6063059aef6f6f-- From MAILER-DAEMON Mon Dec 30 15:05:40 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1im1IK-0005We-3a for mharc-qemu-arm@gnu.org; Mon, 30 Dec 2019 15:05:40 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:53142) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1im1IG-0005Sq-K5 for qemu-arm@nongnu.org; Mon, 30 Dec 2019 15:05:37 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1im1IF-0004KH-3y for qemu-arm@nongnu.org; Mon, 30 Dec 2019 15:05:36 -0500 Received: from mail-il1-x143.google.com ([2607:f8b0:4864:20::143]:37929) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1im1IB-00049i-P6; Mon, 30 Dec 2019 15:05:31 -0500 Received: by mail-il1-x143.google.com with SMTP id f5so28671443ilq.5; Mon, 30 Dec 2019 12:05:31 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=g9X2mXf5DKOk0UjALzlwCxcS5bofOS+FPHTLLKTZLb0=; b=U+LVjlR9VUfWJd8YR/HXe5XyBRM3BY0WeDDqFP/xXyqFIOaLMggKICSb4FJtrNmNb+ XLJ1sLfJWIKBC7IFYDR9H2+gBs6OSnDIRESmYqlTXtEeuSCy5wBS6lU7U9+E1wfW1kRN uZMmAoWvIl17c8w3wcd70L+T7q2D9DprlV6wXOqSWO9JkavImyoZW1Fjtajj3UGFT1uc p60OVoYId8kXY8ufspNBto0VPjatO7lg6K862otGeWaMaIv+rZP3Ypd2Abt2Ek+7e88v 4WeKeZJPyogrr6MGQcQ+ZVYYpujpTzC8nIL6FJfiXcZpoQbrfV/sWkSnvGKdw9vW22Td aB6A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=g9X2mXf5DKOk0UjALzlwCxcS5bofOS+FPHTLLKTZLb0=; b=smKj+FUoByU9bYFdTqAW0pBwwzfwZHfUPnIkrgCRAdEKWVA7wWr4AEOHOls5C5SHqV tXjnh0d+3al3p2ys3Xka7oWWuhRYSwZ8Xx5TVm4uYB3yOGLyyyItp5ryyl53j+1eeRpI pv8+tdIwcM0hx9YoJd3cxNS/AvWwGX0qQr7SUlcjl3W3NFd0rXoK2yVBKbh+aQpkPMA0 0MUXRZsmCRdBeoDQG0jNXfgFYBVJbxfB+yAh7nkPC7KPOyAPkmeYa2H7X5+/ro6QH82s CiWjafBnJQQ/qrTUpyb82BVQNr314zZKsJ+nh0evGkEnTb/oBJh+rgC9Gqdz5MGoSSF2 ZgZg== X-Gm-Message-State: APjAAAVTMXy+bihx8Zf+k6vvoJIs5ip3V16zujnG6SRhvVmgx8zByBSw kh6dvxQ0jUpqDl5tZQr0Fyxw7gRKpbSO+/rukWo= X-Google-Smtp-Source: APXvYqzXxSC2IBjbjyYZY8uFgCDT+5fcS0Xoe+yivePI9lnNAckDpedhw8/Xx0DzpnG8ArDj0EaNR9vXval00uoz+Xs= X-Received: by 2002:a92:d5cf:: with SMTP id d15mr56490425ilq.306.1577736330877; Mon, 30 Dec 2019 12:05:30 -0800 (PST) MIME-Version: 1.0 References: <20191230110953.25496-1-f4bug@amsat.org> <20191230110953.25496-7-f4bug@amsat.org> <9cdbe625-fe29-cb91-2ed4-1231953b3148@redhat.com> In-Reply-To: <9cdbe625-fe29-cb91-2ed4-1231953b3148@redhat.com> From: Niek Linnenbank Date: Mon, 30 Dec 2019 21:05:19 +0100 Message-ID: Subject: Re: [RFC PATCH 6/6] hw/arm/cubieboard: Disable unsupported M-USB in device tree blob To: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= Cc: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= , Peter Maydell , QEMU Developers , Wainer dos Santos Moschetta , Beniamino Galvani , qemu-arm , Willian Rampazzo , Cleber Rosa Content-Type: multipart/alternative; boundary="0000000000008d2163059af15d66" X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::143 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 30 Dec 2019 20:05:38 -0000 --0000000000008d2163059af15d66 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Hey Philippe, I took a second look at this and, it seems my previous suggestion was only partly valid. The kernel error you reported came from the driver in drivers/usb/musb/sunxi.c. Apparently, this is an Allwinner specific driver for M-USB. And I don't see it documented in the A10 user manual. On the other hand, the USB host interfaces EHCI/OHCI do apply for the A10 SoC and this board. Linux has them defined in the DTB in arch/arm/boot/dts/sun4i-a10.dtsi (ehci0/1, ohci0/1). But probably that is for another patch/commit. Regards, Niek On Mon, Dec 30, 2019 at 2:56 PM Philippe Mathieu-Daud=C3=A9 wrote: > On 12/30/19 12:33 PM, Niek Linnenbank wrote: > > Hello Philippe, > > > > I have a suggestion: probably you can apply (almost) the same patch to > > get USB > > working for A10 as I did in the Allwinner H3, in patch #4 "add USB host > > controller" [1] > > That way you can avoid the DTB modifications and with low effort get US= B > > working as well for this board. > > As far as I can see, in Section 21.1 in the A10 user manual [2] has the > > same description > > as for the H3. It basically has the standard EHCI and OHCI interfaces. > > Oh good news. I guess in the long term we want a AllwinnerSoc parent > class where all common blocks are mapped, and A10/H3 children with the > differences. But we'll worry about that after your H3 series get merged. > > > [1] https://lists.gnu.org/archive/html/qemu-devel/2019-12/msg03266.html > > [2] https://linux-sunxi.org/File:Allwinner_A10_User_manual_V1.5.pdf > > > > Regards, > > Niek > > --=20 Niek Linnenbank --0000000000008d2163059af15d66 Content-Type: text/html; charset="UTF-8" Content-Transfer-Encoding: quoted-printable
Hey Philippe,

I took a second look at this and, it seems my previous suggestion was onl= y partly valid.
The kernel error you reported came from the driv= er in drivers/usb/musb/sunxi.c. Apparently, this
is an Allwinner = specific driver for M-USB. And I don't see it documented in the A10 use= r manual.

On the other hand, the USB host interfac= es EHCI/OHCI do apply for the A10 SoC and this board.
Linux has t= hem defined in the DTB in arch/arm/boot/dts/sun4i-a10.dtsi (ehci0/1, ohci0/= 1).
But probably that is for another patch/commit.

=
Regards,
Niek

On Mon, Dec 30, 2019 at 2:= 56 PM Philippe Mathieu-Daud=C3=A9 <= philmd@redhat.com> wrote:
On 12/30/19 12:33 PM, Niek Linnenbank wrote:
> Hello Philippe,
>
> I have a suggestion: probably you can apply (almost) the same patch to=
> get USB
> working for A10 as I did in the Allwinner H3, in patch #4 "add US= B host
> controller" [1]
> That way you can avoid the DTB modifications and with low effort get U= SB
> working as well for this board.
> As far as I can see, in Section 21.1 in the A10 user manual [2] has th= e
> same description
> as for the H3. It basically has the standard EHCI and OHCI interfaces.=

Oh good news. I guess in the long term we want a AllwinnerSoc parent
class where all common blocks are mapped, and A10/H3 children with the
differences. But we'll worry about that after your H3 series get merged= .

> [1] https://lists.gnu.org/ar= chive/html/qemu-devel/2019-12/msg03266.html
> [2] https://linux-sunxi.org/File= :Allwinner_A10_User_manual_V1.5.pdf
>
> Regards,
> Niek



--
Niek Linnenbank

--0000000000008d2163059af15d66-- From MAILER-DAEMON Mon Dec 30 15:10:56 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1im1NP-0007AG-UK for mharc-qemu-arm@gnu.org; Mon, 30 Dec 2019 15:10:55 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:40477) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1im1NN-00077T-2A for qemu-arm@nongnu.org; Mon, 30 Dec 2019 15:10:54 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1im1NL-0001YP-7A for qemu-arm@nongnu.org; Mon, 30 Dec 2019 15:10:52 -0500 Received: from mail-il1-x143.google.com ([2607:f8b0:4864:20::143]:42987) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1im1NH-0001Vi-GB; Mon, 30 Dec 2019 15:10:47 -0500 Received: by mail-il1-x143.google.com with SMTP id t2so13339140ilq.9; Mon, 30 Dec 2019 12:10:47 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=c5Otgqe1JRl3ZBdsNri3GHgmpT8tEdVyUo3kmz6/T+E=; b=nHu/QICPy38pKXiJytNHC3k9WAaRmuFm03T2mS1YS6hjm0tceRB8a+VfPZ0wd2liRF jjLQLaXbagB/Az4DRNX7Zak7YLuseHIrUmkA2kk5hXHncZckWilFoK8mAjWYkQnsZH8u v6TZnybijrVOFe8l7cM7lzihSmrTp9C9xS52hzR5OC4MoFVr3dXST933W0INdPOREiK/ zwS7lXLFVNcG/q2dDCMKYLLf0xU4cH6jvjaS7ZvesxJj3jqxcUxiANcN38Ufv8oA/L49 cnlW4Sq0BzpN0S0KR8+5HiwPLpRGPD2bCl6ZQuLs9flBlPPeN4GKYx4DblJ+cMbaObsl l87Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=c5Otgqe1JRl3ZBdsNri3GHgmpT8tEdVyUo3kmz6/T+E=; b=OUwg/yJxvtDuf/0dtcTSRg6Jeypw2bZcdti6JZybh5qHoFV76CR4Jm7jdaAHdqZUcv INwiiEua2V355Uod6bR4WnaZ+5Qab70+OXM+kEnY9QUgQspC7MhiHlw8/4s7KBICzqNQ rNKmqckWYKJM81FR8lFll6FYIqqE5X7CjuKqcSGhi0qCD3/QWfSIuTszULAUjqMrpACW XtY4qd6TGmudFM3qDa+vclJyiGbltRAadYdaJg31RUPwyVEVIdcIrmiMELbOIzopwb4Q 36jg5HK+mDw1r/NdF5sBoXw68yVev38Hpi7hlu6w9oLBnMWS9/E+pKMZj0p4vfEu32b2 6KEA== X-Gm-Message-State: APjAAAUZFlrAzo55hDFSJUwwr9d6s+aNTf8Wvf7rxFhomSUEI4zH0TTh 5ptwyI2j5KUIKjTDpQ/GSEM8q7v4wov2k2Ma/zs= X-Google-Smtp-Source: APXvYqwWNYypmvf2xieWXZJPHdbhwYTQ0eFkR4W4S510235nkZJPeatnJa21ZYeFHrDZsW7NW2cN2NXdebWeMU7kHSw= X-Received: by 2002:a92:7509:: with SMTP id q9mr36693120ilc.67.1577736646489; Mon, 30 Dec 2019 12:10:46 -0800 (PST) MIME-Version: 1.0 References: <20191216233519.29030-1-nieklinnenbank@gmail.com> <9756419b-55bf-23a9-556a-d5bc5fb29331@redhat.com> In-Reply-To: <9756419b-55bf-23a9-556a-d5bc5fb29331@redhat.com> From: Niek Linnenbank Date: Mon, 30 Dec 2019 21:10:35 +0100 Message-ID: Subject: Re: [PATCH v2 00/10] Add Allwinner H3 SoC and Orange Pi PC Machine To: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= Cc: QEMU Developers , qemu-arm , Peter Maydell Content-Type: multipart/alternative; boundary="0000000000005cfd1c059af17074" X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::143 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 30 Dec 2019 20:10:54 -0000 --0000000000005cfd1c059af17074 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable On Mon, Dec 30, 2019 at 3:56 PM Philippe Mathieu-Daud=C3=A9 wrote: > On 12/30/19 12:28 PM, Niek Linnenbank wrote: > > Hi, > > > > Here a short status report of this patch series. > > Good idea! > > > > > For V3 update I already prepared the following: > > - reworked all review comments from Philippe, except: > > - patch#8: question for the SID, whether command-line override is > > required (and how is the best way for machine-specific cli arg?) [1] > > Answered recently. > Thanks! > > > - added BootROM support, allows booting with only specifying -sd > > - added SDRAM controller driver, for U-Boot SPL > > - added Allwinner generic RTC driver (for both Cubieboard and OrangePi > > PC, supports sun4i, sun6i, sun7i) > > - small fixes for EMAC > > > > My current TODO: > > - integrate Philips acceptance tests in the series > > You can queue them in your series, adding your Signed-off-by tag after > mine. See: > > https://www.kernel.org/doc/html/latest/process/submitting-patches.html#si= gn-your-work-the-developer-s-certificate-of-origin > > The sign-off is a simple line at the end of the explanation for the > patch, which certifies that you wrote it or otherwise have the right to > pass it on as an open-source patch. > > See point (c). > > Ah that certainly helps. I'll read that page. > > - integrate Philips work for generalizing the Allwinner timer, and > > finish it > > We can also do that later, and get your work merged first. > Ok that sounds very good! Agreed, lets do the timer work later. > > > - test and fix BSD targets (NetBSD, FreeBSD) [2, 3] > > - further generalize the series to cover very similar SoCs: H2+, H5 > > > > Does anyone have more comments/requests for the V3 update? > > > > [1] https://lists.gnu.org/archive/html/qemu-devel/2019-12/msg04049.html > > [2] https://wiki.netbsd.org/ports/evbarm/allwinner/ > > [3] > > > https://wiki.freebsd.org/action/show/arm/Allwinner?action=3Dshow&redirect= =3DFreeBSD%2Farm%2FAllwinner > > --=20 Niek Linnenbank --0000000000005cfd1c059af17074 Content-Type: text/html; charset="UTF-8" Content-Transfer-Encoding: quoted-printable


=
On Mon, Dec 30, 2019 at 3:56 PM Phili= ppe Mathieu-Daud=C3=A9 <philmd@redh= at.com> wrote:
On 12/30/19 12:28 PM, Niek Linnenbank wrote:
> Hi,
>
> Here a short status report of this patch series.

Good idea!

>
> For V3 update I already prepared the following:
>=C2=A0 =C2=A0- reworked all review comments from Philippe, except:
>=C2=A0 =C2=A0=C2=A0 - patch#8: question for the SID, whether command-li= ne override is
> required (and how is the best way for machine-specific cli arg?) [1]
Answered recently.
Thanks!

> - added BootROM support, allows booting with only specifying -sd <I= MG>
> - added SDRAM controller driver, for U-Boot SPL
> - added Allwinner generic RTC driver (for both Cubieboard and OrangePi=
> PC, supports sun4i, sun6i, sun7i)
> - small fixes for EMAC
>
> My current TODO:
>=C2=A0 =C2=A0- integrate Philips acceptance tests in the series

You can queue them in your series, adding your Signed-off-by tag after
mine. See:
https://www.kernel.org/doc/html/latest/process/submi= tting-patches.html#sign-your-work-the-developer-s-certificate-of-origin=

=C2=A0 =C2=A0The sign-off is a simple line at the end of the explanation fo= r the
patch, which certifies that you wrote it or otherwise have the right to pass it on as an open-source patch.

See point (c).

Ah that certainly helps. I'll read that page.
=
=C2=A0
>=C2=A0 =C2=A0- integrate Philips work for generalizing the Allwinner ti= mer, and
> finish it

We can also do that later, and get your work merged first.
=

Ok that sounds very good! Agreed, lets do the timer wor= k later.
=C2=A0

>=C2=A0 =C2=A0- test and fix BSD targets (NetBSD, FreeBSD) [2, 3]
>=C2=A0 =C2=A0- further generalize the series to cover very similar SoCs= : H2+, H5
>
> Does anyone have more comments/requests for the V3 update?
>
> [1] https://lists.gnu.org/ar= chive/html/qemu-devel/2019-12/msg04049.html
> [2] https://wiki.netbsd.org/ports/evbarm/allwinn= er/
> [3]
> https://wiki.freebsd.org/action/show/arm/Allwinner?action=3Dsho= w&redirect=3DFreeBSD%2Farm%2FAllwinner



--
Niek Linnenbank

--0000000000005cfd1c059af17074-- From MAILER-DAEMON Mon Dec 30 15:52:34 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1im21i-00043Z-LT for mharc-qemu-arm@gnu.org; Mon, 30 Dec 2019 15:52:34 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:50461) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1im21f-00043O-3Q for qemu-arm@nongnu.org; Mon, 30 Dec 2019 15:52:32 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1im21c-0000I4-5I for qemu-arm@nongnu.org; Mon, 30 Dec 2019 15:52:29 -0500 Received: from us-smtp-delivery-1.mimecast.com ([207.211.31.120]:34234 helo=us-smtp-1.mimecast.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1im21b-0000GE-Io for qemu-arm@nongnu.org; Mon, 30 Dec 2019 15:52:28 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1577739146; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=Zc0FTPmlN/eRAhViCLUrPsRLUXsok9bOT2zdMSbRLgQ=; b=R8X1ijzzwhP2BLHQXQe7+C7Ec4lqGlZV+KePHM+EzWmQ+aRsmT1+jbEn43b0dVmGog84bW gBr5li2m2Z+o5WwlKbuuVU7lN+iDB8m7ZbKwfI/pTrJulTj2M6w//qzELlyvnlznhvtA31 Qh3j1sm7cjWWhsWQQ9+23Xmyab7h9lQ= Received: from mimecast-mx01.redhat.com (mimecast-mx01.redhat.com [209.132.183.4]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-39-NjHmOij-PCKjhle4dijyog-1; Mon, 30 Dec 2019 15:52:21 -0500 Received: from smtp.corp.redhat.com (int-mx01.intmail.prod.int.phx2.redhat.com [10.5.11.11]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx01.redhat.com (Postfix) with ESMTPS id 797B2107ACC5; Mon, 30 Dec 2019 20:52:19 +0000 (UTC) Received: from localhost.localdomain (ovpn-116-92.gru2.redhat.com [10.97.116.92]) by smtp.corp.redhat.com (Postfix) with ESMTP id C0BF778E81; Mon, 30 Dec 2019 20:52:15 +0000 (UTC) Subject: Re: [PATCH 1/6] tests/boot_linux_console: Add initrd test for the CubieBoard To: =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= , qemu-devel@nongnu.org Cc: Beniamino Galvani , Niek Linnenbank , Willian Rampazzo , Peter Maydell , qemu-arm@nongnu.org, Cleber Rosa References: <20191230110953.25496-1-f4bug@amsat.org> <20191230110953.25496-2-f4bug@amsat.org> From: Wainer dos Santos Moschetta Message-ID: <31147d48-2f31-9fce-b8a4-1a270f114a45@redhat.com> Date: Mon, 30 Dec 2019 18:52:13 -0200 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101 Thunderbird/60.4.0 MIME-Version: 1.0 In-Reply-To: <20191230110953.25496-2-f4bug@amsat.org> Content-Language: en-US X-Scanned-By: MIMEDefang 2.79 on 10.5.11.11 X-MC-Unique: NjHmOij-PCKjhle4dijyog-1 X-Mimecast-Spam-Score: 0 Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 207.211.31.120 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 30 Dec 2019 20:52:33 -0000 On 12/30/19 9:09 AM, Philippe Mathieu-Daud=C3=A9 wrote: > This test boots a Linux kernel on a CubieBoard and verify > the serial output is working. > > The kernel image and DeviceTree blob are built by the Armbian > project (based on Debian): > https://docs.armbian.com/Developer-Guide_Build-Preparation/ > > The cpio image used comes from the linux-build-test project: > https://github.com/groeck/linux-build-test > > If ARM is a target being built, "make check-acceptance" will > automatically include this test by the use of the "arch:arm" tags. > > Alternatively, this test can be run using: > > $ avocado --show=3Dconsole run -t machine:cubieboard tests/acceptance/= boot_linux_console.py > console: Uncompressing Linux... done, booting the kernel. > console: Booting Linux on physical CPU 0x0 > console: Linux version 4.20.7-sunxi (root@armbian.com) (gcc version 7.= 2.1 20171011 (Linaro GCC 7.2-2017.11)) #5.75 SMP Fri Feb 8 09:02:10 CET 201= 9 > console: CPU: ARMv7 Processor [410fc080] revision 0 (ARMv7), cr=3D50c5= 387d > console: CPU: PIPT / VIPT nonaliasing data cache, VIPT nonaliasing ins= truction cache > console: OF: fdt: Machine model: Cubietech Cubieboard > [...] > console: Boot successful. > console: cat /proc/cpuinfo > console: / # cat /proc/cpuinfo > console: processor : 0 > console: model name : ARMv7 Processor rev 0 (v7l) > console: BogoMIPS : 832.51 > [...] > console: Hardware : Allwinner sun4i/sun5i Families > console: Revision : 0000 > console: Serial : 0000000000000000 > console: cat /proc/iomem > console: / # cat /proc/iomem > console: 01c00000-01c0002f : system-control@1c00000 > console: 01c02000-01c02fff : dma-controller@1c02000 > console: 01c05000-01c05fff : spi@1c05000 > console: 01c0b080-01c0b093 : mdio@1c0b080 > console: 01c0c000-01c0cfff : lcd-controller@1c0c000 > console: 01c0d000-01c0dfff : lcd-controller@1c0d000 > console: 01c0f000-01c0ffff : mmc@1c0f000 > [...] > PASS (54.35 s) > > Signed-off-by: Philippe Mathieu-Daud=C3=A9 > --- > tests/acceptance/boot_linux_console.py | 41 ++++++++++++++++++++++++++ > 1 file changed, 41 insertions(+) > > diff --git a/tests/acceptance/boot_linux_console.py b/tests/acceptance/bo= ot_linux_console.py > index 9c6aa2040a..4643f60e37 100644 > --- a/tests/acceptance/boot_linux_console.py > +++ b/tests/acceptance/boot_linux_console.py > @@ -400,6 +400,47 @@ class BootLinuxConsole(Test): > self.wait_for_console_pattern('Boot successful.') > # TODO user command, for now the uart is stuck > =20 > + def test_arm_cubieboard_initrd(self): Unless you have two tests, one with and without initrd (not the case=20 though) the suffix '_initrd' is useless. So I suggest to remove it. > + """ > + :avocado: tags=3Darch:arm > + :avocado: tags=3Dmachine:cubieboard > + """ > + deb_url =3D ('https://apt.armbian.com/pool/main/l/' > + 'linux-4.20.7-sunxi/linux-image-dev-sunxi_5.75_armhf.= deb') > + deb_hash =3D '1334c29c44d984ffa05ed10de8c3361f33d78315' > + deb_path =3D self.fetch_asset(deb_url, asset_hash=3Ddeb_hash) > + kernel_path =3D self.extract_from_deb(deb_path, > + '/boot/vmlinuz-4.20.7-sunxi'= ) > + dtb_path =3D '/usr/lib/linux-image-dev-sunxi/sun4i-a10-cubieboar= d.dtb' > + dtb_path =3D self.extract_from_deb(deb_path, dtb_path) > + initrd_url =3D ('https://github.com/groeck/linux-build-test/raw/= ' > + '2eb0a73b5d5a28df3170c546ddaaa9757e1e0848/rootfs/' > + 'arm/rootfs-armv5.cpio.gz') > + initrd_hash =3D '2b50f1873e113523967806f4da2afe385462ff9b' > + initrd_path_gz =3D self.fetch_asset(initrd_url, asset_hash=3Dini= trd_hash) > + initrd_path =3D os.path.join(self.workdir, 'rootfs.cpio') > + archive.gzip_uncompress(initrd_path_gz, initrd_path) > + > + self.vm.set_console() > + kernel_command_line =3D (self.KERNEL_COMMON_COMMAND_LINE + > + 'console=3DttyS0,115200 ' > + 'usbcore.nousb ' > + 'panic=3D-1 noreboot') > + self.vm.add_args('-kernel', kernel_path, > + '-dtb', dtb_path, > + '-initrd', initrd_path, > + '-append', kernel_command_line, > + '-no-reboot') > + self.vm.launch() > + self.wait_for_console_pattern('Boot successful.') > + > + exec_command_and_wait_for_pattern(self, 'cat /proc/cpuinfo', > + 'Allwinner sun4i/sun5i') > + exec_command_and_wait_for_pattern(self, 'cat /proc/iomem', > + 'system-control@1c00000'= ) > + exec_command_and_wait_for_pattern(self, 'reboot', > + 'reboot: Restarting syst= em') I ran this test case with success, so: Tested-by: Wainer dos Santos Moschetta With the comment regarding the _initrd suffix: Reviewed-by: Wainer dos Santos Moschetta > + > def test_s390x_s390_ccw_virtio(self): > """ > :avocado: tags=3Darch:s390x From MAILER-DAEMON Tue Dec 31 06:41:43 2019 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1imFuA-0006uM-Tb for mharc-qemu-arm@gnu.org; Tue, 31 Dec 2019 06:41:42 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:52686) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1imFu7-0006uE-M0 for qemu-arm@nongnu.org; Tue, 31 Dec 2019 06:41:41 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1imFu4-0005Vm-HZ for qemu-arm@nongnu.org; Tue, 31 Dec 2019 06:41:38 -0500 Received: from us-smtp-2.mimecast.com ([207.211.31.81]:44223 helo=us-smtp-delivery-1.mimecast.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1imFu4-0005Pn-3t for qemu-arm@nongnu.org; Tue, 31 Dec 2019 06:41:36 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1577792495; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=1RvyXRVN8X1RUdnsihcJMYirHo2YGnLEsA3LPXm12ho=; b=FgupTo+gJdk4dw7jx2uVZSxmCoN9cCAKznoBdFKVpbhlL+DspzaoKANbh5ZFoPfTAj/AXc BxA03GO8wxgRTT0QC2rWwgjEPe7rMbyA3c05TDyK7Mz6QwbqCJ1oqM/IYbtcMbyVO/uBXw hkUY+tAN7PErq9+xPE7vxPTXS7oh0yA= Received: from mail-wr1-f70.google.com (mail-wr1-f70.google.com [209.85.221.70]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-351-bvJ_f1ZUN_u4JGgdkQI9gQ-1; Tue, 31 Dec 2019 06:41:32 -0500 Received: by mail-wr1-f70.google.com with SMTP id 90so18910073wrq.6 for ; Tue, 31 Dec 2019 03:41:32 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:subject:to:cc:references:from:message-id:date :user-agent:mime-version:in-reply-to:content-language :content-transfer-encoding; bh=OB0+M/UOk5U9g3VP04qpBqnq+CMtYavMNojlSVI60Cc=; b=CBzCQ/1pWNs9JyuKjOfDBWr3v6yZkzpXs8c6ctfU/CXoBbz8jtVS6G02UTgw8O9um0 or+I1AHwZ8eBmkVFRmQorgwSANa2xz8evMTyroW2P6+EcRtft5tidB+JVlqKW1Pd9/Bn J4sV0/RXqZsYvkl5WIDkNKWVFIrR/dt4aZUbs0fIqRK26c+caIXv36GSx7FE1nGZVvSE 1OzsDvywvUENwLRc9uo11qmxuIFQNafUxUKlFai92URKxJxTakRd1OEpQ0ZGA3Vz7Pzc Uzp+SBbtOM8QAwqduNgBmZwaZG5SYGdRtVYDPr9YHv3uYuYzQQvGFSBxNGBocgRpVIfb eb3w== X-Gm-Message-State: APjAAAUYnk99vxN+UGroiHQqCLZ0D/RpmN9njWA5b9lVt+G2/P0wNfR8 SOj8YvFjOc3M2fg+NUKgfl0zdFWxeZjnHuXDjW00OG7No2wEYws5Pc+mzaKTLrjzKHq3GFsF/Vg iUEALl0Yx5twH X-Received: by 2002:a7b:c416:: with SMTP id k22mr3700412wmi.10.1577792490788; Tue, 31 Dec 2019 03:41:30 -0800 (PST) X-Google-Smtp-Source: APXvYqyQQYviqtgrsy6h6Q2nfVIxcS4S8Yk8iib6dfzl65BBEotmjG64G5UJrxGgbIFPIx3ko2J+YA== X-Received: by 2002:a7b:c416:: with SMTP id k22mr3700389wmi.10.1577792490458; Tue, 31 Dec 2019 03:41:30 -0800 (PST) Received: from [192.168.1.25] (abayonne-654-1-140-248.w86-222.abo.wanadoo.fr. [86.222.91.248]) by smtp.gmail.com with ESMTPSA id g21sm52605250wrb.48.2019.12.31.03.41.29 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 31 Dec 2019 03:41:29 -0800 (PST) Subject: Re: [PATCH 1/6] tests/boot_linux_console: Add initrd test for the CubieBoard To: Wainer dos Santos Moschetta , =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= , qemu-devel@nongnu.org Cc: Peter Maydell , Beniamino Galvani , Niek Linnenbank , qemu-arm@nongnu.org, Willian Rampazzo , Cleber Rosa References: <20191230110953.25496-1-f4bug@amsat.org> <20191230110953.25496-2-f4bug@amsat.org> <31147d48-2f31-9fce-b8a4-1a270f114a45@redhat.com> From: =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= Message-ID: Date: Tue, 31 Dec 2019 12:41:28 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.2.2 MIME-Version: 1.0 In-Reply-To: <31147d48-2f31-9fce-b8a4-1a270f114a45@redhat.com> Content-Language: en-US X-MC-Unique: bvJ_f1ZUN_u4JGgdkQI9gQ-1 X-Mimecast-Spam-Score: 0 Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 207.211.31.81 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 31 Dec 2019 11:41:41 -0000 On 12/30/19 9:52 PM, Wainer dos Santos Moschetta wrote: > On 12/30/19 9:09 AM, Philippe Mathieu-Daud=C3=A9 wrote: >> This test boots a Linux kernel on a CubieBoard and verify >> the serial output is working. >> >> The kernel image and DeviceTree blob are built by the Armbian >> project (based on Debian): >> https://docs.armbian.com/Developer-Guide_Build-Preparation/ >> >> The cpio image used comes from the linux-build-test project: >> https://github.com/groeck/linux-build-test >> >> If ARM is a target being built, "make check-acceptance" will >> automatically include this test by the use of the "arch:arm" tags. >> >> Alternatively, this test can be run using: >> >> =C2=A0=C2=A0 $ avocado --show=3Dconsole run -t machine:cubieboard=20 >> tests/acceptance/boot_linux_console.py >> =C2=A0=C2=A0 console: Uncompressing Linux... done, booting the kernel. >> =C2=A0=C2=A0 console: Booting Linux on physical CPU 0x0 >> =C2=A0=C2=A0 console: Linux version 4.20.7-sunxi (root@armbian.com) (gcc= version=20 >> 7.2.1 20171011 (Linaro GCC 7.2-2017.11)) #5.75 SMP Fri Feb 8 09:02:10=20 >> CET 2019 >> =C2=A0=C2=A0 console: CPU: ARMv7 Processor [410fc080] revision 0 (ARMv7)= ,=20 >> cr=3D50c5387d >> =C2=A0=C2=A0 console: CPU: PIPT / VIPT nonaliasing data cache, VIPT nona= liasing=20 >> instruction cache >> =C2=A0=C2=A0 console: OF: fdt: Machine model: Cubietech Cubieboard >> =C2=A0=C2=A0 [...] >> =C2=A0=C2=A0 console: Boot successful. >> =C2=A0=C2=A0 console: cat /proc/cpuinfo >> =C2=A0=C2=A0 console: / # cat /proc/cpuinfo >> =C2=A0=C2=A0 console: processor=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 : 0 >> =C2=A0=C2=A0 console: model name=C2=A0=C2=A0=C2=A0=C2=A0 : ARMv7 Process= or rev 0 (v7l) >> =C2=A0=C2=A0 console: BogoMIPS=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 : 832= .51 >> =C2=A0=C2=A0 [...] >> =C2=A0=C2=A0 console: Hardware=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 : All= winner sun4i/sun5i Families >> =C2=A0=C2=A0 console: Revision=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 : 000= 0 >> =C2=A0=C2=A0 console: Serial=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0 : 0000000000000000 >> =C2=A0=C2=A0 console: cat /proc/iomem >> =C2=A0=C2=A0 console: / # cat /proc/iomem >> =C2=A0=C2=A0 console: 01c00000-01c0002f : system-control@1c00000 >> =C2=A0=C2=A0 console: 01c02000-01c02fff : dma-controller@1c02000 >> =C2=A0=C2=A0 console: 01c05000-01c05fff : spi@1c05000 >> =C2=A0=C2=A0 console: 01c0b080-01c0b093 : mdio@1c0b080 >> =C2=A0=C2=A0 console: 01c0c000-01c0cfff : lcd-controller@1c0c000 >> =C2=A0=C2=A0 console: 01c0d000-01c0dfff : lcd-controller@1c0d000 >> =C2=A0=C2=A0 console: 01c0f000-01c0ffff : mmc@1c0f000 >> =C2=A0=C2=A0 [...] >> =C2=A0=C2=A0 PASS (54.35 s) >> >> Signed-off-by: Philippe Mathieu-Daud=C3=A9 >> --- >> =C2=A0 tests/acceptance/boot_linux_console.py | 41 +++++++++++++++++++++= +++++ >> =C2=A0 1 file changed, 41 insertions(+) >> >> diff --git a/tests/acceptance/boot_linux_console.py=20 >> b/tests/acceptance/boot_linux_console.py >> index 9c6aa2040a..4643f60e37 100644 >> --- a/tests/acceptance/boot_linux_console.py >> +++ b/tests/acceptance/boot_linux_console.py >> @@ -400,6 +400,47 @@ class BootLinuxConsole(Test): >> =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 self.wait_for_con= sole_pattern('Boot successful.') >> =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 # TODO user comma= nd, for now the uart is stuck >> +=C2=A0=C2=A0=C2=A0 def test_arm_cubieboard_initrd(self): >=20 > Unless you have two tests, one with and without initrd (not the case=20 > though) the suffix '_initrd' is useless. So I suggest to remove it. The next patch adds a SD card test: https://www.mail-archive.com/qemu-devel@nongnu.org/msg667628.html If one developer has other tests in progress, but one done, I think it=20 might sense to add the full test name when the first patch is merged, so=20 next tests don't have to modify the first test name. >> +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 """ >> +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 :avocado: tags=3Darch:arm >> +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 :avocado: tags=3Dmachine:cub= ieboard >> +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 """ >> +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 deb_url =3D ('https://apt.ar= mbian.com/pool/main/l/' >> + =20 >> 'linux-4.20.7-sunxi/linux-image-dev-sunxi_5.75_armhf.deb') >> +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 deb_hash =3D '1334c29c44d984= ffa05ed10de8c3361f33d78315' >> +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 deb_path =3D self.fetch_asse= t(deb_url, asset_hash=3Ddeb_hash) >> +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 kernel_path =3D self.extract= _from_deb(deb_path, >> + =20 >> '/boot/vmlinuz-4.20.7-sunxi') >> +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 dtb_path =3D=20 >> '/usr/lib/linux-image-dev-sunxi/sun4i-a10-cubieboard.dtb' >> +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 dtb_path =3D self.extract_fr= om_deb(deb_path, dtb_path) >> +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 initrd_url =3D ('https://git= hub.com/groeck/linux-build-test/raw/' >> +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 '2eb0a73b5d5a28df= 3170c546ddaaa9757e1e0848/rootfs/' >> +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 'arm/rootfs-armv5= .cpio.gz') >> +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 initrd_hash =3D '2b50f1873e1= 13523967806f4da2afe385462ff9b' >> +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 initrd_path_gz =3D self.fetc= h_asset(initrd_url,=20 >> asset_hash=3Dinitrd_hash) >> +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 initrd_path =3D os.path.join= (self.workdir, 'rootfs.cpio') >> +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 archive.gzip_uncompress(init= rd_path_gz, initrd_path) >> + >> +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 self.vm.set_console() >> +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 kernel_command_line =3D (sel= f.KERNEL_COMMON_COMMAND_LINE + >> +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 'console=3DttyS0,115200 ' >> +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 'usbcore.nousb ' >> +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 'panic=3D-1 noreboot') >> +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 self.vm.add_args('-kernel', = kernel_path, >> +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= '-dtb', dtb_path, >> +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= '-initrd', initrd_path, >> +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= '-append', kernel_command_line, >> +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= '-no-reboot') >> +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 self.vm.launch() >> +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 self.wait_for_console_patter= n('Boot successful.') >> + >> +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 exec_command_and_wait_for_pa= ttern(self, 'cat /proc/cpuinfo', >> +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 'Allwinner = sun4i/sun5i') >> +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 exec_command_and_wait_for_pa= ttern(self, 'cat /proc/iomem', >> + =20 >> 'system-control@1c00000') >> +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 exec_command_and_wait_for_pa= ttern(self, 'reboot', >> +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 'reboot: Re= starting=20 >> system') >=20 >=20 > I ran this test case with success, so: >=20 > Tested-by: Wainer dos Santos Moschetta Thanks Wainer! >=20 > With the comment regarding the _initrd suffix: >=20 > Reviewed-by: Wainer dos Santos Moschetta >=20 >=20 >> + >> =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 def test_s390x_s390_ccw_virtio(self): >> =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 """ >> =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 :avocado: tags=3D= arch:s390x >=20 >=20